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XX-4B308-16

February 1979

618 pages

Original

22MB

Document:	VAX-11 System Reference Manual Rev5
Order Number:	XX-4B308-16
Revision:
Pages:	618
Original Filename:	http://bitsavers.org/pdf/dec/vax/archSpec/VAX-11_System_Reference_Manual_Rev5_Feb79.pdf

OCR Text

VAX - 11
SYSTEM REFERENCE MANUAL
19 £t~EB 1979

Revision 5

COpy

3't ,

DO NOT DUPLICATE
For additional oopies, contact:
Diane Secatore
TW/A08
+-------~---------------------------------+

Digital Equipment Corporation, Maynard, Massachusetts

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Revision 1 ,
Revision 3,
Revision 4,
Revision 5,

Sept, 1975
June, 1976
May, 1977
Feb, 1979

The information in this document is subject to change
without notice and should not be construed as a commitment
by Digital Equipment
Corporation.
Digital
Equipment
Corporation assumes no responsibility for any errors that
may appear in this document.
This document does not describe any program or product which
is currently available from Digital Equipment Corporation.
Nor does Digital Equipment Corporation commit to implement
th~s
standard in any program or product. Digital Equipment
Corporation makes no
commitment
that
this
document
accurately describes any product it might ever make.
Digital Equipment Corporation's software is furnished under
a license a~d may only be used or copied in accordance with
the terms of such license.
No responsibility is assumed for the use or reliability of
software on equipment that is not supplied by Digital or its
affiliated companies.
Copyright (c) 1976, 1977, 1979 by Digital Equipment Corporation

The following
Corporation:

are

trademarks

ASSIST-ll
DIBOL
KIlO
COMPUTER LABS DIGITAL
KL10
COMSYST
DNC
LAB-b
COMTEX
EDGRIN
LAB-K
DDT
EDUSYSTEM. /7' MASS BUS
---nEC
FLIP CHIP ! OMNIBUS
DECnet
. t.S ft'OCAL
..t\\i;\V OS/8
DECCOMM 11'" GLC-8
\' \ PDP
DECUS
'--y IDAC
PHA
DECsystem-l0 IDACS
PS/8
DECsystem-20 INDAC
QUlCKPOINT
DECtape
KAl0
RAD-o

Digital

Equipment

RSTS
RSX
RT-11
RTS-8
SABR
SBl
TRAX
TYPESET-8
TYPESET-10
TYPESET-11
UNIBUS
VA~

PREFACE
The VAX-11 is a family of upward-compatible computer systems. It is a
natural outgrowth of and is heavily compatible with the PDP-11 family.
We believe that these systems represent a significant depart~re from
traditional
methods of computer design.
VAX-11 represents the
culmination of years of analysis of the needs of software, and
compilers in particular.
For readers interested in just a summary of the family, please refer
to the VAX-11/780 Technical Summary. It contains a 30 page summary of
this manual which is suitable for marketing and sales use, but is not
sufficiently detailed for software or hardware implementation.
This manual explains the machine language programming and operation of
any member of the VAX-11 family, for both instructional and reference
purposes. Basically the manual defines in detail how the central
processor functions, exactly what its instructions do, how it handles
data, what its control and status information means, and what
programming techniques and procedures must.be employed to utilize it
effectively. The programming is given in machine language, in that it
uses only the basic instruction mnemonics and symbolic addressing
defined by the assembler. The treatment relies neith~r on any other
Digital software nor on any of the more sophisticated features of the
assembler. Moreover, the manual is completely self-contained
no
prior knowledge of the assembler is required.
The text of the manual is devoted almost entirely to functional
dvscription and programming.
Chapter 1 discusses the goals of the
system and the notational conventions used throughout the manual.
Chapter 2 defines the formats of the various forms of data and
instructions. Chapter 3 discusses the addressing modes used in
instructions. Chapter 4 gives the definition and detailed description
of all instructions generally available to users of the system.
Chapter 5 defines the memory management aspects of the system.
Chapter 6 discusses the interrupt and exception handling in the
system.
Chapter 7 covers process structure and context switching.
Chapter 8 defines those interactions between processor, memory, and
1/0 devices which are true of any member of the family. Chapter 9
defines the specifics of interacting with processor
registers.
Chapter 10 documents the PDP-l1 Compatibility Mode of operation.
Appendix A (not included in this release) contains the Glossary of all
terms used in VAX-1l.
Appendix B details the assembler notation
sufficiently for a full understanding of the examples in the manual.
Appendix C includes the software calling sequence standard. Appendix
D documents the condition handling facility. Appendix E details the

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
PR~FACE
Rev 5 -- 19-Feb-79
4

rules for subsetting instructions in various implementations of the
VAX-l1 family. Appendix F is a summary of the instructions, their
operands, and the encoding. It is suitable to be used to construct an
"instruction card".
Appendix G (not included in this release)
documents the notation used in the fermal instruction descriptions.
Appendix h includes examples of how to use the VAX-11 instruction set
to
build multi-precision integer arithmetic.
Appendix 1 is a
conversion guide for converting PDP-l1 machine language programs to
VAX-11.
Appendix J is the rules which the operating system must obey
to use the memory management system without introducing protection
holes. AppendixK gives programming examples.

In addition to being a manual for programmers, this manual is also the
architectural control document for all machines built in the VAX-1'
family. It delineates the permitted variations between processor
implementations.
These decisions were reached taking into account
tradeoffs
between
software
development
costs
and
hardware
manufacturing costs over a wide range of technologies.
In using the System Reference Manual as a reference, there is a
possible ambiguity because a single specification may occur several
times. Although every effort has been made to ensure that the
specifications are consistent, conflicting specification is possible.
In order to resolve any conflicts, the following precedence order is
established:
,.

Appendix F

Formal description in chapters 1-11 in that order

~nglish

Appenaices A-E and G-K in that order

description in chapters 1-1' in that order

Any errors, inconsistencies, or ambiguitities should be brought to the
attentien of:
Ted Taylor
TW/AOo

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

Page 1

VAX-ll System ~eference Manual -- Rev 5

Specification status:
Architectural Status:
File:

under ECQ control

SRPRR5.RNO

PDM I: not used
Date:

19-Feb-79

Superseded Specs:
Abstract:

SRM Rev 4

This document is revision 5 of the definition of the
Hardware Architecture for the VAX-l1 computer family. It
is composed on a
set
of individual
architectural
specifications (chapters) which are published a$ an entity
known as the System Reference Manual. Refer to the Preface
for a description of the manual as a ~hole or to the
abstracts of the indivioual specifications to understand
the purpose and content of each chapter.

Revision History:
Rev.#
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5

Description
Author
Original publication
VAXA
Internal, for review
VAXA
Result of implementor's review April T.F'.
ECQ's
VAXA
ECO's, G & H,interlocked queue Bhandarkar

Revised Date
Qct..,75
Mar-76
13.Jun-76
12 ...May-77
19-Feb-79

+---------------+
I dig ita I I
+---------------+
To:

VAX SRM Distribution

interoffice memorandum
Date:
From:
Dept:

12 February 7 9
~_
Dileep Bhandarkar~
VAX/PDP-11 Sys. Arch.

DTN:

247-2021

Loc/Mail Stop: TW/AOe
Subj:

VAX SRM

This package contains updated versions of Chapters 1, 2, 3,
4, and 6, Appendices C, E, and F, and a new Index and·
Contents.
The SRM now contains
specifications
for
instructions and features not available on machines currentlt
being shipped.
Please continue to treat the SRM as a Company
Confidential document.

CONTENTS

CHAPTER

INTRODUCTION
1• 1

1.2
1 .2. 1
1 .2.2
1.2.3
1 .2.4
1 .2.5
1.2.6

CHAPTER 2

INTRODUCTION
TERMINOLOGY AND CONVENTIONS •
Numbering . • . • • • . • •
UNPREDICTABLE And UNDEFINED •
Ranges And Extents
MBZ • • • • • • • • • • • • •

Reserved
Figure Drawing Conventions

• • 1-1
· . • . • . 1-2

• • 1-2
• 1-2
• • • • • 1-2
· . . . . .
. 1-3
· . . . . . 1-3

· • 1-3

BASIC ARCHITECTURE

ADDRESSING
• 2-1
DATA TYPES
· • • . . . 2-1
2.2.1
Byte
• . . . . . . . . . . .
. 2-1
2.2.2
Word
• • • • . 2-2
2.2.3
Longword • • • • • • • • • • • •
• • 2-2
2.2.4
Quadword
• 2-3
2.2.5
Octaword
. . ..
. . . . . . . . . 2-3
2.2.6
F'_floating
• • • • • •
. . . . . . . . . . . . 2-4
2.2.7
Double Floating (D_floating)
• • 2-4
2.2.8
G_floating
• • . .
• 2-5
H_floating
• • . • •
2.2.9
· • • . . 2-5
2.2.10
2-6
Variable Length Bit Field •
2.2.11
Character String •• • . •
• • • • • 2-7
2.2.12
Trailing Numeric String • • •
• • • • • • 2-t>
2.2.12.1
Leading Separate Numeric String
• • 2-10
2.2.13
Packed Decimal String
• • 2-12
2.3
PROCESSOR STATE • • • .
• • • • • • 2-14
2.4
PROCESSOR STATUS WORD .
• • • ••
2-16
2.4.1
C Bit
•••.
• • 2-16
2.4.2
V Bi t • .
• • • •
• 2-16
2.4.3
Z Bi t . .
• • • • • • 2-16
2.4.4
N Bit
• • 2-16
2.4.5
T Bit •
• • • • •
2-17
2.4.6
• • • • 2-17
IV Bit
2.4.7
FU Bit
· • • • • • 2-17
•. * • •
2.4.8
DV Bit
· . . . . . . . . . 2-17
• • • •
• 2-18
2.5
PERMANENT EXCEPTION ENABLES •
2.5.1
Divide By Zero
• • • •
• •• 2-18
• • • • •
. • 2-18
2.5.2
Floating Overflow • •
2.6
INSTRUCTION FORMAT
• • 2-19
2.7
SEPARATION OF PROCEDURE AND DATA
• 2-19
2.8
I/O STRUCTURE • • .
• • • •
• • 2-19
2.9
2-20
INTERRUPT STRUCTURE • . • • • . . •
2. 1

CHAPTER 3

INSTRUCTION F'ORMATS AND ADDRESSING MODES
.ru

Copyright(o) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COPY
VAX-11 System Reference Nanual
COMPANY CONFIDENTIAL
CONTENTS
3.1
3.2
3.3
3.4
3.4. 1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.5
3.5. 1
3.5.2
3.6
3.7
CHAPTER 4
4. 1
4. 1 • 1

4.1.2
4.1.3
4.2
4.3
4.3.1
4.3.2
4.3.3
4.4

4.5
4.6
4.7
4.8
4.9
4.9.1
4.9.2
4.10
4. 11
4. 12
4.12.1
4.12.2

4.12.3
4.12.4

4.12.5
4.12.6
4. 13
4. 13
HAPTER 5
5.1

OPCODE F'ORNATS
·
OPERAND SPECIFIERS . . . • • .
· .
NOTATION • • . • •
. • • •
GENERAL MODE ADDRESSING FORMATS .
Register Mode • . • •
Register Deferred Node
· . . . .
Autoincrement Mode
· . . . .
Autoincrement Deferred Mode
Autodecrement Mode . • • •
Displacement Mode ••
Displacement Deferred Hode
Literal Mode • • . •
Index Mode • • . • •
SUt-1lvlARY OF' GENERAL IlilODE ADDRESSING
General Register Addressing • . • • .
. • .
Program Counter Addressing (reg=15)
BRANCH MODE ADDRESSING FORMATS . . • •
OPERAND SPECIFIER CONVENTIONS • • • • •

Page 2

. . . • • 3-1
. . . . . 3-2

· 3-3
· 3-4
3-4
. . . . . 3-5
. . . . . 3-5
· 3-6
3-7

. • . 3-8
• 3-9

. . . . . 3-10

· 3-12
• • 3-14
• . • . . 3-14
· 3-15
· 3-16
· 3-17

INSTRUCTIONS
INSTRUCTION SET
· . . . . . . 4-1
Instruction Descriptions
4-1
Operand Specifier Notation
· . . . . . . . . . 4-3
Operation Description Notation
· 4-4
INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS •
. . . . . 4-7
FLOATING POINT INSTRUCTIONS •
. . • .
· 4-35
Introduction
• • . . . • 4-35
Overview Of The Instruction Set
· 4-37
Accuracy • • • . • • •
· . . . . . . 4-38
ADDRESS INSTRUCTIONS
· 4-65
VARIABLE LENGTH BIT FIELD INSTRUCTIONS
· 4-67
CONTROL INSTRUCTIONS
• • • •
· 4-74
PROCEDURE CALL INSTRUCTIONS • . • • . .
• 4-95
MISCELLANEOOS INSTRUCTIONS • • • • •
· 4-103
QUEUE INSTRUCTIONS
· 4-114
. • • . • • • • 4-114
Absolute Queues . • • • • • • • • • .
Self-relative Queues
· 4-123
CHARACTER STRING INSTRUCTIONS •
• • 4-139
CYCLIC REDUNDANCY CHECK INSTRUCTION •
· 4-162
DECIMAL STRING INSTRUCTIONS • • • • • • •
• • • • • . . 4-166
Decimal Overflow
• • • • • • 4-167
Zero Numbers
. • • 4-167
Reserved Operand Exception
• • • • • • • 4-167
UNPREDICTABLE Results • • • • •
. • • • •
• 4-167
Packed Decimal Operations • •
· • • .
• 4-168
Zero Length Decimal Strings
• • . • . . • 4-168
EDIT INSTRUCTION • . • •
· 4-195
OTHER VAX-11 INSTRUCTIONS •.
· 4-216
MEJvlORY MANAGEMENT
INTRODUCTION

. . . . . . . . . . . . . . . . . . . . . 5-1

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
CONTENTS

Page 3

5.2

VIRTUAL ADDRESS SPACE
• • • • •
• • • • • • • • 5-2
Process Space • •
. • • • • • • •
• • 5-2
5.2.2
System Space
• • • • • • • • • •
•• 5-2
5.2.3
Page Protection
• • • • • • • • • • • •
• • 5-3
5.2.4
Virtual Address •
• . • •
• • 5-3
5.2.5
Virtual Address Space Layout
. • • • • 5-3
ACCESS CONTROL
• • • • . • • • • • • • • 5-5
5.3
5.3. 1
Mode
• . • • • • • • •
• • • • • • • • • • • 5-5
5.3.2
Protection Code
••••
• • 5-5
5.3.3
Length Violation • • •.
•••••
• • • • • • • 5-7
5.3.4
• 5-7
Access Control Violation Fault
5.4
ADDRESS TRANSLATION • • • • • • •
5-7
5.4.1
Page Table Entry (PTE) • • • •
••••
5-8
5.4.2
System Space Ad~ress Translation
. • • • • 5-9
Process Space Address Translation
• • • • • • • 5-11
5.4.3
5.4.4
PO Space
• • • • • •
• • • .
• 5-12
5.4.5
P1 Space • • . • • • • • • • • • • • • • • • •
5-14
MEMORY MANAGEMENT CONTROL . • • • • • • •
• • 5-16
5.5
5.5.1
Memory ~anagement Enable . • • • •
5-16
5.5.2
Translation Buffer • • • • • • • •
• • 5-17
5.6
FAULTS AND PARAMETERS •
• • • •
• • • • • 5-17
5.7
PRIVILEGED SERVICES AND ARGUMENT VALIDATION.
• 5-19
5.7.1
Changing Modes • • • • • • • . • • • • • • • • • • • • • 5-19
5.7.2
Validating Address Arguments (PROBE Instructions)
5-19
5.7.3
Notes On The PROBE Instructions • • • ••
• • • • • • 5-22
5.8
ISSUES • • • • • • • • . • • • • • • • • • .
• • 5-22
5.8. 1
Physically Contiguous System Page Table •
• 5-22
5.8.1.1
Size Of SPT • • • • • • • • • • • • • •
• • 5-22
5.8.2
• • • • • • 5-23
Access Across A Page Boundary • • •
5.8.3
Sharing • • • • • • • • • • . . • .
• • • • • 5-23
5.8.3.1
Shared Section In Process Space • •
••••
• • 5-23
5.8.3.2
Shared Sections In System Space •
• • • • 5-24
5.8.4
Protection Check Before Valid Check •
• • • • • • 5-25
5.2. 1

CHAPTER 6
6.1
6. 1 • 1
6. 1.2
6.1.3
6.1.4
6.2
6.3

EXCEPTIONS AND INTERRUPTS

INTRODUCTION
• • • 6-1
. . . . . . 6... 2
Processor Interrupt Priority Levels (IPL)
Interrupts • • • • • • • •
• • 6-2
Exceptions • • • • • • • •
• • 6-3
Contrast Between Exceptions And Interrupts
• • • 6-3
PROCESSOR STATUS
6-5
INTERRUPTS • • • . • •
• 6-8
6.3. 1
Urgent Interrupts - •
• • ••
••• •
• • 6-9
6.3.2
Device Interrupts - • • • • •
. • • • • • 6-9
Software Generated Interrupts - • • • • • •
• • 6-10
6.3.3
6.3.3.1
Software Interrupt Summary Register •
• • 6-10
Software Interrupt Request Register. • • . • • •.
6-10
6.3.3.2
6.3.4
Interrupt Priority Level Register.
• • • • • • • 6-11
6.3.5
Interrupt Example • • • • . • • • •
6-12
6.4
EXCEPTIONS • • • • • ••
••• • • • •
• • 6-13
6.4.1
Arithmetic Traps/Faults •
• • 6-14
6.4.1.1
Integer Overflow' Trap :0 •
• • • • • • • • 6-14
6.4.1.2
Integer Divide By Zero Trap
• • • • 6-15

Copyright(c) 1979 Digital Equipment Corp. ,Maynard,fvlass.
DO NOT COpy
VAX-11 System Reference N.a.nual
COMPANY CONFIDENTIAL
CONTENTS

Page 4

6.4.1.3
Floating Overflow Trap
• • • •
• 6-15
6.4.1.4
Divide By Zero Trap • • • •
• • • •
6-15
6.4.1.5
F'loating Underflow Trap • • • • • . • • • • •
• • 6-15
6.4.1.6
• • 6-15
Decimal String Overflow Trap
6.4.1.1
Subscript Range Trap • • ••
.•••
• 6-16
6.4.1.8
Floating Overflow F'ault • • •
• 6-16
6.4.1.9
Divide By Zero Floating Fault
•••.
• 6-16
6.4.1.10
Floating Underflow F'ault
• • • •
• 6-16
6.4.2
Memory ~~nagement Exceptions
• • • • • 6-17
6.4.2.1
• • • • • • • • 6-11
Access Control Violation Fault
6.4.2.2
Translation Not Valid Fault. • •
• 6-11
6.4.3
Exceptions Detected During Operand Reference
• 6-18
6.4.3.1
• • • • • • • • • 6-18
Reserved Addressing Mode Fault
6.4.3.2
••
•• 6-18
Reserved Operand Exception ••• • •
6.4.4
Exceptions Occurring As The Consequence Of An Instruction 6-20
6.4.4.1
• . • • . • • • • 6-20
Opcode Reserved To DIGITAL Fault
6.4.4.2
• 6-20
Opcode Reserved To Customers (and CSS) Fault ••
6.4.4.3
Compatibility Mode Exception
•• 6-21
6.4.4.4
Breakpoint F'aul t • • • • .
• • 6-21
6.4.5
Tracing • • • • • • • • • • •
• • • • • 6-22
6.4.5.1
Trace Instruction Summary
6-24
6.4.5.2
Using Trace • • • • • • • • • • •
• • 6-25
6.4.6
Serious System Failures • • •
• • 6-26
6.4.6.1
Kernel Stack Not Valid Abort
• • • • • • • • • 6-26
6.4.6.2
Interrupt Stack Not Valid Halt
• 6-26
6.4.6.3
Machine Check Exception • • • • •
• • • • • 6-26
6.5
SYSTEM CONTROL BLOCK (SCB) • • • •
• 6-27
6.5. 1
System Control Block Base (SCBB)
• • 6-27
6.5.2
Vectors • • • • • •
. • • • •
• • • . • • 6-27
6.6
STACKS • • • ••
• • • • . • • ••
• • • • • • • 6-32
6.6. 1
Stack Residency •
• • 6-32
6.6.2
Stack Alignment • • • • • •
• • • •
• • 6-33
6.6.3
Stack Status Bi ts
• • • •
••••
• 6-33
6.6.4
• • • • • • 6-33
Accessing Stack Registers •
6.7
SERIALIZATION OF NOTIFICATION OF MULTIPLE EVENTS • • • • • 6-35
6.8
INITIATE EXCEPTION OR INTERRUPT •
• 6-37
6.9
RELATED INSTRUCTIONS : • • • . •
6-40
6.10
PROCESSOR STATE TRANSITION TABLE
• • 6-44
CHAPTER 1
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
1.4
7.5
1.6
:;HAPTER 8

PROCESS STRUCTURE
PROCESS DEFINITION • • • • • • • • •
• • • • • 7-1
PROCESS CONTEXT • . • • • • • • • • •
• • • • • • • 7-2
Process Control Block Base (PCBB) • •
· . . . . . . 7-2
Process Control Block (PCB) • •
•• • • • • • • • • • 7-2
Process Privileged Registers ••• •
· . . . . 7-6
ASYNCHRONOUS SYSTEM TRAPS (AST) •
• • • 7-7
PROCESS STRUCTURE INTERRUPTS
7-8
PROCESS STRUCTURE INSTRUCTIONS
· . . . . 7-8
USAGE EXAMPLE • • • • • • • • • • • • • • •
•
••
e
•
7-13
SYSTEM ARCHITECTURAL IMPLICATIONS

Copyright(c) 1979 Digital Equipment Corp.,I"laynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CO~FIDENTIAL
CONTENTS
8. 1

8.2
8.3
8.4
8.5
8.6
8.6. 1

8.6.2
ChAPTER 9

Page 5

DATA SHARING AND SYNCHRONIZATION
• • 8-1
CACHE . • • • •
8-2
RESTARTABILITY
• 8-3
INTERRUPTS
• • • .. • 8-4
. . . . .
. . . . . . 8-4
ERRORS • • • •
. . . .
. . . . . . 8-4
I/O STRUCTURE • •
• • • • • •
• 8-5
Introduction
• • • •
. . ..
. . 8-5
Constraints On I/O Registers
PRIVILEGED REGISTERS AND CONSOLE

INTRODUCTION • . • • • • •
. . . . . . . . . . . . . 9-1
PROCESSOR REGISTER SPACE • • . •
• • • • • 9-1
Per-process Registers And Context Switching
• .. 9-2
Stack Pointer Images
. . . • .
9-2
The MTPR And Ml"PR Instructions
• • 9-4
SYSTEM IDENTIFICATION REGISTER (SID)
9.3
• 9-B
9.4
CONSOLE TERMINAL REGISTERS • • • . • •
• • 9-8
9.4. 1
VAX-11/7BO Console Register Implementation
9-11
9.4.1.1
Status Byte Definition
• • • • •
• 9-12
CLOCK REGISTERS • • . • • • • • ...
•• • .
9.5
• 9-13
9.5. 1
Time-of-Year Clock (optional)
• 9-13
. • . • • . 9-14
9.5.2
Interval Clock . • • . • • • •
9.6
VAX-11/780 ACCELERATOR • • . •
· • 9-16
9.7
VAX-11/780 MICRO CONTROL STORE • • • • .
• . . . . . 9-18
9.8
CO~SOLE FUNCTIONS • • • .
9-19
9.8. 1
Operator Interaction
. • • • • • 9-1 9
9.8.2
Control Functions • ~ .. •
9-20
9.8.2.1
Halts • • •
• .••
9-20
9.8.2.2
Continue
•• 9-20
9.8.2.3
Initialize
• 9-21
9.8.2.4
. . . . . . . . . . . 9-21
Start • . • •
9.8.3
Maintenance Functions •
• 9-21
9.8.3.1
Examine And Deposit
· . .- • • 9-21
9-21
9.8.3.2
Single Instruction
• • • • • • • • 9~22
9.8.4
Minimum Console • .
. .. . . . . . . . . .. 9.. 22
SYSTElV1 BOOTSTRAPPING
9.9
9.10
SYSTEN RESTART
• 9-24
9. 1

9.2
9.2. 1
9.2.2
9.2.3

CHAPTER 10
10. 1
10.1.1
10.1.2
10.1.3
10.1.4

PDP-11 COMPATIBILITY MODE

COMPATIBILITY HODE USER ENVIRONMENT . 1 0 - 2
General Registers And Address Hodes
10-2
The Stack • • • • • • •
•••.
• 10-2
Processor Status Word • • • •
• • • • •• • • • 10-2
Instructions • • . • • • • .
. • • •
10-3
10.2
ENTERING AND LEAVING COMPATIBILITY MODE •
•• • • • • • 10-4
10.2.1
General Register Usage • • • • • • • • • • . • • ••
10-5
COMPATIBILITY MODE MEMORY MANAGEMENT
. . • • • • . • • 10-5
10.3
10.4
COMPATIBILITY MODE EXCEPTIONS AND INTERRUPTS • • • • • • • 10-9
10.4.1
Reserved Instr.uction Trap • •
• • 10-9
10.4.2
BPT Instruction •
• • • •
• • • • • 10-9
10.4.3
lOT Instruction • • • • •
• • • • • • • • 10-9

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
])0 NOT COpy
VAX-11 System Reference Manual
CONPANY CONFIDENTIAL
CONTENTS
10.4.4
10.4.5
10.4.6
10.4.7
10.5
10.6
10.7
10.8
10.9
10.10
APPENDIX B

EMT Instruction • • • • • . • . .
TRAP Instruction
• • • •
Illegal Instructions
Odd Address Error • • • . • • . • . • • .
T BIT OPERATION IN CONPATIBILITY HODE
UNIMPLEMENTED PDP-11 TRAPS
COMPATIBILITY MODE I/O REFERENCES .
PROCESSOR REGISTERS •• .
PROGRAM SYNCHRONIZATION • • • •
~OTES • • • • • • • • •

• • 10-9
10-9
10-9
• • 10-10
· • 10-10
· 10-12
• • 10-13
· • 10-13
• • • . • 10-1 3
10-14

ASSEMBLER NOTATION

INTRODUCTION
• . . . • •
NOTATION FOR GENERAL HODE ADDRESSING
Register Mode • . . • • • • • . •
Register Deferred Mode
Autoincrement Mode
Autoincrement Deferred Mode • .
Autodecrement Mode • • • • •
Displacement Mode ••
Di splacement Deferred Node
Literal Mode • • • •
b.2.9
Absolute Addressing iVlode • • • •
B.2.10
General Addressing
B.2.11
Index Mode . • • •
B.3
GENERAL 1"lODE ADDRESSING SDi'1l'-1ARY
B.4
BRANCH DISPLACEMENT ADDRESSING
B.5
GENERIC OPCODE SELECTION
B. 5. 1
Branch Selection •• • . •
B.5.2
Number Of Operand Selection .
B. 1

B.2
B.2.1
B.2.2
B.2.3
B.2.4
B.2.5
B.2.6
B.2.7
B.2.8

APPENDIX C

Page 6

• • • • • • • • B-1

• • • • • B-1
. • • • • •
• B-1

• B-2
• B-2
• b-2
• B-2

• B-2
B-2
• • B-3

• B-3
B-3
• • B-3
· • • • B-3
• • 0-6
• • • • • B-6

· . . • 6-6
• • B-6

PROCEDURE CALLING STANDARD

INTRODUCTION
• C-1
C.2
GOALS AND NON-GOALS •
• C-2
C.3
:JEFINITIONS • • • •
• • C-3
C.4
CALLING SEQUENCE
· • • • • C-4
C.5
ARGUMENT LISTS
• • • • . C-4
C. 5. 1
Argument List Format
. • • •
• • • • • C-4
C.5.2
Argument Lists And Higher-level Languages .
• C-5
C.5.2.1
Order Of Actual Argument Evaluation • • • •
• C-5
C.5.2.2
Language Extensions For Argument Transmission .
• • C-6
c.6
FUNCTION VALUE RETURN •
• • C-7
C. '"{
REGISTER USAGE
• C-7
C.B
STACK USAGE • • • • •
· C-8
C.9
ARGUMENT DATA TYPES .
. . . . . . C-9
C.10
ARGUMENT DESCRIPTORS
• C-11
C.10.1
Descriptor Prototype • • • • . . • • • • •
C-11
C.10.2
Scalar, String Descriptor (DSC$K_CLASS_S) • • • • • • • • C-12
C.10.3
Dynamic String Descriptor (DSC$K_CLASS_D)
C-12
C.10.4
Varying String Descriptor (DSC$K_CLASS_V)
• C-13
C.10.5
Array Descriptor (DSC$K_CLASS_A) • • • •
• C-14
C. 1

Copyright(c) 1979 Digital Equipment Corp. ,Haynard,Mass.
DO NOT COpy
VAX-11 System Reference lI.tanual
COMPANY CONFIDENTIAL
Page 7

CONTENTS

C.10.6
C.10.7
C.10.8
C.10.9
C.10.10
C.l0.11
APPENDIX D

Procedure Descriptor (DSC$K_CLASS_P) • • . • • •
• C-16
Procedure Incarnation Descriptor (DSC$K_CLASS_PI) •• • • C-16
Label Descriptor (DSC$K_CLASS_J) • • • • • • • •
• C-17
Label Incarnation Descriptor (DSC$K_CLASS_JI) ••
• C-17
• • c-18
Decimal Scalar String Descriptor (DSC$K_CLASS_SD)
Reserved Descriptors •• • • • • • • • • • • • •
• C-18
CONDITION HANDLING FACILITY

D. 1

TERMINOLOGY • • • • •

D.2
D.3
D.4
D.5
D.6
D.7
D. 7. 1
D.7.2
D.8
D.9
D. 10

GOALS • • • • • • • • • • • •

D.11

APPENDIX E
E. 1

E.2
E.3
E.4
E.4.1
E.4.2
E.4.3
E.5
E.5.1
E.5.2
E.5.3
APPENDIX F'
14'. 1

F.2
14'.3
F.4
APPENDIX H
H. 1

H.2

B.3
H.4
H.5

. • • • •
•• • •

D-1
• D-2

RETURNING A CONDITION VALUE • •
• • D-3
ESTABLISH A CONDITION HANDLER • • • • •
D-4
REVERT HANDLER • • • • . • • • • • • • • • • • • • • . • • D-5
ENABLING/DISABLING CONDITIONS •
D-5
SIGNAL A CONDITION
• • • •
• D-6
Signal •• • • •
• • • • •
• • D-6
Handler • . . • •
• • • •
• • • • • D-9
OPTIONS OF HANDLER • • • •
• • ••
•• ••
D-10
REQUEST TO UNWIND • • • • • .
• • • • •
• • D-12
MULTIPLE ACTIVE SIGNALS •
• • D-13
IMPLICATIONS FOR COMPILERS
• • • • • D-14
ARCHITECTURAL SUBSETTING
GOALS • • • • • • . • •
• • E-1
• • • • • • li;-2
DEFINITIONS • • • • . . • • • • •
KERNEL INSTRUCTION SET
• • E-2
GUIDELINES FOR SOFTWARE IMPLEMENTORS
• • • • • E-3
Diagnostic Software • • • • • • • •
· • E-3
Operating System Kernel • • • • • •
• E-3
System Software And Compiled Code
· • E-3
. . . . .
. . E-4
GUIDELINES TO HARDWARE IMPLEMENTORS
.
.
.
.
.
.
.
.
.
. E-4
First VAX-11 Machine • • • • • .
. . . .
. . E-4
Machines After The First • • • •
Later Additions To The Architecture •
• • E-4
INSTRUCTION SET AND OPCODE ASSIGNMENTS
INSTRUCTION OPERAND FORMATS • •
OPERAND SPECIFIER NOTATION • • • •
OPCODE ASSIGNMENTS • • • • • • • • • .
INSTRUCTIONS USABLE TO REFERENCE I/O SPACE

. . . • . . F-1
• • F'-9

• • • • F-12
• • F-15

HULTIPRECISION ARITHMETIC
OVERVIEW • • _ • •
ADDM2 ADD,SUM ••
ADDM3 ADD,AUG,SUM ••
SUBM2 SUB,DIF • • • .
SUBM3 SUB,MIN,DIF •

• • H-1
• H-1
• H-2
H-2
• • B-2

~ONTENTS

H.6

EMULM MULR,MULD,PROD

..•

APPENDIX I

PDP-ll TO VAX-ll CONVERSION GUIDE

APPENDIX J

ADDRESS VALIDATION RULES

APPENDIX K

PROGRAMMING EXAMPLES

K. 1

K.2
K.3
K.4
K.5

Page 8

. . . . . . . . . . . . . H-3

PURPOSE . • • . • • • • • • • •
SORT ALGORITHM • • . • • • • • • • •
SIN FUNCTION • . • • . . • • •
FIXED FORMAT FLOATING OUTPUT
COBOL OUTPUT EDITING • • • •

• • • • • . • • • K-1
• • K-l

K-4
• • K-5
. . . . . . K-6

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

VAX-11 Introduction - Rev 5

Specification Status:

Fully approved

Architectural Status:

under ECO control

File:

Page 1

SR1R5.RNO

PDM I: not used
Date:

28-0ct-18

Superseded Specs:
Author:

Typist:

Betty Call

Strecker

Reviewer(s):

Abstract:

Rev 4

P. Conklin, D. Cutler, D. Hustvedt, J. Leonard, P. Lipman,
D. Rodgers, S. Rothman, B. Stewart, B. Strecker

Chapter 1 gives the goals which guided the design of the
VAX-11 architecture.
It then defines the terminology which
is key to understanding the remainder of the System Reference
Ma·nual.

Revision History:
Rev.1
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5

Description
Distributed
EeOs 1-11
Eeos 12-18 plus April Meeting
Editorial

Author
Strecker
Strecker
Strecker
Strecker
Bhandarkar

Revised Date
25-Sep-15
1-Mar-76
10-Jun-76
28-Feb-71
28-0ct-78

Introduction
Change History

28-0ct-78 -- Rev 5

Rev 4 to Rev 5:
1.

UNDEFINED must not hang

MBZ checks mandatory for non-kernel mode fields

MBZ checks optional for kernel mode fields

Rev 3 to Rev 4:
Rev 2 to Rev 3:
1.

Remove 1000:1 goal and multiprocessors

Change UNDEFINED result to UNPREDICTABLE

Define RESERVED

Rev 1 to Rev 2

Define MaZ

[End of SR1R5.RNO]

Page 1-990

Copyright(c) 1979 Digital Equipment Corp. ,Maynard ,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL

CHAPTER 1
INTRODUCTION

28-0ct-78 -- Rev 5

1.1

INTRODUCTION

VAX-ll represents a significant extension of the
PDP-11
family
architecture.
It shares with the PDP-l1 byte addressing, similar I/O
and interrupt structures, and identical data formats.
Although the
instruotion set is not strictly compatible with the PDP-11, it is
related, and can be mastered easily by a PDP-11 programmer.
Likewise
the similarity enables straightforward manual conversion of existing
PDP-11 programs to VAX-ll. Existing user mode PDP-ll programs which do
not need the extended features of VAX-ll can run unchanged in the PDP-l1
compatibility mode provided in VAX-11.
As compared to the PDP-l1, VAX-11 offers a greatly extended virtual
address
space,
additional instructions and data types, and new
addressing modes. Also provided is a sophisticated memory management
and protection mechanism, and hardware assisted process scheduling and
synchronization.
A number of specific goals guided the VAX-11 design:
1.

Maximal compatibility with the PDP-11 consistent with
a
significant extension of the virtual address space, and a
significant functional enhancement.

High bit efficiency. This is achieved by a wide range of data
types and new addressing ,modes.
PDP-11 programs naively
translated to VAX-l1 should not grow significantly in size;
while programs redesigned to exploit VAX-11 should get smaller
despite the extended virtual address space.

A systematic, elegant instruction set with orthogonality of
operators, data types, and addressing modes. This enables the
instruction set to be exploited easily, particularly by high
level language processors.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Introduction
28-0ct-78 -- Rev 5
Page 1-2
INTRODUCTION

Extensibility. The instruction set ,is designed so that new
data types and operators can be included efficiently in a
manner consistent with the currently defined operators and data
types.

Range. The architecture should be suitable over the entire
range of PDP-11 computer system implementations currently sold
by Digital Equipment Corporation.

The VAX-11 System Reference Manual describes the architecture of VAX-11
and applies to all implementations of VAX-11 systems.

1.2

TERMINOLOGY AND CONVENTIONS

A general glossary of VAX-11 terminology appears in Appendix
However, several important terms and conventions are outlined here.

1.2.1

Numbering

All numbers unless otherwise indicated are decimal.
Where there is
ambiguity, numbers other than decimal are indicated with the base in
English following the number in parentheses (e.g., FF (hex».

1.2.2

UNPREDICTABLE And UNDEFINED

Results specified as UNPREDICTABLE may vary from moment to moment,
implementation to implementation, and instruction to instruction within
implementations. Software can never depend on results specified as
UNPREDICTABLE.
Operations specified as UNDEFINED may vary from moment
to moment, implementation to implementation, and
instruction
to
instruction within implementations.
The operation may vary in effect
from nothing to stopping system operation.
UNDEFINED operations must
not cause the processor to hang i.e. reach an unhalted state from which
there is no transition to a normal state in which the machine executes
instructions.
Note the distinction between result and operation.
Non-privileged software can not invoke UNDEFINED operations.

1.2.3

Ranges And Extents

Ranges are specified in English and are inclusive (e.g., a range of
integers 0 through 4 includes the integers 0, 1, 2, 3, and 4.) Extents
are specified by a pair of numbers separated by a colon and are
inclusive (i.e. bits 7:3 specifies an extent of bits including bits 7,
6 , 5 , 4 , and 3).

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Introduction
28-0ct-78 -- Rev 5
Page 1-3
TERMINOLOGY AND CONVENTIONS
1.2.4 MBZ
Fields specified as MBZ (Must Be Zero) should never be filled by
software with a non-zero value. If the processor encounters a non-zero
value in a field specified as MBZ, a reserved operand fault or abort
occurs (see Chapter 6, Exceptions and Interrupts) if that field is
accessible to non-privileged software. MBZ fields that are accessible
only to privileged software (kernel mode) may not be checked for
non-zero value by some or all VAX-11 implementations.
Non-zero values
in MBZ fields accessible only to privileged software may produce
UNDEFINED operation.

1.2.5

Reserved

Unassigned values of fields are reserved for future use. In many cases,
some values are indicated as reserved to CSS/customers. Only these
values should be used for non-standard applications.
The values
indicated as reserved to DEC and all MaZ fields are to be used only to
extend the standard architecture in the future.

1..2.6

Figure Drawing Conventions

Figures which depict registers or memory follow the convention
increasing addresses run right to left aad top to bottom.
\A note on the manual format: At certain pOints
in the manual comments on why certain decisions
were made, unresolved issues, etc., are included
between a pair of back slants.\
[End of Chapter 1]

that

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

Page 1

VAX-11 Basic Architecture -- Rev 5

SpeCification Status:
Architectural Status:
File:

under ECO control

SR2R5.RNO

PDM I: not used
Date:

31-Jan-19

Superseded Specs:

Rev 4

Author:

Strecker

Typist:

Call

Reviewer(s):

Abstract:

P. Conklin, D. Cutler, D. Hustvedt, J. Leonard, P. Lipman,
D. Rodgers, S. Rothman, B. Stewart, B. Strecker

Chapter 2 specifies the formats of each of the data types
supported by the VAX-11 architecture. It also defines the
processor state which includes the general registers and the
processor status word. It briefly describes the instruction
formats, interrupts and the I/O structure.

Revision History:
Rev ,
Rev 1
Rev 2
Rev 3

Rev 4
Rev 5

Description
Distributed
ECOs 1-11
ECOs 12-18 and April Meeting
ECOs
Extended range floating point

Author
Strecker
Strecker
Strecker
Strecker
Bhandarkar

Revised Date
25-Sep-15
9-Mar-76
3-Jun-76
5-Apr-77
31-Jan-19

Basic Architecture
Change History

Page 2-990

31-Jan-19 -- Rev 5

ReV' I', to Rev 5
1.

Rename floating and double to F_floating and D_floating

Add G_floating data type

Add H_floating data type

Add FF bit to PSW

ECO to Overpunch alternate character set

Rev 3 to Rev 4:
1.

Replace zoned with packed (decimal data ECO).

Change CF to FP (CF ECO).

Add definitions of overpunch
alternate forms of overpunch.

and

zoned

formats.

Include

Rev 2 to Rev 3:
1.

Remove AL field, pOinter.

Numeric from left separate to right zoned.

Remove DZ,FV.

IV and DV conditionally enabled by Call instructions.

Remove Round from C.

All overflowing instructions trap.

Remove LP.

Expand to 32 interrupt levels.

Zero length permitted for num"eric and pocked decimal strings.

10.

Zero length field causes 0 memory references.

Rev 1 to Rev 2:
1•

Clarify AL field, add pOinter.

Add Quad.

Clarify floating range.

Don't wrap field.

Basic Architecture
Change History

[End

31-Jan-79 -- Rev 5

Define nibble.

Combine ND,FD,ID into DZ.

Remove TBR.

C gets Round bit.

Registers look like memory.

10.

All instructions can do I/O.

of SR2R5.RNO]

Page 2-991

CHAPTER 2
BASIC ARCHITECTURE

31-Jan-79 -- Rev 5

2. 1 ADDRESSING
The basic addressable unit in VAX-11 is the 8-bit byte.
Virtual
addresses are 32 bits long: hence the virtual address space is 2**32
(approximately 4.3 billion) bytes. Virtual addresses as seen by the
program are translated into physical memory addresses by the memory
management mechanism described in Chapter 5.

2.2

DATA TYPES

2.2.1

Byte

A byte is 8 contiguous bits starting on an addressable
The bits are numbered from the right 0 through 7:
7

byte

boundary.

+---------------+ :A
+---------------+
A byte is specified by its address A. When interpreted arithmetically,
a byte is a twos complement integer with bits of increasing significance
gOing 0 through 6 and bit 7 the sign bit. The value of the integer is
in
the range -128 through 127.
For the purposes of addition,
subtraction, and comparison, VAX-l1 instructions also provide direct
support for the interpretation of a byte as an unsigned integer with
bits of increasing significance going 0 through 7.
The value of the
unsigned integer is in the range 0 through 255.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
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Basic Architecture
31-Jan-79 -- Rev 5
Page 2-2
DATA TYPES
2.2.2

Word

A word is 2 contiguous bytes starting on an arbitrary
The bits are numbered from the right 0 through 15:
1

byte

boundary.

+-------------------------------+ :A
I

+----~--------------------------+
A word is specified by its address A, the address of the byte containing
bit O.
When interpreted arithmetically, a word is a twos complement
integer with bits of increasing significance going 0 through 14 and bit
15 the sign bit.
The value of the integer is in the range -32,768
through 32,767.
For the purposes of addition,
subtraction
and
comparison, VAX-l1 instructions also provide direct support for the
interpretation of a word as an unsigned integer with bits of increasing
significance gOing 0 through 15. The value of the unsigned integer is
in the range 0 through 65,535.

2.2.3

Longword

A longword is 4 contiguous bytes starting on an arbitrary byte boundary.
The bits are numbered from the right 0 through 31:
3
1

+---------------------------------------------------------------+ :A
+---------------------------------------------------------------+
A longword is specified by its address A, the address of the byte
containing bit O. When interpreted arithmetically, a longword is a twos
complement integer with bits of increasing significance going 0 through
30 and bit 31 the sign bit. The value of the integer is in the range
-2,147,483,648 through 2,147,483,647. For the purposes of addition,
subtraction, and comparison, VAX-11 instructions also provide direct
support for the interpretation of a longword as an unsigned integer with
bits of increasing significance going 0 through 31. The value of the
unsigned integer is in the range 0 through 4,294,967,295.
Note that the longword format is different from the longword format
defined by the PDP-11 FP-11.
In that format, bits of increasing
significance go from 16 through 31 and 0 through 14. Bit 15 is the sign
bit.
Most DEC software and in particular PDP-11 FORTRAN and COBOL use
the VAX-11 longword format.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Basic Architecture
31-Jan-79 -- Rev 5
Page 2-3
DATA TYPES
2.2.4

Quadword

A quadword is 8 contiguous bytes starting on an arbitrary byte boundary.
The bits are numbered from the right 0 through 63:
3

+---------------------------------------------------------------+ :A
+---------------------------------------------------------------+
:
:A+4
+---------------------------------------------------------------+
6
3
3

A quadword is specified by its address A, the address of the byte
containing bit 0.' When interpreted arithmetically, a quadword is a twos
complement integer with bits of increasing significance going 0 through
62 and bit 63 the sign bit. The value of the integer is in the range
-2**63 to 2**63-1.
The quadword data type is not fully supported by
VAX-11 instructions.

2.2.5

Octaword

A octaword is 16 contiguous bytes starting on an arbitrary
boundary. The bits are numbered from the right 0 through 127:
3
1

byte

+---------------------------------------------------------------+
I
:A
+---------------------------------------------------------------+ :A+4
+---------------------------------------------------------------+ :A+8
+---------------------------------------------------------------+
I
:A+12
+---------------------------------------------------------------+
1
9
2

7
A octaword is specified by its address A, the address of the byte
containing bit O. When interpreted arithmetically, a octaword is a twos
complement integer with bits of increasing significance gOing 0 through
126 and bit 127 the sign bit. The value of the integer is in the range
-2**127 to 2**127-1. The octaword data type is not fully supported by
VAX-11 instructions.

Copyright(c) 1979 Digital Equipment Corp •• Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Basic Architecture
31-Jan-79 -- Rev 5
Page 2-4
DATA TYPES
2.2.6

F_floating

A F_floating datum is 4 contiguous bytes starting on an arbitrary
boundary. The bits are labelled from the right 0 through 31.

byte

1 1

o
5 4
7 6
+-+---------------+-------------+
lSI
exp
I fraction
I:A
+-+-----------------------------+
fraction
:A+2
+-------------------------------+
A F_floating datum is specified by its address A, the address of the
byte containing bit O. The form of a F_floating datum is sign magnitude
with bit 15 the sign bit, bits 14:7 an excess 128 binary exponent, and
bits 6:0 and 31:16 a normalized 24-bit fraction with the redundant most
significant fraction bit not represented. Within the fraction, bits of
increasing significance go from 16 through 31 and 0 through 6.
The
8-bit exponent field encodes the values 0 through 255. An exponent
value of 0 together with a sign bit of 0, is taken to indicate that the
F_floating datum has a value of O. Exponent values of 1 through 255
indicate true binary exponents of -127 through +127. An exponent value
of 0, together with a sign bit of 1, is taken as reserved. Floating
point instructions processing a reserved operand take a reserved operand
fault (See Chapter 4 and 6). The value of a F_floating datum is in the
approximate range .29*10**-38 through 1.7*10**38. The precision of a
F_floating datum is approximately one part in 2**23, i.e., typically 7
decimal digits.

2.2.7

Double Floating (D_floating)

A double floating or D_floating datum is 8 contiguous bytes starting on
an arbitrary byte boundary.
The bits are labelled from the right 0
through 63:
1 1

5 4

7 6

+-+---------------+-------------+
lSI
exp
I fraction
I:A
+-+---------------+-------------+
fraction
:A+2
+-------------------------------+
I
fraction
: :A+4
+-------------------------------+
I
fraction
I :A+6
+-~~---------------~~~-~-~~-----+

A D_floating datum is specified,by its address A, the 'address of the
byte containing bit o. The form of a D_floating datum is identical to a
floating datum except for an ·additional 32 low significance fraction
bits. Within the fraction, bits of increasing significance go 48

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DATA TYPES
through 63, 32 through 47, 16 through 31, and 0 through 6. The exponent
conventions, and approximate range of values is the same for D_floating
as F_floating. The precision of a D_floating datum is approximately one
part in 2**55, i.e., typically 16 decimal digits.

2.2.8

G_floating

A G_floating datum is 8 contiguous bytes starting on an

boundary.

arbitrary
The bits are labelled from the right 0 through 63:

byte

1 1

5 4
o
4 3
+-+---------------------+-------+
lSI
exp
I fract , :A
+-+---------------------+-------+
I
fraction
I :A+2
+-------------------------------+
fraction
:A+4
+-------------------------------+
fraction
:A+6
+-------------------------------+
A G_floating datum is specified by its address A, the address of the
byte containing bit O. The form of a G_floating datum is sign magnitude
with bit 15 the sign bit, bits 14:4 an excess 1024 binary exponent, and
bits 3:0 and 63:16 a normalized 53-bit fraction with the redundant most
significant fraction bit not represented. Within the fraction, bits of
increasing significance go 48 through 63, 32 through 47, 16 through 31,
and 0 through 3. The 11-bit exponent field encodes the values 0 through
2047. An exponent value of 0 together with a sign bit of 0, is taken to
indicate that the G_floating datum has a value of O. Exponent values of
1 through 2047 indicate true binary exponents of -1023 through +1023.
An exponent value of 0, together with a sign bit of 1, is taken as
reserved. Floating pOint instructions processing a reserved operand
take a reserved operand fault (See Chapter 4 and 6). The value of a
G_floating datum is in the approximate range .56*10**-308 through
.9*10**308.
The precision of a G_floating datum is approximately one
part in 2**52, i.e., typically 15 decimal digits.

A H_floating datum is 16 contiguous bytes starting on an arbitrary
boundary. The bits are labelled from the right 0 through 127:

byte

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DATA TYPES

1 1

5 4

+-+-----------------------------+
IS I
exponent
:A
+-+-----------------------------+
fraction
:A+2
+-------------------------------+
fraction
:A+4
+-------------------------------+
I
fraction
:A+6
+-------------------------------+
fraction
:A+8
+-------------------------------+
fraction
I :A+10
+-------------------------------+
I
fraction
I :A+12
+-------------------------------+
fraction
:A+14
+-------------------------------+
A H_floating datum is specified by its address A, the address of the
byte containing bit O. The form of a H_floating datum is sign magnitude
with bit 15 the sign bit, bits 14:0 an excess 16384 binary exponent, and
bits 127:16 a normalized 113-bit fraction with the redundant most
signif{cant fraction bit not represented. Within the fraction, bits of.
increasing significance go 112 through 127, 96 through 111, 80 through
95, 64 through 79,48 through 63, 32 through 47, and 16 through 31. The
15-bit exponent field encodes the values 0 through 32767.
An exponent
value of 0 together with a sign bit of 0, is taken to indicate that the
H_floating datum has a value of O. Exponent values of 1 through 32767
indicate true binary exponents of -16383 through +16383. An exponent
value of 0, together with a sign bit of 1, is taken as reserved.
Floating pOint instructions processing a reserved operand take a
reserved operand fault (See Chapter 4 and 6). The value of a H_floa~ing
datum is in the approximate range (84'10**-4932 through .59*10*·4932.
The precision of a H_floating datum is-''japproximately one part in 2·*112,
i.e., typically 33 decimal digits.
.5''14-9-''6'>74- 7~78' (Q1~8 fJ2'5"4' 227tfj t,"3").I(,,fi}(.\ J/S

\'i:rqo~ 2..s;%-

2.2.10

'i'?7'i

o~~·3"L ~1'S' '5£'6'7~ 4-SY3 ~

Variable Length Bit Field

A variable bit field is 0 to 32 contiguous bits located arbitrarily with
respect to byte boundaries.
A variable bit field is specified by 3
attributes: the address A of a byte, a bit position P which is the
starting location of the field with respect to bit 0 of the byte at A,
and a size S of the field.
The specification of a bit field is
indicated by the following where the field is the shaded area.

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DATA TYPES

o
P P-1
P+S P+S-1
+---------------+----------------------+------------------------+
://////////////////////1
:A
+---------------+----------------------+------------------------+
S-1
0
The position is in the range -2**31 through 2**31-1 and is conveniently
viewed as a signed 29-bit byte offset and a 3-bit bit-within-byte field:
3

3 2

+-------------------------------------------------------+-------+
byte offset
I bwb
+-------------------------------------------------------+-------+
The sign extended 29-bit byte offset is added to the address A and the
resulting address specifies the byte in which the field begins.
The
3-bit bit-within-byte field encodes the starting position (0 through 1)
of the field within that byte. The VAX-11 field instructions provide
direct support for the interpretation of a field as a signed or unsigned
integer. When interpreted as a signed integer, it is twos complement
with bits of increasing significance going 0 through S-2; bit S-1 is
the sign bit.
When interpreted as an unsigned integer, bits of
increasing significance go from 0 to S-1. A field of size 0 has a value
identically equal to O.
A variable bit field may be contained in 1 to 5 bytes.
From a memory
management point of view (Chapter 5) only the minimum number of bytes
necessary to contain the field is actually referenced.

2.2.11

Character String

A character string is a contiguous sequence of bytes in memory.
A
character string is specified by 2 attributes: the address A of the
first byte of the string, and the length L of the string in bytes. Thus
the format of a character string is:

+---------------+ :A
+---------------+

+---------------+ :A+L-1
+---------------+
7
0

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DATA TYPES

The address of a string specifies the first character of a string.
"XYZ" is represented:

Thus

+---------------+
"X"
I :A
+---------------+
"Y"
:A+1
+---------------+
HZ"
:A+2
+----------~----+

The length L of a string is in the range 0 through 65,535.

2.2.12

Trailing Numeric String

A trailing numeric string is a contiguous sequence of bytes in memory.
The string is specified by 2 attributes: the address A of the first
byte (most significant digit) of the string, and the length L of the
string in bytes.
All bytes of a trailing numeric string, except the least significant
digit byte, must contain an ASCII decimal digit character (0-9). The
representation for the high order digits is:
digit

decimal

0
1
2

48
49
50
51
52
53
54
55
56
51

4
5
6
7
8
9

hex

ASCII character

30
31
32

0
1

3
4
5
6
1
8
9

34
35
36
31
38
39

The highest addressed byte of a trailing numeric string represents an
encoding of both the least significant digit and the sign of the numeric
string. The VAX numeric string instructions support any encoding;
however there are 3 preferred encodings used by DEC software. These are
(1) unsigned numeric in which there is no sign and the least significant
digit contains an ASCII decimal digit charac,t'~r, (2) zoned numeric, and
(3) overpunched numeric. Because the overpunch format has been used by
compilers of many manufacturers over many years, and because various
card encodings ar-e used, several variations in overpunch format have
evolved.
Typically, these alternate forms are accepted on input; the
normal form is generated as the output for all operations.
The valid
representations of the digit and sign in each of the later two formats
is:

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DATA TYPES
I

Representation of Least Significant Digit and Sign
Zoned Numeric Format

Overpunch Format

digit

decimal

hex

ASCII
char

decimal

hex

48
49

123

{

1
2

65
66
61
68
69
10

A
B
C
D
E
F
G
H
I
}

1
2
3
4
5
6
1
8
9
-0

-1
-2

-3
-4
-5
-6
-7
-8
-9

50
51
52

53
54

55
56
57
112
113
114
115
116
111
118
119

120
121

32
33

34
35
36
37

4
5

6
1

71
12

39
10

p
q
r

71
12
13
14

15
76
71
18
19

125
74
75
76

t
u

11
18

42
43
44
45
46

48
49
1D
4A
4B

4C
4D
4E
4F
50
51
52

ASCII char
norm
alt.

J
K
L
M
N

o
P

Q
R

The length L of a trailing numeric string must be in the range a to '31
(0 to 31 digits). The value of a a length string is identically O.
The address A of the string specifies the byte of the string containing
the most significant digit.
Digits of decreasing significance are
assigned to increasing addresses. Thus "123" is represented:

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DATA TYPES

Zoned Format or Unsigned
7

Overpunch Format

4 3

+-------+-------+
I

A+1

+-------+-------+
3
:
3
I
+-------+-------+

A+2

o
4 3
1
+-------+-------+
I
1
I
3
+-------+-------+
2
3
+-------+-------+
I
I
4
I
I
3
+-------+-------+

A
A+1
A+2

and "-123" is represented
Zoned Format

4 3

Over punch Format

+-------+-------+
3
I
+-------+-------+
3

A+1

+-------+-------+
7

A+2

+-------+-------+

2.2.12.1

o
4 3
7
+-------+-------+
3
1
+-------+-------+
I

A+1

+-------+-------+
4
I
C
+-------+-------+

A+2

Leading Separate Numeric String -

A leading separate numeric string is a contiguous sequence of bytes in
memory. A leading separate numeric string is specified by 2 attributes:
the address A of the first byte (containing the sign character), and a
length L, which is the length of the string in digits and NOT the length
of the string in bytes. The number of bytes in a leading separate
numeric string is L+1.
The sign of a separate leading numeric string is stored
byte. Valid sign bytes are:
Sign

decimal

+
+

43
32
45

hex

in a

separate

ASCII character

2B
20
2D

The preferred representation for "+" is ASCII "+".
contain an ASCII digit character:

<blank>
All subsequent bytes

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DATA TYPES

digit

decimal

hex

0
1
2
3
4
5
6
1
8
9

48
49
50
51
52
53
54
55
56
51

30
31
32
33
34
35
36
31
38
39

ASCII character
0
1
2
3
4
5
6
7
8
9

The length L of a leading separate numeric string must be in the range 0
to 31 (0 to 31 digits). The value of a 0 length string is identically

The address A of the string specifies the byte of the string containing
the sign.
Digits of decreasing significance are assigned to bytes of
increasing addresses. Thus "+123" is:

o
1
4 3
+-------+-------+
I 2
I B

1-------+------1 3 I 1
J-------+------1
3
1
2
1-------+------3
3

A
A+1
A+2
A+3

+-------+-------+
and "-123" is:

o
1
4 3
+-------+-------+
I 2
I
D
I

1-------+-------1
3
1 1
:

A+l

1-------+-------1

I
3
1 3
I
+-------+-------+

A+2
A+3

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DATA TYPES
2.2.13

Packed Decimal String

A packed decimal string is a contiguous sequence of bytes in memory.
A
packed decimal string is specified by 2 attributes: the address A of
the first byte of the string and a length L which is the number of
digits in the string and NOT the length of the string in bytes. The
bytes of a packed decimal string are divided into 2 4-bit fields
(nibbles) which must contain decimal digits except the low nibble (bits
3:0) of the last (highest addressed) byte which must contain a sign.
The representation for the digits and sign is:
digit or sign

decimal

0
1
2
3
4
5
6
7
8
9
+

0
1
2
3
4
5
6
7
8
9

10, 12, 14 or 15
11 or 13

hex
0
1
2
3
4
5
6
7
8
9
A,C,E, or F
B, or D

The preferred sign representation is 12 for "+" and 13 for "_H.
The
length L is the number of digits in the packed decimal string (not
counting the sign) and must be in the range 0 through 31.
When the
number of digits is odd, the digits and the Sign fit in L/2 (integer
part only) + 1 bytes. When the number of digits is even, it is required
that an extra "0" digit appear in the high nibble (bits 7:4) of the
first byte of the string. Again the length in bytes of the string is
L/2 + 1.
The address A of the string specifies the byte of the string containing
the most significant digit in its high nibble. Digits of decreasing
significance are assigned to increasing byte addresses and from high
nibble to low nibble within a byte. Thus "+123" has length 3 and is
represented:

o
4 3
7
+-------+-------+
1
121
+-------+-------+
3
12
+-------+-------+

A+ 1

and "-12" has length 2 and is represented:

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DATA TYPES

4 3

+-------+-------+
I 0
I
1
:
+-------+-------+
:
2
:
13 :
+-------+-------+

A+ 1

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PROCESSOR STATE
2.3

PROCESSOR STATE

The processor state consists of that portion of a process's state which,
while the process is executing, is stored in processor registers rather
than memory. The processor state described here consists of that
accessible to non-privileged software.
Certain additional processor
state is described in Chapters 5, 6, and 7.
The non-privileged processor state includes 16 32-bit general purpose
registers denoted Rn where n is in the range 0 through 15 and a 16-bit
processor status word (PSW). Where there is ambiguity (e.g., n is an
arithmetic expression) the notation R[n] is also used to denote the
register. The general purpose registers are used for temporary storage,
accumulators,
index
registers,
and base registers.
A register
containing an address is termed a base register. A register containing
an address offset (in multiples of operand Size, see Chapter 3) is
termed an index register.
The bits of a register are numbered from the right 0 through 31:
3

+---------------------------------------------------------------+ :Rn
+---------------------------------------------------------------+
Certain of the registers are assigned
architecture:

special

meaning

the

VAX-11

R15 is the program counter (PC). PC contains
the next instruction byte of the program.

the

address

R14 is the stack pOinter (Sf). SP contains the address of the
top of the processor defined stack.

R13 is the current frame pointer (FP).
The VAX-11 procedure
call convention (see Appendix C) builds a data structure on the
stack called a stack frame. FP contains the address of the
base of this data structure.

R12 is the argument pOinter (AP). The VAX-11 procedure call
convention uses a data structure termed an argument list. AP
contains the address of the base of this data structure.

Note that these registers are all used as base registers.
The
assignment of special meaning to these registers does not generally
preclude their use for other purposes. However, as will be seen in
Chapter 3, PC cannot be used as an accumulator, temporary, or index
register.
When a datum of type byte, word, longword, or F_floating is stored in a
register, the bit numbering in the register corresponds to the numbering

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PROCESSOR STATE
in memory. Hence a byte is stored in register bits 7:0, a word in
register bits 15:0, and longword or F_floating, in register bits 31:0.
A byte or word written to a register writes only bit,s 7:0 and 15:0
respectively;
the other bits are unaffected. A byte or word read from
the other bits
a register reads only bits 7:0 and 15:0 respectively;
are ignored.
When a quadword, D_floating or G_floating datum is stored in a register
R(n], it is actually stored in 2 adjacent registers R(n] and R(n+1].
Because of restrictions on the specification of PC (see Chapter 3)
wraparound from PC to RO is UNPREDICTABLE. Bits 31:0 of the datum are
stored in bits 31:0 of register R[n] and bits 63:32 of the datum are
stored in bits 31:0 of register R[n+1).
When an octaword or a H_floating datum is stored in register R[n], it is
actually stored in adjacent registers R(n], R(n+l], R(n+2], and R(n+3].
Because of restrictions on the specification of PC (see Chapter 3)
wraparound from PC to RO is UNPREDICTABLE. Bits 31:0 of the datum are
stored in bits 31:0 of register R[n], bits 63:32 in bits 31:0 of
register R[n+1], bits 95:64 in bits 31:0 of register R[n+2], and bits
127:96 in bits 31:0 of register R(n+3].
With one restriction, a variable length bit field may be specified in
the registers:
the starting bit position P must be in the range 0
through 31. As for quadword and D_floating, a pair of registers R(n]
and R(n+l] is treated as a 64-bit register with bits 31:0 in register
R[n] and bit 63:32 in register R(n+1J.
None of the string data types stored in registers can be processed by
the
VAX-11 string instructions.
Thus there is no architectural
specification of the representation of strings in registers.

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PROCESSOR STATUS WORD
2.4

PROCESSOR STATUS WORD

The processor status word (PSW) contains the condition codes which give
information on the results produced by previous instructions and the
exception enables which control the processor action on certain
exception conditions (see Chapter 6). The format of the PSW is:
1

8 7 654 321 0

+---------------+-+-+-+-+-+-+-+-+
I
I
I

MBZ

!DIFIII ! : ! I 1
:V:U:VITIN:Z!VICI

+---------------+-+-+-+-+-+-+-+-+

The condition codes are UNPREDICTABLE when they are affected by
UNPREDICTABLE results.
The VAX-ll procedure call instructions (See
Chapter 4) conditionally set the IV and DV enables, clear the FU enable,
and leave the T enable unchanged at procedure entry.

2.4.1

C Bit

When set, the C (carry) condition code bit indicates the
last
instruction which affected C had a qarry out of the m()st significant bit
of the result or a borrow into the most Significant bit.
When C is
clear, there was no carry or borrow.

2.4.2

V Bit

When set, the V (overflow) condition code bit indicates that the last
instruction which affected V produced a result whose magnitude was too
large to be properly represented in the operand which received the
result or there was a conversion error. When V is clear, there was no
overflow or conversion error.

2.4.3

Z Bit

When set, the Z (zero) condition code indicates that the
last
instruction which affected Z produced a result which was O. When Z is
clear, the result was non-zero.

2.4.4

N Bit

When set" the N (negative) condition code bit indicates that the
instruction which affected N produced a result which was negative.
N is clear, the result was positive (or zero).

last
When

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PROCESSOR STATUS WORD
2.4.5

T Bit

When set, the T (trace) bit forces a trace trap at the end of each
instruction execution.
When clear, no trap occurs. See Chapter 6 for
additional information on the trace trap.

2.4.6

IV Bi t

When set, the IV (integer overflow) bit forces an integer overflow trap
after execution of an instruction which produced an integer result that
overflowed or had a conversion error. When IV is clear, no integer
overflow trap occurs. (However, the condition code V bit is still set.)

2.4.7

FU Bit

When set, the FU (floating underflow) bit forces a floating underflow·
exception if the result of a floating point instruction is too small in
magnitude to be represented in the result operand.
On the original
VAX-11/7'sO's (not implementing the revised floating pOint architecture),
a trap after the execution of the instruction that produced an
underf10wed result occurs. On all other VAX processors, a fault occurs.
When FU is clear, no trap or fault occurs.
\The floating point architecture was revised in January 1979 to take
faults instead of traps on floating exceptions for the original data
types (F_floating and D_floating) as well as the two new data types
(G_floating and H_floating). Modified versions of the VAX-11/780 with
the revised architecture might be built.\

2.4.8

DV Bit

When set, the DV (decimal overflow) bit forces a decimal overflow trap
after execution of an instruction which produced an overflowed decimal
(numeric string, or packed decimal) result or had a conversion error.
When DV is clear, no trap occurs. (However, the condition code V bit is
still set.)

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PERMANENT EXCEPTION ENABLES
2.5

PERMANENT EXCEPTION ENABLES

The processor action on certain exception conditions is not controlled
by bits in the PSW. Traps or faults always result from these exception
conditions.

2.5.1

Divide By Zero

A divide by zero trap is forced after the execution of integer, or
decimal division instruction which has a zero divisor. On the original
VAX-111180, a trap is also forced after the execution of a floating
division instruction which has a zero divisor.
On all other VAX
processors, a fault occurs on a floating division instruction which has
a zero divisor.

2.5.2

Floating Overflow

A floating overflow trap (original VAX-111180) or fault (all other VAX
processors)
is
forced after the execution of a floating point
instruction which produced a result too large to be represented in the
result operand.

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INSTRUCTION FORMAT
2.6

INSTRUCTION FORMAT

VAX-ll has a variable length instruction format.
An instruction
specifies an operation and 0 to 6 operands. An operation specifier is
termed an opcode. Depending on the instruction the opcode is 1 or 2
bytes long. An operand specifier indicates the addressing mode used to
access the operand and may be 1 or 2 bytes. An operand specifier may be
followed by a specifier extension, an address, or immediate data. The
format of an n operand instruction is:
opcode
operand specifier 1
specifier extension, address, or immediate data 1 (if needed)
operand specifier 2

operand specifier n
specifier extension, address, or immediate data n (if needed)
See Chapter 3 for a full description of addressing modes. See Chapter 4
for a definition of the instructions. See Appendix F for a summary of
all operands, instructions, and their binary assignments.

2.1

SEPARATION OF PROCEDURE AND DATA

The VAX-11 architecture encourages (and provides the mechanisms to
facilitate) separation of procedure (instructions) and writable data.
Procedures may not write data which is to be subsequently executed as an
instruction without an intervening REI instruction being executed (See
Chapter 6) or an intervening context switch occurring (See Chapter 1).
If no REI or context switch occurs between a procedure writing data as
instructions to be executed, and those instructions being executed, the
instructions executed are UNPREDICTABLE.

2.8

1/0 STRUCTURE

Generally, the VAX-l1 1/0 structure closely follows that of the PDP-l1.
An 1/0 device controller is defined by a set of registers. The
registers are assigned addresses in the physical address
space.
Commands are issued to 1/0 controllers by the processor writing these
registers; controllers return status by writing these registers and the
processor subsequently reading them. Since the registers have memory
addresses, ordinary instructions can read or write them; no special 1/0
instructions
are needed.
The normal memory management mechanism
controls access to device controller registers.

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Basic Architecture
31-Jan-79 -- Rev 5
Page 2-20
INTERRUPT STRUCTURE
2.9

INTERRUPT STRUCTURE

A VAX-11 processor provides a 32 level vectored
system. This is described in detail in Chapter 6.
[End of Chapter 2]

priority interrupt

Page 1

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

VAX-l1 Instruction Formats and Addressing Modes -- Rev 6

Specification Status:

Fully approved

Architectural Status:

under ECO control

File:

SR3R6.RNO

PDM II: not used
Date: 14-Jul-r"{8
Superseded Specs:
Author:

Typist:

Betty Call

Strecker

Reviewer(s):

Abstract:

Rev 5

R. Brender, P. Conklin, D. Cutler, R. Grove, D. Hustvedt,
M. Jack, J. Leonard, P. Lipman, D. Rodgers, S. Rothman,
B. St ewart, W'. St recker

Chapter 3 gives the fQrmats of opcodes
and
operand
specifiers.
It describes the types of operand specifiers.
It describes the behavior of each addressing mode in both
text and a formal notation. It lists a set of conventions
applied to operand specifier evaluation.

Revision History:
Rev.1
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5
Rev 6

Author
Description
Strecker
Distributed
Strecker
ECOs 1-11
Strecker
ECOs 12-18, April Meeting
Strecker
Address Mode Changes
Strecker
Editorial
128 bit floating data type ECO Bhandarkar

Revised Date
25-Sep-75
10-Mar-76
12-May-76
3-Jun-76
7-Feb-77
14-Jul-78

Instruction Formats and Addressing Modes
Change History

14-Jul-78 -- Rev 6

Page 3-990

Rev 5 to Rev 6:
1.

Add G_floating and H_floating

Add octaword

Rev 4 to Rev 5:
1.

Editorial change to Summary of Mode Addressing

Rev 3 to Rev 4:
1.

Change floating literals

Remove argument mode, local mode and post-index mode

Add byte, word, longword displacement deferred mode

Add autoincrement deferred mode

Write of immediate UNPREDICATBLE

PC index register gives reserved operand fault (future escape)

SP index register OK

Same register for base and index OK for modes other
autoincrement, autodecrement, and autoincrement deferred.

10.

Write to PC of operand
UNPREDICTABLE.

taking

registers

result

than
in

Rev 2 to Rev 3:
1.

Note that modify is not under memory interlock

Change pointer to longword, remove <27:0} and EAL

Change RtR+l to R[n+l]'Rn (typo).

Clarify what is UNPREDICTABLE

Modify and write of immediate is UNPREDICTABLE

Change hex modes to decimal;

Change R to LP in local mode (typo)

Clarify value of PC in displacement and branch displacement

add table

Instruction Formats and Addressing Modes
Change History

14-Jul-18 -- Rev 6 Page 3-991

Change address mode abort to address mode fault

Rev 1 to Rev 2:
1.

Remove R-R mode

Reduce local 6 bits to 5

Add (R)

Add E(Rx]

Rename base-indexed to post-indexed

Eliminate base displacement.
...

Add 28-bit address arithmetic

Make branches 8 bit and 16 bit displacements

-,.~~.-

[End of SR3R6.RNO]

.---

(record indexing)

CHAPTER 3
INSTRUCTION FORMATS AND ADDRESSING MODES

14-Jul-18 -- Rev 6

3.1

OPCODE FORMATS

An instruction is specified by the byte address A of its opcode:
1

+---------------+
opcode
:A
+---------------+
The opcode may extend over 2 bytes; the length depends on the contents
of the byte at address A. If, and only if, the value of the byte is Fe
(hex) through FF (hex) is the opcode 2 bytes long:
1

8 7

+---------------+---------------+
opcode
l
FC - FF
I:A
+---------------+---------------+

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Page 3-2
OPERAND SPECIFIERS
3.2

OPERAND SPECIFIERS

Each instruction takes a specific sequence of operand specifier types.
An operand specifier type conceptually has two components: the access
type and the data type.
The access types include:
1.

Read - the specified operand is read only.

Write - the specified operand is written only.

Modify - the specified operand is read, potentially modified,
and written. This is not done under a memory interlock.

Address - the address of the specified operand in the form of a
longword is the actual instruction operand. The specified
operand is not accessed directly although the instruction may
subsequently use the address to access that operand.
Branch - no operand is accessed.
is a branch displacement.

The operand specifier

itself

Types 1 - 4 are termed general mode addressing and are discussed in
Section 3.4.
Type 5 is termed branch mode addressing and is discussed
in Section 3.6.
The data types include:
1.

Byte

Word

Longword and F_floating which
mode considerations.

are

Quadword, and D_floating and
equivalent.

G_floating

Octaword and H_floating which are also similarly equivalent.

equivalent
which

for

addressing

are

similarly

For the address and branch access types which do not directly
operands, the data type indicates:

reference

Address - the operand size to be used in the
address
calculation in autoincrement, autodecrement, and index modes.

Branch - the size of the branch displacement.

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Page 3-3
NOTATION

3.3 NOTATION
To describe the addressing modes the following is used:
+

*<=
Rn or R[n]
PC or SP

- addition
- subtraction
- multiplication
- is replaced by
- is defined as
- concatenation
- the contents of register n
- the contents of register
, 15 or 14 respectively
NOTE

In the
formal
descriptions
of
the
addressing modes Rn or PC, for example,
always means the contents of register nor
register 15. When there is no ambiguity,
Rn or PC, for example, is often used in
text as the name of register n or register
15.
(x)

{ }
SEXT(x)
ZEXT(x)
OA

- the contents of a location in memory
whose address is x.
- arithmetic parentheses used
to indicate precedence
- x is sign extended to size
of operand needed
- x is zero extended to size
of operand needed
- operand address
- comment delimiter

Each general mode addressing description includes the definition of the
operand address, and the specified operand. For operand specifiers of
address access type, the operand address is the actual instruction
operand;
for
other access types the specified operand is the
instruction operand. The branch mode addressing description includes
the definition of the branch address.

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Page 3-4
GENERAL MODE ADDRESSING FORMATS
3.4
3.4.1

GENERAL MODE ADDRESSING FORMATS
Register Mode

The operand specifier format is:

o
4 3
7
+-------+-------+
I' 5
1 Rn I
+-------+-------+
No specifier extension follows.
In register mode addressing the operand is the contents of register n
(or register n+1 concatenated with register n for quadword, D_floating,
and certain field operands):
operand = Rn
or
R[n+l) 'Rn
or
R[n+3]'R[n+2]'R[n+1]'Rn

I if one register
! if two registers
! if four registers

Because registers do not have memory addresses, the operand address is
not defined, and register mode may not be used for operand specifiers of
address access type (except in the case of the base address for variable
bit field instructions, see Chapter 4). If it is, an illegal addressing
mode fault results (See Chapter 6). PC may not be used in register mode
addressing. If PC is read, the value read is UNPREDICTABLE. If PC is
written, the next instruction executed or the next operand specified is
UNPREDICTABLE. Likewise, SP may not be used in register mode addressing
for an operand which takes two adjacent registers. Again, if it is, the
results are UNPREDICTABLE in the same fashion.
If PC is used in
register mode for a write access type operand which takes 2 adjacent
registers, the contents of RO are UNPREDICTABLE. If R12, R13, SP, or PC
are used in register mode addressing for an operand which takes four
adjacent registers, the results are UNPREDICTABLE. If PC is used in
register mode for a write access type operand which requires 4 adjacent
registers, the contents of RO, .R1, and R2 are UNPREDICTABLE.
Likewise,
if R13 is used in register mode for a write access type operand which
takes 4 adjacent registers, the contents of RO are UNPREDICTABLE;
and,
if SP is used in register mode for a write access type operand which
takes 4 adjacent registers, the contents of RO and Rl are UNPREDICTABLE.
The assembler notation (See Appendix B) for register mode is Rn.

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GENERAL MODE ADDRESSING FORMATS
3.4.2

The operand specifier format is:

4 3

+-------+-------+
6
I
Rn
+-------+-------+
No specifier extension follows.
In register deferred mode addressing, the address of the operand is
contents of register n:

the

OA = Rn
operand = (OA)
PC may not be used in register deferred mode addressing. If it is, the
address of the operand (and whether the operand is written if it is of
modify or write access type) is UNPREDICTABLE.
The assembler notation (See Appendix B) for register
(Rn).

3.4.3

deferred

mode

Autoincrement Mode

The operand specifier format is:
7

4 3

+-------+-------+
8
Rn I
+-------+-------+
No specifier extension follows.
If Rn denotes
follows, and the mode is termed immediate mode.

PC,

immediate

data

In autoincrement mode addressing, the address of the operand is the
contents of register n. After the operand address is determined, the
size of the operand in bytes (1 for byte; 2 for word; 4 for longword
and F_floatingj 8 for quadword, D_floating and G_floating; and 16 for
octaword, and H_floating) is added to the contents of register n and the
contents of register n is replaced by the result:
OA = Rn
Rn <- Rn + size
operand = (OA)
Immediate mode may not be used for operands of modify or write access
type. If i~ediate mode is used for an operand of modify access type,

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GENERAL MODE ADDRESSING FORMATS
the value of the data read is UNPREDICTABLE. If immedi.ate mode is used
for an operand of modify or write access type, the address at which the
operand is written (and whether it is written) is UNPREDICTABLE.
The assembler notation (See Appendix B) for autoincrement mode is (Rn)+.
For immediate mode the notation is I"'#constant where constant is the
immediate data which follows.

3.4.4

Autoincrement Deferred Mode

The operand specifier format is:
7

4 3

+-------+-------+
9
I Rn I
+-------+-------+
No specifier extension follows. If Rn denotes PC,
follows, and the mode is termed absolute mode.

longword

address

In autoincrement deferred mode addressing, the address of the operand is
the contents of a longword whose address is the contents of register n.
After the operand address is determined, 4 (the size in bytes of a
longword address) is added to the contents of register n and the
contents of register n is replaced by the result~
OA = (Rn)
Rn <- Rn + 4
operand = (OA)
The assembler notation (See Appendix B) for autoincrement deferr"ed mode
is @(Rn)+. For absolute mode the notation is @Iaddress where address is
the longword which follows.

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GENERAL MODE ADDRESSING FORMATS
3.4.5

Autodecrement Mode

The operand specifier format is:

4 3

+-------+-------+
7 I Rn I
+-------+-------+
No specifier extension follows.
In autodecrement mode addressing, the size of the operand in bytes (1
for byte; 2 for word; 4 for longword and F_floating; 8 for quadword,
G_floating and D_floating; and 16 for octaword, and H_floating) is
subtracted from the contents of register n and the contents of register
n are replaced by the result. The updated contents of register n is the
address of the operand:
Rn

<- Rn - size

OA = Rn
operand = (OA)
PC may not be used in autodecrement mode. If it in, the address of the
operand (and whether the operand is written if it is of modify or write
access type) is UNPREDICTABLE and the next instruction executed or the
next operand specified is UNPREDICTABLE.
The assembler notation (See Appendix B) for autodecrement mode is -(Rn).

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GENERAL MODE ADDRESSING FORMATS
3.4.6

Displacement Mode

There are 3 operand specifier formats:
7
1•

4 3

+-------+-------+
, Rn
10
+-------+-------+
I

I
I

The specifier extension is a signed byte
byte displacement mode.
7

4 3

diSPlacement~

is termed

+-------+-------+
'12
I
Rn I
+-------+-------+
7

4 3

termed

+-------+-------+
14
l
Rn l
+-------+-------+

The specifier extension is a
longword displacement mode.

longword

displacement.

In displacement mode addressing, the displacement (after being sign
extended to 32 bits if it is byte or word) is added to the contents of
register n and the result is the operand address:
OA = Rn + SEXT(displ)
or
Rn + displ

c).

~:~~t

The specifier extension is a signed word displacement
word displacement mode.

(oll~

!if byte or word displacement
!if longword displacement

operand = (OA)
If Rn denotes PC, the updated contents of PC is used. The updated
contents of PC is the address of the first byte beyond the specifier
extension.
The assembler notation (See Appendix B) for byte, word, and long
displacement mode is BAD(Rn), WAD(Rn), and LAD(Rn) respectively where D
= displ.

Displacement Deferred Mode

There are 3 operand specifier formats:
7

4 3

+-------+-------+
I 11
I
Rn 1
+-------+-------+

The specifier extension is a signed byte displacement.
byte displacement deferred mode.
7

4 3

termed

This

termed

This

termed

+-------+-------+
: 13
,
Rn I
+-------+-------+

The specifier extension is a signed word displacement.
word displacement deferred mode.
7

This

4 3

+-------+-------+
I 15
I
Rn I
+-------+-------+

The specifier extension is a longword
longword displacement deferred mode.

displacement.

In displacement deferred mode addressing, the displacement (after being
sign extended to 32 bits if it is byte or word) is added to the contents
of register n and the result is the address of a longword whose contents
is the operand address:
OA

= (Rn + SEXT(displ»
or
(Rn + displ)

lif byte or word displacement
!if longword

displacement

operand = (OA)
If Rn denotes PC, the updated contents of the PC is used. The updated
contents of PC is the address of the first byte beyond the specifier
extension.
The assembler notation (See Appendix B) for byte, word,
displacement
deferred
mode
is @BAD(Rn), @WAD(Rn),
respectively where D = displ.

and
and

longword
@L"D(Rn)

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GENERAL MODE ADDRESSING FORMATS
3.4.8

Literal Mode

The operand specifier format is:

765

+---+-----------+
I 0 I
literal I
+---+-----------+
No specifier extension follows.
For operands of data type byte, word, longword, quadw~rd,
operand is the zero extension of the 6-bit literal field:

octaword

the

operand = ZEXT(literal)
Thus for these data types, literal mode may be used for values in the
range 0 through 63.
For operands of data type F_floating, D_floating, G_floating,
H_floating, the 6-bit literal field is composed of 2 3-bit fields:
532

and

+-----+-----+
I exp I fra I
+-----+-----+
where exp is exponent and fra is fraction. The exp and fra
used to form a F_floating or D_floating operand as follows:
1 1

5 4

7 6

4 3

+-+---------------+-----+-------+
101
128 + exp l fra I
0
+-+---------------+-------------+
o
:A+2
+-------------------------------+
:A+4
o
+-------------------------------+
:A+6
o
+-------------------------------+
where bits 63:32 are not present in a F_floating operand.

fields

are

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GENERAL MODE ADDRESSING FORMATS
The exp and fra fields are used to form a G_floating operand as follows:
1 1

4 3

5 4

1 0

+-+---------------------+-----+-+
:O~
1024 + exp
I fra :01
+-+---------------------+-----+-+

+-------------------------------+t

+-------------------------------+

:A+2
:A+4
:A+6

+-------------------------------+
The exp and fra fields are used to form a H_floating operand as follows:
1 1

5 4

+-+-----~-----------------------+

:0 I
16384 + exp
l
+-+---+-------------------------+
: fra I
0
:A+2
+-----+-------------------------+
:A+4
o

+-------------------------------+
o
:A+6
+------~------------------------+

:A+8

+-------------------------------+

+-~~--~~---------~~------~------+

+-------------------------------+

:A+10
:A+12
:A+14

+-------------------------------+
The range of values: available is given in the following table:

F -->

E
v
0
1
2
3
4
5
6
7

1/2
1
2
4

9/16
1 1/8
2 1/4
4 1/2

5/8
1 1/4
2 1/2

16
32
64

18
36

10
20
40
80

3/4
l' 1/2
3
6
12
24
48
96

13/16
1 5/8
3 1/4
6 1/2

11/16
1 3/8
2 3/4
5 1/2
11
22
44
88

7/8
1 3/4
3 1/2
7
14
28
56
112

15/16
1 7/8
3 3/4
7 1/2
15
30
60
120

26
52
104

Table 1. Floating Literals

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GENERAL MODE ADDRESSING FORMATS
Because there is no operand address, literal mode addressing may not be
used for operand specifiers of address access type. Literal mode
addressing may also not be used for operand specifiers of write or
modify access type. If literal mode is used for operand specifiers of
either address, modify, or write access type, an illegal addressing mode
fault results (see Chapter 6).
Literal mode addressing is a very efficient way of specifying integer
constants in the range 0 to 63 and the floating point constants given in
Table 1. Literal values outside the indicated range may be obtained by
autoincrement mode using PC (immediate mode).
The assembler notation (See Appendix B) for literal mode is SAlliteral.

3.4.9

Index Mode

The operand specifier format is:
1

8 7

4 3

+---------------+-------+-------+
I
4
:
Rx
+-------------------------------+
Bits 15:8 contain a second operand specifier (termed the base operand
specifier) for any of the addressing modes except register, literal or
index. The specification of register, literal, or index addressing .mode
results in an illegal addressing mode fault (see Chapter 6).
If the
base operand specifier requires a specifier extension, it immediately
foliows. The base operand specifier is subject to the same restrictions
as would apply if it were used alone. If the use of some particular
specifier is illegal (i.e., causes a fault or UNPREDICTABLE behavior)
under some Circumstances, then that specifier is similarly illegal as a
base operand specifier in index mode under the same circumstances.
The 'operand to be specified by index mode addressing is termed the
primary operand.
The base operand specifier is used normally to
determine an operand address. This address is termed the base operand
address (BOA).
The address of the primary operand specified is
determined by multiplying the contents of the index register x by the
size of the primary operand in bytes (1 for byte; 2 for word; 4 for
longword and F_floating; 8 for quadword, D_floating and G_floating;
and 16 for octaword, and H_floating), adding BOA, and taking the result:
OA = BOA + {size

*&x6

operand = (OA)
If the base operand specifier is for autoincrement or autodecrement mode
the increment Or decrement size is the size in bytes of the primary
operand.

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GENERAL MODE ADDRESSING FORMATS
Index mode addressing permits very general and efficient accessing of
arrays.
The base address of the array is determined by the operand
address caculation of the base operand specifier. The contents of the
index register is taken as a logical index into the array. The logical
index is converted into a real (byte) offset by multiplying the contents
of the index register by the size of the primary operand in bytes.
Certain restrictions are placed on the index register x. PC cannot be
used as an index register. If it is, a reserved addressing mode fault
occurs (see Chapter 6).
If the base operand specifier is for an
addressing
mode
which results
in
register modification (i.e.
autoincrement mode, autodecrement mode, or autoincrement deferred mode),
the same register'cannot be the index register. If it is, the primary
operand address is UNPREDICTABLE.
The names of the addressing modes resulting from index mode addressing
are formed by adding the suffix "indexed" to the addressing mode of the
base operand specifier. The following gives the names and assembler
notation (See Appendix B).
The index register is designated Rx to
distinguish it from the register Rn in the base operand specifier.
1.

autoincrement indexed - (Rn)+(Rx]
or immediate indexed - IAHconstant[Rx] which is recognized by
the assembler but is not generally useful. Note that the
operand address is independent of the value of constant.

autoincrement deferred indexed - @(Rn)+[Rx]
or absolute indexed - @laddress[Rx]

autodecrement indexed - -(Rn)[Rx]

byte,
word,
or
longword
displacement
BAD(Rn)[Rx],WAD(Rn)[Rx], or LAD(Rn)[Rx]

indexed

byte, word, or longword displacement deferred
@BAD(Rn)[Rx],@WAD(Rn)[Rx], or @LAD(Rn)[Rx]

indexed

SUMMARY OF GENERAL MODE ADDRESSING
General Register Addressing
0
7
4 3
+-------+-------+
: mode
reg
+-------+-------+

PC SP AP&
FP

Hex

Dec

Name

Assembler

r mwa v

0-3
4
5
6
1
8
9

0-3

y f f f f
y y y y y
y y y f y
y y y y y
y y y y y
y y y y y

f
u
u
u
p

y
uq
y
y
y

y
uo
y
y
y

y y y y y
y y y y y

p
p

y
y

10
11
12
13

y yy y y
y y y y y

p
p

y
y

C
D

y
y

14
15

y y y y y
y y y y y

S"tliteral
literal
i[Rx]
indexed
register
Rn
register deferred
(Rn)
autodecrement
-(Rn)
autoincrement
(Rn)+
autoincrement
deferred
@(Rn)+
B""D(Rn)
byte displacement
byte displacement
@B"'D(Rn)
deferred
W""D(Rn)
word displacement
word displacement
@W"D'(Rn)
deferred
longword displacement L""D(Rn)
longword displacement
@L""D(Rn)
deferred

y
y

Y
Y

y y y y y

!t
5

6
1
8
9

Indexable
f
f
f
Y

we
we
we
y

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SUMMARY OF GENERAL MODE ADDRESSING
3.5.2

Program Counter Addressing (reg=15)
432 1 0

+-------+-+-+-+-+
I
I mode
11 1 1 1 :
+-------+-+-+-+-+

Hex Dec

Name

Assembler

r mwa v

8
9
A
B

10
11

I "'#constant
@Iaddress
B. . address
@B"'address

y u u y y
y y y y y
y y y y y
y y y y y

y
y,
y
y

W"'address
@W"'address

y y y y y
y y y y y

y
y

14
15

immmediate
absolute
byte relative
byte relative
deferred
word relative
word relative
deferred
long word relative
long word relative
deferred

LAaddress
@L"address

y y y y y
y y y y y

y
y

PC SP

Indexable?

Key to 3.5.1 and 3.5.2
D - displacement
i-any indexable addressing mode
logically impossible
f - reserved addressing mode fault
p - Program Counter addressing
u - UNPREDICTABLE
uq - UNPREDICTABLE for quad, octa, D_floating, G_floating, and
H_floating (and f~eld if position + size greater than 32)
uo - UNPREDICTABLE for octa, and H format
ux - UNPREDICTABLE for index register same as base register
y - yes, always valid addressing mode
r - read access
m - modify access
, w - write access
a - address access
v - field access

BRANCH MODE ADDRESSING FORMATS

There are 2 operand specifier formats:

7
1.

+---------------+
displ
I
+---------------+

The operand specifier is a signed byte displacement.
1

+-------------------------------+
displ
+-------------------------------+

The operand specifier is a signed word displacement.
In branch displacement addressing, the byte or word displacement is sign
extended to 32 bits and added to the updated contents of PC. The
updated contents of PC is the address of the first byte beyond the
operand specifier. The result is the branch address A:
A = PC + SEXT(displ)
The assembler notation (See Appendix B) for byte and word branch
displacement addressing is A where A is the branch address.
Note that
the branch address and not the displacement is used.

3.1 OPERAND SPECIFIER CONVENTIONS
The following 3 steps are performed by each instruction:
1.

Each operand specifier in order
occurrence is treated as follows:

instruction

stream

If read access type: evaluate the operand address,
read the operand, and save it.

If write access type: evaluate the operand address
and save it.

If modify access type: evaluate the operand
address and save it; read the operand and save it.

If address access type:
save it.

evaluate the address and

If branch access type:

save the operand specifier.

Perform the operation indicated by the instruction.

Store the result(s) using the saved addresses in the order
indicated by the occurrence of operand specifiers in the
instruction stream.
NOTE
The string (character, zoned decimal, and
packed
decimal) instructions are an exception to 2. and 3.
in that partial results are
stored
before
the
instruction operation is completed. The variable bit
field instructions treat the position, size, and base
address operand specifiers as the specification of an
implied field operand specifier (see Appendix F).

The implications of these conventions are:
1.

Autoincrement and autodecrement operations occur as the operand
specifiers are processed, and subsequent operand specifiers use
the updated contents of registers modified by those operations.

Other than as indicated by 1, all input operands are read, and
all addresses of output operands computed before any results of
.the instruction are stored.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Instruction .Formats and Addressing Modes 14-Jul-78 -- Rev 6 Page 3-18
OPERAND SPECIFIER CONVENTIONS

An operand of modify access type is not read, modified, and
written as an indivisible operation; therefore, modify access
type operands cannot be used for synchronization.
(For
synchronization instructions, See Chapter 4.)

If an instruction references two operands of write or modify
access type at the same address, the first will be overwritten
by the second.

(End of Chapter 3]

Page 1

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title~

VAX-11 Integer and Logical Instructions -- Rev 5

Specification Status:

Fully approved

Architectural Status:

under ECO control

File:

SR4AR5.RNO

PDM II: not used
Date:

27-0ct-78

Superseded Specs:

Rev 4

Author:

Strecker

Typist:

Call

Reviewer(s):

Abstract:

R. Blair, R. Brender, D. Cane, K. Chapman, P. Conklin,
D. Cutler, R. Grove, T. Hastings, D. Hustvedt, J. Leonard,
P. Lipman, M. Payne, D. Rodgers; S. Rothman, B. Stewart,
B. Strecker

Chapter 4 describes the instructions generally used by all
software
across
all
implementations
of
the
VAX-11
architecture.
For convenience of review and
editting,
chapter 4 is separated into a number of specifications. This
specification contains the introductory material and the
integer arithmetic and logical instructions.

Revision History:
Rev /I
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5

Description
Initial distribution of SRM
EeOs 1-11
ECOs 12-18, April Meeting,
and May 25 Meeting
ECO's
Octaword ECO

Author
Strecker
Strecker
Strecker

Revised Date
25-Sep- 75
16-Mar-16
10-Jun-76

Strecker
Bhandarkar

12-Mar-77
27-0ct-78

Page 4-990

Instructions
27-0ct-78 -- Rev 5
Change History for Integer and Logical
Rev 4 to Rev 5:
1•

Add G_floating and H_floating

Add Octaword

Add MOVO and CLRO(same as CLRH)

Rev 3 to Rev 4:
1•

Typos.

Add ADAWI.

Rev 2 to Rev 3:
1.

Reserved operand aborts become faults

C <- 0 for ASHL, ASHQ

Change pointer to longword or address;

Add MINU function in ISP

Explicitly give SEXT or ZEXT in all cases needed

Add MOVQ, CLRQ

Add MOVZBW

Change eMP condition codes per ECO 17

Change results on overflow in EDIV

10.

Specified condition codes on all exceptions

11.

Split into separate specifications

make it 32 bits

Rev 1 to Rev 2:
(* indicated instruction operands or operations changed)
1.

Qualified operand names used in instruction description

BLISS relational operators used in instruction operation

Detailed operation descriptions included on all instructions

Condition code settings specified for all instructions

PUSH {B,W,F,D} eliminated

POP {B,W,L,F,D} eliminated

Instructions
27-0ct-78 -- Rev 5
Change History for Integer and Logical

Page 4-991

EXCH iB,W,L,F,D} eliminated

MOVM {B,W,L,F,D} eliminated

MOVN {B,W,L,F,D} changed to MNEG {B,W,L,F,D}

10.

MOVC {B,W,L} changed to MCOM {B,W,L}

11.

MOVZ {B,W} changed to MOVZ {BW,BL,WL}

12.

INS {B,W,L} eliminated

13.

ADWC {B,W} eliminated

14.

SBWC {B,W} eliminated

15.

C <- 0 for MUL {B,W,L}

16.

MULX changed to EMUL*

17.

DIVX changed to EDIV*

18.

MOD {B,W,L} eliminated

19.

BFC eliminated

20.

AND {B,W,L} eliminated

21.

ASH {B,W} eliminated, ASHQ added

22.

USH {B,W,L} eliminated

23.

ROT {B,W} eliminated

24.

ROTC {B,W,L} eliminated

25.

SXT {B,W,L} eliminated

26.

ADDC {F,D}, SUBC{F,D}, MULC{F,D}, DIVC{F,D} eliminated

27.

INC {F,D} eliminated

28.

DEC {F,D} eliminated

29.

MI {F,D} changed to EMOD {F,D}*

30.

CVTR{F,D} L added

31.

CHOP{F,D} added

32.

POLY{F,D} added

Instructions
27-0ct-78 -- Rev 5
Change History for Integer and Logical
33.

MOVA{B,W,L=F,D} changed to MOVP{B,W,L=F,D=Q}

34.

PUSHA{B,W,L=F,D} changed to PUSHP{B,W,L:F,D=Q}

35.

CMPA{B,W,L=F,D} changed to CMPA*

36.

ADTA, SBFA, DIFA added

37.

MOVZV changed to EXTZV*

38.

EXTV added

39.

CMPV changed to CMPZV*

40.

CMPV added

41.

AVP eliminated

42.

FFS/FFC added

43.

BPN, BME added

44.

BR changed BRB

45.

BRW added

46.

BSP eliminated

47.

BSB changed to BSBB

48.

BSBW Added

49.

BLS/BLC added

50.

CASE{B,W} {B,W,L} eliminated

51.

CASE{B,W,L} added*

52.

CALL eliminated

53.

CALLS/CALLG added

54.

RETURN changed to RET*

55.

AOB changed to AOBLE

56.

AOBLT added

57.

SCB eliminated, ACB* redefined

58.

SOB changed to SOBGE

Page 4-992

Instructions
27-0ct-78 -- Rev 5
Change History for Integer and Logical
59.

SOBGT added

60.

THRD eli.Jt ina ted

61.

JMP/JSB added

62.

LSTZ/LSTO eliminated

63.

MOVPSW added

64.

ASP eliminated

65.

HALT added

66.

MS{B,W,L,F,D,Q} added

67.

MPS{B,W,L=F,D=Q} added

68.

ISP added for string instrucions

69.

MOVLJS changed to MOVC3/MOVC5

70.

MOVRJS eliminated

71.

MOVTS changed to MOVTC

72.

CMPLRS changed to CMPC3/CMPC5

73.

CMPRLS eliminated

74.

SCNLRS changed to SCANC

75.

SCNRLS eliminated

76.

LOCLRS changed to LOCC

77.

LOCRLS eliminated

18.

EDITS changed to \TBS\

19.

MOVTUC proposal added

80.

SPANC proposal added

81.

MATCHC added

82.

MOVN changed to MOVS/MOVU

83.

6 operand ADDN added

84.

6 operand SUBH added

Page 4-993

Instructions
27-0ct-78 -- Rev 5
Change History for lnteger and Logical
85.

6 operand MULN added

86.

6 operand DIVN Added

Page 4-994

87.· MODN eliminated
88.

CVTLN changed to eVTLS/CVTLU

89.

CVTPN changed to CVTPS/CVTPU

90.

CVTSN/CVTUN changed to ASHS/ASHU

91.

Numeric suffix added
ADDB3)

[End of SR4AR5.RNO]

indicate

number

of operands

(e.g.

CHAPTER 4
INSTRUCTIONS

27-0ct-78 -- Rev 5

4.1

INSTRUCTION SET

This chapter describes the instructions generally used by all software
across
all
implementations of the VAX-11 architecture.
Certain
instructions which are specific to specialized portions of the VAX-11
architecture
(e.g., memory management, interrupts and exceptions,
process dispatching, and processor registers) and are generally used by
privileged software are described in the chapters describing those
portions of the architecture. A concise list of instructions and opcode
assignments appears in Appendix F.
The instructions which may be
subsetted in certain VAX-11 implementations are listed in Appendix E.
Details of the assembler notation are given in Appendix B.

4.1.1

Instruction Descriptions

The instruction set is divided into 12 major sections:
1.

Integer arithmetic and logical

Floating point

Address

Variable length bit field

Control

Procedure call

Miscellaneous

Queue

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Instructions
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Page 4-2
INSTRUCTION SET
9.

Character string

10.

Cyclic Redundancy Check

11.

Decimal string

12.

Edit

Within each major section, instructions which are
combined into groups and described together.
description is composed of the following:

closely related are
The instruction group

The group name.

The format of each instruction in the group.
This gives the
name and type of each instruction operand specifier and the
order in which it appears in memory. Operand specifiers from
left to right appear in increasing memory addresses. The
notation used to describe operand specifiers is given in
Section 1I.1.2.

The operation of the instruction given in a concise
The notation is described briefly in Section 4.1.3.

The effect on condition codes.
the operation description.

Exceptions specific to the instruction. Exceptions which are
generally possible for all instructions (e.g., illegal or
reserved addressing mode, T-bit, memory management violations,
etc.) are not listed.

The opcodes, mnemonics, and names of each
group. The opcodes are given in hex.

A description in English of the instruction.

Optional notes on the instruction and programming
Additional examples are given in Appendix D.

notation.

The same notation is used as in

instruction

the

examples.

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Page 4-3
INSTRUCTION SET
4.1.2

Operand Specifier Notation

Operand specifiers are described in the following way:
<name>.<access type><data type>
where:
1.

Name is a suggestive name for the operand in the context of the
instruction. The name is often abbreviated.

Access type is a letter denoting the operand
type:

specifier

access

a - Calculate the effective address of the specified
operand. Address is returned in a longword
which is the actual instruction operand. Context
of address calculation is given by <data type>.
(i.e. size to be used in autoincrement, autodecrement,
and indexing)
b - No operand reference. Operand specifier is a
branch displacement. Size of branch displacement
is given by <data type>.
m - Operand is read, potentially modified and written.
Note that this is NOT an indivisible memory
operation. Also note that if the operand is not
actually modified, it may not be written back.
However, modify type operands are always checked
for both read and write accessability (See
Chapter 5).
r - Operand is read only.

w - Operand is written only.

Data type is a letter denoting the data type of the operand:
b - byte
d - double floating or D_floating
f - floating or F_floating

1 - longword

o - octaword

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Page 4-4
INSTRUCTION SET
q - quadword
w - word

x - first data type specified by instruction
y - second data type specified by instruction

4.1.3

Operation Description Notation

The operation of each instruction is given as a sequence of control and
assignment statements in an ALGOL-like syntax. No attempt is made to
define the syntax formally, it is assumed to be familiar to the reader.
The notation used is an extension of that introduced in Section 3.3.
\Ultimately, the notation used here will be described formally or it
will be replaced by ISP. In either event a formal description of the
notation used to describe instructions will appear in Appendix G.\
+ - addition
subtraction, unary minus

* - multiplication
/ - division (quotient only)

** - exponentiation
, - concatenation

<- - is replaced by

= - is defined as
Rn or R[n) - contents of register Rn
PC, SP, FP, or AP - the contents of register R15, R14, R13,
or R12 respectively
PSW - the contents of the processor status word
PSL - the contents of the processor status long word
(x)

contents of memory location whose address is x

(x)+ - contents of memory location whose address is x;
x incremented by the size of operand referenced
at x
-(x) - x decremented by size of operand to be referenced
at x; contents of memory location whose address is x

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Instructions
27-0ct-18 -- Rev 5
Page 4-5
INSTRUCTION SET

<x:y> - a modifier which delimits an extent from bit
position x to bit position y inclusive
<xl,x2, .•. ,xn) - a modifier which enumerates bits xl,x2, •.• ,xn
{ } - arithmetic parentheses used to indicate precedence
AND - logical AND
OR - logical OR
XOR - logical XOR
NOT - logical (ones) complement
LSS - less than signed
LSSU - less than unsigned
LEO - less than or equal Signed
LEQU - less than or equal unsigned
EQL - equal signed
EQLU - equal unsigned
NEQ - not equal signed
NEQU - not equal unsigned
GEQ - greater than or equal Signed
GEQU - greater than or equal unsigned
GTR - greater than Signed
GTRU - greater than unsigned
SEXT(x) - x is sign extended to size of operand
needed
ZEXT(x) - x is zero extended to size of operand needed
REM(x,y) - remainder of x divided by y, such that x/y and
REM(x,y) have the same sign
MINU(x,y) - minimum unsigned of x and y
MAXU(x,y) - maximum unsigned of x and y

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lnstructions
27-0ct-78 -- Rev 5
Page 4-6
INSTRUCTION SET
The following conventions are used:
1.

Other than that caused by ( )+, or -( ), and the advancement of
PC, only operands or portions of operands appearing on the left
side of assignment statements are affected.

No operator precedence is assumed, other than that replacement
has the lowest precedence.
Precedence is indicated
explicitly by { }.

All arithmetic, logical, and relational operators are defined
in the context of their operands. For example n+" applied to
floating operands means a floating add while "+" applied to
byte operands is an integer byte add. Similarily, "LSS" is a
floating comparison when applied to floating operands while
"LSS" is an integer byte comparison when applied to byte
operands.

Instruction operands are evaluated according to the 'operand
specifier conventions (See Chapter 3).
The order in which
operands appear in the instruction description has no effect on
the order of evaluation.

Condition codes are in general affected on the value of actual
stored results, not on "true" results (which might be generated
internally to greater precision).
Thus, for example,
2
positive integers can be added together and the sum stored,
because of overflow, as a negative value. The condition codes
will indicate a negative value even though the "true" result is
clearly positive.

«-)

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS
4.2

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

MOV

Move

Format:
opcode src.rx, dst.wx
Operation:
dst <- src;
Condition Codes:
N <Z <-

dst LSS 0;
dst EQL OJ

V <- 0;
C <- C;

Exceptions:
none
Opcodes:
90
BO
DO
7D
1DFD

MOVB
MOVW
MOVL
MOVQ
MOVO

Move Byte
Move Word
Move Long
Move Quad
Move Octa

Description:
The destination operand is replaced by the source operand.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

PUSHL

Push Long

Format:
opcode src .rl
Operation:
- (SP) <- src;
Condition Codes:
N <Z <-

src LSS 0;
src EQL 0;
V <- 0;
C <- C;

Exceptions:
none
Opcodes:
DD

PUSHL

Push Long

Description:
The longword source operand is pushed on the stack.
Notes:
PUSHL is equivalent to MOVL src, -(SP), but is 1 byte shorter.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

CLR

Clear

Format:
opcode dst. wx
Operation:
dst <- 0;
Condition Codes:
N <- 0;

Z <- 1;
V <- 0;
C <- C;
Exceptions:
none
Opcodes:
94
B4
D4
7C
7CF"

CLRB
CLRW
CLRL
CLRQ
CLRO

Clear Byte
Clear Word
Clear Long
Clear Quad
Clear Octa

Description:
The destination operand is replaced by O.
Notes:
CLRx dst is equivalent to MOVx SAIO, dst, but is 1 byte shorter.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

MNEG

Move Negated

Format:
opcode src.rx, dst.wx
Operation:
dst <- -src;
Condition Codes:
N <- dst LSS 0;
Z <- dst EQL 0;
V <- {integer overflow};
C <- dst NEQ OJ
Exceptions:
integer overflow
Opcodes:

BE
AE
CE

MNEGB Move Negated Byte
MNEGW Move Negated Word
MNEGL Move Negated Long

Description:
The destination operand is
operand.

replaced

the

negative

of the

source

Notes:
Integer overflow occurs if the source operand is the largest negative
integer
(which
has no positive counterpart).
On overflow, the
. destination operand is replaced by the source operand.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

MCOM

Move Complemented

Format:
opcode src.rx, dst.wx
Operation:
dst <- NOT src;
Condition Codes:
N <- dst LSS 0;
Z <- dst EQL 0;
V <- 0;
C <- C;
Exceptions:
none
Opcodes:
92
B2
D2

MCOMB
MCOMW
MCOHL

Move Complemented Byte
Move Complemented Word
Move Complemented Long

Description:
The destination operand is replaced by the ones complement of the source
operand.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

MOVZ

Move Zero-Extended

Format:
opcode src.rx, dst.wy
Operation:
dst <- ZEXT(src);
Condition Codes:

N <- 0;
Z <- dst EQL 0;
V <- OJ

C <- C;
Exceptions:
none
Opcodes:
9B
9A
3C

MOVZBW Move Zero-Extended Byte to w·ord
MOVZBL Move Zero-Extended Byte to Long
MOVZWL Move Zero-Extended Word to Long

Description:
For MOVZ.BW, bits 7: 0 of the destination operand are replaced by the
source operand;
bits 15:8 are replaced by zero. For MOVZBL, bits 7:0
of the destination operand are replaced by the source operand;
bits
31:8 are replaced by O.
For MOVZWL, bits 15:0 of the destination
operand are replaced by the source operand; bits 31:16 are replaced by
O.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

CVT

Convert

Format:
opcode src.rx, dst.wy
Operation:
dst <- conversion of src;
Condition Codes:
N <- dst LSS 0;
Z <- dst EQL 0;
V <- {integer overflow};
C <- 0;
Exceptions:
integer overflow
Opcodes:
99
98
33

32
F6
F1

CVTBW Convert Byte to \t1ord
CVTBL Convert Byte to Long
CVTWB Convert \t1ord to Byte
CVTWL Convert Word to Long
CVTLB Convert Long to Byte
CVTLW Convert Long to Word

Description:
The source operand is converted to the data type of the destination
operand
and the destination operand is replaced by the -result.
Conversion of a shorter data type to a longer is done by sign extension;
conversion of longer to a shorter is done by truncation of the higher
numbered (most significant) bits.
Notes:
Integer overflow occurs if any truncated bits of the source operand
not equal to the sign bit of the destination operand.

are

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

CMP

Compare

Format:
opcode src1.rx, src2.rx
Operation:
src1 - src2;
Condition Codes:
N <- src1 LSS src2;
Z <- src1 EQL src2;
V <- O·,
C <- src1 LSSU src2;
Exceptions:
none
Opcodes:
91
B1
D1

CMPB
CMPW
CMPL

Compare Byte
Compare Word
Compare Long

Description:
The source 1 operand is compared with the source 2 operand.
action is to affect the condition codes.

The

only

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

TST

Test

Format:
opcode src.rx
Operation:
src - 0;
Condition .Codes:
N <- src LSS 0;
Z <- src EQL 0;
V <- 0;
C <- 0;
Exceptions:
none
Opcodes:
95
B5
D5

TSTB
TSTW
TSTL

Test Byte
Test Word
Test Long

Description:
The condition codes are affected according to the value
operand.

of the

Notes:
TSTx src is equivalent to CMPx src, SAIO , but is 1 byte shorter.

source

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Page 4-17
INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

ADD

Add

Format:
opcode add.rx, sum.mx

2 operand

opcode add1.rx, add2.rx, sum.wx 3 operand
Operation:
sum <- sum + add;

12 operand

sum <- add1 + add2;

!3.operand

Condition Codes:
N <- sum LSS 0;
Z <- sum EQL 0;
V <- {integer overflow};
C <- {carry from most significant bit};
Exceptions:
integer overflow
Opcodes:

80
81
AO
A1
CO
C1

ADDB2
ADDB3
ADDW2
ADDW3
ADDL2
ADDL3

Add Byte 2 Operand
Add Byte 3 Operand
Add Word 2 Operand
Add Word 3 Operand
Add Long 2 Operand
Add Long 3 Operand

Description:
In 2 operand format, the addend operand is added to the sum operand and
the sum operand is replaced by the result. In 3 operand format, the
addend 1 operand is added to the addend 2 operand and the sum operand is
replaced by the result.
Notes:
Integer overflow occurs if the input operands to the add have the same
Sign and the result has the opposite sign. On overflow, the sum operand
is replaced by the low order bits of the true result.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

ADAWI

Add Aligned Word Interlocked

Format:
opcode add.rw, sum.mw
Operation:
tmp <- add;
{set interlock};
sum <- sum + tmp;
{release interlock};
Condition Codes:
N <- sum LSS 0;
Z <- sum EQL 0;
V <- {integer overflow};
C <- {carry from most significant bit};
Exceptions:
reserved operand fault
integer overflow
Opcodes:
58

ADAWI

Add Aligned Word Interlocked

Description:
The addend operand is added to the sum operand and the sum operand is
replaced by the result. The operation is interlocked against 'similar
operations on other processors in a multiprocessor system.
The
destination must be aligned on a word boundary i.e. bit 0 of the
address of the sum operand must be zero.
If it is not, a reserved
operand fault is taken.
Notes:
1.

Integer overflow occurs if the input operands to the add have
the same sign and the result!las the opposite sign. On
overflow, the sum operand is replaced by the low order bits of
the true result.

If the addend and the sum operands overlap, the result and
condition codes are UNPREDICTABLE.

the

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

INC

Increment

Format:
opcode sum.mx
Operation:
sum <- sum + 1;
Condition Codes:
N <- sum LSS 0;
Z <- sum EQL 0;
V <- {integer overflow};
C <- {carry from most significant bit};
Exceptions:
integer overflow
Opcodes:

96
B6
D6

INCB
INCW
INCL

Increment Byte
Increment Word
Increment Long

Description:
One is added to the sum operand and the sum operand is replaced
result.

the

Notes:
1.

Arithmetic overflow occurs if the largest positive integer is
incremented.
On overflow, the sum operand is replaced by the
largest negative integer.

INCx sum is equivalent
shorter.

ADDx

S D1,

sum,

but

byte

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

ADWC

Add With Carry

Format:
opcode add.rl, sum.ml
Operation:
sum <- sum + add + C;
Condition Codes:
N <- sum LSS 0;
Z <- sum EQL 0;
V <- {integer overflow};
C <- {carry from most significant bit};
Exceptions:
integer overflow
Opcodes:
ADWC

Add With Carry

Description:
The contents of the condition code C bit and the addend operand are
added to the sum operand and the sum operand is replaced by the result.
Notes:
1.

On overflow, the sum operand is replaced by the low order
of the true result.

The 2 additions in the operation are performed
A more formal descripion is \TBS\.

bits

simultaneously.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

SUB

Subtract

Format:
opcode sub.rx, dif.mx

2 operand

opcode sub.rx, min.rx, dif.wx

3 operand

Operation:
dif <- dif - sub;

!2 operand

dif <- min - sub;

13 operand

Condition Codes:
N <- dif LSS 0;

Z <- dif EQL 0;

V <- {integer overflow};
C <- {borrow into most significant bit};
Exceptions:
integer overflow
Opcodes:
82
83
A2
A3
C2
C3

SUBB2 Subtract Byte 2 Operand
SUBB3 Subtract Byte 3 Operand
SUBW2 Subtract Word 2 Operand
SUBW3 Subtract Word 3 Operand
SUBL2 Subtract Long 2 Operand
SUBL3 Subtract Long 3 Operand

Description:
In 2 operand format, the subtrahend operand is subtracted from the
difference operand and the difference operand is replaced by the result.
In 3 operand format, the subtrahend operand is subtracted from the
minuend operand and the difference operand is replaced by the result.
Notes:
Integer overflow occurs if the input operands to the subtract are of
different signs and the sign of the result is the sign of the
subtrahend. On overflow, the difference operand is replaced by the low
order bits of the true result.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

DEC

Decrement

Format:
opcode dif .mx
Operation:
dif <- dif - 1;
Condition Codes:
N <- dif LSS 0;
Z <- dif EQL 0;
V <- {integer overflow};
C <- {borrow into most significant bit};
Exceptions:
integer overflow
Opcodes:
97
B7
D7

DECB
DECW
DECL

Decrement Byte
Decrement Word
Decrement Long

Description:
One is subtracted from the difference operand and the difference operand
is replaced by the result.
Notes:
1.

Integer overflow occurs if the largest negative integer is
decremented.
On overflow, the difference operand is replaced
by the largest positive integer.

DECx dif is equivalent
shorter.

SUBx

S I1,

dir,

but

1 byte

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

SBWC

Subtract With Carry

Format:
opcode sub.rl, dif.ml
Operation:
dif <- dif - sub - C;
Condition Codes:
N <- dif LSS 0;
Z <- dif EQL 0;
V <- {integer overflow};
C <- {borrow into most significant bit};
Exceptions:
integer overflow
Opcodes:
D9

SBWC

Subtract With Carry

Description:
The subtrahend operand and the contents of the condition code C bit are
subtracted from the difference operand and the difference operand is
replaced by the result.
Notes:
1.

On overflow, the difference operand
order bits of the true result.

replaced

The
2
subtractions
in
the
operation
are
simultaneously. A more formal description is \TBS\.

the

low

performed

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

MUL

Multiply

Format:
opcode mulr.rx, prod.mx

2 operand

opcode mulr.rx, muld.rx, prod.wx

3 operand

Operation:
prod <- prod * mulr;

!2 operand

prod <- muld * mulr;

13 operand

Condition Codes:
N <- prod LSS 0;
Z <- prod EQL 0;
V <- {integer overflow} ;
C <- 0;
Exceptions:
integer overflow
Opcodes:
84
85
A4
A5
C4
C5

MULB2
MULB3
MULW2
MULW3
MULL2
MULL3

Multiply Byte 2 Operand
Multiply Byte 3 Operand
Multiply Word 2 Operand
Multiply Word 3 Operand
Multiply Long 2 Operand
Multiply Long 3 Operand

Description:
In 2 operand format, the product operand is multiplied by the multiplier
operand and the product operand is replaced by the low half of the
double length result. In 3 operand format, the multiplicand operand is
multiplied by the multiplier operand and the product operand is replaced
by the low half of the double length result.
Notes:
Integer overflow occurs if the high half of the double length result
not equal to the sign extension of the low half.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

EMUL

Extended Multiply

Format:
opcode mulr.rl, muld.rl, add.rl, prod.wq
Operation:
prod <- {muld * muIr} + SEXT(add);
Condition Codes:
N <- prod LSS 0;
Z <- prod EQL 0;

V <- 0;
C <- 0;
Exceptions:
none
Opcodes:
7A

EMUL

Extended Multiply

Description:
The multiplicand operand is multiplied by the multiplier operand giving
a double length result. The addend operand is sign-extended to double
length and added to the result. The product operand is replaced by the
final result.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

DIV

Divide

Format:
opcode divr.rx, quo.mx
opcode divr.rx, divd.rx,

2 operand

qUO.!

3 operand

Operation:
quo <- quo / divr;

!2 operand

quo <- divd / divr;

! 3 operand

Condition Codes:

N <- quo LSS 0;
Z <- quo EQL 0;
V <- {integer overflow} OR {divr EQL OJ;
C <- 0;
Exceptions:
integer overflow
divide by zero
Opcodes:
86
87
A6
A7
C6
C7

DIVB2
DIVB3
DIVW2
DIVW3
DIVL2
DIVL3

Divide Byte 2 Operand
Divide Byte 3 Operand
Divide Word 2 Operand
Divide Word 3 Operand
Divide Long 2 Operand
Divide Long 3 Operand

Description:
In 2 operand format, the quotient operand is divided by the divisor
operand and the quotient operand is replaced by the result. In 3
operand format, the dividend operand is divided by the divisor operand
and the quotient operand is replaced by the result.
Notes:
1.

Division is performed such that the remainder (unless it is
zero and which is lost) has the same sign as the dividend,
i.e., the result is truncated towards O.

Integer overflow occurs if and only if the largest negative
integer is divided by -1. On overflow, operands are affected
as in 3 below.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

If the divisor operand is 0, then in 2 operand format the
quotient operand is not affected;
in 3 operand format the
quotient operand is replaced by the dividend operand.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

EDIV

Extended Divide

Format:
opcode divr.rl, divd.rq, quo. wI, rem.wl
Operation:
quo <- divd / divr;
rem <- REM(divd, divr);
Condition Codes:
N <- quo LSS 0;
Z <- quo EQL 0;
V <- {integer overflow} OR {divr EQL O};
C <- 0;
Exceptions:
integer overflow
divide by zero
Opcodes:
7B

EDIV

Extended Divide

Description:
The dividend operand is divided by the divisor operand;
the quotient
operand is replaced by the quotient and the remainder operand is replace
by the remainder.
Notes:
1.

The division is performed such that the remainder operand
(unless it is 0) has the same sign as the dividend operand.

On overflow, the operands are affected as in 3.

If the divisor operand is 0, then the quotient operand is
replaced by bits 31:0 of the dividend operand, and the
remainder operand is replaced by O.

below.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

ASH

Arithmetic Shift

Format:
opcode cnt.rb, src.rx, dst.wx
Operation:
dst <- src shifted cnt bits;
Condition Codes:
N <- dst LSS 0;
Z <- dst EQL 0;
V <- {integer overflow};
C <- 0;
Exceptions:
integer overflow
Opcodes:
78
19

ASHL Arithmetic Shift Long
ASHQ Arithmetic Shift Quad

Description:
The source operand is arithmetically shifted by the number of bits
specified by the count operand and the destination operand is replaced
by the result. The source operand is unaffected.
A positive count
operand shifts to the left bringing Os into the least significant bit.
A negative count operand shifts to the right bringing in copies of the
most signficant (sign) bit into the most significant bit. A 0 count
operand replaces the destination operand with the unshifted source
operand.
Notes:
1.

Integer overflow occurs on a left shift if any bit shifted into
the sign bit position differs from the sign bit of the source
operand.

If cnt GTR 32 (ASHL) or cnt
operand is replaced by O.

If cnt LEQ -31 (ASHL) or cnt LEQ -63 (ASHQ) all the bits of the
destination operand are copies of the sign bit of the source
operand.

GTR

(ASHQ)

the

destination

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

BIT

Bit Test

Format:
opcode mask.rx, src.rx
Operation:
tmp <- src AND mask;
Conditon Codes:
N <- tmp LSS 0;
Z <- tmp EQL 0;

V <- 0;
C <- C;
Exceptions:
none
Opcodes:
93
B3
D3

BITB Bit Test Byte
BITW Bit Test Word
BITL Bit Test Long

Description:
The mask operand is ANDed with the source operand.
Both operands
unaffected. The only action is to affect condition codes.

are

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

BIS

Bit Set

Format:
opcode mask.rx, dst.mx

2 operand

opcode mask.rx, src.rx, dst.wx

3 operand

Operation:
dst <- dst OR mask;

!2 operand

dst <- src OR mask;

13 operand

Conditon Codes:
N <- dst LSS 0;
Z <- dst EQL 0;
V <- O·,
C <- C;
Exceptions:
none
Opcodes:
88
89
A8
A9
c8

BISB2
BISB3
BISW2
BISW3
BISL2
BISL3

Bit Set Byte 2 Operand
Bit Set Byte 3 Operand
Bit Set Word 2 Operand
Bit Set Word 3 Operand
Bit Set Long 2 Operand
Bit Set Long 3 Operand

Description:
In 2 operand format, the mask operand is ORed with the destination
operand and the destination operand is replaced by the result. In 3
operand format, the mask operand is ORed with the source operand and the
destination operand is replaced by the result.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

BIC

Bit Clear

Format:
opcode mask.rx, dst.mx

2 operand

opcode mask.rx, src.rx, dst.wx

3 operand

Operation:
dst <- dst AND {NOT mask};

12 operand

dst <- src AND {NOT mask};

13 operand

Condition Codes:
N <- dst LSS 0;
Z <- dst EQL 0;
V <- OJ

C <- C;
Exceptions:
none
Opcodes:
8A
8B
AA
AB
CA
CB

BICB2
BICB3
BICW2
BICW3
BICL2
BICL3

Bit Clear Byte
Bit Clear Byte
Bit Clear Word
Bit Clear Word
Bit Clear Long
Bit Clear Long

Description:
In 2 operand format, the destination operand is ANDed with the ones'
complement of the mask operand and the destination operand is replaced
by the result. In 3 operand format, the source operand is ANDed with
the ones complement of the mask operand and the destination operand is
replaced by the result.

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INTEGER ARITHMETIC AND 'LOGICAL INSTRUCTIONS

XOR

Exclusive OR

Format:
opcode mask.rx, dst.mx

2 operand

opcode mask.rx, src.rx, dst.wx

3 operand

Operation:
dst <- dst XOR mask;

!2 operand

dst <- src XOR mask;

!3 operand

Condition Codes:
N <- d~ LSS 0;
Z <- d~ E~ 0;
V <- 0;

C <- C;
Exceptions:
none
Opcodes:
BC

8D
AC
AD
CC
CD

XORB2
XORB3
XORW2
XORW3
XORL2
XORL3

Exclusive OR Byte 2 Operand
Exclusive OR Byte 3 Operand
Exclusive OR Word 2 Operand
Exclusive OR Word 3 Operand
Exclusive OR Long 2 Operand
Exclusive OR Long 3 Operand

Description:
In 2 operand format, the mask operand is XORed with the destination
operand and the destination operand is replaced by the result. In 3
operand format, the mask operand is XORed with the source operand and
the destination operand is replaced by the result.

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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

ROTL

Rotate Long

Format:
opcode cnt.rb, src.rl, dst.wl
Operation:
dst <- srcrotated cnt bits;
Condition Codes:
N <- dst LSS 0;
Z <- dst EQL 0;
V <- OJ
C <- C;
Exceptions:
none
Opcodes:
9C

ROTL

Rotate Long

Description:
The source operand is rotated logically by the number of bits specified
by the count operand and the destination operand is replaced by the
result. The source operand is unaffected.
A positive count operand
rotates to the left. A negative count operand rotates to the right. A
o count operand replaces the destination operand with the source
operand.

CHAPTER 4
INSTRUCTIONS

31-Jan-79 -- Rev 5

1.*1.11111***11 •••••• 1••••• *•••• *.11 ••• 1••••• *.* •• 1••••

•

*
*
I
*
•
FOR EXTENDED RANGE FLOATING POINT DATA TYPES
*
I
***1 ••• 1** COMPANY-CONFIDENTIAL **1*11****
•*
••• ** •• *•• *.*.** ••••• ** ••• *.*.*.*.***.*.*********** •••••*

•

THIS SECTION CONTAINS NEW INSTRUCTIONS

Page 1

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

VAX-l1 Floating Point Instructions -- Rev 5

Specification Status:
Architectural Status:
File:

under ECO control

SR4BR5.RNO

PDM #: not used
Date:

31-Jan-79

Superseded Specs:

Rev 4

Author:

Strecker

Typist:

Call

Reviewer(s):

Abstract:

R. Blair, R. Brender, D. Cane, K. Chapman, P. Conklin,
D. Cutler, R. Grove, T. Hastings, D. Hustvedt, J. Leonard,
P. Lipman, M. Payne, D. Rodgers, S. Rothman, B. Stewart,
B. Strecker

Chapter 4 describes the instructions generally used by all
software
across
all
implementations
of the
VAX-l1
architecture.
For convenience of review and
editting,
chapter 4 is separated into a number of specifications. This
specification contains the floating point instructions.

Revision History:
Rev I
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5

Description
Initial distribution of SRM
ECOs 1-11
ECOs 12-18, April Meeting,
and May 25 Meeting
ECO to POLY, and ECO to
facilitate high speed fl. pt.
Extended range data types ECO

Author
Strecker
Strecker
Strecker

Revised Date
25-Sep- 75
16-Mar-76
10-Jun-76

Strecker

24-Mar-77

Bhandarkar

31-Jan-79

Instructions
31-Jan-79 -- Rev 5
Change History for Floating Point
Rev 4 to Rev 5
1•

Add following instructions:
50F'D

MOVG Move G_floating

70FD

MOVH Move H_floating

7CFD

CLRH Clear H_floating

7CFD

CLRO Clear Octa

52FD

MNEGG Move Negated G_floating

72FD

MNEGH Move Negated H_floating

4CFD

CVTBG Convert Byte to G_floating

6CFD

CVTBH Convert Byte to H_floating

4DFD

CVT'WG Convert Word to G_floating

6DFD

CVTWH Convert Word to H_floating

4EFD

CVTLG Convert Long to G_floating

6EFD

CVTLH Convert Long to H_floating

48FD

CVTGB Convert G_floating to Byte

68FD

CVTHB Convert H_floating to Byte

49FD

CVTGW Convert G_floating to Word

69FD

CVTHW Convert H_floating to Word

4AFD

CVTGL Convert G_floating to Long

4BFD

CVTRGL Convert Rounded G_floating to Long

6AFD

CVTHL Convert H_floating to Long

6BFD

CVTRHL Convert Rounded H_floating to Long

56FD

CVTGH Convert G_floating to H_floating

76FD

CVTHG Convert H_floating to G_floating

33FD

CVTGF Convert G_floating to Floating

F6FD

CVTHF Convert H_floating to Floating

Page 4-990

Instructions
31-Jan-79 -- Rev 5
Change History for Floating Point

Page 4-991

99FD

CVTFG Convert Floating to G_floating

98FD

CVTFH Convert Floating to H_floating

F7FD

CVTHD Convert H_floating to Dfloating

32FD

CVTDH Convert Dfloating to H_floating

51FD

CMPG

71F'D

CMPH Compare H_floating

53FD

TSTG Test G_floating

73FD

TSTH Test H_floating

40FD

ADDG2 ADD G_floating 2 Operand

41FD

ADDG3 ADD G_floating 3 Operand

60FD

ADDH2 ADD H_floating 2 Operand

61FD

ADDH3 ADD H_floating 3 Operand

42FD

SUBG2 Subtract G_floating 2 Operand

43FD

SUBG3 Subtract G_floating 3 Operand

62FD

SUBH2 Subtract H_floating 2 Operand

63FD

SUBH3 Subtract H_floating 3 Operand

44F'D

MULG2 Multiply G_floating 2 Operand

45FD

MULG3 Multiply G_floating 3 Operand

64FD

MULH2 Multiply R-floating 2 Operand

65F'D

MULH3 Mul tiply R-floating 3 Operand

46FD

DIVG2 Divide G_floating 2 Operand

47FD

DIVG3 Divide G_floating 3 Operand

66FD

DIVH2 Divide R-floating 2 Operand

67FD

DIVH3 Divide H_floating 3 Operand

54FD

EMODG Extended Multiply and Integerize G_floating

74FD

EMODH Extended Multiply and lntegerize H_floating

Compare G_floating

Page 4-992

Instructions
31-Jan-'l9 -- Rev 5
Change History for Floating Point

55FD

POLYG

Polynomial Evaluation G_floating

75FD

POLYH

Polynomial Evaluation H_floating

Add floating underflow/overflow faults

Rev 3 to Rev 4:
1.

Remove destination operand specifier for POLY

Reverse the the order of coefficients for POLY

POLYF will not set R4 or R5

Change the name of second operand of POLY to degree

For POLY give reserved operand fault if degree operand> 31.

Define certain pathological addressing combinations to give
UNPREDICTABLE results to facilitate high speed floating point
implementations~

Add introduction and rounding/accuracy.

POLYx UNPREDICTABLE whether reserved operand if arg = O.

POLYx coefficient reserved can give FPD=O fault.

Rev 2 to Rev 3:
1.

Reserved operand aborts become faults

Specify 0 divisor behavior for DIVF, DIVD

Change pOinter to longword or address;

Add MINU function in ISP

Explicitly give SEXT or ZEXT in all cases needed

MOVF, MOVD take reserved operand fault

Remove round bit

Floating overflow, underflow get reserved, 0 respectively

Specified condition codes on all exceptions

10.

Remove CHOPF, CHOPD

11.

Update EMODF, EMODD per ECO 18

make it 32 bits

Instructions
31-Jan-79 -- Rev 5
Change History for Floating Point
12.

Change EMODD to produce longword fraction

13.

Split into separate specifications

Rev 1 to Rev 2:
See CH4A for changes
[End of SR4BR5.RNO]

Page 4-993

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FLOATING POINT INSTRUCTIONS
4.3

FLOATING POINT INSTRUCTIONS

\The floating point architecture was revised in January 1979 to add two
new data types (G_floating and H_floating) and to take faults instead of
traps on floating exceptions for the original data types (F_floating and
D_floating) as well as the two new data types. Modified versions of the
VAX-11/780 with the revised architecture might be built.\
In order to be consistent with the floating paint instruction set which
faults on reserved operands (See Chapter 2), software implemented
floating point functions (e.g., the absolute function) should verify
that the input operand(s) is (are) not reserved. An easy way to do this
is a floating move or test of the input operand(s).
In order to facilitate high speed implementations of the floating pOint
instruction set, certain restrictions are placed on the addressing mode
combinations usable within a single floating paint instruction.
These
combinations involve the logically inconsistent simultaneous use of a
value as both a floating point operand and an address.
Specifically: if within the same instruction the contents of register
Rn is used as both a part of a floating point input operand (i.e., a
.rf, .rd, .rg, .rh, .mf, .md, .mg, or .mh operand) and as an address in
an
addressing
mode
which
modifies
Rn
(i .e • ,
autoincrement,
autodecrement, or autoincrement deferred), the value of the floating
point operand is UNPREDICTABLE.

4.3.1

Introduction

Mathematically, a floating point number may be
form
(+

defined

having

the

or -) (2**K)*f,

where K is an integer and f is a non-negative fraction. For a
non-vanishing number, K and f are uniquely determined by imposing the
condition
112 LEQ f LSS 1.
The fractional factor, f, of the number is then said to be binary
normalized. For the number zero, f must be assigned the value 0, and
the value of K is indeterminate.
The VAX-11 floating point data formats are
derived
from
this
mathematical representation for floating point numbers. Four types of
floating paint data are provided:
the two standard PDP-11 formats
(F_floating and D_floating), and two extended range formats (G_floating
and H_floating). Single precision, o~floating, data is 32 bits long.
Double precision, or D_floating, data is 64 bits long. Extended range
double precision, or G_floating, data is 64 bits long.
Extended range

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FLOATING POINT INSTRUCTIONS
quadruple precision, or H_floating, data
magnitude notation is used, as follows:
1.

128

bits

long.

Sign

Non-zero floating point numbers:

The most significant bit of the floating pOint data is the sign bit:

o for positive, and 1 for negative.

The fractional factor f is assumed normalized, so that its most
significant bit must be 1. This 1 is the "hidden" bit: it is not
stored in the data word, but of course the hardware restores it
before carrying out arithmetic operations.
The F_floating and
D_floating data types use 23 and 55 bits, respectively, for f, which
with the hidden bit, imply effective significance of 24 bits and 56
bits for arithmetic operations.
The extended range data types,
G_floating and H_floating, use 52 and 112 bits, respectively, for f,
which with the hidden bit, imply effective significance of 53 and
113 bits for arithmetic operations.
In the F_floating and D_floating data types, eight bits are reserved
for the storage of the exponent K in excess 128 notation. Thus
exponents from -128 to +127 could be represented, in biased form, by
o to 255. For reasons given belOW, a biased EXP of 0 (true exponent
of -128), is reserved for floating point zero.
Thus, for the
F_floating and D_floating data types, exponents are restricted to
the range -127 to +127 inclusive, or in excess 128 notation, 1 to
255.
In the G_floating data type eleven bits are reserved for the storage
of the exponent in excess 1024 notation. In the H_floating data
type fifteen bits are reserved for the storage of the exponent in
excess 16384 notation.
A. biased exponent of 0 is reserved for
floating point zero. Thus, exponents are restricted to -1023 to
+1023 inclusive (in excess notation, 1 to 2047), and -16383 to
+16383 inclusive (in excess notation, 1 to 32767) for the G_floating
and H_floating data types respectively.
2.

Floating point zero:

Because of the hidden bit, the fractional factor is not available to
distinguish between zero and non-zero numbers whose fractional
factor is exactly 1/2.
Therefore
the
VAX-11
reserves
a
sign-exponent field of 0 for this purpose. Any positive floating
paint number with biased exponent of 0 is treated as if it were an
exact 0 by the floating pOint instruction set. In particular, a
floating point operand, whose bits are all O's, is treated as zero,
and this is the format generated by all floating pOint instructions
for which the result is zero.

The Reserved Operands:

A reserved operand is defined to be any bit pattern with a sign bit
of one and a biased exponent of zero. On the VAX-11, all floating
pOint instructions generate a fault if a reserved operand is

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FLOATING POINT INSTRUCTIONS
Since a reserved operand has a biased exponent of
zero, it can be (internally) generated only if overflow or divide by
zero occurs on the original VAX-11/780. The action of the VAX-l1 in
these circumstances is described at the end of the next section.

enc~untered.

4.3.2

Overview Of The Instruction Set

The VAX-11 has the standard arithmetic operations ADD, SUB, MUL, and DIV
implemented for all four floating data types. The results of these
operations are always rounded, as described in the section on accuracy.
It has, in addition, two composite operations, EMOD and POLY, also
implemented for all four floating pOint data types.
EMOD generates a
product of two operands, and then separates the product into its integer
and fractional terms. POLY evaluates a polynomial, given the degree,
the argument and pOinter to a table of coefficients. Details on the
operation of EMOD and POLY are given in their respective descriptions.
All of these instructions are subject to the rounding errors associated
with floating point operations, as well as to exponent overflow and
underflow.
Accuracy is discussed in the next section, and exceptions
are discussed in Chapter 6.
The VAX-l1 also has a complete set of instructions for conversiop from
integer arithmetic types (byte, word, longword) to all floatirtg types
(F_floating, D_floating, G_floating, H_floating), and vice versa.
The
VAX-11 also has a set of instructions for conversion between all of the
floating types except between D_floating and G_floating. Many of these
instructions are exact, in the sense defined in the section on accuracy
to follow.
However, a few may generate rounding error, floating
overflow, floating underflow, or induce integer overflow. Details are
given in the description of the CVT instructions.
There is a class of move-type instructions which are always exact: MOV,
NEG, CLR, eMP, and TST. And, finally, there is the ACB (add, compare
and branch) instruction, which is subject to rounding errors, overflow
and underflow.
All of the floating point instructions on the VAX-l1 fault if a reserved
operand is encountered.
On the original VAX-11/780, floating point
instructions trap when floating overflow occurs, and DIV generates a
trap if the divisor is O. For either of these exceptions, a reserved
operand is returned as the result, and the N and V condition code bits
are set. On all other VAX processors, floating point instructions fault
on the occurrence of floating overflow or divide by zero, and the
condition codes are UNPREDICTABLE. The FU bit, in the PSW, is available
to enable or disable an exception on underflow. If the FU bit is clear,
no exception occurs on underflow. If the FU bit is set, a trap (on the
original VAX-11/780) or fault (on all other VAX processors) occurs on
underflow.
If underflow occurs, zero is always returned as the result
on the original VAX-11/780.
On all other VAX processors, zero is
returned as the result on underflow only if FU is clear. Further
details on the actions taken if any of these exceptions occurs are
included in the descriptions of the instructions, and completely

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FLOATING POINT INSTRUCTIONS
discussed in Chapter 6.

4.3.3

Accuracy

General comments on the accuracy of the VAX-11
floating
point
instruction set are presented here. The descriptions of the individual
instructions may include additional details on the accuracy at which
they operate.
An instruction is defined to be exact if its result, extended on the
right by an infinite sequence of zeroes, is identical to that of an
infinite precision calculation involving the same operands.
The a
priori accuracy of the operands is thus ignored. For all arithmetic
operations, except DIV, a zero operand implies that the instruction is
exact.
The same statement holds for DIV if the zero operand is the
dividend. But if it is the divisor, division is undefined and the
instruction traps (on t~e original VAX-11/780) or faults (on all other
VAX processors).
For non-zero floating point operands, the fractional factor is binary
normalized with 24 or 56 bits for Single precision (F_floating) or
double precision (D_floating), respectively; and 53 or 113 bits for
extended
range double prec1s1on (G_floating), and extended range
quadruple precision (H_floating), respectively. We show below that for
ADD, SUB, MUL and DIV, an overflow bit, on the left, and two guard bits,
on the right, are necessary and sufficient to guarantee return of a
result identical to the corresponding infinite precision
rounded
operation rounded to the specified word length. Thus, with two guard
bits, a rounded result has an error bound of 1/2 LSB (least significant
bit).
Note that an arithmetic result is exact if no non-zero bits are lost in
chopping the infinite precision result to the data length to be stored.
Chopping is defined to mean that the 24 (F_floating), 56 (D_floating),
53 (G_floating), or 113 (H_floating) high order bits of the normalized
fractional factor of a result are stored; the rest of the bits are
discarded.
The first bit lost in chopping is referred to as the
"rounding" bit. The value of a rounded result is related to the chopped
result as follows:
1.

If the rounding bit is one, the rounded result is the
result incremented by an LSB (least significant bit) .

chopped

. 2.

If the rounding bit is zero, the rounded
are identical.

results

and

chopped

All VAX-11 processors implement rounding so as to produce results
identical to the results produced by the following algorithm. Add a 1
to the rounding bit, and propagate the carry, if it occurs. Note that a
renormalization may be required after rounding takes place; if this
happens, the new rounding bit will be zero, so it can happen only once.

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FLOATING POINT INSTRUCTIONS
The following statements summarize the relations among chopped, rounded
and true (infinite precision) results:
1.

If a stored result is exact
rounded value = chopped value = true value.

If a stored result is not exact, it's magnitude
1.

is always less than that of the true result for chopping.

is always less than that of the true result for rounding if
the rounding bit is zero.

is greater than that of the true result for rounding if the
rounding bit is one.

It will now be shown that an overflow bit and two guard bits are
adequate to guarantee accuracy of rounded ADD, SUB, MUL, or DIV,
provided, of course, that the algorithms are properly chosen.
Note,
first, that ADD or SUB may result in propagation of a carry, and hence
the overflow bit is necessary. Second, if in ADD or SUB there is a one
bit loss of significance in conjunction with an alignment shift of two
or more bits, the first guard bit is needed for the LSB of the
normalized result, and the second is then the rounding bit. So the
three bits are necessary. A number of constraints must be observed in
selection of the algorithms for the basic operations, in order for these
three bits to be sufficient to guarantee an error bound of (1/2) LSB:
1.

ADD or SUB:
1.

If the alignment shift does not exceed 2
constraints, because no bits can be lost.

there

are

If the alignment shift exceeds 2 (or however many guard
bits are used, say g GEQ 2), no negations may be made after
the alignment shift takes place.

If the above constraint is observed, the error bound for a
If, however, a negation
rounded result is (1/2) LSB.
follows the alignment shift, the error bound will be
(1/2)*(1 + 2**(-g+2»LSB

because a "borrow" will be lost on an implicit subtraction,
if non-zero bits were lost in the alignment shift.
Note
that the error bound is 1 LSB if the constraint is ignored
and there are only two guard bits (g = 2).
4.

The constraint on no negations after the alignment shift
may be rep~aced by keeping track of non-zero bits lost
during the alignment shift, and then negating by one's
complement if any "ones" were lost, and by two's complement

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FLOATING POINT INSTRUCTIONS
if none were lost.
be (1/2) LSB.
2.

If this is done, the error

bound

will

MUL:
1.

The product of two normalized binary fractions can be as
small as 1/4 and must be less than one. The overflow bit
is not needed for MUL, but the first guard bit will be
necessary for normalization if the product is less than
1/2, and, in this case, the second guard bit is the
rounding bit.

The first constrain~ on MUL is that the product be
generated from the least to the most significant bit. Low
order bits, in positions to the right of the second guard
bit, may be discarded, but ONLY AFTER they have made their
contribution to carries which could propagate into the
guard bits or beyond.

For the same reasons as for ADD or SUB, if low order bits
of the product have been discarded, no negations can be
made after generating the product.

DIV:
1.

For standard algorithms it is necessary that the remainder
be generated exactly at each step; the overflow and two
guard bits are adequate for this purpose.
The register
receiving the quotient must, of course, have a guard bit
for the rounding bit, and the quotient must be developed to
include the rounding bit.

The Newton-Raphson quadratic convergence algorithms, which
might make good use of high speed multiplication logic,
require a number of guard bits equal to twice the number of
bits desired in the result if the correctness of the
rounding bit is to be guaranteed.

The VAX-11 observes all constraints and generates floating point results
with an error bound of (1/2) LSB for all floating point instructions
except EMOD and POLY. The error analysis of EMOD and POLY is given with
their descriptions.

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FLOATING POINT INSTRUCTIONS

MOV

Move

Format:
opcode src.rx, dst.wx
Operation:
dst <- srcj
Condition Codes:
N <-

dst LSS OJ
Z <- dst EQL OJ
V <- OJ

C <- C·,
Exceptions:

reserved operand
Opcodes:
50
70
50FD
70FD

MOVF
MOVD
MOVG
MOVH

Move F_floating
Move D__floating
Move G_floating
Move H_floating

Description:
The destination operand is replaced by the source operand.
Notes:
On a reserved operand fault, the destination operand is
the condition codes are UNPREDICTABLE.

unaffected

and

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FLOATING POINT INSTRUCTIONS
CLR

Clear

Format:
opcode dst.wx
Operation:
dst <- 0;
Condition Codes:

N <- 0;
Z <- 1;

V <- 0;
C <- C;
Exceptions:
none
Opcodes:
D4
7C

CLRF
CLRD
CLRG
1CFD CLRH

Clear F_floating
Clear D_floating,
Clear G_floating
Clear H_floating

Description:
The destination operand is replaced by O.
Notes:
CLRx dst is equivalent to MOVx HO, dst, but is 5 (F_floating)
(D_floating or G_floating) or 11 (H_floating) bytes shorter.

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MNEG

Move Negated

Format:
opcode src.rx, dst.wx
Operation:
dst <- -src;
Condition Codes:
N <- dst LSS 0;
Z <- dst EQL 0;
V <- O·,
C <- 0;
Exceptions:
reserved operand
Opcodes:
52
72
52FD
72FD

MNEGF
MNEGD
MNEGG
MNEGH

Move Negated F__floating
Move Negated D_floating
Move Negated G_floating
Move Negated H_floating

Description:
The destination operand is
operand.

replaced

the

negative

of the

source

Notes:
On a reserved operand fault, the destination operand is
the condition codes are UNPREDICTABLE.

unaffected

and

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FLOATING POINT INSTRUCTIONS

CVT

Convert

Format:
opcode src.rx, dst.wy
Operation:
dst <- conversion of src;
Condition Codes:
N <Z <-

dst LSS 0;
dst EQL 0;
V <- {src cannot be represented in dst};

C <- 0;

Exceptions:
integer overflow
floating overflow
floating underflow
reserved operand
Opcodes:
4C
6C
4CFD
6CFD

CVTBF
CVTBD
CVTBG
CVTBH

Convert Byte to F_floating
Convert Byte to D_floating
Convert Byte to G_floating
Convert Byte to H_floating

4D
CVTWF
6D
CVTWD
4DFD CVTWG
6DFD CVTWH

Convert Word to F_floating
Convert Word to D_floating
Convert Word to G_floating
Convert Word to H_floating

4E
6E
4EFD
6EFD

Convert Long to F_floating
Convert Long to D_floating
Convert Long to G_floating
Convert Long to H_floating

CVTLF
CVTLD
CVTLG
CVTLH

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FLOATING POINT INSTRUCTlONS
48
CVTFB
68
CVTDB
48FD CVTGB
68FD CVTHB

Convert F_floating to Byte
Convert D_floating to Byte
Convert G_floating to Byte
Convert H_floating to Byte

49
69
49FD
69FD

Convert F_floating to Word
Convert D_floating to Word
Convert G_floating to Word
Convert H_floating to Word

CVTFW
CVTDW
CVTGW
CVTHW

4A
CVTFL Convert F_floating to Long
4B
CVTRFL Convert Rounded F_floating to Long
6A
CVTDL Convert D_floating to Long
6B
CVTRDL Convert Rounded D_floating to Long
4AFD CVTGL Convert G_floating to Long
4BFD CVTRGL Convert Rounded G_floating to Long
6AFD CVTHL Convert H_floating to Long
6BFD CVTRHL Convert Rounded H_floating to Long
56
99FD
98FD

CVl'FD
CVTFG
CVTFH

Convert F_floating to D_floating
Convert F_floating to G_floating
Convert F_floating to H_floating

76
32FD

CVTDF
CVTDH

Convert D_floating to F_floating
Convert D_floating to H_floating

33FD
56FD

CVTGF
CVTGH

Convert G_floating to F_floating
Convert G_floating to H_floating

F'6FD
F7FD
76FD

CVTHF . Convert H_floating to F_floating
CVl'HD Convert H_floating to D_floating
CVTHG Convert H_floating to G_floating

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FLOATING POINT INSTRUCTIONS
Description:
The source operand is converted to the data type of the destination
operand and the destination operand is replaced by the result. The form
of the conversion is as follows:
CVTBF
CVTBD
CVTBG
CVTBH
CVTWF
CVTWD
CVTWG
CVTWH
CVTLF
CVTLD
CVTLG
CVTLH

exact
exact
exact
exact
exact
exact
exact
exact
rounded
exact
exact
exact

CVTFB truncated
CVTDS truncated
CVTGB truncated
CVTHB truncated
CVTFW truncated
CVTDW truncated
CVTGW truncated
CVTHW truncated
CVTFL truncated
CVTRFL rounded
CVTDL truncated
CVTRDL rounded
CVTGL truncated
CVTRGL rounded
CVTHL truncated
CVTRHL rounded
CVTFD exact
CVTFG exact
CVTFH exact
CVTDF rounded
CVTDH exact
CVTGF' rounded
CVTGH exact
CVTHF rounded
CVTHD rounded
CVTHG rounded
Notes:
1.

Only CVTDF, CVTGF, CVTHF, CVTHD, and CVTHG can result in
floating overflow.
On floating overflow, on the original
VAX-11/780, the destination operand is replaced by an operand
of all bits
except for a sign bit of 1 (a reserved operand),
N<-1, Z<-O, V<-1, and C<-O.
On all other VAX processors,

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floating overflow results in a fault; the destination operand
is unaffected and the condition codes are UNPREDICTABLE.
2.

Only converts with a floating point source operand can result
in a reserved operand fault. On a reserved operand fault, the
destination operand is unaffected and the condition codes are
UNPREDICTABLE.

Only converts with an integer destination operand can result in
integer overflow. On integer overflow, the destination operand
is replaced by the low order bits of the true result.

Only CVTGF, CVTHF, CVTHD, and CVTHG can result in floating
underflow. If FU is set a trap (on the original VAX-11/780) or
fault (on all other VAX processors) occurs.
On the original
VAX-11/780, zero is always stored as the result of floating
underflow. On all other VAX processors, zero is stored as the
resul t of floating underflow only if FU is clear. On a
floating underflow
fault,
the
destination
operand
is
unaffected.
If FU is clear, the destination operand is
replaced by 0 and no exception occurs.

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FLOATING POINT INSTRUCTIONS

CIvlP

Compare

Format:
opcode src1.rx, src2.rx
Operation:
src1 - src2;
Condition Codes:
N <- src1 LSS src2;
Z <- src1 EQL src2;

V <- O·,
C <- OJ

Exceptions:
reserved operand
Opcodes:
51
71
51FD
11FD

CMPF
CMPD
CMPG
CMPH

Compare F_floating
Compare D_floating
Compare G_floating
Compare H_floating

Description:
The source 1 operand is compared with the source 2
action is to affect the condition codes.

operand.

The

Notes:
On a reserved operand fault, the condition codes are UNPREDICTABLE.

only

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TST

Test

Format:
opcode src.rx
Operation:
src - OJ
Condition Codes:
N <- src LSS 0;
Z <- src EQL 0;
V <- OJ
C <- O·,
Exceptions:
reserved operand
Opcodes:
53
13
53FD
73FD

TSTF
TSTD
TSTG
TSTH

Test F_floating
Test D_floating
Test G_floating
Test H_floating

Description:
The condition codes are affected according to the value
operand.

of the

source

Notes:
1.

TSTx src is equivalent to CMPx src, 10, but is 5 (F_floating)
or 9 (D_floating or G_floating) or 11 (H_floating) bytes
sh')rter.

On a reserved
UNPREDICTABLE.

operand

fault,

the • condition

codes

are

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FLOATING POINT INSTRUCTIONS

ADD

Add

Format:
opcode add.rx, sum.mx

2 operand

opcode add1.rx, add2.rx, sum.wx

3 operand

Operation:
sum <- sum + add;

!2 operand

sum <- add1 + add2;

13 operand

Condition Codes:
N <- sum LSS 0;
Z <- sum EQL 0;
V <- {floating overflow};
C <- 0;

Exceptions:
floating overflow
floating underflow
reserved operand
Opcodes:
40
41
60
61

ADDF2
ADDF3
ADDD2
ADDD3

Add F_floating 2 Operand
Add F_floating 3 Operand
Add D_floating 2 Operand
Add D_floating 3 Operand

40FD
41FD
60FD
61F'D

ADDG2
ADDG3
ADDH2
ADDH3

ADD G_floating2 Operand
ADD G_floating 3 Operand
ADD H_floating 2 Operand
ADD H_floating 3 Operand

Description:
In 2 operand format, the addend operand is added to the sum operand and
the sum operand is replaced by the rounded result. In 3 operand format,
the addend 1 operand is added to the addend 2 operand and the sum
operand is replaced by the rounded result.
Notes:
1.

On a reserved operand fault, the sum operand is unaffected
the condition cOdes'are UNPREDICTABLE.

and

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31-Jan-79 -- Rev 5
Page 4-51
FLOATING POINT INSTRUCTIONS
2.

On floating underflow, if FU is set a trap (on the original
VAX-11/780) or fault (on all other VAX processors) occurs. On
the original VAX-11/780, zero is always stored as the result of
floating underflow.
On all other VAX processors, zero is
stored as the result of floating underflow only if FU is clear.
On a floating underflow fault, the sum operand is unaffected.
If FU is clear, the sum operand is replaced by 0 and no
exception occurs.

On floating overflow, on the original VAX-11/780, the sum
operand is replaced by an operand of all bits 0 except for a
sign bit of 1 (a reserved operand), N<-l, Z<-O, V<-l, and C<-O.
On all other VAX processors,.the instruction faults, the sum
operand is
unaffected,
and
the
condition
codes
are
UNPREDICTABLE.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
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FLOATING POINT INSTRUCTIONS

SUB

Subtract

Format:
opcode sub.rx, dif.mx

2 operand

opcode sub.rx, min.rx, dif.w.x

3 operand

Operation:
dif <- dif - sub;

12 operand

dif <- min - sub;

!3 operand

Condition Codes:
N <- dif LSS 0;
Z <- dif EQL 0;
V <- {floating overflow};
C <- 0;
Exceptions:
floating overflow
floating underflow
reserved operand
Opcodes:
42
43
62
63
42FD
43FD
62FD
63FD

SUBF2 Subtract F_floating 2 Operand
SUBF3 Subtract F_floating 3 Operand
SUBD2 Subtract D_floating 2 Operand
SUBD3 Subtract D_floating 3 Operand
SUBG2 Subtract G_floating 2 Operand
SUBG3 Subtract G_floating 3 Operand
SUBH2 Subtract H_floating 2 Operand
SUBH3 Subtract H_floating 3 Operand

Description:
In 2 operand format, the subtrahend operand is subtracted from the
difference operand and the difference is replaced by the rounded result.
In 3 operand format, the subtrahend operand is subtracted from the
minuend operand and the difference operand is replaced by the rounded
result.
Notes:
1.

On a reserved operand fault, the difference operand
unaffected and the condition codes are UNPREDICTABLE.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
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VAX-11 System Reference Manual
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Instructions
31-Jan-79 -- Rev 5
Page 4-53
FLOATING POINT INSTRUCTIONS
2.

On floating underflow, if FU is set a trap (on the original
VAX-11/780) or fault (on all other VAX processors) occurs. On
the original VAX-11/780, zero is always stored as the result of
floating underflow.
On all other VAX processors, zero is
stored as the result of floating underflow only if FU is clear.
On a floating underflow fault, the difference operand is
unaffected. If FU is clear, the difference operand is replaced
by 0 and no exception occurs.

On floating overflow, on the
original
VAX-11/780,
the
difference operand is replaced by an operand of all bits 0
except for a sign bit of 1 (a reserved operand), N<-l, Z<-O,
V<-l, and C<-O. On all other VAX processors,the instruction
faults, the difference operand is unaffected, and the condition
codes are UNPREDICTABLE.

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Instructions
31-Jan-19 -- Rev 5
Page 4-54
FLOATING POINT INSTRUCTIONS

MUL

Multiply

Format:
opcode mulr.rx, prod.mx

2 operand

opcode mulr.rx, muld.rx, prod.wx

3 operand

Operation:
prod <- prod * mulrj

!2 operand

prod <- muld * mulr;

!3 operand

Condition Codes:
N <- prod LSS OJ
Z <- prod EQL OJ
V <- {floating overflow};
C <- OJ

Exceptions:
floating overflow
floating underflow
reserved operand
Opcodes:
44
45
64
65
44FD
45FD
64FD
65li'D

MULF2
MULli'3
MULD2
MULD3
MULG2
MULG3
MULH2
MULH3

Mul tiply F_floating 2 Operand
Multiply F_floating 3 Operand
Multiply D_floating 2 Operand
Multiply D_floating 3 Operand
Multiply G_floating 2 Operand
Multiply G_floating 3 Operand
Multiply H_floating 2 Operand
Multiply H_floating 3 Operand

Description:
In 2 operand format, the product operand is multiplied by the multiplier
operand and the product operand is replaced by the rounded result. In 3
operand format, the multiplicand operand is multiplied by the multiplier
operand and the product operand is replaced by the rounded result.
Notes:
1.

On a reserved operand fault, the product operand is
and the condition codes are UNPREDICTABLE.

unaffected

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Instructions
31-Jan-79 -- Rev 5
Page 4-55
FLOATING POINT INSTRUCTIONS
2.

On floating underflow, if FU is set a trap (on the original
VAX-11/780) or fault (on all other VAX processors) occurs. On
the original VAX-11/780, zero is always stored as the result of
floating underflow.
On all other VAX processors, zero is
stored as the result of floating underflow only if FU is clear.
On
a
floating underflow fault, the product operand is
unaffected. If FU is clear, the product operand is replaced by
and no exception occurs.

On floating overflow, on the original VAX-ll 1'780, the product
operand is replaced by an operand of all bits
except for a
sign bit of 1 (a reserved operand), N<-l, Z<-O, V<-1, and C<-O.
On all other VAX processors, the instruction faults, the
product operand is unaffected, and the condition codes are
UNPREDICTABLE.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
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Instructions
31-Jan-79 -- Rev 5
Page 4-56
FLOATING POINT INSTRUCTIONS

DIV

Divide

Format:
opcode divr.rx, quo.mx

2 operand

opcode divr.rx, divd.rx, quo.wx 3 operand
Operation:
quo <- quo / divr;

12 operand

quo <- divd / divr;

! 3 operand

Condition Codes:
N <- quo LSS 0;
Z <- quo EQL 0;
V <- {floating overflow} or {divr EQL Ol;
C <- 0;

Exceptions:
floating overflow
floating underflow
divide by zero
reserved operand
Opcodes:
46
41
66
61
46FD
47FD
66FD
67FD

DIVF2 Divide F_floating 2 Operand
DIVF3 Divide F_floating 3 Operand
DIVD2 Divide D_floating 2 Operand
DIVD3 Divide D_floating 3 Operand
DIVG2· Divide G_floating 2 Operand
DIVG3 Divide G_floating 3 Operand
DIVH2 Divide H_floating 2 Operand
DIVH3 Divide H_floating 3 Operand

Description:
In 2 operand format, the quotient operand is divided by the divisor
operand and the quotient operand is replaced by the rounded result. In
3 operand format, the dividend operand is divided by the divisor operand
and the quotient operand is replaced by the rounded result.
Notes:
1.

On a reserved operand fault, the quotient operand is unaffected
and the condition codes are UNPREDICTABLE.

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VAX-11 System Reference Manual
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Instructions
31-Jan-79 -- Rev 5
Page 4-57
FLOATING POINT INSTRUCTIONS
2.

On floating underflow, if FU is set a trap (on the original
VAX-11/780) or fault (on all other VAX processors) occurs. On
the original VAX-11/780, zero is always stored as the result of
floating underflow.
On all other VAX processors, zero is
stored as the result of floating underflow only if FU is clear.
On
a floating underflow fault, the quotient operand is
unaffected. If FU is clear, the quotient operand is replaced
by
and no exception occurs.

On floating overflow, on the original VAX-11/780, the quotient
operand j3 replaced by an operand of all bits 0 except for a
sign bit of 1 (a reserved operand), N<-1, Z<-O, V<-1, and C<-O.
On all other VAX processors, the instruction faults, the
quotient operand is unaffected, and the condition codes are
UNPREDICTABLE.

On divide by zero, the quotient operand and condition codes are
affected as in 3. above.

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Instructions
31-Jan-79 -- Rev 5
Page 4-58
FLOATING POINT INSTRUCTIONS

EMOD

Extended Multiply and Integerize

Format:
EMODF and EMODD:
opcode mulr.rx, mulrx.rb, muld.rx, int.wl,
fract.wx
EMODG and EMODH:
opcode mulr.rx, mulrx.rw, muld.rx, int.wl,
fract.wx
Operation:
int <- integer part of muld * {mulr'mulrx};
fract <- fractional part of muld * {mulr'mulrx};
Condition Codes:
N <- fract LSS 0;
Z <- fract EQL 0;
V <- {integer overflow};
C <- 0;
Exceptions:
integer overflow
floating underflow
reserved operand
Opcodes:
54
74
54FD
74FD

EMODF
EMODD
EMODG
EMODH

Extended Multiply and Integerize F_floating
Extended Multiply and Integerize D_floating
Extended Multiply and Integerize G_floating
Extended Multiply and Integerize H_floating

Description:
The multiplier extension operand is concatenated with the multiplier
operand to gain 8 (EMODD and EMODF), 11 (EMODG) , or 15 (EMODH)
additional low order fraction bits. The low order 5 or 1 bits of the
16-bit multiplier extension operand are ignored by the EMODG and EMODH
instructions respectively. The multiplicand operand is multiplied by
the extended multiplier operand. The multiplication is such that the
result is equivalent to
the
exact
product
truncated
(before
normalization) to a fraction field of 32 bits in F_floating, 64 bits in
D_floating and G_floating, and 128 in H_floating. Regarding the result
as the sum of an integer and fraction of the same sign, the integer
operand is replaced by the integer part of the result and the fraction
operand is replaced by the rounded fractional part of the result.

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Instructions
31-Jan-79 -- Rev 5
Page 4-59
FLOATING POINT INSTRUCTIONS
'Notes:
1•

On a reserved operand
fraction operand are
UNPREDICTABLE.

fault, the
unaffected.

integer operand and the
The condition codes are

On floating underflow, if FU is set a trap (on the original
VAX-11/780) or fault (on all other VAX processors) occurs. On
the original VAX-11/780, the integer and fraction parts are
replaced by zero on the occurrence of floating underflow. On
all other VAX processors, the integer and fraction parts are
replaced by' zero on the occurrence of floating underflow only
if FU is clear. On a floating underflow fault, the integer and
fraction parts are unaffected. If FU is clear, the integer and
fraction parts are replaced by
and no exception occurs.

On integer overflow, the integer operand is replaced by the low
order bits of the true result.

Floating overflow is indicated by integer overflow;
integer overflow is possible in the absence of
overflow.

The signs of the integer and
integer overflow results.

Because the fraction part is rounded after separation of the
integer part, it is possible that the value of the fraction
operand is 1.

fraction

are

the

same

however
floating
unless

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VAX-11 System Reference Manu~l
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Instructions
31-Jan-79 -- Rev 5
Page 4-60
FLOATING POINT INSTRUCTIONS

POLY

Polynomial Evaluation

Format:
opcode arg.rx, degree.rw, tbladdr.ab
Operation:
tmp1 <- degree;
if tmp1 GTRU 31 then RESERVED OPERAND EXCEPTION;
tmp2 <- tbladdr;
tmp3 <- {(tmp2)+};
!tmp3 accumulates the partial result
l~p3

is of type x

if POLYH then -(SP) <- arg;
tmp4 <- 0;
!underflow flag
while tmp1 GTRU 0 do
begin
Icomputation loop
tmp3 <- {arg * tmp3};
!Perform multiply, and retain a 31 (POLYF),
163 (POLYD, POLYG), or 127 (POLYH) bit fraction.
!(The fraction is truncated before normalization.)
IUse the result in the following add operation.
tmp3 <- tmp3 + (tmp2);
~ f-o +--flu.. X ~ i.
lnormalize,round~ check for over/underflow
!only after the combined multiply/add sequence
if OVERFLOW then FLOATING OVERFLOW EXCEPTION
if UNDERFLOW then
begin
if FU EQL 1 then FLOATING UNDERFLOW FAULT;
lexcept for original VAX-11/780
!' force resul t to 0;
tmp3 <- 0;
lset underflow flag
tmp4 <- 1;
end;
tmp1 <- tmp1 - 1;
tmp2 <- tmp2 + {size of data type};
end;
if POLYF then
begin
RO <- tmp3;
R1 <- 0;
R2 <- 0;
R3 <- tmp2;
end;
if POLYD or POLYG then
begin
R1 'RO <- tmp3;
R2 <- 0;
R3 <- tmp2;

R4 <- 0;
R5 <- 0;
end;
if POLYH then
begin

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Instructions
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Page 4-61
FLOATING POINT INSTRUCTIONS
SP <- SP + 16;
R3'R2'R1'RO <- tmp3;
R4 <- OJ
R5 <- tmp2;
end;
if 1mp4 EQL ~~n FLOATING UNDERFLOW TRAP
Condition Codes:

Fu -r=.~L i

N <- RO LSS 0;
Z <- RO EQL 0;
V <- {floating overflow};
C <- 0;
Exceptions:
floating overflow
floating underflow
reserved operand
Opcodes:
55
POLYF
75
POLYD
55F'D POLYG
75FD POLYH

Polynomial Evaluation F_floating
Polynomial Evaluation D_floating
Polynomial Evaluation G_floating
Polynomial Evaluation H_floating

Description:
The table address operand points to a table of polynomial coefficients.
The coefficient of the highest order term of the polynomial is pointed
to by the table address operand. The table is specified with lower
order coefficients stored at increasing addresses. The data type of the
coefficients is the same as the data type of the argument operand.
The evaluation is carried out by Horner's method and the contents of RO
(R1'RO for POLYD and POLYG, R3'R2'R1'RO for POLYH» are replaced by the
result. The result computed is:
if d = degree
and x = arg
result = C[O) + x*(C(1] + x*(C[2] + ••• x*C(d]»
The unsigned word degree operand specifies
coefficient to partiCipate in the evaluation.
. POLYH requires four longwords on the stack to
instruction is interrupted.
Notes:

the
store

highest

numbered

arg

case

the

Copyright(c) 19'79 Digital Equipment Corp.,Maynard,Mass.
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VAX-11 System Reference Manual
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Instructions
31-Jan-79 -- Rev 5
Page 4-62
FLOATING POINT INSTRUCTIONS
1.

After execution:
POLYF
RO = result
R1 = 0
R2 = 0
R3 = table address +

degree*4 + 4

POLYD and POLYG
RO = high order part of result
R1 = low order part of result
R2 = 0
R3 = table address + degree*8 + 8
R4 = 0
R5 = 0
POLYH
RO = highest order part of result
R1 = second highest order part of result
R2 = second lowest order part of result
R3 = lowest order part of result
R4 = 0
R5 = table address + degree*16 + 16
2.

On a floating fault:
1.

PSL<FPD> = 0 and the instruction faults, or

PSL<FPD> = and the instruction is suspended.
saved in the general registers as follows:

State

POLYF
RO = partial result after iteration prior to the
one causing the overflow/underflow
R1 = arg
R2<7:0) = tmp1 !number of iterations remaining
R2<31:8> = implementation specific
R3 = tmp2
!points to table entry causing exception
POLYD and POLYG
R1'RO = partial result after iteration prior to the
one causing the overflow/underflow
R2<7:0> = tmp1 !number of iterations remaining
R2<31:8> = implementation specific
R3 = tmp2
!points to table entry causing exception
R5'R4 = arg
POLYH
R3'R2'R1'RO = partial result after iteration prior to the
one causing the overflow/underflow
R4<7:0> = tmp1 !number of iterations remaining

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VAX-11 System Reference Manual
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Instructions
31-Jan-19 -- Rev 5
Page 4-63
FLOATING POINT INSTRUCTIONS
R4<31:8> = implementation specific
R5 = tmp2
Ipoints to table entry causing exception
arg is on previous mode stack.
Implementation specific information is saved to allow the
instruction to continue after possible scaling of the
coefficients and partial result by a fault handler.

~~.~
The multiplication is perfor ed such that the preC1310n of the
p odu
a 31 bit
(POLYF), 63 bit (POLYD and POLYG), or 121 bit (POLYH) fraction~ .d'f!icbd,
kl tfby <&1>1..

If the unsigned word degree operand is 0, the result is C[O].

If the unsigned word degree operand
reserved operand exception occurs.

On a reserved operand exception:

greater

than

31,

if PSL<FPD> = 0, the reserved operand is either the degree
operand (greater than 31), or the argument operand, or some
coefficient.
-::
if PSL<FPD> = 1, the reserved operand is a coefficient, and
R3 (except for POLYH) or R5 (for POLYH) is pointing at the
value which caused the exception.

The state of the saved condition codes and the other
registers is UNPREDICTABLE.
If the reserved operand is
changed and the contents of the condition codes and all
registers are preserved, the fault is continuable.

On floating underflow after the rounding operation,
the
temporary result (tmp3) is replaced by zero (always on the
original VAX-111180; and only if FU is clear on all other VAX
processors), and the operation continues.
On the original
VAX-11/780, if FU is set a floating underflow trap occurs at
the end of the instruction if underflow occurred during any
iteration of the computation loop. Note that the final result
may
be non zero if underflow occurred before the last
iteration. On all other VAX processors, if FU is set a
floating underflow fault occurs immediately.

On floating overflow after the rounding operation at any
iteration of the computation loop, the instruction terminates
and causes a trap (on the original VAX-11/780) or fault (on all~1
other VAX processors).
On overflow traps the contents of~R2
and R3 are UNPREDICTABLE for POLYF, ~, ~~, and zero
for POLYH;
the contents of A and ~ are UNPREDICTABLE for
POLYD, ~£IS, alit! Pi II :tif, RO co~ains \the reserved operand
(minus 0) and R1 = O.
~~

~"v

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Instructions
31-Jan-79 -- Rev 5
Page 4-64
FLOATING POINT INSTRUCTIONS
9.

~10.
11 .

POLY can have both over- and underflow in the same instruction.
If both occur, the overflow exception is taken; underflow is
lost.
If the argument is zero and one of the coefficients in the
table is the reserved operand., whether a reserved operand faul t
occurs is UNPREDICTABLE.
For POLYH, some implementations may not push arg on the stack
until after an interrupt or fault occurs. However, arg will
always be on the stack if an interrupt or floating fault occurs
after FPD is set.

Example:
To compute P(x)
where CO = 1.0,
POLYF

PTABLE: .FLOAT
• FLOAT
. FLOAT

= CO + C1*x + C2*x**2
C1 = .5, and C2 = .25
X,#2,PTABLE

0.25
0.5
1 .0

;C2
;C1
;CO

CHAPTER 4
INSTRUCTIONS

30-Nov-18 -- Rev 5

**********************************.********************

*
* THROW THIS PAGE AWAY.
*
*
*
*
* This is the third part of Chapter 4.
*
*
*
****1 COMPANY CONFIDENTIAL ****
*
*
************************************1********************

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

VAX-11 Miscellaneous and Control Instructions -- Rev 5

Specification Status:

Fully Approved

Architectural Status:

under ECO control

File:

Page 1

SR4CR5.RNO

PDM Ii: not used
Date:

30-Nov-78

Superseded Specs:

Rev 4

Author:

Strecker

Typist:

Call

Reviewer(s):

Abstract:

R. Blair, R. Brender, D. Cane, K. Chapman, P. Conklin,
D. Cutler, R. Grove, T. Hastings, D. Hustvedt, J. Leonard,
P. Lipman, M. Payne, D. Rodgers, S. Rothman, B. Stewart,
B. Strecker

Chapter 4 describes the instructions generally used by all
software
across
all
implementations
of
the
VAX-11
architecture.
For convenience of review and
editting,
chapter 4 is separated into a number of specifications. This
specification contains the address, variable length bit
field, control, miscellaneous, and queue instructions.

ReVision History:
Rev II
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5

Description
Initial distribution of SRM
ECOs 1-11
ECOs 12-18, April Meeting,
and May 25 Meeting
ECO's
ECO's

Author
Strecker
Strecker
S'trecker

Revised Date
25-Sep- 75
16-Mar-'16
10-Jun-'16

Strecker
Bhandarkar

31-Mar-77
30-Nov-78

Instructions
30-Nov-78 -- Rev 5
Change History for Miscellaneous and Control

Page 4-990

Rev 4 to Rev 5:
1.

Add following instructions:
7EFD

MOVAH Move Address H_floating

7EFD

MOVAO Move Address Octa

7FFD

PUSHAH Push Address H_floating

7FFD

PUSHAO Push Address Octa

4FFD

ACBG

Add Compare and Branch G_floating

6FFD

ACBH

Add Compare and Branch H_floating

Fix variable bit field description

Add interlocked self-relative queue instructions

Change INSV condition codes
1.

INSQHI

INSQl'I

REMQHI

REMQTI

Rev 3 to Rev 4:
1•

Correct Opcode Assignments.

CF to FP (FP ECO).

CALL Standard ECO.

Add INDEX instruction (INDEX ECO).

Expand descriptions of XFC, HALT, and BPT.

Motivate call frame, etc.

Clear T on CALL (T bit ECO).

Reverse incorrect opcode assignments of FFC, FFS.

Note that FFC/FFS conditon codes had been changed between rev 2
and rev 3.

Rev 2 to Rev 3:

Page 4-991

Instructions
30-Nov-78 -- Rev 5
Change History for Miscellaneous and Control
1.

Reserved operand aborts become faults

Change BLS and BLC to BLBS and BLBC

Change number of bytes referenced
field from 1 to zero

Change HALT in non-kernel mode to privileged instruction fault

Change BPT to Breakpoint fault

Change MOVPSW TO MOVPSL

Add Queue instructions

Change pointer to longword or address;

Add MINU function in ISP

10.

Explicitly give SEXT or ZEXT in all cases needed

11.

Specified condition codes on all exceptions

12.

Remove CMPA, DIFA, ADTA, SBFA

13.

Include pos(31) in Field

14.

Correct operand type typos in Field

15.

Change conditional branches per ECO 17

16.

Add BBSSI, BBCCI

17.

In ACBx, SOBxx, AOBxx set N, Z, V from the add

18.

Change names to AOBLEQ, AOBLSS, SOBGEQ, SOBGTR

19.

Specify branch behavior on overflow ACBx, AOBxxx, SOBxxx

20.

In CALLS, CALLG remove DZ, F'V; set DV,
clear FU; remove ring crossing

21.

BISPSW, BICPSW takes reserved operand fault

22.

Remove MSx, MSPx

23.

Split into separate specifications

access

zero

length

make it 32 bits

from

entry

mask;

Instructions
30-Nov-78 -- Rev 5
Change History for Miscellaneous and Control
Rev 1 to Rev 2:
See CH4A for changes
[End of SR4CR5.RNO]

Page 4-992

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Instructions
30-Nov-18 -- Rev 5
Page 4-65
ADDRESS INSTRUCTIONS
4.4

ADDRESS INSTRUCTIONS
MOVA

Move Address

Format:
opcode src.ax, dst.wl
Operation:
dst <- src;
Condit-ion Codes:
N <-

dst LSS 0;

Z <- dst EQL 0;

V <- O·,
C <- C;
Exceptions:
none
Opcodes:

MOVAB Move Address Byte
MOVAW Move Address Word
MOVAL, Move Address Long
MOVAF Move Address F_floating
MOVAQ, Move Address Quad
7E
MOVAD, Move Address D_floating
MOVAG Move Address G_floating
1EFD MOVAH Move Address H_floating,
MOVAO Move Address Octa
9E
3E
DE

Description:
The destination operand is replaced by the source operand. The context
in which the source operand is evaluated is given by the data type of
the instruction. The operand whose address replaces the destination
operand is not referenced.
Notes:
The source operand is of address access type which causes the address of
the specified operand to be moved.

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Instructions
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Page 4-66
ADDRESS INSTRUCTIONS

PUSHA

Push Address

Format:
o pcode src. ax
Operation:
-(SP) <- src;
Condition Codes : / ' /
N <- ((sii:-)~,~~SS 0;
Z <- \(SP)jEQL 0;

V <- {};.-./
C <- C;

Exceptions:
none
Opcodes:
9F
3F
DF
1F
1FFD

PUSHAB Push Address Byte
PUS HAW Push Addt,~ss Word
PUSHAL, Push Address Long
PUSHAF Push Address F_floating
PUSHAQ, Push Address Quad
PUSHAD, Push Address D_floating
PUS HAG Push Address G_floating
PUSHAH Push Address H_floating,
PUSHAO Push Address Octa

Description:
The source operand is pushed on the stack. The context in which the
source
operand is evaluated is given by the data type of the
instruction. The operand whose address is pushed is not referenced.
Notes:
1.

PUSHAx src is equivalent to MOVAx src, -(SP),
shorter.

but

The source operand is of address access type which
address of the specified operand to be pushed.

byte

causes

the

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VARIABLE LENGTH BIT FIELD INSTRUCTIONS
4.5

VARIABLE LENGTH BIT FIELD INSTRUCTIONS

A variable length bit field is specified by 3 operands:
1.

A longword p~sition operand.

A byte field size operand which must be in the range 0
32 or a reserved operand fault occurs.

A base address (relative to which the position is used to
locate the bit field). The address is obtained from an operand
of address access type. However, unlike other instances of
operand specifiers of address access type, register mode may be
designated in the operand specifier. In this case the field is
contained in the register n designated by the operand specifier
(or register n+1 concatenated with register n).
(See Chapter
2) If the field is contained in a register and size is not
zero, the position operand must have a value in the range 0
through 31 or a reserved operand fault occurs.

through

In order to simplify the description of the variable bit field
instructions, a macro FIELD(pos, Size, address) is introduced with the
following expansion (if size NEQ 0):
FIELD(pos, size, address)
=(address + SEXT{pos<31:3»)<{size - 1} + pos<2:0>:pos<2:0»
lif address not specified by register mode
= {R[n+1]'RnJ<{size - 1} + pos:pos>
lif address specified by register mode and pos + size
!GTRU 32
= Rn<{size - 1} + pos:pos>
lif address specified by register mode and pos + size
!LEQU 32
The number of bytes referenced by the contents ( ) operator
above is:
1 +

{{{size - 1} + pos<2:0>} / 8}

Zero bytes are referenced if the field size is O.

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VARIABLE LENGTH BIT FIELD INSTRUCTIONS

EXT

Extract Field

Format:
opcode pos.rl, size.rb, base.ab, dst.wl
Operation:
dst <- if size NEQU 0 then SEXT(FIELD(pos, size, base»
else 0;
IEXTV
dst <- if size NEQU 0 then ZEXT(FIELD(pos, size, base»)
else 0;
I EXTZV
Condition Codes:
N <-

dst LSS 0;
Z <- dst EQL 0;
V <- 0;
C <- C;

Exceptions:
reserved operand
Opcodes:
EE
EF

EXTV
EXTZV

Extract Field
Extract Zero-Extended Field

Description:
For EXTV, the destination operand is replaced by the sign extended field
specified by the position, size, and base operands. For EXTZV, the
destination operand is replaced by the zero extended field specified by
the position, size and base operands. If the size operand is 0, the
only action is to replace the destination operand with 0 and affect the
condition codes.
Notes:
1.

A reserved operand fault occurs if:
1.

size GTRU 32.

pos GTRU 31, size NEQ 0, and the field is contained in
registers.

the

On a reserved operand fault, the destination operand
unaffected and the condition codes are UNPREDICTABLE.

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VARIABLE LENGTH BIT FIELD INSTRUCTIONS

INSV

Insert Field

Format:
opcode src.rl, pos.rl, size.rb, base.ab
Operation:
if size NEQU 0 then FIELD(pos, size, base) <src<{size - 1}:0>;
Condition Codes:
N <- N;

Z <- Z;
V <- Vj
C <- Cj

Exceptions:
reserved operand
Opcodes:
FO

INSV

Insert Field

Description:
The field specified by the position, size, and base operands is replaced
by bits size-1:0 of the source operand. If the size operand is 0, the
only action is to affect the condition codes.
Notes:
1.

A reserved operand fault occurs if:
1.

size GTRU 32.

pos GTRU 31, size NEQ 0, and the field is contained in
registers.

On a reserved operand fault, the field is
condition codes are UNPREDICTABLE.

unaffected

and

the

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VARIABLE LENGTH BIT FIELD INSTRUCTIONS

CMP

Compare Field

Format:
opcode pos.rl, size.rb, base.ab, src.rl
Operation:
tmp <- if size NEQU 0 then SEXT(FIELD (pos,
size, base» else OJ
!CMPV
tmp - src;
tmp <- if size NEQU 0 then ZEXT(FIELD (pos,
size, base» else 0;
I CMPZV
tmp - src;
Condition Codes:
N <- tmp LSS src;
Z <- tmp EQL src;

V <- 0;
C <- tmp LSSU src;
Exceptions:
reserved operand
Opcodes:
EC
ED

CMPV
CMPZV

Compare Field
Compare Zero-Extended Field

Description:
The field specified by the position, size and base operands is compared
with the source operand. For CMPV, the source operand is compared with
the sign extended field. For CMPZV, the source operand is compared with
the zero extended field.
The only action is to affect the condition
codes.
Notes:
1.

A reserved operand fault occurs if:
1.

size GTRU 32.

pos GTRU 31, size NEQ 0, and the field is contained in
registers.

the

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VARIABLE LENGTH BIT FIELD INSTRUCTIONS
2.

On a reserved
UNPREDICTABLE.

operand

fault,

the

condition

codes

are

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VARIABLE LENGTH BIT FIELD INSTRUCTIONS

Find First

Format:
opcode startpos.rl, size.rb, base.ab, findpos.wl
Operation:
state = if {FFS} then 1 else 0;
if size NEQU 0 then
begin
tmp1 <- FIELD(startpos, size, base);
tmp2 <- 0;
while {tmp1<tmp2> NEQ state} AND
{tmp2 LEQU {size - 1}} do
tmp2 <- tmp2 + ,1;
findpos <- startpos + tmp2;
end
else
findpos <- startpos;
Condition Codes:
N <- 0;

Z <- {bit not found};
V <- 0;

C <- 0;

Exceptions:
reserved operand
Opcodes:
EB
EA

FFC
FFS

Find First Clear
Find First Set

Description:
A field specified by the start position, size, and base operands is
extracted.
The field is tested for a bit in the state indicated by the
instruction starting at bit 0 and extending to the highest bit in the
field.
If a bit in the indicated state is found, the find position
operand is replaced by the position of the bit and the Z condition code
bit is cleared.
If no bit in the indicated state is found, the find
position operand is replaced by the position (relative to the base) of a
bit one position to the left of the ,specified field, and the Z condition
code bit is set. If the size operand is 0, the find position operand is
replaced by the start position operand and the Z condition code bit is
set.

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VARIABLE LENGTH BIT FIELD INSTRUCTIONS
Notes:
1.

A reserved operand fault occurs if:
1•

size GTRU 32.

startpos GTRU
registers.

s.'"1' Nell

-ti
in

the

On a reserved operand fault, the find position operand
unaffected and the condition codes are UNPREDICTABLE.

31 I:nd

the

field

contained

)

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CONTROL INSTRUCTIONS
4.6

CONTROL INSTRUCTIONS

In most implementations of the VAX-11 architecture, improved execution
speed will result if the target of a control instruction is on an
aligned longword boundary.

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CONTROL INSTRUCTIONS

Branch on (condition)

Format:
opcode displ. bb
Operation:
if condition then PC <- PC + SEXT(displ);
Condition Codes:
N <- N;
Z <-

z·,

V <- V·,
C <- C·,
Exceptions:
none
Opcodes:

Condition

{N OR z} EQL 0

{N OR z} EQL

Z EQL 0

Z EQL

N EQL 0

19
1A

N EQL 1
{C OR z} EQL 0

{C OR Z} EQL

1C
1D
1E

V EQL 0
V EQL 1
C EQL 0

C EQL 1

BGTR

Branch on Greater Than
(signed)
BLEQ
Branch on Less Than or Equal
(signed)
BNEQ,
Branch on Not Equal (signed)
BNEQU
Branch on Not Equal Unsigned
BEQL,
Branch on Equal (signed)
BEQLU
Branch on Equal Unsigned
BGEQ
Branch on Greater Than or
Equal (signed)
Branch on Less Than (signed)
BLSS
BGTRU Branch on Greater Than
Unsigned
Branch Less Than or Equal
BLEQU
Unsigned
BVC
Branch on Overflow Clear
Branch on Overflow Set
BVS
BGEQU, Branch on Greater Than or
Equal Unsigned
BCC
Branch on Carry Clear
BLSSU, Branch on Less Than Unsigned
BCS
Branch on Carry Set

Description:
The condition codes are tested and i.f the condition indicated by the
instruction· is met, the sign-extended branch displacement is added to
the PC and PC is replaced by the result.

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CONTROL INSTRUCTIONS
Notes:
The VAX-11 conditional
branch
instructions
permit
considerable
flexibility in branching but require care in choosing the correct branch
instruction. The conditional branch instructions are best seen as 3
overlapping groups:
1.

Overflow and Carry Group
BVS
BVe
BCS
BCC

V EQL 1
V EQL 0
C EQL 1
C EQL 0

These instructions are typically used to check for overflow
(when overflow traps are· not enabled), for multiprecision
arithmetic, and for other special purposes.
2.

Unsigned Group
BLSSU
BLEQU
BEQLU
BNEQU
BGEQU
BGTRU

C EQL 1
{C OR Z} EQL 1
Z EQL 1
Z EQL 0
C EQL 0
{C OR Z} EQL 0

These instructions typically
follow
integer
and
field
instructions
where the operands are treated as unsigned
integers,
address
string
instructions,
and
character
instructions.

Signed Group
BLSS
BLEQ
BEQL
BNEQ
BGEQ
BGTR

N EQL 1
{N OR Z} EQL 1
Z EQL 1
Z EQL 0
N EQL 0
{N OR Z} EQL 0

These instructions
instructions where
integers, floating
instructions.

typically
follow
integer
and
field
the operands are being treated as signed
point instructions, and decimal string

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CONTROL INSTRUCTIONS

Branch

Format:
opcode displ. bx
Operation:
PC <- PC + SEXT(displ);
Condition Codes:
N <- N;

Z <- Z;

V <- Vi

C <- C;
Exceptions:
none
Opcodes:
11
31

BRB
BRW

Branch With Byte Displacement
Branch With Word Displacement

Description:
The sign-extended branch displacement is added to PC and PC is
by the result.

replaced

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CONTROL INSTRUCTIONS

JMP

Jump

Format:
opcode dst .ab
Operation:
PC <- dst;
Condition Codes:
N <- N;
Z <- Zj

V <- Vj
C <- C;

Exceptions:
none
Opcodes:
17

JMP

Jump

Description:
PC is replaced by the destination operand.

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CONTROL INSTRUCTIONS

Branch on Bit

Format:
opcode p0s.rl, base.ab, displ.bb
Operation:
teststate = if {BBS} then 1 else 0;
if FIELD(pos, 1, base) EQL teststate then
PC <- PC + SEXT(displ);
Condition Codes:

N <- N;
Z <- Z;
V <- V;
C <- C;
Exceptions:
reserved operand
Opcodes:
EO
E1

BBS
BBC

Branch on Bit Set
Branch on Bit Clear

See Section 4.5 for definition of FIELD.

A reserved operand fault occurs if pos GTRU 31 and the
contained in a register.

On a reserved
UNPREDICTABLE.

operand

fault,

the

condition

bit

codes

is
are

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CONTROL INSTRUCTIONS

Branch on Bit (and modify without interlock)

Format:
opcode pos.rl, base.ab, displ.bb
Operation:
teststate = if {BBSS or BBSC} then 1 else 0;
newstate = if {BBSS or BBCS} then 1 else 0;
tmp <- FIELD(pos, 1, base);
FIELD(pos, 1, base) <- ne~state;
if tmp EQL teststate then
PC <- PC + SEXT(displ);
Condition Codes:
N <- Nj
Z <-

V <- Vi

C <- C·,

Exceptions:
reserved operand
Opcodes:
E2
E3
E4
E5

BBSS
BBCS
BBSC
BBCC

Branch on Bit Set and Set
Branch on Bit Clear and Set
Branch on Bit Set and Clear
Branch on Bit Clear and Clear

See Section 4.5 for definition of FIELD.

A reserved operand fault occurs if pos GTRU 31 and the
contained in a register.

bit

On a reserved operand fault, the field is
condition codes are UNPREDICTABLE.

and

the

unaffected

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CONTROL INSTRUCTIONS
4.

The modification of the bit is not an interlocked
See BBSSI and BBCCI for interlocking instructions.

operation.

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CONTROL INSTRUCTIONS
BB

Branch on Bit Interlocked

Format:
opcode pos.rl, base.ab, displ.bb
Operation:
teststate = if {BBSSI} then 1 else 0;
newstate = teststate;
{set interlock};
tmp <- FIELD(pos, 1, base);
FIELD(pos, 1, base) <- newstate;
{release interlock};
if tmp EQL teststate then
PC <- PC + SEXT(displ);
Condition Codes:

N <- N;
Z <- Z;
V <- V;
C <- C;
Exceptions:
reserved operand
Opcodes:
E6
E7

BBSSI Branch on Bit Set and Set Interlocked
BBCCI Branch on Bit Clear and Clear Interlocked

Description:
The single bit field specified by the position and base operands is
tested.
If it is in the test state indicated by the instruction, the
sign-extended branch displacement is added to the PC and PC is replaced
by the result. Regardless of whether the 'branch is effected or not, the
tested bit is put in the new state as indicated by the instruction.
If
the bit is contained in memory, the reading of the state of the bit and
the setting of it to the new state is an interlocked operation.
No
other processor or 1/0 device can do an interlocked access on the bit
during the interlocked operation.
Notes:
1.

See Section 4.5 for definition of FIELD

A reserved operand fault occurs if pas GTRU 31 and the
contained in registers.

bit

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CONTROL INSTRUCTIONS

On a reserved operand fault, the field is
condition codes are UNPREDICTABLE.

and

the

Except for memory interlocking BBSSI is equivalent to BBSS
BBCCI is equivalent to BBCC.

and

This instruction is designed to modify interlocks with
processors
or devices.
For example, to implement
waiting":

other
"busy

1$:

BBSSI

bit,base,1$

unaffected

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CONTROL INSTRUCTIONS

BLB

Branch on Low Bit

Format:
opcode src.rl, displ.bb
Operation:
teststate = if {BLBS} then 1 else 0;
if src<O> EQL teststate then
PC <- PC + SEXT(displ);
Condition Codes:
N <- N;

Z <- Z;
V <- V;
C <- C;
Exceptions:
none
Opcodes:
E8
E9

BLBS
BLBC

Branch on Low Bit Set
Branch on Low Bit Clear

Description:
The low bit (bit 0) of the source operand is tested and if it is equal
to the test state indicated by the instruction, the sign-extended branch
displacement is added to PC and PC is replaced by the result.

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CONTROL INSTRUCTIONS

ACB

Add Compare and Branch

Format:
opcode limit.rx, add.rx, index.mx, displ.bw
Operation:
index <- index + add;
if {{add GEQ O} AND {index LEQ limit}} OR
{{add LSS O} AND {index GEQ limit}} then
PC <- PC + SEXT(displ);
Condition Codes:
N <- index LSS 0;
Z <- index EQL 0;
V <- {integer or floating overflow};
C <- C;
Exceptions:
integer overflow
floating overflow
floating underflow
reserved operand
Opcodes:
9D
ACBB
3D
ACBW
F1
ACBL
4F
ACBF
6F
ACBD
4FFD ACBG
6FFD ACBH

Add Compare and Branch Byte
Add Compare and Branch Word
Add Compare and Branch Long
Add Compare and Branch F_floating
Add Compare and Branch D_floating
Add Compare and Branch G_floating
Add Compare and Branch H_floating

Description:
The addend operand is added to the index operand and the index operand
is replaced by the result. The index operand is compared wit~ the limit
operand. If the addend operand is positive (or 0) and the comparison is
less than or equal or if the addend is negative and the comparison is
greater than or equal, the sign-extended branch displacement is added to
PC and PC is replaced by the result.

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CONTROL INSTRUCTIONS
Notes:
1.

ACB efficiently implements the general FOR or DO loops in high
level languages since the sense of the comparison between index
and limit is dependent on the sign of the addend.

On integer overflow, the index operand is replaced by the low
order
bits
of the true result.
Comparison and branch
determination proceed normally on the updated index operand.

On floating underflow, the index operand is replaced by
(always on the original VAX-11/780 and only if FU is clear on
all other VAX processors);
and
comparison
and
branch
determination proceed normally. On the original VAX-11/780, a
trap occurs at the end of the instruction if FU is set. On all
other VAX processors, a fault occurs if FU is set and the index
operand is unaffected.

On floating overflow, on the original VAX-11/780, the index
operand is replaced by an operand of all bits
except for a
sign bit of 1 (a reserved operand); N<-1, Z<-O, V<-1; and the
branch is not taken.
On all other VAX processors, the
instruction takes a floating overflow fault and the index
operand is unaffected.

On a reserved operand fault, the index operand
and the condition codes are UNPREDICTABLE.

Except for 5.

above, the C-bit is unaffected.

unaffected

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CONTROL INSTRUCTIONS

AOBLEQ

Add One and Branch Less Than or Equal

Format:
opcode'limit.rl, index.ml, displ.bb
Operation:
index <- index + 1;
if index LEQ limit then PC <PC + SEXT(displ)j
Condition Codes:
N <- index LSS 0;
Z <- index EQL 0;
V <- {integer overflow};
C <- C;
Exceptions:
integer overflow
Opcodes:
F3

AOBLEQ

Add One and Branch Less Than or Equal

Description:
One is added to the index operand and the index operand is replaced by
the result.
The index operand is compared with the limit operand. If
it is less than or equal, the sign-extended branch displacement is added
to PC and PC is replaced by the result.
Notes:
1.

Integer overflow occurs if the index operand before addition is
the largest positive integer. On overflow, the index operand
is replaced by the largest negative integer, and the branch is
taken.

The C-bit is unaffected.

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CONTROL INSTRUCTIONS

AOBLSS

Add One and Branch Less Than

Format:
opcode limit.rl, index.ml, displ.bb
Operation:
index <-index + 1;
if index LSS limit then PC <PC + SEXT(displ);
Condition Codes:
N <- index LSS 0;
Z <- index EQL 0;
V <- {integer overflow};
C <- C;
Exceptions:
integer overflow
Opcodes:
F2

AOBLSS

Add One and Branch Less Than

Description:
One is added to the index operand and the index operand is replaced by
the result.
The index operand is compared with the limit operand. If
it is less than, the sign-extended branch displacement is added to the
PC and PC is replaced by the result.
Notes:
1.

Integer overflow occurs if the index operand before addition is
the largest positive integer. On overflow, the index operand
is replaced by the largest negative integer, and thus (unless
the limit operand is the largest negative integer) the branch
is taken.

The C-bit is unaffected.

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CONTROL INSTRUCTIONS

SOBGEQ

Subtract One and Branch Greater Than or Equal

Format:
opcode index.ml, displ.bb
Operation:
index <- index - 1;
if index GEQ 0 then PC <PC + SEXT(displ);
Condition Codes:
N <- index LSS 0;
Z <- index EQL 0;
V <- {integer overflow};
C <- C;
Exceptions:
integer overflow
Opcodes:
F4

SOBGEQ

Subtract One and Branch Greater Than or Equal

Description:
One is subtracted from the index oper9-nd and the index operand is
replaced by the result. If the index operand is greater than or equal
to 0, the sign-extended branch displacement is added to PC and PC is
replaced by the result.
Notes:
1.

Integer overflow occurs if the index operand before subtraction
is the largest negative integer.
On overflow, the index
operand is replaced by the largest positive integer, and thus
the branch is taken.

The C-bit is unaffected.

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CONTROL INSTRUCTIONS

SOBGTR

Subtract One and Branch Greater Than

Format:
opcode index.ml, displ.bb
Operation:
index <- index - 1;
if index GTR 0 then PC <PC + SEXT(displ);
Condition Codes:
N <- index LSS 0;
Z <- index EQL 0;
V <- {integer overflow};
C <- C;
Exceptions:
integer overflow
Opcodes:
F5

SOBGTR

Subtract One and Branch Greater Than

Description:
One is subtracted from the index operand and the index operand is
replaced by the result.
If the index operand is greater than 0, the
sign-extended branch displacement is added to PC and PC is replaced by
the result.
Notes:
1.

Integer overflow occurs if the index operand before subtraction
is the largest negative integer.
On overflow, the index
operand is replac~d by the largest positive integer, and thus
the branch is taken.

The C-bit is unaffected.

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CONTROL INSTRUCTIONS

CASE

Case

Format:
opcode selector.rx, base.rx, limit.rx,
displ[O].bw, ... , displ[limit].bw
Operation:
tmp <- selector - base;
PC <- PC + if tmp LEQU limit then
SEXT(displ[tmp]) else {2 + 2 * ZEXT(limit)};
Condition Codes:

N <- tmp LSS limit;
Z <- tmp EQL limit;
V <- 0;
C <- tmp LSSU limit;
Exceptions:
none
Opcodes:
8F
AF
CF

CASEB
CASEW
CASEL

Case Byte
Case Word
Case Long

Description:
The base operand is subtracted from the selector operand and a temporary
is replaced by the result. The temporary is compared with the limit
operand and if it is less than or equal unsigned, a branch displacement
selected by the temporary value is added to PC and PC is replaced by the
result. Otherwise, 2 times the sum of the limit operand and 1 is added
to PC and PC is replaced by the result. This causes PC to be moved past
the array of branch displacements. Regardless of the branch taken, the
condition codes are affected by the comparison of the temporary operand
with the limit operand.
Notes:
1.

After operand evaluation, PC is pointing at displ[O], not the
next instruction. The branch displacements are relative to the
address of displ[O].

The selector and base operands can both be considered either as
signed or unsigned integers.

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CONTROL INSTRUCTIONS

BSB

Branch To Subroutine

Format:
opcode displ. bx
Operation:
-(SP) <- PC;
PC <- PC + SEXT(displ);
Condition Codes:
N <-

Z <- Z;

V <- V;
C <- C;
Exceptions:
none
Opcodes:
10
30

BSBB
BSBW

Branch to Subroutine With Byte Displacement
Branch to Subroutine With Word Displacement

Description:
PC is pushed on the stack as a longword.
The sign-extended
displacement is added to PC and PC is replaced by the result.

branch

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CONTROL INSTRUCTIONS

JSB

Jump to Subroutine

Format:
opcode dst .ab
Operation:
-(SP) <- PC;
PC <- dstj
Condition Codes:
N <- N;

Z <- Z;
V <- V;
C <- C;

Exceptions:
none
Opcodes:
16

JSB

Jump to Subroutine

Description:
PC is pushed on the stack
destination operand.

longword.

replaced

the

Notes:
Since the operand specifier conventions cause the evaluation of the
destination operand before saving PC, JSB can be used for coroutine
calls with the stack used for linkage. The form of such a call is JSB
@(SP)+.

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CONTROL INSTRUCTIONS

RSB

Return from Subrou~ine

Format:
Qpcode
Operation:
PC <- (SP)+;
Condition Codes:
N <- N;

Z <- Z;

V <- V;
C <- C;
Exceptions:
none
Opcodes:
RSB

Return From Subroutine

Description:
PC is replaced by a longword popped from the stack.
Notes:
1.

RSB is used to return from subroutines called by the BSBB, BSBW
and JSB instructions.

RSB is equivalent to JMP @(SP)+, but is 1 byte shorter.

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PROCEDURE CALL INSTRUCTIONS
4.7

PROCEDURE CALL INSTRUCTIONS

Three instructions are used to implement a standard procedure calling
interface.
Two instructions implement the CALL to the procedure; the
third implements the matching RETURN.
Refer to Appendix C for the
procedure calling standard.
The CALLG instruction calls a procedure
with the argument list actuals in an arbitrary location.
The CALLS
instruction calls a procedure with the argument list actuals on the
stack. Upon return after a CALLS this list is automatically removed
from the stack. Both call instructions specify the address of the entry
point of the procedure being called. The entry point is assumed to
consist of a word termed the entry mask followed by the procedure's
instructions. The procedure terminates by executing a RET instruction.
The entry mask specifies the subprocedure's register
enables:
1 1 111
5 432 1

use

and

overflow

+-+-+---+-----------------------+
:DIIIMBZI
REGISTERS
:V IV:

+-+-+---+-----------------------+
On CALL the stack is aligned to a longword boundary and the trap enables
in the PSW are set to a known state to ensure consistent behavior of the
called procedure. Integer overflow enable and decimal overflow enable
are affected according to bits 14 and 15 of the entry mask respectively.
Floating underflow enable is cleared.
The registers R11 through RO specified by bits 11 through 0 respectively
are saved on the stack and are restored by the RET instruction. The
procedure calling standard requires that all registers in the range R2
through R11 used in the procedure must appear in the mask. In addition,
the CALL instructions always preserve PC, SP, FP, and AP.
Thus, a
procedure can be considered as equivalent to a complex instruction which
stores a value into RO and R1, affects memory, and clears the condition
codes.
If the procedure has no function value, the contents of RO and
R1 can be considered as UNPREDICTABLE.
In order to preserve the state, the CALL instructions form a structure
on the stack termed a call frame or stack frame. This contains the
saved registers, the saved PSW, the register save mask, and several
control bits.
The frame also includes a longword which the CALL
instructions clear; this is used to implement the condition handling
facility.
Refer to Appendix D. At the end of execution of the CALL
instruction, FP contains the address of the stack frame.
The RET
instruction uses the contents of FP to find the stack frame and restore
state. The condition handling facility assumes that FP always points to
the stack frame. The stack frame has the following format:

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PROCEDURE CALL INSTRUCTIONS

+---------------------------------------------------------------+
:(FP)
I
condition handler (initially 0)
I~
+---+-+-+-----------------------+---------------------+---------+
ISPAISIOI
mask(11:0>
I
PSW<15:5>
0
I
+---+-+-+-----------------------+---------------------+---------+
saved AP
+---------------------------------------------------------------+
I
saved FP
I
+---------------------------------------------------------------+
saved PC
+---------------------------------------------------------------+
saved RO ( ... )
I
+---------------------------------------------------------------+
+---------------------------------------------------------------+
saved R11 (...)
+---------------------------------------------------------------+
(0 to 3 bytes specified by SPA)
S = set if CALLS; clear if CALLG.
Note that the saved condition codes are cleared. The contents of the
frame PSW(3:0> at the time RET is executed will become the condition
codes resulting from the execution of the procedure.
Similarly, the
saved trace enable (PSW(T» is cleared.

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PROCEDURE CALL INSTRUCTIONS

CALLG

Call Procedure With General Argument List

Format:
opcode arglist.ab, dst.ab
Operation:
tmp2 <- (dst);
tmp1 <- SP;
SP<1:0> <- 0;
for tmp3 <- 11 step -1 until 0 do
if tmp2<tmp3> EQL 1 then
-(SP) <- R[tmp3];
-(SP) <- PC;
-(SP) <- FP;
-(SP) <- AP;
PSW<N,Z,V,C> <- 0;
-(SP) <- tmp1<1:0>'0'0'tmp2<11:0>'PSW<15:5>'0<4:0>;
-(SP) <- 0;
FP <- SP;
AP <- arglist;
PSW<DV> <- tmp2<15>;
PSW<IV> <- tmp2<14>;
PSW<FU> <- 0;
PC <- dst + 2;
Condition Codes:
N <- 0;

Z <- 0;

V <- 0;

C <- 0;

Exceptions:
reserved operand
Opcodes:
FA

CALLG

Call Procedure with General Argument List

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PROCEDURE CALL INSTRUCTIONS
Description:

SP is saved in a temporary and then bits 1:0 are replaced by
so that
the stack is longword aligned. The procedure entry mask is scanned from
bit 11 to 0 and the contents of registers whose number corresponds to
set bits in the mask are pushed on the stack as longwords. PC, FP, and
AP are pushed on the stack as longwords.
The condition codes are
cleared;
A longword containing the saved two low bits of SP in bits
31:30, a
in bit 29 and bit 28, the low 12 bits of the procedure entry
mask in bits 27:16, and the PSW in bits 15:0 with T cleared is pushed on
the stack. A longword 0 is pushed on the stack. FP is replaced by SP.
AP is replaced by the arglist operand. The trap enables in the PSW are
set to a known state.
Integer overflow, and decimal overflow are
affected according to bits 14 and 15 of the entry mask respectively;
floating underflow is cleared. T-bit is unaffected. PC is replaced by
the sum of destination operand plus 2 which transfers control to the
called procedure at the byte beyond the entry mask.

+---------------------------------------------------------------+ :(SP)
: (FP)
stack
:

frame

I
I

+---------------------------------------------------------------+
(0 to 3 bytes specified by SPA)
Notes:
1.

If bits 13:12 of the entry mask are not 0, a
fault occurs.

reserved

operand

On a reserved operand fault, condition codes are UNPREDICTABLE.

The procedure calling standard and the condition handling
facility require the following register saving conventions. flO
and R1 are always available for function return values and are
never saved in the entry mask. All registers R2 through R11
which are modified in the called procedure must be preserved in
the mask. Refer to Appendix C.

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PROCEDURE CALL INSTRUCTIONS

CALLS

Call Procedure with Stack Argument List

Format:
opcode numarg.rl, dst.ab
Operation:
tmp2 <- (dst);
-(SP) <- numarg;
tmp1 <- SP;
SP<1:0> <- 0;
for tmp3 <- 11 step -1 until 0 do
if tmp2<tmp3> EQL' 1 then
-(SP) <- R(tmp3];
-(SP) <- PC;
-(SP) <- FP;
-(SP) <- AP;
PSW<N,Z,V,C> <- 0;
-(SP) <- tmp1<1:0>'1'0'tmp2<11:0>'PSW<15:5>'0<4:0>;
-(SP) <- 0;
FP <- SP;
AP <- tmp1;
PSW<DV> <- tmp2<15>;
PSW<IV> <- tmp2<14>;
PSW<FU> <- 0;
PC <- dst + 2;
Condition Codes:

N <- 0;
Z <- 0;
V <- 0;
C <- 0;
Exceptions:
reserved operand
Opcodes:
FB

CALLS

Call Procedure With Stack Argument List

Description:
The numarg operand is pushed on the stack as a longword (byte 0 contains
the number of arguments, high order 24 bits are used by DIGITAL
software). SP is saved in a temporary and then bits 1:0 of SP are
replaced by 0 so that the stack is longword aligned. The procedure
entry mask is scanned from bit 11 to bit 0 and the contents of registers
whose number corresponds to set bits in the mask are pushed on the
stack. PC, FP, and AP are pushed on the stack as longworqs.
The

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PROCEDURE CALL INSTRUCTIONS
condition codes are cleared. A longword containing the saved two low
bits of SP in bits 31:30, a 1 in bit 29, a 0 in bit 28, the low 12 bits
of the procedure entry mask in bits 27:16, and the PSW in bits 15:0 with
T cleared is pushed on the s~ack. A longword 0 is pushed on the stack.
FP is replaced by SP. AP is set to the value of the stack pointer after
the numarg operand was pushed on the stack. The trap enables in the PSW
are set to a known state. Integer overflow, and decimal overflow, are
affected according to bits 14 and 15 of the entry mask, respectively,
floating underflow is cleared. I-bit is unaffected.PC is replaced by
the sum of destination operand plus 2 which transfers control to the
called procedure at the byte beyond the entry mask. The appearance of
the stack after CALLS is executed is:

+---------------------------------------------------------------+ :(SP)
:(FP)
stack
frame

+---------------------------------------------------------------+
(0 to 3 bytes specified by SPA)

+-----------------------------------------------+---------------+
N
:(AP)
+-----------------------------------------------+---------------+
N longwords of argument list

+---------------------------------------------------------------+
Notes:
1.

If bits 13:12 of the entry mask are not 0, a
fault occurs.

On a reserved
UNPREDICTABLE.

Normal use is to push the arglist onto the stack in reverse
order prior to the CALLS. On return, the arglist is removed
from the stack automatically.

The procedure calling standard and the condition handling
facility require the following register saving conventions. RO
and R1 are always available for function return values and are
never saved in the entry mask. All registers R2 through R11
which are modified in the called procedure must be preserved in
the entry mask. Refer to Appendix C.

operand

fault,

the

reserved

condition

operand

codes

are

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PROCEDURE CALL INSTRUCTIONS

'RET

Return from Procedure

Format:
opcode
Operation:
SP <- FP + 4;
tmp1 <- (SP)+;
AP <- (SP)+;
FP <- (SP)+;
PC <- (SP)+;
tmp2 <- tmp1<27:16>;
for tmp3 <- 0 step 1 until 11 do
i f tmp2<tmp3> EQL 1 then
R[tmp3] <- (SP)+;
SP <- SP + ZEXT{tmp1<31:30>}
PSW <- tmp1<15:0>;
i f tmp1<29> EQL 1 then
begin
tmp4 <- 4 * ZEXT({(SP)+}<7:0»;
SP <- sp + tmp4;
end;
Condition Codes:
N <- tmpl<3>;
Z <- tmpl <2>;
V <- tmp1<1>;
C <- tmp1 <0>;
Exceptions:
reserved operand
Opcodes:
04

RET

Return from Procedure

Description:
SP is replaced by FP plus 4. A longword containing stack alignment bits
in bits 31:30, a CALLS/CALLG flag in bit 29, the low 12 bits of the
procedure entry mask in bits 27:16, and a saved PSW in bits 15:0 is
popped from the stack and saved in a temporary. PC, CF, and AP are
replaced by longwords popped from the stack. A register restore mask is
formed from bits 27:16 of tbe temporary. Scanning from bit 0 to bit 11
of the restore mask, the contents of registers whose number is indicated
by set bits in the mask are replaced by longwords popped from the stack.
SP is incremented by 31:30 of the temporary. PSW is replaced by bits
15:0 of the temporary. If bit 29 in the temporary is 1 (indicating that

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PROCEDURE CALL INSTRUCTIONS
the procedure was called by CALLS), a longword containing the number of
arguments is popped from the stack. Four times the unsigned value of
the low byte of this longword is added to SP and SP is replaced by the
result.
Notes:
1.

A reserved operand fault occurs if tmp1(15:8> NEQ O.

On a reserved operand fault, the
condition
UNPREDICTABLE. The value of tmp1(28) is ignored.

The procedure calling standard and condition handling facility
assume that procedures which return a function value or a
status code do so in RO or RO and R1. See Appendix C.

codes

are

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MISCELLANEOUS INSTRUCTIONS
4.8

MISCELLANEOUS INSTRUCTIONS
BPT

Breakpoint Fault

Format:
opcode
Operation:
PSL<TP> <- 0;
{breakpoint fault};
Condition Cl)des:

N <- 0;
Z <- 0;
V <- 0;
C <- 0;
Exceptions:
none
Opcodes:
03

BPT

Breakpoint Fault

Description:
In order to understand the operation of this instruction, it is
necessary to read Chapter 6. This instruction is used, together with
the T-bit, to implement degugging facilities.

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MisCELLANEOUS INSTRUCTIONS

HALT

Halt

Format:
opcode
Operation:
If PSL<current_mode> NEQU kernel then
{privileged instruction fault}
else
{halt the processor};
Condition Codes:
N <- 0;
Z <- 0;

Ilf privileged instruction fault

V <- 0;
C <- 0;
N <-

N; IIf processor halt

Z <- Z;
V <- V;

C <- C;

Exceptions:
privileged instruction
Opcodes:
00

HALT

Halt

Description:
In order to understand the operation of this instruction it is necessary
to read Chapter 6.
If the process is running in kernel mode, the
processor is halted. Otherwise, a privileged instruction fault occurs.
Notes:
This opcode is 0 to trap many branches to data.

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MISCELLANEOUS INSTRUCTIONS

XFC

Extended Function Call

Format:
opcode
Operation:
{XFC faul t} ;
Condition Codes:

O·,
O·,
V <- O·,
C <- OJ

N <Z <-

Exceptions:
none
Opcodes:
FC

XFC

Extended Function Call

Description:
In order to understand the operation of this instruction, it is
necessary to read Chapter 6. This instruction provides for customer
defined extensions to the instruction set.

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MISCELLANEOUS INSTRUCTIONS

INDEX

Compute Index

opcode

su~script.rl, low.rl, high.rl,
size.rl, indexin.rl, indexout.wl

Format:

Operation:
/

indexout <- {indexin + subscript} *size;
if {sub~cript LSS low} or {subscript GTR high}
then {subscript range trap};
Condition Codes:
N <- indexout LSS 0;
Z <- indexout EQL 0;

V <- 0;
C <- 0;
Exceptions:
subscript range
Opcodes:
INDEX

index

Descriiption:
The indexin operand is added to the subscript operand and the sum
multiplied by the size operand. The indexout operand is replaced by the
result. If the subscript operand is less than the low operand or
greater than the high operand, a subscript range trap is taken.
Notes:
1.

No arithmetic exception other than subscript range can result
from this instruction. Thus no indication is given if overflow
occurs in either the add or multiply steps. If overfl~w occurs
on the add step the sum is the low order 32 bits of the true
result. If overflow occurs on the multiply step, the indexout
operand is replaced by the low order 32 bits of the true
product of the sum and the subscript operand.
In the normal
use of this ihstruction, overflow cannot occur without a
subscript range trap occurring.

The index instruction is useful in index calculations for
arrays of the fixed length data types (integer and floating)
and for index calculations for arrays of bit fields, character
strings, and decimal strings.
The indexin operand permits
cascading INDEX instructions for multidimensional arrays.
For

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MISCELLANEOUS INSTRUCTIONS
one-dimensional bit field arrays it also permits introduction
of the constant portion of an index calculation which is not
readily absorbed by address arithmetic. The following notes
will show some of the uses of INDEX.

The COBOL statements:
01

A-ARRAY.
02

A PIC X(10) OCCURS 15 TIMES.

B PIC X(10).

MOVE A(I) TO B.
could compile to:
INDEX I, H1, 115, 110, 10, HO
MOVC3 /110, A-10[RO], B.
4.

The PL/1 statements:
DCL A(-3:10) BIT (5);
A(I)

= 1;

could compile to:
INDEX I, H-3, 110, 15, 13, RO
INSV
5.

/11, RO, 15, A; assumes A byte aligned

The FORTRAN statements:
INTEGER*4 A(L1:U1, L2:U2), I, J
A(I,J) = 1
could compile to:
INDEX

J, IL2, HU2, IM1, HO, RO; M1=U1-L1+1

INDEX

I, IL1, IU1, #1, RO, RO;

MOVL

#1, A-a[RO]; a = {{L2*M1} + L1} *4

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MISCELLANEOUS INSTRUCTIONS

PUSHR

Push Registers

Format:
opcode mask.rw
Operation:
for tmp <- 14 step -1 until 0 do
if mask<tmp> EQL 1 then -(SP) <- R[tmp];
Condition Codes:

N <- N;
Z <- Z;
V <- V;

C <- C;

Exceptions:
none
Opcodes:
BB

PUSHR

Push Registers

Description:
The contents of registers whose number corresponds to set bits in the
mask operand are pushed on the stack as longwords. R[n] is pushed if
mask<n> is set. The mask is scanned from bit 14 to bit O.
Bit 15 is
ignored.
Notes:
The order of pushing is specified so that the contents of higher
numbered registers are stored at higher memory addresses. This results
in, say, a double floating datum stored in adjacent registers being
stored by PUSHR in memory in the correct order.

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POPR

Pop Registers

Format:
opcode mask.rw
Operation:
for tmp <- 0 step 1 until 14 do
if mask<tmp> EQL 1 then R[tmp] <- (SP)+;
Condition Codes:
N <- N;

Z <- Z;
V <- V;

·C <- C;

Exceptions:
none
Opcodes:
BA

POPR

Pop Registers

Description:
The contents of registers whose number corresponds to set bits in the
mask operand are replaced by longwords popped from the stack. R[n] is
replaced if mask<n> is set. The mask is scanned from bit 0 to bit 14.
Bit 15 is ignored.

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MOVPSL

Move from PSL

Format:
opcode dst.wl
Operation:
dst <- PSL;
Condition Codes:

N <- N;
Z <- Z;
V <- V;
C <- C;
Exceptions:
none
Opcodes:
DC

MOVPSL

Move from PSL

Description:
The destination operand is replaced by PSL (See Chapter 6).

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BISPSW

Bit Set PSw

Format:
opcode mask.rw
Operation:
PSW <- PSW OR mask;
Condition Codes:
N <- N OR mask<3>;
Z <- Z OR mask<2>;
V <- V OR mask<1>;
C <- C OR mask<O>;
Exceptions:
reserved operand
Opcodes:
B8

BISPSW·

Bi t Set PSW

Description:

PSW is ORed with the mask operand and PSW is replaced by the result.
Notes:

A reserved operand fault occurs if mask<15:8>
reserved operand fault, the PSW is not affected.

not

zero.

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BICPSW

Bit Clear PSW

Format:
opcode mask.rw
Operation:
PSW <- PSW AND {NOT mask};
Condition Codes:
N <- N AND {NOT mask<3>};
Z <- Z AND {NOT mask<2>};
V <- V AND {NOT mask<1>1;
C <- C AND {NOT mask(O>};
Exceptions:
reserved operand
Opcodes:
B9

BICPSW

Bit Clear PSW

Description:
PSW is ANDed with the ones complement of the mask
replaced by the result.

operand

and

PSW

zero.

Notes:
A reserved operand fault occurs if mask <15:8>
reserved operand fault, the PSW is not affected.

not

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NOP

No Operation

Format:
opcode
Operation:
none
Condition Codes:

N <- N·,
Z <- Z;
V <- V;
C <- C;
Exceptions:
none
Opcodes:
01

NOP

No Operation

Description:
No operation is performed.

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QUEUE INSTRUCTIONS
4.9

QUEUE INSTRUCTIONS

A queue is a circular, doubly linked list. A queue entry is specified
by its address.
Each queue entry is linked to the next via a pair of
longwords. The first longword is the forward link: it specifies the
location of the succeeding entry. The second longword is the backward
link: it specifies the location of the preceeding entry.
The VAX-11
supports two distinct types of links: absolute, and self-relative. An
absolute link contains the absolute address of the entry that it points
to. A self-relative link contains a displacement from the present queue
entry. A queue is classified by the type of link it uses.

4.9.1

Absolute Queues

Absolute queues use absolute addresses as links.
Queue entries are
linked by a pair of longwords. The first (lowest addressed) longword is
the forward link: the address of the succeeding queue entry.
The
second (highest addressed) longword is the backward link: the address
of the preceding queue entry. A queue is specified by a queue header
which is identical to a pair of queue linkage longwords. The forward
link of the header is the address ~f the entry termed the head of the
queue.
The backward link of the header is the address of the entry
termed the tail of the queue. The forward link of the tail pOints to
the header.
Two general operations can be performed on queues: insertion of entries
and removal of entries. Generally entries can be inserted or removed
only at the head or tail of a queue. (Under certain restrictions they
can be inserted or removed elsewhere; this is discussed later.)
The following contains examples of queue operations.
specified by its header at address H:

3
1

An empty queue

+---------------------------------------------------------------+
:
H
:H
+---------------------------------------------------------------+
H
:H~
+---------------------------------------------------------------+
3
0
1

If an entry at address B is inserted into an empty queue (at either
head or tail), the queue is as shown below:

the

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QUEUE INSTRUCTIONS

3
1

+---------------------------------------------------------------+
:H
B
+---------------------------------------------------------------+
:H+4
B
+---------------------------------------------------------------+
3
0
1

+--------------------------------~------------------------------+

+---------------------------------------------------------------+
H
:B+4
+---------------------------------------------------------------+
3
0
I

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If an entry at address A is inserted at the head of the queue, the queue
is as shown below:
3
1

+---------------------------------------------------------------+
A
I :H
+---------------------------------------------------------------+
,
B
+---------------------------------------------------------------+
3
0
I

3
1

+---------------------------------------------------------------+
:A
B
+---------------------------------------------------------------+
:A+4
H
+---------------------------------------------------------------+
o
3
1

3
1

+---------------------------------------------------------------+
H
I :B
+---------------------------------------------------------------+
A
:B+4
+---------------------------------------------------------------+
3
0
1

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QUEUE INSTRUCTIONS
Finally, if an entry at address C is inserted at
appears as follows:

the

tail,

the

queue

+---------------------------------------------------------------+
A
:H
+---------------------------------------------------------------+
C
:H+4
+---------------------------------------------------------------+
3
0
1

+-------------------------------------------------------~-------+

+---------------------------------------------------------------+
:A+4
H
+---------------------------------------------------------------+
o
3
I

3
1

+---------------------------------------------------------------+
:B
C
+---------------------------------------------------------------+
:B+4
A
+---------------------------------------------------------------+
3
0
1

3
1

+---------------------------------------------------------------+
H
:C
+---------------------------------------------------------------+
B
:C+4
+---------------------------------------------------------------+
o
3
1

Following the above steps in reverse order gives the effect of removal
at the tail and removal at the head.

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QUEUE INSTRUCTIONS
If more than 1 process can perform operations on a queue simultaneously,
insertions and removals should only be done at the head or tail of the
queue. If only 1 process (or 1 process at a time) can perform
operations on a queue, insertions and removals can be made at other than
the head or tail of the queue. In the example above with the queue
containing entries A,B, and C, the entry at address B can be removed
giving:

+---------------------------------------------------------------+
I
A
I :H
+---------------------------------------------------------------+
I
C
:H+4
+---------------------------------------------------------------+
3
0
1

+---------------------------------~.-----------------------------+

+---------------------------------------------------------------+
H
I :A+4
+---------------------------------------------------------------+
3
0
1

3
1

+---------------------------------------------------------------+
:c
H
+---------------------------------------------------------------+
A
+---------------------------------------------------------------+
3
0
1

The reason for the above restriction is that operations at the head or
tail are always valid because the queue header is always present;
operations elsewhere in the queue depend on specific entries being
present and may become invalid if another process is simultaneously
performing operations on the queue.
Two instructions are provided for manipulating absolute queues
INSQUE, and REMQUE.
lNSQUE inserts an entry specified by an entry
operand into the queue following the entry specified by the predecessor
operand.
REMQUE removes the entry specified by the entry operand.
Queue entries can be on apbitrary byte boundaries.
Both INSQUE and
REMQUE are implemented as non-interruptible instructions.

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QUEUE INSTRUCTIONS

INSQUE

Insert Entry in Queue

opcode

entry.ab, pred.ab

Format:

Operation:
If {all memory accesses can be completed} then
begin
(entry) <- (pred);
!forward link of entry
(entry + 4) <- pred;
!backward link of entry
((pred) + 4) <- entry; !backward link of successor
(pred) <- entry;
!forward link of predecessor
end;
else
begin
{backup instruction};
{initiate fault};
end;
Condition Codes:

N <- (entry) LSS (entry+4);
Z <- (entry) EQL (entry+4);
V <- 0;

!first entry in queue

C <- (entry) LSSU (entry+4);

Exceptions:
none
Opcodes:
OE

INSQUE

Insert Entry in Queue

Description:
The entry specified by the entry operand is inserted into the queue
following the entry specified by the predecessor operand. If the entry
inserted was the first one in the queue, the condition code Z-bit is
set;
otherwise it is cleared. The insertion is a non-interruptible
operation. Before performing any part of the operation, the processor
validates that the entire operation can be completed. This ensures that
if a memory management exception occurs (See Chapters 5 and 6), the
queue is left in a consistent state.

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QUEUE INSTRUCTIONS
Notes:
1.

Three types of insertion can be performed by appropriate choice
of predecessor operand:
1.

Insert at head
INSQUE

entry,h

;h is queue head

Insert at tail
INSQUE entry,@h+4
;h is queue head
(Note "@" in this case only)

Insert after arbitrary predecessor
INSQUE

entry,p

;p is predecessor

Because the insertion is non-interruptible, processes running
in kernel mode can share queues with interrupt service routines
(See Chapters 5, 6, and 7).

The INSQUE and REMQUE instructions are implemented such that
cooperating software processes in a single processor may access
a shared list without additional synchronization if
the
insertions and removals are only at the head or tail of the
queue.

To set a software interlock
following can be used:
INSQUE
BEQL
CALL

WAIT( ... )

realized

with

queue,

the

;was queue empty?
;yes
;no, wait

1 $:

During access validation, any access which cannot be completed
results in a memory management exception even though the queue
insertion is not started.

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QUEUE INSTRUCTIONS

REMQUE

Remove Entry From Queue

opcode

entry.ab,addr.wl

Format:

Operation:
if {all memory acceses can be completed} then
begin
«entry+4» <- (entry); !forward link of predecessor
«entry)+4) <- (entry +4); !backward link of successor
addr <- entry;
end;
else
begin
{backup instruction};
{initiate fault};
end;
Condition Codes:
N <- (entry) LSS (entry+4);
Z <- (entry) EQL (entry+4);
V <- entry EQL (entry+4);
C <- (entry) LSSU (entry+4);

!queue empty
!no entry to remove

Exceptions:
none
Opcodes:
OF

REMQUE

Remove Entry from Queue

Description:
The queue entry specified by the entry operand is removed from the
queue.
The address operand is replaced by the address of the entry
removed. If there was no entry in the queue to be removed, the
condition code V bit is set; otherwise it is cleared. If the queue is
empty at the end of this instruction, the condition code Z-bit is set;
otherwise it is cleared. The removal is a non-interruptible operation.
Before performing any part of the operation, the processor validates
that the entire operation can be completed. This ensures that if a
memory management exception occurs (See Chapters 5 and 6), the queue is
left in a consistent state.

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Notes:
1.

Three types of' removal can be performed by suitable
entry operand:
1.

@h,addr

;h is queue header

Remove at tail
REMQUE

Remove at head
REMQUE

choice

@h+4,addr

;h is queue header

Remove arbitrary entry
REMQUE

entry,addr

Because the removal is non-interruptible, processes running in
kernel mode can share queues with interrupt service routines
(See Chapters 5, 6, and 7).

The INSQUE and REMQUE instructions are implemented such that
cooperating software proce5ses in a single processor may access
a shared list without additional synchronization if
the
insertions and removals are only at the head or tail of the
queue.

To release a software interlock
followng can be used:
REMQUE
BEQL
CALL

ACTIVATE ( ..• )

l"'ealized

with

queue,

the

;queue empty?
;yes
;Activate other waiters

1 $:

To remove entries until the queue is empty, the
be used:
1 $:

REMQUE
BVS

EMPTY

following

can

;anything removed?
;no

During access validation, any access which cannot be completed
results in a memory management exception even though the queue
removal is not started.

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QUEUE INSTRUCTIONS
4.9.2

Self-relative Queues

Self-relative queues use displacements from queue entries as links.
Queue entries are linked by a pair of longwords. The first longword
(lowest addressed) is the forward link
displacement of the succeeding
queue entry from the present entry.
The second longword (highest
addressed) is the backward link:
the displacement of the preceding
queue entry from the present entry. A queue is specified by a queue
header, which also consists of two longword links.
The following contains examples of queue operations. An empty queue is
specified by its header at address H. Since the queue is empty, the
self-relative links must be zero as shown below:
3
1

+---------------------------------------------------------------+
:H
o
+---------------------------------------------------------------+
:H+4
o
+---------------------------------------------------------------+
o
3
1

If an entry at address B is inserted into an empty queue (at either
head or tail), the queue is as shown below:
3
1

the

+---------------------------------------------------------------+
B- H
:H
+---------------------------------------------------------------+
B- H
:H+4
+---------------------------------------------------------------+
o
3
1

3
1

+---------------------------------------------------------------+
I
H - B
:B
+---------------------------------------------------------------+
:B+4
H- B
+---------------------------------------------------------------+
3
0
1

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QUEUE INSTRUCTIONS
If an entry at address A is inserted at the head of the queue, the queue
is as shown below:

3
1

+---------------------------------------------------------------+
A H
:H
+---------------------------------------------------------------+
:H+4
B- H
+---------------------------------------------------------------+
o
3
I

3
1

+---------------------------------------------------------------+
:A
B- A
+---------------------------------------------------------------+
:A+4
H - A
+---------------------------------------------------------------+
3
0
1

3
1

+---------------------------------------------------------------+
H- B
:B
+---------------------------------------------------------------+
A- B
:B+4
+---------------------------------------------------------------+
o
3
1

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QUEUE INSTRUCTIONS
Finally, if an entry at address C is inserted at
appears as follows:
3
1

the

tail,

the

queue

+---------------------------------------------------------------+
:H
A - H
+---------------------------------------------------------------+
:H+4
C- H
+---------------------------------------------------------------+
3
0
I

3
1

+---------------------------------------------------------------+
B- A
:A
+---------------------------------------------------------------+
:A+4
H- A
+---------------------------------------------------------------+
o
3
I
t

3
1

+---------------------------------------------------------------+
C B
:8
+---------------------------------------------------------------+
:B+4
A- B
+-------------------------------~-------------------------------+

3
1

+---------------------------------------------------------------+
H- C
:C
+---------------------------------------------------------------+
I
B- C
:C+4
+---------------------------------------------------------------+
o
3
1

Following the above steps in reverse order gives the effect of removal
at the tail and removal at the head.
Four operations can be performed on self-relative queues
insert at
head,
insert at tail, remove from head, and remove from tail.
Furthermore, these operations are interlocked to allow cooperating
processes in a multiprocessor system to access a shared list without

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QUEUE INSTRUCTIONS
additional synchronization. Queue entries must be quadword aligned.
Hardware supported interlocked memory access mechanism is used to read
the queue header. Bit 0 of the queue header is used as a secondary
interlock and is set when the queue is being accessed.
If an
interlocked queue instruction encounters the secondary interlock set, it
terminates after setting the condition codes to indicate failure to gain
access to the queue.

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QUEUE INSTRUCTIONS

INSQHI

Insert Entry into Queue at Head, Interlocked

opcode

entry.ab, header.aq

Format:

Operation:
tmp1 <- (header) {interlocked};

!acquire hardware interlock
!must have write access to header
!header must be quadword aligned
!header cannot be equal to entry
!tmp1<2:1> must be zero

if tmp1<O> EQLU 1 then
begin
(header){interlocked} <- tmp1; !release hardware interlock
{set condition codes and terminate instruction};
end;
else
begin
(header){interlocked} <- tmp1 v 1; !set secondary interlock
!release hardware interlock
If {all memory accesses can be completed} then
!check if following addresses can be written
!without causin~o'a memory management exception:
!
entry./
header 4+ tmp1
,'"'
!Also, check for quadword alignment
begin//'"
tmp2/<- header - entry;
(entry) <- tmp1/+ tmp,2;
! forward link of entry
(entry + 4) <- tmp2;'
!).>ackward link of entry
(header + tmp1 + 4) <- -tmpk/- tmp2;
!backward link of successor
{read (header) {interlocked}};
!acquire hardware interlock
(header) {interlocked} <- -tmp2,~."f·~'
!forward link of header, release interlocks
end;
else
begin
{read (header) {interlocked}};
!acquire hardware interlock
(header){interlocked} <- tmp1;
!release all interlocks
{backup instruction};
{initiate fault};
end;
end;

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Condition Codes:
if {insertion succeeded} then
begin
N <- 0;

Z <- (entry) EQL (entry+4);

!first entry in queue

V <- 0;

C <- OJ

end;
else
begin
N <- OJ

Z <- 0;

V <- OJ
C <- 1 ,•

!secondary interlock failed

endj

Exceptions:
reserved operand
Opcodes:
5C

INSQHI

Insert Entry into Queue at Head, Interlocked

Description:
The entry specified by the entry operand is inserted into the queue
following the header.
If the entry inserted was the first one in the
queue, the condition code Z-bit is set; otherwise it is cleared.
The
insertion
is
a
non-interruptible
operation.
The insertion is
interlocked to prevent concurrent interlocked insertions or removals at
the head or tail of the same queue by another process even in a
multiprocessor environment.
Before performing any
part
of
the
operation, the processor validates that the entire operation can be
completed. This ensures that if a memory management exception occurs
(See Chapters 5 and 6), the queue is left in a consistent state. If the
instruction fails to acquire the secondary interlock, the instruction
sets condition codes and terminates.

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QUEUE INSTRUCTIONS
Notes:
1.

Because the insertion is non-interruptible, processes running
in kernel mode can share queues with interrupt service routines
(See Chapters 5, 6, and 7).

The INSQHI, INSQTI, REMQHI, and REMQTI instructions
are
implemented such that cooperating software processes in a
multiprocessor may access a shared list without additional
synchronization.

To set a software interlock
following can be used:
INSERT:

INSQHI
BEQL
BCS
CALL

INSERT
WAIT( ..• )

realized

with

queue,

the

;was queue empty?
;yes
;try inserting again
;no, wait

1 $:

During access validation, any access which cannot be completed
resul ts in a memory management exception. even though the queue
insertion is not started.

A reserved operand fault occurs if entry or header is an
address that is not quadword aligned (i.e. <2:0> NEQU 0) or if
(header)<2:1> is not zero.
A reserved operand fault also
occurs if header equals entry. In this case the queue is not
altered.

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INSQTI

Insert Entry into Queue at Tail, Interlocked

opcode

entry.ab, header.aq

Format:

Operation:
tmp1 <- (header) {interlocked};

!acquire hardware interlock
!must have write access to header
!header must be quadword aligned
!header cannot be equal to entry
!tmp1<2:1) must be zero

if tmp1<O> EQLU 1 then
begin
(header){interlocked} <- tmp1; !release hardware interlock
{set condition codes and terminate instruction};
end;
else
begin
(header){interlocked} <- tmp1 v 1; !set secondary interlock
!release hardware interlock
If {all memory accesses can be completed} then
!check if the following addresses can be written
!without causing a memory management exception:
!
entry
header + (header + 4)
!Also, check for quadword alignment
begin
J'''
tmp2 <- (header + 4);
-tmp3 <- header - entrj;
(entry) <- tmp3; /
,/!forward link of entry
(entry + 4) <- tmp2 + tmp3; !backwa ti link of entry
if {tmp2 NEQUO} then (header+tm
<- -tmp3 - tmp2
else tmp1 <- -tmp3
tm
!forward link of predecessor
(header+4) <- -tmp3; !backward link of header
{read (header) {interlocked}};
!acquire hardjlare interlock
(header){interlocked} <- tmp1; !release interlocks
end;
else
begin
{read (header) {interlocked}};
!acquire hardware interlock
(header){interlocked} <- tmp1; !release interlocks
{backup instruction};
{initiate fault};
end;
end;

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QUEUE INSTRUCTIONS
Condition Codes:
if {insertion succeeded} then
~egin

N <- 0;

Z <- (entry) EQL (entry+4);
V <- 0;
C <- 0;

!first entry in queue

end;
else
begin
N <- 0;
Z <- 0;

V <- 0;
C <- 1;

!secondary interlock failed

end;
Exceptions:
reserved operand
Opcodes:
5D

INSQTI

Insert Entry into Queue at Tail, Interlocked

Description:
The entry specified by the entry operand is inserted into the queue
preceding the header.
If the entry inserted was the first one in the
queue, the condition code Z-bit is set; otherwise it is cleared.
The
insertion
is
a
non-interruptible
operation.
The insertion is
interlocked to prevent concurrent interlocked insertions or removals at
the head or tail of the same queue by another process even in a
multiprocessor environment.
Before performing any
part
of
the
operation, the processor validates that the entire operation can be
completed. This ensures that if a memory management exception occurs
(See Chapters 5 and 6), the queue is left in a consistent state. If the
instruction fails to acquire the secondary interlock, the instruction
sets condition codes and terminates.

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QUEUE INSTRUCTIONS
Notes:
1.

Because the insertion is non-interruptible, processes running
in kernel mode can share queues with interrupt service routines
(See Chapters 5, 6, and 7).

The INSQHI, INSQTI, REMQHI, and REMQTI instructions
are
implemented such that cooperating software processes in a
multiprocessor may access a shared list without additional
synchronization.

To set a software interlock
following can be used:
INSERT:

INSQHI
BEQL
BeS

CALL

INSERT
WAIT( ... )

realized

with

queue,

the

;was queue empty?
;yes
;try inserting again
;no, wait

1 $:

During access validation, any access which cannot be completed
results in a memory management exception even though the queue
insertion is not started.

A reserved operand fault occurs if entry, header, or (header+4)
is an address that is not quadword aligned (i.e. <2:0> NEQU 0)
or if (header)<2:1> is not zero. A reserved operand fault also
occurs if header equals entry. In this case the queue is not
altered.

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QUEUE INSTRUCTIONS

REMQHI

Remove Entry from Queue at Head, Interlocked

opcode

header.aq, addr.wl

Format:

Operation:
tmp1 <- (header) {interlocked};

!acquire hardware interlock
!must have write access to header
!header must be quadword aligned
!header cannot be equal to ,addr
!tmp1<2:1) must be zero
.~

if tmp1<O) EQLU 1 then
begin
(header){interlocked} <- tmp1; !release hardware interlock
{set condttion codes and terminate instruction};
end;
else
begin
(header){interlocked} <- tmp1 v 1; !set secondary interlock
!release hardware interlock
If {all memory accesses can be completed} then
!check if the following can be done without
!causing a memory management exception:
!write addr operand
tread contents of header + tmp1 {if tmp1 NEQU OJ
!write into header + tmp1 + (header + tmp1) {if
!
tmp1 NEQU O}
!Also, check for quadword alignment
begin
addr <- header + tmp1;
if {tmp1 EQL O} then tmp2 <- header
else tmp2 <- addr + (addr);
(tmp2 + 4) <- header - tmp2;
!backward link of successor
{read (header) {interlocked}};
!acquire hardware interlock
(header){interlocked} <- tmp2 - header;
!forward link of header, release all interlocks
end;
else
begin
{read (header){interlocked}};
!acquire hardware interlock
(header){interlocked} <- tmp1; !release interlocks
{backup instruction};
{initiate fault};
end;
end;

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QUEUE INSTRUCTIONS
Condition Codes:
if {removal succeeded} then
begin

N <- 0;
Z <- (header) EQL 0;
V <- tmp1 EQL 0;
C <- 0;

!queue empty
Ino entry to remove

end;
else
begin
N <- 0;

Z <- 0;
V <- 1;

C <- 1;

!did not remove anything
!secondary interlock failed

end;
Exceptions:
reserved operand
Opcodes:
5E

REMQHI

Remove Entry from Queue ~ T?{l, lnterlocked
,/

Description:
The queue entry following the header is ren;oved from the queue.
The
address operand is replaced by the address of the entry removed. If no
entry was removed from the queue (because either there was nothing to
remove or secondary interlock failed), the condition code V bit is set;
otherwise it is cleared. If the interlock succeeded and the queue is
empty at the end of this instruction, the condition code Z-bit is set;
otherwise it is cleared.
The removal is interlocked to prevent
concurrent interlocked insertions or removals at the head or tail of the
same queue by another process even in a multiprocessor environment. The
removal is a non-interruptible operation. Before performing any part of
the operation, the processor validates that the entire operation can be
completed.
This ensures that if a memory management exception occurs
(See Chapters 5 and 6), the queue is left in a consistent state. If the
instruction fails to acquire the secondary interlock, the instruction
sets condition codes and terminates without altering the queue.

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DO NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Instructions
30-Nov-78 -- Rev 5
Page 4-135
QUEUE INSTRUCTIONS
Notes:
1.

Because the removal is non-interruptible, processes running in
kernel mode can share queues with interrupt service routines
(See Chapters 5, 6, and 7).

are
The INSQHI, INSQTI, REMQHI, and REMQTI instructions
implemented such that cooperating software processes in a
multiprocessor may access a shared list without additional
synchronization.

To release a software interlock
following can be used:
1$:

REMQHI
BEQL
BCS
CALL

2$
1$
ACTIVATE ( ... )

realized

with

queue,

the

jremoved last?
;yes
;try removing again
;Activate other waiters

2$:
4.

To remove entries until the queue is empty, the
be used:
1 $:

REMQHI
BVS

following

can

;anything removed?
;no

process removed entry
BR
2$:

BCS
1$
queue empty

;try removing again

During access validation, any access which cannot be completed
results in a memory management exception even though the queue
removal is not started.

A reserved operand fault occurs if header or (header +
(header»
is an address that is not quadword aligned (i.e.
<2:0) NEQU 0) or if (header)<2:1) is not zero.
A reserved
operand fault also occurs if header equals addr. In this case
the queue is not altered.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
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COMPANY CONFIDENTIAL
Instructions
30-Nov-78 -- Rev 5
Page 4-136
QUEUE INSTRUCTIONS

REMQTI

Remove Entry from Queue at Tail, Interlocked

opcode

header.aq, addr.wl

Format:

Operation:
tmp1 <- (header) {interlocked};

!acquire hardware interlock
!must have write access to header
!header must be quadword aligned
!header cannot be equal to addr
!tmp1<2:1) must be zero

if tmp1<O) EQLU 1 then
begin
(header){interlocked} <- tmp1; !release hardware interlock
{set condition codes and terminate instruction};
end;
else
begin
(header){interlocked} <- tmpl v 1; !set secondary interlock
!release hardware interlock
If {all memory accesses can be completed} then
!check if the following can be done without
!causing a memory management exception :
!write addr operand
tread contents of header + (header + 4) iif tmp1
NEQU O}
!write into header + (header + 4)
!
+ (header + 4 + (header + 4» {if tmpl NEQU O}
!Also, check for quadword alignment
begin
addr <- header + (header + 4);
tmp2 <- addr + (addr + 4);
(header + 4) <- tmp2 - header;
!backward link of header
tmp3 <- tmpl;
!save tmp1 to set Z correctly
if {tmp2 EQL header} then tmpl <- 0
else(tmp2) <- header - tmp2;
!forward link of predecessor
{read (header) {interlocked}};
(header){interlocked} <- tmp1; !release interlocks
end;
else
begin
{read (header){interlocked}};
!acquire hardware interlock
(header){interlocked} <- tmpl; !release interlocks
{backup instruction};
{initiate fault};
end;
end;

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
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Instructions
30-Nov- 7B -- Rev 5
Page 4-137
QUEUE INSTRUCTIONS
1

Condition Codes:
if {removal succeeded} then
begin
N <- 0;

Z <- (header + 4) EQL 0;
V <- tmp3 EQL 0
C <- 0;
end;

!queue empty
!no entry to remove

else
begin
N <- 0;

Z (- 0;
V <- 1;
C <- 1;

!did not remove anything
!secondary interlock failed

end;
Exceptions:
reserved operand
Opcodes:
5F

REMQTI

Remove Entry from Queue at Tail, Interlocked

Description:
The queue entry preceding the header is removed from the Queue.
The
address operand is replaced by the address of the entry removed. If no
entry was removed from the Queue (because either there was nothing to
remove or secondary interlock failed), the condition code V bit is set;
otherwise it is cleared. If the interlock succeeded and the Queue is
empty at the end ~f this instruction, the condition code Z-bit is set;
otherwise it is cleared.
The removal is interlocked to prevent
concurrent interlocked insertions or removals at the head or tail of the
same Queue by another process even in a multiprocessor environment. The
removal is a non-interruptible operation. Before performing any part of
the operation, the processor validates that the entire operation can be
completed.
This ensures that if a memory management exception occurs
(See Chapters 5 and 6), the queue is left in a consistent state. If the
instruction fails to acquire the secondary interlock, the instruction
sets condition codes and terminates without altering the Queue.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Instructions
30-Nov-78 -- Rev 5
Page 4-138
QUEUE INSTRUCTIONS
Notes:
1.

Because the removal is non-interruptible, processes running in
kernel mode can share queues with interrupt service routines
(See Chapters 5, 6, and 7).

are
The INSQHI, INSQTl, REMQHI, and REMQTI instructions
implemented such that cooperating software processes in a
multiprocessor may access a shared list without additional
synchronization.

To release a software interlock
following can be used:
1$:

REMQTI
BEQL
BCS
CALL

2$
1$
ACT I VA TE ( •.. )

realized

with

queue,

the

;removed last?
;yes
;try removing again
;Activate other waiters

2$:

To remove entries until the queue is empty, the
be used:
1 $:

REMQ'I'1
BVS

following

can

;anything removed?
;no

process removed entry

BR
2$:

BCS
1$
queue empty

;try removing again

During access validation, any access which cannot be completed
results in a memory management exception even though the queue
removal is not started.

A reserved operand fault occurs if header, (header + 4), or
(header + (header + 4)+4) is an address that is not quadword
aligned (i.e. <2:0> NEQU 0) or if (header)<2:1> is not zero.
A reserved operand fault also occurs if header equals addr. In
this case the queue is not altered.

CliAPTER 4

lNSTRUCTIONS

26-0ct-78 -- Rev 5

**~*****~~**.******~*******~**i**********i*************

*
*
*

ThROW THIS PAGE AWAY.

This is the fourth part of Chapter 4.

Page 1

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

VAX-l1 Character String Instructions -- Rev 5

Specification Status:

Fully Approved

Architectural Status:

under ECO control

File:

SR4DR5.RNO

PDN if: not used

Date:

26-0ct-7b

Superseded Specs:

Hev 4

A1;'~hor:

strecker

Typist:

Call

Reviewer(s):

Abstract:

R. Blair, R. Brender, D. Ca.ne, K. Cnapman, P. Conklin,
D. Cutler, R. Grove, T. Hastings, D. Hustvedt, J. Leonard,
P. Lipman, h. Payne, D. Rodgers, .s. Rothman, h. Stewart,
b. Strecker

Chapter 4 describes the instructions generally used by all
softviare
acr()ss
all
implementations
of
the
VAX-11
architecture.
For convenience of review and
editting,
chapter 4 is separated into a number of specifications. This
specification contains the character string and
cyclic
redundancy check instructions.

Revision History:
Rev if
Rev 1
Rev 2
Rev j
Rev 4
Rev 5

Description
Initial distribution of SRN
ECOs 1-11
ECOs 12-18, April Meeting,
and Nay 25 Meeting
EC0's
Editorial, lviATCHC ECO

Author
Strecker
Strecker
Strecker
Strecker
Bhandarkar

Revised Date
25-Sep- '(5

16-Mar- {6
10-Jun-76
r

31-tvlar-77
26-0ct-'lb

Page 4-990

Instructions
26-0ct-7b -- Rev 5
Change History for Character String
Rev 4 to Rev 5:
1.

Typos

HATCHC ECO

Rev 3 to Rev 4:
1.

Typos

EGO to complete documentation of eRC Instruction.

Clarify null strings.

Add AUTODIN-II CRG.

Rev 2 to Rev 3:
1.

Reserved operand aborts become faults

Add SKPG

Change pointer to longwora or address;

Add MINU function in ISP

Explicitly give SEXT or i.EXT in all cases needed

Specified condition codes on all exceptions

MOVTC does not translate fill

Increase registers used by M0VC3 and MOVG5 to 6

Change conaition codes setting MOVC, MOVTC, MOVTUC

10.

Add MOVTUC, MATCHC

11.

Add eRC per ECO 12

12.

Change CRC ~able operand from .al to .ab

13.

Split into separate specifications

Rev 1 to Rev 2:
See CH4A for changes
[End of SR4DR5.RNO)

make it 32 bits

Copyright(c) 19'19 Digital Equipment CO'rp.,t'laynard,l"Jass.
DO Nul' CUPY.
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COlVIPANY CONF'lDENTIAL
Instructions
26-0ct-78 -- Rev 5
Page 4-139
ChARACTER STRING INSTRUCTIONS

4.10

ChARACTER STRING INSTRUCTIONS

A character string is specified by 2 operands:

An unsigned word operand which
character string in bytes.

specifies

the

length

the

The address of the lowest addressed byte of the character
string.
Ihis is specified by a byte operand of address acce~s
type.

0f the character string instructions uses general registers RO
through R1, RO throughRj, or RO through R5 to contain a control block
which maintains updated addresses and state during the execution of the
instruction.
At completion, these registers are available to software
to use as string specification operands for a subsequent instruction on
a
contiguous
character
string.
During
the execution of the
instructions, pending interrupt conditions are tested and if any is
found, the control block is updated, a first part done bit is set in the
PSL, and the instruction interrupted (See Chapter 6).
After the
interruption, the instructior. resumes transparently. The format of the
control block is:
~ach

+ __

M ______________

_____

________

+--------~---------~-

___ ___ ___ +
~

LENGTH 1

+-------------------------------+----------~-----~---------.----+
ADDRESS 1

+-------------------------------+-------~-----------------------+
I
I

+-------------------------------+----------..
--------------------+
ADDRESS 2

LENGTH 2

I
I

+-------------------~-----------+-.--~------~.-----~--~----~----+
LE~G'l'H

+---------______________________ + _______ ___ ____
~

w------.-----~-+

ADDRESS j
+-----------------------------------~---------------~--~--~~----+

The fields LENGTH 1, LENGTH 2 (if required) and LENGTH 3 (if required)
contain the number of bytes remaining to be processed in the first,
second and third string operands respectively. The fields ADDRESS 1,
ADDRESS 2 (if required) and ADDRESS j (if required) contain the address
of the next byte to be processed in the first, second, and third string
operands respectively.

Copyright{c) 1979 Digital Equipment Corp. ,Naynard,l"iass.
DO NOT COPY
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instructions
26-0ct-7e -- Rev 5
Page 4-140
CHARACTER STRING INSTRUCTIONS

MOVC

Move Character

Format:
opcode len.rw, srcaddr.ab, dstaddr.ab

3 operand

opcode srclen.rw, srcaddr.ab,
dstlen.rw, dstaddr.ab

5 operand

fill~rb,

Operation:
tmp1 <- len;
tmp2 <- srcaddr;
tmp3 <- dstaddr;
if tmp2 GIRD tmp~ then
begin
while tmp1 NEQU 0 do
begin
(tmp3) <- (tmp2);
tmp1 <- tmp1 - 1;
tmp2 <- tmp2 + 1;
tmpj <- tmp3 + 1;
end;
R1 <- tmp2;
R3 <- tmp3;
end
else
begin
tmp4 <- tmp 1 ;
tmp2 <- tmp2 + l:.EXT (tmp1 );
tmpj <- tmp3 + ZEXI(tmp1);
while tmp1 NEQU 0 do
begin
tmp1 <- tmp1 - 1;
tmp2 <- tmp2 - 1;
tmp3 <- tmpj - 1;
(tmp3), <- (tmp2);
end;
R1 <- tmp2 + ZEXl(tmp4);
R3 <- tmpj+ ZEXT(tmp4);
end;
RO <- 0;
R2 <- 0;
R4 <- OJ
R5 <- 0;

oper'and

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Page 4-141
CHARACTER STRING INSTRUCTIONS

tmp1 <- srclen;
!5 operand
tmp2 (- srcaddr;
tmp3 <- astlen;
tmp4 (- dstaddr;
if tmp2 GTRU tmp4 then
begin
while {tmp1 NEQU OJ AND {tmp3 NEQU O} do
begin
(tmp4) (- (tmp2);
tmp1 (- tmp1 - 1;
tmp2 <- tmp2 + 1;
tmp3 <- tmp3 - 1;
tmp4 <- tmp4 + 1;
end;
while tmpj NEQU 0 do
begin
(tmp4) <- fill;
tmp3 <- tmp~ - 1;
tmp4 <- tmp4 + 1;
end;
Rl <- tmp2;
}(') <- tmp4;
end
else
begin
tmp5 <- MINU(tmp1, tmp3);
tmp6 <- tmpj;
tmp2 (- tmp2 + ZEXT(tmp5);
tmp4 <- tmp4 + ZEXT(tmp6);
while tmp3 GIRU tmp1 do
begin
tmp3 (- tmp3 - 1;
tmp4 <- tmp4 - 1;
(tmp4) <- fill;
end;
while tmp3 NEQU 0 do
begin
tmp1 <- tmp1 - 1;
tmp2 <- tmp2 - 1;
tmp3 <- tmp3 - 1;
tmp4 <- tmp4 - 1;
(tmp4) <- (tmp2);
end;
R1 <- tmp2 + ZEXT (tmp5) ;
R3 <- tmp4 + ZEXT (tmpb);
end;
RO <- tmp1;

R2 <- OJ
R4 <- 0;
R5 <- 0;

Copyright(c) 1919 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
COl"IP~NY· CONF'lDENTIAL
-- Rev 5
Page 4-142
CHARACTER STRING INSTRUCTlONS

VAX-11 System·· Ref'erence1"Janual
Inst~uctions
26-0ct-7b

Condition Codes:
N <- O·,
Z <- 1 ,•

!!viOVC3

V <- O·,
C <-

O·,

N <Z <-

srclen LSS dstlen; !MOVC5
srclen EQL dstlen;
V <- O·,
C <- srclen LSSU d stlen;

Exceptions:
none
Opcodes:

28
2C

MOVC3
MOVC5

Move Character 3 Operand
Move Character 5 Operand

Description:
In 5 operand format, the destination string specified by the length and
destination address operands is replaced by the source string specified
by the length and source address operands. 1n 5 operand format, the
destination string specified by the destination length and destination
address operands is replaced by the source s~rlng specified by the
source length and source address operands. If the destination string is
longer than the source string, the highest addressed bytes of the
destination are replaced by the fill operand. If the destination string
is shorter than the source str'ing, the highest addressed bytes of the
source string are not moved. The operation of the instruction is such
that overlap,of the source and destination strings does not affect the
result.

Copyright(c) 1979 Digital Equipment Corp.,{IIlaynard,Ivlass.
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C01'1PANY C(;Nr'lDENTIAL
Instructions
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Page 4-14~
CHARACTER STRING INSTRUCTIONS
Notes:
1. After execution of MGVC3:

RO = 0
R1

= address of one byte beyond the source string

=0
R3 = address of one byte beyond the destination string.
R4 = 0
R5 = 0
R2

2. After execution of MOVC5:
fiO = number of unmoved bytes rema~n~ng in source string.
RO is non-zero only if source string is longer
than destination string
R1

= address of one byte beyono the last byte
in source string that was moved

R3 = address of one byte beyond the destination string •
R4 = 0
R5 = 0
3. MOVC3 is the preferred way to copy one block of memory to another.
4. MOVC5 with a· 0 source length operand is the preferred way to fill
a block of memory with the fill character.

Copyright(c) 1979 Digital Equipment Corp.,Haynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
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Instructions
26-0ct-78 -- Hev 5
page 4-144
CHARACTER STRING INSTRUCTIONS

MOVlC

Move Translated Characters

F'ormat:
opcode srclen.rw, srcaddr.ab, fill.rb, tbladdr.ab,
dstlen.rw, dstaddr.ab
Operation:
tmp1 <- srclen;
tmp2 <- srcaddr;
tmp3 <- dstlen;
tmp4 <- dstaddr;
if tmp2 GTRU tmp4 then
begin
while ttmp1 NEQU O} AND {tmp3 NEQU O}
begin
(tmp4) <- (tbladdr + ZEXT«tmp2));
tmp1 <- tmp1 - 1;
tmp2 <- tmp2 + 1;
tmp3 <- tmp3 - 1;
tmp4 (- tmp4 + 1;
end;
while {tmp3 NBQU O} do
begin
( tmp4) (- fill;
tmp3 <- tmp~ - 1;
tmp4 <- tmp4 + 1;
end;
R1 <- tmp2;
R5 <- tmp4;
end;
else
begin
tmp5 (- MINU(tmp1,tmpj);
tmp6 <- tmp3;
tmp2 <- tmp2 + ZEXT (tmp5 ) ;
tmp4 <- tmp4 + ZEXT(tmp6);
while tmp3 GTRU tmp1 do
begin
tmp3 <- tmp3 - 1;
tmp4 <- tmp4 - 1;
(tmp4) <- fill;
end;
while tmpj NEQU 0 do
begin
tmp1 <- tmp1 - 1;
tmp2 <- tmp2 - 1;
tmp3 <- tmpj - 1;
tmp4 <- tmp4 - 1;
(tmp4) <- (tbladdr + ZEXT«tmp2»);
end;
R1 <- tmp2 + ZEXT(tmp5);

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CHARACTER STRING lNSTRUCTIONS

R5 <- tmp4 + ZEXT(tmp6);
end;
HO <- tmp1 ;
R2 <- 0;
Rj <- tbladdr;
R4 <- 0;
Condition Codes:

N <- srclen LS~ dstlen;
£ <- srclen EQL dstlen;
V <- 0;
C <- srclen LSSU dstlen;
Exceptions:
none
Opcodes:
2E

MOVIe

Move Translated Characters

Description:
The source string specified by the source length and source address
operands is translated and replaces the destination string specified by
the destination length and destination address operands. lranslation is
accomplished by using each byte of the source string as an index into a
256 byte table whose zeroth entry address is specified by the table
address operand. Ihe byte selected replaces the byte of the destination
string. If the destination string is longer than the source string, the
highest addressed bytes of the destination string are replaced by the
fill operand. If the destination string is shorter than the $ource
string, the highest addressed bytes of the source string are not
translated and moved. The operation of the instruction is such that
overlap of the source and destination strings does not affect the
result. If the destination string overlaps the translation table, the
destination string is UNPREDICTABLE.
Notes:
After execution:
RO = number of untranslated bytes rema~n~ng in source string;
HO is non-zero only if source string is longer than
destination string
R1

= address of one byte beyond the last byte in
source string that was translated

=0
R3 = address of the translation table.

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CHARACTER STR1NG INS1RUCTIONS

= address of one byte beyond the destination
string.

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Instructions
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CHARACTER STRING INSTRUCTlONS

MOVTUC

Move Translated Until Character

If'ormat:
opcode srclen.rw, srcaddr.ab, esc.rb, tbladdr.ab, dstlen.rw,
dstaddr.ab
Operation:
tmp1 <- srclen;
tmp2 <- srcaddr;
tmp3 <- dstlen;
tmp4 <- dstaddr;
if tmp1 GTRU 0 and tmp3 GTRU 0 then
begin
while {tmpl NEQU O} AND {tmp3 NEQL O} do
if{(tbladdr + ZEXT(tmp2» NEQU esc} then
begin
(tmp4) <- (tbladdr + ZEXT(tmp2»;
tmp1 <- tmp1 - 1;
tmp2 (- tmp2 + 1;
tmp~ <- tmp3 - 1;
tmp4 <- tmp4 + 1;
end;
else exit while loop;
end;
RO <- tmp1 ;
R1 <- tmp2;
R2 <- 0;
R3 <- tbladdr;
R4 <- tmp3;
R5 <- tmp4;

Condition Codes:
N (-

srclen LSS dstlen;

Z <- srclen EQL dstlen;
V (- {terminated by escape};
C (- srclen LSSU dstlen;
Exceptions:
none
Opcodes:
2F

MOVTUC

Move Translated Until Character

Copyright(c) 1979 Digital Equipment Corp.,t-'laynard,lvlass.
DO NOT COpy
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COHPANY CONFlDENTIAL
Instructions
26-0ct-78 -- Rev 5
tage 4-148
ChARAC1ER STRING INSTRUCTIONS
Description:
The source string specified by the source length and source address
operands is translated and replaces the destination string specified by
the destination length and destination address operands. Translation is
accomplished by using each byte of the source string as index into a 256
byte table whose zeroth entry address is specified by the table address
operand. The byt~selected replaces the byte of the destination string.
Translation continues until a translated byte is equal to the escape
byte or until the source string or destination string is exhausted. If
translation is terminated because of escape the condition code V-bit is
set;
otherwise it is cleared. If the destination string overlaps the
source string or the table, the destination string and registers HO
through R5 are UNPREDICTABLE.
Notes:
After execution:

HO = number of bytes rema~n~ng in source string (including
the byte which caused the escape). RO is zero only
if the entire source string was translated and
moved without escape
R1

= address of the byte which resulted in destination
string exhaustion or escape; or if no exhaustion or
escape, address of one byte beyond the source string

R2 = 0
R3 = address of the table
R4 = number of bytes remaining in the destination str.ing
R5 = address of the byte in the destination string
which would have received the translated byte
which caused the escape or would have received a
translated byte if the source string were not exhausted;
or if no exhaustion or escap&, the address of one byte
beyond the destination string.

Copyright(c) 1979 Digital Equipment Corp.,haynard,Nass.
DO NOT COPY
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COtv1PANY CUNFIDENTIAL
Instructions
26-0ct-78 -- Rev 5
Page 4-14<9
CHARACTER ~TRING INSTRUCTIONS

CMPC

Compare Characters

Format:
opcode len.rw, srcladdr.ab, src2addr.ab

operand

opcode src1Ien.rw, srcladdr.ab, fill.rb,
src21en.rw, src2addr.ab

5 operand

uperation:
tmp1 <- len;
tmp2 <- srcladdr;

operand

<- src2addr;
if tmp1 EQL 0 then; !Condition Codes affected on tmp1 EQL 0
if tmp1 GIRU 0 then
begin
while {tmpl NEQU O} do
if (tmp2) EQL (tmp3) then
!Condition Codes affected on «tmp2) EQL (tmpj»
begin
tmpl <- tmpl - 1;
tmp2 <- tmp2 + 1;
tmp3 <- tmpj + 1;
end;
else exit while loop;
end;
RO <- tmp1 ;
R1 <- tmp~;
R2 <- HO;
R3 <- tmp3;
tmp~

tmp1 <- src1len;
tmp;::: <- src1addr;
tmpj <- src2len;
tmp4 <- src2addr;

!5 operand

if' {tmp1 EQL OJ AND {tmp3 EQL OJ then;
!Condition codes affected on ltmp1 EQL O} AND ltmp3 EQL OJ
while ttmp1 NEQU O} AND {tmpj NEQU OJ do
if (tmp2) EQL (tmp4) then
!Condition Codes affected on «tmp2) EQL (tmp4»
begin
tmp1 <- tmpl - 1;
tmp2 <- tmp2 + 1;
tmp3 <- tmp3 - 1;
tmp4 <- tmp4 + 1;
end;
else exit while loop;
if NUT{tmp1 NEQU O} AND {tmp3 NEQD O} then
begin
while {tmpl NEQU O} AND {(tmp2) EQL fill} do

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ChARACTER STRING INSTfiUCTIONS
!Condition Codes affected on «tmp2) EQL fill)
begin
tmp1 <- tmp1 - 1;
tmp2 <- tmp2 + 1;
end;
while {tmp3 NEQU O} AND tfill f!;QL (tmp4)} do
!Condition Codes affected on (fill EQL (tmp4»
begin
tmp3 <- tmp3 - 1;
tmp4 <- tmp4 + 1;
end;
end;
RO <- tmp1;
R1 <- tmp2;
R2 <- tmp3;
R3 <- tmp4;
Condition Codes:
!Final Condition Codes reflect last affecting
!of Condition Codes in Operation above.
N <- {first byte} LSS {second byte};
Z <- {first byte} EQL tsecond byte};

V <- 0;
C <- {first byte} LSSU {second byte};
Exceptions:
none
Opcodes:
29
20

CMPC3
Cl"lPC5

Compare Characters 3 Operand
Compare Characters 5 Operand

Description:
In 3 operand format, the bytes of string 1 specified by the length and
address 1 operands are compared with the bytes of string 2 specified by
the length and address 2 operands. Comparison proceeds until inequality
is detected or all the bytes of the strings have been examined.
Condition codes are affected by the result of the last byte comparison.
In 5 operand format, the bytes of the string 1 specified by the length 1
and address 1 operands are compared with the bytes of the string 2
specified by the length 2 and address 2 operands. If one string is
longer than the other, the shorter string is conceptually extended to
the length of the longer by appending (at higher addresses) bytes equal
to the fill operand. Comparison proceeds until inequality is detected
or all the bytes of the strings have been examined. Condition codes are
affected by the result of the last byte comparison. For either CMPC3 or
CMPC5 two zero length strings compare equal (i.e. Z is set and N, V,
and C are cleared).

Copyright(c) 1979 Digital £quiproent Corp. ,Maynard,tvlass.
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lnstructions
26-0ct-78 -- Rev 5
Page 4-151

ChARACTER STRING INSTRUCTlONS
Notes:
1.

After execution of CMPC3:
RO = number of bytes remaining in string 1 (including
byte which terminated comparison);
ltO is zero only if strings are equal
R1

= address of the byte in string 1 which terminated
comparison; if strings are equal, address of one
byte beyond string 1

= flO

R3 = address of the byte in string 2 which terminated
comparison; if strings are equal, address of
one byte beyond string 2.
2.

After execution of CMPC5:
HO = number of bytes remaining in string 1 (including
byte which terminated comparison); flO is zero only
if string 1 and stl'ing 2 are of equal length and
equal or string 1 was exhausted before comparison
terminated
R1

= address of the byte in string 1 which terminated
comparison; if comparison did not terminate
before string 1 exhausted, address of one byte
beyond string 1

R2 = number of bytes remalnlng in string 2 (including
byte which terminated comparison); R2 is zero
only if string 2 and string 1 are of equal length
or string 2 was exhausted before comparison terminated
R3 = address of the byte in string 2 which terminated
comparison; if comparison did not terminate before
string 2 was exhausted, address of one byte beyond
string 2.

If both strings have zero length, condition code Z is set and
N, V, and C are cleared just as in the case of two equal
strings.

Cl~pyright(c) 1979 Digital Equi:)ment Corp. ,Haynard,llllass.
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Instructions
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CHARACTER STRiNG INSTRUCTIONS

SCANC

Scan Characters

F'ormat:
opcode len.rw, addr.ab, tbladdr.ab, mask.rb
Operation:
tmp1 <- len;
tmp2 <- addr;
if tmp1 GTRU 0 then
begin
while {tmp1 NEQU O} AND
{{(tbladdr + ZEXT«tmp2))) AND mask} EQL O} do
begin
tmp1 <- tmpl - 1;
tmp2 <- tmp2 + 1;
end;
end;
kG <- tmpl ;
Rl <- tmp2;
H2 <- 0;
R3 <- tbladdr;
Condition Codes:
N <- OJ
Z <- RO EQL 0;
V <- 0;

C <- OJ

Exceptions:
none
Opcodes:
2A

SCAt\C

Scan Characters

Description:
The bytes of the string specified by the length and address operands are
successively used to index into a 256 byte table whose zeroth entry
address is specified by the table address operand.
The byte selected
from the table is ANDed with the mask operand. The operation continues
until the result of the AND is non-zero or all the bytes of the string
haye been exhausted.
If a non-zero AND result is detecteo, the
condition code Z-bit is cleared; otherwise, the Z-bit is set.

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CHARACTER STRING lNSTRUCTlO~S
VAX-11

Notes:
1.

After execution:

RO = number of bytes remaining in the string (including
the byte which produced the non-zero AND result)
RO is zero only if there was no non-zero AND result.
R1

= address of the byte which produced non-zero
AND result; or, if no non-zero result, address
of one byte beyond the string

= address of the table

If the string has zero length, condition code ~ is set just
though the entire string were scanned.

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CHARACTER STRING IN~TRUCTIONS

SPANC

Span Characters

ft'ormat:
opcode len.rw,addr.ab, tbladdr.ab, mask.rb
Operation:
tmp1 <- len;
tmp2 <- aCidr;
if tmp1 GTRD 0 then
begin
while {tmpl NEQU O} AND
{{(tbladdr + ZEXT«tmp2») AND mask} NEQ O} do
begin
tmp1 <- tmp1 - 1 ,•
tmp2 <- tmp2 + 1 .,
end;
end;
RO <- t;,mp1 ;
R1 <- tmp2;
R2
Rj

<- 0;
<- tbladdr;

Condition Codes:
N <- 0;

Z <- RO EQL 0;

V <- 0;

C <- 0;
Exceptions:
none
Opcodes:
2B

SPANC

Span Characters

Description:
The bytes of the string specified by the length and address operands are
successively used to index into a 256 byte table whose zeroth entry
address is specified by the table address operand.
The byte selected
from the table is ANDed with the mask operand. The operation continues
until the result of the AND is zero or all the bytes of the string have
If a zero AND result is detected, the condition code
been exhausted.
Z-bit is cleared; otherwise, the Z-bit is set.

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Instructions26~Oct-7d -- Rev 5
Page 4-155
ChARACTER STRING INSTRUCT10NS
Notes:
1.

After execution:
RO = number of bytes rema1n1ng in the string (including
the byte which produceO the zero AND result)
RO is zero only if there was no zero AND result.

= address of the byte which produced a zero AND
result; or, if no non-zero result, address of
one byte beyond the string

R2 = 0
R3 = address of the table.
2.

If the string has zero length, the condition code Z is set just
as though the entire string were spanned.

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CHARACTER STRING INSTRUCTIONS

LOCC

Locate Character

f4'ormat:
opcode char.rb, len.rw, addr.ab
CJperation:
tmp1 <- len;
tmp2 <- addr;
if tmp1 GTRU 0 then
begin
while ttmp1 NEQ O} AND t(tmp2) NEQ char!
begin
tmp1 <- tmp1
1,·
tmp2 <- tmp2 + 1 ;
end;
end;
RO <- tmp1;
R1 <- tmp2;

Condition Codes:
N <- 0;
z <- itO EQL 0;
V <... 0;

c <- 0;

Exceptions:
none
Opcodes:

LOCC

Locate Character

Descr.iption:
The Character operand is compared with the bytes of the st.r1ng specified
by the length and address operands. Comparison continues until equality
is detected or all bytes of the string have been compared. If equality
is detected; the condition code Z-bit is cleared; otherwise the Z-bit
is set.
Notes:
1.

After execution:
RO = number of bytes remaining in the string (including
located one) if byte located; otherwise 0
R1 : address of the byte located if byte located; otherwise

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CHARACTER STRING INSTRUCTIONS
address of one byte beyond the string.
2.

If the string has zero length, condition code Z is set j~st
though
each byte of the entire string wer'e unequal
character.

as
to

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Page 4-158

CHARACTER STRING INSTRUCTIONS

SKPC

Skip Character

opcode

char.rb, len.rw, addr.ab

Format:

Operati()n:
tmp1 <- len;
tmp2 <- addr;
if tmp1 GTRU 0 then
begin
while ttmp1 NEQ O} AND {(tmp2) EQL char} do
begin
tmp1 <- tmp1 - 1 ,.
tmp2 <- tmp2 + 1 .,
end;
end;
RO <- tmp1;
R1 <- tmp2;
Condition Codes:

N <- O'
2. <- RO EQL 0;
V· <- 0;

C <- O',

Exceptions:
none
Opcodes:

Skip Character

SKPC

Description:
The character operand is compared with the bytes of' the string specified
by
the length and address operands.
Comparison continues until
inequality is detected or all bytes of the string have been compared.
If inequality is detected;
the condition code Z-bit is cleared;
otherwise the Z-bit is set.
Notes:
1.

After execution:
RO = number of bytes rema~n~ng in the string (including the unequc
one) if unequal byte located; otherwise 0
R1

= address of the byte located if byte located; otherwise addre:

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~age 4-15~

ChARACTER STRING INSTRUCTIONS

of one byte beyond the string.
2.

if the string has zero length, condition code ~ is set just as
though each byte of the entire string were equal to character.

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CHARACTER STRING INSTRUCTIONS

MATCHC

Match Characters

Format:
opcode objlen:rw, objaddr.ab, srclen.rw,

srcaddr~ab

Operation:
tmp1 <- objlen;
tmp2 <- objaddr;
\t~y-'Jtmpj <- srclen;
.$({'.A 1 <"
tmp4 <- srcaddr; /)
tmp5 <- tmp1;
./
?
while ltmp1 NEQU O} AND {tmp3 GEQU tmp1} do
begin
if (tmp2) EQL (tmp4) then
begin
tmp1 <- tmp1 - 1;
tmp2 <- tmp2 + 1;
tmp3 <- tmp3 - 1;
tmp4 <- tmp4 + 1;
end
else
begin
tmp2 <- tmp2 - LEXT (tmp5-tmp1);
tmp3 <- {tmp3 - 1} + {tmp5-tmp1};
tmp4 <- {tmp4 + 1} - ZEXT (tmp5-tmp1);
tmp1 <- tmp5;
end;
end;
, r
(
RO <- tmp1;
[
R1 <- tmp2;
R2 <- tmp3;
.~.
Rj <- tmp4;

Condition Codes:
N <- 0;

Z <- RO EQL 0;

!match found

V <.- 0;

C <- 0;
Exceptions:
none
Opcodes:
39

MATCHC

Match Characters

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CHARACTER STRING I~STRUCTI0NS
VAX-11

Description:
The source string specified by the source length and source address
operands is searched for a substring which matches the object string
specified by the object length and object address operands.
If the
substring is found, the condition codeZ-bit is setj otherwise; it is
cleared.
Notes:
1.

After exec~tion:
ItO = if a match oocurred 0; other'~d~e the number of
bytes in the object string.
R1

= if a match occurred, the address of one byte beyond
the object string; otherwise the address of the
Objeotstring.
\~

R2 ;: if a match occurred, the number of bytes remaining in
the source string; otherwise O.
R3 = if a match occurred, the address of1 byte beyond
the last byte matched; otherwise the address of' 1
byte beyond the source, string .
. C:;,'""'"

If both strings have zero length or if the
zero length, condition code Z is set
substring were found.

object string has
just as though the

If the soUrce string has zero length and the object string has
non-zero length, condition code Z is cleared just as though the
substring were not found.

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instructions
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Page 4-162
CYCLIC REDUNDANCY CHECK INSTRUCTION
r

4.11

CYCLIC REDUNDANCY CHECK INSTRUCTION

This instruction is designed to implement the calculation and checking
of a cyclic redundancy check for ,any eRe polynomial up to 32 bits.
Cyclic Redundancy,Checking is an error detection method involving a
division of the data stream by a CRe polynomial. The data. stream is
represented as a standard VAX-11 string in memory. Error detection is
accomplished by computing tbe CRC at the source and again at the
destination, comparing the eRC computed at each end. The choice of the
polynomial is such as to minimize the number of undetected block errors
of specific lengths. T~echoice of a eRC polynomial is not given here;
see, for example, the article "Cyclic Codes for Error Detection" by W.
Peterson and D. Brown in the Proceedings of the IRE (January, 1961).
The

operands

to the eRC instruction are a string descriptor, a
table, and an initial CRC.
The string descriptor is a
standard VAX-11 operand pair of the length of the string in bytes (up to
65,535) and the starting address of thestring~ The contents of the
table are a function of the CRC polynomial to be used.
It can be
calculated from the polynomial by the algorithm in the notes. Several
common CRe polynomials are also included in the notes. The initial eRC
is used to start the polynomial correctly~ Typioally, it has the value
o or -1, but would be different if the data stream is represented by a
sequence of non-contiguous strings.
16~long~ord

The CRC instruction operates by scanning the string, and for each byte
of the data stream, including it, in the CRC being calculated. The byte
is included by XORing it to the right 8 bits pf the CRC. Then the CRC
is . shifted right 1 bit, inserting zero on the left. The right most bit
ot' the CRe (lost by the shift) is used to control the XORing of the CRC
polynomial with the re$ultant CRC. If the bit is set, the polynomial is
XORed with the CRC. 1hen the CRe is again shifted right and the
polynomial is conditionally IORed with the result a total of eight
times. The actual algorithm used can shift by one, two, or four bits at
a time using the appropriate entries in a specially constructed table.
The instruction produces a 32-bit CRC.
For shorter polynomials, the
result must be extracted from the j2..;bit field. lhe data stream must be
a multiple of' eight bits in length. If it is not, the stream must be
right adjusted in the string with leading 0 bits.

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instructions
26-0ct-78
Rev 5
Page 4-165
CYCLIC REDUNDANCY CHECK lNSTRUCTION

CRG

Calculate Cyclic Redundancy Check

opcode

tbl.ab, ·inicrc.rl, strlen.rw, stream.ab

Format:

Operation:
tmp1 <- strlen;
tmp2 <- stream;
tmp3 <- inicrc;
tmp4 <- tbl;
while tmp1 NEQU 0 do
begin
tmp3<7:0><- tmp3<1:0) XOR (tmp2)+;
for tmp5 <- 1,Iimit do
!see note 5 for limit,s,i
tmp3 <- ZEXT(tmpj<31:s» XOR
(tmp4 + {4*ZEX'l'(tmp3<s-1:0> it i)};
tmpl <- tmpl -1;
end;
RO <- tmp3;
R1 <- 0;
R2

<- 0;

R3 <- tmp2;

!address of end of string + 1

Condition Codes:
N <- flO LoSS 0;
Z <- RO EQL 0;
V <- 0;
C <- 0;

Exceptions:
none
Opcodes:

CRC

Calculate Cyclic Redundancy Check

Description:
The CRe of the data stream described by the string descriptor is
calculated.
Ihe initial CRC is given by inicrc and i~ normally 0 or -1
unless the eRC is calculated in several steps. Ihe result is left in
RO.
i f the polynomial is less than order-32,
the result must be
extracted from the result. The eRC polynomial is expressed by the
contents of the 16-10ngword table. See the notes for the calculation of
the table.

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CYCLIC REDUNDANCY CHECK INSTRUCTION
Notes:
1.

If the data stream is not a multiple of 8-bits long, it must be
right adjusted with leading zero fill.

If the CRC polynomial is less than order 32, the result must be
extracted from the low order bits of RO.

The following algorithm can be used to calculate the eRC
given a polynomial expressed as follows:

table

polyn(n> (- tcoefficient of x**{order -1-n)}
This routine is available as system library routine
LIB$CRC_l'ABLE (poly.rl, table.ab). The table is the
location of a 64-byte (16-longword) table into which
the result will be written.

SUBROUTINE LlB~CRC~rABLE (POLY, TABLE)
INTEGER*4 POLY, lABLE(0:15), lMP, X
DO 190 INDEX = 0, 15

150
190

TMP = lNDEX
DO 150 I = 1, 4
X = TMP . AND. 1
!logical shift right one bit
TMP = ISHFT(TMP,-1)
IF (X .EQ. 1) TMP = TIvlP . XOR. POLY
CONTINUE
TABLE (INDEX) = TMP
CONTINUE
RETURN
BND

The following
polynomials.

are

descriptions

some

commonly

used

eRG

CRC-16 (used in DDCMP and Bisync)
polynomial:
poly:
initialize:
resul t:
CCITT

x 16 + x 15 + x 2 + 1
120001 (octal)

RO(15:0)

(used in ADCCP, hDLC, SDLC)
polynomial:
poly:
initialize:

x 16 + x 12 + x 5 + 1
102010 (octal)
-1<15:0>

,', I

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Instructions
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CYCLIC REDUNDANCY CHECK INSTRUCTION
resul t:

one's complement of RO<15:0>

AUTODIN-il
polynomial:

x~j2+x~26+XA23+x~22+XA16+XA12

poly:
initialize:
resul t:

EDBo8320 (hex)
-1<31:0>
one's complement of RO<31:0>

+xA11+x~10+x~b+xA7+xA5+x~4+xA2+x+1

This instruction produces an UNPREDICTABLE result unless the
table is well formed, such as produced in note 3. Note that
for any well formed table, entry [0] is alw'ays 0 and entryl8]
is always the polynomial expressed as in note 3. lhe operation
can be implemented using shifts of one, two, or four bits at a
time as follows:
shift
( s)

steps
table index
per byte
(limit)

table index
multiplier
(i)

tmp3<O)

tmp3<1:0>

tmp3<3:0>

use table
entries

[O)~
[0 )

,[4],l8],L12]

all

If the stream has zero length, HO receives the initial CRG.

DO NOT COpy

COI'1PANY CONl.'IDENT1AL

CHAPTER 4
iNSTRUCTIONS

2-Nov-78 -- Rev 5

*~*-****************************~********************.*

*.
*
*
*

THROW THIS PAGE AWAY.
This is the fifth part of Chapter 4.

*
i

**************************~****************************

Page 1

Digital Equipment Corporation COMPANY CONFlDENTIAL

Title:

VAX-11 Decimal String Instructions -- Rev 5

Specification Status:

Fully Approved

Architectural Status:

under ECO control

File:

SR4ER5.RNO

PDI"'! II: not used

Date:

~-Nov-'1b

Superseded Specs:

Rev 4

Author:

Strecker / 1.

Typist:

Call

Reviewer(s):

Abstract:

Rarich

R. Blair, R. Brender, D. Cane, K. Chapman, P. Conklin,
D. Cutler' , R~ Grove, T. Hastings, D. Hustvedt, J. Leonar'd,
P. Lipman, ~l. Payne, D. Rodgers, S. Rothman, B. Stewart,
E. Strecker

Revision History:
Rev IF
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5

Description
Initial distribution of SRM
ECOs 1-11
ECOs 12-1b, April Meeting,
and Hay 25 lVleeting
Packed Decimal Standard
Additions to CIS Instructions
Typos

Author
Strecker
Strecker
Strecker

Revised Date
25-Sep-'15
16-Mar-76
10-Jun-76

Rarich

15-F'eb-77

Bhandarkar

2:-Nov-78

Instructions
2-NOv-78 -~ Rev' 5
Change History for Decimal String

Page 4~990

Rev 4 to Rev 5:
1.

l'ypos

Rev 3 to Rev 4
1.

Change Numeric string to'l'railing Numeric

Change CVTNP & CVTPN To CVT'l'P & CVTPT.

Add Leading Separate String converts CVTSP,CVTPS

ASHP now treats -0 overflow like all other instructions.

MULP & DIVP now produce +0 unless decimal overflow occurs.

All operations now produce +0 unless decimal overflow occurs.

Define reserved operand and overflow handling once at beginning
of section.

Add note on convert
registers and overlap.

discuss

use

Add clarifying notes at the beginning of the
length strings etc.

section

zero

10.

Add note on overlap with eMPP instruction.

11.

Change zoned to packed operations (decimal data ECO).

12.

Clarify -0 in
attachment) .

data

ECO

13.

Clarify overflow as non-zero digits, not significant digits.

14.

Leave eVILP address in R3 not R1.

15.

ASHP changed to include rounding operand.

all

to/from

results

and

longword

sources

(decimal

Rev 2 to Rev 3:
1.

Reserved operand aborts become faults

Add empty section for ED1TN

Change pointer to longword or address;

Add MINU function in ISP

Explicitly give SEXl or ZEXT in all cases needed

make it 32 bits

Page 4-991

lnstructions
2-Nov-'l8 -- Rev 5
Change History for Decimal String

Specified condition codes on all exceptions

Lower limit on decimal string length is 0

Digits not checked by numeric instructions

Remove HULN4, DIVN4;

10.

Clobber R2, R3 in CVTLN, CVTNL

11.

CVTNL returns correctly signed low
overflow

12.

Remove CVTLU, CVTPU, ASHU;
to CVTLN, CVTPN~ ASHN

13.

Split into separate specifications

Rev 1 to Rev 2:
See CH4A for changes
LEnd of SR4ER5.RNO]

change names to iv'iULN, DIVN

order

bits

of result

change names of CVTLS, CV'l'PS,

ASHS

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Page 4-166
DECIMAL STRING INSTRUCTIONS
4.12

DECIMAL STRING INSTRUCTIONS

Decimal string instructions operate on Packed Decimal strings.
Convert
instructions are provided between Packed Decimal and Trailing Numeric
String (Overpunched and Zoned) and Leading Separate Numeric string
formats. Where necessary a specific data type is identified. Where the
phrase decimal string is used, it means any of the three data types.
A decimal string is specified by 2 operands:
1.

For all decimal strings the length is the number of digits in
the string. The number of bytes in the string is a function of
the length and the type of decimal string referenced (see
Chapter 2).

The address of the lowest addressed byte of the string.
Ihis
byte contains the most significant digit for Trailing Numeric,
and packed decimal strings. This byte contains a sign for Left
Separate Numeric strings. The address is specified by a byte
operand of address access type.

Each of the decimal string instructions uses general registers RD
through R3 or RD through R5 to contain a control block which maintains
updated addresses and state during the execution of the instruction. At
completion, the registers containing addresses are available to the
software to use as string specification operands for a subsequent
instruction on the same decimal strings.
During the execution of the instructions, pending interrupt conditions
are tested and if any is found, the control block is updated. First
Part Done is set in the PSL, and the instruction interrupted (See
chapter
6).
After
the
interruption,
the instruction resumes
transparently. The format of the control block at completion is:
j

+---------------------------------------------------------------+
o
+---------------------------------------------------------------+
ADDRESS 1
+---------------------------------------------------------------+
o
+---------------------------------------------------------------+
ADDRESS 2
+---------------------------------------------------------------+
o
+---------------------------------------------------------------+
ADDRESS 3
+---------------------------------------------------------------+

RO
R1

R3
R4

The fields ADDRESS 1, ADDRESS 2 and ADDRESS 3 (if required) contain the
address of the byte containing the lowest addressed byte. in the first~
second and third (if required) string operands respectively.

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Page 4-167
DECIMAL STRING INSTRUCTIONS
The decimal string instructions treat decimal strings as integers with
the decimal point assumed immediately beyond the least significant digit
of the string. If a string in which a result is to be stored is longer
than the result, its most significant digits are filled with zeros.

4. 12. 1 Decimal Over flow""
Decimal overflow OC,9t1rs if the destination string is too short to
contain all the/non-zero digits "of the result.
un overflow, the
destination strip-B; is replaced by the correctly signed least significant
digits of theiesult (even if the/result is -OJ. Note that neither the
high nibble of an even length packed decimal string, nor the sign byte
of 2 Leading Separate Numeric string is used to store result digits.

4.1~.2

~ero

Numbers

A zero result has a positive s1gn for all operations which complete
without decimal overflow.
How~ver,
when digits are lost because of
overflow, a zero result receives the sign (positive or negative) of the
correct result.
A decimal string with value -0 is treated as identical to a decimal
string with value +0. 'rhus for example +0 compares equal to -0. When
condition codes are affected on a -0 result they are affected as if the
result were +0: i.e., ~ is cleared and Z is se~.

4.12.3

Reserved Operand Exception

A reserved operand fault occurs if the length of a decimal string
operand is outside the range 0 through 31, or if an invalid sign or
digit is encountered in CVTSP, and CVTTP.

4.12.4

UNPREDICTABLE Results

The result of any operation is UNPREDICTABLE if any source decimal
string operand contains invalid data. Except for CVTSP and CVTTP, the
decimal string instructions do not verify the validity of source operand
data.
If the destination operands overlap any source operands, the result of
an operation will, in general, be UNPREDICTABLE.
~'he destination
strings, registers used by the instruction and condition codes will, in
general, be UNPREDICTABLE ,when ~ reserved operand fault occurs. )

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DECIMAL STRING lhSTRUCTIONS

4.12.5

Packed Decimal Operations

Packed decimal strings generated by the decimal string instructions
always have the preferred sign representation: 12 for 11+" and 13 for
"_". An even length packed decimal string is always generated with a
"0" digit in the high nibble of the first byte of the string.
A packed decimal string contains an invalid nibble if:
1•

A digit occurs in the sign position.

A sign occurs in a digit position.

oJ·

4.12.6

For an even length string, a non-zero nibble occurs in the high
order nibble of the lowest addressed byte.

Zero Length Decimal Strings

The length of a packed decimal string can be O. In this case, the value
is zero (plus or minus) and one byte of storage is occupied. This byte
must contain a "0" digit in the high nibble ·and the sign in the low
nibble.
The length of a trailing numeric string can be O.
1n this case no
storage is occupied by the string. If a destination operand is a zero
length trailing n~~eric string, the sign of the operation is lost.
Memory access faults will not occur when a zero length trailing numeric
operand is specified because no memory reference occurs.
The length of a Leading Separate Numeric string can be O. In this case
one byte of storage is occupied by the sign. Memory is accessed when a
zero length operand is specified, and a reserved operand fault will
occur if an invalid sign is detected.
The value of a zero length
decimal string is identically O.

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DECIMAL STRlNG INSTRUCTIONS

MOVP

Move Packed

format:
opcoae len.rw, srcaddr.ab, dstaddr.ab
Operation:
({dstaddr + ZEXT(len/2)} : dstaddr) (({srcaddr + ZElT(len/2)} : srcaddr);
Condition Codes:

<- tdst string} LSS 0;
Z <- {dst string} EQL 0;

V <- 0;
C <- G;
It:xceptions:
reserved operand
Opcodes:
l'riUVP

Nove Packed

Description:
The destination string specified by the length and destination address
operands is replaced by the source string specified by the length and
source address operands.
Notes:
1.

After execution:
RO = 0
R1

= address of the byte containing the most
significant digit of the source string

R3 = address of the byte containing the most
significant digit of the destination string.
2.

The destination string, RO through R3, and the condition codes
are UNPREDICTABLE if the destination string overlaps the source
string, the source string contains an invalid nibble, or a
reserved operand fault occurs.

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DECIMAL STRING INSTRUCTIONS

If the source is -0, the result is +0,
set.

is cleared

and

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DECIMAL STRING INSTRUCTIONS

CMPP

Compare Packed

li'ormat:
opcode len.rw, src1addr.ab, src2&ddr.ab

3 operand

opcode src11en.rw, src1addr.ab, src21en.rw,
src2addr. a b

4 operand

Operation:
(isrc1aOdr' + ZEXT(len/2)} : src1addr) ({ src2addr + ZEXT (len/2)} : src2addr);

({src1addr + ZEXT(src11en/2)} : srcladdr) ({ src2addr + ZEXT (src21en/2)} : src2addr);

operand
14 operand

Condition Codes:
N <- {src1 string} LSS lsrc2 string} ;
Z <- tsrc1 string} EQL {src~ string} ;

V <- 0;

C <- O·,

Exceptions!
reserved operand
Opcodes:
CMPP3
CMPP4

35
3'7

Compare Packed j Operand
Compare Packed 4 Operand

Description:
In 3 operand format, the source 1 string specified by the length and
source 1 address operands is compared to the source 2 string specified
by the length and source 2 address operands.
the only action is to
affect the condition codes.
In 4 operand format, the source
string specified by the source
length and source 1 address operands is compared to the source 2 string
specified by the source 2 length and source 2 address operands.
The
only action is to affect the condition codes.
Notes:
1.

After execution of CMPP3 or CMPP4:
HO = 0
R1

= address of the

byte containing the most

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DECIMAL STRING INSTRUCTIONS
significant digit of string 1.
R2

R3 = address of the byte containing the most
significant digit of string 2.
2.

HO through R3 and the condition codes are UNPREDICTABLE, if the
source strings overlap, if either string contains an invalid
nibble or if a reserved operand fault occurs.

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DECIMAL STRING lNSTRUCTIONS

ADDP

Add Packed

Format:
opcode addlen.rw, addaddr.ab, sumlen.rw,
sumaddr.ab
opcode add1Ien.rw, add1addr.ab, add2Ien.rw,
add2aadr.ab, sumlen.rw, sumaddr.ab
Operation:
({sumaddr + ZEXT(sumlen/2)} ; sumaddr) (({sumaddr + ZEXT{sumlen/2)}
sumaddr) +
({addaddr + ZEXT{addlen/2)} : addaddr); 14 operand

~~V'-

( {sumaddr + ZEXT (sumlen/2 )} : sumaddr) <({add2addr + ZEXT(add2len/2)}
add2addr) +
({add1addr + ZEXT(add11en/2)} : add1addr);

l6 operand

Codes:

N <- {sum string} LSS 0;
Z <- tsum string} EQL 0;
V <- tdecimal overflowJ;
C (- 0;
Exceptions:
reserved operand
overflow

~ Idecimal
'Ij

Opcodes:
20

ADDP4
ADDP6

Add Packed 4 Operand
Add Packed 6 Operand

Description:
In 4 operand format, the addend string specified by the addend length
and addend address operands is added to the sum string specified by the
sum length and sum address operands and the sum string is replaced by
the result.
In 6 operand format, the addend 1 string specified by the addend 1
length and addend 1 address operands is added to the addend 2 string
specified by the addend 2 length and addend 2 address operands. The sum
string specified by the sum length and sum address operands is replaced
by the result.

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Notes:
1.

After execution of ADDP4:
flO

= address of the byte containing the most
significant digit of the addend string

R2 = 0

R3 = address of the byte containing the most
significant digit of the sum string

After execution of ADDP6:
RO

= address of the byte containing the most
significant digit of the addend1 string

R3 = address of the byte containing the most
significant digit of the addend2 string

R4 = 0

R5 = aaaress of the byte containing the most
significant digit of the sum string

The sum string, flO through Rj (or RO through R5 for ADDP6) and
the condition codes are uNPREDICTABLE if the sum string
overlaps the addend, addend1, or addend2 strings; the addend,
addend1, addend2 or sum (4 operand only) strings contain an
i,nvali,d nibble; or a reserved operand fault occurs.

If all destination 'dIgIts are zero, Z is set and N is
This is true even if the result overflows.

cleared.

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DEC1MA0 STRING INSTRUCTIONS

SUBP

Subtract Packed

Format:
opcode sublen.rw, subaddr.ab, diflen.rw,
difaddr .ab

4 operand

opcode sublen.rw, subaddr.ab, min1en.rw,
minaddr.ab, diflen.rw, difaddr.ab

6 operand

uperation:
({difaddr + ZEXT(diflen/2)j : difaddr) <({difaddr + ZEXT (dif1en/2)}
diraddr)( t subaddr . . . ZEXT (sublen/2 )} : subaddr); ! 4 operand
(tdifaddr + ZEX1(dif1en/2)} : difaddr) <({minaddr + ZEXT(min1en/2)}
minaddr)
l{subaddr + ZEXT(sub1en/2)} : subaddr); !6 operand
Condition Codes:
N <- {dif string} LSS 0;
Z <- {dif string} EQL 0;
V <- tdecima1 overflow};
C <- 0;
Exceptions:
reserved operand
decimal overf1o'Vl
Opcodes:
22
2j

SUbP4
SUBP6

Subtract Packed 4 Operand
Subtract Packed 6 Operand

Description:
In 4 operand format, the subtrahend string specified by subtrahend
length and subtrahend address operands is subtracted from the difference
string specified by the difference length and difference address
operands and the difference string is replaced by the result.
In 6 operand format, the subtrahend string specified by the subtrahend
length and subtrahend address operands is subtracted from the minuend
string specified by the minuend length &nd minuend address operands.
The difference string specified by the difference length and difference
address operands is replac,ed by the resul t.

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DECINAL STRING INSTRUCTIONS
Notes:
1.

After execution of SUBP4:
flO

= address of the byte containing the most

significant digit of the subtrahend string

R2 = 0

R3 = address of the byte containing the most

significant digit of the difference string

After execution of SUBP6:
HO

= address of the byte containing the most
significant digit of the

subtrahend string

R2 = 0

R3 = address of the byte containing the most
significant digit of the minuend string
R4 = 0
R5 = address of the byte containing the most
significant digit of the difference string
j.

The difference string, HO through R3 (RO through R5 for SUBP6),
and the condition codes are UNPREDICTABLE if the difference
string overlaps the subtrahend or minuend strings;
the
subtrahend, minuend, or difference (4 operand only) strings
contain an invalid nibble; or a reserved operand fault occurs.
If all destination digits are zero, ~ is set and N is
This is true even if the result overflows.

cleared.

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DECiMAL STRING INSTRUCTIONS

MULP

Multiply Packed

Format:
opcode mulrlen.rw, mulraddr.ab, muld~en.rw,
muldaddr.ab, prodlen.rw, prodaddr.ab
Operation:
({prodaddr + ZEXT(prodlen/2)} : prodaddr) <llmuldaddr + ZEXT(muldlen/2)}
muldaddr) *
({mulraddr + ZEXT(mulrlen/2)} : mulraddr);
Condition Codes:
N <- {prod string} LSS OJ
Z <- {prod string} EQL OJ

V <- {decimal overflow};
C <- 0;
Exceptions:
reserved operand
decimal overflow
Opcodes:

MULP

Multiply Packed

Description:
The multiplicand string specified by the multiplicand length and
multiplicand address operands is multiplied by the multiplier string
specified by the multiplier length and multiplier address operands. The
product string specified by the product length and product address
operands is replaced by the result.
Notes:
1.

After execution:
RO = 0
R1

= address of the byte containing the most

significant digit of the multiplier string

=0
R3 = address of the byte containing the most

Significant digit of the multiplicand string

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R5 = address of the byte containing the most
significant digit of the product string
2.

The product string, }to through R5, and the condition codes are
UNPREDICTABLE if the product string overlaps the multiplier or
multiplicand strings, the multiplier or multiplicand strings
contain an invalid nibble, or a reserved operand fauLt occurs.

• "IT "all destination digits are zero, Z is set and"NI's"cTeared:-

Ihis is true even if the result overflows.

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DECIMAL STRING, l~STRUCTIONS

DIVP

Divide Packed

F'ormat:
opcode divrlen.rw, divraddr.ab,divdlen.rw,
divdaddr.ab, quolen.rw, quoaddr.ab
Operation:
({quoaddr + ZEXl(quolen/2)} : quoaddr) <({divdaddr + ~EXT(divdlen/2)}
divdaddr) I
(tdivraddr + ZEXl'(divrlen/2)} : divraddr);
Condition Codes:
N <- {quo string} LSS o·,
Z <..- iquo string} EQL O·,

V <- {decimal overflow} ;
C <- O·,
Exceptions:
reserved operand
decimal overflow
divide by zero
Opcodes:

DIVP

Divide Packed

Description:
The dividend string specified by the dividend length and dividend
address operands is divided by the divisor string specified by the
divisor length and divisor address operands.
The quotient string
specified by the quotient length and quotient address operands is
replaced by the result.
Notes:
1.

This instruction allocates a 16 byte workspace on the stack.
After execution SP is restored to its original contents and the
contents of {(SP)-16}:{(SP)-1} are UNPREDICTABLE.

The division is performed such that:
1.

The absolute value of the remainder (which is lost) is less
that the absolute value of the divisor.

The product of the absolute value of the quotient times the
absolute value of the divisor is less than or equal to the
absolute value of the dividend.

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The sign of the quotient is determined by the rules of
algebra from the signs of the dividend a.nd the divisor. If
the value of the quotient is zero, the sign is always
positive.

ilfter execution:
RO = 0
R1

= address of the byte containing the most significant
digit of the divisor string

R3 = address of the byte containing the most significant
digit of the dividend string

R4 = 0

R5 = address of the byte containing the most significant
digit of the quotient string.

The quotient string,RO through R5, and the condition codes are
UNPhEDICTABLE if the quotient string overlaps the divisor or
dividend strings, the divisor or dividend string contains an~ L_ d-invalid nibble, the divisor is 0 or a reserved operand ~~r
occurs.

(""J"J~"I'f>"'~ii'''-destination digits are zero, Z is set and N is
This is true even if the result overflows.

cleared.

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VAX-11

CVTLP

Convert Long to Packed

li'ormat:
opcode grc.rl, dstlen.rw, dstaddr.ab
Operation:
({dstaddr + ZEXT(dstlen/2)}

dstaddr) <- conversion of src;

Condition Codes:
N <- {dst string} LSS 0;

Z <- tdst string} EQL 0;
V <- tdecimal overflow} ;

C <- o·,

Exceptions!
reserved operand
decimal overflow
Opcodes:

CVTLP

Convert Long to Packed

Description:
The source operand is converted to a packed decimal string and the
destination string operand specified by the destination length and
destination address operands is replaced by the result.
t-Jotes:
1•

After execution:

RO = 0
R1

R3 = address of the byte containing the most significant
digit of the destination string
2.

¢~

The destination string, RO through
and the condition
are UNPREDICTABLE on a reserved operand fault.

/3 "Tf' all destination digits are zero, Z is set and N is
(,:ThiS is true even if the result overflows.

codes

cleared.

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DECIMAL STRING INSTRUCTIONS
4.

Overlapping operands produce correct results.

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DECIHAL STRING INSTRUCTIONS

CVTPL

Convert Packed to Long

Format:
opcode srclen.rw, srcaddr.ab, dst.wl
Operation:
dst <- conversion of ({srcaddr + ZEXT(srclen/2)}

srcaddr) ;

Condition Codes:
N <- dst LSS 0;

dst EQL O·,

Z <-

V <- tinteger overflow};

C <- 0;

Exceptions:
reserved operand
integer overflow
Opcodes:
CVTPL

Convert Packed to Long

Description:
The source string specified by the source length and source address
operands is converted to a longwora and the destination operand is
replaced by the result.
Notes:
1.

After execution:

HO = 0
R1

= address of the byte containing the most significant
digit of the source string

R3 = 0
2.

The destination operand, RO through. Rj, and the condition codes
are UNPREDICTABLE on a reserved operand fault or if the string
contains an invalid nibble.

The destination operand is stored after the registers are
updated as specified in 1 above. Thus RO through R3 may be
used as the destination operand.

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DECIMAL STRING INSTRUCTIONS
4.

If the source string has a
value
outside
the
range
-2,147,48j,648 through 2,147,48j,647 integer overflow occurs
and the destination operand is replaced by the low order j2
bits of the correctly signed infinite precision conversion.
Thus, on overflow the sign of the destination may be different
from the sign of the source.

Uverlapping operands produce correct results.

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D~CIMAL STRING INSTRUCTIONS

CVTPT

Convert Packed to Trailing Numeric

Forma.t:
opcode srclen.rw, srcaddr.ab, tbladdr.ab, dstlen.rw, dstaddr.ab
Operation:
{dst string} <- conversion of {src string};
Condition Codes:
N <- {src string} LSS 0;
2.

<- {src string} EQL O·,

V <- {decimal overflow} ;

C <- 0;

Exceptions:
reserved operand
decimal overflow
Opcodes:

CVTPT

Convert Packed to Trailing Numeric

Description:
the source packed decimal string specified by the source length and
source address operands is converted to a trailing numeric string. The
destination string specified by the destination length and destination
address operands is replaced by the result. the condition code Nand Z
bits are affected by the value of the source packed decimal string.
Conversion is effected by using the highest addressed byte of the source
string (i.e., the byte containing the sign and the least significant
digit) as an unsigned index into a 256 byte table whose zeroth entry
address is specified by the table address operand. The byte read out of
the table replaces the least significant byte of the destination string.
The remaining bytes of the destination string are replaced by the ASCII
representations of the values of the corresponding packed decimal digits
of the source string.
Notes:
1.

After execution:

RO = 0
R1

= address of the byte containing the most significant
digit of the source string

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R2

R3 : address of the most significant digit of the
destination string
2.

The destination string, RD through R3, and the condition codes
are UNPREDICTABLE if the destination string overlaps the source
string or the table, the source string or the table contains an
invalid nibble, or a reserved operand fault occurs.

The condition codes are computed on the value of the source
string even if overflow results. In particular, condition code
N is set if and only if the source is non-zero and contains a
minus sign.

by appropriate specification of the table, conversion to any
form of trailing numeric string may be realized. See Chapter 2
for the preferred form of trailing overpunch, zoned and
unsigned data.
1n addition, the table may be set up for
absolute value, negative absolute value or negated conversions.

If decimal overflow occurs, the value stored in the d~stination
may be different from the value indicated by the condition
codes (Z and N bits).

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DECIMAL STRING I~STRDCTIONS

CVTTP

Convert Trailing Numeric to Packed

Format:
opcode srclen.rw, srcaddr.ab, tbladdr.ab, dstlen.rw, dstaddr.ab
Operation:
{dst string} <- conversion of {src string}
Condition Codes:
{dst string}LSS 0;
Z <- idst string} EQL 0;
V <- tdecimal overflow} ;

N <-

C <- O·,

Exceptions:
reserved operand
decimal overflow
Opcodes:
26

CV'I'TP

Convert Trailing Numeric to Packed

Description:
The source trailing numeric string specified by the source length and
source address operands is converted to a packed decimal string and the
destination packed decimal string specified by the destination address
and destination length operands is replaced by the result.
Conversion is effected by using the highest addressed (trailing) byte of
the source string as an unsigned index into a 256 byte table whose
zeroth entry is specified by the table address operand. The byte read
out of the table replaces the highest adQressed byte of the destination
string (i.e. the byte containing the sign and the. least significant
digit).
The rema1n1ng packed digits of the destination string are
replaced by the low order 4 bits of the corresponding bytes in the
source string.
Notes:
1.

A reserved operand fault occurs if:
1.

The length of the source trailing numeric string is outside
the range 0 through 31.

The length of'the destination packed
outside the range 0 through 31.

decimal

string

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DECIMAL STRING INSTRUCTIONS

The source string contains an invalid byte.
An invalid
byte is any value other than ASCll "0" through "9" in any
high order byte (i.e., any byte
except
the
least
significant byte).

The translation of the least significant digit produces
invalid packed decimal digit or sign nibble.

After execution:

RO = 0
R1

= address of the most significant digit of the source
string

R3 = address of the byte containing the most significant
digit of the destination string.

The destination string, flO through R3, and the condition codes
are UNPRED1CTABLE if the destination string overlaps the source
strj.ng or the table, or a reserved operand faul t occurs.

If the convert instruction produces a -0 without overflow, the
destination
packed
decimal
string is changed to a - +0
representation, condition code N is cleared and Z is set.

lf the length of the source string is 0, the destination packed
decimal
string is set identically equal to 0, and the
translatidn table is not referenced.

By a.ppropriate specification of the table, conversion from any
form of trailing numeric string may be realized. See Chapter 2
for the preferred form of trailing overpunch, zoned and
unsigned data.
In addition, the table may be set up for
absolute value, negative absolute value or negated conversions.

'f.

If the table translation produces a sign nibble containing any
valid sign, the preferred sign representation is stored in the
destination packed decimal string.

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DECIMAL STRING INSTRUCTIONS

CVTPS

Convert ~acKed to Leading ~eparate Numeric

F'ormat:
opcOde srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab
Operation:
idst string} <- conversion of {src string};
Condition Codes:
N <Z (-

{src string} LSS 0;
{src string} EQL 0;
V <- {decimal overflow} ;
C <- 0;

Exceptions:
reserved operand
decimal overflow
Opcodes:

CVTPS

Convert Packed to Leading Separate Numeric

Description:
The source packed decimal string specified by the source length and
source address operands is converted to a leading separate numeric
string. The destination string specified by the destination length and
destination address operands is replaced by the result.
Conversion is effected by replacing the lowest addressed byte of the
destination string with the ASCII character '+' or 1_', determined by
the sign of the source string. The remaining bytes of the ~estination
string are replaced by the ASCII representations of the values of the
corresponding packed decimal digits of the source string.
Notes:
1•

After execution:

RO = 0
R1

= address of the byte containing the most significant
digit of the source string

R2 = 0
R3 = address of the sign byte of the destination string

Copyright(c) 1979 Digital Equipment Corp. ,t-iaynard,l'1ass.
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Instructions
2-~ov-78 -- Rev 5
Page 4-190
DEClMAL STRING INSTRUCTIONS
2.

The destination string, RO through R3, and the condition codes
are UNPREDICTABLE if the destination string overlaps the source
string, the source string contains an invalid ~ibble, or a
reserved operand fault occurs.

This instruction produces an ASCII n+" or tl_1i in the sign
of the destination string.

if decimal overflow occurs, the value stored in the destination
may be different from the value indicated by the condition
codes (Z and N bits).

if the conversion produces a -0 without
overflow,
the
destination leading separate numeric string is changed to a +0
representation.

byte

Copyright~c) 1979 Digital Equipment Corp. ,lviaynard,tliClss.
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instructions
2-1'iov-'{8 -- Rev 5
DECIMAL STRING INSTRUCTIONS

CVTSP

Page 4-191

Convert Leading Separate l~umeric to PacKed

I'ormat:
opcode srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab
Operation:
{dst string} (- conversion of lsrc string}
Condition Codes:

N <- {dst string} L5~ 0;
Z (- idst string} EQL 0;
V <- {decimal overflow};
C <.- 0;
Exceptions:
reserved operand
decimal overflow
Opcodes:

CVTSP

Convert Leading Separate Numeric to Packed

Description:

The source numeric string specified by the source length and source
address operands is converted to a packed decimal string and the
destination str.ing specified by the destination addreSS and destination
length operands is replaced by the result.
Notes:
1.

A reserved operand fault occurs if:
1.

lhe length of the source Leading Separate num€~ric string is
outside the range 0 through 31.

The length of the destination packed
outside the range 0 through 31.

The source string contains an invalid byte.
An invalid
byte is any character other than an ASCII "0" through "9"
in a digit byte or an ASCII "+", "(space)", or It_tI in the
sign byte.

After execution:

RO = 0

decimal

string

Copyright(c) 1979 Digital Equipm1ent Corp.,Naynard,1'-1ass.
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Instructions
2-~ov-78 -- Rev 5
Page 4-1S2

DECIMAL STRING INSTRUCTIONS

= address of the sign byte of the source string

=0
R3 = address of the byte containing the most significant

digit of the destination string.
~.

The destination string, HO through R3, and the condition codes
are UNPREDICTABLE if the destination string overlaps the source
string, or a r'eserved operand fault oc,-=c:. . : u:.: . r-=s:. . : .______________~

--=----------

4':-- Tne condition codes are computed on the value of the source
string even if over~flow resul t~s. lnparticular, condition code
N is set if and only,i,f the sOurce is non-zero and contains a
minus sign.

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Instructions
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DEC1MAL STRlNG INSTRUCTIONS

A,sHP

Arithmetic Shift and hound Pacl-tl~a

Format:
opcode cnt.rb, srclen.rw, srcaddr.ab, round.rb
dstlen.rw, dstaddr.ab
Operation:
(tdstaddr + ZEXT(dstlen/2)} : dstaddr) <i({srcaddr + ~EX1(srclen/2)} : srcaddr)
+ iround <3:0)*l10 ** {-cnt-111}J
it {1 0 ww cnt} ;
Condition Codes:
N <- tdst string} LSS 0;
z <- tdst string} EQL 0;
V ~- tdecimal overflow};
C <- 0;

Exceptions:
reserved operand
decimal overflow
Opcodes:
Arithmetic Shift and Round Packed

ASHP

Description:
1he source string specified by the source length and source address
operands is scalea by a power of 10 specified by the count operand. The
destination string specified by the destination length and destination
address operands is replaced by the result.
A positive count operand effectively multiplies;
a negative count
effectively divides; and a zero count just moves and affects condition
codes. ~hen a negative count is specified, the result is rounded using
the Round Uperand.
Notes:
1.

After execution:

HO = 0
Ii1

= aadress of the byte containing the most significant
digit of the source string

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Instructions
2-Nov-'iB -- Rev 5
Page 4-194
DECllVjAL STRING INSTRUCT IONS

= address of the byte containing the most significant
digit of the destination string

The destination string, hO through RS, and the condition codes
are UNPREDlCTABLE if the destination string overlaps the source
string, the source string contains an invalid nibble, or a
reserved operand fault occurs.

When the count operand is negative, the result is rounded by
decimally adding bits j:O of the round operand to the most
significant low order digit discarded and propagating the
carry, if any, to higher order digits. both the source operand
and the round operand are considered to be quantities of the
same sign for the purpose of this addition.

If bits 7:4 of the round operand are non-zero, or if bits j:O
of the round Operand contain an invalid packed decimal digit
the result is UNPREDICTABLE.

When the count operand is zero or posltlVe, the round operand
has no effect on the result except as specified in note 4.

The round operand is normally five.
Truncation
accomplished by using a zero round operand.

may

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

VAX-l1 Edit Instruction -- Rev 5

Specification Status:

Fully approved

Architectural Status:

under ECO control

File:

Page 1

SR4FR5.RNO

PDlvt i;: not. used

Date:

2-Nov-'"{b

Superseded Specs:

hev 4

Author:

Strecker

Typist:

Call

Reviewer(s):

Abstract:

R. Blair, R. Brender, D. Cane, K. Chapman, P. Conklin,
D. Cutler, R. Grove, D. Hustvedt, J. Leonard, P. Lipman,
M. Payne, D. Rodgers, S. Rothman, b. ~tewart, B. Strecker

Revision History:
Rev If
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5

Description
Initial proposal
Reduce context
Complete design
Prune
Re-issue

Author
Blair
Conklin
Conklin
Conklin

Revised. Date
Aug-75
Feb-'T6
May-76
11-Apr-'ll
2-Nov-'(tl

Instructions
Change history for Edit

Page 4-990

2-Nov-78 -- Rev 5

Rev 4 to Rev 5 :
1.

No changes

Rev 3 to Rev 4 :
1.

Drop insert zero/slash and skip zero/slash because infrequent.

Combine fixed inserts and insert

Add

protect.

one

byte

EO~,SET_SIG1~ IF.
j.

Drop move numeric or fill (can use
clear) .

EO$tvl0VE

wi th

significance

Combine move into EO$l"lOVE by setting significance.

Drop insert protection register.

Drop insert comma/period as optimizations not worth it now.

Drop byte repeats.
nibble.

hequire EO$END instead of running off the end.

Combine protection and fill into one register.

10.

Combine currency and sign into one register.
logic of floating currency and sign.

11.

Drop optimized combination of EO$BLANK_ZERO and EO$END.

12.

Heplace options and sign testing fills
EO$LOAD_MINUS.

Make repeats be 0 reserved and 1 .• 15 in low

with

This combines the

EO$LOAD_PLUS

and

The above pruning resul ts in an average gro'wth in the length of
an edit pattern string of about 4 bytes. lhis is offset by
removing two operands (typically 2 to 4 bytes).
13.

Add EO$REPLACE_SlGN to f ixup -0. '.l.'his saves about 10 bytes and
several operators over the previous proposal.

14.

Confine the pattern to associate with the field.
destination length operand and adjust destination.

Drop

15.

Drop input editting--this would be a distinct instruction
needed in volume. Change name to EDITPC.

when

16.

Map flags onto the condition codes.

17.

Do not touch R6 and R7.

lnstructions
Change History for Edit

2-Nov-7H -- Rev 5

Page 4-991

Drop flag set/clear/branch and position add/subtract.

1 c'~.

Invert sense of significance flag.

20.

Assign pattern op codes.

21.

Make 0 length
UNPREDICTABLE.

22.

Use the term nabortil rather than "fault" when wrong
input digits.

23.

Change tlUNDEFINEDu to uUNPREDICTABLEu.

24.

Add usage under notes.

25.

Restrict BO$ADJUST_1NPUT to 31 digits.

26.

Set RO-R1 at end to point to input string.

27.

Correct ISP to not increment pattern pointer at end.

28.

Add comments to pseudo ISP to aid the· initial reader.

EO$BLANK_ZER0

and

be
number

Rev 2 to Rev 3:
1.

Add option to set protection register to blank vs.
asterisk.
reason: removes unnecessary duplication of operators.

Add operator EOHNF
Y-picture.

Add option to force the sign during
handle special sign conventions.

Add operator EOl'1NFS (move numeric or floating
handle FORTRAN sign convention.

Use 86, h7 to keep extra EDlTN context.
Reason:
half of counts for normal string contents.

Change name to EDITN.

Add ability to handle variable length input and output strings.

Change to zoned sign and replace EFSS with EFSO.

~eep

10.

(move

numeric

fill).

PL/I

reason:

initialization.
sign) .

reason:
reason:

keeps

left

lengths GTRU O.

Add skip numeric to validate numeric string and skip alphabetic
for consistency.

instructions
Change History for Edit

2-~ov-'ld

Page 4-992

-- Rev 5

11.

Support packed format.

12.

Limit edit character string to 255 bytes.
sizes.

1j.

Drop move numeric or minus--can be done by selecting one of two
patterns.

This drops all

word

Rev 1 to Rev 2:
1.

Combine two instructions into one.
Make an initialization
option whether or not to examine the input for the presence of
a sign. reason: drop operation code.

Replace BWZF flag with a pattern operator to protect backward
when zero. reason: decrease context; fewer memory cycles.

Reduce context to 4 bytes of edit registers, 5 flags, and only
one hidden count.
reason:
reduce context at no loss of
functionality.

Replace pattern length operand
reason: reduce context.

Add specification of handling when input and output lengths
not match.

Avoid nibble-sized counts. Replace with byte-sized.
consistency with regular instruction set.

with

initialization

Reference edit registers by special operators
generic mechanics. reason: support of point 3.

operand.
do

reason:

rather

than

Replace
reason:

Add pattern operators to adjust source
pointers. reason: generalize and simplify.

10.

Set condition codes
to
reflect
the
result.
consistency with the rest of the architecture.

11.

Add input conversion operators.
are optionally subsettable.

12.

On numeric moves and edits, if the input is not a blank or
digit, set conversion error.
If non-zero, clear Zero flag.
reason: correct setting of condition codes.

13.

If input minus sign and not output, then set conversion
reason: correct setting of condition codes.

flag nibble with general
generalize and simplify.

set/clear

reason:

and

any

flag.

destination

completeness.

reason:
They

error.

Instructions
Change history for Edit

2-Nov-78 -- Rev 5

Page 4-993

14.

Add specification of behavior on reserved pattern
reason: allow simulation of missing operators.

operator.

15.

Use fill or protection registers
flexability.

LEnd of SR4FR5.RNOj

for

all

blanking.

reason:

VAX-11 System Reference Nanual

CHAPTER 4
INSTRUCTIONS

2-Nov-78 -- Rev 5

******~*****~*********************************~*****I**

THROW THIS PAGE AWAY.

*
*

This is the sixth part of Chapter 4.

*
*

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~nstructions
2-Nov-i8 -- Rev 5
Page 4-195

tD1T IhSTRUCTION
4.1~

EDIT INSTRUCT10N

This instruction is designed to implement the common editing functions
which occur in handling fixed format output. it operates by converting
2 packed decimal string
to a character string.
This operation is
exemplified. by a MOVE to a numeric editted (PlCTURE) item in COBOL or'
PL/l, but the instruction can be used for other applications as well.
The operation consists of converting an input packed decimal number to
an output character string, generating characters for the output.
when
converting digits, options include leading zero fill, leading zero
protection, insertion of floating sign, insertion of floating currency
symbol, insertion of special sign representations, and blanking an
entire field when it is zero.
The operands to the EDITPC instruction are an input packed decimal
string descriptor, a pattern specification, and the starting address of
the output string. The packed decimal descriptor is a standard VAX-11
operand pair of the length of the decimal string in digits (up to 31)
and the starting address of the string. The pattern specification is
the starting address of a pattern operation editing sequence which is
interpreted much the way that the normal instructions are.
The output
string is described by only its starting address because the pattern
defines the length unambiguously.
While the EDITPC instruction is operating, it manipulates two character
registers and the four condition codes. One character register contains
the fill character. This is normally an ASCII blank, but would be
changed to asterisk for check protection. The other character register
contains the sign character. Initially this contains either an ASCII
blank or a minus sign depending upon the sign of the input. This can be
changed to allow other sign representations such as plus/minus or
plus/blank and can be manipulated in order to output special notations
such as CR or DB. The sign register can also be changed to the currency
sign in order to implement a floating currency sign. After execution,
the condition codes contain the sign of the input (N), the presence of a
non-zero source (Z), an overflow condition (V), and the presence of
significant digits (e). Condition code N is determined at the sta~t of
the instruction and is not changed thereafter (except for correcting a
-0 input). The other condition codes are computed and updated as the
instruction proceeds. When the EDITPC instruction terminates, registers
RO-R5 contain the conventional values after a decimal instruction.

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Instructions
2-Nov-18 -- Rev 5
Page 4-196
EDIT INSTRUCTION

EDITPC

Edit Packed to Character String

l"ormat:
opcode srclen.rw, srcaddr.ab, pattern.ab, dstaddr.ab
Operation:
if srclen GTRU 31 then {reserved operand};
PSW<V,C> <- 0;
PSW<Z> <- 1;
PSW<N> <- {src has minus sign!;
RO <- sr'clen;
tmp1 <- RO;
R1 <- srcaddr;
R2 <- 1 rl? 1 {if PS\oJ<N> EQL 0 then It n €;lse ,,_It} ,
1<15:b>=sign, <7:0>=fill
R3 <- pattern;
H4

If.

<- ??'(;

R5 <- dstaddr;
exit_flag <- false;
while NOT exit_flag do
begin
{fetch pattern byte};
{if pattern 0:4 no operand};
{if pattern 40:47 increment R3 and
fetch one byte operand};
{if pattern 80:AF except 80, 90, AO
operand is rightmost nibble};
{else {reserved operand}};
iperform pattern operator};
if NOT exit_flag then {increment R3};
end;
if RO NEQ 0 then {reserved operand};
RO <- tmp1;
! length of source string
R1 <- R1 - ttmp1/2}
!point to start of source string
R2 <- 0;
R4 <- 0;
if PSW<Z> EQL 1 then PSyJ"<N) <- 0;
Condition Codes:
N <- {src string} LSS 0;
Z <- {src string} EQL 0;
V <- {decimal overflow};
C <- {significance};
Exceptions!
reserved operand
decimal overflow

!N <- 0 if src is -0
!non-zero digits lost

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Instructions
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EDIT INSTRUCTION

Opcodes:
EDITPC

Edit Packed to Character String

Description:
The destination string specified by the pattern and destination address
operands is replaced by the editted version of the source string
specified by the source length and source address operands.
The
editting is performed according to the pattern string starting at the
address pattern and extending until a pattern end (BO$END) pattern
operator is encountered.
The pattern string consists of one byte
pattern operators. Some pattern operators take no operands. Some take
a repeat count which is contained in the rightmost nibble of the pattern
operator itself. The rest take a one byte operand which follows the
pattern operator immediately.
This operana is either an unsigned
integer length or a byte character. The individual pattern operators
are described,;on the following pages.
Notes:
1.

A reserved operand fault occurs with FPD cleared if srclen GTRU
31. See Chapter 6 for a descrtption of reserved operand faul t's
and F'PD.

The destination string is UNPREDiCTABLE if the source string
contains an invalid nibble, if t~e EO$ADJUST_INPUT operand is
outside the range 1 through 31, if the source and destination
strings overlap, or if the pattern and destination strings
overlap.

After execution:
RO = length of source string
R1 = address of the byte containing the most
significant digit of the source string
R2

= 0

R3 = address of the byte containing the EO$END
pattern operator
R4 = 0
R5 = address of one byte beyond the last byte
of the destination string
If the destination string is UNPREDICTABLE, HO through
the condition codes are UNPREDICTABLE.

and

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Instructions
2-Nov-78 -- Rev 5
Page 4-198

EDIT iNSTRUCTION
4.

If V is set at the end and DV is enabled, numeric overflow trap
occurs unless the conditions in note 9 are satisfied.

the destination length is specified exactly by the pattern
operators in the pattern string. If the pattern is incorrectly
formed or if it is modified during the execution of the
instruction,
the
length
of
the destination string is
UNPREDiCTABLE.

If the source is -0, the resul t may be
pattern
operator
is
included
EO$REPLACE_$IGN) .

The contents of the destination string and the memory preceding
it are UNPREDICTABLE if the length covered by E;O$.BLANK_ZERO or
EO$REPLACE_S1GN is 0 or is outside the destination string.

if more input digits are requested by the pattern than are
specified, then a reserved operand abort is taken with RO = -1
and R3 = location of pattern operator which requested the extra
digit.
The condition codes and other registers are as
specified in note 11. This abort is not continuable.

If fewer input digits are requested by the pattern than are
specified, then a reserved operand abort is taken with R3 =
location of EO$END pattern operator. The condition codes and
other registers are as specified in note 11. This abort is not
continuable.

10.

On an unimplemented or reserved pattern operator, a reserved
operand fault is taken with R~ = location of the faulting
pattern operator. The condition codes and other registers are
as specified in note 11. This fault is continuable as long as
the defined register state is manipulated according to the
pattern operator description and the state specified as ??1 is
preserved.

11.

Un a reserved operand exception as specified in notes 8 through
10, FPD is set and the condition codes and registers are as
follows:
N

= {src has minus sign}

= all source digits 0 so far

v = non-zero digits lost
C = significance
HO = -zeros(15:0) , srclen(15:0)
R1

= current source location

R2 = 1?1 ' sign ' fill

unless a fixup
(EO$BLANK_ZEHO
or

-0

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Instructions
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Page 4-199
EDIT INSTRUCTION

= edit pattern operator causing exception

= '('??

R5 = location of next destination byte
where:
zeros = count of source zeros to supply
sign = current contents of sign character register

= current contents of fill character register

fill

\ The following "picture U editting is outside the scope of EDITPC:

A,X

use MOVC and MOVB

PL/l:E,K

floating point. separate into two integers

PL/l:I,R,T

overpunch. treat as 9 and fixup afterwards

V,P,PL/l:l'-'

scaling by ASHP to get correct position first

BAS1C:)

special case code

BASIC:C,L,R,E;

MOVC with special code

FORl'RAN:*

special code triggered by overflow

FORTRAN:leading -

extra byte in destination string

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lnstructions
2-Nov-'( 8 -- Rev 5
Page 4-200
EDIT lNSTRUCTION
VAX-11

Summary of EDIT pattern operators

name

operand

summary

insert:

EO$INSERT
EO$STORE_SIGN
EO$FILL

EO$MOVE
EO$FLOAT
EO$ENDJ'LOAT

r
r

insert character, fill if insignificant
insert sign
insert fill

move:
move digits, filling insignificant
move digits, floating sign
end floating sign

f'ixup:

EO$BLANK_ZERO
len
EO$REPLACE_SIGN len

r~place

EO$LOAD_FILL
EO$LOAD_SIGN
EO$LOAD_PLUS
EO$LOAD_MlNUS

load fill character
load sign character
load sign character if positive
load sign character if negative

fill backward when zero
with fill if -0

load:
ch
ch
ch
ch

control:
EO$SET_SIGNIF'

'EO$CLEAR_SIGNIF EO:jiADJUSl'_lNPUT len
EO$END
where:

set significance flag
clear significance flag
adjust source length
end edit

ch = one character
r
= repeat count in the range 1 through 15
len = length in the range 1 through 255

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instructions
2-Nov-18 -- Rev 5
Page 4-201
EDIT INSTRUCTION
VAX-11

EDIT pattern operator encoding
(hex)
00
01

EU~END_fLOAT

02
03

EO$SET_SIGNIF

EO~~STORE_.sIG.N

EO$END
EO$CLBAR_~:aGNIF

05 •• 1J.4'

Reserved to DEC

200 o3F'

Reserved for all time

40
41

EO$LOAD_FILL

£O$LOAD_PLUS
EO $L OA D_t-'llN US
EO$INSEf(l

45
46
47

EO$BLANK_ZERO

48 •• 5F

Reserved to DEC

60 .. TiP

Reserved to CSS, customers

80,YO,AO

Reserved to DEC
EO$FILL
Eu$MOVE
EO$F'LOAT

81 •• SF'
910 o9F
A10 oAF

bOo .F'E

EO~ILOAD_SIGN

:-- character is in next byte

1-- unsigned fength is in next byte

EO$REPLACE_SIGN
EO~ADJUST_INPUT

,-- repeat count is (j:O>
I

Reserved to DEC
Reserved for all time

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lnstructions
2-Nov-7~ -- Rev 5
Page 4-202
EDlT INSTRUCTION
The following pages define each pattern operator in a format similar to
that of the normal instruction descriptions. In each case, if there is
an operand it is either a repeat count (r) from 1 through 15, an
unsigned byte length (len), or a character byte (ch). In the formal
descriptions, the following two routines are invoked:

READ:

!function value 0 through 9
__>;:r
. if HO LEQ-- 0
" then
\
begin
~.__ ._.______ i f HO EQL 0 then {reserved operand};
READ <- 0;
HO<31:16> <- RO<31:16> + 1;
!see EO$ADJUST_INPUT
end;
else
begin
READ <- (R1)<3+4*RO<O>:4~RO<0»; !get next nibble
!alternating high then low
RO <- RO - 1;
if RO<O> EQL
then R1 <- R1 + 1;
end;
return;

STORE(char):
(R5) <- char;

R5 <- R5 + 1;
return;
Also the following definitions are used:
fill = R2<7:0>
sign = R2<15:b>

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Instructions
2-Nov-78 -- Rev 5
Page 4-203
EDIT INSTRUCTION
EO$INSERT

Insert Character

Purpose:
Insert a fixed
signific.: nt

character,

substituting

the

fill

character

not

Format:
pattern

Operation:
if PSW<C> EQL 1 then STORE(ch) else STORE(fill);
Pattern operators:

EO$INSERT

Insert Character

Description:
The pattern operator is followed by a character.
If significance is
set, then the character is placed into the destination. If significance
is not set, then the contents of the fill register is placed into the
destination.
Notes:
This pattern operator is used for blankable inserts (e.g.,
comma) and fixed inserts (e.g., slash). Fixed inserts require,
that significance be set (by EO$SET_SIGNIF or EO$END_FLOAT).

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EDIT INSTRUCTION
Store Sign
Purpose:
insert the sign character
ft'ormat:
pattern
Operation:
STORE (sign) ;
Pattern operators:
04

Store Sign

Description:
The contents of the sign register is placed into the destination.
~otes:

This pattern operator is used for any non-floating arithmetic
sign.
It
should be preceded by a Eu$LOAD_PLUS and/or
EO$LOAD_MINUS if the default sign convention is not desired.

Copyright(c) 1~n9 Digital Equipment Corp .. ,Haynard,l"lass.
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EDIT INSTRUCTION
EO~FILL

Store Fill

Purpose:
lnsert the fill character
Format:
pattern

Operation:
repeat r do STOHE(fill);
Pattern operators:
bx

EO$FILL

Store Fill

Description:
The right nibble of the pattern operator is the repeat count.
The
contents of the fill register 1s placed into the destination repeat
times.
Notes:
This pattern operator is used for fill (blank) insertion.

Copyright(c) 19'79 Digital Equipment Corp. ,1'1aynard,Mass.
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EDIT INSTRUCTiON

EO$MOVE

i"1ove Digits

Purpose:
Move digits, filling for insignificant digits (leading zeros)
F'ormat;
pattern

Operation:
repeat r do
begin
tmp <- READ;
if tmp NEQU 0 then
begin

PSw<Z> <- 0;
PSW<.C> <- 1;
!set significance
end;
if PSW<C> EQL 0 then STORE(fill)
else STORE ( "0" + tmp);
end;
Pattern operators:
EO$HOVE

MO-ve Digits

Description:
The right nibble of the pattern operator is the repeat count.
For
repeat times, the following algorithm is executed. The next digit is
moved from the source to the destination. If the digit is non-zero,
Significance is set and zero is cleared.
If the digit is not
significant (i.e., is a leading zero) it is replaced by the contents of
the fill register in the destination.
Notes:
1.

If r is greater than the number of digits rema1n1ng
source string, a reserved operand abort is taken.

This pattern operator is used to move digits without a floating
sign.
If leading zero suppression is desired, significance
must be clear.
If leading zeros
should
be
explicit,
significance must be set. A string of EO$MOVEs intermixed with
EO$INSERTs and EO$FILLs will handle suppression correctly.

If check protection (*) is desired
the EO$MOVE.

EO$LOAD_FILL

must

the

precede

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Instructions
EDIT

Page 4-207

INSTRUCTJ..()l~

Float Sign

EO$FLOAT

Purpose:
Move digits, floating the sign across insignificant digits
Format:
pattern

Operation:
repeat r do
begin
tmp <- READ;
if tmp NEQU 0 then
begin

._~

~i :.p~w<c> .EQ~"Q,._~~en STORE ( sign) ; ,

G~~~~~ ~= 1 ~/" >""!~;~t-';~~;~';~~:nce
eridf~~,;"";;"",,:::·;:,,,···~~''''''4

if PSW<.C> EQL 0 then STORE(fill)
else STORE("O" + tmp);
end;
Pattern operators:
Ax

EO$FLOAT

Float Sign

Description:
THe right nibble of the pattern oper~tor is the repeat count.
For
repeat times, the following algorithm is executed. The next digit frorr!"
~.~U~£~_~.~:'~~~2-n~,~~-2-£">!.t.JJa,,,,,Ilml:~~,t~~t,j~ns.L~~,gnJJJ.2xe.n£.~w_~!. ~=,."",,!22t~~,xet
~~ t. J-.."".~ hen ....tJ1,~__ ""Sl2n~,fHJJS .. gJ~"""t ll~L ..."~l~gJl,,,,,,.£~~g,l.s,t.,>e,r,,, .".~~s. .stprf:d.~"",itL",tJle
d~~~I~,9J,~,gn,. '-.,~.~~~.~~E~,:a~ce.i~ .. ~,~"~",,., . a~~","~~!:<~.J~~;.,,,9~~i!r'.eo~) If the digit is

slgnificant, it is stored in the destination, otherwise the contents of
the fill register is stored in the destination.
Notes:
1.

If r is greater than the number of digits remalnlng
source string, a reserved operand abort is taken.

the

This pattern operator is used to move digits with a floating
arithmetic sign.
The sign must already be setup as for
EO$STORE_SlGN. A sequence of one or more EO$FLOATs can include
intermixed EO$lNSERTs and EO$fi'ILLs. S!gnificanc~, mJ.!.s..t Jte ...91~~r
b~.!~!,e~~~t he,. fJ~,_JU~J~~.§rJJ~~,.,.£,E~.!:\~~£>!:_,~~~E~~!l~~~~!l.ce.
Th e
sequence must be terminated by one EO$BND_FLOAT.

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EDIT Ir~STRUCTION
~.

This pattern operator is used t6 move digits with a floating
currency
sign.
The sign must already be setup with a
EO$LOAD_SIGN. A sequence of one or more EO$FLOA'l's can include
intermixed EO$INSERTs and EO$FILLs. Significance must be clear
before the first pattern operator of the sequence.
The
sequence must be terminated by one EO$END_F'LOAT.

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End Floating Sign
Purpose:
End a floating sign operation
Format:
pattern
Operation:
if PSW(C) EeL 0 then
begin
STORE (sign);
PSv](C)

<- 1;

!set significance

end;
Pattern operators:
End Floating Sign

Description:
If the floating sign has not yet been placed in the destination ~i.e.,
. if significance is not set), the contents of the sign register is stored
in the destination and significance is set.

Notes:
This pattern operator is used after a sequence of one or more
EO~FLOAT pattern operators which start with significance clear.
The EO$fLOAT sequence can include intermixed EO$INSERts and
EO $fe' ILLs.

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EDIT INSTRUCTION
Blank Backwards ~hen Zero
Purpose:
fixup the destination to be blank when the value is zero
Format:
pattern

len

Operation:
if len t;QLU 0 then {UNPREDICTABLE};
if PSW<Z> EQL 1 then
begin
R5 <- R5 - len;
repeat len do STORE(fill);
end;
Pattern operators:
Blank Backw~rds when ~ero
Description:
The pattern operator is followed by an unsigned byte integer length. If
the value of the source string is zero, then the contents of the fill
register is stored into the last length bytes of the destination string.
Notes:
1•

The length must be non-zero and within the destination string
already
produced.
i f it is not,
the contents of the
destination string
and
the
memory
preceding
it
are
UNPREDiCTABLB.

This pattern operator is used to blank out any characters
stored in the destination under a forced significance, such as
a sign or the digits following the radix point.

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EDIT INSTRUCTION
EU$REPLACE_SlGN Replace Sign When~s Zero
Purpose:
Fixup the destination sign when the value is ~~ zero
format:
pattern

len

Operation:
if len EQLU 0 then {UNPREDICTABLEY/
if PSw(Z)' EQL 1
p,a,?tl:~" ~then
(R5 -len) <- fl~ ;

Gia

Pattern operators:
EO$REPLACE_SlGN Replace Sign When

Zero

Description:
The pattern operator is followed by an unsigned byte integer length. If
the value of the source string is ~ zero (i.e., if &4f'eh N .HUI Z ~.l
set), then the contents of the fill register is stored into the byte of
the destination string length before the current position.
Notes:
1•

The length must be non-zero and within the destination string
already
produced.
If it is not, the contents of the
it
are
destination string
and
the
memory
preceding
UNPREDlCTABLE.

This pattern operator ~ used to correct a stored sign
( EO $END_r-'LOAT or EO$STORE_SIGN) if a minus was stored and the
source value turned out to be zero.

~b-v

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EDIT INSTRUCTION
EO$LUAD_

Load Register

Purpose:
Change the contents of the fill or sign register
Format:
pattern

Operation:

Iselect one depending on pattern operator

fill <- ch;

! EO%;LOAD_~'ILL

sign <- ch;

I EO$LOAD_SIGN

if PSW<N> EQL 0 then sign <- ch;

I EO$LOAD_PLUS

if PSW<N> EQL

I EO$LOAD_MINUS

then sign <- ch;

Pattern operators:
40
41

EO$LOAD_FILL
EO~LOAD_SIGl~

EO$LOAD_PLUS
EO$LOAD_MINUS

42
4j

Load Fill Register
Load Sign .Register
Load Sign Register If Plus
Load Sign Register If Minus

Description:
The pat tern operator is followed by a. character. r~or Eu$LOAD_FILL this
character is placed into the fill register. 1"or EO$LOAD_SIGN this
character is placed into the sign register.
14'0('
EO$LOAD_PLUS this
character is placed into the sign register if the source string has a
posi ti ve sign. F'or EO$LOAD_MINUS this character is placed into the sign
register if the source string has a negative sign.
Notes:
1.

EO$LOAD_~'ILL

is used to setup check protection

(it

instead

space) .
2.

EO$LOAD_SIGN is used to setup a floating currency sign.

EO$LOAD_PLUS is used to setup a non-blank plus sign.

EO$LOAD_MINUS is used to setup a non-minus minus sign (such
CR, DB, or the PL/I +).

Copyright(c) 1979 Digital Equipment Corp. ,Maynard,t1ass.
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EDIT l.NSTRUCTI0N
Significance
Purpose:
Control the significance (leading zero) indicator
Format:
pattern
Operation:
!EO$CLEAR_SlGNlF
PSw<c>

<- 1;

Pattern operators:
02

EO~\CLEAR_SIGNIF

EO$SE1'::...SlGNIF

Clear Significance
Set Significance

Description:
The significance indicator is set or cleareo.
This controls the
treatment of leading ~eros (leading zeros are zero digits for which the
significance indicator is clear).

Notes:
1.

EU$CLEAR_SIGNIF' is used to initialize leading zero suppression
lEO~MOVE)
or floating sign (EO$FLOAT) following a fixed insert

(EO$INSERT with significance set).
2.

EO$SET_SIGNIF is used to avoid leading zero suppression (before
EO$MOVE) or to force a fixed insert (before £O$lNSERT).

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EDIT INSTRUCTlON
EO$ADJUST_INPUT Adjust Input Length
Purpose:
Handle source strings with lengths different from the output
l·'ormat:
pattern

len

Operation:
if len EQLU 0 or len GTRU 31 then {UNPREDICTABLE!;
if RO(15:0> GTRU len
then
begin
RO<31 : 16> <- 0
repeat RO<15:0> - len do
if READ NEQU 0 then
begin
PSW<Z> <- 0;
!set significance
PSW<C> <- 1 ;
PSW<V> <- 1 ;
end;
end;
!negative of number to fill
else RO<j1:16> <- RO<15:0> - len;
Pattern operators:
47

EO$ADJUST_INPUT Adjust Input Length

Description:
The pattern operator is followed by an unsigned byte integer length in
the range 1 through ::;1. If the source string has more digits than this
length, the excess digits are read and discarded.
i f any discarded
digits are non-zero then overflow is set J significance is set, and zero
is cleared. If the source string has fewer digits than this length, a
counter is set of the number of leading zeros to supply. This counter
is stored as a negative number in RO<31:16>.
Notes:
If length is not in the range
through 31 the destination
string, condition codes, and RO through R5 are UNPREDICTABLE.

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EDIT INSTRUCTION
EO$END

End Eait

Purpose:
End the edit operation
F'ormat:
pattern
Operation:
exit_flag <- true;

!terminate edit loop
lend processing is
!described under EDITPC instruction

Pattern operators:

EO$END

Ena Edit

Description:
lhe edit operation is terminated.
Notes:
1.

If there are still input digits a
taken.

reserved

operand

abort

If the source value is -0, the N condition code is cleared.

Copyright(c) 1979 Digital Equipment Corp.,t-'laynard,Nass.
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COMPANY CONfIDENTIAL

CHAPTER 4
INSTRUCTIONS

26-0ct-78 -- Rev 5

*
*it
**

THROW THIS PAGE AWAY.
This is the seventh part of Chapter 4.

*'
*'
*
*
*

***********************************************-*******

Digi tal Equipment Corporation COlvlPANY CONF'IDENTIAL

Title:

Other VAX-11 instructions -- Rev 5

Specification Status:

Fully approved

Architectural Status:

under ECO control

File:

PagE:; 1

SR~GR5.RNO

PDM IF: not used

Date:

26-0ct-78

Superseded Specs:

Author:

Abstract:

Ehandarkar

Chapt~r

4 describes the instructions generally used by all
software
across
all
implementations
of'
the
VAX-11
architecture.
For convenience of review and
editting,
chapter 4 is separated into a number of specifications. This
section contains a list of i~structions specified in other
chapters of this document.

Revision History:
Rev If

Rev 5

Description
Initial distribution

Author
Bhandarkar

Revised Date
26-0ct-'/o

Copyright(c) 1979 Digital Equipment Corp. ,t-laynard,Mass.
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Instructions
26-0ct-78 -- Rev 5
Page 4-216
OTHER VAX-11 INSTRUCTIONS

4.13

OTHER VAX-11 INSTRUCTIONS

The following instructions are
document as indicated below.

specified

other

chapters

this

Opcode

IVlnemonic

Instruction

OC
OD

PROBEl<
PROBEW

Probe Read Accessibility
Probe Write Accessibility

5
5

REI

Return from Exception or Interrupt

BC
BD
BE
SF

CHMK
CHME
CHMS
CHMU

Change Node to Kernel
Change Mode to Executive
Change Node to Supervisor
Change Mode to User

LDPCTX
SVPCTX

Load Process Context
Save Process Context

MTPR
MFPR

Move To Processor Register
Move F'rom Processor Register

orr

DA
DB

(End of Chapter 4]

Chapter

6
6

r,
'i

9
9

Digital ~quipment Corporation COMPANY CONFIDENTIAL

Title:

,Page 1

VAX-l1 Memory Management -- Rev 4

Specification Status:
Architectural Status:
File:

under ECO control

SR5R4.V09

PDM ,: not used
Date:

30-Jul-7b

Superseded Specs:
Author:

Lipman

Typist:

8ess/D,

Reviewer(s):

Abstract:

Lindorfer

P. Conklin,
P. Lipman,
B. Strecker

D. Cijtler, ,

D. Roqgers,

D. Hustv~dt,
S. Rothman,

J. Leonard,.,
B. Stewart,

Chapter 5 de~cribes the memory mapping
and
memory
protection mechanisms of the VAX~11 series. The areas
covered include the descr~ption of the virtqal address
space, the translatioQ of virtual address to phYsical
address, the protection of pag~s according to access mode,
and the PROBE instruction.

Revision History:
Rev /I
Rev
Rev 2
Rev j
Rev 4

Description
Original
Per ECO's 1-10
~edesign-~er April 1'a sj( Force
Document Registers

Author
Hastings
Hastings
~ipQlan

Conklin/Taylor

t{evised Date

Oct-75
Mar-76
4""Jun-76
jO-Jul-'/8

Memory Management
Change history

Page 5-990

jO-Jul-78 -- Rev 4

Rev ~ to Rev 4:
~;

Typos.

PTE(24:23> now
untested MBZ.

f~r

s~ftware

use;

<25>

and

(22:21>

are

-<
..,;.

include boot initial state.

Correct picture formats.

Add descriptions
TBIA, and TB1S.

Add picture of stack on fault.

Add example of translation.

Cleanup the description of PROBE.

POLR(26:24> and P1LR<31> ignored on MTPR.

10.

PRuBE uses only mode<1:0>;

11.

Remove redundant, confusing pseudo flows.

12.

Remove some argumentative justifications.

13.

Specify which registers are read/write, etc.

14.

SLR is checked on process page table references.

15.

Clarify address on fault.

16.

M not necessarily maintained in SPT of process page tables.

17.

Add software mnemonics.

10.

SWU bits renamed to OwN and reserved for owning access mode.

19.

M update is not interlocked in multiprocessor.

20.

Add comments on accesses across page boundaries.

translation

buffer,

unmapped,

MAPEN,

ignores rest of operand.

Rell 2 t~ Rev j:
1.

Eliminate the concept of segments, moving protection
page level

the

Streamline the virtual to physical address translation by
eliminating references to the PCB and Internal Segment Table.

Memory Management
Change History

30-Jul-78 -- Rev 4

Remove access level from virtual address

Eliminate Pointer Segments and Stack Segments

Add mode operand to PROBE

Assign codes to protection field

Change sense of condition codes on PROBE

PROBE length is unsigned

Protection field is valid even if v=o.

10.

P1BR specifies lowest (unused) address in Pl-Space

11.

Modify bit moved to page table entry

12.

Memory Mapping Enable Bit

Rev 1 to Rev 2:
1.

Remove execute protection

Added flows for translation

[End of SR5R4.RNO]

Page 5-991

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CHAPTER 5

MEMORY MANAGEMENT

30-Jul-78 -- Rev 4

5.1

INTRODUCTION

This chapter describes the memory mapping and memory protection
mechanisms of the VAX-11 series. The VAX-11 memory manag~ent ha~ the
following goals:
1.

Provide a large address space for in~tructions and data.

Permit most software to be run on all implementations
a large range Of hardware cost.

Allow data structures up to one gigabyte.

Provide convenient and efficient sharing of in~tructions
data.

Contribute to software reliability.

across

and

A virtual memory system is used to provide a large addre~s space,
while
allowing programs to run on small memory size hardware
configurations. Programs are executed in an execution environment
termed a process. The software operating system uses the mechanisms
described in this chapter to provide each process with a 4 billion
byte address space.
The virtual address space is divided into two equal size address
spaces, the proces~ address space and the system address space. The
~ystem address space is the same for
all processes.
The operating
system is in the system address space and is written as callable
procedures. Thus all system code is available to all other system and
user code using a simple CALL. The process address space is separate
for each process. However, several processes may have access to the
same page, thus providing controlled sharing.

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Memory Management
30-Jul~78 -- Rev 4
Page 5-2
IhTRUDUCTION
To improve s~ftware reliability 4 hierarchical layers of memory access
privilege are provided by the access mode mechanism. Protection is
specified at the individual page level. For each of the four access
levels, a page may be inaccessible, read-only, or read-write. Any
location accessible to a lesser privileged mode is also accessible to
all more privileged modes.
Furthermore for each access mode, any
l~cation that is writable is also readable.

5.2

VIRTUAL ADDRESS SPACE

The address space seen by the programmer is a linear array of
4,294,~67,296
bytes.
A virtual address is a j2 bit unsigned integer
specifying a byte location in the address space.
lhis virtual address space is too large to be contained in any
presently available main memory. hence a means f'or mapping the active
part of the virtual address space to the available physical add~ess
spt;e is required.
Also, protection between processes is required.
The operating system controls the memory management tables that map
virtual addresses into physical memory addresses. The inactive but
used parts of the virtual address space are mapped by the operating
system ont~ external storage media.
The virtual address space is
broken into 512 byte units termed pages. The page is the unit of
relocation and protection. See section 5.4 for a description of the
address translation process.
lhe virtual address space is split into two parts. The lower half is
distinct for each process running on the system, while the upper half
is shared by all pr~cesses.

5.2.1

Process Space

lhe lower half is termed "process space". Each process has a separate
2ddress translation map for per process space, so the per process
spaces of all processes are completely disjoint (see 5.ti.j for
controlled sharing in per process space). The address map for per
process space is context Switched when the process running on the
system is Changed (see chapter,).
Process space is split by bit 30 into two regions termed the PO and P1
regions of the process virtual address space. See section 5.4.j.

5.2.2

~ystem

Space

The upper half of the virtual address space is termed "system space".
All processes use the same address translation map for system space,
so system space is shared among all processes. The address map for
system space is n~t context switched.

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Mem~ry Management
jO-Jul-78 -- Rev 4
Page 5~j
VIRTUAL ADDRESS SPACE

5.2.3

Page Pr~tection

Independent of its l~cation in the virtual address space a page may be
pr~tected
accoraing to its use. Thus even though all of' the ~ystem
space is shared, in that the program may generate any address, the
program may be prevented from modifying, or even accessing portions of
it. A pr~gram may als~ be prevented from accessing or modifying
portions of per process space.
For example, in system space, scheduling queues are highly proteQted,
whereas library routines may be executable by code of any privilege.
Similarly per process accounting information may be in per process
space, but highly protected, while normal user code in per process
spaces is executable at low privilege.

5.2.4

Virtual Address

In ~rder to reference each instruction and operand in memory the
pr~cessor
generates a j2-bit virtual address that has the follow~ng
format:
3

9 is

1
VP~

byte

+---------------------------------------------+---------.-------+

5.2.5

VPN

<31:9>

The Virtual Page Number field speoifie& the
virtual page to be referenced.
There are
2i*23 {i.e. 8,388,608) pages in the virtual
address space.

Byte II

<6:0>

The byte number field
address within the page.
bytes.

the byte
A page oontains 512

specifie~

Virtual Address Space Layout

Access to each of the three regi~ns (PO, P1, System) is controlled by
a length register (POLR, P1LR, SLR) (see section 5.3.3). Within the
limits set by the length registers, the access is controlled by a page
table that specifies the validity, acces~ requirements, and location
of each page in the region.

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1979 Digital Equipment Corp.,Maynard,Mass.

VAX-11 ~ystem Reference Manual

Memory Management

DO NOT COPY

COlvlPA:t-4Y CONFIDENTIAL

30-Jul-'/8 -- Rev 4

Page 5-4

VIRTuAL ADDRESS SPACE

00000000

+----------------------------------------------length of PO Region
in pages (POLR)

PO
Region
Pr?cess
Space
(context
s'Witched)

PO Region
gro'Wth direction
I

: 3FFFFFFF'

+~-~-~~-~~~--~~~-----~--~~-~---------~----------

140000000
Pl ftegion

growth direction
P1

Region
length of P1 Region
in pages (2*~21-P1LR)
'IF'FFFfi'FF

80000000

+----------------------------------------------length of System Region
in pages (SLR)

Region
System Hegion
growth direction

.system

: EfF'fFft'Ff

Space

+----.-----------------------------------------:COOOOOOO

Reserved
Region

+----------------------------------------------figure 5-1
Virtual Address Space

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Memory Management
30-Jul-78 -- Rev 4
Page 5-5
ACCESS CONTROL

5,3 ACCESS CONTROL
Access control is the function of validating whether a particular type
of memory access is to be allowed to a particular page. Every page
has associated with it a protection code that specifies for each mode
whether or not read or write references are allowed. Additionally,
each address is checked to make certain that it lies within the PO,
P1, or system region.

5.3.1

Mode

There are 4 hierarchically ordered modes in the processor.
in the order of most privileged to least are:

The

modes

o - Kernel - used by the kernel of the operating system for

page

management, scheduling, and 1/0 drivers.
1 ~ Executive - used for many of

the operating system
calls including the record management system.

- used
-. Supervisor
interpretation.

""t

User - used for
debuggers, etc.

user

services

such

for

level

code,

utilities,

service
command

compilers,

The mode at which the processor is currently running is stored in the
Current Mode field of the Proqessor Status Longword (PSL) (see Chapter
6) ,

5.3.2 Protection Code
Associated with each page is a protection code that describes the
accessibility of the page for each mode.
The protection codes
available allow choice of protection for each access level within the
following limits:
1.

Each level's
no-access.

access

can

read-write,

If any level has read access then all more privileged
also have read access.

If any level has write access then all more privileged levels
also have write access.

read-only,

levels

This results in 15 possibilities. The protection code is encoded in a
4 'bit field in the Page Table Entry (see 5 .ll. 1) as follows:

Copyright (c) 1 ~j'/ 9 Digital Equipment C')rp., I"synard, Mass.
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VAX-l1 System Reference Manual
CuMfhNY CONF1DENTIAL
Memory Management
jO-Jul-'(b -- Rev 4
Page 5-6
ACCESS CONTROL

CODE
Ml\El"!CNlC
Dt;CIHAL B.lNARY

a
2
)

4
5
6
'f
d
~

10
11
12
ij

14
15

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
'10'0
1011
1100
1101
1110
1111

no ACCESS

KR
UW

R
Rw
RW
RW
R
RW
RW
RW
R
RW

Ew
ERK'w

ER
SW
SREW
SRKW
8R

URSW

UREW
lJRKw
UR

are

ALL ACCESS

Rw
R
R

R
R

Rw
RW

R
R
R

R
R

·R

R\~

K - Kernel
E - Executive

S ... Supervisor
U - User

defined

This code was ch')sen to
checking reasonablE for
The access is allo~ed if:

RESERVED

UNPREDICTABLE

- no access
R - read only
Rw - read wri,te
S')ftware symbols
mnemonics.

COMMENT

using PTE;})K_ as a prefix to the above

keep the complexity of hardware access
implementations not using a table decoder.

{CODE N~~U o} AND
{{CODE EQLU 4} UR {eM LSSU WM} OR {READ AND {CM LEQU RM}}}

eM is current mode
RM is left 2 bits of code
WM is one's complement of right 2 bits of c')de

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ACCESS CONTROL
5.~.j

Length Violation

Every virtual address is constrained to lie within one of the valid
addressing regions (PO, P1, or System). The algorithm for making
these checks is a simple limit check. The formal notation for this
check is:
case VAddr<~1:jO>
set
LOJ:
!PO region
if ZExT( VAddr<29:9> ) GEQU POLR
then {length violation};
[1]:
!P1 region
if ~Exl( VAddr<29:9> ) LSSU P1LR
then {length violation};
L2J:
1S region
if ZEXT( VAddr<29:9> ) GEQU SLR
then {length violationl;
Ljj:
!reserved region
ilength violation};
tes;

5.j.4

Access Control Violation Fault

An access control fault occurs if the current mode of the PSL and the
protection field(s) for the page(s) about to be accessed indicate that
the access would be illegal (see 5.6). A fault of this type will also
occur if the address causes a length violation to occur.

5.4

ADDRESS TRANSLATlON

The action of translating a virtual address to a physical address is
governed by the setting of the Memory Mapping Enable (MME) bit (see
section 5.5.1). \+then t"lME is 0 the low order bits of the virtual
address are the physical address and there is no page protection, The
This section describes
number of bits is implementation dependent.
the address translation process when ~~E is 1.
The address translation routine is presented with a virtual address,
an intended access (read or write) and a mode against which to check
that access. If the access is allowed and the address maps without
faulting,
the output of this routine is the physical address
corresponding to the specified virtual address.
The mode that is used is normally the Current Mode field of
but per process page table entry references use Kernel mode

the

PSL

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ADDRESS

TRANSLATIO~

The intended access is read if the operation to be performed is a
read.
The intended access is write if the operation to be performed
is a write. If, however, the operation to be performed is a modify
(i.e.
read follo~ed by write) the intended access for the read
portion is specified as a write.

5.4.1

Page Table Entry (PTE)

All virtual addresses are translated to physical addresses by means of
a Page Table ~ntry (PTE) that has the following format.
j

2 222 2 222

1 0

765 4 j 2 1 0

+-+-------+-+-+---+---+-----------------------------------------+
Iv: PROT lMIO:OWNl 0 l
PFN
+-+-------+-+-+---+---+-----------------------------------------+
valid bit - governs the validity of the M bit
and PFN field.
V=1 for valid, V=O for not
valid.

Valid

<:'1>

PROT

<30:27> protection field - this field is always valid
and is used by the hardware even when V=O (see

5.3.2).
t-'10dify

<26>

modify bit - set if page has already been
recorded as modified.
M=O if page has not
been recorded as modified. Used by hardware
only if V=1.
Hardware sets this bit on a
valid, access allowed memory access associated
with a modify or write access, and optionally
on a PROBEW or implied probe-write.
~f
a
write or modify reference crosses a page
boundary and
one
page
faults,
it
is
UNPRBDICTABLE whether PTE(M> for the other
page is set before the fault.
It is UNPREDlCTABLE whether the modification
of a process PTE M bit causes modification of
the system PTE that maps that process page
table.
Note that the update of the M bit is
not interlocked in a multiprocessor system.

OWN

<24:23> reserved for software use as the access mode
of the owner of the page (i. e ., the mode
allowed to alter the page); not examined or
altered by hardware.

PFN

<20: 0>

Page r~rame Number - the upper 21 bits of the
physical address of the base of the page.
Used by hardware only if V=1.

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Page 5-9
ADDRESS TRANSLATION

Bits 25 and 22:21 are reserved to DIG1TAL and
must
be
zero.
The
hardware d~es not
necessarily test that these are zero because
the PTE is established only by privileged
software.

Software symbols are defined for the above fields using
prefix.

5.4.2

PTE$

the

System Space Address Translation

A virtual address with <31:30>=2 is an address in the

system

virtual

address space.

332
9 8

109

+---+-----------------------------------------+-----------------+
I 2 :
:
Byte ,
I <-------System Virtual Page No. (SVPN)------>:

+---+-----------------------------------------+-----------------+
The system virtual address space is defined by the System Page Table
(SPT), which is a vector of Page Table Entries (PTE's). The physical
base address of the SPT is contained in the System Base Register
(SBR).
The size of the SPT in longwords, i.e., the number of PTE'S,
is contained in the System Length Register (SLR). The PTE addressed
by the SBR maps the first page of System Space, i.e., virtual byte
address 8000000Q(hex).
j 3 2
109

210

+---+-------------------------------------------------------+---+
;MBZI
Physical Longword Address
IMBz:
+---+-~------~-~~~~~--~----~--~---------~~------------ ------+---+

(read/write)
System Base Register (SBR)
3

2 2

2 1

+--~----------------+-------------------------------------------+

fvlliZ

Length of SPT in longwords

+-------------------+-------------------------------------------+
(read/write)
System Length Register (SLR)
The virtual page number is bits <31:9> of the virtual address.
However, system virtual addresses have VAddr<31:30>=2. Thus, there
CQuid be as many as 2**21 pages in the system region~ (Typically the
value is in the range of a few hundred to a few thousand system pages

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ADDRESS TRA~~LATION
(see section 5.b).) A 22 bit length field is required to express the
values 0 through 2idi21 inclusive. At bootstra.p time, the contents of
b~th registers is UNPREDICTABLE.
j j 2
109

9 b

+---+--------------------+--------+
byte

: 2 :

SVA:

(System VirtUal
Address)

+---+--~-------~~~-------+~-~~-- ~+
I

212
):2

E.xtract and
Check Length

2110

+--------+--------------------+--+
o
: 01
+--------+--------------------+--+
Add

+-----------------------------+--+
Phys Base Adr of SfT
: 01
+-----------------------------+--+

SBR:

Yields

+-----------------------------+--+
Phys Adr of PTE
I 01
+-----------------------------+--+
fetch

C; 2
1 0

check access

PTt.:

+-+--------+--------------------+
Pf'N
+-+--------+--------------------+
I

jl2

1 Ol~

Phys Adr ~f Data:

I
I

~Ib

V 0

+---+--------------------+--------+
I 0 :
+---+--------------------+--------+

Figure 5-2a
System Virtual to Physical Translation
Thus, the arithmetic necessary to generate a physical address
system region virtual address is:

frl')m

!System Region

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ADDRESS TRANSLATION
5.4.3

Process Space Address Translation

The process virtual address space is split into two separatelf mapped
regi~ns
according to the setting of bit 30 in the process virtual
address. If bit jO is 0, the PO region ~f the address space is
selected and i f bit 30 is 1, the P1 region is selected.
The PO region of the address space maps a virtually contiguous area
that begins at the smallest address (0) in the process virtual space
and grows in the direction of larger addresses. In contr~st, the P1
region of the address space maps a virtually contiguous area that
begins at the largest address (2**31-1) in the process virtual space
and grows in the direction of smaller addresses.
each region (PO and P1) of the process virtual space is desqribed by a
virtually contiguous vector of Page Table Entries. In oontrast with
the System Page Table which is addressed with a physical address,
these two page tables are addressed with virtual addresses in the
system region of the virtual address space. Thus for Process Space
the address of the PTE is a virtual address in System Space and the
fetch of the PTE is simply a fetch of a longword using a system
virtual address.
There is a particularly compelling reason to address process page
tables in virtual rather than physical space. A physically addressed
pr~cess page table that required more than a page of PTE's (l.e., th~t
mapped more than 6~K bytes of process virtual space) would require
physically contiguous pages. Such a requirement would make qynamic
allocation ~f process page table space very awkward.
A process space translation that causes a translation buffer miss will
cause one mem~ry reference for the process PTE associated with this
translation (see 5.5.2).
If the virtual address of the
page
containing the process PTE is also missing from the translation
buffer, a second memory reference is required to fetch the system fTE
for the system virtual address of the process PTE. When a process
page table entry is fetched, a reference is made to system space.
Ihis reference is made as a kernel read.
Thus the system p,ge
containing a process page table is either "No Access"
(i.e.,
protection
code
zero) or will be accessible (protection 90de
n~n-zero).
Similarly, a check is made against the system page table
length register (SLR).
Thus, the fetch of an entry from a process
page table can result in access or length violatiQn faults (see
stction 5.b).

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Page 5-12
ADDRESS TRANSLATlON
5.4.4

PO Space

The PO region of the address space is mapped by the PO Page Table
(POP1) that is defined by the PO Base Register (POBR) and the PO
Length Register (POLfi). POBR contains a virtual address in the system
half of the virtual address space which is the base address of POPT.
POLR contain the size of POPT in longwords, i.e., the number of page
table entries.
The PTE addressed by POSR maps the first page of the
PO region of the virtual address space, i.e., virtual byte address O.
j

3 2
210

109

+---+-------------------------------------------------------+---+
I 2 I
System Virtual Longword Address
IMBZ:
+---+-------------------------------------------------------+---+
(read/write)
PO Base Register (POBR)

3
1

2 2
',6

2 222
4 3 2 1

+---------+-----+---+-------------------------------------------+
:
NBZ
: IGN IMBZ:
Length of POPT in longwords
:
+---------+-----+---+-------------------------------------------+
(read/write)
PO Length Register (POLR)
The virtual page number is bits <29:9> of the virtual address.
Thus,
there could be as many as 2**21 pages in the PO region. A 22 bit
length field is required to express the values 0 through 2**21
inclusive.
POLR<26:24>&re ignored on lvlTPR and reads back 0 on MFPR.
At bootstrap time, the contents of both registers is UNPREDICTABLE.
(An ,attem?t ,to load POB~ with a value less than 2**31 or greater than
'" ~**j1+2**jO:-;1\ results ln a
reserved
operand
fault
in
some
\ lmplementations.
\.....

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COMPANl CONFIDENTIAL
M.eD1~ry Management
30-Jul-7t3 -- Rev 4
Page 5-13
PO V~rtual to Physical Translation

:; 3 2

PYA:
(.ProGes~

t,>yte

l 0 I

Virt ua 1,

9 8

109

+---+-~---------------.--+--------+
I

Addres:a)

212
312

3
1

POBR:

Extract and
Check L~ngth

I
I

2110

I 0:

Sys Virt Base Adr of POPT

I 01

Yields
, I

I
I

Sys Virt Adr of PTE

: 01

Fetch by Algorithm in 5.4.2
including length and
access checks, in K mode

3 3

2 2
1 0

1 0

PTE:

:1I

PFN

Oheck acoess

this access check
: in current mode

1
I
I

312

1 019
Phys Adr of Data:

I
I
I

918

: 0 I
+---+--------------------+--~-----+

F;igure 5-2b
PO Virt~al to Physical Translation

Thus, the arithmetic necessary to generate a physical address

from

PO region virtual address is:

= POBR+4*PVA(29: 9>
!PO Region
PTE~PA
= (SBR+4*PVA~PTE(29:9»(20:0>tPVA-PTE<tl:0>
PROC_PA = (PTE_PA)<20:0>'PVA<8:0>
PYA_PTE

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Page 5-14
AUDRE~S TRANSLATION
5.4.5

Pl Space

The Pl region of the address space is mapped by the Pl Page Table
tP1PT) that is defined by the Pl Base Register (P1BR) and the Pl
Length Register (P1LR). Because Pl space grows backwards and because
a consistent hardware interpretation of the base ana length registers
was desired, P1BR and P1LR describe the portion of Pl Space that is
not accessible. P1ER contains a virtual address of what would be the
PTE for the first page of Pl,
i.e.,
virtual
byte
address
40000000(hex). P1LR contains the number of non-existent PTE's.
Note that the address in P1BR is not necessarily an address in
Space, but all the addresses of PTEs must be in System Space.

System

210
+----------------~-----~~~~-----~~~------~~~-~~-~---~--~~-~-+---+

Virtual Longword Address

IMBZ:

+-------------~---------------------~-~------~---~---~------+-~-+
~1

3 3

2 2

1 0

2 1

(read/write)
Base Register (P1BR)

+-+-----------------+-----~----~---~-~--~--~--~-~~-~~-~------~~-+

III

2**21 - Length of P1PT in longwords

+-+-----------------+---------.-~------~~~-~-~----~-----~~------+

(read/write)
P1 Length Register (P1LR)
At bootstrap
P1LR<jl> is ignored on MIPR and reads back 0 on MFPR.
time, the contents of both registers is UNPREDICTABLB. An attempt t~
1030 PlbR with a value less than 2**31-2**23 ('lF800000, hex) or
greater than 2-*jl+2-*30-2**2j-1 results in a reserved operand fault
in some implementations.

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Page 5 ... 15
Pl Virtual to Physical Translation

332
109

I 1

PYA:

byte

(Process Virtual
Address)

9 8

,
I

2:2

312

Extract and
Check Length

2110

I 0I
Add

PlbR:

I 0:

Base Adr of P1PT

~hys

Yields
Sys V1rt Adr of PTE

I 0:

f!'etoh by Algor! thm in 5,4.2
including length and
access checks, 1nk mode

3 S

2 2

1 0

PTE:
check access 1 this acce$S check
1 in current m?de
I
I

:> :,12
1 019

Phys Adr of Data:

I
I
I

918

I
~
I .

V 0

I 0 I
Figure 5-2c
P1 Virtual to Physical Tr9n~lation

Thus, the arithmetic necessary to genera.,te a physioal addres$

from

P1 region virtual address is:
PYA_PTE

PTE_PA
PROC_PA

= ~1BR+4*PVA<29:9>
!P1 Region
= (SBR+4*PVA_PTE<29: 9> )<20: 0> 'PVA_PTE<6; 0>
= (PTE_PA)·<20:0)'PVA<b:O>

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MEMORY MANAGEMENT CONTROL
5.5

MEMORY MANAGEMENT CONTRUL

There are three additional privileged registers used to control the
memory management hardware.
One register is used to enable and
disable memory management, the other tw~ are used to clear the
hardware's address translation buffer when a page table entry is
changed.

5.5.1

Memory ~~nag€ment Enable

The privileged register MAPEN contains the value of 0 or
according
to whether the memory management described in the rest of this chapter
is disabled or enabled respectively.
j

1 0

+--------------------------------~----------------------------+-+

HBZ

: t'l:
iM:

IE:

+-------------------------------------------------------------+-+
(read/write)
Map Enable Register (MAPEN)
At bootstrap time, this register is initialized to O.
When memory management is disabled, virtual addresses are mapped to
physical addresses by ignoring their high order bits. All accesses
are allowed in all modes and no modify bit is maintained.

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MEMORY MANAGEMENT CONTROL
5.5.2

Translation Buffer

In ~rder to save actual memory references when repeatedly referencing
pages, a hardware 'implementation may include a mechanism to remember
successf~l virtual address
translations and page states.
Such a
mechanism is termed a translation buffer.
Whenever the process context is loaded with LDPCTX the translation
buffer is automatically updated (i.e., the process virtual address
translations are invalidated). However, whenever a page table entry
for the system or current process regions is changed other than to set
PTE<V> the software must notify the translation buffer of this by
moving a virtual address within the corresponding page into TBIS.
Whenever the location or size of the system map is changed (SBR, SLR)
the entire translation buffer must be cleared by moving 0 into TSIA.
Since the contents of the translation buffer at bootstrap time is
UNPREDICTABLE, the entire translation buffer must be cleared by moving
o into TBIA before enabling memory management.

1
~z

(write only)
Translation Buffer Invalidate All (TBIA)

Virtual Address
(write only)
Translation Buffer Invalidate Single (TBIS)

5.6

FAULTS AND PARAMETERS

There are two types of faults associated with memory mapping and
protection (see Chapter 6 for a description of faults). A Translation
Not Valid Fault is taken when a read or write reference is attempted
through an invalid PTE (PTE<31>=O). An Access Control Violation Fault
is taken when the protection field of the PTE indicates that the
intended access to the page for the specified mode would be illegal.
Note that these two faults have distinct vectors in the System Control
Block.
If both Access Control Violation and Translation Not Valid
faults could occur, then the Access Control Violation Fault takes
precedence.
An Access Control Violation Fault is also taken if the
virtual address referenced is beyond the end of' the associated page

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FAuLTS AND PARAMETERS
table.
~uch
a "length violation" is essentially the same as
referencing a PTE that specifies tiNo Access" in its protection field.
T') avoid having the fault s')ftware redo the length check a "length
violation" indication is stored in the fault parameter word described
below.

+---------------------------------------------------------+-+-+-+
o
l~dP:L: :(SP)
+~----~------~---------~---------~~--~~-~----~~~~~~~~~-~--+~+-+-+

s')me virtual address in the faulting page
+----------------------------~--~--~-------~~--~~~-----~----~---+
PL t') f faul ting instruction

+-------------------------------~----~-~~------~~-------~--~--~-+

P3L at time of fault

+---------------------------------------------------------------+
The same parameters are stored for both types of fault. The first
parameter pushed ')n the Kernel stack after the PSL and PC; is some
virtual address in the same page as the initial virtual address that
caused the fault. A process space reference can result in a system
space virtual reference for the PTE. If the PTE reference faults, the
virtual address that is saved is the process virtual address.
1n
addition a bit is stored in the fault parameter word indicating that
the fault occurred in the PTE reference.
The sec~nd parameter pushed on the Kernel stack contains the following
inf')rmation:
L

<0)

Length Violation - Set to 1 to indicate that
an Access Control Violation was the result of
~ length violation rather
than a protection
violation.
This bit is always 0 for a
Translation Not Valid Fault.

<1>

PTE Reference - Set to 1 to indicate that the
fault occurred during the reference to the
process page table associated with the virtual
address.
This can be set on either length or
protection faults.

<2)

Write ')r Modify Intent - Set to 1 to indicate
that the program's intended 2ccess was a writ€'
or modify. This bit is 0 if the program's
intended access was a reed.

l?pyright(~)

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VAX..,11 ~ystem Reference Nanual
hem">ry Man~gement
,)O ... Jul ... ·, ~ - ... Rev 4

5.~
~. {.1

PRIVIL~G~D ~~HV~CE~

ANV ARGUM~hT VALIDArlO~

Changing Modes

are f'?ur instructi?ns pr?viaed t? all?w a program to change the
at which it is running to a m?re privileged mode and transfer
c?ntrol t? a service dispatcher for the new m?de. These instructions~
In~re

m?de

ChMl(

ChME
CHMS

CHMu

change m")oe to Kernel
change m?de to Exec
change mode to ~uper
ch:;lngc m?de t? User

that !re described in detail ~n Chapter 6, pr?vide the only mechanism
for less privileged c?de to call more privileged cOde. When the mode
transit!?n takes pl~ce the previous mode is saved in the Previous Mode
field of the P~L thu~ all?wing the more privileged code to determine
the privil~ge of its caller,

5. '(.;2

Va.l.id.~,ting

Address Argum~nts (PROBE Instructi?ns)

1wo instructi?ns, PROBER and PR05~W, are praviaed to allow privileged
services to qheck addresses passea as p~ram€ters. To avoid protection
holes in the system a service routine must ~lways validate that its
les~
privileged call~r could ha~e directly referenced tile addresses
passeQ as peramet~rs ls€e ApP$ndix J).

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PRIVILEGED SERVICES AND ARGUMENT VAL10ATlON

PROBE·

Probe aocessibility

Format:
opcode

mod€.rb, len.rw, base.ab

Operation:
prob_mode <- NAXU (mode< 1 : 0>, PSL<PRV_1"10D»
condition codes <- {accessibility of base} and
{accessibility of lbase+Z~Xl(len)-1}}
using probe_mode
Condition Codes:
N <- 0;

Z <.- if {both accessible! then 0 else 1 ,•

V <- 0;

C <- C;
Exceptions:
translation not valid
Opcodes:
OC

PROBER
PROBEW

Probe Read Accessibility
Probe write Accessibility

Description:
The PROBE instruction checks the read or write accessibility of the
first and last byte specified by the base address and the zerO
extended length. The protection is checked against the mode specified
in the mode operand which is restricted (by maximization) from being
more privileged than the Previous Mode field of the PSL.
Note that
probing with a mode operand of 0 is equivalent to probing the mode
specified in PSL <PRV_fvl0D>.
The following flows describe the operation ?f PROBE on each of the
virtual addresses it is checking~ Note that probing an address only
returns the accessibility of the page(s) and has n~ affect on their
residency.
1.

Lookup the virtual address in the translation buffer.
If
found, use the associated protection field to determine the
accessibility and EXIT.

Check for length violation for System ~r Per-Process address
as appropriate. See 5.5.2 and 5.5.) for the length viol~tion
check flows. If length violation then return No Access and

EXIT.

Copyrigpt(c) 1979 Pj,e;ita~ f;qulp11J.ent ~Ol"p"t1aynard,Mass.
DO ~OT COpy
VAX-11 Syste~ Iieference Manual
COM-PAN'X CONFIDENl'.l.AL
MemQry Manc;gement
30"",Jul-78
,key 4
P;:;.ge 5-21
PR1V1LEGED SERV1CES AND ARGUM~ht VALIDAT10N
'!"' ...

~f' Systiem virtual aqQres$, f?l"l!l phY$ical address of PTE
(see
5.5.2), fetc~the Fti, use the protection field to determine
the accessibility and EXiT,

for fer'!"'ir~ce~s virtual addres~, mu~t
referen~e f~r

do a virtu&l memory

the PT~.

LOQkup th~ virtua~ addresSQf the PTE in the translation
buffer, fQrm the physical address of the PTE if found,
fetch the PTE, u~e the protection field to Qetermine the
access1billty and ~Xll.

Cheq~

th$ System virtual address of toe PTE for length
violati?n ~~*e 5.~.~), ~f length violation, then return
No Aeee$$ .n~ IXIT. \This length violatiQn is clearly an
?p~rat.lngsy~tem errt)r" and Sh!?uld never happen.
Perhaps
it should fa.ul t. \

T1.Page Table Entrr for the

page

containing

the

p~r"!' pr~('HHU3 fT~,

If the protectiQn field Qf 11 indicates' no access (not
even re.da~le by Ker"e~)~ then return No Aocess and EX1!.
A no ~oceSStnQt valid p,inter to a page of PTE's saves a
page full of no .oa~ss, not valid PTE's.

If the valid bit 1n Tl 1~ 0, then take a Translation Not
Valid Fal.lltand EX1T. Th~e case allows for the demand
Pliins of per~,r~cess pase tables.

F~nal~',

o.lo~late

the
phYsical
address
Qf
the
toe PF~ field ')f 11 (see 5.5.2),
fetcb the '~I, use the protection field to determine the

per ... pr~oe~~

PtE

fro~

BQcesslbility, an4 EllT.

Copyright(c) '979 Digital t.:quipmeTlt Corp. ,~~&ynard,Hass.
1.)0 NOT COPY
VAX ... " ~ystem Hef'erenc€ lVanual
COt-lPANY CUNFIDEN'XIAL
Memory Managemerit
iO-Jul-~e -- Rev 4
Page 5-22
PR~V!L~GED SERVICE~ A~D AHGUME~l VAL!DAT10N

5.7.3

hotes On The PROBE lnstructions
1.

The valid bit of the page
address is ignored.

A length v-iolation gives a status of "not~acces·sible.1t

On the probe of a process virtual address, if the valid bit
of the system page table entry is clear then a Tra"nslation
Not Valia Faul.t occurs. This allows for the oemand paging of
the process page tables.

On the probe of a pr?qe~s virtual address, if the protection
field of the system page table entry indicates No Access,
then a status?f " n ot .. accessible-' is given. Thus, a single
No Access page table entry in the system map is equivalent to
12~ No Access page table entries in the process map.

it is UNPREDiCTAbLE whether the Hodify bit
page table entry is set by a ~ROBEW.

5.d.l

t2.ble

entry

mapping

the

probed

examined

Physically (;~ntiguous System Page Table

During the design the issue was raised that a physically based
physically c0ntiguous SPT might require a 12rge amount of memnry to
handle a reas~nable number of very big proceSses.

Si ze (;f SPl' - '1'0 examine the size 0f SPT, note first
page ~f SP! maps b4 K6 0f system virtual address space.
mapped in the system virtual space?
5. b. 1. 1

1•

Operating System 1~l')de and data (€xclud ing

memory

that
What is

management

data) - 64 Kb to 96 KB, 1 to 1.5 pages.
2.

...;'

Memory Management Data for physical page management • 4 to b
longwords per physical page of memory. 0ne l?ng~ord of page
t~ble maps 1 page of memory management data which handles
24
physical pages of memory. 1 page of page table handles ~K
physical pages = 1.5 ~B of physical memory
Shared (,;ode
1.

command interpreter

debugger

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-l1 System Reference Manual
COMPAN~ CONFIDENTIAL
Memory Management
30-Jul-78 - ... Rev 4
Page 5 ... 23
ISSUES

record manager

GTSt s FORTRAN, COBOL, BASIC

Allowing 16 KB for each of the above items, the total
KB or 1 1/2 pages of SPT.
4.

Procfss Page Tables
One l:1ngword of SPT maps one page of process page table which
in turn maps 64 Kb of process virtual address space. Sixteen
longwords of SPT maps 1 MB of process virtual address space.
One page of SPT maps 8 MB. A very straight forward balance
set management design that reserved a fixed (SYSGE,N) number
of balance set slots each with a fixed (also SYSGEN) ~a~imum
virtual address space would use only 2 pages of SPT to allow.
16 processes of up to 1 MB each in the balance set.

lt would appear from the foregoing analysis that a 6 page SPT would
handle a very reasonable system and increasing the 1 MB proc~ss
virtual space to 4 MB and 16 processes in the balance set would add
only 6 more pages of SPT for a total of 12. A smaller system with 256
KB of memory and 8 balance set processes each 512 KB maximum size
would need about 3 pages of SPT.

,.8.2

Access Across A Page Boundary

If an access is made across a page boundary, the order in which the
pages are accessed is UNPREDICTABLE.
However, for a given page,
access control violation always takes precedence over translation not
valid.

5.ti.3

Sharing

To discuss sharing, it is useful to assume the concept of a saction in
the operating system.
A section is a collection of pages that have
some relationship to each other. Though units as small as pages may
indeed be shared, sections are the usual unit of sharing.

5.b.j.1 Shared Section In Process Space - Sharing in the process half
of the virtual address space requires that the page table fragment~
for the sections being shared be replicated in the process page
table(s).
Clearly this introduces multiple PTE's for the same
physical page. This is a problem traditionally avoided by one or more
levels of indirection, i.e., the PTE points to the shared PTE that
points to the page.
We can avoid introducing this level
of
indirection in the hardware by observing the following s~ftware rules:

Copyright(c) 1979 Digital Equipment Corp.,~aynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDEhTIAL
Memory Y~nagement
30-Jul-78 -- Rev 4
Page 5-24
ISSUES
1.

A share count is maintained for each shared page in memory
and in effect counts the number of direct pointers to that
page.

when a process releases a page from its working set and it is
a shared page as indicated in the working set data base, the
'private PTE must be changed to point at the shared PTE for
the page, and the private copy of the modify bit must be
OR'ed into the shared PTE.
Then the share count
is
decremented and if the count is now 0, the page is released
and the shared PTE is updated to reflect that. Note that the
process' w~rking set data base allows it to find its private
PTE and the physical page data base points to the shared PTE.

When a process gets an invalid page fault one of the possible
states of the "invalid" PTE is that it points to a shared
PTE. Of course that PTE might say that the page was not
resident requiring a page read. Whether or not the read was
necessary, the shared PTE is eventually copied to the private
PTE and the share count of the page is incremented.

Note that throwing a process out of the balarice
equivalent of releasing all its pages (see 2.)

The use of the indirect page pOinter as a software only
mechanism seems to be adequate for this form of sharing. It
should be noted that it is very difficul t to change the Pf'N
of a page in memory when it is actively being shared. That
would require a scan of the page tables for all the processes
in the balance set.

set

the

5.8.3.2 Shared Sections In System Space - When a process is using a
shared section in the system region of the address space, it is
referencing a Single shared page table. Since it is possible for a
process to simply reference such a shared section without ever having
declared its intention to do that, the operating system must be
prepared to do something reasonable when such a reference faults. A
straight forward design for this kind of sharing is:
1.

Have programs explicitly declare their intention to use each
shared system section.
This could be done statically at
compile or link time or dynamically at runtime.

Have the balance set manager swap in and lock down the entire
section when the process intending to use it is swapped in.

Of course the balance set manager maintains share counts on
the section and only discards its pages when no process in
the balance set wants it.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Memory Management
30-Jul-78 -- Rev 4
Page 5-25
ISSUES
4.

If a,process faults such a page because it failed to declare
its intention to use the section, then that is considered a
programming error.

approach for shared system sections allows a process to
reference pages of the section with no prior declaration of its intent
to use tbem. Such pages would be demand paged within a pool of pages
reserved for that purpose. There would be a list of the pages in use
in that pool and a fault for a new one would cause one in the pool to
be replaced.
This would use the same sort of working set management
that is used for the process address space but it would be global
across processes.
An~ther

5.8.4 Protection Check Before Valid Check
The Page Table Entry has been defined as having a valid bit that o'nly
controls the validity of the Modify Bit and Page Frame Number field.
The proteotion field is defined as always being valid and checked
first.
The the motivation for this design is the behavior the PROBE
instruction would exhibit if the Valid bit had to be set before it
could check protection. PROBE would actually have to fault in the
page to make it valid so that it could check the protection'and then
indicate whether or not the intended access was permissable. For the
vast percentage of PROBE instructions, the access is permitted and
faulting the page in the PROBE is certainly not unreasonable.
But a
program could be run in user mode that would PROBE all around in the
System region of the virtual address space faulting all the swappable
pages of the System. Though this would not violate the integrity of
the operating system it certainly would mess up any statistics that
the system might be gathering about the relative goodness of the
swappable pages.
The only drawback to the protection check before valid check design
seem to be a slight loss of flexibility in the memory management
software. If the valid bit governed the rest of the longword, then'
the software could use all of the remaining 31 bits when V=O. This is
not an obvious winner since if the protection field isn't maintained
in the PTE it must be kept s9mewhere else.
[End of Chapter 5)

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

Page 1

VAX-11 Exceptions and Interrupts -- Rev 6

Specification Status:
Architectural Status:
File:

SR6R6.RNO

PDN#:

not used

Date:

31-Jan-79

Superseded Specs:

under ECO control

Rev 5

Author:

Leonard, P.

Typist:

Ford, B.

Reviewer(s):

Abstract:

Conklin

Call, J.

Bess

P. Conklin, D. Cutler, D. Hustvedt, J. Le{)nard, P. Lipman,
D. Rodgers, S. Rothman, B. Stewart, B. Strecker

Chapter 6 describes the mechanisms by which exception and
interrupt conditions are presented to software, and the means
by which programs change their access level.

Revision History:
Rev 1/
Rev
Rev 2
Rev 3
Rev 4
Rev 5
Rev 6

Description
Initial Distribution Qr SRM
April Meeting
Approval by STAR Task Force
ECOs and Reedit
Editorial
Floating F'aul ts

Author
Hastings
Leonard
Leonard
Conklin
Conklin/Taylor
Bhandarkar

Revised Date
Oct-75
'l-May-76
3-Jun-76
20-Apr-77
30-Jul-78
31-Jan-79

Exceptions and Interrupts
Change History

31-Jan-79 -- Rev 6

Page 6-990

Rev 5 to Rev 6:
1•

Floating F'aul tEnable

xxxQUE are unaligned

ECO IS, IPL for exceptions

Rev 4 to Rev 5:
1.

Add SW mnemonics for arithmetic traps.

xxxQUE are aligned (ECO) .

Clean up Initiate Exception or Interrupt.

Rev 3 to Rev 4:
1.

Add reserved length on EDIT (EDITPC ECO).

Make Kernel Stack not valid IPL be 1F, power fail IPL be 1E (KS
not valid ECO).

Correct numerous typos including residual -16 and -14.

Add POLYx reserved operand.

Change "disaster" to "urgent".

Compatibility mode is a fault except odd address
abort. Reconcile codes with chapter 10.

Trace is a trap (TP is a fault).

IPL 1F is for exception vector<1:0>:1.

IPL lE is for power fail only.

10.

If interrupt routine modifies FPD, regs, or
are UNPREDICTABLE.

11.

Add console terminal and interval timer vectors and IPL.

12.

Change "STAR device" to "NEXUS".

13.

CHMK and REI do not get KS not valid or IS not valid.

14.

REI verifies IPL NEQU 0 if IS NEQU O.

15.

Add BIC/BISPSW to reserved operand list.

16.

Remove terms ISR, ESR, WCS.

(POLY ECO)

ce,

which

then

results

Exceptions and Interrupts
Change History

31-Jan-79 -- Rev 6

Page 6-991

17.

Add flow for initiation of exception or interrupt.

18.

Add between instruction flow.

19.

If FPD=1 saving PSL, then TP cleared.

20.

Verify on REI that if IS=1, then current mode=O.

21 •

Correct PROBEW in CHt-'lx.

22.

Reserve negative CHMx codes to CSS, customers. Change table to
document that transitions are legal in all modes to lS=O for
interrupts and IS=1 for exceptions.

23.

SCBB bit 30 is MEZ also.

24.

Clarify the PCB stack pointers are not maintained.

25.

Add invalid digit to reserved operand list.

26.

Don't allow IPL>O if current mode NEQ O.

27.

Document FC and FFFF as permanently reserved.

28.

Document saved PC on all exceptions/interrupts.

29.

Document that
Access
Translation Not Valid.

jOe

Add interrupts example.

31.

Machine check is on a best effort basis.

32.

Move IPL here from chapter 9.
returned O.

33.

SIRR ignores <31:5>;
<4:0> GTRU 15.

34.

Add table of arithmetic trap types to 6.3.

35.

Change reserved operand reference from CVTNP
(ECO) .

36.

Clarify FP and SP unpredictability on aborts.

37.

Merge divide by zero trap;

38.

Note that faults do not restore everything, only enough.

39.

Another inter vs except distinction is previous mode field.

Violation

Verify on REI.

IPL<31:5> is ignored

ignores <4:0> = 0;

over

precedence

takes

reserved

write,

aborts

CVTTP,

CVTSP

add index trap (INDEX ECO).

Exceptions and Interrupts
Change History

Page 6-992

31-Jan-79 -- Rev 6

40.

CCodes may change on reserved operand.

41.

STAR violates reset not clear halt reason.

42.

If a routine sets FPD, UNPREDICTABLE.

43.

SCBB is realy machine dependent.

44.

Stack switch on except/int is optional if to same stack.

45.

MTPR IPL changes states in state table.

46.

Don't execute
reinterrupt.

47.

Check console halt with all interrupts.

4d.

Add that STAR memory errors on 1B.

49.

Remove that interrupts can not push on stack.
find it useful.

50.

Interrupts/exceptions can be to shared process space!

51.

Add that STAR traps PC, @PC, -(PC).

52.

MTPR, MFPR now get stack pointers.

53.

Add bootstrap intial settings of these registers.

54.

POLY underflow occurs at end.

55.

Add processor register reserved operands.

56.

CALL clears saved T.

57.

Add documentation of xSP registers.

58.

Legal to REI with FPD and TP both set.

59.

SIRR(31:4> are ignored.

60.

On STAR, vector(1:0> = 2 with no WCS is a HALT.

61.

On STAR,

62.

Check-ASTLVL in REI only if returning to lS=O.

63.

Add explanation and rationale for T and TF.

64.

Add usage note that IPL splits with all ISP above all KSP.

~HI~

first

instruction

interrupt

routine

The future might

TP takes precedence.

vector(1:0> is ignored.

Exceptions and Interrupts
Change History

31-Jari-79 ~- Rev 6

Page 6-993

65.

Add usage note for ISRs to not drop 1PL below original.

66.

Add usage notes for debuggers.

Rev 2 to Rev 3:
1.

Renumber interrupt levels, in hex, for hardware 10
software 01 to OF.

Provide names of Software Interrupt Request Register (SIRR) and
Software Interrupt Summary Register (SISR).

Change "Numeric" to "Decimal".

Clarify fact that previous mode is cleared
loaded from current mode on exceptions.

Add description of software interrupt mechanism.

Add description of System Control Block
register (SCBB), and format of vectors.

Remove requirement to halt on exceptiQn if IS=1.

Combine cache parity error with machine check.
check to note that excepiion may be fault.

£i'ix

machine

Change name of trace exception back to trap.
Even
implemented as a fault, people think of it as a trap.

though

10.

Fill out descriptions of arithmetic traps, giving
result, and condition codes.

codes,

11 •

Eliminate decimal strings from reserved operand list, and
illegal combinations in CALLx, RET; illegal PCB in LDPCTX;
illegal register in MTPR, MFPR.

12.

Combine memory error abort with machine check.

13.

Remove concept of programmable device vectors.

interrupt,

(SCB) ,

its

type

and

base

Rev 1 to Rev 2:
1.

Define IPL's -16 to 15, and clarify definitions.

Change all references to "EXCEPTION STACK" to "KERNEL STACK".

Add descriptions of processor modes and stacks.

Eliminate trap-pending bits other than TP.

Redefine PSL.

Exceptions and Interrupts
Change History

Page 6-994

31-Jan-79 -- Rev 6

Delete references to ISL.

Rewrite exc~ption/interrupt and REI flow descriptions
with new scheme.

Simplify TEIT description for CHM scheme.

Eliminate address break and reserved address traps.

10.

Rewrite REI description.

11.

Add CHM instructions.

12.

Add chart describing state transitions.

13.

Fix introduction to eliminate misconception that exceptions are
always synchronous and interrupts aren't. New version could
still use word.

14.

Remove concept of interrupt enables.

15.

Clarify stack residency and validity.

16.

Rename T bit to trace.
faul t.

17.

Define effect of bits 1:0 of vector
interrupt stack, or WCS.

18.

Redefine 8CB vectors, eliminating and combining conditions, and
add interrupt vectors.

19.

Change most aborts to faults or traps.

20.

Specify results from arithmetic
overflow and underflow.

21.

Change Ivaster Control
(SCB) .

22.

Include checks of compatability mode conditions in PSL of REl.

23.

Add example
trace.

[End of SR6R6.RNO]

showing

Clarify how T and

Block

(NCB)

serialization

TP
select

traps;
to

work

trap,

work

for

trace

kernel

stack,

clarify

System

floating

Contr'ol

interrupt,

Block

and

Copyright(c) 1979 Digital Equipment Corp. ,Maynard ,Mass.
DO NOT COpy
VAX-11 System Reference ~Bnual
COMPANY CONFIDENTIAL

CHAPTER 6

EXCEPTIONS AND INTERRUPTS

31-Jan-79 -- Rev 6

6.1

INTRODUCTION

At certain times during the operation of a system, events within the
system require the execution of particular pieces of software outside
the explicit flow of control.
The processor transfers control by
forcing a change in the flow of control from that explicitly indica~ed
in the currently executing process.
Some of the events are relevant primarily to the currently executing
process, and normally invoke software in the context of the current
process. The notification of such events is termed an exception.
Other events are primarily relevant to other processes, or to the system
as a whole, and are therefore serviced in a system-wide context. The
notification process for these events is termed an interrupt, and the
system-wide context is described as "executing on the interrupt stack"
(IS). Further, some interrupts are of such urgency that they require
high-priority
service,
while
others
must be synchronized with
independent events. To meet these needs, the processor has priority
logic that grants interrupt service to the highest priority event at any
point in time. The priority associated with an interrupt is termed its
interrupt priority level (IPL).

Copyright(c) 1979 Digital Equipment Corp.,Haynard,I"lass.
DO NOT COpy
VAX-11 System Reference l-'lanual
COMPANY CONFIDENTIAL
Exceptions and Interrupts
j1-Jan-i9 -- Rev 6
Page 6-2
INTRODUCTION
6.1.1

Processor lnterrupt Priority Levels (~PL)

The processor has 31 interrupt priority levels (IPL), divided into 15
software levels (numbered, in hex, 01 to OF), and 16 hardware levels (10
to 1F, hex). User applications, system calls, and system services all
run at process level, which may be thought of as IPL O. Higher numbered
interrupt levels have higher priority, that is to say, any requests at
an interrupt level higher than the processor's current IPL will
interrupt immediately but requests at a lower or equal level are
deferred.
Interrupt levels 01 through OF (hex) exist entirely for use by software.
No device can request interrupts on those levels, but software can force
an interrupt by executing MTPR src,#SIRR. (See Chapter 9 and section
6.2.3).
Once a software interrupt request is made, it will be cleared
by the hardware when the interrupt i~ taken.
Interrupt levels 10 to 17 (hex) are for use by devices and controllers,
including UNIBUS devices; UNIBUS levels BR4 to BR7 correspond to VAX-11
interrupt levels 14 to 17 (hex).
Interrupt levels 18 to 1F (hex) are for use by urgent conditions,
including the interval clock, serious errors, and power fail.

6.1.2

Interrupts

The processor arbitrates interrupt requests according to priority. Only
when the priority of an interrupt request is higher than the current IPL
(Bits 20:16 of the Processor Status Longword) will the processor raise
the IPL and service the interrupt request.
The interrupt service
routine is entered at the IPL of the interrupt request and will not
usually change the IPL set by the processor.
Note that this is
different from the PDP-11 where the interrupt vector specifies the IPL
for the ISR.
Interrupt requests can come from devices, controllers, other processors,
or the processor itself. Software executing in kernel mode can raise
and lower the priority of the processor by executing MTPR src, #IPL
where src contains the new priority desired; see Chapter 9. However, a
processor cannot disable interrupts on other processors.
Furthermore
the priority level of one processor does not affect the priority level
of the other processors.
Thus in multiprocessor systems interrupt
priority
levels cannot be used to synchronize access to shared
resources.
Even the various urgent
interrupts
including
those
exceptions that run at IPL 1F (hex) do so on only one processor, thus
special software action is required to stop other processors in a
multiprocessor system.

Copyright(c) 1979 Digital Equipment Corp. ,Maynard ,Mass.
DO NOT COPY
COMPANY CONFIDENTIAL
Exceptions and lnterrupts
31-Jan-79 -- Rev 6
Page 6-3
INTRODUCTION

VAX-l1 System Reference Manual

6.1.3

Exceptions

Most exception service routines execute at IPL 0 in response to
exception conditions caused by the softwar'e. A variation from this is
serious system failures, which raise IPL to the highest level (lF, hex)
to minimize processor interruption until the problem is corrected.
Exception service routines are usually coded to avoid exceptions,
however nested exceptions can occur.
A trap is an exception condition that occurs at the end of the
instruction that caused the exception. Therefore the PC saved on the
stack is the address of the next instruction that would normally have
been executed.
Any software can enable and disable some of the trap
conditions with a single instruction;
see the BlSPSW and BICPSW
instructions described in Chapter 4.
A fault is an exception condition that occurs during an instruction, and
that leaves the registers and memory in a consistent state such that
elimination of the fault condition and restarting the instruction will
give correct results. Note that faults do not always leave everything
as it was prior to the faulted instruction, they only restore enough to
allow restarting.
Thus, the state of a process that faults may not be
the same as that of a process that was interrupted at the same point.
An abort is an exception condition that occurs during an instruction,
and potentially leaves the registers and memory indeterminate, such that
the instruction cannot necessarily be correctly restarted, completed,
Simulated, or undone.

6.1.4

Contrast Between Exceptions And Interrupts

Generally exceptions and interrupts are very similar.
When either is
initiated, both the processor status (PSL) and the program counter (PC)
are pushed onto the stack.
However there are
seven
important
differences:
1.

An exception condition is c,aused by the execution of the
current instruction while an interrupt is caused by some
activity in the computing system that may be independent of the
current instruction.

An exception condition is usually serviced in the context of
the process that produced the exception condition, while an
interrupt is serviced independently from the currently running
process.

,).

The IPL of the processor is usually not
processor initiates an exception, while
raised when an interrupt is initiated.

changed when the
the IPL is always

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Exceptions and lnterrupts
31-Jan-19 -- Rev 6
Page 6-4
lNTRODUCTION
4.

Exception service routines usually execute on a per-process
stack while interrupt service routines normally execute on a
per-CPU stack.

Enabled exceptions are always initiated immediately no matter
what the processor IPL is, while interrupts are held off until
the processor IPL drops below the IPL of the requesting
interrupt.

Most exceptions can not be disabled. However, if an exception
causing event occurs while that exception is disabled, no
exception is initiated for that event even when enabled
subsequently.
This includes overflow which is the only
exception whose occurrence is indicated by a condition code
(V). If an interrupt condition occurs while it is disabled, or
the processor is at the same or higher IPL, the condition will
eventually initiate an interrupt when the proper enabling
conditions are met if the condition is still present.

'7.

The previous mode field in the PSL is always set to Kernel on
an interrupt, but on an exception it indicates the mode of the
exception.

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PROCESSOR STATUS
6.2

PROCESSOR STATUS

When an exception or an interrupt is serviced, the processor status must
be preserved so that the interrupted process may continue normally.
Basically, this is done by automatically saving the Program Counter (PC)
and the Processor Status Longword (PSL). These are later restored with
the Return from Exception or Interrupt instruction (REI).
Any other
status required to correctly resume an interruptable instruction is
stored ~n the general registers. Process context such as the mapping
information is not saved or restored on each interrupt or exception.
Instead, it is saved and restored only when process context switching is
performed.
Refer to the LDPCTX and SVPCTX instructions in chapter 7.
Other processor status is changed even less frequently;
refer to the
privileged register descriptions in chapter 9.
The Processor Status Longword (PSL) is a longword consisting of a word
of privileged processor status concatenated with the Processor Status
word (PSW). Refer to chapter 2 for a description of the PSW.
The PSL
is automatically saved on the stack when an exception or interrupt
occurs and is ~aved in the PCB on a process context switch. The PSL can
also be stored by the MOVPSL instruction; refer to chapter 4. (The
terms current PSL and saved PSL are used to distinguish between this
status information when it is in the processor and when copies of it are
materialized in memory.)
Bits <31:21> of the current PSL can be changed explicitly only by
executing a return from exception or interrupt instruction (REI). REI
considers the current mode when restoring the PSL, and faults if a
program attempts to increase its privilege by this means. Thus REI is
available to all software including user exception handling routines.

3 3 2 2 2 2 222 2 2 2

1 1
8 7 6 5 4 321 0
1 0 9 8 7 6 5 432 1 0
6 5
+-+-+---+-+-+---+---+-+---------+--------------_.+-+-+-+-+-+-+-+-+

lelTI
IFIIICURIPRVIMI
IMIPlMBZIPISIMODIMODIBl
l l I IDI:
lZI

IPL

MBZ

IDIFlrlTINlz:vlel
IVlUIVI I I I : I
I I : : : : : I I

+-+-+---+-+-+---+---+-+---------+-------------+-+-+-+-+-+-+-+-+-+
\
/
\
/
+-----------PSW-----------+

Processor Status Longword
At bootstrap time, PSL is cleared except for IPL and IS.

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PROCESSOR STATUS
Bits

Description

3:0

Condition Codes:

Trace enable (1).
When set at the
beginning
of
an
instruction, causes TP to be set. When TP is set between
instructions (before examining T), a trace fault is taken.
The effect is that setting bit 4 forces a trace ~before
the execution of each subsequent instruction. when clear, no
trace exception occurs.
Most programs should treat T as
UNPREDICTABLE because it is set by debuggers and trace
programs for tracing and for proceeding from a breakpoint.

Integer Overflow trap enable (IV).
When set, forces an
integer overflow trap after execution of an instruction that
produced an integer result that overflowed or had a conversion
error.
When IV is clear, no integer overflow trap occurs.
(However, the condition code V bit is still set.)

Floating Underflow exception enable (FU). When set, forces a
floating
underflow
exception
after
execution
of the
instruction that produced an under fl owed result (i.e., a
result exponent, after normalization and rounding, less than
the smallest representable exponent for the data type).
When
FU is clear, no exception occurs. On the original VAX-11/7bO
a trap occurs; on all other VAX processors a fault occurs.

Decimal Overflow trap enable (DV).When set, forces a decimal
overflow trap after execution of an instruction that produced
an overflowed decimal (numeric string, or packed decimal)
result (i.e., no room to store a non-zero digit) or had a
conversion error.
When DV is clear, no
trap
occurs.
(However, the condition code V bit is still set.)

15:9

Reserved to DIGITAL, must be zero.

20:16

Interrupt Priority Level (IPL).
The
current
processor
priority, in the range 0 to 1F (hex). The processor will
accept interrupts only on levels greater than the current
level. At bootstrap time, IPL is initialized to 1F (hex).

Reserved to DIGITAL, must be zero.

22:23

Previous Access Mode (PRV_MOD). Loaded from current mode by
exceptions and CHMx instructions, cleared by interrupts, and
restored by REI.

25:24

Current Access Mode (CUR_MOD).
The access
currently executing process, as follows:

N, Z, V, C (See chapter 2)

o - KERNEL
1 - EXECUTIVE
2 - SUPERVISOR

mode

the

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PROCESSOR STATUS
3 - USER

Interrupt Stack (IS). When set the processor is executing on
the interrupt stack. Any mechanism that sets IS also clears
current mode and raises IPL above O. If an REI attempts to
restore a PSL with IS=1 and non-zero current mode or zero IPL,
a reserved operand fault is taken. When clear, the processor
is executing on the stack specified by curr'ent mode. At
bootstrap time, IS is set.

2',

First Part Done (FPD). When set the instruction addressed by
PC cannot simply be restarted, and must be resumed at some
other, implementation specific, point in its operation.
If
FPD is set and the exception or interrupt service routine
modifies FPD, the general registers, or the saved PSL (except
for T or TP), the results of the interrupted instruction's
execution are uNPREDICTABLE.
If a routine sets FPD, the
results are also UNPREDICTABLE.

29:28

Reserved to DIGITAL, must be zero.

Trace Pending (TP). Forces a trace fault when set at the
beginning of any instruction. Set by the processor if T is
~,~_t.~"~. ~~"~~ begillning of an instruction ._l'~~Any- exception or
!interrupt servI6e'·'":r"ouEl]'re"···c·tearlng -TP-~must also clear T or the
! tracing of the
interrupted
instruction,
if .any,
is
{ UNPREDICTABLE.
I

~"'---~.--..-.~--.----'" •.~.---..-""-~

Compatibility Mode (CM). When set the processor is in PDP-11
compatibility mode (see chapter 10). When CM is clear, the
processor is in native mode.

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INTERRUPTS
6.:3

INTERRUPTS

T11e processor services interrupt

requests between instructions.
The
processor also services interrupt requests at well defined pOints during
the execution of long, iterative instructions such as the string
instructions.
For these instructions, in order to avoid saving
additional instruction state in memory, interrupts are initiated when
the instruction state can be completely contained in the registers, PSL,
and PC.
The following events cause interrupts:
1.

Device completion (IPL 10-17 hex)

Device error (IPL 10-17 hex)

Device alert (IPL 10-17 hex)

Device memory error (IPL 10-17 hex)

Console terminal transmit and receive (IPL 14 hex)

Interval timer (IPL 18 hex)

7•

Recovered memory or bus or processor errors (implementation
specific,
IPL 18 to 1D hex);
The VAX-11/780 processor
interrupts at 1B on memory errors.

Unrecovered memory or bus or processor
specific, IPL 18 to 1D hex)

Power fail (IPL 1E hex)

10.

Software interrupt invoked by MTPR HSIRR (IPL 01 to OF hex)

11.

AST delivery when REI restores a PSL with mode greater than
equal to ASTLVL (see chapter 7) (IPL 02)

errors

(implementation

Each device controller has a separate set of interrupt vector locations
in the system control block (SCB). Thus interrupt service routines do
not need to poll controllers in order to determine which controller
interrupted.
The vector address for each controller is fixed by
hardware.
In order to reduce interrupt overhead, no memory mapping information is
changed when an interrupt occurs.
Thus the instructions, data, and
contents of the interrupt vector for an interrupt service routine must
be in the system address space or present in every process at the same
address.

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INTERRUPTS
6.3.1

Urgent Interrupts -- Levels 18-1F (Hex)

The processor provides 8 priority levels for use by urgent conditions
including
serious
errors (e.g., machine check) and power fail.
Interrupts on these levels are initiated by the processor upon detection
of certain conditions.
Some of these conditions are not interrupts.
For example, Machine Check is usually an exception but it runs at a high
priority level on the interrupt stack.
Interrupt level 1E (hex) is reserved for power fail. Interrupt level 1F
(hex) is reserved for those exceptions that must lock out all processing
until handled. This includes the hardware and sc)ftware "disasters"
(machine check and kernel stack not valid). It might also be used to
allow a kernel mode debugger to gain control on any exception.

6.3.2

Device Interrupts -- Levels 10-17 (hex)

The processor 'provides 8 priority levels for use by peripheral devices.
Any given implementation mayor may not implement all 8 levels of
interrupts. The minimal implementation is levels 14-17 (hex) that
correspond to the UNIBUS levels BR4 to BR7 if the system has a UNIBUS.

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INTERRUPTS
6.3.3

Software Generated Interrupts -- Levels 01-0F (Hex)

6.3.3.1 Software Interrupt Summary Register - The processor provides 15
priority interrupt levels for use by software.
Pending software
interrupts are recorded in the Software Interrupt Summary Register
(SISR).
The SISR contains 1's in the bit positions corresponding to
levels on which software interrupts are pending. All such levels, of
course, must be lower than the current processor IPL, or the processor
would have taken the requested interrupt.
1 1

6 5

1 0

+-------------------------------+-----------------------------+-+
I Pending Software Interrupts IMI
MBZ

I
IB!
IF E D C B A 9 8 7 6 5 4 3 2 11Z1

+-------------------------------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
Software Interrupt Summary Register
The SISR is a read/write privileged register accessible only to
privileged software (see Chapter 9). At bootstrap time, the contents of
SISR is cleared. The mechanism for accessing it is:
MFPR HSISR,dst

Reads the software interrupt summary register.

MTPR src,#SISR

Loads it, but this is not the normal way of
making software interrupt requests. It is
useful for clearing the software interrupt
system, and for reloading its state after a
power fail, for example.

6.3.3.2 Software lnterrupt Request Register - The software
interrupt
request register (SIRR) is a write-only ~ bit privileged register
used for making software interrupt requests. ~(5\1'.(
:J

4 3

+-------------------------------------------------------+-------+
ignored
I request I
+-------------------------------------------------------+-------+
Software Interrupt Request Register
Executing MTPR src,HSIRR requests an interrupt at the level specified by
src<3:0). Once a software interrupt request is made, it will be cleared
by the hardware when the interrupt is taken.
If src<3:0) is greater
than the current IPL, the interrupt occurs before execution of the
following instruction. If src<3:0) is less than or equal to the current
IPL, the interrupt will be deferred until the IPL is lowered to less
than src<3:0) and that there is no higher interrupt level pending. This
lowering of IPL is by either REI or by MTPR x,IIPL. If src<3:0) is 0,

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INTERRUPTS
no interrupt will occur.
Note that no indication is given if there is already a request at the
selected level.
Therefore, the service routine must not assume that
there is a one-to-one correspondence of interrupts generated and
requests made.
A valid protocol for generating such a correspondence
is:

6.3.4

The requester uses INSQUE to place a control block
the request onto a queue for the service routine.

The requester uses MTPR src,#SIRR to request
the appropriate level.

The service routine uses REMQUE to remove a control block from
the queue of service requests.
If REMQUE returns failure
(nothing in the queue), the service routine exits with REI.

If REMQUE returns success (an item was removed from the queue),
the service routine performs the service and returns to step 3
to look for other requests.

describing

interrupt

Interrupt Priority Level Register

Writing to the IPL with the MTPR instruction will load the processor
priority field in the Program Status Longword (PSL), that is, PSL<20:16>
is loaded from IPL<4:0>. Reading from IPL with the MFPR instruction
will read the processor priority field from the PSL. On writing IPL
bits <31:5> are ignored, on reading IPL bits <31:5> are returned zero.
3

5 4

+-----------------------------------------------------+----------+
ignored; returns 0
lPSL<20:16>:
+-----------------------------------------------------+----------+
Interrupt Priority Level Register
At bootstrap time, IPL is initialized to 31 (1F, hex).
Interrupt service routines must follow the discipline of not lowering
IPL below their initial level.
If they do, an interrupt at an
intermediate level could cause the stack nesting to be improper.
This
would result in REI faulting (see 0.13). Actually, a service routine
could lower the IPL if it ensures that no intermediate levels could
interrupt, however this is probably unreliable code.

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INTERRUPTS
6.5.5

Interrupt Example

As an example, assume the processor is running in response to an
interrupt at IPL5, it then sets IPL to 8, and then posts software
requests at IPLj, IPL7, and IPL9. Then a device interrupt arrives at
IPL11 (hex).
Finally IPL is set back to IPL5.
The sequence of
execution is:
event

state after event
contents of IPL
SISR
(hex)
(hex)

IPL in
PSL on
stack

(initial)
MTPR li8, 11IPL

5
8

0
0

MTPR 113, IISIRR

MTPR 4/7, IISIRR
MTPR #9,HSIRR interrupts to
device interrupts to

8
9
11

88
88
88

8,0

device service routine REI
IPL9 service routine REI
MTPR #5,#IPL changes IPL to 5
and the request for 7 is
granted immediately
IPL7 service routine REI
initial IPL5 service routine
REI back to IPLO and the
request for 3 is granted
immediately
IPL3 service routine REI

8,0
9,8,0

(:)

5,0

o
o

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EXCEPTIONS

6.4

EXCEPTIONS

Exceptions can be grouped into six classes:

1•

Arithmetic traps/faults

Memory management exceptions

Exceptions detected during operand reference

Exceptions occuring as a consequence of an instruction

Tracing

Serious system failures

I,'

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EXCEPTIONS
6.4.1

Arithmetic Traps/Faults

This section contains the descriptions of the exceptions that occur as
the result of performing an arithmetic or conversion operation. They
are mutually exclusive and all are assigned the same vector in the SCB,
and hence the same signal "reason" code. Each of them indicates that an
exception had occurred during the last instruction and that the
instruction has been completed. An appropriate distinguishing code is
pushed on the stack as a longword:

+---------------------------------------------------------------+
type code
:(SP)
+---------------------------------------------------------------+
PC of next instruction to execute*
+---------------------------------------------------------------+
PSL
+---------------------------------------------------------------+
*same as the instruction causing exception in case of fault
type code
(hex)
1
2

4
5
6
7

8
9
A

exception type

software mnemonic

TRAPS
SRM$K_INT_OVF_T
integer overflow
SRM$K_INT_DI V_T
integer divide by zero
SRM$K_FLT_OVF_T
floating overflow
floating/decimal divide by zero SRM$K_FLT_DIV_J'
SRM$K_FLT_UND_T
floating underflow
SRM$K_DEC_OVF_T
decimal overflow
SRM$K_SUB_RNG_T
subscript range
FAULTS
floating overflow
floating divide by zero
floating underflow

SRM$K_F LT_O VF _F
SRM$K_FLT_DIV_F
SRt'1$K_FLT_UND_F

\Floating overflow, underflow, divide by zero traps occur only on the
original VAX-11/780.
On all other VAX processors, these floating
arithmetic exception conditions result in faults.\

6.4.1.1 Integer Overflow Trap - An integer
overflow
trap
is
an
exception that indicates that the last instruction executed had an
integer overflow setting the V condition code and that integer' overflow
was enabled (IV set). The result stored is the low-order part of the
correct result. Nand Z are set according to the stored result.
The
type code pushed on the stack is'1 (SRM$K_INT_OVF'_T). Note that the
instructions RET, REI, REMQUE, REMQHI, REMQTI, MOVTUC, and BISPSW do not
cause overflow even if they set V. Also note that the EMODx floating
point instructions can cause integer overflow.

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EXCEPTIONS
6.4.1.2 Integer Divide By Zero Trap - An integer divide by zero trap is
an exception that indicates that the last instruction executed had an
integer zero divisor. The result stored is equal to the dividend and
condition code V is set.
The type code pushed on the stack is
2 (SRM$K_INT_Dl V_T ) .

6.4.1.3 Floating Overflow Trap - A floating overflow
trap
is
an
exception that indicates that the last instruction executed resulted in
an exponent greater than the largest representable exponent for the data
type after normalization and rounding. The result stored contains a one
in the sign and zeros in the exponent and fraction fields.
This is a
reserved operand, and will cause a reserved operand fault if used in a
subsequent floating point instruction. The N and V condition code bits
are set and Z and C are cleared. The type code pushed on the stack is
j (SRM$K_r'LT_OVF-,f) •

6.4.1.4 Divide By Zero Trap - Floating or Decimal String - A floating
divide by zero trap is an exception that indicates that the last
instruction executed had a floating zero divisor. The result stored is
the reserved operand, as described above for floating overflow trap, and
the condition codes are set as in floating overflow.
A decimal string divide by zero trap is an exception that indicates that
the last instruction executed had a decimal string zero divisor. The
destination and condition codes are UNPREDICTABLE. The zero divisor can
be either +0 or -0.
The type code pushed on the stack for both types of divide
4 (SRM$K_FLT_DIV_T).

zero

6.4.1.5 Floating Underflow Trap - A floating underflow trap is
an
exception that indicates that the last instruction executed resulted in
an expc)nent less than the smallest representable exponent for the data
type after normalization and rounding and that floating underflow was
enabled (FU set). The result stored is zero. Except for POLIx the N,
V, and C condition codes are cleared and Z is set. In POLYx, the trap
occurs on completion of the instruction, which may be many operations
after the underflow. The condition codes are set on the final result in
POLYx. The type code pushed on the stack is 5 (SRMtK_F'LT_UND_T).

6.4.1.6 Decimal String Overflow Trap - A decimal string overflow trap
is an exception that indicates that the last instruction executed had a
decimal string result too large for the destination string provided and
that decimal overflow was enabled (DV set). The V condition code is
always set. Refer to the individual instruction descriptions in Chapter
4 for the value of the result and of the condition codes. The type code

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EXCEPTIONS

6.4.1.7 Subscript Range Trap - A subscript range trap is an exception
that indicates that the last instruction was an INDEX instruction with a
subscript operand that failed the range check.
The value of the
subscript operand is lower than the Ipw operand or greater than the high
operand. The result is stored in indexout, and the condition codes are
set as if the subscript were within range. The type code pushed on the
stack is 7 (SRM$K_SUB_RNG_T).

6.4. 1 .8 r'loating Overflow Faul t - A floating overflow faul t is
an
exception that indicates that the last instruction executed resulted in
an exponent greater than the largest representable exponent for the data
type after normalization and rounding. The destination was unaffected
and the saved condition codes are UNPREDICTABLE. The saved PC points to
the instruction causing the fault. In the case of a POLY instruction,
the instruction is suspended with FPD set (see Chapter 4 for details).
The type code pushed on the stack is 8 (SRM$K_I.'LT_OVF_F) .

6.4.1.9 Divide By Zero Floating Fault - A floating divide by zero fault
is an exception that indicates that the last instruction executed had a
floating zero divisor. The quotient operand was unaffected and the
saved condition codes are UNPREDICTABLE. The saved PC points to the
instruction causing the fault. ~n the case of a POLY instruction, the
instruction is suspended with FPD set (see Chapter 4 for details). The
type code pushed on the stack is 9 (SRH$K_ft'LT_DIV_F).

6.4.1.10 Floating Underflow Fault - A floating underflow fault is an
exception that indicates that the last instruction executed resu· ted in
an exponent less than the smallest representable exponent for the data
type after normalization and rounding.
The destination operand is
unaffected. The saved condition codes are UNPREDICTABLE. The saved PC
points to the instruction causing the fault. The type code pushed
the stack is A (SRM K_F'LT_UND_F).

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EXCEPTIONS
6.4.2

Memory Management Exceptions

6.4.2.1 Access Control Violation Fault - An access control violation
fault is an exception indicating that the process attempted a reference
not allowed at the access mode at which the process was operating.
See
Chapter 5, Memory Management, for a description of the information
pushed on the stack as parameters. Software may restart the process
after changing the address translation information.

6.4.2.2 Translation Not Valid Fault - A translation not valid fault is
an exception indicating that the process attempted a reference to a page
for which the valid bit in the page table was not set. See Chapter 5,
Memory tvianagement, for a description of the information pushed on the
stack as parameters. Note that if a process attempts to reference a
page for which the page table entry specifies both Not Valid and Access
Violation, an Access Control Violation Fault occurs.

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EXCEPTIONS
6.4.3

Exceptions Detected During Operand Reference

6.4.3.1 Reserved Addressing Mode Fault - A reserved addressing
mode
fault is an exception indicating that an operand specifier attempted to
use an addressing mode that is not allowed in the situation in which it
occurred. No parameters are pushed.
The situations in which each specifier type is reserved are:
SPEcni'IER

RESERVED SITUATION

Short Literal

Modify, destination, address
source, or within index mode.

Address source or within index mode.

Index Mode

Wi thin index mode, or wi·th PC as' index.

See Chapter 3 for combinations of addressing modes and registers that
cause UNPREDICTABLE results. The VAX-11/780 processor also faults on
PC, @PC, and -(PC).

6.4.3.2 Reserved Operand Exception - A reserved operand exception is an
exception indicating that an operand accessed has a format reserved for
future use by DIGITAL. No parameters are pushed. This exception always
backs up the PC to point to the opcode. The exception service routine
may determine the type of operand by examl.nl.ng the opcode using the
stored PC.
Note that only the changes made by instruction fetch and
because of operand specifier evaluation may be restored.
Therefore,
some instructions are not restartable. These exceptions are labelled as
ABORTs rather than FAULTs. The PC is always restored properly unless
the instruction attempted to modify it in a manner that results in
UNPREDICTABLE results. The PSL other than FPD and TF is not changed
except for the conditon codes, which are UNPREDICTABLE.
The reserved operand exceptions are caused by:
set

and

the

1•

A floating point number that has the sign bit
exponent zero except in the POLY table (FAULT)

A floating point number that has the~g~~~it set and the
exponent zero in the POLY table r ABORT;\ )see chapter 4 for
\~
restartability)

POLY degree too large (FAULT)

Decimal string too long ~)

Invalid digit in CVTTP, CVTSP

(~)

JJ~

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EXCEPTIONS

Bit field too wide (FAULT)

Invalid combination of bits in PSL restored by REI (FAULT)

Reserved pattern operator in EDITPC (ABORT;
restartability)

Incorrect source string length at completion of EDITPC (ABORT)

10.

Invalid combination of bits in
(FAULT)

11.

invalid combination of bits in BISPSW/BICPSW (FAULT)

12.

Invalid CALLx entry mask (FAULT)

13.

Invalid register number in MFPR or l-'lTPR (FAULT)

14.

Invalid combinations in PCB loaded by LDPCTX (ABORT)

15.

Unaligned operand in ADAWI (FAULT)

16.

Invalid register contents in MTPR instructions
registers for some implementations (FAULT):
SISR<31:16>'SlSR<0> NEQU 0
POBR<1 : 0) NEQU 0
POBR LSSU 2**31
POBR GIRU 2**31+2**30-1
P 1BR<1 : 0) NEQU 0
P1BR LSSU 2**31-2**23
P1BR GTRU 2**31+2**30-2**23-1
POLR<31:27>'POLR<23:22> NEQU 0
P1LR<30:22> NEQU 0
ASTLVL<2:0> GTRU 4

PSW/MASK

see Chapter 4

longword

for

during

RET

some

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EXCEPTIONS
6.4.4

Exceptions Occurring As The Consequence Of An Instruction

6.4.4.1 Opcode Reserved To DIGITAL Fault - An
opcode
reserved
to
DIGITAL fault occurs when the processor encounters an opcode that is not
specifically defined, or that requires higher privileges than the
current mode. No parameters are pushed. Opcode F'FFF (hex) will always
fault.

6.4.4.2 Opcode Reserved To Customers (and CSS) Fault - An
opcode
reserved to customers fault is an exception that occurs when an opcoue
reserved to the customers or DIGITAL's Computer Special Systems group is
executed.
The operation is identical to the opcode reserved to DIGITAL
fault ~xcept that the event is caused by a different set of opcodes, and
faults through a different vector. All opcodes reserved to customers
(and CSS) start with Fe (hex), which is the XFC instruction.
If the
special instruction needs to generate a unique exception, one of the
reserved to CSS/Customer vectors should be used. An example might be an
unrecognized second byte of the instruction.

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EXCEPTIONS
I

6.4.4.::;

Compatibility Node Exception - A compatibility mode exception
is an exception that occurs when the processor is in compatibility mode.
A longword of information is pushed on the stack, which contains a code
as follows:
0

1
2

reserved opcode
BPT
rOT
EMT

TRAP

illegal instruction
odd address

FAULT
FAULT
FAULT
FAULT
FAULT
FAULT
ABORT

All other exceptions in compatibility mode occur to the regular VAX-11
vector, e.g., Access Control Violation, Translation Not Valid, Memory
Error, and Machine Check Abort. See chapter 10, Compatibility Mode.

6.4.4.4 "Breakpoint Fault - A breakpoint fault is a.n exception that
occurs when the breakpoint instruction (BPT) is executed. NO parameters
are pushed.
To proceed from a breakpoint, a debugger or tracing program typically
restores the original contents of the location containing the BPT, sets
T in the PSL saved by the BPT fault, and resumes. When the breakpointed
instruction completes, a trace exception will occur (see section 6.7).
At this pOint, the tracing program cen again re-insert the BPT
instruction, restore T to its original state (usually clear), and
resume. Note that if both tracing and breakpointing are in progress
(i.e., if PSL(T) was set at the time of the BPT), then on the trace
exception both the BPT restoration and a normal trace exception should
be processed by the trace handler.

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EXCEPTIONS
6.4.5

Tracing

A trace is an exception that occurs between instructions when trace is
enabled.
Tracing is used for tracing programs, for performance
evaluation, or debugging purposes. It is designed so that one and only
one
trace exception occurs before the execution of each traced
instruction (except that aservtce routine invoked by CH~, c-~and
terminated by REI is considered a single instruction). The saved PC on
a trace is the address of the next instruction that would normally be
executed. "'//\"
h . '
-t, ;
)

.~.

In order to ensure that exactly one trace occurs per instruction despite
other traps and faults, the PSL contains two bits, trace enable (T) and
trace pending (TP) (see section 6.3). If only one bit were used then
the occurrence of an interrupt at the end of an instruction would either
produce zero or two traces, depending on the design.
Instea~}L the
PSL(T) bit t'u: defined to produce a trap after any other traps or ab&rts.,,,
The trap effect is implemented by copying PSL(T) to a second bit
(PSL(TP»
that is actually used to generate the exception. PSL(TP)
generates a fault before any other processing at the start of the next
instruction. See sectlou 6.11 for detai19G f10\IS.
The rules of operation for trace are:
1.

At the beginning of an instruction, if T is set then TP is set.

If the instruction faults or an interrupt is serviced, the
pushed PSL(TP) is cleared. The pushed PC is set to the start
of the faulting or interrupted instruction.

If the instruction aborts or takes an arithmetic trap,
pushed PSL(TP) is set or cleared as the result of step 1.

If an interrupt is serviced after instruction c()mpletion and
arithmetic traps' but before tracing, is checked for at the start
of the next instruction, then the pushed PSL(TP) is set or
cleared as the result of step 1.

At the beginning of an instruction, if TP is set then
pending fault is taken.
,f

the

trace

The routine entered by a CHMx is not tra6ed because CHMx clears T and TP
in the new PSL.
However, if T wa( set at thE? be,ginning of CHMx the
saved PSL will have both T and TP set. REI will t'r,ap either if Twas
set when the REI was executed or if TP in the saved PSL is ~et. Because
of this, the instruction sequence CHMx •.• REI ahts as'" 'a'"A"siingle \
inst"p,uet"ion.
Note that the trace exception occurring after an REI that
had T' set before being executed will be taken with the new PSL.
Thus,
spec:{al care must be taken if exception or interrupt routines are
traced.
In addition, the CALLx instructions save a clear T, although T in the
PSL is unchanged.
This is done so that a debugger or trace program
proceeding from a BPT fault does not get a spurious trace from the RET

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EXCEPTIONS
that matches the CALL (see 6.6.4) .
. The detection of interrupts and other exceptions;., occurp b-e-fore~·<the
d e.t..e.ct.i-0!1'·' , of·a t rae'e~"~xc·eption . ~y··,·t<h±-s~'c'auses no di.fficulti es
S~fl'ee,-"~he entire PSL (including T and
TP) is automatically saved on
interrupt or exception initiation and is restored at the end with an
REI. This makes interrupts and benign exceptions totally transparent to
the executing program.

'(.

(

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EXCEPTIONS
6.4.5.1 Trace Instruction Summary - The following table shows all of
the cases of T enabled at the beginning of the instruction, enabled at
the end of the instruction, and TP set in the popped PSW or PSL for
ordinary ins~ructions (XXX), CHMx ... REI, interrupt or exception ... REI,
CALLx, RETURN, CHMx, REI, BISPSW, and BICPSW:
Trace exception
enabled
at beg
(T)
XXX
CHMx ... REI

enabled
at end
(T)

'IP bit
at end
(TP)

N
y

N
Y

interrupt or
exception ... REl

CALLx

N
Y

(pushed PSW<T> clear)
(trap after next instruction)

RET

CHrvIx
REI
(if PSL(TP>=O
on stack)
REI
lif PSL(TP>=1
on stack)
BISPSW
BICPSw
interrupt or
exception

N
y
Y

N
N

N*
y*
N*
y*

N
N

N*
Y*
N*

Y
Y

Y
Y
N

---..-._,,......¥,,, ..

(pushed PSL<TP> clear)
(pushed PSL<TP> set)

Y
Y
Y

(only one trap)

N
N

(pushed PSL<TP> clear)
(pushed PSL(TP> depends
on above description)

* = depends on PSW<T> popped from stack

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EXCEPTIONS

6.4.5.2 Using Trace - Routines using the trace facility are termed
trace handlers.
They should observe the following conventions and
restrictions:
1.

when the trace handler performs its REI back to the traced
program, it should always force the T bit on in the PSL that
will be restored. This defends against programs clearing T via
RET, REI, or BICPSW.

The trace handler should never examine or alter the TP bit when
'continuing tracing. The hardware flows ensure that this bit is
maintained correctly to continue tracing.

when tracing is to be ended, both T and TP should
This ensures that no further traces will occur.

TraCing a service routine that completes with an REI will give
a trace in the restored mode after the REI. If the program
being restored' to was also being traced, only one trace
exception is generated.

If a routine entered by a CALLx instruction is executed at full
speed by turning off T, then trace control can be reqained by
setting T in the PSW in its call frame.
Tracing will resume
after the instruction following the RET.

Tracing is disabled for routines en.tered by a CHMx instruction
or any exception. Thus, if a CMHx or exception service routine
is to be traced, a breakpoint instruction must be placed at its
entry point.
If such a routine is recursive, breakpointing
will catch each recursion only if the breakpoint is not on the
CHMx or instruction with the exception.

If it is desired to allow multiple trace handlers, all handlers
should preserve T when turning on and off trace. They also
would have to simUlate traced code that alters or reads T.

cleared.

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EXCEPTIONS
6.4.6

Serious System Failures

6.4.6.1 Kernel Stack Not Valid Abort - Kernel stack not valid abort is
an exception that indicates that the Kernel stack was not valid while
the processor was pushing information onto the Kernel stack during the
initiation of an exception or interrupt. Usually this is an indication
of a stack overflow or other executive software error.
The attempted
exception is transformed into an abort that uses the interrupt stack.
No extra information is pushed on the interrupt stack in addition to PSL
and PC.
IPL is raised to 1F (hex). Software may abort the process
without aborting the system. However, because of the lost information,
the process cannot be continued.
If the Kernel Stack is not valid
during the normal execution of an instruction (including CHMK or REI),
the normal memory management fault is initiated. If the exception
vector (1:0) for Kernel Stack Not Valid is 3, the behavior of the
processor is UNDEFINED (see section 6.jr.2).

6.4.6.2 Interrupt Stack Not Valid Halt - An interrupt stack not valid
halt is an exception that indicates that the interrupt stack was not
valid or that a memory error occurred while the processor was pushing
information onto the interrupt stack during the initiation of an
exception or interrupt. No further interrupt requests are acknowledged
on this processor. The processor leaves the PC, the PSL, and the reason
for the halt in registers so that it is available to a debugger, the
normal bootstrap routine, or an optional watch dog bootstrap routine. A
watch dog bootstrap can cause the processor to leave the halted state.

6.4.6.3 Machine ChecK Exception - A machine check exception indicates
that the processor detected an internal error in itself. As usual for
exceptions, this exception is taken independent of IPL. IPL is raised
to 1F (hex) only if vector(1:0) is 1..
Implementation specific
information is pushed on the stack as longwords.
The processor
specifies the number of bytes pushed by placing the number of bytes
pushed as the last longword pushed. (0 if none, 4 if one, ... ).
This
count excludes the PC, PSL, and count longwords. Software can decide,
on the basis of the information presented, whether to abort the current
process if the machine check came from'the process. Machine check
includes uncorrected bus and memory errors anywhere, and any other
processor-detected errors.
Some processor errors cannot ensure the
state of the machine at all.
For such errors, the state will be
preserved on a "best effort" basis. If the exception vector (1:0) for
machine check is 3, the behavior of the processor is UNDEFINED (see
section 6.$.2).

6.5

SYSTEM CONTROL BLOCK (SCB)

The System Control Block is a page containing the vectors by 'which
exceptions and interrupts are dispatched to the appropriate service
routines.

6.5.1

System Control Block Base (SCEB)

The SCBB is a privileged register containing the physical address of the
System Control Block, which must be page-aligned.

332

9 8

109

+---+-----------------------------------------+-----------------+
IMBZI
Physic,l page address of SCB
I
MBZ
I
+---+-----------------------------------------+-----------------+
System Control Block Base
At bootstrap time, the contents of SCBB is UNPREDICTABLE.
The actual
length is implementation dependent because it represents a physical
address.

6.5.2

Vectors

A vector is a longword in the SCB that is examined by the processor when
an exception or interrupt occurs, to determine how to service the event.
Separate vectors are defined for each interrupting device controller and
each class of exceptions. Each vector is interpreted as follows by the
hardware. Bits 1:0 contain a code interpreted:
O.

Service this event on the kernel stack unless already running
on the interrupt stack, in which case service on the interrupt
stack. See also 6.10.

1•

Service this event on the interrupt stack. If this event is an
exception, the IPL is raised to 1F (hex). See also 6.10.

Service this event in writable control store, passing bits 15:2
to the installation-specific microcode there.
If writable
control store does not exist or is not loaded, the operation is
UNDEFINED.
On the VAX-11/780 processor, the operation in this
case is a HALT.

Operation UNDEFINED. Reserved to DIGITAL.
processor, the operation is a HALT.

the

VAX-11/780

For codes 0 and 1, bits 31:2 contain the virtual address of the service
routine, which must begin on a longword boundary and will ordinarily be

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SYSTEM CONTROL BLOCK (SGB)
in the system space. CHMx is serviced on the stack selected by the new
mode, see section 6.13. Bits <1:0) in the CHMx vectors must be zero or
the operation is UNDEFINED. On the VAX-11/780 processor, these bits are
ignored in the CHMx vectors.

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SYSTEM CONTROL BLOCK (SCB)
System Control Block (exception and interrupt vectors)
Number of
Params Notes

Vectl)r
(hex)

Name

Unused

Nachine Check

Abort/
Faul t/
Trap

Processor-and errorspecific information
is pushed on the
stack, if possible.
Restartability is
processor specific.
If vector<1:0> is 1,
IPL is raised to 1F(hex)
and the interrupt stack
is used (i.e. IS <- 1) ..
* -- the number of bytes
of parameters is pushed
on the stack and is
implementation dependent.

Kernel Stack Not Valid

Abort

Serviced on the
interrupt stack
(i.e. IS <- 1). IPL is
raised to 1F (hex).

Power Fail

Interrupt 0

Reserved/Privileged
Instruction

Fault

Opcodes reserved to
DIGITAL and
privileged instructions.

Customer Reserved
Instruction

F'aul t

XFC instruction.

Reserved Operand

Faul t/
Abort

Type depends on
circumstances. See

Type

Reserved to DlGITAL.

IPL is raised
to 1E (hex).

(0.4,3.·2...

Reserved Addressing Mode Fault

Access Control Violation Fault

Virtual address
causing fault is
pushed onto stack.
See chapter 5.

Translation Not Valid

Virtual address
causing fault is
pushed onto stack.
See chapter 5.

Fault

Trace Pending (TP)

Fault

Breakpoint Instruction

Fault

Compatibility

Fault/
Abort

A type code is pushed
onto the stack.
See 6 •.fr.~

If
34

Arithmetic

38-3C

Unused

Trap/
[<'aul t

A type code is pushed
onto the stack.
See 6.4.
Reserved to DIGITAL.

CHMK

Trap

CHME

Trap

The operand word is
sign extended and
pushed onto the stack.
Vector(1:0> MBZ.

CHHS

Trap

The operand word is
sign extended and
pushed onto the stack.
Vector(1:0> MBZ.

CHHU

Trap

The operand word is
sign extended and
pushed onto the stack.
Vector(1:0> MBZ.

Reserved to DIGITAL.

50-80

Software Level

interrupt 0

Software Level 2

Interrupt 0

Ordinarily used for
AST delivery.

Software Level 3

Interrupt 0

Ordinarily used for
Process Scheduling.

90-BC

Software Levels 4-F

Interrupt 0

Interval Timer

Interrupt 0

C4-DC
EO-EC
F'O-F4

Unused
Unused
Unused

Console Terminal Rec.

IPL is 18 (hex).
Reserved to DIGITAL
Reserved to eSS/Customers
Reserved to DIGITAL

interrupt 0

IPL is 14 (hex).

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S YS'l'EM CONTROL BLOCK (SGB)

Console Terminal Trans. Interrupt 0

100-1FC Device Veotors

IPL is 14 (hex).

Interrupt 0

In the.,VAX-111780 processor, only h'ar.d.ware levels 14 to 17 (hex) are
available to a "NEXUS external to the CPU, and there is a limit of 16
such NEXUS. A NEXUS is a connection on the SBI, which is the internal
interconnection structure. The NEXUS vectors are assigned as follows:
100-1jC IPL 14 (hex') NEXUS 0-15
140-1'lC IPL 15 (hex) NEXUS 0-15
l80-1BC IPL 16 (hex) NEXUS 0-15
1CO-1FC IPL 17 (hex) NEXUS!~0-15
I'J;

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STACKS
6.6

STACKS

At any time, the process~r is either in a process context (IS=O) in one
of four modes (kernel, exec, super, user), or in the system-wide
interrupt service context (IS=1) that operates with kernel privileges.
There is a stack pointer associated with each of these five states, and
any time the processor changes from one of these states to another, SP
(R14) is stored in the process context stack pointer for the old state
and_ loaded from that for the new state.
The process context stack
pointers (KSP=kernel, ESP=exec, SSP=super, USP=user) are allocated in
the PCB (see Chapter 7), although some hardware implementations may keep
them in privileged registers. The interrupt stack pointer (lSP) is in a
privileged register.
Operating system design must choose a priority level that is the
boundary between kernel and interrupt stack use. The SCB interrupt
vectors must be set such that interrupts to levels above this boundary
run on the interrupt stack (vector(1:0) = 1) and interrupts below this
boundary run on the kernel stack (vector(1:0) = 0).
Typically, AST
delivery (IPL 2) is on the kernel stack and all higher levels are on the
interrupt stack.

6.6.1

Stack Residency

The USER, SUPER, and EXEC stacks do not need to be resident. The kernel
can bring in or allocate process stack pages as Address Translation Not
Valid faults occur. However, the kernel stack for the current process,
and the interrupt stack (which is process-independent) must be resident
and accessible. Translation ~ot Valid and Access Control Violation
faults occurring on references to either of these stacks are regarded as
serious system failures, from which recovery is not possible.
If either of these faults occurs on a reference to the kernel stack, the
processor aborts the current sequence and initiates Kern:~l Stack Not
Valid abort on hardware level 1F (hex).
If either of these faults
occurs on a reference to the interrupt stack, the processor halts. ~ote
that this does not mean that every possible reference is checked, but.
rather that the processor will not loop on these conditions.
It is not necessary that the kernel stack for processes other than the
current one be resident, but it must be resident before a process is
selected to run by the softwarets process dispatcher.
Further, any
mechanism that uses Translation Not Valid or Access Control Violation
faults to gather process statistics, for instance, must exercise care
not to invalidate kernel stack pages.

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STACKS
6.6.2

Stack Alignment

Except on CALLx instructions, the hardware makes no attempt to align the
stacks.
For best performance on all processors, the software should
align the stack on a longword boundary and allocate the stack in
longword increments.
The convert byte to long (CVTBL and MOVZBL),
convert word to long (CVTWL and M
;;TTY12: - PLEASE DELETE ANY UNNECESSARY FILES ON DSKB .... TBANX ...
OVZ WL), convert long to byte (CVTLB) ,
and convert long to word (CVTLW) instructions are recommended for
pushing bytes and words on the stack and popping them off in order to
keep it longword aligned.

6.6.3

Stack Status Bits

The interrupt stack bit (IS) and current mode bits in the privileged
Processor Status Longword (PSL) specify which of the five stack pointers
is currently in use as follows:
IS

MODE

0
0

ISP
KSP
ESP
SSP

0
0
0
0

1
2
3

USP

The processor does not allow current mode to be non-zero when IS=1.
This is achieved by clearing the mode bits when taking an interrupt or
exception, and by causing reserved operand fault if REI attempts to load
a PSL in which both IS and mode are non-zero.
The stack to be used for an interrupt or exception is selected by the
current PSL<IS) and bits <1:0> of the vector for the event as follows:
vector<1:0>
00
01

+-----+-----+
+-----+-----+
: ISP : ISP :
+-----+-----+

o I KSP : ISP :
PSL<IS)

Values 10 (binary) and 11 (binary) of the vector<1:D> are used for other
purposes. Refer to section 6~2 for details.

6.6.4

Accessing Stack Registers

The processor implements five privileged registers to allow access to
each stack pointer. These registers always access the specified pointer
even for the- current mode.
If the process stack pointers
are
implemented as registers, then these instructions are the only method

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STACKS
for accessing the stack pointers of the current process. If the process
stack pointers are kept in the PCB, MTPft and MFPR of these registers
access the PCB. The register numbers were chosen to be the same as
PSL<26:24>. The previous stack pointer is the same as PSL<23:22> unless
PSL<IS> is set. At bootstrap time, the contents of all stack pOinters
are UNPREDICTABLE.
3

+---------------------------------------------------------------+
virtual address of top of stack
+---------------------------------------------------------------+
Kernel Stack Pointer
Executive Stack Pointer
Supervisor Stack Pointer
User Stack Pointer
Interrupt Stack Pointer

KSP = 0
ESP = 1
SSP = 2
USP = 3
ISP = 4

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SERIAL1ZATION OF NOTIFICATION OF MULTIPLE EVENTS

6.7

SERIALIZATION OF NOTIFICATION OF MULTIPLE EVENTS

The interaction between arithmetic traps, tracing, other exceptions, and
multiple interrupts is complex.
In order to ensure consistent and
useful implementations, it is necessary to understand this interraction
at a detailed level. As an example, if an instruction is started with
T=1, it gets an arithmetic trap, and an interrupt request is recognized,
the following sequence occurs:
1.

The instruction finishes, storing all its results.

The overflow trap sequence is initiated, pushing the PC and PSL
(with TP=1), loading a new PC from the vector, and creating a
new PSL.

The interrupt sequence is initiated, pushing the PC and PSL
appropriate to the trap service routine, loading a new PC from
the vector, and creating a new PSL.

If a higher priority interrupt is
noticed,
the
first
instruction of the interrupt service routine is not executed.
Instead, the PC and PSL appropriate to that routine are saved
as
part of initiating the new interrupt.
The original
interrupt service routine will then be executed when the higher
priority routine terminates via REI.

The interrupt service routine runs, and exits with REI.

The trap service routine runs, and exits with REI, which
a PSL having TP=1.

finds

'i.

The trace occurs, again pushing PC and PSL but this
TP=O.

with

Trace service routine runs, and exits with REI.

time

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SERIALIZATION OF NOTIFICATION OF MULTIPLE EVENTS
This is accomplished by the following operation between instructions:
!here at completion of instruction including
at end of REI from an exception or interrupt routine
if {arith trap needed and no other abort
or trap} then {initiate arith trap};
1$:

{possibly take interrupts or console halt};
if PSL(TP) EQLU 1 then
!if trace pending, take trace
begin
\ "-I
PSL(TP) <- 0;
{initiate trace fault};
end;
{possibly take interrupts or console halt};
PSL<TP) <- PSL<T);
!if trace enable, set trace pending
{go start instructi()n execution};
!Note: FPD is tested here, thus TP takes
! precedence over FPD if both are set.
if {instruction faults} OR {an interrupt or console halt
is taken before end of instruction} then
begin
{back up PC to start of opcode};
{either set PSL(FPD) or back up all general
register side effects};
PSL<TP) <- 0;
{initiate exception or interrupt};
!note: all instructions end by flowing
! through 1$, thus the REI from the service
! routine will return to 1$
end;

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INITIATE EXCEPTION OR INTERRUPT

6.8

INITIATE EXCEPTION OR INTERRUPT
<none>

Initiate Exception or Interrupt

Operation:
!The notation PSL<xxx>_SP is used to refer
to the SP appropriate to the mode xxx specified
in the PSL. The actu~l stack pointer may be either
in the PCB or in Ci general pegister (see chapter 7).
{disable interrupts};
<- SCB[vector];
!get correct vector
III'if tmpl<1 :0> EQLU j then {UNDEFINED};
if tmpl<1:0) EQLU 0 AND {machine check or
kernel stack not valid} then {UNDEFINED};
if tmp1<1:0> NEQU a AND {CHMx} then {UNDEfINED};
if tmPcJ <1 : 0> EQLU 2 then
begin
if {writable control store exists and is loaded}
then {enter writable control store}
else {UNDBFINED};
end;
!switch stacks
if PSL<IS> EQLU 0 then
begin
PSL<CUR_NOD> SP <- SP; !save old SP
if tmp1 <1 : O>EQLU 1 then
SP <- iSP;
else
SP <- new_mode_SP; !kernel_SP unless CHMx
end;
tmp2 <- PSL;
PSL<CM,TP,FPD,DV,FU,IV,T,~,Z,V,C> <- 0; !clean out PSL
if {interrupt} then
PSL<PRV~MOD> <- 0;
!kernel mode
else
PSL<PRV_MOD> <- PSL<CUR_MOD>;
PSL<CUR_MOD) <- new_mode;
!kernel_mode unless CHMx
-(SP) <- tmp2;
Ion a fault or abort, the saved
!condition codes are UNPREDICTABLE
-(SP) <- PC;
as backed up, if necessary
{push parameters if any}
if kernel stack not valid exception
occurs while pushing tmp2, PC, or other
palrameters then PSL <- tmp2 before
initiating exception
if {interrupt} then
!set new IPL
PSL<IPL> <- new_IPL
else
if tmp1<i:O> EQLU 1 then
!IF (hex)
PSL<IPL> <- 31;
!otherwise
keep old IS
if tmp1 <1 : 0) EQLU 1 then PSL<IS) <- 1;
!longword aligned
PC <- tmp1<31:2> t 0<1:0);
~tmpl

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Exceptions and Interrupts
31-Jan-19 --Rev 6
Page 6-38
lNITIATE EXCEPTION OR INTERRUPT
{enable interrupts};
if {PSL<lPL> LEQU 15} AND {PSL<IPL> GEQU 1} then
SlSR<PSL<IPL» (- 0;
Condition Codes (if vector(1:0) code is 0 or 1):

N <- 0;
Z (- 0;
V <- 0;
C <- 0;
Exceptions:
interrupt stack not valid
kernel stack not valid
Description:
The handling is determined by the contents of a longword vector in the
system control block which is indexed by the exception or interrupt
being processed. If the processor is not executing on the interrupt
stack, then the current stack pointer is saved and the new stack pointer
is fetched. The old PSL is pushed on~o the new stack. The PC is backed
up (unless this is an interrupt between instructions, a trace pending
fault, or a trap) and is pushed onto the new stack.
The PSL is
initialized to a canonical state.
IPL is chang.dif this is an
interrupt or if it is an exception with vector(1:0) code 1.
Any
parameters are pushed. Except' for interrupts, the previous mode in the
new PSL is set to the old value of the current mode. Finally, the PC is
changed to point to the longword indicated by the vector<31:2>.
Notes:
1.

Interrupts are disabled during this sequence.

If the ~ector<1:0) code is invalid, the behavior is UNDEFINED.

On an abort, the saved condition codes are UNPREDICTABLE. On a
fault
or
interrupt,
the
saved
condition
codes
are
UNPREDICTABLE; they are only saved to the extent necessary to
ensure correct completion of the instruction when resumed. On
an abort or fault or interrupt that sets FPD, the general
registers except PC, SP and FP are UNPREDICTABLE unless the
instruction. description specifies a setting.
If FP is the
destination in this case, then it is also UNPREDICTABLE. On a
Kernel Stack Not Valid abort, both SP and FP are UNPREDICTABLE.
In this case, UNPREDICTABLE means unspec~fied; upc~ REI the
instruction behavior, and results are predictable. This implies
that processes stopped with FPD set cannot be resumed on
processors of a different type pr engineering change level.

If the processor gets an Access Control Violation or a
Translation Not Valid condition while attempting to push
information on the kernel stack, a Kernel Stack Not Valid abort

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-ll System Reference Manual
COMPANY CONFIDENTIAL
Exceptions and Interrupts
31-Jan-79 -- Rev 6
Page 6-39
INITIATE EXCEPTION OR INTERRUPT
is initiated and IPL is changed to IF (hex). The additional
information, if any, associated with the original exception is
lost.
However PSL and PC are pushed on the interrupt stack
with the same values as would have been pushed on the kernel
stack.

If the processor gets an Access Control Violation or a
Translation Not Valid condition while attempting to push
information on the interrupt stack, the processor is halted and
only the state of ISP, PC, and PSL is insured to be correct for
subsequent analysis. The PSL and PC have the values that would
have been pushed on the interrupt stack.

The value of PSL(TP> that is saved on the stack is as follows:
fault
trace
interrupt

clear
clear
clear (if FPD set)
from PSL<TP) (if after traps, before trace)
from PSL<TP)
from PSL<TP)
from PSL<TP)
clear
clear

abort
trap
CHMx
BPT, XFC
reserv.instr.

The value of PC that is
following:
fault
trace
interrupt
abort
trap
CHMx
BPT, XFC
reserv.instr.

saved

the

stack

points

the

instruction faulting
next instruction to execute
instruction interrupted or
next instruction to execute
instruction aborting or
detecting Kernel Stack Not Valid
(not ensured on machine check)
next instruction to execute
next instruction to execute
BPT, XFC instruction
reserv.instr.

The non-interrupt stack pointers may be fetched and stored by
hardware in either privileged registers or in their allocated
slots in the PCB. Only LDPCTX and SVPCTX always fetch and
store in the PCB, see Chapter 7. MFPR and MTPR always fetch
and store the pointers whether in registers or the PCB.

Copyright(c) 1979 Digital Equipment Corp. ,Maynard ,Mass.
DO NOT COpy
VAX-11 System Reference ~~nual
COMPANY CONFIDENTIAL
Exceptions and Interrupts
31-Jan-79 -- Rev 6
Page 6-40
RELATED INSTRUCTIONS

6.9

RELATED INSTRUCTIONS
REI

Return from Exception or Interrupt

Opcode
Operation:
tmp1 <- (SP)+;
tmp2 <- (SP)+;

Pick up saved PC
and PSL

if {tmp2<CUR_MOD> LSSU PSL<CUR_MOD>} OR
{tmp2<IS> EQLU 1 AND PSL<IS> EQLU O} OR
{tmp2(IS> EQLU 1 AND tmp2<CUR_MOO> NEQU O} OR
{tmp2(lS> EQLU 1 AND tmp2<IPL> EQLU O} OR
{tmp2(IPL> GTRU 0 AND tmp2·<CUR_lvIOD> NEQU O} OR
ttmp2(PRV_MOD> LSSU tmp2<CUR~~OD>} OR
{tmp2(IPL> GTRU PSL<lPL>} OR
{tmp2(PSL_MBZ> NEQU O} then {reserved operand fault};
if {tmp2<CM> EQLU 1} AND
{{tmp2(FPD,IS,DV,FU,IV> NEQU O} OR
{tmp2<CUR_MOD> NEQU 3}} then {reserved operand fault};
if PSL(IS> EQLU

then ISP <- SP
!save old stack pointer
else PSL<CUR_MOD>_SP (- SP;
then tmp2<TP> <- 1;
!TP (- TP or stack TP

if PSL(TP> EQLU
PC <- tmp1;
PSL (- tmp2;
if PSL<IS> EQLU 0 then
begin
SP (- PSL<CUR_MOD>_SP;
!switch stack
if PSL<CUR_MOD> GEQU ASTLVL
!check for AS! delivery
then {request interrupt at 1PL 2};
end;
{check for software interrupts};
Condition Codes:
saved PSL<3>;
Z <- saved PSL(2);
V <- saved PSL<1>;
C <- saved PSL<O>;

N <-

Exceptions:
reserved operand
Opcodes:
02

REI

Return from Exception or Interrupt

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Exceptions and Interrupts
31-Jan-79 -- Rev 6
Page 6-41
RELATED INSTRUCTIONS
Description:
A longword is popped from the current stack and held in a temporary PC.
A second longword is popped from the current stack and held in a
temporary PSL. Validity of the popped PSL is checked.
The current
stack pointer is saved and a new stack pointer is selected according to
the new PSL CUR_HOD and IS fields (see 6.10.3).
The level of' the
highest privilege AST is checked against the current mode to see whether
a pending AST can be delivered; refer to chapter 7. Execution reSlli~es
with the instruction being executed at the time of the exception or
interrupt. Any instruction lookahead in the processor is reinitialized.
Notes:
1.

The exception or interrupt service routine is responsible for
restoring any registers saved and removing any parameters from
the stack.

As us~al for faults, any Access Violation or Translation Not
Valid conditions on the stack pops restore the stack pointer
and fault.

3 .. The non-interrupt stack pointers may be fetched and stored
either in privileged registers or in their allocated slots in
the PCB. Only LDPCTX and SVPCTX always fetch and store in the
PCB (see Chapter 7). MFPR and MTPR always fetch and store the
pointers whether in registers or the PCB.

4 Ju." 1.·:ecf'f~L~ , d ..,.
I

~ ~'V\,,,4\" ..

Copyright(c) 1979 Digital Equipment Corp.,tt~ynard,Hass.
DO NOT COpy
VAX-11 System Reference tv"anual
COMPANY CONFIDENTIAL
Exceptions and Interrupts
31-Jan-79 -- Rev 6
Page 6-42
RELATED INSTRUCTIONS
CHM

Change Mode

Purpose:

request services of more privileged software

Format:
opcode

code .rw

Operation:

;'"

tmp1 <- {mode selected by opcode (K=O, E=1, 8=2, U=3)};
tmp2 <- MINU(tmp1, PSL<CURjiOD»;
!maximize privilege
tmp3 <- SEXT (code);
if {PSL<IS> EQLU 1} then HALT;
!illegal from 1 stack

~~iO )., PSL<CUR_MOD>.J)P <- SP;

~'(.

!save old stack pointer

if ~ (!), tmp4 <- tmp2_SP;
! get new stack pointer
~\;,
----.,1 PROBEW (from tmp4-1 through tmp4-12 with mode=tmp2);
! check
~'
I'~~! new stack access
AS\'; /
if {access control violation} then
{initiate access violation fault};
if {translation not valid} then
/ .
tinitiate translation not valid fault};

",---;,.n. .

{initiate CHMx exception with new_mode=tmp2
and parameter=tmp3
using 40+tmp1*4 (hex) as SCB offset
using tmp4 as the new SP
and not storing SP again};
Condition Codes:
N <Z <V <C <-

0;
OJ
O·,
0;

Exceptions:
halt
Opcodes:

Be
BD
BE

CHtvlK
CHME
CHMS
CHMU

Change tvlode to Kernel
Change Mode to Executive
Change Mode to Supervisor
Change i"'lode to User

Copyright(c) 1979 Digital Equipment Corp. ,ZVlaynard,Mass.
DO NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Exceptions and Interrupts
31-Jan-79 -- Rev 6
Page 6-43
RELATED INSTRUCTIONS
Descriptic)n:
Change Mode instructions allow processes to change their access mode in
a controlled manner.
The instruction only increases privilege (i.e.,
decreases the access mode).
A change in mode also results in a change of stack pointers;
the old
pointer is saved, the new pointer is loaded. The PSL, PC, and code
passed by the instruction are pushed onto the stack of the new mode.
The saved PC addresses the instruction fol~owi.ng the CHMx instruction.
The code is sign extended. After execution, the new stack's appearance
is:

+---------------------------------------------------------------+
sign extended code
:(SP)
+-----------------------------------------------~---------------+

PC of next instruction

+---------------------------------------------------------------+
old PSL
+---------------------------------------------------------------+
The destination mode selected by the opcode is used to obtain a location
from the System Control Block.
This location addresses the CHMx
dispatcher for the specified mode. If the vector<1:0> code NEQU 0 then
the operation is UNDEFINED.
Notes:
1.

As usual for faults, any Access Violation or Translation Not
Valid fault saves PC, PSL, and leaves SP as it was at the
beginning of the instruction except for any pushes onto the
kernel stack.

The non-interrupt stack pointers may be fetched and stored
either in privileged registers or in their allocated slots in
the PCB. Only LDPCTX and SVPCTX always fetch and store in the
PCB, see Chapter 7. MFPR and MTPR always fetch and store the
pointers whether in registers or the PCB.

By software convention, negative codes are reserved to CSS
customers.

Examples:
CHMK

;request the kernel mode service
; specified by code 7

CHME

1/4

;request the executive mode service
; specified by code 4

CHMS

/J-2

;request the supervisor mode service
; specified by customer code -2

and

Copyright(c) 1979 Digital Equipment Corp.,Haynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COI-1PANY CONF'IDENTIAL
Exceptions and Interrupts
31-Jan-19 __ Rev 6
Page 6-44
PROCESSOR STATE TRANSITlON TABLE
6.10

PROCESSOR STATE TRANSITION TABLE

FINAL STATE
\
INITIAL:
STATE

User
IS=O
1PL=0

User
18=0
IPL=O

REI

Super
lS=O
IPL=O

Exec
lS=O
IPL=O

Kernel
IS=O
IPL=O

Kernel
IS=1
IPL)O

Kernel
lS=O
IPL)O

Program
Halt

+--------+--------+--------+--------+--------+--------+--------+
CHMU
CHMS
CHME I CHMK IInter(0)IExcep(1): impos- I
I

:Excep(O):

IInter(1):

sible I

" I

+--------+--------+--------+--------+--------+--------+--------+
Super
CHMU,S
CHME: CHt'lK :lnter(O)IExcep(l)I impos- I
15=0
IPL=O
Exec
IS=O
IPL=O
Kernel
IS=O
IPL=O

Kernel
IS=O
IPL)O

Kernel
IS=1
IPL)O

REI

REI-

IExcep(O)1
I
'

I
I

linter(1)1

sible I

I
I

+--------+--------+--------+--------+--------+--------+--------+
ICHMU,S,E: CHMK Ilnter(0)IExcep(1)1 impos- I
REI*

REI*

REI

IExcep(O)I

IInter(1):

sible I

+--------+--------+--------+--------+--------+--------+--------+
:CHNUSEK IMTPR IPLI SVPCTX IHALT
I
REI*

REI*

REI* lInter(0)IExcep(1)1 Instr.l
IExcep(O) :
IInter( 1 ) I
IMTPR IPL:
: LDPCTX :

REI~:

+--------+--------+--------+--------+--------+--------+--------+
ICHMUSEK I
REI*

8E1*

RE1*

MTPR IPLI REl* I SVPCTX IHALT
REI~
IExcep(0)IExcep(1)1 Instr.
IInter(0):Inter(1)1
IMTPR IPLI
I LDPCTX I

+--------+--------+--------+--------+--------+--------+--------+
SVPCTX IHALT
:
REI-

REI*

REI-

LDPCTX
REI*

REI*

REI
I lnstr. :
Excep ICHMUSEK
I Inter I
IMTPR IPLI

+--------+--------+--------+--------+--------+--------+--------+
Inter is Interrupt
Excep is Exception
i

(0) is vector(1:0> = 0; see 6.9
(1) is vector(1:0) = 1; see 6.9

Any REI that increases mode can cause an
interrupt request at IPL 2 for AST delivery.
Processor State Transitions

(End of Chapter 6]

Di~it?l EQuipm~nt

Corporation COMPANY CONFIDENTIAL

Pap;e ,

VAX .. " Process Structure ~~ Rev 4

Title:

Specification Status:
Arcnit~ctural

File:

Status:

under ECO control

SR7R4.V07

PDM II: not used

Superseded Specs:
Author:

Hustvedt

Typist:

Ford, B.

Review~r(s):

Abstract:

~evis1on

Call

P. Conklin,
P. Lipman,
B. Strecker

D. Cutler,
D. Rodgers,

Hustvedt t
S. Rot.hman,

J. Leonard,
B. Stew8.rt,

Chapter 7 describes the set of h~rdware primitiveB provided
in
VAX-1'
that
permit
the implement~tion of hi~h
performanoe process di~patchin,O': softwar~. It defines the
process context known to hardw~re, the process control
plock (PCS) and the handlin~ of softwarp. interrupts termed
asynchronous system tr9ps (ASTs).
History:

Rev #

De~criptiol'l

Author

RflV 1

issue
Revised for software needs
Total Rewrite
Fixes to LDPCTX and SVPCT~

Hastin~s

Revised D?te
Oct·75

Hustvedt
Hustvedt
Con kl in/Ta yl or

8-Jun-76
1O-A uv, .... 78

Rev ¢
Rev 3
Rev 4

Ori~inal

J~n-76

10-Aug~78 ~-

Process Structure
Chanp:e History

Rev 4

Pa~~

7-990

Rev 3 to Rev 4:
L

Typos.

Add privilep;ed register descriptions of ASTLVL s.nd PME, includin~ their
initial values.

ASTLVL GEOU 5 is reserved,

Contents of PCBB is initially UNPREDICTABLE.

Change "privileged instruction" to "reserved instruction."

Chan~e

Scheduler runs on IPL = 3.

Add software offsets for PCB.

Add notes to LDPCTX and SVPCTX.

10.

Add reserved operand checks to LDPCTX.

R12, R13 to APt FP.

Revision 3 is a total rewrite repl~cin~ all previous revisions.
1.

All process structure instructions described in previous revisions are
deleted as wel! as the descriptions of firmware implemented scheduling.
These changes were made as the result of efforts to simplify the VAX
architecture and reduce i~plementation risks. The primitives described
in this revision Bre believed to be sufficient to implement the same
functionaity in software.

Deleted CHMI instruction

Changed LDPCTX to effeot transition to Kernel Stack.

Changed SVPCTX to include function of CHMI.

Add tr~nslation buffer pur~p to LDPCTX.

·6.

Chan~ed

interrupt priority level numberin~ to eliminate n~R:ative IPL.

[End of SR7R4.RNO]

Copyright( 0) , 979 Digital EquiplIumt Corp. ,Maynard, Mass.
DO NOT COpy
VAX-l1 System Reference Manual
COMPANY CONFIDENTIAL

CHAPTER 7
PROCESS STRUCTURE

A process 1$ a sin,le thr,ad of execution.
It is the ba~ic
sohedulable entity thet is exeeuted by th~ processor. A process
con~1stsQf an adoreS$ $paQe and both hardwa.re and
software context.
The hardw.re qontex1,:. of a process is defined by a Process Control
Block (PCS) that contai~s irpages ()f the 14 general p~rpose registers,
the prooessor $t~t\,Js longword (P$L). the program counter. (PC), the 4
per-process stack po1nters, the f)roe~ss virtual memory defined by the
base and lenp.!th regist~rs POSR, POLR, P1BR, and P1LR and several minor
control field"
lnord~rror a proce~$ to ex;eout~,
the majority of
the pce Ptustbemoved into the internal rep:isters,. While a process is
executing, $oU!e of~t~ tiardware oontext is being updated in thf'
j,.,ternal registers, When~ pr~oesl 1;, not bein~ executed its hardware
context ~s ~toredit\ a data stru~turetermed the Prooess Control Block
(PCB).
Sav1~~ th. contents of the privile~ed r.gisters in the PCB of
the currently execut1n~ prooe~~ ~l1d then loading a new set of context
from another PCB is term$oQontext switching. Context switchin,:r
occurs as on~ prooess $fteranott\er is scheduled for execution.

Copyri!l:ht(c) '979 PiQ'italEquipment Corp.,Maynard,Ma~s.

System Reference Manval
COMPA~Y CONFIDENTIAL
Process Structure
10-Au~~78 -- Rev ~
PROCESS CONTEXT

DO NOT CO~y

VAX~'1

7.2

Pa~e

7-2

PROCESS CONTEXT

7.2.'

Process Control Block Base (PCBS)

The proces~ control block for the currently execut1n~ process is
pointed to by the conte~t of the Process Control Block Base (PCBB)
register, an internal privileged rellister.
PCBS

332
109

lMEZI

210

physical lon~word address of PCB

IMBZI

(read/write)
Prooess Control Block Base
At bootstrap t~me, the contents of PCBB is UNPREDICTABLE~

7.2.2

Process Control Block (PCB)

The process control bloqk (PCB) contains all of the switchable process
context collected into a compact form for ease of movement to and from
the privileged internal regi~ters. Although in ~ny . nor~al op~ratin~
system· there is addition~.l software context for each process, the
followincr description is limited to that portion of the PCB known to
the hardwflr~.

Copyright(c) 1979 Di~ital Equipment Corp, ,M~ynard,Ma$s.
DO NOT COpy
VAX-11 System ReferencF Manual
COMPANY CONFlD~NTIAL
Process Structure
PROCESS CONTEXT

10-Au~-78

.- Rev 4

Process Control Block (PCB)
31

Pave 7-3

o
I :PCB

KSP
ESP

SSP
USP

+12

+,6

+20

R3
R4

+32

+36

R7
R8
R9

+52

R10

+56

R11

+60

AP(R12)
+------~-~.,---~--

MBZ

AST
LVL

FP(R13)

+68

+72

PSL

+76

POER

+80

.. -.......... . . -----.......... --".. ..-. . . ,...--..,""',.W',...'-_.. _,.. ..... ""......""' ... +
~-

.84

I
I

POLF

IMBZ:

P1BR

+88
+92

Cooyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Process Structure
10-Aug-78 -- Rev 4
PB~e 7-4
PROCESS CONTEXT
Description of Process Control Block
Longword

Bits

Mnemonic

Description

<3' : 0>

KSP

Kernel St8ck Pointer. Contains the
stack pointer to be used when the
current access mode field in the
PSL is 0 and IS = O.

<31: 0>

ESP

Executive Stack Pointer.
Contains
the stack pointer to be used when
the current access mode field in
the PSL is 1.

<31: 0>

SSP

Supervisor Stack Pointer. Contains
the stack pointer to be used when
the current access mode field in
the PSL is 2.

<31: 0)

USP

User Stack Pointer.
Contains the
stack pointer to be used when the
current access mode field in the
PSL is 3.

4-17

<31: 0>

RO-R 11,
AP,FP

General re~isters RO throu~h R11,
AP, FP.

<31: 0)

Program Counter.

<31: 0)

PSL

Proa;z:ram Status Lona:z:word.

<31: 0>

POBR

Ba se

for
pa.~e
table
process
virtual
addresses from 0 to 2**30-1.
See
chapter 5.
re~ister

describin~

<21: 0>

POLR

Length re~ister for page
table
located
by
POBR.
Describes
effective len~th of page table.
See chapter 5.

<23: 22)

MBZ

Must be zero.

Copyright(c) 1919 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX ... 11 System Reference Manual
COMPANY CONFIDENTIAL
Process Structure
10-Au~-78 -- Rev 4
Page 1-5
PROCESS CONTEXT
.
21

<26:24>

ASTLVL

Contains
access
mode
number
established by software of the most
privileged access mode for which an
AST
is
pending.
Controls the
tri~~erin~
of the AST
delivery
interrupt during REI instructions.
Meaning

ASTLVL

AST pending for
mode 0 (kernel)

access

AST pendin~ for access
mode 1 (executiJe)
2

AST pending for access
mode 2 (supervisor)

AST pendin~ for
modp 3 (user)

No pendin~ AST

5-1

Reserved to DIGITAL

access

<31:21>

MBZ

Must be zero.

<31: 0>

P1BR

Base register
describing
addresses from
See cha.pter 5.

<21: 0>

P1LR

table
Length register for page
located
by
P1BR.
Describes
effective length of page table.
See cha.pter 5.

<30:22>

MBZ

Must be zero.

<31>

PME

Performance Monitor Enable controls
a signal visible to an external
hardware performance monit.or. This
bit
is
set to identify those
processes for which monitoring is
desired and permit their behavior
to be observed without interference
from other system activity.

for
page
table
process
virtual
2**30 to 2**31-1.

Software symbols are defined for these locations by usin~ the prefix
PTX$L_ and the mnemonic shown above. For example, the PCB offset to
R3 is PTX$L_R3. The following are also defined:
longword 21

1979 Di~ital Equipm~nt Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Process Structure
10-Au~-78 -- Rev 4
Pa~e 7-6
PROCESS CONTEXT
Copyri~ht(c)

lon~word

To alter its POBR, P1ER, POLR, P1LR, ASTLVL or PME, a proces~ must b~
executin~
in kernel mode. It must first store the desired new value
in the memory irnaFe of the PCB then move the vplu~ to the appropriate
privile~ed
re~ister.
This protocol results from the fact th~t these
are read-only fields (for the context switch instructions) in the PCB.

7.2.3

Process Privileged Re,z:isters

The ASTLVL and PME field~ of the PCB are contained in registers when
the process is runnin~.
In order to access them, two privileg~d
re~isters are provided.
3
1

3 2
i~nored;

returns 0

IAST- I
LVLI

(read/write)
AST Level Re~istpr
An MTPR src,#ASTLVL with src<2:0> GEQU 5 results in a reserved operand
fault. At bootstrap time, the contents of ASTLVL is 4.
3
1

1 0

MBZ

(read/writ.e)
Performance Monitor Enable Re~ister
At bootstrap time, PME is cleared.

IP I
IMI
IE·I

Copyright(c) 1979 Di.rz:ltal Equipment Corp.,Maynard,M~s~.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Process Structure
10-Au~-78
Rev 4
Page 7~7
ASYNCHRONOUS SYSTEM TRAPS (AST)

7.3 ASYNCHRONOUS SYSTEM TRAPS (AST)
Asynchronous system traps are a techniqu~ for notifying a process of
events that are not synchronized with its execution and ini ti.atinp.;
processin~ for asynchronous events
with the least po~sible delay.
This delay in delivery may be due to either process non~residence or
an access mode mismatch. The efficient ha.ndlinp: of AST' s in VAX-11
requires some hardware assistance to detect changes in access mode
(current access mode in PSL).
Each of the four execution acce~s
modes, kernel, exec, super, and user, may receive AST'sj however, an
AST for a less privileged access mode must not be permitted to
interrupt execution in a more prote(!ted access mode~ Since outward
access mode transitions occur only in the REI instruction, comparison
of the current access mode field is made with a privileged re~ister
(ASTLVL) containing the most privileged access mode number for which
an AST is pending. If the new access mode is p:reater tha.n or equal to
the pending ASTLVL, an 1PL 2 interrupt is tri~gered to cause delivery
of the pending AST.
General Software Flow for AST processing:
1.

An event a.ssociated wi th an AST causes soft~re enqueuing of
an AST control block to the software PCB and the software
sets the ASTLVL field in the hardware PCB to the most
privileged access mode for which an AST is pending. If the
target process is currently executing, the ASTLVL privileged
re~ister also has to be set.

When an REI instruction detects a transition to an access
mode that can be interrupted by a pending AST, an IPL 2
interrupt is tri~~ered to cause delivery of thp. AST.
Note
that the REI instruction does not make pendin~ AST checks
while returning to a routine executing on the interrupt
stack.

The (IPL 2) interrupt service routine should compute th~
corrp.ct new value for ASTLVL that prevents additional AST
delivery interrupts while in kernel mode and move that value
to the PCB and the ASTLVL re~ister before lowerin~ IPL and
actually dispatching the AST. This interrupt service routine
normally executes on the kernel stack in the context of the
process receiving the AST.

At the conclusion of processin~ for an AST, the ASTLVL is
recomputed and moved to the PCB and ASTLVL register by
software.

Copyright{c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COPY
VAX-11 Sy~te~ Reference Manual
COMPANY CONFIDENTIAL
Process Structure
10-Aup-78
Rev 4
Pa~e 7-8
PROCESS STRUCTURE INTERRUPTS

1.4 PROCESS STRUCTURE INTERRUPTS
Two of the software interrupt
structure 8oftware.

prioritips

are

reserved

for

process

They are:
(IPL 2) - AST delivery interrupt.
This interrupt is tri~gered by a REI that detects PSL<CUR_MOD> GEQU
ASTLVL and indicates that 8. pending AST may now be delivered for the
currently executinp; process.
(IPL 3) ~ Process scheduling interrupt.
This interrupt 1s only trig~ered by software to allow the software
running at IPL 3 to cause the currently executing process to be
blocked and the highest priority executable process to be sch~duled.

7.5

PROCESS STRUCTURE INSTRUCTIONS

Process scheduling software must ex~cute on the interrupt stack
(PSL<IS> set) in order to have a non-context switched stack available
for use. If the scheduler were running on a process's kernel stack,
then any state information it had there would' disappear when a new
proceee is selected. Running on the interrupt stack can occur as the
result of the interrupt origin of scheduling events, however some
synchronou$ scheduling requests such as a WAIT service may want to
cause rescheduling without any interrupt occurrence. For this reason,
the Save Process Context (SVPCTX) instruction can be executed while on
either the kernel or interrupt stack and forces a transition to
execution on the interrupt sta.ck.
All of the process structure instructions are privileged
kernel mode.

and

require

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-1'1Syetem Reference Manual
COMPANY CONFIDENTIAL
Process Structure
10-Au~-78
Rev 4
Page 7-9
PROCESS STRUCTURE INSTRUCTIONS
LDPCTX
Purpose:

Load Process Context

restore re~ister and memory ma.nagement context

Format:
opcode
Operation:
if PSL<CUR_MOD> NEQU 0
then {privileged instruction fault};
{invalidate per-process translation buffer entries};
!PCB is located by physical address in PCBB
if {internal registers for stack pointers} then
begin
KSP <- (PCB);
ESP <- (PCB+4);
SSP <- (PCB+8);
USP <- (PCB+ 12);
end;
RO <- (PCB+16);
R1 <- (PCB+20);
R2 <- (PCB+24);
R3 <- (PCB+28);
R4 <- (PCB+32);
R5 <- (PCB+36);
R6 <- (PCB+40);
R7 <- (PCB+44);
R8 <- (PCB+48);
R9 <- (PCB+52);
R10 <- (PCB+56);
R11 <- (PCB+60);
AP <- (PCB+64);
FP <- (PCB+68);
tmp1 <- (PCB+80);
if {tmp1<31:30> NEQU 2} OR {tmp1<1:0> NEQU O} then
{reserved operand abort};
POBR <- tmp 1;
if (PCB+84)<31:27> NEQU 0 then {reserved operand abort};
if (PCB+84)<23:22> NEQU 0 then {reserved operand abort};
POLR <- (PCB+84)<21:0>;'
if (PCB+84)<26:24> GEOU 5 then {reserved operand abort};
ASTLVL <- (PCB+84)<26:24>;
tmp1 <- (PCB+88);
tmp2 <- tmp1 + 2**23;
if·{tmp2<31:30> NEOU' 2} OR {tmp2<1:0> NEQU O} then
{reserved operand abort};
P1BR <- tmp1;
if (PCE+92)<30:22> NEOU 0 then {reserved operand abort};
P1LR <- (PCB+92)<21:0>;
PME <- (PCB+92)<31>;
:J.4. (PSB+9~)<~(}.22> N!Qt1 (} then {reserved operafiCl a.hOI t};
if PSL<IS> EOLU 1 then

Copyright(c) 1979 Pif;ital ~qlll ...nt Corl>.,M"n~rd,Ma~."
DO NOT Cppy
VAX-1' Syst~m Ref~rence M~nu~lCOMl"AN1CONfIPENTIAL
Process Structure
10~A~~~78
Rev 4
Pe~~ 7-10
PROCESS STRUCTURE INSTRUCTIONS

bep:in
ISP ('" Sf;
{int~rrupt$ off};
PSL<lS> <... 0;

Sf <. . (PCB);

!~et

{interrupts on};
,nd;
-(SP) <~ (PCB+76)
-(SP) <- (PCB+72)

KSP

'push PSL
!push PC

Condition Codes:
N <... N;
Z <- Z;
V <- V;
C <-

Exceptions:
reserv~d

operand
1nstruetion

pr1vile~ed

Opcodes:

LDPCTX

Load Process Context

Description:
The Process Control Block is sP~oified by the privtl~~ed register
Process Control Block Base. The «enfral register! are loaded from t~e
PCB. The memory management l"e'ister~ de~(!ribinp; the proqess address
spcce are also loaded and the proo.,ss entries in the translation
buffer are cleared. Execution ~~. :!Switched to ~h~ kernel $taek.
Tne
PC and PSL ~re movfld from thE> PC~to the ~taek, luitable for U$e by a

subsequent REI instruotion.
Note:
1.

Some prOQessors keep a QOPY ot each ofth~ pel"~prQce~$ stao~
pointera in int~rnal re~ister~, Il' 1j.hose prooe$sor~ thet do,
LDPeTX loads the internal r~~l$ter~ trom the PC~~ ThQse
processors thet do not kpep aeoPYQf' all four per... proqeS$
stack pointers 1n internal re~1stersJ keep only the ourrent
access mode register in ~n ~ntf:rnal re~1ster and switch this
with the PCB cQntent$ whenever the eurr,nt ecc"$~ mod~ field
changes.

Some implernentations !l)ay not
reserv~d operand Qh,cks~

perform s()me or all of the

Copyrip:ht(c) 1979 Dig:ital Equipment Corp"Maynard,Mase,
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VAX-11 System Referenc~ Manuel
COMPANY CONFIDENTIAL
Process Structure
10~Au~-78 •• Rev 4
Pa~~ 7-11
PROCESS STRUCTURE INSTRUCTIONS
SVPCTX
Purpose:

Sav~

Prooess Context

save re~ister context

Format:
opcode
Operation:
if PSL<CUR~OD> NEOU 0 then
{privileged instruction fault};
IPCB is located by physioal add~ess in pcse
if {internal registers for staok pointers} then
be~in

(peE)

<- KSP;

(PC5+4) <- ESP;
(PCB+8) <- SSP;
(PCB+12) <- USP;
end;
(PCB+16) <- RO;
(PCB+20) <- R1;
(PCB...24) <- R2;
(PCB+28) <- R3;
(PCB+32) <- R4;
(PCB+36) <- R5;
(PCB+40) <... R6;
(PCB+44) <- R7;
(PCB+48) <- H8;
(PCB+52) <... R9;
(P(:B+56) <"PO F10;
. (PCB+60) <- R11;
(PC13+64) <- AP;
(PCB+68) <- FP;
!pop PC
(PCB+72) <... (SP)+;
(PCE+76) <- (SF)+;
!pop PSL
If PSL<IS> EQLU 0 then
beg;in
PSL<IPL> <- MAXD(1, PSL(IPL» ;
!s~ve KSP
(PCB) <- SP;
{interrupts off};
PSL<IS> <- 1;
SP <- ISP;
{interrupts on};
end;
Condition Codes:
N <- N;

Z <- Z;
V <- V;
C <- C;
Exceptions:

1919 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-'1 Syst,m Reference Manual
COMPANY CONFIDENTIAL
Process Structure
10~Aug-18
Rev 4
Pa,~e 1-12
PROCESS STRUCTURE INSTRUCTIONS

COPJri~ht(c)

privileged instruction
Opcodes:
SVPCTX

Save Process Context

Description:

The Procee! Control Block is specified by the privile~ed re~ister
Prooes$ Control Block Base. The general registers are saved into the
PCB. The PC and PSL currently on the top of the current stack are
popped and stored in the PCB. If a SVPCTX instruction i~ executed
when IS is clear, then IS is set, the interrupt stack pointer
activated, and, IPL is maximized with 1 because of the swl tch to the
interrupt stack.
Notfls:
1.

The map, ASTLVL, and PME contents of the PCB are not saved
because they are ra.rely changed.
Thus, not wri tin.'!: them
saves overhead.

Some processors keep a copy of each of the per-process stack
pointers in internal registers. In tho~e processors that do,
SVPCTX stores the internal registers into the PCB.
Those
processors that do not keep a copy of all four per-process
stack pointers in internal registers, keep only the current
access mode re~ister in an internal register and switch this
with the PCB contents whenever the current access mode field
ohanges.

Between the SVPCTX instruction that saves state for one
proces! and the LDPCTX that loads the state of another, the
internal stack pointers may not be referenced by MFPR or MTPR
instructions.
This implies that interrupt service routines
invoked at a priority higher than the lowest one used for
context switching must not reference the process stack
pointers.

Copyri~ht(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Process Structure
10-Aug-78 -- Rev 4
Pa~e 7-13
USAGE EXAMPLE

7.6

USAGE EXAMPLE

The following example is intended to illustrate how the process
structure instructions can be used to implement process dispatching
software. It is assumed that this simple dispatcher is always entered
via an interrupt.
ENTERED VIA INTERRUPT
IPL=3
RESCHED:

SVPCTX

Save context in PCB

<Remove head of highest>
<priority, non-empty, >
<RUN queue.>
MTP~ @#PHYSPCB, PCBB
; Set physical PCB address
;in PCBS
LDPCTX
Load context from PCB
For new process
REI
Place process in execution
[End of Chapter 7]

Dir,ital Equipment Corporation COMPANY CONFlDENTIAL

Pa~e

VAX-'1 System Architectural Implications -- Rev 4

Title:

Specification Statu~:
Architectural Status:

Under ECO Control

SR8R4.V09

File:

PDM II: not used
Dat~:

10-Au~ ... 78

Superseded Specs:
Author:

Rodgers

Typist:

Bess

Reviewer(s):

Abstract:

P. Conklin,
P. Lipman,
B. Strecker

D. Cutler,
D. Rod~ers,

D. Hustvedt,
S. Rothman,

J. Leonard,
B. Stewart,

Chapter 8 discusses system structural implications and
implementation constraints of the VAX-" architecture. The
broad cate~orie$ of interaction are:
data sharin~ and
synchronization, restartability, interrupts and errors.
Chapter 8 also discusses I/O in a general way.

Revision History:
Rev II
Rev 3
Rev 4

Description
Original Version
Document cache and interlocks

Author
Revised Date
D. Rodgers
2-Jun-76
Conklin/Taylor 30-Jul-78

Sy~tem Archi~eoturel Implieation~

108Au«"78 -- R~v 4

Chan,ge Hi story

Rev 3 to Rev 4:
1~

Move 1/0 here from onapter 9.

Document int~rlock~ on ADAWI.

Document cache a.n9 its con~traints.

xx~OUE ~r~

Ensure that t'a'ul t when interlocked does not hang.

Note multiproc rule forupd~te !ystem PTEs.

Clean up di$cussion of interlocks.

Rev 3:

Original creation
[End of SR8R4.RNO)

aligned (ECO)~

CHAPTER 8
SYSTEM ARCHITECTURAL IMPLICATIONS

10-Au~-18

-- Rev 4

Certain portions of the VAX- l' a.rchi tecture have implications on the
sy~tem
structure of impl ementa.tions. There are four broad categories
of interaction: data sharing and synchronization, restartability,
interrupts and errors. Of these, data sharin~ is most visible to the
pro!trammer.

8.1

DATA SHARING AND SYNCHRONIZATION

The memory ~ystem must be implemented such that the ~ranularity· of
~ccess
for independent modification is the byte. Note tha.t this does
not imply a maximum reference size of one byte but only that
independent modifying accesses to adjacent bytes produce the same
results re~crdless of the order of execution.
For example, suppose
locations 0 and 1 contain the values 5 cnd 6. Suppose one processor
executes INCB 0 ?nd another executes INCB 1. Then regardless of the
order of execution, including effectively simultaneous, the final
contents must be 6 and 1.
Access to explicitly shared data thct may be written must be
synchronized by the pro~rammer or hardware desi~ner. Before accessing
shared writeable data, the programmer must acquire control of the data
structure.
Three instructions (BBSSI, BBCCl, ADAWI) are provided to
allow the programmer to control ("interlock") access to a control
variable.
These interlocked instructions must be implemented in such
a way that read, test, modify, and write happen while other processors
and I/O devices are locked out of performin~ interlocked operations on
t~esame.c~rt.~r.:?!._variab~ This is termed
an interlocked sequence.
Only'irit'er'Iocking-"'operations are locked out by the interlock. On the
VAX-1'/780, the SBl primitive operations are interlock read and
interlock write.
BBSSI and BBCCI instructions use
hardware
provided
primitive
operations to make a read reference, then test, and then make a write
reference to a sin~le bit within a single byte in an interlocked
seQuence.
The ADAWI instruction uses a hardware provided primitive
operation to make a read and then a write operation to a single

Copyright(c) 1979 Digital Equipment Corp. ,Maynard ,Mass.
DO NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
System Architectural Implications
10-Au~-78 -- Ret· 4
Pag~ 8-2
DATA SHARING AND SYNCHRONIZATION
aligned word in an interlocked sequence to allow counters to be
maintained without other interlocks. The ADAWI instruction takes the
hardware lock on the read of the .mw operand (the second operand which
is the one being modified).
and REMQUE instructions provide a series of .~~
reads and writes in an uninterruptible sequence to allow
queues to be maintained without other interlocks in a uniprocessor
system.

The INSQUE
lon~ord

In order to provide a functionality upon which some UNIBUS peripheral
devices rely, processors must insure that all instructions makin~ byte
op.'Z word sized modifying references (.mb a.nd
.mw) use the DATIP
/"""0 ATO (B) functions when the operand physical address selects a UNIBUS
device. This constra~nt does not apply to lonp:word, qua.dword, field,
floating, ~;;,l""W\ string operations if implemented usinsz; byte or
word modifying references. This constraint also does not apply to
instructions precluded from I/O space references (see Appendix F).
In a mul ti processor system, any software clearing PTE<V> or ch:;).nginp;
the protection code of a page table entry for system space such th~t
it issues a MTPR xxx,#TBIS must arrange for all other processors to
issue a similar TBIS. The original processor must wait until all the
other processors have completed their TBIS before it allows access to
the system page.

8.2 CACHE
A hardware implementation may include a mechanism to reduce access
time by making local copies of recently used memory contents. Such a
mechanism is termed a cache. A cache must be implemented in such a
way that its existence is transparent to software (except for timin~
and error reporting/control/recovery). In particular, the following
must be true:
1.

Program writp.s to memory followed by starting
output transfer must output the updated value.

peripheral

Completing a peripheral input transfer followed
pro~ram reading of memory must read the input value.

A write or modify followed by a HALT on one processor
followed by a read or modify on ~nother processor must read
the updated val uP.

A write or modify followed by a· power failure followed by
restoration of power followed bya read or modify must read
the updated value provided that the duration of the power
failure does not exceed the maximum non-volatile period of
the m~in memory.

the

Copyright(c) 1919 Digital Equipment Corp.,Maynard,Mass.
DO NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
System Architectural Implications
10-Aug-78 -- Rev 4
Page 8-3
CACHE
5.

In multiprocessor systems, access to variables shared between
processors must be interlocked by software executin~ one of
the interlocked instructions (BBSSI, BBCCI, ADAWI).

Vali.d accesses to I/O registers must not be cached.

On the VAX-11/780, this is achieved by a. cache that writes through to
memory and that watches the memory bus for all externa.l writes to
memory.
At bootstrap time, the cache must be either empty or valid.

-rr,!
8.3

RESTARTABILITY

The VAX-11 architecture requires tha.t all instructions be restartable
after a fault or interrupt that terminated execution before the
instruction was completed.
Generally, this means that modified
registers are restored to the value they had at the start of
execution. For some complex or iterative instructions, indicated in
Chapter 4, intermedi~te results are stored in the general registers.
In the latter case memory contents may have been altered but the
former case requires that no operand be written unless the instruction
can be completed. For most instructions with only a single modified
or written operand, this implies special processing only when a
multibyte operand spans a protection boundary making it necessary to
test accessibility of both parts of the operand.
In order that instructions which store intermediate results in the
general registers not compromise system integrity, they must insure
thet any addresses stored or used are virtual addresses, subject to
protection checking, and that any state information stored or used
cannot result in a non-interruptable or non-terminatin~ sequence.
Instruction operands that are peripheral device re~isters having
access
side
effects may produce UNPREDICTABLE results due to
instruction restarting after faults.
In order that software may
dependably access peripheral device registers, instructions used to
access them must not permit device interrupts during their execution.
Memory modifications produced as a side effect of
instruction
execution, e.~.
memory access statistics, are specifically excluded
from the constraint that memory not be altered until the instruction
can be completed.
Instructions that abort are constrained only
protection (e.g., re~isters can be changed).

insure

memory

Copyri~nt(c) 1979 Di~ital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
System Architectural Implications
10-Au~-78 -- Rev ~
Pa~e 8-~
INTERRUPTS

8.~

INTERRUPTS

Underlying the VAX-11 architectural concept of an interrupt is the
notion that an interrupt request is a static condition, not a
transient event, which can be sampled by a processor at appropriate
times.
Further, if the need for an interrupt disappears befor~ a
processor has honored an interrupt request, the interrupt request can
be removed (subject to implementation dependent timing constraints)
without consequence.
In order that software be able to operate deterministically it is
necessary that any instruction chan~in~ the processor priority (1PL)
such that a pending interrupt is enabled must allow the interrupt to
occur before executing' the next instruction that would ha.ve been
executed had the interrupt not been pending.
Similarly, instructions that ~enerate requests at the
software
interrupt levels (See Chapter 6) must allow the interrupt to occur, if
processor priority permits, before executin~ the apparently subsequent
instruction.

8.5

ERRORS

Processor error~, if not inconsistent with instruction compl~tion,
should create high priority interrupt reouests. Otherwise, they must
terminate instruction execution with an exception (fault, trap or
abort) , in which case there may also be an associated :i.nterrupt.
request.
Error notification interrupts may be delayed from the apparent
completion of the instruction in expcution at the time of the ~rror
but if enabled, the interrupt mu~t be requested before processor
context ifil switched, priority permitting:.
An example of A. case where both an interrupt and an exception are
associated with the same event occurs when the VAX-11/780 instru~tion
buffer gets a read data substitution (i.e. read memory data error).
In this case the interrupt request associated with error will not be
taken if the priority of the runnin~ pro~ram is hi~h, but an abort
will occur when an attempt is rnad€ to execute the instruction.
However, the interrupt is still pendin~ and will be taken when the
priority is lowered.

8.6

1/0 STRUCTURE

Copyright(c) 1979 Di~ital Equipment Corp. ,Maynard ,Mass.
DO NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
System Architecturel Implications
10-Au~-78 -- Rev 4
Pa~e 8-5
I/O STRUCTURE
8.6.1

Introduction

The VAX-11 I/O ~rchitecture is very similar to the PDP-11 structure,
the principal difference being the metpod by which processor re~isters
(such as the PSL) are accessed (see c'v.o:iJ'ume ~:~ 1).
Peripheral device
control/status and data registers appea~ at location~ in the physical
address space, and can therefore be manipulated by normal memory
reference instructions.
On the VAX-11/780 implementation, this I/O
space occupies the upper half of the physical address space. and is
2**29 bytes in length. Use of sreneral instructions permits ?11 the
virtual address m2ppin~ and protection mechanisms described in Chapter
5 to be used when referencing I/O r€~isters. Note: Implementations
that include a cache feature must suppress caching for references in
the I/O space.
For any member of the VAX-l1 series implementin~ the UNIBUS, there
will be one or more areas of the I/O physical address space each 2**18
bytes in lenl2:th, which "maps throtJP.:h" to the UNIBUS addresses.
The
collection of these areas is referred to as the UNIBUS space.

8.6.2

Constraints On I/O Registers

The followin.sz: is a list of both hardware and prop: rammi nF.t constraints
on I/O rep:isters.
These items affect both hardware register design
and pro~rammin~ considerations.
1.

The physical address of an I/O register must be an intep:ral
multiple of the register size in bytes, (which must be a
power of two);
i.e., all reF.ti~ters must be aligned on
natural boundaries.

References using a length attribute other than the length of
the
re~ister
and/or
unali~ned
references may produce
UNPREDICTABLE results. For example a byte reference to a
word-length
rep:ister
will
not necessarily respond by
supplyin~ or modifyin~ the byte addressed.

In all peripheral devices, error and status bits that may be
asynchronously set by the device must be cleared by software
writing a "1" to that bit position and not affected by
writinp: a "0". This is to prevent clearing bits that may be
asynchronously set between readin~ and writing a re~ister.

Only byte and word references of a read-modify-write (i.e.,
".mb" or ".mw") type in UNIBUS I/O spaces are guaranteed to
interlock correctly. References in the I/O space other than
in UNIBUS spaces are UNDEFINED with respect to interlocking.
This includes the BBSSI and BBCCI instructions.

Strinsz:, Quad, double, floating and field
I/O space result in UNDEFINED behavior.

references

the

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Ma.ss.
DO NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
System Architectural Implications
10-Au~-78 -- Rev 4
Page 8-6
I/O STRUCTURE
(End of Chapter 8J

Digital Equipment Corporation COMPANY CONF'lPENTIAL

Title:

Page 1

Privileged Register and Console Structure -- Rev 4

VAX~11

Specification Status:
Architectural Status:
File:

Under ~CO control

SR9R4.V11

PDM Ii: not used

Date:

4. . Aug-78

Superseded Specs:

C~9R3.SRM

Author:

Learoyd, P.

Typist:

Sleet

Reviewer(s):

P. Conklin,
P. Lipman,

Conklin

D. Cutler,
D. Rodgers,

D. Hustvedt,
S. Rothman,

J. Leonard,

B. Stewart,

B. Strecker

Abstra.ct:

Chapter 9 is divided into two major areas; the privileged
register
space;
and various architecturally defined
console functions. To ensure consistency across members of
the VAX architectur~, certain console functions are defined
architecturally. lhe second section of Chapter 9 describes
the operation of HALT, CONTINUE, IhITIALIZE, and some
restrictions on other console features.
Also, a m~n~mum
console functionality is defined, and a description of the
system bootstrap mechanism is given.

Revision History:
hev iF
Rev 1
Rev 2
Rev j
Rev 4

Description
Original
Added Registers
Added Console Specs
Add Processor Reg Specs

Author
Rodgers
Rodgers
Learoyd
Conklin/Taylor

Revised Date
10-0ct-75
21-fieb-76
3-Jun-76
4-Aug-'lb

Privileged Registers and Console
Change history

Page 9-990

4-Aug-78 -- Rev 4

Rev 3 to Rev 4:
1.

Remove I/O section to chapter 8.

i"lT/ f',,tJri 0 f xS,tJ al\liays works (~tack Register ECO),

Move I~L register to chapter 6.

ij.

Add SID definition.

Add Console terminal definition.

Add Clock definition.

Move TBlA/TbiS to chapter 5.

i'lOve VAX-ll /7 bO error registers to chapt\er 11.

Document VAA-11/'7bO accelerator registers.

10.

Document VAX-l1/780 Control store registers.

11.

hTPh faults if RO;

12.

Add register numbers.

lj.

Add VAX-ll/7dO registers to table.

14.

IPL is h/W not w.

15.

ICR is RO,

16.

add ASTLVL in 7;

17.

Add Initial values of all registers, T Buf, cache.

lb.

Add boot set of general registers.

19.

Make console terminal mandatory.

~O.

~iD<23:0> no~

21.

Add hO, RW, WC,

2~.

Clarify identity of function for
register number.

2~.

Console halt only between instruction;

24.

Change reset to initialize.

25.

change i buf clear from deposit to continue.

~ICR

MF~ri

is ~O;
kAP~h

faults if ~o.

not R/~.
in 5;

PMri in 7;

TOOR in ~.

type specific.
~u

field notations.
machines

having

the

not an interrupt.

same

~rivileged

riegisters and Console
Change history

4.Aug~7d

Page 9 .... ~~1

-- Rev 4

26.

Gonsole virtual relative to fJSL<CUk_l~'lQ1.».

21.

Add system restart section.

2b.

Move x~P to chapter 6.

29.

hove process registers to chapter 7.

30.

Clarify when RACS and TXCS cause interrupts.

)1.

~ake

ACC$ type be 8 bits.

32.

~ote

diagnostics use NOP for sGope sync.

jj.

Deposit/virtual command maintains PTE.

34.

Add 7bO SID spec.

35.

Name change CRxx, CTxx to HXxx, lXxx,

36.

Missing lODN is always O.

Rev 2 to Rev 3:
1.

Added notion of ~hlBUS space.

Added 1/0 register constraint rules.

Added 1/0 space interlocking.

Added f'ilTPrl , t-'lr'PH descriptions.

1"!TPR, NF'PR require kernel mode.

Added clocks, bootstrap (no spec yet).

r( •

Added WCS reg (no spec yet)

Added r~CS Internal f\egisters.

Added console function section.

10.

Deleted aescription of multiple register sets.

11.

Make WC~ registers implementatiQn-~pecific.

12.

uelete PSL in PIR space.

13.

Add discussion
register space.

14~

Added description of interval timer.

per~process

registers

privileged

Privileged Registers and Console
Change History
15.

4-Aug-18 -- hev 4

Add description of time-of-day clock

Rev 1 to Rev 2:
1.

Added list of privileged registers

Expanded I/O description

Expanded privileged register description.

[Bnd of SR9R4.RNO)

Page 9-992

Copyright(c) 19'(9 Digital Eq'-1il'ment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System ReferenCe Manual
CUMPANY CONFlDENT1AL

ChAPTER 9

PRIVILEG#:D REGISTERS AND CONSOLE

9.1

lNTRODUCTlON

Chapter 9 is divided into two major areas;
the privileged register
space;
and various architecturally defined console functions. To
ensure consistency across members of the VAX architecture, certain
console functions are defined architecturally. The second section of
Chapter 9 describes the operation of HALT, CONTINUE, INITIALIZE, and
some restrictions on other console features. Also 1 a minimum Qonsole
funotionality is defined, and a description of the system bootstrap
mechanism is a;iven.

9.2

PROCESSOR REGISTER SPACE

The processor register space (PRS) provides access to many types of
CPU control and stP,tus registers sucb as the memory management base
registers, the PSL, and the multiple stack pOinters. These registers
are explioitly accessible only by the Move to Processor Register
(tvlTPR) and Move from Processor Register (Mf'PR) instructions which
require kernel mode privileges. See section 9.2.3 for a description
of these instructions.
All the internal processor registers are summarized in the tables at
the end of this section.
lhose which need futher explanation are
described below. Refer-ence to general registers means RO through R13,
the SF, and the PC (See Ch~pter 2). Registers referenced by the MTPR
and MFPR instructions are designated processor registers, and appear
in the processor register space.

Copyright(c) 1979 Digital .t£quipment ('orp.,ha.ynerd,i'-!3sS.
D0 NuT COpy
VAX-ll System heference Manual
CONPANY CONr'IDE1-..TlAL
Privileged Registers and Console
4-Aug-1L -- hev 4
Pags 9~2
PROCESSOR REGI~T~R ~PACE
Per-process Hegisters And Context Switching

9.~.1

there are several per-process registers which are loaded from the PCB
during a context lo?d operation and, with the Exception of the memory
mapping registers and AST levEl, written back to the PCB during a
context save operation (see Cnapter 1). ~ome implementations may copy
some or all of. these r~gisters from the ~CB into scratchpad registers
ana write them back into the PCE during a context save operation.
Other implementations may retain the registers in main memory in the
PCB.
For this reason, reading or writing any of these registers via the
or MTPR instruction, or through reference to SF, mayor may not
read Or write the register copy in thE currEnt PCB, depending on the
implementation.
Likewise modifying one of these registers in the PCB
will not necessarily upaate the register which appears in the register
space or SP.

M~PR

Furthermore, it is possible that implementations which retain some or
all registers only in the PCb will implement the MTP~ and MFPrl for
those registers as a no-op, at least in the sense that the destination
or register is not written.
10 ensure that the PCB is always
correctly updated and to permit implementation flexibility, software
must use the following convention when referencing ~ny of the
per-process registers in the processor register space.

9.~.2

Nl'PR - .software must first write the valuE. directly into the
proper location in the current PCB by using a NOVL lfor
examp.i.e) then execut e an i'vdf'ri wi th the same source as tne
MUVL. ~mplement~tions which do not retain internal copies of
these registers may effectively no-op the r-'l1f'R instruction.
they must not, however, take a reserved operand fault which
would normally occur for a non-existent register.

£·iF'fJft - ~o ftware must first read the value directly

from the
proper location in the current PCb by using a MOVL (for
example), ~hen execute an MFPR instruction using the same
destination as the MOVL. ~mplementations which do not retain
internal copies of these registers may effectively no-op the
MFPR instruction.
Iney must not, ho~ever, take a reserved
operand fault which would normally occur for a non-existent
register.

~tack

Pointer ~mages

Reference to SP (the stack pOinter) in the general registers will
&ccess one of fiVe possible stacK pointer's; the user, supervisor,
executive, kernel, or interrupt stack painter, aepending on the values
of the current mode &nd IS bits in the P~L (see Chapter oJ. however,
software may access any of the four stack pointers not currently
selected by the current mode and ~S bits in the P~L via the MTPR ana

~ri.vil€ged

Registers and Console
PhOC6SSUrt REG1Sl~R SPACE

Corp.,,t.JCiynard,t-~qss.

DO NOT COpy

CONPANY CQNF'lDENTIAL
4-~ug-7b.-

Rev 4

Page ~-j

M¥fR instructions. kesults are ~~PRED1CTABL~ if the stack pointer
sp€cifi~d
by the current mode and l~ bits in the fSL is referenced in
the p~~ by an M1PR or MFPR instruction. ~lhis applies only to the K~P
and l~P, since these instructions require kernel privil~ge).

Copyright(c) 1919 Digital J!:quipment Corp. ,Maynard,tvlass.
DO NUl COpy
VA:A-11 ~ystem He ference tvIanual
COi-1PA:NY CONt'IDENTIAL
'Privileged Registers and Console
~-Aug-~8 -- Rev 4
Page 9-4
PROCESSOR REGISTER SPACE
9.2.3

fhe M1PR And MFPR Instructions

MTPR

Move To Processor Register

opcode

src.rl, procr€g.rl

Format:

Operation:
if PSL (CUR_I'1UD> hEQ 0 then {reserved
instruction f&ult};
PriS[procreg) <- src;
Condition Codes:
N <-

src LSS 0;
Z <- src EQL 0;
V <~ o·,

!if register is replaced

N <- 1-..;
L. <- Z;

!if register is not replaced (see 9.2.1)

C <- C;

V <- V;
C <.- C;

Exceptions:
reserved operand fault
reservea instruction fault
Opcode:
t1TPR

Move To Processor Register

Description:
Loads the source operand specified by source into the processor
register specified by procreg.
The procreg operand is a longword
Execution may have
Which contains the processor register number.
register-specific side effects.
.
Notes:
1.

~f the processor internal register does not exist a
reserved
operand fault may occur or the instruction may no-op (see

9.2.1).

A reserved instruction fault occurs if instruction
is attempted in other than kernel mode.

execution

Privileged Registers and Console

DO NOT COpy

COl"lPA.NY CUNr'lDENTIAL

4-Aug-18 -- Rev 4

Page 9-5

PROCESSQR REGISTER SPACE
MFPR

Move From Processor Register

Format:
opcode procreg.rl, dst.wl

Operation:
if PSL <CUR_MOD> ~EQ 0 then {reserved
instruction fault};
dst <- PRS[procreg];
Condition Codes:
N <- ost LSS 0;
'I.. <... dat EQL 0;

lif destination is replaced

V <- 0;
C <-

N <- N;
Z <- Z;
V <- V;

lif destination is nQt replaced (see 9~2.1)

C <- C;
t.:xceptions:
reserved operand fault
reserved in~truction fault

Upoode:

MFPR

Djj

Move From Processor Register

Description:
The destination operand is replaced by the contents of the processor
register specified by procreg.
lhe procreg operand is a longword
Execution may have
which contains the processor register number.
register-specific side effects.

l'4otes:
1.

If the processor internal register does not exist a reserved
operand fault may occur or the instruction may no-op (see
9.2.1).

A reserved instruction fault ocours if instruction
is attempted in other than kernel mode.

execution

Copyright(c) 1~n9 Digit~l Equipment Corp. ,M8yrlard,i"lass.
D0 NOT COpy
VAX-l1 .::,ystem Reference Nanual
CQI-jJ;JANY CONi'"'lDENI1AL
Privileged Registers and Console
4 ... Aug-;/b -- nE:V 4
Page 9-6
PRQC~~SOR hEG1SIER 6PAce
VAX~11

Series hegisters
Mne-

Hegister hams
Kernel ~taCK Pointer
Executive ~tack Pointer
Supervisor Stack Pointer
User ~tack Pointer
~nterrupt Stack fointer
PO Bas€ Register
fO Length Register
,tJ1 Base Register
P1 Length Register
~ystem tiase Register
System Limit Register
Process Control Block Base
System Control Blook Base
Interrupt Priority Level
AST Level
Software lnterrupt hequest
~oftware interrupt ~ummary
Interval Clock Control
~ext ~nterval Count
.i..nterval Gount
Time of Year loptional)
Consol~ Receiver C/~
Console Rec~iver D/b
Console Transmit CIS
Console Iransmit Dlb
1"~emor'y hanagem'2nt Enable
Trans. Buf. Invalidate All
Trans. buf. ~nvalidate Single
Per formancE. honi tor Bn.n-bla
System ldentific~tion

moni9

Number

Type

K~P

R/W
R/w

ESP

Scope

fRO(;
Pk{OC
,tJROC

SSP
USf

2
j

R/W

PrlOC

~SP

POER
POLR

CPU
FROC

R/W
R/W
N/W

P1BR

R/~

P1LH

H/W

FROC
PROC

SBR
SLR

12
13

R/~

P~6B

leB

16
11
16
19
20
21
24
25
26

R/w
R/W
R/W
R/W
W
H/W
R/W
W
R

IGDR

R/W

R~CS

RXDB
T1GS

~j
~4

TXDB

R/W
h
R/W
w

SCBb
IPL

AS1LVL
SIRR
SlSR

lces
N~CR

R/w

RI ~

.\.nit'?

PRoe
CPU
CPU

PROC
c~u

~fiU

yes

PRoe

yes

CfU

CPU
GPU

GfU
CPU
CPU
CPU
CPU

CPU

no
Yii;S

yes

CPU

i"lAPEh

HI W

CPli

161A

CPU

Tbl~

W
W

PMR

R/~

CPU
PROC

~~D

CPU

yes

yes
no

Copyrj.ght(o) 19'19 Digital bquipm~nt Corp. ,l'-'Jaynard,Mass.
DO NOT COpy
VAX ... 11 System Re ference rianual
COiYIPA1~~ CUNFIDENTlAL

Privileged Registers and Console
PROCESSOR REGISTER SPACE

4 Aug-7d -~ Rev 4

Page 9-7

VAX ... 11l780 Specific Registers
ZV'm€'I""

hegister hame
Accelerator Control/Status
Accelerator Maintenanc~
WC~ Address
wCS Data
SBl Fault/Status
S}5l '::>110

SBl Silo Comparator
~Bl Maintenance
Sbl f:,;rror R~gi~ter
~bl Timeout Addre~s
~t$l Quadword Clear
Micro Program areakpoint

monic

Aces
ACCrl

wCSA
wCSD
SBlFS
SBIS
SSlSC
SBINT
SBIER
SEITA
S:elQC
l"~BRK

!~umber

Type

Scope

R/W
R/w
R/W
R/w
R/W
R

CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU

48
49
50
51

R/W

R/w
R/W

..I

R/W

efU

CPU

In1 t"

yes
no
no

yes
yes
no

yes
yes
yes

no .

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAA-11 System Reference Manual
COMPANY CONFIDENTIAL
~rivileged Registers and Console
4-Aug-7d -- Rev 4
Page 9-8
SYSTEM IDENTIFICATlON REGISTER (SID)

S.3 SYSTEM lUENTIFICATION REGISTER (~lD)
The SlD is a read only constant register that specifies the processor
type.
the entire SID register is included in the error log and the
type field may be used by software to distinguish processor types.
l: 2

4 3

+--------------~+-----------------------------------------------+

TYPE:

type specific

+---------------+-----------------------------------------------+
(read only)
System Identification Register
Type

A unique

number assigned by engineering to identify a specific
processor:

o = Reserved to DIGITAL (error)
1 = VAX- 11 1'1 80

2 through 127 = Reserved to DIGITAL
128 through 255 = Reserved to CSS and customers
type specific

format and content is a function of the value -in
type. It is intended to include such information
as serial n~~ber and revision level.
For the VAX-11/780, the type specific format is:
2
j

1 1
6 5

1 1
2 1

+---------------+-------+-----------------------+
ECO level
: plant I
serial number
+---------------+-------+-----------------------+
9.4

CONSOLE TERMl~AL REGISTERS

lhe console terminal is accessed through four internal registers. Two
ere associated with receiving from the terminal and two with writing
to the terminal. In each direction there is a control/status register
and a data buffer register.

Copyright(c) 1979 Digital Equipment Corp.,~~ynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONF1DENTIAL
Privileged Registers and Console
4-Aug-78 -- Rev 4
Page 9-9
CONSOLE TERMINAL REGISTERS

8 "1 6 5

ID III
lulEI
I~: I

MBZ

NBZ

Console Receive Control/Status

(RXeS)

1 1 1

65421

1 1

8 'I

lEI

IRI
IR!

(read only)
Console Receive Data Buffer

DATA

I
·1

(RXDS)

At bootstrap time, RXes is initialized to O. whenever a datum is
received, the read only bit DONe is set by the 90nsole.
lf IE
(interrupt enable) is set by the software then an inte~rupt is
generated at IPL 20. Similarly, if DONe is already set and the
software sets ~E, an interrupt is generated (i.e., an interrupt is
generated whenever the function {IE AND DON} changes from 0 to 1). If'
the received data contained an error such as overrun or loss of
connection then ERR is set in RXDB.
The received data appears in
DATA.
When a MFPR #RXDB,dst is executed, DONe is cleared as -is any
interrupt request. If ID is 0 then the data is from the console
terminal.
If
ID
is
non~zero
then the entire register is
implementation dependent.

Copyright(c) 1979 Digital Equipment Corp.,iVJaynard,Hass.
DO NOT COpy
VAX-11 System Reference ~anual
CUl"1PANY CONfe'lDENTIAL
Privileged Registers and Console
lERMlhAL REGl~lERS

4-Aug-18 -- Rev 4

Page 9-10

CON~vLE

8 7 6 :,

:RD.:
ID IE I
:y: :

hbZ

MBZ

R Ft
()

Console Transmit Control/Status (IXC~)
j

1 1

2 1

lwrite only)
Console l'ransmi t Data Buffer

(fl'XDB)

At bootstrap time, lXeS is initialized with just the RDY bit set
(ready).
Whenever the console transmitter is not busy, it sets the
read only bit RDY. if IE (interrupt e~able) is set by the software
then an interrupt is generated at IPL 20. Similarly, if RDY is
already set and the software sets IE, an interrupt is generated (i.e.,
an interrupt is generated whenever the function {lE AhD RDY} ohanges
from 0 to 1). 'lhe software can send a datum by writing it to DATA.
When a M1PR src,#TXDb is expected, RDY is cleared as is any interrupt
request. if lD is written 0 then the datum is sent to the console
termin~l.
if
~D
is
non-zero
then the entire register is
implementation dependent.
On the VAX-11/'(t30 if l,u is one then the oatum is sent
disk.

the

floppy

C,;opyrignt(c) 19'(9 j)igital ~Quipment
VA). ... 11 System Ref~rence l"lanua!
~rivilegeQ Regist~rs
CON~OLE

9.4.1

and ~onsole

Corp.,l"layn~rd,Mass.

Page ~ -11

4-Aug-'j 6 .,. . . Rev 4

lERMlhAL RiGi~TERS
VAX-11/{60 Corisole Register Implementation

RXDB
j

2 2
4 ~

1 1
6 5

1 1
2 1

b '(

Used by
DL~11

Select

D?ta
F'ield

Field

lXDS
2 2
1+ 3

DO NuT COpy

COMPAN'X CONF'lDENTIAL

1 1

6 5

2 1

b 7

I
Select

Field

Data
Field

Copyright(c) 1979 Digital Equipment Corp.,Maynard,M&ss.
DO NOT COpy
VAX-11 System heference Nanual
(;CJMPANY CONFIDENTlAL
Privileged Registers and Console
4-Aug-78 -- hev 4
Page 9-12
CONSOLE TERM1NAL REGlSTERS
Select Field Values (in Hex)
Select Code

Data Field Values

Device

0 thru TF'

Drive 0 (Data)

0 thru FF - Binary Data
(.~tatus)

Function Complete
9

- ASCil Data

Operator's lerminal

0 = Re8.d Sector
1 = Write Sector
2 = Read Status

Drive 0 (Command)

= write Deleted Data
~ector

4 = Cancel Function

5
F

tV1i sc. (;ommunica tion

= Protocol .t!:rror

1 = Software Done
2 = Boot CPU

3 = Clear warm-start flag
= Clear Cold-start flag

Code 5 (Protocol Error), is sent
following occurs:

the

console

when

one

the

Another load device command (except for Cancel Function)
issued by the US before a previous command is completed.

The console gets a 'Drive 0 (DATA)' when expecting a command.

9.4.1.1 Status Byte Definition - The Status Byte is used by VM~ to
determine the success .or failure of a Read or Write operation. The
Status Byte is sent to the OS at the completion of a Read, Write, or
Read Status operation. The Select code is always 'Function Complete'
(code 2). The Status Bit assignments are as follows:

Copyright(c) 1979 Digital Equipment Corp. ,Maynard,t'lass.
DO NOT COpy
VAX-11 System Reference Manual
COlvifANY CONf'lDENTIAL
Privileged Registers and Console
4-Aug·78 -~ Rev 4
Page 9-1~

CQNSOLE TERMINAL REGISTERS

RXDa
2 2
4 3

1 1
2 1

1 1

8 '7 6

210

+----------~-+~-----------+------------+-----+-+-+---+-+-+-+
I
I

MBZ

I
I
I
I

I
I
I
,

+------------+--~------~.-+--~--------~+-----+-+-+-.-+-+-+-+
I

I CRC ERR

CODE '2'
-- ...... - .......... - ......I

,-------I

....

PARITY ERROR

............ -...
INl DONE
I

--~-

...........

I
1------,..,.--

DELeTED DATA

,-- ......... --_ .. -.,-_ ....
: ERROR
,,..... ..
~.--

The Status Bit assignments are identical to those supplied by the
Floppy controller, e~cepting bit 7. Bit 7 corresponds to Bit 15 of
the Floppy's 'RXeS' Register.

9.5

CLOCK REGISTERS

The clocks consist of an optional time of year clock and a mandatory
interval clock.
The time of year clock is used to measure the
dUration of power failures and is only required for unattended restart
after a power failure. The interval clock is used for accounting, for
time dependent events, and to maintain the software date and time.

9.5.1

Time-of-Year Clock (optional)

The time-of-year clock consists of one longword register.
The
register forms an unsigned 32-bit binary counter that is driven by a
precision clock source with at least .0025' accuracy (approximately 65
seconds per month).
The counter has a battery back-up power suppl.y
sufficient for at least 100 hours of operation, and the clock does not
gain or lose any ticks during transition to or from stand-by power.
The battery is recharged automatically. The least significant bit of
the counter represents a resolution of 10 milliseconds. Thus, the
counter cycles to_O after approximately 497 days.
If the battery has failed, so that time is not accurate, then the
register is cleared upon powE:r up. it then starts counting from O.
Thus, if software initializes this clock to a value corresponding to a

Copyright(c) 1979 Digital Equipment Corp.,t-'laynard,Nass.
DO NOT COPY
VAX-11 ~ystem Reference lVlanual
COMPANY CONFIDENTIAL
Privileged Registers and Console
4-Aug-7H -- Rev 4
Page 9-14
CLO(.;K Rt:G1STERS
large time (e.g., a month), it can chec~ for loss of time after a
power restore by checking the clock value.
j

+-----~~~-----~-----~-~~-~~~~-~--~-~---~~----~~~-----~-~~-~-~---+

time of year since setting
~read/write)

Time of Year (tODR)
lf the clock is not installed, then the clock always reads
and ignores writes.

9.5.2

~nterval

out

Clock

The interval clock provides an interrupt at IPL 24 at programmed
intervals.
The counter is incr6mented at , microsecond intervals,
The clock
with at least .01~ accuracy tB.64 seconds per day).
interface consists of three registers in the privileged register
space:
j

interval count
+----~~------~~--~-~--~---~----~~-~~----~-~~---~----~----------~+

(read only)
interval count register tlCR)

o
+--~--~-----~-~-----~------~-~----~-~~-~-----~~--~----------~~--+

next interval count

+~-------~~--------~--~~-~----------~--~~--------~-~-- ----------+

(write only)
next interval (NICR)

b " 6 5 4 3

1 0

+-+---------------------~-----------------------+-+-+-+-+-----+-+
:l:~,s:xl

tv.iBZ

Ih:

INIEIGIFI HBZ :UI

IT I IL Ihl

IN I

+-+-~-------------------------------------------+-+-+-+-+-----+-+
~J
wRWW
R

CwO 0
Interval Clock Control/Status (leCS)

Copyright(c) 1979 Digital l!;quipment Corp. ,l"laynard,Mass. . DO NUT CUpy
VAX-11 System Reference Manual
COl~lPANY CONFIDENTIAL
Privileged Registers and Console
4-Aug-78 -- Rev 4
Page 9-15
CLOCK REGISTERS
1•

i.nterval Count
The intervc;:.l register is a read only
register
incremented
once
every microsecond.
It is
automatically loaded from WIeR upon a carry out from bit 31
(overflow) which also interrupts at IPL 24 if the interrupt
is enabled.

Next Interval Count - The reloaa register is a write only
register that holds the value to be loaded into IGft when it
overflows. The value is retained when leR is loaded.
NICR
is capable of being loaded regardless of the current values
of lCR and lCCS.
The Ices register
Interval Clock Control status (ICGS)
contains control and status information for the interval
clock.

RUN

<0>

When set, lCB increments each microsecond. when clear,
lCB does not increment automatically. At bootstrap
time, run is cleared.

XFR

<4>

A write only bit.

Bach time this bit is set,

NICR

If RUN is clear, each time this
is set, lCH is incremented by one.

bit

transferred to IGR.
SGL

<5>

A write only bit.

<6>

When set, an interrupt request at IPL 24 is generated
every time leR overflows (I~T is set). When clear, no
interrupt is requested. Similarly, if INT is already
set and the software sets IE, an interrupt is generated
(i.e., an interrupt is generated whenever the function
{IE AND INT} changes from 0 to 1).

INT

<7>

Set by hardware every time IGR overflows. If IE is set
then an interrupt is also generated. An attempt to set
this bit via MTPR clears INT, thereby reenabling the
clock tick interrupt (if l~ is set).

ERR

<31>

Whenever IGR overflows, if I~T is already set, then ERR
is set.
thus, ERR indicates a missed clock tick. An
attempt to set this bit via MTfrl clears ERR.

Thus, to setup the interval clock, load the negative of the desired
interval into NICR. Then a MTPR #AX51,~ICCS will enable interrupts,
reload lCRwith the NICR interval and set run. Every "interval count"
microseconds will cause INT to be set and an interrupt to be
requested. The interrupt routine should execute a MTPH #AXC1 ,IICCS to
clear the interrupt. If iNT has not been clearea (i.e., the interrupt
has not been handled) by the time of the next lCR overflow, the ERR
bit will be set.

Copyright(c) 19'''''9 Digital Equipment Corp. ,l"iaynard,ivlass.
DO t-.OT COpy
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CLOCK REGISTBRS
At bootstrap time, bits <6> and <0> of ICCS are cleared.
ICeS and the contents of NICH and rCH are U~PHEDleTABLE.

9.6

The rest

VAX-11/780 ACCELERATOR

The VAX-11/780 processor has an optional accelerator for a subset of
the instructions.
Two internal registers control the accelerator,
ACC~ and ACCrl.

Aces is the accelerator control and status register.
It indicates
whether an accelerator eXists, controls whether it is enabled,
identifies its type and reports errors and status. At bootstrap time,
the type and enable are set; the errors are cleared.

332 2 2 2

111

1 0 9. 8 '"{ 6

6 5 II

+-+-+-+-+-+---------------------+-+-------------+---------------+
IE IIvll u 10 IR I
IRIBINIV!SI
IRIZIFIFIVI

MBZ

TYPE

tviBZ

+-+-+-+-+~+---------------------+-+-------------+----- ----------+
R RRR
R
flO
o 000
W

Accelerator Control/Status (ACCS)

TYPE <7:0>

Read only field specifying
follows:

the

accelerator

type

o = No Accelerator

1 = ¥loating point accelerator

Numbers in the range 2 through 127 are reserved to
Numbers in the range 128 through 255 are
reserved to CSS/customers.

DIGITAL.
ENB

<15>

Read/write field specifying whether the accelerator is
enabled.
At bootstrap time, this is set if the
accelerator is installed and functioning. An attempt
to set this if no accelerator is installed is ignored.

RSV

<27>

Read only bit specifying that the last operation had a
reserved operand.

OVti'

<28>

Read only bit specifying that the last
an overflow.

operation

had

UNft'

<29>

Read only bit specifying that the last
an underflow ..

operation

had

ERR

<31>

·Head only bit specifying that at least one of bits
RSV, OVf<', and UNF is set. Note that bits <31:27> are

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
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4-Aug-78 -- Rev 4
Page 9-17
VAX-11/780 ACCELERATOR
normally cleared by the main processor
before starting the next macro instruction.

microcode

ACCR is the accelerator maintenance register.
It controls the
accelerator's microprogram counter.
At bootstrap time its contents
are UNPREDICTABLE.
3 3
1 0

IE I

2 2
4 3

1 1 1 1
6 5 4 3

I E INI
IMIPI
ILIMI

NICRO PC

MBZ

IT'

I TRAP ADDRESS

ILl

9 8

Accelerator Maintenance Register (ACCR)
PC

<0:8>

NEXT MICRO PC on read. This contains the
address to be executed.

micro

MICRO PC on write. If EML is also
this updates the micro PC match register.

set,

then

~~TCH

MPM

(14)

MICRO PC MATCH. A read only bit that is set whenever
the accelerator's micro PC matches the micro PC match
register. This is useful primarily as a scope sync
signal.

ENL

<15>

ENABLE MICRO PC ~~TCH LOAD. A write only
when
set
causes
<8:0) to be loaded
accelerator's micro PC match register.

bit that
into the

TRAP <16:23> TRAP ADDRESS. A read/write field used by the main
processor to force the accelerator to a specified
micro location.

ETL

<31>

ENABLE TRAP ADDRESS LOAD. A write only bit that when
set oauses <23:16> to be loaded into the accelerator's
trap address register.
Subsequently,
the
main
processor's micro code can force the accelerator to
trap to this location by asserting an internal signal.

Copyright (c) 1979 £Jigi tal hquipment Corp. ,11aynard ,t-'Jass.
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Privileged Registers and Console
~-Aug-78 -- Rev 4
Page 9-1rl
VAX-11/7bO MICRO CONTRUL STORE
9. r(

VAA-ll 17 &0 M1CftO COl'4TROL STORK

The VAX-ll/7dO processor has three registers for control/status of its
microcode.
lwo are usee for writing into any writable control store
(~CS) and one is used to control micro breakpoints.
3

+-----~~-------~----------------+-+~~-+--~--------~--~ ----------+

Ii? I
I
IIICTRI

WCS ADDR

IN I
+--------------------~-~--------+-+---+----~-----.-----~---~-~~-+

R RW
W

~ritable

Control Store Address (~CSA)

wCS Data
+-----------------------------------------.----------- ----~---~-+

(on write)
3

o
+-----------------------------------------------+---------------+
1

8 7

PRESENT

+-----------------~--~~---~~----~---------------+----- ----------+

(on read)
writable Control Store Data

(wCSD)

Reading wCSD indicates ~hich control store addresses are writable. If
WCSD<n> is set, then addresses n*102~ through n*1024+1023 are writC;'ible
(i.e., that \ttCSA<12:10> f:.I.../LU n corresponds to writable control store),
n=4 corresponds to wCS that is reserved to DIGITAL for diagnostics and
engineering change orders.
Other fields correspond to blocks of
control that can be used to implement customer or CSS specif~c
microcode. Each wore of control store contains 90 bits plus 3 parity
bits.
To write one or more words, initializeWCS ADDR to the address
and eTR to O. Then each MTPrl to ~CSD will write the next 32 bits and
automatically
increment eTR.
When C'l'R would become 3, it is
automatically cleared and wCS ADDR is incremented.
If PIN is set,
then any writes to WCSD are done with inverted parity. An attempt to
execute a microword with bad parity results in a machine check.
At
bootstrap time, the contents of ~CSA are UNPREDICTABLE.

Copyright(c) 1 '/79 Digital t;quipment Corp. , tvla ynard ,Mass.
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Page 9-19
VAX-11/780 MICRO CONTROL ~TORE

1 1

3 2

+---------------------~---------------+--------------- ----------+
I'HeRO PC
NBZ

(read/write)
Micro Program breakpoint Address (MBRK)
whenever the microprogram PC matches the contents of MBRK, an external
signal is asserted.
If the console has enabled stop on microoreak,
then the processor clock is stopped when this signal is asserted.
if
the console has not enabled microbreak, then this signal is available
as a diagnostic scope point. Many diagnostics use the NOP instruction
to trigger this method of giving a scope point. At bootstrap time,
the contents of MBRK are LNPREDICTAbLE.

Y.o CONSOLE FUNCTIO~S
CPU consoles by nature are very implementation specific. However, the
specification and interaction of oertain console functions are defined
architecturally for consistency across VAX-11 series members. Also, a
minimum console functionality is defined.
Console functions may be split into three broad areas:
system
operator
interaction including communication with the operating
system; control functions, such as START and HALT;
and maintenance
functions such as examine, deposit.
The control functions are
generally used for both system operation and maintenance. Although it
is recognized that sophisticated programmers may use the maintenance
features for software debugging, this is not a constraint on the
console implementations.
Consoles may have write access to machine
registers and other hardware facilities not accessiblethrough the
instruction set even in Kernel mode.
It may be possible for the
console to leave the machine in an inconsistent state. In this case
machine behavior is UNDBFlNED.

Y.~.1

Operator Interaction

A set of four registers is reserved in the privileged register space
for a DL-11-like interface to a terminal. If the system implements a
console with a terminal, this interface will be implemented and
communicate with the console terminal. Other uses of the terminal,
for example as a system operator's console, are optional.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
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4-Aug-18 -- Rev 4
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CONSOLE FUNCTIO~S

9.8.2

Control Funotions

9.8.2.1 Halts - There are essentially three types of CPU halts:
error halts, console requested halts (i.e., a console HALT function)
and a halt as the result of a hALT instruction being executed. A CPU
halt is defined as stopping any further instruction execution and
entering a state that will recognize and service any console requested
functions, or execute an auto-boot sequence.
1.

Error halts - An error halt may occur at any stage of
instruction
execution
as
a
result of certain error
conditions, for example interrupt stack not valid.
'The CPU
will set the appropriate bit in the CPU error register and
enter the console service state. On a best efforts basis,
error halts do not alter the value of the PSL, the ISP, or
the PC. Following an error halt the PC is left pointing to
either the opcode of the instruction that caused the error,
or, if between instruction execution (e.g., responding to an
interrupt), to the next executable instruction.

Console requested halts - The CPU halts at the beginning of
the next instruction following the halt request, but does not
execute any of that instruction. The PC is pointing to that
instruction.
It is also possible that an exception or
interrupt occureq at the same time as the halt request.
If
this is the case then the PC will point to the first
in:struction of the service routine. Note that instructions
that e~ecute indefinitely are interruptible during execution.
Thus, the regular clock interrupts ensure that a console halt
request will b~ honored except possibly for problems handling
urgent interrupts.

HALT instruction execution - The HALT instruction executes by
invoking a halt request similar to that caused by the
console. The PC is left pointing to the next instruction.

9.0.2.2 Continue - If the CPU is running, a continue function has no
effect.
If the CPu is halted at the beginning of an instruction,
continue resumes execution with the instruction currently pointed to
by the PC.
The instruction buffer, if implemented, will be flushed
before execution is resumed.

A continue following an error halt without an intervening initialize
results in UNDE¥I~ED operation. On the VAX-1111bO, this is another
halt.

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CONSOLE FUNCTIONS
9.~.2.3

Initialize - A console initialize function initializes the
processor to the state defined in section 9.9, bootstrapping, except
that all general registers (hO through R13, SP, and the PC) are not
intialized.

9.8.2.4 Start - A start sequence consists of an initialize function
followed by loading the PC, followed by a continue. Implementations
that do not provide a mechanism to load the PC will set the PC to a
constant value as a result of the initialize function. The specific
machine documentation includes this value.

9.8.3

Naintenance i··unctions

Naintenance functions include features such as examine and deposit,
single
micro cycle, etc.
Hany of those functions are highly
require
implementation
dependent.
however,
certain
areas
architectural specification.

9.8.3.1

Examine And Deposit -

Functions that do not explicitly alter the programmer visible
state (e.~., examine or deposit) will not change any of the
programmer visible state other than, in the case of deposit,
the location explicitly referenced and its map entry.

Error conditions, such as non-existent memory, that would
normally cause an abort or fault, will be inhibited during
console service memory cycles (i.e., examine and deposit),
and no error status bits set in the CPU error register. The
CPU will, however, have a mechanism to inform the console
that the error has occurred. Any status from an error halt
may be lost.

Console virtual memory accesses have the privilege of the
PSL's current access mode and will occur in the current
process's virtual address space. A virtual memory deposit
will cause the modify bit in the page table entry to be set.

9.~.3.2 Single Instruction - A "single instruction" function
is not
defined architecturally.
H9wever, clearing the console halt request
along with setting a flag which will cause the console request to be
asserted at the next "beginning of instruction" effectively yields a
"single instruction" functionality.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference i"lanual
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Page 9-22
CONSOLE FUNCTIO~S
9.b.4

Minimum Console

All VAX-11 series members have a mechanism to implement at
following console functions:

least

the

In addition a means for indicating that the CPU is running (i.e.,
halted) and a "power on" indication will be provided.

not

9.9

Bal t

Continue

lnitialize

SYS1EM BOOTSTRAPPING

At bootstrap time the machine is initialized as follows:

fiO through R13
PC

boot parameters
boot code

PSL
translation buffer
cache
instruction buffer

041FOOOO (hex)
UNPREDICTABLE
empty or valid
empty or valid

KSP,ESP,SSP,USP,ISP
POBR, POLR, P 1bR, P 1LR
SER,SLR
PCBB,SCbb
IPL
ASTLV

UNPREDICTABLE

SISft

ICeS
NICR,ICR
TODR
RXCS
nADb
TXCS
MAPEN
PMR
SID
ACCS
ACCR
WCSA
WCSD
SBIxx
t'iBRK

UNPh~DICTABLE

UNPRt.vICTABLE
UNPREDICTABLE
114' (hex)
4

UNPREDICTABLE except <6>'<0> clear
UNPREDICTAbLE
time since set or since power up

UNPHEDICTABLE
tiO (hex)

System identification
o if no accelerator;
d001 (hex) if floating point accelerator
UNPREDICTABLE
UNPfiEDICTABLE
writable blocks
\1'BS\
UN~Rt;DICTABLe

As part of the primary (ROM), bootstrap, certain general registers are
set up to specify the bootstrap device. lhese registers pass the

t-"~nual

COMPANY

Privileged Registers and Console
SYSTeM BOOT~TrlA~fI~G

DO NOT COPY

COl~r'lDENl'IAL

4-Aug-7b -- Rev 4

Page 9-23

If a
further ( so ft ware) bootstraps.
applicable, 0 is specified. The boot

bootstrap information to any
register specified is not
register parameters are:
3

4 3

I DVT):P I

MEZ

: HO

+----------~~~----~------~--~--~~-~---~---~-------------+--~----+

VVIYf identifies the device type as follows:

o - disk pack
1 - cartridge disk
4 - magnetic tape
5 - DECtape
8 - paper tape
12 - Synchronous Communications Line
14 - Asyncnronous Communications Line
All other values are reserved to D1GITAL.
reservation. **** \

\ **** Need CSS device

4 3
SBA

MEZ

:R1

+--~----------~~--~--~~---~.-------~----------~~~----- --+-------+
SBA is an implementation dependent system bus address.
SBA is the NEXUS on the S81.

VAX-11/7tiO

for a ~NiBUS bootstrap device,
j

1 1

d 7

320

:----------------~------~---+-----~----~------------------+-----+
NBZ
UBA
I MBZ:

+---------------------------+-----------------------------+-----+
3
1

+-----------------------------~~---~---~~~---~~~~~---- ----------+

+---------------------------------------------------------------+
UBA is UNIBUS address bits <17:3>.

: R2

:R3

Copyright(c) 1979 Digital Equipment Corp.,1Vlaynard,Mass.
DO NOT COpy
VAX-11 System Reference 1"Janual
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Privileged Registers and Console
4-Aug-78 -- Rev 4
~age 9-24
SYSTEM BOOTSTRAPPING

for a NASSBUS .bootstrap device,
~
1

4 3

:R2

MBZ

4 3

o
:R3

CA is the formatter number.

UA is the unit number.

For all devices,
3

+-.--~.--------------.---------~---------------------- ----------+

:H4

BA is the block address on the device.
The content:;; of registers R5 through R13 are UNPREDICTABLE.

9.10

SYSTEM RESTART

After restoration of power or optionally after the processor halts,
system operation is resumed by initializing the processor, locating
the lowest addressed memory, and starting at the address specified in
the longword at this lowest address plus 4. Software depends upon the
content of the three longwords at lowest address, lowest address plus
4 ~nd lowest address plus 8, and also that the memory configuration
does not change from system interruption to restart.
(~nd

of Chapter 9)

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

VAX-11 PDP-11 Compatibility Mode

Specification Status:

Fully approved

Architectural Status:

under ECO control

File:

SR10R4.R~O

PDIlIl II:

not' used

Date:

28-Feb-77

Page 1

Rev 4

Superseded Specs:
Author:

Cutler

Typist:

Bess

Reviewer(s):

Abstract:

P. Conklin,

D. Cutler,

P. Lipman,
B. Strecker

D. Rodgers,

D. Hustvedt,
S. Rothman,

J. Leonard,
B. Stewart,

Chapter 10 describes the Compatibility Mode that
is
provided in the VAX architecture to allow a certain subset
of PDP-11 programs to be directly executed on VAX machines.
VAX com~atibility mode hardware, in conjunction with a
compatibility mode software executive, can emulate the
environment provided to user programs on a PDP-11.

Revision History~
Rev If
Rev 1
Rev 2
Rev 3
Rev 4

Description
Distributed
ECO 3
April /.Vleeting
Typos

Author
Rothman
Rothman
Cl,ltler
Cutler

Revised Date
25-Sep-75
1-Jan-76
3-Jun-76
26-1i'eb-77

PDP-11 Compatibility Mode
Change History

2U-~eb-77

Page 10-990

-- Hev 4

Rev 3 to Rev 4:
1.

Typos

Rev 2 to Rev 3:
The chapter has been extensively modified due to the restartibility of
instructions and the new memory management architecture. Virtually
all sections were affected. The following are major revisions:
1.

The PDP-11 environment exclusion list was expanded to include
more features that are not supported by compatibility mode
hardware.

iltlF'/TP (riD) were moved to the list 0 f supported

They execute exactly
ignore previous mode.
j.

push

and

instructions.
pop instructions and

Compatibility mode can now be entered only via an HEl
instruction since the process structure has been deleted trom
the architecture. The number of privileged bits in P,sL has
been reduced due to the restartibility of' instructions.

4. Compatibility mode programs directly m
;;TTY12: - PLEAS~ tAKE NOTE OF NOTICE.TXT.
ap into the first 64k
bytes of the per process part of the address space without
any special address manipulations.
5.

Exceptions now push information on the kernel stack
is no longer present in the architecture.

and

ISL

the new memory martagement architecture obviated the need
the MCMA instruction.

for

Rev 1 to Rev 2:
1.

The chapter has been extensively rewritten. lncluded now are
complete definitions of the interfaces to VAX native mode,
inclUding memory management and exceptions. A set of notes
has also temporarily been added at the end of the chapter
that answers some common questions, describes open issues,
and
explains
rejected
alternatives
to
some of the
compatibility mode specifications. The other items in this
list are only the changes to revision 1 of this chapter, not
the additions.

HTl and HiT no longer perform the same operations in
compatibility mode. They are now exactly equivalent to their
PDP-11 counterparts.

The comment about floating point simulation has been changed
since the VAX mode ~loating point instructions have changed.

PDP-11 Compatibility Mode
Chanseti1story

28-~"eb-11

-- Rev 4

Page 10-991

The I'k>ve Compatibility Mode Address instruction has been
chanled to make it completely general with respect to
restriction level.

[End of SR10R4.RNO]

Copyright(c) 19'19 Digital t;quipment Corp. ,1"laynard,l"lass.
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COtvlPANY CONfIDENTIAL

CRAPTER 10
PDP-11 COMPATIBILITi MODE

28-F'eb-71

Rev 4

Compatibility Mode is provided in the VAX architecture to allow a
certain sUDset of PDP-11 programs to be directly executed on VAX
machines. VAX compatibility mode hardware, in conjunction with a
compatibility mode software executive (which runs in VAX mode),· can
emulate the environment provided to user programs on a PDP-11.
This
environment excludes ·from a complete PDP-11 the normal operation of
the following features:
1.

Privileged instructions such as hALl' and RESET.

Special instructions such as traps and WAIT.

Access to internal processor registers (e.g., PSW and console
switch register).

Direct access to trap and interrupt vectors.

Direct access to 1/0 devices. (Compatibility mode programs
can directly reference I/O devices if and only if proper
mapping has been established by VAX mode software.)

Interrupt servicing.

Stack overflow protection.

Alternate general register sets.

Any processor mode other than user
Supervisor modes are not supported).

10.

Floating point instructions.

(i.e.,

Kernel

and

This chapter is split in two parts.
The first part is a brief
description
of
the
PDP-11
environment
provided by the VAX
compatibility mode hardware.
Details of the operation of PDP-11
compatible operations can be found in the appropriate PDP-11 handbook.
The second part describes the hardware mechanisms provided in the VAX
architecture which enable the implementation of various compatibility

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DO NOT COPY
Nanual
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PDP ... 11 Compatibility l'1ode
28-fi'eb .... '77 -- Rev 4
Page 10-2

VAX ... ' 1 Syetem Reference

mode exeoutives.

10.1

COMPA1'151Lll'Y MOlJE US~R

10.1.1

Gener~l Hegi~ters

t;NV1R0i'4MENT

And Address Modes

All cf the PDP·'1 general regieters and addressing modes are provided
in compatibility mode. Side effects caused by a destination address
calculation have nQ effect on source values, and auto-increment modes
in JMP and J~R dQ not affect the new PC. All addresses are 16 bits
wiqe.

1Q.1.2

The Stack

General register a6 is used as the stack pointer by
certain
instructions, as in the PDP-1'.
It is not,however, used by the
hardware for any exoeptions or interrupts. There is also no stack
overflow protection in compatibility mode.
See Sections 10.5 and

10.7.

10.1.3

Processor Status Word

A subset Qf the f~ll PDP-11 Processor Status Word is available
compatibility mode. the format of the oompatibility mode PSW is:

5 4 321 0

IT:NIZIVIC!

The PS·W can only be affected by the cond i tion code instructions, RT1,
and HTT. when an RTl or HTT instruotion is executed, bits 15 through
5 in the saved PSW on th~ s~aok are ignored.

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28-Feb-11 -- Rev 4
Page 10-3
COMPATIBILlTY MODE USER ENVIRONNENT
10.1.4

Instructions

The following' instructions are
hardware.

provided

the

compatibility

mode

TABLE 1
Compatibility Mode Instructions
Opcode
(octal)

Mnemonic

000002
RTI
000006
HTT
00010D
JMP
00020R
HTS
000240-000277
Condition codes
0003DD
SwAB
Branches
000400-003777
Branches
100000-103777
004RDO
JSR
.050DD
CLR(B)
COM(S)
.0510D
INC (B)
.052DD
DEC(B)
.053DO
NEG(B)
.054DD
ADC(B)
.055DD
.056DD
SBC(B)
TST(B)
.0570D
.060DD
ROR(S)
.061DO
ROL(B)
.062DD
ASR(B)
.063DD
ASLCb)
0065SS
MFPl*
0066DD
tvlTPI*
10653S
MFPD*
1066DD
MTPD*
006'7DO
SXT
070RSS
MUL
071RSS
DIV
072RSS
ASH
ASHe
073RSS
074RSS
XOR
SOB
077RNN
.1SS0D
MOV(S)
.2SSDD
CMP(B)
.3SSDD
BIT (B)
.4SSDD
BIC(B)
.5SSDD
SIS (B)
06sSDD
ADD
16SSDD
SUB
* These instructions execute exactly as they would on a PDP-11 in user
mode with In$truction and Data space overmapped.
More specifically,
they ignore the previous access level and act like PUSH and POP
instructions referencing the current stack.

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PDP-11 Compatibility Mode
28-Feb-77 -- Rev 4
Page 10-4
COMPATIBILITY MODE USER E~VIRONMENT
The following trap instructions cause the machine to enter VAX mode,
where either the complete trap may be serviced, or where just the
instruction may be simulated. See Section 10.5.
TABLE 2
Compatibility Mode Trap Instructions
Opcode
(octal)

l"lnemonic

000003
000004
104000-104377
104400-104777

BPT
lOT
~MT

TRAP

The following instructions and a:Ll other opcodes not defined above are
considere;d reserved instructions in compatibility mode, and trap to
VAX mode. See ~ection 10.5.
TABLt. 3
Compatibility Node Reserved Instructions

~ote

Opcode
(octal)

l"!llemonic

000000
000001
000005
00023N
0064NN
0'7500R
07501R
O,"(502R
or(503R
17).XXX

hALT
\,.AIT
RESET
~PL

l"lAhK

fADD--FIS
r'SUB--FIS

FMUL--F'lS
r'DIV--FIS

fP11 Floating Point

that no floating point instructions are included in compatibility

mode.

10.2

BNTERl~G A~D

Lt.AVING COMPATIBILITY MODE

Compatibility mode is entered by executing an REI instruction with the
compatibility mode bit set in the image of the PSL on the staok.
Other bits in the PSL have the following effects:

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fiDP-11 Compati bil i ty l-'iode
28-Fe b-77 -- Rev 4
}Jage 10-5
ENTERING AND LEAVING COMPATIBILITY MOD£

bits

Ef fect

NL'.VC
T
DV

Condition Codes
T bit
Reserved operand fault if not zero
Reserved operand fault if not zero
Reserved operand fault if not zero
Reserved operand fault if not zero
Reserved operand fault if not 3
Reserved operand fault if not 3
Reserved operand fault if not zero
Reserved operand fault if not zero
T pending bit. See Section 10.6 for a
complete description of how T bit traps
work in compatibility mode.

r'lJ

IV
IPL

PRY HOD
CUR MuD
IS
ft"'PD

VAX mode is re-entered from compatibility mode by the compatibility
mode program causing an exception, or by an interrupt. The PSL pushed
on the kernel or interrupt stack when leaving compatibility mode· has
all the bits that cause reserved operand faults in the above table set
to the appropriate state.
Note that when an RTI or fiTT instruction is executed in compatibility
mode, the 11 high bits of the PS~ are ignored, but when the PSW is
restored as part of the PSL when going from VAX to compatibility mode,
those bits must be zero, or a reserved operand fault occurs.

10.2.1

General Hegister Usage

Compatibility mode registers RO through R6 are bits 15 through 0 of
VAX general registers RO through R6, respectively. Compatibility mode
register R7 (PC) is bits 15 through 0 of VAX general register R15
(PC).
VAX registers R8 through R14 (SP) are not affected by
compatibility mode. when entering compatibility mode, VAX register R7
and the upper halves of registers HO through R6 and R15 are ignored.
when an exception or interrupt occurs from compatibility mode, VAX
register R7 is UNPREDICTABLE and the upper halves of RO through R6 and
the stacked R15 (fC) are zero. Since there are no FP11 floating point
instructions
in
compatibility
mode,
there
are
no floating
accumulators.

10.3

COllI}PATlblLITY MODE hEt-lORY MANAGEl'1ENT

PDP-11 addresses are 16 bit byte addresses, hence compatibility mode
programs are confined to execute in the first 64k bytes of the per
process part of the virtual address space.
There is a one-to-one
correspondence between a compatibility mode virtual address and its
VAX counterpart (e.g., virtual address 0 references the same location
in both modes).
A compatibility mode address is interpreted as

Copyright(c) 1979 Digital Equipment Corp. ,Naynard,Mass.
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COtvlPANY CONFIDENTIAL
PDP-11 Compatibility Mode
28-F'eb-77 ... - Rev 4
Page 10-6
COMPATIBILITY MODE MEMORY 1"1ANAGEMENT
follows:
31

9 8

16 15

PAGE

DISPLACEMENT

The PDP-11 capability of providing different access protection to
different segments is automatically provided since protection is
~peoified at the page level in the VAX architecture (i.e.,
VAX pages
are smaller than PDP-11 segments).
The memory management system protects and relocates compatibility mode
addresses in the normal manner. Thus, all of the memory management
mechanisms available in VAX mode are available to the compatibility
mode executive for managing both the virtual and physical memory of
compatibility mode programs. All of the exception conditions which
can be caused by memory management in VAX mode can also occur when
relocating a compatibility mode address. See Chapter 5.
Host of the features of the KT11-D affecting the user environment can
be simulated with the VAX memory management system. The following
table provides a general description of how this can be done;
reference Chapter 5 of this manual and the appropriate PDP-11
documents for details of each system.

Copyright(c) 1979 Digital Equipment Corp.,~aynard,Mass.
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COMPANY CONFIDENTIAL
PDP-11 Compatibility Mode
28-Feb-77 -- Rev 4
Page 10-7
COMPATIBILITY MODE MEMORY MANAGEMENT

KTll-D
VAX
feature to be simulated simulation method
-~--~~--~--~~------~-----------------------~--

8 segments
per user.

8 segments can be simulated by dividing
the 128 pages of the compatibility mode
virtual address space into 8 logical groups
of 16 pages each having possibly different
protection.

Segment size from 64
to 8K bytes (1 to
128 blocks) in 64 byte
increments, using
contiguous memory.

Segment size from 512 to 8K bytes
(1 to 16 pages) in 512 byte (1 page)
increments, using discontiguous memory.

F'orward growing
segments
(Expand Direction.O).

Cap be simulated using page table entries
~pecifying no access for those pages that
are not allocated.

Backward growing
segments

Can be simulated using page table entries
specifying no access for those pages that
are not allocated.

(ED=1).

Segments begin o~ any
64 byte boundary.

Segments begin on any 512 byte boundary.

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VAX .... 11 System Hefer~nce Manual
Cul'-~PANY CONr'IDEN'l'lAL
PDP-11 Compatibility Mode
2b-Feb-77 -- Rev 4
Page 10-8
COI"lPATIBILITY HODE MEMURI t'1ANAGEMENT
What follows is an eX~lple of how a PDP-11 environment can be created
using the above concepts.
Segments 0, 1, and 2 of the PDP-11
environment are program segments; j is unused; 4 and 5 are stack;
and 6 and 7 are read-write data.

VAX .Page Table

11 ~nvironment
- ......... -- ..... -- ..... -Seg #
0

.. ..
~

-~-

.. -- ..... -- ..

Size
Expand
(bytes)Direction

Access

Page

Access

Up
Up
up

Read only
Read only
Read only
t.. one

0... 15

Read-~rite

Read only
Read only
Read only
~o Access
Read-Write
Read-write
Read- wr i te·

bK
~

256

4
5

1K
cit<.

Down
Oown

,Read-Write
Read-write
Read-Write

16-31
32

33-77
78-'l9
80-95

96-111
112-115 Read-~rite
116-1~7 No Access

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PDP-11 Compatibility Node
2o-Feb-77 -- Rev 4
Page 10-9
COMPA1IbILITY MUDE ~XCEPTIONS AND INTERRUPTS
10.4

COMPATIbILITY MODE EXCEPTIONS AND INT£RRUPTS

All interrupts and exception conditions which occur while the machine
is in compatibility mode cause the machine to enter VAX mode, and are
serviced as indicated in Chapter 6 (note that this includes backing up
instruction side effects if necessary).
The following exception
conditions are specific to compatibility mode. All these exceptions
create a three longword frame on the kernel stack containing. PSL, PC,
and one longword of trap specific information. Bits 15 through 0 of
this longword contain a code indicating the specific type of trap and
bits 31 through 16 are zero.

10.4.1

Reserved Instruction ~

etI'

'Y'CA-{A

\r~Lc;;..~

These are the opcodes that are defined~ in compatibility
code for the reserxed instruction t~ is O.

mode.

The

~"-0
10.4.2

BPT Instruction

The code for the BPT instruction is 1.

10.4.~

lOT Instruction

The code for the lOT instruction is 2.

10.4.4

t.:c 1T Instruction
J

The code for the group of EMT instructions is 3.

10.4.5

TRAP Instruction

The code for the group of TrlAP instructions is 4.

10.4.6

Illegal Instructions

Illegal instructions
instructions with a
instructions is 5.

in compatibility mode
register destination.

and
are
JMP
JSR
The code for illegal

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PDP-11 Compatibility Mode
28-F'eb-17 -- Rev 4
Page 10-10
COHPATIBILITY MODE EXCEPTIONS AND INTERRUPTS
10.4.7

Odd Address Error

¥,#'

~~(T1I \

An odd address error ~iS caused in compatibility mode whenever a
word reference is attempted on a byte boundary. References that use
the ~p or PC are always word references, even if used in a byte
instruction. The code for odd address errors is 6.

10.5

T BIT OPERATION IN COMPATIBILITY MODE
-

~"-;;2'''''P".-

\'i-;-

A compatibility mode S bit tra'p occurs at the .e·nd" of an instruction
when the Tf>bit is set-'iii' the psL.at the beginning of the instruction.
A. 't,-~...t.~,tr;al7;,,,,al.so_,-D,c,out~,s.•,..a,~,,,,,,tJ,ne""'end~'"'O'fw"an"'RT1:-"'''rn'st:ruetJ:r'Orl'; j:-fL:the,·--1':·, bolt"~

I'"

On 'f,,,,-b4.,,,t,,,,..·t,pa:J)s, a two long
word kernel stack frame is created, containing PSL and PC. IPL and IS
are zero and CM is one in the stacked PSL. Compatibility mode T bit
-t-P'a-p' uses the same vector as VAX mode T bit 1rrP-ap. See Chapter 6.
was..---&e.t.--i..n~&-,I?.S\i·~",12Q!2e-G·" ~p~m-",,-ttl$,·,,<s:taek.

-t,

\There ha.veoeen problems with the operation of the l' bit on PDP-11s.
TheT pending~6it in the PSL solves those problems. For that reason,
the operation of the T bit in compatibility mode is not identical to
that of PDP-11s.\
There are two ways to get the T bit
compatibility mode instruction:
1.

set

the

beginning

An RTT'instruction is executed in compatibility mode anfl the
bit·~ set in the PSW image on the stack. In this case,
the next instruction is executed (the one pointed to by the
PC on the stack), and al'--"bit '~'p is taken aftel t;h~t:'
instruction.
,',- ; ': i i '
h,,,e

An REI instruction is executed in VAX mode which has both the
T bit and CM bit set (and Tp'&A~~ng clear) in the saved PSL
image on th)t stp,Ok. Again, one instruction is executed, and
the T bit :.t~i{tis taken. (r~or a c.omplete description of the
interaction of REI, T bit, and T('pend-i-ng, see Chapter 6. The
operations that occur as a function of these conditions are
the same whether or not compatibility mode is being entered
from the REI.)

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28-~eb-77 -- Rev 4
Page 10-11
T BIT OPERATION IN COMPATIBILIT:Y 1'10DE
The T b~t interacts with other compatibility mode operations as
follows (for interaction with other than compatibility mode specific
operations, see Chapter 6.):
(~J

T bit

se~

instructio~ ~hich
'":, i",'. .......tr\, .. ,~

the beginning of any
does not t-Paf).
l J~., i 1

~.~ .

compatibility

mode

,,"'"

In this case;\ a T bit t.ciip. is taken ~'aJit.e.r. the' instruction.
The saved PSL has the T bit set and Tf~ clear.
The
compatibility mode executive ]»,1;11' do one of the following
things:
1.

If it services the t~ap directly, it may clear the T bit
in the saved PSL on the kernel stack i f i t no longer
wants to trace the program, or it may leave it set if it
wants to continue tracing the program. It exits with an
REI.

If it returns the trap to compatibility mode, it pushes a
(16 bit) PC and (16 bit) PSW with the T bit set~,on the Ct:'"
User stack to simulate the effect of the T bit ~PJa~.
lt
then clears the T bit in the saved PSL image on the
-kernel stack, and does an REI.
The compatibility mode
service routine then may clear the T bit in the PSW image
on its stack, as a function of whether or not it wants to
continue tracing~ The compatibility mode routine returns
with RT'1:. (rr-'tt'l-wys'·"e-};ea~a..Jt.h.!L,,!,,~i,~ . in the saved
P~w.",~._it","4~e,s,not",matter",if,i tr.e,t,UrJUt:wlth·~'·HTr·'()':t'. RTT .,)
,

T bit set at t~e beginning of an RTl or RTT.

,\'

;..

f ·

'':''·''~1.~-l

i~~~~,,·,after the . . instruction is
executed.
There are two different cases, depending on
whether or not the T bit was set in the image of the PSW
which was popped from the stack by the instruction:
A T bit t-raJ;'occurs

1•

T bit not set.

Neither TP nor T will be set in
kernel stack.
2.

the

PSL

the

This is the

same

T bit set.
'IP will not be set, and T will be set.
case as for nontrappir!J instructions.

saved

T bit setrat the beginning of any instruction which causes
compatibility mode tr~p
#?

The t..PaJ, condition is serviced first. TP is ,s'et in the saved
PSL pushed on the kernel stack. TA-ese..~-t.raps~,.may: .... be .. ,::te.c:v.i4ed
in --one'-erf'-'wa-ys :

fwo

{",

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.COMPAl'4Y CONli'IDENTIAL
PDP-11 Compatibility ~bde
2b-Feb-17 -- Rev 4
Page 10-12
T BIT OPERAtION IN COMPATIbILITY MODE
1.

compatibility mode executive
trap condition.

Th~

directly

services

the
j"

In this case ,when the compatibility mode executi y. e . is
done, it executes an REI. The l'P and CM bits in/the PSL
image on the st·ack will be set, so a compatibiJ:r£y mode l'
bi~ trap will immediately be taken.
2.

The compatibility mode executive r'.~:~t·u·~ns
the
trap
condition to a compatibility mode routine which services
the trap.
In this case, the compatibility 'mode executive will push
(16 bit) PC and (16' bit) PS~ on the user stack to
simulate the effect oft~e trap. Trie~PSW pushed by the
compatibility mode executive will h~ve the l' bit set,
because the TP bit was set in the saved 'PSL on the kernel
stack.
The compatibility mode executive ~ill then 61ear
the T and TPbits in the saved PSL and do an'R~I to the
compatibility
mode
service
routine.
'Wben
the
compatibility mode routine is done servicing the ~rap, it
will do an HTI, which will then cause the compatibility
mode T bit trap to occur.
.
a

10.6

UNIMPL~MENTED

PDP-11 TRAPS

There are several traps that occur in PDP-11s that are not implemented
in compatibility mode:
1.

There is no stack overflow trap. This is equivalent to the
User Mode of the KT11, where there is also no overflow
protection.
Stack overflow can
be
provided
by
the
compatibility mode executive using the memory management
mechanisms.

There is no concept of a double error trap in compatibility
mode, since the first error always puts the machine in VAX
mode.

All other trap conditions such
parity, and memory management
enter VAX mode.

as power failure, memory
traps cause the machine to

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DO NOT COPY
VAX-11 System Reference Manual
COMPANY CO~FIDE~TIAL
PDP-11 Compatibility Node
28-Feb-77 -- Rev 4
Page 10-13
COtvlPATlbILITY t'lUDE 1/0 Ht:r'ERENCES
10.7

COMPATIB1LITY MODE 1/u REFERENCES

Since 1/0 devices are accessible with all instructions in VAX mode (as
in
the
PDP-11), 1/u devices may be referenced directly from
compatibility mode, if the memory mapping is set up to allow it. This
may be done by mapping pages directly to 1/0 devices. Note that, in
general, 1/0 devices will NOT appear in the physical address space oh
VAX machines the same way they do on PDP-11s, so existing PDP-11
programs that directl~ reference 1/0 devices probably will not work.
In addition, compatibility mode programs can only do word or byte
references; many VAX 1/0 devices may require that some references be
32 bits wide.

10.ti

PROC~SSOH

REGISTERS

The only processor register available in compatibility mode is part of
the PS~, and it may only be referenced with the condition code
instructions, RTI, and RTT. Access to all other registers must be
done in VAl mode.

10.9

PhUGRAM SYNChRONIZATION

All PD~-11s guarantee that read-modify-write operations to 1/0 device
registers are interlocked; that is, the device can determine at the
time of the read that the same register will be written as the next
bus cycle. This synchronization also works in memory on most PDP-11s.
In compatibility mode, instructions that have modify destinations will
perform this synchronization for UNIBUS 1/0 device registers and never
for memory.

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28-Feb-77 -- hev 4
Page 10-14
tiOl'ES
10.10

NOTES

There are no references to specific PDP-11 implementations.
At some point, the PDP-11 "Table of Programming Differences"
should be updated to include VAX compatibility mode. No one
is committed to do this.

There have been proposals to make the upper four bits of the
compatibility mode PSW be ones, so that compatibility mode
programs appear to be running with the current mode and
previous mode as User. This does not make any sense; the
hardware never materializes the compatibility mode PSw, it
only uses an image of it for the RTI and RTT instructions.
That image is created by software; if it is desired to make
the upper four bits one, the software may do it.

It must be made clear that all compatibility mode processes
also have a VAX mode. There is nothing that prevents the VAX
mode of the process from being rather extensive;
the only
constraint is that the VAX part of the process be careful
about using virtual addresses 0 to FFFF(hex) since those are
used for mapping the compatibility mode addresses.

A proposal to ignore the PSL bits that cause an UNDEFlNED
operation was rejected. That would potentially add more cost
to the hardware, and it should not affect the software, since
the hardware always returns those bits as zero in the PSL
pushed on the exception stack when leaving compatibility
mode.

A proposal to simulate Kl' 11 registers MMRO and MlVlR 1 in
hardware has been rejected.
MMRO and MHR1 can easily be
simulated by software with the information available on
memory management faults and aborts (i.e., MNRO is the
address of the instruction causing the fault and ~1R1 is
always zero since all side effects "are backed up).

[End of Chapter 10]

Page 1

Digital Equipment Corporation COMPANY CONFIDENTlAL

Title:

VAX-11 Assembler Notation -- Rev 5

Specification Status:

Fully approved

Architectural Status:

under ECO control

File:

SRBR4.RNO

PDM if: not used
Date:

31-0ct-78

Superseded Specs:
Author:

Strecker

Typist:

Principe

Reviewer(s):

Abstract:

P.Conklin, D.Cl,ltler, D.Hustvedt, J.Leonard,
D.Rodgers, S.Rothman, B.Stewart, B.Strecker

P.Lipman,

Appendix B gives the assembler notation sufficient to
understand the examples in other sections of the System
Reference t1anual. lt also details the notation used to
. express addressing modes. It includes a full list of all
the notations which can be used in an operand and which
addressing mode each results in.

Revision History:
Rev II
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5

Description
Distributed
ECOs 1-11
ECOs 12-10 an9, April Meeting
Typos
Updates

Author
Strecker
Strecker
Conklin
Conklin
Bhandarkar

Revised Date
25-Sep-ri5
9-Mar-76
13-Jun-'l6
21-Mar-'(7
31-0ct-78

Assembler Notation
Change History

Page B-990

31-Uct-78 -- Rev 5

Rev 4 to Rev 5:
1.

LJpc.ate register mode for 128-bit operands

Rev j to Rev 1+:
1•

Typos

DO~n) ,

:J.

Default D is word, G is longword.

D(hn)lRx] generate register deferred if D::;:O.

Rev 2 to Rev 3:

Change uNDEFINED to UNPREDICTABLE

Add absolute addressing

Add 6-byte addressing

',.

Correct typos

Remove speci&l <•• > notation

Correct lypos

10.

Add assembler/linker
argument modes.

11.

Update to Chapter ~ Rev 4 Addressing Modes

12.

Change immediate to r prefix

1~.

Add ~rt notation

14.

Add assembler ban of (PC)

15.

@(rt)

Rev 1 to

checks

was missing

Rev 2:

1•

Remove R-R mode

introduce branch displacements

Add index mode

displacement;

local,

and

Assembler Notation

.;) 1-U C t - of ~ ... - Rev 5

Change History

Add summary

Add special notation

LEnd of ~RBR~.RNOj

!"age

B-991

Copyright{c) 1979 Digital Equipment Corp. ,tvlaynard,1"lass.
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C0MPANY CONFIDE~TIAL

APPENDlX B
ASSEMBLER NUTATION

j1-oct-~1'8

B.1

-- Rev 5

INTRODUCTIUN

The VAX-11 assembler provides, as a subset, a notation which is very
similar to the PDP-l1 assembler notation. The principal differences
are due to the fact that the VAX-11 architecture has new addressing
modes and has several length variations of modes for which the PDP-11
has only a single length. ii'or example, the .PDP-11 has displacement
~ddressing
with a single displacement size of 16 bits. VAX-l1 has
displacement addressing in various forms with displacements of 8, 16,
and 32 bits.
In general, the programmer need not be aware of the length variations
in VAX-11 addresssing modes.
The programmer simply writes the
addressing mode in a format identical to the analogous PDP-11
addressing mode, and the assembler will choose the shortest form of
addressing consistent with the state of symbol definition at assembly
time.
Occasionally, a programmer may wish to force a given length
addressing mode.
The VAX-l1 assembler includes a notation for
accomplishing this.
(Of course, if the programmer forces a length
which cannot be accommodated at assembly or link time, the assembler
or linker will generate an error indication.)

B.2
B.2.1

NOTATIG~

FOR GENERAL MODE ADDRESSING

The general notation is Rn. Since results are UNPREDICTABLE if R is
PC for operands taking a single register, or if' Rn is SP or PC for
operands taking a pair of registers, or if Rn is AP, FP, SP, or PC for
operands taking four registers, the assembler generates an error
indication.

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j1-0ct-78 -- Rev 5
Page B-2
NOTATION fuR GE~ERAL MODE ADDRESSING
8.2.2

The general notation is (Rn). Since results are UNPREDICTABLE
is PC, the assembler generates an error indication.

B.2.j

mode

see

Autoincrement Mode

The general notation is (Rn)+.

B.2.4

For immediate mode see B.2.b.

Autoincrement Deferred Mode

The general notation is @(Rn)+.

For

absolute

addressing

B.2.9.

B.2.5

Autodecrement Mode

The general notation is -(Rn). Since results are UNDEFINED if R is PC
the assembler generates an error indication.

B.2.6

Displacement Mode

The general notation is D(Rn).
10 force .a byte, word, or long
displacement, the notation is BAD(Rn), WAD(Rn), LAU(hn) respectively.
if a general address G is used, the assembler assembles this as D(PC)
where U = G
tupdated value of PC}. This latter form is termed
PC-relative addressing. If a form is forced which is shorter than the
actually needed displacement, the assembler or linker generates an
error indication.

B.2.7

Displacement Deferred Mode

The general notation is @D(Rn).
To force a byte, word, or long
displacement,
the
notation
is
@BAD{Rn),
@WAD(Hn),
@LAD(Rn)
respectively.
If a general address @G is used, the assembler
assembles this as @D(PC) where D = G - (updated value of PC). This
latter form is termed PC-relative deferred addressing. If a form is
forced which is shorter than the actually needed displacement, the
assembler or linker generates an error indication.

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31-0ct-78 -- Rev 5
Page B-j
NOTATION FOR GENERAL MODE ADDRESSING

B.2.8

Literal Mode

The general notation is #cons. This results in, depending on the
value of the cons, either immediate or literal mode. To force literal
mode, the notation is S"#cons. To force immediate mode, the notation
is 1"#cons.
If either literal or immediate mode is used on a modify
or write operand, the assembler generates an error indication.

Absolute Addressing Mode

8.2.9

To force a reference to an absolute address the notation
@#location. This is assembled as autoincrement deferred using PC.

B.2.10

General Addressing

;J"hen a reference to a symbOl wi,ll be either absolute or PC-relative,
but the choice is to be determined by the linker, the notation is
G"location. This is assembled as a five byte operapd.
The linker
chooses either @#location or L"D(PC) depending on whether the location
is absolute or PC~relative. This is used both for general external
references
and for general references between program sections
(PSECTs) .

B.2.11

Index Mode

The general notation is <base operand mode>[Rx] where <base operand
mode> is the notation for any of the addressing modes register
deferred,
autoincrement
(immediate),
autoincrement
deferred
(absolute), autodecrement, displacement (PC-relative), displacement
deferred (PC-relative deferred) or general addressing.
Since the
result is UNPREDICTABLE if a register in the base operand mode is the
same as the index register (except for PC), the assembler generates an
error.

b. j

GENERAL MODE ADDRESSING SUMt-1ARY
Symbolic

....,--- ... -- ...

Assembled Mode

---,..-- ...... -----

1•

(R)

(R)~

autoincrement

..J.

Co pyright (c) 19'19 Digital Equipment Corp., Ma ynard ,Mass.
DO NOT COpy
VAX-11 System Reference l"ianual
COMPANY CONFIDENTJ..AL
Assembler Notation
31-0ct-78
Rev 5
Page B-4
GENERAL MODE AODRt;SSlNG SUMMARY
4.

-(R)

autodecrem€nt

D(H)

byte, word, or longword displacement. register deferred.
a€f~ult is word if D is not known

B"D(R)

byte displacement

'i .

WAD(R)

word displacement

L"DtR)

longword displacement

byte, word, or longword
displacement off PC
default is longword if G is not known

10.

BAG

byte displacement off PC

11 .

~J"G

word displacement off PC

12.

LAG

longword displacement off PC

13.

GAG

general addressing
\absolute or PC-relative)

14.

iicons

autoincrement of PC (immediate) or
literal

15.

,s . . 1fcons

short literal

16.

..i.. "

immediate

1't •

\ R )[hx]

1d.

(R)+[Rxj

autoincrement indexed

19.

1iconsl Rx]

autoincrement of PC (immediate) indexed
\This is probably not useful.\

20.

.1.

"lfconsl fix)

autoincrement of PC (immediate) indexed
\lhis is probably not useful.\

21.

- (Ii )(Rx]

autodecrement indexed

22.

j) Ut) lHx]

byte, ~ord, or longword
displacement indexed.
register deferred indexed.

23.

bAlJ(R)LRx]

byte displacement indexed

24.

~AD(R)LRx]

word displacement indexed

25.

LAD(R)[Hx}

longword displacement indexed

,icons

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GENERAL MODE ADDRESSING SUMMARY

26.

ULRxJ

byte, word, or longword
displacement off PC indexed

27.

B"U[RxJ

byte displacement off PC indexed

20.

w"ULftx]

word displacement off PC indexed

29.

L"GLRxj

longword displacement off PC indexed

~O.

GAlocation(Rx]

general (absolute or PC-relative)
indexed

::;1.

e(R) [Rx]

byte displacement deferred indexed
with 0 displacement

32.

@(fd+LRxj

autoincrement deferred indexed

jj.

@lllocationl Rx]

autoincrement of PC (immediate)
deferred indexed

34.

~D(R)[Rx]

byte, word, or longword
displacement deferred indexed.

j5.

@I{'D (R) [Rxj

byte displacement deferred indexed

j6.

@w"D(R)[Rx)

word displacement deferred indexed

:/(

. ~L AI; (R) (RxJ

longword displacement
deferred indexed

38.

eG[Rx]

byte, word, or longword
displacement off PC deferred indexed

39.

@BAGlRxJ

byte displacement off PC deferred indexed

40.

@w"GlRx]

word displacement off PC deferred indexed

41 .

eL AU LftXj

longword dlsplacement off PC deferred indexed

42.

e(R)

byte displacement deferred
with 0 displacement

4j.

tHR)+

autoincrement deferred

44.

elf location

autoincrement of PC (immediate)

45.

@D(R)

byte, word, longword displacement
deferred

46.

@B"iJ(R)

byte displacement deferred

47.

eW"D(R)

word displacement deferred

40.

@L"DOn

longword displacement deferred

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GENERAL tvlODE

ADDRES~ING

SUtvl.t"'1ARY

49.

byte, word, or longword
displacement off PC deferred

50.

@B"U

byte displacement off PC deferred

51.

@VJ"G

\o4'ord displacement off PC deferred

52.

@L"'C

longword displacement off PC deferred

B.4 BRANCH DISPLACEMENT ADDRESSING
The
The general notation is locn, where locn is the branch address.
assembler fills in the displacement displ where displ = locn {updated value of PC}.

8.5

GENERIC OPCODE SELECTION

As a convenience to the programmer, the assembler automatically
selects from among similar instructions. This allows the programmer
to write code without worrying about these distinctions.

B.5.1

Branch Selection

If the programmer gives BR or ESB as the mnemonic, the assembler will
automatically select either BRB or BRw (BSBB or BSBw) based on the
distance to the label. If the label is not yet defined, the word
branch displacement form will be selected.

B.5.2

Number Of Operand Selection

If the programmer omits the final digit from those opcodes which have
two forms ,E'.g., ADDw instead of' ADDW2 or ADDW:), the assembler will
select the correct form based on the numb~r of' operands specified by
the user.
\Initially, the assembler always chooses the shorter form.\
\The idea of selecting the correct data type was rejected because the
assembler has no notion of' data type. The idea of doing jump/branch
resolution (including reversing the test condition) was rejected as
better left to compilers.\
[End of Appendix B)

Page 1

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

VAX-11 Procedure Calling Specification -- Rev 5

Specification Status:

Pending VAXA Approval

Architectural Status:

Under ECO control

File:

SRCR5.RNO

PDM #: not used
Date:

1-Feb-'"{9

Superseded Specs:

Rev 4

Author:

Richard Grove

Typist:

Gerry Hesley

Reviewers:

R. Brender,
P. Conklin,
D. Cutler,
A. G~ldstein,
T. Hastings,
D. Hustvedt,
P. Lipman, T. Rarich, R. Shaw, M. Spier

Abstract:

Appendix C contains a specification for use of the VAX-11
hardware CALL mechanism by standard higher level languages,
BLISS, and the assembly language.
This mechanism will be
used as the inter-module CALL interface for all major VAX-11
subsystems, ,including: RMS and the VAX/VMS Operating System.

L. Frampton,
H. Jacobs,

Specifications for calling sequenc~s, argument transmission,
stack usage, and state preservation are included.
Revision History:
Rev.1I
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5

Description
Original specification
Completion of specification
Update to SRM Rev 3 and format
ECOs
ECOs

Author
R. Grove
R. Grove
P. Conklin
P. Conklin
D. Bhandarkar/
T. Hastings

Revised Date
6-Feb-76
5-Mar-76
13-Jun-76
30-Mar-77
1-Feb-79

Procedure Calling Standard
Change History

Page C-990

1-Feb-79 -- Rev 5

Rev 4 to Rev 5
1•

Octaword t G_floating, H_floating.

ASCII text string, right justified data type.

Decimal Scalar String Descriptor.

Rev 3 to Rev 4:
1.

Packed decimal ECO.

CF to FP ECO.

Remove \ comments including
describing arglists.

Mask frame<28> reserved to DEC.

Add DSC$ mnemonics.

Add data types 22, 23.

Add classes 0, 2, 6 to 8.

Move bounds block.

Note that UNWIND alters return pOint.

10.

Note that procedures mayor may
null arguments.

11.

Clarify that RO and R1 can not contain two quantities.

12.

Note that the stack
exception routines.

13.

Document that complex has real before imaginary.

14.

Strings, arrays, and
values.

15.

If string function, then push args over one.

rejected

alternative

self-

Change 2 to 3 and 3 to 5.

Remove virtual array.

below

not

(SP)

procedures

handle

belongs

can

not

Rev 2 to Rev 3:
1•

Bring into SRM format as an appendix

Convert from pointers to 32-bit addresses

Reverse address and length in descriptors

omitted

trailing

interrupt

RO/R1

and

function

Procedure Calling Standard
Change History

1-Feb-79 -- Rev 5

Page C-991

Add zoned numeric string format

Explain why entry mask must be used

Reserve classes and types to CSS

Note interchangability of varying and fixed strings for reading

Length of packed string is in digits (nibbles-1)

Change name to DSC_FL_COLUMN and DSC_POINTER

10.

Swapped multipliers and limits in array descriptor

Rev 1 to Rev 2:
1.

Reverse address and length in description

Change register order in call frame

Arg count is unsigned byte

[End of SRCR5.RNO]

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APPENDIX C
PROCEDURE CALLING STANDARD

1-Feb-79 -- Rev 5

C.1

INTRODUCTION

This appendix specifies a software standard for use of the VAX-11
hardware procedure CALL mechanism. This standard is applicable to all
externally CALLable interfaces in
DEC-supported
standard
system
software.
This standard applies to all external procedure
standard DEC language processors, including:

CALLs

generated

BASIC+2/VAX
BLISS/VAX
COBOL/VAX
FORTRAN IV-PLUS/VAX
This standard is also applicable to inter-module CALLs to
subsystems.

major

VAX-11

This standard does not apply to calls to internal (or local) routines.
Within a single module, the language processor or programmer may use a
variety of other linkage and argument-passing techniques.
This standard specifies a single mechanism to be used in a wide variety
of applications.
As a result, certain compromises have been made
between the conflicting requirements of generality, uniformity, and
efficiency. Thus:
1.

The standard defines and supports the use of call-by-value,
call-by-reference, and call-by-descriptor.
This permits the
designer of a procedure to make trade-offs between generality
and efficiency.
The cost of this freedom is a somewhat more
complex interface as perceived by the caller of a procedure.

The procedure CALL mechanism depends on agreement between the
calling and called procedures to interpret the argument list.
The argument list itself is not fully self-describing.

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GOALS AND NON-GOALS
C.2

GOALS AND NON-GOALS

Goals for the VAX-11 procedure CALLing standard are:
1.

The standard must be applicable to all of the inter-module
CALLable
interfaces
in
the
VAX-11
software
system.
Specifically, the standard must consider the requirements of
BASIC, COBOL, FORTRAN, BLISS, MARS and CALLs to the operating
system. Thus:
1.

The standard must support all of the calling capabilities
needed
for the higher-level languages which DEC now
supports (BASIC, COBOL, FORTRAN).

The needs of other languages which DEC may support
future must be noted (PL/1, Algol, APL).

the

It must be possible to write calling and called procedures
BLISS and MARS which conform to the standard.

The standard
not
include
capabilities
for
should
lower-level
(e.g., BLISS, MARS, operating
components
system) which cannot be invoked from the higher-level
languages.

The calling program and called procedure can be
different languages, including any of the above.

written

The procedure mechanism must be sufficiently economical in both
space and time to be used and usable as the only calling
mechanism within VAX-11.

The standard should contribute to the writing of error-free,
modular, and maintainable software.
Effective sharing and
re-use of VAX-11 software modules is a significant goal.

The standard must allow the called procedure a variety of
techniques for argument handling. The called procedure may (1)
reference arguments indirectly through the argument list, (2)
copy scalars and array addresses, (3) copy addresses of scalars
and arrays.

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GOALS AND NON-GOALS
Some possible attributes of a procedure-calling mechanism have been
considered and rejected.
Specific non-goals for the VAX-11 procedure
CALL mechanism include:

C.3

It is not necessary for the procedure mechanism to provide
complete checking of argument data types, data structures, and
parameter access. The VAX-11 protection and memory-management
system is not dependent upon "correct" interactions between
user-level calling and called procedures.
Such
extended
checking may be desirable in some circumstances, but system
integrity is not dependent upon it.

The VAX-11 procedure mechanism need not provide complete
information for an interpretive DEBUG facility. The definition
of the DEBUG facility will include a DEBUG symbol table which
contains the required descriptive information.

DEFINITIONS

Procedure - A procedure is a routine which follows this specification.
A procedure may return values via the argument list and/or the standard
value return registers.
Function - A function is a procedure which returns a single value in the
value registers.
If additional values are returned, they are returned
via the argument list.
Subroutine - A subroutine is a procedure which does not return a known
value in the value registers. If values are returned, they are returned
via the argument list.
Address - A 32-bit VAX-1'1 address positioned in a longword item.
Exception Condition - Any procedure may be defined to have cases for
which it will fail or produce an exception condition. Such failures are
indicated by:
1.

Returning a function value indicating failure, or

SIGNALing a failure using the standard
condition mechanism, see Appendix D.

VAX-11

The choice of exception condition reporting mechanism is a part
interface speCification for each procedure.

exception
of

the

OTS - Object Time System. A collection of procedures which help support
a higher level language. OTS procedures are called using the standard
CALL mechanism.

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Page C-4
CALLING SEQUENCE
C.4

CALLING SEQUENCE

The calling program invokes the called procedure using either the
or CALLS instruction:
CALLG

Arglist.ab, Proc.ab

CALLS

Argcnt.rl, Proc.ab

CALLG

or
CALLS pushes the argument count Argcnt.rl onto the stack as a longword
and sets AP to the top of the stack. The complete sequence using CALLS
is thus:
Push

Argn

Push
CALLS

Arg1
#n,Proc

If the called procedure returns control to the calling procedure,
control must return to the instruction immediately following the CALLG
or CALLS instruction. Skip returns and GOTO returns are prohibited
except during UNWIND, see appendix D.
The called procedure returns control
executing the return instruction, RET.

C.5
C.5.1

the

calling

procedure

ARGUMENT LISTS
Argument List Format

The format of the argument list is a sequence of longwords:

+-----------------------+-------+
o
I
n
I :Arglist
+-----------------------+-------+
Arg 1
Arg 2
Arg n

+-------------------------------+
The argument count n is an unsigned byte contained in the first byte of
the list. The high order 24 bits of the first longword are reserved for
future use and must be zero. To access the argument count, the called
procedure must ignore the reserved bits and pick up the count with the
equivalent of a MOVZBL instruction.

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ARGUMENT LISTS
Each Arg entry in the argument list is a 32-bit longword
32-bit values may be:
1.

An uninterpreted 32-bit value.

An address; typically a pointer to
array, or a procedure.

An address of a descriptor;
fully below.

scalar

descriptors

value.

data

are

These

item,

discussed

an
more

The standard thus permits simple call-by-value, call-by-reference,
call-by-descriptor, or combinations of these. Interpretation of each
argument list entry depends upon agreement between the calling and
called procedures.
A procedure having no arguments is CALLed with a list consisting of a
argument count longword. This is efficiently accomplished by
CALLS

10, Proc.

A missing or null .argument, for example CALL SUB(A"B), is represented
on VAX-11 by an Arglist entry consisting of a longword O. Some
procedures allow trailing null arg~ents to be omitted, others require
all arguments; refer to the procedure's specification for details.
The argument list must be
procedure.

C.5.2

treated

read-only

data

the

called

Argument Lists And Higher-level Languages

Higher-level language functional notations for procedure CALLs
mapped into VAX-11 argument lists according to the following rules:

are

Actual arguments are mapped left-to-right
to
increasing
argument list offsets. The left-most (first) actual argument
corresponds to Arglist +4, the next to Arglist +8, etc.

Each actual argument position corresponds to
argument list entry_

single

VAX-11

C.5.2.1 Order Of Actual Argument Evaluation - Since most higher-level
languages do not specify the order of evaluation (with respect to side
effects) of actual arguments, those language processors may evaluate
actual arguments in any convenient order.
In constructing an argument list on the stack, a language processor may
evaluate arguments right-to-left and push their values on the stack. If
call-by-reference is used, actual argument expressions can be evaluated

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ARGUMENT LISTS

left-to-right,
right-to-Ieft.

with

pOinters

the

expression

values being pushed

The choice of argument evaluation order and code generation strategy is
constrained only by the definition of the particular language. Programs
should not be written which depend on the order of evaluation of actual
arguments.

C.5.2.2 Language Extensions For Argument Transmission - The
VAX-11
procedure standard permits arguments to be transmitted by value, by
reference, or by descriptor.
Each language processor will have a
default set of argument mechanisms. Thus ~'ORTRAN will pass scalars,
arrays and functions by reference, and will pass strings (CHARACTER) by
descriptor.
BASIC, however, will transmit both strings and arrays by
descriptor.
A set of language extensions is defined to reconcile the different
argument transmission techniques.
Each language will be extended to
provide the user explicit control of argument transmission in the
calling procedure.
An alternative to language extension is to use the (worst) general-case
solution
in
all
circumstances.
This achieves uniformity at a
substantial penalty in space and speed.
Each language must be augmented to provide, and each language
must support, the following compile-time intrinsic functions:

processor

~VAL(arg)

Corresponding argument list entry is the actual
32-bit value of the argument arg, as defined in the
language.

~REF(arg)

- Corresponding argument list entry is a pointer to
the value of the argument arg, as defined in the
language.

%DESCR(arg)

- Corresponding argument list entry is a pointer to a
VAX-11 descriptor of the argument, as defined in
this appendix and the language.

These intrinsic functions can be used in the syntax of a procedure
to control generation of the actual argument list. For example:

CALL

CALL SUB1(%VAL(123), %REF(X), %DESCR(A»
The intrinsic functions are a necessary escape mechanism in permitting
any procedure to be called by programs written in any higher-level
language. Careful design of procedure packages will minimize the actual
need to use these escape mechanisms.

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Page C-7
FUNCTION VALUE RETURN
C.6

FUNCTION VALUE RETURN

A function value is returned in register RO if representable in 32 bits
and registers RO and R1 if representable in 64 bits. Two separate
32-bit entities cannot be returned in RO and R1 because higher level
languages could not deal with them. If the function value cannot be
represented in 64 bits, the source language list of arguments and
formals is shifted by one and the first formal in the argument list is a
descriptor for the function value. One of the following mechanisms is
used to return the function value:
1.

If the maximum length of the function value is known (e.g.
octaword and H_floating), the calling procedure can allocate
the required storage and pass a pOinter to the function value
storage as the first argument.
This method is adequate for CHARACTER functions in FORTRAN
VARYING strings in PL/1.

and

The calling procedure can allocate a dynamic string descriptor.
The called procedure then allocates storage for the function
value and updates the contents of
the
dynamic
string
descriptor.
This method requires a heap (non-stack) storage
management mechanism.

Procedures, such as operating system CALLs, return a success/fail value
as a longword function value in RO. Success returns have bit 0 of the
returned value set (Boolean true); failure returns have bit 0 clear
(Boolean false). The remaining 31 bits of the value are used to encode
the particular success or failure status, refer to Appendix D.

C.7

The following registers have defined uses:
PC

- program counter

- stack pointer

- current stack frame pointer. Must always point at current
frame; no modification permitted within a procedure body.

- At the instant of CALL, AP must point to a valid argument
list. A parameterless procedure pOints to an argument list
consisting of a single longword containing the value O.

RO,R1 - Function value return registers. These registers are not
preserved by any called procedure~ They are available as
"free temporaries" to any called procedure.

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REGISTER USAGE
All other registers (R2, R3, ..• , R10, R11, and AP, FP, SP, PC) are
preserved across procedure calls. The called procedure may use any of
these provided that it saves and restores them using the procedure entry
mask mechanism. The entry mask mechanism must be used so that any stack
unwinding done by the condition handling mechanism will correctly
restore all registers.

C.8

STACK USAGE

The stack frame -created by the CALLG/CALLS instructions for
procedure is:
on-condition longword (0)
mask/PSW
AP

the

called

: (SP): (FP)

PC
HO

(optional)

R11

(optional)

FP always points at the on-condition longword of the stack frame.
other use of FP at any time within a procedure is prohibited.

Any

The contents of the stack located at higher addresses than the mask/PSW
longword belongs to the calling program;
it should not be read or
written by the called procedure, except as specified in the argument
list.
The contents of the stack located at lower addresses than (SP)
belongs to interrupt and exception routines; it must be assumed to be
garbaged continu~lly.
Local storage is allocated by the called procedure by subtracting the
required number of bytes from the SP provided on entry. This local
storage is automatically freed by the RET instruction.
Bit 28 of the mask/PSW longword is reserved to DEC for future extensions
to the stack frame.

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Page C-9
ARGUMENT DATA TYPES
C.9

ARGUMENT DATA TYPES

The following encoding is used for atomic data elements:
Mnemonic

Code

Description
Unspecified.
The
calling
program
has
specified no data type; the called procedure
should assume the argument is of the correct
type.
string;

see

Byte Logical. 8-bit unsigned quantity.
note at the end of this section.

See

Word Logical. 16-bit unsigned quantity.
note at the end of this section.

See

Longword Logical. 32-bit unsigned quantity.
See note at the end of this section.

Quadword Logical. 64-bit unsigned quantity.
See note at the end of this section.

Octaword Logical. 128-bit unsigned quantity.
See note at the end of this section.

Byte Integer.
integer.

8-bit

signed

2's-complement

word Integer.
integer.

16-bit

signed

2's-complement

Longword
Integer.
2's-complement integer.

32-bit

signed

Quadword
Integer.
2's-complement integer.

64-bit

signed

Octaword
Integer.
2's-complement integer.

128-bit

signed

Single-precision Floating.
F_floating point.

32-bit

VAX-11

Double-precision D_Floating.
D_f'loating point.

64-bit

VAX-11

Double-precision G_Floating.
G_floating point.

64-bit

VAX-11

Quadruple-precision Floating.

128-bit VAX-11

Bit.
Ordinarily
a
bit
discussion of descriptors.

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ARGUMENT DATA TYPES
H_floating point.
Complex. Ordered pair of single-precision
F_floating quantities, representing a complex
The
lower
addressed
quantity
number.
represents
the
real
part,
the higher
addressed represents the imaginary part.
Double-precision Complex.
Ordered pair of
.louble-precision D_floating point quantities,
representing a complex number.
The lower
addressed quantity represents the real part,
the higher addressed represents the imaginary
part.
Double-precision Complex.
Ordered pair of
double-precision G_floating point quantities,
representing a complex number.
The lower
addressed quantity represents the real part,
the higher addressed represents the imaginary
part.
Quadruple-precision Complex. Ordered pair of
quadruple-precision
H_floating
point
quantities, representing a complex number.
The lower addressed quantity represents the
real part, the higher addressed represents
the imaginary part.
The following string types are ordinarily described by a string
descriptor. The data type codes below occur in those descriptors:
14

ASCII text string.
characters.

A sequence of 8-bit ASCII

Numeric string, unsigned.
end of this section.

DSC$K_DTYPE_NL

Numeric string, left separate sign.

DSC$K_DTYPE_NLO

Numeric string, left overpunched sign.

DSC$K-PTYPE_NR

Numeric string, right separate sign.

DSC$K_DTYPE_NRO

Numeric string, right overpunched sign.

DSC$K_DTYPE~Z

Numeric string, zoned sign.

DSC$K_DTYPE_P

Packed decimal string.

DSC$K_DTYPE_Z I

Sequence of instructions.

DSC$K_DTYPE_ZEM

Procedure entry mask.

See

note

the

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Page C-11
ARGUMENT DATA TYPES
The following type codes are RESERVED for future use:
24

RESERVED to DEC

31-191

RESERVED to DEC

192-255

RESERVED to CSS and customers

Note:
The unsigned data types (codes 2,3,4,5,15,25) do not allocate any space
for representing the sign. All bit or character positions are used to
represent significant data.

C.10

ARGUMENT DESCRIPTORS

A uniform descriptor mechanism is defined for use by all procedures
which conform to this standard. Descriptors are uniformly typed and the
mechanism is extensible.
As new varieties of descriptor
become
necessary, they will be added to this catalogue.

C.10.1

Descriptor Prototype

Each class of descriptor
following format:

consists

of at

+-------+-------+---------------+
I CLASS I DTYPE I
LENGTH
+-------+-------+---------------+
POINTER
+-------------------------------+

least

longwords

the

: Descriptor

DSC$W_LENGTH
<0,15:0>

A one-word field specific to the descriptor
class; typically a 16-bit (unsigned) length.

DSC$B_DTYPE
<0,23:16>

A one-byte "atomic data type code (see C.9)

DSC$B_CLASS
<0,31:24>

A one-byte descriptor class code (see below)

DSC$A_POINTER
<1,31:0>

A longword pointing to the first byte of the
data element described.

Note that the descriptor can be placed in a pair of registers with a
MOVQ instruction and then the length and address used directly. This
gives a word length, so the class and type are placed as bytes in the
rest of that longword. Class 0 is unspecified and hence no more than
the above information can be assumed.

Scalar, String Descriptor (DSC$K_CLASS_S)

A single descriptor form is used for scalar data and simple strings.

+-------+-------+---------------+
I
1
I DTYPE I
LENGTH
I
+-------+-------+---------------+
POINTER
+-------------------------------+
DSC$W_LENGTH

DSC$B_DTYPE
DSC$B_CLASS
DSC$A_POINTER

C.10.3

Length
of data
item
in
bytes,
unless
DTYPE EQLU 1 (Bit), or 21 (Packed Decimal). Length
of data item is in bits for bit string.
Length of
data item is in digits (nibbles-1) for packed
string.
1=DSC$K_CLASS_S
Address of first byte of data storage

Dynamic String Descriptor (DSC$K_CLASS_D)

The following descriptor form is used for variable length strings that
do not have a fixed maximum length (e.g., BASIC strings). When the
string is written, both the length and address fields may be modified.
Space is presumed to be allocated dynamically. Note that for reading,
this format is interchangeable with type 1 (fixed string).

+-------+-------+--------------+
2
I DTYPE I
LENGTH
I
+-------+-------+--------------+
POINTER
I
+------------------------------+
Current length of data item (in bytes, unless
E"QLU 1, or 21).
DSC$B_DTYPE
DSC$B_CLASS
DSC$A_POINTER

DTYPE

2=DSC$K_CLASS_D
Current address of lowest addressed byte of string.

Varying String Descriptor (DSC$K_CLASS_V)

The following descriptor form is used for variable length strings having
a fixed maximum length (e.g., PL/1 VARYING). Note that for reading,
this format is interchangeable with type 1 (fixed string).

+-------+-------+---------------+
3
I DTYPE I
LENGTH
+-------+-------+---------------+
POINTER
+---------------+---------------+
MEZ
I
MAXLEN
I
+---------------+---------------+
DSC$W_LENGTH
DSC$B_DTYPE
DSC$B_CLASS
DSC$AJOINTER

Current length of data
DTYPE EQLU 1, or 21).

item

(in

3 =DSC $K_C LASS_V
Address of lowest addressed byte of string.

<2,15:0>

Maximum length of data item (in bytes
unless DTYPE EQLU 1 or 21).

<2,31: 16>

MBZ;

DSC$W~MAXLEN

bytes

reserved to DEC.

unless

Array Descriptor (DSC$K_CLASS_A)

An array descriptor consists of 3 contiguous blocks.
The first block
contains the descriptor prototype information and is part of every array
descriptor. The second and third blocks are optional.
If the third
block is present then so is the second. A complete array descriptor has
the form:

+-------+-------+---------------+
4
I DTYPE I
LENGTH
: : Descriptor
+-------+-------+---------------+
POINTER
I
+-------+-------+---------------+
I DIMCT : AFLAGSIDIGITS I SCALE I
Block 1 - Prototype
+-------+-------+---------------+
ARSIZE
I
+-------------------------------+
+--------~----------------------+

+-------------------------------+
M1
:
+-------------------------------+
+-------------------------------+
M(n-1)
+-------------------------------+
+-------------------------------+
+-------------------------------+
L1
+-------------------------------+
U1
I
I

I
,

Block 2 - Multipliers

+------------------~------------+

Block 3 - Bounds

+-------------------------------+
:
Ln
:
+-------------------------------+
Un
:
+-------------------------------+
DSC$W-LENGTH
DSC$B_DTYPE
DSC$B_CLASS
DSC$A_POINTER

Data element size (in bytes unless
DTYPE EQLU 1, or 21)
4=DSC$K_CLASS-A
Address of first actual byte of data storage.
Signed power of ten multiplier to convert the
internal form to external form. For example,
if internal number is 123 and scale is +1, then
the represented external number is 1230.
If non-zero, unsigned number of decimal digits

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Procedure Calling Standard
1-F'eb-79 -- Rev 5
Page C-15
ARGUMENT DESCRIPTORS
in the internal representation. If zero, the
number of digits can be computed based on
DSC$W_LENGTH.
DSC$B_AFLAGS
<2,23:16>

Array flag bits.

Reserved
<2,20:16>

MBZ

DSC$V_FL_COLUMN
<2,21>

If set, the elements of the array are
stored by columns (FORTRAN). Otherwise the
elements are stored by rows.

DSC$V_F'L_COEFF
<2,22>

If set, the multiplicative coefficients in
Block 2 are present.

DSC$V_FL_BOUNDS
<2,23>

If set, the bounds information in' Block 3
is present.

DSC$B_DIMCT
<2,31:24>

Number of dimensions

DSC$L_ARSIZE
<3,31:0>

Total size of array
(in bytes unless DTYPE EQLU 1 or 21).

DSC$A_AO
<4,31:0>

Address of element A(O,O, ••. ,O). This need
not be within the actual array; it is the same
as DSC$A_POINTER for O-origin arrays.

DSC$L_Mi
<4+i,31:0>

Addressing coefficients
( Mi = Ui-Li+1 )

DSC$LJ.,i
<3+n+2*i,31:0>

Lower bound of it th dimension.

DSC$L_Ui
<4+n+2*i,31:0>

Upper bound of itth dimension.

Procedure Descriptor (DSC$K_CLASS_P)

The descriptor for a procedure specifies its entry address and
value data type, if any.

function

+-------+-------+---------------+
5
: DTYPE I
LENGTH
+-------+-------+---------------+
:
POINTER
+-------------------------------+
DSC$W_LENGTH
DSC$B_DTYPE
DSC$B_CLASS
DSC$A_POINTER

Length associated with the function value.
Function value data type.
5 =DSK$K_CLASS_P
Address of entry mask to routine.

Procedures return values in RO or RO and R1 as follows:
1.

If a scalar, then the value is in RO or RO and R1.
The type
and length are specified as DSC$B_DTYPE and DSC$W_LENGTH in the
procedure descriptor.

If not a scalar (i.e., if an array, a string, a procedure,
etc.), then no function value may be returned. Instead, the
argument expressed as a function value is in,stead passed as the
first argument and the other arguments are shifted down by one.

C.10.7

Procedure Incarnation Descriptor (DSC$K_CLASS_PI)

The descriptor for a procedure incarnation is the same as a procedure
descriptor with the addition of its call frame address. This is used to
refer to a specific incarnation of a procedure, such as in ALGOL or
PL/I.

+-------+-------+---------------+
6
I DTYPE I
LENGTH
:
+-------+-------+---------------+
POINTER
+-------------------------------+
FRAME address
+-------------------------------+
DSC$W_LENGTH
DSC$B_DTYPE
DSC$B_CLASS
DSC$A_POINTER
DSC$AJRAME
(2,31:0>

Length associated with the function value
Function value data type.
6=DSC$K_CLASS_PI.
Address of entry mask to routine.
Address of frame of this incarnation.

Co pyright (c) '1919 Digital Equipment Corp., i"'laynard , Mass.
DO NOT COPY
VAX-11 System Reference Manual
COIv1PANY CONFIDENTIAL
Procedure Calling Standard
1-Feb-19 -- Rev 5
Page C-11
ARGUMENT DESCRIPTORS
C.10.8

Label Descriptor (DSC$K_CLASS_J)

The descriptor for a label specifies the start of its code.

+-------+-------+---------------+
I
1
I DTYPE I
LENGTH
:
+-------+-------+---------------+
POINTER
+-------------------------------+
DSC$W_LENGTH
DSC$B_DTYPE
DSC$B_CLASS
DSC$A_POINTER

C.10.9

Not used; MBZ.
Not used; MBZ.
1=DSC$K_CLASS_J
Address of label to jump to.

Label Incarnation Descriptor (DSC$K_CLASS_JI)

The descriptor for a label incarnation is the same as a label descriptor
with the addition of its procedure incarnation's call frame address.
This is used to refer to a label within a specific incarnation of a
procedure, such as in ALGOL or PL/I.

+-------+-------+---------------+
:
8
I DTYPE I
LENGTH
I
+-------+-------+---------------+
POINTER
+-------------------------------+,
FRAME ADDRESS
+-------------------------------+
I

DSC$W_LENGTH
DSC$B_DTYPE
DSC$B_CLASS
DSC$A_POINTER
DSC$A_FRAME
(2,31:0>

Not used; MBZ.
Not used; MBZ.
8=DSC$K_CLASS_JI.
Address of label to jump to
Address of frame of this incarnation.

Copyright(c) 1979 Digital Equipment Corp. ,Maynard ,Mass.
DO NOT COPY
VAX-11 System Reference ~~nual
COMPANY CONFIDENTIAL
Procedure Calling Standard
1-Feb-79 -- Rev 5
Page C-18
ARGUMENT DESCRIPTORS
C.10.10

Decimal Scalar String Descriptor (DSC$K_CLASS_SD)

A single descriptor form is used to give decimal
information for scalar data and simple strings.

size

and

scaling

+-------+-------+---------------+
9
I DTYPE I
LENGTH
+-------+-------+---------------+
POINTER
+---------------+-------+-------+
RESERVED
!DIGITS I SCALE !
+---------------+-------+-------+
DSC$W_LENGTH

DSC$B_DTYPE
DSC$B_CLASS
DSC$A_POINTER
DSC$B_SCALE

Reserved
<2,31 : 16>

C.10.11

unless
bytes,
in
data
item
Length
of
DTYPE EQLU 1 (Bit) , or 21 (Packed Decimal) . Length
of data item is in bits for bit string.
Length of
data item is in digits (nibbles-1) for packed
string.
9=DSC$K_CLASS_SD
Address of first byte of data storage
Signed power of ten multiplier to convert the
internal form to external form. For example, if
internal number is 123 and scale is +1, then the
represented external number is 1230.
If non-zero, unsigned number of decimal digits in
the internal represel'.tation. If zero, the number of
digits can be computed based on DSC$'W_LENGTH.
Reserved for future use.

MBZ.

Reserved Descriptors

Descriptor classes 10-191 are RESERVED to DEC. Classes 192 through 255
are RESERVED to CSS and customers.
\Descriptor class 10 has been
assigned to COBOL-74 and will be documented later.\
[End of Appendix C]

Page 1

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

VAX-l1 Condition Handling Facility -- Rev 5

Specification Status:

Approved

Architectural Status:

Under Change Control

File:

SRDR5.RNO

PDM II: not used

Date: 31-Mar-77
Superseded Specs:
Author:

Conklin, T.

Typist:

Conklin

Reviewer(s):

Hastings

R. Blair, R.Brender, P. Conklin,

D. Cutler,

R. Grove,

D. MacLaren, J. Rudy, M. Schwartzman.
Abstract:

Appendix D defines a unified facility which supports the
exception handling mechanisms needed by each of the common
languages. lt provides the programmer with some control
over fixup, reporting, and flow of control on errors. it
provides subsystem and application writers with the ability
to override system messages in order to give a more
suitable application oriented interface.

Revision History:
Rev 4f
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5

Description
original
major expansion
general cleanup and proposal
heavy pruning
result of implementation

Author
L. Ii'rampton

M. Schwartzman
T. Hastings
P. Conklin
P. Conklin

Revised Date
Mar-76
21-Apr-76
17-Sep-'76
12-Nov-'(6
31-Mar-77

Condition handling Facility
History

.Page D-990

j1-Mar-77 -- hev 5

Ch:=.mge

Rev 4 to Rev 5:
1.

hdd minimum constraints to goals.

Change CHF$ to Llb$ or SYS$ or S~~ where appropriate.

Document that hard~are exceptions are treated like

calls

SlG~AL.

Add a b5K stack frame depth limit.

Add table of actions.

Add ~S~_INSFRAME error.

Note that a handler may be called back on unwind.

Remove table with summary of symbols.

Document that severity is condition<2:0).

10.

Ada definition of exception vectors to section 4.

11.

Change name from SET_UNWIND to uNWiND.

12.

Allow handler to modify the signal argument veotor.
particular, to modify the severity of condition_value.

13.

Add symbols for offsets.

Rev ~ to Rev 4:
1.

Remove function vs. subroutine call indicator.

rlemove ERRRET function and ability
signaling VS. status reporting.

Remove AHL and ability to list a set of handlers.

Simplify REVBRT.

Rem07e PUSH/POP Handler.

Remove spscial conditions ERRRET and hATCH_ANY.

Hemove hNABLE/DlSABLE except for h/~ PS~ bits.

hemove SIGNAL DISABLEd.

Add unwind_PC to handler args.

control

exception

Condition Handling Facility
Change history

Page D-991

:'1-h&r-'l7 -- Rev 5

10.

Replace STARLET
Ho.ndler.

resignal

argument

with

frame

depth

11.

Replace establisher args to Handler
ar'gument.

with

establishEr

12.

Add MBZ arg for future growth.

13.

Add Handler return value of CHF$~_R£SlGNAL.

14.

Shift handler control return value bits left one.

15.

Add OTS frame above main program.

16.

Make names LEQ 15 characters.

17 •

hemove
CHF.$E_RE'LTO_TERMINATE,
CHF$TERMINATE. They can be added

to
frame

and

CHF$E_TERMINATE,

in the future if needed.

18.

Remove handler and ~ignaler look ahead. Move default action
to be at top of stack and to always issue message. The error
status codes are error conditions and result in image exit.

19.

Aad vectored Handlers.

20.

Modify handler argument format to agree with that from system
signals. ~olves the HO/R1 problem.

21.

Un multiple active signals,
establisher's Handler.

22.

hemove arithmetic
exception.

23.

Change "process termination" to "im~ge exit".

24.

Remove Explicit versus implicit terminology.

2~.

Change fac$E_... to fac$_ ...

26.

Add procedure library argument notation.

2'i.

Change CF to FP.

28.

Change handler arg layc";.1t.

29.

Add CHF$STOP.

jOe

Change ChF$uNW1ND to CHF$SE1'_UNWl~D with different semantics.

31.

Add example to Multiply active signals.

exceptions

enter

Handler's

Handler,

they

since

are

not

system

Condition Handling r'acility
Change History

ii1-ivlar-'17 -- Rev 5

32.

Remove BLISS, OTS, and STARLET changes.

33.

Remove redundant or obsolete definitions.

Rev 2 to Rev 3:
1.

Eliminate conditional Handler.

Specify specific routines and codes.

Eliminate PROPAGATE-ENABLE/DISABLE.

Add PUSH/PUP Handler.

Add UWW1NO.

Add ERRREl'.

Hev 1 to Rev 1:::
1.

Add special case of multipl~ active signals.

Establish consistent conceptual framework.

Establish consistent terminology.

LEnd of SROR5.RNO]

·Page D-Y92

APPENDIX D
CONDITION HANDLING FACILITY

. 31-Mar-77 -- Rev 5

D. 1 TERMINOLOGY
Condition Handling Facility - A collection of VAX-11
Library
procedures and operating system services which implement the condition
handling mecnanisms ot' the VAX ... 11 system.
Condition - A condition occurring during an operation which
is brought to the attention of the invoker of the operation. Although
an exception condition usually represents a failure, it is not
restricted to error Situations.
Exc~ption

Condition Value - A 32-bit quantity
exception condition. The format is:
j

uniquely

which

1 1
6 5

1 0

specifies

3 2

+-+-------~----~--~-------------+-------------------------+-----+

:el

facility code

status code

lsever:

\ +-+-----------------------------+-------------------------+-----+
\

C = 1 if Customer or CSS facility code
o if Digital facility code
sever is the severity code as follows:
bit <0> is set for success (logical true)
bits <2:1) distinguish degrees of success or failure
thus, the field <2:0) can be considered as a number
o = warning
1 = success
2 = error
ij = severe_error
3, 5, 6, 7 reserved to DEC for the future

Copyright(c) 1Y79 vigital Equipment Corp.,Maynard,Mass.
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Condition handling f'acility
31-tvlar-'i7 -- Rev 5
Page D-2
TE;.Ri'11~OLOGY

Condition Symbol - A global symbol used to specify a condition
A condition symbol has the form;

value.

where fac is the three letter facility name and symbol is a string of
alphanumerics and unaerlines which identify the specific condition.
Procedure Activation - The environment in which a procedure executes
including a unique stack frame allocated in the process stack for
temporary storage.
Handler - A function which a procedure activation establishes.
handler is called when an exception condition is signalea.

~ignal

- The standardized procedure call to the signal procedure to
indicate the occurrence of an exception condition.
the signal
procedure Calls 2. previously established handler.
Signals are also
generated by th~ operating system in response to hardware detected
exceptions and some software detected exceptions.

D.2

GOALS
1.

ProvidE what the common OTS needs to
languages.

support

the

different

Provide the programmer with some control
reporting, and flow of control on exceptions.

over

fixing,

Provide subsystem 2nd application writers with the ability to
overrids system messages in order to give a more suitable
application oriented interface.

At a minimum, the following must be possible:
4.

tor fortran, allow routines to signal an 01'S
the main program that does the ERRSET check.

routine

above

For bASIC, support the 0N - GOIO statement.

For COBOL, support the USE - FOR statement.

Application programmers must be able to intercept all system,
OTS, and library messages. The condition handling routine
must be able to issue an alternate message. It must also be
able to unwind and send control to a recovery point.

VAX-11 System Reference Manual
Condition Handling facility

C(Jt-'lPA~Y

DO NOT COpy

CONFIDENTIAL

j1-1"lar-Ti -- Rev 5

Page D-j

GOALS
From thesE goals
subordinate gOcls:

and

constraints

can

derived

the

following

Provide a standardized, language-independent way for handling
errors (and other exception conditions) which is usable by
all procedures written in any language, including 14'ORTRAN,
COBOL, and BASIC, as well as ~ARS and bLISS. This goal i~
derivea from the goal of allowing any language -to call
procedures ~ritten in any other language. The users of this
facility are the Common OTS,
subsystem
writers,
and
programmers writing in any of these languages.

Handle hardware and software detected exception conditions in
the same w~y with the same functionality, including creation
of defaults.

10.

Provide a
mechanism
whose
ease
of
use
encourages
understandable and reliable programming. 1n particular the
caller of a procedure must only be able to affect its
execution in well defined ways.

11.

Avoid one pitfall of the PL/I on
is:

condition

mechanism

which

PL/~ does not provide any way for
intervening procedure
activations to perform user specified cleanup when a
(non-local) GO TO is performed from a handler to the
procedure which established it.

12.

D.j

Add no space or time overhead LO procedure calls and returns
which do not establish handlers. tolinimize time overhead for
establishing handlers at the cost of increased time overhead
when exceptions occur.

h£TUHNING A CONDITION VALUE

The most rE;;liable means for indicating a software detected exception
condition occurring in a called procedure is for the called procedure
to return a condition value as a function Value and for the caller to
check the return value for TRUE or FALSE. lRUE is bit 0 set and FALSE
is bit 0 cleared.
lRUE means that the requested operation was
performed successfully; F'ALSE means an error condition occurred; in
both cases, the rest of the value is a condition value.
Thus, most
procedures are written as functions, rather than subroutines. If it
is necessary to indicate an exceptional situation without returning a
value, then generate a LALL to L1B$SlGNAL, refer to section 1,
I' Signaling a condition.

Copyright(c) 1979 Digital E.quipment Corp. ,lilaynard,Mass.
DG NOT COpy
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COMPANY CONFlDENTlAL
Condition handling Facility
j 1-Mar- rtl -- Rev 5
Page D-4

ESTABLISH A CONDITION HANDLER
D.4 ESTABLISH A CONDITION HANDLER
for the primary purpose of handling hardware detected exceptions, the
VAX-11 system supplies a mechanism for the programmer to specify a
,handler function to be called when an exception occurs.
Ihis
, mechanism may also be used for software detected exceptions.
Each procedure activation has a condition handler potentially attached
to it via a longword in its stack frame. Initially, the longword
contains 0, indicating no handler. A handler is established by moving
the address of the handler's procedure entry point mask to the
establisher's stqck frame.
\

In addition, the operating system provides two exception vec~ors at
each access mooe.
These vectors are available to deciareA1andiers
which take precedence over any handlers declared at the procedure
level.
These are used, for example, to allow a debugger to monitor
all exceptions, whether or not handled. Since these handlers do not
obey the procedure nesting rules, they should not be used by modular
code. Instead, the stack based declaration should be used.

A procedure library entry point is d~fined to help users of languages
which do not provide explicit syntax to reference the stack frame or
to declare handlers:
old_hr.;tndler.flu.r = LIB$ESTABLISH (new_handler.flu.rp)
The routine is:

MOVL
Ivl0VAL
RET

@12(FP),RO
e4(AP),t!12(ftP)

;get previous handler
;set new handler
;return to caller

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTlAL
Condition Handling Facility
31-Mar-'i7 -- Rev 5
Page D-5
REVERT ftANDLER
D.5

REVERT HANDLER

The revert handler operation deletes the handler associated with the
procedure activation. This is done by ciearing the handler address in
the stack frame.

A procedure library entry point is defined to help users of languages
which do not provide explicit syntax to reference the stack frame or
to revert handlers;
old_handler.flu.r = LIB$REVERT
The routine is:

D.6

MOVL

e12 (FP), RO

CLRL
RET

@12(F'P)

jget previous handler
;clear handler
jreturn to caller

ENABLING/DISABLING CONDITIONS

The purpose of disabling a condition within a procedure activation is
to prevent any established handler for the condition from getting
control. This is allowed primarily for the hardware enableable
exceptions.
Procedure library entry points are defined to help users of languages
which do not provide explicit syntax to enable exceptions or to
reference the PSW:
old_setting.wlu.v = LIB$FLT_UNDER (new_setting.rlu.r)
old_setting.,;Iu.v = LIB$INT_OVER (new_setting.rlu.r)
old_setting.wIu.v = LIB$DEC_OVER (new_setting.rlu.r)
where old_setting and new_setting are Boolean values.
The routine in each case is:
EXTV
INSV
RET

pos,#1,4(FP),RO ;get boolean value of old setting
@4(AP),pos,#1,4(FP) jset new value in
j saved PSW
jreturn to caller

Copyright(c) 15H9 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
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CGl"!,PANY CONFIDENTIAL
Condition handling facility
jl-i\lar-',7 -- hev 5
Page D-6
~iGNAL A CONDIT10N

D.,

SIGNAL A CUNDITIO~

The signal operation is the method used for indicating that an
exception condition has occurred.
It is primarily intended for
indicating the occurrence of hardware detected exceptions.

D., . 1 Signal
a language or user
standard procedure:

~hen

wishes

issue

CALL Ll.B$SlGl~AL lcondition_value.r'lu.v,

signal,

calls

the

ar~list ... )

when a language or user wishes to issue a signal and never continue,
it calls the standard procedure:
CALL LIB$STOP (condition_value.rlu.v, ar&-list ..• )
where in both cases condition_val\.4e indicates the condition which is
being signaled.
Conditipn_value<31:S> indicate the condition and
condition_value<2:0> indicate the severity. The severity should be
chosen as follo~s. If the default action should be to issue a message
and continue, then the severity should be 1 (i. e., "success").
Otherwise, the choice should be between 0, 2, and 4 according to what
severity of error should be reported to the command processor. In the
choice between error and severe error (2 and 4), the norm is
severe_error unless a good re&S0n exists to make it error. The
arguments ar&-list are a series of arguments describing the details of
the exception.
lhese are the same arguments used to issue a system
message. Note that unlike most CALLs, L~B$SrGNAL preserves RO and Rl
as well as the other registers. This allows a debugger to display the
entire state of the process at the time of the exception.
It also
allows signals to be plac6d in assembly language code without changing
the register usage.
This is useful for debugging checks
and
statistics gathering.
hardware and system service exceptions behave
as though they were a call to L1B$SlGNAL.
The signal procedure examines the two exception vectors and then up to
65K previous stack frames. The current and previous stack frames are
found by using FP and chaining bacK through the stack frames using the
saved FP in each frame. lhe exception vectors are a pair of address
locations per access mode.
A frame before the call by the system command processor to the main
program establishes a catch-all handler which issues system messages.
The catch_all handler uses condition_value to call $GETEHR to get the
message and then uses $FAO and the arK-list to output the message. If
the condition_value<O> is set the catch_all handler returns with
SS~_CONT1NLJE, otherwise it calls SYS$EXIT.

Copyright{c) 1979 Digital equipment Corp~,t~aynard,Mass.
DO NOT COPX
VAX-ll ~ystem Reference Manual
COl~PANX CONflDEN1'~AL
Condition handling facility
~1-Mar-17 -. hev 5
Page D~7
SlGNAL A C0ND1TION
the stack search terminates when the old ff is 0 or is not accessible
or 65K frames have peen examined. If no handler is found, or all
handlers returned with a S$$JtBSIGNAL, then SIGNAL issues a message
that no handler was found ana then issues the SlUl~ALed message via
~GETERH and ;fAO
and then calls SYS~~llT.
This message is not
signalled.
If a handler returns SS$_CONTlNUE, and Llb$STOP was not call~d, then
control returns to the signale'r. Otherwis~ l,.,lS$STOP issues a message
that there was Qn attempt to continue from a non-continuable exception
and calls SIS$EXIT. This message is not signaled.

Copyri.ght{c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Condition Handling Facility
31-Har-77 -- Rev 5
Page D-8
SIGNAL A CONDITION
All combinatiops of interaction between handler actions, the default
handler, the type of signal, and the call to signal or stop are
detailed in the following table.
handler I no handler
specifies : is found
UNWIND I (stack bad)

condition I catch all I handler
(0) Igets cntrol: specifies
I (default) I continue

+-----+------~----+-----------+-------~---+-----------+

call to I

SlG~AL

I
I condition
I
message

I"no handler I
:
found II
RET
UNWIND
I condition
RET
message
EXIT
+-----+---~-------+-----------+-----------+-----------+
I"no handler I
condition
I
found"
o
message
RET
U~WIND
Icondition
EXll
message
EXIT

.-------+-----+-----------+-----------+-----------+-----------+
condition I
l"no handler:
message I "can't
:
"can't
: continue":
t;XlT
continue" I
EXIT
STOP

UNWIND

:
found"
I condition
message
EXIT

+-----+-----,------+-----------+-----------+-----------+
I
I"no handler!
o

condition
message
I
EXlT
I

"can't
I
continue ll :
EXI T
I

UNWiND

I
found"
Icondition
message
EXIT

+-----+-----------+-----------+-----------+-----------+
condition message is the standard message for
the condition value as retrieved by $GETERR
and formatted by $FAO.
lino handler found" is a, standard message which
indicates tha.t no handler was found (i. e . ,
that the stack is bad). The message
distinguishes between no handler (old FP = 0
or too many frames) and access violation
(old F'P = junk).
"can't continue" is a standard message which
indicates an attt3mpt to continue from a call
to LIB$STOP. The message includes part of
the standard condition message.

Copyright(c) 1979 Digital }:;quipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONF1DEN1IAL
Condition Handling ft"'acility
31-Mar-/7 -- Rev 5
Page D-9
SIGNAL A CONDITION
D.7.~

handler

If a condition handler is found on a software detected exception,

the

ha.ndler is called with a argument list consisting of:
continue.wlu.v = handler (signal_args.ml.ra, mechanism_args.ml.ra)
where each argument is a reference to a longword vector. The first
lon.gword of each vector is the number of remaining longwords in the
vector. The symbols CHF$L_SIGARGLST (=4) and CHF$L_MCHARGLST (=8) can
be used to reference the handler arguments relative to AP.
Sj.gnal.,....arss is the arg list from the call to LIB$SlGNAL or LIB$Sl'OP.
In particular, the second longword is the condition_value being
signaled. Since bits <2:0) of the condition_value indicate severity
and do not indicate which condition is being signalled, the handler
should examine only condition_value<31:3>. The setting of bits <2:0>
vary depending upon the environment.
In fact, some handlers may
simply change the severity of a condition and resignal.
The symbols
ChF$L_SIG_ARGS (=0) and CHF$L_SIG_NAME (=4) can be used to reference
the elements of the signal vector.
Mechanism_args is a vector of five longwords
(4.rl.v, frame.rl.v, depth.rl.v, RO.rl.v, R1.rl.v)
+----------------------~--------+

frame
+-------------------~-----------+

depth
RO
R1

+-------------------------------+
Fra$€ is the contents of in the establisher's FP. This can be used as
a base to reference the local storage of the establisher if the
restrictions in section 8 are met. Depth is a positive counter of the
number of procedure activation stack frames above the signal that the
handler was established.
Depth has the value 0 for an exception
handled by the activation invoking the exception (i.e., containing the
instruction causing the harQware exception or calling LIB$SlGNAL).
Depth has positive values for procedure invocations calling the one
having the exception (1 for the immediate caller, etc.) If a system
service gives an exception, the immediate caller of the service gets
notified at depth = 1.
Depth has value -2 when the handler is
established by the primary exception vector and -1 when it is
established by. the secondary vector.
HO and R1 are the values of
these registers at the time of the call to LIB$SlUNAL.

Copyrighttc) 19',9 Digital equipment Corp. ,I.".laynard,J:I~ss.
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j 1-lViar-'({ .. - hey '5
Page D... 10
SlG~AL A CONDITiON
The handler function must return with a function value to indicate
whether it wants the prooedure to continue (SS$_CO~'fJ.NUE) or the
signal to be resignaled (SS~JtESlGNAL).
If the handler wants to
unwind, it calls SYS~uNwlND and then returns.
In this case the
handler function value is ignored.
For hardware detected exceptions, the condition.,....value indicates which
exception vector was taken and the next 0 or several longwordB are the
additional parameters as specified in Chapter 6.
The remaining two
longwords are the PC and PSL:
n

condition

+-~----------~--~-~~~~~~-~.~~~-~+

none or some
additional
arguments

\
n

+-------------------------~-----+I

+-~---------~--~---~~~~~~~~~-~

PSL

+------~--~~------~~-~-~-~~-~~~~+

D.b

OPTIONS OF hANDLER

In order not to impact compiler optimizatiQn, a handler and anything
it
calls
is restricted to referenCing only explicitly passed
arguments. 'lhay cannot reference COMt'lON or other externa,l storage and
they c~nnot reference iocal storage in the procedure which establisned
the handler. ~ompilers relaxing this rule must ensure that any
~ariables
referenced by the handler are always kept in memory
(VOLAT1LE) and have a full lifetime.
if the handler decides not to handle the condition, it returns to
caller with a function value of S~$~RES1GNAL.

its

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Pag~ D~11
OPTIONS OF hANDLER
when an exception condition occurs, the handler function performs
actions in three distinct areas before returning a function value to
the signaler. The handler actions are:
1.

Fix the problem:
1.

lake corrective action so that a
the desired effect.

~IGNAL

continue

will

achieve

a different condition. Note that this SIGNAL will
check the exception vectors and then search only frames
which were not searched on the previous still aotive
signals. Refer to section 10, Multiple Active Signals.

Report the exception:
1.

Keep a count, etc.

RESIGNAL the same condition which will usually report
the user at a terminal or in a log file.

Change the severity
RESIGt-.AL.

and

SlG~AL a

field

the

condition_value

different condition.

flow of control:
1.

Continue from the signal~ If the signal was issued by
call to L1B~~10P, then LIB$~TOP will exit the image.

unwind to the establisher's caller with establisher
function value from RO and R1 in the mechanism vector.

Unwind to the establisher ~t th~ point of the call which
resulted in the eXQeption. The callee's function value
is taken from HO and R1 in the mechanism vector.

Unwind to
specified
vector.

a specified activation and transfer to a
location with RO and R1 from the mechanism

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VAX-11 System Reference Manual
COt'lPANY CONFIDENTIAL
Condition Handling Facility
~1-Mar-1~ -- Rev 5
Page D-12
REQUEST TU UNWIND

D.Y

REQUEST TO UNW1ND

If the handler decides to unwind, the
calls performs:

handler

any

procedure

success.wlu.v = SYS$uNWlND
( ldepth.rl.r = {handler depth} + 1J,
[new_PC.rlu.r = {return PC}] )
where depth specifies how many pre-signal frames to remove. if depth
is LEQ 0 then nothing is to be unwound. The default is to return from
the establisher.
To unwind to the establisher, the depth from the
call to the handler should be specified.
The argument new_PC
specifies the location to receive control when the unwind is complete.
The function value is a standard success code (SS$_NORMAL), or
indicates the failure "no signal active ll (SS$_~()SIGNAL), Italready
unwinding" (S!:)~_UN~INDING), or "insufficient frames
for
depth"
(SS~_INSFRAME) .
The unwind will happen when the handler returns to the condition
handling facility.
Unwinding is done by scanning back through the
stack and calling each handler which has been associated with a frame.
The handler is calltd with exception SS~_UNwlND to perform any
application specific cleanup. In particular, if the depth specified
includes unwinalng the establisher's frame, then the current handler
will be re-called with this un~ind exception.
The call to the handler is of the same form as described above with
the following values:
signal_args
1

condition_value = SS$_UNwlND
mechanism_args
4

frame
depth
RO
R1

establisher's frame
o (i.e., unwinding self)
RO which unwind will restore
R1 which unwind will restore

After each handler has been called, the
previous frame.

stack

cut

back

the

&ote that the exception vectors are not checked because they are not
being removed.
Any function value from the handler is ignored. In
the unlikely case that the handler wants to specify the value of the
top level Ii function" being unwound, it should modify RO and R1 in the
mechanism vector because they will be restored from the mechanism
argument vector at the end of the unwind.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
D0 NOT COPY
COMPANY CONFIDENTIAL
Condition Handling :li'acility
::)1-Mar-7
Rev 5
Page D-13
tvlULl'lPLE ACTlVE SIGNALS

VAX-11 System Reference Manual

{

D.10

MULTlPLE ACTIVE SIGNALS

A signal is said to be active until the signaler gets control again or
is unwound. It is possible for a signal to occur while a handler or a
procedure it has called is executing. Consider the following example.
For each procedure (A, B, C, ... ) let the handler it establishes be
(Ah, Bh,· Ch, ... ). If A calls B calls C which signals liS" and Ch
resignals, then Bh gets control. If Bh calls X calls Y which signals
"T" the stack is:
<signal 1')
Y
X

Bh
<signal S>
C
B

which was programmed:
A

B ------------------> Bh
C

x
y

<signal T>
The desired .order to search for handlers is Yh, Xh, <Bh)h, Ah. Note
that Ch should not be called because it is a structural descendent of
B.
Eh should not be called again because that would require it to be
recursive. If it were recursive, then handlers could not be coded in
nonrecursive languages such as FORTRAN.
Instead Eh can establish
itself or another procedure as its handler (Bhh).
TO implement this, the following algorithm is used.
As usual, the
primary and secondary exception vectors are checked. Then, however,
the search backward in the process stack is modified. In effect the
stack frames traversed in the first search are skipped over in the
second search. Ihus, the stack frame preceding the first handler up
to and including the frame of the procedure which has established the
handler is skipped. Despite this skipping, depth is not incremented.
The stack frames traversed in the first and second search are skipped
over in a third search, etc. Note that if a handler SIGNALs, it will
not automatically be invoked recursively.
However, if a handler
itself establishes a handler this second handler will be invoked.
Thus, a recursive handler should start by establishing itself. Any
procedures invoked by the handler are treated in the normal way; that
is, exception signaling follows the stack up to the handler.

Copyright(c) 1 </19 Digital Equipment Corp. ,i'1aynard,Mass.
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Condition Handling Facility
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Page D-14
MULT~PLE ACTIV~ ~lGNALS

For proper hierarchical operation, an exception occurring during
execution of a handler established in an exception vector should be
handled by that handler rather than propagating up the activation
stack.
This is the vectored handler's responsibility. It is most
easily accomplished by the vectored handler establishing a catch-all
handler.

D.11

IMPLICATlONS iOR COMPILERS

compiler giving explicit support for condition handling should
allow & handler to access COMMUN or external variables because this
would impose a constraint on the code generated by other compilers
during operations which could trap. For external procedures used as
or by handlers, this rule must be observed by the programmer.

LEnd of Appendix Dj

Page 1

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

VAX-11 Architectural Sub setting -- Rev 5

Specification Status:

Fully approved

Architectural Status:

under EGO control

File:

SRER5.RNu

PDM Ii:

not used

Date:

6-sep-7b

Superseded Specs;

Rev 4

Author:

Hastings

Typist:

Reviewer(s):

Abstract:

Forbes

P. Conklin, D. Cutler, D. Hustvedt, J. Leonard, P. Lipman,
D. Rodgers, S. Rothman, B. Stewart, B. Strecker

Appendix E describes the instructions, and other features of
the architecture which may be omitted or provided as a
customer option in some processor implementations.
These
declslons were originally agreed to by the Pruning Committee
which consisted of: Bob Armstrong, Jega Arulpragasam, Roger
Blair, Ron Brender, Peter Conklin, Dave Cutler, Bruce Delagi,
Roger Gourd, Rich Grove, Tom Hastings, Len Hughes, Herb
Jacobs, Rich Lary, Dave Rodgers, Steve Rothman, Rich Shaw,
Bob Stewart, and Bill Strecker.

Revision History:
Rev /I
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5

Description
Results of pruning meeting
Made names agree with EGO 5
ECOs 12-1($ and April Meeting
ECOs
G_floating and H_floating

Author
Hastings
Hastings
Conklin
Conklin
Bhandarkar

Revised Date
18-Dec-75
11-Mar-76

27-MaY-76
2c-Feb-77
6-Sep-78

Architectural Subsetting
Cheng€' History

Page E-990

6-Sep-" 6 --Rev 5

Rev 4 to Rev 5 :
Add G_floc.ting.
2.

Add H_floating.

Rev J to hev 4 :
',)

EDlTPC ECO.
2.

Packed decimal EGO.

Rev 2 to Rev

•

~--<
..I •

Add i1GVF, 1'10VD to subset

Add CVT{B,~,LJiF,D} to subset

Add ACBF,. ACED to subset

Remove CROPF, CHOPD, POLYF, POLYD

Add CRG as a class

Make EDITN a separate class

'7.

Remove HOVU, lV1ULN4, DIVN4, CVTLU, CVTPU, ASHU

Change names to MOVN, NULN, DIVN, CVTLN, CVTPN, ASHN

Add MOVTUC, MATCHC to character class

10.

Clarify subsetting a class

11.

Remove address break

12.

Document rules on future additions

13.

Note that eRC, tJ10VTUC, MATCHC are not currently
It'irst Machine.

14.

Add POLYF, POLYD

15.

Make MULN, DrVN a separate class

16.

Add SKPG

Rev 1 to Rev 2:
Update names per EGO 5
[End of SRER5.RNO)

committed

for

APPENDIX E
ARCHITECTURAL SUBSETTING

6-Sep-'78

Rev 5

This appendix describes those parts of the VAX-11 architecture which may
be: 1) omitted completely from a processor, or 2) provided to customers
as a processor option. The subsetting of the architecture reflects the
need for certain agreements between hardware and software implementors
in order to be able to trade-off manufacturing
cost,
software
development cost, and performance across all future machines implemented
in the VAX-11 family. It is agreea that the first processor will
implement all of the instructions in the VAX_11 arcbitecture as defined
by April 1976.
These decisions are an attempt to reach a compromise on the following
conflicting hardware and software goals for all processors produced in
the future in the VAX-11 family:

E.1

GOALS

Hardware goal - Permit an implementor of a low end processor to
omit instructions and other features in order to reduce
manufacturing cost without losing the ability to run all of the
system software.
The implementor will have some idea of the
impact on space and time performance of various classes of
software products as he makes his subsetting design decisions.
2.

Software goal - Provide as small a number of classes of
processor instruction sets as possible to reduce software
development costs. In particular a single version of each
compiler should run on all processors in the VAX family. Also
the combination of hardware and a processor specific operating
system kernel will (as required) give the appearance of a
complete architecture on all processors.

Copyright(c) 1~79 Digital Equipment Corp.,l'1aynard,Mass.
DO NOT COPY
VAX-11 System Reference Ivlanual
COLViPANY CONFIDENTIAL
Architectural Subsetting
6-Sep-78 -- Rev 5
Page E-2
DEFINITIONS

E.2

DEFINIT10NS

Kernel i.nstruction Set - The kernel instruction set is that subset of
the VAX-11 architecture ~hich is always present in all processors in the
VAX-11 family.
Subsettable instructions
The subsettable instructions
are
the
instructions in the VAX architecture which processor implementors may
choose: (1) to omit completely, (2) to include as a processor option,
or (3) to include in the basic processor.
Processor option - An implemen~2tion technique whereby a particular
processor is designed to provide customers the ability to purchas~
additional hardware to provide some or all of the omitted instructions
or other processor features.

E.3

KERNEL INSTRUCTION SET

The Kernel instruction set inciudes all
architecture,
except
the
following
instructions:

of
b

the instructions in the
classes
of subsettable

Floating it - NOVF', MNEGF', CVTF'{B, W, L}, CVTtb, W,L 1r', Ct-1PF, TSTF,
ADDF2, ADDF3, SUBF2, SUBF3, MULF2, MULF3, DIVF2, DIVF3, CVTRFL,
EMODF, POLYF, ACBF
2.

Double w - MOVD, MNEGD, CVTD{B,W,L,F}, CVT{B,W,L,F}D, CMPD,
TSTD, ADDD2, ADDD3, SUBD2, SUBD3, MULD2, lViULDj, DIVD2, DIVD3,
CVTRDL, EMODD, POLYD, ACBD

G_floating* - MOVG, t-'ll~EGG, GVTG1.B,W,L,F}, GVTtB,.w,L,F}G, CMPG,
TSTG, ADDG2, ADDG3, SUBG2, SUBG3, MULG2, MULG5, DIVG2, DIVG3,
CVTRGL, EMODG, POLYG, ACBG

H_floating*
MOVH,
MNEGH,
CVTH{B, W,L, F, D,Gj ,
CYT{B,w,L,F,D,GjH,
CMPH, TSTH, ADDH2, ADDHj, SUBM2, SUBH3,
MULH2, MULHj, DIVh2, DIYH:) , CY1'RHL, EMODH, POLYH, ACBh, HOVO,
CLRH, MOVAH, PUSHAH

Cyclic Redundancy Check - eRC

Packed*' - MOYP, CMPP3, CMPP4, ADDP4, ADDP6,
CVTLP, CVTPL, CVTPT, CVT'l'P, CVTPS, CV'I'SP, ASHP

SUBP4,

SUBP6,

Packed Multiply - MULP, DIVP (If packed included
not, then do setup and set FPD).

and

multiply

Edit - EDITPC

and except the following class which may become a
the VAX architecture:

subsettable

part

Copyright (c) 1979 Digital Equipment Corp.,Maynard,tvlass.
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VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Architectural Subsetting
6-Sep-'lb -- Rev 5
Page ~-3
KERNEL INSTRUCTION SET

Character*' - M()V'I'C, MOVTlJC,
SKPC, I'1A'l'CHC

CIvlPC~,

CMPC5, SCANC,

SPANC,

LOCe,

*Note: All forms of the address data type and all forms of context
indexing have been included in the kernel set. In addition, MOVC3 and
MOVe5 are part of the kernel set. NoVe3 is the recommended technique
for moving blocks of data. Using MOVC5 with a zero length source is the
recommended technique for clearing an area of memory.
This means that if any
Each class may only be subset as an entity.
instruction of a class is incluoed, all instructions of that class must
be included.

E.4

GUIDELINES FOR SOFTwARE l1'1PLEMENTORS

E.4.1

Diagnostic Software

Use only the kernel instruction set.

E.4.2

uperating System Kernel

Use only the kernel instruction set. The operating system kernel (as
required) will simulate in software all instructions omitted from a
machine. Thus each processor and processor option has a potentially
different operating system kernel.

E.4.3

System Software And Compiled Code

This category includes all of the rest of the soft~are, namely
compilers, utilities, compiled code, application programs, and operating
system support (e.g., file system, data management, etc.).
Use the
kernel instruction set and the character instructions freely. Use the
instructions in a subset table class only if' they are natural for the
data being operated upon and are used extensively in the program. The
kernel will simulate the missing instructions.
Isolated use
of
subsettable instructions for ad hoc purposes is to be discouraged. For
low end machines after the first we will measure the use of the
character instructions and determine the performance penalty due to
software simulation. No character instructions will be permitted to be
subsetted until the measurements have been done. No software should
avoid using character instructions in anticipation of them being
subsetted" in a future low end machine; otherwise, the performance data
will be biased.

Copyright(c) 1979 Digital Equipment Corp.,tviaynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COlV1PANY CONfi'lDENT1AL
Architectural Subsetting
6-Sep-18 -- Rev 5
Page E-4
GUiDELINES TO HARDWARE IMPLEMENTORS

E.5

GUIDELINES TO HARDWARE IMPLEMENTORS

E.5.1

First VAX_11 Machine

provided
and
no
All instructions in the architecture will be
instructions will be subsettable or provided as processor options.
G_floating and H_floating instructions were added to the architecture
after the first machine was designed a.nd shipped; therefore they will
be offered as options.

E.5.2

Machines After The First

Any or all instructions in each omitted instruction class (classes 1-8)
may be omitted or provided as an option. No kernel instructions may be
omitted or included as an option. If any subsettable instructions are
omitted, the processor implementors are required to provide simulation
routines for omitted instructions. Then quantifiable space, time, and
cost tradeoffs can be made by hardware and software implementors early
in the processor design cycle by measuring existing systems.

E.5.3

Later Additions To The Architecture

Additions to the architecture after April, 1976 t will not necessarily be
in all machines.
Thus, the specification of the instruction must
include the simulation code for older machines.
LEnd of Appendix E)

Page 1

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

VAX-11 Instruction Set and Opcode Assignments -- Rev 16

Specification Status:

Fully approved

Architectural Status:

under ECO control

File:

SRFR16.RNO

PDM I: not used
Date:

25-0ct-78

Superseded Specs:

Rev 15

Author:

Conklin & A.

Typist:

Principe

Reviewer(s):
Abstract:

Helenius

P. Conklin, D. Cutler, D. Hustvedt, J. Leona.rd, P. Lipman,
D. Rodgers, S. Rothman, B. Stewart, B. Strecker

Appendix F describes the format of all of the instructions
including the data type of each operand. It also includes
the opcode assignment of each instruction. This document is
updated
in
parallel
with
every
ECO to the VAX-11
Architecture.

Revision History:
Rev #
Rev 1

Description
Review of Chapters 1-4 SRM
Rev 1 ECO #1
Rev 2
Results of Pruning ECO 112
Rev 3 Chapter 10 ECO #3
Rev 4
Changes to Field, Loop,
and String ECO #4
Rev 5 Name Changes ECO 15
Rev 6
Memory Management ECO #6
Rev 7 Opcode Assignments Added
Rev 8
(ECO 18 - Chapter 6 does not
change this)
Rev 9 Conditional Branch ECO 119
Rev 10 Change to Make Same as SRM
Rev 11 Proofreading Rev 10
Rev 12 CALL ECO 111
Rev 13 Field Instructions ECO 1110
Rev 14 Per April 1-9 Meeting
Rev 15 ECO's
Rev 16 Interlocked queue, Octaword,
G_floating, and H_floating

Author
Hastings

Revised Date
19-Dec-75

Hastings
Rothman
Rodgers

7-Jan-76
9-Ja.n-76
28-Feb-77

Strecker
Hastings
Rodgers

2-Feb-76
22-Jan-76

Strecker
Strecker
Strecker
Gourd
Strecker
Strecker
Strecker

13-Feb-76
26-Feb-76
27-Feb-76
25-Feb-76
16-Mar-76
3-Jun-76
9-Mar-77

Bhandarkar

25-0ct-78

Instruction Set and Opcode Assignments
Change Hi story

25-0ct-78 -- Rev 16 Pa.ge F-990

Rev 15 to Rev 16:
1.

Add 2-byte opcodes for G_floa.ting and H_floating.

Fix CRC destination.

Fix POLYD implied operands.

Add interlocked queue instructions.

Rev 14 to Rev 15:
1.

Change name of EDITN to EDITPC (EDITPC ECO).

Delete option and destination length operands of EDIT
ECO) •

Change from zoned to packed instructions (decimal data ECO).

Add CLRF and CLRD as same a.s CLRL and CLRQ.

Add Rounding to ASHP.

Correct order of field reference on EXTV, etc.

Change operands of POLY Instruction

Add CVT{SP,PS};

Add ADAWI.

change xxN to xxT;

add INDEX.

Rev 13 to Rev 14:
1.

Add MOVQ

Remove CLRF

Add ADDA2, ADDA3, SUBA2, SUBA3

Remove CHOPF, CHOPD

Correct EMOD operands per ECO 18

Remove POLYF, POLYD

Cha.nge MOVP, PUSHP to MOVA, PUSHA

Remove CMPA, DIFA, ADTA, SBFA

Correct conditional branches per ECO 17

10.

Add BBSSI, BBCCI

(EDITPC

Instruction Set and Opcode Assignments
Change History

25-0ct-78 -- Rev 16

Page F-991

11.

Remove MSx, MSPx

12.

Add XFC

13.

Remove ECMA

14.

Add INSQUE, REMQUE

15.

Add MOVTUC, MATCHC

16.

Add CRC per ECO 12

17.

Correct CRC operands

18.

Remove MOVU, CVTLU, CVTPU, ASHU;
CVTPN, ASHN

19.

Remove MULN4, DIVN4;

20.

Change name to EDITN

21.

Add CHMK, CHME, CHMS, CHMU, CHMI

22.

Add PRBPR, PRBPRW

23.

Add LDPC, SVPC

24.

Add MTPR, MFPR

25.

Replace opcode encoding to minimize decode logic (Apr 76)

26.

Change names to LDPCTX, SVPCTX

27.

Cha.nge MT/FPR from .w/rl to .rl

28.

Change queue context from .aq to .ab

29.

Correct FFS/C to .wl

30.

Correct EMOD to mulrx

31.

Correct typo on CLR

32.

Add section on instruction interruptiblility

33.

Change operand names to agree with chapter 4-9

34.

Add mode to PROBER/W and change names

35.

Remove CHMI

36.

Change MOVPSW to MOVPSL

change names to MOVN,

change names to MULN, DIVN

CVTLN,

Instruction Set and Opcode Assignments
Change History

25-0ct-78 -- Rev 16

37.

Remove ADDA, SUBA

38.

HALT and BPT are faults

39.

Add POLYF/D

40.

Add SKPC

41.

Change EMODD to int.wl

42.

Add implicit operands

43.

Change field operand type from .ab to .vb

44.

Change name to BLBS/C

45.

BPT is legal in all modes and on interrupt stack

46.

SVPCTX is legal in kernel mode

47.

Add final encoding (1-Jun-76)

48.

Add CRC destination

49.

Expand .1/0 restriction rules

50.

Allow boot in 110 space

51.

Put {} around implied operands

52.

Add field implied operand on field instructions

53.

Add register implied operands on string and POLY

Page F-992

Rev 12 to Rev 13:
1.

Change operands to EXTV, EXTZV, INSV, CMPV, CMPZV per ECO 10

Change operands of FFC, FFS per ECO 10

Cha.nge operands of BBx, BBxx per ECO 10

Change operands to BLS, BLC per ECO 10

Rev 11 to Rev 12:
1.

Change operand of CALLS per ECO 11

Rev 7 to Rev 11:
1.

Add BHE, BPN

Instruction Set and Opcode Assignments
Change History

25-0ct-78 -- Rev 16

Page F-993

Remove BNEVER

Add BSBB;

Change name to BRB, BRW

Change opcode assignments of above and BLS, BLC, JMP, JSB

change name to BSBW

Rev 5 to Rev 7:
1.

Add opcode assignments;

add CRLF

Rev 4 to Rev 5:
1.

Change name to EMUL, EDIV

Change name to ASHQ

Chs.nge name to MOVP, PUSHP, CMPA, ADTA, SBFA, DIFA

Change name to FFC, FFS

Change ns.me to BR1, BR2

Change name to BLS, BLC

7•

Change na.me to CALLG, RET

Change name to MOVPSW

Change name to EMOD

10.

Change name to MOVC, MOVTC, CMPC, SCANC, SPAN, LOCC

11.

Change name to CMPN, ADDN,
CVTPS, ASHS

12.

Change name to MOVC3, MOVC5, etc.

13.

Change name to EDITC

14.

Change name to MS, MPS

SUBN,

MULN,

DIVN,

CVTNL,

CVTLS,

Rev 1 to Rev 4:
1.

Change operands of INSV, EXTV, EXTZV, CMPV,

BBx, BBxx, 8T, 8F
2.

Remove AVP

Change order of string descriptor

CMPZV,

FFZ,

FFO,

Instruction Set and Opcode Assignments
Change History

25-0ct-78 -- Rev 16

Change order of operands in ACB, AOBLT, SOBGT

[End of SRFR16.RNO]

Page F-994

APPENDIX F
INSTRUCTION SET AND OPCODE ASSIGNMENTS

25-0ct-78 -- Rev 16

F.1

INSTRUCTION OPERAND FORMATS

The format of the instructions is given using the qualified name
convention described in the next section. For the mnemonics {} encloses
a list of data types of which one must be selected. Instructions which
have two forms differing in the number of operands have the number of
operands appended to the opcode as a digit.
For the opera.nds, {}
encloses all implied operands.
See Appendix B, VAX-11 a.ssembler
notation, for a description of when the data type suffix and operand
The order of the instructions is
number suffix ma.y be omitted.
generally that in the SRM.
Instructions
1.

Move
MOV{B,W,L,F,D,G,H,Q,O} src.rx, dst.wx

Push Long
PUSHL src.rl, {-(SP).wl}

Clear
CLR{B,W,L=F,Q=D=G,O=H} dst.wx

4•

Move Negat ed
MNEG{B,W,L,F,D,G,H} src.rx, dst.wx

Move Complemented
MCOM{B,W,L} src.rx, dst.wx

Move Zero-Extended
MOVZ{BW,BL,WL} src.rx, dst.wy

Convert
CVT{B,W,L,F,D,G,H}{B,W,L,F,D,G,H} src.rx, dst.wy
All pairs except BB,WW,LL,FF,DD,GG,HH,DG, and GD

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Instruction Set and Opcode Assignments
25-0ct-78 -- Rev 16
Page F-2
INSTRUCTION OPERAND FORMATS
8.

Convert Rounded
CVTR{F,D,G,H}L src.rx, dst.wl

Compa.re
CMP{B,W,L,F,D,G,H} src1.rx, src2.rx

10.

Test
TST{B,W,L,F,D,G,H} src.rx

11.

Add 2 Operand
ADD{B,W,L,F,D,G,H}2 add.rx, sum.mx

12.

Add 3 Operand
ADD{B,W,L,F,D,G,H}3 add1&rx, add2.rx, sum.wx

13.

Increment
INC{B,W,L} sum.mx

14.

Add With Carry
ADWC add.rl, sum.ml

15.

Add Aligned Word
ADAWI add.rw, sum.mw

16.

Subtract 2 Operand
SUB{B,W,L,F,D,G,H}2 sub.rx, dif.mx

17.

Subtract 3 Operand
SUB{B,W,L,F,D,G,H}3 sub.rx, min.rx, dif.wx

18.

Decrement
DEC{B,W,L} dif.mx

19.

Subtract With Carry
SBWC sub.rl, dif.ml

20.

Multiply 2 Operand
MUL{B,W,L,F,D,G,H}2 mulr.rx, prod.mx

21.

Multiply 3 Operand
MUL{B,W,L,F,D,G,H}3 mulr.rx, muld.rx, prod.wx

22.

Extended Multiply
EMUL mulr.rl, muld.rl, add.rl, prod.wq

23.

Divide 2 Operand
DIV{B,W,L,F,D,G,H}2 divr.rx,

24.
25.

Divide 3 Operand
DIV{B,W,L,F,D,G,H}3

7
~uo.mx

divr.rx, divd.rx, quo.wx

Extended Divide
EDIV divr.rl, divd.rq, quo.wl, rem.wl

Copyright(c) 1979' Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manua,l
COMPANY CONFIDENTIAL
Instruction Set and Opcode Assignments
25-0ct-78 -- Rev 16
Page F-3
INSTRUCTION OPERAND FORMATS
26.

Arithmetic Shift
ASH{L,Q} cnt.rb, src.rx, dst.wx

27.

Bit Test
BIT{B,W,L} mask.rx, src.rx

28.

Bit Set 2 Operand
BIS{B,W,L}2 mask.rx, dst.mx

29.

Bit Set 3 Operand
BIS{B,W,L}3 mask.rx, sre.rx, dst.wx

30.

Bit Clear 2 Operand
BIC{B,W,L}2 mask.rx, dst.mx

31.

Bit Clear 3 Operand
BIC{B,W,L}3 mask.rx, src.rx, dst. wx

Exclusive OR 2 Operand
mask.rx, dst.mx

33.

Exclusive OR 3 Operand
XOR{B,W,L}3 mask.rx, src.rx, dst.wx

34.

Rotate Long
ROTL ent.rb, sre.rl, dst. wI

35.

Extended Modulus
EMOD{F,D} mulr.rx, mulrx.rb, muld.rx, int.wl, fract.wx
EMOD{G,H} mulr.rx, mulrx.rw, mUlde rx, int.wl, fraet.wx

36.

Polynomial Evaluation F_floating
POLYF arg.rf, degree.rw, tbladdr.ab, {RO-3.wl}

37.

Polynomial Evaluation D_floating
POLYD arg.rd, degree.rw, tbladdr.ab, {RO-5.wl}

38.

Polynomial Evaluation G_floating
POLYG arg.rg, degree.rw, tbladdr.ab, {RO-5.wl}

39.

Polynomial Evaluation H_floating
POLYH arg.rh, degree.rw, tbladdr.ab,
{RO-5.wl,-16(SP):-1(SP).wb}

40.

Move Address
MOVA{B,W,L=F,Q=D=G,O=H} sre.ax, dst.wl

41.

Push Address
PUSHA{B,W,L=F,Q=D=G,O=H} src.ax, {-(SP).wl}

42.

Index
1
INDEX subscript.rl, low.rl, high.rl, size.rl, indexin.rl,
indexout.wl

32.

XOR{B,W~L}2

Copyright(c) 1979 Digital Equipment Corp. ,Maynard,Ma.ss.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Instruction Set and Opcode Assignments
25-0ct-78 -- Rev 16
Page F-4
INSTRUCTION OPERAND FORMATS
43.

Extract Field
EXTV pos.rl, size.rb, base.vb, {field.rv}, dst.wl

44.

Extract Zero-Extended Field
EXTZV pos.rl, size.rb, base.vb, {field.rv}, dst.wl

45.

Insert Field
INSVsra.rl, pos.rl, size.rb, ba.se.vb, {field.wv}

46.

Compare Field
CMPV pos.rl, size.rb, base.vb, {field.rv}, src.rl

47.

Compare Zero-Extended Field
CMPZV pos.rl, size.rb, base.vb, {field.rv}, src.rl

48.

Find First
2
FF{S,C} startpos.rl, size.rb, base.vb, {field.rv}, findpos.wl

49.

Conditional Branch
B{condition} displ.bb

Condition

Name

LSS
LEO
EQL, EQLU
NEQ, NEQU
GEQ
GTR
LSSU, CS

Less Than
Less Than or Equal
Equal, Equal Unsigned
Not Equal, Not Equal Unsigned
Greater Than or Equal
Greater Than
Less Than Unsigned, Carry Set
Less Than or Equal Unsigned
Greater Than or Equal Unsigned,
Carry Clear
Greater Than Unsigned
Overflow Set
Overflow Clea.r

LEQ~

GEQU, CC
GTRU
VS
VC

wor~~DiSPlacement

50.

Branoh With {Byte,
BR{B,W} displ.bx

51.

Jump
JMP dst.ab

52.

Branch on Bit
BB{S,C} pos.rl, base. vb, displ.bb, {field.rv}

53.

Branch on Bit (and modify without interlock)
BB{S,C}{S,C} pos.rl, base. vb, displ.bb, {field.mv}

54.

Branch on Bit (and,modify) Interlocked
BB{SS,CC}I pos.rl, base.vb, displ.bb, {field.mv}

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Instruction Set and Opcode Assignments
25-0ct-78 -- Rev 16
Page F-5
INSTRUCTION OPERAND FORMATS
55.

Branch on Low Bit
BLB{S,C} src.rl, displ.bb

56.

Add Compare and Branch
7
ACB{B,W,L,F,D,G,H} limit.rx, add.rx, index.mx, displ.bw
Compare is LE on positive add, GE on negative
add.

57.

Add One and Branch Less Than or Equal
AOBLEQ limit.rl, index.ml, displ.bb

58.

Add One and Branch Less Than
AOBLSS limit.rl, index.ml, displ.bb

59.

Subtract One and Branch Greater Than or Equal
SOBGEQ index.ml, displ.bb

60.

Subtract One and Branch Greater Than
SOBGTR index.ml, displ.bb

61.

Case
3
CASE{B,W,L} selector.rx, base.rx, limit.rx, displ.bw-list

62.

Branch to Subroutine With {Byte, wond~DisPlacement
BSB{B,W} displ.bx, {-(SP).wl}

63.

Jump to Subroutine
JSB dst.ab, {-(SP).wl}

64.

Return from Subroutine
RSB {(SP)+.rl}

65.

Call Procedure with General Argument List
CALLG arglist.ab, dst.ab, {-(SP).w*}

66.

Call Procedure with Stack Argument List
CALLS numarg.rl, dst.ab, {-(SP).w*}

67.

Return from Procedure
RET {(SP)+.r*}

68.

Breakpoint Fault
BPT {-(KSP).w*}

69.

Halt
HALT {-(KSP).w*}
~alts in Kernel mode, faults otherwise.
Assigned opcode O.

70.

Push Registers
PUSHR mask.rw, {-(SP).w*}

Copyright(c) 1979 Digital Equipment Corp.,Ma.ynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Instruction Set and Opcode Assignments
25-0ct-78 -- Rev 16
Page F-6
INSTRUCTION OPERAND FORMATS
71.

Pop Registers
POPR mask.rw, {(SP)+.r*}

72.

Move from PSL
MOVPSL dst.wl

73.

Bit Set PSW
BISPSW mask.rw

74.

Bit Clear PSW
BICPSW mask.rw

75.

No Operation
NOP

76.

Extended Function Call
XFC {unspecified operands}

77.

Insert Entry in Queue
INSQUE entry.ab, pred.ab

78.

Insert Entry into Queue at Head, Interlocked
INSQHI entry.ab, header.aq

79.

Insert Entry into Queue at Tail, Interlocked
INSOTI entry.ab, header.aq

80.

Remove Entry from Queue
REMQUE entry.ab, addr.wl

81.

Remove Entry from Queue at Head, Interlocked
REMQHI header.aq, addr.wl

82.

Remove Entry from Queue at Tail, Interlocked
REMQTI header.aq, addr.wl

83.

Move Cha.racter 3 Operand
MOVC3 len.rw, srcaddr.ab, dstaddr.ab, {RO-5.wl}

84.

Move Chara.cter 5 operand
1
MOVC5 srclen.rw, srcaddr.ab,.fill.rb, dstlen.rw, dstaddr.ab,
{RO-5.wl}

85.

Move Translated Characters
1
MOVTC srclen.rw, srcaddr.ab, fill.rb, tbladdr.ab, dstlen.rw,
dstaddr.ab, {RO-5.wl}

86.

Move Translated Until Character
1
MOVTUC srclen.rw, srcaddr.ab, e~c.rb, tbladdr.ab, dstlen,rw,
dstaddr.ab, {RO-5.wl}

87.

Compare Characters 3 Operand
CMPC3 len.rw, src1addr.ab, src2addr.ab, {RO-3.wl}

Compare Characters 5 Operand
CMPC5 src1len.rw, src1addr.ab, flll.rb, src2len.rw,
src2addr.ab, {RO-3.wl}

89.

Scan Characters
SCANC len.rw, addr.ab, tbladdr.ab, mask.rb, {RO-3.wl}

90.

Span Characters
SPANC len.rw, addr.ab, tbladdr.ab, mask.rb, {RO-3.wl}

91.

Locate Character
LOCC cha.r.rb, len.rw, addr.ab, {RO-l.wl}

92.

Skip Character
SKPC char.rb, len.rw, addr.ab, {RO-l.wl}

93.

Match Characters
MATCHC lenl.rw, addrl.ab, len2.rw, addr2.ab, {RO-3.wl}

94.

Cyclic Redundancy Check
CRC tbl.ab, inicrc.rl, strlen.rw, stream.ab, {RO-3.wl}

95.

Move Packed
MOVP len.rw, srcaddr.ab, dstaddr.ab, {RO-3.wl}

96.

Compare Packed 3 Operand
CMPP3 len.r~, src1addr.ab, src2addr.ab, {RO-3.wl}

97.

Compare Packed 4 Operand
1
CMPP4 srcllen.rw, srcladdr.ab, src2len.rw, src2addr.ab,
{RO-3.wl}

98.

Add Packed 4 Operand
1
ADDP4 addlen.rw, addaddr.ab, sumlen.rw, sumaddr.ab, {RO-3.wl}

99.

Add Packed 6 Operand
1
ADDP6 addllen.rw, addladdr.ab, add2len.rw, add2addr.ab,
sumlen.rw, sumaddr.ab, {RO-5.wl}

100.

Subtract Packed 4 Operand
1
SUBP4 sublen.rw, subaddr.ab, diflen.rw, difaddr.ab, {RO-3.wl}

101.

Subtract Packed 6 Operand
SUBP6 sublen.rw, subaddr.ab, minlen.rw, minaddr.ab,
diflen.rw, difaddr.ab, {RO-5.wl}

102.

Multiply Packed
MULP mulrlen.rw, mulraddr.ab, muldlen.rw, muldaddr.ab,
prodlen.rw, prodaddr.ab, {RO-5.wl}

103.

Divide Packed
DIVP divrlen.rw, divraddr.ab, divdlen.rw, divdaddr.ab,
quolen.rw, quoaddr.ab, {RO-5.wl, -16(SP):-1(SP).wb}

Convert Long to Packed
CVTLP src.rl, dstlen.rw, dstaddr.ab, {RO-3.wl}

105.

Convert Packed to Long
CVTPL srclen.rw, srcaddr.ab, {RO-3.wl}, dst.wl

106.

Convert Packed to Trailing
2
Convert Trailing to Packed
CVT{PT,TP} srclen.rw, srcaddr.ab, tbladdr.ab, dstlen.rw,
dstaddr.ab, {RO-3.wl}

107.

Convert Packed to Leading Separate
2
Convert Leading Separate to Packed
CVT{PS,SP} srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab,
{RO-3.wl}

108.

Arithmetic Shift and Round Packed
ASHP cnt.rb, srclen.rw, srcaddr.ab, round.rb, dstlen.rw,
dstaddr.ab, {RO-3.wl}

109.

Edit Packed to Cha.racter String
1
EDITPC srclen.rw, sreaddr.ab, pattern.ab, dstaddr.ab, {RO-5.wl}

110.

Probe {Read, Write} Accessability
PROBE{R,W} mode.rb, len.rw, ba.se.ab

111.

Change Mode
CHM{K,E,S,U} param.rw, {-(ySP).w*}
Illegal on interrupt stack.
Where y=MINU(x, PSL<eurrent_mode»

112.

Return from Exception or Interrupt
REI {(SP)+.r*}

113.

Load Process Context
LDPCTX {PCB.r*, -(KSP).w*}
Legal only on interrupt stack.

114.

Save Process Context
SVPCTX {(SP)+.r*, PCB.w*}
Legal only in Kernel mode.

115.

Move To Process Register

MTPR sre.rl, proereg.rl
Legal only in Kernel mode.
116.

Move From Processor Register
MFPR proereg.rl, dst.wl
Legal only in Kernel mode.

Total

304

OPERAND SPECIFIER NOTATION

The standard VAX notation for operand specifiers is:
<name>.<access type><data type>
where:
1.

Name is a suggestive name for the operand in the
context of the instruction. It is the capitalized
name of a register or block for implied operands.

Access type is a letter denoting the operand
specifier access type.
a - Calculate the effective address of the
specified operand. Address is returned in a
pointer which is the actual instruction operand.
Context of address calculation is given
by data type given by <data type>.
b - No operand reference. Operand specifier is
branch displacement. Size of branch
displacement is given by <data type>.
m - operand is modified (both rea,d and written)
r - operand 1s read only
v - if not "Rn", same as a. If "Rn", R[n+l]'R[n).
w - operand is written only

Data type is a letter denoting the data type of the
operand
b - byte
d - D_floating
f - F_floating
g - G_floating
h - H_floating
I - longword
o - octaword
Q - Quadword
v - field (used only on implied operands)
w - word
x - first data type specified by instruction
y - second data type specified by instruction
* - multiple longwords (used only on implied operands)

For names, the following names and abbreviations are used:
1.

add - addend

addr - address

arglist - ,argument list

base - base

char - character

cnt - count

dif - difference

displ - displacement

divd - dividend

10.

divr - divisor

11.

dst - destination

12.

entry - entry

13.

esc - escape

14.

fill - fill

15.

findpos - find position

16.

fract - fraction

17.

index - index

18.

inicrc - initial crc

19.

int - integer

20.

len - length

21.

limit - limit

22.

mask - mask

23.

min - minuend

24.

muld - multiplicand

25.

muIr - multiplier

26.

mulrx - multiplier extension

27.

numarg - number of arguments

28.

option - option

29.

param - parameter

pos - position

31.

pred - predecessor

32.

procreg - internal processor register

33.

prod - prod uc t

34.

quo - quotient

35.

rem - remainder

36.

selector - selector

37.

size - size

38.

src - source

39.

startpos - starting position

40.

stream - stream

41.

strlen - string length

42.

sub - subtrahend

43.

sum - sum

44.

tbl - table

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-ll System Reference Manual
COMPANY CONFIDENTIAL
Instruction Set and Opcode Assignments
25-0ct-78 -- Rev 16
Page F-12
OPCODE ASSIGNMENTS
F.3

OPCODE ASSIGNMENTS

SINGLE BYTE OPCODES
Mnemonic

Binary

Hex

Mnemonic

00000000 00
00000001 01
00000010 . 02
00000011 03
00000100 04
00000101 05
00000110 06
00000111 07

HALT
NOP
REI
BPT
RET
RSB
LDPCTX
SVPCTX

00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111

20
21
22
23
24
25
26
27

ADDP4
ADDP6
SUBP4
SUBP6
CVTPT
MULP
CVTTP
DIVP

00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111

08
09
OA
OB
OC
OD
OE
OF

CVTPS
CVTSP
INDEX
CRC
PROBER
PROBEW
INSQUE
REMQUE

00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111

28
29
2A
2B
2C
2D
2E
2F

MOVC3
CMPC3
SCANC
SPANC
MOVC5
CMPC5
MOVTC
MOVTUC

00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111

10
11
12
13
14
15
16
17

BSBB
BRB
BNEQ,BNEQU
BEQL,BEQLU
BGTR
BLEQ
JSB
JMP

00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111

30
31
32
33
34
35
36
37

BSBW
BRW
CVTWL
CVTWB
MOVP
CMPP3
CVTPL
CMPP4

00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111

18
19
lA
lB
lC
1D
lE
IF

BGEQ
BLSS
BGTRU
BLEQU
BVC
BVS
BGEQU,BCC
BLSSU,BCS

00111000
00111001
00111010
00111011
00111100
00111101
00111110
00111111

38
39
3A
3B
3C
3D
3E
3F

EDITPC
MATCHC
LOCC
SKPC
MOVZWL
ACBW
MOVAW
PUSHAW

Binary

Hex

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-l1 System Reference Manual
COMPANY CONFIDENTIAL
Instruction Set and Opcode Assignments
25-0ct-78 -- Rev 16
Page F-13
OPCODE ASSIGNMENTS

Binary

Hex

Mnemonic

Binary

Hex

Mnemonic

01000000
01000001
01000010
01000011
01000100
01000101
01000110
01000111

40
41
42
43
44
45
46
47

ADDF2
ADDF3
SUBF2
SUBF3
MULF2
MULF3
DIVF2
DIVF3

01100000
01100001
01100010
01100011
01100100
01100101
01100110
01100111

60
61
62
63
64
65
66
67

ADDD2
ADDD3
SUBD2
SUBD3
MULD2
MULD3
DIVD2
DIVD3

01001000
01001001
01001010
01001011
01001100
01001101
01001110
01001111

48
49
4A
4B
4C
4D
4E
4F

CVTFB
CVTFW
CVTFL
CVTRFL
CVTBF
CVTWF
CVTLF
ACBF

01101000
01101001
01101010
01101011
01101100
01101101
01101110
01101111

68
69
6A
6B
6C
6D
6E
6F

CVTDB
CVTDW
CVTDL
CVTRDL
CVTBD
CVTWD
CVTLD
ACBD

01010000
01010001
01010010
01010011
01010100
01010101
01010110
01010111

50
51
52
53
54
55
56
57

MOVF
CMPF
MNEGF
TSTF
EMODF
POLYF
CVTFD
RESERVED to DEC

01110000
01110001
01110010
01110011
01110100
01110101
01110110
01110111

70 MOVD
71 CMPD
72 MNEGD
73 TSTD
74 EMODD
75 POLYD
76 CVTDF
77 RESERVED to DEC

01011000
01011001
01011010
01011011
01011100
01011101
01011110
01011111

58
59
5A
5B
5C
5D
5E
5F

ADAWI
01111000 78 ASHL
01111001 79 ASHQ
RESERVED to DEC
RESERVED to DEC
01111010 7A EMUL
RESERVED to DEC
01111011 7B EDIV
INSQHI
01111100 7C CLRQ,CLRD,CLRG
INSQTI
01111101 7D MOVQ
REMQHI
01111110 7E MOVAQ, MOVAD, MOVAG
REMQTI
01111111 7F PUSHAQ,PUSHAD,PUSHAG

Binary

Hex

Mnemonic

Binary

Hex

Mnemonic

10000000
10000001
10000010
10000011
10000100
10000101
10000110
10000111

80
81
82
83
84
85
86
87

ADDB2
ADDB3
SUBB2
SUBB3
MULB2
MULB3
DIVB2
DIVB3

10100000
10100001
10100010
10100011
10100100
10100101
10100110
10100111

AO
A1
A2
A3
A4
A5
A6
A7

ADDW2
ADDW3
SUBW2
SUBW3
MULW2
MULW3
DIVW2
DIVW3

10001000
10001001
10001010
10001011
10001100
10001101
10001110
10001111

88
89
8A
8B
8C
8D
8E
8F

BISB2
BISB3
BICB2
BICB3
XORB2
XORB3
MNEGB
CASEB

10101000
10101001
10101010
10101011
10101100
10101101
10101110
10101111

A8
A9
AA
AB
AC
AD
AE
AF

BISW2
BISW3
BICW2
BICW3
XORW2
XORW3
MNEGW
CASEW

10010000
10010001
10010010
10010011
10010100
10010101
10010110
10010111

90
91
92
93
94
95
96
97

MOVB
CMPB
MCOMB
BITB
CLRB
TSTB
INCB
DECB

10110000 BO
10110001 B1
10110010 B2
10110011 B3
10110100 B4
10110101 B5
10110110 B6
10110111 B7

MOW
CMPW
MCOMW
BITW
CLRW
TSTW
INCW
DECW

10011000
10011001
10011010
10011011
10011100
10011101
10011110
10011111

98
99
9A
9B
9C
9D
9E
9F

CVTBL
CVTBW
MOVZBL
MOVZBW
ROTL
ACBB
MOVAB
PUSHAB

10111000 B8
10111001 B9
10111010 BA
10111011 BB
10111100 BC
10111101 BD
10111110 BE
10111111 BF

BISPSW
BICPSW
POPR
PUSHR
CHMK
CHME
CHMS
CHMU

Binary

Hex

Mnemonic

Binary

Hex

Mnemonic

11000000
11000001
11000010
11000011
11000100
11000101
11000110
11000111

CO
C1
C2
C3
C4
C5
C6
C7

ADDL2
ADDL3
SUBL2
SUBL3
MULL2
MULL3
DIVL2
DIVL3

11100000 EO
11100001 E1
11100010 E2
11100011 E3
11100100 E4
11100101 E5
11100110 E6
11100111 E7

BBS
BBC
BBSS
BBCS
BBSC
BBCC
BBSSI
BBCCI

11001000
11001001
11001010
11001011
11001100
11001101
11001110
11001111

C8
C9
CA
CB
CC
CD
CE
CF

BISL2
BISL3
BICL2
BICL3
XORL2
XORL3
MNEGL
CASEL

11101000
11101001
11101010
11101011
11101100
11101101
11101110
11101111

E8
E9
EA
EB
EC
ED
EE
EF

BLBS
BLBC
FFS
FFC
CMPV
CMPZV
EXTV
EXTZV

11010000
11010001
11010010
11010011
11010100
11010101
11010110
11010111

DO
D1
D2
D3
D4
D5
D6
D7

MOVL
CMPL
MCOML
BITL
CLRL,CLRF
TSTL
INCL
DECL

11110000 FO
11110001 ;~ 1
11110010 F2
11110011 F3
11110100 F4
11110101 F5
11110110 F6
11110111 F7

INSV
ACBL
AOBLSS
AOBLEQ
SOBGEQ
SOBGTR
CVTLB
CVTLW

11011000
11011001
11011010
11011011
11011100
11011101
11011110
11011111

D8
D9
DA
DB
DC
DD
DE
DF

ADWC
SBWC
MTPR
MFPR
MOVPSL
PUSHL
MOVAL,MOVAF
PUSHAL,PUSHAF

11111000 F8
'1'1100' F9
1'1'1010 FA
11111011 FB
11111100 FC
11111101 FD
11111110 FE
11111111 FF

ASHP
CVTLP
CALLG
CALLS
XFC
ESCD to DEC
ESCE to DEC
ESCF to DEC

Copyright(c) 1979 Digital Equipment. Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Instruction Set and Opcode Assignments
25-0ct-78 -- Rev 16 Page F-16
OPCODE ASSIGNMENTS

TWO BYTE OPCODES

Hex

Mnemonic

OOFD
to
31FD

RESERVED to DIGITAL

32FD

CVTDH

34FD
to
3FFD

RESERVED to DEC

Hex

Mnemonic

33FD

CVTGF

/40FD
41FD
..- 42FD
/43FD
/44FD
<./·.45FD
/~ 46FD
47FD

ADDG2
ADDG3
SUBG2
SUBG3
MULG2
MULG3
DIVG2
DIVG3

60FD
//61FD
62FD
·//63FD
.-- 64FD
j/65FD
../·66FD
67FD

ADDH2
ADDH3
SUBH2
SUBH3
MULH2
MULH3
DIVH2
DIVH3

,/ 48FD
/49FD
/4AFD
/4BFD
4CFD
4DFD
4EFD
4FFD

CVTGB
CVTGW
CVTGL
CVTRGL
CVTBG
CVTWG
CVTLG
ACBG

68FD
69FD
6AFD
/'6BFD
6CFD
6DFD
6EFD
6FFD

CVTHB
CVTHW
CVTHL
CVTRHL
CVTBH
CVTWH
CVTLH
ACBH

'e'/

Copyright(c) 1979 Digital Equipment Corp. ,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Instruction Set and Opcode Assignments
25-0ct-78 -- Rev 16 Page F-17
OPCODE ASSIGNMENTS

55FD
56FD
51FD

MOVG
CMPG
MNEGG
TSTG
EMODG
POLYG
CVTGH
RESERVED to DEC

--70FD
,//71FD
,,·/72FD
/"'73FD
,- 74FD
75FD
/76FD
71FD

MOVH
CMPH
MNEGH
TSTH
EMODH
POLYH
CVTHG
RESERVED to DEC

58FD
59FD
5AFD
5BFD
5CFD
5DFD
5EFD
5FFD

RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC

18FD
19FD
7AFD
7BFD
1CFD
1DFD
7EFD
7FFD

RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
CLRH,CLRO
MOVO
MOVAH,MOVAO
PUSHAH,PUSHAO

80FD
to
91FD

RESERVED to DIGITAL

98FD

CVTFH

99FD

CVTFG

9AFD
to
F5FD

RESERVED to DIGITAL
F7FD

CVTHD

F8FD
to
FCFF

RESERVED to DIGITAL

FDFF

aUGL (used by VMS for BUGCHECK) FEFF

BUGW

FFFF

RESERVED for all time

/50FD
c/51FD
", 52FD
,·/'53FD
/~54FD

",/ F6FD

CVTHF

INSTRUCTIONS USABLE TO REFERENCE I/O SPACE

Some of the instructions are not usable to
reasons for this are:

reference

I/O

space.

The

String instructions are restartable via PSL(FPD)

The instruction is not in the kernel set

The PC, SP, or PCBB can not point to I/O space

I/O space does not support operand types of quad, floating,
field, or queue; 'nor can the position, size, length, or base
of them be from I/O space

The instruction may be interruptible because it is
a slow instruction in some implementations

Only instructions with a maximum of one modify or write
The destination must be the last
destination can be used.
operand

potentially

In any case, the programmer is responsible for ensuring that any memory
reference to I/O space is in an instruction which ca.n not take an
exception after the first I/O space reference. This includes deferred
references to I/O space.
Instructions for which any explicit operand can be in I/O space:
MOV{B,W,L}, PUSHL, CLR{B,W,L}, MNEG{B,W,L}, MCOM{B,W,L}, MOVZ{BW,BL,WL},
CVT{BW,BL,WB,WL,LB,LW}, CMP{B,W,L}, TST{B,W,L}, ADD{B,W,L}2,
ADD{B,W,L}3, ADAWI, INC{B,W,L}, ADWC, SUB{B,W,L}2, SUB{B,W,L}3,
DEC{B,W,L}, SBWC, BIT{B,W,L}, BIS{B,W,L}2, BIS{B,W,L}3, BIC{B,W,L}2,
BIC{B,W,L}3, XOR{B,W,L}2, XOR{B,W,L}3, MOVA{B,W,L}, MOVAQ, PUSHA{B,W,L},
PUSHAQ, CASE{B,W,L}, MOVPSL, BISPSW, BICPSW, CHM{K,E,S,U} PROBE{R,W},
MTPR, MFPR
Instructions for which all operands except the branch
be in I/O space:

displacement

can

BLB{S,C}
Instruction for which some operand can be in I/O space:
XFC
REMQUE

(depending on implementation)
addr (destination)

Notwithstanding the above rules, it is possible for a specific hardware
implementation to execute macro code from the I/O space and/or to allow
the stack or PCB to be in I/O space. This might, for example, be used
a.s part of the bootstrap process. If this is done, then it is valid for
software to transfer to this code.

Copyright(c) 1919 Digital Equipment Corp. ,Maynard ,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Instruction Set and Opcode Assignments
25-0ct-18 -- Rev 16 Page F-19
INSTRUCTIONS USABLE TO REFERENCE 1/0 SPACE
\ For reference, instructions were discarded as follows:
1.

String: MOVC3/5, MOVTC, MOVTUC, CMPC3/5, SCANC, SPANC, LOCC,
SKPC, MATCHC, CRC, MOVP, CMPP3/4, ADDP4/6, SUBP4/6, MULP, DIVP,
CVTLP, CVTPL, CVTPT, CVTTP, CVTPS, CVTSP, ASHP, EDITPC

not in kernel set: MOV{F,D,G,H}, MNEG{F,D,G,H},
CVT{B,W,L,F,D,G,H}{F,D,G,H}, CVT{F,D,G,H}{B,W,L,F,D,G,H},
CVTR{F,D,G,H}L, CMP{F,D,G,H}, TST{F,D,G,H}, ADD{F,D,G,H}2,
ADD{F,D,G,H}3, SUB{F,D,G,H}2, SUB{F,D,G,H}3, MUL{F,D,G,H}2,
MUL{F,D,G,H}3, DIV{F,D,G,H}2, DIV{F,D,G,H}3, EMOD{F,D,G,H},
. POLY{F,D,G,H}, ACB{F,D,G,H}

PC, SP, PCBB not in 1/0 space and instruction has no other
operands: Bxxx, BRB/W, JMP, BSBB/W, JSB, RSB, RET, BPT, REI,
HALT, NOP, LDPCTX, SVPCTX

operand types: MOVQ, CLRQ, ASHQ, INSQUE, BB{S,C},
BB{S,C}{S,C}, BB{SS,CC}I

slow: MUL{B,W,L}2, MUL{B,W,L}3, EMUL, DIV{B,W,L}2,
DIV{B,W,L}3, EDIV, ASHL, ROTL, EXTV, EXTZV, INDEX, INSV, CMPV,
CMPZ V, FFSI C, CALLG /S·, PUSHR, POPR

modify or write operand must be last:
AOBLSS, SOBGEQ, SOBGTR

(End of Appendix F)

ACB{B,W,L}, AOBLEQ,

APPENDIX G

Unwritten

DIGITAL

EGUIPMENT

CORPORATION

Digital Equipment Corporation COl:4fANY CONflDENT1AL

Title:

VAX-11

1'1ul tiprecision Arithmetic --Rev 4

Specification Status:

Fully approved

Architectural Status:

under ECO control

};4'i Ie;

Page 1

SRHR4. RNO

PDN H: not used
Date: 21-Mar-77
Superseded Specs:
Author:

Conklin

Typist:

Call

Reviewer(s):

Abstract:

P. Conklin,
P. Lipman,
.B. ~trecker

D. Cutler,

D. Rodgers,

S. Rothman,

Hl,.lst~~edt,

Leonard~

B. Stewart,

Appendix H sholNS ho\o.l to use th~ instruotion set to perform
general multiprecision integer aritmnetic. In practice,
these algorithIns would be tuned to
handle
specific
environments such as variable precision.

Revision History:
hev.1i
Rev 3
Rev 4

Description
uriginal
Typos

Author

Revised Date

Conklin

12-May-'l6
21 ....Mar-7'1

Conklin

Multiprecision Arithmetic
Change History

21-Mar-11 -- Rev 4

Rev 3 to Rev 4:

Rev 1

Typos~

Correct order of looping operands.

to Rev 3 :
1•

'Orignal cr'eation

LEND OF APPENDIX H)
[End of' SRHR4.HNO]

Page H-990

APPENDIX H

MULTIPRECISION ARITHMETIC

21-Mar-17 -- Rev 4

H. ,

OVERVIEW

Multiprecision integers are stored as a sequence of consecutive bytes
in memory.
'I'hey can be thought 0 f as a set 0 f N consecutive
longwords. The sequence is a two's complement representation with bit
31 of the highest longword as the sign. Arithmetic is performed
without integer overflow trapping using the ADWC, SBWC, EMUL, -and EDIV
instructions.
Low order components are treated as unsigned positive
integers with the C condition code containing the carry.
If the V
condition code is set after computing the high order result, then the
result overflowed. No attempt is made to set the Z condition code
correctly.
of this section, the data type is
"M" for
Each of the integer arithmetic instructions is
composed as a pattern. In all cases, N is the common length of the
operands in longwords.
For

the

purpose

multipr~cision.

H.2

1 $:

ADDM2 ADD, SUM

BICPSW
CLRL
ADWC
AOBLSS
BVS

;clear carry and integer overflow
''''X21
RO
;clear loop index
ADDlRO),SUM[HO] ;add including carry
fj!,~ , RO, , 1 !j)
;loop over vector
overflow
;branch if Qverflow

Copyright(c) 1 ';;79 Digital Equipment Corp. ,Maynard,Nass.
DO NOT CQP~
VAX-11 System ReferEnce Manual
COMPANY CONFIOENTIAL'
Multiprecision Arithmetic
21-Mar-11 -- Hev 4
Page B-2
ADDH:) ADD, AUU, SUM

1 $:

BICPS\t.
CLRL
N0VL
ADwC

. AObLSS
BVS

h.4

SijB~2 ~DB,DlF

BICP~W
¢:1 ..,.

CLltL
'::;BwC
AuBL~S

BV;:)

H' • h:>

1 c;: Ojo'-

fr"X21
;clear carry and integer overflow
HO
;cleQr loop index
ADDlROj,SUMLROj ;move addend to result
AUG[hO] ,SUiVl(ROJ ;a~d inoluding carry
jloop over vecter
tiN, RO, 1 $
overflow
; branch if' overflow

; clear cat'ry and integer OVE:rflOw
;clear loop index
SUb[ROJ ,DIF'LRO] ;subtract including borrow
1H'4 ,HO, 1$
;loop over vector
ovprflow
; branch if overflow
tl-"X21

SUBM5 SUB,M1N,DIF
Bl.CPSw
CLRL
HOVL
S:&~C

ACBLSS
BVS

;clear carry and integer overflow
;clear loop index
SUBlRO j, D~£i'LRO J ;mov€ ~ubtrahena to result
f-'llNLROJ,DIFlROJ ;subtract inclUding borrow
ifN, HO, 1~,
;loop over veotor
overflow
;branch if overflow
t("X21

Copyright(c) 19'/9 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Me.nual
COMPANY CONfIDENTIAL
Multiprecision Arithmet~c
21"",Mar-77 -- Rev 4
Page h-3
EMU~M MULR,MULD,PROD
H.6

EtvlULtv! MULR, b1ULD, PROD

6lCPSW
C~RL

CL,RQ

1$:

2$:

3$:

MOVL
IwlOVL
CLRL

MOVL
COMPL
BLEQ
fvluVL
SUbL3
~MUL

l'Sl'L

BGEQ
ADDL2
4$:

1'Sl'L
BGEQ

ADDL2
5~:

ADDL~

ADwC
Al)WC

AOBLEQ

aRB
6$· :
7$:

SOBGEQ
AOBLEQ
i'10VL
l'STL

BGEQ
CLRL
8$;

SB~C

9$:

TS1'L

10$:

BICPSw
CLRL
SBwC
AOBLEQ
TSTL

AOaL~Q

BGEQ'

gA X20
R4
R2
R2,PRODLH4]
R3,R2
R3

;clear integer overflow
;clear destination loop index
;clear temporary accumulator
;start result with carry sum
;adjust carry
;clear excess carry
R4,R6
;set inner down count
R6,*N~1
;see if beyono end
2$
;no--ok to' proceed
'N-1,R6
~yes--back UP to end
R4,R6~R5
;clear inner up count
MULRL~5),MULP[~6J,#O,RO ;extended multiply
llilULfHR5 j
; handle unsigned MULR longword
4$
;same as signed--no fixup
MULDLh6),R1
;different--fix result
llllULDlR6J
;handle unsign~d MULD longword
5$
;same as signed--no fi~up
MULRlR5),R1
;different--fix result
RO,PROD(R4j
;incorporate product
R1,R2
;count extension as carry
#O,R3
; (quad carry)
.fi.N -1 , R5 ,6$
; adva.nce count
7$
;terminate loop if done
R6,3$
;loop for this result
#2*N-2,~4,1$
;loop over result vector
R2,PR~D~2*N~1
;store final result
MULR+N-1
;handle signed MULR vector
9$
;same as signed--no fixup
R4
.
;different--clear loop index
l"1ULD[R4],PROD+t~lR4] ;subtract to fix result
#N-1,H4,tit
;loop over fixup
MDLD+N-1
;handle signed MULD vector
11$
;same as signed--no fixup
#1
;clear carry
R4
;different--clear loop index
NuLRL114],PROD+N[R4] ;subtract to fix result
HN.1,R4,10$
;loop over fixup
PRGD+2N-1
;set condition code ~

APPENDIX I
PDP-11 TO VAX-11 CONVERSION GUIDE

24-Mar-77-- Rev 4
The following is an aid to converting PDP-11 programs to
programs.
Each
PDP-11 instruction is paired with its
equivalent. Five types of equivalence are noted:

VAX-11
VAX-11

Equivalent instruction.

Possible simulation. A sequence of VAX-11 instructions is
equivalent. There is no suggestion that the simulation given
is the best in space or time.
The stack is used for
temporary space in the simulations. Particular care must be
taken with respect to operands specified by a.ddressing modes
with side effects.

Functionality.
A VAX
instruction
provides
similar
functionality.
The programmer should compare the VAX-11 and
PDP-11 instruction.

No good' simulation.
Although the instruction
can
be
simulated, the space or time required is disproportionate to
the probable contribution of the instruction to the algorithm
being
implemented.
The programmer will generally find
another way to implement the algorithm.

Not available.
architecture.

Instruction relates to concepts not in VAX-11

In addition, note that there is no odd address trap.

Copyright(c) 1979 Digital Equipment Corp. ,Naynard,Mass.
Du NO'I' COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
PDP-11 to VAX-11 Conversion Uuide
24-Mar-77 -- Rev 4
Page 1-2

PDP-11

VAX-11

HALT

hALT. Saved
fault.

WAIT

Not available.

Rl1

Functionality available
inward.

with

BPI

hfT.

canonical PSL set.

lUT

Functionality available with CHMK, CliME,
Canonical PSL set.

RESET

different;

Saved PC different;

~unctionality

available

with

canonical

REI.

MTPh.

PSL

set

Faults

P~L

CHMS,

Faul ts

CHMU.
outside

kernel mode.
Rl",L'

F'unctionality available with REI.

JMP

JMP.

RTS

n EQL 7, RSB •

Otherwise no good simulation.
sequences
including
HTS
may
efficiently using RET.
Sf'L

functionality available
kernel mode.

NOP

NUP.

CLear CC

BICPSw •

.sEt CC

BISPSw.

S'tJAB d st

Possible simulation:
MOVW

N,~,V,C

with

dst,-(SP)

NO Vb

( SP ) , 1 (S p )

hOVb
MOVw

dst, (SP)
(SP)+,dst

affected differently.

BRb or BHW.

·bNE.

bNEQ.

However,
certain
be simulated very

MTPR.

Faul ts

outside

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference lvJ2.nual
COt~.PANY CONFIDENTIAL
PDP-11 to VAx-11 Conversion Guide
24-Mar-17 -- Rev 4
Page l~j

BEQ

BEQL.

BGE

BGE~.

Branches on ~ ~QL 0 rather than N XOR V EQL O.

bLT

BLSS.

Branches on N ~QL

BGT

BGTR. Branches on Z OR N EQL 0 rather than
XOR V} EQL O.

Z OR

BLE

BLEQ. Branches on Z OR N EQL 1 rather than
XOR V} EQL 1.

Z OR

JSR

Rn ,dst

rather than N XOR V eQL 1.

If n=7, bSBB, BSBW, or JSB.
Otherwise no good
simulation.
sequences
including JSR
may
efficiently using CALLS or CALLG.

CLH

CLRw.

COt'! dst

MCOM~

INC

INCW.

C affected differ~ntly.

DEC

DECW.

C affected differently.

NEG dst

MNEGW

dst ,d st.

ADC dst

Possible simulation:

However
certain
simulated very

C affected differently.
dst ,dst.

bCC
INC~

C affected differently.

1;p
dst

1 $:

v, C affected differently.
In most cases ADC appears in sequences like:
ADD
ADC
ADD

A,E
B+2
A+2,b+2

This is of course simulated by:
ADDL

A,S

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 ~ystem Reference ~anual
COMPANY CONfIDENTIAL
PDP-11 to VAX-11 Conversion Guide
24-Mar-71 -- Hev 4
Page 1-4

SbC dst

Possible simulation:
BCC

DECw

1$
dst

1$:

V, C affected differently.

In most cases SEC appears in sequences like:
SUb
SEC
SDB

A,B
B+2

A+2,B+2

This is of course simulated by:
SUBL

A,E

1'ST

TSTw.

ROR

No good simulation.

ROL

No good simulation.

ASR dst

Possible simulation:
CVTWL
ASHL

dst,-(SP)

CVTL~

dst

#-1, (SP), (SP)

v, C affected differently.
ASL dst

ADD-W.2 dst, d st.

MARK

Not available.
by CALLS/HET.

Stack clean up functionality

provided

Not available.
src,-(SP).

functionality

available

with

MOVW

i'1TPI d st

Not available.
(SP)+ ,dst.

Functionality

available

with

MOV~

SXT dst

Possible simulation:
BLSS
CLRw

BRB
1$: NNEGw
2$:

dst
2$
111 ,dst

Copyright(c) 1979 Digital Equipment Corp.,Maynard,~~ss.
DO NOT COpy
VAX~1' System Reference Manual
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PDP-11 to VAX~11 Conversion Guide
24-Mar-77 -- Rev 4
Page 1-5

C affected differently.

NOV

MOVw.

eMP

CMPW. N, V. affeoted differently.
However oompare
followed by an equivalent conditional branch behaves
similarly.

81T

BITW.

BIC

SICW2.

B:.t,3

BlSW2.

ADD

ADDW~.

MU~

sro, Rn

If n is odd:
NUI.,.W2

src,Rn

v, C affected differently.
If n is even, possible simulation:
CVTWL
CVl'INL
MULL2
MOVw

Rn, -(SP)

MOVw

(SP)+,Rn

src,-(SP)
(SP)+, (SP)
(SP)+,Rn+1

v, C affected differently.
If the functionality of high and low halves of result
in
different
registers is not needed, possible
simulation:
CVTWL
CVTWL
Ml)LL2

Rn,Rn

src,-(SP)
(SP)+, Rn

v, C affected differently.

Copyright(c) 1979 Digital equipment Corp.,Naynard,t-lass.
DO NOT COpy
VAX-11 ~ystem Heference Manual
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PDP-11 to VAX-11 Conversion Guide
24-Mar-77 -- Hev 4
Page 1-6

D1 V src, Rn

Possible simulation:

CVl'wL

Rn,-(SP)
Rn!1,-(SP)
src, - (.::;P)

EDIV

(SP)+, (SF)+, fin, Rn! 1

MUVW

MOV,-

v, ~ affected differently.
If only the functionality of the quotient is needed:
DIVWt::

src, Rn

V, L affected differently.

ASH src, Rn

Possible simulation:
CVTwL
ASHL

Rn, Rn
src,Rn,Rn

v, C affected differently.

Result may be different if

src GTR 31 or src L~S -31.
ASHC src, Rn

lf n even, possible simulation:
hOTL
tv10VW

ASHL
t-10VW
ROIL

U16,Rn,Rn
Rn+1 , Rn
src, Rn
Rn , Rn+ 1
#16,Rn,Rn

v, C affected differently.
If the functionality of high and
different registers is not needed:
AShL

low

halves

src, Rn, fin

hesult may be different if src GTR 31 or src LS& -31.
If n odd:
lNSV
ASBL

Rn,il16,#16,Rn
src, Rn

v, C affected differently.

Copyright(c) 1979 Digital Equipment Corp. ,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
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tDP-11 to VAX-11 Conversion Guide
24-Mar-77 -- Rev 4
Page 1-7

XOR

XORw2.

FADD Rn

ADDi2 (Rn)+,(Rn).
overflow.

Condition

codes

different

FSUB lin

SuBF2 (Rn)+,(Rn).
overflow.

Condition

codes

different

F'MUL Rn

MULf2 (Rn)+,(Rn).
overflow.

Condition

codes

different

ti'Dl V Rn

DIVF2 (Rn)+,(Rn).
Condition
overflow or divide by zero.

codes

different

SOB

Rn ,dst

Possible simulation:
DECW
BNE

dst

N, Z, V affected differently.
available with SOSOTH.

Similar functionality

BPL

BOTR.

Bl"a

bLSS.

BHI

BGTRU.

BLOS

BL1:.QU.

BVe

BVC.

BV;S

BV;:>.

BCe, 8111S

BCC, BGEQU.

beS, BLO

BCS, BLSSU.

EIvlT

r'unctionality available with CHMK, CHME,
Canonical PSL set.

CHMS,

CHMU.

TRAP

Functionality available with CHHK, eMME,
Canonical PSL set.

CHMS,

C~lU.

CLRB

CLRB.

COMB dst

MCOl~

. INCB

INCB.

C affected differently.
dst,dst.

C affected differently •

C affected differently.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass..
00 NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
PDP-11 to VAX-11 Conversion Guide
24-ivlar-77 -- Hev 4
Page 1-8

DEC£

DECB.

NEGB dst

MNEGB d st,d st.

ADCB dst

Possible simulation:

C affected differently.

Bce

INCB

dst

1$:

v, C affected differently.
saCB dst

Possible simulation:
Bce

D~CB

dst

1 $:

v, C affected differently.
TSTB

TS'l'B.

RORB

No good simulation.

ROLB

No good simulation.

ASRB dst

Possible simulation:
CVTBL
ASHL
eVTLB

dst, -(SP)
iF1, (SP), (SP)
(SP)+,dst

v, e affected differently.
ASLB dst

ADDB2 dst, d st.

MTPS src

Usually just BISPSW, BICPSW.
Possible simulation:
i"10VPSL
lvlOVb

-(Sp)

sre, (SP)

MOVW

(SP)+, (SP)

BICPSW
BISPSW

#-1

(SP)+

T affected differently.

Copyright(c) 1919 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference l-lanual
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PDP-11 to VAX-11 Conversion Guide
24-Mar-17 -- Rev 4
Page 1-9

MF'PD arc

Not

available.

Functionality

available

with

fi'unctionali ty

available

·with

MOW src,-(SP).

Iv1TPD dst

Not
available.
MOVW (SP)+,dst.

MFPS dst .

Possible simulation:
MOVPSL
INSV

-(SP)
/f0 , /18 , (S P )+ , d st

dst<7:5> different.

N, Z affected differently ,

MOVE src, d st

If dst is not a register, MOYB.
CVTBW.

CMPB

CMPB. N', V affected differently.
However compare
followed by an equivalent conditional branch behaves
similarly.

B1TB

BITB.

BICB

BICB2.

BISB

BISB2.

SUB

SUBW2.

CFCC

Not available.

Only a single set of condition codes.

SETF

Not available.

Separate instructions.

SET1

Not available.

Separate instructions.

SETD

Not available.

Separate instructions.

SETL

Not available.

Separate instructions.

LDFPS

Not available.

Only one status word.

STFPS

Not available.

Only one status word.

STST

Not available.

Only one status word.

CLRF

CLRF.

No FCC.

CLRD

CLRD.

No r~CC.

TSTF

TSTF.

TSTD

T8TD.

No FCC.

FCC.

If dst is a register,

Copyright(c) 1979 Digital Equipment Corp.,Maynard,~ass.
DO NOT COpy
VAX-11 System Reference l"lanual
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PDP-11 to VAX-11 Conversion Guide
24-Mar-77 -- Rev 4
Page 1-10

ABSF src, d st

Possible simulation:
l'-j 0 V£i'

src,dst

BGEC

NNEGF

dst ,dst

1 $:
~o

AESD src,dst

FCC.

Possible simulation:
NOVD

src ,dst

BGEQ
l'-lNEGD

dst ,dst

NEGF dst

MNEGF dst ,dst.

No FCC.

NEGD dst

MNEGD dst ,dst.

NO FCC.

MULF

MULF2.

FCC.

MULD

MULD2.

FCC.

MODF

Not available.

Functionality provided by EMODF.

[vluDD

Not available.

F1 unctionali ty provided

ADDF

ADDF2.

No FCC.

ADDD

ADDD2.

No fCC.

LDF

{vlOVF.

No FCC.

LDD

MOVD.

No £i'CC.

SUBr'

SlJBF2.

No F'Ce.

SUBD

SlJBD2.

No 14'CC.

CMPF

C~lPF'

No FCC.

CllflPD

CMPD.

No fCC.

STlt'

MOVF.

No !t'CC.

1 $:

No FCC.

by EMODD.

Copyright(c) 1919 Digital Equipment Corp.,Maynard,Mass.DO NOT COpy
VAX-11 System Reference Manual
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PDP-11 to VAX~11 Conversion Guide
24-Mar-11 -- Rev 4
Page 1.11

STD

HOVD •. No FCC.

DIVF

DIVF2.

No FCC.

DIVD

DIVD2.

No FCC.

STEXP Rn ,dst

Possible simulation:
EXTV
CVTLS
SUBB3

11, #8, Rn, - (SP)

(SP)+,-(SP)
'128, (SP)+,dst

v, C affected differently.

No FCC.

STCFl

CVTF~.

C, V affected differently.

No FCC.

STCFL

CVTFL. C, V affected differently.
format different.

No FCC.

STCDI

CVTDW.

C, V affecteo differently.

No FCC.

STCDL

CVTDL. C, V affected differently.
format different.

No FCC.

STCFD

CVTFD.

No F"CC.

·STCDF

CVTUF ..

No FCC.

LDEXP src, Rn

Possible simulation:
SUBL2
ADDB3
INSV

'3,SP
1128,src,-(SP)
(SP)+,11,lb,Rn

No FCC.

LDCI~~

CVTwlt"' •

LDCID

CVTWD.

No FCC.

LDCLF

CVTLF.

No It'CC.

Longword format different.

LDCLD

CVl'LD.

No FCC.

Longword format different.

LDCDF

CVTDF.

No FCC.

LDCFD

CVTFD.

No FCC.

FCC.

Longword

. Longword

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference ~anual
COMPANY CONFIDENTIAL
PDP-11 to VAX-11 Conversion Guide
24-Mar-77 -- Rev 4
Page 1-12

[End of Appendix I)

Digital hquipment Corporation CON,PANY CONF1DENTIAL

Title:

to VAX-11 Conversion Guide -- Rev 4

PDP-11

Specification Status:

Fully approved

Architectural .;:;tatus:

under ECO control

F1LE:

Page 1

SRIR4.RNO

PDM I: not used

Date: 24-Mar-77
Superseded Specs:
Author:

Strecker & P.

Typist:

Call

Reviewer(s):

Abstract:

P. Conklin,
P. Lipman,
B. Strecker

Conklin

l).

1).

Cutler,
Rodgers,

D. Hustvedt,
S. Rothman~

J. Leonard,
6. Stewart,

Appendix I is an aid to converting PDP~11 programs to
VAX-11 programs.
Each PDP-l1 instruction is paired with
its VAX-11 equivalent. The types of equivalence are:
1.
2.

3.
4.
5.

Equivalent instruction
Possible simulation given
Functional similarity given
No good simulation
Not available

The table is in the order of the PDP-11 instruction opcode
aSSignments.
Revision history:
Rev. if
Rev 1
Rev 2
Hev 3
Rev 4

Description
Notes
Corrected Notes
Formalized, and Reconciled
MIPS, l"iF,fJS

Author
Rarich
Conklin
Strecker
Streck~r

Revised Date
Oct-75
Jan-'"{6
13-Jun-76
24-Lvlar-77

PDP-1, to VA~-11 Conversion Guide
Change hif$tory

24-Mar-77 -- Rev 4

Rev 3 to Rev 4:
1.

AddMTPS, 1-1FPS.

Hev 2 to Rev 3:

F'ormalize the various categories

2 .. Add complete instruction list

Include many possible simulations

Reconcile with SRM Rev 3

Improve simulation of ASL, ASLB

Rev 1 to Rev 2:
1.

Correct var!ous misunderstandings

Reconcile with SRM Rev 2

[End of SRIR4.RNO]

Page 1-990

Digital Equipment Corpor-etion COMPANY CONFIDENTIAL

Title:

Page 1

VAX-ll Address Validation Rules - Rev 4

Specification Status:

Fully Approved

Architectural Status:

under ECO control

File:

SRJR4.RNO

PDM I:

not used

Date:

l-Feb-77

Superseded Specs:
Author:

Cutler

Typist:

Bess

Reviewer(s):

Abstract:

P. Conklin,
P. Lipman,
B. Strecker

D. Cutler,
D. Rodgers,

D. Hustvedt,
S. Rothman,

J. Leona.rd,
B. Stewart,

The hardware memory management mechanisms described in
Chapter 5 must be supplimented with software to provide a
protected operatinp: environment.
Appendix J sets forth
hardware and software assumptions about· such an environment
and a set of rules that must be followed bY operating
system soft-ware to construct a protected system.

Revision History:
Rev.n
Rev 1
Rev 2
Rev 3
Rev 4

Description
Original
Incorporate Review Comments
skipped to maintain numbering
Typos

Author Revised Date
Cutler 20-May-76
Cutler 8-Jun-76
Cutler

l-Feb-77

Address Validation Rul~s
Chan~e History

Pap:e J .... 990

Rev 2 to Rev 4:
1.

Typos.

Reouire PROaE before read to protect I/O side effect$.

Rev 1 to Rev 2:
1.

Add retriction on MTPR to previous mode of PSL.

Add assumption thet REl verifies consistency.

[End of SRJR4.RNO]

APPENDIX J
ADDRESS VALIDATION RULES

l-Feb-77 -- Rev 4
separates
The memory management system described in Chapter 5
validation from the access of ar~uments.
In the previous scheme
validation and access were performed as an indivisible operation.
There is some Question as to whether the new scheme will be adequate
to build reliable and secure operating systems. Specifically will it
be possible for a user to call an inner access mode in such a manner
as to cause the inner access mode to access data in a way that
corrupts system integrity (e.g., causes supervisory code to write over
itself) or incorrectly allows access to data that would otherwise have
been inaccessible (e.g., the reading of a password table).
In order to accomplish either of these encroachments, the user must be
able to generate a bogus address in such a way to cause supervisory
software to have protection or security holes.
The
followin~
discussion sets forth operating system and hardware assumptions and
then explains the rules that must be adhered to when accessing
arguments from an inner a.ccess mode to avoid such a hole.
The following
software:

assumptions

are. made

concernin,St

operating

system

Operating system software (kernel and executive mode) is
trustworthy and does not maliciously at tempt to brea.kdown the
protection mechanisms (e.g., change the mapping or protection
of pages at arbitrary times).

The protection of a shared page may not be chan~ed unless the
share count is one and the process attempting the change is
that sharer.

The protection of a page with B. nonzero I/O pending count may
not be changed until the count~oes to zero.

Operating system software will not
access modes while the process
access mode.

deliver AST's to outer
is executing in an inner

Copyri~ht( c) 1979 Digital Eoui pment Corp. ,11aynard, MrJ ss.
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VAX-11 System R~ference Manual
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Address Validation Rul~s
1-Feb-77 -- Rev 4
Pa~e J-2

passed to an inner access mode can be maliciously
destroyed asynchronously by another process (e.g., ahared
data) or by an 1/0 transfer, but not by a less privile~ed
mode of the ex~cuting process itself.

Kernel and executive stacks are never allocated in shared
memory or accessible to other than their respective access
modes.

Ar~uments

The following ~ssumptions are made concernin~ the VAX hardware:
1.

Four access modes are provided
process per access mode.

and

there

stack

per

Protection i~ hierarchical with the innermost access
being the least restricted ~nd the outermost the
restricted.

mode
most

Four instructions are provided to change the processor mode
to the four access modes (CHMU, CHMS, CHME, and CHMK);
furthermore, when a process is executing a chan~e mode
instuction the access mode can only be decreased (chan~ed to
a more privile~ed mode) or left the sa.me.

Two instructions are provided to validate the accessibility
of arg;uments, Probe Read (PROBER) and Probe Write (PROBEW).
Thp.~e instructions validate the
accp.ssibility of ar~uments
using the maximization of the Previous Mode field of PSL and
Thus only current and
more
a specified access mode.
restricted access modes can be probed.

The Return from Interrupt instruction (REI) insures that the
current mode field of the restored PSL is greater than or
equal to the current mode field of the current PSL and that
the previous mode field of the restored PSL is ~reater than
or equal to the current mode field of the restored PSL.

Copyright(c) 1979 Di~ital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONfIDENTIAL
Address Validation Rules
1-Feb-77 -- Rev 4
Pa~e J-3

Given the above operating system and hardware assumptions, the
following rules ~uarantee that less privil~~ed modes cannot pa~s bogus
addresses to more privileged mode~.

All addresses (incl udinp: indirect addresses) pa s'sed
as
arguments to an inner access mode must be copied (preferably
to a re~ister, but in any case to an area of memory that is
not
modifiable
by
less privileged modes) before the
accessibility of
the
actual
s.rQ;ument
is
validated.
Furthermore, if such an address will later be used to
asynchronously post information back to an outer access mode,
then the least privileged access mode that can perform the
specified operation (i.e., a. read or write of data), must be
copied from the coresponding page table entry and stored with
the argument address.
NOTE
Using least privilege does not work properly when the
data
structure resides in pages with different
protection and the first page has a lesser protection
value
than
the
others.
When
checking
the
accessibility of such a structure in the context of
the serial execution of the process, the check will
succeed, but later when the accessibility is checked
ag:ain during the a.synchronous posting of information,
the check will fail. This situation is considered to
be s.n operating system bug (may cause the ~eneration
of a bug check) and merely causes no information to
be posted.

The synchronous validation of arg,:ument addresses (i.e. ,_ as
the result of serial program execution) must be explicitly
coded using Probe instructions specifying an Rccess mode of
zero (i.e., c~use maximization to previous access mode).

The asynchronous validation of argQ~ent addresses (i.e., as
the result of software interrupts) must be explicitly coded
usin~ Probe
instructions specifying the least privileged
access mode stored when the argument address was saved (see
1. above) and with a previous access mode field eoual to or
greater than that of the current mode field of PSL (i.e.,
cause maximization to least privile~ed access mode).

All arguments to be .written must be PROBEW'ed before they are
written (protection hole if not).

Copyright( ,!) 1979 Digital Equi pment Corp., Maynard, Mass.
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VAX-11 System Reference Manual
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Address Validation Rules
1-Feb-77 -- Rev 4
Page J-4

All arguments to be read must be PROBER' ed before they are
read to defend against arguments mapped to I/O space and
thereby causin~ an I/O side effect.

All addresses passed from an outer access mode to an inner
access mode must be copied and validated before bein~ passed
as arguments in a call to a more inner access mode.
\This
insures the intep:rity of intermedi2.te modes. \

The above discussion centered on the validation of argument addresses.
There are other arguments that also deserve the careful handlin~
described. Such arguments are typically a.ddress modifiers (e.g. , a
buffer length) and in most cases must also be copied to insure system
integrity.

It is believed that the above assumptions and specified rules for
validation make it possible to construct a reliable operating system.
No claim is made as to whether a secure operatin~ system can be built.
[End of Appendix J]

Digital Equipment Corporation COMPANY CONFIDENTIAL

Title:

VAX-11 Programming Examples -- Rev 4

Specification Status:

Fully approved

Architectural Status:

under ECO control

File:

Page 1

SRKR4.RNO

PDM #: not used
Date:

24-Mar-77

Superseded Specs:
Author:

Strecker

Typist:

Principe

Reviewer(s):

Abstract:

P. Conklin,
P. Lipman,
B. Strecker

D. Cutler,
D. Rodgers,

D. Hustvedt,
S. Rothman,

J. Leonard, .
B. Stewart,

The examples in Appendix K are designed to illustrate the
capabilities of the VAX-11 instruction set. They are not
intended to be a tutorial on pro~ramming.
A familiarity
wi th PDP-11 assembly language programming is a.ssumed.
There is no suggestion that a compiler or a programmer
might code these examples as production code, rather they
are intended as illustrations only.

Revision History:
Rev /I
Rev 1
Rev 2
Rev 3
Rev 4

Description
Distributed
ECOs 1-11
ECOs 12-18 and April Meeting
Add comments; keep with ECOs

Author
Strecker
Strecker
Conklin
Conklin

Revised Da.te
25-Sep-75
8-Mar-76
13-Jun-76
24-Mar-77

Programming Examples
Chan~e History

24-Mar-77 -- Rev 4

Rev 3 to Rev 4:
1.

Add some comments.

Track EDITPC, decimal, POLY ECOs.

Add EDIT PC examples.

Rev 2 to Rev 3:
1.

Update assembler constant notation

Don't save RO, R1

Chan~e

to MOVAL, BLEQ, AOBLEQ, AOBLSS, RET

Chan~e

to 10$

Correct loop ending tests

Change terminology to post-indexed

Add SIN example

Add Floating output example

Add MOVL of N in SORT exa.mple

10.

Remove space after comma in examples

11.

Add integer/numeric overflow enables to entry masks

12.

Add POLY to SIN example

Rev 1 to Rev 2:
1.

Remove EXCHx instruction

Change to positive arg displacement

Remove LSTO

Don't precompute the N ar~ument

[End of SRKR4.RNO]

Page K-990

APPENDIX K
PROGRAMMING EXAMPLES

24-Mar-77 -- Rev 4

K. 1

PURPOSE

The purpose of the prQgrammin~ examples is to illustrate VAX-11
capabilities which are not present in the PDP-11. It is not intended
to be tutorial on pro~ramming; a familiarity with PDP-11 assembly
lan~ua~e programming is assumed.

K.2

SORT ALGORITHM

The following subroutine written in FORTRAN is
sorting an array of values into ascendin~ order.

algorithm

for

SUBROUTINE SORT(N,A)
<dpt~ type x> A(N), TEMP
INTEGER*4 N, I, J
DO 10 1=1, N-1
DO 10 J=I+1, N
IF (A(I).LE.A(J» GO TO 10
TEMP = A(I)
A(I) = A(J)
A(J) = TEMP
CONTINUE
RETURN
END

The following is VAX-11 code to implement this a1~Qrithm. There 1s no
suggestion that any given FORTRAN compiler would ~enerate this code;
the algorithm was expressed in FORTRAN only for convenience.
The subroutine is assumed to be called by the VAX-11 standard calling
convention (See Appendix C); hence, 4(AP) points to the address of N
and 8(AP) points to the address of A (0 origin assumed).

Copyright(c) 1979 Digital Equipme~t Corp. ,Maynard ,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Programming Examplt's
24-Mar-77 -- Rev 4
Page K-2
SORT ALGORITHM

SORT: :
1•

.WORD

MOVAL
MOVL
MOVL
ADDL3
CMPx
BLEC
MOVx
MOVx
MOVx
AOBLEO
AOBLSS
RET

3.
4.
5.
6.
7.
8.
9.

1$:
2$:

10.
11.

12.
13.

10$:

AX4QOC

;Entry mask to save R3, R2
; and enable integer overflow
@8(AP),RO
;Get A base
@4(AP),R12
;Get N (~ize)
11,R1
;Initialize I
H1,Rl,R2
;Initialize J to 1+1
(RO)[R1],(RO)[R2) ;Correct order?
10$
;Yes
;Save A(l)
(RO)[Rl],R3
(RO)[R2),(RO}[R1) jReplace A(I) with A(J)
R3,(RO)[R2)
;Replace A(J) with saved A(I)
R12,R2,2$
;Continue
R12,Rl,1$
;Co~tinue
;Return B.nd restore
;registers R2 and R3

Line 1 contains an entry mask so that registers R2, and R3 will' be
saved by the CALL instruction which calls the subroutine.
By
convention, RO and R1 are not saved. Inte~er overflow is enabled.
Line 2 gets the base of the A array. The move address instruction is
used in conjunction with argument mode addressing. This instruction
saves memory accesses inside the loop.
Line 3 gets the array size. The move long instruction is used in
conjunction with argument mode addressing. This instruction saves
memory accesses inside the loop.
Line 4 initializes I to 1.

Literal mode addressing is used.

Line 5 initializes J with 1+1.

A three operand add is used.

Line 6 compares A(I) to A(J).
is used.

Line 7 branches past the exchange if the array
right order.

mode

are

the

Lines 8 through 10 exchange the array elements if they are
wrong order. Register post-indexed mode addressing is used.

the

Argument

mode

Lines 11 and 12 carry out the
addressing is used.

loop

end

elements

addressing

operations.

Line 13 returns and restores registers R2 and R3.
Note, that because of logical indexing in Lines 5, 7, 8, and 9 and the
orthogonality of operator and data type, the subroutine works for
byte, word, longword, floating, or double data types of arra.y A simply
by substituting B, W, L, F, or D respectively for x. Note that if
double, then R4 would have to be saved also in the entry mask.

Copyright(c) 1979 Digital Equipment Corp.,Maynard,Mass.
DO NOT COpy
VAX-ll System Reference Manual
COMPANY CONFIDENTIAL
Programming Examples
24-Mar-77 -- Rev 4
Page K-3
SORT ALGORITHM
The size of eaoh instruction is:
1.
2.

5.
6.
7.
8.
9.
10.
11 "
12.

13.
Tot~l

2 bytes

4
4

4
5
2

4
5

4
4
4
1

46 bytes

Copyri~ht(c) 1979 Di~ital Equioment Corp. ,Maynard,Mass.
DO NOT COPY
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Programming Examples
24-Mar-77 -- Rev 4
Pa~~ K-4
SIN FUNCTION

K.3

SIN FUNCTION

This example shows how the initial argument handling might be done in
the math library to handle argument ran~e reduction followed by
CASEin~ to the algorithm for each octant.

x = SIN (Y)
PIHI=xxx
PILO=xxx

;hi~h 4 bytes (8 if double)
;low byte of 4/PI

SIN: :

• WORD
MOVAL

EMODx

1$:
2$:

BGEO
ADDx
DECL
BICB2
CASEB
. WORD
. WORD
.WORD
. WORD
.WORD
.WORD
. WORD

~X400C

;save R2-R3 for POLYF, -R7 for POLIO
;enable integer overflow
HANDLER,O(FP)
;enable inte~er overflow
; condition handler to catch
; loss of significa.nce on
; a hu~e ar~ument
IPIHI,IPILO,@4(AP),R2,RO
;~et octant in R2
; reduced ar~ument in ·RO
1$
;if positive, ok
I F1.0,RO
;if negative, get
R2
; positive reduction
I C7,R2
;mask to 8 octants
R2,11,#6
;branch to each octant
OCT_1-2$
OCT_2-2$
OCT.3-2$
OCT_4-2$
OCT3-2$
OCT_6-2$
OCT_7-2$
;fall out of CASE on octant
A

octant 0 with fully precisp reduced arp:ument in RO
OCT_a:

POLYx
RET

1$:

. FLOAT

RO,2$,1$

; eva! uate polynomial
;return value in RO

.FLOAT
2$=.-1$-1
HANDLER:

;condition handler
.WORD

Copyright( c) , 919 Digital Equ1 pment Corp. ,Maynard ,Mass.
00 NOT COpy
VAX~11 System Reference Manual
COMPANY CONFIDENTIAL
Programming Examples
24-Mar-11 ."" Rev 4
Pap:e 1(.5
FIXED FORMAT FLOATING OUTPUT
K.4

FIXED FORMAT FLOATING OUTPUT

This example showe how to
FORTRAN format F9.3 .

output

floatin,

point

number

the

; string = FOUT (X)

STRING: .BLKE

;room for output

PATTERN:
EO$FLOAT
EO$END_FLOAT
EO$MOVE
EO$INSERT
EO$MOVE
EO$END

"'A/.I

;EDITPC pattern string
; float 8i,n, mov·e 4 dig1 t~
;end floating $ign
;move one digit
;lnsert period
;move three fraotional digits
;end of pattern

FOUT: :
;save R2-R5, enable overflows
;make room on staok
,"'F1000,O,@4(AP),RO
;normalize for th, ,3
CVTRFL RO,RO
;roun~ digits
CVTLP RO"a,(SP)
;convert to digits on etaak
EDITPC 18,(SP),PATTERN,STRING
jedit to output
MOVQ
'<.LONG 9,STRING+1>,RO
;tunct1on value is a
; string descriptor
RET
;return restoring R2-R5
; and the stack

•WORD
SUBL2
MULF3

"'XC03C

18,sP

Copyright(c) 1979 Digital Equipment Corp.,Haynard,Mass.
DO NOT COpy
VAX-11 System Reference Manual
COMPANY CONFIDENTIAL
Programming Examples
24-Mar-77 -- Rev 4
Page K-6
COBOL OUTPUT EDITING
K~5

COBOL OUTPUT EDITING

In all of these examples, A is a COMP-3 datum of
operation is

len~th

A_LEN.

The

MOVE A TO B.
The generated code is
EDITPC

IA_LEN,@A,MICRO,@B

In the patterns, the EO$ADJUST_INPUT can be omitted if A is the sa.me
size as S, and the EO$REPLACE_SIGN (and its EO$LOAD_FILL) can be
omitted if A cannot contain a -0.
1 , PICTURE

MICRO:

2. PICTURE
MICRO:

$$,$$9.99CR
EO$ADJUST_INPUT
EO$LOAD_SIGN
EO$FLOAT
EO$INSERT
EO$FLOAT
EO$END_FLOAT
EO$MOVE
EO$INSERT
EO$MOVE.
EO$LOADJLUS
EO$LOAD_MINUS
EO$STORE_SIGN
EO$LOAD_MINUS
EO$STORE_SIGN
EO$REPLACE_SIGN
EO$REPLACE_SIGN
EO$END

6
'$
1

'e
'R
2
1

+$99,999.99
EO$ADJUST_INPUT
EO$LOAD_PLUS
EO$STORE_SIGN
EO$SET_SIGNIF
EO$INSERT
EO$MOVE
EO$INSERT
EO$MOVE
EO$INSERT
EO$MOVE
EO$LOAD_FILL
EO$REPLACE_SIGN
EO$END

7
'+

'$
2

3,
2
'+

DO NOT COPY
Copyright(c) 1979 Di~ital Equipment Corp.,Maynard,Mass.
COMPANY CONFIDENTIAL
VAX-11 System Reference Manual
Programming Exa,mpl es
Page K-7
24-Mar w 77 -- Rev 4
COBO~ OUTPUT EDITING

3. PICTURE
MICRO:

4. PICTURE
MICRO:

5. PICTURE
MICRO:

6. PICTURE

MICRO:

ZZ,ZZZ.ZZ
EO$ADJUST_INPUT
EO$MOVE
EO$INSERT
EO$MOVE
EO$SET_SIGNIF
EO$INSERT
EO$MOVE
EO$BLANK_ZERO
EO$END

7
2

3
2

99,999.99 BLANK WHEN ZERO
EO$ADJUST_INPUT
EO$SET_SIGNIF
EO$MOVE
EO$INSERT
EO$MOVE
EO$INSERT
EOIMOVE
EO$BL,ANK_ZERO
EO$END

7
2

,,
3,

-----9.99
EO$ADJUST_INPUT
EO$FLOAT
EO$END_FLOAT
EO$MOVE
EO$INSERT
EO$MOVE
EO$REPLACE_SIGN
EO$END

4
1

+++++9.99
EO$ADJUST_INPUT
EO$LOAD_PLUS
EO$FLOAT
EO$END_FLOAT
EO$MOVE
EO$INSERT
EO$MOVE
EO$LOAD_FILL
EO$REPLACE_SIGN
EO$END

7
'+
4

'+
5

Copyright(c) '919 Di~ital Equipment Corp.,Maynard,Mase.
DO NOT COpy
VAX-" System Reference Manual
COMPANY CONFIDENTIAL
Programming Examples
24-Mar-71 ....... Rev 4
Pa~~ K-8
COBOL OUTPUT EDITING
1. PICTURE
MICRO:

•• ,••• .••
EO$ADJUST INPUT
EO$LOAD_FILL
EO$MOVE
EO$INSERT
EO$MOVE
EO$SET_SIGNIF
EO$INSERT
EO$MOVE
EO$BLANK_ZERO

',.

,,
2
2

EO~END

8. PICTURE
MICRO:

BBBZZBZZZ.ZZB
EO$ADJUST_INPUT
EO$FILL
EO$MOVE
EO$FILL
EO$MOVE
EO$SET_SIGNIF
EO$INSERT
EO$MOVE
EO$BLANK_ZERO
EO$FILL
EO$END

[End of Appendix KJ

3
2
1

3
2

3
1

Page

Index-1

INDEX
in CALL standard, C-4, C-4
%DESCR - CALL by Descriptor
Intrinsic function, C-6
%REF- CALL by Reference
Intrinsic function, C-6
%VAL - CALL by Value
Intrinsic function, C-6
()

as a notation, 3-3
Abort, 6-1, 6-3
ABSD
PDP-11 instruction, 1-10
ABSF

PDP-11 instruction, 1-9
Absolute addressing
assembler notation, B-3
Absolute addressing mode, 3-6
Absolute indexed addressing mode,

3-13
Absolute indexed mode, 3-13
Absolute mode, 3-6
Absolute queues, .4-114
Absolute vs. relative
assembler notation, B-3
ACBB - Add Compare and Branch
Byte, 4-85
ACBD, E-2
ACBD - Add Compare and Branch
D_floating, 4-85
ACBF, E-2
ACBF - Add Compare and Branch
fc'_floating, 4-85
ACBG, E-2
ACBG - Add Compare and Branch
G_floating, 4-85
AeBH, E-2
ACBH - Add Compare and Branch
H_floating, 4-85
ACBL - Add Compare and Branch
Long, 4-85
ACBw - Add Compare and Branch
Word, 4-85
Accelerator
VAX-11/180, 9-16
Accelerator Control/Status
Register (ACCS), 9-16
Accelerator Maintenance
Register (ACCR), 9-16
Access across page boundaries,
5-23

Access control, 5-5
Access control violation fault,
6-11
Access mode, 6-5
memory, 6-5
Access mode, memory, 5-5
Executive, 5-5
Kernel, 5-5
Supervisor, 5-5
User, 5-5
Access type, operand, 3-2
address, 3-2, 3-11
branch, 3-2, 3-17
modify, 3-2, 3-17
synchronization, 3-18
read, 3-2, 3-17
write, 3-2, 3-17
AceR - Accelerator ~~intenance
Register, 9-16
Aces - Accelerator Control/Status
Register, 9-16
Activation, procedure, D-2
ADC

PDP-11 instruction, 1-3
ADCB
PDP-11 instruction, 1-8
ADD
PDP-11 instruction, I-5
ADDB2 - Add Byte 2 Operand, 4-17
ADDB3 - Add Byte 3 Operand, 4-17
ADDD
PDP-11 instruction, 1-10
ADDD2, E-2
ADDD2 - Add D_floating 2 Operand,
4-50
ADDD3, E-2
ADDD3 - Add D_floating 3 Operand,
4-50
ADDF
PDP-11 instruction, 1-10
ADDF2, E-2
ADDF2 - Add F_floating 2 Operand,
4-50
ADDF3, E-2
ADDF3 - Add F_floating 3 Operand,
4-50
ADDG2, E-2
ADDG2 - ADD G_floating 2 Operand,
4-50
ADDG3, E-2
ADDG3 - ADD G_floating 3 Uperand,
4-50
ADDH2, £-2

Page
ADDH2 - ADD H_floating 2 Operand,
4-50
ADDH3, E-2
ADDH3 - ADD H_floating 3 Operand,
4-50
Additions to the architecture, E-4
ADDL2 - Add Long 2 Operand, 4-17
ADDL3 - Add Long 3 Operand, 4-17
ADDM - Multiprecision Addition,
H-1
ADDP4, E-2
ADDP4 - Add Packed 4 Operand,
4-173
ADDP6, £-2
ADDP6 - Add Packed 6 Operand,
4-173
Address, 2-1
Address access type, operand,
3-2, 3-17
Address arguments, validating,
5-19
Address instructions, 4-65
Address translation, 5-7
Address validation rules, J-l
Addressing mode
assembler notation, B-1
Addressing modes notation, 3-3
ADDW2 - Add Word 2 Operand, 4-17
ADDW3 - Add Word 3 Operand, 4-17
ADWC - Add With Carry, 4-20
Alignment
stack, 6-33
target of control, 4-74
AOBLEQ - Add One and Branch
Less Than or Equal, 4-87
AOBLSS - Add One and Branch
Less Than, 4-88
AP - Argument Pointer Register,
2-14
AP - Argument POinter register
in CALL standard, C-7
Architecture additions, E-4
Argument count
in CALL standard, C-4
Argument data types
in CALL standard, C-9
Argument descriptor, C-11
Argument list
in CALL standard, C-4
Argument Pointer Register, 2-14
Argument, missing
in CALL standard, C-5
Arithmetic
multiprecision, H-l
Arithmetic faults, 6-14
Arithmetic instructions

Index-2

decimal string, 4-166
floating point, 4-35
integer, 4-7
Arithmetic traps, 6-14
Array addressing, 3-13
Array descriptor, C-14
ASCII string data type, C-10
ASH

PDP-l1 instruction, 1-6
ASHC
PDP-11 instruction, 1-6
ASHL - Arithmetic Shift Long, 4-29
ASHP, E-2
ASHQ - Arithmetic Shift Quad, 4-29
ASL
PDP-l1 instruction, 1-4
ASLb
PDP-l1 instruction, 1-8
ASR
PDP-11 instruction, 1-4
ASHE
PDP-l1 instruction, 1-8
Assembler notation
absolute addressing, B-3
absolute vs. relative, B-3
addressing modes, B-1
branch dislacement, B-6
branch selection, B-6
general addressing, B-3
generic opcode selection, B-6
relative addressing, B-2
AST - Asynchronous System Trap,
6-8, 6-30, 6-41
AST - Aynchronous System Trap,
6-32
AST, Asynchronous System Traps,
7-7
ASTLVL - Asynchronous System
Trap Level, 6-8
ASTLVL - Aynchronous System
Trap Level, 6-19, 6-40
ASTLVL - Pending AST Level, 7-5
Autodecrement addressing mode, 3-7
Autodecrement indexed
addressing mode, 3-13
Autodebrement indexed mode, 3-13
Autodecrement mode, 3-7
Autoincrement addressing mode, 3-5
Autoincrement deferred
addressing mode, 3-6
Autoincrement deferred indexed
addressing mode, 3-13
Autoincrement deferred indexed
mode, 3-13
Autoincrement deferred mode, 3-6
Autoincrement indexed
addressing mode, 3-13

Page
Autoincrement indexed mode, 3-13
Autoincrement mode, 3-5
Backslant
as a notation, 1-3
Base operand specifier, 3-12
Base register, 2-14
BBC -'Branch on Bit Clear, 4-79
BBCC - Branch on Bit Clear
and Clear, 4-tlO
BBCCI - Branch on Bit Clear
and Clear Interlocked, 4-82
BECS - Branch on Bit Clear
and Set, 4-80
BBS - Branch on Bit Set, 4-79
BBSC - Branch on Bit Set
and Clear, 4-dO
BBSS - Branch on Bit Set
and Set, 4-80
BBSSI - Branch on Bit Set
and Set Interlocked, 4-82
BCC
PDP-l1 instruction, 1-7
Bce - Branch on Carry Clear, 4-75
BCS
PDP-11 instruction, 1-7
BCS - Branch on Carry Set, 4-75
BEQ
PDP-11 instruction, 1-2
BEQL - Branch on Equal, 4-75
BEQLU - Branch on Equal Unsigned,
4-75
BGE
PDP-l1 instruction, 1-2
BGEQ - Branch on Greater Than
or Equal, 4-75
BGEQU - Branch on Greater Than
or Equal Unsigned, 4-75
BGT
PDP-l1 instruction, 1-3
BGTR - Branch on 'Greater Than,
4-75
BUTRU - Branch on Greater Than
Unsigned, 4-75
BRI
PDP-11 instruction, 1-7
BHIS
PDP-11 instruction, 1-7
BIC
PDP-l1 instruction, 1-5
BICB
PDP-ll instruction, 1-9
BICB2 - Bit Clear Byte 2 Operand,
4-32
BICB3 - Bit Clear Byte :; Operand,
4-32

Index-3

BICL2 - Bit Clear Long 2 Operand,
4-32
BICL3 - hit Clear Long 3 Operand,
4-32

BICPSW - Bit Clear PSW, 4-112
BlCw'2 - Bit Clear Word 2 Operand,
4-32
BlCW3 - Bit Clear Word 3 Operand,
4-32
BIS
PDP-l1 instruction, 1-5
BISB
PDP-11 instruction, 1-9
B1SB2 - Bit Set Byte 2 Operand,
4-31
BISB3 - Bit Set Byte 3 Operand,
4-31
BISL2 - Bit Set Long 2 Operand,
4-31
BlSL3 - Bit Set Long 3 Operand,
4-31
B1SPSW - Bit Set PSW, 4-111
BISW2 - Bit Set word 2 Operand,
4-31
BISW3 - Bit Set Word 3 Operand,
4-31
BIT
, PDP-11 instruction, 1-5
Bit data type, C-9
Bit efficiency
as a goal, 1-1
B1TB
PDP-11 instruction, 1-9
BITB - Bit Test Byte, 4-30
BITL - Bit Test Long, 4-30
blTW - Bit Test Word, 4-30
BLBC - branch on Low Bit Clear,
4-84
BLBS - Branch on Low Bit Set, 4-84
BLE
PDP-11 instruction, 1-3
BLEQ - Branch on Less Than
or Equal, 4-75
BLEQU - Branch on Less Than
or Equal Unsigned, 4-75
BLO
PDP-11 instruction, 1-7
BLOS
PDP-11 instruction, 1-7
BLSS - Branch on Less Than, 4-75
BLSSU - Branch on Less Than
Unsigned, 4-75
BLT
PDP-11 instruction, 1-3
BMI
PDP-11 instruction, 1-7

Page
BNE
PDP-11 instruction, 1-2
BNEQ - Branch on Not Equal, 4-75
BNEQU - Branch on Not Equal
Unsigned, 4-75
Boolean values, C-7
Bootstrapping, system, 9-22
BPL
PDP-l1 instruction, 1-1
BPT
PDP-11 instruction, 1-2
BPT - Breakpoint Fault, 4-103
BR
PDP-11 instruction, 1-2
Braces
as a notation, 3-3
Branch access type, operand, 3-2,
3-17
Branch displacement
assembler notation, B-6
Branch displacement addressing,
3-16
Branch selection
assembler notation, B-6
BRB - Branch Byte Displacement,
4-77
Breakpoint fault, 6-21
BRW - Branch Word Displacement,

Index-4

byte displacement mode, 3-7
Byte Integer data type, C-9
Byte Logical data type, C-9

C - Carry Condition Code, 2-16,
6-5
C condition code, 2-16, 6-5
Cache, 8-2
CALL, C-1
Call frame, 4-95
CALL standard
Argument data types, C-9
Local storage, C-8
Preserved registers, C-8
Temporary registers, C-7
CALLG - Call Procedure With
General Argument List, 4-97
Calling sequence standard, C-4
CALLS - Call Procedure With
Stack Argument List, 4-99
CASEB - Case Byte, 4-91
CASEL - Case Long, 4-91
CASEW - Case Word, 4-91
CFCC
PDP-11 instruction, 1-9
Change mode instructions, 6-42
Character, 2-'7
fill, 4-195
sign, 4-195
4-17
Character string data type, 2-7
BSBB - Branch to Subroutine
Character string instructions,
Byte Displacement, 4-92
BSBW - Branch to Subroutine
4-1j9
Check protection, 4-212
Word Displacement, 4-92
Bug check, operating system, J-3
CHME - Change Node to Executive,
BVC
6-42
PDP-11 instruction, 1-7
ChMK - Change Hode to Kernel, 6-42
BVC - Branch on Overflow Clear,
CHMS - Change Mode to Supervisor,
6-42
4-75
BVS
CHMU - Change t'lOde to User, 6-42
PDP-11 instruction, 1-7
CLear CC
BVS - Branch on Overflow Set, 4-75
PDP-11 instruction, 1-2
Byte, 2-1
Clock Registers, 9-13
Byte data. type, operand, 3-2
Clock, interval, 9-14
Byte displacement
CLR
addressing mode, 3-7
PDP-11 instruction, 1-3
Byte displacement deferred
CLRB
addressing mode, 3-8
PDP-11 instruction, 1-7
CLRB - Clear Byte, 4-10
Byte displacement deferred
indexed addressing mode, 3-13
CLRD
Byte displacement deferred
PDP-11 instruction, 1-9
CLRD - Clear D_floating, 4-42
indexed mode, 3-13
Byte displacement deferred mode,
CLRF
PDP-11 instruction, 1-9
3-8
Byte displacement indexed
CLRF' - Clear fc"'-.floating, 4-42
addressing mode, 3-13
CLRG - Clear G_floating, 4-42
Byte displacement indexed mode,
CLRH, E-2
3-13

Page
CLRH - Clear H_floating, 4-42
CLRL - Clear Long, 4-10
CLRO - Clear Octa, 4-10
CLRQ Clear Quad, 4-10
CLRW - Clear Word, 4-10
CMP
PDP-11 instruction, 1-5
CMP - Compatibility lvlode, 6-5
CiVIPB
fDP-1t instruction, 1-9
CMPS ..., Compare Byte, 4-15
Cl'4PC3" B-2
CMPC3.... Compare Characters
3 Operand, 4-149
GMPC5, E-2

CMPC5 - Compare Characters
5 Operand, 4-149
GMPD, E-2
PD·P,,"" 11 instruction, I-10

CNPD ... Compare D_floating, 4-48
CMPF, E-2
pDP... 11 instruction·, 1-10
CMP}i' - Compare t_floating, 4-48

CNPG, E-2
CMPG ... Compare G_floating, 4-48
CMBH, E... 2
CHPH - Compare tl_floating, 4-48
CHPL - Compare Long, 4-15
CMPP3, B-2
C~lPP3 - Compare Packed
3 Op er and, 4-1 7 1
CHPP4, E-2
CMPP4 ... Compare Packed
4 Operand, 4-171
CMPV ... Compare F'ield, 4-70
CIvlPW ... Compare Word, 4-15
CMPZV - Compare Zero Extended
field, 4-70
COBOL o~tput editing examples, K-6
COIvI

PDP-l1 instruction, 1-3
COMB
PDP-l1 instruction, 1-7
Compatibility
as a goal, 1-1
Compatibility (PDP-l1)
long·word data format, 2-2
Compatibility mOde, 6-5
addr€ss modes, 10-2
addresses, 1:0-5
BFT trap, 10...,9
EMT trap, 10 ... 9
entering, 10-4
exceptions, 10-9
I/O, 1'0-13
illegal instruction trap, 10-9

1ndex-5

instructions, 10-3
interrupts, 10-9
lOT trap, 10-9
leaving, 10-5
memory management, 10-5
processor registers, 10-13
PSW, 10-2
register mapping, 10-5
registers, 10-2
reserved instrucion trap, 10-9
reserved instrucions, 10-4
stack, 10-2
synchronization, 10-13
T- bit, 10-1 0
trap instrucions, 10-4
TRAP trap, 10-9
unimplimented traps, 10-12
user environment, 10-2
Compatibility mode exception, 6-21
Complex data type, C-10
Condition Codes, 2-16, 6-5
Condition value, D-1
Condition vector, D-4
Condition, Exception
definition, C-3
Console functions, 9-19
Console Receive Control/Status
register (RXCS), 9-9
Console Receive Data Buffer
register (RXDE), 9-9
Console terminal registers, 9-8
Console Transmit Control/Status
register (TXCS), 9-10
Console Transmit Data Buffer
register (TXnB), 9-10
Constraints on I/O registers, ti-5
Context switching, 7-1
Context, process, 6-1, 6-3, 6-5,
6-32, 7-1 to 7-2
Context, system wide, 6-1, 6-32
Continue, 9-20
Control functions, 9-19
Control instructions, 4-74
Control Store, Micro
VAX-11/780, 9-18
Conventions
general, 1-2
in notation, 4-5
CRC, B-2
CRC - Calculate Cyclic
Redundancy Check, 4-163
CSS, Reserved to, 1-3
Currency sign, 4-195
Current frame Pointer Register,
2-14
Current mode, 6-5

Page
CUR_MOD - Current {vloae, 6-5
Customers, Reserved to, 1-3
CVTBD, E-2
CVTBD - Convert Byte to
D_floating, 4-44
CVTBf, E-2
CV'l'BF - Convert Byte to
F_floating, 4-44
CVTBG, E-2
CVTBG - Convert Byte to
G_floating, 4-44
CVTBH, £-2
CVTBH - Convert Byte to
H_floating, 4-44
CVTBL - Convert Byte to Long, 4-14
CVTBW - Convert Byte to word, 4-14
CVTDB, E-2
CVTDB - Convert D_floating to
Byte, 4-44
CVTDF, £-2
CVTDF - Convert D_floating to
£C'_floating, 4-44
CVTDH, E-2
CVTDH - Convert D_floating to
H_floating, 4-44
CVTDL, E-2
CVTDL - Convert D_floating to
Long, 4-44
CVTDW, £-2
CVTDW - Convert D_floating to
Word, 4-44
CVTF'B, E-2
CVTFB - Convert l'~floating to
Byte, 4-44
CVTF'D, E-2
CVTFD - Convert F~f'loating to
D_floating, 4-44
CVTFG, B-2
CVTF'G - Convert fi'--floating to
G_floating, 4-44
CVTFH, £-2
CVTFH - Convert f,--floating to
H_floating, 4-44
CVTFL, B-2
CVTFL - Convert F_floating to
Long, 4-44
CVTFW, E-2
CVTFW - Convert F_floating to
Word, 4-44
CVTGB, £-2
CVTGB - Convert G_floating to
Byte, 4..:.44
CVTGlo' , E-2
CVTGF - Convert G_floating to
F_floating, 4-44
CVTGH, E-2

Index-6

CVTGH - Convert G_floating to
H_floating, 4-44
CVTGL, E-2
CVTGL - Convert G_floating to
Long, 4-44
CVTGlti, £-2
CVTGW - Convert G_floating to
Word, 4-44
CVTHB, B-2
CVTHB - Convert H_floating to
Byte, 4-44
CVTHD, £-2
CVTHD - Convert I1_floating to
D_floating, 4-44
CVTHF, E-2
CVTHF
Convert H_floating to
F_floating, 4-44
CVTHG, E-2
CVThG - Convert H_floating to
G_floating, 4-44
CVTHL, E-2
CVTHL - Convert H_floating to
Long, 4-44
CVTHW, B-2
CVTHW - Convert H_floating to
Word, 4-44
CVTLB
Convert Long to Byte, 4-14
CVTLD, E-2
CVTLD - Convert Long to
D_floating, 4-44
CVTLF, E-2
CVTLF - Convert Long to
l'",-floating, 4-44
CVTLG, E-2
CVTLG - Convert Long to
G_floating, 4-44
CVTLH, E-2
CVl'LH - Convert Long to
H_floating, 4-44
CVTLP, E-2
CVTLP - Convert Long to Packed,

4-181
CVTLW - Convert Long to \aiord, 4-14
CVT1~P , E-2
CVTPL, £-2
CVTPL - Convert Packed to Long,

4-183
CVTPN, E-2
CVTPT - Convert PacKed
to Trailing Numeric, 4-185
CVTRDL, E-2
CVTRDL - Convert Rounded
D_floating to Long, 4-44
CVTRf'L, E-2
CVTRFL - Convert Rounded
t"_floating to Long, 4-44

Page
CVTRGL, E-2
CVTRGL - Convert Rounded
U_floating to Long, 4-44
CVTRHL, E-2
CVTRHL - Convert Rounded
H_floating to Long, 4-44
CVTSP - Convert Leading Separate
Numeric to Packed, 4-191
CVT~JB - Convert Word to Byte, 4-14
CVTWD, E-2
CVTWD - Convert Word to
D_floating, 4-44
CVTWF, E-2
CVTWF - Convert Word to
F_floating, 4--44
CVTWG, E-2
CVTWG - Convert Word to
G_floating, 4-44
CVTWH, E-2
CVTWH - Convert Word to
H_floating, 4-44
CVTWL - Convert Word to Long, 4-14
Cyclic redundancy check, 4-162
Data sharing, 8-1
Data synchronization, 8-1
Data type
character string, 2-7
decimal string, 2-12
floating, 2-4 to 2-5
integer, 2-1 to 2-3
packed decimal string, 2-12
string, 2-7, 2-12
variable length bit field, 2-6
Data type, operand, 3-2
byte, 3-2
D_floating, 3-2
F_floating, 3-2
G_floating, 3-2
H_floating, 3-2
longword, 3-2
octaword, 3-2
quadword, 3-2
\llord, 3-2
Data types, 2-1
in CALL standard, C-9
DEC
PDP-11 instruction, 1-3
DEC, Reserved to, 1-3
DECB
PDP-11 instruction, 1-1
DECB - Decrement Byte, 4-22
Decimal overflow, 2-11, 6-5
Decimal Scalar String Descriptor,
C-18
Decimal string dat~ type

Index-1

packed, 2-12
Decimal string divide by
zero trap, 6-15
Decimal string instructions, 4-166
Decimal string overflow trap, 6-15
DECL - Decrement Long, 4-22
DECW - Decrement Word, 4-22
Descriptor
in CALL standard, C-11
Descriptor prototype, C-11
Diagnostic software guidelines,
E-3
Digits
significant, 4-195
Directive call, C-1
Disable condition, D-5
Dispatch
CHMx, 6-43
Displacement addressing mode, 3-8
Displacement deferred indexed
addressing mode, 3-13
Displacement deferred indexed
mode, 3-13
Displacement mode, 3-8
DIV
PDP-11 instruction, 1-6
DIVB2 - Divide Byte 2 Operand,
4-26
DIVB3 - Divide Byte 3 Operand,
4-26
DIVD
PDP-11 instruction, 1-11
D1VD2, E-2
DIVD2 - Divide D_floating
2 Operand, 4-56
DIVD3, E-2
DIVD3 - Divide D_floating
3 Operand, 4-56
DIVIt'
PDP-11 instruction, 1-10
D1VF2, E-2
DIVF'2 - Divide r",-floating
2 Operand, 4-56
DIVF3, E-2
DIVF3 - Divide F_floating
3 Operand, 4-56
DIVG2, E-2
DIVG2 - Divide G_floating
2 Operand, 4-56
DIVG3, £-2
DIVG3 - Divide G_f1oating
3 Operand, 4-56
DIVH2, £-2
DIVH2 - Divide H_floating
2 Operand, 4-56
DIVH3, E-2

Page
DIVH3 - Divide h_floating
3 Operand, 4-56
Divide by zero fault, 6-16
Divide by zero trap, 6-15
DIVL2 - Divide Long 2 Operand,
4-26
DIVL3 - Divide Long 3 Operand,
4-26
DIVP, E-2
DIVP - Divide Packed, 4-179
DIVW2 - Divide Word 2 Operand,
4-26
DIVW3 - Divide Word 3 Operand,
4-26
Double data type, C-9
DQuble floating," 2-4
Double-precision Complex data
type, C-l0
Double-precision Floating data
type, C-9
DV - Decimal Overflow Enable,
2-17, 6-5
Dynamic string descriptor, C-12
D_floating, 2-4
D_f'loating data type,
operand, 3-2
EDIPTC examples, K-6
Edit instruction, 4-195
EDIT PC , E-2
EDITPC - Edit Packed to
Character String, 4-196
EDIV - Extended Divide, 4-28
Efficiency, bit
as a goal, 1-1
El'10DD, E-2
EMODD - Extended Multiply and
lntegerize D_floating, 4-58
EMODF, E-2
EMODF - Extended Multiply and
Integeri ze F'_floating, 4-58
EHODG, E-2
EMODG - Extended Multiply and
Integerize G_f1oating, 4-58
EMODH, B-2
EMODH - Extended Multiply and
Integerize H_floating, 4-58
El'1T

PDP-11 instruction, 1-7
EMUL - Extended Multiply, 4-25
EMULM - Multiprecision Multiply,
H-3
Enable condition, D-5
Entry mask, 4-95
EO$ADJUST_INPUT - Adjust Input
Length, 4-214

Index-8

- Blank Backwards
When Zero, 4-210
EO$CLEAR_SIGNIF - Clear
Significance, 4-213
EO$END - End Edit, 4-215
EO$END_F'LOAT - End Floating Sign,
4-209
EO$FILL - Store Fill, 4-205
EO$FLOAT - Float Sign, 4-207
EO$INSERT - Insert Character,
4-203
EO$LOAD_FILL - Load Fill
Register, 4-212
EO$LOAD_MINUS - Load Sign
Register If Ninus, 4-212
EO$LOAD_PLUS - Load Sign
Register If Plus, 4-212
EO$LOAD_SIGN - Load Sign
Register, 4-212
EO$.NOVE - Move Digits, 4-206
EO$REPLACE_SIGN - Replace Sign
when ~dnus Zero, 4-211
EO$SET_SIGNIF - Set Significance,
4-213
EO$STORE_SIGN - Store Sign, 4-204
Error severity code, D-1
Errors, processor, 8-4
ESP - Executive Stack Pointer,
6-34, 7-4
Establish a handler, D-4
Examine and Deposit, 9-21
Examples, K-1
Exception, 6-3
Exception condition, 6-1, D-1
Exception Condition
definition, C-3
Exceptions detected during
operand reference, 6-18
Exceptions detected during
the operation, 6-14
~xceptions occurring as the
instruction, 6-20
Executive memory access mode, 5-5
Executive Stack Pointer (ESP),
6-34
Extensibility
as a goal, 1-1
Extension, specifier, 3-8 to 3-9,
3-12
Extent, 1-2
External call standard, C-1
EXTV - Extract Field, 4-68
EXTZV - Extract Zero Extended
Field, 4-68
EO$BLA~K_ZERO

Page
Facility code, D-1
F'ADD
PDP-11 instruction, 1-6
Fail Return
in CALL standard, C-7
FALSE Boolean value, C-7
r"'ault, 6-1, 6-3
memory management, 5-17
Faults
arithmetic, 6-14
F'DIV
PDP-11 instruction, 1-7
FF - Floating Fault Enable, 6-5
FFC - Find First Clear, 4-72
FFS - Find First Set, 4-72
Field, 2-6
FIELD - field addressing
notation, 4-67
Field instructions, 4-67
Fill, 4-195
Fill character, 4-195
Fill register, 4-195
First machine, E-4
First part done, 6-5
Fixed string descriptor, C-12
Floating, 2-4 to 2-5
Floating currency symbol, 4-195
Floating data type, 2-4
Floating divide by zero fault,
6-16
Floating divide by zero trap, 6-15
Floating fault, 6-5
Floating output example, K-5
Floating overflow fault, 6-16
F'loating overflow trap, 6-15
F'loating point
immediate constant, 3-11
Floating point instructions, 4-35
Floating sign, 4-195
Floating underflow, 2-17, 6-5
Floating underflow fault, 6-16
Floating underflow trap, 6-15
FMUL
PDP-11 instruction, 1-7
FP - Current Frame Pointer
in CALL standard, C-7
FP - Current Frame Pointer
Register, 2-14
FPD - First Part Done, 6-5
Frame Pointer Register, Current,
2-14
FSUB
PDP-1,l instruction, 1-7
FU - Floating Underflow Enable,
2-17, 6-5
Function

Index-9

definition, C-3
Function value
in CALL standard, C-7, C-16
Functions, intrinsic
in CALL standard, C-6
F'_floating, 2-4
F_floating data type, C-9
F_floating data type, operand, 3-2
General addressing
assembler notation, B-3
General mode addressing, 3-4
General Registers, 7-4
General registers
in CALL standard, C-7
Generic opcode selection
assembler notation, B-6
Goals, 1-1
G_floating, 2-5
G_floating data type, C-9
G_floating data type,
operand, 3-2
HALT
PDP-11 instruction,'I-2
HALT - Halt, 4-104
Halt, console, 9-19
halt, processor, 6-26, 6-32,
6-36, 6-39, 6-42" ~-2, 9-19
VAX-l1 /780, 6-27
Halts, 9-20, 9-24
Bandler, condition, D-2
H_floating, 2-5
H_floating data type, C-10
H_floating data type,
operand, 3-2
1/0 instructions, F-16

I/O structure, 2-19, 6-4
ICCS - Interval Clock
Control/Status register, 9-14
ICR - Interval Count Register,
9-14
Immediate addressing mode, 3-5
Immediate constant
floating point, 3-11
integer, 3-10
Immediate indexed
addressing mode, 3-13
Immediate indexed mode, 3-13
Immediate mode, 3-5
INC
PDP-11 instruction, 1-3
Incarnation descriptor,
C-16 to C-17
INCE

Page
PDP-11 instruction, 1-7
INCB - Increment Byte, 4-19
INCL - Increment Long, 4-19
I~CW - Increment Word, 4-19
INDEX - Compute Index, 4-106
Index addressing mode, 3-12
Index mode, 3-12
Index register, 2-14
Indivisible operation
modify access, 3-18
Initialize, 9-21
Initiate exception or interrupt,
6-37
INSQHI - Insert Entry into Queue
at Head, Interlocked, 4-127
INSQTI - Insert Entry into Queue
at Tail, Interlocked, 4-130
INSQUE - Insert Entry in Queue,
4-119
Instruction buffer, 9-20
Instruction format, 2-19
Instruction operand formats, F-1
INSV - Insert Field, 4-69
Integer
immediate constant, 3-10
Integer data type, 2-1 to 2-3
Integer divide by zero trap, 6-15
Integer instructions, 4-7
Integer overflow, 2-17, 6-5
Integer overflow trap, 6-14
Interrupt, 6-1 to 6-3, 6-8
Interrupt AST Delivery, 7-8
Interrupt priority level, 6-5
Interrupt Priority Level (IPL),
6-2, 6-11
Interrupt process, 6-8
Interrupt stack, 6-5
Interrupt stack not valid halt,
6-26
Interrupt Stack Pointer (ISP),
6-34
Interrupt structure, 2-20
Interrupt, Process Scheduling, 7-8
Interrupts, 8-4
Interrupts, Process Structure, 7-8
Interval clock, 9-14
Interval Clock Control/Status
register (ICCS), 9-14
Interval Count Register (ICR),
9-14
Intrinsic functions
in CALL s"tandard, C-6
lOT
PDP-11 instruction, 1-2
IPL - Interrupt Priority Level,
6-2, 6-5, 6-10 to 6-11

Index-10

IS - Interrupt Stack in use, 6-5,

6-33
ISP - Interrupt Stack POinter,
6-34
IV - Integer Overflow Enable,
2-17, 6-5
Jl1P

PDP-11 instruction, 1-2
Jump, 4-78
JSB - Jump To Subroutine, 4-93
J,sR
PDP-11 instruction, 1-3
JHP -

Kernel instruction set, E-2
Kernel memory access mode, 5-5
Kernel software guidelines, E-3
Kernel stack not valid abort, 6-26
Kernel Stack Pointer (KSP), 6-34
KSP - Kernel Stack Pointer, 6-34,
7-4
Label descriptor, C-17
Label incarnation descriptor, C-17
LDCDF
PDP-11 instruction, 1-11
LDCFD
PDP-ll instruction, 1-11
LDCID
PDP-11 instruction, 1-11
LDCIf-'
PDP-l1 instruction, 1-11
LDCLD
PDP-11 instruction, 1-11
LDCLF
PDP-11 instruction, 1-11
LDD
PDP-11 instruction, 1-10
LDEXP
PDP-11 instruction, 1-11
LDt"
PDP-l1 instruction, 1-10
LDF'PS
PDP-11 instruction, 1-9
LDPCTX - Load Process Context, 7-9
Leading separate sign, 4-166,
4-189, 4-191
Leading zero, 4-213
Literal addressing mode, 3-10
Literal mode, 3-10
Local storage
in CALL standard, C-8
LOCC, E-2
LOCC - Locate Character, 4-156
Logical instructions, 4-7
Longword, 2-2

Page
PDP-11 compatibility, 2-2
Longword data type, operand, 3-2
Longword displacement
addressing mode, 3-7
Longword displacement deferred
addressing mode, 3-8
Longword displacement deferred
indexed addressing mode, 3-13
Longword displacement deferred
indexed mode, 3-13
Longword displacement deferred
mode, 3-8
Longword displacement indexed
addressing mode, 3-13
Longword displacement indexed
mode, 3-13
Longword displacement mode, 3-7
Longword Integer data type, C-9
Longword Logical data type, C-9

M - Modify bit, 5-8
Machine check exception, 6-26
Maintenance functions, 9-21
Map Enable Register (MAPEN), 5-16
NAPEN - Map Enable Register, 5-16
MAPEN - Memory ~~pping Enable, 5-7
MARK
PDP-11 instruction, 1-4
l'1ATCHC, B-2
MATCHC - Match Characters, 4-160
MBRK - Micro Program Breakpoint
Address register, 9-19
1"18Z, 1-2
MCOMB - Move Complemented Byte,
4-12
l"1CO[VlL - Move Complemented Long,
4-12
MCOMw - Move Complemented Word,
4-12
Memory access mode, 5-5, 6-5
Executive, 5-5
Kernel, 5-5
Supervisor, 5-5
User, 5-5
Memory management control, 5-16
Memory management enable, 5-16
Memory management exceptions, 6-17
Memory management faults, 5-17
hemory fvlapping Enable (HAPEN), 5-7
MFPD
PDP-11 instruction, 1-9
MFPI
PDP-11 instruction, 1-4
MFPR - Move From Processor
Register, 9-5
HFPS

Index-11

PDP-11 instruction, 1-9
Micro Control Store
VAX-11/780, 9-18
Micro Program Breakpoint Address
register (MBRK), 9-19
Ninimum console, 9-21
MINU - minimum unsigned notation,
4-5
Niscellaneous instructions, 4-103
[vii ssing argument
in CALL standard, C-5
MME - Memory ~~pping Enable, 5-7
MNEGB - Move Negated Byte, 4-11
MNEGD, E-2
l\il~EGD - Move Negated D_floating,
4-43
NNEGfi' , £-2
MNEGF - Nove Negated F_floating,
4-43
MNEGG, B-2
MNEGG - lVlOve Negated G_floating,
4-43
l"1NEGH, E-2
lvlNEGH - Move Negated H_floating,
4-43
lVlNEGL - Move Negated Long, 4-11
NNEGW - Hove Negated Word, 4-11
IvlODD

PDP-11 instruction, 1-10
5-5, 6-5
compatibility, 6-5
Mode changing instructions, 6-42
Mode, memory access, 5-5, 6-5
MODF
PDP-11 instruction, 1-10
Modify access type, operand, 3-2,
3-17
synchronization, 3-18
Modify bit, 5-8
MOV
PDP-11 instruction, 1-5
MOVAB - Move Address Byte, 4-65
MOVAD - Move Address D_floating,
4-65
MOVAF - Move Address F~floating,
4-65
MOVAG - Move Address G_floating,
4-65
MOVAH, E-2
MOVAH - Move Address H_floating,
4-65
MOVAL - MO,ve Address Long, 4-65
MOVAO - M-ove. Address Octa, 4-65
MOVAQ - Move Address Quad, 4-65
MOVAW - Move Address Word, 4-65
MOVB

l'tlode,

Page
PDP-11 instruction, 1-9
MOVB - Move Byte, 4-8
MOVC3, E-3
MOVC3 - Move Character 3 Operand,
4-140
MOVC5, E-3
MOVC5 - Move Character 5 Operand,
4-140
1"10VD, £-2
MOVD - Move D_floating, 4-41
MOVF, E-2
HOVF - Move F_floating, 4-41
MOVG, £-2
MOVG - Move G_floating, 4-41
MOVH, E-2
MOVH - Move H_floating, 4-41
MOVL - Move Long, 4-8
MOVO, E-2
MOVO - Move Octa, 4-8
MOVP, E-2
MOVP - Move Packed, 4-169
MOVPSL - Move PSL, 4-110
MOVQ - Move Quad, 4-8
MOVTC, E-2
MOVTe - Move Translated
Characters, 4-144
MOVTDe, E-2
MOVTUC - Move Translated
Until Character, 4-147
MOVW - Move Word, 4-8
MOVZBL - Move Zero-Extended
Byte to Long, 4-13
MOVZBw - Move Zero-Extended
Byte to word, 4-13
MOVZWL - Move Zero-Extended
Word to Long, 4-13
MTPD
PDP-11 instruction, 1-9
MTP1
PDP-11 instruction, 1-4
MTPR - Move To Processor
Register, 9-4
MTPS
PDP-11 instruction, 1-8
MUL
PDP-11 instruction, 1-5
MULB2 - Multiply Byte 2 Operand,
4-24
MULB3 - Multiply Byte 3 Operand,
4-24
MULD
PDP-11 instruction, 1-10
MULD2, E-2
MULD2 - Multiply D_floating
2 Operand, 4-54
MULD3, E-2

Index-12

MULD3 - Multiply D_floating
3 Operand, 4-54
MULF
PDP-11 instruction, 1-10
l'1ULF2, E-2
MULF2 - Multiply F_floating
2 Operand, 4-54
MULF3, E-2
1'1DLF3 - Mul tiply {t'_floating
3 Operand, 4-54
MULG2, £-2
MULG2 - Nultiply G_floating
2 Operand, 4-54
lv1ULG3, E-2
MULG3 - Multiply G_floating
3 Operand, 4-54
rviULH2, E-2
MULH2 - Multiply H_floating
2 Operand, 4-54
MULH3, £-2
MULH3 - Multiply H_floating
3 Operand, 4-54
MULL2 -'Multiply Long 2 Operand,
4-24
MULL3 - Multiply Long 3 Operand,
4-24
NULP, £-2
MULP - Multiply Packed, 4-177
Multiple active signals, D-13
Nultiprecision arithmetic, H-1
MULW2 - l'1ul tiply word 2 Operand,
4-24
MULw3 - Multiply Word 3 Operand,
4-24
N - Negative Condition Code,
2-16, 6-5
N condition code, 2-16, 6-5
NEG
PDP-11 instruction, 1-3
NEGB

PDP-11 instruction, 1-7
NEGD
PDP-11 instruction, 1-10
l~EGF

PDP-11 instruction, 1-10
Next Interval Count
Register (NICH), 9-14
Nibble, 2-12
NICR - Next Interval Count
Register, 9-14
NOP
PDP-11 instruction, 1-2
NOP - No Operation, 4-113
as a diagnostic scope point,
9-19

Page
Notation

(), 3-3
addressing modes, 3-3
FIELD - field addressing, 4-61
MINU - minimum unsigned, 4-5
OA - operand address, 3-3
operand specifier, 4-3, F-9
operation description, 4-4
register, 2-14
REM - remainder, 4-5
Rn, 2-14
R[n], 2-14
SEXT - sign extend, 3-3, 4-5
ZEXT - zero extend, 3-3, 4-5
\, 1-3
t}, 3-3
Numbering, 1-2
Numeric string data type, C-10
OA - operand address notation, 3-3
Object Time System
definition, C-3
Octaword, 2-3
Octaword data type, operand, 3-2
Octaword Integer data type, C-9
Octaword Logical data type, C-9
Opcode assignments, F-12
Opcode formats, 3-1
Opcode reserved to customers
fault, 6-20
Opcode reserved to DIGITAL Fault,
6-20
Operand format summary, F-1
Operand specifier, 3-2
Operand specifier access type, 3-2
Operand specifier conventions,
3-11
Operand specifier data type, 3-2
Operand specifier notation, F-9
Operand specifier, base, 3-12
Operand, primary, 3-12
Operating system
integrity, J-1
reliable, J-1
secure, J-1
Operator interaction, 9-19
Orthogonality
as a goal, 1-1
OTS
definition, C-3
Overflow, 6-4 to 6-5,
6-14·to 6-16, 6-35
stack, 6-26

Index-13

PO Base Register, 7-4
PO Base Register (POBR), 5-12
PO Length Register (POLR), 5-12
PO Limit Register, 7-4
PO Page Table (POPT), 5-12
PO Region, 5-12
POER - PO Base Register, 5-12, 1-4
POLR - PO Length Register, 5-12
POLR - PO Limit Register, 1-4
POPT - PO Page Table, 5-12
P1 Base Register, 7-5
P1 Base Register (P1BR), 5-14
P1 Length Register (P1LR), 5-14
P1 Limit Register, 1-5
P1 Page Table (P1PT), 5-14
P1 Region, 5-14
P1BR - P1 Base Register, 5-14, 7-5
P1LR - P1 Length Register, 5-14
P1LR - P1 Limit Register, 7-5
P1PT - P1 Page Table, 5-14
Packed, 4-193
Packed decimal
instructions, 4-166
Packed decimal string, 2-12
Packed decimal string data type,
C-l0
Page, 5-2
Page frame number field, 5-ti
Page Table Entry (PTE), 5-8
Parentheses
as a notation, 3-3
Part done, 6-5
PC - Program Counter Register,
2-14
PC - Program Counter register
in CALL standard, C-1
PC - Program Counter Register
in process context, 1-4
PCB - Process Control Block, 7-2
PCBS - Process Control Block
Base, 7-2
Performance monitor enable, 7-5
PFN - Page Frame Number field, 5-8
PM~ - Performance ~bnitor Enable,
1-5
POLYD, E-2
POLYD - Polynomial Evaluation
D_floating, ·4-60
POLYF, E-2
POLYF - Polynomial Evaluation
F_floating, 4-60
POLYG, E-2
POLYG - Polynomial Evaluation
G_floating, 4-60
POLYH, E-2
POLYH - Polynomial Evaluation
H_floating, 4-60

Page
POPR - Pop Registers, 4-109
Power fail, 8-2
Precision arithmetic, H-1
Preserved registers
in CALL standard, C-8
Previous mode, 6-5
Primary operand, 3-12
Priority level, 6-5
Probe accessibility, 5-20, 5-22
PROBER - Probe Read
accessibility, 5-20
PROBEW - Probe Write
accessibility, 5-20
Procedure
definition, C-3
Procedure activation, D-2
Procedure CALL, C-1
Procedure call instructions, 4-95
Procedure calling interface, 4-95
Procedure descriptor, C-16
Procedure incarnation descriptor,
C-16
Process context, 1-1
Process control block, 1-2
Process scheduling, 1-1
Process Space, 5-2, 5-11
Process, definition, 7-1
Processor Errors, 8-4
Processor Internal Register
space, 9-1
Processor option, E-2
Processor ~egisters, 9-6
Processor Status Longword (PSL),
6-5
Processor Status Word, 2-16
Processor type, 9-8
Program counter
in process context, 7-4
Program Counter Register, 2-14
Program status longword
in process context, 1-4
Programming examples, K-1
PROT - Protection field, 5-8
Protection, 5-J
check, 4-212
Protection Code, 5-5
Protection field, 5-8
PRV.YIOD - Previous l";lOde, 6-5
PSL - Processor Status Longword,
6-5
PSL - Program Status Longword
in process context, 7-4
PSw - Processor Status word,
2-16, 6-3, 6-5, 6-19
PTE - Page Table Entry, 5-8
PUSHAB - Push Address Byte, 4-66

Index-14

PUSHAD - Push Address D_floating,
4-66
PUSHA£" - Push Address F_floating,
4-66
PUSHAG - Push Address G_floating,
4-66
PUSHAH, E-2
PUSHAH - Push Address H_floating,
4-66
PUSHAL - Push Address Long, 4-66
PUSHAQ - Push Address Quad, 4-66
PUSHAw - Push Address Word, 4-66
PUSHL - Push Long, 4-9
PUSHR - Push Registers, 4-108
Quadruple-precision Complex data
type, (;-10
Quadruple-precision Floating data
type, C-10
Quadword, 2-3
Quadword data type, operand, 3-2
Quadword lnteger data type, C-9
Quadword Logical data type, C-9
Queue instructions, 4-114

RO - Function Value Register
in CALL standard, C-7
R1 - Function Value Register
in CALL standard, C-7
Range
as a goal, 1-2
Range of values, 1-2
Read access type, operand, 3-2,

3.. 17

Register
fill, 4-195
sign, 4-195
Register addressing mode,
3-4 to 3-5
Register deferred
addressing mode, 3-4
Register deferred indexed
addressing mode, 3-13
Register deferred indexed mode,
3-13
Register deferred mode, 3-4
Register mode, 3-4 to 3-5
Register usage, 2-14, C-1
Registers
VAX-11 Series, 9-6
VAX-11/7BO Specific, 9-7
REI - Return from Exception or
Interrupt, 6-40
Relative addressing
assembler notation, B-2
Relative vs. absolute

Page

Index-15

assembler notation, B-3
SCANC - 5can Characters, 4-152
SCBB - System Control Block Base,
Reliable operating systems, J-l
REM - remainder notation, 4-5
6-27
Scheduling, process, 7-1
REMQHI - Remove Entry from Queue
Secure operating systems, J-1
at Head, Interlocked, 4-133
REMQTI - Remove Entry from Queue
Self-relative queues, 4-123
Separate Sign, leading, 4-166,
at Tail, Interlocked, 4-136
REMQUE - Remove Entry from Queue,
4-189, 4-191
Separation of procedure and data,
4-121
2-19
RhSERVED, 1-3
Serial number, 9-8
Reserved addressing mode fault,
Serialization of notification
6-18
of multiple events, 6-35
Reserved descriptors, C-18
SET CC
Reserved operand exception, 6-18
PDP-11 instruction, 1-2
RESET
PDP-l1 instruction, 1-2
SETD
Restart, system, 9-24
PDP-l1 instruction, 1-9
SETF
Restartability, 8-3
RET - Return from Procedure, 4-101
PDP-11 instruction, 1-9
Revert handler, D-5
SETI
PDP-11 instruction, 1-9
Revision level, 9-8
SETL
HOL
PDP-l1 instruction, 1-4
PDP-11 instruction, 1-9
Severe_error severity code, D-1
ROLB
Severity code, D-1
PDP-11 instruction, 1-8
ROR
SEXT - sign extend notation, 3-3,
PDP-l1 instruction, 1-4
4-5
RORB
Sharing, 5-23, 8-1
SID - System Identification, 9-8
PDP-l1 instruction, 1-8
ROTL - Rotate Long, 4-34
Sign, 4-195
currency, 4-195
RSB - Return From Subroutine, 4-94
RTl
Sign character, 4-195
PDP-l1 instruction, 1-2
Sign register, 4-195
RTS
Signal condition, D-2
PDP-l1 instruction, 1-2
SIGNAL routine, D-6
RTT
Significance, 4-195
Significance indicator, 4-195,
PDP-11 instruction, 1-2
RXCS - Console Receive
4-213
Significant digits, 4-195
Control/Status register, 9-9
SIN example, K-4
RXDB - Console Receive
Single instruction, 9-21
Data Buffer 'register, 9-9
Single-precision Floating data
type, C-9
Saved PC, 6-3, 6-5, 6-14, 6-18,
SIRR - Software lnterrupt
6-22, 6-35 to 6-37
Request Register, 6-2, 6-8,
Saved PSL, 6-3, 6-5, 6-14,
6-10 to 6-11
6-21 to 6-23, 6-35 to 6-37
SISR - Software Interrupt
Saved TP, 6-22 to 6-23, 6-25,
Summary Register, 6-10
6-35 to 6-37
SBC
SKPC, E-2
SKPC - Skip Character, 4-158
PDP-11 instruction, 1-4
SLR - System Length Register, 5-9
SBCB
PDP-l1 instruction, 1-8
SOB
SBR - System Base Register, 5-9
PDP-11 instruction, 1-7
SOBGEQ - Subtract One and Branch
SBWC - Subtract With Carry, 4-23
Greater Than or Equal, 4-89
Scalar descriptor, C-12
SOBGTR
- Subtract One and Branch
SCANC, E-2
Greater Than, 4-90

Page
Software interrupt, 6-10
Software Interrupt
Request Register (SIRR), 6-10
So ftware Interrupt
Summary Register (SISR), 6-10
Sort example, K-1
SP - Stack Pointer Register, 2-14
SP - Stack Pointer register
in CALL standard, C-7
SPANC, E-2
SPANC - Span Characters, 4-154
Specifier extension, 3-8 to 3-9,
3-12
SPL
PDP-11 instruction, 1-2
SPT - System Page Table, 5-9, 5-22
SSP - Supervisor Stack POinter,
6-34, 7-4
Stack alignment, 6-33
Stack frame, 4-95
Stack pointer
in process context, 7-4
Stack pointer images, 9-2
Staok Pointer Register, 2-14
Stack residency, 6-32
Stack unwinding, C-8
Stack usage
in CALL standard, C-8
Stack, switch, 6-32, 6-37, 6-40
Start~ 9-21
Status return value
in CALL standard, C-7

STCDF
PDP-11 instruction, 1-11
STCDI
PDP-11 instruction, 1-11
STCDL
PDP-11 instruction; 1-11
STCFD
PDP-11 instruction, 1-11
STeFl
PDP-11 instruction, 1-11
STCFL
PDP-11 {nstruction, 1-11

STD
PDP-11 instruction, 1-10
STEXP
PDP-11 instruction, 1-11
STft'

PDP-11 instruction, 1-10
STFPS
PDP-11 instruction, 1-9
STOP routine, D-6
String data type
character, 2-7
packed decimal, 2-12

Index-16

String descriptor, C-12 to C-13
as operand, 4-139, 4-166
string instructions, 4-166
String instructions
character, 4-139
cyclic redundancy check, 4-162
decimal, 4-166
string instructions
string instructions, 4-185,
4-187
STST
PDP-l1 instruction f 1-9
SUB

PDP-11 instruction, 1-9
SUBB2 - Subtract Byte 2 Operand,
4-21
SUBB3 - Subtract Byte 3 Operand,
4-21
SUBD
PDP-11 instruction, 1-10
SllBD2, B-2
SUBD2 - Subtract D_floating
2 Operand, 4-52
SUBD3, B-2
SUBD3 - Subtract D_floating
3 Operand, 4-52
SUbF
PDP-11 instruction, 1-10
SUBF'2, E-2
SUB14'2 - Subtract F'_floating
2 Operand, 4-52
SUBF'3, E-2
SUBF3 - Subtract F_floating
3 Operand, 4-52
SUBG2, E-2
SUBG2 - Subtract G_floating
2 Operand, 4-52
SUBG3, E-2
SUBG3 - Subtract G_floating
3 Operand, 4-52
SUBH2, E-2
SUBH2 - Subtract h_floating
2 Operand, 4-52
SUBH3, E-2
SUBH3 - Subtract H_floating
3 Operand, 4-52
SUBL2 - Subtract Long 2 Operand,
4-21
SUBL3 - Subtract Long 3 Operand,
4-21
SUBN - Nultiprecision Subtract,
H-2
SUBP4, B-2
SUbP4 - Subtract Packed
4 Operand, 4-175
SUbP6, E-2

Page
SDBP6 - Subtract Packed
6 Operand, 4-175
Subroutine
definition, C-3
Subscript range trap, 6-16
Subsettable instructions, E-2
SUBW2 - Subtract Word 2 Operand,
4-21
SUBW3 - Subtract word 3 O'perand,
4-21
Success heturn
in CALL standard, C-7
Success severity code, D-1
Summary, 1-1
Supervisor memory access mode, 5-5
Supervisor Stack Pointer (SSP),
6-34
SVPCTX - Save Process Context,
7-11
SwAB
PDP-l1 instruction, 1-2
Switching, context, 7-1
SXT
PDP-11 instruction, 1-4
Synchronization, 8-1
modify access, 3-18
System Base Register (SBR), 5-9
System bootstrapping, 9-22
System Control Block Base (SCEB),
6-27
System Identification
register (SID), 9-8
System Length Register (SLR), 5-9
System Page Table (SPT), 5-9, 5-22
System Region, 5-9
System restart, 9-24
System software guidelines, E-3
System Space, 5-2, 5-9
1 - Trace Enable, 6-5
T - Trace Trap Enable, 2-17
TBIA - Translation Buffer
Invalidate All Register, 5-17
TBIS - Translation Buffer
Invalidate Single Register,
5-17
Temporary registers
in CALL standard, C-7
Terminology
general, 1-2
Time-of-Year Register (TODR), 9-13
to Leading Separate Numeric, 4-189
to Packed, 4-187
TODR - Time-of-Year Register, 9-13
TP - Trace Pending, 6-5
Trace, 6-5, 6-22

Index-17

Trace pending, 6-5
Trace trap, 2-17
Translation buffer, 5-17
Translation Buffer Invalidate
All Register (TBIA), 5-17
Translation Buffer Invalidate
Single Register (TBIS), 5-17
Translation not valid fault, 6-17
Translation, address, 5-7
Trap, 6-1, 6-3
TRAP
PDP-l1 instruction, 1-7
Traps
arithmetic, 6-14
TRUE Boolean value, C-7
TST
PDP-11 instruction, 1-4
1'STB

PDP-11 instruction, 1-8
IST8 - Test Byte, 4-16
TSTD, E-2
PDP-11 instruction, 1-9
T3TD - Test D_floating, 4-49
TSTF, E-2
PDP-11 instruction, 1-9
TSTF - Test F'_floating, 4-49
TSTG, E.-2
TSTG - Test u_floating, 4-49
TSTH, E-2
TSTH - Test H_floating, 4-49
TSTL - Test Long, 4-16
/~~
TSTW - Test Word, 4-16
TXCS - Console Transmit
Control/Status register, 9-10
TXDB - Console Transmit
Data buffer register, 9-10
Type, processor, 9-8
UNDEFINED, 1-2
UNIBUS, 6-2, 6-9, 8-1
Unmapped system, 5-16
UNPREDICTABLE, 1-2
Unsigned integer, 2-1 to 2-2
UNWIND routine, D-12
User memory access mode, 5-5
User Stack Pointer (USP), 6-34
USP - User Stack POinter, 6-34,
7-4

v - Overflow Condition Code,
2-16, 6-5
V - Valid bit, 5-8
V condition code, 2-16, 6-5
Valid bit, 5-8
Validating address arguments, 5-19
Variable length bit field

Page
bytes referenced, 2-7
data type, 2-6
Variable length bit field
instructions, 4-67
Varying string descriptor, C-13
VAX-11/780 Accelerator, 9-16
VAX-11/780 Micro Control Store,
9-18
Vector, 6-2, 6-20 to 6-21,
6-26 to 6-27, 6-32 to 6-37
interrupt, 6-8
Vector, condition, D-4
Virtual address, 2-1
Virtual Address Space, 5-2
Virtual Page Number, 5-3
VPN - Virtual Page Number, 5-3
WAIT
PDP-l1 instruction, 1-2
Warning severity code, D-1
WCSA - Writable .Control Store
Address register, 9-18
wCSD - Writable Control Store
Data register, 9-18
Word, 2-2
Word data type, operand, 3-2
Word displacement
addressing mode, 3-7
Word displacement deferred
addressing mode, 3-8
Word displacement deferred
indexed addressing mode, 3-13
Word displacement deferred
indexed mode, 3-13
Word displacement deferred mode,

3-8

Word displacement indexed
addressing mode, 3-13
Word displacement indexed mode,
3-13
Word displacement mode, 3-7
Word Integer data type, C-9
Word Logical data type, C-9
Writable Control Store Address
register (WCSA), 9-18
Writable Control Store Data
register (wCSD), 9-18
Write access type, operand, 3-2,

3-17
XFC - Extended Function Call,
4-:-105
XOR
PDP-ll instruction, 1-6
XORB2 - Exclusive OR Byte
2 Operand, 4-33

Index-1b

XORB3 - Exclusive OR Byte
3 Operand, 4-33
XORL2 - exclusive OR Long
2 Operand, 4-33
XORL3 - Exclusive OR Long
3 Operand, 4-33
XORW2 - Exclusive OR word
2 Operand, 4-33
XORW3 - Bxclusive OR Word
3 Operand, 4-33
Z - Zero Condition Code, 2-16, 6-5
Z condition code, 2-16, 6-5
Zero
leading, 4-213
ZEXT - zero extend notation, 3-3,
4-5
Zoned numeric string data type,
C-10
\ (backslant)
as a notation, 1-3