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Document:	KY11-LB Programmer's Console/Interface Module Operation and Maintenance Manual
Order Number:	EK-KY1LB-MM
Revision:	001
Pages:	118
Original Filename:

OCR Text

KY11-LB programmer’s

console/interface module
operation and maintenance
manual

dlifgliltiall

EK-KY1LB-MM-001

KY11-LB programmer’'s
console/interface module
operation and maintenance

manual

digital equipment corporation « maynard, massach'usetts

1st Edition, January 1977

Copyright © 1977 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment é'orp'oréition: assumes n'o»re‘é:,pc'm.'~ :
sibility for any errors which may appear in this-

manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000

computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

‘DECUS

RSTS

DIGITAL

TYPESET-8

DECsystem-10
DECSYSTEM-20
-

MASSBUS

PDP

TYPESET-11
"UNIBUS

CONTENTS

k| jd fd
ek
o

-l>-l>u~)l'\)'—‘l

CHAPTER 1

OPERATING CHARACTERISTICS

INTRODUCTION . .«

vttt

GENERAL DESCRIPTION

FUNCTIONAL DESCRIPTION
SPECIFICATIONS

1.4.4

Environmental Specifications

2.2.2
2.3

e e e

e e e e e

e e e

e e i

e e e|

e e e e e

00000

Flectrical Specifications

- 2.2.1

e e

Mechanical Specifications

e e d

. .. . . o

1 42

e e e

M7859 Interface Module Performance Spec;1f1cat10ns

1.4.3

CHAPTER 2

. . ........... L

. . ... . .

.. . ... ..

. . . . . . . . . .

e e e e

..o

. . . . .. ... ... ..o 0oL

" FUNCTIONAL DESCRIPTION
INTRODUCTION

. .. ... ... e

e e e eS

PROGRAMMER’S CONSOLE KEYPAD FUNCTIONS/

CONTROLS AND INDICATORS
‘Console Mode

e e e e

. .. ... ... e

Maintenance Mode

e e e ee e

. . . .. .. e e e

HARDWARE ORGANIZATION

e e
e

e e i e e e e
e e e e e e.

e e e e e e.

... ..... I P

2.4

MICROPROCESSOR INSTRUCTION SET T

'CHAPTER 3

INTERFACE MODULE

3.1

MICROPROCESSOR . . . i

v et vt

e e e e it e ete e e e e

3.1.1

General Organization . . . ... .. ...... e e

3.1.2

State Control

3.1.3

Microprocessor Timing . . . ..
. . . .. .. ... .... . e e e e e

3.14

Transition State Diagram . . . . . . . . ¢ o v v b

3.1.5

3.2

. . . . . . .

System Start-Up

. . . . . . v v v v v v

Address Register

. . . . .. e e e

3.2.2

Bus Address Register

3.2.3

Switch Register

3.2.4

Data
Bus Control

. . . ... ..

3.2.5

Unibus Control

. . . . ... ...

4.1

o v .. e e

DATA AND INSTRUCTION FORMATS

MICROPROCESSOR INSTRUCTIONS

- 4.2.1

Index Register Instructions

e e e

e e e e e e e

e e e . e e e e e i e e he e e

- MICROPROCESSOR INSTRUCTION DESCRIPTION

4.2

e e e e e e

. . . . .. . . v i v it i e

. . . .. . .. e

e e e . .

e e e e e e

INTERFACE MODULE REGISTERS AND CONTROLS e e

3.2.1

CHAPTER 4

e e e e e |

e e e e e e e e e e e e e e e e e e e e

. .+ © « v o v e

. . . ¢

oo vt

. . . . . . ...

e e
e .L

e e v
0oL

4.2.2

Accumulator Group Instructions . . . . ., . . . . ... ..o

4.2.3

Program Counter and Stack Control Instructlons

4.2.4

Input/Output Instructions

4.2.5

Machine Instruction

e e e e e e e e.

. . .. ... ... ... e

. . . . . .. e i e e e e e e

e e
e e e e e e

CONTENTS (Cont)
Page

CHAPTER 5
5.1

5.2.1
5.2.2

5.3
15.3.1
5.3.3

5.3.4
5.3.5

5.3.6

5.3.7

53.8

539

'5.3.10
5.3.11
5.3.12

5.3.14
5.3.15

5.3.16

5.3.16.1
15.3.16.2

- CHAPTER 6
6.1
6.2

6.4

CHAPTER 7
7.1
7.2

INTERFACE MODULE DETAILED LOGIC DESCRIP’TION

PROGRAMMER’S CONSOLE KEYPAD FUNCTION SEQUENCES ..... - 5-3
oo e 5-3
oo
Console Mode Key Functions .. . . . . . oo
Maintenance Mode Key Functions . . e e e e e e e e e e e e e 5-5
e e e e e e e 5-5
R
- DETAILED LOGIC DESCRIPTION
- 5-5
v v v i v e e e e ee e e
Clock CIrCUItFY &«
3D
e
e
Power-Up Logic/Interrupt . . . « o o't v v v vt e
5-6
e eMicroprocessor . . . . . . . e e
50
e
e e
e
e
v
v
v
v
v
v
v
v
.
.
.
Decoder
Timing State
5-6
I
..
.
.
.
Address Register . . . .
1Y
R
St U A
1:00)) S
5-7
UP
RAM ........ e e e e e e e [P
. . . e e e e 6 e i e e e e e e 5-7
Switch Register- . . . .« ¢
T 5-7
Switch Register Address Decode. Loglc T

5-8

e e e

e ee

Bus Address Register . . . . .. .. .. e

Logic . . . . .. e
Data Bus Control

Unibus Control . . . & &« i v i e i e e e e e e e e e e e e e e e e 5-10
Keypad Scan LOIC . « v @ v ve v oo e v e e e e e e e 5-10
Indicator Logic . . . . . . o« o i i e e e e

Buffers . . . . v v v v i e

Tristate Buffers (8093) e

e e e e e e e

e .
e

e 5-11

e e 5-11

‘Tristate Transceivers (8833) e
o

| CONSOLE MODE OPERATION

e e e 5-11

INTRODUCTION ee e e e e e e e e e e e i e e s e e e e e e e e 6-1
CONSOLE KEY. OPERATIONS e e e e e e e hee e e e e e e . 6-1

e e .. ... 65
ES . . . . . i i it e e e e e
ON OPERATION
NOT
... 66
EXAMPLES OF CONSOLE SEQUENCES . . .. . vt v v v
R

MAINTENANCE MODE OPERATION

INTRODUCTION . ... ... ... ... .. e e e e e e e e e e e 7-1
................ 7-1
MAINTENANCE MODE KEY OPERATIONS

7.3

CHAPTER 8

8.1
8.2

KY11-LB MAINTENANCE

PRELIMINARY CONSIDERATIONS e e

M7859FAILURES

T S

e e e e

e e e e e .. ..

e e e ... 82

CONTENTS (Cont)

CHAPTER 9

KY11-LB INSTALLATION

9.1

KYII-LBDESCRIPTION . . . . ..t oiiii

9.2

CPUBOXTYPE

...
. ...e e e e e e e e e e e e e e e e e |

9.3

CPUDIFFERENCES

9.4

BA11-L 13.3 CM (5-1/4 INCH BOX) INSTALLATION . .. .........

. . ... .............. e,

9.5

BA11-K 26.7 CM (10-1/2 INCH BOX) INSTALLATION

9.6

MAINTENANCEMODE HOOK-UP

APPENDIX A

KY11-LB MICRO-CODE LISTINGS

APPENDIX B

IC DESCRIPTIONS

. ... .......

. . . . .. .. .. ... .........

FIGURES

Figure No.
1-1

- Title

Programmer’s Console/Interface — PDP-11/04/34 Conflguratlon

1-2

Interface Module (M7859)

2-1

KY11-LB Logical Organization e e e

2-2

KYI1-LBKeypad

2-3

Interface Module Detailed Block Dlagram

...... .

. . . . . . . . . . . ...

... ...........e

e e e e

e e e e e

e e

e e e e e e e e e e e e e e e e

3-1

Microprocessor Signal Interface

3-2

Timing Diagram — Microprocessor Instruction

3-3

Transition State Diagram

e e

5-1

RAM Address Allocations . . . . . . . . . . .
v i i i
Keypad Image . . . . . . . . v i i i i e e e e e e e e e e

e e e e e
e e

. . . . . . . . . .. .. ... . .. .. ...

. . . . . .. . .. .. ... .

. . . ... ... ... e

8-1

Clock Waveforms

9-1

M7263

. . . . ... e e e e e e e e e e

9-2

M7266

. . ... ... ........ e e e e e e e e e e e e e e e e e e

9-3

Cables

. ..... ... ......... e

9-4

BALL-L

9-5

. . .

. ...
. .. e

e e e e e e e. e

e e

e e e

e e

e e e e e e
e e e

e
e e e e e e e e e e

e e e e e e e e e

TableNo.

Tite

2-1

KY11-LB Controls and Indicators . )

3-1

State Control Coding

CycleCoding

- 5-1

RAM Function Address Assignments

. . ..

... .. e e

. . ... ... ... .. ... ...

. . .

.. ...

Page

e .

eoL

..
... .........

2-3
32

3-3
5-2

KY11-LB PROGRAMMER’S CONSOLE/INTERFACE MODULE OPERATION

(=L,

PREFACE

The KY11-LB Programmer’s Console/Interface Module Operation and Maintenance Manual provides
the information required to operate this option in console or maintenance mode. The manual also
presents a detailed theory of operation of the interface module hardware and software components,
data on the utilization of the programmer’s console as a maintenance tool for the PDP-11/04/34
processors, and information on the troubleshooting and mamtenance of the 1nterfaee module 1tself
The informationis presentedin nine chapters:
Chapter 1

Provides an inroduction, general description, and overview of electrical and
mechanical specifications.

Chapter 2

Presents a functional description of the console, operating modes, controls

and indicators, and a general discussion of 1nterface module hardware organization and software facilities.

Chapter 3

Describes, on a detailed block diagram level, interface module functions,

registers and controls, and the functions of the MOS/LSI microprocessor.
Chapter 4

Describes the microprocessor instruction set.

Chapter 5

Presents a description of the M7859 Interface module to the logic level.

Chapter 6

Provides operating information on console utilization in console mode.

Chapter 7

Contains procedures for using the console in mamtenance mode (maintenance of PDP-11/04/34 processor)

Chapter 8

Covers some maintenance techmques for the KYll LB interface module.

Chapter 9

Describes installation procedures for various options.
NOTES
In the material presented in this manual, the term
“processor” refers to the KD11-D, KD11-E, and
KD11-EA PDP- 11 /04 /34 processors

If the operator is not familiar with console functlons,

Chapter 6 should be consulted.

CHAPTER 1

OPERATING CHARACTERISTICS

1.1
INTRODUCTION B
The PDP-11/04/34 Programmer’s Console and Interface module (KYll LB) provides all the func-

tions now offered with the PDP-11/05. The Programmer’s console interfaces to the Unibus (Figure 11) through a quad SPC module. To use this option, the normally provided KY11-LA Programmer’s

Console must be removed and the KY11-LB Console installedin its place. The KY11-LB Console
contains a 7-segment LED display and a 20-key keypad for generatlng the console commands. Several
mdlcators are also provided for additional convenlence in monitoring system status.

| PROGRAMMER'S

;

A
3

]

MODULE

INTERFACE -

I OPTIONS

KY11-LB

consoLE/
.
,

ADDITIONAL

KD11-D
|

KD11-E,
-EA |

MEMORY
|

PROCESSOR
o

11-4855
......

F’igur'e 1-1 Pr‘ogrammer’s Console/ In%%zrface - PDP- 1’1_/04/ 34 Configuratibn
The KY11-LB Programmer’s Console/Interface module comprises an INTEL 8008 single-chip, large
scale integration (LSI) microprocessor and associated registers, Unibus control logic, and auxiliary
memory. The unit is also provided with a 20-key keypad for operator/programmer interaction with
the KDI11-D, -E, -EA via the interface module, six indicator LEDs, a 6-digit, 7-segment display for
- address or data and a dc power switch. The microprocessor communicates with a read-only memory
(ROM) which contains a number of fixed routines for use during normal console and mamtenance
~ operation.
1.2 GENERAL DESCRIPTION
The M7859 Interface module (Figure 1-2) functions as the interface between the programmer’s console
and the KD11-D, KD11-E, or KD11-EA processor, via the Unibus. The unit consists of solid state
integrated circuits with TTL-compatible input and output lines. The heart of the interface moduleis a
single-chip, large scale integration (LSI) microprocessor which executes designated keyboard functions
via programs stored in ROM memory. Auxiliary logic functions including clock, decoding and timing
circuitry, and addressing and Unibus drivers/receivers comprise the remaining logic of the board.

1-1

9‘:3

8141-14
Figure 1- 2

Inter face Module (M7859)

1-2

The microprocessor chip is an 8-bit, parallel control element packaged as a single metal oxide silicon
circuit in an 18-pin, dual in-line package. With the addition of external clock driving circuitry and
decoding elements, plus memory and data bus control, the unit is capable of performing as a powerful,
general-purpose, central processing unit. Internal logic of the microprocessor chip is structured around
an 8-bit internal data bus and includes instruction decoding, memory control, accumulator and
scratchpad memory, arithmetic and logical capability, program stack, and condition code indicators.
Data transfer between the microprocessor chip and the remaining logic functions of the interface
module is accomplished through an 8-bit, bidirectional data port which is an integral part of the
microprocessor. An internal stack (scratchpad memory) contains a 14-bit program counter (PC) and
an additional complement of seven 14-bit registers for nesting up to seven levels of subroutines. The
14-bit addressmg capacity allows the mloroprocessor to access up to 16K memory locations which may
comprise any mix of ROM or RAM.
|
,
1.3 FUNCTIONAL DESCRIPTION
The KY11-LB Programmer’s Console permits the 1mplementatron of a variety of functions through a
20-key keypad located on the front panel of the programmer’s console. Keypad functions are divided
into two distinct modes: console mode and maintenance mode. In console mode operation, a number
of facilities exist for displaying addressesand data, for depositing datain and examining the content of
Unibus addresses including processor registers for entering data into a temporary buffer for use as

address or data, and for single instruction stepplng the processor. The latter featureis espec:1ally useful
during program debugging functions.
‘
Normal console keyboard functlons are not available during maintenance mode Thls mode permits
sampling and display of the Unibus address lines and Unibus data lines, and may allow the console to
take control of the Unibus to examine and deposit Unibus addresses if a processor is not present in the
system or is malfunctioning. Additionally, the maintenance function permits assertion of the manual
clock enable and display of the current processor microprogram counter (MPC). Single-clock cycling

of the MPCis also possible to facilitate step by step checkout of processor op codes and control logic
during maintenance functions. In conjunction with this function, assertion of manual clock enable
permits the processor to be stepped through its power-up routine. The manual clock enable may be
dropped via the START key at any time with a resulting dislay of the current MPC. Exit from maintenance mode to console mode may be accomplished at any time by depressing the CLR key on the
keypad.
1.4

SPECIFICATIONS

1.4.1 M7859 Interface Module }Perfo'rma'n‘c,e Speeifications
Operating Speed at 500 kHz

Two-Phase Clock Period

2us

Time State (SYNC)
Instruction Time (Mlcroprocessor)

4us
- 12-44 pus

Word Size

Data
Instruction
Address

Memory Size
ROM
RAM

8-bit word

S
|

1, 2, or 3 8-bit words
14 bits
|

»
4 512 X 4 organized as 1024 8-bit words
16 words by 8 bits

| Input/Output Lmes
Memory Data

16 bits
18 bits

~Address

Control (Address)
- Unibus Control

| Mrcroprocessor Instructlon Repertorre
48 Basic Instructions
Instruction Categories

1.42

Electrical Specifications

Accumulator
PC and Stack Control

- 1/0

Machine

+5Vat30A

Power Supply

-15Vat60mA

_InputLogrc Levels (all modules)
.

2 bits
5 »bits

0.0t 0.8 Vdc

TTL Logic Low
TTL Logrc Hrgh

2.0to 3.6 Vdc

Output Logic Levels (all modules)’

TTL Logic Low

0.0 to 0.4 Vdc

TTL Log1c ngh

| Power Consumptlon

2.41t03.6 Vdc
E

Interface Module

Momtor/Control Panel 1 4.3 Mechamcal Spec1ficatlons

14W

M7859 Interface Module

Quad SPC

Board Type

Dimensions
Height

~ Length

21.44 cm (8.44 in)
26.08 cm (10.44 in)

ProgrammerS Console (Overall Panel D1mensrons)

Width
Herght
Depth

1.44 Environmelrtal Speeific’atiohs

47.63 cm (18. 75 in)

- 13.02 cm (5.125 in)
- 6.76 cm (2.66 in)

Amb1ent Operatmg Temperature
Hum1d1ty

5° t0 50° C (41° to 122° F)
10% to 95% maximum,
wet bulb 32° C (90° F)

CHAPTER 2
FUNCTIONAL DESCRIPTION

2.1
INTRODUCTION
:
|
Logical organization of the KY11-LB Interface module is centered around a microprocessor and a
bidirectional data bus (Figure 2-1). The 8-bit data and address bus (D0-D?7) is time multiplexed to
‘permit control signals, 14-bit addresses, and data to be transmitted between the microprocessor, memory, and additional buffer registers. Two registers, the switch register and the bus address register,
contain data and addresses (respectively) to be routed to the Unibus. The transceivers permit 16-bit
data words to be loaded into the microprocessor from the Unibus via the 2-way data bus. Data flow
depends on the type of operation indicated by the keypad and the instruction the microprocessor is
“executing at a given time.
In a typical operation involving an instruction fetch, for example, the microprocessor program counter
contents are transferred to the address register in two successive 8-bit bytes. The address register
outputs activate the appropriate ROM location containing the instruction. The instruction
is routed

back via the tristate transceivers and the bidirectional bus to the microprocessor for decoding
and
subsequent execution. Instructions range from one to three bytes in length; the state counter decoding
is capable of discriminating between the op code types and the resulting instruction length. The
microprocessor is driven by a nominal 500-kHz, symmetrical, two-phase, nonoverlapping clock
and is
capable of responding to externally generated interrupt conditions. The data interface is a bidirectional

8-bit bus and the unit also provides four control outputs which include three state control signals
and a
sync signal. The control signals are applied to external decoding logic to generate system timing
states
and are subsequently distributed to the remaining interface module control circuitry. The state
control
signals are also utilized in the chip for sequencing data processing operations.

2.2

PROGRAMMER’S CONSOLE KEYPAD FUNCTIONS/ CONTROLS AND INDICATORS

Operator/programmer control of the KY11-LB is accomplished through a 20-key keypad located
on
the console panel (Figure 2-2). A summarized description of the key functions and other controls
and
indicators is contained in Table 2-1. The table first presents those functions involved in console
mode
which are primarily of interest to the programmer. A second portion of the table describes entry
into
maintenance mode and presents facilities useful for processor checkout and maintenance
. The
CNTRL key functions primarily as an interlock which prevents accidental inerference with other
console operations.
o
8
2.2.1
Console Mode
|
Detailed presentation of console mode keypad functions and their use in program debugging
is
reserved for a later chapter; the various functions are outlined and briefly described in Table 2-1.
The
operator indicators available for both modes are also described. Upon power-up, the programmer’
s
console is in console mode. If in maintenance mode, pressing the CLR key causes a reversion
to
console mode through a HALT.

HLT GRANT

SSYN

]

[-]

MICROPROCESSOR
:

ADDRESS/DATA BU

3-STATE

3STATE

ROM

BUFFER

512:X 8

] L

| L

| |

TRANS7
8008 < DATA BUS>‘| ceiven
[Q DATA
IN (3STATE)

RAM

(

CLOCK

] I
16 X 8

DATA OUT

TIMING

TIME STATES

DECODER

;

ADDRESS

14-8

7-0

| 2

DATA BUS
CONTROL

RAM CNTRL

4 L

ROM ENABLE

INPUT/OUTPUT
PORTS
L

]

I CONSOLE

DISPLAY

;

KEYPAD
'

}

]

HLT RQST

I— — ——l

MSYN

}

2-2

INIT

KY11-LB Logical Organization

[

BUS ADDRESS

REG 3

[

BUS ADDRESS

REG 2

BUS ADDRESS

REG 1

S.R.

CONTROL

SWITCH REGISTER
ro————

{

Figure 2-1

REG

11-4852

ADDRESS/DATA BUS

BUS CONTROL

’

TRANSCEIVER

777570

TRANSCEIVER

BUS ADDRESS <17:0>,
C1, CO
UNIBUS

BUS DATA <15:0>

DIS AD

EXAM

DEP

HLT/SS
/

Nk
LAD

CONT

BOOT

\
LSR

CLR

INIT “|

1] | cCNTRL

START

11-4846

Figure 2-2

KY11-LB Keypad

Table 2-1 KY1 1-LB Controls and Indicators

Contrpl /Indicator -

Function

Keyboard - Console Mcde

LAD

Load Address - Moves the 18-bit numberin the temporary register into the Unibus address pointer. The temporary reglster is
then cleared and d1splayed
.
.

LSR

Load Switch Register - Moves the 16 lower bits of the temporary register to a register which can be read via Unibus address
777570. The switch register contents will be displayed.

DEP

Deposit — Causes the console to do a DATO on the bus address
pointed to, using the data in the temporary register (two MSBs
are truncated). Sequential deposits cause the address pointer to
be incremented. This key is operatlve only if the processor is
halted.

0-7

Numerics - These keys are used to enter data into a temporary
data buffer prior to use as either address or data. Use of a
numeric key forces the console to display the data held in the
temporary buffer. A 6-digit numberis generated as octal digits
are entered from the right and left shifted.

CNTRL

Control - This key is used on’ly in conjunction with other keys

either to prevent accidental operation of certain functions or to

provide entry into maintenance mode or other features. When
used, the CNTRL key must be pressed first and held down
while the second key is pressed. Those keys which are interlocked with the CNTRL key are indicated by “CNTRL-second
‘key” (e.g., CNTRL-START).

2-3

Table 2-1
Control /Indicator
CNTRL-INIT

KY11-LB Controls and Indicators (Cont)
Function

Initialize - Operative only if the processor is halted. Causes |
BUS INIT L to be generated for 150 ms.

DIS AD

| Dlsplay Address - Thls key causes the current Unibus address

pointer to be displayed. The next examine or dep051t will occur
at the address dlsplayed

EXAM

| Examme-— Causes the console to do a DATI on the bus address
pointed to and stores the data in the temporary register which is
then displayed. Sequential examines cause the address pointer
to be incremented by 2 or by 1 if the address is in the range

777700-777717. This key is operative only if the processor is

halted.
CLR

Clear Entry - Clears the current contents of the temporary register whichis then displayed.

CNTRL-BOOT

Causes M9301 bootstrap terminator to be activated if present in
the system. Console will boot only if the processor is halted.

CNRL-HALT/SS

Halt/ Single Step— Halts the processor if the processor is running. If the processor is already halted it will single-instruction

step the processor. It also retrieves and dlsplays the contents of
R7 (program counter). The CNTRL key is not required
to
Single-Instruction Step the machine.
CNTRL-CONT

Continue — Allows processor to continue using its current program counter from a halted state. The contents of the switch

reglster are dlsplayed

CNTRL-START

Operative only if halted, this causes the program counter (R7)
to be loaded with the contents of the Unibus address pointer.
BUS INIT L is then generated and the processor is allowed to

run. Switch register contents are then displayed.

CNTRL-7

Causes the Unibus address pointer to be added to the temporary data buffer which is also incremented by 2. This allows the
console to calculate the correct offset address when mode 6 or 7,
register 7 PIC (Posmon Independent Code) instructions are
encountered

CNTRL-6

This causes the switch register to be added to the temporary
data buffer. This is useful when mode 6 or 7 1nstruct10ns are
encountered not using R7.

CNTRL-1

Mamtenance Mode - This combination puts the console into
maintenance mode with certain maintenance features available.
When the console is in maintenance mode, the normal console
mode keypad functions are not available. The CLR key causes

the console to exit from maintenance mode into concole mode
via a processor halt.

2-4

Table 2-1 KY11-LB Controls and Indicators (Cont)
Control/Indicator

Function

Keyboard — Maintenance Mode
-

NOTE

In maintenance mode the keypad functions are rede-

fined with the following definitions.

DIS AD
" CLR
EXAM

Causes the Unibus address lines to -be sampled and displayed.
Returns the console to console mode via a console halt.

Causes the console
to sample the Unibus data lines and display
the data.

Causes the console to take control of the Unibus. Should be
used only when a processor is not present in the system.

HLT/SS

Asserts manual clock enable and displays the current microprogram counter (MPCQC).

CONT

(

BOOT

START

Asserts manual clock enable, generates a manual clock pulse,
and displays the current MPC.
:
Boots the M9301. If manual clock enable1s asserted, this will
allow the processor to be stepped through the power-up routine.

Drops manual clock enable and displays the current MPC.
Indicator LEDs - Any Mode

DC ON

BATT

All dc power (+5 V) to loglcis on.

Battery monitor 1nd1cator operative only in machlnes having
the battery back-up option. This indicator has four states
Off
- Indicates either no battery present or battery failure if a batteryis present
On (contlnuous) Indicates that a batteryis present and

charged.

Flashing (slow)
- Indlcates ac power is ok and batteryis charging.

Flashing (fast) - Indicates loss of ac power and that bat-

tery is discharging while maintaining MOS memory
contents.

RUN

Indicates the state of the processor, either running or halted.

Table 2-1

KY11-LB C_ontrols and Indicators (Cont)

Control /Indicator

SR DISP

~ Function

Indlcates that the content of the sw1tch reglster is belng |
|

>d1sp1ayed

MAINT

Indicates that console is in maintenance mode.

BUS ERR

|
|

Indicates that an examine or deposit resulted in a SSYN time-

out or that HALT

REQUEST failed to receive a HALT

GRANT.

DC OFF

DCON

STNBY

DC Power Switch

Alldc power to logic is off.

{

All dc power to logic is on.

DC power is provided to MOS memory only.*

*Available in all BA11-C machines. Available in BA11-K boxes which have
Battery Backup Option only.

Table 2 1 refers to certam reglsters wh1ch are located in the scratchpad RAM. These melude the

followmg

. Di_spl_ay Data

Keypad Image
- Temporary Data Buffer

Unibus Address Pointer
Switch Register Image

-EXAM, DEP, ENB and Cl1 flags

Detailed d1seussron of the scratchpad RAM and its reglsters is set forthin Chapter 5.
2.2.2

Mamtenance Mode o
Mantenance modeis entered by pressmg the CNTRL key and the 1 key simultaneously. Note that the
functions performed by the appropriate keys are quite different from console mode. This mode offers
the ability to assert the manual clock enable and thus to single-clock cycle the processor while monitoring the contents of the processor mlcroprogram counter.

2.3

HARDWARE ORGANIZATION
A detailed block diagram of the interface module showing data flow and controlis indicatedin Figure
2-3. The control functions shown include those for the Unibus interface and the internal data bus with

the microprocessor. The latter controls include those for reading from and writing into the RAM,
enabling ROMs 1 and 2, and reading the Unibus temporary buffer register or loading the bus address
and switch regrsters All of these functlons occur on approprlate control from the stored program and
keypad

2-6

DIN 0-7H

MASTER

CLOCK

—

M.P

gBITBUS

—V

TRANS.

ADRDO7H

S.R.

16 BIT

ADDR

REG

SYNC H

'ROM 2 EN

ROM 1 EN

S0 -S1 S2

ADRD 0-8

_INT

POWER

‘

- BUS

SSYN L (TO HALT)

DECODE
LOGIC

ROM

BUS DATA

m
?
2

ENDB—~B|L

(DECODE 777570)

LOGIC

<15:0>

ADDR

1024 x 8

SWITCH
REG

(16

BITS)

ADDR

‘
>

[—> ISiL

CLE?XQ:)NG

DECODER }—— T1IL
|

|
» TS3L

BYTES

TSl

182

—<#CLR BUS L

b—— TS4L

HALT

RQST

UNIBUS |1 BUsINTL

’

ADRD 0-5

CNTL

LOGIC

777570

<17:0>

|—hes EN DB—BUS L

L 1. & TAKE BUS L

—7‘->1 BUSMSYNL

BUS ADDRESS

ADRD 6, 7> CYCLE .—+->1 MAN CLK EN L
SINGLR

CNTL

ADRD(

—i~ MIAN CLK L

. DATA

AD
PC FUN
o PeX B 1)

BUS

CNTL

——= DIN DRIVERS D15
H

REG

+2 CONTROL

BITS

|}1ew RAM WRITE

|
»

—2<+ DIN BUS L (RAM)

&<+ LOAD REG 0-5H
:

—

18 BITS

{

EN AR—BUSL

BUS

—gf—b READ INPUT 0-7 L

ADDR

;

2.
|

AND IND CNTL

—<»ROM1ENL
.
& ROM2ENL

—~»BUSERL
_

ADRD 4-7

IND

1
> SRDISPL

DISPLAY

CNTL | 1 o MAINTMOL

1
s BOOTL
ADRD 0-3H

|
i

16 X 8

RAM

DOUT 0-7H
,

RAM-DIN BUS L

SCAN SIGS

KEYPAD

RAMWRITEH

SCAN

SWITCHES (20)

LOGIC

KEYPAD

CONN D — CONN 11 H

(MPC INPUTS)
FOR DISPLAY

MAINT

HALT GRANT H-

CLR BUS L

CONN

PU PL

HALT

BUS BUSY L

CNTL

BUS SSYN L

BUS INIT L

BUS

BUSY

& BB SSYN H
|
& BUS SACK L

TAKE BUS L

‘

& RUN L

11-4845

|
|

Figure 2-3

Interface Module

Detailed Block Diagram

Under microprogram control, the data bus control logic develops the loading or reading signal for the
appropriate register and thus determines the selected input/output port via the data bus control and

the function currently being executed

- As shownin Chapter 3 when the detailed mlcroprocessor cycle1s presented the microprocessor exe-

~cutes four basic machine cycles. They are summarlzed here to show their relation to interface module
| ‘functions

PCI
- This is always the first cycle of a microprocessor instruction and initiates the instruction fetch. The program counter is transferredin two bytes from the microprocessor to the
16-bit- interface module address register (14 bits of address, 2 control bits) to fetch the
instruction data from either the ROM or RAM A single byte of instructions is retrieved
during this cycle.
|

PCR
- This cycle may retrieve an additional byte of instruction (if the instructionis a 2- or 3byte instruction) or it may fetch a data byte if the indicated instruction contains only one
byte.

3.
|

PCC - This cycle specifies the function as an I1/O operation. This machine cycle reads and
loads the address and data registers which cause information to be read from or written into

the microprocessor.

PCW -This cycle controls the memory write function according to the designated address.

| Figufe 2-3 shows that the basic satellite logic and control for the microprocessor chip consists of the
f following elements:

2-phase master clock
Decoder for interface module time states
Power-up logic
16-bit address register
16-word X 8-bit RAM
1024-word X 8-bit RAM (four - 512 X 4)
Switch register (16 bit)
Switch register address decoding
Bus address register (20 bit)
~

Tristate transceivers

Keypad scan and display logic

Data bus control
|
Unibus control and single-cycle control
Indicator control
- Halt control
These major functions are briefly described in the following paragraphs; detailed theory of operation is
presented in Chapter 5.

2-Phase Master Clock

The master clock drives the microprocessor internal logic and generates the system states for instruc-

tion sequencing. The nominal 1 MHz clock frequencyis toggled down to two nonoverlapping, 500kHz pulses known as phase 1 (01) and phase 2 (02). Phase 1 is normally used to pre-charge data lines
and memories while phase 2 controls data transfers w1th1n the microprocessor.

2-8

Decoder for Timing States
- The decoder element receives the state outputs SO, S1, and S2 from the microprocessor and generates

‘the time states for the operatlon of the interface module A sync pulse corresponding to two phase
clock periods (1 time state)is also provided by the microprocessor.
Power-up Logic

|
This circuitry activates the microprocessor, clearing its various registers and generating a clear line to
all the registers of the interface module. There are separate clears for the address register and all other
reglsters

Address Register

This 16-bit register is the principal buffer between the microprocessor and the remainder of the logic of
the interface module. Although designated as an address register, the element also handles control data
for the Unibus, data bus, and other control functions and outputs to the bus address and switch

registers. One of its major functions is to receive the MICTOProcessor program counter contents for
fetchmg new instructions from the ROM or RAM.
RAM

|
|
The 16-word by 8-bit RAM gives the 1nterface module a scratchpad memory which may be read or
whose contents may be modified under program control.

-ROM
The ROM, c0n31st1ng of four 512 X 4-bit ROMs, makes a total of 1024 8 bit bytes available for the

stored programs which execute the console functions.

Switch Register Address Decoding
This logic decodes 777570, an 18-bit address defining the switch register and a DATI on the Unibus to
cause the switch register to be enabled onto the Unibus.

Switch Register

This 16-bit buffer register handles the data word to the Unibus.
Bus Address Register
This 20-bit register buffers address 1nformat10n between the 1nterface module and the Unibus. Eighteen bits are allocated for the actual address, and two control bits indicate the direction of data flow.
Scan signals for the keypad and NUM lines for the display logic are specified by this register.

Tristate Gates
|
These units are used to gate buffered Unibus data (16 bits) and Unibus address (18 bits) lines onto the
tristate data bus by asserting an approprlate read input line. Keypad outputs and those maintenance
lines provided for display of the processor microprogram counter are similarly buffered and gated. The
outputs are all wire ORed onto the internal data bus and apphcd as input to the tristate transceivers.
-

Keypad Scan and Display Logic
This circuitry develops read and drive signals for the keypad and LED display respectwely Five read
signals developed from the scan signals are used to scan the keypad switch closuresin groups of four.
The drive signals are applied to the LED displays whose values are determined by the 3- bit NUM
input.

Data Bus Control

This circuitry performs all internal interface module control functions including RAM control, ROM
enable, and selection of input/output ports. The logic also determines system operation during instruction, data fetch, or data out (TS3) via a 32- X 8-bit ROM.

Unibus Control
|
|
|
o
The Unibus control register supervises data transfers between the interface module and the Unibus.
According to the input bit patterns to the register, data transfer from the interface module to the
Unibus, halt request, bus master sync, and other functions may be generated as required for proper
1nterfac1ng of the two elements. Two other signals generated 1n the Unibus control reglster permlt
single stepping of the processor clock.
,
|
Indncator Loglc

This 4-bit register drives appropriate console mdlcators to show certarn console states OT errors.. An

indicatoris turned on to show the existence of a bus error, when the switch register is bemg dlsplayed
or whenin maintenance mode.
.

Halt Loglc

- This circuitry halts the processor under variouscondltlons and performs handshaklng functlons when

the console takes complete control of the bus. When a HALT from the consoleis detected by the
processor, the processor recognizes it as an 1nterrupt request. The processor then inhibits its clock and

returns a recognition signal to the console causing the console to assert an acknowledge. The console

now has complete control of the Unibus and processor and may maintain thlS COIldlthIl w1th the
processor halted as long as desired.
,
»
»

2.4 MICROPROCESSOR INSTRUCTION SET
- The interface module microprocessor has a repertone of 48 basic instructions. Accordlng to the
- instruction type, these may range from 1 to 3 bytes (8 to 24 bits)in length. The successive bytes of a
given instruction must be locatedin sequential memory locatlons Instructions fall into one of five

- categories:

- Index Register

Accumulator (Arlthmetlc / Loglcal)
Program Counter and Stack Control
Input/Output
Machine

A descrrptron of the microprocessor 1nstructlons and the number of time states requ1red for the1r

*executlon is glven in Chapter 4.

CHAPTER 3

INTERFACE MODULE

3.1

MICROPROCESSOR

3.1.1

General Organization

- The microprocessor sends and receives data over an 8-bit data and address bus (Do to D7) and utilizes
four input and four output lines (Figure 3-1). The microprocessor contains six 8-bit data registers, an
8-bit accumulator, two 8-bit temporary registers, four flag bits, and an 8-bit parallel binary arithmetic
unit. The arithmetic element is capable of performing addition, subtraction, and logical operations.
Additionally, a memory stack containing
a 14-bit program counter and seven 14-bit words is used to

store program and subroutine addresses. The microprocessor machine cycle usually requires five

sequential states: TS1, TS2, TS3, TS4, and TSS. During time states TS1 and TS2, the external memory

is addressed by a lower and an upper address byte respectively
to form a 14-bit address. Also at TSI
time, the program counter (PC) is incremented for the next instruction fetch cycle. During time state

' TS3, the instruction addressed during states TS1 and TS2 is fetched and during the final two cycles,

TS4 and TS3, it is executed. Figure 3-2 shows the possible number and sequence of the instruction
states. Note that for this application of the microprocessor, the interrupt function is utilized only
during the power-on sequence.
-

FROM:
ROM

RAM

DATA (Unibus)

ADDRESS (Unibus)
—_—

KEYPAD .

/-\\

MAINT

FROM POWER-ON

LOGIC

L—_

INTERRUPT

READY|

NOT USED
(+5 V)

’

01 |

" MICRO

PRO s

C o

MASTER CLOCK

02
|

—

3STATE

TRANS-

—————

|o |

OUTGOING
DATA

> TO

CEIVERs

[ [ ADDRESS REG

XK,

'bz

PROCESSOR

FROM

AND RAM

L
-

D7
—
e

SO0~
S1

—

—&

Figure 3-1

> TIMING PHASE
DECODER

Microprocessor Signal Interface
3-1

11-4856

2 |NN\
SYNC

A I

—

N o

‘

A N A\ VAN A\ VA Y A B/ WY A

L/
- S2

TS1

TS2

WAIT

CPU
‘
INTERRUPTED

LOWER
8-BITS

HIGHER
8-BITS

EXTERNAL MEMORY

ADDRESS

NOT READY

FETCH, OR

RECEIVED

ouT

TWO BITS

(OPTIONAL)

DATA OUT

CPU

CONTROL

TS3

STOPPED

INSTRUCTION | HALT
OR DATA
INSTRUCTION |

TS4

TS5

o EXECUTION
~ OF = .
INSTRUCTION

(8-BITS)

out

11-a889

Figure 32 T_iming‘Dia’_gramv,‘—,\"Michr‘Op'roc‘e_SSor Instruction
3 1 2 State Control

The microprocessor operates as a sequent1a1 state machlne controls the use of the data bus and

according to its stored program, determines whether it sends or receives data. Output state 31gnals SO,
S1, and S2 are decoded externally and distributed to the perlpheral control log1c Table 3-1 shows the
codlng of the state b1ts to y1eld a glven phase ,

3. 13 Mlcroprocessor Tlmmg

The microprocessor machine cycleis shownin Figure 3-2. Since machlne operatlon is asynchronous

the exact timing sequences depend on the instruction executed. A typical cycle may consist of five
states. During T1 and T2, an addressis sent to memory; at T3 time, instruction or data fetch occurs; T4
and TS5 provide execution time.
|
A number of microprocessoriinstructions may require -'upto three cycles and do not require the two
execution states T4 and T5. As a result, cycle length
is variable and the state counter determines
whether T4 and TS5 are to be executed or omitted. This is accomplished via the cycle control coding
(Table 3-2)in bits D6 and D7. Cycle 1 is always an instruction fetch cycle (PCI). The second and third
cycles are for data reading (PCR), data writing (PCW), or I/O operatlons (PCC) The cycle type bits
D6 and D7 are present on the data bus during T2 time only.
3
|

Table 3-1

[ S1

0
0
|
0
1
1

1
0
0
0
|1

1|1
|
0

State Control Codmg

S2
0

State
|

1
|
1|
0
0
o
1
1

3-2

TI1

TI11
T2
WAIT
T3
|
STOPPED
T4
TS

Table 3-2

Cycle Coding

Cycle

'PCI

PCR

Designates the addressis for a memory read data (addltlonal
| bytes of instruction or data).

PCC

‘Designates the data is a command 1/O operation.

PCW

Designates the address
is for a memory write data.

Functlon

De51gnates the address 18 for a memory read (first byte of

instruction).

3.1.4 Transition State Diagram
Possible state transitions within the processor are shownin Figure 3- 3 Note that a normal machme

cycle would begm at cycle 1, run from T1-TS5, and revert back to cycle 1 again. The state counter
within the microprocessor operates as a 5-bit feedback shift register with the feedback path controlled
by the current instruction. The number of states normally required by each instruction is discussedin
Chapter 4.

~ (CYCLE 1) (HLT - INT + RETURN(CF)) + (CYCLE 2) (OUT + LMr)

+ (CYCLE 3) (LMI + JUMP (CF)) + CALL (CF)

CYCLE 1

—»|

CYCLE2

—_—

(CYCLE 1) (HLT = INT) + RDY

CYCLE
3

T (CYCLE 2) (LM + JUMP + CALL)
(CYCLE 1) (LrM) + ALUM + ALUI + IN + OUT + Lrl + JUMP + CALL

(CYCLE 1) LMr

~
-~

NORMAL RETURN AT END OF MEM CYCLE

NOTE: CF = Failure Condition
11-4857

Figure 3-3

Transition State Diagram

3-3

3.1.5 System Start-Up
The microprocessor of the interface moduleis running any time power is apphed to the system. When
power (VDD) and clocks (01, 02) are first turned on, a flip-flop internal to the microprocessor is set by

sensing the rise of VDD. This internal signal forces a HALT (00000000) into the instruction register

and the microprocessor is thenin the stopped state. The next 16 clock periods are required to clear
internal chip memories and other external logic and regi1ers. ‘Upon clearing the registers the system is
ready for operation. If for any reason during operation, the microprocessor decodes a HALT, the
system reverts to the begmmng of the program after 16 clock periods.

3.2
32.1

INTERFACE MODULE REGESTERS AND CONTROLS (Figure 2-1)
Address Register

Thisis the principal buffer register between the microprocessor and the rest of the interface module
logic. It has a capacity of 16 bits (two 8-bit bytes). The low order byteis loaded by time state TS1 and
the high order byte by time state TS2 during each cycle.
3.2.2

Bus Address Register

The bus address register buffers address data between the interface module and the Unlbus Address’:
1nformat10n may be loaded into thls reglster at tlme state TS3
3 23

Switch Regnster
Similar to the bus address register, the swntch register buffers outgomg data. Thls element may also be "
loaded at TS3.

3.2.4 Data Bus Control
|
|
The principal function of the data bus controlis to determine interface module operatlon durmg TS3
time. It determines, through input bit coding, the type of function to be performed (i.e., RAM control |
ROM enable) or programs any of its other I /Oin accordance with the stored program.
3.2.5

Unibus Control
This register is also loaded at TS3 andis selected by the data bus control for activation at that time.
According to its input coding, U.C.R. may issue a HALT request, BUS INIT, enable—data bus-to-bus,

or generate a bus master sync in addition to other functions.

3-4

CHAPTER 4
MICROPROCESSOR INSTRUCTION DESCRIPTION

4.1
DATA AND INSTRUCTION FORMATS
|
|
|
Data in the CPU is stored in the form of 8-bit binary integers. All data transfers to the system data bus
will be in the same format.
|

[D7Ds Ds Dy D; D, D, Dy |
DATA WORD

The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be
stored in successive words in program memory. The instruction formats then depend on the particular
operation executed.
|

(

One Byte Instructions

ID; Ds Ds D; D; D, D; Dy |
|

OP CODE

I/O arithmetic or logical, rotate or

return instructions.
Two Byte Instructions

|D7 D¢ Ds D4y D3 D, D, Dy |

OPERAND

Immediate mode instructions.

Three Byte Instructions

[D;D¢D;DsD;D,D,D;]

OPCODE

[D;D¢D;DsD;D,DD;]

LOWADDRESS

[X X D;D,D; D, D Ds]

HIGH ADDRESS*

*For the third byte of this instruction, D¢ and D7 are ““don’t care’’ bits.

4-1

JUMP or CALL instructions

4.2

MICROPROCESSOR INSTRUCTIONS

4.2.1

Index Register Instructions
The load instructions do not affect the flag flip-flops. The increment and decrement instructions affect
all flip-flops except the carry.

Mnemonic

Minimum

States

Instruction Code
D7D6 D;:D,D; D,D,D,

Description of Operation

Required
(1) Lryr,

(5)

|
1

DDD

Load index register r; with the content

of index register r,.

(2) LtM

(8)

LMr

(7)

DDD

11
-

(8)

O- O

DDD

1 1 0

BBB

BB 'B

- 9)

INT

(5)

- Load memory register M with the con-

- LMI

of memory reglster M

(3) L1l

| : Load index reglster r with the content

tent of index register r.

Loadindex register r with data B ...B.
|

111 110
0

Load memory register M with data’

Increment the content of index register

h DCr B "1(:5).; o

DDD

T (r #+ A).

0 01 |

Decrement the content of index reglster
r(r #A).

4.2. 2 Accumulator Group Instructions
The result of the ALU instructions affect all of the flag flip-flops. The rotate 1nstruct10ns affect only

the carry flip-flop.

Minimum
Mnemonic

States

Instruction Code

D.D¢

D;D,D; D,D;D,
SRR

000 S S S

Required

Description of Operation
R

- (5)

ADM

(8)

ADI

(8)

000
000
100
BB
BBB
B BB

(5)

001

Add the content of index register r,

(8)

001

memory register M, ordata B...B to

(8)

g B BBB BB B

ACr

ACM

ACI

ADr
AD
~

000

001

100

|
|

Addthe content ofindex "re‘giStef r‘,,'-”-'
memory register
M, or dataB.. .Bto

the accumulator. An overflow (carry)

sets the carry flip-flop.

the accumulator with carry. An over-

flowv(carry) sets the carry fllp-flop -

Minimum

- Mnemonic

o SUr

SBr

SBM

(8)

D -

(8)

(]; (];

(5)

XRI

ORr

1 0

ORI

CP1

- RLC
|

RRC

RAR. B

B
|

113 % g

BBB BBB

110

B with the

Comptite the Exclusive OR of the contentofindex registerr, memory M, or
data B. .. B with the accumulator.

'
| Compute the Inclusive OR of the con-

tentofindex register r, memory

_accumulator.

S S S
1

borrow.

- Compute the logical AND of the con|

B (]; g

the accumulator with

An underflow (borrow) sets the carry

100

tent of index register r, memory

g g | ]13 ]13 g | ]13 g g

accumulator.

(5) |

111

88 S

‘Compare the content of index register

| (8)

111

r,,.memory register M,ordataB... B

the accumulator is unchanged.

(8.)

| (]; (]; . ]13 ]13 ];

]13 (]; ](3)

010

000

with the accumulator. The content of

Rotate the content of the accumulator

left.

OO0

001

010

Rotate the content
of the accumulator

(05 ;

OO0

010 010

Rotate the content of the accumulator

)

011

1 01

RAL 1

100

1 |

rom

10 0O S S S

1100

| ? memhory registeiri\/l, or.f}fl‘;)a B...B
|

S S S

Subtract the c’ontent of index register

111

An underflow

- (borrow) sets the carry flip-flop.

101

@)
:-

from the accumulator.

101

‘(5).

CPr

CPM

r, memory register M, or data B . . .’ B

(8)

|
ORM

011

0 0 | 01

)

NDI -

Subtract the content of index register

100

NDM

- Description of Operation
g

S S S

| 0 '3 01 1 | S 'S S |

‘NDr

XRM

010

5 |
|

XRr

(]; % ](; B g B B B-

- SBI -

(s)

SUI I

D, D, D.,DD,DDD,
-

(5)

SUM
|

Instruction Code

|
States
~ Required

010

left through the carry.

Rotate the content of the accumulator
right through the carry.

4-3

4.2.3

Progr'am Counter and Stack Control Instruetians E

Mnemonic

Minimum
States

4) JMP

(1)

(5) JFc

Instruction Code
D,D¢ D;D,D; D,D;Dg

Requlred N

XXX

B;B,

B,B,B,

B2 B, B,

| X X|

B3 B, B3'_B3 B; B;

(Qorll)

0C, C;

000

B, B, B,
B3 B, B,

(9orll)

| dress B; . B3B2 B2
|
-

|
Jump to memory address

B3 ...B3B;...Byif the cond1tron
| fllp—flOp Ccis false Otherwise,
|
execute the next instruction in
sequence.

1CC

000

Jump to memory address

B, B2

B,B,B,

B, 132 B,

B;...B;B,...B, if the cond1t1on

X X

B, B, B,

B3 B3 B3

(11)

B,B,

X X
S

~ | the next instruction
in sequence.. -

XXX

110 | Unconditionally call the subroutine at

B,B,B,

memory address B3 ...B3B,...B,.

ByB;B; B;B,B;

(Qorll)

flip’-flop C 1S true ‘Otherwise, execute

01
4

| UncondrtlonallyJump to memory ad-

(5) CFc

(4) CAL

(5) JTc

0 0

| 'B2 132 B,B,B,
| X X
ByB,B,
o

L
Description of Operation

Save the current address (up one level

in the stack).

0CC;

010

| Call the subroutine
at memory address

B,B,

B,B,B,

B, 132 B,

B; ...B3B, ...B, if the condition

B;B;B;

B;B,B,

flip-flop c is false, and save the current

)

-~ address (up one levelin the stack).

Otherwise, execute the next 1nstruc—
|

(5) CTc
o

Qorll)
-

tron m sequence.

1CGC4

O 1

- B,B,

B,B, B,

B,B,B,

B, B, B"3

B, B, B,

Call the subroutine at memory address
" B;...B3B,...B, if the condition
B

flip—flop C 1S true and save the current

address (up one level in the stack).

| Otherwise, execute the next instruc- tion in sequence.
|
|
(4) RET

(5)

(5) RFc

XXX

111

in the stack)

“(Bor))

0 0

0C,C;

1 1

(5) RTc
N

(3 or5)
o

Return (down one level in the stack) if
the condition flip-flop c is false. Other-

- Uncondrtlonally return (down one level |

- wise, execute the next instruction in

sequence.

1¢CC
B

011

‘

Return (down one levelin the stack) 1f
" the condition flip-flop ¢ is true. Otherwise, execute the next instruction
in.
sequence.

RST

(5)

AAA

101

Call the subroutine at memory address
AAAOQOQ00 (up one level in the stack).

4.24 Input/‘Output Instructions
|

‘Minimum

Mnemonic

States

Required

" INP

(8)

D;D;D;

0 1

(6)

D,D,D,

Description of Operation

00 M M ‘M1

| OUT

Instruction Code
D,D¢

- Read the content of the selected input
port (MMM) into the accumulator.

RRM MM1

Write the content of the accumulator
into the selected output port

(RRMMM) (RR # 00).

425 Machine Instruction

Minimum

- Mnemonic

States

Required

@ HLT

_
Instruction
Code

D,D¢

D,D;D,

Description of Operation

HL.T

D;D,D;

00O

0O0O0X
o

111

Enfer the STOPPED state and remain
there until interrupted.

111

Enter the STOPPED state and remain
there until interrupted.

NOTES:
(1)

SSS =Source Index Register

DDD = Destination Index Register

- These registers, I, are designated A (accumulator—OOO)‘.
B(001), C(010), D(011), E(100), H(101), 1(110).

(2) Memory registers are addressed by the contents of registers H & L.

(3)

Additional bytes of instruction are designated by BBBBBBBB.

(4)

X=“Don’t Care”.

| (5)

Flag flip-flops are defined by C, Cs:

carry (00 overflow or underflow), zero (01-result is zero),
sign (10 MSB of result is “1”), parity (11-parity is even).

CHAPTER S

INTERF ACE MODULE DETAILED LOGIC DESCRIPTION

5.1 INTRODUCTION

Keypad operation initiates appropriate mlcroprocessor routlnes which perform certain data transfers
within the interface module, between the interface module and the Unibus, and between the interface

module and the programmer’s console dlsplay Prior to discussing the interface module logic, the
sequences (i.e., register transfer, /O operations, etc.) which occur after pressmg a given key are briefly
described.

Figure 5- l shows the 16-word by 8-bit scratchpad RAM and its address allocatlons This datais also
summarlzedin Table 5-1. The keypad 1
i mage w1th1n the RAM
i1S shownin Figure 5-2.

ADDRESS

. |‘_4..L 3 |

2 1 1

] o

11-4853

~ Figure 5-1

RAM Address Allocations

5-1

KEYPAD IMAGE

CLR

LSR

LAD

DIS AD

1 |

é_"

Asfi"

'i;EXAM

< sé,. -5 |Nfi,T.?.

| 0

CNTRL

START

BOOT

CONT

‘

DEP

HLT/SS

11-4854

”’Figure_'S-.Z | K‘eypéd,lmage -

" Table
5-1 RAM Function Address Asl"si:gnm;ent's'
" Function

Address (Octal)

Display Data
(18 bits)

- Word0
‘Word |
Word 2

Keypad Image. - o

(20 b1ts)

Word3

- Word4
- Word5
~

Word6 .

Address Bits

|
|

| Bits0-3

|
|
|

Word7
=

Temporary Data Buffer

Bits0-3

Word 11 -

Bits0-7

Word 12

BitsO,1

=~ Word13
|
~Word 14 - Word 15

EXAM FLAG

DEP FLAG
ENB FLAG

Sw1tch Register Image

| Bit7

‘Word 15

Bit
2

- Word 16

Word17

5-2

Bits0-7
Bits 0-7
Bits O, 1

Word15
Word
15
Word 15

C1 FLAG

(16 bits)

Bits0-3
Bits0-3

o ‘W(})‘r'd 10 - | Bits0-7

' (18 bits)

Unlbus Address Pointer
(18 b1ts)
L
e

Bits 0-7
Bits 0-7
BitsO, 1

Bit
6
Bit 3

Bits 0-7

~ CHAPTER 5
INTERF ACE MODULE DETAILED LOGIC DESCRIPTION

5.1 INTRODUCTION |

PS,

Keypad operation initiates appropriate mlcroprocessor routlnes Wthh perform certain data transfers
within the interface module, between the interface module and the Unibus, and between the interface

module and the programmer’s console display. Prior to discussing the interface module logic, the
sequences (i.e., reglster transfer, I/O operations, etc.) which occur after pressmg a given key are briefly
described.
Flgure 5-1 shows the 16-word by 8-bit scratchpad RAM and its address allocatlons This datais also
'summarlzedin Table 5-1. The keypad i1mage W1th1n the RAMis shownin Flgure 5-2.

RAM

.
ADDRESS

3
|
Bl

]

DISPLAY DATA

UNUSED

KEYPAD

IMAGE

6
.
,

"TEMPORARY

//UNUSED

13
14

UNIBUS ADDRESS POINTER
-

|rAc | Fiac %%ED/

EX AM

DEP

/////////

22l

SWITCH REGISTER IMAGE

‘

'
11-4853

~ Figure 5-1 RAM A.d-dre'ss Allocations

5-1

KEYPAD IMAGE

CLR

LSR

LAD

DIS AD

2‘ |

Exam

° i IS N

CNTRL

DEP

START

BOOT

CONT

HLT/SS

11-4854

| 'Figure,'5v§.2 “.Keypad.lmage D

" Table 5-1 RAM Function Address Assignments
“ Function

Address (Octal)

Display Data
(18 bits)
)

Keypad Image =

(20 bits)
-

Témporary Data Buffer
(18 bits)

...

Address Bits

- Word0
Word 1
"Word?2

~ Word3

Bits 0-7
Bits 0-7
Bits O, 1

| Bits0-3

~ Word4
Word5
Word6..

|
|

Bits0-3
Bits 0-3
Bits0-3

B Word7

Bits0-3

. - __',Wd‘rd 10
Word 11
Word 12

Unibus AddressxPo‘_inter B

| Bits0-7
-{
|

Bits0-7
BitsO, 1

Bits 0-7

(18 bits)

Word 15

‘Word15

EXAM FLAG
DEP FLAG
ENB FLAG

Word
15
Word 15
Word 15

Switch Register Image
(16 bits)
S

Word 16

~ Word17

5-2

Bits 0-7
Bits 0, 1
Bit 7
Bit 6
Bit 3
Bit 2

Bits 0-7
Bits 0-7

5.2

PROGRAMMER’S CONSOLE KEYPAD FUNCTION SEQUENCES

5.2.1

Console Mode‘ Key Functions

NUMERICS (0-7)
1.

Value of Key _ (left shifted) » Temporary Data Buffer

Temporary — Display

Clear indicators.

Temporary - Unibus Address Pointer
Zero —» Temporary

W N =

LAD

Temporary — Switch Registér'Image

LSR

Temporary - Display

Clear/Indicators.

Switch Register Image — Switch Register

SR DISP indicator is set.

CLR

Zero - Temporary
Temporary — Display
Clear indicators.

B
-

EXAM

Pre-increment Unibus address pointer if the EXAM flag is set.
Unibus Address Pointer - Bus Address Register
|
Bus Address Register - Unibus Address
Assert MSYN.

SANG

Unibus Data —» Temporary

Temporary — Display
Set EXAM flag.

‘/“

NOTE
Console waits for BUS SSYN to be retumed If
SSYN does not occur within 20 us, the transferis
aborted and the BUS ERR indicator is set.

Pre-increment Unibus address pointer if the DEP flagis set.
Unibus Address Pointer -+ Bus Address Register with C1
= 1.
Bus Address Register - Unibus Address
Temporary — Switch Register
Switch Register - Unibus Data
- Assert MSYN.

DEP

"
NOTE
Console waits for BUS SSYN to be returned. If
SSYN does not occur within 20 us, the transferis
aborted and the BUS ERR indicator is set.

Set DEP flag.
Switch Register Image - Switch Register

5-3

DIS AD

1.
2.

Unibus Address Pointer —» Display
Clear EXAM or DEP flag if set.

CNTRL-INIT
1.
Set BUS INIT and HALT REQUEST for 150 ms.
CNTRL-HLT/SS

I.
2.
3.
4.

Clears BUS SACK /BUS BUSY if set and sets HALT REQUEST
When HALT BUSYis active, sets 777707 —» Bus Address Register

Bus Address Register - Unibus Address
Assert MSYN

NOTE
|
Console waits for BUS SSYN to be returned. If
- SSYN does not occur within 20 us, the transfer is
aborted and the BUS ERR indicator is set.

5.
6.

Unibus Data » Temporary
Temporary - Display

CNTRL-CONT

1.
2.
3.

Clears BUS SACK and BUS BUSY.
Switch Register Image —» Display
Set SR DISP indicator.

CNTRL-BOOT

1.
2.

|
|
Sets and clears BOOT signal <
Switch Register Image — Display

Set SR DISP indicator.

CNTRL-START

1.
2.
3.
4.

777707 - Bus Address Register with C1
= 1
Bus Address Register - Unibus Address
B
Unibus Address Pointer —» SwitchReglster
Switch Register » Unibus Data
|
Assert MSYN.

NOTE
Console waits for BUS SSYN to be returned If

SSYN does not occur within 20 us, the transferis
aborted and the BUS ERR mdlcatoris set.
|
6.
7.

Switch Register Image— SW1tch Reglster
Assert BUS INIT for 150 ms.

8.
9.

Switch Register Image — D1sp1ay
Set SR DISP indicator.

CNTRL-7

Unibus Address Pomter + Temporary +2- Temporary

Temporary + Swrtch Reglster Image — Temporary

5-4

~
CNTRL 1
1.
Set maintenance indicator.

|
MPC Lines (sampled) —» Display

2.
5.2.2

Maintenance Mode Key Functions

1.
2.
3.

Clears indicators.
Clears manual clock enable, if set.
Goes to halt condition.

DIS AD

|
Unibus Address (sampled) —» Display

EXAM
1.

Unibus Data (sampled) - Display

HLT/ISS

Sets manual clock enable.

2.
3.

Clears BUS SACK and BUS BUSY.
MPC (sampled) —» Display

Sets and clears manual clock

Sets and clears BOOT signal.

MPC (sampled) — Display

1. Clears manual clock enable, if set.‘

5.3

MPC (sampled) - Display

Sets TAKE BUS signal, forcing console to assert BUS BUSY.

DETAILED LOGIC DESCRIPTION

3.3.1

Clock Circuitry
The M7859 Interface boardis driven by an MC 4024 (E42) 1-MHz clock (drawing CS M7859-0-1,
sheet 2). The 1-MHz output at E42-8 is toggled down to two nonoverlapping 500-kHz pulses at E12-5,
6, and E30, and these pulses are applied to the microprocessor (E18) input as 01 and 02. The 02 clock,
designated as KY1 CK2 H and KY1 CK2 L, is also used as a control pulse to clear system registers
and together with the sync pulse to define the end of a timing cycle.

Figure 5-1 shows the relation between the two clock pulses.
5.3.2 Power-Up Logic/Interrupt (Drawing CS M7859, Sheet 2)
The power-up logic/interrupt circuitry is comprised of E1-6, E40-10, E1-4, E36 E12, E29-1, E6, and
E26. These elements sense when the system turns on, generate the interrupt to the microprocessor
needed to start it, and clear registers to force program startup at location O.

5-5

BUS DC LO at E1-3 initiates the function by clearing E36 which is configured as an 8-bit counter and
generates KY1 PUP 1 L. This signal is routed to the Unibus control, indicator control, switch register,
and bus address register as a master clear line. The address register is provided with its own clear line,
KY1 ADR CLR L.

BUS DC LO L puts the microprocessor in the STOP state. The counter starts counting in the STOP
state (E6, E36). KY1 STOP L and KY1 C2 L at E29-1 clock E6. E6 is a divide by two on the clock,
while E36 counts from 0-7. Sixteen clock periods are thus counted. At the transition of E36 from 7to
0, the interrupt is generated at E12-8 and the microprocessor goes into the T1I state (Interrupt). KY1
TI1I L and KY1 CK2 L then reset E12 and clear the address register via E6-6 and the system is
initialized.
»
|
S

5.3.3 Microprocessor (Drawing CS M7859, Sheet 2)
|
o
The 8008 Microprocessor Chip (E18) was discussed in detail in Chapter 3. According to drawing CS
M7859, sheet 2, the unit communicates over an 8-bit bidirectional data bus via 8833 tristate trans~ceivers E16 and E17, with the satellite logic of the interface module. A single interrupt line is received
from the power-up logic to initiate microprocessor operations. Driven by a 2-phase, 500-kHz clock
(Figure 5-1), the element yields a 3-bit state output code, SO, S1, and S2, plus a sync pulse, to drive a
7442 Timing Phase Decoder. The latter element provides eight separate timing cycles for the sequencing of interface module data transfers and other discrete operations.
L

5.3.4 Timing State Decoder
|
o
|
|
|
The timing state decoder (E23) receives the state outputs SO, S1, and S2 from the microprocessor and
generates the timing states for the interface modules (drawing CS M7859, sheet 2). This unit is a 7442
4-line to 10-line decoder, with two unused outputs, that yields an 8-output sequence according to its 3input state code. State control coding is presented in Chapter 3. State control inputs are determined in
the microprocessor and depend on an internal 5-bit feedback shift register with the feedback path
controlled by the instruction being executed.
|
|
5.3.5 Address Register (Drawing CS M7859, Sheet 2)
|
The address register, the principal buffer between the microprocessor and the remainder of the interface module logic, consists of four 74175 quad, D-type, double rail output latches. The low order bits
are handled by E5 and E4 which generate KY1 ADRD 0 L through KY1 ADRD 3 L (E5) and their
complements (for RAM addressing), and KY1 ADRD 4 H through KY1 ADRD 7 H (E4), respectively. This 8-bit byte is the low order unit of the address or data with E10 and E28 containing the high
order information ADRD 08-13 and PC FUN 1 and 0.
|
|

The data contained in the address register is routed to the following locations according to direction by
the stored program:

1.
~

ROM (address
of next instruction)(KY1 ADRD 0 L » KY1 ADRD
8 L plus ROM1 EN L
orROM2ENL)

2. RAM (address
of data to be read or written) (KY1 ADRD
0 L - KY1 ADRD 3 L)

Unibus Control (KY1 ADRD 0 H— KY1 ADRD 3 H)

Indicator Control (KY ADRD 4 H » KY1 ADRD 7 H)

Data Bus Control (KY1 ADRD 9 H - KY1 ADRD 13 H, KY1 PC FUN 0 H, KY1 PC

Switch Register (KY1 ADRD 0 H - KY1 ADRD 7 H)

Bus Address Register (KY ADRD 0

H- KY1 ADRD 7 H)

5-6

The address register is loaded with a low order byte (E4 and E5) by signal KY1 LD AD 1 H, generated

by AND E22-12 at time state TS1. The high order byteis gatedin E28 and E10 by KY1 LD AD2H

generated at E22-6 at t1m1ng state TS2.

5.3.6 ROM
The interface module ROM con51sts of E3, E21, E33 and E39 (drawmg CS M7859, sheet 3). The four

512-word by 4-bit elements are addressed so that the ensemble looks like two 512- X 8-bit RMs. E3
and E21 are activated by KY4 ROM 1 EN L and E33 and E39 by KY4 ROM 2 EN L. Address bits
KY1 ADRD 0 H through KY1 ADRD 8 H are routed to all four ROM elements with the enable 1 or 2
determining the address activated and thus yielding 1024 8-bit locations. Outputs are wire ORed with
various inputs to. give the KY2 DIN O H through KY2 DIN 7 H inputs to the tristate transceivers, E16
and E17.
|

The ROM 1 or RM 2 enables are generated by the data bus control logic.
5.3.7 RAM
|
The scratchpad RAM consists of Ell and E27 (draw1ng CS M7859, sheet 3) These units effectively
comprise a 16-word by 8-bit read /write memory, and serve as worklng storage for the microprocessor
programs in storing addresses and data. Datais routed to the RAM (KY1 DOUT 0 H through KY1
DOUT 7 H) directly from the tristate transceivers of the microprocessor bidirectional data bus during’
RAM write operations. The 4-bit address lines KY1 ADRD 0 L through KY1 ADRD 3 L specify the
address to be read from or written into during read/write.

Selection of the RAM for read or writeis determined by the stored program via the data bus control.
Either KY4 RAM - DIN BUS L or KY4 RAM WRITE H must be true to select the RAM. Output
lines are wire ORed with various other microprocessor input ports to be routed to the 8833 tnstate
transceivers.
5.3.8 Switch Register (Drawing CS M7859, Sheet 6)
The switch register contains the 16-bit data used and consists of four 74175 quad D-type, double rail
output latches. The four elements comprising the register are E9, E19, E2, and E15. These units feed
the 8641 bus transceivers E7, E25, E8, and E13 (respectively). Incomlng 16-bit data (KYS BB D00 H
through KY5 BB D15 H)is applled to the 8093 tristate buffers and gated by an appropriate read line
from the data bus control. Outgoing data (BUS D00 L through BUS D15 L)is gated by KY4 EN DB
L, a signal generatedin the switch register address decoding logic (sheet 5).

The switch register is addressable from the Unibus as address 777570 as described in Paragraph 5.3.9.
5.3.9 Switch Register Address Decode Logic (Drawing CS M7859, Sheet 5)
The switch register address decoding logic allows the Unibus to address the SW1tch register via a

decoding of address 777570. The logic has two outputs:
1.

BUSSSYN L
KY4ENDB-BUSL

K44 EN DB - BUS L at E43-10 gates the data lines onto the Unibus (CS M7859, sheet 6) while the
assertion of BUS SSYN L designates that the slave device has completed its part of the data transfer.
The second stage of the address decode at E32 is gated by assertion of BUS MSYN L at E32-10.
Assertion of MSYN requests that the slave defined by the A (address) lines perform the function
required by the C lines. In this case, KY7 BB C1 H at invertor E40-9 specifies that the datais to be
‘transferred to the Unibus data lines.

5-7

5.3.10 Bus Address Reglster (Drawing CS M7859, Sheets 7 and 8)
The bus address register consists of five 74175 quad D-type, double rail output latches. The five
elements comprising the register are E67, ES7, E73, ES8, and E51. Input to the bus address register is
from the address register (KY1 ADRD 0 H through KY1 ADRD 7 H). Outputs are routed to the
display and keypad logic and to the 8641 Unibus transceivers E61, E56, E65, E55, and ES50.

A Unibus address is enabled to the Unibus via the bus address transceivers from the bus address
register by KY7 EN AR L generated at E51-11. The switch register is ‘available to the Unibus as

-address 777570 via the bus address transceivers and the switch reglster decode logic. The latter functlon is discussedin Paragraph 5 3.9.
E67 and E57 contain the keypad scan signals (KY6 SCAN 1 L through KY6 SCAN 6 L) whlle E73
drives the display (KY6 NUM 1 H through KY6 NUM 3 H).
Incoming 18-bit address information (KY6 BB A00 H through KY7 BB A17 H)is apphed to the 8093
tristate buffers and gated by an appropriate read line from the data bus control.
5.3.11 Data Bus Control Logic (Drawing CS M7859 Sheet 5)
The data bus control directs the reading and loadmg of the various interface module registers, the
- reading of the ROMs, and the reading/writing of the RAM. It also determines the direction of data
flowin the interface module and between the interface module and the Unibus, i.e., whether data will

be read from or be routed to the Unibus. A list of 1/O functions and associated select signals follows:
Select Signal
READ INPUTOL
READ INPUT 1L

|
o

o
B

READ INPUT 2L
READ INPUT 3 L

Function
UNIBUS DATA
|
~
UNIBUS ADDRESS
|

READ INPUT 4 L

'READ INPUT 5L

READINPUTG6L

'READ INPUT7L

LDREGOH

LD REG 1 H
LD REG 2 H

- KEYPAD REG
~

)

MAINTENANCE
R

BUS ADDR REG
'

)

LDREG3H

LDREGSH

LD REG 4 H

ENROM I L
ENROM2L

RAM WRITEH

‘

UNIBUS CONT LOGIC
ROM SELECT

- RAM WRITE

RAMDINBUSL
DIN DRIVERS DIS H

SWITCHREG

ENABLE RAM DATA
DISABLE DATA IN

5-8

Specifically, the data bus control loglc decodes memory references into three areas (ROM 1, ROM 2,
and RAM) and determines whether the access is a read or write. The logic also decodes I/ O instructions and generates loading or gating signals depending on the direction of data transfer and the port
selected.
In order to facilitate understanding of the logic, the following explanation of memory address allocation and I/0O instruction operation is mcluded

'ROM 2 (E33 and E39)
Memory addressing space spans locatlons 0 through 777.
ROM 1 (E3 and E21)
Memory addressing space spans locations 4000 through 47717.
RAM (E11 and E27)

Memory addressing space spans locations 20000 through 20017.

The two bus control signals provided by the m1croprocessor and latched with the upper byte of the
address register, KY1 PC FUN 0 H and KY1 PC FUN 1 H, determine data transfer direction and I /O
operations. The following table explains the decoding of these signals.

PC FU_N 0

PC FUN 1 |

_‘

Memory read of first byte of instruction only (fetch)
Memory read of additional bytes of ihstruction or data.

" L

Memory write (used only to write into RAM).

I/0 operatlon

Memory reads and writes signify that the address register (KY1 ADRD 0 H through KY1 ADRD 13
H) contains the address of the locatlonin memory to be accessed.

The code for I/0 operations, however, srgnlfies a very dlfferent situation. Thisis due to the following
~occurring after the initial instruction fetch cycle:
1.

During TS1 the content of the A register (accumulator) in the microprocessor is available on
the data lines and is latched into the low byte of the address register.

During TS2 the content of the instruction register (containing the I/O 1nstructlon)is available on the data lines andis latched into the high byte of the address register.

During TS3 of an INP (input) instruction, data on the data linesis loaded into the A register. On OUT (output) instructions, the datais strobed out of the low byte of the address
regrster
I/O Instruction Code:
~

INP

01 OOMMM]1

OUT 01 RRMMMI

5-9

"TS3 (INP) or to load the data from the low byteof the address reglster 1nto an output port durmg TS3

(OUT)

The 32 X 8 PROM (E34) does the initial decodlng of the type of transfer (read, write, or [/O) from the
signals KY1 PC FUN 0 H and KY1 PC FUN 1 H. If the transferis a memory read or write, it is
decoded into one of the following four signals. KY4 RAM - DIN BUSL (RAM read) KY4ROM 1
EN L (memory readin address range 4000-4777), KY4 ROM 2 EN L (memory readin address range
000-777), and an enable which is ANDed with KY1 SYNC H, KYI1 TS3 L, and KY1 CK2 L to
provide a write pulse, K<Y4 RAM WRITE H, to the RAM
-

Another enable from the PROMis ANDed Wlth KY1TS3Lto prov1de the s1gnal KY4 DIN DRIVER
DIS H. This signalis normally high, disabling the driver portions of the 8833 transceivers (E16 and
E17). It will be low only dur1ng TS3and when data transferis 1nto the mlcroprocessor o

| Two other outputs of the PROM are used for1/0 operatlons One output of the PROM (E34 7), when

‘low, enables the 74154 4-to-16 decoder on all 1/0O instructions. The second output (E34-9) determines
’ whether the I/0 instruction 1s INP or OUT If the instruction is OUT then thesignal will be h1gh

Note that address register bits KY1 ADRD 11, KY1 ADRD 10 H, and KY1 ADRD 9 H, are applied
to the low order inputs of the 74154. This selects which of the poss1ble ports will be used. The fourth
input, the highest order input, determines if it is an INP or OUT instruction. This input is the ANDed
condition of the PROM output (E34-9), KY1 SYNC H,KY1TS3, and KY1 CK2. Thus, if the instruction is an INP, then the input gating signal will be one of the lower order e1ght outputs of the 74154
(KY4 READ IN O L through KY4 READ IN 7L).
L
o

If the PROM signal (E34-9)is high, signifying an OUT instruction, then 1n1t1ally a low order output is
selected (does not substantially affect anything) and then a high order output will be pulsed as the
gated clock pulseis applied to the high order input of the 74154. Thus, the high order outputs are
pulsed and buffered to prov1de loadmg pulses to the selected reglsters (KY4 LD REG 0 H etc. )

5.3.12 Umbus Control (Drawmg CS M7859, Sheet 5)

Unibus controlis accomplished via two 74175 quad, D--type, double rail output latches E52 and E64.
The stored program input bit configurations are read in under control of an appropriate data bus
control signal, LD REG 5 H. E64 D2 and D3 latches are utilized for the manual clock enable and
manual clock lines while the other six lines are Unibus control signals.
o
|

5.3.13 Keypad Scan Loglc (Drawing CS 5411800-0-1)

The logic and driving c1rcu1try for the keypad and display elementsis located on a c1rcu1t boardin the
V.rear of the programmer S console panel
-

Scan s1gnals for the keypad are generated at the 1nterface module (bus address reglster) These six lines
(KY6 SCAN 1 L through KY6 SCAN 6 L) are then routed through hex 7417 buffer drivers to the
console circuit board where they are designated as READ and DRIVE signals. As indicated by CS
5411800-0-1, sheet 2, READ 1 through READ 5 signals continuously scan the keypadin groups of 4.
As each READ s1gnalis applied to check for a pressed key, a corresponding DRIVE signalis simulta-

neously generated and applied to the appropr1ate transistor in the LED d1splay circuitry (CS 11800-01, sheet 3)
o
o
r

A pressed key thus results in activation of 1 to 4 lines. This information'is rout’e'd out through J1to the
interface module and applied
to the _data_bus for eventual read-in
to the miroprocessor.

5-10

AN
‘

Note that the two most significant bits of the instruction will correspond to PC FUN O = 1 and PC
FUN 1 = 0 when loaded into the high byte of the address register, thusdenotlng an I/ O operation.
| Therefore the data bus controllogic determines whether to gate data into the microprocessor during

5.3.14

Indicator Logic (Drawmg CS M 7859, Sheet S)

‘The indicator control consists of a single quad D-type, latch configuration, 74175 (E68) and four 7417
open collector inverters (E69) for driving the panel indicators. Input bit coding KY1 ADRD 4 H
through KY1 ADRD 7 H via the stored program determines which of the following panel indicators
are turned on:
.
1.
2.
3.
4.

5.3.15

BUS ERR
SR DISP
MAINT
BOOT
Halt Logic (Drawing CS M7859-0-1, Sheet 9)

The halt logic allows the console to obtain control of the Unibusin order to perform Unibus transactions. Control of the Unibus is passed to the KY11-LB from the PDP-11 processor via a HALT
REQUEST and HALT GRANT sequence. Use of the HALT/SS key initiates a program sequence
within the KY11-LB to issue a HALT REQUEST to the PDP-11 processor. The procesor will arbitrate the request and at the appropriate time will respond with HALT GRANT. The reception of
HALT GRANT H by the halt logic direct sets the HALT SACK flip-flop on E63-4, causing BUS
"SACK L to be generated at E62-13. The set output of the HALT SACK flip-flop (E63 5) sets up the
‘data input of the HALT BUSY flip-flop (E63-12).
The reception of BUS SACK L by the PDP—ll processor will cause it to drop HALT GRANT H.
When the Unibus becomes free (unasserted BUS BUSY L and BUS SSYN L), the E63-11 will be
clocked, setting the HALT BUSY flip-flop. This, in turn, asserts BUS BUSY L through E62-10 and
causes the RUN indicator to be turned off via the 7417 buffer (E66-12). This logic operates in the same
manner if the HALT GRANTis generated not by a HALT REQUEST from the KY11-LB but by a
HALT instruction in the PDP-11 processor. The output of the HALT BUSY flip-flop (KYB HALT
BUSY H) can be tested by the microprocessor program to check if the console has control of the
Umbus before performing Unibus transactions.

The HALT SACK and HALT BUSY fhp flops are direct cleared by either BUS INIT L from the
Unibus or by the signal KY4 CLR BUS L which can
be generated by the microprocessor program.
Clearing these flip-flops relinquishes control of the Unibus to the PDP-11 processor.

The signal KY4 TAKE BUS L, which can direct set the HALT BUS flip-flop, allows the micro-

processor program to perform Umbus operations without first obtaining the Unibus through a legal
request. This signalis only used during maintenance mode operatlon of the KY11-LB to bypass a

failing or hung processor.
5.3.16

5.3.16.1

Buffers (Drawing CS M7859 Sheet 4)

Tristate Buffers (8093)- The following units, which are gated by read input signals from the

data bus control, buffer 1nput data from several sources.

Unibus Data
Unibus Address
Keypad Register
|
Maintenance Inputs (from processor microprogram counter).

Outputs from the 8093s are wire ORed and sent to the trlstate transcelvers w1th the ROM and RAM
data as KY2 DIN 0 H through KY2 DIN 7 H.

5.3.16.2

Tristate Transceivers (8833)- These units buffer data between the mrcroproeessor b1d1rec-

tional data bus and the satellite logic of the interface module.

5-11

CHAPTER 6

CONSOLE MODE OPERATION

6.1

INTRODUCTION

This chapteris a recapitulation of all console key and indicator functlons Operatlon use, and exam-

ples of the utilization of each key are presented. Key operations are divided into console mode and
maintenance mode. Examples of console sequences to demonstrate the proper use of the KY11-LB are
presented together with further notes and hints on operation.
6.2

CONSOLE KEY OPERATIONS

This section describes the operation of each keyin a step-by-step procedure. The readeris assumed to
have read earlier chapters as some descriptions include the use of keys previously described.

A notation for each key will be introduced in each description and is enclosed in angle brackets < >.
These notations are used extensively in Paragraph 6.4 to describe various sequences of key operations.
<CLR> - Used to clear an incorrect entry or existing data.
1.
2.

Press and release the CLR key.
The display (six digits) will be all zeros.

Clears the SR DISP, BUS ERR, or MAINT 1nd1cators if on.

Numerics 0-7 - Used to keyin an octal numeric d1g1t (v through 7).,
1.
2.
3.

Press a numeric key (0 through 7).
The corresponding -digit will be left shlfted into the 6-digit octal display with the previously
displayed digits also being left shifted.
Release the numeric key.
|

ok
=

To enter the number <xxxxxx>, e.g., 123456'.

Press and release the CLR key (000000 will be dlsplayed)
Press and release the 1 key (000001 will be displayed).
Press and release the 2 key (000012 will be displayed).
Press and release the 3 key (000123 will be displayed).
Press and release the 4 key (001234 will be displayed).
Press and release the 5 key (012345 will be displayed).
Press and release the 6 key (123456 will be displayed).

The number has now been entered. Leading zeros
do not have to be entered.

<LSR> - Used to load the switch register (accessible as Unibus address 777570).
1.

Press and release the LSR key.

The d1splay will show the data loaded and the SR DISP indicator will be on.

To load the number 777ie.,<LSR 777> into the switch register:
1.
2.
3.
4.

Press and release the CLR key.
Key in the number 777.
Press and release the LSR key.
T77 Wlll be dlsplayed and the SR DISP. indicator will be on.

<LAD>
- Used to load the Umbus address pomter prror to performmg an EXAMINE DEPOSIT or
START

Press and release the LAD key

Display will be all zeros.

BN =

To load address 200 1. €., <LAD 200>
Press and release the CLR key.
Keyin 200.
Press and release the LAD key
“Displayis all zeros.

<DIS AD> - Displays the current contents of the Unibus 'address pointer.
1.
2.

Press and release the DIS AD key.
Display will show the current Unlbus address pomter

To perform the sequence. |
LAD 400
DIS AD

W N

. Press and release the CLR key
Key in 400.

Press and release the LAD key (d1splayis all zeros)

Press and release the DIS AD key.
Display shows the 400 from the Unibus address pomter

<DEP> - Used to dep031t a number 1nto the locatlon pomted to by the Un1bus address pomter

Processor must be halted (RUN1nd1cator off) otherw1se keyis 1gnored
Press and release the DEP key.
Display shows the data deposited.

1.
2.
3.

6-2

To deposit <DEP XXXXD (e.g., 5252) into location 1000, the sequence is as follows:

LW
—

LAD 1000
DEP 5252

Press and release the CLR key; 'g
Keyin 1000.
Press and release the LAD key.
Keyin 5252.
,
Press and release the DEP key.

<EXAM> - Used to examine the contents of a location pointed to by the Unibus address pointer.
1.
2.
3.
\ —

Machine must be halted.

Press and release the EXAM key.
Display shows the contents of the locatlon exammed

- To examine general-purpose regrster R7 (program counter) at Unrbus address 777707 the followmg
sequence is used:

LAD 777707
EXAM

Press and release the CLR key
Keyin 777707.
Press and release the LAD key.
Press and release the EXAM key.
The contents of R7 will be dlsplayed

<CNTRL>
- The CNTRL keyis always usedin con3unct1on with some other key When 1t is used 1t
must be pressed and held down while the second keyis pressed and released
|
|
'
<CNTRL-HLT/SS> - Used to halt the processor.

Press and hold down the CNTRL key.

Press and release the HLT/SS key.
3.

Display will show the current contents of R7 (program counter) and the RUN 1nd1cator w1ll

be off.
4.

Release the CNTRL key.

If the processor is already halted the use of the HLT / SS key wrll srngle-rnstructlon step the processor |
(The CNTRL keyis not requ1red to smgle-mstructlon step the processor once halted )
1.

Press and release the HLT/ SS key.
Processor will perform one instruction and halt.
|
|
Display will show the new current contents of R7 (program counter)

6-3

<CNTRL-CONT> - Used to allow the processor to begin running from a halt.
1.
2.

. -

(

Press and hold down the CNTRL key
Press and release the CONT key.

Processor will run unless a program halt instruction is encountered. The RUN and SR DISP
indicators should be on and the contents of the switch register should be displayed. If a halt
instruction was encountered, the indicators will be off and the program counter will be
displayed.
Release the CNTRL key.

(i the processor

|
NOTE
is already running, use of

<CNTRL-CONT>> will resultin the switch register
being displayed; there will be no other effect on the
processor

Eala

<CNTRL BOOT> Used to mrtrate runmng of M9301 Bootstrap program Processor must be halted
Press and hold down the CNTRL key.
Press and release the BOOT key.

(

“

Processor should start running (RUN 1nd1cator on) the bootstrap programselected on the
M9301.

|
NOTE
For more information concerning the M9301 Boot-- .~
strap program, consult the system users guide. =~

(

Release the CNTRL key

.«

B RN

<CNTRL START> Used to start theprocessor runmng a.program from a g1ven startmg address
Processor must be halted otherwise keyis.ignored.
Press and hold down CNTRL key.
~
Press and release the START key.
SRR

Release the CNTRL key.

‘

RUN indicator will be on unless a halt 1nstructlon i encountered The SR DISP 1nd1cator

« -should also be on and the contents of the switch register: should be displayed..
=

(

QMPWN?f

To start runnmg a program at locat1on 1000 the followmg sequence 1s used
Press and release the CLR key R
T T
T S
TRV
Keyin 1000.
S
|
Press and release the LAD key.
.
Ce
T
Press and hold down the CNTRL key T
S
Press and release the START key..
R
TS
N
IO S DI
Release the CNTRL key.

R
~

e e
S
RGO

Rdlhaiiadl
> e

<CNTRL-INIT> - Generates a Bus Initialize without the processor starting.
Processor must be halted.
Press and hold down the CNTRL key.
Press and release the INIT key.

Bus Initialize will be generated for 150 ms.
Release the CNTRL key.

6-4

(

;

<CNTRL-7> - Used to calculate the correct address when a mode 6 or 7 register R7 instruction is

encountered.

2.
3.

Press and hold down the CNT

L key

Press and release the7 key
|
D1splay will show the new temporary reglster wh1ch contarns the old temporary reglster plus
the Unibus address point or plus 2.

See 'Paragraph 6.4 foran example.
<CNTRL-6>
- Used to calculate the offset address when mode 6 or 7 1nstructrons other than register

R7 are encountered.

Press and hold down theCNTRL keyl

Press and release the 6 key.
Display shows the new temporary reglster Wthh contains the old temporary plus the switch
register.

Release the CNTRL key.

2.
3.

See Paragraph 6.4 for an example.
<CNTRL-1>
- Used to enter the console into maintenance mode Malntenance mode should only be
used as an aid to troubleshooting hardware problems. Maintenance mode provrdes no helpin debugging software problems.
S
,
|
1.

3.
“ 4.

6.3

Press and hold down the CNTRL key
Press and release the 1 key.

MAINT indicator will be on and the MPC (m1croprogram counter) will be sampled and
displayed.
_
oy
Release the CNTRL key

NOTES ON OPERATION

An erroneous drsplay will result if, while the processor is runnlng and the switch.reglster is bemg
-

displayed, a numeric keyis pressed. Although the SR DISP indicator will remain on, the d1sp1ay no
longer reflects the actual contents of the switch register. 1If at any time while the processor is running, it
is des1red that the switch register contents be displayed, the CNTRL—CONT keys should be used.
As a general practice, prior to entermg a new 6-digit number and if the displayis nonzero, the CLR key

should be used to initially zero the d1splay

In orderto s1ngle-1nstruct1on step the processor from a glven startmg address, the program counter
(R7) must be loaded with the starting address using the Unibus address of R7 (777707)i.e., to s1ngleinstruction stepfrom the beglnnmg of a program starting at locatlon 1000, the following sequence is

necessary:

LAD 777707
DEP 1000

- CNTRL-INIT (if des1red)
HLT/SS
HLT/SS

etc.

6-5

The console requires an 18-bit address Thisis especially 1mportant toremember when accessing device
registers (i.e., 777560 instead of 177560). Otherwrse an erroneous access to memory or to a nonexistent
address will occur.
o
The Unibus addresses for the general-purpose registers can only be used by the console. A PDP-11
program using the Unibus addresses for the general-purpose registers will trap as a nonexistent
address. Also, internal registers R10 through R17, which are used for various purposes (depending
upon processor), may beaccessed by the console through Umbus addresses 777710 through 7 777 17.
The BUS ERR indicator on the console reflects a bus error by the console only. The 1nd1cator will not
reflect bus errors due to other devices succh as the processor,

6. 4 EXAMPLES OF CONSOLE SEQUENCES
|
|
This section combines key opcratrons wrth example sequences to demonstrate the proper use of the
KY11-LB Programmer S Console
|
|
|

The following sequences use the notatiOns for 'key operatiOns as described in Paragraph 6.2.
The angle brackets <
> will be used in the sequences to 1dcnt1fy the display contents after the
operation is performed ie., LAD 200 <0>
1.
2.
3.
4.

Press and release the CLR key.
Press and release 2 key.
Press and release 0 key.
Press and release 0 key.
»

Press and release the LAD key.

000000 will be dlsplayedin the 6- d1g1t readout

Example 1
This sequence uses the examine function and the swnch reglster Umbus address 777570 to read the
‘contents of the SW1tch register.
.
LSR 123456

EXAM
DISAD
LSR 777
EXAM

.<123456> I

o
R ».f<123456>’“
<LT77570>
o
L1T>
o
<TTT>

Example 2

This sequence ‘demonstrates the use of the followmg kcys LAD DIS AD LSR, EXAM DEP,
CNTRL-START, CNTRL—C()NT andCNTRL—HLT/SS

This example loads the followrng program 1nto memory, whlchis then runto demonstrate various
operatlons
.
Program

Memory Location/Contents

1000/13737

1002 /177570
1004/1014
1006,/0000
1010/137
1012/1000
1014/0000

;Move the contents of

theswitch register to
~

S
|
|

|
7

memory location 1014
;Halt
Jump to location 1000

- Sequence |
-

<0>

DEP 13737
DEP 177570
DEP 1014
- DEPO
DEP 137
-DEP 1000
DEPO

LAD 1000
EXAM

EXAM
- EXAM
EXAM
EXAM
EXAM
EXAM

"DISAD =
LSR 123456
LAD 1000

CNTRL-START
LAD 1014
EXAM
DEPO
EXAM
DIS AD
LSR 125252

CNTRL-CONT
LAD 1014
EXAM
DEPO
LAD 1006
DEP 240
EXAM
LAD 1000

CNTRL-START
LSR 70707
CNTRL-HLT/SS
LAD 1014
|
EXAM
HLT/SS
HLT/SS
~ HLT/SS

<1000>

<0>
<0>
<13737>
<177570>
- <1014>
<0>
<137>
- <1000>
<0>
<1014>
<123456>
<0>
<1010>
<0>
<123456>
<0>
<0>
<1014>
<125252>
<1010>
- <0>

<125252>
<0>
<0>
<240>
<240>
<0>
<125252>
<10707>

<0>
<10707>

<052525>
<0>

- <052525>

LSR 05252
HLT/SS
LAD 1014
EXAM

<13737>
<177570>
<1014>
<0>
<137>

6-7

- Example 3

This sequence demonstrates the use of CNTRL-7 and CNTRL—6 The followmg dataare loaded into
memory:

- 1000/177

1002/100
1004/000
1006/5060

1010/1020
1104/1006
RO = 777760

The sequence to load the datais as follows:

LAD IOOO
DEP 177

<177>

DEP 100

<100>

DEPO0

<0>

DEP 5060
- DEP 1020

<5060>

LAD 1104

<0>
<1006>

<1020>

DEP 1006
LAD 777700

<0>
<777760>

DEP 777760

Sequence
LAD 1000
EXAM
EXAM

<0>
<177>

- <100>
<1104>

CNTRL-7
LAD
EXAM
LAD
EXAM
EXAM
LSR
LAD 777700
EXAM

<0>
|
<1006>
<0>
<5060>
- <1020>
<1020>
<0>
<T777760>
- <100006>

CNTRL-6
LAD
EXAM

- <0>
-

<177>

CHAPTER 7

- MAINTENANCE MODE OPERATION

7.1

INTRODUCTION

This chapter covers the keypad facilities of the programmer s console available for hardware malntenance of the processor.
7.2

MAINTENANCE MODE KEY OPERATIONS
The following definitions apply to a subset of the same keys used in console mode however the
functions and operatlons differ from thosein console mode. In general, console mode functions are
not available whlleIn maintenance mode, and many keys have no functronin maintenance mode.

NOTE
Maintenance mode operation is mdlcated by the
MAINT indicator being on.

In order to use the hardware maintenance features avallablein malntenance mode the maintenance

cable (11/04) or cables (11/34) must be connected between the KY11-LB interface board (M7859) and
the corresponding processor board (M7263-11/04, M7266- 11/34, M8266-11/34A, or
- M8267-FP11A). An exception to thisis the 5 (maintenance mode) operation which allows the console
to examine or deposit into memory or device registers without the processor bemg e1therpresent or

functional.

///—\\

DIS AD (Maintenance Mode) -~ Used to display. Unibus address lines.
1.
2.

Press and release the DIS AD key.

Unibus address lines will be sampled (read once) and displayed, i.e., d1splay w111 not be

updated as address 11nes change.

EXAM (Marntenance Mode) Used to d1sp1ay Unlbus data hnes
1.

Press and release the EXAM key.
|
~Unibusdata lines will be sampled and displayed.

HLT/SS (Malntenance Mode) - Asserts manual clock enable and displays MPC (mlcroprogram

counter).
1.

Press and release the HLT/ SS key.

Manual clock enable will be asserted.
MPC will be sampled and displayed.

1.
2.

| 3.

the MPC.

i ,/"_“\\“

CONT (Maintenance Mode) - Single microsteps the processor through one microstate and displays
Press and release the CONT key.
Manual clock will be pulsed.

New MPC will be sampled and displayed.

BOOT (Maintenance Mode)-~ Boots the M9301. If manual clock enableis asserted, the M9301 routine
will not be entered but because the M9301 simulates a power fail the processor will power up through

location 24.

Press and release the BOOT key.

The display is not affected. If manual clock enable is asserted, the MPC is now at the
beginning of the power-up sequence. To see the new MPC, use the HLT /SS key

START (Maintenanc‘e Mode) - Drops manual clock enable.

Press and release the START key.

2. Manual clock enableis released.
3 MPC w1ll be sampled and dlsplayed

)

CLR (Mamtenance Mode) Returns console to console mode operation.
I.
2.
3.
4

Press and release the CLR key.
MAINT indicator is off.
.
Processor should halt.
Program counter should be dlsplayed

B
N

(

5 (Mamtenance Mode) Allows the console to take control of the Umbus if a processor is not in the
system

1. Press and release the 5 key.

The MAINT indicator will be off (console mode operation now).

Console attempts to read the program counter whichis not present and therefore the BUS
ERR indicator will be on.

7.3 NOTES ON OPERATION
|
S
|
If the smgle-mwrostep featurein maintenance modeis to be used it is preferable that the processor be
halted prior to entering maintenance mode, if it is poss1b1e Thisis because the assertion of manual
clock enable, which turns off the processor clock if it is running, cannot be synchronlzed with the
processor clock. Therefore, if the processor is not halted, the clock may be running and the assertion of

(

manual clock enable may cause an erroneous cond1t1on to occur.

In order
to single-microstep the processor from the beginning of the power-up sequence, the following -

steps may be used:
1.

Halt the processor if possible.

Use CNTRL 1 to enter mamtenance mode.

Use HLT /SS to assert manual clock enable (RUN indicator should come on).

Use BOOT to generate a s1mulated power-fail (will not work if M9301 is not present in the
system).
|

(

.
.
'-\

. /m\
.

Use HLT/SS to display the MPC (microprogram counter) for the first microstep in the

power-up routine.

Use CONT to single-microstep the processor through the power-up routine. (The new MPC
will be displayed at each step.)

Unibus address lines and Unibus data (see NOTE below) lines may be examined at any
microstep by using DIS AD and EXAM, respectively. Use of these keys does not advance
the microprogram. To redisplay the current MPC without advancing the microprogram, use
the HLT/SS key.
:
To return from maintenance mode, use the CLR key.

To single-microstep through a program, the program counter (R7) must first be loaded with
the starting address of the program as in smgle-mstructlon stepping the processor prlor to
entering maintenance mode.
NOTE
Because the data transfer occurs asynchronously
with the processor clock, Unibus data will not be displayed on DATI in maintenance mode when using

the console with an 11/04 processor. Unibus data on
DATO on the 11/04 and both DATI and DATO on

the 11/34 will be displayed.
Due to hardware changes, the M8266 module will

gate the AMUX lines onto the Unibus when manual
clock enableis asserted and a Unibus transactlon is
not occurring.

7-3

CHAPTER 8
KY11-LB MAINTENANCE

8.1

PRELIMINARY CONSIDERATIONS

The followingis a guide to locating possible problems on the KY11 LB
1.

Power Switch Failure - If the power switch fails to control the pdwer 'supply, check cable

7011414-2-2 (BA11-L) at J2 or cable 7011992-0-0 (BA11-K) at Faston tabs TB4 and TB5 on
the bezel- mounted board to ensure that cable(s) are securely and correctly installed.

If the power switch does turn on the power supply (fans turn) but the DC ON indicator does

not come on, check cable 701 1992 0-0 (BA11-K) at tabs TB6 and TB7 on the bezel-mounted

~ board.

If the four indicators on theleft Slde of the keypad are all on, then the cable 7012214-0-0

connecting the bezel-mounted board to the 1nterface board (M 7859)is probably pluggediin
backward on one end.

If no display and none of the four indicators are on, then check cable 7012214 0-0 at J1 on
the bezel-mounted board and M7859 board to ensure that it is eorrectly and seeurely‘
installed.

Note that there should be no cables from either the bezel-mounted board or the M7859
board attached to the backplane. The connection at the backplaneis for use by the KY11LA Operator Console only.

If the RUN indicator is on but there is no display and no responsefronr the keypad, the
problem is probably at the M7859 Interface module. Check the module to ensure that the

microprocessor chip (E18) is securely installed in its socket.

If the display works and the console responds to the keypad except for the BOOT key, check

that cable 7011413-0-0 is properly connected to the M9301 and to the bezel-mounted board
at tabs TB1 and TB2.

If the display MPC, single microstep, etc. functions in maintenance mode do not work
correctly, check that the cable(s) from J2 and J3 of the M7859 are properly installed.
NOTE

These cables should be installed only for maintenance of the processor. By disconnecting these cables
for normal operation, the effect is that the maintenance functions are nonoperative except for the
TAKE BUS function.

8-1

8.2

M7859 FAILURES

In general, there are two levels of poss1ble failures on the M7859 module. The first level and most
difficult to fixis themicroprocessor and its support logic which constitutes about 1/3 of the logic. The
second level is failures which occur in the perlpheral logic constituting the Unlbus 1nterface and the
display/keypad interface. These are generally easier to troubleshoot.

Generally, a first level failureis readily apparent and will usually be indicated when no dlsplayis on
and the only indicators onare DC ON and RUN

A second level failure, although easier to troubleshoot is not always readily apparent as it may only
occur on certain key functions or may be data dependent. A failure on the display/keypad interface
would be indicated by odd displays, row, or column failures on the keypad. The Unibus interface can
be tested with a good confidence level by loadmg the switch register with a 123456 data pattern and
then reading it back over the Unibus by examining locat1on 777570

The following1is a guide to troubleshootmg a failing M7859 module. Generally, the minimum equ1p-

ment neededis a dual trace osc1lloscope with delayed sweep.

1L ._Check that 9 Vis ava1lable at pin l of the mleroprocessor E18
2.
~

Check that the clock frequencyis 1.0 MHz + 2% at the test point, TPl The frequency can
be eorrected if needed by adJustmg the var1able res1stor at the top of the module

Check that the two clock signals are at E18-15 and E18-16. These clocks should be 500 kHz

‘frequency with nonove_rlappmg positive pulses of 0.5 ms dutatlon (Figure 8-1).

E18-16

E1815 02

l |

"FIG X
11-4858

Figure ‘8'-1' _Cloek Wavefo_rms'

)
-)
‘\\.
. ~

Check the signal at E18-18 which should be at logic low. If the signalis high the microprocessor may not have responded to the interrupt request on power-up. If the signalis

toggling, this may be indicative of a different class of problems discussedin the following
paragraphs.

The M7859 logic is such that if the MiCroprocessor encounters a HALT instruction and goes

‘to the STOP state, peripheral logic will automatically try to restart the microprocessor from
location 0. Hence, if there are problems in the microprocessor support logic, such as address
or data failures, time state decoding failures, etc., the microprocessor will not follow the
program and generally encounters a HALT instruction.
|

The general technique to solve this class of problems is to sync off of the signal STOP L and
to use delayed sweep to track addresses backward to find the specific failing address. A
quick check of the number of times TS1 L is true between the times that STOP L is true will
- give an idea of how far into the program the failure occurs. In general the easiest techniqueis
to use the TS3 L s1gna1 as a visual key on one channel while using the other channel to probe
addresses data, timing signals, etc.

CHAPTER 9

KY1i-LB INSTALLATION

9.1

KY11-LB DESCRIPTION

The KY11-LBis a programer’s console option for both the 11 /04 and 11/34 CPUs. It replaces the
KY11-LA (operator’s console) whichis the standard console on 11/04s and 11/34s. The hardwarein
the KY11-LB option is exactly the same for both the 11/04 and 11/34. The KY11-LB contains a bezel
assembly (consisting of a keypad, 7-segment display, indicator lamps and ON/OFF switch) and a
separate SPC quad interface module (M 7859). Also, three loose piece cables: two 10-conductor, 45.7
cm (18 inch) long cables and one 20-conductor cable. The two 10-connector cables are not required for
normal console functions and should only be installed when using the consolein. maintenance mode.
9.2
CPU BOX TYPE
PDP-11/04s and 11/34s are availablein both the BA11-L 13.4 cm (5-1/4 1nch) box and BA11-K 26.7
cm (10-1/2 inch) box. The difference between these two boxes creates the only differencein installing
the KY11-LB. In allcases, the 10-conductor cable, running from the operator s console to the CPU

backplane, is not used and must be removed when the KY11-LBis installed. Itis extremely 1mportant
not to connect thls cable to theKY11- LB as a short circuit may result.

/’/-\.\ .

9.3
CPU DIFFERENCES
The 11/04 is a single-module CPU (M7263). The 11/34 is a 2-module CPU (M7265 and M7266).
Maintenance mode connections between KY11-LB and 11/04 are made on the M7263. Maintenance

mode connections between KY11-LB and 11/34 are made on the M7266 (Figures 9-1 and 9-2). Note
that all figuresin this procedure show the M7266 module (11/34). Thisis done because the hook-up
for normal KY11-LB operation is the same for both CPUs.
|
To identify cables and part numbers for cables, refer to Figure 9-3.

9.4 BAI11-L 13.3 CM (5-1/4 INCH BOX) INSTALLATION
1.

from the CPU backplane to J1 on the KY11-LA must be removed. No connection is made
from the backplane to the KY11-LB.

9-1

CONNECTOR FOR KY11-LB
|

CONNECTS TO J2 ON M7859

PIN 1 -

DURING MAINT MODE OPERATIONS

M7263

(11/04)

11-4849

Figure 9-1 M7263

CONNECTORS
FOR KY11-LB

- CONNECTED TO M7859 ONLY

DURING MAINT MODE OPERATION

. M7266
(11/34)

11-4850

Figure 9-2 M7266

9.2

CHAPTER 9

) A\

KY1i-LB INSTALLATION

9.1 KY11-LB DESCRIPTION
The KY11-LB is a programer’s console optlon for both the 11 /04 and 11/34 CPUs. It replaces the
KY11-LA (operator’s console) whichis the standard console on 11/04s and 11 /34s. The hardwarein
the KY11-LB option
is exactly the same for both the 11/04 and 11/34. The KY11-LB contains a bezel
assembly (consisting of a keypad, 7-segment display, indicator lamps, and ON/OFF switch) and a

separate SPC quad interface module (M7859). Also, three loose piece cables: two 10-conductor, 45.7
cm (18 inch) long cables and one 20-conductor cable. The two 10-connector cables are not required for
normal console functions and should only be installed when using the console in maintenance mode.
9.2

CPU BOX TYPE

PDP-11/04s and 11/34s are availablein both the BA11-L 13.4 cm (5- 1/4 1nch) box and BA11-K 26.7

cm (10-1/2 inch) box. The difference between these two boxes creates the only differencein installing
the KY11-LB. In all cases, the 10-conductor cable, running from the operator s console to the CPU
backplane, is not used and must be removed when the KY11-LBis 1nstalled Itis extremely 1mportant
not to connect thls cable to theKY11- LB as a short circuit may result.

9.3

CPU DIFFERENCES

The 11/04 is a single-module CPU (M7263). The 11/34 is a 2-module CPU (M7265 and M7266).
Maintenance mode connections between KY11-LB and 11/04 are made on the M7263. Maintenance
mode connections between KY11-LB and 11/34 are made on the M7266 (Figures 9-1 and 9-2). Note
that all figuresin this procedure show the M7266 module (11/34). Thisis done because the hook-up .
for normal KY11-LB operatlon is the same for both CPUs.
To identify cables and part numbers for cables, refer to Flgure 9-3.

9.4 BAII-L 13.3 CM (5-1/4 INCH BOX) INSTALLATION
1.

Remove the operator’s console (KY11-LA), noting to which Faston tabs the M9301 is connected. The connections will be to the same tabs on the KY11-LB. The cable from H777
Power Supply plugged into J2 on the KY11-LA will plug into J2 on the KY11-LB. The cable
from the CPU backplane to J1 on the KY11-LA must be removed. No connection is made
from the backplane to the KY11-LB.

9-1

CONNECTOR FOR KY11-LB

CONNECTS TO J2 ON M7859

o
»

o
°®

&
®
-

DURING MAINT MODE OPERATIONS

M7263

(11/04)

11-4849

Figure 9-1 M7263

CONNECTORS
FOR KY11-LB
"~ CONNECTED TO M7859 ONLY

DURING MAINT MODE OPERATION

i
' M7266

(11/34)

11-4850

'.Fi‘gure‘9-2'~ M7266

9-2

In
.

INDICATES PIN 1

M9 =

—)
20 CONNECTOR

o I

10 CONNECTOR
o

PART #70-11411-1D-0

(18 in. LONG)

;

‘

PART #70-12214-0-0
LENGTH 2" 4" =+ 1"

PART #70-11411-0J-0

skl
s

(8 in. LONG)

11-4851

Figure 9-3

Cables

Install M7859 (KY11-LB 1nterface)in any SPC slot (within CPU backplane) and connect it

to the KY11-LB bezel as shownin Figure 9-4.

CONFIGURATION NOTE
‘
|
The M7859 consumes 2A at +5 V and can only be
plugged into the CPU backplane.
|
WARNING

\‘

When doing any reconfiguratmg of the CPU backplane that might be necessary to make room for the
M7859, be sure that the M9302is never installedin a
modified Unibus slot (which resultsin short circuits).

. /

9.5

BA11-K 26.7 CM (10-1 /2 INCH BOX) INSTALLATION

Remove the operator’s console (KY11-LA), noting to which Faston tabs the M9301is con-

nected. The connection will be the same tabs on the KY11-LB (Figure 9-5). You will notice
that J2 on the operator’s consoleis not used on the BA11-K box. The signals and voltages
that come in on this jackin the BA11-L box come in on Faston tabsin the BA11-K box. The
cable connecting the CPU backplane to J1 on the operator s console must be removed and

no connection from the backplane to the KY11-LB is made.

Install M7859 (KY11- LB 1nterface)in any SPC slot (with CPU backplane) and connect to
KY11-LB bezel as shown in Figure 9-5.

WARNING

When doing any reconfigurating of the CPU backplane that might be necessary
to make room for the
M7859, be sure that the M9302 is never installed in a
modified Unibus slot (which results in short circuits).

9.3

L7
J2

M7266

CPU BACKPLANE
RED STRIPE —

10 CONDUCTOR CABLE

10 CONDUCTOR CABLE ~5y
RED STRIPE
RED STRIPE
s\

TB1

TB2

TB3

TB4

TB5

TB6

OPERATORS CONSOLE KY11-LA

M7266
M7859

‘
B

pARN

CPU BACKPLANE

REDSTRIPE

20 CONDUCTOR CABLE

CONDUCTOR CABLE

|
SW

RED STRIPE

o
RED STRIPE —

ENA

T
J1

TB1

TB2

TB3

TB4

TB5

TB6

' PROGRAMMERS CONSOLE KY11-LB

TO M9301 ==
3 THIS CONNECTOR NOT USED
11-4847

Figure 9-4 BAII-L

9-4

L7
J2

M7266

CPU BACKPLANE
RED STRIPE —

RED STRIPE
s\

BLUE/BLK T.P..

RED/BLK T.P.

10 CONDUCTOR CABLE ~5

a4
ENA +5V GND

GND ON

U L

J U Uy

TB1

TB2

TB3

TB4

TBS

TB6

OPERATORS CONSOLE KY11-LA

s
J2

M7266

M7859

CPU BACKPLANE

REDSTRIPE

RED/BLK T.P.

BLUE/BLK T.P.

20 PIN CABLE

RED STRIPE \\_‘_

ENA

+5V

GND

Uuuu
TB2
TB3 TB4

TB5

U
TB6

TB1

—
J2

PROGRAMMERS CONSOLE KY11-LB

TOM93071 ==

X H775C
11-4848

Figure 9-5

BA1l1-K

9-5

9.6

MAINTENANCE MODE HOOK-UP
|
|
To utilize the KY11-LB as a maintenance tool for troubleshooting the CPU or
system, additional
cable(s) must
be installed. The 11/04 requires one additional cable and the 11 /34 requires two additional cables.
o
A

PDP-11/04 (Maintenance Mode Cabling)
|
The 11/04 requires only one additional cable for maintenance mode operation. This
10-conductor
ccable (Part No. 70-11411-1D-0) connects J2 of the M7859 to the unmarked male connector
on the
M7263 (11/04 CPU). The cable (70-11411-1D-0) has a pointer on each end to indicate pin 1
as shown
in Figure 9-3. Install the cable with the pointer
on the end of the cable lined up with pin 1 on the CPU
module (M7263). Pin 1 on M7263 is called out on Figure 9-1. Points on J2 (M7859)
and the cable
should also be lined up.
o
|
.
T
e
PDP-11/34 (Maintenance Mode Cabling)
|
|
N
The 11/34 requires two additional cables for maintenance
mode operation. Both cables are the same
and are the same part as is used on the 11/04. See Figure 9-3 for part number.
~

NOTE

~ Maintenance cables for both 11/04 and 11/34 are all
45.7 cm (18 inch) long, 10-conductor cables.

When installing maintenance cables connect J2 (M7859) to J1 (M7266) and J3 (M7859)
to J2 (M7266).
The pointers on the cable and board must be matched at both ends of the cables.
|

APPENDIX A

’

‘IJ

./ ’\

~. K

KYll-LB MICRO-CODE LISTINGS

A-l

KYLILE FROGRAM

RT-11 MACKD YUMOR-10

sMACROS

&YllLB FROGRAM

»KYilLBhPRQGRfiH

000000

5}
&y

000000

‘

8008

QO L1325 PFAGE 7

RT-11 MACRO WMOZ-10

00813325 FAGE 8

REGO=0

REG] =1,

QOQO0R

RE G2

OO0003

OO0004

QOO0

QDOOO3

OOOO0Y

RERBE=3

000004

OOOA0Y

NUMO=NUMOX

QOGA03

NUME=NUM2
X

HO0A0]

QU400

OO0

1.8

QOO402

NUM4=NUMAX

Y
6

DL B

STARTS

KRBT

BEGING

LHI

240

00001

O5 &

OOODR

,
ObE

Q0004

020
JME

013

QOO

OO0
104

o001l

00,

OO0

000

3100013
(4
&

G0Nl 4

D00

00015

00016
00017

RéaM

(40

AND

SET

SFRESET

ENARLE

ADURESS

7727970

MALT.

FOINT

DISFLAYED

RAM.

QVER

LET 0

SZERD REGISTER F.

SZERD

§ZERD

ZR0

ool

MEMORY

LOCATION

(RAMY

FOINTED

|
REGISTERS

FPOFECREMENT

SUUME

UNTIL

061,

JES

BEGL

BACK

RAM

ALl

ZERQDED.

120

QOO

016
GO0

D002

106

OO0

ODORE

000

KYLLLE

.
BEGL

DOORD

36 00023

(2000

FROGRAMMED

304

00020
OOOR0

FOINT

OVER

00013

Q0017

JME BEGIN

SO001D

30 00010

00014,

104

QOOV0E

10,

00005

OC01LS

OFLAG

SN
LLT

00003

OTD

2800003

SFRESET

OO0

’

SINITIALIZE

015

D000

NLIM
S = MU M5 X

DI
B

OOOO00

00000
QOOO0

NUMZ=NUM3EX

GOo001

R0
JTITLE KYLILE FROGRAM

Q00001

FAGE

CASECT

000000

W/vsr74

RT-11 MACRO UMOZ2-10

1.2

FOR

QOILAI2E PAGE 1

FROGRAM

DIGEFL:

RT-11

DAl DIsPLs

MACRD

YMO2-10

SOALL DISFLAY SUBRRDUTINE (STAYS IN DISPLAY SURROUTINE

RTRE

FAGE

A-2

g AN

‘

000246
QOO24

SLIMTIL

KEYSEY

QO30

200

DLSFLS:

305

SUTHBFLAY

OO0

SFOR

D002

(44
200

0004

DOOE

1,50

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05
000

040
150

D043

00094

00045

05 &,

D004

(340

OO0

SIFOBIT

REGS

POTHERWISE

P18

JdTE

NXET

LHI

SO0

DO0E ],

.//—‘\\\

BIT

PREVENT

MASEK

FROGRAM

BETING

SET. (KY11-LE

FURTHER

SERVICTING

'
FL NETE

THE

MALT

SERVICE

~
ROUTTNE,

CONTINUE

FMAGK

OFF

200

Ple

THIE

PREEN

THE

WITH

DISFLAY

ROUTINE.

WHEN

SET

THE

BIT

& & A% A DISFLAY DIGTT COUNTER,
KEYSERUICE FLAG STORED IN REGISTER.

INOTCATES

Lal

PERESET

DUT

121

GPRESET
|
FOUTFUTS

REGO

)

00065

STILL

|
REGISTER

THE

ZERD

FRRESET

MEMORY

QO31AL2Y FAGE 84

[

;

MACRO UMOR-10

KEY

HAY

DEFRESSED,

WITH

ZERD,

USED

A%
A&

.
&

TURN

OFF

THE

OTSELAY
.

RT-11

|
&

LLT

066

THAT

SERVICED

DISF2T

KYL1LLE FROGRAM

BUSY

(0044

00065

FOR

PLOAD

01
DO

MHaLT

BUSY

QOO

00064

AND

BUSY)
.,

QOCESE

TEST

MalT

SOTHERWISE

340

HEOO006D

58000457

FLAG

THE

FGJLMEP

50005

GOOA

NOT

QO ¥

BIT.

FOR

BUS

304

044

G005

SET

OO0

G005

INTO

CHECK

ASSERTING

SOLEAR

»
KT S

026
Q04

QCCURS,

ROUTINE,

HALT

010

Q0052

HALT

IME

JHEHLTE

5 4

NOT

104

QOOEE

00054

s HALT
.

SOF

5X0005

PROGRAM

0007
D004

,
REGISTER

00042
D042

SERVICE

FROGRAMMED

NXT

113

0000

Q0041

SUBROUTINE,

HJTE

00037

{344

SUBROUTINE

0054

QOO A0

200

5
s

|
H

PLOAD
:

GOO37
48

0008

DEFRESSED

DISFLAY

’

0003

eJLMFTO O KEY

00031

REY

FROM

1 QA

QOORAZ
3%

yRETURNSG

A-3

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|

STRORE

BIT.

Q0084

Q00 .

sTO PICK UP THE CDNTENTS OF THE FIRST LOCATION IN RaAaM.

000647
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044

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007

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ourT

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sOUTFUT

Q0074

L.y

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sTO

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106

Q0103

O0LO4

Q00

THE KEYFAD

CONTENTS OF

AND

ROTATE

LEFT

SET

TURN
ON THE

DIGIT.

Cal.

SHEFTL

FOUBROUTINE

WHICH

WILL

SHIFT

THE

DIFLAY

DATA

SFOSTTLONS
.

SON
302

00106

Q74

00LOY7

00l

STE

00110

00110
GO111

1350
137

00112

Q00

DISP4%

QO113

00113

004

00114

001

00116
113

SOIGIT

RBEING

SINFUT

ROUTINE

SIF LAST DIGIT

SOTHERWISE.
Al

SURBROUTINE»

AND

CHECK

FOR

LOAD
A

LAST

DISFLAYED.

I8 BEING DISPLAYED JUMP OVER KEYFAD

(CONTAINING

©)

QO117

Q44

Q0120

Q17

QOL21

s AREA

s INFUT

THE

RAM.

COLUMM

FROM

THE

KEYFAD

s MASK FOR 3IGNIFIGQNT BITS.,

OOL1L7

00121

WITH

SHIFT

360

0116

RETURN FROM

AND LOAD MEMORY FOINTER TO FOINT TUVKEYPQD TriaGE

00115
Q0115

COLUMN OF

SLOAD REGISTER B WITH A 3 TO FABS TO THE SHIFT

QOLOY

8é

FPARTICULAR

LATER.

LBl

QO10&

THE

BADK

016
Q03

QOLO2

QOLOG

READ

330

AND

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.

ALSD SELECT

SGET

RILG

Q0102

7é

RAM.

002

00100
00100

303

QQ077
ROOYY

THE

LOCATION

STO TURN ON THE FROPER DIGIT OF THE DISFLAY.THIS
sWILL

Q0074

BITS

THE LOWEST

FIRST

OUT REGO

&
VOO

THE

SLOAD THE 0 REGISTER INTOQ A REGISTER aND QUTFUT

Q0074

00075
QOO7%

303

CONTENTS

OFF

NDOT

123

00073

THE

307

Q0070

sGET

DSR4

SOHECK FOR NO KEYS UEFRESSED OTEHERWISE

150

Q0122

13é

Q0123

QOO

Q0124

Q024
257
RYLLLE FROGRAM
RT=11

MACRD

SCOMPARE

UMO2-10

AGATNST

THE

CONTENTS

THE

RAMIKEYFAD

IMAGE)

0013125 FAGE 8+

A-4

/M\

00125

JTZ

Q0125

89
Y0

Q0126

132

QOLA7
Q0130

000

00130

040

Q0131

00131
00133

040

QOL3Z
00133

040

00133
00134

113

00134

044

Q01 3%

0Ly

001364
001364

370

NIGH32

00137
Q&4 00140

00140

110

00141
00142

Q00

STARLE,

TNUREMENTED

FINFUT

NDE

yMASK

THE
FOR

ONE

IF THERE

COLUMN
OF

KEYFAD

STGNIFICANT

RBITS.

AGALIN

MATCH.,

AND

DTSFA4%52

FNECREMENT

THE

DISPLAY

COUNTER

JEE

FIF NOT

DONE JUMF BACK AND

Q0143

004
016194

v IF o oALL

DIGITS

Q0L 4%
o
L

ouT

REGO

sREEN

AND

DISFLAY NEXT UIGLT.

REAXy

HAVE

LOAD

BEEN

DISFLAYED

WITH

R
'3

AND

KEYFAD

ZERD

aND

HAS

OUTFUT

AR
N

T
0146
Qlé

0147

V04

SHE
T

0150
21351

S35

0152

Q00

106

0153

L.ty

TURN

DISFLAY

OFF.

JLOAD REGISTER B WITH & & TO BE FASSED TO THE SHIFT

LRI

0146

102

FRE
KEYS

103
B

FRUBROUTINE.

SIXK MORE SHIFTS ARE NECESSARY TO

FFINTSH SHIFTING AN

18 BIT NUMBER

(SIX DIGITS)

s THROUGH

MEMORY

RaM

PUET

CONTENTS

THE

BITS

OF
OF

THE
E

aND

WORDS)
.

CHECRK

0183
Q154

Q154

200
.....

0185

104

1A
D156

107

143

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Q&

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A04

10%

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Q1 &4

Q1 éd

074
0l

110

KYLLLE

s LF O ONLY

v IFONO

ARRV

KEYSERVICE

KEYS

ARE

FLAG

KEYS

ARE

SET

(KEY

ND LONGER

)

UMOE-10

TRUE

RETURN

QOTLII2E

PaGE

A-5

REYSERVICE

DEFRESSED

FROGRAM

DEPRESSED

OTHERWISEy CHECK

s 0L

QL &a&

vl ad

DTGP

DEPRESSED)

L16

QL &S
Jr—

KEYFAD

sSTORE IN KEYFAD IMAGE AREA UF‘RQM’FUR NEXT TIME.

QLEO

105

THE

SDOES NOT MATCH THE RAM CONTENTS.

INF

194

THAT

0G144
001 4%

CHECK

NIGF4%

00143

100

sT0

$INGREMHNT‘REGI$TER EBY THREE IF THE KEY I8 HEPRESSEHo

7 00137

NISF3

150

FROM

FOR

AND

DISFLAY

ARE

FLAG

A 2

CLEARED,

STARLE)

SUBROUTING
70

SERVICE

111

0147

CRL

"""

074

170

D17

113 el
0172

104

0173

031

0174

olele

SIEY

BT O

0175

0l
é

KEYSEVE

0176

Q00

122

123

OROR

003

0204

OFR

125

0204
0R20%

0R05

140

0206

344

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010

021

140

O21R

205

0213
0214

DL0

0314

032

128
129

130

0216

o217

0L0

131

327

022y

135

.
TO

INDICATE

MEMORY

FOINTER

FEET

THE

FAREA
OF

DISEAD

SOOLUMN
|

THAT

KEY

HAS

THE

BEEN

SERVICED.

KEYFAL

’

ITMAGE

AREAS,

FIRST

COLUMN

RAM.

ROTATE

THE

INTQ

KEYS

FROM

THE

KEYFAD

VALUE
OF

THE

FIRST

IMAGE

THE

CARRY

THAT

KEY

BIT

AND

JUMF

THE

KEY

JTE

LADY

THAT

SERVICE

o
»

CRAR

FROUTINE

FROTATE

FOR

THE

VALUE

THE

BIT

THE

NEXT KEY

SET.

AND

OTHERWISE

S50

UNTIL

|
-

Rak

JTC

L8R

UETHE

|
WHOLE

COLUMM

HAS

BEEN

CHECKED
.,

CLRL

Q010

QR4

04H0

0RR5

307

0226

OR26

032

|
CIN
B

FROGRAM

BAFTER

PMEMORY

WHOLE

COLUMN

FOINTER

AND

HAS
GET

BEEN
THE

CHECKED
VALUES

INCREMENT
THE

THE

COLUMN

|
RAR

s OF

KEYS

FROM

THE

KEYFRAD

THE

SAME

MANNER
.

0R27

KYL1LE

JTE

ORRR

133

|
FLAG

140

0224

TO ZERD.

SHEET

0221

132

ASS0CTATED

Q032

OR23

134

0220
QR20

KEYS

0215
140

RAR

0R15

MODE

0210

CONSOLE

KEYSERVICE

0210

FUNCTION

KEY.

s
PEET

124

0211

0203

307

127

|
LLT

V&b
&

0203

126

200

THE

0R0otL
0ROl

LET
046
200

EACH

S RESET

0127
0L
0200

LRI

DECODES

FARTICULAR

5 W TTH

0175

ROUTINE .

ROUTINE

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RT-11 MACRO UMOZ~10

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00113125 PAGE 8+

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15380,

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TEXTvTEXTmMHOOfifivTEXT
X

A-32

APPENDIX B

IC DESCRIPTIONS

B-1

BINARY COUNTER
RO (1)

R3(1)

los

— il

—q{T

—qT

—

—qT
-

R2(1)

12
J

RIC1)

CLR
Ly

7493

CLKBC

CLKO

LOGIC

DIAGRAM

|03

R3_(1 ) —

R2(1) P—
03

R1(1) o

CLR

.02

12
RO(1) p—

CLKBC

CLKO

TO1

T1‘4

VCC= PIN

GND=PIN 10

7493

TRUTH TABLE

(SEE NOTES)

OUTPUT.

CLKBC

INPUT

)

ol1]1}|o0

PULSE | ..

(O]

0
1

0]
|

Notes:

;

1. Truth table applies when 7493 is used as 4-bit ripple — through counter.

2. OQutput RO(1) connected to input CLKO.

3. To reset all outputs to logical 0 both pins 02 and

O:=LOW

(]

1= HIGH

03 inputs must be high.

Either (or both) reset inputs Rg(1) (pins 02 and 03)

must be low to count.

IC-7493

B-2

8641 QUAD BUS TRANSCEIVER
|
|
The 8641 consists of four identical receiver/drivers and a smgle enablmg gate in one package for
interfacing with the PDP-11 Unibus. The transceiver drivers are enabled when ENABLE A and

ENABLE B are both low. The other input of each driveris connected to the data to be sent to the
Unibus. For example, when enabled, DATA IN 1 (pin 2) is read to the Unibus via BUS 1 (pin 1).
Durmg a write operation, data comes from the Unibus as BUS 1 (pm 1) andis passed through the
receiver to the device as DATA OUT 1 (pin 3).
-

BUS 1——

DATA IN-1 —2——
DATA OUT1 ——
- BUS 23—

DATA IN2 ——
DATAOUT
2 ——
ENABLE A ——

BUS 4
DATA IN 4

—opataouT 4

- sear

BUS 3
DATAIN3
DATA OUT 3

GROUND——]

ENABLE B

[—

ENABLE A—

1
BUS

DATAQUT1

ENABLE B

IC -8641

74154 4-LINE TO 16-LINE DECODER
The 74154 4-Line to 16-Line Decoder decodes four binary- coded 1nputs into one of 16 mutuallyexclusive outputs when both strobe inputs (G1 and G2) are low. The decoding functionis performed
by using the four input lines to address the output line, passmg data from one of the strobe 1nputs w1th

74154

D2
D1

16 OUTPUTS

1 OF 16 MUTUALLY

EXCLUSIVE OUTPUTS
DECODED FROM BCD INPUT
WHEN BOTH STB1 AND
STBO ARE LOW
|

-—h

—.

BCD
INPUT
FOR DECODING

A32335333

fi3

f15
BRET:

the other strobe mput low. When elther strobe mput is hlgh all outputs are high.

STB1

~STBO

+5V= PIN 24
GND=PIN 12

Notes For Demuitiplexing:
-

Inputs used to address output line.

Data passed from one strobe input

" with other strobe held low. Either
strobe high gives all high outputs.
IC-74154

74175

QUAD STORAGE REGISTER

TRUTH

TABLE

INPU

OUTPUTS

th+1

R(1)R(O)

H
L

L
H

th =Bit time before

clock pulse.
th+1=Bit time after

clock

pulse.

R3(1) 15+

R3(0) 14
10

~<1p2

DO o—

R2(0) 11

DATAJ
74175

CLEAR

RO(1) |2
RO(0)

CLR

(2)

CLK (o)—>°

R1(1)
“R1(O)

RO}

(1)
R

POUTPUTS

D10

CLK

R1l

(7)

(1)

INPUTS

(4)

R2(1) —

CLK (0)f—=
CLEAR

(12)

D2
o

(10)

(1)

CLK

R2
0)—=

CLEAR

(9)

CLOCK o—
—

CLEAR

()

D3
Q

03<§J3)

CLK

R3]

(15)

(1)
R3
(0)}—o°

CLEAR

Pin (16)= V¢, Pin (8)=GND
IC-74175

Reader’s Comments
KY11-LB Programmer’s Console/Interface
Module Operation and Maintenance Manual

EK-KY 1LB-MM-001

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