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EK-KXT11-UG-PR1

November 1981

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Document:	M8063 Falcon SBC-11/21 Single-Board Computer User's Guide
Order Number:	EK-KXT11-UG
Revision:	PR1
Pages:	355
Original Filename:

OCR Text

M8063 Falcon
SBC-11/21
Single-Board

Computer

User’s Guide

PRELIMINARY

Prepared by Educational Services
of

Digital Equipment Corporation

1st Preliminary, November 1981
2nd Preliminary, December 1981

The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any

errors which may appear in this manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation:

DIGITAL

TOPS-20

MASSBUS

DEC

DECsystem-10

OMNIBUS

0S/8

PDP

DECSYSTEM-20

DECUS

DIBOL

UNIBUS

RSTS

EDUSYSTEM

RSX

DECnet

VAX

TOPS-10

IAS

VYMS

MINC-11

4/82-14

o
M
«Q
®

CONTENTS

b NN
S

PROMS/EPROMS..................................2-17

RAMS ¢ ¢ cooooooccssesscsessoessscssossssssassscssesel—ll

SELECTING BACKPLANES AND OPTIONS.ceecscccccccssses2—20

el
POWER SUPPLY eeoececsccsccsscscsosscscssssssssasssssscsss2l
2l
ssssesl
sscscssssss
csssssscscs
eeeesoscocc
.
EXTERNAL CABLES
Parallel I/0 Interface (J3)eeeeccocsonsoccsccssesl2=2l
Serial Line Interfaces (J1 and J2) eceecesccesesel—23

|]
[J
N =

VERIFYING OPERATION ¢ e eeocoocooseosssssesccsosssssocsel20

Macro—ODT OpPtiONeeceececececscasosscscssccssssscasel2=26

Loopback CONNECLOLSeseeecocsccsssssssssscscsssesel—26

Verification ProceduUrCeceesecccsccssssscscccscocscsssl—26

GENERAL.......Q........................‘0000000000003—
SUPPORTED OPTIONS. ® © 0 0 060 0 0 0 0 600 6 5 00 0 06 060 00 00 0 LN 3—
UNSUPPORTED OPTIONS. ® © © 0 0 0 0 5 0 006 0 0 5 060 00 060 060 0 06 0 0 0 0 0 0 3—
4

OPTIONS

MACRO-ODT
4_

INSTALLATION AND CONFIGURATION..cceoescsosccoscsessd—
ENTRY CONDITIONS..........0.......000000000000000004—
Macro-ODT Input Sequence.........................4—

iii

N
NN
=

o
o

Memory MAPSeeeoceccsoscssscscscsnssscsssscsssossesesl l]

MEMOY 1€ S ceeoocsscsoooesssosscoscssssssssssscssssssssel—l3

GENERAL.................‘.O............‘.....l....
*

NN
ol e | | t 1
WO O
- -

»
o
o

o
o

W
-

Parallel I/O0ceecccecsccscccscscssoscssscsccccsscsscocscs
Serial I/0cececccccccscsssoscscscscssosscsssscsscsscsscssse

INtErrUPtSeeecescscssessososcssccscscscscsscoscsanssses

NNe
¢ e

FEATURES.:ccececoscscccccccccs

Wake Up Circuiteceeccececcccsccoccccccssccsccncns
Starting AdAreSSeececececccccsoccccsosccssscsscocssscnse

NN Ndoauoib
W
-

OPERATIONAL

BaCKkUPeecesoosoosooscoccsssscccscscscccccccce

Battery

[]
[]
[]

INSTALLATION

SELECTING

[]

UM B DBWNHFERFHFRFRRFRRPFRRREFREO

o
o
o
e

GENERAL...........................................

CHAPTER

RELATED HARDWARE MANUALS.ceccscosessccccscsscscssosel=

CHAPTER
wWww

INTRODUCTION

1SPECIFICATIONS ceceeecccccscoscosscsccscsnscscscsscscscssscccscsse
1PhySiCaAlececececcccsscoscsccsccssscccssccccscscscccsscsns
1Power RequirementS.ccceccoscccccccsscccsccccccsccce
1BUuS LoA@dinNgeeccececcecocscsocssscsccscssscccosccccsscscss
1~
Environmental.eceeccecococccscscscsscssosscsscosccsscscsscsce
1BACKPLANE PIN UTILIZATION.:cccsosocccccccosccsccscscscscoe

CHAPTER
NN NNNNNMNDNDNDNONNNDNNDNDNNNNDNDNDNDNON

GENERAL.............Q...................O.........

¢
®

WNE

= e

CHAPTER

/(ASCII

Carriage

<LF>

(ASCII

12)

Line

RetUINeeeececeecccoooccees 4—Feed.oeeeoeccoecconcoccsssssess 4~

(ASCII

122)

(ASCII

123)

(ASCII

107)

(ASCII

Designator....... 4-—
Word..eeeeeoeecooees 4 GOeaeoeosooococcccncsscsssccsaceccsss 4-

120)

Proceed..ceeececececcecssccccsasoecss 4~

DX,

(ASCII

Internal

Processor

StatusS

BOOtLStIAPSeeeeeccococosssensaceccconeaes 4~

130)

DiagnoSticCS..eeecececseccccccncocsas 4 -

Error
ODT

AND

PROGRAMMING

HINTS . eeeeoeccocoscoccocsese 44—

DeCOdiNg.ceeeecesceccecccsccccsccoscsncccsss 4~

Stack

Warningeeeeeeeeececescecccosccccooccocceso 4 -

Addresses

to AVOid.eseececocoecscoccccnsaocconacscsses 4—
Priorityeeeeeeeecseseecceeoocsecccncsocoscsassss 4 Terminal Related ProblemS..c.ceeececcsncecccoasessd—1

CPU

SPUrioUS HALTS:eeeeeaeocessocsconcocncosscsanssead=10
Serial I/0 ProtoCOl.ceiceescecccecocsessecsecsnacesed=10
Interrupt

ARCHI.TECTU
e v ceocecencoocco
RE.
scssesse

(DIRECT

ACCESS) ceceeceeeccccsccccssacees

UP/DOWN

PROGRAMMING

FACILITY .escececcocoscscocccocnscssaes

INFORMATION

GENERAL ¢ eeveeoeoocooscseacsasssoscssscoescscscscsososscscssaes
»

ASYNCHRONOUS
Data

Baud

How

U WN
-

Modes

NNNDNDDNDND
-

o
o
o
o

LINE

UNITS e:eeceooccccacocecess

InterruptS.eeceeeeeeacscecesscscsossecsscosoncsoccoscss

PROGRAMMING

SERIAL

RaAteS..eeeeeececsccccscsccccscsccccncoceses

THE

Use
of

PARALLEL

This

Section

I/0

INTERFACE.
. eeececcosces

The

Manual....cceeee.b

WO W

POWER

MEMORY

ORGA
. e NIZA
eeeccccecccscscsccosonosnccs
TION
saes

OperatioN.eccececcececcccesscscssscsccsssbd—

©C O

DMA

MEMORY

StacCK.ieeeeeecosceooecscocccsccoconssnsossso
INterrUPtS .t ceeeecsoscscscccscsccscsccconcsosccoscees

Hardware

RegisSterS..cseencocecscsccscoccccccococsss
RegisSter.icicesecosceecccccccccccccconoas

Status

General

[]

REgiSterS.eeeeeceeeseeesccococococooooocascssaccess
[]

[]
[]
[]
[]
WN

MICROPROCESSOR

GENERAL........00.......0..00....I....0.........0.‘

uvruonuugt
[
NSO
N

ARCHITECTURE

OVOYOY
OV OV
|

SYSTEM

InitializatioN.eeeecececccaceeead—10

Vector

—

o
o
o
s
o
®
s

Odoud
WwWwN +—

o
o
&

L
o

T
e

R
¢
¢
e

[

[]
[)
[ ] [)
L
[]
[]
[}
[}
B WNHHEHRPFRHO

Loty
n

o
o
o
e
e
s

15)

WARNINGS

NNNNNDNDNDNNDEHEEFEEFEO

S1laSh.eeeeeceocsosoccsccscasscaccess 4 -

(ASCII

INI T IALIZATION . ceeeooceascsescecsssscssosanscscscscesss 4-

CHAPTER

057)

<CR>

DD,

CHAPTER

)N le) ) le) e We) We) W) Mo W e We)

Output SeqUENCEe...ceeeecccccccscccccces 4-—
COMMANDS . ¢ ceeeaocssoscocsoscccccccscccssss 4-

CLOLVWVOVWVOWOWOU-INAAOO
S D WN N

OCOJOULTdWN
-

O
¢
¢

SO N
O
O
I
S
O

WWWWWWWWWWN

= Y -N L Y

Macro—ODT

MACRO=ODT

Port

RegiSteresceeeeeccccescsccccsosccccccconocssebdb=10

Mode
Port

0
A

Basic
and B

Input/OUtpPUt..cecececcceccoscoseesab=10
RegiSterS.iceceeecsccccocccccccseesab—10

Mode

(Strobed

Input/OUtpUt) ceeeeesccececneeesb—14

Parallel I/O HandshaKinNg...eceeeeeoeosocsscooscsssea0=27

.l1.5.
.l.

WK
-

o
&

1
1

«2

2.1

Direct AdAresSsSinNgececececcsoccescscsscsccsscscsccsccccce
Register ModE.eeeececeoocssosscscscccscscccccnccces
Autoincrement MoOdE€.ceeeoeceocccsscccocccccsccccnse

Autodecrement Mode (Mode 4).ececccscccccccccsel
Index Mode (MOdEe 6)cecececccccssssossocsosanesel=1ll
Deferred (Indirect) AddressinNg..cecececceccecessl/=13
Use of the PC as a General Register..eececececeseel/=17
Trmediate MOdC..eeececececssosscsscsscsccsccsesl/—18
Absolute AdAressSing..ccececesccscsccscscccscssel/—19
I

D W
-

&
&

o
o

&
o

o
¢

1
1

Single Operand AddresSinNgececcecsccccccosccccccs
Double Operand AddresSingececeececccescccccccccnss

NN NN
=
|
|
1
oAU
WH ==

1
1

ADDRESSING MODES AND INSTRUCTION SET
GENERAL :veoeeocccossososessssscssscsscsssssosscsscccococsocoe
ADDRESSING MODES . ececseceeccccscscssscscscccscsoscscscscccccce

o
o

Parallel I/0 InitializatioNeececeseeseccoccseessb=27

Setting Bits in Port Coeeescconocsossscnscssessb—25

NN
N

YA
YO O

0
fa s}
¢

NN NN NNN N NN NNSNNNNNNNNNNENNSENEYENYNNNEN
NN NN NNN

Mode 2 (Strobed Bidirectional I/0).ccececsecsecs6-14
Control Word Register...........................6-21
Mode SeleCtiONeecescocsooscsscssscssscccscssesdb—25

Relative AdAresSiNg.ceeeccecccscscsessscscssccsssel—21
Relative Deferred Addressing..ceecececccccceecesl/=22
Use of Stack Pointer as General Register........7-22

INSTRUCTION SET eeececcsesossesoscososscsssesssssensssel=23
INStruction FOrMAtS.eeeceececcccssesscsoacccccosesl—24

Byte INSELUCLIiONSeeeeeoecocescsosssssccscesnsssl=26

.2.1.1
2.2
2.3
.2.3.1
e2.3.2
e2.3.3
.2.3.4
2.4
.2.4.1
.2.4.2

PS Word Operators.............................7—41
Double Operand INStrucCtionNS.ceecececccccccccsesssl/—42
GENEYAleeeeoosocececcccsscscsssossnsscscsccsscscacel=42
Logical.......................................7—46

e2.5
.2.5.1

BranNChESeeeeecscocsesscessscssssssssossccssecssnscessl—49

e2.5.2
e2.5.3

.2.5.4
«2.5.5
.2.5.6
e2.5.7
.2.5.8
«.2.5.9
.2.5.1

List of INStruCtioNS.cecececsccecsscsscscccccscssl/—27

Single Operand INStrUCtioNS.eeeecccscoscosoccocosssl=29
GeNETraleeceoseessoseccssssssossscsssessscencoses/—29

ShiftS & ROLALESeeeeseocecccscscscsscscssssssssl—33

Multiple PrecisSioN.ceesceceececcecscssccsccsss/—38

Program Control INStruCtionNS.eeecececsosssosesss/—49

Signed Conditional BranCheS..ceececcccscccessssssl/—54

/=57
Unsigned Conditional BrancheS....ccceeeocecese

Jump & Subroutine INStructionNS.ceecececcosscscesl/—59
Traps.........................................7—64

/=68
Reserved Instruction TrapS..ccceccscccecsseccscecs

Halt INterrUPteecececcecsccsscssccscscccccscccscess/—08

Trace Trap....................................7—68
/=69
Power Failure INterrupt.cecececcceccscssecscccccssess
69
......7—
........
........
........
ts......
Interrup

7.2.5.11
7.2.6

Special Cases T_bit....bo.t.......O...000.00007_69
Miscellaneous INSErU
. ... eeeeeeooo
CEI
oonneaaal
ONS
=T0

Condition

and

R/—=
. eeeeoceccacc
WLB)
oses
and SEL]l) ceeeecsocess
Bus Clear
(BCLR) ceceooccococccccssoccsccccncses
CloCk OUL (COUT) eeeeecoccocceasacooceccooccnsssse
MiCcroprocessor TranSaCtioNS..ceeeeececcoccoscscsss
FetCh/ReaAd. s ceeeeeeeceooeocooasoscoeoccocsesss
Flags

(SELO

write..................Q..........C...........

S
UU
OO

o
o

&
o
o

| e

(R/-WHB

Output

Read/Write

Select

Address Strobe (CAS) eeeeceeescsscoscccses
Priofity IN (PIl)eecececeoossosscccsscscccccnssnss

Column

SignalS...eeesecesccceses

(RAS) ceeeeecsoccsoccocscoessse

Control

Strobe

Address

IAK...........................l.........'il....8
DMA.................0......0.............0.... 8
ASPI...0.0....0.....0....................000008—12

[]

[]
o
&
9o
o
@
e

N
WN e
AU
WN -

e
s

=
*
»

Row

[[

)y Sy Wy

UpPeeeeeeeensosccnscoseecososcosccoocnsnccses
INPUL.eeteseetaeecececocceossocscsasoansescs
INPUL ... eeeaceceoeecseecossoscecccsscsssseses

POWEY

DS DD

&
8

InitializatioN.eeeeeeeeeococeoees

RESET...............O..0.....0.........0.......

&
o

RIUTUTO

¢
o
o

°«

Microprocessor

MODE

NOP......................O..0000000000000000008—12
REGISTER

CONTROL.:seeeeccocccocococsacooooseeeB8—13
CONTROL.:oeeecetecasscecccconssoooansnseeeld—15

INTERRUPT
OdOhUId
WK =

o
s

MICROPROCESSOR...QOO....0..0.....‘.................

o6
e

OPERATION

e e

&
e

Microprocessor

o
o
o
o
o
o
o

THEORY

CloCK
Ready

HRFOONAOAUBWWWWWWWWWNHRR el

OpPeratorS..ceeeeececcecoososocssssl—71

GENERAL...........I............QQ..................

e e

GO 00 GO 00 00 00 OO 0O CO 0O CO CO 00 0O 0O 0O GO 0O OO 0O OO 00 GO 0O GO 0O GO Q0 0 OO0 00 OO OO0 A0 00 OO OO 00 00 00 00 00

CHAPTER

Code

00 0O 00O 0O CO COOCO COOD OO CO 0O OO OO OO OO

T7e2.7

Details

Interrupt

Control LOGiC...eeeescoeees8=17
READY ¢t eeeececescoeoacoscsccssccscsscosocscscsocssonnssad—19
IAK

DATA

HALT

POWEYr

IN
(IAKDIN) teeeeoeseosoceososcccnanonseses8=21
Interruptee.sccecceesccccececessccccccccnsssad—21

Fall.e.eeieuwseeoseeoosesecocancssconsncccseseB=24
LOCAleeeeeeeensonsosoossssoseccososcecononsssocesossssl—24
ExXternal..eeeeeenecessoseececosceesoosssasnccncessB=25

DMA

DCO04

Interrupt.ecceaceeescsessececscccscccccoccccoceeald=25
PROTOCOL.cteosesoncocscoosecccssoccssaescaceeB=25

ADDRESS

MEMORY

RAM

LATCH:eeeeoeooovesssssasccsscccoscsscsnseeed—26

ADDRESS

DECODE..ceeescececcooscsosocccccccsseel8=26
MEMORY .. eoeeeeoocoscsscccccoccscccccsocnssssssssd—206

ROM/RAM
SERIAL

MEMORY

LINE

PARALLEL

TI/0

SOCKETS . eeeeeecoocoscnccscsocscseesB=27

INTERFACE

UNITS..eeeeeooasssosocaccoeeeB=29
INTERFACE. . ceeceeccececesssnscocsssessB8=31

.11

POWER

.12

CLOCK: e oeoeeeeccssessessoesscssnsosasscaccaossesscesssB8=34

.13
.14

UPuceeeoceaocesosocsosesoscsscseccosncsossncanscssal—33

CLOCK CONTROL.::¢teoeeceeeocesnssssasscsssccsossanssessB—35
D
< T ¥

POYNC e e ooooossssssssesssssoscssssssssssscsssssseessd—38

8.15

READ/WRITE........................................8—39
REPLY TIMEOUT .o eceeoocecocsssossscscccsccssncssssssd4dl
BUS CONTROL.......................................8—42

8.16
8.17

LSI-11

SBC-11/21 SINGLE BOARD COMPUTER ¢ ccoocococonsnsoscsed 2

MASTER/SLAVE RELATIONSHIP :eeeooocossccssssossssssesesd2

DATA TRANSFER BUS CYCLES .eeeoeosossoscsccsscsossscsscsscssd—d

Bus Cycle ProOtO0COl.eecesececccscscsscssossssssosssesd—d

[

INTERRUPTSo.......................................9—12
DevVice PrioritVe.eeeeescescccsssscscscscsccsssncssssd—l3
Interrupt ProOtOCOleeeessesessoscssssssnssscssseseld—l3l
CONTROL FUNCTIONS . eeoeseacsssococsscsssssossssoscssssed—ld
HAlt e oo vocecooecscesccooasssssnsssssssscssscncssdI—]lb
INitia1iZatioNeeeeeesescessscsssossasescacsscasesd—lb
POWEY StALUS.eeesoccosssoscocsscscsssnsssssssccnessI—lb
Power-Up/Down Proto0COleeececseseccccsscsscsscccsscoeesl=1l0

[)
N

[4
LJ

Direct Memory ACCESSeenoscscoccssssssssssnsssssed—ll

[}
[
N

[

[]

Device Addressing.........;....................9 5

[ ) []
L] [ ]
S W

®
[]
[
[]
[]

BUS

GENERAL............................................9 1

[)

NSO
oid s b WWWwWwNE
O

WWOWOWWOWOWYWWOWOYOWWYWWOLY
WYY VYWY

CHAPTER

LSI-11 BUS ELECTRICAL CHARACTERISTICS ceeeoscoseoseesd—1l7

MODULE CONTACT FINGER IDENTIFICATION.ceeceoossnsesI—17

APPENDIX
APPENDIX
APPENDIX

APPENDIX

PROGRAMMING DIFFERENCE LIST

INSTRUCTION TIMING

SOFTWARE DEVELOPMENT

APPENDIX

MACRO-ODT

ROM

SBC~11/21

SCHEMATICS

vii

FIGURES

Title
KXT11-AA (M8063)
SBC=11/21 Module
Interrupt

During

Parallel

I/0

Socket

Interrupt

Acknowledge...2-

MEMOXY

MaAPSeeeeeesccecssccsocsssesccosocsssssascsnnceel=17

Parallel

Serial

BC20N-05

"Null

BC21B-05

Modem

and

I/O

Line

CONNECLOr.ceeecsecoosoocsansael=22
Unit

Modem"

CONNECLOreeeeeseccoccccees2—24

Cable...ceeceececccsescscecsel2=25

Cable.ieceeeescccccescccooonssanees2—25

Processor

Status

Line
Line

Parallel

I/O

Parallel

I/O

Unit
Unit

Interface (SLU) ...ececcecococccssoccessb=2
Register Bit MapPS...eeoecececcccncas 6-4

Interface............O................ 6-9
Flowchart

Mode

Port

Mode
Mode
Mode

0
1

Port
Port

C
C

Bit
Bit

Port

Mode
Mode

Input

Strobed

Mode

Output

Data

Mode

Strobed

Bit
Data

Guide..eeeeeeceeesococaceeneeb—l 1

Bit

AssignmentS....c.ceeeeeeeeeb6—12
AssignmentS...ecececcecscsccccseceeb=13
AssignmentS.....ccccecececcececesab—14

ASSignmMeNntS.ceeeceecececccsccccoseesb—22
Handshaking Sequence.....cecee...6-28

Input

Timinge.eceeeeecececescceccccssssb6—28

Handshaking

Sequence...........6-29
TiminNg.cceeeececececocscceccessasasb6=30
Output Timing....cceceeesees.6-30

Mode

Port

Output
Strobed

Mode

Port

Bidirectional

Timinge.....ceeeececeeea6-32
AddresSSing.ciceececececenccccccccceces
AdAresSSinNg.cseeeccccceccccoccocccsnsss
RegiSter.icieeesessseseceococscossscnscscnscas

Operand
Operand

O
2

Mode

AutoincCrement..ccecenceoccoscoscescoocsccccsscces

MOde

Autod
.. ceecescocccccsooco
ecrem
snocsocscnocscsss
ent
INAECXeeceeeeaooessssoooscccssosoooscosscnccccsaoses

INC

ADD

InCrementeceeeecceccseesvecococcscocscocsococcacocccsss

R2,

Add.eceeceescecsssonccscsaccsscscacsoscnsscsonscesa

COMB R4 Complement Byte€...ceoecececcscecccscssscsccseses
CLR (R5)+ Clea@r.ececcscccsceccccccsscsoscsocscncocsscscsscssse
CLRB

(R5)+

Clea@r

Byt€.c.eoeeceeeoscocososcssssscccses

Mode
Mode

Single
Double

Word....eceeeeocessesasd=2

MaAPSeeeeeecceccssscasnsoscsassoacscsscsccsscncscnassd—b

[

Pin
Pin

CWWVWOIYAULUNd
W

30
10

T
|
|
O

I
D
NN
i
I
[

Bus

Sets A and B InterconnectioN.eceecececesescececsee2—15
Configuration.ciececececsecccecccccsconccesal—l6

Serial
Serial

LSI-11

ConfiguratioNieceeeceececeescceccenoceeel=l

Memory

MEMOrY

SBC-11/23 ModUlE€..eeeeeoscocoococasol—
LayOUl.eeeeeeeeoooasacacsccccocseelm
ConfigurationS.eeeeeeceecececcescscccccccessl

Time-out

Registers

N NNNNNNNNN

Page
WO ON W

No.

= HHEOONdOUMBWNEFEFHFEHERMRRMY
® NOUMBWNRFNEMEEE
OO NIAAUTD WN BW
N
O
W N
O
= O

Figure

ADD

(R2)+

INC

—(RO)

Increment.cececccceccccccococcssoscoccosal—l

INCB

- (RO)

7-15
7-16

ADD

—(R3),

CLR

200

7-17

COMB

200

AAQd..cecececoccscoccosccsccocssacsocnncssees

Increment

(R4)

(R1l)

Byt€eeeeeeocsocoocossosscsseel—10
Add.eceececcecoeccocscoscosocsscsscosel—ll

ClEaA@reccscscecsccccsscscoccsoncnocscscacel—l2

Complement

viii

Byt€...ceeseeeesccsccececsl—12

7-19

7-20
7-21
7-22
7-23

7-24

ADD 30 (R2, 20 (R5) AGd . eeeeevesosossocsssccsasessl=13
—14
Mode 1 Register Deferredececeecececscsssssossnsscsel
/—14
scsel
ssasc
ececc
eeses
Mode 3 Autoincrement Deferredee
4
Mode 5 Autodecrement Deferred.eeeeeecscecscscscscasacel—1
~1lD
ssnssl
sassna
ascsso
cosses
Mode 7 Index DEferred.eeeececss
CLR

INC

7-25

COM

7-26
7-27

ADD

7-28
7-29
7-30
7-31
7-32
7-33

7-34
7-35

7-36
7-37
7-38
7-39
7-40
7-41
7-42
7-43
7-44
7-45
7-46
7-47
7-48
7-49
7-50
7-51
7-52

7-53
7-54

ADD
CLR
ADD

P EOHEDO®
D

7-18

RS ClEaF.eeoceeasocsosascsssssssosssosssssnssesl/~1D

(R2)+ Increment................;.,..........7—16
- (RO) Complement.................a..........7—l6
100 (R2), R1 AAA . e eecensasonascanssoansoessasl=l?

10, RO Add. e eececocoescseccsssssscsosnsesasel—19

# 1100 ClEal.eceocesesessosscccssssscssscssesl—20
# 2000 Add.eeceececcccccccssosssssnscscsccssssl=20
Increment...................................7-21

INC
A ClEACeceeeeesesssososcsasssscssssocscsscsnsl=22
CLR
Single Operand Group..............................7—24
Double Operand Group..............................7—24
Program Control Group BranCh..eeececoccnoscsccccssl—24
Program Control Group JSReeeseosoccssssnosssocseneel—24

Program Control Group (RTS) cevseecocssacasesscssasel=25
Program Control Group TraAPSeeeecescsssscssoscsassasel =25
Program Control Group SUDEIrACt.eeseeesccascsocsnsel=23

Operate Group.....................................7-25
Condition Group...................................7—25
Byte INSErUCEIONS ceeesosseacescscsscsssacsnssnsscssel=20
........ 7-29

CLR....'O..................O.Q............

COM. v e evecenceassscsssessesesscsssssssssssssnesacsseel=30

........ 7-31

INC.......................................

DEC e e oo eocesceoseasosssssessscscsscssssscasscsssscsesl=3]

......l. 7-32

NEG......Q......C.........................

TS T . oo v eeeeooecaoassssssssscscssessssssosnssnssscssssl=33
ASR...............................................7—34
ASR Description...................................7—34
ASL...............................................7—34

ASL Description...................................7—35

ROR.e @ v oeeoseeccssssasssessssssssssssssscssosnssssesl=35
ROR Description...................................7—36
ROLi s o e v eeoeoeccccoasseessasnsassesssascsssssecsnssssl=30

7-55

ROL Description...................................7—37

7-56
7-57

Multiple Precision...O....O..................0....7—38

7-58
7-59

SBCeeosooscssocsosnsssosssassscsassssscsscssssescsel—40

7-60

7-61
7-62
7-63
7-64
7-65

7-66

SINAB . o e e eeveccccassaseaseacssccsssscssoscsssscsnsscsl=37

ADC.................O.............................7—39
SX T eeeonasosocosasescsocscscscssssscssssscssssscssssesl—40
MEPS e eeeescoossoasosssossssconsscsscsssossncssasacsesl—4l
—42
MTPS e eeeeesocesassosocsscssoscsssasssocscscssnnccssl
MOV . « e eooceocanscsosscsscscscssssscsesasssccscsncsscesl/—42

CMP e e eeeocosoosasesancsccssssanssasssossascscascsscesl—44
ADD . ceeoecocsosesocsccsssssssssssscscsscccsnsossesel/—44

SUB......Cl.........0..O...........................7—45

R
Jy

BIC.......................................

........7—47
U
¥ XOR e e tteteoneeeecetooenscenosanosascnasoc
nsnasensT—48
S N

BNE.....................fi................
.........7—51
o
28 |
BPL.......................................
........7-52
BMI.....................«...................._...
.7—52
BV C e et teteeoeoecosnscecosneconssseccosecas
eanenesdsT=53
BVS..........................................u...
.7—53
O
Y-

BCS..........................................,....7—54
N,
29
BLT.......................................
...o....7—56
L .
-~
BLE..........................................o..
..7—57
BHI e e sttteneeoeeesossecoenecescosececcasecsesse
cesad=57
BLOS......................................
...a....7—57
BHIS......................................
........7—58
L U
iy
L
T T S T
P '
JO R e e ettt eneeeoeesesosececesasoscsesocscocececsneal
—60
JOR EXaAMPlE s eeeteeteetecescacecoancnccccon
cnsenessT=62
S
' &
RTS EXaMPle..eeeeeesseosecccecesonncoecc
oceceneeesT=63
L
EMT.......................................
........7-64

EMT EXAMPle..eeceeecoesessoscecocsoscencsacccsacnesl
—65
RAP e e tteteeoeeeeosessseseecacsessossocsccecnens
ssdsl~66
R,
iy
LR
-2,
T T S T NP
L, |
T R
JU 3
HALT..............................................7—70
WAIT......................................
........7—70
S S R,
§ |

Condition
SBC-11/21

........7-71
OpPeratOrS.eceeeeeeseescccsseseccnsesl=71
Functional Block Diagrame..ceeeeecececess.8-2

Code

oo oo

SBC=11/2] MiCrOPrOCESSOr.eeeeseescsessscncsocecesessB8-4
Fetch/Read TransSacCtioN..eeeeneeeseesececocoeseneeas
8
Write TranSACEioN.ceeeceeeesnseesescncecaccacoseses
9
IACK

DMA

ASPI
BUS

Mode

TransSaAcCtioN.eeeesssecoesosecececcoossscccssocssss8—1
0
TransacCtioN.e..ceeeeecsccecesoesscsascscsonseaesal8—11
I

H OO NoOUTId
WN

00 CO 00 0O CO CO 0O 00 00 OO
L
L
L
L N
A
O
A

MFPT......................................

TransSacCtioN.ceieeeeceeeececeosesceosccsonsseeaB=12

NOP

TransacCtioNeseecesscecececcessecosceccccccssaB8~13

SBC=11/21

CoONtrol.s.eeeceesessesesceccccscceesaB8=14

Interrupt

LOGiC.eeeeeeesescocsesassseseseB=16

8-11
8-12

8-13
8-14
8-15
8-16

8-17
8-18
8-19
8-20
8-21
8-22

HFHERPROYONOUD
WN N O

0OQOQOO00000Q0

W WY LWWYWWYWILWWYWIWYWOo B

WO WNDEFENDNDNDND
N O,
b

8-23

Interrupt CONELOLeeeeeceoncoaoocooasessnscsssssenased=l?

Ready.............................................8—20

IAKDIN............................................8—22
HALT Interrupt....................................8—23
Memory Maps.......................................8—27
RAM Memory........................................8—28
ROM/RAM Memory SOCKEES e eseoeoseccsssscsssssscsesssd=29

Serial Line Interface UnitS.ceecscecsscsccccscesesa8-30
Parallel I/0 INterfacC@.ceeecececscscscsscssceassccsssssd=32
Power Up..........................................8—33
ClOCK . eeoeosoeosoososossssssscsscsssssosnssssssssssed33D
ClOCK CONEYOleveeessococecsoscsssssssossssscssnsessed—36

DMA...............................................8—37

TOSYNC e oo oeosoaososesesssssssssscsssessssssososssesd—39

REAA/WritCeeoessoosoeacecccscosossasssssnssssscsssssead3—40
Reply TiMEOUL eseeoeocoossscsosssssssssossssoscscsesed 4l
BUS CONLILOLleeeeocoooseoceaocacssssascsacsscsscsscsesd=d2
DATI BUS CYCl@euveecocesssosssoscasssosscccscsasascsssed=bd
DATI Bus Cycle TiMinNgeceeeeocoscsssccscnscccssccsss)=8
DATO or DATOB BUS CYClEeeceeeeeococscsssccsscssnesnesI=9
DATO or DATOB Bus Cycle Timing..esecccescecsscesssd—10
DMA ProtOCOl.cecececececscssssssssossssesessossssseal—l2
DMA Request/Grant Timing.eeeeeeesceeccccccscccesssd=l3
Interrupt Request/Acknowledge SequUeNCe......ess.s.9-14

Power-Up/Power-Down Timing..eeeecoccecescccsccecesd=l?

Double-Height Module Contact Finger

IdentifiCatioNeeeeeseseeecesesccsscssssasacsscssesd—l8

Overview of Software Development.cessssoeccoccsssesC—4d

Application OvervieW.csesseseecesoocccscsssssssssssC=?
MONitor ProgramM.e.cececscscscssscscsesccscscsscssossescessC—8
Load Map..........................................C—lO

Power Up TASKeeoosoosooooosossossscessssssssvcscsssssssssC—1l0
Power Fail RECOVEIY.eeeoescsossossssosesossssssseesC—10
SLU Diagnostic TasSK.eeeoeossoossoocsscscscoescssssesasasC—ll
RAM Diagnostic TaSKeeesseoeocoesosscososcsscsesssesCml2
ROM DiagnosticC TaSKeeoeeoosoososscseccssoscsccssnseesslC—l2

Parallel I/0 Diagnostic TasSKeeeeeseoseososscaoscsesaC—1l3

CONtrol TaSKeeeeeoesoossocsosssossssssoscscsossssssccesC—ld
Power Fail TaSK.eeeoeoeooocccsossscssscssssscossesslC—1d
TABLES

{
W N

N NN

Page

SBC-11/21 Module Backplane Pin Utilization....c¢cceelConfiguration Pin DefinitionS.cecececccccccccsccscsl
Standard

Factory ConfigurationN.iceeecececescceccccccns

Mode Register ConfiguratioN..cecesececcscecccccccnns

Oo~Jwu

Title

Table No.

Configuration
Configuration

(Strobed

Mode

Buffer

Configuration

and

Jumper

Connection

Memory

Map

and BREAK RESPONSEC.eveeoscoccesssl2—1l4d
ConfigurationS..esceeceeceescencscsscccceeel2=lb

Configuration

for

EPROM/PROM..ccceoes2-18

Configuration

for

Socket

Set

Configuration

for

Socket

Set

Configuration

EPROM/PROM. .eeeees.2-19
RAM....eeeeececceese2=20

for

RAM....ceecececceceosee2=20

Diagnostic

Slew

Rate

Fault

Unsupported
Macro—ODT

Macro-ODT

ResSisStor

VAlueS...eeeeeseeocecccesee2=23

INAiCaAtorS..eeeeeecscocooscccssessl—28

LSI-1]1

OptioNnS.ceeeeceeecescececccscccsssses3=b

COMMANAS . ceeecesocosscosscccscccscscscsssss

States

and

Valid

Processor

Status

Word

Bit

PSW

LevVelS.i.eeeescosceeceacoscscascccccanscsses
INterrUPtS.eceeeecceceoccocssssoossosansses

InNterrupt

SBC=11/2]

Serial

Line

Unit

Receiver

Control

Receiver

Data

and

Transmitter

Control
Data

AddreSSeS.eeececcoceecoeeeass
Bit DescriptionS.......
DesScCriptionNS.eeeeecesecess.

Bit
and

Status

Buffer

Bit

Parallel

Mode

Bit Description.....
DescriptionS.eeceseceee.

I/0 Register AdAresSSeS..ceeceececccenccsccsss
ConfiguratioN.ceececsececeeeeosconcoseccaneeesb=l

Mode

Port

Mode

Port

Bit

Port

Control

Bit DescriptionS...ceeeceeceeees.6-12
DeSCriptionNS..eeeceececccccenceesb-13

Signals

Mode

Combinations
1
1

Port
Mode

Mode

Control
Control
1

Mode

l....cceecececsceeab—1b

of Mode l..ieiececeeecceesecoccnncnsansasb=16
Port C Bit DesCriptionS....ceecceccsccscosceeab=17
ConfigurationN.eeeececceececccocensscncaneesab=21
Control

Port

Signals

Mode

2...ccececcccensssab=22

Bit

DesSCriptionS...ecececeececccncseesb—-23
ConfiguratioN..iceeeecececeeseececccscscnosnssssb—24
Register

Words

Mode

for

Interrupt

Mode

CharacterSeceeeee.

Status

Buffer

Transmitter

Input

DescriptionS...cecececesces

O\G\O\O\O\OINU'IU'IU'be
I
N
|
N
T

Set

NONdAOAUVUWHEID
WU W

A
Y
A
(R

TR T

[

HEOWONOOUD

I/0)...¢e....2-13
Handshake€....e.....2-14

Set

Mode
Mode

RWNHDWN-

Handshake)..eeeeoo2-12

Socket

Control

OWOWWYWWYWoO®
WO

(No

Socket

.Y IV} NNDODNNDNDNDNDNDNON
N
R R
T
T
A
A
B

IO TR B
O

Buffer
Buffer

0
1

EIA

WNFWNHN -

122Ne) Re) ie) ey BEe) o) Bie)We ) le ) We )Mo ) WS, I, WS, I N

Mode
Mode

Bit

Set/Reset

Input

Selection

Mode

Bit Functions.....6-24
SelectioN...ceecesceccnsceesb—25

Set/Reset
Control

Bit

FunctionS.o.....6-26

WordS....ceeeeececosesab—26

Handshaking

SignalS...ceecececccccoceeb6-27
Handshaking SignalS....cceeececcoeess6—29
Bidirectional Handshaking SignalS......e...6-31

Output

Start

Address ConfigurationNS....ccececececececsccsneeeoaB8—15
Designated INterrUPtS.eeeeeeeceeaceecsocesecsceascesss8—18

Serial

PPI

Signal
Data

Line

Unit

Addressable

RegisSterS..c.eeceeeeesoocessseasssad=31

RegisterS.i.i.eeeceecececececcsssccccoesalB=32

AsSsignmentS..eecececcececccccccccaccascesesad=3

Transfer

Bus

Signals

Bus

OperationS...ececceccecccocccscccccesasdI—4

Used

in Data Transfer Operations.......9-4
IdentifierS..ciccecececcceccccscocccacenenead=10

xii

PREFACE

This

manual

provides

the

described

with

user

system architecture and
configuration,
programming information for the SBC-11/21.
The configuration requirements are described
in Chapter 2 and the system architecture is
The programming
presented in Chapter 5.
techniques

are

Chapter

and

the instruction set is listed in Chapter 7.
The operational theory 1is presented in
Chapter 8 and the schematics are in Appendix
E. The Macro-ODT option is described in
Chapter 4 and the 1listing is in Appendix D.

Options for use on the LSI-11 bus are listed
in Chapter 3 and the module bus requirements
An example of
are described in Chapter 9.

software development is covered by Appendix
Appendix A summarizes the instruction
C.
timing and Appendix B compares the SBC-11/21
to other LSI-11 microprocessors.

NOTE

This

in Figure

1-1.

manual

used

only

for

the

SBC-11/21 module, M8063 Revision C. This
revision can be identified by the circuit
board $#501448C 1located on the module as
described

CHAPTER

INTRODUCTION
GENERAL

1.0

as the
system

in Figure 1-1

is shown

module

(M8063)

The KXT11-AA

and designated

SBC-11/21 single board computer. It is a complete computer
on an 8.5 X 5.2 inch printed circuit board that executes

(see Appendix B). The
the well known PDP-11 instruction set
for up to 32 Kb of
sockets
SBC-11/21 module contains 4 Kb of RAM,

PROM or additional RAM, two serial I/O lines, 24 lines of parallel
I/0 and a 50 Hz, 60 Hz or 800 Hz real time clock. In addition, the
SBC-11/21 is equipped with a complete LSI-11 bus interface which
enables it to communicate with most of DIGITAL's large family of
as described in the Microcomputer
(see Chapter 3)
modules
Interfaces and Microcomputers and Memories handbooks.
features the following:

The SBC-11/21

A powerful processor running the PDP-11 instruction set.

Direct
bytes

words,

16-bit

32K,

addressing
(K

8-bit

64K

1024).

Efficient processing of 8-bit characters without the need

On-board 4K bytes of static

Sockets for up to 32K bytes of PROM, jumper configurable
for a wide range of memory types from several vendors.

rotate,

swap or mask,

Additional RAM can also be

Hardware

memory

subroutines,

Direct-memory
in

and

the bus

Eight

read/write memory.

installed

for

stack

in these sockets.

structured

handling

data,

interrupts.

access

for

high-data-rate

devices

inherent

architecture.

general-purpose

registers

data
storage,
pointers
dedicated: SP and PC.

and

that

are

available

accumulators;

Fast
on-board
bus
for
high
memory access is not required.

LSI-11
bus
structure
that
provides
position-dependent
priority as peripheral device interfaces are connected to

Fast

I/0

when

for
are

the

throughput

two

external

bus.

interrupt

powerful

response without device

and

convenient

set

polling.

programming

instructions.
o

Two

serial

I/O0
interfaces,
compatible
with
EIA
RS-232C
RS-423,
with
software
programmable
baud
rates
range of 300 to 38,400 baud.

and
EIA
over the
o

One

parallel

I/O

input/output

and

one

with

two

8-bit

control

Real-time clock which can be
Hz

interface,

ports,

Many

800

bidirectional

set by the

user

50 Hz,

Hz.

jumper-configurable

operating

different

memory

restart

address,

real-time

clock

frequency.

Optional

PROM

resident

maps,

modes,

exception

parallel

1/0

including

handling,

1.1

four

start

and

configurations,

and

Macro-ODT

containing

diagnostics, bootstrap programs for mass storage
(TU58, RX02 and RX02), console communications and
debugging facility.

The

8-bit

port.

module
devices
on-1line

SPECIFICATIONS
SBC-11/21

1.1.1

module

specifications

described

below:

Physical

Height

13.2

(5.2

in)

22.8

(8.9

1in)

Width

1.27

(0.5

in)

Weight

360

Length

(includes

1.1.2

are

module

handle)

Power

Requirements

Power

Supply:

+5.0

+12.0

(12

oz)

2.5

(Typical)

2.8

(Maximum)

(typical)

max

used

on-board

circuitry
1.1

(Maximum)

supplied
to
through pin 10

includes

connector

Battery

+5.0

V +

Backup:

170

(Typical)

260

(Maximum)

1-2

current

outside
world
of the serial I/0

NOTE:

REVISION STATUS LOCATION

ON SOLDER SiDE OF BOARD

d TMo O OO0 L TM L L -

ono

T o w U ouo T oo adu0 0 - - S " N L BN T 000 O uUo

b ¢

q b

g
b

MR 71798

x4 ol

KXT11-AA (M8063) SBC-11/21 Module

NOTE

The

+12.0

typical

current is measured
with
no
connections
at
pin
10
of
the
serial I/0 connectors (fused line).

1.1.4

Bus

Loads

A.C,

D.C.

1.1.3

Environmental

Temperature:

Storage
Operating

-40° to 850 C (540 to 1(5)0o F)
52 to 60°
C (417
to 140~
F)
NOTE

The

Relative

module

must

brought

operating

temperature

allowed

stabilize

into

the

environment

and

before

operating.

Storage

10%

90%

(no

Operating

condensation)

10%

90%

(no

condensation)

Humidity:

Altitude:
Storage

(50,000

Operating

ft)

(50,000

ft)

(90

mercury

minimum)

NOTE

Dera%g the maéimum operating temperature
by 1TM
C
(1.8
F)
for
each
300 m
(1000
ft) of altitude above 2.4 Km (8000 ft).

Environment:

Air

must

Airflow:

(operating)

Adequate

airflow

temperature

F),

airflow

temperature

rise

must

across

60°

must

rise

provided

the

(140°

across

These

non-caustic.

module

the

For

(9°

operation

1limit

the

the module

10°

inlet

when

design

temperature

limits

inlet

(18

the

life

limits.
will

the

outlet

the

maximum.

Lower

serve

product.

below 55°

NOTE

are

increase

limit

5°

F).

provided

inlet

(131°

outlet

1.2
BACKPLANE PIN UTILIZATION
Backplane pin connections for the
Table

1-1.

The

names

unique

bus
the

the

also

SBC-11/21

includes

SBC-11/21

module

and

module

are

utilization

list

listed

and

signal

standard

LSI-11

backplane names associated with each pin. Note that although
signal names may differ, the module is completely LSI-11 bus

compatible,
not

table

with

performed

are

unique

not

used

the

Table

the

exception

the

SBC-11/21.

the

LSI-11

bus

refresh

Signals
bus.

STOP

These

transaction
L,

SRUN

are

TTL

1-1

Side

SBC-11/21

Module

(Component

Side)

Backplane

SBC-11/21
Signal Function

LSI-11
Signal

Bus
Name

AAl

Bus

terminator

BIRQS5

AB1
AC1
AD1

Bus
Bus
Bus

terminator
terminator
terminator

BIRQ6 L
BDAL16 L
BDAL17 L

AE1l

STOP

AF1

SRUN

AH1

Not

SSPARE1
SSPARE?2

connected

SSPARE3

connected

MSPAREA
MSPAREA

AJl

GND

Not
GND

GND

AM1
AN1

GND
BDMR

AP1

BHALT

AR1

Bus

GND
BDMR

terminator

BHALT

BREF

AS1

Not connected

+12B

AT1

GND

AUl
AV1

Not connected
+5 VB (battery)

+5B

BAl

BDCOK

BB1

BPOK

BC1

Bus

terminator

BD1

Bus

terminator

SSPARES

BE1l

Bus

terminator

SSPARE®6

terminator

BF1

Bus

BH1

START

BJ1
BK1

GND
Not

BL1

BSACK
Bus

BR1

BEVNT

Not

terminator

BS1

BV1

SSPARE7
SSPARES

MSPAREB

BP1

Not

SSPARE4

MSPAREB

BM1

GND

H
H

connected

BN1

BT1

BPOK

connected

Not
GND

BU1l

H
H

PSPARE1l

connected

BSACK

BIRQ7

BEVNT

+12B
GND

connected
V

PSPARE?2
+5

START

signals

Utilization

Backplane
Pin

AK1
ALl

and

level

SBC-11/21.

(BREF),

Table

1-1

SBC-11/21 Module Backplane Pin Utilization

Side

1.3
The

(Solder

(Cont)

Side)

Backplane

SBC-11/21

LSI-11

Signal

Signal Name

AA2
AB2
AC2

+5 V
Not connected
GND

GND

AD2
AE?2

+12 V
BDOUT

AF2

BRPLY

Function

AH?2

BDIN

AJ2

BSYNC

AK?2
AL?2
AM2
AN?2
AP2
AR2

BWTBT L
BIRQ4 L
Not connected
BIAKO L
BBS7 L
Not connected

+5 V
-12 V

BDIN
L

Bus

BSYNC

BWTBT L
BIRQ4 L
BIRKI L
BIAKO L
BBS7 L
BDMGI L

AS2

BDMGO

AT2

BINIT

AU2
AV 2

BDALO
BDAL1

L
L

BDALO
BDAL1

L
L

BA?2

BB2

Not

BC2

GND

BD2

+12

BE2
BF2

BDAL2
BDAL3

connected

-12

GND
V

+12

L
L

BDAL2
BDAL3

L
L

BH2

BDAL4

BJ2

BDALS

BK2
BL2

BDAL6
BDAL7

L
L

BDAL6
BDAL7

L
L

BM2

BDALS8

BDAL8

BN 2

BDALY9

BP2

BDAL10

BR2

BDAL11l

BDAL1l]1l

BS2

BDALl12

BDAL12

BT2

BDAL13

BU2

BDALl14

BDALl1l4

BV2

BDAL1S

BDAL1S5

RELATED HARDWARE MANUALS
primary reference document for

considgrable
compatible

amount

useful

products

may

the SBC-11/21 is this volume. A
information about other LSI-11 bus

found

the

following

publications.

Document No.

Title

Microcomputers and Memories Handbook, 1981 Edition
Microcomputer Interfaces Handbook, 1980 Edition
PDP-11 Bus Handbook, 1979 Edition
These documents can be ordered from:
Digital Equipment Corporation
444 Whitney

Northboro,

St.

01532

Attention: Printing and Circulation
Mail Station NR-2/W3

EB-18451-20
EB-20175-20
EB-17525-20

CHAPTER 2
INSTALLATION

GENERAL

ter

The installation procedure for the SBC-11/21 single-board compu
2.0

module must include the following.

is best
It
configuration

NOTE

to 1leave the factory
undisturbed until module

performance has been verified.

Install jumpers to select operational features.

Select and mount an LSI-11 bus-structured backplane and

Select and connect an appropriate power supply.

add any required LSI-1l1 bus options.

Provide appropriate cables to connect external devices to

Verify operation of the module.

the serial and parallel I/O interfaces.

These items are discussed in detail in this chapter.
2.1

SELECTING OPERATIONAL FEATURES

the users to configure the
The module has 66 wirewrap pins for neces
to meet their
module for the operating modesed by sary
r
eithe installing or
requirements. This 1is accomplish
The locations and
pins.
rap
removing jumper wires between the wirew
shown in Figure
are
pins
numerical identification of the wirewrapions
d in Table
liste
are
2-1. The wirewrap pins and theirrt.funct
res are
featu
table
selec
The
2-1, by the features they suppo
lel
Paral
,
rupts
Inter
ss,
Addre
ing
Battery Backup, Power Up, Start
Detailed requirements for each of.
1/0 Buffering and Memory maps. ibed
in the following paragraphs
these configurations are descr
The standard factory configuration is described in Table 2-2.
p

Battery Backu
2.1.1
to maintain a +5 Vdc
The user can select the Battery Backup mode
if desired, to the
and,
RAM
c
stati
battery supply to the 4KB of
socket set A. The +5 Vdc
two 28-pin sockets that are designated as
1 bus via pin AV1 and
battery supply is provided through the LSI-1
This supply is connected to
a maximum of 260 mA is required.
p of 4KB of static RAM,
wirewrap pin M3. To enable battery backu
ll a Jjumper
remove the Jjumper wire between M1l and M2, and insta
A, remove
set
t
socke
wire between M3 and M2. To provide backup for
r wire
Jjumpe
a
ll
insta
and
the Jjumper wire between M4 and Ml,
between M2 and M4.

me4 M62

|_opooomsg

M65 |~ A

M63 ’14 E69

}

amM31t

E55

am30

—~—

(2]

[ J1]

E43

E67

M230M28

PROGRAMMABLE

PERIPHERAL

M22 | Bvoe

M25

Im21] | @

INTERFACE

o——M19
ami1s

SERIAL LINE UNIT NO. 2

—
R2
OM16

E65

—

SERIAL LINE UNIT NO. 1

||
oMmi15

E64

] R1

MICROPROCESSOR

— o mia

o o M2

M13

E62
HIGH BYTE

E48
LOW BYTE
SOCKET SET B

SOCKET SET B

E61

HIGH BYTE
SOCKET SET A

M11
.
o—— M10

E47
LOW BYTE

SOCKET SET A

DOooOMS

M490 O M48

?MSIMG

omss

M45

M47 ——0 0 —— M46
oo

M9 M7

M44

M4300 M42
M57 —O0-M56
M41
oo
M40
na
M54
M39——poOo——M38
M53—Oom52
M37aoM36
M51-M-5—0—g
(=] TM
M35

M55

E59

aM32

levl

e i

M40

M3oDOM1
B

MR-6691

Figure 2-1

SBC-11/21 Module Layout

Table 2-1
Pin

Configuration Pin Definitions
Description

Function

Battery Backup
V power

System +5

+5 Vdc power distribution to support

Battery backup +5 V power source

static

Socket

RAM

set A,

high

26,

and

low

byte.

Nonmaskable
and Trap to

Interrupt
the Restart

Address

level

+5 Vdc voltage

~-CTMER interrupt request input (edge

Timeout error

-CTMER interrupt enable

Interrupt Acknowledge

M10

System GND

M1l

High logic level

sensitive)

output

(TMER)

(-IAK)

output

(+3 Vdc)

Serial Line Unit #1
M12

System GND

M13

Transmit

M14

Serial

transceiver

M1l6

Line

BHALT

unit

Break

line
Detect,

Interrupt request output

Power
M15

side

System +5 V power,

diode,

cathode side.

wake up circuit

Wake up circuit diode, anode side.

Table

2-1

Configuration

Function

Serial

Definitions

(Cont)

Description

Line

Unit

M17

Transmit

side

BEVNT

transceiver

M18

real

time

clock

output

M19

real

time

clock

output

M20

800
Memory

Map

real

time

clock

High

M22

M23
M24

Start

Address

(Mode

logic

level

(43

map

select

(LSB)

Memory

map

select

(MSB)

System

GND

Start

address

control

M26

Start

address

control

M27

Start

address

control

M28

High

M29
M30

logic

level

(+3

side

vdc)

Interrupt

maskable)
System GND

Recelive

transceiver

M31

vdc)

Memory

M25

(Level

output

Decoder

M21

BHALT

line

BHALT
interrupt
sensitive)

request

BHALT

input

line

(edge

Table

Function

2-1

Configuration

Definitions

(Cont)

Description

Memory

M32

Address

M33

High

M34

Socket

set

high

byte,

M35

ggcket

set

high

and

M36

line

logic

level,

for

PROMs
pin

low

byte,

Socket set A, high and low byte, pin
20

M37

Socket set B, high byte, pin 23

M38

Socket set B, high and low byte, pin
20

M39

Socket set B, high byte, pin 22

M40

Socket set B,

M41

Socket set A, low byte, pin 22

M42

Socket set B, low byte, pin 23

M43

Socket set A, low byte, pin 23

M4 4

gocket set A, high and low byte, pin

M45

gocket Set B, high and low byte, pin

M46

Address line 13

M47

Socket Set B Chip Select

M48

Socket Set A, high and low byte, pin

M49

Address line 12

M50

System GND

M51

Read Strobe (-Read)

M52

Write low byte strobe (-WLB)

low byte, pin 22

(—CSKTB)

Table

2-1

Confiquration

Function

Definitions

(Cont)

Description

M53

Static

RAM

high

byte

Output

Enable

RAM

1low

byte

Output

Enable

strobe

(-WHB)

(OE)
M54

Static

(OE)
M55

High

M56

Socket

set

M57

Socket

set

high

byte,

and

M58

byte

Socket

byte,

Parallel

write

set

Chip

Select

(-CSKTA)
pin

high

22
and

1low

Input/Output

M59

Port

M60

System GND

M61

Port

buffered

output,

M6 2

Port

buffered

output,

M6 3

Port C PC4

output

(8255A-5

13)

M64

Port

output

(8255A-5

11)

M65

High

logic

M66

Port

Buffer

PC6

direction

level

buffer

(+3

control

Vvdc)

direction

control

2.1.2
Wake Up Circuit
The module has an on-board power wake up circuit designed
to be
used in systems without the LSI-11 bus power sequencing protocol.
This circuit holds the BDCOK line negated until one second after
+5 V power is applied. When the module is being used in an LSI-11
backplane, which has a power sequencing
routine,
the module wake
up

circuit

jumper

wire

using

power

note

that

supplies

must

disabled.

between

M15

supplies
the

have

This

M16.

without

module

and

rise

power

requires

time

The
the

less

accomplished

installing

jumper

removed

The

user

wire

sequencing.
+5

Vdc

than

and

ms.

+12

Vdc

when

should
power

Table

2-2

Standard

Factory Configuration

Function

Jumpers

Standard

(No

LSI-11

Bus

Power

Battery Backup)

Wake

up Circuit

Start

Address*

Start

Enabled
.

address

M1l

and

M1l

and M4

jumpers

M25

and

M26

and

M24

M27

and

M28

Memory Map O

M22
M23

and
and

M23
M24

2K X 8

M34

address

10004

Between

M26

Restart

10000

Installed

Memories:

INTEL EPROM

M41
M56
M51
M32

and M43

and

M34

and
and
and

M57
M36
M57

and

M58

M37 and M42
M5 and M37
M41 and M39
M47 and M38
M51 and M40
Interrupts:

Timeout traps to restart address
except during LSI-11 bus IAK.

M9 and M8
M7 and M6

SLU#1 Break asserts BHALT and BHALT
is received as level 7 interrupt

M1l3 and M1l4
M30 and M31

(vector

140)

SLU#2 60

Hz Real Time Clock

asserts

LSI-11

BEVNT

Parallel

I/0

Mode

Port A Receive data,
on PC4
Port B Tranhsmit data

Connection

with

STROBEA

M59

and

M60

M65
M61

and
and

M66
M63

pins

M3, M10, M11, M12, M15, M1l6, M18,
mM20, M21, M33, M35, M44, M45, M46,
M49, M50, M52, M53, M54, M55,
M62,

M19 and M17

M64

M48,

*Before using with Macro-ODT the start address must be changed to
172000, as described

in Table 2-3.

2.1.3

Starting

Address

The starting address for the microprocessor is selected by the
user via wire wrap pins. When the module is powered up, the
microprocessor loads this value into R7 (program counter) as the
first fetch address. The wirewrap pins are M24, M25, MZG, M27, and
M28, defined in Table 2-1. The user has eight stértlng addresses

available to choose from. Table 2-3 lists the available addresses
and the jumper connections required for each address. The restart
address
1is always the start address
incremented by four.
The

wirewrap pin

locations are
Table

2-3

shown

Mode

in Figure

2-1.

Configuration

Start

Restart

Connect

Address

M27

M26

M25

000000

000004

M28

M24

M28

010000%*

010004

M28

M24

020000

020004

M24

M28

040000

040004

M24

M28

M24

100000
140000

100004
140004

M24
M24

M24

172000

172004

M28

173000

173004

M28

M24

M28

*Factory

setting.
The
start
address
should
be
selected
1in
conjunction with the memory map configuration.
Figure 2-6 shows
how the available start addresses fit into the memory maps.

2.1.4
Interrupts
The
SBC-11/21
implements

a
multilevel
interrupt
system
that
eleven
separate
interrupts.
A
complete
listing
of
system
interrupts
will
be
found
in
Table
5-3.
Three
of
these
interrupts, CTMER, BKRQ, and REVNT, are user-configurable by means
of jumper wires as shown in Figure 2-2 and will be discusse
d here.

consists

The

CTMER

caused

interrupt

timeout,

FETCH/READ,

WRITE,

the

that

highest

is,

level

failure

IACK

(non-maskable).
detect

transaction.

RRPLY

For

the

during

a
factory

configuration, -TAK
is connected to
the D
input of
flip-flop E4
via M9
to M8
jumper.
This
prevents
setting
that
flip-flop and
inhibits CTMER for
timeouts occurring during
IACK
transactions.
Such

a condition could only occur if the peripheral which
caused
interrupt
failed
to
return
BRPLY
during
the
vector
reading
operation.
Refer
to
Chapter
8
for
a
discussion
of
External

the

Interrupts.

help

disadvantages

the

this

jumper

takes

place

during

the

IAK

user

evaluate

option,

timeout

the

advantages

sequence

described

events

Figure

and

which

2-3.

Observe

that a timeout during IAK causes a zero vector to be read
by the microprocessor. This occurs in both cases describe
d
in
Figure
2-3.
The
difference
is
in
the
setting
of
CTMER,
which

causes

the

RESTART.

second

stacking

and

PSW,

followed

jump

+3VDC-A

+5 VDC

GND

MSéMH M10é

-lak M9

_D ---------‘ '—-— D

ONE SHOT

M14

[

M13

M12

GNo ——0
BHALT L

M30
L
GND—{]

60HZ ~———J~— -~
s
o0

‘

TEVNT |

£S5

+3VDC

o ——UMm
M19

-BCLR

M31
A

BEVNT L

SLU 2
LTC

RESET

-CTMER
: NONMASKAB
INTERRUPT LE

+3VDC

RRPLY L

T LIS P

cas |,

l"fl'\g_________ 'VE'?___ c

RRPLY LI,

TOOUT H
TDINH

D
Y

800 HZ ——1

INTERRUPT

£33 hLlli\éE(lABLE

RESET

san

E38

s .

BKRQ

E29

cas

cas] .

LEVEL®6
E27 | INTERRUPT

RESET

vEY

+3VDC - B =]

M24

GND —(]

MR-6668

Figure 2-2

Interrupt Configurations

LSI-11 BUS INTERRUPT

(BIRQ4)
PROCESSOR RETURNS IAK

M8 CONNECTED TO M9 (-IAK)

M8 CONNECTED TO M11 (+3 VDC)

TIMEOUT DURING IAK

NO CTMER

CTMER SET

PC AND PSW PUSHED ON THE STACK

PC AND PSW LOADED FROM VECTOR AND VECTOR +2

(VECTOR IS 0 BECAUSE NOTHING IS DRIVING TDAL)

PC AND PSW PUSHED ON THE STACK
PC AND PSW LOADED FROM VECTOR AND VECTOR +2

(VECTOR IS 0 BECAUSE NOTHING IS DRIVING TDAL)

JUMP TO NEW PC

NEW PC AND PSW PUSHED AGAIN
RESTART ADDRESS —+PC
340
—+PSW

JUMP TO NEW PC
MR-7202

Figure

2-3

Time-out

During

LSI-11

Bus

Interrupt

Acknowledge

The other two interrupts configurable by the user are BKRQ and
REVNT. Their vectors and priorities are described in Table 5-3.
All jumper combinations which are "electrically correct" as
described

in Figure 2-2 are legal.

Some typical configurations are described below to
user with the various combinations available.
Install

This

jumpers

between

arrangment

allows

and

M31

M8
M6

and
and

M1l
M14

M12
M17

and
and

M13
M20

the

SLU

BREAK

input

familiarize the

set

the

-CTMER

nonmaskable interrupt and trap to the restart address. The timeout

(TMER) input sets the BKRQ level 7 maskable interrupt. The BHALT L
bus signal is ignored. The SLU 2 800 Hz line time clock and the

BEVNT

L bus signal

Install

jumpers

enable

between

the REVNT

and

interrupt.

M30

M14 and M31
M8 and M1l
M13 and M1l2
M17 and M24

This arrangment allows the BHALT L bus signal to set the -CTMER
nonmaskable interrupt and trap to the restart address. The SLU 1
BREAK input sets the BKRQ level 7 maskable interrupt and only the
BEVENT L bus signal enables the REVNT interrupt.
Install

jumpers

between M7
M8

and M6
and

M1l

M14

and

M13

M30

and

M31

M17

and

M21

This arrangement allows
the
timeout
(TMER)
to
set
the -=CTMER
nonmaskable interrupt for all timeouts. The SLU 1 BREAK or the
BHALT bus signal set the BKRQ level 7 maskable interrupt and the

BEVNT L bus line
generated

is clamped low and therefore no

by BEVNT

interrupts can be

2.1.5
Parallel I/0
The
Parallel
I/0
is
implemented
with
the
8255A-5
Programmable
Peripheral Interface
(PPI)
and connects to the user's interface
through the J3 connector. Wirewrap pins used for the configuration
of the Parallel I/O are shown in Figure 2-4 and are defined in
Table
2-1.
Dash
lines
in
Figure
2-4
represent
the
factory
confiquration jumpers installed. The wirewrap pin locations are

PCO

INTERRUPTS

PC3
—

—

r_74|_3244

BUFFERS
l
N

PCO

PC1
PC2

Wl
M61

M63|
PORT
C | pc4 M63

PC5

rce M64
B

M62

3
4

ll> |

PC7

—

N
L

<l|

;

g 4

—_—

—

PORT B BUS
TRANSCEIVERS

M60

B DATA

M5b9

GND —0- - ~-O—
PORT A BUS

TRANSCEIVERS [\ ADATA
M66

NE43

R11

a2
—)—

M65

+3vpC —--- O

MR-6667

Figure

shown

Figqgure

2-4

Parallel

2-1.

The

I/0

Configuration

directions

port

and

port

transceivers are dependent upon the logic level connected to M59
and
M66.
Wirewrap pin
66
connects
to
port A through a
200
ns
minimum
rising
edge
time delay circuit.
When M65
(+3 Vdc)
Iis
Jumpered

pins

inputs
to
connectors.

and

M66,

the
Programmable
When M60 (GND) is

and

port

The

direction

Interface

M59

port

the

connector.

port

and

Peripheral
jumpered to

B buffers act as outputs
to

port

can

buffers

act

Interface
from
the
J3
pins M59 and M66, port A

from the

port

Programmable

also

Peripheral

controlled

the

user's
program.
To
make
this
possible,
M63
and
M64
must
be
jumpered to M59 and M66. Then data outputs via port C will control
the voltage levels at the direction control inputs to ports A and
B. The software required to accomplish this control is discussed
in

Chapter

Wirewrap

pins

the
user
connector

M61

and

M62

can

Jjumpered

or M64 and M62 to control the direction of
connected between M63 and M61 and between
and

PC6

M59

and

M66

allow

to control
the direction of the transceivers via J3
pins 5 and 7. When not using wirewrap pins M63 and M6l

to be

used

inputs

the

PPI

ports A and B, jumpers
M64 and M62 allow PC4

from the J3

connector.

NOTE

If pins M61, M62, M63 or M64
for
program
control
of
ports
the
the

user must ensure that the PPI
and
buffer
do
not
contend
as
driver

output

driver

output.

condition is allowed to occur,
both drivers may result.
The

are used
A
or
B,

Programmable

Peripheral

Interface

can

this

damage

function

The jumper configurations and
signals for each of these modes are shown in Tables
2-6. For programming information refer to Chapter 6.
selected

Table

software.

2-4

Mode

Buffer

Configuration

(No

three

modes

the handshake
2-4, 2-5, and

Handshake)

PPI

Act

Element

Program

Input

Output

via

Port

M66

M65

M66

M60

M66

M64

M63

Port

M59

M65

M59

M60

M59

M64

M63

Never

M64

Input

M62

Always
Never

an
an

Output
external

Output

Never

M63

Input

M61

Always
Never

an
an

Output
External

Output

PC3

Never

Input

Interrupt

(Vector 134)
Always an Output
PC2

Always

PCl

Never

Input

Always

PCO

Never

Input

Interrupt

Input

Never

Output

Output
B

(Vector 130)
Always an Output

Control
C

Table

Mode

2-5

Buffer

Configuration

(Strobed

I/0)

Act
Input

Element

To Act As
Output

Program Control
via Port C

Port

M66

M65

M66

to M60

N/A

Port

M59

M65

M59

PPI

PC7

Never

M60

M64

M63

Indicates

Input

Buffer

Full

PC6

M62

M64

Never

(Acknowledge
PC5

Never

A)*

External

Output

Indicates

Input

Buffer

Full
PC4

M61 to M63
(Strobe A)

Never

PC3

Never

Interrupt

PC2

Strobe

B
Input

PCl

Never

External

Input

Never

Buffer

Never

Serial

I/0

The
jumper
options
interrupt response
explained

tabulation

given

2.1.7

Table

Output

Input

Full

Input

receipt

relating
to
the
of the system,

Paragraph

2.1.4.

responses

Output

Interrupt B
(Vector 130)

*User's hardware acknowledgés

2.1.6

Mode

PCO

Output

Mode

Acknowledge
Output

the

For

output

by port

serial
I/0
determine
the
and have been thoroughly

the

BREAK

data

sake

detection

completeness,

the

SLUl

1is

2-7.

Memories

The memory system for the module consists of the LSI-11 bus, 4K
bytes of local RAM and four 28-pin sockets that will accept either
24-pin or 28-pin industry standard +5 V memory chips. These chips
are provided by the user and can be either EPROMs, PROMs, ROMs or
static RAM. The sockets will accept 1K X 8, 2K X 8, 4K X 8, and 8K
X 8 PROMs/EPROM or 2K X 8

static RAMs.

Table

Mode

2-6

Buffer

Configuration

and

PPI

Input

Output

Element

Signal

Port

Bidirectional

Port

Not

used

bus

Mode

If
Not

M66

used

Output

Handshake

M64

in Mode

Buffer

Never

PC6

Acknowledge

PC5

Never

PC4

Strobe

PC3

Never

PC2

Always

PC1l

Never

Input

Always

Output

PCO

Never

Input

Always

Output

Input

(if

M61

M63)

Input

Table

2-7

QOutput

Input

Buffer

Never

SLUl

Full

Output

Interrupt

Input

Never

A Full

PC7

M62

A
Output

BREAK Detection

Jumper Connection

BREAK

Ml14

M30

M13
M31

BHALT L Signal to the LSI-11 Bus
and BKRQ interrupt (vector 140)

M13

M1l2

M30
M14

to
NC

M31

Response

response

Ml14

M31

BKRQ

M13

M1l2

(no

M14

CTMER

interrupt

M13

M12

(HALT

trap)

M1l

interrupt
BHALT

(vector

140)

bus)

through

Restart

A which is
There are two socket sets, one designated as SET
B which is
SET
as
controlled by -CSKTA and the other designated
socket and
byte
high
a
of
controlled by -CSKTB. Each set consists
e 2-5.
Figur
in
shown
as
cted
a low byte socket which are interconne
Figure
in
shown
are
y
The wirewrap pins used to configure the memor
ion
gurat
confi
ry
facto
ard
stand
2-6 and described in Table 2-1. The
in
lines
dash
the
by
d
sente
repre
of the jumper wires installed is
must
user
the
ts,
socke
the
g
Figure 2-6. In addition to configurin
configure the Decode Memory Address chip to select one of the four
memory maps available.

CSKTA

M56

ADS _3

MD47

AD4 ——~1 HIGH BYTE

ap12 —0

AD3 —

Mnss

ap1 19

AD2 —|

-WHB —]

ToAL8 11|

L18 rpAL14

-READ —O

onD —H]

S, roAL1

M53

24
Ap10
L2%

7 | sockeTsETB|

L19 1pALtE

—0

M36

BYTE
AD4 —— HiGHcor
AD3 —

AD2 —

23 w37
22

—4321 M39

L1% 1paLis

AD1 10 ]

TDALS

L18 tpaLia

anp =4

15 TDAL11

M38

|17 tpaLis
L16 1pAL12

TDALY —12]
ToaL10 13

L17 1paL13
16 tpaL12

ms2 | Tpale 12
-WLB MD51 TDAL1O 3]

A +5 V

AD5 ——] 28PIN

""021 ms7

M35

L25 Ano

5
ADE ——

23 1 m3a

- Y

AD7 -

7 | sockeTsETA | 22

M49

ADS _3_

|22, AD10

ADE —]

aps —2 28 PIN

—

AD13 ME

L2245 Ao

AD7 —
5

M45

-cskTs —0

Ma4

M58

-rReaDHB —O)

‘

M54

-READLB —O)

+5 vbc —0

+5 V

M50
anp —0

+5 V

L— 45V
27

AD8 —>

|26 5y

M33

+3voc —0O

ADS ——

AD? —
5

AD9
B24 AD10

—]
AD7
—3
ADE

L——— 45V
27

AD6

AD9
—2%— ADIO

23 M42
—2-2—0

6
28 PIN
ADS ]

23 M43
-—22—0

6 28 PIN
AD5 ——{

AD2 —]
Ap1 —2

AD2 —
AD1 ——

TDALO —1—

12
L1% rpaL7
18 TDALS
_T'I_

11
TDALO -Tz—'

S
L tpAL?
18 TDALG
r—1"7—

TDAL2 =

|—— TDAL4

TDAL2 —14_

| 16 TDAL4

__7| sockeTseTA

BYTE
—1 | ow car
AD4
AD3 ——
1

7| socKkeTSETB
[ =21 O
— (oWBYTE
AD4
cas
AD3 —-

Pl
5

DALY ——]

g TDALS

TDALI —1-§—

GND —

|15, TDAL3

anD —4

o TDALS

L15 tpaLs

MR 6866

Figure 2-5

Socket Sets A and B Interconnection
NOTE

When configuring pins M32 to M58 the RAM
chips in sockets E60 and E46 must be

removed. The RAM chips are replaced into
the sockets when the configuration is

completed.

2.1.7.1 Memory Maps —-- There are four memory maps available as
shown in Figure 2-7 and the module can be configured to select one
that meets the user's requirements. Wirewrap pins M21, M22, M23,

and

M24

are

used

requirements are listed

select

the

in Table 2-8.

memory

map

and

the

Jjumper

Table

2-8

Map

Selection

Jumper

Map

W=
O

Memory

M21

Map
Map
Map

Map

M22

Configurations

Jumper

M23

M24

M21

M23

M21

PIN 21 HIGH BYTE SET
A

Ap11

M32my

PIN 21

M58

PIN 21

AD12 M494

T
}

I-——DML— PIN 23 LOWBYTE SET A
F—-OSL pIN 23 HIGH BYTE SETB
b3
2
LowBYTE SET B

————

M46

M46m

+3vDec

433

-ece 24g

!
[

PIN 2 HIGH

BYTE

EF_—{:::PHU2LOWBYTESETA
Mas

}
:

_HBCE -M33my

Maa

M33

READ-MRLp

LOW BYTE SET B

PO piN 23 HIGH BYTE SET
A

wHg 28m
wie 4520
AD13

LOW BYTE SET A

PIN 21 HIGH BYTE SET B

SET A

PIN 2 HIGH BYTE SET B

PIN 2 LOW BYTE SET B
M7

oiN 22 HIGH BYTE SET A

lL--nM‘__ PIN 22 LOW BYTE SET A

r—--nM—— PIN 22 HIGH BYTE SET
B

L—M0 pin 22 LOWBYTE SET B

+5vDC —22
) J

D.M{: PIN 27 HIGH BYTE SET A
PIN 27 LOW BYTE SET A

M50

M35

PIN 27 HIGH BYTE SET B

PIN 27 LOW BYTE SET B
CSKTAMSS

_ _ _

43%@£::HNNHMHEHE%TA

PIN 20 LOW BYTE SET A
M47

-CSKTB—L

e - — — —

M38

_D__L__‘

PIN 20 HIGH BYTE SET B

PIN 20 LOW BYTE SET B
Ma

PIN 26 HIGH BYTE SET A

E}——{:::FHNZGLOWBYTESETA
M21

3V —]

GND -M24py~

QM—”-

NOTE:

M23

DECODE

MEMORY

ADDRESS

M4 IS USED TO PROVIDE BATTERY
BACKUP POWER TO SOCKET SET A

WHEN THIS OPTION 1S INCORPORATED.
MR-6670

Figure

2-6

Memory

Configuration

M23

(177776)
(173000)

MAP 0

64 KB

MAP 1

64 KB

(NOTE 3)

2 KB (NOTE 1)

(172000)

MAP 2

64 KB

(NOTE 3)

3
MAP

64 KB

(NOTE 3)

4 KB LOCAL RAM
4 KB LOCAL RAM
aE%E%FALRAM
4 KB LOCAL RAM
(170000)
=_2)
56KB(Non
TE2)
56KB(NO
)
KB
N
&6
2)
OTE
6KB(
(1mxmm5

48 KBH

48 KB

“40000)48 KB-

LSI-11 BUS

LSI-11 BUS
“20000)40 K B-

40 KB+

40 KB~

(100000)32 KB~

32 KB:

32 KB

(emmm24 ;

24 KB-

24 KB!

24 KB4 16 KB SOCKET A

MmmmlGK&

16 KB

16 KB
A
8 KB SOCKET

8 KB+

20000 8 KB+
(20000}

(10000)
NOTE4

0 KB

8 kB 16 KB SOCKET B

8 KB

4 KB SOCKETA

B
8 KB SOCKET

B
4 KB SOCKET

0 KB

0 KB:

NOTES:

1. SOCKET SET A IS MAPPED OVER SOCKET SET B AND IS
THEREFORE LIMITED TO USING EITHER SOCKET A OR
SOCKET B, BUT NOT BOTH TOGETHER.

2. ADDRESSES 160000 THROUGH 160007 ARE ASSUMED TO
RESIDE ON THE LSI-11 BUS.
3. THIS SECTION CONTAINS THE LOCAL 1/0 ADDRESSES FOR
THE SLUs AND PPI. ALL UNASSIGNED ADDRESSES ARE
ASSUMED TO RESIDE ON THE LSI-11 BUS.

-4. UNDERLINED ADDRESSES ARE JUMPER-SELECTABLE START
ADDRESSES, ACCORDING TO TABLE 2-3.

Figure

2.1.7.2 PROMs/EPROMs
28-pin PROMs or EPROMs.

2-7

The

Memory

28-pin

MR-7243

Maps

sockets

24-pin

If 24-pin chips are selected, caution must
ed into socket hole
be observed to ensure pin 1l o f the chip is plac
compatible
industry
3.

The

configuration

requirements

some

2-10. The user may
PROMs/EPROMs are described by Tables 2-9 and
guration must be
select chips from other vendors bu t the pin confi
output

compatible

with

the

sockets

provided.

250

maximum

Table
Vendor

2-9

Socket

Part

Set

Pins

A Configuration

Size

Connect

for

EPROM/PROM

Referenced

M43

M48

M44

M34

M57

M36

M4l

M58

M51

M56

M51

M50

M51

M56

M51

M32

M49

M51

M56

M51

M32

Socket A Pin

EPROMS
INTEL

2758

INTEL

2716

2716-1

2716-2

2732

2732A

INTEL

2764

M49

M33

M46

M49

M51

M56

M51

M32

TMS2508

M51

M56

M51

M33

M51

M56

M51

M32

TMS2516

TMS2516-35

TMS2564

M46

M50

M51

M46

M56

M49

M51

M32

Mostek

MK2716

M51

M56

M51

M32

Mostek

MK2764

M49

M46

M49

M51

M56

M51

M32

PROMS
INTEL

3628

Signetics

82Ls181

M56

M51

M33

M51

M56

M33

M51

M33

M51

M33

requires

connection.

enable
time
is
also
required
compatible PROMs/EPROMs is 450

defined

the

bus

master

the

The

user

chip

time
time

installs

type
provides

are

from
the

the

module

jumper

the

and

socket pin
reference
for

the
maximum
access
time
for
The maximum output enable time
assertion of TDIN or TDOUT by a

ns.

wire

asserts
from

valid

the

in
signals

the

described

a
all
associated
with
the
wirewrap
pins.
listed separately under socket set A

data

onto

referenced

the

bus.

the

tables.

Figure 2-6
socket
pins

and
the
These
interconnections
are
and socket set B,
and some
jumper wires are common to both socket sets. Some devices may not
require
a
connection
or
a
jumper
wire
installed
and
these
are
designated by an
"NC"
in the
tables.
The wirewrap pin locations
shown

Figure

2-1.

Table 2-10

Socket Set B Configuration for EPROM/PROM

Part

Pins

Size

Connect Referenced Pin

INTEL

2758

1Kk X 8

M51 M47 M51 M50

INTEL

2716

2K X 8

M51 M47 M51 M32

INTEL

2732

4K X 8

M49 NC

M49 M51 M47 M51 M32

2732A

INTEL

2764

8K X 8

MA49 M33 M46 M49 M51 M47 M51 M32

TMS2508

1K X 8

M51 M47 M51 M33

TMS2516

2K X 8

M51 M47 M51 M32

TMS2564

8K X 8

M46 M50 M51 M46 M47 M49 M51 M32

Mostek

MK2716

2K X 8

Mostek

MK2764

8K X 8

M49 NC

M46 M49 M51 M47 M51 M32

INTEL

3628

1K X 8

M47 NC

M47 M51 M33 M51 M33

SIGNETICS

82LS18l1

1K X 8

M47 NC

M47 M51 M33 M51 M33

Vendor

to Socket B Pin
M42 M35 M45 M37 M39 M38 M40 M58

EPROMS

2716-1
2716-2

TMS2516-35

24
24

2K X 8
2K X 8

4K X 8

2K X 8

M51 M47 M51 M32

PROMS

NC requires NO connection.

RAMs -- The 28-pin sockets can also accept 24-pin static
the chip
RAM chips and caution must be observed to ensure pin 1 of ments
of
require
ration
configu
The
3.
hole
is installed into socket
and
2-11
Tables
in
ed
describ
are
RAMs
ble
some industry compati
the pin
2-12. The user may select chips from other vendors but ed.
The
provid
s
socket
the
with
ible
compat
be
must
n
configuratio
time
selected RAMs are required to meet the maximum output enable
2.1.7.3

and the maximum access time specified for the PROMs.

The user installs a jumper wire from the pin referenced by the
chip type to the socket pin described in the tables. Figure 2-6
provides a reference for all signals and the socket pins
associated with the wirewrap pins. The interconnections are listed

separately

under

socket

common

both

socket

connection

"NC"

the

jumper

tables.

2-1.

Table
Vendor

2-11

Part

and

socket

sets.

wire

The

Socket

Set

MK4802

TOSHIBA

TMM2016P

TMM2016P-1

HM6116P

HITACHI

requires

HITACHI

requires

shown

Configuration

for

Socket

M43

Figure

RAM

Referenced

M48

M44

M34

MS57

M36

M41

M58

M55

M53

M56

M54

M32

M52

M55

M53

M56

M54

M32

M52

M55

M53

MS56

M54

M32

Set

Size

Confiquration
Connect

for

RAM

Referenced

Socket

M42

M35

M45

M37

M39 M38

M40

M58

M52

M55

M53

M47

M54

M32

M52

M55

M53

M47

M54

M32

M52

M55

M53

M47

M54

M32

and

boxes

HM6116P

connection.

SELECTING
of

system

designated

BACKPLANES

different

available

are

M52

2.2
are

require

TMM2016P

these

Connect

TMM2016P-1

number

wires

not

Socket
Pins

MK4802

TOSHIBA

2-12

Part

MOSTEK

and

jumper

may

connection.

Table
Vendor

some

locations

Size

MOSTEK

and

devices

installed

wirewrap

Pins

Some

from

requirements

AND

OPTIONS

LSI-11

bus

compatible

Digital.

The

choice

such

the

backplanes

must

number

and

dictated
type

the

optigns

(described
in Chapter
3),
environmental conditions and packaging
considerations.
A list of all
available backplanes and
boxes
1is
described
in the Microcomputer Interfaces Handbook referenced
in
Chapter 1.

2.3
POWER SUPPLY
The choice of power supply

and

packaging

behavior of

the

requirements.

supply during

governed

important

power

the

size

the

system

consideration

up and power down.

the

All Digital

power supplies 1listed in the Microcomputer Interfaces Handbook
(see Chapter 1) are compatible with the LSI-11 bus protocol. This
loss of data when using
reliable operation with no
assures
battery-supported
conform

2.4

this

memories.

Any

user-designed

power

supply

must

protocol.

EXTERNAL

CABLES

The module has a 30-pin connector (J3) for external interfacing
with the Programmable I/0 Interface and two 10-pin connectors (J1
and J2) for external interfacing with the Serial Line Units (SLU).

The

2-1.

location of these connectors on the module
The user's requirements to

defined

below.

2.4.1

Parallel

I/0

cable

Interface

in Figure

is shown

interface with these connectors

(J33)

The module connector is a 30-pin AMP MODU connector with the I/0
signals defined by Figure 2-8. The I/O signals are buffered and
are capable of driving up to 50 feet (maximum) of unshielded flat
ribbon

end.

module

AMP

round

The

following

with

1list

30-pin

AMP

connectors

contact

housing

compatible

each

with

the

connector.

MODU

snap-in

polarized

Latching,

and

nonpolarized

receptacle

contact

housings

for

polarized

2-87631-6

housings:

87733-6

strain

relief

strain relief

Nonlatching,
housings:

polarized

1-87977-3 no strain relief
1-102184-3 strain relief

Nonlatching,
housings:

nonpolarized

2-87456-6
2-87832-7

Receptacle

Mass

contacts:

parts:

(nonpolarized)

Separate

parts:

(polarized)

Connector

and

cover

kits:

(nonpolarized)

Connector

and

(polarized)

cover

no strain relief
strain relief

87045-3 for 30 to 26 AWG
102098-3 for 32 to 27 AWG

termination connectors

Separate

crimp

contacts:

kits:

for

flat

cables

1-88378-1

connector

1-86873-2
1-88340-1

cover
strain

1-88392-1

connector

1-86373-2
1-88340-1

cover
strain

1-88379-1

1-88476-1

with

relief

strain

1-88393-1

1-88478-1

with

2-21

relief

cover

relief

strain

cover

relief

strain

relief

PPl INTERFACE
CONNECTOR J3

LOOPBACK
TEST CONNECTOR
JUMPER WIRES

PCO
PC1
pc2

(USED ONLY WHEN PORT A BUFFERS

ARE CONFIGURED AS INPUTS AND
PORT B BUFFERS ARE CONFIGURED
AS OUTPUTS.)

PC3

PC4 ____|
PC5

PC6

PC7

PBO

PBY —
PB2 ___|

PB3

PB4
PB5

PB6

PB7
PA7

PAB
PAS

PA4
PA3
PA2
PAT

PAO

GND

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE
29

GND PAO

PA1]1PA2|PA3

PB4

PB5

[GND PB6 | PB7 | PCO | PC6 | PC4 | PC1|GND

GND PA7

PA6 | PA5|PA4

PB3

PB2

|GND

PB1|PBO

|PC3

|PC7 | PC5 | PC2 |GND

%N
PC

BOARD
MR-6671

Figure

2-8

Parallel

I/0

Connector

connector

1-88392-1

Separate parts:

cover

1-86873-2

strain

1-88340-1

cover

relief

Latching connectors and covers:
(polarized)

1-88423-1 no strain relief
1-88479-1 with strain relief

Mass Modular Connector System:

1-102393-3 housing for 30-26 AWG
1-102396-3

cover

1-102392-3 kit
1-102398-3 housing
1-102396-3
1-102397-3

for

26-22 AWG

cover
kit

Connectors can be terminated to discrete wire in sizes 30-26 AWG,
26-24 AWG, as well as jacketed cable and bonded ribbon cable.
Serial Line Interfaces

2.4.2

(J1 and J2)

Each of the Serial Line Units is compabible with EIA RS-232 C and
Serial line unit #1 interfaces
EIA RS-423 serial type interfaces.
through J1

and

mA current

line

serial

loop device

unit #2

interfaces through J2.

then

the DLV11-KA option

and

the

box

must be used. The option has an EIA cable

the

converter

standard

box

20 mA cable

the

using

module

the

When a

desired,

(BC21A-03)

8-pin Mate-N-Lock

that connects

mates

with

connector.

the

Note

that the option does not support the Reader Run strobe and the 110
baud rate so that LA-33 or similar devices cannot be used.

The user is required to install a slew rate resistor determined by
the operating baud rate as defined

resistor

shown

Factory

The slew rate

is designated as R6 and its location on the module 1is

Figure

2-1.

Table 2-13

in Table 2-13.

EIA Slew Rate Resistor Values

Baud Rate

Resistor R6

38400
19200
9600
4800
2400

22K*
51K
120K
200K
430K

1200
600
300

820K
Im
1M

Installed Value.

(ohms)

The serial line unit connectors showing the signals assigned to
The user is required
the connector pins are shown in Figure 2-9.
to

provide

assist

describes

the

some

the

interconnecting

standard

user

cables.

DIGITAL cables

in designing

and

The

also

following

1list

information

some

cables.

SLU

CONNECTOR

LOOPBACK

BAUD RATE

cLockoutPut

TEST CONNECTOR

(16 X BAUD)

JUMPER WIRES

TRANSMIT DATA+ —{ 3

INDEXING KEY

— 6

RECEIVE DATA+

—{

RECEIVE DATA-

—f 7

+12 VDC FUSED

—]

GND

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE
9

O0Olo|O0}|0]O

O|]O0O|®@]|0O|O
|»

PC BOARD

INDEX (NO PIN)

Figure

DIGITAL

cables

BC20N-05

2-9

for

the

foot

Serial

Line

Unit

Connector

SBC-11/21

EIA

RS-232C

null

modem

cable

directly

interface with the EIA RS-232C terminal
(2 X 5
Amp female to RS-232C female; see Figure 2-10).

foot

EIA

RS-232C

modem

cable

and acoustic couplers (2 X
C male; see Figure 2-11).

interface

Amp

with

female

50
foot
EIA
RS-422
or
RS-423
cable
for
highspeed
transmission (19.2K baud) between two SBC-11/21's (2
X 5 pin Amp female to 2 X 5 pin Amp female).

BC20M-50

modems
RS-232

]

BC21B-05

SBC-11/21

EIA RS-232C

XMT DATA +>3

l’ ‘|

3L RCV DATA

RCV DATA + ) 8

i :

!—

2 XMT DATA

[

RCV DATA
- HLeem
GRD >2
GRD

i i

| |

|
n

2L GRD

oot

SHIELD

1¢
>

IMPORTANT:

ATTACH TO CHASSIS
AT ENTRY POINT.
MR-6672

Figure

2-10

BC20N-05

SBC-11/21

"Null

Modem"

Cable

EIA RS-232C

{5 €&- g CLEAR TO SEND (CB)

GRD) 9>

( 4 &~ - REQUEST
TO SEND (CA)

RCV DATAD 7 )-

—{ 6 €- - DATA SET READY (CC)

+12VDC

Fone

«
10)

758012W

1,
!
wWA—20€
— - DATA TERMINAL READY (CD)

RCV DATA
) 8)

{ 3 {RECEIVED DATA (BB)

XMIT DATA +) 3 )

—{ 2 { TRANSMITTED DATA (BA)

GRD> 2 )

£ 7€{ SIGNAL GROUND (AB)

©r
SABLE
CONNECTOR
()

1 { PROTECTIVE GROUND (AA)
MODEM

MR-6673

Figure

2-11

BC21B-05

Modem

Cable

When designing a cable for the SBC-11/21, here are several points
to

consider:
1.

The receivers on the SBC-11/21 have differential inputs.
Therefore, when designing an RS-232C or RS-423 cable,
RECEIVE DATA- (pin 7 on the 2 X 5 pin Amp connector) must
be tied to signal ground (pins 2, 5, or 9) in order to
maintain proper EIA levels. RS-422 is balanced and uses
both RECEIVE DATA+ and RECEIVE DATA-.

directly connect to a local EIA RS-232C terminal,
it
is necessary to
use
a null modem.
To design the null
modem into the cable,
one must switch RECEIVE DATA
(pin
2)
with
TRANSMITTED
DATA
(pin
3)
on
the
RS-232C
male
connector

mate

Receptacle

Clip

2.5.1

Figure

2-10.

connector

block,

(pin

Contacts

AMP

87133-5

DEC

12-14268-02

AMP

87124-1

DEC

12-14267-00

AMP

87179-1

DEC

12-15418-00

following

OPERATION

can

be
field
tested
to
verify
Macro-ODT
option
and
the
loopback
support the testing of the module.

Macro-ODT

the

needed.

VERIFYING

Cable

SBC-11/21
operation.
The

used

the

are

Key

The

shown

parts

Locking

2.5

its
functional
connectors
are

Option

The Macro-ODT option (part # KXT1l1-A2) consists of two, 24 pin, 2K
X
8
PROM
chips
that
contain
the
Macro-ODT
code
and
modgle
diagnostic
programs.
The
Macro-ODT
code
is
used
to
establish
communication
between
the
module
and
the
user
via
console
commands.
The use of ODT commands is detailed in Chapter 4.
The
module diagnostic programs verify that the Parallel I/0 and Serial
Line
Unit
interfaces
will
function
with
commands
from
the
microprocessor.
2.5.2

The

Loopback

loopback

Connectors

connectors

module

diagnostic

jumper

wires

installed

the
Parallel
I/0
with the loopback

and

2.5.3

used

with

can

tests.
is

The

fabricated

30-pin

shown

connector

Fiqure

2-8,

the

user

with

the

and

for

the

loopback
used

with

connector J3.
The
Serial
Line Unit connector
jumper wires installed
is shown in Figure 2-9,
the serial line unit #2 connector J2.

Verification Procedure
module must be restored to the standard factory configuration
for the test to be valid,
except that the start address must be
172000
instead of 10000. The module can be verified by using the
following procedure.

The

Set

the

start

address

high

byte

172000

Insert

the

socket

E61.,

Insert
socket

the low byte ODT ROM
E47.
Ensure pin 1 is

Ensure

ODT ROM
pin

into

shown

socket

inserted

Table

set A,

into

2-3.

high

socket

byte

hole

into socket set A, low byte
inserted into socket hole 3.

Insert.the
2.5.2) into

30-pin
loopback
connector
(see Paragraph
the module Parallel I/0 connector J3.

Insert.the
2.5.2) into

l10-pin loopback
connector
(see Paragraph
the serial line unit #2 connector J2.

Install the module into the LSI-11 backplane with the
power turned off. An external power supply may be used to
provide +5 Vdc to finger pins BV1, BA2, and AA2, +12 Vdc
to

finger

AT1,

AC2,

BC2,

BD2

AM1l,

and

Ground

and BM1.

finger

pins

BJl,

AJl,

The
Connect an external terminal (printer or video).
code
ASCII
7-bit
a
g
generatin
of
capable
be
must
terminal
with odd parity or 8-bit ASCII code with no parity, and
baud rates of 300, 600, 1200, 2400, 4800, or 9600. The
terminal is connected to the serial 1line unit #1
or
cable
BC20N-05
Digital
a
using
connector Jl1
equivalent. Turn the terminal on and on line.

Turn on the backplane power or enable the +5 Vdc and +12
The LED should
Vdc sources. Monitor the module LED.
If
illuminate and then return to the normal OFF state.
the
in
fault
a
is
the LED remains illuminated, there
serial line unit #1 circuits or the on-board RAM memory.

After the backplane power is turned on, press the
"RETURN" key (carriage return) on the terminal in order

for the module to synchronize its baud rate to that of

the

terminal.

character

"@",.

The

module

responds

with

the

prompt

To initiate the module diagnostic programs press the "X"
The diagnostic test will exercise the module
key.
The
including the Parallel I/O and Serial line unit #2.
The
al.
termin
the
on
out
d
printe
are
test
the
of
results

error results are listed in Table 2-14 and indicate what
The error code
area of the module contains a fault.
"000000"

indicates a good module.

Table

2-14

Diagnostic

Parallel

I1I/0
Test

Internal

Fault

Indicators

Serial*

External

Serial**

Printout

Loopback

000000

Passed

000001

Failed

Passed

000010

Passed

Failed

Not

Performed

000011

Failed

Not

Performed

000100

Passed

Failed

000101

Failed

Passed

Failed

000110

Not

Used

Not

Used

Not

Used

000111

Not

Used

Not

Used

Not

Used

*The

Internal

to-serial

baud

Serial

I1/0

I/O0

conversion,

rate.

This

test

Loopback Test

Loopback

Test

I1/0

Loopback Test

exercises

the

parallel-

the

serial-to-parallel conversion, and the
can
be
performed
without
the
1loopback

connector.

**The

External

Serial

functions as well
signal paths.

I/0
the

Loopback
drivers,

Test

exercises

receivers,

and

the

above

external

CHAPTER

OPTIONS

3.0

GENERAL

operate

The SBC-11/21
some

the

LSI-11

applications

SBC-11/21

the

module

following

manuals

listed

that will

is a complete single board microcomputer

the

bus

could

extend

itself.

sections.

in Chapter

standalone

advantageous

its

configuration.

add

all

such

this

modules

that provided

options

found

information may be

optional

functionality beyond

listing

given

in hardware

manual.

SUPPORTED OPTIONS

3.1

The following options are functionally compatible with the
SBC-11/21. Software diagnostics for these options will run on the
SBC~-11/21 equipped with a mass storage device (TU58, RX0l or RX02)
and the Macro-ODT option. To order diagnostics, contact your DEC
sales

representative.

TUS8

This

low cost mass memory device

SBC-11/21
lines.

TU58

attaching

offers

random

can

one

access

used

the

with

serial

block

the

I/0

formatted

data on pocket-size cartridge media. It is ideal as a
small computer systems device, as inexpensive archive
mass storage, or as a software update distribution
medium.
A dual drive TU58 offers 512 Kb of
storage
space, making it one of the lowest cost complete mass

storage
subsystems
available.
For
mounting
flexibility, the TU58 is offered both as a component
level subsystem and as a
fully powered
5-1/2
inch

interfaces with the
The TU58
rack-mount subsystem.
microprocessor over an RS-423 serial line interface.

DLV11-E

The DLV11-E is an asynchronous line interface module
that interconnects the LSI-11 bus to standard serial
communications lines. The module receives serial data,

converts it to parallel data, and transfers it to the
LSI-11 bus. Also, it accepts parallel data from the
LSI-11 bus, converts it to serial data, and transmits
has
module
The
device.
©peripheral
the
to
it
jumper-selectable

software-selectable

baud

rates

interface

module

(50-19,200), and jumper-selectable data bit formats.
The DLV1l1-E offers full modem control for EIA/CCITT
interfaces.

DLV1l-F

The

that

DLV11-F

interconnects

asynchronous

1line

the LSI-11 bus to several

types of

module
The
lines,
communications
serial
standard
receives serial data, converts it to parallel data,
It also accepts
and transfers it to the LSI-1l1 bus.

parallel data
serial data,

from the LSI-11 bus,
and transmits it to

converts it to
the peripheral

device.

The

module

has

software-selectable

jumper—-selectable

baud

rates

(50-19,200)

and

jumper-selectable
data
bits.
THe
DLV11-F
supports
either 20 mA current loop or EIA standard lines,
but
does not include modem control.
DLV11-J

The

DLV11-J

serial
devices

receives

four

independent

data

from

the

peripheral

device

(lines

that

not

control

module

can

DLV11-KA

used

with

adapter

1is

jumper—-selectable

baud

The

DPV11-DA

double-buffered

use

current

used.

rates

asynchronous

interface
peripheral
channel transmits and

leads
a

DPV11-DA

contains

1line
channels
wused
to
to the LSI-11l bus.
Each

over

loop

The

from

150

single-line

EIA data

1line).

The

devices

DLV11-J

39.4

if
has

baud.

program-controlled,

device
designed
to
interface the LSI-11 Bus to a serial synchronous line.
This self-contained unit is capable of handling a wide
variety of protocols including bit-oriented protocols
such

SDLC,

protocols

The

HDLC,

such

module

such

communication

1is

ADCCP,

DDCMP

used

remote

for

batch,

and

X.25,

and

byte-oriented

BISYNC.

high

remote

speed
data

synchronous
collection,

lines
remote

concentration,
and
communication
networking.
In
addition to being compatible with EIA RS-232 and CCITT
V.28
interface
standards,
the
module
is
compatible
with
EIA
RS-423
and
422
electrical
standards,
permitting low cost, local communications capability.
DRV11

The

DRV11l

parallel

to
1interconnect
parallel
1line

the
TTL

program—-controlled
words

per

control
vector

second

interface

data
and

1logic
to
handling.

module

that

used

LSI-11
bus
with
general-purpose
or
DTL
devices.
It
allows
transfers
uses

LSI-11

rates

bus

40K

interface

and

generate
interrupts
and
The
data
1is
handled

process
by
16

diode-clamped input lines and 16 latched output lines.
two 40-pin connectors on the module for user
applications.

There are
interface
DRV11-B

The

DRV11-B

memory

the

system

programmed

blocks of
locations
there

access

an
(DMA)

interface
to

module

transfer

that

data

direct
between

memory and an I/0 device.
The interface is
by
the
processor
to
move
variable
length

8- or 16-bit data words to
in
the
system
memory.

or from specified
Once
programmed,

module

1is
no
processor
intervention
can transfer up to 250K 16-bit

single-cycle

the

uses

directly

mode

and

per
second
in
the
burst
mode.
read-modify-restore operations.

required.
The
per second

words

500K
It

1l6-bit

words

also

allows

DRV11-J

The DRV11-J provides sixty-four
on

also

DRV11-J

for

module

double-height

includes

input/outut data lines
The

bus.

LSI-11

the

structure

interrupt

advanced

with bit interruptability up to 16 lines, programmable
interrupt vectors, and program selection of fixed or
The
rotating interrupt priority within the DRV11-J.
make
response
real-time
for
DRV11-J's bit interrupts
It
it especially useful for sensor I/0 applications.
to
interface
general-purpose
a
as
used
be
also
can
connected
be
can
two DRV1l-Js
and
custom devices,
back-to-back as a link between two LSI-11 buses.
DUV11-DA

The

synchronous

DUV11-DA

equivalent.
respect to

and

bits),

module

1line

interface

fully

programmable

the
between
1line
communication
data
a
modem or
synchronous
and a Bell 201

establishes
LSI-11 bus

The

module

sync characters,

character

The

selection,

parity

length

(up

receiver

bus.
LSI-11
the
for
data
serial
accepts
transmitter logic converts the parallel LSI-11
data into serial data for the transmission line.

interface

logic

converts

levels

logic

the TTL

with

to 8

logic

The
bus
The

the

EIA voltage levels required by the Bell 201 modems and
also controls the modem for half-duplex or full-duplex

operation.
DZV11-B

The DZV11-B is an asynchronous multiplexer interface
module that interconnects the LSI-11 bus with up to
four asynchronous serial data communications channels.

EIA

provides

interface

voltage

levels

and

The

module

The
the

IBV11-A is an interface module that interconnects
LSI-11 bus with the instrument bus described in

data set control to permit dial-up
(auto-answer)
options with full-duplex modems such as Bell models
The DZV11-B does not
103, 113, 212, or equivalent.
the secondary
or
operations
half-duplex
support
some
in
available
operations
receive
and
transmit
The module has applications
modems such as Bell 202.
in data concentration and collection systems where
front-end systems interface to a host computer and for
use in a cluster controller for terminal applications.
IBV11-A

IEEE

standard

Programmable

1975,

488

"Digital

Instrumentation.”

The

Interface

IBV11-A

for

makes

system
instrument
programmable
processor-controlled
possible.
The module can accomodate up to 15 IEEE-488
devices.
MRV11-C

The

MRV11-C

1is

flexible,

high-density

ROM

module

The module contains sixteen
used with the LSI-11 bus.
a variety of user-supplied
accept
which
24-pin sockets

accept masked ROMS,

fusible 1link

densities of ROM chips up to and

including 4K

ROM chips.
PROMs,

several

and

It will

ultraviolet

3-3

erasable

PROMs.

accepts

chips.

module

Using

these

high-density

chips

total capacity of 64K bytes.
module
can
be
accessed
in
one

the

The
of

gives

the

contents

two

ways

-—either
directly
or
window-mapped.
Direct
access
provides total
random access to all ROM locations on
the
module,.
Window-mapping
provides
two
2K-byte
windows
of
memory
address
space
to
access
2K-byte
segments

the

viewed

through
control.

MSV11-D

The

ROM

each

array.

window

The

can

segments

varied

that

under

are

program

MSV11-D

module
has
either
8K,
16K,
or
32K X
16
MOS memory.
The module has an on-board memory
and performs the necessary LSI-11 bus cycles.
The
memory
addressing
is
selectable
by
the
user
by
configuring
switch
settings,
The
module
can
use
a
battery
backup system
to
preserve
data
when
primary
power is lost.

bits of
refresh

MXV11-A

The

MXV11-A

module

for

memory,

the

dual

LSI-11

provisions

asynchronous

serial

signal

derived

memory

height
It

for

read-only

line

from

multifunction

bus.

contains

interfaces

option

read/write

memory,

and

two

clock

crystal oscillator.
Read/write
either 8K or 32K bytes
(4K or
16K words).
Two 24-pin sockets are provided for +5 V
read-only memories.
1K X 8,
2K X 8,
or 4K X 8 ROMS

may

supplied

used.

with

The

words

lines

transmit

sockets

bootstrap

150

baud
to
current
loop

code.

and
38.4K

receive
baud.

operation

with the DLV11-KA
serial lines will

EIA

parity

Serial

also

be
used
for
256
asynchronous serial

two

EIA-423
20
mA

110

signal
active

baud

may

levels from
or
passive
be

obtained

20 mA converter option.
The
not support the reader run function
option.
The
serial
1lines
provide

of
the
DLV11-KA
error
indicator
bits
and

may

The

error,

for

but

overrun

not

error,

have

frame

modem

line

error,

controls.

1 may be configured to respond to a break
The serial lines have signal level interrupt
Serial line 1 along with serial line 0, may be
used
with
any
of
several
standard
types
of
serial
communication devices.
The 60 Hz clock signal can be
selected
by
a
wirewrap
Jjumper
to
provide
line-time
clock interrupts on the bus.

signal.
logic.

RXV21

The

RXV21

memory
on
can

RXV21l
interface

single
module

disk

that

preformatted,

store

The

floppy

device
and

data

flexible

retrieve

system

option

stores

random

diskette.
512K

access

fixed-length
8-bit

rack-mountable

and

Each
bytes

mass

blocks

diskette
of

consists

data.

an
module,
an
interface
cable,
and
either
a
or dual RX02 floppy disk drive.
The interface
converts
the
RX02
I/0
bus
to
the
LSI-11
bus

structure.

controls

the

RX02

interrupts

the

decodes

processor,

addresses

device

for

selection, and handles the data interchange between
Power
the RX02 and the processor via DMA transfers.
LSI-11
the
by
supplied
is
module
for the interface

bus.

The RXV1l option consists of an interface module,
cable assembly, and either a single or dual drive RX0l

RXV11

floppy

disk.

This

option

random

access,

mass

storage device that stores data in fixed-length blocks

on a preformatted flexible diskette. Each diskette can
store and retrieve up to 256K, 8-bit bytes of data.
The RXV1l system is rack mountable in the standard
48.3

3.2

The

cabinet.

in)

(19

UNSUPPORTED OPTIONS

following

LSI-11

options

bus

1listed

Table

3-1

are

not

guaranteed to be functionally compatible with the SBC-11/21, and
are termed “unsupported." Their diagnostics are not available.
Table 3-1

Unsupported LSI-11 Options

AAV11-A
ADV11-A

FEPTC-BA
FPF1l1

DRL11-SN

KDF11-AB/AC/BB

BDV11-AA/BA
DA11-MS/QQ/QU
DAV11-A/B

DUV1l1-E/F

DUV25
DW1ll

DWV11-A

LPV1l
MRV11-AA/BA/VU

TRV11
TSV11

RKV1l1

VTV0l-A

IPV12
KD11l-F
KD11-HA

MSV11-E/P
NCV11l-A
REV11

KDF11-BC/P

RLV11

KPV11-A
KWV1ll-A
LAV11

RLV12
TEV11

VMV66-A
VK170
VSVvll
VTV30-H

CHAPTER

MACRO-ODT

GENERAL

4.0

The Macro-ODT is the KXT11-A2 option that is available for users
of the SBC-11/21 single board computer. The option consists of two

24-pin, 2K X 8 ROM chips which contain the Macro-ODT firmware, and
a complete listing of the firmware. The chips are installed on the

module

using

the

PROM

sockets.

Macro-ODT allows the user to do the following:

Examine and deposit data in memory or general registers.

Examine or alter the Processor Status Word

Start the execution of the program.

Resume the execution of a halted program.

Bootstrap

Run a confidence test for on-board devices.

programs

from

mass

(PSW).

storage

cassette, RX01 or RX02 floppy disks).

device

(TUSS8

INSTALLATION AND CONFIGURATION

4.1

This is described in detail in Chapter 2 and the user is referred
to it for installation and startup instructions.
4,2

ENTRY

CONDITIONS

Macro-ODT

entered:

Upon

power

Via the "BREAK" key on the console terminal.

Execution of a HALT instruction.

Assertion of the BHALT L signal on the LSI-11 Bus.

.
Accessing nonexistent memory (i.e., a bus timeout)

4.2.1

Macro-ODT

up.

Input Sequence

Upon entry to Macro-ODT, the RBUF register is read using a DATI
and the character present in the buffer is ignored. This is done
so that erroneous characters or user program characters are not

interpreted by Macro-ODT as commands, especially when a program is

halted.

The input sequence for Macro-ODT is as follows.
1.

Read and ignore character in RBUF,.
4-1

Output

contents

<CR>

terminal

<KLF>

terminal.

(program

counter

ODT

entered

via

instruction or an attempt
to
fetch
nonexistent memory. Output a "?" to
is entered via a bus timeout.

R7)

Output

the

Enter a wait loop for terminal input. The
7 in RCSR,
is tested using a DATI.
If it

<KLF>

prompt

six

digits

HALT
an
instruction from
the terminal
if ODT

<CR>

BREAK,

BHALT,

terminal.

character,

terminal.

Done flag, bit
is 0, the test

continues.
7.

4.2.2
The

RCSR

DATI.

Macro-ODT

output
1.

bit

Test

4.3

Output

sequence
XCSR

continue

then

low

byte

RBUF

DATI

read

using

Sequence

for

ODT

byte

(Done

follows.
flag)

using

and

testing.

If XCSR bit 7
is 1, write character to low byte of XBUF
using a DATI followed by a DATO (high byte is ignored by
interface).

MACRO-ODT

COMMANDS

The

Macro-ODT

commands

the

following

paragraphs.

The

parity

are

listed

in Table
4-1
and
described
in
commands are a subset of ODT-11 and
use the same command character. The Macro-ODT internal states are
listed
in Table 4-2.
For each state only specific characters are
recognized as valid inputs; other inputs invoke a "?" response.

Macro-ODT,

bit,
and

bit

the

input

parity is copied to
internally generated
to

All

characters

input

are

The

all

input

character

the output buffer
by ODT (e. g., <CR>)

characters

are

characters

echoed,

1is

the

echoed.

Only

uppercase

NOTE

use

ODT

commands

establishes
a
the
user
and
the
Therefore,
all
the
characters
typed
by
the
user
are
underlined
and
the
system
response
is
not underlined.

dialog
between
microcomputer.

by
the

(XBUF).
Output characters
have the parity bit equal

recognized.

The

ignored

state

command

Macro-ODT Commands

Table 4-1
Command

Symbol

Use

Slash

Prints the contents of a

Carriage Return

<CR>

Closes an open location.

Line Feed

<LF>

Closes an open

specified

location.

location and

then

opens the next location. This command
cannot be used with the general
registers.

Internal Register

Opens a specific processor register.

Word Designator

Opens

Starts program execution.

Proceed

Resumes execution of a program.

Boot from Device

Execute Diagnostics

Designator
Processor

Status

057)

the

command.

PSW

must

Loads and runs programs from floppy

diskettes or TUS58

cassettes.

Runs SBC-11/21 module verification
diagnostic.

Slash

/(ASCII
4.3.1
This command is used to open an on board module address,andLSI-11
must
Bus address, processor register, or procesSor status word

which specify a location.
be normally preceded by other charascters
contents of the location
the
print
-ODT
In response to /, Macro
space (ASCII 40). After printing
(i.e., six characters) and then a eithe
r new data for that location
is complete, Macro-ODT waits for
character is
or a valid close command (<KCR> or <LF>). The space
ble new contents
and possi
issued so that the location's contents termi
nal.

entered by the user are legible on the
Example:

@001000/12525<SPACE>
where:

001000

= Macro-ODT prompt character

ss
= octal location in the LSI-11 Bus addre
0O0s are
space desired
not required)

by the

user

(leading

command

open

octal

location
012525

contents

<SPACE>

space

issued

<LF>

4.3.2

This

immediately

printed

character

after

because

contents

location

generated

prompt

location

not

contents

1000
by

character

15) Carriage Return
used to close an open

are

changed,

the

user

Macro-ODT

causes

<CR>

open.

location.

should

the new data.
If no change is
without altering its contents.

desired,

Example:

<CR>

@R1/004321<SPACE>

<CR>

@
Processor

issued

<CR>.

was

response

opened

Example:

@R1/004321<SPACE>

1234

this

case

entered

data

the

open

Macro-ODT

echoes

additional

<CR>,

Example:

user

before

location
the

and

<CR>

followed

@1000/012525<SPACE>

<LF>

change

R1l,

Macro-ODT

printed

<LF>,

1234

location's
<CR>

the

with

location

<CR>

the

and

<CR>

desired

Macro-ODT

<CR>

<CR>.

then

was

<CR>,

entered

change

the

closes

the

<CR>

desired

issuing

a
the

<LF>

were

precede

<CR>

and

<LF>@.

<CR> (ASCII

command

user

and

user

data,

1234,

new

and

the

<CR>

deposited

<LF>

printed

the

new

then

prints

<CR>

<LF>

where:

first

1line

new

data

and

the

1234

entered

location

into

closed

location

with

1000

<CR>»

4.3.3
<LF> (ASCII 12) Line Feed
This command is used to close an open location and then open the
next contiguous location. LSI-11 Bus addresses are incremented by
2.

the

processor

<LF>

will

<CR>

7?2

not

<KCR>

closed

enter
<KLF>,

the
If

and

open

any

changed,

the

entered,

the

Example:

@1000/123456<SPACE>

open

and

data

<LF>

command

that

was

typed

ODT

prints

1location's

new

the

error

contents

data
should
precede
the
<LF>.
If
no
location is closed without being altered.

@1002/054321<SPACE>

<LF>

<CR>

<LF>

issued,

prior

message

are

data

are

Table

4-2

Macro-ODT

States

and

Valid

Input

Characters

Example of
Terminal
State

Output

Valid

0--7
P
X
D

0--7
S

@1000/

0--7

123456

<CR>

@R1/123456

0--7
<CR>
<LF>

@1000

0--7

/
G

@R1

or @RS

@1000/
123456

0--7

1000

@RrRl/
123456
o *

0--7
1000

<CR>

@Dy

1
<CR>

10%*

@DX

1
<CR>

@DD

11%*

<CR>

0
1

*NOTE:

not

enter

followed

<CR>.

Input

In this case, the user entered <LF>
response, Macro-ODT closed location

with
1000

no data preceding it. In
and then opened location

1002.

4.3.4
R(ASCII 122) Internal Register Designator
The "R" character when followed by a register number, 0 to 7,
PS designator, S, will open that specific processor register.
Example:

@R0/054321<SPACE>
or

@R7/000123<SPACE>

456

<CR>

<LF>

@
If

than

Macro-ODT
Example:

one

uses

all

character
the

typed

characters

@RO0007/000123<SPACE>

<CR>

(digit

the
<CR>

after

the

designator.

<LF>

e
4.3.5

This

designator

must

(ASCII

employed

123)

for

Processor

opening

after

the

Status Word

the

PSW

user

(processor

has

status

entered

the

word)

and

designator.

Example:

@RS/100377<SPACE>

@RS/100317<SPACE>

Note

that

T-BIT

via

the

T-BIT

Macro-ODT.

FILTER

The

<CR>

prevents

T-BIT

can

<LF>

the

user

cleared

from

any

setting

write

the

PSW. When the filter is disabled, the T-BIT can be set by loading
the PSW to set bit
4
to
a one.
This is normally not considered
desirable. The T-BIT FILTER can be disabled by setting bit 15 of

location
The

167772

PRIORITY

one.

FILTER

prevents

the

user

from

setting

priority

level of 7 via Macro-ODT.
Operation at priority level 7 masks out
(disables)
the BREAK interrupt and makes it impossible to return
to Macro-ODT.
This type of operation is normally undesirable. If
required, the PRIORITY 7 FILTER can be disabled by setting bit 7
of location 167772 to a one. With the filter disabled, a priority
level

established

writing

340

4.3.6
G (ASCII 107) Go
This
command
is
used
to
start
program
entered immediately before the G.
Example:

@200G

into

the

PSW.

execution

location

The

Macro-ODT
sequence
character, is as follows.
1.

Load

(PC)

for

with

the

example,
R7
is equal
execution begins.)

echoing

entered

data.

200

that

and

The

The
LSI-11
Bus
1is
initialized
by
asserting BINIT L for 17 microseconds

The

BINIT

user

after

negates

cleared

the

(In

command

the

where

above

program

the
processor's
minimum and then

program

begins

execution

the

1location

specified.

The user
is warned that the command clears the PSW, which will
permit clock
interrupts to be acknowledged.
Failure to load the
address of the clock service routine into the clock vector address
(100) may lead to unpredictable results.
4.3.7

(ASCII

120)

Proceed

This
command
is
used
to
resume
programmer-visible machine state is
Example:

execution
of
a
program.
altered using this command.

WNo

Program

execution

4.3.8

DD,

resumes

the

address

pointed

R7.

After

P is echoed, Macro-ODT exits and the program resumes execution.
DX,

Bootstraps

This command is used to bootstrap a standalone program or XXDP+
diagnostics from an RX01l,
RX02 floppy diskette or a TU58
tape
cartridge. The next character after the D command determines the

type of device being booted. The numerical character, either 0 or
1, is optionally used to specify a particular drive or unit of the
device being booted. If <CR> is typed instead of 0 or 1, then unit
0

assumed.

Examples:

Boot

unit

TU58

device:

unit

RX01l

device:

unit

RX02

device:

@DD<KCR>

Boot

epx1
Boot

@DY0
NOTE

not

type

both

unit

number

and

<CR>.

boot

diskette

controller CSR
TU58,
it
must

drive,

ODT

expects

the

RXV1l

address
to be configured
for 177170.
To
be
connected
to
SLU2
and
the
baud
rate

RXV2l

boot
set

the
for

38,400.

Any

error

will

command

boot

execution

the

during

detected

cause a halt at one of several addresses in the boot portion of
the ROM, with the PC contents printed on the console. The actual
addresses, and the specific error each signifies, are given in the
listing

Some

supplied

errors,

with

the option.

however,

are

not

reported.

no TU58

is connected

use

SLU2, or if baud rates are incompatible, no error indication is
given after using the "DD" command and the program simply waits
forever. This is also true when booting from floppies when the
drive power
if off.
return to ODT prompt

The D

command

If
a

will

there

In either case,
level "@".

perform

the

user

following

RAM memory at

can

<BREAK>

operations.

address

zero,

it will

cause

halt.

It will initialize the LSI-11
for 17 microseconds minimum.

Bus

asserting

It
will
read
Block
0
(the
first
512
bytes)
selected
mass
storage
device
into
memory

BINIT

from
the
locations

000--777.

It will read location zero and if it is 240, it will 1load
Rl register with the CSR address of the booted device,
load RO register with the selected unit or drive number,
and jump to location zero.

the

contents

location

zero

260,

then

the

mass

storage device contains a "standalone program". Macro-ODT
interprets the contents of 1locations
2,
4,
and
6
as a
RADIX-50
encoded
six
character
file name.
Macro-ODT
assumes

that

the

mass

storage

structured

volume

and

volume

the

name

for

file

device

searches

provided

the

RT-11

directory

locations

file

the

and

6. When the file is found, the entire file is loaded into
contiguous
memory
starting
at
1location
zero.
The
RO
register is loaded with the number of the unit or drive
and the Rl register is loaded with the CSR address of the
booted

device.

contents

The

loaded
begins

with
the
execution.

contents

the

Stack

location

Pointer

and

contents

location

the

loaded

with

the

Program

(SP)

Counter

(PC)

40.

The

program

240

location

zero

not

260,

then

the device does not contain a valid boot block. The boot
command is aborted and the SBC-11/21 is initialized as if
a

power

occurred.

4.3.9

After

(ASCII

typing

octal

detail

number

the

will

in Chapter

4.4

130)

Diagnostics

letter
2.

"X",

3-second delay will occur,

displayed.

This

command

then an

described

INITIALIZATION

When it is desired to re-initialize the system without removing
power, enter 173000G from the console in response to the "@". Note
a

that

will

return

carriage

have

pause,

type

<CR>

provided

after

typed,

resynchronize the terminal as described in the following example.

Example:

4.5

@173000G

pause
a
After
resynchronize.

1least

WARNINGS AND PROGRAMMING

following

The

assist

the

4.5.1

user

warnings

one

HINTS

programming

and

in operating Macro-ODT.

second,

hints

are

Error Decoding

In the event of an unexpected appearance of "@", it is a good
practice to examine the word at 167774. This is an error word that
indicates the cause of entry to ODT. A HALT instruction, BREAK, or
an attempt to fetch from nonexistent memory will appear as 100000.

Other attempted bus transactions to nonexistent memory will appear
as 000200, or 000201 if accessed by the stack pointer R6.
4.5.2

While

ODT Stack Warning

performing

its

various

functions,

Macro-ODT

requires

two

words of user stack. It will transparently push and pop internal
information there. It is imperative then, that the user always
provide two more words than those actually necessary for the

proper execution of the application program. If desired, these two

words can be given back when the program is completely debugged
and operating within its own ROMs without ODT.

For proper program operation, R6 should always contain a valid
even RAM memory address. Failure to observe this rule will cause
unpredictable results.

4.5.3

Addresses to Avoid

Since the firmware uses the top of the SBC-11/21 on-board RAM as
its scratchpad, the user should not write to any address above
167642 unless specifically designated in this manual.

The vector at 140 governs the BREAK interrupt. Altering locations
140

and

142

could

result

the

1inability

suspend

program

execution.

4.5.4

CPU Priority

When the PSW is set to 340, the BREAK key will have no effect, and
will not invoke Macro-ODT. Running at a level 6 priority (PSW set
to 300) is adequate for most programming needs. This will disable
all

interrupts except

for BREAK.

4.5.5

Terminal

Macro-ODT
prompt.

Some

as
communication.

4.5.6

every

timeout,
Macro-ODT
will then print the
the

"@"

prompt.

4.5.7

typed

terminals

commands.

Spurious HALTs
last word of an

the

Problems

character

intelligent

characters

When

echoes

The

response

the

also

respond

control

results

instruction

may

all

include

zeros

and

"@"

1loss

causes

bus

will
interpret
it as a HALT
instruction.
It
contents of PC on the terminal, before issuing

Serial

I/O Protocol
operates
the
serial
line
interface
in full duplex
mode
and
each
character
is
echoed
by
the microprocessor
to
the
terminal.
Programmed
I/0
techniques
are
used
rather
than
interrupts.
When
the
Macro-ODT
firmware
is
busy
printing
a
multi-character message using the transmit side of the interface,
the
firmware
is
not
monitoring
the
receive
side
for
incoming
The

Macro-ODT

characters.

interface

Any

may

characters

set

the

coming

overrun

error

this

bit,

but.

time

the

are

lost.

Macro-ODT

The

does

not check
this bit and
those
characters
are
not
recognized.
All
peripherals
communicating
with
the
Macro-0DT
through
this

Interrupt
power-up,

(REVNT

other

observe

100)

vectors

this

Vector

Macro-ODT

and

are

the

protocol.

Initialization
initializes

BREAK

initialized

the

interrupt

and

[

4.5.8
Upon

must

interface

may

LTC

vector

contain

interrupt

(BKRQ

vector

at 140).
spurious data.

CHAPTER
SYSTEM

5.0

ARCHITECTURE

GENERAL

This

chapter

describes

the

architecture

the

microprocessor,

memory
organization
and
power
up method.
The microprocessor
architecture describes the
registers,
hardware stack,
interrupts
and DMA mechanism. The memory organization describes byte or word
addressing
and
memory
mapping.
The
power
up
procedure
and
initialization are also briefly described.
5.1
The

MICROPROCESSOR ARCHITECTURE
SBC-11/21
microprocessor
executes

subset

the

PDP-11

instruction
set.
It
has
eight,
high
speed,
general
purpose
registers that are used as accumulators,
address pointers,
index
registers and for other specialized functions. The microprocessor
executes

single
and
double
operand
instructions
wusing
either
16-bit
words
or
8-bit
bytes.
The
Direct
Memory
Access
(DMA)
function transfers data directly
from the LSI-11
bus
to the on

board

I/0

5.1.1

devices

and

memory,

while

the

program

continues

run.

Registers

With reference to Figure 5-1, the microprocessor contains a number
of
internal
registers
which are
used
for various
purposes.
The
registers are broken up into two groups:

General

Status

5.1.1.1
General
Registers
-The
microprocessor
contains
eight
16-bit general-purpose
registers
that
can
perform
a
variety
of

functions.
These
registers
can
serve
as
accumulators,
index
registers, autoincrement registers, autodecrement registers, or as
stack
pointers
for
temporary
storage
of
data.
Arithmetic
operations
from

one

memory

and

stack.

locations

Registers
(SP)

can

memory

performed

location
or

are

and

contains

the

from

one

device

dedicated.

location

serves

and contains the address
It
is normally used
for

general

and

another,

between

the

last

processor

another,

general

serves

(address)

the

Stack

Pointer

entry

Program

Counter

the

(PC)

of the next instruction to be executed.
addressing purposes only and
not
as an

accumulator.
5.1.1.2

contains

©Status

information

the

The

Processor

current

Status

processor

information includes the current processor priority,
codes
describing
the
arithmetic
or
logic
results

Word

(PSW)

status.

This

the
of

condition
the
last

instruction,
and an
indicator for detecting the execution of an
instruction to be trapped during program debugging. The PSW format
is
shown
in
Figure
5-1,
and
Table
5-1
1lists
status
word
bit
descriptions.

Certain

instructions

allow

programmed

manipulation

R1
R2

GENERAL REGISTERS
R3

R4
R5

STACK POINTER

PROGRAM COUNTER

MR-7204

PROCESSOR STATUS

PRIORITY
|

04
TRACE

TRAP

03
NEG

OVER

|ZERO FLOW CARRY

]

MR-7203

Figure 5-1
of

condition

Chapter

code

Registers and Processor Status Word

bits

and

storing

(moving)

the

processor status. Not all instructions affect the condition codes
in an obvious manner. For details of specific instructions refer
7.

Hardware Stack

5.1.2

The hardware stack is part of the basic design architecture of the
SBC-11/21. It is an area of memory set aside by the programmer or

by the operating system for temporary storage and linkage. It is
handled on a LIFO (last in/first out) basis, where items are
retrieved in the reverse of the order they were stored. The stack
starts at the highest location reserved for it (376 octal at power
up) and expands linearly downward to a lower address as items are
added

the

stack.

Table 5-1

Processor Status Word Bit Descriptions

Bit

Name

Description

15--8

N/A

These bits are not accessible
no
contain
and
programmer

to the
wvalid

information.

7--5

Priority

These bits define
level

set

the

the current priority

microprocessor

program

higher
and only interrupts with a
priority
are
recognized
by
the
microprocessor. Table 5-2 describes
the microprocessor interrupt levels as
functions of bits 5-7.

Trace

When

this

bit

allows

the

Condition Code N

This

bit

set

when

instruction

Condition

This

bit

set

when

1instruction

zero.

microprocessor to trap to locations 14
and
16
after
an
instruction
is
executed.
It
can
only
be
set
by
executing
an RTI
or RTT
instruction
with
the desired PSW already on the
stack.
The
trace
bit
1is
wuseful
in
debugging programs by allowing them to
be single stepped.

Code

causes

the

result

negative,.

Condition

Code V

This bit
1is set when an
instruction
causes an overflow condition.

Condition

Code

This bit
is set when
causes
a
carry
out
significant bit.

It is not necessary
which data is being
the

use

the

to keep track
stacked. This

Stack

Pointer

an
instruction
of
the
most

of the actual 1locations into
is done automatically through

(SP).

six

(R6)

always

contains the memory address where the last item is stored in the
stack.
Instructions
associated
with
subroutine
1linkage
and
interrupt service automatically use register six as the hardware
stack pointer. For this reason, R6 1is frequently referred to as
the system SP. The hardware stack is organized in full word units
only.

5.1.3

Interrupts

are

the

processor

service

processor

priority

requests,

the
only

made

peripheral

temporarily

suspend

requesting

device.

when

indicated

its

priority

PSW<7:5>,

its

devices,

present

which

device

can

execution
interrupt
the

higher

than

the

shown

Table

Fail

Every

and

The

priority

except

interrupt

HALT

vector

1is
is

associated

pair

with

words,

interrupts:

-HALT.

interrupt

vector.

processor

5-2.

SBC-11/21 supports a vectored interrupt structure with
four levels. In addition, it supports two nonmaskable

Power

cause

program

interrupt

(address
(priority
with
which the routine must be executed). Upon interrupt the current PC
and PSW are saved on the stack and the new PC and PSW are loaded
from the vector address.

that

device's

vectors

service

may

routine)

reside

and

the

first

PSW

256

memory

locations

(octal 374 is the highest vector location).
The vector address
provided by the
interrupting device
(external vector address)
generated internally by the microprocessor.
NOTE

The

Power

vector

Fail

address

interrupt
24,

HALT

uses

interrupt

associated with
PC
and
PSW

immediately
with

not

a vector. It pushes the
onto
the
stack
and
goes to the restart address

PSW

340.

Table

5-2

PSW

Interrupt

Levels

Microprocessor
Priority

Interrupt Levels
Acknowledged

PSW Bits
7
6
5

level

Unmaskable

1
1

1
0

level

level
level

4
0-3

7,6
7,6,5
7,6,5,4

Interrupt

is
or

The

SBC-11/21

has

eleven

interrupt

maskable and two are nonmaskable.

The

sources

which

nine

are

interrupt request can occur

at any time but is not acknowledged until the completion of the
current instruction. This allows the microprocessor to execute a
program until the interrupt occurs and then the microprocessor
vectors to the service routine for the interrupt. After the

service routine is completed, a Return From Interrupt (RTI)
instruction is executed. The microprocessor then pops the top two
words from the system stack, which were the original PC and PSW,
and the interrupted program is resumed.

The eleven interrupt sources with their respective priorities are

listed

in Table 5-3.

For a device to be serviced,

its priority

level must be higher than the current microprocessor level. When
two devices with equal priority numbers simultaneously request an
interrupt, the device listed closest to the top of the table will
be

serviced

first.

When the interrupt is requested by several LSI-11 bus devices
simultaneously, the device electrically nearest to the SBC-11/21
is

serviced

first.

DMA

5.2

(DIRECT MEMORY ACCESS)

DMA allows the programmer to implement block transfers by
specifying the direction of transfer, the starting address in

memory, the number of words and any additional parameters that a
particular external device requires. SBC-11/21 does not have an
on-board DMA interface, but can support DMA transfers for
external devices via the LSI-11 bus interface. A typical device
utilizing the DMA technique is the RX02 double-density floppy.
User designed devices can also be connected to the SBC-11/21 DMA
facility. For a more detailed treatment the reader is referred to
9.

Chapter

MEMORY ORGANIZATION

5.3

The SBC-11/21 memory consists of onboard memory and LSI-11 bus
memory. The memory map configurations and the types of onboard
memory

chips

described

are

Chapter

The

memory

maps

are

Addresses from 0 to 376 octal are
in Figure 5-2.
described
reserved for vector locations and addresses from 60 Kb to 64 Kb
are

reserved

for

I/0 devices.

The address space of the SBC-11/21 module is 64 Kbytes. A 16-bit
word is composed of two 8-bit bytes with bits 0--7 representing

the low byte and bits 8--15 representing the high byte. Words are
always addressed by even numbers. The bytes are addressed by
either even or odd numbers. The high bytes are stored in the odd
numbered
locations and the 1low bytes are stored in the even
numbered

locations.

MAP O

64 KB

(NOTE 3)

MAP 1

MAP 2

64 KB

(NOTE 3)

2 KB (NOTE 1)

(NOTE 3)

MAP 3

(NOTE 3)

4 KB LOCAL RAM
? KB LOCAL RAM
4 KB LOCAL RAM
4 KB LOCAL RAM
56 KB (NOTE 2)
56 KB NOTE 2 )
56 KB (NOTE 2)
56 KB (NOTE 2)

48 KB+

LSI-11 BUS

48 KB4

LSI-11 BUS

48 KBs

LSI-11 BUS

40 KB+

32 KB~

32 KBj

32 KB

24 KB4

24 KB+

24 KB4 16 KB SOCKET A

16 KB+

16 KB

8 KB SOCKET A

8 KB+

8 KB

8 KB4

16 KB SOCKET B

4 KB SOCKET A
8 KB SOCKET B

4 KB SOCKET B
O KB

O KB

0KB

0 KB-

NOTES:

1. SOCKET SET A IS MAPPED OVER SOCKET SET B AND IS
THEREFORE LIMITED TO USING EITHER SOCKET A OR

SOCKET B, BUT NOT BOTH TOGETHER.
2. ADDRESSES 160000 THROUGH 160007 ARE ASSUMED TO
RESIDE ON THE LSI-11 BUS.
3. THIS SECTION CONTAINS THE LOCAL I/0 ADDRESSES FOR
THE SLUs AND PPI. ALL UNASSIGNED ADDRESSES ARE
ASSUMED TO RESIDE ON THE LSI-11 BUS.
MR-6643

Figure

5-2

Memory
5-6

Maps

Table 5-3

SBC-11/21

Interrupts

Interrupt

Control

Priority

Vector

HALT

-CTMER

nonmaskable

POWER FAIL

-PFAIL

nonmaskable

LSI-11
Signal

Bus
BHALT

BKROQ

140

LSI-11
Signal

Bus
BEVNT

REVNT

100

Source

Signal

Level

Address*¥*

SLU2

REC

RDL?2

120

SLU2

XMIT

XDL2

124

PARALLEL

I/0

PBRQST

130

PARALLEL

I/0 A

PARQST

134

SLUl

REC

RDL1

SLU1

XMIT

XDL1

IRQ4

Read from
LSI-11 Bus

LSI-11
Signal

Bus
BIRQ4

*The microprocessor jumps directly to the restart
with a PSW priority level 7. (RESTART is loaded
and 340 into PSW).
**A1l

vectors

defined

this

table

are

internal

supplied
by
the microprocessor,
except
interrupt which is read from the bus.

5.4

POWER UP/DOWN FACILITY

SBC-11/21

has

facilities

for

assuring

for

address
into PC

vectors

the

automatlc

BIRQ4

program

start—up when power is turned on and for orderly shutdown, without
loss of data,
when power
is turned off or 1lost.
This
1is

accomplished by a combination of hardware

features and

software.

Hardware

features:

Two

signal

BPOK

signals
One

The

Battery

their

power

up,

and

detailed

the
for

LSI-11
power

usually generated
line

the

bus

LSI-11

called

up/down

the

bus,

BDCOK

protocol.

power

backup

interrupt

called

BINIT

the

SBC-11/21.

power

down

routines,

facility

and

These

supply.

system.

vectoring

programmer

found

only

which

connections

features:

store

The

the

Software

are

signal

resets

lines

wused

must

provide

addresses
at

location

description

Chapter

power

the

and

jumper

for

the

selected

power

down

up/down

start

address

and
for

routine.

protocol

will

CHAPTER

PROGRAMMING
6.0

The

two

INFORMATION

GENERAL

SBC-11/21

serial

programmable

operating

has

I/0

three

1lines.

on-board

These

features

that

characteristics.

interfaces,

interfaces

allow

This

the

chapter

one

parallel

contain

user

explains

I/0

number

change

how

this

and

their

can

accomplished.
SBC-11/21

1is

also

equipped

with

hardware

that

enables

the

microprocessor to behave in a controlled manner when the power 1is
turned on and off. This specialized hardware requires software to
make it work and an example in Appendix C describes the basic
principles

this

programming.

ASYNCHRONOUS SERIAL LINE UNITS

6.1

The two Serial Line Units (SLUs) are described by Figure 6-1 and
provide the means of transferring data between the microprocessor
and two user connectors Jl or J2. The user interfaces support the
RS232C EIA standard and RS423 protocol, at baud rates ranging from
300

Each

38400.

SLU

with

equipped

four

addressable

that

registers

are

listed in Table 6-1, described by Figure 6-2, and functionally
described by Tables 6-2, 6-3, 6-4, and 6-5. The registers can be
accessed by the microprocessor or any DMA bus master. SLUl, with
the proper software handling, can be used as a system console and
initiating a hardware interrupt when BREAK is
is capable of
detected.

SBC-11/21

can

configured

for

the

BREAK

cause

level 7 interrupt with an internal vector of 140, enable the BHALT
SLUZ2
interrupt or request a HALT trap to the restart address.

provides three line time clocks at 50 Hz, 60 Hz and 800 Hz, which
can be wire-jumper configured to enable the BEVNT level 6
Refer to Chapter 2 for details on how to configure the
interrupt.
SLUs.

Table 6-1

RCSR

- Serial Line Unit Register Addresses

Description
Receiver Control and Status

Address
177560

AD2

AD1

RDBR

Receiver Data Buffer

177562

TDBR

Transmitter Data Buffer

177566

TCSR

SLU2

RCSR

Transmitter Control and Status

Receiver Control and Status

177564

176540

RDBR

Receiver Data Buffer

176542

TDBR

Transmitter Data Buffer

176546

TCSR

Transmitter Control and Status

176544

J1 OR J2
RCSR

RECEIVER

CONTROL AND
STATUS

MICROPROCESSOR BUS

RDBR

RECEIVER

DATA BUFFER

RDAT H

RECEIVER

GND

TCSR
TRANSMITTER

CONTROL AND
STATUS
A

TDBR

TRANSMITTER
DATA BUFFER

XDAT L

TRANSMITTER

GND

MR-7207

Figure

6-1

Serial

Line
6-2

Unit

Interface

(SLU)

Receiver Control and Status Bit Descriptions

Table 6-2
Bit

Name

Direction

12-15

Not

Read

Receiver

Read

Function
Reserved for future use.

Only

Used

This bit is set to a

Oonly

Active

Read

08-10

Not

Used

Only

Receiver

Read

This
the

into

Read
Write

Receiver
Interrupt

Enable

on power-up.

"zero"

Reserved for future use.

Only

Done

by the

"one"

cleared

stop bit at the end
It is also cleared

"zero" by the
of each byte,.
to

and

bit

start

the

set

bit

received

byte

cleared

"zero"

Data

Buffer

This

bit

set

read.

the

when

"zero"

transferred

Buffer.

RCV Data

cleared

when

"one"

1is

RCV

also

on power-up.

under

"one"

it
When set,
control.
program
allows an Interrupt Request to be
initiated whenever the Receiver
It is cleared to
Done bit is set.
a

"zero"

RESET,

power—-up

to
Refer
control.
program
under
Jjumper
interrupt
2 for
Chapter
configuration.

Read
Only

Not
Used

00-05

Reserved

6.1.1
Data Baud Rates
The serial line units transmit
by character. Each
bits
of
data,
and

receiver
cannot
Power

rate

and

defaults

for

external

RESET,

receive

character consists of
the
stop
bit.
Split

transmitter

supply

for

300.

the

baud

outputs

SLU

future

data

use,

serially

bit

and

ten bits; a start bit, 8
speed
operation
of
the

not

supported

rate

clock

are

disabled

the
and

and
SLU.

later

the

user

During
the

baud

The

baud
rates
9600,
19200 or

Status

are

selected

These

four

sensitive,

programmable

38400

when

(TCSR)

for

300,

bit

the

set

one.

programming

bits

05--03

bits

used

for

the

not

latch.

and

TTL

levels

times

the

baud

rate

the

baud

selected

bit
the

for

rate

its

2400,

4800,

Control

baud

rate

and
then

TCSR.

selection

the

reset
SLU.

that

1200,

The

Therefore,

of the TCSR must use bit set and
the
baud
rate
is
written
1into
output

600,

Transmitter

are

software

1level
control

type instructions after
Each
SLU
provides
an

connector

(J1

J2)

SLU.

RECEIVER CONTROL AND STATUS REGISTER
15

RCV

act|

@ | O

Rcv | RV

|ponel IE

SLU 1 ADDRESS 177560
SLU 2 ADDRESS 176540

RECEIVER DATA BUFFER REGISTER
15

ERR

ERR | ERR

REC

BRK

03
T

lRECEIIVED D:‘\TA BlIJFFEFil

SLU 1 ADDRESS 177562
SLU 2 ADDRESS 176542

TRANSMITTER CONTROL AND STATUS REGISTER
5

cjo0ojojpofo

xwiT | xvit|{eBr

|rov |ie

| pPBR | PBR

PBR | XMT

|seL2|seLt]seLo MAINT| eng | BRK

SLU 1 ADDRESS 177564
SLU 2 ADDRESS 176544

TRANSMITTER
DATA BUFFER REGISTER
15

04
T

03
T

02
T

]

TRANSMIT
DATA BUFFER
|

SLU 1 ADDRESS 177566

SLU 2 ADDRESS 176546
MR-7208

Figure

6-2

Serial

Line
6-4

Unit

Bit

Maps

Table

Bit

Name

Error

6-3

Receiver
Direction

Buffer

Bit

Descriptions

Function

Read

Only

Data

Overrun

Read

Error

Only

The bit is set to a "one" when the
Overrun Error or the Framing Error
bit is set.
It
is cleared to a
"zero"
when
the
error
producing
condition is removed.

The bit is set to a "one" when the
received byte is transferred into
the RCV Data Buffer before the RCV

DONE bit is cleared.
The Overrun
Error indicates that the previous
byte
in
the RCV Data
Buffer was
not cleared prior to receiving a
new byte.
The bit is updated when
a byte is transferred into the RCV
Data
Buffer
and
cleared
to
a
"zero" on power-up.
13

Framing

Read

Error

Only

The bit is set to a "one" when the
received character does not have a
valid stop bit and is transferred
into the RCV Data Buffer.
The bit
is
cleared
to
a
"zero"
when
a

character with a valid stop bit is
received and
1is transferred
into
the
RCV
Data
Buffer
or
on
power—-up.

Not

Read

Used

Only

Received

Read

Break

Only

Reserved

for

future

use.

The bit is set to a "one" when the
received signal goes from a MARK
to a SPACE and stays in the SPACE
condition for 11 bit times after

The
serial reception starts.
is cleared to a "zero" when
returns to
received signal

MARK condition or
08-10

00-07

Not

Read

Used

Only

Received

Read

Data

Only

Buffer

Reserved

These

recent

are

6-5

for

cleared

on power-up.

future

bits
byte

use.

the

most

These

bits

represent

received.
to

bit
the
the

"zero"

power-up.

Table

6-4

Transmitter Control and Status Bit Description

Bit

Name

Direction

08-15

Not

Read

Used

Only

Transmitter
Ready

Read

Only

Function

Reserved

Transmitter

Read

Interrupt

Write

Enable

This

Programmable
Baud Rate
Select

use.

bit

"one"

set

power-up.

"one"

under

it
set,
When
control.
program
allows an Interrupt Request to be
initiated whenever the Transmitter
1is
bit
The
1is set.
Ready bit
cleared
power—-up

03-05

future

The bit is set to a "one" when the
ready
to
XMIT
DATA
BUFFER
is
The bit is cleared
accept a byte.
to a
"zero"
by writing
into the
XMIT DATA BUFFER.
The bit is also
set

for

Read
Write

to
a
"zero"
by RESET,
or under program cohtrol.

The

condition

these

bits

BAUD RATE

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

300
600
1200
2400
4800
9600
19200
38400

bits

selects
the
baud
rate
under
program
control,
provided
the
Programmable
Baud
Rate
Select
The baud rates
Enable bit is set.
these
setting
are
selectable
by
follows.

Baud
Programmable
the
Wwhen
Select Enable bit is not set
rate defaults to 300.

Rate
baud

Table
Bit

6-4

Transmitter Control and Status Bit Description (Cont)
Direction

Name

The

transmitter

Select

and

Function
NOTE

Programmable

Enable

bits

Baud

are

Rate

1level

This
1latched.
not
and
sensitive
the
of
requires that software in control
clear
and
set
bit
use
must
TCSR
instructions to access the TCSR once the
baud rate has been written into the SLU.
02

Mainte nance

Read

Write

set

When

program.

controlled

bit

This

llone |

the
the

is
output
serial
transmitter
connected to the receiver serial
input and disconnects the external
This bit is cleared
serial input.

to
or
01

Programmable

Baud Rate

Enable

a "zero" by INIT,
the program.

power-up,

Read

Write

This bit is controlled
by the
When set to a "“one",
program.
bits 03-05 are used to determine
the

baud

rate.

baud

"zero"

the

baud.
"zero"

This bit
by INIT,

When

rate

cleared

will

300

is cleared to a
the
power—-up or

program,

Transmit

Break

Read

Write

This

bit

controlled

Bit

Descriptions

the

program.
When set to a "one", the
serial output is forced
into the
SPACE
condition.
This bit
is
cleared by INIT, power-up or the
program,

Table

6-5

Transmitter

Bit

Name

Direction

08-15

Not

Read

Used

Only

00-07

Transmit

Read

Data

Write

Buffer

Data

Buffer

Function

Reserved

for

These

bits

data
These

byte
to
be
bits
are

power-up.

6-7

future

use.

represent

the

transmitted.
cleared
by

should

autobaud

noted

feature

that

terminal's

baud

feature

operating

6.1.2

Each

the

Macro-ODT

option

only

when

Macro-ODT

provides
to

both

request

Receiver

service

from

running

Interrupt

the

with

the

to
the
autobaud

the

Transmitter

Interrupt

Enable

level

higher

(RCSR)

(bit

set

higher

interrupt

priority

06)

system.

6.2

Table

Control

and

level

than

SLUl

Status

which

has

receiver

has

Within

each

unit

the

transmitter.

SLUl

uses

vector

for the receiver and 64 for
receiver
and
124
for
the
summarized

The

independently enabled by
is enabled when the RCV

Receiver

priority,

priority.

the

microprocessor.

one.

interrupt

than

the

and

on-board

Receiver and Transmitter requests can be
software.
The Receiver
Interrupt
request

equipped

Interrupts

SLU

Interrupt

SLU2

that
enables
SLUl
to
adjust
itself
rate
between
300
and
9600
baud.
The

address

the transmitter. SLU2 uses 120 for
transmitter.
These
relationships

60
the
are

5-3.

PROGRAMMING

THE

PARALLEL

I/O

INTERFACE

The parallel I/0 interface, described by Figure 6-3,
provides
means of transferring data between the microprocessor bus and

the

the
user
interface connector J3.
The
interface
is equipped with four
addressable registers for data and control which are summarized in
Table 6-6.

Table

6-6

Parallel

the

user

and

control.

Address

Addresses

Status

Port

176200

Read/Write

176202

Read/Write

Port

Word

registers

interface.
The

Port

Control

Port

I/0

control

of
the
Parallel
programmability to

are

176204

Read/Write

176206

Write

used

only

for

Port

used

for

word

data

Only

transfer

both,

data

and

from

transfer

and

used

exclusively

1I/0
interface.
this register.

The

interface

to
for

control

owes

its

In addition to software programming, the parallel interface
also be programmed by hardware. This is covered in Chapter 2.

can

CONTROL
»

PCO

WORD

INTERRUPTS

PC3

176206
USER CONNECTOR

I—_ 74@44j
NG

]

)

PC2,,,

PC3

ORTC

| N

PC4

M61
—nn—-l—<
}

PC5 M63

~ |

PROCESSOR BUS

PCO

|
|

176204

PORT A

'”

176200

GND

§ H' TM (8 LINES)

M60 M59

I DIR

—0---0—

PORT B

A DATA

§ ||

(8 LINES)
B DATA

176202

DELAY

l NETWORK I

M66

0---0

M65

+3VDC

MR-7209

Figure

6-3

Parallel

6-9

I/0

Interface

6.2.1

The

How To

parallel

understanding

effort.
I/0

easier.

The

its

very

subset

make

contents

aid

the

1is

The

efficient
these

the

task

shown

this

section

examining

the

flowchart

complex

will

use

and

require

can

thorough

considerable

made

capabilities.

This

section

Manual

quite

capabilities

flowchart

the

Section

interface

all

However,
using

organized

After

Use This

1I/0

finding

Fiqgure

and

the

6-4

few

the

needed

provides

minutes

parallel
has

been

information

overview

reviewing

will

user.

position
to
?hapter
or

decide

whether

specific

interest.
If this is the
directly to that section.

the

read

1I/0

case,

how the

data

system

The modes
is

are

designated

through

will

detail

three

bits

setting

software

routed

the

rest

better

this

configuration
is
of
immediate
the reader is encouraged to refer

Modes of Operation
6.2.2
The
interface ports can operate

selected

reader

as Mode

ports A and

basic

modes

the

that

Control

and

are

Word

and

define

the

port

controls

NOTE

If the bidirectional buffers are being
hardwired, care must be taken to insure
that the wired direction conforms to the
programmed

directions

ports

and

This is necessary to avoid driver output
to driver output
connections,
which
could damage the integrated circuits.

Port

6.2.2.1

assignments

bit

The

for

interface

control

handshake

This

ports A and B.

the

bits

8255A-5

provides

and

the

set/reset

are

the handshake

output
using

connector.

the

Control

The

Word

register which is described in the Control Word section. The port
1in the
be described
C condition for the various modes will
those modes.

sections dealing

with

Basic

6.2.2.2

Mode

Input/Output

This

mode

provides

simple

input and output of either port A or port B or both as described
is simply read from the port

if programmed

bidirectional

in Table 6-7.

The data

no handshaking

requirements.

as an input or written to the port if programmed as an output with
The port A and port

buffers may be hardwired as described in Chapter 2. They may also

be program controlled by port C bits 4 and 6 if dynamic change of
In this mode the outputs are
the port direction is desired.
latched

6.2.2.3

but

the

Port

port A and B

Table 6-8.

and

are

not.

Registers

registers are shown

These

The

bit

assignments

for

in Figure 6-5 and described

the

registers are used as data buffers for all modes

operation.

o)}

inputs

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Table

6-7

Mode

Configuration

PPI

Act

Element

Act

Input

Direction

Ouput

via

Port

M66

M65

M66

M60

M66

M64

M63

Port

M59

M65

M59

M60

M59

M64

M63

PC7

Never

PC6

M64

PC5

Never

PC4

M63

Input

Always

M62
an

Never

Input

Always

M61

Never

Control

Output

External

Output

PC3

Never

Input

Interrupt

(Vector
Always

PC2

Always

PCl

Never

Input

Always

PCO

Never

Input

Interrupt

Input

Never

Output
Output

(Vector
Always

134)

Output

130)
an

Output

UNDEFINED
]

PORT DATA
MR-7211

Mode 0,

Figure 6-5

Port A or B, Bit Assignments

Mode 0 Port A or B Bit Descriptions

Table 6-8
Bit

Name

Direction

Function

8-15

Undefined

Not

0-7

Port Data

Read/Write

Data to output or

valid
the

entire

read

performed

word.

read,
depending
direction.

input data to be
on

the

port

6.2.2.4

Port

Mode
0
-Ports
A
and
B
use
no
of
port
C
1lines
can
be
used
as
Input/Output data lines.
The bit assignments are shown in Figure
6—§ and described
in Table 6-9.
When PCO
and PC3 lines are not
being used as interrupt requests,
these bits should be cleared by
the Control Word to prevent erroneous interrupts.

handshaking

signals

and

some

IUNDEF'NEDI

/o | 1o | vo [ 1o

[NoT | IN_

[NOT

|NOT

pc7 | Pce | pcs | Pca | USED Lg; USED | USED
MR-7212

Figure

Table

6-6

6-9

Mode

Port

Bit

Name

Direction

Function

8-15

Undefined

Not

Assignments

Descriptions

wvalid

the

PC7

Read/Write*

Output

PC6

Read/Write*

entire
bit.

Port

input

and

read

performed

word.
Drives

the

Upper

1is

M64

LED
defined

connected

M62

then it
C Upper

is an input bit.
1If Port
is defined as output and
connected to M66 (M59) then
output
which
controls
the
direction for Port A
(Port

M64 is
it
is
buffer

B).
A
"1"
input and a
5

PC5

Read/Write*

Same

PC4

Read/Write*

1If

PC7.

Port

sets
the
buffer
"0" for output.
No

LED.

Upper

input and M63
then it is an

1is

A).
input

PC3

Not

PC2

Read

0-1

PCO-PC1l

Not

*Bit

written

explained

the

used
Only

used

using

Control

the
Word

Not

defined

as
output
and
M59
(M66) then

output
which
direction for

controls
the
Port B
(Port

A
"1"
sets
the
buffer
and a "0" for output.

for

wvalid.

Input

Not

1is

is connected to M6l
input bit.
If Port

C
Upper
is defined
M63 is connected to
buffer

for

bit.

valid.

Control

Word

section.

6-13

bit

set/reset

function

6.2.2.5
on

Mode

port

control

(Strobed

generate

the

Input/Output)

transfer

signals

from

data

through

0--3

(lower

nibble)

are

used

4--7

(upper

qibble)

are

used

with

In
the

ports

conjunction
port

node,

user

interface

and

with

These

defined

Table

6-11

and

usable

are

described

Flna{ly,

Table

degcribes

configurations

Figure

6-7
and
operation

links

Chapter

tabulated
in
Table
of
mode
1
to
the

1/0 | 1/0

|IBFA

known

UNDEFINED
]

IBFB
I

10
1

(STBB)

OBFB
INTEB
(ACKB)

INTEA
(ACKA)

A AND B BOTH OUTPUTS

INTRA

1/0

OBFA

INTRB

INTEB

INTEA

6-12.
jumper

INTRA

(STBA)

are

]

bits

ports A
in mode

UNDEFINED

]

bits

and

the four input/output combinations of
1. The port C bit assignments as used

A AND B BOTH INPUTS

6-10.

port

which
C

of
the
signals

discussed

Port

lines

details
control

§—13

]

mode

signals

as
"handshaking"
signals.
Before
describing
the
handshaking protocol, the basic functions of these
are

the

this

INTRB
MR-7213

Figure

6.2.2.6

Mode

implements

6-7

Mode

(Strobed

means

Port

Bit

Bidirectional

communication

with

Assignments

1I/0)

user

This

device

mode

over

single 8-bit bus for both transmitting and receiving data.
Handshaking and interrupt signals are used in a manner similar to

mode

This mode is used with port A only and five control lines on port

C. Both inputs and outputs are latched. When port A is operating

in this mode, the port B bidirectional buffers cannot be operated
under program control since PC4 and PC6 are being used. Port B can
still operate in either mode 0 or mode 1, but the buffers must be
hardwired. PCO--PC2 are defined by port B usage for mode 1 and are
available as I/0 lines when port B is

in mode 0.

Table

6-10

Abbrev/Port C Bit

Signal
Strobe

-STBA/PC4

Input

in Mode 1

Port C Control Signals

—STBB/PCZ

Function

A low on this input
the
into
user data

1loads
input

latch.

Input

Buffer

Full

Interrupt Request
(Input Mode)

IBFA/PC5
IBFB/PCI

INTRA/PC3
INTRB/PCO

output
this
on
high
A
acknowledges that the data
the
into
1loaded
been
has
input latch. Set by STB and
program
the
by
reset
reading the input latch.

A high on this output can
interrupt the CPU when an

input

data

Interrupt Enable
(Input Mode)

INTEA/PC4
INTEB/PCZ

device

into

the

strobes

port.

setting

Enables
and

INTR_.

This

output

input

being

its

INTR

Program

controlled %y PC4 or PC2.

Output Buffer Full

Acknowledge

Input

-OBFA/PC7
-OBFB/PCl

- ACKA/PCG
-ACKB/PCZ

(Output

Request

Mode)

INTRA/PC3
INTRB/PCO

1low

low.

A low on this input tells
the
that
processor
the
user's device accepted the
data

Interrupt

goes

interface
user
the
tell
that CPU has written data
to the port. Reset by ACK

from

A or

A high on this output can
interrupt the CPU when an
output device has accepted
data
transmitted
by
the
CPU. Set by ACK. Reset when
new data is written to the
port.

Interrupt Enable
(Output Mode)

INTEA/PC6
INTEB/PCZ

Enables
Program
or

PC2.

INTR.
setting of
by PC6
controlled

Table

6-11
Port

Port

C Bit
Functions

Port

STBA

PC4

STBB

Combinations
A

Input

with

Port

Mode
A

Output

with
B

Input

Output

Input

N/A

PC4

N/A

PC2

N/A

PC2

IBFA

PC5

N/A

PC5

IBFB

N/A

PC1

N/A

PC1l

INTRA

PC3

INTRB

PCO

OBFA

N/A

PC7

N/A

OBFB

PC1

N/A

PCl

N/A

ACKA

N/A

PC6

N/A

ACKB

PC2

N/A

PC2

N/A

PC5

N/A

PC4

N/A

PC6,7

H O

Port

OO
= O

Output

Ports

HOMORF
X

Ports

Port

outputs

PC7
(Controls

Port

inputs

N/A

Word

(Direction

PC0-3)

(Direction

Port

(Mode

D3
D4

(Direction
(Direction

Port

PC4-7)

Port

A Mode

Port

Mode

set

Mode
enable

Control

FOHMHOK
O X

Other

LED)

HO R

Other

Table

6-12

Mode

Port C

Bit Descriptions

Bit

Name

Direction

Function

8-15

Undefined

Not wvalid
if a read
on the entire word.

PC7

Read/Write*

Port

A Mode

Port

4-7,

OBFA

Read

Only

bits

performed

Input:
defined

output this bit
and controls the
the LED on and a

is an output bit
A "0" turns
LED.
"1" turns it off.

Unused

input

Port

OBFA
data

PORT

bits

A Mode

Output:

goes
low
been
has

output

4-7

defined

to
1indicate
that
the
1into
written

buffer

the

processor.

This
bit
1is
set
when
the
ACKA
input goes 1low
(PC6, M64 to M62)
external
the
that
indicating
output
the
device has accepted
data.
OBFA is present on PC7 to
the external device.
6

PC6

Read/Write*

Port A Mode

Input:

as
defined
4-7
bits
C
Port
If
M62
to
connected
is
input and M64
If Port
then it is an input bit.
C bits 4-7 defined as output and
M59 is connected to M64 it 1is an
output which controls the buffer
A "1" sets
direction for Port B.
"O"
input and a
the buffer for
sets

INTEA

Read/Write*

the

buffer

Port A Mode

INTEA

for

set

when

output.

Output:

INTRA

enables

when
SBC-11/21
the
interrupt
output data has been accepted by
the external device.
ACKA

When

M64

external
receipt

connected

signal

data

M62,

acknowledging

acts

INTEA.

the

Table

6-12

Mode

Port

Bit Descriptions

Bit

Name

Direction

Function

IBFA

Read

Only

Port

IBFA

A Mode

indicates

has

been

set

M61)

Input:

that

latched

the

low

the

for

STBA

being

(Cont)

data
It

(PC4,

M63

reset

the

input

and

input

Port

processor
reading
the
port data.
This signal
is present on PC5
to
the external ldevice.
PC5

Read/Write*

Port

A Mode

Output:

If Port C Upper defined as output
then it is an output bit.
If Port
C
Upper
defined
as
input
it
1is

unused.
4

INTEA

Read/Write*

Port

INTEA

A Mode

set

interrupt
the input
PC4

Read/Write*

Port

output

then

INTRA

Read

Only

bits

and

M59

this

input

4-7
is

1is

output

direction

"0"

sets

bits

4-7

M63

interpreted
strobe).

connected

input

bit

and

STBA

(input

sets

M61

A Mode

then

indicates

that

data.

STBA

(PC4,

M63

"1"
IIOII

and
.

Input:

input

INTRA

and

for

valid

low

the Port
the buffer

input

processor

which

"1"

pulsed

as
M63

defined

"1"

and

Port

defined

connected

Port

whenever

full.

output.

INTRA

Output:

bit

the

allow

SBC-11/21

buffer

buffer.

for

Input:

will

the

A Mode

controls

and

It
to

1is

reading

Port

has

set

M61)

being

reset
the

Port

the

data.

enabled

INTEA

being

disabled

INTEA

being

Table

Bit

Name

6-12

Mode

Port

Direction

Bit

Descriptions

(Cont)

Function
If

Port

A Mode

"1"

indicates

ready

Output:
that

set

new
ACKA

Port

output data.
(PC6,
M64
to

M62) being pulsed low and reset by
the
processor
writing
new output
data
to
disabled
When

the

port.

enabled

processor

INTEB

IBFB

Read/Write*

Read

Only

INTEB

INTRA

interrupts

has

vector

and

This signal
the external
2

when

Mode

IBFB

also

set

the

an
on

will

and

INTRB

PC3.
to

request

Input:

Port B
the STBB

is set by
and
is
reset

the
134.

output

allow

input

for

line

SBC-11/21

indicates

latched

device

interrupt
service.
Port

Enabled

above.

data

has

when a "1".
(PC2) being

been
It
low

by
the
processor
reading
the
port
data.
This
signal
is
present on PCl
to
the
external device.

OBFB

Read

Only

Port

Mode

Output:

goes

low

indicate

processor

has

written

OBFB

port.
(PC2)

This

bit

that

data

set

going
1low
indicatinig
external
device
has
accepted

output

data.

This

present

device.

PCl

signal

the

ACKB
the
the
1is

external

Table

Bit

Mode

6-12

Name

Direction

INTRB

Read

Port C

Only

Bit Descriptions

Function
If Port B Mode

(Cont)

Input:

A "1"
indicates Port B has valid
input data.
It
is
set
by STBB
(PC2 being pulsed low and is reset
by the processor reading the port
data.
INTRB is enabled when INTEB
is

"1"

and

Port

disabled

when

1is

IlO!I.

Mode

Output:

A "1" indicates the port is ready
to accept new output data.
It is
set by ACKB (PC2) being pulsed low
and reset by the processor writing
new

output
data
to
the
port.
Enabled and disabled as above,.

This signal
is also an output
the external device on PCO.

*Bit

written

described

the

using

Control

the
Word

Control

Word

Bit

set/reset

section.
NOTE

is asserted
low and
a
read or
write access is made to the port by the
processor before an ACK strobe is sent
by the external device, the OBF line for
the accessed port will negate during the
assertion of the read or write to the
port and become reasserted when the read
or write operation is complete.
If

OBF

function

Table

6-13

Mode

Configuration

PPI

Input

Output

Element

Conditions

Program

Conditions

via

Port

M66

M65

M66

M60

N/A

Port

M59

M65

M59

M60

M59

PC7

Never

Input

Output

Buffer

Control

Port

M64

port

M63

Full
PC6

M62

to M64
(Acknowledge

PC5

Never

an
External

A)*

Input

Output

Buffer

Full

PC4

M61

M63

(Strobe
PC3

Never

an
External

Input

Interrupt

(Vector
PC2

Strobe

B
Input

PC1l

Never

Buffer

Never

*User's

hardware

Control

signals

assignments

Input

are

used

Table

mode

the

jumper

6.2.3
The

Control

interface.

Input

acknowledges

tabulated
2

the

functions

and

determined

bit.

B
130)

receipt

data

Table

output

6-14.

the
the

discussed

The

port

bit

by
Figure
6-8
and
links
operation of
in

Chapter

Output

(Vector

configurations

bit
7
is
register
determines
the
direction of
the
ports.
contents

Interrupt

defined

The

Full

Input

in mode
2
are
described
6-15.
Finally,
Table 6-16

Word

Output

Mode

PCO

134)

Mode.

Acknowledge
Output

Output

controls
the operation of
the
parallel
set
(active
high),
the
contents
of
the
mode
of
operation
and
the
Input/Output
If
bit 7
is
cleared
(active
1low),
the
will

set/reset

bits

state

(active

6-21

are

the

Port

described

high

bits.

6-17,

active

Table
low)

the

UNDEFINED

2
INTEA

INTEA 1

(ACKA)

Figure 6-8

Table

6-14

Signal
Request

(STBA)

Mode 2 Port C Bit Assignments

Port

Abbrev/Port

Interrupt

INTRA

IBFA

OBFA

Control

Signals

Function

INTRA/PC3

Bit

high

in Mode

output

interrupt
input
tions.
Output

Buffer

Full

Acknowledge

01 _ 00

]

OBFA/PC7

ACKA/PCS

This

this

the

and

CPU

for

output

goes

can

both

opera-

1low

indicate
that
the
CPU
written data to port A.

has

A low on this input
the output tristate

buffers

out

port

send

enables

the

data. Otherwise that buffer
is
in
the
high
impedance
state.

Interrupt

Enable

INTEAl/PC6

Enables

INTR

when

true.
Controlled
set/reset of PC6.
Strobe

Input

Buffer

Full

OBF
by

is
bit

STBA/PC4

A low on
data into

this
input 1loads
the input latch.

IBFA/PCS

A
high
on
this
output
indicates
that
data
has
been loaded into the input
latch.

Interrupt

Enable

INTEA2/PC4

Enables
INTR
when
true.
Controlled
set/reset of PCA4.

IBF
1is
by
bit

Table

6-15

Mode

Port

Bit

Name

Direction

Function

Undefined

Not
the

OBFA

Read

Descriptions

wvalid.
If
a
entire word.

read

done

Will go low to indicate that the
processor has written output data
to the port.
It is set when ACKA

Only

(PC6
M64
to
M62)
goes
low
indicating the external device has
accepted the data.
This signal is
output
device.

PC7

the

external

INTEAl

Read/Write*

When this bit is set it allows an
interrupt
INTRA
when
the
output
buffer
is
ready
to
accept
new
data.

IBFA

Read

IBFA indicates that input data has
been latched when a "1".
This bit
is reset when the processor reads

Only

the

input

output

data.

This

PC5

the

signal

external

device.
INTEA2

Read/Write*

When

this bit is
interrupt
INTRA

buffer
INTRA

Read

when

These
mode

PC3

bits

are

the

defined

selection.

NOTE

using

Port

in mode
2
operation
the software must clear the input buffer
of Port A if the input buffer full flag
(IBFA)
is
set
before
it
performs
the
read during an intended write to ensure
that the handshake lines and port flags
are

not

set

out

input

A high on this bit indicates that
the port is requesting service of
the
processor.
This
signal
1is

Only

output

When

allows

the

full.

device.
PCO-PC2

set

sequence.

external

Port

Table

6-16

Mode

Output

Input

PPI

Configuration

Conditions

Element

Conditions

Port A

Bidirectional

Port B

Hardwired

PC7

Never

PC6

Acknowledge A

Never

PC5

Never

Input

Buffer A Full

PC4

Strobe A

Never

PC3

Never

PC2

Always

PC1

Never

Input

Always

Output

PCO

Never

Input

Always

Output

Table

6-17

(M61

Unused

Always

Port

A Mode

Port

A Mode

Port

input

Port

bits

Port

Mode

Port

input

Port

bit

to M63)

Never

Mod e

Set

M64

only

Output

(Vector

134)

Output

Selection

Bit

M62

Buffer A Full

Interrupt

Input

Control

8-15

Output

Input

Hardwired

only

Input

Bit

M66

Input

Bit

bus

Bit

Functions

Reset

Unused
set

Always

set

Port

mode

Port

Mode

Port

output

Port

4--7

are

Port

Mode

Port

output

Port

bits

and

input

are

inputs

outputs

and

6.2.3.1
Mode
Selection -- The
user
determines
the mode of
operation for the ports and defines them as inputs, outputs or
bidirectional.
The user then must insure that the bidirectional
buffers are configured
(See Chapter 2)
to match the software
requirements.
Table 6-18 1l1lists all the control words available
for the Control Word register.
The user selects the control word
that matches the requirements and loads it into the register.
The
register is defined as "write only" and any attempts to read the
register

results

erroneous

data.

6.2.3.2
Setting Bits in Port C -also used to set or reset the Port
word bit functions are described in

Table 6-18

Port
Mode

A
0

Port
Mode

A
1

Port

Mode
IN

Mode
ouT

Mode
IN

Mode
ouT

233

231

237

235

233

221

227

225

213

211

217

215

203

201

207

205

273

271

277

275

263

261

267

265

253

251

257

255

243

241

247

245

3X3

3X1

3X7

3X5

Port

PC4,PC6

Port

PC5,PC7

INPUT
OUTPUT

INPUT

ouTPUT

INPUT

OUT

Port

OUT

Port A
Mode

Control Words for Mode Selection

Port A
Mode

The control word register is
C register bits. The control
Table 6-19. To set a bit the

Don't

Unavailable,

care

Used

condition

for

handshaking

OUTPUT

Table

6-19

Control

Bit

Function

8-15

Not

Always

6,5,4

Not

3,2,1

These

bits

reset

PCO

02
0

0
1

1
1

0
0

PC6

PC7

bit

The
B

the

set

bit

that

set

cleared

PC2

loaded

PC3
PC4

set

the

bit

with

and

bit

selected

bit

set.

bit

set/reset

interrupts

disable

Table
Mode

Port

enable

the

being
and

select

cleared.

Functions

follows.

reset

Port

Bit

reset

Bit

This

Set/Reset

used

PC5

number

Bit

used

PC1l

6-20

for

the

selected
Port

cleared,
To

can

the

1--3

equal

the

same

bit,

bit

used

SBC-11/21.

interrupts

Interrupt

Direction

bits

reset

are

bit

enable
The

listed

Set/Reset

control

Table

Control

the
0

bit

would

disable

the

words

used

6-20.

Words

INTRA

INTRB

Enable

Disable

Enable

Disable

Input

011

010

005

004

Output

015

014

005

004

Input

011

010

None*

Output

015

014

None*

*Port

does

not

function

the

bidirectional

Mode

6.2.4
During
C data

Parallel I/0 Initialization
Power up or the execution of a RESET instruction, the Port
lines are driven high and the LED (driven by bit 7 of port
C)
is turned off.
If
Ports A and B bidirectional
buffers are
hardwired, the directions are not altered and the data lines are
driven high if the buffer is configured as an output.
If Ports A
and B bidirectional buffers are program controlled by Port C, the
data lines will go to the input state.

6.2.5

Parallel I/0 Handshaking
I/O can operate in either mode 0, 1 or 2 to transfer
data into or out of the SBC-11/21. The mode 0 data transfers do
not require any handshaking control signals. The mode 0 input data
The

Parallel

not

latched

the

same

output

362

data

nsec

and

time
is

after

data

should

the

read

latched
the

available

strobe

and

data

trailing

edge

enables
is

valid

the

8255A-5.

the

WRITE

I/0

connector
The

I/0O

mode

connector

strobe

the

The handshaking signals which pass across the user interface are
detailed
as
follows.
Mode
1
operation
requires
the handshaking
control signals and these are dependent upon defining the ports as

inputs or outputs. Mode 1 input signals are listed in Table 6-21
and the handshaking function is shown in Figure 6-9. Mode 1
input
timing
is
described
in
Figure
6-10.
Mode
1
output
signals
are
listed
Figure
Figure

in Table 6-22
and
the
handshaking
function
is
shown
1in
6-11.
Mode
1
output
timing
is described
for
Port A
in
6-12 and Port B in Figure 6-13.
Mode 2 operation allows

Port

A to be bidirectional and the handshaking signals are listed
in Table 6-23. Mode 2 timing
is described
in Figure 6-14. When
Port A operates in mode 2, Port B can only operate in mode 0 or
mode 1.

Table

6-21

Mode

Signal

Name

Function

STB

Strobe

Port

PC4

the

Port

PC2

SBC-11/21

Input

external

asserted

This

signal

device

and

input

low

Port

PC1

STB
to
notify
loaded into the

SBC-11/21

Interrupt

must

signal

the

1latch.

This

PC5

PC3
PCO

the

into

Full

data

minimum.

asserted

A
B

loads

525

IBF

INTR

Buffer

port

Signals

for

Port

Port
Port

Input

Handshaking

response

the
.interface
input latch.

Request

This

asserted

assertion

that

signal

low

can

data

used

was

generate
an
interrupt
to
the microprocessor.
The bitset/bitreset commands must be used
to

enable/disable
Interrupts
is negated

the

INTE

bit

will be generated
with IBF asserted.

for

each

either

port.

when

STB

EXTERNAL DEVICE

SBC-11/21
REQUEST DATA
e

IBF UNASSERTED

e PLACE DATA ON

I/0 BUS

® ASSERTS STB

ACCEPTS DATA
® ASSERTS IBF

ACKN

OWLE

DGES

ACCE

PTED

DATA

e UNASSERTED
STB
REQUEST INTERRUPT IF INTE SET
e ASSERT INTR

e PROCESSOR READS DATA PORT
o NEGATE INTR IF ASSERTED
e NEGATE IBF
MR-7216

Figure 6-9

STB

TM mMAX

—.I MIN I’- '
|

312ns

IBF

Input Data Handshaking Sequence

Mode 1

, 312ns MAX

—{

INTR
|
INFUTDATA

/0 BUS

12ns :

312ns

| 412
AR

—>

192ns |

!|
!

| MIN 1 MIN

)
- VALID DATA

_ — — _ _ _m—m——/—————'

l
P

PORT DATA
READ

|
MR-7217

Figure 6-10

Mode

1 Strobed

Input Timing

Table

Signal

6-22

Name

Mode

Output

(A or
B)

Output

Port

PC7

low

Port

PCl

written

ACK

Port

A -

PC6

low

Port

PC2

accepted

the

specified

port.

Signals

Function

OBF

Handshaking

Buffer

This

indicate

that

the

data

into

the

Input

Acknowledge

the

Full

external

INTR

Interrupt

Request

PC3

generate

Port

PCO

when

the

external

and

INTE

This
device

This

set

device

and

SBC-11/21

ACK

signal
to

the

has
is

port

signal

output

interrupt

asserted

microprocessor

specified

1latched

Port

output

asserted

indicate
data

can

has

from

the

used

received

the

negated.

OUTPUT DATA
e OUTPUTS DATA ON 1/0 BUS

® ASSERTS OBF

ACCEPT DATA
® ASSERTS ACK
READS DATA

OUTPUT COMPLETE
o

NEGATES OBF

\ ACKNOWLEDGES RECEIVED DATA

GENERATE INTERRUPT/

® UNASSERTS ACK

IF INTE SET

® ASSERTS INTR

NOTE 1:

IF OBF IS ASSERTED LOW AND A READ OR WRITE TO THE PORT

BY THE SBC-11/21 PROCESSOR OCCURS BEFORE AN ACK STROBE
ISSENT BY THE EXTERNAL DEVICE, THE OBF LINE FOR THE ACCESSED PORT WILL NEGATE DURING THE ASSERTION OF THE READ OR
WRITE TO THE PORT AND THEN BECOME REASSERTED.
NOTE 2: OBF WILL ASSERT ON THE READ PORTION OF EVERY READ BEFORE

INTENDED WRITE TO PORT B AND THE OBFB WILL NEGATE AND REASSERT ON THE WRITE STROBE. IF INTEB IS SET AND INTRB IS ASSERTED, INTRg WILL NEGATE ON THE READ BEFORE THE INTENDED
WRITE TO PORT B.

NOTE 3: OBF WILL ASSERT ON THE WRITE PORTION OF EVERY READ BEFORE
INTENDED WRITE TO PORT A. IF INTEA ISSET AND INTRA 1S ASSERTED, INTRA WILL NEGATE ON THE WRITE PORTION OF THE READ BEFORE INTENDED WRITE TO PORT A.
MR-7218

Figure 6-11

microprocessor

EXTERNAL DEVICE

has

latches.

Mode 1 Output Data Handshaking Sequence

data

[

WRITE
PORT DATA

962ns MAX

INTR

I 662ns
L

OBF

|‘ ‘375ns !

MAX

f‘

_—

| 362ns

t =—325ns
|
_
MAX 375ns|

ACK

MAX

OUTPUT DATA

MAX

X LATCHED OUTPUT DATA

I/0 BUS

MR-7219

Figure 6-12

Mode 1 Strobed Output Timing

I
OBF

INTR —

MAX |

ACK

375ns

le— max

|
|

I
362ns|
MAX |<-—-b|
OUTPUT DATA

DAI?T(XUTPUT
LATC HE

)'(

1/0 BUS
MR-7220

Figure 6-13

Mode 1 Port B Strobed Output Timing

Table

6-23

Mode

Bidirectional Handshaking

Signals

Signal Name

Function

STB (PC4)

Strobe Input - This signal is asserted low by
the external device and strobes data into Port
A.

IBF

Input
when

(PC5)

Buffer Full - This
the
microprocessor

signal is asserted
has
accepted
STB

strobe.
INTR

This signal can be used
Interrupt Request to the microprocessor
interrupt
an
to generate

(PC3)

when the external device is demanding service.
OBF

(PC7)

Output Buffer Full - This output is asserted
has
microprocessor
the
that
1indicate
to
written data into the output port latches.

ACK

(PC6)

Acknowledge Input - This signal is asserted
low by the external device to indicate it has
taken

data

controls

from

the

NOTE

is configured,

When mode

after

user

output

port

PC6

(ACK)

jumpered to the port A direction control
pin through a rising edge delay circuit.
when PC6 is negated, the rising
Hence,
edge is delayed by 250 ns minimum, which
means that the buffer will be driving
data out the connector 250 ns minimum
the

interface

negates ACK.

Since every write is preceded by a read,
the contents of the input buffer should
be saved if IBF_,
is asserted prior to
writing

latches.

the DIR pin of the port A buffer.

port A mode

2 data.

WRITE

| .622ns MAX |

| MAX |

INTR |

| 325ns
MIN

ACK

525ns

'
i

_MIN

STB
IBF

312ns{

MAX ,‘ L
I 12ns |

192ns |

DATA

MIN

l—

|
|325ns|

para
le—sl
|
|

MAX . OUTPUT

312ns

I MAX|

! 20ns MIN I
READ

PORT A

500ns MAX
MR-7221

Figure 6-14

Mode 2 Port A Bidirectional Timing

CHAPTER 7

ADDRESSING MODES AND INSTRUCTION SET
7.0

The

GENERAL

discussion

topics:
O

modes

addressing

divided

into

major

six

Single Operand Addressing -- One part of the instruction
word specifies the registers; the remaining part provides
information for locating the operand.

Double Operand Addressing -- Part of the instruction word
specifies the registers; the remaining parts provide
information for locating two operands.

Direct Addressing —- The operand
selected

Deferred

(Indirect)

Addressing

the content of

the

The

contents

selected register is the address of the operand.

Use of the PC as a General Purpose Register —-- The PC is
unique from other general-purpose registers 1in one
Whenever the processor retrieves an
important respect.
By
instruction, it automatically advances the PC by 2.
four
with
combining this automatic advancement of the PC
of the basic addressing modes, we produce the four
special PC modes -- immediate, absolute, relative, and
relative deferred.

Use of the Stack Pointer as a General Purpose Register —Can be used for stack operations.

These addressing modes will now be discussed

by descriptions of

individual

instructions.

in detail,

followed

NOTE

Instruction mnemonics and address mode
writing
for
sufficient
are
symbols
The
programs.
language
assembly
programmer need not be concerned about
1is
this
binary digits;
conversion to
the
by
automatically
accomplished
assembler
7.1

ADDRESSING

Data stored
is
handling
etc.),
o

which

The

program.

MODES

in memory
specified

usually

function

must be accessed
by an SBC-11/21

indicates:

(operation code).

7-1

and manipulated.
(MOV,
instruction

Data
ADD,

general-purpose

source

used

large

operand

when

addressing

portion

the

(in

modes
data.

the

pointers.
the

pointers

for

index

the

important

how

the

computer

lists,

used

instruction

with

data

contents

than

the

processing

These

this

word

any

resides

the

address

through

memory

backward

modes

array

known

the

feature,

which

addressing

the

should

modes,

particularly

data.

instance,

following

are

contents

instruction

to
produce
the
address
of
the
operand.
easy access to variable entries in a list.

with

itself.

step

stepping

the

stepping
forward
through
known
as
autoincrement

tabular

registers.

handling

manipulated

operand

automatically

addressing.

and

usually

SBC-11/21

rather

selected

etc.).

flexible

microprocessor

conjunction

arrays,

automatically

summed
allows

specify

handled

The

the

operand.

and

which

autodecrement

locating

used).

Automatically
locations
is

addressing;

when

efficient

The

locations.
consecutive

used

for

may

operand,

useful

destination

(to

accumulators.

within

general-purpose

strings,

provide

general
registers
following ways.

the

data

character

structured

mode

is/are

addressing

the

locating

structured

The

and/or

of
are

This

considered

the

any

specific

arrangement.

Six

hardware

Program Counter

(PC)

Registers

are

not

function;
decoded.

their

general-purpose

They

through
use

can

contents

another
o

They

Stack

be
of

registers

Pointer

(SP)

determined

used
two

for

(R0--R5)
register

dedicated
by

the

operand

registers

(R6)

(R7)

can

instruction

storage.
be

For

added

and

that

example,
stored

serve

can

contain

pointers

They

can

the

address

used

for

used

the

operand

operand.

autoincrement

autodecrement

features.

They
and

can

program

index

access

7-2

registers

for

convenient

data

The

SBC-11/21

also has
instruction addressing mode
facilitate temporary data
storage structures.
for
convenient
handling
of
data
that
must
frequently.
This is known as stack manipulation.

combinations

that
used

used

to
pointer

keep

track

(SP).

Any

program

control;

subroutine
register R6
frequently

stack manipulation
register can be used as

however,

certain

referred

The

stack

the

stack.

The

stack
and

always

The

the

(SP)

pointer

moves

points

hardware

accumulator.
the

used

recommended

program

the

stack

keeps

down

items

used

the

clear,

The

the
pointer"

associated

with

latest

are

removed.

during

entry on

added

the

Therefore,

trap

allowing

the

interrupt

processor

its program counter

used

instruction

the

stack.

processor as
not

items

are

top

automatically

instruction

track

(PC).

stack

pointer

from

memory,

the

two

fetched

incremented

point

word.

7.1.1
Single Operand Addressing
The
instruction format for all single
as

"stack

instructions

information
program.

by the
that

Whenever

counter

known

"SP".

pointer

handling to store
return to the main

1linkage
and
interrupt
service
automatically
use
as a "hardware stack pointer".
For this reason, R6 is

stack

This can be
be
accessed

increment,

test)

operand

instructions

(such

is:

]

MODE
1

Rn
1L

OP CODE

1
7

DESTINATION ADDRESS
MR-5458

Figure

Bits 15 through 6
of instruction to
Bits

7-1

specify the operation
be executed.

five through zero form a
field.
This consists

address
o

Bits

Single Operand

zero

through

general-purpose

instruction

word.

code

Addressing

that

six-bit field called
two subfields.

defines

the

type

destination

two

registers

specify
is

which
of
the
eight
be
referenced
by
this

Bits
will

three through five specify how the selected register
be
used
(address
mode).
Bit
three
1s
set
to

indicate

deferred

(indirect)

addressing.

7.1.2
Double Operand Addressing
Operations which imply two operands

(such

second

assignments

add,

subtract,

and
compare)
are
handled
by
instructions
that
addresses.
The first operand is called the source
the destination

operand.

destination address
different
registers.
operand

instruction

12
I

the

source

and

fields may specify different
The
1instruction
format
for

modes and
the double

[

MODE

two
the

is:

OP CODE
L

Bit

move,

specify
operand,

[

03
L}

00
I

MODE

Rn
1

SOURCE ADDRESS

DESTINATION ADDRESS
MR-5459

Figure

7-2

Double

Operand

Addressing

The source address field is used to select the source operand, the
first operand. The destination is used similarly, and locates the
For example, the instruction ADD
second operand and the result.

A, B adds the contents (source operand) of location A to the
After execution B
contents (destination operand) of location B.
of A will
contents
the
and
addition
the
of
will contain the result
be

unchanged.

Examples

SBC-11/21

this

paragraph

instructions.

instructions

is located

Mnemonic

Description

CLR

Clear

CLRB

Clear byte

and

chapter

complete

use

the

1listing

in Paragraph 7.2.

following

the

sample

SBC-11/21

Octal Code

(zero

the

specified

destination)

(zero the byte in the specified

0050DD

1050DD

destination)

INC

INCB

Increment

(add one to contents of destination)

0052DD

(add one to the contents of

1052DD

Increment byte
destination

byte)

COM

Complement (replace the contents of the
destination by its logical complement;
each zero bit is set and each one bit is

0051DD

cleared)

COMB

Complement

byte (replace the contents of the
destination byte by its logical complement;
each 0 bit is set and each 1 bit is cleared).

1051DD

ADD

Add (add source operand to destination
operand and store the result at destination

06SSDD

address)
DD

destination

source

(

)

7.1.3

The

field

(six

bits)

field

contents
Direct

of
Addressing

following

direct

bits)

table
addressing.

summarizes

the

DIRECT

Mode

Name

Assembler
Syntax

INSTRUCTION

four

basic

modes

used

with

MODES

Function

————1

contains operand

OPERAND

MR-5460

Figure

Autoincrement

7-3

(Rn)+

Mode 0 Register

sequential

INSTRUCTION

—»1

ADDRESS

used
data,

then

pointer

incremented

OPERAND

*
+2

FOR WORD,

FOR BYTE

MR-5461

Figure

7-4

Mode

7-5

Autoincrement

Autodecrement

- (Rn)

is
a

decremented

then

OPERAND

»{

-1 FORBYTE

and

pointer.,

——» -2 FOR WORD,

ADDRESS

INSTRUCTION b—»]

MR-5462

Figure

Index

7-5

Mode

X (Rn)

Autodecrement

Value

produce
Neither

INSTRUCTION |—TM

added

address of
X nor (Rn)

(Rn)

operand.
1is modified.

—'l

ADDRESS

OPERAND

MR-5463

Figure
7.1.3.1 Register
registers may be

7-6

Mode

With

used

simple

contained
registers,

the

assembles

instructions

Index
mode

accumulators
register.
Since

selected

any

the

general

and
the operand
is
they
are
hardware

within the processor, the general registers operate at
high speeds and provide speed advantages when used for operating
on
frequently-accessed
variables.
The
assembler
interprets
and
opcrations.

of
represents

the

form

OPR
1is
used
to
represent
a
Assembler
syntax
requires
that
a
follows.
RO
R1

=
=

%0
%1

%2,

etc.

Registers

are

typically

sign

R5,

R6,

PC,

respectively.

and

R7.

indicates

general

referred

However,

OPR
Rn
as
register
mode
register name or number and
general
instruction
mnemonic.

general

and

OPR

are

7-6

defined

definition)

name
also

RO,

R1l,

referred

R2,
to

R3,

R4,

and

Symbolic

Octal

INC

005203

Operation:

Code

Instruction

Increment

Add

one
register

the

contents

0
)

0
L

1
L

R3.

15
T

Name

0
b

1
A

04
T

o
i

—

general

00
i

purpose

OP CODE (INC(0052))

DESTINATION FIELD

|
|

[

R6 (SP)

R7 (PC)

ADD

R2,

Operation:

Figure 7-7

INC R3 Increment

060204

aAdd

Add

the

contents

BEFORE

the

AFTER

000002

000004

000006

MR-5468

Figure

7-8

ADD

R2,

Add

contents

R4.

COMB

105104

Operation:

One's

Complement
complement

general

only

bits

0--7

(byte)

are

used,

byte

registers

operate

Byte

bits

0--7;

i.e.,

BEFORE
R4

R4.

(When

instructions

byte

the

AFTER

022222

022155

MR-5469

Figure

7-9

7.1.3.2 Autoincrement Mode

COMB

Complement

Byte

-- This mode provides

for automatic

stepping of a pointer through sequential elements of a table of
It assumes the contents of the selected general purpose
operands.
Contents of registers
be the address of the operand.
to
register
always by two for
words,
for
two
by
bytes,
for
one
(by
are stepped
The
location.
l
sequentia
next
the
address
to
R7)
R6 and
and
g
processin
array
for
useful
y
especiall
is
mode
ment
autoincre
It will access an element of a table and then
stack processing.
step the pointer to address the next operand in the table.
Although most useful for table handling, this mode is completely
general and may be used for a variety of purposes.
OPR

(Rn)+

Autoincrement Mode Examples

Symbolic
1.

CLR

(R5)+

Octal Code

Instruction Name

005025

Clear

Use contents of R5 as the address of the

Operation:

operand.

Clear selected operand and then

increment the contents of R5 by two.

BEFORE

AFTER

ADDRESS SPACE

20000

005025

30000

1111116

030000

ADDRESS SPACE

20000

005025

30000

000000

030002

MR-5464

Figure

7-10

CLR

7-8

(R5)+

Clear

Clear Byte

105025

(R5)+

CLRB

Use contents of R5 as the address of the
Clear selected byte operand and then
operand.

Operation:

increment the contents of R5 by one.
AFTER

BEFORE
ADDRESS SPACE

20000

30000 |

105025

111

30002

116

ADDRESS SPACE

030000

20000

105025

030001

30000 |

111

30002

000

|
MR-5465

Figure

ADD

7-11

CLRB

Operation:

The

contents

the

operand

which

R4.

then

are
is

062204

used

added

Byte

as
to

incremented

BEFORE

the
the

address

contents

two.

AFTER

ADDRESS SPACE
10000

Clear

Add

062204

(R2)+,R4

(R5)+

REGISTERS
R2

100002

010000

ADDRESS SPACES
10000

062204

REGISTERS
R2

100004

020000

v
100002

010000

100002

010000

MR 5470

Figure

7-12

ADD

(R2)

Add

7.1.3.3 Autodecrement Mode
(Mode 4)
-- This mode
is wuseful for
processing data in a list in reverse direction.
The contents of
the selected general purpose register are decremented (by two for
word instructions, by one for byte instructions) and then used as
the address of the operand.
The choice of postincrement,
predecrement
features
for
the
SBC-11/21 were not arbitrary
decisions,

but

were

intended

facilitate

hardware/software

stack

operations.
OPR- (Rn)

Autodecrement Mode

Examples

Symbolic

Octal

INC =-(RO)

005240

Operation:

Code

Instruction Name

Increment

The contents of RO are decremented by two and
used as the address of the operand.
The
operand

BEFORE

005240

17774

000000

incremented

one.

ADDRESS SPACE

017776

AFTER

REGISTERS

ADDRESS SPACE

1000

005240

17774

000001

017774

MR-5466

Figure

INCB

-(R0)

7-13

105240

Increment

Byte

used as the address of the operand.

operand byte
BEFORE
ADDRESS SPACE

105240

17774 | 000 |

17776

-(RO)

The contents of RO are decremented by one then

Operation:

1000

INC

increased by one.
AFTER
ADDRESS SPACE

017776

1000

105240

The

017775

* 1

00O

17774 | 001

%
|

17776

| 000

4
|

1
MR 5471

Figure

7-14

INCB

7-10

-(RO)

Increment

Byte

ADD

-(R3),RO

064300

Operation:

The

Add

contents

used
is

added

pointer
to

the

are

decremented

an operand

contents

two

(source)

then

which

(destination

operand).
BEFORE

AFTER

ADDRESS SPACE

10020

064300

17774

000020

077776

ADDRESS SPACE

10020

000050

064300

77774

77776

0000070

077774

000050

77776

MR 5472

Figure

7.1.3.4
general

Index

instruction
The

Mode

purpose

word,

contents

calculating
elements of

and

(Mode

ADD

-(R3),

The

and

are

form

the

summed

selected

a series of addresses,
data structures.
The

modified by program
instructions are of
word

7-15

is located
in
and Rn is the

Add

contents
index

the
may

address
be

the

selected

following

used

the

operand.
base

thus allowing random access
selected
register can
then

to access data in the table.
the form OPR X(Rn) where X is
the

word

for

to
be

Index addressing
the indexed word

memory location following the
general purpose register.

instruction

selected

OPR X (Rn)
Index

Mode

Examples

Symbolic

Octal

CLR

005064

200(R4)

Code

Instruction Name
Clear

000200

Operation:

The

operand

determined

adding 200 to the contents
location is then cleared.

address

the

R4.

The

operand

AFTER

BEFORE

ADDRESS SPACE

001000

1020

005064

1022

000200

1000

1024

ADDRESS SPACE

005064

1022

000200

001000

1024

+200
{,

1200

000000

1200

177777

1200
1202

MR 5473

Figure

COMB

Clear

Complement

105161
000200

200(R1)

(R4)

Byte

The contents of a location which is determined
by adding 200 to the contents of Rl are one's

Operation:

complemented

AFTER

BEFORE

105161

1022

000200

ADDRESS SPACE

ADDRESS SPACE
1020

logically complemented).

(i.e.,

017777

1020

105161

1022

000200

20176

166 | 000

20200

CLR 200

7-16

017777

017777
+200

20176

020177

r 1

011

| 000
i

20200

MR-7230

Figure

7-17

COMB

200

(R1l)

Complement

Byte

ADD

30(R2),20(R5)

066265

Add

000030

000020
Operation:

The

contents

by adding 30
the contents

to
of

a location which is determined
the contents of R2 are added to
a location which is determined

by
is

the

adding
stored

20
at

the

contents
destination

20(R5)
.

BEFORE

The

result

i.e.,

AFTER

ADDRESS SPACE

1020

066265

1022

000030

1024

000020

1130

2020

ADDRESS SPACE

1020

066265

1022

000030

1024

000020

000001

1130

000001

2020

000002

1100

R5.

address,

001100

002000

001100

002000

2000

+30

+20

1130

2020
MR-5475

Figure

7-18

ADD

(R2),

(R5)

Add

7.1.4
Deferred (Indirect) Addressing
The four basic modes may also be used with deferred addressing.
Whereas in the register mode the operand is the contents of the
selected register,
in the register deferred mode the contents of
the selected register is the address of the operand.
In the three other deferred modes,
the contents of the register
select the address of the operand rather than the operand itself.
These modes are therefore used when a table consists of addresses

rather

than

operands.

addressing

following

table

modes.

"@"

(or

Assembler

" ()"

summarizes

when

the

syntax
this

for

deferred

indicating

not

deferred

ambiguous).

versions

the

The
basic

Assembler

Function

Syntax

Mode

Name

@Rn or

Deferred

(Rn)

INSTRUCTION |—TM

operand.

OPERAND

|—"

ADDRESS

MR-5476

Figure

Autoincrement

Deferred

7-19

Mode

Deferred

@ (Rn) +

pointer to a word containing the
address of the operand, then
incremented (always by two;
for byte instructions).

INSTRUCTION

[—TM

ADDRESS

even

OPERAND

)

MR-5477

Figure

7-20

Mode

Autoincrement

Deferred

Autodecrement

Deferred

@-(Rn)

pointer

INSTRUCTION

ADDRESS

—

is decremented

by two; even for byte
instructions) and then

used as a
containing the

address

a word

-2

ADDRESS

the

(always

operand.

OPERAND

MR-5478

Figure

7-21

Mode

Autodecrement

Deferred

Index
Deferred

@X (Rn)

Value

X (stored in a word
following the instruction)
(Rn) are added and the sum

used

pointer

containing
operand.
modified.

address

Neither

nor

word

the

(Rn)

ADDRESS

INSTRUCTION

the

and

ADDRESS

OPERAND

MR-5479

Figure

The

following

examples

Deferred

Mode

7-22

Mode

illustrate

Index

the

Octal

CLR

005015

Clear

The contents
cleared.

Operation:

Code

1700

modes.

Instruction Name

location

BEFORE

ADDRESS SPACE
1677

deferred

Example

Symbolic
@R5

Deferred

AFTER

specified

ADDRESS SPACE

001700

1677

000100

are

1700

001700

000000

MR-5480

Figure

7-23

Autoincrement Deferred Mode
Symbolic

Octal

INC@(R2)+

005232

Operation:

CLR

Example

Code

Clear

(Mode

Instruction Name

Increment

The contents of R2 are used as the address of
the address of the operand.
Operand is increased by one.
Contents of R2
are

incremented
by

two.

BEFORE

AFTER

ADDRESS SPACE

R2
1010

ADDRESS SPACE

010300

000025

000026

1010

1012

010302

1012

10300

001010

10300

001011

MR-7231

Figure

Autodecrement

Deferred

7-24

Mode

Symbolic

Octal

COM

005150

@-(RO)

Operation:

The

INC

Example

Code

used
operand.

logically

(R2)

(Mode

RO are decremented by two and
the address of the address of the
Operand is one's complemented
(i.e.,
complemented).
as

BEFORE

AFTER

ADDRESS SPACE

10100

012345

ADDRESS SPACE

010776

10100

10102

10774

Increment

Complement

contents

then

165432

010774

10102

010100

10774

10776

167677

10776

MR-7232

Figure

7-25

COM

@-(R0)

Complement

Index

Deferred

Mode

Example

(Mode

Symbolic

Octal

ADD

067201

1000 (R2),R1

Code

Instruction Name
ADD

001000

Operation:

1000

and

contents

the address
operand the

of R2 are summed to produce
of the address of the source
contents of which are added to

contents

R1l;

the

BEFORE

stored

R1l.

AFTER

ADDRESS SPACE

1020

067201

1022

001000

ADDRESS SPACE

001234

000100

1024

1%?0

result

1020

067201

1022

001000

001236

000100

1024

000002

1050

000002

1100

001050

]
1100

001050

1000
+100
1100
MR-5483

Figure 7-26

7.1.5

Although

Use

the

seven

ADD @ 1000

General

general

purpose

in
function
as
the
program
counter
Whenever the processor uses the program
from

(R2), R1 Add

doubles

for
the microprocessor.
counter to acquire a word

memory,
the program counter
is automatically incremented by
two to contain the address of
the next word
of
the
instruction
being
executed
or
the
address
of
the
next
instruction
to
be
executed.
(When the program uses the PC to locate byte data, the
PC is still incremented by two.)

The

responds

there

are

However,

provide

advantages

unstructured

immediate,
deferred,

all

the

four

for

data.

standard

these

handling

When

SBC-11/21

modes

with

position

utilizing

the

addressing

modes.

which

can

code

and

the

independent

these

absolute (or immediate deferred),
are summarized below.

modes

relative

are

and

termed

relative

and

Assembler
Mode

Name

Syntax

Function

Immediate

Operand

Absolute

e#A

Absolute

follows

follows
6

Relative

Deferred

Address

operand

instruction.

Relative

follows

instruction.

Address

the

(index

value)

instruction.

Index value (stored in the
word following the instruction)
is the relative address for the
address

the

operand.

When

a standard program is available for different users, it often
helpful to be able to load
it into different areas of memory
and
run
it there.
SBC-11/21 can accomplish the relocation of a

program

code

very

(PIC)

efficiently

which

through

written

relative
relative
PIC

usually

The

use

position

the

addressing

relative

the

independent

modes.
If
and its operands are moved in such a way that the
distance
between
them
is
not
altered,
the
same offset
to the PC can be used in all positions in memory.
Thus,

instruction

This

the

using

references

locations

current

location.

also

greatly facilitates the handling of unstructured data.
particularly true of the immediate and relative modes.

7.1.5.1

Immediate Mode -- Immediate mode
is
equivalent
to
using
autoincrement mode with the PC.
It provides time improvements
accessing constant operands by including the constant in the
memory location immediately following the instruction word.
the
for

OPR
Immediate

Mode

Symbolic
ADD

#10,RO

#n,DD

Example

Octal
062700
000010

Code

Instruction Name
Add

Operation:

The
the
RO.

value 10 is located in the second word of
instruction and is added to the contents of
Just before this instruction is fetched

and executed, the PC
of the instruction.

first word and
operand

increments
is 27

source

PC).

Thus,

fetch

the

mode

the PC

operand

instruction)
point to the

points to the
The processor

the PC by two.
(autoincrement

used

(the

first word
fetches the

second

pointer

word

before being incremented
next instruction.

BEFORE

The
the

the

two

AFTER

ADDRESS SPACE

1020

062700

\R 0

000020

1020

062700

1022

000010

001020

1022

000010

1024

000030

001024

1024

MR-7233

Figure

7-27

ADD

10,

Add

7.1.5.2 Absolute
Addressing
—-This
mode
is
the
equivalent
of
immediate deferred or autoincrement deferred using the PC.
The
contents

the

location

following

the

the address of the operand.
Immediate
absolute address (i.e., an address that

where

memory

the

assembled

Mode

CLR

executed).

Examples

Symbolic

are

#1100

Octal

Code

005037

Instruction

Name

Clear

001100

Operation:

Clear

the

contents

taken

is interpreted as an
remains constant no matter

instruction
OPR

Absolute

instruction

data

location

1100.

AFTER

BEFORE

ADDRESS SPACE

005037 L\\\\

001100

1777717

1100

005037

001100

1100

000000

1102

MR-5485

Figure

ADD

#2000,R3

7-28

CLR

1100

Clear

063703
002000

Operation:

Add

contents

location

2000

AFTER

BEFORE

063703

000500

002000

000020

2000

000300

R3.

ADDRESS SPACE

063703

001000

002000

000024

2000

000300

K//

MR-7234

Figure

7-29

ADD

2000

Add

7.1.5.3

Relative

Addressing

This

mode
using
R7.
The
base of
the
stored in the second or third word

mode

1is

assembled

index

address
calculation,
which
is
of the instruction,
is not the

address

(PC),

of
the operand,
but the number which,
becomes the address of the operand.
This

when
mode

added to
is useful

writing position independent code since the location referenced
always
fixed
relative
to
the
PC.
When
1instructions
are
to
relocated, the operand is moved by the same amount.

where
Relative

Addressing

OPR A
or
the location of

the

for

is
be

instruction.

Example

Symbolic

Octal

INC

005267

OPR X (PC)
relative to

the

Code

Instruction Name
Increment

000054
Operation:

increment

location

location immediately
are added to (PC) to
Contents

are

memory

increased

one.

BEFORE

AFTER

ADDRESS SPACE

1020

005267

1022

000054

\\\\

1020
PC

1024

1026

000000

Jooa

1022

1024

1100

contents

following instruction word
produce address A.

1100

0005267
000054
«—PC

000001

_+54

1700
MR-5487

Figure

7-30

INC

Increment

7.1.5.4 Relative

Deferred

Addressing

This

mode

OPR

@X (PC)

similar

the relative mode, except that the second word of the instruction,
when added to the PC, contains the address of the address of the
operand, rather than the address of the operand.

where x

Relative

OPR Q@A

location containing

address of A,

instruction.

DeferYed

Mode

relative to

the

Example

Symbolic

Octal

Code

CLR @A

005077

Instruction Name
Clear

000020

Operation:

Add second word of instruction to updated PC to
Clear
produce address of address of operand.
operand.

AFTER

BEFORE

ADDRESS SPACE

(PC = 1020) 1020

005077

1022

600620

\
PC

(PC =1024) 1024

1024

1044

1020

005077

1022

000020

1024

+20

1044

010100

]

10100

100001

1044

010100

10100

000000
MR-7235

Figure

7.1.6

7-31

CLR

Clear

Use of Stack Pointer as General Register

The processor stack pointer (SP, register R6) is in most cases the
general register used for the stack operations related to program
Autodecrement with register R6 "pushes" data on to the
nesting.
stack and autoincrement with register R6 "pops" data off the
Since the SP is used by the processor for interrupt
stack.
it has a special attribute: autoincrements and
handling,
Byte operations
of two.
autodecrements are always done in stepsd.
unmodifie
addresses
odd
using the SP in this way leave

7.2

INSTRUCTION SET
specification
for
each
octal
code,
binary
code,
a

The

instruction,

effect
and

the

instruction

diagram

symbolic

notation

condition

codes,

examples,

MNEMONIC:

This

instruction
shown.
INSTRUCTION

has

indicated

byte

FORMAT:

describing
a

before

the

its

description,

each

equivalent,

diagram

includes

showing

execution
special

description.

the

accompanying

the
mnemonic,
format
of
the

and

the

comments,

When

the

word

byte

mnemonic

also

each

instruction

shows

the octal op code, the binary op code, and bit assignme
nts.
[Note
that
in byte
instructions
the
most
significant bit
(bit
15)
is
always a one].
SYMBOLS:

()

src

source

dst

destination

contents

loc

of
address
address

becomes

"is

popped

from stack"

"is

pushed

onto

boolean

AND

boolean

s € <

<€

]

location

exclusive

boolean

Reg

Byte

not
register

for

word

for

byte

concatenated

stack"

7.2.1

The

Instruction Formats

information.

DECB, NEG, NEGB, ADC, ADCB, SBC, SBCB,
TST, TSTB, ROR, RORB, ROL, ROLB, ASR,
ASRB,

SXT,

)

instructions for more detailed

(CLR, CLRB, COM, COMB, INC, INCB, DEC,

sSingle Operand Group

OP CODE
1

1n.the

used

instructions

all

individual

Refer to

SBC-11/21.

include

formats

following

ASL,
XOR)

)

ASLB,

JMP,

SWAB,

MFPS,

DD(SS)
i

MTPS,

MR-5191

Double

Operand

Single Operand Group

7-32

Figure

Group

(BIT,
suB,

12
|

BIC,
BICB,
BIS,
CMP, CMPB)

06
]

]

ADD,

]

[

Double

Operand

)

BISB,

MOVB,

OP CODE
1

BITB,
Mov,

]

MR-5192

Figure

Program
a.

7-33

Control

Group

Branch

(all

branch

instructions)

08
1

[

]

OP CODE
]

Group

)

]

OFFSET
1

MR-5193

Figure

Jump

7-34

Program

Subroutine

(JSR)

Control

Group

Branch

MR-5194

Figure

7-35

Program Control

Group JSR

Subroutine

Return

(RTS)

MR-5195

Figure

7-36

Program Control

Group

(break

point,

IOT,

BPT)

Traps

)

EMT,

TRAP,

(RTS)

15
i

OP CODE
Il

MR-5196

Figure

Subtract

7-37

and

Program

branch

09
¥

]

{

Control

(SOB)

Group

Traps

]

NN
L

MR-5197

Figure 7-38

Operate

Group

(HALT,

Program Control Group Subtract

WAIT,

RTI,

RESET,

RTT,

NOP,

MFPT)

15
I

)

]

OP CODE
I

MR-5198

Figure
5.

Condition

Code

7-39

Operators

Operate
(all

condition

15
1

]

0
L

Group

06
1

)

[

Figure

instructions)

0/1

7-40

code

Condition

MR-5199

Group

7.2.1.1 Byte
Instructions
-The
SBC-11/21
includes
a
full
complement of instructions that manipulate byte operands.
Since
all microprocessor addressing is byte-oriented, byte manipulation
addressing

straightforward.

Byte

instructions

with

autoincrement
or
autodecrement
direct
addressing
cause
the
specified register to be modified by one to point to the next byte
of data.
Byte operations
in register mode access the low-order
byte
of
the
specified
register.
These
provisions
enable
the
SBC-11/21 to perform as either a word or byte microprocessor.
The
numbering scheme for word and byte addresses in memory is:

HIGH BYTE

WORD OR BYTE

ADDRESS

002001

BYTE 1

BYTE O

002000

002003

BYTE 3

BYTE 2

002002

MR-5201

Fiqure

7-41

Byte

The most significant bit (Bit 15)
to indicate a byte instruction.

Instructions

the

instruction

Example:

Symbolic

Octal

CLR

0050DD

CLRB

1050DD

Clear Word

Clear Byte

word

set

7.2.2
The

List

SBC-11/21

SINGLE

of Instructions
instruction set

shown

the

following

sequence.

OPERAND

Mnemonic

Instruction

Op Code

General
CLR(B)

clear

COM (B)
INC (B)

complement

increment

dst

DEC (B)

decrement

052DD

dst

NEG (B)

053DD

negate

TST (B)

test

Shift

050DD

dst

051DD

dst

054DD

dst

057DD

Rotate

ASR (B)
ASL (B)
ROR (B)

ROL (B)
SWAB

Multiple

arithmetic
arithmetic

shift
shift

right
rotate left
swap bytes

060DD
0003DD

Precision
add

subtract carry
sign extend

carry

055DD

056DD
0067DD

Operators

MFPS

move

byte

from

MTPS

move

byte

MOV (B)

move

source

CMP (B)

compare

ADD

add src to dst
subtract src from

DOUBLE

062DD

063DD
061DD

SBC (B)

Word

right
left

rotate

ADC (B)
SXT

dst

1067DD

1064ss

OPERAND

Gener al

SUB

src

destination

dst

15SDD
2SSDD
06SSDD
16SSDD

Logic al
BIT (B)

bit

BIC (B)

bit clear
bit set
exclusive

BIS(B)
XOR

test

3SSDD
45SDD

55SDD
074RDD

PROGRAM

CONTROL

Op Code
or

Mnemonic
Branch

Instruction

000400

BNE
BEQ
BMI
BVC

branch if minus
branch if overflow is clear

100400
102000

BCC
BCS

branch if carry is clear
branch if carry is set

Signed Conditional

BGT
BLE

Conditional

Branch

(to zero)

103400

branch if lower

Subroutine

jump
jump to

SOB

subtract one and branch

RTS

return

0001DD
004RDD

subroutine

from

002000
002400
003000
003400
101000
101400
103000

branch if higher
branch if lower or same
branch if higher or same

JMP
JSR

102400

103000
103400

branch if greater than (zero)
branch if less than or equal (to zero)

BLO
&

Branch

branch is greater than or equal
branch if less than (zero)

BGE
BLT

BHI
BLOS
BHIS

100000

branch if overflow is set

BVS

Unsigned

001000
001400

branch if plus

BPL

Trap

Code

branch (unconditional)
branch if not equal (to zero)
branch if equal (to zero)

Jump

Base

subroutine

00020R

(if # 0)

077R00

Interrupt

EMT
TRAP
BPT
I0T
RTI
RTT

emulator trap
trap
breakpoint trap
input/output trap
return from
return from

interrupt
interrupt

104000--104377
104400--104777
000003
000004

000002
000006

MISCELLANEOUS

HALT
WAIT
RESET

halt

000000

wait for interrupt
reset external bus

000001
000005

MFPT

move

000007

processor

type

RESERVED

INSTRUCTIONS

00021R

00022
CONDITION

CODE

OPERATORS

CLC

clear

000241

CLV

clear

000242

CLZ

clear

000244

CLN

clear

CCC

000250

clear

all

SEC

set

SEV

set

000262

SEZ

set

000264

SEN

set

all

NOP

Single

bits

000257

000261

SCC

7.2.3

000270
CC

bits

000277

operation

Operand

00240

Instructions
NOTE

all

SBC-11/21

instructions

write

operation
to
a
memory
location
or
register
is
always
preceded
by
a
read
operation from the same location.
The
exception is when writing PC and PSW to
the stack in two cases.
l.

The

execution

the

preceding
an
interrupt
service routine.
2.

Interrupt

and

trap

microcode

trap

instructions:

HLT

TRAP
BPT
IOT

7.2.3.1

General

-—-

CLR

CLRB
CLEAR DESTINATION

=050DD

15
L]

0/1

0
i

0
I

0
Il

1
)

0
1

1
1

0
L

0
)

Figure

)

7-42

7-29

d
1

CLR

d
i

d
L

d
g

d
)

MR-5202

Operation:

(dst) <0

Condition Codes:

Description:

cleared

set

cleared

Word:

Contents

replaced
Byte:

with

specified

destination

Same

Example:

CLR

Before
(R1)

are

zeros.

After

177777

(R1)

000000

NZVC

1111

0100

COM
COMB

COMPLEMENT DST

2051DD

15
i

0/1

0
L

0
I

0
1

1
1

0
L

Figure

Operation:
Condition

]

0
1

00
T

d
1

d
]

d
L

d
[

d
}

MR-5203

7-43

COM

(dst)
<~ (dst)

Codes:

Description:

N: set if most significant bit
cleared otherwise
Z: set if result is 0; cleared

cleared

set

result

set;

otherwise

Replaces the contents of the destination address
by their logical complement (each bit equal to 0
is set and each bit equal to one is cleared)
Byte:

Same

Example:

COM

Before

(RO)

013333

After

(RO)

164444

NZVC

0110

1001

INCB

INCREMENT DST

0/1

=(052DD

MR-5204

Figure

Operation:

(dst)<(dst)

Condition Codes:

N:
Z:
V:
C:

Description:

Word:

Add

Byte:

Same

set
set
set
not

7-44

INC

if result is <0; cleared otherwise
if result is 0; cleared otherwise
if (dst) held 077777; cleared otherwise
affected
one

Example:

contents

INC

destination

Before

(R2)

After

000333

(R2)

000334

NZVC
0000

DEC
DECB
DECREMENT DST

=053DD

06
¥

0/1

)

00
L)

MR-5205

Figure

& (dst)
(dst)

Condition Codes:

N:
7Z:
V:

set
set
set

if
is
if

not

affected

Word:

result is
result is
(dst) was

Subtract

destination
Byte:

Same

DEC

-1

Operation:

Description:

7-45

one

<0, cleared otherwise
0; cleared otherwise
100000; cleared otherwise

from

the

contents

the

Example:

DEC

Before
(R5)

After

000001

(R5)

000000

NZVC

1000

0100

NEG

NEGB
NEGATE DST

15 I
0/1

=054DD

1
O

L
0

T
0

¥
d

]

MR-5206

Figure

Operation:
Condition

(dst)<

Codes:

NEG

—-(dst)

set

the

set

result

7-4¢

set

1if

result

the

result

the

result

otherwise
C:

Description:

cleared

<0;

cleared

otherwise

100000;

set

cleared

otherwise

Word:

Replaces
the
contents of
the
address
by
its
two's
complement.

destination

100000

(in

is
replaced
complement notation the

positive

Byte:

itself

most
counterpart).

negative

NEG

Before
=

000010

(RO)

After
177770

NZVC

0000

1001

that

two's
number has

Same

Example:

(RO)

Note

TSTB
TEST DST

u057DD

0/1

0
)

]

1
1

{

00
d

1
MR-5207

Figure

Operation:

<€ (dst)
(dst)

Condition Codes:

N:
Z:

set
set

cleared

if
if

7-47

TST

the result is <0; cleared otherwise
result is 0; cleared otherwise

Word: Sets the condition codes N and Z according
the destination address,
the contents of
to

Description:

contents of dst

remains unmodified

Same

Byte:

TST

Example:

After

Before

(R1)

012340

(R1)

NZVC
0000

NZVC
0011

7.2.302

Shifts

Rotates

accomplished by the shift
ASR -- Arithmetic

- Scaling data
instructions:

shift

= 012340

factors

two

1is

right

ASL -- Arithmetic shift left

of the operand is reproduced in shifts to
(bit 15)
The sign bit
The low order bit is filled with zero in shifts to the
the right.
Bits shifted out of the C bit, as shown in the following
left.
examples, are lost.

The rotate
bit

instructions operate on the destination word and the C

though

instructions

manipulation.

they

formed

facilitate

17-bit

sequential

bit

"circular

testing

buffer."

and

These

detailed

bit

ASR
ASRB
ARITHMETIC SHIFT RIGHT

=062DD

15
J

Figure
Operation:

Condition

(dst)<(dst)

Codes:

set

set
Z:

if
if

the

Description:

one

the
by

MR-5208

place

the

cleared

bit

result

otherwise

Exclusive OR of
the
completion

low-order

right

bit of
the
otherwise

cleared

result

V: loaded from
C-bit
(as
set
operation)
C: loaded from

ASR

high-order
0);

d
1

7-48

the

shifted

(result
set

the N-bit and
of
the
shift

the

destination

Word:
Shifts all
bits of the destination right
one place.
Bit 15 is reproduced.
The C-bit
is
loaded
from bit
zero of the destination.
ASR
performs

signed

division

the

two.

destination

Word:
Example:
00

BYTE:

ODD ADDRESS
T

EVEN ADDRESS

j I

00
T

C
{

MA-7236

Figure

7-49

ASR

Description

ASL
ASLB
ARITHMETIC SHIFT LEFT

=063DD

15
|

0/1

0
|

—

0
I

0
]

1
1

0
1

0
L

Figure

1
1

7-50

00
T

d
[

AsL

d
1

d
L

d
[

d
I

mrezio

Operation:

(dst)<€(dst)

Condition Codes:

N:
set
if high-order bit of the
(result < 0); cleared otherwise
Z: set if the result = 0; cleared

shifted

one

place

the

result

Word:

sShifts

one.place.

CTb1F

all

Bit

the

bits

zero

status

significant

bit

signed

destination

]

[ —

set

the N-bit and
of
the
shift
bit

the

destination

left

with

loaded

zero.

from

The

the

most

two

Word:

15 ¥

the

loaded

word

perfprmg

otherwise

V: loaded with the exclusive OR of
C~-bit
(as
set
by the
completion
operation)
C:
loaded
with
the
high-order
destination
Description:

left

the
destination.
nmultiplication
of
with overflow indication.

ASL

the

]

BYTE:

?DD ADDRESS

|u—

Figure

7-51

EVEN ADDRESS

je—

ASL

-0

Description

ROR

RORB
ROTATE RIGHT

=060DD

15
1

0/1

0
[l

0
Il

0
1

1
1

1
[]

0
1

(dst)<(dst)

Operation:
Condition

Codes:

0
1

Figure

]

d
[

]

d
1

MR-5212

7-52

rotate

ROR

right

one

place

N:
set if the high-order bit of
set (result <0); cleared othewise
Z:
set
1if
all
bits
of
result
otherwise

the
=

result
0;

cleared

loaded

with

the

Exclusive

C-bit
(as
operation)

set

the

completion

with

the

low-order

bits

loaded

the
of

N-bit

the

bit

and

rotate
of

the

right

one

destination
Description:

Rotates

all

the

destination

place.
Bit 0 is loaded into the C-bit and the
previous contents of the C-bit are loaded
into
bit 15 of the destination.

Example:
WORD:

I
15
C

]

}

{

]

—

BYTE:

OoDD

EVEN

MR 5213

Figure

7-53

ROR

Description

ROL
ROLB
ROTATE LEFT

m061DD

15
1

0
)

0
A

1
Bl

]

Operation:

Condition

(dst)

Codes:

set

<(dst)
if

the

0
}

Filgure

]

00
T

{

d
1

d
L

)

MR-5214
7-54

rotate

ROL

left

one

place

high-order

bit

the

result

is set (result < 0); cleared otherwise
Z:
set
1if
all
bits
of
the
result
word
cleared otherwise

word
=

loaded

with the Exclusive OR of the N-bit and
C-bit
(as set by the completion of the
rotate
operation)
C:
loaded
with
the
high-order
bit
of
the
destination

Description:

Word:

Rotate

one

place.

the

status

C-bit

all

and

loaded

the
destination
1left
loaded
into the C-bit of
the previous contents of the

word

are

bits

Bit

into

Bit

the

destination.

Example:
WORD:

DST

{

je—0

BYTE:

:
T

oDD
]

EVEN

Figure

7-55

ROL

[

Description

SWAB
SWAP BYTES

0003DD

15
T

MR-5216

Figure

Operation:

Byte

1/Byte

7-56

<Byte

SWAB

0/Byte

Condition Codes:

(bit

N: set if high-order bit of low-order byte
7) of result is set; cleared otherwise
7: set if low-order byte of result = 0;

cleared

otherwise
V: cleared
C: cleared

Exchanges high-order byte and low-order byte of

Description:

the destination word

(destination must be a word

address)
.

SWAB R1

Example:

(R1)

Before

(R1)

= 077777

After

= 177577
NZVC
0000

NZVC
1111

7.2.3.3 Multiple Precision -- It is sometimes necessary to do
The
arithmetic on operands considered as multiple words or bytes.

SBC-11/21

makes

instructions

byte

ADC

special

(Add

provision

Carry)

and

for

SBC

such

operations

(Subtract

Carry)

with

and

the

their

equivalents.

For example, two 16-bit words may be combined into a 32-bit double
precision word and added or subtracted as shown below.
32-BIT WORD

(
31

OPERAND

h
0

(
31

OPERAND

)
0

RESULT

MR-5217

Figure 7-57

Multiple Precision

Example:
The

addition

-1

(R1)

-1

and

-1

could

(R2)

177777

(R2)

are

performed

follows:

37777777777

ADD

R1,R2

ADC

ADD

R4,R3

177777

After

ADC

(R3) and (R4) are added
Result is 37777777776 or

(R1l)

and

instruction

adds

(R3)

added,
bit

177777

(R4)

loaded

into

the

(R3);

(R3)

177777

bit

-2

ADC

ADCB
ADD CARRY

=0550D

15
1

0/1

O
)

0
[

0
1

1
]

1
|

00
v

d
1

d
[

d
|

d
I

d
Il

MR-5218

Figure

Operation:

Condition

(dst)<€(dst)+(C

Codes:

N:
Z:
V:

cleared

0: cleared otherwise
0; cleared otherwise
was
077777
and
(C)

was

otherwise
1if
(dst)
otherwise

177777

and

(c)

Adds
the
contents
of
the
C-bit
1into
the
destination.
This
permits
the carry
from the
addition of the
low-order words
to be
carried
into the high-order result.
Byte:

Example:

ADC

bit)

set if result <
set if result =
set
if
(dst)

cleared
C:
set

Description:

7-58

Same

Double

precision addition may be
following instruction sequence:

done

ADD

AQ0,BO

;add

low-order

ADC

;add

carry

ADD

Al,Bl

;add

high-order

into

with

the

parts
high-order
parts

SBC
SBCB
SUBTRACT CARRY

0/1

=056DD

{

]

04
'

)

MR-5219

Figure

Operation:

(dst)
< (dst)-(C)

Condition Codes:

N:
Z:
V:

7-59

SBC

set if result <0; cleared otherwise
set i1f result 0; cleared otherwise
set if (dst) was 100000; cleared otherwise
cleared
was 0 and C was 1;
(dst)
if
set

otherwise

the C-bit from
the carry from
the subtraction of two low-order words to be
the
of
part
order
high
the
from
subtracted

Word: Subtracts the contents of
This permits
the destination,

Description:

result.
Same

Byte:

Double precision subtraction is done by:

Example:

AOQ,BO
Bl
Al,Bl

SUB
SBC
SUB

SXT

0067DD

SIGN EXTEND
15 1

0 ;

0 A

0 L

]
|

|
\

|
1

1
1

T
1

|
1

1
1

|
I

|
]

d
MR-6220

Figure

7-60

SXT

Operation:

(dst)<0 if N-bit is clear

Condition Codes:

(ds t)<1

V:
C:

N-bit

unaffected

set

is set

if N-bit clear

cleared

unaffected

Description:

the

condition

code

bit

set

then

-1

placed in the destination operand;
if N bit is
clear, then a zero is placed in the destination
operand.
This
instruction
is
particularly

useful in multiple precision arithmetic
it
permits
the
sign
to
be
extended
multiple words.
Example:

SXT

(A)

7.2.3.4

PS Word

Before
012345

(A)

After
177777

NZVC

1000

Operators

because
through

MFPS
MOVE BYTE FROM PROCESSOR STATUS WORD

1067DD

0
b

0
A

]

00
I

)

d
1

]

d
L

d
4

d
|

MR-5221

Figure

Operation:

MFPS

bits

Code

Description:

aO<INZ

Condition
Bits:

(dst) <PS
dst lower

7-61

set if PS bit 7
set if PS <0:7>
cleared
not affected

The

bit

contents

l1;: ;
0;

cleared
cleared

the

otherwise
otherwise

are

moved

the

effective destination.
If destination is mode
0, PS bit 7 is sign extended through upper byte
of
the
register.
The
destination
operand
address is treated as a byte address.
Example:

MFPS

Before

After

[0]

[000014]

[000000]

MTPS

1064SS

MOVE BYTE TO PROCESSOR STATUS WORD

15
1

]

{

]

MR:-5222

Figure

7-62

MTPS

Operation:

PS< (SRC)

Condition Codes:

Set according to effective SRC operand bits 0--3

Description:

The eight bits of the effective operand replaces

The source
the current contents of the PS.
operand address is treated as a byte address.
Note that the T bit (PS bit four) cannot be set

with this

unchanged.
change the

instruction.

remains

The SRC operand

to
This instruction can be used
the
in
7--5)
bits
(PS
priority bits

PS.

Double Operand Instructions

7.2.4

(and time)
Double operand instructions provide an instruction
and
"loaQ“
need for
saving facility since they eliminate the accum
ented
r-ori
ulato
"save" sequences such as those used in
machines.

7.2.4.1 General

-—-

MOV
MOVB

®1SSDD

MOVE SQURCE TO DESTINATION

0/1
L

]

}

[

S
1

|§

]

[

00
d

d
[l

1
MR-5223

Operation:
Condition

(dst)
<€ (src)

Codes:

Description:

set

(src)

<0;

set

(src)

cleared

not

cleared

otherwise

cleared

otherwise

affected

Word:

Moves
the
source
operand
to
the
destination location.
The previous contents of

the destination are lost.
The contents of the
source address are not affected.
Byte:
Same
as
MOV.
The
MOVB
to
a
register
(unique
among
byte
instructions)
extends
the
most significant bit of the low order byte (sign
extension).
exactly

Example:

MOV

Otherwise
MOV

operates

XXX,R1l

MOVB
on

operates

bytes

words.

;loads
the

contents

one

with

memory

location; XXX represents
a
programmer—-defined
mnemonic

used

represent

to
memory

location.

MOV

#20, R0

;loads
the
number
20
into
Register
0;
"#"
indicates that the value
20

MOV

#20,

- (R6)

(R6)

+,@

#177566

operand.

; pushes

the

contained

onto
MOV

the

;pops

the

operand

and

moves

;performs

MOVB @#177562,

@#177566

;moves

off

location

(terminal

R1,R3

stack.

stack

memory

MOV

operand

location

into

177566

buffer).

inter

transfer.

character

from

terminal keyboard buffer
printer
terminal
to
buffer.

CMP
CMPB
m2SSDD

COMPARE SRC TO DST

0/1

)

MR-6224

Figure

Operation:

(src)=(dst)

Condition Codes:

N:
7Z:
V:

7-64

CMP

set if result <0; cleared otherwise
set if result = 0; cleared otherwise
set if there was arithmetic overflow;

that

cleared otherwise.
if there was a carry

most

is, operands were of opposite signs and the sign
of the destination was the same as the sign of

the result;
C: cleared

the

from

set otherwise.

significant bit of the result;

Compares the source and destination operands and
sets the condition codes, which may then be used

Description:

for arithmetic and logical conditional branches.
The only action
Both operands are unaffected.
The compare 1is
is to set the condition codes.
branch
conditional
a
by
followed
customarily
instruction.

the
not

Note that unlike the subtract instruction
(src)-(dst),
is
operation
of
order
(dst)-(src).
ADD

ADD SRC TO DST

1
1

06SSDD

)

]

[

1
[

¥
i

1
1

Figure

Operation:
Condition

MR-5225

7-65

ADD

(dst)<€(src)+ (dst)
Codes:

set

result

<0;

if result = 0;
set
i1f
there
was

cleared otherwise.
cleared othrwise.
arithmetic
overflow

result of the operation;
that is both operands
were of the same sign and the result was of the
opposite sign; cleared otherwise.
C:
set
if
there
was
a
carry
from
the
most
significant
bit
of
the
result;
cleared

othrewise.

Adds the source operand to the destination
operand and stores the result at the destination

Description:

address.
destination
source are

the
of
contents
original
the
The contents of
lost.
Two's complement
affected.

is no

equivalent byte mode.

performed.

addition

Note:

The
are
not

There

ADD

20, R0

ADD

, XXX
R1

Add register to register:

ADD

R1,R2

Add memory to memory:

ADD@

Add to register:

Examples:

Add

XXX

memory

memory:

programmer-defined

17750 ,XXX

for

mnemonic

location.

SUB

SUBTRACT SRC FROM DST

1
L

1
1

16SSDD

]

s
|

]

Figure

N:
Z:

d
1

7-66

Condition Codes:

S
]

(dst)
<€ (dst)~-(src)

if
if

s
L

Operation:

set
set

d
i

d
L

00
d

MR-5226

SUB

result <0; cleared otherwise
result = 0; cleared otherwise

set
if
there
was
arithmetic overflow as a
result of
the operation,
that
is
1if operands
were
of
opposite
signs
and
the
sign
of
the
source was the same as the sign of ther esult;
cleared otherwise.
C:
cleared
if there

significant

bit of

was

the

carry

result;

from

the

most

set otherwise.

Description:

Subtracts
the
source
operand
from
the
destination operand and leaves the result at the
destination address.
The original contents of
the destination are lost.
The contents of the
source are not affected.
In double-precision
arithmetic
the
C-bit,
when
set,
indicates
a
"borrow".
Note: There

Example:

equivalent

byte

mode.

SUB R1l,R2
Before

(R1)
(R2)

=
=

After

011111
012345

(R1)
(R2)

=
=

NZVC
1111

011111
001234
NZVC
0000

same format as the
7.2.4.2 Logical -- These instructions have the operat
ions on data
They permit

double operand arithmetic group.
at the bit level.

BIT

BITB

=3SSDD

BIT TEST

1
L

1
1

1
]

I
1

¥
1

i
L

0605

!
1

I
1

Ll
[l

|
1

d
MR-5227

Figure

7-67

BIT

Operation:

(src) /\ (dst)

Condition Codes:

N: set if high-order bit of result set; cleared
otherwise

V:
C:

Description:

set if result = 0;

cleared otherwise

cleared
not affected

Performs logical "and" comparison of the source
and destination operands and modifies condition
codes

accordingly.

Neither

the

source

nor

The BIT instruction
destination is affected.
the
any of
whether
test
to
may be used
the
in
set
are
that
bits
corresponding
destination

whether

all

are

also

set

corresponding

destination are clear

bits

in the source.

source

set

the

test bits three and four of R3

BIT #30,R3

Example:

R3 = 0

000

see

000

011

both are off

00O
After
NZVC

Before
NZVC

0001

1111

BIC

BICB
m4SSDD

BIT CLEAR

0/1

00
d

Ll
[

]

MR-5228

Figure

7-68

BIC

Operation:

(dst)<(dst) /\ ~(src)

Condition Codes:

N: set if high order bit of result set; cleared
otherwise

V:
C:

Description:

set if result = 0; cleared otherwise

cleared
not affected

that
destination
the
in
bit
each
Clears
The
corresponds to a set bit in the source.
original contents of the destination are lost.
The contents of the source are unaffected.
BIC R3,R4

Example:
(R3)
(R4)

Before
= 001234
= 001111

(R3)
(R4)

After
= 001234
= 000101
NZVC

NZVC

0001

1111

001
001

010
001

011
001

100
001

Before:

(R3)
(R4)

= 0
= 0

000
000

After:

(R4)

= 0

000 000 001 000 001

BISB
BIT SET

s5SSDD

12
T

0/1

06
1

)

Operation:

(dst)<(dst) \/

Condition Codes:

set

Description:

not

{

MR-5229

BIS

7-69

(src)

high-order

otherwise
Z: set if result
V: cleared
C:

Figure

00
Ll

bit

result

cleared

set,

cleared

otherwise

affected

Performs
"Inclusive OR"
operation
between
the
source and destination operands and leaves the
result
at
the
destination
address;
that
is,
corresponding bits set in the source are set in
the
destination.
The
contents
of
the
destination

are

lost.

Example:

BIS

(RO)

(R1)

RO,R1

Before
001234
001111

(RO)

(R1)

After
001234
001335

NZVC

0000

Before:

After:

(RO)

000

001

010

011

100

(R1)

000

001

(R1l)

000

001

011

101

XOR

EXCLUSIVE OR

15
0

074RDD

Figure

7-70

XOR

]

00
d

MR-5230

Operation:

(dst)<(dst)=\/4

Condition Codes:

N:
Z:

set
set

cleared

unaffected

Description:

if
if

(Reg)

the result <0; cleared otherwise
result = 0; cleared otherwise

The exclusive OR of the register and destination
operand
is stored in the destination address.
Contents of register are unaffected.
Assembler
format

is:

XOR R,D.

Example:

XOR

(RO)
(R2)

RO,R2

Before
001234
001111

=
=

(RO)
(R2)

After
001234
000325

=
=

NZVC
1111
Before:

(RO
(R2)

=
=

0
0

000
000

001
001

010
001

011
001

100
OO1

After:

(R2)

000

011

010

101

7.2.5

Program Control

7.2.5.1

Branches

location

the

current

1.
2.

defined

contents

the branch
it

The

offset

Instructions

These

the

1instructions

cause

sum of

the

offset

instruction

unconditional.

the

Program Counter

conditional

testing

NZVC
0001

and

condition

number

the

codes

words

branch

(multiplied
if:

conditions

are

two)

met

and

after

(NZVC).

from

the

current

contents

PC forward or backward.
Note that the current contents
point to the word following the branch instruction.

the

Although the offset expresses a byte address the PC is expressed
in words.
The offset is automatically multiplied by two and sign
extended to express words before it is added to the PC.
Bit seven
is the sign of the offset.
1If it is set, the offset is negative

and

the branch

is done

is not set, the offset
forward direction.

in the backward direction.

Similarly

positive

and

the

branch

done

if
in

it
the

The
8-bit offset allows branching
in the
backward
direction
by
2008 words
(400
bytes)
from the current PC,
and
in the forward
direction by 1778 words (376 bytes) from the current PC.

The microprocessor assembler handles address arithmetic for
the
user and computes and assembles the proper offset field for branch
instructions in the form:
Bxx

Where
which

loc

"Bxx" is the branch instruction and "loc" is the address to
the
branch
is
to
be made.
The
assembler gives an error

indication

the

instruction

exceeded.

Branch

instructions

have

Conditional
met,

are

branch

treated

instructions

the

permissible

where

effect

the

branch

range

condition

codes.

branch

condition

not

OPs.

BRANCH (UNCONDITIONAL)
15

0
L

0
1

000400
PLUS OFFSET

0
1

0
Il

0
1

]

[

]

[

OFFSET

MR-5231

Operation:
Condition

PC
Codes:

Description:

€

Figure

7-71

offset)

PC +

Unaffected
Provides

way

within

range

one

word

transferring

—12810

program

+127lo

control

words with

instruction.

New PC address =

updated PC +

Updated PC =

address of

Example:

With the Branch instruction at location 500, the
following

(2 X offset)

branch

offsets

instruction +2

apply.

New PC Address

Offset Code

Offset

474

375

-3

500
502
504
506

377
000
001
002

-1
0
+1
+2

476

376

-2

(decimal)

BNE
001000 PLUS OFFSET

BRANCH IF NOT EQUAL (TO ZERO)

]

[

OFFSET

Figure 7-72
PC +

]

MR-5232

BNE

Operation:

PC <€

Condition Codes:

Unaffected

Description:

Tests the state of the Z-bit and causes a branch
if the Z-bit is clear.
BNE is the complementary
operation to BEQ.
It is used to test- -inequality

CMP,

following
test that

a
BIT
operation,
the result of the

was

nhot

CMP

A,B

BNE

will

the

ADD

A,B

BNE

will

were

that

also

some

bits

the

set

source,

and generally,
to
previous operation

2zero.

;compare

;branch

branch

and

test

destination

following
the

Example:

(2 X offset)

and

they are not equal

A # B

sequence

equal

;add

;Branch

branch to C

if the

is not

result

if A + B # 0

001400 PLUS OFFSET

08
)

00
|

OFFSET

Figure

7-73

MR-5233

Operation:
Condition

Codes:

€ PC +

(2 X offset)

Unaffected

Tests the state of the Z-bit and causes a branch
if Z is set.
As an example, it is used to test
equality following a CMP operation, to test that

Description:

the
source
generally,
previous

CMP
BEQ

Example:

following
a
BIT
operation,
to
test
that the
result of

operation

A,B
C

will
and

to C

and
the

zero.

;jcompare A
;branch if

branch
the

was

set

in the destination were also

set

bits

if A =

and B
they are

equal

(A -

B =

result

sequence

ADD
BEQ

A,B
C

;add A to B
s;branch if the

will

branch

A +

BPL
100000 PLUS OFFSET

BRANCH IF PLUS

08
T

0
|

0
L

]

[

OFFSET

[

MR-5234

Figure

Operation:
Condition

PC
Codes:

Description:

€

7-74

BPI,

offset)

Unaffected
Tests

the

state

the

N-bit

and

causes

if N
is clear,
(positive result).
complementary operation of BMI.

BPL

branch

the

BMI
100400 PLUS OFFSET

BRANCH IF MINUS

08
T

0
1

0
i

00
1

1
b

Figure

)

OFFSET

7-75

MR-5235

BMI

Operation:

€

offset)

if N

Condition Codes:

Unaffected

Description:

Tests the state of the N-bit and causes a branch
if N is set.
It is used to test the sign (most
significant bit) of the result of the previous
operation), branching if negative.
BMI 1is the
complementary function of BPL.

BVC
BRANCH IF OVERFLOW IS CLEAR

102000 PLUS OFFSET

08
T

)

OFFSET

Figure

Operation:
Condition

PC
Codes:

Description:

€

MR-5236

7-76

offset)

BVC

if V =0

Unaffected
Tests

state

the
the V

bit

operation

of the V-bit and causes a branch
is
clear.
BVC
1is
complementary

BVS.

BVS
BRANCH IF OVERFLOW IS SET

102400 PLUS OFFSET

08
!

)

OFFSET
i

]

MR-5237

Figure

7-77

(2 X offset)

BVS

1if V =1

Operation:

PC € PC +

Condition Codes:

Unaffected

Description:

Tests the state of V-bit (overflow) and causes a
BVS is used to
branch if the V bit is set.
previous
detect arithmetic overflow in the
operation.

BCC
BRANCH IF CARRY IS CLEAR
15

103000 PLUS OFFSET

¥
0

I
0

Figure

Operation:

€

Condition Codes:

Unaffected

Description:

Tests

the

state

if
¢
is
operation

MR.5238

7-78

BCC

offset)

1£

the

clear.
to

OFFSET

C-bit

BCC

and

causes

the

branch

complementary

BCS.

BCS
BRANCH IF

CARRY

IS SET

103400
PLUS OFFSET

]

1
1

{

)

OFFSET

)

MR-5239

Figure

Operation:

PC € PC +

Condition Codes:

Unaffected

Description:

Tests

the

7-79

BCS

(2 X offset)

1f C =1

state

C-bit

if C is set.
the result of

the

and

causes

It is used to test for
a previous operation.

branch

carry

7.2.5.2 Signed Conditional Branches -- Particular combinations of
the condition code bits are tested with
the
signed
conditional
branches.
These
instructions are used
to
test the
results of
instructions

(two's
Note

in
which
the
complement) values.

that

unsigned

the

sense

signed

comparisons

that

arithmetic
largest

operands

the

sequence
077777
077776

were

comparisons

values

signed
is

considered

differs

16-bit,
follows.

from

two's

signed

that

complement

positive

000001
Zero

000000

177777
177776

negative

smallest

100000

100001

whereas

unsigned

16-bit

arithmetic

the

sequence

considered

highest

177777

000002

000001

lowest

000000

BGE
BRANCH IF GREATER THAN OR EQUAL

002000 PLUS OFFSET

(TO ZERO)
15

08
T

0
1

0
I

0
1

]

0
1

1
1

Condition

Codes:

Description:

€

00
L

[

Figure

7-80

offset)

]

OFFSET

Operation:

MR-5240

BGE

NAVL V=20

Unaffected
Causes

branch

and

are

either

both

clear

or both set.
BGE is the complementary operation
to
BLT.
Thus
BGE will
always
cause
a
branch
when
it
follows
an
operation
that
caused
addition of two positive numbers.
BGE will also
cause a branch on a zero result.

BLT
002400 PLUS OFFSET

BRANCH IF LESS THAN (ZERO)
08

]

{

OFFSET

Figure

PC € PC +

Operation:
Condition

Codes:

Description:

7-81

{

MR-5241

BLT

(2 X offset)

if NXFV =1

Unaffected
Causes

a branch if the "Exclusive Or" of the N
and V bits are one.
Thus BLT will always branch
following an operation that added two negative

numbers,
even
1if
overflow
occurred.
In
particular, BLT will always cause a branch if it
follows
a
CMP
instruction
operating
on
a
negative source and a positive destination (even
if overflow occurred).
Further, BLT will never
cause a branch when it follows a CMP instruction
operating
on
a
positive
source
and
negative
destination.
BLT will not cause a branch if the
result
of
the
previous
operation
was
zero
(without overflow).
BGT
BRANCH IF GREATER THAN (ZERO)

003000 PLUS OFFSET

OFFSET

Figure

7-82

MR-5242

BGT

Condition Codes:

Unaffected

Description:

Operation of BGT is similar to BGE, except BGT
a branch on a zero result.
will not cause

PC < PC + (2 X offset) if z \/ (N:NFV)

Operation:

BLE
BRANCH IF LESS THAN OR EQUAL (TO ZERO)

003400 PLUS OFFSET

00
T

]

OFFSET
1

Figure

7-83

MR-5243

BLE

if z \/ (NXAFV) =1

(2 X offset)

Operation:

PC < PC +

Condition Codes:

Unaffected

Description:

Operation is similar to BLT but in addition will
cause a branch if the result of the previous
operation

was

zero.

7.2.5.3 Unsigned Conditional Branches -- The unsigned conditignal
operations

result

the

considered

are

operands

which the

testing

for

means

provide

Branches

comparison

unsigned

values.
BHI

BRANCH IF HIGHER

15
1

OFFSET

101000
PLUS OFFSET

MR-5244

Figure

Operation:
Condition

PC
Codes:

€

7-84

BHI

offset)

and

Unaffected

Description:

Causes

branch

the

neither a carry nor
happen in comparison
the source has
destination.

operation

a
zero
result.
(CMP) operations

higher

unsigned

caused

This will
as long as

value

than

the

BLOS
BRANCH {F

LOWER OR SAME

101400
PLUS OFFSET

08
¥

0
L

0
Il

]

0
1

0
|

0
1

1
1

00
I

[

}

1
L

[

OFFSET

BLOS

MR-5245

Operation:

€ PC +

Condition Codes:

Unaffected

Description:

Causes

(2 X

offset)

branch

the

C\/

either a carry or a 2zero
complementary operation to

operation

caused

result.
BLOS is the
BHI.
The branch will

occur
in comparison operations
source
1is
equal
to,
or
has
a
value than the destination.

as long as the
lower
unsigned

BHIS
BRANCH IF HIGHER OR SAME

0
L

103000 PLUS OFFSET

0
i

[

PC <« PC +

Condition Codes:

Unaffected

1is

]

7-86

1§

[

MR-5246

if C = 0

instruction

same

the

BHIS

(2 X offset)

Operation:

BHIS

OFFSET

mnemonic

Figure

Description:

This

BCC.

included only for convenience.

BLO

BRANCH IF LOWER
15

0
1

103400
PLUS OFFSET
T

0
[

1
1

1
L

PC € PC +

Condition Codes:

Unaffected

Description:

BLO
is

Operation:

[

OFFSET

(2 X offset)

same

if C =1

instruction

BCS.

included only for convenience,

This

mnemonic

7.2.5.4 Jump & Subroutine Instructions -- The subroutine call in
the microprocessor provides for automatic nesting of subroutines,
reentrancy, and multiple entry points.
Subroutines may call other

subroutines

(or

indeed

themselves)

to any level

of nesting without

making special provision for storage of return addresses at each
level of subroutine call.
The subroutine calling mechanism does
not
modify
any
fixed
1location
in
memory,
thus
providing
for
reentrancy.
This allows one copy of a subroutine to be shared
among

several

interrupting

processes.

JMP
JUMP

0001DD

0
L

0
N

0
|

]

0
L

0
1

]

0
1

0
L

0
"y

<€

Condition Codes:

Unaffected

Description:

JMP

d
)

Figure 7-88
Operation:

d
1

{

JMP

d
|

HreRes

(dst)

provides

flexible

program

branching

than provided with the branch instructions.
Control may be transferred to any location in
be
can
and
limitation)
range
(no
memory
the
of
accomplished with the full flexibility
addressing modes, with the exception of register
Execution of a jump with Mode 0 will
mode 0.
cause an "illegal instruction" condition, and

will cause the CPU to trap to vector address
(Program control cannot be transferred to
four.
Register deferred mode is legal
a register.)
and will cause program control to be transferred
to the address held in the specified register.
Note that instructions are word data and must
from an even-numbered
therefore be fetched
address.

Deferred

index

mode

JMP

instructions

permit

transfer of control to the address contained in
table of dispatch
a selectable element of a

vectors.

Example:
JMP

FIRST

;s Transfers

First

JMP

@LIST

;Transfers

location

First:
cesee

List:

FIRST

;jpointer

JMP

@(sP)+

;Transfer

and
the

pointed

LIST

FIRST

the

location

top

remove

the

pointed

the

stack,

pointer

from

stack.

JSR

JUMP TO SUBROUTINE

004RDD

15
H

0
[

0
N

1
1

0
1

(tmp)
<
register)

00
T

(dst)

(tmp

7-89

(Push

{

Figure

V (SP) €reg

)

Operation:

{

MR-5249

JSR

reg

internal

contents

onto

processor

processor
stack)

reg<PpC

(PC

holds

location

following JSR;

address
PC< (dst)

(PC

now

points

put

this
regq)

subroutine

destination)
Description:

execution of the
register

specified

JSR,
(the

the o0ld contents of
"LINKAGE
POINTER")

automatically
pushed
onto
the
and
new
linkage
information
register.
Thus
subroutines

the
are

processor
stack
placed
1in
the
nested
within

subroutines to any depth may all be called with
the
same
linkage
register.
There
is
no
need
either to plan the maximum depth at which any
particular

subroutine

will

called

include instructions in each routine to save and
restore the linkage pointer.
Further, since all
linkages are saved in a reentrant manner on the
processor stack,
execution of a
subroutine may
be
interrupted,
and
the
same
subroutine
reentered

routine.

and

executed

interrupt

service

Execution of the initial subroutine can then be
resumed when other requests are satisfied.
This
process
(called
nesting)
can
proceed
to
any
level.
A
subroutine
<called
with
a
JSR
reg,dst
instruction can access the arguments following
the call with either autoincrement addressing,
(reg)
+,
(if
arguments
are
accessed
sequentially) or by indexed addressing, X(regqg),
(if accessed in random order).
These addressing
modes may also be deferred, @(reg)+ and @X(reg)
if the parameters are operand addresses rather
than the operands themselves.

JSR
PC,
dst
1is
a
special
<case
of
the
microprocessor
subroutine
call
suitable
for
subroutine
calls
that
transmit
parameters
through the general
registers.
The SP and the
PC are the only registers that may be modified
by this call.
Another special case of the JSR
instruction
is
JSR PC, @(SP) + which exchanges the top element
of the processor stack and the contents of the
program counter.
Use of this instruction allows
two routines to swap program control and resume
operation
when
recalled
where
they
left
off.
Such routines are called "co-routines."

Return

from

instruction.

into
the
processor
Example:

SBCALL

SBCALL+4

SBCALL+2+2M:

—» CONT

SBR

subroutine

the

ARG

INSTRUCTION

MOV(R5)+,dst]l &—

contents

RTS
reg

—

the

SBR

loads

done

PC and
pops
the top element of
stack into the specified register.
R5,

reg

JSR

RTS

SBCALL

CONT

SBCALL+4

n-2

SBR

MOV (R5) +,dst2
MOV (R5)+,dst2

EXIT

MOV (R5)+,dstM
OTHER INSTRUCTIONS

RTS RS

SBCALL+2+2M
CONT

CONT

n-2 EXIT

JSR R5,

SBR

STACK

(SP)

AFTER:

DATAO

SBR
DATAO

PC+2

JSR PC,

BEFORE:

(PC}

(P}

SBR

STACK

DATAO

PC+2

MR-5250

Figure

7-90

JSR

Example

RTS

00020R

RETURN FROM SUBROUTINE
15
0

T
L

T
)

00
r

|
MR-5261

Figure

Operation:

Description:

PC <€ (req)
(reg) <€ (sp)

7-91

RTS

Loads contents of register into PC and pops the
top

element

specified

the

processor

stack

into

the

Return from a non-reentrant subroutine 1is
typically made through the same register that
was used in its call. Thus, a subroutine called

with a JSR PC, dst exits with an RTS PC and a
subroutine called with a JSR R5, dst, may pick
up parameters with addressing modes (R5) +,
X(R5), or @X(R5) and finally exits, with an RTS
R5.

RTS R5

Example:

BEFORE:

(PC)

STACK

RTS RS
SBR
R7

DATA
0

(SP)

AFTER:

n+2

Rb5

O
DATA

MR-6262

Figure

7-92

RTS

Example

SOB
SUBTRACT ONE AND BRANCH (IF # 0)

077RNN

09
|

)

06
)

[

OFFSET

MR-5253

Figure

Operation:

Condition

(R)
-(2

Codes:

€«
(R)
-1;
X offset),

7-93

if
if

SOB

this result # 0
then
(R) = 0 then PC < PC

Unaffected

Description:

The

register is decremented.
1If it is not equal
zero, twice the offset is subtracted from the
(now pointing
to
the
following
word).
The
offset
1is
interpreted
as
a
six
bit
positive
to
PC

number.
This
instruction
provides
a
fast,
efficient
method
of
1loop
control.
Assembler
syntax is:

where

the

that

7.2.5.5
Traps
emulators,
I/0
interpreters.

-Trap
monitors,
A
trap
1is

software.

When

processor

and

stack

trap

the

SOB

control

instruction

the

cannot

forward

used

direction.

instructions
provide
for
<calls
to
debugging
packages,
and
user-defined
effectively an
interrupt generated by

occurs

processor
and

address
to which transfer
decremented R is not equal

transfer

(PC)

R,A

made

Note

Counter

SOB

the

contents

Status

replaced

Word

the

(PS)

the

current

are

pushed

contents

Program
onto

two-word

the
trap

vector containing a new PC and new PS.
The return sequence from a
trap involves executing an RTI or RTT
instruction which restores
the
o0ld
PC
and
old
PS
by
popping
them
from
the
stack.
Trap
instruction
vectors
are
1located
at
permanently
assigned
fixed
addresses.
EMT
EMULATOR TRAP

0
L

104000—-104377

0
Il

0
H

1
}

0
|

0
1

{

]

0
L

MR-5254

Figure

7-94

EMT

Operation:

Vv (SP) <PS
¥ (SP) <PC
PC<(30)
PS<(32)

Condition Codes:

Description:

N:
Z:
V:
C:

loaded
loaded

from

trap

from

trap

loaded
loaded

from
from

All

operation

vector

vector
trap vector
trap vector

codes

from

104000

104377

are

EMT
instructions
and
may
be
used
to
transmit
information
to
the
emulating
routine
(e.qg.,
function to be performed).
The trap vector for
EMT
the

word

at address 30.
The new PC is taken from
at address 30; the new processor status

(PS)

taken

Caution:
EMT
software
and
general use.

from
is
1is

the

word

address

used
frequently by DEC
system
therefore
not
recommended
for

PS
1

PC 1

STACK

1
DATA

(32)

(30)

BEFORE:

AFTER:

DATA1
PS
1

n—4

PC1

MR-52565

Figure

7-95

32.

EMT

Example

TRAP

156

104400104777

]

1
|

MR-5256

Figure

Operation:

7-96

TRAP

trap
trap
trap
trap

vector
vector
vector
vector

Vv (SP) €PS
v (SP) €PC
PC«<(34)
PS<(36)

Condition Codes:

N:
Z:
V:
C:

loaded
loaded
loaded
loaded

from
from
from
from

Description:

Operation

codes

operation,

except

instructions.
is

address

from

TRAPs

that

EMTs

the

104777

104400
and

are

trap vector for TRAP

34.

Note: Since DEC software makes
EMT,
the TRAP
instruction
1is
general

are TRAP

identical

frequent use of
recommended for

use.

BPT
BREAKPOINT TRAP

000003

00
L

0
A

0
d

0
|

0
]

0
)

0
]

0
1

0
§

0
1

0
i

]

0
1

1
1

1
)
MR-5267

Figure

Operation:

7-97

BPT

Vv (SP) <PS

V¥ (SP) €PC
PC<(14)
PS<(16)

Condition Codes:

N:
Z:

loaded
loaded

from
from

trap
trap

vector
vector

V:
C:

loaded
loaded

from
from

trap
trap

vector
vector

Description:

Performs
a
address
of
The

is
cautioned
against employing
code
these
debugging
run
under
programs

user

000003

vector
trap
sequence
with
a
Used
to
call
debugging
aids.

trap
14.

aids.
(No

information

transmitted

the

low

byte.)

IOT
INPUT/OUTPUT TRAP

000004

)

]

MR-52568

Figure

7-98

IOT

from trap
from trap
from trap
from trap

vector
vector
vector
vector

v (SP) €PS

Operation:

Vv (SP) <PC
PC<(20)
PS<(22)

Condition Codes:

N:
Z:
V:
C:

loaded
loaded
loaded
loaded

Description:

Performs
a
trap
address of 20.
(No

information

sequence

with

transmitted

trap

the

vector

low

byte.)

RTI

RETURN FROM INTERRUPT

000002

00
1

0
L

0
)

]

0
_y

]

0
i

0
1

]

0
1

1
b

0
i

MR-5259

Figure

7-99

RTI

Operation:

Pc<(spP)
1

Condition Codes:

loaded

from

processor

stack

loaded

from

processor

stack

V:
C:

loaded
loaded

from processor
from processor

stack
stack

PS<(SP)
T

Description:

Used

routine,

exit

The

from the
pending,
not

from
PC

processor
the first

executed

interrupt

and

are

TRAP

restored

service

(popped)

stack.
If a trace trap is
instruction after RTI will

prior

the

trap.

RTT
RETURN FROM INTERRUPT

0
1

0
I

000006

0
1

]

0
1

]

MR-5260

Figure

Operation:

7-100

RTT

PC< (SP) T
PS<(SP)
T

Condition Codes:

Description:

7.2.5.6

N:
Z:

loaded
loaded

from
from

processor
processor

stack
stack

V:
C:

loaded
loaded

from
from

processor
processor

stack
stack

Operation
1is
the
same
as
RTI
except
that
it
inhibits a
trace
trap while RTI
permits
trace
trap.
If new PS has T bit set, trap will occur
after execution of first instruction after RTT.

Reserved

attempts

processor

expansion

Instruction

execute

Traps

1instruction

(reserved

These

codes

are

reserved

instructions)

caused
for

future

instructions

with

illegal addressing modes (illegal instructions).
Order codes not
corresponding to any of the instructions described are considered
to

reserved

instructions.

JMP

and

JSR

with

destinations are illegal instructions, and trap to vector
four.
Reserved instructions trap to vector address 10.

7.2.5.7
Halt Interrupt --HALT
interrupt
saves
the
address with PS = 340.

7.2.5.8

Trace

Trap

——

This is
PC
and

Trace

Trap

caused by the
PS
and
goes

enabled

mode

address

-HALT line. The
to
the
restart

by bit

four

the

and causes processor traps at the end of instruction execution.
The instruction that is executed after the instruction that set
the T-bit will proceed to completion and then trap through the
trap vector at address 14.
Note that the trace trap is a system
debugging aid and is transparent to the general programmer.

7.2.5.9
Power
Failure
Interrupt
-Occurs
when
-PF
1line
|1is
asserted.
Vector for power failure is location 24 and 26.
Trap
will occur if an RTI instruction is executed in power fail service
routine.
7.2.5.10

Interrupts

——

Refer

Table

5-3.

NOTE

the PS can only
of
four
Bit
indirectly by executing an RTI

instruction

with

desired

the

be
or

set
RTT

are

special

the

stack.

7.2.5.11 Special Cases T-bit -- The
the T-bit.

following

cases of

NOTE

The
traced
instruction
is
instruction after the one that set

the
the

An instruction that cleared the T-bit -Upon fetching
the traced instruction, an internal flag, the trace flag,
was
set.
The
trap
will
still
occur
at
the
end
of
execution of this
instruction.
The status word on the
stack, however, will have a clear T-bit.

An instruction that set the T-bit -- Since the
already set, setting it again has no effect.
will

T-bit was
The trap

occur.

instruction

trap

that

caused

performed

Instruction

and

the

Trap

entire

The

routine

for

the
service
trap
1is
executed.
If
the
service
routine
exits
with
an
RTI
or
in
any
other
way
restores
the
stacked
status
word,
the
T-bit
is
set
again,
the
instruction following the traced instruction is executed
and,
unless
it
is
one
of
the
special
cases
noted
previously, a trace trap occurs.

Interrupt

Trap

Priorities

case

multiple

trap and
interrupt conditions, occurring simultaneously,
the following order of priorities is observed
(from high
to low):

Halt Line
Fail Trap

Power

Trace

Trap

Internal

Interrupt

Request

External

Interrupt

Request

Instruction

Traps

Miscellaneous Instructions

7.2.6
HALT
HALT

000000

15
1

)

MR-5261

Figure

7-101

HALT

¥ (SP) €PS
V¥ (SP) €PC

Operation:

PC<restart
PS<340

address

Condition Codes:

Unaffected

Description:

The processor goes to the restart address after
placing the current PC and PS on the stack.
PS
is

initialized

340.

WAIT
WAIT FOR INTERRUPT

15
0

]

000001

00
1

MR-5262

Figure

7-102

WAIT

Condition Codes:

Unaffected

Description:

In WAIT, as in all instructions, the PC points
to
the next
instruction following the WAIT
instruction.
Thus when an interrupt causes the
PC and PS to be pushed onto the processor stack,
the address of the next instruction following
the WAIT is saved.
The exit from the interrupt
routine (i.e., execution of an RTI instruction)
will cause resumption of the interrupted process
at

the

instruction

following

the WAIT.

RESET

000005

RESET EXTERNAL BUS

15!
0

]

[

MR-5263

Figure

Condition Codes:

Unaffected

Description:

The

-BCLR

line

7-103

RESET

asserted

is
1loaded.
-BCLR
1is
transaction takes place.
not affected.

and

the

mode

negated
and
an
ASPI
PC, PS, and R0O--R5 are

MFPT
MOVE FROM PROCESSOR TYPE WORD
15

0
[

0
'

0
1

000007

0
]

[

Condition

Figure 7-104
Operation:

0
1

1
L

MFPT

Hnee

R0<4
Codes:

Unaffected

Description:

The

number

four

the

system

software

placed
that

in
the

indicating

processor

type

to
is

SBC-11/21.

7.2.7

Condition

CLN

SEN

CLZ

SEZ

CLV

SEV

CLC

SEC

CCC

scCcC

Code

Operators

CONDITION CODE OPERATORS

0002XX

]

o1]

MR-5266

Figure

7-105

Condition

7-71

Code

Operators

Description:

Set

and

clear

combinations

conditon

code

bits.

Selectable

these

bits

may

cleared

together.

Condition

code

bits

Mnemonic

Operation

CLC

Clear

000241

CLV

Clear

000242

CLZ
CLN

Clear
Clear

2
N

000244
000250

SEC

Set

SEV

Set

000262

SEZ

Set

000264

set

to
bits in the condition code operator
(Bits 0--3)
are modified according to the sense of bit four,
the set/clear bit of the operator; i.e., set the
bit specified by bit zero, one,
two, or three,
if bit four is a one.
Clear corresponding bits
if bit 4 = 0.

SEN

Set

all

CCC

Clear

all

Clear

operations

combined
CLC

(241)

000270
CCs

000277

CCs

and

000257

000243

Operation

*Combinations

may

000240

the
be

with

above

ORed

instructions.
ORed

Code

000261

SCC

NOP

corresponding

CLV

set

together

Clear
(code

and
242).

or
to

clear
form

represents

CHAPTER
THEORY

8.0
This

OPERATION

explanation
of
the
of view of the logic

SBC-11/21
designer.

GENERAL
chapter

provides
a
detailed
operation from the point

hardware
It
will
level.

useful

for

troubleshooting

the

device

the

chip

NOTE

The

negated

1inverse

signal

designated
by
the
"-"
character.
For
example,
RAS
is
normally
low
and
asserted
high
when
activated
and
the
~RAS would be normally high and asserted
low when activated.
This
convention
is
used throughout this chapter. The LSI-11
bus signals will remain consistent with
the
The

SBC-11/21

standard

functional

bus

conventions.

block

diagram

(Figure

8-1)

provides

overview of
the module functions and how they are
related.
The
main components of the single board computer are shown on sheet 1.
The

single
board
computer
is
comprised
of
the
microprocessor
interconnected
to
the Serial
Line Units,
RAM memory,
ROM memory
and
the
Parallel
I/0
Interface via
the on-board TDAL bus.
The
TDAL bus can access the LSI-11 bus
(BDAL bus)
by the Bus Control

function shown by broken lines and is for reference only.
Also on
sheet 1 is the Address bus, the Memory Address Decode function and
the Interrupt Control function.
The microprocessor
support
functions are described on
by

broken

Control,

1lines

for

Ready,

microprocessor.

reference

DMA

The

functions
sheet 2.

and

IAK

only.

Halt

and
The

the
LSI-11
interfacing
microprocessor is shown

The

Power

functions

Data

In,

Sync,

are

used

Up,

are

Read/Write,

Timeout

The
the
its

functional descriptions used in this chapter will first define
microprocessor
and
the
input/output
signals
associated with
operation.
The support
functions,
the LSI-11
bus
interface

8.1

single

board

computer

LSI-11

the

Bus Control functions
microprocessor.

and the remaining
in detail.

the

Clock

and
the

functions
described

interface

Clock,
used

devices

bus

are

also

MICROPROCESSOR

The microprocessor 1is contained within
Figure
8-2.
There
are
eight
16-bit

a 40-pin LSI chip shown in
general
purpose
registers

(RO--R7)

Stack

which

operates

operates
as
the
microprocessor
purpose status register contains

the

Pointer

(SP)

and

Program
Counter
(PC).
A
special
the current Processor Status Word
8-1

THALT

All

TEVNT

" .

- *

XDL2

CAS

PC3

INTERRUPT

L—-—-

_ IAK

%
AD3-AD15

TO SHEET
2

—

2 BDAL 00-15
-

CONTROL

KK TDAL 00-15 X

AD1

CSLIP .

BCLR

E40

-CSQB

(_-sELe -

—

00-07

_WLB

-WHB_|

RAM
-READ| vEMORY

_ 3
00-15

—_— —

—

-CSQB

FROM

BDALO, 1,2

_READ

_WHB

-RSYNC

SHEET 2

BDALDO, 1,2

DCO04

ZZSTOCOL

| BDIN L

BDIN L
BDOUT L |

-WLB

-SEL6

BDOUT L

BWBT L

BRPLY L

BWTBT L

BRPLY :—l
7

ADDRESS BUS

AD1-AD13

FROM

-CSRAM

E25

SHEET 2"

" PARALLE
L L
o

_READ | E&7

_CSKTA
-CSKT8B

PCO

-CSPL| INTERFACE

DECODE |~opam

FROM DCLO

I (SEE SHEET 2) I \

| E——
-CSDL1 J

ADDRESS | -CSPL

1
A

MEMORY

M22

_RSYNC

FROM
SHEET 2
BUS

00-15 2

_WLB

-CSDLO

BEVNT L

”

XDL2

TREAD

LBS7

DATA ADDRESS BUS TDAL 8-TDAL 12

)

(_csbL2| E66

Egg

BHALT L

EG5

-CSDi.1

LATCH

BIRQA L

TEVNT
1

['pp)5 —A
INTERFACE
AD2_ o| UNITS
1 &2 |——

AD2
ADDRESS

EF;;)CESSOR

CONTROL

1 THALT

DL:IL;T SERIAL LINE XDL 1

FROM

SHEET 2
MICRO

)

BCLR |

DCLO

ROL1

RBS7

2:;

:gt;
PCO

BCLR

-READ

-BCLR | MODE

TM| REGISTER [& TDALS8, 11,13, 14,15
2®
SHEET

CONTROL

-wie |

rom/RAM

_WHB | MEMORY

_CSKTA

SOCKETS

00-15

-cskTB

DATA ADDRESS BUS TDAL 00-TDAL 15
MH 60739

Figure

8-1

SBC-11/21
(Sheet

Functional
1

8-2

Block

Diagram

PROCESSOR CONTROL SIGNALS

SEL 1 g

BWTBT L A

-RAS

BDIN L

-CAS

BDOUT L

-P|

-SEL 1
245

R/WHE
\RMWLE

-BCLR

T CLK SP

TSYNC

~C SYNC

B:::LSY L
TDIN
REPLY

\?IE*?TDE/

SYNC

TDOUT TIMEOUT
*

—DRRPLY

[_.

T::(;;
-IAK

2;:(:;1_
BBS 7

_READ

]

RBS? -

RSYNC

TREAD _

———

m. (B)gfsleHOL

-DMG

§
@

-BCLR

;
]

IAK DIN
DMG

DMG

-TMRP

SEL 1

SYNC

TIAKO _|

SELO

-RAS

CAS

DMA

-BCLR

-CDMRQ ="— —= =7

COUT

BDMRL

M‘

* BDMGOL

TREAD

TMER

[

oflq
CAS

-CTMER I
—ol

HALT

SEL 1

SELO

-BCLR

I MICRO

RAS

1AK

Ot
_BCLR

:DNATA

> BIAKO

TDAL 12|
¢

TMRE
SYNC

oLk P

TOLKSP
J

PROCESSOR CONTROL SIGNALS

CAS
-BCLR

BPOKH

BDCOK H

:YMN;ZP

€As I o lock

DCLO

-BCLR | coNTROL

PUP |

CLOCK

|
READY

READY

~—

-1AK

SCLK

DCLO —& TO SHEET 1

-TCLK

PUP

)
fi}

'
:

-DRRPLY

|DLCLK
o 10 SHEET 1

| (SEESHEET 1) |

COUT
'—i(;:;?_.p

TCLKSP

| er up

| prOCESSOR
E64

IAKDIN

[

;

chzgis.fl?n

SIGNALS

POWER FAIL 4
L
PROCESSOR CONTROL SIGNALS

MR-6038

Figure

8-1

SBC-11/21

(Sheet

Functional
2

Block

Diagram

_CTMER

_PFAIL —2L6 )

ENCODED

TDAL

TDAL 13

TDAL
12

TDAL
11

+—

DAL 10

)

‘*"%%%%fifi%‘“"

ToaLr

Al-2

TDAL 15

Al5

INTERRUPT4 —213

INPUTS

—
e

¢ a0AL

TDAL 06

mol

TDAL 05

_CDMRQH —AL0_,

TDAL 04

TDAL 03

TDAL 02

~TCLK ————»

XTLO

L "

MICROPROCESSOR

E64

TDAL
01

TDAL 00

—
e
)

SELO
SEL1

READY —READY]

R WHE

_pup —LUP

» | TRANSACTION

TYPE

nwis

" | CONTROL

—RAS

—CAS
P

« | TRANSACTION
~ CONTROL

CouT

—BCLR

»RESET

» | STROBES

MR-6634

Figure

8-2

SBC-11/21

Microprocessor

(PSW).
The
operating
characteristics
of
the
microprocessor
are
affected
by
the
mode
register.
It
1is
discussed
1in
detail
in
section 8.2.
8.1.1
Microprocessor Initialization
The microprocessor will initialize the SBC-11/21 module during the
power up sequence or whenever the RESET instruction is executed.

8.1.1.1
RESET -- The RESET instruction asserts the -BCLR output
and this clears or
resets the control
1logic of the module to an
initial state. The microprocessor loads the Mode Register from the
TDAL bus
with
the
Mode
Register
Control
data.
The
LSI-11
bus
transceivers are disabled when -BCLR is asserted. The RCVIE bit of
the RCSRs and the XMITIE, MAINT and XMITBRK bits of the XCSRs are
reset
in
the
Serial
Line Units
(SLU).
The port C buffer output

lines

the

buffers

are

Parallel
output

turned

off

Assert

Priority

any

during

Interrupts

disturb

the

I/0

are

the

connectors,

reset.

DMA

requests.

any

internal

and

reset

instruction

except

completely

PUP

then

reset.

negated,

performs

starting

The

the

and

the

into

the

service

any
instruction is

interrupts

The

normally

PUP

input

registers

interrupt

inputs

high,

8.1.2

Clock

-TCLK

MHz

crystal

time

base

(COUT).

then

port

The

LED

negated

and

performed

instruction

service
does

not

Line

Program
the

The

module

for

the

Units

the

output

asserted.

described

BDCOK

goes

The

are

loads

the

376

into

location

Status

are

asserted,

microprocessor

processor

(R7),

Processor

registers

BPOK

high.
The

Counter

(ASPI)
or
DMA

(SLU)
and

RESET

Word

set

transaction
is
performed
to
requests
before
the
first

remains low for all operations.
If PUP
is
present
transaction
1is
terminated
and
the

the

initial

The

and

fetched.

asserted
internal

transactions.

the
Stack
Pointer
(R6)
and
340.
An
Assert
Priority
In

high.

(PUP)
input
goes
from
low
to
applied and this initiates the

manner

delay,

NOP

port

set

RESET

output

-BCLR

bus

output

The

same

are

registers.

Serial

After

ten

address

the

Also,

they

-BCLR

Power Up
is first

-BCLR

high.

transaction

PSW

sequence.

cleared

The

(ASPI)

8.1.1.2
Power Up -- The
high when the 5.0 V power
power

set

and

the

reset

undetermined
microprocessor

state.

The

control

TDAL bus,
signals will

the
all

state.

Input

input

4.9152

oscillator.

MHz

This

clock

the

microprocessor

and

COUT

pulsed

every

once

can

represent

either

the

type

transaction.

whenever

the

-TCLK

three

input

for

four

The

that

comes

from

used

for

input
is

the

source

the
the

19.6608
internal

the

clock

microcycle

and

-TCLK

input

microprocessor

pulses

will

output

microcycle

depending

halt

stop

disabled.

8.1.3
Ready Input
READY input
is normally high and will not
interfere with
the
microprocessor
transactions
in any way.
However,
when this
input
is
held
low,
a
single
microcycle
slip
occurs
during
every
transaction.
When
READY
is
clocked
with
COUT,
while
RAS
is
The

asserted,

then

the

microprocessor

time
the
input
is
placed
in
an
idle

pulsed.

This

state

either

asserted

received

8.1.4
The
the

Microprocessor

data

Control

microprocessor controls the
use of eight microprocessor

listed
RAS,

wait

below

CAS,

PI,

with

COUT,

description
and

BCLR

for
logic
transitions.
The
steady
state
logic
signals

signals.

will

slip

allows

the

until

the

bus.

microcycle

microprocessor

peripheral

every

device

has

Signals
functions

the

control signals.
of the functions

are

transaction

SBC-11/21

through

These signals
they perform.

control

R/-WLB,
R/-WHB,
SELO
wused
as
transaction

strobes

are
The
used

and
SELl1
are
type
control

8.1.4.1

Row

Address

TDAL bus
interrupt

acknowledge

signal

data

onto

used

For

Write

The

leading

are

read

the

Address

The

bus

Strobe

(CAS)

edge

the

Priority

(PI)

that

The

the

TDAL

control

TDIN,

Read/Write

the

request
of

bus

lines

the microprocessor.

acknowledge

that

the

that

READ

data

placed

the

signal

into latches which

PI.

The

data

edge

leading

the

TDAL

bus

lines

during

used

edge

also

R/-WLB)

These

leading

TDOUT

(R/-WHB

and

TWTBT

are

both

transactions,

and

Fetch

and

Read/Write

the

Write

enable

the microprocessor to read the interrupt inputs AI-0 to AI-7
to initiate IAK, RESTART, POWER FAIL, or DMA transactions.
8.1.4.4

the

edge

trailing

interrupt requests

The

stable.

lines.

read by

wused

edge

stable

removed after a specified time.

assertion

acknowledge

transactions

used

1is

transactions.
During
strobes
the
interrupt

data

transactions was

and to strobe

during

that

1leading

address

the

12--08

transactions

the TDAL bus,

TDAL

microprocessor data will be

used

that

acknowledge

during Read and Fetch

8.1.4.3

(RAS)

during
Read/Write
and
Fetch
transactions
the
leading
edge

Column

8.1.4.2

Strobe

acknowledge

used

signal

control

asserted

transactions

signals.

enable

and

high

For

two

signals

enabling

Read

and

the

Fetch

the TDIN control

circuits. During Write transactions the TDOUT and TWTBT control
circuits are enabled when either or both signals are asserted low.
are
circuits
TWTBT control
1low the
is asserted
If only one

enabled

occurs

for

8.1.4.5

indicate

the

leading

either

edge

high byte

CAS

a Write

and

low byte.

(SELO and SEL1l)

Select Output Flags
the

transaction

being

DMA

transaction

byte

transaction

-- These two signals

performed.

When

both

When

SEL1

are

1low,

Read, Write, ASPI or NOP transaction is selected and when both are
high,

high
SELO

the

Fetch

low an

transaction

IAK

selected.

transaction

selected
is

being

low

and when SEL1l

and

is high

SELO

and

performed.

8.1.4.6 Bus Clear (BCLR) -- This signal 1is used to reset the
It is only asserted during the
control logic and generate BINIT.
of a RESET instruction.
execution
the
during
and
Power Up sequence
Clock Out
8.1.4.7
e
microcycl
every

(COUT) -- This signal 1is asserted once for
1is wused to time the microprocessor
and

transactions.

8.1.5

Microprocessor Transactions

transactions to support
and the interrupt
access,
the instruction set, direct memory
Read, Write, DMA,
Fetch
are
ions
structure. The types of transact
IAK transaction
or
ad
Fetch/Re
normal
A
IAK, ASPI, and Bus NOP.

The microprocessor

performs

six

types of

requires

either

can

take

one

many

signal is asserted
used
to
transfer

two

microcycles

required

before

and

extended

timeout

once for every microcycle.
information
and
data
via

transactions

occurs.

The
the

The

COUT

transactions are
TDAL
bus
which

interconnects
all
1local
devices
and connects
them to
the LSI-11
bus
interface.
The
operation
of
the
transactions
1is
described
below.

8.1.5.1
Fetch/Read -- This transaction is used to either fetch an
instruction
or
read
data
for
the
microprocessor.
The
data
may

originate from the on-board memory, I/0 device, or from the LSI-11
bus.
The
microprocessor
control
signals
for
the
transaction are
described by Figure 8-3. The R/-WLB and R/-WHB control signals are
asserted.
the Fetch
Read
The

The SELO output
transaction and

is high and the SEL1l output is
both of these outputs are
low

low
for

for
the

transaction.
following

The

sequence

events

microprocessor

when

the

Memory

The

data

places

transaction

received.

then

Address

takes

the

place.

address

initiated

circuits

1is

received

The

microprocessor

and

the

onto

the

latched

assertion

TDAL

SYNC.

RRPLY

TDAL

bus

after

accepts

the

data

and

CAS,

bus
into

1is

negates

TDIN.

Interrupt

and

DMA

requests

while PI is asserted,
when PI 1is negated.

and

are

latched

into

the

set

microprocessor

NOTE

write

transaction

read

always

preceded

transaction

except

when

the

microprocessor
pushes
onto
the
stack.
Therefore,
each
write
consists
of
at
least four microcycles,
assert address,
read
data,
assert
address,
and
write
data.
Write

microprocessor

8.1.5.2

peripheral

device.

transaction are
control
signals
writing a byte,
SELO

and

This

SEL1

transaction

memory,
The

local

used

I/0

microprocessor

write

device

control

data

from

the

LSI-11

bus

signals

for

the

described by Figure 8-4.
The R/-WLB and R/-WHB
are
asserted
low when
writing
a
word
and
for
either the high or byte signal is asserted. Both

control

signals

are

negated.

FETCH/READ TRANSACTION

READ DATA ———»

:‘I:

j¢————————— ASSERT ADDRESS

NOTE 2

couT

’

TDAL

ADDRESS

00—15

Al-0—-Al-7

(

INT AND DMA

(

DATA IN

REQUEST

)

\
\

CAS

/__

_____________ F———-

SELO

NOTE 1

|
T

fl\‘

SEL1_\
==

}

SYNC

RRPLYH

TDIN

]

)

‘L

NOTES:

1.SELO IS HIGH FOR FETCH TRANSACTIONS
AND LOW FOR READ TRANSACTIONS.
2. LSI-11 BUS TRANSACTIONS CAN CAUSE THIS
PORTION OF TIME TO SLIP UNTIL THE
DEVICE RESPONDS OR TIMEOUT OCCURS.
MR-6635

Figure

The

following
o

sequence

8-3

events

The

microprocessor

the

state

The

address

the

When

the
is

CAS

1is

take

places
R/W

into

address

causes
the

the

TDAL

TWTBT

Memory

Address

bus

and

asserted.
circuits

SYNC.

asserted,

and

Transaction

place.

the

lines

latched

assertion

transactions

Fetch/Read

left

TWTBT

asserted

for

1is

negated

byte

for

transactions.

word

The
data
1is
placed
on
asserted and is written
TDOUT is negated.

the
into

When
the
addressed
device
TWTBT signals are cleared.

TDAL
bus
before
TDOUT
is
the addressed location when

negates

BRPLY,

the

SYNC

and

The DMA requests are detected while PI 1is asserted and
latched into the microprocessor when PI is negated. No
other
interrupts are read by the microprocessor during
write transactions.

WRITE TRANSACTION

j———ASSERT ADDRESS

couT

WRITE DATA
NOTE 3

A|.0_A|-7:X

{

DMAREQUEST

SEL1

SYNC

/—

NOTE 1

ISR
] =

NOTE1

SELO

S T VN i R

R/—WHB_

R/—WLB—‘

s e

CAS

)

\___.

-————-—-—-——*— — T— —
e vl ———

RAS

DATA OUT

ADDRESS

TDAL

e ey

)

e ——

RRPLYH

—

TDOUT

TWTBT

NOT
_NoTE2
_ _ _ _ ___]_.

NOTES:

1. R/—WHB OR R/—WLB CAN BE HIGH WHEN
PERFORMING A WRITE BYTE TRANSACTION.
2. TWTBT IS LOW FOR WORD TRANSACTIONS.
3. LSI-11 BUS TRANSACTIONS CAN CAUSE THIS
PORTION OF TIME TO SLIP UNTIL THE DEVICE
RESPONDS OR TIMEOUT OCCURS.
MR-6636

Figure

8-4

Write
8-9

Transaction

8.1.5.3

TIAK

request

interrupt

The

during

detected

was

previous read transaction and the microprocessor initiates an IAK
transaction as described by Figure 8-5. The R/-WHB and R/-WLB
control signals are asserted high and CAS, PI, and SELO are
asserted low for the

the

acknowledged

the

vector

and

wused

are

reset

represent

12--08

The TDAL bits

transaction.

input

interrupt

the

request. For local interrupts TDAL bits 07--00 are ignored because

interrupts,

address

vector

the

address

microprocessor.

read

from

the

For

bus

LSI-11
using

bus

TDAL

bits 07--02. TDAL bus bit 12 is set low for this type of IAK and
directs the control 1logic to initiate an LSI-11 bus IAK
transaction. The TDIN signal is asserted for the transaction and
the TIAKO output acknowledges the interrupt. The requesting device
then places the vector address on the low byte of the bus and

The microprocessor stops slipping microcycles,
asserts BRPLY,
It then negates TIAKO on
negates TDIN, and accepts the vector.
the trailing edge of RAS and continues to the next transaction.
SEE NOTE

TDAL 12-08

TDAL 07-00

INTERRUPT REQUEST DATA

RAS
SELO

:\Ir>< 8

CouT

|<——

VECTOR IN

[
\

IAKDIN

\
—~

SEL1

TIAKO
\

TDIN

—

—~IAK

/
NOTE:

LSI-11 BUS TRANSACTIONS CAN CAUSE THIS
PORTION OF TIME TO SLIP UNTIL THE DEVICE
RESPONDS OR TIMEOUT OCCURS.
MR-6637

Figure

8-5

IACK

Transaction

read during a previous
8.1.5.4 DMA -- The DMA request was
transaction. The microprocessor will acknowledge the request by
tri-stating the TDAL bus as shown in Figure 8-6. The SELO and SEL1
outputs are asserted

The

relinquished.

until

indicate

that

transaction will

the DMA transfer

couT /_—\

TMAL T -\

bus mastership has

been

will

then

continue with no
The

is completed.

negate SEL1
control output
to
mastership,
followed
by
the
transaction is not a fetch.

the

microprocessor

indicate
that
negation
of

it
1is
resuming bus
SELO
if
the
next

/__—\____

TRI-STATE

0016 o
S

interruptions

Ao\

[__seEnote

R/-WHBTM ~

TRI-STATE

\.
r

SELO

SEL1

DMG

TDMGO

j—_\

RDMR

RSACK

‘\\

NOTE:

Al-0 1S ASSERTED LOW UNTIL BSACK IS NEGATED
AND NO OTHER RDMR IS BEING ASSERTED.
MR-6638

Figure

8-6

DMA

Transaction

8.1.5.5

ASPI —-- The Assert Priority In

RESET

the

allow

the

microprocessor

asserted

and

the

in Figure 8-7.

shown described
interrupts

transaction.

DMA

requests.

0015

recognize

and

RAS

and

oA
¢
ALO-ALT
_(

pending

for

are

the

\.—

)

\
/

R/-WLB_ __ 3

T T T T\

——

any

outputs

[T
TT

SELl—

AND DMA)
( INT
ML

CAS

SELOT

sequence

negated

)

R/—WHBTM—————

latch

R/-WLB

outputs. are

TRI-STATE

RAS

R/-WHB

\
DAL~

power

the

The CAS and PI outputs are asserted

The

SEL1,

SELO,

COUT—}

instructions

WAIT

and

transaction is used

(ASPI)

MR-6639

Figure

8.1.5.6

8-7

ASPI

Transaction

NOP —-- The Bus NOP transaction performs no operation and

is used during the power-up sequence oOr
intentionally introduces a delay into the

if the programmer
program. The AI-O0

The
through AI-7 inputs are tri-stated to prevent interrupts.
SEL1
and
SELO
the
and
d
asserte
R/-WHB and R/-WLB outputs are
outputs are taken low. The RAS, CAS, and PI control strobes are
inhibited during the transaction as shown in Figure 8-8.

COUT

[)

——
TDAL == ===~

00—15

ALo-Al7

PREVIOUSLY LATCHED DATA

TRI-STATE

—_—————

RAS

f——————

—

e oo—

\
CAS

R/-WHBTMTM
R/-WLB_.

— ~ ~

______

SELO

—_

_ _ . _ -

MR-6640

Figure

8.2
The

MODE
mode

8-8

BUS

this

time

sSequence
the

-BCLR

Transaction

CONTROL

internal

define the operating mode of
register is written into from

power

NOP

when

output

the
the

reset
low

microprocessor

factory

following

set

force

the

used

microprocessor. The 16-bit mode
TDAL 00--15 data lines during a

instruction

and

the

mode

The mode
register
1logic
(Figure 8-9)
has
that are enabled when the —-BCLR input goes

are

executed.

During

loaded.

five
tri-state drivers
low. TDAL bits 11 and 8

microprocessor

operate

the

mode.

The

microprocessor

clock

mode

selected.

The

microprocessor pulses the COUT output once for every four
XTL1l input pulses during DMA and Interrupt transactions.
For all other transactions, the microprocessor pulses the
COUT output once for every three XTL1l input pulses.
o

The

standard

microcycle

wuses

Interrupts
and
transactions.

mode

four

XTL1l

three

XTL1

selected.

The

1input

periods

for

input

periods

for

standard
DMA

all

and

other

ted. The normal
The normal Read/Write mode is selec
control 1lines
write
read/
the
Read/Write mode establishes
of -RAS and
tion
asser
(R/-WLB and R/-WHB) prior to the
remain valid after the negation of —-CAS.

The

memory

static

mode

and

selected

therefore

dynamic memory chips may be installed on the module. The
refresh function is disabled.

The memory addressing is limited to 64K bytes.

The bus consists of 16 bits.

The

user

transactions

mode

Status Word.

E44

M28

15V ———1]

with

selected.

automatic

M27

M25

This

test

mode

the

performs

Processor

TDAL 15

[—

M26

M24

TRI-STATE
DRIVERS
E42

TDAL 14
TDAL 13
11
|TDAL
8
— — TDAL

MR6641

Figure 8-9

Mode Register Control

the user and
The status of the TDAL bits 13--15 are selected by
rocessor.
microp
the
for
ses
addres
t
restar
determine the start and
The start address is the location of the first fetch after power
a HALT
up and the restart address is the location of a fetch after
pt.
interru
HALT
the
of
ion
assert
the
or
d
execute
instruction is
the
of
s
ol the statu
The wire wrap pins M27, M26, and M25 contrce.
M28
pin
Wire wrap
TDAL 13--15 bits during the power up sequen

wire wrap pin
is pulled up to +5 Vdc and represents a one, while Pins
M27, M26,
M24 is connected to ground and represents a zero.
listing
the
according to
and M25 are jumpered to either M28 or M24 restar
the
for
s
addres
t
in Table 8-1 to select the start and
microprocessor.

Table

8-1

Start

Address

Wirewrap Pins
Bit

Start

Bit

Restart

Bit
M26

172000

173000

173004

000000

000004

1
0

0
1

010000
020000

010004
020004

040000

040004

100000

100004

140000

140004

Connection
Connection

to
to

The

Address

M27

8.3

Configurations

M25

M28
M24

172004

=1
= 0

INTERRUPT CONTROL

interrupt

8-10.

Studying

logic,

presented later
The elements of

Address

Five

this

a block diagram,

diagram

will

in this section easier

this

illustrated

the detailed
to follow.

make

Figure

explanation

include:

scheme

flip-flops

which

the

1latch

interrupt

lines.

REVNT

Wire

interrupt

Outputs

following

signals.

interrupt

five

Level
DMA

PFAIL

Power

OR-ed with
RDL1
XDL1
RDL2
XDL2

BEVNT,

interrupt
interrupt

request.
request.

latches,

which

described

latch

the

above

signals:

IRQ4

signals

synchronizing

latches

DMRQ

configurable.

Twelve

TEVNT

I/0 Port A
I/0 Port B

Level 7, maskable interrupt, configurable.
interrupt,
nonmaskable
CTMER,
Produces

BKRQ
HLTRQ
o)

OR-ed

Parallel
Parallel

PARQST
PBRQST

from

LSI-11

bus

interrupt

request

fail

the

nonmaskable

Interrupt

Interrupt Requests

interrupt

Acknowledge

from SLUs.

Decoder,

SLUl
SLUl
SLU2

Receiver Interrupt Request
Transmitter Interrupt Request
Receiver Interrupt Request

SLU2

Transmitter

8-15

Interrupt

Request

wire

The

operation

centers

AI-0

serves

AI-1

around

eight

microprocessor

input

AI-0
to AI-7,
driven
by
interrupt
signals,
either
indirectly, through the Interrupt Encoding PROM.

request

AI-4

DMA

are

request

driven

maskable

line

the

connected

output

directly

the

lines,

directly

Interrupt

DMRQ.

Encoder

interrupts.

AI-5 is driven by the VEC gate which detects the presence of the
LSI-11 bus interrupt on the outputs of the Interrupt Encoder. It
calls for a vector read transaction from the bus.

AI-6

power

fail

AI-7

1is

restart

driven

directly

the

Power

Fail

input

line

force

1line

force

trap.

driven

the

HALT

interrupt

trap.

O—=jD

MICROPROCESSOR

USER

SELECT

OTHER

PBRQST_|

DMRQ

LmiNPUTS

FLIP-FLOPS

———| ENCODING

LINES

| xoL2

2 RESETS

ADL1

XDL1 —j

2 RESETS

5Luz

MEMORY
512%4
ROM

INT

ACK

JRIAKO

TDAL 811

SELO—» pecope

Al-5

SELT |—m

{VEC}

RAS |l

IAK

cas

- 5
4

’

INTERRUPT

ACK

TDAL - 8-1

DECODER

MEMORY

32X8 ROM

4 RESETS

— — — — N
Al-1TO Al—4
- — = -

BUS

k—. XDL2 gn

SLUT

e
gl

o ROLI

| | l |

TDAL1I2}—»f

9 ADDRESS | INTERRUPT

ROL2

RESETS

SELTl—»|

Al-0

PRIORITY

(12)

SELO

Al—6

pmero bivecooioe
1l
IRQa | syncHrRONIZERS | 0000 | 2

RDL2

Al-7

PFAIL

oCMRQI INTERRUPT

———% ()

o BKRQJ

HALT

T P FAIL

SIGNALS

ARUSTLATCHING
oPPARQST

ocsic |

REVNT

HLTRQ

HALT

MR 7223

Figure

8-10

SBC-11/21

Interrupt

Logic

The

microprocessor

reads
the
AI-0
to
AI-7
input
1lines,
and
interrupt
priority
according
to
Table
8-2.
1In
addition,
the state of AI-1
to AI-5
is
reproduced
on TDAL
12-8
lines during the Acknowledge cycle. TDAL 11-8 lines are used as an
address in the Interrupt Acknowledge Decoder,
which
is a 32-byte
arbitrates

PROM.

SLU

the

Output

receive

bits

and

7-4
of
that
PROM
are
the
previously mentioned
transmitter
interrupt
requests
(RDL1l,
RDL2,
XDL1,

XDL2)

which

are

SLUs.

TDAL12

reflects

the

LSI-11

Bits

0-3

bus

are

wire-ORed

used

earlier.

With

general

this

8.3.1

reset

state

the

-VEC

signals

for

the

latched

protocol.

mentioned

the
reader
follows.

the

can

reset

understanding

proceed

Details

into

the

Interrupt

the

Control

four

and

interrupt

requests

signal

detailed

the

used

latches

scheme in mind,
explanation
that

Logic

The Interrupt Logic
(Figure 8-11)
receives the interrupt requests
from the interface devices and applies them to the microprocessor.
The
microprocessor
will
acknowledge
the
highest
priority
interrupt,
provided
its
priority
1is
higher
than
the
current
microprocessor
status
word
priority.
There
are
nine
interrupts

E32
RDL1

XDL1

RDL2

XDL2
—1AK

SEL1

—SELO
Ras |
IS A

T PN

E%S

B7
B6

DAL 11
T

[~ +3 Ve

DAL 1

Q4 A1

Q3 A2

FLIP-FLOPS

ACKNOWLEDGE
DECODER
B3

35&1 8

Al4
Al-3

2Mm

Al-2

PROM

REVNTIP!

Al-1

ENCODE

Q7 P—1A6 512X4
Qo

—

Al-5

—VEC

] A7

EG5
-

E43

B2} —

E27

PARQST

E36

MEMORY

E34

oM
TM

INTERRUPT Q1 }——A4 INTERRUPT

D5
E29

—A0

PBRQST

A2
A1

TDAL 9
TDAL 8

D6
D7

E29
[.

Bop—+C

M30

81—

+3VC

2) (&BKRQ

E55
M31

CBKRQ

E33
b

?
E43

—BCLR
PCO
PC3

CAS
BEYNT

TEVNT

&,.

THALT B?.

BHALT L

Figure

8-11

Interrupt

Control

MR 6645

and

available

inputs

either

one

all

can

high

output.

The

enabled

These

outputs

the

Interrupt

synchronizers E27 and E33. Any interrupt is active when the signal
goes high. Five of these inputs are latched and remain high until
reset. Four interrupts are clocked through flip-flops E29, and ES55
to

maintain

the

through

flip-flops

Interrupt

present

transaction.

present

transaction.

Interrupt Encode Memory which

CAS

the

Interrupt

and

their

the

input of

the

1locations

is enabled by the -PI

Memory

Encode

clocked

during

asserting

address

The

are

interrupts

outputs

the

interrupt code equivalent to the highest input priority.
interrupt

The

rank

descending

codes

priority

Table

8-2

Designated

Interrupt
Source

Input
Signal

Priority
Level

HALT

HLTRQ

Non-

Power Fail

PFAIL

listed

are

1levels

is enabled,

in Table 8-2. When the PI output

the

Interrupts

Coded Input
AI-1 AI-2 AI-3 AI-4 AI-5

Vector
Address

maskable

Address

Non-

140

100

Restart

maskable

BKRQ

LSI-11

Bus

Signal

BHALT

LSI-11

Bus

Signal

BEVNT

REVNT

SLU2

REC

RDL?2

120

SLU2

XMIT

XDL2

124

PARALLEL

I/O B

PBRQST

130

PARALLEL

I/0

PARQST

134

SLUl

REC

RDL1

SLUl1

XMIT

XDL1

IRQ4

Read

LSI-11

Bus

Signal

BIRQ4

from
LSI-11
Bus

NOTE:

HALT

and

inputs

AI-1

priority.

Power
AI-5.

Fail
All

interrupts

signals

are

not

listed

generated

the

descending

order

coded

microprocessor

looks

completion of a Read

the

interrupt

transaction

inputs

and

following

will

initiate an IAK transaction

for an

interrupt with the proper priority.

decoded

to determine which

The coded

input

the

microprocessor is placed on the TDAL bus using bits 08 through 12.
Bit 08 represents the AI-1 input and bit 11 represents the AI-4
input. These four TDAL bus bits are inputs to the Acknowledge
Decoder Memory which is enabled when the microprocessor starts the
IAK transaction and the -IAK input goes low. These inputs are
interrupt was granted

and will

output a

low to negate that interrupt. The interrupt flip-flop is reset by
the clear 1line for that interrupt switching the output of the
selected AND gate low. The E66 and E65 transmitter and receiver
interrupt lines are latched outputs and are reset by wire OR-ing
and asserting low the output of the Acknowledge Decoder PROM. The
This
this process.
to
is an exception
interrupt
LSI-11 bus
low
the
and
E35
gate
NAND
of
inputs
the
interrupt code enables

output enables the -VEC (AI-5) input to the microprocessor. This
input instructs the microprocessor to receive the vector address
from the TDAL bus. TDAL 12 reflects the state of the -VEC input
when the microprocessor acknowledges the interrupt and is used to
determine that the LSI-11 bus 1Interrupt Acknowledge handshake

protocol must be invoked. The LSI-11 bus interrupt is not reset by
the Acknowledge Decoder PROM,

TIAKO

and

Interrupt

Acknowledge

but

received

are

signals

it should be

the

bus

reset when the TDIN

device

during

the

Sequence.

‘Before further discussion of the Interrupt system, the READY logic
must

described.
NOTE

The

8-12

waveform
and

subsequent

referenced

diagrams

shown

figures

Figure

the circuit schematics

are

Appendix
E.
They
were
obtained
by
photographing the displays produced by a
logic
analyzer
and
are
subject
to
in all
inherent
quantization errors
logic analyzers. They are intended only
as a help in understanding the logic and
not
as
a
precise
representation
of
timing relationships.
READY

8.3.2

The Ready logic
(Figure 8-12)
provides the READY input to the
microprocessor and is used to control the cycle slip function.
The microprocessor will cycle slip when the READY input is being

pulsed

while

inhibited

when

RAS

the

asserted

READY

input

set

Ready flip-flop and the COUT input
generate the READY input.
When the
and the TSYNC
high. -DRRPLY

E13

are

cycle

the

and

high.

go to
-CSLIP

slip

The

function

output

the

the E1l3 OR gate and
input to Ell 1is high

input is high, the output of the Ell AND gate goes
is not yet asserted and the -TCLKSP and the output

high,

the

output

high.

This

enables

E1l2

—TMRP
E12

—~TCLKSP
—DRRPLY

fr—

IAKD!N

E13

—CSLIP |

> R1 READY

TSYNC
CcouT

—BCLR
MR-665T

--.J

n—

e ® o=
_-.—-i-—fi_fi- ® oaa—

TSYNC
—CSLIP L

b
E20PIN
E11PIN1

—CSQB
IAKDIN

6
E40 PIN
E13PIN 4

RAS

E32 PIN 13

—CAS

E49 PIN 15

—TMRP

E26 PIN 10

—DRRPLY

PING

PIN 12

couT
—RQSLP

E7
E7

PIN3
PINB8

READY

E13PIN 11

TCOUT

E13PIN 13
E7 PIN12

A
»

&l
o
»
p o o

[

p—

g M. o b

h-/

S
E20PIN
E11PIN1

B
i —Csa

IAKDIN

E40PING
E13PIN 4

RAS

—CAS

E49 PIN 15

puisass

F;---

— TSYNC
—CSLIP L

. * | a..1.

i!---J-.-=-I-—i-|

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——-_-

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b_—

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gy SR g )

-y

8-12

8-20

—TMRP

E26 PIN 10

—DRRPLY

PING

PIN 12

CouUT

PIN3

~RQSLP

PINS8

READY

E13PIN 11

TCOUT

E13PIN 13

—CSRAM

E40PIN 10

]

B. Signals during local transaction

Figure

PIN1

Ready

and

the

preset

input

output is low at
every COUT.
When

the

OR gate El1l3
the
IAKDIN

flip-flops

low.

The

TSYNC inputs are negated, the output of the E9 AND gate
It allows the E12 NAND gate output to go low and forces
terminal of
the OR gate
READY
while

the E4
is now

flip-flops low.
The output of the
low and this allows the COUT input

output.
The
this
input
is

flip-flop

and it enables the READY input with
input goes
high
and
the
-CSLIP
and

microprocessor

will

being

The

pulsed.

goes high.
the preset

flip-flop to
to clock the

continue
to
cycle
-TMRP input
to
the

slip
NAND

gate will go low when either the BRPLY or TMER input from the bus
is received.
This will
remove the
low from the preset
input of
the first flip-flop.
Shortly after the -TMRP input goes 1low the
-DRRPLY input also goes low and forces a high to the input of the
flip—-flop.
The high is clocked through by the COUT clock and the
flip-flop output to E13 will go high.
This
disables
the
READY
input
to
the
microprocessor
and
allows
the
transaction
to
be
completed.

The

second

the

flip-flop

microprocessor

completion.,
references.

The

8.3.3

DATA

IAK

Ready

required
at

the

circuit

ensure

that

data

peripheral

prior

inactive

during

1is

stable

transaction

1local

address

(IAKDIN)

The IAKDIN output is enabled by the output of the NOR gate E21 as
shown in Figure 8-13.
The microprocessor acknowledges an external
interrupt
request,
asserts -SEL1
and
negates
SELO.
When
the
microprocessor has to read the interrupt vector from the bus, the

TDAL12 input is low as
interrupt request read.
and assert TDIN to the

a result of AI-5 being low during the
This allows the IAKDIN output to go high

bus.
The RAS input 1is high and this
enables the TIAKO flip-flop E22,.
IAKDIN is clocked by the COUT
input causing TIAKO to go high and the inverter E16 sets the BIAKO
output 1low.
The BIAKO output goes to the bus as an interrupt
acknowledge.
The TIAKO output goes to the Bus transceiver logic
and enables the low byte transceivers to receive the vector.
The
IAKDIN
output
goes
to
the
Ready
1logic
and
allows
the
microprocessor to cycle slip until the interrupting device asserts
the —-BRPLY input or a timeout occurs.
When either response is
received, the SELO input goes high to disable the IAKDIN output
and signals that the microprocessor has read the vector. The RAS
goes

low

The

microprocessor

timeout

-BRPLY

clear

occurs

and

8.3.4

HALT

interrupt

the

cannot

will

and

flip-flop.

abort

read

the

reading

timeout

counter

triggers.

vector

zero

vector

1if

cases

all

1if

INTERRUPT

(Figure

microprocessor

configuration

request

TIAKO

not asserted

The

HALT

the

BHALT

the

8-14)

designated

input,.

can

trigger

control

that

AI-7

signals,

The

such

this

user
as

-CTMER

and

determines

TMER,

interrupt.

SLU

goes

the

BREAK

The

-IAKDIN

g'+3 \Y
£10

-BIAKO

E22

cCOuUT

TIAKO

'0)

RAS

—BCLR

E36

MR-6652

-_— - . -

-—
-———.—_;-.--F-———.—-—

C AS

—--- —-—--_-'-._-—--—._-—---*- Pl
-

SEL1

' —-—

R AS

-IAKDIN

E21PIN 12
E22 PIN 11

TIAKO

READY

E22PIN 9
E64 PIN 26

-f

XHB

E59 PIN 5

*‘

-1AK

E35PIN 6
E45 PIN 4

“%——

PBRQST

E27 PIN 14

{RQ4

E27 PIN 7
E35PIN
8
E41PIN 4

'_—.'.*_—-——-_‘-—.—-—-.—.———-_

—-—

--—.--.-.—‘.n-_-p.-..p..‘-.c...-.
- .—..*—--

m—

———. -— —-.-.-._-.

-—-—-‘.-—o— * —-

E49PIN S
E32PIN 10

Co UT

E35PINS
E49 PIN 16

EB7 PIN 4

—
-

f——g——

-PBAKH

A. Signals during local interrupt

S
E49 PIN
E32PIN 10
E35PINS
E49 PIN 16

""" o
sae

*6__Sspsscesnbessens

28050008000008 sonh

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e
XX

TS BN SIS

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CcouT

EEAAKDOY

e s b_--ii.‘.—.__--_--wg___ RHLB
TM
-

—

’

—

Figure

8-13

IAKDIN

E22 PIN 9
£64 PIN 26
E59 PIN &
ES7 PIN 4

E35PING
E45 PIN 4

PBRQST

E27 PIN 14

AlD

E27 PIN
7
E35PIN
8
E41 PIN
4

IRQ4

-PBAK H

B. Signals during LS!-11 Bus interrupt

E21PIN 12
E22 PIN 11

6-+3 \%
—1AK

—0

O—

TMER

E33

—CTMER

CAS

—

O1+———=
Al-7

[

—BCLR

TREAD

E19

MR-6653

—

p—

"
'

.
-

)

:
Y

-RRPLY

TMER

&5 RAS

ottt

;

E6 PIN 11
E6

PIN9

PIN
12

E5 PIN 13

;

M6(TMERE4
) PIN 11
HLTRQ
E4 PINO
===

PIN
12

HITRQ

E33PIN5

CTMER

E33PIN7

E19 PIN 4

CAS

=" TREAD

—emm— |

E13PINS8

E13PIN 3

E11PINS
E6

TDIN

TDOUT

e« TRGTM

‘

—IAK

E33PIN 9

E21PIN 6

E35 PIN 6

A. Signals during LSI-11 Bus time out

{(Interrupt Acknowledge with M8 and M9 jumpered)

’W..

[X X

[

, fififlfifi“‘fi.‘r“ TSYNC

XTI

XX XX

.-.l.flo.—

%
-

——
'

)

-o

—RRPLY

* RAS
‘M8

E20PIN5
E13P|N

E13PINS8

E6 PIN 12
E6

PIN 11

E5 PIN9

PIN 13

PIN 12

——

S pmeeme MG(TMER) E4 PIN 11

———

TRGTM

e TME
R

_f
AR

READY

HLTRQ

E33PIN5

. CAS

’

TREAD

E21PING

E19 PIN 4

—1AK

{with M8 and M9 jurpered)

8-14

HALT

E33PIN 9

B. Signals during nonexistent LSI-11 bus address

Figure

PIN9

Interrupt

E35 PIN 6

flip-flop

and

goes

clocked

enables

the

The

input.

flip-flop

the -CTMER

microprocessor

EI19.

Fetch

Read

and

CTMER

The

this

time

asserts

output

the

E33

high

and

into

the

flip-flop

the E33

set

assertion

during

switches

the

E19

NAND gate

latches

transaction

This sets the output of

output low.

CAS clocks

The

same

the

and

input

output.

gate

NAND

microprocessor

the

assertion

-CTMER

reset

low to

the E25 AND gate

The E33 flip-flop
the E4 flip-flop for the next HALT interrupt.
or AI-7 input
microprocess
The
strobe.
CAS
next
the
by
is cleared
for one PI
negated
be
must
it
is,
that
ive,
is pseudo edge-sensit
invoked.
be
can
address
restart
the
to
trap
another
before
time

connecting
interrupt

bus

LSI-11

during

assertion

Chapter

explained

prevents-CTMER

transactilons.

acknowledge

This will prevent the restart trap resulting from this timeout.
8.3.5

The

Power

-PFAIL

Fail

output

1is

connected

the

AI-6

microprocessor and is recognized as the power fail
is

nonmaskable.

does

not

initiate

and

PSW

microprocessor

the

This

traps

IAK

through

highest

priority

octal

addresses

Power

the

interrupt

and

the

access

routine

This

Routine.

Fail

acknowledged,

When

transaction.

User's

the

for

second

1input

interrupt which

should
include a RESET instruction and any other
instructions
required to initialize the bus and the module, as well as an MTPS
instruction that will load 340 into the PSW and a wait instruction
to inhibit the assertion of any LSI-11 bus control signal when
battery

backup

being

alternative

location
at
stored
through 24, 340 will

utilized.

the

MTPS

instruction,

340

may

simply

microprocessor
the
loaded into the PSW.

when
Then,
26.
automatically be

vectors

NOTE

BDCOK
reset

can be
used as
a microprocessor
signal,
unrelated
to
power

failure.

guarantee

correct

restart,

the
BDCOK
pulse must
be
at
1least
100
microseconds
wide.
BPOK
should
remain
inactive during this reset operation.
8.3.6
Local
The on-board local

interrupts

are

listed

Table

8-2

and

use

coded input on the AI-1 through AI-5 inputs to the microprocessor.
Some of these interrupt functions are determined by the user when
configuring the module. There are eight local interrupts and they
are

all maskable.
interrupt
with

microprocessor.

The
the

All

multiple

interrupts

are

arbitrated

highest

priority

1is

serviced

1local

interrupts

initiate

IAK

and
by

the
the

transaction

and
their
vector
addresses
are
internal
to
the microprocessor.
During IAK, the serviced interrupt is driven on TDAL lines 11--08
to

address

reset

the

interrupt

interrupts.

acknowledge

TDAL

PROM.

bits

The

07--00

outputs

are

the

PROM

ignored.

The

and

PSW

present

the

pushes

microprocessor

and

stack

the

onto

receives a new PC and PSW from the vector address

location and the

input

location.

8.3.7
level

External
LSI-11 bus

interrupt

through

AI-4

inputs

the

also

uses

coded

microprocessor

and

the

maskable.
For
microprocessor
is

the
bus
interrupt
the
AI-5
taken low to
indicate that the

must

LSI-11

read

from

bus

bits

07--02.

The

the

AI-1

interrupt

input
vector

to
the
address

microprocessor

does

an
IAK
transaction and places the BDIN
bus to the requesting peripheral device.

and BIAKO signals on the
This device responds with

-BRPLY

from

and

the

vector

microprocessor
reads

next
If

new

pushes

PSW

and

address

the
PC

read

current

from

the

and

vector

PSW

the

LSI-11

onto

address

the

bus.

The

stack

and

location

and

the

location.

the

interrupting

peripheral

device

fails

assert

the

BRPLY

bus
signal
within
10
usec
after
BDIN
1is
asserted,
the
module
timeout signal TMER is enabled.
The microprocessor completes the
IAK transaction and receives a vector address of zero, since there
is nothing driving the bus. The new PSW and PC are then read from
locations
2zero
and
two.
However,
the
user
has
the
option
to
connect the timeout signal TMER to
the HALT
interrupt.
The HALT
interrupt can then be processed and pushes the current PSW and PC,
which were read from locations 0 and 2, onto the stack.
It then
loads the PC with the
restart address and the PSW
the HALT
is
ignored
for
the vector
timeout,
then
through

locations

8.3.8
The

DMA
DMA

zero

and

two

will

with
only

340.
If
a
vector

occur.

Interrupt

request

1is
connected
to
the
AI-0
input
to
the
microprocessor. The DMA request is received by the microprocessor
during any Read, Write, Fetch or ASPI transaction. The request |is
not acknowledged by an IAK transaction but is acknowledged by the
microprocessor asserting the SELO and SEL1 outputs to
1initiate a
DMA transaction as described in Paragraph 8.14.

8.4

DC004

PROTOCOL

The

DC004

protocol

The

-CSQB

input

the

LSI-11

logic

read/write
goes

chip

signals

high

(see

Figure

8-1,

Sheet

interfaces

strobed

RSYNC

enable

with

and

the

module

read/write

signals.

the

logic. The BDIN L input goes low to request read data and switches
the -READ output low. The BDOUT L input goes low to strobe write
data and switches the -WHB and -WLB outputs low if the BWTBT L
input is high. When the BWTBT L input is low, the BDALO L input

will select either the -WHB or the -WLB. A low on the BDALO L
input
switches
the
-WLB
output
1low.
The
BRPLY
L
output
is

-CSQB

the

controlled

low

BDALO

input.

When

=-CSQB

input

high,

this

indicates the LSI-11 bus was not selected. The BRPLY L output is
enabled and is switched low, after an RC delay, whenever BSYNC L
and either the BDIN L or BDOUT L outputs are switched low.
If the
-CSQOB input is low, the LSI-11 bus is selected and the BRPLY L
output is disabled
The BDALO, 1, and 2 inputs control the -SEL6
output. The output goes low when BDALl1 L and BDAL2 L inputs are
and

the

high.

8-25

8.5

ADDRESS LATCH

The Address Latching logic (see Figure 8-1, Sheet 1) consists of
s are
16 transparent latches designated E53 and E63. The 1latche
bus
TDAL
The
input.
Control
Output
the
ng
always enabled by groundi

bits 01--15 and the I/O page select signal RBS7 are monitored. The

status of these inputs is latched to the Address Bus as bits ADl
through AD15 by the RSYNC input going high. The Address Bus and
the latched LBS7 signal go to the Memory Address Decode logic
(FPLA). The address bus is common to the module memories and the
I/0 circuits and remains stable while RSYNC is asserted.
8.6

MEMORY ADDRESS DECODE

(see Figure 8-1, Sheet 1)

The Memory Decode logic

Field Programmable Logic Array

(FPLA)

predetermined output according

the

available

address

bits

and

latched

the

LBS7

module address range includes
interface registers and LSI-11
different

maps

memory

that decodes

signal.

the
bus

consists of a

The

the applied

FPLA

selects

selected memory map.

The

these

are

on-board memory, the 1/0
addresses. There are four
the

user

and

described in Figure 8-15. The M22 and M23 wire-wrap pins allow the
user to select one of these maps and these are described in
Chapter 2. The FPLA is enabled provided the DCLO input is low. An
address location in the RAM memory enables the =CSRAM output and

an address location of either socket set A or B of PROM enables
either the -CSKTA or —-CSKTB outputs. A register address for either
SLU 1 or SLU 2 will enable the -CSDLO or -CSDL1l outputs. The -CSPL
output is enabled when a register of the parallel I/O0 logic 1is
addressed. The -CSLIP output is low for all the above address
conditions. The -CSLIP output goes high only when the address is
located on the LSI-11 bus and the -CSQB output is enabled low. The
~CSLIP output allows the processor to cycle slip during the LSI-11
bus read/write and IAK transactions.

8.7

RAM MEMORY

The Static RAM memory is a 2K X 16-bit memory that consists of a

2K X 8-bit high

byte

chip and

described by Figure 8-16.

2K X 8-bit

low byte

chip as

The memory is selected by the -CS5 RAM

input going low to the CS pin. The memory is addressed by address
bits AD1--AD11 and 16-bit data is read from or written to via TDAL
bits 00--15. The memory is read by the —-READ input going low to
produce a low output from the AND gate E25 to the OE pin of the
memories. The -WLB selects the low byte and the -WHB selects the
high byte. The -WHB and -WLB inputs to the WE pin enables the
write function and the output of AND gate E25 also goes low to the
OE pin of the memories, to accommodate the dual CS function of
some vendor's

static

RAMs.

MAP O
64 KB

MAP 1

MAP 2

64 KB

(NOTE 3)

64 KB

(NOTE 3)

2 KB (NOT1)
E
7 KB LOCAL RAM

MAP 3

64 KB

4 KB LOCAL RAM

(NOTE 3)

(NOTE
3)

4 KB LOCAL RAM

4 KB LOCAL
RAM

56 kA NOTE 2)

2)
N [ NOTE

o6 ksl INOTE 2

o6 kplNOTE 2]

48 KB+

48 KB-

48 KB/

48 KB:

LSI-11 BUS

40 KB

40 KBA

40 KB

32 KBA

32 KBH

32 KB1

32 KB

24 KB

24 KB-

24 KBy

24 KB4 16 KB SOCKET
A

16 KB~

16 KB

16 KB
8 KB SOCKET
A

8 KB+

8 KB4

8 KB

s kB4

16 KB SOCKET
B

4 KB SOCKET
A
8 KB SOCKET
B

0KB

0 KB

4 KB SOCKET
B

0 KB:

0 KB

NOTES:
1. SOCKET SET A IS MAPPED OVER SOCKET SET B AND IS

THEREFORE LIMITED TO USING EITHER SOCKET A OR
SOCKET B, BUT NOT BOTH TOGETHER.

2. ADDRESSES 160000 THROUGH 160007 ARE ASSUMED TO

RESIDE ON THE LSI-11 BUS.
3. THIS SECTION CONTAINS THE LOCAL I/O ADDRESSES FOR
THE SLUs AND PPI. ALL UNASSIGNED ADDRESSES ARE
ASSUMED TO RESIDE ON THE LSI-11 BUS.
MR-6643

Figure

8.8
The

ROM/RAM MEMORY SOCKETS
memory provides the

socket

high

Memory

ROM/RAM

described
by
Fiqgure
industry standard +5

32KB

8-15

PROMs,

sets

are

byte

socket

8-17,

chips.

PROMs

designated

and

low

user

The

and

socket.

four

either

sockets

and

byte

with

ROMs

Maps

The

28-pin sockets,
as
24-pin
or
28-pin

can

accommodate

8KB

each

static

designation

sockets

use

RAM.

the

to
The

has

-CSKTA

—READ

E25

—WHB
—CS RAM

STATIC RAM

2K X8

AD1-AD1U1

HIGH BYTE

EGO

K TDAL 08-15
>

TDAL 00-15

TDAL 00—07

—CS RAM

C% STATIC RAM

—WLB

—-

LOWBYTE

—READ

—

2K X8

E46

OE
MR-6642

Figure

8-16

RAM Memory

ss Decode and the user
and -CSKTB outputs from the Memory Addre
y maps associated with
memor
should refer to Figure 8-15 for the

-WLB signals from the DCO004
these signals. The -READ, -WHB and Byte
Enable (HBCE) and a
Protocol are used to provide a High are 30Chip
wrap jumper posts
wireThere
Low Byte Chip Enable (LBCE).
available for the memory configuration and detailed information is
provided

in Chapter

NOTE

When a memory chip is placed into a
socket wired for a larger capacity part,

for example a 1K X 8 chip in a 2K X 8
socket, the addresses above the 1K
boundary will wrap around into the start

in
of the memory. This should be kept map
ory
mem
mind when choosing the
configuration.

—~WHB

:flflfliL—\

_HBCE

“CSKTA

M55

E25

—READ

TDAL

—CSKTB

00—15

Ma7

M56

M53

(]

AiSREAD

M51

|
E25

—WLB

? M44

—LBCE

M54
‘

—WLB

28-PIN

M52

SOCKET A

E47

Md4s

(m]

(w]

AD12

AD13

1? M45
2

M50

M33

SOCKETA | O~

E61

28-PIN

[SOCKETB

3V |E48

NCR

ws70—22

23-Om43

]

HIGH BYTE

?M%

28-PIN

SOCKET B

22l _Amao

M390___22E62

m3Tg—23

gm4a2

M32

m340—{23

LOW BYTE

28-PIN

2L amar

HIGH BYTE

?M%

2
?MBS

|LOWBYTE

—0

MAO

?M48

AD11

AD1—AD10

TM%

MR-6644

Figure

8.9

8-17

ROM/RAM

Memory

Sockets

SERIAL

There

LINE INTERFACE UNITS
Asynchronous
Serial
Line Units
designated
provide serial I/0 interface through J1 and J2 as

are

SLU2

two

to
Figure 8-18.

Operational

The
SLUs
transmit
parity,
one start

aspects

are

discussed

Chapter

SLUl

and

shown

or
receive
8-bit,
bit,
and one
stop

byte-oriented
data,
with
no
bit.
SLUl
provides
the XDL1
and RDL1 interrupts for transmit and receive, and the
BREAK output
which is wired to pin M14. The user can jumper
the BREAK output to
the
HALT
interrupt
(pin M13)
and
use
SLUl
as
a
system console.
SLU2
provides
the
XDL2
and
RDL2
interrupts
for
transmit
and
receive, and three real time clock interrupts at 50 Hz, 60 Hz,
and
800 Hz.
These
interrupts are wired to pins M18, M19,
and M20 for
use with the TEVNT interrupt (pin M17).
When

the

serial

SLUl

and

the

line

-CSDL1

units
input

are

addressed,

selects

SLU2

the

-CSDLO

enabling

input

the

chip

(CS)
inputs.
Address
bits
AD2
and
ADl1
are
used
to
individual
registers within the SLUs.
These
registers are
in Table 8-3 with their address and the logic states for

ADl

input

AD2 and
the
-WLB

to access them. The -READ
selected by -CSDLO or -CSDL1,

onto

the

When

asserted

low,

the

TDAL
AD1,

bus

the

will

TDAL

into

bus

However,

written

provided

only

-WLB

the

into.

input

DLCLK

select
1listed
AD2 and

read the 16 bit register
AD1 by placing the contents
input
is
not
asserted
low.
will write the low byte of the

selected

The

will

selects
select

-CSDLO

bits

input

8-29

-CSDL1l,

designated

AD2

and

read/write

crystal

controlled

—CSD

M14 M13

THALTH +12 F——q10
"' "Bf
BREAKOUT|

BRCLK
SLU1
DLART

£30

E65

RCVIRQ RDLI

DCLO
AD2
AD1

—READ

_12VE

DLCLK

BRCLK

)

]

TDAL 00-15

[@U‘lbm

%RB

—WLB

+12 F=——10

SLu 2
DLART

EG6

E30

RCVIRQ |~ RDL2
g xpL2

XMITIRQL

M18

—0

M19

60HZ L0
800HZ

M17

O——TEVNTH —12V

M20

DLCLK

I © AN

50HZ

—CSDL1

[ o}

E37

E43

A 03

+5 VDC

E44

Figure

8-18

£28

E.g v

_@0._{(——“—\5——12.0 vDC

Serial

__=ECS

Line

Interface

Units

clock reference used by the SLU to generate baud rates and real
The BCLR input is asserted during a RESET
time clocks.
instruction, the RCVIE bit of the RCSR register and the XMITIE,

MAINT and XMIT BRK bits of the XCSR register are reset.

When the

registers.

The baud

DCLO

input

outputs and

asserted

resets all

during

internal

power

up,

logic and

disables

all

SLU

rate will be set at 300 baud after the SLU is initialized by DCLO.

The RS232 and RS423 signals for the interface connector are
provided by 9636 (E30) and 9637 (E37) dual line drivers and dual

line receivers.

The slew rate for both channels is controlled by

resistor R6. The factory configuration uses a 22K ohm resistor to
provide a 2 usec slew rate for operating at a 38.4 K baud rate.
Refer to Chapter 2 for the configuration requirements at other
baud

rates.

Table

8-3

Serial

Line

Unit

Description

Registers

Address

AD2

AD1

SLU1
RCSR

Receiver

Control/Status

RBR

Receiver

177560

Buffer

TCSR

Transmitter

177562

TBR

Control/Status

Transmitter

177564

Buffer

177566

SLU2
RCSR

Receiver

Control/Status

RBR

Receiver

176540

Buffer

TCSR

Transmitter

176542

Control/Status

TBR

176544

Transmitter

Buffer

176546

8.10
PARALLEL I/0O INTERFACE
The
programmable
parallel
I/0
provides
a
30
pin
connector
for
transferring parallel data into or out of the SBC-11/21 module.
The parallel I/0 uses an 8255A-5 programmable interface chip,
two

8-bit

Figure

transceiver
8-19.

chips

The

and

8255A-5

has

8-bit

three

buffer

chip

input/output

port
A,
port
B
and
port
C.
connected to 8-bit bidirectional

Port
A
and
Port
transceivers that

When

wirewrap

these

pins

the

M59

data

and

M66.

lines

act

inputs

logical
to

defined

B
outputs
are
are controlled

one

the

described

ports

1is

applied

module

and

when

logical
zero
1is
applied
to
these
pins
the
data
1lines
act
as
outputs from the module.
The user can configure these as 1inputs
or outputs using wirewrap pins M60
and M65 or as programmable
inputs/outputs by programming the PC4 and PC6 lines (M64, M63) of
Port C as described in the configuration description in Chapter 2.
The Port C outputs are connected to directional buffers and used
for interrupts and the handshake control for ports A and B.
PCO
PC3

are

wired

Request

and

for

port

for

port

as
A

8255A-5

the

-CSPL

and

PC3

enables

PCO

enables

the

PC6

can

used

Programmable

input

from

the

Parallel

Peripheral
Memory

listed

Table

8-4.

The

Port

acknowledge

Interface

Address

176200-176207
addresses
are
selected.
lines are decoded to select one of four
and

Interrupt

Request

strobe
inputs or can be configured to dynamically control the direction
of ports A and B from either the 8255A-5 interface or the external
peripheral device.
PCl, PC5 and PC7 are wired as outputs and PC7
is wired to a LED that can be program controlled.
PC2 is wired as
an input and has a current limiting resistor for protection when
PC2 might be programmed as an output from the 8255A-5
interface.
Detailed configuration requirements are provided in Chapter 2 and
the programming information is provided in Chapter 6.
The

PC4

outputs,

and

(PPI)

Decode

chip

1is

enabled

whenever

The
ADl1l
and AD2
registers within

Port

and

Port

by
the

address
the PPI

registers

——»PC3

I—.

PCO
PC1

PCO

AD1

oc3

AD2

PCA |0

M63

M61
u___'__<

M64

}

l//

R10

PC2

~CSPL ——Qlcs
PCS

_READ

pcel—0

RESET

ber

lJ\V\

8255A-5

“seLsl

{__ _BUFFERs

PERIPHERAL
INTERFACE

E67

TDAL 00-07

E69

PROGRAMMABLE

JAN

-WLB ——OWR

~BCLR

PBO

PB1

PB2

PB4

PB3

PB5

MEB9

20
19

L DIR

]

E:m

GNDOME0

PAO
PA1

B6
B4

PA2

PA3

PA4

PAG

B85

PA7

PA5

BUS
TRANSCEIVERS

’ I
R11

M66 O— &}

flm
+3V OME5

15
I
s

BUS

PB7

+5 Vv

TRANSCEIVERS

PB6

| )

ES4

DIR

AB
A4

27
25

A1l

—

E
MR-6647

Figure

8-19

Table 8-4

Parallel

1I/0

Interface

PPI Addressable Registers

Address

Status

Port A
Port B
Port C
Control Word

176200
176202
176204
176206

Read/Write
Read/Write
Read/Write
Write Only

BPOK H
E33

CAS

~P FAI
o___é_l;

—B CLR

M15

M16
D1

l +6VNCR

E12

—PUP

$
R4
<

DCLO

BDCOK H
MR-6648

P XLB

E36 PIN 6

BPOK H

E57 PIN 13

f“'anL

E16 PIN 4

———

;

e I

scr

E14PINS

¢—

—PUP

E12PIN8

-t

]

___g_}

—

0 - -Tclk

E15PIN17

Signals during Power-Up

Figure

are read/write and the
The addressed
register.

TDAL

the

07-00

bus

addressed
input

-READ

the

inhibits

therefore

when

-WLB

read

input

placed

strobe

from

The

asserted.
the

-SEL6

The

07-00

Control

Word

the

control

asserted.

the TDAL
L

the

and

NAND

gate

E1l2

treated

asserted and all 8255A-5 24 I/O lines are then defined as
The buffer outputs to the connector will be driven high.

inputs.

the PPI

used with

Only the

and any data

when

is always

the microprocessor.

word

input

contents

bus

erronous

produces

data

read

Control Word register is a write only
register is written into with the data on

any

the

Power

8-20

low byte of

the high byte

the TDAL bus

as erroneous.

The -BCLR input is used to reset the PPI when it is

8.11

The

POWER

power

+5VNCR

power

circuits
source

sequence. When the +5VNCR

(Figure
the

input

8-20)

module

sense

and

the

first applied,

8-33

application

initiate

the

power-up

input at the

low

E10

the

nand

gate

+5VNCR

input

charges

inverter

flip-flop E5 to be low,

microprocessor

and

causes

1is

1low,

thus keeping

El12

held

reset

and

through

the

its output low.Since an
the

-BCLR

PUP

input

the

output.

1level

threshold

the

until

high,

output

=-PUP

asserts

the

input

clear

the

The

inverter E10 is reached. This occurs at approximately 2.6 Vdc and
This causes the reset input to
70 ms after +5VNCR was applied.
input to go low, setting the
set
and
the PUP flip-flop to go high

flip-flop.
initiates

The -PUP output of

the

power

the

nand gate

the

sequence

This

low.

goes

El2

processor.

The power up delay circuit can be by-passed by inserting a jumper
This allows the BDCOK H and BPOK H bus
between M15 and M16.
The +5VCNR input goes directly
signals to control the PUP output.
to

the

output

inverter

until

power

causes

the

flip-flop
input

then

1low.

nand

gate

preset

input

The

El1l2

asserts

then

the

input

supply stabilizes,

microprocessor

flip-flop.

driving

E10

controlled

The

BDCOK.

the

causing

BPOK

signal

the

flip-flop

the

-BCLR

the

drives

E38

inverter

BDCOK

reset

PUP

input

low

also

high.

output

E38

the

PUP

1is

and

The

high.

the

resetting

output

low.

signal

low

this

1low

The

PFAIL

After a minimum of 3 ms the BDCOK bus input goes high

After a minimum
and allows the PUP flip-flop E5 reset to go high.
of 70 ms the BPOK H bus input goes high causing the PUP preset
This allows the output to go high and when both
input to go low.

inputs to the nand gate E12 are high the -PUP output is low.
the power

initiates

The

This

H bus

BPOK

up sequence of

input

also

not

Following

the

power

the

goes

wuntil

enabled

flip-flop

the microprocessor.

PWR

FAIL

flip-flop

the

microprocessor

the

first

This
E33.

power

up sequence is completed and therefore the BPOK H input is already

high.

the

PFAIL

flip-flop.

the

PFAIL

flip-flop

The

sequence,

flip-flop

input goes low indicating a power fail.

and

resets

interrupt and trap to location 24.

it.

remains

set

CAS

pulse

until

sets

the BPOK

The next CAS input clocks

This

causes

the

power

fail

This interrupt must be negated

for at least one microprocessor read before another assertion will

recognized by the microprocessor.

8.12

CLOCK

The module uses a 19.6608 Mhz crystal oscillator as the basic time
The oscillator output goes to the Clock Control
base reference.
The
logic (see Figure 8-21) and to the E8 binary counters.
by
divided
is
output
MHz
19.6608
The
counters are always enabled.
Line
Serial
the
to
goes
Khz,
614.4
at
output,
32 and the DLCLK
units and to the charge pump. The oscillator is also divided by 4
When
and the 4.91 MHz output goes to the pulse sync circuit E15.
output
the
and
enabled
are
circuits
the
low
is
the TCLKSP input
When the TCLKSP input is
goes to the next pulse sync circuit.
The
is no output.
there
and
inhibited
are
circuits
the
high
When
second pulse sync circuit is controlled by the PUP input.
the PUP input is low, TCLK to the XTLl input is enabled and when
the PUP input is high, the XTL1l input is inhibited.

8-34

S CLK

DIVIDE

BY 16

BY 2

Lok

DIVIDE

19.66 MHZ
OSC E2

BY 4

O O—

E15

E1s

Stk

TCLK SP
—PUP

MR-6649

SR
i,

LT ok ok S
)

:
—-:pr—_
B

[
.

v——

[

’

]

kel hekorl whwk s SR LL TV
-

ot By o

__—'iP:M EBPIN 10

A nasa

o——

;4‘_ -

{ TCLKSP

4.91 MHZ

wL-_—"fl

Signals for clock logic

Figure

8.13

CLOCK CONTROL

The

clock

control

the

low

inputs

This

1is

clocked

1logic

8-21

(Figure

Clock

8-22)

the AND gate E9 and

the

used

stop

the

XTLl

IAK flip-flop El17.

The

input to the microprocessor and forces the microprocessor to stop
or wait until the XTL1l input is enabled again.
The TCLKSP output
is normally low to enable XTL1l and this is controlled by the TMRP
input being high.
This forces a low for both inputs to the OR
TCLKSP
the
through
clocked
1is
output
1low
the
and
E31
gate
flip—flop by the 19.6 MHZ input.
When TMRP goes low this removes

TSYNC input is high for Read/Write and Fetch transactions and when
the -CAS input goes high the AND gate E9 output also goes high.
through

the

TCLKSP

flip-flop

and

the

output

goes

high to stop the 4.91 MHZ clock output of E15. The TSYNC input is
low for DMA and IAK transactions so that input to the AND gate E9
holds the output low.
However the IAK flip-flop E17 is set when
the -IAK clock

transaction and
the TCLKSP

input

goes

high

the

end

the E31 output goes high.

flip-flop and

the

output

goes

This

high

external

interrupt

clocked

stop

the

through

4.91

MHz

clock output of E15. The microprocessor XTL1 input will remain
stopped until the TMRP input goes high again signaling that either
BRPLY or TMER have been negated.
This forces the IAK flip-flop
E17 output to go low. This negates the TCLKSP output and enables
the

XTL1l

input

the

microprocessor.

8-35

TSYNC

6_+3V

—~CAS

. T CLKSP

Eat

13V

“

—

—TCLKSP
D———

E17
—|AK

+3V

~TMRP

E10
E3

S CLK

—BCLR

—~DRRPLY

MRA-6650

- ev

———
.-

Y )
g

. OCLK
- o mone

TCLKSP

PIN13

PIN 10

E15 PIN 13
7
E15PIN

DRI

R
it
+

+
'

[

-.-'.. .o

;

— _IAK

"‘L‘-

. DRRPLY

TSYNC

——
il

E49 PIN 15

e DRRPLY

i [ i“‘

E20PIN S

)

——

]

[PS

-:-»—9

“
.Jij‘i{——i?;
1

TCLKSP

TCLK

Signals for clock control

Figure

8-22

Clock Control

PIN3

PIN 12

E20PIN b

PINDB

E17 PIN 11

PINS

PIN9

E15 PIN 11
E15PIN 7

8.14
The

DMA
DMA

logic

(Figure

8-23)

controls

the

bus

and

microprocessor

for DMA transactions.
The BDMR L input goes low to initiate a DMA
request.
The output of the
inverter goes high and
is clocked
through flip-flop E14 by COUT.
The low output goes to the E21 NOR
gate and the high output goes to flip-flop El4.
The high output
is
clocked
through by COUT and the high output enables
the two
NAND gates E28 and El.
The high output 1is also clocked through
flip-flop E33 by the CAS input.
The high output enables the NAND
gate E12 and the —-CDMRQ output
(AIO Input)
is switched low.
-CDMRQ
output
is
the
DMA
interrupt
to
the
microprocessor
initiates a DMG transaction.
The microprocessor acknowledges

8 DMR L 4:>
E14

B SACK L

E59

E38

nil

E14

COUT

E33

E12

CAS

—BCLR

—CDMRQ

]

SEL1

BDMGO

SELO

£28

; E22

~RAS

[

:.\ ----- -.._b o« @ W=y
-

_DMG

I........!RDMR
= COUT

DMRQ

——
e

o—

..'. - & & & ® &

—

DMG

—

e
i

US g
&

E33PIN
2

E49 PIN 13

—DMG

E22PINS

RSACK
TDMGO

8-23

E33PIN 9

E49 PIN 6

—

Signals for DMA logic

Figure

E14PIN9

SEL1

o
gy S

E14PIN5

+f:h_qr

CDMRQ

E14PIN
3

ey SE LO

CAS

‘

E51 PIN3

DMA

XHB

E21PIN
9
E21PIN8

E11PING

E18PIN
12

E19PIN
8

The
and
the

request by outputing SEL1 and SELO high
preset of flip-flop E22 goes
low to set
the
the

-DMG output low.
output low and it

normally
gate

high

E21.

causing
gate El1

and

All

to NAND gate E28,
the DMG output high

The
and
switches
input is

The DMG high input to NAND gate E12
goes to NOR gate E21.
The BSACK L

when

inverted

three

1inputs

the output to
switches BDMGO

switch
low on

E59
the

NOR

low

gate

input
E21

are

the

NOR

now

low

high.
Two high
inputs to
the NAND
the bus to the originator of the DMA

request.
The requesting device
low and the BDMR L input high.

then sets the bus signal
BSACK L
is
inverted
by

BSACK L
E59
and

removes the low from the NOR gate E21 and the high input to the
NAND
gate
E1
causing
the
BDMGO
output
to
go
high.
It
also
provides a high input to the NAND gate E28 causing the output to
switch low.
This low goes to the preset
input of the flip-flop
El14 and clamps the output high which holds the microprocessor in
the DMG mode.
The requesting device maintains the BSACK L input

low for the duration
This removes the low

of the DMA transfer and then sets it high.
from the preset input of flip-flop El1l4 and

enables the flip-flop.
was
inverted
as
a
low

Previously the BDMR
to
flip-flop El4.

through by COUT and provides
The low is now clocked

El14.

go
high
which
microprocessor

a low input to the enabled
through causing the -CDMRQ

outputs.
The preset
input of
the low data
input
is clocked

high.

The

DMG

output

complete

the

DMA

transaction.

8.15

The

TSYNC

output

microprocessor
low for

IAK

flip-flop
to

output

removes
the
request
from
the microprocessor.
The
completes the DMA interrupt transaction and negates

the SEL1 and SELO
no longer low and

goes

L input went high and
This
low was
clocked

(Figure

controlled

and DMA

goes

low

and

the

8-24)

1is

normally

Fetch/Read

transactions.

-DMG

and Write

These

flip-flop E22 is
through when RAS

output

goes

high

for

the

high

transactions

conditions

-SEL1 input which is high and low for the same transactions.

and
the

The

exclusive OR gate E32 acts as a non inverting buffer and yhen RAS

goes high the -SEL1 input of the TSYNC flip-flop E20 is clock
Whenever the —-CSYNC clear input goes low,
through as the output.
The
it forces the output of the TSYNC flip-flop E20 to go low.

CSYNC

TCLKSP
TCLKSP

flip-flop

E20

normally

has

the

clear

and the output to the AND gate E1l1l
input goes high the input of the

input

pulled

low

When tt}e
is high.
CSYNC flip-flop is

enabled. At this time the -DRRPLY clock input is low and goes high
to clock the flip-flop shortly before the TCLKSP input gets reset.

If a DMA transaction is in progress the -DMG input is high and Fhe

CSYNC

flip-flop output

remains

low when

clocked

by -DRRPLY going

For any transaction other than the DMA, the -DMG input 1s
high.
low and the CSYNC flip-flop output goes high when clocked by —RPTM

going high.

TSYNC

This allows the CSYNC output to go high and clegr the

flip-flop E20 the write byte flip-flop E17

WT flip-flop E4

in Figure 8-25.

and

the

disable

6-+3 \Y
—SEL1

—_—

O— —T SYNC
Q

é;+3v =
_DMG

TSYNC

E20

RAS

|
E20

EE—

o-—_@c

—DRRPLY

_CSYNC

fi’

TCLKSP
—BCLR

MR-6655

8-24

TSYNC

8-25)

controls

Figure

READ/WRITE

8.16

(Figure

logic

The Read/Write

the

read,

write,

and

sets

both

R/-WLB

and

fetch transactions for the microprocessor and supports the IAK and
The microprocessor controls the R/-WLB and
DMA transactions.
R/-WHB inputs to select either BDIN, BDOUT or BWTBT bus signals.
To

select

R/-WLB
enable

the

BDIN output

inputs high

the

NOR

gate

the microprocessor

the NAND gate E28.,

E21

and

disables

the

The output goes low to

AND

gates

El18

and

Ell.

When
The -TSYNC input to E21 is low for read/write transactions.
TDIN
The
high.
goes
the -CAS input goes low, the TREAD output
gate
NAND
of
output
BDIN
the
and
output of OR gate E13 goes high
E21 goes 1low.
except for DMA
IAKDIN

high

input

and

BDIN

The -DMG input to the NAND gate is always high
During interrupt transactions, the
transactions.
E13

low.

enabled

The
microprocessor
determines
either R/-WLB or R/-WHB input
The

output

NAND

gate

E28

high,

and

also

causes

any write
condition
low or both of these

goes

high

allows

the

and

enables

TDIN

by
setting
inputs low.

the

AND

gates

The output of flip-flop E4 is high and the -CAS
E1ll and E18.
input to AND gate E18 is also high.
The output of AND gate EI18
The DMA input
goes high and the output of OR gate E31 goes high.
to NAND gate

high and

BWTBT output

low.

this time the write destination address is written onto the bus.
The logic now determines if the data being written is a word or a
The exclusive OR gate E32 monitors the R/-WLB and R/-WHB
byte.
A
inputs and the output goes high when the inputs are different.
output
low
a
and
byte
a
is
data
the
indicates
high output
indicates the data is a word.
The output goes to flip-flop El7.

8-39

—DMG

5"'3 \Y
—SEL1

—RAS

E26

—pI

0———

—

£18

BWTBT

£31

—CAS
g+3 v

—,—j

E17

E32

0
—CSYNC

[

TREAD

R/WLB

R/WHB

E28

—] E2

2DIN

—TSYNC

TDIN

IAKDIN

TDOUT

BDOUT

TSYNC

-~
-

=
iy

"’
=

-,
i &

—

"-!—-—“—-—'_—-» —RAS
—
TSYNC

E49 PIN 4
E20PIN
5

-—w—o ——aE——— —CAS

—

—
_1._‘
b

E49 PIN 15

TDOUT

E11PINS8

R/-WLB

E32PIN?2

R/—WHB

E28 PIN 4

................

WBYTE

—~—
Y

—

T e
=

—

——

]

E17PIN 2

WRITE

E28PING

E18 PIN 6

—CSQ8B

E40 PIN 16

—CSLIP

E11PIN 1

_NOBYTE E4 PIN6
E17PIN5

TWTBT

E31PING

Signals for Read/Write logic

Figure

8-25

Read/Write

The microprocessor asserts CAS,
the CAS
input to E17 and E9 goes
high and -CAS input to E18 goes low.
The -CAS input to AND gate
E18
switches
the
output
low,
to
remove
BWTBT but
the CAS
input
clocks
flip-flop E17
and
enables
the WBYTE
signal
to
E31.
The

output

for

word

the

asserted low
transaction.

and
AND

when
gate

flip-flop

E17

transactions.

high

for

byte

BWTBT

signal

transaction

for

The

TSYNC

and

the

input

goes

Ell

enabled

output high.
going low and

This

byte

writes

The
CAS

inputs

high

the

transactions

will

negated

to AND gate
gate output

either
high

for

and

low

remain
a

word

E9 are set
goes high.

high
The

and
the
output
of
E9
switches
the
TDOUT
inverted and the BDOUT output is enabled by

the

data

word.

At the same time the -RAS and -PI inputs to NOR gate E26 are both
low switching the output high.
The high clocks flip-flop E4 and
the output goes low.
This inhibits the AND gate E18 when the -CAS
input goes high again.
The flip-flops are reset by CSYNC at the
end

the

8.17

transaction.

TIMEOUT

The Reply Timeout
1logic
(Figure 8-26)
monitors
the
bus
BRPLY
L
input
to
indicate
that
an
LSI-1]1
bus
device
responds
to
an
address, The TMER flip-flop E5 output
is normally set low by the

RAS input to clear the flip-flop.
The BRPLY L input
inverted so the RRPLY output
is 1low.
The -TMRP NOR

are

both

low and

initiated

the

the -TMRP output

either

TDIN

(50

usec

timeout

start.

The

microprocessor

the

BRPLY

complete.,

input

When

BRPLY

cycle

go
L

TDOUT

slips)

starts

low

high.

inputs
to

low,

slip

the

transaction

high.

monostable
cycle

indicating

switches

The bus

going

This

waiting

transaction
output

enables

multivibrator
while

bus

RRPLY

is high and
gate
inputs

goes

to
for

can
high

and the -TMRP output goes low.
The TMER output remains low.
If
the BRPLY L does not go low and the 50 usec timeout circuit allows
the 50 cycle slips and the TMER flip-flop is clocked and the TMER
output goes high.
This also forces the -TMRP output to go 1low.

The assertion of the TMER output goes to the HALT logic and
microprocessor action is dependent upon the configuration of

module,

The

-TMRP

output

goes

disables

cycle

slips

logic,

and

clock.
enables

The
RRPLY
bus data to

the

and

Clock

the

Enable,

start/stop

the
XTL1
output
goes
to
the
Bus
Control
1logic,
and
be received during LSI-11 bus device reads.

RRPLY

6'+3V

E26

~TMRP

+5 =y

TDIN

SYNC,

TDOUT

E6
D-

RAS
MR.6657

Figure 8-26

Reply Timeout

the
the
Ready

BUS CONTROL

8.18

The Bus Control logic (Figure 8-27) controls the transmit and
The transceivers are
receive functions of the Bus Transceivers.
Read/WRite and
controlled
or
microprocess
for
in transmit mode
during LSI-1l1
and
I/0
Local
memory,
local
to
Fetch transactions
during an
mode
receive
the
to
go
transceivers
The
bus writes.
receive
the
to
go
s
transceiver
the
DMA,
During
read.
bus
I.SI-11
mode to accept the local device address and will stay in this mode

until the device is addressed.
When
a read transaction occurs,
When the -BCLR input
the transceivers go into the transmit mode.
is high the transceivers are able to transmit data and when -BCLR
During an IAK
is asserted low, the transceivers are disabled.

mode

the

vector.

TDAL 0-15

BDAL 0-15

RLB

£31

RRPLY

RHB
—CsQB

005
BUS

TRANSCEIVER

E10

|
E10

E19

LOW BYTE

E11

DMG

{E45, E51)

[

HIGH BYTE

T SYNC .’

(E59, E57)
E19

E36

XLB

XHB

E18

BINITL

E16

TDAL 13

TDAL 14
L 15

TDAL 15 |

—RSYNC

RBS?7

B’ O——de1s

E35

disable
receive

low to
to the

transaction, the -IAK input to AND gate E18 goes
the transceiver high byte and the low byte goes

BBS7L

SEL1

MR.6658

Figure

8-27

Bus

Control

The

receive
function of
the
bus
transceivers
transmit function any time the receive
inputs

When

data

low

The

and

TREAD

read

inverter
input

from

LSI-11

E10

makes

AND

gate

E1l8

function.
When the data
is on the
gate E18 goes high and the output of

gates

read

E31

Receive

onto

allow

High

the

Byte

TDAL

high

inputs

bus.

TIAKO

input goes high and

transcelvers.

the

input

set

bus
the

high

enable

During

interrupt

the

transceivers.

enables only the

the

-CSQB

AND

for

input

gate

the

El8.

receive

the DRRPLY input to
gate goes high.
The

override
the
enabled high.

are

device,

output

and

bus

high

will

Receive

AND
two

Low

Byte

transaction,

the

Receive

The

data

Low Byte

now

input

The

DMG

transaction

grants

bus

control

requested
the direct memory grant.
the duration of the DMG transaction.
gate

Ell1

and

the

NAND

gate

E19.

device

that

The DMG
input goes high
This input enables the

for
AND

The

the

BSYNC

external

input

high

and

inverted low to the two NAND gates E19.
This switches the NAND
gate outputs high and the receive and transmit functions are both
enabled.
However,
the
receive
function overrides
the
transmit
function and the TDAL bus receives data from the BDAL bus.
This
condition exists until
the bus master asserts the BDIN
L
input
low.
It
is
inverted
high and
enables
the NAND gate E19.
The
-CSQB input is dependent upon the address received from the BDAL
bus.
This input is low if the address is a bus location and high
if the address is for the local memory or I/O0 device.
A low input
sets
the output of NAND gate E19 high and
enables
the receive
function of the transceivers.
At the same time,
the -CSQB
1low
input is inverted high and the output of NAND gate El19 is switched
low to disable the transmit function.
When
the -CSQB
input
1is
high indicating the local memory is being addressed, the NAND gate
E19 is enabled.
The -CSQB high input is also inverted low to NAND
gate E19
and
enables
the receive function.
The bus master now
asserts either BDIN L or BDOUT L bus signals.
The -READ input

goes
low
for
the BDIN
L
signal
and goes high
for
the BDOUT L
signal.
If -READ goes high, it is inverted low and switches the
output of NAND gate E19 high to enable the receive function.
If
-READ goes low,
it is inverted high and
switches the output of
NAND gate
function
the BDIN

E19

low

inhibit

remains enabled.
L bus signal, the

when it asserts the BDOUT
module even if it was not

The

BBS7

I/0

the

consists

normally

bytes of
possible
this

bus

signal

the

upper

page

reserved

and
low
NOR

function

and

the

transmit

L bus signal
addressed.

the

enabled

whenever

address
bytes

low

portion

from

for

I/0

devices

page,

the

TDAL

data

received

the

64KB.

the

bus

LSI-11

This

bus,

the

addresses

This

transaction.

56KB

page

|is

the

but

within this page.
It is also
bytes of memory located within

page.

and

this

are

inputs

NAND

bus

gate

bits

E35.

13,

The

14,

output

and

are

set

switched

low

goes to the NOR gate E26.
The SEL1 input to NOR gate E26
for read, write and fetch transactions.
When both inputs
gate
E26
are
1low,
the
output
is
switched
high.
This

inverted
RBS7

the

receive

local RAM memory resides
to have an additional 2K

address

high

during

the

Therefore, when the bus master asserts
data is transmitted from the module and

low

for

BBS7

output.

high.

8-43

inverted

again

Iis
to
1is

set

CHAPTER 9
LSI-11 BUS

9.0
The

GENERAL
LSI-11 bus provides

such

processors,

each

other.

Not

SBC-11/21.

Only

all

For

reader

referred

The

LSI-11

are for
control
There

bus

four

Six

the

The

bus

functions

signal

treatment

PDP-11

LSI-11

to
are

are
of

type

modules

communicate

with

supported

1in

the
this

bus

the

described
the

LSI-11

Handbook.
18

are

supports

control

transfer

Bus

lines,

SBC-11/21

groups

data

interfaces

complete

has

the

for

and

supported

control.
lines.

are

the

chapter.

interconnections

memories,

devoted

only

data

and

lines

and

lines.

control

lines:

access

control

BBS7
BDIN

BDOUT
BRPLY

BSYNC

BWTBT

Four

direct

memory

lines:

BDMGI
BDMGO

BDMR

BSACK

Six

interrupt

control

lines:

BIAKI
BIAKO

BIRQ4

BIRQ5
BIRQ6
BIRQ7

Six

Not
Not
Not

used
used
used

system

by
by
by

SBC-11/21
SBC-11/21
SBC-11/21

control

lines:

BDCOK

BPOK
BHALT
BINIT

BREF

Not

used

SBC-11/21

BEVNT

(Refer

Table

9-4

for

functional

description

these

signals.)

Most LSI-11 Bus signals are bidirectional and use terminations for
a negated (high) signal level.
Modules connect to these lines via
high-impedance
bus
receivers
and
open
collector
drivers.
The
asserted state is produced when a bus driver asserts the line 1low.
Although bidirectional lines are electrically bidirectional
(any
point along the line can be driven or received), certain lines are
functionally unidirectional.
These lines communicate to or from a
bus master or signal source, but not both.
Interrupt acknowledge
(BIAK)
and
direct
memory
access
dgrant
(BDMG)
signals
are
physically unidirectional in a daisy-chain fashion.
These signals
originate at the processor output signal pins.
Each is received
on
device
input
pins
(BIAKI
or
BDMGI)
and
conditionally
retransmitted
signals
are
retransmitted

9.1

via
device
output
pins
(BIAKO
or
BDMGO).
These
received
from
higher
priority
devices
and
are
to lower priority devices along the bus.

SBC-11/21

SINGLE

BOARD COMPUTER

The SBC-11/21 module functions on the LSI-11 bus and can act as a
bus-master,
a
bus
slave,
or
a
bus
arbitrator
and
allows
a
DMA
master

access

the

board

functions.

The

module

supports

only

16 data/address lines and terminates the excess lines.
It also
contains its own on-board memory and accesses the bus for external
memory
or
devices.
It
should
be
noted,
however,
that
while
accessing its on-board devices the SBC-11/21 asserts bus control
signals in the same manner as when communicating with the LSI-11
bus. The memory maps defining on-board and external addressing are
described in Chapter 2.
The module's microprocessor supports an
on
board
multilevel
interrupt
structure
and
the
BIRQ4
bus
interrupt control
1line
is
an
active
bus
interrupt with
a
1level
four priority.
Therefore the BIRQ5, BIRQ6, and BIRQ7 bus control
interrupt lines are not recognized or accepted by the SBC-11/21
module.
The DMA request is recognized by the module at the lowest

interrupt

1level,

but

once

the

DMA

master

there are no other
interrupts until
the DMA master relenquishes the bus.
support

the

9.2

BREF

control

MASTER/SLAVE

Communication

line

for

has

accessed

the

bus,

the transfer is complete
The module does not use

refreshing

dynamic

or
or

memory.

RELATIONSHIP

devices
on
the
bus
is
asynchronous.
A
master/slave relationship exists throughout each bus transaction.
At any
time,
there
is one device
that has
control
of
the bus.
This
controlling
device
is
termed
the
bus
master.
The
master
device controls the bus when communicating with another device on
the
bus,
termed
the
slave.
The
bus
master
(typically
the
processor

between

DMA

device)

initiates

device

bus

transaction.

The

slave

responds by acknowledging the transaction in progress and
by receiving data from, or transmitting data to, the bus master.
LSI-11
Bus
control
signals
transmitted
or
received
by
the
bus

master

bus

or bus
protocol.

The

processor

device

controls

master

processor,

the

any

slave

given

must

bus

time.

master,

complete

arbitration,
typical

fetching

the

i.e.,

example

sequence

who
this

instruction

according

becomes

bus

relationship

from

memory,

which is always a slave.
Another example is a disk, as master,
transferring data to memory as slave.
Communication on the LSI-11
Bus is interlocked so that for certain control signals issued by
the master
device,
there must be a
response
from
the
slave
in
order
to
complete
the
transfer.
It
is
the master/slave signal
protocol that makes the LSI-11 Bus asynchronous.
The asynchronous
operation precludes the need for synchronizing with,
and waiting
for, clock pulses.
Since
bus
cycle completion by the
bus
master
requires
from
the
slave device,
each
bus
master must
include a

error

response
time-out

circuit that will abort the bus cycle if the slave device
respond to the bus transaction within 10 microseconds.

does

not

The

actual

time

before

the reply
bus.

time

slowest

The

assignments

signal

the

time-out

are

Table

occurs

peripheral

shown

9-1

error

in Table

memory

longer

device

Signal Names

Data/Address

BDALO,

BDALl,

Data

BDOUT,

BRPLY,

BDAL2...BDAL1lS,
BDIN,

BSYNC,

BWTBT,

BBS7

Interrupt

DMA

System

+12

Vvdc

-12

vdc

GND

SSPARES

MSPARES

PSPARES

Control

Vvdc

(battery)

the

Signal Assignments

Functional
Category

than

9-1.

Number
of Pins

Control

must

BIRQ4,
BDMR,

BHALT,

BIAKO,
BDGO,

BIAKI

BDMGI,

BDCOK,

BPOK,

BSACK

BEVNT,

BINIT

DATA TRANSFER BUS CYCLES

9.3

Data transfer bus cycles are listed and defined in Table 9-2.
NOTE

The

SBC-11/21

microcomputer

performs

read
transaction before
every write
transaction.
It does not perform DATIO
or
DATIOB
bus
transactions
as
one
address.
It
executes
read-modify-write
instructions by addressing the source as
one
transaction
and
addressing
the
destination as another transaction.

Data Transfer Operations

Table 9-2

Function (with Respect
to the Bus Master)

Bus Cycle
Mnemonic

Description

DATI

Data word

DATO

Data word output

Write

DATOB

Data byte output

Write byte

These

bus

cycles,

Read

input

executed

bus

master

words or 8-bit bytes to or from slave
listed
in
Table
9-3
are
used
in
the
described in Table 9-2,

Table

9-3

Mnemonic
BDAL

<15:00>

Bus

Signals

Used

in Data

Description
L.

devices,

transfer

Transfer

Operations

Function

Data/address

lines

BDAL<K15:00>

for
word
transfers.

BSYNC
BDIN

L
L

Bus Cycle Control

Strobe

signal.

Data

input

Strobe

signal.

output

Strobe

signal.

Strobe

signal.

BDOUT

Data

BRPLY

Slave's

bus
BWTBT

BBS7

indicator

acknowledge

cycle

Write/byte

control

I/0 device select
Indicates address

the

16-bit

devices.
The bus signals
data
transfer
operations

I/0

page

9-4

are

and

Control

signal,

Control

signal.

used

byte

Data

and
one

transfer

bus

cycles

can

reduced

DATO(B). These transactions
slave device selected during

two

basic

types:

DATI,

occur between the bus master
the addressing portion of the

and
bus

cycle.
9.3.1

Bus

Refore

have

Cycle

initiating

Protocol

been

completed

addressing

portion,

bus

master.

The

bus

cycle,

the

(BSYNC

and

data

bus

cycle

negated)

can

and

bus

the

divided

transfer

transaction

device

into

must

two

portion.

must

become

parts,

During

the

addressing portion,
the bus master outputs the
address
for
the
desired slave device,
memory location or device register.
The
selected slave device responds by latching the address bits and
holding this condition for the duration of the bus cycle until
BSYNC L becomes negated.
During the data transfer portion, the
actual

9.3.1.1

data

transfer

Device

occurs.

Addressing

The

device

data transfer bus cycle comprises an
and an address hold and deskew time.,
deskew time, the bus master does the

Asserts

BDAL

address

bits

Asserts

BBS7

<K15:00>

with

a device

addressing

portion

address setup and deskew time
During the address setup and
following:

the

desired

I/0 page

SBC-11/21)
is being
addressed.
Devices
ignore BDAL <15:13>,
and decode BBS7 L

slave

device

(56--64 Kb for

in the I/0
along with

page
BDAL

<12:00>.

Asserts

BWTBT

Inactive

BWTBT

Asserts

L
The

and

address,

BSYNC
BWTBT L

BBS7

L
L

if
the
cycle
is
a
DATO(B)
bus
cycle.
indicates a DATI or DATIO (B) operation.

at least 150
are valid.

and

BWTBT

after

signals

slave bus
receiver for at least 75 ns
The address hold and deskew time begins

BDAL

must

<15:00>

asserted

BBS7

the

before BSYNC goes active.
after BSYNC L is asserted.

The slave device uses the active BSYNC L bus receiver output to
clock BDAL address bits,
BBS7 L,
and BWTBT L
into
its
internal
logic.
BDAL <15:00> L, BBS7 L, and BWTBT L will remain active for
25 ns
(minimum)
after BSYNC L bus
remains active for the duration of
Memory devices
page;
however,

receiver goes active.
the bus cycle.

generally do not
respond
to addresses
some
system
applications
may
permit

reside in the I/0 page for use
bootstraps or diagnostics, etc.

DMA

buffers,

BSYNC

in the
I/O
memory
to

read-only

memory

SLAVE

BUS MASTER

(MEMORY OR DEVICE)

(PROCESSOR OR DEVICE)
ADDRESS DEVICE MEMORY
*+ ASSERT BDAL <15-00> L
'

ADDRESS AND

e ASSERT BBS7 IF THE ADDRESS
IS IN THE 56-64 K BYTE RANGE
e ASSERT BSYNC L

———

DECODE ADDRESS

e STORE"”DEVICE SELECTED"
OPERATION

-—

REQUEST DATA

» REMOVE THE ADDRESS FROM
BDAL <15-00> L AND

NEGATE BBS7 L
——

e ASSERT BDIN L

—

——

INPUT DATA

¢ PLACE DATA ON BDAL <15-00> L
R ASSERT BRPLY L
—

—

TERMINATE INPUT TRANSFER

e ACCEPT DATA AND RESPOND
BY NEGATING BDIN L

—_—
—

—~—

TERMINATE BUS CYCLE
e NEGATE BSYNC L

OPERATION COMPLETED
e NEGATE BRPLY L
e REMOVE DATA FROM
BDAL <15-00> L

MR-7195

DATI Bus Cycle

Figure 9-1

DATI -- The DATI bus cycle,
operation.

transfer

data are

During DATI,

consist of 16-bit word
portion

the

illustrated in Figure 9-1, is a read

DATI

Data

input to the bus master.

transfers over the bus.
bus

cycle,

the

During

bus master

BDIN L 100 ns minimum after BSYNC L is asserted.
responds to BDIN L active as follows:

the data

asserts

The slave device

125
L and
BDIN
receiving
Asserts BRPLY L after
(maximum) before BDAL bus driver data bits are valid

Asserts BDAL <15:00> L with the addressed data

When the bus master receives BRPLY L, it does the following:
o

Waits at least 200 ns deskew time and then accepts

Negates

input

data at BDAL <15:00> L bus receivers.

(maximum)

BDIN

150

(minimum)

after BRPLY L goes active.

9-6

microseconds

NOTE

Continuous
control

and

assertion

the

device

of BSYNC L retains
bus
by
the
bus
master,
previously
addressed
slave
the

remains
selected.
Also,
a
slow
slave device can hold off data transfers
to
itself by keeping BRPLY L asserted,
which
will
cause
the
master
to
keep
BSYNC L asserted.

The

slave device responds to BDIN L negation by negating
and
removing
read data
from
BDAL
bus
drives.
BRPLY
L
negated 100 ns
(maximum)
prior to removal of read data.

master

responds

Conditions

for

the

negated

the

BSYNC

BSYNC
L
previous

Figure

9-2

L must

BRPLY

assertion

remain negated

must
BRPLY

illustrates

bus

negating

are

for 200

not
become
L negation
DATI

asserted

cycle

BSYNC

The

output

when

data

setup

data

transfer

and

During

can

BWTBT

occur

has

portion

deskew

time

data

setup

the

BDAL

<15:00>

after

been

within

300

and

deskew

least

data

addressing

hold

portion

the

bus

cycle

and

time,
100

timing.

DATO(B)

and

the

asserted

(minimum)

=-DATO(B),
illustrated
in
Fiqure
9-3,
is
operation.
Data is transferred
in 16-bit words
(DATO)
bytes
(DATOB)
from the bus master to the slave device.
transfer

follows:

DATO(B)

cycle

BRPLY

must
be
The bus

bus

master.

deskew

the

a
write
or 8-bit
The data

comprises

data

time.

master

outputs

the

after BSYNC L is asserted.
If it is a word transfer, the bus master negates BWTBT L at least
100 ns after BSYNC L assertion.
BWTBT L remains negated for the
length of the bus cycle. If the transfer is a byte transfer, BWTBT
L remains asserted. During a byte transfer, BDAL 00 L selects the
high or low byte. This occurs while in the addressing portion of

the
cycle.
If
asserted,
the
high
byte
(BDAL
<15:08>
L)
is
selected;
otherwise,
the
low byte
(BDAL <07:00> L)
is selected.
The bus master
asserts
BDOUT
L at
least
100
ns after BDAL and
BWTBT

L
bus
drives
are
stable.
The
slave
device
responds
by
asserting BRPLY L within 10 microseconds to avoid bus time-out.
This completes the data setup and deskew time.

During the data hold and deskew time the bus master receives
L and negates BDOUT L.
BDOUT L must remain asserted for at
150

master.

100

from

the

BDAL

ns after
inputs.

receipt

<15:00>

BDOUT

BRPLY

bus

before

drivers

negation.

The

being

remain

bus

negated

asserted

master

then

for

BRPLY
least

the

negates

bus

least

BDAL

TIMING AT MASTER DEVICE

T/RDAL (44 X T ADDR

(4)

RrRDATA

(4)

100 s MIN

200 ns MAX

150 ns

NN ]

T SYNC

s MAX

T DIN

MAX
150 nsnsMIN
e— 2,000

o
;oo ns MIN

DATA

200 s

MIN

R RPLY

—

CLOCK

300 ns MIN——s
f—

e— 150 Ns MIN
—

T8s7 (41X

100 ns_MIN

(4)

TWTBT (@)

TIMING AT SLAVE DEVICE

R/TDAL

(4 X RADDR

pod lvgennd
bun
MIN ¥

rRsyne

(4)

—ef
0 ns

Ttoata

125 ns MAX -+

75 nsle rM'N le—150 ns MINi

[+100 ns MAX,0 ns MIN
|

150 ns ]

MIN

R DIN

(4)

300 NS MIN—s

T RPLY

rRBs7

RWTBT

—_—1
(4 X

(4)

le—75 ns MIN
X

—|

(4)

be—25 ns MIN
A

(4)

NOTES:

1. TIMING SHOWN AT MASTER AND SLAVE DEVICE BUS DRIVER
INPUTS AND BUS RECEIVER OUTPUTS

2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T = BUS DRIVER INPUT

R = BUS RECEIVER OUTPUT

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT SIGNAL
NAMES INCLUDE A “B” PREFIX

4, DON'T CARE CONDITION
MR-7180

Figure

9-2

DATI

Bus Cycle Timing

SLAVE

BUS MASTER

(MEMORY OR DEVICE)

(PROCESSOR OR DEVICE)
ADDRESS DEVICE/MEMORY
e ASSERT BDAL <15-00>L
WITH ADRESS AND

e ASSERT BBS7 L (IF ADDRESS IS
IN THE 56-64 K BYTE RANGE
e ASSERT BWTBT L (WRITE
CYCLE)

e ASSERT BSYNC L

\
—_

——

— —_—
~n

DECODE ADDRESS

e STORE“DEVICE SELECTED”

- -~

OUTPUT DATA

= OPERATION

FROM
VE
ADDRESS
MO
« RETHE
>
AND NEGATE
L-00
BDAL <15
L
BBS7 L AND BWTBT

« PLACE DATA ON BDAL <15-00> L
«

ASSERT BDOUT L

—

\\ — —_—
~n

TAKE DATA

o RECEIVE DATA FROM BDAL
LINES

__e ASSERT BRPLY L

TERMINATE OUTPUT TRANSFER 4
¢ NEGATE BDOUT L (AND BWTBT L
|F A DATOB BUS CYCLE)
«

REMOVE DATA FROM

BDAL <15-00> L

—

/ //

T —

/’

m— /

TERMINATE BUS CYCLE
e

/ -

OPERATION COMPLETED
o NEGATE BRPLY L

/ /

NEGATE BSYNC L

Figure 9-3

DATO or DATOB Bus Cycle

MR-7196

The
During this time, the slave device senses BDOUT L negation.
bus
The
L.
BRPLY
negates
device
slave
the
and
data are accepted
will
processor
the
However,
L.
BSYNC
negating
by
master responds
not negate BSYNC L for at least 175 ns after negating BDOUT L.
Before the next cycle BSYNC
This completes the DATO(B) bus cycle.
Figure 9-4
L must remian unasserted for at least 200 ns.
illustrates DATO(B)

bus cycle timing.

—DI

T DAL

(4)

T ADDR

T DATA

MIN "l MIN | '

l‘_ 150ns

T SYNC

100ns

MIN

r—

(4)

—p| 100ns |.

¢ Bus

e— 175ns MIN

MAX

T DOUT

Ons MIN

150ns MIN—-|

R RPLY

J‘

—le—— 200ns MIN ———

L—-

300ns MIN

%
-

TBS7

(4)

TWTBT

|-— 100ns MIN

——I 150ns MIN pa—

)(

(4)

ASSERTION = BYTE

L150nsM|N- 100ns L—

(4)

—ol 100ns MIN L—

MIN

TIMING AT MASTER DEVICE

R DAL

(4)

X R ADDR X

—

R SYNC

I 75ns

MIN

R DOUT

T RPLY

25ns MIN

—TM

L——25ns MIN

e—— 100ns MIN ——oL— 150ns MIN —fi
ns

2505 |

——| 150ns MIN -—\

R BS7

(4)

R WTBT

(4)

75ns MIN

25ns MIN 4

L—- MIN

—d

[#—

{(4)

—

75ns

r— 300ns MIN —————

MIN

——-—‘

(4)

25ns
MIN

[
,

R DATA

ASSERTION =BYTE

25ns MIN

L— 25ns MIN

(4)

TIMING AT SLAVE DEVICE
NOTES:

1. TIMING SHOWN AT MASTER AND SLAVE DEVICE

BUS DRIVER INPUTS AND BUS RECE!VER QUTPUTS.
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT

SIGNAL NAMES INCLUDE A “B"” PREFIX.
4. DON'T CARE CONDITION.

T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT
MR-1179

Figure

9-4

DATO

DATOB

Bus

Cycle

Timing

9.3.2

Direct Memory Access

DMA is accomplished after the processor (normally bus master) has
passed bus mastership to the highest priority DMA device that is
requesting the bus.,
The processor arbitrates all requests and
grants the bus to the DMA device located electrically closest to
it.
A DMA device
remains
bus
master
indefinitely
until
it
relinquishes its mastership.
The following control signals are
used

during

bus

arbitration.

BDMGI

DMA

Grant

Input

BDMGO

DMA

Grant

Output

BDMR L
BSACK L

DMA Request Line
Bus Grant Acknowledge

A DMA transaction can be divided
o
o

into

Bus mastership acquisition
Data transfer phase

three phases:

phase

Bus mastership relinquish phase

During the bus mastership acquisition phase, a DMA device requests
the bus by asserting BDMR L. The processor arbitrates the request
and initiates the transfer of bus mastership by asserting BDMGO L.
The maximum time between BDMR L assertion and BDMGO L assertion is
DMA latency. This this is processor-dependent. BDMGO L/BDMGI L is
1in the
one signal that is daisy-chained through each module
backplane. It is driven out of the processor on the BDMGO L pin,

enters each module on the BDMGI L pin and exits on the BDMGO L
pin. This signal passes through the modules in descending order of

priority

until

1is

stopped

the

requesting

device.

The

requesting device blocks the output of BMDGO L and asserts BSACK
L. If BDMR L is continuously asserted, the bus will be hung.

During the data transfer phase, the DMA device continues asserting
BSACK L. The actual data transfer 1is performed as described
earlier,

NOTE

If multiple data transfers are performed
during this phase, consideration must be
given to the use of the bus for other
system

The DMA device
(minimum) after
become

functions.

can assert BSYNC L for
it receives BDMGI L and

a data transfer 250 ns
its BSYNC L and BRPLY L

negated.

During the bus mastership relinquish phase, the DMA device
relinquishes the bus by negating BSACK L. This occurs after
completing (or aborting) the last data transfer cycle (BRPLY L
negated). BSACK L may be negated up to a maximum of 300 ns before

negating

BSYNC

Figure

9-5

illustrates

the

DMA protocol

and

BUS MASTER

SBC-11/21 MICROPROCESSOR

(CONTROLLER)

(MEMORY IS SLAVE)

GRANT BUS CONTROL
® NEAR THE END OF THE
CURRENT BUS CYCLE

(BRPLY L IS NEGATED).

ASSERT BDMGO L AND
INHIBIT NEW PROCESSOR

THE DURATION OF THE

DMA OPERATION.

TERMINATE GRANT

SEQUENCE

® NEGATE BDMGO L AND

.. REQUEST BUS
® ASSERT BDMR L

WAIT FOR DMA OPERATION
TO BE COMPLETED

”,/”

~~w_

\\‘

MASTERSHIP

_ ==

OF
IT
FOR NEGATION
®WA

® RECEIVE BDMG
L AND BRPLY L
BSYNC

® ASSERT BSACK L
o NEGATE BDMR L

TM EXECUTE A DMA DATA
TRANSFER

e ADDRESS MEMORY AND
TO 4 WORDS
UPSFER
TRAN
OF DATA AS DESCRIBED
FOR DATI, OR DATO BUS
-

gEgg“A"EIgT\IOCESSOR

CYCLES

BY
THE BUS E
® RELEAS

TERMINATING BSACK L

(NO SOONER THAN
NEGATION OF LAST BRPLY

L) AND BSYNC L.

® ENABLE PROCESSOR-

GENERATED BSYNC L

(PROCESSOR IS BUS

WAIT 4usOR UNTIL

ANOTHER GRANT IF BDMR
L IS ASSERTED.

IS PENDING BEFORE
REQUESTING BUS AGAIN.

MASTER) OR ISSUE

ANOTHER FIFO TRANSFER

MR-7181

DMA Protocol

Figure 9-5

Figure 9-6

INTERRUPTS

Bus

signhals

BIRQ4 L
BIAKI L

BIAKO L
BDAL <15:00>
BDIN L
BRPLY

used

interrupt

transactions are:

Interrupt request priority level
Interrupt acknowledge input

Interrupt acknowledge output
Data/address lines
Data input strobe
Reply

The LSI-11

9.4

illustrates DMA request/grant timing.

SECOND

-q17

REQUEST

le— DMA LATENCY

T OMR

T"/‘;"/‘,"',",",'" 77TV
4

—-o'

0 ns MIN.

R DMG

T SACK

250 ns MIN,—=

R/T SYNC

WA\

R/T RPLY

IO—

250ns MIN-

—

0 ns MIN.

l*—300 ns MAX

L—

N\ LN
—

T DAL

—

e——(0 ns MIN.

ne MIN.

—

ADDR

(ALSO BS7

OR__X_

WTBT,REF)

alla

r»— 100
ns MAX

NOTES:

TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER
INPUTS AND BUS RECEIVER OUTPUTS.

SIGNAL NAME PREFIXES ARE DEFINED BELOW
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A “B* PREFIX
MR-7178

Figure

9-6

DMA Request/Grant Timing

9.4.1
Device
The
SBC-11/21

Priority
supports
only
one
method
of
device
priority
arbitration:
position-defined
arbitration
-priority
1is
determined solely by electrical position on the bus. The closer a
device is to the processor, the higher its priority is.
9.4.2
Interrupt Protocol
Interrupt protocol
on
the
SBC-11/21

has

three

phases:

request
phase,
interrupt
acknowledge
and
priority
phase, and interrupt vector transfer phase. Figure 9-7
the interrupt request/acknowledge sequence.

interrupt

arbitration
illustrates

SBC-11/21
MICROPROCESSOR

DEVICE
INITIATE REQUEST
—

STROBE INTERRUPTS

—_

ASSERT BDIN L

T \\

——*

ASSERT BIRQ4 L

RECEIVE BDIN L
*

‘

STORE “INTERRUPT SENDING

IN DEVICE

GRANT REQUEST
»

PAUSE AND ASSERT BIAKO L

—__ —
—_—

T T
RECEIVE BIAKI L
e

RECEIVE BIAK! L AND INHIBIT

PLACE VECTOR ON BDAL <15-00> L

ASSERT BRPLY

BIAKO
L

-+ NEGATE BIRQ L
/‘
—

RECEIVE VECTOR & TERMINATE

REQUEST
»

INPUT VECTOR ADDRESS

NEGATE BDIN L AND BIAKO L

\ —~—
T—

COMPLE
VECTOR TRANSFER
TE
e
’/l’_/,,,‘-

REMOVE VECTOR FROM BDAL BUS
NEGATE BRPLY

—

-—

PROCESS THE INTERRUPT
*

SAVE INTERRUPTED PROGRAM
PC AND PS ON STACK

LOAD NEW PC AND PS FROM
VECTOR ADDRESSED LOCATION

EXECUTE INTERRUPT SERVICE

ROUTINE FOR THE DEVICE
MR-7197

Figure 9-7

Interrupt Request/Acknowledge Sequence

The
interrupt
request
phase
begins
when
a
specific
conditions
for
interrupt
requests.

device
For

meets

its

example,

the

SBC-11/21

and

device
is ready,
done,
or an error has occurred.
The
interrupt
enable bit
in a
device
status
register must be set.
The device
then
initiates the
interrupt by asserting
the
interrupt
request
line. BIRQ4
is asserted

The

L is the only hardware priority
for all interrupt requests.

interrupt

acknowledged.

request

line

remains

asserted

level

until

the

request

During
the
interrupt acknowledge and priority arbitration phase
the
SBC-11/21
processor
will
acknowledge
interrupts
under
the
following conditions:

The

The device
PS<7:5>.

The processor has completed instruction
additional bus cycles are pending.

processor

interrupt

acknowledges

priority

the

interrupt

higher

than

the

execution

request

current

and

by asserting

BDIN

L,
and
225
ns
(minimum)
1later
asserting
BIAKO
electrically closest to the processor receives the
its BIAKI L bus receiver.

L.
The
device
acknowledge on

When

The

the

device

receives

the

acknowledge,

reacts

follows:

If not requesting an interrupt, the device asserts BIAKO
L and the acknowledge propagates to the next device on
the bus.

If
the
device
was
requesting
an
interrupt,
the
acknowledge is blocked using the leading edge of BDIN L
and
arbitration
is
won.
The
interrupt
vector
transfer
phase begins.

interrupt

vector

transfer

phase

enabled

BDIN

and

BIAKI

L. The device responds by asserting BRPLY L and its BDAL <15:00> L
bus driver
inputs with the vector address bits.
The
BDAL bus
driver inputs must be stable within 125 ns (maximum) after BRPLY L
is asserted.
The processor
then
inputs
the vector
address
and
negates BDIN L and BIAKO L. The device then negates BRPLY L and
100
ns
(maximum)
later
removes
the
vector
address
bits.
The
processor

then

enters

the

device's

Propagation

delay

from

BIAKI

than

500

not

LSI-11

Bus

slot.

The device must
microseconds

9.5
The

NOTE

asserts

Processor

BINIT

Initialize

BDCOK

BEVNT

External

Power

BIAKI

per

provide

halt

power

BIAKO

BRPLY L within 10
(maximum)
after
the

BHALT
H

assert

CONTROL FUNCTIONS
following LSI-11 Bus signals

BPOK

routine.

greater

must

processor

service

OK
Event

control

functions.

9.5.1

Halt

9.5.2

Initialization

9.5.3

Power

Refer to Chapter 2 for explanation of BHALT L response.

Devices along the bus are initialized when BINIT L is asserted.
The microprocessor can assert BINIT L as a result of executing a
RESET instruction or as part of a power-up sedquence. BINIT L is
asserted for approximately 17 microseconds when RESET is executed.
Status

Power status protocol is controlled by two signals, BPOK H and
BDCOK H. These signals are driven by some external device (usually
the

power

supply).

BDCOK H -- When asserted, this indicates that dc power has been
stable for at least 3 ms. Once asserted, this 1line remains
asserted until the power fails. Its negation indicates that only 5

microseconds of dc power reserve remains.

BPOK H -- When asserted this indicates that there is at least an 8
ms reserve of dc power and that BDCOK H has been asserted for at
least 70 ms. Once BPOK H has been asserted, it must remain
asserted for at least 3 ms. The negation of this line, the first
event in the power—-fail sequence, indicates that power is failing
and that only 4 ms of dc power reserve remains.
9.5.4

Power-Up/Down Protocol

begins when the power supply
(Figure 9-8)
Power-up protocol
applies power with BDCOK H negated. This forces the processor to
assert BINIT L. When the dc voltages are stable, the power supply
or other external device asserts BDCOK H. The processor responds
by clearing the PS. BINIT L is asserted for 17 microseconds and
then negated for 110 microseconds. The processor continues to test
for BPOK H until it is asserted. The power supply asserts BPOK H
70 ms (minimum) after BDCOK H is asserted. The processor then

performs its power-up sequence. Normal power must be maintained at
least 3.0 ms before a power-down sequence can begin.

A power-down sequence begins when the power supply negates BPOK H.
when the current instruction is completed, the microprocessor
traps to a power-down routine at location 24. The routine must

provide for loading 340 into the PSW, execute a RESET instruction
and must terminate in a WAIT instruction or branch on itself.

There
shoulq
be
no
DMA
requests
issued
after
the
RESET
is
gxecuted. This procedure prevents any possible memory corruption
in

the

battery

supported

system

the

voltages

decay.

NOTE

SBC-11/21
does
not
generate
BINIT
L
during
the
power-down
sequence.
The

power—-down
include
devices

routine

must

a RESET instruction
into a known state.

therefore

set

bus

O
B POK H

MAX

l-— 4ms MIN ——
)

—
!

DC POWER

—»f Tus L—

70ms MIN
BDCOK H

je—— 3ms MIN

-’

3ms

‘

MIN

—-I

70ms MIN

f¢————— 8ms MIN

Bus MIN

l.—

\__/

POWER UP

SEQUENCETM

‘_NORMAL_fi .

POWER DOWN

POWER

SEQUENCE

POWER UP

SEQUENCE

o NORMAL

PowER

NOTE:
ONCE A POWER DOWN SEQUENCE IS STARTED,
IT MUST BE COMPLETED BEFORE A POWER UP
SEQUENCE IS STARTED.
MR-1184

Figure

9-8

Power-Up/Power-Down

Timing

9.6

LSI-11 BUS ELECTRICAL CHARACTERISTICS
Configuring
LSI-11
bus
systems
requires
an
appreciation of
its
transmission line characteristics which can be best
obtained from
the PDP-11 Bus Handbook.

9.7
DIGITAL
contact

MODULE

CONTACT

plug-in

modules,

finger

bus

on the use of
connector. Each

and

solder

sides

IDENTIFICATION

including the SBC-11/21, all use the same
1identification
system,
The
LSI-11
bus
is

(pin)

based

FINGER

double-height modules that pPlug into a 2-slot
slot contains 36 1lines
(18 each on component
circuit board).

Slots,

shown as row A and row B in Figure 9-9,
include a numeric
identifier
for
the
side
of
the
module.
The
compecnent
side
is
designated
side
1
and
the
solder
side
is
designated
side
2.
Letters

ranging

identify a
identifies
summary

from

through

(excluding

and

0Q)

particular pin on a side of a slot. Table 9-4 lists and
the bus pins of the double-height module. For a quick

refer

Table

1-1.

The

bus

identifier

ending

with

is
found
on
the
component
side of
the
board,
while
a
bus
identifier
ending
with a
2
is
found
on the
solder
side of
board. A typical pin is designated as follows.
AE2:

Row

The

Side

pin
the

(o)

positioning
notch between the two
rows of pins mates with a
protrusion on the connector block for correct module positioning.

R__eo==Q=UoIo=R,
L

oo3 <

—

SIDE 2
ROW B

MR-7177

Figure

9-9

Double-Height

Module

9-18

Contact

Finger

Identification

Table
Bus
AEl

Mnemonics

9-4

Bus

Identifiers

Description

SSPARE1

(Alternate

+5B)

Special

Spare
in
DIGITAL
assemblies;

not assigned or bused
cable
or
backplane
available
for
user

connection.

Optionally,
this
pin may
be used for +5 V battery (+5B)
backup
power to keep critical circuits alive
during
power
failures.
A
Jjumper
|is

required on LSI-11 bus options to open
(disconnect)
the
+5B
circuit
in
systems that use this line as SSPARE]l.
AF1

SSPARE2

Special Spare
in
DIGITAL

-- not assigned or bused
cable
or
backplane

assemblies;
available
interconnection.
AJ1

GND

Ground

System

signal

for

user

ground

and

return.,

AK1

MSPAREA

ALl

MSPAREA

Maintenance
connected

Spare

together

each
option
connection).
AM1

GND

Ground

the

1location

System

signal

Normally
backplane

(not

Dbused

ground

and

return.

AN1

BDMR

Direct

Memory Access
(DMA)
Request -A
device
asserts
this
signal
to
request bus mastership.
The processor
arbitrates
bus
mastership
between
itself and all DMA devices on the bus.
If the processor is not bus master (it

has

completed

bus

cycle

and

BSYNC

is
not
being
asserted
by
the
processor),
it grants
bus
mastership
to the requesting device by asserting
BDMGO
L.
The
device
responds
by
negating BDMR L and asserting BSACK L.
AP1

BHALT

AT1

GND

Processor

Halt

Refer

Ground

System

signal

ground

Chapter

and

return.

AUl

PSPARE

Spare
not

(Not

assigned.

recommended.)

modules

are

9-19

Customer

Prevents

inserted

upside

damage

down.

usage
when

Table 9-4

Bus Pin

Mnemonics

AV1

+5B

(Cont)

Bus Pin Identifiers

Description

Secondary +5

+5 V Battery Power --

Battery power can be

power connection.

used with certain devices.

BAl

BDCOK H

DC Power OK -- Power supply-generated

BBl

BPOK H

Power

signal that is asserted when there
sufficient dc voltage available
sustain reliable system operation.

Asserted

power

the

is
to

supply 70 ms after BDCOK. Negated when
ac power drop below the value required
to sustain power (approximately 75% of

dur ing
negated
When
nominal) .
processor operation, a power fail trap
sequence

initiated.

BH1

SSPARES8

Special Spare -- Not assigned or bused

BJ1

GND

Ground

backplane
user
for

and
<cable
DIGITAL
in
available
assemblies;
interconnection.

-- System signal

ground

and dc

return.

BK1

BL1

MSPAREB

Maintenance

Spare

Normally

connected together on the backplane at
each option location
(not a
bused
connection).

BM1

GND

Ground

System

signal

ground

and

DMA

return.

BN1

BSACK L

BR1

BEVNT

BS1

PSPARE

This

signal

1is

asserted

device in response to the processor's
BDMGO
L signal,
indicating
that
the
DMA device is bus master.

External
Event
Interrupt
Request
-When asserted, the processor responds
(if
Ps
bit
7
1is
0)
by
entering
a
service
routine via vector address

100.

A typical

line

time

Power

Spare

function,

use

clock

not

this

signal

is a

interrupt.

(Not

recommended

assigned
for

use).

Table
Bus
BT1

9-4

Bus

Identifiers

Mnemonics

Description

GND

Ground

(Cont)

System

signal

ground

and

return.

BU1

PSPARE?2

Power

Spare

function,

a module is
and
if
the

inserted

BVl

-12

Vdc

not

(not

assigned

recommended

for

use).

using -12 V
(on pin AB2)
module
is
accidentally

upside

down

appears

the

backplane,

BUl.

Power

Normal

Vdc

system

Power

Normal

Vdc

system

power.,

AA2

power.

AB2

-12

Power

power

for

=12

Vdc

devices

(optional)

requiring

this

voltage.
NOTE

LSI-11 modules which
voltages
contain
an

require negative
inverter
circuit

(on each module)
which generates the
required
voltage(s).
Hence,
-12
V
power
is
not
required
with

AC2

GND

DIGITAL-supplied

options.

Ground

signal

System

ground

and

return.

AD2

+12

AE2

BDOUT

+12
L

Data

Power

Output

implies

that

<0:15>

BDAL

Vdc

system

BDOUT,

when

valid
L

data
and

power.
asserted,

that

available
an

output

transfer,
with
respect
to
the
bus
master device, is taking place. BDOUT
L is deskewed with respect to data on
the bus.
The
slave device
responding
to
the
BDOUT
L
signal
must
assert
BRPLY
AF2

BRPLY

response

complete

BRPLY
to

BDIN

the

transfer.

1is

asserted

BDOUT

1in
and

during
IAK
transactions.,
It
is
generated
by
a
slave
device
to
indicate that it has placed
its data
on
the
BDAL
bus
or
that
1it
has
accepted

9-21

output

data

from

the

bus.

Table

Bus
AH2

9-4

Bus

Identifiers

(Cont)

Mnemonics

Description

BDIN

Data Input -- BDIN L is
types of bus operation:

When

asserted

BDIN

implies

respect to
requires a

during

used

BSYNC

input

for

transfer

two

time,

with

the current bus master, and
response
(BRPLY L). BDIN L

is asserted when the master device is
ready
to
accept
data
from
a
slave
device.
When

asserted

indicates that
is occurring.

The

master

data

from

without

device

BRPLY

BSYNC

interrrupt

must

operation

deskew

input

AJ2

BSYNC

Ssynchronize —-- BSYNC L is asserted by
the bus master device to indicate that
it
has
placed
an
address
on
BDAL
<0:15> L. The transfer is in process
until BSYNC L is negated.

AK?2

BWTBT

Write/Byte —-- BWTBT L is used
ways to control a bus cycle:

two

It is asserted at the leading edge of
BSYNC
L
to
indicate
that
an
output
sequence is to follow (DATO or DATOB),
rather than an input sequence.
It
is asserted during BDOUT L,
in a
DATOB bus cycle, for byte addressing.
AL2

BIRQ4

Interrupt Request Priority Level 4 -A level 4 device asserts this signal
when
its
interrupt
enable
and
interrupt request flips-flops are set.
If
the
PS
word
bit
7
1is
0,
the
processor responds by acknowledging
the
request
by asserting
BDIN
L
and
BIAKO

Table
Bus

Mnemonics

AM2

BIAKI

AN?2

BIAKO

9-4

Bus

Identifiers

(Cont)

Description

Interrupt

with

Acknowledge

interrupt

asserts

BIAKO

interrupt.

protocol,
L

accordance

the

processor

acknowledge

The

bus

receipt
transmits

this
to
BIAKI
L
of
the
device
electrically closest to the processor.
This
device
accepts
the
interrupt
acknowledge under two conditions:
l.

The
device
requested
asserting BIRQ4L, and

the

device

interrupt
that
If

the

highest

request

the

bus

priority

bus

time.

these

device

has

the

conditions

asserts

are

BIAKO

not

met,

the

device
on
the
bus.
This
process
continues
in
a daisy-chain fashion
until
the
device
with
the
highest
interrupt
priority
receives
the
interrupt acknowledge signal.
AP2

BBS7

Bank

7
Select
-The
bus
master
asserts this
signal
to
reference
the
I/0
page
(including
that
portion of
the I/0 page reserved for nonexistent

memory). The

address in BDAL <0:12> L
when BBS7 L is asserted is the address
within the I/0O page.

AR2

BDMGI

AS2

BDMBO

Direct Memory Access Grant -- The Bus
arbitrator
asserts
this
signal
to
grant bus mastership to a
requesting
device,
according
to
bus
mastership
protocol,
The
signal
is passed
in a
daisy-chain
from
the
arbitrator
(as
BDMGO L) through the bus to BDMGI L of
the next priority device (electrically
closest
device
on
the
bus).
This
device accepts the grant only 1if
it
requested to be bus master
(by a BDMR
L).
If
not,
the
device
passes
the
grant
(asséerts
BDMGO
L)
to
the
next
device
on
the
bus.
This
process
continues until the requesting device
acknowledges the grant.

9-23

Table

Bus
AT2

Mnemonics
BINIT

9-4

(Cont)

Bus Pin Identifiers
Description

Initialize -- This signal is used for
system reset. All devices on the bus
initial
known,
a
to
return
to
are

to
reset
registers are
1i.e.,
state;
zero, and logic is reset to state 0.
completely
be
should
Exceptions

documented
engineering

programming
in
specifications for

and
the

device.
AU2

BDALO

AV?2

BDAL1

Data/Address Lines -- These two lines
are part of the 16-line data/address
data
and
address
which
over
bus
information are communicated. Address

information is first placed on the bus
same
The
by the bus master device.
device then either receives input data
from, or outputs data to the addressed
slave device or memory over the same

BA2

bus

lines.

Power

Normal

Vdc

system

power,

BB2

-12
Vv
power

-12

Power
-=12
Vdc
(optional)
for
devices
requiring
this

voltage.
BC2

Ground

GND

System

signal

ground

and

return.

+12

Data/Address Lines -- These 14 1lines
are part of the 1l6-line data/address
bus previously described.

BDAL2

BDAL3

BH2

BDAL4
BDALS
BDAL®6

BDAL7

BM2

BDALS

BN2

BDALY

BDAL12
BDAL13

BU2

BDAL14

BV2

BDAL15

BS2
BT2

BDAL1O

BDAL11

[

BP2
BR2

BK2
BL2

BJ2

BE2

BF2

e o

BD2

Power

+12

system

power.

APPENDIX

INSTRUCTION
INSTRUCTION

A
TIMING

TIMING

The following fetch and
transacting
with
local
when accessed.

execute times
devices
that

assume that the SBC-11/21 is
do not
require cycle slips

Destination

Execute

Fetch

and

Number

Instructions

Mode

Time

(usec)

Transactions

Microcycles

CLR(B),
INC(B),

Ccom(B),
DEC(B),

0
1

4,27

1
3

NEG (B),
ROL(B),
ASL(B),

ROR(B),
ASR(B),
SWAP,

2
3
4

4,27
5.49
4.88

3
4
3

7
9
8

ADC(B),

SBC(B),

Single

SXT,

Operand

MFPS,

XOR

TST (B)

MTPS

2.44

6.10

7.32

2.44

3.66

5.49

4,27

5
6

5.49

5.49
6.71

4.88

6.10

7.32

6.71

7.93

6
7

7.93
9.16

3
4

13
15

Time

1.83

3.05

BIS(B)

BIC(B),

MOV (B),

BIT(B),

6.10

Source

CMP(B),

Number

Double Operand
Instructions

SUB,

Source

ADD,

Bus

Mode

(usec)

Includes
Mode

Fetch

3.05

4,27

3.66

4.88

6.10

CMP(B),

and

3.66
3.05
4.27
4.27
5.49

1.83
3.05
2.44
3.66
3.66
4.88

Fetch

Destination
Mode
N
B W
-

Subroutine
Instructions

SNV
DWW N

JMP

JSR

Time

SOB

3.05
3.66
3.66

3.66
4.27

4.27
5.49

5.49
6.10
6.10
6.10

Trap
Interrupt

7.90

3.66

Instructions

Destination
Mode

Time

BR,

2.44

BNE,
BMI,

BEOQ,
BVC,

10
10

6.71
6.71

Fetch

Branch,

BPL,

(usec)

4,27

RTS

and

Execute

\S)

Jump

BIT(B)

2.44

O~I~J
UV
-

BIS (B)

2.44

BIC(B),

BIT(B),

AN
DUV W W

0.61
1.83

CMP(B),

SUB

OdJoaaoowm

NOoOnDs WO

0.61

ADD,

(usec)
S WWNWNNDO

MOV (B),

Time

WNNFNNF
O

Mode

S Wwwdhwhn

Destination
Mode

N AUNMHWN
O

Destination

Double Operand
Instructions

and

Execute

(usec)

BVS,

BCC,

BGE,

BLT,

BCS,
BGT,

BLE,

BHI,

BLOS,

BHIS,

BLO

EMT, TRAP

9.77

RTI

4,88

RTT

6.71

Miscellaneous
and Condition
Code
Instructions

Destination
Mode

Fetch and
Execute
Time (usec)

HALT

8.54

WAIT

2.44

RESET

22.28

NOP

3.66

3.05

BPT,

IOT

cLc,

CLv,

CLZ,

CLN,

CCC,

SEC,

SEV,

SEZ,

SEN,

then

loop

SCC
MFPT

The
measure
of
LSI-11
BUS
interrupt
latency
is
the
time
from
assertion of BIRQ until
BIAKI
1is
accepted
by
the
interrupting
device electrically closest to the processor on the LSI-11 BUS.
The

measure

local

interrupt

latency

the

time

from

assertion

of the request until the time the microprocessor is ready to fetch
the first instruction in the interrupt service routine.
This time
is primarily comprised of the time to perform two pushes and a PC

and

PSW

restore,

DMA

latency

known

the

period

time

between

asserting
its BDMR and
receiving BDMGI when
it
LSI-11
BUS
as
the
electrically
closest
DMA
processor.

Interrupt

Latency:

LOCAL

LSI-11

BUS

23.2

usec

9.3

usec

device

resides on
device
to

the
the

NOTE

Assume
reside

that

the

stack

the

LSI-11

BUS

device

vector

within

IAKI.

The

and

SBC-11/21
can

600

nsec

service

vector

memory

and

that

assert

BRPLY

after

1latency

the

and
receiving

(time

from

BIRQ until
the
time
the microprocessor
is ready to fetch the first instruction

in
the
depends

interrupt
service
routine)
on
the
response
time
of
the
interrupting device i.e., RDIN to TRPLY
and negation of TRPLY.

DMA

latency:

WAIT

1.3

instruction

usec

latencies:

internal

vector

11.8

external

vector

12.4

usec

5.06

usec

DMA

usec

minimum

11.0

usec

maximum

APPENDIX

PROGRAMMING
DIFFERENCE

comparison

SBC-11/21

Activity
%R,

(R)+

OPR

%R,-(R)

between

LSI-11/2

source

operand.

OPR %R, @(R)+ or OPR %R,@-(R)
using the same register as both

source and destination: contents
of R are incremented (decremented) by 2 before being used as
the source operand.
In

the

above

contents
source

OPR

PC,

PC,@A;

X(R);

used

OPR

contain

the

(R)+

JSR

new

PC.

JMP

case,

contents

JSR

Four local
exist.

Four LSI-11
exist.

Initial

interrupt

levels

the

traps

exists.
interrupt

interrupt

overflow not

stack

OPR +

reg,%R

bus

LSI-11

(BR4)

used

Only

one

OPR

reg,(R)+:

are

location

instruction).

Stack

the

Location

(illegal

level

initial
as

PC,@X(R);

PC,A:

the

In the above
will contain
JMP

cases,

are

operand.

OPR

will

two
R

overflow

levels

implemented.

trap

exists.

the

LSI-11/23

using the same register as both
source and destination: contents
of R are incremented (decremented) by 2 before being used as
the

LIST

The
following
table
presents
a
consise
SBC-11/21, LSI-11/2, and LSI-11/2 3.

OPR

DIFFERENCE

X
X

The

first
interrupt

executed
occurs

level

instruction

in an
will not be
another interrupt

routine
if

at a higher
than assumed

priority
by the first

interrupt.
Eight
PSW

general

address,

177776,

implemented.
MFPS

purpose

Must

registers.
not

use

MTPS

and

instructions.

Only

implicit

RTT,

traps

load T
T bit.

references

and

bit.

(RTI,

interrupts)

Console

can

cannot

load

If an interrupt occurs during an
instruction that has the T bit
set,

the

ledged

bit

before

trap
the

RTI sets the
is acknowledged
following RTI.

RTT

trap

sets

occurs

acknow-

bit, T bit
immediately

following
RESET

usec

the

after

bit,
the

out

the

trap

bit

instruction

RTT.

instruction

interrupt.

T bit trap will sequence
WAIT instruction.
If

INIT

consists

followed

usec

pause,
Power fail not
recognized until the instruction

complete.

RESET
usec

instruction
of

INIT

followed

3.2 msec pause.
recognized until

is
Odd

consists

Power

the

a minimum
fail not

instruction

complete.
address

not

references

using

the

trap.

Non-existent

address

references

using the
address.

trap

the

restart

MOVB

instruction does

(DATIP)

and

sequence

a WRITE

for

last

READ

(DATO)

memory

bus

cycle.

MOV instruction does a WRITE
(DATO) bus sequence for the last
memory

MOV

cycle.

instruction does

READ

(DATI) and a WRITE (DATO) bus
sequence for last memory cycle.
From

Through

Response

210

217

Trap

11/21

11/2

NOTE

11/23
1

Reserved

Instr.

210

227

Trap

Reserved

Instr.

70000

73777

Trap

NOTE

Extended
Instr.

75000

75037

Trap

75040

75777

Trap

NOTE

Set

Floating
point
Reserved

Instr.

170000

177777

Trap

NOTE

Reserved
Instr.

NOTE

1l:

Maintenance

NOTE

Response

depends

and

SXT

READ

CLR(B)
and
the

instructions
on

processor

(DATI)

a WRITE (DATO) sequence
last bus cycle.

for

CLR(B)

and

and SXT do a READ (DATI)
a WRITE (DATO) bus sequence

for

the

last

bus

cycle.

CLR(B) and SXT do a WRITE
bus sequence for the last

(DATO)
bus

cycle.

MARK

instruction.

SOB,

RTT,

SWAB

clears

ASH,

ASHC,

DIV,

SXT,

XOR

MUL

instructions.

B-3

options

Register addresses (177700177717) are handled as regular
memory addresses.
No internal
registers are addressable from
either the bus or the console.
Register addresses (177000177717) time-out when used as
program

address

contains

memory

address

CPU.

non-existent

and

occurs, PC will
incremented.

the

bus

have

error

been

If register contains a
non-existent memory address in
mode 2 and a bus error occurs,
register will be incremented.

If register contains an odd value
in mode 2 and a bus error occurs,
register will be incremented.

HALT

user

mode

HALT instruction
PSW on the stack
with 340 and the
restart address.
Only power-up
Resident

ODT

traps

10.

pushes PC and
and loads the
PC with the

mode

X
PS

implemented.

microcode,

Instruction

execution

completion

regardless

runs to
bus

error.

BEVNT
Bus

line

error

address.

interrupt
traps

error

before

during

level

restart

Instruction

completion

Bus

runs

X
X

trap.

IAK

vectors

through 0 and traps to restart
address. The first instruction
of service routine is guaranteed
to

execute,

Only sixteen-bit
supported.

addressing

The no-BSACK
implemented.
BDMGO

18 usec time-out
1If time-out occurs

aborted.

Bus halt line is a jumperconfigured nonmaskable interrupt.
Acknowledgement causes PC and
PSW to be stacked and the
processor vectors thru level 7
internal vector 140.
Vector

address accepted only on
BDAL<K7-2>, This limits vector
address

space

374.

Certain vector addresses are
reserved for "local" devices
other

than

BEVNT.

SBC-11/21
Priority
of
DMA,
system
interrupts, HALT trap, and

Priorities

traps ,
WAIT:

external

DMA

HALT trap (timeout
Power Fail Trap

WAIT

Interrupt

instruction

1internal

(highest

priority)

request)

Traps (illegal instruction,
Internal Interrupt Request
External

interrupts,

bit,

Request

(lowest

priority)

APPENDIX

SOFTWARE

DEVELOPMENT

c.0
GENERAL
This section of the manual presents programming hints which may be
helpful to application programmers in gaining familiarity with the
SBC-11/21.
The following three topics are discussed:

Running

stand-alone programs
The software development process
An application example

o
o
A

method

creating,

briefly

explained.

software

development

board
computer,.
practical example

SBC-11/21.
simple, but
greater

This

and

1is

running

followed

process,

complexity.

The

prove

PSW value
transfer

an operating system, on a
image
can
then
be
loaded
option is required to load

used

address

applies

single

ROM

based

the

presents
a
run on the

program

quite

has

been

rewarding

thoroughly

the

first

RUNNING STAND-ALONE PROGRAMS
can develop stand-alone programs,

requiring
The
.SAV
Macro-ODT
To

discussion

The
output
chosen
for
the program
is deliberately
the methodology is applicable to programs with a much

degree

user

programs

The
1last
section of
this
appendix
of a
real-time program written to

tested and studying it should
time users of the SBC-11/21.
c.1
The

stand-alone

with

Macro-0ODT,

Macro-ODT

BREAK

the

stand-alone

service

300

location

control

Macro-ODT

that
is programs not
separate RT-11 based system.
into
the
SBC-11/21
and
run.
the program and to run it.

142.
when

routine

This

will

the

BREAK

program
in

must

location

have
140

enable

the

key

depressed.

the

and

program

a
to

In order to be able to load the stand-alone program from the mass
storage device into the SBC-11/21, the device's boot block must be
modified.
This modification extends to locations 0,
2, 4 and 6.

Location 0 normally contains 240 and must be changed to 260.
When
the
device
is
booted,
this
tells
the
Macro-ODT
that
the mass
storage device
contains
a
stand-alone
program.
Macro-ODT will
then interpret the contents of locations 2, 4 and 6 as a RADIX-50
encoded six character file name, and search the directory of the
volume
for
that
file.
The
volume
must
have
the
RT-11
file

structure.
When the file is found, the entire file is loaded into
contiguous memory starting at location zero.
Then Macro-ODT loads
register RO with the number of the unit or drive, and register Rl
with

the

CSR

address

the

booted

device.

This information may be of interest to the stand-alone program if
it uses overlays.
Then the Stack Pointer (SP) is loaded with the
contents of location 42, the Program Counter
(PC)
is loaded with
the contents of location 40, and the program begins execution.
Please
note,
that
a
stand-alone
program
developed
on
an
RT-11

C-1

based system will already have the correct values for PC and SP in
locations

and

42.

The detailed procedure for performing these modifications in the
boot block and the stand-alone program will now be outlined.
This
will be done on an RT-11 based system using the SIPP utility.

In the examples below, the program that is to be loaded and run
from the stand-alone volume is named FOOBAR.SAV and resides on DK.
The characters entered by the operator are underlined. "<CR>" is a
carriage return and not the four characters "<", "C", "R" and ">".

The
key
The

""C" and ""Y" symbols are obtained by holding down the "CTRL"
and typing "C" or "Y" respectively before releasing "CTRL".
"XXXXXX"
is a string of octal digits whose value can be

anything

but

First modify

not

the

relevant

stand-alone

the

process.

program:

;Run the SIPP utility

R SIPP <CR>

* DK:FOOBAR.SAV <CR>

;Name of file to be

Base?

;Defaults

patched

<CR>

Offset?

140

Base

Offset

01d

New?

000000

000140

xxxxxx

170000

000000

000142

xxxxxXx

300

000000

000144

xxxxxx

<CR>

*"C

;load address of Break
;routine at Break vector

; PSW during
;Exit

NOTE

If
you
are
wusing
vyour
own
BREAK
intercepting routine, put its address at
location
140
in
place
of
the
value
170000.

the

SIPP

*DK:/A
Base?

bootblock:

<CR>

Offset?

<CR>

Break

patching

;Exit SIPP

Now modify

zero

routine

Base

Offset

01d

New?

000000

=xxxxxx

000260

000000

000002

=xxxxxx

;RFOO

<CR>

000000

000004

=xxxxxX

;RBAR

<CR>

000000

000006

xxxxxx

;RSAV

<CR>

000000

000010

=xxxxxx

“Y

<CR>

*°C
C.2

THE

SOFTWARE

DEVELOPMENT

PROCESS

Software
development
for
the
SBC-11/21
consisting of four distinct steps as shown
1.

Design

Enter,
edit
application.

Build

the

application

Load

the

program

the

software

application
debugging of
C.2.1

Design

the

and

code

assemble

into

the

can
be
thought
in Figure C-1.
source

tasks

runable

that

memory

step

tasks.

SBC-11/21

program.
This
the application.

and

will

make

the

image.

execute

the

involve

the

Software

An important consideration in the design of application software
is the run-time memory configuration.
Since the SBC-11/21 is a
ROM/RAM system, the location of the ROM/RAM boundaries must be
defined.
All
instructions
and
constants
must
be
grouped
separately for location in the ROM portion of memory.
Variable
information must
be
grouped
together
for
1location
in
the
RAM
portion

memory.

Throughout

the

development

process,

the

segregation of ROM and RAM
information must be maintained.
MACRO-11 Language Reference Manual describes methods of data and
code

separation.

C.2.2
Editing
The second step

and Assembly
in the development

cycle

the

entry,

editing,

and assembly of the application software.
To enter and create the
application software
involves the
use
of
an
editor
on
the
development system.
Once the application software is entered and
the designer is satisfied with the contents, it can be saved on a
mass storage device.
The assembler must then be used to convert
the source code instructions into executable code.
The result of
the assembly process is an object file.
The assembler detects common
issues appropriate warnings.

should

made

re-editing

assembly language coding errors and
If errors are detected, corrections

the

C-3

source

and

assembling

again.

START

UNDERSTAND PROCESS
TO BE INTERFACED
WITH, DO TASK DESIGN

!
CREATE THE SOURCE
CODE FILE WITH AN
EDITOR

|
ASSEMBLE THE
SOURCE CODE

CORRECT

YES

__~ASSEMBLY
ERRORS

ERROR-FREE
OBJECT CODE

!
BUILD THE
APPLICATION
PROGRAM

YES

BUILD

ERRORS

LOAD RUN-TIME IMAGE

!
EXCUTE APPLICATION

EXPECTED
RESULTS

DEBUG

COMPLETED
MR-7201

Figure

C-1

Overview of

Software Development

Once

the

object

application

form,

software

ready

for

has

the

been

translated

Process
the development

cycle

create

memory

The

build

the

application

runable

linking of the tasks
single memory image.
or

modules

and

image.

that

make

The

building

assigns

the

process

absolute

into

step.

C.2.3
Building
The third step in
a

error-free

building

process

takes

memory

process

involves

software

object

references

to
the

into

module
to

the

information contained in the object code.
The user assigns these
locations by the
sectioning
of
the code
that
took place during
design.
The result of the build phase is an executable run-time
memory

image

that

can

now

loaded

and

tested.

C.2.4
Running and Debugging the Program
The fourth step in the development cycle
is the
loading of
the
runable memory image into the SBC-11/21.
Once loaded, the program
can be run and debugged.
There are three techniques that can be
employed to transfer the software to the target.
The methods are:

ROM
transfer.
This
method
involves
the
programming
of
ROMS
via
a
PROM
blasting
utility,
such
as
PB-11,
and
placing
the PROMS
into
the
target configuration.
This
simple loading technique most closely resembles the final
target configuration since actual ROM storage is used.

Media

transfer.
When
this
method
1is
used,
the
application program is loaded, in stand-alone form, into
the target from a mass storage system.
The directions on
creating a stand-alone bootable program are provided
in
the
first
part
of
this
appendix.
The
target
configuration uses LSI-11 bus RAM memory in place of the
SBC-11/21 on-board ROM during initial start-up and debug.
The
SBC-11/21
configuration
must
contain
the
Macro-0DT

ROMs

described

means

Chapter

the

The

application

ODT

ROMs

program

provide

and

are

the
used

during program debug.
Media transfer does not reflect
the
final
configuration,
but
execution
from
RAM
makes
debugging and testing easier.
The speed of the program
in this mode is approximately half that of the ROM based
system,

Down-line
of

the

controller

This

method

software

from

the

allows

development

transfer
system

to
target system via a serial communication 1ink.
The
down-line
loader must be
a development system utility.
The target configuration is similar to the media transfer
configuration.
In addition to the LSI-11 bus, RAM, and
the Macro-ODT ROMs one of the
serial
I/O
1lines on the
SBC-11/21 must be dedicated to the communication with the
development system.
the

When

the desired loading technique is implemented, the final phase
development is to debug and run. The loading technique employed

C-5

dictates the approach that will be taken during debug.

If the application is being loaded via the ROM transfer method,
When ROM transfer is
initial testing and debugging is difficult.
used there must be embedded code in the application that will
Another way
report the state of the control system periodically.
to check the system is to observe changes that occur in the
If errors are found, correction requires a
external devices.
complete

debugging

When

the

testing

reprogramming
can

quite

application

debugging

and

PROMs.

the

This

type

testing

and

cumbersome.

loaded

becomes

via

easier

media
than

transfer,

the

ROM

the

method.

1inital

Once

the application program is loaded into LSI-11 bus RAM or into
The
on-board RAM, it can be run using the features of Macro-ODT.
the
in
halts
periodic
and
designer can also embed reporting tasks
should
It
system.
the
of
state
application to examine the current
be noted that executing out of LSI-11 bus RAM during debug will be

approximately twice as slow as running out of the SBC-11/21
on-board memory. If errors are found minor modifications can be
made in the application code since testing is being done in RAM.
This eliminates the loop of making new run-time memory images for

Once the target system is running successfully,
every change.
tasks integrated, the run-time configuration can
the
with all of
step is to commit the application program to
last
The
be set-up.
ROM and run

c.3

in the SBC-11/21.

AN APPLICATION EXAMPLE

This is a sample application (Figure C-2) to show the development

of a controller program using MACRO-11. The sample program will
simply light the LED used by Port C of the SBC-11/21. The LED will

light for ten seconds whenever an input is detected on the console

port

(SLUl).

The controller program for this simple system 1is best served by
An interrupt service
using an interrupt driven environment.
When an input is
port.
routine is used to monitor the console
timer for ten
the
received, a routine is entered that will set

seconds and light the LED. A second interrupt service routine is
used to count up to ten seconds and then turn off the LED. This

1In addition to the
routine is serviced by the BEVNT interrupts.
application tasks, there are tasks to initialize the input/output
Also there are diagnostic programs
devices and data structures.
for the SBC-11/21 and programs used to handle any exceptions. The
controller
integrated

program

developed

individual

into a complete final program,

tasks

and

then

The monitor program is described by Figure C-3 and consists of
Power Up programs, Diagnostic programs, Task programs and
The Power Up programs consist of POWRUP and
Exception programs.
The Diagnostic programs
RECOVR which 1is initiated by POWRUP.

START

POWER-UP ROUTINE
IS THIS RECOVERY FROM A POWER FAILUR

E (POWRUP)

lNO

INITIALIZE THE DATA STRUCTURES FOR
DIAGNOSTICS (DIAG)

YES

PERFORM DIAGNOSTICS (DIAG)

TEST SBC-11
S10, PIO, /21
RAM, ROM

RESTORE STATUS
PRIOR TO THE POWER FAIL

ANY ERRORS

(RECOVR)

————4

REPORT TO OPERATOR,
GO INTO INFINITE LOOP

INITIALIZE THE DATA STRUCTURES (START
)
FOR CONTROL/MONITOR TASKS

ENABLE INTERRUPTS (START)

—e WAIT FOR INPUTS (STA
RT)

REC OR BREAK

TIMER

HANDLE EXCEPTIONS

INTERRUPT TASK NO. 1

INTERRUPT TASK NO. 2

VIA CONSOLE SLU INPUTS

BY BEVNT INTERRUPT

ENTERED BY AN INPUT RECEIVED

POWER FAIL (POWERF)

ENTERED EVERY 1/60 OF A SECOND

DO THE FOLLOWING:

BUS ERRORS (RESTRT)

DO THE FOLLOWING:

1. SET TIMER FOR TEN SECONDS

1. TICK OFF TIME IF THE TIMER

2. LIGHT THE LED

IS SET TO GREATE
THAN R
0,

2. IF TIME EXPIRE
TURN OFF
S

THE LED

MR-7200

Figure
consist

C-2

Application

SLUTST, PIOTST, RAMTST
of TIMER,
REC and BREAK.
POWERF,
RESTRT
and
PRINT.

consist
of

constants

and

variable

data

RAM

memory.

ROM

instruction

for

socket

are

application

Map

set

and

data

Map

Figure

The

assigned

Cc.3.1

Power

code

controller

and

ROMTST.

The

Exception

All

these

located

and

assumed

Load

160000.

The

the

Memory

data

Overview

the

The

programs
the

stack

(Table

shows

data.

ROM

are

2-8),

battery-backed

C-4

Task

actual

programs

consist

with

the

memory.

The

located

the

with

the

RAM

starting

memory

program

at
locations

Up Programs

program begins when
the
system power
1is applied.
microprocessor
accesses
location
2zero
which
1is
the
jumper-configured start address.
This location contains a jump to
the
power
up
routine
POWRUP
(see
Figure
C-5).
This
routine
determines if this is a normal
power up or a recovery from a
power
The

failure.

the

RAM

This

memory.

recovering

from

RECOVR

program

conditions

the

program

Program

determined

the
power

(see

Diagnostic

executed

programs.

fail

Figure

that

execution.

flag

checking

set

condition

C-6).This

existed

Prior

the

flag

and

then

the

POWER

the

not

that

program

Program

the

c-7

the

indicate

flags

the

system

jumps

restores

power

set,

FAIL

program

fail

the

and

the

system

resumes

initial

power

branches

the

«TITLE FALCON DEVELOPMENT EXAMPLE
+ENARL

+.GLOBL

POWER1,POWER2,ERROR,STACK,RESTRT

+GLOBL

POWERF,BREAK,REC, TLMER,RECOVR,S5LUTST,PIOTST,RAMTST,ROMNTST

§ This is an example of a simple controller application for the KXT11=AA,
'-

«SBTTL
e

Program gection definitions

Define the three program sections that will be used

’-

000000
000000

+ASECT
+PSECT

ROM

3 Assign absolute memory locations
¢ For insructions and constant data

000000

«PEECT

RAM,D

7} To define all RAM locations

+SATTL

Equates

that will be stored in rom memory

3 Constant definitions
,-

176540

RCSR1

=z 176540

3 Auxiliary SLU addresses

SLU addresses

000052

CONBR

RCSRC

sz 177560

$ Console

176200
176206
000261
000017

PPA
PCW
LEDON
LEDOFF

ez 176200
ez 176206
=z 461
=x 17

3
3
¢
;7

160010
167776

RAMBGN
RAMTIOP

== 160010
== 1677176

?} Bottom of the user RAM
3 Top of the user RAM

106016

csUm

zz 106016

7 Checksum value for the system tasks

«SB8TIL

HMacro definitions

177560

¢ Proaorammable baud rate mask (9600)

ex 52

Parallel port A
Parallel control word
Parallel C8wWw to light the LED
Parallel CS¥ to turn otf the LED

14+

; Define macros that will be used by the application
,-

+MACRD
KOV

PUSH ARG
ARG,~(SP)

§ stack push operation
1 move the argument onto the stack

+MACKO
MOV

PUP ARG
(8P)+,ARG

$ stack pop operation
: move the argument from the stack

+ENDM

«SBTTL
e

Entry

points

Define entry point, interrupt, and trap service routine addresses

’-

+ASECT

000000

000000
000000
000004
000024

000060

000100

000140

000167
000167

N 1]

000000°
000000G

000024
000000G 000340

« 224

000060

+ =60

000100

+2100

000140

«%340

000000G 000300

000000G 000300
000000G 000300

000000

JMP
JMP

POMRUP
RESTRT

$ Jump to the power«-up routine
§ Jump to the restart routine

«WORD

PUWERF ,340

Power

« RORD

REC, 300

Console receiver service routine

+WURD

TIHKER,300

Timer service routine

«WORD

BREAK, 300

3§

Console break service routine

+EBTTL
«FSECT

Power
ROM

fall

service routine

routine

POWRUPSS

000000

I X]

3 Come here f£irst under all circumstances and decide if this 18 a normal
{

000000G 135724

BNE
CHP
BNE

POwEK1,#123456

000016

001006
026727
001002

DIAG
POWER2,#135724
D1AG

3
3
$
7

1Is this recovery from
power failure
or is it a normal power=-up ?
Increase the chance to distinquish
by checking against a 32 bit pattern

000020

000167

0000006

JMP

RECOVR

This a recovery from power

000000

000006
000010

026727

power up or recovery from a power fail

000000G 123456

Figure

CHpP

C-3

Monitor

Program

fail

+SBTTL Diagnostics
000024

DIAGs:
I 4

¢#

the

system

diagnostics

004767
000174°

000074

004767

004707
004767
004767

0000006
0000006
000000G
0000006

000070

005767

0000006

000074
000076

T8T

001404
004767

000040

000102
000104
000106

000332°
000777
004767

CALL

000112

000253°

177564

DIAUM
RAMTST
ROMTST
SLUTST

CALL
CALL

PrOTST

ERROUR
18
PHINT

BLQ

000030

183

117

Tell the operator that the power=
up diagnostics are running
Perform the KXT11i RAM memory test
Pertorm the KXTii ROM memory test
Perform the KXT11 serial line test
Perform the KXT11 parallel 1/0 test

+«WURD
BR

EMESS

CALL
«WORD

PRINT
HMESS

«SBTTL

Initlalization

the
the
the

stack
error flag
console SLU

Is the error flag zero
Yes, no errors proceed
No,

diagnostic

init

faflure

Walt

until there is operator action
Indicate that things are OK

ana

completion,

move

allow

appiication

tasks

run

STARTS
¢

a0uvL14

i1y
120

FE]

{

121
122
123

This

the

start of

the main body of

the

application

126 0004 36

004767
004015°

177560

PERCSKC+2
#100,90RCSRC

1518
Bl1S
MTPS
CALL
+WORD

177562
000300
000000
000004

0
PRINT
GO

108737
052737
106427

000114
000420
124 000126
12% 000132

118

CALL
«WORD
CALL
CALL

1nitialize
Initialize
1nitialize

0527317

#5TACK,
8P
ERROK
#CUNBK,@#RCSRC+4

MOV
CLR
BIS

we we e

000042
000046
000050
000054
000060
0vov6s

005067

000000G
0000006
000052

012706

000024
000030
000034

.. W We Ve W we

Flush the receiver buffer
Enable interrupt on the receiver
Allow interrupts to happen
Tell the operator that the
application is up and running

127

146
147

017604
005216

000000

005216

1s:

112405
001406
105737
100375

110537
000770

28¢

177564

177566
3s:

015
015
015
015

000445

01s

012
012
012
012
012

159
160

000517
000571
000613
000650

018
015
015

161

000701

155 000412
156
157
158

162 000736
163 001015
164 001061
165
166
161

the actual

015
015
018
018
0490

RETURN

@#RCSRC+4
24

RS, 8#RCSRC+6

LSe

«SBTTL
«NLIST

BEX

DIAGMIS

ASCIZ

HHESES3::

.ASCl1Z

040

EMESSS:

.ASCIZ

012

007
040
040

012

040

PMESSSE ASC1Z
SLUEs:
.ASCLZ
SLGOOLS
s . ASCIZ
MESRAL113.,ASCIZ

012
012
012

040
040

012

040
040

RAGUODS
3 .ASC12Z
MESRU1t3.ASC1Z
ROGOOD$
3 .ASC1Z
PGOOULS: .ASClZ
GOt
+ASCIL

V40

«ASCIZ

040

sp)

(8P)
(:4)+.a5

+DSABL

040
040

012
040

LSB
#(8P),R4

000207

148
149

150
151
152 000174
153 000253
154 000332

+ENABL
MOV
INC
INC
MOVH
BEQ
TS1B
BPL
MOVB

Ve W

000170

145 000172

subroutine prints

144

143 000164

This

142

000156
000162

for

interrupts

messages

’-

Ve W

141

139
140 000454

000146
000150
000152

wait

[A4

137
130

and

PRINT:S

000142

132
i33
133
138
136 000142

S8it

131

000777

128 000140
129
130

Messages

sent

Point to the beginning of the message
Increment beyond message address in the
calling routine
Hove the next character to be printed

Is
No,

this

the end of

output

another

the

back

operator

<i5><12>/ The power=-up diagnostics are running ... 7<15><12>
<15><12>/ System checked out, there were no faults /<15><i2>
<15><12>/ System did not pass initial power up test /<15><12>
<1521 25<T>€T><T1><71>/
<15><12>/ Serial line

RUNTLIMKE FALLURE /<18><12>
unit dlagnostic failure /<15><12>

<15><12>/ Serlal line unit passed diagnostics
<15><12>/ RAM fallure /<15><12>
<15><12>/
<15><12>/
<15»<12>/

RAM
ROM
RUM

C-3

/<15><12>

passed diagnostics /<15><12>
checksum error /<15><12>
passed diagnostics /<15><12>

<15><12>? Parallel input/output passed diagnostics 7<135><1i2>
<§15><12>/ Tne application 1ls running ... /7 <15><12>
/
Type any key to light the KXTi1i1=-AA LED for

+END

Figure

Get ‘another character

<EVEN

0000014

message marker
character

Transmitter ready
Output the character

Monitor

Program

(Cont)

secs./

RT=11 LINK
«SAV
C
Section
«

ABS,

VU06,01C
Title:

Tue 06=-0Oct=81 09:02:01
/R3000400
Global

Addr

8ize

.Global

000000

000400

(R¥W,1,GBL,ABS,0VR)
LEDOFF
000017
CUNbBR
CSUM
106016
RAMBGN
PPA
176200
PCH
RCSRC
177560

RUOM

000400 157400

RAM

160000 000332

Transfer

Load Map
ldent:?
FALCUN

Value

Global

Value

000052
160010
176206

LEDON
RAMTUP
RCSR}

000261
167776
176540

PUOWRUP
000400
DIAG
PRINY
000542
DIAGHM
EMESS
000732
FMESS
SLGUOD
001117
MESRAL
MESRO1
001250
ROGOUD
GO
001415
RECOVR
TIMER
001656
DREAK
PUWERF
001720
RESTKT
RAMTST
002132
ROMTIST
(RW,D,LCL,REL,CUN)

000424
000574
001012
001171
001301
001556
001702
001764
002212

BSTART
HMESS
SLUE
RAGUOD
PGOUD
REC
ULAST
SLUTST
PIUTST

000514
000053
001045
001213
001336
001634
001716
0011774
002262

ERROR

160012

160020

SAVER6

160014

(RW,I,LCL,REL,CON)

POWER]

address = 000001,

High

160010

POWER2

limit =

160330 =

28760,

Load

Map

160016

STACK

160332

words

LC
RAM,D

The varjiable data

TIME

C-4

+ENABL
«PSECT

000000

s assigned

the user

RAM

space on

the

KXT11<«AA

000000

we
wo
W
wo

+WORD
oBLHKW

oo.

000000
000000

TIME::

oBLKW
POWER1
13 .WORD
POWER2:
3 ,WORD
SBAVERG63
2 ., WORD

000000
000000

«WORD

[-N-R-N-3N

000332

000020
000022

ERRURS
S

-Cc

SR VOl S CUXms

000000
000010
0000412
000014
000v16

-~ [

Non

existant

Power

KXTil=-AA

gfallure

Time
This

flag
is the

memory

32-bit comparision

flag
Stack pointer area for
Diagnostic error flag

power

faflure

stack

S8TACK3
S

«END

000001

Figure

C-5

«ENABL

+«GLUBL
«MCALL
+PSECT

000000

Power Up Task

SAVERG6,IIME,RCERC,CONBR,LEDUN,PCWH
POP
ROM

RECOVR3:

000000

1This routine is entered if a recovery from a power fajlure is taking place
§= Entered Prom POWRUP
000004
000010

LJ4]4

SP
SAVERG,
TINE
RS

$
¢

Restore the
Restore

stack pointer
any variable information

POP

Restore

general

000012

0]4

registers

000014
000016
000020
000022
000024
000032
000040
000044
0000406

POP

052737

000100

0000006

POP
POP
Bls

R3
R2
R1

000000G 0000046

BIS

005767
001403

0000006

T8T
BEQ

Re=initialize console SLU, enable
interrupts and set=-up baud rate
Is the LED timer set
No, continue
Yes turn the LED on for the rest

000054

000002

3
¢
3
3
?
$
$
}

000000

016706

MOV

0000006

POP

052731
012737

000000G

MOV

0000006
is:

#100,@#RCSKC
, @#¥RCSRC+4
#CONBR

TINE

3s
@ #PCH
#LEDON,

RTIL

000001

Figure

C-6

Power

Fail

the

purpose

of the time prior to power=-fail
Return from point of power=-fall
interrupt

«END

@]
|

[ N [

Figure

VXN
T
N -

Value

Recovery

C.3.2
Diagnostic Programs
The
diagnostic
programs
initialization routine.
The

are

entered

SLUTST

(see

via

Figure

diagnostic

C-7)

program

1is

the first diagnostic and
it tests the auxiliary Serial Line Unit
on the SBC-11/21.
The diagnostic enables the SLU maintenance mode
and
transmits various
test patterns.
After
a
certain
amount of

time

the

correctly

program

checks

received.

mode
allows
data
to
through the internal
to

the

port

The

second

RAM

memory.

RAM

location

that

will

and
location.

see

that

the

test

noted

that

the

be
transmitted
to
the
loopback.
Therefore if
respond

diagnostic
This

should

test

then

this

RAMTST

checking

1
2
3 000000

that

were

maintenance

EIA port
as well
as
a device is connected

data.

(see

performed

patterns
SLU

Figure

C-8)
which tests the
known data
into a

writing

the

correct

«ENABL
+GLOBL
+PSECT

LC,LSB
RCSR1,ERROR,PRINT,SLUE,SLGOOD
ROM

routine

checks

MOV
TSTB.
MOV

$RCSR1,R1
2(RY)
#6,4(KRY)
_
f8,,R2
#PATERN,R3

information

5
6

000000

SLUTSTs?
2

’-

1his

the

auxiliary

SLU

port

the

KXTii=AA

10
11

12
13
14
15
16
17
19
19
20

000000
000004

012701
105761

000000G
000002

000016
000022
000026
000030
000034
000036
000040

012702
032703
005005
105761
400402
077504
000422

000010
000132°

000004

i8¢
2¢;
s:

21
22

000042
000046

111364
005005

000006

24 000052
25 000054
26 000056

100402
077503
000413

000064

29 000066
30 000070

000010

23 000050

27 000060

012761

000004

$
$}

Point

the

address

Flush the contents of RBUF
Set the SLU for maintenance and
programmable baud rates
Initialize the baud rate counter
Point to the test patterns
Initialize time out counter
Loop the pattern around
Branch 1f ready to send
If not ready, bump time out counter
IF timed out then = ERROR =

MOV
MOV
CLR
8T8
BMI
SOB
BR

48
RS, 38
1008

3
?}
$
3
$
¢
¢
¢t
3

MOVB
CLR

(R3),6(R1)
RS

$
$

Send the information out
Initialize the time out counter

BML
soB
BR

68
R5,5%
8

3
;7
3

Yes it 15 and branch
1f not ready, bump time out counter
If timed out then =-ERROR=~

001010

BNE

1008

NOo

105723
001356

518
BNE

(R3)+
a9

$}
§

All
No,

of the test paterns done
go do another pattern

All

105711

126113

000072

005302

000074

001412

000076

062761

334
35

000104

000746

36 000106
37 000112

005267
004767

000116

000000G

000122

004767

000126

0000006

000130

000207

0001232

177

39 000120

000006

000403

583

000002

6812

)
000010

000004

TSTB

cHps

RS
4(R1)

{R1)

2(R1),(R))

1s the receiver ready 17

was the information sent OK ?
it

was

not

DEC

BEQ

2008

Yes,

get

ADD

#10,4(RY)

NO,

set-up

the

another

=ERROR~

baud

out

the

rates

tested

this

routine

000000G
000000G

1008

INC
CALL

ERROR
PRINT

3
3

Bump the error counter
Print the error message

«WORD

SLUE

0000006

2008

CALL

Go back

1508

RETURN

Bye

PATERN:

.BYTE
+EVEN

177,40,0

Test

.DSABL

LSB

« WORD

1508

The

test

loop,

baud

was

reinit

successful

S8LGOOD

44
45
46
47
48

0090013

040

000

+END

Figure C-7

SLU

Diagnostic

patterns

Task

for

SLU

rate

patterns

1
2
3

000000

«ENABL
«GLOBL

LC,LsB
RAMBGN,PRINT,RAMTOP,MESRA1,RAGOOD,ERROR

+PSECT

ROM

$
)
7

000000

RAMTST3
3+
¢
This routine

]

checks

the

user

RAM

the

KXT1i=AA

MOV

(sP),R2

Save

the

return

000002

016703

0000006

MOV

ERRUR,RI

)

Save

the

contents

000000
000006

011602
012700

000000G

MOV

SRAMBGN,RO

Point

13
14
15

the address

ovo0i2

010010

000014
000016

020010
Q001405

000020

004767

000024

00000V0G

19
20
21

000026
000030
000032
22 000034
23 000040
24 000042
25 000046

000000G

005203
000407
005720
020027
000002G
103764
004767
000000G
0000006

28t

the

address

start

the ERRUR

the

user

MOV

RO, (RO)

Write

CHP
BEQ

RO, (RO)
24

!
3

Read it
was the

CALL

No,

+WORD

MESRAL

INC
BR
TST

R3
33
(RO)+
RO, #RANTOP+2
1s
PRINT
RAGOOVL

}
3
$
$

set the error flag,
and ¢go back
Go onto the next location

Indicate

MOV
MOV
RETURN

R2,(SP).
R3,ERROR

t
t
3

Restore the return address
Restore the ERROR flag
Test completed

+DSABL

LSB

CMP
BLO
CALL
«WORD

back
value

report

Until

read

the

there

RAM

flag
RAM

correctly

failure,

no more

test

success

206

27 000050
24 000052
29 000056
30

010216
010367
000207

0000006

000001

+END

RAM Diagnostic Task

Figure C-8

The

third

ROM

memory.

and

THe

diagnostic
This

is ROMTST
(see Figure C-9)
which checks the
calculates a checksum on the actual control

test

monitoring

tasks.

potential

1If

there

failure

some

last

installed
registers

cannot

checked

unless

the

000000

then

there

loopback

connector

into these
device can

data.

+ENABL

mismatch

on the J3 connector.
When data are written
and
a device
is connected to the port,
the

000000

checksum

is PIOTST
(see Figure C-10)
which checks the
I/O port on the SBC-11/21.
This test verifies that the
I/0
registers
can
be
addressed.
The
send/receive

capability

2
:

location.

diagnostic

Parallel
Parallel

respond

ROM

LC,LSB

«GLOBL
REC,LAST,CSUNM,PRINT,MESRO1,ROGUOD,
ERROR
+PSECT ROM
ROMTSTs
8

This

}

the

routine will check the
portion of the RUM that

ROM

on the KXT11=AA, this test checks
contains the actual control/monitor tasks

11 000000
12 000004

012700
005001

000006

062001

15
16

000014
000016

001374
022701

000022

001406

li 000010

000024

022700

004767

000000G

000002G
000000G

000000G

000030

000000G

000032
000036

005267
000403

000000G

004767

000000G

22
23

000040
000Ua4

000046

000000G

000207

182

$REC,RO
Rr1

ADD

(RO)+,RE

SLAST+2,R0

BNE
[of 14
BEQ

is
#$CSUM,RY
28
MESRO1L
ERROR
s

CALL

RETURN

«WORD

+DSABL

+END

Figure

«WORD
INC
BR

283

000001

}
¢

CMP

CALL

26
21

MOV
CLR

C-9

PRINT
ROGLOD

Point to the control task address
Initialize checksum value
Update

value

Until

$
3
?

1f there are still some
Are the checksums equal
Yes, leave the test

3
3
$}
?

NO,

there are no values

report

Set the error flag
Leave the test

Report

the

LS8

ROM

Diagnostic

the

fallure

Task

test

passed

9o
?

to sum
get

them

CERXARD
WA -

+ENABL
+GLOBL

000000

+PSECT

000000

LC,LSB
PPA,PRINT,

RGM

’

PGOOD

PIOT8Ts
i

5.
}

This routine checks
testithe anility to

’-

the parallel ports
address the port

the

KXTii=AA

this

only

10
i;
l:

000000
000004
000006

012701
005000
005760

000003
000000G

183

MOV
CLR
8T

#3,R4
RO
PFA(RO)

17
" 000012

005720

87T

(RO)+

Ri,18
PRINT
PGOOD

¢
$
$

Initialize
Initialize
Attempt to

attempt

loop counter
counting index
address P10 port 1f the
fails a trap through the

restart

will

20
21

000014
000016

077104
004767

23
2

000022

0000006

SOB
CALL
«WORD

000207

RETURN

000001

+DSABL
+END

24 000024

000000G

206
217

any

the

will

set

Error

status

all

above

Flags

report

run

time

out

since

there

locations

3
3

Do the port
Indicate success

memory

2-4

LSB

diagnostics

Flag.

Error

and

Parallel I/0 Diagnostic Task

Figure C-10

When

occur

netenener
§ Increment the index, this will not

The

detect

diagnostic

before

failure,

program

enters

the

will

task

program

check

the

programs.

an error is found, the operator is informed that a diagnostic test
failed and the program enters a loop to wait for the operator to

intervene.

Each

indicating

success

diagnostic
or

will

failure.

message

1is

printed

Cc.3.3

Control

Task

Programs

when an

interrupt

If
and

there
the

message

are

program

the

operator

failures,
enters

then

the

task

programs.

complete the
(see Figure C-11)
The Control Tasks programs
initialization of the system by clearing the receive buffer,
enabling the interrupts, and lowering the microprocessor priority
that the
The operator is then informed
to accept interrupts.
receives
TIMER
The
system is running and waiting for interrupts.
entered
is
program
REC
The
a BEVNT input sixty times per second.

is received from the console.

The program will

The BREAK
then turn on the LED and load the ten second counter.
the
performs
and
detected
is
break
a
whenever
program is entered
second
ten
the
decrement
will
program
TIMER
A
REC.
same task as
When the
counter, if it is enabled, every time BEVNT is received.
ten second counter is decremented to zero, the program will turn
If the LED is turned on and another break or
off the LED.

interrupt occurs, the ten second counter is reset for ten seconds.
The program also anticipates any exception conditions.

C.3.4
The

Exception

system

only when a
program
is
operator.

now

Programs
running

and

power fail occurs
entered
only
to

the

exception

programs

are

or a bus timeout occurs.
establish
communication

entered

The PRINT
with
the

+SBTTL

CONTROL

AND MONITORING

TASKS

+ENABL

+GLOBL

TIME,LEDON,PCW,RCSRC,LEDOFF

5 000000

+PSECT

RON

000000

REC:?

4
?

This

}

received

interrupt
a

rodtine

ten

second

accepts
counter

an
is

from

the

console,

initialized

input

and

the

Set

timer

for

Turn

the

Lk oON

LED

When
i{s

the

input

turned

1is

on.

12
13

000000

012767

001130

000000G

MOV

000006

012737

000000G 000000G

nov

000020

000002

15 000014

105737

000002G

TIMERS:
It

5 This

21
22

$}
3

23
24
000022

26
27
28
29
gu
1

000026
000030
000034
000036
000044

000046

005767
001406
005367
001003
012737
000002

interrupt

routine

when

second counter and turn
returns immedfately.

0000006G

000000G
0000006

60.>,TINE

SLEDUN,@8PCW

@8RCS5RC+2

RTI

117
19 000022
19

1<10.%

8718

000000G

GOBACKS

off

entered

every

the

LED

TIME
GUBACK
TINE
GOBACK
SLEDOFF,08PCW

BEQ
DEC
BNE
KOV
RTI

#
?
3
3

seconds

back

clock

the

ten

Flush the receive buffer

tick

time

will

decrement

expired,

the

otherwise

ten

1t the time is set update the
counter otherwise go back
Yes, bump the counter and 1f it is
The last tick then shut the LED off
Otherwise go back

BREAK:?

i3
34

i+
J This

§-

interrupt service

treated

routine will be entered

regular

input

the

KXTii=-AA

a break detected

console

this

port.

31
000046

012767

001130

000000G

MoV

1<10.

39 000054
40 000062

3¢

012737
000002

0Q00000G 000000G

Mayv
RTI

SLEDON,88PCH

LAST:t

60.>,TIME

Set

3
1

Turn the LED on
Go back

the

timer

for

ten

seconds

4
42

000001

«END

Figure

timeout

will

device does

not

occur

C-11

when

reply to an

Control

address

Task

does

not

respond

interrupt acknowledge,

occurs the SBC-11/21
will trap
address.
The start address is

When a

timeout

to location 4 which is the
defined as location 0 and

restart
restart

address is defined as location 4 by the
factory configuration.
The
RSTRT
program
1is
entered via
location
4
and
informs
the
operator
that a
run-time error has occurred and waits
for
the
operator

intervene.

An imminent power failure is detected when the system power is
going down.
This enables the powerfail
interrupt and causes a
trap to location 24.
The POWERF program
(see Figure C-12)
is
entered via location 24 and the POWER FAIL flags are set in the
RAM

memory.

The

RAM

memory

1incorporates

the

Battery

Backup

feature of the SBC-11/21 module.
Program information contained in
the general
purpose
registers,
the
stack pointer
and other

pertinent data are stored
in the non-volatile RAM memory.
The
program
then
puts
the
bus
into
a
known
state
with
RESET
instruction and waits for the power loss to occur.
When power is
eventually
recovered

restored,
as

the

POWRUP

system

routine

restarts.

1is

executed

and

data

are

000000
000000

POWER{ ) POWER2, TIME, SAVERG,PRINT,FMESS
PUSH
ROM

POWERF1¢
5+

000000G
0000006

NOV
MOV
PUSH

000010
0v0020

#123456,POnER1
#135724,PONER2

PUSH
PUSH
PUSH

000008

000042

000777

MOV

TINE
8P, SAVERG

000040

PUSH

000000G

RESET

010667

000044

detected

Initialize

and

the

saves

32=bit

the

power

recovery

test pattern tn #irst two words of RAM

and

000024

000026
000030
000034

Save

PusH
PUSH

000022

123456
135724

012767
012767

000000
000006
000014

This routine is entered when a power fail
pertinent finformation in non-volatile RAM

?
!

the

general

any pertinent
volatile RAM area

purpose

data

registers

none

Save the stack pointer in the
volatile ram area
Put the bus in & known state
and walt for loss of power

non-

RESTRTtS
1A4

!
§
’-

hhen a
& trap

bus error occurs
thru the restart

000044

004767

000050
000052

000777

000001

+END

0000006

000000G

CALL

«WORD

such as an JAnterrupt time=out or
takes place and comes here

FMESS

Figdre C-12

Power

O
I

CENRC
DN -

+ENABL
«GLOBL
e MCALL
«PSECT

Fail

bus

’

Indicate

that

’

occurred

and

wait

intervention

Task

time-out

run-time
for

error

operator

has

APPENDIX
MACRO-ODT

This

appendix

Macro-ODT

ROM

provides
firmware.

the

user

with

the

program

listing

ROM

the

KXT11=A2

TABLE

CUNTENTS

FIRMWARE

MACRD

e
e

KXT11=-A2
Equates

Se
b=

11~

13-

5-~0CT=-81

EDIT

General DLAR1 Equates
General PPl Equates
Program=specific Equates
MACKO DEFINITIONS
kAM Detinition

TRAPS=Trap=handling

routines

Trap=killer

14~

TRAPS=LTC

14~

TRAPS=BREAK

RESTART=1Introduction
RESTART=Entry point
RESTART=See 1if stack exists
RESTART=Exit 1f in IN=RUM state
RESTARI-Cause determination
RESTARI=Exits
POWERULP=1Introduction

15=

19=

2u=42=-

23~
N

2424~

26=
27=

27=-

e (e C

26~

~N b N
AL b

25~

e N\t o

i bt

2]=

20=-

28~

30=-

b e e e

32=-

33~
35~

pmb b bt d ek et ped

36=
37=

3y~
40=41-

42=

43~
44-

b b

45~

48~

48=
48=

poa

47-

Lol [¢,]
L

46~

49=49=50=

51=

w N
N
SR Vell o VR

49=-

OO
e
SR O
S

49=-

S51=
52=
52=-

52~

N
o

53~
53=

handler

POWERUP-~Turn

LED

POWERUP=-Test console DLART
PUwERUP=Test and set up 1/0-page
POwERUP=Turn off LED
PUWERUP=~lest for "low core®

RAM

POWERUP=EXIit

PUWERUP=Subroutine to initialize vectors
AUTOBAUD=Synchronize with Conscole
macro0DT=1lntroduction
macroObI-Save status and print prompt

macro0DT=Get ODT command
macro0DT=

and

Proceed

macro0ODT=Reglister and PS command
macroQDT=Examine and Deposit

macroOLT=-Get and echo character
macroObDT~-Type

ASCII

string

macroO0T=Get octal digits
macroUpT=-0CTSTR--type binary

ASCII

macro0DI-0utput messages
DIAGNOSIICS~for
HARDWARE

ENTRY

sSLUZ2

and

PPl

POUINT

DIAGNUSTICS=Continued
BOOTS=Description
BOUTS~=RX Controller Definitions
BOOIS~-TUS8 Definitions and Protocol
BOOTS=R111 Deftinitions and kquates

BOOTS~Program entry point

49~

22:5&6:27

HISTOkKY

14-

V04.0U

et e

==a=e>

HALT

wm=m=wd>
=====>
~=e=s>

HALT
HALT
HALT

PC=172234
AT PC=172264
AT PC=172304
AT PC=172376

INDICATES

IiNDICATES
INDICATES
INCICATES

Equates

"llleqal

device name"
*jllegal unit nuwber"
"NO low memory, can‘t boot"
"unexpected timeout during bootTM

BOOTo=-RX01/RX02 Bootstrap
s001S8S=Distinguishing type 0f boot block
emew=> HALT AT PC=172454 1INDICATES "NO booOt
BOUTS~1uU58

ceww=>
~wwe=>

HALT
HALT

block

volume"

Bootstrap

AT
AT

PC=172542
PC=172562

INDICATES
INDICATES

"1U58
"TUS®

initiaslization error”
block 0 read error"

B00TS=5tana=alone volume
emwm=> HALT AT PC=172014

bootstrep
INUVICATES

"Directory

read

error"®

KXT11=A2

TABLE

CONTENTS

FIRMJARE

MACRU

V04.00

5-UCT=-861

22:56:27

53=-

54=

BOOTS~Loaa

54-

e=e=e> HALT AT PC=172732

1NDICATES

“Stand-alone

5455~

i2
1

=ee==>

INDICATES

"illegal

56-

BOOTS=Continued

St-

BOOTS=RX01/RX02

57~

306

weeee>

HALT

PC=17307v

INDICAIES

57~

114

~vwe=>

HALT

PC=173262

INDICATES

wee~=>

1730006

HALT

HALI

PC=172652

Stand-Alone
AT

ENTRY

IMDICATES "File
Fiie

PC=17275U

Kead

Read

routines

we===>

HALT

PC=173556

61-

INDICATES

cee==>

HALIT

PC=1730610C

INDICATES

63~

STATEMENT

file

transier

read error"
address®

routines

61-

END

found"

POINT

60~-

BOOTS~TUS8

not

Program

"Floppy
"Floppy
"TU58
*Tu58

drive not ready"
readad error"

END packet missing"
checksum error®

KXT11i=A2 1K FIRMWARE

MACRD VO04.00

5-0C1-81 22:56:27 PAGE &

+TITLE KXTii=AZ 1K FIRMAARE

«1DENT /V1.00/
+ENABL LC

2
3

; Place identification number in last RUA location:

6 V00000

1
8 173776

1731777

173776
000

001

+ASEC1

«=173776
O
BYTE

BYTE

KXT11=A2

FIRMwARE

MACRU

V04,00

5~0UCT=B1

22:56:27

PAGE

CUPYRIGHT

NOTICE

(C)

1980,

1941

BY
DIG1TAL EQUIPMENT CURPURATION,

MAYNARD,

MASS,

W
e

ONLY

INCLUSION OF THE ABOVE COPYRIGHT NOTICE.,
THIS SOFIWARE, OR ANY OTHER
COFPIES THEREOF MAY NOT bE PROVIDED UR OTHERW1SE MADE AVAILABLE TO ARY

FURNISHED UNDER

ACCOKDANCE

PERSON.

w#IfH

THE

TITLE TO

TERMS

AND

L1CENSE AKD MAY BE USED AND COPLED
OF

SUCH

OANERSHIP

L1CENSE

THE

AND

WITH

SOFTWAKE

IS5

THE

HEReBY

TRANSFERRED,

THE INFURMATION IN THIS DOCUMENT 1S SUBJECT TO CHANGE WITHOUT NOTICE
AND SHOULD NOUT Bk CONSTRUED AS A COMMITMENT 8Y DIGITAL EQUIPMENT
CORPOKATION,

DIG1TAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS
SOFTWARE ON EQUIPMENT WHLCH 1S5 NUT SUPPLIED BY DIGITAL.
VERSION

V1,00

U6 NI

UThHER

1IN

TH1S SOFTwWARE

+SBTTL

VWO

MKl
O U b
e

COPYRIGHI wOTICK

EUWARD P.

LUWISH

29=GEP=81

KXT11=A2 1K FIRMWARE

KXT11=A2 EDIT HISTURY

MACRO V04,00

5=UCI=-81 22:56:27 PAGE ¢
.SBTTL
sED11 H1STORY:S
[

KXIll=A2 ED1T HISTURY

KXT11=AZ

FLIRMWARE

MACRO

V04,00

5«0(T=b1

22:56:27

PAGE

EQUATES

+SBTTL

2
7

B1T

Equates

EQUATES

070001

B1TO

000002

Bill

2
4

000004

B1T2

00001V

BITs

000020

BlT4

000040

BITS

20
40

000100

12
13

000200
000400

8IT6
BIT7?

200

BITSH

400

100

001000

BIT9

1000

002000

BIT10

004000

2000
4000

BIT11

010000

b1112

10000

i
19

020000
040000

BIT13

20000
40000

100000

B1T15

BIT14

22
23
24

;

00v012

000015

000040

ASClI

LF
CR

SPACE

100000
CHARACTER

12
15
40

EQUATES

sLine

feed

sCarriage
:Space

return

MACRU

V04,00

S5«UCT=81

22:%6:47

PAGE b

+SBTTL General DLART Equates

DLART EQUATES

177560

RCSRs1

177562

RBUF$1

177564
177560
176540

176542
176544

176546

XCSRS1
XBUFS1
RCSKS§2

RBUF§2
XCSRs§2
XBUF§2

DLART

SLU1
SLU1
14 SLul
14 SLU1l
[ SLU2
r SLU2
14 SLUZ2
[4 SLUZ2

177560
177562
177504
177566
176540
176542
176544
176540
RECEIVE

CSR

[]

[

RC.ACT

BIT11

000200

RC.DUN

BIT?

000100

KCL.IEN

8176

004000

DLART RECELVE

BUFFER

RB.ERK

BIT15

040000

RB.OVR

BIT14

020000

KB
F KM

B1T13

We
Ve
We
W
We

sIT11

WMe

RB.BRK

004000

Receive buffer
Xmit CSR
Xmit buffer

Receiver active
while

received,
Recelver done

Set

(R/0).

character

(R/0).

being

character has been completely
received and now reslaes
in

RBUF.

Receiver int. enable (R/W).
when set, enables “keyboard"
interrupts, using vector
at

60,

(k/0)

100000

BI1YS

Receive CSK
Receive puffer
Xmit CSR
Xmit butfer
Heceive CSR

BITS
W Ws

LCE~NOU
&
N

KXT11l=A2 1K FIRMWARE
GENERAL DLART EQUALES

Error.,
Framing error or
overrun has occurred.
Character was
Overrun error,
recelived before previous one
was

read.

Framing error.
bit

was

No valid stop

detected.

Break detect.

Set when break

is detected, reset when next
start bit arrives.

KXI311=A2

1K F1lRMwmARE

MACRU

V04,00

5=0CI=81

22:56:27

PAGE 7

GENERAL DLART EQUATES

000200

kDY

000100

XC.IEN

TRANSM1:T

CSR

BITS

BIT7

we %o

DLART

Transmitter

Wo e

;s
000010
000020

000040

new

one,

int. enable (R/w).
when set, enables "consocle
printer" interrupts, using
vector

64.

Programmable baud rate bpits

PBRO
PBR1
PBR2

PBRO=2

BIT3
BIT4
BITS

set baud

rates

follows:
300
600

rate

000000
000010

BD.003
BO.006

;B8aud

PBRO

s Baud rate

000020
0000390
000040

BD,012

PBR1

;Baud

rate

1200

PBR1!{PBRO

s Baud

rate

2400

PBR2

sBaud

rate

4800

000060
000070

BD.024
BD.048
BD.096
BD.192
BD.384

PBR2!PBRO
PBR2IPBR1
PBR2!PBR1!PBRO

7 Baud
;Baud

rate
rate
rate

9600
19200
38400

000004

XCJMNT

BITZ2

;Baug

8171

set,

WS
We
We
WE

MINED

BAUD RATE 1S DETEK=BY VOLTAGES APPLIED

BITO

WHEN

tapulated above,
CLEAR,

Transmit oreak

XC.BRK

when
baud rate enable.
the baud rate is determined py bits 3=5 as

Proyg.

000001

set,

internal "loop=back" between the transmitter
and receiver.,
Also disconnects the external
serial input.

creates

XC.PBE

000002

When

(R/W),

maintenance

0000590

(R/0),

Transmit

B1Té

ready

set, indicates that the
last character was completely
sent and XBUF is ready for

When

DLART

serial
continuous

set,

PINS.

(R/wW).

output
BREAK.

when
a

KXT11=-A2

FIRMwWARE

GENERAL

PPl

EUUATES

MACRO

V04,00

5S=UCT=yd1

22:56:27

PAGE

.3BT1IL

PRUGRAMMABLE

PERIPHERAL

PPl

Equates

INTERFACE

(PP1)

EQUATES

176206

PP.CWR

176200

;PP

Control

176200

PPL,A

PoOort

Keglster

PP.B

176200
176202

;PPI

176202
176204

PP.C

170204

sPPI
sFPI

Port
Port

8
C

Keglster
Register

wora

Reglister

General

PPl

MODE=-SEITING

KXTi1l=AA

board

;

the

bits.

mode

BITS

conftiguration

Consult

the

does

not

manual

000040

PP, MDA

;
n

PP.MD2

B1Te

000100

b1ITS

all

using

combinations

the

bits

:Sets

;If
¢

mode

bit

mode

set
is

mode,

low,

port

determines

PP.DRA

(hi=mode 1, lo=mode
sbirection 0of port A.

BIT4

;

BIT3

PP.CHI

BIT2

PP.¥DB
PP.DRB

BIT1

000001

PP.CLOD

BITOQ

“a

000002

000004

BIT

SET/RESET
bit

CONTROL
is

low,

Hi=IN,
Mode

port

upper

half

1l0=0UT.
port

Hi=mode

lo=mode

Direction of port
Hi=Ik, lo=QUT.

bDirection

Hi=IN,

1lo=QUT.

port

lower

haltg

lo=0UT.

BITS

“o

PP1

when

;)

Hi=iwn,

;Direction
Wy

000010

individual bits in Port
of the port’s pnits, and

0T-a

;
000020

PPI.

3 This MUST pe or‘’d with other

BIT7

000200

permit

before

writing

the

PPI

depending

the

CSk will set or reset
the mode and direction

combination

000010

PP.BL7

BIT3!blT2!BITI1

sUse

OwE

0000U1i4

PP.E16

BIT3!BITZ
BIi3!BIT1L
BIT3

70t

these

$to

select

000012

PP.815

060010

PP.B14

000006

PP.BI3

B1T2!BIT1

000004

PP.BRI2

BIT2

1to

000002

PP.bI1l

81Tl

;SLT

000000

PP.EIO

sCLEARed

00vo0u1

PP.BIS

81T

;SET

600000

PP.BIC

sCLEAR

bits

you

;which bit
1is desired
or

specified

bit.

specitied

bit.

write.

MACRO
1K §fIRMwARLE
PROGRAM=SPECIF1C EGWUATES

KXT11-AZ

VU4,00

5=-0CT-81

22 56:27

«SBTTL

7
govz21

BWUATES

MODE

USEGC

TUKN

Program=-specific

LED

AND

rquates

OFF

PP.MODI{PP,DRALIPP.CLO

sPort

Mode

sPort

Mode

QUT

sPort

upper

nibble

sPort C

lower

nibbple = IN

0UUT

~NT

PAGE

000017

LEDUFF

7
000032

PP.BIS!PP.BI7

EQUATES

BAUDRS

USED TC SET

UP DLAKTS

BD,024.XC.PBE

:Set PC7

sInitial console baud rate to
s

000072

TUBAUD

TT-d

;7
160010
167776

BD.384!XC.PBE

MEMORY

CONFIGURATION

2460,

rates

;TUS8

Baud

prog.

RAMBOT

160010

sBottom

1677706

sTop

rate

38,400

address

RAM

SOFTWARE FLAGS AND MASKS

000300

PR16

300

sPS

for

priority

000340

PRI7

340

sPS

for

priority

000200

RFLAG

BIT?

000020

T.BIT

BIT4

;

baud

EQUATES

RAMTOP

with

enabled.,

USED

ODT

MUDULE

:Register flag bit= Indicates
;3 register 1s being examined
sTrace bit in PSW

KXr11=A2

FIRMAARE

MACRU

V04.00

5~0CT=81

22:56:27

PAGE

EQUATES

PRUGRAM=SPECIFIC

[

TYPE

WORD

BlIS

R. hALT

000200

Re. NXM

81T15
BiT7

000001

R. STAK

8110

A SNG

100000
b

HRESTART

’

100000

BOOT

CONTROL

WORD

BITS

BIT1S

NO.LOW

sHALT or BREAK occurred
sAccessed non=existent memory
sbouble=pus error

;N0
5

not

found

DEVBIT

BIT7

11
= RX01/02 floppy
30 = TUSB cassette

000001

DEVNUMN

B1TO

sunit

no.

loopback

DIAGNOSTIC

000000~

boot

000200

[

cl—-d

memory

MESSAGES

000100

E.EXT

000010

E. INT

100
io0

:SLU2
sSLUZ

000001

E. PAR

;Parallel

internal
port

test

falled
loopback failed
loopback

failed

5=0CT=-81

22:56:27 PAGE 11

«SBTIL MACRO DEFINITIONS

DEFINITIONS

MACRU

This macro will insert ABOR1S into the code which will halt the
program, exit to ULI with the PC printec on the console, and generate

an entry in the table of contents which describes the error condition.

AN
U b
N

MACRO V04.00

1Kk FIRMwARE

MACRO DEFINITIUNS

KXT11~A2

«MACRO

ABORT

TEAT

HALT

«IRP

€T-d

«SBITL
«BENDR

«ENDM

PCS,\.

wee=e> HALT AT PC="PCS INDICATES "“TEXI"

KXT11«A2
MACRU

72
el €

FIRMWARE

MACRO

V04,00

5=0CTI=81

22:56:27

PAGE

DE¥FINITIONS
R

;

DLLAY

A,B,N
where

and

clear

1hls

macro

RUM)

When

N<4,

when

produces

,2399N

names

through)
a

delay

and
whose

registers

that

are

integer.

duration

(when

free

running

(both

seconds,

;

CLR

slw

2.44

;

so8

Rn, .

239461.76

;

{508

tlv

239861.76)

{soB

RD,.

21w

239861.761]

H
macro

generates

efticient

code

the

following

code:

H
H

MOV

;n§:

CLR

71w

N¥2.44

S0B

‘Rb, .

siv

65536N%3.66

H
3~

S0B

Ra,n$

N*3.,66

«MACRO

DELAY

CLR
S08B

B
B,.

SOB

A,
L

«ENDM

2N, Ra

25
26

MOy
Ls

#N,A

following:

22
24

the

use

The

are

A.B,N,2L

3.66

will

KXT1i=Aa

KXI[11=A2 1K FIRMWARE
RAM

MACRU V04,00

5~0CT=81 22:56:2} PAGE 13

DeFIGITION

+.SBTTL RAM Definition

1
2

3
4

SCRATCH RAM AREA

167776

TRAPS4

167776

sEnables trap-to-4 emulation

i
8
9
10
11

167774

ODTWHY

167774

1677172

0.CNTL

167772

sUser=readable copy of R.IYPE,
; Restart cause,
See R.TYPE
;
table in RESTART routine.
:GDT Control word.
Set Bit 15
; to disable T=Bit filter, set

13
14
15
i6
17

167770
1677606
167764

B.CNTL
R.PC
IN,USR

==
==
==

167770
167766
167764

167762

R.,TYPE

167762

167760

USERSP

167760

22
23

167756

RPUINT

167756

217

167754
167752
167750

167746

SAYPS
SAVPC
ODIFLG

==
==
==

167754
167752
167750

167744

ODTSTK

167744

24
25
26
28

;

167644

ODTLOC

$STACK

167746

ODTSTKk=100

when none=zero

Bit 7 to disable Priority 7

;
filter.
;Boot control word,
swnhere restart saves top of stack
renables user-caused restart
3 and BREAK when non=zero

sRestart cause,

See table in

s RESTART routine.

sised by ODT to store the user’s
;s

stack pointer.

sUsed by UDT to point to the image
; of user’s RO in its stack.

:Store halted PS here for 0ODT
:5tore halted PC here for 00T
sUsed by OUT for internal flags.

;Used by 00T to peoint to location
;7

currently open.

:Bottom of ODT’s stack

:Bottom of default user stack

KXT11l=A2

FIRMWARE

MACRO

V04,00

5=UCT=¥1

Z22:56:27

PAGE

OQOQUWUWENCUULUNESCLEENCU
- WX~
U b

DEFINITIOW

W WANNNINNNNRN
N N
e b
b et b pd s o

91-d

RAM

170000

«=170000
«SBIiL

FRPFIRRR PRI

IR R X

«SBTIL

TRAPS=Trap=handling routines
TKAPS=LTC Trap=killer

«SBTIL

TRAPS<-BREAK

BREAK=HANDLING

005767

170004

001001

170008
170006

000v02

AND

R
R R A R

LINE
N

handler

N N N
R
IR RIRININIRII NI

170000
170000

1IME
N

CLOCK

R R

ROUTINE

R N
N

R N RN NN
E N NN R R Y ]
IIIEIGIINIIRI RIS

INTERRUPT

NN R
N

R
R

KILLER

R R N
R

N N SN R N
R N

NN
S

7iz3
NN

R E

R RN

S§SSPRKS:

177760

TST

IN.USK

sAre

user

BNE

BRKNUO

sYES=Go

uUDT

sNO=Go

back

mode?

$SSLTC::
RT1

;7
7

BREAKS

can

BRKNODO:3

170010
170014

012667
012667

177736
177734

170020

V12707

100000

1700206

005067

177732

000167

000544

177734

MOV

(SP)+,SAVPC

:Save

MOV

(SP)+,SAVPS

sfor

nQoV

#RHALT,R.TYPE

CLR

IN.USK

Jmp

OoDT

ROM

program.

ignored
POWERUP

OlAGNOSTICS.,

170010

are

RESTART,

170032

001,

and

the

The

BOOTS

interrupted,

context
ODT.

sCauses

PC to be printed

7 upon entry to ODT.
:Get out of user mode

though.

KXT11=A2

FIRMWAKE

MACRO

v04.00

5=UCT=81

22:56:27

PAGE

RESTART=INTRODUCTION

«SBITL

RESTART=Introduction

FIEIIRINFITRIICIINRIRRININIRIRIIIINIRINIIGNIIIIRIISIIIIIIIIIIGLIS
PREIIIERIIEVRIIIVINIIIINIIIINRINNINNIIIIIIINIIIGIGIIIIIINIIIIIIIII:
iii’

iiiv

RESTART

Piis
iiii

MGDULE

i?ii

$ii’

PRI

RVIIIIINIRRITIINIINIIIIIINIINIII

;The purpose
sknown state
saction.

of the RESTART routine is to restore the
following those exceptions which cause a

This

action

consists

stacking

;counter, then setting the PSW to
sRESTART location.
This location

the

FALCON to a
RESTART hardware

current

PSW

and

program

340 and jumping to the hardwired
is at the address START+4 where

sSTART is Jumper selectable as 00000V, 016000, 020000, 040000, 100000,
$140000, 172000 or 173000 (all in octal).
This program is designed
sfor a START location of 172000, thus RESTARTs jump to 172004,
[4

sThere

are

several

different

zfunction, depending
2ot the location the

on
SP

;
sR,TYPE,

type

the

restart

ways

which

RESTART

performs

the value of IN.USR, TRAP4, the
points to,; and one bit (R, STAK)
word,

RESTART’s

output

its

contents
in R,TYPE,
ODT.

’

useful

The

’-

R COESNTNBRBWNEOUTNCTEWN
SO J BWKN

LT-d

W WWwWwWwNNNNNNNMNRRNNRNNE
b
e e e e b e

IR0
FIRIIIRRIFIIIIICRRRIIRIIIRIIIIINIRINRIIIIIIRIRR
s

goal

maximize

debugging

PDP=11

Information

software

the

compatibility

program

developer.,

and

provide

KXT11=A2

FIKMWAKE

MACRO

V04,00

5-00T=81

22:56:27

PAGE

RESTART=INTRODUCTILUN

mremcccen-

KeSTKT

Enter
with

via

hardware

mechanism,

(PS)=340

[}

Is the stack
flag set?
]
Y

|
|

cSTeoeTeceYsSeonsanee e

{
i
i

|
|
}

Set

Set R NXM
In=ROM mode
Go to ODT

|
|
i

We
We

I
i

Set

Read

Check

stack

top

bit

|
j<===Could

stack

1t too close to
Clear stack bit

"hole"

time

|<=====exit
|

out

and

cause

the

to ODT shown above

We
We
Wy

{
|
|

|
|
|1

top

the

there’s no memory 1in

|{==wmeoate==e=s

stack 0000007

Did restart occur
in user mode?
N
Y

]

cPeonacesoraeeene

‘

BREAK

does

vector

this

when

area.

Pop

frame

stack
and

0Only

BREAK

while

get

here,

back

the

0ODT

RTI

can

takes

0ODT.

Set

carry

and

return

Leave

user

mode

stack

BREAK

when

memory

does

there’s

inm

the

0000007

this===>}

Y
N
|
LD
LD LD DL Ly

frame and go
to BREAK’s

|
|

the TKAPS module.
1t
where a BREAK 1in user

SAVE

CONTEXT

entry

point

}
|

goes

stack

|
I

Pop

corecesesencescen

vector area

top

UWE

return

|J<e+=====«

81-d

{
|
I

j{»==¢===e==This

|
|

entry

when

the

point

there

vector

area.

is
mode

memory

KXT11-A2 1K FIRMwARE
RESTART=INIKUDUCTION

5-0CT=81

22:56:27 PAGE 17

cressanccrsecececncanne

;

]

it 172004 on top.

and FS locations.

;

Pop stack frame

Get pushed PC.
Set up ODTI’s PC

|
|

;
H

|
|

’

Fr T L T T L L L T LT TP e ysy ¥

5
6

}

13
15
lb

17
18

6T-d

MACRO v04.00

cesscessevTessesnecanas

;

COULD====>]

Test word prior

QUTew====)>|

PC points

H
;

TIME=====>]

to where pushed

|
Y LT YL P Y

Y Y

sas the word
a HALT

1
|

YT Y Py

H
;

|
l

T T I T Y I I I T

22
23

;
H

I
cacscceersenecewemen

|
|

cocnoronsoncencacw

’

29
30
31
32
33

;
;

;
;
;
;

;

’

cemeconeerTsecoATTEEaRGWw®

H
;

24
25

)

19
20

i or did PC==>NXM? i
[
N
Y

Y P

Y v y-y

|
i

! Set HALT flag !
|
Go to ODT
I

Soceceeeoeweocawwe

| Is trap=-to=4
i emulation
enabled?
t
Y
N
I

T P

Y T T T L Y

|
I
)
|

[

cTeseseseseceoswonwew

i
i

| Set NXM fiag |
|
Go to upT
I

36
37

;
;

W .
-W

41
42

;
;

|
|

Set user mode
Push 8#6, R%4

’

]

;

4._5

FY Y YT YT T F T 0 PP Yy

onto

and

|
|

stack

R1I

KXT11l=A2

FlKMWAKE

MACRU

Vv04.00

5=0CT=81

22:56:27

PAGE

’

ikxception~type word
738 to why a restart

passed

ODT

and

R:ESTARTS

word

ODTwWHY,

"pest

guess"

W,
WP W

user~readable

copy

this

Ne We
We WA WE

NAME

CAUSE

RLHALT

]

i
|
)

!
]
]
)}

HALT instruction in user code=-RESTART POPS STACK.
Nnote~BREAK also sets this bit (see the TRAPS
module).
OUDT uses this bit for PDP=~1i ODI

Note:

EXIT

------l

------'

compatibility.

14
13

|
|

{
{

Reserved
keserved

TO0

TRAF

)

Reserved

FOUK

)

Reserved

1
|

9
8

i
|

|
i

Reserved
Reserved

I
I

1
|

|}
{

Timeout during
memory

'
6
I
s
[ N
S
P
3
b2
1
1

1
i
|
1
)
1

|
|
|
|
}
{

Reservedq
Reserved
keserved
Reserved
Reserved
Reserved

)

i
}

MO W

ME WE

obT

]

ceosseas ' [T Y

|
1

ODT

BIT

opT
OR

0c-d

(KR.1YPE)
happened:

We WE

GV h

N =

RESTART=INTRODUCTIOUN

R.NXM

T T . LI YT

Reserved

user

access

non=existant

T '

R.STAK

Indicates

that

timeout

was

caused

RESTART

itself accessing non-existant memory.
occurs in conjunction with testing for
validity of the stack pointer.
ln PDP~11 parlance, this is a

{

*double=pus error"

7IThis

MACRU

VU4,00

5S=0CT=81

22:56:27

PAGE

oOI<r"~@ON~eV>TM~@c-E~~@C->~S[[*[nTTNsnvBX]o €eNEQ=03=[= Xb(toOTnunNS"R[ooaST oTnNo[nTwvTsaN[sTaL]

KXT11=A2 1K FIRMwARE
RESTART=ENIRY PUINT

Onon S o

16
17

21
22
23

SGWO4un0a0SAOoynuhanOSWT0MBRa4, IoNYnTN [oT~[INTEN-LoY b[2TSITN£-[(ITSERTSNx7[L1rIT 4-bL(TIN[&O[TLN)TS]=R1([T4)7N -Q<"o(Tn«N X¥oOnmD «-=[TNTf<P=[TomNtK[Z2LozTZSW)DoOanuYo*[T=nNT’ Ds(eoLnbT -|[*o5TS4'mnTS1 7[2TS54 ([4o"+n3 -oSnu6 SO8tNny4ua So*nuah
|Ro©=4 L-=4]c0xdP]n
T[N1T -x0+>4L[R 4-b0
n
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o
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c
]
w
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.
>
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o
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k
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e
x
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l
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r
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M
L
9
x
"
4
0
D(0= Oo0PNnn [=-~/oC2o0wm
LeDot2 Ls“c]0o«» OvH-N(DKH-D20]O03-2CO0oLwCc
%]

o~ o ~

O N N« 0

19
20

ReSTRTZ
S

- ~ r~ TM~ -y o

E.T

-y

E 0

170036

") weo
Qe U -

12
13
14

(
T
S
R
S
[
T
t
n
o
O
m
o
[=4 3w -0 Sm ‘S Sn ”n

[0O(ITwnNTS'To“NNnS O[TLM[TnSEs*TNn
oOn0 *h0n4 SnO 8S4n S8R4 aSBm non

1
S
[
T
=
1
Y
(
T
S
R
o
o
"
o
[
a
m
o
n
L
O
I
v
l
s
}
L
T
S
0O M 4 [oaTon S Sh Sn [fIuNEooNn *sna ‘4*n Sh Sn on O‘SYmn SoLInS
=] ()

124 L)IS[[eoNuT'[u"ooTSnn-Q23v]]Lf[sY)4I8BxK47Q}t[+|[oL1[eTmnNINKTo[-TnT~S 1'SN[TQ>.nTSo[aTn=4[

aSt0fmn%u o[YnT oeLIN~CIN L(1ISTNE S-omn [TN [(ITN'T1NY [sS(7Tua,S]=4-tns1a =-o[TNtTN s[41o[TnS%][]=noTN o[TYwSIEL'SM]—Los1mnf [=SPT4n oT[~NmT [TN'TN ‘af*nu

e Sa Sn fa Sa B4 S
oan on ToN LoN
Sm *n 0 fm L

=L}

[ad

KXT11=-AZ2

FIRMwARE

MACRO

V04.00

5=UCT-81

22:56:¢27

PAGE 20

RESTART=SEE IF STACK EXISTS

]L1

£ -

[
]

- el o, 53}

Ve Q>

N oM~

=zX

(W=]2 o~ON

38
170122

005266

170126

000002

E=3

000002

28:

INC
RT1

IN.USR
O~

O ~~ +* - ot ) Q. ”~~ e

2(5P)

€L |9

POmaSnkBS,aSANOmOAhmSPk&N*n
LY LR
oS
TN LI
ontn n"
LY

L1 L1

[18 (2%
on
(19

[2N

1N
L1 on
L1

on on on o’

Ll o
on

1N
on o
L1

L1N

- [N -m (Y

- b

[N S N

o~ [N (Y

STMdOumk
-~

:XiAre we 1n user mode?

4=1 O|[ oe oQ

:Rl

*fSnaw

c0 QX %1sd

here

QJq wa w PLC LY n>7T

~] D~
(=

r~r~ =] - -t

IST

177654

[IN

O ‘tn
=»

005767

o, Ll

ony

1N[
(1%
e *n
ok o
on

v “w o

170104

TM et -t
-t
N - YoD

LIS
TN LI
enLY "LA

Ra "

OLSoh
Sa an

On *h

OR, GO BACK TU ODT IF A BREAK wllH NO LUW MEMORY

SOA¢P0lmnN% SBFan4h0,

RETURN WITH CARRY SEI IF 1N "IN=ROM" MODE

on o

onTN oLTS
LU

LUY omn LY oS oSn

0O%ASmoSMhShO0ndOnhFfhutSaSou

21
22
23
24
25

TC©%W

[«A~ =t

.SBTTL RESTART=Exit if in IN=-ROM state

® T -

i»

OETOVLOED

- [ r~ 0 r~ -

tS&W%Pnmh

N-

-] o c -~

a4]££

= -] &
)[

:RiSet carry in pushed PS

skl UNLESS ALREADY SET

sRiand return to ROM code that
3Rl

caused

timeout

KXT1i1=-A2 in FIRMWARE

MACRO V04,00

RESTARI=CAUSE DETERMINATION

5=-0CT~8} 22:56:27 PPGE 21

.SBTTL RESTART=Cause determination

3
4

AR
AR

AR AR R R R R A A A R R R A A R R R A R A A R R A R A R R R R R R R R A R R R R R R RN
R R R R
R R R R A R R R A R A A A A R A R R R R R A R R A R A A A A R R R R R R R A R R

[
!

R
HARE;

DETEKMINE HOW USER CAUSED A RESTARI

177630

A R A R R R A R A R A R R R R A R R AR R A R R R A A A R R R R R R R N R R N NN N

38z

CLR

INJUSR

sUilwe were in user mode,

11 170130

005067

170134

005716

TST

(SP)

170136
170140
170142

001003
022626
000167

BNE
CMP
JMP

48
(SP)+,(SP)+
BRKNUO

13
14
15
16
17

3is?
i

PP NINNNININIIINNIRINIINNNIIIINIINIIIIIIIIIIINIININIiiiiii

?
12

]
A

177642

skl but no longer.

sRISee 1f BRrAK brought
:P| us here without low ®"core",
;RINO=Just a RESTART
;RIYES=-Behave like a BREAK that
sRI happened while in user prog.

gc—d

19
20

22
23
24
25
26

27 170146
28 170152
2? 170154

021627
001001
022626

172004

31
32
33

012667
011667

177604
177566

39 170172

162767

000002

41 170200
42
43 170204
44

005777

177562

35 170156
36 170162

37 170166
38

014667

177566

000240

45 170206
46 170210

001005
052767

48 170220

(0U415

47 170216

177560

022626

If the CPU attempts to fetch an instruction from non=existent

H
H
H
;

memory, two traps (the first from executing a HALT, the second
from timing ocut) will occur, tne result being that secona
trap pushes the restart address and 340 on the stack.
This information 1s useless and gets popped here.

483

CMP
BNE
CcMp

H
H
:

Note: Because the contents Of the stack is assumed to remain
unchanged ftollowing the first instruction below, it is imperative
that interrupts be disabled during the next three instrutions.

5§:

MOV
MOV

(SP),#RESTAR
Ss
(SP)+,(SP)+

sRiGet pushed PC
JRIODT would like

MOV

(SP)+,R.PC
(SF),SAVPS

-(SF),SAVPC

;Rito see these

SUB

#2,R.PC

;R|Set pointer to last word fetched

TST

BR.PL

:R11s contents of pushed PC = 2
:RI a zero (eg a HALT)?
;RiMake sure next instruction
:R] won’t execute if we time out

NOP
100000

177544

sXiGet rid of double stacking
sXlcaused by EXECUTION of NXM
s X}

BNE
BIS

b8
#R,HALT,R.IYPE

8BS

CMp

(SP)+,(5P)+

’

;7RI before restart occurred

;RiNU= 1t was an NXM
sRIYES= Flag a HALT,

sRipop the non=PDP=11 stack frame

sRiand go to OD1T.

KXT11=A2

MACRO

FIRMWARE

V04,00

5=GCT=81

22:56:27

PAGE

RESTART=EX11IS

052707

000107

000200

000322

177506

183
§s:

LDO DOD - m o~

] ] et v e ed v

YBLo4 ShL SanA Sokw

ko] » S*nTmASaSnsh

o|-BoatSanSSuafOwnSSauStuaoonn

@ot~N[TNEYN[T.

oNE-n¥\HOOoOo0OKiu<MtnTo[oNunTe-~ (sToSo

W1Z7"PX-=tn2Vu]

BIS

#R.NXM,

JMP

ueT

][oTn

ou on snoo O3o 1wvoO8O@0I

170240

19 170254

eO
et

11
18

MNSNP@O HD~-DMNO ODOoOFR~FOr0~rN~0 T-0M~TO~M~

G—*"uaoO*n,

-no[1mTN

R.IYPE

sRiflag NXM error
sRigo to OOT

[+] [~

1] ° o~
@ [=4 o o -~L

5=0CT=81

22:56:27

PAGE

Wy
W

WMy

Ve
Ve
WS

WE
.e

W»

«SBITL POWERUP=-1lntroduction

v04,.,00

MACRO

W
NP CLCX~NTUDdWN=O CAa&NOCOUD

[SE SIS

g¢—-da

KXT11=AZ 1K FIRMWARE
POWERUP=-1NTRODUCTION

..'.'...
wa?aewa’a.°°°ea.‘fi.9....fl'.".'..'.'..........'.‘.
R R R N R N R N R
R R R R

NN
[ I RO B

R R

A R

R R

A R

AR R R

A A

R R

R A

I E N ERENEEREEENENIE R B A B N B B
OO P O & g o L ]
[ IR B B A N
B B B B 2N AN 1
R R A R R R R R R A R R R R A R R A R R R R A A R R R A R R R R R A R R R R RN N N R R
H

B )

a® e

. e

irii

PUWER=UP

MUDULE

Fid’

R]
AR
HE
T3 IRINNIINNIIIINISIIRIGIINRINIRNISNIIINIIIVIIINIRRIN
S IIIININIINNNIIIINIINNNIIIININIINIIIIIIINIIRNRIIGNII
This module contains a series of routines which perform
These
tests on the on=-board RAkR and the console DLART.,
tests are preceded by the lighting of the L&D on the
Should
KXTi11=AA board, and followed by its extinguisning.
the LED tail to elther light or go out, there may be a
defect in the board or its configuration,

Following these tests, the on=board RaM 1s written with the

default values of certaln control words, and, lf there is

memory in the vector region

(i.e.,

and clock vectors are set up.,

boot control word to disable

near 000000),

the BREAK

1f not, a bit is set in the

the bootstraps.

FIRMWARE

MACRO

V04.00

5-0CT=81

56227

FAGE

LED

«SBTTL

POWERUP=Turn

LuD

os[TuNE =([TN [TN -T[otNTn s*"‘ae a*oSmn L_SNUm TL*‘Nn L"OUy O*LnRY.

O fa u Sn 'a Sa n
0N om *h

(T[L1T[(NSNTL1T'T[(["NSTSSTTSNR (-t47[))43af1C1[]lw-[»eTso0TsToMnnaNSawo[o"-[[sTnToTuV [T 73] eno

HOALHNP M

O
S
a
n
o
oL1nYUnTY xL &-[ € 1oTTnSNIoL[nIT[ otS*'BuNnmay*oeo"o°nnn SOOOamnmtTo_ananm
SeTanN"S o" oL = oo9nnonn [} L1 *tLwaY°ona *ooynoasyn
7N[T se“~w SSoTnnny,Ge[SotnTy, S[tnTS"fLamU,
t0%u, FOau ASa EnS, OSmn Ofm Sn

KXril1=A2

PJAERUP~-TURN

SftPWunmha soTtSPOnRa te*na TLNU4

w[TN'TS=}on*u moa4[on"
11

PWRsUP::

170260
17v260

0127086

’

ie
17

’

-~ ~ < N el «

o~ T~ ~m ~

[~ < o o~ [ -4

st TM~ ] (3] o o

B ecause

26
27

28
29
30

sInitialize

stack

pointer

mode=setting command automatically clears all the internal
in the PPI, and clearing Port C sit 7 turns on the LED, all
we
have to do is set the mode, which is port A and lo half of C as
i nput, ports B and ni half of C as ocutput.
r egisters

x o -~

i)et-~ <]o O.] = xQ

[Q n &

Q[ Q.3 o]x=%|

1
[+ Q. [

Q 1)

E o kel L.

3] o [~ u

005037

177504

CLR

@#XCOKS]

L[INIYN T0L"N,I

sDisable
;

170276

005737

170302

032737

177562
600300

177500

IST

8¥RBUFS1

BIT

$<KRC.IENIRC.VUR>,8#RCSRS1

Set

s Take

moes-m

4s-e lnola dh @0 TMmo DNO [=ONOe- =o~

-y ~ r~ 7o) O <>

> =] (=4 TM~ b= k=d

N XZOo)

e«3

b.d TM|
& w x w0 -4 -~ L] Ead |84 3 X Q Eal

XMIT

XMIT,

baud

out

;8hould

D0.
(N v -

bRK

interrupts,

maint.
rate

the

Fol

default

trash.

O OQ= - WQv [=1 [4Y
o]

mode

clear.

o L

170272

&[Ye"TS~) .o[7TaNO

fu om n

#$STACK,SP

tSf[TOTaanN [fSSFTfNaunuE t6yhaA OBN Shn S%Sun [TSSSY Wouyl PoS"fth
Leoo[TaNu *-Lo*n~NnE OCw0ToNInET*oL-.NSn
to0n -ooS~ X eW(TnaNTSLofINaS
oa o [T
tm su N "
[TObCnnySSC-eO [bTyTN S[eoTymRTuSoo,uN
[Td[SuTwNTo*Nnn [TTsN [-SA N
LUo[SmaTNIoLSNyWu Sun Sh Sh BLfTLGn8mNSER[SSTNN
Na0W BBAa SGRk fSm O .P

NIMO(

MOV

167644

2] x
Qe -

12
13

< [

o[
%] [ .

KXT31=A2

FIKMWARE

MACRO

V(04.00

POWERUP-TEST AND SET UP I/0-PAGE RAM

5=0Ct=81

22:56:27

PAGE 25

and

set

I/0=page RAM

+SKHTIL POWERUP=Test

IR
I NNV IIEIIIIEIIELS
R R R R R R R R R A R A R A R A A R R A R R R R R R A R R A R A R R R R R R R R R R R R A

S L

’rz’

R -

iiid

HE
i
FPINNNINNIIIINRINIIIIIRIININNRIRINIRLIIIIIIII
s IR}
3ISIINIIININRININIIIIIRRIIIILIRILIIIIRIRLIIIRIVIIINIIIGRIIIIINNGIR:S

WK = COCX-NT
U
WK =C L <

222

1/0 PAGE RAM TEST
AND INIYIALIZATION

HA
$id

b o

: ¥rite the location’s address into the location and read it back.

NN NN DN N

LZ~-d

pd o bbb

s
s

;s
;
170322

012700

170326

010010

160010

Do this for all i/0 page RAM locations,
1f it fails, enter tight loop,.

In the process,

value of

1s:

most of

clear all of tnils RAM.
the control

1is

zero.

#KAMBGT,RO
RO, (RO)
RU, (RO)
28

sLowest address of RAM
sWrite the address
sRead it back
:Tight failure loop

;until no mOre to test.

170330

020010
001317

170334

005020
020027

CLR
ChP

RO, $REKTOP+Z

103771

BLO

is$

170336
170342

Note that the default

flag words

KOV
MOV
CMP
BNE

170332

282

and

(RO)+

;Clear and go on to next location

oso1[STotTs[1[Lbso[t[wTtS0TuZTnLmSnNaNnumnSIaNN,TSINXrC'E[so"'(oa-.on[[n([oasSeISStOTSTNTmnaTIAmNSNNanEPtoauSa-Y)>(QT4]-=S[e&|s=aff43]~ajel,u]«»nAtSn4aswaS[se[[sLtYJm(o®ToOTs(eoSeTuTENamNnNnanwNhynQTITEN'wo[o"ao-os-a[[[~NoTSoSSLnnYnTYTnTnoha[%[(a(|-'»w]w[¥=o14=«=5V@T)d[-3)M]]L1[+|«L24.[»(]9-==3N-=),T+[&1]ESeos&Tahoof[teUaTto[WOT1[SPownmSuwnanwNmTmSNnmu'TT*a[o-oS‘[mwoTSPF[(oeSo"usTynunmuNnuTwRn[StSnan-to(tQoQXz=S2t3una.]OSaSVs[=[bt[(oTLTeoo2L1OT1oo*SfnINaTSNnnIaNNTmnYnu,ySN'NRCeoIYT*ToL[o-Y[o[o-sTSu[-eNNSYnunT~mTuSnmT~mTu[k-L=Tw1=[s]Po0L=L[3&Mo@cOvc[&)]4o8=}41tI[]2]~[))1]OeNeYWDonXO7Y]Ytu&GNgsOawoTaSnvvQ0RMoXohLtT9Cnm"s-“L]0xTWoFN[uoMe[7Tm0,o-|mGToT[[os(Ln11[1LT(&nTaeooo1t'In9NY'aSSNmnwNanTNSTLAKTSNTF[sLTo[.o["o-eTP-[eSoNRINnuInTTNaT~[S,BTfSuax25a-=-([oPx¥BS74T~jN]|]x-SzfL-l}ot31a)a&1tir>[4nn]TNTSSARCaRTA[Ts1ST[tLELwteW[[TTS(oSoSYNNIZNTnaymanmunR9INTNELNCTtRS[o[faTos‘o-[TN[LTo2YSNTTnm»uenNIn=e=[o©-2)[|&X-Q79'eA[1l]%«'[t+]54
ooOLO[a0(mannTSNTSE'NTooAeITSnunNaSSunxntsSnan*SSAunnSo[soTt(oSTaannuwOTSE[ons-STyuSn[=1e] eSA(Too1[uN9nTN[Seo(SSOo-TLmnVNOGeSnSSOtmnuaS&SnuLaIosLSSYnunnSItoSt"oas[.nuLTaeOL¢»]ot]d]|~bw0QC»cw%WmoBboQokaO20MLo-»OOo4-=i0WSo -¢4t~[ SLToWfToImMSNnSCSNo-[tYMomTnSo[StTmuSTA]*)e-QaUSSTnum[STTe[a(e¥sounSannnoLToS[Su-nTnUuSn
--toTouO<a<d~nl~d ]e=W-o2M0oODt}~~0M=ootNtlvoQwMDldt0~0<Ov=vB2oti9tlNN0bTO[iLo=tlP

42
43
170364
1703606
005710

45
170370
103403

46
170372

170376
v04767
000403
000042

170400

052767
100000

50
-

FlRMWARE
MACKO

"ODyO0

= 1

OTM x

KXT11=A2

POWERUP=YURN OFF LED
V04,00

177362

5=0C1I=81

‘!
R ead

000240

8¢

22:56:27

TIST

PAGE
26

nO@E]1Lvbold ofeD]

-] o~ (=4 O
-4 r~L

/A UTOBAUD
memory at 000000, discard result.
It this fails, exit to
rather tnan continuing with normal powerup sequence.

NOP

(RO)

BCS

7s
.

CALL
VECSET

;bon‘t

BIS

$§NO.LOW,B,CNTL

:D1d

+This wlll execute even if
last instruction times out
[
;Iimed out, don‘t set vectors
;Didn’t

r
.

set
time

time

let

the

out,

NO.LOW

world

SO0
go

flag

out,

know,

ahead

KXT11=A2

FIRMWARE

MACRD

V04.00

5=-UCT=81

22:56:27

PAGE

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PUWERUP=EXIT

]

32
i3

170440

35
36

170440
170446

170454

170462

170470

N ote

This

r estore

was

subroutine

tne

read

vector

into

low

area

owo (O= D&bho~eO-

also

the

used

event

the

that

pbootstrap

module,

invalid boot block

memory,

VECSET::

012737
012737

170000
0003490

000140
000142

012737

170006

000100

012737
000207

000340

000102

MOV

#SSSBFK,@#140

MOV

#PRI7,0#142

MoV

#$SSLIC,0¥100

;Set

MOV

$ER17,e8102

RETURN

sSet

the

BREAK=detect

vector.

the

vector.

line

time

-4 -

177330

(v= c= ~[~}tQ

-0TP9M0m~0TM No<~ToM

([IR=] NINOD ON -Ot

177340

clock

FI1RMwARE

MACRU
wlTH

V04,00

5=0CY=81

22:56:27

“p

we
e

—e

“e

Wo
Ve

we
e

we
~e

we
e

TMo
e

iels

SEICEIRRINRIIINNRINRIRIIRIRIINISVIRIININGIGRIEG
PPN IRIINIINIR IR NRRINIRIIRG
G

Wa
W

e
Wa

R
I

MODULE

R R R A R R R R A R R R R R R R R A R R R R R A R R b

R R R R R R R R A R R

i rearssiiiss
iR iasddisisiRisiviiiiidinis

with Console

Description:

e W W W W W NN NN DR NN KR e s b b et b d b b
LT N WMNROOENT
U
&EWNSROLENCUE
WK =S WENOU Bl

AUTOBAUD

Upon syncnronization,

VA e

AUTOBAUD allows the FALCUN to automatically synchronize its
console DLART to the baud rate of tne console terminal.
On power=up, the user must type a carriage return character.
character

AUTUBAUU will proceed to QUT where an

displayed

the

‘@’

console.

will

loop

indefinitely

until

synchronization is

successful.

Autobaud wlll

Environment:

The algorithn requires that the console terminal generates a
zero (space) for the eighth bit in the carriage return.
This
will happen 1f the terminal is capable ot sending eight-bitno=parity or sevepn~bit-odd=parity characters,

service routines may cause DLART overruns,

Interrupts must be disabled for the algorithm to execute correctly
since time durations are critical ancé delays due to long
ignores

cannot

whicn thils routine

tolerate,

sequence

has

begun,

leave garbage
we

must

in the DLART long after the

delay a

bit

before

completed

AUTOBA:

170472

012737

170500

005000

000032

177564

clearing garbage

out of the DLART, otherwise the garbage would arrive after the clear
The "garpage® is an X=ON (<CTRL~qg>)
(i.e., wnile polling for input).
that the VI-100 hardware sends after its power=up diaghostics have
successfully.

e
OO

vV1103/FALCON configurations

but

powerup

S
MOV

#BAUDRS ,@#XCSRS$1

:Set

;Delay

KkO,.
RO,.

H
H

X
U

B
o
WK

2¥

AUTUBRUD=Synchronize

«SBTTWL

170472

LY
- O

0g-d

PAGE

CONSULE

KXT11=A2

AUTUBAUD=SENCHRUNIZE

170502

077001

CLR
S0B

170504

077001

S0B

2400 baud
«d
seconds

KXT11=~AZ

MACRO

FIKMWARE

AUTOBAUD=-SYNCHKONIZE

wlTh

VU4.00

5=-0Ct=81

22:56:27

PAGE

CUNSULE

AUTCBAUD

proper:

7
8

170520
170524

113700
012701

170530

120021

170532

001411

170534

020127

170540

001373

176542

005000

170544

077001

170546

000757

177562
170550
30s:
170556

'
40s:

ISTB

@#RCSRs1

BPL

268

MOVB

G#RBUFS1,

MOV

$INBYTE,

CMPB

RO,

BEQ

HVBAUv

Rl'

BNE

308

CLK

S0B

RO,

108
you

1input

scrampled

the

table?

#INBYTS

yes

end

table

not

vet

40s

uh oh, wait for DLART
walt for a while

would

see

octal

character

try

for

sent

char

table

reached?

another

the

clear

character

following

170550

200

«BYTE

170551

300

170552

170
346

«BYTE

200
170

rates,

170550

600

24 170553

015

«BYTE

346

«BYTE

15
362
371

1200
2400
4800
9600,

302
3717

«BITE
«BYTE

INBYTE:

19200,

38400

pointer

into

INBYTS

have

match.

170556

162701

170562

006301

34
35

170564
170%66

006301
05201

170570

006301

110572

010137

176576

005000

170600

077001

into

DLART.

170551

177564

;

Fall

suB

#INBYTE+1,

ASL

INC

ASL

MOV

R1,

CLR

S08

KO,
.

into

ODT.

BFXCSRS1

turn

rate

HVBAUD:

turn

170556

baud

set

the

Set

into

170554
170555
170556

input

were

garbage

25
26
27

any

and

b aud

what

for

18
19

Table

wait

delay

Te-dad

;

(k1)+

cMP

16
17

RO
R1

105737

100375

-e

170512

170516

discard

20s:

B*RBUFs1

177560

TI5Ty

10s:

177562

1u5737

170506

3
4

bit

mask

XC.PBE
baud

rate

CSR

.24

char.

seconds
at

slo

for

baud

rest
rates

out

5=0CT=81 22:56:27 PAGL 30

Ne
e

We Ng

WS
Ne

N
We
up

s W

s Wy Ny

We -Me

.SBTIL

We We WS Ve Wa

MACRO VU4.00

e WE W

KXT11=A2 1K FIKMWARE
MACKROODT=1N1RUDUCT1UN

macrolbT=Introduction

NG
SrIrrrrIIRIIRRILIIRNIIIIRRiRRIRNRNERRIRRRRRRNIRRIGii
A R A A A R A A A R R A R R R A R R R R R R R R R
A
I I
N
H
R
HE
HH
R
R
macro0DT
1
i3
H
PIRIIIIIINNININRRIRIRRRRNRNNNNNNNNRRRINIINNIG
IETEIIIrIiINNINRRIRINIRRINGNRNIRINIRININIGIINRRINNIINIVINNVG
macroODT is the user intertface to the functions contained
in the KXTi11=-A2 firmware product. It interprets commands
entered via the console terminal keyboard (see tables vpelow)
to permit tne user to load a program into memory, execute
it and debug 1it.
COMMAND

i= Slash (/)
a=UPEN MEMORY LOCATION
b=QFPEN GENERAL KEGISTER
¢=0PEN STATUS REGISTER

2« Carriage return

(<CR>)

a=CHANGE AND CLOSE MEMORY LOCATION OR REGISTER

p=CLOSE WITHOUT CHANGE
3= Line feed (<LF>)

a= CHANGE AND CLUSE MEMORY LOCATIOM AND UPEN NEXT

b= CLUOSE MEMORY LOCATION WITHUUT CHANGING AND OPEN NEXT

4= Go

(G)

5= Proceed

(F)

6= Execute I/0 diagnostics
7= Execute bootstraps

(D)

(X)

KXT11=A2

FIKMWARE

MACRU

V04.00

5=0C1=81

22:56: 27

PAGE

sDURING

AND

A FIetR

sSYNTAX UF COD MMANDS L1STED ABOVE,
Key:

n=an

THE

TYPING

SHOWING COnSOLE
THE COMMAND,

u~the digits 0 or 1
all other characters

single

octal

the

user,

digit
are

literals

Xx=a

octal integer typed by
last 6 digits significant

BEFORE,

BEFORE

DUKING

AFTER

]
e

en/

BN/XXXXXX

@RS/

Bn/XXXXXX
BRX/XXXXX X
BRS/xXxxxX X

en/xxxxxx n<CR>
GRX/XXXXXX n<CR>

Q
a

PRRX/XXXXXX

XXXXXX/XX XXXX

XXXXXX/XXXXXX

EBN/XXXXXX
BRX/XXXXX X
ERS/XXXXX X
XXXXXX/XX XXXX

an/xXxxxxx

NP
NP
Wi
e
W
NG
WA
WE
we

TOoOOoTOMOMNDDOUOTD

erRx/

@RX/XXXXXX

QRX/XXXXXX
@RS/XxxXxXxX

Nn<CR>

N<CR>

730

XXXXXX/XX XXXX

H
;
76

8
(]
@

[

oo [+ ]

XXXXXX/XXXXXX
XXXXXX/XXXXXX

en/xxxxxx <LF>
XXXXXX/XXXXXX <LF>

an/xxXxxxx

e
2]
@
XXXXXX/XXXXXX

XXXXXX/XX XXXX

enN/XXXXXX

@RS/ XXxXXXx <CR>
XXXXXX/XXXXXX <CR>
8n/XxXxxxx n<LF>
XXXXXX/XXXXXX NCLF>

w W w

$2b

XXXXXX/XXXXXX

aneG

epP
XXXXXX

POV

RPDD

€e-a

RNANNNKNNDN
=
-

L&~
U
W=

MACRUUOLT=LKTRODUCTION

8DDu
wbau

eDYu
QUDLCR>
@DX<KCR>
@DY<KCR>

onily

V04.00

5=0CT~81

22:56327

177562

016767

177150

170614

010667

170620

012706

MOV

177140

Save

SP,USERSP

MOV

#0DTSIK,SP

user

¢ SAVE

USERS

$LOAD NEwW

7 SAVE

010446

UV
MOV

k3,=-(5P)
R2,={SP)

;7
;

MOV

R1,-(SP)

;

MOV
MOV

RO,-(SP)
SP,RFOINT

;
REGISTERS
sPOINTER TO RO

010346

170636

010246

170640

170642

010146
010046

170644

010667

177106

e
WE

Wu
We

W
We

We
NE

$RESERVE LOCATIUN

4,=(SP)

Wa
WO
Ne

USERSP, (SP)
RS,~(5P)

170634

POINTER

program’s context

Mov

177130

STACK

MOV

016716

Me
ws

but save user’s 3P first

MOV

170624
170630
170632

into user area

010546

25
26
27

we
-

we
"

wp
~a

we
.

we
-us

wm
..

s
-y

we
-

we
e

we
we

we
e

we
-

wa
e

e
s

TMTMg
~e

TMo
e

we
e

we
-

“e
-

MOV

rest of

garbage

R.TYPE,ODTWHY

Protect agailnst stack timeouts,

167744

we
-

we
w.

wms

wa
ne

wa
e

“e

We
w8

-y

e
e

ws
~e

“eo
we

weo
e

we
e
.

the restart type word

console

out

sClear

@4#RBUFS$1

PRINT MESSAGES AnD PROMPT

W
.

Wwe

Wws

“.

prompt

weo

wo
w

wa
we

“e

“e
e

e
we

and

weo

status

“r

W
-y

w
.

w4
e

%o
s

Wp
Be
W2

Mo
we

We
W

macroubT=save

Copy

177160

reE-a

We
"e

TSTB

;

1706006

105737

;
16

=]
|

170602
170002

SAVE CONTEXT,

W
Ws
W4

+SBTTL

11
12

PAGE

PRUMPT

AND

“e

STATUS

-e

MACRO

FLRMWAKE

MACROUUT=SAVE

KXT11-A2

Determine whether

"?"

FOR R®

ALL

UF
USER’S
GENERAL

or PC message is approprlate,

and print it

177108

TST
BPL

R.1TYPE
QoDT

016700

177070

MOV

SAVPC,RO

$YES=PRINT PC
$GE1 STUPPED PC

004767

000764

CALL

OCTSTO

sTYPE THE PC ON TERMINAL

TSTB

R.TYPE

BPL

KbD$§

$;SEE IF RESTART OCCURRED
s (NXM ONLY=B1T 7 SET)
s TIPE PROMPT

170650

005767

170654

100004

170656

170662

1706066

sD1d we get a HALT or BREAK?
sNU=next question

QODT:

170668

105767

170672

100003

177070

;
48

170674

012700

170700

000402

179702

170702

012700

54 170706
55 170712
56 170716
57 170722

005067

177050

106427
004107
005067

000620

Here’s

where

the

prompt gets

printed,

with or

without

leading

"?*

KBDQ:

171730

MOV
BR

#MSGGE,RO
PRINT

s GET
sTYPE

? ADDRESS
IN MESSAGE

MOV

#MSGS, RO

:GET PROMPT MESSAGE ADDRESS

CLR

R.TYPE

1S5S0

MIPS

#PRIG

sAllow

KBDS
¢

171731

000300

177022

PRINT:

CALL
CLR

PUTSIR
ODTFLG

reentry

gives

BREAks

error

happen

:TYPE THE PROMPT ALREADY
3CLEAR FLAG FUR NEW ENTRY

msg.

FIRMWARE

MACRG

V04,00

171024

120227
V01321

R2,#°P

s PROCEED?

CMPB

R2,%#°R

sREGISIER?

BEQ

RCMD

000060

cHpPB

R2,%°0

s YES
;O0CTAL DIGIT?

BLU

KBDQ

000070

CHPB
BHIS

Rz2,%°%8

CLR

CALL

GETNUM

BCC

KBDO

28:

000122

000576

PCHMD

KBDu

W
@

&
e

W W2
We

WA
W

WMo
N

W
W8
e
Ws
e

CMPB
BEG

000107

%
-

sYES

000057

“e

“a

%o
“e

e
as

%weo
“e

we
e

‘we

weo

wo
e

“eO
ws

N9
Ne

“wo

we
e

e
-

“e

We
ws

TMo

We
e

DIAGKO

000120

Wwo
e

Wy
-

“e

w4y

‘up

TMo

w-a

-e

‘e

“a

W
“s

TMe

-e

g
-y

TM
s

%®

We
we

“e

“o

-y

“e

TY
LT

we
we

“e

we
“

sNO

JMP

120227
001511

e
-s
we
we

WMo

e
N

we
ws
we

sDIAGNOSTICS?

103736

171022
171030

R2,%#°X

000776

RO contains

7ees INPUT CHARACTERS

BNE

-o

171016

103327

MNP

171014

103333
V05000
004767

We N

i71006
i71010

typed in.

ChPB

000130

171004

the address

sNO

120227
001002
000167

120227

the octal integer

JMP

170744
170750

171000

carriage return.

;BOUTSTKAPS?

001220

120227

(7 bit ASCII)

1f carry is clear,

is
BOOTS

176740

001465

followed by a

the character

BRE

000104

170770
170772
170776

R2.

note: On exit to LCSET or talling through to GO routine,

WE Mo

was

Following CALL GETNUM,

R2,%°D

000556

120227
001002
0v0167

170764

Following CALL GETCHR,

appears

Note:

GETCHR

004767

170732
170736

120227
001430
120227

command

CALL
CHMPB

1701726

170756
170762

GDT

INTERPRET FIRST CHARACTER OF CUMMAND

Note:

o~
O
-

Sg-d

wacrol DT=Get

«SBT TL

170752

PAGE 33

22:56:27

5=0C1~-81

COMMAND

KXT11~A2

MACROOUT=GET UD1L

FIES

$YES

sNO,ERRUR
sVALID DIGIT?

sNO,ERROR

:ITS A DIGIT
$GET REST OF THE DIGIT OR CMD

JCR WAS

ISSUED,ERRCR

The last character at the end of the number could be a valid command-

iLet®s

chec Ks
CMPB
BEG
CMPB

R2,%°/

BNE

KBDG

LCSET

R2,%°G

JEXAMINE LOCATION?
FYES

;60 TO?

3 NO,ERROR

MACRO

V04,00

S=UCT=B1

22:56:27

PAGL

TABLE

PEKM1SSABLE

STATES

VALID INPUTS
U=1

coccass)

COMMENT
digit.

csveuam)

proceed,

seoseeew)
escecoan)

prompt

STATE

NU.

Wwp

CUMMAND

8176000/000002

esesesw)

boot

csessas)

another digit.
examine loc,

ccoumew)

8175620
[input aigit]

device

ooecsene)

input new value,
display next loc.

loc

input more digits.

eweceaw)

save

data

display

cececass)

save

data

ecsssesw)
cosease)

from

cecesan)

esecesse)

Se=

0=7

WO W

82007000023

[ L]

@RS
eR5/000024

@R5/700U0024

loc

T T) )
YT
LT

eweosmee)

PSw.
exarine,
input new

sceseese)

ODT

b md

b ot o

et o

=
PO -200bNe=C WU PN

NN
B

ChakN

9¢-a

FIRMWARE

MACROODT=GET

KX[11=A2

0=7

cweoseose)

escemea)

0=7
CR

eceseceses)

secesces)

save value go

prompt.
next.

prompt.

value,
location.

digits

input

to prompt

171040

000005
005067

171050
171052
171056

171060
171062

for

the

%
Ve We
WS
W

W
N
NG
WA
WS
W

“weo

We
e

W
o

W
w

ws
we

we
.

we
s

“o
s

wg
w.

we
“e

“s

o
e

“e

environment

MEMORY

WLOCATION

command

¢BUS INITIALIZE
sCLEAR PSW

RESET

CLR

%o
“s

W
e

we
-

we
-e

we
we

%
s

%o
-y

we
-

we
~e

Wwe
e

“p
e

Wy
we

%
s

-s

-y

the

;PUT SUPPLIED

RO,SAVPC

W
-

WMo

WE
we
.

ODT COMMANDS

we
e

AkD PRUCEED

“e

Wg
wes

“e

weo

me
«e

-e

We
e

we
.o

«a

@y
we

“s

W
-

“p

we
“e

wWe
e

-y

weo

-s

“wo
-

weo
weo

Wwe

-e

we
ws

w»
wo

W
e

MNP

and Proceed

SAVPS

Entry point for the Proceed command

First, check for valid stack:

PCMD:

016600
005740

14(SP),RO
=(RO)

suser’s stack polinter
:Where SAVPS will go (see below)

BCS

IST

=(R0O)

2No good.
Timed out.
swhere SAVPC will go

MOV

000014

TST
NOP

000240
103403
005740
000240

NOP

103004

BCC

000201

176702

sSufficient

EITHER Stack no good,

user’s context

1s:¢

MOV

012767

171072

000700

(in case of time out)

171064

so simulate a double bus trap without losing the
as

$R.STAKIR

stored

NXM,O0CTWHY

the ODT stacke.
:Sneaky!

only

(R.TYPE

the

user

untouched=-

image of

it)

prompt,

sError

KBDQ

Stack 1s UK,

stack.,

so restore user’s context.
sRESTGRE

012001

171100

012602

MOV
MOV

171102

012603

“ov

(SP)+,R0
(SP)+,R1
(SP)+,k2
(SPI+,R3

i71104

012604

MOV

(SP)+,K4

171106

012605

MOV

(SP)+,R5

17111V

106427

000340

MTPS

$PR17

;No BREAKS

171114

042716

000001

BIC

#B1TO, (SP)

171120
171122
171126
171132

011606

MOV

(5P),SP

10dd stacks are too odd for T=-it
sRESTURE USER SP
$1Set user mode

171136
171140
171142

176636
176622

COM

016746

Mov

IN,USK
SAVPS,=(sP)

016746

1760614

MOV

SAVPC,=(5P)

V05167

W
WS

ALL

OF
USER’S

GENERAL
REGISTERS

000655

HKBDG:

KBDW

000657

HKBDS

KBDS

allowed

until

out of

ODT!

sRESTORE

AND

2.0eSTACK WHEKE RT1 WILL LOOK
sRETURN

RTT

000006

WME

171074

171v76

012600

MOV

LE-A

171054

Prepare

176710

171044

171030

MOV

176714

;

macroubDl= Go

PRUCESS GO

Ui
@Y
-

010067

«SBTTL,

171032

PAGE

22:56:27

5=uCl=81

MACRO V04.00
KXT11=A2 1K FIRMWARE
MACRUODT= O AND PKHOCEERD

TO USERS

sHELP IN BR
sHELP IN BR

PROGRAM

MACRO

Vv04.00

5=0CT=-81

PAGE

W
We

W
Ne

WMa
W

WG
3

wo
n

W
s

we
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we
-

T
LR

e
e

we
~e

e
s

we
e

we
"

we
~e

LTI

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we

W
e

“wa

w8
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and

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s

we
we

for

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wa

wa
wa

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point

we
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LU

weo

-s

W
ME

Entry

WUr
W

COMMANDS

ODT

WS
We
e

WNe

we
T

we
e

we
ws

we
we

command

w~e

“e

TMo

PROCESS

commands

RCHD:

171144

052767

000200

BIS

$RFLAG,0DTFLG

171152

004767

000420

CALL

ONENUM

171156

103236
120227

BCC

KBuQ

000123

CHPB

K2,%°S

BEW

SwCup

CMPB

R2,#%%/

BNE

KBEDQ

171160
i7ilioa

001412

171166

120227

171172

001240

171174

and

ws
~e

W
Wy

weo

“wo
o

«s

.o
- we

we
.

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s

we
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s
We

macrouDl=-Kegister

N¢
e

WE
W

We
Wg

171144

«SBTTL

8e€-d

22:56:27

COMMANU

LM~
PP
N

FIRMWARE
AND

KXT11=A2

MACRUODT=REGISTEK

020027
101235

171200
171202

001013

171204
171210

000413

012700

176576

000057
000007

cup

167752

;7
171212

Status

7SET KEGISTER FLAG
/GET KREGLSTER NUMBER
fA VALID CMD DID NOT FOLLONW
$IS .T THE RS?
sYES,BRANCH

JEXARINE?
#NO,ERRUR

RO, #7

272

BHI

KBDu

§ YES,ERRQR

BNE

RCni1

sI5 IT EXACTILY SEVEN
JYES,GET PC ADDRESS
sDISPLAY

MOV

#SAVPC,RO

REGOUT

(PS)

selected:

SWCHD:

171212

004767

000272

CALL

GETCHR

171216
171222
171224
171230

120227

000057

CcMPB

R2,#°/

BNE

KBDG

sNO,ERROR

MOV

#SAVPS,RO

sGET

REGOUT

;G0

001224

012700
000403

167754

171232

006300

171234

066700

176516

171240

0190067

176502

171244

000402

RCMD1l:
REGUOUT:

sWHAT

YUU

WANT

WITH

RS?

FEXAMINE?
ADDRESS

AnND

ASL

ADD

RPOINI,RC

MOV

k0,0DTLOC

#5TORe

LOCDSP

JDISPLAY

/SHLFT

;GET

WHERE

18§

DISPLAY
FOR

EXACT

OFFSET

ADDRESS OF

LOCATION

MEMORY

REG.

MACRO

v04.00

5-0CT-81

22:56:27

PAGE

DEPQSIT

W
w9

We
W

W
We

We
WE

W
We

Wwe

we
~e

we
we

e
-

we
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wp
e

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we
s

e
e

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ws
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weo
we

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e

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o
we

weo

we
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wa
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ws

w8
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-

EXAMINE/DEPUSIT

AND

MEMORY

“e

w
e

e
“y

weo

wo
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Deposit

“we
-

T
LU

weo

we
-

“s

“e

we
we

“e

ODT

“eo

W
We

W
Ne

M
NS

NS
s

PROCESS

and

We
-y

010067

171252

011000

171254

000240

171256

171246

C L

6£-d

ODTLUC points to register or memory location
Following CALL GETNUM, 1f carry is clear, CR followed digit.
OLDIFLG: If register bit set indicates register is being examined

$ENTRY

wINNs NNP
W w;W
tw
W N N N N
oAT AP
DD [ w W ww
W N = C e ® ~ O NN =
e N=C WO~
WUh w K=o A -4

ol el

)

macroGUT=-Examine

«SBTTL

KXT11=A2 1K F1RMWARE
MACROCDT-EXAMINE AND

171260
1712064

1712170
171274
171300
171304
171306
171312

171314
171320
171322
171324
171330
171332

171336
171340

171344

103730
004767

176474

FROM CMU ROUTLiNE AFTER LOC.

VALUE

IS5 GIVEN

LCSET:

MOV

RO,007TLGC

$SAVE NEW LOCATION

LOCDSP:

MOV
NOP

(k0),RO

;GET DATA
;So next inst.

000372

BCS

HKBDGQ

sif we
sPrint

CALL

OCTSTR

sPRINT

sPrint a

does

time out.
"?" if we
1IT

not

execute

timed out

112702
004767
004767

000040

Movg

#S5PACEL ,R2

000226

PUTCHR

000210

CALL
CALL

GETCHK

$GET

120227

000015

CMPB

R2, #CR

:FINISH

BEQ

HKBDS

$YES,CLOSE

000060

CMPB
BLO

k2,270
4$

sDEPOSIT?
s8N0, CHECK

8HIS
CLR

hKBDG
RO

sNU,FORGET
sYES

CALL
BCC

GETNUM
1s

$GET REST OF NUMBER
sCR FOUND, STGRE NEW

CHPB
BNE
TSTB
BMI

R2,#LF
HKBDG
ODTFLG
HKBDG

sNot CR, must be LF
:Print error message
;If LF, cannot be register
s (Error exit)

001716

120227

103450
120227

CMPB

000070

103307

005000
004767

000262

103006

120227
001300

000012

105767

176404

100675

$T=-B1T FILTER.,

RZ2,%’8

The T=-BIT

space

sMAYBE!

can be

set

from

022761

171354

001021

1713%6

042700

177400

171362

005767

176404

171366

100402

171370

042700

167754

176372

1s5:

000020

;2562

CMP

#SAVPS,UDTLOC

the data

CHARACTER
LOCATION

LF
IT

the keyboard

sThis can either be useful tor debugging or disastrous.
3d0 it only if you first set FILT,.T In O.CNTL (BIT 15),
171346

after

VALUE

via QDT.
So,

sAre we dldadling the PS?

BNE
BIC
TST
BMI

3s
$4C<377>,10
0.Ch1L
28

;NOo, we’re not.
;PS 1is not a word.
:Is BIT 15 (FIiLY.T) SET?
;Yes, the filter’s disabled

BIC

$I.BIT,RO

sKILL

THE

sFall

thru

Filter

T=-BIT

to Priority

1K FIRMWARE
MACROODT=EXAMINE AND

MACRO

KXT11=AZ

V04.00

5«0CT=81

22:56:27

sPriority~7
sactually
sprotects
105767
100407
105700

176372

17140¢

032700

000%00
00004V

171420

001402
042700
010077

171424

120227

000012

171430
171432

001407

171374
171400
171402

171412
171414

253

100005

3s:

176322

000643

filter:

set
the

unless FILT.7

the PS to priority
apility to break,

(BIT 7)
7

vusing

in O.CNTIL
QDT

from

the

set,

you cannot

keyboard.,

T1STB

O.CNIL

sUUT control word

BM1
TSTB

3s
RO

300 nothing=filter
sIntenaed new PS

BPL
BLT
BEQ

35
#BIL6,RO
38

:Do nothing=Priority < 4
sCheck again
:Do nothing=Priority < 6

This

disablea

BIC

#B1TS,KO

sLGWER

THE

MOV
CMPB
BEQ

RO ,e0DTLOC
R2, #LF
58

sSTORE
:Go on
sSure,

NEW VALUE
to next location?
why not.

B00M

HKBDS

$GO TO

CHMPB

R2,#LF

318 A

BNE

HkBDu

$ NU,ERRUR

TSTB
BM1
MUVB
CALL
ADD
MOV

ODTFLG
HKBDG
#CR,R2
PUTCHE
#2,0D1LOC
ODTLOC,RO

215 REGISTER FLAG SET
2YeS, LK NUT PERMITTED
;TO LINE UP CURSOR
$SEND IT
sGET ADDRESS OF NEXT LOC,
$GET NEXT ADDRESS VALUE...

MOVB
CALL

$°/,R2
PUTCHR

sSEND A SLASH BEFORE..-»
?eseSHOWING THE CONTENTS...

LoCDsP

7eee0OF

PRUMPT

R RN

WNR
B

NN NN

ov-da

b o

SOV
D WN = C

171404

PAGE

DEPOSIT

171434

120227

171440

001237

171442
171446

105767
100634

171454

004767

171450
171460
i7146¢
1714172
171476
i71502
171506

112702

176302

062767

0ou002

004767

176254
000160
000057

004767

000014

000661

5§

000015
000042

016700

112702

482

000012

176260

CALL
BR

OCTISTK

ISSUED

eeeAND PRINT 1T
THE

LUCATION

KXTi11=A2

MACRUUDT-GET

FLRMWARE
AND

ECHO

MACRU

V04,00

5=UCT=81

22:56:27

PAGE

CHARACTER
+SBTTL
*

0900

R
o

ame

R R A

]

nacrouvI=Get
BN NN BN BN BN B

BN BN B

BN B

and

NN ]

R R A

CHAKACTER

INPUT

AND

R R N R R R R R

N R N

echo
[

character

DK BN NN BN BN BN BN N

RN NN R R R R R N N

R R S R R R R

N NN

0608
g

R RN

R N N RN N R R R R A

ECHO

SUBRUUIINE

[

v—-a

171510
171510
171514
171516
171522
171522

21 171526

22 171530
23 171534

24 171540

iri?
0990

R R T R R
R
R R A R

LSO

TSN

SECTOEPOESSPrae

2
s

Get a character from tne console keyboard and echo it back
exactiy as receivea including parity bits 1f any.
Return with
in

k2,

TP
I R

character

PR s
R R N

;

15
16
17
18
19
20

riil
2

]
2

N N RN

iR
IRt isiasRisisessvssvisivieis
R R
R R R R N R R R R R R R N R R RN NN R A R

eighth

bit

(and

high

byte)

zero.

GETCHR:

105737

100375
113702
'
105737
100375
110237
042702
000207

177560

177562

177564

177566
177600

ISTB

@#RCS5KS1

s CHARACTER READY?

BPL

GEICHH

sBRANCH

MOVB

@#RBUFS1,R2

s TRANSFER

Is18

@#XCSRS1

sPRINTER

BPL
MOVB

PUTCHR
R2,0#XBUFS1

sNO, TRY AGAIN
sYES, XMIT CHARACTER

Bl1C

$°C<177>,R2

sCLEAR PARITY

NOT

AND

KEEP

CHARACTER

PUTCHK?

RETURN

s CONTINUE

READY

TRYING

KXTi1=A2

MACRO

FIKMWARE

MACROODT=TYPE

ASCI1

V04.00

5-0C1=-81

22:56:27

PAGE

STRING

«SBTTL

macro0ODI-Type

ASCILl

string

R S

R R
T e

siis

R R R R R R R R R R R A R A R R A R R R R

iR iR

FRi

A R A R A R A A A A R R A A R R R R R

A R R A B

s iisririvsdiissistrssssceiscs
HH

MESSAGE

PKINT

SUBRQUTINE

37337
R

SRR RIS EINRRININIRNNINIRIRREIIINNIIRIINIIIIIISS
A

R R

SRR

RSN

12
13

3
;

ending
1s not

message

starting

with first
printed).

with

character

pointed

with eighth bit

set

(this

and

character

171542

c¢v-a

16 171542
17 171544
18 171546
19 171552
20

112002
100413
004767
000773

PUTSTR:

177750

sENTRY

MDVB
BM]
CALL
bR

(RO)+,R2
DONE
PUTCHR
PUTSTK

FOR CARRIAGE

:GET ASCII CHAR
:1IS IT IHE END MARK?
$NQ, PRINT IT
? MORE

RETUKN

22
23

171554

24 171554
25 171560

PUTCLF:

112702
004767

000015
177736

000012
17772e

MOvVB
CALL

#CR,R2
PUTCnR

sPRINT CR
sFALL THRU

#LF,R2

sPRINT

26
27

sENTRY

29
30

171564
171570

112702
004767

171574

000207

PUTLF:
DUNE:

FOR

MOVB
CALL
RETURN

PUTCHR

AND PRINT LF

FIRMWARE

MACRO

V04.00

5=0CT=81

22:56:27

N
W
We
Ws
%O
Ne

W
W8
@4
we
e

We
We
Wy
WMe

We
we
e

we
e

®e

we
-

“e
e

«e

weo

“we
we

w¢

ws
“e

%
-

“e

%e
we

-e

ws
e

W
.e

we
..

«e

“e
“s

“wa
e

W
we

we
~e

w9
o

g
we

“o

we
e

“eo
e

wo
e

we
e

ROUTINE

we
e

INPUT

w§

we
~e

“e

%e
“e

w8
e

weo

“e

TMo

Te
~e

“o
ws

we
e

digits

we
-

“e

we
we

“e

wus

ws
e

“e

“we

e
~o

“e

wo
e

we
we

%
We

We
W

N
WE

octal

WMe Ne Ve

WNE

macrouUbI-Get

NUMERIC

b
U
T

«SBTTL

exit,

the

“e

If the carry bit 1s
possibply a command,

carry

contains
pit

the

binary

clear,

set,

some

representation

<CR>

followed

other

the

number

entered

number

character

followed

the

ACCUMULATOR

number,

171576

171600
1716900
171604

CLR

;s CLEAR

CALL

GETCHK

#GET

cHpPB

R2,#CR

sCLEAR CARRY AND RETURN

BEQ

SRET

sIF

sus

#°8,R2

sCONVERT

NEXNUMS

004767

120227

177704
000015

001412

DIGIT
<CR>

162702

000070

Goz2ivd

VVUVVvViwv

WAS

ADD

nnanNnan

103007

#$°8=-"U,R2

TERMINATOR
TYPED

BINARY.eo

FeesAND TEST iF OCTAL OR

BCC

NOCT

$NOT

VALID

006300

ASL

FMAKE

ROOM

171632

006300
006300
050200

ASL
ASL

RO
RO

sDITTO
;DITTU

BIS

R2,R0

$PUT

171634

000761

NEXNUM

sGET

171636

000241

111040

000207

GETNUMS

NS R

171610
171612
171612
171616
171022
26 171624
27 171626
28 171630

ONENUM:

005000

DIGIT.

FOR

NEW

DIGIT

PLACE

34
35

171042

36 i71646
37 171650

062702

000261

000207

SRETS

000060

NOCT ¢

CLC

sCLEAR

RETURN

sCONTINUE

ADD
SEC
RETURN

$°0,R2

CARRY

sRESTORE

ASCll

7 o0 POSSIBLE
sCONTINVE

BECAUSE...

COMMAND

171576

Ev—-a

b e

b ek

TN COUX
G P
N=C X w

PAGE

DIGIIS

OCTAL

“e

MACROODI=-GET

“e

KXT11l=A2

KXT11=A2

FIRMEARE

V04,00

MACRO
bINARY

MACROODI=OCTISTR==TYPE

. 5=0CT=81

22:50:27

PAGL

ASCII

macroUDT=-0CTSTR~=type

binary

ASCIl

FRIFIVIGERIIININRNIIIIRIIINRIRISIRRNIRIIIIIRIIIIIIIRRILIIITS
FRPERRRRRRIRIIIRICIRII
IR IRRIRIIIIRRININIIINNRRIINNGIIIIEG;
i’
73z

U
s
b
b
b

P G ON

+SBITL

ivi’

NUMERIC QUTPUT

irii
FRIRIRERIIIRII

171652

004767

171656
171656

010046

171664

012746
005002

171660

171666
171670

rv—-a

kKO

171672
i71676
171702
171704
171706
171710
171712
171714
171716
171720
171722
i71724
171726

177676

R R R

Prints,

number

OCTSTO:

N N R
as

N
a

006100

5s:

006102

062702
004767
005316
001406

000060
177620

Firs

RRIRININRIRINIRIR

512
IR0

6=digit

R N R

octal

R N

integer,

the

N R RN R NN N

value

binary

PUTCLF

sNEED CRLF AT ODT ENTRY

MOV

RO,=(SP)

7SAVE

MOV

#6,-(5P)

sNU.

CLR

;OUTPUT

ROL

§SHIFT

MSB

INTO

ROL

ADD

#°0,k2

sMAKE

CALL

PUTCHR

7OUTPUT

DEC

(sP)

$COUNT
: DONE

VALUE
OF

CHARACTERS
HOLD
N

108

CLR

FNEXT

006100
006162
006100

ROL

sGET

ROL

7R2
sFIRST

006102

RUL

000762
005726

sCONTINUE

TST

(SP)+

sCLEAR

MOV

(SP)+,R0

7ORIGINAL

RETURN

;

]

TWQ
"

LSB
6N

DIGIT
A

BEQ

10s:

the

CALL

005002

012600
000207

RO,

OCTSTR:
000006

ROUTINE

CHARACTER

DIGIT
BITS
0

=®

COUNT
VALUE

INTO

oT[NT*Ru[a=lLOTOhNSC"[TTNNX'b][=4
o[Ton wN)oLIoS [=2+

ooTo11toSmnSNn["ono[[onTT (L[744]Y T1[[1Te[IINYTNNIY''[[[L[oTNTITTSN o5[[]]8e]}]+[)[|
LU LCIN 1)[
4oonn"o PfaSqTLSSyI[oPSnT €v0
tLOownuW*oou~ [1f1TYaNNE("LYLNN9 [=]e~]
IoOu-o.S T1N1N[LITS o[1 wov
ooLLoNoImnTNEoL*oooIT,UnmN (TLtTTONYaNNnLTLs[nL(SLITaI9
[IN' NS o[nINoN
nLL)TINETOSTNaN TAOn fTSuRnn fTSaN Lt1SLUaYnSTCILoSSNNnE
L[INTN TNn oo (TSN .
o[nNo [LITNNIITNS e

MACROUDT=UUTPUT

1K
FIRMWAKE

13 171731
14
15
171730

015

MACROG

012

V04,00

077

100

5=0CT=81

22:56:27

+NLIST

-LIST

PAGE

MSGs

+ASCII

1414

MSGS:

«ASCII

[eoTn'YS [os~a

+EVEN
BEX

LOoonuaTIoo-ASn ¥a Gn 6n L[(SOIhSNLCN*TTNn

KXT11=A2
MESSAGES

BEX

Soen

;
ERROR

;

FRUMPT

MESSAGE

nSOBfouNak,

MACRU

E1RMWARE

V04.00

WO
W

we
"

WS
N
WE

W
Ne
Ne

We
W

w8
-e

o
-

weo
e

W
-

TMo

“a
e

we
-~

W
-

ws
e

wo
e

we
e

N
.

w8
we

-«

W
e

-s

we
e

W
.

wa
“s

NWE

«s

we
e

we
-

TMme

“
e

weo

we
ne

»s

e
ws

we
-

e
e

we
wo

e
e

e
ws

Wg
we

we
"y

“wa
we

w8
e

we
“s

we
we

WO
wa

Ny
MO
weo

we
e

“e

w»

“e

We
Ns

Ws
W

Liagnose PPl in mode U with loopback connectors instailed.
Dilagnose SLU2 internal circuitry (maintenance mode)} and
SLU2 drivers/receivers (with external loopback connectorj.
List of

error

bit definitions

Q00100

«WORD

E.EXT

« W0ORD

E.INT

return to user.

ERRBIT:

171742

1711/42

000000

25
26

171744
171746

000002
000006

MODULE

LIAGNDOSTIC

000010

M
WS
We

Ne
RO
We
e
we
s
e

test

then external loopback

tirst,

test.

«NORD

XC.PBE
XC.PBE !

+WORD
«WORD

171750

Perform internal loopback

List of masks to put in XCSR§2.

s
7

XC.MNT

300 baud
300 baud and maintenance

INITS:

171750

252

000

List

;

All bits on,

Note:

PATERN:

pattern

last

BYTE

bytes

loop around,

alternating bits,

byte

must

377,

252,

all bits off.

+EVEN

171754
171754
171762

012737

000221

1762086

012737

000017

176206

171770

005000

DIAGNO:

+ENABL

LS&B

MOV
MOV

#MODE,@#PP,.CHR
#LEDOFF ,@4PP.CdR

CLR

Perform

parallel

171712

005001

CLR

171774

000405

port

AROUNZ

;7
:

set proper PPI mode= LED
must immediately be turned

0ft

assume

consequence,

success

diagnostic
wo

37
38
39

loop

pattern

97-d

O
E

171736

18 171740

b
U

«SBT1L DIAGNOSTICS-for SLU2 and PPl

FAGE

22:56:27

S-u(T-81

AND PPl

KXT11~AZ

DIAGNUSTICS=FUK SLUZ

SKIP

UVER

THE

ENTRY

POINT

KXT11~A2

FIKkM#ARE

MACRO

V04,90

5=0CT=81

22:56:27

PAGE

~N U BN

HARDWARE ENTRY POINT
«SBTTL
«=172000

172000
START:

1720609

172000
172004

000167

172004

000167

170254

JMP

PeRSUP

JMP

K¢ STKT

RESTAK:
S

170026

HARDwARE ENTRY

POINT

KXT11=A2

F1RHWARE

MACRO

V04.00

5=0C1=81

22:56:27

PAGE

«SBTTL

B1S

¥k .PAK,

s08B

Ri,

Perform SLU

18§

it out port

port

set

error

flag

for

all

else
loop

R2=>error
R1

ignore

R4=>initial

init XCSR
branch 1f

done

R2=>next

error

012702

171742

MOV

0127901

176540

MOY

016140

000002

MOV

$ERRB11, R2
#RCSR$2, R1
2(kl), =(SP)

172044

012704

MOV

#$INLTS,

172050

014461

171750
000004

MOV

=(R4),

4(k1)

172054

001436
005742
viz27ie
012703
005605

BEG

118

TST

000010

171750

4s:

=(K2)
#8., (5P)
#PATERN, K3

58¢

CLR

init

105761

000004

683

I81B

100402

BMl

loop pattern around
branch 1f ready

88532

105711

TSTB

(R1)

100402

BMI

938

S0B

RS,

000413

10s

CMPB

2(R1),

BNE

10s

ISTB

(R3)+

000002

112130

105723

172132

V01350

BNE

172134
172136

005316

DEC

001744

BEQ

172140

062761

172146

000740

172150

051200

172152
172154
172160

Vus728
1774172

176516

(k2),K0
(sP)+

CALL

BR
g

$#10,

ADD

BIS
TST

We
NE
W

branch

4(R1)

yes
no,

0CTSTO

JMP

KBbs$

«DSABL

LSE

i1f

pump

ready
timeout

counter

timeout

come back 0K?
no, set error bit & exit
done all bit patterns?
yes,

000167

000004

(R3)

branch
else

004767

000010

126113
001010

initialize timeout counter

172122

timeout

6(R1)

077503

172126

(r3),

CLK

counter

p11]

MOVB

flag

counter

timeout counter

71s:

000006

temp

value

pranch

Wwe

111361
005005

172110
172112
172114
172118
172120

make

XCSR

timeout

172104

garbage,

else bump

SUB

flags

SLU2

(sP)=baud rate
R3=>patterns

077504
000422

172100

172102

MOV

1720064

i72070
172012
i72076

MOV

“wa

172056
i72060

172030

2 dlagnostic

172034
1712040

valuyes

send

check input in
branch i{f same

BEQ

283

@¥PP.B

voooul

RiPP.A,

052700

077110

K1,

001402

MOVB

CMPB

183

176200

176202

123701

110137

i72v010
172014
172020
172022
172026

DIAGNOSTICS=Continuea

AROUNZ:

172010

B R DB P WWWL LW WWWWANRNKNNNNKNRKNR
S e
s
BRUNRCETLO T RLNE OCEENC P RUNBSCOCEE-0 U H
N CE

BB
TV

8¥v—-da

DIAGHOSTICS=CONTINULD

set

doneé
to

all

bauds?

baud

error blit
rid of temp
print error flags
and just get out,

rate

format

(RT=11

Since entry is effected
character (D, X or i).
floppy

sequence

boot

Attempt
disk,

W
Ve

Ny
N

N$
Ne

WO
e

w
a8

we
«e

we
we

we
e

w8
e

e
-

weo

We
e

W
g

we
we

we
~e

W
e

W
-

-y

we
e

",SAV"estructured

bootstrap

we
~o

bootstrap program designed to handle floppy
either our standard bootable format or in

Tne

'wo

wo
~o

weo

-y

«s

“e

“wo

-8

weo

“e

“eo

short

cassettes

volume

W
-

w-e

W
e

W
.y

we
e

W
e

weo

we
~a

WO
N

-e

“a

~-e

we
e

we
«s

“e
e

“e

“n

wo
we

“we

wa
“-

“e

wo
“o

-e

wo
-

“s

N8
o

-y

Wwe

“e

We
We

MODULE

N
W
W

We
Ne

W
We

«REPT

BOUTS=-Description

BOOTSTRAP

0ouQoQU

This
tare

6¥-d

PAGE

«£2:56:27

5=UCT=81

V04.00

«SBTTL

CX~NOGTT
P W

MACRU

KXT11=A2 1K FIRMwARE
BOGTS=DESCRIPIIUN

1ls

files),

follows:

by typing D in response to ODT prompt, get next
Get optional device number next (default is 0).

selected:

read 512 bytes

starting

disks or TusSs8
the stand=alone

from

0 at

from specified unit of

logical

the

block

density of

zero,

the

into

medium

the floppy

memory

present

locations
in the

drive at the time.
b.

the drive

medium,

back

not ready or
to

does not contain a bootable

0ODT,

It TuUu58 boot 1s selected, read the first
drive into locations starting at 0,

the

first

using

block

from

the

selected

first byte read into RAM 1is 240 octal, jump to it.
If the
is 200 octal, execute the stand-alone volume loader,
the selected device as input,

byte

+ENDR

177170
177172

06-d

26
27
28

2Yv

100000
040000
030000
004000
003000
000400
000200

000100

000040
000020
000016

000001

1771170

RxDB=

RXCS+2

000001

34
35
36

000v03
000005
000007

37
3¢
39

000011
000013
000015

0oLo17

000400
0UV200

000100

000040

U00020

000004

000001

RXS$SSIN=
RX$s5XA=
RX§$02=
RXS$S§Xx=
RXS$SSDE=
RXSSTR=
RXSS1E=

sError

sInitiallze controller
sExtended address bits
31 1f RX02; 0 1f RXO%
sUnused bits
:Density (i1=double 0=single)
sTransfer function
sinterrupt enable

040000
030000
004000
003000
000409
000200
000100

sbone

RX$SDON= 00GVO040

RX$SUN= 000020

sunit select

KX$8G0= 000001

sFunction seject

RXsskhn= 000016
(in RX$$FN)

RXSFIL= 0*2+RX$SGO
RXSEMP= 1¥2+4RX$SGOU

with GO bit preset

sF11l buffer
sEmpty buffer

RXSWRT= 2¥2+KX$5GO0
RXSKRED= 3*¥2+KX$SGO

sWwrite sector
?Read sector

RXSRSTI= S5*%2¢RXS$SGO

sRead status

RXSKEC= 7¥2+RXS$S5GO

sRead error code

RXSSTD= 4*%2+4RX$$GO

RASWDD= 6¥2+KXS$S$GO
RX

krror

:Set medla density

swrite sector with deleted aata

RXESDN= 000040
KXESDE= 000020
RXES1L= 0000V4
RXESCR= 000001

sUnit selected
;brive ready
;veleted data
;Drive density
svensity error
sinitialize aone
;CRC error

Miscellaneous Definitions

000010

Codes

RXESUN= 000400
RXESDk= 000200
RXESDL= 000100

;Data Buffer

RXS$SEkK= 100000

:Control and Status

NE
WO
e

RX Control and Status Bits

s kX Function Codes

3
32
33

44
45

W8 NE

e
e
W4
We
W

-y

W
e

Mg
we
-

W
We
W
-

W
we

wa
we

ws
-e

we
»e

w2
e

W
e

wa
ue

w8
ne

we
s

was

w¢
~e

we
ne

-e we

we
~

we
“e

we
“«s

“e
wo

N
e

we
«e

we
~e

TMma

-e

wp
e

“we

LTI

“a

“s

weo

we
-e

“y

LTI

“e

wme

“e

we
we

wa
we

(RXV11,RXV21)

RXCS=

18
1y
29
21
22
23

RXU1/RX02

~e
-

w9
o

we
we

e
w

“e
“s

we
we

N
MO
e

+SBITL BUOIS=RX Controller Definitions

9
10

14
15

“eo

-e

we
e

we
.s

i2
13

BY BOUOTSTRAPS

EQUATES USED OhLY

N
we

W4
W

W
N

We
We

6
i

3
4

PAGE

22:56:27

5«0CT=81

V04,00

MACRU

KXT11-A2 1K FIRMWARE
BOUTS=DESCRIPTLIUN

RETKY=

:Numbelr

retries

+SBTTL BOUTS=TUS8 Definitions and Protocol Equates

KXT11=A2

BOOTS=TUS8

FlKkMWARE

DEFINIT1UNS

MACRO

AND

Vv04.00

PROTUCuL

5-0CT=81

223562327

PAGE

48=1

EQUATES

;

Apsolute

address

000002

FILNAM

000002

001000

VIRBUF

001000

definitions
sAdaress
?

f£ilename

program

;Start of 512, word buffer used
; for RT=11 directory operations
7
in stand-aione loading

definitions

TISCSR

RCSRs$2

;UL

T1sBEEK

KBUFS$2

176544

TOSCSk

XCSks2

TOSBFR

ASUFS2

;UL receiver data buffer
sDL transmitter control and
:DL transmitter data buffer

TUS8

Kadial

Flag

Byte

RSSDAT

Serial

;Control message
sInitiallize flag

“B<00U010>

~B<00100>

000020

RSSCON

000023

R$SXUF

~B<10000>
“B<10011>

packet

RSWKIT

000004

RSCUMP

L[ O L O

000005

RSFOS1

000006

RSABRT

000007

RSUVIAG

000010

RSGETS

IO L

000011
000012

R$SLTIS
RSGETC

000013

RSSETC

000100

RSEND

END

RSREADL

000003

RSHOP

RSIMNIT

1.
2,

and

message

sContinue

» XOFF

operation

codes:

slio=operation
sInitialize
sRead

operation

swrite

4.
5.

sCompare

operation

(NOP

TUSB)

sPosition operation
sAbort (NOP on TUSS)
sDiagnose

6.
7.

O
T
I

10,
11.

8.
9.

~“B<01000000>

packet

flag

success

status
status (NOP on TUS58)
characteristics
characteristics (NOP on

;Get
sSet
7Get
;Set
s *END

codes:

SSWNURM

;Normal

SSRETK

sSuccess

but

177776

SS$PART

-2,

1777170
177767
177765
171757
177740
177737

SSUNIT

-8,

sPartial
;Invalia

operation (end
unit number

success

SSCART

-9,

tNo

SSwPRrRT

-11.

sCartridge

SSDCHK

-17.

SSSEEK

-32.

SSKECHN

sMotor
=48,

«SBTTL

8UOLIS=kT11

Definitions

with

retrles

check
error

write

medium)

protected

error
(block

not

stopped

sInvalid

operation

;Invalia

record

and

cartridge

sData
sSeek

SSMUTK

177711

TUS8)

message

000001

SSUFCD

status

flag

000000

171720

status

codes

sData

R$SCTL
RSSINI

Go0000

control

Definitions:

000002

000001
00vo02

Protocol

receiver

“B<000OL>

000004

Control

for

176542

000001

Address

RADS0

176540

i76546

114

TUS58

stand-alone

Equates

code

number

found)

BOUTS=RT11
115
118
1117

118
119
120
121
122

MACROG

v04.00

5=0CT=-81

}

0010vV
001002
001004
001000

R1-11

sNumber

segments

;Number

HGHSEG

DIKBUF+4

sHignest

ATKBYT

DIRBUF+6
DIRBUF+10

sHumber

127

001000

ENMPTYS

129
130
i

004000

000400

128

002000

PERKF'S

7%2
10
6004060
u01000
002000

ENUSGS$

004000

D FLEN
IENTAS

;

RI=11

ystem Communications

132
133
134

000040
000042

RTSSTA

000040

RIS1SP

i3s
i37

138
139
140
141
142

000044

RISJSH

000042
000044

000040

RTSUSR

000046

000050

RTSHGH

000050

RISEmMT

RTSUER

000052
000053

RTSRMN

000054

RTSFCH

000056

RTSFCT

000057

000052
000053
000054
000056
000057

betinitions

UIRBUF

ENTS1Z

1206

Directory Structure

DIKBUF+2

00U01o
000010

i3ds

PAGE 48-2

MNXISEG

STRBLK

124
125

22:56:27

SEGALO

001010

123

¢s-=a

FIRMWAKE

DEF1INITIUNS AND EQUATES

KXT11~-A2

segment
ot

allocated

loglcal
in

extra

bytes

:Starting olocks for
$ in this segment
$5ize

segment

use

directory

per

entry

files
entry

:0ftset to file length in entry
;Flag for tentative file entry
sFlay

for

s¥lag

for permanent

empty

area

;Flag

for

end nf

entry

file

segment

Area Definjitions
program

;S5tart address

for

sInitial

pointer

;Job
s USR

stack

status word
Jload address

sJob high memory limit
;(Byte)
:(Byte)

EMT error code
User error code

;Base address of resident monitor
s(Byte) Console fil1l character
;(Byte) Console £ill count

KXT11=A2

FIRMWARE

MACKO

VU4,.00

5=0UC1~81

22:56:27

PAGE

BOUTS=FROGRAM ENTRY POINT

N
W2
N6
We
WS

WME
N
.

e
N

Wa
e
.

W
Ne
©

Ve
.

FsEPIROYOEFISLIOSIPTYEIYPVUIRIRY

[

INTERPRETER
-

COMMAKD
o

AND
.

[

CrYTVRIIFIIFFYRETIPIZIVC
VY

€

[

€

INITIALIZATION

«LK

we
e

we
-~

we
e

we
..

point

LTI

-e

W
e

entry

“o

we
wo

e
e

T
LR

weo
w

we
-

BOUTS=-Program

“n

“a

we
e

we
s

we
e

wo
e

e
¢

Wwe

bUOTSTRAP

O
C Xt

U N

«SBTTL

rovrrsrer

""I"';l"l"'lI""l""’l'"'l""""""I'll"i"'l;"
R NN E

A °D’ was entered in response to the
here and expect ‘D’,’X" or ‘Y’ next,
unit

number.,

set

bits

OuT prompt,
tollowed by

B.,CNTL

]

SO we get
a CR or a

follows:

-y

[ E

TUSS
RX01/02

=
=

0
1

Used

BIT

read routine.
02

Device

stande=alone

volume

loader

select

proper

number

Note: if
called

£s-ad

8IT

25 172164
26 172164

no memory was
"NO.LOW"TM will

found at 000000, bit 15 of B.CNTL,
be set and the bootstraps will be

disabled,

BUOTS::

012737

000072

MOV

170544

#1UBAUD,@#TOSCSR

;Set

TUS8

Baud

Rate

;s Jump here with OUT if booting TU58“s at other than default baud rate
30

172172

STTUBD::

010667

175566

Mov

SP,IN.USR

sPermit
s

33
33
35
36
37
3d
39
40

17217
172200
172204
i7221v
1712212
172216
1ij2222
172224

005004

172230

001402

172232

172236

0047067

177240

172242

022702

000015

46 172246
47 17225
48 172254
49 1712256
50 172260

004767
120227

001412
012704
020227

177304

000200
000130

001405

020227

is:

CALL

GETCHK

sKeyboard character

BEQ

;R4

MOV

#DEVBIT,R4

3R4

Cup
BEQ

K2,#°X
1s

sDX = KX01
;DY = RX01

or
or

DMA,

K2,#%#°D

ABORT

<Illegal

CALL

device

is clear
pit 7 is

sitles,

3Get

#15,R¢

+1Is

sCR

means

#°0,R2
38
R2

sYup.

005302

SuB
BEG
VEC

sbrive

1?2

V01402

BEQ

7Y¥es,

skip

ABURT

<Illegal

283

INC

sFor

unit

383

MUVB

R4,B.CNTL

;Set

device,

TST

B.CNIL

slest

NU.LOW

BPL

swe

000060

174262

172266

005204

54 1722790
55 1712274
56 172300

11v467

175474

005767

175470

100002

device

;0rive

unit

for
set

for

RX02
RXv2,

DX,

the code’s

non=DMA

name>

GETCHR

162702

in R2

the same= it knows both den~

BEQ

001405

B.CNTL here

:DD = TUSB cassette

RZ2,#°1Y

BEQ

new

non=zero

sAssemble

CMP

001410

and BREAKS

IN.USR

CMP

000131

HALTS

making

CLR

CMPB

000104

number

CR?
arive

the

ABURT

number>

;we

unit

information.

have

low memory
don’t, so go to

UDT

KXT11=A2Z 1K
HALI

~me==>

MACRU V04,00
5=0CT~81 22:56:27 PAGE
FIRMRARE
PC=172204 InDICATES "“ILLEGAL UNIT NUMBFER"

ABORT

012737

172370

000004

012737
000005

000300

00000ve

memory,

can‘t

rpoot>

device

primary

them

4s:

bootstraps

and

(see

can

get

CHK240,

the

information

MOV

#BALUBCOT, 644

t1f

MOV

$PRIo,E#b

sinitialize

KESET

the previous instruction also
perform a long initialization

wnhich

1s
is

Note:
which

automatic

order
it.

boot

need

we time out,

sFor

necessary in
desired from

they

now,

se want to re=

everything.

init.

the

bus.

screws up
sequence,

some
such

devices
as RX02’s,

The

long

delay

from

drive

assure

drive

ready

172324
172336

012706

167644

DELAY
mov

RO,R1,9.
#SSTACK,SP

sDelay z seconds
sInitialize the stack.

172342

010667

175430

MOV

SP,TRAP4

sSet
sby

trap=-to=4

making

TRAP4

#37776,(SP)

sSome

R4,R2

; address here, so
sBoot control word

BIC

$*C<DEVNUM>,R2

;Want

only

unit

no.

iIn

010246

MOV

R2,=(SP)

$And

we’ll

save

too,

172362

105704

ISIB

;Bilt

for

172364
1723866

100405

BM1

KXBOOT

2Go

floppy

TUBOOT

:Go

TUS8

172354
172360

042702

037776

17771176

000436

172370

iiz2370
i712374

boots

set

need

emulation
non=zero

MOV

012716
010402

167644

MOV

#SSTACK, 5P

ABORTYT

<Unexpected

sRestore

timeout

during

poot>

the

memory=top
8k will
here

RX01/02
boot

boot

BADBGT:
012706

below

boot

ROV

172340

172352

and

passed

below),

172314
172322

lOw

172306

<NO

Before proceeding, we set up the bus timeout trap vector, enable
we do a delay (see
trap to 4 emulation and reset the bus.
explanation below) and set up the stack so the stand=alone booter

172302

7G-a

49-1

stack

KXT11=A2

FIRMWARE

MACKO

BOUTS=RXUI/KX02 BOOTSTRAP

V04.00

b5=0CT=81

£2:56:27

PAGE

+SBTTL

BUUTS=RX01/RX02

Bootstrap

2
3

SRR ITINNIIINNINIiNERNIIRIINNIINININIGISNLINIRIIIIVIIZRIILL
S

PPN IRNIIRIINRIIREIIILIIIIIRRIIINIIIIIIIIIIINISNLIIIIISIZS

2827

HE A

iri:

PREIINIININIINIININIIININIIIIiaNiiisiiiiiiisrenits

F PRI T PR

HHHH

FLOPPY

BUUTSTRAP

i
H

R e T RGP R VTSP

P TrI T Iresrsir i riisediessrivsiets?

Inls

;

media mounted

S6-d

13
15
16
17
18
19
20
21

172400
172400
172404
172410
172412
172416
172420
172422

012746
005737
000240
012701
005000
005004
004767

177170
177170
001000

000402

RXBOUT:

routine

MOV
TST
NUP
MOV
CLR
CLR
CALL

will

bootstrap

that drive,

#RACS,=(SP)
@ #RXCS
#512.,R1
RO
R4
DREAD

either

floppy

drive,

the

density

;veed floppy CSR for CHK240
;1f not there, time out via 4
;to ST173 and reset the world
;Byte count
:Starting block number
:RAM bufter address = 000000
sLOAD IT ALL IN

the

KXT11=A2

FLIRMWARE

MACRO

V04,00

5=0CT=81

22:56:27

PAGE

B0UTS=V1STINGULSHING TiPk UF BULUT BLUCK
bl

+SBTTL b001S=Distinguishing type of boot block

PRIIIRRIIIIINIRININIININIGINIRNIINIIVINIIIINININIIIGIIR:
R R
R R N R R R R N N R R R N
R R R R R R R R N R R R R R R R AR R AR N RN

iiii
HHHH

DISTINGUISh STANDARD FROM S1AND=ALONE FROM
NUN=BUOTABLE

VOLUMES.

iiiv

$iii
;ivs

“e

iiid
i¥is
R R R R N R N N R R N R R R S N R N RN R R R R RN R RN R R
R R R S R
PERINIINININIIINNIIINIRIIIIIISNINIVIIIIGNINIIVIIINIIVIIVES

NN NN R N N -t b e ot b s b b
~NGC
-~
U DN OCET
T BN = WX

9¢6-a

iri:

The ChHK240 routine will repeat powerup seguence 1f location (0 does not

contain a valid secondary pbootstrap (i.e., does not have a 240 or 260
It starts execution of the booted program if there’s a 240,
and goes to the stand-=alone program loader if there®s a 260.

CHKZ240:

172426

:Did we read a valid bootstrap?

$240,@80
is
$260,230

000240

000000

CcMp
BEG

022737
001447

000260

000000

STANDB

;Stand=alone

004767

1757066

CMP
BEQ
CALL

VECSET

skestore

ABURT

<No

MOV

172426
112434
172436
172444
172446
172452

0227317
001419

boot

172456

012601

172460

012600

Mov

(SP)+,R1
(SP)+,R0

172462

005007

CLR

1s:

plock

volumes

wiped=out

start

vectors

volunmed>
sUnit

CSR

address

sUnit number
:Standard secondary

boots

with

260

KXT11-A2 1K FIKMWARE
BO0TS=-TUSE

MACRU V04,00

5~DCI=-81 22:56:27 PAGE 52

BOOTSTRAP

+SBTTL BUOTS~TU58

Bootstrap

3
4

R
R R R R R R R R R R A R R R R R AR R R A R A A R A R R R A A A R R A A R R R R R R R R R R AR A A 2
AR
R A A R R R R R R R R R A A A A A R
A R R R R R R A R A A R R R R R R AR R A R A R A A

5
)

iiis
25

§
?

R A AR R A A A R R R R R R A A A R R A A AR R R R R R R A R A R R R A R R R R R R R R R A A R A R R R R R
$SINNNRNNIIINIIINIIIIIIIIILIINIIIEIIIIIIIRINIIIIIIINRNRIEN

172464

13 172404

012746

176540

17 172500

004767

001132

14 172470
15 172474
i6 172476
i 172504

LG-a

19 172506

012701
905003
005211
105711

100376

20 172510
21 172514

042711
012703

23 172520

004715

22 172510

23
25
206
27

172522
1725924
172530
172532

28 172536
29 172540

004

005741
105737
100375
121127
001402

183

176540

+ENABL

LSB

MOV

#$TISCSR,=(SP)

s CHK240 wants TUS58 CSR

CHBOUY

:5end eight NULLS

31If PL no - wait

MOV
CLR
INC

#TUSCSR,R1L
R3
eR1

TSTR

@8R1

CALL
BPL

«BYTE

004

283

000020

$XC,BRK,@R1
(PC)+,R3

112560

005000
012701
004767
100323

001060
000212

3s:

sR1 => output CSR for TU5S8 serial line
sSet R3 = 0 (Two NULLS)
sStart transmitting BREAK to TUbS8
;1s transmitter ready again yet?

RSSINI,KSSINT

sElse stop sending BREAK now
;Get two INIT commands for TU58
:And transmit them
sDump any garbage char in TI$BUF
;Is character available from the TU587
:1f PL, no = wait in loop
;If so, was 1t a CONTINUE flag?

CALL

8RS

BEQ
ABURT

sIf EQ, yes= go ahead
3s
<TUS8 initialization error>

TST
TSTB
B8PL
CMPB

=(R1)
@¥TISCSR
28
@R1,#KS$SCON

: TU58 is now initialized.

172544
172546
172592
174556

Piis
HE
sii’

BIC
Mov

000001

33
34
35
36

TUBOOT:

176544

TUS8 LAPe CASSLTTE BOOTSTRAP

CLR
MOV
CALL
BPL

RO
£#512.,R1
KEADZU
CHK24U

+USABL

LSB

ABORT

Prepare to read block #0,

;Block number = 0
;dyte count = one block
tAttempt to read the block
21t PL, read was successful

MACRO

V04,00

5=0CT=81

22:56:27

PAGE

BOOTSTRAP

W N
e
W
WS
W
s

We
W

V3
Be

N2
W

W
%o

Wy
W

We
Ny

We
s
we

we
we

“e

"o
we

“o

ATIR

“e

we
we

mp
.

we
e

e
s

weo
e

“ws

o
we

we
“e

9
we

1)
LTI

W3
we

“e

LTI

we
-.s

“e

weo
e

“wp

“e

W
e

we
~

routine
format)

Wa
e

We
We

we
e

“

pootstrap

BOOISTRAP

loaas stand-alone programs (assumed to be in RT=11 «SAV
from an Ri=11 fjile structured 1USH8 cartridge.
It is

invoked 1f the tirst word in block 0 of the cartridge is a 260,

STANDB:

172564

012700

172570

006300

1725712

022020

000001

1s:

MOV

#1,Ku

;8et

directory

ASL

7Two

plocks

CMP

(RO}+,(RO)+

sAdd

8¢—-d

we
e

we
ws

ws
.

W
s

was
-a

we
“s

~~e

We
s

W
s

-y

wa
we

ws
we

w»

Wp
we

We
e

This
flle

W
N
We

volume

WS
NS
W

We
W

VA
We

WE
We

172504

WNE
e

O W
G
CHAG
w

¢+
;

BJUTS=Stand=alone

STAND~ALONE=VOLUME

- N

«SB1TL

VOLUME

FIRMWARE

KXT11=AZ

BUUTS=STAND=ALONE

segment

per

RO,

segment

directory

172574

012701

002000

MOV

#1024.,R1

;Prepare

172000
172604

012704
004707

001000

MOV

7into

the directory buffer

tRead

tne

172610

100002

BPL

#$DIKBUF,R4
READU
28

ABORT

<Dilrectory

MOV

#S5TKBLK,R%

000162

CALL

172612

172616

012704

172622

012400

172624

010403

172626

032724

172032
172634

V01010
022744

172640

001015

172642
i12646
172650

013700
001350

001010

3s:
002000
004000

MOV

(R4)+,K0

MoV

R4,K3

s1f
read

PL,

read

blocks

segment

read

was

prepare

successful

tElse

pick

;7 starting block
7RO = starting block for tiles
7Save pointer to current entry
:1s this a permanent file?
:If bit set, yes =~ check if it matches
7Else is this tnhe end=ofe=segment

B1T

FPERMES,(R4)+

BNE

CHP

FENDSGS ,~(R4)

BNE

;I1f

MOV

d¥NXTSEG,RQ

BNE

tElse get number
3If NE, there is

ABOKRT

<f'ile

not

two

error>

001002

marker?

NE,

skip

this

found>

172654

01270%

MOV

#FILNAM,RS

022425
001004

sPoint

CHP

(R4)+,(R5)+

;Check

file

BNE

5§

022425

cup

(R4)+,(KS)+

001002

BNE

s1f NE not desirea file
J.sosCheck second word of

001410

172674

010304

172076

062704

45:

022425

562
000010

entry

of next segment
one = Qo reaa it

iiz2e6v0
172662
172064
17206066
1726170
i72672

000002

starts

1In blocki#o

CMP

(R4)+,(R5)+

BEQ

LOAD

MOV

R3,Ra

RADS0

name

name,

first

desired

file

word

filename
s1f NE not aesirea one
7...Finally, check extension
s1f EQ, got it - go load this

one

seet

into memory
entry

polnter

back

1712102
1712704
172700

062400

ADD

*D,FLEN,R4

sAdvance

ADD

022424

CMp

(R4)+,RO
(R4)+,(KkK4)+

ADD

6#XTRBYT,R4

172712

000744

sUupdate current file base
sAnd sKip to next file entry
sPlus any extra bytes in each entry
sContinue file search

063704

001006

file

size

entry

KXT11~A2

MACRO

Fl1RMwARE

V04.00

5=-0CT=861

22:56:27

PAGE

S0UTS=LUAD STANU~ALUNE PROGRAM FILE
+SBITL

P
3

4
s
6
/I
8
9
10
11
12
13
i4

172714

iizite
172720
172722
1727126
112730
172734
i72740
172744
172746
172752

15 1727%2
16 172754
17 172756

18 172762

i9 172766

-d

172770

22 172770
23 172772
2% 172776

011401

000301
006301
004767
100002

013705
032705
001402

LGOAD:s

Program

File

BPL

ABORT

<Stand=~alone

MOV
BIT

G#RTSSTA,RS
#1,K5

BEQ

STARYES

ABOKT

<fllegal

MOV
Movs

(SP)+,R1
(SP)+,R0

sPass tne CSR address
sGet unit number bpooted

MOV

@#RT$1SP,SP

s;Load program’s

CLR

TkAF4
eKS

sDisable trap to 4 feature
$Go start program execution

R4
4(SP),R2
ARUUN3

sLoad at 0
2Get unit number
s SKIP OVER THE ENTRY

CALL

000040
000001

Stand=Alone

eR4,R1
k1
Kl
READZU
1s

MOV
SWAB
ASL

000042

BUOTIS~Load

iRl = size of file in blocks
s * 256, = word count
; ¥ 2 = byte count
;kead the program file into memory
71f &1, error in read=ABORT
file

read

error>

;Get program start
71s adrs even?

adrs

;1f EQ yes = okay
transfer

address>

STARTS:

012001
112600
013706

00%067

00VV115

000042

175010

JMP

stack pointer

READZU:

005004
016602

000407

Q00004

CLR
READU:

MOV

POUINT

EWTRY

09-d

C X~ Tl N

1Kk

1730006

[

KXT11=A2

MACKDO

FIKMWARE

V04,00

5=0CT=81

22:56:27

PAGE

POINT
«SBTTIL

173000G

ENTRY

POINT

«=173000

173000
S11733:

173000
173000

10044/

173004
173006
173010

LVET

173012

V00167

00034y

NTPS

#PR17

RESET

005009
077001

sCan’t
;But

CLR
S08

RO
RO, .

JMP

PARSUP

anything

usually

here.

does,

sUELAY tor the sake 0f DLART.
s(Maint, bit cleared by RELSET
sjust

175242

assume

PWRsUP

little

too

long).

KXTil=AZ

FI1RMwARE

MACRO

Vv04.00

5-0CT=81

22:56:27

PAGE

bSo

19-a

SR
S

BOOTS=CONTINUED
«SBYTL

BUOTS=Continued

173018

i7301e
173022

173024

105767

100402

000167

174740

000370

TST8

B.CNTL

bil

DREAD

sBit

JMP

TREAD

sRead

set
from

for RX01/RX02
tape

FIRMWARE

MACRO

V04,00

5=0CT=81

£2:56:27

PAGE

READ RUUTINES

we
We

Wa
We

Wus

W
We

We
we

“e

“eo

we
e

We
e

“e

weo

"ne

wue
ny

we
-

weo

we
ws

-e

“o

-y

“o

W¢

we
e

we
~s

we
s

we
-

“eo
we

o
~e

weo

“e
e

e
e

we
~e

wo
e

ROUTINES

READ

w8
we

wa
e

we
-

.
e

“e

“eo
we

e
LT

w»

-e

we
-e

W
e

-y

Wwe

-y

“e

we
~e

“wa

LTI

we
e

w4
..

we
e

“e

-y

wa
-e

we
e

“e

-e

weo
ne

“s

W
e

W Ny

D1SK

RXV11

Programmed

I/U0

RO:

Starting

block

numper

transfer.

with registers set up as below, read the appropriate number of
full sectors from tne floppy, at either density, with either
OMA or

kK1:

Byte

®Z:
K43

Unit number
Aadress of buffer

RXVZ21l

intertace,

routines

WO
ws

We
we
"

Reaa

DU o
~
O

FLOPPY

e =

«SHTTL B001S=RX01/RXU2

KXT1l=A2

BUUTS=RX01/KX02

173030

010446

173032
173034

010046

LSB
MOV
MOV

V10146

M0V

<ENABL
DREAD:

;

for

transfer

recelve

data

R4,-(SP)
RO,=(SP)
R1,=(SF)

sSave pbuffer address
sSave starting LBN
;Save pyte count

Check status and media density of

selected drive

006002

MOV
CLR
ROR

¥RXDB,R1
RO
)2

103002

BCC

BIS
JSR
«WORD

#RXSSUN,RO
RS ,RXGU
RXSRST

;Set unit 1
sStart a read status operation
7 to determine status and density

MOVB

BR1,r2

sPick

ABORT

<Floppy

BIT

ERXESDN,R2

:Check media density

BEQ

s1f

173036

012701

173042
173044
1730406
173050

005000

177172

052700

000020

1730%4
173000
173062

004567
0u0013

000312

173064

100402

i73006
173072
17307e

032702

1s:e

111102

BMIL

000uV40

283

173100

Ub2700

173104
173106
173110
173112
itaiaa
173120

012602

we
we

Double

001411

Sector

vou3v2

012603
006303

012704

000200

173122

012602

173124

000302

sector
count

set

;1f Py,

drive

not

low

unit

byte

status

drive not ready

ready>

EQ,

single

density

number

byte

loglical

block number *

count/256,

(SP)+,Rr2
RZ
(SP)+,R3

;S5et aouble density

ASL

sMultiply

MOV

$128,,R4

:Words

per

number

#RXSSDE,RO

Single

Logical
Sector

3s:

MOV
SWAB
| o)}

000410

;Bit

BIS

000400

sSet up R1 tor benefit of RAGU
sInitialize current unit/density word

density.

Logical

-s

¢9-d

count

s8yte count
:Divide by 256
;LB
by

sector

density.

sector
count

number
pyte

loglcal

block

count/128.

MOV

(SP)+,R2

sByte

SWAB

sDivide

count
py

256

In command

KXT11=A2 1K
~=was> HALT

MACKU VU4.00
5-0CT=-81 22:56:27 PAGE
F1lKMwWARE
PC=173070 I8DICATES "FLUPPY DKRIVE NOT READY"

173126

005302

ASL

173130

012603

MOV

(5P)+,K3

173132
1/3134
173130

006303

ASL

006303
012704

ASL

Rr3

sKultiply

MUV

#o4.,R4

sWords

per

sector

G(SP)

CK as folilows:
Logical Sector

per

sector

Set

2(5P)

= Sector count

;

4(SP)

words

o(SP)

Buffer

;

;And
s LBN

per

Number

sector

address

173142

010446

MOV

R4,=(8P)

;Words

173144

010240

MOV

R2,-(SP)

;Sector

173146

010346

MOV

R3,=(5P)

sLogical

Sector

Number

;Start a

sector

read

173150

004567

173154

000007

483

000216

Start

This

5s:

7
173156

011603

012702

000010

022703

006400

R5,RXGO

«WORD

RXSRED

171400

006103

Physical tracks and
;Get

sectors.

Logical Sector

Nunmber

.10}

$8,,R2

sLoop

count

CMP

#26.%200,R3

sDoes

BHI
ADD

s
#=26,%200,R3

sBranch if not, C clear (BHl => BCC)
sSubtract 26 from dividend (C set)

nUL

:Shift

DEC

jLecrement

MOVB

k3,R2

CLRB
SwAB

R3
R3

sCopy track number
:Remove track number

into

dividend

dividend?

and

guotient

173200
173202
173204
{13200
173210
i73212
173216

005302

Cup

$#12.,R3

006103

ROL

173220

000302

ASL

113222
113224

060203

;bouble the track number

ADD

R2,R3

060203

1i32206
173230

ADD
ADD

R2,KR3
R2,K3

;Skew the sector
by adding in

060203

V6202

ASkR

78:

Numbers

eSP,R3

173232

005202

INC

173176

101002

062703

JSk

Convert Logical Sector

683

count

the read operation.
1is the top of the loop.

MOV

173160

173104
173170
1731172

BGYT

Q03370
110302
105003
000303
022703

000013

;Get

062703

8s:

000033
Read

SuUB

$20,,R3

BGE

ADD

#27.,R3

the

%
e

track

1-76

and make
for
Put

number

the

number

(Skip track

ANSI)

sector

into

range

1=206

sector

R2,¢6R1

;8et

track

number

KS,eR4

sPerform

sector

MOV

R3,@R1

004514

JSK

kS, ekq

173252

010211

MOV

173254

004514

JSR

173256

100002

bPL

ABORT

number

;Set

010311

173250

<floppy

remainder

1f sector 13-25)

(C)

sector

173246

173260

from

remainder

Undouble

173242

000032

002375

162703

173240

count

sC=1 if 13<=R3<=25, else C=0
sSector¥2 (2:1 interleave)

173234

loop

sBranch till divide done

s+l

114

myltiply

[+7]

000100
H

£9-a

S57-}

;I1f

read

error>

mI,

error

reaa

KXT11=AZ2

HALT

FlKMWARE
AT

PC=173262

MACKU

—~O bW
N~ C O

N
T

?9-da

V04.00

INDICATES

5=-0CI=8i

"FLUPPY

;
173764

004567

173270

oouLL3

173272
173300

032737
001407

000102
004000

B WA=

~===<>

Olobbll

173306

004514

173310

016611

173314
173316

004514

Empty

983

177170

173302

KEAL

Ra02

000004
000006

000410

RX01

22:50:27

PAGE

EKRUR®

RXV11/RXVs1

buffer

into

RAM

JSK

RS, RAGU

«WORD

RXSEMP

b1l

BRXSSUZ,Q#RXCS

;Start empty buffer
; and walt for TR
;Is DMA avallable?

BEQ

108

21f

DMA

handle

Mov

4(SP),ak1

JSR

R5, @k4

MOV

6(5F),@K1

sAnd

load

JSR
BR

K5,4R4

;wait

for

DONE

word

count

12s

Programmed

I/0

sElse
jwWwajit

load word
for IR

4(SP),R3

sGet

sturn

HOV

6(5P),R2

sGet

MnQVB

eR1,(R2)+

004514

sMove

one

pbyte

JSR

KBS, @8R4

swait

for

077303

SOB

R3,11s8

sLoop

for

all

173326
173332
173334
173336

016602

000004

10s:

000006

11s:

111122

Loop

back

not

yet

word count
starting

006303
060366

ASL

;Get word count
¢Turn into byte

000006

ALD

R3,6(SP)

supdate

bus

INC

Loglical

DEC

esp
2(5P)

sUpdate

000002

BNE

000010

ADD

173366

005366
001273
062706

ovuzs?

CcCcC

4(SP),R3

sDecrement
sReaa
sPop

000207

RETURN

.DSABL

LSB

first

;All done

Sector

Count

sector

stack

condition

show

count

address

another
the

sClear
;

173370

finished

173344

0us5216

buffer

memory

DONE

bytes

000004

173346
173352
173354
173360
173362

aadress

from

016603

MOV

address

into byte count

bus

173340

1282

bus

Operation

006303

RX01

count

current

MUV

016603

Operation

ASL

173320

173324

function

codes

success.

Number

sector

PC=317326%

MACKG

e
e
P

22156327

KEAD

The

- nde

main

LilC sl

PAGE

ERKOR"

subroutine

for

sending

~Aamw?a [ R,

LVt

disk

commands

and

waiting

for

LT LIVLe

density

010704
005741

5=0CT=b1

"FLOPPY

RXDB

address

RXGO0

IR/DONE

usages:

bit

unit
test

select
routine

bit

(proto

for

commands)

pointer

O ©
b
e

1/3402

et e

012504

050004

G~
O T o
N

173372

173374
173376

o b

S9-d

V04,00

INDICAILS

UL
M =

FlrMWARE

hHALT

KXT11=p2
==w==>

173404
173406
173412
173414
1734i6

010437

82711

001775

KXGO:

1771170

000240

MOV

(&3)+,R4

BIS

RO, k4

sCopy
sSet

command
unit

word

NOV

K4 ,8¥RXCS

sStart

PC, R4

sCopy

TST

=(R1)

sR1

BIT

¥RXSSTRIRXS$SDN,@R1

BEQ

s#alt for IR or
31t E0, neither

000205

RIS

+
(k1)

use

and density
operaticn

MOV

005721

adrs

sReset
sReturn

for

later

calls

RXCS

R1
to

DONE
are true

RXDB

caller

and

yet

check

for

errors

KXT11=AZ

FIRHMWARE

MACRU

V04,00

640

PAGE

223506 127

5=UCT=81

BUODTS=1U58 READ KUUTINES

173422

173424
173430
173434
173440
173442
173444
173440
173450
173452
173454
173456
173460
173462
173464

012704

004767
012703
004715

010203
004715

005003
V04715
010103

004715
010003
004715
010403
004715

W
Ve

Ws
We

Ne
We

WA
s

W
W2

wo
«e

“e

-e

we
-s

LU
T

we
wa

—e

weo

W
e

W8
e

we
“y

wa
e

e
e

We
we

W
e

Ne
N

MOV

“s

wo
we

000002

W
-

CALL

we
e

MOV

000206

operation on the TUS8 by transmitting a command packet

starting block #
byte

count

unit

numper

for

R1,

R4,

for

to receive data

unchanged

R4,=(SP)
R4
£#10,%4004RSSCTL,R3

CHZUUT
#RSREAD,R3

CALL
MuVv

eRS

CALL

@8R5

transfer

address of buffer

LSB
MOV
CLR

005002

ws
e

R3,

we
~e

we
~

we
s

we
e

-e

w3
e

0,
Destroys:

WS
We

s
e

we
we

We
-

we
.

ws
“e

e
we

TMo

wo
-

-e

“e

~Ne

Wy
-

-e

TMo

w8
ne

we
-y

ws»

WTM
"s

“e

TMo

“e

-y

W
-

"TMgs
e

W
N

s
Wy

LTI

we
Wa

Wy
W2
We

Ne
WE

WMe

e
N W
My
W
Ne
Ms

Qutputs:

RO
Rl

inputs:

TREAD:

010446
005004

ar ead

Starts

+ENABL
173420

1I READ ROUTINES

DeECtape

1U58

X~
O U WP N

99-d

Kead routines

+SBTTL BUULS=TUSS8

:S5ave buffer address
:1nit checksum
:Set command £lag and length

;0utput two chars and set R5
:>end read command and modifier=0

R2,R3

:Then unit number and switches=0

CLPR

sPlus a zero sequence number

CALL

@RS

MOV

KR1,R3

CALL
MOV

@RS

CALL

eRrR5

KO ,R3

MOV

R4,R3

CALL

@RS

sFollowed by the byte count
:And the block number

;Finally, transmit the checksunm

KX111=A2

FLRMwARE

READ ROUTINES

MACRO

S
- -V
L

LY-d

VU4.00

5~0CTI~B8l

1734s¢

012500

173470

006001

173472

004767

000116

122703
001017

000001

bow

173476

173502
173504
i73%00
173510
173512

105003

000303
106003

160301

173514
173516
173522
173524
173526
173532

010320
077504
004767
V05701

173534

001356

173536

010305
004767

000102

000044

004767

000052

173542

004767

000056

173546

122703

600100

173552
173554
173560
173562
173566

3s:

001402
019300
004707

000032

Vu4767

000004

173572
173574

000207

173576

004767

22:56:27

ready

HOV

S PR

BOUTS=TU58

483

0003u0

PAGE

gata

messages

(SP)+,RO

RUR

CALL

CMPB

#RSSLAT,R3

BNE

CLR8B

SWAB

RORb

SuB
MOV

R3,Kr1
k3,R5

CALL

the

sGet first word
7Is tnls indeed

+1f NE no =
sElse clear
sMove packet
7And

sRemove

TST

sHave

BNE

CALL

718

3 transferred?
sIf NE no

CALL

CMPB

#RSEND,R3

BEG

ABURT

<TU58

MOV

R3,R0

CALL

SWAB

CALL

;Get

END

packet

this

KE no

173616

000402

CLR

7Aand

173620

V04717

173622
1736024
173630

CALL

ePC

V04767

060304

173632

005504

CALL

erc

CH2IN

ADD

R3,k4

ADC

RETURN
«USABL

LSB

sklse

CALL

two

error>

END

checksum
match

bytes

calculated

with

success

checksum
the

sRead

words

7Head

Into

with

7And

ERROR

get

sAda

code

caller

return

sInit

;

packet?

= ABORT

success

;Get

005004

checksum

remainder of EnD packet
check its checksum
CC’s on success code of transfer

sDoes

;If

bytes

packet

sIs

173614

<TUS58

been

prospective

71t

7Save
?Read

message

compare

records

END

RETURN

ABORT

data

sAnd
iSet

CH2IN

data

and

start
opcode/success

missing>

count

counter

}Get
of

byte

packet

JReturn

BEQ

entire

all

get

END

low

in pbuffer
for

checksum

$And

000207

words

CALL

173012

173634

two

R3,(RO)+

CMF

000036

loop

count

transfer

K5,28

iLoop

count

word

tfor

MOV

001402

004717

508

sStore

byte

from

copy

’Get

packet
data message?
may be £ND message
flags

convert

sAnd

173602
173004
1736086

020403

TU58

2RO => data buffer
;s (CH20UT jeaves C clear)
?R1 = word count for transfer

CLC

RETURN

000064

from

first

two

bytes

checksum

end=around

back

word

carry

caller

value?

KXT11=A2

1K F1lHMWARE

MACRO

vU4,.00

5=0CT=81

22:56:27 PAGE 62

Ny W e WS Ve Ns

CX~
O U DN =

we Np We W2 we

weme=> HALT AT PC=173610 INDICATES "TUSH8 CHECKSUM t.RROR"

173636

1713030
173640
173032

173642
113644

89-d

173646
173650

173652

173656
173060

173064

CH20UT == write two bytes to the TubSd

Arites two bytes to interface and updates checksum,
Inputs?

R3
R4

two bytes to pe output; low byte first
current checksum word

Outputs:

R3 unchanged
R4 updated to new

CH8UUT:

CHZUUT:

V10705
060304
005504
004717
105737

100375
1103317

CALL

ePC
¥PC

MOV

PC,R5

ADD

R3,R4

ADC
CALL

CALL

004717
004717

176544

176540

000407

3
s

cnecksum

R5 pointing to CHIOUT routine fog easier future CALLs
sEntry point to output 8 characters

;S5et KS to following routine adrs
jupdate checksum word

with end=around carry

sRepeat for both characters

ePC

;Is intertace ready for ocutput?

TSTB

@aTOSCSR

BPL

MOVH

1s
R3,R8%TOSBFR

CHRET

$11f PuL no = walt

:Else transmit character to TUSS8

;4herge with other routine to return

CHZIN == Read two bytes from the TUSE
CHIN

~= Read a single byte from the TUS8

ilnputs:

;

;3
H
173660

004717

173670
173672

105003
105737

116540

173700
i73704
113706

153703

176542

i73076

100375

000303
900207

none,

Outputs:
R3 = character(s)

CH21Nn:
CHINS
1s:

CALL
CLHB
518

ePC
R3

sRead two, not one
;And zero out space

for new one

@#TISCSR

:1s a character available?

BlsSs

e#TISBFR,K3

:Else set into register

SWAB

BPL

CHRET:

read

RETURH

¢1f£ PL no

:Move current character over
:And return to caller

KXT11=AZ 1K FIRMWARE
EnD STATEMENT

69-d

1
2

MACRU

V04,0V

5=0CT=81

22:56:27

PAGE

«SBTTL
000001

<END

END STATEMENT

KXT1l=A2Z

F1RMWARE

VU4.00

5=LCT=81

22:50:27

PAGE

63-1

000001

PP.plé6=

00V014

RTSUSR=

00V0v46

R.PC

167766

FAKUUT

170424

PP.B17

00uo1le

RXbUOT

17240v

ReSTAK=

TVTIVIVE

AUTOBA

170472

FILNAM=

0u000L2

PP.C

176204

RXCS

167762

172370

GETCHK

171510

PP.CHI

0QoulL

RXDB

R.8TRT

BAUDRS=

000032

GELNUH

171612

PP.CLU

000001

RXESCR=

177170
177172
ITTOITV
Y

R.TYPE=

8ADBULT

170030

SAVPC

167752

8D,003=

0VLQ0O

HGHSEG=

001004

PP.CwR

1762086

RXESDD=

000100

SAVPS

167754

BL.0VG=

000010

HKBDW

1731140

PP.DRA

000020

RXESDE=

000020

SEGALU=

001000

0u0o04v

8D,012=

QU020

HKBDS

00QuU2

RXESDN=

00004V

SPACE

000030

HVBAUD

17114
170556

PP.DRB

8D.024=

PP.MDA

000040

RXESDR=

Y0200

SKeT

171636

B8b.048=

0V0u4U

INBY1E

170550

Pr.MDRB

0000v4

RX&$1D=

QuoUU4

S1ANDB

8D, 096=

000050

INBYTS

17u5506

PP.MD2

000100

RXeSUN=

000400

START

INITS

171750

PP.MOD

000200

RXGO

STARTS

IN,USR=

1677064
17064

170706

RXSEMP=

173372
000003

172504
1/2000
172752
001010

PRIb

000300

RXSFlL=

000001

STTUBD

170702

Pkl/

000340

RXSREC=

000017

171522
171554

RXSRED=

RXSRST=

000007
000013

ST173
SWCMD

RXS$STD=

0006011

S$DCHK=

RXSWDD=

000015

S$MOTR=

172172
173000
171212
177767
177157
177137

8D, 384= 000070
BITCO

00VoUt

KBDQ

BIT1L

0000u2

BITLV

002000

171246

PUTCHR

B1T11

004000

KBDS
LCSET
LEDOFF=

000017

PUTCLF

81114

010000

VU012

PUTLF

BITi3

020000

LOAD

172714

PUTSTkR

171252

PwRSUP

000221

@opl

171564
171542
170200
170666

MSGQ

171730

RAMROT

160010

1677176
177562
176542
004000

BiTi4

040000

LOCDSP

BIT1S

100000

MODE

8IT2

000v04

MSGS

171731

RAMTOP

NEXNUM

RBUFS1

000040

NCCT

171600
171642

RBUFS$2

BIT6

000100

NO.LOW=

100000

RB.8RK

BIT?

00200

NXTSEG=

0u1002

RB.ERR

BITS8

000400

OCTSIR

171656

BITY

ovidov

OCTSTO

171652

BUOTS

172104

oDT

170602

BRKNUO

170010
ie7770

ODTIFLG=

Qoo

000010

000020

[ 2N

8IT3

BIT4
BITS

STRBLK=

SSCART=

RXSWRT=

000005

SSNORM=

000090

RXSSDE=

000400

SSQPCD=

RXS6DN=

000040

SSPART=

SSRECN=

177720
177776
177711
000001

RXS$SER=

100000

RXSSFN=

0u001le

SSRETR=

RX$$G0=

000001

SSSEEK=

0001900

SSUNIT=

KXSSIN=

040000

SSWPRT=

177740
177770
177765

RB.FRM

100000
020000

RXSSTR=

000400

040000

RXssUnN=

0o02v0
000020

TENTAS=

KB.OVR

TI$BFR=

RCMD

RXSSXA=

030000

T1$CSR=

RX§SXxX=

003000

RXs$§02=

004000

TOSBFR=
TOSCSR=

RSABRT=
R$COMP=

000000

TRAP4

176542
176540
176546
176544
167776 G

000004
000007

TREAD

17342v

RC.DUN

171144
171232
177560
176540
00400y
000200

TUBAUD=

00u072

000100
000012

TUBOOT
T.BIT =

172404
000020

USERSP=

167760

ODTSTK=

172426

ODTWhHYI=

CHRET

1737104

167774

ONENUM

171576

CH21Iwn

O0.CNTL=

167772

RC.IEN

00010y

RSEND

CH20UT

FATERN

171750

REAQU

1727172

RSGETC=

PBRO

000010

READZU

RSGETS=

000010

PBR1

009020

KREGOUT

RSIN]IT=

000001

VECSET

000000

XBUFS1=

CHIN

ii3e66
it3642
CHBOUT
173636
= 000015
CR’

[2]

173670

CHK240

QDTLOC=

RXSS1E=

167750
167746
167744

B,CNTL=

E,PAR

1730616

[2E
2N YR~

172010

AROUN3

(2 X

AROUNZ

BD.192=

RChD1
RCSRS$1
RCSRS2
RC.ACT

RSD1AG=
=

DeEvBIT=

000200

000040

RESTAR

172770
171240
172004

VDEVNUMS

000001

PCMD

171044

RETRY

00001¢

RSPOSI=

000uVS

XBUFS$2=

G
170440 G
1775066
176546

DIAGNU

171754

PERMFS=

002000

RFLAG

000200

RSREAD=

0000u2

XCSRs 1=

177564

D1RBUEF=

001600
171574
173030

PP.A

176200

KPOLNT

R$SELIC=

0090013

XCSR$2=

176544

PP.B

170202

RTSEMT

167756
000052

RSSE1S=

000011

XC.BRK=

VU000l

DONE
DREAD
D.FLEN=

PBR2

000010

RSNOP

oL-d

MACRO

1ABLE

SYmBUL

PP.BIC=

0U000V0

KRTsFCH

000056

RSWRIT=

vo0uoL3

XC.IEN=

Vouviovy

PP.BIS=

000001

RTSFCT

000057

R$SCON=

000020

XC.MNT=

000004

EMPLYS=

00100V

PP.BI0=

000000

R1ISHGH

000050

R$SCIL=

000002

XC.PBE=

000062

ENDSGS=

0040U0

PP.BIl=

000002

KTSISP=

000042

R$SDAT=

00V00i§

XC.RDY=

000200

ENTS1l4=

000V16

PP.BI2= 000uv04

RTSJSH

000044

RSSINT=

J0V004

X1IRBYT=

ERRBIT

171742

PP.BI3=

000000

RTSRMN=

000uS54

RSSXUF=

000023

SSTACK=

0010ueb
167644

100060
00o200

$$6BRK
$SSLTC

170000 G
170008 G

E.EXT

000100

PP.BId= 000010

RTSSTA=

000040

R.HALT=

EJINT

00001y

PP.B1S=

RYSUER

000uS3

R.NXM

ABS,

ERRORS

174000

000

000000

Oul

DETECTED:

00012

KXT1l=Az

SYMBOL

FIRMWAREL

VIRTUAL

MEMURY

USED?

DYNAMIC

MEMORY

AVAILABLE

¢ FALCON/C=FALCON

TL-d

MACRU

VU4.00

5=0CT=B1

TABLE

9216

WURDS

FOR

(

PAGES

PAGLS)

22:56:27

PAGE

63=2

KXT1l=Ad

$$S$BRK

27=31
24-13

AROUNZ
ARUUNS3

44=47

q0=2%

54=24

So=2%

27=13

(CREF

li=14#

26=49%

BADBOT

49=60

49=90¢%

"9=144
T=21%

28=44

BD.OVG
80,012

5=U(T=81

22:56:27

PAGE

S=1

)

27=117

49=77

49-91

49=54%

49=55

56=3

28=43#

B.CNTL

8D.003

VU4.00

v04.00

27=35

14=20%
i3=30¢

BAUDRS

cL-A

14=i61#

$$SLTC
$SIACK

AUTUBA

MACRU

FIRMKARE

CRDSS REFERENCE TABLE

1=22%

J=23

8D,024

T=244

8D.048

T=25%

80,096

T=264

=14

8D.192

T=27%

8D, 384

T=28%

s8Ir0’

S=5%

10=-13

35=50

B8IT1
BIT10

S=b}#

B=42

=44

BIT11

belb#

5=15%

B1T1Z2

HY=17%

B8IT13

S=18%

6=35

BITl4

5=19%

BIT15

S=20%

6=32
6=30

B1T2'
BIT3

9=7%
§
S8

81T4

S=yj

BITS

S=10#

BIT6

5=11#%

8IT7

S=12%
S=13#

BITH

81719

7=30

8=25

10=9
g=38

8=43

=15
1=16

8=23

8=38

8=41

T=11
6=~23
6=-19

10=3

8«21

9=34

8=18

38=11

T=8
7=3

8=17

33=21

BRKNUU

jg=18

14=206%

21=17

CH21¥

bl=34

bl=46

62=34%

CH20UT

60=27

b2=106%

H2=17

62=13¢

CHIN

62=35%

CHKZ24V

S51=17»

62=24
b=25%

D.FLEN

48=125%

DEVBIT

10=-114

52=36

be=39%
IT=26
HY3=47

10=13%

Q0N

33=25
dyeb2#
40=-17

49=31
49=83

DREAD

50=21

48=-118
40=314
56=4

E.E€XT

10=17%

44«17

VEVNUM

VDIAGNO
DIRBUF

E.INT

{v=iu#

44-18

10=194

46=6

EMPTYS

48=1274%

ENTSLIZ
ERRBIT

35=1294%

48-124%

44=19%

38=21

40=24

41-20

43-13

48=-119

48~120

4b=121

448~122

44=374

E.PAR
ENDSGS

10=11

49=25%

CH30UT

10-4

S=14%

B0O01s

CHRET

8=15

53=31
40-11

57=21%

53=21

KXT11=A2

FLRMWARE

CRUSS REFEKENCE

MACKO

V04.00

(CREF V04,00

27=12

2/=15%

FILNAM

48=604#

53=38

GELCHR

33=1Y

3b6-30

31=25

GETNUM

371=33

41=22%

HGHSEG

33=30
48=120%

HKBDS

35=57¢%

37=27
37=21

38=15

FAKOUT

35=56¢

HVBAUD

IN,USR

INBYTS
INBYTE
INITS
KBDS

KBDQ

LCSET
LEDOFF

29=10
13=10%
29=11
29=8

14=31%

19=-36%

22-13%

27=16%

35=52%

49=31%

35=56

36-16

36=20

36=22

29-32

33=45

35-37

38=17

40-29

43-13

38=23%

37=174
26=27

44-39

37=36

38-13

S4=-34
37=18%

38-28

24-20

44-3y

43=13#

41=184#

41=30

NO.LOW

10=93
41=25

26=49
41=35%

48=119%

0.CNTL

13=10%

OCTSTO

32=40

GCTSTR

371=22

UpT

14=32

UDTFLG

13-264#
13=27%
13=29%

43-12%

53=34
37=48

42-14#

38=5
46=44

3y=25
22=1y
32=57%

42=-15¢%

27=18
36=14%

37=38

36=38%

37=117%

38=19
38=12%

13=30

32=-21

37=45

353=35%

7=28

ODTwWHY

13=7%#

32=106%

ONENUM

431=16%

32=11%

PATERN

36=15
44=334

PBRO

TT=15#

46=19
=22

T=24

T=26

PBR1

1=16%

1=23

=24

PBR2

T=17¢

1=25
35=24%
53=29

T=27

7=26

7=27

PCHD

33=28
48-128¢

PP.B10

Tgep#
B=17%
8=45%

PP.BIL

B=44%

PP.B

PP.BI2

B=43%

PP.BI3

H=q2#

PP.B14
PP.B15

g=a1y
B=40%

PP.Blb

g=39»

PP.BI/

d=38¢

PP.BIC

u=48§

PP.BIS

B=47%

PP.C
PP.CHI

8=23%

PP.CLU

¥=2Y%

g=u#

46=4
do=3%

49=44

38=20

33=37

32=52

49-34

37=37

46=45

9=5%

S5=2

37=-131

35=57

NEXNUN

PERME'S
PP.A

41-19

33-34

32=49

ODTSTK

39=17

32=51%

M3GQ

0DTLOC

39-15%#

33-32

36=39

NXTSEG

rAGE

32=483%
33=43
“9=10%
5=244%

LoCDsP

NOCT

2£4:56:27

46=14

53=44

MSGS

29-31+#
14=17
29=2714%
29=20%

S=0UCT=8l

)

44=27%
32=44

LF
LOAD
AODE

¢eL—d

TABLE

7=-28
T=28

38=24

36=-32

KXT11=A2

FIRMWARE

REFERENCE

TABLE

MACRO

(CREF

PP.CWK

B=5#

24=20%

PP.DRA

g=2its

PP.DRB

B=27%

9=5

PP.MD2

B=174

PP.MDA

8=-18%

PP.MDB

8=25%

PP, HOD

8=15#

V04,00

V04.00

26=27%

5=0CT=81

22:56:47

PAGL

5=3

)

44-38%

44=39%

9-5

PRIb

9=27%

27-11

32=-55

49=67

PR17

9=28%

27=36

27=38

35=48

55=5

38=27

39=19%

39=21

40=1%

40-25

40~-30

42=22

21=40b%

22-18%

32=-16

PRINT
PUICHR

32=59

3i=24

PUTCLF

30=23%

PUTLF

40-29%

32-544

=22
42-14

PUTSTK

32=56

4U=15¢

24-12%

40=-19

PWRSUP

45=5

55=10

Q00T

32=37

RSSCON

48=814

32=41%
52=27

R§SCTL

48=79%

60=26

RSSDAT
RESINT
RSSXOF

RSABRT

vL-d

CRUSS

48=75
48=504#
48=82%

48=90#

RSDIAG

RSEND

48-933
46=983%

RSGLTC

48=96
§

RSGETS

4u=66F

RSPOUSI

RSSETS

4y=91#
489-804
48=97%
45=-95%

RSWRIT

43=49y

R STRT

19=114#

ReHalLT

10=3%

RoNXM

R STAK

10=4¢%
13=15%
i0=53

R.TYPE

13-18%

RAMBUT

9224
9=23#

RSREAD

R.PC

RAMTUP

RB.BRK

6=374%

Rb,ERR

6=30%

61=25

60-24

45=17

14=29

21=46

19=34
21-35%
20=11

22=18
21=39%*

35«35

14=29%

19=32

19=34%

20-11%

20~17%

29=3

29=17

32~12

39=-18

39=~16

35=35
21=41

25=19

25=44

RB.FRHM

6=35§

RB.UVR

6=32%

gBUFs1

b=6%

24=35

RBUFS2

o=10%

44-69

RCL,ACT

52=-22

48=94%
48=47¢

RSnuP

RSSETC

52«22

d8=-924%

Rs$Cudp

RSINIT

61=7

6=10%

RC.DUN

6-19%

RC.IEN

6=234

24=3b6
24=36

RCMY

33=30

36=13¢%

RCHMD1

36=23

3o~36#

RCSRS1

6=5%

24-36

29-5

RCSRs2

6=9%

46=12

48-68

READU

S3=y2

54=23%

32-36

32-42

32=54x

KXT11=-AZ2

FIRMWARE

MACRU

V04,00

H=0CT=81

22:56:27

PAGE

S-4

CKOSS HEFERENCE TABLE (CkeF V04.00 )

READZU
REGOUT

RES1AK
RETRY
RFLAG

RPUINT

RTSEMT
RTISFCH

RTSFCT
RTSHGH

RTS1SP
RISJSW
RTSKMN
RTSSTA

RTSUER

54=6

54-21%

16=25
21=27

36=-34

36-38#

Y=324#

3o=14

13=22%

=32

48~1414%

48=142%
48=-137%

48=134%#
48=135¢%

54=17

48=1334
48=139%

54-9

48=140%

48=130
48-23%

RXSSFN

RXSSGU

RXSSIE
RXSSIN

48=219
4H=264%
48~15#
48=288
48=29%

58=5

57=44
59-15

4y-33

48=244

59=15

RXSSUN

48=27%

48=20%

57=31

RXSSXA
RX$SSXX

4y=22#

RXSEMP

48~34#
48=33¢%
48=40%
48=36%

RXSREC

RX$RED
RXSRST
RXS$STD
RXSwWDD

4B8=38¢
48=37%
48=398
du=354#

49=87

50=14%

RXCS

48=13»

RXDB

RXESCR

48=144#
48=50%

48=~14
57=21

RXESDD

48=464#

48=47%

RXESUR

48=45%

RXESLD

ab-493

RXESUN

48=44%

RXGO

97=32
48-106%
48~106%
48-110%

SSMUTR
SSNURM
S$OPCUL

4u-102+%
3H=1114%

SSPART

48=104+%

SSRECN

48-112%

SSRETK
SSSEEK

48=37

50=-15

50=16

58=5

59=-12%

58=3

59=-10%#

4u=-48%

RAESDN

SSDCHK

48-36

57=178
57=33

RXBOUT

SSCART

48=35

58«4

RASWRT

RXESDE

48~34

48=25%
48=-19#

RXSSTH

RXSFIL

30=37

36=130%

RTSUSR

RXSSER

45=0#

48=54%

RX§$02
RASSDE
RXSSDN

SL-d

52=35

48-103+¢

48=1094%

57=37

57=1717

48-38

48-39

48=40

KXT11=-AZ
CROSS

FIRMwARE

SSUNIT

48=1054

SSWERT

45=107%

TABLE

MACKU
(CREF

V04,00

5=UC1=81

22:56:27

PAGE

S=5

)

SAVPC

13-25%

14=27+#

21-37%

27-12%

32-39

SAVPS

13=244%

35-11%

35-54

21=30%

36~24

27-11%

35=16%

SEGALU

4o=116%
S=26#

14-28%

35=53

3633

37-45

37=23

SRET

41=21

55=44

di=32#

ST173

52-25

62=36

49=2b%

52=~14

22=11"
6U=24%

6221

49=-78%

54=18%

SPACE

9L-d

KEFERENCE

STANDB

H1e=21

START
STARTS

45=43
S4=11

54=14%

STKBLK

4u=) 224

53=25

STTUBD

4Y=304%

SWCMD
T.BLT

36=18
9=3gH

TENTAS

48=12064%

53=15#

36=29+

37=50

TISBFR

jh=bvg

TISCSR

44=-684%

52=13

TOSHBFR

02=23%

b62=3%

TRAP4

48=71%
28=70%
13=5¢

TREAD

Ho=5

TUBAUD

Ye1BE

TUBOOT

49-84

USEKRSP

i3=20%

32=20%

32=25

27=34%
39~22%
48=71

51=22

TUSCSR

VECSET

26=46

XBUFS$1

6=8#

XBUFs§2

6=12%

XCoBRK

T=43%
1=34
7=30%
T=364#
T=3#

XC.IEMN

XCoMNT
XC.PBE

XC.RDY
XCSRs1

XCSRs2
XTRBYT

49=26

S52=124

52=20
44~26

9=14
24=324%

6=114

4870
53=50

48=121¢#

9-18

44-25

44=26

24-39

28=44%

29-37%

24=39

6=74%

39-20

KXTi1=AZ

FIRMWAKE

MACRO

V04.U0

CRUSS REFERENCE 1ABLE (CREF V04,00

ABURT

LL—-d

DELAY

11=154
b1=21
12-23%

49=42

bi=37
49=1/6

49=51

5=0CI=81

22:56:27

PAGE M=}

)

49=54

49=92

51~23

52=29

52=37

53-24

$3=3¢6

54-8

54=-12

57=36

57-114

APPENDIX

SBC-11/21
This
the

appendix
SBC-11/21

provides
module.

the

user

with

the

electrical

SCHEMATICS

schematics

for

n2en2en2snz’?
8D

745374

€27
e 2

XXTt

KXT3 REVNT W —-2{D8
R1

R2 £

KXT? PARDST W ——{P!

KxTu IRQ4 H

~Zloz

RoL1 W —3103
1
xoL1 w130

KXT? PBROST w ——D%
'’
xpLe W —=D6

rROL2 # —{07

SEL)

KXTt RAS H
5

-kXT1

SEL®

St
RON

GND

6306

e ] HE— kxT1 CxDL1 K

3n 1 :

RSF=—KXT1

RePE—kxT1

CPBROST

cxpL2 W

KXT1

P2 kxT1 cROLZ H

CBXKRQ H

151

HEX

7;;_253

GND

KXT1

£
5o

TOAL

PAL11

TORL

DALY
pALS

TOAL
TOAL

09
88

H
H

10AL

87 H

ToAL

paL 18pf2

DAL?

paALS

Pt
bt

@82

TOAL
TDAL

01
08

H
H

a1z

39
bRy

ALe

peES

H —{pe

2 F
rols
>

rilfg

KXT3 HLTRQ H—>D}

kxT3 BKrRO H—8p2

XXT1

CTHER

BCLR

SEL1
H—]

kXT3 PUP

KXT1

SEL}

xxT1 TCOUT H—L

-KXT}

CAS

XxT1

KXT1 TCOUT H

-kXT1

SEL1

TDAL

enDPixri s2cie L

1inDPI—kx11 BoLR L

COUT H

TCOUT

BCLR

~KXT1

RAS

CAS

~KXT2

TSTHC

KXT1

-KXT1

URITE

R H2-kxT1 D15 W

out

BIT

3-STATE

KXT1 SEL® L

€63
ront

3
AL

6n DPE kxT1 cout L

DAL

KxT3 RBS? H

2103
13

nDPE—wxt1 cout L

—1d

—

TOAL

T0AL

TREAD

-XXT1

KXT1 JAKDIN H
KxXT2

TSYNC

KXT1

KXTI

KxT1 TDIN M

CAS

KxTt

kXT3

KXT1

TDOUT

TDIN

vo)

e Y8

TDOUT

CAS

~KXT2 HO BYTE

M
KXT1

R4 12

KXT1

LBS?

KxT1 ape’

poy ik

¥XT1 ap@3

RE 16

KxXT1 ADOS

pey ik

KxT1 ADO7

—— KXT1 RSTNC L

—kati TRGTN W

Apev

KXT1 AD@2

g out

aper,

KxT1

HoqHoLo

XXT3 RSTNC H

®3

KXT1

“
TOAL

KXT1

aD13

745373

WRITE

xxt)1

GND

74LS8E2—KXT1 UBYTE H

~KXT1

'8
KxT1

QD11

LARICH

5h DO

ADP9

1000

KXT1
15
P——kXT1

B —— D7

*°
RrRE

I PP3— -kxT1 cas L

KXT1 ADBS M

H —={D%

ToAL 13 B

_xxT1 RAS L

we DRSS kxT1 SELY L

19
SELO

9
"

ToaL 11 w-Ltps

H ——03

SFTBND L

-KxT2 ROSLP H—!'2

,2-‘—xxh ap1e M

H —~p2

an DO

"
KXT1

KXT1 €as H—2JcLk

220

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H —pup

xxT1 BacLR L —dcir

KXTt SEL®

155

couT
READT

RAS

KXT1

xTLifES

6ND —SX4%TLE

- KXT1 1

SELE [

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R/UHB D50

1AL

R1 13 vxt1 ap12 w

H—D1

7415249

roue
P28

KXT1 CBKRG H

R3[ 1u

LINE

DRIVER

gae—n(‘rl aDi1w B
Do

o
AL
18

3-STATE

KXT1

pE——ee—————
kXTI

CcRS D.“—————xxn €as b

R2 [

H—3D3

TOAL

3
1%

aloblss
RaSPPED o
xtr R0s L

KXT1 COMRQ H

D—l

81T

£53

13D

7915175

KXT1

14 W

TDAL

a1sbEY

£33

H
H

TOAL

AlY

@4
03

—
—

TDAL
DAL

D
D

LIJ

TIAKO H

D= 10AL

LATCH

DAL1
paLe

ecLr =

KXT1

1R~B

745373

TDAL 85 H

vbaLz

PFAIL

or-8 Pt oaL 11 w

10-8

TOAL 10 H

pALE

KXT4

loo-8

ToAL 1w M
TOAL 13 H

baL12d

1AKDIN H

1857 L

DALY
paL3

SKXT1

13 W

ToaL 15 M

paL by
DAL 13DES

+3va

DNRG

88 H

D——7 TOAL

3-5TATE

AL 3D

xxT2

Dro—ToaAL
D

IR-A

E6Y

abr

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15 n

2R-A
3R-0

10-8

pCT11

4 |

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Dro—ToAL

Te ] 208
3D-a

KXT1 B2CLR L—J—C"“ €no-8

SEL?

cPu

31y

CPBROST H

BR-A

KXT1 BCLR H

Ew2

DRIVERS

&0-a

1ldeno-a

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KXT1 CXDL1 W

kxT1

12 H

_XXT1

SEL8 H

74153670

igl £3%5

|12

117

oz
KXTi

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DAL

‘;1 7408108

f: 11
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XXT1

1Ak

E3%

0 —QEN ouT

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KXT1

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n2e

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naa2n23

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nas

STNC
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74120

E15
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32x8]
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-KxT2

74L.5393

TCLKSP

ono

KXT2

DLCLK

13ds,
2

JEvy | poy

~KXT2

E¥YNTRK

oaL 08 H—12 g

1129

TOAL

07 1vE

ToAL @9 H— 1

€15

18 K731 2

ToaL 11 H— 3

PZ4-reek L

GND

KXT2 CSKTB M

1F
2F

-kxT2
-%XT2

CS0LY M
CSQB H

~KXT2

CSLIP

“F

-KXT2

CSPL

W
W

~KXT2

BKAK

-KXT2

CSDL®

-KXT2

PARK

~KXT2

CSKTA

PBAK

-KXT2

CSRAN

-KXT2

ROL1

XDLY H

Uoe

RDL2 H

KXT1

x0L2

ADO3 H——g Dt

KxT1

AD@S

H—<dD2

KXT1

ADB7?

W-—2HD3

KXT1 ADB3 W —iDy

KXT1 AD11 H—D5

ADR

KxT1 api3 W —3{oe

KXT1 aD1S H—32107

kxTt tax L23GEn

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H—£lbe

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SCLk

:R?G";n

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bE9s

828123
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€ue

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KXT1

AD@

H—S4D12

KXT1

AD@Y

H—2+1013

KXT1 LB52 #—£1i014

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FUSE

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€39

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TUTBT

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KXT1

DRRPLY

vi{

KXTt

SND 2
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KXT1

B2CLR

KXT1

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KXT2

COUT

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1
KXT2

TSYNC H

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19.6608MH2

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KX12

SCLK

KXT1

B2CLR

DRRPLY

OSCILLATOR PACKAGE

SELI

KxT2

DNG

TSTNC

KXT2

TSYNC

CAS

DRRPLY

~KXT1

KXT2

NOTE:

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S5]74LS11\6

KXT2

€9

TCLKSP

1S NETAL

KXT3

KXTi1

RRPLY

R @70

DRRPLY

laKk

KXT4

DRRO

RSACK

RDHR

KXT1

COUT H

BCLR L

KXT1

COUT

791508),

€12

€28

DARG H

KXT2 DNG M

GND

KXYT4

KXTi

SEL®

KXT1 SEL! H
KXT2

DRRPLY

LR
KXT1 CDMRG H ——{:Q_.!
KXT1

~KXT2

Ras w2

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LOCATION OF DECOUPLING
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KXT2

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Digital Equipment Corporation - Bedford, MA 01730