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Document:	KXJ11-CA Single-Board Computer User's Guide
Order Number:	EK-KXJCA-UG
Revision:	001
Pages:	256
Original Filename:

OCR Text

EK-KXJCA-UG-001

KXJ11-CA
Single-Board Computer
User's Guide

EK-KXJCA-UG-001

KXJ11-CA

Single-Board Computer
User's Guide

Prepared by Educational Services
of Digital Equipment Corporation

Preliminary Edition, May 1986
First Edition, January 1987

Equipment Corporation 1986,

1987.

The reproduction of this material, in part or whole, 1s strictly
prohibited. For copy information, contact the Educational Services
Department, Digital Equipment Corporation, Marlboro, Massachusetts
01752.

information
The
Digital
notice.

in this document 1is subject to change without
Equipment Corporation assumes no responsibility

for any errors that may appear in this document.

The

following

Maynard,

are

trademarks

Massachusetts 01754.

of Digital Equipment Corporation,

dlifg]iftla]1 ]
DEC

MASSBUS
PDP

Rainbow
RSTS

VAXstation
VAXstation II

DECwriter

QO-Bus

UNIBUS

Work Processor

DECmate
DECUS
DIBOL

P/0OS
Professional
Q22-Bus

RSX
RT

VAX

VMS
VT

CONTENTS

KXJ11-CA HARDWARE FEATURES:ccccooescocccs
KXJ11-CA OPERATING MODEScsccsooccocsccccocscs
Standalone MOdE€.:cceesocoscocssocsosccsssoc
Peripheral Processor MOd€.csecocosocscoss
KXJ11-CA SPECIFICATIONS:ccoscoosoococscsse
oo
e NT
TERMINOLOGY USED IN THIS DOCUME
RELATED SOFTWARE PRODUCTS ccocoococcesccoccse

AVATLABLE OPTIONS:ccccoc0c0c0coo0scoccsosssse
S
ccosccs
MENT
i csccoo0ceccco
RELATED DOCU

L]
®

]

[]

AU
WN
O

[:]

= O 00U
W N

N ouvoomuibs D WD NDNDDNDDNDDNDDDNDMDDDMDDNDDDDDDDDODH

[]
[]
[}
@
®
@
®

O-Bus Base Address Selection.....
DMA

RequestSceeccsccsoscsoccscssososcocses

PROM

AddressinNngeeceococsccoocsssococos

Locked Instruction Enable.ccecececoe
BREAK Enable SelectiONeecosocoess
HALT Option SelectiONececoccooccss
Power-Up Option Selection....
SLU1

SLU1
SLU1
SLU2

Baud

Rat€eecocoocecccocosocscs

Transmittereececcooosoccsocsoscocscaos
RECEiVEeYr eooososooosossocsscscs
Channel A ReCelVEereeocsooossoo

Channel B Transmitter...
SLU2 Channel B ReCE€iVErecososoosososcoococss
Real-Time Clock Interrupt....
SLU2

]

INSTALLING

[}

[]

@
@

[

[]

SELECTING OPERATING FEATURES...
oo
Boot/Self-test SwitCheecooooooos
O-BUS SiZ€oecoossossssoscscsscococcose

NS
e ceeccoocoscoscos
POWER SUPPLY CONSIDERATIO

[]
L

eool-1
eeol-1
eeol-3
eeel-3

eeel-3
eeol1-4
eool-4
1-5
1-6

1-6

INSTALLATION
INTRODUCTIONOO....O...Q...0..0......

MDD NDNDNODNNODNODNMNMODNOMNNMMMNNNODNODNDNDNNONNODDNODDNODDNDD

CHAPTER 2

[]

OVERVIEW
ocoeses
G:
cosscscscssosc
TION
e e cocoosossco0oc
INTRODUC

[

[]
[]
®
[]
[]
[
®

OdOoO
U
WWWwNH

L
e

CHAPTER

KXJ11-CA

INTO A

.
BACKPLANE.

o oe2-1
eoo2-1
eo 24
coe2-9
«.2-10
o212
ee2—-13

ee2—18
e «2-19
e« 2—-20
oo 2-21
o02—22
e «2—23

.o 2—24
e s 2—25
e s 2=25

ee2—26
Edge Connector Pin AssignmentS.ccececsscoceccsos
ee2-29
CONNECTORS AND EXTERNAL CABLING:ccoooecooe
e 2-29
Parallel I/0 Interface (J4).cecccecoscosoccoocs
Serial I/0 Lines (J1, J2, J3)cccccocsoccs 000000002-30

Loopback CONNECLOrSeessescscsscsscssssscosssscsessl=34
ERROR DETECTION AND REPORTING WITH THE LEDS....0o0+2=36
DIAGNOSTIC TESTING WITH XXDP+.cocosssooocscocsscsocsel=38
iii

INTRODUCTION...................................;...3—1
KXJ11-CA BLOCK DIAGRAM . ¢ o ¢ o oo soooeocscsssscsossscsssesld—l
J=11 MiCrOprOCESSOTr cessescossssossosssssssssanseosd—l
RAM v v o o o e coooosoosscsssesassssssssssssssocscosssssld—l
Two Port Register (TPR) Fil€eceeeceooscososeccosesa3—3

3.1

3.2
3.2.1
3.2.2

3.2.3

3.2.3.4
3.2.3.5
3.2.3.6
3.2.4
3.2.4.1
3.2.4.1.
3.2.4.1.
3.2.4.2
3.2.5
3.2.6
3.2.7
3.2.8
3.2.8.1
3.2.8.2
3.2.8.3
3.2.8.4
3.2.8.5
3.2.8.6
3.2.8.7
3.2.8.8
3.2.9
3.2.10
3.2.11

3.2.12

3.2.13
3.2.14
3.2.15
3.2.16
3.2.17
3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
3.6
3.6.1
36,2
3.7
3.7.1
3e7.2
36743

w N+

3.2.3.2.
3.2.3.3

Arbiter/TPR Communication ProtoCOl.eccecsosccesed—4
TPRO & o o o e oo soecocscsosssscsscsssosssssssossssssssses3—d

3.2.3.1
3.2.3.2
3.2.3.2.
3.2.3.2,

ARCHITECTURE

a Control Register.ccescecscecsccssscssl3=d
TPRO as
TPRO as a Test Register.ceeecsccscccscoscoscsseld—’
TPRO as a O-Bus ODT Registerecececeecoccssseq3—ll
TPRL . v o o oo oeecoccscssssssescsscssssssssnsssossess3—l3
TPR2 e o v e ooeooecoesasssssssessossssssossessssssssse3—ld
TPR3 e o v o 0 coocecocsssossssessscsosssossessssssssss3—ld
TPR4 Through TPR15 . coooecocccsocsssssssssssssse3—lD

PROM and Firmware CONntrol...cesceoossecsscsosesss3—16
Firmware Usage considerationSeeececcccecscsosese3—18
SElf-tEStSeeeeeecoccocsosssssessancssssseassess31B
Booting.....................................3—18
Native Firmware Vs. User-Designed Firmware....3-19
CPU ID Switch...................................3—19

DMA CONETOLlET e eeessoesesoosocssssosssssoosssseeld—ld
Wake-Up CiTCUILt eevesocossocsaccssssssossssosssessl3—ld
KXJ11-CA Control and Status Registers...ceeees..3-20
KXJ11
KXJ1l1
KXJ1l1

KXJ1l1l
KXJ11
KXJ1l1

KXJ1ll1
KXJ1l1

Control/Status
Control/Status
Control/Status
Control/Status
Control/Status
Control/Status
Control/Status
Control/Status

GmEmmEg QoW

CHAPTER

. «os03—20
(KXJCSRA)
.
(KXJCSRB) eoee3—21
. coee3—22
(KXJCSRC)
.
(KXJCSRD) coee3—23
. eso0e3—26
(KXJCSRE)
. eoee3—20
(KXJCSRF)
. ceoee3—27
(KXJCSRH)
(KXJCSRJ) coee3—28

O0-Bus Interrupt Register (QIR).ceccccceccccecse «oee3—29

Maintenance Register.ccecescecsccccoscccocccs eose3—30

Program Interrupt Request (PIRQ) Register... eoee3—31

CPU Error Registereccceccccccscsocccoocccsccscscs eoee3—31

Processor Status Word (PSW)eeceoocoecceococscoo ese0e3—32

Console Asynchronous Serial I/Occcececcoccss eoee3—34
Synchronous/Asynchronous Serial I/0ceccsoces eese3—34
Parallel

I/0cccecccssscccsscsssosssccscccssssse eeeo3—34

—12V Charge PUMPeccsossoososscsccoscsosssscocccsss «sse3—34
esee3—35
O-BUS INTERFACE:cccoccscoccooscoccccccssosscoscee
eoes3—35
cce
ococsso
ccccccc
ecosoco
ccococc
PTS:cco
INTERRU
CA
KXJ11Interrupts From The Q-Bus To The KXJ11-CA... eeee3—36
upts From The KXJ11-CA To The Q-Bus... csee3—36

Interr

local Interrupts From On-Board DeviceSeeeooocoose3=37

SPECIAL INTERRUPT HANDLING . o cocceosooccssscsssccsssscs3—38
KXJ11-CA RESETS..................,................3—39
Software RESEL o coovoccososssossssscssssssssscssssld—39

HardWare RESEt eoceoceessosecscssssssssssscsssoscsessld—dl
MEMORY MANAGEMENT ARCHITECTURE....................3—42
Page Address Registers (PARS) oo oocosssssssscssseld—d3

Page Descriptor Registers (PDRS) e eccccococsocscsee3—43
O (MMRO) e e o cococooeoss3—44
Memory Management Register
iv

CHAPTER 4
4.1
4,2

4.2.1
4.2.1.1
4.2.1.2
4.2.2
4.,2.2.1
4.2.2.2

4.2.2.3
4.2.2.4
4.2.2.5
4.2.2.6
4.2.2.7
4.2.2.8
4.3

4.3.1
4.3.2
4.3.3

4.3.3.1

4.3.4

CHAPTER 5
5.1
5.2

5.2.1
5.2.1.1
5.2.1.2
5.2.2
5.2.2.1

e0o03—46
eoe3—46
eoo3—46
eoe3-47
eo+3—48
eoe3—48

SHARED MEMORY s ccocooccoooscosoccooocssococcocscsescs

Shared Memory OrganizatlONececceccccccssosos
Defining One Block of Shared MemOry.:eee.s..
Defining Two Blocks of Shared MemoOry......
Defining 64 Blocks of Shared MemOrY.eso.e.e
Enabling and Disabling Shared MemOrye......
Shared Memory ConsiderationS.cececcscccscscse

e s3—50
eoe3-51
eos3—52
eee3—-53

DMA TRANSFER CONTROLLER
csscsooos
OVERVIEW:. o e c 006 c600co0cscsoosoocscososocossosocooccsses

S
s s oo
DATA TRANSFER CONTROLLER (DTC) REGISTER

DTC Global RegisSterSeeccoscooseosccsocccsocsscsco
Command RegisSter.ceececoccessscccoccsscscsccscss
Master Mode Register.scccocccoscccccscscscscs
DTC Channel RegisterSceccssccccsccscsccscccscoe

current Address Registers A and Beeooooooo
Base Address Registers A and Beescooococsocccoos

A
L
T
I
J
O~ ~dO i N

3.8.3
3.8.4
3.8.5
3.8.6

Memory Management Register 1 (MMR1) coocccooe
Memory Management Register 2 (MMR2).cocceoes
Memory Management Register 3 (MMR3)...cc..

3.7.4
3.7.5
3.7.6
3.8
3.8.1
3.8.2

‘
Chain Address Register.........................4—8
10
Interrupt Vector and Interrupt Save Register..4Status Register...............................4—11
Current and Base Operation Count Registers....4-13
Pattern and Mask RegisterSeecceccecscocccs

Channel Mode Registerecccoccocccsoscscscoe

PROGRAMMING THE DTC.occccococoscocscsocssoococe

Chip Initialization.cseccccsccocccsooccoscs
DMA OperatiONecccccocccscocscosscsossocssccs
Termination OptioNSecceccecsccsocscoosscscens

FOP Condition Handlingeeeseooooosoocoocscce

cosoosd—14
ceeosod—15
oe.4-18
eoo4-18
eoed-21
oo od-22
oo04-23

EXAMPleSccoecossssossssssssscssossoscsccccoscse

PARALLEL I/O CONTROLLER
se
OVERVIEW o c c 6 606006000 cccseoscooscssosossocsssssso

PARALLEL I/O PORT (PIO)

REGISTERS.ecsecccocs

Master Control RegisterSciceccceccscccccsccoscs

Master Interrupt Control Register.......
Master Configuration Control Regilster...
Port Specification Registers.cececcescssccoccs
Port Mode Specification Registers

(Ports A and B)eeeceosoososscsooccsoosscsoccscs

00005—5

(Ports A and B).sseocoscccscoscsoscsscccss

00005-7

5.2.2.2

Port Handshake Specification Registers

5.2.2.3

port Command and Status Registers

0000005—8
. so05—10
Bit Path Definition RegisterSeeceececsecssocsccs
es5-10
..
ers...
Regist
ty
Polari
Data Path
eoeD—11
scos
ccoccc
ececcc
erScec
Regist
ion
Direct

(Ports A and B)eeoosoo

Data

Special I/0 Control RegisterS..cececcecececeo
Pattern Definition RegisterSeeccccsccccosccse

eee5-11
eoe5—12

o
©
e

wN
-

=
> W N
(N

o
o
e
e

O J~JJO
SO O O Ul
D
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[
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b
—

W
-

WN
O 0 JO U

[
©

[

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[}

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[-]

[]

e
e
e b
e b
e b
b
e b
b
o b
= b=
N

AU BREDBRWWWWWWWWWWHNNNN
-

@
[

WWNHNNDNDDNDDN
-

]
e
e
©
o
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WWWWWWWwWwwWwWwWwwwWwwWwWwwwwwww

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-

o
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WWWNhDNMNDNMDDNMMNMDNMNMMDDNMNNMDDMDDNMDDNDDN

e
o

ool
oottt
Ul

[]
®

OY O OO

®
@
[
@

O\ OY O
O

oY O
o
e
e
©
e

o xaxaxaxaxa

[
@
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e xa

[
[}
[
[
[

xaxakaa

[]
[
e

[
[

[}

ook
e

Port Data RegisterS..ceccocscscosscossssoscscocssssd—13
PIO Counter/Timer Control RegistersS.cececececceesssd-14
PIO Counter/Timer Mode Specificationeeececeecs..5-14
PIO Counter/Timer Command and StatuS..cceecsssed=16
PIO Counter/Timer Time Constanteeccececececoceccesssd=18
PIO Counter/Timer Current Count.cecscocececoeoosd=18
Interrupt Related RegisterSiccececcececcsssoccscsssad=1d
Interrupt Vector Register..ccecececocsccscossad=ld
Current Vector Registerecceccscscecccsscssccscssssd=20
I/0 Buffer Control Register.cecceccecccococoscsesed=20
PROGRAMMING THE I/0 PORTS...,.....................5-21
Programming the I/O Ports as Bit PortsS..ceeeee..5=21

Programming the I/0 Ports as Ports with
HandsHaKe.eeeooecooooosoosoocsosssssccssosssscsssseed24
Programming the PIO Counter/TimerSceeccceccccccecsd—42

CHAPTER

[]

Pattern Polarity Registers (PPR)cecccecocsoocsed=1l2
Pattern Transition Registers (PTR)cccecccooeeed—13
Pattern Mask Registers (PMR).sccecscccscscocscsesd—l1l3

SERIAL

LINE

UNITS

OVERVIEW G ¢ 00 e 0coocosccoooocccscssoscssscscsssssssssscsscssb—l
CONSOLE SERIAL PORT (SLUl)¢cccccoccsscsocscscsscscossesb—l
SLUl (Console) RegiSterSeececceccscsssocossscsossscscsesb—l
Receiver Control/Status Register (RCSR).ccecoseeb=2
Receiver Buffer Register (RBUF).scecocscocsscsssb—3
Transmitter Control/Status Register (XCSR).....6—-4
Transmitter Buffer Register (XBUF) :ccoooeceooseeeb=D5
MULTIPROTOCOL SERIAL CONTROLLER (SLU2) cecscccococeceeb=06
Synchronous/Asynchronous Serial Line (SLU2)
REgiSterSeceeeossscssocsssosssoscsssososcssossscsssscseb=0
KXJ11l Control/Status Register A (KXJCSRA)eeoeoob6=7
Timer RegisSterS.cceseccscccsssscscoscsscsssssccscssb—8
SLU2 Timer Control RegisSterSeeceececscscsscscessb6—-10
SLLU2 Timer Data RegisterS.cceccceccocsccssssssb=12
SLU2 Timer Programming ConsiderationSe.......6-14
SLU2 Control RegisSterScecceccecscccsccccsosssssesb—14d
Control Register Ocecececcoscossssssosscssscecb—1ld
Control Register l.ccecececccsscscscscssssosb=l1?
Control Register 2 - Channel A....cceooceosab6-18
Control Register 2 - Channel B..:coosocooossb-19
Control Register 3ceeecessscssssccscsccsccsesb=20
Control Register 4eeeeeccocscscssosccssccscossb=2l1
Control Register S5.ccecesccccccccocosscssoosesb=22
Control RegisSter Beceececsscccsscscoscsscscscesb=24
Control Register Teeeeecoocscsssscssscssscscesb=24
SLU2 Status RegisterSeccecccccsecscscsssscscssab=25
Status Register Oceeescosscssocoscscsoccosseb=25
Status Register l.cececescoscscscssccososccsssesb=27
Status Register 2 (Channel B Only).cceceoooes6=29
SLU2 Transmitter RegisterS.cceccccsssscsccccsssb=30
SLU2 Receiver RegisterSc.ccecesssssccccssocsssseb=30
EXAMPleS cececoosssosacsscssscsscssoscssosossssssssesseb=30

APPENDIX

MEMORY MAP SUMMARY

A.l

APPENDIX

KXJ11-CA/KXT11-CA DIFFERENCES

APPENDIX C

USER

(P)ROM PROGRAMMING INFORMATION

INTRODUCTION......‘.....Q.Q........O...O.....O

(NI

HAarAWaY e o oeooososocososososossossosossosscscsscsse
SOFtWAY e ooooosooossossossosonossscsscsssscssscsso
ProceduUr€eecoscoccocscssosocsoos

Setting

®
®

ReqUirements.O..Qi..0....'O..._.OO.........

N -

TRANSPORTING NATIVE FIRMWARE:cccocoocoooocccscse

ParameterS.c.cocccccooccsosccscocscaos

PROM Map......00..........................
CheCksum.........C....O'............0.0...

Checksum AlgorithMececocsooocsccosocsccsscs

]

BSOS

QOO0

000

DIFFERENCES BETWEEN THE KXJ11-CA AND THE KXT1l1-CA..B-1

MDD

B.1

APPENDIX

coosoC=2
cossC—=2
coeeC—2
ceoosesC-2

ceoeC—2
N
eeoesC=5

eo s C=7

BUILDING AN APPLICATION
APPLICATION BUILDING....Q.O...O....OOO......

D.l

ceooC—1
cesosC-1

e o .0 .D_l

FIGURES

Title

Figure No.

Memory Mapping - PROM in LOW MEemMOIrY.eoeooccsos
Memory Mapping - PROM in High MemoOry...e....
Boot/Self-test SwitCheeosoooocososcocscossoccss
O-Bus Size SelectiONecccooccccsccoccsscscccsscs
O-Bus Base Address SelectiONecececcosssccscscs

DMA REeQUEStSeessosscccoccsososcosssccscccscocsoso

csoeel2=2
cooe2—4
eo002=5
coee2-0
coee2-9
ese2-11
coe2-12

W N - o

Locked Instruction Enable.sccecceccccccccscns

I
NNNNNNI\')NNNNNNI\)
|

== OO JouUldwWwdDH-

KXJ11-CA Jumper LayOUteiceececcoooocscosccn

2—-15

BREAK Enable...O..................00....00..
HALT Option Selection..fi..fi......O......0.0.
PROM

AddressSiNgeececcecsosccscssoscccossoscsssescscos

SLU1

Baud

SLU1
SLU1

2—-17

SLU?2
SLU2

2-18

SLU?2

2-16

2-19
2—-290

2-21
2—-22

Rat©@eeceococssocooocossossososssosoccsscss

Transmittereeceoccoosscssoccoscoscsssssoccsss
RECEI1VEY esooosoosoosososssscssocossosoccssssscos

Channel A ReCEelVereoeoooososocossssssosococscss
Channel B Transmittereececececcccssocooessoccocscss

Channel B RECEiVEereeosocossocsscscssscsss

Real-Time Clock

Backplane

Interruptececcscsccocsccosccocsss

InstallatiONecessscccccoccscccccssccsce

Using Grant

CardS.cceccccocscsscccoscococcsecs

Parallel I/O Interface Pin AssignmentsS.cceecceossess2=29
vii

J2 and J3 Pin Assignments

J1 Pin Assignments

ConnectoOrSeescescees

Loopback

as-

TPRO

TPR2

TPR3

as
as

TPRO

0o
W

TPRO

KXJ11-CA Block DiagramMeeecococeecosooo
Two Port Register (TPR) File.ceecococsn

|
O 00 ~JO

WWwWwWwWwwwwwwwww

(10-Pin)....

(40-Pin)c..ccececoscocsos

Control Registereeoeecoeoess
Test Registerecececcccocsscocscso
Test Result Register.iceseeces
Test Result Regsiter....

..
TPR1.

TPR3

Format

During Hardware

Reset.....

PROM Space Allocation - 8K X 8 PROMs..
PROM Space Allocation - 16K X 8 PROMs.
PROM Space Allocation - 32K X 8 PROMs.

Control/Status Register A..
KXJ11 Control/Status Register Beoesoosoo
KXJ11 Control/Status Register Coeoooosoc
KXJ11 Control/Status Register Decososcoe
KXJ11 Control/Status Register FPeoosooooo
KXJ1l1 Control/Status Register Heoooooo
KXJ1l1 Control/Status Register Jeoososooo
O-Bus Interrupt Register (QIR)cecoecoscco
Maintenance Register.cececceccocsccoccss
PIRQ Register.........”..............
CPU Error Register......
KXJ11

coeesessl2=31
coosesssl2=31
cseeeesel2—35
A
A
L
B
cesesesseld—D
N
coesssseld—1l
ceeseses3—1l

0000000003_11
ceeseses3—13
cesosese3—15
coesessel3—16
coeceessel3=17
ceesssesl3=17
ceceoseee3—20
cesosssel3—21
ceecceceel3—22
coeosees3—23
cecoccee3—26

e
ceosssse3—28
ceoseese3—29
ceeesees3—30
ceeceeess3—31
cesesese3—31

ceecsesee3—32
Processor Status Word (PSW)..ecoeoocccosso
ceosseee3—43
cce
(PAR):cccccoc
Register
Address
Page
ceeoseess3—43
csscs
(PDR)ccccecocc
Register
Descriptor
Page
cececsses3—44
(MMRO)..ccce.
O
Register
Management
Memory

Memory Management Register 1
Memory Management Register 3

(MMRl)...c... ceeseses3—46
L
(MMR3).ceeceo T

Defining One Block of Shared MemOIY.eeoeeoecocooesse3-49
Control Register Bits/Q-Bus Address Relationship..3-49
Defining Two Blocks of Shared MemOrY..ceeecesosess3=50
Defining

R
DTC Command RegisStereccecescsoccocccscccssscss R

O 00 -JOoOOUTLd
W
-

Master Mode Register.ccecccccccososccoccccscs cocescsecsd=0

Current A or B Address Segment/Tageeceecsess ceossescecd=T

N - o

Current A or B Address Offset.ccccccccceccs coessoecscd=8
Chain Address Segment/Tageccscescscossococsos I

et =

|
»?4>¢>®wh4>¢hhwhd>#b®wh
[
N
T
D

64 Blocks of Shared MemOryeeeoooo coessees3=5l

4-14
4-15
4-16
4-17

4-18

4-19

Chain Address Offset.ececececcccccssosccccccscs coeseeseed-9
Interrupt Vector Registerceccccsccccccceccces ceeseesesd-10
Interrupt Save Register.ccecceceeccsccccccss cseossessd—10
Status Register.ccccceccccccscccocsccsocscss coosseessd-11
Current Operation Count Register.c.ccececeees cosceceesd-14

Base Operation Count RegisSter..ccceoececcoccsscosccd=14

Pattern Register.iccocecoococsossoscsocsscsccsecs 000000004_14

Mask RegiStereceeecccocssosssscoccsosssssssosssosesd—ld

Channel Mode Higheeeooececoooooosocsosccscccnce 000000004-15

Channel MoOde LOWe.eceeooososooossosssscoccsssaos 000000004—16
Chain Address Registerececcscccscsocccccocecsooe 000000004—19

Reload WOTrd.eeeeecooocoeososossscssssosssssssssosscssecd=19

Example leoooooooosssssosssssssscsossssssssssoscssococsd=20
Example 2 e o oecescosccsocccosscocssccoscscsscsscsscsocsssd=20
viii

Master Interrupt Control Registereeeessececososccceed=3
Master Configuration Control Registereeeccscoocooeed—d
Port Mode Specification Registers (Ports A and B)..5-5
Port Handshake Specification Registers

(Ports A and B)....................................5-7
Port Command and Status Registers (Ports A and B)..5-8
Data Path Polarity Registers (Ports A, B, and C) ..5-10
Data Direction Registers (Ports A, B, and C)eeoo «eD—11
Special I/0O Registers (Ports A, B, and C)eeosocos ..5-11
e «e5—12
Pattern Polarity Registers (Ports A and B)..
«e5-13
B)
and
A
Pattern Transition Registers (Ports
®

Pattern Mask Registers (Ports A and B)......
Port Data Registers (Ports A and B).cecoconcs

Port C Data Registerececceccecocccscccscsoccoccsscs

Counter/Timer Mode Specification
(Counter/Timers 1, 2, and 3).ccccccocccsccscs
Counter/Timer Command and Status

(Counter/Timers 1,

2, and 3)cececccccocccccscs

Counter/Timer Time Constant (Counter/Timers

«e5-13
ee5—13
«e5-13

..5-16

l’ 2' and 3)Q........O..................O;..
Counter/Timer Current Count
(Counter/Timers 1, 2, and 3).ceccecccccoccccsccn

- Current Vector Registereiccscecsccossscocscs

I/0 Buffer Control Register...cecececcocccs

PIO HandShake Lines...O...0.0..............
PIO Output Duty CyCleS.ccccoccscscccccosce

Receiver Control/Status Register (RCSR)....
Receiver Buffer Register (RBUF).ceooccsss

Transmitter Control/Status Register (XCSR).
Transmitter Buffer Register (XBUF).eecococos
KXJ1l Control/Status Register A.cecccoscoccc
Timer Control Register Format
(Timers O’

].’

and 2)...OO....O..'...........

Timer Data Register Format (Read and Write

Registers 0,

and 2)ccceccooceccssccocccs

Timer Data Register Format When Used as a

Timer Status ReglisStereeceoseccoccocccsocossoocscosco
Control Register Qeceocococsccccccccccccscs
Control Register le.cecoocoosoccscsccccccscss

Control Register 2 - Channel A..ccccccees
Control Register 2 - Channel Beecoooooooon

Control Register 3.ccceccesccssscoccsecccscs
Control Register 4d..cccecccsocsoccccsccccs
Control Register S5.cccecccscccsosccscssoccs
Control Register 6Gececoococccscscsoocsosccscscs
Control RegisSter 7Teececcococsocscossosccsccs
Status Register Occeecoecocosccoccssssssscscs
Status Register l.cececceccccscoscoccssssccscs

Status Register 2 (Channel B Only)..ccc...

Transmitter Registers A and Beecocoooooocse
Receiver Registers A and Beeeocoocscsooocscse

2K X 8KB PROM MaPO ® 6 © © ¢ ©¢ © © @ ©® © o © ® © 6 © ¢ © 6 @ © o
2K X ]-6KB PROM Map. @ © © © @ © © © © 0@ ©O e @ © @ @ @ © © © © ©
2KX32KB PROP’l Map......’......O......O.....
ix

o 6—-12
..6-14
e e6—-17

..6-18
..6-19
. «6—-20
e s6-21
e 06—22
. o 6—24
.s6—-24
e «6-25
e s 6—27
. 629
. +6-30

. .6-30
s C—06
ee
e C—6
eosC—6

TABLES

e
r oy

HHEWNDNEFOOPPOWNDEFEWNDHFOODUDE
WD
OOOJOOUTE WN -

WP OGO UVUTUUNTUTE R R WWWWWWNDNNMNNMNMNODMNDDNDDNDN

Table

Title

No.

Page No.

Factory-Shipped Jumper ConfiguratiONeeecececccecocoseeel2—3
Boot/Self-test Switch FunctionS.cceccecoccocsococccoeel—7
Q-Bus Base Address SeleCtiONeccecccecsccoccososcscocscsel2—10
SLU1 Baud Rate JumperinNge.cececcceccosccoccccosococccsccecel2—19
KXJ11-CA Pin IdentificatiONeccoccoocccccocccccccoocseel27
RS422/RS423 Interface tOo Jleceeoescscosccscossooccscel=32
RS232-C

Interface

Jl.ecececceccscsccccccoscococscscsel—33

CCITT/V.35 Interface tOo Jleceececoocosososcoccscseel34
LED Display DefinitiOnNSceccccccccccosccccscscscscscecl—36
TPR2 and TPR3 as Test Result RegisterSc.cecccsccooccee3=9
Interrupts
Interrupts

from
from

the
the

Q-Bus to
KXJ11-CA

the KXJ11l-CA.ccceeeeoe3—36
to the QO-BuS.:ccceceeee3—-37

Summary Of KXJ11-CA Local InterruptSceecccscecoccseee3—38
KXJ11-CA Software ResSeltceccecoccocoocccccccsossocoscccseeld—40
KXJ11-CA Hardware Reset.ccccococsscccoscscccoccssel—4l
DTC Global RegisterSceccecececcccscocscososssoscscocescesd—3
DTC Channel ReglsterSeeececcccoocccsccocossscoccscocsscscsocd—3
DTC Command SUMMALY eceoeocccosossocsssosccssscscsscessced—D
PIO RegiSterSceescocoscsccscsccsosscossscsoscsoscscsccscsossesd—2
Pattern SpecificatiOnNSecceccosccsocoosocscccccososccssed—12

Counter/Timer EXternal ACCESScscocssoscssoocsssoocsssd=1b
Port C Handshake Lines Port C BitS.ececcecocscsseed—25
PIO Counter/Timer External Access LineSceecccooceeed—42
SLU2 REg1StEerSceeosccoscoossocccssscsssscsososscscscsssscscebd—7
Synchronous Baud RateS.ccececcossccosssscocsoscsocsocscsesb—9
Asynchronous Baud Rate€Sceecceccscccecccscscccscscsosceccssb—9
KXJ11-CA RegiSterSecececoccecoccoccosccososssccssssocsscsccscsesA-l
KXJ11-CA/KXT11-CA DifferenCesS.ccecccccocccsccsoscscsseB—l

CHAPTER 1
OVERVIEW

INTRODUCTION

l.1

J-11
The KXJ11-CA (M7616) is an 1I/0 processor based on the
,
length
ed
extend
eight,
quad-h
a
1is
It
chip.
microprocessor
ction
single-width module that executes the extended PDP-11 instru
memory
with
)
g-point
floatin
ng
includi
ctions
set (all 140 instru
management. The KXJ11-CA can operate as a O-Bus slave device under
a

arbiter

Q-Bus

processor,

OIr can act as a

the

direction

The
DMA
of

KXJ11-CA meets the specification for a Q-Bus slave and Q-Bus
master, and can interface with most of Digital's large family
0-Bus modules described 1in the Microcomputer Interfaces

standalone

processor.

Handbook and the Microcomputers and Memories Handbook.
KXJ11-CA HARDWARE FEATURES
1.2
The KXJ11-CA has the following features:

1l6-bit microprocessor

J-11 (DCJ11-AC)

PDP-11

extended

Executes

instruction

instructions including floating-point)

Contains

memory

Operates

management

unit

for

memory protection and 4 MB addressing

three

(140

set

levels of
|

MHz

Memory

512 KB of dynamic RAM

Can

accessed

local (on-board) devices and Q-Bus

devices

firmware

PROM, 16 KB of which is allocated for

O-Bus

interface

word,

commands

two-ported
and

Mechanism

for

RAM

(TPR)

file

for passing

parameters

posting

interrupts

the

Q-Bus

Two channel programmable DMA transfer controller
Performs
transfers
between
local
22-bit
16-bit, 18-bit, or 22-bit QO-Bus addresses
Eight

control/status

Console

asynchronous

(DTC)

addresses

and

registers

serial

line

DL-compatible

EIA RS-422/RS-423/RS-232C-compatible
Programmable

baud

rates

300

Primary synchronous/asynchronous
Full

modem

EIA RS-449

38400

serial

baud

line unit

support

(CCITT V.24)

and RS-422/RS-423/RS-232C-

compatible

Programmable baud

rates of

Bit-oriented

character-oriented synchronous protocol

110

to 76800

baud

support

Secondary synchronous/asynchronous serial line unit

RS-449 (CCITT V.24) data and timing only
RS-422/RS-423/RS-232C-compatible
Programmable

baud

Bit-oriented

rates of

110

to 76800 baud

character-oriented synchronous protocol

support

Party

Two

line

operation

programmable timers for the synchronous/asynchronous

serial line units

and one watchdog

timer

Parallel I/Q Interface

Two 8-bit bidirectional double-buffered I/O

ports

One 4-bit special purpose I/0 port
Pattern recognition logic

Three independent 16-bit counter/timers
IEEE 488 electrically-compatible
MODES

KXJ11-CA OPERATING
1in
-CA can operate 1in either standalone mode be orthese
KXJ11
The
descri
follow
peripheral processor mode. The sections that
modes. The AC and DC characteristics of the KXJ11-CA are identical
1.3

in both modes.

lone Mode

Standa
1.3.1
standalone
The KXJ11-CA can be configured to operate as a other
Q-Bus
with
n
icatio
commun
processor. In standalone mode,
ane
backpl
The
ed.
disabl
is
r)
devices (including the system arbite
power
both
of
source
a
as
acts
d
into which the KXJ11-CA is plugge
The KXJ11-CA preserves the continuity of the
ground.
and
daisy-chained interrupt acknowledge and DMA grant lines on the

backplane.

0 or
To select standalone mode, position the on-board ID switchandat other
this
in
appear
that
1. In the operational descriptions
chapters, ignore any references to Q-Bus activity if the KXJ11-CA
is operating in standalone mode.

1.3.2

Peripheral Processor Mode

designed

primarily

an I/O processor. In a

The

KXJ11-CA

from

traffic that would ordinarily degrade system performance. Up

devices
typical system, a KXJ11-CA 1is connected to one or more I/OQO-Bus.
In
the
with
ly
direct
aced
that would otherwise be interf
and
pts
interru
handles
CA
KXJ11peripheral processor mode, the
data processing associated with the I/0 devices, freeing the Q-Bus

.
to 14 ' peripheral processors per system can be accommodated
switch
ID
d
on-boar
the
when
d
Peripheral processor mode 1s selecte
is in positions 2 through 15.

1.4

KXJ11-CA

Physical
Height

SPECIFICATIONS

26.6 cm (10.5 1in)
22.8 cm (8.9 1in)
(includes module handle)
1.27 cm (0.5 in)
665 g (22 0z) maximum

(quad)
(extended)

Length

Width (single)
Weight
Power

requirements

Operational

+5V

power

+12v

5%
+

6.0
5%

option
+12V

AC
DC

loads

maximum

with

DLV11-KA

without

DLV11-KA

|
+

option
Bus

A maximum
1.4

0.4

A maximum

loads
loads

=
=

2
1

units
unit

Environmental
Temperature

Storage

~-40 to gsoc (=40 to %SOOF)

Operating

Relative

60°C

(41

140°F)

humidity

Storage

10%

90%

Operating

10%

90%

(non-condensing)
(non-condensing)

Altitude
Operating

Up
Up

15
15

km
km

(50,000
(50,000

quality

Alr must

non-caustic.

Storage

Air
1.5
Some

to
to

ft)
ft)

TERMINOLOGY USED IN THIS DOCUMENT
terms used throughout this document are

Local

device/memory

located

the

Global

or Q-Bus

O-Bus

addresses.

—--

Shared
memory
-space that is also

Arbiter

grantor,

resides
BDAL

lines.

The

and

bus

KXJ11-CA

Refers

defined

I/O device

Q-Bus

address,

below.

or memory

that

board.

Refers

Refers
assigned

any

to
to

including

the area of memory in local
Q-Bus address range.

KXJ11-CA

address

default master, interrupt acknowledger, DMA
and
reset
control device (usually
up/down
slot of the Q-Bus).

Q-Bus

power

the

first

-=-

The

Q-Bus

(backplane)

multiplexed

data

and

address

O-Bus transceivers —-- The interface between the O0-Bus and the QDAL
|

bus.

7DAL,

bus

The 22-bit address and 16-bit data path between the

BDAL transceivers and the KDAL transceivers.

KDAL bus -- The KXJ11-CA internal module multiplexed data and
address bus, which is common to all local memory and I/O devices.

=--

bus

JDAL

The 22-bit address and 16-bit data path between the

KDAI transceivers and the J-11 microprocessor.

Instruction cycle -- The sequence of bus transactions involved in
the execution of an entire instruction by the J-11 microprocessor.
Transaction -- Either a KXJ11-CA address and data exchange or a
DMA master address and data exchange with the necessary handshake
signal

assertions.

——

DTC

Refers

controller.

the

28016

direct

memory

access

transfer

PIO —- Refers to the 278036 parallel I/O unit and counter/timer.
uPD7201 -- Refers to the NEC 7201 multiprotocol serial controller.

Also referred to as

Native
the

SLUZ2.

firmware -- ROM-based program that directs and coordinates

operation

the

KXJl1-CA,

and

allows

the

KXJ11-CA

interpret and respond to commands from the arbiter processor.

asynchronous
DL-compatible
the
to
Refers
DLART
to as
referred
Also
port.
console
the
as
used
tter
/transmi
receiver
SLUl.

RELATED SOFTWARE PRODUCTS

1.6

The toolkits listed below support the development of applications
on the KXJ11-CA. Refer to the Software Product Descriptions (SPDs)
for more detailed information.

Peripheral Processor Tool Kit -

SPD 12.70

Peripheral Processor Tool Kit -

SPD 13.25

MicroPower/Pascal-RSX, Version 2.3

SPD 14.83

MicroPower/Pascal-Micro/RSX, Version 2.3

SPD 18.21

RT-11,

RSX,

Version 2.3

Modular Executive and Microcomputer
software Development Toolset

Peripheral Processor Tool
Micro/RSX, Version 2.3

Kit -

SPD

MicroPower/Pascal-RT,

Version

Modular

Microcomputer

Executive

Software

and

Development

2.3

18.48

SPD 19.12

Toolset

MicroPower/Pascal-VMS,

Version

2.3

SPD 26.24

Modular Executive and Microcomputer
Software Development Toolset
l.7

The

AVAILABLE

OPTIONS

following option

available with

the

KXJ11-CA.

DLV11-KA
-EIA
to 20 mA converter. This option consists of the
DLV11-KB
EIA-to-20 mA converter unit and a BC21A-03 EIA interface
cable.
Detailed information is provided in the DLV11-KA EIA to 20
mA
Installation
Guide
(EK-DLVKA-IN),
the
DLV11-KA Maintenance
Print
Set
(MP00694),
and
the Microcomputer Interfaces Handbook
(EB-23144-18).
1.8

DOCUMENTS

This
User's
Guide
1s the primary reference in the documentation
package
that accompanies the KXJ11-CA. The other documents in the
package

include:

DCJ11 Microprocessor User's Guide
AmZ7Z8036/AmZ8536 Counter/Timer, Parallel I/O Technical Manual
uPD7201 Multiprotocol Serial Controller Technical Manual
Am9516/AmZ8016 DMA Controller Technical Manual
8254
DLART

Programmable
Data

Interval

Timer

Data

Sheet

KXJ11-CA Schematics
KXJ11-CA Firmware Listings

The
order number for the documentation package is EK-KXJCA-DK, 1if
additional
sets
are
required. The documentation package 1s also
referred

to as

Other documents

the KXJ11-CA Hardware Documentation Kit.
the

reader may find useful

include:

Title
Microcomputers and Memories Handbook
Microcomputer Interfaces Handbook
PDP-11 Architecture Handbook
TU58 Technical Manual
DLV11-KA EIA to 20 mA Installation Guide

Order Number
EB-20912-20
EB-23144-18
EB-23657-18
EK-OTU58-TM
EK-DLVKA-IN

DLV11-KA Maintenance

MP00694

These

documents

are

available

Set
from:

Digital Equipment Corporation
Accessories and Supplies Group
P.O. Box CS2008
Nashua, NH
03061

Attention:

Documentation

Products
1-6

CHAPTER 2
INSTALLATION

INTRODUCTION

2.1

This chapter describes how to install the KXJ11-CA module.
NOTE

the factory-shipped
changing
Before
make sure the
ion,
configurat
jumper
rs shown in
jumpe
match the
jumpers
the module
that
y
verif
Figure 2-1, and
in Section
ibed
descr
is operating as
2.7

Installation includes the following activities.

operating

appropriate jumpers.

characteristics

Determining power supply requirements.

Installing the board into a backplane.

Selecting

2.2

Selecting

and

installing

and connecting cables from serial and parallel

I/0 interfaces to external devices.
Verifying proper operation.

SELECTING OPERATING FEATURES

defined by jumper
geveral characteristics of the KXJ11-CA arestics
that are part
cteri
chara
the
settings. This section describes
to change
how
shows
also
It
ion.
of the factory-shipped configurat
these characteristics by changing the appropriate jumpers.

r settings. Table
Figure 2-1 illustrates the factory-shipped jumpe
ng. The sections
setti
r
jumpe
each
2-1 summarizes the meaning of
ng alternatives
setti
r
Jjumpe
us
vario
that follow describe the
available.

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o
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l
o][0d]¢BI[o0Ee] ’ Old o]ogn¢an[LFNoT1O]SSgNsOnD[o TzImNsVHOg9 znA1NsVHDmvT m #0 alHOLIMS 2ZLNNPEoNNS9eN LSLNNLN9YLUN
mL2

6L°IN

eROy

Table 2-1

Factory-Shipped Jumper Configuration

Function

Setting

Jumpers Installed

O-Bus Size

22 bits

M3 to M4

17775400

Ml to M2

SLU2 Channel A Receiver

Enabled

M10 to M1l1

SLU2 Channel A Transmitter

Enabled

M7 to M8

LLocked Instruction Enable

Disabled

M65 to M66

BREAK Enable

Enabled

M12 to M13

HALT Option Selection

MicroODT

M14 to M15

Power-Up Option Selection

Firmware

No jumper

PROM Addressing

15-bit

NOo jumper

SLUl Baud Rate

9600

M56 to M55

SLLU1 Transmitter

RS423

M62 to M61

SLUl Receiver

RS423

No jumper

SLLU2 Channel A Receiver

RS422

M34 to M33

SLU2 Channel B Transmitter

RS422

M38 to M36

SI,U2 Channel B Receiver

RS422

Real-Time Clock Interrupt

60 Hz

Boot/Self-test

QO-Bus Base Address

ID Switch Position

DMA

Requests

8036 Counter/Timer

Switch Position

to M6

Disabled

M60

M32
M30
M28
M26
M24

M51

to M59

to
to
to
to
to

M3l
M29
M27
M25
M23

to M50

M42 to M4l

M40
M20

to M39
to M21

M52 to M53

Note: The SLU2 Channel A Transmitter is not configured with
jumpers, but 1is configured Dby selecting appropriate signals on
connector Jl.

2.2.1
Boot/Self-test Switch
The
boot/self-test switch is a 16 position
the board is configured to execute firmware
upon power-up. It has three functions.
1.

switch that is used if
(rather than MicroODT)

It
determines
how
the KXJ11-CA will act when a
interrupt
condition
exists,
1including
whether
self-tests will run (see Section 3.5).
It
determines
whether
special
performed either by user code or

special
or not
|

interrupt
handling
by firmware.

It
determines
where
in
memory
the
on-board
PROM is
mapped.
There are two alternatives -- low memory or high
memory. The memory maps associated with low and high PROM
mapping are shown in Figures 2-2 and 2-3, respectively.

17777777

17774000
17773777

POWER UP

17773000

1/O PAGE

17772777

17770000
17767777

MONITOR AND
DIAGNOSTICS

17760000

17757777

NXM

Fa o

2200000
2177777

2174000
2173777

POWER
UP

2173000

NATIVE

2172777

FIRMWARE

2170000
2

167777

MONITOR AND
DIAGNOSTICS

2140000

2137777
USER PROM

2000000
1777777
RAM
77777

PROM/RAM SPACE

ADDRESSES 77777-0 MATCH ADDRESSES 2077777-2000000
MR-17263

Figure

2-2

Memory Mapping in Low Memory

PROM

2-4

17777777

17774000
17773777

17773000

POWER UP
/O PAGE

17772777

17770000

17767777

17760000

MONITOR AND
DIAGNOSTICS

17757777

220000éw

NXM

2177777

2174000

2173777

‘

2173000

POWER UP

NATIVE

2172777 |

FIRMWARE

2170000
2167777

2140000

MONITOR AND
DIAGNOSTICS

2137777

USER PROM
2000000
1777777
RAM

MR-17262

Figure 2-3

Memory Mapping PROM

in High Memory

The
location of the boot/self-test switch is shown in Figure 2-4.
Table
2-2
summarizes
the
functions associated with each switch
position.

[

S
BOOT/SELF-

IR W
e

—

TEST SWITCH

N
Figure

2-4

Boot/Self-test Switch

MR-16215

Boot/Self-test Switch Functions

Table 2-2

Special

Switch
Position
0

Interrupt

KXJ11-CA

PROM

Special Interrupt Response

Handling

Mapping

User PROM application code is

Firmware

Low

Firmware

Low

Firmware

Low

Application code is booted from
a TU58 via SLUl. Auto self-tests
are performed, then the TU58
primary bootstrap is executed.

Firmware

High

MicroODT is entered. No self-tests

Firmware

High

Auto self-tests are performed.
The KXJ11-CA awaits command from

Firmware

High

No self-tests are performed.
The KXJ11-CA awalits a command
from the arbiter via TPRO.

Firmware

High

Auto self-tests are performed
continuously. No application
code is booted or executed.
‘Loopback connectors (see
gection 2.5.3) are installed

None

High

User PROM application code is

User Code

Low

User Code

Low

User Code

Low

executed.

No self-tests

are

performed.

User PROM application code 1is

executed. Auto self-tests are

performed.

User PROM application code 1is

executed. Auto self-tests are

performed. The user (P)ROM
checksum test is also performed.

are performed.

the arbiter via TPRO.

for

these

executed.

tests.

No self-tests are

performed.

User PROM application code is

executed. Auto self-tests are

performed.
10

User PROM application code is

executed. Auto self-tests are

performed. The user (P)ROM
checksum test is also performed.

Table 2-2

Boot/Self-test Switch Functions

(Cont)

Special

Switch
Position

KXJ11-CA
Special Interrupt Response

Application code

booted

from

Interrupt
Handling

PROM
Mapping

User Code

High

User Code

High

User Code

High

User Code

High

None

High

a TU58 via SLUl. Auto self-tests
are performed, then the TU58
primary bootstrap is executed.

MicroODT
are

entered.

No self-tests

performed

Auto self-tests are performed.
The KXJ11-CA awaits a command
from the arbiter via TPRO.

No self-tests are performed.
The KXJ11-CA awaits a command
from the arbiter via TPRO.

Auto self-tests are performed
continuously. No application
code 1s booted or executed.
Loopback connectors (see
Section 2.5.3) are installed
for

these

tests.

Notes:

Switch position 6 is the factory-shipped configuration.

The
encoded
value
of
the boot/self-test switch position 1is
available
in the KXJCSRB register in bits <7:4>. For example,
switch position 1 would be encoded as 0001 in KXJCSRB <7:4>.

The
user
(P)ROM
checksum
test
1looks for a checksum at the
highest
word
address of user (P)ROM. Similarly, the firmware
checksum test looks for a checksum at the highest word address
of
the
firmware
PROM.
Either
checksum
1is
calculated and
checked according to the following DECPROM algorithm:
CHECKSUM = 0
FOR
I
=
number
of
PROM
addresses
to
be
checksumed
CHECKSUM = CHECKSUM + contents of address
(high order carry from addition is discarded)
CHECKSUM
NEXT

4.,

ROTATE_LEFT
ONE_ BIT

interrupt handling can be performed by user code in
Special
switch positions 8-15. This function is useful in applications
need to continue running after the Q-Bus signal BHALT or
that
the 0-Bus signal BINIT has been asserted. For switch positions
0 through 7, special interrupt handling is done by firmware.
2-8

Boot/Self-test Switch Functions (Cont)

Table 2-2

TIf the KXJ11-CA is in standalone mode, switch positions 5, 6,
13, and 14 should not be wused. These postions cause the
KXJ11-CA to idle and wait for a command. In standalone mode,
the KXJ11-CA will 1idle indefinitely, waiting for an arbiter

command that will never come.

2.2.2

Q-Bus Size

The KXJ11-CA may be configured to handle 16-, 18-, or 22-bit Q-Bus
addressing. This is accomplished with the Q-Bus size jumpers (see
Figure 2-5). 22-bit addressing is selected as part of the
factory-shipped configuration.

Description

Jumper Connection

M3 g

i M5

22-bit addressing selected*

M3 o

i M5

18-bit addressing selected

M3 g

o M5

- 16-bit addressing selected

M4 o
M4

o M6

I
Figure 2-5

o o

..... ——

O-Bus Size Selection

* Factory-shipped configuration

MR-16216

2.2.3

O-Bus Base Address Selection

processor boards, make sure each
I/0O
with multiple
systems
In
unique Q-Bus base address to distinguish the boards
a
has
board
from one another. This is accomplished on the KXJ11-CA by setting
the ID switch and installing or removing a jumper that connects Ml
and

M2.

Table 2-3 lists the base addresses that can be selected. Table 2-3
addresses. If the KXJ11-CA is configured for 16- or
22-bit
lists
the lower 16 or 18 bits of the addresses
use
addressing,
18-bit
specified

Table

2-3.

O-Bus Base Address Selection

Table 2-3
ID Switch Position

| Base Address
(Jumper IN)

Base Address

(Jumper OUT)

2
3
4
5
6
7

17760100
17760140
17760200
17760240
17760300
17760340

17762100
17762140
17762200
17762240
17762300
17762340

9
10
11

17775440
17775500
17775540

17777440
17777500
17777540

17775400+

12
13
14
15

17775600
17775640
17775700
17775740

17777400

17777600
17777640
17777700
17777740

* These switch positions disable the Q-Bus interface. That 1is, the
KXJ11-CA is

running

in standalone mode.

1 Factory-shipped configuration

Figure

2-6

shows the locations of jumper connections M1l and

M2,

and the ID switch. The factory-shipped base address is 17775400,
Description

Jumper Connection

Factory-shipped configuration

Base address = 17775400

S
— R

..... [

o M1
o M2

Figure 2-6

E—

O-Bus Base Address Selection

MR-16217

Requests

2.2.4

DMA

and

channel A transmitter.

DMA
requests
to
the
on-board DMA transfer controller (DTC) may
come from several sources. The KXJ11-CA has a set of jumpers which
enable
or
disable
DMA
requests
from:
(1)
the SLU2 channel A
(2) the SLU2 channel A transmitter, or (3) the on-board
receiver,
8036
PIO counter/timer. The location of these jumpers is shown 1in
Figure
2-7. Only
two
of
the
three
sources
may be specified
(jumpered)
at one time. The two sources that are jumpered as part
of
the
factory-shipped configuration are SLU2 channel A receiver
SLU2

Description

Jumper Connection

M1l
M10
oO——O

M9
O

M8
o)

M7
o)

Allows
DMA channel 0
channel A receiver?®*

M7
o)

channel 1 requests from
DMA
Allows
counter/timer

M1l
o)

M10
o

M8
M9
oO———oO

mMill1
0

M10
O

M9
o

M7
M8
oO———O0

connections

connect

M10

and

jumper

M9.

between

This

configuration is not supported.

M11

M10 M9

©O

1
Figure

I
2-7

SLUZ2

PIO

channel 1 requests from SLU2
DMA
Allows
channel A transmitter¥®
NOTE

not

requests from

DMA

Requests

* FPactory-shipped configuration

]

MR-16218

I.ocked Instruction Enable

2.2.5

the
The KXJ11-CA has a set of jumpers which enable or disableocked
interl
ASRB
and
TSTSET,
WRTLCK,
the
of
ic
locking characterist
instructions. The location of the jumpers is shown in Figure 2-8.
Locking 1is disabled as part of the factory-shipped configuration.
is
For most applications, locking must Dbe disabled. If locking the
1f
4
n
locatio
to
trap
a
cause
may
enabled, a O-Bus timeout
0-Bus 1is heavily 1loaded, and one of these instructions 1is
executed.

Jumper Connection

Description

M64 M65 M66
o)
o——o0

The locking characteristic of the WRTLCK,
TSTSET, and ASRB instructions is enabled
The locking characteristic of the WRTLCK,
TSTSET, and ASRB instructions 1is

M65 M66
o———o0

M64

M65

M66

I N=I

Figure 2-8

Locked Instruction Enable

* Factory-shipped configuration
2-13

.L—L::

disabled?*

M64
o

MR-1086-1235

2.2.6
There
BREAK

BREAK Enable Selection
1is
a
jumper on the board that enables or disables console
requests
from
SLU1l
(the on-board DLART) to the J-11. The
location
of
this
Jjumper
1is
shown
in
Figure
2-9. A BREAK is
generated
by
SLUl
when
a
console
terminal is attached to the
system
and the BREAK key on the console keyboard is pressed. When
BREAK
1is received, the J-11 executes MicroODT. BREAK requests are
enabled as part of the factory-shipped configuration.
Jumper Connection

Description

M13

o———o

MI12

Console BREAK requests enabled*

M13

M12

Console BREAK requests disabled

.....
M12

=17

[

M13

|
Figure

2-9

BREAK

Enable

Factory-shipped configuration

2-14

MR-16219

HALT Option Selection

2.2.7

A jumper on the KXJ11-CA determines what action will be taken if a
HALT instruction is executed in kernel mode. The location of this
is shown in Figure 2-10. The jumper affects the state of
jumper
bit 3 of the Maintenance Register (see Section 3.2.10). If the
(the factory-shipped configuration), a HALT
jumper 1is installed

instruction executed in kernel mode causes the processor to enter
jumper is not installed, the KXJ11-CA traps to
the
If
MicroODT.

location

1in kernel instruction space and sets bit 7 in the CPU
|

error

Jumper Connection

Description

M15

o—o0

M1l4

HALT
a
when
entered
is
MicroODT
instruction is executed in kernel mode*

M15

Ml4

KXJ11-CA

traps

location 4 in Kkernel

and sets bit 3 of the
space
instruction
CPU error register if a HALT instruction
is executed

.....

in kernel mode

G}___J/——osvnso o M14

Figure 2-10

]

HALT Option Selection

' * Factory-shipped configuration

MR-16220

Power-Up Option Selection

2.2.8

jumper (see Figure 2-11) determines what action the
The power-up
take when the board is powered up or reset. The
KXJ11-CA will
jumper affects the state of bit 2 of the Maintenance Register (see
the jumper is installed, the
if
power-up,
At
3.2.10).
Section
register cleared. This 1is
PS
the
enters MicroODT with
processor
jumper is not installed,
the
If
1.
as power-up option
also known
KXJ11-CA executes the
the
n),
configuratio
(factory-shipped
the
power-up (PC =
during
173000
code at location
firmware power-up
option 3. Only
power-up
as
known
PS = 340). This is also
173000,
power-up options 1 and 3

are used for the KXJ1l1-CA.

Jumper Connection

Description

Ml17

o——o0

M16

MicroODT is entered during power-up*

M17

M16

The

KXJ11-CA bootstraps through location

173000 during power-up*

.....

I
I:::

@J/&M17o oM16

Figure 2-11

Power-Up Option Selection

Factory-shipped configuration

2-16

[

MR-16221

PROM Addressing

2.2.9

The
KXJ11-CA
can .be jumpered to accommodate various PROM types.
The
location
of
the
PROM
addressing jumper is shown in Figure
2-12.
If
the
jumper
1is
not
installed, the on-board PROMs use
15-bit
addresses. PROMS such as the Intel 2764 (8K X 8) and 27128
(16K X
8)
wuse 15-bit addresses. If the jumper is installed, the
PROMs
use
16-bit
addresses. This accommodates PROMs such as the
Intel
27256
(32K X
8)
that
wuse 16-bit addresses. 15-bit PROM
factory-shipped
the
of
part
as
specified
is
addressing
configuration.

Description

Jumper Connection

M19

15-bit addressing selected*

M18

M19

16-bit addressing selected

M18

1
Figure

]
2-12

]

J@/g Wi

[

PROM Addressing

* Factory-shipped configuration

MR-16222

2.2.10

SLUl1 Baud Rate

The jumpers shown in Figure 2-13 select the default baud rate for
the SLUl transmitter and receiver. The default baud rate for SLU1
is set when the KXJ11-CA is powered up or reinitialized. This rate
can be changed under software control, if KXJCSRJK3> is set. Table
7-4 shows the various baud rates that can be selected. A default
baud rate of 9600 is specified as part of the factory-shipped
configuration.

Description

Jumper Connection

M60

M58

M56

o——o

o©

o——o0

Factory-shipped configuration

M59

9600 baud

M57
M55

M60 o o M5B9

M58 o o M57

M56 o o Mbb \

“
Figure

2-13

R
SLU1 Baud Rate

MR-16223

Table 2-4

Baud Rate

M56 to M55
|

38400

M58 to M57

M60 to M59

In
Out
Out
In
In
Out
Out

In
In
In
Out
Out
Out
Out

19200
9600%
4800
2400
1200
600
300

SLU1 Baud Rate Jumpering

Out
In
Out
In
Out
In
Out

Factory-shipped configuration

2.2.11

SLUl Transmitter

The
SLUl
transmitter can be jumpered to send either single-ended
(RS423)
or
differential
(RS422)
asynchronous
serial
data via
connector J3. The location of the jumpers is shown in Figure 2-14.
part of the factory-shipped
as
selected
1is
transmission
RS423
configuration.

Description

Jumper Connection

RS423 transmission selected?

M61

M63

M62

oO——0

M63

M62

RS422 transmission selected

M61

oO——0

..... =

I
Figure

JL_J =

2-14

SLUl Transmitter

* Pactory-shipped configuration
-

2-19

JG@/ -

MR-16224

2.2.12

SLUl1l Receiver

The SLUl receiver can be jumpered to receive either single-ended
(RS423) or differential (RS422) asynchronous serial data via
connector J3. The location of the jumper is shown in Figure 2-15.
RS423 reception 1is selected as part of the factory-shipped
configuration.

Jumper Connection

M48

Description

RS422 reception selected

M47

o——O0

RS423 reception selected®

M47
o

mimE

I
Figure 2-15

L_AL—::

M48

MR-16225

SLUl Receiver

* Factory-shipped configuration

2.2.13

SLU2 Channel A Receiver

The SLU2 channel A receiver can be jumpered to receive either
single-ended (RS423) or differential (RS422) serial data via
connector J1. The location of the jumpers is shown in Figure 2-16.
RS422 reception is selected as part of the factory-shipped
configuration.

Description

Jumper Connection

M34

o——o0

M33

RS422 reception selected*

M33

RS423 reception selected

M32
M30
M28
M26
M24

o—o0
o—o0
o———o0
o——0O
o—o0

M34

M32
M30
M28
M26
M24

O
o
o
o©
o

o
o
o
o
o

M3l
M29
M27
M25
M23

M34 o © M33

M32 o
M30 o
M28 0
M26 o

o M31
o M29
o M27
o M25

[

Figure 2-16

. L_L_—::

[
|E

M24 o o M23

N |I
SLU2 Channel A Receilver

* Factory-shipped configuration

MR-16226

2.2.14
SLU2 Channel B Transmitter
The
SLU2
channel
B
transmitter
can
be
Jjumpered
to
send
single-ended
(RS423),
differential (RS422), or party line (CCITT
R1360)
serial
data via connector J2. The location of the jumpers
is shown in Figure 2-17. RS422 transmission is selected as part of
the

factory-shipped

configuration.

Jumper Connection

Description

M38

RS422 transmission selected*

M46 M45 -M37 I
o

M35

M36

oO———o0
M51
M50

o)
M49

M38

RS423

transmission selected

M46

M45

M37

O——O0

M35

M36

M51

M50

M49

M38

M46

M45

O——0

M37

Party line

transmission selected

M35

o——O
M36

M51

M50

M49

.....

—

4Figure 2—17
*

Factory-shipped

(

M46 M45 M37 M36 M35
o

M51

M50 M49

SLU2 Channel B Transmitter
configuration
2—-22

MR-16227

2.2.15

SLU2 Channel B Receiver

jumpered
B receiver can be
channel
SLU2
The
differential (RS422), or party
(RS423),
single-ended
serial data via connector J2. Two groups of
R1360)
and shown in Figure 2-18. RS422 reception is
involved
part of the factory-shipped configuration.
- Description

M43

M42 o——o0
o——o0
M40

M4l
M39

M44 o

M43

M44

o
o

M42
M40

o
o

M44d
M42

o——o
o
o

M40

M4l
M39

M43
M4l
M39

M20

M21
M22

RS422 reception selected*

Jumper Connection

M20

RS423 reception selected

M21
M22

o
Z

M20
M21

Party line reception selected
|

M22

M44 0

o M43

o M20

M420

o M41

o M21

oM22

M40 o0 o M39

Figure 2-18

]

[

SLU2 Channel B Receiver

Factory-shipped configuration
2—-23

MR-16228

to receive
line (CCITT
jumpers are
selected as

2.2.16

Real-Time Clock

Interrupt

(the on-board DLART) can generate real-time clock interrupts
SILUlL
of 50 and 60 Hz. Jumpers M52, M53, and M54 select
frequencies
at
the 60 Hz real-time clock as input to the
or
Hz
50
the
either
interrupts are enabled, each clock
If
logic.
control
interrupt
"tick"TM results in a maskable priority level 6 interrupt request to
J-11. The location of the real-time clock interrupt
on-board
the
shown in Figure 2-19. A real-time clock rate of 60 Hz
1is
jumpers
is specified as part of the factory-shipped configuration.
Description

Jumper Connection
o)

60 Hz real-time clock selected*

M54
M53
M5
2

50 Hz real-time clock selected

M54
M53

M52

Figure 2-19

[

]

Real-Time Clock Interrupt

Factory-shipped configuration

[

MR-16229

POWER SUPPLY CONSIDERATIONS

2.3

When installing the KXJ11-CA, make sure the power supply can
handle the extra load presented by the board. The KXJ11-CA draws a
maximum of 6A at +5V. In addition, the KXJ11-CA draws a maximum of
1.4A at +12v, for systems with the DLV11-KA option, or .4A maximum
for systems without the DLV11-KA option. The board adds
at +12v,
2.7 ac loads and 1.0 dc loads to the bus.

'In standalone mode, at least four power fingers (backplane
connections) and four ground fingers for +5 Vdc must be connected
to the power supply. In addition, at least two power fingers and
two ground fingers for +12 Vdc must be connected to the power
supply.

2.4

INSTALLING THE KXJ11-CA INTO A BACKPLANE

The KXJ11-CA plugs into any DEC standard quad height Q-Bus
backplane (see Figure 2-20). No special backplane wiring or
jumpering is required to accommodate the KXJ11-CA. However, the
grant structure must be preserved if there are blank slots between
and the top of the backplane. This can be
KXJ11-CA
the
accomplished by inserting grant cards where appropriate (Figure
2-21 is an example of the use of grant cards.) The dual height
grant card (M8659) preserves grant continuity for slots A and B,
and grant card G7272 preserves both the DMA and interrupt grant
continuity for slot C. The KXJ11-CA board must also be configured
for the proper Q-Bus address size.

MA-12021

Figure 2-20

Backplane Installation

MR 12020

Figure

2.4.1

2-21

Using Grant

Edge Connector Pin Assignments

Table
2-5
summarizes
KXJ11-CA.
The
board
height

Cards

backplanes

the edge connector pin assignments for the
1is
designed to mate with DEC standard quad

for Q-Bus-based

systems.

Table 2-5
Component Side

KXJ11-CA

KXJ11-CA Pin Identification
Solder Side

KXJ11-CA

Signal

AAl
AB1
ACl
AD1
AE1
AF1
AH1
AJ1
AK1
ALl
AM1
AN1
APl
AR1
AS1
AT1

NC
NC
BDAL16 L
BDAL17 L
NC
NC
NC
GND
NC
NC
GND
BDMR L
BHALT L
NC
NC
GND

AA2
AB2
AC2
AD2
AE2
AF 2
AH2
AJ2
AK?2

+5V
NC
GND
NC
BDOUT L
BRPLY L
BDIN L
BSYNC L
BWTBT L

AS?2
AT?2
AU2
AV?2

BDMGO
BINIT
BDALO
BDAL]l

BAl
BB1
BC1
BD1
BE1l
BF1
BH1
BJ1
BK1
BL1
BM1
BN1
BP1
BR1
BS1
BT1
BU1
BV1

BDCOK H
BPOK H
BDAL1S8 L
BDAL19 L
BDAL20 L
BDALZ21 L
- NC
GND
NC
NC
GND
BSACK L
NC
NC
NC
GND
- NC
+5V

BA?2
BB2
BC2
BD2
BE2
BF2
BH?2
BJ?2
BK?2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

AUl
AV1

NC
+5VB

AL2
AM2
AN2
AP2
AR2

BIRQ4 L
BIAKI L
BIAKO L
BBS7 L
BDMGI L

+5V
NC
GND

L
L
L
L

+12V
BDAL2 L
BDAL3 L
BDAL4 L
BDALS L
BDAL6 L
BDAL7 L
BDALS8 L
BDAL9 L
BDAL10 L
BDAL11l L
BDALl12 L
BDAL13 L
BDALl1l4 L
BDAL15 L

Table 2-5

KXJ11-CA Pin Identification

Component Side

(Cont)

Solder Side

KXJ11-CA
Signal

CAl
CB1
CCl
CDhl1
CEl
CFl
CH1

NC
NC
NC
NC
NC
NC
NC

CA2
CB2
CC2
CD2
CE2
CF2
CH2

+5V
NC
GND
NC
NC
NC
NC

CL2

CN2

IAK L (Note 2)

CJl
CKl1

NC
NC

CL1

CJ2
CK?2

NC
NC

CM1

CM?2

CP1

CP2

CT2
CU2

NC
NC

CN1

CR1
CS1

NC
NC

CT1l
CU1l

GND
NC

DAl
DB1
DC1
DD1
DE1l

CVl

CR2
CS2

‘

IAK L (Note 2)

DMG L (Note 3)
DMG L (Note 3)

CVv2

NC
NC
NC
NC
NC

DA2
DB2
DC2
DD2
DE 2

DF1
DH1
DJ1
DK1
DL1
DM1
DN1
DP1
DR1
DS1

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

DF 2
DH2
DJ 2
DK 2
DL2
DM2
DN 2
DP2
DR2
DS2

+5V
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

DT1

GND

DT?2

DU1
DV1

NC
NC

DU2
DV 2

NC
NC

Notes:

Pin
daisy

Not

CM2

connected

1is

jumpered to pin CN2

for the

interrupt acknowledge

chain.

Pin CR2 is jumpered to pin CS2 for the DMA grant daisy chain.

2-28

CONNECTORS AND EXTERNAL CABLING

2.5

el I/O
The KXJ11-CA communicates with external devices via a parall
J3).
and
J2,
(J1,
tors
connec
connector (J4) and three serial I/0O
connectors and
This section specifies the pin assignments of these

lists the types of cables that can be used with each connector.
2.5.1

Parallel I/0 Interface (J4)

The parallel 1I/0 (PIO) interface signals appear at connector J4.
ft.
These signals are buffered. They can be driven over a 50 AMP
40-pin
a
with
cable
round
or
distance via a ribbon cable,
contact housing (AMP part number 746473-9) at each end. A PIO
cable is not provided with the KXJ11-CA. The following PIO cables
are recommended for use in the KXJ11 and are available from
Digital Equipment Corporation.

R shielded ribbon cable
L "mirror image" cable

BCO6
BCO5

Figure

connector.

pin assignments for J4, the parallel I/0

the

1lists

2-22

BOARD

BB DD FF J

LL NN RR TT VV

sG|sGglsclsg|sG|sG|SG|SG|SG|SG|C1|cCO|BO|B1|B2 B3 |B4 |B5|B6| B7

A7 | a6 |AB| A4 A3 |A2 |A1|AD| C3|C2|SG|SG SG|SG|SG|SG|SG|SG|SG|

ACEHKMPSUWYAACCEEHHKKMMPPSSUU
VIEW INTO THE CONNECTOR FROM THE MODULE EDGE

NOTE: SG = SIGNAL GROUND
AQ- A7=PORTA
BO-B7=PORTB
CO0-C3=PORTC
MR-12615

Figure 2-22

Parallel I/0 Interface Pin Assignments

2.5.2
Serial I/0 Lines (J1, J2, J3)
The KXJ11-CA has three serial I/0 lines.

SLU2

channel

line

(J1), a synchronous/asynchronous serial

with modem control

SLU2
channel
B
(J2), a synchronous/asynchronous
line without modem control

SLUl (J3),
control)

Each

serial

RS422/RS423

the

line

1is

with

the

the
KXJ11-CA
with
lines can be done by

asynchronous

compatible

protocols.

compatible

Serial
cables
and are

console

with

addition,

CCITT

R1360

party

a
4-20 mA current
using the DLV11-KA

serial

the

line

EIA

(no modem

RS232-C

SLU2

channel

line

protocol.

loop device
option.

(J2)

5-foot
connection

This
one

EIA

RS232-C
between
the

cable has a
and
a

and

Interfacing

via

the

1line
cables
must
be supplied by the user. The
are recommended for use for the J2 and J3 serial
available from Digital Equipment Corporation.

BC20N-05

serial

following
I/O lines

null

modem
cable for a direct
KXJ11-CA
-and an EIA terminal.

10-pin (2 x 5) AMP female connector on
25-pin RS232-C female connector on the

end

other.
BC21B-05

5-foot

between

This

EIA

the

cable

one

end

RS232-C

modem

KXJ11-CA

has

and

10-pin

25-pin

cable

a modem

AMP

RS232-C

for

connection

acoustic

coupler.
connector on

female

male

connector

the

other.
BC20M-50

50-foot

EIA

RS422

RS423

cable

connection
between the KXJ11-CA and a
Used
1in
applications
requiring high
speeds (up to 19.2 K baud), this cable

5)
The

All

AMP

female

designations

three

make

ground.

Because

sure

there

the

your

cable.

number

i1llustrates

the

each

are

direct

end.

shown

factory

(-)

Figure

2-23.

<configured

signal(s)

standard

for

standard

746473-9)

handle

outputs. If you change the configuration
1lines
to
handle single-ended inputs or

return

Corporation

own

and

lines

Equipment
part

inputs
and
the
serial

outputs,

signal

for

serial

differential
of
any
of

connector

for

remote processor.
data transmission
has a 10-pin (2 X

SLU2

cable

channel

40-pin

for

assignments

AMP

the

cable

available

from

SLU2

you
to

channel

are

tied

Digital

need

construct

may

used

connector

connection

for

Jl.

Figure

(J1).

(AMP

2-24

SLU

RECEIVE DATA-

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE
9

0|00 |0]|0O

O|0|®|O|O

PC BOARD

INDEX (NO PIN)

Z 1

+12 VDC FUSED

INDEXING KEY

RECEIVE DATA+

(16 X BAUD)

TRANSMIT DATA+

BAUD RATE CLOCK OUTPUT

CONNECTOR

MR-0586-0691

J2 and J3 Pin Assignments (10-Pin)

Figure 2-23

BOARD

04
02
D
B
RC | NC
SC
A
01

IS
cC
03

06
F
BA

08
J
RD

TM | RRR
H
E

10
L
DA
*
K
09

12
N
ST

14
R
RT

16
T
CS

18
\Y
CA

20
X
IC

22
z
DM

NC
M

RS | RDR | DMR| TRR | NC
Y
W
U
S
P

24
BB
RR

SD
AA
23

26
DD
CD
*
CcC
25

28
FF
¥

34
32
30
LL NN
JJ
TT | RSR | NC

TTR|
EE

NC | SDR|
KK
HH
31

38.
36
RR 1T
NC | STR|

40
\AY
SG

TR | CSR | RTR | 101
uu
SS
MM PP
39
37
35
33

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE
MR-12352

Figure 2-24

J1 Pin Assignments (40-Pin)

Tables 2-6 through 2-8 show the correspondence between the pins of
the standard connectors for the RS422/RS423, RS232, and CCITT
protocols, and the pins of Jl. These tables make it easy to
construct an appropriate cable. The KXJ11-CA register address
associated with each signal 1is specified in the last column of
table for ease of programmer reference. The register
each
descriptions in Chapters 3 and 6 provide further details.

Table 2-6

Pin Circuit Direction

RS422/RS423

Interface to Jl

Function

Protective Ground

To Modem

6
7

RD
RS

SHIELD

SPARE

RS-232 CCITT
CI

112

Send Data (+)

103

From Modem

Send Timing (+)

114

From Modem
To Modem

Receive Data (+)
Request to Send (+)

BB
CA

104
105

115

From Modem

Receive Timing (+)

From Modem

To Modem

DM
TR

From Modem
To Modem

Data Mode (+)
Terminal Ready (+)

CC
CD

107
108/2

RR
RL

From Modem

To Modem

Receiver Ready (+)

Remote Loop

109

1IC

From Modem

Incoming Call

SF/SR

To Modem

Select Frequency

To Modem

Terminal Timing (+)

From Modem

Test Mode

11
12
14

From Modem

Clear to Send (+)
Local Loop

Signal Rate Select

DA
AB

106

141

140

Pin
-

5,E

23,AA

6,F

8,J
13,P

17775702
17775704

18,V

14,R

16,T

25,CC

Gen.

22,12
33,M
26,DD

24 ,BB

9,K

Gen.

17777520

113

30,33

17777530

142

5,E

102
102b

3,C

10,L

40 ,W
2,B

RTR
CSR

37,SS
35,PP

DMR
TRR

To Modem

Receive Timing (-)
Clear to Send (-)

29
30

From Modem
From Modem

From Modem
To Modem

Data Mode (-)
Terminal Ready (-)

17,V
W
19,

31
32

RRR
SS

From Modem
To Modem

From Modem

TTR

To Modem

31,KK
38, TT
15,5
32,LL

Receiver Ready (-)
Select Standby
Signal Quality

Terminal Timing (-)

17777522

Terminal in Service

New Signal

17775700

Dummy

3,C

111

26
27

17775710
17777520

126

To Modem
From Modem
From Modem
To Modem

22
23
24
25

Dummy

17775710

SDR
STR
RDR
RSR

SPARE

17775720

17775700

20,X

125

Send Data (-)
Send Timing (-)
Receive Data (-)
Request to Send (-)

17775706
17777520

Signal Ground
Recelive Common

SG
RC

17777522

12,N

To Modem
From Modem

19
20

Location

116
CG

110

3,C

17777520

7,H
28 ,FF

Dummy

Gen.

27 ,EE

RS422/RS423 Interface to J1 (Cont)

Table 2-6

From Modem

To Modem

117

Standby Indication

l1,A

102a

Send Common

Location

RS-232 CCITT

Function

Pin Circuit Direction

Notes on Figure 2-23 and Table 2-6:

Pins K 9, 25 CC, and 28 FF are driven by dummy generators that
disable RL (CCITT 140), LL (CCITT 141), and SS (CCITT 116)

respectively.

The label NC indicates no connection.

3., The

suffix

1in

three-letter

label

(such as RDR)

signifies that the pin is associated with the return side of a
differential driver or receiver.

Circuit IS can be redefined to mean SF. Or IS can be redefined

as SR. In the second case, TM is also redefined as SI.
Table 2-7

Pin Circuit Direction

RS232-C Interface to Jl

CCITT

101
103
104

39,00
17775706
6,F
17775702
8,J

1
2
3

AA
BA
BB

To Modem
From Modem

Protective Ground
Transmitted Data
Received Data

From Modem

Data Set Ready

CA
CB

4
5
7

9
10

(From Modem) (+ DC Test Voltage)
(- DC Test Voltage)
(To Modem)

From Modem
-

SCB

From Modem

SBA

To Modem

From Modem

SBB

From Modem

SCF

From Modem

SCA

To Modem
To Modem

To Modem

Signal Ground

Request to Send
Clear to Send

To Modem
From Modem

Location

Function

Receliver Ready
Unassigned

105
106
107

102

109

18,v
16,T

17775704
17775700

22,2

17775710

40 ,W

24 ,BB 17775700

Secondary Carrier

122

Secondary Clear to

121

Secondary Trans-

118

Transmitter Clock

114

12,N

Secondary Received

119

Data

Receiver Clock

115

14,R

Secondary Request to

120

Data Terminal Ready

108/2

26 ,DD 17777520

Detector

Send

mitted

Data

Receiver Dibit Clock
Send

2-33

17777520

Table 2-7

RS232-C Interface to Jl1

Pin Circuit Direction
From Modem

Function

CCITT

Signal Quality

110

Detector

CE
CH/CI

From Modem
To Modem

Ring Indicator
Data Rate Selector

125
111

20,X
5,E

17775710
17777522

To Modem

External Transmitter

113

10,

17777530

To Modem

Force Busy

CCITT/V.35 Interface to J1

RS232

A
B
C
D
E

101
102
105
106
107‘

Protective Ground
Signal Ground
Request to Send
Ready for Sending
Data Set Ready

AA
AB
CA
CB
CC

109

108/1

To Modem

Connect

RCV Line Signal Det

J
R

108/2
125
104

To Modem
From Modem
From Modem

Data Terminal Ready
Calling Indicator
Received Data A

104

From Modem

Received

To Modem
From Modem
From Modem

From Modem

Data

Set

115

From Modem

Receive Timing A

115

From Modem

Receive

114

From Modem

Transmit Timing

103

To Modem

Transmit Data A

103

To Modem

Transmit

Data B

113

To Modem

Terminal

Timing

2.5.3

Loopback

114

From Modem

113

To Modem

Location

RS
CS
DM

39,00
40 ,W
18,V
16,T
22,7

17775704
17775700
17775710

24,BB

17775700

CD
CE
BB

TR
IC
RD

26,DD
20,X
8,J

17777520
17775710
17775702

Timing B

Transmit Timing A

RS449
SG

14,R

6,F

Terminal Timing A

Connectors

Data B

\Y/
Y

17777520

Clock

Function

3,C

112

Pin Circuit Direction

Location

22
23

Table 2-8

(Cont)

12,N

10,L

17777520
17777520
17775706

17777530

Loopback
connectors (not provided with the KXJ11-CA) are attached
to the serial or parallel communication ports to determine whether
or
not
they
are operating correctly (see Figure 2-25). They are
typically
used
in
conjunction
with
the
running of diagnostic
programs,
and
in
some firmware self-tests (see Sections 2.2.1).
These connectors may be ordered from Digital Equipment Corporation
or

may

built

the

user.

3
S

BOOT/SELF-TEST
SWITCH

SBC ID

SWITCH

‘

ég(N)PBACK

sséé!!:iii;\éfiéééga//////
1

RS 422 TEST

S1-1
ON

N
#

o |

S1-3 §S1-4
ON OFF

s1-5 S16 S1-7 S1-8 S1-9 $S1-10
ON OFF ON OFF OFF ON

RS423 TEST

S1-1
OFF

N
#

§1-2
ON

NECTORS

S§1-2 S1-3 S14
OFF OFF ON

S1-6
OFF

s1-6
ON

S1-7 S1-8 S1-9
OFF ON ON

S1-10
OFF
MR-11874

Figure

2-25

Loopback Connectors

There are three different types of loopback connectors available
from Digital. A 10-pin loopback connector (DEC part number H3270)
is plugged into either J2, to test SLU2 channel B, or into J3 to
1is
test SLUl. A 40-pin loopback connector (DEC part number H3022)
tor
connec
k
loopbac
This
A.
plugged into J1 to test SLU2 channel
(see
can also be configured to test RS422 or RS423 operation
pins
40
also
is
tor
connec
ck
Figure 2-25). The third type of loopba
(DEC part number H3021), and 1is plugged into J4 to test the
parallel

I/0 port.

2-35

2.6

ERROR DETECTION AND REPORTING WITH THE LEDS

LEDs on the edge of the KXJ11-CA board which the
four
are
There
native firmware uses to indicate the state of the board. These are
power-up Or
during
purposes
diagnostic
for
useful
especially
reinitialization.
These
LEDs
verify that the board is operating
there is a problem with the board, can help the
if
or,
properly
difficulty. Table 2-9 summarizes the conditions
the
locate
user
the

LEDs

can

indicate.

During power-up or reinitialization, all four LEDs are illuminated
second if they are working properly. When
1/2
approximately
for
the

KXJ11-CA

1is

installed

in a backplane

in a box,

the LEDs are

labeled L4 through L1 from left to right. If the KXJ11-CA runs 1its
the
of
setting
the
by
determined
is
(this
self-tests
switch), L4 is off and L3 - L1 should be on as the
boot/self-test
self-tests
run. If one of the self-tests fails, L4 is illuminated
- L1 indicate the test that failed. Self-tests are run in
L3
and
the order listed in Table 2-9. Thus, if a test fails, the user can
also determine which tests

all

(if

any)

passed.

the self-tests run without error,

the KXJ11-CA performs a

boot operation. The boot/self-test switch setting determines which
remains off and L3 - L1 indicate the
L4
performed.
1is
function
of the executing code. Note that the boot/self-test switch
status

may
run,
it

be set so self-tests are not run. If self-tests have not been
then L4 is off and L3 - L1 indicate the state of the board as

executes

code.

LED Display Definitions

Table 2-9
LEDs

Meaning

All

Can't

LEDs

for

1/2

sec.

at the start of a

power—-up or reinitialization operation

access

Control/Status

Registers

in I/0

jumper
power—-up
the
OR
error)
(fatal
page
precludes
which
installed,
is
(M16-M17)
self-tests

(in Micro ODT).

DMA or RTC test failed

RAM test

ROM checksum test failed

Serial line test of SLUl failed

Serial line test of SLU2 channel A failed

Serial line test of SLU2 channel B failed

failed

LED Display Definitions (Cont)

Table 2-9
LEDs

Meaning

Parallel port test failed

Auto

Loopback tests and auto self-tests running

0-Bus ODT mode

Unused

Waiting for command

Performing DTC load

TU58 primary bootstrap executing

Executing non-native code

self-tests running. Auto self-tests do not

require loopback connectors.

Quick LED Reference
LEDs

Meaning

gelf-test error detected

Fatal self—-test error detected

No self-test errors detected
Application running without error

Legend
X

Off
Don't

care

(either On or Off)

2.7
DIAGNOSTIC TESTING WITH XXDP+
The
KXJ11-CA
can
be
tested
by
running
XXDP+,
a
diagnostic
operating
system that is booted from the user's system disk. This
section
explains
how
to
run
the XXDP+ diagnostics to test the

KXJ11-CA.
More
information
User's Manual (AC-F348F-MC).

XXDP+

1is

found

When
vyou
have
successfully booted XXDP+
message
such
as
the
one
shown
below
terminal.
The
items
that
that are system dependent.
BOOTING

XXDP-

XXDP-SM
BOOTED

This

(underscore)

System

system
on the

disk, a
console
indicate values

VERSION

MEMORY
SYSTEM

RESTART

ADDR:

XXDP=

from the
appears

XXDP+

MONITOR

THIS

the

blank

the

FROM

NON-UNIBUS

When

are

TYPE

"period"

prompt

"H"

appears,

"H/L"

the

FOR HELP

user

types

ZKXA??2<CR>

initiates

the

running

the

tests.

The message

ZKA
_ .BIN

appears
on
the
console,
followed
by
several
1lines of
information
(the
underscore indicates characters that are
- dependent). Then the following message should appear.
USE

<ESC>

KXJ

FUNCTIONAL

SWR

HALT
TEST

OCTAL

FUNCTION

100000

HALT

040000

INHIBIT

13
12

020000
010000

ERROR SUMMARY
INHIBIT ERROR REPORTS
IOP IO# KNOWN GOOD FOR TESTING

004000

TEST

002000

ENABLE

001000

LOOP

000400

LOOP ON

000200

INHIBIT TEST NUMBER/TITLE

SWR

140000

NEW =

ERROR

STAND ALONE
ON

EXTENDED

IOP
MEMORY

TESTS

ERROR

TEST

SWR<6:0>

system
system

At this point, type <CR>, which runs the tests until an error 1s
detected. As the tests run, their results are displayed on the

console. If an error is detected, a self-explanatory error message

is displayed, and the tests halt if bit 15 in the SWR is set to 1.
The halt causes an entry into MicroODT. To continue after an error
has caused a halt,

type

PLCR>

using the console keyboard.

If no errors are detected, testing can be terminated by pressing
the ESCAPE key (which halts the KXJ11-CA (and causes microODT to
if the BREAK enable Jjumper 1is installed, or by
be entered)

pressing the BREAK key (which halts the arbiter).

CHAPTER 3
ARCHITECTURE

INTRODUCTION

3.1

chapter

This

explains
the

describes

architecture

the

KXJ11-CA and

the operation of the various user—accessible portions of

KXJ11-CA.

In the case of the on-board I/O devices (chips), more detailed
information 1is found 1in the technical manuals included in this
documentation package. This chapter describes how the I/0 devices
operate on the KXJ11-CA. The information in the chapter may differ
from the information in the technical manuals, since the technical
manuals only describe the operations on a chip level. The
differences, where they exist, are noted.
KXJ11-CA BLOCK DIAGRAM

3.2

Figure 3-1 illustrates the major operational elements and data
paths of the KXJ11-CA. The sections that follow describe the
important characteristics of

3.2.1

these components.

J-11 Microprocessor

The J-11 microprocessor operates at 14.0 Mhz. It contains a full
PDP-11 memory management unit (MMU) and executes the PDP-11
Extended Instruction Set (EIS). The processor also contains
microdiagnostics and console ODT. Cache memory and the Floating
Point Accelerator (FPA) are not included as part of the KXJ11-CA
architecture. The start address is fixed at 173000 and the restart
address is set at 173004. Status bits are used to determine the
reason for a restart. J-11 power-up options 1 and 3 can be
selected using jumper M17-Ml6.
3.2.2

RAM

The KXJ11-CA employs 256K X 1 dynamic RAM chips, and a 512 KB X 18
bit array 1is provided for memory and parity storage. RAM may be
accessed locally or may be configured as shared memory (accessible

both locally and from the Q-Bus) in quantities of 0 KB to 512 KB.
Shared memory 1is assignable 1in 8 KB blocks on 8 KB address
and if more than one block is configured, all blocks
boundaries,
are contigious. The memory is configured with the KXJCSRF and
and is enabled by a bit 1in the KXJCSRJ
KXJCSRH registers,
KXJCSRF contains the starting Q-Bus address, as well as
register.
the number of 8 KB blocks assigned to the shared memory. KXJCSRH
contains the ending Q-Bus address assigned to the shared memory.
Section 3.8 provides more details on shared memory and how to set
it

up.

3-1

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3.2.3

Two Port Register (TPR) File

The Two Port Register (TPR) File is a 16 word set of registers
that can be accessed either by the on-board J-11 microprocessor Or
by the 0-Bus. The TPR file is the primary means by which the Q-Bus
arbiter controls and communicates with the KXJ11-CA. There are
four groups of TPRs. TPRO through TPR3 1is a communication channel
between the KXJ11-CA native firmware and the arbiter. The other
three groups, TPR4 through TPR7, TPR8 through TPR11l, and TPR12

through TPR15, typically act as communication channels between the
user's application and the arbiter. All TPRs reside in the GAP
on-board gate array (DC7036B). The TPRs are enabled by a bit 1in
the KXJCSRD register. If TPRs are disabled, all TPRs except TPRO

are read-only from the arbiter side and always read as zeros.
Writes to any register except TPRO will time out 1f the TPRs are
disabled. Writing to TPRO with the TPRs disabled succeeds but
reads a zero. This allows writing to TPR0<K14> to cause a hardware
reset. Figure 3-2 illustrates the TPR file.

LOCAL ADDRESS

QBUS ADDRESS
(R/W) BASE + ID + 36

TPR15

17775036

(R’W) 34

TPR14

17775034

(R’W) 32

TPR13

17775032

(R/W) INTERRUPT ON WRITE 30
(LEVEL 5 VECTOR 134)

TPR12

(R’W) 26

(R/W) 24

‘

TPR11

‘

17775030

17775026

TPR10

17775024
17775022

(RO) STATUS, WRITES TIMEOUT

TPRO

(R/W) INTERRUPT ON WRITE

TPR8

17775020

(R’'W) 16

TPR7

17775016

TPR6

17775014

(RO) STATUS, WRITES TIMEOUT

TPRS

17775012

(R/W) INTERRUPT ON WRITE

TPR4

17775010

(R/W) 06

TPR3

17775006

(R/W) 04

TPR2

17775004

(RO) STATUS, WRITES TIMEOUT 02
(R/W) BASE + ID + 00

TPR1

17775002

TPRO

17775000

'(LEVEL 5 VECTOR 124)

(R’'W)

(LEVEL 5 VECTOR 120)

INTERRUPT ON WRITE

NON-MASKABLE RESTART TRAP
MR 17199

Figure 3-2

Two Port Register (TPR) File

following
The
-Communication Protocol
Arbiter/TPR
3.2.3.1
is implemented by KXJ11-CA firmware. It 1s used
protocol
general
handle arbiter commands when the arbiter is communicating with
to
TPRO through TPR4. If the user wants the
registers
KXJ11-CA
the
to be ready to receive a command from the ‘arbiter during
firmware
the boot/self-test switch should be set to positions 5
up,
power
or

(the command register) is tested to determine if it
TPRO
to receive a command. The KXJ11-CA is ready to
ready
is
receive a command only when all bits

2 .

them

into TPR2

parameters,

requires

command

the

The arbiter writes the command

The

completion

are

zero.

the arbiter loads

and/or TPR3.

arbiter

in TPRO

waits

the

for

into TPRO.

TPRO to be zero,

execution

the

indicating the

command

the

firmware.

that may have
errors
any
for
check
can
arbiter
The
the
examining
by
execution,
command
during
occurred
appropriate

bits

in TPRIl.

From the 0-Bus, TPRO can be interpreted or used
~-TPRO
3.2.3.2
in
three
different
ways:
as a KXJ11-CA control register, as a
test

or as

a Q-Bus ODT register.

NOTE

TPRO assumes that
of
description
This
bit 6 of KXJCSRJ (NMI ENable) is set.

bit 15 is cleared when TPRO is written from the Q-Bus, TPRO is
If
interpreted
as
a control register. If bit 15 is set when TPRO 1is
first

accessed

from

the

0Q-Bus,

TPRO

1is

interpreted as a test

register.
After
a
"Start Q-Bus ODT" command is issued (that 1is,
when
bit 3 is set while TPRO is used as a control register), TPRO
is
interpreted
as
a
0-Bus
ODT command register until an "Exit
ODT", "Proceed", or "Start Program" command is issued (that
O-Bus
or bit 3 is set). The sections that
4,
bit
15,
bit
wuntil
is,
bit descriptions for all three interpretations of
provide
follow
TPRO.

TPRO is always used as a "hard reset", which when set
of
14
Bit
O0O-Bus, causes a KXJ11-CA initialization that is handled
the
from

by the KXJ11-CA native firmware. A hardware or software
O-Bus ODT GO command disables non-maskable interrupts.

To avoid unpredictable

used

results,

reset or a

the user should not alter the TPRs

to pass parameters while a command or test is executing. The

descriptions in the sections that follow specify the TPRs are
bit
used to pass parameters for the various commands and tests.

After
or

any command,

without

error),

test, or Q-Bus ODT operation is executed (with
TPRO

cleared.

3-4

3.2.3.2.1 TPRO as a Control Register -- If TPRO is used as a
control register (Figure 3-3), a set bit in TPR0<9:0> specifies a
command. Only one command at a time can be specified. If any
parameters accompany a command, they are passed through TPR2 and
TPR3.
14

DIS

WRU

SHM

SHO

CON

SHM

DMA

oDT

NOP

SHOW

TC |

LOAD

TRAP

INIT
MR-17200

TPRO as a Control Register

Figure 3-3
Bits

Name

Description

TC I

Test/Control

Hard

Indicator

- When set, TPRO

is used as a test register. When cleared,
TPRO is used as a control register.

- When set, a local power-up

reset

sequence occurs during the write portion
current Q0-Bus cycle. The setting
the
of
any previously
cancels
bit
this
of
bit
this
Setting
operations.
invoked
causes a hardware reset and is equivalent
board. This occurs
the
to powering up
regardless of whether or not the native

1is installed, or if the TPRs or
firmware
non-maskable interrupts are enabled.

Not used (read/write)

13:11

WRU

you

are

When

set,

causes the

to write a value of 1 in TPR2Z,
firmware
indicating that the board is a KXJ11-CA.

Not used (read/write)

What

DIS SHM

Disable

shared

memory

When

set,

When

set,

bits

set, and
When
shared memory.
disables
disabled,
already
is
memory
shared
when
sets bit 15 of TPR1l to indicate a command
error.

SHOW SHM

Show

shared

memory

<22:13> of the starting address of shared
loaded into TPR2 bits <9:0>.
are
memory
pages to be shared minus
of
number
The
into TPR3. When set and
loaded
is
one
is disabled, sets bit
memory
shared
when
15

TPRI1.

3-5

Bits

Name

Description

Enable
shared memory - When set, enables
shared
memory. Bits <21:13> of the Q-Bus
starting address are taken from TPR2. The
number
of
pages
to be shared minus one

SHM

are

taken

from TPR3.

No
operation
- This bit is reserved for
use
by Digital Equipment Corporation. It
currently
has
no
effect
on
KXJ11-CA

NOP

operation.
SHO

CON

Show
configuration - When set, loads the
boot/self-test
switch
setting
into
TPR3<7:4>.
Also,
writes
TPR3<2:1> with
the
type
of
ROMs used on the board are
shown

TPR<2:1>

ROMs

00
01
10

8 K X 8
16 K X 8
32 K X 8

Not

used

Start
Q-Bus
ODT
- When set, forces the
KXJ11-CA
into
Q-Bus
ODT
mode. TPRO 1is
redefined
(see
Section 3.2.3.2.3) until
bit
15
(EXIT),
bit
3
(GO),
or bit 4
(PROCEED) is set.

ODT

below.

INIT

Restart/Initialize - When set, forces‘the
native
firmware
sequence.
If
(decimal),
the

to perform 1its power—-up
TPR3
contains
an
8
boot/self-test
switch

setting
is
used
to
determine
which
operations to perform. If TPR3 contains 0
through
7
(decimal), that value 1is used
instead
of
the
boot/self-test
switch
setting.
TPR3
values
greater
than
38
(decimal) are not valid.
DMA

LOAD

DMA

load - When set,
the

DTC.

TPR3

starts
1s

used

a chain load
to

pass

"segment tag" parameter, and TPR2 is used
to
pass
an
"offset tag" parameter of a
chain
control table (see Section 4.3.1).
After
the
operation is complete, bit 14
set and the contents of the
1is
TPR1
of
DTC
Status
Register
are
written
1into
TPR2.

Bits

Name

Description

TRAP

Trap - When set, causes a trap emulation.

(which
in TPR2
1is
vector
trap
The
contains
(which
contains the PC) and TPR3
The trap vector 1s assumed to
PSW).
the
in kernel

space.

3.2.3.2.2 TPRO as a Test Register -- If TPRO is used as a test
register (Figure 3-4), a set bit in TPR0<10:0> specifies a test.
Test results are passed
Only one test at a time can be specified.
After a test 1is
through TPR2 and TPR3 as described below.
The user application should be
completed, TPRO 1is <cleared.
reloaded after any of these tests are performed.
10

QBUS

TPR

SLU2

SLU1

PIO

QiR

TC |

RAM

CPU

BEVENT

ROM

CSR

DMA

TPRO as a Test Register

Figure 3-4

Bits

Name

TC I

Test/Control

indicator

- When set, TPRO

is used as a test register. When cleared,
TPRO is used as a control register.

Not used (read as zeros)

14:11

Description

TPR

write

test

When set, performs read and

tests on the local side of the TPR

TPR4 through TPR15 are set at
file.
upon completion of this test.

)

QIR

OIR

test

this

test

interrupt
interrupt

When

run.

set,

zero

tests the QO-Bus

The address of the
mechanism.
vector must be in TPR3 before

DMA

DMA controller test - When set, tests the

PIO

on-board DMA controller by performing DMA
transfers between memory locations.

test

- When set, tests the parallel

its
and
port
I/0
connector
loopback

J4 before this test

associated timers. A
must be installed on

1s run.

Bits

Name

SLUZ2

Description

SLU2

test

When

set,

tests

the

multiprotocol serial controller. Loopback
connectors
for
J1
and
J2
must
Dbe
installed
before this test is run. A one
in
TPR3
indicates
that
SLU2 channel A

will
that
zero

SLU1

BEVENT

CPU

ROM

be
tested. A two in TPR3 indicates
SLU2
channel
B
will be tested. A
in TPR3 indicates that SLU2 channels

and B will

SI.LU1

test

tested.

- When set,

tests

the console

serial line. A loopback connector must be
installed on J3 before this test is run.

BEVENT test - When set, verifies that the
be
can
(BEVENT)
interrupt
<clock
line
The
disabled.
and
asserted,
enabled,
BEVENT is at
with
associated
interrupt
priority level 6 with a vector of 100.

test

CPU

- When set,

tests the on-board

J-11 microprocessor.

test - When set, performs a checksum
ROM
on-board ROM. TPR3 must be
the
of
test
user (P)ROM and the
the
1f
1,
to
set
native

firmware

zero,

are

to be

tested,

or set

1if only the native firmware

1is

tested.

test

When

set,

performs a non-

RAM

CSR

CSR
test - When set, performs read tests
the
and
KXJCSRJ,
through
KXJCSRA
on
the
all
for
registers
control/status
other on-board I/O devices.

destructive

test of

all on-board RAM.

TPR2<10:0> indicate which test(s), if any, have failed (see Figure
Note the correspondence
A set bit indicates a failed test.
3-5).
by TPR0<K10:0>
specified
tests
the
and
TPR2<10:0>
between
respectively.

TPR2<15:11>

are unused.

and TPR3 provide detailed information about certain failed
TPR2
1in Table 3-1. Bits <15:12> of TPR3 (Figure
summarized
as
tests,
contain an octal value (see Figure 3-5), which indicates the
3-6)
last

test

it failed

(Figure 3-6).

the TPR2 error bit that was set plus one. For
equals
wvalue
This
failed, TPR3 bits <15:12> equal two,
test
RAM
the
example, if
since TPR2 bit 1 is the RAM test error bit.

TPR2 and TPR3 as Test Result Registers

3-1

TPR2 Bit

TPR3 Bit

Set.

Set

Definition

CSR

Bus
Bus
Bus
Bus
Bus

error at CSR address
error at QIR address
error at TPR address
error at SLU1l address
error at SLU2 address

Bus

error

Bus error at
Undefined

address

PIO

DMA controller

address

RAM error. TPR1 will have the NXM or parity
error
flags
set if appropriate. Otherwise

RAM

Bus error at SLU2 counter/timer address

OdOUTdE
|

Failed
Test

WDNEO

Table

the

data

read

did

not

match

the

data

written.

Undefined
error

CPU

Undefined

CLOCK

> W=
O

checksum

Native

Undefined
Clock interrupt not masked
Clock doesn't interrupt
Can't shut it off
Undefined

SLU1

N OOtk WO

firmware

ROM

interrupt
interrupt
interrupt
interrupt

not
not
not
not

Undefined

coovnUtd
LW
- O

level

masked at level 4
received
masked at level 4
received

Recieved data incorrect
No RCVR done, loopback open
Undefined

2 doesn't
SLU2 counter/timer

interrupt

Asych mode, data transfer incomplete
Synch mode, EOF-SDLC not received
Synch mode, data transfer incomplete
Synch/asynch mode, received data incorrect
Undefined

Status incorrect or no interrupt request
with "request to send" set
Status incorrect or no interrupt request

with
p—

SLU2

Undefined

XMTR
XMTR
RCVR
RCVR

User application (P)ROM checksum error
No user (P)ROM space exists
Undefined

"RS-422"

set

Status incorrect or no interrupt
with "terminal in service" set
3-9

request

TPR2 and TPR3 as Test Result Registers (Cont)

Table 3-1
Test

Failed

Set

TPR2 Bit

TPR3 Bit

Set

Definition

PIO

0
1

Undefined
Reset state

4
5
6
7

Interrupt not masked at level 4
Interrupt not received
Loop timeout, data transfer incomplete
Received data incorrect

DMA

2
3

incorrect
Timer did not start
Timer never stops

8-11

Undefined

1
2
3
4
5

OIR

TPR

)

0-Bus address undefined, access not tested
Channel interrupt not received
DMA channel hung (TC/EOP both cleared)
DMA aborted (EOP = 1 = NXM)
DMA data

error

6-11

Undefined

O0-Bus vector not defined

O-Bus interrupt request never posted

Undefined

Local

interrupt not masked at level 5

Local

interrupt not received

Interrupt

6-11

Undefined

The data read did not match the. data

NXM

2-11

interrupt

written
error

Undefined

acknowledge

didn't

request

clear

oo
,h,w N -

OCTAL CODE

TESTS FAILED

CSR TEST
RAM TEST
ROM TEST
CPU TEST
BEVENT TEST

SLU1 LOOPBACK TEST
SLU2 LOOPBACK AND
TIMER TEST

PARALLEL I/0 LOOPBACK

AND TIMER TEST

DMA TRANSFER TEST

QIR TEST

TWO PORT RAM TEST

13
MR-11678

TPR2 as a Test Result Register

Figure 3-5

15
]

]

CODE

09
,

]

DISCRETE ERRORS
|

]

DISCRETE BIT ENCODED ERROR OF LAST TEST

TEST CODE OF LAST
FAILED TEST

MR-11677

TPR3 as a Test Result Register

Figure 3-6

as a Q-Bus ODT Register -- When the KXJ11-CA is 1in
3.2.3.2.3 TPRO
This
0O-Bus ODT mode, TPRO is interpreted as shown in Figure 3-7.
is set.

interpretation of TPRO continues until bit 15

PRO

EXIT

OP EX
REG

DEP

OP EX
MEM

Description

Exit

ODT

When set, O-Bus ODT mode is

KXJ11-CA
The
exited.
command from the arbiter.

Not used (read/write)

TPRO as a Q-Bus ODT Register

Name

Bits

EXIT

Figure 3-7

then

awaits

Bits

Description

Name

the context of an
Proceed - When set,
restored and the
is
m
progra
interrupted
resumes at the
m
progra
the
of
execution

PRO

address specified by the restored PC.

program

Start

operation
of

the

When

set,

restart

1is performed and the execution

program begins at the PC address

passed through TPR3. The system bus 1is
A RESET 1instruction 1s
initialized.
ize the local 1I/0
initial
to
executed
and MMR3
5:13,0>
MMR0<1
The
devices.
DT,
Micro/O
by
zero
at
set
are
registers
when
system
this
on
zero
at
and are set
following
The
executed.
is
RESET
are cleared: PS, PIRQ, CPUERR,

registers

Memory System Error, and Floating. Point
Status. The system Memory Error Register
(177744) is cleared by Micro/ODT but does
not exist on the KXJ11-CA.

Deposit

DEP

- When set, the contents of TPR2

1into the current open memory
loaded
are
location or register.

REG

Open and examine register - When set, the
register specified by TPR3 is opened and
its contents are loaded into TPR2. The
registers are encoded in TPR3 as follows
(note that bit 11 of the PS selects the
register set):

Code
000000
000001
000002
000003
000004
000005

000006
000007
000010

PSW

Any

R6,
R7,

other

SP
PC

code will set bit 15 of TPR1,

indicating a command error.

MEM

Open and examine memory - When set, opens

location and deposits 1its
memory
a
contents in TPR2. The address of the
memory location has 22 bits. The six most
significant bits are obtained from the
six least significant bits of TPR2. The
lower 16 bits are obtained from TPR3.
3-12

—— The firmware uses TPR1 to record KXJ11-CA errors
This register is read-only from the Q-Bus but
3-8).
Figure
(see
can be read or written by the on-board J-11.

3.2.3.3

TPRI1

t$§$;

NXM
ERROR

cMD
ERR
DM

STATE

FATAL
ERR

)

SIH

PARITY

ERR

Figure

Bits

Name

CMD

3-8

TPR1

Description

Command error during
detected

ERR

Set when an error is
the execution of a

command.

DMA

DMA error - Set when the DTC aborts after
a DMA LOAD command from TPRO (bit 1) has

ERR

been

1issued.

Not used (read/write)

13
NXM

Non-existent

ERR

non-existent

memory

error

trap

Set

ocCcurs

when a
while

O-Bus ODT or self-tests are running.
PARITY

ERR

Parity
occurs

Not used

o))

running.

trap
Set when parity
error are
sts
self-te
or
ODT
Q-Bus
while

FATAL

ERR

Fatal

(read/write)

error

- Set when a fatal error 1is

during auto self-test,

detected

or QO-Bus

KXJ11-CA
The
self-test.
controlled
respond
not
does
and
able
becomes unavail
except
,
arbiter
the
any commands from
to
causes
which
14,
bit
the setting of TPRO
a hardware

SIH

USER

reset.

Set when
handling
1interrupt
Special
special
handles
code
application
user
handles
firmware
when
Clear
interrupts.
special interrupts.

Not used

(read/write)

Bits

Name

Description

2:0

STATE

State

Reflects

the

state

the

KXJ11-CA:

000

Zero State - KXJ11-CA not available.
commands should be sent from the
No

001

Power-up
KXJ11-CA

The
Self-test
Auto
auto
1its
performing
is

self-tests.

010

Dedicated
Test
State
The
boot/self-test
switch
1is
set
to
either
7
or 15. No commands should
be

sent

from the

ODT

011

OQ-Bus

100

Command - The KXJ11-CA
For
Waiting
waiting for a command
1idle and
is

The KXJ11-CA is

participating
in
a
operation.
Only
Q-Bus
should be sent from the

from the

101

Mode

0O-Bus.

O-Bus
ODT
ODT commands
Q-Bus.

arbiter.

Application From TU58 - The
Loading
1loading (or attempting
1is
KXJ11-CA
1load) a boot block from the TU58
to
serial
console
the
to
connected
line.

110

state is reserved
This
Reserved
future use by Digital Equipment
for

Corporation.

111

Application
User
Executing
executing
1is
KXJ11-CA
The

Code a user

application program.

indeterminate when
1is
STATE
that
Note
J-11 console ODT is active.

pass parameters required to
to
wused
1is
TPR2
-TPR2
3.2.3.4
execute
commands.
See the description of TPRO (Section 3.2.3.2)
This register
the commands and parameters that involve TPR2.
for
can be read or written by both the Q-Bus and the on-board J-11.

3.2.3.5
execute
through
involve
(Figure

TPR3 -- TPR3 1is used to pass parameters required to
commands or perform tests. Refer to Sections 3.2.3.2
3.2.3.2.3 for the commands, tests, and parameters that
TPR3. Upon hardware reset, TPR3 has the following format

3-9).

o oo, Jojojo]e
oo
[oTofoToof

Description

Name

Not used (read as zeros)

15:8

7:4

TPR3 Format During Hardware Reset

Figure 3-9

Bits

Boot/self-test

BOOT

encoded

switch

Reflects

position

the
the

boot/self-test switch.

Not used (read as zeros)

3:0
This

on-board J-11.

can

read or written by both the Q-Bus and the
~

3.2.3.6 TPR4 Through TPR15 -- 1If the TPRs are enabled and the
appropriate enable bit in KXJCSRD is set, registers TPR4 through
TPR15 are used by the user's application to pass status and

information between the 0-Bus arbiter and the KXJ1l1-CA.
control
From
All the TPRs may be read or written by the on-board J-11.
the
and
read-only
are
TPR9
and
however, TPR1l, TPR5,
the O0-Bus,
other TPRs are read/write.

and TPR1l2 from the Q-Bus cause maskable
Writes to TPR4, TPR8,
interrupts. The vectors associated with these interrupts
level 5
are 120, 124, and 134 respectively. The status of the enables and
interrupt requests are contained in the KXJCSRD register.

3.2.4

PROM and Firmware Control

The
operation
of
the
KXJ11-CA
1is
controlled by firmware that
resides
in
two
8K
X
8
PROMs (Intel 2764 or equivalent).
The
firmware occupies 8 KB of PROM space. The other 8 KB of PROM space
is
available
for
the user's application program. Note that PROM
data
at
addresses
2140000 through 2177777 also appears at other
addresses.
The address space from 2140000 - 2177777 is duplicated
three times for the 8K X 8 PROMs (see Figure 3-10).
|

If
you
want
to
enter your application in PROM, you will need a
PROM
programmer
and
a program called DECPROM or its equivalent.
Using
these
items, blast your new PROMs that contain both a copy
of the firmware and the application.
The procedure for doing§ this
is

explained

in Appendix

The
KXJ11-CA
can
also
accommodate
two 16K X 8 (Intel 27128 or
equivalent)
or
two
32K X 8 (Intel 27256 or equivalent) PROMs if
you need more than 8 KB of PROM for your application.
Figure 3-11
shows
how
address space is allocated for the 16K X 8 PROMs.
The
data
at
addresses
2100000
through
2177777 is duplicated once.
Figure
3-12
shows
the
address space allocation for the 32K X 8
PROMs.
There
1is
no duplication of address space when using the
8

PROMs.

The

firmware

always

occuplies 8

KB of

space.

8K X 8 PROMS

2177777
FIRMWARE

[ |

32K x

2140000

2000000
MR-17260

Figure

3-10

PROM Space Allocation
-

8K x

PROMs

16K X 8 PROMS
2177777

FIRMWARE

—

2140000

USER CODE

2100000

2000000
MR-17259

Figure 3-11

2177777

PROM Space Allocation
-

16K x 8

PROMs

- 32K X 8 PROMS
FIRMWARE

2140000

USER CODE

2000000
MR-17261

Figure 3-12

PROM Space Allocation
-~

32K x

PROMs

3.2.4.1
Firmware
Usage
Considerations
==
During power-up, the
firmware assigns PAR7 and PDR 7 in kernel I (instruction) space to
map
to
the I/0 page. Do not modify the mapping registers in your
program
if you continue to use your native firmware. In addition,
if
you
enable kernel D (data) space mapping, then PAR7 and PDR 7
in kernel data space must also be mapped to the I/O page.
If
firmware
application

commands
are
is
running on

going
to
be
issued
while
a
wuser
the KXJ11-CA, there must always be 128

bytes
available
on the kernel stack.
Upon entering the firmware
through a special interrupt condition (see Section 3.5), 128 bytes
should
be used on the kernel stack to save the user's context and
for internal work space.

Do
not
alter
MMRO, MMR3, or any of the kernel mapping registers
using
OBUS
ODT.
The registers may examined, but a command error
will
be returned in TPR1 if an attempt is made to write to any of
them.

When
using
firmware to load or start a user application program,
no
code
or
data
should be loaded into locations 157600 through
157777.
This is where the firmware stack resides.

In
order for the arbiter to communicate with the native firmware,
bit
6
of
KXJCSRJ
(NMI
enable)
must
be set. Note that if the
KXJ11-CA
executes a RESET instruction, KXJCSRJ 1is cleared.
Bit 6
of
KXJCSRD
(TPR
enable)
must also be set. When the firmware is
waiting
to
receive
a command or is in the process of exiting to
user code, it sets bit 6 of KXJCSRJ and bit 6 of KXJCSRD.

3.2.4.1.1 Self-tests
=~- The native firmware determines whether or
not
self-tests are to be performed, depending upon the setting of
the
Dboot/self-test
switch
(see
Section 2.2.1). A subset of the
self-tests
1is
called
the auto self-tests, and includes tests of
the
on-board
CPU,
RAM,
ROM,
control/status
registers (CSRs),
two-port
RAM
(TPR) registers, the line clock (BEVENT) mechanismn,
and
the
local
DMA mechanism. Test results are deposited in TPR2
and
TPR3
at
the
completion
of
the
auto
self-tests (Section
3.2.3.2.2). Test status is displayed on the LEDs (Table 2-9).
3.2.4.1.2 Booting
=-If
the
self-tests
run
successfully, the
firmware is then ready to boot the user's application specified by
the
setting
of
the
boot/self-test
switch (Section 2.2.1). The
application
can
be
booted
either
from ROM or from a TU58 tape
drive.
If the application is booted from ROM, the native firmware
transfers control to the application in ROM by emulating a trap to
location
24.
If
the
application
1is booted from a TU58, a boot

block

1is

port).

octal

the

wvalue of

execution

the

transferred

boot

to the KXJ11-CA via SLUl

first

240

byte

277,

transferred

operation

the

boot block

location

repeated

received
0.

is
a

(the console serial

boot

block matches

considered
match

alternately on TU58

valid

does

not

units

and

occur,

and

An application
memory, or by
operation that

may also be loaded into RAM through either shared
requesting the firmware to perform a DMA load
transfers the application from external Q-Bus

memory to the KXJ11-CA local memory. Once the application is in
local memory, KXJ11-CA processor execution is transferred to the
application by requesting the firmware to perform a Q-Bus ODIT "Go"
.
command

Firmware Vs. User-Designed Firmware -- The
Native
3.2.4.2
KXJ11-CA is shipped with firmware that is referred to as "native
firmware provides the KXJ11-CA with the
Native
firmware".
functions described in the sections that follow. The handling of
O-Bus exceptions, interrupts, and resets are all functions which
involve the native firmware.

If you wish to design your own firmware, your user—-designed
firmware should have an entry point at physical location 173004.
An entry point in firmware for location 173000 should also be
provided for power-up handling.
3.2.5

CPU ID Switch

A hex encoded ID switch is used to select either standalone or IOP
mode of operation. ID numbers range from O through 15, with 0 and

1 signifying standalone operation, and 2 through 15 signifying
system usage of the Q-Bus. The ID switch code can be read via
KXJCSRC. There are two jumpers (M3-M4 and M5-M6) that correspond

with the
backplane

address width (16-, 18-, or 22-bit) of the QO-Bus
being used. These jumpers determine the size of the

3.2.6

DMA Controller

memory decode required for shared memory.

16-bit DMA controller is addressed by the local processor as an

I/0 device. The DMA controller has two independent channels and
can perform transfers between any local 22-bit address and any
16-, 18-, or 22-bit Q-Bus bus address. Transfers can also be

performed

between any two local 22-bit addresses or any two Q-Bus

addresses. Word, high byte, and low byte operations are supported
locally. Only word operations are supported across the Q-Bus
Either the source or the destination may have
interface.
Words may be
incrementing, decrementing, or fixed addresses.
the DMA
through
£flow
they
as
compared with a mask register
ved
interlea
be
can
ns
operatio
DMA
controller or as they are read.
in
occur
may
or
channel,
other
the
with the 1local processor and
hardware
service
can
1
channel
or
0
various burst sizes. Channel
requests from SLU2 or the PIO, oOr can be invoked by software
commands after certain mask control bits are cleared.
3.2.7

Wake-Up Circuit

KXJ11-CA

board only).

The wake-up circuit
signal on the J-11

provides automatic generation of the INIT
to initialize the LOCAL system (i.e., the

The wake-up circuit does not support power

down sequencing, and assumes that +5V and +12V rise together.
O-Bus signals BDCOK and BPOK are used to synchronize the Q-Bus
with the LOCAL system bus. With Vcc rising in approximately 30 40 ms, power-up oOccurs in approximately 400 ms for standalone

mode, and 550 ms for peripheral processor mode.
3-19

3.2.8
The

KXJ11-CA
KXJ11-CA

Control

has

eight

Status

Control
sections

and
Status
Registers,
and
that follow.
All the KXJ1ll
the

3.2.8.1
KXJ11
Control/Status
control

cleared

SLU2

upon

operation

on-board

gate

that

the

and

the

real

are

used

board.

They

monitor

are

the

and

KXJ1l

both
are
described in
Control/Status Registers

the
are

arrays.

- Control/Status
Register
A
(Figure

hardware

Registers

registers

control

contained

overall

and

A
used

(KXJCSRA)
to monitor and

time

clock

(RTC).

This

1is

reset.

ADDRESS: 17777520

oooooo
oooooo
oooooo
oooooo
......

ololojJojof[o]o|oO

o
ooooooo
ooooo

CNTIE

TERM

|SYNCM A|SYNCM B

RTCIE

SER
TT 108/2

SLuzs
EN
MR-17146

Figure

Bits

Name

3-13

KXJ11l

Control/Status

Description

15:8

Not

used

(read

ones)

CNT

1IE

Programmable
counter
interrupt enable When
set,
1interrupts
£from programmable
timer/counter
2
are
enabled.
When
cleared, these interrupts are inhibited.

RTC

1IE

Real

time
clock
set,
interrupts
line-time
clock

5
4

TERM

SER

interrupt

enable - When
from
the
on-board
(LTC) are enabled. When

cleared,

these

Not

(read/write)

used

interrupts

are

disabled.

Terminal
in
service
For
wuse
with
modems.
When
set,
Terminal
1In Service
(IS)
1s
asserted and incoming calls can
be
connected.
When
cleared,
IS is not
asserted.

TT108/2

Modem
connected
For use with modems.
When
set,
Terminal
Ready
(TR)
1is
asserted.
When
cleared,
TR
1is
not
asserted.

Bits

Name

‘Description

SYNCM A

Clock

channel A - When set, SLU2

select

1its clock from the
channel A receives
When
generator.
rate
baud
on-board
clock
1its
channel A receives
cleared,
from an external

Party

SLU2BR EN

KXJ11-CA

source.

enable

line

configured

1is

Used
for

when

the

party line

channel B
SLU2
set,
When
operation.
When
data.
line
party
receive
cannot
for
n
1line data receptio
party
cleared,
channel B

channel B - When set, SLU2

select

Clock

SYNCM B

is enabled.

1its <clock from the
receives
channel B
When
generator.
rate
baud
on-board
clock
1its
receives
channel B
cleared,
from an external

source.

==
(KXJCSRB)
B
Register
Control/Status
3.2.8.2 KXJ11
the
Control/Status Register B (Figure 3-14) 1is used to monitor
state of the boot/self-test switch, the base address jumper, the
bus size jumpers, and the SLU2 modem test function. The register
is read-only, with the exception of Dbits <7:4>, which are
read/write.

ADDRESS: 17777522

15
0

14
0

13
0]

0]O0

-l

BST

BUS

S{ZE

BASE

TT142
MR-17773

Figure 3-14

KXJ11l Control/Status Register B

Bits

Name

Description
Not

used

low

zeros)

addresses.

Base address jumper - When set, indicates
that
the
Q-Bus
base
address jumper 1is
installed
(see
Section 2.2.3). This bit
is
loaded
during
hardware
reset
and

BASE

cannot
2:1

Boot/self-test
switch
Contains
the
encoded
value
of
the
boot/self-test
switch
position (see Section 2.2.1 for a
description
of
the
boot/self-test
switch).
0000
corresponds
to
switch
position
0,
0001
corresponds to switch
position
1,
and
so
on. These bits are
read/write.
BST
is
1loaded
with
the
encoded
value
of
the
boot/self-test
switch
during hardware reset, and can be
changed
by the user's software. Exercise
caution
when
writing
BST,
since
it
controls
the
mapping
of ROM to high or

BST

(read

BUS

changed

software.

Bus
size
jumpers
- Indicates the Q-Bus
size jumper settings (see Section 2.2.2).
This
bit
is
1loaded upon hardware reset
and cannot be changed by software.

SIZE

Bus Size

Address Bits Used

00
01
10
11
0

22
16
18
Reserved

Modem test - When set, indicates that the
modem
connected
to SLU2 channel A is 1in
test
mode.
When cleared, indicates that
the
modem
1is
not in test mode. Cleared

TT142

upon

hardware

reset.

3.2.8.3
KXJ1l1
Control/Status
the

state

Control/Status
Register
C
(KXJCSRC)
-KXJll1
Register
C
(Figure 3-15) contains information on
the CPU 1ID s witch and the state of the on-board LEDs.

ADDRESS: 17777524
13

0Ojo0]oO0

0Ol]o}|

]

01
'
LED

]

MR-17174

Figure

3-15

KXJ11l

Control/Status

Bits

Description

Name

Not used (read as zeros)

15:8

7:4

Contains

switch

CPU

the encoded

value of the CPU ID switch position. 0000
position 0, 0001
switch
to
corresponds
to switch position 1, and so
corresponds
These bits are read-only. These Dbits
on.
and
reset
hardware
during
loaded
are
cannot be changed by software.

3:0

LLED state - Each bit determines the state

LED

one of the four on-board LEDs. LEDs 4
of
<K3:0>
to Dbits
correspond
1
through
respectively. If a bit is set, the LED 1is
If a bit is cleared, the LED 1is OFF.
ON.
to determine the
read
are
bits
These
of the LEDs, or are written to set
state
during hardware

are

bits

These

LEDs.

the

set

to one

reset.

Control/Status Register D (KXJCSRD) -- KXJl1
3.2.8.4 KXJ11
D (Figure 3-16) monitors and controls the
Register
Control/Status
Q-Bus reset/interrupt mechanism. This
the
and
QIR, the TPRs,
Access is read/write.
reset.
during
cleared
register is
ADDRESS: 17777530

PWRFL

IQIR

QIR REQ

QB
BQIR
EN

RQST

BHALT
IE

QB
RESET

IE<124>

TPR
EN

RQ<134>

Figure 3-16

TPR | IE<134>|1E<120> |RQ<124>

BHALT

RESET

RQ<120>
MR-17175

KXJ11 Control/Status Register D

Bits

Name

Description

PWRFL

Power

fail

When

set, the Q-Bus has

a power
indicating
BPOK,
deasserted
BPOK
that
s
indicate
clear,
When
failure.
cleared
be
should
bit
This
asserted.
is
after a PWRFL special interrupt.

Bits

Name

QIR

Description
QIR
request
When set, indicates that
the QIR has been written and that a QO-Bus
interrupt
1s
pending.
Clearing QIR REQ
after
it has been set clears the pending
request
to the Q-Bus. The deassertion of
the
O0O-Bus
signal
BIAKI clears QIR REQ.
This
bit
cannot be set by the user. QIR

REQ

has

operating
13

IOIR

meaning

the

KXJ11-CA

1is

standalone mode.

QIR interrupt enable for J-11 - When set,
the
on-board
J-11
receives
a
level 5
interrupt request for vector 130 when any
of the following situations occur.

When BIAKI is asserted as part of the
O-Bus interrupt handling sequence.

When bit
cleared
has been

When
Q-Bus

14 (QIR REQ)
before
the
serviced.

BINIT
1s
interrupt

is set and then
Q-Bus interrupt

asserted
before the
has been serviced.

If
IQIR
1IE is set, the arbiter causes a
local
level
5
interrupt
when
it
acknowledges a QIR interrupt.
12

BQIR

QIR

1interrupt

When

set,

enable

enables

for Q-Bus

the

Q-Bus

master
master

participate
1in Q-Bus interrupt handling.
When
BQIR
EN is set and J-11 writes the
vector, the 0-Bus master receives a level
4 interrupt request for the vector in the
QIR
register.
When
cleared,
Q-Bus
interrupt
requests
are
blocked
from
reaching the Q-Bus master.
11

O-Bus
reset
- Set when bit 10 (QB RESET
is IE) and bit 6 KXJCSRJ (NMI EN) 1is set,
a
special interrupt condition is that is
handled
by
the KXJ11-CA native firmware
(see
Section
3.5 for details). This bit

RESET

should

special
10

RESET

be
cleared
interrupt.

after

Q-Bus
reset interrupt enable
enables
the
KXJ11-CA
to
assertion of the Q-Bus signal

set,

and

(OB

RESET)

KXJ11-CA
the

when BINIT

set.

1is prevented

assertion
3-24

1is
of

BINIT.

- When set,
detect
the
BINIT. When

asserted,

When

RESET

bit

cleared,

from responding

11
the

Bits

Description

Name

Bus

BHALT

bit

halt - Set when bit 8

(BHALT IE) and

is set,

(NMI EN)

6 KXJCSRJ

and BHALT

is asserted. When BHALT is set, a specilal
1is
that
exists
condition
interrupt
the KXJ11-CA native firmware
handled by
Section 3.5). Firmware handles this
(see
trap through vector 24.
a
emulating
by
This

bit should be cleared after a BHALT

special
BHALT

- When set,
enable
interrupt
halt
Bus
the
detect
to
KXJ11-CA
the
enables
When
BHALT.
signal
Q-Bus
the
of
assertion
BHALT is asserted, bit 9
and when
set,
the
When cleared,
set.
is
(BHALT)

KXJ11-CA
the

TPR

RQST

interrupt.

TPR

1is prevented from responding to

assertion of

restart

BHALT.

request

Set

Dby a QO-Bus

write to TPRO when KXJCSRJ bit 6 (NMI EN)
indicates an exception
This
set.
is

condition that is handled by the KXJ11-CA
This bit cannot be set
firmware.
native
set,
is
RQOST
TPR
Once
directly.
cause
not
do
TPRO
to
writes
nt
subseque
This bit is cleared by
exceptions.
more
when the
firmware
native
KXJ11-CA
the
.
execution
d
complete
has
command

TPR

the
allows
set,
When
-~
enable
TPR
accessed
be
to
file
TPR
the
of
contents
from the O0-Bus. When cleared, forces the
from the TPR file
=zeros
to read
O-Bus
All TPRs except
out).
time
will
(writes
by this
disabled
and
are enabled
TPRO
the
from
le
accessib
always
1is
TPRO
bit.
O-Bus.

IE<134>
I1E<124>
IE<120>

TPR interrupt enables - When each bit 1is
set, a TPR interrupt enables a level 5

a
occur when
to
request
interrupt
IE<134>
written.
is
TPR
particular
from TPR12
requests
interrupt
controls
for vector

134.

controls interrupt requests from
IE<124>
1IE<120> controls
124.
for vector
TPR8
TPR4 for vector
from
requests
interrupt
the
<cleared,
is
bit
a
When
120.
is
request
t
interrup
corresponding
blocked.

Bits

Name

Description

2:0

RQO<134>
RO<K124>
RO<K120>

TPR request flags - When each bit is
set, TPR request flags indicate that a
particular TPR has been written. RQ<K134>,
RQ<124>,
and
RQ<K120>
corresponds
to
TPR12,
TPR8,
and
TPR4 respectively. If
the
corresponding
1IE<K134>,
1IE<K124>, or
IE<120>
bit
1is
also
set,
a
1level
5
interrupt occurs when the TPR is written.

3.2.8.5
KXJ1ll1
Control/Status
Register
E
(KXJCSRE)
Control/status
register
E
1is
a
dummy
register
provided
for
software compatibility with the corresponding reserved register on
the
KXT11-CA.
This register can be read and written, but writes.
to the register do not affect KXJ11-CA operation, and reads to the
register
always
produce
zeros.
The
address
of
KXJCSRE
1is
17777526.

3.2.8.6
KXJl1
Control/Status
the

Control/Status
Register
F
(KXJCSRF)
==
KXJ1l1
Register F (Figure 3-17) defines the lower limit of

shared memory

is
defined
by
3.2.8.7).
This

space

accessible

the

Q-Bus.

The

upper

limit

KXJ11
Control/Status
Register
H
(see
Section
register is initialized to a value of 177600 upon

power-up.

ADDRESS: 17777534

]

1
STA ADD

]

Figure 3-17

]

KXJ11l

Control/Status Register F

Bits

Name

Description

15:7

STA ADD

Starting
address
Contains
the
most
significant nine bits of a Q-Bus starting
address. The starting address defines the
beginning
of
the shared memory space on
this
board
that
1is
accessible
to the
Q-Bus. STA ADD corresponds to BDAL<K21:13>
at
address
time.
These
bits
are
read/write
and
are
unaffected
by
a

6:0

hardware

reset.

Not

(read

used

zeros)

Control/Status Register H (KXJCSRH) -- KXJll
3.2.8.7 KXJ1l1
r H (Figure 3-18) defines the upper limit of
Registe
control/Status
the shared memory space accessible to the Q-Bus. The register
also contains the number of blocks in this memory space. The
lower 1limit is defined by KXJ11 Control/Status Register F (see
This register 1is initialized to a value of
Section 3.2.8.6).
177777

during power-up.

ADDRESS: 17777536

]

13 12
|

]

END ADD

]

SO0

SO
......

.......

04 03
I

NUM BLK

]

]
MR-17178

KXJ11l Control/Status Register H

Figure 3-18

Bits

Name

Description

15:7

END ADD

Ending

address

- Contains the nine most

bits

significant

0Q-Bus

ending

board's shared memory.
the
for
address
is defined as the
The ending address

last 8K block of
the
first address of
memory (see
shared
accessible
O-Bus
for an example of the use
Section 3.8.1

The KXJ11-CA compares END
END ADD).
of
to
on the Q-Bus,
ADD with addresses

determine the 0-Bus addresses that refer
shared memory. END ADD
board's
the
to
at address
corresponds to BDAL<K21:13>
and are
rite
read/w
These bits are
time.
unaffected by a hardware reset.

Not used (read/write)

5:0

NUM BLK

Number

of blocks - Contains a value that

represents

the

accessible

the

shared

number of 8 KB blocks in

memory

the

space

that

are

Q-Bus. This value is

derived from the starting address of the
0-Bus shared memory and the number of
blocks to be shared (see Section 3.8).
Since

the shared memory is 512 KB, up to

KB blocks can be specified. These
8
64
bits are read/write and are unaffected by
a

hardware

reset.

3.2.8.8
KXJ11
Control/Status
Register
J
(KXJCSRJ)
-KXJ1l1
Control/Status
Register
J
(KXJCSRJ)
(Figure
3-19) enables and
disables
the
non-maskable
interrupts (power fail, BINIT, BHALT,
and
TPRO
writes).
KXJCSRJ also indicates if timeouts for DMA or
bus-locked
operations
have
occurred.
KXJCSRJ determines if the
baud

rate

shared

specifies
register

for

SLUl

memory

can

parity
1is

under

software

accessed

characteristics

read/write

and

control,

from

the

for

cleared

and

determines

0Q-Bus.

the

on-board

upon

hardware

KXJCSRJ

also

RAM.

This

software

reset.

ADDRESS: 17777540
15

Figure 3-19
Bits

Name

SACK

BAUD

TOUT

RATE

PAR

Description
Not

used

(read

Not

used

(read/write)

NMI

SACK

OO0

KXJ11 Control/Status Register J

15:8

TOUT

zeros)

Non-maskable
interrupt
enable
When
written
with a 1, enables recognition of
interrupts
from
the
following sources:
power failures, the assertion of BINIT or
BHALT,
and
interrupts
that result from
writing TPRO. When NMI EN is written with
a
0,
disables
recognition
of
the
interrupts
from
the
sources
listed
previously.

SACK
timeout
Set if a DMA request to
the
O0-Bus
1is not granted in the alotted
time
(approximately
140
wus). May occur
when the Q-Bus is heavily loaded with DMA
activity from multiple devices. Writing a

1
has
no
effect
on this bit. This bit
must
be
explicitly cleared by writing a
ZE€ro.

LOCK

TOUT

Lock

timeout

Set

when

bus

locked

instruction
(WRTLCK, TSTSET, or ASRB) 1is
executing locally and access to the Q-Bus
cannot
be
obtained
1in the alotted time
(approximately
140
wus). Writing a 1 has
no
effect
on this bit. This bit must be
explicitly cleared by writing a zero.
3-28

Bits

Name

Description

BAUD RATE

Baud

- When set, the baud rate for

rate

SLUl is under software control, according

to the value written to PB in the Console
Status Register (XCSR). When
Transmitter
baud rate is determined by
the
cleared,
jumpers.

the SLUl baud rate

set,

When

enable

O-Bus

QOB ENB

enables the

shared
KXJ11-CA
the
access
to
O-Bus
it has been allocated. When
that
memory
to the
access
Q-Bus
prevents
cleared,
shared memory.

WR PAR

Write

parity - When set, generates wrong

Does

not

parity

writes

write

the on-board RAM.

parity on writes

wrong

from MicroODT.

enable - When set, enables parity

Parity

PAR ENB

to be detected. If a parity error
errors
parity
non-maskable
a
detected,
is
associated
an
with
occurs
interrupt
parity
When cleared,
114.
of
vector

3.2.9

ignored.

are

errors

O-Bus Interrupt Register (QIR)

The O-Bus Interrupt Register (QIR) (Figure 3-20) is used by the
KXJ11-CA to interrupt the arbiter. When the KXJ11-CA initiates a
it loads an interrupt vector into the 0Q-Bus
interrupt,
O-Bus
This causes bit 14 in KXJ11-CA Control/Status
Register.
t
Interrup
3.2.8.4) to be set. It then asserts BIRQ4
Section
(see
D
Register
(BQIR EN) of Control/Status Register D 1is
12
bit
if
on the 0O-Bus,
the content of the QIR register on the
drives
The KXJ11-CA
set.
and bit 12 of Control/Status Register
BIAKI,
receives
0-Bus, if it
clears bit 14 in KXJCSRD. This
BIAKI
of
receipt
The
D is set.
|

ADDRESS: 17777532

0|0

11 10

01010}

|
I

07
SR

L
R

05
VEC
WA

|
N

|
S

0
MR-17205

Figure 3-20

O-Bus Interrupt Register (QIR)

Bits

Description

Name

Must

15:10

zero

Vector
Contains
the interrupt vector
used
to service the KXJ11-CA's interrupt
to the Q-Bus. These bits are not affected
by a hardware reset.

VEC

Must

1:0

zero

Maintenance Register
3.2.10
Maintenance
Register
(Figure
The
power-up

status of
unaffected

options were

selected by

the QO-Bus signal BPOK.
by

hardware

3-21) indicates which halt
the user. It also indicates

This register

read-only and

and
the

reset.

ADDRESS: 17777750
15

Of|

HLT

BPOK

PUP
MODE
MR-17206

Figure

Bits

3-21

Maintenance

Description

Name

11110110

0011,

indicating

the

CPU

code

for

the

KXJ11-CA.

Halt
When set, indicates that M15 and
M14
are
not
Jjumpered
together.
When
cleared,
1indicates
that M15 and M14 are
jumpered
together.
The M15 - M1l4 jumper
determines
what action the KXJ11-CA will
take if a HALT instruction is executed 1in
kernel mode (see Section 2.2.7).

HLT

PUP

MODE

Power-up
mode - When set, indicates that
M16
and
M17
are not jumpered together.
When
c¢leared, indicates that M16 and M17
are
jumpered
together.
The
Ml6
- M17
jumper
determines
how the KXJ11-CA will
act when the board is powered up or reset
(see Section 2.2.8).
Must

BPOK

BPOK
BPOK

status
1is

Set when the Q-Bus

asserted.

3-30

signa
‘

Program Interrupt Request (PIRQ) Register
3.2.11
Register provides seven
(PIRQ)
The Program Interrupt Request
for the on board J-11
y
capabilit
levels of software interrupt

microprocessor. An interrupt is queued Dby setting one of bits
<15:9>, which correspond to interrupt priority levels 7 through 1
Bits <7:5> and <3:1> are set by the on board J-11
respectively.
to the encoded value of the highest pending request. When the
interrupt request is granted, the J-11 traps through location 240
The wuser's interrupt service routine must
in kernel I space.
clear the appropriate PIRQ bit before exiting. The format of the
PIRQO is shown in Figure 3-22.

REQUEST l.EVELS——I

)

1§

cm—

|¥

PIR7|PIR6|PIR5|PIR4|PIR3|PIR2|PIRT}]

PRIORITY ENCODED VALUE OF BITS 9-15

<15:9>

read-only.

The other bits are read as

3.2.12

CPU Error Register

is read/write.

Bits <7:5> and <3:1> are

or written.

read

can

MR-9013

PIRQ Register

Figure 3-22

Bits

zeros.

The CPU Error Register (Figure 3-23) identifies the source of a
trap through location 4. Refer to the DCJ1l Microprocessor User's
Guide (EK-DCJ11-UG) for details on handling the <traps. This

ADDRESS: 17777766

15
0o

14
0

13
0

ILL
HLT

YEL
STA

NXM
ADD

I/0

RED

ERR

TOT

STA
MR-17207

Figure 3-23

CPU Error Register

Bits

Name

Description

15:8

ILL HLT

Not used

(read as

zeros)

Illegal

halt

Set when execution of a

HALT
instruction is attempted in user or
supervisor
mode,
or attempted in kernel
mode
when
M14
and
M15
are
Jjumpered
together.

ADD ERR

Address error - Set when a word access 1is
made
to
an odd byte address, or when an
register

NXM

Non-existent

I/0 TOT

I1/0

YEL STA

~ RED STA

made

to a non-existent

Yellow

1:0

stack

zone

Red

stack

trap

occurs.

Unused

3.2.13

Processor Status Word

memory - Set when reference

non-existent memory

address.

timeout - Set when reference is

bus

yellow

internal

attempted.

to a

is made

a J-11

from

fetch

instruction

I/0 page

violation

Set

address.

stack

overflow occurs.

trap

(read as

when

Set when a red stack

zeros)

(PSW)

The
Processor
Status Word (Figure 3-24) contains the current and
previous
operational modes, the J-11 general-purpose register set
the current priority level, condition codes, and the
used,
being

trace

bits

trap

<10:9>

bit.

All bits in this register are read/write except

(which are read-only but are not used).

ADDRESS: 17777776
i1

[ow

m [ms]ofolo]

Tem
|

[v[w]z[v]c]
MR-17208

Figure 3-24

Processor Status Word

(PSW)

Bits

Name

15:14

13:12

Description

Current

Mode
Kernel
Supervisor
Illegal

User

mode
Previous
mode
operational
are

the

current

used

the previous
Displays
same codes
the
wusing
,

for CM.

1 (RO’
set
set,
When
set
Register
R5') of the J-11 general-purpose
through
When cleared, set 0
used.
1is
registers
(RO

1is used.

through R5)

Not used

(read as

Determines

Priority

zeros)

interrupt priority

the

hardware

level.

Priority Level
W OO

PRI
111
110
101

100
011

010
001

PRI

Displays

mode:

CM
00
01
10

that
11

mode

- operational

000

- When set, causes a trap to
end of the current
the
at

trap
Trace
14
location

When

instruction.

trace

trap

cleared,

disables the

function.

N bit - Set if the result of the previous
instruction was

negative,

7 bit - Set if the result of the previous
instruction was

bit

resulted

- Set

zero.

if the previous instruction

in an arithmetic overflow.

- set if the previous instruction
bit
C
most
1its
of
carry
a
in
resulted
significant

bit.

3.2.14
Console Asynchronous Serial I/0
The console asynchronous serial line interface (based on the DLART
chip)
provides
program
or
Jjumper selectable baud rates (300 to
38.4K
baud),
real-time clock outputs (800 Hz, 60 Hz, and 50 Hz),
eight data bits, no parity, one stop bit, and break detection that

causes

the J-11

to enter ODT if the BREAK enable jumper

(M12-M13)

is
1installed.
A
Dbreak detect bit appears in the RBUF of a UART
during
the
time
a
BREAK
condition
exists
on the line.
Also
featured
are
RS422/RS423/RS232-C
EIA
interfaces,
a
10-pin
interface
connector,
and
an optional EIA to 20ma conversion kit
utilizing
the
DLV11-KA.
There is no reader run pulse generation
or

110

baud

rate

input.

3.2.15
Synchronous/Asynchronous Serial I/O
A
two-channel
multiprotocol
serial
communications
controller
(uPD7201)
supports
asynchronous, character-oriented synchronous,
and
bit-oriented
synchronous
protocols,
programmable character
size,
parity,
CRC generation and checking, BREAK detect, framing
error
detection,
automatic
detection
and
generation
of
SYNC
characters,
auto hunt, and external or internal programmable baud
rates
from
110 to 76.8K baud.
The primary channel (SLU2 channel
A) is provided with type SR (send-receive) RS449(CCITT) electrical
interface
and
modem
control lines.
The secondary channel (SLU2
channel
B)
1is
a synchronous/asynchronous secondary channel with
type
DT (data and timing only) RS449(CCITT) electrical interface.
In
addition,
this
second
<channel
can be operated in a 16 node
party-line

3.2.16

configuration.

Parallel

Twenty

1I/0

programmable

parallel

I/O0

1lines

are

provided,

with

programmable
direction
control
of
IEEE-488 electrical standard
compliant input buffers,
and either passive pull-up drivers or TTL

compatible

drivers.

There are three parallel

I/O ports:

two 8-bit

data
ports
and
one
4-bit
control port. Features include three
interrupt
requests
and
handshake
control
for
either
polled,
interrupt
conditional
control,
three-wire,
or
bidirectional
operation.
Three
programmable
16-bit
timers
are provided with
either
internal
<control
and
interrupt,
or
external
buffered
control

Pump

KHz.

The

charge pump

zener diode

6l4.4

-12V Charge

serial
1I/0
drivers
and
receivers require a negative 12V
This
1is
provided
by an on board charge pump operating at

3¢2.17

Local
bias.

lines.

regulated.

QO-BUS

3.3

INTERFACE

The 0-Bus interface can be considered from two perspectives: from
the perspective of the Q-Bus and from the perspective of the local
KXJ11-CA bus. There are two distinct portions of the KXJ11-CA that
The I/0 page
in any way the user sees fit.
may be partitioned
file's address is determined by the base address
TPR
addressable
while the addresses 1in shared
switch setting,
ID
CPU
the
and
From the Q-Bus, the KXJ11-CA
be defined by the user.
can
memory
a 16 word I/O page addressable register file that may
1like
looks
and command
status
transmit
a
into
partitioned
1logically
be
The file
section.
status
and
command
receive
a
and
section,
The Q-Bus master can read
a control communication path.
provides
from/to any of three defined command registers and has
and write
status
only
read
associated
three
of
from any
status
read
TPR4,
file words may be written or read.
other
All
registers.
the
flag
either
can
Q-Bus,
the
from
written
when
TPR12,
and
TPR8,
five
level
unique
with
J-11
the
interrupt
or
KXJCSRD
through
J-11
addition, when the first file word is written, a
In
interrupts.
This is a priority
restart trap is generated.
J-11
nonmaskable
command

channel.,

The 0O-Bus sends messages or asks for status through the TPR file.,
either by directly reading or writing the
respond
can
The J-11
by invoking the data path controller (DTC) to move data
or
file,

1interface and signal the arbiter when completed.
bus
the
across
arbiter at will by
OQ-Bus
the
signal
can
processor
1local
The
interrupt register (QIR), to generate a
Q-Bus
its
into
writing
level 4 interrupt to the Q-Bus arbiter, or by writing into the two

port register for polled operations.

DMA controller can address any portion of the QO-Bus
KXJ11-CA
The
Shared memory is visible from the local bus
22-bit address space.
a contigious physical memory with an address range of 00000000
as

The addressing
All 512 KB can be shared.
KB).
(512
01777777
and stored in two
host
the
by
determined
is
Q-Bus
the
from
These registers contain
registers, KXJCSRF and KXJCSRH.
internal

starting address (KXJCSRF), a value for the number of blocks,
the
Shared memory is enabled and
address (KXJCSRH).
ending
the
and
Q-Bus memory may be
locally mapped
The
by KXJCSRJ.
disabled
contigious increments in any non I/O address
KB
8
in
allocated
The range selected must also be on 8 KB boundaries, which
range.
user a total of sixty-four 8 KB pages. The shared memory
a
allow
area

located at

the

3.4

KXJ11-CA

firmware

is discussed

top of

local RAM.

INTERRUPTS

There are three general categories of interrupts which involve the
from the Q-Bus to the KXJ1l1-CA, interrupts
interrupts
KXJ11-CA:
KXJ11-CA to the 0-Bus, and local interrupts by on-board
the
from
This section describes the KXJ11-CA's role
1I/0 devices.
KXJ11-CA
Special interrupt handling by the
interrupt.
of
type
each
in
in Section 3.5.

Interrupts From The Q-Bus To The KXJ1l1-CA
3.4.1
device can interrupt the KXJ11-CA by writing TPR4, TRPS8,
O-Bus
A
and the TPR interrupts are enabled (as
TPRs
the
If
TPR12.
or
by bits 6:3 of KXJCSRD), a write to any of these three
determined
the Q-Bus causes a level 5 interrupt. The vectors
from
registers
interrupts are located at logical addresses
the
with
associated
The sequence of
120, 124, and 134 respectively in kernel I space.
events during a Q-Bus interrupt is illustrated in Table 3-2.

Interrupts from the Q-Bus to the KXJ1l1l-CA

Table 3-2

0-Bus Device
or Arbiter

KXJ11-CA

Writes TPR4, TPRS,
or TPR12

interrupts are enabled,
TPR
If TPRs and
with the
interrupt
5
level
a
handles

3.4.2

The

(DC7037B)

vector.

TPR
TPR4

Vector
120

TPRS
TPR12

124
134

Interrupts From The KXJ11-CA To The Q-Bus

KXJ11-CA

arbiter)

following

can

through

called

of the QIR is

interrupt

devices on the Q-Bus (including the
1in

the

on-board

GAP

gate array

the QIR or Q-Bus Interrupt Register. The format

described

in Section 3.2.9.

order for the KXJ11-CA to interrupt the Q-Bus through the QIR,
In
If this bit is
must first be set.
(BQIREN)
of KXJCSRD
12
bit
posted.
be
cannot
cleared, interrupts from the KXJ11-CA

KXJCSRD bit 12 is set, a write to the QIR sets KXJCSRD bit 14
If
(OIR REQ), which causes the Q-Bus signal BIRQ4 to be asserted and
At some later time, a
generates a level 4 interrupt on the Q-Bus.
0-Bus device (or arbiter) asserts the signal BIAKI to acknowledge
for the
the QIR
of
contents
the
reads
and
interrupt,
the
appropriate

vector.

interrupt) clears
(acknowledgement of
assertion of BIAKI
The
14. If KXJCSRD bit 13 is set, the assertion of BIAKI
KXJCSRD bit
a level 5 local interrupt request with a vector of 130. The
posts
that there is a vector at 130 that points to a
user must ensure
that will handle the interrupt. The routine handles the
routine
Table 3-3 summarizes the
interrupt and the operation is complete.
sequence

events.

Table 3-3

Interrupts from the KXJ11-CA to the Q-Bus

O-Bus Device
or Arbiter

KXJ11-CA
Writes
is

Sets

with vector when KXJCSRD<12>

KXJCSRD<K14>

Asserts

QIR

set

BIRQO4

Reads QIR

BIAKI

Handles
vector

a local
of

level

interrupt with a

130

Local Interrupts From On-Board Devices
3.4.3
The
KXJ11-CA
on-board
devices that can post local interrupts to
the
on-board J-11 include the data transfer controller (DTC), the
parallel
1I/0
port
(PIO),. the
console
serial line (SLUl), the
multiprotocol
serial
controller
(SLU2), the SLU2 counter/timer,
the real-time clock (RTC), TPR4, TPR8, TPR12, and the QIR.
Interrupts

from local devices are all handled

in the same general

way.

The

local device posts an

The

J-11

through the J-11's

reads

performs

handles

the

vector

interrupt

IRQ lines,

that

1nterrupt

points

to the on-board J-11

acknowledge cycle and
an

interrupt service

routine,

The

routine

Operation

interrupt,

and

resumes.

The
DTC
and
the PIO share a common interrupt request line.
The
DTC
has the higher priority of the two devices (these two devices
are daisy-chained), and allows the PIO to acknowledge an interrupt
only if there are no DTC interrupts pending.
Table
3-4
1is
a summary of all the interrupts handled locally by
the
KXJ11-CA,
their
relative
priorities,
and
the
vectors
associated
with
each
interrupt.
Within
a priority level, the
interrupt with highest priority is listed first.

The
vectors
for DTC interrupts and PIO interrupts shown in Table
3-4 are the defaults set by the native firmware. These vectors are
programmable.

Table 3-4

Summary of KXJ11-CA Local

Interrupts

Priority

Vector(s)

Interrupt Type

Programmable

240

PIRQ

100

Real-Time Clock

5
5

120
124

Interrupt
Interrupt

from Q-Bus
from Q-Bus

Interrupt

from Q-Bus

104

SLU2 Counter/Timer 2

Interrupt to Q-Bus

130

134

the user.

changed by

*Default values.

May be

3.5

INTERRUPT HANDLING

SPECIAL

(via QIR)

DTC Interrupt
PIO/PIO Timer Interrupt
Console (SLUl) Receiver
Console (SLUl) Transmitter
MPSC (SLU2) Communication

224 ,230*%
200,204,210%
60
64
70

4
4
4
4
4

(watchdog timer

The
KXJ11-CA
native firmware is designed to handle four types of
special
1interrupts.
A
special interrupt occurs when the enable
bit

(KXJCSRJ

bit

set

and

A command

issued

(TPRO

is written),

A power fail occurs

(BPOK

is deasserted),

occurs
halt
QO-Bus
A
corresponding enable bit

1initialization is performed (BINIT is asserted)
O-Bus
A
enable bit (KXJCSRD bit 10) is set.
corresponding
the
and

asserted)
1is
(BHALT
(KXJCSRD bit 8) is set,

and
or

the

During an special interrupt, the KXJ11-CA switches to kernel mode,
pushes the current PC and PS on the kernel stack, forces the PC to

PS to 340, clears bit 6 of KXJCSRJ (NMI EN),
the
forces
173004,
Typically, the KXJ1l1-CA firmware
code.
execute
to
begins
and
1If the user has his own code for
interrupt.
special
the
handles

should make sure that the entry
he
handling,
interrupt
special
The
logical location 173004.
kernel
the
at
is
code
this
point for
follows:
as
interrupt
special
a
handles
firmware

TPR1 bit 4 selects either user code or firmware to handle
If TPR1 bit 4 = 1, control is
interrupt.
special
the
locations 24 and 26, and user
through
code
user
to
passed
special interrupt. If TPRl bit 4 = 0,
the
handles
code
control is retained by the KXJ11-CA firmware that handles
interrupt. The steps that follow assume the
special
the
KXJ11-CA firmware handles the special

interrupt.

The

cause

the special

interrupt

is determined by the

contents

special

If
the
special
interrupt is caused by the assertion of
BHALT or BINIT and the appropriate enable bit 1s set, the
firmware
traps
through
locations
24 and 26 and allows
user code to handle the interrupt.

If
the special interrupt is caused by issuing a command,
the
firmware determines which command has been issued by
looking
at
TPRO
and
then
executes
the command.
The
arbiter may need to load command parameters into TPR2 and

the

KXJCSRD.

interrupt

is caused by a power failure,

the firmware traps through locations
user code to handle the interrupt.

TPR3

before

issues

and

allows

the command.

After the special interrupt is handled, the firmware sets
the
enable
bit
(bit
6
of
KXJCSRJ) to enable another
special
interrupt.
If the user's code 1is processing the
special
interrupt,
it is important that the proper exit
sequence
be
used
upon
completion.
First,
the
event
indicator
(BHALT,
BINIT,
or
PWRFL) must be cleared in
KXJCSRD.
Then,
the
enable
bit must be set in KXJCSRJ.
Finally,

3.6

an RTI

instruction must be

KXJ11-CA RESETS

There

are

two

reinitialized.

ways

executing

software

By
is

executed.

which

the

RESET

instruction.

reset.

KXJ11-CA

can

This

reset or

1is called a

the assertion of the local power-up signal PUP.

called

hardware

reset.

This

The sections that follow explain the causes and effects of the two
types

3.6.1

When
a
various
Table

resets.

Software

Reset

RESET
instruction
1is executed by the on-board J-11, the
components
of the KXJ11-CA are affected as summarized in

3-5.

Table

3-5

KXJ11-CA Software Reset

Component

" Effect

SLUl1

input INIT is asserted, which
DLART
The
1interrupt enables and clears bits
clears
0 of the SLU's XCSR. Refer to the
and
2
details of DLART
for
Sheet
Data
DLART

(DLART)

behavior when INIT

asserted.

inputs ZDS and ZAS are asserted
PIO
The
PIO. Refer to the PIO
the
resets
which
of* PIO
details
for
Manual
Technical
behavior when DS and AS are asserted.

PIO

DS and AS are asserted,
1inputs
The DTC
DTC. Refer to the DTC
the
resets
which
DTC
of
details
for
Manual
Technical
behavior when DS and AS are asserted.

DTC

and the
disabled
1is
management
Memory
executes a RESET instruction. Refer
J-11
the DCJ1ll User's Guide for details of
to
J-11 behavior when RESET 1s executed.
SLU2

(MPSC)

Unaffected.

SLU2

Timers

Unaffected.

RTC

Interrupts disabled (KXJCSRAK6> cleared)

KXJCSRA

Unaffected.

KXJCSRB

KXJCSRC
KXJCSRD

Cleared.

KXJCSRE

Unaffected.

KXJCSRF

KXJCSRH

This disables shared memory and
Cleared.
interrupts. It has other effects
special
as described in Section 3.2.8.8.

KXJCSRJ

Boot/Self-test
Switch

Switch

Pending

on software

resets.

Unaffectéd.

LEDs

No effect

Interrupts

No effect
Cleared.

software

resets.

Hardware

3.6.2

Reset

Hardware
resets are caused by the assertion of the local power-up
signal
PUP.
A
hardware
reset occurs when any of the following
conditions

occur.

the

+5V

the KXJ11-CA is not

in standalone mode

the

BDCOK.

KXJ11-CA is

in standalone mode

power.

O0-Bus

hardware

are affected as

signal

Component

(DLART)

reset,

summarized

Table

SLU1

(as determined

by the setting of the ID switch), a hardware reset occurs
when
the
on-board wake-up circuit detects the assertion
caused by writing a 1

During

(as determined by

the
setting
of
the ID switch), a hardware reset occurs
when
an on-board wake-up circuit detects the presence of

3-6

to TPRO bit

A hardware reset is also
14

from the Q-Bus.

the various components of the KXJ11-CA

in Table

3-6.

KXJ11-CA Hardware

Reset

Effect

The DLART input TEST is asserted, which resets

the
DLART.
Refer to the DLART Data Sheet for
details
of
DLART
behavior
when
TEST
1is
asserted.

PIO

The PIO inputs ZDS and ZAS are asserted, which

DTC

J-11

resets
Manual

the
for

and

are

ZAS

PIO.
Refer
to the PIO Technical
details
of PIO behavior when ZDS

asserted.

The

resets
Manual

DTC inputs ZDS and ZAS are asserted which
the
for

and

ZAS

are

The

J-11

DTC.
Refer
to the DTC Technical
details
of DTC behavior when ZDS

asserted.

input INIT is asserted.

Refer to the

DCJ11
Microprocessor
User's
Guide
J-11 behavior
of
details
for
(EK-DCJ11-UG)
when
INIT
1is
asserted.
Jumper
M17-M1l6
determines
if
control
1is
passed
to
the
firmware
(location
173000)
or
to ODT after
power-up

SLU2

(MPSC)

complete.

The MPSC input RESET is asserted.

MPSC

Data

when

RESET

Sheet

Refer to the

for details of MPSC behavior

asserted.

themselves upon power-up.

SLU2 Timers

Initialize

RTC

Interrupts disabled (KXJCSRAK6> cleared)

KXJ11-CA Hardware Reset (Cont)

Table 3-6
Component

Effect

KXJCSRA
KXJCSRB

Initialized to power-up values. See specific
register descriptions for details. All

writeable bits are cleared.

KXJCSRC

KXJCSRD

KXJCSRE
KXJCSRJ

KXJCSRF

Initialized to a value of 177600 upon
and are unaffected by a hard

power-up,
reset

from the

Q-Bus.

Initialized to a value of 177777 upon

KXJCSRH

and are unaffected by a hard
power-up,
reset

from the

firmware

Q-Bus.

1s executed upon power-up,

Boot/Self-test

LEDs

All

ID Switch

Value is loaded into KXJCSRC, thus affecting

this switch specifies the function performed.

Switch

the

Q0-Bus

address.

Cleared.

Pending

Interrupts

3.7

MEMORY MANAGEMENT ARCHITECTURE
NOTE

for readers
written
was
section
This
PDP-11 memory management
with
familiar
For further details on memory
concepts.
Chapter 4 of the
to
refer
management,

DCJ11

Microprocessor

.
(EK-DCJ11-UG-PRE)

User's

Guide

the full PDP-11 memory management and
with extensions for extended direct
The KXJ11-CA memory management registers include Page
addressing.
Page Descriptor Registers (PDRs), and
(PARs),
Address Registers
MMRO
(MMRO - MMR3).
Memory Management Registers 0 through 3

The KXJ11-CA implements
architecture
protection

contained in the on-board J-11 microprocessor.
are
through MMR3
These registers
The PARs and PDRs are located in physical memory.
are described

in the sections that follow.

Page Address Registers (PARs)
3.7.1
is a total of 48 PARs, with eight PAR's alloted for each of
There
foll owing:
kernel I space, supervisor I space, user 1 space,
the
Each PAR
supervisor D space, and user D space.
kernel
D
space,
contains

address

page

a page

address field (PAF) that specifies the
as a block number in physical memory.

starting

NOTE

Kernel
I
space
and
D
space
PAR7 1is
mapped
to the I/0O page by the firmware.
This mapping must not be altered.
The

format

a PAR

shown

Figure

3-25.

MR-17127

Figure

Page Address Registér (PAR)

3-25

Page Descriptor Registers (PDRs)
3.7.2
is a total of 48 PDRs, with eight PAR's alloted for each of
There
kernel I space, supervisor I space, user I space,
foll owing:
the
kernel
“supervisor
D space, and user D space. Each PDR
D
space,
page length, and
direction,
information
on
expansion
contains
access

control.

The

format

......
......
oooooo

]

{

a PDR

..........

........

..........

-------------

'''''''''''
OOC

.........

shown

in Figure

3-26.

O|PW]

O | ED

AFF

| wmpaziat

Figure

Bits

Name

15
14:8

3-26

Descriptor

(PDR)

Description

Not
PLF

Page

used

(read/write)

Page
length
field - Specifies the block
number,
which
defines the page boundary
(see
bit
3).
The
block
number of the
virtual
address
1is compared with PLF to
detect
1length
errors.
An
e€error OCCUrS
when
expanding
upwards
1f
the
block
number
1is
greater
than
PLF,
and when
expanding
downwards
if the block number
is less than PLF.

Description

Name

Bits

Not used (read as zero)

When set, this page has

it was loaded 1into
since
been modified
This bit is cleared when the PAR
memory.
is written.

this page

or PDR of

Not used (read as zeros)

5:4

written

Page

Expansion direction - When set, this page

from block numb€r 127
downwards
expands
Dblocks with lower addresses.
include
to
this page expands upwards
cleared,
When
to include blocks
0
number
from block
with higher addresses.

2:1

for this page.

access code

ACF

Access

Read/write

Contains

the

Non-resident - abort all accesses
Read only - abort on write attempt
Not used - abort all accesses

00
01
10

field

control

Access

ACF

access

Not used (read as zero)

Memory Management Register 0 (MMRO)
3.7.3
information for the memory
MMRO contains status and control
read-only. Figure 3-27
1is
register
This
unit.
management
illustrates

the format of MMRO.

ADDRESS: 17777572

13
l

o|lo|l

O0]O0O]
“

08
O]

07
O

|PAGMOD
1

03
J

PAG NUM
L1

]

ABO NRE| ABO ACV

ABO PLE

I/D SPC

ENB REL
MR-17130

Figure 3-27

Memory Management Register

0 (MMRO)

Bits

Name

ABO

Description
NRE

Abort
non-resident
- Set when an access
attempt
is made to a page with an access
control
field key of 0 or 2. Also set by
attempting
to use memory relocation with
a current processor mode (PS<15:14>) of 2
(illegal).
ABO
NRE
1is set when PAG MOD
equals

ABO

PLE

Abort
page
length
- Set when an access
attempt
is
made
to a page with a block
number outside the range specified by the

page's PDR. Also set by attempting to use
memory
relocation
with
a
current
processor
mode
(PS<15:14>)
of
2
(illegal).

ABO ACV

Abort
access
violation
Set
when
attempting
to
write
a
read-only
page
(that is, the access control field equals
l.)

Not used
PAG

MOD

(read as

mode
Page
associated

zeros)

mode
CPU
the
Indicates
with
the
page
causing
an

abort.

PAG MOD
00
01
10

Mode
Kernel
Supervisor
Illegal Mode

User

If
is

I/D SPC

an illegal mode

Page
address space - When set, a D space
mapping
operation
was attempted when an
abort
occurred. When cleared, an I space
mapping
operation
was attempted when an
abort

PAG

NUM

is specified, ABO NRE

set,

occurred.

Page number reference
a

Contains the page number of
causing a memory management

abort.
ENB

REL

memory
set,
When
relocation
Enable
address
and
enabled
is
management
When cleared, memory
occurs.
relocation
is disabled and addresses are
management

relocated nor protected.
neither
by RESET instruction.

Cleared

1 (MMR1)
Memory Management Register
3.7.4
of any
autodecrementing
or
autoincrementing
the
records
MMR1
(GPR) during an instruction, including
register
purpose
general
(PC). This register is
program counter
the
through
references
an instruction. Whenever a GPR is
beginning of
the
at
cleared
autoincremented or autodecremented, the register number and amount
(in 2's complement notation) by which the register was modified is
1low byte of MMR1 is written first. The
The
into MMR1l.
written
format of MMR1

shown

in Figure

1110

—

[l [

| ]

l L. 1 _
|

3-28.

AMOUNT CHANGED

(2'S COMPLEMENT)

NUMBER

(2'S COMPLEMENT)

NUMBER
MR 8924

Figure 3-28

3.7.5

Memory Management Register

(MMR1)

(MMR2)

program counter (VPC) and is
virtual
the
<called
also
1is
MMR2
at the beginning of each
address
wvirtual
16-bit
a
with
loaded
register

This

instruction fetch.

is read-only.

3 (MMR3)
Memory Management Register
3.7.6
and disables data space mapping for
enables
3-29)
(Figure
MMR3
It also controls I/0 mapping,
kernel, user, and supervisor modes.
18-bit/22-bit mapping, and whether requests for Call to Supervisor
Mode
instruction are enabled.
This register is read/write and 1is
cleared

during

a hardware

reset.

ADDRESS: 17772516

ojlojojJojofloj|joOo}JO}|O0O]|O

]

r:/tODEI
ENB CSM

ENB 228
MR-17132

Figure

3-29

Memory Management Register

(MMR3)

Bits

Description

Name

15:6

Not used (read as zeros)

Not used (read/write)

22-bit mapping - When this bit 1is

Enable

ENB 22B

set

memory

and

management

1is

enabled

1is set), 22-bit
(i.e., bit 0 of MMRO
bit is cleared
this
When
used.
is
mapping
is enabled,
ent
managem
memory
and when

1is used. This bit has no

mapping

18-bit

memory = management

when

effect

disabled.

Mode

MODE

in kernel I

bits

Mode - When

space.

enable and disable kernel,

supervisor, and user D space as shown:

Bit
MODE<2>
MODE<2>
MODE<1>
MODE<1>
MODE<KO>

=
=
=
=

0
1
0
1

= 0
MODE<0> = 1

3.8

Supervisor

a Call to Supervisor
set,
1is
this bit
be executed. When
may
ction
instru
(CSM)
execution of a
the
,
cleared
1is
this bit
trap through
a
causes
tion
CSM instruc
location 10

2:0

Call

Enable

ENB CSM

Meaning
Disable kernel D space
Enable kernel D space
Disable supervisor D space
Enable supervisor D space
Disable user D space
Enable user D space

SHARED MEMORY

The KXJ11-CA contains 512 KB of on-board RAM. The RAM can be
configured as "shared memory" that can be accessed by devices on
the O-Bus as well as the on-board J-11 microprocessor. Shared
memory could be wused, for example, in an application where the
arbiter needs to access RAM that is read or written locally.
Shared memory can be configured under software control by loading
KXJ11-CA Control/Status Registers KXJCSRF and KXJCSRH (Sections
3.2.8.6 and 3.2.8.7), and enabled by setting KXJCSRJ<2>. KXJCSRF
and KXJCSRH contain values that specify the starting address,
ending

address,

and number of blocks for the shared memory area.

This section explains how to derive the values you need to load
into KXJCSRF and KXJCSRH once you have determined which QO-Bus
addresses are to be associated with shared memory. The section
that follows explains the mechanics of how the registers are
loaded by the arbiter or by the on-board J-1ll.

When configuring shared memory, make sure that there are no
That 1is, O-Bus addresses must be
overlapping Q-Bus addresses.

[

unique.

3.8.1

Shared Memory Organization

Shared
memory
consists
of one or more 8 KB blocks of RAM. Since
there
1is
512
KB
of
RAM on the KXJ11-CA, the maximum number of
shared memory
blocks
is
64.
Each
block must start on an 8 KB
boundary.
On
the KXJ11-CA, the last block is the highest 8 KB of
RAM
(1777777
1760000),
the
next
to
1last block is the next

highest
8 KB (1757777 - 1740000), and so on. All blocks of shared
memory
are
contiguous. The shared memory space is located at the
top
of
local
RAM.
The 1local
starting
address
1is (2000000 N*20000) octal, where N is the number of blocks.

The algorithms for determining
are as follows.
|

CSRF:

the contents

of KXJCSRF

(0-Bus starting address/100)

and KXJCSRH
o

octal

CSRH<15:7>:
[(Ending address) AND 17720000] /20000
CSRH<5:0>: [Negate[(Q-Bus starting address)/20000 +
(number of

The

sections

determined

3.8.2

Suppose
memory.

that

and used.

blocks)]]

fdllow

Defining One Block of

AND 77

illustrate

how

octal

these

values

are

Shared Memory

you
want to define one 8 KB block of addresses as shared
The following example illustrates how this would be done.

In
this
example,
you
want
to
define one 8 KB block of shared
mémory starting
at
Q-Bus
address
100000. In this case (Figure
3-30),
addresses 100000 through 117777 on the Q-Bus correspond to
KXJ11-CA
shared
memory
addresses 1760000 through 1777777.
What
values

The

do we

value

need

for. the

load

into KXJCSRF

and KXJSCRH?

"starting address"

that we need to load

into

KXJCSRF
1is obtained by shifting the starting Q-Bus address
to the
right six bits. Figure 3-31 shows the relationship between KXJCSRF
and
the
22-bit Q-Bus
address. Plugging in our Q-Bus address of
100000
(octal),
we
see
that 1000 (octal) should be loaded into
KXJCSRF .
Bits 6:0 of KXJCSRF are not used and read as zeros.

The
value
for
the
"ending
address"
that we need to load into
KXJCSRH
bits
15:7
(END
ADD)
1is
obtained
by taking the first
(0-Bus)
address in the last block and shifting it to the right 13
bits.
In
this
case, we are working with only one block, so the
first
block
1is
the
only
block. The first address in the block
shifted to the right 13 bits yields 000000100 for bits 15:7.

KXJ11-AA

Q-BUS

17777777

11777777

1760000

117777
8K

100000

‘

MR-17256

Defining One Block

Figure 3-30

STARTING Q-BUS

ADDRESS

Shared Memory

20119

17 | 16

6:0

15 | 14

MR-17255

Figure 3-31

Control Register Bits/Q-Bus
Address Relationship

The value for the "number of blocks" that we need to load into
KXJCSRH bits 5:0 is obtained by extracting bits 18:13 of the Q-Bus
adding the number of blocks, and two's
address,
starting
complementing (negating)

the result.

O-Bus address 100000 bits 18:13
Add number of blocks

000100
1
+
000101

Negate

111011

The value 111011 is loaded into bits 5:0 of KXJCSRH.
interprets this value as one Dblock.

The KXJ11-CA

3.8.3
Suppose

Defining Two Blocks of Shared Memory
you
want
to define two blocks of shared memory.

Assume

that
the
range
of
Q-Bus addresses assigned to shared memory in
this
case
1is
100000
through
137777.
On
the
KXJ11-CA,
the
corresponding
two
blocks
are
contiguous
in
RAM and reside at
addresses
1740000
through
1777776. The relationship between the
O0-Bus
addresses
and
the
KXJ11-CA
addresses
1is illustrated 1in
Figure

Find

3-32.

the

correct

values

load

into KXJCSRF

and KXJCSRH.

The
value
for
the
"starting address" that we need to load into
KXJCSRF
1is obtained by shifting the starting Q-Bus address to the
right six bits. This yields 1000 (octal) for KXJCSRF.
Bits 6:0 of
KXJCSRF

are

not

used

and

read

zeros.

The
value
for
the
"ending
address"
that we need to load into
KXJCSRH
bits
15:7
(END
ADD)
1is
obtained
by taking the first
(0-Bus)
address in the last block and shifting it to the right 13
bits. In this case, the first address of the last block 1is 120000.
Shifting
the
address
to
the right 13 bits yields 000000101 for
bits

15:7.

"number of blocks" that we need to load into
the
for
value
The
KXJCSRH bits 5:0 is obtained by extracting bits 18:13 of the Q-Bus
starting
address,
adding
the number of blocks, and negating the
result.

O-Bus address 100000 bits
Add number of blocks

18:13

0001060
+
10
000110

Negate

The value

interprets

111010

111010
this

loaded

value

17777777

into bits 5:0 of KXJCSRH.

two blocks.

KXJ11-AA

Q-BUS

1777777

137777

740000

8K
120000
177777

100000

MR-17257

Figure

3-32

Defining Two Blocks
of

3-50

Shared

Memory

The KXJ11-CA

3.8.4

Defining 64 Blocks of Shared Memory

Suppose you want to define all 64 blocks of RAM as shared memory.
Assume that the range of Q-Bus addresses assigned to shared memory
in this case 1is 1000000 through 2777777. On the KXJ11-CA, the
corresponding blocks are contiguous in RAM and reside at addresses
0 through 1777777. The relationship between the Q-Bus addresses
and the KXJ11-CA addresses is illustrated in Figure 3-33.
The correct values to load into KXJCSRF and KXJCSRH are
KXJCSRF = 10000

(octal)

Since the first (0-Bus) address of the last Dblock is 2760000,
KXJCSRH bits 15:7 = 001011111

KXJCSRH bits 5:0 are determined as follows.

O-Bus address 1000000 bits 18:13
Add number of blocks

160000
+ 1000000
1100000

100000

Negate
Carries are

ignored.

Q-BUS
177777771’

2777777

KXJ11-AA

512K

1000000

17777777

LT
MR-17258

Figure 3-33

Defining 64 Blocks
of

Shared

Memory

3.8.5
Enabling and Disabling Shared Memory
Shared
memory
can be enabled and disabled by either the on-board
J=-11
or by an arbiter command. When shared memory is enabled, the
relationship between Q-Bus addresses and KXJ11-CA RAM addresses 1s
defined
by
the
wvalues
in
KXJCSRF
and
KXJCSRH.
This section
describes how the on-board J-11 and arbiter can enable and disable
shared

memory.

Once KXJCSRH and KXJCSRF are set up, the on-board J-11 enables and
disables
shared
memory simply by writing bit 2 of KXJCSRJ.
When
this
bit
is
set,
shared
memory
1is
enabled.
When the bit 1is
cleared,
shared
memory
is
disabled.
The
shared
memory
configuration
values
might be known at startup time, or they can
be
passed from the arbiter to the KXJ11-CA through one of the TPR
user communication channels.

When
the arbiter wants to enable or disable shared memory through
the
firmware,
the
process is somewhat more involved.
To enable
shared memory, the following events occur.

The
arbiter
determines
receive a command.
This

that
occurs

TPRO<K15:0>

for

command"

The

arbiter

address
3.

This

sometimes

called

ready to
100, and

the

"waiting

the Q-Bus

starting

state.

writes

bits

into TPR2<8:0>

21:13

and writes

of
zeros

into TPR2<15:9>.

The
arbiter writes the number of blocks of shared memory
minus
one
1into
TPR3<5:0>.
For
example,
TPR3<5:0> =
000000 for one block of shared memory, TPR3<5:0> = 000001

for

two blocks

writes

the
KXJ11-CA is
when TPR1<2:0> =

The

zeros

arbiter

into

sets

shared memory,

and so on.

The

arbiter

TPR<15:6>.

TPRO

bit

Only

bit

should be

set.

If the arbiter were to set more than one bit at a time in
TPRO,
an
error
would
result (and would be recorded in
TPR1).
Setting
bit
6
causes
the KXJ1l1-CA firmware to
configure and enable shared memory.
The data in TPR2 and
TPR3
are
translated
into values, which are loaded into
KXJCSRF and KXJCSRH, and bit 2 of KXJCSRJ is set.
5.

After

shared

memory

KXJ11-CA clears TPRO
the KXJ11-CA back

configured

the

"waiting

and sets TPR1<2:0>

into

and

enabled,

100.

for command"

NOTE

A
local reset or a Q-Bus ODT GO command
will
disable
shared
memory because it
clears
KXJCSRJ
bit
2. The contents of
KXJCSRF and KXJCSRH are unaffected.

the

This puts
state.

To disable shared memory, the following events occur.

-CA is ready to
The arbiter determines that the KXJ11
KXJ11-CA is 1in
the
when
s
receive a command. This occur
the "waiting for command" state.

d be set.
The arbiter sets TPRO bit 8. Only bit 8bitshoul
at a time in
If the arbiter were to set more than one
TPRO, an error would result (and would be recorded in
.
TPR1)

The

KXJ11-CA

clears

bit 2 of KXJCSRJ, disabling shared

memory.

= 100. This
The KXJ11-CA clears TPRO and sets TPR1<2:0>
puts the KXJ11-CA Dback into the "waiting for command"”
state.

3.8.6

Shared Memory Considerations

d note the following
Wwhen designing an application, the user shoul
circumstances under which the wuse of shared memory could yield
unpredictable results.

y architectures that are
The KXJ11-CA is designed for use in memor
as the KDJ11l) must
non-cached. Arbiters with cache memory (such
sing shared memory. The
disable or bypass the cache when accesthe
er's cache when
kXJ11-CA has no mechanism for updating by arbit
the on-board J-1l1 or
cached shared memory locations are altered
DMA controller.

CHAPTER 4
DMA TRANSFER CONTROLLER

OVERVIEW

4.1

The DMA transfer controller (DTC) is designed around the AmZ8016
chip. For details on the operation of the AmZ8016 chip, refer to
the AmZ8016 DMA Transfer Controller Data Sheet included in this
documentation package. The information that follows summarizes and
describes the DTC functions implemented on the KXJ11-CA.

The

DTC

addresses.

can

perform

DMA transfers between any of the following

A local address to a local address

A local address to a QO-Bus address

A O-Bus address to a local address

A O0-Bus address to a Q-Bus address

From

To/From the PIO chip through DMA channel 1

channel A transmitter of the multiprotocol SLU

the

through DMA channel

the

channel

through DMA channel 0

receiver

the

multiprotocol SLU

Word and byte transfers are supported locally. Only word transfers
are supported across the Q-Bus. Note that in byte mode, the
addressing is the 1inverse of the PDP-11 addressing scheme. For
example, DTC address 1000 corresponds to PDP-11 address 1001, and
DTC address 1001 corresponds to PDP-11 address 1000.

The

operations

the

DTC

are

controlled by several internal

registers. The DTC can load these registers directly from memory,
thereby minimizing the amount of processor intervention necessary
to perform a DMA transaction. The area of memory where the

parameters for the DTC are stored is referred to as the chain
table. The local J-11 microprocessor need only load the address of
the

chain

table

1into

initiate a DMA transfer.

the

DTC

and. issue a "start" command to

DMA
transactions
may
be initiated locally by either the J-11 or
the
arbiter CPU. If the transfer is initiated by the arbiter, the
command
words
and
transfer parameters are placed in the command

registers
initiate
arbiter.

of the two-port RAM (TPR)
the DMA transaction using

file. The local J-11 will then
the parameters supplied by the

The

DTC
consists of two identical channels. DMA transfers may be
interleaved
between these two channels or interleaved between the

DTC

and

allows
The

the

DTC

J-11.

DMA

transfer

supports

three

also possible
to

run

types

Transfer-and-Search.

the

data

from

source

and

Transfer

and

transferred

between

transferred

meets

Mode

the

implies,

data

source

this

and

match

"hog

Search,

and
move

read

data

A mask

care"
bits.
features
of
operation,

destination

condition

that

operations

pattern

type

mode"

interruption.

Transfer,

Transfer

the

without

declare
"don't
combines
the

functions.
the

select

operations:

name

user
to
operation
a

completion

destination.

compare

wuntil

specified

data
the

the

The
the"
1is

data

Channel

The DTC is
processor

capable of performing multiple DMA transactions without
intervention.
This
can
be
accomplished in two ways:
base-to-current
reloading
or chaining. Base-to-current reloading
allows
the
DTC
to
reload
a
portion
of
its registers before
initiating
a
DMA
transfer.
The reload operation occurs between

internal

registers,

This

type

data

1is

allows

reloaded

some
from

Upon
completion
combination
of
processor,

reload.

4.2

or
a

also

1is

are

only

all

new

of the

chain

memory access

practical

transferred

of
a
the

perform

may

there

operation

continuously

Chaining
to

between

the

applicable

Dbase-to-current

delays.

same

registers

where

addresses.

the

DTC

table.

DMA
transfer,
the
following
options:

choose

in applications

take

DATA TRANSFER CONTROLLER

DTC
may
interrupt

reloading,

perform any
the
1local

perform

chain

action.

(DTC)

REGISTERS

NOTE

Refer to Section 4.3 for descriptions of
how
the
DTC
registers are used during
DMA operations.
The

Data

Transfer

Controller

global
registers
and
the
overall operation
global

registers;

boundaries.

one
as

for
words

Table

the

contains

two

types

registers:

channel registers. Global registers
and configuration of the DTC. There
command

and

the

control
two

are

master

4-1). Channel registers define the
There
are
two
1identical
sets

mode

state of a
of channel

each
channel.
These
registers
are always
and
are
aligned
on
even
(word)
address
4-2
1lists the DTC channel registers and their

addresses.

4-2

DTC Global Registers

Table 4-1

Address

Access

Description

17774454%*
17774470

W
RW

Command Register
Master Mode Register

* Iocation

17774454

can be read or written. When read,

information only.
cannot be read back.

status

that

Channel 0

it yields

information

DTC Channel Registers

Table 4-2
Channel

is written with command

Address

Access

Description

17774400
17774404
17774410
17774414

17774402
17774406
17774412
17774416

RWC
RWC
RWC
RWC

Current B Address Offset
Base B Address Offset
Current A Address Offset
Base A Address Offset

17774424
17774430
17774434

17774426
17774432
17774436

RWC
RWC
RWC

Base B Address Segment/Tag
Current A Address Segment/Tag
Base A Address Segment/Tag

17774444

17774446

RWC

Chain Address Segment/Tag

17774452

Address

17774420

17774440

17774450

17774454%*
17774460
17774464

17774474

17774422

17774442

17774456
17774462
17774466

17774472

17774476

17774500
17774504

17774502
17774506

17774520

17774522

17774530
17774534

17774532
17774536

* T,ocation

17774454

17774510
17774514

17774524

17774512
17774516

17774526

RWC

R
RWC
RWC

Current B Address Segment/Tag

Chain Address Offset

Interrupt Save Register

Status Register
Current Operation Count
Base Operation Count
Reserved

Reserved

X
X

RWC
RWC
RWC

RWC

RWC
X

Reserved
Reserved

Pattern Register
Mask Register
Channel Mode Low

Channel Mode High
Interrupt Vector
Reserved

can be read or written. When read, it yields

information only.
status
be read back.
cannot
that

It is written with command information

The KXJ11-CA DTC is
AmZ8016
Technical
are

not

the

The

based on the AmZ8016 chip (as described in the
Manual). Several registers of the AmZ8016 chip
implemented in the KXJ11-CA. These are shown as "reserved"

tables.

tables

specify

the

abbreviations

The

can

read

W =

The

can

written

The
register
operation.

X = The
by

4.2.1.1

Command

write-only
the

can

Global

These

code

for

each

The

key

follows.
by

the
by

loaded

on-board
the

J-11

on-board

the

DTC

processor.

J-11

processor.

part

chaining

implemented or is reserved for future use
Corp.

Registers
Register

DTC.

Figure

Dbe

Equipment

DTC

(see

4.2.1

used

access

the

that

the

commands

The

Command

on-board

include

J-11

uses

Reset,

Start

issue

Chain,

1is

the

commands

and

others

4-1).

ADDRESS: 17774454
10

""""""" B B R0t ARRRaas

Figure

Bits

Name

15:8

7:5

4-1

DTC

Command

CIE

used

Function

function

05
|

- Description
Not

field

specifies

performed

FF
000
001

Function
Reset
Interrupt

010

Software

011

Flip

100

Hardware

101

Start

Reserved

111

Reserved

indicates
enabled.

4-4

type

DTC.

|
Mask

Chain

interrupt

that

the

Request

Bit

110

Channel

enable

interrupt

When

requests

set,

are

"Bits

Name

Description

1US

Interrupt

indicates
serviced.

Interrupt

pending
interrupt

that

service
under
interrupt
an
that

- When set,
request 1s

When

1is

set,

being

indicates
currently

pending.

- When set, specifies a set or
cleared, specifies a
When
condition.
1
clear or 0 condition.

SET

Set/Clear

Channel 0/Channel 1 - When set, specifies

4-3

Table

channel
channel

summarizes

the

cleared,

When

functions

that

can

writing the various bits of the DTC Command Register.
Table 4-3

specifies

performed

DTC Command Summary

DTC Command Register Bits

210

543

Reset

O0OXX

1XX
1XX
O0XX
OXX

XXO
XX1
X10
Xl11

Clear Software Request Channel 0
Clear Software Request Channel 1
get Hardware Mask Channel 0
Set Hardware Mask Channel 1
Clear Hardware Mask Channel O

01
01
10
10
10

0XX
O0XX
0XX
O0XX
0XX

XO00
XO01
X10
Xl11
X00

Clear Hardware Mask Channel 1
Set CIE, IUS, IP Channel 0
Set CIE, IUS, ID Channel 1
Clear CIE, IUS, IP Channel O
Clear CIE, IUS, IP Channel 1

10
00
00
00
00

0XX
1EsS
1ES
1ES
1lES

X01
P10
Pll
POO
POl

Set Flip Bit .Channel 0
Set Flip Bit Channel 1
Clear Flip Bit Channel O
Clear Flip Bit Channel 1

01
01
01
01

1XX
1XX
1XX
1XX

Xl10
Xl11
XO00
XO01

Command

10
10
01
01

Start Chain Channel O
Start Chain Channel 1
Set Software Request Channel 0
Set Software Request Channel 1

XXX

Notes:

AS
P
X

Set to perform set/clear on CIE, clear for no effect on CIE.
Set to perform set/clear on IUS, clear for no effect on IUS.
Set to perform set/clear on IP, clear for no effect on IP.
"Don't care" bit. This bit is not decoded and may be 0 or 1.
4-5

Master Mode Register —-- The Master Mode Register controls
4.2.1.2
various aspects of overall DTC operation (see Figure 4-2).

ADDRESS: 17774470
15

o0|lo]J]O0O}jO0}]O

DC CTR

HOG

00
|

DMA ENB
MR-17128

Figure

Bits

(read as ones)

Not used

Description

Name

15:8

Master Mode

4-2

CTR

Must

zero

Must

one

Must

zero

chain control - When set,

Daisy

interrupt

requests

from the

inhibits

on-board PIO

PIO counter/timer 1is
counter/timer. The
daisy chain at a
interrupt
an
of
part
higher
Must
2

than

the

DTC.

one.

mode - When set, the DTC interleaves
Hog
1I/0O bus with the
local
the
of
control
DTC
the
cleared,
When
J-11.
on-board
a
until
bus
the
of
control
retains
exists (as indicated
condition
terminal
the contents of the Current Operation
by
Section
1in
described
Register
Count
4.,2.2.6). This is also called "hog mode".

HOG

DMA

level

ENB

zero

Must

DMA

enable - When set,

allows

the DTC to

1local I/O bus.
the
of
control
request
chaining or DMA
prevents
cleared,
When
operations.

4.2.2

DTC Channel Registers

Current Address Registers A and B -- Each channel has two
current Address Registers; one that specifies the current source
t
address of a DTC transfer and one that specifies the curren
er
Regist
Mode
l
Channe
the
in
bit"
"flip
The
destination address.
the
(see Section 4.2.2.8) specifies which registers (A or B) are
t
Curren
te
comple
A
tion.
destina
the
are
ers
source and which regist
an
and
t/tag
segmen
a
words,
two
of
ts
Address Register consis
4.2.2.1

of fset. The segment/tag specifies.

the

destination) address resides on the

(or

source

O-Bus

If the source (or destination) address resides in the I/0
page

(or destination)

source

the

<21:16>

bits

Address

source (or destination) address should Dbe
the
1f
or held constant as the
decremented,
incremented,

address

transfer proceeds

The segment/tag has the following format (Figure 4-3).
ADDRESS: 17774420, 17774422,17774430, 17774432
15

11
I

ADDR"
|
|
1

010

A{ZF
1

/L
/0

MR-17129

current A or B Address Segment/Tag

Figure 4-3
Bits

Name

Description

Q/L

Bus Choice - When set, causes the current

source (or destination) address to reside

When the bit is cleared,
on the 0-Bus.
1is a local address
the current address
(KXJ11-CA).

I/0

bit

7:5

ADDR

set,

causes the Q-Bus

signal BBS7 to be asserted, which forces
The
the I/0 page.
to
reference
a
y
locall
referenced I/0 page can reside
Q-Bus
the
on
1is cleared) or
(if bit 15
(if bit 15

13:8

When

is set).

Bits <21:16> of the current address.
Must be zero
4-7

Bits

Name

4:3

ACF

Description
Count

method

will

determines

affected

how

the

addresses

DTC

transfer

proceeds.

ACF
00
01
10
11
2:0

Function
Increment address
Decrement address
Hold address
Hold address

Must

The offset consists of
address (Figure 4-4).

bits

zero

<15:00>

the

source

(or

destination)

ADDRESS: 17774400, 17774402,17774410,17774412
15

o
]

]

" CURRENT ADDRESS OFFSET

]

o
]

MR-17132

Figure

4.2.2.2

4-4

Address

Base
Address
Registers
A

and

Address

Registers

and

Base

Address

with

the

B Address

Registers
A
and B -B
are
1identical

Registers

same

reloading

Current

B.
and

information.
Current

Address

Base

Address
Registers.
register bit descriptions.

the

Current

Refer

transfer
Registers
to

The formats
to those of

beginning
Address

Figures

of Base
Current

transfer,

Registers

<can
with

Offset

are

restarted

the

contents

4-3

and

4-4

the

loaded

the

for

the

4.2.2.3
Chain
Address
Register -- The Chain Address Register is
to point to a "reload word", the first word in a chain table
(see Section 4.3.1). The reload word specifies which registers are

used

to
Dbe
chain

loaded, in order to set up a chaining operation. The other
table entries contain the data with which the registers are

loaded.

The
and

Chain
Address
Register consists of
offset. The segment/tag specifies:

two

words,

segment/tag

an
&

the

reload

word

address

resides

the

(Q-Bus

the

reload

word

address

resides

the

I/0

Address

bits

<21:16>

the

reload

word

page

address

The segment/tag has the following format (Figure 4-5).
ADDRESS: 17774444, 17774446
15

ADDR

ojo]o0o}|

1/0

MR-1713%

Bits

Chain Address Segment/Tag

4-5

Figure

Name

Description

Q/L

Bus Choice - When set, indicates that the

reload word address resides on the Q-Bus.
when cleared, indicates that the address

causes the Q-Bus
I/0 bit - When set,
which forces
ed,
assert
signal BBS7 to be
The
page.
I/O0
the
to
reference
a
y
locall
reside
can
page
referenced I/0
Q-Bus
the
on
or
d)
1is cleare
15
(if bit

I/0

is set).

(if bit 15

13:8

Bits <21:16> of the reload word address.

ADDR

Must

7:0

The

offset

(Figure 4-6).

one.

(KXJ11-CA)

is a local

consists

<15:0> of the reload word address

bits

zeros

ADDRESS: 17774440, 17774442
15

L
Figure

4-6

" CHAIN ADDRESS OFFSET
S

01 I QO

TN NN R

Chain Address Offset

4.2.2.4

Interrupt

channel

has

output

occurs,

the

The

1Interrupt

during
the

Status

Vector

and

Interrupt

Vector

interrupt

contents

the

are

Save
Register.
This
chaining
and
a
new

Interrupt

Vector

Save

Interrupt

cycle.

Vector

Each

Interrupt

the

When

vector

automatically

allows
a
new
DMA
operation

into

that

interrupt

and

the

Save

part

Interrupt

vector
to be loaded during
can
be performed before an
The Interrupt Save Register

interrupt
acknowledge
can be read but can not

cycle
occurs.
be directly written by

The
Interrupt
4-7).

Vector

contains

acknowledge

loaded

and

has

the

user.

following

format

(Figure

ADDRESS: 17774530, 17774532
15

06
T

05
1

02
1

s B
SO0

.......

.....
............
KRR
XN QOSSR
.

CRRRANAS!
:

Lo
...........
Mt

Figure

Bits

4-7

Interrupt Vector Register

Name

Description

15:8
7:2

Not
VEC

Not
Interrupt

(read/write)

Interrupt

1:0
The

used

Save

used
has

vector

(read/write)

the

following

format

(Figure

4-8).

ADDRESS: 17774450, 17774452

HRQ

[

MCL

MCH

VEIC

]

04
03 02

]

00
o

EOP

CH NUM
MR-17138

Figure

4-8

Interrupt Save

Bits

Name

Description

HRQ

Hardware

MCH

Match

request

bit

count

bit

copy

Status

high
4.

copy

of Status

Bits

Name

Description

MCL

Match

count

Chain

abort

- A copy of Status Register

Match

count

- A copy of Status Register

EOP

End

process

copy

Status

Terminal

count

copy

Status

CH NUM

Channel

number

When

set,

bit

12.

Interrupt

VEC

Status
:

cleared,

When

refers to

refers

¢to

channel

7:2

channel

copy

low

vector

Vector Register bits

A copy of Interrupt

<7:2>.

Not used

1:0

4.2.2.5 Status Register -- Each channel has a read-only Status
Each status register contains an interrupt status field
Register.
(bits <12:9>), a hardware
a DTC status field
(bits <15:13>),
interface field (bits <6:5>), and a completion status field (bits

The bits that comprise these fields are described below.
<4:0>).
register are copied to the Interrupt Save
the status
of
Parts

when
that

an interrupt occurs. Note that bits <12:9> = 0000
is initialized and waiting for a
the channel

request.

The Status Register has the following format (Figure 4-9).
ADDRESS: 17774454, 17774456

02 01 00
08 07 06 05 04 03]
15 14 13 12/11 10 09/

ofof | |

CIE

IP
IUS

NAC
CA

SIP

HRQ

WFB

MCL
MCH

EOP
MC

TC
MR-17139

Status Register

Figure 4-9

Bits

Name

CIE

Description

set,
When
enable
interrupt
Channel
are
requests
interrupt
that
indicates
as bit 4 of the
same
the
Set
enabled.
Command Register.

IUS

Interrupt
indicates
serviced.
Command

NAC

abort - When set, indicates that a
Chain
has been terminated.
operation
chaining
when the DTC 1is
set
also
1is
bit
This
bit is cleared when a
This
initialized.
new
chain
address segment/tag or offset
word

- When set, indicates
pending
Interrupt
request 1is currently
interrupt
an
that
as bit 2 of the
same
the
Set
pending.
Command

set,
When
service
under
being
1is
interrupt
an
that
same as bit 3 of the
the
Set

loaded.

on chaining - When set,
reload
auto
No
that the channel has completed
indicates

DMA transfer and that neither base-toa
reloading nor auto-chaining were
current
is also set when the
bit
This
enabled.
1initialized. This bit is cleared
1is
DTC
when a Start Chain Command is issued.

WFB

Waiting
for
bus
When set, indicates
channel wants control of a bus
the
that
to perform a DMA transfer.

SIP

Second

interrupt

interrupt
Must
HM

When

set,

acknowledge

occurs.

zero

mask - When set, indicates that
Hardware
this channel is inhibited from responding
channel's
the
of
assertion
the
to
hardware

HRO

pending

1is
interrupt
second
a
that
indicates
on the channel, and that channel
pending
until an
suspended
be
should
activity

request

line.

When set, indicates
request
Hardware
the channel's hardware request line
that
is

asserted.

Bits

Name

Description

MCH

MCL

EOP

End of process - When set,

indicates that

Terminal count - When set,

indicates that

Match

count high - When set,

indicates a

Match

count

low - When set,

indicates a

Match

count - When set,

match
between
the
upper
byte of data
or
transferred-and-searched
being
the pattern determined by
and
searched,
the Pattern and Mask Registers.

of data
byte
1lower
the
between
match
or
transferred-and-searched
being
the pattern determined by
and
searched,
the Pattern and Mask Registers.

indicates that a

due to a
terminated
was
operation
DMA
transferredbeing
data
between
match
the
and
searched,
or
and-searched
specified by bits <1:0> of the
condition
Channel Mode High Register.

a DMA operation was
the
of
assertion
.
line
)
(EOP

terminated due to the
end of process
DTC's

was terminated because
DMA operation
a
the operation count reached zero.

Each
Current and Base Operation Count Registers -4.2.2.6
specifies
which
Register,
Count
Operation
Current
a
has
channel
number of words (or bytes) remaining to be transferred for a
the
DMA operation. The contents of the register are decremented by one
a datum is transferred. A DMA operation can be resumed
time
each
off by using the count contained in this register.
left
it
where
is completed, the register contains zero. The
transfer
DMA
a
When
is specified by loading this register with
K)
(64
count
maximum
ZEero.

Register. The
Operation Count
a Base
has
also
channel
Each
are initially
Register
Count
the Base Operation
of
contents
As the
Register.
Count
Operation
identical to those of the Current
Operation
Base
the
of
contents
the
however,
transfer progresses,
Register are not decremented. If a DMA transfer needs to be
Count
from scratch, the original byte (or word) count can be
restarted
the Base Operation Count
of
contents
the
loading
by
restored
Register,
Count
Operation
Register into the Current
Refer to Figures 4-10 and 4-11

for the register formats.

ADDRESS: 17774460, 17774462

EURI?IENT bPERIATIOII\J COL'JNT |I

]

MR-17140

Current Operation Count Register

Figure 4-10

ADDRESS: 17774464, 17774466
1%

[

BASE OPERATION COUNT

]

02
i

1
MR-17141

Base Operation Count Register

Figure 4-11

and Mask Registers -- Each channel has a Pattern
Pattern
' 4.2.2.7
in search and
used
are
which
Register,
a Mask
and
Register
contains a
Register
Pattern
The
operations.
transfer-and-search
or
whether
determine
to
with
compared
is
data
read
pattern - that
not

condition exists.

"match"

The user can program the DTC to

stop a search when there is a match or when there is no match. The
the
from
selected Dbits
exclude
to
used
is
Register
Mask

Setting a Mask Register bit to "1" excludes that bit
comparison.
from the comparison. The formats of the Pattern and Mask Registers
are

shown

in Figures

4-12

and

4-13.

ADDRESS: 17774510, 17774512

o
T
r
1
T
1
T
Loy

11T
1

MR-17142

Pattern Register

Figure 4-12

ADDRESS: 17774514,17774516

[

TR T

M IS

vaa i MR N

03 .02
|

NN NN N

MR-17143

Figure 4-13

Mask Register

4-14

4.2.2.8

Mode

Channel

channel

Each

has

Mode

Register. The Mode Register specifies what type of DMA operation a
channel will perform, how the operation will be executed, and what
action, if any, will be taken when the operation is completed. The

consists of two words: a Channel Mode High and a
Channel Mode Low. Channel Mode High is used to

mode

Initiate a DMA operation

Specify what is to occur if a match condition exists

software

how

Determines

hardware

and

requests

are

handled.

Channel Mode High has the following format (Figure 4-14).
ADDRESS: 17774524, 17774526

06 05

D
04/ 03 02

0|o|o|o|o|olololo|o|o|sa 1o we |
Channel Mode High

Figure 4-14

Name

Description

Not used

[1 ]

Bits

(read as zeros)

request - When set, initiates a
Software
The channel requests the
n.
operatio
DMA
transfers as specified
performs
and
bus
by XFER in Channel Mode Low.

When set, prevents the

Hardware

mask

Not used

(read as zero)

from responding to the assertion
channel
s hardware request line.
channel'
the
of

Match

Specifies

on
on
on
on

no match
no match
word match
byte match

condition

occur for match conditions.
MC

00
01l
10
11

Action

Stop
Stop
Stop
Stop

what will

Channel

Mode

Low

The

type

Which
source

What

Channel

Mode

specifies
of

of
and

will

operation

and

the
Current
which is the
occur

Low has

when

the

transfer

performed

Address Registers
destination
DMA

following

operation

format

12 11

’

06,?05

04 03202

]

EOPCE

MCCE

Figure

MCBC

4-15

the

4-15).

EOPIE

TCIE

FLIP

MCIE

EOPBC

TCBC

XFER

TCCE

completed

(Figure

ADDRESS:'17774520, 17774522

15 14

(A or

Channel

Bits

Name

Description

TCCE

Terminal

Mode

count

Low

chain

enable

When

set,

causes
a
chain
reload for the next DMA
operation
1if the Current Operation Count
Register is decremented to zero.
14

MCCE

EOPCE

Match

count
chain
enable
When set,
causes
a
chain
reload for the next DMA
operation if a match condition exists.
End

process

chain

enable

When

set,

causes
a
chain
reload for the next DMA
operation
if
an
end-of-process
(EOP)
termination occurs.
12

TCBC

Terminal

causes
Current

count

decremented
11

MCBC

Match

base-current

base-to-current
Operation
Count
to

count

EOPBC

End

causes

base-current

process
a

TCIE

Terminal

set,
the

count

the

decremented

i1ssues

zero.

termination

Operation
to

set,

the
1is

set,

When

reload

interrupt

channel

Current

4-16

base-current

(EOP)

When

reload

base-to-current

end-of-process
9

When

zero.

causes
a
base-to-current
match condition exists.
10

reload if
Register

set,
if

occurs.

enable

When

interrupt

Count

"Bits

Name

Description

MCIE

count
Match
channel
the

interrupt enable - When set,
issues

interrupt

match condition exists.

EOPIE

End
set,

the

interrupt enable - When
channel issues an interrupt 1if

process

termination

(EOP)

end-of-process

OCCurs.

XFER

Transfer
transfer
the
to

Specifies

type

the

type

for

Manual

Technical

DTC

Refer

the channel will perform.

descriptions of these transfers.
XFER Transfer Type

01
10
11
FLIP

Flip

Single transfer

Demand dedicated with bus hold
Demand dedicated with bus release
Channel to channel demand interleave
-

bit

set,

When

Current Address

and
source,
the
contains
Register A contains the
Address
Current
of a transfer. When cleared,
destination

Current

and

Current

contains

the

source

Address Register B contains

the destination.

OoP

Operation
operation

type

the

Specifies the type of
channel will perform. See

the DTC Technical Manual for descriptions

of these operations.

Operand
Size
OP

Operation

0000
0001

Transfer
Transfer
Reserved
Reserved

word Word

0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Trnsf-Search
Trnsf-Search
Reserved
Reserved
Transfer
Reserved
Reserved
Reserved
Trnsf-Search
Reserved
Search
Search

4-17

Byte

Transaction
Type

Flowthrough
Flowthrough

Byte

Flowthrough
Flowthrough

Byte

Word

Flowthrough

Byte

Word

Flowthrough

Word Word

Word Word
Byte

Byte

Read

NOTE

"Flyby"
the

4.3

general

are

not

supported on

KXJ11l-CA.

PROGRAMMING

Programming the
DMA
Operation,

operations

THE

DTC

DTC consists of three phases: Chip Initialization,
and
Termination.
This
section
will provide a

description

these

phases.

4.3.1
Chip Initialization
The RESET instruction is used to place the DTC in a known state. A
reset will clear the CIE, IP, SIP and WFB bits, and set the CA and
NAC bits in the Channel Status registers. The Master Mode register
will
also
be
<cleared.
Before a DMA operation is initiated, the
local
CPU
1loads
the
Master Mode register and the Chain Address
register
of
the
appropriate channel of the DTC. The DTC fetches
any
other
parameters
that are necessary from a table located in
system
memory known as the chain table. This minimizes the amount
of
CPU
1intervention
necessary
to
perform a DMA operation. The
relationship
of
the Chain Address Register to the chain table is
shown in Figure 4-16.
The
first
word in the chain table is the reload word. The reload
word
1is
used to specify which registers should be loaded for the
pending DMA operation. Bits <9:0> of the reload word correspond to
the registers of the DTC as shown in Figure 4-17. Bits <15:10> are
not

used.

Therefore,
if
a
bit
in
the
reload
word
1is
set,
then
the
corresponding
registers
are to be reloaded from the chain table.
Since
all
of
the
registers
are
not
applicable
to
each DMA
operation, the chain table may be of variable length (that is, the
pattern
and
mask
registers
would not be used in DMA operations
that do not search the data). It is incorrect to select a register
in
the
reload
word
and
subsequently load that register with a
dummy
argument
such as zero. Figures 4-18 and 4-19 show examples
of the relationship between the reload word and the chain table.
The
DTC
has been properly initialized once the chain tables have
been
created,
and
the
Master
Mode
register and Chain Address
Register for the selected channel have been loaded.

CURRENT ARA
CURRENT ARB
CURRENT OP-COUNT

BASE ARA
BASE ARB
BASE OP-COUNT

PATTERN AND MASK
INTERRUPT VECTOR
CHANNEL MODE

CHAIN ADDRESS
MR-0586-0688

Figure

4-16

Chain Address

SYSTEM
MEMORY

RELOAD WORD

DTC

CHANNEL 0 /

1
DTC

CHAIN
ADDRESS |

NEW CHAIN ADDRESS

REG

RELOAD WORD

DTC
REGISTER
DATA

MR-0586-0689

Figure

4-17

Reload

Word

4-19

CURRENT ARA SEGMENT/TAG
CURRENT ARA OFFSET

CURRENT ARB SEGMENT/TAG
CURRENT ARB OFFSET

CURRENT OP—COUNT
CHANNEL MODE HIGH

CHANNEL MODE LOW

MR-0186-0098

Example

Figure 4-18

CURRENT ARA SEGMENT/TAG
CURRENT ARA OFFSET

CURRENT OP—COUNT

PATTERN REGISTER

MASK REGISTER

CHANNEL MODE HIGH

CHANNEL MODE LOW

CHAIN ADDRESS SEGMENT/TAG
CHAIN ADDRESS OFFSET

MR-0186-0099

Figure 4-19

Example

4.3.2

DMA Operation

The
DTC
may
perform
a
DMA operation once it has been properly
initialized. A DMA operation may be initiated in one of four ways:
by
software
request,
by
hardware
request,
by
1loading
a set
software request bit in the Channel Mode register during chaining,
or as the result of a command from the arbiter.

Software
Request:
The
1local CPU may initiate a DMA operation by
writing
a
Start
Chain
command
to the Command Register. If the
Software
Request
bit
1is
not
set
as
part
of the start chain
command,
then
the
Software
Request <command
can
be issued to
initiate

the DMA operation.

The Software Request command

sets

the

software request bit in the channel's mode register. If either the
Second
Interrupt Pending (SIP) bit or the No Auto-Reload or Chain
(NAC)
bit
1is
set
1in
the
channel's
status
register, the DMA
operation
will
not
begin.
The SIP bit will be cleared when the
channel
receives
an
interrupt
acknowledge. The NAC bit will be

cleared when the channel receives a Start Chain command.

The Start

Chain
command
1initiates the DMA operation after the registers of
the
selected
channel
are loaded from the chain table. The Start

Chain
command
is
ignored if the SIP bit or the Chain Abort (CA)
bit
are
set
1in
the
channel's status register. The SIP bit was
described
above.
The
CA bit is cleared when the channel'’s chain
address

1is

reloaded.

Hardware
Request:
DMA
operations
may be started by asserting a
channel's
DREQ
input
from
SLU2 or the PIO. The mask bit in the
Channel
Mode
Register
controls
whether
or not this request is
detected.

Starting
After
Chaining:
If
the
software
request
bit of the
channel's Master Mode register is set during chaining, the channel
will perform the DMA operation at the end of chaining.
Arbiter
Request:
The
arbiter
may
1interrupt
the
1local CPU to
request
a
DMA
operation.
This
1is
accomplished
by
passing
parameters to load the chain address register of channel 0 through

the two-port RAM. The arbiter loads register 2 of the TPR with the
offset
of the chain address register, and loads register 3 of the
TPR with
the
segment/tag of the chain address register. The DMA
operation is then initiated by setting the DMA Load bit (bit 1) in
the
TPR
command
register (register 0). Error conditions will be
returned

in TPR register

Information in the channel's mode register determines what type of

DMA
operation
will
be
performed.
The
Channel
Mode
register
consists of two words: Channel Mode High and Channel Mode Low.
Bits <3:0> of the Channel Mode Low register select the type of DMA
operation.
These
bits
determine
whether
the
data
should
be
transferred,
searched,
or transferred-and-searched. Bit 4 is the
flip
bit.
It
1is
wused to determine which set of current address
CARB)

points

to the

(CARA,

registers

source.

Bits <6:5> determine the transfer type. The types of DTC transfers
hold, demand
with bus
dedicated
demand
transfer,
single
are
demand
channel-to-channel
and
release,
bus
with
dedicated
wused with devices that transfer
1is
transfer
Single
interleave.
irregular intervals. A single DMA transaction will occur
at
data
a Software Request command is issued or the DREQ input
time
each
bus hold is a software hog
with
dedicated
Demand
asserted.
is

allows the DMA transaction to run to completion
This mode
mode.
1local addresses, as long as there is a valid op count and the
for

is asserted. If the DREQ input is not asserted, no DMA
input
DREQ
will occur but the channel will retain bus control. In
operations
0-Bus hog mode, the KXJ11-CA releases the bus and requests the bus

again
is

after each word transfer. Demand dedicated with bus release

similar

demand

dedicated

with

bus

hold,

because a DMA

allowed to run to completion if DREQ is asserted.
1is
transaction
DTC must release the bus, thus
the
asserted,
not
is
DREQ
If
other devices to obtain the bus. The operation performed
allowing
channel-to-channel demand interleave request depends on the
a
by
state of bit 2 in the Master Mode register. If MM bit 2 is clear,
then control may be passed between each channel of the DTC without
the need to release the bus. If MM bit 2 is set, then the DTC must
bus with the local processor. The DTC will release the
the
share
bus and then request it again after every DMA iteration.

Bits <1:0> of the Channel Mode High register are used to determine
and Transfer-and-Search
in Search
type of match control
the
1is capable of generating a termination
The DTC
operations.
condition based on 'No Match', 'Word Match', and 'Byte Match’.
the Channel Mode High register causes the channel to
of
<4>
Bit
and perform transfers when it is set by a Software
bus
the
request
Request

4.3.3

command or a chain reload.

Termination Options

the
control
register
Low
the Channel Mode
of
<15:7>
Bits
number
a
in
terminated
be
may
operation
DTC
A
options.
termination
Current Operation Count Register goes to zero,
the
If
ways.
of
termination is generated. External
(TC)
Count
Terminal
a
then
Process (EOP) input of the DTC to
Of
End
the
assert
may
logic
any time. In addition, during a
at
termination
EOP
an
generate
a match condition may
operation,
-Search
Transfer-and
or
Search
<15:7> allow the DTC
Bits
termination.
MC
a
generates
that
occur
or to
reload,
ent
base-to-curr
a
reload,
chain
a
perform
to
termination
MC
or
EOP,
TC,
a
if
processor
1local
the
interrupt
<15:7> are cleared, then no
bits
If
encountered.
1is
condition
EOP, or MC condition 1is
TC,
a
when
initiated
1is
action
special
encountered.

EOP Condition Handling

4.3.3.1

reference to
of a
a result
EOP conditions occur either as
Q-Bus
condition.
timeout
Q-Bus
a
to
due
or
memory
nonexistent
the
to
access
granted
not
1is
KXJ11-CA
the
when
occur
timeouts
0-Bus by the arbiter within a fixed period of time (approximately
<condition only occurs during periods of heavy
The
wusecs).
140
for the 0-Bus by other peripherals performing DMA
contention
is possible to recover the DMA transfer operation
It
operations.
from the point of termination, depending upon the application of
the

DMA channel.

between an EOP condition resulting from a Q-Bus
differentiate
To
to nonexistent memory, bit 5 of KXJCSRJ
reference
a
and
timeout
This status bit is used to notify the
tested.
be
may
TOUT)
(SACK
condition has occurred. It is a
timeout
Q-Bus
a
that
application
specific to a particular DMA
not
is
it
because
bit
status
global
condition that occurred
timeout
a
by
set
be
may
bit
This
channel.
that the exception
suggest
We
channels.
DMA
both
or
one
on
context of both
needed
the
to
access
have
always
handler
condition
DMA

channels.

it has been determined that a Q-Bus timeout condition has
Once
occurred, it is possible to restart the DMA operation by using the
Current Operation Count register (Section 4.2.2.6). This register
(or bytes, depending on mode of
number of words
the
contains
|
operation) remaining to be transferred.
Examples

4.3.4

The following example programs were developed on a PDP-11/23+
(version 5.1)
wusing the RT-11
system with 256KB of memory,
Software
Processor
Peripheral
KXJ11-CA
the
with
system
operating
and the
MACRO-11
with
familiar
be
should
programmer
The
Toolkit.
KXJ11-CA Peripheral Processor Toolkit.
EXAM1.MAC

This program transfers data from local KXJ11-CA addresses to

local KXJ11-CA addresses. This program should be compiled and
linked on the development system, and then downloaded into the
KXJ11-CA using the KXJ11-CA Software Toolkit. Once the program
has been compiled and linked, use the following KUI commands to
execute

it and verify

its success.

+KUI

KUI>SET n

! Where n is the appropriate KXJ11-CA

KUI>ODT
o

| Use KUI ODT to verify that the
destination addresses are cleared

KUI>LOAD EXAMI

VWO

.TITLE

ODT>CTRL/C

KUI>EXECUTE

KUI>ODT
.

Execute EXAMI

I Use KUI ODT to verify that the transfer
was successful

O
WO

KUI>EXIT

ODT>CTRL/C

;

SET

174470

;

MASTER MODE

CMDREG

CASTFO0

174454

;

COMMAND REGISTER

174446

;

CHANNEL O CHAIN ADDRESS SEGMENT/TAG
FIELD

;

CHANNEL

CAOFO

START:

MOVB

#130,MMREG

LOAD MASTER MODE

CLRB

CMDREG

RESET

MOV

#0,CASTFO

MOVB

#240,CMDREG

;

CHAIN

RELOAD:

LOAD

#102,CMDREG

MOVB

LOAD

SEG/TAG

#131,MMREG

THE

ADDRESS
REG

OFFSET
TO

DISABLE

CHAIN

ADDRESS

LOAD

CHAIN

ADDRESS

LOAD

SET

START CHAIN

THE

MASTER MODE

SOFTWARE

REG

REQUEST
CHANNEL
THE

ENABLE

CHANNEL

DTC

OFFSET

DTC

STAY

HERE

WHILE

;

THAT

THE

PROGRAM

USER VERIFIES

;

RELOAD WORD

CURRENT ADDRESS REGISTER A SEG/TAG

WAS

SUCCESSFUL

REGION

.WORD

001602

<Select

CARA,CARB,COPC,CM>

;

SOURCE

. CURRENT ADDRESS REGISTER A
- <{This local address is the

« WORD

000000

« WORD

DESTNT

CURRENT

OFFSET

o
e

the

CHANNEL

MODE

CHANNEL

MODE

000040

1is

CURRENT OPERATION

000000

- WORD

words>

COUNT

<Transfer

LOW

<{No match conditions, do nothing
upon completion, transfer

« WORD

ADDRESS

CURRENT ADDRESS REGISTER B SEG/TAG

type =

Demand

wWe

000013.

OFFSET
source>

000000

« WORD

FIELD

DTC

MOVB

THE

#RELOAD,CAOFO

CHAIN

MOV

174442

;

=
©

MMREG

CARA =

source,

Dedicated w/Bus
word

transfers>

Hold,

SOURCE:

.WORD

1,2,3,4,5,6,7,6,5,4,3,2,1

DESTNT:

.BLKW

13.
START

«END

EXAM2.MAC

This program transfers data from local KXJ11-CA addresses to
global Q-Bus addresses. This program should be compiled and
linked on the development system, and then downloaded into the
KXJ11-CA using the KXJ11-CA Software Toolkit. Once the program
has been compiled and linked, use the following commands to
execute it and verify its success.

<HALT the development machine so that locations may be examined
Q-Bus

with

ODT>

! Examine the destination locations and clear

@600000/xxxXXXX

them

i1if

necessary

.TITLE

@600030/xxXXXX

Use the

'P'

command to return to the system

KUI>LOAD EXAM2
KUI>EXECUTE
KUI>EXIT

Where n is the appropriate KXJ11-CA

<HALT the development machine so that locations may be examined
with

Q-Bus

ODT>

@600000/xxXXXX
.

! Examine the destination locations to verify
the success of

the transfer

)

@600030/xxXXXXX

‘

+KUI

KUI>SET n

VWO

prompt

SET

MMREG
CMDREG

=
=

174470
174454

;
;

MASTER MODE REGISTER
COMMAND REGISTER

CAOQOFO

174442

CHANNEL O CHAIN ADDRESS OFFSET FIELD

START:

MOVB

174446

+ CHANNEL O CHAIN ADDRESS SEGMENT/TAG FIELD

#130,MMREG

s LOAD MASTER MODE REG TO DISABLE DTC

CLRB

CMDREG

CASTFO

MOV

#0,CASTFO

MOV

#RELOAD,CAOF0

;

RESET THE

DTC

LOAD THE CHAIN ADDRESS REGISTER

SEG/TAG

;

OFFSET

LOAD THE CHAIN ADDRESS REGISTER

;

CHAIN

RELOAD:

MOVB

#131,MMREG

LOAD

MOVB

#102,CMDREG

SET

MOVB

#240,CMDREG

START

STAY

HERE

WHILE

THAT

THE

PROGRAM

LOAD

REGION

« WORD

SOFTWARE
CHAIN

RELOAD WORD

REG

REQUEST
CHANNEL

<Select

THE
WAS

ENABLE

CHANNEL

DTC

O
USER VERIFIES
SUCCESSFUL

CARA,CARB,COPC,CM>

« WORD

000000

CURRENT ADDRESS

« WORD

SOURCE

CURRENT

<This

CURRENT ADDRESS

+
s

CURRENT ADDRESS REGISTER B
<This global Q-Bus address

«
;s
+
;

destination>
<This corresponds to address 600000 on
the Q-Bus>
<The DTC uses physical addresses only>

« WORD

¢
SOURCE

001602

MASTER MODE

101400
00000

000013.

ADDRESS

local

address

OFFSET

source>

CURRENT OPERATION COUNT

words>

OFFSET
is the

<Transfer

« WORD

000000

CHANNEL

« WORD

000040

CHANNEL

¢
s
+
s+

« WORD
« END

MODE
MODE

the

1,2,3,4,5,6,7,6,5,4,3,2,1
START

EXAM3.MAC

This program transfers data from global Q-Bus addresses to local
KXJ11-CA addresses. This program should be compiled and linked
on the development system, and then downloaded into the KXJ11-CA
using the KXJ11-CA Software Toolkit. Once the program has been
compiled and linked, use the following commands to execute it
its

and verify

success.

<Use 0-Bus ODT to deposit values in locations

600000(8)-->600030(8).

These values will be the source for this operation>
@600000/000001

! Deposit source values

@600030/000001

| Use the 'P' command to return to the system
prompt

.KUI

! Where n is the appropriate KXJ11-CA

KUI>LOAD EXAM3
KUI>EXECUTE

1 Use KUI ODT to examine the destination

KUI>ODT

locations to verify that the transfer was

KUI>SET n

.TITLE

KUI>EXIT

SET UP REGISTER ASSIGNMENTS

=
=

174470
174454

;s
;

CAOFO

174442

s+ CHANNEL 0 CHAIN ADDRESS OFFSET FIELD

START:

MOVB

#130,MMREG

CLRB

CMDREG

MOV

#0,CASTFO

MASTER MODE REGISTER
COMMAND REGISTER

MMREG
CMDREG

#RELOAD,CAOFO

ODT>CTRL/C

successful
OoDT>

=
@

. CHANNEL O CHAIN ADDRESS SEGMENT/TAG FIELD

174446

#240,CMDREG

%®

MOVB

#131,MMREG
#102,CMDREG

<20

MOVB
MOVB

MOV

CASTFO0

LOAD MASTER MODE REG TO DISABLE DTC
RESET THE DTC
LOAD THE CHAIN ADDRESS REGISTER
SEG/TAG
LOAD THE CHAIN ADDRESS REGISTER
OFFSET

LOAD MASTER MODE REG TO ENABLE DTC
SET SOFTWARE REQUEST CHANNEL O

START CHAIN CHANNEL O
STAY HERE WHILE THE USER VERIFIES
THAT THE PROGRAM WAS SUCCESSFUL
4-277

000000

« WORD

DESTNT

« WORD

101400

« WORD

000000

« WORD

RELOAD WORD

001602

CURRENT ADDRESS

RELOAD:
. WORD

CURRENT ADDRESS

REGION

<This

LOAD

CURRENT ADDRESS

CHAIN

CURRENT ADDRESS

000000

« WORD

000060

the

CURRENT OPERATION

COUNT

HIGH

LOW

WO
O
WO

OFFSET

<Transfer

MODE

destination>

MODE

START

CHANNEL

« END

13.

address

CHANNEL

TMY

DESTNT:
. BLKW

« WORD

local

<SelectCARA,CARB,COPC,CM>

000013.

« WORD

)

;

words>

<{No match conditions, do nothing upon
completion, transfer type = Demand
Dedicated w/Bus Hold,
CARB = source, word
transfers> <Notice how similar this reload
table
is to the one in EXAM2. By utilizing
the flip bit in the CM Reg Low, no further
changes were necessary to use the table 1in
this example>

EXAM4.MAC

This program transfers data from global Q-Bus addresses to other
global Q-Bus addresses. This program should be compiled and
linked on the development system, and then downloaded into the
KXJ11-CA using the KXJ11-CA Software Toolkit. Once the program
has been compiled and linked use the following commands to
execute it and verify its success.

{Use Q-Bus ODT to deposit values in locations

600000(8)-->600030(8).

These values will be the source for this operation>
@600000/000001

! Deposit source values

@600030/000001

| Use the 'P' command to return to the system
prompt

.KUI

KUI>SET n

KUI>LOAD EXAM4

! Where n is the appropriate KXJ11-CA

KUI>EXECUTE
KUI>EXIT

@610000/xxXXXXX

.TITLE

8610030/xxXXXX

| Return to system prompt

SET UP REGISTER ASSIGNMENTS

MMREG
CMDREG

=
=

174470
174454

¢+ MASTER MODE REGISTER
;s COMMAND REGISTER

CAOFO0

174442

- CHANNEL 0 CHAIN ADDRESS OFFSET FIELD

MOVB #130,MMREG

#0,CASTFO

MOV

#RELOAD,CAOFO

MOVB #102,CMDREG
MOVB #240,CMDREG
BR

MOVB #131,MMREG

QW0

MOV

CLRB CMDREG

: CHANNEL O CHAIN ADDRESS SEGMENT/TAG FIELD

=
9

174446

START:

LLOAD MASTER MODE REG TO DISABLE DTC

RESET THE DTC
[LOAD THE CHAIN ADDRESS REGISTER
SEG/TAG
LOAD THE CHAIN ADDRESS REGISTER
OFFSET

LOAD MASTER MODE REG TO ENABLE DTC
SET SOFTWARE REQUEST CHANNEL O
START CHAIN CHANNEL O

STAY HERE WHILE THE USER VERIFIES
s+ THAT THE PROGRAM WAS SUCCESSFUL

CASTF(Q

4-29

101400

« WORD

000000

CURRENT ADDRESS
CURRENT

<This

destination>

to Q-Bus

COUNT

CURRENT OPERATION

CHANNEL

MODE

CHANNEL

MODE

OFFSET

the

address

<Transfer

LOW

{No match conditions, do nothing upon
completion, transfer type = Demand
Dedicated w/Bus Hold,
CARA = source, word transfers>

START

« END

address

000040

1is the source>
address

global Q-Bus

000000

« WORD

OFFSET

words>

« WORD

ADDRESS

000013.

VWO

« WORD

ADDRESS

CURRENT ADDRESS

101400
010000

CARA,CARB,COPC,CM>

CURRENT

« WORD

<Select

« WORD

RELOAD WORD

- WORD

« WORD

001602

=
9

REGION

RELOAD:

LOAD

CHAIN

;

.TITLE EXAM5.MAC

the
This program demonstrates how chaining is implemented using
m
progra
under
ted
initia
be
will
er
DTC. A local to local transf
to
local
a
DTC,
the
of
e
featur
ng
chaini
control. Then, using the

global transfer will be performed, followed by a global to
global transfer, and finally a global to local transfer. The

following diagram illustrates these transfers.

WY
WO

mmmmmmmm =
—————————————— |

Transfer #1

@ WO WO WO WP WO WP WO WO WO WO wWe O W Wy WO VWO WO WO WO WY WY WO We We Wo o @) WY WO WY WO W WO

O-Bus Memory

KXJll—CA Memory
$m——

+-=>

————————————

Transfer #2

| emmmmmm———————- >

Transfer #3

——————————

———t

(==t

m
e
(mmmmmmmmm

This program should be compiled and linked on the development
system and then downloaded into the KXJ11-CA using the KXJ11-CA

software Toolkit. Once the program has been compiled and linked
|

use the following commands to execute it and verify its
success.

<Use O-Bus ODT to clear the memory locations 600000(8) -->
600030(8) and 6100000(8) --> 610030(8) before executing the

program>
-KUI

KUI>SET n

I Where n is the appropriate KXJ11-CA

KUI>EXECUTE

I Use KUI ODT to verify that the destination

KUI>LOAD EXAMS

KUI>ODT
OoDT>
OoDT>

contents are accurate

ODT>CTRL/C
KUI>EXIT

<Use 0-Bus ODT to examine the contents of the intermediate

destinations to verify their accuracy>
SET UP REGISTER ASSIGNMENTS

MMREG
CMDREG

=
=

174470
174454

; MASTER MODE REGISTER
; COMMAND REGISTER

CAOFO0

174442

; CHANNEL O CHAIN ADDRESS OFFSET FIELD

CASTFO

174446

:; CHANNEL O CHAIN ADDRESS SEGMENT/TAG FIELD

MOVB

#130,MMREG

LOAD MASTER MODE REG TO DISABLE DTC

CLRB

CMDREG

RESET

MOV

#0,CASTFO

LOAD THE

CHAIN

ADDRESS

#LOAD1 ,CAOQOFO0

+
e

SEG/TAG
LOAD THE

CHAIN ADDRESS

OFFSET

LOAD

MASTER

@
@

SET

SOFTWARE

START

MOVB

#131,MMREG

MOVB

#102,CMDREG

MOVB

#240,CMDREG

MODE

CHAIN

REG

REQUEST

CHANNEL

STAY

HERE

WHILE

THAT

THE

PROGRAM

ENABLE

CHANNEL

DTC

THE

USER VERIFIES

WAS

SUCCESSFUL

« WORD

000000

« WORD

AREA2

AREAl

CURRENT

ADDRESS

SEG/TAG

CURRENT

ADDRESS

OFFSET

<This

transfer
CURRENT

ADDRESS

CURRENT

ADDRESS

=
w0

CHANNEL

MODE

HIGH

CHANNEL

MODE

LOW

RELOAD WORD

<Select

SEG/TAG

OFFSET

the

source

WO
REG

local address
#2>

CURRENT ADDRESS

SEG/TAG

<This

CURRENT

OFFSET

ADDRESS

<This global
transfer #2
4-32

word

CARA,CARB,COPC,CM,CA>

transfer

upon

chain

CURRENT ADDRESS
ADDRESS

source,

CARA =

CURRENT

101400

ADDRESS

Hold,

reload
Demand

RNE

000000

w/Bus

CHAIN

AREA?2

000000

<Transfer

CHAIN ADDRESS

«WORD

« WORD

destination

transfers>

« WORD

COUNT

SEG/TAG

Dedicated

001603

« WORD

OFFSET

<{No match conditions, chain
completion, transfer type =

LOAD2

the

LOAD2

OPERATION

1is

CURRENT

000000

« WORD

words>

« WORD

source

100040

the

000000

« WORD

1is

« WORD

address

#1>

000013.

local

« WORD

CARA,CARB,COPC,CM,CA>

000000

« WORD

<Select

« WORD

RELOAD WORD

001603

« WORD

LOADl1:

=
e

CHAIN LOAD REGION

;

DTC

MOV

THE

START:

address is the
- 600000(8)>

destination

000000
« WORD 100040

« WORD

001603

« WORD

101400
000000

<o
w®
WO
WO
WO
W
%y

000013,

000000
100040

000000
LOAD4

« WORD

1014060
010000

000000

« WORD

AREA3

» WORD

« WORD

001602

« WORD

LOAD4

< @

« WORD

CHAIN ADDRESS REGISTER SEG/TAG

wd
WO
QY
=Y

101400
010000

TMy

« WORD

word

CHAIN ADDRESS REGISTER OFFSET

<This address points to the new chain

« WORD

CARA = source,

table>

LOAD3

transfers>

« WORD

000000
LOAD3

{No match conditions, chain reload upon
completion, transfer type = Demand
Dedicated w/Bus Hold,

« WORD

CHANNEL MODE REGISTER HIGH
CHANNEL MODE REGISTER LOW

wWd

« WORD

CURRENT OPERATION COUNT <Transfer 13
words>

000013.

«WORD

RELOAD WORD <Select CARA,CARB,COPC,CM,CA>

CURRENT ADDRESS REGISTER A SEG/TAG
CURRENT ADDRESS REGISTER A OFFSET

<This global address is the source of

transfer #3>

<600000(8)>

CURRENT ADDRESS REGISTER B SEG/TAG
CURRENT ADDRESS REGISTER B OFFSET

<This global address is the destination of
transfer #3 -

610000(8)>

CURRENT OPERATION COUNT <Transfer 13
words>

CHANNEL MODE REGISTER HIGH
CHANNEL MODE REGISTER LOW

{No match conditions, chain reload upon
completion, transfer type = Demand
CARA = source, word
Dedicated w/Bus Hold,
transfers>

CHAIN ADDRESS REGISTER SEG/TAG
CHAIN ADDRESS

RELOAD WORD <Select CARA,CARB,COPC,CM>

CURRENT ADDRESS REGISTER A SEG/TAG
CURRENT ADDRESS REGISTER A OFFSET

<This global address is the source of

transfer #4>
<610000(8)>

CURRENT ADDRESS REGISTER B SEG/TAG
CURRENT ADDRESS REGISTER B OFFSET

<This local address is the destination of
transfer

#4>

4-33

O
e

000000
000040

CURRENT OPERATION
words>

wWe

WTM

.WORD
-WORD

000013.

.WORD

AREAl
AREA?2

« BLKW

13.

AREA3

13.

BLKW

« END

START

CHANNEL MODE
CHANNEL MODE

COUNT

<Transfer

<{No match conditions, do nothing upon
completion, transfer type = Demand
Dedicated w/Bus Hold, CARA = source,
word transfers>

EXAM6.MAC

This program demonstrates how to initiate a DTC operation from
the arbiter CPU. This program will transfer a block of data from
O-Bus memory to KXJ11-CA memory. All of the information
necessary for the transfer will reside in Q-Bus memory (chain
table, source data). This program should be compiled, linked,
and run on the arbiter development system. After the program

executes, use the following KUI commands to verify the transfer.

KUI>ODT

! Where n is the appropriate KXJ11-CA

ODT>5000/xXxxXXXX
.

| Examine locations 5000 --> 5030 to verify
that the data was transferred correctly

KUI>EXIT

WO
WO

ODT>5030/XxXXXXX
ODT>CTRL/C

+KUI

KUI>SET n

TM0

LY )

.TITLE

Two-port RAM register definitions

TPR0=160100
TPR2=160104
TPR3=160106
EXIT

.MCALL

START: MOV #100000,TPR3 ; Place Chain Address Reg Seg/Tag in TPR3
.+ Place Chain Address Reg Offset in TPR2
MOV #LOAD,TPR2
Issue DMA Load command to the command

#2,TPRO

BIS

001602

.WORD

100000

. WORD

SOURCE

.JWORD

000000

.WORD

005000

+.WORD

000013.

.WORD
.WORD

000000
000040

.WORD

LY)

LOAD

« EXIT

source>
CARA OFFSET

CARB SEG/TAG <Select KXT address 5000
as destination>

CARB OFFSET

s+ COPC <Op-count = 13 words>

SOURCE:

RELOAD WORD <Select CARA,CARB,COPC,CM>
CARA SEG/TAG <Select Q-Bus address as

CM High

CM Low <select no termination options,
software hog-mode, CARA = source, word
transfers>

.WORD

1,2,3,4,5,6,7,6,5,4,3,2,1

« END

START

CHAPTER

PARALLEL I/O CONTROLLER

OVERVIEW

5.1

1I/0 controller (PIO) is designed around the AmZ3036
The parallel
on the operation of the AmZ28036, refer to the
details
For
chip.
1I/0 Unit Technical Manual
and Parallel
er
Counter/Tim
28036
information that
The
package.
on
documentati
this
in
included
implemented on
functions
PIO
the
describes
and
summarizes
follows
the

KXJ11-CA.

The KXJ11-CA PIO has the following features.

Two 8-bit, double buffered, bidirectional I/O ports

A 4-bit special purpose I/0 port
Four handshake modes

REQUEST signal for utilizing the DMA controller
Pattern recognition logic

Three independent 16-bit counter/timers

The two 8-bit ports (A and B) are identical except that Port B can
access to Counter/Timers 1 and 2. Each port may
external
provide

be configured under program control
or
1logic,
with handshake
port
recognition
Pattern
applications.
port. This logic allows interrupt
Ports A
1is recognized.
pattern
16-bit port with handshake logic.

as a single or double-buffered
as a bit port for control
logic is also included in each
generation whenever a specific
and B may be linked to form a

When Port A or B 1is wused as a port with handshake logic, the
control lines are supplied by a special 4-bit port (Port C). If no
handshake lines are required, then Port C may be used as a bit
Port C also provides external access to Counter/Timer 3 and
port.
a REQUEST 1line that allows the PIO to utilize the DMA controller
when transferring data.

identical 16-bit counter/timers. These
The PIO supplies three
a frequency of 2 MHz, which provides a
at
counter/timers operate
counter/timer may operate with one of
Each
ns.
resolution of 500
three

output

addition,

duty

each

cycles:

unit

may

pulse,

one-shot, or square-wave.

operate

retriggerable

non-retriggerable. Timers 1 and 2 can be cascaded to make a 32-bit
timer. External count, external gate, and external trigger lines
are provided for all three counter/timers.

PARALLEL I/O PORT (PIO) REGISTERS
5.2
designed around the AmZ78036 chip and consists of
The
PIO
1is
8-bit
port
and
ports:
one
4-bit
a
counter/timer.
Table

two

5-1
the

PIO.
summarizes
the
registers
associated
with
the
All
registers
in
reside
in
Table
the
5-1
AmZ7Z8036 chip, with the
exception of the I/0 Buffer Control Register, which resides in the
on-board
gate array (DC7037B). The sections that follow give
GAS
brief descriptions of the PIO registers.

Table

5-1

PIO Registers

Master Control Registers
Master Interrupt Control Register
Master Configuration Control Register

Port Specification Registers
Port Mode Specification Register
Port Handshake Specification Register
Port Command and Status Register
Bit Path Definition Registers
Data Path Polarity Registers
Data Direction Registers
Special I/0 Control Registers

17777000
17777002
A

17777100

17777120

17777102
17777020

17777122

17777022
B

17777104

17777124

17777012

17777106

17777126

17777014

17777110

17777130

17777016

Definition Registers
Pattern Polarity Registers (PPR)
Pattern Transition Registers (PTR)
Pattern Mask Register (PMR)

17777112
17777114

17777132
17777134

17777116

17777136

Port

17777032

17777034

17777036

C/T 1

C/T

C/T 3

17777070

17777072

Pattern

PIO
PIO

Data Registers

Counter/Timer
Counter/Timer
Counter/Timer
Counter/Timer
Counter/Timer
Counter/Timer
Counter/Timer

Control Registers
Mode Specification
Command and Status
Time Constant (MSB)
Time Constant (LSB)
Current Count (MSB)
Current Count (LSB)

17777074

17777024

17777026

17777030

17777054
17777056

17777060
17777062

17777040
17777042

17777044
17777046

17777064
17777066
17777050
17777052

Interrupt Related Registers
Interrupt Vector Register
Current Vector Register

C/T

17777004
17777076

17777006

17777010

I/0 Buffer Control

17777140

PIO
PIO

PIO

5.2.1

The

PIO.

Master Control Registers

Master

Control Registers affect the overall operation of the

There are two Master Control Registers: the Master Interrupt

the Master Configuration Control Register.

and

Control

except

bit

5.2.1.1

Master Interrupt Control Register -- See Figure 5-1.

All

bits

of these two registers are cleared upon hardware reset,

of the Master Interrupt Control Register, which 1is

set. Both registers are read/write.

ADDRESS: 17777000

CT T[] [ofefofefefo]|
MIE

RIS
MR-17161

Master Interrupt Control Register

Figure 5-1

Bits

Name

Not used (read as ones)

15:8

MIE

Master

interrupt

enables

interrupts.

prevents
interrupt
interrupt

enable - When cleared,

PIO
the
or
service
acknowledge

requesting
from
to an
responding
When set,
cycle.

Must be zero

6:1

Description

RIS

Reset

- Set upon hardware reset. Must be

When set, reads of
explicitly cleared.
other PIO registers will yield a value of
one,

and writes will be ignored.

5.2.1.2

Master Configuration Control Register -- See Figure 5-2.
ADDRESS: 17777002
%

NN EEEEEEEE
|

PIE

T2E

LAB

PAE

T3E

T1E

MR-17162

Figure 5-2

Bits

Name

15:8

PBE

Master Configuration Control

Description

Not used

(read as ones)

Port

enable

T1E

port

high

impedance

and

from

forces

- When cleared,

issuing

the

T2E

interrupt

port B

I/O lines

Counter/timer
1
enable
inhibits
counter/timer 1
interrupt
request,
and

Counter/timer

inhibits

request,

into a

state.

the
Counter/Timer
Register.

- When cleared,
from issuing an
clears bit 0 of

Command

enable

and

Status

- When cleared,

inhibits
counter/timer 2 from issuing an
interrupt
request,
and
<clears bit 0 of
the
Counter/Timer
2
Command and Status

T3E

Port

into

LAB

C and counter/timer 3 enable - When

cleared,
inhibits
port
C
and
counter/timer 3 from issuing an interrupt
request.
Also
clears
bit
0
of
the
Status
and
Command
3
Counter/Timer
Register, and forces the port C I/O lines

Port

port

a high

impedance

state.

1link control - When cleared,
A

and

port

allows

operate

independently.
When
set,
1links ports A
and
B
to
form
a 1l6-bit port. When the
ports are linked, only port A's Handshake
and
Command
and
Status
Registers
are
used.
Port
B is specified as a bit port

and
1its
pattern
matching capability is
disabled.
When
1linked,
port
B must be
read
or
written
before
port A. If the
ports
are to be linked, this bit must be
set

before
5-4

the ports

are

enabled.

Bits

Name

Description

PAE

Port

port

and

high

1:0

enable

- When cleared, inhibits

the

port A I/O lines into a

A from issuing an interrupt request

forces

state.

impedance

Counter/timer link control - Specifies if

counter/timers

how

and

are

linked. The counter/timers must be linked

before they are enabled.

Configuration

Counter/timers are independent

C/T 1ls output (inverted) enables

5¢62.2

C/T 2

C/T 1ls output (inverted) triggers

C/T

C/T 2

count

1ls

output (inverted) is C/T 2s

input

Port Specification Registers

operating
the
define
Registers
Specification
Port
The
of Port
types
three
are
There
B.
and
A
ports
characteristics of
Specification Registers: Mode, Handshake, and Command and Status.
Each port (A and B) has one set of these three registers.

B) -5.2.2.1 Port Mode Specification Registers (Ports A andcleare
d
are
They
5-3).
(Figure
rite
These registers are read/w
reset.

during hardware

ADDRESS: 17777100,
15

17777120
10

PTS

ITB

PI\:AS

IMO

LPM/DTE

MR-17163

Figure 5-3

Port Mode Specification Registers
(Ports A and B)

Bits

Name

Description
Not

PTS

used

Port

(read

type

ones)

select

Specifies

the

port

type.

ITB

PTS

Port

00
01
10
11

Bit port (no handshake)
Input port with handshake
Output port with handshake
Reserved

Interrupt

the

Interrupt

Type

two

Dbytes

Pending

When

(IP)

bit

cleared,

for this
port
(bit
5
of
the
Port
Command and
Status
Register) 1is set when one byte of
data is available for transfer. When this
bit
1is
set, IP is set when two bytes of
data
are
available for transfer. For an
input port, IP is set when the Input Data
Register
1is full. For an output port, IP
is
set
when the Output Data Register is
empty. This bit must be cleared for ports
specified
as bit ports, single- buffered
ports, or bidirectional ports.
SB

Single
buffered
mode
When
cleared,
specifies
that
this
port
1is
doublebuffered.
When
set, specifies that this
port
1is
single-buffered.
This
bit
1is
always cleared for bit ports.

IMO

Interrupt

interrupt

1is

match

only - When set, an
generated
when data moved

into
the
Input
Data Register or out of
the
Output
Data
Register
matches
the
pattern specification.

PMS

Pattern
mode specification - Defines
operation of the pattern match logic.

PMS
00
01
10
11

the

Pattern Mode
Disable pattern matching
AND mode
OR mode
OR-priority encoded vector mode

Bits

Name

Description

LPM/DTE

Latch

match (LPM) or deskew

pattern

a dual
1s
This
(DTE)
enable
timer
bit. The LPM function is active
function
the port is used as a bit port. The
when

1is active when the port is
function
DTE
with
port
output
an
as
specified

1logic. If LPM is set, the port
handshake
data when a pattern match
input
latches
If LPM is cleared, pattern
detected.
is
but the data read
detected
are
matches

the port is the current (unlatched)
from
value. If DTE is set, the deskew timer 1is
perform delay functions
can
and
active
Port
the
of
description
the
(see
that.
Register
Specification
Handshake
1is
DTE
When
section).
this
follows
cleared, the deskew timer is not active.

5.2.2.2 Port Handshake Specification Registers (Ports A and B) -The Port Handshake Specification Registers (Figure 5-4) determine
A Port Handshake
parameters of a handshake operation.
the
as a bit
configured
is
port
a
if
ignored
is
Register
on
Specificati
1s
These registers are cleared during reset. Access
port.,
read/write.

ADDRESS: 17777102, 17777122
1%

T N TN A T

I OI

HST

:RWSi

:DTSB:

MR-17164

Port Handshake Specification Registers

Figure 5-4
Bits

Name

Description

Not used (read as ones)

15:8

7:6

(Ports A and B)

HST

Handshake

type

Specify

the

handshake operation performed.

HST
00
01
10
11

type of

Handshake Type
Interlocked
Strobed
Pulsed
3-Wire

pulsed and 3-wire handshake must not
The
ports.
bidirectional
for
specified
be
the
use
can
time
a
at
port
one
Only
the
uses
port
one
If
handshake.
pulsed
handshake, the other port must be
3-wire
a bit port.

5-7

Bits

Name

Description

5:3

RWS

Request/Wait
Defines
how
this
port
implements the request function. The wait
function

not

1implemented

the

KXJ11-CA.

RWS
000

Request
Request

Function
disabled

001
010
011
100
101
110

Reserved
Reserved
Reserved
Output request
Reserved

111

Input

Special

request

Only port A can participate in a request.
Port B must be programmed as a bit port.

2:0

DTSB

Deskew

time

specification - Defines the

minimum
number
of
PIO
clock cycles of
delay between the time a new byte of data
is
output,
and
the
time the handshake

mechanism
indicates
that
new
data
1is
available.
The PIO clock has a period of
ns. A deskew time of zero is defined
250
DTE to zero in the Port Mode
setting
by
Specification Register.

5.2.2.3
Figure

Port

5-5.

DTSB
000

Deskew Clock Cycles
2

001
010
011
100

4
6
8
10

101

110

111

Command and Status Registers

(Ports A and B)

-- See

ADDRESS: 17777020, 17777022
15

(09

IUS

ORE

ERR

PMF

IRF

IOE
MR-17165

Figure 5-5

Port Command and Status Registers
(Ports A and B)

5-8

Name

Descriptibn
Not used

Bits

I1US

(read as ones)

acknowledge

enable

Interrupt

pending

Bits

000

- When set,

indicates

reset.

and IP are written according to

1IE,

following
<7:5>

command codes.

Command

(no effect)

Null

001

Clear

010

Set

011

Clear

100

Set

IP and

IUS

101

Clear

110

Set

111

Clear

Interrupt

error - This bit is meaningful

1IE

if this port has been configured as
only
a bit port, and pattern matching has been
a
that
1indicates
set,
When
enabled.
match occurred before a previous
pattern
could be acknowledged. This bit 1is
match
read-only (writes to it are ignored), and
is

ORE

cleared, this

port requires service because
this
that
handshake
a
match,
pattern
a
of
When cleared,
error.
an
or
operation,
that the port does not require
indicates
1is read/write and is
bit
This
service.

the

When

Interrupt

1US,

ERR

Interrupt

an
requesting
from
prevented
1is
port
an interrupt
in
engaging
or
interrupt
these
set,
When
sequence.
acknowledge
1is
bit
The
enabled.
are
interrupts
read/write and is cleared during reset.

cleared during

sequence.

reset,

cleared during

set,

the same level or lower are
at
bit is read/write and is
This

requests
disabled.

When

indicates that this port is engaged in an
interrupt

service

under

Interrupt

cleared

during

Output

reset.

empty

When

set,

Output

Data

that this output port's Output
indicates
empty. Can be cleared
is
Register
Data
only

writing

the

bit is read-only (writes
This
Register.
is set during
and
1ignored)
are
it
to
reset.

Bits

Name

IRF

Description

Input register full - When set,

that
this
Register
1is

indicates

input
port's
Input
Data
full. Can be cleared only by

reading the Input Data Register. This bit
is
read-only (writes to it are ignored),
and is cleared upon reset.

PMF

Pattern

match

flag - When set,

this bit

error

bit

set indicates the occurrence of a pattern
match,
if pattern matching is enable for
this
port. This bit is read-only (writes
to
1t
are ignored), and is cleared upon
reset.

IO0E

Interrupt

This

1is

meaningful
only
for
bit
ports
with
pattern
matching
enabled. When cleared,
this bit prevents an interrupt from being
issued by this port if an error occurs 1in
pattern
matching.
When
set,
this
bit
allows
these
interrupts.
The
bit
1is
ignored
by
ports
with
handshake
and
should
be
cleared
for these ports. The
bit is read/write.

5.2.3

Bit Path Definition Registers

5.2.3.1

Data
Path
Polarity Registers -- The Data Path Polarity
(Figure
5-6) define
whether
the
bits in a port are
or
non-inverting.
These
registers are cleared during

Each
port
(A,
B,
and
C)
has
one
set of Bit Path Definition
Registers.
They
include
the Data Path Polarity, Data Direction,
and Special I/O Control Registers. Only the four least significant
bits of the registers are valid for the Port C registers.

Registers
inverting
reset.

Access

read/write.

ADDRESS: 17777104, 17777124,17777012

’

]

POLARITY

]

MR-17212

Figure 5-6

Data Path Polarity Registers
(Ports

and

Description

Name

Bits

Not used (read as ones)

15:8

Data path polarity - If a bit is set, the

DPP

7:0

path for this port 1is
bit
corresponding
a bit is
If
LOW).
(asserted
inverting
corresponding bit path for
the
cleared,
(asserted
non-inverting
1is
port
this
.
HIGH)

5.2.3.2 Data Direction Registers -- The Data Direction Registers
define the data direction of each bit in a port.
(Figure 5-7)
These registers are ignored by ports with handshake logic and are
cleared upon reset. Access is read/write.

ADDRESS: 17777106, 17777126, 17777014

l1l1]1|1l1|1l1|1|

DIRECTION
)

]

MR-17183

Data Direction Registers

Figure 5-7

and C)

Description

Name

Bits

(Ports A,

Not used (read as ones)

15:8

direction

Data

7:0

a bit is set, the

1is
port
this
of
bit
corresponding
is
bit
a
input bit. If
an
as
specified
this
of
bit
corresponding
the
cleared,
port is defined as an output bit.

Control Registers -- The Special 1I/O
I/0
52.3.3 Special
Registers (Figure 5-8) allow special characteristics to Dbe defined
for a port's data path. These registers are cleared during reset.

Access

1is

read/write.

ADDRESS: 17777130, 17777110, 17777016

111

05 -04

I/OL
l| " SPECIAL
I
1

|
MR-17184

Figure 5-8

Special I/0 Registers
(Ports A,

and C)

Bits

Name

Description

15:8

Not

7:0

SIO

used

(read

ones)

Special
input/output
- If a bit is set,
the
corresponding
bit
of
this port is
specified
as
a 1l's catcher for input. A
1's
catcher
functions
by automatically
latching
a 1 if the input goes to 1. The
1's
catcher is cleared only by writing a
zero to the Input Data Register.

5.2.4

Pattern Definition Registers

The
Pattern
Definition
Registers (Figures 5-9 through 5-11) are
used
collectively to specify a match pattern for each bit in Port
A
or
Port
B.
The
pattern
specification
for
any
bit (x) 1is
summarized in Table 5-2. These registers are cleared during reset.
Access

1is

read/write.

Table 5-2

Pattern Specifications

PPRx

PTRx

PMRXx

Bit x Match Condition

0
0
0
0

0
0
1
1

0
1
0
1

Bit masked off
Bit masked off
Any transition
Any transition

1
1

0
0

0
1

Zero
One

1
1

0
1

One to zero
7ero to one

5.2.4.1

Pattern Polarity Registers

transition
transition

(PPR)

—-- See Figure 5-9.

ADDRESS: 17777112, 17777132
15

Figure 5-9

O05

Pattern Polarity Registers
(Ports A and

5.2.4.2

Pattern Transition Registers (PTR) -- See Figure 5-10.
ADDRESS: 17777114, 17777134

PIATTE'RN TIRAN5‘;|TIOIEJ
|I

MR-17188

Pattern Transition Registers

Figure 5-10

5.2.4.3

(Ports A and B)

Pattern Mask Registers (PMR) -- See Figure 5-11.
ADDRESS: 17777116, 17777136

]

l|
]] PAWTERI{I| MA!SK
|

O1
]

MR-17213

Pattern Mask Registers

Figure 5-11

502.5

(Ports A and B)

Port Data Registers

are used to hold data that is read from or
Port Data registers
Port Data Register format for ports A and
The
written to the PIO.

B is shown in Figure 5-12. The format for the Port C Data Register
is shown in Figure 5-13. These registers are read/write and are
unaffected

reset.

ADDRESS: 17777032, 17777034

15 14 13

12 11 10 69 08 07 06 05 04 03 j 02 01 | 00

Fonfomm
]
]
]

oo [o [P [t ]

]

MR-17214

Port Data Registers

Figure 5-12

(Ports A and B)

ADDRESS: 17777036

1 ) 1

PCEN
L1

Il PCl |'
I

MR-17215

Figure 5-13

Port C Data Register

Bits

Name

Description

15:8

Not used

7:4

PCEN

3:0

(read

as ones)

Port
C
bit
enable
used
as
a
write-protect
bit mask for bits <3:0>. A
set
bit
in PCEN inhibits the writing of
the
corresponding
bit
in bits <3:0>. A
cleared
bit
in PCEN enables the writing
of the corresponding bit in bits <3:0>.

Port

data -

contains the

four bits of

data
to be read by or written to Port C.
Subject to masking according to the value
of

PCEN.

5.2.6
PIO Counter/Timer Control Registers
There
are three PIO counter/timers numbered 1, 2, and 3. Each PIO
counter/timer
has a set of six control registers that specify the
operation
that
the
counter/timer
performs.
The
registers are
described

the

paragraphs

that

follow.

5.2.6.1
PIO
Counter/Timer
Mode
Specification
=
Each
counter/timer
has
a
Mode
Specification Register (Figure 5-14).
These
registers
define
an operational mode for a counter/timer,
and specify which external control and status lines are used. They
are cleared during reset. Access is read/write.

ADDRESS: 17777070, 17777072,17777074

DSF

EGE

ECE

C/sC
EOE

ETE

REB
MR-17166

Figure 5-14

Bits

Name

15:8
7

Counter/Timer Mode Specification
(Counter/Timers 1, 2, and 3)

Description

Not
C/SC

used

(read as

ones)

Continuous/single
cycle
- When set, the
time
constant
value
initially
used 1is
reloaded,
and
the countdown sequence 1is
repeated
when
the counter reaches zero.
When
cleared,
the countdown sequence 1is
terminated when the counter reaches zero.

Bits

Name

Description

EOE

External
output
enable
- When set, the
output
of
the counter/timer is provided
on
the
I/0
1line
associated
with that
particular counter/timer (see Table 5-3).
This

bit must

be programmed

an output

bit in the Data Direction Register of its
port.
When
cleared,
external access to
the counter/timer 1is disabled.
5

ECE

External count enable - When set, the I/0O
line
of
the
port
associated
with the
counter/timer

1is

corresponding

bit

input

counter

When

input.

wused

Table

(see

external

5-3).

The

must be programmed as

cleared,

external access

disabled.
4

ETE

External

is
EGE

the

corresponding bit must be programmed
When cleared, external access
input.

The
as

enable - When set,

trigger

1line of the port associated with the
I/0
1is used as a trigger input
counter/timer
bit to the counter/timer (see Table 5-3).

disabled.

External
gate enable - When set, the I/0
line associated with the counter/timer is
the
to
gate
external
an
as
used
This
5-3).
Table
(see
counter/timer

1line to suspend or
external
the
allows
progress by
1in
countdown
the
continue
toggling the line. When cleared, external
access

REB

disabled.

Retrigger enable bit - When set,
that

occur

a
cause
cleared,

during

External
following

DSC

the
to
access
I/0 lines (Tabl

begin. When
to
occur
during a

countdown
new
triggers
that

countdown sequence are

1:0

triggers

a countdown sequence

ignored.

Output duty cyéle select DSC
00
01

Output Duty Cycle
Pulse output
One-shot output

10
11

Square wave
Reserved

counter/timers

output

1is provided through the

Counter/Timer External Access

Table 5-3

Function

C/T 1

Counter/Timer Output
Counter Input
Trigger Input
Gate Output

Port
Port
Port
Port

C/T 3

C/T 2
B
B
B
B

C
C
C
C

Port
Port
Port
Port

0
1
2
3

B
B
B
B

Port
Port
Port
Port

4
5
6
7

O
1
2
3

-- . Each
Status
and
Command
Counter/Timer
PIO
5.2.6.2
counter/timer has a Command and Status Register (Figure 5-15) that
to control and monitor timer operation. These registers
used
is
are

cleared

during

reset.

ADDRESS: 17777024, 17777026, 17777030
15

o08

OO0

RCC TCB l

ERR

GCB

CIP
MR-17167

Figure 5-15

Bits

Name

Description

Not used

15:8
7

Counter/Timer Command and Status
(Counter/Timers 1, 2, and 3)

IUS

(read as ones)

Interrupt

indicates
engaged

service

When

set,

1is
counter/timer
this
that
acknowledge
1interrupt
an
in

sequence.

level

under

Interrupt

requests

or lower are disabled.

the same

This bit

read/write.
6

Interrupt

enable

When

cleared,

this

from
prevented
is
counter/timer
requesting an interrupt or engaging in an
interrupt acknowledge sequence. When set,

the

interrupts

read/write.

5-16

are

enabled.

The bit

Bits

Name

Description

Interrupt
pending
- When set, indicates
that this counter/timer requires service.
The
bit
1is automatically set
each time
the
counter/timer
reaches
1its terminal
cleared, indicates that the
When
count.
counter/timer
does
not require service.
This bit is read/write.

IUS,

the

IE,

<7:5>

Bits

000

ERR

GCB

TCB

(no effect)

Clear

010

Set

011

Clear

100

Set

IP and

1IUS

IUS

1US

101

Clear

110

Set

111

Clear

1IP

1IE

set, indicates
When
error
Interrupt
a
reached
has
counter/timer
the
that
previous
the
before
count
terminal
been serviced. This
has
count
terminal
is

Read

read-only.

counter

control - When

set,

causes

the contents of the Counter/Timer Current
normally follows
(which
Register
Count
down counter) to be frozen until the
the
least significant byte of the register is
bit cannot be set unless the
This
read.
1in the Master
enabled
1is
counter/timer
Configuration Control Register.
- When set, starts or
bit
command
‘Gate
When
sequence.
countdown
the
resumes
countdown sequence.
the
halts
cleared,
This bit is read/write.

the
set,
When
bit
time
the
with
loaded
value, and a countdown sequence
constant
initiated. This bit is write-only and
is

command
Trigger
1s
down-counter

is
CIP

Command

Null

001

bit
RCC

and IP are written according to

following command codes.

always

read

zero.

progress - When set, indicates
1in
Count
that a countdown sequence is in progress.
the
when
set
automatically
is
It
time
with the
loaded
1is
down-counter
automatically
1is
It
value.
constant
reaches
down-counter
the
when
cleared
zero.

This bit

5-17

read-only.

PIO Counter/Timer Time Constant -- Each counter/timer has
5.2.6.3
a
register
that
contains
a
time constant value. This value 1is
loaded
into the down-counter of a counter/timer when a trigger is
detected.
Each
register
1is
16 bits wide and is accessed as
consecutive
bytes
(bit
7
of
the
MSB
1is
bit
15
of the
Register). Refer to Figure 5-16
Constant
Time
Counter/Timer
the
register
format.
These
registers
are
read/write
and
unaffected

5.2.6.4

reset.

two
PIO
for
are

PIO Counter/Timer Current Count -- Each counter/timer has

a
Current Count Register (Figure 5-17). This register follows the
contents of the appropriate down-counter until a 1 is written into
the RCC bit of the Status/Control Register. When this happens, the
contents
of the Current Count Register are frozen until the least

Then the register
read.
1is
register
the
of
byte
significant
The countdown
again.
down-counter
the
of
contents
the
follows
wide and 1is
bits
16
is
register
Each
affected.
not
1is
sequence
bit 15 of
is
MSB
the
of
7
(bit
bytes
two consecutive
as
accessed

Current
the
to
Register
Register are

reset forces the Current Count
A
Register).
Count
Writes to the Current Count
down-counter.
follow the

ignored.

ADDRESS: 17777054, 17777060, 17777064 — MOST SIGNIFICANT BYTE
ADDRESS: 17777056, 17777062, 17777066 — LEAST SIGNIFICANT BYTE
1%

F|1I1I1|1I1l1|1|

MSB OR LSB

MR-17168

Counter/Timer Time Constant

Figure 5-16

(Counter/Timers 1,

and 3)

ADDRESS: 17777040, 17777044, 17777050 — MOST SIGNIFICANT BYTE
ADDRESS: 17777042, 17777046, 17777052 —~ LEAST SIGNIFICANT BYTE
15

05
!

)

]

MSB OR LSB
1

|
MR-17169

Figure 5-17

Counter/Timer Current Count
(Counter/Timers 1, 2, and 3)

5.2.7

Interrupt Related Registers

service

in a polled environment.

Interrupt related registers are registers used in the handling of
PIO interrupts. Three of these are vector registers: one for Port
A, one for Port B, and one shared by the three counter/timers.
Another register is provided to indicate which devices need
Register =-- The Interrupt Vector
Vector
Interrupt
5.2.7.1
Register holds the vector used during an interrupt acknowledge
The native firmware initializes the vector for Port A
operation.
(octal), the vector for Port B at 204, and the vector for
at 200
the counter/timers at 210. If the MIE bit of the Master Interrupt
and 3 of the vector are
bits 1, 2,
is set,
Control Register
affected

shown.

Ports A and B

OR-Priority Encoded Vector Mode:

Bit 3
X

Encodes the number of the highest
priority bit with a match.

Bit 1
X

Bit 2
X

All other modes (see Port Command and Status Register
description):

Bit 3

ORE
0

Bit 1

Bit 2

No error
Error

PMF
0

IRF
0

Counter/Timers
Bit

0
0
1

Bit

0
1
0

Counter/timer 3
Counter/timer 2
Counter/timer 1
Error

This register is read/write and is unaffected by a reset. The
format of the Interrupt Vector Register is shown in Figure 5-18.
ADDRESS: 17777004, 17777006, 17777010
14

07
N

06
N

05 04
N

' VEIC
B

'
M

MR-17170

Figure 5-18

Interrupt Vector Register

5-19

5.2.7.2
Current Vector Register -- The Current Vector Register is
a
read-only register. When read, it returns the vector that would
have
been
returned during an interrupt acknowledge cycle, if the
device
had
been assigned the highest priority interrupt pending.
The order of priority (highest to lowest) is counter/timer 3, Port
A,
counter/timer
2,
Port
B,
counter/timer
1.
If
no enabled
interrupts
are pending, or if the PIO is reset, the register will
contain

pattern

all

1's.

This

1is

the Current Vector Register

wuseful

1in

a polled

environment.

The format of

shown

in Figure

5-19.

ADDRESS: 17777076

Figure

O T

A A

IS I

5-19

IV.EC

[

OC
0

Current Vector Register

5.2.8
I/0 Buffer Control Register
The
PIO
is
protected
from
the
connector by a set of IEEE 488
compatible
buffers.
The buffers are controlled by the I/O Buffer
Control
Register
(Figure
5-20). The register allows the user to
configure
ports
as
inputs or outputs. Also, port driver buffers
can
be
configured to operate in open collector or active pull-up
mode.
This register is cleared during reset. This is a write-only
register.

ADDRESS: 17777140
1

PClTT
PABTT

INSLAL
]

]

PAHN

T
|

]

T
|

T T
1

1
|

DIR

PALN
DIR

Figure

5-20

I/0 Buffer Control Register

Bits

Name

Description

PCTT

Port
C
configures
pull-up
drivers

PABTT

buffer
control
When
set,
the
Port C drivers as active

drivers. When cleared, the Port
are open collector drivers.

Ports
A and B buffer control - When set,
configures
the
port
A and B drivers as
active pull-up drivers. When cleared, the
port
A
and B drivers are open collector
drivers.

5-20

Bits

Name

Description

13:10

PC DIR

Port

C bit

is a receiver.

Port

direction - If a bit is set, the

Port C bit is a driver. If
corresponding
bit is cleared, the corresponding Port
a

PAHN DIR

high

nibble

direction

When

the Port A high nibble bits <7:4>
clear,
receivers. When set, the Port A high
are
nibble bits are drivers.

PALN DIR

Port A low nibble direction - When clear,

bits <3:0> are
nibble
1low
A
Port
the
low
A
Port
the
set,
When
receivers.
nibble bits are drivers.

7:0

5.3

PB DIR

direction - If a bit is set, the

Port

B bit

is a

Port B bit is a driver. If
corresponding
bit is cleared, the corresponding Port
a
receliver.

PROGRAMMING THE I/O PORTS

This section describes how to program the I/O ports and provide
example programs. In particular this section describes how to use
the I/0 ports as bit ports, as ports with handshake logic, 1in
and with the DMA controller. The use of the
16-bit linked mode,
pattern recognition logic will also be discussed.

5.3.1

Programming the I/O Ports as Bit Ports

a nibble

(4-bit)

Using the I/O ports as bit ports provides up to 20 lines for
control and status. Each bit in ports B and C may be independently
configured as an input or output bit. Port A must Dbe configured on
basis.

Programming the PIO as a bit port is straightforward. First, the
Port Mode Specification Register is used to select the port as a
bit port with or without pattern matching. Then, the Bit Path
used to determine the polarity,
are
Registers
Definition
istics of the bits of the port. If
character
direction, and special
the Pattern Definition Registers
enabled,
1is
pattern recognition
then a simple matter to write to
is
It
d.
must also be initialize
the correct control signals, and
provide
to
the output data buffer
to read the input data buffer to monitor status.

The following program provides an example for using the PIO in the

bit mode.

.TITLE

PIOl.MAC

s +

This program provides an example of how to program the PIO's
I/0 ports as bit ports.
This program utilizes the PIO
loopback connector (Part #H3021 or 54-16227) which makes the
following

connections:
A0
Al

---

BO
Bl

A7
co
cl

----

B7
C3
C2

After this program has been assembled and linked on the
development machine, use the KUI utility of the KXJl1l-CA
Software Toolkit to load the program into the KXJ11-CA. The
program will execute as shown in the following example.
;

SET

;

LOAD PIOl.SAV

;

EXECUTE

;

10DT

;

1001152

;
;
;
;
s
;
;
;
;
;
e

1R2/000000
11154/041101
1001156/042103
1001160/043105
1001162/177507
1001164/041101
1001166/042103
1001170/043105
1001172/000107
1001174/000000
17C

;

EXIT

A non-zero result in R2 indicates that an error has occurred.
(Try running the test without the loopback connector).
Location 1154 is the beginning of the output buffer. Location
1164 is the beginning of the input buffer.
Register Assignments
MIC
MCC
PAMODE
PAPOL
PADDIR
PASIO
PADATA

==
==
==
==
==
==
==

177000
177002
177100
177104
177106
177110
177032

PBMODE
PBPOL
PBDDIR
PBSIO
PBDATA

==
==
==
==
==

177120
177124
177126
177130
177034

IOCNTL

177140

#340

Inhibit recognition of
interrupts

MTPS

¢ ¢
START

Initialize PIO

CLRB

$#1,MIC

. Reset device and inhibit interrupt

MIC

. Enable device (interrupts still

Set-up Port A

CLRB
CLRB
CLRB

CLRB
¢

PASIO

Set-up Port B

CLRB
CLRB
MOVB

CLRB
.

PAMODE
PAPOL
PADDIR

PBSIO

requests

inhibited)

. Port A: bit port, no pattern match
. Port A bits are non-inverting
. Port A bits are output bits
+ Normal output

. Port B: bit port, no pattern match
- Port B bits are non-inverting
s+ Port B bits are input bits
.+ Normal input

Set-up the PIO buffers

#1400, IOCNTL

MOV

PBMODE
PBPOL
#377 ,PBDDIR

MOVB

;* Initialize GPRs
$#OUTBUF , RO

MOV

# INBUF ,R1
R2

MOV
CLR

Point to data to be output

s+ Point to input data buffer
s+ R2 will indicate error status

Flush input buffer

TSTB

PBDATA

Enable Ports A and B and send the data

MOVB

$#204 ,MCC

configure the PIO buffers for

A=output and B=input

Enable ports A and B

1S:

MOVB

(RO)+,PADATA

Move

NOP

data

into

out

Port

PBDATA, (R1)+

¢+

and

TSTB

(RO)

s
;

Test to
IF (RO)

BPL

;

THEN

transfer

another

byte

ELSE

check

data

wvalid

see 1f done
is positive

Compare original data with received data

MOV

#OUTBUF, RO

;

Point

output

MOV

#INBUF,R1

;

Point

input

;

Test

TSTB

(RO)

;

BMI

CMPB

(RO)+,(R1)+
28

BEQ

INC

3$:

MOVB

;

2S:

ouTBUF:

o
.BYTE

see

(RO)

data
data

buffer
buffer

done

negative

;

THEN

;

ELSE

;
;

Compare bytes
IF bytes are equal

;

THEN

test

;

ELSE

1indicate

;

Branch here

done comparing
do another compare

another

non-zero

pair

error

value

indicates

error

upon

completion

101,102,103,104,105,106,107,-1

« EVEN

INBUF:

.BLKB

« END

START

5.3.2

Programming

Ports

and

facilitate
used

the
See

provide

Table

Figure

I/O0

transferring

REQUEST line

transfer

the

may

5-4

5-21
data,

the

and

data

handshake

utilize

for

shows

Ports

with

ports

two

PIOs

with

the

can

lines

that

OUTPUT

Port

handshake

basis.

addition,

DMA controller

handshake

Handshake

byte-by-byte

lines.

description

how
the

configured

Port

transfer
C

DATA

DAV

ACKIN | <

PIO

—e | ACKIN

RFD

MPR-0286-025

Figure

5-21

PIO Handshake

Lines

may

the

is
use

data.
lines.

together

utilized.

INPUT

" PIO

handshake

connected
are

Port

5-4

Table

C Handshake Lines Port C Bits

Port A/B Configufation

Pin C3

Pin C2

Pin Cl

Pin CO

Ports A & B = Bit Ports

Bit I/O

Bit I/0

Port A = Input or Output
(Interlocked, Strobed,

RFD or DAV

ACKIN

REQUEST
or Bit I/0

Bit I/0

Port B = Input or Output

REQUEST

Bit I/0

RFD or DAV

ACKIN

Port A or B = Input Port

RFD

DAV

REQUEST

DAC

Port A or B = Output Port

DAV

DAC

REQUEST

RFD

Port A or B = Bidirectional
(Interlocked or Strobed

Not implemented on the KXJ11-CA

or Pulsed Handshake)*

or Bit I/O

(Interlocked, Strobed,

or Pulsed Handshake)*

(Output)

(3-Wire Handshake)

(Output)

(3-Wire Handshake)

(Input)

(Output)

or Bit I/O0

(Input)

or Bit I/O

Handshake)

* ports

output

and

ports

be specified at the same time as input or

may

the

with

Interlocked,

Strobed,

Pulsed

if neither port uses REQUEST. Only one port can use

Handshakes,

the Pulsed Handshake at a time.

Strobed,
Interlocked,
are
available
are
ke type
handsha
each
of
short description
A

that
handshakes
The
3-Wire.
and
Pulsed,
follows.

When

using

that

the

the Interlocked Handshake, any action by the PIO must

be acknowledged by the external device before the next action can
take place. In other words, an output port does not indicate that
it has new data available until the external device indicates that
it is ready for data. Likewise, an input port does not indicate
that it is ready for new data until the external device indicates
byte

of data is no longer available (thereby

acknowledging the input port's acceptance of the last byte).

The Strobed Handshake uses external logic to "strobe" data into or
out

port.

contrast

to the Interlocked handshake,

the

signal indicating that the port 1is ready for an other data transfer
independently of the ACKIN input. External logic must
operates

ensure that data transfers at the appropriate speed.

The

data

Handshake is used for mechanical devices that require

Pulsed

to be held for relatively long periods of time,

gated

Interlocked

out

Handshake,

order

of the device. The logic is similar to the
except

that Counter/Timer 3 is linked to

the handshake logic to add the appropriate delays to the handshake
lines.

5-25

The
3-Wire
Handshake
may
be
used
communicate
to
several
input
ports
essentially the same as the Interlocked

so
one
output
port
simultaneously.
This
Handshake, except that

can
1is
two

individual
lines are used to indicate when an input port is ready
for
data
(RFD), and when the input port has accepted data (DAC).
Because this handshake requires three lines, only one port can use
the 3-Wire Handshake at a time.

When
Ports
A and B are configured as ports with handshake logic,
they
must
also
be
configured
as
single
or
double-buffered.
Double-buffering a port allows more time for the interrupt service
routine
to
respond
to a data transfer. A second byte of data 1is
input
to
or
output
from
the port before the interrupt for the
first byte is serviced. A single-buffered port is used where it 1is
important to have byte-by-byte control over the transfer, or where
it
1is
important
to
enter the interrupt service or routine in a
fixed amount of time after the data has been accepted or output.

The

REQUEST

control

line

1line

may
the

also be used by ports with handshake.
PIO

the PIO with the DTC,
A
Data Register, and
Data Register.

signal

the

address
address

DMA

controller

This

the
port
wishes
to
transfer
data
without
CPU
intervention.
The
operation
of
the
REQUEST line depends upon the Interrupt on Two
Bytes
(ITB) bit in the Port Mode Specification Register. If ITB =
0,
then
the REQUEST line is asserted anytime a byte is available
for
transfer.
If
ITB = 1, then the REQUEST line is not asserted
until
two bytes are available for transfer. The implementation of
the
PIO
on
the KXJ11-CA requires that only one port be used for
DMA
transfers.
8Since the REQUEST line utilizes one of the Port C
bits, the other port must be programmed as a bit port. Also, bit 1
in
the Port C Polarity Register must be set to insure the correct
polarity for the REQUEST line if the DTC is used with the PIO.

When using
the
Port
the Port B

enables

17777033 must
17777035 must

be
be

that

used
used

for
for

The following examples display the capabilities of the PIO used as
a port

with

handshake.

PIO2.MAC

transfer
This program demonstrates the ability of the PIO to Interl
ocked
the
uses
am
progr
The
basis.
data on a byte-by-byte
ports
Both
B.
Port
to
A
Port
from
data
er
Handshake to transf
are configured as single-buffered. The PIO loopback connector
(part #H3022 or 54-16227) or a functional equivalent is
required to successfully run this program.

After this program has been assembled and linked on the
development machine, use the KUI utility of the KXJ11-CA
software Toolkit to load the program into the KXJ11-CA. e.
The program will execute as shown in the following exampl

QWY wme WO WO WO We WI w9 W WO WG W WO WO WO W WO W9 W6 Wo WO

weg

WEI

.TITLE

SET 2
LOAD PIO2.SAV
EXECUTE
10DT
|

1001214

11262/065151
1001264/066153
1001266/067155
1001270/070157
1001272/000377
1001274/065151
1001276/066153
1001300/067155
1001302/070157
1001304,/000000
1°C

EXIT

This verifies that the contents of the output buffer r(location
1262 were successfully transferred to the input buffe
(location 1274).

MIC
MCC

==
==

177000
177002

PAVEC
PASTAT
PADATA
PAMODE
PAHDSH
PAPOL
PASIO

==
==
==
==
==
==
==

177004
177020
177032
177100
177102
177104
177110

PBVEC

PBSTAT

177006
177022

PBDATA

177034

PBMODE

177120

PBHDSH

177122

PBPOL

177124

PBSIO

177130

PCPOL

177012

PCDDIR

177014

IOCNTL

177140

START
¢ ¢

MTPS

#340

MOVB

#1,MIC

CLRB

MIC

Inhibit

recognition

device

and

interrupts

Reset

;

requests

s
e

Enable device
inhibited)

(interrupts

from

inhibit

the

interrupt

PIO

still

MOVB

#200,PAVEC

MOV

#OUT ,@#200

;

Set

interrupt

vector

MOV

#340,Q@#202

...

and PSW

MOVB
MOV
MOV

#204 , PBVEC

s
*

Set
...,

up Port B
and PSW

interrupt

|
vector

; Set-up Port A
MOVB
#220, PAMODE

;

Port

CLRB
CLRB
CLRB

PAHDSH
PAPOL
PASIO

s
¢+
s
s

A: Output Port,
single-buffered
Use interlock handshake
Port A bits are non-inverting
Normal output

MOVB

#300,PASTAT

Enable

#120, PBMODE

;

Port

CLRB
CLRB

PBHDSH
PBPOL

+
;
;

single-buffered
Use interlock handshake
Port B bits are non-inverting

CLRB
MOVB

PBSIO
#300,PBSTAT

s
s

Normal
Enable

;

#IN,Q#204
#340,Q@4#206

Set—-up

MOVB

Port

interrupts

Input

input
Port B

; Set-up the Port C handshake lines.
s
All handshake lines are configured
;
1f they are not inputs!
MOVB
#377 ,PCDDIR
s Port C bits
; Set—-up the PIO buffers
MOV
#165400,I0OCNTL
;

C configure

B=input,

Port,

interrupts

inputs,

are

inputs

even

the PIO buffers for A=out
CO0,C2=input, Cl,C3=output

%)
O

Start the first transfer

MOVB

#200,PASTAT

)

(RO)
1$

MOVB

(RO)+,PADATA

BR
MOVB
MOVB

28
#240,PASTAT
#140,PASTAT

1S:
2S

TSTB
BMI

¢
OUT:

+ Enable Interrupts
$#224 ,MCC
MOVB
#200,MIC
MOVB
#0
MTPS

RO
#OUTBUF,
# INBUF,R1

MOV
MOV

Set-up data areas

Point to -Output Buffer
Point to Input Buffer

Enable ports A,
Enable

and C

MIC

Enable recognition of interrupts

Set IP to initiate a transfer
Wait here for the interrupts
IF (RO) are negative
THEN transfers are complete
ELSE transfer another byte
Move byte to the Port A output data
register

Clear IP when done
Clear IUS on each pass

¢
IN:

PBDATA, (R1)+

MOVB

#140,PBSTAT

MOVB

RTI

Move byte from Port B input data
register

Clear IUS on each pass

RTI

OUTBUF: .BYTE

« EVEN

INBUF:

151,152,153,154,155,156,157,160,—1

.BLKB

« END

START

PIO3.MAC

This program is basically the same as PIO2.MAC with the
exception of double-buffered ports in this program. The
PIO loopback connector (part #H3022 or 54-16227) or a
functional equivalent is required to successfully run this
program. After this program has been assembled and linked on
the development machine, use the KUI utility of the KXJ11-CA
Software Toolkit to load the program into the KXJ11-CA.
The program will execute as shown in the following example.

W
WO
WO

EXECUTE

10DT

PIO3.SAV

11272/065151
1001274/066153
1001276/067155
1001300/070157
1001302/000377
1001304/065151
1001306/066153
1001310/067155
1001312/070157
1001314/000000
1°C
EXIT

WO
WO

1001214

SET

LOAD

.TITLE

This verifies that the contents of the output buffer (location
1272) were successfully transferred to the input buffer
(location

1304).

MIC
MCC

==
==

177000
177002

PAVEC

177004

PASTAT
PADATA
PAMODE
PAHDSH
PAPOL
PASIO

==
==
==
==
==
==

177020
177032
177100
177102
177104
177110

PBVEC
PBSTAT

==
==

177006
177022

177034
177120
177122
177124
177130

PBDATA
PBMODE
PBHDSH

PBPOL
PBSIO

PCDDIR

177012
177014

TIOCNTL

177140

PCPOL

#340

MOVB

#1,MIC

CLRB

MIC

MOVB

#200, PAVEC

Inhibit recognition of interrupts
Reset device and inhibit interrupt
requests

MTPS

¢¢
START

WO
w0

MOVB

#204,PBVEC

MOV

#IN,@#204
#340,@%206

MOV

#340,@#202

Set-up Port A
#240, PAMODE
MOVB

Port A:

PAHDSH

CLRB
CLRB

PAPOL

PASIO

#300,PASTAT

CLRB

Set-up Port B
#140, PBMODE
MOVB
CLRB
CLRB

PBHDSH

PBPOL

CLRB

PBSIO

Output

Port,

double-buffered
Use interlock handshake

Port A bits are non-inverting

Normal

output

Enable Port A interrupts

Port B: Input Port, double-buffered

Use interlock handshake

Port B bits are non-inverting
Normal

input

Enable Port B interrupts

All handshake lines are configured as inputs - even
if they are not

OVB

PSW

Set-up the Port C handshake lines.
inputs!

#377 ,PCDDIR

Set-up the PIO buffers
#165400,I0CNTL

wgy

MOV

g W W) WO

MOVB

#300,PBSTAT

and

...

MOVB

Set up Port B interrupt vector

wng

MOV

Set up Port A interrupt vector

#0UT,@#200

(interrupts still

inhibited)

MOV

from the PIO

Enable device

Set-up data areas
, RO
#OUTBUF
MOV
,R1
# INBUF
MOV

Port C bits are inputs

configure the PIO buffers for A=out
B=input, C0,C2=input, Cl,C3=output
Point to Output Buffer
Point to Input Buffer

;

Enable

Interrupts

MOVB

#224 ,MCC

Enable

ports

MOVB

#200,MIC

Enable

MIC

MTPS

’

Enable

recognition

¢+

Start

the

first

and

C
interrupts

transfer

MOVB

#200,PASTAT

Set

Wait

TSTB

(RO)

;

BMI

;

THEN

transfers

ELSE

transfer

another

Move

lst

the

Port

output

the

Port

buffer

here

initiate

for

the

transfer

interrupts

OUT:
:

MOVB

(RO)+,PADATA

(RO)

are

negative

byte

are

complete

byte

data. register

MOVB

(RO)+,PADATA

Move

2nd

byte

1$:
2S

BR
MOVB
MOVB

2S
#240, PASTAT
#140,PASTAT

H
H

Clear
Clear

PBDATA, (R1)+

’

Move

IP when done
IUS on each pass

RTI
IN¢::

MOVB

data

MOVB

PBDATA, (R1)+

;

Move

MOVB

#140,PBSTAT

Clear

RTI

OUTBUF
:
. EVEN

INBUF
:

.BLKB

.END

START

lst byte
register

2nd
register

IUS

byte

from Port

input

from

buffer

Port

each pass

PIO41I.MAC

Be WP WO WO WO wme WO W VO W O % W W WY WO WO WY WY WO W WO We WO Ry W) WO WG WO WY WO WO VWO W WO = %y O

.TITLE

is a more practical example - one KXJ11-CA
The following
to another. Two programs follow: one
data
ring
transfer
Port B using the double-buffered mode
through
data
accepts
program sends data out of Port A
second
the
(PIO4I.MAC);
In order to
mode (PIO40.MAC).
buffered
double
using the
must be connected
KXJ11-CA
the
,
programs
these
run
ully
successf

by a "straight-thru" ribbon cable that is given a half twist.
In other words, it should make the same connections that the
PIO loopback connector does.

Each program should be assembled and linked separately on the
development machine. Then use the KUI utility of the KXJ11-CA
Software Toolkit to load the programs into the KXJ11-CA.
The program will execute as shown in the following example.
SET 3
LOAD PIO4I.SAV
EXECUTE

SET 2
LOAD PIO40.SAV
EXECUTE

SET

| ODT
]

1001130

11152/065151
1001154/066153
1001156/067155
1001160/070157
1001162,/000000
1~C

EXIT

This verifies that the data was successfully transferred to
the input buffer of KXJ11-CA #3.

—-_----—_0-—-—‘—~-—~--——

-—--—-_fi-‘—-_.———-‘—--——-———--—-u——-_-1‘_-_--.—

MIC
MCC

==
==

177000
177002

PBVEC
PBSTAT
PBDATA
PBMODE
PBHDSH

==
==
==
==
==

177006
177022
177034
177120
177122

PBPOL

PBDDIR

177124
177126

PBSIO

177130

PCDDIR

177014

IOCNTL

177140

START¢

MTPS

#340

Inhibit

MOVB

#1,MIC

;

Reset

recognition

;

requests

;
¢

Enable device
inhibited)

(interrupts

interrupt

device

and

from

interrupts

inhibit

the

interrupt

PIO

CLRB

MIC

MOVB
MOV

#204 ,PBVEC
#IN,Q#204

Set

MOV

#340,Q@#206

...

and PSW

MOVB

#140 ,PBMODE
PBHDSH
PBPOL
PBSIO
#300,PBSTAT

;
+
;
;
;

Port

CLRB
CLR
CLR
MOVB
MOVB

#377,PCDDIR

;

Port

MOV

#165400,IOCNTL

;
;

configure the PIO buffers for A=out
B=input, CO0,C2=input, Cl,C3=output

MOV

# INBUF,R1

Point

Port

still

vector

B: Input Port, double-buffered
Use interlock handshake
Port B bits are non-inverting
Normal input
Enable Port B interrupts

bits

are

input
B

inputs

data
and

buffer

MOVB

#220,MCC

;

Enable

ports

MOVB

#200,MIC

Enable

MIC

MTPS
BR

#0
.

:
;

Enable recognition of interrupts
Wait here for the interrupts

MOVB

PBDATA, (R1)+

MOVB

PBDATA,(R1)+

MOVB

#140, PBSTAT

;s
;
:
;s
s

Move lst byte from Port
data register
Move 2nd byte from Port
register
Clear IUS on each pass

IN::

RTI

INBUF :

« BLKB

« END

START

input

buffer

PI0O40.MAC

.TITLE

MIC
MCC

PASTAT
PADATA

PAMODE
PAHDSH
PAPOL

PADDIR
PASIO

PCDDIR

177012
177014

IOCNTL

177140

PCPOL

: ¢
START
MTPS

#340

#1,MIC

CLRB

MIC

MOVB

#200,PAVEC

#340,@#202

MOVB

#240 ,PAMODE

CLRB

PAHDSH

CLR

PAPOL

CLR

PASIO

MOVB

#300, PASTAT

MOVB

#377,PCDDIR

MOV

#165400,I0CNTL

MOV

#OUTBUF ,RO

MOVB

#24 ,MCC

MOVB

#200,MIC

MTPS

WO
WO

#200, PASTAT

MOVB

LY]

)

MOV

$0UT,@%200

MOV

MOVB

177004
177020
177032
177100
177102
177104
177106
177110

PAVEC

Inhibit recognition of interrupts
Reset device and inhibit interrupt

requests

from the PIO

Enable device (interrupts still
inhibited)

Set up Port A interrupt vector
oo

and

PSW

Port A: Output Port,
double-buffered

Use interlock handshake

Port A bits are non-inverting

Normal

output

Enable Port A interrupts

Port C bits are

inputs

configure the PIO buffers for A=out
B=input, CO0,C2=input, Cl,C3=output
Point to output data buffer

Enable ports A
Enable

MIC

and C

Enable recognition of interrupts
Set IP to initiate a transfer
Wait here for the interrupts

(RO)+,PADATA

23
$240,PASTAT
#140,PASTAT

all

ELSE

do another transfer
lst byte to the Port
register

1$:

2S¢

MOVB
MOVB

(RO)

Move

data
Move

MOVB

(RO)+,PADATA

THEN

MOVB

(RO)

BMI

TSTB

OUTz:
¢

2nd
register

Clear
Clear

are

negative

data

byte

has

been

the

output

Port A

buffer

IP when done
IUS on each pass

RTI

OUTBUF:¢
+BYTE

151,152,153,154,155,156,157,160,-1

« END

START

transferred

W wp WO WO WO WO WO WO WO WO We WO WO wWo WO @ WY WO WO WE WY WO WO WO WO WO WI W WO W =9 @ WE WO WP WO WO WO WO WO WO wWe WO WO W6 wWe WO @

The following two programs demonstrate how the DTC may be used
DTC
to transfer data from the PIO to KXJ11-CA local memory.
PIO.
the
of
A
Port
transfers may only be accomplished using
It is not possible to properly connect two PIOs with a ribbon
cable, because the handshake lines will not align correctly
when connecting Port A to Port A. Therefore, it is necessary to
build a cable that makes the following connections.
Output Port A
Input Port A
AQ
{mmmmm——— >
A0
Al
{mmmmmm—— >
Al
A7

{emmmm——— >

C2
C3

{mmmmmm—- >
{mmmmm——— >

C3
C2

It is also necessary to place a jumper between posts M48 and
M49 so that the REQUEST line from the PIO may signal the DTC.
For more information about programming the DTC, please refer to
Section 4.3.

After each program has been assembled and linked on the
development machine, use the KUI utility of the KXJ11-CA
Software Toolkit to load the programs into a KXJ11-CA.
The program will execute as shown in the following example.
SET 3
LOAD PIOS5I.SAV
EXECUTE

SET 2
LOAD PIO50.SAV
EXECUTE

SET

1ODT
!

1001140

11140/000777
1001142/065151
1001144/066153
1001146/067155
1001150/070157
1001152/001602
1°C

'Examining the contents of the input buffer (location 1142)
verifies that the data was successfully transferred.

PIO5I.MAC

« TITLE

This

;

memory

transfers

utilizing

data

the

from Port

A of

the

PIO

local

DTC

CMDREG

| I
| B

174470

MMREG

174454

(I TR
|R | I

’

program

174444

MIC

177000

MCC

177002

PAVEC

174440

177004

[N | B

CASTF1
CAOF1

177020

PASTAT

PASIO

PAPOL
PADDIR

177100
177102
177104

PAHDSH

177032

177106

PAMOCDE

| O

PADATA

177110

PCPOL

177012

PCDDIR

177014

IOCNTL

177140

STAR:T
:
MTPS

for more
Load

CLRB

CMDREG

Reset

MOV
MOV
MOVB

#0,CASTF1
#RELOAD,CAOF1
#155,MMREG

MOVB

#241 ,CMDREG

CLRB

MIC

WO
TM0

PIO

Master Mode
the

DTC

Reg

Disable

DTC

.oad the CH1 Register SEG/TAG
Load the CH1 Register Offset
Load Master Mode Reg to
Start Chain Channel 1

the

#1,MIC

interrupts

information on the

Reset

Initialize

requests

MOVB

recognition of

4.3.

to Section
#154 ,MMREG

DTC -

refer
4
MOVB

Initialize the

Inhibit

#340

device
from

Enable device
inhibited)

and
the

Enable

inhibit

interrupt

PIO

(interrupts

DTC

still

PAPOL

CLR

PASIO

MOVB

#2,PCPOL

#377,PCDDIR

MOV

#164377,I0CNTL

MOV

# INBUF ,R1

MOVB

#24 ,MCC

WO
e

for the REQUEST

Port C bits are inputs
configure the PIO buffers for A=in

B=output, CO0,C2=input, Cl,C3=output

« BLKB

used

Point
Enable

INBUF:

Port A bits are non-1nvertlng
Normal 1nput
Invert pin Cl - this is the line
signal

REQUEST

that

MOVB

Port A: Input Port, single-buffered
Use interlock handshake, 1nput

CLR

MOVB

Port A
#120, PAMODE
#70,PAHDSH

Set-up

input data buffer

ports A and

Wait here while the DMA transfers
take

place

Chain Load Region

« WORD

000020
padata+l

; Reload Word <Select CARA,CARB,CQPC,CM>

000010

« WORD

000000
000001

« WORD

000000
inbuf

« WORD

001602

« WORD

RELOAD:

« END

START

Current Address Register A Seg/Tag
Current Address Register A Offset
<This local address 1is the source,
its address

is held constant,

since the DTC is doing byte
transfers specify
the source address high byte>

Current Address Register B Seg/Tag
Current Address Register B Offset
<This local address 1is the
destination>

Current Operation Count <Transfer 8
words>

Channel Mode Register High
Channel Mode Register Low

{No match conditions, do nothing

upon completion,

transfer type =

Single Transfer CARA = source, byte
transfers>

PIO50.MAC

data

out

Port A of

the

PIO

174470

CMDREG

174454

CASTF1
CAOF1

==
==

174444
174440

MIC

177000

MCC

177002

PAVEC
PASTAT
PADATA
PAMODE

==
==
==
==

177004
177020
177032
177100

PAHDSH

177102

PAPOL

177104

PADDIR

177106

PASIO

177110

PCPOL
PCDDIR

==
==

177012
177014

IOCNTL

177140

START
¢ ¢

#340

MTPS

CMDREG

Reset

Load

#RELOAD,CAOQOF1

MOVB

#155,MMREG
#241 ,CMDREG

MOVB

the CH1

WO
WY

requests

Enable device

inhibited)

MOVB

#220 ,PAMODE

Port

MOVB

#050
, PAHDSH

Set-up

Port

PAPOL

CLR

PASIO

and

inhibit

(interrupts

A: Output Port,
single-buffered
Use interlock handshake,
REQUEST

Port A bits
Normal

are

output

DTC

interrupt

from PIO

CLR

device

still

A
WO

MIC

to Disable DTC

Load the CH1 Register Offset
Load Master Mode Reg to Enable
Start Chain Channel 1

Reset

CLRB

Reg

interrupts

DTC

PIO

the

+ Initialize the
MOVB
#1,MIC

#0,CASTF1

MOV
MOV

Load Master Mode

CLRB

recognition of

=WE

« Initialize the DTC
MOVB
#154 ,MMREG

Inhibit

VWE

This program transfers
utilizing the DTC

+TITLE

output

non-inverting

#2,PCPOL

MOVB

#377,PCDDIR

MOV

#165400, IOCNTL

;

MOV

, RO
#OUTBUF

MOVB

+.BYTE

configure the PIO buffers for A=out
B=input,

CO0,C2=input,

Cl,C3=output

Point to output data buffer

Enable ports A and C

: ¢
OUTBUPF

the line used to signal the DTC
Port C bits are inputs

Pin Cl must be inverted - this is

Wait here while the DMA transfers
complete

151,152,153,154,155,156,157,160,-1

- EVEN

« WORD

000000
outbut

« WORD

000020
padata+l

« WORD

+«WORD

001602

« WORD

REGION

« WORD

000010

Reload Word <Select CARA,CARB,COPC,CM>

current Address Register A Seg/Tag
Current Address Register A Offset
<This local address

is the source>

current Address Register B Seg/Tag
Current Address Register B Offset

<This local address is the destination,
Hold the address, must specify high byte
for byte

transfer>

Current Operation Count <Transfer 38

« WORD

000000
000001

- WORD

words>

‘RELOAD:

LOAD

CHAIN

« END

START

- Channel Mode Register High
Channel Mode Register Low

{No match conditions, do nothing upon
completion, transfer type = Single

Transfer

CARA = source, byte transfers>

5.3.3
Programming The PIO Counter/Timers
This
section
describes how to program the PIO Counter/Timers and
provides example programs demonstrating their capabilities.
Each of the three PIO Counter/Timers provides up to four lines for
external
access.
If
these
external
1lines
are
used,
the
corresponding
port
pins
must be available and programmed in the
proper direction. Table 5-5 displays which port pins correspond to
the Counter/Timer external

access

lines:

The
first
step
in programming a PIO Counter/Timer is to specify
which,
1if
any,
external
1lines
are to be used, the output duty
cycle,
and
whether
the
<cycle
1is
continuous
or single-cycle.
Figure 5-22 displays the available output duty cycles.

PIO Counter/Timer External Access Lines

Table 5-5

Function

C/T 1

Counter/Timer Output
Counter Input
Trigger Input
Gate Input

Port
Port
Port
Port

C/T 2

C/T 3
Port
Port
Port
Port

BO
Bl
B2
B3

Port
Port
Port
Port

B4
B5
B6
B7

IF TIME CONSTANT VALUE = 5
500 NS

PULSE OUTPUT MODE

|
T

|
5

|
4

|
3

|
2

|
1

l
T

|
5

|
4

IF TIME CONSTANT VALUE =8
SQUARE WAVE MODE

MR-1086-1231

Figure 5-22

PIO Output Duty Cycles

CO
Cl
C2
C3

Output Duty Cycles

Each
Registers must be loaded.
Constant
Time
the
Next,
to
used
are
which
,
registers
these
of
two
Counter/Timer contains
when
ter
down-coun
the
into
loaded
is
that
value
form the 16-bit
the Counter/Timer is triggered.

If external lines are to be used, then the corresponding port pins
should be programmed as bit ports with the correct data direction.
the Counter/Timer enable bit for that port must be
Finally,
enabled in the Master Configuration Control Register.

The down-counter is loaded and the countdown sequence is initiated
when the Counter/Timer is triggered. This trigger may occur if the
Trigger Command Bit (TCB) in the Command and Status Register 1is
set, or if an external trigger input was asserted. Once the
it will continue towards the terminal
countdown is initiated,
count as long as the Gate Command Bit (GCB) in the Command and
Status Register is set and the Gate Input is held asserted (if it
is enabled). If a trigger occurs during a countdown sequence, the
action taken 1is determined by the Retrigger Enable Bit (REB). If
REB = 0, the trigger is ignored, but if REB = 1, the down-counter
is reloaded and a new countdown is initiated.

count
terminal
the
When
Continuous/Single Cycle bit
Register

reached, the state of the
is
(C/SC) in the Mode Specification

examined. If C/SC = 0, the countdown sequence stops.

If C/sSC = 1, the time constant is reloaded and a new countdown is
initiated. If the Interrupt Enable Bit (IE) is set, an interrupt
request 1is generated when the down-counter reaches its terminal
count. If a terminal count occurs while the Interrupt Pending Bit
1is set, an error is indicated by the Interrupt Error (ERR)
(IP)
bit.

The

following

program

PIO Counter/Timers.

TMo

.TITLE

provides an example of how to program the

CT1.MAC

how to utilize one of the
This program demonstrates

Counter/Timers on the KXJ11-CA. Counter/Timer 1 will be used 1in
this program. This counter/timer is clocked at a 500 ns rate.
The time constant used for the counter is 50,000. Therefore,

the countdown sequence will take 25 ms. (500 ns X 50,000 =
25,000,000 ns = 25 ms). The interrupt service routine waits
until the countdown sequence has completed 40 times and then
outputs an 'A' out of the console port. This should happen
approximately one time a second. (25 ms X 40 = 1 s).

After this program has been assembled and linked on the
development machine, use the KUI utility of the KXJ11-CA
software Toolkit to load the program into the KXJ11-CA.
The program will execute as shown in the following example.

LOAD

EXECUTE

O
WO

SET

EXIT

CT1l.SAV

Notice

coming

#340

;

Disable

MOVB

#1,MIC
MIC

i
;

Reset

CLRB

MOVB
MOV

#210,CTVEC
#ISR,Q#210

;
;

Initialize Counter/Timer vector

MOV

#340,@#212

;

and

ISR

CLR

Used

MOVB

#200,CT1MOD

;

that

the

'A's

keep

after you

exit

KUI!

MIC

MCC

177000
177002

CTVEC

177010

CTI1CON

177024

CT1HI

177054

CT1LO
CTIMOD

==
==

177070

177056

START
¢ ¢

MTPS

recognition

#203,CT1HI
#120,CT1LO

interrupts

PIO

Enable

PIO

Select

(Interrupts

disabled)

address

counter

continuous mode,

access,

MOVB
MOVB

pulse

;
;

CT1HI and CT1LO combine
141520(8) = 50000(10)

MOVB

#100,MCC

;

MOVB

#200 ,MIC

;

MTPS

;

Enable
Enable
Enable

BISB

#306 ,CT1CON

;

Set

external

form

output

Counter/Timer 1
PIO interrupts
recognition of interrupts

IE,GCB,TCB -

this

starts

the

countdown
BR

’

Wait

here

for

the

interrupts

ISR:

INC

;

CMP

R1,#40.

;

Increment the counter
IF this 1s not the 40th

BNE

;

THEN

CLR

;

MOVB

#101,Q@#177566

;
is

the

count

again

ELSE

clear

the

send

'A'

counter
the

time
and...

console

s +

;

The

;

development

;

terminal

2S:

console

MOVB

this

system

case

console.

SLUl

#44,CT1CON

see

the

« END

START

'A's

Clear
GCB

RTI

KXJ11-CA

Therefore,

IUS

console
you'll

pop

and

NOT

the

have

hook

out.

but

don't
,

bother
-

CHAPTER 6
SERIAL

LINE

UNITS

OVERVIEW

6.1

The KXJ11-CA has two serial line units (SLUs): SLUl and SLUZ2.

SLUl is also called the console port and is designed around the
DLART (DC319) chip. SLUl is dedicated for a console device. For
details on the operation and programming of the DLART, refer to
the DLART Data Sheet included as part of this documentation
package.

SLU2 is also called the multiprotocol serial controller (MPSC) and
has two independent channels, A and B. SLU2 is designed around the
uPD7201 chip. For details on the operation of the MPSC, refer to
the MPSC Data Sheet included in this documentation package. There
are three timers associated with SLU2, and designed around the
Information on these timers 1is included here for
8254 chip.
completeness. Refer to the 8254 Data Sheet included as part of
this documentation package for operational details.

The

material

that follows summarizes and describes the DLART and

MPSC functions implemented on the KXJ11-CA.

CONSOLE SERIAL PORT (SLU1l)

6.2

provides

SLUl1

console

serial

the

line:

following

features

and capabilities for the

Asynchronous operation

Error detection overrun, framing, and BREAK detection
Internal baud rate generation from 300 to 38.4 K baud
Common baud rate for both transmitter and receiver
50- and 60-Hz real-time clock interrupt outputs

One

6.2.1

stop bit

SLUl

only

(Console)

Registers

The console serial port (SLUl) is based on the DLART (DC319) chip.
All SLUl registers are contained in this chip. SLUl has a receiver
and a transmitter, each of which has a control/status register and
a buffer register. These registers are described in the sections
that follow. Note that these registers are the ones used for
console ODT operations.

6.2.1.1
Receiver
Control/Status
Register (RCSR) -- The Receiver
Control/Status
Register
(Figure
6-1)
1is
wused
to
monitor and
control
the
operation
of
the
SLUl
receiver. This register is

read-only.

ADDRESS: 17777560
15

RCV

R!:V

ACT

RCV

Figure 6-1

Bits

Name

15:12

(RCSR)

Description

Not

RCV ACT

10:8

Receiver Control/Status Register

RCV DN

5:0

RCV IE

(read

zeros)

Receiver

active - When set,

Not

(read

the

receiver

is active.
Set when the start bit of the
input
serial
data
1is
received.
When
cleared,
the
receiliver
is
1nactive.
Cleared at the expected time of reception
of the stop bit (after RCV DN is set).
used

zeros)

Set
after
a character has been received
and
1is
1in
the receiver buffer register
(RBUF).
Cleared
when
the
character 1is
read

used

from

RBUF.

When
set, allows an interrupt request to
be
made when bit 7 (RCV DN) is set. When
cleared, disables interrupts from RCV DN.
Not

used

(read

zeros)

6.2.1.2 Receiver Buffer Register (RBUF) —-- The Receiver Buffer
(Figure 6-2) holds the most recent byte received
Register (RBUF)
and contains break and error information for this byte. RBUF is
read-only.

ADDRESS: 17777562

117

olo]oO

R
I

RCV DATA

MR-17180

FR
ERR

ERR
OR

RCV

ERR

BRK

Figure

Bits

Name

ERR

6-2

Receiver Buffer Register (RBUF)

Description

Set when bit 14 (OR ERR) or bit
Error Cleared when the
set.
is
(FR ERR)
13
condition causing the error is cleared.
ERR

Overrun error - Set when a received byte
is loaded into bits 7:0 (RCV DATA) before
the RCSR (RCV DN) 1is cleared.
of
7
bit
This occurs when a new byte is received
before the reception of the previous byte
is updated each
bit
This
complete.
is
time a byte

FR ERR

Framing

is received.

error - Set when a recelved byte

loaded 1into
is
without a valid

bits
stop

(RCV DATA)
7:0
FR ERR is
bit.

updated each time a byte is received.

Not used

RCV BRK

10:8

7:0

RCV DATA

(read as zero)

- Set when the receiver's
break
Receive
goes from a mark to a
1line
input
serial
stays in the space
and
n
conditio
space
after
times
bit
11
for
condition
serial
when
Cleared
starts.
reception
input returns to the mark condition.
Not used

(read as zeros)

Receive

data

- Contains the most recent

1is
Each time a byte
received.
byte
is
RCSR
the
in
bit
DN
RCV
the
received,
set.

6.2.1.3
Transmitter
Control/Status
Register
(XCSR)
==
The
Transmitter
Control/Status
Register
(Figure
6-3)
1s
wused
to
monitor
and
control
the operation of the SLUl transmitter. Bits
<15:7> of this register are read-only. Bits <6:0> are read/write.

ADDRESS: 17777564

|
|

04
PB

02-

OO0

X RDY

PBE

XIE

X BRK
MR-17181

Figure 6-3

Transmitter Control/Status
Register

Bits

Name

15:8

Description

Not used

X RDY

(XCSR)

(read as

zeros)

set,
(XBUF)

When
ready
Transmit
Register
Buffer
Transmitter
ready to accept

a byte.

the
1is

Cleared when XBUF

is written.

5:3

X IE

Transmit

interrupt

disables

interrupts

Programmable

the

determine
baud

rate

PB
000
001
010
011
100
101
110
111

Maintenance

When set,

enable

interrupt
(X RDY) is

an
allows
bit 7
when

request to be made
set. When cleared,

from X RDY.

baud

rate

transmitter

These

Dbits

and receiver

shown:

Baud Rate
300
600
1200
2400
4800
9600
19200
38400

When set, external serial

SLUl is disabled and the
to
input
data
transmitter serial output is connected to
input. This allows
serial
receiver
the
self-testing of

SLUl.

Bits

Name

Description

PBE

Programmable

to SLUl.

source external

- When set, the

rate

baud

When
PB.
by
determined
1is
rate
baud
cleared, the baud rate is determined by a

forced

line
output
condition.

set, the serial

When

break

Transmit

X BRK

space
|

-- The Transmitter
(XBUF)
6.2.1.4 Transmitter Buffer Register
recent Dbyte
most
the
holds
6-4)
(Figure
Register
Buffer
Bits
read-only.
are
register
this
of
<15:8>
Bits
.
transmitted
<7:0>

are read/write.

ADDRESS: 17777566
1%

0| O

Figure 6-4

Bits

Name

IXM{TDAEI’A '
B

Transmitter Buffer Register (XBUF)

Description

Not used (read as zeros)

15:8

7:0

XMIT DATA

Transmit data - Contains the next byte to

be transmitted. When the X RDY bit in the
XCSR is clear, XMIT DATA is copied into a
serial data output
(the
register
shift
for transmission. XMIT DATA is
register)
be
to
byte
next
the
with
loaded
transmitted, which sets X RDY. When X RDY
is cleared, the operation is repeated.

6.3
SLU2

MULTIPROTOCOL SERIAL CONTROLLER (SLU2)
provides
the KXJ11-CA
with
the following

features

and

capabilities.

Two

full

duplex

channels

Channel A provides full modem control
Channel B provides data and timing leads

only

Each channel may be operated in one of three modes
Asynchronous

5, 6, 7, or 8 Data bits
1, 1-1/2, or 2 Stop bits
0odd, Even, or No Parity
Break generation and detection
Interrupt on Parity, Overun, or
Character-oriented

Monosync,

Bisync,

synchronous

and External

Framing Errors

Sync Operations

Software Selectable Sync Characters
Automatic Sync Insertion

CRC Generation and Checking

Bit-oriented synchronous
HDLC and SDLC Operations

Abort Sequence Generation and Detection
Automatic Zero Insertion and Detection
Address Field Recognition
CRC Generation and Checking
I-Field Residue Handling

Programmable

Baud

Rates

Double Buffered Transmitted Data

Quadruple—Buffered Received Data

Programmable

Channel A may utilize the DMA controller to transfer data

CRC Algorithm

6.3.1
Synchronous/Asynchronous Serial Line (SLU2) Registers
SLU2
is
a
synchronous/asynchronous
serial
device
with
two
independent
channels, A and B. SLU2 is based on the uPD7201 chip.
The registers associated with SLU2 are summarized in Table 6-1.
KXJ1l

gate
an

Control/Status

array.

contained

in the GAS on-board

The timer data and control registers are contained in

on-board
1Intel
8254-2
timing
controller
registers are contained in SLU2 itself, that is,

chip.

The
other
the uPD7201 chip.

Table

6-1

SLU2 Registers

Address

Access

Description

17777520

KXJ11l Control/Status Register A

17775736
17775734
17775732
17775730
17775724
17775722
17775720

W
W
W
W
R
R
R

SLU2 Timer Control Register
SLU2 Timer 2 Data Register
SLU2 Timer 1 Data Register
SLU2 Timer 0 Data Register
SLU2 Timer 2 Data Register
SLU2 Timer 1 Data Register
SLLU2 Timer 0 Data Register

Channel A

Channel B

Address

Access

Description

17775706
17775704
17775702
17775700

17775716
17775714
17775712
17775710

W
W
R
R

Transmitter
Control Register
Receiver
Status Register

Register A (KXJCSRA)
Control/Status
6.3.1.1 KXJ11
on which affects the overall
informati
control
register contains
whenever the KXJ11-CA
cleared
is
register
The
operation of SLU2.
is powered up or reinitialized.

KXJ1l1

Control/Status

ADDRESS: 17777520
15

......
......

......

......
......
......
......
......

......

......
......
......

CNT IE

TERM

|SYNCM A SYNCM B

RTC IE

SER

TT 108/2

SLU2B

EN
MR-17146

Figure 6-5

KXJ11l Control/Status Register A

Bits

Name

Description

15:8

Not

used

(read

ones)

CNT

Programmable
counter
interrupt enable When
set,
interrupts
from programmable
timer/counter
2
are
enabled.
When
cleared, these interrupts are inhibited.

RTC

Real-time

set,

clock

interrupts

1interrupt

from

enable

the

- When

on-board

real-time
clock
(RTC) are enabled. When
cleared, these interrupts are disabled.

Not used
TERM

SER

(read/write)

Terminal
in
service
For
use
with
modems.
When
set,
Terminal
In Service
(IS)
1is
asserted and incoming calls can
be
connected.
When
cleared,
IS is not
asserted.

TT108/2

Modem
connected
For use with modems.
When
set,
Terminal
Ready
(TR)
1is
asserted.
When
cleared,
TR
1is
not
asserted.

SYNCM A

Clock
select
channel A - When set, SLU2
channel
A
receives
1its
<clock from the
on-board
baud
rate
generator.
When
cleared,
channel
A
receives
1ts clock
from

SLU2BR EN

external

Party
line
KXJ11-CA is

source.

enable
configured

operation.
When
set,
not
receive
party
cleared,
party
1line
channel B is enabled.

SYNCM B

Used
when
the
for
party line

SLU2 channel B can
line
data.
When
data reception for

Clock
select
channel B - When set, SLUZ2
channel
B
receives
1its
clock from the
on-board
cleared,
from an

baud
channel
external

rate
generator.
B
receives
1its

When
clock

source.

6.3.1.2
Timer
Registers
-=There
are three independent timers
associated
with
SLU2.
These
timers,
1labeled
0, 1, and 2, are
contained
in
an
on-board 8254-2 timing controller chip. Timer 0
and
timer
1 run at 9.8304 MHz and are used to determine the baud
rates
for
SLU2
<channels
A
and
B,
respectively. Timer 2 is a
general-purpose
800
Hz clock capable of generating interrupts at
priority level 6. Interrupts from the 800 Hz timer are enabled and
disabled
via
bit
7
of KXJ11-CA Control Register A (see Section
6.3.1.1).

has

timer

Fach

a Control Register and a Data Register. To use a

timer, its Control Register is loaded first with configuration
information. Then, its Data Register is loaded with the number of
clock "ticks" the timer 1is to count.

The baud
"divider

rates for channels 0 and 1 can be set by loading a
For synchronous
Register.
Data
a
into
ratio"

transmission,

Divider ratio = 9830.4 K / synchronous baud rate

6-2

Table

illustrates the correspondence between various divider

ratios and synchronous baud rates.

For asynchronous transmission,

Divider ratio = 614.4 K / asynchronous baud rate

Table 6-3 1illustrates the correspondence between various divider
|
ratios and asynchronous baud rates.
Table 6-2

Synchronous Baud Rates

Divider Ratio (Decimal)

72.282
55.855
47.720
19.200
9.600
4.800
1.200

136
176
204
512
1024
20438
8192
Table 6-3

5586

K
K
K
K
K
K
K

Asynchronous Baud Rates

Divider Ratio (Decimal)
2
4
8
16
32
64
128
256
512
1024
2048

Synchronous Baud Rate

Synchronous Baud Rate
307.2
153.6
76.8
38.4
19.2
9.6
4.8
2.4
600.0
300.0
150.0

K
K
K
K
K
K
K
K

109.989

6.3.1.2.1
SLU2
Timer
Control Registers =- There are three Timer
Control
Registers,
one
for each timer. They all have the format
shown

Figure

6-6.

17775736

ADDRESS:
%

1|1l1l1l1

SC
|

RIW
|

]M]
]

]

BCD

MR-17147

Figure

Bits

Name

15:8

7:6

6-6

Timer Control

(Timers

and

Description
Not used

(read as

ones)

Select counter - Determines which counter
is
selected
or
command is issued.

whether

read

SC
00

Selection
Select counter O

01
10
11

Select counter 1
Select counter 2
Issue read-back command

If
a
<5:0>

back

read-back
command is issued, bits
of
the Timer Control Register are

defined

follows:

Bit

Definition

Count
When
set,
1latches
the
contents
of the Timer Counter Data
Register(s)
specified
by
bits
<3:1>.
The
contents
of
the
register(s)
are
1interpreted
as a
count of clock "ticks."

Status
When
clear, latches the
contents
of the Timer Counter Data
Register(s)
specified
by
bits
<3:1>.
The
contents
of
the
register(s)
are
interpreted
as
status information.

When

set,

specifies

counter

When

set,

specifies

counter

When

set,

specifies

counter

Must

6-10

zero

Bits

Name

Descriptioh

5:4

Read/write

information

1is

byte of
a
to/from

which

Determines

read/written

Data Register or whether a counter
Timer
latch command is issued.
RW

Selection

Issue counter latch command

Read/write

least

significant byte

most

significant

only

Read/write

Dbyte

only

first,

least

significant byte

then most significant byte.

command is 1issued,
latch
counter
a
If
<3:0> of the Timer Control Register
bits
not
are
and
bits
care”
"don't
are
interpreted.

the operational
Selects
select
Mode
the timer. See the uPD7201 Data
of
mode
Sheet for descriptions of these modes.
M
000
001
010
011

Mode
Reserved
Reserved
Baud rate generator
Square wave

101
110
111

Reserved
Reserved
Reserved

100

BCD

Software triggered strobe

BCD enable - When set, indicates that the
information in the Timer Data Register 1is
to be interpreted in binary coded decimal
When
decades) .
(four
format
(BCD)
1n
ted
interpre
1is
data
the
cleared,
16-bit binary

format.

6.3.1.2.2
SLU2
Timer Data Registers =- There are six Timer Data
Registers,
two
for
each
timer. Each timer has one register for
read
data
and another register for write data. They all have the
format
shown
1in
Figure
6-7 except when status data is read. In
that case, the format is as shown in Figure 6-8.

ADDRESS: 17775720, 17775722, 17775724, (READ-ONLY)
17775730,

17775732, 17775734, (WRITE-ONLY)

11111|11l1

03
]

]

MR-17148

Figure

Name

7:0

Timer Data Register Format
(Read and Write Registers 0,

and 2)

Description
Not

00/

Bits

6-7

used

Counter
timer

(read

ones)

data

specifies

clock

"ticks."

number of

ADDRESS: 17775720, 17775722,17775724,
1%

R\IN

'Ml

]

BCD

OUTPUT
NULL
MR-17149

Figure

Bits

Name

15:8

6-8

Timer Data Register Format When Used
as a Timer Status Register

Description

Not used

OUTPUT

Output

(read as ones)

When

set,

the

corresponding

The
asserted.
is
signal
output
the same as the
1is
bit
this
of
of
the
timer's pin on the 8254-2

timer
state
state

chip.

NULL

Null - When cleared,
written

and

1is

a new count has been

ready

to be

read.

When

set,

the counter contains a "null count"

user

desires

value which should not be
count.

read unless

the previous

the

(not updated)

Description

byte of
which
Determines
Read/write
a
to/from
read/written
1is
information
Timer
Data Register or whether a counter
latch command is issued.
RW

Selection

Issue counter latch command

Read/write

significant byte

1least

only

significant

most

Read/write

byte

only

least

Read/write

significant byte

then most significant byte

first,

command is issued,
latch
counter
a
If
Control Register
Timer
<3:0> of the
bits
care"

"don't

are

bits

and

are

not

interpreted.

Mode
mode

select
of

Selects

the operational

timer.

M
000
001
010
011

Mode
Reserved
Reserved
Baud rate generator
Square wave

101
110
111

Reserved
Reserved
Reserved

100

Software triggered strobe

BCD enable - When set, indicates that the
information in the Timer Data Register 1is
to be interpreted in binary coded decimal
When
decades) .
(four
format
(BCD)
1in
interpreted
1is
data
the
cleared,

binary

16-bit

BCD

the

format.

6.3.1.2.3
SLU2
Timer
Programming
Considerations
-When
the
watchdog
timer
is
operating
in Mode 2 (that is, as a baud rate
generator),
an
initial
<count
1is
1loaded
into
the
Timer Data
Register
and
the count is decremented upon each clock tick. When
the
count
1is
decremented
to
a
value
of
1,
an interrupt is

generated,
the
initial count
decremented.
This
process
periodically generate

is reloaded, and the count is again
causes
the
watchdog
timer
to

interrupt.

When
a
read-back
command
is
issued to the watchdog timer, the
timer
is
loaded on the next 800 Hz clock tick. If the user tries
to
read
back values written into the timer before the clock tick
has
occurred,
erroneous
data may be read. The user should delay
the
reading back of values written to the timer for at least 1.25
milliseconds.

The
way
to stop the watchdog timer is to write the Timer Control
Register, selecting counter 2 in bits <7:6> and specifying a valid
mode
in
bits <3:1>. When this is done, the timer stops and waits
for a new initial count to be loaded into the Timer Data Register.
If
a
new initial count is not loaded, the operation of the timer
is

suspended

and

effectively

stopped.

Hardware
resets
have
no effect on the operation of the watchdog
timer.
A
hardware reset only clears a pending interrupt (if any)
from the

timer.

6.3.1.3

SLU2 Control Registers -- Each channel has a set of eight

write-only
Control
Registers
numbered
0
through
7.
Control
Register
0 can be written directly. Control Registers 1 through 7
are
accessed
by
first writing Control Register 0 bits <2:0> and
then
writing the desired Control Register. This section describes
each of

the

6.3.1.3.1

Control

Registers.

Control Register 0 -- See Figure

6-9.

ADDRESS: 17775704, 17775714
15

CRC
|

CMD

01
RP

MR-17150

Figure

6-9

Control

Bits

Name

Description

Not used

15:8
CRC

(read as ones)

CRC
control
The
following
commands
control
the
operation
of
the
cyclic
redundancy check (CRC) circuitry:
CRC

Mode

Null - No effect.

- 1In
checker
CRC
receiver
Reset
synchronous
mode,
resets
the CRC
checker
to
zeros.
In
SDLC mode,
resets

CMD

the

CRC

checker

ones.

Reset
transmitter
CRC generator In synchronous mode, resets the CRC
generator
to
zeros. In SDLC mode,
resets

Used when setting

other
fields in Control Register 0
such as the register pointer field.

the

CRC

generator

ones.

Reset
1idle/CRC
1latch - Clears the
idle/CRC
latch. When a transmitter
underrun
occurs,
the
transmitter
enters
the
CRC phase of operation
and
begins
to
send
the
CRC
character
calculated
up
to
that
point.
Then
the
1latch 1s set. If
the
underrun
condition
persists,
idle
characters are sent after the
latch is set
This
character.
CRC
when the channel is initialized.

following SLUZ2
The
Commands
are specified by this field:

commands

CMD

Command

000

Null - No effect. Used when setting
fields in Control Register O
other

001

1in SDLC mode.
Used
abort
Send
code to be
abort
SDLC
an
Causes
transmitted.

010

external/status interrupts Reset
external
pending
any
Clears
interrupts
interrupts

allows
and
to be detected.

new

Bits

Name

Description

011

the
Disables
and
receivers
outputs
(transmitter
transmitters
modem
sets
and
high)
set
are
Disables
high.
outputs
control
clears all DMA and
and
interrupts
Control
All
requests.
interrupt
after a
rewritten
be
must
Registers

reset
Channel
channel’s

reset

channel

One

command.

NOP

instruction must be executed before
a new command can be written.

100

interrupt on next character
Enable
operating in Interrupt
when
Used
mode. Reenables
Character
First
on

the

received

101

pending

transmitter

Clears a
Becoming
Buffer
er
Transmitt
pending
request

interrupt/DMA

Error

request
DMA
or
interrupt
character.
another
sending

reset

Clears

Receive Condition interrupt.
parity

111

for the next

character.

Reset

Empty
without

110

logic

interrupt

and

Special

Clears

overrun errors.

End of interrupt (Channel A only) -

part of an
as
included
Typically
routine.
service
interrupt
1in
devices
priority
Reenables lower
for
chain
daisy
interrupt
the
pending
any
of
servicing
interrupts.

2:0

Specifies which
pointer
Register
or which
written
Control Register will be
When
next.
read
be
Register will
Status
ed,
initializ
or
reset
is
the KXJ11-CA
the
allows
which
000
this field is set to
the
or
0
Register
Control
of
writing
Reading of Status Register 0. Following a
read or write to a Control Register other
than 0,

this field

is set to 000.

6.3.1.3.2 Control Register 1 -- See Figure 6-10.
ADDRESS: 17775704, 17775714, RP = 001, WRITE ONLY
15

04
|

R:M

EXT IE

SAV

XMIT IE
MR-17151

Figure

Bits

Name

Must
-

RIM

Description

Not used

15:8
B

Control

6-10

(read as ones)
zero

Receiver

interrupt mode - Determines how

a channel handles received characters.
RIM

Interrupt Mode

request
interrupts/DMA
Receiver
or
interrupt
Disables
disabled
a
1if
channel
this
from
DMA requests
(polled
received
is
character
.
mode)

Interrupt on first character only to be issued
interrupt
an
Causes
received
character
first
the
for
first
on
an enable interrupt
after
given
been
has
command
character
Control
of
description
(see
is 1in
channel
the
If
0).
Register
1issued
is
request
a DMA
DMA mode,
character . received,
each
for
including

the first.

Interrupt

all

received

characters - Causes an interrupt to

whenever a character is
issued
be
channel's receive
the
in
present
is issued if
request
A DMA
buffer.
mode.
DMA
in
1is
channel
the
ed
consider
is
error
parity
n.
Special Receive Conditio

A
a

received
all
on
Interrupt
to
similar
1is
This
characters
The
ly.
previous
described
10,
that a parity error
1s
difference
<considered to be a Special
not
is
Receive Condition.

6-17

Bits

Name

SAV

Description

Must be 1 for
vector
affects
Status
A. This
channel
for
0
be
must
B,
channel
loaded
vector
the
that
ensures
setting
B, 1s
channel
2,
Register
Status
into
the
of
cause
the
indicate
to
modified
interrupt.

XMIT

When set,
enable
interrupt
Transmit
when
interrupt
an
issue
will
this channel
oOr
empty
becomes
buffer
transmitter
the
phase
Idle
an
enters
transmitter
when the
flag
or
sync
transmitting
begins
and

characters.

EXT

interrupt enable - When
status
External
set, this channel will issue an interrupt
occur:
following
the
of
any
when
(CD)
Detect
Carrier
a
of
Transition
to Send
Clear
a
of
transition
input,
of sync input,
transition
input,
(CTS)

synchronous

leaving

entering

Phase
SDLC

or
or

detection
detection

break
abort

set.

latch becoming

Idle/CRC

6.3.1.3.3 Control Register 2 - Channel A -- See Figure 6-11.
ADDRESS: 17775704, RP = 010, WRITE-ONLY
OO0

110

O
O |PRI|

DMA

MODE
MR-17209

Figure

6-11

Control

Hunt

termination,
termination,

Channel A

Bits

Description

Name

15:8

Not used (read as ones)

723

Must be 00010

If both channels A and B are

TxA

> RxB > TxB > extA > extB if

RxB

> TxA > TxB > extA > extB if

Priority

PRI

the interrupt priority

in interrupt mode,
is

RxA
PRI

cleared and

set.

If channel A is in DMA mode and channel B
1interrupt
the
mode,
interrupt
in
is
1s

priority

RxA >

extB

extA >

Must be zero

TxB

RxB >

mode - If set, channel A operates 1in

DMA

DMA MODE

mode

DMA

cleared,
in

channel

and

does

not.

neither channel A nor B operates
\

DMA mode.

6.3.1.3.4 Control Register 2 - Channel B -- Control Register 2 for
channel B holds the SLU2 interrupt vector (Figure 6-12). Although
the register is programmed via channel B, the same vector is used
for interrupts on both channels A and B. Initially, the KXJ11-CA
firmware loads this vector with an octal value of 70. If bit 2 in
Control Register 1 is set, the contents of this register will be
modified according to the type of interrupt that occurs. The
modified vector is obtained from Status Register 2 (see Sectilon
6.3.1.4.3).

ADDRESS: 17775714, RP = 010, WRITE-ONLY

I
|

|
]

|
|

I
!
VECTOR
|

l
MR-17210

Figure 6-12

Control Register 2 - Channel B

6.3.1.3.5

Control Register 3

See

Figure

6-13.

ADDRESS: 17775704, 17775714, RP = 011, WRITE-ONLY
15

L
BPC
)

AUTO

RCV

ENB

CRC

HUNT

SYNC.

LOAD

ADDR

RCV IE

SRCH
MR-17211

Figure

6-13

Control

Description

Name

Not

used

(read

ones)

Bits per character - Specifies the number
of data bits per received character.

BPC

AUTO

ENB

BPC

Bits

00
01

5
6

Per Character

Auto

enable

Detect
(CD)
receiver
and
as the enable

When set, causes Carrier

to act as an enable for the
Clear to Send (CTS) to act
for the transmitter.

Hunt
When set, causes the receiver to
enter
a
hunt
phase.
This is typically
done to restore synchronization. When the
receiver
1is enabled, a hunt begins and a

HUNT

transfer
can
occur
only when character
synchronization
has
been
achieved. The
hunt
phase is also automatically entered
whenever a channel is reset.
RCV

CRC

Receiver
CRC
enable - When set, enables
CRC
calculation.
When cleared, disables
(but
does
not
reset)
the receiver CRC
generator.

ADDR

SRCH

Address
search
mode
- This bit must be
zero
1in
non-SDLC
modes. If this bit is
set in SDLC mode, character assembly does
not
begin
wuntil
the
8-bit
character
(secondary
address
field) following the
starting flag of a message matches either
the
address
programmed
into
Control
Register 6 or the global address 11111111
(binary).
6-20

Bits

Name

Description

SYNC LOAD

Sync

character
the

prevents

load inhibit - When set,

1loading of sync characters

into the receive buffer. Meaningful only
in synchronous mode. When using CRC, this

strip only the
to
wused
be
should
bit
preceding
characters
sync
leading
embedded
the
not
and
message

bit

using other types

Protocols

characters.

block checking, however, may use this
embedded

the

strip

characters.

Receiver

RCV 1IE

channel's

enable - When set,

enables

When

receiver.

disables the receiver.

this

cleared,

6.3.1.3.6 Control Register 4 -— See Figure 6-14.
ADDRESS: 17775704, 17775714, RP = 100, WRITE-ONLY

15
1

14
1

07 06

Cll.K

f:/l

SIB

PAR

PAR
ENB
MR-171562

Control Register 4

Figure 6-14

Bits

Name

Not used (read as ones)

15:8

7:6

Description

CLK

Clock

rate

When

operating

CLK

Clock Rate

the
between
inputs
clock

must be

00
01
10
11

1
16
32
64

Specify

1in synchronous mode, CLK

00.

X
X
X
X

data
data
data
data

the relationship

receiver
transmitter
and the actual data rate.

rate
rate
rate
rate

Bits

Name

5:4

Description
Sync

Mode

Selects

which

synchronous

protocol
to use if this channel has
programmed in a synchronous mode.
M

Protocol

Monosynch
Bisynch
SDLC
External Synch

01
10
11
3:2

Stop

bits/synchronous
mode
the
channel
will

whether

synchronous

asynchronous

PAR

this

Asynchronous

mode,

Asynchronous

mode,

1.5

Asynchronous

mode,

also

of stop bits used by
receiver always uses

Mode
Synchronous

sense

mode.

field

SB
00

Parity

Specifies
wused
1in

asynchronous

mode,

specifies the number
the transmitter. The
one stop bit.

been

mode

When

stop

bit

stop

set,

bits

causes

even

parity
generation
and
checking.
When
cleared, causes odd parity generation and
checking.
0

PAR

ENB

Parity

Control

When

set,

causes

parity

each

received

Also

performed
5

See

for

Figure

6-15.

ADDRESS: 17775704, 17775714, RP = 101, WRITE-ONLY
15

OO0

BI;C

XMIT

RTS

ENB

BRK

‘

CRC

XMIT

SEL

CRC
MR-17153

6-15

extra

character.

Figure

parity information to be
with
each
transmitted

be
6.3.1.3.7

enable

bit
containing
concatenated

Control

checking

character.

Bits

Descriptioh

Name

(read as ones)

Not used

15:8

Must

zero

Transmitted

BPC

Specifies

bits

number

the

per

character

data bits per

character.

transmitted

Bits/Character

BPC
00

01
10

7
)

less

that
Note
bits/character,
formatted

for

the

follows:

five
data

less
be

or
must

Format

Bits/Character

1111000d
111000dd
11000ddd
1000dddd
000ddddd

1
2
3
4
5

Where
d
represents a data bit. The most
always 1in the
1is
bit
data
significant
leftmost position.

XMIT

channel's
(spacing).

ENB

SEL

transmitter

set,
data

forces

this

output

low

Transmitter enable - When this channel is
The
cleared.
is
bit
this
reset,
is forced high
output
data
transmitter
(marking) and the transmitter is disabled
this

until
CRC

When

break

Send

BRK

CRC

bit

select

polynomial

set.

1is

When set,

the

When cleared,

the

selected

(X**16 +

CRC-CCITT polynomial is selected

(X**16 +

CRC-16

X**15

polynomial
X**2

+
X**12
polynomial

1is

1),

CRC-CCITT
The
1).
+
X**5
must be selected when in SDLC

mode.
RTS

Request
When

to Send - When set, asserts
RTS.
deasserts
cleared,

RTS.
In

1is
RTS
modes,
SDLC
and
synchronous
asynchronous
In
immediately.
asserted
the
only when
asserted
1is
RTS
mode,
completely
1is
buffer
data
transmitter
empty.

6-23

Bits

Name

Description

XMIT CRC

Transmitter
CRC
enable
When
set,
enables
this
<channel's
transmitter CRC
generator.

When

cleared,

individual

characters

the

CRC

calculation is not performed. Setting and
includes or excludes
bit
this
clearing
from

If this bit is cleared when
calculation.
a
transmitter
underrun
occurs, the CRC
will

not

sent.

Register 6 -- Control Register 6 (Figure 6-16)
Control
6.3.1.3.8
different meanings in different
has
which
1,
byte
sync
holds
modes.

ADDRESS: 17775704, 17775714, RP = 110, WRITE-ONLY

[1|1

1l1|1l1l1l1|

SYNC BYTE

04
|

MR-17154

Figure

6-16

The

Monosync
the

Idle

Control Register 6

8-bit sync character transmitted during

phase.

significant

least

The

bits of the 16-bit

Bisync

- A secondary address value that is matched to the
SDLC
Secondary Address field of the SDLC frame when in Address

transmit

and

receive sync character.

Search mode.

External Sync - The sync character transmitted during the
Idle

phase.

Register 7 -- Control Register 7 (Figure 6-17)
Control
6.3.1.3.9
different meanings in different
has
which
2,
byte
sync
holds
modes:

ADDRESS: 17775704, 17775714, RP = 111, WRITE-ONLY
15

111

OO0

lSYN(li BY'|;E2 :
MR-171565

Figure

6-17

Control

matched

character

sync

8-bit

The

by the

Monosync

Bisync

SDLC - Must contain the flag character (01111110) matched

receiver.

transmit and receive sync character.

of the 16-bit

bits

significant

most

The

receiver,

the

Sync

External

sync mode.

external

Control

1is

not

used in

6.3.1.4 SLU2 Status Registers -- Channel A has two read-only
Status Registers numbered 0 and 1. Channel B has three read-only
Status Registers numbered 0 through 2. A Status Register 1is read
by first writing Control Register 0 with an appropriate register
pointer. Then, a read to address 17775700 (for channel A) or
17775710 (for channel B) produces the status data. This section
describes each of the Status Registers.

6.3.1.4.1 Status Register 0 -- See Figure 6-18.
ADDRESS: 17775700, 17775710
1%

HEEIEEIEREIE

IDLE

Bits

Name

IP
XBE

RCA

Status Register 0

Description

Not used (read as ones)

15:8

DCD

BR/AB

Figure 6-18

BR/AB

IDLE

When

set in asynchronous

Break/Abort

or more 1's)

has been detected.

indicates that a break
receive mode,
A Dbreak
has been detected.
sequence
held low
is
input
occurs when the data
ter
charac
one
than
for more
(spacing)
high
returns
input
the
time. Cleared when
An External/Status interrupt,
(marking).
if enabled, occurs when the state of this
in SDLC mode,
When set
bit changes.
e (seven
sequenc
abort
indicates that an

Idle

Indicates

the

state

the

in synchronous and
Idle/CRC latch wused
1is set during a
bit
This
SDLC modes.

and cleared by a Reset
reset operation,
Transmit Underrun/EOM Latch command.
6-25

Bits

Name

Description

Clear
to
send
This bit reflects the
state
of the CTS input for this channel.
When set, CTS is asserted. Any transition
of
this
bit
causes
an External/Status
interrupt request.

Ssync
status
Meaning depends
operating mode of this channel.

upon

the

Asynchronous:
Reflects
the state of the
SYNC
input.
When set, SYNC is asserted.
Any
transition
of
this
bit
causes an
External/Status interrupt request.

External
sync
mode:
asynchronous
mode.
A
transition
of
this
bit
synchronization
has
been
character

assembly

Monosync,
indicates

DCD

the

begun.

Bisync,
SDLC modes:
that
the
receiver

Sync
Hunt
phase
cleared,
1indicates
in

has

Similar
to
low-to-high
indicates that
achieved
and

Receive

Data

When set,
1is 1in the

of
operation.
When
that the receiver 1is
phase.

Data
carrier detect - Reflects the state
of
the
DCD
input.
When
set,
DCD
1is
asserted.
Any
transition
of
this
bit

causes

External/Status

interrupt

request.
XBE

Transmitter
buffer
empty
When
set,
indicates
that the transmitter buffer 1is
empty,
except during transmission of CRC
charactcers
in
synchronous
mode.
When
cleared, indicates the transmitter buffer
is loaded. This bit is set during a reset
operation.

Bits

Description

Name

Interrupt pending (Channel A only) - Used
conjunction with the interrupt vector
in
Register 2, channel B)
(Status
register
SLU2
an
of
status
the
determine
to

interrupt.
this
mode,

Interrupt
Non-Vectored
Status
when
set
1is
bit
B is read. The low
channel

2,
Register
Register
Status
this
of
bits
three
cause of the interrupt. In
the
indicate
the Interrupt
mode,
Interrupt
Vectored
1is the
SLU2
set when
is
bit
Pending
requesting
device
priority
highest
either mode, the
In
service.
interrupt
cleared when an End of Interrupt
is
bit
is issued and there are no other
command
requests. This bit is
interrupt
pending
for channel B.

zero

When set,
enable
character
Received
rs are
characte
more
or
one
indicates that
Once
buffer.
receiver
the
1in
available
been
have
s
character
e
availabl
the
all
new
a
until
cleared
1is
bit
this
read,
received.
been
has
r
characte

RCA

6.3.1.4.2 Status Register 1 -- See Figure 6-19.
ADDRESS: 17775700, 17775710, RP = 001, READ-ONLY
1%

02
|

]

01
|

EOF

PE
MR-17157

Figure

Bits

Name

Description

Not used

15:8
EOF

Status Register

6-19

(read as ones)

End of frame - This bit is valid only 1in
indicates that a
set,
When
SDLLC mode.
flag has been received and
ending
valid
the CRC error flag and residue code
that
are

valid.

command

character of

Cleared

the next

frame.

upon

Error Reset

reception of the first

Bits

Name

Description

Framing
error - When set in asynchronous
mode, indicates that no stop bit has been

detected

the

end

received

character. When set in synchronous modes,
indicates
that
the calculated CRC value
does
not
match
the
last
two
bytes

received.

an
OR

This bit
command

issued.

the programmed sense
remains

(even/odd).

set until an Error Reset

issued.

residue code - These bits are valid
SDLC
only in SDLC mode. The data portion of an
a
of
consist
may
message
SDLC
number of characters. Since
non-integral
the
oriented,
character
are
transfers
code provides the capability to
residue
receive
any
leftover
bits.
See
the
uPD7201 Data Sheet for a table of residue
of
characters
to
corresponding
codes
various

issuing

- When set, indicates that
error
Parity
parity checking has been enabled and that
character
received
a
of
parity
the

matches

is cleared by

command.

error - When set, indicates that
Overrun
receiver buffer has been overloaded.
the
(FIFO) can contain
buffer
receiver
The
If a fourth character
characters.
three
1last character in the
the
received,
is
error bit
This
overwritten.
1is
buffer
remains
latched
until
an
Error
Reset
command

This bit

Error Reset

lengths.

All sent - When set in asynchronous mode,
that the transmitter buffer is
indicates
empty. When cleared in asynchronous mode,
that a character is present in
indicates
the transmitter buffer or shift register.
synchronous modes, this bit is always
In
set.

(Channel B Only)

6.3.1.4.3 Status Register 2

-- See Figure 6-20.

ADDRESS: 17775710, RP = 010, READ-ONLY

%
1

12
1

09
1

)

VEC

I
]

01
S

OO0

]
MR-17158

Figure

Bits

Name

Status Register 2

6-20

(Channel B Only)

Description

Not used (read as ones)

15:8

7:3

VEC

2:0

Interrupt vector - Contains bits <7:3> of
the vector contained in Control Register
2, channel B (see Section 6.3.1.3.4).
These
modifiers
Status
indicate the following:

three

bits

Description

111

No Interrupt Pending

000

Channel B Transmitter Buffer Empty

001

channel B External/Status Change

010

Channel

Received

Character

Available

011

Channel B Special Receive Condition

100

Channel A Transmitter Buffer Empty

101

Channel A External/Status Change

110

Channel

111

Channel A Special Recelve Condition

Received

Character

Available

be
They may
two meanings.
has
111
of
1
bit
examining
by
distinguished
0, channel A (Interrupt
Register
Status
Pending).

6.3.1.5
SLU2
Transmitter
Data
Registers,
one
for
registers

shown

Registers -- There are two Transmitter
each
channel.
The
format
of
these

Figure

6-21.

ADDRESS: 17775706, 17775716
1%

1.1

]

[

]

TRANSMIT DATA

MR-17159

Figure

6-21

Transmitter Registers A and B

6.3.1.6
SLU2
Receiver
Registers
=-There
are
Registers
(data
registers),
one for each channel.
these registers 1is shown in Figure 6-22.

two
The

Receiver
format of

ADDRESS: 17775702, 17775712
15

06
|

05
|

RECEIVE DATA

]

MR-17160

Figure

6-22

6.3.2
Examples
The
following
programs
application programs.

provide

"skeletons"

which

base

user

SLUl.MAC

This program utilizes the uPD7201 to transfer serial data. The
data will be transferred out of Channel A and received by
Channel A, so a loopback connector is required (Part #H3022 or
54-16229-01). This example transfers the data in asynchronous
mode

using

interrupts.

. TITLE

Receiver Registers A and B

After this program has been assembled and linked on the
development machine, use the KUI utility of the KXJ1l1-CA
Software Toolkit to load the program into the KXJ11-CA. This
program will execute as shown in the following example.

EXECUTE

1ODT

1001206

1001302/041101
1001304,/042103
1001306/043105
1001310/044107
1001312/041101
1001314/042103
1001316/043105
1001320/044107
1001322,/000000
1R4,/000000
ICTRL/C
EXIT

This verifies that the data was successfully transferred. 1302
is the address of the transmit buffer and 1312 is the address
of

the

receive buffer.

R4=0 verifies that no external or

special condition interrupts were receilved.

STATB

175710

CNTRLB

175714

TIMREG

175736

TIMERO

175730

Channel
Channel
Channel
Channel

175704
175706

CNTRLA

Channel
Channel

status register
receiver
control register
transmitter

ve vy

TBUFA

RBUFA

175700
175702

STATA

wme

WE WO

wWe

o
WG

SET 2
LOAD SLUl.SAV

status register
control register

Timer control register
Timer 0 data register

¢ ¢
START

This section initializes the KXJ11-CA system environment
interrupts

#340

Disable recognition of

MOV
MOV

#ISR,Q@#70
#340,@%#72

SLU2 interrupts at location 70
Let the ISR run at priority 7

CLR

This

MOV
MOV

#TBUF ,R2
#RBUF ,R3

CLR

MTPS

the

R2 points
R3 points

transmit

char counter

to the transmit buffer
to the receive buffer

of
This counter keeps track.
external status changes and
special receive conditions

= @

This section initializes the bit rate generator
MOVB

, TIMREG
#26

7
e

MOVB

#64. ,TIMERO

Select timer 0,

mode

low byte only,

binary

This divider selects 9600

bps

#30,CNTRLA

MOVB

Wait
Point

=29

#20,CNTRLA

MOVB

#1,CNTRLA
#36 ,CNTRLA

1 stop bit,

rate

Char length = 8
Interrupts

CRl1

Transmit IE, Interrupt on all
received chars, enable condition

@@
WO
WO

char length = 8

Reset External/Status

Enable

CR3

Enable transmitter,

affects

MAIN::

16x data

Enable receiver,

w0
O
@

Point

MOVB

to CRO

CNTRLA

(R2)+,TBUFA

asynch mode,

Point

CLRB

No parity,

to CRS5

#152,CNTRLA

MOVB

Point to CR4
Set operation mode:

Point

MOVB

interface options:

No DMA, RXA>RXB>TXA...,
Non-Vectored

#5,CNTRLA

CR2A

Point

MOVB

MTPS

Setup bus

rate =

#3 ,CNTRLA
#301,CNTRLA

MOVB

Channel

for reset to complete

clock

MOVB

for reset to complete

MOVB

#4 ,CNTRLA
#104 ,CNTRLA

MOVB

#2,CNTRLA
#24 ,CNTRLA

NOP

Reset

#30,CNTRLB

Reset Channel A

Wait

TMe

MOVB

NOP

MOVB

b
X

This section initializes the 7201 for asynch operation

Send

vector

recognition of

first

character

Stay here while the

occur

interrupts

STATB,-(SP)

This section

determine

the

SR2B

#2 ,CNTRLB

MOVB

Point

wWe

MOVB

Store

the

ISR::

the

condition affects

vector

stack

inspects the Condition Affects vector to
cause

ROR

(SP)

;

BCS

EXT

ROR

(SP)

;

BCS

RCV

the

interrupt

Rotate bit 0 into the carry bit
If this bit was set then the
interrupt was caused by a special
receive condition or an external/
change

status

Rotate bit 1 into the carry bit
If this bit was set then the
interrupt was caused by a received

If neither of the above conditions was
satisfied then the interrupt must have
been caused by the transmitter buffer

character
+

empty

going

XMIT:

RO
RO, #8.
1$
(R2)+,TBUFA

.
H
H
;

Increment the xmit char counter
IF this is the eight char
THEN branch to 18§
ELSE send another char

IDONE

;

and

MOVB

#50,CNTRLA

;

IDONE

request

RBUFA, (R3)+

Store

IDONE

;

and

INC
CMP
BEQ
MOVB

MOVB

RCV::

BR
o
~

’

any)

this

interrupt

return

then

character

return

and continue.

xw)

INC

IDONE:: TST
MOVB

(SP)+
#70,CNTRLA

RTI

+BYTE

RBUF
: :

.BLKB

Increment the
return

counter

and

Fix

;
i

TBUF
¢ ¢

« END

return

reset pending xmit

This program does not take any special action if an
External/Status interrupt or Special Receive Condition
Just note that it occurred (there shouldn’'t be
occurs.

1S:

the

stack

Issue end of interrupt command
and return to main program

101,102,103,104, 105,106,107,110
.

START

SLU2.MAC

This example program for the uPD7201 transfers serial data via
a loopback connector (part #H3022 or 54-16229) between Channel
No ISR is
A's transmit and receive, using the DMA controller.
uPD7201
the
how
show
to
meant
is
it
as
included in this example
should
program
"real-life"
A
and the DTC may work together.
include an ISR which monitors any External or Special Receive
For more information regarding the
condition interrupts.
programming of the DTC please refer to Section 4.3.

After this program has been assembled and linked on the
development machine, use the KUI utility of the KXJ11-CA

Software Toolkit to load the program into the KXJ11-CA. This

program will execute as shown in the following example.

SET

LOAD

EXECUTE

10DT

.TITLE

1001234

EXIT

This verifies that the data was transferred successfully. The
transmit buffer begins at address 1276, and the receive buffer
begins

address

1306.

N
WE

11276/041101
1001300/042103
1001302/043105
1001304/044107
1001306/041101
1001310/042103
1001312/043105
1001314/044107
1001316/000000
ICTRL/C
|

SLUZ2.SAV

Master Mode Register
Command Register

MMREG
CMDREG

==
==

174470
174454

¢+
.+

STATA
RBUFA
CNTRLA
TBUFA
STATB
CNTRLB
TIMREG
TIMERO

==
==
==
==
==
==
==
==

175700
175702
175704
175706
175710
175714
175736
175730

¢+ Channel A status register
+ Channel A receiver
e+ Channel A control register
e+ Channel A transmitter
¢ Channel B status register
¢ Channel B control register
+ Timer control register
; Timer 0 data register

CASTFO0
CAOFO0
CASTF1
CAOF1

==
==
==
==

174446
174442
174444
174440

:
+
.+
e+

Chan
Chan
Chan
Chan

0
0
1
1

Chain Address
Chain Address
Chain Address
Chain Address

Seg/Tag Field
Offset Field
Seg/Tag Field
Offset Field

This section initializes the KXJ11-CA system environment
Disable recognition of

MOV

#TBUF ,R2
#RBUF ,R3

R2 points to the transmit buffer
R3 points to the receive buffer

L X ]

#340

MOV

This section initializes the bit rate generator
MOVB

, TIMREG
#26

7
e

MOVB

#64.,TIMERO

Select timer 0,
3,

mode

low byte only,

binary

This divider selects 9600 bps

This section initializes the 7201 for asynch operation
e

NOP
MOVB

Reset

#30,CNTRLA

#30,CNTRLB

MOVB

#4 ,CNTRLA
#104 ,CNTRLA

CR2A

interface options:

Set

to CR4

operation mode:

asynch mode,

clock

rate =

No parity,
Point

CR3

Point

CRS5

Point

to CRO

Point

to CR1

16x data

Enable receiver,

1 stop bit,

rate

char length =

Enable transmitter, Char length = 8

#20,CNTRLA

MOVB

#1,CNTRLA
#16,CNTRLA

CNTRLA

Reset External/Status Interrupts
Transmit IE, Interrupt on 1lst
received char and issue DMA
request enable condition affects
vector

WO
wWE

MOVB

CLRB
MOVB

MOVB

#5,CNTRLA
#152,CNTRLA

MOVB

#3,CNTRLA
#301,CNTRLA

Setup bus

Point

MOVB

Point

.,
Chan A DMA, RXA>RXB>TXA..
Non-Vectored

MOVB

Reset Channel

Wait for reset to complete

#2,CNTRLA
#25,CNTRLA

Channel A

Wait for reset to complete

MOVB

NOP

MOVB

interrupts

MTPS

¢ ¢
START

section initializes the DMA controller

This

CLRB
MOV

MOV

the

DTC

#0,CASTFO

: Load Chain Address Register Seg/Tag

#0,CASTF1

. Load Chain Address Register Seg/Tag

# LOADO , CAOFO0

Load Chain Address Register Offset

MOV

# LOAD]1 ,CAOF1

Load Chain Address Register Offset

MOVB

#115,MMREG

Load Master Mode Reg to Enable DTC

MOVB

#240,CMDREG

Start Chain Channel 0

MOVB

#241 ,CMDREG

MOV

Reset

CMDREG

Start

OcCcur

Reload Word

CARA,CARB,COPC,CM>

Chain Load Region
« WORD

000000

« WORD

TBUF

TBUFA+1

« WORD

000010

« WORD

000020
000001

000020

« WORD

O
TME
WO
WO
g

« WORD

Y ]

®wme

« WORD

001602

LOAD1:

Stay here while the DMA transfers

=
@

MAIN:

Chain Channel

<Select

Current Address Register A Seg/Tag

Current Address Register A Offset
<This local address 1is the source>

Current Address Register B Seg/Tag

Current Address Register B Offset
<This local address is the destination>

Current Operation Count

Channel Mode Register High
Channel Mode Register Low

{No match conditions, do nothing upon
completion, transfer type = single transfer
CARA = source, byte transfers>

.WORD

000000

-.WORD

RBUF

.WORD

000010

.WORD
.WORD

000000
000001

.WORD

000020
RBUFA+1

001602

LOADO: .WORD
.WORD

O
TMY

BYTE

¢ :
RBUF

+BLKB

« END

START

current Address Register A Seg/Tag
Current Address Register A Offset
{This local address 1is the source>

Current Address Register B Seg/Tag

Current Address Register B Offset

Current Operation Count <Transfer 8 bytes>

: :
TBUF

Reload Word <Select CARA,CARB,COPC,CM>

-Channel Mode Register High
Channel Mode Register Low

<{No match conditions, do nothing upon
completion, transfer type = single transfer
CARA = source, byte transfers>

101,102,103,104,105,106,107,110
10

APPENDIX

MEMORY MAP

A.1

Table

A-1

1lists

all the registers in the KXJ11-CA and specifies

the addresses associated with these registers.

Table A-1

KXJ11-CA Registers

KXJ11-CA Address

17772200-17772216
17772220-17772236
17772240-17772256
17772260-17772276

I Space
Supervisor
Supervisor D Space
Supervisor I Space
Supervisor D Space

17772300-17772316
17772320-17772336
17772340-17772356
17772360-17772376

Kernel
Kernel
Kernel
Kernel

17772516

Memory Management Register 0 (MMR3)

17774400
17774402
17774404
17774406
17774410
17774412
17774414
17774416

DTC CH1 Current B Address Offset
DTC CHO Current B Address Offset
DTC CH1 Base B Address Offset
DTC CHO Base B Address Offset
DTC CH1 Current A Address Offset
DTC CHO Current A Address Offset
DTC CH1 Base A Address Offset
DTC CHO Base A Address Offset

17774440
17774442

DTC CH1 Chain Address Offset
DTC CHO Chain Address Offset

17774420
17774422
17774424
17774426
17774430
17774432
17774434
17774436

17774444
17774446

17774450
17774452

SUMMARY

I
D
I
D

Space
Space
Space
Space

PDRO-PDRY
PDRO-PDR7Y
PARO-PARY
PARO-PAR7

PDRO-PDR7
PDRO-PDRY
PARO-PAR7
PARO-PAR7

DTC CH1 Current B Address Segment/Tag
DTC CHO Current B Address Segment/Tag
DTC CH1 Base B Address Segment/Tag
DTC CHO Base B Address Segment/Tag
DTC CH1 Current A Address Segment/Tag
DTC CHO Current A Address Segment/Tag
DTC CH1 Base A Address Segment/Tag
DTC CHO Base A Address Segment/Tag
DTC CH1 Chain Address Segment/Tag
DTC CHO Chain Address Segment/Tag
DTC CH1 Interrupt Save Register
DTC CHO Interrupt Save Register
A-1

Table A-1
KXJ11-CA Address
-

KXJ11-CA Registers

(Cont)

17774454
17774454
17774456
17774460
17774462
17774464
17774466
17774470

DTC
DTC
DTC
DTC
DTC
DTC
DTC
DTC

CH1 Status Register (Read Only)
Command Register (Write Only)
CHO Status Register
CHl1 Current Operation Count
CHO Current Operation Count
CH1 Base Operation Count
CHO Base Operation Count
Master Mode Register

17774472-1774506

DTC

Reserved

17774510
17774512
17774514
17774516
17774520
17774522
17774524
17774526

DTC
DTC
DTC
DTC
DTC

CH1
CHO
CH1
CHO
CH1

Pattern Register
Pattern Register
Mask Register
Mask Register
Channel Mode Low
DTC CHO Channel Mode Low
DTC CH1 Channel Mode High
DTC CHO Channel Mode High

17774530
17774532
17774534-17774536

DTC CH1 Interrupt Vector
DTC CHO Interrupt Vector
DTC Reserved

17775000

TPRO

17775002

TPR1

17775004
17775006
17775010
17775012
17775014
17775016
17775020
17775022
17775024
17775026
17775030
17775032
17775034
17775036

TPR2
TPR3
TPR4
TPR5
TPR6
TPR7
TPR8
TPR9
TPR1O
TPR11
TPR12
TPR13
TPR14
TPR15

17775700
17775702

SLU2 Channel A Status Register
SLU2 Channel A Receliver

17775704
17775706

SLU2 Channel A Control Register
SLU2 Channel A Transmitter

17775703

17775707

17775710
17775712
17775714
17775716
17775720

SLLU2 Channel A Receiver (when used with DTC)
SLU2 Channel A Transmitter (when used with DTC)
SLU2
SLU2
SLU2
SLU2
SLU2

Channel
Channel
Channel
Channel
Timer 0

B Status Register
B Receliver
B Control Register
B Transmitter
Data Register

Table A-1
KXJ11-CA Address

KXJ11-CA Registers (Cont)
Register

17775722
17775724
17775730
17775732
17775734
17775736

SLU2 Timer 1 Data Register
SLU2 Timer 2 Data Register
SLU2 Timer 0 Data Regilster
SLU2 Timer 1 Data Register
SLU2 Timer 2 Data Register
SLU2 Timer Control Register

17777000
17777002
17777004
17777006
17777010
17777012
17777014
17777016
17777020
17777022
17777024
17777026
17777030

PIO Master Interrupt Control Register
PIO Master Configuration Control Register
PIO Port A Interrupt Vector Register
PIO Port B Interrupt Vector Register
PIO Counter/Timer Interrupt Vector Register
PIO Port C Data Path Polarity Register
PIO Port C Data Direction Register
PIO Port C Special I/0 Control Register
PIO Port A Command and Status Register
PIO Port B Command and Status Register
PIO Counter/Timer 1 Command and Status Register
PIO Counter/Timer 2 Command and Status Register
PIO Counter/Timer 3 Command and Status Register

17777032

PIO Port A Data Register

17777035

PIO Port A Data Register (when used with DTC)
PIO Port B Data Register
PIO Port B Data Register (when used with DTC)

17777040
17777042
17777044
17777046
17777050
17777052
17777054
17777056
17777060
17777062
17777064
17777066
17777070
17777072
17777074

PIO Counter/Timer 1 Current Count (MSB)
PIO Counter/Timer 1 Current Count (LSB)
PIO Counter/Timer 2 Current Count (MSB)
PIO Counter/Timer 2 Current Count (LSB)
PIO Counter/Timer 3 Current Count (MSB)
PIO Counter/Timer 3 Current Count (LSB)
PIO Counter/Timer 1 Time Constant (MSB)
PIO Counter/Timer 1 Time Constant (LSB)
PIO Counter/Timer 2 Time Constant (MSB)
PIO Counter/Timer 2 Time Constant (LSB)
PIO Counter/Timer 3 Time Constant (MSB)
PIO Counter/Timer 3 Time Constant (LSB)
PIO Counter/Timer 1 Mode Specification
PIO Counter/Timer 2 Mode Specification
PIO Counter/Timer 3 Mode Specification

17777033
17777034

17777036

17777076

17777100
17777102
17777104
17777106
17777110

17777112
17777114
17777116
17777120

PIO Port C Data Register

PIO Current Vector Register

PIO Port A Mode Specification Register
PIO Port A Handshake Specification Register
PIO Port A Data Path Polarity Register
PIO Port A Data Direction Register
PIO Port A Special I/O Control Register

PIO Port A Pattern Polarity Register (PPR)
PIO Port A Pattern Transition Register (PTR)
PIO Port A Pattern Mask Register (PMR)
PIO Port B Mode Specification Register

Table A-1
KXJ11-CA Address

17777122
17777124
17777126
17777130
17777132

17777134
17777136

17777140

17777520
17777522
17777524
17777526
17777530

17777532
17777534
17777536
17777540
17777560
17777562
17777564
17777566

KXJ11-CA Registers

(Cont)

PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO

Port B Handshake Specification Register
Port B Data Path Polarity Registers
Port B Data Direction Registers
Port B Special I/0O Control Registers
Port B Pattern Polarity Registers (PPR)
Port B Pattern Transition Registers (PTR)
Port B Pattern Mask Register (PMR)
I/0 Buffer Control Register

KXJ1l Control/Status Register A (KXJCSRA)
KXJ1ll Control/Status Register B (KXJCSRB)
KXJ11l Control/Status Register C (KXJCSRC)
KXJ11l Control/Status Register E (KXJCSRE)
KXJ1l1l Control/Status Register D (KXJCSRD)
O-Bus Interrupt Register (QIR)
KXJ11l Control/Status Register F (KXJCSRF)
KXJ1l Control/Status Register H (KXJCSRH)
KXJ1l1l Control/Status Register J (KXJCSRJ)
SLUl Receiver Control/Status Register (RCSR)
SLUl Receiver Buffer Register (RBUF)
SLUl Transmitter Control/Status Register
SLU]l Transmitter Buffer Register (XBUF)

17777572
17777574
17777576

Memory Management Register 0
Memory Management Register 1
Memory Management Register 2

17777600-17777616
17777620-17777636

User
User

I
D

Space
Space

PDRO-PDR7
PDRO-PDR7

17777640-17777656
17777660~17777676

User
User

I
D

Space
Space

PARO-PAR7
PARO-PAR7Y

17777750

Maintenance

17777766

CPU

17777772

PIR

17777776

Processor Status Word

Error

(PSW)

(MMRO)
(MMR1)
(MMR2)

(XCSR)

APPENDIX

KXJ11-CA/KXT11-CA DIFFERENCES

B;l

Table
the

DIFFERENCES BETWEEN THE KXJ11-CA AND THE KXT11-CA

B-1 summarizes the differences

between

KXJ11-CA

the

and

KXT11-CA.

Table B-1

KXJ11-CA/KXT11-CA Differences
KXJ11-CA

KXT11-CA

Memory management

Yes

PROM

RAM

512

RAM parity

Yes

Shared memory

Yes

warm floating-point

Yes

NoO

Maintenance Register

Yes

NoO

DTC

vectors

TPRO (control mode)

TPR1

kilobytes

214

kilobytes

and 220

kilobytes

8-32

32-48

110

kilobytes

and

TPR0<14>
TPR0O<9>
TPRO<8>
TPROLK7>
TPROK6>

Hard reset
Execute program

Unused
Unused
Unused
Unused
Unused

TPR1<13>

Unused

Trap to
disable

TPR1<12>

Non-existent memory e€rror

Unused

TPR1<11>

Parity

TPR1<10>

Unused

Disable shared memory
Show shared memory
Enable shared memory

error

114

SP NXM test

flag

Power-up with

battery backup

Table

KXJ11-CA/KXT11-CA Differences

B-1

(Cont)

KXJ11-CA

TPR1<9>

KXT11-CA

Unused

Power-up without
battery

backup

TPR1<7>

Unused

O-Bus ODT

flag

TPR1<6>

Unused

Serial ODT

TPR1<4>

Firmware not handling
special interrupts

ODT on HALT
instruction

TPR1<3>

Unused

Stack

CSRBK7:4>
CSRB<3:1>

Writeable
Base address
size jumpers

flag

error

flag

CSRB

and bus

jumpers

CSRDK15>

PWR

CSRE

No operation

Controls PIO

CSRF
CSRH

Yes
Yes

HALT

instruction

Read-only
Memory mapping

NXM

‘

If in kernel mode,
enters serial ODT

Restart

Stack violations and
NXM references in
kernel mode

Fatal

error

Not

Exceptions

Caused by the

assertion

HALT

runtime

applicable

instruction

of BHALT or BINIT, th e
deassertion of BPOK, or
the writing of TPRO by
the arbiter
Battery

backup

Firmware

stack

Hardware

Arbiter

reset

NOP

command

Yes

128 kilobytes at top of
kernel stack for
native firmware scrat ch

Separate

area

user

Caused by power-up oOr
by setting TPR0<K14>

Caused

Ignored

Reserved

RAM

I/0 page

transparent

power-up

KXJ11-CA/KXT11-CA Differences (Cont)

Table B-1

KXT11-CA

KXJ11-CA

in KXJ1l1-CA are

Boot/self-test switch

Switch positions 0-6

ID Switch

Switch position changes

identical to switch positions 0-6 1in
KXT11-CA. Switch positions 7-15 are unique.

made while the board is’
powered up take effect
only after a hardware
reset.

position

Switch

changes made
while the board
is powered up
immediately
affect QO-Bus
address.

Console

ODT

Firmware

Microcode

All

alpha characters

must

upper

case

R and
upper

S may be
oOr lower

case

last memory

(close

location or register and
open preceding) not

Supported

supported

Examining a range of
locations not supported

Supported

Not

well

supported

an R

Autobaud not supported

Supported

All addresses are 22 bits

All

addresses

are

Two register sets and
three stack pointers

Not

applicable

LEDs

Indeterminate

bits

LEDs in fixed
state while in
ODT

Software control

of SLU1l

baud rate

Selectable by a bit
in KXJCSRJ

Jumper

selectable

APPENDIX

USER (P)ROM PROGRAMMING INFORMATION

C.1l

This

INTRODUCTION

contains

appendix

applications

in PROM or ROM.

the

guidelines

for

installing

wuser

E23
There are two sockets for PROM on the KXJ11-CA, E22 andns E23.
low
the
contai
E22
and
word,
PDP-11
a
contains the high byte of
16
e
provid
to
PROMS
8K
X
8
two
with
d
byte. The KXJ11-CA is supplie
16K,
X
8
odate
accomm
also
can
CA
KXJ11kilobyte of PROM space. The
64 KB of
or 8 X 32K PROMs in these sockets to provide 32 KB and KXJ11CA
the
with
ed
suppli
PROMs
PROM space respectively. The
of
ts
consis
e
firmwar
native
The
code.
e
contain the native firmwar
first
is
power
when
ed
execut
1is
initialization code, which
re
applied. ©Under <certain reset conditions, the native firmwaand
TPRO
from
ed
receiv
ds
comman
ret
contains routines that interp
handle non-maskable interrupts and self-test programs.

Since

these

applications
firmware.

The
two

are

PROM

only

PROM

sites

the

module,

user

must reside in the same PROM as the native

native firmware requires 16 kilobytes of PROM. Either of the
larger parts may be selected to provide 16 kilobytes or 48

kilobytes of user

C.2

the

(P)ROM.

TRANSPORTING NATIVE FIRMWARE

KXJ11-CA with
If users want to replace the PROMs supplied with thenative
firmware
the
retain
also
and
PROMs of a larger size,
in the
code
re
firmwa
the
er
transf
functions, then they must
Digital-supplied PROMs to the new PROMs.

The requirements and procedure for doing this are as follows:

C.2.1

Requirements

C.2.1.1

Hardware

programmer

that

used by VAX

DECprom.

operating
PROM

protocol

DATA
DATA
DATA
DATA

system,

I/0
I/0O
I/0
I/O

Model
Model
Model
Model

Any

spare,

and

VAX

the

terminal port

and cable

the

and socket

to connect

the VAX/VMS operating

DECprom Utility

Procedure

Remove

transfer

are:

PROM programmer.

the VAX DECprom User's Guide,

C.2.2

configurations.

to the command and data

Included

Software —-- Version 3.2 or later of

system.

See

RLO2

such
as programming modules
PROMs being used.

dedicated VAX/VMS

communicate with

C.2.1.2

adheres

dual

19
29A
121A
171

Any
necessary
hardware,
adapters, specific to the
A

VAX-11 system supported by the VAX/VMS

except VAX-11/730

PROMs

Chapter 2,

for further details.

that

are

supplied with the KXJ11-CA

from their

sockets.

Ce2.2.1
Setting
Parameters
-- DECprom requires PROM parameters,
such
as
PROM
length,
word
width,
unprogrammed state, and the
pinout
code,
to
be set whenever data is to be transferred to or
from PROM.

Invoking

This

done

the PARAMETERS

printed

CURRENT

PARAMETER VALUES

PROM

1)
2)
3)
4)
5)
6)

the

using

the

PARAMETERS

command caused

the

command.

following display

to be

terminal:

Parameters

FAMILY AND PINOUT CODE (4 HEX characters) ceceececcsccococsocs
LENGTH (power of 2, 2 => 1073741824) cccccescocccccsccses 16384
WIDTH (1 => 8) ceceecoscoocososcosososcssososscsscsossoscsocsscssosossssses O
UNPROGRAMMED STATE (0/1) ccooecoccccocoscsocscscscscsscscscoscsossoscs 1
COLUMN POSITION IN PROM SET (0 through WIDTH-1l) .cccccecesecesse O
PROGRAMMER RAM BUFFER SIZE (power of 2, 2 -> 65536) ..... 16384

TARGET

Parameters

7) WORD SIZE IN BITS (1 => 128) cccoococoscccscocscocsccocccscscsccses 16O
8) NUMBER OF BITS PER ADDRESS (1 -> word SizZ€) cecccceccocccoscses 8
9) INVERTED DATA (YES/NO) «ccecoccococsccscscsosscsscscsessoscsscssss NO
10) INVERTED ADDRESS (YES/NO) cccoccoocsoccoosccscssscsscsssscsccses NO

TYPE THE NUMBER TO CHANGE PARAMETER (1/2/3..../EXIT) <EXIT>:

The above parameters would be correct to read the contents of the
native firmware in the 8 x 8KB PROM except for item 1. To change
the parameter of item 1; type the number 1 at the colon. The
terminal will display the following:

FAMILY AND PINOUT CODE (4 HEX characters) <>:

The

Family and pinout code depends on the type of PROM programmer

use. Consult the DECprom manual and the PROM Programmer manual

for more details.

utility

LIST

command, create an unformatted

Using

the

DECprom

Using

the

DECprom utility PROGRAM command, transfer the contents

memory image file (SAV type)

on the host system.

of the file created by the list command to the new PROM.

Example: The user wants to replace the 8 X 8K PROMs supplied with
the KXJ11-CA with 8 X 32K PROMs, but still retain the native
firmware functionality. The wuser must copy the native firmware
from the 8 x 8 K PROMs into an unformatted memory image file on
the host VAX/VMS system, using the DECprom LIST command.

The user removes the PROMs from their sockets on the KXJ11-CA. The

user installs the low byte PROM into a compatible PROM programmer
that is connected to the host VAX/VMS system.

The

user

then

invokes

the

DECprom utility on the host VAX/VMS

system.

COMMAND

<HELP>:

LIST

OUTPUT SPECIFICATION

{TT:>:

FIRM.SAV

THE LIST FORMAT IS (AHEX/AOCTAL/ABINARY/BINARY) <AOCTAL>: BINARY
<0>: O
TARGET START ADDRESS
37776
<0>:
ADDRESS
STOP
TARGET

PROM START ADDRESS (0 -> LENGTH-1)

<0>: O

ADDRESS [ 20000 : 37776 1, BIT [ 0 : 7 1, PROM COUNT IS 1
DO YOU WISH TO SKIP THIS PROM (YES/NO) <NO>: NO

MOUNT PROM AND PRESS <RETURN> TO PROCEED:

ADDRESS [ 20000 : 37776 1, BIT [ 8 : 15 ], PROM COUNT IS 2
DO YOU WISH TO SKIP THIS PROM (YES/NO) <NO>: NO

(*** The user must now install the high byte prom**¥*)
MOUNT PROM AND PRESS <RETURN> TO PROCEED:

TARGET START ADDRESS (Target word boundary) <0>: EXIT
COMMAND

The

<LIST>:

native

firmware

has now been successfully transferred to an

unformatted memory file in the host VAX/VMS system.

1into the
firmware
native
the
blast
to
now wishes
user
The
change
must
user
the
so,
do
To
PROMs.
32K
X
8
user-supplied

and change the PROM programmer
PROGRAM command, the user
DECprom
the
using
Then,
etc.
socket,
created on the host VAX
file
the
from
code
the firmware
transfers

parameters

the

new

COMMAND
INPUT

for the new size PROMs,

PROM.

<HELP>:

FILE

<>:

OLD FILE NAME

PROGRAM
FIRM.SAV

(NONE)

<>:

NONE

FILE FORMAT (EXE/LDA/MIM/SAV/TSK/HEX/MOS) <MIM>: SAV

TARGET START ADDRESS (Target word boundary) <0>: O
TARGET STOP ADDRESS (Target word boundary) <0>: 37776
PROM START ADDRESS (0 =-> LENGTH-1) <0>: 60000

WRITE DATA TO FILE (YES/NO) <NO>: NO
ARE BLANK PROMS BEING USED (YES/NO) <YES>

ADDRESS[ 60000 : 77776 1, BIT
DO YOU WISH TO SKIP THIS PROM
MOUNT

PROM AND PRESS

[ 0 ¢« 7 ], PROM COUNT IS 1
(YES/NO) <NO>: NO

TO PROCEED:

TO PROCEED:

$PROM-S-PROGRAMMED, PROM HAS SUCCESSFULLY BEEN PROGRAMMED
ADDRESS[ 60000 : 77776 1, BIT [ 8 ¢ 15 ], PROM COUNT IS 2
DO YOU WISH TO SKIP THIS PROM (YES/NO) <NO>: NO
MOUNT PROM AND PRESS

S PROM-S-PROGRAMMED,

COMMAND

PROM HAS SUCCESSFULLY BEEN PROGRAMMED

<PROGRAM>:

Continuing

the same example,

with

the user now wishes to program

quarters of the 2 X 32K
three
first
the
into
application
his
map that the last
output
linker
The user determines from a
PROMs.
address
of
the
application is 136006 octal. The DECprom session
begins

COMMAND
INPUT

OLD

burning

<HELP>:

FILE

<>:

FILE NAME

the

user

code:

PROGRAM
MYROM.SAV

(NONE)

<>:

NONE

FILE FORMAT (EXE/LDA/MIM/SAV/TSK/HEX/MOS) <MIM>: SAV
TARGET START ADDRESS (Target word boundary) <0>: O
TARGET STOP ADDRESS (Target word boundary) <0>:137006

PROM START ADDRESS (0 -> LENGTH-1) <0>: O
WRITE DATA TO FILE (YES/NO) <NO>: NO
ARE BLANK PROMS BEING USED (YES/NO) <NO>
ADDRESS[ 00000 : 57003 ], BIT [ O ¢+ 7 ], PROM COUNT IS

DO YOU WISH TO SKIP THIS PROM

(YES/NO)

<NO>:

MOUNT PROM AND PRESS <RETURN> TO PROCEED:
SPROM-S-PROGRAMMED, PROM HAS SUCCESSFULLY

BEEN PROGRAMMED

MOUNT PROM AND PRESS <RETURN> TO PROCEED:
SPROM-S-PROGRAMMED, PROM HAS SUCCESSFULLY

BEEN PROGRAMMED

ADDRESS[ 00000 : 57003 ], BIT
DO YOU WISH TO SKIP THIS PROM

COMMAND

<PROGRAM>:

[ 8 ¢ 15
(YES/NO)

], PROM COUNT IS
<NO>: NO

The

following

steps

used

then

are

calculate and burn the

checksum:

COMMAND

<HELP>:

LIST

OUTPUT SPECIFICATION <TT:>:

MYROM.CC

THE LIST FORMAT IS (AHEX/AOCTAL/ABINARY/BINARY) <BINARY>: BINARY
TARGET START ADDRESS (Target word boundary) <0>: O
TARGET STOP ADDRESS (Target word boundary) <177776>: 137774
PROM START ADDRESS (0 -> LENGTH-1)

<0>: O

ADDRESS[ O : 137774 1, BIT[ 0 : 7 ], PROM count is 1
DO YOU WISH TO SKIP THIS PROM (YES/NO)

<NO>: NO

MOUNT PROM AND PRESS <RETURN> TO PROCEED:

ADDRESS[ O : 137774 1, BIT[ 8 : 15 1, PROM count is 2

DO YOU WISH TO SKIP THIS PROM (YES/NO)

<KNO>: NO

MOUNT PROM AND PRESS <RETURN> TO PROCEED:
COMMAND <LIST>: CALC CHECK
INPUT FILE <>: MYROM.CC

FILE FORMAT (EXE/LDA/MIM/SAV/TSK/HEX/MOS) <SAV>: SAV
TARGET START ADDRESS (Target word boundary) <0>: 0
TARGET STOP ADDRESS (Target word boundary) <137774>: 137774
PROM START ADDRESS (0 -> LENGTH-1) <0>: O
CHECKSUM BUFFER START LOCATION (1 --> 128) <1>: 1
COMMAND <CALC_ CHECKSUM>:

STORE_CHECK

CHECKSUM BUFFER START LOCATION (1 --> 128) <1>: 1
CHECKSUM COUNT (1 --> 128)

<1>:

PROM START ADDRESS (0 => LENGTH-1) <0>: 57777
ADDRESS[ 0 : 0 ], BIT[ O : 7 1, PROM count is 1
DO YOU WISH TO SKIP THIS PROM (YES/NO) <NO>: NO
MOUNT PROM AND PRESS <RETURN> TO PROCEED:

SPROM-S-PROGRAMMED, PROM HAS SUCCESSFULLY BEEN PROGRAMMED
ADDRESS[ O : 0 1, BIT[ 8 : 15 ], PROM count is 2
DO YOU WISH TO SKIP THIS PROM (YES/NO) <NO>: NO
MOUNT PROM AND PRESS <RETURN> TO PROCEED:

S PROM-S-PROGRAMMED, PROM HAS SUCCESSFULLY BEEN PROGRAMMED

COMMAND <STORE CHECKSUM>:
C.2.3

EXIT

PROM MAP

Figures C-1, C-2, and C-3 show how the firmware is physically
mapped into the three sizes of PROMs that can be used in the
KXJ11-CA PROM sites. On the left is the physical address of the
PROM. On the right is the physical address(es) in the KXJ11-CA at
which PROM will be visible. Multiple addresses are shown 1in the
cases of the two smaller PROMs because of wraparound that occurs
with KXJ11CA address decode.
C.2.4

CHECKSUM

The checksum for the user code is optional. If users require a
checksum for their PROM code, the DECprom utility allows them to
calculate it and store it. The user checksum must reside in the
For 8 X 16K PROMs the checksum is at
last user PROM 1location.
of fset 17777 1in each PROM, and for 8 X 32K PROMs, it's at offset
57777,

2 X 8 KB PROMs

OFFSET WITHIN

ADDRESS(ES) IN KXJ11-CA

EACH PROM

17777

00000

FIRMWARE CHECKSUM

2177776,2137776
2077776,2037776

START OF NATIVE FIRMWARE

2140000,2100000
2040000, 2000000
MR-1086-1233

Figure

C-1

8KB

PROM

OFFSET WITHIN
EACH PROM

Map

ADDRESS(ES) IN KXJ11-CA

37777

FIRMWARE CHECKSUM

START OF NATIVE FIRMWARE

20000

USER CHECKSUM

17777

2177776,2077776

2140000, 2040000
2137776,2037776

16 KB OF PROM SPACE FOR

USER APPLICATIONS

00000

2100000, 2000000
MR-1086-1232

Figure

C-2

16KB

PROM Map

2 X 32 KB PROMx

OFFSET WITHIN
EACH PROM

ADDRESS(ES) IN KXJ11-CA

77777

FIRMWARE CHECKSUM

START OF NATIVE FIRMWARE

60000

USER CHECKSUM

57777

48KB OF PROM SPACE FOR
USER APPLICATIONS

00000

2177777

2140000
2137776

2000000
MR-1086-1234

Figure

C-3

32KB

C-6

PROM Map

Checksum

C.2.4.1

Algorithm -- The following algorithm is used to

calculate the PROM checksum.
CHECKSUM = 0

FOR I = number of PROM addresses to be checksumed DO
CHECKSUM = CHECKSUM + contents of address

(high order carry from addition is discarded)

ONE_BIT
ATE
LEFT
CHECKSUM = ROT

....

(bit0 -> bitl, bitl -> bit2,

,bitl5 -> bit0 )

in MACRO-11:
CLR

CHECKSUM

# <ENDUSR-BGNUSR-2>/2,R0

;NUMBER OF USER PROM WORDS

MOV

#BGNUSR,R1

s START OF USER PROM

MOV

1$:

2S:

Note
set,

ADD
CLC
BPL
SEC
ROL

SOB

that

not as

(R1)+,CHECKSUM

CHECKSUM
RO,1$

MINUS ONE WORD FOR CHECKSUM

+ADD ADDR CONTENTS TO CHECKSUM
s DISCARD CARRY, SET CARRY = 0
sBRANCH IF BIT 15 OF CS = 0
;sCARRY = BIT 15 =1
: ROTATE CHECKSUM LEFT 1 BIT
; LOOP CONTROL

DECprom calculates the checksum for the PROM as a PROM
individual PROMs.

APPENDIX

BUILDING AN APPLICATION

APPLICATION BUILDING

D.1

When vyou build an application for the KXJ11-CA, you must specify
certain switches and options. Since the application runs on the
KXJ11-CA independent of the operating system environment, there is
no need for a header, stack area, or memory management. Therefore,

when

building an application, the negated header switch (/-HD) 1is

attached

This switch suppresses
the image file specification.

the header within the image. To suppress memory management, the
negated memory management switch (/-MM) 1is attached to the image

file

will

specification.
run

hardware.

This

system

switch

that

does

specifies that the application
not

have
|

memory management

To suppress the stack area in the task builder command sequence
If you need to
during option input, STACK=0 should be used.

specify a stack with your application, you should do so within the

Since the KXJ11-CA application starts up as
application itself.
the application is initially bound to physical memory.
unmapped,
The application must be installed at the same memory address for
which it was built. Therefore, during option input, use the PAR
ption to specify the base address and length of an application.

The

named

following

examples build a 24 kilobyte application code file

APPCODE.

MCR Example:
MCR>

TKB<KRET>

TKB> APPCODE/-HD/-MM=APPCODE<KRET>
TKB> /<RET>
Enter Options:
TKB>

TKB>
TKB>

STACK=0<RET>

PAR=DUMCODE:0:60000<RET>
//<RET>

- DCL Example:

DCL> LINK APPCODE/NOHEADER/NOMEMORY_MANAGEMENT/OPTIONS<RET>

Options?

STACK=0<RET>

Options? PAR=DUMCODE:0:60000<RET>

INDEX

—A-

Application building, D-1
Arbiter, 1-4, 3-3, 3-4

Arbiter/TPR communication protocol,

3-4

=B=

Backplane installation,
Block diagram, 3-1, 3-2

2-25

Boot/Selftest switch, 2-4 through 2-9
BREAK enable jumper, 2-14

=C=

Charge

pump,

Connectors

O-Bus,

J1l
J2

3-34

2-26,

2-27

(SLU2 channel A),
(SLU2 channel B),

2-30,
2-30,

2-31
2-31

J3 (SLul), 2-30, 2-31
J4 (PIO), 2-29
Loopback, 2-34, 2-35

Console asynchronous serial I/0, 3-34, also see SLU1
interface

(J3),

2-30

Control/Status Registers (CSRs), Host Side, also see KXJ11
Control/Status Registers
TPRO,

3-4

TPR1,
TPR2,

3-13,
3-14,
3-15

TPR3,

3-14
3-15

TPR4 through TPR15, 3-15
CPU Error Register, 3-31

Index-1

=D=-=

Diagnostic testing with XXDP+,
DMA transfer controller (DTC),
command

summary,

2-38,
3-19,

2-39
4-1 through

4-35

4-5

data transfer, 4-21
initializing, 4-18

through

4-22

programming examples, 4-23 through
reload word, 4-19
registers, 4-2 through 4-21
Base Address Registers, 4-8

4-35

Chain Address Register, 4-8 through 4-9, 4-19
Channel Mode Register, 4-15 through 4-18
Command Register, 4-4
Current Address Registers, 4-7 through 4-8

Current and Base Operation Count Registers,

Interrupt Save Register, 4-10, 4-11
Interrupt Vector Register, 4-10, 4-11
Master Mode Register, 4-6
Pattern and Mask Registers, 4-14
Status Register, 4-11 through 4-13
termination options, 4-22
DMA request jumpers, 2-12

Edge

connector pin

assignments,

2-26

Firmware usage

considerations,

3-18

-H-=

HALT option selection

jumper,

2-15

ID switch, 2-10 through 2-12, 3-19
Interrupts, 3-35 through 3-39
from KXJ11-CA to QO-Bus, 3-36
from Q-Bus to KXJ11-CA, 3-36
local,

3-37

special, 3-38
IOP mode, 1-3

-J-

J-11

microprocessor,

3-1

Index-2

through

2-28

4-13,

4-14

KXJ11l
KXJ11l
KXJ11l
KXJ11l
KXJ11l
KXJ11l
KXJ1l

Control/Status
Control/Status
Control/Status
Control/Status
Control/Status
Control/Status
Control/Status

Registers
Register
Register
Register
Register
Register
Register

QD "MEOoOQm
P

=
=K

3-20 through 3-29
(KXJCSRA), 3-20, 6-7
(KXJCSRA), 3-21

through 3-26

(KXJCSRA),

3-23

(KXJCSRA),

3-26,

3-47

(KXJCSRA), 3-27,
KXJ11l Control/Status Register
(KXJCSRA), 3-28
Register
tus
Control/Sta
KXJ1l
through B-3
B-1
s,
difference
KXT11-CA
KXJ11-CA/

3-47

-],-

LEDs,

2-36

through 2-37

Loopback connectors,

2-34 through 2-35

M-

Maintenance Register,

Memory
Memory
Memory
Memory
Memory
Memory

3-30

management, 3-42 through 3-47
Management Register 0 (MMRO), 3-44
Management Register 1 (MMR1), 3-46
Management Register 2 (MMR2), 3-46
Management Register 3 (MMR3), 3-46
map summary, A-1 through A-4

Multiprotocol serial controller, 6-6, also see SLU2
=P

Page Address Registers

(PARs),

3-43

Page Descriptor Registers (PDRs), 3-43, 3-44
Parallel I/O0 (PIO), 3-34, 5-1 through 5-44
interface

(J4),

programming examples,

5-27 through 5-44

registers, 5-2 through 5-21
Current Vector Register, 5-20
Data Direction Registers, 5-11

Data Path Polarity Registers, 5-10
Interrupt Vector Register, 5-19
I1/0 Buffer Control Register, 5-20
Master Configuration Control Register, 5-4
Master Interrupt Control Register, 5-3
Pattern Polarity Registers, 5-12
5-13
Pattern Transition Registers,

Pattern Mask Registers,

5-13

PIO Counter/Timer Command and Status, 5-16
PIO Counter/Timer Current Count, 5-18

PIO Counter/Timer Mode Specification, 5-14 through 5-16
>I0 Counter/Timer Time Constant,

5-18

Port Command and Status Registers, 5-8 through 5-10

Port Data Registers,

5-13

Index-3

Port Handshake Specification Registers, 5-7, 5-8
Port Mode Specification Registers, 5-5 through 5-7
Special I/O Control Registers, 5-11, 5-12
Power supply considerations, 2-25
Power-Up option selection jumper, 2-16
Processor Status Word (PSW), 3-32
Program Interrupt Request (PIRQ) Register, 3-31
PROM addressing jumper, 2-17

PROM

and

firmware

control,

3-16

through 3-17

_Q_

O-Bus
O-Bus
Q-Bus
O-Bus

base address selection jumper,
1interface, 3-35
Interrupt Register (QIR), 3-29
size jumpers, 2-9

2-10,

2-11

=R=

RAM,

3-1, 3-46, 3-47
Real-time clock interrupt
Resets, 3-39 through 3-42
hardware, 3-41, 3-42
software, 3-39, 3-40

-G -

jumpers,

2-24

Shared memory, 3-47 through
considerations, 3-53

3-53

enabling

and disabling, 3-52,
3-48 through 3-51
organization, 3-48

3-53

examples,

SLU1
baud

rate

jumpers,

2-18,

2-19

receiver jumper, 2-20
registers, 6-1 through

6-5
Receiver Buffer Register, 6-3
Receiver Control/Status Register, 6-2
Transmitter Buffer Register, 6-4
Transmitter Control/Status Register, 6-4
transmitter jumpers, 2-19
SLU2

channel

channel
channel

B
B

receiver

jumpers, 2-21
receiver jumpers, 2-23
transmitter jumpers, 2-22

programming examples, 6-30 through
registers, 6-7 through 6-30

Control
Control
Control
Control
Control

6-37

0, 6-14 through 6-16
1, 6-17, 6-18
2 - Channel A, 6-18,
2 - Channel B, 6-19
3, 6-20, 6-21

Index-4

6-19

Control Register 4,

Control Register 5,

6-21,

6-22

6-22 through 6-24

6-24
6-24, 6-25
7,
Register
Control
Register A, 3-20,
Status
KXJ11l Control/
and B, 6-29
A
s
Register
Receiver
through 6-27
6-25
0,
Register
Status
6-28
6-27,
1,
Status Register
6-29
2,
Status Register
Timer Control Register, 6-10, 6-11
Timer Data Register, 6-12, 6-13
Transmitter Registers A and B, 6-30
Control Register 6,

Specifications, 1-4
Standalone mode, 1-3

Synchronous/asynchronous serial I/0, 3-34
interfaces (J1 and J2), 2-30 through 2-34
=T=

Terminology, 1-4, 1-5
TPRO, 3-4 through 3-13
as a control register,

3-5

as a Q0-Bus ODT register,

as
TPR1,
TPR2,

a test register,
3-13, 3-14

TPR3,

3-15

3-11,

3-14

3-9,

3-10

a test result register,

3-9,

3-10

file,

3-3

as a test result register,
as

TPR4

3-12

3-7

through TPR15,

Two-Port Register

3-15

(TPR)

...U-

User

(P)ROM programming, C-1 through C-7

—W=-=

Wake-up circuit,

3-19

Index-=5

-}‘I
-

Digital Equipment Corporation ® Marlboro, MA

01752