Digital PDFs

XX-A8E51-57

1975

40 pages

Original

1.2MB

Document:	IMP11-A PDP-11 Host to IMP Interface Feb19
Order Number:	XX-A8E51-57
Revision:	000
Pages:	40
Original Filename:	http://bitsavers.org/pdf/dec/unibus/IMP11-A_PDP-11_Host_to_IMP_Interface_Feb1975.pdf

OCR Text

IMP I I-A
PDP-II HOST TO IMP
FULL DU?LEX NPR IUTERFACE

•

COMPUTER TYPE

DRAWING seT NO.

PDP-II

7010678-0-0

PROGRAM NO.

DOCUMENT NO.

DECSPEC-ll-AYNADB

CSS-MO-F-3.3-2u

..
~

-.:

DATE

FEERUARY 1975

•

..
,

TABLE OP CONTENTS

SECTION 1
i~

GENERAL

1.1

GENERAL DESCRIPTION

1.2

OPERATION

1.3

SPECIFICATIONS

1.4

AVAILABILITY

1-1
1-1
1-2
1-2

SECTION 2
INSTALLATION
2.1

SITE CONSIDERATIONS

2·.2

CABLES

2.2.1

Unibus Cables

2-1

2.2.2

Signal Cable

2-1

2.2.3

Internal Cabling

2-5

2.3

GROUNDING

2.4

INITIAL OPERATION

2-1
2-1

2.4.1

Acceptance Test

2.5

2-5
2-5

2-5

LITERATURE

2-6

HARDWARE REGISTERS

3-1

Transmit word count Register
(TXWCR) - 172410

3-1

3.1.2

Transmit Bus Address Register
(TXBAR) - 172412

3-2

3.1.3

Transmit Command/Status
Register (TXCSR) - 172414

3-2

3.1.3.1

ERROR (Bit-IS)

3.1.3.2

NEX

(Bit-14)

3-3

3.1.3.3

ATTN (Bit-I3)

3-4

SECTION 3
OPERATION AND PROGRAMMING
3.1
;

3 1 .1

3-3

..,

3.1.3.4

MAINT (Bit-12)

3-4

3.1.3.5

Bits 9. 10, and 11

3-4

,-".1.3.6

(Bit-8)

3-4

3.1.3.7

READY (Bit-7)

3-4

3.1.3.8

IE (Bit-6)

3-4

3.1.3.9

XBAI7. XBA16 (Bits 5 & 4)

3-5

3.1.3.10

Bit 3

3-5

3.1.3.-11

ENABLE LAST BIT (Bit 2)

03-5

3 .1.3.12

TX Clear status (Bit 1)

3-5

3.1.3.13

GO (Bit-O)

3-5

3.1.4

Transmit Data Buffer
Register (TXDBR) - 172416

3-6

3.1.5

Receive Word Count
Register (RXWCR) - 172430

3-6

3.1.6

Receive Bus Address
Register (RXBAR) - 172432

3-6

..........., 1.7

Receive comnand/StatuSo ~
Register (RXCSR) - 172434

3-6

3.1.7.1

ERROR (Bit-IS)

3-6

3.1.7.2

NEX (Bit-14)

3-7

3.1.7.3

ATTN (Bit-13)

3-7

3.1.7.4

MAINT (Bit-12)

3-7

3.1.7.5

HOST READY (Bit-II)

3-8

3.1.7.6

IMP NOT READY (Bit-l0)

3-8

3.1.7.7

READY LINE ERROR (Bit 9)

3-S

3.1.7.S

CYCLE (Bit-8)

3-8

3.1.7.9

READY

CDi t-7)

3-S

3.1.7.10

3.1.7.11

XB17, XB16 (Bits 5 and 4)

3-S

RX WRITE ENABLE (Bit-3)

3-9

HOST READY (Bit-2)

3-9

3.1.7.13

CYCLE

(Bi t-G)

3-8

,f·

·~.I. 7.14

RX CLEAR STATUS (Bit-I)

3-9

3.1.7.15

GO (Bit-O)

3-9

3.1.8

Data Buffer Register
(RXDBR) Receive - 172436

3-9

3.2

INDICATORS

3-9

3.3

PROORAMMING EXAMPLE

3-10

4.1

GENERAL

4-1

4.2

INTERFACE LEVELS

4-3

SECTION 4
THEORY OF OPERATION

I~·
.~

4.3

TRANSMIT LOGIC

4-3

- i~
~

,,',

4.4

4.5

RECEIVE LOGIC

4-5

DR-lIB LOGIC

4-6

IMP-ll/DR11B SIGNAL NAMES

4-7

GENERAL

5-1

MODULES

6-1

SECTION 5
MAINTENANCE
5.1

SECTION 6
SPARE PARTS
6.1

APPENDIX A
DEVICE DIAGNOSTIC PROGRAM DESCRIPTION

....

A.l

ABSTRACT

A-l

;'.2

LOADING PROCEDURE

A-l

>\.3

LOADING PROCEDURE

A-2

;..4

STARTING PROCEDURE

A-2

-\.5

ERRORS

A-2

I'
L
!ir

:" APPENDIX B

SHIPPING LIST

B.1

I
I

I-

EQUIPMENT FURNISHED

B-1

...

r~----~----------.P-~-_

----_agl~pp----~,~~*-_.u1~.(~7~~._.~a~

___

_____

_____=_'~Mm~~._.~.-a_'~'

~_._.A~~~

__. _____

-,~

'i;

omputer
pecial

ystems
9 4

ection 3.3-20

IMP 11-A
PDP-11 HOST TO IMP FULL DUPLEX NPR INTERFACE
1. 1 GENERAL DESCRIPTION
. The IMP(f)11-A Interface, manufactured by Digital, provides a direct connection between PDP-II
Computer Systems and the Interfoce Message Processor (IMP) used to. connect Host Computers to the
Advanced Research Proiects Agency (ARPA) network. This UNIBUS option ollows the user (with ~ddi
tion of appropriate software) to communicate via the network with other Host systems, and is supplied with level conversion modules to connect to either the Local or Distant Host interface of net-

work IMP·s.

The IMP ll-A (Figure 1-1) is supplied in a BAll-ES mounting box, complete with power supply,
UNIBUS coble and light Emitting Diode (LED) indicator panel, and includes all the logic elements
required to implement the full duplex bit serial signal interchange defined for IMP to HOST connections. Diagnostic and exerciser software is also included to facilitate acceptance and maintenance
procedures.

;;

ii
II
oj.

UNIBUS

r-- - - - - POP -II
COMPUTER
SYSTEM

I
I
I
I
I
I
I
I
I

r--·-,

ORII- B

~-,

DRtt-B

TRANSMIT
LOGIC

RECEIVE
LOGIC

r---LEVEL CONVERTERS

I
I
I
I
I
I
I

.
II

ii
ii

I
I
I

••

IMP

LOCAL OR
DISTANT Hosr
INTERFACE

IL IMP
H-A
CABLE I
_________
...JI IMP-HOST
(NOT SUPPLIED) :
I

-.-.--~.---.---

;

CS-U56

Figure 1-1 System Block Diagram
1.2

OPERATION

The IMP ll-A logic consists of two DRll-B general purpose NPR interfaces plus two specially wired
BB 11 System Unit mounting blocks containing standard Digital M-Series Modules. One DR 11-B and
itsossociated BB 11 is dedicated to the transmit data and control signal path, and the other to the
receive signals. When enabled for transmit, 16-bit words are loaded into a register where the IMP
defined four way handshake signals shift one bit at a time out to the IMP. Each 16-bit word to be

___

__
" __

')1

~.*\~'~i~~~M

.•

____m___=__
'-__'______

~·~IF--~-~~
~~_t_$.~?

~~~

__________

______

----~--~

mifted:Ovt of the IMP ll-A is Input to the register by the DRl1-8 untU the preset word count overflows. Thil overflow terminates the transmit sequence.
On receive, 164ft words are assembled from the seriol bit stream from the IMP and are trans.ferred ta
K ' ;> .. iem memory by tfwt OR 1 '-B.
Either word count overflow or disconnection of the IMP terminates the
r,;. ~...:k and appropriate status interrupts are generated.
1.3

SPECIFICATIONS"
a.

MechcmtcQI:
h'.ounting 80x
DlrMnsions
WeIght
Prorequisites

One, type 6A11-ES
10-1/2 in. h, x 19 in. W, x 24 in. d

130lbs
None

E lectr;cal:
Input Power
Power Supply
logic

120 Vac :t: 10%, 47-63 Hz
One, type H72o-E
M-series modules, TIL levels

Operational:
Capacity
Transfer
Unibus loads
Data Rate
Interrupt

One IMP host interface
full duplex, NPR

Two
bits/sec., full duplex
Nominal 100,000
Receive Section 1) Receipt af LAST BIT from IMP
, 2) Receive word count overflow
Transmit Section
t) Word count overflow
local host .. single ended 0 Vdc to 5 Vdc
• Distant host .. differential± 1.0 Vdc
Bit asynchronous with request/acknowledge
handshake per bit
12 front ponel light Emitting Diodes displaying
major 1M? ll-A (unctions
Connector only supplied far terminating customer
supplied IMP-HOST cable

Output levels
Signalling
Indicators
Cabling

1.4

AVAILABILITY

The IMP ll-A Interface is manufactured to meet the specifications of the March 1974 revision of
SB & N report No. 1822, "Specifications for the interconnection of a host and an IMP".

"'-'"'

---

.......

'-_..

~U~

by Digital Equipment Corpora.tion

"""""'-"'---~'"'

I
.'

•

. 1 ,

,.',

SECTION 2
INSTALLATION
2.1

SITE CONSIDERATIONS

The IMP-1LA logic is contained in a

BAIl-ES mounting box.

Power

is derived from an H720E power supply which is also contained in
the BA-llES mounting box.

No special environmental considerations

exist, the IMP-ItA operates in the same envirofu~ent as the PDP-ll/45.

2.2

CABLES

2.2.1

Unibus, Cables

connection between the IMP-Il and the PDP-ll Unibus is accomplished
by means of standard PDP-ll

Unibus Cables (BelLA).

An M92~ jumper

card is provided for the Unibus connection between the two DR-llB's
in the l'MP-ll.

I,
l'

.j1,

The input bus cable from the processor side is

connected to slots AB~l in the DR-llB in the front of the mounting

L
I,

;, I; ,~

box and the output bus cable is connected to slots AB¢4 in the
second DR-llB.

NOTE:

It was not intended for'any other logic to be housed in the
BA-llES mounting box with the IMP-ll, therefore Unibus conn-

:"~
'J

ections were not provided in the other two system unit&.

,it is essential to mount another Unibus device in this box,
.-f

a short length of bus cable must be used to connect it to the

.
,

". !

DR-llB's located in the front of the box.

2.2.2

Signal Cable

A signal cable is not provided with the IMP-ll, the user must provide
a cable to connect the IMP-ll to the IMP.

The

end of this cable

which is to attach to the IMP-ll should be connected to the M908 which
is provided as follows:

2-1

'1
------

;hl

\-..

SIGNAL mME.... •

SIGNAL
PIN

SIGNAL
GROUND
PIN

Ready-for-next-host-bit

Data: Host to Imp
(TX Data)

Last Host bit

Ready-for-next-IMP-bit

There's-your-Imp-bit

'. D2

Data: Imp to host
(RX Data)

):,ast IMP bit

-(\

(TX RFNB)
~i'-

'--

There's-your-host-bit
(TX TYB)

(TXLB)

'. (rue RFNB)

(RX TYB)

(RXLB)

IMP Ready test

LI
L2

Host Master Ready
Host Ready test

JI
J2

Shield Ground

IMP master ready

**The names shown correspond to the names used in BB+N Report ¥l822.
Shown in parenthesis are the corresponding signal names in the
IMP-llA.

The signal cable will be connected to slot F¢4 6f the interface logic
for local host operation and slot E¢4 for distant host operation.
The two slots are pin compatible and no change in the signal cable
should be required by the IMP-II to convert from local host to distant
host operation.

Figire 2-1 shows a simplified schematic of a typical

signal to illustrate the relationship of the two connector slots.

2-2

."f

--'f--

i
i"
1
,

DIFFERENTIAL
E¢4

RECEIVER

DISTANT
BOST-IMP
CONNECTION

IDe TTL

SIGNAL

- -+"3"-,

LOCAL
aOST IMP
CONNECTION

..-

----~

~--~-+----------~--~---+----~

-=__I

I
1-

M906YA

IMP TO HOST SIGNAL

\"l'L SIG~AL

DISTANT
~------~~--~~~~----~
• HOST-IMP
r-------~~~--~.-~!>~~--I ONNECTION

,t
I

------------~------------------------4_~--~~~~--~:>>---

--~~---~~~---M906 YA

HOST TO IMP SIGNAL
FIGURE 2-1
TYPICAL IMP-II SIGNAL CONNECTIONS
2-3

LOCAL

HOST-IMP
CONNECTIOt

•

....,

Note that the ~istant and local transmit (hoat to IMP).signals do
not interfere but that the distant and local receive signals will
interfere in local host mode unless the MS007 differential receiver

I
,
I
I
t

is removed.

i ..

Therefore, to convert an LMP-Il from local to distant

host operation, use slot E~4 instead of F~4 and remove the M5~~7
module.

.
~

.'
~ _f~

•

2-4
(

"'Further specifications for construction of the interface cable can
be found in Bolt, Beranek, and Newman report #1822, "Sepcifications
for the Interconnection of a Hoat and an Imp".
~ ..

2.2.3

Internal Cabling

A short length of ribbon cable is used to connect the LED indicators
on the front panel to the indicator cable slot '(D~4) in the IMP-II lO<Jic.

A short Unibus Cable

(BCIlA-~2)

to the IMP-lIA transmit logic.

is used to connect the first DR-lIB
An M920 jumper is used to connect

the second DR-lIB to the receive logic.

GROUNDING

2.3

The IMP-lIA should be grounded to the processor system ground with
the ground strap provided.
-../

2.4

.t.

!-' :.

rr
I

INITIALOPERATION

1
I

The following checkout and acceptance procedures are performed
in-house prior to shipment of the IM.?-llA.

It is suggested' that th~y

be performed again at the customers site, as an initial on site

turn-on procedure.

2.4.1
A.

Acceptance Test

Check out the DR-lIB's on a stand-alone basis.
Disconnect the IMP-II interface logic from the DR-lIB's by disconnecting the BC-IIA Unibus Cable from slot CD~4 of the first
DR-lIB and the M920 jumper from slot CD~4 of the second DR-lIB.

2-5

. . til
,

"I'

Move the M968, DR-lIB test board, from AB~2 to slot CD~4 in each
(~NDEC-lI-DZDRBA)

DR-llB.

Run the DR-lIB diagnostic

"-~

DR-llB.

The test should be run for twenty minutes without error

on each

on each DR-lIB. (See Section 3.1 for DR-lIB addresses).
4 R~ <'W10 v~ ') U rv'1{JG e. Eu~ 4 / - ..£03 C .:L
B.

;

Check out the IMP-II in local host mode.
Reconnect the DR-lIB's to ~e

~-ll

interface logic.

the DR-lIB test board to slot ABj2 in each DR-lIB.

Restore

Install the

IMP-II loop-back connector in slot F~4 of the LMP-Il interface
logic.
Remove the M5007 differential receiver.

NOTE:

The IMP-II will

malfunction' in the local host mode if this module is not removed.
Run the IMP-II exerciser

(DECSPEC-II-AYNADB)for 45 minutes.

Checkout the

IMP~ll

in distant host mode.

Replace the M5007 differential receiver module in the IMP-II
logic and move the loop back connector from slot F~4 to slot E~4.
Repeat running the IMP-II exerciser for 45 minutes.
NOTE:

For factory acceptance, a long twisted pair cable will

be used in this test in place of the loop back connector to
more realistically test the differential level converters.

: ..

(
t

2.5

RELATED LITERATURE

Bolt, Beranek, and Newman Report #1822, "Specifications for
Interconnection of a Host and an IMP".

...........

DR-lIB Option Description DEC-II-HDRA-D

Unibus Interface Manual

Logic Handbook

2-6

M-----

, _ .. _

•
SECTION.
3
OPERATION AND PROGRAMMING

~ f~~

~~
~ {'r'

I·

. All access to the IMP-II logic by the pr<><Jram i8 through the two

DR-IIBts.

The option appears and

functio~s as two standard DR-IlB's
I

with the exception of the function and status bits, which are redefined
I

for the IMP-llA.

The reader is referred to ~e DR-lIB manual which
/

is provided with the IMP-ll for a more thQfough description of the
~"

standard DR-lIB functions.

3.1

'~I

HARIMARE REGISTERS

The following is a list of the hardware registers in the IMP-ltA
with their standard address assignments:
TXWCR

172410

TXBAR

172412

TXCSR

172414

I ,- :

TXDBR

172416

(;

,
:4 ..
I.

17~430

RXWCR

! :

RXBAR·

172432

RXCSR

172434

RXDBR

172436
77;) ~J'

Standard vector addresses are

3.1.1

Transmit

124

Receive

-114 .

/11/

<. I ./ •I

- -

. ,'.

'.~

Transmit word count register (TXWCR) - 172410

:f t~
; "

The TXWCR is a 16 bit read/write register.

It is initially loaded

with the 2's complement of the number of words to be transmitted
and increments toward zero after each bus cycle.

When the overflow

occurs (all l's to all ¢'s)the READY bit of the TXCSR sets, bus

3-1

; ii
t .~

"Ji

t':

"cycles cease # and if the interrupt enable (bit ¢6 of the TXCSR) is
set an interrupt is generated.

3.1.2

TXWCR is cleared by bus INIT.

Transmit Bus Address Register (TXBAR)-" 172412

The TXBAR is a 15 bit reaQlwrite register.

Bit~, corresponding

to address bit A~~ is set permanently to a zero.

With the two

extended memory bits in the TXCSR (XBA16 and XBA17) the TXBAR
specifies BUS A (17 : ~1) in direct bus access.

The register is

incremented by two following each bus cycle advancing the address
to the next sequential word location in the UNIBUS address space.

~f the TXBAR overflows (all l's to all ~'s) the error bit in the
TXCSR sets.

~is

error condition is cleared by loading the TXBAR

J NOTE: TXBAR is a word register; do not use byte

or by bus INIT

instructions when loading the register.

The TXBAR is cleared by bus INIT.

Overflow does ~ increment the

extended address bits XBA16 and XBAl7.

Therefore the maximum block

that can be transferred is \lZK words and a block ca~ be transmitted
that overlaps a 32K boundary.
2.1. 3

Transmit Command/Status Register "(TXCSR)~ 172414
()~

r--=--15

ERROR

USED
NEX
fi.~r;.c ATTN

XBA17

READY

ENABLE

NOT

XBA 6

USED

LAST
BIT CLEAR
StrATUS

Cyct.E

NOT

USED
.. -~

3-2

-.-3.1.3.1

ERROR (Bit-IS) - The ERROR bit is read-only, and specifies

an error condition when:
a.

The DRll-B has attempted to address non-existent memory
(also indicated by NEX Bit-14) or

The ~-t modul-e -is -notinse!:'ted -m- slor-iil102 or CD04 of
~

DR1I-B,-ur

The bus address ~gi~r---T:{BAR" has overflowed by incremen-ting from alII's to all O's.

ERROR sets READY (Bit-7) and causes an interrupt if INTERRUPT ENABLE
(Bit-G) is set.

The ERROR bit is cleared by removing the condition(s) that caused
it to set:
e.

NEX is cleared by loading Bit-l4 with a zero.

knSert-the t:e-st module in slot AB02 for norrnaloperat:i-on
O-r--eD¢4 for diagnostic tests.

3.1.3.2

Reload the bus address register DRBA.

NEX (Bit-14) - NEX is a read/write to 0 bit.

The non-

existent memory condition specifies that, as Unibus master~ the
DR-lIB did not receive a SSYN response within a 20 microseconds
following assertion of MSYN.

NEX sets ERROR (Bit-IS), READY (Bit-7),

and causes an interrupt request if IE (Bit-G) has been set.

This

bit is\cleared by INIT or by loading a zero, it cannot be loaded with
,"

..
::

done.

3-3

:.1'

(Bit 13) - The ATTN bit is pulsed by the transmit
RFADY BIT in the DRllB when TX CLEAR

STATUS

(Bit 2)

t:'

,':

will cause an interrupt if IE (Bit 6) is set.

This

is a READ ONLY Bit and should normally be zero.
3.1.3.4

MAINT (B~'t- 2) -·The MAINT bit is read/write: it is used

exclusively with

gnostic programs and is cleared by 1N~T (refer

to Chapter Five

he DRl1-B manual for further information).

3.1.3.5

Bits

~io, and 11 are not used in the transmit logic.

They a~e reaJon~ bits.
3.1.3.6

CY~Bit-8) - The cycle bit is not used in the

IMP-II

logic and m~b~ignored.

3.1.3.7

READY (Bit-7) - The read-only READY bit specifie~that the

DR1l-B is ready to accept a

ne~

command.

Wh~n

set, READY forces the

DR1I-B to release control of the Unibus and inhibits further DMA cycles •

This bit is set by INIT, ERROR (Bit-IS), or word count overflow and
is cleared by GO (Bit-O).

Note that READY must be cleared prior to

initiating the block transfer.

When set, causes an interrupt request

if IE (Bit-G) has been set.

3.1.3.8

IE (Bit-G) - The read/write IE bit enables an interrupt to

occur when either ERROR or READY is asserted.
by INIT.

3-4

This bit is cleared

..
"

~
3.1.3.9

XBA17, XBAl6 (Bits 5 and 4) - These two read/write e~tended

1
ff'

~us ~ddress bits (17 and 16) are used with TXBAR to s~cify A(l7:0l / ~_ "
in direct memory transfers.

XBAl7 and XBA16 do JIIeo11 increment when

3.1.3.10

Bit 3 is not used in the transmit logic.

3.1.3.11

ENABLE LAST BIT (BIT 2)

--/ L

When set, the IMP-II will generate

the LAST BIT signal to indicate the end of message when the word count

-;.

overflows.

The bit is cleared to stop the IMP-II fromsignalinq

end of message when transmitting multiple buffers.

This bit should

be set when transmitting the last buffer in the message. -If the
message consists of only one buffer, the bit can be set before starting

,
!j-

: i

transmission (setting the go bit)
~te. of

NOTE:

~'l%e

I-MP-llexamines t-he .

this -bit when the last word (word count-GVerflow) hasbeeri

: ':

" J

--' 1

~I:
: I.

, ,I

3.1.3.12
logic.

TX Clear Status (Bit 1)

This bit initializes the transmit

It should be set and cleared to initialize the transndt logic

in the IMP-II.

NOTE:

Leaving this bit set will disable the transmit

I ~l II

IIIill

III1
J
j

logic.

Setting this bit will also cause the transmit DR-lIB to

abort any operation and set i~s Ready bit.

Will cause an interrupt if

IE (Bit 6) is set.
~
". f

3.1.3.13

(Bit~O)

- The write-only GO bit causes a pulse to initiate

the first DMA cycle in the block transfer.
a zero.

This bit always reads as

When set, this bit clears ready (Bit 7).

3-5

3.1.4

Transmit Data Buffer Register (TXDBR) - 172416

I·'
:,-

.E.

The TXDBR serves as temporary storage register in the DR-lIB to

L
t.

hold the word being transferred under program control.

There should

be no need for access to this register in the IMP-llA.

3.1.5

Receive Word Count Register (RXWCR)

172430

The function of the RXWCR is equivalent to the TXWCR (see section 3.1.1).'

3.1.6

Receive Bus Address Register (RXBAR) -

172432

The function of the RXBAR is equivalent to the TXBAR (see section 3.1.2).

'3.1.7

Receive Command/Status Register (RXCSR)

.14

ERROR

172434

MAINT

READY

WRITE
ENABLE
HOST

LINE
NE

END

3.1.7.1

ERROR
CYCLE

XBA17

MOO

IMP
NOT
READY

READY

ERROR (Bit-1S) -The ERROR bit is

READY

ATTN

XBA16

read-only~

RX
CLEAR
STATUS

and specifi~

an error condition when:
a.

The DRll-B h~s attempted to address non-existent memory
(also indicated by NEX Bit-14) or

Tim --t=e-s-t ltIodu1e tsnot inserted in slot AB02 or CD04 of the

DRll----t3,

The bus address

Pegi-s~er

RXBAR has overflowed by incrementing

from alII's to all O's.

3-6

ERROR sets READY (Bit-1) and causes an interrupt if INTERRUPT ENABLE
'(Bit-6) is set.

The E~~OR bit is cleared by removing the condition(s) that caused
it to set:
e.

NEX is cleared by loading Bit-14 with a zero.

:Insel:~~e

test -m-ochllain slot An02 for no-rnfal--operation

or--DCO¢ for di-aqnostic

tests~

Reload the bus address register RXBAR.

3.1.7.2

NEX

(Bit-14) - NEX is a read/write to O-bit.

The non-

existent memory condition specifies that, as Unibus master, the
IMPll-:-A did not receive a SSYN response within a 20 microseconds
following

asserti~n

of MSYN.

NEX sets ERROR (Bit-15), READY (Bit-7).

and causes an interrupt request if IE {Bit-6h has been set.

This

bit is cleared by INIT or by loading a zero, it cannot be loaded
with a one.

3.1. 7.3

ATTN

(B~::-\'3),

mp-ll when the

(

The ATTN bit is read' onl;; it is pulsed- by th '

),.,.(bi~ signal has been received from the IMP.

C:This causes an interrupt if interrupt enable (Bit 6) is

set~The ~

error bit will not be set and end of MSG (Bit 11) wi~l be set

when ' /

the last bit has been

rec~«y The ATTN Bit is also pulsed by the

receive logic to set

the.JR-li'"~ -~R"eady Bit when RX clears' status is

.:~

,l
i

asserted.
3.1.7.4

MAINT (Bit-12) - ~e

MAINT bit is read/write; it is used

exclusively with diagnostic~r~rams and is cleared by INIT (refer
"\

to Chapter Five in the DRll-B ~anual for further information).
\

3-1

3.1.7.5 "END OF

MSG ,(Bit 11) -

Indicates that the last bit signal
:.

has been received from the IMP signifying the end of a message. Cleared
,

!
i:: .

by rue CLEAR STATUS or GO (Bi t

~).

'--~

,rl 3 .-1 • 7 • 6

IMP NOT READY (:i.it 10) - When set, indicates that the IMP

is not ready.
3.1.7.7

READY LINE ERROR (Bit 9)

When set, indicates that either
W~
vJt?
(Lev 8J
~C.L~
HOST READY
not. set or IMP NOT READY ¥f se~.

(1..&-0/

~ ~ ~-r .J

3.1.7.8

CYCLE

(Bit-8)

The cycle bit is not used in the IMP-ll and

may be ignored.

3.1.7.9

READY (Bit-7) - The read-only READY bit specfies that the

DRI1-B is ready to accept a new command.

When set, READY forces the

;" :

DR11-B to release control of the Unibus and inhibits further DMA
This bit is set by INI~, ERROR (Bit-IS), or word count over-

cycles.

flow and is cleared -by GO (Bit-O).

r:
~

Note that READY must be cleared prior t'

; i

to initiating the blcck transfer.

When set, causes an interrupt

;· iI
·i

request if IE (Bit-G) has been set.

3.1. 7.10

;

· I:

IE (B"it-6)'- The read/write IE bit enables an interrupt to

Iii,
: Ii
Ii

nnT.

~·l

3.1.7.11

· Ii
'-11

occur when either ERROR or READY is asserted.

This bit is cleared by

.- II

• II

'II

XB17, XB16 (Bits 5 and 4) - These two read/write extended bus

address bits (17 and 16) are used with TXBA~ to specify AL17:0t~

iri direct memory transfers.
TXBAR

XBA17 andXBA16

overflows ,...=i.n:;~2i1d, -ERROR is- set.

~not

increment when

,\'1

i,· "I

"3-8

: II

, II
) !I

3.1.7.12

. --

RX WRITE ENABLE (Bit 3) - Must be set for proper operation

of the receive logic.
~

-~-----

If this bit is not set, the IMP-II will

effectively discard any data that is received although it will other
wise appear to operate normally.

3.1.7.13

HOST READY (Bit 2) - SET to INDICATE to the IMP that the

host is on line and ready.

3.1.7.14

(READ/WRI'i'E)

Cleared by INIT.

(READ/WRITE)

RX CLEAR STATUS (Bit 1) Initializes RECEIVE LOGIC.

should be set and then cleared to initialize the logic.

NOTE:

Leaving this bit set will disable the transmit logic. Setting this bit
will cause the receive DR-lIB to abort any operation and set it's ready
bit. Will cause an interrupt it IE (Bit 6) is set.
,
3.1.7.15

GO (Bit-O) - The write-only GO bit causes a pulse to initiate·

the first DMA cycle in the block transfer.
a zero.

3.1.8

When set, this bit clears

This bit always reads as

READY (Bit-7).

Data Buffer Register (RXDBR) receive. - 172436

The RXDBR serves as a temporary storage register in the DR-lIB to hold
the work being transferred under program control.

There should be

no need to access this register in the IMP-llA.

. II
3.2

'II

INDICATORS

There are 12 indicators on the front of the IMP-1lA.

DAl)l\

'{'YB

DlfA 1JB

TX
HFNB
0
HX

HOST
NOT

T.B

ROY

HIW

NOT

(5FNB

1M)

..-------~--

.. - ------.--

FIGURE 3-1 IMP-ll INDICATOR PANEL
3-9

(See figure 3-1) •

:1 he lights, DATA, RFNB, and TYB represent the current state of the
1

Datj, Ready-for-Next-Bit and There's-your-Bit signals respecively
between the host and IMP.
The lights IMP NOT READY and HOST NOT READY reflect the state of the
ready signals in the IMP and host.

The normal condition of these

lights is that both should be out.

If either of these lights is lit

it indicates an abnormal condition in either the host or

the IMP.

The two ready lights reflect the state of the , DR-lIB ready signals.
These lights will be out while ~~ transfers are taking place and will
be on when the respective DR-lIB is idle.
3.3

PROGRAMMING EXAMPLE

The following example shows the programming steps necessary to transmit
,

a block of 500 decimal words.
TRNSMT:

MOV

#TXBUF,TXBAR; Set up Bus Address

MOV

#-500., TXWCR: Set up word count

MOV

#2,TXCSR; TOGGLE TX CLEAR STATUS

MOV

#4,TXCSR; Set Enable Last Bit

.. ,
':-

BIS

•o

#lOl,TXCSR; Set TX GO and INT Enable •

•
TXBUF:

(500 words of data)

114:

Transmit Interrupt Service Address

116:

and Processor Status Word

\
"

3-10

-.,

The following shows the programming steps necessary to receive a
500 word (or less) message:

MOV

#RXBUF,RXBAR~

MOV

#-500., RXWCR; Set RX Word Count

MOV

#16,RXCSR; Set, host ready, write enable and clear status

BIC

#2,RXCSR: Drop Clear Status

BIS

#IOl,RXCSR: Set RX GO and Interrupt Enable

Set RX Bus Address

124{ RX- Interrupt Service routine address and Processor Status Word
126
.

The above program for receiving will cause an interrupt whenever 50~
words of data have been received and/or the last bit signal is received.

NOTE:

The last bit signal is not recognized by the IMP-II until the

end of a word.

,.
I

3-11

"
SECTION 4
THEORY OF OPERATION
4.1
'--

GENERAL

The IMP-II is a PDP-II family device for interfacing a PDP-II to
the Advanced Researcn Projects Agency Network (ARPANET).

The

IMP-II is designed to-connect to an Interface Message Processor
(IMP)

which is the

~ommunications

processor in the ARPANET.

The

signalling scheme is in adherence with the specifications in Bolt,
Beranek and Newman Report 1822, "Specifications for Interconnection
of a Host and an IMP."

Figure 4.1

shows a simplified block diagram of the ~-ll logic.

4-1

/\
TRANSMIT
DR-lLB

. . . ______ ~ ____~J

- -1

I '-I
I

TRANSMIT
INTERFACE
LOOIC

RECEIVE
DR-lIB

RECEIVE

INTERFACE
LOGIC

_.1

LOCAL

HOST
SIGNALS

, - _ .. [-.-

[

~~;;ANT
LEVEL
.CONVERTERS

· -=
rL
;__ .. _

SIGNALS,

________ I~~~~ANT
LEVEL

---t>
.

CO~~R§---i

,
I

FIGURE 4.1
IMP-II SrMPLIFIED LoGIC DIAGRAM
"

The interface to the UNIBUS is. through 2 DR-lIB's.

Associated with

this pair of DRll-B's is an interface logic assembly.

This logic

controls the ORll-B's, serializes and de-~erializp.s the data,and
generates the control signals required by the Host Interface in the
IMP

\
I

4-2

4 •..2

INTERFACE LEVELS

The IMP-ll is capable of operating in two modes, as either a local
host or as a distant host.

The local host signals out of the rMP

' - are standard TTL levels of 0 and +3V to ground driven by high current
drivers.

The distant host signals are differential signals as

follows:

4.3

Signal Line

Logic 1
+O.5V

Logic ~
-O.SV

Pair

-O.5V

+O.SV

TRANSMIT LOGIC

The transmit section of the interface logic assembly consists of a

16 bit shift register, a 4 bit counter, and a number of flip-flops
for status and control bits.

The transmitting sequence is initiated when the GO bit is set and the
DR-lIB Ready signal goes low.
~ logic.

This removes the reset·fram the transmit

This causes a pulse on TX READY FALL and a request is given to .

the DR-lIB for the first word.

The DR-lIB does an NPR cycle, inputing

the first word from computer memory and passing it to the transmit shift
register of the interface logic assembly.

The data is shifted out

according to the four way hand shaking protocol of the Host Interface
of the IMP.

(see timing diagram print IMP-II-O-IO).
~

The four way hand shaking sequence associated with each data bit proceeds

as follows.

i'
J' .

The assertion of Ready-for-Next-Bit (RFNB) fram the Host

interface in the IMP is detected in the IMPII-A and the next data bit
is s11ifted onto the data line.

After a short delay, the IMPll-A asserts

l
i·'

Thcrcs-your-Bit.

---

(TYB)

The Host interface uses this signal to strobe the

Jata bit in and then drops RFNB.

The negation of RFNB at the IMP-llA

rc·sults in the dropping

The interface logic in the IMPlI-A starts

of TYB.

on the next four-transition cycle when RFNB signal is re-asserted by the
Host interface.

4-3

r-'--"
i

..
Figure 4-2 shows a simplified diagram of this sequence.
r - ----.--- - - - - --

R-F-N-B
(From Host interface
in IMP)

~,,-~

1-)

_ ~J .-

:_---,)
,-

._--

'".

T-Y-B
(From IMPlI-A)

--~~-.

-t

Data present
on data lines

Data
accepted
"'by
" receiver

FIGURE 4.2
The 4 bit counter is incremented and the shift register is shifted
during each cycle.

When the counter overflows, (16 bits transmitted)

a new wc,rd request: is given to the DR-lIB and fu:.:ther transfers al:e
inhibited until the word has been received from the DR-lIB and loaded
into the shift register.

Note that the counter is incremented to one

as soon as the word is loaded since the first bit is present on the
data lines at that time.

4-4

The TX

Last Word flip flop is set as soon aa the last word is beinq

transmitted (indicated by the rise of the DR-llB ready signal.
'-

the last bit of the last word, the Last Bit (LB) signal is transmitted
along with the data if the Enable Last Bit was set in the DR-llB status
register.

The Last Word flip flop is cleared automatically following'

transmit~ing

this bit so that it will be initialized for the next

block of data.

As Boon as the Last Word signal is cleared, the Reset

signal is asserted and the logic is disabled until the next block
transfer.

4.4

RECEIVE LOGIC

The basic operation of the receive logic is very similar to the
transmit logic.

There are several minor differences and several

additional features.

One of the minor differences is the 4 bit counter

starts at zero rather than one because the first bit must be shifted
in before it is counted.

When the Last Bit signal has been recognized by the IMP-II logic, it
is not presented to the processor as an interrupt until the word has
been transferred by the DR-lIB.

Therefore, if it is sent before all

16 bits have been received, the interrupt will not occur until all
16 bits have been received.

!MP-ll-~-~9

shows a detailed drawing of the receive timing

sequence.

4-5

·"_..

•

#~- . .-.-~

."",,-"' • • . ' - ' .

~.'

-~~.~.

is included in the logic to signify to the IMP that the
host PDP-II is ready.

The two sides of the relay contacts are

brought out to the IMP as signal lines.

The normal way to use these

is to ground one side and sample the output of the other side.

The

other side will then be switched between an open circuit and ground
depending on the state of the relay.
host ready bit in the RXCSR.

The relay is set by setting the

Naturally. if power is lost to the

IMP-II, the relay will open and indicate to the IMP" that it is not"
ready.

A flip flop (Ready Line Error) has been included to store the fact

that either HOST NOT READY or IMP NOT READY has been asserted.
.

DR-lIB LOGIC

(" ,

- //-

.... -, . '

.:....

/~!),,~,

DR-lIB option description for a thorough analysis of the DR-lIB logic.
Since some of the normal DR-lIB signals have different names in the
IMP-II, a table is presented here to show the correlation of the
standC".rd DR-lIB signal names and the nat-nes given to tr~e signals in
the IMP-II logic.

4-6

TABLE 4-1

IMP-I1/DRllB SIGNAL NAMES

----~~----~----~------------------------

IMP-11
RECEIVE SECTION NAME

NAME IN RECEIVE DRIlB

GROUND

CO CONTROL H

WRITE ENABLE

C1 CONTROL H
CYCLE REQUEST AH

RX WORD READY

CYCLE REQUEST BH

+3V

WC INC END H

+3V

SA INC ENB H

GROUND

AOO H

RX END OF MESSAGE

DSTAT A H

IMP NOT READY

DSTAT B H

READY LINE ERROR

DSTAT C H

'RX ATTN H

ATTN H

+3V

SINGLE CYCLE H

RX WRITE ENABLE

FNCT 3 H

HOS'.r REALY

FNCT 2 H

RX CLEAR STATUS

FNCT I H

RX INACTIVE

READY H

RX CYCLE BUSY

BUSY H

RX WORD ACCE PT

END CYCLE H
GO H
NO LOCK H
INIT II

4-7

OATIS OUT H
DATI4 OUT H
DATI3 OUT H.
DATI2 OUT H
DATIl OUT H
DATIO OUT H
DAT09 OUT H

OAT 08 OUT H
DAT07 OUT H

;;

DAT06 OUT H
4-8

•

" ..
,

·f.
-;

IMP-ll

. RECEIVE SECTION NAME

NAME IN RECEIVE DR-llB
DATOS 0U'l' H

DAT04 OUT H
DAT03 OUT H
DAT02 OUT H

DATOl OUT H
DATOO OUT H

TruL~SMIT

IMP-ll

. NAME IN TRANSMIT DR-lIB

SECTION NAME

GROUND

CO CONTROL H

GROUND

Cl CONTROL H

WORD REQUEST

CYCLE REQUEST AH
CYCLE REQUEST BR

+3V

WC INC ENB H

+3V

BA INC ENB H
AOO H

DSTAT A H
DSTAT B H
DSTAT C H
TX A'I'TN H

ATTN H

+3V

SINGLE CYCLE H
FNCT 3 H

TX ENABLE LAST BIT

FNCT 2 H

TX CLEAR STATUS

FNCT 1 H

TX HE1\DY

READY H

I'V

... CYCLE BUSY

BUSH H

T'X WORD VALID

END CYCLE H
GO H

.........,.

NO LOCK H
INIT H

4-9

.. ---

• .,.

--.~

-->"0

...

,"-

......

-,0...;- ___

¥-

,~.-

,","-~

--T
;~

•

IMP-II
TRANSMIT SECTION NAME

NAME IN RECEIVE DR-lIB

DAT15

IN H

DATI4

INH

DATIl

IN H

DATI2

INH

DATIl

IN H

DATlO

IN H

DAT09

INH

DAT08

IN H

DAT07

IN H

DAT06

IN H

DATOS

IN H

DAT04

IN H

DAT03

IN H

DAT02

IN H

DAT01

IN H

DATOO

IN H

BIT 8

DAT1S

OUT H

DAT14

OUT H

DAT13

OUT H

DATI 2

ou'r H

DATIl

OUT H

DAT10

OUT H

DAT09

OUT H

DAT08

OUT H

DAT07

OUT H

-..../

DAT06

OUT H

BIT 2

DAT05

OUT H

4-10

J:1

" 11

...

r :~
r

• • ,
TX

BIT 3

DAT04

OUT B

DAT03

OUTH

'--

DAT02

OUTH

BIT 6

DAT01

OUT H

--.-

4-11

•

•
SECTION 5
MAINTENANCE
5.1"

SPECIAL TEST EQUIPMENT - NONE

5.2

SPECIAL TOOLS

5.3

PREVENTIVE MAINTENANCE

NONE

Clean fan filters to insure adequate ventilation is provided.

This

will facilitate proper cooling of power supplies and control logic.

5.4

CORRECTIVE MAINTENANCE

It is suggested that the acceptance and test procedure in Appendix A
be repeated to locate and repair malfunctioning logic.

5-1

SECTION 6
SPARE PARTS
6.1

MODULES

Table 6.1 lists the IMP-ItA module complement by Dec No •• function,
and quantity.

TABLE 6.1

IMP-llA MODULE COMPLEMENT

...----: ....

TYPE

FUNCTION

G8000

+12V SUPPLY

K265

Relay Driver

~nll

Inverter

Ml13

10-2 Input Nand Gate

1-1117

6-4 Input Nand Gate

M205

5 "D" Flip Flops

M238

SY!lchronous 4 bit UP/Down Counter

M245

4 Bit shift register

M3l0

Delay Line-

M40l

Variable clock

M594

EIA level converter

M611

High Speed Power Inverter

MS007

Differential Receivers

W964-YA

Resistor Network with -5V supply

M906YA

Tenninator

6-1

SlTY·

!iii

APPENDIX A
DEVICE DIAGNOSTIC PROGRAM DESCRIPTION
A. 1

ABSTRACT

The diagnostic program for the IMP is the IMP-llA Offline Exerciser
(DECSPEC-II-AYNADA). An online

diagnostic which checks the operation

of both the IMP and the IMP-II is available from Bolt, Beranek, and
New~an.

The On line diagnostic is not supported by DEC and any

inquiries regarding it should be addressed directly to BB+N.

The offline exerciser tests the IMP-II by looping the transmit side
into the receive side by using the test connector provided.

The diagnostic transmits 500 words

of random data through the IMP

on each pass. It also checks the proper operation of all status and
function bits and interrupts.

NOTE:

-."

The IMP-II offline exer.ciser was not intended to be used in
isolating problems in the DR-lIB's.

These problems can best

be isolate0 by running the DR-lIB diagnos~ic on each of the
DR-lIB's with them disconnected from the IMP-llA logic.

Since

the majority of the logic in the IMP-II is in the DR-lIB, it
is suggested that the first step in isolating any problems
that occur should be to verify the operation of the DR-lIB's
on a stand-alone basis.

A.2

REQUIREMENTS

The diagnostic can be run with 8K of core, any PDP-II processor, and
the IMP-II.

]\.-1

I
jj

II
II

.. ">,"
, .

....

A.3

)

LOADING PROCEDURE

The program is normally furnished on paper tape.

The nonnal procedure

for loading binary tapes is followed for loading the tape into memory_

A.4

STARTING PROCEDURE

There are three starting addresses used in the program:
200 Normal Start and Initialization
204 Restart Address
210 Start program at this address to input any non-standard

IMP-li addresses.

A.S

ERRORS

~men

an error occurs, the diagnostic prints out the contents of the

IMP-II hardware registers (see section 3).

If a data check error

occurs, the diagnostic also prints out the number of the word in error
-....".'

........

and the transmitted and received words.

A-2

" 611"/'
.. u..,..,

APPENDIX B
SHIPPING LIST
,

B.I

EQUIPMENT FURNISHED

The following documents and equipment are provided with an IMP-llA:

BAllES mounting box with mounting hardware.

(1 each)

H720E power supply with remote turn-on cable.

DR~lIB

IMP-II interface logic with full module complement (see table 6.1)

Test connector for IMP-II logic.

(1 each)

Blank M908 for user signal cable.

(1 each)

IMP-II Option Description

L'1P-II Offline

IMP-II Print Set.

DR-IIB/DA-IIB Manual.

DR-lIB Print Set.

DR-lIB/DA-IIB Diagnostic, (MAINDEC-ll-DZDRBA)

(1 each)

general purpose NPR interface (2 each)

(CSS-MO-F-3.3-la~)

Exerciser (DECSPEC-II-AYNADB)

...

. "

/
{ ':'

B-1

,....