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EK-RUX50-TM

October 1984

76 pages

Original

2.4MB

Document:	RUX50 Controller Technical Manual 198410
Order Number:	EK-RUX50-TM
Revision:	000
Pages:	76
Original Filename:	http://bitsavers.org/pdf/dec/unibus/EK-RUX50-TM-001_RUX50_Controller_Technical_Manual_198410.pdf

OCR Text

EK-RUXSO-TM-001

RUXSO Controller
Technical Ma,nuol

. ''rl'~"'!l':I.
~a~ u11 "'u~
-

- --

- -----

EK-RUXSO-TM-001

RUX50 Controller
Technical Manual

Prepared by Educational Services
of
Digital Equipment Corporation

First Edition, October 1984

The reproduction of this material, in part or whole, is strictly
prohibited. For copy information, contact the Educational Services
Department, Digital Equipment Corporation, Maynard, Massachusetts
01754.
The information in this document is subject to change without
notice. Digital Equipment Corporation assumes no responsibility
for any errors that may appear in this document.
IBM is a trademark of International Business Machines Corporation.
The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts.

~n~nomo

DECmate
DECnet
DECsystem-10
DECSYSTEM-20
DEC US
DECwriter
DIBOL

DIGITAL
MAS SB US
Micro/PDP-11
PDP
P/OS
Professional
Q-Bus
Rainbow

RSTS
RSX
UNIBUS
VAX
VMS

VT
Wo'rk Processor

CONTENTS

CHAPTER 1

INTRODUCTION

1.1
1. 2
1. 3
1. 4

General Information ••••••••••••••••••••••••.••••
Related Documentation • • • • • • • • . • • • • • • • . • • • • • • • • • •
General Description .•••••••••••••.•••••...••••••
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 2

CONFIGURATION AND INSTALLATION

2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.4

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem Configurations ••••••••••••••••••••••••
Jumper Configurations ••••••••.•••••••••••.•••••.
Device Address Selection ••••••.••••••.••••••
Logical Unit Number Selection ••••••••••••...
Device Type Selection ••••.••••••.•••••••••••
Interrupt Request Level ••••••..••••••.••.•••
Long- or Short-Line Selection •..•.••••••.•••
Subsystem Installation .•••••••••••••••••••••••••

CHAPTER. 3

THEORY OF OPERATION

3.1
3.2
3.2.l
3.2.2
3.2.3
3.2.4
3.3
3.3.1
3.3.1.l

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UNIBUS Interface Circuits •••••••••••••••.•••
T-11 Processor Circuits ••.•••••••••••••••••.
DMA Control Circuits •••••••.••••••...•.•••••
Diskette Drive Controller Circuits ••••••••.•
Circuit Details .• . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UNIBUS Interface Circuits •••••••••••••••••••
UNIBUS Address Transceivers/Address
Match Detector

3.3.1.2
3.3.1.3
3.3.1.4
3.3.1.5
3.3.1.6
3.3.2
3.3.2.1

.•••••.•..•..•......••••..

UNIBUS Data Buffer/Transceivers ••••.•..•
UNIBUS Control Transceivers ••.•••••.••.•
PIO Read/Write SA Registers ••..•••••••••
MSCP PIO Controller/IP Register •••••••••
Interrupt Controller and Vector Register
T-11 Processor Circuits ••••••••••••••••••••.
Interrupt Request, Initialize, and
Asychronous Hold Registers ••.•..••.••.••

iii

1-1
1-2
1-2
1-2

2-1
2-1
2-2
2-2
2-4
2-4
2-4
2-4
2-6

3-1
3-1
3-1
3-3
3-3
3-4
3-4
3-4
3-6
3-6
3-6
3-6
3-6
3-7
3-7
3-7

3.3.2.2

T-11 Microprocessor, Mode buffer, Address
Latch, I/O Bit Map, and Memory Decoder ••

3.3.2.3
3.3.2.4
3.3.2.5
3.3.2.6
3.3.3
3.3.3.1

RAM and ROM •••••••••••••••••••••••••••••

3.3.3.2
3.3.4
3.3.4.1
3.3.4.2
3.3.4.3
3.3.4.4

Display Register and LEDs •...••••••..•••
Device Type Register .••••••..•••••••••••
LUN Register

•••••••.•••••••..•••••••••.•

DMA Control Circuits ••••••••••••••••••••••••
DMA Controller, Timers, and Data Buffer
CS Rs • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
UNIBUS DMA Address Pointer/Buffer and
UNIBUS Address Extension Register •••••••
Diskette Drive Controller Circuits •.••••••••
Diskette Drive CSR and Data CSR •••••••••
Diskette Drive Controller ••..••••••••..•
Data Separator/Write Precompensation ••••
Drive Interface Transceivers •••••••.••••

3-9
3-10
3-11
3-11
3-11
3-11

3-11
3-13
3-13
3-14
3-14
3-15
3-15

CHAPTER 4

INTERCONNECTIONS

4.1
4.2
4.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UNIBUS Connector . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . •

4-1
4-1

Drive Interface Connector Jl ••••••••••••••••••••

4-1

CHAPTER 5

TROUBLESHOOTING

5.1
5.2
5.3
5.3.1
5.3.1.1
5.3.2
5.3.2.1
5.3.3
5.3.3.1
5.3.3.2
5.3.4
5.3.4.1
5.3.4.2
5.3.4.3
5.3.4.4
5.3.4.5
5.3.4.6
5.3.4.7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 6

PROGRAMMING

6.1
6.2
6.2.1
6.2.2
6.3
6.4
6.4.1

Introduction
Control Protocols •••••••••••••••••••••.•••••••••
Mass Storage Control Protocol •••.•••••••.•••
Diagnostics and Utilities Protocol •••••••••• ·

Initialization Test .•••••••••••••••••••.••••
Initialization Drop Unit Summary ••••••••
Performance Exerciser •••••••••••.•••••••••••
Performance Exerciser Drop Unit Summary •
Operating Instructions •.••••••••••••••••••••
Hardware Configuration Questions ••••••••
Software Parameter Questions •••••••••.••
Diagnostic Error Reporting •.•••••••.•..•••••
Initialization Errors •••••••••••••••.•••
Performance Exerciser Errors ••••••••••••
Errorlog Messages . . . . . . . . . . . . . . . . . . . . . . .
MSCP Errors

•••••••••••••••••••••••••••••

Sample Error Message ••••••••••••••••••••
Performance and Progress Reports ••••••.•
Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Registers •••.••••••••••.•••••.•••••
IP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1
5-1
5-4
5-4
5-5
5-5
5-5
5-6
5-6
5-8
5-11
5-12
5-12
5-12
5-12
5-13
5-13
5-13

6-1
6-1
6-1
6-2
6-2
6-3
6-3

6.4.2
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10
6.5.11
6.5.12
6.5.13
6.5.14
6.5.15
6.5.16
6.5.17
6.5.18
6.5.19
6.5.20
6.5.21
6.5.22
6.5.23
6.5.24

SA Reg i st er • • • • • • • • • • • • • • • • • . • • • . • • • • • • • • • • •
Internal Hardware Registers •••••••••••••••..••••
Load Interrupt Vector ••••••••••••••••.••••••

Status •••••••
Track ••••••••
Sector •••••••
Data •••••••••

6-3
6-3
6-3
6-5
6-5
6-5
6-5
6-6
6-6
6-6
6-6
6-7
6-7
6-7
6-7
6-7
6-7
6-7
6-7
6-8
6-8
6-9
6-9
6-9
6-9
6-9

CHAPTER 7

SPECIFICATIONS

7.1
7.2
7.3
7.4
7.5
7.6
7.6.1
7.6.2
7.7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Specification ••••••••••••••••••••••••••
Electrical Specifications ••••.••••••••••••••••••
Environmental Specifications •••••••.••••••••••••
Operating Characteristics ••••.••••••••••••••••••
Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital's Data Format •••••••••••••••••••••••
Alternate Data Format •••••••••••••••••••••.•
Supported Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-1
7-1
7-1
7-1
7-2
7-2
7-2
7-2
7-4

APPENDIX

RX180 CABLING

Load System Display . . . . . . . . . . . . . . . . . . . . . . . . .

Load UNIBUS Pointer •••••••••••••••••••••••••
Load UNIBUS Extension •.••.••••.•••••..•••.••
Clear OMA Error Flags ••••••.••••••••••••••••
Load Drive CSR .•••••••••••••••••••••••••••••

Load Transmitter Buffer .••••••••••••••••••••
Load Data CSR •••••••••••••••••••••••••••••••

Diskette Drive Controller Write Command •••••
Diskette Drive Controller Write Track •.•••••
Diskette Drive Controller Write Sector ••••••
Diskette Drive Controller Write Data ••••••••
Diagnostic Interrupt ••••••••••••••••••••••.•
Interrupt UNIBUS ••••.•.••••••••.••••••••.•••
Read PIO Status/Address •.••••••••••••.••••••
Read Receive Buffer •••••••••••.•••••••••••••
Read LUN ••••.•••••••••••••••••••••••••••••••

Read De!1ce Type •••••••••••.••••••••••••••••
Read Drive CSR •••.•••••.••••••••••••••.•••.•
Read Data CSR •••••••••••••••••••••••••••••••

Diskette
Diskette
Diskette
Diskette

Drive Controller
Drive Controller
Drive Controller
Drive Controller

Read
Read
Read
Read

FIGURES
2-1
2-2
2-3
3-1
3-2
3-3
3-4
3-5
4-1

RUX50 Jumper Locations .•••••••••••••••••••••••.•
RUX50 Subsystem Installation ••••••••••••••••••••
Long-Line Adapter Installation •••••.••••••••.•••
RUX50' Circuits ••••..•.••.•••••....•...••••.•.•••

UNIBUS Interface Circuit ••••••••••••••••••••••••
T-11 Processor Circuit ••••.•••••••.•••••••••••••
DMA Control Circuits •••••••••••.••••••••••••••••
Diskette Drive Controller Circuit ••••••.••••••••
Connector Jl Pin Functions ••••••••••••••••••••••

2-3
2-7
2-7
3-2
3-5
3-8
3-12
3-13
4-6

6-1
7-1
7-2
7-3
A-1

Device Type Register ••••••••••••••••••••••••••••
Digital's Data Format •••••••••••••••••••••••••••
Alternate Data Format •••••••••••••••••••••••••••
Supported Drives ••••••••••••••••••••••.•••••••••
RX180 Cabling ..........•••.•••••.........••••.••

6-8
7-3
7-3
7-4
A-1

TABLES
2-1
2-2
2-3
2-4
4-1
4-2

4-3
5-1
5-2
5-3
6-1

Subsystem Configurations ••••••••••••••••••••••••
2-1
Device Address Jumper Configuration •••••••••••••
2-2
Logical Unit Number Jumper Configuration ••••••••
2-5
Device Type Jumper Configuration ••••••••••••••••
2-5
UNIBUS Signal Pin Assignments •••••••••••••••••••
4-2
UNIBUS Signal Descriptions ••••••••••••••••••••••
4-3
Drive Interface Signals •••••••••••••••••••••••••
4-7
Self-Test Sequence •.••••••••••••••••••••••••••••
5-2
Generic Error Code Definitions ••••••••••••••••••
5-3
Error Codes Generated by ZRQA Exerciser ••••••••• 5-14
Hardware Register Definitions •••••••••••••••••••
6-4

CHAPTER 1
INTRODUCTION

1.1

GENERAL INFORMATION

This
manual describes the configurations, installation, and
operation of the RUX50 controller module as a diskette drive
subsystem. The manual identifies associated diskette drives, but
it does not describe them in detail.
•

Chapter 1
features.

briefly

describes the RUX50 and presents its

•

Chapter 2 tells how to configure and install the RUX50 as
a subsystem.

•

Chapter 3 describes the RUX50's operation.

•

Chapter 4 provides
connectors.

•

Chapter 5 covers troubleshooting. It explains how to
interpret errors detected by the RUX50's self-test and
diagnostics.

•

Chapter 6 describes the programmable registers that are
UNIBUS addressable on the RUX50. It briefly covers mass
storage control protocol
(MSCP) and diagnostics and
utilities protocol
(DUP). To give you a better understanding
of the RUX50's operation, Chapter 6 also
describes the internal hardware registers.

•

Chapter 7 lists environmental and functional specifications for the RUX50 as well as data formats and supported
drive characteristics.

detailed

1-1

information

on the RUX50

1.2

RELATED DOCUMENTATION

The following documents provide more information on the RUXS0.
Title

Number

RUX50 Field Maintenance Print Set

MP02006

UDA50 ·programmer's Documentation Kit

QP-905-GZ

RX50-D, -R Dual Flexible Disk Drive
Subsystem Owner's Manual

EK-LEP0l-OM

For extra information, refer to documentation for the system in
which the RUX50 is installed.
1.3

GENERAL DESCRIPTION

The RUX50 (M7522) is a UNIBUS controller for 5-1/4-inch diskette
drives. It is a quad-size, single-board controller that recognizes
a subset of MSCP.
The RUX50 interfaces RX50 diskette drives to any hex-size backplane that implements an 18-bit/16-bit UNIBUS. It also supports
other drives:
Single-density, single-sided, dual diskette drives
Single-density, double-sided, single diskette drives
Double-density, double-sided, single diskette drives.

1.4

FEATURES

The RUX50 has the following features.
•

Is a single, quad-size module.

•

Supports direct memory access
18-bit/16-bit addressing modes.

•

Supports 18-bit addressing on a UNIBUS.

•

Interfaces up to four logical units.

•

Implements
drives
Corporation's.

other

•

Is compatible
diskettes.

Micro/PDP-11

with

1-2

(DMA) data transfers in

than

Digital

Equipment

and Professional RX50

CHAPTER 2
CONFIGURATION AND INSTALLATION

2.1

INTRODUCTION

The RUX50 is a direct memory access (DMA) device that mounts in
any
small
peripheral controller (SPC)
slot of the UNIBUS
backplane. A single RUX50 interfaces up to four logical units-to
the host processor. The RUX50 must conform to valid subsystem
(Paragraph 2.2), jumper (Paragraph 2.3), and cabling configurations (Paragraph 2.4).
RX50 diskette drive is a random access storage device that
~e
uses two single-sided, 133.4-mm (5-1/4-in) RX50K diskettes. The
total storage capacity of the RX50 is 800 kilobytes of formatted
data.

2.2

SUBSYSTEM CONFIGURATIONS

Typically, the RUX50 interfaces one or two RX50s to the host
system. Each RX50 is two logical units. The device type jumpers
(Paragraph 2.3) must be set for each logical unit attached to the
RUX50. Table 2-1 lists acceptable RUX50 subsystems. Dual diskette
drives must start on the first and third logical unit boundaries
assigned to the RUX50 (Paragraph 2.3.2).
Table 2-1

Subsystem Configurations

Configuration

Number and Type of
Diskette Drives

Logical Diskette
Drive Numbers

One RX50

Units 0, 1 = RX50

Two RX50s

Units 0, l = RX50
Units 2, 3 = RX50

One single logical unit
drive

Unit 0 = single unit

One RX50 and one single
logical unit drive

Units 0, 1 = RXS0
Unit 2 = single unit

2-1

2.3

JUMPER CONFIGURATIONS

To change the RUX50's device address, logical unit number, device
type, logical location, and long- or short-line transmission from
their standard settings, reconfigure the jumpers on the RUX50.
Figure 2-1 shows the jumper locations.
2.3.1

Device Address Selection

Figure 2-1 shows the location of the RUX50 address jumpers. Table
2-2 lists the jumper configuration for the standard address,
772150. To configure the RUX50 for an address other than 772150,
use Table 2-2 to determine the appropriate configuration for
address bits A2 through Al3 on jumpers W4 through WlS.

Table 2-2

Device Address Jumper Configuration

Jumper

UNIBUS
Address
Bit

Standard
772150
State

ws
W6
W7

A3
A4
AS

out
in
out

W8
W9
Wl0

A6
A7
AS

out
in
in

Wll
Wl2
Wl3

A9
Al0
All

in
out
in

µi-'r

Wl4
Wl5

Al2
Al3

out
out

r-1

Standard
Binary
State

Standard
Octal
State

r:::, 1
0

0
0

f-t
\-".

.:::r·~

0
1
0

~
~--0
Q_

1
1

<sJ. ~

0
1
1
0
0

2-2

000~

W39

CJ c:::J

CJ c::::J
Cl c::::J

W15

DD~~

CJ c:::J
ICJtJl

INTERRUPT REQUEST
PLUG E39

Figure 2-1

RUX50 Jumper Locations

2-3

MA-1229o84

2.3.2

Logical Unit Number Selection

Figure 2-1 shows the location of the RUX50's logical unit number
(LUN) jumpers. Set these jumpers to the lowest LUN assigned to any
diskette drive controlled by the RUX50. The standard configuration
for the LUN jumpers is 0. Use Table 2-3 to configure the RUX50 for
its LUN.
2.3.3

Device Type Selection

Sixteen jumpers identify each device connected to the RUX50. These
jumpers are standardly configured for the RX50. They are organized
in four groups of four jumpers. The RUX50 supports four logical
units, so each jumper group defines the device for each logical
unit. Dual logical units must occupy the first or third jumper
group. Single logical units can occupy any jumper group as long as
the dual logical units have the first or third. Table 2-4 defines
the jumper states for various drive types. (Refer to the appendix
for drive type descriptions.)
2.3.4

Interrupt Request Level

The RUX50 interrupts at priority level 5, which is determined by
the interrupt request plug in E39. Figure 2-1 shows E39 on the
module.
2.3.S

Long- or Short-Line Selection

The RUX50 supports drive cable configurations that are long and
short. A long-line configuration (standard) allows 40 ft (maximum)
or less of cable between the RUX50 and the drive. A short-line
configuration allows 10 ft (maximum) or less of cable between the
RUX50 and the drive.
Install jumper W49 for long-line configurations and .jumper W50 for
short-line configurations.
NOTE
For most applications, the long-line
configuration is typical. If the total
cable length between the RUX50 and drive
is less than 10 ft, you can use the
short-line configuration.

2-4

Table 2-3

Logical Unit Number Jumper Configuration

First
Logical
Unit

Jumper States
W32
W33
W34

W35

W36

W37

W38

W39

out
out
out
out
out
out
out
out
out

out
out
out
out
out
out
out
out
in

out
out
out
out
in
in
in
in
out

out
out
in
in
out
out
in
in
out

out
in
out
in
out
in
out
in
out

255

0
1
2
3
4
5
6
7

Table 2-4

Device Type Jumper Configuration

Jumper

Bit

W31
W30
W29
W28
W27
W26
W25
W24
W23
W22
W21
W20
Wl9
Wl8
Wl7
Wl6

0
1
2
3

0
1
2
3
0

1
2

Legend
Single-sided,
1
Single-sided,
2
Double-sided,
3
Double-sided,
4

Logical Unit
Location

Jumper States for Device Type
1
2
3
4

First
First
First
First
Second
Second
Second
Second
Third
Third
Third
Third
Fourth
Fourth
Fourth
Fourth

in
out
out
out
in
out
out
out
in
out
out
out
in
out
out
out

out
in
out
out
out
in
out
out
out
in
out
out
out
in
out
out

in
in
out
out
in
in
out
out
in
in
out
out
in
in
out
out

dual drive or RX50 (96 tracks per inch)
dual drive ( 4 8 TPI)
single drive (96 TPI)
single drive (48 TPI)

2-5

out
out
in
out
out
out
in
out
out
out
in
out
out
out
in
out

2.4

SUBSYSTEM INSTALLATION

Install the RUX50
(M7522)
in any slot of the UNIBUS backplane.
Follow these rules when installing the RUX50 into the UNIBUS
backplane.
•

After installing the RUX50, make sure all empty slots
have a grant card (PN G727 or G7273).

•

Remove the nonprocessor request (NPR) grant jumper for
the slot containing the RUX50 from the backplane.

Before installing the RUX50, make sure its jumpers for device
address, logical unit number, device type, logical location, and
longor
short-line
transmission are configured correctly
(Paragraph 2.3).
The RUX50 subsystem consists of the controller module, the signal
cable to the interconnect panel, and the long-line adapter that
installs in the diskette drive. Figure 2-2 shows a typical
subsystem.
Connect the 50-conductor signal cable (PN 17-00743-06) to the Jl
connector on the RUX50. Connect the other end of this cable to the
signal distribution panel in the host cabinet.
NOTE
FCC cabinets already have the mounting
bracket
and interconnect panel. For
other
cabinets,
install a mounting
bracket (PN 74-27292) if necessary.
For all long-line configurations, install the long-line adapter in
the diskette drive (Figure 2-3). The adapter goes between the
drive's interconnect panel and flat ribbon cable. Four jumpers are
on the long-line adapter (Wl, W2, W3, and W4). Jumper Wl is always
removed for RX50s. Jumpers W2, W3, and W4 are installed when the
diskette drive is the last unit or a single unit for daisychained
diskette drives. Remove all the jumpers if the drive is the center
unit in a daisychain configuration.

2-6

*CABLES ARE AVAILABLE IN LENGTHS
OF 9 ft, 12 ft, 15 ft, AND 20 ft. TOTAL
CABLE LENGTH MUST BE LESS THAN 40 ft
(17-00743 + BC17Y + BC17Y::; 40 ft).
MA·1226-84

Figure 2-2

RUX50 Subsystem Installation

MA·1231·B4

Figure 2-3

Long-Line Adapter
Installation

2-7

CHAPTER 3
THEORY OF OPERATION

3.1

INTRODUCTION

This chapter gives a general description of how the circuits on
the RUX50 function. Then it gives a detailed description of each
circuit.
3.2

CIRCUIT OVERVIEW

The
RUX50 has four major circuit functions that interface
5-1/4-inch diskette drives to the UNIBUS. These circuits interact
to store and retrieve data between the UNIBUS controller (host
processor)
and the diskette drives. Figure 3-1 shows these
circuits.
UNIBUS interface circuits
T-11 processor circuits
DMA control circuits
Diskette drive controller circuits
3.2.1

UNIBUS Interface Circuits

These circuits
(Figure 3-1)
contain the MSCP registers and the
UNIBUS interfacing circuits required by a SPC UNIBUS device. They
perform the following standard UNIBUS operations.
•

Initialize the entire
poll (IP) write.

RUX50

via an initialization and

•

Initiate the RUX50 to start polling via a IP read.

•

Read and write the status and address (SA) register from
the UNIBUS.

•

Enable the vector address onto the UNIBUS data lines.

•

Perform DMA request
DMA control circuits.

handshaking between the UNIBUS and

3-1

UNIBUS

::::;

~
<(

w
a:

::::;

::::;
c

z<(

::;;

c
c

::;;
0

ADDRESS

UNIBUS
INTERFACE
CIRCUITS
OMA
CONTROL
BUS

OMA
CONTROL
CIRCUITS

T·11
PROCESSOR
CIRCUITS

T·11
COMMAND
BUS

DISKETTE DRIVE
CONTROLLER
CIRCUITS

<n
:::>

~
0

'--v---'
DISKETTE
DRIVE

Figure 3-1

RUXSftJ Circuits

3-2

3.2.2

T-11 Processor Circuits

These circuits (Figure 3-1) control the operation of the RUXS0.
They contain the microcode that interprets and responds to the
MSCP accesses that the RUX50 receives from the UNIBUS interface
circuits. The T-11 processor circuits perform the following
standard operations.
•

Read and write the SA register from T-11 memory.

•

Load the vector register in the UNIBUS interface circuits
from T-11 memory.

•

Initialize the RUX50 when the UNIBUS interface circuits
detect a IP write. This function includes the following
operations.
T-11 runs preliminary diagnostics.
T-11 reads the SA write register for the length of the
MSCP command/response rings and the interrupt enabling,
and places this data in the RUX50's RAM.
T-11 writes the
ring lengths.

read register with its command and

T-11 then reads the SA write register for ring base low
and ring base high starting addresses.

•

For OMA accesses, the T-11 processor circuits move data
between the OMA data buffer register in the UNIBUS
interface circuits and T-11 memory.

•

T-11 reads and writes the drive control and status
register (CSR) in the diskette drive controller circuits.

•

T-11
reads
and writes between the diskette drive
controller chip (W01793) and the T-11 or T-11 memory.

3.2.3

OMA Control Circuits

These circuits (Figure 3-1) interact with the UNIBUS interface and
T-11 processor circuits to perform OMA transfers between the
host's main memory and T-11 memory. To perform this function, the
OMA control circuits do the following operations.
•

Initiate and monitor DMA transfer requests to the UNIBUS
interface circuits.

•

Generate bus and data transfer synchronization signals
for the UNIBUS interface circuits.

3-3

•

Provide DMA status
processor circuits.

information

•

Provide memory address
interface circuits.

for

on request to the T-11

DMA transfer to the UNIBUS

Diskette Drive Controller Circuits

3.2.4

The T-11 processor circuits control the diskette drive controller
circuits
(Figure 3-1)
to access the diskette drives. To perform
this function, these circuits do the following operations.

•

Receive control information from the T-11 for the drives •

•
•

Receive status information from the drives for the T-11 •
Convert data in T-11 memory to diskette drive formatted
data and send it to the drive.

•

Retrieve diskette drive formatted data from the drive and
convert it to 8-bit words for T-11 memory.

3.3

CIRCUIT DETAILS

This section describes the RUX50's basic architecture and data
path relationships for each major circuit function. Figure 3-1
shows that the RUX50 is a bus-oriented subsystem. The host system
controls the subsystem, and the T-11 processor and DMA control
circuits share it.
3.3.1

UNIBUS Interface Circuits

These circuits (Figure 3-2) consist of the following components.
UNIBUS address transceivers/address match detector
UNIBUS data buffer/transceivers
UNIBUS control transceivers
Port input/output (PIO) read/write SA registers
PIO controller/IP register
DMA request controller
Interrupt controller
DMA data buffer/transceivers
Vector register

3-4

0
(.)

UNIBUS
DATA BUFFER/
TRANSCEIVERS

!;:
Cl)

I
l1l

1-t-1

~§
(.) x

W N

OMA
DATA BUFFER/
TRANSCEIVERS

PIO
READ SA
REGISTER

74LS245
74LS374

..(~

Cl)

::i

<i
zw

PIO
WRITE SA
REGISTER

VECTOR
REGISTER

74LS374

u. u. u.
::i

Cl)

"' ::ia:"' I-::i"' a:"'

::i

>
>
<i (.) ~ (.)

>
0

~~-n·
~ ~ ~$.
w w

UNIBUS
CONTROL TRANSCEIVERS
8641
8640

<i <i

CONTROLLER
LOGIC

c:0 ::ix

z a:
> >
I- I(.) u
"' ::;; z z

I- z
z> 0
Cl)
Cl)

Cl)

a: x a:
0 0 0
zw ..J
..J a:

I-

-)
v

~ a:
0. ~
Cl)
Ci Ci 0

::i

z
(.)
E
g: < >
u. l!l
0.
z z z I- a:

"'
Cl)

Cl)

a: Cl)

>
0

Cl)

"' "'a:

I- ::i
(.) I-

z
l!l ..J
(.)

"'
Cl)

I-

Cl)
Cl)

J NPR

74S112
74LS74
PAL1628

Cl)

::i

Cl)
Cl)

I-

z ::i
0

OMA REQUEST
CONTROLLER

<i 0
..J
<i
<i N ..J Cl)
(.)
0 <i
I- l!l ::;;
~ <
0
Cl)

I-

Cl)

a: a: i= a:
i= I- a: a: "'

MSCPPORT 1/0
CONTROLLER/
IP REGISTER

z I- a:
z (.) u;
::i "'
> <

I-

a:
~
0 ..J
OMA

..J

DAL<15:0>

"' "' "' "'

Cl)

8242
8641

/~ t;

Cl)
Cl)

W15

74LS244
B641

Cl)

UNIBUS
ADDRESS
TRANSCEIVER/
ADDRESS MATCH

,._E_N_D_l_R_2U_B_S_ _ _~ a:,.-.

I-

FROM OMA
Iz ::i
z z
0 0
0
"'.I-REQUEST AND
z ::i
I> >
(.) ..J ..J
E
0
g: E
(.) (.)
INTERRUPT CONTRO LLER
0. ~
a: l(l
l!l "'
<i
c:; ::;;
~ ~
<i 0 z z z

BRS
PLUG

> ICl)

Cl)

5l "'
l!l

z I- Ia: ::;;
> z z 0 a: > ;;'
0
:: ~ ::;; I:r
a: a: a: a:
0.
I-

Cl)
Cl)

Cl)

0
I-

J
INTERRUPT
CONTROLLER
DC013
74LS74

DC013

"'"'a: a:~ I-::i"' 0::i"'
..J
z w
u ;t l!l a:

J.i

l!l

~i
TO
UNIBUS

a:
0

Cl)

"' w
!:: I- 0
~

::i >

~ a:

c: c: c:

OMA CONTROL BUS

T· 11 COMMAND BUS

__,
MA·1232.S4

Figure 3-2

UNIBUS Interface Circuit

3.3.1.1 UNIBUS Address Transceivers/Address Match Detector -This circuit compares the jumpered address to the UNIBUS address.
When an address match occurs (indicating an SA or IP read/write),
this
circuit
asserts
PIOADRDET. PIOADRDET alerts the PIO
controller to enable the appropriate data paths and interrupts in
the RUX50.
This circuit also receives the UNIBUS DMA address (PREBUS<l5:0>)
and UNIBUS address extension (EXUABUS<l7:16>) from the DMA control
circuits. The DMA control signal ENADRSPTR enables this address
onto the UNIBUS address lines.
3.3.1.2 UNIBUS Data Buffer/Transceivers
This circuit is 16
bits wide and passes data between the UNIBUS and the XUD bus. It
is enabled by the DMA controller (through the pio controller) or
by the PIO controller during MSCP accesses.
3.3.1.3 UNIBUS
Control
Transceivers
The UNIBUS control
transceivers buffer and transfer the UNIBUS control signals
between the UNIBUS controller (host processor) and the RUX50.
3.3.1.4 PIO Read/Write SA Registers -- These SA registers are
used by the T-11 and the UNIBUS processor (host computer) for the
MSCP port initialization sequence. These registers occupy the same
UNIBUS I/O page address. The SA write register is written by the
UNIBUS processor and read by the T-11. The SA read register is
written by the T-11 and read by the UNIBUS processor. During the
initialization sequence, the UNIBUS controller writes the MSCP
command buffer address and interrupt vector to the SA write
register for the T-11. The T-11 writes the SA read register with
the initialization status data for the UNIBUS processor. The SA
read and write registers are both 16 bits wide.
3.3.1.5 MSCP PIO Controller/IP Register -- This circuit performs
the following functions simultaneously.
•

It detects MSYN and sends SSYN to or from the UNIBUS
control transceivers after the host processor receives or
sends data.

•

The PIO control logic also enables output and direction
of the UNIBUS data transceiver.

•

The PIO controller decodes the type of transfer by the C0
and Cl signals for an IP read, IP write, SA read, or SA
write.

3-6

•

After
the UNIBUS address transceivers/address match
detector detects a valid address, the PIO controller/IP
register loads the SA write register from the UNIBUS or
enables the SA read register to the UNIBUS.

After receiving a request signal from the interrupt controller
(REQVECTOR) , the PIO controller gates the vector from the vector
register
onto
the
UNIBUS
through
the
UNIBUS
data
buffer/transceivers
and the UNIBUS interrupt signal
(TINTR)
through the UNIBUS control transceivers. The PIO controller sends
interrupt signals (PIOIPWRT, PIOIPRD, PIOSAWRT)
to the T-11
processor circuits whenever the host processor reads or writes the
SA or IP registers.
3.3.1.6 Interrupt Controller and Vector Register -- The interrupt
vector register contains the vector that is gated to the UNIBUS
during an interrupt sequence. The MSCP initialization sequence
supp'lies the T-11 with the vector. The T-11 then loads the
. interrupt vector register. The contents of this register transfers
to the UNIBUS under control of the interrupt controller (via the
PIO controller). The vector register is 8-bits wide and ranges in
value from 0 to 774. The normal interrupt vector is 154 and the
priority level is S.
3.3.2

T-11 Processor Circuits

These circuits (Figure 3-3) consist of the following components.
Interrupt, request, initialize, and asynchronous hold registers
T-11 microprocessor
Mode buff er
Address latch
I/O bit map and memory decode
Random access memory (RAM)
Read-only memory (ROM)
Display register and light emitting diodes (LEDs)
Device register
LUN register
3.3.2.1 Interrupt Request, Initialize, and Asynchronous Hold
Registers
The interrupt request register performs conditional
priority on interrupt requests to the T-11. It stores the results
in the asynchronous holding register
(AHR) every T-11 column
address strobe (CAS)
cycle. The output of the AHR goes directly
into the T-11 interrupt port.
·
The initialize register monitors the UNIBUS AC LO and DC LO
(PWROK)
signals
to determine when to perform power-up or
power-down functions. The register also begins an initialization
sequence when the host processor writes to the IP register or
during UNIBUS initialization.
3-7

I-

z
a
<

I-

0::

I-

0::

0 a:
;: a:
;:
a.

;:
a.

0
!:: a:
;!

rrr

"'a:0

0 0
"'a: 0 :::;
c "'Qa., c: c: a:~ ;:a., -z I-"' "'w "'w
...J

INTERRUPT REQUEST
AND INITIALIZE
REGISTER

PAL16L8

..._

INIT+IPWRT

CLOCK

l _il

ASYN HOLD
REGISTER
74LS274

!::
z

T-11 CLOCK

T-11 MICROPROCESSOR

CNTRLCLK
TODMA
LOGIC

"'a:

~ c
c <
a:

"' g :::; :c"' "'
"' "' "'"' s: s:

IC IC

I- I- WW

...J
(.)

"'
t

DISPLAY
REGISTER
AND LEDS

BCLR

(.)

"'a:

OAL<16•lu1

DAL<14, 11,B,O>

MODE
BUFFER
74LS240
...J

...J

74LS174
74LS244

LDSYSDISP

TODMA
LOGIC

RDDEV

ADDRESS
LATCH

lI~

DEVICE
REGISTER
W31

LUN
REGISTER
W39

DAL<15:0>

l TM::a~6-1J

zw zw

i
T-11 Processor Circuit

3-8

ROM
<l
AM2764

[

:;; :;;
< <
a:
a:

T·11 COMMAND BUS

MEMADR<15:1>

W32 74LS240

Figure 3-3

:c "'
...J
;: ;:

1/0 BIT MAP/
MEMORY DECODE
74LS13B
PAL16LB

wis 74LS240
ENLUN

Jg~

:;; 0
0 a:
0:: :;;
z w
w :;;

3.3.2.2 T-11 Microprocessor, Mode Buffer, Address Latch, I/O Bit
Map, and Memory Decoder -- The supervisory control of the RUX50 is
done by the T-11 with an input clock frequency of 7.5 MHz. During
a power-up sequence, the initialize register (Paragraph 3.3.2.1)
configures the T-11 for the 16-bit mode and enables the T-11 to
use static RAM.
The address latch latches the T-11 memory address onto the memory
address lines
(MAL)
during the address phase of the bus cycle.
This allows the T-11 to point to any specific location in the ROM,
RAM, or I/O bit map memory decoder. The I/O bit map and memory
decoder enables and loads all the registers and devices that the
T-11 can access.
The T~ll performs the following operations.
1.

Sends the host processor status information through the
DMA data buffer register. The DMA controller moves data
from the DMA data buffer to the SA read register. If
prior to the T-11 loading the OMA data buffer register,
the T-11 sets the GOLDSA flag in the OMA data buffer.

Reads the host processor's status information through the
SA write register.

After receiving the host vector address from the SA write
register during port initialization, the T-11 loads the
vector address into the vector register.

T-11 initiates an interrupt to the host processor
~e
when the T-11 finishes performing the instructions in the
host command ring in T-11 RAM. This happens if interrupts
were enabled during port initialization.

Reads and writes the
device type register.

Reads and writes all data from or to the diskette drive
controller chip from T-11 RAM.

Interaction between the T-11 and the OMA control circuits
brings host command rings and data to be written to the
drives into T-11 RAM.

drive

CSR and reads the LUN and

The T-11 loads the source UNIBUS address into the
UNIBUS address registers. The OMA state machine
increments these registers after each word transfer.

The T-11 then polls the DMADONE bit in the DMA data
buff er CSR (DDBCSR) .

3-9

3.3.2.3

If the DMADONE bit is set, the T-11 sets the
GOOMAFUBS bit in the DOBCSR, which initiates the OMA
control circuits to get a word from host memory
referenced from the UNIBUS DMA address pointer.

The T-11 then polls the RCVRFUL bit in the DDBCSR. If
this is set, the T-11 writes the contents of the DMA
data buffer register into the T-11 RAM.

The T-11 then checks its internal word counter to
determine if it should repeat the process. If the
internal word counter is not equal to the number of
words
of a particular transfer, then the T-11
increments its internal T-11 word counter and repeats
steps b through e until the end of a particular
transfer.

Interaction between the T-11 and the DMA control circuits
brings RUX50 response rings and data from the drives to
T-11 RAM for transfer to host memory.
a.

The T-11 ioads the destination UNIBUS address into
the UNIBUS address registers. The OMA state machine
increments these registers after each word transfer.

The T-11 then polls the XMITFUL bit in the OMA data
buffer CSR (DDBCSR).

If the DMA data buffer is empty (XMITFUL = 0), then
the T-11 loads the DMA data buffer register with the
data to be transferred to the host memory from T-11
RAM. The loading of the OMA data buffer initiates the
OMA controller to transfer the word from the DMA data
buffer register to the host memory referenced from
the UNIBUS OMA address pointer.

RAM and ROM

The SK X 16 RAM has three major sections.

T-11 work space
Device control block
Sector buff er
The T-11 address space allocated to the RAM lies between 100000
and 120000 (octal) • The SK X 16 PROM just stores the T-11
instructions.
Its T-11 address space lies between 000000 and
020000.
3-10

3.3.2.4 Display Register and LEDs -- T-11 processor circuits load
the display register. This register controls the LEDs that show
the RUX50's status.
3.3.2.5 Device Type Register
The device type register is a
jumper-configured, 16-bit register. It indicates the type of drive
for each of the four logical units attached to the RUX50. (See
Paragraphs 2.3.3 and 6.5.18 for details.)
3.3.2.6 LUN
Register
The
LUN
register is an 8-bit
jumper-configured register. The T-11 reads this register. (See
Paragraphs 2.3.2 and 6.5.17 for details.)
3.3.3

OMA Control Circuits Detail

The OMA qontrol circuits (Figure 3-4) are made up of the following
components.
OMA controller
Timers
Data buffer CSRs
UNIBUS OMA address pointer/buffer and UNIBUS address
extension register
3.3.3.1 OMA Controller, Timers, and Data Buffer CSRs -- The OMA
controller, when enabled, controls the UNIBUS OMA address pointer,
UNIBUS address extention register, and the UNIBUS address and data
transceivers. It also controls the loading of the SA read
register, the OMA data buffer, and the OMA data buffer CSR. It
operates with a 15-MHz clock input. In a OMA read, the source of
the data is the OMA data buffer register and the destination of
the data is the host memory. Similarly, in a write, the source of
the data is the host memory and the destination of the data is the
OMA data buffer.
The data transfer occurs as an NPR operation and obeys the UNIBUS
OMA protocol. OMA transfers occur in one word transfers per bus
acquisition. The OMA controller sets error flags and process
complete flags in the OMA data buffer CSR after it does a OMA.

3-11

OMA CONTROL BUS

~
OMA
~
GOT
CONTROLLER

TDATDH/DATI

GDLDSA

TMSYN

REQ BUS

GODMAFUBS

w
N

INCADRsJ

CNTRLCLK

T-11{

DMASALD
RINIT'
T·11{

V'
~

CNTRLCLK

ENADRSPTR
tr·l1( CNTRLCLK

TIMEUP

LDUBSPTR

GOLDSA
GODMAFUBS

DEADMAN

RDCVRBUF

CLRGO

LDXMITBUF
74LS23

74LS163

UNIBUS
OMA
ADDRESS
POINTER/
BUFFER

TO
UNIBUS
INTERFACE
CIRCUITS

..!\.
PREBUS<lS:O>

-v

INCADRS

GODMA2UBS/
XMITFUL

LDDATCSR
RSTCNTRL

GOT

EXUABus·17
EXUABUS16

-1'._

BCLR

GOT

TIMERS

UNIBUS
ADDRESS
EXTENTION

LDUBSEXT
DATA
BUFFER
CS Rs

74F374
B2S105

lTIMEUP
RESETIMEUP

CNTRLCLK
INCADRS

ENADRSPTR

.......

GNTUBS

CLRGO

CNTRLTIMEOUT

TIMEUP

PERR

ENDAT2UBS

LDRCVBUF

GODMA2UBS/XMITFUL

T-11{

RSSYN

ENADRSPTR

-"'

CNTRLTIMEOUT
74LS74
74LS244

DAL<lS:O>

RESETIMEUP

74LS163
74LS244

RSTCTRL

L--J

DAL<15:0>

"\[
T-11 COMMAND BUS
MA·t230.84

Figure 3-4

OMA Control Circuits

3.3.3.2 UNIBUS OMA Address Pointer/Buffer and UNIBUS Address
Extension Register
The UNIBUS DMA address pointer/buffe·r and
UNIBUS address extension register consists of five loadable
counters. The T-11 loads the beginning UNIBUS addresses into the
counters.
The T-11 loads the address extension before DMA
operation if an extended address is necessary. The extended
address is incremented if a transfer occurs across a 16-bit
boundary. The output of these buffers goes to the UNIBUS interface
circuit and is placed on the UNIBUS by the DMA controller.
Diskette Drive Controller Circuits

3.3.4

These
circuits
components.

(Figure

are

3-5)

made

the

following

Diskette drive CSR
Data CSR
Diskette drive controller
Data separator/write precompensation
Drive transceivers

T·11 COMMAND BUS

WRITE PROTECT LEDs <3:0>
WR CSR

DRIVE SELECT <4:1>
MOTOR OON

RDCSR

T-11{~
A

741.5244
741.5273

WRITE PROTECT
FLOPPY READ1
HEAD!.OT

~15:~

....

SIDE
DISKETTE
DRIVE
CSR

WRITE PROTECT

~
~
~

FLOPPY READY
INDEX
TRACKO
TKG43
DIRECTION

MEMADRl
T·ll{

MEMADR2

DISKETTE
DRIVE
CONTROLLER

STEP

DISKETTE}~

WR1793

I-'
DAL<7:0>

ODEN

DRIVE WRITE DATA

LATE

DRIVE READ DATA

WRITE DATA IN

EARLY
READCLOCK

LDDATCSR

DATA
BUFFER
CSR

DATA
SEPARATOR
AND WRITE PRECOMPENSATION

READDATA
RST1793
1793

1 MHz

74LS74
DISKETTE{
DRIVE
CSR
CLOCK

PCO
PC1

CLOCK
9229

74LS241

Figure 3-5

W49
W50

WRITE GATE
DRIVE
CSR

RD1793

I--

DRIVE
INTERFACE
TRANSCEIVERS

Diskette Drive Controller Circuit

3-13

74LS244
74LS04
7438
26LS32
26LS31

<=>

DISKETTE
DRIVE

3.3.4.1 Diskette Drive CSR and Data CSR -- The T-11 reads and
writes the diskette drive CSR. The command register accepts a T-11
word that selects one of the four diskette drives and one of three
precompensation values. This word also controls reads and writes
in a single-density or double-density diskette drive format. It
turns the drive motors on and lights the write protect LEDs on the
drives.
NOTE
The T-11 turns all the drive motors off
after no diskette activity has occurred
for about 6 seconds or more to prolong
the life of the drives.
The status register provides the T-11 with a data word that
indicates the selected drive and the precompensation values. This
word
indicates
whether
the RUX50 reads and writes in a
single-density or double-density diskette drive format. It shows
the status of the drive motors and the write protect LEDs. It also
shows whether the drive is ready and whether the selected diskette
is write protected.
The T-11 processor circuits also load the data buffer CSR. This
control register allows the T-11 to reset the diskette drive
controller.
3.3.4.2 Diskette Drive Controller
This controller (WD1793)
performs all drive motor and data manipulations. It controls
stepper motor direction. It also controls the conversion of data
from serial to parallel and parallel to serial from the data
separator/write precompensation circuit. This controller can read
and write serial data in MFM (double density) or FM (single
density) formats.
The T-11 loads the diskette drive controller with sector, track,
data, and command information. The controller checks or generates
a 16-bit cyclic redundancy check (CRC) from or to the selected
drive.

3-14

3.3.4.3 Data
Separator/Write
Precompensation
The data
separator synchronizes the raw read signal from the selected drive
and the free-running clock signal. It does this through a phase
lock loop circuit, which captures the raw data directly from the
drive within the pulse window of the clock.
The write precompensation circuit receives the serial data to be
written to the drive and performs the following functions.
•

Automatically generates
(MFM) bit stream.

modified frequency modulated

•

Automatically precompensates the MFM bit stream.

It has three possible precompensation values, depending on the
position of the head. These precompensation values are selected
from the diskette drive CSR. Depending on whether the early or
late
signals
are
generated
from
the WD1793, the write
precompensation circuit adjusts the delivery timing of the serial
data written to the drive. The operating frequency of the this
circuit is 16 MHz.
3.3.4.4 Drive Interface Transceivers
The drive interface
transceiver communicates directly between the RUX50 and the
diskette drives. Two jumpers allow the the drive transceivers to
pass the read data from long-line or short-line ports on the
connector to the data separator. The output and input of the
transceiver go to a 50-pin connector.

3-15

CHAPTER 4
INTERCONNECTIONS

4.1

INTRODUCTION

This
chapter
provides detailed descriptions of the UNIBUS
connector (Paragraph 4.2) and the drive interface connector
(Paragraph 4.3).
4.2

UNIBUS CONNECTOR

Table 4-1 lists the UNIBUS signal pin assignments that the RUX50
uses, and Table 4-2 defines the signals.
4.3

DRIVE INTERFACE CONNECTOR Jl

The drive interface transceivers on the RUX50 connect to a 50-pin
connector
(Jl) • The transceivers allow direct communication
between the RUX50 and the diskette drives. The transceivers also
provide open collector line driver output. Figure 4-1 shows the
pins on connector Jl. Table 4-3 lists pin signals and their
functions.

4-1

Table 4-1

UNIBUS Signal Pin Assignments

Name

CAl
CBl
CCl
CDl
CEl
CFl
CHl
CJl
CKl
CLl
CMl
CNl
CPl
CRl
CSl
CTl
CUl
CVl

NPG IN
NPG OUT
PA L

CA2
CB2
CC2
CD2
CE2
CF2
CH2
CJ2
CK2
CL2
CM2
CN2
CP2
CR2
CS2
CT2
CU2
CV2

+sv

EAl
EBl
ECl
EDl
EEl
EFl
EHl
EJl
EKl
ELl
EMl
ENl
EPl
ERl
ESl
ETl
EUl
EVl

DAl
DBl
DCl
DDl
DEl
DFl
DHl
DJl
DKl
DLl
DMl
DNl
DPl
DRl
DSl
DTl
DUl
DVl

Dll L

DC LO
PB L
GND
AC LO

INIT L

GND

DA2
DB2
DC2
DD2
DE2
DF2
DH2
DJ2
DK2
DL2
DM2
DN2
DP2
DR2
DS2
DT2
DU2
DV2

GND
Dl5 L
Dl4 L
Dl3 L
Dl2 L
Dl0 L
D09 L
D08 L
D07 L
D04 L
D05 L
001 L
D00 L
D03 L
D02 L
D06 L
+SV
GND
BR7 L
BR6 L
BRS L
BR4 L
BG7 IN
BG7 OUT
BG6 IN
BG6 OUT
BGS IN
BGS OUT
BG4 IN
BG4 OUT

4-2

FAl
FBl
FCl
FDl
FEl
FFl
FHl
FJl
FKl
FLl
FMl
FNl
FPl
FRl
FSl
FTl
FUl
FVl

Name

Al2 L
Al7 L
MSYN L
A02 L
A01 L
SSYN L
Al4 L
All L
Al0 L
A09 L
GND
A06 L
A05 L

SSYN L
BBSY L

NPR L
INTR L

GND

Name

EA2
EB2
EC2
ED2
EE2
EF2
EH2
EJ2
EK2
EL2
EM2
EN2
EP2
ER2
ES2
ET2
EU2
EV2

+SV

FA2
FB2
FC2
FD2
FE2
FF2
FH2
FJ2
FK2
FL2
FM2
FN2
FP2
FR2
FS2
FT2
FU2
FV2

GND
Al5 L
Al6 L
Cl L
A00 L
C0 L
Al3 L
A08 L
A07 L

A04 L
A03 L
+SV

SACK L

Table 4-2

UNIBUS Signal Descriptions

Name

Mnemonic

Number
of Lines

Function

Data Transfer Signals
Address

Al7:00

The current bus master
asserts the address lines.
The host processor can
address the RUX50 registers
and the RUX50 can address
memory locations during OMA
data transfers.

Data lines

015:00

The data lines carry the
word of information that is
being transferred between
the bus master and slave.
Data lines carry commands,
responses, DMA data, and
interrupt vectors.

Control lines

Cl:C0

The bus master asserts the
select lines and specifies
the type of data transfer to
take place. The KLESI-UA
uses and recognizes three
operations.
Name/Cl:C0/Function
Data in/00/0ne word of data
from slave to master
Data out/10/0ne word of data
from master to slave
Data out/11/0ne byte of data
from master to slave

Master sync

MSYN

The bus master asserts and
·negates MSYN, which and is
received by the bus slave.
When MSYN is asserted, the
master tells the slave to
perform the function
dictated by the C lines.
When MSYN is negated, the
master tells the slave that
a data transfer is complete.

4-3

Table 4-2

UNIBUS Signal Descriptions (Cont)

Name

Mnemonic

Number
of Lines

Function

Data Transfer Signals (Cont)
Slave sync

SSYN

The bus slave asserts and
negates SSYN, which is
received by the master. When
SSYN is asserted during a
data transfer, the slave
tells the master that it has
received, the data. The host
(slave) asserts SSYN during
an interrupt to tell the
master that it has received
the interrupt vector.

Parity

PA, PB

The bus slave asserts the
parity error indicators and
the master receives them.
PA = 0, PB = 0: no parity
error exists.
PA = 0, PB
exists.

= 1: parity error

The RUX50 does not use PA.
Interrupt

INTR

The RUX50 asserts INTR to
the host processor after the
RUX50 becomes bus master. It
signals that an interrupt is
to be performed and that an
interrupt vector is on the D
lines.

Priority Arbitration Signals
Bus request

BR7:4

The RUX50 asserts the
appropriate BR line to
request a bus interrupt.

Bus grant

BG7:4

The host processor asserts
the appropriate BG line in
response to a BR and grants
use of bus.

Selection
acknowledged

SACK

The RUX50 asserts SACK in
response to a bus grant.

4-4

Table 4-2

UNIBUS Signal Descriptions (Cont)

Name

Mnemonic

Number
of Lines

Function

Priority Arbitration Signals (Cont)
Nonprocessor
request

NPR

The RUX50 asserts NPR
anytime it is ready to start
a data transfer.

Nonprocessor
grant

NPG

The host processor asserts
NPG to the RUX50 and grants
use of bus for data
transfers.

Bus busy

BBSY

The current bus master
asserts BBSY to all other
devices, indicating that the
data section is in use.

Initialization Signals
Initialize

!NIT

The host processor asserts
INIT and starts a subsystem
reset operation.

AC low

AC LO

AC LO is asserted by any
device on the UNIBUS and is
rec'eived by the RUXS<.J. AC LO
indicates possible failure
and aborts a RUX50 data
transfer if in operation.

DC low

DC LO

DC LO is asserted by any
device on the UNIBUS and is
received by the RUXS0. DC LO
indicates possible failure
and causes a subsystem reset
operation.

4-5

J1=1
J1=2
J1=3
J1=4
J1=5
J1=6
J1=7
J1=8
J1=9
J1=10
J1=11
J1=12
J1=13
J1=14
J1=15
J1=16
J1=17
J1=18
J1=19
J1=20
J1=21
J1=22
J1=23
J1=24
J1=25
J1=26
J1=27
J1=28
J1=29
J1=30
J1=31
J1=32
J1=33
J1=34
J1=35
J1=36
J1=37
J1=38
J1=39
J1=40
J1=41.
J1=42
J1=43
J1=44
J1=45
J1=46
J1=47
J1=4B
J1=49
J1=50

DREADDATA L
DREADDATAH

WRTPRTL
DRVBUSOE L
RXOWPTLED L
RX1WPTLED L
DSTEP H
DSTEP L
DWRTDATAH
DWRTDATA L
DWRTGATEH
DWRTGATE L
TG43L
DRVSEL4 L
INDEX L
DRVSEL1 L
DRVSEL2 L
DRVSEL3 L
RX2WPTLED L
RXMOTORON L
DIRECTION L
STEP L
WRTDATAL
WRTGATE L
TRACKO L
RX3WPTLED L

READDATA L
HEADLOAD L
SIDE L
FLPREADY L

GND
MA-1222·84

Figure 4-1

4-6

Connector Jl
Pin Functions

Table 4-3

Drive Interface Signals

Name and State

Function

DREADDATA L/H

1, 2

Read Data is the data signal input from
the drive for long-line configurations.
It is a twisted pair signal. Data is a
low-going pulse from a minimum of 750
ns to a maximum of 1250 ns for each
flux transition.

WRTPRT L

Write Protect is sampled whenever a
write command is received. When
asserted, it terminates the write
command and reports a write protected
error.

DRVBUSOE L

Drive Present indicates that a diskette
drive is present and powered up.

RX0WPTLED L

Logical unit 0 write protect LED enable

RXlWPTLED L

Logical unit 1 write protect LED enable

DSTEP H/L

15, 16

Step Pulse is a twisted pair signal for
long-line configurations. It carries a
2-us pulse, which is output to the
drive. For every step pulse (6 ms per
step) issued, the drive moves one track
in a direction determined by the
direction control signal (DIRECTION
L/H) •

DWRTDATA H/L

17, 18

Write Data is a twisted pair signal for
long-line configurations. It carries a
250-ns pulse that is generated for each
flux transition. Precompensation is
generated according to the position of
the read/write head. (Precompensation
values and track separation will be
determined.)

DWRTGATE H/L

19, 20

Write Gate is a twisted pair signal for
long-line configurations. This output
is made valid before writing can be
done on the diskette.

TG43 L

Track Greater than 43 indicates that
the read/write head is between track 44
and 79, which lowers the write current
of the head on the drive during a write
operation. The output is valid only
during read and write commands.

4-7

Table 4-3

Drive Interface Signals (Cont)

Name and State

Function

DRVSEL4 L

Select Unit 4

INDEX L

Index Pulse informs the RUX50 when the
index hole is found on the diskette.
Minimum pulse width is 20 us.

DRVSELl L

Select Unit 1

DRVSEL2 L

Select Unit 2

DRVSEL3 L

Select Unit 3

RX2WPTLED L

Logical unit 2 write protect LED enable

RXMOTORON L

Motor Power On turns on the drive's
spindle motor. The spindle motor takes
up to 25 ms to accelerate.

DIRECTION L

Stepping Direction Control is active
low when stepping in and high when
stepping out. It is valid 12 us before
the first stepping pulse is generated.

STEP L

Step Pulse is a 2 us pulse that is
output to the drive. For every step
pulse (6 ms per step) issued, the drive
moves one track in a direction
determined by the direction control
signal (DIRECTION L/H).

WRTDATA L

Write Data is a 250-ns pulse that is
generated for each flux transition.
Precompensation is generated according
to the position of the read/write head.
(Precompensation values and track
separation will be determined.)

WRTGATE L

Write Gate indicates when the write
data is valid. This signal must be
active before writing can be done on
the diskette.

TRACK0 L

Track 00 informs the RUX50 that the
read/write head is over track 00.

RX3WPTLED L

Logical unit 3 write protect LED enable

4-8

Table 4-3

Drive Interface Signals (Cont)

Name and State

Function

READDATA L

Read Data is the data signal input from
the drive. This signal is a low-going
pulse from a minimum of 750 ns to a
maximum of 1250 ns for each flux
transition.

HEADLOAD L

Head Load selects head 0 when high and
head 1 when low for double-sided
drives.

SIDE L

Side Select selects side A when high
and side B when low for double-sided
drives.

FLPREADY L

Floppy Drive Ready indicates that the
diskette drive is ready. This signal is
sampled before read or write commands.
If FLPREADY is low, the read or write
operation is done. If FLPREADY is high,
the read or write operation is not done
and the RUX50 aborts the command. When
the RUX50 is not doing any operation,
it checks the ready lines sequentially
every second for the status of the
drive to indicate volume changes.

4-9

CHAPTER 5
TROUBLESHOOTING

5.1

INTRODUCTION

The RUX50 has several methods for detecting errors.
Self-test at power-up
Self-test at idle states
Self-test at the beginning of IP register writes
Diagnostics
5.2

SELF-TEST

The power-up self-test is a set of firmware routines in the RUX50.
It verifies that the T-11, the ROM and RAM, and the diskette drive
controller are functioning correctly.
The self-test does not test the logic associated with UNIBUS or
the drive data transfers. The test selects the drives to indicate
their presence. This is the only test for the drives.
Four LEDs on the RUX50 give an immediate indication of its pass or
fail status, and they pinpoint the test sequence when a failure
occurs.
The self-test takes less than 5 seconds to complete. It runs
continuously after power-up and during idle states when the RUX50
is not serving a drive. During a IP write, the RUX50 stops running
the self-test and tests the drive control status register (CSR).
This test asserts all the drive select LEDs before starting port
initialization to show that the RUX50 is about to be initialized.
The self-test code is made up of two test routines: Tlltst and
CSRtst. Tlltst tests the T-11, diskette drive controller, and the
ROM and RAM. CSRtst tests the drive CSR and asserts all the
drives' select and write protect LEDs.
If the LEDs never flash on the drives, check the LEDs on the RUX50
to see which test failed. If the self-test does not detect any
errors, the RUX50 loops on Tlltst. CSRtst does not repeat.

5-1

CSRtst also runs at the beginning of each IP write or port
initialization
to
show that the RUXS0 is undergoing port
initialization. Tlltst does not run at port initialization. Table
5-1 shows the power-up and idle state sequence that the RUX50
executes during the self-test.
Table 5-1

Self-Test Sequence

Sequence

LED
States

Routine

Description

0111

CSRtst

Starts at power-up or bus
initialization and when a IP write
is detected. Tests the drive CSR
on the RUX50 and flashes the drive
select and write protect LEDs on
the drives.

0001

Tlltst

Starts testing the T-11 commands
and address modes.

0010

Tlltst

Tests the diskette drive
controller.

0011

Tlltst

Tests the interrupt logic
diagnostic interrupt.

Tlltst

Does a checksum on ROM.

Tlltst

Does a moving inversion test on
RAM.

Tlltst

Leaves the Tlltst routine.

Tlltst

Repeats steps 2 through 7, looping
on the Tlltst. The three lower
LEDs flash in the sequence
described above. The flashing may
not be very noticeable. Looping in
the Tlltst stops when the host
processor requests port
initialization.

5
6

0HH

7
8

0***

1001

Part 1 of port initialization is
complete.

1010

Part 2 of port initialization is
complete.

1100

Part 3 of port initialization is
complete •.

1000

Part 4 of port initialization is
complete or running MSCP or DUP.
5-2

On detecting a fatal error in the operation of the diskette drive
controller, T-11, or the ROM and RAM, the self-test loads an error
code into the RUX50's SA register. The self-test then loops on a
branch instruction to halt the operation of the RUX50. The host
processor must reinitialize the RUX50 to start the self-test and
port initialization sequence again. Table 5-2 provides the error
code definitions that the MSCP receives.
Table 5-2

Generic Error Code Definitions

Error Value
Bits 10--0
Bit 15 Set

SA Error Message

Envelope/packet read error (parity or timeout)

Envelope/packet write error (parity or timeout)

RUX50 ROM and RAM parity error

RUX50 RAM parity error

RUX50 ROM parity error

Ring read error (parity. or timeout)

Ring write error (parity or timeout)

Interrupt master failure

Host access timeout (higher level protocol dependent)

Credit limit exceeded

UNIBUS master error

RUX50 fatal error

Instruction loop timeout

Illegal virtual circuit ID

Interrupt vector illegal

Maintenance read/write invalid region identifier

Maintenance write load to nonloadable RUX50

RUX50 RAM error (nonparity)

Initialization sequence error

5-3

Table 5-2

Generic Error Code Definitions (Cont)

Error Value
Bits 10--0
Bit 15 Set

SA Error Message

Higher level protocol incompatibility error

Purge/poll hardware failure

Mapping register read failure (parity or timeout)

Attempt to set port data transfer mapping when option
not present

501

T-11/CPU failure

502

Nonparity ROM checksum error

5.3

DIAGNOSTICS

The diagnostic
(ZRQAD0) for the RUX50 consists of two parts, the
initialization test and the performance exerciser. The operator
cannot select which of these two parts to run. Both parts execute
sequentially.
NOTE
For
building system exercisers
DECX, the RUX50 module is XRQAD0.
5.3.1

with

Initialization Test

This test verifies the hardware configuration (as specified by the
operator)
and brings each drive unit on-line. The initialization
test precedes the execution of any other test.
The initialization test runs in the following general sequence.
1.

Verifies the presence of each drive unit.

Checks the BR level specified by the operator.

Initializes each RUX50 configured for testing.

Brings each drive unit on-line.

Issues one or two MSCP reads to the innermost logical
block number
(LBN)
of each selected diskette to ensure
that each drive can seek and be read.
5-4

When this test finds fatal or hard drive errors, it drops the
appropriate unit. If basic error messages are enabled, then the
test prints out the reason for dropping the unit. Failed units are
not tested further unless the operator intervenes.
Unit
Summary
During the
5.3.1.1 Initialization
Drop
initialization test, the test drops any drives from the sequence
if it cannot be brought on-line or if the operator-specified drive
does not match the hardware.
5.3.2

Performance Exerciser

This test exercises the drives by simulating a standard operating
system environment. This test shows the operating performance of
the drives. rt uses random diskette addresses, random word counts,
and data patterns. Protected diskettes are subject to read-only
operations.
Unprotected
diskettes can be read or written,
depending on the answers the operator gives to the software
parameter questions. The test declares an end-of-pass when the
specified number of bytes have transferred to all the diskettes.
If a read/write error occurs during this test, then the RUX50
initiates an appropriate number of retries. If all retries fail,
the test reports a hard error to the host processor, displays an
error message on the console terminal, and tallies the error for
the summary report. The test drops the unit if the hard error
count exceeds the specified limit.
5.3.2.1 Performance Exerciser Drop Unit Summary -- During the
exercise, the test drops a unit for one of three reasons.
1.

The test finds an incomplete transfer of N megabytes,
where N is specified by the operator during software
questioning.

The test finds that the number of hard errors exceeds the
operator-specified limit.

The test finds a fatal error.

Units dropped for hard errors can be added to the test cycle
later. However, the diagnostic clears the statistics for the added
unit to 0.
If the operator specified a transfer limit, in which
case the unit was dropped for a soft error, the diagnostic may or
may not clear the statistics. This depends on the operator's
answer to question 10 in Paragraph 5.3.3.2 ••

5-5

5.3.3

Operating Instructions

The operating instructions for this diagnostic are in Chapter 5 of
XXDP+ Operator's Manual. The following paragraphs give detailed
information on the hardware and software questions that the
diagnostic asks before execution.
5.3.3.1
Hardware Configuration Questions
The
following
questions collect the parameters necessary to identify each RUX50
subsystem. The diagnostic asks these questions in response to a
START command.
1.

CHANGE HW (L) ?
Answer NO to use the prebuilt answers for all hardware
questions. This diagnostic tests four units with the
default answers listed at the end of the following
questions. The answers can be changed anytime with the
set-up utility. Answer YES if you want the diagnostic to
ask you all the hardware questions.
NOTE
The first time you run this diagnostic,
answer
YES
to
question 1 to set
parameters
for the RUX50 subsystem.
Then, when you run the diagnostic again
without
changing
the parameters by
answering
NO
to
question
1, the
diagnostic
uses
the
predefined
parameters.

NUMBER OF UNITS (D) ?
This question has no default answer. Answer with the
number of units to be tested. You can specify one to four
units.
This
answer determines how many times the
diagnostic asks the following questions.

IP address (O) 172150 ?
Enter the address of the RUX50's IP register as addressed
by the host processor with memory management turned off.
The diagnostic expects an even 16-bit address from 160000
to 177774. The default answer is 172150.

5-6

Vector (0) 154 ?
Answer with the interrupt vector of the RUX50 described
in question 3. You can specify a vector address from 4 to
774. The default answer is 154.

BR LEVEL [USUALLY 4-RQDXl 5-RUX50]

(0)

4 ?

Answer with the bus request interrupt level used by the
RUX50, which is 5. Levels 4 through 7 are acceptable. The
default answer is 4, but the RUX50 is jumpered for 5.

Drive number (D) 0 ?
Enter the logical unit number
(LUN)
for one drive
associated with the IP register address in question 3.
LUNs range from 0 through 15. The number entered here
must be within the range implied by the jumper (LUN 0--7)
on the RUX50. The default answer is 0.
NOTE
Questions 7 and 8 are actually software
parameter questions. Because different
drives can exist on the subsystem, these
questions become unit-by-unit, hardware
questions.
If selected LBNs are greater
than
the maximum for a drive, the
diagnostic assigns the maximum bounds
for that drive.

Also run DUP exerciser (L) Y ?
This question does not apply to the RUX50 subsystem.
Press RETURN to continue to the next question.

Test entire customer area of this disk (L) Y ?
The default answer to this question is YES because the
operator usually wants to test the entire diskette media.
NO prompts the diagnostic to ask these four questions.
a.

Lower octal word of beginning LBN address (O) 0 ?
Enter the lower octal word for the starting logical
block number (LBN) of the data area you want to test.
LBNs range from 0 to 799. The default answer is 0.

Higher octal word of beginning LBN address (O) 0 ?
Enter the higher octal word for the starting LBN of
the data area you want to test. LBNs range from.0 to
799. The default answer is 0.

5-7

Lower octal word of ending LBN address (D) 177777 ?
Answer this question with the lower octal word for
the LBN of the last data area you want to test. LBNs
range from 0 to 7 9 9. The default answer (177777) is
maximum (799).

Higher octal word of ending LBN address (O) 0 ?
Answer this question with the higher octal word for
the LBN of the last data area you want to test.

WRITE ON CUSTOMER DATA AREA ON THIS DISK UNIT (L) ?
Answering
following
prompt.

YES destroys any data on the diskette. The
warning message appears with a confirmation

** WARNING - CUSTOMER DATA AREA WILL BE OVERWRITTEN! ••
CONFIRM (L) ?
The default answer
hardware questions.

if you decide to bypass the

5.3.3.2 Software Parameter Questions -- The diagnostic asks the
following questions in response to the START, RESTART, and
CONTINUE commands.
1.

CHANGE SW (L) Y ?
Answer NO to bypass the following questions, and answer
NO when you first run the diagnostic. NO causes the
diagnostic to select the default parameters listed with
the following questions. Then, depending on the errors
detected,
change this answer to YES to alter the
parameters and isolate the problem.

Enter time as HHMM
allowed) (D) 0 ?

(Example:

1305 - No leading zeros

Enter the time of day (in 24-hour format). Do not enter
numeric values beginning with 0.
3.

Hard Error limit (D) 32 ?
Enter the number of hard errors allowed before the
diagnostic drops a unit from testing. A number from 1 to
65535 is acceptable.

5-8

Transfer limit in megabytes (0 for "Quick pass")

(D) 0?

When the specified number of bytes have transferred to or
from a unit, the diagnostic drops the unit from testing.
When all units are dropped, the diagnostic indicates an
end-of-pass.
This
method
determines how long the
diagnostic runs.
NOTE
The
only
other way the diagnostic
declares an end-of-pass is if it drops
all units because the errors on each
exceed the limit. You can abort the
diagnostic anytime by holding down the
CTRL key and pressing C.
5.

Percentage of "Fixed
operations (D) 99 ?

Disk"

operations

out

total

The diagnostic adjusts the numbers associated with usage.
It does this according to drive type and percentage to
simulate a normal operating environment.
6.

Clear statistical tables after printing (L) N ?
Answering
YES
causes the diagnostic to clear the
statistical fields to 0 after the summary report prints
(at end-of-pass or at operator request) • Answering NO
maintains cumulative totals.

Want to rewrite
reads (L) y ?

blocks when "Forced Error" detected on

This question does not apply to the RUX50 subsystem.
Press RETURN to continue to the next question.
8.

you want to halt on Bad-block Hard Errors (#s 35, 38)

(L)

y ?

This question does not apply to the RUX50 subsystem.
Press RETURN to continue to the next question.
9.

Do you want to halt
36-37, 39-45) (L) y ?

other Hard Errors (#s 31-34,

When the diagnostic runs with the halt on error (HOE)
switch set (START/FLAGS:HOE), the diagnostic halts on any
error. Answer NO to this question if you want testing to
continue when hard errors are found, even with the HOE
switch set.

5-9

10.

Do you want to halt on Soft Errors (#s 50-54)

(L) N ?

When
the diagnostic runs with the HOE switch set
(START/FLAGS:HOE), the diagnostic halts on any error.
Answer NO to this question if you want testing to
continue when soft errors are found, even with the HOE
switch set.
11.

Count each retry on a Read/Write error as a separate Soft
error (L) N ?
When the diagnostic finds a read or write error, the
RUX50 retries the operation a number of times. If the
operation
is
eventually successful, the diagnostic
reports a soft error. The errorlog packet contains the
number of retries performed before the operation was
successful. Normally, the diagnostic classifies the whole
sequence of retries as one soft error. Answer YES to this
question if you want the diagnostic to count each retry
as a separate soft error.

12.

Random seek mode (L) Y ?
Answer YES to make the diagnostic select LBNs randomly.
Answer
NO
to
make
the
diagnostic
select LBNs
sequentially.

13.

Read-compares performed at the Controller (L) Y ?
Answering YES causes all read commands to include the
compare modifier. This forces the RUX50 to perform two
read operations on the same diskette address and compare
the results.
NOTE
The following message appears after you
answer question 13.
The remaining questions only apply to unprotected disks

14.

Write-compares performed at the Controller (L) N ?
Answering
YES
changes
all write I/O requests to
write-compares.
After each write, the RUX50 reads the
data and compares it to data from the host processor.

5-10

15.

Check all Writes at Host by reading (L) Y ?
The diagnostic asks this question if you answered NO to
question 14. Answering YES to question 15 causes the host
processor to check all writes by reading the data
immediately after a write. This process consumes extra
computing time and doubles the amount of storage required
for
writes.
Answer
YES
when
you suspect drive
write-compares.

16.

User-defined data pattern (L) N ?
Answering YES allows you to define your own data pattern
to be used in all write operations. NO allows you to
select a predefined data pattern in question 18.

17.

Select
pre-defined
selection) (D) 0 ?

data

pattern

for

Sequential

Twenty-one predefined data patterns are available. Select
one by answering with any number from 1 to 21. An answer
of 0 causes the diagnostic to select patterns 1 to 21
sequentially for each write.
18.

Number
(0)

words in data pattern (D) 16 ? pattern values

The diagnostic asks this question if you answered YES to
question 16. The actual bit patterns are entered in octal
form.
5.3.4

Diagnostic Error Reporting

The diagnostic recognizes four types of errors: fatal system
errors, fatal drive errors, hard errors, and soft errors. Fatal
system errors indicate that the diagnostic detected an error in
loading or controlling the diagnostic process. Fatal drive errors
are fatal to the drive, but testing continues. Hard errors result
from soft error retries, an unrecoverable error, or a soft error
when retries are not set. Soft errors are media related. The RUX50
retries all soft errors. The diagnostic retrieves soft errors from
the RUX50 via the errorlog capabilities of MSCP.
All general error messages include the type of error (fatal
system, fatal drive, hard, or soft) and a unit number. If the
error applies to a RUX50, then the message gives only the first
unit number of the RUX50.

5-11

Basic error messages provide more details about the error. The
diagnostic prints all basic error messages along with the diskette
address, if applicable. In some cases where a fatal drive error
applies to a RUX50, the message prints the RUX50's IP register
address.
Extended error messages print the relevant fields of command and
end message packets, status codes, SA register contents, and
errorlog messages. All values are in octal form.
5.3.4.1 Initialization Errors -- The initialization test reports
two types of errors: fatal system errors and fatal drive errors. A
fatal system error means that too many units are specified. A
fatal system error causes the diagnostic to abort. Fatal drive
errors affect only the unit(s) involved. Testing continues on all
other units. Fatal drive errors include, but are not limited to,
the following failures.
Register existence test failure (no drive present)
Vector test failure
BR level test failure
Initialization sequence failure
On-line failure
Access failure
5.3.4.2 Performance Exerciser Errors
Most errors reported
during this diagnostic originate from MSCP end message packets.
The diagnostic translates the status code field to text and prints
it as part of the basic error message. Any subcode value follows
if extended error messages are enabled.
5.3.4.3 Errorlog Messages -- The contents of the errorlog message
from the RUX50 prints as the host processor receives it. You can
decipher the message with the MSCP specifications.
5.3.4.4 MSCP Errors
An MSCP error occurs when the host
processor receives an invalid command end message from the RUX50.
In this case, the host processor prints the erroneous command with
the reason for the error. If extended printouts are enabled, then
the host processor prints the entire contents of the end message
in octal form without data interpretation.

5-12

5.3.4.5 Sample
Error Message
The errors listed by the
diagnostic are usually very descriptive and self-explanatory. The
following example is a sample error message. It is the extended
error message.
DISK xxx
Invalid Comnand
SUB-CODE xxxx
COMMAND: xxxx
LBN: xxxxx
BYTE COUNT IN COMMAND xxxxx
ACTUAL # OF BYTES TRANSFERRED xxxxx

!Disk unit number
!Major status code received back
!Sub-code of given ccmmand
!Conmand given to drive
!Logical block number given
!Number of bytes wanted to read
!Number of bytes actually read

The status code in an end message has two parts. The first five
bits represent the major status code given by the invalid command
message. The 11 remaining bits represent the subcode, which
indicates the error in the RUX50. The LBN is the logical block
number on the diskette that the RUX50 was trying to read. The byte
count refers to the number of bytes the RUX50 was going to read
from the LBN. The actual number of bytes transferred refers to the
number of bytes read before the error.
5.3.4.6 Performance and Progress Reports
A summary report
prints after each pass of the diagnostic or on demand by the
operator.
Depending on how you answer software question 6
(Paragraph 5.3.3.2), the diagnostic may or may not clear the
statistical fields to 0 after the report prints. Any units added
to the test cycle begin with cleared statistics.
Errors listed in this report group into two categories, hard and
soft. Each of these categories divides into four more categories,
depending on the most probable classification for the error.
Diskette errors
Seek (or format) errors
RUX50 or drive errors
Host processor errors
The following example is a
values are in decimal radix.

sample summary report. All numeric

BYTES
-- SFT ERS --- HRD ERS -# OF BYTS # OF
TYPE READS READ WRITES WRITTEN DAT SEK DRV HST DAT SEK ORV HST

x
x
x

xxx xx xx xx xx xxxxx xxxxxx x
xxx xx xx xx xx xxxxx xx xx xx x
xxx xx xx xx xx xxxxx xxxxxx x

UNIT

--- ---- ----- ---- ------ ------- --------------- ---------------

5.3.4.7
codes.

Error

Codes

x
x
x

-- Table 5-3 defines the diagnostic's error
5-13

Table 5-3
Code

Error Codes Generated by ZRQA Exerciser
Fault

Problem

Fatal System Error
1

More than four units are
specified.

Fatal Drive Errors
10

Host processor couldn't
address RUX50.

Wrong IP address selected
at the address given.

RUX50 didn't interrupt at
the interrupt vector given.

Wrong vector address
selected.

RUX50 didn't· interrupt
at the BR level given.

Wrong BR level selected.

Initialization sequence
failed.

Either one of the four
initialization steps did
not receive the correct
response from the RUX50,or
one of the steps timed out.

Fatal error exists in
RUX50.

The error bit (bit 15) in
the SA register was set.

Host processor failed to
bring unit on-line.

On-line response had an
error code. See also codes
22 and 23.

Write protect conflict
exists.

The unit was hardware write
protected and write
operations were requested
on the unit.

Access to the inner or the
outer track failed.

Innermost or outermost
track's header may be
corrupt.

Unit went off-line.

Drive type is not known.

The version of the
exerciser being run does
not support this drive
type.

RUX50 failed to send
the set controller
characteristics command.

Either the unit is offline or the diagnostic is
corrupt because of problems
with RAM.

5-14

Table 5-3
Code

Error Codes Generated by ZRQA Exerciser (Cont)

Problem

Fault

Fatal Drive Errors (Cont)
21

RUX50 returned wrong end
code for the set
controller characteristics
command.

A problem is in the RUX50
microcode or the port/DMA
interface.

Host processor failed to
send on-line command.

Either the unit is offline or the diagnostic is
corrupt because of problems
with RAM.

RUX50 returned wrong
end code for the on-line
command.

A problem is in the RUX50
microcode or the port/DMA
interface.

Drive went to the available
state.

Hard Errors
31

RUX50 received an invalid
command.

The diagnostic is corrupt
because of problems with
RAM. A problem is in the
RUX50 microcode (RAM or
ROM) or in the port/OMA
interface.

Command was aborted by
RUX50.

Command timed out in the
RUX50.

Media format error exists.

Drive is write protected.

RUX50 read or write
compare error exists.

Data error exists.

Host buffer access error
exists.

Controller error exists.

CRC error in the data field
of a diskette block.

This problem is difficult
to categorize without
looking at the error
subcode or associated
errorlog message.
5-15

Table 5-3
Code

Error Codes Generated by ZRQA Exerciser (Cont)

Problem

Fault

Hard Errors (Cont)

Drive error exists.

See code 40.

Host write compare error
exists.

Error detected when host
processor compared the data
written and read. May be a
problem with the host
processor or RUX50 RAM.

Message from internal
diagnostics exists.

See code 40.

RUX50 detected duplicate
unit number.

Unknown end code received.

A problem is in the RUX50
microcode or the port/DMA
interface.

Soft Errors
50

Controller error exists.

See errorlog packet for
details. The exact cause
may not be evident.

Host memory access error
exists.

See code 50.

Drive transfer error exists.

See code 50.

Standard drive interconnect
error exists.

See code 50.

Small disk error exists.

See code 50.

5-16

CHAPTER 6
PROGRAMMING

6.1

INTRODUCTION

The
RUX50 is a direct memory access
(DMA)
interface with
interrupts and 18-bit extended memory addressing. The interface
implements MSCP, therefore, it supports SA and IP registers and
host
handshaking
as
specified
in the UDA50 Programmer's
Documentation Kit (QP-905-GZ).
This chapter discusses the control protocols and bus protocols
that the RUX50 supports and how it conforms to the protocols. This
chapter also defines the programmable and hardware registers.
6.2

CONTROL PROTOCOLS

The RUX50 supports two control protocols: mass storage control
protocol (MSCP) and the diagnostics and utilities protocol (DUP).
6.2.1

Mass Storage Control Protocol

MSCP is the message-oriented set of rules by which the RUX50
communicates with the host processor. MSCP allows the host
processor to send a command message and the RUX50 to send a
response message. The host processor designates an area of memory
as a communication area and tells the RUX50 the location of this
area. The size of the communication area varies and is determined
by the host software. For more information on MSCP, see the UDA50
Programmer's Documentation Kit (QP-905-GZ).
Because drives that use 5-1/4-inch diskettes do not have the
capabilities of larger storage devices, the RUX50 conforms to
MSCP, except for the following commands and subcommands.
•

The RUX50
formats.

does

not generate the following MSCP message

Access path attention m~ssage (not multiported)
Duplicate unit number attention message (no unit plug)

6-1

•

The RUX50 rejects the REPLACE command and all host writes
to the replacement and caching table (RCT) •

•

The
RUX50
reports
all
pertinent device geometry
information except for the following information.
Replacement block numbers (RBNs) per track
Diagnostic block numbers (DBNs) per unit
RCT copies
RCT size

•

Because the RUX50 is not cached or multiported, it
supports the following functions as "no operations"
(NOPs) •
Compare controller data
Determine access paths
Flush

6.2.2

Diagnostics and Utilities Protocol

DUP allows communication between the host processor and the
diagnostic and utilities server task (DUST). This protocol allows
the host processor to request the DUST to load a diagnostic or
utility and execute it. During execution, the host processor can
ask the DUST about the progress of the diagnostic or utility being
executed. The host processor can also abort the diagnostic or
utility after unexpected results. For more information on DUP, see
the UDA50 Programmer's Documentation Kit (QP-905-GZ).
6.3

BUS PROTOCOLS

Because of the type of devices it controls, the RUX50 supports the
following
UNIBUS/Q-Bus
software
services
protocol
(UQSSP)
functions.
•

18-bit bus addressing

•

Software-set interrupt vector

•

Enhanced diagnostic support (data wraparound (SA) and
purge/poll tests)

•

Last failure packet

The RUX50 does not support the following.UQSSP functions.
•
•
•

Burst NPR transfer size
Maintenance read
Maintenance write

6-2

6.4

PROGRAMMABLE REGISTERS

The programmable registers on the RUX50 are the initialize and
poll (IP) register and the status and address (SA) register. These
registers can be addressed as any memory location.
6.4.1

IP Register

The IP register has a standard UNIBUS address of 772150. The
device address jumpers
(Wl through W12) on the RUX50 determine
this address.
(See Paragraph 2.3 for jumper selection information.)
The host processor begins the initialization sequence by issuing a
bus initialization signal or by using the IP initialize operation.
The IP register is not an actual register. It is simply a circuit
that checks for a write at the IP register address. Any write to
that address starts the initialization sequence.
6.4.2

SA Register

The SA register has a standard UNIBUS address of 772152. The
device address jumpers on the RUX50 determine this address.
The SA register consists of two registers, the SA read register
and the SA write register. They are named according to their
function with the host processor.
The T-11 writes to the SA read register, while the host processor
reads from it. This register passes initialization status to the
host processor.
The host processor writes to the SA write register, while the T-11
reads from it. During the initialization sequence, this register
passes the MSCP command buffer address and interrupt vector to the
T-11.
6.5

INTERNAL HARDWARE REGISTERS

The RUX50 has 24 internal registers to control its hardware
functions. The T-11 on the RUX50 accesses these registers •. The
starting T-11 address for this set of registers is 177400. The
registers are write-only and read-only registers. See Table 6-1
for the definitions of these registers.
6.5.1

Load Interrupt vector

Writing to this register defines the interrupt vector that the
RUX50 uses for the host processor.

6-3

Table 6-1

Hardware Register Definitions

Address

Mnemonic

Function

Type

177400

LDVECT

Load interrupt vector

Write-only

177402

LDSYSDISP

Load system display

Write-only

177404

LDUBSPTR

Load UNIBUS pointer

Write-only

177406

LDUBSEXT

Load UNIBUS extension

Write-only

177410

CL RE RR

Clear DMA error flags

Write-only

177412

WRCSR

Load drive CSR

Write-only

177414

LDXMITBUF

Load transmitter buffer

Write-only

177416

LDDATCSR

Load data CSR

Write-only

177420

Reserved

177422

Reserved

177424

Reserved

177426

Reserved

177430

WR1793

Diskette drive controller
write command

Write-only

177432

WRl 793

Diskette drive controller
write track

·Write-only

177434

WR1793

Diskette drive controller
write sector

Write-only

177436

WR1793

Diskette drive controller
write data

Write-only

177440

DIAGINTR

Diagnostic interrupt

Write-only

177442

INTRUBS

Interrupt UNIBUS

Write-only

177444

ROSA

Read PIO status/address

Read-only

177446

RDRCVRBUF

Read receive buffer

Read-only

177450

ENLUN

Read LUN

Read-only

177452

RDDEV

Read device type

Read-only

6-4

Table 6-1

Hardware Register Definitions (Cont)

Address

Mnemonic

Function

Type

177454

RDCSR

Read drive CSR

Read-only

177456

RODA TC SR

Read data CSR

Read-only

177460

RD1793

Diskette drive controller
read data

Read-only

177462

RD1793

Diskette drive controller
read sector

Read-only

177464

RD1793

Diskette drive controller
read track
Diskette drive controller
read status

177466

RD1793

6.5.2

Load System Display

Read-only
Read-only

Writing to this register controls the diagnostic LEDs on the
RUX50. Bits 08 through 11 control the LEDs. Writing to all other
bits does not affect the RUX50.
Bit
08
09
10

LED

6.5.3

1
2
3

Load UNIBUS Pointer

This is a 16-bit register that receives the UNIBUS OMA address.
6.5.4

Load UNIBUS Extension

This register receives the two UNIBUS extended address bits: 16
and 17. Writing to bit 00 is for the extended address bit of 16
and bit 01 is for 17. Writing to bits 02 through 15 has no effect.
6.5.5

Clear DMA Error Flags

This is a strobe-only register that clears the DMA error flags.
The data has no effect.

6-5

6.5.6
Bit
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
6.5.7

Load Drive CSR
Function
Control write protect LED 0 (H turns LED on.)
Control write protect LED 1 (H turns LED on.)
Control write protect LED 2 (H turns LED on.)
Control write protect LED 3 (H turns LED on.)
Enable double density (H enables; L disables.)
Select precompensation 0 (H)
Select precompensation 1 (H)
Logical drive select 1 (H selects drive 1.)
Logical drive select 2 (H selects drive 2.)
Logical drive select 3 (H selects drive 3.)
Logical drive select 4 (H selects drive 4.)
Motor on (H turns on the drive motor.)
Side select (H selects side 0; L selects side 1.)
Load head on selected drive (H loads the read/write head.)
Not used
Not used
Load Transmitter Buffer

This register holds a 16-bit data word for transfer to the host
processor or SA read register.
6.5.8

Load Data CSR

The diskette drive controller
(WD1793) master control (bit 9),
when written to as a 0, resets the diskette drive controller chip.
The GOLDSA (bit 5), when written to as a 1, initializes the OMA
control circuits to perform a OMA transfer to the PIO SA read
register from the data buffer. The data buffer must be loaded
after a GOLDSA for the SA to be loaded. The GODMAFUBS (bit 0),
when written to as a 1, initializes the OMA control circuits to
perform a OMA transfer from the host processor to the data buffer.
Bit
00
05
09
6.5.9

Function
GODMAFUBS
GOLDS A
Diskette drive controller master control
Diskette Drive Controller Write Command

Bits 00 through 07 pass a command to the drive controller on the
RUX50. Writing to bits 08 through 15 has no effect.

6-6

6.5.10

Diskette Drive Controller Write Track

Bits 00 through 07 pass a destination track number to the drive
controller on the RUX50. Writing to bits 08 through 15 has no
effect.
6.5.11

Diskette Drive Controller Write Sector

Bits 00 through 07 pass a destination sector number to the drive
controller on the RUX50. Writing to bits 08 through 15 has no
effect.
6.5.12

Diskette Drive Controller Write Data

Bits 00 through 07 pass data to be written to the diskette by the
drive controller on the RUX50. Writing to bits 08 through 15 has
no effect.
6.5.13

Diagnostic Interrupt

This is a strobe-only register that
interrupt flag. Writing has no effect.
6.5.14

enables

the

diagnostic

Interrupt UNIBUS

This is a strobe-only register that enables the UNIBUS interrupt
flag. Writing has no effect.
6.5.15

Read PIO Status/Address

This register holds a 16-bit, MSCP-defined word containing status
or address data.
6.5.16

Read Receive Buffer

This register
receiver.
6.5.17

holds

16-bit

data

word

from the data buffer

Read LUN

This register holds an 8-bit word containing the logical unit
number, bits 00 through 07. Jumpers W36 through W29 control these
bits. Bits 08 through 15 are not used.

6-7

MA·1224-84

Figure 6-1

6.5.18

Device Type Register

Read Device Type

This register holds a 16-bit word separated into four parts
(Figure 6-1). Each part defines the drive type connected for each
logical unit.
The RUX50 recognizes five device codes that enter this register
from jumpers Wl3 through W28.
Code
0000
0001
0010
0011
0100
6.5.19

Device
None
RX50
RX180
Reserved
Reserved

Description
No device at this logical unit location
Single-sided, double-density, dual unit (96 TPI)
Single-sided, double-density, dual unit (48 TPI)
Double-sided, double-density, single unit (96 TPI)
Doµble-sided, double-density, single unit (48 TPI)

Read Drive CSR

This register contains the status information at the time of the
last executed command.
Bit
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15

Function
Write protect LED 0 (H = LED 0 on)
Write protect LED 1 (H = LED 1 on)
Write protect LED 2 (H = LED 2 on)
Write protect LED 3 (H = LED 3 on)
Double density (H = enabled; L = disabled)
Select precompensation 0 (H)
Select precompensation 1 (H)
Logical drive select 1 (H = drive 1 selected)
Logical drive select 2 (H = drive 2 selected)
Logical drive select 3 (H = drive 3 selected)
Logical drive select 4 (H = d~ive 4 selected)
Motor on (H = drive motor on)
Side select (H = side 0 selected; L = side 1 selected)
Load head on selected drive (H = read/write head loaded)
Selected drive write protected (L)
Diskette drive ready (H)

6-8

6.5.20

Read Data CSR

This status register provides the following status information to
the T-11.
Bit
01
02
03
04
06
07
08
6.5.21

Function
Transmitter full (1 = data transmitter buffer full)
Receiver full (1 = data receiver buffer full)
Timeout (1 = UNIBUS timeout occurred)
Parity error (1 = parity error occurred during OMA operation)
Reset OMA control circuits (1 = OMA control circuits hung)
OMA done (0 = OMA not in process)
Diskette drive controller master reset status (0 = reset)
Diskette Drive Controller Read Status

Bits 00 through 07 contain the drive controller's status word.
Bits 08 through 15 are not used.
6.5.22

Diskette Drive Controller Read Track

Bits 00 through 07 contain the current track number of the
read/write head location. Bits 08 through 15 are not used.
6.5.23

Diskette Drive Controller Read Sector

Bits 00 through 07 contain the current sector number of the
read/write head location. Bits 08 through 15 are not used.
6.5.24

Diskette Drive Controller Read Data

Bits 00 through 07 contain the next data word retrieved from the
diskette. Bits 08 through 15 are not used.

6-9

CHAPTER 7
SPECIFICATIONS

7.1

INTRODUCTION

This chapter provides the hardware specifications for the RUXS0.
It includes information on drives and diskette format to prevent
drive compatibility problems.
7.2

PHYSICAL SPECIFICATIONS

Module
Height
Width
Length
Weight
7.3

Quad-size M7S22
26.S6 cm (10.46 in)
1. 2 7 cm ( 0 • S in)
22.70 cm (8.94 in)
1 lb
ELECTRICAL SPECIFICATIONS

Power requirements
AC bus loads
DC bus loads
7.4

+S Vdc +S% at 2.9 A (typical)
+lS Vdc-+S% at 0.07 A (typical)
2.2

0.S

ENVIRONMENTAL SPECIFICATIONS

Temperature
Storage
Operating

s 0 c to 66°c (40°F to 1S0~F)
s 0 c to S0°C (41°F to 122 F)

Relative humidity
Storage
Operating

10% to 9S%, noncondensing
10% to 9S%, noncondensing

7-1

Altitude
Storage
Operating

9.1 km (30,000 ft) maximum
2.4 km (8000 ft) maximum

Airflow
Operating up to 50°c

7.5

Maximum temperature rise 0 acros5 the
RUX50 must not exceed 20 C (68 F)
input to output.

OPERATING CHARACTERISTICS

Base device address

772150 (typical, jumper selectable)

Vector

Software selectable
(usually set at 154)

Drives per RUX50

Up to four logical units

7.6

DATA FORMATS

The RUX50
formats.
7.6.1

can

read

and

write

Digital' s

standard

diskette

data

Digital's Data Format

In this format, data stores on the diskette in fixed-length
blocks. Each track on the diskette divides into sectors with 512
bytes of data on a track. Each sector has two main fields, an ID
field and a data field. The ID field stores information about the
location of the data. That is, it stores information about which
track, side, and sector where the data resides. The data field
contains the 512 bytes of data to be read or written by the RUX50.
Figure 7-1 represents the format.
7.6.2

Alternate Data Format

The alternate data format on IBM's 5-1/4-inch diskette is similar
to Digital's data format. The alternate data format (Figure 7-2)
does have two differences.
1.
2.

Every track has 4096 bytes of data.
The index mark is in gap 1.

7-2

"GAP 1"

REPEAT ONCE
PER SECTOR

GAP 1:

(A?) X 4E

SYNCH:
IDAM :

DATA:
2CRC :
GAP3:

(B?) X 00
3 XA1
FE
[PHYSICAL TRACK NUMBER)
[PHYSICAL SIDE NUMBER)
[PHYSICAL SECTOR NUMBER)
02 [TRANSLATION;>512 BYTES PER SECTOR)
2 CRC BYTES
22 X 4E
12 x 00
3XA1
FB
512 X E5
2 CRC BYTES
(C?) X 4E

GAP4:

(D?) X 4E

TRACK:
SIDE :
SECTR:
SIZE :
2CRC :
GAP 2 :
SYNCH:
DAM :

LEGEND: FOR EXAMPLE, DIGITAL's FORMAT WOULD USE:
(A?); 47
(B?); B
(C?); 48
(0?)-6250 MINUS (THE SUM OF BYTES UPTO GAP 4).

MA-1221·84

Figure 7-1

Digital's Data Format

GAP1A:
SYNCH:
INDEX:

GAP1B:

"GAP 1"

DATA
2 CRC
GAP3

(B?) X 00
3XA1
FE
[PHYSICAL TRACK NUMBER)
[PHYSICAL SIDE NUMBER)
[PHYSICAL SECTOR NUMBER)
02 [TRANSLATION;>512 BYTES PER SECTOR)
2 CRC BYTES
22X4E
12X 00
3XA1
FB
512 X E5
2 CRC BYTES
(C?) X 4E

GAP 4

(D?) X 4E

SYNCH:
IDAM :

REPEAT ONCE
PER SECTOR

80X4E
12X 00
3XC2
FC
50X4E

TRACK:
SIDE :
SECTR:
SIZE
2 CRC :
GAP 2 :
SYNCH:
DAM

LEGEND: FOR EXAMPLE, IBM's FORMATTED DISKETTE WITH 8 TRACKS:
(B?); 12
(C?); 64
(D?)-6250 MINUS (THE SUM OF BYTES UP TO GAP 4).

Figure 7-2

Alternate Data Format

7-3

7.7

SUPPORTED DRIVES

The RUX50 has a device type register, which can be set through
jumpers. During the initialization sequence, the host processor
reads the device type register and translates each logical unit
with the following characteristics (Figure 7-3).

DEVICE DENSITY HEADS
DEVICE
NAME
PER
TYPE
UNIT
REGISTER

HEAD !TUNNEL MOTOR
DISKS TRACKS STEP
AND
PER
RATE SETTLE ERASE DELAY
(TPI)
TIME
TIME
UNIT

0000

NONE

0001

RX50

DOUBLE

80 (96)

12ms

50 ms

3ms

0.5 s

0010

RX180

DOUBLE

40 (48)

20ms

30ms

3 ms

0011

FUTURE DOUBLE

80 (96)

12 ms

50 ms

3 ms

0.5 s

0100

FUTURE DOUBLE

40 (48)

20ms

50ms

3ms

0.5 s

MA 1223+84
0

Figure 7-3

Supported Drives

7-4

APPENDIX
RX180' CABLING

The
RUX50' can interface RX180 diskette drives. RX180's are
single-density, single-sided, dual-diskette, (5-1/4-inch) drives.
Digital no longer sells or supports RX180's.
To connect a RX180 to the RUX50, configure the RUX50 as described
in Chapter 2 for a single-sided, dual-drive (48 TPI) controller.
Build a cable to connect the RX180' and RUX50 by following the
point-to-point connector chart in Figure A-1.

034 018 01
0
0

~0---1-1------------,
0

:U--1-------------.

.....-----1--~-035

0
'"'20 0
..---.i--.i-----+-.J"\-0~37 ~
0

0
0
~-1---1--+----1---n22
..----l---l--+--1-----+--0-0'39..,.
0

Oo--t-----.

:o--.i-------.

~u--------.1

~o---t------+-----+---+---1--------'

0
0
0
0
0

~05---+----~

0
,..._7

'--+---1------1---+--1---+---+----1--~41"'24 ~o=-s-t----.

( ) . u - - t - - -......

:
U-+-----1----+--+--+---------'
0-

~U-+----1---1-----t---+--t-----------'
13

::;--

0
0
0

;:_,,___s_.....,

-'"'26 ..,-

0
0
0
0

0
0

0
0
0

~u--15-t---t--t----t----+--i

0
033
050
017

CONNECTOR
RX180

1
2
3
4
5
6
7

8
9
10

11
12
13
14-25

RUX50
CONNECTOR

SIGNAL NAME
DRIVE SELECT 4
INDEX SELECTOR
DRIVE SELECT 1
DRIVE SELECT 2
DRIVE SELECT 3
MOTOR ON
DIRECTION SELECT
STEP
WRITE DATA
WRITE GATE
TRACK DO
WRITE PROTECT
READ DATA
GROUND

Figure A-1

RX180' Cabling

A-1

Digital Equipment-Corporation • Maynard, MA 01754