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EK-M9301-TM-001

June 1977

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Document:	M9301 Bootstrap/Terminator Maintenance and Operator's Manual
Order Number:	EK-M9301-TM
Revision:	001
Pages:	134
Original Filename:	http://bitsavers.org/pdf/dec/unibus/EK-M9301-TM-001_M9301_Bootstrap_Terminator_Module_Maintenance_and_Operators_Manual_Jun77.pdf

OCR Text

M9301
bootstrap/terrninator
module maintlsnance and
operator's manual

'-------- ~~- ~-- -- - ~ -- - -----

EK-M9301-TM-OOI

M9301
bootstrap/terrninator
module maint,snance and
operator's manual

digital equipment corporation • m'aynard, massachusetts

18t Edition, June 1977

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL's DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem-IO
DECSYSTEM-20

DECtape
DECUS
DIGITAL
MASSBUS

9/77-14

PDP
RSTS
TYPESET-8
TYPESET-I 1
UNIBUS

Page
CHAPTER 1

INTRODUCTION

1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.5
1.5.1
1.5.2
1.5.3
1.5.4

GENERAL DESCRIPTION
FEATURES . . . . . . . . .
PHYSICAL DESCRIPTION
ELECTRICAL SPECIFICATIONS
External Electrical Interfaoes
Electrical Prerequisites ... .
Timing . . . . . . . . . . . .
Operating Environmental Specifications
INSTALLATION . . . . . .
Power-Up Reboot Enable
Low ROM Enable
Boot Switch Selection
External Boot Switch

CHAPTER 2

HARDWARE DESCRIPTION

2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.5

2.7
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.9
2.10
2.11

GENERAL
...... .
DEFINITION OF TERMS . .
POWER-UP SEQUENCE
POWER-UP BOOTING LOGIC
Power-Up and Power Down
Processor Reads New Program Counter
Processor Reads New Status Word
Power-Up Reboot Enable Switch
EXTERNAL BOOT CIRCUIT . . . . .
POWER-UP TRANSFER DETECTION LOGIC
POWER-UP CLEAR . . . . . . .
ADDRESS DETECTION LOGIC
M9301 Address Space
M9301 Memory Access Constraints
Low ROM Enable Switch
ROM Address Generation
ADDRESS OFFSET SWITCH BANK
ROMMEMORY . . . .
M9301 TERMINATOR . . .

CHAPTER 3

THE CONSOLE EMULATOR

3.1
3.2
3.3
3.3.1
3.3.1.1
3.3.1.2

GENERAL
........ .
SYMBOLS . . . . . . . . . .
USING THE CONSOLE EMULATOR
Successive Operations
Examine
Deposit . . . . .

2.6

iii

1-1
1-1

1-1
1-3

1-3
1-3

1-3
1-3
1-3

1-5
1-6
1-6
1-6

2-1
2-1
2-1
2-2
2-2
2-2
2-2
2-3
2-3
2-3
2-5
2-5
2-5
2-5
2-5
2-7
2-7
2-7
2-10

3-1
3-1

3-1
3-7
3-7
3-7

CONTENTS (CONT)
Page

3.3.1.3
3.3.1.4
3.3.2

3.4
3.4.1
3.4.2
3.5

Alternate Deposit-Examine Operations
Alternate Examine-Deposit Operations
Limits of Operation . . . . . . . . . . . .
BOOTING FROM THE KEYBOARD . . . . . .
Booting the High-Speed Reader Using the Console Emulator
Booting a Disk Using the Console Emulator ..
RECOVERING FROM ERRORS IN THE CONSOLE
EMULATOR ROUTINE
............. .

CHAPTER 4

BOOTSTRAPPING - M9301-YA, -YB, -YE, -YF, -YJ

CHAPTERS

EXTENDED ADDRESSING

5.1
5.2
5.3
5.4
5.5
5.6

GENERAL
......................... .
VIRTUAL AND PHYSICAL ADDRESSES . . . . . . . . . .
ADDRESS MAPPING WITHOUT MEMORY MANAGEMENT
ADDRESS MAPPING WITH MEMORY MANAGEMENT
CREATION OF A VIRTUAL ADDRESS
CONSTRAINTS . . . . . . . . . . . . . . . . . . . . .

CHAPTER 6

M9301-O

6.1

6.2

GENERAL
. . . . . . . . . . '... .
PROM PROGRAMMING PROCEDURE

CHAPTER 7

M9301-YA

7.1
7.2
7.3
7.4
7.5
7.5.1
7.5.2
7.6

INTRODUCTION . . . . .
BOOTSTRAP PROGRAMS
MICROSWITCH SETTINGS
PROGRAM CONTROL THROUGH THE MICROSWITCHES
DIAGNOSTIC PROGRAMS . . . . . . .
Primary CPU Tests . . . . . . . . . . . . . . . . . .
Secondary CPU and Memory Tests . . . . . . . . . .
TROUBLESHOOTING THROUGH REGISTER DISPLAY

CHAPTER 8

M9301-YB

8.1
8.2
8.3
8.4
8.4.1
8.4.2
8.5

INTRODUCTION . . . . .
BOOTSTRAP PROGRAMS
MICROSWITCH SETTINGS
DIAGNOSTICS . . . . . .
Primary CPU Tests ..
Secondary CPU and Memory Tests
TROUBLESHOOTING THROUGH REGISTER DISPLAY

3-8
3-8
3-8
3-8
3-9
3-10
. 3-10

5-1
5-1
5-1
5-1

5-2
5-3

6-1
6-1

7-1
7-1

7-2
7-3
7-3
7-5
7-8
. 7-10

8-1
8-1

8-2
8-5
8-5
8-8

8-9

CONTEN1~S (CONT)

Page
CHAPTER 9

M9301-YC

9.1
9.2
9.3
9.4
9.5
9.6
9.6.1
9.6.2
9.6.3
9.7

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIAGNOSTIC TEST EXPLANATION . . . . . . . . . . . . . . . . . . . .
DIAGNOSTIC TEST DESCRIPTIONS . . . . . . . . . . . . . . . . . . . .
PDP-ll/70 BOOTSTRAP . . . . . . . . . . . . . .
. . . . . ..
MICROSWITCHES . . . . . . . . . . . . . . . . .
STARTING PROCEDURE
. . . . . . . . . .
. . . . ..
Console Switch Settings
Starting Addresses .
Operator Action
ERRORS . . . . . . . .

CHAPTER 10

M9301-YD

10.1
10.2
10.3
10.4
10.5
10.6

INTRODUCTION . . . . . . . . . . . . . . . . .
NORMAL BOOTSTRAP (173000) . . . . . . . . .
SECONDARY MODE BOOTSTRAP (173006) .
FLOPPY BOOTSTRAP (173700) . . . . .
SENDING DDCMP MESSAGES . .
RECEIVING DDCMP MESSAGES

CHAPTER 11

M9301-YE

11.1
11.2
11.3
11.4
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.6
11.7

INTRODUCTION . . . . . . . .
PROGRAM MEMORY MAP
MICROSWITCH FUNCTIONS
...... .
BOOTSTRAPPING PAPER TAPE
DECNET BOOTSTRAPPING: DUll, DLI1-E, DUPl1
Primary Bootstrap ..
Secondary Bootstrap . . . . . . . . .
Tertiary Bootstrap . . . . . . . . . . . . . . .
MOP Message Formats . . . . . . . . . . . . .
POWER-UP BOOT AND CONSOLE BOOT . . . . .
LOAD ADDRESS AND START PROCEDURE VIA
CONSOLE SWITCH REGISTER . . . . . . . . . . . .
OPERATION OF THE M9301-YE CONSOLE EMULATOR
RESTARTING AT THE USER POWER FAIL ROUTINE
DIAGNOSTICS . . . . . . . . . . . . .
CPU Tests
Secondary CPU and Memory Tests
TROUBLESHOOTING . . . . .
...... .
FLOATING DEVICE PRIORITY . . . .

11.8
11.9
11.10
11.10.1
11.10.2
11.11
11.12

9-1
9-2
9-2
9-6
9-6
9-8
9-8
9-8
9-9
9-9

10-1
10-2
10-3
10-3
10-3
10-3

11-1
11-1
11-2
11-3
11-3
11-3
11-3
11-3
11-5
11-6
11-6
11-8
11-9
11-9
11-9
11-15
11-16
11-17

CONTENTS (CONT)
Page
CHAPTER 12

M9301-YF

12.1
12.2
12.3
12.4
12.5
12.6
12.6.1
12.6.2
12.7
12.8

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . .
OPERATION OF THE M9301-YF
............... .
MICROSWITCH SETTINGS
.................. .
PROGRAM CONTROL THROUGH THE MICROSWITCHES
LOAD ADDRESS AND START MODE . . . . .
DIAGNOSTICS . . . . . . . . . . . . .
Primary CPU Tests . . . . . . . . . . . . . . . . . .
Secondary CPU and Memory Tests . . . . .
TROUBLESHOOTING . . . . . . . . . . . . . . . . .
RESTARTING AT THE USER POWER FAIL ROUTINE

CHAPTER 13
13.1
13.2
13.3
13.4
13.5
13.6
13.6.1
13.6.2
13.6.3
13.6.4
13.7
13.8

M9301-YH
INTRODUCTION . . . . . . . . . . . .
MEMORYMAP . . . . . . . . . . . . .
DIAGNOSTIC TEST EXPLANATION
DIAGNOSTIC TEST DESCRIPTIONS
INSTALLATION . . . . . . . . . . .
STARTING PROCEDURE . . . . . . . . .
Power-Up Start . . . . . . . . . . . . .
. . . . .
Power-Up Boot Examples (11/60 only)
.....
Load Address Start Mode
.......
. . . . .
LOAD ADDRESS and START Examples (11/70 only)
ERRORS . . . . . . . . . . . . . . . . . . . . .
OPERATOR ACTION AND ERROR RECOVERY . . . . .

CHAPTER 14

M9301-YJ

14.1
14.2
14.3
14.4

INTRODUCTION . . . . . . . . . . . . . . . . . . . . .
PROGRAM MEMORY MAP
.............. .
MICROSWITCH FUNCTIONS
............ .
BOOTSTRAPPING PAPER TAPE, FLOPPY DISK, AND
MAGNETIC TAPE
.............. .
BOOTSTRAPPING THE DMCII-DECNET
Primary Bootstrap ..
. Secondary Bootstrap . . . . . . . . .
Tertiary Bootstrap . . . . . . . . . .
MOP Message Formats . . . . . . . . .
POWER-UP BOOT AND CONSOLE BOOT ..
LOAD ADDRESS AND START PROCEDURE VIA
CONSOLE SWITCH REGISTER . . . . . . . . . . . . .
OPERATION OF THE M9301-YJ CONSOLE EMULATOR
RESTARTING AT THE USER POWER FAIL ROUTINE
DIAGNOSTICS . . . . . . . . . . . . . . . . . . . . . . . . .

14.5
14.5.1
14.5.2
14.5.3
14.5.4
14.6
14.7
14.8
14.9
14.10

12-1
12-2
12-3
12-4
12-5
12-9
12-9
12-12
12-13
12-13

13-1
13-1
13-2
13-2
13-5
13-6
13-7
13-7
13-11
13-12
13-12
13-12

14-1
14-1
14-2
14-3
14-3
14-3
14-4
14-4
14-4
14-7
14-9
14-9
14-10
. 14-10

CONTENTS (CONT)
Page
14.10.1
14.10.2
14.11
14.12

CPU Tests
Secondary CPU and Memory Tests
TROUBLESHOOTING . . . . . .
FLOATING DEVICE PRIORITY .. .

14-10
14-15
14-16
14-17

FIGU:RES
Figure No.
1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
2-7

2-8
2-9
3-1
6-1
6-2
7-1
7-2
7-3
8-1

8-2
8-3

9-1
9-2
9-3
10-1
10-2
11-1
11-2
11-3
11-4
12-1

12-2

Title
Bootstrap/Terminator Module . . . . . . . . . . . . .
M9301 Timing . . . . .' . . . . . . . . . . . . . . .
Offset Switches and Corresponding Bus Address Bits
Power Fail Sequence
. . . . .
Power-Up Boot Logic
External Boot Circuit
External Boot Timing
Transfer Detection Logic
Power-Up Clear Logic
Address Decoder Logic
Address Offset Switch Bank
M9301 ROM Memory . . . .
Console Emulator Routine Flowchart
PROM Pin Connection Diagram .. .
PROM Internal Logic . . . . . . . . .
Program Memory Map for the M930 1-YA
Offset Switches and Corresponding Bus Address Bits
M930 1-YA Program Flowchart . . . . . . . . . . .
Program Memory Map for the M9 30 1-YB . . . . . . .
Offset Switches and Corresponding Bus Address Bits
M930 1-YB Program Flowchart . . . . .
Program Memory Map for the M9 30 1-YC
Microswitch Assignment . . . . . . . . .
M9301-YC Program Flowchart . . . . .
Offset Switches and Corresponding Address Bits
M9301-YD Program Flowchart . . . . . . . .
M9301-YE Program Memory Map . . . . . . .
Offset Switches and Corresponding Bus Address Bits
M9301-YE Down Line Load Flowchart
M930 1-YE Operator's Flowchart
M9301-YF Memory Map
..... .
Program Flowchart for the M930 1-YF

vii

Page
1-2
1-5
1-5
2-2
2-3
2-4
2-4
2-4
2-5
2-6

2-8
2-9
3-3
6-1
6-2
7-1
7-3
7-4
8-1
8-3

8-4
9-1
. . . . .. 9-6
9-7
10-1
10-2
11-1
11-2
11-4
11-11
12-1
. . . 12-3

FIGURES (CONT)
Figure No.
12-3
12-4
13-1
13-2
13-3
14-1
14-2
14-3
14-4

Title
M9301-YF Flowchart
......... .
M930 1-YF Load Address and Start Mode Flowchart
M930 1-YH Program Memory Map
M9301-YH Used with PDP-l1/60
M9301-YH Used with PDP-11/70
M930 1-Yl Program Memory Map
Offset Switches and Correspondence Bus Address Bits
M9301-Yl Down Line Load Flowchart
M930 1-Yl Operator's Flowchart
......... .

Page
12-6
12-8
13-1
13-9
13-11
14-1
· 14-3
· 14-5
14-11

TABLES
Table No.
1··1
3.. 1

5-1
5··2
7-1
7-2
8-1
8-2
9··1
11-1
11-2
11-3
12-1
12-2
12-3
13-1
13-2

14-1
14-2

14-3

Title
M9301 Modified Unibus Pin Assignments
Deposit Errors: Useful Examples
Unibus Address Assignments
..... .
Reloca tion Constants . . . . . . . . . .
Bootstrap Routine Codes for the M9301-YA
Options and Corresponding Switch Settings
Bootstrap Routine Codes for the M9301-YB
Options and Corresponding Switch Settings
Error Halts
........ .
Microswitch Settings
Load Address and Start Codes
Bootstrap Programs . . . . .
M9301-YF Bootstrap Programs
Options and Corresponding Switch Settings
Load Address and Start
Microswitch Functions
Error Halts Indexed
Microswitch Settings
Load Address and Start Codes
Bootstrap Programs

viii

Page
1-4
· 3-11
5-2
5-2
7-2
7-5
8-2
8-3
9-9
11-7
11-8
11-8

12-2
12-4
12-7
13-5
13-13
· 14-8
· 14-9
14-10

PREFACE

This manual describes the M9301 Bootstrap/Tel'lrninator module and its various versions. Complete
understanding of the manual requires that the user have a general knowledge of digital circuitry and a·
basic unde:rstanding of PDP-II computers. The following related documents may be valuable as
references.
PDP-II Peripherals Handbook
PDP-II Processor Handbooks
PDP-l 1/34, 11/04 User's Manual
PDP-ll/70 Systems Manual
Drawing Directory B-DD M9301-0 (for ROM listings)

CHAPTER I
INTRODUCTION

1.1 GENERAL DESCRIPTION
The M9301 contains a complete set of Unibus termination resistors along with 512 words of read-only
memory which can be used for bootstrap programs, diagnostic routines, and the console emulator
routine. The module also provides circuitry for initiating bootstrap programs either on power-ups or
from an external or logic level switch closure. Se:e Figure I-I for a photo of the module.
1.2 FEATURES
•

A vailable features depend on the variation used.

•

The M9301 combines Unibus termination and bootstrap capability on one double height
lmodule.

•

Can be used in PDP-II machines which can handle an extended length module in the terminator slots. (The M9301-YC can be used only in a PDP-I 1/70 system.)

•

Bootstrap programs may be initiated by the following means:
1.
2.
3.
4.

•
•

Direct program jumps to the menlory space occupied by the bootstrap.
Programmer's console load address and start sequence.
Power restarts (Paragraph 2.3).
External boot switch closure.

Provides capability of enabling or disabling boots on power restarts.
Provides 512 words of user memory space which can be programmed by the user or purc~hased with standard patterns provided by DEC.

The first two chapters of this manual describe features of the M9301 which apply to all versions.
Chapters 3, 4, and 5 do not pertain to the -YC and -YH versions.
The remaining chapters deal with the programm:ing information and specific functions for each version. One chapter is devoted entirely to each v(~rsion, so that the reader need not search through
irrelevant information to find what he needs.

1.3 PHYSICAL DESCRIPTION
The M9301 is a double height extended, 21.6 X 14 cm (8-1/2 X 5-1/2 in) Flip-Chip module which
plugs into the A and B terminator slots on the PDP-II backplane.

1-1

PROMS

MICRO-SWITCHES

sa61

Figure 1-1

Bootstrap/Terminator Module

1-2

1.4 ELECTRICAL SPECIFICATIONS
Power Consumption
+5 Vdc - 2.0 A typical
Electrical Interfaces

The Unibus interface is standard using 8837 and 8640 receivers and 8881
drivers.

1.4.1 External Electrical Interfaces
The external interface consists of three Paston tabs (TP1, TP2, and TP3) provided at the handle end of
the module. The following loading and usage constraints apply.
TPI

Represents one standard TTL load with a lK ohm pull-up. Input should be stable
during a power-up. Refer to Paragraph 2.4 for TP1 usage.

TP2

Represents two standard TTL loads with a 1 kilohm pull-up resistor. Input signals
should be limited to a lOOns minimum pulse width with all switch bounce noise
restricted to a 5 ms maximum duration. Note that triggering is initiated upon
release of an input low (logic 0) pulse. On all power-ups, triggering is disabled
until approximately 100 ms after power returns (Paragraph 2.7), assuming that +5
Vdc will be available from the power supply within 20 ms. It is also important to
realize that this input has no high voltage protection capability and adequate
filtering must be provided when locating this input outside the standard DEC
computer enclosure. Refer to Paragraph 2.5 for TP2 usage.

TP3

Should be used as a ground return for external switches attached to TP1 and TP2.
Note that there is no protection for large voltage spikes on this input so proper
filters should be externally installed to guarantee adequate isolation.

1.4.2 Ele'ctrical Prerequisites
Refer to Chapter 6 and following for system constraints on the specific version being used.
Power and Ground Pinouts (Refer to Table 1-1 for pin assignments.)
+5 V dc: Pins AA2, BA2
GND: Pins AC2, AT1, BC2, BTl
1.4.3 Timing
Figure 1-2 shows important timing constraints for the M9301. Values shown are typical.
1.4.4 Oplerating Environmental Specifications
Temperature Range
5° C to 50° C
Relative Humidity

20% to 95% (without condensation)

1.5 INSTALLATION
As a unive:rsal bootstrap/terminator module, the M9301 in its various versions, can be adapted by the
user to m(~et a variety of boot requirements and system configurations. Major factors that must be
considered during installation concern the address offset microswitches and the external boot switch.
Figure 1-3 shows the relationship between the switches and the lower nine bus address bits.

1-3

Table I-I

M9301 Modified Unibus Pin Assignments

Signal

AAI
AA2
ABI
AB2
ACI
AC2
ADI
AD2
AEI
AE2
AFI
AF2
AHI
AH2
AJI
AJ2
AKI
AK2
ALI
AL2
AMI
AM2
ANI
AN2
API
AP2
ARI
AR2
ASI
AS2
ATI
AT2
AUI
AU2
AVI
AV2

BUS INIT L
POWER (+5 V)
BUSINTRL
TEST POINT
BUS DOO L
GROUND
BUSD02L
BUS DOl L
BUS D04 L
BUSD03 L
BUSD06L
BUSD05 L
BUSD08 L
BUSD07 L
BUS DIO L
BUSD09L
BUS D12 L
BUS Dll L
BUS D14 L
BUS D13 L
BUS PAL
BUS D15 L
PI
BUS PBL
PO
BUS BBSY L
BAT BACKUP +15 V
BUS SACK L
BAT BACKUP -15 V
BUS NPR L
GROUND
BUS BR 7 L
+20V
BUSBR6L
+20V
+20V

BAI
BA2
BBI
BB2
BCl
BC2
BDI
BD2
BEl
BE2
BFl
BF2
BHl
BH2
BJI
BJ2
BKI
BK2
BLI
BL2
BMI
BM2
BNl
BN2
BPI
BP2
BRI
BR2
BSI
BS2
BTl
BT2
BUI
BU2
BVI
BV2

SPARE
POWER (+5 V)
SPARE
TEST POINT
BUS BR 5 L
GROUND
BAT BACKUP +5 V
BR4 L
INT SSYN
PAR DET
BUSACLOL
BUS DCLOL
BUSAOI L
BUSAOOL
BUSA03 L
BUSA02 L
BUSA05 L
BUS A04 L
BUS A07 L
BUS A06 L
BUS A09 L
BUSA08L
BUS All L
BUS AlO L
BUS A13 L
BUS A12 L
BUS A15 L
BUS A14 L
BUS A17 L
BUS A16 L
GROUND
BUSCIL
BUSSSYNL
BUS CO 1
BUS MSYNL
-5 V

1-4

BUS AC LO L

----.J

UNIBUS ADDRESS TRUE

\---166

=-:t

---------

BUS MSYN L

I 60

I
I.

·1

24·0

11-4868

Figure 1-2

LOW ROM ENABLE

:M9301 Timing

POWER UI' REBOOT ENABLE

•+

-I 1 12

CORRESPONDING
BUS ADDRESS BITS
BINARY VALUE
OF SWITCHES
OCTAL VALUES
OF SWITCHES

:1(

x x

S1
SWITCHES

V
ON = 0
OFF = 1

Figure 1-3

11-4865

Offset Switches and. Corresponding Bus Address Bits

1.5.1 Power-Up Reboot Enable
Automatic booting on all power-ups can be enabled or disabled using the POWER UP REBOOT
ENAB switch (S 1-2). If this dip switch is set to the OFF position, the processor will power up normally, obtaining a new PC from memory location 248 and a new PSW from location 268. When the
switch is in the ON position during a power-up, the processor will obtain its new PC and PSW from
locations 173024 and 173026 respectively. The address of BOOT SELECT switches SI-3 through SI-10
is 173024.
The function performed by the REBOOT ENABLE switch (S 1-2) can be controlled by an external
switch using the Faston tabs on the M9301 module. This external switch closure should be made to
ground (enabling boot) using Faston tab TP3 as a ground return. In the PDP-ll/04 and 34, when
MOS memory is present with battery backup, a battery status indication signal is generated by the
power supply. This signal should be attached to thc~ POWER UP REBOOT ENAB input (TPl) on the
M9301. If this status signal goes low, it indicates that the contents of the MOS memory are no longer
valid and rnlUst be reloaded, usually from some mass storage device. The M9301, sensing the status of
the memory, forces a boot on power-up, allowing new data to be written into memory. Note that
grounding TPI will override SI-2 if the switch is off.
If the battery status input is high (logic I), the M9301 will not automatically boot on power-up, and
execution will begin at the address specified by location 24.
1-5

1.5.2 Low ROM Enable
This dip switch (SI-l), when set to the OFF position, prevents the M9301 from responding to the
Unibus address range 765000 through 765777. See address maps for the specific versions to :see how
each version is affected by S I-I.
1.5.3 Boot Switch Selection
In order to select bootstraps to be run on power-ups and external boot enables, eight dip switches (S 1-3
through S 1-10) are provided on the M9301. Tables in Chapter 7 and following chapters show switch
configurations for the various options supplied by each version.
1.5.4 External Boot Switch
A device can be externally booted using the EXTERNAL BOOT input on Faston tab TP2. If this
input is brought to ground, BUS AC LO L will be activated causing the processor to perform a
POWER FAIL. Upon returning to a logic I, this input will deactivate BUS AC LO L init.iating a
power-up sequence in the CPU. Faston tab TP3 should be used as a ground return for the ,external
boot switch. Note that the power-down trap vectors to locations 248 and 268.

1-6

CHAPTER 2
HARDWARE DESCRIPTION

2.1 GENERAL
All versions of the M930I are physically and electrllcally identical with the exception of the ROMs that
are used; and the hardware description which follows applies to each of them. Various portions of the
circuitry will be analyzed separately for clarity. :M9301 circuit schematics (CS M930I-0-l) will be
referenced throughout the description.
2.2 DEFINITION OF TERMS
Bootstrap Program
A bootstrap program is any program which loads another (usually larger) program into computer
memory from a peripheral device.
Bootstrap
Bootstrap and bootstrap program are used interchangeably.
Boot
Boot is a verb which means to initiate execution of a bootstrap program.
NOTE
Some processors have a f.~ature which enables them
to select power fail vectOl·s. A vector of 248 will be
used in this discussion for the sake of simplicity.

2.3 POWER-UP SEQUENCE
Typically all PDP-II computers perform a power-up sequence each time power is applied to their CPU
module(s). This sequence is as follows:
1.
2.

3.
4.
5.

6.
7.

+5 Vdc comes true
BUS DC LO L un asserted by power supply
BUS INIT asserted
BUS AC LO L released by power supply
Processor accesses memory location 248 for new PC
Processor accesses memory location 268 for new PSW
Processor begins running program at new PC contents.

With an M930I Bootstrap/Terminator in the PDP-II computer system, on power-ups the user can
optionally force the processor to read its new PC from a ROM memory location (Unibus location
773024 8) and offset switch bank on the M9301 on power-up. Switch SI-2 on the M930I can enable or
disable this feature. A new PSW will also be read from a location (Unibus location 773026 8) in the
M930I menlory. This new PC and PSW will then direct the processor to a program (typically a bootstrap) in the M930I ROM (Unibus memory locations 773000 through 773776).

2-1

If switch S 1-2 is turned off, disabling power-up boots, an external switch or logic level can be: used to
force the processor to execute a boot program.
2~4 POWER-UP BOOTING LOGIC
The status of the PDP-ll power supply is described by the two Unibus control lines BUS AC LO L
and BUS DC LO L. The condition of these two lines in relation to the +5 V output of the power
supply is defined by Unibus specifications as summarized in Figure 2-1.

POWER DOWN
ACPOWER
AClO

POWER UP

~L________________~

~~
I
I
I
•

DClO

______________________

DC POWER

~r--

~I~_

~---_/:

I I
1>01

1>0'

1>5MS I

1
/
CPU TRAPS

1>0'

"
CPU TRAPS
11-4878

Figure 2-1

Power Fail Sequence

2.4.1 Power-Up and Power Down
On the M9301, power-up sequences are detected by the circuitry shown in Figure 2-2. When +5 V first
becomes true, both BUS AC LO and BUS DC LO are asserted low. Assuming the PO\VER UP
REBOOT ENABLE switch (SI-2) is closed on, flip-flop E29 will then be set. When BUS L~C LO L
goes high followed by BUS AC LO L, this flip-flop is then cleared, generating a low-to-high tlransition
on the output of E20 (pin 13). This transition triggers the one-shot E21 which asserts Unibus address
lines BUS A09 L, BUS AIO L, and BUS AI2 L through BUS AI7 L for up to 300 ms.
2.4.2 Processor Reads New Program Counter
During the 300 ms time-out of E21, the central processor will be performing its power-up sequence.
When the processor attempts to read a new program counter (PC) address from memory localtion 248,
the address bits enabled by the one-shot are logically ORed to generate the address 773024 8. This
location happens to be an address in the M9301 ROM space which contains the starting address of a
specific boot routine.
2.4.3 Processor Reads New Status Word
Having obtained a new PC from location 7730248, the processor then attempts to read a new processor
status word (PSW) from memory location 268. The address bits enabled by one-shot E21 are logically
ORed to generate the address 7730268 which is also in the M9301 ROM address space. Once this
transfer is completed, the removal of MSYN from the bus will generate an ADDR CLR L signal
which clears the one-shot (E21) time-out, removing address bits BUS A09, BUS AIO, and HUS AI2
through BUS A17. The 300 ms time-out length of E21 was chosen to guarantee enough timc~ for any
PDP-II processor to complete the two memory transfers described before releasing the address lines.

2-2

R17
30K

EXT BOOT ENAB L - - - - - . . ,

+6V-A,J\,f'v-,,----,

CLEAR ADDR L

11-4879

Figure 2-2

Powc::r-Up Boot Logic

2.4.4 Power-Up Reboot Enable Switch
The POWER UP REBOOT ENABLE switch (Sl··2) can be used to disable the logic shown in Figure
2-2. With this switch open, the clear input to flip-flop E29 will always be low, preventing it from ever
being set on power restarts. Faston tab TPI is provided to allow switch S 1-2 to be remotely controlled.
Note that when an external switch is used, Sl-2 nlust be left in the OFF position.
2.5 EXTERNAL BOOT CIRCUIT
The processor can be externally activated by grounding the Faston tab TP2 input, as shown in Figure
2-3. This low input sets flip-flop E13 which then generates a BUS AC LO L signal on the Unibus.
Upon seeing this signal the PDP-ll processor will begin a power-down routine, anticipating a real
power failure. After completing this routine, the processor will wait for the release of BUS AC LO L,
at which tirne it will perform a power-up sequenc~~ through locations 248 and 268.
When the EXTERNAL BOOT input switch is released, the one-shot E2l is triggered, causing an 8 ms
time-out, and the set input to flip-flop E13 is removed (Figure 2-4). At the end of the one-shot timeout, flip-flop E13 is clocked low, releasing the BUS AC LO L line and firing the 300 ms one-shot (E2l).
The processor then is forced to read its new ]PC and PSW from location 773024 and 773026
respectively.
2.6 POW]~R-UP TRANSFER DETECTION LOGIC
After BUS AC LO L and BUS DC LO L have performed their power-up sequence, the logic shown in
Figure 2-5 ,~ounts the first two DATI transfers on the Unibus and generates a 75 ns pulse on the CLR
ADDR L line. The two Unibus transfers performed will be to obtain a new PC and PSW as previously
described. The CLR ADDR L pulse resulting will be used to clear the one-shot E2l shown in Figure 22, releasing bus address line BUS A09, BUS AlO, and BUS A12 through BUS A17.

2-.]

+6V

rEXTE RNAt1
BOOT

I SWITCH I TP2
I
I

E13
EXT BOOT ENAB L

I
L __ .J

PWRUPCLRL--~----------------~

Figure 2-3

11-4885

External Boot Circuit

TP2 SWITCH CLOSURE

BUS AC LO L

E21 ONE SHOT TIMEOUT

8ms

~__________~~_________~----____, ,______~l
PROCESSOR PERFORMS
POWER DOWN

40n8

PROCESSOR PERFORMS
POWER UP

"t "

11-4876

Figure 2-4

External Boot Timing

+6V

+6V
AOOR ENAB (1) H

R24

ENAB DATA (1) H

C:LR

8
4

~~DDR L

R23
47U
C3e
270pf

114883

Figure 2-5 Transfer Detection Logic
2-4

2.7 POWER-UP CLEAR
The circuit shown in Figure 2-6 is included on the, M9301 to guarantee that specific storage elements
on the module are cleared when power is first applied. The PWR CLR L signal will be held low for
approximately 70 ms after the +5 V has returned, assuming that the +5 V supply has a rise time of less
than 20 ms . The exact period of time for holding PWR C LR L is a function of the rise time of the + 5 V
power supply.

BUS INIT L - - - - - - .

R11
4.7K
PWR UPCLR L

03
0884

Figure 2-6

2.8

11-4884

Powc::r-Up Clear Logic

ADDRESS DETECTION LOGIC

2.8.1 M9.301 Address Space
Figure 2-7 shows the complete Unibus address dletection logic on the M9301. The purpose of this
circuitry is to detect Unibus addresses within the address space of the M9301: 7730008 - 773777 8 and
7650008 - 765777 8, and to recognize the specific addresses 7730248 and 7730268 for the power-up circuit
previously described.
2.8.2 M9.301 Memory Access Constraints
The circuitry shown in Figure 2-7 determines when the M9301 ROM address space is being accessed.
Upon receiving a recognized Unibus address, and BUS MSYN, the ROM data outputs are enabled
onto the Unibus data lines (BUS DOO L - BUS ])15 L), and BUS SSYN L is enabled 200 ns later.
Conditions which must be met before enabling the ROM data and returning BUS SSYN are as
follows:
1.

Detection of the Unibus address 765XXX (dependent on position of the L ROM ENABLE
switch SI-I) or 773XXX.

Transfer being performed is a DATI operation where BUS CI L is not asserted.

A BUS MSYN L control signal has bee:n obtained.

2.8.3 Low ROM Enable Switch
The LOW ROM ENABLE switch (SI-l) shown in Figure 2-7 allows the user to disable the M9301
detection of Unibus addresses 765000 through 765777. Disabling the detection of these addresses (S I-I
is set to OFF position) becomes essential when that memory space is being used by other peripheral
devices in the system. For M9301 modules containing standard DEC programs, users should note
what program features will be eliminated by disabling M9301 address locations 765000 through
765777.

2··5

BUS A17 L ---'iiPClI

BUSA16L--~~~~

BUS A16 L ----riO
BUS A14 L --':oH:']I
BUSA13 L --:;.("1"-BUS MSYN L -~~

+6V
BUS C1 L

+6V
R13
4.7K

ENAB DATA H
~-----------ENABDATAL

BUS A12 L
R9
1K

o-;;........,cr-.....o-......,.-766XXX L

I8USA11L

BUSA10 L

I8US A09 L
DCLOH

....----1------- A08 H
BUS A08 L

A07 H
~------

BUS A04 L

A06 H
A06 H

1-------+-I-i--i-----A04H
BUSA06 L

A03 H
....----- A02 H

BUS A03 L

..-+-H-+-+----4---+---- A01 H
BUS A01 L
ENAB JUMP L
BUS A02 L

BUS A07 L

766XXX L

11-4881

Figure 2-7

Address Decoder Logic

2-6

2.8.4 ROM Address Generation
Logic shown in the lower half of Figure 2-7 performs two functions. First it receives the nine address
inputs for the M9301 ROM memory (765XXXL and AOIH through A08H). Second it detects the
Unibus address 773024 and generates the offset switch enable signal ENAB JUMP L.

2.9 ADDRESS OFFSET SWITCH BANK
As previoUlsly mentioned, on power-up, the M9301 processor obtains its new PC from location
7730248 instead of location 248. When the M9301 address detection logic decodes address 248, it
enables (via ENAB JUMP L) the address offset switch bank (Figure 2-8). The contents of these switches, combinl~d with the contents of the specified address in M9301 ROM memory, produce a new PC
for the CPU. This new PC will point the processor to the starting address of a specific program
(usually a bootstrap routine) in the M9301 memo:ry. Several programs can be included in the M9301
memory with anyone being user selectable through the address offset switch selection.
Example:
M9301 ROM address 773024 contains
Offset switch bank contains
New PC read by CPU

173000
254
173254

NOTE
A switch in the ON position = O.
A switch in the OFF position = 1.
See Figure 1-3 for the relationship of the address offset switches to the bus address bits.

2.10 ROl\f MEMORY
The heart of the M9301 is the 512-word ROM shown in Figure 2-9. It is composed of four 512- X 4-bit
tristate ROMs organized in a 512- X 16-bit configuration. All four units share the same address lines
and produce 16-bit PDP-II instructions for execUltion by the processor.
All four sets of ROM outputs are always enabled, so that any change in address inputs will result in a
change in the Unibus data lines when the ENAB DATA signals in Figure 2-7 are enabled. For further
information on M9301 compatible ROMs, consullt Chapter 6.
M9301 users that program their own PROMs should note the following programming constraints.
I.

There is no address or data output translation required.

Unibus address locations 7730008 through 773776 8 are located in the lower 256 words of the
PROM. These addresses constitute the upper portion of the PROM, as far as the rest of the
system is concerned, however. Unibus slddress locations 7650008 through 7657768 are resident in the upper 256 words. These addresses consitute the lower PROM addresses with
rdation to the system, however, and are enabled and disabled by SI-I, the LOW ROM
ENABLE switch.

When coding PROM patterns, data bits DOl through 008 must always contain the inverse
of the data required, to compensate for the extra inversion logic included in the M9301
offset switch circuitry.

PROM location 773024 bits DOl through 008 must be logical Is for the offset switches to
work correctly.

2-7

ROM 016 H

BUS016'L

ROM 014 H
BUS 014 L

ROM 013 H

BUS 013 L

ROM 012 H
BUS 012 L
ROM 011 H
BUS 011 L
ROM 010 H
BUS 010 L

ROM 009 H
BUS 009 L
ENAB DATA H
ROM OOB·L

10
BUS OOB L

S1-3

S1-4

ROM 007 L
BUS 007 L

ROM 008 L

10K

BUS 008 L
16

S1-6

10K

ROM 006 L

BUS 0015 L
15

ROM 004 L

S1-8

10K

BUS 004 L
14

ROM 003 L

S1-7

7
10K

BUS 003 L
13
ROM 002L

S1-8

12 S1-9

10
BUS 002L

BUS DOlL
ENAB DATA L

ENAB DATA H
ROM 000 H

2
3

~
L
6
E8
BUS 000

ROM 001 L
11 S1·10

ENAB JUMP L

10
10K

Figure 2-8

Address Offset Switch Bank

2-8

11,4880

13--rQ MEl
E12
14

766XXX L

A08H
A07 H
A06 H
A06 H
A04H

1
I

I
TRI- 04 ~ ROM 016 H
G STATE 03 ~ ROM 014 H

2
3
4

02 ~ ROM 013 H

r..!!.. RClM012H

0
C

A03 H
A02 H
A01 H

B A

17 16\6

~ I

ME1

E11

r-i--

~
I

H TRI- 04 ~ ROM 011 H
G STATE 03
ROM 010H

2
3
4

t-12t-!!- ROM 009 H

01 ~ ROM 008 L

0
C

B A

6
1 \6

f-<) MEl

f-~

f--

..!....

ROM 007 L
H TRI- 04
G STATE 03 ..1!L ROM 006 L

2
3
4

F
B
E

02 ..!L ROM 006 L
01 ~ ROM 004 L

0
C B

J 7 J6\6
13

r<:J MEl
14

'-r--

04 ...!... ROM 003 L
TRI---- 1 G STATE
03 ...!Q...

3
4

01 ~ ROM OOOH

0
C

I
I

ROM 002 L
02 ~ ROM 001 L

B A

6
17 1

I
I

.J
11-4882

Figure 2-9

M9301 ROM Memory

2-9

2.11 M9301 TERMINATOR
The terminator section of the M9301 consists of four resistor pack circuits, each containing the
required pull-up and pull-down resistors for proper Unibus termination. Since PDP-I 1/04 amd PDP11/34 computers incorporate BUS GRANT pull-up resistors on the processor modules, 8pace has
been left on the M9301 for five jumpers (WI through W5) which allow the user to decide whether or
not to include BUS GRANT pull-up resistors. The M9301 BUS GRANT jumpers must be installed on
all modules which are used to replace an M930.
Caution should be taken when inserting M9301 modules in various PDP-II computers. If the processor in question does not have BUS GRANT pull-ups on the CPU, jumpers WI through V1l5 on the
M9301 should be inserted or the M9301 should be positioned at the end of the Unibus furthest from
the CPU.
A good rule of thumb is that the jumpers should be installed when the M9301 is used in place of an
M930 or equivalent.

2-10

CHAPTER 3
THE CONSOLE EMULATOR

3.1 GENERAL
The console emulator routine is a standard part of the firmware for the M930 1- Y A, -VB, -YE, -YF,
and -Y J options. A simplified operator's flowchart is presented in Figure 3-1 to give the reader a
unified picture of the routine.
3.2 SYMBOLS
A list of the symbols used follows.
Rectangle: indicates an automatic operation performed by the machine.
Diamond: indicates a decision, an automatic operation which can take either of two paths
depending on how the question stated within the diamond is answered.
Trapezoid: indicates operator action, the moving of a switch or the typing of keys.

3.3 USING THE CONSOLE EMULATOR
With switches S I-I through S 1-10 set in the ON position the system will execute a normal console
emulator power-up routine when power is supplied or the boot switch is pressed. Diagnostic tests 1-5
will run first. An error will cause the processor to loop. Completion of these diagnostic tests will be
followed by the register display routine. RO, R4, R6, and R5 will be printed out on the terminal. A $
sign will be printed at the beginning of the next line on the terminal, indicating that the console
emulator routine is waiting for input from the opl~rator. In the discussion that follows, the following
symbols will be used.
(SB): Space bar
(CR): Carriage return key
X: Any octal number 0-7
The four console functions can be exercised by pressing keys, as follows:

Function

Keyboard Strokes

Load Address
Examine
Deposit
Start

L(SB) X X X X X X (CR)
E(SB)
D (SB) X X X X X X (CR)
S(CR)

3-1

1. THE ROUTINE IS ENTERED ON POWER UP OR WHEN THE BOOT SWITCH
IS DEPRESSED (IN STANDARD M9301 CONFIGURATIONS! OR UPON THE _
RETURN OF AC POWER (AFTER AN INTERRUPTION OF AC POWER!

2. A DIAGNOSTIC LOCATED ON THE M9301 TESTS BASIC CPU OPERATION - -

3. IF THE DIAGNOSTIC IS PASSED, THE SYSTEM TERMINAL WILL PRINT
OUT FOUR, SIX DIGIT NUMBERS

4. THE SYSTEM IS NOW WAITING FOR THE OPERATOR TO ENTER
INFORMATION FROM THE KEYBOARD

5. THE OPERATOR ENTERS A CODE (DESCRIBED IN THIS SECTION!
WHICH WILL LOAD AN ADDRESS OR EXAMINE (A PREVIOUSLY LOADED
ADDRESS! OR DEPOSIT (INTO A PREVIOUSLY LOADED ADDRESS), OR
START (AT A PREVIOUSLY LOADED ADDRESS! OR BOOT A SELECTED
PERIPHERAL

6. THE FIRST TWO INPUT CHARACTERS ARE VERIFIED AS BEING A
KNOWN COMBINATION

7. IF THE KEY COMBINATION INDICATED A START, THE START WILL BE
IMPLEMENTED NOW, AT THE PREVIOUSLY LOADED ADDRESS. NOTE THAT
START WILL EXIT FROM THIS ROUTINE; TO ENTER AGAIN, THE OPERATOR
MUST BOOT

START
PROGRAM

8. IF THE KEY COMBINATION WAS AN EXAMINE, THE PREVIOUSLY LOADED _ _
ADDRESS, WITH ITS CONTENTS WILL BE PRINTED ON THE SYSTEM
TERMINAL

EXIT FROM
CONSOLE
EMULATOR

PRINT
ADDRESS AND
CONTENTS

INCREMENT
ADDRESS

9. IF THE CODE WAS NOT AN EXAMINE OR START, THE CONSOLE
EMULATOR JUMPS TO LOAD OR DEPOSIT OR BOOT

GO TO:
LOAD OR DEPOSIT OR BOOT

11·3283A

Figure 3-1 Console Emulator Routine
Flowchart (Sheet 1 of 2)
3-3

LOAD
SEQUENCE
10. SEQUENCE IS
ENTERED

DEPOSIT
SEQUENCE
SEQUENCE IS
ENTERED

BOOT
SEQUENCE
SEQUENCE IS
ENTERED

~--s

DATA TO BE DEPOSITED
IS ENTERED, MOST
SIGNIFICANT DIGIT
FIRST

DATA TO BE
DEPOSITED

ADDRESS TO BE

11. ADDRESS IS ENTERED
MOST SIGNIFICANT
DIGIT IS FIRST

UNIT SELECT
NO.

UNIT NUMBER IS
ENTERED,DEFAULT
NUMBER IS ZERO

12. A CHECK IS MADE TO INSURE THAT THE NUMBER WHICH WAS ENTERED
WAS AN OCTAL NUMBER 0-7; IF IT ISN'T, A $ IS PRINTED SIGNIFYING AN ERROR.

13. ENTERING (CR)
SIGNIFIES THE END
OF THE LOAD
SEQUENCE

TEST TO SEE IF THE
COMBINATION INPUT,
IMMEDIATELY PRE·
CEDING THIS ONE
WAS A DEPOSIT

ENTERING ICR)
SIGNIFIES THAT THE
OPERATOR WISHES TO
BOOT NOW

14. ADDRESS IS LOADED
INTO AN INTERNAL
REGISTER AND $ IS
PRINTED SIGNIFYING
SYSTEM IS READY
FOR NEXT KEYBOARD
INPUT

IF PREVIOUS OPERAnON WAS A DEPOSIT.
ADDRESS WILL
INCREMENT

PRIOR TO BOOTING, A
MEMORY DIAGNOSTIC
IS RUN; IF IT FAILS,
RUN LIGHT REMAINS
ON AND PERIPHERAL
IS NOT BOOTED

15.

(CR) INDICATES THAT
THE OPERATOR WISHES
TO DEPOSIT - NOW

IF MEMORY DIAGNOSTIC
PASSED, THE DEVICE IS
NOW BOOTED

16.

DATA IS DEPOSITED
FOLLOWED BY A $
PRINTOUT,SIGNIFYING
THE SYSTEM IS READY
FOR THE NEXT KEY.
BOARD INPUT

MACHINE EXITS FROM
THE CONSOLE
EMULATOR; TO RE·
ENTER THE OPERATOR
MUST DEPRESS THE
BooT/lNIT SWITCH

ADDRESS
IS
LOADED

HALT
ON
ERROR

INCREMENT
ADDRESS

YES

"CR = CARRIAGE RETURN KEY

11·32838

Figure 3-1 Console Emulator Routine
Flowchart (Sheet 2 of 2)

3-5

The first digit typed will be the most significant digit. The last digit typed will be the least significant. If
an address or data word contains leading zeros, thc~se zeros can be omitted when loading the address or
depositing the data. An example using the load, examine, deposit, and start functions follows. Assume
that a user wishes to:
1.
2.
3.
4.
5.
6.

Turn on power
Load address 700
Examine location 700
Deposit 777 into location 700
Examine location 700
Start at location 700.

To accomplish this, the following procedure must be followed.
Terminal Dblplay

Operator Input

1.
2.
3.
4.
5.
6.

TURNS ON POWER
L(SB) 700 (CR)
E(SB)
D(SB) 777(CR)
E(SB)
S(CR)

xxxxxx XXXXXX XXXXXX xxx XXX
$L700
$E 000700 XXXXXX
$0777
$E 000700 (XJ0777
$S

NOTE
The console emulator routine will not work with odd
addresses. Even numbered addresses must always be
used.
3.3.1

Successive Operations

3.3.1.1 Examine - Successive examine operations are permitted. The address is loaded for the first
examine only. Successive examine operations cause the address to increment and will display consecutive addresses along with their contents.
For example, to examine addresses 500-506:
Operator Input

Terminal Display

L(SB) 500 (CR)
E(SB)
E(SB)
E(SB)
E(SB)

L500
$E 000500 XXXXXX
$E 000502 XXXXXX
$E 000504 XXXXXX
$E 000506 XXXXXX

3.3.1.2 Deposit - Successive deposit operations are permitted. The procedure is identical to that used
with examine.
For example, to deposit 60 into location 500, 2 into location 502, and 4 into location 504:
Operator Input

Terminal Display

L(SB) 500 (CR)
O(SB) 60 (CR)
O(SB) 2 (CR)
O(SB)4 (CR)

$L500
$060
$02
$04

3··7

3.3.1.3 Alternate Deposit-Examine Operations
This mode of operation will not increment the address. The address will contain the last data which
was deposited.
For example, to load address 500 and deposit 1000, 2000, and 5420 with examine operations after
every deposit:
Operator Input

Terminal Display

L(SB) 500 (CR)
I)(SB) 1000 (CR)
E(SB)
D(SB) 2000 (CR)
E(SB)
D(SB) 5420 (CR)
E(SB)

$L500
$01000
SE 000500 001000
$02000
$E 000500 002000
$05420
$E 000500 005420

3.3.1.4 Alternate Examine-Deposit Operations
If an examine is the first instruction after a load sequence, and is alternately followed by deposits and
examines, the address will not be incremented, and the address will contain the last data which was
deposited. The above example applies to this operation, and with the exception of the order of examine
and deposit, the end result is the same.
3.3.2 Limits of Operation
The M9301 console emulator routine can directly manipulate the lower 28K of memory and the 4K
I/O page. See Chapter 5 for an explanation of techniques required to access addresses above the lower
28K.
3.4 BOOTING FROM THE KEYBOARD
Once the $ symbol has been displayed in response to system power-up, or pressing of the boot switch,
the system is ready to load a bootstrap from the device which the operator selects. The procedure is as
follows.
1.

Find the 2-character boot command code in the appropriate chapter that corresponds to the
peripheral to be booted.

Load paper tape, magtape, disk, etc. into the peripheral to be booted if required.

Verify that the peripheral indicators signify that the peripheral is ready (if applica.ble).

Type the 2-character code 0 btained from the table.

If there is more than one unit of a given peripheral, type the unit number to be bootled (0-7).
If no number is typed, the default number will be O.

Type (CR); this initiates the boot.

3-8

Before booting, always remember:
1.

The medium (paper tape, disk, magtape, cassette, etc.) must be placed in the peripheral to be
booted prior to booting.

The machine will not be under the control of the console emulator routine after booting.

The program which is booted in must:
a. Be self starting or
b. Allow the user to load another program by using the CONT function or
c:. Be startable from the console emulator after having been booted in.

Actuating the boot switch will always abort the program being run. The contents of the
general registers (RO-R 7) will be destroyed. There is no way to continue with the program
which was aborted. Some programs arc~ designed to be restartable.

3.4.1 Booting the High-Speed Reader Using the Console Emulator
To load the CPU diagnostic for an 11/34 computer system with a high-speed reader, perform the
following procedure.
1.

Place the HALT /CONT switch in the CO NT position.

Obtain a $ by either turning on system power or actuating the boot. (RO, R4, SP, and old PC
will be printed prior to the $.)

Place the absolute loader paper tape (coded leader section) in the high-speed reader.

Type: PR (CR)
The absolute loader tape will be loaded, and the machine will halt.

Remove the absolute loader and place the leader of the program, in this case a CPU diagnostic, in the reader.

~v1ove the HALT /CONT switch to HALT and then return it to CONT. The diagnostic will
be loaded and the machine will halt (normal for this program; non-diagnostic programs may
or may not be self-starting).

If program is not self-starting, activate the BOOT /INIT switch. This will restart the console
emulator routine.

Using the console emulator, deposit de:sired functions into the software switch register (a
nlemory address) location. (See the diagnostic for the software switch register's actuallocation and significance.)

lJsing the console emulator, load the starting address, and start the program as described
earlier in this section.

3-9

3.4.2 Booting a Disk Using the Console Emulator
To boot the system's RKll disk, which contains the CPU diagnostic that you want to run, perform the
following procedure.
1.

Verify that the HALT jCONT switch is in the CONT position and the write lock switch on
the RK 11 peripheral is in the ON position.

Turn on system power or press the console boot switch. The system terminal displays RO,
R4, SP, and old PC which are octal numbers, followed by a $ on the next line.

Place the disk pack in drive O.

When the RK05 load light appears, the system is ready to be booted.

Type: DK (CR)
This causes the loading of the bootstrap routine into memory and the execution of that
routine.

The program should identify itself and initiate a dialogue (which will not be discussed here).

3.5 RECOVERING FROM ERRORS IN THE CONSOLE EMULATOR ROUTINE
Table 3-1 describes the effects of entering information incorrectly to the console emulator routine. The
following symbols are used in the table.
(9) - Represents a non-octal number (8 or 9)
(Y) - Represents:
1.

All keys (other than numerics) which are unknown

Keys which are known but do not constitute a valid code in the context which they are
entered.

Refer to previous sections for a discussion of the correct method operating the console ~:mulator
routine.
'Escape Route
If an entry has not been completed and the user realizes that an incorrect or unwanted character has
been entered, press the rub out or delete key. This action will void the entire entry and allow the user to
try again.

3-10

Table 3-1

Deposit Errors: Useful Examples

Error

Result

Remedy

Operator

Terminal

L was followed by a
key other than (SB)

Terminal display will
immediately return a $
to signify an unknown
code. No address is
loaded.

Try again

L(Y)

$L
$

An illegal (non octal)
number (8 or 9) is typed
after the correct load
entrance, within an
otherwise valid number.

Upon receipt of the
Try again
illegal number, the
Console Emulator will
ignore the entire address
and return a $.

L(SB)XXX9

$L XXX9
$

An incorrect alphabetic
key is typed after the
correct load entrance within
an otherwise valid number.

Same as illegal number.

Try again

L(SB)XXXY

$L XXXV
$

The most significant octal
number in a six bit address
is greater than one.

An address will be
loaded. However, the
state of the most
significant address bit
will be determined
by bit 15 only:

Try again
if required

S(SB) 6XXXXX

$S OXXXXX
$

2=0
3=1
4=0
5= I
6=0
7=I
An unwanted but legal
octal number is loaded.

Address will be loaded
but unchanged.

An extra (seventh) octal
number is typed.

The loaded number will Try again
be incorrect. The system
will accept any size
word but will only
remember the last six
characters typed in.

L(SB) I XXXXXX

$LIXXXXXX
$
Actually
Load
XXXXXX

A memory location higher
than the highest memory
location available in the
machine is loaded.

No errors will result
unless a deposit,
examine, or start is
attempted.

L(SB) I XXXXX
(CR)

LIXXXXX

3-11

Try again

Table 3-1

Deposit Errors: Useful Examples (Cont)
Remedy

Operator

Terminal

Machine will wait
Load address and number
were.entered correctly, (CR) indefinitely for (CR).
$ will not be returned.
was not entered.

Type (CR)

L(SB)XXXXX
(CR)

$L XXXX x
$XXXXX( CR)

E or S is followed by a key
other than space.

Terminal display will
immediately return a $
to signify an unknown
code.

Try again

E(Y) or S(X)

$E
$
$S
$

Examine or start is
attempted to a memory
location which is higher
than the highest available
memory location in the
machine (I/O page can be
examined) or to an odd
memory location.

The system will hang
up when (SB) is
executed.

Depress the
boot switch

E(SB) or S(SB)

$E or $S

Examine is performed
without loading an address
prior to first examine.

An examine operation
of an unknown address
will be performed. It
is possible that the
machine may attempt
to examine an address
which does not exist.
The system may
hangup in a program
loop.

Try again
or boot if
system hangs
up.

Start is performed without
loading an address prior
to starting.

Start at an unknown
location will occur.

Reload
program and
try again.

D was followed by a key
other than space.

Terminal display will
immediately return a $
to signify an unknown
code.

Try again

$D
$

Deposit is attempted to a
memory location which is
higher than the highest
available memory location
in the machine (with the
exception of the I/O page).

The system will hang
up when (SB) is
executed.

Activate the
boot switch
to reboot the
system.

Error

Result

3-12

Table 3-1

Deposit Error~i: Useful Examples (Coot)

Error

Result

Remedy

Deposit is performed
without loading an address
or knowing what
address has been previously
loaded.

a. Data will be written
over and lost.

a. Immediately
following the
error, perform
an examine to
determine the
location which
was accessed.
Restore original
contents if known

b. Machine might hang
up in a program
loop.

b. Reboot machine.

The system will hang
up when (CR) is
executed.

Depress the boot
switch.

Deposit into an odd address
is attempted.

3-13

Operator

Terminal

CHAPTER 4
BOOTSTRAP]~ING - M9301-YA, -VB, -YE, -YF, -YJ

The routines to bootstrap a device typically read in the first sector, block, or 512 words from the device
into location 0 through 512 of memory. The exception to this rule is the paper tape boot. The paper
tape boot is unique in that it can do no error checking and the secondary bootstrap (the absolute
loader, for example) is read into the upper part of memory. The actual locations loaded by the paper
tape boot are partially determined by the secondary bootstrap itself and by the size routine which
determines the highest available memory address within the first 28K. The flexible disk (or floppy)
reads sector 1 on track 1 into consecutive locations starting at O. The magnetic tape boots read the
second block into consecutive locations starting a1t O. If no errors are detected in the device, the bootstraps normally transfer control to location 0 in order to execute the secondary bootstrap just loaded.
The only exception to this starting address conce:rns the paper tape boots. They transfer control to
location XXX374, where XXX is determined initially by the size routine to be at the top of memory.
This is wh~~re the absolute loader has just been loaded.
If a device c!rror is detected, a reset will be executed and the bootstrap will try again. The bootstrap will
be retried indefinitely until it succeeds without error unless the user (operator) intervenes. The advantage of retrying the boot is that if a particular devi(~e being booted is not on-line or not loaded, perhaps
because of a power failure, the boot will give the device a chance to power up (for disks this is
essential).

A magnetic tape transport, however, will not automatically reload itself after a power failure and
restart. This situation requires user intervention. The user must reload the magtape and bring it back
on-line, at which time the magtape bootstrap, whkh will have been continually attempting to boot the
tape, will succeed.
Note that the only way to bootstrap a device drive: (unit or transport) other than drive 0 is by entering
the console emulator to specify the drive number d~~sired. Otherwise the bootstraps will default to drive
O. This means that only drive 0 of a device can be! bootstrapped without operator intervention.

4-1

CHAPTER 5
EXTENDED ADDRESSING

5.1 GENERAL
This chapte~r applies to use of the M930 1-Y A, -VB, -YE, -YF, and -YJ in PDP-II systems which have
no console. When the memory of a PD P-II system is extended beyond 28K, the processor is able to
access uppe~r memory through the memory management system. However, the console emulator normally allows the user to access only the lower 28K of memory. This chapter provides an explanation of
the method by which the user can gain access to upper memory in order to read or modify the contents
of any location. The reader should be familiar with the concepts of memory management in the KD lIE processor.
5.2 VIRTUAL AND PHYSICAL ADDRESSES
Addresses generated in the processor are called virtual addresses, and will be 16 bits in length. Physical
addresses refer to actual locations in memory. Thc~y are asserted on the Unibus and may be up to 18
bits in length (for 128K memories).
5.3 ADDRESS MAPPING WITHOUT MEMORY MANAGEMENT
With memory management disabled (as is the casc~ following depression of the boot switch), a simple
hardware mapping scheme converts virtual addresses to physical addresses. Virtual addresses in the 0
to 28K range are mapped directly into physical addresses in the range from 0 to 28K. Virtual addresses
on the I/O page, in the range from 28K to 32K (160000= 177776), are mapped into physical addresses
in the rangc~ from 124K to 128K.
5.4 ADDRESS MAPPING WITH MEMORY l\1ANAGEMENT
With memory management enabled, a different mapping scheme is used. In this scheme, a relocation
constant is added to the virtual address to create a physical or "relocated" address.
Virtual address space consists of eight 4K banks where each bank can be relocated by the relocation
constant associated with that bank. The procedur1e specified in this sectiol1 allows the user to:
I.

Create a virtual address to type into the load address command.

Determine the relocation constant required to relocate the calculated virtual address into the
dc!sired physical address.

Enable or disable the memory managerrlent hardware.

5·,1

5.5 CREATION OF A VIRTUAL ADDRESS
The easiest way to create a virtual address is to divide the 18-bit physical address into two separate
fields - a virtual address and a physical bank number. The virtual address is represented by the lower
13 bits and the physical bank by the upper 5 bits. The lower 3 bits of the physical bank number (bits 13,
14, 15) represent the virtual bank number (Table 5-1). Thus if bits 13, 14, and 15 are all Os, thc~ virtual
bank selected is O. The user should calculate the relocation constant according to Table 5-2. He can
then deposit this constant in the relocation register associated with virtual bank 0 (Table 5-1).
Table 5-1

Unibus Address Assignments

Virtual Address

Virtual
Bank

Relocation Descriptor
Register
Register

160000-177776
140000-157776
120000-137776
100000-117776
060000-077776
040000-057776
020000-037776
000000-017776

7
6
5
4
3
2
1
0

172356
172354
172352
172350
172346
172344
172342
172340

Table 5-2

172316
172314
172312
172310
172306
172304
172302
172300

Relocation Constants

Physical
Relocation
Bank Number Constant

37
36
35
34
33
32
31
30
27
26
25
24
23
22
21
20

17
16
15
14
13
12
11
10
7
6
5
4
3
2
1
0

007600
007400
007200
007000
006600
006400
006200
006000
005600
005400
005200
005000
004600
004400
004200
004000

003600
003400
003200
003000
002600
002400
002200
002000
001600
001400
001200
001000
000600
000400
000200
000000

One relocation register exists for each of the eight virtual banks. In addition to the relocation registers,
each bank has its own descriptor register which provides information regarding the types of access
allowed (read only, read or write, or no access).

5-2

The memory management logic also provides various forms of protection against unauthorized access.
The corresponding descriptor register must be set up along with the relocation register to allow access
anywhere within the 4K bank.
For example, assume a user wishes to access lo(:ation 5337208 • The normal access capability of the
console is 0 to 28K. This address (533720) is betw1een the 28K limit and the I/O page (760000-777776),
and consequently must be accessed as a relocated virtual address, with memory management enabled.
The virtual address is 13720 in physical bank 25 and is derived as follows.
All locations in bank 25 may be accessed through the virtual addresses 000000-017776. The relocation
and descriptor registers in the processor are still accessible since their addresses are within the I/O
page. (Note that access to the I/O page is not automatically relocated with memory management,
while access to the I/O page is automatically relocated when memory management is not used.)
The relocation constant for physical bank 25 is 005200. This constant is added in the relocation unit to
the virtual address, as shown, yielding 533720.
013720
520000

Virtual address
Relocated constant (Table 5-2)

533720

Physical address

The Unibus addresses of the relocation registers and the descriptor registers are given in Table 5-1. The
relocation constant to be loaded into the relocation register for each 4K bank is provided in Table 5-2.
The data to be loaded in the descriptor register to provide read/write access to the fu1l4K is always
077406.
The Unibus address of the control register to enable memory mangement is 177572. This register is
loaded with the value 000001 to enable memory :management, and loaded with 0 to disable it.
To complete the example previously described (ac:cessing location 533720), the console routine would
be as follows:
$L
$D
$L
$D
$L
$D
$L
$D
$L
$D
$L
$E

172340
5200
172356
7600
172300
77406
172316
77406
177572
1

13720

/ Access relocation register for virtual bank 0
jDeposit code for physical bank 25.
/ Access relocation register for virtual bank 7.
/Deposit code for the I/O page.
/ Access des~;riptor register, virtual bank O.
/Deposit code for read/write access to 4K.
/ Access descriptor register, virtual bank 7.
/Deposit code for read/write access to 4K.
/ Access control register.
/Enable melmory management.
/Load virtual address of location desired.
/Examine the data in location 533720.
/Data will be displayed.

5.6 CONSTRAINTS
Loading a new relocation constant into the relo(;ation register for virtual bank 0 will cause virtual
addresses 000000-017776 to access the new physic:al bank. A second bank can be made accessible by
loading the: relocation constant and descriptor data into the relocation and descriptor registers for
virtual bank 1 and accessing the location through virtual address 020000-037776. Seven banks are
accessible in this manner, by loading the proper constants, setting up the descriptor data, and selecting
the proper virtual address. Bank 7 (I/O page) nlust remain relocated to physical bank 37 as it is
accessed by the CPU to execute the console emulator routine.
5-3

Memory management is disabled by clearing (loading with Os) the control register 177572. It should
always be disabled prior to typing a boot command.
The start command automatically disables memory management and the CPU begins executing at the
physical address corresponding to the address specified by the previous load address command. Pressing the boot switch automatically disables memory management. The contents of the relocation registers are not modified.
The HALT/CONT switch has no effect on memory management.

5-4

CHAPTER 6
M9301-0

6.1 GENERAL
The M9301-0 has been created as a universal bootstrap device which allows the user to program and
install customized 512- X 4-bit PROMs. This module version comes with four 16-pin IC (integrated
circuit) sockets in place of the ROMs normally inserted on other module versions. When configuring
PROM bit patterns for the M9301-0, care should be taken to arrange them to meet the address and
data output pinouts on the module (Paragraph 2.10).
The switches for this version are hardwired in the same way as the switches for the other versions
(Paragraphs 2.4, 2.8, and 2.9). However, the uSI;,r will have to determine how he wants to set the
switches, depending on the programs he blasts into the PROMs and the program starting locations he
selects.
6.2 PROM PROGRAMMMING PROCEDURE
The PROl'~ is manufactured with logic level Os in all storage locations. In -order to program a logic
level 1 at a specified bit, the ROM programmer must electrically alter a bit at logic level 0 to logic level
1. There are 2048 bits which are organized as 512 words of 4 bits each. Figure 6-1 shows a PROM pin
diagram. Figure 6-2 is a block diagram showing the logic internal to the PROM.
TOPVIEW

ADDRESS A6

VCC SUPPLY VOLTAGE

ADDRESS

A7 ADDRESS

ADDRESS

CE CHIP ENABLE

ADDRESS

OUTPUT

ADDRESS

OUTPUT

ADDRESS

OUTPUT

GND

OUTPUT

11-4877

Figure 6-1

PROM Pin Connection Diagram

6-1

(12)

04
(9)

OUTPUT BUFFER

- - -

MUX

- -

ROM MATRIX

- -

ADDRESS DECODER

11-4867

Figure 6-2

PROM Internal Logic

6-2

CHAPTER 7
M9301-YA

7.1 INTRODUCTION
The M9301-Y A is designed specifically for PDP-ll/04 and PDP-ll/34 OEM systems. The ROM
routines include basic CPU and memory GO-NO GO diagnostics, a console emulator program, and a
specific set of bootstrap programs.
The only physical difference between the M9301- YA and the M9301-0 module is that specially programmed tristate 512- X 4-bit ROMs are inserted in the 16-pin dip sockets of the M9301-0. Figure 7-1
is a program memory map of the M9301- Y A module, and it lists the nature of each diagnostic test in
the ROMs. A program listing for the ROMs may be found in the M9301 engineering drawings.

r----------.... 173777
HIGH ROM

CONSOLE

EMULATOR

RK11
RP11·
TC11
TM11
DL11
PC11

BOOTSTRAP
BOOTSTRAP
BOOTSTRAP
BOOTSTRAP
BOOTSTRAP
BOOTSTRAP

' - - - - - , - - - - -.... 173000

166777
DIAGNOSTICS

LOW ROM

TA11
RX1'

BOOTSTRAP
BOOTSTRAP

'--_ _ _ _ _ _ _ _ _--' 166000
11-4869

Figure 7-1

Program Memory Map for the M9301- Y A

7.2 BOOTSTRAP PROGRAMS
The commands which can be used to call the bootstrap programs from the console emulator are listed
in Table 7-1.

7-1

Table 7-1

Bootstrap Routine Codes for the M9301-YA

Device

Description

Command

RKII
RPII
TCll
TMII
TAll
RXII
DLll
PCll

Disk Cartridge
RP02/03 Disk Pack
DECtape
800 bpi Magtape
Magnetic Cassette
Diskette
ASR-33 Teletype
Paper Tape

DK
DP
DT
MT
CT
DX

IT
PR

An explanation of the functions performed by the various bootstrap programs follows.
RX 11 Diskette Bootstrap - Loads the first 64 words (2008 bytes) of data from track one, sector one
into memory locations 0-176 beginning at location O. If location 0 does not contain 240, the boot is
restarted. Restarts will occur 2000 times before the machine is halted automatically.
TAil Cassette Bootstrap - This bootstrap is identical to that of the RXII except that data is loaded
from the cassette beginning at the second block.
PC 11 Paper Tape Reader Bootstrap - Loads an absolute loader formatted tape into the upper rnemory
locations XXX746 to XXX777 (XXX is dependent on memory size). Once loading is completed, the
boot transfers operation to a routine beginning at location XXX752. In systems containing anM9301Y A which is set up not to run diagnostic test 1 through test 5, XXX will become 017, not the upper
part of memory.
Disk and DECtape Bootstraps (excluding RXll) - Load 10008 words (2000 8 bytes) of data from the
device into memory locations 0-17768 •
Magtape Bootstraps
TMll - Loads second record (2000 8 bytes maximum size) from the magtape into memory location 0-1776 8 •
7..3 MICROSWITCH SETTINGS
A set of ten microswitches is located on the M9301 module. They determine which ROM routines are
selected on power-up and give the user automatic access to any function. Switch SI-1 should be on for
normal operation in order to allow access to the low ROM addresses (765000-765777). The primary
activating processes for the M9301- Y A are the power-up sequence and the enabling of the console
boot switch. Switch S 1-2 must be in the ON position in order to enable activation of the M9301- Y A on
a power-up. If switch SI-2 is off, then the processor will trap to location 24 (as normal) to exe1cute the
user power-up routine. When switch SI-2 is ON, the other switches, SI-3 through SI-10, determine
what action the M9301- YA will take on power-up.

If the system includes a console boot switch, then any time that switch is pressed the M9301- Y A will be
activated. Note that some processors will have to be halted for this switch to have any effect. Enabling
the console boot switch causes the processor to enter a ROM routine by creating a fake powerdown/power-up sequence. The user should note that the position of switch SI-2 is irrelevant when the
console boot switch is used.

7-2

Pushing the console boot switch thus results in a normal power-up sequence in the processor. Prior to
the power-up sequence, the M9301-Y A asserts 773000 on the Unibus address lines. This causes the
new PC to be taken from ROM location 773024 instead of location 000024. The new PC will be the
logical OR of the contents of ROM location 773024 and the eight microswitches on the M9301-Y A
module. A switch in the ON position is read as a 0, while a switch in the OFF positiun is a 1. In this
way all the M9301-YA program options are accessible.
Each program option is given a different starting address. Note that microswitch SI-10 is ORed with
bit 1 of the data in ROM location 773024. SI-9 is ORed with bit 2, etc. No switch is provided for
combination with bit 0, because an odd address could result when going through the trap sequence.
Figure 7-2 shows the relationship of the switch(:s to the bus address bits.
LOW ROM ENABLE

,I •I

POWER UP REBOOT ENABLE

+
2

CORRESPONDING
BUS ADDRESS BITS
BINARY VALUE
OF SWITCHES

S1 SWITCHES

OCTAL VALUES
OF SWITCHES

Y
ON = 0
OFF = 1

Figure 7 -2

11-4865

Offset Switches and Corresponding Bus Address Bits

7.4 PROGRAM CONTROL THROUGH TH1[ MICROSWITCHES
The microswitches on the M930 1-Y A enable th(: user either to start a bootstrap operation or to enter
the console emulator, simply by pressing the boot switch. Note that a momentary power failure will
have the same effect as pushing the boot switch. The user should also note that he can select any
function with or without diagnostics. Adding 2 to the appropriate octal code in the switches will
disable the diagnostics.
Figure 7-3 shows a program flowchart for the M9301-Y A. Notice that the choice and sequence of
routines is entirely dependent on the offset swih:=h settings.
Table 7-2 shows the options with their corresponding switch settings and octal codes.

7.5 DIAGNOSTIC PROGRAMS
An explanation of the eight CPU and memory diiagnostic tests follows. Three types of tests are included in the M930 1- Y A diagnostics:
1.
2.
3.

Primary CPU tests (1-5)
Secondary CPU tests (6, 7)
Memory test (8)

7-3

NORMAL MODE

AUTOMATIC BOOT MODE

DISPLAY MODE

OFFSET
SWITCH
SETTING

I
000

I
I

002

030

I
I

CPU
DIAGNOSTIC
TESTS 1-6

440-R K11-442
466-RP11-470
606-TC11-610
624-TM11-626
624-TA11-626
636-RX11-640
660-DL 11-662
660-PC11-662

\
CPU
DIAGNOSTIC
TESTS 1-6

ro;ER /
CPU
DIAGNOSTIC
TESTS 1-6

USER
POWER UP
ROUTINE

Y
EXTENDED
CPU
DIAGNOSTIC
TESTS 6.7

EXTENDED
CPU
DIAGNOSTIC
TESTS 6.7

MEMORY
SIZING

MEMORY
DIAGNOSTIC
TESTS

L
BOOTTHE
DEVICE
SELECTEDoIN
KEYBOARD
DISPATCH

BOOTTHE
DEVICE
SELECTED IN
KEYBOARD
DISPATCH

BOOT THE
DEVISE
SELECTED
IN THE OFFSET
SWITCHES

BOOTTHg
DEVISE
SELECTE:D
IN THE OFFSET
SWITCHES
'11-4860

Figure 7-3

M9301-YA Program Flowchart
7-4

Table 7-2

Options and Corresponding Switch Settings
S3

S10

Octal
Code

000

OFF

002

OFF

030

CPU Diag. Boot RK 11
Boot RKll (without Diag.)

OFF
OFF

ON
ON

OFF
OFF

ON
ON

ON
OFF

440
442

CPU Diag. Boot RP11
Boot RPll (without Diag.)

OFF
OFF

ON
ON

OFF
OFF

ON
OFF

OFF
ON

466
470

CPU Diag. Boot TC11
Boot TCll (without Diag.)

OFF
OFF

ON
ON

OFF
OFF

ON
ON

ON
OFF

OFF
ON

506
510

CPU Diag. Boot TM 11
Boot TM 11 (without Diag.)

OFF
OFF

ON
ON

OFF
OFF

ON
ON

OFF
OFF

ON
ON

OFF
OFF

ON
OFF

524
526

CPU Diag. Boot TAll
Boot TAil (without Diag.)

OFF
OFF

ON
ON

OFF
OFF

ON
ON

OFF
OFF

ON
OFF

624
626

CPU Diag. Boot RX 11
Boot RXII (without Diag.)

OFF
OFF

ON
ON

ON
OFF

OFF
ON

636
640

CPI Diag . Boot DL11
Boot DLII (without Diag.)

OFF
OFF

ON
ON

OFF
OFF

ON
ON

OFF
OFF

ON
ON

ON
OFF

650
652

CPU Diag. Boot PC11
Boot PC II (without Diag.)

OFF
OFF

ON
ON

OFF
OFF

ON
ON

ON
OFF

660
662

Function
CPU Diagnostics with
Console Emulator
CPU Diag. Vector
through location 24
Console Emulator
without Diag.

Note: Ol'l = Logic 0, 0 FF = Logic 1

7.5.1 Primary CPU Tests
The primary CPU tests exercise all unary and double operand instructions with all source modes.
These tests do not modify memory. If a failure is detected, a branch-self (BR.) will be executed. The
run light will stay on, because the processor will hang in a loop, but there will be no register display.
The user must use the halt switch to exit froml the loop. If no failure is detected in tests 1-5, the
processor will emerge from the last test and ent,er the register display routine portion of the console
emulator program.
TEST 1 -- SINGLE OPERAND TEST
This test executes all single operand instructions using destination mode O. The basic objective is to
verify that all single operand instructions operat1e; it also provides a cursory check on the operation of
each instruction, while ensuring that the CPU dlecodes each instruction in the correct manner.

7-5

Test 1 tests the destination register in its three possible states: zero, negative, and positive. Each
instruction operates on the register contents in one of four ways:
1.

Data will be changed via a direct operation, i.e., increment, clear, decrement, etc.

Data will be changed via an indirect operation, i.e., arithmetic shifts, add carry, and subtract
carry.

Data will be unchanged but operated upon via a direct operation, i.e., clear a register
already containing zeros.

Data will be unchanged but examined via a non-modifying instruction (TEST).
NOTE
When operating upon data in an indirect manner, the
data is modified by the state of the appropriate condition code. Arithmetic shift will move the C bit into
or out of the destination. This operation, when performed correctly, implies that the C bit was set correctly by the previous instruction. There are no
checks on the data integrity prior to the end of the
test. However, a check is made on the end result of
the data manipulation. A correct result implies that
all instructions manipulated the data in the correct
way. If the data is incorrect, the program will hang in
a program loop until the machine is halted.

TEST 2 - DOUBLE OPERAND, ALL SOURCE MODES
This test verifies all double operand, general, and logical instructions, each in one of the seven addressing modes (excludes mode 0). Thus, two operations are checked: the correct decoding of each double
operand instruction, and the correct operation of each addressing mode for the source operand.
Each instruction in the test must operate correctly in order for the next instruction to operate. This
interdependence is carried through to the last instruction (bit test) where, only through the correct
execution of all previous instructions, a data field is examined for a specific bit configuration. Thus,
each instruction prior to the last serves to set up the pointer to the test data.
Two checks on instruction operation are made in test 2. One check, a branch on condition, is :made
following the compare instruction, while the second is made as the last instruction in the test sequcmce.
Since the GO-NO GO test resides in a ROM memory, all data manipulation (modification) must be
performed in destination mode 0 (register contains data). The data and addressing constants uSled by
test 2 are contained within the ROM.
It is important to note that two different types of operations must execute correctly in order for this
test to operate:

Those instructions that participate in computing the final address of the data mask for the
final bit test instruction.

Those instructions that manipulate the test data within the register to generate the expected
bit pattern.

Detection of an error within this test results in a program loop.
7-6

TEST 3 - JUMP TEST MODES 1, 2, AND 3
The purpose of this test is to ensure correct operation of the jump instruction. This test is constructed
so that only ajump to the expected instruction wilt provide the correct pointer for the next instruction.
There are two possible failure modes that can occur in this test:

The jump addressing circuitry will nlalfunction causing a transfer of execution to an
incorrect instruction sequence or non-e:xistent memory.

The jump addressing circuitry will malfunction in such a way as to cause the CPU to loop.

The latter case is a logical error indicator. The forlmer, however, may manifest itself as an after-the-fact
error. For example, if the jump causes control to be given to other routines within the M9301, the
interdependent instruction sequences would probably cause failure to eventually occur. In any case,
the failing of the jump instruction will eventually cause an out of sequence or illogical event to occur.
This in itsdf is a meaningful indicator of a malfunctioning CPU.
This test contains a jump mode 2 instruction, which is not compatible across the PDP-11 line. However, it will operate on any PDP-II within this test, due to the unique programming of the instruction
within test 3. Before illustrating the operation, it is. important to understand the differences of the jump
mode 2 between machines.
On the PDP-II/20, 11/05, 11/15, and 11/10 proc,essors, for the jump mode 2 [JMP(R)+], the register
(R) is incrc;:mented by 2 prior to execution ofthejump. On the PDP-ll/04, 11/34, 11/35, 11/40, 11/45,
11/50, 11/55, and 11/70, (R) is used as the jump address and incremented by 2 after execution of the
jump.
In order to deal with this incompatibility, JMP (R)+ is programmed with (R) pointing back on the
jump itself. On 11/20, 11/05, 11/10, and 11/15 processors, execution of the instruction would cause
(R) to be incremented to point to the following instruction, effectively continuing a normal execution
sequence.
On PDP-ll/04, 11/34, 11/35, 11/40, 11/45, 11/50, 11/55, and 11/70 processors, the use of the initial
value of (R) will cause the jump to loop back on itself. However, correct operation of the autoincrement will move (R) to point to the next instruction following the initial jump. The jump will then be
executed again. However, the destination address will be the next instruction in sequence.
TEST 4 - SINGLE OPERAND, NON-MODIFYING BYTE TEST
This test focuses on a unique single operand instruction, the TST. TST is a special case in the CPU
execution flow since it is a non-modifying operation. Test 4 also tests the byte operation of this instruction. The TSTB instruction will be executed in mode 1 (register deferred) and mode 2 (register
deferred, autoincrement).
The TSTB is programmed to operate on data which has a negative value most significant byte and a
zero (not negative) least significant byte.
In order for this test to operate properly, the TSTB on the low byte must first be able to access the even
addressed byte and then set the proper condition codes. The TSTB is then reexecuted with the
autoincrement facility. After the autoincrement, the addressing register should be pointing to the high
byte of th(! test data. Another TSTB is executed on what should be the high byte. The N bit of the
condition ,codes should be set by this operation.
Correct execution of the last TSTB implies that the autoincrement recognized that a byte operation
was requested, thereby only incrementing the address in the register by one, rather than two. If the
correct condition code has not been set by the associated TSTB instruction, the program will loop.
7-7

TEST 5 - DOUBLE·OPERAND, NON·MODIFYING TEST
Two non-modifying, double-operand instructions are used in this test - the compare (CMP) and bit
test (BIT). These two instructions operate on test data in source modes 1 and 4, and destination modes
2 and 4.
The BIT and CMP instructions will operate on data consisting of all ones (177777). Two separatle fields
of ones are used in order to utilize the compare instructions, and to provide a field large enough to
handle the autoincrementing of the addressing register.
Since the compare instruction is executed on two fields containing the same data, the expected result is
a true Z bit, indicating equality.
The BIT instruction will use a mask argument of all ones against another field of all ones. The expected
result is a non-zero condition (Z).
Most failures will result in a one instruction loop.
On successful completion of test 5, the register display routine is enabled, provided the console emulator has been selected in the microswitches. This routine prints out the octal contents of th,e CPU
registers RO, R4, SP, and old PC on the console terminal. This sequence will be followed by a prompt
character ($) on the next line.
An example of a typical printout follows.

XXXXXX

XXX XXX

XXXXXX

R6
(Stack
Pointer)

R5
(Old PC)

Prompt
Character
NOTES:
1.

Where X signifies an octal number (0-7).

\Vhenever there is a power-up routine or the boot switch is released on PDP-ll /04 and
PDP-I 1/34 machines, the PC at this time will be stored in R5. The contents of R5 are then
printed as the old PC shown in the example.

The prompting character string indicates that diagnostics have been run and the proc1essor is
operating.

7.5.2 Secondary CPU and Memory Tests
The secondary CPU tests modify memory and involve the use of the stack pointer. The JMP and JSR
instructions and all destination modes are tested. If a failure is detected, these tests, unlike the primary
tests, will execute a halt.
Secondary CPU and memory diagnostics are run immediately after test 5 when they have been evoked
by means other than the console emulator, provided that the correct microswitches have been set. If
the console emulator has been entered at the completion of test 5, the secondary CPU and memory
diagnostics will be run when the appropriate boot command is given.

7-8

Note that the user can execute the secondary CPt] and memory diagnostics without running a bootstrap program. A false boot command (an invalid device code followed by a carriage return) will cause
execution of tests 6, 7, and 8 before the attempt to lboot is made. If these tests are executed successfully,
the device will be called but not found. The processor will trap to location 4, which has been set up by
the M930I·,Y A. A new PC is obtained at location 4, causing control to return to the console emulator.
The readings for the four registers are now available, and the old PC is the highest location in memory.
A failure in one of the tests will, of course, cause a halt.
TEST 6 - DOUBLE OPERAND, MODIFYING .BYTE TEST
The objective of this test is to verify that the doublc::-operand, modifying instructions will operate in the
byte mode. Test 6 contains three subtests:
1.
2.
3.

Test source mode 2, destination mode 1, odd and even bytes
Test source mode 3, destination mode 2
Test source mode 0, destination mode 3, even byte.

The move byte (MOVB), bit clear byte (BICB), and bit set byte (BISB) are used within test 6 to verify
the operation of the modifying double-operand functions.
Since modifying instructions are under test, memory must be used as a destination for the test data.
Test 6 uses location 500 as a destination address. Later, in test 7 and the memory test, location 500 is
used as the first available storage for the stack.
Note that since test 6 is a byte test, location 500 implies that both 500 and 501 are used for the byte
tests (even and odd, respectively). Thus, in the word of data at 500, odd and even bytes are caused to be
all Os and then alII s alternately throughout the test. Each byte is modifed independently of the other.
TEST 7 - JSR TEST
The JSR is the first test in the GO-NO GO sequence that utilizes the stack. The jump subroutine
command (JSR) is executed in modes 1 and 6. After the JSR is executed, the subroutine which was
given control will examine the stack to ensure that the correct data was placed in the correct stack
location (5UO). The routine will also ensure that the line back register points to the correct address. Any
errors detected in this test will result in a halt.
TEST 8 - MEMORY TEST
Although this test is intended to test both core and MOS memories, the data patterns used are
designed to exercise the most taxing operation for MOS. Before the details of the test are described, it
would be appropriate to discuss the assumptions placed upon the failure modes of the MOS
technology.
This test is intended to check for two types of problems that may arise in the memory.
1.

Solid element or sense amp failures

Addressing malfunctions external to the:: chip.

The simplest failure to detect is a solid read or write problem. If a cell fails to hold the appropriate
data, it is (~xpected that the memory test will easily detect this problem. In addition, the program
attempts to saturate a chip in such a way as to cause marginal sense amp operation to manifest itself as
a loss or pick-up of unexpected data. The 4K- X I-chip used in the memory consists of a 64- X 64matrix of ~10S storage elements. Each 64-bit section is tied to a common sense amplifier. The objective of the program is to saturate the section with, at first all Os and one I-bit. This I-bit is then floated
through the chip. At the end, the data is complenlented, and the test repeated.

7-9

For external addressing failures, it is assumed that if two or more locations are selected at the same
time, and a write occurs, it is likely that both locations will assume the correct state. Thus, prior to
writing any test data, the background data is checked to ensure that there was no crosstalk between
any two locations. All failures will result in a program halt as do failures in tests 6 and 7.
NOTE
If the expected and received data are the same, it is
highly probable that an intermittent failure has been
detected (i.e., timing or margin problem). The reason
the expected and received data can be identical is
that the test program rereads the failing address
after the initial non-compare is detected. Thus, a
failure at CPU speed is detected, and indicated by
the reading of the failing address on a single reference (not at speed) operation.
7.6 TROUBLESHOOTING THROUGH REGISTER DISPLAY
When a halt occurs, the user should reboot the system by pressing the BOOT /INIT switch. The
registers RO, R4, R6, and R5 will be displayed on the terminal in that order.
RO
R4
R6
R5

Expected data
Received data
Failing address (SP)
Old PC

The diagnostic program in the M9301- Y A will cause the processor to jump to one of four addresses:
165316, 165346, 165370, or 165534. The user should consult the diagnostic program listing to find the
failing test and begin troubleshooting. Possible causes of the failure include bus errors, a bad M9301
module, and a bad CPU.

7-10

CHAPTER 8
M9301-YB

8.1 INTRODUCTION
The M9301-YB is designed specifically for PDP-ll/04 and PDP-ll/34 end user systems. The ROM
routines include basic CPU and memory GO-NO GO diagnostics, a console emulator program, and a
specific set of bootstrap programs. Figure 8-1 is a program memory map for the M9301-VB.
, . . - - - - - - - - - - - - 173777

CONSOLE EMULATOR
DIAGNOSTICS
173000

CONSOLE EMULATOR
DIAGNOSTICS

166777

BOOTSTRAP
' - -_ _ _P_R_OG_R....
;A_M_S. _ _ _-' 166000
11-4872

Figure 8-1

Program Memory Map for the M9301-YB

8.2 BOOTSTRAP PROGRAMS
The commands used to call the bootstrap programs from the console emulator are listed in Table 8-1.
An explanation of the functions performed by the various bootstrap programs follows.
RXII Diskette Bootstrap - Loads the first 64 words (200 8 bytes) of data from track one, sector one
into memory locations 0-176 beginning at location O. Once loaded the content of location 0 is checked.
If it contains 240, operation is transferred to the routine beginning in location O. If location 0 does not
contain 240, the boot is restarted. Restarts will occur 2000 times before the machine is halted
automatically.
TAll Cassette Bootstrap - This bootstrap is identkal to that of the RXII except that data is loaded
from the cassette beginning at the second block.

8-1

Table 8-1

Bootstrap Routine Codes for the M9301-YB

Device

Description

Command

RK11
RP11
TCll
TM11
TAll
RXll
DL11
PC 11
RJS03/04
RJP04
TJU16

Disk Cartridge
RP02/03 Disk Pack
DECtape
800 bpi Magtape
Magnetic Cassette
Diskette
ASR-33 Teletype
Paper Tape
Fixed Head Disk
Disk Pack
Magnetic Tape

DK
DP
DT
MT
CT
DX
TT
PR
DS
DB
MM

PCll Paper Tape Reader and DL11 Bootstraps - Load an absolute loader formatted tapc~ into the
upper memory locations XXX746 to XXX777 (XXX is dependent on memory size). Once loading is
completed, these boots transfer operation to a routine beginning at location XXX7S2.
Disk and DECtape Bootstraps (excluding RX11) - Load 1000s words (2000s bytes) of data from the
device into memory locations 0-1776.
Magtape Bootstraps
TM 11 - Loads second record (2000s bytes maximum size) from the magtape into memory location 0-1776 8 •
TJU16 - Load second record (2000s bytes maximum aize) from magtape into memory locations
0-1776. (Note that the first record contains the magtape directory.)
8.3 MICROSWITCH SETTINGS
A set of ten microswitches is located on the M9301 module. They determine which ROM routines are
selected and give the user automatic access to any function.
The primary activating processes for the M9301-YB are the power-up sequence and the enabling of the
console boot switch. Switch S 1-1 (low ROM enable) must be in the ON position in order to enable
activation of the M9301-YB console emulator or diagnostics. Switch Sl-2 (POWER UP REBOOT
ENABLE) must be on to activate the ROM on power-up. If switch S 1-2 is off, then the processor will
trap to location 24 (as normal) to execute the user power-up routine. When switch S 1-2 is on, the other
switches, Sl-3 through Sl-10, determine what action the M9301-YB will take on power-up.
If the system includes a console boot switch, then any time that switch is pressed the M9301-YB will be
activated. Note that some processors will have to be halted for this switch to have any effect. Enabling
the console boot switch causes the processor to enter a ROM routine by creating a fake powerdown/power-up sequence. The user should note that the position of switch S 1-2 is irrelevant when the
console boot switch is used.
Pushing the console boot switch thus results in a normal boot on power-up sequence in the processor.
Prior to the power-up sequence, the M9301-YB asserts 773000 on the Unibus address lines. This causes
the new PC to be taken from ROM location 773024 instead of location 000024. The new PC will be the
logical OR of the contents of ROM location 773024 and the eight microswitches on the N[9301- YB
module. A switch in the ON position is read as a O. Likewise, a switch in the OFF position is a 1. In this
way all the M9301-YB options are accessible.
8-2

Each option is given a different address. Note that nlicroswitch S I-lOis ORed with bit I of the data in
ROM location 773024. SI-9 is ORed with bit 2, etc. No switch is provided for combination with bit 0,
because an odd address could result when going through the trap sequence. Figure 8-2 shows the
relationship of the switches to the bus address bits.
LOW ROM ENABLE

POWER UP REBOOT ENABLE

I •I •
2

CORRESPONDING
BUS ADDRESS BITS
BINARY VALUE
OF SWITCHES
OCT AL VALUES
OF SWITCHES

S1 SWITCHES

ON = 0
OFF = 1

Figure 8-2

11-4865

Offset Switches and Corresponding Bus Address Bits

The microswitches on the M9301-YB also enable the user to enter the console emulator, simply by
pressing the boot switch.
Figure 8-3 shows a program flowchart for the M9301-VB. Notice that the choi.ce and sequence of
routines is ell1tirely dependent on the offset switch settings.
,.
Table 8-2 shows the options and corresponding switch settings and octal codes. The user should note
that the M9301-YB does not provide for default booting from a peripheral.

Table 8-2
I 'unction

Options and Corresponding Switch Settings

SI-I

-2

-3

-4

-5

-6

-7

-8

-9

-10

Octal
Code

OFF

000

OFF

002

OFF

226

( on Power-up)

f ector through

[ _ocation 24H
( "la-NO

( :onsole

E:mulator
(

:la-NO GO

\ rector through

L,ocation 24H
( :onsole

E~mulator

NOTE
The above functions are the same for a boot initiated
by the boot switch except that SI-2 may be ON or
OFF.

8-3

NORMAL MODE
OFFSET
SWITCH
SETTINGS

I
I

000

002

226

CPU
DIAGNOSTIC
TESTS '·6

USER
POWER
UP

Y
EXTENDED
CPU
DIAGNOSTIC
TESTS 6,7

MEMORY
SIZING

MEMORY
DIAGNOSTIC
TESTS

BOOTTHE
DEVICE
SELECTED IN
KEYBOARD
DISPATCH

BOOTTHE
DEVICE
SELECTED IN
KEYBOARD
DISPATCH
11-4861

Figure 8-3

M9301-YB Program Flowchart

8-4

8.4 DIAGNOSTICS
An explanation of the eight CPU and memory diagnostic tests follows. Three types of tests are included in the M9301-YB diagnostics:
1.
2.
3.

Primary CPU tests (1-5)
S(~condary CPU tests (6, 7)

Memory test (8)

8.4.1 Primary CPU Tests
The primary CPU tests exercise all unary and double operand instructions with all source modes.
These tests do not modify memory. If a failure is detected, a branch-self (BR.) will be executed. The
run light will stay on, because the processor will hang in a loop, but there will be no register display.
The user must use the halt switch to exit from the loop. If no failure is detected in tests 1-5, the
processor will emerge from the last test and enter the register display routine (console emulator).
TEST 1 - SINGLE OPERAND TEST
This test eXlecutes all single operand instructions using destination mode O. The basic objective is to
verify that all single operand instructions operate; it also provides a cursory check on the operation of
each instruction, while ensuring that the CPU· decodes each instruction in the correct manner.
Test 1 tests the destination register in its three possible states: zero, negative, and positive. Each
instruction operates on the register contents in onl~ of four ways:
1.

Data will be changed via a direct operation, i.e., increment, clear, decrement, etc.

Data will be changed via an indirect operation, i.e., arithmetic shifts, add carry, and subtract
carry.

Data will be unchanged, but operated upon, via a direct operation, i.e., clear a register
already containing zeros.

Data will be unchanged but examined via a non-modifying instruction (TEST).
NOTE
When operating upon data in an indirect manner, the
data is modified by the state of the appropriate condition code. Arithmetic shift will move the C bit into
or out of the destination. This operation, when performed correctly, implies that the C bit was set correctly by the previous instruction. There are no
checks on the data integrity prior to the end of the
test. However, a check is made on the end result of
the data manipulation.; A 4:orrect result implies that
all instructions manipulatE~d the data in the correct
way. If the data is incorrect, the program will hang in
a program loop until the machine is halted.

TEST 2 - DOUBLE OPERAND, ALL SOURCE MODES
This test verifies all double operand, general, and logical instructions, each in one of the seven addressiing modes (c~xcludes mode 0). Thus two operations: are checked: the correct decoding of each double
operand instruction, and the correct operation of c~ach addressing mode for the source operand.

8-5

Each instruction in the test must operate correctly in order for the next instruction to operate. This
interdependence is carried through to the last instruction (bit test) where, only through the: correct
execution of all previous instructions, a data field is examined for a specific bit configuratioll1. Thus,
each instruction prior to the last serves to set up the pointer to the test data.
Two checks on instruction operation are made in test 2. One check, a branch on condition, is made
following the compare instruction, while the second is made as the last instruction in the test se1quence.
Since the GO-NO GO test resides in ROM memory, all data manipulation (modification) must be
performed in destination mode 0 (register contains data). The data and addressing constants used by
test 2 are contained within the ROM.
It is important to note that two different types of operations must execute correctly in order for this
test to operate:

Those instructions that participate in computing the final address of the data mask for the
final bit test instruction.

Those instructions that manipulate the test data within the register to generate the c::xpected
bit pattern.

Detection of an error within this test results in a program loop.

TEST 3 - JUMP TEST MODES 1,2,3
The purpose of this test is to ensure correct operation of the jump instruction. This test is constructed
such that only a jump to the expected instruction will provide the correct pointer for the next
instruction.
There are two possible failure modes that can occur in this test:
1.

The jump addressing circuitry will malfunction causing a transfer of executioll1 to an
incorrect instruction sequence or non-existent memory.

The jump addressing circuitry will malfunction in such a way as to cause the CPU to loop.

The latter case is a logical error indicator. The former, however, may manifest itself as an after··the-fact
error. For example, if the jump causes control to be given to other routines within the M930I, the
interdependent instruction sequences would probably cause a failure to eventually occur. In any case,
the failing of the jump instruction will eventually cause an out of sequence or illogical event to occur.
This in itself is a meaningful indicator of a malfunctioning CPU.
This test contains a jump mode 2 instruction which is not compatible across the PDP-II line. However, it will operate on any PDP-II within this test, due to the unique programming of the instruction
within test 3. Before illustrating the operation, it is important to understand the differences of the jump
mode 2 between machines.
On the PDP-I 1/20, 11/05,11/15, and 11/10 processors, for the jump mode 2 [JMP(R)+], the register
(R) is incremented by 2 prior to execution ofthejump. On the PDP-l 1/04, 11/34, 11/35, 11/40, 11/45,
11/50, 11/55, and 11/70, (R) is used as the jump address and incremented by 2 after execution of the
jump.

8-6

In order to avoid this incompatability, the JMP (R)+ is programmed with (R) pointing back on the
jump itself" On 11/20, 11/05, 11/10, and 11/15 processors, execution of the instruction would cause
(R) to be incremented to point to the following instruction, effectively continuing a normal execution
sequence.
On the PDP-ll/04, 11/34, 11/35, 11/40, 11/45, 11/50, 11/55, and 11/70 processors, the use of the
initial value of (R) will cause the jump to loop back on itself. However, correct operation of the
autoincrement will move (R) to point to the next instruction following the initial jump. The jump will
then be exe:cuted again. However, the destination address will be the next instruction in sequence.
TEST 4 - SINGLE OPERAND, NON-MODIFY][NG BYTE TEST
This test fOlcuses on one unique single operand instruction, the TST. TST is a special case in the CPU
execution flow since it is a non-modifying operation. Test 4 also tests the byte operation of this instruction. The TSTB instruction will be executed in mode 1 (register deferred) and mode 2 (register
deferred, autoincrement).
The TSTB is programmed to operate on data whkh has a negative value most significant byte and a
zero (not ntegative) least significant byte.
In order for this test to operate properly, the TSTB on the low byte must first be able to access the even
addressed byte and then set the proper condition codes. The TSTB is then reexecuted with the
autoincrement facility. After the autoincrement, the addressing register should be pointing to the high
byte of the test data. Another TSTB is executed on what should be the high byte. The N bit of the
condition codes should be set by this operation.
Correct execution of the last TSTB implies that the autoincrement recognized that a byte operation
was requested, thereby only incrementing the add.ress in the register by one, rather than two. If the
correct condition code has not been set by the associated TSTB instruction, the program will loop.
TEST 5 - DOUBLE-OPERAND, NON-MODIFYING TEST
Two non-modifying, double-operand instructipns are used in this test - the compare (CMP) and bit
test (BIT). These two instructions operate on test data in source modes 1 and 4, and destination modes
2 and 4.
The BIT and CMP instructions will operate on data consisting of all ones (177777). Two separate fields
of ones are used in order to utilize the compare instructions, and to provide a field large enough to
handle the autoincrementing of the addressing register.
Since the compare instruction is executed on two fields containing the same data, the expected result is
a true Z bit, indicating equality.
The BIT instruction will use a mask argument of all ones against another field of all ones. The expected
result is a non-zero condition (Z).
Most failurles will result in a one instruction loop.
On successful completion of test 5, the register display routine is enabled, provided the console emulator has been selected in the microswitches. This routine prints out the octal contents of the CPU
registers RO, R4, SP, and old PC on the console terminal. This sequence will be followed by a prompt
character ($) on the next line.

8-7

An example of a typical printout follows.

XXXXXX

XXX XXX

R6
(Stack
Pointer)

R5
(Old PC)

Prompt
Character
NOTES:
1.

Where X signifies an octal number (0-7).

Whenever there is a power-up routine or the boot switch is released on PDP-I 1/04 and
PDP-I 1/34 machines, the PC at this time will be stored in R5. The contents of R5 are then
printed as the old PC shown in the example.

The prompting character string indicates that diagnostics have been run and the processor is
operating.

8.4.2 Secondary CPU and Memory Tests
The secondary CPU tests modify memory and involve the use of the stack pointer. The JMP and JSR
instructions and all destination modes are tested. If a failure is detected, these tests, unlike the primary
tests, will execute a halt.
Secondary CPU and memory diagnostics are run immediately after test 5 when they have been evoked
by means other than the console emulator, provided that the correct microswitches have bec~n set. If
tlhe console emulator has been entered at the completion of test 5, the secondary CPU and memory
diagnostics will be run when the appropriate boot command is given.
Note that the user can execute the secondary CPU and memory diagnostics without running a bootstrap program. A false boot command (an invalid device code followed by a carriage return) will cause
execution of tests 6, 7, and 8 before the attempt to boot is made. If these tests are executed succ:essfully,
the device will be called but not found. The processor will trap to location 4, which has been set up by
the M930 1-VB. A new PC is obtained at location 4, causing control to return to the console elm ulator.
The readings of the four registers are now available, and the old PC is the highest location in tnemory.
A failure in one of the tests will, of course, cause a halt.
TEST 6 - DOUBLE OPERAND, MODIFYING BYTE TEST
The objective of this test is to verify that the double-operand, modifying instructions will operate in the
byte mode. Test 6 contains three subtests:
1.
2.
3.

Test source mode 2, destination mode 1, odd and even bytes
Test source mode 3, destination mode 2
Test source mode 0, destination mode 3, even byte.

The move byte (MOYB), bit clear byte (BICB), and bit set byte (BISB) are used within test 6 to verify
the operation of the modifying double-operand functions.
Since modifying instructions are under test, memory must be used as a destination for the test data.
Test 6 uses location 500 as a destination address. Later, in test 7 and the memory test, location 500 is
used as the first available storage for the stack.

8-8

Note that since test 6 is a byte test, location 500 implies that both 500 and 501 are used for the byte
tests (even and odd, respectively). Thus, in the word of data at 500, odd and even bytes are caused to be
all Os and then all I s alternately throughout the test.. Each byte is modified independently of the other.

TEST 8 - MEMORY TEST
Although this test is intended to test both core and MOS memories, the data patterns used are
designed to exercise the most taxing operation for MOS. Before the details of the test are described, it
would be appropriate to discuss the assumptions placed upon the failure modes of the MOS
technology .
This test is intended to check for two types of problems that may arise in the memory.
1.
2.

Solid element or sense amp failures
Addressing malfunctions external to tht~ chip.

The simplest failure to detect is a solid read or write problem. If a cell fails to hold the appropriate
data, it is c~xpected that the memory test will easily detect this problem. In addition, the program
attempts to saturate a chip in such a way as to cause marginal sense amp operation to manifest itself as
a loss or pick-up of unexpected data. The 4K- X I-chip used in the memory consists of a 64- X 64matrix of ~10S storage elements. Each 64-bit section is tied to a common sense amplifier. The objective of the program is to saturate the section with, at first all Os and one I-bit. This I-bit is then floated
through th(~ chip. At the end, the data is complenrlented, and the test repeated.
For external addressing failures, it is assumed that if two or more locations are selected at the same
time, and a write occurs, it is likely that both locations will assume the correct state. Thus, prior to
writing any test data, the background data is chet~ked to ensure that there was no crosstalk between
any two locations. All failures will result in a program halt as do failures in tests 6 and 7.

NOTE
If the expected and recehred data are the same, it is
highly probable that an illltermittent failure has been
detected (i.e., timing or margin problem). The reason
the expected and received data can be identical is
that the test program rl~reads the failing address
after the initial non-compare is detected. Thus, a
failure at CPU speed is detected, and indicated by
the reading of the failing address on a single reference (not at speed) operation.

8.5 TROUBLESHOOTING THROUGH REGISTER DISPLAY
When a halt occurs, the user should reboot the system by pressing the BOOT /INIT switch. The
registers RO, R4, R6, and R5 will be displayed on the terminal in that order.
RO
R4
R6
R5

Expected data
Received data
Failing address (SP)
Old PC

8·-9

The diagnostic program in the M9301-YB will cause the processor to jump to one of four addresses:
165316, 165346, 165370, or 165534. The user should consult the diagnostic program listing to find the
failing test and begin troubleshooting. Possible causes of the failure include bus errors, a bad M9301
module, and a bad CPU.

8-10

CHAPTER 9
M9301-YC

9.1 INTRODUCTION
The M9301-YC is used primarily in the PDP-ll/70. It contains basic CPU, cache, and memory diagnostics. It can boot from anyone of 8 devices and to anyone of the 16 lowest 32K banks of memory
(0-SI2K).
The PDP-Ii /70 requires pull-up resistors on the bus grant lines, so WI through WS must be installed.
Refer to ECO M9301-0000S to determine if W6 nlust be installed.
The ROM routine causes a device code, drive number, and desired bank to be obtained from the
console switch register after load and start. If the SWR is 0, then device code and drive number are
obtained from the M9301 microswitches (32K bank 0 is used). For instructions on how to start, refer
to Paragraph 9.6.
Figure 9-1 shows a memory map for the M9301-YC ROMs. MAINDEC-II-DEKBH is a listing of the
code. A copy of this may be found in the PDP-l1/70 ~§'tms lV1ahutz/. ;vt."/JI/( <:J., I",.". >r/lt.t~ T/ttJ../"" 1 ./'fl- CACHE MEMORY DIAGNOSTICS

17773777

____B_O_OT_S_TR
....A_P_PR__O_G_RA_M___ 17773000

CPU & MAIN DIAGNOSTICS

1'7765777
17765000
11-4873

Figure 9-1

Program Memory Map for the M9301-YC

9--1

(,,"-4' L

9.2 DIAGNOSTIC TEST EXPLANATION
The diagnostic portion of the program will test the basic CPU, including the branches, the regis.ters, all
addressing modes, and most of the instructions in the PDP-II repertoire. It will then set the stack
pointer to kernel D-space PAR 7. It will also turn on, if requested, memory management and the
Unibus map, and will check memory from virtual address 100 to 157776. After main memory has been
verified, with the cache off, the cache memory will be tested to verify that hits occur properly. Main
memory will be scanned again to ensure that the cache is working properly throughout the 28K of
memory to be used in the boot operation.
If one of the cache memory tests fails, the operator can attempt to boot the system anyway by pressing
continue. This will cause the program to force misses in both groups of the cache before going to the
bootstrap section of the program.
A listing of the M9301-YC diagnostic tests follows.
TEST 1
TEST 2
TEST 3
TEST 4
TEST 5
TEST 6
TEST 7
TEST 10
TEST 11
TEST 12
TEST 13
TEST 14
TEST 15
TEST 16
TEST 17
TEST 20
TEST 21
TEST 22
TEST 23
TEST 24
TEST 25
TEST 26
TEST 27
9.3

This test verifies the unconditional branch
Test CLR, MODE 0, and BMI, BVS, BHI, BLOS
Test DEC, MODE 0, and BPL, BEQ, BGE, BGT, BLE
Test ROR, MODE 0, and BVC, BHIS, BHI, BNE
Test BHI, BLT, and BLOS
Test BLE and BGT
Test register data path and modes 2, 3, 6
Test ROL, BCC, BLT, and MODE 6
Test ADD, INC, COM, and BCS, BLE
Test ROR, BIS, ADD, and BLO, BGE
Test DEC and BLOS, BLT
Test COM, BIC, and BGT, BGE, BLE
TestADC,CMP, BIT, and BNE, BGT, BEQ
Test MOVB, SOB, CLR, TST and BPL, BNE
Test ASR, ASL
Test ASH, AND SW AB
Test 16 KERNEL PARs
Test and load KIPDRs
Test JSR, RTS, RTI, and JMP
Load and turn on memory management and the Unibus map
Test main memory from virtual 100 to 28K
Test cache data memory
Test virtual28K with cache on

DIAGNOSTIC TEST DESCRIPTIONS

TEST 1 - This test verifies the unconditional branch.
The registers and condition codes are all undefined when this test is entered and they should remain
that way upon the completion of this test.
TEST 2 - Test CLR, MODE 0, and BMI, BVS, BHI, BLOS.
The registers and condition codes are all undefined when this test is entered. Upon completion of this
test the SP (R6) should be zero and only the Z flip-flop will be set.
TEST 3 - Test DEC, MODE 0, and BPL, BGE, BGT, BLE.
Upon entering this test the condition codes are: N = 0, Z = I, V = 0, and C = O.
The registers are: RO = ?, Rl = ?, R2 = ?, R3 = ?, R4 = ?, R5 = ?, and SP = 000000.
Upon completion of this test the condition codes will be: N = 1, Z = 0, V = 0, and C = O.
The registers affected by the test are: SP = 177777.
9-2

TEST 4 - Test ROR, MODE 0, and BVe, BHIS, BUI, BNE.
Upon entering this test the condition codes are: N' = 1, Z = 0, V = 0, and C = O.
The registers are: RO = ?, Rl = ?, R2 = ?, R3 = ?, R4 = ?, R5 = ?, and SP = 177777.
Upon completion of this test the condition codes will be: N = 0, Z = 0, V = 1, and C = 1.
The registers affected by the test are: SP = 077777.
TEST 5 - Test BUl, BLT, and BLOS.
Upon entering this test the condition codes are: 1'1l = 0, Z = 0, V = 1, and C = 1.
The registers are: RO = ?, Rl = ?, R2 = ?, R3 = ?, R4 = ?, R5 = ?, and SP = 077777.
Upon completion of this test the condition codes will be: N = 1, Z = 1, V = 1, and C = 1.
The registers are unaffected by the test.
TEST 6 - Test BLE and BGT.
Upon entering this test the condition codes are: 1'1l = 1, Z = 1, V = 1, and C = 1.
The registers are: RO = ?, Rl = ?, R2 = ?, R3 = ?, R4 = ?, R5 = ?, and SP = 077777.
Upon completion of this test the condition codes will be: N = 1, Z = 0, V = 1, and C = 1.
The registers are unaffected by the test.
TEST 7 - Tcst register data path and modes 2, 3, 6.
When this test is entered the condition codes are: N = 1, Z = 0, V = 1, and C = 1.
The registers are: RO = ?, Rl = ?, R2 = ?, R3 = ?, R4 = ?, R5 = ?, and SP = 077777.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are left as follows: RO = 125252, R 1 =: 000000, R2 = 125252, R3 = 125252, R4 = 125252,
R5 = 125252, SP = 1225252, and MAPLOO == 125252.
TEST 10 - Test ROL, BCC, BLT, and MODE 6.
When this test is entered the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are: RO = 125252, R 1 = 000000, R2 =: 125252, R3 = 125252, R4 = 125252, R5 = 125252,
SP = 125252, and MAPLOO = 125252. Upon completion of this test the condition codes are: N = 0, Z = 0, V = 1, and C = 1.
The registe:rs are left unchanged except for MAPLOO which should now equal 052524.
TEST 11 - Test ADD, INC, COM, and BCS, BI,E.
When this test is entered the condition codes are: N = 0, Z = 0, V = 1, and C = 1.
The registers are: RO = 125252, R 1 = 000000, R2 =: 125252, R3 = 125252, R4 = 125252, R5 = 125252,
SP = 125252, and MAPLOO = 052524.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are left unchanged except for R3 whkh now equals 000000, and Rl which is also 000000.
TEST 12 -, Test ROR, BIS, ADD, and BLO, BG]~.
When this test is entered the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are: RO = 125252, R 1 = 000000, R2 == 125252, R3 = 030000, R4 = 125252, R5 = 125252,
and SP = 125252.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are left unchanged except for R3 whkh should be modified back to 000000, and R4 which
should now equal 052525.
TEST 13 -, Test DEC and BLOS, BLT.
When this test is entered the condition codes are:: N = 0, Z = 1, V = 0, and C = O.
The registers are: RO = 125252, Rl = 000000, R2 == 125252, R3 = 000000, R4 = 052525, R5 = 125252,
and SP = 125252.
Upon completion of this test the condition codes are: N = 1, Z = 0, V = 0, and C = O.
The registe:rs are left unchanged except for R 1 which should now equal 177777.

9-3

TEST 14 - Test COM, BIC, and BGT, BLE.
When this test. is entered the condition codes are: N = 1, Z = 0, V = 0, and C = O.
The registers are: RO = 125252, Rl = 177777, R2 = 125252, R3 = 000000, R4 = 052525, R5 = 125252,
and SP = 125252.
Upon complet.ion of this test the condition codes are: N = 0, Z = 0, V = 1, and C = 1.
The registers are left unchanged except for RO which should now equal 052525, and Rl which should
now equal 052524.
TEST 15 - Test ADC, CMP, BIT, and BNE, BGT, BEQ.
When this test is entered the condition codes are: N = 0, Z = 0, V = 1, and C = 1.
The registers are: RO = 052525, Rl = 052524, R2 = 125252, R3 = 000000, R4 = 052525, R5 = 125252,
and SP = 125252.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are now: RO = 052525, Rl = 000000, R2 = 125252, R3 = 000000, R4 = 052525, R5 =
052525, and SP = 125252.
TEST 16 - Test MOVB, SOB, CLR, TST and BPL, BNE.
When this test is entered the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are: RO = 052525, Rl = 000000, R2 = 125252, R3 = 000000, R4 = 052525, R5 = 1052525,
and SP = 125252.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 0, and C = O.
RO is decremented by an SOB instruction to 000000; R 1 is cleared and then incremented around to
000000.
TEST 17 - Test ASR, ASL.
When this test is entered the condition codes are:: N = 0, Z = 1, V = 0, and C = O.
The registers are: RO = 125252, Rl = 000000, R2 = 125252, R3 = 000000, R4 = 052525, R5 = 1052525,
and SP = 125252.
Upon completion of this test the condition codes are: N = 0, Z = 0, V = 0, and C = O.
The registers are left unchanged except for RO which is now equal to 000000, Rl which is now 1000001,
and R2 which is now 000000.
TEST 20 - Test ASH, and SWAB.
When this test is entered the condition codes are: N = 0, Z = 0, V = 0, and C = O.
The registers are: RO = 000000, Rl = 000001, R2 = 000000, R3 = 000000, R4 = 052525, R5 = 052525,
and SP = 125252.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 0, and C = 1.
The registers are left unchanged except for R 1 which should now equal 000000.
TEST 21 - Test 16 KERNEL PARs.
When this test is entered the condition codes are: N = 0, Z = 1, V = 0, and C = 1.
The registers are: RO = 000000, R 1 = 000000, R2 = 000000, R3 = 000000, R4 = 052525, R5 = 052525,
and SP = 125252.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 00, and C = O.
TIle registers now equal: RO = 172400, R 1 = 000000, R2 = 000000, R3 = 000000, R4 = 052525~1 R5 =
125252, and SP = 125252.
AJI KERNEL PARs = 125252.
TEST 22 - Test and load KIPDRs.
When this test is entered the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are: RO = 172400, R 1 = 000000, R2 = 000000, R3 = 000000, R4 = 052525, R5 = 125252,
and SP = 125252.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers that are modified are: RO = 172300, Rl = 000000, and R2 = 077406.
All KERNEL I-SPACE PDRs (172300 - 172316) = 077406.
9-4

TEST 23 - Test JSR, RTS, RTI, JMP.
This test first sets the stack pointer to KDPAR 7 (1.72376), and then verifies that JSR, R TS, RTI, and
JMP all work properly.
On entry to this test the stack pointer (SP) is initialized to 172376 and is left that way on exit.
TEST 24 - Load and turn on memory management and the Unibus mapp.
This test is only executed if the upper 4 bits « 15: 12» of the switch register are non-zero. The test will
load memory management to relocate to the 32K block number specified. It will also set up the Unibus
addresses correctly. (If bits < 15: 12> specify block number 3, the user should boot into memory from
96K to 128K. The KIP ARs will be loaded as follows: KIPARO = 006000, KIPAR 1 = 006200,
KIPAR2 = 006400, KIPAR3 = 006600, KIPAR4 = 007000, KIPAR5 = 007200, KIPAR6 = 007400.
KIPAR7 will always equal 177600.)
The Unibus map registers will then be set as follows: MAPLO = 000000, MAPHO = 03, MAPLI =
020000, MAPH 1 = 03, MAPL2 = 040000, MAPH2 = 03, MAPL3 = 060000, MAPH3 = 03, MAPL4
= 100000, I\1APH4 = 03, MAPL5 = 120000, MAPH5 = 03, MAPL6 = 140000, MAPH6 = 03.
TEST 25 - Test main memory from virtual 1000 t(]l 28K.
This test will test main memory with the cache disabled, from virtual address 001000 to 157776. If the
data does not compare properly, the test will halt at either 165740 or 165776. If a parity error occurs,
the test will halt at address 165776, with PC + 2 on the stack which is in the KERNEL D-SPACE
PARs.
In this test the registers are initialized as follows: RO = 001000, R 1 = DATA READ, R2 = 067400, R3
= 0001000, R4 = 067400, R5 = 177746 (control register), SP = 172376.
The following two tests are cache memory tests. ][f either fails to run successfully, the program will
come to a halt in the M9301 ROM. If you desire to try to boot your system or diagnostic, you can press
continue and the program will force misses in both groups of the cache and go to the bootstrap that
has been selected.
TEST 26 - Test cache data memory.
This test will check the data memory in the cache, first group 0 and then group 1. It loads 052525 into
an address, ,complements it twice and then reads the:: data. It then checks that address to ensure the data
was a hit. The sequence is repeated on the same address with 125252 as the data. All cache memory
data locations are tested in this way. If either group fails and the operator presses continue, the program will try to boot with the cache disabled.
The registers are initialized as follows for this test: RO = 001000 (address), Rl = 000002 (count), R2 =
001000 (count), R3 = 001000 (count), R4 = 1252:52 (pattern), R5 = 17771';6 (control register), SP =
172374 (flag of zero pushed on stack).
TEST 27 - Test virtual 28K with cache on.
This test checks virtual memory from 001000 through 157776 to ensure that you can get hits all the way
up through main memory. It starts with group 1 enabled, then tests group 0, and finally checks memory with both groups enabled. If anyone of the threc~ passes fail, the test will halt at CONT + 2. Then if
the operator presses continue, the program will try to boot with the cache disabled.
Upon entry the registers will be set up as follows: RO = 001000 (address), Rl = 000003 (pass count),
R2 = 067400 (memory counter), R3 = 001000 (first address), R4 = 067400 (memory counter), R5 =
177746 (control register), SP = 172374 (pointing to code for control register).
Upon completion of this test, main memory from virtual address 001000 through 157776 will contain
its own virtual address.
9··5

9.4 PDP-ll/70 BOOTSTRAP
The bootstrap portion of the program (beginning at 17773000) looks at the lower byte of the console
switch register to determine which one of eight devices and which one of eight drives to boot from.
Switches <02:00> select the drive number (0-7), and switches <07:03> select the device code (1-11) to
be used. If the lower byte of the switch register is zero, the program will read the set of microswitches
on the M9301 to determine the device and drive number. These switches can be set to select a. default
boot device (provided the console SWR is 0).
If the bootstrap operation fails as a result of a hardware error in the peripheral device, the program
will do a RESET instruction, jump back to the test that sets up memory management, and will attempt
to boot again.

9.5 MICROSWITCHES
Switch SI-1 is the low ROM enable switch. It is used to inhibit (when OFF) the M9301-YC from
responding to addresses 17765000-17765777. Switch SI-2 is the power-up reboot enable switch. It
enables the M9301-YC ROM on power-up. Switches SI-3 through SI-10 correspond to bus data bits
8-1 respectively. They are read when location 17773024 is accessed (Figure 9-2).

Address bits

Switches S1

LOW
ROM
ENABLE

t i 4

POWER UP
REBOOT
ENABLE
1

NOTE:
On = 0

~
DRIVE '#

.......
DEVICE '#

Off = 1

Figure 9-2

11-4864

Microswitch Assignment

Since the external boot switch and boot on power-up capabilities are available on the M9301-YC
(ECO M9301·00005), if all required ECOs are included and microswitch SI-2 is ON, the PDP-l1/70
will boot (dependent on console switch register and/or the microswitches) on a power-up. If booting
on power-up is not desired, switch S 1-2 should be OFF.
If the operator wishes to load address 17765000 and start (or boot on power-up), switch S 1-1 should be
on. However, some peripheral devices in the system may require bus addresses in the range of
17765000-17765777. In this case switch SI-1 must be OFF. With switch SI-1 OFF, the M9301-YC
must be started at location 17773000 or an SSYN time-out will occur. Microswitches S 1-3 through S I10 are used whenever 17765000 or 17773000 is loaded and the processor is started from the console,
and the console switches are set equal to 0 (all ON). Microswitches SI-8 through SI-10 correspond to
drive numbers. Microswitches S 1-3 through S 1-7 correspond to device codes. For example, the RK05
drive 1 is selected through the following configuration:

S 1-1
ON/OFF

SI-2
ON/OFF

SI-3
ON

SI-4
OFF

SI-5
OFF

SI-6
ON

SI-7
OFF

SI-8
ON

SI-9
ON

SI-10
OFF

l'f ote that only eight devices can be selected (1-4 and 6-11). Device code 5 is reserved. Use of this code

will result in errors.
Figure 9-3 shows a program flowchart for the M9301-YC. Notice that the choice of routines is determined by jumpers and microswitch settings as well as console switch register settings.
9-6

OPERATOR
DECISION

CONTENTS
OF THIS
ADDRESS
ARE USED
AS THE
STARTING
ADDRESS

NORMAL
POWER UP
SEQUENCE
THROUGH
STARTING VECTOR

ERROR
RESULTS
NOT
PREDICTABLE

DIAGNOSTIC
TESTS

GET DATA
FROM MICROSWITCH
SETTINGS LOC
MEMORY BANK

POWER UP
SEQUENCE
THRU STARTING
VECTOR
17773224

BOOT FROM
DRIVE II AND
DEVICE II
SELECTED INTO
MEMORY ElANK
SELECTED

BOOT
DRIVE llANO
DEVICE II
SELECTED INTO
MEMORY BANK

JUMPTO
LOCATION 0
TO START
PROGRAM

* Note:Jumpers WI through W5 must be installed
or system behavior is unpredictable_
11-4863

Figure 9-3

M9301-YC Program Flowchart

9-7

9.6 STARTING PROCEDURE
9.6.1 Console Switch Settings
The lower byte of the console switch register should be set to have the drive number (0-7) in switches
<02:00>, and the device code (1-11) in switches <07:03>.
The upper byte of the switch register should be set to have the bank number of the 32K block of
memory for the bootstrap operation (0-17) in switches < 15:12>.
The memory blocks are as follows:

o
1
2
3
4

Physical Memory 0-28K
Physical Memory 32K-60K
Physical Memory 64K-92K
Physical Memory 96K-124K
Physical Memory 128K-156K

Physical Memory 256K-284K

14
15
16
17

Physical Memory 384K-412K
Physical Memory 416K-444K
Physical Memory 448K-476K
Physical Memory 480K-508K

9.6.2 Starting Addresses
The normal starting address for the diagnostic and boot routine is 17765000 (microswitch SI-1 nlust be
ON). If the diagnostic portion of this program fails and the operator wants to attempt to boot anyway,
he must follow these steps:
1.

Set up memory management if booting into other than the lower 28K of memory. BUS
INIT (console start) initializes memory management to 0-28K of main memory.

2a. If the device is on the Massbus, set stack pointer to a valid address and load that address
with the memory bank number put into switches <15:12>.
2b. If the device is on the Unibus, set up Unibus map registers 0 through 6 to map to the same
memory as memory management. BUS INIT (console start) initializes the map to 0-128K of
main memory.
3.

Deposit address 173000 into the PC.

Set the device code and drive number in the lower byte of the switch register.

Press continue.

Examples:
A.

RP04-

Set stack pointer to 40000,
load 000000 into address 40000,
load 173000 into the PC (17777707),
set 000070 into switches (RP04 drive 0),
press continue.

RKOS-

Load 173000 into the PC (17777707),
set 000030 into switches (RKOS drive 0),
press continue.
9-8

9.6.3 Operator Action
If the diagnostic portion of the ROM routine fails, record PC of the instruction and refer to the listing
to find out which test in the program failed.
9.7 ERRORS
Table 9-1 is a list of error halts indexed by the address displayed.
Table 9-1

Error Halts

Address Displayed

Test Number and Subsystem Under Test

17765004
17765020
17765036
17765052
17765066
17765076
17765134
17765146
17765166
17765204
17765214
17765222
17765236
17765260
17765270
17765312
17765346
17765360
17765374
17765450
17765474
17765510
17765520
17765530
17765542
17765550
17765760
17766000

Test 1, Branch Test
Test 2, Branch Test
Test 3, Branch Test
Test 4, Branch Test
Test 5, Branch Test
Test 6, Branch Test
Test 7, -Register Data Path Test
Test 10, Branch Test
Test II, CP1) Instruction Test
Test 112, CPU Instruction Test
Test 13, CPU Instruction Test
Test 14, COM Instruction Test
Test 14, CPU Instruction Test
Test 15, CP1) Instruction Test
Test 16, Branch Test
Test 16, CPU Instruction Test
Test 17, CPU Instruction Test
Test 20, CPU Instruction Test
Test 20, CP1) Instruction Test
Test 21, KERNAL PAR Test
Test 22, KERNALPAR Test
Test 23, JSR Test
Test 23, JSR Test
Test 23, RTS Test
Test 23,RT][ Test
Test 23, JMP Test
Test 25, Mai.n Memory Data Compare Error
Test 25, Main Memory Parity Error
(no recovery possible from this error)
Test 26, Cache Memory Data Compare Error
Test 26, Cache Memory No Hit
(Pressing coltltinue here will cause
boot attempt forcing misses)
Test 27, Cache Memory Data Compare Error
Test 27, Cache Memory No Hit
(Pressing coltltinue here will cause
boot attempt forcing misses)
Test 25 OR 26, Cache Memory Parity Error
(Pressing continue here will cause
boot attempt forcing misses)

17773644
17773654
17773736
17773746
17773764

9-9

Error Recovery
Most of the error halts are hard failures (there is no recovery). If main memory halts are the fault, try
booting to another bank (if the program is relocatable) or swap modules from another bank with bank

If the processor halts in one of the two cache tests, the error can be recovered from. Press continue to
finish the test (if at either 17773644 or 17773736) or force misses in both groups of the ca1che and
attempt to boot the system monitor with the cache disabled (if at either 17773654, 17773746, or
17773764).
If this program fails in an uncontrolled manner, it might be due to an unexpected trap to llocation
000004. If this is suspected, then load a 000006 into address 000004 and a 000000 into location 000006.
This will cause all traps to location 000004 to halt with 00000010 in the address lights. The operator
can then examine the CPU error register at location 17777766.
The bits in the CPU error register are defined as follows:
Bit 02 = Red zone stack limit
Bit 03 = Yellow zone limit
Bit 04 = Unibus time-out
Bit 05 = Nonexistent memory (cache)
Bit 06 = Odd address error
Bit 07 = Illegal halt

9-10

CHAPTER 10
M9301-YD

10.1 INTRODUCTION
The M9301-YD is programmed to provide transparent pass-through of data between a terminal on a
satellite cornputer and an asynchronous serial. linc~ on the same computer. It also contains all of the
necessary instructions for requesting a secondary naode program load and accepting a down-line load
on its serial line from another machine using Dl)CMP protocol. These features enable a PDP-II
computer to be a satellite in a REMOTE-II system.

The M9301··YD ROM will run on any PDP-II cornputer. Two DLI1s are required with the following
addresses and vectors:
Function

Addn~ss

Vector

Local Terminal
Interprocessor

177560
1756]lO

60
400

The ROM may be activated by placing the starting address for the desired type of bootstrap in the
switch register and pressing LOAD ADDRESS, START, or by utilizing the power-up bootstrap feature of the M9301-YD with proper setting of the address offset microswitches.
Figure 10-1 shows the relation of the microswitches to the starting address. Figure 10-2 is the
M9301-YD power-up flowchart.

LOW ROM ENABLE

POWER UP IftEBOOT ENABLE

I •I +
2

CORRESPONDING
BUS ADDRESS BITS
BINARY VALUE
OF SWITCHES

S1 SWITCHES

OCTAL VALUES
OF SWITCHES

V
ON = 0
OFF = 1

Figure 10-1

11-4865

Offset Switches and Corresponding Address Bits

10··1

NO
STARTING
ADDRESS IS

173000

ROM CODE
INITIATED
PASS
THROUGH MODE

[

[
[

MEMORY
SIZE
ASCERTAINED

STARTING
ADDRESS IS

173706

AUTOMATIC
DOWN LINE
LOAD

COMM
REGIONS
SET UP

FLOPPY DISK
BOOTSTRAP
PROGRAM

RESULTS
UNPREDICTABLE

SYSTE:M
POWER UP
THROUGH
LOC 24

ENTER
TERMINAL
MODE
11-5040

Figure 10-2

M9301-YD Program Flowchart

10.2 NORMAL BOOTSTRAP (173000)
The starting address is 173000. Switches SI-1 through SI-10 are on for power-up bootstrap. Ordinarily, when the ROM code is initiated, the satellite comes up in pass-through mode. First, the rnemory
size of the computer is ascertained. Then, necessary communications regions are set up and th~~ OSOP
message "Enter terminal mode" is sent on the serial line. All further communication is in ASCII with
the ROM program polling the ready flags in the four control and status registers to determine the next
action. XON (Q) and XOFF (S) are supported within the satellite computer, and transmission is
assumed to be full duplex.
The only way the terminal mode may be discontinued is through the receipt of a D DCMP nlessage.
The ROM accepts only the following messages: "Program load without transfer address," "Program
load with transfer address," and "Enter terminal mode."

10-2

10.3 SECONDARY MODE BOOTSTRAP (173006)
Switches Sl-l through Sl-8 are ON for use of tht~ power-up bootstrap function. Sl-9 and Sl-lO are
OFF. The alternate starting address 173006 causes an automatic down line load. The "Enter terminal
mode" message is replaced by "Request secondary mode program load." The host machine should
respond to this message with a program load so that terminal mode is only transiently activated. Bus
addresses 177560-177566 will be addressed during this time. The secondary mode program load message may be used for loading programs into satellites without terminals or for loading a scroller into a
machine with a graphics terminal. All other secondary mode actions are identical to those of the
normal bootstrap.
10.4 FLOPPY BOOTSTRAP (173700)
The starting address 173700 should be used for initiating a boot load from a floppy disk. The switches
should be St;!t as follows: Sl-l, Sl-2 ON; SI-3 through Sl-5 OFF; SI-6 through SI-10 ON.
10.5 SENDING DDCMP MESSAGES
A callable subroutine within the ROM will sendl DDCMP boot mode messages. These messages
should be already loaded in memory. Location 162 is loaded by the M9301-YD with the address of this
subroutine. To use it, call from the user program with:
CLR
MOV
JSR

R2
#MSG,R5
PC,@162

;indicatc~ no completion routine

where MSG has the following format:
Bytes 01 and 1 contain the number of bytes in the message
Byte 2 has an asap code
Bytes 3 through n have the data (if any).
The messagt~ is sent using interrupt driven code, but control is not returned to the user program until
the message has been completely sent out.

10.6 RECEIVING DDCMP MESSAGES
A program which has been booted down line from the host to the satellite will automatically receive

ODCMP m1essages if properly initialized and if the interrupt for the serial line receive register is
(~nabled. The: program listing which follows shows the routine which handles the messages. It should be

included in the booted program.
MOV
SUB
MOV
CLR
CLR
JSR
BCS
Add

@162,-(SP)
#62,(SP)
#-9.,R4
R3
R2
PC,@(SP)+
ERROR
#8.,RO

;get RECDDC address
;MSU size
;CRC iniitialize
;completion (move)
;call RECDDC
;point to asap Code

To restart this receiving routine, execute JMP@164.
The M9301-YD uses locations 150-167 for communications and 170-171 for temporary data during
program loads. It also loads location 54 with the high usable memory address. The address in 54 has
been adjusted to leave room for buffers and a stack for use by the ROM.

10-.3

CHAPTER 11
M9301-YE

11.1 INTRODUCTION
The M9301-YE provides DECnet bootstrapping capabilities for the PDP-II system with or without
the console switch register. In addition, the M9301-YE includes a console emulator routine, a paper
tape bootstrap, and some basic CPU and mem,ory GO-NO GO diagnostic tests.
This module has been designed for maximum flexibility of operation. Its function may be initiated in
any of four ways: automatically at power-up, by pressing the console boot switch, by a LOAD
ADDRESS and START sequence, or by using the I:onsole terminal while running the console emulator routine.
11.2 PRO(;RAM MEMORY MAP
Figure 11-1 is a program memory map for theM9301-YE.
773777

BOOTSTRAP PROGRAMS

773000

766777

CONSOLE EMUL"TOR
DIAGNOSTICS

766000
11-4871

Figure 11-1

M9301-YE Program Memory Map

The lower addresses 765000-765777 can be disabled by putting switch SI-1 in the OFF position. This
would free addresses 765000-765777, allowing thc;~ user to occupy this address space. Note that if
switch S 1~ 1 is OFF, the console emulator, the low-speed paper tape boot, and diagnostics are no
longer available.

11··1

Note also that the code in the M9301-YE is written with the assumption that the processor will trap to
Unibus location 24 on power-up if the default boot on power-up feature is to be used. It is also
assumed that a power-up trap to Unibus location 24 will be invoked by the assertion and then nl~gation
of AC LO if the pushbutton boot feature is used.

11.3 MICROSWITCH FUNCTIONS
A set of ten microswitches is located on the M9301 module. They determine which ROM routines are
selected and give the user automatic access to any function.
The primary activating processes for the M9301- YE are the power-up sequence and the enabling of the
console boot switch. Switch SI-I must be in the ON position in order to enable activation of the
M9301-YE console emulator and diagnostics. Switch SI-2 is the power-up reboot enable switch. It
must be ON to enable to M9301-YE on power-up. If switch S 1-2 is OFF, then the processor will trap
to location 24 (as normal) to execute the user power-up routine. When switch SI-2 is ON, the other
switches, SI-3 through SI-IO, determine what action the M9301-YE will take on power-up.
If the system supports a console boot switch, then any time that switch is pressed, the M930 1-YE will
be activated. Enabling the console boot switch causes the processor to enter a ROM routine by creating a fake power down/power-up sequence. The user should note that the position of switch SI-2 is
irrelevant when the console boot switch is used. Pushing the console boot switch thus results in a
power-up sequence in the processor through an M9301-YE ROM routine.

Prior to the power-up sequence, the M9301-YE asserts 773000 on the Unibus address lines. This causes
the new PC to be taken from ROM location 773024 instead of location 000024. The new PC will be the
logical OR of the contents of ROM location 773024 and the eight microswitches on the M9301-YE
module. A switch in the ON position is read as a 0, and a switch in the OFF position is a I. In this way
all the M9301-YE options are accessible. Each option is given a different address. Note that microswitch SI-IO is ORed with bit 1 of the data in ROM location 773024; SI-9 is ORed with bit 2, ,etc. No
switch is provided for combination with bit 0, because an odd address could result when going through
the trap sequence.
The microswitches on the M9301-YE enable the user either to start a bootstrap operation or to enter
the console emulator, simply by pressing the boot switch. Note that a momentary power failure will
have the same effect as pushing the boot switch.
Figure 11-2 shows the relationship of the switches to the bus address bits.

LOW ROM ENABLE

POWER UP REBOOT ENABLE

+ +

S1 .
SWITCHES

I I

CORRESPONDING
BUS ADDRESS BITS
BINARY VALUE
OF SWITCHES

OCTAL VALUES
OF SWITCHES

ON
0
OFF = 1

11·4865

Figure 11-2 Offset Switches and Corresponding Bus Address Bits

11-2

11.4 BOOTSTRAPPING PAPER TAPE
The paper tape boot is unique in that it can do no error checking and that the secondary bootstrap
(e.g., the absolute loader) is read into the upper part of memory. The actual locations loaded by the
paper tape boot are partially determined by the secondary bootstrap itself and by the size routine
which determines the highest available memory address within the first 28K. The paper tape boot
transfers control to location XXX374, where XXX is determined initially by the size routine to be at
the top of memory; this is where the absolute loader will have just been loaded.
Note that the only way to bootstrap a device other than unit 0 is by entering the console emulator to
specify the drive number desired. Otherwise the' bootstraps will default to unit O. This means that only
unit 0 of a device can be bootstrapped without opl:rator intervention.

11.5 DECNET BOOTSTRAPPING: DUll, DLll-E, DUPII
The DECnet bootstrap routines load memory in a satellite computer over a communication link, using
the maintenance operation protocol (MOP) within the DECnet system. The entire bootstrapping proct~SS involves three separate bootstrap programs.
11.5.1 Primary Bootstrap
The primary bootstrap is a mode associated with the communications device within the M9301-YE
ROMs. It requests a secondary boot from the host l~omputer. The primary bootstrap routine will wait
approximate:ly 9 seconds for a reply and then make another request for the secondary boot. If, after
eight tries, the host has not responded, the satellite will hang up the phone for approximately one half
second. Data terminal ready (DTR) is turned OFF and then ON again. After interrupting the communication link:, the primary bootstrap will initiate another series of requests for a secondary boot. The
M9301-YE supports two MOP codes, 8 and 0, as follows. The primary boot sends out a MOP 8
message. It expects a MOP 0 message back. The MOP 0 is the secondary boot which loads the tertiary
boot with transfer address.
If the primary boot detects any errors, it will makc~ the request again.

11.5.2 Secondary Bootstrap
The secondary bootstrap program, once loaded, requests a tertiary boot. These intermediate steps are
iimportant because the boot program which handles the actual loading of the operating system is too
long and complex to be stored in the ROM.
11.5.3 Tertiary Bootstrap
Once the tertiary boot has been requested and loaded, it relocates in upper memory and then begins
the down-line loading of the operating system. Figillre 11-3 is a flowchart showing the relation of the
lthree bootstrap programs.

11··3

ENTRY} - POINTS

POWER
FAIL
BOOT

LOAD
ADDRESS
AND START

CONSOLE
BOOT
BUTTON

CONSOLE
EMULATOR

J
J

START
SECONDARY
BOOT

SETUP
TO RECEIVE
TERTIARY
BOOT

START
PRIMARY
BOOT

REQUEST]
TERTIARY
BOOT

INITIALIZE
COMMUNICATIONS
DEVICE

START
TERTIARY
BOOT

REQUEST
SECONDARY
BOOT
(MOPS)

RELOCATE
TERTIARY
BOOT TO UPPER
MEMORY - UIP TO
124K

START LOA",.G
IN OPERATING
SYSTEM

HANG UP
PHONE

START
OPERATING
SYSTEM

11-5220

Figure 11-3

M9301-YE Down Line Load Flowchart
11-4

11.5.4 MOP Message Formats
The current MOP version (1.2, July 1976) operate:s within DDCMP maintenance envelopes. The current DDC~~P version is 3.03-Dec 1975. All MOP messages are sent in a DDCMP maintenance mode
envelope. This basic DDCMP message provides a CRC block check on the MOP data but does not
provide any acknowledgement of receipt. It is similar to a numbered data message used for conformance with DDCMP formats and hence software/hardware drivers for DDCMP. Its form is as
follows.
SY:N, SYN, DLE, COUNT, Q, S, FILL, FILL, ADDR, CRCl, MOP MSG, CRC2
where:
SYN

=
=
Q =
S =
FILL =
ADDR =
CRCI =
MOPMSG =
CRC2 =
DLE
COUNT

The DDCMP sync c~haracters: (8 bits)
226 synchronous - DUll, DUPll
337 asynchronous - DLll-E
The boot message header character: 220 (8 bits)
The 14-bit count field: number of bytes in MOP message (14 bits)
The async link control flag: (1 bit, always = 1)
The select link control flag: (1 bit, always = 1)
A fill character: 000 (8 bits)
The tributary station address: (for pt-to-pt = 1) (8 bits)
The header CRe on DLE through ADDR (16 bit CRC-16)
The MOP message described below (COUNT 8 bit quantities)
The data CRC on ~[OP message only (16 bit CRC-16)

Notice that the maintenance messages are preceded by 3 or more SYNC characters appropriate to the
link used; synchronous - 226, asynchronous - 337.
The MOP message resides in the data field of the maintenance envelope. The form of the MOP message is:
CODE, INFO
where:
CODE
INFO

=
=

The MOP opera.tion code (8 bits)
The information field (specific to each CODE)

The form of the MOP 8 program (request secondary boot) follows.
CODE (I byte) = 8
MSG DATA = DEY TYPE, STA DDR, (1) PGM TYPE (0)
where:
DEY TYPE (l byte)

The device type at the requesting system. DLII-E = 4, DUll = 2, and
DUPll = 128 •

STA DDR (1 byte)

The address of the requesting station. For point-to-point this is always
1. This is always 1 for the M9301-YEo

PGM TYPE (1 byte)

The type of secondary program requested. PGM type is always 0 for the
M9301-YE.

11-5

The form of the MOP 0 program (memory load with transfer address) follows.
CODE (1 byte) = 0
MSG DATA = LOAD NUM, LOAD ADDR, IMAGE DATA, TRANSFER ADDR
where:
LOAD NUM (1 byte)

The load number for multiple load images. It nlay be
preceded by loads without transfer address. This starts
at 0 and is incremented for each load. This should
always be 0 for the M9301-YEo

LOAD ADDR (4 bytes)

The memory load address (starting address) for the storage of the data image. It should be 0 in MOP O. This
should always be 0 for the M9301-YEo

IMAGEDATA

The image to be stored in the computer memory. The
form sent will be machine dependent and may vary with
the type and word length of the system [e.g., for PDP-II
systems, each byte represents one memory byte (8 bits)].

TRANSFER ADDR (4 bytes)

The starting address of the image just loaded. This is
always 6 for the M9301-YEo

DECnet uses two CPU registers. RO contains the device index code. Rl contains the CSR address of
the device.
11.6 POWER ..UP BOOT AND CONSOLE BOOT
When the operator performs a system power-up or presses the console boot switch, he causes the
M9301 module to react by initiating a bootstrap routine. Table 11-1 shows the correct microswitch
settings for the various options.
11.7 LOAD ADDRESS AND START PROCEDURE VIA CONSOLE SWITCH REGISTER
The user who wishes to initiate a function other than the one which he has specified in the :microswitches can do so without resetting those microswitches. This involves a load address, placing an
option code in the switch register, and start procedure. Thus it can be done only on machine:s with
console switch registers.
The user must load address 173100 and then, before pressing the start switch, he must place a device
code or option code in the switch register. These options and codes are shown in Table 11-2.

11-6

Table 11-1

Microswitch Settings

Function

SI-1

2**

Octal
Code

Console
Emulator
with Diag.

000

Console
Emulator
without Diag.

OFF

002

User Powe:r Fail
Routine through
Vector 24
with Diag.

OFF

062

User Powe:r Fail
Routine through
Vector 24
without Diag.

OFF

064

Boot Paper Tape
Reader with Diag. ON

OFF

106

DECnet Boot
DL11E with Diag. ON

OFF

010

DECnet Boot
DLI1E without
Diag.

OFF

012

DECnet Boot
DUll with Diag.

OFF

154

DECnet Boot
DU 11 without
Diag.

OFF

156

DECnet Boot
DUP11 with Diag. ON

OFF

164

DECnet Boot
DUPII without
Diag.

OFF

166

*= switch setting makes no difference.
** = for pushbutton boot switch setting makes no difference.

11-7

Table 11-2

Load Address and Start Codes

Code

Function

165362
165364
173106
173010
173012
173154
173156
173164
173166

Enter console emulator after running diagnostics
To enter console emulator without running diagnostics
Boot the DLII paper tape with diagnostics
Boot the DECnet DLII-E with diagnostics
Boot the DECnet DLII-E without diagnostics
Boot the D ECnet DUll with diagnostics
Boot the D ECnet DUll without diagnostics
Boot the D ECnet D UPII with diagnostics
Boot the DECnet DUPII without diagnostics

Note that adding two to a code for an option with all diagnostics results in the entry for that option
without any diagnostics.
11.8 OPERATION OF THE M9301-YE CONSOLE EMULATOR
The user can boot a program from any of the four types of peripheral devices by calling the bootstrap
program for that peripheral through the console emulator.
The first routines to be executed (if 000 is the contents of the microswitches) are the primary CPU
diagnostics.
The display routine is entered automatically. This routine will type the contents of RO, R4, R6, and R5
(note the sequence) on the Teletype or terminal in octal. Pressing the console boot switch causes the
PDP-I 1/04 and PDP-I 1/34 systems to copy the PC into R5 before the power-up sequence starts. The
console emulator (keyboard dispatch) program is then entered automatically. This routine types a
carriage return, a line feed, and then the prompt symbol, $. The user can call bootstrap programs at
this point by typing the appropriate device code. He then types an octal number following the device
code specifying the drive number (default 0) and hits the carriage return key. Table 11-3 lists the
peripheral bootstrap programs supported by the M9301-YEo
Note that 12 console fill characters are used between the carriage return and the line feed in the console
em ulator routine.
Table 11-3

Bootstrap Programs

Device

Description

Command*

DLII**
DLIIE
DUll
DUPII

Low Speed Paper Tape Reader
Asynchronous Communications Interface
Synchronous Communications Interface
Synchronous Communications Interface

TT
XL#
XU#
XW#

*The # specifies the unit number (default 0). This may be from 0-178 for XU and XW and 0-36 8 for XL.
**This device is not bootable if S 1 is OFF.

11-8

11.9 RESTARTING AT THE USER POWER FAIL ROUTINE
If the user wishes to restart his own software on a power-up he may do so by merely disabling the
power fail restart switch in the microswitches (turn switch S 1-2 OFF).
But the user can use the M9301- VE to run dhlgnostics (just the primary CPU tests described in Paragraph 11.1 O)} before running his power-up routinl:. This will in no way disturb the contents of memory
and will in fact verify the machine's basic integrity after the power-down and -up sequence.
To use this option the operator should load the 'code 062 into the microswitches as described in
Paragraph 11.7. This will result in the running of the primary CPU diagnostics upon power failure and
then a simulated trap through 24 which will start the user's specified power-up routine.
If the code~ 064 is placed in the microswitches, the~n the simulated trap through 24 is executed without
running diagnostics.

Figure 11-4 is an operator's flowchart showing the relation of the various options and codes available
to the user.
11.10 DIAGNOSTICS
An explanation of the eight CPU and memory dia.gnostic tests follows. Three types of tests are included in the M9301- VE diagnostics:
1.
2.
3.

Primary CPU tests (1-5)
Secondary CPU tests (6, 7)
~v1emory test (8)

11.10.1 CPU Tests
The primary CPU tests exercise all unary and double operand instructions with all source modes.
These tests do not modify memory. If a failure is detected, a branch-self (BR.) will be executed. The
run light will stay ON, because the processor will hang in a loop. If no failure is detected in tests 1-5,
the processor will emerge from the last test and enter the register display routine (console emulator).
TEST 1 - SINGLE OPERAND TEST
This test executes all single operand instructions using destination mode O. The basic objective is to
verify that all single operand instructions operate; it also provides a cursory check on the operation of
each instruction, while ensuring that the CPU de1codes each instruction in the correct manner.

11-9

USER POWER
UP MODE

NORMAL MODE

AUTOMATIC
BOOT MODE

LOAD ADDRESS 773100
AND START MODE

I
I
I

I
000

002

I
062

064

106

PAPERTAPE

173106

PAPERTAPE

173010

010

DL11-E

012

173010

DL11-E

173012

154

DUll

156

173154

DUll

173156

164

DUP11

166

173164

DUP11

173166

I
I

CONSOLE
EMULATOR

165362

165364

,
I
I
I
I

I
I

(
CPU DIAG
TESTS
1-5

CONSOLE
EMUt.ATOR

CPU DIAG
TESTS 1-5

CONSOLE
EMULATOR

USER POWER
UP ROUTINE

CPU DIAG
TESTS 1-5

USER POWER
UP ROUTINE

START

CPU DIAG
TESTS 1-5

CPU DIAG
TESTS-6,7

MEMORY
SIZING

EXTENDED
CPU DIAG
TESTS 6,7

MEMORY
DIAG TESTS

MEMORY
SIZING

BOOT THE DEVICE
SELECTED IN
THE OFFSET
SWITCHES

MEMORY
DIAG
TESTS

BOOT THE
DEVICE
SELECTED
ONKBD

START

CONSOLE
eMl)LATOR

CONSOLE
EMULATOR

EXTENDED
CPU DIAG
TESTS 6,7

BOOT THE DEVICE
SELECTED IN
THE OFFSET
SWITCHES

MEMORY
SIZING

BOOT THE DEVICE
SELECTED IN THE
SWITCH REGISTER

MEMORY
DIAG
TESTS

BOOT THE
DEVICE
SELECTED
ON KBD

BOOT THE DEVICE
SELECTED IN THE
SWITCH REGISTER
11-5219

Figure 11-4 M9301-YE
Operator's Flowchart

11-11

Test I tests the destination register in its three possible states: zero, negative, and positive. Each
instruction operates on the register contents in one of four ways:
I.

I)ata will be changed via a direct operation, i.e., increment, clear, decrement, etc.

Data will be changed via an indirect operation, i.e., arithmetic shifts, add carry, and subtract
c:arry.

Data will be unchanged, but operated upon via a direct operation, i.e., clear a register
already containing zeros.

I)ata will be unchanged but examined via a non-modifying instruction (TEST).
NOTE
When operating upon data in an indirect manner, the
data is modified by the state of the appropriate condition code. Arithmetic shift will move the C bit into
or out of the destination. This operation, when performed correctly, implies that the C bit was set correctly by the previous instruction. There are no
checks on the data integJrity prior to the end of the
test. However, a check is made on the end result of
the data manipulation. A correct result implies that
all instructions manipulated the data in the correct
way. If the data is incorrect, the program will hang in
a program loop until the machine is halted.

TEST 2 - DOUBLE OPERAND, ALL SOURCE MODES
This test v<::rifies all double operand, general, and logical instructions, each in one of the seven addressing modes (excludes mode 0). Thus, two operations are checked: the correct decoding of each double
operand instruction, and the correct operation of each addressing mode for the source operand.
Each instruction in the test must operate correctlly in order for the next instruction to operate. This
interdependence is carried through to the last instruction (bit test) where, only through the correct
execution of all previous instructions, a data field is examined for a specific bit configuration. Thus,
each instruction prior to the last serves to set up the pointer to the test data.
Two checks on instruction operation are made in test 2. One check, a branch on condition, is made
following the compare instruction, while the second is made as the last instruction in the test sequence.
Since the GO-NO GO tests reside in ROM menlory, all data manipulation (modification) must be
performed in destination mode 0 (register contains data). The data and addressing constants used by
test 2 are c:ontained within the ROM.
It is important to note that two different types of operations must execute correctly in order for this
test to operate:

Those instructions that participate in computing the final address of the data mask for the
final bit test instruction.

Those instructions that manipulate the test data within the register to generate the expected
bit pattern.

Detection iQf an error within this test results in a program loop.
11-13

TEST 3 - JUMP TEST MODES 1, 2, 3
The purpose of this test is to ensure correct operation of the jump instruction. This test is constructed
so that only a jump to the expected instruction will provide the correct pointer for the next instruction.
There are two possible failure modes that can occur in this test:
l.

The jump addressing circuitry will malfunction, causing a transfer of executioltl to an
incorrect instruction sequence or non-existent memory.

The jump addressing circuitry will malfunction in such a way as to cause the CPU to loop.

The latter case is a logical error indicator. The former, however, may manifest itself as an after-the-fact
error. For example, if the jump causes control to be given to other routines within the M9301, the
interdependent instruction sequences would probably cause a failure to eventually occur. In any case,
the failing of the jump instruction will eventually cause an out of sequence or illogical event to occur.
This in itself is a meaningful indicator of a malfunctioning CPU.
This test contains a jump mode 2 instruction which is not compatible across the PDP-II linl:. However, it will operate on any PDP-II within this test, due to the unique programming of the instruction
within test 3. Before illustrating the operation, it is important to understand the differences of tllle jump
mode 2 between machines.
On the PDP-II /20, 11/05, 11/15, and 11/10 processors for the jump mode 2 [JMP(R}+] the register
(R) is incremented by 2 prior to execution ofthejump. On the PDP-l1/04, 11/34, 11/35, 11/40,11/45,
11/50, 11/55, and 11/70 processors, (R) is used as the jump address and incremented by 2 after
execution of the jump.
In order to avoid this incompatability, the JMP (R)+ is programmed with (R) pointing back on the
jump itself. On 11/20, 11/05, 11/10, and 11/15 processors, execution of the instruction would cause
(R) to be incremented to point to the following instruction, effectively continuing a normal execution
sequence.
On the PDP-II /04, 11 /34, 11/35, 11/40, 11/45, 11 /50, 11/55, and 11 /70 processors, the uSle of the
initial value of (R) will cause the jump to loop back on itself. However, correct operation of the
autoincrement will move (R) to point to the next instruction following the initial jump. The jump will
then be executed again. However, the destination address will be the next instruction in sequence.
TEST 4 - SINGLE OPERAND, NON-MODIFYING BYTE TEST
This test focuses on one unique single operand instruction, the TST. TST is a special case in the CPU
execution flow since it,is a non-modifying operation. Test 4 also tests the byte operation of this instruction. The TSTB instruction will be executed in mode 1 (register deferred) and mode 2 (register
deferred, auto increment).
The TSTB is programmed to operate on data which has a negative value most significant byte and a
zero (not negative) least significant byte.
In order for this test to operate properly, the TSTB on the low byte must first be able to access the even
addressed byte and then set the proper condition codes. The TSTB is then reexecuted with the
autoincrement facility. After the autoincrement, the addressing register should be pointing to the high
byte of the test data. Another TSTB is executed on what should be the high byte. The N bit of the
condition codes should be set by this operation.

11-14

Correct execution of the last TSTB implies that the autoincrement feature recognized that a byte
operation was requested, thereby only incrementing the address in the register by one, rather than two.
If the corrl~ct condition code has not been set by the associated TSTB instruction, the program will
loop.
TEST 5 - DOUBLE OPERAND, NON-MODIFYING TEST
Two non-nl1odifying, double-operand instructions - the compare (CMP) and bit test (BIT) - operate
on test data in source modes 1 and 4, and destination modes 2 and 4.
The BIT and CMP instructions will operate on data consisting of all ones (177777). Two separate fields
of ones are: used in order to utilize the compare instructions, and to provide a field large enough to
handle the autoincrementing of the addressing register.
Since the compare instruction is executed on two fields containing the same data, the expected result is
true Z bit, indicating equality.
The BIT instruction will use a mask argument of an ones against another field of all ones. The expected
result is a non-zero condition (Z).
Most failures will result in a one instruction loop.
At the end of test 5 the register display is enabled, provided the console emulator routine has been
selected in the microswitches. The register display routine prints out the octal contents of the CPU
registers RO, R4, SP and old PC on the console terminal. This sequence will be followed by a prompt
character ($) on the next line.
An example of a typical printout follows.

XXXXXX

xxxxxx

R6
(Stack
Pointer)

R5
(Old PC)

Prompt
Character
NOTES:
1.

Where X signifies an octal number (0-7).

Whenever there is a power-up routine or the boot switch is released on PDP-I 1/04 and
PDP-I 1/34 machines, the PC at this tinle will be stored in R5. The contents of R5 are then
printed as the old PC shown in the exaimple.

The prompting character string indicates that primary diagnostics have been run and the
processor is operating.

11.10.2 S4~condary CPU and Memory Tests
The secondary CPU tests modify memory and involve the use of the stack pointer. The JMP and JSR
instructions and all destination modes are tested. If a failure is detected, these tests, unlike the primary
tests, will execute a halt.
Secondary CPU and memory diagnostics are run i:mmediately after test 5 when they have been evoked
by means other than the console emulator, provided that the correct microswitches have been set. If
the console: emulator has been entered at the corrlpletion of test 5, the secondary CPU and memory
diagnostics will be run when the appropriate boot command is given.
11-15

Note that the user can execute the secondary CPU and memory diagnostics without running a bootstrap program. A false boot command (a non-existent device code or unit number followed by a
carriage return) will cause execution of tests 6, 7, and 8 before the attempt to boot is made. If these
tests are executed successfully, the device will be called but not found. The processor will trap to
location 4, which has been set up by the M930l- YEo A new PC is obtained at location causing a halt to
be executed at location O.
TEST 6 - DOUBLE OPERAND, MODIFYING BYTE TEST
The objective of this test is to verify that the double-operand, modifying instructions will operatc~ in the
byte mode. Test 6 contains three subtests:
1.

2.
3.

Test source mode 2, destination mode 1, odd and even bytes
Test source mode 3, destination mode 2
Test source mode 0, destination mode 3, even byte.

The move byte (M OVB), bit clear byte (BICB), and bit set byte (BISB) are used within test 6 to verify
the operation of the modifying double-operand functions.
Since modifying instructions are under test, memory must be used as a destination for the test data.
Test 6 uses location 500 as a destination address. Later, in test 7 and the memory test, location 500 is
used as the first available storage for the stack.
Note that since test 6 is a byte test, location 500 implies that both 500 and 501 are used for the byte
tests (even and odd, respectively). Thus, in the word of data at 500, odd and even bytes are caused to be
all Os and then alII s alternately throughout the test. Each byte is modified independently of the other.
TEST 7 - JSR TEST
The JSR is the first test in the GO-NO GO sequence that utilizes the stack. The jump subroutine
command (JSR) is executed in modes 1 and 6. After the JSR is executed, the subroutine which was
given control will examine the stack to ensure that the correct data was placed in the correct stack
location (500). The routine will also ensure that the line back register points to the correct address. Any
errors detected in this test will result in a halt.
T"E:ST 8 - DUAL ADDRESSING AND DATA CHECK
Finally the memory test performs both dual addressing and a data check of all the available memory
on the system below 28K. This test will leave all of memory clear. Like the secondary tests the lnemory
test will halt when an error is detected. At the time the memory error halt is executed, RO will c:ontain
the address at which the failure was detected. R4 will contain the failing data pattern and R6 will
contain the expected data pattern. Thus after a memory failure has occurred, the user can enter the
console emulator and have this information printed out immediately by the display routine (see section
on console emulator).
11.11 TROUBLESHOOTING
When a halt occurs, the user should reboot the system by pressing the BOOT /INIT switc:h. The
registers RO, R4, R6, and R5 will be displayed on the terminal in that order.
RO
R4
R6
R5

Failing address
Failing data
Expected data
Old PC

The diagnostic program in the M930 1- YE will cause the processor to halt at one of four addresses:
165604, 165620, 165634, or 165774 in the event of a failure. The user should consult the diagnostic
program listing to find the failing test and begin troubleshooting. Possible causes of the failure include
bus errors, a bad M9301 module, and a bad CPU.
11-16

11.12 FI,OATING DEVICE PRIORITY
The M9301-YE assumes the following priority of devices in the floating address space.

1.
2.
3.
4.
5.

OJll
OHll
OQll
DUll
OUPll

The M930 1-YE will not function properly unless the above priority and correct Unibus address spacing is followed.

11-17

CHAPTER 12
M9301-YF

12.1 INTRODUCTION
The M9301-YF is designed to function in PDP-ll systems. It provides bootstrapping capabilities for
all major PDP-II devices and includes routines for console emulation and some basic CPU and memory GO-NO GO diagnostic tests.
This bootstrap module has been designed for maximum flexibility of operation. Its function may be
initiated in any of four ways: automatically at power up (exception 11/45, 11/50); by depressing the
console boot switch; by a LOAD ADDRESS and START sequence; and by using the console emulator through a terminal.
The M9301-YF is essentially a combination of the ~\19301-YA and the M9301-YB. The M9301-YF can
boot from the console switch register, but only unit number O. Figure 12-1 is a memory map for the
M9301-YF. Note that the TAll is not supported"
773777

BOOTSTRAP PROGRAMS

773000

766777

CONSOLE EMULATOR
DIAGNOSTICS

766000
11-4871

Figure 12-1

M9301-YF Memory Map

The lower addresses, 765000-765777, can be disabled by putting switch SI-1 in the OFF position. This
would free addresses 765000-765777, allowing the: user to occupy this address space.
Note that if switch SI-1 is OFF, the console emulator and diagnostics are no longer available. Also,
the DLll and PCll cannot be booted if SI-1 is OFF.
12-1

12.2 OPERATION OF THE M9301-YF
The user can boot a program from any of II peripheral devices by calling the bootstrap program for
that peripheral through the console emulator. The first routines to be executed (if 000 is the conhmts of
the microswitches) are the primary CPU diagnostics.
The display routine is entered automatically. This routine will type the contents of RO, R4, R6, a.nd R5
(note the sequence) on the Teletype or terminal in octal. Pressing the console boot switch causes the
PDP-I 1/04 and PDP-II /34 systems to copy the PC into R5 before the power-up sequence star1ts. The
console emulator (keyboard dispatch) program is then entered automatically. This routine types a
carriage return, a line feed and then the prompt symbol, $. The user can call bootstrap programs at this
point by typing the appropriate device code. He then types an octal number following the device code
specifying the drive number (default 0) and hits the carriage return key. Table 12-1 lists the peripheral
bootstrap programs supported by the M9301-YF.
Table 12-1

M9301-YF Bootstrap Programs

Device

Description

DLll
PC 11
RKII
RK611
RPII
RXII
TCll
TMII

Low-Speed Paper Tape TT
High-Speed Paper Tape PR
RK03/05 Disk Drive
DK
RK06 Disk Drive
DM
RP02/RP03 Disk Drive DP
RXOI Floppy Disk Drive DX
DECtape
DT
TUIO 800 bpi Magtape MT

Command

Massbus Devices·
(RH II, RH70)
RS03/RS04
RP04 /RP05 / RP06
TUl6

Fixed Head Disk
Disk Pack Drive
Magnetic Tape

DS
DB
MM

*Different devices on same Massbus controller are not supported.

An explanation of the functions performed by the various bootstrap programs follows.
RXII Diskette Bootstrap - Loads the first 64 words (2008 bytes) of data from track one, sector one
into memory locations 0-176 beginning at location O.
PCII Paper Tape Reader Bootstrap - Loads an absolute loader formatted tape into the upper memory
locations XXX746 to XXX777 (XXX is dependent on memory size). Once loading is completed, the
boot transfers operation to a routine beginning at location XXX752.
Disk and DECtape Bootstraps (excluding RXII) - Load 10008 words (20008 bytes) of data from the
device into memory locations 0-17768.

12-2

Magtape Bootstraps
TM 11 - Loads second record (2000 8 bytes maximum size) from the magtape into memory location 0-,17768 •
TJU16 - Loads second record (2000 8 bytes maximum size) from magtape into memory locations
0-17768 • (Note that the first record contains 1the magtape directory.)

12.3 MICROSWITCH SETTINGS
A set often microswitches is located on the M9301 module. They determine which ROM routines are
selected and give the user automatic access to any function.
The primary activating processes for the M9301-YF are the power-up sequence and the enabling of the
console boot switch. Switch SI-1 must be in the ON position in order to enable activation of the
M9301-YF console emulator and diagnostics. Switch S 1-2 is the power-up reboot enable switch. It
must be ON to enable to M9301-YF on power up. If switch S 1-2 is OFF, then the processor will trap to
location 24 (as normal) to execute the user power-up routine. When switch S 1-2 is ON, the other
switches, S 1-3 through S 1-10, determine what action the M9301-YF will take on power-up.

If the system includes a console boot switch, then an.y time that switch is pressed the M9301-YF will be
activated. N'ote that some processors will have to be halted for this switch to have any effect. Enabling
the console boot switch causes the processor to enter a ROM routine by creating a fake powerdown/power-up sequence. The user should note that the position of switch SI-2 is irrelevant when the
console boot switch is used.
Pushing the: console boot switch thus results in a. power-up sequence in the processor through an
M9301-YF ROM routine. Prior to the power-up sequence, the M9301-YF asserts 773000 on the
Unibus address lines. This causes the new PC to be taken from ROM location 773024 instead of
location 000024. The new PC will be the logical OR of the contents of ROM location 773024 and the
eight microswitches on the M9301-YF module. A switch in the ON position is read as a 0, while a
switch in the OFF position is a 1. In this way all the M9301-YF options are accessible.
Each option is given a different address. Note thatmicroswitch SI-10 is ORed with bit 1 of the data in
ROM locatiion 773024. S 1-9 is ORed with bit 2~ etc. No switch is provided for combination with bit 0,
because an odd address could result when going through the trap sequence. Figure 12-2 shows the
relationship of the switches to the bus address: bits.

LOW ROM ENABLE

POWER UP FIEBOOT ENABLE

I •1+
2

CORRESPONDING
BUS ADDRESS BITS
BINARY VALUE
OF SWITCHES

S1 SWITCHES

OCTAL VALUES
OF SWITCHES

Y
ON = 0
OFF = 1

Figure 12-2

11-4865

Program Flowchart for the M9301-YF

12·,]

12.4 PROGRAM CONTROL THROUGH THE MICROSWITCHES
The microswitches on the M9301-YF enable the user either to start a bootstrap operation or to enter
the console emulator, simply by pressing the boot switch. Note that a momentary power failure will
have the same effect as pushing the boot switch. The user should also note that he can select any
function without diagnostics by adding 2 to the appropriate octal code in the switches.
Figure 12-3 is a flowchart showing three of the four modes available to the M9301-YF user. In these
three modes (normal mode, user power-up mode, and automatic boot mode), the choice and sequence
of routines is entirely dependent on the offset switch settings.
Table 12-2 is a list of microswitch settings and corresponding octal codes which can be directly related
to the flowchart in Figure 12-3.

Table 12-2

Options and Corresponding Switch Settings

Function

S10

Octal
Code

CPU Diagnostics with
Console Emulator*

000

Console Emulator
(without diag.)*

OFF

002

CPU diag. Vector
through location 24
User power
fail routine*

OFF

644

Vector through location
24 (without diag.)
User power
fail routine*

OFF

646

OFF

040

OFF

042

CPU Diag. Boot RJP04/05/06* ON
Boot RJP04/05j06
(without diag.)
ON

OFF

224

OFF

226

CPU Diag. Boot RJS03/04*
Boot RJS03/04
(without diag.)

OFF

440

OFF

442

CPU Diag. Boot RPll *
Boot RPll
(without diag.)

12-4

Table 12-2 Options and CorrE~sponding Switch Settings (Cont)
Function

SAo.)

S10

Octal
Code

CPU Diag. Boot RKII *
Boot RKII (without diag.)

ON
ON

OFF
OFF

ON
ON

OFF
OFF

ON
OFF

144
146

CPU Diag. Boot RK611 *
Boot RK611 (without diag.)

OFF
OFF

Ol~

0]'1

OFF
OFF

ON
ON

ON
OFF

OFF
ON

662
664

CPU Diag. Boot RX 11 *
Boot RXII (without diag.)

OFF
OFF

ON
ON

OFF
OFF

ON
ON

OFF
OFF

ON
OFF

544
546

CPU Drag. Boot TCII *
Boot TCll (without diag.)

ON
ON

OFF
OFF

ON
OFF

174
176

CPU Diag. Boot TM 11 *
Boot TM 11 (without diag.)

OFF
OFF

ON
ON

• 01~
01'l

OFF
OFF

ON
OFF

474
476

CPU Diag. Boot TJU 16*
Boot TJU 16 (without diag.)

ON
ON

01~
01~

OFF
OFF

ON
ON

OFF
OFF

ON
OFF

054
056

CPU Diag. Boot DLII *
Boot DL 11 (without diag.)

ON
ON

OFF
OFF

ON
ON

OFF
OFF

ON
OFF

364
366

CPU Diag. Boot PCll *
Boot PC II (without diag.)

OFF
OFF

ON
ON

OFF
OFF

ON
OFF

704
706

*SI-1 must bl;! on.
ll. To boot on power up, S 1-2 must be on.
2. If the boot switch is used, the position of S 1-2 is irrelevant.

Note: ON = 0, OFF = 1

1.2.5 LOAD ADDRESS AND START MODE
The user who wishes to initiate a function other than the one which he has specified in the microswitches can do so without resetting those microswitches. This involves a load address, placing an
option code itn the switch register, and a start procedure. It can be done only on machines with console
switch registc!rs. Figure 12-4 is a program flowchart. Table 12-3 lists the switch register codes in tabular
format. The user must load address 173016, and then, before pressing the START switch, he must
place a device code or option code in the switch register.

12-5

OFFSET
SWITCH
SETTING

AUTOMATIC BOOT
MODE

USER POWER
UPMODE

NORMAL MODE

I
I
I

I
I
000
I

I
I
002
I

I
I

844

040RP11
- 042
224 - RJP04/05/06 - 226
440RJS03/04
- 442
144RK11
- 148
662RK611
- 664
- 546
544RX11
- 176
174TC11
- 476
TM11
474 - 056
054TJU16
- 366
DL11
364 - 706
PC11
704 -

848

\ Po;0"7 \ PO;:" ,7

CPU
DIAGNOSTIC
TESTS 1·5

r
CPU
DIAGNOSTIC
TESTS 1·6

CPU
DIAGNOSTIC
TESTS 1·6

EXTENDED
CPU
DIAGNOSTIC
TESTS 8.7

!
USER
POWER
UP

EXTENDED
CPU
DIAGNOSTIC
TESTS 8.7

USER
POWER UP
ROUTINE

MEMORY
SIZING

MEMOrlY
SIZING

MEMORY
DIAGNOSTIC
TEST 8

BOOTTHE
DEVICE
SELECTED IN
KEYBOARD
DISPATCH

MEMORY
DIAGNOSTIC
TEST8

BOOTTHE
DEVICE
SELECTED IN
KEYBOARD
DISPATCH

BOOTTHE
DEVICE
SELECTED
IN THE OFFSET
SWITCHES

BOOTTHltJ:
DEVICE
SELECTEI)
IN THE OIFFSET
SWITCHE.S
11·4862

Figure 12-3

M9301-YF Flowchart

12-6

Table 12-3

Load Address and Start

Load Address

Result

165404**
165406**

To enter console emulator after running diagnostics
To enter console emulator without running diagnostics

1173040*
1173042

To boot the RPll with diagnostics
To boot the RPll without diagnostics

1173224*
1173226

To boot the RJP04, RJP05, or RJP06 with diagnostics
To boot the RJP04, RJP05, or RJP06 without diagnostics

1173440*
][73442

To boot the RJS03 or RJS04 with diagnostics
To boot the RJS03 or RJSI04 without diagnostics

1173144*
1173146

_To boot the RK 11 with diagnostics
To boot the RKll without diagnostics

173662*
173664*

To boot the RK611 with diagnostics
To boot the RK611 without diagnostics

]73544*
173546

To boot the RXll with diagnostics
To boot the RXll without diagnostics

173174*
173176

To boot the TCll with diagnostics
To boot the TCll without diagnostics

]73474*
173476

To boot the TM 11 with diagnostics
To boot the TM 11 without diagnostics

]73054*
]73056*

To boot the TJU 16 with diagnostics
To boot the TJU 16 withou.t diagnostics

173364*
173366*

To boot the DLll paper tape with diagnostics
To boot the DLll without diagnostics

]73704*
173706*

To boot the PCll paper tape with diagnostics
To boot the PC 11 without diagnostics

*SI-1 must b~~ ON.
**If the switches on the M9301-YF are set up to default boot the console emulator, the state of switch SI-10 will
determine whether or not diagnostics are run. SI-10 must be on if diagnostics are to be run. SI-1 must also be
ON.

12-7

LOAD ADDRESS AND START MODE
LOAD ADDRESS 173016
SET SWITCH REGISTER TO
ONE OF THE VALUES LISTED
BELOW TO SELECT THE
FUNCTION DESIRED.
165404
173040
173224
173440
173662
173544
173174
173474
173054
173364
173704
173144

CONSOLE EMULATOR
RP11
RJP04/05/06
RJS03/04
RK611
RXll
TCll
TMll
TJU16
DLll
PCll
RK11

165406
173042
173226
173142
173664
173546
173176
173476
173056
173366
173076
173146

CPU
DIAGNOSTIC
TESTS 1-5

EXTENDED
CPU
DIAGNOSTIC
TESTS 6, 7

MEMORY
SIZING

MEMORY
DIAGNOSTIC
TEST 8

BOOT THE
SELECTED
DEVICE

11-4987

Figure 12-4

M9301-YF Load Address and Start Mode Flowchart

12-8

12.6 DIAC:NOSTICS
An explanation of the eight CPU and memory diagnostic tests follows. Three types of tests are included in the M9301-YF diagnostics:
1.
2.
3.

Primary CPU tests (1-5)
Secondary CPU tests (6, 7)
Memory test (8)

12.6.1 Primary CPU Tests
The primary CPU tests exercise all unary and double operand instructions with all source modes.
These tests do not modify memory. If a failure, is detected, a branch-self (BR.) will be executed. The
run light will stay on, because the processor will hang in a loop, but there will be no register display.
The user must use the halt switch to exit from the loop. If no failure is detected in tests 1-5, the
processor will emerge from the last test and enter the register display routine (console emulator).

TEST 1 - SINGLE OPERAND TEST
This test exe:cutes all single operand instructions using destination mode O. The basic objective is to
verify that all single operand instructions operate; it also provides a cursory check on the operation of
each instruction, while ensuring that the CPU decodes each instruction in the correct manner.
Test 1 tests the destination register in its three possible states: zero, negative, and positive. Each
instruction operates on the register contents in one of four ways:
1.

Data will be changed via a direct operation, i.e., increment, clear, decrement, etc.

Data will be changed via an indirect operation, i.e., arithmetic shifts, add carry, and subtract
carry.

Data will be unchanged, but operated upon via a direct operation, i.e., clear a register
already containing zeros.

Data will be unchanged but examined via a non-modifying instruction (TEST).

NOTE
When operating upon data in an indirect manner, the
data is modified by the 'state of the appropriate condition code. Arithmetic shift will move the C bit into
or out of the destination. This operation, when performed correctly, implies that the C bit was set correctly by the previous instruction. There are no
checks on the data integrity prior to the end of the
test. However, a check, is made on the end result of
the data manipulation. A correct result implies that
all instructions manipulated the data in the correct
way. If the data is incorrect, the program will hang in
a program loop until the machine is halted.

TEST 2 - DOUBLE OPERAND, ALL SOURCE l\10DES
This test verifies all double operand, general, and logical instructions, each in one of the seven addressing modes (excludes mode 0). Thus, two operations are checked: the correct decoding of each double
operand instruction, and the correct operation of each addressing mode for the source operand.

12-9

Each instruction in the test must operate correctly in order for the next instruction to operate. This
interdependence is carried through to the last instruction (bit test) where, only through the correct
execution of aU previous instructions, a data field is examined for a specific bit configuration. Thus,
each instruction prior to the last serves to set up the pointer to the test data.
Two checks on instruction operation are made in test 2. One check, a branch on condition, is made
following the compare instruction, while the second is made as the last instruction in the test sequence.
Since the GO-NO GO tests reside in ROM memory, all data manipulation (modification) 1nust be
performed in destination mode 0 (register contains data). The data and addressing constants used by
test 2 are contained within the ROM.
It is important to note that two different types of operations must execute correctly in order for this
test to operate:

Those instructions that participate in computing the final address of the data mask for the
final bit test instruction.

Those instructions that manipulate the test data within the register to generate the e:xpected
bit pattern.

Detection of an error within this test results in a program loop.

TEST 3 - JUMP TEST MODES 1, 2, AND 3
The purpose of this test is to ensure correct operation of the jump instruction. This test is constructed
so that only a jump to the expected instruction will provide the correct pointer for the next instruction.
There are two possible failure modes that can occur in this test:
1.

The jump addressing circuitry will malfunction causing a transfer of execution to an
incorrect instruction sequence or non-existent memory.

The jump addressing circuitry will malfunction in such a way as to cause the CPU to loop.

On the PDP-ll/04, 11/34, 11/35, 11/40, 11/45, 11/50, 11/55, and 11/70 processors, the use of the
initial valule of (R) will cause the jump to loop back on itself. However, correct operation of the
autoincrement will move (R) to point to the next instruction following the initial jump. The jump will
then be executed again. However, the destination address will be the next instruction in sequence.
TEST 4 - SINGLE OPERAND, NON·MODIFYING BYTE TEST
This test fOicuses on the one single operand instruction, the TST. TST is a special case in the CPU
execution flow since it is a non-modifying operatioll1. Test 4 also tests the byte operation of this instruction. The TSTB instruction will be executed in mode 1 (register deferred) and mode 2 (register
deferred, autoincrement).
The TSTB is programmed to operate on data whkh has a negative value most significant byte and a
zero (not nc!gative) least significant byte.
In order for this test to operate properly, the TSTB on the low byte must first be able to access the even
addressed byte and then set the proper condition codes. The TSTB is then reexecuted with the
autoincrement facility. After the autoincrement, the addressing register should be pointing to the high
byte of the test data. Another TSTB is exec.uted on what should be the high byte. The N bit of the
condition codes should be set by this operation.
Correct execution of the last TSTB implies that the autoincrement recognized that a byte operation
was requested, thereby only incrementing the address in the register by one, rather than two. If the
correct condition code has not been set by the associated TSTB instruction, the program will loop.
TEST 5 - DOUBLE·OPERAND, NON·MODIFYING TEST
Two non-modifying, double-operand instructions are used in this test - the compare (CMP) and bit
test (BIT). These two instructions operate on test data in source modes 1 and 4, and destination modes
2 and 4.
The BIT and CMP instructions will operate on data consisting of all ones (177777). Two separate fields
of ones are used in order to utilize the compare instructions, and to provide a field large enough to
handle the autoincrementing of the addressing register.
Since the compare instruction is executed on two fidds containing the same data, the expected result is
a true Z bit, indicating equality.
The BIT instruction will use a mask argument of all ones against another field of all ones. The expected
result is a non-zero condition (Z).
Most failun,s will result in a one instruction loop.
At the end of test 5, the register display routine is enabled, provided the console emulator has been
selected in the microswitches, is enabled. The register display routine prints out the octal contents of
the CPU registers RO, R4, SP, and old PC on the console terminal. This sequence will be followed by a
prompt character ($) on the next line.

12-11

An example of a typical printout follows.

XXX XXX

XXXXXX

XXX xxx

R6
(Stack
Pointer)

(Old PC)

Prompt
Character

NOTES:
1.

Where X signifies an octal number (0-7).

Whenever there is a power-up routine or the boot switch is released on PDP-ll/04 and
PDP-I 1/34 machines, the PC at this time will be stored in R5. The contents of R5 are then
printed as the old PC shown in the example.

The prompting character string indicates that diagnostics have been run and the processor is
operating.

12.6.2 Secondary CPU and Memory Tests
The secondary CPU tests modify memory and involve the use of the stack pointer. The JMP and JSR
instructions and all destination modes are tested. If a failure is detected, these tests, unlike the primary
tests, will execute a halt.
Secondary CPU and memory diagnostics are run immediately after test 5 when they have been evoked
by means other than the console emulator, provided that the correct microswitches have be<m set. If
the console emulator has been entered at the completion of test 5, the secondary CPU and memory
diagnostics will be run when the appropriate boot command is given.

In contrast to the M930I-YA and M930I-YB, the M930I-YF reacts to a false boot comrrland (an
invalid address code) by trapping to location 4 with the end result being a halt if diagnostics are
selected. This halt should not be interpreted as a diagnostic test failure.
TEST 6 - DOUBLE OPERAND, MODIFYING, BYTE TEST
The objective of this test is to verify that the double-operand, modifying instructions will operate in the
byte mode. Test 6 contains three subtests:
1.
2.
3.

Test source mode 2, destination mode 1, odd and even bytes
Test source mode 3, destination mode 2
Test source mode 0, destination mode 3, even byte.

12-12

TEST 7 - ,JSR TEST
The JSR is the first test in the GO-NO GO sequence that utilizes the stack. The jump subroutine
command (JSR) is executed in modes 1 and 6. After the JSR is executed, the subroutine which was
given control will examine the stack to ensure that the correct data was placed in the correct stack
location (500). The routine will also ensure that the: line back register points to the correct address. Any
errors detelcted in this test will result in a halt.
TEST 8 - DUAL ADDRESSING AND DATA CHECK
Finally the memory test performs both dual addrc~ssing and a data check of all the available memory
on the systt~m below 28K. This test will leave all of memory clear. Like the secondary tests the memory
test will hah when an error is detected. At the timl~ the memory error halt is executed, R4 will contain
the address at which the failure was detected. RO will contain the failing data pattern and R6 will
contain the: expected data pattern. Thus after a nlemory failure has occurred, the user can enter the
console emulator and have this information printed out immediately by the display routine (see section
on console emulator).
12.7 TROUBLESHOOTING
When a halt occurs, the user should reboot .the system by pressing the BOOT /INIT switch. The
registers RO, R4, R6, and R5 will be displayed on the terminal in that order.
R4
RO
R6
R5

Expected data
Received data
Failing address (SP)
Old PC

The diagnostic program in the M9301-YF will ca.use the processor to halt at one of four addresses:
165646, 165662, 165676, or 165776. The user shoulld consult the diagnostic program listing to find the
failing test and begin troubleshooting. Possible causes of the failure include bus errors, a bad M9301
module, and a bad CPU.
12.8 RESTARTING AT THE USER POWER I~AIL ROUTINE
If the user wishes to restart software on a power-up, he may do so by merely disabling the power fail
restart switch in the microswitches (turn switch SI-2 OFF). However, the user can use the M9301-YF
to run diagnostics (the primary CPU tests just described) before running his power-up routine. This
will in no way disturb the contents of memory and will in fact verify the machine's basic integrity after
the power-down and -up sequence. In order to use this option, put the code 644 into the microswitches
as described previously. Switch S 1-9 must be OFF. This will result in the running of the primary CPU
diagnostics and then a simulated trap through 24 which will start the user's specified power-up routine.
If the code 646 is placed in the microswitches, then the simulated trap through 24 is executed without
running any diagnostics.

12-13

CHAPTER 13
M9301-YH

13.1 INTRODUCTION
The M9301-YH has been created to provide bootstrapping capabilities for the PDP-ll/60 and PDP11/70 computers. It also provides basic diagnosti(~ tests for the CPU, memory, and cache.
The M9301-YH provides flexibility of operation via user-settable microswitch options. Its functions
can be initiated automatically on power-up, by pre:ssing the console boot switch (PDP-I 1/60), or by a
load-address start sequence.
NOTE
For the PDP-ll/60, juml)erS WI-W5 must be out.
(WI-W5 provide pun-ups. for bus grant lines.) For
the PDP-ll/70, jumpers '\\,I-W5 must be in.
13.2 MEl\10RY MAP
The four triistate ROMs which contain the program information use two distinct address spaces:
I.
2.

XXX65000-XXX65776
XXX73000-XXX73776

All the diagnostic tests reside in the first address space. All the bootstrap loaders reside in the second
address space (Figure 13-1).

XXX73776

BOOTSTRAP]
PROGRAMS
XXX73000

XXX65776

CACHETEST
MEMORY TEST
CPU TEST

XXX65000

11-5179

Figure 13-1

M9301-YH Program Memory Map

13--1

13.3 DIAGNOSTIC TEST EXPLANA nON
The diagnostic portion of the program will test the basic CPU including the branches, the registers, all
addressing modes, and many of the instructions in the PDP-II repertoire. It will check memory from
virtual address 1000 to the highest available address up to 28K. After main memory has been v,erified,
with the cache off, the cache memory will be tested to verify that hits occur properly. Main lttemory
will be scanned again to ensure that the cache is working properly throughout the 28K of menlory to
be used in the boot operation.
If one of the cache memory tests fails, the operator can attempt to boot the system anyway by pressing
continue. This will cause the program to force misses in both groups of the cache before going to the
bootstrap section of the program.

A list of the M9301-YH diagnostic tests follows.
TEST 1
TEST 2
TEST 3
TEST 4
TEST 5
TEST 6
TEST 7
TEST 10
TEST 11
TEST 12
TEST 13
TEST 14
TEST 15
TEST 16
TEST 17
TEST 20
TEST 21
TEST 22
TEST 23
TEST 24

This test verifies the unconditional branch
Test CLR, MODE 0, and BMI, BVS, BHI, BLOS
Test DEC, MODE 0, and BPL, BEQ, BOE, BOT, BLE
Test ROR, MODE 0, and BVC, BHIS, BHI, BNE
Test BHI, BLT, and BLOS
Test BLE and BOT
Test register data path and modes 2, 3, 6
Test ROL, BCC, BLT, and MODE 6
Test ADD, INC, COM, and BCS, BLE
Test ROR, BIS, ADD, and BLO, BOE
Test DEC and BLOS, BLT
Test COM, BIC, and BOT, BOE, BLE
Test ADC, CMP, BIT, and BNE, BGT, BEQ
Test MOVB, SOB, CLR, TST and BPL, BNE
Test ASR, ASL
Test ASH, and SWAB
TestJSR, RTS, RTI, and JMP
Test main memory from virtual 1000 to highest
available address up to 28K
Test cache data memory
Test memory 28K with cache on

13.4 DIAGNOSTIC TEST DESCRIPTIONS
TEST 1 - This test verifies the unconditional branch.
The registers and condition codes are all undefined when this test is entered and they should remain
that way upon completion of this test.
TEST 2 - Test CLR, MODE 0, and BMI, BVS, BHI, BLOS.
The registers and condition codes are all undefined when this test is entered. Upon completion of this
test the SP (R6) should be zero and only the Z flip-flop will be set.
TEST 3 - Test DEC, MODE 0, and BPL, BGE, BGT, BLE.
Upon entering this test the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are: RO = ?, Rl = ?, R2 = ?, R3 = ?, R4 = ?, R5 = ?, and SP = 000000.
Upon completion of this test the condition codes will be: N = 1, Z = 0, V = 0, and C = o.
The registers affected by the test are: SP = 177777.

13-2

TEST 4 - Test ROR, MODE 0, and BVC, BHIS, BHI, BNE.
Upon enh~ring this test the condition codes are: N = 1, Z = 0, V = 0, and C = O.
The registers are: RO = ?, Rl = ?, R2 = ?, R3 := ?, R4 = ?, R5 = ?, and SP = 177777.
Upon conlpletion of this test the condition Godes will be: N = 0, Z = 0, V = 1, and C = 1.
The registers affected by the test are: SP = 077777.
TEST 5 - Test BHI, BLT, and BLOS.
Upon entering this test the condition codes are: N' = 0, Z = 0, V = 1, and C = 1.
The registers are: RO = ?, Rl = ?, R2 = ?, R3 == ?, R4 = ?, R5 = ?, and SP = 077777.
Upon conlpletion of this test the condition codes will be: N = 1, Z = 1, V = 1, and C = 1.
The registers are unaffected by the test.
TEST 6 - Test BLE and BGT.
Upon entt~ring this test the condition codes are: N = 1, Z = 1, V = 1, and C = 1.
The regist,ers are: RO = ?, Rl = ?, R2 = ?, R3 == ?, R4 = ?, R5 = ?, and SP = 077777.
Upon cOITlpletion of this test the condition codes will be: N = 1, Z = 0, V = 1, and C = 1.
The regisilers are unaffected by the test.
TEST 7 - Test register data path and modes 2, 3!. 6.
When this test is entered the condition codes are:: N = 1, Z = 0, V = 1, and C = 1.
The regist1ers are: RO = ?, Rl = ?, R2 = ?, R3 == ?, R4 = ?, R5 = ?, and SP = 077777.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are left as follows: RO = 125252,R 1 = 000000, R2 = 125252, R3 = 125252, R4 = 125252,
R5 = 125252, SP = 125252, and MAPLOO = 125252.
TEST 10 -- Test ROL, BCC, BLT, and MODE 6.
When this test is entered the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registt~rs are: RO = 125252, R 1 = 000000, R2 = 125252, R3 = 125252, R4 = 125252, R5 = 125252,
SP = 125252, and MAPLOO = 125252.
Upon completion of this test the condition codes are: N = 0, Z = 0, V = 1, and C = 1.
The registc!rs are left unchanged except for MAP'Loo which should now equal 052524.
TEST 11 -- Test ADD, INC, COM, and BCS, BLE.
When this test is entered the condition codes, are: N = 0, Z = 0, V = 1, and C = 1.
The registe:rs are: RO = 125252, R 1 = 000000, R2= 125252, R3 = 125252, R4 = 125252, R5 = 125252,
SP = 125252, and MAPLoo = 052524.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registe:rs are left unchanged except for R3 whkh now equals 000000, and R 1 which is also 000000.
TEST 12 -- Test ROR, BIS, ADD, and BLO, BGE.
When this test is entered the condition codes, are: N = 0, Z = 1, V = 0, and C = O.
The registe:rs are: RO = 125252, Rl = 000000, R2 := 125252, R3 = 030000, R4 = 125252, R5 = 125252,
and SP = 125252.
Upon completion of this test the condition codes. are: N = 0, Z = 1, V = 0, and C = O.
The registe:rs are left unchanged except for R3 whkh should be modified back to 000000, and R4 which
should now equal 052525.
TEST 13 -. Test DEC and BLOS, BLT.
When this test is entered the condition codes: are: N = 0, Z = 1, V = 0, and C = O.
The registers are: RO = 125252, Rl = 000000, R2 := 125252, R3 = 000000, R4 = 052525, R5 = 125252,
and SP = 125252.
Upon completion of this test the condition codes are: N = 1, Z = 0, V = 0, and C = O.
The regist~~rs are left unchanged except for Rl which should now equal 177777.

13-3

TEST 14 - Test COM, BIC, and BGT, BLE.

When this test is entered the condition codes are: N = 1, Z = 0, V = 0, and C = o.
The registers are: RO = 125252, Rl = 177777, R2 = 125252, R3 = 000000, R4 = 052525, R5 = 125252,
.lnd SP = 125252.
Upon completion of this test the condititon codes are: N = 0, Z = 0, V = 1, and C = 1.
The registers are left unchanged except for RO which should now equal 052525, and Rl which should
now equal 052524.

TEST 15 - Test ADC, CMP, BIT, and BNE, BGT, BEQ.
When this test is entered the condition codes are: N = 0, Z = 0, V = 1, and C = 1.
The registers are: RO = 052525, R 1 = 052524, R2 = 125252, R3 = 000000, R4 = 052525, R5 = 125252,
and SP = 125252.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are now: RO = 052525, Rl = 000000, R2 = 125252, R3 = 000000, R4 = 052525, R5 =
052525, and SP = 125252.

TEST 16 - Test MOVB, SOB, CLR, TST and BPL, BNE.
When this test is entered the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are: RO = 052525, R 1 = 000000, R2 = 125252, R3 = 000000, R4 = 052525, R5 = 052525,
and SP = 125252.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 0, and C = o.
RO is decremented by an SOB instruction to 000000; Rl is cleared and then incremented around to
000000.

TEST 17 - Test ASR, ASL.

When this test is entered the condition codes are: N = 0, Z = 1, V = 0, and C = O.
The registers are: RO = 125252, Rl = 000000, R2 = 125252, R3 = 000000, R4 = 052525, R5 = 052525,
and SP = 125252.
Upon completion of this test the condition codes are: N = 0, Z = 0, V = 0, and C = O.
The registers are left unchanged except for RO which is now equal to 000000, R 1 which is now 000001,
and R2 which is now 000000.

TEST 20 - Test ASH, and SWAB.

When this test is entered the condition codes are: N = 0, Z = 0, V = 0, and C = o.
The registers are: RO = 000000, Rl = 000001, R2 = 000000, R3 = 000000, R4 = 052525, R5 = 052525,
and SP = 125252.
Upon completion of this test the condition codes are: N = 0, Z = 1, V = 0, and C = 1.
The registers are left unchanged except for R 1 which should now equal 000000.

TEST 21 - Test JSR, RTS, RTI, JMP.
This test first sets the stack pointer to "KDPAR7" (172376), and then verifies that JSR, RTS, RTI,
and JMP all work properly.
On entry to this test the stack pointer (SP) is initialized to 172376 and is left that way on exit.

TEST 22 - Test main memory from 1000 to highest available address up to 28K.
This test will test main memory with the cache disabled, from virtual address 001000 to the last address
(up to 28K). The memory is sized before testing begins. If the data does not compare properly, the test
will halt at either 165516 or 165536. If a parity error occurs, the test will halt at address 165750, with
PC + 2 on the stack.
In this test the registers are initialized as follows: RO = 001000, Rl = DATA READ, R2 = 001000, R3
= 177746 (cache control register), R5 = last memory address, SP = 000776.

13-4

The following two tests are cache memory tests. If either of them fails to run successfully it will come to
a halt in the M9301 ROM. If you desire to 'try to boot your system, or diagnostic anyway, you can
press continue and the program will force misses in both groups of the cache and go to the bootstrap
that has been selected.
TEST 23 - Test cache data memory.
This test will check the data memory in the cach~:; first group 0 and then group 1. On the PDP-II /60,
group 0 is the top 0.5K of cache and group 1 is the bottom 0.5K of cache. It loads 125252 into an
address, c:omplements it twice and reads the datal. It then checks that address to ensure the data was a
hit. The sequence is repeated on the same addr~~ss with 052525 as the data. All cache memory data
locations are tested in this way. If either group fails and the operator presses continue, the program
will try to boot with the cache disabled.
The registers are initialized as follows for this test RO = 001000 (address), RI = 000002 (count), R2 =
001000 (count), R3 = 177746 (CCR), R4 = 1252:52 (pattern), R5 = last memory address, SP = 000776
(flag of z(~ro pushed on stack).
TEST 24 - Test up to 28K of memory with cach~~ on.
This test checks memory from 001000 through ]l57776 to ensure that you can get hits all the way up
through main memory. It starts with group 1 enabled, then tests group 0, and finally checks memory
with both groups enabled. If anyone of thethrc~e passes fails, the test will halt. Then if the operator
presses continue, the program will try to boot with the cache disabled.
Upon entry the registers will be set up as follows: RO = 001000 (address), RI = 000003 (pass count),
R2 = 001000 (first address), R3 = 177746 (CCR), R5 = last memory address, and SP = 000776.
Upon completion of this test, main memory fronl address 001000 through 157776 will contain its own
address.
13.5 INSTALLATION
A flat-pa(;k on the M9301 containing 10 microswitches determines what actions the M9301 ROM
, program will take. The various microswitch options are provided to give the user a flexibility of
operation and an ability to use the module in a wide variety of system configurations. Following is a
description of the functions provided by the microswitches. Table 13-1 lists the function of each switch,
and more detailed explanations follow.
Table 13-1

Microswitch Functions

Switch

Function

S 1-10
SI-9
S 1-8

ON selects 11/60, OFF selects 11/70
ON selects diagnostics, OFF selects no diagnostics
OFF boot from dlevice selected in microswitches

SI-7
SI-6
S 1-5
SI-4
SI-3
SI-2
S I-I

~~boot]from

de:::

:::::: in console switch register
i

MSB
OFF selects all diagnostics
ON selects all diagnostics except 21-24
Power-up reboot enable for 11/70
Low ROM enable

13-5

Microswitch SI-10
This switch is used to select the processor type. If the M9301 is used on the PDP-ll/60 processor, the
switch should be ON. Ifit is a PDP.l1/70 processor, the switch should be OFF. OFF is indicated by a
1 (or light lit) when bit 01 at location 773024 (17773024 for 11/70) is read.
Microswitch SI-9
If this switch is OFF, then none of the diagnostic tests can be executed. If the switch is ON, them the
ROM program will enter the diagnostic test section. The execution of the memory modifying tests
(JSR, RTS, RTI, memory test, cache test) depends on the setting of microswitch SI-3 described later.
OFF is a 1 in bit 02 at location 773024.
Microswitch SI-8
If this switch is OFF, the ROM program will not check the console switch register, but will boot. from
the device specified in the microswitches <7:4>. If this switch is ON, the ROM program will chel~k the
console switch register and boot accordingly (Paragraph 13.5). This microswitch option has been
provided for installation environments which cannot assure the integrity of the console switch r~:gister
contents (on power-up). OFF is a 1 in bit 03 at location 773024.
Microswitch <SI-7:S1-4>
These four microswitches should be set up to the device code, to select the desired device to boot from ..
This device is usually referred to as the default device. Drive 0 of the default device will be used.
Paragraph 13.5 gives the various device codes. While setting up switches <7:4> for the device code, it
should be remembered that a microswitch in the ON position gives a O. In the OFF position it gives a
1. Switch 4 is the MSB, and switch 7 is the LSB.
Microswitch SI-3
If this switch is OFF, then the memory-modifying tests (tests 21, 22, 23, 24 described previously) will
be executed before booting. If the switch is ON, these tests will not be executed, thus saving the
previous core image. Microswitch 81-3 is sensed only if microswitch 81-9 is ON. OFF is a 1 for bit 08
at location 773024.
Microswitch SI-2
When used with a PDP-l1/60 processor switch, 81-2 should be OFF. (On the PDP-ll/60, ifthl~ boot
on power-up option is desired, the slide-switch on the console should be set in the boot position.)
On the PDP-l1/70, the boot on power-up option is available if the following conditions are nlet:
1.
2.

ECO 5 is installed
Jumper W6 is installed, in accordance with ECO 5.

If these conditions are satisfied, then the boot on power-up option can be selected by putting lnicroswitch SI-2 ON. If the conditions are not met, switch 81-2 should be OFF.

Microswitch SI-1
If switch SI-1 is OFF, the low ROM (addresses XXX65000-XXX65776) is disabled. The normal
position of switch 1 is ON, since the diagnostic portion of the program resides in the low ROM.

13.6 ST ARTING PROCEDURE
The bootstrap test program can be started in one of the following ways:
1.
2.
3.

Automatically on power-up
Pressing the boot switch on the console (only for PDP-l1/60)
Load address and start sequence from the console.

13-6

13.6.1

Power-Up Start

PDP-ll/60
On the PDP-ll/60, a 3-position slide-switch (BOOT/RUN/HALT) is provided on the console. If this
switch is in the boot position and power-up occurs, automatic booting will take place from the device
specified in the microswitches (Figure 13-2).
PDP-ll/70
If S 1-2 is ON, ECO 5 is installed, and jumper W··6 is installed, an automatic boot on power-up will
occur from the device specified in the microswitches or console switch register (Figure 13-3).
PDP-ll/60 and PDP-ll/70
On power-up boot, the default device specified in microswitches < S 1-7:S 1-4> will be used if:
1.
2.

Ivlicroswitch S 1-8 is 0 FF or
~1icroswitch S 1-8 is ON and the low byte of the console switch register is a zero. (On the
PDP-ll/60, the console switch register is cleared on power-up.)

Other microswitch options are specified Paragraph 13.4.

Boot Switch Mode
This mode is available only on the PDP-II /60. Automatic booting will take place if a power up occurs
when the slide-switch on the console is in the boot position.
13.6.2 Power-Up Boot Examples (11/60 only)
A.
SI-1
ON

TOI0·SI-2
OFF

Set the microswitches as follows:
SI-3
OFF

SI-4
ON

SI-5
ON

SI-6
ON

SI-7
OFF

SI-8*
ON

SI-9
ON

SI-10
ON

SI-9
OFF

SI-10
ON

On power-up, the system will execute all diagnostics and boot the TO 10.
B.
S 1-1
ON

RK05-S 1-2
OFF

Set the micros witches as follows:
SI-3
OFF

SI-4
ON

SI-5
ON

SI-6
OFF

SI-7
OFF

SI-8*
OFF

On power-up the system will boot drive 0 of the RK05 without executing diagnostics.

*Note that on the 11/60 the position of S 1-8 is irrelevant, because the console switch register is cleared automatically. But if 81-8 is OFF, the program will never look at the console switch register, even if a LOAD ADDRESS
and START is attempted. Also, the M9301-YH can default only to drive 0 of any device.

13-7

WRONG
PROCESSOR
SELECTED
ERROR
IN CACHE
DIAGNOSTIC

LOW ROM

YES

DISABLED

EXECUTE

All
DIAGNOSTICS

21-24

DEVICE
SELECTED IN
CONSOLE
SWITCH
REG

BOOT THE DEVICE
SELECTED IN THE
MICROSWITCHES

11-5178

Figure 13-2 M9301-YH
Used With PDP-l1/60
13-9

THROUGH LOC
24

PROCEsson
SELECTED
ERROR
IN CACHE
DIAGNOSTIC

EXECUTE
ALL
DIAGNOSTICS

EXCEPT
21-24

BOOT THE
DEVICE
SELECTED IN
CONSOLE
SWITCH
REG

800T THE DEVICE
SELECTED IN THE
MICROSWITCHES

11-5177

Figure 13-3

M9301-YH Used with PDP-ll/70

13.6.3 Load Address Start Mode
This mode allows the user to boot from any devic:e and unit number specified in the console switch
register.
On the PDP-ll/60, load address 773000. On the PDP-ll/70, load address 17773000. Then the switch
register should be loaded with the appropriate device code (Figures 13-2 and 13-3).

13-11

SW REG <6:3> contains the device code (0-12). SW REG <2:0> contains the drive unit number
(0-7). The device codes are as follows:

Use the device specified in microswitches <S 1-7:S 1-4>.
TMII/TUI0
Magnetic Tape
TCll/TU56
DECtape
RKII/RK05
Disk
RPII/RP03
Disk
RK611/RK06
Disk
RHll-RH70/TUI6
Magnetic Tape
RH ll-RH70/RP04
Disk
RHII-RH70jRS04
Fixed Head Disk
RXI1/RXOI
Floppy Disk
PCll
Paper Tape Reader

1
2
3
4
5
6
7
10
11
12

In order to use the LOAD ADDRESS and START sequence, microswitch SI-8 must be in the ON
position.
13.6.4
C.
S 1-1
ON

LOAD ADDRESS and START Examples (11/70 only)

RS04SI-2
ON

Set the microswitches as follows:
SI-3
ON

SI-4

SI-5

SI-6

SI-7

SI-8
ON

SI-9
ON

SI-10
01FF

Load address 17773000.
Load 1038 in the console switch register.
Start.
The system will boot from drive number 3 of the RS04 disk drive.
13.7

ERRORS

A list of error halts indexed by the address displayed is shown in Table 13-2.
If the bootstrap operation fails as a result of a hardware error in the peripheral device the program will
do a reset instruction and attempt to boot again.
13.8 OPERATOR ACTION AND ERROR RECOVERY
If the diagnostic portion of the ROM program detects an error, the processor will halt. The: address
displayed should be noted. Paragraph 13.6 contains a cross-reference of address displayed ve:rsus test
number and subsystem under test. For further details, refer to the listing for the ROM program.
Most of the errors described in Table 13-2 are hard failures, and there may be no recovery frolll them.
If the processor halts in one of the two cache tests, error recovery is possible. When continue is pressed,
the program will either attempt to finish the test (XXX65604 or XXX65720) or force misses in both
groups of the cache and attempt to boot with the cache fully disabled (XXX6514, XXX65732, or
XXX65752).

13-12

Table 13-2

Error Halts Indexed

Address Displayed

Test Number and Subsyst4~m Under Test

XXX65004
XXX65020
XXX65036
XXX65052
XXX65066
XXX65076
XXX65126
XXX65136
XXX65154.
XXX65172
XXX65202
XXX65210
XXX65224
XXX65246
XXX65256
XXX65300
XXX65334
XXX65352
XXX65376
XXX.65406
XXX65416
XXX65430
XXX65436
XXX65520
XXX65540

Test 1, Branch Test
Test 2, CLR and Conditional Branch Test
Test 3, DEC and Con,ditional Branch Test
Test 4, ROR and Conditional Branch Test
Test 5, Conditional Branc:h Test
Test 6, Conditional Branc:h Test
Test 7, Register Data Path Test
Test 10, Conditional Branch Test
Test 11, CPU Instruction Test
Test 12, CPU Instruction Test
Test 13, CPU Instruction Test
Test 14, CPU Instruction Test
Test 14, CPU Instruction Test
Test 15, CPU Instruction Test
Test 16, Branch Test
Test 16, CPU Instruction Test
Test 17, CPU Instruction Test
Test 20, CPU Instruction Test
Test 21, JSR Test
Test 21, JSR Test
Test21, RTS Test
Test21, RTI Test
Test 21, JMP Test
Test 22, Main Memory Data Compare Error
Test 22, Main Memory Data Compare Error no recovery possible from this
error
Test23, Cache Memory [~ata Compare Error
Test 23, Cache Memory 1'r0 Hit
(pressing continue here will cause boot attempt, forcing cache misses)
Test 24, Cache Memory :Data Compare Error
Test 24, Cache Memory l'r 0 Hit
(pressing continue here will cause boot attempt, forcing misses in the cache)
Test 22, 23, or 24, Cache Memory or Main Memory Parity Error. (Examine
memory error register 777744 to find out more.) If cache parity error, pressing continue here wilt cause boot attempt forcing misses in cache.

XXX65604
XXX65614
XXX65720
XXX65732
XXX65752

xxx = 001 for PDP-11/60
XXX = 177 for PDP-11/70

13-13

If the program fails in an uncontrolled manner, it might be due to an unexpected trap to location 4 or
10. If this is suspected, then load the following:

LOC

CONTENTS

4
6
10
12

6
0
10
0

The above will cause all traps to vectors 4 and 10 to halt the processor at addresses 6 and 12 respectively (with addresses 10 and 14 in the display); the operator can examine the CPU error register at
XXX77766 to get more error information. Bits in CPU error register are defined as follows:
Bit 02 = Red Zone Stack Limit
Bit 03 = Yellow Zone Stack Limit (11/70 only)
Bit 04 = Unibus Timeout
Bit 05 = Non-Existent Memory (Cache, 11/70 only)
Bit 06 = Odd Address Error
Bit 07 = Illegal Halt (11/70 only)

13-14

CHAPTER 14
M9301-YJ

14.1 INTRODUCTION
The M9301-YJ provides DECnet bootstrapping capabilities for the DMCll on PDP-II systems with
or without the console switch register. In addition, the M9301-YJ includes a console emulator routine,
bootstrap routines for floppy disk, magnetic tape, paper tape, and some basic CPU and memory GONO GO diagnostic tests.
This module has been designed for maximum flexibility of operation. Its function may be initiated in
any of four ways: automatically at power-up, by pressing the console boot switch, by a LOAD
ADDRESS and START sequence, or by using the console terminal while running the console emulator routine.
14.2 PROGRAM MEMORY MAP
Figure 14-1 is a program memory map for the M9301-YJ.
773777

BOOTSTRAP PROGRAMS

773000

CONSOLE EMu:JTOR 766777
DIAGNOSTICS
766000
11-4871

Figure 14-1

M9301-YJ Program Memory Map

14-1

The lower addresses (765000-765777) can be disabled by putting switch 81-1 in the 0 FF POSitiOltl. This
would free addresses 765000-765777, allowing the user to occupy this address space. Note that if
switch 81-1 is OFF, the console emulator, the low-speed paper tape boot, and diagnostics are no
longer available.
Note also that the code in the M9301-YJ is written with the assumption that the processor will trap to
Unibus location 24 on power-up if the default boot on power-up feature is t~ be used. It is also
assumed that a power-up trap to Unibus location 24 will be invoked by the assertion and then nc~gation
of AC LO if the pushbutton boot feature is to be used.
Note further that the processor priority is left at 7 when the standard boots are exited.

14.3 MICROSWITCH FUNCfIONS
A set of ten microswitches is located on the M9301 module. They determine which ROM routines are
selected and give the user automatic access to any function.
The primary activating processes for the M9301-YJ are the power-up sequence and the enabling of the
console boot switch. 8witch 81-1 must be in the ON position in order to enable activation of the
M9301-YJ console emulator and diagnostics. 8witch 81-2 is the power-up reboot enable switch. It
must be ON to enable to M9301-YJ on power-up. If switch 81-2 is OFF, then the processor will trap to
location 24 (as normal) to execute the user power-up routine. When switch 81-2 is ON, thc~ other
switches, SI-3 through 81-10, determine what action the M9301-YJ will take on power-up.
If the system supports a console boot switch, then any time that switch is pressed, the M9301-YJ will
be activated. Enabling the console boot switch causes the processor to enter a ROM routine by creating a fake power-down/power-up sequence. The user should note that the position of switch S 1-2 is
irrelevant when the console boot switch is used. Pushing the console boot switch thus resullts in a
power-up sequence in the processor through an M9301-YJ ROM routine.
Prior to the power-up sequence, the M9301-YJ asserts 773000 on the Unibus address lines. This causes
the new PC to be taken from ROM location 773024 instead of location 000024. The new PC will be the
logical OR of the contents of ROM location 773024 and the eight microswitches on the M9301-YJ
module. A switch in the ON position is read as a 0 and a switch in the OFF position is a 1. In this way
all the M9301-YJ options are accessible. Each option is given a different address. Note that microswitch SI-10 is ORed with bit 1 of the data in ROM location 773024; 81-9 is ORed with bit 2, letc. No
switch is provided for combination with bit 0, because an odd address could result when going through
the trap sequence.
The microswitches on the M9301-YJ enable the user either to start a bootstrap operation or to enter
the console emulator, simply by pressing the boot switch. Note that a momentary power failure will
have the same effect as pushing the boot switch.
The user should also note that he can select any function without diagnostics by adding 2 to the
appropriate octal code in the switches. Figure 14-2 shows the relationship of the switches to the bus
address bits.

14-2

LOW ROM ENABLE

POWER UFt REBOOT ENABLE

•

-I 1 12

CORRESPONDING
BUS ADDRESS BITS
BINARY VALUE
OF SWITCHES

S1
SWITCHES

OCTAL VALUES
OF SWITCHES

Y
ON = 0
OFF = 1

11-4865

Fgure 14-2 Offset Switches and Correspondence Bus Address Bits
14.4 BOOTSTRAPPING PAPER TAPE, FLOlPPY DISK, AND MAGNETIC TAPE
The paper tape boot is unique in that it can do. no lerror checking and the secondary bootstrap (e.g., the
absolute loader) is read into the upper part of memory. The actual locations loaded by the paper tape
boot are partially determined by the secondary bootstrap itself and by the size routine which determines the highest available memory address within the first 28K. The flexible disk (or floppy) reads
sector 1 on track 1 into locations starting at zero. The magnetic tape boot reads the second block into
locations starting at O. If no errors are detected in the device, the bootstraps normally transfer control
to location 0 in order to execute the secondary bootstrap just loaded. The only exception to this
starting address is with the paper tape boot. It transfers control to location XXX374, where XXX is
determined initially by the size routine to be at the top of memory; this is where the absolute loader will
have just been loaded.
If a device error is detected, a reset will be executed, and the bootstrap will try again. The bootstrap
will be retried indefinitely until it succeeds without error unless the operator intervenes. The advantage
of retrying the boot is that if a particular device being booted is not on-line or loaded, because of a
power failure and restart for example, the boot will give the device a chance to power-up. For disks this
is essential.. If a magnetic tape is to be booted, the user must reload the magtape and bring it back online and restart the boot.

Note that the only way to bootstrap a non-DECnet drive (unit or transport) other than drive 0 is by
entering the console emulator to specify that drive number desired. Otherwise the bootstraps will
default to drive O. This means that only drive 0 of a device can be bootstrapped without operator
intervention.
14.5 BOOTSTRAPPING THE DMCII-DECNET
The DMClll bootstrap routine loads memory in a satellite computer over a communication link, using
the maintenance operation protocol (MOP) within the DECnet system. The entire bootstrapping process involves three separate bootstrap programs.
14.5.1 Priimary Bootstrap
The primary bootstrap is a mode associated with the DMCII within the M9301-Yl ROM. It requests
a secondary boot from the host computer. The primary bootstrap routine will wait approximately 9
seconds for a reply and then make another request for the secondary boot. If, after eight tries, the host
has not responded, the satellite will hang up thle phone for approximately one half second. Data
terminal ready (DTR) is turned OFF and then 01'-~ again. After interrupting the communication link,
the primary bootstrap will initiate another series of requests for a secondary boot. The M9301-Yl
supports two MOP codes, 8 and 0, as follows. The primary boot sends out a MOP 8 message. It
expects a ~fOP 0 message back. The MOP 0 is the secondary boot which loads the tertiary boot with
transfer address.

14-3

If the primary boot detects any soft errors, it will make the request again. A soft error results from the
detection of either a non-fatal hardware error or a counterfeit message. Detection of a fatal error will
cause the M9301-YJ to reinitialize, disable DTR for approximately 1 second, reassert DTR, and begin
as it would on a power-up boot.

14.5.2 Secondary Bootstrap
The secondary bootstrap program, once loaded, requests a tertiary boot. These intermediate ste:ps are
important because the boot program which handles the actual loading of the operating system is too
long and complex to be stored in the ROM. Detection of an error in the secondary boot will cause a
reinitialization of the primary boot.
14.5.3 Tertiary Bootstrap
Once the tertiary boot has been requested and loaded, it relocates in upper memory and then begins
the down-line loading of the operating system. Figure 14-3 is a flowchart showing the relation of the
three bootstrap programs.
14.5.4 MOP Message Formats
The current MOP version (1.2, July 1976) operates within DDCMP maintenance envelopes. The current DDCMP version is 3.03-Dec 1975. All MOP messages are sent in a DDCMP maintenance: mode
envelope. This basic DDCMP message provides a CRC block check on the MOP data but does not
provide any acknowledgement of receipt. It is similar to a numbered data message used for conformance with DDCMP formats and hence software/hardware drivers for DDCMP. Its forrn is as
follows.

SYN, SYN, DLE, COUNT, Q, S, FILL, FILL, ADDR, CRCI, MOP MSG, CRC2
where:
SYN

DLE
COUNT
Q
S
FILL
ADDR
CRCI
MOPMSG
CRC2

=
=
=
=
=
=
=
=
=

The DDCMP sync characters: (8 bits)
226-synchronous
The boot message header character: 220 (8 bits)
The 14-bit count field: number of bytes in MOP message (14 bits)
The async link control flag: (I bit, always = I)
The select link control flag: (I bit, always = I)
A fill character: 000 (8 bits)
The tributary station address: (for pt-to-pt = I) (8 bits)
The header CRC on DLE through ADDR (l6-bit CRC-16)
The MOP message described below (COUNT 8-bit quantities)
The data CRC on MOP message only (16-bit CRC-16)

Notice that the maintenance messages are preceded by 3 or more SYNC characters appropriatc~ to the
link used; synchronous - 226.
The MOP message resides in the data field of the maintenance envelope. The form of the MOP message is:
CODE, INFO
where:
CODE
INFO

=
=

The MOP operation code (8 bits)
The information field (specific to each CODE)

14-4

START
PRIMARY
BOOT

START
SECONDARY
BOOT
INITIALIZE
DMC11

SET UP
TO RECEIVE
TERTIARY
BOOT
REQUEST
SECONDARY
BDOT
(MOPS)
REQUEST
TERTIARY
BOOT

ENTRV,l __
POINTSJ

POWER
FAIL
BOOT

CONSOLE
BOOT
BUTTON

LOAD
ADDRESS
AND START

START
TERTIARY
BOOT

CONSOLE
EMULATOR

WAIT
1 SECOND"

RELOCATE
TERTIARY
BOOT TO UPPE R
MEMORY·UPTO
124K

HANG UP
PHONE

START LOADING
IN OPERATING
SYSTEM

START
OPERATING
SYSTEM

11·5217

Figure 14-3 M9301-YJ Down
Line Load Flowchart
14-5

The form of the MOP 8 program (request secondary boot) follows.
CODE (1 byte) = 8
MSG DATA = DEV TYPE 148, STA DDR (1), PGM TYPE (0)
where:
DEV TYPE (1 byte)

The:: device type at the requesting system. It is always 148
for the DMCII and the M9301-YJ.

STA DDR (1 byte)

The: address of the requesting station. For point-topoint this is always 1. This is always I for the M9301-YJ.

PGM TYPE (1 byte)

The: type of secondary program requested. PG M type is
always 0 for the M9301-YJ.

The form of the MOP 0 program (memory load with transfer address) follows.
CODE (1 byte) = 0
MSG DATA = LOAD NUM, LOAD AI)DR, IMAGE DATA, TRANSFER ADDR
where:
LOAD NUM (1 byte)

The: load number for multiple load images. It may be
pre(~eded by loads without transfer address. This starts
at 0 and is incremented for each load. This should
always be 0 for the M930I-YJ.

LOAD ADDR (4 bytes)

The memory load address (starting address) for the storage of the data image. It should be 0 in MOP O. This
should always be 0 for the M930I-YJ.

IMAGEDATA

The image to be stored in the computer memory. The
forrn sent will be machine dependent and may vary with
the type and word length of the system [e.g., for PDP-II
syst'ems, each byte represents one memory byte (8 bits)].

TRANSFER ADDR (4 bytes)

The starting address of the image just loaded. This is
always 6 for the M930 1-Y J.

DECnet uses two CPU registers. RO contains the device index code. R I contains the CSR address of
the device.

14.6 PO'VER-UP BOOT AND CONSOLE BOOT
When the operator performs a system power-up or presses the console boot switch, he causes the
M9301 module to react by initiating a bootstrap routine. Table 14-1 shows the correct microswitch
settings for the various options.

14-7

Table 14-1

Microswitch Settings

Function

SI-1

0 etal
Code

Vector 24

OFF

Console
Emulator
with Diag.

000

Console
Emulator
without Diag.

OFF

002

Run Non-Memory
Modifying
Diag. then
ON
Vector 24

OFF

01 54

Vector 24

OFF

01 56

Boot RXOI
with Diag.

OFF

152

Boot RXOI
without Diag.

OFF

1. 54

Boot TUIO
with Diag.

OFF

i..

Boot TUIO
without Diag.

OFF

Boot DLII
with Diag.

OFF

100

Boot DMCll
Unit 0
with Diag.

OFF

354

Boot DMCll
Unit 0
without Diag.

OFF

:3 56

Boot DMCII
Unit I
with Diag.

OFF

372

Boot DMCll
Unit I
without Diag.

OFF

374

Note that when using the console boot switch, the state of S 1-2 has no relevance.
14-8

,56

...

.. 60

14.7 LOAD ADDRESS AND START PROCE))URE VIA CONSOLE SWITCH REGISTER
The user who wishes to initiate a function other than the one which he has specified in the microswitches can do so without presetting those micros witches. This involves a load address, placing an
option code in the console switch register and prl:ssing start; or simply by doing a load address and
pressing start at one of the addresses specified below.
The user must load address 173072 and then, before pressing the start switch, he must place a device
code or option code in the switch register. Or the. user may place the device code or the option code in
the console: switch register and then press load address and start. These options and codes are shown in
Table 14-2 .
Table 14-2

Load Address and Start Codes

Code

Function

173000*
173004*
173152*
173154*
173256*
173260
173100*
173354*
173356
173372*
173374

To enter console ernulator after running primary diagnostics
To enter console ernulator without diagnostics
To boot the RXOI with diagnostics
To boot the RXO 1 without diagnostics
To boot the TV 10 with diagnostics
To boot the TUI0 without diagnostics
To boot the DLII paper tape with diagnostics
To boot the DMClll unit 0 with diagnostics
To boot the D MC 111 unit 0 without diagnostics
To boot the DMClll unit 1 with diagnostics
To boot the DMClll unit 1 without diagnostics

*Switch SI-1 must be on.

14.8 OPERATION OF THE M9301-YJ CONSOLE EMULATOR
The user cam boot a program from any of four peripheral devices by calling the bootstrap program for
that peripheral through the console emulator.
The first routines to be executed (if 000 is the contents of the microswitches) are the primary CPU
diagnostics.
The display routine is entered automatically. This routine will type the contents of RO, R4, R6, and R5
(note the sequence) on the Teletype or terminal in octal. Pressing the console boot switch causes the
PDP-l1/04 and PDP-ll/34 systems to copy the PC into R5 before the power-up sequence starts. The
console emulator (keyboard dispatch) program is then entered automatically. This routine types a
carriage return, a line feed and then the prompt syrnbol, $. The user can call bootstrap programs at this
point by typing the appropriate device code. He then types an octal number following the device code
specifying the drive number (default 0) and hits the carriage return key. Table 14-3 lists the peripheral
bootstrap programs supported by the M9301-YJ.
Note that 12 console fill characters are used betwecm the carriage return and the line feed in the console
emulator routine.

14-9

Table 14-3

Bootstrap Programs

Device

Description

Command*

DLll **
DMCII
RXII
TMII

Low Speed Paper Tape Reader
Synchronous Line Interface
RXOI Floppy Disk Drive
TU 10800 BPI Magtape

TT
XM#
DX#
MT#

*The # specifies unit number (default 0). It can be 0 or 1 for OX, 0-7 for MT, and 0-17 for XM.
**This device is not bootable if S 1-1 is off.

14.9 RESTARTING AT THE USER POWER FAIL ROUTINE
If the user wishes to restart his own software on a power-up, he may do so by merely disabling the
power fail restart switch in the microswitches (turn SI-2 OFF).
But the user can use the M9301-YJ to run diagnostics (just the primary CPU tests described in Paragraph 14.10.) before running his power-up routine. This will in no way disturb the contents of m.emory
and will in fact verify the machine's basic integrity after the power-down and -up sequence.
To use this option the operator should load the code 054 into the microswitches as described in
Paragraph 14.7. Be sure that switch SI-2 is ON. This will result in the running of the primary CPU
diagnostics and then a simulated trap through 24 which willstart the user's specified power-up routine.
If the code 056 is placed in the microswitches then the simulated trap through 24 is executed without
running diagnostics.
Figure 14-4 is an operator's flowchart showing the relation of the various options and codes available
to the user.

14.10 DIAGNOSTICS
An explanation of the eight CPU and memory diagnostic tests follows. Three types of tests are ilnc1uded in the M9301-YJ diagnostics:
1.
2.
3.

Primary CPU tests (1-5)
Secondary CPU tests (6, 7)
Memory test'(8)

14.10.1 CPU Tests
The primary CPU tests exercise all unary and double operand instructions with all source lmodes.
These tests do not modify memory. If a failure is detected, a branch-self (BR.) will be execute:d. The
run light will stay ON, because the processor will hang in a loop. If no failure is detected in tests 1-5,
the processor will emerge from the last test and enter the register display routine (console emulator).
Note that the CRC and LRC for diagnostic DZM9A are XXXXXX and XXXXXX.
TE:ST 1 - SINGLE OPERAND TEST
This test executes all single operand instructions using destination mode O. The basic objective is to
verify that all single operand instructions operate; it also provides a cursory check on the operation of
each instruction, while ensuring that the CPU decodes each instruction in the correct manner.

14-10

USER POWER
UP MODE

NORMAL MODE

AUTOMATIC
BOOT MODE

LOAD ADDRESS
AND START MODE

000

002

054

056

I
I
I

152

RX01

154

173152

RX01

173154

256

TU10

260

173256

TU10

173260

100

DL11

173100

DL11

354

DMC11
UNIT 1

356

173354

DMC11
UNIT 0

173356

372

DMC11
UNIT2

374

173372

DMC11
UNIT 1

173374

START

CPU DIAG
TESTS
1-5

CONSOLE
EMULATOR

CPU DIAG
TESTS 1·5

CONSOLE
EMULATOR

USER POWER
UP ROUTINE

CPU DIAG
TESTS 1-5

USER POWER
UP ROUTINE

173000

CONSOLE
EMULATOR

START

CPU DIAG
TESTS 1-5

START

CPU DIAG
TESTS 1-5

CONSOLE
EMULATOR

CPUDIAG
TESTS 6,7

CONSOLE
EMULATOR

MEMORY
SIZING

EXTENDED
CPU DIAG
TESTS 6,7

MEMORY
DIAG TESTS

MEMORY
SIZING

BOOT THE DEVICE
SELECTED IN
THE OFFSET
SWITCHES

MEMORY
DIAG
TESTS

BOOT THE
DEVICE
SELECTED
ONKBD

173004

EXTENDED
CPU DIAG
TESTS 6,7

BOOT THE DEVICE
SELECTED IN
THE OFFSET
SWITCHES

MEMORY
SIZING

BOOT THE DEVICE
SELECTED IN THE
SWITCH REGISTER

MEMORY
DIAG
TESTS

BOOT THE
DEVICE
SELECTED
ONKBD

BOOT THE DEVICE
SELECTED IN THE
SWITCH REGISTER
11·5218

Figure 14-4 M9301-YJ
Operator's Flowchart
14-11

Test 1 tests the destination register in its three possible states: zero, negative, and positive. Each
instruction operates on the register contents in one of four ways:
1.

Data will be changed via a direct operation, i.e., increment, clear, decrement, etc.

Data will be changed via an indirect op~~ration, i.e., arithmetic shifts, add carry, and subtract
carry.

Data will be unchanged, but operated upon via a direct operation, i.e., clear a register
already containing zeros.

Data will be unchanged but examined via a non-modifying instruction (TEST).

NOTE
When operating upon data in an Indirect manner, the
data is modified by the state of the appropriate condition code. Arithmetic shift will move the C bit into
or out of the destination. This operation, when performed correctly, Implies that the C bit was set correctly by the prevlQus Instruction. There are no
checks on the data integJrity prior to the end of the
test. However, a check hi made on the end result of
the data manipulation. A correct result Implies that
all Instructions manipulated the data In the correct
way. If the data is incorrect, the program will hang in
a program loop until the machine is halted.
TEST 2 - DOUBLE OPERAND, ALL SOURCE MODES
This test verifies all double operand, general, and logical instructions, each in one of the seven addressing modes (excludes mode 0). Thus, two operations are checked: the correct decoding of each double
operand instruction, and the correct operation of each addressing mode for the source operand.
Each instruction in the test must operate correctly in order for the next instruction to operate. This
interdependence is carried through to the last instruction (bit test) where, only through the correct
execution of all previous instructions, a data field is examined for a specific bit configuration. Thus,
each instruction prior to the last serves to set up the pointer to the test data.
Two checks on instruction operation are made in test 2. One check, a branch on condition, is made
following the compare instruction, while the second is made as the last instruction in the test sequence.
Since the GO-NO GO test resides in ROM memory, all data manipUlation (modification) must be
performed :in destination mode 0 (register contains data). The data and addressing constants used by
test 2 are contained within the ROM.
It is important to note that two different types of operations must execute correctly in order for this
test to operate:
1.

Those instructions that participate in computing the final address of the data mask for the
final bit test instruction.

Those instructions that manipulate the tl~st data within the register to generate the expected
bilt pattern.

Detection of an error within this test results in a program loop.
14-13

TEST 3 - JUMP TEST MODES 1, 2, 3
The purpose of this test is to ensure correct operation of the jump instruction. This test is constructed
such that only a jump to the expected instruction will provide the correct pointer for the next
instruction.
There are two possible failure modes that can occur in this test:
1.

The jump addressing circuitry will malfunction, causing a transfer of execution to an
incorrect instruction sequence or non-existent memory.

The jump addressing circuitry will malfunction in such a way as to cause the CPU to loop.

The latter case is a logical error indicator. The former, however, may manifest itself as an after-the-fact
error. For example, if the jump causes control to be given to other routines within the M9301, the
interdependent instruction sequences would probably cause a failure to eventually occur. In any case,
the failing of the jump instruction will eventually cause an out of sequence or illogical event to occur.
This in itself is a meaningful indicator of a malfunctioning CPU.
This test contains a jump mode 2 instruction which is not compatible across the PDP-II line. However, it will operate on any PDP-II within this test, due to the unique programming of the instruction
within test 3. Before illustrating the operation, it is important to understand the differences of the jump
mode 2 between machines.
On the PDP-ll/20, 11/05, 11/15, and 11/10 processors, for the jump mode 2 [JMP(R)+] the register
(R) is incremented by 2 prior to execution ofthejump. On the PDP-ll/04, 11/34, 11/35, 11/40, 11/45,
11/50, 11/55, and 11/70 processors, (R) is used as the jump address and incremented by 2 after
execution of the jump.
In order to avoid this incompatability, the jump (R)+ is programmed with (R) pointing back on the
jump itself. On 11/20, 11/05, 11/10, and 11/15 processors, execution of the instruction would cause
(R) to be incremented to point to the following instruction, effectively continuing a normal <~xecution
sequence.
On the PDP-l 1/04, 11/34, 11/35, 11/40, 11/45, 11/50, 11/55, and 11/70 processors, the use of the
initial value of (R) will cause the jump to loop back on itself. However, correct operation of the
autoincrement will move (R) to point to the next instruction following the initial jump. The jump will
then be executed again. However, the destination address will be the next instruction in sequence.
TEST 4 - SINGLE OPERAND, NON-MODIFYING BYTE TEST
This test focuses on one unique single operand instruction, the TST. TST is a special case in the CPU
execution flow since it is a non-modifying operation. Test 4 also tests the byte operation of this instruction. The TSTB instruction will be executed in mode 1 (register deferred) and mode 2 (register
deferred, autoincrement).
The TSTB is programmed to operate on data which has a negative value most significant byte and a
zero (not negative) least significant byte.
In order for this test to operate properly, the TSTB on the low byte must first be able to access the even
addressed byte and then set the proper condition codes. The TSTB is then reexecuted with the
autoincrement facility. After the autoincrement, the addressing register should be pointing to the high
byte of the test data. Another TSTB is executed on what should be the high byte. The N bit of the
condition codes should be set by this operation.

14-14

Correct execution of the last TSTB implies that the autoincrement feature recognized that a byte
operation was requested, thereby only incrementing the address in the register by one, rather than two.
If the correct condition code has not been set by 1the associated TSTB instruction, the program will
loop.
TEST 5 - DOUBLE OPERAND, NON-MODIFYING TEST
Two non-modifying, double-operand instructions .- the compare (eMP) and bit test (BIT) - operate
on test data in source modes 1 and 4, and destination modes 2 and 4.
The BIT and CMP instructions will operate on data consisting of all ones (177777). Two separate fields
of ones are used in order to utilize the compare instructions, and to provide a field large enough to
handle the autoincrementing of the addressing register.
Since the compare instruction is executed on two fie~lds containing the same data, the expected result is
true Z bit, indicating equality.
The BIT instruction will use a mask argument of all ones against another field of all ones. The expected
result is a non-zero condition (Z).
:Most failun:~s will result in a one instruction loop.
At the end of test 5 the register display routine is enabled, provided the console emulator has been
selected in the microswitches. The register display routine prints out the octal contents of the CPU
registers RO, R4, SP, and old PC on the console terminal. This sequence will be followed by a prompt
character ($) on the next line.
An example of a typical printout follows.

XXXXXX

R6
(Stack
Pointer)

R5
(Old PC)

Prompt
Character
NOTES:
1.

Where X signifies an octal number (0-7).

Whenever there is a power-up routine or the BOOT switch is released on PDP-ll/04 and
PDP-ll/34 machines, the PC at this time: will be stored in R5. The contents of R5 are then
printed as the old PC shown in the exarrtple.

The prompting character string indicates that diagnostics have been run and the processor is
operating.

14.10.2 Se(=ondary CPU and Memory Tests
The secondary CPU tests modify memory and involve the use of the stack pointer. The JMP and JSR
instructions and all destination modes are tested. If a failure is detected, these tests, unlike the primary
tests, will execute a halt.

Secondary CPU and memory diagnostics are run itllmediately after test 5 when they have been evoked
lby means other than the console emulator, provided that the correct microswitches have been set. If
the console emulator has been entered at the completion of test 5, the secondary CPU and memory
diagnostics will be run when the appropriate boot command is given.
14-1l5

TEST 6 - DOUBLE OPERAND, MODIFYING BYTE TEST
The objective of this test is to verify that the double-operand, modifying instructions will operate in the
byte mode. Test 6 contains three subtests:
1.

2.
3.

Test source mode 2, destination mode 1, odd and even bytes
Test source mode 3, destination mode 2
Test source mode 0, destination mode 3, even byte.

The move byte (M OVB), bit clear byte (BleB), and bit set byte (BISB) are used within test 6 to verify
the operation of the modifying double-operand functions.
Since modifying instructions are under test, memory must be used as a destination for the te~st data.
Test 6 uses location 500 as a destination address. Later, in test 7 and the memory test, location 500 is
used as the first available storage for the stack.
Note that since test 6 is a byte test, location 500 implies that both 500 and 501 are used for 1the byte
tests (even and odd, respectively). Thus, in the word of data at 500, odd and even bytes are caused to be
aU Os and then allIs alternately throughout the test. Each byte is modified independently of the other.

TEST 7 - JSR TEST
The JSR is the first test in the GO-NO GO sequence that utilizes the stack. The jump subroutine
command (JSR) is executed in modes 1 and 6. After the JSR is executed, the subroutine which was
given control will examine the stack to ensure that the correct data was placed in the correct stack
location (500). The routine will also ensure that the line back register points to the correct addrc~ss. Any
errors detected in this test will result in a halt.
TEST 8 - DUAL ADDRESSING AND DATA CHECK
Finally the memory test performs both dual addressing and a data check of all the available memory
on the system below 28K. This test will leave all of memory clear. Like the secondary tests the lmemory
test will halt when an error is detected. At the time the memory error halt is executed, R4 will contain
the address at which the failure was detected plus two. RO will contain the failing data pattern and R6
will contain the expected data pattern. Thus after a memory failure has occurred the user can emter the
console emulator and have this information printed out immediately by the display routine (sec~ section
on console emulator).
14.11 TROUBLESHOOTING
When a halt occurs, the user should reboot the system by pressing the BOOT /INIT swit.ch. The
registers RO, R4, R6, and R5 will be displayed on the terminal in that order.
RO
R4
R6
R5

Failing (received) data
Failing address
Expected data
Old PC

The diagnostic program in the M9301-YJ will cause the processor to halt at one of four addresses:
165600, 165614, 165630, or 165776. The user should consult the diagnostic program listing to find the
failing test and begin troubleshooting. Possible causes of the failure include bus errors, a bad M9301
module, and a bad CPU.

14-16

14.12 FLOATING DEVICE PRIORITY
The M9301-YJ assumes the following priority of devices in the floating address space.
1.

2.
3.
4.
5.
6.
7.

DJll
DHII
I)QII
DUll
DUPII
LKII-A
DMCll

The M9301-YJ will not function properly unless thl~ above priority and correct Unibus address spacing
is followed.

14··17

Reader's Comments
M9301 BOOTSTRAP/TERMINATOR MODULE
MAINTENANCE AND OPERATOR'S MANUAL
EK-M9301-TM-OOI

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