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Document:	Unibus Troubleshooting User's Manual
Order Number:	EK-FS002-OP
Revision:	001
Pages:	108
Original Filename:	http://bitsavers.org/pdf/dec/unibus/EK-FS002-OP-001_Unibus_Troubleshooting_Users_Manual.pdf

OCR Text

Service
,,';;"
Test
~~l:~ q,ui pmen t
. "f: • • "~'.~ :......

Unibus
Troubleshooting
user's manual

EK-FS002-0P-001

COMPANY CONFIDENTIAL

digital equipment corporation • maynard, massachusetts

1st Edition, February 1977

Copyright © 1977 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
This manual is intended for use by authorized
DIGITAL personnel only. The information
contained in this manual is intended to be used
for analyzing product performance.
Printed in U.S.A.

This document was set on DIGITAL's DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem-10
DECSYSTEM-20

DECtape
DECUS
DIGITAL
MASSBUS

PDP
RSTS
TYPESET-8
TYPESET-II
UNIBUS

CONTENTS
Page

1.1
1.2
1.3
1.4
1.5

INTRODUCTION
SYSTEM OVERVIEW . . . . . . . . . . . . ..
UNIBUS TROUBLESHOOTING TECHNIQUES
HI/LO TERMINATOR MARGIN CARDS
UNIBUS VOLTAGE MARGIN TESTER BOX
SINGLE-ENDED MARGINING TECHNIQUE

CHAPTER 2

UNIBUS CONFIGURATION

2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2.2.1 0
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.5
2.5.l
2.5.2
2.5.3
2.5.4

GENERAL
..... .
UNIBUS DEFINITIONS
Bus Segment
Bus Cable
Bus Element
Lumped Load
Bus Jumper
Bus Terminator
Semi-Lumped Load
AC Unit Load
DC Unit Load
Unibus Length and Loading
UNIBUS CONFIGURATION RULES
Maximum Cable Length (Rule No.1)
Maximum dc Loading (Rule No.2)
Maximum Lumped Loading (Rule No.3)
Skewed Cable Lengths (Rule No.4)
Skewed Cable Lengths, Supplement (Rule No.5)
Rule Violations (Rule No.6) . .
System Acceptance (Rule No.7)
Actual Bus Loading
UNIBUS LATENCY . . . . .
Device Categories
NPR Calculations for Tl
Latency Tolerance Calculations
BR Devices . . . . . . . . .
Unibus Loading Rules
BUS BUSY TEST TECHNIQUES .
Bus Busy and Latency Tolerance
Calculating Nominal Bus Busy Times
Measuring Bus Busy Times
Configuration Tables . . . . . . . .

CHAPTER 1

iii

1-1
1-2
1-2
1-2
1-2

2-1
2-1
2-1
2-2
2-2
2-2
2-2
2-4
2-4
2-5
2-6
2-6
2-7
2-8
2-8
2-8
. 2-11
2-13
. 2-16
2-16
2-17
2-19
2-22

2-22
2-23
2-23
2-23
2-24
2-24
2-25
2-27
2-30

CONTENTS (Cont)

Page
CHAPTER 3

TROUBLESHOOTING

3.l
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.3.1
3.4

GENERAL
..... .
TIMING CONSIDERATIONS
DATO-DATOB . . . .
DATI-DATIP . . . . . .
Interrupt Transactions .
High-Frequency Cable Losses
Peripheral Data Rate . . . .
PROP AGA TION DELAY. . . .
Line Termination Technique
CABLE AND CONTACT RESISTANCE LOSSES

CHAPTER 4

BUS MARGINING

4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.4
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.6.3

GENERAL
.....
BUS QUIESCENT LEVELS
Quiescent Conditions
Multiple Bus System Considerations
Grant Line Termination . . . . . .
HI/LO TERMINATOR BUS MARGINING
UNIBUS VOLTAGE MARGIN TESTER BOX
Functional Description . . . . . . . . .
UVM-TA Operation and Test Procedures
SINGLE-ENDED MARGINING . . . . . . .
Setup and Operation (Using M9308 Single-Ended Margin Head)
Single-Ended Circuit Consideration
SACK Timeout . . . . . . . . . . . .
MODIFYING M930 TERMINATOR CARD
Equipment Required
Modifying the M930
Procedure for Use

CHAPTERS

UVM-TA TESTER

5.1
5.2
5.3
5.4
5.5
5.6
5.7

UVM-TA OVERVIEW
TESTER KIT COMPONENTS
TESTER SPECIFICATIONS
UNP ACKING PROCEDURE
ACCEPTANCE TEST . . .
CONTROLS AND INDICATORS
OPERATING PROCEDURE
MAINTENANCE PHILOSOPHY
PREVENTIVE MAINTENANCE
CORRECTIVE MAINTENANCE
DISASSEMBLY/ASSEMBLY ..

3.3

5.8
5.9

5.l0
5.l1

3-1
3-1
3-1
3-1
3-5
3-5
3-6
3-6
3-11
· 3-12

4-1
4-1
4-2
4-6
4-8
4-8

· 4-10
· 4-13
· 4-13
· 4-15
· 4-15
· 4-17
4-21
· 4-21
· 4-21
4-22
· 4-23

5-1
5-1
5-2
5-3
5-3
5-3
5-3
5-5
5-5
5-6
5-6

CONTENTS (Cont)

APPENDIX A

ECO HISTORY AND REWORK

APPENDIX B

M9202-2 UNIBUS JUMPER INSTALLATION

APPENDIX C

AC AND DC LOAD TABLE

APPENDIX D

BUS LOADS

FIGURES
figure No.

2-1
2-2
2-3
2-4
2-5
2-6

2-7
2-8
2-9
2-10
2-11
2-12
2-13

2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23

2-24
3-1
3-2

3-3
3-4
3-5
3-6

3-7
3-8

Title

Lumped Loads (Example A)
Lumped Loads (Example B)
Semi-Lumped Loads (Example C)
...... .
Bus Load Example
Rule No.3 Violation (Block Diagram)
Rule No.3 Violation (Waveform Example)
Rule No.3 Implementation (Block Diagram)
Rule No.3 Implementation (Waveform Example)
Multiple Bus System Example ., . . . . . . . .
.. . . .
Rule No.4 Violation (Block Diagram)
Rule No.4 Implementation (Example A) Block Diagram
Rule No.4 Implementation (Example B) Block Diagram
Rule No.4 Violation (Waveform Example)
Rule No.4 Implementation (Waveform Example) ..
Skewed Cable Length Violation . . . . . . . . . . .
Skewed Cable Length Violation (Waveform Example)
Violation of Rule No.5 (Waveform Example) . . . .
Implementation of Rule No.5 (Waveform Example)
Actual Bus Loads Example . . . . . . . .
Algorithm to Determine NPR Sequence ..
Unibus Length Between Device and Memory
Single-Cycle Transaction
Double-Cycle Transaction . . . . .
DLT Configurations . . . . . . . .
Unibus Troubleshooting Flowchart
System Cabling Configuration Example
Transmission Line Circuit Example
BCII-A Unibus Cable Delay Example .
BCll Unibus Cable Impedance Example
Impedance Mismatch Example
Impedance (Low Resistance) Mismatch Example
Mismatch Reflection Curve Example
..... .

Page

2-3
2-4
2-5

2-7
2-8
2-9
2-9
2-10
2-10
2-11
2-11

2-12
2-12
2-13
2-14
2-14
2-15
2-15

2-17
2-20
2-28
2-29
2-30

2-31
3-2
3-5

3-7
3-7
3-8
3-9
3-9
3-10

FIGURES (Cont)

Figure No.
3-9
3-10
3-11
3-12
4-1
4-2
4-3

4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
5-1
5-2
5-3

Title
BCl1 Unibus Cable Mismatch (Waveform Example)
System Device Impedance Example
Line Termination Technique Example
Cable Resistance Problems Example
Unibus Slot Backplane Signals
Low True Unibus Line
Equivalent Unibus Line Circuit
Quiescent dc Level Example .
Load Current Leakage Example
Quiescent Level vs. Bus Loading (Worst Case)
Margining Multiple Bus Systems . . .
Grant Line Bus Margining Technique
Margining Cards . . . . . . . . .
Hi/Lo Terminator Circuit Example
UVM-TA Circuit Representation
Controls and Indicators
UVM-TA Block Diagram
Single-Ended Circuit Example .
Quiescent Voltage vs UVM-TA Voltage
M9308 Termination Circuit Example
M9308 SACK Turnaround Logic
M930 Modification Example
Unibus Voltage Margin Tester Box
Controls and Indicators (Indexed)
UVM-TA Troubleshooting Flowchart

Page
3-10
3-11
3-12
3-13
4-3

4-4
4-4
4-5
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-11
4-12
4-15
4-18
4-20
4-22
4-23
5-2

5-4
5-7

TABLES

Table No.

2-1
2-2
2-3
2-4
2-5
4-1
4-2
5-1
5-2
5-3

Title
Realistic Load Values
. . . . . . . . . . . . . .
Maximum NPR Rates of the NPR Devices with Variable Speed
Device Delay (Ddv) . . . . . . .
Memory Access Delay (Dma)
Transmitter/Receiver Delay (Dtr)
Bus Quiescent Levels
Terminator Application Data
Tester Kit Components
Controls and Indicators (Indexed)
Preventive Maintenance Schedule

Page
2-18
2-19
2-26
2-26
2-26
4-1
4-19
5-1

5-5
5-6

PREFACE

This user's manual is a detailed troubleshooting and reference guide for isolating Unibus problems
related to (a) systems which are inoperative and (b) systems which are marginal.
Due to the complexities and terminology associated with the Unibus, this manual also contaim
descriptions, definitions and reference material relative to the Unibus and associated hardware.
NOTE
This manual does not define the optimum system
configurations for throughput or latency tolerence
which may be dependent on customer usage and
applications environment.
This manual supersedes Unibus Margin Tester user's guide, document number EK-FS002-0P-PRE.
NOTE
The M9308 Margin Heads are direct replacements
for the M9303 Margin Heads. However, the M9308
allows for greater margining voltage (2.93 to 7.85 V)
than the M9303 (4.2 to 7.0 V).

CHAPTER 1
INTRODUCTION

1.1 SYSTEM OVERVIEW
Most of the PDP-l1 's internal electronic components and system peripherals are connected to and
communicate with each other through the Unibus. There are 56 lines on the bus that handle such
signals as address, data and control information. Each device, including memory locations and peripheral device registers, is assigned one address on the Unibus.
NOTE
This manual is intended for use by authorized DIGITAL EQUIPMENT CORPORATION personnel
only. Information contained in this manual is neither
intended to be a product specification nor to supersede or replace any other published information that
is available to customers or users of DIGITAL
products.
Some PDP-II system configurations experience permanent and intermittent bus failures due to
improper signal termination and loading techniques. (These problems can exist even when the proper
guidelines and rules for system configurations are followed.) This manual will assist in the proper
procedures for isolating configuration and Unibus problems, and corrective action that can be implemented for better system operation.
Due to complexity of system configuration and operation, all Unibus systems are subject to additional
electrical and mechanical factors which may become even more relevant when, and if, these factors
interact. If this interaction becomes large enough, it can cause false signal levels that can seriously
effect system operation. Some of the signal conditions that can occur because of these additional
electrical and mechanical factors follow.
1.
2.
3.
4.
5.
6.
7.

Signal caused by dc loading of receivers and drivers
Signal loss caused by nonzero resistance of BC 11 jumper cable
Signal loss caused by connector contact resistance
Standing wave reflections from devices on the line
Increased propagation delay caused by devices on the line and high frequency cable losses
Crosstalk on bus lines caused by the cable or by devices attached to the bus
Signal skew caused by multiple high-frequency loading on different lines by a device

1-1

1.2 UNIBUS TROUBLESHOOTING TECHNIQUES
Currently, there are three troubleshooting aids that can be used to troubleshoot and isolate Unibus
problems.
1.
2.
3.

Hi/Lo Terminator Margin Cards
Unibus Voltage Margin Tester Box
Single-Ended Margining Technique

A fourth troubleshooting aid is the flowchart (refer to Chapter 3) which is organized into a general
flow and reference diagram which points out particular sections that contain troubleshooting techniques and supportive information. The supportive information will aid in the understanding of, and
provide background for, the use of the Unibus Troubleshooting techniques outlined in Chapter 3 of
this manual.
1.3 HI/LO TERMINATOR MARGIN CARDS
The Hi/Lo Terminator Margin Cards are used to replace the M930 bus terminator in the PDP-II
system for margining purposes. The Hi/Lo Terminator Cards are used as a go/no go test and are not
to be installed in the system on a permanent basis. (Refer to Chapter 4 for additional operational
procedures and descriptions.)
1.4 UNIBUS VOLTAGE MARGIN TESTER BOX
The Unibus Voltage Margin Tester Box is designed to test Unibus driver and receiver terminating
networks for the PDP-II system. The tester is connected to the Unibus through special terminator
cards called margining heads. When the tester is cabled to the Unibus, the operator can select which
signal(s) (single, groups, or all) is to be tested. (Refer to Chapter 4 for additional operational procedures and descriptions.)
1.5 SINGLE-ENDED MARGINING TECHNIQUE
For some PDP-II processors (e.g., PDP-I 1/04 and PDP-I 1/34), it is not possible to use the M930
margining heads with the Unibus Voltage Margin Tester Box. This is due to additional hardware on
the terminator module (boot strap function, sack turnaround, etc.) which must be present in order for
the processor to operate normally. It is for these processors that the Unibus Tester Box' single-ended
margining technique has been developed. However, this technique can be used with any Unibus processor. (Refer to Chapter 4 for additional operational procedures and techniques.)

1-2

CHAPTER 2
UNIBUS CONFIGURATION

2.1 GENERAL
After the Unibus option configuration (based on NPR latency, physical location, etc.) is determined,
these options must be interconnected using the correct procedure and techniques.
The definitions, rules and guidelines outlined in this section are designed to aid you in configuring an
electrically reliable Unibus. These rules and guidelines are intended for new systems and are not to be
considered as a justification for any changes in existing systems, unless Unibus related problems are
encountered and cannot be resolved in any other way.
The configuration rules (Paragraph 2.3) ensure, with reasonable confidence, that Unibus segments will
be electrically reliable, i.e., resulting dc bus levels will guarantee an adequate noise margin, and reflections from lumped loads will not be excessive.
To configure a Unibus system, the required order of options on the Unibus, based on NPR latency,
physical location, etc., should first be determined. The rules will then determine the length the Unibus
cable interconnecting the options and the number and location of bus repeaters. If the number of bus
repeaters is excessive, total cable length can sometimes be reduced by rearranging the order of options
on the bus (again, paying close attention to NPR latency, etc.). Then, after reapplying the rules in this
guide, one or more bus repeaters may be eliminated or located further down the bus to optimize system
speed. For large systems, more than one pass of this procedure may be necessary to achieve satisfactory results.
A reasonable effort should always be made to ensure total cable length is as short as possible, particularly if one or more bus repeaters can be eliminated in the process. Bus repeaters are costly and slow
down the system. Before implementing configuration rules, the user should carefully read and understand the definitions that follow.
2.2 UNIBUS DEFINITIONS
Prior to configuring the Unibus, review the definitions outlined in Paragraphs 2.2.1 through 2.2.10.
2.2.1 Bus Segment
The Bus Segment is defined as that portion of a Unibus system between and including two terminators.
A bus segment consists of: a terminator, a 120 ohm transmission path (cable) with options containing
drivers and receivers attached to it, and another terminator in that order. A single bus system is one
which has one bus segment. A multiple bus system is one which has more than one bus segment,
usually separated by bus repeaters (DB11s) or bus switches (DT03s - which contain bus repeaters).

2-1

2.2.2 Bus Cable
A Bus Cable is defined as cable connecting two backplanes which acts as a 120 ohm transmission line
with a length of two feet or more. A BC llA cable is defined to be both a cable and a bus element. For
our purposes, the cable is a subset of the bus element and should be treated as such. The following bus
elements are Unibus cables:

BCllA-2
BCllA-3
BCl1A-5
BC1IA-6
BCIlA-8F
BClIA-1O
BClIA-15
BC11A-20
BCIIA-25
BClIA-30
M9202

2-foot Unibus cable (60.96 cm)
3-foot Unibus cable (91.44 cm)
5-foot Unibus cable (1.52 m)
6-foot Unibus cable (1.82 m)
8.5-foot Unibus cable (2.59 m)
lO-foot Unibus cable (3.04 m)
l5-foot Unibus cable (4.57 m)
20-foot Unibus cable (6.07 m)
25-foot Unibus cable (8.60 m)
30-foot Unibus cable (9.14 m)
24-inch folded Unibus cable (60.96 m)

The M9202 is considered to be a cable (for the purposes of this manual) because it contains 2 feet of
120 ohm cable.
2.2.3 Bus Element
A B us Element is defined as any module, backplane, cable or group of these items that has a common
designation which has a direct electrical connection to one or more Unibus signal lines (other than AC
LO L or DC LO L). For example, an M930 terminator, an M7821 module, a BBII backplane, a BCll
cable, and an RKll controller are Unibus elements. An H720 power supply, an LA36 DECwriter and
a BAll expander bo.X are not Unibus elements.
2.2.4 Lumped Load
A Lumped Load is defined as a group of Unibus elements, other than cables or jumpers, which are
interconnected via Unibus jumpers and direct wiring (backplane wire, PC etch) only. The group is not
a lumped load if it uses a Unibus cable to interconnect the Unibus elements or if the elements are
separated by a bus repeater. (Be certain the difference between "jumper" and "cable" is understood see Figures 2-1 and 2-2.)
2.2.5 Bus Jumper
A Bus Jumper is defined as a Unibus element connecting two backplanes which contains less than two
feet of cable. The following elements are Unibus jumpers:

M920
M9200
M98l
BCllA-O

jumper
jumper with boards 1.27 cm (0.5 in) apart
jumper /terminator
6-inch cable (15.24 cm)

The BCllA-O is considered to be a jumper (for the purposes of this manual) because it contains less
than 60.96 cm (2 feet) of 120 ohm cable.

2-2

JUMPER

CABLE
M930

11/06
CPU

MM11-L

BC11A-16

RK11-D

-i

M920

~ DD11-B -

)

..........

M9301

LUMPED LOAD

DL 11-A

~~------------~,,~-------------)
LUMPED LOAD
CP-2615

In this system, there are two lumped loads:
1.
2.

M930, 11/05 CPU, and MMll-L
RKII-D, DDll-B, DLII-A,and M9301

Suppose the M920 is replaced by an M9202:

CABLE
M930

11/06
CPU

MM11-L

CABLE

BC11A-16

RK11-D

H tM9202

~
LUMPED LOAD

LUMPED LOAD

DD11-B

M9301

I
DL11-A

l,-_ _~-....,.-~____--,)
LUMPED LOAD
CP-2616

Now there are three lumped loads:
1.
M930, 11/05 CPU, and MMII-D
2. RKII-D
DDII-B, DLlI-A, and M9301

Figure 2-1

Lumped Loads (Example A)

2-3

JUMPER
M930

JUMPER

11/45

DB11-A

DD11-B

I
I

DL11-A

CPU

\~----------~~--------~)1

DL11-A

I
I
I
I

LUMPED LOAD

I
I
1\
I
I
I

.,,.

M9301

DL11-A
DL11-A

---------~)
'-"
LUMPED LOAD

.....e - - - - - - - - UNIBUS
SEGMENT

UNIBUS
SEGMENT

CP·2617

This system has two Unibus segments separated by a bus repeater, so the system has two lumped loads:
1.
2.

M930, 11/45 CPU, DBII-A (left side)
DBII-A (right side), DDll-B, four DL11-As, M9301
NOTE
These examples are for illustrative purposes only and
do not represent practical configurations.

Figure 2-2

Lumped Loads (Example B)

2.2.6 Bus Terminator
A Bus Terminator is defined as a Unibus element or part of an element containing a resistive network
which connects to the end of a Unibus segment and matches the 120 ohm characteristic impedance of
the Unibus transmission path. The M930 and M9306 are Unibus terminators if they connect to the
Unibus. The following bus elements contain Unibus terminators:
M981
jumper /terminator
M9300
Unibus B terminator (M930 + NPR logic)
M9301
bootstrap /terminator
M9302
M930 with SACK return
DT03
bus switch
DBII-A
bus repeater
PDP-l1/04 CPU (NOTE: other CPUs also contain terminators)
A Unibus segment must always have a Unibus terminator at each end of its 120 ohm transmission
path.
2.2.7 Semi-Lumped Load
A semi-lumped load is defined as a group of lumped loads interconnected by 91.44 cm (3 ft) or less of
cable (M9202, BC11-2 or BCll-3) and not separated by a bus repeater. Refer to Figure 2-3.

2-4

.--M930

11/05
CPU

~ M9202

I- DB11-A H BC11A-10 J-- DD11-B I-- M9301

'---

I...

)

L-J:L-J

"-'"
LUMPED LOAD

LUMPED I LUMPED
LOAD I LOAD

I
)

"-'"
SEMI-LUMPED LOAD

I'---...r-J
: SEMI-LUMPED
LOAD

I
DL11-A
DL11-A
DL11-A
DL 11-A

'"'-------.....-~----)
LUMPED LOAD

SEMI-LUMPED LOAD

I
UNIBUS
I
UNIBUS
..
"'4~----SEGMENT-------1..
~I.4------SEGMENT-----"'-

I
CP-2618

This system has two Unibus segments, with a total of four lumped loads and three semi-lumped loads.
Lumped loads:
1.

2.
3.
4.

M930, 11/45 CPU
DBII-A (left side)
DBII-A (right side)
DDII-B, four DL11s, M9301

Semi-lumped loads:
1.

2.
3.

M930, 11/45 CPU, DB11-A (left side)
DBII-A (right side)
DDII-B, four DL11s, M9301

Figure 2-3

Semi-Lumped Loads (Example C)

2.2.8 AC Unit Load
An ac unit load is defined as a number related to the impedance that a Unibus element presents to a
Unibus signal line (due to backplane wiring, PC etch runs, receiver input loading, and driver output
loading). This impedance load on a transmission line causes a "reflection" to occur when a step is sent
down the line. This reflection shows up on an oscilloscope as a spike occurring shortly after asserting
or un asserting edge. An ac unit load is nominally 9.35 pF of capacitance. Nine lumped ac loads reflect
20 percent and 20 lumped ac loads reflect 40 percent of a 25 ns risetime step. AC loads must be
distributed on the Unibus in the manner described by the rules in this manual in order to provide bus
operation with reflections guaranteed to be at or less than a tolerable level.

2-5

The ac unit load rating of Unibus elements is usually based on the greatest of the capacitances that the
element presents to the BBSY, SSYN, and MSYN Unibus signal lines. Appendix C contains the ac
loading specifications of the Unibus elements. If the element is customer~designed, its ac unit loading
must be determined from a reasonable estimate of the equivalent capacitance presented to the Unibus.
2.2.9 DC Unit Load
A dc unit load is defined as a number related to the amount of dc leakage current that a Unibus
element presents to a Unibus signal line which is high (undriven). A dc unit load is nominally 105 /-LA
(80 /-LA - receiver plus 25 /-LA - driver). However, the dc unit load rating of a bus element is not strictly
based on the element's signal line that has the greatest leakage, (e.g., dc leakage is less important on D
lines than it is on SSYN). The dc unit loading of an element should always be obtained from the
specification for that element (see Appendix D). It should not be obtained from a calculation of the
receiver and driver leakage current, unless the element is custom-designed and is not listed in the
applicable documentation.
2.2.10 Unibus Length and Loading
The Unibus is a transmission line on which data transfers are asynchronous and interlocked. Significant electrical delay affecting system operation may, therefore, be imposed through unnecessarily long
Unibus cables.
With ribbon cable the maximum length is 15.24 m (50 ft). For proper operation, the length of taps or
stubs must be minimized. The Unibus signals should have receivers and transmitters in one place (near
the U nib us cable) to act as a buffer between the Unibus and the signal lines carrying Unibus signals
within the equipment. The maximum length of ribbon cable is obtainable only if the individual tap
lengths are less than 5.08 cm (2 in), including printed circuit etches and if the loading is not more than
one standard bus load. One bus load is defined as one transmitter and one receiver (see Figure 2-4).
The Unibus is limited to a maximum of 20 bus loads. This limit is set to maintain a sufficient noise
margin. For more than 20 bus loads, a Unibus repeater option (DBll-A) is used.

2-6

UNIBUS

TRANSMITTER

8881
RECEIVER

1 BUS LOAD = 1 TRANSMITTER + 1 RECEIVER
CP-25fi4

Figure 2-4

Bus Load Example

2.3 UNIBUS CONFIGURATION RULES
The following rules and guidelines are intended to be used for new systems and/or existing systems
that experience Unibus problems. The seven rules are listed below for quick reference. A more detailed
description, comments, and suggestions are described in the following paragraphs.
Rule No.1 (Maximum cable length) - The total length of Unibus cable in a Unibus segment should
not exceed 15.24 m (50 ft).
Rule No.2 (Maximum dc loading) - The total number of dc unit loads on a Unibus signal line should
not exceed 20. (See Appendix D.)
Rule No.3 (Maximum lumped loading) - No lumped load on a Unibus segment should contain more
than 20 ac unit loads unless the entire segment consists of one lumped load.
Rule No.4 (Skewed cable lengths) - If (a) a lumped load (called the "affected lumped load") has 2.59
m (8.5 ft) or longer cables connected to both bus in and bus out and (b) the sum of the ac unit loads in
the two lumped loads connected to the opposite ends of the cables exceeds 18, or (c) the sum of the ac
unit loads in the two semi-lumped loads connected to the opposite ends of the cables exceeds 36, then
the lengths of these cables should differ by 1.52 m (5 ft) or more with the longer cable being on the end
with the greatest number of ac unit loads (if there is a practical choice).

2-7

Rule No.5 (Skewed cable lengths, supplement) - If the length of one of the cables connected to the
affected lumped load in Rule No.4 must be increased because of that rule, then the longer cable should
have at its opposite end of the semi-lumped load with the greater number of ac unit loads. This rule
should be implemented only if it is practical to do so, i.e, in cases where its implementation will not
increase total cable length more than 1.52 m (5 ft).
Rule No.6 (Violation of Rules No.1 through No.5) - Rules No.1 through No.5 should not be
grossly violated. If a bus segment violates a rule slightly, and for practical reasons reconfiguring is
undesirable, then the segment must pass voltage-margin tests (a) when the system is originally configured and (b) when any Unibus element is added, deleted, or swapped (including the swapping of a
defective module or backplane).
Rule No.7 (System acceptance) - Even if rules No.1 through No.5 are implemented, all Unibus
segments of a system should be voltage margined after the system is configured.
2.3.1 Maximum Cable Length (Rule No.1)
If Rule No.1 is violated, (a) the dc drop across the bus, when driven at one end and received at the
other, may be excessive, and (b) far-end crosstalk may be excessive. In calculating lengths, the M920
should be considered as zero feet, the M9202 as 60.96 cm (2 ft), and the Be lIA-O as 15.24 cm (6 in).
If the length of a segment exceeds 15.24 m (50 ft), reconfiguring (changing the order of bus elements)
may reduce the length. If that fails, a DB11-A bus repeater will be necessary.
.
2.3.2 Maximum de Loading (Rule No.2)
If too many dc loads are put on a Unibus segment, the quiescent undriven voltage may be lowered to a
level where bus receivers become susceptible to reflections from lumped loads and the overall noise
margin on the high end (bus un driven) may become too small. DB11 bus repeaters should be used (as
required) to implement this rule.
2.3.3 Maximum Lumped Loading (Rule No.3)
If a lumped load is too large, it may generate a reflection on the Unibus large enough to create a false
logic signal and cause a failure (see Figures 2-5 and 2-6). M9202 folded cables (or BC11A-2s, if M9202
is unavailable) should be used in place of M920s in order to separate large lumped loads. The effect of
the M9202 is to cause the peak reflections from the lumped loads it separates to occur at slightly
different times. The following examples (see Figures 2-7 and 2-8) illustrate implementation of Rule No.
3.

+5V

178n
LUMPED LOAD
BCllA-15

383(l

I
L

WITH 40 AC
UNIT LOADS

I
I

___ .J

Figure 2-5

Rule No.3 Violation (Block Diagram)

2-8

The system shown in Figure 2-5 violates Rule No.3. When the driver in the affected bus element
unasserts the bus, the receiver in that element will see the following waveform:

+
(DRIVER WAVEFORM)

v
(NET WAVEFORM
AT RECEIVER)

(REFLECTION
FROM LUMPED
LOAD)

CP-2566

Figure 2-6

Rule No.3 Violation (Waveform Example)

The reflection may cause the threshold of the 8640 receiver to be crossed a second time, and a failure
may result. To implement Rule No.3, the lumped load must be split into two equal loads by adding an
M9202 in place of an M920 (see Figure 2-7).

AFFECTED ELEMENT

+ 5V
17811
LUMPED LOAD
WITH 20 AC
UNIT LOADS

LUMPED LOAD
WITH 20AC
UNIT LOADS

383 II

CP-2567

Figure 2-7

Rule No.3 Implementation (Block Diagram)

2-9

The conditions to satisfy Rule No.3 are now implemented. When the driver in the affected bus element
unasserts the bus, the receiver in that element will see the following waveform (Figure 2-8).

+
(DRIVER WAVEFORM)

(NET WAVEFORM
AT RECEIVER)

(REFLECTION
OF TWO LUMPED
LOADS)

CP-256B

Figure 2-8

Rule No.3 Implementation (Waveform Example)

Now the 8640 threshold is not crossed and the danger of a failure is reduced.
Rule No.3 states that there is no limit to the number of ac unit loads on a Unibus segment (unless the
entire segment consists of one lumped load). The reason for this statement is that there is no 120 ohm
cable in the segment on which reflections can travel. The following segment (Figure 2-9) is an example.

I
I

DL11-A

DLll-A

DL11-A

DL 11-A

DL11-A

DLll-A

I
~
I

I
I

;1
LUMPED LOt.D

UNIBUS SEGMENT

1
CP·2569

Figure 2-9

Multiple Bus System Example

2-10

This segment obeys all configuration rules. It has zero (0) feet of cable, 20 dc unit loads, and an
irrelevant number of ac loads. In this configuration none of the M920s have to be replaced by M9202s.
2.3.4 Skewed Cable Lengths (Rule No.4)
There may be several ways to implement Rule No.4. Consider the following bus segment(Figure2-1O).

LUMPED LOAD
WITH 18 AC
UNIT LOADS

BC11A-10

AFFECTED
LUMPED
LOAD

BC11A-10

LUMPED LOAD
WITH 9 AC
UNIT LOADS

Cp·2619

Figure 2-10

Rule No.4 Violation (Block Diagram)

This segment violates Rule No.4 because the sum of the lumped loads that are connected to the
opposite ends of the cables exceed 18 unit loads. AC unit loads equal 27 (18 + 9 = 27) lumped at the
ends of the BC lIAs of equal length. One way to implement Rule No.4 is to increase the length of one
cable to 4.57 m (15 ft) (see Figure 2-11).

LUMPED LOAD
WITH 18AC
UNIT LOADS

AFFECTED
lUMPED
LOAD

LUMPED LOAD
WITH SAC
UNIT LOADS

CP-2570

Figure 2-11

Rule No.4 Implementation (Example A) Block Diagram

2-11

Another way is to split the lumped load on the left into two lumped loads using an M9202 (see Figure
2-12).

LUMPED LOAD
WITH 9AC

UNIT LOADS

AFFECTED
LUMPED
LOAD

LUMPED LOAD
WITH 9 AC
UNIT LOADS

SEMI-LUMPED LOAD WITH

SEMI-LUMPED
LOAD WITH
9 AC UNIT
LOADS

18 AC UNIT LOADS

Figure 2-12

Rule No.4 Implementation (Example B) Block Diagram

When this rule is violated and when a driver in the affected lumped load un asserts the bus, reflections
from the ends of its bus in and bus out cables will arrive at the affected lumped load simultaneously
and superimpose. The net reflection may cross the 8640 threshold and cause a failure (see Figure 2-13).

~ + -y-

I
I

)
DRIVER
WAVEFORM

REFLECTION
FROM END

REFLECTION

NET WAVEFORM

FROM END

AT AFFECTED

OF BUS OUT
CABLE

LUMPED LOAD

OF BUS IN
CABLE

Figure 2-13

Rule No.4 Violation (Waveform Example)

2-12

8640 THRESHOLD

When the rule is implemented by making the lengths of the bus in and bus out cables different, the
reflections will arrive at slightly different times (see Figure 2-14):

+ ----y--

-yI

:t1

1'2

REFLECTION
FROM END
OF BUS IN
CABLE

REFLECTION
FROM END
OF BUS OUT
CABLE

DRIVER
WAVEFORM

NET WAVEFORM
AT AFFECTED
LUMPED LOAD
CP-2573

Figure 2-14

Rule No.4 Implementation (Waveform Example)

Now the reflection does not cross the 8640 threshold and the danger of a failure is reduced.
The configuration in Figure 2-12 does not violate Rule No.4 because the sum of the ac unit loads
lumped at the ends of the BC11A-1O cables is 18 (9 + 9 = 18) and the sum of ac unit loads in the semilumped loads at the BC lIA-lO's ends of the cables is 9 plus the lumped loads (18) for a total of 27 unit
loads (9 + 18 = 27).
Either of these methods could be used to implement Rule No.4 but the second is more desirable in this
example because it minimizes the total cable length of the segment.
2.3.5 Skewed Cable Lengths, Supplement (Rule No.5)
To understand why this rule is necessary, consider the following example (Figure 2-15).

2-13

LUMPED LOAD
WITH 20 AC
UNIT LOADS

I
I

M9202

LUMPED LOAD
WITH 20AC
UNIT LOADS

\..

M9202

LUMPED LOAD
WITH 20AC
UNIT LDADS

I
I

)

'"
SEMI·LUMPED LOAD WITH 60
AC UNIT LOAD

CABLE #1
;;? 2.59 m 18.5 ft)

AFFECTED
LUMPED
LOAD

I
I

CABLE #2
;;? 2.59 m 18.5 tt)

LUMPED
WITH 20
AC UNIT
LOADS

~
SEMI·LUMP
LOAD WITH
20AC UNIT
LOADS

Figure 2-15

CP·2574

Skewed Cable Length Violation

Suppose that the length of cable no. 1 equals the length of cable no. 2. This violates Rule No.4. In this
case, the affected lumped load will see the following waveform (Figure 2-16) when its driver un asserts
the bus.

8140
THRESHOLD

+
I

-W-

\.._-~,,----~)

I t,
\.._--~-...r__- _ . . J )

\.~---~-----)

DRIVER
WAVEFORM

REFlECTION
FROM END OF

REFLECTION
FROM END OF
CABLE /12

CABLE #'

____ _____J
~

NET WAVEFORM
AT AFFECTED
LUMPED LOAD

CP·2575

Figure 2-16

Skewed Cable Length Violation (Waveform Example)

2-14

The reflection in this waveform crosses the 8640 threshold and may cause a failure. The best way to
implement Rule No.4 in this example is to increase the length of either cable no. 1 or cable no. 2 by
1.52 m (5 ft). Suppose the length of cable no. 2 is increased by 1.52 m (5 ft). (This violates Rule No.5
because this is the end with the smaller lumped load.) In this case, the affected lumped load will see the
following waveform (Figure 2-17) when its driver un asserts the bus.

+
I

~
I

\.'----~'-...r---~)
REFLECTION
FROM END
OF CABLE #2

REFLECTION
FROM END OF
CABLE #1

DRIVER
WAVEFORM

)

"-"
NET WAVEFORM
AT AFFECTED
LUMPED LOADS

CP-2576

Figure 2-17

Violation of Rule No.5 (Waveform Example)

The reflection in this waveform also crosses the 8640 threshold and may cause a failure.
Now suppose the length of cable no. 1 is increased by 1.52 m (5 ft) instead of cable no. 2. This will
implement Rule No.5 correctly. In this case, the affected lumped load will see the following waveform
(Figure 2-18) when its driver unasserts the bus.

+
I

~
I

-y

I
I t2
\.._ _~",,"___~J

\.'--_ _~'-"'~___)

\._-~'-...r,---.-')

REFLECTION
FROM END OF
CABLE #1

REFLECTION
FROM END OF
CABLE #2

NET WAVEFORM
AT AFFECTED
LUMPED LOAD

DRIVER
WAVEFORM

CP-2577

Figure 2-18

Implementation of Rule No.5 (Waveform Example)
2-15

The reflection from the ends of cables no. 1 and no. 2 do superimpose somewhat, but not much. As a
result, the 8640 threshold is not crossed.
2.3.6 Rule Violations (Rule No.6)
Rules No. 1 through No.5 should be implemented if possible. On rare occasions it may not be practical to do so. For example, the last bus segment on a system may exceed the 15.24 m (50 ft) maximum
length rule by 1.52 m (5 ft), and implementing Rule No. 1 may require another DBI1-A repeater,
which may require another BA11-ES expander box, which may require another H960 cabinet. In this
case, it is acceptable to violate Rule No.1, providing that the system is tagged so that Rule No.6 is
always followed when the system undergoes change or corrective maintenance. Common sense has to
be exercised if any of Rules No.1 through No.5 is violated.
The voltage margining procedure follows.
1.

Replace the two terminators of the segment (M930, M9300, M9301, M9302, M981) with the
appropriate low-margin cards (M9304, M9305).

Run complete diagnostics and system exercisers.

Replace the two low-margin cards by the. corresponding high-margin cards (M9304-Y A,
M9305-YA).

Run complete diagnostics and system exercisers.

Replace the two high-margin cards with the original terminators.

If any diagnostic or system exerciser fails during this procedure, the system has a problem. It may be
necessary to implement a rule violation in order to correct the problem. A Unibus voltage margining
tester box (Chapter 4) may be necessary to isolate the problem. To determine if there is a margin
problem, failures during margining must correspond with (or compared to) no failures when not
margining.

2.3.7 System Acceptance (Rule No.7)
On rare occasions, Rules No.1 through No.5 may not be sufficient to eliminate all reflection problems. On these occasions, a Unibus voltage margin tester box (UVM-TA) should be used (along with
common sense) to isolate the problem and implement solutions. When an option fails (gives data
errors, hangs the bus, etc.) during a margining test, particularly the low-margining test, be suspicious
of reflections from surronding options after eliminating weak drivers, leaky receivers, etc. The solution
may be to replace an additional M920 in those surrounding options with an M9202 (or even a BC l1A3) in order to further spread out and reduce reflections. If Rules No.1 through No.5 do not eliminate
a reflection problem, please consult F.S.11 Product Support in Maynard.

2-16

2.3.8 Actual Bus Loading
PDP-II systems are configured to have no more than twenty loads or 15.24 m (50 ft) of Unibus cable
on a given bus. Most devices are specified in terms of whole number loads but in fact this is not always
the case. Table 2-1 lists realistic numbers for various options and using the system shown (Figure 2-19),
it is seen how loading may differ from that determined by conventional configuration guidelines.
NOTE
If quiescent voltages are correct, then dc loading is

probably not a problem.

11/40
CPU

[

BM
873

KW11P

DLl1

MF11
(48K)

RK11

TM11

DH11

CR11

LP11

BUS LOADS
CONVENTIONAL

ACTUAL (380 RECEIVERS!

23.2

ACTUAL (8640 RECEIVERS!

16.7

Cp·2578

Figure 2-19

Actual Bus Loads Example

Caution must be exercised in customer situations - the published loading specifications for each device
(as listed in Appendix D) must be used in discussions with non-DEC personnel. Table 2-1 is included
only for your information. (Refer to Chapter 3, Paragraph 3.3)

2-17

Table 2-1

Realistic Load Values

Option

No. of
Drivers

Driver
Type

No. of
Rcvrs

Max. No.
unit
loads if
Rcvrs
are 380s

AAIIA
AAI1B
AA11C
AA11D
AAllE
AD01
AFeil
BM792Y
BM873
CB11
COlI
CM11
CRll
DAllB
DAIIF
DBI1A
DCll
DHII
DJll
DKII
DLll
DMllBB
DNII
DPll
DRIIA
DRllB
DRIIC
DT03F
DXll
GT40
KEI1A
KGll
KWIIL
KWI1P
LCIIA
LPII
LPSII
LS 11
LV11
M792
MEll
MF11
MM11

5
5
5
5
5
3
2
I
0
2·
3
4
4
2
2
1
3
1
2
2
4
2
2
3
4
2
4
2
2
3
1
2
1
3
4
2
2
2
2
1
1
1
1

8881
8881
8881
8881
8881
8881
8881
8881
NONE
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
74HOl-1
74HOl-1
74HOl-l

2
2
2
2
2
1
1
1
2
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1

1.52
1.52
1.52
1.52
1.52
1.119
1
.8809
1.523
1
1.119
1.238
1.238
1
1
.8809
1.119
2.404
1
1
1.238
1
1
1.119
1.238
1
1.238
1
1
1.119
.8809
1
.8809
1.119
1.238
1
1.52
1
1
.8809
1.952
1.952
1.952

2-18

Max. No.

I unit
loads if

Rcvrs
are 8640s
.76
.76
.76
.76
.76
.7380
.6190
.5
.7619
.6190
.7380
.8571
.8571
.6190
.6190
.5
.7380
1.261
.6190
.6190
.8571
.6190
.6190
.7380
.8571
.6190
.8571
.6190
.6190
.7380
.5
.6190
.5
.7380
.8571
.6190
.76
.6190
.6190
.5
1.571
1.571
1.571

Table 2-1

Realistic Load Values (Cont)

Option

No. of
Drivers

Driver
Type

No. of
Rcus

Max. No.
unit
loads if
Rcvrs
are 380s

MRII
MSII
PCl1
PR11
RCl1
RFl1
RKI1C
RK11D
RPII
TAll
TCII
TMll
UDCII

1
2
4
4
3
2
2
2
2
3
2
2

8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881
8881

1
1
1
1
1
1
1
1
1
1
1
1
2

.8809
1
1.238
1.238
1.119
1
1
1
1
1.119
1
1
1.52

Max. No.
unit
loads if
Rcvrs
are 8640s
.5
.6190
.8571
.8571
.7380
.6190
.6190
.6190
.6190
.7380
.6190
.6190
.76

2.4 UNIBUS LATENCY
This section is designed to familiarize the Field Service Engineer with the recommended NPR Device
Sequence on the Unibus and also provide the ability to determine and minimize possible "Data Late"
errors.
The device sequences for a given PDP-ll System (CPU, memories, and devices) can be obtained by
applying the algorithm given in Figure 2-20 and Table 2-2.

Table 2-2 Maximum NPR Rates of the NPR
Devices with Variable Speed
Device

Maximum Data
Transfer Rate

Maximum
NPRRate

CDII-E
CDll-A
DAll-B/DRII-B
DHII
DQII-DA
DQII-EA
GT40

1000 card/min
1200 card / min
500,000 word/s
16 X 9600 Baud
10,000 Baud
1 Megabaud
20,us/point

1.33 kHz
1.6 kHz
500 kHz
15.4 kHz
1kHz
100 kHz
50kHz

2-19

NPR DEVICE SEQUENCE ON UNIBUS
CPU
MEMORY

GIVEN:
CPU, MEMORIES,
AND OEVICES IN

> 90 KHz (NPR RATES)

RK11iRK05 (90 KHz)

90 KHz> 36 KHz

NO
TM11/TU10 (36 KHz)

YES
~ 36 KHz>

5 KHz

YES

TC11/TU56 (5 KHz)

MAXIMUM
XFER RATE FROM
NPR SEQUENCE
CHART

5 KHz> 1.7 KHz

RJS04 (T1 = B71's)

NO
RJ P04 jT1

= 1321's)

RK611/RK06 (T1

= 2121's)

RJS03 (41's/wd)(T1

= 2311's)

RP11C/RP03 (T1

= 463"s)

RJS03 (S"s/wd) (T1 /487"s)

TJ U45 (T1

TJU16 (T1

= 900"s)
= 1B01"s)

RF11/RS11 (T1

PLACE DEVICE I
IN ORDER OF
INCREASING T1
VALUES (BEFORE
ANY CATEGORY 1
DEVICES WHOSE
NPR RATE IS
LESS THAN
1.7 KHz
(SEE TEXT)

ORDER OF
DECREASING NPR
RATES AFTER
CATEGORY 2
OEVICES (SEE
TEXT)

NPR RATES
BEFORE
CATEGORY 2
DEVICES (SEE
TEXT) ••••

= 100 ms)

1.7 KHz
DH11

DB11·A

~DH11

Figure 2-20 Algorithm To Determine NPR Sequence (Sheet 1 of 2)
2-20

ADD A BUS
REPEATER AT
THE END IF NOT
ALREADY ADDED

DEVICE· •
BEFORE THE
LAST BUS
REPEATER TO
IMMEDIATELY
AFTER IT.

HIGHEST BANK
OF CORE
MEMORY
BEFORE THE LAST
REPEATER TO
IMMEDIATELY
AFTER IT

• If only one BUS REPEATER, this means betwB6n the CPU and the BUS REPEATER .

•• Or the le8st frequently used category 1 device .
••• Tl = Maximum tolerance between bus cycles
****Except asyncheonous communication devices
(e. g., DH11 , which have great latency tolerance
capacity. DH11 can be placed in rear of all
other devices.
NOTES,
1.

Throughput is conditional and is well studied at the CPU. I/O bandwidth is more
difficult to determine but has been investigated by Engineering.

SR device can Ue put behind repeaters or behind NPA device. SR device should be
placed in front of asynchronous devices. (i.e, NPR11 - DMC11. DVM11 DC11)177

CP·2686

Figure 2-20 Algorithm To Determine NPR Sequence (Sheet 2 of 2)
2-21

Using the procedure outlined in Figure 2-20 and the maximum NPR rates specified in Table 2-2, the
following steps should be used to approach a DATA LATE problem.
1.

Determine the correct sequence of devices on the Unibus. If the configuration is incorrect,
correct it.

Determine from the configuration tables whether or not the system is expected to experience
DLTs due to Unibus bandwidth (refer to Figure 2-24).

If the system is not expected to experience DLTs but nevertheless does, isolate the hardware
malfunction with the bus busy measurement technique.
In some cases, it may be useful to apply the Bus Busy measurement technique to systems
which may experience Data Lates due to Unibus bandwidth. In such instances, the technique helps to demonstrate that the hardware is functioning correctly.
NOTE
For the purposes of this manual, bandwidth is defined
as the number of bus cycles that can be accommodated and stilI provide successful execution of the
application software.

2.4.1 Device Categories
All existing NPR devices that are connected to the Unibus are considered to be in one of the two
defined categories. Note the fact that all communication devices are considered to be in category 1
classification even though some devices have data buffers of more than six words (usually, these
devices multiplex more than one line).
Category 1 - Devices whose controllers have six or fewer words of data buffer (excluding
RFII/RSII which, although it has only a one-word data buffer, falls more closely into
category 2 simply because it can wait for a maximum of three disk revolution time or 100 ms
without getting "data late" errors). Other devices in this category are: CD 11, DAll, DH 11,
DQll, DRII, GT40, RKII/RK05, TMII/TUlO, and TCll/TU56.
Category 2 - Devices whose controllers have more than six words of data buffer (including
RFll/RSII as described under category I). Devices included in this category are: RJS04,
RJP04, RK6II/RK06, RJS03, RPIIC/RP03, TJU45, TJU 16, and RFll/RSl1.
2.4.2 NPR Calculations for T1
NPR rates of category 1 devices can be computed in one of the following ways.
NPR RATE = baud rate /10 (may be different for different devices), or

= word/s, or
= card/min X 1.33
Within Category 1, devices with higher NPR rates should be placed before devices with lower NPR
rates.

2-22

2.4.3 Latency Tolerance Calculations*
The process of determining category 2 device sequence can be simplified by comparing T1 (maximum
tolerance between bus cycles) of each device, which can be computed as follows:

Tl = TDBS - TBBLUP X 2
where: TDBS
= Time to transfer DBS words to/from the device (in J.Ls)
DBS
= Data buffer size of the device controller (for RHl1, DBS = 66)
TBBLUP = Typical data bubble up time of the device controller (for RHll, TBBLUP = 16
J.Ls)

Please note the following information carefully.
1.

If the sector size of a device is larger than DBS, TDBS is simply the product of the
instantaneous data transfer rate of the device and the DBS of the device controller. For
example, the sector size of RP04 is 256 words (DBS = 66 words), and the instantaneous data
transfer rate is 2.48 J.Ls/word, so TDBS = 2.48 X 66 = 164 J.LS.

If the sector size of a device is smaller than DBS, the sector gap and interleaved sector and
gap (if any) must be accounted for to compute TDBS. The situation can be clarified better
with the examples that follow. RS03 has sectors of 64 words, sector gaps of 25.6 J.LS and an
instantaneous data transfer rate of 3.6 J.Ls/word. Its DB (or silo) has two more words than a
sector; therefore, two words must be gotten to/from the next sector.

Sector-noninterleaved (4Is/wd): TDBS = 3.6 X 64 + 25.6 + 3.6 X 2 = 263 J.LS
Sector-interleaved (8 J.Ls/wd): TDBS = (3.6 X 64 + 25.6) X 2 + 3.6 X 2 = 519 J.LS
NOTE
Within category 2, devices with greater TI should be
placed after devices with smaller TI. All category 2
devices should be placed before category I devices
with NPR rate less than 1.7 kHz, except for asynchronous communication devices (e.g., DHll) which
have great latency tolerance capacity. DHll can be
placed in rear of all other devices.
2.4.4 BR Devices
All the BR devices should be placed after NPR devices. However, sometimes for convenience sake
some BR devices may be put before NPR devices (e.g., a DECwriter may be placed next to the CPU).
2.4.5

Unibus Loading Rules

Maximum loading before the first bus repeater is 19 dc bus loads; between two adjacent bus
repeaters is 18 dc bus loads.

Maximum Unibus cable length between the first bus repeater and the CPU or between the
adjacent bus repeaters is 15.24 m (50 ft). For example, configure a system with 11/45, 128K
of MFII-UP, DL11-A/LA30, KWII-L, RKII/RK05, RJS04, RJP04, DHll, DQII-EA (at
I2.5K baud), RFII/RSIl, TJU16, GT40, CDIt-E.

*Latency tolerance capacities of devices in category 2 are defined and computed using "Latency Tolerance
Capacities of NPR Controllers/Devices and Configuration Guidelines". 4/23/75.

2-23

After going through Figure 2-20 and Table 2-2, the following sequence results.
Device

Unibus Loads

11/45
KWII-L
DL11A/LA30
128K MFII-UP
RKII/RK05 (90 kHz)
GT40 (50 kHz)
RJS04
RJP04
TJU16
RFll/RSll
DHll (15.4 kHz)
CD ll-E (1.33 kHz)
DQII-EA (1.25 kHz)
TOTAL

2
1
1

8
1

1
1
1
1
1

2
1
_1_
22 UNIT LOADS

There are a total of 22 unit loads. Therefore, a DBI1-A is added at the end and DHll, DQII-EA and
CDII-E are repositioned after DBI1-A.
NOTE
The NPR device sequence algorithm does not take
into 'account the measures of the usage of the devices.
For example, suppose that in the system given above
GT 40 is seldom used. GT 40 may be placed behind
RFll/RSll to improve system throughput.
2.5 BUS BUSY TEST TECHNIQUES
The following description is designed to aid in determining "nominal" device bus busy times for PDP-II
system configurations. It is intended for use in cases where a system under test is configured correctly,
but is still incurring Unibus "Data Late" errors.
Almost every PDP-II I/O device, transferring data at the NPR level, has a period of time in which a
word or byte of data can remain in its data buffer before the next incoming word displaces it. This
period of time is known as a device's latency. If, during this period of time, the device is unable to
complete a Unibus transfer, the word in the data buffer will be displaced and lost. A data late error will
result and the transfer operation must be aborted and restarted. This is obviously an undesirable
condition.
Latency, or Data Late, errors may occur as a result of many factors, e.g., device and memory types,
Unibus configurations, software in use, and hardware malfunction. This document will address hardware malfunctions.
2.5.1 Bus Busy and Latency Tolerance
In many instances stand-alone diagnostics and system exercisers will provide sufficient information to
allow the problem to be identified and isolated. This generally leads to a traditional troubleshooting
approach.

2-24

Sometimes, however, the malfunction will be more subtle, eluding even the most rigorous diagnostics.
In the past, large devices were slow (by today's standards) and there was little concern about how long
a device took to complete a transaction on the Unibus. As systems have expanded in size and devices
have become faster and software more stringent in its I/O demands, the need for NPR devices to
complete their transactions and release the Unibus to another device as soon as possible has become
im perative.
If an NPR device holds BBSY asserted on the Unibus for an abnormally long period of time, that
device (in some configurations) could "crowd out" another NPR device competing for Unibus time
forcing an error condition to occur. It should be evident, then, that Data Lates being reported by one
device may be caused by another device on the system being a "bus hog".
The following paragraphs will show how to predict nominal BBSY time for a given configuration and
how to measure the actual BBSY times. Guidelines are included to help determine whether or not the
measured BBSY times fall within an acceptable range around the predicted value.
2.5.2

Calculating Nominal Bus Busy Times
NOTE
It doesn't matter if the calculations necessary to predict a BBSY time are performed first or if the measurements are made first. In some cases however it is
necessary to determine if a device is conducting
"single cycle" or "double cycle" transactions, as this
will affect the calculations that must be made. This
will be true of some Massbus devices (RHll). If in
doubt, proceed to Paragraph 2.4.3 and make this
determination.

This section deals with calculating or predicting a BBSY time for a device within a given configuration.
Component tolerances throughout the system make exact calculations impossible, but typically a
device should fall within a plus-or-minus 30 percent range of the predicted value. If, after measuring
the real BBSY time, it exceeds the predicted value by more than 30 percent, a potential problem area
has been found and steps should be taken to bring the offending device nearer to specification.
For the purposes of this manual, BBSY can be thought of as composing four separate components:
1.

Ddv
This is the internal timing delay ofthe device itself. The figure can be obtained from Table 2-

3.
2.

Dma
This is memory access time or the time it takes memory to assert SSYN after it sees MSYN.
This figure can be obtained from Table 2-4.

Dtr
This is the delay associated with Unibus transmitters and receivers. This figure may be
obtained from Table 2-5.

Dp
This is the propagation delay of the Unibus itself, taking into account its length and loading
properties. This must be calculated from a formula.

2-25

Table 2-3

Device Delay (Ddv)

Controller
Type

Ddv (in nanoseconds)
Single
Cycle

TC, TM, RPII-C, RKII-C, RFll
DHII
RK11-D
RHll 680

1100
1350
935
1355

Table 2-4

Double
Cycle

NjA
NjA
NjA

Memory Access Delay (Dma)

Memory
Type

Dma (in nanoseconds)
Single
Cycle

Double
Cycle

8K MFII-L
8K MFII-LP
16K MFII-U
16K MFII-UP
Other Core

365
430
375
460
410

730
860
740
920
820

Table 2-5

Transmitter/Receiver Delay (Dtr)

Transmitter /Receiver
Type

Dtr (in nanoseconds)
Single
Cycle

Double
Cycle

Dt 8881
Dt 8838
Dt380
Dt 8640

60
40
40
40

120
80
80
80

Single Cycle = Dp = (3.4 X UL) + (3.5 X de unit loads)
Double Cycle = Dp = (6.8 X UL) + (7 X de unit loads)

2-26

The summation of these four components yields a BBSY value unique to particular device and
configuration.
BBSY = Ddv + Dma + Dtr + Dp
The first three components of the formula (Ddv, Dma and Dtr) are easily obtained by referring to the
referenced tables. Locate in the table the appropriate device, memory type or transmitter jreceiver type
and extract the number from either the "single cycle" or "double cycle" column as it pertains to the
device. Determining "single cycle" or "double cycle" is explained in Paragraph 2.5.3.
The fourth component of the formula (Dp) may be derived in the following manner.
Single Cycle
Dp = (3.4 X Ul) + (3.5 X dc unit loads)
or
Dp = (6.8 X Ul) + (7 X dc unit loads)

Double Cycle

where:
UI = Unibus length in meters (feet) between the device and memory
DC Unit Loads = the number of DC Unit Loads between the devices and memory, including the dc
unit loads presented by memory itself.
To illustrate this, look at the sam pIe configuration shown in Figure 2-21. If the device under test were
the RKII-D the value of U 1 would be 60.96 cm (2 ft) and the dc unit loads would be 3 (1 dc unit load
for each 16K bank of memory). If the device under test were the TM11, Ul would equal 2.13 m (7 ft)
and dc unit loads would equal 4.
NOTE
If the device under test is located behind one or more
DRll bus repeaters add 375 ns (for devices doing
"single cycle" transfers) or 750 ns (for devices doing
"double cycle" transfers) to the calculations for each
bus repeater between the device and memory.
2.5.3 Measuring Bus Busy Times
A dual-trace oscilloscope with three probes will be needed to conduct the following tests. The third
probe will be used to monitor MSYN in order to determine if some of the NPR devices (such as
RH lIs) are doing "double cycle" transactions. If it is certain that all the devices to be tested will be
conducting "single cycle" transfers only, the third probe may be eliminated and all calculations will be
made from figures extracted from the "single cycle" columns in Tables 2-3, 2-4, and 2-5.

2-27

60.96 em (2 ttl

RHll

MFll-U

I0-16K

1S-32K

SPC & PCll

MFll-U

EIS

RKll-0

FIS

1-------1

KT11

I-

RPll-C

I--

0
r

----,

L _ _ _ _ -l

RS04
I

____ ---J

L ____

TM1.l

32-48K

KWll-L

UNIBUS

1.52 m (5 ftl

2.43 m (8 ttl

1.52 m (5 ftl

I
I
L _____ J

I
L

__ -

- J

L _ _ _ _ --J
KOll

CP-2683

Figure 2-21

Unibus Length Between Device and Memory

Set up the oscilloscope as follows:
Coupling = dc
Trigger = External positive
Mode = Alternate
Vols/Div = .1 (with XIO probes)
Time/Div = .5 microseconds.
Now locate a convenient access to the Unibus. The TCII (DECtape) is a good access point if available,
otherwise any backplane with Unibus-in or Unibus-out will do.
Connect the probe corresponding to external trigger to SACK L at pin AR2.
Connect the probe corresponding to channell to BBSY L at pin AP2.
Connect the probe corresponding to channel 2 to MSYN L at pin BVI.
The software to be run during these tests will be DEC/XIl. Before proceeding, note that Table 2-4
(Dma) doesn't include data on MOS or bi-polar memory systems. For this reason, ensure that
DEC/XII doesn't use MOS or bi-polar as write buffer space. If the system under test is an all core
system this will not be of any concern. If the system does include MOS or bi-polar it will be necessary
to lock the run-time exerciser in memory (via the RUNL command) so that the beginning of
DEC/Xl Is write buffer space (which coincides with the last address + 2 or the last module) is in core.
It is acceptable if the DEC/X 11 code exercises from MOS or bi-polar as long as the write buffer space
is in core. Finally, inhibit write buffer rotation via the ROTOFF command.

2-28

Before issuing the RUNL command, DESelect all modules and SELect the module corresponding to
the first device to be tested.
NOTE
By testing only one device at a time and by triggering
the scope from SACK, it is ensured that the signals
seen will be those issued by the device under test.
Once DECjX 11 has been started and the scope trigger has been properly adjusted, the brace should
correspond to one of the two figures shown in Figures 2-22 and 2-23. Figure 2-22 shows a device doing
single-cycle transaction, and Figure 2-23 shows a device performing double cycle transactions.
The key here is the channel 2 trace displaying MSYN. If MSYN is seen being asserted once during the
BBSY time displayed on channell, the device is performing single-cycle transfers and the "single
cycle" column in Tables 2-3, 2-4 and 2-5 should be used. If MSYN is seen being asserted twice during
the BBSY time the device is performing double cycles and the "double cycle" column in the tables
should be used for the calculations on that device.
The BBSY time being displayed on channell is the time to be ultimately concerned with. This is the
value that should coincide (plus-or-minus 30 percent) with the calculated value.
Once the measurements have been taken for a device, issue a control C from the keyboard to stop the
run-time exerciser. When DECjXll is ready to accept new commands DESelect the device just tested
and SELect the module corresponding to the next device to be tested and repeat these procedures until
all NPR devices on the system have been measured.

"I.~~- BBSY TIME -~----t~

CHANNEL 1

CHANNEL2

CP-2684

MSYN

Figure 2-22

Single-Cycle Transaction

2-29

1+1"---

BBSY TIME

---<!>I"I

CHANNEL 1

CHANNEL 2

1st MSYN

Figure 2-23

2nd MSYN

CP-2685

Double-Cycle Transaction

2.5.4 Configuration" Tables
The configuration table (Figure 2-24) is presented here to familiarize the user with Data Late (DLT)
occurrence possibilities of some common PDP-II systems. No attempt is made in this manual to cover
all possible configurations because of the complexity of the problems that could be encountered.
In all configurations, the general rules are:
1.

If a configuration runs DLT-free, then a subset of the configuration should also run DLTfree.

If a configuration runs with DLT, adding more devices to the system should also give DLT.

2-30

8Knp'

16Knp

8Kp**

16Kp

1. RK11D·TC11·RJS04·RPllC-T JU16·1~4DH11

2. RK11D·TC11·RJP04-RP11C·TJU16·1~4DH11

3. RK11D-TC11·RJP04·RJS03(8Ms)·T JU16·1 ~4DH11

4. RK11D·TM11·TC11·RJS03(4Ms)·RP11C·1 ~4DH11

RK11D·TC11·RJS03(4Ms)·RP11C·TJU16·1~4DH11

6. RK11D·TM11·TC11·RP11C·RJS03(8Ms)·1 ~4DH11

RK11D·TC11·RP11C·RJS03(8Ms)·1~4DH11

RJS04-RJP04·RP11C

RJP04·RJS03(4Ms)·RP11 C

DL T -Free region. The configurations that
*8Knp = non-parity memory

fall in this region should run without

DL T errors when all devices are
transferring data to/from the main memory
simultaneously.

**8Kp = parity memory

DL T region. The configurations that fall
in this region will give us DL Terrors
when all devices are transferring data to/
from the main memory simultaneously.

Cp·2776

Figure 2-24

DLT Configurations

2-31

CHAPTER 3
TROUBLESHOOTING

3.1 GENERAL
This section is designed to aid in isolating and troubleshooting Unibus failures. The Unibus Troubleshooting Flowchart (Figure 3-1) is designed to provide a step-by-step procedure for checking and
correcting Unibus problems. The flowchart references chapters and paragraphs (which contain additional information and possible solutions to solve Unibus problems) are included for reference.
3.2 TIMING CONSIDERATIONS*
Some system failures such as address errors, missing data, illegal traps and system halts can occur
because of bus timing relationships.
3.2.1 DATO-DATOB
The Unibus specification states that MSYN must be asserted 150 ns (minimum) after the address,
control, and data (for DATO and DATOB transactions). This delay includes 75 ns to allow internal
logic in the slave device to decode the address. If MSYN is asserted before 150 ns, insufficient deskew
and signal decoding at the slave may result in errors. An 8881 driver and an 8640 receiver combination
can cause up to 60 ns of skew leaving as little as 15 ns as the allowable skew because of the Unibus
transmission media. The most timing-sensitive lines have been found to be BBSY, MSYN, SSYN and
INTR. Cable length and configuration can be a noticeable factor in these lines.
3.2.2 DATI-DATIP
For a DATI or DATIP operation, the slave puts requested data on the D lines and then asserts SSYN.
The slave should not assert SSYN at the driver input before the data and enable lines are valid at the
data driver inputs. The critical point seems to be around 35-40 ns skew in SSYN vs. DATA at which
point it is possible for high-speed systems (such as the 11/45 which allows only the 75 ns maximum
skew) to clock in erroneous data.

Some memories have a potential problem with this timing relationship in certain systems. When a
system is upgraded from an 11/05 or 11/20 to an 11/45 or when more of this memory is added in an
extended cabinet by a longer Unibus cable, the risk factor for problems becomes greater. If problems
are experienced with these memories (MM ll-L, MMll-S, MMll-E, MM ll-F) in high-speed systems,
consult F.S. Product Support.

*Refer to the 1975 Peripherals Handbook for Unibus timing information.

3-1

INSTALL FOAM
ON UNIBUS
CABLES
(SEE APPENDIX A)
NO

TERMINATE
GRANT LINES
WITH PROPER
PULL-UP RESISTORS
(SEE APPENDIX A)

ISOLATE SOURCE
OF PROBLEM
(BREAK BUS
SEGMENTS
AND TERMINATE
SUCCESSIVELY
SMALLER
SECTORS
OF THE UNIBUS

REFER TO
SECTION
2 FOR SYSTEM
CONFIGURATION
RULES - IF
CHANGES
ARE MADE
RETURN TOG)

WHILE
MONITORING
THE QUIESCENT
LEVEL ON THE
BAD LINE)

A
TERMINATORS.
SHORTS
ANDIOR OPENS
ON THE
UNIBUS RESOLVE THE
PROBLEM
BEFORE
CONTINUING

A
CP-2584

Figure 3-1

Unibus Troubleshooting Flowchart (Sheet 1 of 3)
3-2

OBTAIN
HI/LO

REGIONAL
OFFICE

SINGLE-ENDED
MARGINING
CARDS FROM
REGIONAL
OFFICE.

OBTAIN
UVM-TA TESTER
BOX FROM
REGIONAL
OFFICE.

1. DOULBLE
CHECK THE
QUIESCENT
VALUES.
2. TRY REPLACING
380 RECEIVERS

REFER TO
SECTION 4
AND PERFORM

HI/LO
TERMINATOR
TEST.

REFER TO
SECTION
4 AND PERFORM
SINGLE-ENDED
MARGINING
TEST.

THE QUIESCENT
VALUES
2. TRY REPLACING
THE 3BO
RECEIVERS
WITH 8640'S
3. YOU MAY
HAVE TO OBTAIN
UVM-TA FROM

WITH B640'S
3. POSSIBLE
CAUSE IS
REFLECTION
ON UNIBUS OR
MARGINAL
RECEIVER (TRY

YES

OFFICE

INSTALLING A
M9202-2
OR A MARGINAL
BUS RECEIVER
(TRY INSTALLING
AN M9202-2
BUS JUMPER

BUS SEGMENTS

SECTION 2
FOR SYSTEM
CONFIGURATION
RULES - IF
CHANGES MADE
RETURN TOeA)

Figure 3-1

IF MULTIPLE
BUS SYSTEM,
REPEAT HI/LO
MARGIN TEST
FOR REMAINING

Unibus Troubleshooting Flowchart (Sheet 2 of 3)

3-3

FIND CRITICAL
LINE OR LINES.

OBTAIN
UVM-TA TESTER
BOX FROM
REGIONAL
OFFICE

(START WITH
MSYN, SSYN,
INTR, SACK
AND BBSY) IF
PROBLEM NOT
HERE TRY
OTHER SECTIONS

REFER TO
SECTION 4
AND PERFORM
UVM-TA
MARGINING

OF THE BUS.
1. LOW BYTE
DATA
2. ADDRESS AND
CLINES
3. REQUEST LINES
4. HIGH BYTE
DATA

FIND THE
CRITICAL
DEVICE AND
REPAIR IT.
(POSSIBLY
REPLACE THE
BUS RECEIVER
AND/OR DRIVER
ON THE FAILING

UVM-TA
MARGINING
WILL NOT
HELP AT THIS
TIME.
DISCONNECT
UVM-TA AND
REPLACE
SYSTEM
TERMINATORS.
(RETURN TO
START)

LINE)
START AT
POINT WHERE
SYSTEM
OPERATES AND
SLOWLY ADJUST
TERMINATOR
VOLTAGE
UNTIL FAILURE
OCCURS (RANGE
OF 4.2 TO 7V)

AND SLOWLY
DECREASE
TERMINATOR
VOLTAGE UNTIL
FAILURE

MARGIN BOX
AND REPLACE
SYSTEM
TERMINATORS

REPEAT FOR
ALL OTHER
BUS SEGMENTS

CP-2603

Figure 3-1

Unibus Troubleshooting Flowchart (Sheet 3 of 3)

3-4

3.2.3 Interrupt Transactions
A typical 11/45 system will experience problems if the data lags the INTR line on the cable by more
than 30-40 ns. Most DEC interfaces assert the vector address and INTR at exactly the same time and
Unibus skew times may cause a timing problem if the bus is long. Experiments with a typical system
show the vector address lagging INTR on the cable by as much as 30 ns with 9.14 m (30 ft) of Unibus
cable and a TC11 or 45 ns with 9.44 m (31 ft) of bus and a DLll. The electrical configuration rules as
listed in Chapter 2 will minimize these problems when properly applied.
3.2.4 High-Frequency Cable Losses
The increase in transmission line conductor resistance at high frequencies, known as skin effect, may
be a factor in bus analysis. This function exhibits a very fast rise time to 50 percent of the input, but a
very slow dribble up from 50 percent to 90 percent of the input.
A 15.24 m (50 ft) bus cable could theoretically have a dribble up noticeable for up to 170 ns in response

to a step function at the input.
The bus should, therefore, be kept as short as possible to avoid potential timing problems. The published (i.e., allowable) Unibus length is 15.24 m (50 ft), but it is desirable to use as little cable as
possible for a given configuration (see Figure 3-2). Devices should be physically arrangecf in the same
order as they are electrically connected, if possible. (If M9202 folded cables are needed due to physical
arrangement, they should not be replaced by M920s in order to decrease bus length.)

CABINET

I
I
I
I

CABINET

I
THIS

NOT THIS

CP-2587

Figure 3-2

System Cabling Configuration Example

3-5

3.2.5 Peripheral Data Rate
It is possible to support only a certain rate of data transfer on the Unibus - beyond this rate, data late
situations will occur. A method for roughly determining permissible combinations of simultaneous
peripheral device activity (such as would occur when executing DECX11) follows.
1.

Determine a window for a given system based on the slowest NPR device transfer rate (,us).4
If you have an RK11, RPll, TM 11 and TC11, the slowest device will be the TCll with a
transfer rate of 200 ,us/word.
Window = 200,us (in this case)

Determine how many transfers the faster devices will perform in the window time.
(Window Time)/(Transfer Rate)
RK 11 (11.1 ,us/word)
TM11 (27.7 ,us/word)
RP11 (7.5 ,us/word)

200/11.1 = 18.02
200/27.7 = 7.22
200/7.5 = 26.66

Calculate the total number of transfers occurring within the window.
TC11 = 1
RK11 = 18.02
RPll = 26.66
TMll = 7.22
Total = 52.90 transfers will occur within 200 ,us window.

Calculate the time per transfer by dividing the total number of transfers into the window
time.
200 +- 52.9 = 3.78 ,us/transfer rate

If this figure is greater than 2.5 ,us*, the system should run without data lates: (This is approximately a
rate of 400 kHz.)
3.3 PROPAGATION DELAY
If a voltage is supplied between any two conductors, they may be c~.msidered as a transmission line.
The ideal transmission line input impedance looks like pure resistance but, in fact, is mainly a combination of capacitance and inductance (see Figure 3-3).
When the voltage at one end of the transmission line is changed, that change does not instantaneously
appear at the other end. There is some delay, which is called propagation delay (see Figure 3-4). The
propagation delay of BCll Unibus cable is approximately 1.4 to 1.9 ns per foot (or .0348 m).

*Bus repeaters and bus switches will decrease the data rate supportable on the bus. A figure of 3.0 may be more
applicable on a repeated line.

3-6

T
CP-2588

Figure 3-3 Transmission Line Circuit Example

1.....1 - - - - - - - - - 1 5 . 2 4 m (50 ttl BCll CABLE ---------I1~
(BI

(AI

Pd
PROPAGATION

-I

TIME

DELAY

•
CP-2589

Figure 3-4 BCll-A Unibus Cable Delay Example

3-7

A lossless transmission line of infinite length looks like a pure resistance of value Z = L/C. If such a
line is broken and terminated with a resistor of this value (R = Z), the line will behave like an infinitely
long line, i.e., appear resistive (see Figure 3-5). The impedance (Z) of Unibus BC 11 cable is approximately 120 ohms with Unibus foam and as low as 60-80 ohms unfoamed.

Z = 120n

R (TERMINATION)

CP-2590

Figure 3-5

BC 11 Unibus Cable Impedance Example

When a voltage is applied to the line, the instantaneous power consumed will be:
P = E2/Z

P = E2/120

Suppose now that the terminating resistor (R) is not equal to the characteristic impedance of the line.
The power which is traveling down the line before it reaches the termination (during propagation
delay) is equal to E2 /Z, but the power dissipated in the resistor after propagation delay is approximately equal to E2 /R.
If resistance (R) is greater than the impedance (Z), there will be extra energy available at the termination and since energy cannot simply disappear, it will be reflected back into the line. After one more
propagation delay (for the return journey), this reflection will be seen back at the source (see Figure 36A).

3-8

(A)

(SOURCE)

(6)

I
I
I

(TERMINATION)

I
I
I

I
I

~ Pd, --.I.-- Pd, ~ Pd, ---J.- Pd. --+l4- Pd,--+i
I

CP-2591

Figure 3-6

Impedance Mismatch Example

Some of this reflection will be dissipated by the source impedance and some will be re-reflected back
into the line. When this re-reflection is seen at the termination (Figure 3-6B), (after still another propagation delay), the energy difference will be reflected back to the source. Eventually both source and
termination will arrive at the same level. The important point to note here is that what was intended to
be a level change with a clean transition did not turn out that way on the line due to a termination
mismatch between Rand Z.
Essentially the same situation occurs when the termination resistor is smaller than the characteristic
impedance of the line. If resistance (R) is less than impedance (Z), there will be a mismatch and this
will also be reflected back to the source (see Figure 3-7).

REFLECTION

(SOURCE)

(TERMINATION)

Pd
CP-2592

Figure 3-7

Impedance (Low Resistance) Mismatch Example

3-9

Note that: (a) transmission line which is not terminated in its characteristic impedance will have reflections and (b) the voltage seen at any point on the line or at any instant in time will be a combination of
the incident and reflected voltage.
The amount of reflection depends on the mismatch, and approaches 100 percent for either a shorted or
an open line (see Figure 3-8).

+100%

REFLECTION

~--------.:-=_-----!-..:::::::::::.------

-100%
CP-2593

Figure 3-8

Mismatch Reflection Curve Example

Essentially the same thing happens on the negative going edge of a level change so that what seemed to
be a clean transition as in Figure 3-9A, may look more like Figure 3-9B.

Figure 3-9

BCII Unibus Cable Mismatch (Waveform Example)

3-10

To further compound the problem, each device in the bus contributes its own unique impedance and
mismatch in complex time relationships (Figure 3-10) .

•

SOURCE

DEVICE

~
SOURCE

DEVICE

\J'"
SOURCE

I
DEVICE

0
CP-2595

Figure 3-10

System Device Impedance Example

All of this impedance and resistance mismatch is normal and to be expected in Unibus systems. The
objective here is to point out the possible impedance mismatch and how to use the appropriate tools to
minimize the effects of reflections and "noise". Reference the techniques listed in the following
paragraphs.
3.3.1

Line Termination Technique

The question may be asked, how can a 178 and 383 ohm resistor properly terminate a line which has an
impedance of 120 ohms?

3-11

A perfect power supply has an ac resistance (impedance) of zero ohms, so for ac considerations the
termination diagram changes somewhat to that shown in Figure 3-11 B and simplified in Figure 3-11 C.

178 Q
Z = 120 Q
(A)

383 Q

=
Z = 120 Q
(B)

178Q

383 Q

+5V
POWER
SUPPLY

~
Z = 120 Q
(e)

tl:~l",

"" :: f
~

CP-2596

Figure 3-11

Line Termination Technique Example

The choice of these two values satisfies both the quiescent condition and the required termination
impedance.

3.4 CABLE AND CONTACT RESISTANCE LOSSES
The threshold point at which a bus receiver switches (asserted) from a 0 to a 1 is approximately 1.3 V.
If a driver cannot pull the line low enough to completely assert the line, erratic system operation will
occur. There must be adequate low-threshold margin to prevent this problem.
In the asserted (low true) condition, wire and contact resistance may cause the input voltage at a
receiver gate to be higher than the driver output.

3-12

+5
178 n

178 !l
Rub

V Rub

383 n

+
383 n

(DRIVER)

(RECEIVER)
CP-2597

Figure 3-12

Cable Resistance Problems Example

Referring to Figure 3-12, assume a pure cable resistance of 0.6Qj.3048 m (1 ft)* and ignore contact
resistance (which would only aggravate the problem). If the cable between the driver (A) and receiver
(B) were 15.24 m (50 ft), then RUB = 30, or 0.6Q X 15.24 (50) = 9.14 (30).
A voltage will be developed across RUB with the polarity as indicated when the driver asserts the line.
This voltage could be as great as 0.7 V.

Yin will not be 0.8 V, but instead
Yin = 0.8 V + VR UB

In this case, Yin might be as high as 1.5 V (0.8 +0.7) and erratic system operation may result. Unibus
cable card contacts must be clean (to minimize contact resistance) and cable length should be as short
as possible (to minimize wire resistance).

*BCIIA cable is typically O.IQ/O.3048 m (ft). Considering the return path in addition to the signal line, cable
resistance is approximately O.2Q/O.3048 m (ft) of cable length.

3-13

CHAPTER 4
BUS MARGINING

4.1 GENERAL
Experience has shown that a properly functioning Unibus will operate with terminator source voltages
of between 4.2 and 7.0 volts without any adverse effects. If the voltage is varied between these values, it
may be possible to detect and/or aggravate bus problems and thus make it easier to define and correct
the failures. At present, there are two methods that can be used to change the quiescent levels on the
Unibus for margining purposes.
1.

Use a Unibus Voltage Margin Tester Box to vary the source voltage applied to the terminator network.

Use Hi/Lo Terminator Cards to vary the terminator network (rather than the voltage). The
hardware required for this method is less expensive and more portable than the Unibus
Voltage Margin Tester Box, however, this method is more difficult to use for troubleshooting Unibus failures.
NOTE
A third method, referred to in this manual as the
single-ended margining techniques, is an extension of
the UVM-TA method described in item 1. This
method must be used for those processors that
employ Sack turnaround or Bootstrap functions on
the terminator cards.

4.2 BUS QUIESCENT LEVELS
Normal bus quiescent levels are listed in Table 4-1. Any level that deviates from the normal level
should be considered as a potential failure. In many instances the improper level will be the result of
either a defective bus receiver or driver. In the case of AC/DC LOW, these levels are power supply
dependent.
Table 4-1

Bus Quiescent Levels

Signal

Quiescent Level

BG7:4
NPG
ACLow
DC Low
All Others
(Except BBSY which depends on CPU type)

+.45 V (±0.35)

4-1

+4.9V (±0.35)
+3.4V (±0.2 V)

To measure quiescent Unibus levels:

Turn the system on with the processor halted. Press the START key and release it (with
HALT down).

Use a calibrated oscilloscope (or voltmeter) to measure the Unibus signal lines. (See chart of
Unibus slot backplane pins, Figure 4-1.)
NOTE
To obtain meaningful readings of bus grant lines (BG
4:7 and NPG), they should be measured at the grant
input of each device down the length of the bus.
All buses should be checked in multiple bus systems.

4.2.1 Quiescent Conditions
Low true lines: (Address, Data, Control and Arbitration)
The low true Unibus lines are characterized by a termination at both ends and some number of
"loads" determined by the system configuration as shown in Figure 4-2.
In the quiescent conditions we are dealing with dc levels. Ignoring loads for a moment, consider the
equivalent Unibus line circuit based on termination alone as shown in Figure 4-3.
The quiescent dc level on the line may be calculated using Ohms law, where:
I

E/Rl + R2

(IXR2)

5/89+ 191.5

0.0178X 191.5

0.0178A

3.4087 (3.41) volts

If the potential on the line were measured (with respect to ground), it would be 3.41 volts as shown in
Figure 4-4.

In theory, the loads should not affect the quiescent level of the bus lines, but in practice this is impossible to achieve. To be considered acceptable, one load cannot contribute more than 210 JlA ofleakage
current (see Chapter 2 for definition of dc unit load), but even this level will have an effect on the
quiescent level of the line.
If 20 loads are added to the original example (Figure 4-5), with each drawing 210 JlA of current, the
calculation changes somewhat.
(20 X 210 JlA = 0.0042 amps of leakage current)
The total current through R 1 now increases which increases the 1R 1 drop.
The quiescent level of the line will now be approximately 3 volts.

4-2

IVIEWED FROM BACKPLANEI

,
INIT L

@-+5

INTR L
Be

.... -

C
D.
E
Fe

Je
K
Le

--- ..--- ....
.-

M
N@

-..

02
01
04
03
06
05
08
07
10
09
12
11
14
13

)

-PA
15
PB

- --...
0

R@
S®

DATA LINES

BBSY
SACK
NPR
BR7

r~p-;

BR6

I
I

@-+5

BO
C

-- --- .-.
--

BR5

BR4

I
I

E®
Fe"

JfI
K.
L.
M
N.
P
Rtr
S
T®
U

' -'

--- --

BG7

BG6
BG5

..,
I

I
I

I
I
I
I

L- BG4

..J

r ----,
AC LO
I
DC LO

01
00
03
02
05
04
07
06
09
08
11
10
13
12
15
14
17

)

ADDRESS LINES

16 "'

SSYN
MSYN

KEY
•

3.4 V 1±.2 VI

.45 V 1±.35 VI

4.9 V 1±.35 VI

® GND
EEl +5
CP·2600

Figure 4-1

L ___ ..J

Unibus Slot Backplane Signals
4-3

• ••

CP·2579

Figure 4-2

Low True Unibus Line

178Q

383n

383Q

89fl

191.5n
R2

I = .0178A
8

CP-2580

Figure 4-3

Equivalent Unibus Line Circuit

4-4

CP-2S81

Figure 4-4

Quiescent dc Level Example

'R2

0
A

',.

'-.
-'...

0
A

>
-'-

v ~
210,ua

210,ua

0
A

• • •

;--

'---

-:L

1\
V

210 J.l a

CP-2582

Figure 4-5

Load Current Leakage Example

4-5

3.7

....... .......

.......

..............

3.6

..............

....... ........

QUIESCENT
LEVEL

........

...............

..............

-_ . . . . r
........

- -TERMINATOR

E = 5.5V

........

3.4

....... .......

3.3

3.2

3.1

3.0

2.9

-... ............

. . . . . . . . ..........r
............

TERMINATOR E = 4.5 V

........

2.8 L.....-~-L---L_L-..L..-~-L.--.l_
..........
...=L.....,L----l_.L.-....l..--L.--.l-L-...L-.-L---L----'L-----+ 2.8
10 ............

BUS LOADS
(WORST CASE)

............
-

..........
2.7

........................
............

2.6

CP·2583

Figure 4-6

Quiescent Level vs. Bus Loading (Worst Case)

By Unibus convention, these lines are asserted true when low (= 1) and negated when high (=0). The
threshold point at which a receiver switches from a one to a zero is approximately 2.5 V using a DEC
380 Receiver Module (or 1.7 V with an 8640 Receiver Module). If enough loading is present to force
the quiescent level low enough (see Figure 4-6), system operation may become extremely erratic.
(There must be an adequate noise margin above the threshold level to allow for crosstalk and
reflections. )
4.2.2 Multiple Bus System Considerations
Multiple bus systems are those which include bus repeaters or bus switches; the entire Unibus is repropagated (see Figure 4-7). When margining techniques are employed with multiple bus systems, it is
desirable to margin all bus sections on an individual basis. (It is not necessary to margin multiple buses
sim ultaneously.)

4-6

·11'

CPU

UNIBUS A

BUS
REPEATER

1:-

UNIBUS B

I
-=

~
~~

A. SINGLE BUS SYSTEM

+5
~
I

-..l

CPU A

I
I

UNIBUS A

-::!:

-= +5

BUS

SWITCH

UNIBUS C

I
J

CPU B

I
I

UNIBUS B

-=
B. MULTIPLE BUS SYSTEM

Figure 4-7

Margining Multiple Bus Systems

BUS

REPEATER

I
~

BUS 0

~
-::

It is important that the correct termination points are used for any given bus in a system - do not guess.
Refer to the module utilization prints to determine which terminators go with which bus.
4.2.3 Grant Line Termination
The grant lines on the Unibus represent a special case of termination and assertion levels (high = true).
Grant lines may not always run from one physical end of the bus to the other. The Grant line is broken
at each device wired to it and repropagated if that device is not requesting (see Figure 4-8). It should be
noted that changing the bus quiescent levels at the terminator will not affect grant lines which have
been repropagated. To measure the quiescent level of grant lines or to observe grant line waveforms, it
is necessary to check at the specific point of interest.

DEVICE A

DEVICE 8

178 n

178 Q

UNIBUS
UNIBUS

• M930 TERMINATORS

CP-2598

CHANGING QUIESCENT LEVELS
(BY CHANGING TERMINATOR
VOLTAGE OR NETWORK) DOES
NOT AFFECT GRANT LINES
WHICH HAVE BEEN REPROPAGATED

Figure 4-8

Grant Line Bus Margining Technique

4.3 HI/LO TERMINATOR BUS MARGINING
The Hi/Lo Terminator cards (see Figure 4-9) are designed to test the high and low bus margining
voltages by varying the terminator network (rather than varying the voltage when using the UVM-TA
tester). The M930 terminators must be removed from the system under test and be replaced by M9304
low margin or by the M9304-Y A high margin terminator cards.
There is a special terminator used in the 11/35 and 11/40 processors which combines the functions of a
terminator and a unibus jumper module (M981). There are Hi/Lo terminator cards to fit this application also (M9305 low margin and M9305- Y A high margin).

4-8

Margin terminators are used as a go/no go test and are not to be installed in the system on a permanent
basis. (They are too lar ge to fit in an expander box with the covers closed which will help avoid this
mistake.) Figure 4-10 illustrates the circuit representation of the Hi/Lo terminator cards plus representative load values.
WARNING
When using special terminators, it is important that
the same type (Hi or Lo) be installed at both ends of
the bus for the test to have meaning.

Figure 4-9

Margining Cards

4-9

+5V

+5 V

121 II

+5V

+5 V

196 II

121 \l

196 \l

UN IBUS

UNIBUS

301 II

301 \I

(LOW)

(HIGH)

CP-2601

Figure 4-10

Hi/Lo Terminator Circuit Example

High Margin
1.

M9304-YA
(Replaces the M930 Terminator)
M9305-YA
(Replaces the M981 special case 11-35/11-40 terminator)

Quiescent = 5 V-(1 R drop caused by loads)
Failures here usually caused by weak drivers, receiver with marginal threshold or dirty bus cable
contact fingers.
'
Low Margin
I.
2.

M9304
(Replaces the M930)
M9305
(Replaces the M981 special case 11-35/11-40 terminators)

Quiescent = 3.03-(1 R drop caused by loads)
Failures here usually caused by a receiver with marginal threshold or reflections on MSYN, SSYN,
INTR, BBSY.
4.4 UNIBUS VOLTAGE MARGIN TESTER BOX
The Unibus Voltage Margin Tester (UVM-TA) is a portable tester designed to check all Unibus
receivers and drivers in a system, either singly or as a group. Figure 4-11 illustrates the circuit representation of the UVM-TA plus representative load values. The control panel (Figure 4-12) furnishes a
switch for each of the designated bus signals and is used to provide fixed (+ 5 V) or varia ble termination voltage to special terminator boards (called Margining Heads - M9303) which are used in place
of the standard M930 terminators. The margining heads cards allow the voltages selected to be applied
to each terminating network on an individual basis. Refer to Figure 4-13 for a block diagram overview
of the UVM-TA.

NOTE
This does not change the effective Unibus length.
4-10

17812

17811
POWER
SUPPLY

UNIBUS

383 \I.

383 12

UVM-TA

-=
CP-2602

Figure 4-11

Figure 4-12

UVM -T A Circuit Representation

Controls and Indicators

4-11

UNIBUS VOLTAGE MARGIN TESTER (UVM-TA)

VARIABLE
DC POWER

VARIABLE DC

(56 SWITCHES -- ONE FOR
EACH LINE ON THE BUS.)

FIXED DC +5 V
FIXED

+5 V DC
POWER SUPPLY

PANEL CONNECTORS

BC11 CABLE

\ \\

\
WARNING: Do NOT plug this
cable directly .into a UNIBUS
slot -- it comes directly
from the power supplies and
may damage UNIBUS drivers

MARGINING HEAD
M9303 OR M9303-4A (11/70 HEAD)

EITHER +5 V FIXED
________ OR VARIABLE DC

180 II

AS SELECTED BY
SWITCH IN MARGIN
TEST02.

390 Sl

PIN COMPATIBLE WITH ~
M930 TERMINATOR
......u._______V
CP·2604

Figure 4-13

UVM-TA Block Diagram

4-12

4.4.1 Functional Description
Functionally the UYM-TA consists of a fixed supply, a variable supply, a control panel, Unibus
cables, and terminator cards that enable the user to margin voltages in the Unibus sections.
NOTE
The use of the Unibus cable with this tester is as a
power transmission cable.
The fixed supply provides the voltage for normal system operation. The variable supply (when
selected) provides the variable voltage, for system margining purposes. The front panel controls and
indicators control the choice of fixed or variable voltage, vary the voltage, display the voltage, indicate
both ac and dc power on, and select individual Unibus signal lines.
CAUTION
This Unibus cable must never be plugged directly
into a CPU, option or peripheral while connected to
the tester - it should be plugged into the margining
head only.
With the recommended program (DECXll or operating system) running in the system, the user now
selects any or all lines to be margined. The respective switches should be placed in the YARIABLE
position. The margin voltage can then be varied by using the VARIABLE potentiometer. The voltage
level at which the system fails or when the limits of the supply are reached, may be obtained by viewing
the metered display.
4.4.2

UYM-TA Operation and Test Procedures
1.

Unlatch and remove the top cover from the suitcase tester and place to one side. This allows
room for the cabling to be connected into the tester box.

Remove test heads M9303, M9303-YA and BCll-A from inside the top cover pocket. Place
all signal switches (56 total) in the "down" or FIXED position. Place power switch in the
OFF position.

Turn system power off. Remove the M930 terminators from both ends of a section of bus in
the unit under test and replace with the M9303 margining heads (M9303-YA for 11/40
CPUs).

Plug the Unibus cable (BCllA) into the margining heads.

Plug the (BCll-A) power cable into the margining heads. Plug the BCll-A cable into tester
slots 1 and 2.
CAUTION
Plugging the BCl1-A Unibus cable directly into a
CPU or peripheral without the test heads M9303Y A may cause the Unibus drivers to burn up.

4-13

Plug tester box ac cord into a convenient power source. Power can now be applied to the
system and the tester.

Place power switch in the ON position and adjust the variable voltage to +5 V.

Load recommended programs (DECX11 or operating system).
NOTE
Signal switches must not be switched while the system is running. Always halt the system before
attempting to change selection switch setting.
There is one switch for each of the designated bus signals and is labeled on the tester box
control panel. By setting a switch in the VARIABLE "up" position, the margin voltage
displayed is applied to the individual pull-up resistors and thus the signal lines can be margined by varying the VARIABLE potentiometer.

With the system halted, put all (56) bus signal switches in the VARIABLE "up" position.
Restart system running the selected program. Adjust the variable voltage to 6 V and run
system for 15 minutes (or longer) with all options selected. Then, increase in .5 V steps (or
smaller increments if necessary) until the failure occurs. Record this value.
CAUTION
Halt and restart the program each time a new voltage is selected when running DECXll.

10.

Adjust variable voltage to 4.5 V and run system for 10 minutes (or longer). Then, decrease in
.5 V steps (or smaller if necessary) until a failure occurs. Record this value.
CAUTION
Halt and restart the program each time a new voltage is used when running DECXl1.

11.

Every system must run between 4.2 V and 7 V. If a system failure occurs, margin the following five signals only:
SSYN, MSYN, INTR, SACK, BBSY

12.

If it is not one of these signals that failed, continue to margin sections of the bus until a line
failure or group of lines is isolated as the problem area. Repair the defective line and recheck
the margins for:
a.
b.
c.
d.
e.

13.

Low byte data
Address and Clines
Request lines (NPR/BR)
High byte data
Remaining lines

When tests are complete, turn power off, remove the special test equipment, replace the
terminator cards and remove tester from power source.

4-14

4.5 SINGLE-ENDED MARGINING
F or some processors, it is not possible to use the M9303 series of margin heads with the voltage margin
tester. This is because some machines include additional hardware on the terminator module (bootstrap function, sack turnaround, etc.) which must be present for the machine to operate normally. For
these machines, a single-ended margining technique has been developed (PDP-l1/04; 11/34). This
technique may be used with any Unibus machine.
Single-ended margining is accomplished by placing a voltage margin terminator on only one end of a
bus segment and varying the voltage applied to it ((see Figure 4-14). This accomplishes the same results,
but the considerations are slightly different.
NOTE
Using the M9308 single-ended margin terminator, a
system should operate successfully between 7.85 V
(high margin) and 2.93 V (low margin) as displayed
by the panel meter on the voltage margin tester.

+ 5V

SYSTEM TERMINATOR

180 Ii

390 Sl

rl J l
I
I
I
I
I
I
I
I
I ~ I

L _ J

BUS LINE

UNIBUS VOLTAGE
MARGIN TESTER

M9308 SINGLE ENDED
MARGIN TERMINATOR
CP-2605

Figure 4-14

4.5.1

Single-Ended Circuit Example

Setup and Operation (Using M9308 Single-Ended Margin Head)
1.

Unlatch and remove the top cover from the suitcase tester and place to one side. This allows
room for the cabling to be connected into the tester box.

Remove test head M9308 and BC l1-A from the inside cover top pocket. Place all signal
switches (56) in the "down" or FIXED position (-l.). Place power switch in the OFF
position.

4-15

Turn system power off. Remove the M930 system terminator (see application table) and
install the M9308 margin head. If the M9308 is not used at the electrical end of the bus,
disable SACK turnaround with the switch located on the M9308 module.

Plug the Unibus cable (BC IIA) into the M9308 margining head.
CAUTION
Connecting the BCII power cable directly into a
CPU or peripheral without the margin head may
cause equipment damage.

Connect the BC 11 power cable into tester slots 1 or 2.

Plug tester box ac cord into a convenient power source. Power may now be applied to the
system and the tester.

Place power switch in the ON position and adjust the variable voltage to +4.34 V.

Load recommended programs (DECXll or operating system).
NOTE
Signal switches must not be switched while system is
running. Always halt the system before attempting to
change selection switch setting.
There is one switch for each of the designated bus signals and is labeled on the tester box
control panel. By setting a switch in the VARIABLE "up" position, the margin voltage
displayed is applied to the individual pull up resistors - thus, the signal lines can be margined by varying the VARIABLE potentiometer.

With the system halted, put all (56) bus signal switches in the VARIABLE position. Adjust
variable voltage to 6 V and restart system running program selected. Then, increase in .5 V
steps (or smaller increments, if necessary) until a failure occurs. Record this value.
CAUTION
Halt and restart the program each time a new voltage is selected when running DECXI1.

10.

Adjust variable voltage to 4.0 V and run system for 10 minutes or longer. Then, decrease in
.5 V steps (or smaller, if necessary) until a failure occurs. Record this value.
CAUTION
Halt and restart the program each time a new voltage is used when running DECXI1.

11.

Every system must run between 2.93 V and 7.85 V. If system failure occurs, margin the
following five signals only:
SSYN, MSYN, INTR, SACK, BBSY

4-16

12. If the problem is not with one of the above signals, continue to margin sections of the bus
until a failing line or group of lines is isolated as the problem area. Repair the defective line
and recheck margins for:
a.
b.
c.
d.
e.

Low byte data
Address + Clines
Request lines
High byte data
Remaining lines

13. When tests are complete, turn power off, remove the special test equipment, replace the
terminator module and remove tester from ac power source. If margin values are recorded
for future use, be sure to note that these values were obtained with single-ended techniques.
4.5.2 Single-Ended Circuit Consideration
The user of the single-ended margining technique should be aware of the theory and application of the
Quiescent Voltage versus UVM-TA Voltage considerations. Calculations are not necessary because
Figure 4-15 is designed to provide this information. However, the difference must be made between
single-ended and double-ended margining techniques because of the different voltages that must be
applied by the UVM-TA tester under these conditions.

Table 4-2 supplies terminator application data for the M9308 single-ended margin head plus doubleended terminators, and how they relate to particular CPU bus segments. In bus segments not including
a CPU, the same procedures apply.
According to Thevinen's Theorem, any line or network of impedance and generators, when viewed
from any two points in the network, can be replaced by an equivalent voltage source and an equivalent
impedance in series. As an example, consider the termination network used on the M930 Unibus
terminator.
The voltage looking "back" into the network will be 3.42 V because of the voltage divider action of R 1
and R2. This is an equivalent voltage source of 3.42 V.

R1
18011

R2
3900

CP·2560

4-17

5
HIGH
LIMIT

MARGIN RANGE

-------

----

(NORMAL)

3
lOW

~"""'i

SINGLE ENDED

LIMIT

DOUBLE ENDED

~
I

o
2

3
/
2.93 lOW liMIT
(SINGLE ENDED)

NORMAL

HIGH LIMIT

ENDED)

(DOUBLE

4.34 NORMAL
(SINGLE ENDED)

[

MARGIN BOX VOLTAGE

(DOUBLE

}8
7.85 HIGH LIMIT

ENDED)
(SINGLE ENDED)

4.2 lOW LIMIT
(DOUBLE ENDEDI
CP·2606

Figure 4-15

"I'

Quiescent Voltage vs UVM-TA Voltage

:h'

Table 4-2 Terminator Application Data
M930

M9300

M9301 (YA-YO)

M9302

M9303

M9304

M930S

M9306

M9308

M981

Standard
Terminator

Used
on
RHll

Bootstrap
Terminator
YA-YD '" Various
Bootstrap Progs.

SACK turn
around
logic

Margin
HeadUsed w/
Bus Margin
Tester

Fixed
Margin
Term.

"Magic"
Backplane
Terminator

Sing1eEnded
Margin
Terminator

Bus
Jumper +
Terminator

11/03

Non-Unibus Machine - Terminated on M7264 Module (Expansion Configurations use M9400-XX Terminator)

11/04

Near End
REQUIRED

Far End
REQUIRED

OPTIONAL
Far End

11/05
11 /10

Both
Ends

OPTIONAL
Near End

11/15
11/20
11/21

REQUIRED
Near End
(Mech.)

OPTIONAL
Far End

.j;:..
I

Near End
w/Opt sw.
Panel
Near and
Far endUsed with
Bus Margin
tester
and doubleended
technique

Near
and
Far
end
fixedmargin
technique

M9303-YA
Near End
For
Margin

Far End
For
Margin

Near and
Far end
For
Margin

Near
and
Far end
For Margin

OPTIONAL
Either
end
OPTIONAL
Far End

Far End
Margin
Term. for
use with
Bus Margin
tester
and sing1eended
margin
technique

11/34
11/35
11/40

Far End

11/45
11/50
11/70

Both
Ends

OPTIONAL
Either
End

OPTIONAL
Far End

Near End
For
Margin

REQUIRED
Near End

OPTIONAL
Either
End

The Thevinen equivalent impedance, R Th of the circuit is found by shorting the generator and calculating the circuit impedance.

12311

CP-2561

The equivalent voltage source can be represented by a circuit consisting of a 3.42 V source in series
with an impedance of 123.157 ohms.

118.411

CP·2562

The termination network used on the M9308 single-ended margin terminator consists of 180 ohms to
the voltage source and 562 ohms to ground (see Figure 4-16).
If this network is considered a Thevenin generator, it becomes a source of 78.9 percent X voltage
applied (because of the voltage divider action) in series with 118.4 ohms.

+5V

150\l

18011

Rl
12311

39011

~BUSLINE

56211

Figure 4-16

M9308 Termination Circuit Example

4-20

118.4

The voltage seen on the bus line may be computed by considering what happens when these two
generators are connected together. For example, if the M9308 has 7.85 volts applied to it:
1.

E = 6.16 - 3.42 = 2.74 V

RT 123Q + 1I8.4Q = 24I.4Q

I = EjR = 11.35 mA

Voltage drop across Rt = 11.35mAX 123Q = 1.396 V

Voltage on the bus line = 3.42 + 1.396 = 4.8 V

In this application (since the Thevenin equivalent impedances are similar), a simple rule of thumb is:
3.42

(0.79

UVM-TA)j2

V bus line

4.5.3 SACK Timeout
In some processors, if SACK is not received within ten ms after a grant is issued, the processor will
timeout and proceed as if no grant had been issued (unless, of course, a request line continues to be
asserted). In others, the processor will continue to wait for the return of sack; this will cause the bus to
hang. This problem is solved on some terminators by turning bus grant around and sending SACK
back to the CPU. The processor will then release BBSY and, if no device is requesting, will immediately regain control of the bus through the passive bus release mechanism. The M9308 margin head
will turn bus grant around into SACK and set a latch. There is a LED installed on the M9308 to
"remember" the fact that a grant was received (not a normal condition at the end of the bus). Switches
are provided to enable SACK turnaround and reset the latch (see Figure 4-17).
NOTE
If SA CK turnaround is enabled, the M9308 must be
used at the electrical end of the bus.
4.6 MODIFYING M930 TERMINATOR CARD
I f the test equipment previously described is not avilable, it is still possible to employ voltage margining techniques.
4.6.1

Equipment Required
1.

Variable dc power supply with a 1 percent a regulation (or better) and a 2 amp output rating
(minimum).

Modified M930 Terminators (two each).

4-21

+5V

"ENABLED"
BUS NPG H - - - \
BUS BG7 H - - - J

D - - - BUS SACK l

BUS BG6 H --~-......
BUS BG6 H - - - I

BUS BG4 H --~-......
D1

D---r~~-~~

+5V

ClK
• THE switches and
L.E.D are labeled
on the M9803 Module

NOTE: If SACK turnaround is enabled. the M9308 must be
used at the electrical END of the bus.
CP-2607

Figure 4-17

4.6.2

M9308 SACK Turnaround Logic

Modifying the M930
1.

On side 2 of the M930, cut etch at pin AA2.

On side 2 of the M930, cut etch at pin BA2.

Attach one end of a 4.57 m (10 ft) piece of No. 16 gauge (or larger) insulated wire to the etch
as indicated in Figure 4-18 (step 3). This will be the plus (+) lead to the variable power
supply.

Attach one end of a 4.57 m (10 ft) piece of No. 16 gauge (or larger) insulated wire to the etch
as indicated in Figure 4-18 (step 4). This will be the minus (-) lead to the variable power
supply.

4-22

STEP 2

BA2

AA2

STEP 1

CP·2608

Figure 4-18

4.6.3

M930 Modification Example

Procedure for Use
1.

Turn all system power off.

Connect modified terminators to the variable power supply (double check polarity).

Remove system M930 terminators from Unibus.

Install modified terminators in system where standard terminators were.

Turn on variable power supply and adjust output to +5 V.

Turn on system power.

Proceed with bus margining as described in Paragraph 4.3.

4-23

CHAPTER 5
UVM-TA TESTER

5.1 UVM-TA OVERVIEW
This chapter provides DIGITAL Field Service personnel with sufficient information to operate and
maintain the Unibus Voltage Margin Tester (UVM-TA) and use it to troubleshoot Unibus Problems.
The UVM -T A is a portable device (see Figure 5-1) designed to check all Unibus receivers and drivers
in a system by applying a margining voltage to the Unibus lines. The tester provides a dc termination
voltage to special terminator boards. These special terminator boards, called margining heads, are
used in place of the standard M930 terminator. The margining heads do not change effective Unibus
length.
5.2 TESTER KIT COMPONENTS
The complete tester kit consists of the components shown in Table 5-1.
Table 5-1
Number

Tester Kit Components
Part Number

Description
UVM-TA Tester

Margining head

M9303

Margining head

M9303 YA

TBS

Unibus Cable

BCll-A

UVM -T A Troubleshooting
Guide
The UVM -T A is a relatively simple electrical Unibus testing device. It contains two dc power supplies
(a fixed supply and a variable supply), a digital voltmeter (DVM) to monitor the power supplier, and
56 SPDT switches.
The fixed 5 Vde power supply provides the voltage normally used to terminate the Unibus lines. Any
of the 56 Unibus line switches placed in the fixed position will connect the terminating network of the
selected line to the fixed supply. This allows the operator to keep certain lines at the normal terminating voltage while varying the terminating voltage on other lines. The fixed supply also supplies
power to the DVM.
The variable de power supply provides between 2 and 8 Vdc to margin Unibus lines. The supply is
adjustable via a front panel control and is monitored by a DVM also located on the front panel. Any
of the Unibus line terminating networks can be connected to this supply by setting the corresponding
data switch to VARIABLE.
5-1

Figure 5-1

Unibus Voltage Margin Tester Box

The front panel DVM normally monitors the variable supply. When the DISPLAY FIXED VOLTAGE button is pressed, the DVM displays the voltage of the fixed supply.

5.3 TESTER SPECIFICATIONS
The tester contains two dc power supplies, a fixed supply and a variable supply.
Fixed supply
Variable supply

5 Vdc at 2 amps
2 V to 3 Vat 2 amps

The tester is designed for use in the field. It is packaged in a brief case type carrying case and weighs 35
pounds. The carrying case holds the tester, margining heads, cables and the manual. The tester
requires 115 or 230 Vac (10 percent), 50 or 60 Hz single-phase power.

5-2

5.4 UNPACKING PROCEDURE.
To unpack the UVM-TA:
1.

Remove the carrying case from the shipping carton and inspect for exterior damage. Damage claim should be directed to the responsible shipper.

Open the carrying case and inspect the components for damage.

Verify that all components are present. (See Paragraph 5.2 for Kit Components).

5.5 ACCEPTANCE TEST
The UVM-T A is shipped ready-to-use. If the unit is not operating properly, refer to Preventive
Maintenance (Paragraph 5.9) to diagnose and correct the problem. Service should be performed by
qualified personnel only. A Tripplet (model 630-NA) or Simpson (model 260) multimeter is required
to perform the acceptance test.
To check out the UVM-TA:
1.

Plug tester ac cord into power source.

Place 56 signal switches in the down position.

Turn tester on. Verify visually that power indicator is on, FIXED DC INTERNAL
indicator is on, and DVM is. displaying a voltage between 1 and 9 Vdc. An internal fan will
come on. This can be verified by listening for the sound of the fan.

Using the VARIABLE potentiometer, vary the internal variable dc supply between 2 and 8
volts. This can be verified by observing the DVM. Set the variable dc supply to 6 volts. The
VARIABLE DC INTERNAL indicator will be lit. Press DISPLAY FIXED VOLTAGE.
DVM will read 5 V.

Using the multi meter, probe pin BSI of the test connector 1. Voltage will read 5 Vdc. Put
ADDRESS REGISTER switch in up or VARIABLE position. Voltage will read 6 Vdc. Put
switch into FIXED or down position and probe similar pin on test connector 2. Voltage will
read 5 Vdc. Switch to up position. Voltage will read 6 Vdc. Leave switch up to indicate it has
been tested.

Repeat step 5 for remaining 55 Unibus signal switches.

5.6 CONTROLS AND INDICATORS
All controls and indicators for the UVM-T A are located on the front panel of the unit (Figure 5-2).
The function of each control and indicator is listed in Table 5-2.
5.7 OPERATING PROCEDURE
Refer to Chapter 4, Paragraph 4.4.2 for operating procedures.

5-3

7534-2

Figure 5-2

Controls and Indicators (Indexed)

5-4

Table 5-2
Index No.

Controls and Indicators (Indexed)
Function
FUSE 2.5 AMP - Protects tester from current overload.

ON/OFF - Switch controls ac power to tester.

ON /OFF Indicator - Lights when tester is on.

56 single-pole double-throw switches - control margining voltage to each of 56 individual Unibus lines. When in the down
position the selected line is connected to a 5 Vdc fixed voltage
supply. When in the up position the selected line is connected to
variable dc voltage supply.

Tester connectors - connects selected voltage levels to margining heads.

Controls output voltage of variable voltage.

. When depressed, digital voltmeter monitors voltage of fixed
supply voltage. DVM normally monitors variable supply
voltage.

Digital voltmeter monitors voltage of selected power supply.

VARIABLE lights when variable supply is operating. Brightness is proportional to selected voltage.

FIXED lights when fixed supply is operating.

5.8 MAINTENANCE PHILOSOPHY
Tester maintenance consists of preventive and corrective maintenance procedures. The preventive
maintenance procedures should be performed regularly in order to detect any damage caused by
improper handling of the unit. A troubleshooting flow diagram is provided to aid service personnel in
isolating and repairing faults within the tester circuits. The troubleshooting flowchart and corrective
maintenance information given in this chapter covers only the tester unit. The flow diagram makes use
of the acceptance test procedure outlined in Paragraph 5.5.
To perform disassembly/assembly and preventive and correction maintenance, only a multimeter and
standard hand tools are ,required. Recommended multimeters are: (1) Triplett model 630-NA or (2)
Simpson model 260.
5.9 PREVENTIVE MAINTENANCE
As preventive maintenance, the acceptance test procedure should be performed from time to time to
ensure complete operational readiness and to check the unit adjustments. The frequency of the checkouts depend on hours of handling, and environmental conditions. The schedule given in Table 5-3 is
suggested as a minimum time table.

5-5

Table 5-3

Preventive Maintenance Schedule

Performance Interval

Test or Procedure

Monthly

Visually inspect for physical damage; correct if required.
Clean externally.

Quarterly

Clean internally with vacuum cleaner or a soft brush
Check for looseness of the knobs, switches, and indicators.
Perform acceptance test procedure (Paragraph 5.5)

5.10 CORRECTIVE MAINTENANCE
If the tester fails the acceptance test or fails while testing a Unibus system, corrective maintenance
must be performed. The flowchart (Figure 5-3) will pinpoint the faulty tester component. However,
before using the flowchart, unscrew and lift up the control panel and perform a visual inspection. Look
for burnt or damaged wires or components. Replace any faulty wires and component(s), if found, and
perform the acceptance test procedure to determine if the tester has been repaired. If not, begin using
the flowchart.
CAUTION
Certain circuits in the tester operate at 110 Vac.
Special care must be taken when probing near these
circuits. Before disconnecting, replacing and / or
reconnecting any part other than a fuse, turn tester
off and unplug it.
NOTE
Turn tester off when replacing front panel fuse.
5.11 DISASSEMBLY/ASSEMBLY
Many of the components within the tester are also accessible and can be replaced without performing
any disassembly. The switches, indicators, and plugs on the tester control panel are easily accessible for
repair or replacement. However, to remove either power supply, the transformer, or the fan, the tester
must be disassembled. To disassemble the tester, perform the following procedure:
1.

Unplug line cord.

Remove the tester from its carrying case by slipping it out of the case.

Unscrew and lift up the control panel.

To remove the power supplies, remove the power supply bracket using a socket screwdriver.

Remove the transformer, unscrew the four mounting bolts at the base of the transformer
using a screwdriver. Unsolder the transformer connecting leads.

To remove the fan, first remove the fan mounting bracket assembly from the tester using a
Phillips head screwdriver. Unsolder the fan connecting leads. Then remove the fan from the
mounting bracket using a socket head screwdriver and a Phillips head screwdriver.

5-6

START

CONTROL AND
ADJUST FOR
3 VDC ON DVM
DVM IS
PROBABLY BAD:
REPLACE IF
NECESSARY

P2 FROM J1 ON
+5 FIXED
REGULATOR
BOARD. SHOULD
MEASURE 5 VDC
BETWEEN PINS
2AND30FJ1.

DISCONNECT
P1 FROM J1 ON
VARIABLE
REGULATOR
BOARD. SHOULD
MEASURE 5 VDC
BETWEEN PINS
2 AND 3 ON J1.

ISOLATE
PROBLEM
AND REPAIR.
POSSIBLE
PROBLEM IS
REGUALTOR
BOARD OR BAD
ADDRESS
SWITCH.

YES

MEASURE AC
VOLTAGE
BETWEEN
LUGS nAND T2
OF n. REPLACE
FAN IF
NECESSARY

ON REGULATOR
BOARDS AND
REPLACE IF

PROBABLY
BAD. REPLACE
IF NECESSARY:

LAMPS ON
REGLATOR
BOARDS ARE
LIT REPLACE

REMOVE AND
REPLACE BAD
POWER CORD

USE VARIABLE
CONTROL AND
ADJUST FOR 6
vbc ON DVM.

~~:e~E:~~~~GEI
REPLACE
ON-OFF
SWITCH

PUSHBUTTON
UNIT FROM
AC POWER
SOURCE AND
ISOLATE
PROBLEM(S).

CP·2609

Figure 5-3

UVM-TA Troubleshooting Flowchart

5-7

APPENDIX A
ECO HISTORY AND REWORK

A.l UNIBUS TERMINATORS (M930)
The initial ECOs to the M930 (dated 1970) changed the termination of bus AC and DC LO, which
brought the M930 to etch revision B. This etch revision is now obsolete. If system bus problems are
suspected for failure, later etch terminators than the B etch should be tried.
A.l.l Revision C Etch
ECO No.3 to the M930 Unibus Terminators changed the termination resistors tolerance from 5 percent to I percent. This change improves the worst case noise tolerance and with suspected bus problems. 1 percent terminators should be used.
CAUTION
Some "C" etch terminators were manufactured with
missing etch runs. Pins ANt, APt, ARI and AS1
should be connected to pin BEl. These runs were
omitted. The missing etch runs are grounds and if not
present may contribute to system noise.
A.1.2 Revision D Etch
ECO No.4 to the M930 Unibus Terminators adds four decoupling capacitors and improved grounding. This change significantly decreases noise on the bus. Rev D is the optimum etch revision currently
used (Sept. 1976) and should be used if bus problems are suspected because of old type etch boards.
There are other terminators which will be available for new processors and systems in the near future.
A.2 BUS RECEIVERS
A number of integrated circuit types (i.e., chips) have been or will be used as Unibus receivers (Table
A-I). Of these, the DEC 380 was most common. It has been phased out and is no longer available. A
recent series of ECOs to most options which used the DEC 380 now uses DEC 8640 Bus receivers. The
DEC 8640 is a pin-compatible replacement for the DEC 380 and is used in Unibus applications
because it has more closely defined specifications and higher noise immunity (see Figure A-I). Substituting one DEC 8640 on a module does not necessitate changing all DEC 380s, these chips may
reside in any combination. (This is a phase-in and field rework is not intended except for repair
purposes.)

A-I

3.0 , . . . - - - - - - - - - - . . , . - - - - - - - - - - - - - - ,
(HIGH)

2.5 -+-r7'"7'-:..-r-r--r-T;"'7"7".,..-,-;-rr?'7"7--r-r:..-r-r..,...,1

2.0
(1.7)

1.5
(1.3) _F-"-':..£..L..:..L.<~~..£..L.~.L..U:..£..L..:..L.<+_L~..£..L.~..£..L.~.L..U:..£..L.~~~

I
1.0

I
(LOW)

DEC 8540

DEC 380

Cp·2585

Figure A -1

Comparison of 8640 vs. 380 Threshold (W orst Case)

Table A-I

Unibus I.e. Types
Note
1
2
1
3
3
4
1
4

Receivers
Type
380
8640
11380
8644
8645
314
384
8837

DECP/N
19-09485
19-11469
19-11113
Not assigned
19-12128
19-09704
19-09486
19-11116

Function
Quad nor
Quad nor
Quad nor
Hex inverter
7 input nor
7 input nor
Quad or
Hex inverter

Drivers
8881
74H01

19-09705
19-09849

Quad nand
Quad nand

Transceivers
8641
19-11579
8838
19-11117
Notes
1.
2.
3.
4.

Input Voltage
Low
1.3
1.3
Hysteresis
1.3
1.3
1.3
1.3
1.3

High
2.5
1.7

Leakage
160
80

1.7
1.7
'2.5
2.5
2.5

80
80
160
160
160
25
250

Quad transceiver
Quad transceiver

3
1

Not allowed in new designs.
Replaces the DEC 380 in Unibus applications.
A vailable in July '75.
To be used in new designs only until pin compatible replacements are available.

I.e.
314
8837

Replacement
8645
8644

A-2

100
100

A.2 BUS DRIVERS
The DEC 8881 is the standard Unibus driver. Others which have been used are listed in Table A-I.
Unibus pin assignments are illustrated in Figure A-2.
A.3 GRANT LINE TERMINA nON
The terminators on each of the Unibus do not terminate grant lines which are received and repropagated. Grant lines are terminated as shown in Figure A-3 (between devices receiving a grant line). A
recent series of ECOs that includes all devices using grant lines has changed the previous termination
techniques as discussed previously. (A 180n pull up resistor has been added to the grant receivers of
each device). This significantly reduces reflections and false grants on the bus, i.e., traps to 0, traps to 4
and undefined interrupts.
A.3.t

Rework Procedure
1.

Obtain a supply of 180n resistors. (These may be ordered under DEC PIN 13-01322).

Using the proper print set for each option, locate the grant receiver input.

If no 180n pull up resistor is installed from the input of the grant receiver to +5 V, install
one (refer to the applicable ECOs).

NOTE
Bus switches and repeaters already have these resistors installed.
CAUTION
Some devices receive more than one grant line and
many devices receive both NPG and BGxx signals.
All grant receivers should be terminated in this
manner.
NOTE
To maintain termination consistancy, a t80n pull up
could be added at the receiver and a 390n pull down
could be added at the driver. If a device with the driver pull down were used with a device which did not
have the receiver pull up, the assertion level would not
be high enough to ensure reliable operation.
A.4 BCll CABLE FOAM
The BCIIA cable (see Figure A-4) consists of two (60 conductor) mylar Flex-print cables used to
connect system units in different mounting cabinets or to connect peripheral devices not located within
the cabinets. The two Flex-print cables are taped together to form a single flat 120 conductor cable. In
system applications, there is little control over how this cable is routed. Impedance of the Be 11 cable
can vary widely due to physical routing and has been found to be in the range of 60-80n in typical
systems. (Design specification is 120n).
Eeo No. Be 11 A-004 corrects this low-impedance problem with the addition of foam between the two
mylar cables. The impedance of the cable is stabilized at 120n and is not too sensitive to physical
configuration when this foam is installed.

A-3

12
11
10

9
6
6
4

O - r - - - - - - - 15
,>---13

8 = vee
11 ----1--1

[ ) - r - - - - - - - 12
314/7314

rl-r-------- 4
12
11

6
5

D-"
D-"
D-'

'>--- 6
2

">---3
8 = GND
16 = vee

9
8838/8641
TRANSCEIVER

D:=:
8 = vee

380/7380/8640
11380

I }-"
I f-"
I f-'
I f-'

7 = GND

14 =

--L-I}-"
--L-I}-,
--L-I}-,
--L-Ir::
14 = vee

vee

74H01

8881

DRIVER

CP-2586

Figure A-2

Pin Assignments of Unibus I.e.s

A-4

+5
180 il
UNIBUS

390 il

-=
+5

±6

.,.
180 il

\. ....

I 1BO il

UNIBUS

390 il

=
CP-2610

Figure A-3

Grant Line Termination

Figure A-4

BCll Cable

A.4.1 Foam Installation Procedure
Obtain sufficient foam to do the job. This may be ordered under DEC part number 90-08881 (see
Figure A-5). The length required will be twice the sum of all BC11 cable lengths in the system, plus
twice the length of all parallel cable runs.

Foam Tape
(Part #90-08881)

Figure A-5

Foam Tape Installation

Perform the following steps for all Bell cables in the system:
1.

2.
3.
4.

Remove the tape holding the two mylar Flex-print cables together.
Examine the cables for any nicks, cuts or sharp creases, discard the cable if unserviceable.
Separate the cables and apply the foam tape to both edges for the entire length of the cable.
Retape the two mylar cables together with electrical tape. (Foam is sandwiched between
cables and a single flat cable results. Do not squeeze the cables together at the taped points.)
NOTE
If two Bell cables run parallel to each other for any
distance, foam should be placed between them. See
Figure A-6 for multiple cable foam installation.

Figure A-6

Multiple Cable Foam Installation
A-6

APPENDIX B
M9202-2 UNIBUS JUMPER INSTALLATION

B.l GENERAL
Reflections on the Unibus can be caused by termination mismatch, stubs, or loads. (Stubs cannot be
matched, any stub will cause a reflection.) Backplanes have wires attached to the Unibus which act as
stubs. In addition to this, individual modules may have bus lines carried on etch which adds length to
the backplane stub. Individual device options cause reflections on the Unibus which are called signatures. These signatures combine to form the composite waveform seen on the bus. (See Figure B-1.)

'V
I
I

r---'l/
I

----------------------------~~
c

_ _ _----'!=VCP-2611

Figure B-1

Composite and Signature Waveforms

B-1

A level change, in theory, should be a clean transition.
Devices placed on the bus may contribute signature reflections.
Many devices in close proximity may contribute to composite reflections great enough to cross over
the threshold level of bus receiver.
The M920 Unibus jumper module (double module) connects the Unibus from one system unit device
to the next. Its length is very short electrically. If device options are installed in close proximity to each
other (lumped loads), their signatures may combine to place a large reflection and false information on
the bus.
If these signatures could be separated, they would not present such a problem. The M9202-2 Unibus
Jumper Module is physically compatible with the M920; however, it induces some delay and lessens
the effect of lumped loads. The same signatures shown in Figure B-2 can be separated to reduce the
composite signal. This will prevent composite signal from crossing the bus receiver threshold and thus
from presenting false information due to large reflections.

RECEIVER
THRESHOLD

MULTIPLE REFLECTIONS
SEPARATED IN TIME TO
PREVENT THIER PEAKS
FROM COMBINING

CP-2612

Figure B-2

Separation of Multiple Reflections

This does not altogether eliminate the source of the problem, however, it does offer a reasonable
alternative for reducing the effect of reflections.
B.l.2 Jumper Installation
A first pass approximation is to install one M9292-2 bus jumper between each 4 to 8 unit loads (replace
the existing M920 with a M9202). (Refer to Chapter 2 for detailed configuration rules.)
NOTE
The M9202 is a useful troubleshooting aid and
should be left in the system on a permanent basis if
required. The M9202 will not fit in BAll-Cs or
BAll-Es mounting boxes. In these systems, use
BCllA-2 cables.

B-2

BC11A-10
110' BUS CABLE)
11/45
KT11
FP11
KW11L
PC11
OL11

MF11 LP

0011

(24K)

BM873
TA11

RK11C

CP-2613

Figure B-3

Configuration Using M920

U sing the configuration shown in Figure B-3, the following waveforms (see Figure B-4) were obtained
at SSYN on the RK 11 C backplane.

11 V/cm @40 nsec/div)

1 V

SSYN AS SEEN AT RK11 C

2V
1 V

SSYN as seen at RK11 C with
M920 jumpers replaced by
2' bus jumpers
CP-2614

Figure B-4

Jumper Threshold Levels

B-3

APPENDIX C
AC AND DC LOAD TABLE

AC & DC LO~D TABLE

-.~~-.-DEVICE
OPTIONS
~,.

If'

-------.---.-----...-~----------.-------..~.-~.----.--- ..-.-.. -- ..--.-...---~--~
LOAD
f')C
ons'l'
TI'lA Rr.:SULT5

MSYN

~ . . . . . . . . . . . . . . . _ • • • • • • • ~• • • _ • • • "

AA11-~

A011-K
AR11<"'73S')
8H79~

4
0

814&13
CRll
COll

OAll e S

9
0

0811-A (RIGHT)
0(;11
D011-A(OBSOI..ETEl
0011-8

OB11-~(LF.FT)

oou-e

0011-D (SI..OT 1-4)
0011-" (SLOT I-til
($1.0'5-<n

DH11·DMtl·B~

OJll
OL11-A(1011aQJ0)
oL.ll-C
OLlI-!
OL11-W(10116S6)
OMC II'
DF'l1
o/')u

ORU-B
DRueC(M1eU)

OR11-/<
CRU-L

rJR11- M
OTB3tCPU,

DTS3(SH.4REDJ
DTI!I6(UNI6VS .t)

12
3
6
4"
4

1I
tI
14
'3
3
tI

3
3
3

5
8
q
S
'5
3
3

7
3

1
1
1
1
1
1

2.~7

~.1I2

2.26
5.16

10.75

1. 9 1
1.iIl0

3.8 11
2.71li

11.24

1. 9 1

092375
1 fill '57!l

09237'5

5.7'5
5.119
1f.OIl~

3.:Hl
b.8q

1.911
4.16

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/j.3'5
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11'1.19
2.51
5.38

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a92275
a92?t,
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120 17I.! UJ P- \II REV. 3 AC
I..OAO IS IN PROCESS)
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3.~8

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1.711J

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fIJ

21
1
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11.83

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2.91'1
11.67
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l.q6

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C-l

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&. A OUT)
&. BOUT)

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3.2~

1.3 q

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3.69
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rU~I XBtJS ~)

DATE
OTHLR INFOR.)

NOTE~~EAaURE

S8YN

6./1'3
I~.

2.16
0.82
l'I.82
2.96
3.rI!7
1.7'5
1.S Q
1. 1I 7

11.12
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2. 119
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~.47

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7.88
II. l 1
3.48
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2.9'"
b.S2
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1.23
1.14
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2. 9 1'1

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1.61
1.7Q

2.~7

13 .. 2t1
'5.26

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1.71
0.5'"
1 "'.'15

3.56

08C!175
121874

0'3031!l
03037'5
030315
1~t570

030375
101775
11''11775
10167';
101775
030775
030775
081770
081170
08117&
081770
a8117tl
08177b
1111157'5
12157&
10157'5
101575

3.0/1

1.17

3.89
2. til

3.83

1.8a;

1.8'S

101575
011 /177
051 M'5

1
1

2.02

2.28

3.5~

10227'5

'1.7111

3.18
1.115
1. 9 1

1.13
3.81

1221'J75

3.(J'S

KGU

KW~l"K

3
4

S
tl

K~U-L(to11e7)

KW11-~(OL~ ~7228)
K~l1-P(NfW ~722e
C$ J)

nEv.F

K'f11-LA
K111-1.8 (M7859)
LI<U
lPll
L"21
LSll
LVll
M919i
M165~CPARITY MOOUlE)
M1659(PROGRAM C~NSOlE)
MAll
_MOORE S~STfM OEVICE$I
1) (OCC+OOll-A
2)IDCC("55a,9q5~1)

~) ~"OI ("556)

s
II

S
3
3

3
2

IS
S
III

HF'lleL(3X8~)

3
3
1
1
2
S
'1
q

MfU-U(2XU IQ

III

"'t<U-IJP(lX16~)

1)lCAlCVLATOR(Q9319)
H14 11-0P
MS11-JP
Mfl1-L(8AC~~LANE)

Mf'11- L( \ Xe K)
MFll e L(2X5K)

""U- UP (;!X16K)
M'll-W

"'/I!11·W~

III

6
6

1
1
1
1

3.O7
1.%

2.80
7.bB1

3.0"1

2.81

1
1

0.22

1.11

2.05

12157b

0.';11

I~. qq

5.5111

121':i7b

11.1113

1. /17

081nl>
081t/7b(I;.ST .l.

R~ui

RLU
RI='U-C(OR E)
RXU
TAU

0
7

"
6
3

2.9':;

1.'37 11.72
1.57 2.16
1.71 3.12
1
1
1

0
1
1
1
2
2

3
1

0.711

!.1C1
0.'56

1Il. 1I C1
2.1111
3.01'J
5.5111
3.76

2.:33

1.18
2.3121

1.0Q
(.1.33
1.12
I~. 90
7.0121

11.57

4.96
1.1"1
111.01
1. 1C~

081'Hb
0811'J7b
0111157b

!'J.58

010576

0.3"1

121I'J7'5

11.4"1

4.0OJ

8.70

7. 11"1

8.~0

4.IZIOJ

C).sq

4.4~

2.11
3.70

8.011')

6.001

1.1l6

I). lib

IJ.49

g.B

11.7 q

8.45

8.50
5.38

7.89
9.93
3.58
12.14
11. 01 8

0911')7'5
091 tJ 7b

ril30Q7'5

lZI~t1)75

0911'J75

RI<UeD(OLO)
RI<11-0(NEW)

1.12

lL't157b
10167'5
052710
050275

41
PC: 11 (OlO)
1
tI?
PCl1.(NEW)
1
POP I1Im4(M7203,M93~1) 1\
1
PO,. 11/1115'
l~
1
(;I
PDP 11/34(WITH Mq391)
1
12
PDP i1/35
1
2
PD~ 11/115(BUS A,KW11-L) 11
1/1
(SUS B)
2
S
~BUS- A 1 '"'OS)
1
(BUS A 2 MOS) 9
2
~~~INNTRONrcs CACHE)
6
1
'1
PDP 11/60
11
0
4
PDP 11/60(BACKPlANE)
01
20
PDP 11/70(SLOTl-3 9 )
(SLOT1~3~ BACKPLANE) S
III
($LOT4m.44 BACKPLANE)S
RH11i1
3.45 1
5
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1
1\
1
RfU

RHO

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1
1

lI.3!
11'1.03

c.ln

10./19

I~. 07

2.Pl7

I~.

2.56

7.2~

2.'57
3.1!~

1).24
7.1 Q

11.21

3.22

2.51

'3.15
'3. 1'3

2.79
2.36
11.16

5.12
0. 8 1'1
q.1 '"

3. /15
~.2f11
'1.~3
~.32

10.7

5.09
8. 113
1.8O!

rilbl2'176
12087"
ll'157b

12167 4
101075(DC 1.0"05 I KW tH.,
CPU'
217077'5

3.26
2. 9 8

211187'1
2111/177
(DC lOADSIKWI1L,CPU,

2.33

qR~7015l0T39.2FT-KW111..
2FT~SLOTn0,REV.

3.3?
1.01
II. 1ll!

6.8L')
6.51
8.2L')

011/177>

092375
101375
09057'5
09057'5
090575

11.97
ll. q7

2.78
I~. q~

1~157b

0. 711

ll.1'0

0.0i??

121570

3.119

".91
2.43

2.78

12167 11

2. qll

3. 9111

1
1

5.5t1

1
1
1

2.15

C-2

Tell

TERMINATO~(Mq30)

("'ere 1)

'f
0
0

tI.'lZ

0
iii

1 .. ~"

11.79

0 1H f)7'5

1~2f)7!.1
Q .1I1~
7.Z2
a
5.67
1
10297 U
6.6q
7.50
a
5.32
1
TMA1i
121570
g
6.0"i
ll.62
11.11
2
TMSli
09227~
3.511l
11.68
3.22
S
TR7q.F
1
121157b
2.63
s
2."Q
'5.11
vS6e
1
__ ~"_ • • W~_ • • 4 . _ _ _ _ . - _ . _ _ _ _ _ • _ _ _ _ _ _ • _ _ _ • _ _ _ _ • _ _ _ _ _ • __ · · - - - • • • ~-~.----.-~~

T"4U

NOTE,
1, OPTIMIZE N~R DEVICES SEQUENCE: RK11-D,TM11,TCll,
RJS0a,~JP0~,RK611,RJS03,RP1JC,DMC11(lMB),TJU16,
~Fl1,nMC!lC5bKn)fDHll.

2, ? MEANS OATA IS susrICIOU3.
3, • FQREIGN nEVICES.
~, IF yoU ~nUAT snME np THE VALues IN THE TABLE, PLfASE
CONTACT CHIH LX CPK3-2/S17, OR X5229),

C-3

MECHANICAL
Model

Number

Description

Mounting
Code

Size

Cab

(H x W x D)

Incl

(inches)

AAll·D
ADOI·,o
AFCII

D/ A Subsyste, .•
A/ D Subsystem
A/ D Subsystem

SU
PAN
CAB

ARll
BAIl·is
BA40B

Analog Subsyste~
MOLintir.g Box
Amplifier

MOD
PAN
(LPSII)

D/A Converter
Blank Mntg Panel

(AA11·D)
SU

BA614
BBll
BCIIA
BM792
BM873
CDll·A

tJ
,

Bootstrap Loader

SPC
SPC
SU c TT

CD11·E
CMll·F
CRll

Card Reader
Card Reader
Card Reader

SU +- TT
SPC i TT
SPC·t TT

DAll·B
DAll·F
DB11'A

UNIBUS Link
UNIBUS Window

SU
SU
SU

Bus Repeater

DCll·A
DDll
DFOI·A

Asynch Line Inter

DF11
DHll
DJII

Line Sig Cond
Asynch line MX

Peri ph Mntg Panel
Acoustic Coupler

Asynch Line MX

DL11·A
DLII
DM11·BB

Terminal Control
Asynch line Inter

DNII
DQ1!
DRll·B

Auto Calling Unit

DRII·C
DT03·F
DUll

General Interface

GT40
H312·A
H324
H720·E
H722
H742
H744
H745
H960·C
H960·D
KG11·A
KWll·L
KWll·P
LA36
LPll·R
LPll·V

Line Multiplexer

NPR Synch Line
DMA Interface

Weigt-:t

(Ibs)

( C)

('Yo)

lOAO

10·90

5'0

10AO
100

14 x 24 x 18

15·32

20·80

0.3
1.0
2.5

38 x 24 x 38
llxl9xl4
11x19x14

200
60
60

15·32
15·32
15·32

20·80
20·80
20·80

6 x 7 x 12

OF slot
2 SU + PAN
SU + PAN

51;'
51;'

Power Supply

(BAll)
(PCll·A)
(H960·D)

+5V Regulator
-15V Regulator
Cabinet

Cab (I drawer)
Comm Arith Unit
Line Clock
Programmable Clock
DECwriter II

Ptr (heavy duty)
Line Printer

(H742)
(H742)
FS
FS
SPC
MOD
SPC
FS
SPC + FS
SPC + FS

Level

60
60
1700

776 756 140,144
776 770
130
772 570
134

ARll
BAll·ES
BM08

4·5
4·24
6·8

BA614
BBll
BCllA

I
I
I

4·25
4·27
4·30

BM792
BM873
CD11·A

.002A @ -ISV

I
I
I

4·30
4A3
4·43

CDll·E
CM11·F
CR11

4
5
3.2

124
float

5
7

X
X

I
I
11'1

4·53
4·58
4·66

DAll·B
DAlI·F
DB11·A

2.2

float

4·67
4·75
4·79

DCll·A
DDlI·A
DFOI·A

774 000

0.3

0.24A @ -15V
+ 15V req'd
0.15A @ -15V
0.15A @ -15V

float
float

775 200
float
7,72410

± 15V req'd

300

(75)
1.5
0.8
I

1.5
1.5

float

4·258
4·135
4·89

Dlll·A
Dlll
DMll·B8

I
1
1

4·152
4·160
4·195

DNll
DQ11
DRll·B

I
I + I
1

4·200
4·210
4·214

DRll·C
DT03·F
DUll

4·233 GT40
4·239 H312·A
4·26
H324

72 x 21 x 30

float

I
I
I
X
X

5
7

120

4
5

'float
1500

4·81
DFlI
4·89
DH11
4·118 OJ 11

4
4

float
124
user

2
I

float

767 770 float

float
float

777 560 060,064
776 500
float
775 000
float

± 15V req'd

(25)
X

10·40
10-40

4·19
4·22
4·279

72 x 21 x 30

10·90
10·90
10·90

AAll·D
ADOI·D
AFCll

4
6
6

10AO

4·5
4·9
4·13

230
230
230

100
BOO
340

I
I
I

4,5
4 - 7
4

772 460
777 160
777 160

(22)

single ht

Number

1150
600
600

,30

Model

No.

2
20·80

Page

10
6
6

1.5

15·32

Bus
Loads

2.5
1.5
1.5

8.4
5

150

NPR

2.0

33 x 28 x 24
48 x 49 x 36
45 x 33 x 22

Vector

51;'

Address

(W)

1.4
6.0
3,3

PAN

230

SU
SU
SU

Pushbutton Panel

Int

772 460

18 x 20 x 24

UNIBUS

1st Reg

600

1.8
1.8
2,8

Powe! Supply

PROGRAMMING
Power
Dis

0.5
0.5
15

SPC
SPC
(DHll)

Graphics Terminal
Full Modem

Transformer

SU
SU
TT

I 115 VAC/Other
(amps)

10';'

5 1/,

Synch line Inter

~ 5V

Humid

hex ht

SPC
PAN
SPC

UNIBUS Switch

Cur needed/(supplied) __

Rei

UNIBUS Cable
Restart/Loader
Card Reader

POWER

ENVIRON'.1ENTAL
Oper
Temp

(lOA) @ -15V
1.5A @ 230 VAC
(IA) @ +15V

700

(lOA) @ -15V
8

2
17
4,5

300
2000
500

770 700
777 546 100

772 540 104

I
1
1

777 514 200
777 514 200

4
4

I
1

4·22
4·313
4·240

H720·E
H722
H742

4·240
4·240
4·240

H744
H745
H960·C

4·240 H960·D
4·245 KGll·A
4·254 KWll·L
4·255
4·258
4·261
4·261

KWll·P
LA36
LPll·R
LPll·V

rJ)~
rZ
O~

000

MECHANICAL
Model

Weight

Temp

(inches)

(Ibs)

(,C)

(%)

5';'
12 x 28 x 20
34x22x19

80
155
60

10·40
15·32

10·90
20·80

160

10-40

10·90

Code

(H x W x D)

LPS11
LS11
LT33

Lab Periph System

PAN
spc+n
FS
SPC + FS
MOD
MOD

38x19x18

MOD
MOD
SPC

single ht
single ht

Line Printer
Teletype
Electrostatic ptr

Adrs Select Module
Bus Transmitter
Bus Receiver

Bus Transceiver
Diode ROM

Cab
Incl

Rei
Humid

Description

M784
M785
M792

Oper

single ht
single ht

Word Count

Bus Control
Bus Jumper

MOD
MOD
MOD

M930
M7820
M7821

Bus Terminator
Interrupt Control
Interrupt Control

MOD
MOD
MOD

-double ht
single ht

: MEll·L

PAN
2 SU
2 SU

5';'

MFlI-U

Core Memory (8K)
Core Memory (8K)
Core Memory (16K)

MMll·L
MM11-U
MR11·DB

Core Memory (SK)
Core Memory (16K)
Bootstrap

(MF11·L)
(MF11·U)
2 SPC

MS11
PCl!
PR11

Semiconductor Mem
Paper Tape
Paper Tape (rdr)

(11/45)
SPC + PAN
SPC + PAN

10'/2
10'/2

RK05
RK11·D
RJP04

Disk Drive

PAN
SU + PAN
2 SU + FS

10'12
10%
40x31x32

RJS04
RP03
RP04

Disk & Control

Disk Drive
Disk Pack

2 SU + PAN
FS
FS

16
40 x30 x24
40x31x32

RS04
RPll-C
TAll

Disk Drive
Disk & Control
Cassette

PAN
CAB + FS
SPC + PAN

TCll-G
TMll
TJU16

DECtape & Control
Magtape & Control.
Magtape & Control

PAN + PAN
PAN + PAN
2 SU + CAB

26 + 10'/2

TU10
TU16
TU66

Magtape
Magtape
DECtape

PAN
PAN
PAN

26
26
10%

UDell
VR01
VR14

I/O Subsystem
Display
Display

CAB
PAN
PAN

lO'h
10%

30
75

VTQl
VTOS
VTSO

Display
Alphanum Term
Alphanum Term

IT
IT
IT

12 x 12 x 23
12 x 19 x 30
14 x 21 x 28

SO
55
4S

MF11-L

Disk & Control

Cur needed/(supplied)
+5V

(amps)
1.5

1.5
0.34
0.2

1.25

UNIBUS

PROGRAMMING
Power
Dis

1st Reg
Address

Int

Vector

Level

NPR

4
4

opt

Model
Number

2
1

4·268
4·280
4·286

LPSll·S
LSll
LT33

4·294
6·9
6·11

LVII
MI05
M783

6·11
6·13
4·25

M784
M785
M792

6·14
6·17
6·24

M795
M796
M920

6-24
6·25
6·29

M930
M7820
M7821

(W)

3
3
2

300
300
200

float

777 514

200

600

777 514

773 000

6A @ -15V
3.4A @ +20V

125
125
125

1
1
1

4·298
4·298
4·298

ME11·L
MFll·L
MFl1·U

0.5A @ -15V
0.5A @ +20V

125
125

1
1
2

4·298
4·298
4·25

MM11-L
MM11·U
MR11·DB

1
1
1

4·303 MS11
4·306 PC 11
4·306 PR11

1
1

4·314, RK05
4·314 RKll-D
4·326 RJP04

3.4
6.1
1.7
5.4
0.6

50
50

10-40
10·40

10-90
10·90

1.5
1.5

3
3

350
350

110
250
600

10·40
10·40
15·32

10-90
10-90
20·80

2
2

350
415
600

10·40
15-32
IS-32

10-90
20·80
20·80

120
740

10·40
15·32
10-40

10·90
20-80
20·80

X
X
X

250
500
500

15·32
15·32
15·32

20·80
20·80
20-80

X
X

450
450
80

lS-32
IS·32
15·32

20·80
20·80
20-80

10·40

10·90

X
X

5';'

•
10-40
10·40

10·90
10·90

7.5
16

1.5

6
7
1

9
9
8

Page
No.

Bus
Loads

single ht

lO'h + lO'h

I 115 VAC/Other

0.2
0.3
0.23

M795
M796
M920

Size

NUmber

LVll
M105
M783

Mounting

POWER

ENVIRONMENTAL

3 phase power

160
200
2100

0.6A @ -15V
6A @ 230 VAC
3 phase power

450
1300
2100

6A @ 230 VAC

3S0
2100
120

0.6A @ -ISV

870
1000
1000

9
8
3

1000
900
350

1
4

120
400

2.2
2
1

2S0
130
110

772 100 114
777 550 70,74
777 550 070

220
254

5
5

X
X

772 040 204

777 400

4-336
4·375
4·326

RJS04
RP03
RP04

776 710 254
777 500 260

5
6

1
1

4·356
4·375
4,385

RS04
RPll·C
TAll

777 340 214
772 520 224

6
5

X
X
X

1
1
1

4·390
4·424
4·403

TCll-G
TMll
TJU16

771 774 234

4
4

4·424 TU10
4·403 TU16
4·390 TUS6
2

4,6

e'.

4·438 UDCll
4·44S VROI
4·446 VR14
4·448 VT01
4·449 VT05
4·455 VT50

Digital Equipment Corporation
.Maynard, Massachusetts

DIGITAL EQUIPMENT CORPORATION, Corporate Headquarters: Maynard,
Massachusetts 01754, Telephone: (617) 897-5111
SALES AND SERVICE OFFICES
UNITED STATES-ALABAMA, Huntsville. ARIZONA, Phoenix and Tucson.
CALIFORNIA, EI Segundo, Los Angeles, Oakland, Ridgecrest, San Diego, San
Francisco (Mountain View), Santa Ana, Santa Clara, Stanford, Sunnyvale and Woodland
Hills. COLORADO, Englewood. CONNECTICUT, Fairfield and Meriden. DISTRICT
OF COLUMBIA, Washington (Lanham, MD) • FLORIDA, Ft. Lauderdale and Orlando.
GEORGIA, Atlanta • HAWAII, Honolulu • ILLINOIS, Chicago (Rolling Meadows) •
INDIANA, Indianapolis. IOWA, Bettendorf. KENTUCKY, Louisville. LOUISIANA,
New Orleans (Metairie) • MARYLAND, Odenton. MASSACHUSETTS, Marlborough,
Waltham and Westfield. MICHIGAN, Detroit (Farmington Hills) • MINNESOTA,
Minneapolis. MISSOURI, Kansas City (Independence) and St. Louis. NEW
HAMPSHIRE, Manchester. NEWJERSEY, Cherry Hill, Fairfield, Metuchen and
Princeton. NEW MEXICO, Albuquerque. NEW YORK, Albany, Buffalo (Cheektowaga), Long Island (Huntington Station), Manhattan, Rochester and Syracuse •
NORTH CAROLINA, Durham/Chapel Hill • OHIO, Cleveland (Euclid), Columbus and
Dayton. OKLAHOMA, Tulsa. OREGON, Eugene and Portland. PENNSYLVANIA,
Allentown, Philadelphia (Bluebell) and Pittsburgh. SOUTH CAROLINA, Columbia.
TENNESSEE, Knoxville and Nashville. TEXAS, Austin, Dallas and Houston. UTAH,
Salt Lake City. VIRGINIA, Richmond. WASHINGTON, Bellevue. WISCONSIN,
Milwaukee (Brookfield) •
INTERNATIONAL-ARGENTINA, Buenos Aires. AUSTRALIA, Adelaide, Brisbane,
Canberra, Melbourne, Perth and Sydney. AUSTRIA, Vienna. BELGIUM, Brussels.
BOLIVIA, La Paz. BRAZIL, Rio de Janeiro and Sao Paulo. CANADA, Calgary,
Edmonton, Halifax, London, Montreal, Ottawa, Toronto, Vancouver and Winnipeg •
CHILE, Santiago. DENMARK, Copenhagen. FINLAND, Helsinki. FRANCE,
Grenoble and Paris. GERMANY, Berlin, Cologne, Frankfurt, Hamburg, Hannover,
Munich and Stuttgart. HONG KONG. INDIA, Bombay. INDONESIA, Djakarta .
IRELAND, Dublin. ITALY, Milan and Turin. JAPAN, Osaka and Tokyo. MALAYSIA,
Kuala Lumpur. MEXICO, Mexico City. NETHERLANDS, Utrecht. NEW ZEALAND,
Auckland. NORWAY, Oslo. PUERTO RICO, Santurce • SINGAPORE. SWEDEN,
Gothenburg and Stockholm. SWITZERLAND, Geneva and Zurich. UNITED
KINGDOM, Birmingham, Bristol, Edinburgh, Leeds, London, Manchester and Reading
• VENEZUELA, Caracas.

printed in US A