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EK-DZ110-UG-002

February 1979

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Document:	DZ11 User's Guide
Order Number:	EK-DZ110-UG
Revision:	002
Pages:	54
Original Filename:	http://bitsavers.org/pdf/dec/unibus/EK-DZ110-UG-002_DZ11_Users_Guide_Feb79.pdf

OCR Text

DZ11
user's guide

EK-OZ110-UG-002

DZ11
user's guide

digital equipment corporation • maynard, massachusetts

Preliminary Edition, March 1977
Preliminary Edition (Rev), June 1977
1st Edition, September 1977
2nd Edition, February 1979

The drawings and specifications herein are the property of Digital Equipment
Corporation and shall not be reproduced or copied or used in whole or in part
as the basis for the manufacture or sale of equipment described herein without
written permission.

Copyright © 1977, 1979 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in
this man uaI.

Printed in U.S.A.

This document was set on DIGITAL's DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC
PDP
DECUS
UNIBUS

D ECsystem-l 0
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
lAS

CONTENTS
Page
CHAPTER 1

GENERAL DESCRIPTION

1.1
1.2
1.2.1
1.3
1.3.1
1.3.1.1
1.3.1.2
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.3.9
1.3.10
1.4
1.4.1
1.4.2
1.4.3

INTRODUCTION .............................................................................................. 1-1
PHYSICAL DESCRIPTION .............................................................................. 1-2
Configurations ............................................................................................. 1-3
GENERAL SPECIFICATIONS ......................................................................... 1-8
Outputs ........................................................................................................ 1-9
DZII-A, -B, and -E ...........................................'................................... 1-9
DZII-C, -E, and -F .............................................................................. 1-9
Inputs ........................................ '--.................................................................. 1-9
Power Requirements, DZII-A, -B, and -E .................................................... 1-9
Power Requirements, DZII-C, -D, and -F .................................................... 1-9
Environmental Requirements - All DZlls ............................................... :.. I-IO
Distortion - DZII-A, -B, and -E ................................................................. I-IO
Interrupts ................................................................................................... 1-10
Line Speed .................................................................................................. 1-10
Distance (DZII-A, -B, and -E) ................................................................... .1-ll
Distance (DZII-C, -D, and -F) ................................................................... 1-11
FUNCTIONAL DESCRIPTION ...................................................................... 1-11
PDP-II Unibus Interface ............................................................................ 1-12
Control Logic ............................................................................................. 1-12
Line Interface ............................................................................................. 1-13

CHAPTER 2

INSTALLATION

2.1
2.2
2.3
2.4
2.4.1
2.4.1.1
2.4.1.2
2.4.2
2.4.3

SCOPE ................................................................................................................ 2-I
CONFIGURATION DIFFERENCES ............................................................... 2-1
UNPACKING AND INSPECTION ................................................................... 2-1
INSTALLATION PROCEDURE ....................................................................... 2-1
H317 Distribution Panel and Static Filter Installation ................................... 2-1
EIA Option .......................................................................................... 2-1
20 rnA Option ....................................................................................... 2-2
M7819 Module Installation .......................................................................... 2-2
M7814 Module Installation .......................................................................... 2-6

CHAPTER 3

PROGRAMMING

3.1
3.1.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4

INTRODUCTION .............................................................................................. 3-1
Device and Vector Address Assignments ...................................................... 3-1
REGISTER BIT ASSIGNMENTS ...................................................................... 3-2
Control and Status Register (CSR) .................................... ,.......................... 3-2
Receiver Buffer (RBUF) ............................................................................... 3-6
Line Parameter Register (LPR) ..................................................................... 3-7
Transmit Control Register (TCR) ................................................................. 3-8

111

CONTENTS (CONT)
Page
3.2.5
3.2.6
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.S
3.4

Modem Status Register (MSR) ..................................................................... 3-9
Transmit Data Register (TDR) ..................................................................... 3-9
PROGRAMMING FEATURES ........................................................................ 3-9
Baud Rate .................................................................................................... 3-9
Character Length ........................................................................................ 3-1 0
Stop Bits ..................................................................................................... 3-1 0
Parity ......................................................................................................... 3-1 0
Interrupts ................................................................................................... 3-10
Emptying the Silo ....................................................................................... 3-11
Transmitting a Character ............................................................................ 3-12
Data Set Control ........................................................................................ 3-13
PROGRAMMING EXAMPLES ...................................................................... 3-13

APPENDIX A

DZll (M7814) TO AN ACTIVE DEVICE INSTALLATION

FIGURES
Figure No.
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
2-1
2-2
2-3
2-4
2-5
3-1
A-I
A-2

Title

Page

D Z 11 System Applications ................................................................................... 1-1
DZ11 EIA Module (M7S19), Distribution Panel (H317-E), Static Filter
(H7004C), and Cables (BC06L-OJ and BC05W -15) .............................................. 1-2
DZ11 20 rnA Module (M7S14), Distribution Panel (H317-F), Static
Filter (H7004B), and Cables (BC06K-OJ and BCOSS-15) ...................................... 1-3
DZ11 Hardware Interconnections ........................................................................ 1-4
H3271 or H327 Turnaround ................................................................................. 1-5
Test Connectors H327, H3190, H3271, and H325 ................................................ .l-6
H3190 Staggered Line Turnaround ....................................................................... 1-7
General Functional Block Diagram ................................................................... .l-12
M7S19 Address Selection ..................................................................................... 2-3
M7819 Vector Selection ........................................................................................ 2-3
BC05W -15 and BCOSS-15 Interconnection ........................................................... 2-5
M7814 Address Selection ..................................................................................... 2-6
M7814 Vector Selection ........................................................................................ 2-7
Register Bit Assignments ...................................................................................... 3-3
DZ11 (M7814) to Active Device Connection ....................................................... A-1
H319 Current Loop Receiver Schematic Diagram ............................................... A-2

TABLES
Table No.
1-1
1-2
2-1
2-2
3-1
3-2
3-3
3-4

Title

Page

DZll Model Configurations ................................................................................ 1-4
DZll Performance Parameters ............................................................................. 1-8
Items Supplied Per Configuration ......................................................................... 2-2
DZll to Terminal Wiring (Using BC04R Cable) .................................................. 2-8
CSR Bit Functions ............................................................................................... 3-5
RBUF Bit Functions ............................................................................................ 3-7
LPR Bit Functions ............................................................................................... 3-8
Baud Rate Selection Chart .................................................................................. 3-10

CHAPTER 1
GENERAL DESCRIPTION

1.1 INTRODUCTION
The DZII is an asynchronous multiplexer that provides an interface between a PDP-II processor and
eight asynchronous serial lines. It can be used with PDP-II systems in a variety of applications that
include communications processing, time-sharing, transaction processing, and real-time processing.
Local operation to terminals or computers is possible at speeds up to 9600 baud using either EIA
RS232C interfaces or 20 rnA current loop signaling. Remote operation using the public switched
telephone network is possible with DZII models offering EIA RS232C interfaces. Enough data set
control is provided to permit dial-up (auto answer) operation with modems capable of full-duplex*
operation such as the Bell models 103 or 113 or equivalent. Remote operation over private lines for
full-duplex* point to point or full-duplex* multipoint as a control (master) station is also possible.
Figure 1-1 depicts several of the possible applications for the DZII in a PDP-II system.

REMOTE

LOCAL

I TELEPHONE

--- ~ ~=- -- 1J
I
___ -e~~N=- __
I

1.. ------------.1-1

DATA SET 104

REMOTE 1
TERMINAL

TELEPHONE

U 1+-_+1 DZ11
N
SYSTEM

I
B
U

'---r----'

ITO

MODEMS
TER-

II a

N
1+----------+1 1
B
U

MINALS

I
11-4332

Figure 1-1

DZII System Applications

*The DZ 11 data set control does not support half-duplex operations or the secondary transmit and receive
operations available with some modems such as the Bell model 202, etc.

1-1

The DZ 11 has several features that provide flexible control of parameters such as baud rate, character
length, number of stop bits for each line, odd or even parity for each line, and transmitter-receiver
interrupts. Additional features include limited data set control, zero receiver baud rate, break generation and detection, silo buffering of received data, module plug-in to hex SPC slots, and line turnaround.
Each DZII module provides for operation of eight asynchronous serial lines. Since the module interfaces to these channels with a 16-line distribution panel, 2 DZII modules can be used with 1 panel.
Also note that the two versions of the DZII (EIA or 20 rnA output) consist of different module and
panel types. This fact allows a system to mix EIA and 20 rnA by using multiple DZlls.

1.2 PHYSICAL DESCRIPTION
The DZII (8-line configuration) comprises a single hex SPC module and a 13.34 cm (5.25 in), unpowered distribution panel, connected by a 4.6 m (15 ft) ribbon cable. Several types of interconnecting
cables are used between the distribution panel and the modem or terminal, depending on the device. A
16-line configuration uses two modules and a single distribution panel connected by two ribbon cables.
The DZII modules, cables, static filters,· and distribution panel are shown in Figures 1-2 and 1-3. The
subsequent paragraphs present a detailed description of the physical and electrical specifications of the
various DZII options and configurations.

DZ11 (M7819-EIA)

CABLE
- - - - - - - - - (BC06L-OJ)

Figure 1-2

DZII EIA Module (M7819), Distribution Panel (H317-E), Static Filter (H7004C),
and Cables (BC06L-OJ and BC05W -15)

·Static filters are not supplied with earlier modules.

1-2

OZ11 (M7814-20MA)

CABLE
_-------(BC06K-OJ)

8884-2

Figure 1-3

DZll 20 rnA Module (M7814), Distribution Panel (H317-F), Static Filter (H7004B),
and Cables (BC06K -OJ and BC08S-15)

1.2.1 D Z 11 Configurations
The DZII can be supplied in six different configurations, each designated by a suffix letter (A-F). The
DZII-A and the DZII-B options are EIA devices with partial modem control. The DZII-E is the
combination of a DZll-A and a DZII-B. The DZII-C and the DZII-D are 20 rnA loop output
versions. The DZII-F is the combination of a DZII-C and a DZII-D. Table 1-1 lists the various
option configurations and Figure 1-4 shows the required hardware for the various configurations.
The DZII-A and DZII-B each use an M7819 module that plugs into slot 2 or 3 of a DDII-B or any
system unit with a hex SPC slot; however, slots in the PDP-l 1/20 BAll box cannot be used. The
H317-E distribution panel provides 16 communication lines from 2 M7819 modules (8 lines per module) and is included with the DZII-A and DZII-E configurations. The H317-F distribution panel
provides 16 lines for the DZtl-C and DZII-F configurations, which use the M7814 modules (20 rnA
system). The distribution panels require no power and can be mounted in an H960 48.26 cm (19 in)
cabinet. Static filters (H7004C, EIA, and H7004B, 20 rnA) are used to prevent problems caused by
electrostatic discharge. A 50-conductor, flat, shielded cable, BC05W-15, connects from the M7819
module to the static filter. Cable BC06L-OJ connects the static filter to the EIA distribution panel. A
40-conductor, flat, shielded cable, BC08S-15, connects from the M7814 module to the static filter.
Cable BC06K-OJ connects the static filter to the 20 rnA distribution panel.

1-3

PDP-11

- **..
I
I

UNIBUS

I
r---'--'----~- -t
I
H317-E

8LINES

_:.J
-

BC03M

CUSTOMER SUPPLIED
CABLE

103A OR
EQUIVALENT

TO TELEPHONE
LINES
NOTE

* Not included with DZ11, must be
ordered separately.

** DZll-E=DZll-A and DZ11-B

11-4333

DZll-F= DZll-C and DZ11-D

Figure 1-4

DZII Hardware Interconnections

Table 1-1

DZll Model Configurations

Model

Output

Module

Panel

DZII-A
DZII-B
DZll-E
DZII-C
DZI1-D
DZI1-F

EIA
EIA
EIA
20 rnA
20 rnA
20 rnA

M7819
M7819
M7819 (2)
M7814
M7814
M7814 (2)

H317-E
H317-E
H317-F
H317-F

Test
Connector

Cables

Static
Filter

H325/H327
H327
H325/H327
H3190
H3190
H3190

BC05W, BC06L
BC05W, BC06L
BC05W (2), BC06L (2)
BC08S, BC06K
BC08S, BC06K
BC08S (2), BC06K (2)

H7004C
H7004C
H7004C
H7004B
H7004B
H7004B

NOTES
H327 will be replaced by H3271 in later units.
H3190 is not supplied with early units. The shipping
list will indicate which test connector, if any, is supplied.
H7004C, H7004B, BC06L, and BC06K are not supplied with early units. The shipping list will indicate
which static filter and cable, if any, are supplied.

1-4

Modems or terminals are connected to the H317-E EIA panel by cables that attach to 16 DB25P cinch
connectors. These cables are not provided with the DZll. The BC05D-25 cable is recommended for
data set interconnections, and the BC03M cable is recommended for local terminal interconnections.
The BC05W-15 cable carries the data and control signals for all eight lines. Connections between
terminals and the H317-F 20 rnA panel are by customer-supplied cables to 16 (4-screw) terminal strips.
The data signals for all eight lines are carried to the distribution panel by the BC08S-15 cable.
Two accessory test connectors, H325 and H3271 *, are provided with each DZI1-A. The H325 plugs
into an EIA connector on the distribution panel or on the end of the BC05D cable to loop back data
and modem signals onto a single line. The H3271 connects to the module with the BC05W cable (two
M7819 modules can be connected to one H3271) and staggers the data and modem lines as shown in
Figure 1-5. The connectors are shown in Figure 1-6.
The 20 rnA (M7814 module) options also have a staggered turnaround connector (H3190t). The
H3190 connects to the M7814 using the BC08S cable and staggers the lines as shown in Figure 1-7.
A priority level 5 insert plugs into a socket on the M7819 or M7814 module to establish interrupts at
level 5 on the Unibus.
Maximum configuration allows 16 DZII modules per Unibus.

TRANS 0 - - - - - - - - - - - - - - . . . REC 1

OTR 0 - - - - - - _ - - - - - - - . . : RI 1
~------~- C01

0------. . . .

RI0---------~----------•• OTRI

REC0--------------... TRANS

NOTE:
Lines 2 8 3, 4 8 5 and 6 8 7 are
staggered the same way.
11-4334

Figure 1-5

H3271 or H327 Turnaround

*This is a new item replacing the H327. The H327 may be used until the H3271 becomes available. The H327
plugs directly into 11 on the M7819 module.
tThis is a new item; check the shipping list for availability.

1-5

H327

H3190

H3271

H325
8639-1

Figure 1-6 Test Connectors H327, H3190, H3271, and H325

1-6

20MA LOOP

+
LINE 0
TRANSMITTER

LINE 1
RECEIVER

20MA LOOP

LINE 1
TRANSMITTER

LINE 0
RECEIVER

LINES 2 & 3, 4 & 5, AND 6 & 7 ARE STAGGERED THE SAME WAY
11-5141

Figure 1-7

H3190 Staggered Line Turnaround

1-7

1.3 GENERAL SPECIFICATIONS
The following paragraphs contain electrical, environmental, and performance specifications for all
, DZII configurations. Table 1-2 lists the performance parameters of the DZII.

Table 1-2 DZll Performance Parameters
Parameter

Description

Operating Mode

Full-Duplex

Data Format

Asynchronous, serial by bit, 1 start and I, 1-1/2 (S-level codes only), or 2
stop bits supplied by the hardware under program control

Character Size

S, 6, 7, or 8 bits; program-selectable. (Does not include parity bit.)

Parity

Parity is program-selectable. There may be none, or it may be odd or even.

Bit Polarities

Unibus

Interface

EIA Out

20mA Loop

Data Signal

Low = 1
High = 0

High = 1
Low = 0

Low = 1 = Mark
High = 0 = Space

O-SmA
IS-20 rnA

Control Signal

Low == 1
High = 0

High = 1
Low = 0

Low = OFF
High = ON

Order of Bit

Transmission/reception low-order bit first

Baud Rates

SO, 7S, 110, 134.S, ISO, 300, 600, 1200, 1800, 2000, 2400, 3600, 4800, 7200,
and 9600

Breaks

Can be generated and detected on each line

Throughput

21,940 characters/second = (bits/second X No. Lines
X direction)/(Bits/Character)
Example: (9600 X 8 X 2)/7 = 21,940 characters/second
NOTE
The theoretical maximum is 21,940. Adual throughput depends on other factors such as type of CPU,
system software, etc.

1-8

1.3.1

Outputs

1.3.1.1 DZII-A, -B, and -E - Each line provides voltage levels and connector pinnings that conform
to Electronic Industries Association (EIA) standard RS232C and CCITT recommendation V.24. The
leads supported by this option are:*
Circuit AA (CCITT 101)
Circuit AB (CCITT 102)
Circuit BA (CCITT 103)
Circuit BB (CCITT 104)
Circuit CD (CCITT 108.2)
Circuit CE (CCITT 125)
Circuit CF (CCITT 109

Pin 1
Pin 7
Pin 2
Pin 3
Pin 20
Pin 22
Pin 8

Protective Ground
Signal Ground
Transmitted Data
Received Data
Data Terminal Ready
Ring Indicator
Carrier

NOTE
Signal ground and protective ground are connected.
1.3.1.2 DZII-C, -D, and -F - Each line is a 20 rnA current loop used for connection to local terminals. (No data set control is provided.) All lines are active and, therefore, can only drive a passive
device. However, a pair of H319 20 rnA receivers for each line may be used to convert from active to
passive operation in order to allow the DZ11 to drive an active device. Refer to Appendix A for
connection details.
1.3.2 Inputs
The PDP-II Unibus is the input for all DZ11s. The DZ11-A, -B, -C, and -D present one unit load to
the Unibus and the DZ11-E and -F present two unit loads to the Unibus. Four ac loads per module are
presented to the Unibus in the EIA version and five ac loads per module are presented in the 20 rnA
version.
1.3.3 Power Requirements, DZII-A, -B, and -Et
Typical

Maximum

(A)

2.2
0.13
0.1

2.5
.0.15
0.13

at +5.0 Vdc
at -15.0 Vdc
at +15.0Vdc

1.3.4 Power Requirements, DZII-C, -D, and -Ft
Typical

Maximum

(A)

2.1
0.4
0.12

2.3
0.42
0.15

at +5.0 Vdc
at -15.0 Vdc
at + 15.0 Vdc

*Circuit CA (CCITT 105 - Request to Send) is connected to circuit CD (DTR) through ajumper on the distribution panel. This allows control of the Request to Send line for full-duplex modem applications that use the R TS
circuit.
tDZll-E and DZll-F are twice the above given values.

1-9

1.3.5

Environmental Requirements - All DZlls

Class C Environment Operating
Temperature

50 to 50 0 C* (41 0 to 122 0 F)

Relative Humidity

10 to 95%, with a maximum wet bulb of 32 0 C (90 0 F) and a
minimum dewpoint of 2 0 C (36 0 F)

Cooling
DZII-A, -B, -C, and -D
DZII-E and -F

Air flow 1.416 l/second (3 cu. ft/min)
Air flow 2.832 l/second (6 cu. ft/min)

Heat Dissipation
DZll-A and -B
DZII-E
DZ ll-C and -D
DZII-F

3.99 gocaljsecond (57 Btu/hr)
7.98 g·cal/second (114 Btu/hr)
3.85 gocaljsecond (55 Btu/hr)
7.7 gocal/second (110 Btu/hr)

1.3.6 Distortion - DZII-A, -B, and -E
The maximum "space to mark" and "mark to space" distortion allowed in a received character is 40
percent.
The maximum speed distortion allowed in a received character for 2000 baud is 3.8 percent. All other
baud rates allow 4 percent. The maximum speed distortion from the transmitter for 2000 baud is 2.2
percent. All other baud rates have less than 2 percent.
1.3.7

Interrupts
RDONE

Occurs each time a character appears at the silo output.

Silo Alarm. Occurs after 16 characters enter the silo. Rearmed by reading the
silo. This interrupt disables the RDONE interrupt.

TRDY

Occurs when the scanner finds a line ready to transmit on.
NOTE
There are no modem interrupts.

Normally, a level 5 priority plug is supplied. The interface level can be modified to level 4, 6, or 7 by
using the proper priority plug.
1.3.8 Line Speed
The baud rate for a line (both transmitter and receiver) is program-selectable. Also, the receiver for
each line can be individually turned on or off under program control. (See Table 1-2 for a list of
available baud rates.)

*Maximum operating temperature is reduced 1.8 0 C per 1000 meters (1.0 0 F per 1000 feet) for operation at
altitudes above sea level.

1-10

1.3.9 Distance (DZII-A, -B, and -E)
The recommended distance from computer to DZll is 15 m (50 ft) at up to 9600 baud with a BC05D
cable or equivalent. Operation beyond 15 m (50 ft) does not conform to the RS232C or CCITT V.24
specifications. However, operation will often be possible at greater distance depending on the terminal
equipment, type of cable, speed of operation, and electrical environment. Reliable communication
over long cables depends on the absence of excessive electrical noise. For these reasons, DIGITAL
cannot guarantee error-free communication beyond 15 m (50 ft). However, the EIA versions of the
DZll may be connected to local DIGITAL terminals and most other terminals at distances beyond 15
m (50 ft) with satisfactory results if the terminal and computer are located in the same building, in a
modern office environment. Shielded twisted pair wire (Belden 8777 or equivalent) is recommended
and is used in the BC03M null modem cable.
With cables made with shielded twisted pair wire, such as the Belden 8777, the following rate/distance
table may be used as a guide. This chart is for informational purposes only and is not to be construed
as a warranty by Digital Equipment Corporation of error-free DZll operation at these speeds and
distances under all circumstances.
90 m (300 ft) at 9600 baud
300 m (1000 ft) at 4800 baud
300 m (1000 ft) at 2400 baud
900 m (3000 ft) at 1200 baud
1500 m (5000 ft) at 300 baud
NOTE
The ground potential difference between the DZll
and terminal must not exceed 2 V. This requirement
will generally limit operation to within a single building served by one ac power service. In other cases, or
in noisy electrical environments, 20 rnA operation
should be used.
1.3.10 Distance (DZII-C, -D, and -F)
The length of cable that may be used reliably is a function of electrical noise, loop resistance, cable
type, and speed of operation. The following chart is given as a guide; however, there is no guarantee of
error-free operation under all circumstances.
Speed (Baud)

Belden 8777, 22 AWG,
shielded, twisted pairs
(shields floating)
(DEC P /N 9107723)

22 AWG, 4 conductor
inside station wire
(DEC P /N 9105856-4)

9600
4800
2400
1200 and below

150 m (500 ft)
300 m (1000 ft)
600 m (2000 ft)
1200 m (4000 ft)

300 m (1000 ft)
540 m (1800 ft)
900 m (3000 ft)
1500 m (5000 ft)

1.4 FUNCTIONAL DESCRIPTION
The following paragraphs present a general description of DZl1 operation. Figure 1-8 is a general
functional block diagram that divides the DZll into three basic components: Unibus interface, control
logic, and line interface.

1-11

Ico-;;;o~ - l

DATA

u
N
I
B

ADDRESS

PDP~11

INTERFACE

u
S
CONTROL

I
I
I
I
I

SCANNER

I
I

LINE
INTERFACE

I
I

REGISTERS

8
LINES

I
I
I
I
L ____ J
11-4335

Figure 1-8

General Functional Block Diagram

1.4.1 PDP-II Unibus Interface
The PDP-II Unibus interface component of the DZII handles all transactions between the Unibus
and the DZII control logic. The Unibus interface performs three functions: data handling, address
recognition, and interrupt control. In its data handling function, the interface routes data to and from
the various registers in the control logic and provides the voltage conditioning necessary to transmit
and receive data to and from the PDP-II Unibus. The address recognition and control logic activates
the proper load and read signals when it recognizes its preselected address on the Unibus. These signals
are used by the data handling function to route the incoming and outgoing data to the desired locations. The interrupt control function initiates and controls interrupt processing between the DZII and
the PDP-II processor.
1.4.2 Control Logic
The control logic provides the required timing and control signals to handle all transmitter and receiver operations. The control logic can be divided into two major sections: the scanner and the registers.

The scanner continuously examines each line in succession and, based on information from the line
interface and the registers, generates signals that cause data to flow to or from the appropriate line.
The scanner comprises a 5.068 MHz oscillator (clock), a 64-word FIFO receiver buffer, a 4-phase
clocking network, and other control generating logic.

1-12

The DZ 11 uses four device registers in a manner that yields six unique and accessible registers, each
having a 16-bit word capacity. The six discrete registers temporarily store input and output data,
monitor control signal conditioning, and establish DZII operating status. Depending on their functions, some of the registers are accessible in bytes or words; others are restricted to word-only operation. Registers can be read or loaded (written), depending on the operation. The ability to read or
write a register allows the use of two of the device registers as four independent registers.
1.4.3 Line Interface
Two of the most important operations in the DZII are the conversions from serial-to-parallel and
parallel-to-serial data formats. These conversions are required since the DZII is located between the
PDP-II Unibus (a parallel data path) and either local terminals or telephone lines (serial data paths).
Conversions for each line in the DZII are performed by independent universal asynchronous receivertransmitter (U AR T) integrated circuits. Another component of the line interface, the line receiver or
driver, converts the TTL voltage levels in the DZII so that they correspond to those in the external
device input lines (modem or terminal).

1-13

CHAPTER 2
INSTALLATION

2.1 SCOPE
This chapter contains the procedures for the unpacking, installation, and initial checkout of the DZ11
Asynchronous Multiplexer.
2.2 CONFIGURATION DIFFERENCES
The DZll can be supplied with or without a distribution panel. The DZII-B and -D do not have
distribution panels. The following list describes the variations.
DZll-A
DZll .. B
DZ11-C
DZI1-D
DZll .. E
DZ11-F

EIA level conversion with distribution panel (8 lines)
EIA level conversion without distribution panel (8 lines)
20 rnA loop conversion with distribution panel (8 lines)
20 rnA loop conversion without distribution panel (8 lines)
DZI1-A and DZI1-B (l6lines)
DZl1-C and DZI I-D (16 lines)

2.3 UNPACKING AND INSPECTION
The DZI 1 is packaged in accordance with commercial packaging practices. First, remove all packing
material and check the equipment against the shipping list. (Table 2- 1 contains a list of supplied items
per configuration.) Report damage or shortages to the shipper immediately and notify the DIGITAL
representative. Inspect all parts and carefully inspect the module for cracks, loose components, and
separations in the etched paths.
2.4 INSTALLATION PROCEDURE
The following paragraphs should be followed to install the DZ11 option in a PDP- II system.
2.4.1 H317 Distribution Panel and Static Filter Installation
Install the H317 distribution panel and static filters according to unit assembly drawing D-UA-DZI 10-0.
2.4.1.1 EIA Option - For the DZ11-A or DZ11-E option, check to ensure that all of the machineinsertable jumpers on the distribution panel are in place. (See Drawing E-UA-5411928 .. 0-0 for jumper
locations.) These jumpers are in anticipation of future use of the DZll with modems other than the
103; however, two of the jumpers are now functional. The jumper labeled DTR (refer to D-CS5911928-0-1) connects DTR to pin 4 or Request to Send.'This allows the DZI 1 to assert both DTR
and RTS if using a modem which requires control of RTS. The jumper labeled BUSY is also connected
to the DTR. lead for use in modems that implement the Force Busy function. This jumper should
normally be cut out unless the modem has the Force Busy feature and the system software is implemented to control it.

2-1

Table 2-1

Items Supplied Per Configuration

Quantity

Description

I
I
I
I
I
I
I
I

M7819 module
H7004C static filter (EIA)
H3271 test connectort
BC06L-OJ filter cable (EIA)
H317-E distribution panel assembly
H325 test connector
BC05W-15 cable
Print set (B-TC-DZII-0-6) DZII, A, B, and C
order number MPOOl32
Software kit
Panel and static filter mounting hardware set
Priority insert (5)
DZII User's Manual (EK-DZIIO-OP-OI)
M7814 module
H7004B static filter (20 rnA)
BC08S cable
BC06K-OJ filter cable (20 rnA)
H317-F distribution panel assembly
Print set (B-TC-DZII-O-II) DZII, C, D, and F
order number MP00253
H3190 test connectort

X
X
X
X
X
X
X
X

X
X

*
*

I
I
I
I
I
I
I
I
I
I
I

X
X
X
X

X
X

X
X
X
X

X
X
X

X
X
X
X
X
X
X
X
X
X
X

X
X
X

X
X
X
X
X

*
*
*
*

X
X

*Shipment contains two of the items listed.
tNew item: An H327 will be shipped with each M7819 unit until the H3271 becomes available. The shipping list

will indicate which test connector is supplied.
:j:New item: The shipping list will include the H3190 test connector when supplied.

2.4.1.2 20 mA Option - For the DZII-C or DZII-F option, refer to D-UA-5411974-0-0. Each line
has a jumper on the distribution panel (WI through W16) which should be in if the terminal operates
at 300 baud or less. The jumper should be removed for higher baud rates.
2.4.2 M7819 Module Installation
To install the M7819 module, perform the following procedure.
I. Ensure that the priority insert (level 5) is properly seated in socket E52 on the M7819 module(s). (Refer to drawing D-UA-M7819-0-0.)
2. Refer to Paragraph 3.1.1 for descriptions of the address assignments. Set the switches at E81
so that the module will respond to its assigned address. When a switch is closed (on), a
binary 1 is decoded. When a switch is open (off), a binary 0 is decoded. Note that the switch
labeled I corresponds to bit 3, 2 corresponds to bit 4, etc. (See Figure 2-1.)

2-2

A12

All

Al0

E81

OFF
NOTE:
Address -160000 - A12 through A3, OFF
160010 - A12 through A4, OFF; A3, ON
177770 - A12 through A3,_ ON
(OFF= LOGICAL 0. ON=LOGICAL 1)

MSB
14

I I I I l I I

I 11 I 10

LSB
3

SWITCHES

I '------.y------

'---v------'
o TO 7

6 OR 7

(0211 REGISTERS)
11-4563

Figure 2-1

M7819 Address Selection

3. Vector selection is accomplished by the 8-position switch at Ell. Switch positions I and 8
are not used. Switch position 2 corresponds to vector bit 3, 3 corresponds to vector bit 4, etc.
When a switch is closed (on), a binary 0 is decoded. When a switch is open (off), a binary I is
decoded. Note that this is opposite of the address switch decoding. (See Figure 2-2.)

E11
OFF

OFF

NOTE:
ON
OFF

LOGICAL 0
LOGICAL 1

VECTOR
300
310

ON
ON

V5
V7
V6
OFF OFF ON
OFF OFF ON

V4
ON
ON

V3
ON
OFF

770

OFF

OFF OFF

OFF

11-5314

Figure 2-2

M7819 Vector Selection

2-3

4. If the DZII is supplied with the H3271 test connector, perform step 4. If the H327 test
connector is supplied, go to step 5.
a.

Insert the module(s) into an SPC slot and connect the flat shielded cable (BC05W-15),
ribbed side up, to Jl on the module(s). Connect the other end of the cable, ribbed side
up, to the H3271.*
CAUTION
Insert and remove modules slowly and carefully to
avoid snagging module components on the card
guides and changing switch settings inadvertently.

Run the DZll diagnostic in staggered mode to verify module operation. Refer to
MAINDEC-II-DZDZA, the diagnostic listing. Run at least two passes without error.

Remove the BC05W-15 cable(s) from the H3271 and install the cable(s) (with smooth
side up) to the static filter socket(s) on the back of the H317-E distribution panel. Refer
to D-UA-DZII-O-O and Figure 2-3.

Proceed to step 8.

5. Install the H327 test connector in Jl (the cable connector at the top of the M7819) and align
arrows for proper connection.
6. Insert the M7819 in its SPC slot and run the DZII diagnostic in the staggered mode to verify
module operation. Refer to MAINDEC-II-DZDZA, the diagnostic listing for the correct
procedure. Run at least two passes without error.
CAUTION
Insert and remove modules slowly and carefully to
avoid snagging module components on the card
guides and changing switch settings inadvertently.
7.

Replace the H327 test connector with the BC05W-15 cable and observe the same caution as
in step 6. Install the other end of the cable at the static filter socket on the back of the
distribution panel. Refer to Figure 2-3 and D-UA-DZII-0-0.

8. Connect the H325 (or H315) test connector on the first line and run the diagnostics in
external-mode. The test connector may be installed on the H317 -E distribution panel or on
the end of a BC05D cable.
Repeat this step for each line.
9.

Run DEC/XlI system exerciser to verify the absence of Unibus interference with other
system devices.

*The H3271 has connections for two H7819 cables.

2-4

STATIC
FILTER SOCKET

SMOOTH
SIDE
BC05W -15 CABLE
OR
BC08S-15 CABLE

OUTPUT BOARD

11-4327

Figure 2-3

BC05W-15 and BC08S-15 Interconnection

10. The DZ 11 is now ready for connection to external equipment. If the connection is to a local
terminal, a null modem cable must be used. Use the BC03M or BC03P null modem cables
for connection between the distribution panel and the terminal. The H312-A null modem
unit may also be used with two BC05D EIA cables (one on each side of the null modem
unit). If connection is to a BellI 03 or equivalent modem, a BC05D cable is required between
the distribution panel and the modem. All of the cables mentioned must be ordered separately as they are not components of a standard DZII shipment. When possible, run the
diagnostic in echo test mode to verify the cable connections and the terminal equipment.

2-5

2.4.3

M7814 Module Installation

To install the M7814 module, perform the following procedure.
1. Ensure that the priority insert (level 5) is properly seated in socket E41. Refer to D-UAM7814-0-0.
2. Refer to Paragraph 3.1.1 for a description of address assignments. Set the switches at E72 so
that the module will respond to its assigned address. When a switch is closed (on), a binary 1
is decoded. When a switch is open (off), a binary 0 is decoded. Note that the switch labeled 1
corresponds to bit 3, 2 to bit 4, etc. (See Figure 2-4.)

A12

A11

A10

ON
E72
OFF
NOTE:
Address 160000 - A12 through A3, OFF
160010 - A12 through A4, OFF; A3, ON
177770 - A12 through A3, ON
(OFF=LOGICAL (2), ON=LOGICAL 1)

MSB

LSB

12\11

110 1 9

SWITCHES
I

I '------.r------

~
o TO 7
(DZ11 REGISTERS)

6 OR 7

11-4562

Figure 2-4

M7814 Address Selection

3. Vector selection is accomplished by an 8-position switch at E81 on the module(s). When a
switch is closed (on), a binary 0 is decoded. When a switch is open (off), a binary 1 is
decoded. Note that this is the opposite of the address switch decoding. Also, note that switch
positions 7 and 8 are not used and switch 6 corresponds to bit 3, 5 to bit 4, etc. (Refer to
Figure 2-5.)
CAUTION
Insert and remove modules slowly and carefully to
avoid snagging module components on the card
guides and changing switch settings inadvertently.

2-6

E81

OFF

NOTE:
ON
OFF

LOGICAL 0
LOGICAL 1

VECTOR
300
310

V8
ON
ON

V7
OFF
OFF

V6
OFF
OFF

V5
ON
ON

V4
ON
ON

V3
ON
OFF

770

OFF

OFF
11-5140

Figure 2-5

M7814 Vector Selection

4. Insert module(s) into their assigned SPC slot(s). Connect the BC08S cable, with ribbed side
up, to J1 on the module(s).
5. Skip this step if you have an H3190 test connector; otherwise perform the following.
a.

Connect the other end of the BC08S cable to the static filter on the back of the distribution panel (H317-F) with smooth side up. Refer to Figure 2-3 and D-UA-DZI1-0-0.

Run the DZII diagnostic in internal (maintenance) mode for two error-free passes.
Refer to MAINDEC-11-DZDZA, the diagnostic listing, for the proper procedure.

Proceed to step 9.

6. Connect the other end of the BC08S cable, with smooth side up, to the H3190 test connector.
7. Run the DZ11 diagnostic in staggered mode for two error-free passes. Refer to MAINDECll-DZDZA, the diagnostic listing, for the correct procedure.
8. Remove the BC08S cable from the H3190 test connector and plug it into the static filter
socket on the back of the distribution panel (H317-F) with smooth side up. Refer to Figure
2-3 and D-UA-DZ11-0-0.
9. Run the DEC/XII system exerciser to verify the absence of Unibus interference with other
system devices.

2-7

10. The DZII is now ready for connection to passive external equipment. This is accomplished
with a customer-supplied cable. Most DIGITAL terminals use a BC04R cable as shown in
Figure 2-6. Table 2-2 shows terminal connections for connecting VT05, LA30, or LA36 to
DZII. Run an echo test to verify terminal connections.
NOTE
For customer terminals that can only transmit or re..
ceive in a single direction, the echo test cannot be
run.
If the DZ II is to be connected to an active device, a pair of H319s are required. Refer to
Appendix A for details on this connection.

11-2700

Figure 2-6

BC04R Cable

Table 2..2 DZII to Terminal Wiring (Using BC04R Cable)
VT05 Wiring
Mate..N..Lok

VT05
Signal

Color

DZII
Terminal No.

5
2
3
7

Terminal + R CV
Terminal-RCV
Terminal - XMIT
Terminal +XMIT

Black
White
Green
Red

4 (XMIT+)
3 (XMIT-)
2 (REC-)
I (REC+)

2-8

Table 2-2

DZll to Terminal Wiring (Using BC04R Cable) (Cont)
LA30, LA36 Wiring

Mate-N-Lok

LA30,LA36
Signal

Color

DZll
Terminal No.

5
2
3
7

Terminal + XMIT
Terminal - XMIT
Terminal-REC
Terminal +REC

Black
White
Green
Red

1 (REC+)
2 (REC-)
3 (XMIT-)
4 (XMIT+)

NOTE
Terminal RCV is connected to DZll XMIT. Terminal XMIT is connected to DZll RCV. Polarity
should always be + to + and - to - for both XMIT
and RCV.
In addition, post 1 is located at the top of the terminal block on the distribution panel and goes in sequence to post 4 at the bottom of the terminal block.

2-9

CHAPTER 3
PROGRAMMING

3.1 INTRODUCTION
This chapter provides basic information for programming the DZ11. A description of each DZll
register, its format, programming constraints, and bit functions are presented to aid programming and
maintenance efforts. Special programming features are also presented in this chapter.
3.1.1. Device and Vector Address Assignments
The DZ11 's device and vector addresses are selected from the floating vector and device address space.
NOTE
The device floating address space is 1600108 to
1637768 • The vector floating address space is 3008 to
7768 •
Its floating address space follows the DJ11, DHll, DQll, DUll, DUPll, LKll, and DMCll.
Its floating vector space follows the DC11; KL11jDL11-A, -B; DP11, DM11-A; DN1l; DM11-BB
and other modem control vectors; DR11-A; DR11-C; PA611 reader, PA611 punch; DT11; DX11;
DLll-C, -D, -E; DJ11; DH11; GT40; LPS11; DQ11; KW11-W; DUll; DUP11; DV11; LKI1-A;
DWUN; and DMCll. If a DZll is installed in a system with any of the above listed options, then its
assigned vector and device address should follow the vector and device address of the other options.
Two examples follow. First, the simplest case where there is only one DZ11.
Option

Address

GAP
GAP
GAP
GAP
GAP
GAP
GAP
DZll
GAP

160010
160020
160030
160040
160050
160060
160070
160100
160110

Vector

Comment
No DJlls
NoDH11s
No DQlls
No DUlls
No DUP11s
No LKlls
No DMClls

300
No more DZ11s

3-1

Next, a system with one DJll, one DH11, one GT40, one KWll~W, and two DZlls.
Option

Address

Vector

DJll
GAP
GAP

160010
160020
160030

300

DH11

160040
160050
160060

310

GAP
GT40

No more DJ11s
DH 11 must start on an address boundary that is a multiple of 20.
No more DHlls
GT40 address is not in the floating address space.
KWII-W address is not in the floating
address space.
No DQ11s
NoDUlls
No DUPlls
No LKlls
No DMClls

320

KWII-W
GAP
GAP
GAP
GAP
GAP
DZ11
DZll
GAP

Comment

330
160070
160100
160110
160120
160130
160140
160150
160160

340
350
No more DZlls

3.2 REGISTER BIT ASSIGNMENTS
A comprehensive pictorial of all register bit assignments is shown in Figure 3-1. The four device
registers (DRO, DR2, DR4, and DR6) are subdivided to form six unique registers. This subdivision is
accomplished in DR2 and DR6 by assigning read-only (RO) or write-only (WO) status to each register. Since the reading and writing of DR2 and DR6 accesses two registers, PDP-II processor instructions that perform a read-modify-write (DATIP) bus cycle cannot be used with DR2 or DR6. Also,
DR2 permits only word instructions, but either byte or word instructions may be used with DR6. DRO
and DR4 have no programming constraints. In all register operations, the following applies: read-only
bits are not affected by an attempt to write, and write-only and "not-used" bits appear as a binary 0 if
a read operation is performed. Specific programming constraints for each register are discussed in the
following paragraphs. A description of each bit function is presented in Tables 3-1 through 3-3.
3.2.1 Control and Status Register (CSR)
The control and status register (CSR) contains the states of flags and enable bits for scanning, processor interrupts, clearing, and maintenance. The 16-bit CSR has no programming constraints. The format is depicted in Figure 3-1, and bit functions are described in Table 3-1. Write-only and "not-used"
bits are read as zeros by the Unibus, and read-only bits are not affected by write attempts.

3-2

MSB
15
RO

b---

ORO

CONTROL
& STATUS
(CSR)

RECEIVER
BUFFER
(RBUF)
OR2
LINE
PARAMETER
(LPR)

TROY

TRANSMIT >J:
CONTROL
(TCR)

MODEM
STATUS
(MSR)

>}:

RW
--- - rRO

....

TIE

ryj

r--~

SAE

RO
RO
RO
RO
1 - - - - -1----DATA
FRAM
PAR
VALID OVRN ERR
ERR

W~~
..:5~

~---

..'::J':j

WO
RX
ON

..:5~

1 - - - I- - - - 1 - - -

OTR
6

~--- 1 - - - -

MSE

~---

CLR

MAINT

LSB
00

w~ ~
~

..:5

RO
RO
1-------

RBUF
02

RBUF
01

..:5

LINE
B

LINE
A

RBUF
07

RBUF
06

RBUF
05

RBUF
04

RBUF
03

WO
WO
WO
- - - - - - - - ---- 1 - - - - ----- ------ODD PAR
STOP CHAR
CHAR

FREQ
0

FREO
C

FREO
B

FREQ

PAR

ENAB

CODE

LGTH
B

LGTH
A

- - - - ---

1----

OTR
4

OTR
3

OTR
2

1-----1-- - - - 1 - - - - ---

RW
--_.
-RW-- RW

I- - -

LINE
ENAB
4

I- -

CO
2

CO
1

1 - - - - - 1 - - - - 1 - - - - ~--- ~--- ~-- 1--- -

BRK
1

' RO

1""""--

CO
0

RI7

RI6

RI5

- - I- - -

1-----

BRK
0

---

I- - - - 1 - - - -

1 - - - - I- - - -

TBUF
7

TBUF
6

1----

LINE
C

RW __ I-FLW__ I- RW __ _ RW_

LINE LINE LINE
ENAB ENAB ENAB
7
6
5

CO
3

BRK
2

OTR
0

CO
4

BRK
3

RO
RO
RO
RO
----------- ---

OTR
1

CO
5

BRK
4

RW
RW
----

.5'

OTR
5

BRK
5

RIE.··

~---

CO
6

BRK
6

1----

RO
RO
---RX
RX

CO
7

BRK
7

--- RW

RO
RX
LINE
C

RW
RW
RW
1-----1-----1------ RW

OTR
7

TLiNE TLiNE TLiNE ROONE
A
C
B

RW
RW
I- - - -

OR6
TRANSMIT
DATA
(TOR)

~--- r---

OR4

BYTES
HIGH LOW
08
07

TBUF
5

---

TSUF
4

LINE
A
~RW

~--

LINE
ENAB
3

LINE
ENAB
2

LINE
ENAB
1

LINE
ENAB
0,

RI3

RI2

RI1

RIO

TBUF
2

TBUF
1

rBUF
0

r----- r-- - - roo - - - ,....---

RI4
WO

LINE
B

RBUF
DO

WO
I- -

---

TSUF
3

r - - - - t - - - - 1-"- - -

*The high byte of the TCR (Data Terminal Ready) and the MSR are not used with the 20 mA options.
11-5313

Figure 3-1

Table 3-1

CSR Bit Functions

Bit

Title

00-02

Not used

Maintenance (MAINT)

A read/write bit that, when set, causes the serial
output data from the transmitter to be fed back as
serial input data to the receiver. All lines are turned
around. Cleared by BUS INIT and CLR.

Clear (CLR)

A read/write bit that fires a one-shot to generate a
15 fJ,S reset which clears the receiver silo, all
U ARTs, and the CSR. After a CLR is issued, the
CSR and line parameters must be set again. CLR
in progress is indicated by CLR = 1. Modem control registers are not affected, nor are bits 00
through 14 of RBUF.

Master Scan Enable

A read/write bit that activates the scanner to enable the receiver transmitter and silo. Cleared by
CLR and BUS INIT.

Receiver Interrupt Enable

A read/write bit that enables the receiver interrupt.
Cleared by CLR and BUS INIT.

Receiver Done (RDONE)

A read-only bit (hardware set) that generates RCV
INT if bit 06 = 1 and bit 12 = O. The bit clears
when the RBUF is read and resets when another
word reaches the output of the silo (RBUF). If bit
06 = 0, RDONE can be used as a flag to indicate
that the silo contains a character. If bit 12 = 1,
RDONE does not cause interrupts but otherwise
acts the same.

08-10

Transmit LineA-C (TLINE)

When bit 15 = 1, these three read-only bits indicate
the line that is ready to transmit a character. Bit 15
clears when the character is loaded into the transmit buffer, but sets again if another line is ready. A
new line number could appear within a minimum
of 1.9 fJ,S. Bits 08-10 return to line 0 after a CLR or
BUS INIT. These bits are meaningful only when
bit 15 (TRDY) is true.

Not used

Silo Alarm Enable (SA E)

Function

A read/write bit that enables the silo alarm and
prevents RDONE from causing interrupts. If bit 06
= 1, the SAE allows the SA (bit 13) to cause an
interrupt after 16 entries in the silo. If bit 06 = 0,
the SA can be used as a flag. The bit is cleared by
CLR and BUS INIT.

3-5

Table 3-1

CSR Bit Functions (Cont)

Bit

Title

Function

Silo Alarm (SA)

A read-only bit set by the hardware after 16 characters enter the silo. It causes an interrupt if bit 06
= 1 and is cleared by CLR, BUS INIT, and reading the RBUF. When the silo flag occurs (SA = 1),
the silo must be emptied because the flag will not
be set again until 16 additional characters enter the
silo.

Transmitter Interrupt Enable
(TIE)

A read/write bit that allows an interrupt if bit 15
(TROY) = 1.

Transmitter Ready (TROY)

A read-only bit that is set by hardware when a line
number is found that has its transmit buffer empty
and its LINE ENAB bit set. It is cleared by CLR,
BUS INIT, and by loading the TBUF register.

3.2.2 Receiver Buffer (RBUF)
The receiver buffer (RBUF) register contains the received character bits, with line identification, error
status, and data validity flag. As one of two registers in OR2 (RBUF and LPR), RBUF is accessed
when a read operation is performed (write operation accesses the LPR). The programming constraints
for the RBUF register are as follows.
1.

Byte instructions cannot be used.

It is a read-only register.

TST or BIT instructions cannot be used because they cause the loss of a character.

The register requires master scan enable (CSR, bit 05) to be set in order to be functional.
When this bit is off, bits 00 to 14 of the RBUF become invalid regardless of the state of bit
15 (data valid) and the silo is held empty. The register format of RBUF is depicted in Figure
3-1 and bit functions are described in Table 3-2. Each reading of the RBUF register advances the silo and presents the next character to the program. Bits 00 through 14 do not go
to zero after a CLR or BUS INIT; however, they become invalid and the silo is emptied. Bit
15 (data valid) does clear to zero. (See Table 3-2.)

3-6

Table 3-2

RBUF Bit Functions

Bit

Title

Function

00-07

Received Character

These bits contain the received character. If the selected code level is less than eight bits wide, the
high-order bits are forced to zero.

08-10

Line Number

These bits present the line number on which the
character was received.

Not used,

Parity Error

This bit indicates whether the received bit had a
parity error. The parity bit is generated by hardware and does not appear in the RBUF word.

Framing Error

This bit indicates improper framing (stop bit not a
mark) of the received character and can be used for
break detection.

Overrun

This bit indicates receiver buffer overflow. The result is a received character which is replaced by another received character before storage in the silo.
A character is lost but the received character put in
the silo is valid.

Data Valid

This bit indicates that the character read from the
silo (RBUF) is valid. The RBUF is read until the
data valid bit = 0, indicating an invalid character
and empty silo. Cleared by CLR and BUS INIT.

3.2.3 Line Parameter Register (LPR)
The line parameter register (LPR) is a 16-bit register that sets the parameters (character and stop code
lengths, parity, speed, and receiver clock) for each line (Table 3-3). Bits 00-02 select the line for
parameter loading. Line parameters for each line must be reloaded after a CLR (bit 04 of CSR) or
BUS INIT operation. The programming constraints for the LPR are as follows.
1.

It is a write-only register.

BIS or BIC instructions are not allowed.

Byte operations cannot be used.

3-7

Table 3-3 LPR Bit Functions
Bit

Title

Function

00-02

Line Number

These bits select the line for parameter loading

03-04

Character Length

These bits set the character length for the selected
line. The parity bit is not part of the character
length.
04

0
0
1
1

0
1
0
1

5 bits
6 bits
7 bits
8 bits

Stop Code

This bit sets the stop code length (0 = I-unit stop, 1
= 2-unit stop or 1.5-unit stop if a 5-level code is
employed).

Parity

This bit selects the parity option (0 = no parity
check, 1 = parity enabled on TRAN and RCV).

Odd Parity

This bit selects the kind of parity (0 = even parity
select, 1 = odd parity select). Bit 06 must be set for
this bit to have effect.

08-11

Speed Select

These bits select the TRAN and RCV speed for the
line selected by bits 00-02. Refer to Table 3-4 for a
list of available baud rates.

Receiver On

This bit must be set when loading parameters to
activate the receiver clock. (Transmitter clock is always on.) A CLR or BUS INIT turns the receiver
clock off.

3.2.4 Transmit Control Register (TCR)
The transmit control register contains 16 bits for the EIA options (M7819 module) and 8 bits for the 20
rnA option (7814 module). The difference is that the data terminal ready (DTR) lines that make up the
high byte (bits 08 through 15) of the TCR are not used by the 20 rnA options because they do not have
modem control capabilities.
The high byte (M7819 only) contains a read/write DTR bit for each line. This byte is cleared by BUS
INIT only, not by CLR. When the high byte is not used (M7814 only), it reads back to the Unibus as
all zeros. Attempts to write into it will have no effect. The low byte contains a read/write line enable
bit for each line. A set bit allows transmission on the corresponding line. Paragraph 3.3.7 explains how
to properly use this bit. This byte is cleared by CLR and BUS INIT.

3-8

3.2.5 Modem Status Register (MSR)
This is a 16-bit register used only with the EIA options (M7819 module). The 20 rnA options (M7814
module) do not have modem control capabilities. When not used, this register reads all zeros to the
Unibus.
The MSR consists of two bytes: the low byte (bits 00-07) and the high byte (bits 08-15). The low byte
monitors the state of each line's ring indicator (RI) lead; the high byte monitors the state of each line's
carrier (CO) lead. The MSR is the read-only portion of DR6 and has the following programming
characteristics.
1.

It is a read-only register.

CLR and BUS INIT have no effect.

Bit format is shown in Figure 3-1.

3.2.6 Transmit Data Register (TDR)
The TDR consists of two 8-bit bytes. The low byte is the transmit buffer (TBUF) and holds the
character that is to be transmitted. The high byte is the break register with each line controlled by an
individual bit. When a break bit is set, the line associated with that bit starts sending zeros immediately
and continuously. The TDR is the write-only portion of DR6 and has the following programming
characteristics.
1.

It is a write-only register.

BIS or BIC instructions cannot be used.

For character lengths less than 8 bits, the character loaded into the TBUF must be right
justified because the hardware forces the most significant bits to zero.

The break register has no effect when running in the maintenance mode (Le., CSR bit 03 =

1).
5.

It is cleared by CLR and BUS INIT.

Bit format is shown in Figure 3-1.

3.3 PROGRAMMING FEATURES
The DZII has several programming features that allow control of baud rate, character length, stop
bits, parity, and interrupts. This section discusses the application of these controls to achieve the
desired operating parameters.
3.3.1 Baud Rate
The selection of the desired transmission and reception speed is controlled by the conditions of bits 08
through II of the LPR. Table 3-4 depicts the required bit configuration for each operating speed. The
baud rate for each line is the same for both the transmitter and receiver. The receiver clock is turned on
and off by setting and clearing bit 12 in the LPR for the selected line.

3-9

Table 3-4

Baud Rate Selection Chart

Bits
11
10

Baud Rate

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
Not used

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

3.3.2 Character Length
The selection of one of the four available character lengths is controlled by bits 03 and 04 of the LPR.
The bit conditions for bits 04 and 03, respectively, are as follows: 00 (5-level), 01 (6-level), 10 (7-level),
and 11 (8-level). For character lengths of 5, 6, and 7, the high-order bits are forced to zero.
3.3.3 Stop Bits
The length of the stop bits in a serial character string is determined by bit 05 of the LPR. If bit 05 is a
zero, the stop length is one unit; bit 05 set to a one selects a 2-unit stop unless the 5-level character
length (bits 03 and 04 at zero) is selected, in which case the stop bit length is 1.5 units.
3.3.4 Parity
The parity option is selected by bit 06 of the LPR. Parity is enabled on transmission and reception by
setting bit 06 to a one. Bit 07 of the LPR allows selection of even or odd parity, and bit 06 must be set
for bit 07 to be significant. The parity bit is generated and checked by hardware, and does not appear
in the RBUF or TBUF. The parity error (bit 12, RBUF) flag is set when the received character has a
parity error.
3.3.5 Interrupts
The receiver interrupt enable (RIE) and silo alarm enable (SAE) bits in the CSR control the circumstances upon which the DZII receiver interrupts the PDP-II processor.
If RIE and SAE are both clear, the DZII never interrupts the PDP-II processor. In this case, the
program must periodically check for the availability of data in the silo and empty the silo when data is
present. If the program operates off a clock, it should check for characters in the silo at least as often as
the time it takes for the silo to fill, allowing a safety factor to cover processor response delays and time
to empty the silo. The RDONE bit in the CSR will set when a character is available in the silo. The
program can periodically check this bit with a TSTB or BIT instruction. When RDONE is set, the
program should empty the silo.

3-10

If RIE is set and SAE is clear, the DZII will interrupt the PDP-ll processor to the DZII receiver
vector address when RDONE is set, indicating the presence of a character at the bottom of the silo.
The interrupt service routine can obtain the character by performing a MOV instruction from the
RBUF. If the program then dismisses the interrupt, the DZII will interrupt when another character is
available (which may be immediately if additional characters were placed in the silo while the interrupt
was being serviced). Alternatively, the interrupt service routine may respond to the interrupt by emptying the silo before dismissing the interrupt.
If RIE and SAE are both set, the DZll will interrupt the PDP-ll processor to the DZII receiver
vector when the silo alarm (SA) bit in the CSR is set. The SA bit will be set when 16 characters have
been placed in the silo since the last time the program has accessed the RBUF. Accessing the RBUF
will clear the SA bit and the associated counter. The program should follow the procedure described in
Paragraph 3.3.6 to empty the silo completely in response to a silo alarm interrupt. This will ensure that
any characters placed in the silo while it is being emptied are processed by the program.

NOTE
If the program processes only 16 entries in response
to each silo alarm interrupt, characters coming in
while interrupts are being processed will build up
without being counted by the silo alarm circuit and
the silo may eventually overflow without the alarm
being issued.
If the silo alarm interrupt is used, the program will not be interrupted if fewer than 16 characters are
received. In order to respond to short messages during periods of moderate activity, the PDP-II
program should periodically empty the silo. The scanning period will depend on the required responsiveness to received characters. While the program is emptying the silo, it should ensure that DZII
receiver interrupts are inhibited. This should be done by raising the PDP-II processor priority. The
silo alarm interrupt feature can significantly reduce the PDP-II processor overhead required by the
DZII receiver by eliminating the need to enter and exit an interrupt service routine each time a character is received.

The transmitter interrupt enable bit (TIE) controls transmitter interrupts to the PDP-II processor. If
enabled, the DZII will interrupt the PDP-II processor to the DZII transmitter interrupt vector when
the transmitter ready (TRDY) bit in the CSR is set, indicating that the DZII is ready to accept a
character to be transmitted.
3.3.6 Emptying the Silo
The program can empty the silo by repeatedly performing MOV instructions from the RBUF to
temporary storage. Each MOV instruction will copy the bottom character in the silo so it will not be
lost and will clear out the bottom of the silo, allowing the next character to move down for access by a
subsequent MOV instruction. The program can determine when it has emptied the silo by testing the
data valid bit in each word moved out of the RBUF. A zero value indicates that the silo has been
emptied. The test can be performed conveniently by branching on the condition code following each
MOV instruction. A TST or BIT instruction must not access the RBUF because these instructions will
cause the next entry in the silo to move down without saving the current bottom character. Furthermore, following a MOV from the RBUF, the next character in the silo will not be available for at least
1 /-LS. Therefore, on fast CPUs, the program must use sufficient instructions or NOPs to ensure that
successive MOVs from the RBUF are separated by a minimum of I /-LS. This will prevent a false
indication of an empty silo.

3-11

3.3.7 Transmitting a Character
The program controls the DZll transmitter through five registers on the Unibus: the control and
status register (CSR), the line parameter register (LPR), the line enable register, the transmitter buffer
(TBUF), and the break register (BRK).
Following DZII initialization, the program must use the LPR to specify the speed and character
format for each line to be used and must set the master scan enable (MSE) bit in the CSR. The
program should set the transmitter interrupt enable (TIE) bit in the CSR if it wants the DZII transmitter to operate on a program interrupt basis.
The line enable register is used to enable and disable transmission on each line. One bit in this 8-bit
register is associated with each line. The program can set and clear bits by using MOV, MOVB, BIS,
BISB, BIC, and BleB instructions. (If word instructions are used, the line enable register and the DTR
registers on M7819 modules are simultaneously accessed.)
The DZII transmitter is controlled by a scanner which is constantly looking for an enabled line (line
enable bit set) which has an empty UART transmitter buffer. When the scanner finds such a line, it
loads the number of the line into the 3-bit transmit line number (TLINE) field of the CSR and sets the
TRDY bit, interrupting the PDP-II processor if the TIE bit is set. The program can clear the TRDY
bit by moving a character for the indicated line into the TBUF or by clearing the line enable bit.
Clearing the TRDY bit frees the scanner to resume its search for lines needing service.
To initiate transmission on an idle line, the program should set the TCR bit for that line and wait for
the scanner to request service on the line, as indicated by the scanner loading the number of the line
into TLINE and setting TRDY. The program should then load the character to be transmitted into the
TBUF by using a MOVB instruction. If interrupts are to be used, a convenient way of starting up a line
is to set the TCR bit in the main program and let the normal transmitter interrupt routine load the
character into the TBUF.
NOTE
The scanner may find a different line needing service
before it finds the line being started up. This will occur if other lines request service before the scanner
can find the line being started. The program must
always check the TLINE field of the CSR when responding to TRD Y to ensure it loads characters for
the correct line. Assuming the program services lines
as requested by the scanner, the scanner will eventually find the line being started. If several lines require
service, the scanner will request service in priority
order as determined by line number. Line 7 has the
highest priority and line 0 the I()west.
To continue transmission on a line, the program should load the next character to be transmitted into
the TBUF each time the scanner requests service for the line as indicated by TLINE and TRDY.
To terminate transmission on a line, the program loads the last character normally and waits for the
scanner to request an additional character for the line. The program clears the line enable bit at this
time instead of loading the TBUF.

3-12

The normal rest condition of the transmitted data lead for any line is the 1 state. The break register
(BRK) is used to apply a continuous zero signal to the line. One bit in this 8-bit register is associated
with each line. The line will remain in this condition as long as the bit remains set. The program should
use a MOVB instruction to access the BRK register. If the program continues to load characters for a
line after setting the break bit, transmitter operation will appear normal to the program despite the fact
that no characters can be transmitted while the line is in the continuous zero sending state. The program may use this facility for sending precisely timed zero signals by setting the break bit and using
transmit ready interrupts as a timer.
It should be remembered that each line in the DZll is double buffered. The program must not set the
BRK bit too soon or the two data characters preceding the break may not be transmitted. The program must also ensure that the line returns to the I state at the end of the zero sending period before
transmitting any additional data characters. The following procedure will accomplish this. When the
scanner requests service the first time after the program has loaded the last data character, the program
should load an all-zero character. When the scanner requests service the second time, the program
should set the BRK bit for the line. At the end of the zero sending period, the program should load an
all-zero character to be transmitted. When the scanner requests service, indicating this character has
begun transmission, the program should clear the BRK bit and load the next data character.

3.3.8 Data Set Control
DZ II models with EIA interfaces include data set control as a standard feature. The program may
sense the state of the carrier and ring indicator signals from each data set and may control the state of
the data terminal ready signal to each data set. The program uses three 8-bit registers to access the
DZ II data set control logic. One bit in each register is associated with each of the eight lines. There are
no hardware interlocks between the data set control logic and the receiver and transmitter logic. Any
required coordination should be done under program control.
The data terminal ready (DTR) register is a read/write register. Setting or clearing a bit in this register
will turn the appropriate DTR signal on or off. The program may access this register with word or byte
instructions. (If word instructions are used, the DTR and line enable registers will be simultaneously
accessed.) The DTR register is cleared by the INIT signal on the Unibus but is not cleared if the
program clears the DZII by setting the CLR bit of the CSR.
The carrier register (CAR) and ring register (RING) are read-only registers. The program can determine the current state of the carrier signal for a line by examining the appropriate bit of the CAR
register. It can determine the current state of the ring signal by examining the appropriate bit of the
ring register. The program can examine these registers separately by using MOVB or BITB instructions or can examine them as a single 16-bit register by using MOV or BIT instructions. The DZll
data set control logic does not interrupt the PDP-ll processor when a carrier or ring signal changes
state. The program should periodically sample these registers to determine the current status. Sampling at a high rate is not necessary.

3.4 PROGRAMMING EXAMPLES
The following six examples are sample programs for the DZII option. These examples are presented
only to indicate how the DZII can be used.

3-13

Example 1 - Initializing the D Z 11
The DZII is initialized by a power-up sequence, a reset instruction, or a device clear instruction.
Device Clearing the DZll
001000
001002
001004
001006
001010
001012
001014

012737
000020
160100
032737
000020
160100
001374

001016

000000

START:

MOV #20, DZCSR

1$:

BIT #20, DZCSR

;Set bit 4 in the
;DZ 11 control and
;status register.
;Test bit4.
;If bit 4 is still
;set, the branch
;condition is true
;and the device clear
;function is still in
;progress.
;The device clear
;function is complete
;and the DZII has been
;cleared.

BNE 1$

HALT

DZCSR = Control and Status Register Address = 160100.
Example 2 - Transmit Binary Count Pattern on One Line
001000
001002

012737
000020

001004
001006
001010
001012
001014

160100
032737
000020
160100
001374

001016
001020
001022

012737
001070
160102

MOV #n, DZLPR

001024

012737

MOV #1, DZTCR

START:

MOV #20, DZCSR.

;Set bit 4 in the DZII
;control and status
;register.

1$:

BIT #20, DZCSR

;Test bit 4.

BNE 1$

;If bit 4 is still set,
;the branch condition
;is true and the device
;clear function is still
;in progress.
;Load the parameters
;for line 0: 8-bit
;character; 2 stop bits;
;110 baud
;Enable line 0
;transmitter.

3-14

001026
001030
001032
001034
001036
001040

000001
160104
012737
000040
160100
005000

001042
001044
001046

005737
160100
100375

0\;1050
001052
001054
001056

110037
160106
105200
100371

INCB RO
BPL2$

001060

000000

HALT

MOV #m, DZCSR
CLRRO
2$:

TSTDZCSR
BPL2$
MOVB RO, DZTDR

;Set scanner enable bit
;5 in the control and
;status register.
;Set binary count
;pattern to zero.
;Test the transmitter
;ready flag (bit 15).
;If branch condition
;is false, continue;
;otherwise test again.
;Load character to be
;transmitted.
;Increment binary count.
;If branch condition is
;false, the binary count
;pattern is complete.

RO = Register 0 = Binary Count Pattern
DZCSR = DZII Control and Status Register Address = 160100
DZLPR = DZII Line Parameter Register Address = 160102
DZTCR = DZll Transmit Control Register Address = 160104
DZTDR = DZII Transmit Data Register Address = 160106
Example 3 - Transmit a Binary Count in Maintenance Loopback Mode, with the Receiver "On" in the
Interrupt Mode
Output Received Data to Console
001200

005000

CLRRO

001202
001204

012701
001400

MOV 1400, RI

001206
001210
001212
001214
001216

012706
001100
012737
001304
000300

MOV#SP,R6

001220
001222

005037
000302

CLR(RVEC+2)

001224
001226

012737
000020

MOV #20, DZCSR

MOV #INT, RVEC

3-15

;Set binary count
;to zero.
;Set R I to first
;address of data
;buffer.
;Initialize stack
;pointer.
;Set DZII vector
;address to start of
;receiver interrupt
;routine.
;Set up processor
;status word for DZII
;receiver interrupt.
;Set bit 4 in the
;DZII control and
;status register.

001230
001232
001234
001236
001240

160100
032737
000020
160100
001374

001242
001244
001246

012737
011070
160102

MOV #PAR, DZLPR

001250

012737

MOV #1, DZTCR

001252
001254
001256
001260
001262

000001
160104
012737
000150
160100

MOV #150, DZCSR

001264
001266
001270

005737
160100
100375

001272
001274
001276
001300

110037
160106
105200
001371

INCB RO
BNE2$

001302

000777

BR.

1$:

2$:

BIT #20 DZCSR ,

;Test bit4.

BNE 1$

;If bit 4 is still
;set, the branch
;condition is true
;and the device clear
;function is still in
;progress.
;Load the parameters
;for line 0: 8-bit
;character; 2 stop bits;
;110 baud; no
;parity; receiver on.
;Enable line 0
;transmitter.

TSTDZCSR
BPL2$
MOVB RO, DZTBUF

3-16

;Turn scanner on,
;enable receiver
;interrupts, and loop
;lines back on themselves.
;Test the transmitter
;ready flag.
;If branch condition is
;false, continue;
;otherwise test again.
;Load character to be
;transmitted.
;Increment binary count.
;If branch condition is
;false, the binary count
;pattern is complete.
;Wait for last character
;transmitted to be
;received.

Receiver Interrupt Service Routine
001304
001306

013711
160102

MOV DZRBUF, (Rl)

001310
001312
001314

022721
100377
001401

CMP #100377,
(Rl)+
BEQ.+2

001316
0(,l320
001322

000002
012701
001400

RTI
MOV #1400, Rl

001324
001326
001330

105737
177564
100375

001332
001334
001336
001340
001342

111137
177566
022721
100377
001370

CMP #100377,
(Rl)+
BNE3$

001344

000000

HALT

3$:

TSTBTPS
BPL3$
MOVB (Rl), TPB

R VEC = DZ 11 Receiver Interrupt Vector Address
DZCSR = DZ 11 Control and Status Word Address
DZLPR = DZll Line Parameter Register (Write-Only) Address
DZTCR = DZ 11 Transmit Control Register Address
DZTBUF = DZ 11 Transmit Buffer Address
DZRBUF = DZl1 Receiver Buffer Address (Read-Only Register)
TPS = Teletype® Punch Status Register Address
TPB = Teletype Punch Data Register Address

OOTeletype is a registered trademark of Teletype Corporation.

3-17

;Store received
;character in memory
;table.
;Check for last
;character.
;Branch condition is
;true when last
;transmitted character
;is received.
;Exit routine.
;Initialize pointer
;to start of received
;data buffer in memory.
;Test to see if console
;is ready.
;Wait, and test again.
;If condition is met,
;transfer character
;to console.
;Check for last
;character.
;N ot finished if
;condition is true.
;finished.

Example 4 - Transmit and receive in Maintenance Mode on a Single Line
The switch register bits (SWROO-SWR07) hold the desired data pattern (character).
001000
001002

012737
000002

001004
001006
001010

160104
012737
017471

001012

160102

001014
001016
001020
001022
001024
001026

012737
000050
160100
005737
160100
100375

001030
001032
001034
001036

113737
177570
160106
000240

001040

012701
177670

START:

MOY #LINE, DZTCR

MOY #PAR, DZLPR

MOY #N, DZCSR
Test 1:

TSTDZCSR
BPL Test 2

MOYBSWR,
DZTBUFF
NOP

MOY#DEL,Rl

3-18

;Select the line for
;transmitting on.
;Choose one ofeight.
;Line #1 selected.
;Select desired line
;parameters for
;transmitting line
;and turn on receiver
;for that line.
;8-leve1 code, 2 stop
;bits, and no parity
;selected.
; 19 .2K baud selected
;Note: 19.2K baud is
;not used by the
;customer but can be
;used for diagnostic
;purposes to speed up
;the transmit-receive
;loop to make it easier
;to scope.
;Start scanner and set
;maintenance bit 3.
;Test for bit 15
;(transmitter ready).
;If the branch condition
;is false, the transmitter
;is ready; if true, go
;back and test again.
;Load the transmit
;character from the
;switch register.
;No operation. This
;location can be changed
;to a branch instruction
;if only test 1 is
;desired (replace 000240
;with 000771).
;Delay equals a
;constant that will
;allow enough time for
;the receiver done
;flag to set before
;recycling the test.
;The value will change
;with baud rate and
;processor. The
;constant given is
;good for 19.2K baud
;on a PDP-ll/05.

001042
001044
001046

105737
160100
100402

001050
001052

005201
001373

001054
001056

013700
160102

001060

000760

Test 2:

TSTBDZCSR
BMIl$

INCRI
BNETEST2
1$:

MOV DZRBUF, RO
BR TEST 1

;Test bit 2 (receiver
;done flag).
;When the branch
;condition is true,
;the receiver done
;flag is set.
;Increment delay.
;If the branch
;condition is true, the
;delay is not finished.
;Read the DZll
;receiver buffer to
;register O.
;Loop back and
;test again.

Example 5 - Transmit and Receive on a Single Line Using Silo Alarm in Maintenance Mode
001200
001202
001204
001206
001210
001212
001214

012706
001100
012737
001274
000304
005037
000306

MOV #1100, R6

001216
001220

012700
001304

MOV #DBUF, RO

001222

012737

MOV #1, DZTCR

001224
001226
001230
001232
001234
001236
001240
001242

000001
160104
012737
017470
160102
012737
050050
160100

001244
001246
001250
001252

032737
020000
160100
001774

1$:

001254
001256
001260
001262

01372Q
160102
000240
000240

2$:

MOV #3$, TVEC
CLR TVEC+2

MOV #17470,
DZLPR
MOV #50050,
DZCSR

BIT #20000,
DZCSR
BEQ 1$
MOVDZRBUF,
(RO)+
NOP
NOP

3-19

;Initialize stack
;pointer.
;Initialize transmitter
;vector address.
;Initialize transmitter
;vector processor status
;word.
;Set first address of
;input data table
;into RO.
;Enable line 0
;transmitter.
;Set up line parameters
;and turn on the receiver
;clock for line O.
;Enable transmitter
;interrupt and silo
;alarm. Turn on
;scanner and maintenance
;mode.
;Test for silo alarm
;Loop until silo alarm
;flag sets.
;Read DZll silo
;receiver buffer output.
;Delay to allow next
;word in silo to filter
;down to the silo
;output.

001264

100773

BMI2$

001266
001270

012700
001304

MOV #DBUF, RO

001272

000764

BR 1$

;Data valid set says
;that word is good,
;go back for more.
;Silo has been emptied.
;Reinitialize data
;table address pointer.
;Do it again.

Transmitter Interrupt Service Routine
001274
001276
001300
001302

112737
000252
160106
000002

MOVB DAT, DZTBUF

;Transmit
;character 252

RTI
Data Table
1304
1306

100252
100252

;Word 1

1340
1342

100252
000252

;Word 16
;Data valid
;not set
;character is
;invalid

NOTE
It is possible to get more than 16 words because they
are being put into the silo simultaneously with the
reading of the silo.

3-20

Example 6 - Echo Test on a Single Line (Transmit Received Data)
001000

012737

001002
001004

011073
160102

001006
001010
001012
001014
001016
001020
001022
001024
001026

012737
000010
160104
012737
000040
160100
105737
160100
100375

001030
001032
001034

005737
160100
100375

001036
001040
001042
001044

013700
160102
110037
160106

001046

000765

START

MOV #PAR, DZLPR

MOV #LINE, DZTCR

1$:

MOV #n, DZCSR

;Turn scanner on
;(set CSR-5)

TSTBDZCSR

;Test (bit 7) for
;RDONE
;If bit 7 is not set,
;go back and test again.
;Test (bit 15) for
;TRDY
;Ifbit 15 is not set
;go back and test again.
;Read received data
;word into RO
;Load character
;into DZ 11 TBUF
;register for
;transmitting.
;Repeat.

BPL 1$
2$:

;Load line parameters
;for line being used.
;Line 3, 8-bit
;character, 2 stop
;bits, no parity,
; 110 baud, and receiver
;clock on.
;Turn line 3
;transmitter on.

TSTDZCSR
BPL2$
MOVRBUF,RO
MOVB RO, DZTDR

BR 1$

3-21

APPENDIX A
DZll (M7814) TO AN ACTIVE DEVICE INSTALLATION

When a 20 rnA DZ 11 is used with another active device, two H319 current loop receivers must be used.
Figure A-I provides an example of the connections involved when the DZII is used with another
active device, in this case another DZII. A schematic of the H319 is shown in Figure A-2.

"A"

"B"

DZll
H317F DISTRIBUTION PANEL

DZ11
H317F DISTRIBUTION PANEL

DZll "A" REC +

1
DZ11 "A" REC DZ11 "A" XMIT -

REC + DZ11 "B"

~
2

(JJ) 2 REC - DZ11 "B"

XMIT - DZ11 "B"

3
DZ11 "A" XMIT +

H319 INPUT

€}

H319 OUTPUT

9 4 XMIT + DZ11 "B"

10 FT. CABLE
SUPPLIED WITH
H319

11-5639

NOTE:

THE CABLE ATTACHED TO THE H319 SHOULD HAVE THE
CONNECTOR REMOVED AND RING LUGS ATTACHED TO THE
RED AND GREEN LEADS AS SHOWN.
THE BLACK AND WHITE LEADS IN THE H319 CABLE AND BC04R CABLE
ARE NOT USED.

Figure A-I

DZII (M7814) to Active Device Connection

A-I

J1
1

•

BLK

•
5

TL + WHT

•

33.11

RL + GRN

8
•

5
04
2.4V

Q2
Q2132

03
0664
0664
01
0664

R3
3K

RL _ REO
11-5640

Figure A-2

H319 Current Loop Receiver Schematic Diagram

A-2

Reader's Comments
DZll USER'S GUIDE
EK-DZII0-UG-002

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