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EK-DX11B-MM

January 1976

180 pages

Original

18MB

Document:	EK-DX11AB-MM-002 DX11-B System 360 370 Channel to PDP-11 Unibus Interface Maintenance Manual
Order Number:	EK-DX11B-MM
Revision:	000
Pages:	180
Original Filename:	http://bitsavers.org/pdf/dec/unibus/EK-DX11AB-MM-002_DX11-B_System_360_370_Channel_to_PDP-11_Unibus_Interface_Maintenance_Manual_Jan76.pdf

OCR Text

EK-DXIIB-MM-002

DX11-8 system 360/370
channel to PDP-11 unibus
interface
maintenance manual

digital equipment corporation • maynard, massachusetts

1st Edition, August 1972
2nd Printing (Rev) March 1973
3rd Printing July 1973
4th Printing May 1974
5th Printing (Rev) January 1976

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTER LAB

CONTENTS
Page
CHAPTER 1

GENERAL DESCRIPTION

1.1
1.2

1.4
1.4.1
1.4.2
1.4:3
1.4.4
1.5

Purpose of Manual
System Description
Mechanical Description
Specifications
Physical
Environmental
Electrical
Performance
Engineering Drawaing Drawings

CHAPTER 2

INSTALLATION AND ACCEPTANCE TEST

2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.3
2.3.1
2.3.2
2.4
2.4.1
2.4.2
2.4.3
2.5
2.6
2.6.1
2.7
2.7.1
2.7.2
2.7.3

Summary of Installation Functions
Installation and Acceptance Test Requirements
Equipment Required
Diagnostics Required
Space Requirements
Power Requirements
Information Requirements
Test Schedule
Unpacking and Inspection
Unpacking
Inspection
Installation
PDP-II and DX11-B Cable Installation (within PDP-II System)
IBM Device Address Jumper Installation
Interrupt Vector Address Jumper Installation
Turning Power On for the First Time
PDP-II System Test Without DX11-B

2-1
2-2
2-2
2-2
2-3
2-3
2-5
2-6
2-6
2-6
2-7
2-7
2-7
2-8
2-12
2-12
2-13

Control and Indicator Panel Lamp Check
DX11-B Test Without IBM 360/370 (OffLine)
M306 NPR Timeout Mono Calibration Procedure
BLLM Calibration
Run the DX11-B Maintenance Clock 2 Test
(MAINDEC-11-DZDXF-[REV] -PB)
Run the DXII-B Off-Line Exerciser (MAINDEC-11-DZDXG-[REV] -PB)
DX11-B CABLE TEST
On Line B Delay Adjustment
DXTO Calibration Procedure
IBM 360/370 Cable Test Using DXII-B to Test Cables Without
IBM 360/370 System

2-13
2-13
2-14
2-15
2-15

1.3

2.7.4
2.8
2.8.1
2.8.2
2.8.3

iii

1-1
1-2
1-5
1-5
1-6
1-6
1-6
1-6
1-7

2-15
2-15
2-18
2-19
2-19

CONTENTS (Cont)
Page
2.9
2.10
2.11
2.12
2.13
2.14
2.14.1
2.14.2
2.14.3
2.14.4
2.14.5
2.14.6
2.14.7
2.14.8
2.14.9
2.15
2.15.1
2.15.2
2.15.3
2.16
2.17
2.18

Filling Out Test Preparation Card
I/O Cable Requirements
Connecting DX11-B Cables To IBM Channel
EPO Cable Connection
EPO Panel Check
DX11-B System Test Using IBM 360/370
Introduction
Test Preparation
FRIEND Diagnostic Operating Procedure
Filling Out Test Preparation Card
Card Deck Preparation Procedure
DME/2848 Diagnostic Operation Procedures
Test Preparation
DME/2848 Diagnostic Operation Procedure
FRIEND or DME/2848 Diagnostic Operating Procedure for 3270 Console
Operating Suggestions
On-Line Operation Requirements
Errors with DME/2848 Diagnostic
Format Consideration and Logic Levels
Errors That Occur When FRIEND is Run
Maintenance Procedures
Hints on Interface Signal Monitoring While Troubleshooting

2-20
2-21
2-21
2-24
2-25
2-26
2-26
2-26
2-27
2-31
2-31
2-34
2-34
2-34
2-38
2-40
2-40
2-41
2-41
2-41
2-42
2-42

CHAPTER 3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4

OPERAnON
Scope
Controls and Indicators

3-1
3-1

861 Controls and Indicators
Pilot Lamps
Circuit Breaker
LOCAL/OFF/REMOTE Switch
Remote Switching Control Bus Connectors

3-9
3-9
3-9
3-9
3-9

CHAPTER 4

PROGRAMMING

4.1
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7

Scope
IBM 360/370 and PDP-II Format Comparison
IBM 360/370/DX11-B Communication
DX11-B/PDP-ll Communication
DX11-B Formats
Device Status Register (DXDS)
Command and Address Register (DXCA)
Control Unit Status Register (DXCS)
Offset and Status Register (DXOS)
Bus Address Register (DXBA)
Byte Count Register (DXBC)
Maintenance Out Register (DXMO)

4-1
4-1
4-2
4-2
4-3
4-4
4-6
4-7
4-9
4-10
4-11
4-11

CONTENTS (Cont)
Page
4.5.8
4.5.9
4.5.10
4.5.11
4.5.12
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6

Maintenance In Register (DXMI)
Control Bits Register (DXCB)
Non-Processor Request Data Register (DXND)
Extra Signals Registers (DXESI and DXES2)
Maintenance Out Buffered Register (DXMOB)
Programming Considerations
Hardware/Software Interlock
Boundary Considerations
Interrupt Request
Data Transfer
Status Presentation
On-Line/Off-Line Control

CHAPTERS

THEORY OF OPERATION

5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.1.3
5.4.1.4
5.4.1.5
5.4.2
5.4.2.1
5.4.2.2
5.4.2.3
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
5.5.8

Scope
Functional Description
Block Diagram Discussion
IBM Interface Operation
IBM Control Operation
Unibus Interface Operation
PDP-II Control Operation
Central Control Operation
Channel Simulator Operation
Sequences of Operation
IBM Sequences
Selector Channel-Initiated Sequences (CHI)
Control Unit Initiated Sequences (CUI)
Reset Sequences
Multiplexer Channel Differences
IBM Sequence Summary
DXll-B Sequences
Register Organization
Flow Diagram Conventions
Design Flows
Circuit Descriptions
DXll Device Status Register (DXDS)
Control Unit Status Register (DXCS)
DXll Bus Address Register (DXBA)
DXll Byte Counter (DXBC)
Control Unit Status Register (CUSR) Part of DXOS
NPR Data Register (DXND)
DXll Control Bits Register (DXCB)
Control Lines Out Register (CONO) Part of DXMO

4-13
4-14
4-16
4-17
4-18
4-18
4-18
4-19
4-19
4-20
4-20
4-20

5-1
5-1
5-2
5-3
5-11
5-12
5-12
5-13
5-14
5-14
5-15
5-15
5-19
5-20
5-22
5-24
5-27
5-27
5-29
5-30
5-40
540
5-41
541
542
542
5-43
543
544

CONTENTS (Cont)
Page
5.5.9
5.5.10
5.5.11
5.5.l2
5.5.13
5.5.14
5.5.15
5.5.16
5.5.17
5.5.18
5.5.19
5.5.20
5.5 .21
5.5.22
5.5.23
5.5.24
5.5.25

Control Lines In Register (CONI) Part of DXMI
IBM Bus-In Lines (BUS!) Part of DXMI
Tumble Table Index (TTNDX)
Control Unit Address Register (CUAR) Part of DXCA
Control Unit Command Register (CUCR) Part of DXCA
Unibus Interface
NPR and TNT Control
Data Bus Multiplexer
Clock, Phase and Time State Generator
Maintenance Out Buffered Register (DXMOB)
General Controls
Signals and Gates
Parity and Address Compare
IBM Interface
Select Bypass and Power Fail
"Bit Slice" and "Select" Loop Trace in Off-Line Cable Mode
EPO Panel Operation

CHAPTER 6

MAINTENANCE

6.1
6.2
6.2.l
6.2.2
6.3
6.3.1
6.3.2
6.3.3

Introduction
Preventive Maintenance
Mechanical Checks
Test Equipment Required
Corrective Maintenance
General Corrective Procedures
Diagnostic Testing
Vibration Tests

CHAPTER 7

ENGINEERING DRAWINGS

7.1

General

5-44
5-45
5-45
5-45
5-45
5-46
5-46
5-47
5-47
5-47
5-48
5-48
5-49
5-50
5-50
5-51
5-51

6-1
6-1
6-1
6-1
6-2
6-2
6-2
6-3

7-1

APPENDIX A REFERENCE MATERIAL
A.l
A.2
A.3

Glossary
HEX/OCTAL/EBCDIC Conversion Chart
Hexadecimal/Octal Conversion

A-I
A-12
A-13

APPENDIX B ADDRESS ASSIGNMENTS

B-1

APPENDIX C INTRODUCTION TO DXI1-B FLOW DIAGRAMS

C-l

ILLUSTRATIONS
Title

Page
1-3
1-4
1-5

2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25

DXll-B, System 360/370 Channel to PDP-II Unibus Interface
Typical DXll-B System Block Diagram
DXll-B Functional Block Diagram
H960 and H957 Cabinet Dimensions
DXll-B Cable Connections Configured for User Operation
(Viewed from Rear)
DXll - IBM Cable Assembly Configured to Execute Cable Loop
Around Test DZDXH
M908 Module Before Wiring
I/O Address Format
Example of Wiring for Four Devices
Example of Wiring for 16 Devices 10 through IF (1x)
Example of Wiring for 32 Devices 50 through 6F (5x and 6x)
Example of Wiring for One Device (10)
Example of Wiring for Two Devices (10 to 11)
Example of Wiring for 8 Devices (20-27)
NPR Timeout Mono Calibration Waveform
BLLM Calibration Signal
Test Bus Cable Connections Without IBM 360/370 Cables Supplied
By Customer
Test Bus Cable Connections Using IBM 360/370 Cables
S.ignal Flow for Test Cable Connections
Normal Cable Connections to Channel Bus if on End of Bus
Normal Cable Connections to Channel Bus if Not on End of Bus
Sample FRIEND 360/370 Console Printout
IBM 360/370 Console
Sample Prep Card
Test Preparation Card
Typical Line Printer Copy from the DME/2848 Diagnostic
Input/Output Signals
Formats for Transmission of Information on the Buses

3-1
3-2

DXll-B Controls and Indicators
Type 861-A,-B,-C Power Controller Panels

3-2

4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11

IBM 360/370/PDP-ll Data Format Comparison
360/PDP-ll Transfer Conventions
Device Status Register Bit Assignments
Command and Address Register Bit Assignments
Control Unit Status Register Bit Assignments
Offset and Status Register Bit Assignments
Bus Address Register Bit Assignments
Byte Count Register Bit Assignments
Maintenance Out Register Bit Assignments
Maintenance In Register Bit Assignments
Control Bits Register Bit Assignments

4-1
4-3
4-4
4-7
4-7
4-10
4-11
4-11
4-12
4-13
4-14

Figure No.
1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14

vii

2-4
2-8
2-9
2-10
2-10
2-11
2-11
2-11
2-11
2-12
2-12
2-14
2-15
2-16
2-17
2-18
2-22
2-23
2-29
2-30
2-32
2-33
2-35
2-43
2-43
~-1O

Figure No.

ILLUSTRATIONS (Cont)
Title

Page

4-12

Non-Processor Request Data Register Bit Assignments

4-16

4-13

Extra Signals Register DXESI Bit Assignments

4-17

4-14

Extra Signals Register DXES2 Bit Assignments

4-18

4-15
4-16
5-1

Maintenance Out Buffered Register Bit Assignments
Tumble Table

4-18
4-21

DXll-B System, Functional Block Diagram

5-1

5-2

DXll-B System, Block Diagram

5-2

5-3

DXll-B, Block Diagram

5-3

5-4

Channel/DXll-B Interface

5-9

5-5

Channel Selection Chain

5-11

5-6

Initial Selection Sequence (ISS) Selector Channel Initiated

5-16

5-7a

Data (Read) Transfer and Ending Sequences with Selector Channel

5-17

5-7b

Data (Write) Transfer and Ending Sequences with Selector Channel

5-17

5-8

I/O Stop Sequence on Selector Channel

5-18

5-9

Stack Status Sequence

5-19

5-10

CUI Sequence to Selector Channel

5-20

5-11

Interface Disconnect Sequence to CU Idle of/the Channel

5-20
5-21

5-12

Interface Disconnect Sequence to CU Idle on the Channel

5-13

Interface Disconnect Sequence to CU Active on the Channel

5-21

5-14

ISS, Multiplexer Channel Initiated

5-22

5-15

CUIS and Data Transfer, Multiplexer Channel

5-23

5-16

CUIS and Status Transfer, Multiplexer Channel

5-23

5-17

Fast CU Busy Sequence, Multiplexer Channel

5-24

5-18

OFF to ON and ON to OFF Line Transition Timing

5-52

5-19
5-20

One Bit Slice Loop Trace
Select-Out/Select-In Loop Trace

5-52
5-53

TABLES
Table No.

Title

Page

2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8

Summary of Installation Functions
Equipment Required for Installation and Acceptance Test
DXIl-B Diagnostics LIBKIT NO. ZJ13l-RB
DXIl-B Option Designations
EXAMPLE I
EXAMPLE 2
Diagnostic Card Deck
System Configuration Definitions

3-1

DXll-B Controls and Indicators

4-1

DXll-B Registers (Addressable as PDP-II Memory)

4-2

DXDS Bit Assignments

4-3
4-4

4-3

DXCA Bit Assignments

4-7

2-1
2-2
2-3
2-5
2-29
2-31
2-34
2-36
3-1

4-4

DXCS Bit Assignments

4-8

4-5

DXOS Bit Assignments

4-10

viii

TABLES (Cont)
Table No.
4-6
4-7
4-8
4-9
5-1
5-2
6-1
7-1
A-I
A-2

Title

Page

DXMO CONO Bit Assignments
DXMI CONO Bit Assignments
DXCB Bit Assignments
DXESI and DXES2 Bit Assignments
I/O Command Byte Formats
Channel/DXII-B Interface Lines
Test Equipment Required
DXII-B Engineering Drawings
DXII-B Signal Glossary
Hex/Octal/EBCDIC Conversion Chart

4-12
4-14
4-15
4-17
5-8
5-10
6-2
7-1
A-I
A-12

CHAPTER 1
GENERAL DESCRIPTION

1.1 PURPOSE OF MANUAL
This manual provides the information necessary to maintain the DXII-B, System 360/370 Channel fo PDP-II'
Unibus Interface. Chapter 1 contains introductory information with brief specifications. Chapter 2 of this
manual is concerned with the basic information needed to unpack, install and test the equipment. Specific
reference should be made to the individual Customer Site Plan for the particular installation requirements.
Included are general programming procedures required in testing, following installation. Chapters 3 and 4
provide information as to formats and programming considerations. For more detailed programming information
refer to the PDP-II programming documentation.
This manual is primarily concerned with the operation of the DXII-B hardware and the ways in which it interacts with its specially designed software. Chapter 5, Theory of Operation, provides information about the 360/370
Channel operation as it bears on the interface with the DXII-B. Included are detailed discussions of the functional parts and the various sequences of operation.
This is not a basic manual, some prior knowledge of the IBM 360/370 is required, together with familiarity with
the PDP-II System, particularly with regards to the Unibus Interface. The following is a list related PDP-II and
IBM documents applicable to the DXII-B System.
Title

Number

Coverage
How to program the PDP-II computer
and interface to the PDP-II Unibus

PDP-II Peripherals Handbook
Programming-Interfacing
IBM System/360 and System/370
I/O Interface Channel to Control
Unit OEMI.

GA22-6974

How to interface to an IBM 360/370
Channel

IBM System/360 Principles of
Operation

GA22-6821

How the 360 works
How the PDP-II and the, Peripherals
Work

Applicable PDP-II Maintenance
Manuals and Peripheral Option
Maintenance Manuals

1-1

1.2 SYSTEM DESCRIPTION
The DXll-B, System 360/370 Channel to PDP-II Unibus Interface, shown in Figure I-I, is a data and status
transfer controller that provides communication between an I/O channel of a System 360 or System 370 IBM
Computer and software within a Digital Equipment Corporation PDP-II Computer. The system is table-driven
for convenience and efficiency. When installed, the DXII-B responds automatically to any 360/370 I/O command or status interrogation that is directed to its assigned addresses. It will conduct data transfers (upon PDP-II
program initiation) between the 360/370 Channel and the Unibus, automatically transferring data between the
DXll-B buffers and the Unibus locations; participating in data transfers on the 360/370 Channel, and stopping
the transfer when the prescribed number of bytes have been transferred. Additionally, the DXll-B communicates
with the PDP-II processor which, in tum, controls the status indications provided to the 360/370 Channel, sets
up the DXII-B to execute the commands transmitted by the channel, and provides communication between
other devices on the Unibus and the address space used by the DXll-B.
As shown in Figure 1-2, the typical system that is attached to an IBM processor consists of a channel (CH), the
control units (CD) attached to the channel, and the devices attached to each controller. Several channels can
operate with one processor. The DXll-B operates as a control unit, routing data from devices that store data in
different formats to a channel that provides selection and timing control.
The DXIl-B is used to perform some of the functions of a controller. However, much of the functional operation
of the controller, such as determining the status of the devices, initiating transfers, and detecting errors, is performed by a PDP-II programmed processor that is interposed between the DXIl-B and the devices with which it
operates. In addition, the DXII-B, under control of the PDP-II processor, can appear to the channel to operate
with several different types of devices.
As shown in Figure 1-3, from a functional standpoint, the DXII-B can be considered to be two interfaces: a
standard hardware interface to the IBM 360/370 and a standardized software interface (within the PDP-II) to
device emulator programs and application programs. The basic package can be programmed to emulate most
standard IBM control units with up to 128 devices attached. The emulation only requires the addition of software to the basic package. As a result, the PDP-II based equipment can be substituted directly for a 360/370
device or devices, with no reprogramming of the 360/370 required. Although hardware and software are
described separately in this manual, because of the interactive characteristics between hardware and software
in the DXll-B, they are, in reality, inseparable and must be considered as one device in order to gain a
complete understanding of the operation of this equipment.
The outstanding features of the DX Il-B are:
• Operates on either multiplexer, block multiplexer, or selector channels.
• Emulates up to 128 devices with as many as eight separate sets of contiguous addresses.
• Handles concurrent I/O on all emulating devices.
• Operates with standard 360/370 operating software.
• Is plug-compatible with the standard IBM channel.
• Contains powerful built-in maintenance capability.
• Contains an interface simulator, allowing complete off-line diagnosis.
• Provides a fully buffered I/O (4-byte buffer).

1-2

Figure 1-1 DX11-B, System 360/370 Channel
to PDP-II Unibus Interface

1-3

SELECT OUT

CHANNEL
(CH)

....-----.jh : CONTROL
I

UNIT
(CU)

360/370

CENTRAL
PROCESSOR
(CP)

: CONTROL
I
UN IT
i----r------,
:
(CU)
I

SELECT IN

DEVICE

360/370
STORAGE

SELECT OUT
CHANNEL
(CH)

SELECT IN
PDP-11
CP

11-1228

Figure 1-2 Typical DX11-B System Block Diagram

1-4

• Handles sequence checking.
lit

Operates on multiple sub channels.

• Operates on shared or unshared subchannels.
@

Operates on selector sub channels.

• Has table-driven status response and burst mode selection.
• Makes available all control unit options.
@

Provides hardware disconnect if program or system fails due to power failure, if PDP-II halts, or if
OPERATIONAL IN is up for 5 seconds without program interaction.

1.3 MECHANICAL DESCRIPTION
The DXll-B is housed in a standard 19-in. rack (CAB-II H960 or H957), containing four H911 Mounting
Panels for M-series logic, and IBM 360 connectors for cable connection from the channel and to the next
channel unit. Power is provided by an H740 Logic Power Supply, a 716 Power Supply for the indicator panel,
and a unit source power panel (EPO) with its power sequence control to the IBM power interface logic. Indicators are provided for logic operation on one panel located on the top front of the unit. Controls are located
on the EPO panel available behind a removable front cover, and on the back of the H740 Power Supply, which
contains its own power control circuitry. Caravelle fan cooling is provided as part of the basic cabinet. Connections are made between this cabinet and other cabinets containing the PDP-II Computer and associated equipment. Equipment other than the DXII-B must not be mounted in the DXII-B cabinet.

1.4 SPECIFICATIONS
Physical, environmental, and electrical specifications for the DXII-B are contained in the following paragraphs.
IBM
360/370

3601

IOS/

370
USER

ACCESS
METHOD

CHANNEL BUS
PDP-11

DX11-B
EMULATOR
PACKAGE

USER

TERMINAL
AND
DEVICE
DRIVERS

LINES
AND
) DEVICES

11-1229

Figure 1-3 DXII-B Functional Block Diagram

1-5

1.4.1

Physical
Dimensions
(CAB H960)
20-3/16 in.
71-7/16 in.
25 in.

(CAB H957)
20-3/16 in.
47-1/2 in.
25 in.

42 in.
42 in.

Width:
Height:
Depth:
Service Access Dimensions
Front:
Rear:

1.4.2 Environmental
The DX II-B operates under normal conditions of humidity, shock, and vibration.
Ambient Temperature:
Relative Humidity:

50°F to 122°F (10°C to 50°C)
20% to 95% (noncondensing)

1.4.3 Electrical
Estimated Power Consumption (H740) Logic:
Overall AC:

20A@J+5 Vdc
220 VA @ 120 Vac

1.4.4 Performance
Operating Modes:

Program transfer and non-processor transfer depending
upon control unit state and channel function being performed.

Transfer Width:

DXII-B to IBM Channel
Eight bits plus parity for information and six individual
lines for selection and control.
IBM Channel to DX Il-B
Eight bits plus parity for information and eight bits for
selection and control.
DXII-B to/from PDP-II
All standard Unibus interface signals. Sixteen-bit data
path only for data transfers with IBM channel (two bytes/
PDP word).
Parity used between DXII-B and IBM Channel
Odd in both directions.

DX II-B Clock Frequency:

Effective: 2.5 MHz
Internal: 5.0 MHz
Two discrete time pulses, each standard 50 ns width
occurring sequentially 200 ns apart.

DXII-B to CHICH to DXII-B Transfer Rate:

Nominal 250K bytes/sec depending on system (PDP-II
and 360/370) configuration. The theoretical limiting
speed caused by the OX JJ-B clock is JM bytes/sec.

1-6

1.5 ENGINEERING DRAWINGS
A complete set of engineering drawings is supplied with each DXII-B System. The engineering drawings are
bound in a separate volume entitled DX JJ-B Engineering Drawings. A list of applicable engineering drawings
is included in Chapter 7 of this manual. The general logic symbols used on these drawings are described in the
DEC Logic Handbook, 1972. Specialized symbols and terminology, particularly those used in the flow diagrams
for the DXII-B, are explained on the drawings as notes and are further defined in Chapter 5 (Paragraph 5.4.2).
NOTE
The documents described in Paragraphs 1.1 and 1.4 are available
from the nearest DEC Field Office or from:
Digital Equipment Corporation
Communications Services (Direct Mail)
146 Main Street
Maynard, Massachusetts 01754

1-7

CHAPTER 2
INSTALLATION AND ACCEPTANCE TEST

This chapter contains the information and procedures for installing and testing the DXII-B System. This chapter
is not intended to supersede the installation·requirements stipulated in the customer's site plan; however this
chapter supplements that information by providing an installation and checkout procedure to ensure the system
is installed correctly and that the system operates correctly after it is installed.
CAUTION·
Do not attempt to unpack or install ~e DXII-B system
until the DEC sales office has been notified and a DEC
Field Service representative is present. Failure to do so
can void the equipment warranty.
2.1 SUMMARY OF INSTALLATION FUNCTIONS
Installation functions and responsibilities are summarized in Table 2-1. It is very important that the DEC Field
Service Engineer, the IBM CE; and the user be aware of what they must do to ensure a successful installation.
Table 2-1
Summary of Installation Functions
Responsible Personnel

Function

User/DEC Representative

Identify space and power required for system configuration.

User/DEC Representative

Survey Proposed site.

User/Optionally DEC Representative

Prepare site in accordance with customer site plan.

User/DEC Field Service

Fill out diagnostic preparation card.

User/DEC Field Service

Establish Test Schedule.

DEC Field Service

Notify corporate support immediately if any unusual problem that
affects the installation and acceptance test occurs.

DEC Field Service

Unpack and install the equipment.

DEC Field Service

Perform PDP-II and DXII-B Acceptance Test off-line.

User

Arrange forlBM CE to connect DXII-B cables to the IBM system.

DEC Field Service

Connect IBM cables to DXII-B.

User/DEC Field Service

Run on-line and operational test.

2-1

2.2 INSTALLATION AND ACCEPTANCE TEST REQUIREMENTS
The equipment and diagnostics required to install and test the DXII-B should be available before beginning the
installation and acceptance test procedures.
2.2.1

Equipment Required

Table 2-2 contains a list of equipment required for the DX II-B installation and acceptance test.
Table 2-2
Equipment Required for Installation and Acceptance Test
Equipment

Specification

Equivalent Equipment

Oscilloscope

dc to 50 MHz with calibrated deflection
factors from 5 mV to 10 V/division.
Maximum horizontal sweep rate of 0.1
microsec/division. Delaying sweep and
dual trace is desirable.

Tektronix Type 453, 465 or
equivalent

Probes

XIO with response characteristics
matched to oscilloscope.

Tektronix Type P60 I 0

Ground Lead for Probe

Tektronix

DXII-B Maintenance Kit
Jumper Wire

30 gauge

Integrated circuit Pin
Extender

DEC 29-10246

Module Extender Board
for Single Height Module
DEC-Type 142

Tool Kit
The DXII-B Maintenance Kit consists of the following items:
I.
2.
3.
4.
5.

DME, 2848 Diagnostic, and FRIEND (DZDXD-A-C)
G890 Power Fail-Select By-Pass Module
M597 360 Cable Receiver Module
M697 360 Cable Driver Module
M405 Crystal Clock Module @ 5 MHz

All local offices responsible for a DXII-B should have a maintenance kit.
2.2.2 Diagnostics Required
The diagnostics required for the DXII-B acceptance test are listed in Table 2-3.
FRIEND is an IBM Diagnostic Program requiring 16K bytes of memory in the 360/370 and is supplied in the
form of a card deck, containing 186 cards. The user must enter channel commands from the console keyboard
using the English language. FRIEND supports the commands for most of the IBM files, drums, printers, card
readers, punches, etc.
The FRIEND and DME/2848 diagnostic card decks (DZXD-A-C) are part of the DXII-B maintenance kit. This
kit (and/or card decks) is available at all DEC regional field offices.
2-2

Table 2-3
DXII-B Diagnostics
LIBKIT NO. ZJ131-RB
Off Line Test

Number

Maintenance Clock 1
Maintenance Clock 2
Off Line Exerciser
On Line Exerciser

DZDXA-D
DZDXF-D
DZDXG-C
DZDXH-C

On Line Test

Number

2848 Responder
DME, 2848 Diagnostic,
and FRIEND

DZDXC-A
DZDXD-A-C (Cards)
DZDXE-A-C (Cards)

2.2.3 Space Requirements
The DXII-B is mounted in a H960 tall cabinet or H957 short cabinet (Figure 2-1). Cabinets may be placed
individually or attached to other cabinets to form a multibay configuration. The accessories and hardware
included with the cabinet include rear door, front pop off panels, 2 end panels, bezel, logo panels, blower fan
and power controller.
Figure 2-1 shows the dimension of both cabinets. Space should be provided in the front and rear of the cabinets
for access by maintenance personnel.
CAUTION
The DXII-B cabinet must never be shared with other
equipment.
A minimum clearance of 30 inches (75 centimeters) above each cabinet is recommended to permit free circulation
of cooling air. If this requirement cannot be met, some other means of allowing free air flow above and around
the equipment should be provided.
2.2.4 Power Requirements
The power source should be free of conductive interference. All computer system power supplies should be
connected to the same power source to avoid loading and source differentials that may affect computer operation.
The computer cabinets should be tied to a grounding system which provides less than 10 ohms resistance to moist
earth from dc to 10 megahertz. The ground should also be insulated from sources of electrical noise to prevent
noise from entering the system via ground.
The power required for the various DXII-B options is shown in Table 2-4.

2-3

LEGEND
CABINET TYPE

T
1~

DIMEN.

H960-A

H957

20 3116

71 7116

47 112

T
1

1 T

TOP VIEW

1r-

TOP VIEW

r- ----1
l

-----1

1=-=--]

r-s---i

I-A-----1

l
C

....

...'"

SIDE VIEW

FRONT VIEW

.'"'

....

FRONT VIEW

...SIDE
""
""...
VIEW

H957

H960-A

Figure 2-1 H960 and H957 Cabinet Dimensions

2-4

1\-1230

Table 2-4
DXII-B Option Designations
Nomenclature

Cabinet Type

Voltage

DXll-BA
DXll-BB
DXll-BC
DXll-BD

H950
H950
H957
H957

115 Vac
230 Vac
115 Vac
230 Vac

The maximum power required is 600 VA @ 120 Vac.
The DXll-B EPO Panel must be connected to unswitched system power on the DXll-B system 861 power
controller.
2.2.5 Information Requirements
Information determined by the system configuration which varies from installation to installation is required to
run the diagnostics.
Before proceeding the following information must be obtained, before any diagnostics are used. This information
relates to the PDP-II and IBM systems and is necessary to execute any diagnostics.
fuformation

Selected fuformation
(Customer Supplied)

Default

Unibus Address
Vector Address
Priority Level

176200
300

Model 360/370
Channel Type and
Number

Not Applicable

First Control Unit
Address (must
start on zero
boundary)

Not Applicable

IBM System
Main Storage
Memory Size

Not Applicable

Number of Devices
per Control Unit

Not Applicable

The entire DME/2848 diagnostic test procedure in Paragraph 2.14.4 should be read to obtain the information
necessary to fill out the preparation card. Consult the customer and resolve any questions regarding system
configuration prior to obtaining stand-alone time to run the on-line diagnostics.
NOTE
Do not attempt to run the diagnostic at this time,
only obtain the information required.

2-5

2.2.6 Test Schedule
As stipulated in the DEC sales agreement, the customer agrees to provide up to 12 pours of 360/370 Stand Alone
time for DXII-B installation and acceptance testing. Stand Alone means the 360/370 must be dedicated solely to
the DXII-B and not occupied in any way with the customer's operating system.
The DEC Field Service Engineer should consult the customer and schedule the time the On Line-Stand Alone
tests are to begin. All tests in the acceptance test procedure up to Paragraph 2.14 should be completed before
the on line tests are attempted. Prior to the time the test is to be run, the FSE should verify that the customer's
system will be available as a stand alone system at the scheduled time.
In order to use this time efficiently, the following guidelines should be followed by the FSE.

An FSE untrained in the DXII-B should not use more than one hour of stand alone time to diagnose
on line failures. An FSE who is trained may use up to two hours. More time should not be used unless
instructions to do so are received from Regional or Corporate Support.

Regional Support can authorize use of an additional two hours of stand alone before notifying
Corporate Support.

If Corporate Support cannot resolve the problem within an additional four hours of stand alone time,
assistance must be obtained from DEC Engineering.

During installation and any time thereafter, any unresolved problem should be reported to both
Regional and Corporate Support by the local Field Service Office. These problems typically are the
type that involve software.

2.3 UNPACKING AND INSPECTION
CAUTION
Do not attempt to unpack or install the equipment
until a DEC Sales Office has been notified and a DEC
Field Service Engineer is present. Failure to do so may
void equipment warranty.
2.3.1 Unpacking
The DXII-B is mounted in a DEC H957 or H960 cabinet and is shipped on a pallet mounted container. A
forklift truck is necessary to move the container to its final location. To unpack and install the computer only
small hand tools, pliers, screwdrivers, etc. are required.
To unpack the equipment follow the steps listed below;
I.

Remove the outer shipping container;
NOTE
The container can be either heavy corrugated cardboard
or plywood. Remove all metal straps first, and then
remove any fasteners and cleats securing the container
to the skid. If applicable, remove the wood framing and
supports from around the cabinet.

2-6

After removing the outer container, if applicable, remove the cardboard container.

Remove the polyethylene cover from the cabinet.

Remove the tape or plastic shipping pins from the cabinet rear door.

Unbolt the cabinet from the shipping skid. The bolts are located on the lower supporting side rails and
can be reached by opening the access door.

Raise the leveling feet above the level of the casters.

Use wooden blocks and planks to form a ramp from the skid to the floor and carefully roll the cabinet
onto the floor.

Roll the cabinet to the prepared site.

2.3.2 Inspection
After unpacking, inspect and inventory the equipment.
1.

Inspect the external surfaces of the chassis for surface, switch, and light damage, etc.

Inspect the inside of the cabinet for damage, loose or broken modules, fan damage, loose nuts, bolts,
screws, etc.

Check the equipment, documents, software, received against the shipping list and verify all equipment
was received. If an item is missing, notify the DEC Sales Office and transporting agency as soon as
possible.

Ensure that the modules, hold down bars, and module clips are secure.

2.4 INSTALLATION
After the cabinet is rolled to the prepared site, it should be leveled by adjusting leveling feet at the bottom of the
cabinet.
2.4.1 PDP-ll and DXll-B Cable Installation (within PDP-ll System)
Connect DXII-B cables as follows:
I.

Ensure the circuit breaker on the H740 power supply, and the circuit breaker on the 861 control
panel at the bottom of the cabinet are OFF.

Connect the Unibus cable (see Figure 2-2 for cable location) to the PDP-II Unibus. The DXII-B must
be the first NPR device on the Unibus. That is, the Unibus cable must be inserted in a Unibus slot that
is electrically closer to the processor than any of the other NPR devices installed on the Unibus.
CAUTION
Do not connect IBM system cables at this time.

Connect the power control from the DXII-B EPO Panel to Jl, 12, or 13 on the 861 power controller.

Connect the power control cable (part number 70-0-08288-8) from the DXII-B 861 power control
to another power control on the system.

2-7

INDICATOR
PANEL

-~
32

/V /

v----;-

---

INDICATO R
CONNECTOR S

I---

1
M9 OaYB
ADD RESS
CA RD

B
IN
32 31
UNIBUS
CONNECTORS
(M930 )

-I- r

D
OUT OR~...TERMINATOR

i-'r
E
2
8 FROM
... 1-~90
EPO CONTROL

F
STORAGE
LOCATION
FOR M9B4 ' TERMINATORS

"14

0807

,/r;\

t---

TAG CABLES

t---

r'I~,

(~~~ /

BUS CABLES

THE TOP CONNECTOR S
IN THIS ASSEMBLY AR E
'--------ALWAYS THE DARK COLORED AND
THE BOTTOM CONNECTOR ARE
LIGHT COLORED .
." For OX 11 cable loop around test move the following cables

H07 to H 17 and place M984 in H07
J07 to J 17 and place M984 in J07
H14 to H 18 and place M984 in H14
J14 to J18 and place M984·YA in J14
Mate together the corresponding IBM Connectors contained within the DX11 assembly, i.e., the

IN BUS cable is removed from the bracket and mated to the OUT BUS cable. The same thing is
done for the TAG cables. When the cables are mated, a dark colored IBM plastic connector
housing should be mated to a light colored IBM plastic connector housing. Do not mate the

same color connectors together. (See Figure 2-3,)
11-3459

Figure 2-2 DXII-B Cable Connections Configured for User Operation
(Viewed from Rear)
2.4.2 IBM Device Address Jumper Installation
The M908-YB address jumper card (Figure 2-4) located at A20 has the jumpers cut for 10 Hexedecimal at the
factory. If some other address is used by the DX II-B that is being installed, the jumpers must be changed to
select the assigned address. The card is equipped with split lugs for easy wiring.

2-8

TYPICAL
RETAINER
BAR

UNI BUS
CABLE
LOOSEN
SCREWS
S SLIDE
RETAINER
PLATES
BACK
TO REMOVE
RECEPTACLE

DXII-B
TERMINATOR
CARDS ARE
STORED IN
EMPTY
SLOTS ON
LOWER LEFT

6257-6

Figure 2-3 DX11 - IBM Cable Assembly
Configured to Execute Cable Loop Around Test DZDXH
Any standard wire can be installed on the split lugs as jumpers. However, the number 30 wire wrap carried by all
DEC Field Service Engineers is adequate.
The I/O address format is shown in Figure 2-5. The DX11-B never sees the 8-bit channel address portion of the
I/O instruction. There are four of these instructions by which the 360/370 CP controls I/O operations. These
are: (1) Start I/O, (2) Test I/O, (3) Halt I/O, and (4) Test Channel. A Test Channel Instruction does not issue
an I/O address, but for the other three, the address is generated and decoded as described in Paragraph 5.5.21.
Figures 2-6 through 2-11 give wiring examples. Some of the examples are explained in the following paragraphs.
Figure 2-6 shows the wiring for four device addresses in the range 3x. Pins K and H are grounded by jumpering
to pin C. Pin L isjumpered to pin B and pin E is tied to pin D.
In Figure 2-7, jumpering pin B to pin V2 and then running the jumper to pins U through M, the first hex digit is
decoded by an MISS module at location A19. When pins K, H, E, and Bare jumpered to pin C (gnd), the
DX11-B ignores the second hex digit causing it to automatically respond to device addresses 10 through IF.
Figure 2-8 is an example of wiring for the 32 device addresses 50 through 6F. Note that pin F (5x) is tied to pin
V2, while pin H (6x) is tied to pin U before being jumpered through pin M. The second digit is responded to as
it is in Figure 2-7.
Using the examples in Figures 2-6 through 2-11, the wiring for any combination can be derived.

2-9

~~~~~~~~~~~~~~~~~~
A1@()OX
B@()1X
C@()ZX

@)VZ
@)U
@)T
@)S
@)R
@)p

D@()3X
E@()4X
F@X)5X
H@X)6X
SETS
CU
ADDRESS

@)N

J@X)7X
K@X)BX
L@X)9X
M@()AX
N@()BX

@)M
@)L
@)K
@)J
@)H

P@X)CX
R@()DX

@)F

SETS
DEVICE
ADDRESS

@)E
@)D
@)C
@)B
@)A

S@X)EX
T@X)
U@)
V@)

SETS
CU
ADDRESS

~~ 0

0
11-12.31

Figure 2-4 M908 Module Before Wiring

I/O INSTRUCTION
360/370
I/O ADDRESS

2324

1516

31
NOTE THATCU IS
TRANSPARENT TO
THE 360 SYSTEM!

CU ADDRESS

ONLY VAUO
CHANNEL
ADDRSSES
(0-6)

{!
0
0
0
0

0
0
0
0
0
0
0

0
0
0
0
1
1

0
0
I
I
0
0

0
I
0
I
0
I
0

0
0
(OR 0)

THROUGH

1
1
(OR F)

NOTE

DXl1-B CAN
DECODE ANY
EIGHT OF
THE SIXTEEN

DXll-B CAN
DECODE
ALL SIXTEEN
11-1232

Figure 2-5 I/O Address Format

2-10

~~~~~~~~~~~~~~~~~~

~~~~~~~~~~~~~~~~~~
AIOODX

SOO1X

COO2X

EOO4X

V2
U

COO2X

DOO3X

SETS
CU
ADDRESS

EOO4X

FOO5X

F@X)5X

SETS
CU
ADDRESS

HOO6X

J@X)7X

JOO7X

)~~~

LOO9X

MOOAX
NOOSX

KOO8X

KOO8X
LOO9X
MOOAX
NOOSX
pOOCX
ROODX
SOOEX

pOOCX

SETS
DEVICE
ADDRESS

ROODX
SOOEX

TOO

U@
V@

~~ 0

j 1-1233

11-3453

Figure 2-6 Example of Wiring for Four Devices

Figure 2-7 Example of Wiring for 16 Devices
10 through 1F (1 x)

~~~~~~~~~~~~~~~~~~

U
C 0

T
SETS
CU
ADDRESS

DOO3X

E@X)4X
FOO5X

HOO6X

JOO7X

KOO8X

SETS
CU
ADDRESS

LOO9X

KOO8X
LOO9X
MOOAX
NOO8X

MOOAX
NOO8X
pOOCX

pOOCX

ROODX

SooEX

SOOEX

TOO
U@

TOO
8

~~ 0
0

SETS
DEVICE
ADDRESS

8
FX

~.~

~~ 0

o
11- 3452

11-1234

Figure 2-9 Example of Wiring for One Device (10)
(Not Supported by DXII-B Diagnostics)

Figure 2-8 Example of Wiring for 32 Devices
50 through 6F (5x and 6x)
2-11

~~~~~~~~~~~~~~~~~~

~~~~~~~~~~~~~~~~~~
Al@()OX
B
1X
C@()2X

SETS
CU
ADDRESS

Al@()OX

U
T

B@()1X
C
2X

U
T

SETS
CU
ADDRESS

D@X)3X

E@()4X

D@()3X

E@()4X

F@()5X
H@()6X

F@()5X

H@()6X

J@()7X

K@()8X

L@()9X
M@()AX
N@()BX
P@()CX
R@()DX
S@()EX
T@()
U@)
V@)

~~
~~

SETS
CU
ADDRESS

K@()8X
L@()9X
M@()AX
N@()BX

SETS
DEVICE
ADDRESS

P@()CX
R@()DX
S@()EX

T@()

U@)
V@)

B
FX

@)A

~~ 0

@)A

~~ 0
0

SETS
CU
ADDRESS

11-3455

11 ~3454

Figure 2-11

Figure 2-10 Example of Wiring for Two Devices
(10 to 11)

Example of Wiring for 8 Devices
(20-27)

2.4.3 Interrupt Vector Address Jumper Installation
A floating vector convention is used for the DXll-B and other communications devices in the PDP-II system.
These vector addresses are assigned in order starting at 300 and proceeding upwards to 777. The first vector
address 300 is assigned to the first communication device in the system and if another communication device
is used, it would then be assigned the vector address 310. The vector addresses (up to a maximum of 32) are
assigned for each communication device in the system. For more information, see Appendix B.
Jumpers W2-W8 on the M7821 module must be configured to select the Interrupt Vector Address (see Drawing
D-BS-DXII-B-18). Jumpers are removed to obtain a logical zero and installed to obtain a logical 1.

2.S TURNING POWER ON FOR THE FIRST TIME
When power is turned on for the first time, the switches on the PDP-II computer, the DXII-B, and all peripheral
options should be set to the correct position for system operation. The DXII-B is not connected to the channel
at this time.

2-12

The procedure is as follows:
1.

Ensure the DXII-B, the PDP-II computer, and all peripherals are connected to the same ac power
source. The 861 Power Control Unit in the DXII-B must be connected to an unswitched power
source if the EPO panel is used in the system.

Place the SYSTEM/LOCAL Switch (Figure 3-1) to the LOCAL position.

Ensure the circuit breaker on the 861 power control panel is ON.

On the H740 power supply, ensure the circuit breaker is pushed in.

Turn the PDP-II computer power ON and verify fans are running.

Set ENABLE/HALT to HALT.

Ensure all peripheral devices connected to the UNIBUS are powered up.

2.6 PDP-Ii SYSTEM TEST WITHOUT DXI1-B
Perform the PDP-II Acceptance Test procedure for the PDP-II processor used with the DXII-B. The customer
acceptance procedure document for the processor is shipped with the system and the processor diagnostics
should be loaded and run according to procedures described in the related customer acceptance procedure. Refer
to the System Maintenance Manual for details on the test procedure for the processor.
After testing of the processor is completed run the Customer Acceptance Test Procedure for each of the devices
in the system.
CAUTION
The configuration shown in Figure 2-9 is not supported
by DXI1-B diagnostics. Configurations of 2 or more
devices are supported.
Control and Indicator Panel Lamp Check

2.6.1

Perform the following steps to verify all lamps on the Control and Indicator Panel will light.
I,
2.

Turn PDP- I 1 power OFF.
Remove the four connectors in back of and on the left hand side of the Control and Indicator Panel in
slots A29, A30, A31, and A32. (Figure 2-2).

Turn PDP-II power ON and verify all lamps on the panel are lit. If not, replace the burned out
lamp(s).

Turn PDP-II power OFF and replace the four connectors that were removed in step 2.

2.7 DXII-B TEST WITHOUT IBM 360/370TOFF LINE)
All diagnostics that do not require the DXIl-B to be connected to the IBM 360/370 system should be run and
any hardware malfunctions that occur should be repaired before the DXII-B is connected to the IBM 360/370
system for on line tests.

2-13

CAUTION
Do not connect the IBM 360/370 cables to the DXll-B
for these tests.
Load the DXII-B Maintenance Clock 1 Diagnostic MAINDEC-II-DZDXA-[REVJ-PB (use latest revision). Refer
to the software abstract (MAINDEC-II-DZDXA-[REVJ-D for loading instructions. Run the entire diagnostic a
minimum of two passes with iterations. No errors are allowed.
2.7.1 M306 NPR Timeout Mono Calibration Procedure
To calibrate the NPR Timeout Mono, proceed as follows:
1.

Place channell (sync) probe on the output of the NPR DLY Mono (Pin F04S2). Set oscilloscope
controls to following positions:
a.

AC Low Frequency Reject

POS SYNC

Time Base to 100 microseconds/division.

INTERNAL SYNC to CHANNEL 1.

Place channel 2 probe on the NPRX flip-flop (pin F04H2).

Restart the Maintenance Clock 1 Diagnostic (DZDXA).

Select and loop on test 15. See diagnostic write up for instructions.

Adjust the mono potentiometer in slot F04 to 12 J.l.s. (NPRX(1) L neg, edge to NPRDLY). Put XIO
magnifier on to make measurement (Figure 2-12).

' - - - - - - t - NPRDLY - F04S2
100~s/DIV.

I
I

r--_ _+_NPRX (t) L-F04H2

~_ _

X 10 MAG. ON

10~s/DIV.

~:..L.--:
-----111111
II-

--I

12,..

Figure 2-12 NPR Timeout Mono Calibration Waveform

2-14

11-1236

2.7.2 BLLM Calibration
This test ensures that BLLM is calibrated for the optimum data transfer rate (250K byte/sec). To perform the
BLLM calibration proceed as follows:
1.

Set up the oscilloscope as follows:
a.

Channell to 2 V /mv

Timebase to 2/ls/mV

SYNC on (NEGATIVE SYNC and NEGATIVE going signal)

Select and loop on Test 16. The instructions are in the write up with the diagnostic.

Use channell to monitor E32H2

Adjust the top potentiometer on module E32 until there is 4 JlS between leading edges of the signal
(Figure 2-13).

~IE~---- 4~s -------~~I

SRVI(l) L
(E32 H 2)

--"""'U

L
11-3456

Figure 2-13 BLLM Calibration Signal

2.7.3 Run the DXll-B Maintenance Clock 2 Test (MAINDEC-ll-DZDXF-[REV]-PB)
Refer to the software abstract for loading and running instructions. Run a minimum of two passes with
iterations. No errors are allowed.
2.7.4 Run the DXll-B Off-Line Exerciser (MAINDEC-ll-DZDXG-[REV] -PB)

Refer to the software abstract for loading and running instructions. Run a minimum of two passes with
iterations. No errors are allowed.
2.8 DXI1-B CABLE TEST
To test the DXII-B offline without IBM cables proceed as follows:
NOTE
The system is shipped with the cables connected for
this test. However, they should be checked using the
following procedure to ensure they are connected
. correctly (Figure 2-14). This procedure may also be
used to run the on-line cabled test at a later time
after installation is completed. If errors occur and
cable signals must be monitored with an oscilloscope,
refer to Paragraph 2.18 (Figure 2-16).

2-15

The DXII-B cable configuration should be as follows: (Refer to Figures 2-2 and 2-14).
1.

Cable normally in H07 moved to H17.

Cable normally in J07 moved to 117.

Cable normally in Hl4 moved to HI8.

Cable normally in 114 moved to J18.

M984 terminators should be installed in H07, J07, and H14.

A M984-Y A terminator should be installed in J 14.

The TAG cables should be connected together (Figure 2-14). The Bus cables should also be fastened
together in a like manner. Dark connectors should be connected to light connectors.

Load and run the DX11-B on-line cable test (MAINDEC-l1-DZDXH-[REVJ-PB). Refer to software
abstract for loading and running instructions. Run a minimum of two passes with iterations. No errors
are allowed.
TYPICAL
RETAINER
BAR

UNI BUS
CABLE
LOOSEN
SCREWS
S. Sli DE
RETAINER
PLATES
BACK
TO REMOVE
RECEPTACLE

DXII-B
TERMINATOR
CARDS ARE
STORED IN
EMPTY
SLOTS ON
LOWER LEFT

6257·6

Figure 2-14 Test Bus Cable Connections Without IBM 360/370 Cables
Supplied By Customer

2-16

DX11-B
TERMINATORS
STORED IfERE
WHEN NOT
IN USE

IBM
CABLES
6257-4

Figure 2-15 Test Bus Cable Connections Using IBM 360/370 Cables

2-17

2.8.1 On Line B Delay Adjustment
1.

Restart the DXIl-B On Line Cabled Exerciser (MAINDEC-ll-DZDXH-[REVJ-PB).

Set the Switch Register to 4000 to inhibit operations (SWll = 1).

Set the oscilloscope up as follows:
a.

2 V/cm on CHI.

select CHI only.

set trigger on NORMAL and trigger on edge.

set sweep rate for 2 ms.

Connect CHI scope probe to pin E32T2.

Adjust the lower potentiometer on the M302 module in E32 until the output of the delay is high for
5 to 6 ms.
NOTE
Figure 2-16 illustrates the signal flow for test
connections.

B IT PROGRAMMABLE

r-----------------

AT PDP-It

PIO

,----

-------

DXMO
REGISTER,

IBM cable is butted
together. The signals
are passed through
these cables in a
straight line. As on
ellomple G07 of one

OX-II BACK
PANEL
CONNECTION

INTERNAL
1-_---,________ MAINTENANCE

IBM connector

MOOE

corresponds to G07

of the other.

L_
BUS IN

TO BUS IN

MAINTENANCE
r--------

PIO
DXMI

iL ___ .....I _ _ _ _ _ _ _ _ _ ___ JI

~ ---- ------- ___ ~11~~!1~,!c!
LEGEND
EXTERNAL MODE
V IA IBM CABLES

--4---

SIT PROGRAMMABLE

AT PDP-It
P/Q

DXMO
REGISTER

INTERNAL
MAINTENANCE MODE

COMMON PATHS FOR
BOTH MODES
11-,3458

Figure 2-16 Signal Flow for Test Cable Connections

2-18

2.8.2 DXTO Calibration Procedure
TIus procedure ensures that when OPERATIONAL IN is set and if the program does not interact for 5 seconds
the DXTO flip-flop sets. To calibrate DXTO proceed as follows:
NOTE
TIlis is a visual check procedure. You must observe
the DXTO and OPLI lamps on the control and indicator
panel and determine the time between the lighting
of OPLI and DXTO. DXTO should light 5 sec after
OPLI.
1.

Set ENABLE/HALT to HALT.

Hit START to cause DXll initialization.

Set switch register to 176216 and hit LOAD ADDRESS: This operation selects the DXMI.

Set switch register (SR) to 100000 and hit DEPOSIT to cause Operational-In to set (OPLI).

Approximately 5 seconds later, DXTO should set as indicated by the DXTO lamp lighting.

Repeat Steps 2 through 5 as necessary. Adjust the potentiometer on the M306 module in slot F03
so that the DXTO sets approximately 5 seconds after OPLI is set.

2.8.3 IBM 360/370 Cable Test Using DXII-B to Test Cables Without IBM 360/370 System
Tllis test checks the continuity IBM 360/370 cables supplied by the customer. Tlus test should be run if the
user supplied channel cables are available. If not go to Step 6 in this section.
NOTE
The DXII-B is not connected to a channel on the IBM
360/370 for this test.
To test the IBM 360/370 cables proceed as follows:
1.

In the rear of the DXII-B cabinet disconnect the IBM connectors that have been mated together.
Return them to their normal position in the mounting receptacle. Do not move the flip chip
connectors in the DX Il-B back panel.

Temporarily label one user cable as TAG and the other cable as BUS (Figure 2-2).
CAUTION
The IBM cables should always be mated dark-to-light
and light-to-rlark. Interchanging TAG and BUS cables
will cause incorrect operation, but will not harm the
equipment. Use care in mating these plugs to prevent
damage to pins. If cables are damaged, notify support
immediately.

Connect one end of the TAG cable to the control TAG from the channel receptacle of the DX11-B.
Connect the other end of the control TAG cable to the next unit TAG receptacle of the DXII-B
(Figure 2-15).

2-19

Con'nect one end of the BUS cable to the DATA BUS from the channel receptacle of the DXI1-B.
Connect the other end of the DATA BUS cable to the next unit BUS receptacle of the DXII-B
(Figure 2-15).

Load and run the DXII-B On Line Cabled Test (MAINDEC-I1-DZDXH-[REVJ -PH). Refer to the
software abstract for loading and running instructions. Run a minimum of two passes with iterations.
NOTE
DXll-B Off Line Testing and calibration is now complete.
The DXI1-B can now be changed from the maintenance
cabled mode to the normal on-line (user) mode. TIle
DXII-B need not be configured in the maintanence mode
again except to verify channel receivers, drivers, and
on-line A and B logic when a hardware failure is suspected.
All preventive maintenance and most corrective maintenance can be accomplished while the DXI1-B is connected
to the IBM channel.
Refer to the software abstract for the instruction to load and run the diagnostics.

Remove the IBM 360/370 cables and return the cables to their normal configuration as follows:
a.

Remove terminator cards from H07, J07, and H14 and replace in 129, 130, and J31
respectively.

Remove terminator card M984-YA from JI4 and replace in J32.

Move cable connector H17 to H07.

Move cable connector 117 to J07.

Move cable connector Hl8 to H14.

Move cable connector JIS to 114.

Remove the channel cables if attached for the cable test (Figure 2-15).

Disconnect the DXll-B cables from the loop around position (Figure 2-14) and return them to
to the normal position.

2.9

FILLING OUT TEST PREPARATION CARD

The preparation card in Figure 2-24 should be filled out at this time. Refer to Paragraph 2.14.S for the
procedure.
NOTE
Figure 2-21 is a sample of this card.

2-20

2.10

I/O CABLE REQUIREMENTS

The customer is required to supply all necessary material to make the physical connection between the DXII-B
and the IBM system. In most configurations this will consist of the following material:
IBM BUS Cables
IBM #5353920

This 40 position cable can be used in all systems except when the two byte interface
is implemented on the IBM channel. At least two of these cables are required.

IBM #5466456

This 48 position cable can be used on all systems. It is required when the two byte
interface is implemented on the IBM channel. At least two of these cables are
required.
NOTE
The same cables are used for TAG lines and DATA
BUS lines.

IBM Channel Terminators
There are fourIBM channel terminators available, these terminators are used in pairs (i.e., one for TAG line and
one for DATA BUS lines). Thus there are two distinct sets. The set to be used on a given system is dependent on
the IBM BUS cables used. These terminators are used in the DXII-B only if it is the last Control Unit on the
channel.
If IBM cable #5353920 is used then the BUS terminator must be IBM #540649 and the TAG terminator of this
set is IBM #540650.
If IBM cable #5466456 is used then the BUS terminator must be IBM #2282675 and the TAG terminator of this
set is IBM #2282676.

IBM EPO Cable (IBM No. 5351178)
The IBM EPO cable may be required, depending on the requirements of the installation itself. The DXII-B can
be used on the channel without this cable. The function of this cable is to place the power sequencing of the
entire PDP-II under control of the IBM system.
NOTE
Even if the EPO cable is installed the PDP-II system
power can be controlled with the PDP-II console key
switch, by switching the DXll-B EPO Panel
SYSTEM/LOCAL switch to LOCAL.

2.11

CONNECTING DXll-B CABLES TO mM CHANNEL

Each IBM BUS cable consists of 40 or more coaxial conductors, these conductors are encased into one cable
assembly by, a thick vinyl casing. Each conductor of this assembly is terminated in a rectangular plastic mounting
box by a gold U shaped pin. These pins are durable but extreme care should be used when mating the cables.
The rectangular plastic mounting blocks used at each end of the cable are color coded. One end of the cable
block is light gray or brown, and the opposite end of this same cable block is dark gray or black. This is true
regardless of what type of IBM cable is used. This color coding is used when mating IBM BUS cables to
peripherals or other BUS cables. When mating connector blocks always mate unlike shades together, light gray or
brown to dark gray or ,black. Note that the light gray cable can be mated to the black block and the brown block
can be mated to the dark gray block.
2-21

TAG
CABLE

TAG
TERMI

DO NOT CONNECT
UNTI L OFFLINE CHECKOUT
IS COMPLETE
6257-5

Figure 2-17 Normal Cable Connections to Channel Bus if on End of Bus

2-22

Figure 2-18 Normal Cable Connections to Channel Bus if Not on End of Bus

2-23

These connection procedures must be followed to ensure that the proper conductors are mated. If identically
shaded blocks(i.e., light to light) are mated the cable connections at this point are reversed.
To install the cables procede as follows:
1.

Po_wer down the PDP-II system and be sure that the DXII-B ON LINE ENABLE switch is in the
OFF LINE position and that the SYSTEM/LOCAL switch is in the LOCAL position.

Using the procedure listed in the previous paragraph ensure that all cables and connector blocks
within the DXII-B are moved to their normal position (Figure 2-2).

To ensure an orderly installation request that the customer diagnostics be executed on the channel to
which the DXII-Bis to reside on; This can be done by customer or IBM personnel. The purpose of
this test is to verify the integrity of the channel.

Reguest thaUhe customer Stop the IBM system by pressing STOP on the 360/370 console. It is not
necessary to power down theIBM system. Do not pro cede until the system is stopped.

Have the customer or IBM personnel connect the IBM BUS and TAG cables to the channel. This
connection is made at the channel itself or at a peripheral on the channel depending on the DXII-B
position which is designated by the customer. Before connecting the cables mark them for identification, the cables should be marked at both ends. One cable Should be marked TAG and the other
DATA BUS. When the cables are connected to the IBM system they should be connected so that
light Shade color connectors are presented to the DXII-B.

DEC personnel should now connect the labeled cables to the DXII-B. Connect the TAG and DATA
BUS cables received from the channel or control unit closer to the channel to the connector mounted
within the DXII-B. This is the top connector in each section and is a dark shaded connector.

When mounting this connector inspect the pins on each block before mating the two together. If bent
pins are found straighten them if possible. To mate the connectors slide them together by hand. Before
tightening the securing screw in the connector block ensure that the maximum space between the
front surface of each block is less than 1/16 of an inch.

IUhe DXII-B is not the last device on the IBM channel connect the cables to next control unit on the
BUS after the DXII-B by repeating step 7. The bottom set of connector blocks are used to propogate
the channel signals. These connectors on the DXII-B are a light shade and the cable connectors
mated to them are dark shade (Figure 2-20).

If the DX Il-B is the last device on the IBM channel place the customer supplied terminators in the

bottom set of connector blocks. Since these two terminators are not identical ensure the proper
connector block and terminator are mated (see Figure 2-2).
2.12 EPO Cable Connection
1.

If the EPO cable is to be used have the customer or IBM personnel power down the IBM system. If

the EPO cable is not used, proceed to Paragraph 2.14.
2.

If the EPO cable is to be used have the customer or IBM personnel plug the EPO cable into the EPO
controller. The EPO cable is supplied by the customer. Connect the customer supplied EPO cable to
the DXII-B. This connection is made at the EPO and power control panel, which is mounted
directly below the DXII-B logic panels. This is the same panel that the ON LINE and SYSTEM/LOCAL
switches are mounted on. The connector for the EPO cable is mounted in rear of this panel. The
connector is a six pin female socket mounted on stand-off near the center of the panel.
2-24

2.1 3

EPO PANEL CHlECK

The following test verifies that power can be applied locally by the PDP-II console keyswitch or remotely by
the IBM 360/370 system. This test is performed only if the customer supplied EPO cable is connected to the
DXll-B.
1.

Turn PDP-II power OFF using the console keyswitch. The IBM system should still be powered down
from Step 2.12.

On the DXl1-B set ON LINE ENABLE switch to OFF LINE.

Set LOCAL-SYSTEM switch to SYSTEM.

Turn the PDP-II console switch ON.

Verify the PDP-II system remains powered down.

Have the customer or IBM personnel power up the IBM 360/370.

Verify DXII-B power is ON.

Have customer or IBM personnel power down the IBM 360/370.

Verify the PDP-II system is powered down.

10.

On EPO panel set LOCAL-SYSTEM to LOCAL.

11.

Verify the PDP-II system is now powered up.

12.

Turn CPU power OFF and verify power is off.

13.

The IBM 360/370 system may now be powered up.

14.

With the LOCAL-SYSTEM switch in the local position, the PDP-II system power is controlled by the
PDP-II console key switch in the normal manner.
With the LOCAL-SYSTEM switch in the system position, the PDP-II system power is controlled by
the IBM 360/370. However, the PDP-II console key switch must be in the on position. In this
configuration the PDP-II system can be powered down at any time via the console key switch, but
will only be powered up when the IBM 360/370 is powered up and when the PDP-II console key
switch is in the on position.
If the EPO cable is not used, the LOCAL-SYSTEM switch should always be in the LOCAL position.
NOTE
Once the EPO cable has been installed, it should not be
unplugged from the DXll-B without replacing the IBM

360/370 end with a jumper plug. Otherwise the IBM
360/370 power sequencing will hang the next time it is
powered up.
After all cables, including the EPO cable, if used, have been connected, repeat step 3, Paragraph 2.11 to ensure
that the DXII-B is not affecting channel operation. Ensure that the DXII-B ON LINE/OFF LINE switch is in
the OFF LINE position.
NOTE
The DXII-B is not completely tested until the on-line
test in Paragraph 2.14 is completed.
2-25

2.14 DXII-B SYSTEM TEST USING IBM 360/370
This section provides the information and procedures to test the DXII-B on-line. These tests determine whether
or not data can be transferred properly between the DXII-B and the IBM 360/370 system. The IBM FRIEND
Diagnostic and the 2848 Diagnostic are used to run these tests.
NOTE
Prior to starting the on-line system test, read the
information in Paragraphs 2.15 through 2.18. These
three paragraphs provide some very useful information about problems encountered while the oil-line
tests are being performed. Figure 2-16 shows the
signal flow for the test connections.
2.14.1

Introduction

FRIEND is an IBM Diagnostic Program requiring 16K bytes of memory in the 360/370 and is supplied in the
form of a card deck, containing 186 cards. The user must enter channel commands from the console keyboard
using the English language. FRIEND supports the commands for most of the IBM files, drums, printers, card
readers, punches, etc. However, only commands related to the DXII-B's emulation of a 2848 will be discussed
here.
For additional information, refer to FRIEND program description documentation which should be available at
most DXII-B sites.
The on line diagnostics should be run in the following order:
I.

Run FRIEND in the 360/370 with CTP (REV G or later) in the PDP-II, for a minimum of 10 minutes
without error.

Run FRIEND in the 360/370 with 2848 RESPONDER in the PDP-II, for a minimum of 10 minutes
without error.

Run DME/2848 Diagnostic in the 360/370 with 2848 RESPONDER in the PDP-II. Run a minimum
of two passes (the cards must be reloaded for each pass) without errors, except as indicated.

2.14.2 Test Preparation
Prior to requesting stand alone time to run the FRIEND diagnostic, the FSE should:
I.

Request that the customer's 360/370 operator assist in loading the FRIEND diagnostic.

Because FRIEND is capable of writing on the customer's tapes, drums, disks, etc. if the wrong device
address is accidentally typed, request that the customer write protect or disable all such devices.
CAUTION
Some 360/370 models (Models 128, 158, 168, and
some other systems with a CRT console) may use a
different command structure. Check with the customer to determine if the console command
structure is standard. If the command structure
is not standard, the DXl1-B cannot be tested as
described in this procedure. If this is the case,
contact Corporate Product Support for assistance.

2-26

2.14.3 FRIEND Diagnostic Operating Procedure
NOTE
If the IBM system is a 370 system and has the 3270
CRT display console do the first three steps of this
procedure and go to Paragraph 2.14.9 for the FRIEND
and DME/2848 diagnostic loading procedure.
To load and run the FRIEND diagnostic proceed as foJIows:
1.

Load one of the foJIowing programs into the PDP- I I. Refer to the write-up for details on starting the
program.
NOTE
DEC/XII is a replacement program for CTP. CTP
should be used until the DEC/XII ON-LINE
module is available.
a.

2848 Responder (MAINDEC-II-DZDXC-A).

NOTE
The 2848 Responder is capable of running up to 2
devices (channel) simultaneously. The control unit
address contained in the PDP- I I Switch Register
when the program is started, and that address plus
I. If the DXII-B is to be exercised at any additional
control unit addresses, the 2848 responder must be
restarted with the new control unit address loaded
in the Switch Register.
b.

CTP (MAINDEC-II-DZQCA-G). Use only
Revision G or later and select the DX II-B for
on-line operation.

DEC/XII. Select the DXII-B on line module.

NOTE
CTP and DEC/XII are capable of running up to four
devices (channel) simultaneously. The control unit
address contained in the PDP-II switch register when
the program is started, and that address plus I, 2, and
3. If the DXII-B is to be exercised at any additional
control unit addresses, CTP or DEC/XII must be
restarted with the new control unit address loaded
in the Switch Register. When CTP or DEC/XII are
used, run the first pass with all devices except the
DXlI-B deselected.
NOTE
If the 370 has a 3270 type console, refer to Paragraph
2.14.9.

Place FRIEND deck in the 360/370 card reader with the cards face down and Row Nine on the cards
positioned toward the card reader.
NOTE
All 360 console inputs are terminated by EOB, obtained
by pressing ALT mode and 5 simultaneously on the 360
console. On 370s, press END on the console. This refers
to every line entered.
2-27

Press START and EOF (End of File) on the card reader.

Wait for the READY indicator on the card reader to illuminate.

Refer to Figure 2-20 and set the 360/370 load unit switches to the card reader address (usually OOC).

Press the blue LOAD button the the 360/370,

The card deck will now load and the console will print an introductory message. The introductory
message ends with FRIEND asking for the 360/370 CPU model.
CPU Model XX =

Answer by typing 25, 30,40,50,65, or 75 for the correct 360 CPU model. (For all 370 models, reply
with 75. For 360/67, reply with 65.)

Next, FRIEND will ask for the device address by typing DEV =.

10.

Answer by typing the Control Unit address (including Channel number) of the DXII-B (in
Hexidecimal). This Control Unit address was specified to the PDP-II when CTP, DEC/XII, or the
2848 Responder were started.
NOTE
EOB on the SELECTRIC is equivalent to END on the
hardcopy matrix or ENTER on the 3270 CRT.

II.

12.

Now type the channel program using one of the following examples:
a.

Use Example I in Table 2-5 - If the 2848 Responder is running in the PDP-II.

Use Example 2 in Table 2-6 - If CTP or DEC/XII is running in the PDP-II.

If you wish to change the channel program after Example I or 2 has been started:

Press REQUEST on the 360/370 console device: This terminates any data transfer in progress.

Wait for the PROCEED light to illuminate.

Type the following:
RESET (EOB)

Then, FRIEND responds with:
DEV=

Then proceed to type in the DXII-B's address and channel program per Example I or 2
(Tables 2-5 and 2-6).
NOTE
Figure 2-19 is a sample of FRIEND introductory
message and channel program.

13.

Allow FRIEND to run for a minimum of 10 minutes with the 2848 RESPONDER and a minimum of
10 minutes with CTP or DEC/XII. No errors are allowed.

2-28

Table 2-5
EXAMPLE 1
In this example FRIEND writes 480 bytes of EBCDIC character 0 (octal 360) from the
buffer designated $a to the DXII-B. FRIEND reads this data back and stores it in the buffer
designated $b. Buffers $a and $b are then compared. Any differences are printed out on
the 360/370 console as a data error. The data transfer continues until REQUEST is pressed
on the console. (Refer to Figure 2-20).
NOTE
Program queries are underlined.
X =Channel number
YY = Control unit address (in HEX)

~XYY(EOB

cmd 01 from $a (EOB)
DATA = 480cO (EOB)
cmd 06 into $b (EOB)
!21..:: 480 (EOB)
compare $a, $b (EOB)
go (EOB)

F R I E ~ D -3-

D~SCRIPTIO~

*~ARNING*

CUMMANUS MAY DESTROY UATA
UR CE lRACKS.

~RIT~

ON A CUSI0M~k

PACK/C~LL

[NT~RPPfJIVE

PROGRAM 10

ftlAT

YOU

AFl~R

INSTRUCtIONS
PROCEtD LIG~r

WH~N

f::I',Tr;F

T~RMl~ATi

AfTER eCN
T(l

CPU

t:NTf"R

~ACH

!~O[)E.L

CC~

AR~

X~Q CCw CO~MA~DS
DiVICE(.:;).

TYP~D,E~TER

tUR~S

i~rRY

EACH COMMAND

ON.

~JTH

AN AL1£FNAIE CODE 5 (lOb).

CHAI~ HAS ~£~~ ~NT~k~DgTYPE
GO.
I~EXr CCiN CHAI'~,PFESS RbOU~,ST,TYPI'.: PES!::!'.

t...:75

D~V=DEV[C~

ENTEp

fUr.; ANY

IN 2841 VOL. A02 OR 2314 YULe 501

ADDR~3S

LIST

XXX=020
~NGLISH

cmd 01 from $a
l)ATA::480cv'

cmd 06 into Sb
DL=4811
corr,pare Sa,Sb

go
NOTE
This sample printout is from a 370/145. The PDP-ll
was running the 2848 Responder. The DXI1-B control
unit address is 20 (Hex), and it is on the multiplexer
channel (Channel 0). The EOB or other terminating
characters are not printed.
Figure 2-19 Sample FRIEND 360/370 Console Printout

2-29

[----- ]

t~;

':.,.:

C",l

:-)

,-- ---l

~-~)

L -----~

::'
;;

------

---~-

,,,--l

'-,

(':
---.-/

:
I

~.~

' ,

.~ !

,~:

:~;

___ -' ~_J

: ;

,-,
:--',

"'!1

()

000000000000000000

GJ
STORAGE
DATA
SWITCHES

STORAGE
SELECT
SWITCH

r
-,-------'1--.-/
1-_ _ _ _---1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- , -_ _ _ _ _ _ _ _-1

[I ~ 1~ 19191919191919/

[Dam

~/
~,I

•

ODD
DOD

~D
I

START, DISPLAY
AND STORE
BUTTONS

Figure 2-20 IBM 360/370 Console

2-30

STORAGE
ADDRESS
SWITCHES

LOAD UNIT
SWITCHES

000
[r;J

00000

L
L,NTERRUPT
BUTTON

~LOAD
BUTTON

Table 2-6
EXAMPLE 2
In this example FRIEND writes 64 bytes of data each equaling 156AC17E (Hexidecimal)
from the 360 buffer designated $a to the DXII-B. FRIEND then reads this data back and
stores it in the 360 buffer designated by $b. Buffer $a and $b are then compared. Any
differences in the two buffers is printed out on the 360/370 console as a compare error.
The data transfer continues until the REQUEST key is pressed on the 360/370 console
device.
NOTE
Program queries are underlined.
DEY = XYY (EOB)
cmd 01 from $a (EOB)
DATA = 64 X 156AC17E (EOB)
cmd 02 into $b (EOB)
DL = 256 (EOB)
compare $a, $b (EOB)
go (EOB)

X = Channel number
YY = Control unit address (in HEX)

2:14.4 Filling Out Test Preparation Card
NOTE
All necessary information required to run the diagnostic
is given in the Preparation Card in Figure 2-22.
Fill out the preparation card in Figure 2-22 being careful to fill in all blanks as follows:
NOTE
Figure 2-21 is a sample of this card.
a.

Fill out the blank spaces on the form in Figure 2-22. The information recorded and the control
characters are used to test the DXII-B on line with the IBM 360/370.

Fill in line 4 with the parameters listed in step lOaf the DME diagnostic test procedure (Paragraph
2.14.8).

Fill in line 6 with the parameters described in steps 11 and 12 of the DME diagnostic test procedure.
The sample preparation card in Figure 2-21 was filled out with information for a 370/158 with
1024K bytes of main storage. The DXll is jumpered for a control unit address of 2FO to 2FF
(Hexidecimal) and is connected to the selector channel (channel 2).

2.14.5 Card Deck Preparation Procedure - Perform the following checks to prepare all card decks for loading
when the FRIEND diagnostic is run.
I.

Check between the decks for blank cards. Blank cards may have been inserted between the decks for
ease in separating them. If so, the blank cards must be removed before placing the decks into the
reader.

Ensure that the first and last card in each deck is marked. If they are not already marked, mark them.
This makes it easier to separate the decks at a later date.

The 2848 diagnostic card decks are usually marked; A, B, C, D, E, and F on the side of the decks. If
they are not marked A to F, the decks can be identified by the IBM diagnostic number which is
punched in columns 73 to 76 of each card.IRefer to Table 2-7.

The cards in each deck must be in order. The number of each card is punched in columns 77 to 80.
2-31

CUSTOMER Sample ---"Y._Il_H_~_~_t:._-_ _

2848 DIAGNOSTIC PREP CARD

DATE

Load and start the 2848 responder (MAINDEC-ll-DZDXC) in the PDP-II.

Load DME monitor into the 360/370.

Make sure 360/370 line printer is on line.

Press "Request" on the 360/370 console (Maintenance Console or Console Terminal). Wait for "Proceed."

Type the system configuration as follows: (Refer to Paragraph 2.14.9).

£.2 .Q...~.J....~ L ......Q.. F L £ r P(EOB)*
(Be sure to type the periods)

Press "Request" on the 360/370 console.

Type the following:
NOTE
If the M908 is jumpered for only one device address,

omit the second line entry.

;.. r
a70,0_
:2
a70,0_

.Q.1B. .!.OOO
F L.1B. Looo

£ -2... (EOB)*

£. ..Q. (EOB)*

(Be sure to type the commas and periods)
7.

Then type: L/b (EOB)

The system configuration will now be printed on the line printer (if online) or on the 360/370 console.

The remaining card decks will now load and the DXll-B will be exercised.
*END if a 370
Figure 2-21

Sample Prep Card

2-32

CUSTOMER

2848 DIAGNOSTIC PREP CARD

DATE

Load and start the 2848 responder (MAINDEC-ll-DZDXC) in the PDP-II.

Load DME monitor into the 360/370.

Make sure 360/370 line printer is on line.

Press "Request" on the '360/370 console (Maintenance Console or Console Terminal). Wait for "Proceed."

Type the system configuration as follows: (Refer to Paragraph 2.14.4).
(EOB)*

(Be sure to type the periods)
5.

Press "Request" on the 360/370 console.

Type the following:
NOTE
If the M908 is jumpered for only one device address,

omit the second line entry.
.1 B.
.lB.

a70,0
a70,0

000
000

(EOB)*
(EOB)*

(Be sure to type the commas and periods)
7.

Then type: L/b (EOB)

The system configuration will now be printed on the line printer (if online) or on the 360/370 console.

The remaining card decks will now load and the DXll-B will be exercised.
*END if a 370
Figure 2-22 Test Preparation Card

2-33

Table 2-7
Diagnostic Card Deck
DEC
Designation

IBM
Designation

Number
of Cards

A
B
C
D
E
F
MONITOR (DME)

7005
7015
7025
7035
7075
7085
0404

137
117
73
69
183
155
586

A typical line printer output from the DME/2848 diagnostic when the 2848 RESPONDER was running in the
PDP-II is shown in Figure 2-23. The parameters for this example are listed on the sample preparation card
(Figure 2-17).
2.14.6 DME/2848 Diagnostic Operation Procedures
The DME/2848 diagnostic consists of the DME diagnostic monitor card deck and six 2848 diagnostic card decks.
The diagnostic runs in conjunction with the 2848 RESPONDER in the PDP-II system.
The diagnostic and monitor card decks are loaded into the 360/370 through its card reader.
NOTE
A minimum of 64K bytes of storage are required in the
360/370. If it has less than 64K bytes, the DME/2848
diagnostic cannot be run and on line testing of the
DXI1-B must be limited to running FRIEND in the
360/370.
2.14.7 Test Preparation ~ Stand alone time is required to run the DME/2848 diagnostic.
Prior to requesting "Stand Alone" time, the FSE should perform each of the preparation procedures listed in
Paragraph 2.14.5 and request that the customer's 360/370 operator assist in loading the DME/2848 diagnostic.
NOTE
Some 360/370 models (Model 128, 158, 168 and some
other systems with CRT console) may use a diHerent
command structure. Check with the customer to determine if the console command structure is standard. If
the command structure is not standard, the DXII-B
cannot be tested as described in this procedure and
Corporate Support must be contacted for assistance.
2.14.8 DME/2848 Diagnostic Operation Procedure
To load and run the DME/2848 diagnostic proceed as follows:
1.

Load and start the 2848 Responder, MAINDEC-DZDXC, in the PDP-II. Refer to the write-up for
details on starting the Program. If the DXII-B Interrupt vector address is not 300, the MAINDEC
must be patched. For patching, refer to the Write-up.
NOTE
If the 370 has a 3270 console, refer to Paragraph 2.14.9

2-34

2-2if
REVISION LEVEL 4
09. 08. OfFfFF
A10. ~2FU. lB. 80000fo
Wl~

D~E

U65.

0~.

A70,

~i2Fl.

lb.

8~);j0;t1f()

L/6

MODEL bS GASr ADR OfFFFf
nil'

EMULAfOR NDNE
1200 8002~39b LDR CAkD
DM10 1204 8309000~ CE OUT
D~10 1208 g~0A001F
CE INp
UT UP
fEAT
CPU ADOR AOUR
D~10

0000~0

~000

00a00~

00
00
00

000000
000000
000000

80
80
80
80

0100
0200
0300
0000

000000

000C

82 00
83 09
83 18

000000
000000
000000

80
80
80

000D
000£
000F

42
i4
44
44
80

ADDR

ADOR

RECCl;,nViE1'~DED :-;WITCH SE11'INGS
CPU AND STORAGE CHECK IN PROGRESS
CHl\~;NF.L

LOG CM,

T ll\'\r~R ON

F7005

1'7015

T
S

F7025

T
F7035

S
T

S
niil75
.SD0
F7075
01
005898
02fl
NO ATTE:NTr~N INTFPT IN 1 ¥tINUTE, SECTION TERMINATED
T

F7'i~85

*SDO

F708S

NO CE MANUAL

00~441

RESPG~SE

02Fl
TO INSTRUCTIONS ON 226J S WITKIN 60

Sf~C01\iDS

Figure 2-23 Typical Line Printer Copy from the DME/2848 Diagnostic

2-35

Table 2-8
System Configuration Definitions
Where:
AA is the 360 model number (30, 40,50,65,67, or 75).
For 370 models use the following numbers for AA

370 Model

135
145
155
158
165
168

40
50
65
65
75
65

BB=OO
CC is as follows for the 360/370 main storage size:
Storage Size (Bytes)

64K
128K
256K
512K
768K
1024K

05
06
07
08
08
09

Model

360/30
360/40
360/50
360/65
360/67
360/75
370/135
370/145
370/155
370/165
370/158
370/168

FA
FA

DD is as follows:

CB
4B
4B
19
19
19
08
08
08
08

EEEEEE is as follows for 360/370 main storage size:
Storage Size (Bytes)

EEEEEE

64K
1281(
256K
512K
768K
1024K

OOFFFF
01FFFF
03FFFF
07FFFF
08FFFF
OFFFFF

2-36

Place the DME monitor deck (largest deck, contains 586 cards) in the 360/370 card reader with the
cards face down and row 9 on the cards positioned toward the card reader. Place the 2848 diagnostic
decks (A, B, C, D, E, and F) on top of the DME monitor deck in a similar manner.
NOTE
All 360 console inputs are terminated by (EOB), which
is obtained by simultaneously pressing ALTmode and
5 on the 360 console. On 370s, press END on the
console. This applies to every line entered.

Press START and the End of File (EOF) on the card reader.

Wait for the READY indicator on the card reader to illuminate.

If a line printer is available, ensure that it is on-line. All printouts occur on this printer. If no printer
is on-line, or if that line printer has a non-standard address, all printouts occur on the console.

Set the 360/370 load unit switches to the card reader address, (usually OOC), (refer to Figure 2-20).

Press the blue LOAD button on the 360/370.

The monitor card deck only loads at this time and WTE DME is printed on the line printer.
NOTE
If the prep card has already been filled out omit
steps 9 through i 3 of this section. Use steps 4
through 9 of the Prep Card to replace the cited
steps of Section 2.14.8.

Press the REQUEST button on the console and wait for the PROCEED light.

10.

Type the system configuration as follows:
uAA.BB.CC.DD.EEEEEE (EOB)
(Refer to Table 2-8 for definitions of A, B, C, D, and E)
NOTE
For short procedure follow Prep Card Figure 2-22.

II.

Press REQUEST on the console and wait for the PROCEED light. Then type the following:
NOTE
If the M908 is jumpered for only one device address,
do not type the second line.
a70,OCDD.I B.XOOODD (EOB)
where:
C

= The Channel number to which the DXII-B is connected.

DD = The low order DXII-B control unit address (in Hexidecimal). Equivalent to the address
placed in the PDP-II switch register. When the 2848 Responder was started.
EE = DD+l

x = 8 -If the DXII-B is on a selector channel.
o - If the DXII-B is on a multiplexer channel.
2-37

12.

Press REQUEST on the console and wait for the PROCEED light. Then type:
a70,OCEE.IB.XOOODD (EOB) (Refer to step 11 for definitions of C, D, E, and X).

13.

Now type the following:
L/B (EOB)

14.

The system configuration is printed on the line printer (or console if no line printer is available).
This printout can be ignored.

15.

Now the remaining 6 card decks wi1lload, one every few minutes. After each card deck is loaded, the
PDP-II system is exercised. The line printer prints the following as each deck is loaded and executed
without error:
a.

S F70XX
T

where:
XX = The test number (05,15,25,35,75, and 85).
b.

Tests F7075 and F7085 prints the following allowable errors:
S
F7075
*SDO F7075 CI 005R9R 02FI
No attention INTRPT in 1 minute, Section terminated.

T
S
F7085
*SDO F7085; 0 I 00544402FI
No CE Manual Response to Instructions on 2260 S within 60 seconds.
c.
16.

These are the only errors allowed. All other errors are printed in a similar manner to that above.

The 2848 diagnostic terminates with the following printout:
WTEDME

17.

Two passes are sufficient for DXII-B on-line acceptance.

2.14.9 FRIEND or DME/2848 Diagnostic Operating Procedure for 3270 Console
The IBM 3270 CRT Display console is frequently used in place of the hard copy printer keyboard combination
found on all IBM 360s, and some 370's CPUs.
By using the Light Pen (LP) attached to the console and the keyboard (KB) this system can easily be configured
to communicate with the operator in order to run the FRIEND and DME/2848 diagnostics.
NOTE
The system must be dedicated to the DXll-B at this
time. Be sure the customer has completed his operations on the IBM system and that all disks and other
storage devices are protected by being turned OFF LINE.

2-38

Face the 3270 Display Console and perform the following steps.
1.

Unlock the security key on the right side of the 3270 display housing. (This key switch mayor may
not already be in the unlocked position.)

Press the STOP button on the front of the processor.

Press the Initial Micro Program Load (lMPL) button on the same processor console. This causes the
control storage of the processor to be reloaded from floppy disk units contained within the 370
console. It takes approximately one to two minutes, during this period the floppies will be in motion
and make unusual sounds, the 3270 display shows arbitrary patterns. At the completion of the IMPL,
the 3270 display posts the IMPL COMPLETE message. If the IMPL error light is displayed on the
processor panel repeat this step.
The next display posted by the 3270 console is the first frame modified by the operator or installer.
This is displayed automatically.
These frames are modified by using the light pen (LP) and console keyboard (KB). The LP is used by
placing the tip of the LP on the square block to the immediate left of the desired selection and
pushing it forward on the screen until the snap action switch within the LP is actuated, be sure that
the LP is placed squarely on the screen over the desired block.

This frame gives information that relates to the 370 system configuration. This includes CPU
features, number and types of channels, assignments and types of UCWs. Included with this in the
lower corner of the displayed frame is the KEYBOARD PRINTER mode selection.
Place the LP over the KEYBOARD printer mode select square and activate the LP.

Next:on this same displayed frame select with the LP the sqaure that corresponds to the MANUAL
mode selection. Subsequent to this selection, a second frame is displayed on the 3270 display. This
occurs automatically after selecting the MANUAL mode.
This second frame displays information used in loading during Initial Program Load (IPL) time, such
as the address of the device information is to be loaded from. It also contains the necessary selections
to execute either a System Reset or PSW RESTART and to load the information from the specified
device.

Using the LP, select the LOAD UNIT square, now on the KB specify the address of the device which
the FRIEND or DME/2848 diagnostic will be loaded (IPL'd) from. This is usually the card reader
and is a three character entry such as OOC where the most significant character represents the IBM
channel and the remaining two characters represent the control unit and device address.
After entering the three characters terminate the entry by depressing the ENTER key on the KB.
Note the address of each IBM device is most often attached to that device with a three character
emblem that is quite visible.

Place all the cards in the card reader selected as the load device and make the card reader ready to
read by pushing the START and END OF FILE buttons, one card should be read and then the
green READY light should come on.
NOTE
Place Card Reader END plate on top of last card. This
is used to weight cards down. Be sure all cards are placed
in the reader NINE edge in and face down.

2-39

With the LP, .select the square for a SYSTEM RESET. Next at the bottom of the displayed frame use
the LP to select the EXECUTE square, this executes the System Reset.
With the LP, select the square for the LOAD function. Next using the LP, select the EXECUTE
square. At this point the cards should be read by the reader. At times the reader may halt before the
full card deck has been read in (refer to step 10).

Assuming that the full card deck has been read successfully, either the FRIEND or DME/2848
diagnostics displays information on the screen. At this point refer to the operational description of
the particular program contained within this manual.
If the card deck has been completely read but a message is not displayed on the 3270 screen, depress
upper case A on KB followed by the ENTER key. If the 3270 screen is still blank, refer to step 10.

10.

This step is performed if the IPL or program load was not successful.

lOA. If the reader halts before the full deck has been read, repeat steps 7 and 8. Ifthe reader halts more
than 3 times, go to lOB.
lOB. Clear the card reader of any remaining cards, do this by manually clearing any cards in the output
hopper. Next remove any cards in the input hopper and press the NPRO button on the reader, this
flushes any cards left in the reader.
Reassemble the card deck keeping all cards in order. Check the card sequence numbers in the last
four columns of the card to be sure that all cards are in sequence.
lOCo Reload the cards according to step 7. Before placing the cards in the reader, fan the edges of the
cards with your finger to loosen any cards that might be sticking.
IOD. On the left hand side of the 3270 keyboard, press the MODE key. This causes the second frame to be
redisplayed. When this frame is redisplayed, return to step 7. If the screen remains blank, return to
step 1.
NOTE
After the cards are read in, go to step 15 in Paragraph
2.14.3 or 2.14.6 for remainder of the operating
instructions.
2.15 OPERATING SUGGESTIONS
This section contains some helpful hints for running the on-line diagnostic test.
2.15.1 On-Line Operation Requirements
Do not attempt on-line operation unless all four of the DXII-B off-line diagnostics (DXDXA, DZDXF, DZDXG,
and DZDXH) have successfully run. System exercisers should also run (CTP, GTP, DEC/XII).
NOTE
Ensure all diagnostics are the latest revision.

2-40

2.15.2 Errors with DME/2848 Diagnostic
1.

If errors occur, run FRIEND with CTP. Attempt to create the same error by specifying the same data
pattern and device address (on the channel) that failed with the 2848 diagnostic. This information
should be available from the error printout on the 360/370 line printer.

If you cannot reproduce the failure try running FRIEND and the 2848 responder.

Most errors are easier to diagnose and check with the oscilloscope using FRIEND and CTP.

2.15.3 Format Consideration and Logic Levels
IBM BIT 00 to bit 07 are opposite from DEC BIT 00 to 07 (DEC bit 00 = IBM Bit 07, etc.) All channel signals
are: +3 V = 1 (true), a V= Q(false). All channel signals are available for checking with the oscilloscope on Rows
Hand J of the DXII-B. However, this should not be attempted when the 360 is running the customer's
software.
2.16 ERRORS THAT OCCUR WHEN FRIEND IS RUN
1.

None of the PDP-II programs check any data when the DXII-B is on line. All data checking is done
in the 360/370 by using the COMPARE command. If CTP halts, the cause is most likely a Unibus
problem. If the 2848 RESPONDER halts, ensure you patched the program for the corrent vector
address (see Paragraph 2.4.2). If the DXII-B does not interrupt to 300 (load the contents of 300
and 302 into the DXII-B interrupt vector address and that address plus 2). This procedure is listed
in MAINDEC-II-DZDXC-A-D. The 2848 Responder may also halt if the ON LINE ENABLE is in the
OFF position or ON LINE cannot be set.

If you are using FRIEND to drive the 2848 Responder, ensure character data is specified correctly.
If you typed in a lower case character, (a, b, e, f, etc.) an upper case character (A, B, E, F, etc.) is
read by the channel. TIlis causes a data compare error so always specify an upper case character.
This is a software function of 2848 Responder.

Unit = XXX Data compare error byte No. 0001 $a = FF $b = 00. This example of a data compare
error contains the following information. Unit = XXXX is the failing address on the channel. This
should be the device address you specified to FRIEND.
Byte No. 000 1 is the failing data byte number. If this is greater than 000 1, the error is intermittent.
FF is the contents of the write buffer (good data). 00 is the contents of the read buffer (bad data).

Unit = XXXX - No DEV END or CUE I/O Interrupt. This error means the DXII-B never caused
an interrupt to present device end or control unit end to the channel. The DXII-B may be hung
or the PDP-II may be halted.

Unit = XXXX Start I/O not accepted.

csw = 00 000000 XX yy 0000
This error means the DXII-B did not respond to initial Hand Shaking on the channel.
XX = Control Unit status.
YY = Channel status - if non-zero indicates a possible channel error.

2-41

If XX == 02 (Unit Check) sure the control unit address specified to FRIEND (DEV == ..... ) was the
address (minus the channel number) placed in the PDP-II switch register; plus up to 3 for CTP and
DEC/XII; or plus I for the 2848 Responder. This address is a hexidecimal number.

Anytime the 360/370 Data transfer or error printout is stopped with REQUEST or INTERRUPT on
the 360/370 console if the DXII-B should stop in and remain in Phase O.
2.17 MAINTENANCE PROCEDURES
Maintenance (P.M.'s etc.) can be performed while the DXII-B is connected to the channel, however, care must
be used. Even though the DXII-B is off line or even powered down, it is possible to crash or hang the customer's
360/370 operating system.
Do not remove any of the following unless the DXIl-B is disconnected from the channel or the 360/370 is
halted or the 360/370 is dedicated stand alone to the DX1I-B;
G890 (slot FOl)
Any M596 or M597
Coax Cable connector cards (to and from the channel)
All other modules can be removed provided the DXII-B is powered down.
2.18 HINTS ON INTERFACE SIGNAL MONITORING WHILE TROUBLESHOOTING
In order to monitor the interface signals you must understand the nature of the two buses and their associated
tag lines (Figure 2-24). BUS OUT consists of 9 lines that carry addresses, commands, control orders, and data
from the IBM 360/370 system to the DXII-B system. The 4 outbound tag lines are asserted to indicate to the
DXII-B system what information is being transmitted. BUS IN consists of 9 lines that carry addresses, status,
sense information and data from the DXll-B system to the IBM 360/370 System. The inbound tag lines are
asserted to indicate what information is being transmitted from the DXII-B to the IBM 360/370 system.
In order to determine what signal(s) should be present on a line of the bus you must determine what informatio'n
is being transmitted and which lines should be asserted for that particular information.
When information consisting of less than 8 bits of information is transmitted on the bus (Figure 2-25) the bits
must be placed in the highest numbered bit position on the bus. The unused bit positions must be held to a logical
zero. As an example: if 6 bits of information are transmitted, bit position 0 and 1 are held to a logical zero,
the MSB is bit position 2 and the least significant bit is bit position 7. For a more detailed description of the
buses, refer to the IBM System/360 and IBM System/370 I/O Interface Channel to Control Unit Original
Equipment Manufacturers Information Manual.

2-42

IBM 360/370

DXll-B
SYSTEM
SCAN a SELECT
IIO DEVICE

vI'\.

SYSTEM
II.

)

SELECTION CONTROLS

...

....
II.

"'-

BUS IN
(9 LINES)

IDENTIFIES
INFORMATION
ON BUS

V
I'\.

ADDRESS
STATUS
SENSE
INFORMATION DATA

~ IDENTIFIES
INFORMATION
/.. ON BUS

INBOUND TAG LINES
(5 LINES)

DATA
ADDRESS
COMMANDS
CONTROL ORDERS

USED TO
SCAN AND
SELECT
IIO DEVICE

BUSOUT
(9 LINES)

....

.,-

"-"

OUTBOUND TAG LINES
(4 LINES)

11-3461

Figure 2-24 Input/Output Signals

MSB

LSB

FORMAT FOR 8 BITS OF INFORMATION

5
~MSB
NOT*
USED

7
LSB

FORMAT FOR 6 BITS OF INFORMATION
NOTE
Unused lines are held to a logical zero.

11-3460

Figure 2-25 Formats for Transmission of Information on the Buses

2-43

CHAPTER 3
OPERATION

3.1 SCOPE
This chapter provides the information necessary to operate the DXII-B. The description is divided into two
major parts: Controls and Indicators, and Special Operating Procedures.
3.2 CONTROLS AND INDICATORS
Figure 3-1 shows the DXll-B control and indicator panels. The indicator panel is located at the top front of the
unit. The control panel (EPO) is located in the center front of the unit behind a removable panel. The figure ic
keyed, by index number, to the functional descriptions given in Table 3-1.

Table 3-1
DXI1-B Controls and Indicators
Index
No.
DXDS

Name

Function

Device-Status-Register - Sixteen lamps which indicate the contents
of the DXII-B Device Status Register as follows:

PARER

Parity-Error - Indicates an even parity condition on Bus-Out,
when either a command or data information is sent from CH
to CU (DXII-B). (Error indicator.)

NXM(PDPTO)

Non-existent-Memory - Indicates more than 20 /1S were required
to complete a single NPR. (Error indicator.)

SELRST

Selective-Reset - Indicates a malfunctioning DXII-B device.
(IBM Reset indicator.)

SYSRST

System-Reset - Indicates the execution of a System Reset
sequence. (IBM Reset indicator.)

INFDSC

Interface-Disconnect - Indicates that the channel has performed
a disconnect operation with the DXII-B. (IBM Reset indicator.)

UCHKS

Unit-Cheek-Sent - Indicates that Unit Check has been presented
in the status byte. (Channel Status flag.)
(continued on Page 3-3)

3-1

7
6257-3

Figure 3-1 DXI1-B Controls and Indicators

Table 3-1 (Cont)
DXII-B Controls and Indicators
Index
No.

Name
CHENDS

Channel-End-Sent - Indicates to the emulator that Channel End
status was sent in a status response. (Channel Status flag.)

BSYS

Busy-Sent - Indicates that Busy status was sent to the channel.
(Channel Status flag.)

CHIS

Channel-Initiated-Selection-8equence - Indicates a channelinitiated sequence is in progress with the DXII-B.

ESEND

Ending-Sequence-End - Indicates a status byte was presented
to the channel as a result of either a program-initiated sequence
or a stacked status having been accepted. Can indicate a
CUI-ISS contention. (CUI End indicator.)

CHDEND

Channel-Data-End - Indicates a channel byte count overflow
during a Data Transfer sequence. (CUI End indicator.)

CUDEND

Control-Unit-Data-End - Indicates an all zero state in the DXBC
Register during a Data Transfer sequence. (CUI End indicator.)

ISSREJ

ISS-Rejected - Indicates a channel-initiated selection sequence
addressed to the DXII-B was answered by a CU Busy status indication and a short CU Busy sequence. (Special indicator.)

CMDCHN

Command-Chaining - Indicates that another CCW operation will
probably follow for the CU/Device currently connected when
Device End is presented. (Special indicator.)

STKSTB

Stack-Status-Byte - Indicates that the status byte being presented
on the Bus-In cannot currently be accepted by the channel.
(Special indicator.)

CMDREJ

Command Reject - Indicates the command sent to the DXII-B
was illegal. Unit check is presented in the status byte. The rejected command is indicated in the CUCR. (Special indicator.)

(cont)

Function

Control Unit Address Register - Eight lamps which indicate the contents of the CUAR constituting the right-hand byte of the DXCA
(Command and Address Register). Contains the device address from
Bus-Out during an ISS.
CUS~06

Control Unit Status Register - Eight lamps which indicate the contents of the CUSR constituting the right-hand byte of the DXOS
(Offset and Status Register). These status bits, transmitted to the
channel are as follows:
DXll-B

ATTN
CUEND
BSY
CHEND
DEVEND
UCHECK
UXCEP

STAMOD

Attention
Control Unit End
Busy
Channel End
Device End
Unit Check
Unit Exception
Status Mode

Bit Assignments
Channel (CH)

7
5
4
3
2

0
2
3
4
5

6
6

(continued on next page)
3-3

Table 3-1 (Cont)
DXII-B Controls and Indicators
Index
No.
4

Maintenance Out Register - Sixteen lamps which indicate the contents of the Maintenance Out Register. This register comprises two
subregisters, the left-hand byte constituting the CONO or Control
Lines Out Register, and the right-hand byte, the BUSO or Data
Lines or IBM Bus-Out Register. These bits are as follows:
OPLO

Operational-Out - Indicates that the channel is in operation
(Selection Control Line)

HLDO

Hold-Out (Selection Control Line)

SELO

Select-Out (Selection Coritrol Line)

SUPO

Suppress-Out (Selection Control Line)

ADRO

Address-Out (Tag Line)

CMDO

Command-Out (Tag Line)

SRVO

Service-Out (Tag Line)

PARa

Parity-Out (Parity Line)

REC'D BUS OUT
LINES (BUSO)

Indicate the Bus-Out data bits as seen either directly from the
Bus-Out cables or from BUSOB if off-line.

DXMI_16

OPLI
SELl
REQI
ADRI
STAI
SRVI
CLKO
PARI
BUSI
6

Function

Name

DXCB

Maintenance In Register - Sixteen lamps which indicate the contents of the Maintenance In Register. This register comprises two
subregisters, the left-hand byte constituting the CONI or Control
Lines In Register, and the right-hand byte the BUSI or Data Lines
or IBM Bus-In Register. These bits are as follows:
Operational-In (Selection Control Line)
Select-In (Selection Control Line)
Request-In (Selection Control Line)
Address-In (Tag Line)
Status-In (Tag Line)
Service-In (Tag Line)
Clock-Out (from Bus-Out)
Bus Parity In
Indicates the data bits enabled to the Bus-In lines for transmission
back to the IBM 360 Channel.

Control Bits Register ~ Sixteen lamps which indicate the contents
of the Control Bits Register as follows:

LOCKa

Lockout - Indicates that the first five programmable registers are
made read-only to the PDP-II program.

PHASE 2,1,0

Indicate the existing major phase of the DXll-B.

TSFF

Time State Flip-Flop - Indicates the state of the clock control
(time state) flip-flop.
1= TSI
Q=TS2

(continued on next page)
3-4

Table 3-1 (Coni)
DXII-B Control§ and Indicatofs
Index
No.
6
(cant)

Name

Function

FASTCV

Fast Control Unit Response - This signal is made available fOf
diagnostic test purposes.

SYNC

Synchronization Flip-Flop - This is a phase synchronizing flipflop used to disable certain portions of logic within any particular
phase.

CUDX

Control Unit Data Control - Indicates that the Control Unit
data (CVCR and CVSR) is available to either the bus-out or
bus-in lines.

IOD

I/O-Done - Indicates an Input-Output Done condition.

BYPAS

Bypass - Indicates one of the following:
a.

This is the first byte of data that is being transmitted or
received.

The device status table will not be accessed by this
particular channel-initiated sequence.

No address-out has been received.

A copy of the parity okay signal (between Phases 2 and
3).

A copy of status pending (between TS I and TS2 of
Phase 0 during a CHI sequence).

In TS2, indicates that a fast CU Busy was made in TS 1.

NPRX

NPR Control Switch - Indicates that the DXII-B is requesting
a non-processor or memory-to-device transfer from the PDP-Il.
When extinguished, indicates that the transfer has been completed.

NPRT

NPR Transfer Direction - Indicates that data is being sent into
PDP-II core. If extinguished, indicates that data is being taken
from PDP-II core.

BALF

Byte Alternator Load Flop - Indicates that status is pending
and that the device for which status is pending has been addressed
by the channel. During Phases 5 and 6, it keeps track of which
half of the data word is currently being used.

ONLINB

On line B - Indicates whether or not the DXII-B is connected to
the I/O interface.

ADRECC

Control Unit Address Compare - Indicates that the control unit
portion of the address matches Bus-Out.

ADRECD

Device Address Compare - Indicates that the device portion of
address matches Bus-Out.
(continued on next page)

3-5

Table 3-1 (Cont)
DXll-B Controls and Indicators
Index
No.

Name

Function

NPR Data Register - Sixteen lamps that indicate each data word
that is transmitted to or from PDP-II core via NPRs.

DXND

PAROK

Parity OK - Indicates odd parity on the channel and device address
from the channel to the DXII-B.

DXTO

DXll-B Timeout - Indicates that while Operational-In was up, the
program did not interact for 5 sec. (Program Response Latency
error.)

MNCLEN

Maintenance Clock Enable - (MCLKEN) Indicates that the DXII-B
is enabled for maintenance clock mode. When set, the DXII-B will
not change time state until Maintenance Clock pulse is set. This
flip-flop is pulsed by the SINGLE PULSE switch on the EPO panel.
An on and an off condition of the MNCLEN indicator will result in
the DXII-B switching from one time state to the other.

TIMDIS

Timeout Disable - Indicates disabling of DXTO during program
debugging.

NPRTO

NPR Timeout - Indicates that DXII Bus Master was not asserted
during timeout interval. (NPR Latency error.)

ODD

ODD Flip-Flop - Copy of DXBA (00). Always zero when presented
to Unibus (or read by program). This data (odd buffered address)
is saved here to initialize BALF.

14
IS

Two undesignated lamps that can be jumpered to any signal for
observation.
DXBA

NPR Bus Address Register - Fifteen lamps that indicate the following:

NOTE
00 is always (0). See Item 13.

During data transfers, points to PDP-II core location to
or from which data will be transferred.

During CHIS, points to the SPW and device status byte in
PDP-II core.

When information is to be stored in the Tumble Table
(TT), indicates that address.

DXCS_ 04

Control Unit Status Register - Fifteen lamps that indicate the contents of the Control Unit Status Register as follows:

PARSTP

Parity E"or Stop - Indicates that a data transfer sequence will
be terminated upon a Bus-Out Parity error. If out, will not prevent a parity error from being raised, but the sequence will end
normally.

(continued on next page)

3-6

Table 3-1 (Cont)
DXll-B Controls and Indicators
Index
No.
16

Name

Function

CUFBM

Control-Unit-Forced-Burst-Mode - Indicates that Forced Burst
mode has been enabled. (Program set.)

ENDEN

Control Unit End Enable - Indicates that the CUEND will be
asserted in the device status presented to the channel during a
CU Busy sequence. (Program set.)

BSYEN

Control Unit Busy Enable - Indicates that CUBSY can be immediately set upon responding to a CUI or CHI. (Program set to
emulate a single thread control unit.)

ONLINA

On line A - Indicates that the DXII-B has made or is making a
request to go on-line to the 360 channel. (Program set.)

CUBSY

Control Unit Busy - Indicates that a channel-initiated sequence
will be answered by a control unit sequence. (Program and hardware set.)

DONE

If INTEN is also set, indicates that an interrupt will be requested.
Program cleared only before making an attempt to change
registers.

(cant)

In Phases 0 or 7, if reset, LOCKO can also be reset.
In Phase 4, TS 1 is cleared to reset Interrupt Request. In Phase 4,
TS2 is set with NPRX.
NOTE
A program set of DONE should only be attempted
by a maintenance program as an isolation test of
the DXll-B interrupt.
INTEN

Interrupt Enable - Indicates an interrupt enable condition. The
bit is always writable. Should always be on before activating the
on-line flip-flop. Should not extinguish until the on-line flip-flop
has been cleared. (Program set and cleared only.)

STKSTA

Stack-Status - If set, indicates that status was stacked. If cleared,
indicates that status was accepted. Program set when presenting
a suppressable status. Automatically set when the CH requires a
status to be stacked and the DXII-B will attempt to present it
again.

XBA17
XBA16

Extended Bus Address - Two lamps that indicate the extended
most significant bits of the Memory Address Register during data
input/output. Program loaded and cleared. During NPR cycles,
complements on a DXBA overflow when the DXBA is incremented
+2, during a data transfer.
(continued on next page)

3-7

Table 3-1 (Cont)
DXI1-B Controis and Indicators
Index
No.
16
(cont)

Function

Name

FCTN2
FCTN 1

Function - Two lamps that indicate the binary contents of the
DX11-B Function Register, which represent the operation desired
as follows:
FCTN=O = Reset the DXII-B
FCTN=1 = Input data transfer
FCTN=2 = Output data transfer
FCTN=3 = Present status
Indicates that the function requested is performed. If FCTN=O,
DONE is left cleared; if FCTN*O, REQI is raised.

GO
17

CUCR

SINGLE PULSE

Momentary toggle switch. Each operation will complement
MNCLKF. Two operations will step the DXII-B from one time
state to the other.

SYSTEM/LOCAL

Two-position toggle switch. In SYSTEM position, puts the DXII-B
under control of 360/370 power up sequencing.

Control Unit Command Register - Eight lamps indicate the contents
of the CUCR constituting the left-hand byte of the DXCA (Command and Address Register). Contains the last command sent by the
channel even if it was rejected by the DXII-B.

In LOCAL position, removes the DXII-B from control of 360
power sequencing.
20

POWER HOLD

One lamp that indicates completion of the 360/370 power up
sequence.

ENABLE
ON LINE
OFF LINE

Two position toggle switch. In ON LINE position enables the
DXII-B to be put on-line by the program, and in OFF LINE
position enables the DXII-B to go off-line in accordance with
. 360/370 protocol.

ON LINE ENABLED

One lamp that indicates when the DXII-B is enabled on-line.

3-8

3.3 861 CONTROLS AND INDICATORS
Figure 3-2 shows the front panels for the 861-A, 861-13 and 861-C Power Controllers. Each version has two pilot
lamps, a circuit breaker, a 3-position toggle switch, and several power outlets. Their functions are discussed in the
following paragraphs.
3.3.1 Pilot Lamps
In all 861 Power Controller versions, all pilot lamps are lighted whenever the controller input power cable is
connected to the live mains, regardless of the position of the power controller circuit breaker or LOCAL/OFF /
REMOTE switch.
3.3.2 Circuit Breaker
Circuit breaker CHI, when ON, provides power to the unswitched outlets, and to the switched outlets when the
LOCAL/OFF/REMOTE switch is in the LOCA.L position (or in the REMOTE position and a connection exists
between pins 1 and 3 of a Remote Switching Control Bus connector*). The circuit breaker opens automatically
when an overload condition exists at a power outlet or within the power controller.
3.3.3 LOCAL/OFF/REMOTE Switch
The LOCAL/OFF/REMOTE switch provides the Remote Switching Bus with the means to control the power
to the switched outlets. When the power controller is energized and the switch is in the OFF position, the
switched outlets are disabled. When in the REMOTE position and connected to a bus where Power Request and
Emergency Shutdown are in use (or a means of effecting connection between pin 3 and pins I or 2 exists), the
switched outlets are enabled or disabled in accordance with conditions on the bus. When in the LOCAL position,
the switched outlets are enabled only when the Emergency Shutdown signal is not asserted.
3.3.4 Remote Switching Control Bus Connectors
The three female Signal Bus connectors, adjacent to the LOCAL/OFF/REMOTE switch, are wired in parallel.
These connectors provide a means of daisy-chaining the Remote Switching Control Bus between the controller
and system devices.

* A connection between pins 2 and 3 of the Remote Switching Control Bus disables the switched outlets, regardless of the position of the
LOCAL/OFF/REMOTE switch.

3-9

REMOTE

OFF

LOCAL

UNSW1TCHEO

(~;) ('~:) ~
J

@~
CP-0374

REMOTE

OFF

LOCAL

UNSWITCHED

(dfJ
(dfJ,
®

CP-0375

SWITCHED
CIRCUIT
ONE

REMOTE
ON

CIRCUIT
ON

OFF

LOCAL
ON

o~o
EEl

EEl
CP-0376

Figure 3-2 Type 861-A,-B,-C Power Controller Panels

3-10

CHAPTER 4
PROGRAMMING

4.1 SCOPE
This chapter presents general programming information for software control of the DXll-B. Although a few
typical program examples are included, it is beyond the scope of this manual to provide detailed programming
information.
This chapter is divided into four major portions:
a.
b.
c.
d.

360/370 and PDP-II Format Comparison
360/370jDXll-B Communication
DXlI-B/PDP-l1 Communication
DXl1-B Formats

4.2 IBM 360/370 AND PDP-II FORMAT COMPARISON
As the DXII-B transfers data between 360/370 and PDP-II memories, a comparison of their word formats is
called for (Figure 4-1).

Io
o

BYTE

,- - -

- -

- - -

- - - -

- -

- - -

HALF:WORD

1516

WO:RD

1516

2324

3132

2324

IBM
360/370

DOUBL~ WORD

3940

4748

5556

I
15

BYTE

: ' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - } PDP-II

I:===~~====~I
WO:RD

______ ------------------------------

Figure 4-1 IBM 360/370/PDP-ll Data Format Comparison

4-1

11-1237

In the IBM 360/370, information is handled in units of eight bits (byte). A ninth bit (parity) is generated for
each byte and carries odd parity on the byte but is not included in references to size of data fields. Bits are
numbered from left to right (00-07). A halfword comprises two consecutive bytes (00-15) while a word is four
bytes (00-31). The location of any group of bytes is specified by the address of the left-most byte. Partitioning
is based on a hexadecimal notation in which each byte represents two hexadecimal digits in 4-bit binary form
(0000=0, 1111=F).
PDP-II information is also handled in 8-bit bytes, but parity is not generated. Bits are numbered from right to
left (IS: 00>, with a word comprising two consecutive bytes. The right-most byte (07: 00) is designated the low
byte and is addressed in even locations. The left-most byte <15:08) is designated the high byte and is addressed in
odd locations. Partitioning is based on an octal notation in which three binary bits represent one octal digit
(000=0, 111 =7). In the PDP-II, the basic unit of data is the byte; the only smaller unit recognized by the hardware is the individual bit.
4.3 IBM 360/370/DXl1-B COMMUNICATION
The DXII-B functions as a control unit (CU) in the IBM 360/370 System and is in communication with a channel
unit in that system. All transactions between the DXII-B and the channel (CH) are conducted over an I/O interface. The DXII-B accepts control signals from the channel, controls the timing of data transfers over the I/O
interface, and provides status of the devices it controls. The interface provides the DXII-B with an information
format and a sequence of signals that is common to all control units on that channel. The DXII-B decodes commands from the channel, interprets them for a particular device on the Unibus, and generates a signal sequence
necessary to execute a given operation. The channel directs the flow of information between the I/O devices
and 360/370 memory.
Communication between the channel and the DXIl-B is on an interlocking basis, in which each signal requires a
response for the sequence to proceed. The I/O interface contains two buses (Bus-In and Bus-Out), Mark and Tag
lines, and Selection and Metering Control lines.
Bus-Out is used to transmit information from the channel to the DXII-B such as data, device addresses, commands, and control orders. Bus-In transmits information in the opposite direction (data, selected I/O device
identification, status and sense data). Mark indicates the bus being used. Tag lines are used to identify what
kind of information is placed on the bus at anyone time. The selection control lines serve a scanning or selection
function of attached I/O devices, while the metering lines condition usage meters on the attached units.
4.4 DXlI-B/PDP-l1 COMMUNICATION
The DXlI-B functions as one of the devices on the PDP-II Unibus, and is in communication with the PDP-II
Central Processor over that bus. The Unibus is similar to the 360/370 I/O Interface except that all devices,
memory, and the processor are connected to the same logical set of wires. Whereas on the IBM interface the
channel controls all transactions, on the Unibus any device, or the processor, can control the transfer of information.
The DXII-B communicates with the PDP-II processor in three ways. The most important way is via NonProcessor Request (NPR) cycles for direct access to the core memory. The DX II-B uses this to retrieve device
status, store sequence results, and to transfer data.
A second way is via the interrupt which causes a temporary change in the PDP-II program. The interrupt is used
to notify the program that sequence information is now available.

4-2

The third type of interaction is program changes to the DXII-B control registers. In this case, the PDP-II
processor becomes Unibus "master" and the DXII-B becomes the "slave" device.
In the IBM System, the channel is always in charge of signal sequences, as data is spoken of as from or to the
channel. On the Unibus side of the DXII-B, devices can be either "master" or "slave", depending on whether or
not they have initiated an operation. Direction of data transfer in the PDP-II System is described relative to that
device that has momentarily become "master". To avoid confusion, in this manual "360 read" and "360 write"
are used to describe the direction of data transfer with respect to the IBM System. The terms "output" and
"input" are used to describe direction of data transfer with respect to the PDP-II System. It can be seen from
this that a transfer from 360 to PDP-II will be a "write" transfer to the DXII-B and an "input" transfer to the
PDP-II (Figure 4-2).

OUTPUT

READ
BUSIN

PDP

IBM
BUSOUT
INPUT

WRITE

11-1238

Figure 4-2 360jPDP-ll Transfer Conventions

On the Unibus, only a single sequence is involved in establishing a logical connection; but in the IBM System, data
(status information and commands) must be exchanged while maintaining a sequence. Neither method uses a
synchronizing clock and both have overall time limitations.
4.5 DXII-B FORMATS
This paragraph lists all of the DXII-B Unibus programmable registers in tabular form (refer to Drawing
C-FD-DXII-P-04, Sheet 7 of 8). All bits can be read by the program; all registers are byte addressable. Table 4-1
lists just the registers with their byte numbers (Base Address Offset), mnemonics, word number, full register
name, and pertinent information about each. Tables 4-2 through 4-9 break each register down bit by bit, giving a
detailed description of each bit's function.
Table 4-1
DXII-B Registers
(Addressable as PDP-II Memory)
Base
Address
Offset

Mnemonic

1,0
3,2
5,4
7,6
11,10
13,12
15,14

DXDS
DXCA
DXCS
DXOS
DXBA
DXBC
DXMO

Word
No.

Remarks

1
2
3
4
5
6
7

Device Status (TT entry no. 1) (Read-only)
Command and Address (IT entry no. 2) (Write lockout)
Control Unit Status (loaded by ISR) (Write lockout)
Offset and Status (loaded by ISR) (Write lockout)
Bus Address (loaded by ISR) (Write lockout)
Byte Count (loaded by ISR)
Maint Out (simulator) (diagnostic)
(continued on next page)

4-3

Table 4-1 (Cont)
DXll-B Registers
(Addressable as PDP-II Memory)
Base
Address
Offset

Mnemonic

17,16
21,20
23,22
25,24
27,26
31,30

DXMI
DXCB
DXND
DXESI
DXMOB
DXES2

Word
No.

Remarks

Maint In (simulator) (diagnostic)
Control Bits (control) (diagnostic)
NPR Data (control) (diagnostic)
Extra Signals (control) (diagnostic)
Buffered Bus Out (simulator) (diagnostic)
Extra Signals (control)

9
10
11
12
13

4.5.1 Device Status Register (DXDS)
The DXDS register contains all the interrupt and device status flags. The DXDS register is read only and stored
as the first tumble table (TT) entry for this device before reset. These bits and their functions are listed in Table 4-2
and shown in Figure 4-3.
15

PARER

DXDS REGISTER
7
e

NXM ISELRSTI SYSRST INFDSCI UCHKS ICHENDS eSYS I CHIS I ESEND CHDENDICUDENDIISSREJ CMDCHNISTKSTBICMDREJ

,
ERRORS

IEIM
RESET

STATUS
FLAGS

• CJI
END

CUI
END

ALL
BITS
READ
ONLY

SPECIAL
CONDITIONS

READ ONLY
11-1239

Figure 4-3 Device Status Register (DXDS) Bit Assignments

Table 4-2
DXDS Bit Assignments
Bit No.

Description

Mnemonic

Error Indi~ators
15

PARER

Parity Error - This bit is set if the DX (also referred to as CU) detects an
even-parity condition on the Bus-Out when either a command or data
information is sent by the channel (CR) to the CU. The PARER flip-flop
will be set if bad Command-Out parity is detected during an ISS or if bad
(BUSO) Data-Out parity is detected. The PARER flip-flop is not set on
bad Address-Out parity during an ISS. In this case, the CU simply will not
recognize the address from the CR. If set during a data transfer while
PARSTP is set, this will terminate the sequence by IOD=1 and CUDEND
will also be set.
(continued on next page)

4-4

Table 4-2 (Coni)
DXDS Bit Assignments
Bit No.

Mnemonic

Description

Error Indicators (Cant)
14

NXM

Non-Existent Memory - This bit will set when the CD takes longer than
20 JlS to complete anyone Non-Processor Request transaction (NPR), as a
result of addressing a non-existent (memory) location. If set during a data
transfer, this will terminate the sequence by IOD=l and CDDEND will also
be set. Bus time out is taken as equivalent to bus completion elsewhere, so
that a sequence can proceed to its normal ending point.

IBM Reset Indicators
13

SELRST

Selective Reset - This bit will be set by the CH execution of a Selective
Reset sequence as described in the CH to CU OEM Interface Manual
published by IBM. This sequence is usually a response to a malfunctioning
CD/device. When set, this bit causes a Program Interrupt (PI).

SYSRST

System Reset - This bit will be set by the CH execution of a System-Reset
sequence as described in the IBM document, eH to CU OEM Interface
Manual. When set, this bit will cause a PI.

INFDSC

Interface Disconnect - This bit is set when the channel performs a disconnect operation with the CU.

CH Status Flags
10

UCHKS

UC Sent - This bit is asserted when Unit Check has been presented in the
status byte.

CHENDS

CH End Sent - This bit is used to notify the emulator that CHEND status
was sent in a status response.

BSYS

BSY Sent - BSY status bit was sent to the channel.

CHI End Indicator

CHIS

Channel-Initiated Selection Sequence End - This bit is set when a
channel-initiated sequence has been completed with the CD. This bit
becomes a 0 when the DXDS is reset after the DXDS is entered into the
TT.

CUI End Indicators

ESEND

Ending Sequence End - This bit is set when a status byte is presented to
the channel as a result of a program-initiated sequence or when a stacked
status is finally accepted. This bit is most commonly associated with the
ending status presentation type of sequence which normally follows a
Data Transfer sequence.
It may, under some circumstances, occur that the CHIS bit is set as a
result of a CUI-ISS contention situation, where the device address requested matches the device address selected from the channel and the CD
was requesting to present status.

(continued on next page)

4-5

Table 4-2 (Cont)
DXDS Bit Assignments
Bit No.

Description

Mnemonic

CUI End Indicators (Cont)
05

CHDEND

Channel Data End - This bit is set during a Data Transfer sequence when
the channel byte count overflows. (Command-Out is sent in response to
Service-In.) This bit, in its true state, causes the CU to terminate the Data
Transfer sequence. This bit is also set when the CH terminates a Data
Transfer sequence by Interface Disconnect (INFDSC=I). It also sets the
laD signal. CHDEND is cleared after being copied into the TT.

CUDEND

Control Unit Data End - This bit is set during a Data Transfer sequence
when the DXBC (Byte Count) goes to its all 0 state. When set, this bit
causes a PI and also causes the DONE bit to assert. It also sets the laD
signal. When this bit is asserted, it causes the CU to terminate the Data
Transfer sequence.

Special Indicators
03

ISSREJ

Initial Selection Sequence Rejected - ENDEN in the DXCS register enables
this bit to set when a channel-initiated selection sequence addressed to the
CU is answered by the CU with a Control Unit Busy status indication and
a short Control Unit Busy sequence. This can only occur if the CUBSY bit
in the DXCS is set when the CH tries to initiate an ISS and status is not
pending for the addressed device. ISSREJ is not cleared with the rest of the
DXDS, but remains set until CUE is accepted by the CH.

CMDCHN

Command Chaining - The bit sets if the CH has indicated that another
(CCW) operation will probably follow for the CU/Device currently connected when Device End is presented. Command chaining occurs when the
Status-In tag from the CU is answered by Service-Out with Suppress-Out
up.

STKSTB

Stack Status Copy - This bit is set when the CH informs the CU that the
status byte being presented on Bus-In cannot currently be accepted by the
CH. This occurs when the CH responds to Status-In with Command-aut.
STKSTA can be set by the program if the CU is not active with the CH
(LOCKO=O). This is useful when initiating a CU request for status presentation. If Suppress-Out and STKSTA are both true, the CU drops its
Request-In, since the status contained is suppressable (once status has been
stacked the CH also defines that status as suppressable). Since this bit is a
copy of the STKSTA flip-flop, it is read-only.

CMDREJ

Command Reject - This bit is set when the command sent to the DXII-B
is rejected. The rejected command is stored in the CUCR.

4.5.2 Command and Address Register (DXCA)
This DXCA register contains the Control Unit Command Register, CUCR, and the Control Unit Address Register,
CUAR. These two bytes are the command and address as transmitted from channel during an initial selection
sequence. This register is stored as the tumble table entry for this device upon completion of a CH-CU interaction. These bits and their functions are listed in Table 4-3 and shown in Figure 4-4.

4-6

Table 4-3
DXCA Bit Assignments
Bit No.

Mnemonic

Description

15-08

CUCR

The left-hand byte of the DXCA Register contains the CUCR. The CUCR
cannot be loaded by the program. This byte contains the last command
sent by the channel (even if it was rejected by the CU).

07-00

CUAR

The right-hand byte contains the CUAR. The CUAR is loaded with the
device address from Bus-Out during an initial selection sequence. The
CUAR is also loaded and cleared via PDP-II program control if LOCKO
is a O.

DXCA REGISTER

READ'ONLY

COMMAND REGISTER (CUCR)

------1:*_.._-----

SECOND DATA B Y T E - - - - - - - - i - "
'1-1240

Figure 4-4 Comand and Address Register (DXCA) Bit Assignments

4.5.3 Control Unit Status Register (DXCS)
This register contains the primary control command information bits and primary status indications for the
DXII-B. The DXCS can not be modified by the PDP-II program when LOCKO equals 1 (except for DONE and
INTEN). These bits and their functions are listed in Table 4-4 and shown in Figure 4-5.

ENABLE
FORCED
BURST
MODE

UNUSED
ALWAYS

FAST
CU
BUSY
SEQUENCE

ENABLE
STOP ON BAD
PARITY DATA

11-1241

Figure 4-5 Control Unit Status Register (DXCS) Bit Assignments

4-7

Table 4-4
DXCS Bit Assignments
Bit No.

Mnemonic

Description

PARSTP

Stop on Parity Error Enable - If this bit is set to a 1 and a parity error
occurs on Bus-Out during a Data Transfer sequence, then the sequence is
terminated and CUDEND will be set. If this bit is not set, PARER can still
be set but the sequence will end nonnally.

CUFBM

Control Unit Forced Burst Mode Enable - This bit can be set by the program when CU Forced Burst mode is desired. This condition causes the CU
to hold OPL-IN up from initial selection through the presentation of
Channel End (except for TIO and HIO).

ENDEN

Control Unit End Enable - This bit is set and cleared only by the pragram.
The purpose of setting this bit is to assert CUEND in the device status presented to the channel during a CU busy sequence, i.e., where the CUBSY
bit is already set.

Not Used

BSYEN

CUBSY Enable - This bit enables the setting of CUBSY immediately upon
responding to a CUI or CHI. This bit is set to 1 by the program for emulating a single thread control unit.
Reserved

ONLINA

On-Line Request Enable - This flip-flop, when set, indicates that the control unit has made or is making a request to go on-line to the 360 channel.
It is a two-level flip-flop. This is the lower stage of the on-line flip-flop
which is loaded or cleared by program command (ONLINA: DXCS (09)).
The upper stage is the operating on-line flip-flop ONLlNB (DXCB (02)).
ONLINB follows the changes of ONLINA at a time when, as specified in
the OEM channel manual (IBM), it is proper to make changes from on-line
to off-line or from off-line to on-line. (The CH is considered on-line itself
whenever operational-out is set.)

CUBSY

Control Unit Busy Enable - This bit set will cause a channel-initiated
sequence to be answered by the control unit with a CU Busy sequence.
This bit causes the BSY and SM bits to assert to the Bus-In during the subsequent status presentation from the CU. This bit is set and cleared by the
program and by the DX hardware if so enabled by BSYEN. Program
manipulation of CUBSY is not recommended.

DONE

Sequence Done - The DONE bit is the normal interrupt producing condition which the DXll uses for its primary interrupt control (c.f., INTEN).
If both DONE and INTEN are set, an interrupt will be requested. Clearing
DONE is required (of the program) only before making an attempt to
change registers. With DONE reset, LOCKO may also be reset if the DXll
is in either Phasp. 0 or Phase 7. Loading DONE is allowed only in Phases
o or 7.
In Phase 4, TSl, DONE is cleared to reset the interrupt request. In Phase 4,
TS2, DONE is set (also NPRX is set) so as not to conflict with a possible
program load in Phase 7.
(A program set of DONE should only be attempted by a maintenance program as an isolation test of the DXll interrupt.)
(continued on next page)
4-8

Table 4-4 (Cont)
DXCS Bit Assignments
Bit No.

Mnemonic

Description

INTEN

Interrupt Enable - This bit is always writable. It is recommended that this
bit always be in its I state before activating the on-line flip-flop and that the
on-line flip-flop be cleared prior to clearing this bit. This bit can be cleared
or set by program control only.

STKSTA

Stack Status (c.f, STKSTB) - If set, STKSTA indicates that status is
stacked. When cleared, it indicates that status is accepted. It can also be
set voluntarily by a program that is presenting a suppressable (or low
priority) status. It is also set automatically by the DXII when the CH
re;quires a status to be stacked and the CU will attempt to present it again.

04,03

XBA

Extended Bus Address Bits - These bits are the two extended, most
significant bits of the memory address register during all transfers to
or from core via NPR operations. They are loaded and cleared under
program control and can be caused to complement should the DXBA
overflow from a DXBA increment of +2 during a data transfer. They
are used for all NPR transfer sequences, status word fetches, tumble
table entries, and data transfers.

02,01

FCTN

Function - These two bits make up the DXII Function Register. They
are used by the program to select the CU operations desired:
FCTN=O - reset the DXII
FCTN= I - input data transfer
FCTN=2 - output data transfer
FCTN=3 - present status

When the GO bit is set, the function requested is performed. If
FCTN=O, the reset operation is done on the DXII and the DONE bit is
left cleared.
If FCTN:;i:O then Request-In (REQI) will be raised at the start of a CUI
sequence.

4.5.4 Offset and Status Register (DXOS)
This register contains the offset address of the status pointer word (SPW), which is termed CUOR, and the status
byte, termed CUSR. The contents of the CUOR are program loaded for the first (or the left-most) six bits. Bits
9 and 8 of the CUOR are unused and are always zeros.
The CUOR contains the high-order six bits of the SPW table and of the tumble table. The CUOR should be set
before an on-line request is made.
The CUSR contains the status information listed in Table 4-5 and shown in Figure 4-6. These bits are transmitted
to the channel.

4-9

Table 4-5
DXOS Bit Assignments
Bit No.

Mnemonic

Description

ATTN

Attention

STAMOD

Status Modifier

CUEND

Control Unit End

BSY

Busy - The program should not directly set this bit. This bit is set only by
a CU Busy sequence or by being loaded as the status portion of the SPW.

CHEND

Channel End

DEVEND

Device End

UCHECK

Unit Check

UXCEP

Unit Exception

DXOS REGISTER

CONTROL
UNIT
END

CHANNEL
END

ATTENTION

UNIT
CHECK

UNIT
EXCEPTION

I<>-_ _ _ CONTROL U(~I;F~~~S~; SRpE~~STER (CUORI -----<>II<>----CONTROL UNIT STATUS REGISTER (CUSRI--~
I < > - - - - - - - F I R$T DATA BYTE ------~
11-1242

Figure 4-6 Offset and Status Register (DXOS) Bit Assignments

4.5.5 Bus Address Register (DXBA)
This 16-bit register, shown in Figure 4-7, can be cleared and loaded under program control if LOCKO is a O. It is
used during data transfers to point to the PDP-II core location to or from which data will be transferred in I6-bit
words at a time. During a data transfer, the DXBA is preset by the program to point to the first byte location
where data is sent or stored. The DXBA is incremented by two each time a PDP-II data word is fetched or stored
in core during the data transfer process. Should the DXBA overflow, the extended memory address bits (XBA) in
the DXCS will be caused to complement their states appropriately.
The DXBA is also used during channel-initiated sequences to fetch both the status pointer word and the device
status byte from PDP-II core. In addition, the DXBA is used to address the tumble table when information is to
be stored there.
The low-order bit of the DXBA (DXBA 00) is normally set to 0 by program load. When this bit is placed on the
Unibus address lines, it is always represented as O.

4-10

During write operations, when data is being sent from the IBM channel to the PDP-II, starting or stopping on an
odd byte boundary always puts a garble in the adjacent byte.
DXBA REGISTER
15
NPR
#

I 14

I 11

I I I I I

I- CONTROL UNIT OFFSET REG. (CUOR)"

615

J 2

I I I I I I I
10

(0)

DST OFFSET FOR THIS DEVICE

~654321

15
13
12
11
10
14
'-CONTROL UNIT OFFSET REG. (CUOR__..

(1)

15
14
13
12
11
10
-CONTROL UNIT OFFSET REG. (CUOR)'"

(I)

7
6
5
4
3
2
I
0
I--CONTROL UNIT ADDRESS REGISTER (CUAR)_
CONTROL UNIT COMMAND REG (CUCR)_

5
4
3
2
I
0
TUMBLE TABLE INDEX (TTNDX) ______

0
(0)

ALWAYS (0) WHEN
PRESENTED TO
UNIBUS OR READ BY
'-IPROGRAM. DATA SENT
HERE IS SAVED IN
ODD TO INITIALIZE
BALF.

7
6
5
4
3
2
I
0
_ _ TUMBLE TABLE INDEX (TTNDX)+2 _ _

DATA ADDRESS

11-1243

Figure 4-7 Bus Address Register (DXBA) Bit Assignments

4.5.6 Byte Count Register (DXBC)
This register, shown in Figure 4-8, is used only during data transfers. It is loaded and cleared under program
control and is set up prior to the data transfer involved. The DXBC is set to the complement of the number
of bytes desired to be transferred. As each byte is actually transferred to or from the DXII-B, the DXBC is
incremented by one until all bytes are transferred, (DXBC=all zero's) whereupon the DXBCequals O. When
the DXBC contents go to 0 during a Data Transfer sequence, the CUD END bit of the DXDS will set and
thereby terminate the Data Transfer sequence with the channel.
The program could set DXBC to -1 at any time during a data sequence (Phase 5 or 6) to terminate that sequence.
Several attempts may be required in case the DXBC is incremented at the time of program load.
DXBC REGISTER

i - - - - - - - - - - - - - - B Y T E COUNT REGISTER (DXBC) - - - - - - - - - - - - - - 1
i - - - - - - - - - - - - - - - - P D P SET TO-l TOSTOPI/O--------------~
11-1244

Figure 4-8 Byte Count Register (DXBC) Bit Assignments

4.5.7 Maintenance Out Register (DXMO)
This register, shown in Figure 4-9, is used to hold the 360 Channel Bus Out Data and Tags. This register is always
directly readable by a PDP-II program. When the DXII-B is on-line, the bits in this register are mostly the same
as what appears on the Bus-Out lines (hardwired cables to the Bus-Out plug). When the DXII-B is off-line, these
bits can be written directly by a PDP-II programmed request. The programmed bits are held buffered in the
DXMOB. When the DXII-B is on-line but cabled to the Bus-Out Test plug, these bits are also writable by PDP-II
programs. The On-Line Cabled mode is used to isolate the cables and Bus-Out receivers as an error source.

4-11

DXMO REGISTER

15
OPLO

14
HLDO

I 11

ISELO I SUPO IADRO I CMDO ISRVO PARO

SELECTION
CONTROL
LI NES

7
7

I 5

I 2

J 6 I 5 J 4 1 3 I 21 1 I 0 II

I 2 I 3 I 4 I 5 I 6 I

ACTUAL BUS
OUT SIGNALS
BUSOB

TAG
LI NES
GOES

CLKAOL~H~~ CABLED
CONO-CONTROL LINES OUT

BUSO-I8M BUS OUT

WRITABLE ONLY WHEN EITHER OFFLINE. OR CABLED ONLINE
11-1245

Figure 4-9 Maintenance Out Register (DXMO) Bit Assignments

The IBM Bus-Out Register (BUSO) bits 07 -00 contain the Bus-Out data bits 0 to 7 as seen either directly from
the Bus-Out cables or from BUSOB if off-line. When written by the PDP-II program, this byte is buffered in
BUSOB.
The Control Lines Out Register (CONO) bits 15-08 contain the signals listed in Table 4-6 as strobed (copied) at
TPI or TP2 from either the Bus-Out lines or from CONOB.
Table 4-6
DXMO CONO Bit Assignments
Bit No.

Mnemonic

Description

Selection Control Lines
15

OPLO

Operational-Out - This line indicates that the channel is in operation.
NOTE
Refer to IBM manual A22-6843 for a detailed
description of each line of the 360 Bus.

HLDO

Hold-Out

SELO

Select-Out - This flip-flop is set only if both hold out and select out are
set. When set or cleared by a PDP-II program, only the simulated select
out signal is affected (see DXMOB).

SUPO

Suppress-Out

ADRO

Address-Out

CMDO

Command-Out

SRVO

Service-Out

Tag Lines

(continued on next page)

4-12

Table 4-6 (Cont)
DXMO CONO Bit Assignments

Bit No.

Mnemonic

Description

Parity Line
Parity Out ~ This bit has double duty when written by a PDP-II program
while the DX is in On-Line Cabled mode. At such times the state of the bit
will be translated directly both into the state of the Simulated Clock Out
line (of the Bus-Out Test plug) and into the Parity-Out line. Clock Out's
primary purpose is to provide a synchronization time for the Control Units
to make changes in their ON/OFF LINE state.

PARO

Another function of the bit is to allow program generation ofeither normal
(odd) Parity-Out or the generation of "bad" (even) Parity-Out. This feature
is necessary to permit checking the parity generator within the main DXll
logic.
The parity is determined by counting the number of ones in Bus-Out
(8 bits); if the result is an even number, PARO should be set to 1. Parity
is then checked by adding all 9 bits together; good parity always gives an
odd sum.

4.5.8 Maintenance In Register (DXMI)
This register, shown in Figure 4-10, is used for reading the Bus-In tags and data originating from the main DXll-B
logic. In this way, the register represents the channel's view of Bus-In. The output of these flip-flops is enabled
to the Bus-In lines either when OPLI=l or when a Fast CU Busy is in progress.
The register is normally read-only; but for maintenance purposes, programmed modification is permitted except
for CLKO and PARI. When the DXll-B is off-line, the data read by PDP-II programmed references comes
directly from DXMI. When the DXll-B is on-line, the data read by the PDP-II program comes from the Test-In
plug. Correct data will be seen then only if the plugs are cabled together.
The Buffered Bus In Data Register (BUS!) bits 07 ~OO contain the data that is enabled to the Bus-In lines for
transmission back to the IBM 360 Channel. The output of this byte is always input to a parity generator that
produces the signal PARt
The Buffered Control Lines In Register (CONI) bits l5~08 are listed in Table 4-7.
DXMI REGISTER

OPLI

SEll

REQI

"CO,,,,,·
CONTROL
LI NES

ADRI

STAI

SRVI

CLKO

PARI

"~~ I

LI NES

READ ONLY WHEN ONLINE

(FROM
(NOT
CABLES)
FF)
OK TO
PARITY
GO ON
OF
LINE
BUSI
WHEN OFFLINE-ACTUAL BUSI
WHEN ONLINE-BUSI VIA CABLES

READ ONLY
CONTROL LINES IN (CONI)

IBM BUS IN (BUSI)
11-1246

Figure 4-10 Maintenance In Register (DXMI) Bit Assignments

4-13

Table 4-7
DXMI CONO Bit Assignments
Bit No.

Description

Mnemonic

Selection Control Lines
15

OPLI

Operational-In

SELl

Select-In (not direct cleared)

REQI

Request-In

ADRI

Address-In

STAI

Status-In

SRVI

Service-In

CLKO

Clock Out Signal from Bus-Out - This line always comes from the cables,
even when the DXll is off-line.

PARI

Bus Parity In (not a flip-flop - output of parity generation for BUS!)

Tag Lines

Test Lines

4.5.9 Control Bits Register (DXCB)
This register contains control bits used for DXI1-B operation. They are read-only, and are used for diagnostic or
. emergency purposes only. The register is reset by INIT=I, except for ONLINB and SELL These bits are listed in
Table 4-8 and shown in Figure 4-11.
DXCB REGISTER
15

LOCKO

PH2

TIME
STATE
WRITE
LOCKOUT
ON OX

REGS
RO

O~ R/W

(NOT
FF)

PHASE
STATE
SYNC
FLOP

(NOT
FF)
lIO
DONE
CU
DATA
CONTROL

(PENDI NG
STATUS)
BYTE
ALTERNATOR
FLOP

1 ~GO

O~DONE

ON
LINE
TO
IBM

~----------------------------------READONLY----------------------------------~
11-1247

Figure 4-11 Control Bits Register (DXCB) Bit Assignments

4-14

Table 4-8
DXCB Bit Assignments
Bit No.

Mnemonic

Description

LOCKO

Lockout - If this bit is set to aI, the first five programmable registers are
made read-only to the PDP-II program. It is this Lockout protection
which provides the interlocking or contention control which is needed
when a channel-initiated sequence conflicts with the setup of a control
unit initiated sequence. The channel sequences are always given precedence, and the control unit programs are prevented from further modification of the DXll Registers.

14,13,12
11

Phase Control Bits - These bits are used to determine the major phase of
the DXll Controller.
TSFF

Time State - This bit is the clock control:
0= TS2
1 = TSI

FASTCU

This signal is available for diagnostic test purposes.

SYNC

Synchronizer - This is a phase synchronizing flip-flop that is used for
miscellaneous purposes to disable certain portions of logic within any
particular phase. The details of this use are spelled out in the flow diagrams.

CUDX

CU Data Control - This is a control unit data control flip-flop. If it is aI,
this means that the Control Unit data (composed of the CUCR and CUSR)
can be used or is available to either the Bus-Out lines, or to the Bus-In lines,
in the case of PDP-II output transmission.

IOD

Input-Output Done - This bit is not a flip-flop, but is the Inclusive-OR of
all conditions which can stop a data transfer that is taking place in Phase 5
or 6.

BYPAS

Bypass - This bit is used for a number of purposes:
a.

First, it is used to indicate that this is the first byte of data that is
being transmitted or received, i.e., bypass suppress-out.

Bypass to a 1 also indicates that the device status table will not be
accessed by this particular channel-initiated sequence .. This might
occur because of a zero pointer in the left portion of the SPW, i.e.,
bypass DST.

Bypass to aI, may also be used as an indication that no address out
has been received. This is a synchronizing function that is used in
Phase 0 for a CUI sequence, i.e., bypass SPW and DST.

Bypass is also used as a copy of the parity okay signal. This is used
to communicate between Phases 2 and 3, i.e., bypass the command.

Bypass is used as a copy of the status pending indication between
TS I and TS2 of Phase 0 during a CHI sequence, i.e., bypass Phase 1
and both SPW and DST.

Bypass a 1 (and SYNC=O) is used to indicate in TS2 that a fast CU
Busy response was made in TS 1. This is essentially a synchronizing
function, i.e., bypass CHI sequence.
(continued on next page)
4-15

Table 4-8 (Cont)
DXCB Bit Assignments
Description

Mnemonic

Bit No.

NPRX

NPR Control Switch - This flip-flop is the NPR control. If it is a 1 this
means the DX is requesting a non-processor or memory-to-device data
transfer from the PDP-II. When NPRX becomes a 0 this is the indication
that the transfer has been completed.

NPRT

NPR Transfer Direction - If NPRT equals 0, then data (or status table
information) is being taken from the PDP-II core. If NPRT is 1, then data
(or TT information) is being sent into PDP-II core.

BALF

Byte Alternator Flip-Flop a.

If this bit is aI, it indicates that status is pending and that the
device for which status is pending has been addressed by the
channel. In this case both the SPW and the DST fetches are bypassed and the CUSR is used as is, i.e., alternate logic is used.

This bit is used during Phases 5 and 6 to keep track of which half
of the data word is currently being used, i.e., alternate bytes are
used.

ONLINB

On Line to IBM - The state of this flip-flop reflects the actual status of the
DXll as to whether arnot it is connected to the I/O interface. ONLINB
is the second level of the ONLINA flip-flop found in DXCS bit 9. ONLINB
is not direct cleared when the rest of the DXCB is cleared.

ADRECC

Address of Control- This bit is not a flip-flop, but is the continuing.signal
from the address comparator indicating that the control unit portion of the
address matches Bus-Out.

ADRECD

Address of Device - ADRECD is a similar signal indicating that the device
address matches (ADRECC=l also).

4.5.10 Non-Processor Request Data Register (DXND).
This register, shown in Figure 4-12, contains each data word that is transmitted to or from the PDP-II core via
NPRs. This word is available for use by the MAINDEC.
DXND REGISTER
15

NPR

I I

1 + - - - - OFFSET OF DST FOR THIS

I I

DEV---1ATT~EN I cuT~NDT CH~ND 1 J~CK I
10

TO
STAMOD

BSY

TO
DEVEND

CONTENT

!--SPW

TO
UXCEP

2 I - - - - - - O D D STATUS B Y T E - - - - - - . j . [

f.-DST

3 I+-----------------DXDS----------------~TT
4 I----------------DXCA---------------~.TT
N i ' " - - - - - - - - - - - - - - S E C O N D DATA B Y T E - - - - - - - - - - - - - + ! + . I / O
I----------------READON~--------------~
11-12.48

Figure 4-12 Non-Processor Request Data Register (DXND) Bit Assignments
4-16

4.5.11 Extra Signals Registers (DXESI and DXES2)
The bits assigned to this register are listed in Table 4-9 and shown in Figures 4-13and 4-14. These two bytes are
provided for future 370 controls and for diagnostic uses.
Table 4-9
DXESI and DXES2 Bit Assignments
Bit No.

Mnemonic

Description

15-08

TTNDX

Tumble Table Index Byte - This byte is the low-order address of the TT
entry to be used next. It is shifted left before being copied into the DXBA.

07-00

MISC

Miscellaneous Signals

DXESI

Reserved

ODD

Copy of DXBA (00) (for future use)

NPRTO

NPR latency error. Bus grant not received within timeout interval.

DXTO

Program response latency error. While OPL-IN was up, the program did
not interact for a 5 sec period.

TIMDIS

Set to disable DXTO during program debugging.

SOSIEN

Fast NPR test enable (Service-Out-Service-In-Enable). Causes simulated
SRVO to follow SRVI.

MNCLEN

Maintenance Clock Enable - When this bit is set, the DXll does not
change time states until MCLKP is set.

MCLKP

Maintenance Clock Pulse - If MNCLEN is set, setting this bit causes the
DXll to enable the next time state.
One normal clock pulse will be issued with each setting ofMNCLKF, the
Clock pulse thus generated will reset the MNCLKF. The Unibus Interface
continues to run at normal speed at all times. Maintenance Clock mode
cannot be entered when on-line.

DXES2
01

DSCRSP

Disconnect Response - Set when IBM issues an Interface Disconnect.

IRS

IBM Reset Stored - Set in Phase 4 if an IBM Reset is issued, and used in
Phase 7 to remember that an IBM reset sequence occurred.

I<>-----TUMBLE TABLE INDEX (TTNDX)----+i

BUS
TIMEOUT
ERROR

DISABLE
PROGRAM
TIMEOUT

ENABLE
CLOCK

1 + - - - - - - - - READ ONLY ----------<+_----- MISCELLAN EOUS (MI SC) ---~-""'i
11-1249

Figure 4-13 Extra Signals Register DXESI Bit Assignments
4-17

DXES2 REGISTER

11-12.50

Figure 4-14 Extra Signals Register DXES2 Bit Assignments

4.5.12 Maintenance Out Buffered Register (DXMOB)
This register, shown in Figure 4-15, holds the bits written by the Unibus into DXII-B address plus 14 (program
thinks that this is the DXMO). This register is needed when the DXII-B is in On-Line Cabled mode to present
steady levels to the drivers. The left-hand byte is CONOB (Control Out Buffered); the right-hand byte is BUSOB
(Bus Out Buffered).

cONos------.--..f·I-·--SUSOS-----l:1

f~---------------------------------READ DN~--------------------------------~-·
NOTE,
Normally these flops are loaded by write address 15. 14 and
read by read add ress 2.7. 2.6.
I f offline, they are read by read address 15, 14.
I f online-cabled, they are also read by read address 15,14.

11-1251

Figure 4-15 Maintenance Out Buffered Register (DXMOB) Bit Assignments

4.6 PROGRAMMING CONSIDERA nONS
This paragraph contains a discussion of some of the general programming considerations that pertain to the
DXll-B.
4.6.1 Hardware/Software Interlock
Because of ~ contention situation that can arise when both the channel and the control unit (through software
request) attempt to use the interface, an interlock mechanism is necessary to protect information used by both
parts of the system. The control unit can appear busy to channel activity when the control unit software must
use the facilities. After system reset, while table initialization is in progress, the CUBSY flip-flop is set.
The general soultion is simply to let CH requests always override CU requests. This is done by the LOCKa flipflop which prevents further changes to the DXII-B registers once a selection sequence has begun. The program
can later examine the interrupt conditions to determine if the program requests must be repeated. LOCKa gates
DXCS, DXCA, DXOS, and DXBA. Only DXBC remains program-writable.

4-18

4.6.2 Boundary Considerations
a.

The SPW is 256 words long and TT is 128 words long, the two must begin on a 2000 8 address boundary.

All DSTs are 256 bytes long and begin on a 400 8 address boundary.

All data transfers should begin on an even boundary. On input operations, the following will occur for
odd BA and odd BC, respectively:

When starting an input on an odd address, the previous even address byte is clobbered.

When ending an input on an even address, the following odd address byte is clobbered.

On output operations, as many as two words following the end of the data buffer can be pre-fetched.
Therefore, buffers should not be assigned at the end of core. This prevents spurious NXMs.

4.6.3 Interrupt Request
When the DXll-B requires either a program interrupt or tumble table service, it sets the DONE bit, leaving
LOCKa set. When the program is ready to try a CUI, it must clear DONE; then, if no new selection is in progress,
the DXll-B clears LOCKa.
The tumble table (TT) is a 256 word buffer in core memory (see Figure 4-16) that is used to store the contents
of the DXDS and DXCA registers which provide a record of event notification to the program. Entries used by
the program must be zeroed when they are used. All entries into the TT are guaranteed not to be zeros. A zeroed
entry indicates no entry.
The tumble table entry address is generated in the DXBA register by combining the contents of the DXOR high
order byte, the tumble table index byte times two, and by putting a zero in the lower bit of the DXBA register
(see Figure 4-7). The tumble table index is incremented after each entry.
NOTE
Clearing INTEN is discouraged during DXII-B operation.
The following rules should be followed for programming interrupts and servicing the tumble table.
a.

The TT entry should be zeroed after being serviced.

On an Interrupt, all nonzero TT entries should be serviced before dismissing Interrupt (RTI).

Software should keep a pointer to current TT entry. This should follow the hardware pointer in relieving the entries the hardware places (hardware will guarantee a nonzero TT entry).

No software requests for data transfer or status should be made until all TT entries are serviced.

Before each TT entry is serviced, DONE should be cleared with a

BIC # DONE, DXCS
thus, the general INT service procedure is:
1.

Clear DONE.

Service current TT entry. Update action to be performed for device whose address is in TT entry.
Do not request data transfer or status at this time. (Note that this may cancel a previously queued
request for this device.)

Clear TT entry.

4-19

Bump software pointer to next TT entry.
NOTE
If IT entry not 0, go back to Step 1. If it is 0, proceed.

When a zero TT entry is encountered, initiate last action pending for each device.

Dismiss interrupt CRT!).

4.6.4 Data Transfer
Data transfer sequences (DT) are always initiated by the DXII-B program. It is a software responsibility to
ensure that a DT is valid at the point requested. Information supplied to the hardware includes Buffer Start
Address (DXBA), Byte Count (DXBC), Device Address (CUAR), and I/O direction (FCTN - input or output).
The hardware will get control of the I/O interface and transfer the data in a single burst, after which it will generate a Data End interrupt. The last bit set is the GO bit. If LOCKOUT is set at this time, the effect is a NO OP
and the result is no data transfer.
Several other events can happen as follows:
a.

A bus out parity error can occur, setting PARER. This will terminate data transfer with PARSTP.

A timeout reference can occur, setting NXM.

c.
d.

The channel can indicate I/O stop, setting CHDEND.
An Interface Disconnect can occur.

If a CUI is used, it could be overridden by an ISS, in which case an interrupt would occur; but different bits

would be set in the DXDS and copied into the tumble table.
4.6.5 Status Presentation
There are several cases in which presentation must be initiated by the program as follows:
a.

When stack status is indicated by the channel. In this case, the DXII-B will automatically request
presentation of the status again, until it is subsequently relieved or overridden via an ISS (only if
BSYEN = 1).

When ending status is initially available for the device (DEVEND, etc.).

When asynchronous status becomes available for the device (DEVEND or ATTEN).

When a device that had previously been interrogated while busy becomes free (CUEND or DEVEND).

At the termination of a data transfer (CHEND or CHEND+DEVEND).

The program loads the status and device address and requests status presentation (FCTN=3). If the status is
accepted, the device status, device address and command (if any) are loaded into the tumble table and an interrupt is generated.
4.6.6 On-line/Off-line Control
The ONLINA flip-flop is written by the program to request a change of on-line status. The ONLINB flip-flop, in
DXCB, can be read to verify that the transition occurred. The program clears the ONLINA flip-flop to attempt
to put the DXII-B off-line. The ONLINB flip-flop will not clear if any channel activity is in progress.

4-20

NOTE
When the program sets ONUNA, the ONUNlB flip-flop
sets after::; ms if the hardware ON-LINE/OFF-LINE switch
is in the ON LINE position and a function is not pending.
An on-line/off-line request can be made at any time. If channel activity occurs at the time ONLINA is cleared,
it will not clear. This allows the program a chance to reconsider the off-line request in view of the new CHIS.

NOTE
An On-line/Off-line sequence should not be attempted in an
interval less than 10 ms.

.......
TUMBLE {
TABLE
ENTRY
~

DXDS
(SEE FIG. 4-3)

DXCA
(SEE FI1G. 4- 4)
CUAR

CUCR

~
256 WORDS
OF
CORE MEMORY

128 EN TRIES

+
......
TUMBLE {
TABLE
ENTRY

.......

DXDS
(SEE FIG. 4-3)
DXCS
(SEE F t 4-4)
CUCR

CUAR

,1'-3398

Figure 4-16 Tumble Table

4-21

CHAPTER 5
THEORY OF OPERATION

5.1 SCOPE
This chapter provides a detailed description of the DXI1-B System. The discussion consists of three major parts:
a) a functional description of the overall control unit operation, b) a system block diagram discussion, and c) a
detailed theory of operation covering control unit logic circuits. The discussions in this chapter are supported by
a complete set of engineering drawings contained in a companion volume entitled DXII-B, System 360/370
Channel to PDP-II Unibus Interface, Engineering Drawings.

5.2 FUNCTIONAL DESCRIPTION
As described in Chapter 1, the DXII-B functions as a data and status transfer controller between an IBM 360/370
I/O Channel and a DEC PDP-II Computer (Figure 5-1). When operational, it executes signal sequences, performs
NPR data transfers, initiates status presentation, and handles stack status conditions, returning appropriate indications to the program that enable that program to complete the sequence. When initiated by a stored PDP-II
program, the DXII-B conducts transfers between the IBM Channel and the Unibus, automatically transferring
data between its buffers and Unibus locations, participating in data transfers on the channel, and stopping the
transfer when the prescribed number of bytes have been transferred. In addition, the DXII-B communicates with
the PDP-II Processor, which controls the status indications provided by the DXII-B to the 360 Channel.

;>
rn

::J

IBM
360/370

CHANNEL

'"z

::J

DXl1-B

(MPX OR SEll

PDP-ll

d..

0..

11-125

Figure 5-1 DXII-B System, Functional Block Diagram

As such, the DXII-B must have the dual capability of communicating in hexadecimal code with the IBM environment, and in octal code with the PDP-II System. It must also make the format conversions between the bit formats of both systems. The DXII-B must be able to respond to the normal signal sequences generated by either a
multiplexer or selector type channel, and must also be able to participate in Unibus dialogue - within the latency
requirements of both systems.

5-1

5.3 BLOCK DIAGRAM DISCUSSION
A typical DXII-B System block diagram is shown in Figure 5-2. As can be seen from the figure, a 360/370
Central Processor is connected to several miniprocessors termed channels. These channels can be of either a
multiplexer or selector variety. Each channel can accommodate several control units which, in turn, interface to
several devices. The DXII-B Controller functions as a control unit in the 360 system and can be tied to either a
multiplexer or a selector channel bus. The DXII-B, then, is assigned a Unibus address and is thereby put in
communication with the PDP-II processor, its memory, and any devices on the bus. Special software (emulators)
placed in the PDP-II memory adapt the hardware, causing it to appear to be any of most IBM type control units.

TO OTHER

~----L-----------------------------'CONTROL

UNITS

TO OTHER

~----r-------------.---------------'CONTROL

UNITS

TO OTHER
OEVICES
NOTE:
Can also be connected to MPX channel.

11-1253

Figure 5-2 DXII-B System, Block Diagram

Although the overall system comprises hardware and software sections, the hardware consists of two parts: Data
Paths and Control Logic. The data paths are in three sections: 1) IBM Control, 2) Central Control, and 3) PDP
Control (Figure 5-3). The control logic is divided into nine parts: phase independent operations plus eight major
phases. Finally, each major phase comprises two time states.
Internally, the DXII-B contains a data path control section which ties directly to the 360/370 Interface, a section
for dealing with the PDP-II Unibus, and a central data path section for synchronizing operations between the two
hardware interfaces. The IBM control, central control, and PDP control sections are internal to the DXII-B and
are not visible across the formal interfaces.
It is the control logic section, along with the support software, that provides the basic program ability of the unit.

The separation of the DXII-B into functional sections does not imply that they are physically separable sections.

5-2

DXll-B
CHANNEL SIMULATOR

~ I+----t--+I
A
N
N
E
L

IBM
INTERFACE

I I g~:i::: I I

I":~~,, ~
i
I

B
U

N
UNIBUS
INTERFACE

~ ,Jr.,,-]

TIME STATE a. PHASE
GENERATOR

U
S

I
11-1254

Figure 5-3 DXII-B, Block Diagram

5.3.1 IBM Interface Operation
An understanding of the operation of the IBM Interface can be gained only by becoming familiar with the opera-

tion of the 360/370 Channel. For detailed information, refer to the Introduction and Input/Output Operations
sections of the System/360 Principles of Operation, and to the System/360 I/O Interface, Channel to Control
Unit manuals. Although it is beyond the scope of this manual to provide exhaustive coverage of IBM architecture
and facilities, this paragraph supplements the referenced information by giving a minimal description of the
360/370 I/O Interface as seen by an external device such as the DXII-B.
The I/O capability of the 360/370 Central Processor (CP) is provided by a number of limited-function I/O
processors called channels (CH). All channels are attached to the CP and provide a standard I/O interface to
external devices. Thus, each channel provides a single data path into memory which is shareable among up to 256
directly addressable devices per channel.
NOTE
The DXII-B can accommodate only 128 devices at a time.
Conventional I/O is handled by two types of channels: Multiplexer (MPX) and Selector (SEL).
An MPX channel provides concurrent, byte-interleaved I/O with multiple devices, and is used primarily with
slower devices such as printers, card-readers, and communications multiplexers, although it can handle high-speed
bursts of data.
An SEL channel is specifically designed for high-speed burst operation and can service only one device at a time.
The typical transfer is one block or physical record at a time. SEL channels are typically used for high-speed
devices such as disks, drums, and data concentrators.

Each channel represents a single path to memory, and has a single I/O interface that is, itself, logically connected
to only one device at anyone time. Multiple interleaved operations on one channel can be effected with the use
of sub channels described later in this section.

5-3

A channel can be termed a processor in the sense that its activities are governed by stored programs using
sequential fetch and execute techniques. The basic unit of a channel program is the Channel Command Word
(CCW). The term "Command" is used to distinguish it from Central Processor "Instructions". A single command,
Transfer In Channel (TIC), is dedicated to program control. It provides the channel with an unconditional program branch (Jump) capability. All other commands relate to device operations and cause activity on the channel/
device interface. Read and Write are typical commands.
Sequential command execution is not automatic but is a function of a command chaining bit in each command.
If this bit is set, execution continues with the next command. If it is not set, the program terminates. A program
can also be aborted (command chaining suppressed) by detection of a malfunction or other abnormal condition
in the channel or in the device.
The channel cannot initiate the execution of a program. This is done by the CP using a Start I/O (SIO) instruction.
The SIO alerts the channel which then fetches the first command, establishes logical connection with the indicated
device, and reads back status from the device indicating either acceptance or rejection of the command. If the
command is accepted, the CP and CH can continue concurrent and asynchronous execution of their respective
programs. If the command is rejected, the CH program is aborted. The CP will be aware of this at the completion
of the SIO execution and can process the exceptional condition indication. Channel program termination is communicated to the CP through state words and interrupts.
The activities encountered during a typical command execution are a Selection Sequence, a Data Sequence, and
an Ending Sequence. A detailed set of IBM interface timing diagrams are given in Appendix C of the IBM OEM
manual (refer to the Foreword). During a command execution, the channel fetches the command that follows the
SIO, establishes logical connection with the indicated device, and transmits command information. This is called
an Initial Selection Sequence (ISS). If the command is accepted, a Data Sequence (DS) can follow in which data
is transmitted across the interface. When I/O is complete, the device presents status that indicates the success or
failure of the operation. This Ending Sequence (ES) completes command execution.
Some commands involving control operations have no data sequence. In a magnetic tape rewind command, for
example, the ISS starts the rewind operation and the ES takes place when the rewind is complete. If the tape
was already rewound, that would be an "immediate" command for which the ending status is presented during
the ISS and for which there is no separate ending sequence.
Logical connection between the channel and device can be maintained throughout command execution. In this
case, the device monopolizes the channel until the ES is complete. This is the only method used on the selector
channel. On the other hand, the channel and the device can operate independently after the ISS, resynchronizing
only as necessary for transferring data and status. Thus, a multiplexer channel can interleave command executions
for different channel programs.
The channel provides a standard bus of interface signals to all devices regardless of type. Thus, each device
requires a control unit to translate the standard interface sequences into those control signals that are peculiar to
the specific device, and to translate the device's responses back into standard interface sequences. The DXII-B
performs this function for the PDP-II System to which it is attached. As such, the PDP-II, its memory, devices,
and software, constitute a device on the IBM channel - a device, which with changes to the software, can emulate
any of many standard IBM devices. In some cases, such as printers, readers, tapes and disks, the control unit (CU)
is logically (and often physically) distinct from the device. The DXII-B falls into this category. In other
instances, such as the channel-to-channel adapter and other wholly electronic devices, the CU is an integral part of
(and indistinguishable from) the device.

5-4

Devices which are configured in groups, of which only one device need be active at a time, can share a Cu. An
example of this is magtapes, where four drives can share a single CD.
Each device on a channel is assigned a unique 8-bit address. Each CU is responsible for recognizing the addresses
of all devices it controls. Multi-device control units are assigned blocks of contiguous addresses, the block size
being some power of two with the first address being some multiple of the block size. The limit on block size is
usually 16; if the CU requires more addresses, it is assigned two or more (usually contiguous) blocks. Where only
one block is assigned, the high-order address bits that are common to all devices on the control unit can be
regarded as the "CU Number", and the low-order bits that address the devices as the "Device Number". In cases
where the address cannot be broken down in this way, one device address can be dedicated to the CU itself for
commands that involve only the CU.
A system-wide unique address for each device is provided by prefixing the 3-bit "Channel Number" to the 8-bit
device address. This is the full device address used by the CP in initiating channel programs.
As stated earlier, multiple interleaved operations on one channel c:an be effected with the use of "sub channels" .
The facilities required by a channel to service one device are termed a subchannel. These facilities are the command address, data address, data count, etc. The number of channel programs that a channel can execute concurrently is merely the number of subchannels it contains. The sub channel, then, is just some storage area in the
channel where it maintains status information on the particular device or devices that are active. Note that this
storage is not in the CU but in the channel itself.
A selector channel (SEL) has only one subchannel. From the initiation of a channel program for a particular
device until that device releases the channel at the end of the last command, channel facilities are monopolized by
that device; during this period, other devices on that channel are restricted to operations that do not require use
of the channel.
A multiplexer channel (MPX) has several subchannels; at least one for each currently active device. It is monopolized by any device a) during a selection sequence, b) during part of a data sequence for transferring one byte or
burst of bytes, or c) during a status transfer. In other words, it is monopolized only during times in which the
device has an active, immediate need for channel services. The multiplexer channel thus appears to each program
that it executes as a dedicated selector channel.
Because the sub channel used for any device is fixed in any given installation, the channel determines automatically,
from the device address, which sub channel to use. Some sub channels are shared among a group of devices with
contiguous addresses, while others are dedicated to single devices. Shared sub channels can service only one of
their associated devices at a time (the selector sub channel is, in effect, a shared subchannel). Shared sub channels
are particularly applicable to shared CU devices that automatically satisfy the one-at-a-time requirement.
The use of multiple sub channels provides the MPX with its basic multiplex mode, an interleaved half-duplex byte
stream. However, the device can request the channel to operate in burst mode (a transfer in which the device
retains monopoly of the channel for more than about 100 /1s). The burst can involve anything from a few bytes
to a complete command execution. This is called Control Unit Forced Burst Mode (CUFBM).
The selector channel, by contrast, operates only in burst mode. In discussing devices designed to operate on
either type of channel, this is called Channel Forced Burst Mode (CHFBM).
The number, type, and sub channel configuration of channels that can be included in a system are a function of
the CP model. A typical configuration has a single MPX and one or more SEL channels. In addition, the width
(in bytes) of a channel's access to memory, and the degree to which it shares facilities with the CP are functions
of the CP model number. Because of this, it is impossible to make any but the most general statement about
channel capabilities. IBM provides a guide for each CP model on the intricate calculations required to determine
channel loading. The principal limiting factors are a) shared facilities with the CP, and b) the access width.
5-5

In summary, the MPX channel is suitable for operations involving frequent but short data transfers, while the
SEL channel is suitable for infrequent but large data transfers. The respective ranges of suitability are from telegraph adaptors to slower magtapes for the multiplexer, and from magtapes to high-speed disks and drums for the
selector.
The architecture of 360 channels allows them to accommodate devices within a wide range of data rates and
response times. This is achieved through the use of edge-interlocked signal sequences in which, typically, only one
outbound signal from the channel and one inbound signal from the control unit participate. One signal can rise
only when the other has risen, and must then remain up until the other has fallen. This is similar to the MSYN/
SSYN relationship on the PDP-II Unibus. This requirement and the use of control unit initiated sequences allow
the CU to present data and/or status information at times and rates appropriate to the specific device.
Despite its ability to operate at almost dc rates, the channel imposes certain timing constraints to guarantee that
no device ever requires excessive time to complete a signal sequence. This is done to prevent one device from
jeopardizing the operation of other devices on the channel. In particular, device selection sequences are required
to be performed within 32 J.1s, start to finish. A channel timeout monitors this performance. Other timeouts
related to data transfers and to interface activity, in general, are scaled to appropriate limits ranging from 1/2 sec
to 30 sec. I/O under System 360/370 is under the overall control of the CP, which has instructions for starting
channel programs (SIO), testing their current operational status (TIO), and aborting them (IllO).
The Start I/O instruction (SIO) initiates the execution of the first command of a channel program. Before the CP
executes an SIO, it must first set up a pointer called the Channel Address Word (CAW). This word points to the
first Channel Command Word (CCW) of the channel program to be executed. The CAW is at a fixed core location
and, since its contents are required by a channel only during SIO execution, only one is required to service all
channels. The SIO instruction itself identifies the channel and device for which the channel program is to be executed. A condition code, returned by the channel, indicates whether or not the channel was able to select the
addressed device, and, if so, whether or not the device accepted the command. The execution of an SIO instruction is not complete until the condition code is available. Successful completion of an SIO execution does not
guarantee that a channel program (or indeed even the first command of the program) will be completed successfully, only that the program was started successfully.
Because the IBM diagnostics utilize these codes to inform the programmer of malfunctions, a discussion of their
meanings is in order. These condition codes are set in the 360/370 and can be interrogated by the program in a
similar fashion to the Branch On Condition instruction in the PDP-II. There are four sets of condition codes
expressed by two bits in the 360/370 Program Status Word. Their meanings for an SIO instruction are as follows:

o = The device that was selected has accepted and is now beginning to process. Does not say that the
process was completed.
The device that was selected did not accept. Does not say why. Implies that the device was there
and did not want to start..
2

The channel or sub channel was busy. Occurs on an SEL channel if one device has been started, is
still active, and a start I/O is issued to that or another device. On an MPX channel, occurs if two
SIOs are issued in a row to the same device.

No CU recognized the device address that was put on the bus. The assumption is that the CU is
off-line. Note that if the device was not there, the I/O would not be accepted and a condition
code I would be indicated.

5-6

Between SIO executions, all channel-to-CP communication is done through the Channel Status Word (CSW) and
via I/O interruptions. An I/O interrupt signifies that the channel in question has new information to store in the
CSW. Such information typically contains channel status, device status, the address of the last CSW executed, and
the residual data count (if appropriate for the last operation). The usual function ofI/O interrupts is to indicate
termination of a channel program, either because the last chained CCW has been executed, or because an exceptional condition has caused the I/O program to be aborted.
In addition to using the I/O interrupt facility, the CP can obtain information from channels through the "Test
I/O" (TIO) instruction. This instruction appears on the interface as a no command. Its function is to test control units and devices and to relieve them of status conditions that might otherwise cause an I/O interrupt. A
TIO can also be issued by the channel itself under some circumstances where it is desirable to obtain status
quickly. As with all instructions, there are four sets of condition codes expressed as follows:

The path to the device is free.
The device attempted an I/O interrupt because of the completion of its activity but was prevented
from doing so because the CH was disabled. Relieves that interrupt pending condition without
actually causing an I/O interrupt. This is similar to a PDP-II System turning off INTEN and spinning
on the DONE flag, or raising the priority to 7.

2 = The CH was busy.
3 = The CD is off-line. Did not recognize the address selection of the no.
A "Halt I/O" (RIO) instruction is used to terminate I/O activity for a particular device. This appears on the
interface as a special signal sequence called "Interface Disconnect". Depending on the device and the current
activity on the interface, the channel can first be required to select the affected device before it can execute the
disconnect sequence. If the channel is operating in burst mode at the time HIO is executed, Interface Disconnect
is signaled to the currently active device, regardless of which device was actually addressed by HIO. This instruction is typically used to clear channels for higher priority operations and to terminate operations involving nonpassive devices, such as communication devices, for which the CP program cannot determine a prior termination
condition.
The four sets of condition codes associated with an HIO are as follows:

o = The device has been signaled to stop.
1
2
3

An I/O interrupt for that device is pending.
A burst mode transfer was stopped.
The CD is off-line.
NOTE
A condition 2 instead of condition 0 will be returned on an
HIO when it terminates a transfer on either an SEL or MPX
channel in burst mode.

The command structure of 360 channels provides five basic I/O commands. These are Read, Read Backwards,
Write, Sense, and Control. Variations on the basic commands are obtained by micro coding command-byte bits
that are not used by the basic commands. The command-byte formats for the basic commands (and for test I/O
which looks like a command to the external device) are given in Table 5-1. The bits marked "m" are the command
modifiers. For basic operations, they are O. For other operations, they are microcoded according to the requirements of the particular application.

5-7

Table 5-1
I/O Command Byte Formats
Command Name
Read
Read Backward
Write
Sense
Control
Test I/O

Bit Number
2
5
4
3

0
m
m
m
m
m
0

m
m
m
m
m
0

m
m
0
m
0

m
m
m
0

0
0
0
1
0

7
0
0
0
1
0

The I/O command Read transfers data from the device to 360/370 core, where it is stored in ascending byte
locations starting at the address contained in the CCW for the read command.
Read Backward is similar to Read except that data is stored in descending locations from the starting address.
The Write command transfers data from ascending core locations to the device starting with the address contained
in the CCW.
Sense is essentially a "read" command except that the data transferred pertains to exceptional conditions in the
device and/or CU. The sense bytes identify, in detail, what caused the CU to present a unit check indication.
The Control command transfers control data to the device. The modifier bits can provide enough data to cover
all control functions, or the Control command can send one or more bytes providing any additional information
required. For example, a magnetic tape rewind can be signaled through the modifier bits alone, while a communications device "control" command, such as a 2701 Set Mode command, can require two or more bytes of control information to be transmitted. A control command with all modifier bits set to 0 is considered an I/O
NO OP command.
A channel has two means of establishing logical connection with a device. It can address a device directly or it
can scan (poll) for devices requiring service. Addressing is the start of the initial selection sequence (ISS) for a
command. It can also occur due to the execution of a TIO or HIO instruction. It is achieved by first sending the
address to all devices common to the bus, and then requesting the addressed device to acknowledge. Polling, on
the other hand, is performed in response to a request from one or more currently active devices. Since RequestIn is a common bus line, the channel can only determine which device is requesting by polling all devices on the
channel. This is accomplished by raising its selection lines, Select-Out. Unlike the other channel interface lines,
Select-Out is a serial line. The fact that it is serial allows allocation of service priorities and avoids contention
conflicts. With this agreement, each CU, in turn, has a chance to obtain selection. If it does not require service,
it can propagate Select-Out to the next CU down the chain. Thus, only one CU at a time can make a selection
decision. CUs which are closer to the channel on Select-Out are consequently selected preferentially and have
higher priority than CUs logically further away from the CR.
If Request-In is up, the channel will normally conduct a polling operation before starting an ISS. This gives cur-

rently active devices preference for service over the initiation of activity for some currently idle device. This
reduces the chance of overruns or loss of synchronization for the active devices.

5-8

In order to obtain selection during a polling sequence, the requesting CU blocks the propagation of Select-Out and
executes a Control Unit Initiated (CUI) selection sequence. The cm sequence terminates polling during its execution; requesting CUs further down the selection chain do not see Select-Out until the channel resumes polling
after that CUI sequence is complete.
As shown in Figure 5-4, the physical interface consists of 31 lines (16 Out and 15 In). Each line group consists
of a 9-bit data-pius-parity bus, a number of tag lines that are used to identify what is being presented on the bus,
and a number of selection control lines. The functions of these lines are summarized in Table 5-2. Three additional lines are used for device metering but are not included in the table.

IBM 360/370 CHANNEL

DX 11-8

I
I
I
I
160UT LINES

I
I
I
#15

I
I
I
15 IN LINES

I
I
I
#15

NOTE,
The 16 out lines and 15 in lines are just what the DX11-B uses. There

lines that are daisy-chained through the DX1t-8 but not used.

are other
11-1255

Figure 5-4 Channel/DXII-B Interface

Operational-Out is normally up for an active channel. The other interface lines, in general, are significant only
when this line is up. It is dropped only during certain reset sequences and when the channel is deactivated for
diagnostic purposes.
Hold-Out is used to condition Select-Out and is functionally identical to Select-Out at the channel. Select-Out,
however, is a serial line while Hold-Out is distributed to all CUs in parallel. As such, Hold-Out is not subject to
the propagation delays inherent in Select-Out. The fall of Hold-Out indicates the impending fall of Select-Out and
is used to purge the select line chain of Select-Out directly, thereby eliminating the delays that would be entailed
in propagating the trailing edge of Select-Out through the selection chain.

5-9

Table 5-2
Channel/DXII-B Interface Lines
Name
Bus-Out
Bus-In
Operational-Out
Hold-Out
Select-Out
Suppress-Out
Operational-In
Select-In
Request-In
Address-Out
Command-Out
Service-Out
Address-In
Status-In
Service-In

Function
Output data bus: 8 data bits + I parity bit.
Input data bus: 8 data bits + I parity bit.

Selection control lines, used to select, scan, or disconnect devices.

Tag lines, used to identify data being presented on bus lines, to interlock the data transfer, and to signal special interface sequences.

Select-Out is the interface select line. It is used to indicate that addressed or polled devices can respond. The
selected device remains selected at least as long as Select-Out is up. This allows Select-Out to cause channel-forced
burst from devices attached to SEL channels. The first CU on a 370 Channel always has it's Select-Out line asserted.
Suppress-Out is a line used by the channel (when it cannot immediately handle an interrupt status) to temporarily
suppress the presentation of data and status, and to signal certain reset sequences.
Operational-In is a signal from the CU that indicates either that it recognizes the address on Bus-Out during an
attempted ISS, and is available, or that it desires service during a polling sequence. In general, in-tag and data
lines are significant only while Operational-In is up.
Select-In is a sign~al returned to the CH by the last CU in the selection loop (Figure 5-5). The rise of Select-In at
the channel indicates that no CU recognized the address on Bus-Out during an attempted ISS, or no device
required service during a polling sequence. Every CU in the chain propagated Select-Out.
Request-In is raised by a CU to indicate the need to transfer data or status. Request-In causes the CH to perform
a polling sequence as soon as feasible. Request-In is normally dropped when the CU obtains selection, i.e., when
it raises Operational-In.
Address-Out is normally used to indicate the presence of a device address on Bus-Out during an attempted ISS.
It is also used during the Interface Disconnect Sequence.
Command-Out is normally used to indicate the presence of a command byte on Bus-Out. It is also used either as
an "I/O Stop" or as "Stack Status" indicator.
Service-Out is used as a data-interlock line. It indicates data on Bus-Out during output operation, and acknowledges the data on Bus-In during input operations.
Address-In is used to indicate the presence of a device address on Bus-In during an ISS or polling sequence.
Status-In is used to indicate the presence of status information on Bus-In.
Service-In is the input analog of Service-Out. It indicates data on Bus-In during input operations and requests
data on Bus-Out during output operations.
5-10

*Dotled lines show propagation
of select out by CU~ not being
addressed or not requiring
service.
**SELO jumpers to SELl at last
CU in chain.

11-1256

Figure 5-5 Channel Selection Chain

These are the interfacing signals between the IBM Channel and the DXll-B Control Unit. All "Out" signals are
generated by the channel and issued to the DXll, while the DXll must respond to the channel by generating all
"In" signals. The timing and relationship of these signals, one with the other, have been explained briefly. For a
detailed discussion of their interlocking relationships, refer to Paragraph 5.4 in which the various sequences of
operation are discussed.
5.3.2 IBM Control Operation
The DX1l-B can present one of three states to the channel. These are available, busy, or not operational. The
DX11 is defined as available if it can respond to a channel-initiated selection sequence (CHIS) addressed to it,
decode the command presented by the channel, and present appropriate status to the channel. The DX1l is busy
if it cannot accept the CHIS because a previous operation is still underway, or because status from a previous
operation is available in the DX1l but has not yet been accepted by the channel. The DX11 is not operational if
it does not respond in any way to a CHIS. This can be due to either a power down in the DX11, or if it is powered
up and off-line.
The DX1l-B can operate with either an SEL or MPX channel. It can be attached to a Block Multiplexer Channel
as well. The DXl1-B can operate in one or more of several possible modes that are commonly designated as
shared, unshared, burst, and byte by IBM. A more descriptive delineation defines these modes as single-thread
(shared), multi-thread (unshared), and burst ..
In burst mode, once selected by an ISS, the DX11 will force Operational-In to remain up until Channel-End is
presented, regardless of whether Select-Out remains up during this period or not.
In single-thread mode, when connected to an SEL channel, the DX11-B operates in channel-forced burst mode and
is operationally indistinguishable from a burst mode control unit. When connected to an MPX channel, however,
the DX11 operates in either byte or burst data mode as determined by program selection. When in byte mode,
it must deselect and res elect periodically to maintain the byte mode operation. It can service activity for only
one attached device at a time and, therefore, is busy to selections addressed to all other devices it services from
the time one device is selected (via an ISS) until Channel-End is presented for that device. Selections during this
period receive the Fast CU Busy sequence described in Paragraph 5.4.1.4.
NOTE
The use of the term "device" in these discussions is intended
to be synonomous with the term "360 Device Address".

5-11

In multi-thread mode, the DXII normally operates only with an MPX channel and only in byte mode. It will
accept a number of selections and maintain several active devices at once. While a CU Busy sequence can be executed, it is usually the result of a transient condition and thus the "busy" and "status modifier" status is accompanied by Control-Unit-End, causing the CP to immediately retry the selection.
The type of channel to which the DXII-B is to be attached is a consideration of the emulator software. The
DXII-B hardware makes no distinction.
5.3.3 Unibus Interface Operation
The DXII-B services the PDP-II Unibus with standard DEC modules which are, in turn, controlled by the DXII-B
through simple synchronized flip-flops. The interrupt is controlled by a DONE indication and INTEN. The NPR
is controlled by a direction flip-flop (NPRT) and by a flip-flop which the DXII-B turns on to request (NPRX)
and the Unibus turns off when complete.
The NPR and BR operation of the DXII-B with the PDP-II Unibus is standard and will not be discussed in great
detail here. The reader is referred to the various PDP-II interface manuals for more information.
5.3.4 PDP-ll Control Operation
The function of the PDP-II Control is to allow the DXII-B to operate as a conventional device on the Unibus.
Since NPR and BR operations are adequately documented in the PDP-II Handbook and PDP-II Unibus Interface
Manual, only their use will be defined in this paragraph.
During selection sequences, NPRs are used in the fetching of ISS status and in all data transfer operations. The
slave address and data direction are controlled by the synchronization section current state of theDXII-B.
BR sequences are initiated to transmit command information (i.e., the command byte) and the IBM device
address to the PDP-II during the ISS and to signal exceptional conditions (e.g., reset sequences) on the IBM
interface.
All NPR and BR sequences are executed under control of the synchronization section. See discussion in the
control flows discussion in Paragraph 5.4.2.3.
During data transfer sequences, the DXII-B maintains a data address and data count. Data transfers are made
continuously using NPR sequences (not back-to-back) until either the count is exhausted or the IBM interface
indicates I/O Stop, at which time the BR facility and device status words are used to notify the PDP-II of the
completion.
The DXII-B maintains information for each emulated device. There are three types of status involved: a) the
status byte presented to the channel, b) the status (condition) of a particular device, and c) the status of the
DXII-B.
The DXII-B status is always available to the PDP-II via the special register within the DXII-B called the DXCS
(Control Unit Status). This register is loaded by the service routine.
Device status is generated during an ISS and is kept in the DXII-B DXDS Register until stored in a circular buffer
list in PDP-II memory called the Tumble Table (TT), where it is kept for use by the program. The TT contains
information concerning event notification. A single entry consists of DXDS (Device Status Word) and DXCA
(Command and Address Word), also located within the DXII-B. The program must zero the entry after use. All
entries are guaranteed to be nonzero.

5-12

The channel status is obtained from either of two tables held in PDP-II core. These are a word table (l6-bits
wide) called the Status Pointer Words (SPW) and the Device Status Table (DST), a byte table 8-bits wide. A
single SPW exists for each device on the DXII-B.
5.3.5 Central Control Operation
Most DXII-B hardware is designed into a matrix of time states and logic phases. Each logical operation, gating,
or enabling condition is valid only during particular time states; i.e., if all conditions are met to perform an opera
tion then that operation will actually take place when the appropriate time pulse occurs.
A phase is an arbitrary but logical subdivision of the sequences which the DXII-B performs. Each phase has
both a name and a number between 0 and 7 with the name describing the main operational function or functions
performed during that phase. The sequence of phases entered varies depending on the function or operation to
be performed.
A time state, on the other hand, is a fixed division of time that is generated by a free-running clock. There are
two time states (1 and 2) and these states pertain to all phases .. The DXII-B can process from Phase X/Time
State I through Time State 2 of that same phase to Time State I of the next phase with no delays; but it will
more often remain in some phase and step regularly between the two time states of that phase until the proper
conditions are met (in Time State 2 (TS2)) to enter the next phase called for.
The use of phase-controlled logic in the DXII-B simplifies the control and results in a better understanding of
the sequences involved. Optimum subdivision also results in logic savings when a phase can be used in several
different types of sequences.
Drawing C-FD-DXII-B-04, Sheet I is a major phase diagram showing the transitions made by the DXII-B logic.
On that drawing, the phase number is indicated in the upper right-hand corner of each functional block.
Phase 0, the Idle or Requesting phase, is used for the following functions:
a.

Selection Bypassed
I.
2.

Selection Sequences
I.
2.
3.

ISS in Progress
Polling Sequence
Status Pending

Asynchronous Operations
I.
2.

Propagate Select-Out
Fast CU Busy Sequence

System Reset
PDP-II Interrupt Granted

Programmed Interactions
I.
2.

DXII Reset
Request Made

Phase I, the Address Response phase, uses the address from the BUSO (Bus-Out) flip-flops and the Offset Register
CCUOR) to obtain the Status Pointer Word (SPW) from PDP-II core. The information thus obtained is used to
set certain control flip-flops. Control of the DXII-B is then transferred to Phase 2.

5-13

Phase 2, the Status Preparation phase, is used to prepare for status presentation or, if a CU request has been
granted, to transfer to the appropriate phase (3,5, or 6) from which the DXII-B proceeds with the request. If a
command h.tS been accepted, then the Device Status Table (DST) is accessed. If the command was rejected for
some reason (e.g., bad parity), then the DST is bypassed. During an ISS, Phase 3 is used next. If any IBM Reset
condition is issued during Phase 2, then Phase 4 is used next.
Phase 3 is the Status Presentation phase. The logic controlled by TS I of this phase governs the transfer of information into BUSI (Bus-In) flip-flops and then onto the Bus-In lines. The logic of TS2 of this phase makes the
appropriate responses, depending upon whether status was accepted or stacked.
Phase 4, or Mark phase, stores the device information resulting from the I/O interface transaction into a tumble
table of data in PDP-II core. The information consists of the DXDS (two bytes of device status indicators) and
the CUCR (command byte) plus the CUAR (address byte).
Phase 5, the Input phase, governs the transfer of information from the channel into the DX11-B. It contains two
separate logic paths which run independently. One path synchronizes NPR word transfers to the PDP-II with the
transfer of data bytes from the I/O interface. The other path controls the signals required by the channel-to-DX11
interaction.
Phase 6 is the Output phase. This phase is similar to the Input phase except that data is transferred out from the
DX11-B to the channel.
Phase 7 is the Done phase. It synchronizes the termination of the signal sequences and makes the appropriate
response either to an SEL or MPX channel, depending on which is attached to the DXII-B.
There are certain phase-independent operations performed by the DX11-B. These operations synchronize a) the
various signals that could occur either independently of the DX11-B clock and/or during any phase, or b) flip-flop
changes that must be synchronized with the DXII-B clock.
5.3.6 Channel Simulator Operation
The Channel Simulator comprises built-in diagnostic hardware which is used in conjunction with a PDP-II diagnostic program to test all DX1I-B responses as seen and simulated by the channel. These are the programmable
registers DXMO and DXMI. These are 16-bit writable registers to give off-line checks. This block is shown alone
in Figure 5-3, as it normally does not function as part of the DX11-B but is put into operation by relocation of
channel bus and tag cables to connectors associated with these registers.
The feature includes a set of test receivers and drivers so that tests can be made in on-line mode to check the
entire DXII-B hardware without the need for the IBM system with which it normally operates. Channel tags in
360 sequence can be simulated by this hardware, as well as all control signals and data bits.
In off-line mode, all logic except the 360/370 bus receivers and drivers are tested.
5.4 SEQUENCES OF OPERATION
As previously explained, the DXI1-B is a static piece of hardware when divorced from its specially designed software. It will do very little without program intervention at almost every step of the way from start of an operation
to the conclusion of that operation's execution. As such, the sequences of operation are of prime importance in
understanding the functioning of the hardware. There are many different sequences depending on both the operation to be performed and the way that the'programmer wishes to perfrom them; often times, many sequences
occur simultaneously and independently in the IBM interface, the DXI1-B itself, and in the PDP-II interface.
There are timing constraints imposed by both the 360/370 channel and the PDP-II System; in most cases, the
time limitations must be satisfied for all three portions of the operational system.
5-14

In this paragraph, the sequences with their attendant timing diagrams are divided into two main categories:
a) those on the IBM interface, and b) those in the DXII-B, including the interaction with normal PDP-II interchange.
5.4.1 IBM Sequences
In dealing with the IBM channel, the DXII-B takes part in several sequences of operation. These involve
a) initiation of activity either by the channel or by the DXII-B, b) the transfer of data either to or from the
360/370, c) presentation of status to the channel by the DXII-B, and d) reset sequences from the channel to
the DXII-B.
In these subparagraphs, detailed descriptions of sequences are arranged in narrative order, in an attempt to give
a feel for overall operation. The particulars pertain primarily to operation with an SEL channel since operation
with an MPX channel is very similar. Following this, a subparagraph is devoted to the specific differences in the
operation of the DXII-B with an MPX channel. Finally, IBM sequences are summarized as to contrasting conditions to give a complete understanding of this very important part of DXII-B operation.
5.4.1.1 Selector Channel-Initiated Sequences (CHI) - In the execution of a typical Channel Command Word
(CCW) involving data transfer such as read, write or sense, the channel, in executing a CCW, first selects the
device, then performs the data transfer, and finally terminates the CCW by going through an ending status
sequence.
The sequence for selecting the device begins with the raising of Operational-Out with the 8-bit device address
being placed on the bus by the channel, and with the channel raising Address-Out (Figure 5-6). After this, the
channel raises Select-Out and Hold-Out (the latter not shown on the diagram).
NOTE
In these figures the arrows denote sequence only and are not
intended to imply preconditions.
At this point each CU on the bus, in turn, propagates Select-Out after comparing the device address with its range
of device addresses and finding no comparison. This propagation continues until the CD (e.g., the DXII-B) that
is being addressed recognizes the address and raises Operational-In. This prevents any further propagation of
Select-Out to any CUs further down the bus and allows the channel to drop the information on Bus-Out, and to
drop Address-Out.
NOTE
The latter part of this sequence is somewhat different from all
other sequences since normally bus information must remain
on the bus as long as the qualifier tag is up.
When the channel drops Address-Out, the DXII-B echoes the device address on Bus-In and raises Address-In.
NOTE
Bus-Out (BUSO) refers to a group of 9 lines comprising 8 data
bit lines and 1 parity bit line.
When the device address is echoed on Bus-In by the DXII-B, the channel puts the op code portion of the CCW
on Bus-Out and raises Command-Out. When Command-Out rises, the DXll is permitted to drop Address-In, at
which time it waits for Command-Out from the channel to fall.

5-15

~------------------------------------------~~
OPLO

~--------------------------------------~~
SELO

--+---1-1

ADRO _-+-_>'-'

~----------------------------------~~

CMDO-+_ _4-_ _-+_~-4_---~

~------------------~~

SRVO~~-~--+--~-~---+_-~-~-~----~

BUSO

~--+---~----~------I~

~~--+---~--~--~~----~----~--~~
OPLI _ _ _ _ _ _---1

ADRI _ _ _ _ _ _ _

~-~

L-------4-~----~----~--~~

STAI _ _ _ _ _ _~~-_4---~--~------~-~

'-------I~

BUSI _ _ _ _ _ _ _ _---'
11·12.57

Figure 5-6 Initial Selection Sequence (ISS) Selector Channel Initiated

At this point, the DXII-B can accept or reject the command on the bus. If it accepts it, the DXII presents a 0
status byte on Bus-In and raises Status-In.
The channel acknowledges receipt of that status by raising Service-Out which, in turn, allows the DXII-B to drop
Status-In and take the status byte off of Bus-In. When the channel drops Service-Out the DXII-B is officially
selected and the selection sequence is ended. The command is now stored in the DXII-B along with the address
of the device commanded ("ordered" in IBM terminology), and the DXII can now proceed to do what is necessary to get that device going, including interrupting the PDP-II program so that the data transfers can start.
The ensuing data transfer sequence is shown in Figure 5-7. Assuming that the command,just stored as a result of
an ISS, was a Read command, the DXII-B must then put data on Bus-In.
NOTE
Although the convention has been established to designate
"read" and "write" operations with respect to IBM, and comparable "out" and "in" operations for PDP-II, the Bus designations must remain IN for an IBM read and OUT for an IBM
write.

5-16

OPLI

SELO

I
I
I
I

STAI--1~I----++--4-~-4----~~-4---4-----++-~~~------~~
I

I
BUSI~
CHEND S DVEND
I~'-----------DATA

TRANSFER SEQUENCE------------.~~I.~---ENDING
(READ)
I

SEQUENCE~

I
11- 1258

Figure 5-7a Data (Read) Transfer and Ending Sequences with Selector Channel

-4F------.--~---------------.-------------,
OPLI

I
I
I
I

I-

S RV 0 - - \ ...
1 _-.'-=I

--\~I_4--~~T_~~--_r~--+-_+~_r~--_T----4_0
SELO

SRVI --\1

BUSO

-4 ...1_ _-'
I
I

-------L--__------------------------~-----------J

BUSI--1~I--__

lONE DATA
1
_TRANSFER _
CYCLE

CHEND

I..,.,------------DATA TRANSFER SEQUENCE-----------~I-ENDING SEQUENCE _ _I
I
(WRITE)
I
I
11 - 1259

Figure 5-7b Data (Write) Transfer and Ending Sequences with Selector Channel

5-17

With data on Bus-In, the DXII-B raises Service-In. The channel acknowledges the receipt of that data by raising
Service-Out. At that time the DXll drops Service-In, takes the data off of Bus-In, and the channel drops ServiceOut. This constitutes just one cycle in a data transfer sequence with the same events repeating for each byte of
data transferred. Notice that Operational-In remains up throughout the recurring period, as does OperationalOut, Hold-Out, and Select-Out. The DXII-B remains on the channel during this period until it has transferred all
the data it has to transfer. If the channel runs out of storage space first, an 10-Stop sequence is initiated. This
special sequence is discussed later.
Assuming a normal transfer with no 10-Stop, when the DXII-B has transferred all its data, it ends the transfer
sequence by entering an Ending Sequence. This is indicated to the channel by the DXll presenting ending status
instead of data on the Bus-In and then raising Status-In. If there were no errors during the transfer, that ending
status will consist of Channel-End (CHEND) and Device-End (DEVEND). The channel accepts that status in the
same way that it accepts data, by dropping Select-Out and raising Service-Out. The DXll responds by dropping
Status-In and Operational-In (the DXll cannot drop Operational-In until Select-Out is down), and the channel
comes back with a drop of Service-Out. This concludes the sequence, the DXII-B is off the channel and the tags
are down.
Figure 5-7b illustrates the sequence for a write in which the channel puts the data on Bus-Out. As with a Read
command, the DXll raises Service-In and waits for Service-Out to rise. The DXll then strobes the data on BusOut and acknowledges receipt by dropping Service-In. This cycle repeats until the data transfer is complete. At
this point, the DXII places status on Bus-In and raises Status-In and proceeds with a normal ending sequence.
Note again that an NPR is executed for every two
bytes of data and to retrieve initial ISS status. A program interrupt is generated at the end of the ISS, at
the end of the complete data transfer, and at the end
of every status cycle.
Considering the eventuality, mentioned earlier, that
the CH might run out of storage area because the
size of the buffer (360) was smaller than the amount
of PDP-II data to be transferred to the CH, an additional signal comes in to play, as shown in Figure 5-8.
In this case, the CH, instead of acknowledging the
receipt of the data by raising Service-Out, raises
Command-Out instead. This indicates to the DXII-B
that the CH did not accept the data that was presented on Bus-In, and that it should not raise ServiceIn again. It also requires the DXll to raise Status-In
as its next In-Tag to end the sequence. The status is
presented on Bus-In. Raising Status-In causes the
channel to drop Select-Out and to raise Service-Out.
When the DXll sees this, it drops Operational-In and
Status-In; the channel then drops Service-Out. The
sequence is ended and the proper interrupts have
been made along the way to the PDP-II program.

OPLI

SRVO

SELO

STAI __

________________

CM DO --+--------,f-I

SRVI ----~--_F_..J

BUSI ________...J
I

I
I

I
I
I/O

STOP

11-1260

Figure 5-8 I/O Stop Sequence on Selector Channel

If command chaining is indicated in the CCW, the DXII-B is required to do nothing but wait for the next selection
to occur immediately. This condition is indicated to the DXll, when ending status is presented, by the channel
raising both Suppress-Out and Service-Out.
5-18

In this sequence, it may be possible that the channel cannot accept status when the DXII-B wishes to present it
because it has no storage available into which to put it. In this event, the DXII must be prepared to "stack" the
status. This sequence is shown briefly in Figure 5-9, in which the DXll
is on the channel with Select-Out and Operational-In both up. When the
DXII-B places the status byte on Bus-In and raises Status-In, the chan-

INDICATES
STACK ~TATUS

nel immediately raises Comm·and-Out and drops Select-Out. This indi-

I
I

cates to the DXll that it must get off the channel by dropping Status-In,
by taking the status off of Bus-In, and by dropping Operational-In. The
channel then drops Command-Out and the sequence ends with the
DXII-B not having presented status for the transfer completed.
The above conditions represent unfinished business for the DXll-B. It
has the status it needs to present, and, in order to present it, the DXll-B
must get back on the channel. If the DXII at this time were to arbitrarily raise Status-In again, the channel would have no way of knowing the
source. The sequence for finishing this condition is explained in Paragraph 5.4.1.2 in which a Control Unit Initiated Sequence (CUIS) is
described.
In the sequences just discussed, where no data transfer results as part

SELO

CMD 0 ---\-F-'

OPLI

STAI

BUSI

Figure 5-9
Stack Status Sequence

of the ISS, status is generated as a function of the command received
unless status was already pending for that device. If no status was
pending but parity on the command was bad, then Unit Check (UCHECK) is presented to reject the command.
The command is also rejected if the addressed device is off-line or if the command is illegal for the particular
device.
When the DXII-B is not operational because it is either powered-down or is powered-up and in off-line state,
Select-Out is propagated automatically: all in-tag, in-control and bus-in functions are logically disconnected from
the channel interface. An attempt by the channel to address the DXII-B in this instance will cause Select-In to
rise (eventually) back at the channel (and via the channel to the CP program), indicating that the DXll is logically
not on the interface.
5.4.1.2 Control Unit Initiated Sequences (CUI) - The DXll-B initiates selection sequences to transfer data to,
request data from, or transfer status to the channel; the latter being the purpose carried over from the previous
paragraph as just one example. A status transfer can arise because emulator status has just become available, or
because a previous status transfer was stacked by the channel, as is the case in this running description. On an
SEL channel, only status is actually transferred by a CUI selection sequence. On an MPX channel, the transfer
can consist of one or more data bytes and/or status bytes.
As shown in Figure 5-10, the DXll-B raises Request-In to execute a CUI. This is a parallel line that indicates to
the channel that some CU on the bus desires to use the channel. The channel, when it is free, responds by raising
Select-Out (and Hold-Out). Select-Out is propagated in the same manner that it was by CHIS, but this time the
DXI1-B does not do an address compare. The receipt of Select-Out is all that is necessary for it to raise

5-19

Operational-In. Now that Operational-In is raised, the DXll can drop Request-In and at this point it puts its
address on Bus-In to identify itself to the channel. When the channel decodes the address, it acknowledges by
dropping Select-Out and raising Command-Out.
NOTE
This is a special use of Command-Out. There is no command
on the bus. In this instance it is used as part of the dialogue
to acknowledge receipt of the initiating address, i.e., that a
polling sequence has been completed.

When the DXII-B sees acknowledgment of its address,
it drops Address-In and takes its address off of Bus-In.
Since the channel will have dropped Command-Out,
and Operational-In is up, the DXII-B is now on the
channel and the sequence is complete.
Continuing with the example started in the previous
paragraph, now that the DXII is back on the channel, it can attempt to present status once again. There
is no guarantee that the channel will accept it, particularly if it still has no room. Since there is no harm in
trying, the DXII-B proceeds as it did before to present
status by putting the status byte on Bus-In and raising
Status-In. Assuming that the channel accepts the status
this time, it raises Service-Out instead of CommandOut, the DXll drops Operational-In, and the sequence
terminates normally.

REOI

SElO _ _- ,

OPlI _ _ _ _-'

BUSI ______

______

ADRI ________________

CMDO ______________________- - d
r
I

DX11-B IS
ON THE CH
I! -1262

Figure 5-10 CUI Sequence to Selector Channel
5.4.1.3 Reset Sequences - There are three reset sequences initiated by the channel to the DXII-B. They
are: a) System Reset, b) Selective Reset, and c) Interface Disconnect.
An interface disconnect is an asynchronous event that
can occur at any time as a result of the 360 program
executing an HIO instruction. An HIO can occur under
three possible conditions: a) when the device is idle, so
consequently the DXII-B is off the channel and
Operational-In is down; b) when the DXII-B is on the
channel but is currently between sequences with
Operational-In and Select-Out both up, but all other
tags are down; or c) during a data transfer with SelectOut and Operational-In both up and Service-In is raised.
A Halt-IO (RIO) is defined as a static condition in which
Select-Out=O and Address-Out= 1.

The sequence for case a is shown in Figure 5-11. The
DXII-B is off the channel presently idle. When the program issues an HIO, the channel must first select the

5-20

BUSO

ADRO

SELO _ _--'

OPLI~

_ _ _....

BUSI _ _ _ _ _ _ _-'

ADRI ______________

~6l!sec
I

11-12.63

Figure 5-11 Interface Disconnect Sequence
to CU Idle off the Channel

DXll in order to tell it to deselect. This is done by putting the DXll address on Bus-Out, then raising AddressOut and Select-Out. Select-Out is propagated until seen and recognized by the DXll-B. At that point, the DXll
raises Operational-In which drops Address-Out. Then the DXll puts its address on Bus-In and raises Address-In,
which causes Select-Out to fall and Address-Out to rise. With the conditions for interface disconnect now met,
the DXll-B has 6 f.1.s to take everything off the bus and drop Operational-In. This 6 f.1.s limitation to get off the
bus is extremely important in dealing with the 360/370, particularly when operating with an MPX channel, which
will hang if the time limit is not met and will, in turn, hang the whole system. The DXll-B is equipped with complex logic to ensure that the 6 f.1.s limit is met.
The sequence for case b is shown in Figure 5-12. The DXII-B is on the channel presently idle, as it would be
between bytes of a data transfer, or if it had just been selected and had not begun transferring data as yet, or if
all the data had been transferred and it was presently generating status that had not as yet been presented. Both Select-Out
INFDSC
I
and Operational-In are up when the program issues an RIO.
I
The channel drops Select-Out at this point, which causes the
I
DXll to do nothing, then raises Address-Out. This is the interI
I
face disconnect combination. The DXll-B then drops
Operational-In and Address-Out drops. This concludes the
sequence and the 6 f.1.S condition prevails as before.
I

SELO~

ADRO~

The sequence for case c is shown in Figure 5-13. The DX1I-B
is on the channel performing a data transfer when the program
issues an RIO. Operational-In and Select-Out are both up, and
the DXll raises Service-In. Instead of responding with ServiceOut or Command-Out, the channel drops Select-Out and raises
Address-Out, creating the conditions for an interface disconnect. Seeing this, the DXll-B drops both Service-In and
Operational-In and the sequence is complete.
Note that in these cases, once again IBM uses a tag for a purpose other than what its mnemonic would indicate. As with
Command-Out in the CUI sequence, Address-Out is used
here, with no address on the bus, to combine with SelectOut in creating an interface disconnect.
In summary, on an interface disconnect from the channel,
the DXll-B removes all signals to the 360/370 bus. The
DXll notifies the emulator of the condition; subsequent
DXll actions are a function of the emulator.

om-----lL
I

:""-6Asec
I

1\-1264

Figure 5-12 Interface Disconnect Sequence
to CU Idle on the Channel

INFDSC
I

I
I

AD RO ------t'-l

SELO

OPLI

SRVI _ _---'
I

Selective Reset is indicated when Operational-In is down
and Suppress-Out is up when the DXll-B is concurrently
operational with the channel. When these conditions exist,
the DXll drops all in-tags and notifies the emulator of the
condition. Selective Reset affects only the currently active
device.
System Reset is indicated when Operational-Out and
Suppress-Out are both down concurrently. The emulator is

5-21

SRVO _ _ _ _ _ _ __

CMDO _ _ _ _ _ _ __
11-1265

Figure 5-13 Interface Disconnect Sequence
to CU Active on the Channel

notified of the condition. The emulator clears all indicators anCl registers in the IBM Control Section, except the
CU Busy indicator, which is set. The DXll must drop all in-tags when system reset is indicated. Subsequent
DXll actions are a function of the emulator.
5.4.1.4 Multiplexer Channel Differences - Figures 5-14 through 5-16 illustrate the normal sequences when the
DXII-B is attached to an MPX channel. Comparison of these diagrams with those for an SEL channel will show
the similarities in the sequences. The principle difference is that Select-Out does not remain up during the
sequence. On the SEL channel it is the fact that Select-Out remains up that forces channel forced burst mode.
On that type of channel, Operational-In must remain up while Select-Out is up.

AD R 0 ____---'

ON MPX SELO DOES NOT REMAIN UP .

SELO _ _ _---'

OPLI _ _ _ _ _.....I

ADRI ________________

CMDO ______________________.....I

S~I

______________________________

SRVO ________________________________

BUSO~

ADR

~--------~~~-------------------

BUSI ________________

ADRE

~-----'~~-----11-1266

Figure 5-14 ISS, Multiplexer Channel Initiated

During an ISS on an MPX channel, Select-Out is allowed to fall shortly after Operational-In rises and after
Address-In rises. After an ISS is completed, the DXll drops Operational-In (unless forcing burst mode) because
selection has already taken place, the command is known, and the device address has been identified. When that
device has data to transfer (Figure 5-15), a cms is executed to get back on the channel. Once back, the DXll
has Operational-In up again and can raise Service-In, as required, to transfer the data. When the data is transferred,
the DXll drops Operational-In.
When the DXll has more data to transfer, it goes through another cms. When a data transfer is finally complete,
another cms must be executed in order to present status (on another page) (Figure 5-16).

5-22

OPLI ~_ _---J

ADRI;.....I_ _ _ _ _---.J

CMDO~

_ _ _ _ _ _---J

1
SRVI~

__________

SRVO~I_ _ _ _ _ _ _ _ _ _ _~_~

BUSI

---1

1 - 1_ _ _ _ _

I-

CUIS

I
1

Iol

/ol

I r READ

-I

DATA TRANSFER

11-1267

Figure 5-15 CUIS and Data Transfer, Multiplexer Channel

REQ!

SELO

OPU

ADRI

CMDO

STA!

SRVO

BUS!

______~~~____~r:lL_______
I-

1 4 - - - - CUIS

------14--1

STATUS
J
TRAN'SFER~
11-1268

Figure 5-16 CUIS and Status Transfer, Multiplexer Channel
5-23

The reason for getting on and off in this fashion is to allow interleaving of data from different devices on the
MPX channel. This allows several relatively slow devices to be run simultaneously, each transferring a little data
when they have it ready without holding up any other device on the channel.
There is special logic in the DXll-B to deal with a situation on
an MPX channel (shared CU) when the channel tries to select a
device when that CU is busy servicing another device. Because
the CU is shared, it can only service the first device, but must
respond to the selection for the second. This response is called
a Fast CU Busy sequence.

BUSO

ADRO

Figure 5-17 illustrates this sequence. The selection starts normally since the CU is off the channel, but the difference here
is that the CU is busy and is in between sequences on the channel for the device it is servicing.
The channel begins by placing an address for the second device
on Bus-Out and raising both Address-Out and Select-Out. The
DXll recognizes that the address is within its range of addresses,
so it cannot propagate Select-Out. If it were not busy it would
raise Operational-In, but it cannot accept this selection sequence
so it places a special status on Bus-In (Status Modifier + Busy
and optionally CUEND) and raises Status-In. This indicates

SELO

NOT RAISED
OPL I

---+--f-+--=-

STAI ---H~

BUSI _ _--'

1[-1269

to the channel that the DXll has recognized its address selection but cannot accept it at this time. The channel then drops
its tags to abort the selection and the DXll responds by drop-

Figure 5-17 Fast CU Busy Sequence,
Multiplexer Channel

ping its tags. This completes the sequence.
NOTE
The status CUEND is not presented for 2848 emulation, but
some other emulators will present it along with the other
status.
5.4.1.5 IBM Sequence Summary - There are two types of selection sequences: Channel Initiated (CHI), and
Control Unit Initiated (CUI). On a CHI, when Address-Out rises, the DXll decodes the address being presented
on Bus-Out, including parity, then waits for Select-Out. When Select-Out rises, the DXII response is a function
of the address and parity on Bus-Out, as well as the busy state of the DXll. If the DXll does not recognize the
address, or if the parity is incorrect, the DXll propagates Select-Out. It will continue to do this until the incoming Select-Out falls. If the DXII does recognize the address and if the parity is correct, the DXll blocks propagation of Select-Out and raises Operational-In or Status-In. It then waits for Address-Out to fall.
Status-In is raised if the DXll is operating in Single-Thread mode and a previous selection is still active for
another device address. Busy and Status-Modifier are placed on the bus as status. When Address-Out falls, StatusIn is dropped, ending the sequence. Operational-In is raised if the DXII can accept the selection or if the device
addressed has status pending.
When Address-Out falls, the DXII gates the recognized address on to Bus-In and raises Address-In. When
Command-Out rises in response to Address-In, the DXll decodes the command being presented on Bus-Out, including parity. When the DXII no longer requires the data on Bus-Out, it drops Address-In, removes the address
from Bus-In and waits for Command-Out to fall.

5-24

When Command-Out falls, and the DXII is ready to present initial status, it gates the status byte to Bus-In and
raises Status-In. Status is generated as a function of the command received unless status was already pending for
that device. If no status was pending but parity on the command was bad, then Unit-Check is presented to reject
the command. The command is also rejected if the addressed device is off-line or if the command is illegal for
that particular device.
The channel accepts the presented status by raising Service-Out. Alternatively, the channel can stack the status
(for presentation by the DXll at a later time) by raising Command-Out. In either case, the DXll removes the
status data from Bus-In, drops Status-In, and waits for the out-tag to fall.
When the DXII is not operational because it is powered-down or if it is powered-up and in the off-line state,
Select-Out is propagated automatically. All in-tag, in-control, and bus-in functions are logically disconnected
from the channel interface.
During a CUI, the DXII raises Request-In at the interface unless it is already connected (Operational-In is up).
When the channel initiates a polling sequence by raising Select-Out while Address-Out is down, the rise of SelectOut at the DXII will cause the DXll to raise Operational-In and drop Request-In. The DXII gates the address
to Bus-In, raises Address-In, and waits for Command-Out. The rise of Command-Out signals the acceptance of
the address, the DXll removes the data from Bus-In and drops Address-In, then waits for Command-Out to fall.
The DXII-B response to this depends on the type of transfer. For data output to the channel, the DXII gates
the data byte to Bus-In. For data input or output, DXll raises Service-In. For status, the DXII gates the status
byte to Bus-In and raises Status-In. In all cases, the DXII then waits for an out-tag to rise.
If the channel raises Service-Out, the DXII response depends on the transfer type. For input to the channel, it
removes the data from Bus-In and drops Service-In. For output from the channel, it transfers the data on BusOut to the device, then drops Service-In. For status transfers, the DXll removes the status from Bus-In and
drops Status-In before initiating another action. In all cases, the DXll waits for Service-Out to drop. Unless
Control Unit Forced Burst mode is in effect, the DXll will drop Operational-In after the rise of Service-Out, if
the DXll was transferring a single byte.
If the channel raises Command-Out, the DXll response once again depends on the type of transfer. For input to

the channel, response is as for Service-Out, except that no further data transfers are requested. Status mayor may
not be presented at this time, depending on whether or not Burst mode is in effect and whether status is available
from the emulator. For output, a termination indication is transferred to the emulator, the data on Bus-Out is 0,
but parity is not significant. No further data transfers are requested. For status, if the DXll is operating in
single-thread mode, the DXll places the status in the stacked state and prepares for a new curs under control of
Suppress-Out. If in multi-thread mode, the emulator must recognize the stacked condition and attempt to
re-present the status at a convenient time.
After status presentation, the DXll drops the in-tag and waits for Command-Out to fall. The DXll also drops
Operational-In and, if status has been stacked, the DXll can raise Request-In to prepare for a new CUIS.
Data transfers can be caused by the execution of anyone command but will occur in only one direction across
the interface determined by the emulator at the time it initializes for the first byte transfer. Each device then
retains that direction until Channel-End has been presented. Read-type commands, including Sense, send data to
the channel; while Write commands, including some control commands, input data/rom the channel.
Upon a read command, the DXII gates the data to Bus-In and raises Service-In, waiting then for Service-Out to
rise. When it does, the DXll drops Service-In and removes the data from Bus-In, waiting then for Service-Out to
fall.

5-25

For a Write command, the DXll raises Service-In and waits for Service-Out to rise. When it does, the DXll
strobes the data on Bus-Out. When data is no longer needed, the DXll drops Service-In and waits for Service-Out
to fall.
For both Read and Write commands, Service-Out must be down and Operational-In must be up before Service-In
can rise. The data on Bus-In is loaded 200 ns before the rise of Status-In or Service-In.
The distribution of data cycles relative to other signal sequences is a function of the data transfer mode, either
"burst" or "byte". In CH Forced Burst mode, Select-Out remains up from the ISS through the presentation of
Channel-End. Operational-In remains up until Select-Out falls. Thus, the data cycles are an contiguous and are
bracketed by ISS and ES.
Normally, CU forced burst means that Operational-In is held up from the ISS through the presentation of
Channel-End. Use of burst mode on the MPX channel must be explicitly requested by the emulator before the
CH initiates the associated selection sequence.
The data sequence can be terminated by either the channel or the DXII-B. The channel terminates a data
sequence by raising Command-Out instead of Service-Out during a data cycle. During input, the data on Bus-In is
ignored. During output, no data is presented on Bus-Out. The DXII indicates the termination condition to the
emulator.
The DXll, at the request of the emulator, terminates the operation with the channel by gating status to Bus-In
and raising Status-In. Channel-End is presented at this time along with any other status conditions, including
Device-End if it is available. If Device-End is not presented, a separate status cycle is required to present DeviceEnd when it does become available.
The channel can attempt to suppress data cycles by raising Suppress-Out while Service-Out is up in response to
Service-In. When this occurs, the DXII will not raise Service-In again (except for the first byte after a CUIS)
until Suppress-Out falls. If, however, the device requests a termination at this time, Status-In can be raised,
regardless of the condition of Suppress-Out.
A status cycle can begin only when Operational-In is up and all out-tags are down. The DXll places the status on
Bus-In, raises Status-In, and waits for an out-tag to rise. For a normal status cycle, the channel raises Service-Out
when the status has been read. The DXll drops Status-In and waits for Service-Out to fall. If the channel raises
Command-Out in response to Status-In, the DXII enters the Stacked Status condition.
The occurrence of status cycles relative to other signal sequences is a function of the availability and type of
status involved. However, between the time that the DXll has been selected and the time that either Device-End
or some other status that precludes presentation of Device-End has been accepted by the channel, the DXll is
in the "working" condition. The DXII will execute as many status cycles as are required to clear "working". At
most, this consists of three cycles, as for the typical I/O operation having the following cycles:
a.
b.
c.

An ISS O-status cycle (pre-I/O status, part of the ISS)
An ES Channel-End cycle
An ES Device-End cycle

If the channel indicates Stack-Status, the DXIl-B retains the status and will attempt to present it again by a
cms. This status indication is retained by the DXll for the device in question until subsequently accepted by
the channel.

If the channel raises Suppress-Out before raising Select-Out in response to Request-In, it is requesting the DXII
to suppress status. If Request-In is up to request a data transfer, or the transfer of status that has not been

5-26

stacked, the DXII will proceed with the cms regardless of Suppress-Out. However, if the status has been
stacked, the DXII will respond to Suppress-Status by dropping Request-In. It will not raise Request-In again for
the stacked status until Suppress-Out falls.
Command chaining is indicated when the channel raises Suppress-Out before raising Service-Out in response to
Status-In. The command-chaining indication for the affected device is retained until the device is again selected
by the channel. If command chaining is indicated in response to Channel-End (Device-End not yet available),
the DXII must present Device-End for the affected device before any pending Device-End indications for other
devices unless, in the interim, the DXII is addressed again for another device.
Most status is emulator-provided, either from preset tables (for ISS status) or from status transmitted directly by
the emulator (for ending status). However, under certain circumstances, the DXII itself can affect status and
sense data. These circumstances involve malfunctions or exceptional conditions to which all control units respond
identically. One of these conditions is incorrect parity on Bus-Out during Command-Out. The DXII will present
Unit Check alone during ISS status presentation. During the subsequent Sense operation, the emulator presents
Bus-Qut-Check. Another condition occurs during Control Unit Busy sequences, when the DXII will present
Busy and Status-Modifier in response to the selection attempt. Control Unit End can be presented if enabled by
the device.
If the channel attempts to address a nonexistent device, within the range of device numbers assigned to the DXII,
another example is illustrated as the DXII responds with Unit Check alone during ISS status presentation. During
the subsequent Sense operation, the emulator will present Intervention-Required.
If the DXII attempts to address nonexistent memory, the DXII responds with Unit Check alone during ISS
status presentation and indicates NXM on its indicator panel. During the subsequent Sense operation, the emulator will present Equipment-Check.
NOTE
Appendix C\explains the concepts and symbology used
in the DBX11-B flow diagrams.

5.4.2 DXll-B Sequences
The DXII-B sequences are described in Drawing D-FD-DXII-B-04, Sheets 1 through 9. The symbology used is
unique to this equipment and requires some explanation. The technique used in these flow diagrams is such that
a complete understanding of the entire operation of the DXII-B can be gained by following through the sequences.
Termed "Design Flows", the DXII was designed directly from these flows. Because of their completeness, the
sequence discussions that follow will constitute the bulk of operational discussions. No gate-by-gate discussions
are necessary in this manual.
In this paragraph, the basic data paths are first discussed. This is followed by an explanation of the conventions
used in the flows and a detailed discussion of the design flows.
5.4.2.1 Register Organization - Sheet 9 of Drawing 04 contains the DXII-B data paths. The registers on Sheet 9
are shown in detail on Sheet 8. Refer to that sheet for an explanation of the programmable registers, their
mnemonics, and uses. The conventions used on this diagram are explained in a legend at the bottom of the page.
Note that as part of this legend the symbol for data gate number is given as an arrow intersected by a dotted line
and a number. These numbers refer to a list of signals on the right-hand side of the page. They appear in the
block schematics and on the control flows.
The significance of the mnemonics assigned may not always be obvious, but they do follow a loose convention.
Gate 1, for example, pertains to the signal ARSO. For the most part, these signals were derived by dropping the
prefix from a register (either CU or DX) and combining the last two letters of both registers (or signals) involved
in that transaction. The mnemonic ARSQ means the Control Unit Address Register (CUAR) gets the contents of

5-27

Bus-Out (BUSO). The mnemonic BAAR means the DXll Bus Address Register (DXBA) gets the shifted contents
of the Control Unit Address Register CCUAR). There are exceptions as with the signal for gate number 4 (BIAR),
which means that Bus-In gets the contents of CUAR. When confusion arises as to the meaning of a mnemonic,
refer to Appendix A of this manual, which contains a glossary of signals used in the DXIl-B.
Note that the drawing is divided into three vertical areas segregating the registers and data paths associated with
I13M Control, Central Control, and PDP-II Control. Along the top edge of this sheet are four ellipses which represent external connections to the IBM channel and DXll-B Channel Simulator. The left-hand plug receives the
lines that come from the IBM Channel; this is termed the Bus-Out plug. The Select-Out line of this plug can be
connected to a hardware element (shown in a small ellipse which bypasses the Select-Out signal) either when offline to the channel, or when the PDP-II is powered down. The signals from the Bus-Out plug also go to the
Bus-Out receivers. After the signals have been amplified by the receivers, the clock out signal is sent to the CLKO
location contained in DXMI. The other signals from the receivers are gated by whether or not the DXII is on-line.
If the DXII is on-line, these signals are presented to the inputs of the CONO flip-flops. These flip-flops are
clocked at either T1 or T2. Note that the Select-In tag, which is held in CONI, is cleared if either Hold-Out or
Select-Out fall. The plug data is not clocked into flip-flops but is presented continually as BUSO to both a parity
check and to a comparison circuit. The parity check circuit produces a signal called parity okay (P AROK) which,
when a I, indicates that the proper parity has been seen on Bus-Out. If the BUSO lines contain an address, gate
number I will be activated by the control flow logic, thereby copying the contents of BUSO into the CUAR.
All of the data paths indicated on this diagram are activated by the logic control flows discussed later in
Paragraph 5.4.2.3.
Gates I through 4 are involved in Address Response. Gate number I (ASRO) is hit when an address is being
copied from the BUSO as the CUAR gets the contents of BUSO. Gate number 2 (BAAR) is used to read the
shifted contents of the CUAR into the DXBA in preparation for a fetch of the status pointer word (SPW). At the
same time that gate 2 is activated, gate 3 (BAOR) is used to bring in the contents of the Control Unit Offset
Register (CUOR). Gate number 4 (BIAR), shown at the upper middle of the page, is used to read the contents
of the CUAR and place it on the BUSI lines for presentation to the Bus-In plug.
Gates 5 through 9 are involved in Status PreparatiOn. After the SPW has been fetched, gate number 5 (BAND SO)
is used to read the pointer part of the SPW from the DXND to the left half of the DXBA. At the same time,
gates 6 and 7 are used to copy the command (which is now in the BUSO line) into both the CUCR and the right
half of the DXBA.
Gate 8 (SRNDH) or 9a (SRNDL), which is to the right under CUSR, is used to copy the status byte that is subsequently fetched from the DST into the CUSR. Actually, either gate 8 or gate 9 (SIG3) is used for this purpose;
they are mutually exclusive.
Gates 9 through 15 are used for Status Presentation. Gate 9 (SIG3) can be used to read the status half of the
DXND when it contains the contents of a DST. Status bits that come from the SPW and are presented to BUS!
are available for the program to read via CUSR. All bits that are (or were) presented to Bus-In are available to the
program by reading BUSI. Gate 10 (BISR), located under BUSI, is used to strobe the contents of the status
register into the BUSI flip-flops from which it is represented to the Bus-In plug if on-line and enabled.
Gate 11 (SIG8) is used along with gate 12 (also 8IG8) to read the contents of both the CUeR and the CUAR (the
DXCA) into the DXND in preparation for the first tumble table entry. The second tumble table entry, namely
the DXDS, is gated to the DXND through gates 14 (SIG7) and 15 (also SIG7). Gate 13 (BANX) is used to gate
the shifted contents of the TTNDX into the DXBA to advance the tumble table address. It is shifted left one
position because AOO on the PDP-II Unibus is not used for an address bit but is rather a byte pointer. On the
DXII-B interface, this bit is permanently grounded to force this bit to always be O.
5-28

Gates 16 through 23 are used for Data Transfer. Gate numbers 16 (CRS02) and 17 (SRSO) are used to gate the
second and first bytes of the data into CUCR and CUSR, respectively. Their contents are transmitted to the
DXND by gates 18 (NDCRSR) and 19 (also NDCRSR). Note that gate 18 is identical in function to gate 11
though used for different kinds of information.
The contents of the DXND, on the other hand, are transmitted to the CUCR and CUSR during a PDP-II output
transmission by means of gates 22 (CRSRND) and 23 (also CRSRND). Gates 20 (SISR) and 21 (SICR) enable
that same data, byte by byte, to the BUSI.
Note that BUSO is continually gated to both the parity check and the address comparison. BUSO also goes to
gates 7, 16, 1, 17 and 6. The BUSO data can also be read by means of a PDP-II programmed read. This is indicated by the dark arrow coming out of the BUSO register.
5.4.2.2 Flow Diagram Conventions - Referring to Sheet 1 of this set, a "Flow Diagram Legend" is given containing the various symbols used in the flows. For example, a condition followed by a curved line to which a
right arrow is appended, implies that the condition (or conditions) contained to the left of the curved line will
produce the action to the right of the vertical line to which the arrow points. A condition may be a Boolean
expression containing logical AND, logical OR, the state of the flip-flops, and/or the condition of the signals.
The AND is symbolized by a dot and is given higher precedence than a logical OR operation, which is symbolized
by a + sign. Thus, when the OR of two conditions is itself to be ANDed with other conditions, the entire OR
expression is enclosed in parentheses.
An action or result can be one of four things:

A signal level signified by an equals sign.

A flip-flop transitioned to a particular state indicated by a left arrow meaning the function "gets".

A gating operation in which one byte or a two byte register is given the contents of another byte or
register represented by a double left arrow.

A reset operation in which one byte or register is cleared, shown as a double left arrow followed by a

o.
Certain signals that can change in a completely asynchronous fashion (e.g., the on-line enable switch) or that can
be slightly out of phase with other signal transitions are enclosed in brackets.
When a condition is used as an enabling condition, there are three ways in which it can be portrayed. The first
two have the same meaning:
a.

Vertical line and condition and right arrow starts off an additional line of logic (sometimes used to
indicate parallel sequences splitting off or simply to show additional enabling conditions to perform
some action).

Right arrow and condition in parentheses and another right arrow used when a single condition is
necessary to continue and usually when a symmetric split is made in the flow.

An enabling path broken by a double squiggly line. This means that if the line above the break was

enabled, control will eventually get to this point. To proceed, however, the condition to the left of the
right arrow below the break must be met. This is the full, necessary condition for proceeding. This
provides the method of consolidating signal sequences. The break implies that there could be a wait
until the condition is met. A number appearing in this break indicates approximately how many time
state cycles will be made before the condition is satisfied. A 0 between the break lines means that the
condition is normally met immediately.

5-29

When a logic line terminates at a circle with a letter within it, a page connector is indicated. This is for informational purposes and serves no logical function. The matching circle will be found at the top of another logic path,
either on the same page or another. Occasionally two page connectors will be found connected to a single logic
line. This indicates that either or both paths may have become enabled.
Beneath each reference to a page connector is a short descriptive-comment, in parentheses, on the reason for the
reference. Similar comments at the top of a page describe categories of the logic paths that follow.
A downward pointing triangle indicates that a phase transition will be made. All phase transitions are made by
changing the appropriate bits in the phase control flip-flop when TP2 appears, and when the conditions required
during TS2 have been met. When the phase transition occurs, only the conditions in the new phase will be enabled
and the conditions in the old phase will be disabled completely.
When a logic path has been enabled, many times a signal name is assigned to that line and printed vertically along
the logic path. These signals include phase and time state conditions.
Certain synchronization operations are phase independent; they are also shown on Sheet 1. For example,
examining the seventh action in the center list titled SYNCHRONIZATION OPERATION, when both IBM signals,
HLDOUT and SELOUT, equal I, then the flip-flop SELO will get a 1. All phase independent actions are
accomplished by either TPI or TP2. This sheet also shows various special signals that are generated. These signals
contain no phase or time state information. This is also an index of the major phase interactions, with the sheet
number on which that phase can be found. These are shown as part of the diagram at the right-top titled MAJOR
PHASE DIAGRAM AND INDEX.
Program interventions that trigger special responses are emphasized by a pointing hand symbol.
Each gate has a footnote number to correlate it with the logic signal name used internally to perform the operation. These number-name pairs appear at the right or bottom and are the same as used in the control flows and
the data paths.
5.4.2.3 Design Flows - This paragraph refers to Sheets 2 through 7 of Drawing 04. These pages are arranged in
phases of the DXII-B, with each page divided into two sectors (top and bottom) representing the two possible
time states (TSI and TS2) of each phase. As described earlier, a sequence will proceed through the phases but
not necessarily in order. In some instances, the sequence will repeat an earlier phase as with Phase 2 during which
status is prepared. Depending upon whether the command from the channel is odd or even, the sequence will
proceed from Phase 2 to either Phase 5 for input (360 write), or Phase 6 for output (360 read). The phases, as
shown on the Major Phase Diagram and Index on Sheet I are:
a.
b.
c.
d.
e.
f.
g.
h.

Phase 0, Idle or Requesting
Phase 1, Address Response
Phase 2, Status Preparation
Phase 3, Status Presentation
Phase 4, Mark
Phase 5, Input
Phase 6, Output, and
Phase 7, Done.

As Drawing 04 indicates, there are many combinations of phase rotation depending upon the function being performed. Note that Phase 4, the Mark phase, is automatically entered when any recordable event takes place.
Upon entering this phase, the DXII-B performs two NPRs to enter t1:.e activity in the tumble table. All four
reset functions also require the DXll to go to Mark before returning to the Idle state.

5-30

Phase 0 - Idle or Requesting

Referring to Sheet 1 of Drawing 04, in Phase 0, the DXII-B is either idle with nothing to do, or it is doing one of
four main tasks: Selection Bypass, Selection Sequences, Asynchronous Operations, and/or Program Interactions.
Neither of the first two can become active unless Operational-Out is high, Select-Out is high, Select-In is low, and
Status-In is low. The Select-In low signal implies that the Select-Out signal is not being propagated. The Status-In
low means that the DXll is not presently presenting status by means of the Fast CU Busy sequence.
Assuming that Request-In is down, and either Address-Out is 0 or the DXll does not match the control unit
address, i.e., ADRECC=O, then the DXll will follow the left-most branch on this diagram and Select-In will be
enabled to be set when the clock ticks at the end of TS 1. This will cause Select-Out to be propagated to the next
CU on the bus.
If the address on Bus-Out is recognized (ADRECC=I), but the DXll is busy with.another device (CUBSY=l), the

DXll follows the Fast CU Busy line which terminates in page connector L2. When the clock ticks at the end of
TS 1, the signal FASTCU will perform all of the operations which are listed beside it, namely, ISSREJ will be set
to 1, BYPAS gets a I, and the BUSI flip-flops will be loaded with the appropriate status bits.
In TS2 of line L2, the "necessary and sufficient conditions" to set Status-In are that BYPAS=1 (it is), SELO=1
(it is), and that SYNC=O (which is true because the selection sequences have been bypassed). Therefore, Status-In
is set to a 1 at TP2.
Notice that Select-Out=O is a requirement for clearing Status-In and nothing further will be enabled during TS2.
Therefore, the clock continues to tick through TSI and TS2, but nothing happens until the Select-Out line is
stro bed to the 0 state at TS 1, or TS2, or if a System-Reset is issued by the channel. The latter condition is
illustrated as the left of two asynchronous operations in the center of the page. When the Select-Out line is
strobed to 0, this will now enable the clearing of Status-In and the transition of BYPAS to O. At this time, the
DXII-B is once agrun idle.
Assuming that ADRECC matches on an initial selection sequence, and that the DXll is not busy (CUBSY=O),
the first thing done is to set LOCKO and SYNC to 1s by signal SIG 1. If either ADRECD or BSYEN are false, the
FCTN bits are cleared (so that ESEND will not be set in Phase 3).
This occurs at TSI. Note that LOCKO set to a 1 from now on prevents the programmed interactions that terminate in nodes L4 and L5. This additional synchronization is required to protect a 200 ns window against the program initialization of a control unit function at the same time as we have begun or are about to begin acceptance
of a channel initiated function. Lock out will not appear in the remaining phases, but is should be remembered
that as long as LOCKO is aI, the fIrst five programmable registers of the DXII-B cannot be changed by the
program.
Setting SYNC to a 1 prevents either asynchronous operation from being enabled during TS2. This is needed so
that a phase change does not occur and/or so that LOCKa will not be cleared even if DONE were just cleared or
SYSRST just set.
If the DXII-B is in "single-thread" mode (BSYEN=I), then any pending status must be relieved by this ISS. If a
pending status condition is recognized (SIGIB=l), BYPAS is set to bypass the SPW and DST fetches. The BALF
flip-flop is used to remember the state of SIG IB for use in Phase 3.
Continuing down the middle of the page in TS2, both the channel-initiated sequence and the polling sequence
merge briefly but set the CHIS flip-flop to the contents of Address-Out (1 or 0). As shown on Sheet 8 of Drawing
04, CHIS is set if Address-Out is a 1. This is considered a channel-initiated sequence. On the other hand, if

5-31

Address-Out were 0 and the DXll were responding, then it would be a response to polling and that would be a
control unit initiated sequence and one of bits 6 (ESEND), 5 (CHDEND), or 4 (CUDEND) of the DXDS would
be set.
The DXII also sets Operational-In and clears Request-In. At this time the 5 sec timeout (DXTO) is started since
Operational-In sets at this time. If BSYEN is set, CUBSY is also set; and SYNC is cleared in preparation for a
phase change (this happens on every phase change). If BYPAS were still 0, this would be the normal sequence of
events and the contents of the Bus-Out register would be gated to become the new contents of the control unit
address register (CUAR); and a change to Phase 1 would also be enabled. When the clock ticks at the end of TS2
these operations are performed and control is switched to Phase 1, page connector M on sheet three. On the other
hand, if BYPAS were 1, then the CUAR address is placed on BUSI to identify the device to the channel as the
DXll begins either a response to poll or a pending status presentation and the DXll enters Phase 2 on Sheet 3,
page connector N. This would also be; done if REQI=l showing a request by the DXll. No NPR will be done for
either SPW or DST.
If the DXll-B is busy, then the fast busy response is used unless this selection sequence is for the same device
that is causing the busy condition and that device has status pending (FCTN=3). CUBSY can only be set in
single-thread mode or immediately after System Reset.
In Phase 0 if a system reset from the CH is recognized (SYSRST=I) and if an ISS is not in progress (SYNC=O),
then LOCKO (Phase 0) and CUBSY (synchronization operation, Sheet 1) are set and the results are stored in
the tumble table for use by the emulator (Phase 4).
If DONE=O, this indicates an entry in the tumble table has been serviced by the program; if INTEN= 1, an inter-

rupt may have been made to the PDP-II. Either way, the program, by clearing DONE, has indicated that it has
serviced the interrupt and is about to load the DXII registers. Therefore, the DXll must clear LOCKO. At least
one instruction time must be allowed after clearing DONE before loading a programmed register. These conditions
will be enabled repeatedly at every TPI rather than only once.
NOTE
Programmed load (set/reset) of DONE is permitted only in
Phases 0 and 7. Furthermore, only a diagnostic should attempt
to set DONE.
Referring to programmed interactions at page connector L, in the idle phase a nonzero FCTN code and the GO bit
cause Request-In to be set. If GO is a 1 and FCTN code is 0, then the DXII is immediately reset.
b.

Phase 1 - Address Response

Referring to Sheet 2 of Drawing 04, the DX11-B enters the Address Response phase only from Phase 0 when an
ISS is in progress. As Phase 11 is entered (Phase II-Phase I, TS I), SYNC is a 0 as it always is on entrance to a
phase, and therefore gates 2 and 3 are enabled. An automatic shift left and transfer of CUAR bits (07:00> are
enabled to DXBA bits (08:01) placing the device address, recognized from the channel, in the DXBA as a word
address. Note that DXBAOO gets a O. Actually, this bit cannot be loaded since it is wired to ground. Also, bits
(15: 10) of the offset register (DXOR) are enabled to bits (15: 10> of the DXBA. DXBA09 gets a O. When loaded
by the transition of time states, this places an offset base address for the recognized device into the DXBA. All of
this is in preparation for fetching device status on the addressed device. In reality, this operation is to fetch the

5-32

pointer word for that status word (SPW). When the clock ticks, the following occur: an NPR request is made,
and SYNC is set to a 1 (so that these operations will not be repeated while still in this phase).
NOTE
In the DXII-B, SYNC functions as a general synchronizer within phases as a flag to indicate that"some function has been done
and thereby prevents it from being done again while cycling
between time states.
Note that during TS2 nothing will be enabled until the NPR has been finished (NPRX=O). Since SYNC was set
to a 1 in TSI by BAAR, the operations indicated (e.g., loading CUSR) in TS2 will then be performed on the next
clock tick. This includes putting the address register (echo) into Bus-In (gate 4) in preparation for the address
response to the ISS. Transfer is made at this time to Phase 2 (Status Preparation). Refer to the DXND format on
Sheet 9 and note, as indicated on the flow diagram for Phase State 22, that if the right byte of the SPW is nonzero
or if the left byte of the SPW (offset of DST for this device) is zero, BYPAS will be set to 1 to indicate that no
NPR will be done for this DST. Note also that CUSR is cleared if the right-hand byte of the SPW is zero.
If any IBM reset has been recognized at this point, control will be sent to Phase 4 to mark the fact in the tumble
table. Otherwise (lBMRST=O), the DXll will continue to Phase 2, same sheet, page connector N, and the SPW
fetch is done.
c.

Phase 2 - Status Preparation (Part 1)

The DXll-B can enter Phase 2 from either Phase 0 or Phase 1. If Address-Out does not drop in Phase 2, the
DXll will wait, unless an interface disconnect is signaled by the fall of Select-Out or a reset signal is generated.
The top of Phase 2 (node N) raises Address-In as the tag for data placed on BUSI in either Phase 0 or Phase 1.
Then the DXll waits for Command-Out (CMDO) to rise. Note that no operation is as yet enabled in TS2. When
CMDO=l, the command at BUSO is copied into the command register (CUCR) and the parity OK signal is saved
in BYPAS for use later in Phase 3.
If this is a polling sequence (or release of pending status) for which no DST fetch is needed, then BYPAS will be
a 1 and the right-hand path will be taken. This path is also taken if the command has bad parity.
In TS2 of Phase 2, the decision is made as to what phase to transfer to next, depending on the function code specified when the sequence began (not necessarily when the program initially hit the GO bit). At this point, Phase 3,
5, or 6 can be entered.
NOTE
The function codes can be changed even after the GO bit is set
but not after a sequence has begun. Thus it is possible for the
program to clear the GO flag before a response is granted or
clear the function code before a response which hangs the DXI1-B
in phase 3. The function and GO bits should be asserted simultaneously
and not changed until an Interrupt is generated.
If a command status byte is needed from the device status table, then the left-hand path is taken (signal BANDSO).
The address is composed in the DXBA (gates 5 and 6) and NPR request is made (NPRX = 1). SYNC is set to
enable TS2 (above node H).
NOTE
BAND SO = DXBA gets DXND • BUSO.

5-33

After the data is in DXND (NPRX=O), either the left or the right byte is loaded into the CUSR status bits. This
result will be sent to the channel in Phase 3.
d.

Phase 2, Part 2

Having entered Phase 2 at the preceding TP2, and at that time, in either Phase 0 or Phase I, having loaded the
address into Bus-In via the BUSI flip-flop, 200 ns later (one time cycle) the DXll can be sure that the signals on
the Bus-In lines will have settled down and the DXII is ready to raise the tag line Address-In (ADRI). This is
done immediately because the conditions ADRO=O, CMDO=O, SYNC=O exist. Note that further activity in TS 1
of Phase 2 is disabled, for the moment, because Command-Out is not a 1.
The next question is whether anything in TS2 is going to be active. Notice that NPRX is 0 now (it was 0 in order
to have proceeded out of Phase 1). Also, SYNC is a 0, but Address-In is a 1 so that SIG4 is not true. Thus, no
action is enabled yet in TS2. Address-Out=O is part of the TS2 conditions so that only one phase change would
be possible if an interface disconnect were encountered during Phase 2.
In TS I, the DXII will again set a I to Address-In (this has no effect and is a correct procedure) and wait until
Command-Out becomes a 1 indicllting that the channel has loaded the command onto the Bus-Out (BUSO) lines.
Now the DXll reads Bus-Out into the Command register and responds by lowering the in-tag Address-In.
The parity okay signal is copied into the bypass flip-flop at this time. If command parity is bad, then the DXII
does not respond to the command. Instead, it ignores the command by taking the right-hand path. The DST is
bypassed if Operational-Out has dropped because of a selective or system reset. The DST is also bypassed if
BYP AS= 1 because of conditions set in Phase I. However, if the command is okay (P AROK = I) and bypass is 0,
then the DXII takes the left-hand branch and moves the NPR data into the left half of the DXBA; the right half
of the ElXBA is loaded with the command, itself, as taken from BUSO. Also, the DXII puts a 1 to both NPRX
and SYNC. At this point in TS2, with no further action transpiring, NPRX is not a 0, so nothing happens above
node H. SYNC is a 1 so that nothing happens on the right side of TS2.
Back in TSI again, the DXll determines whether anything is enabled. Address-Out is a 0, Command-Out could
be dropped to a 0 now that the tag-in low response has been given, but SYNC is a 1; now Address-In will not be
raised and parity okay will not again be copied into bypass.
Nothing further happens in Phase 2 until the NPR response is indicated by NPRX going to a O. Assume that it is
strobed to a 0 at TSI. Therefore, TS2 is enabled. The DXll will set SYNC to a 0 in preparation for a change to
Phase 3, and the appropriate byte that was in core will be loaded into the control unit status register (CUSR).
The low-order bit of the Command register is used to decide whether this was an odd or an even command. The
DXll now proceeds with the status presentation.
e.

Phase 3 - Status Presentation

Referring to Sheet 4 of Drawing 04, Status Presentation, this phase is entered from either Phase 2 or 7. Upon
entering Phase 3, Status-In (STAI) is O. At this point, the logic must be able to make many determinations as
illustrated by the complex logic expressions stated to the right side of the main path. These determinations are
based on the following considerations:
1.
2.
3.
4.
5.
6.
7.

Did the command have good parity (BYPAS=l)?
Was the SPW and/or the DST fetched from core without a nonexistent memory reference (NXM=O)?
Is this a test 10 instruction (TESTIO=I)?
Is this a status pending sequence (BALF=I)?
Is this a sense command (SENSE=1)?
Is this an illegal command (UCHECK=I)?
Is this a channel initiated sequence (CHIS=l)?
5-34

If this is a control unit initiated sequence (CHIS=O) then the DXll sends the contents of CUSR to the BUSI.

Otherwise, if parity is okay, if there is no timeout error, if this is not a sense command, and if this is either a) not
status pending or, b) a test 10 instruction, then the DXll-B moves the status register to Bus-In using signal BISR.
If parity is okay, if status is pending (BALF=!), and if this is not a test 10 (SIG5B), then the busy bit is sent to

BUSI04 and the rest of BUSI is loaded from the CUSR. If this is either bad parity or if the DXll has failed to get
proper time response either during the device status table fetch or during the SPW fetch (causes PDP-II timeout to be
a 1) and if this is not a status pending situation, then only the unit check bit is sent to BUSI and CUSR as the status
response. If a hardware error prevented command interpretation, but a pending status exists for this device, then
that status is presented.

In TS2, Command-Out could still be a 1; since Status-In is 0, this would prevent further operation. Assuming that
Command-Out becomes a 0 or has become 0 by this time, then, with Service-Out a 0, the DXll is able to set StatusIn to a 1. If an interface disconnect, system reset, or selective reset were present here, then Operational-Out would
be a 0 and this sequence would quickly conclude. The DXll now waits for either a Command-Out or a ServiceOut response with Status-In a 1. Notice that as long as Status-In is a I no activity is enabled during TS 1.
When a response is given to the status presented, the DXlllowers the Status-In tag at TS2, makes a phase change
to Phase 4, and recognizes either Stack-Status or Status-Accepted. If status is stacked, the Stack-Status bit
becomes a 1. (Note that this will not be done by the channel if a 0 status is given to other than a test 10 instruction.)
If status is accepted, stack status is reset to O. If Suppress-Out is a 1 at this time, the DXll recognizes Command-

Chaining. If the function code is three then ESEND is set because this is either a presentation of the previously
stacked status or is, in fact, an ending sequence presentation.
Finally, if Control Unit End status is accepted, the ISSREJ flip-flop must be cleared, since a CUEND is no longer
outstanding.
f.

Phase 4 - Mark

Phase 4, the Mark phase, is also located on Sheet 4 of Drawing 04. This phase can be entered from any other
phase since this phase is used to enter data into the tumble table. On entering the Mark phase, SYNC is 0 and
NPRX is 0 unless there is an NPR already in progress (and interrupted by a reset condition). A number of operations are done in TS 1 with the objective of making the first entry into the tumble table. The tumble table address
is composed in the DXBA by combining the contents of the DXOR high-order byte, the tumble table index byte
times two, and by putting 0 in the lower bit of the DXBA. For the data that will be stored, the contents of the
DXDS (the device status) register are placed in the DXND.
At the clock tick, NPRX is set to 1 and the data transfer proceeds. At this time, SYNC is also set so that none of
the TS I operations can be enabled again, and the DXII proceeds to count the tumble table index by +1. In TS2
nothing happens until the first NPR has completed, whereupon the Command and Address (DXCA) is put into
the NPR data register (DXND). The DXll again copies the tumble table address into the DXBA and loads one to
NPRX to request the second NPR store cycle for the tumble table data. At this time, the DXll clears SYNC,
increments the tumble table index, and switches to Phase 7 with the NPR in progress.
When the DXDS is copied for the tumble table store operation, a special flip-flop, IRS, must be set to remember
if an IBM reset condition was stored in the tumble table. IRS is then used in Phase 7 (where DXDS is cleared)
to determine if a reset sequence occurred between Phases 4 and 7.

5-35

Phase 5 - Input (360 Write)

Referring to Phase 5, Input, located on the same sheet of Drawing 04, the DXll enters at node Y. The transition
to Phase 5 from either Phase 2 or 7 is initialized by setting BALF to 0, BYPAS to I, and CUDX to 1. With
CUDX=l, data okay ai, Service-In a 0, and IOD a 0, the resultant SIG9 is generated, which raises Service-In
delayed by BLLM.
Later the DXII will zero the BYPAS flip-flop. The use of the BYPAS flip-flop here is simply a reflection of its
appearance in the data okay expression to check for first data byte. Note that nothing will be active under node
Z because SYNC is not a 1. The entire Phase 5 is similar to Phase 6. Note the symmetry in the two flow diagrams.

The next actions in Phase 5 occur in TS2. If the channel responds with Service-Out to Service-In, the DXII
lowers Service-In, at the same time copying the content of BUSO into either CUCR or CUSR. The destination is
determined by the present value of the BALF flip-flop. If BALF=I, then the CUCR is filled and CUDX is reset
to 0, indicating that path Y activity is no longer in progress.
NOTE
If Command-Out is raised. in response to Service-In (IO Stop)

then BUSO will contain zeros. Thus if only the low-order byte
contains data, the high-order byte will contain zero. Similarly,
if CVDEND is to be set, and BALF is 0, then CVCR is cleared
so that the last byte entered into PDP-II core will be zero.
In addition, for each cycle through this sequence, i..e, for each BUSO copy, I is added to the byte count. Data
transfer will cease when, I) the DXBC is minus one, 2) a timeout error occurs, or 3) a parity stop is indicated.
The latter is a special feature that allows the option of arresting the data sequence when a parity error occurs on
Bus-Out. In byte-multiplex mode this permits deletion of the bad byte and resumption of the operation.
There is still no activity below node Z, Phase 5, TS I, because SYNC is still not a 1; but in TS2, under node Z,
activity is now possible because the three lower conditions are now present (SYNC=O, NPRX=O, and CUDX=O).
The DXII now takes the left-hand branch and copies CUCR and CUSR into DXND in preparation for transfer
of the two bytes of data into PDP-II core. The transfer is started by NPRX= I and the direction is controlled by
NPRT=I. CUDX is also set to a 1 to indicate that activity is again valid in regard to CU data.
Finally, SYNC is set to I, enabling the operations under node Z, TS 1. This happens when NPRX is O. The operations are clear SYNC and increment DXBA by two.
NOTE
Incrementation is possible at this point because it follows the
completion of the NPR cycle and another NPR cycle will not
be made for a period of time, allowing plenty of time for the
DXBA to carry, even into its extended address bits.
When lOD is finally set to I and activity is no longer possible on the CU data, and when the NPR transfer is complete, the top three conditions exist under column Z, Phase 5, TS2. These are IOD=l, NPRX=O, and CUDX=l.
The DXll now follows the right-hand path to clear SYNC and switch to Phase 4, marking the termination of this
particular transfer.

5-36

Phase 6 - Output (360 Read)

Referring to Sheet 5 of Drawing 04, the Output phase, the DXll will have arrived here from either Phase 7 (done)
or Phase 2 (status presentation). Upon entering this phase at node A, SYNC is already 0; in TS 1, this will now
enable the setting of SYNC; and with IOD being a zero, SYNC=O will also enable the setting ofNPRX. This will
not occur until the clock tick to TS2; but, when the tick occurs, SYNC=O will first allow NPRX to be set and will
then set itself. The transition to TS2 will perform the ftrst fetch of data from the PDP-II core, assuming that
the program has correctly initialized the DXll Bus Address Register (DXBA) and the Byte Count (DXBC).
When the NPR is completed, NPRX is reset to 0 and the conditions to enable operations in TS2 are met. SYNC
is reset to O. Assuming that IOD is still a 0, the DXll increments the DXBA by two. Simultaneously, the DXll
copies the data from the DXND into the CU data registers (CUCR and CUSR are used for this purpose) and sends
a I to CUDX indicating that the IBM buffer is ready.
At the next tick, the DXII reverts to TS I, but this time both page connectors, A and B, are activated. At this
point, SYNC is zero once again, so it and NPRX will set to 1 on the next transition of states. The NPR direction
control (NPRT) was already reset to 0 when this phase was entered; now, both NPRX and CUDX are in the I
state or active.
Inspecting the logic path begun at connector node B, CUDX is a I, the data okay signal is a I (see phase independent sequences on Sheet I), Service-In is assumed to be 0, and IOD is also assumed to be O. If BALF is 0, then
the DXII will load CUSR into the BUSI flip-flops. From there the 8 bits of data plus parity will be presented to
the Bus-In lines. At this time, the DXII sets the Bus Load Limiting flip-flop (BLLF) which, at the next TP2, will
set Service-In (SRVI) to a 1. This setting is delayed by the BLLF to give a one time pulse difference between
loading the BUSI and setting the appropriate in-tag, thereby ensuring that the parity line (PARI) will have time to
settle (its data is the output of the BUSI flip-flops).
Repetitive SRVI sequences are delayed by BLLM and BLLF to limit the rate of data transfer to the channel and
DXII. The rate is set to 4 JlS when shipped. This is an installation parameter dependent on system conftguration.
NOTE
It is possible for both logic paths A and B to have TS 1 or TS2

elements enabled simultaneously. This is to allow simultaneous
operation of both the I/O interface bus and the PDP-II Unibus
synchronized to the DXll clock. At TS2, the DXll will also
set BYPAS to a 0 to mark the end of the fIrst data transfer.
When Command-Out is raised in response to Service-In being asserted, the DXII will respond by lowering
Service-In and taking the left-hand branch of Phase 6, node B, TS2. At this point, the DXII recognizes that the
channel has indicated data transmission end. This will set a bit in the device status (CHDEND, which also causes
IOD to assert) at TS2. In addition, this clears the CUDX flip-flop so that no further activity is enabled under
path B. If, however, Service-Out is raised, indicating acceptance of the data, the DXll takes the right-hand
branch, complements the BALF flip-flop, and increments the byte count (DXBC). If the byte count is minus 1
at this time (i.e., about to go to 0), then the DXII sets control unit data end (CUDEND), which also asserts the
IOD line and clears the CUDX flip-flop. The same task would be done if PDPTO were set, indicating an NPR
failure.
From node A in TS2, assuming that CUDX is 0 (or was made 0 at prior TS2), the same cycle as described above
would be repeated. If, however, both IOD and Interface Disconnect = 1, CHDEND will be set to indicate that
the channel terminated the data transfer by means of an interface disconnect. In any case, if IOD is ai, the DXll
will simply switch to Phase 4 (Mark) to record the data end indication bits into the tumble table and then proceed
to Phase 7 (Done).

5-37

Phase 7, Done

Referring to Sheet 6 of Drawing 04, to enable any condition in the done phase, node J, the last NPR should be
completed (NPRX=O). SYNC will be 0 but the DXII must also wl,lit for either Select-Out or Stack-Status to
become o. When this happens, the actions listed to the right of the line are enabled to occur on the next clock
tick. SYNC will be set to a I, the FCTN and GO bits will be cleared, the device status register (DXDS) will be
cleared (Note, except bits 3, II, 12, and 13), and both the BALF flip-flop and the NPR transfer flip-flop (NPRT)
will be reset.
Now, control will go in one of two paths. Notice that, with the exception of the top three quantities in the righthand gate, the conditions for right- and left-hand directions are complements. An SEL channel will take the left
path (Forced Burstmode) while an MPX channel will take the right path (Byte Multiplex mode).
When operating with an SEL channel, Select-Out is up, the DXII takes the left-hand path and drops into Phase
State 72. If an IBM reset is issued at this time (IBMRST=I), SYNC=I and OPLI is still I, the DXII will take page
connector T to reset SYNC with the signal BLAST, enter Phase 4 to mark the fact, come back to Phase 7 and
take the right-hand path to get off the channel.
If no reset is received, however, Operational-In is still up, and the DXII-B will just set SYNC on the time state
transition. Lockout was set in Phase 0; the only condition remaining is the requirement that the program clear
DONE.
When the program clears DONE, Lockout is disenabled and the DXII drops into the next gating condition (provided an IBMRST is not issued, see above). To enable SIGI7, the only requirement needed now is for the program to set GO, since OPLI and SYNC are both set. The program will set GO simultaneously with setting the
function.
The function code that is set at this time depends on the intention of the program. If FCTN is set to 0, the
DXll will enter Phase 0 at node L and perform a DXll RESET operation (resets the world).
If this is an input operation, FCTN is set to I and the DXII enters Phase 5 at node Y. It will also set Lockout,

BYPAS, and CUDX; the ODD flip-flop will be copied into the BALF flip-flop. Upon returning from Phase 5
(after having gone to Phase 4 to store the device status, command, and address in the tumble table, and setting
DONE), the DXII takes the normal path and does all the things it did during the last pass. When it drops to
TS2, this time it sets ending status by setting FCTN to 3 and setting GO. This time the DXII exits at page
connector H, goes to Phase 3, then to Phase 4, and back to Phase 7.
If this is an output operation, the program would set FCTN to 2, go to Phase 6, then to Phase 4, then to Phase 7,
and back to Phases 3, 4, and 7.
Once data and/or status has been presented, the channel drops Select-Out. This enables the DXII to take the
right-hand path in TS I of Phase 7. SELO=O yields the signal IRCCLR. This drops Operational-In on the next
clock tick; with SYNC= I, SIG 16 clears everything listed to the right of the line. This restores the flow to the
idle state, Phase O. If status has not been presented (STKSTA=l) and BSYEN=I, FCTN is automatically set to 3
and Request-In is raised to try a CUI.
j.

IBM Reset Stored Sequence

The purpose of the IRS flip-flop, located in the DXDS Register, is to remember the fact that IBMRST has been
issued to store that fact in the tumble table by a forced additional tumble table entry.

5-38

Referring to the flow diagram for Phase 4, Sheet 4 of Drawing 04, SIG7 is generated, which on the clock tick to
TS2 sets the NPRX flip-flop and transfers the contents of DXDS to the DXND. Once transferred, that data is
ready to be sent to the tumble table in the next microsecond or two, when the present NPR cycle is through. At
that instant, before the second NPR is done (DXCA store), if IBMRST is issued, IRS is set and the condition that
caused the IBMRST is stored in the DXDS. These can be a System Reset (SYSRST), a Selective Reset (SELRST)
or an Interface Disconnect (INFDSC) (see "Special Signals" on Sheet I of Drawing 04).
The DXII then drops through TS2 of Phase 4 and enters Phase 7, where the DXDS is cleared except for certain
bits containing the reason for the IBMRST. The DXII then attempts to take the right-hand path and although
IRS=I, Operational-Out is now a 0 (one of the results ofIBMRST). This forces the DXll to take the left-hand
path (not zero the reset conditions), and to fall out at page connector T, where it finds the conditions right to
. generate the signal BLAST. This zeros SYNC and causes the DXII to return to Phase 4 where it can do another
tumble table entry.
The uncleared reset conditions in DXDS are now transferred to the DXND and stored in the tumble table. The
DXII goes through the second phase of storing the address (this is meaningless at this point) and returns once
again to Phase 7. This time the right-hand path conditions are met (IRS=I, SELO=O) enabling IRCCLR (IBM
Reset Conditions Clear). At the tick to TS2, SYSRST, SELRST, and OPLI are all cleared, all other Phase 7
functions are performed, and the DXll returns to Phase O.
Note that since on an IBMRST OPLI-+O, the setting of IRS (an ORed condition) provides an additional way to
enable IRCCLR and a return to Phase O.
k.

Interface Disconnect Sequence

Interface Disconnect (INFDSC) is a special situation indicated by the combination of interfacing signals comprising Select-Out=O, Operational-In=l, and Address-Out=l (see Synchronization Operation on Sheet 1 of
Drawing 04). When the DXII-B has Operational-In raised, if the channel raises Address-Out, puts the DXII
address on the bus and then drops Select-Out, it is informing the DXll-B to go away. In IBM parlance this is
called an Interface Disconnect; IBM requires that the DXll drop Operational-In within 6 IlS after receiving an
INFDSC. Since the DXll, upon receipt of a disconnect, could be involved in internal bookkeeping and in transactions with the PDP-II that could take longer than 6 IlS, it provides hardware to satisfy the IBM requirement
while allowing its own operations to proceed. Further, since once the DXII has responded to the disconnect a
subsequent selection from the channel could occur before processing of the disconnect was completed, this circuitry permits proper interchange with the channel to occur without hindering the successful completion of its
internal operations.
Referring to the note on the flow diagram on Sheet 7 of Drawing 04, this sequence can be enabled in either
Phase 4 or Phase 7, immediately following receipt of INFDSC and functions simultaneously with these phases.
In actuality, it uses the hardware designated for Select-Out propagation and for the Fast-CU-Busy sequence of
Phase O.
If an INFDSC is received during S9me data phase, the DXll will immediately terminate that phase and go to
Phase 4. It will perform all normal functions in this phase, including the setting of DXDS bit 11 (INFDSC).
When this bit sets it causes the Disconnect Response flip-flop to set which, 200 ns later, causes OPLI, ADRI, and
SRVI to drop, and enables the operation of the Disconnect Response flow. Meanwhile, the DXll continues to
complete the tumble table entry and then goes to Phase 7, as;'. would if a disconnect had not occurred.
In this case, as the DXII enters Phase 7, DSCRSP=l, which enables SIG14. It then takes the right-hand path
finding both IRS and INFDSC set, sufficient conditions for IRCCLR. This results in the dropping of SYSRST,
SELRST, and OPLI, the latter being the IBM requirement to release the channel. The DXII then continues

5-39

through Phase State 72, clearing all conditions to the right of the line. Since this could take considerable time to
complete as the DXll does its NPR cycles (as much as 10 to 15 JJ.s each), and since the channel could become
selective again in that time, the logic described in the Disconnect Response flow diagram is provided to take care
of that eventuality. Remember, events in this flow occur simultaneously with events in Phases 4 or 7.
If the channel becomes operational while the DXll-B is still processing the INFDSC; then as the DXll enters
the response sequence OPLO will be a I, SELO=l, and STAI=O. At this point in the flow the determination is
made as to whether or not the channel's reselect is addressed to the DXll or to another CU on the bus. If the
select is for another CU, ADRECC=O (no compare) and the left-hand path will be taken. In this instance, SELl

will be set and the Select signal is propagated down the line.
If, however, the Select is for the DXll-B, ADRECC=l and the right-hand flow is taken. In this event, the DXll
is still busy and cannot accept the selection so the FAST CU response is given. The DXll rejects the ISS
(ISSREJ=l) and records the fact in the tumble table. BYPAS is set to enable Bus-In. Bus-In is cleared but bits
04 (BUSY), 05 (CHEND), and 06 (STAMOD) are force-set. When the clock ticks to TS2, Status-In is raised to
put the status on the bus. When the channel responds with a Select-Out drop, Status-In is dropped and BYP AS
is cleared. The DXll then proceeds with the FASTX logic described at that point in Phase O. Meanwhile, the
DXll has processed through Phase 7 and terminates its flow in Phase O.

5.5 CIRCUIT DESCRIPTIONS
As mentioned at the beginning of the last paragraph, the flow diagrams are such that a gate-chasing discussion is
not required. In this paragraph, therefore, only certain subtle circuitry characteristics are discussed. In these
block schematics, each signal is preceded by a source code to identify the drawing number on which that signal
is generated. For example:

t,-.--D25SIG5 ----...
Source Drawing No.

Signal Name

means SIG5, generated on DrawingQXll-B-25. In most cases, the location designation of a flip-flop bears a
numerical relationship to its bit position in the register format. For example, on Drawing 05 (DXDS), the M205
at the top left-hand side of the page is located at C25. Its position in the DXDS format is bit 15. In most cases,
if lOis subtracted from the hardware locations, the register bit position can be determined. Another example is
the SYSRST flip-flop directly below, located at C22 and situated in the register at bit position 12 (22-10=12).
There are exceptions to this convention, e.g., the IRS flip-flop shown as part of the DXDS at location C24 is not
a functional part of that register. Bit 14 of the DXDS is NXM, which is located in the NPR and INT Control.
IRS is displayed as bit 00 of the DXES2 Register.
In this paragraph, the circuits are described in drawing number order, excluding the functional flows.
5.5.1 DXll Device Status Register (DxnS)
The DXDS is shown on Drawing No. D-BS-DXll-B-05, Sheets 1 and 2. This register contains the bits stored in
the DXDS, except the M205 at C24. This is IRS which is not part of this register but is part of the DXES 1 register bit 00. Bit 14 in the DXDS is NXM set by PDPTO which comes from a timer in the NPR control. This register is the ftrst of two tumble table entries described in the sequences (Status, and Command & Address).

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A typical setting arrangement can be described for the register by using PARER as an example. Enabling conditions are AND/NORed to the data input of the flip-flop and this result is ANDed with CLKN to the clock input.
CLKN2 ticks at pin B1 of the M 112 every 200 ns, but nothing happens until the data gate is activated, e.g., the
top condition is SIGSI\BYPAS (0). As shown on Drawing 25, SIGS implies Phase 3, TSl. If BYPAS=O, that gate
will be enabled on the phase change and will go low at pin Al of the MIl2 and at pin Kl of the flip-flop. The
flip-flop will set on the leading edge of CLKN2.
Setting of all other flip-flops in this register is similar with the gating conditions being more or less complex. Note
that SYSRST can only be direct-set, however, as with ISSREJ. The latter cannot be direct-cleared, but is reset by
clocking against a grounded data input.
Note that all flip-flops in this register are "set-only". They cannot be cleared from the gates. With the exception
of INFDSC (bit 11), SYSRST (bit 12), SELRST (bit 13), and ISSREJ (bit 03), they are all direct-cleared by
CLR DXDS or CLR DXDSA. This signal is the product of four OR conditions and CLKN. The M606 is a PA
that, when enabled, produces a low-going edge (one pulse 30 to 100 ns wide).
5.5.2 Control Unit Status Register (DXCS)
The DXCS is shown on Drawing No. D-BS-DXII-B-06, Sheets I and 2. In this register, all flip-flops are set or
reset in fundamentally the same way, just the gating complexity varies. Most are direct-cleared by CLR DXCS,
either alone or in conditioned combination.
The exceptions are CUBSY, which has no direct-clear, and the two function flip-flops which are cleared by CLR
FCTN, but here this signal is a function of CLR DXCS when combined with CLKP2ASIG 14; the latter generated
in Phase 7, TSI. CLR DXCS is generated by CLKN2 for either a DXRESET or an INIT. This is seen on Sheet 1
at coordinates C2.
All flip-flops are program-Ioadable since data inputs to all flip-flops contain, as their inputs, the appropriate DB US
bit for that flip-flop, either directly or once again in combination with appropriate gating conditions.
All flip-flops are clocked by some combination of positive or negative clock depending upon gate polarity requirements. Clocking is usually enabled by DXCS CLKEN (the ANDing of ADRS04, DATO EN HIGH, and LOCK (0)).
When clocked, all flip-flops will set on the presence of data and reset on the absence of data.
Most flip-flops cannot be loaded in Maintenance Clock mode; note that the FCTN and GO flip-flops can be loaded
since their clock pulse originates at the free-running source in the clock generator. The FCTN flip-flops use PCLK
while the GO flip-flop uses NCLK. All other flip-flops use the gated versions CLKN or CLKP.
5.53 DXl1 Bus Address Register (DXBA)
The DXBA is shown on Drawing No. D-BS-DXII-B-07. This is the register in which the tumble table address is
composed for each NPR.
The register comprises a loadable 16-stage M238 Counter that keeps track of the next tumble table entry address,
and an M 169 Multiplexer to gate the various source addresses into the register. Clocking is accomplished by an
M606 that is fed by the OR of all input gating conditions. All flip-flops are cleared by DXRESET.
Pin SI, the 00 input, on the M238 is grounded so that on each and every register load (LOAD DXBA) the register
is counted by + I as triggered by CLKPI (COUNT BA). The register will be counted by +2 during Phase 5, TS1,
when SYNC=l and NPRX=O. This incrementation is done following the NPR cycle, at a time when another NPR
cycle will not occur for a period of time long enough to permit carrying to occur (DXBA CRY). CRSRND is used
to increment the address during an output transmission.

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When ADRSIO HI\OUT HI HI\LOCKO (0) H are all true, BADBI and 2 are generated on Drawing 25. BADRI
enables the contents of DB US <15:01) to the register, while RADB2 generates LOAD DXRA.
In Phase 1, TS 1, BAAR loads the shifted contents of the CUAR into the register in preparation for a fetch of the
SPW. At the same time, RAOR enables the contents of the CUOR into the register as an offset.
In Phase 2, TS 1, after the SPW has been fetched, RANDSO reads the pointer part of the SPW from the DXND to
the left half of this register, and copies the command from the BUSO lines into the right half of this register.
During Phase 4, BANX is used to gate the shifted contents of the TTNDX into this register to advance the TT
address.
5.5.4 DXll Byte Counter (DXBC)
The DXBC is shown on Drawing No. D-BS-DXII-B-OS. The program loads the negative byte count (2's complement) into this register (LOAD DXBC) and the register counts on the AND of CLKPI and either SIG 10 (during
input operations) or SIG 13 (during output operations).
When the count is about to be exhausted (about to go to 0), the signal BCMO (Byte Count Minus One), is generated, which ANDs with either SIG 10 or SIG 13 on Drawing 05 to set CUDEND. This, in turn, asserts IOD and
clears CUDX on Drawing 11 indicating DONE.
A DX RESET generates CLR DXBC to reset the register.
5.5.5 Control Unit Status Register (CUSR) Part of DXOS
The CUSR is shown on Drawing No. D-BS-DXII-B-09, Sheets 1 and 2. The bits stored in this register are shown
in Figure 4-6. These are the Control Unit Status bits loaded either from PDP-II core during Phase 2, TS2 (SRDlB),
or from multiplexed sources as described below.
When ADRS06 HJ\OUT LOW HI\LOCKO 0 H are true, SRDB (CUSR~Data Bus) is generated allowing the Data
Bus (DBUS (07:00» to enable the flip-flops in the register. This loads the register with the status bits from core.
In Phase 1, TS2, SRNDEN (CUSR~DXND Enable) is generated when the NPR has been granted to enable the
status CDXND <07:00» into this register.
In Phase 2, TS2, one of two signals will be generated on Drawing 25, depending on whether the command stored
in the CUCR is odd or even. If CUCROO is a 1, SRNDH will be generated and enable DXND <15:08) into this
register. If CUCROO is a 0, the low byte CDXND (07:00») will be enabled to this register.
NOTE
IBM commands are odd for in transfers (IBM Write) and
even for out transfers (IBM Read).
In Phase 5, TS2, SRSO is generated to gate the second data byte from the Bus-Out into this register.
In Phase 6, TS2, CRSRND is generated to enable the contents of the DXND low byte to this register during
PDP-II output operation.
Clocking for all flip-flops is essentially the same. The signal STB CUSR is exactly the same as STBA CUSR; both
are based on CLKN21\CUSR CLK ENA, the latter being the OR of all multiplexer gate enables.
The register is cleared by CLR CUSR, the AND of DX RESET and CLKN2.

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Note that on Drawing 24, when any of these bits are set during a channel initiated sequence (CHIS (1)) or when
a status operation is underway (FUNEQ3), the signal CUSRNZ is generated to indicate that the CUSR is nonzero.
The CUOR,also a part of this DXOS register, is represented by two M238 Modules on Sheet 2. Note that this
register is writable only when in off-line mode. Bits 09 and 08 are not used in this register.
5.5.6 NPR Data Register (DXND)
The DXND is shown on Drawing No. D-BS-DXII-B-lO, Sheets 1 and 2. As shown in Figure 4-12, this register is
used to hold the contents of two other registers and the contents of the data bus for sequential NPRs.
NOTE
The bit position/module location convention does not apply to
this register.
The data inputs of all flip-flops are fed by M169s; they are four-way multiplexers. On Sheet 1, DXND 05:08),
only three of the four inputs are used. On Sheet 2, DXND (07: 00>, all four inputs are used. The enables for each
set of inputs are generated on Drawings 24 and 25 to determine which input set is gated into the register.
The enable NDDB (DXND+--Data Bus) is generated on Drawing 24 as the AND of NPRX (I) (request has been
made) and NPRT (0) (transfer is from PDP-II). When raised, it enables the contents of the Data Bus into this
register.
The enable SIG7 is generated on Drawing 25 during Phase 4, TS 1, when both NPRX and SYNC'" 0. When raised,
it enables the contents of the DXDS into this register.
The enable SIG8 OR NDCRSR (DXND+--CUCR 'CUSR) is also generated on Drawing 25 during Phase 5,1'82, and
Phase 4, TS2. When raised, NDCRSR enables the contents ofCUCR (07:00> into DXND (15:08). During Phase 5,
TS2, it enables the contents of CUSR into DXND (07:00>, and during Phase 4, TS2, 8IG8 enables the contents of
CUAR (07:00> into DXND (07:00>.
The clock for this register is made up of the OR of all data enabling conditions and CLKPl, in turn ORed as
DXND CLK or DXND STB. The left-hand byte is additionally enabled for clocking by INIT.
Clearing is generated on Drawing 21 as the AND ofDX RESET OR INITI\CLKN2. Note that four DXll clear
pulses are generated and fed to sets of six flip-flops each. This is accomplished by internal wiring on the M2l6,
which contains six flip-flops per module. All flip-flops on the same module are cleared simultaneously (see footnote on Drawing 21).

5.5.7 DX11 Control Bits Register (DXCB)
The DXCB is shown on Drawing No. D-BS-DXII-B-Il, Sheets 1 through 4. This register holds some of the DXll
control bits shown in Figure 4-11 .. Exceptions are bits 11, 10, 01, and 00, generated elsewhere, and signals generated here but displayed elsewhere. These are DSCRSP (bit 2 of DXES 1) and ODD (bit 6 of DXES). NPTDONE
on Sheet 2 is not displayed at all.
On Sheet 1, LOCKO (bit 15) is clocked by CLKNI when enabled for clocking by either DONE (l)ASYNC (1) in
Phase 0, TS2; or OPLI(l)ASYNC(l)I\DONE(O) in Phase 7, TS2. It will be enabled for setting on either SIG17,
when the function is set to anything but 00, or on an IBMRST or an error status condition.
The phase control flip-flops 0, I, and 2 represent a binary arrangement, the combined states of which determine
which of eight possible states the DXII-B is in.

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Clocking for these three flip-flops is the OR of all possible enabling conditions. The SET PHx signals are wired to
provide the proper coded combination for each phase. Cm5 yields a 1-0-1 combination or Phase 5. CUI6, in like
fashion, generates a Phase 6 condition, while SIG8 results in a Phase 7 setting. All three flip-flops, as with most
in this register, are direct-cleared by CLR DXCB generated on Sheet 4. Exceptions are DSCRSP, ONLINB, and
ODD, which appear on Sheet 4.
Notice that the data enable/clocking scheme in these flip-flops is similar to most other flip-flops in the DXIl,
in which the data input to the flip-flop is used as one possible condition for clocking such that if the data conditions are not present, the flip-flop, when clocked, will reset.
On Sheet 4, ONLINB (a function of ONLINA) is fed to M611 inverters that function as master gates to run all
receivers and drivers in the IBM interface.
The various conditions for the rest of the flip-flops in this register are self-evident and will not be detailed here.
5.5.8 Control Lines Out Register (CONO) Part of DXMO
The CONO byte of the DXMO is shown on Drawing No. D-BS-DXII-B-12. It stores the states of the IBM Selection Control lines and Tag lines as received at the interface on Drawing 27, and displayed as shown in Figure 4-9.
PARO is also displayed but is not stored in this register. Note that although HLDO is displayed, SELO is made a
condition of HLDO by ANDing on its data input.
This register is writable only when either off-line or on-line and cabled. It is used by the simulator program only.
All flip-flops are clocked by CONO CLK, a function of CLKN, and all are direct-cleared by DX RESET OR INIT
as generated on Drawing 24.
The low-order byte of this register (DXMO), as displayed, is not stored in flip-flops but rather displays either the
actual Bus-Out signals (BUSO (07:00> or the buffered versions (BUSOE (00:07».
5.5.9 Control Lines In Register (CONI) Part of DXMI
The CONI byte of the DXMI is shown on Drawing No. D-BS-DXII-E-13, Sheet 1. This register is used for maintenance purposes to read the Bus-In tags originating in the DXII-B logic. As such, it gives a representative view
of the bus as seen by the channel. The register is usually read-only but, in Maintenance mode, can be modified
by the program. When off-line, the PDP-II program reads this register (if ENABLE= l); when on-line, it reads
the test-in plug. The output of these flip-flops is enabled to the IBM Bus-In interface on Drawing 27.
The byte is loaded from DBUS (J 5: 10> with LOAD BUS DXMI, which is generated by the AND of
ADS 161\DATO EN HIGHI\-ONLINE. There are other loading combinations that can be read from the print
while referring to the flows.
Clocking is accomplished by CLKN3 in various combinations as shown. In all cases, one of the conditions for
iclocking is the presence or absence of data.
All flip-flops except SELl are direct-cleared by CLR DXMI, the AND of CLKN3 with the OR of INIT, ON, or
DX RESET.
Also displayed in this register, but not stored in it, are CLKO (bit 09) which comes from the cables even when
off-line, and PARI (bit 08) generated on Drawing 26 as a comparison of the bits described in Paragraph 5.5.10.

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5.5.10 IBM Bus-In Lines (BUSn Part of DXMI
The BUSI byte of the DXMI is shown on Drawing No. D-BS-DXII-B-13, Sheet 2. This register contains the data
that is enabled to Bus-In for transmission back to the channel. The output of this byte is sent to the parity generator on Drawing 26 to produce PARt
The flip-flops are all identical with multiplexed data inputs. Clocking is achieved by CLKN3 ANDed with either
the output of the multiplexer or with BUDATA, which is made up in the center of the page of either all multiplexer gate conditions or the OR of ON, SIG5A, or SIG5D.
In Phase 0, TS1, FASTCU is generated on Drawing 24. At this time a 1 will be sent to BUSW6, ENDEN
(STAMOD) will be set in BUSI05, and a 1 will be put in BUSI04 (CUEND); all other bits will be reset to O. This
is the first portion of a disconnect response.
During Phase 1, TS2, BIAR performs a ones transfer of CUAR to this register as the address echo for transmission
to the Bus-In lines.
In Phase 6, TS 1, if BALF is a 0, SISREN will be generated to enable the transfer of the contents of the CUSR
(first data byte) into this register for presentation to the Bus-In lines. If BALF is aI, SICR will be generated to
transfer the contents of the CUCR (second data byte) into this register and then to the Bus-In lines.

5.5.11 Tumble Table Index (TTNDX)
The TTNDX is shown on Drawing No. D-BS-DX1I-B-14. It holds the low-order address of the next tumble table
entry. It is shifted left before being copied into the DXBA.
M238s are used to form this incrementing counter. It is incremented by COUNT TTNDX, the AND of BANX
and CLKPI. The register can be cleared by either ON or the signal DXRESET OR INIT, which forms the signal
TTNDXCLR.

5.5.12 Control Unit Address Register (CUAR), Part of DXCA
The CUAR byte of the DXCA is shown on Drawing No. D-BS-DXI1-B-15.
of DBUS <07:00> or BUSO (07:00>.

The register holds either the contents

The data inputs of each flip-flop are multiplexed by Ml21 s so that in Phase 0, TS2, on an ISS when BYPAS=O,
ARSO is generated to copy the address on Bus-Out into this register. When DATO EN LOW/\LOCKO (0)/\ADRS02
are true, eUAR DATA LOAD transfers the DBUS contents to this register.
Clocking is the OR of both data conditions, ANDed with CLKNI. The flip-flops are direct-cleared by CLR CUAR,
the AND of CLKNI and DX RESET.
5.5.13 Control Unit Command Register (CUCR), Part of DXCA
The eUCR byte of the DXCA is shown on Drawing No. D-BS-DXII-B-16. This register holds the last command
byte as transmitted from the channel during an ISS, even if it was rejected by the DXll-B. It also holds the
second data byte received from the DBUS, which is stored as the second tumble table entry for a specific device
upon completion of the CH/CU transaction. This register is read-only; it cannot be loaded by program.
The data inputs of each flip-flop are multiplexed by M121 s. In Phase 2, TS 1, CRSO I is generated to transfer the
command on Bus-Out to this register and simultaneously drop Address-In.
In Phase 5, TS2, if BALF is aI, CRS02 is generated to transfer BUSO into the odd byte of this register.

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In Phase 6, TS2, CRSRND is generated to transfer the high byte of DXND into this register during a PDP-II
output operation.
As in other DXII registers, clocking is a function of data gate enables ANDed with CLKNI. Direct-clearing occurs
on DX RESETI\CLKNI.
5.5.14 Unibus Interface
The Unibus interface is shown on Drawing No. D-BS-DXII-B-17, Sheets 1 and 2. Referring to Sheet 1, there
are some differences in this interface from the standard configuration, particularly in the way the M105 is used.
In this arrangement, Slave-Sync is not taken from this chip, and the Select 0, 2, 4, and 6 outputs are also ignored.
NOTE
These outputs are here and can be used for maintenance purposes, if desired, but the pins do not appear on the wire list.
In the DXII-B, test point L2 is used to yield ADRS SELD L, which indicates that Master-Sync and all the bits are
compared with the jumpered combination. Signals OUT LOW H, OUT HIGH H, and IN H are used for their normal functions. Note that BUS A (04:01> are not applied to the MI05, but are received directly from the bus and
buffered by the receivers on Drawing 17.
This device recognizes blocks of 16 addresses. Whenjumpered, 3, 4, and 5 must match all the time. The module
isjumpered for the address 7762xx or 00-37.
The circuit is synchronized with high clock, i.e., the M205 is clocked with negative clock using the trailing edge
or the rise of NCLKI to high.
Operation can be traced by referring to the timing diagram provided at the bottom of the page. As soon as an
address match is seen, ADRS SELD L is asserted, putting a low on the SEL SYNC flip-flop data input, and, by
inversion, removing direct-clears on both flip-flops. At the next clock pulse, SEL SYNC will set and wait for the
next sequential clock. When it arrives, the STROBE-SYNC flip-flop will set, putting Slave-Sync out on the bus.
Data is loaded at the spike shown on DATO EN coincident with the leading edge of the clock pulse. This scheme
locks the Unibus to the DXII-B clock for strobe, eliminating a need to change clocks. The IBM interface is also
strobed with this clock so that everything happens at the same clock and contention problems are eliminated.
ADRS SELD L is also used to enable a utility MISS in the center of the page where the four address bits A (04:01>
are again decoded to provide address lines for use throughout the machine. They go to various gates to load
registers.
The rest of the operation is standard PDP-II interchange.
Sheet 2 shows the drivers and receivers on the Unibus. This is standard with two sets of drivers (BUS A <15:00)
and BUS D <15:00», and two sets of receivers (DBUS <15:00) and A (04:01». Inputs are from the DXBA, DXND,
and MUXD lines and are described in Paragraph 5.5.16. Enables (ADRS TO BUS H and DATA TO BUS H) are
generated on the NPR and INT Control on Drawing 18. Extended address bits BUS A (17: 16) are generated in
the CUSR as a result of DXBA CRY created on Drawing 07.
5.5.15 NPR and INT Control
The NPR and 'INT control is shown on Drawing No. D-BS-DXII-B-13. This is the classic version of the PDP-II
control and, as such, will not be discussed here. For more information, refer to PDP-11 Peripherals Handbook
Interfacing-Programming. The priority is usually set at 4.

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5.5.16 Data Bus Multiplexer
The data bus multiplexer is shown on Drawing No. D-BS-DXII-B-19. This circuit comprises sixteen M1713
modules which are 16-to-lline data multiplexers. The outputs, labeled MUXD 05:00> L, are fed directly to the
Unibus interface on Drawing 17. Note, once again, that by subtracting 10 from the location number the bit
number can be derived.
Address bits A (04: OI>, received and buffered from the Unibus, are applied to all multiplexers as enabled by
EN DATA TO BUS L. This arrangement takes each and every register in the DXII-B and gives back data to the
Unibus. Each multiplexer represents a bit slice of those registers.
These Ml713s are open-collector out, feeding directly to the M798s on the interface. Since the M798 contains a
lK resistor to +5V on the board, they can be plugged directly together.
5.5.17 Clock, Phase and Time State Generator
The Clock, Phase and Time State Generator is shown on Drawing No. D-BS-DXII-B-20. In this circuit, a basic
200 ns clock is generated by an M405 at B31, producing three free-running pulse trains, NCLKl, NCLK2 and
PCLKI. The NCLK is also fed through an AND gate to produce CLKPI and CLKP2. This is further inverted to
produce gated CLKN signals.
The AND gate producing the CLKP and CLKN signals is used to provide a Maintenance Clock mode, and is enabled
only by CLK GATE a function of the Maintenance Mode, made up of two flip-flops: a) Maintenance Clock Enable
(DXESI 01), ilnd b) Maintenance Clock flip-flop (DXESI 00).
Under normal circumstances, the 5 MHz clock NCLK and PCLK is free-running throughout the DXl1-B; but
when the DXll is placed in Maintenance Clock mode by setting bit 01 in register 14 (DXES), the normal clock is
disabled. As long as that bit is set, a clock pulse (CLKP and CLKN) is generated only when the Maintenance
Clock flip-flop is set by DBUSOO (in DXES). This flip-flop is arranged to reset when it sets, producing a single
pulse. The switch on the left-hand side of the drawing is located on the EPO panel and designated SINGLE STEP.
Pulsing this switch will produce the same result. Note that the SSTF flip-flop will complement on each closure as
its (0) L side is recirculated. The setting of SSTF will AND with PCLKI to produce SSP which, in turn, can also
clock the Maintenance Clock flip-flop. The Maintenance Clock flip-flop will then clear SSTF.
The rest of the circuit is involved in setting time states and phases. As described in the flows, it is these states
that control the operating modes of the entire DXII-B. The free-running clock output is used to complement the
time state flip-flop (TSFF) which is then used to condition a 16 output decoder (MI55B24). The binary combinations of the three signals PHO, 1, and 2 determine the eight possible phases, while TSFF determines which of
two possible states the machine is in. This results in a 16-time-compartmented structure expressed in PHS terms
(Phase/State) to control the machine.
TSFF complements every 200 ns from a clock pulse width of 60 ns or less. The indicator for this function looks
at TSFF (1) or TSI. When the indicator is out, the machine is in TS2. This is observable only when in Maintenance mode.
5.5.18 Maintenance Out Buffered Register (DXMOB)
The DXMOB is shown on Drawing No. D-BS-DXII-B-21, Sheets 1 and 2. This register holds the bits from the
Unibus (DBUS (15 :00») when addressing the DXMO while in on-line cabled mode. It is the function of these
flip-flops to provide steady levels to the drivers when in this mode.
The left-hand byte is loaded with CONO (07:00), while the right-hand byte gets BUSO <07:00>.

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Clocking is accomplished by CONOB CLK, which is the AND of ADRS1 4/\DATO EN HIGH combined with
NCLK2 for the CONO half of the register. Clocking of the right half is identical using DATO EN LOW as part
of the equation.
Clearing is a function of DX RESET OR INIT/\CLKN2 yielding four identical DXCLRP signals which direct-clear
four flip-flops each for loading purposes (actually six per board, see note on print).
At the bottom of Sheet 1 of this drawing notice a special maintenance flip-flop (SOSIEN) which eventually
results in a signal called FASTSRV. This is used in Maintenance mode to create a fast Service-Out response to a
programmed Service-In when simulating, diagnostically, an IBM sequence.
When the program loads DBUS02 and clocks it with LDADRL24 (Load Address Location 24), this flip-flop will
set yielding SOSIEN (Service-Out-Service-In Enable). Now when Service-In rises it ANDs to generate FASTSRV
(CONOBOI is CLKO when cabled). FASTSRV then goes to the IBM Interface, Drawing 27, Sheet 1, where at
location 4B it ANDs with OFFLINE to immediately generate Service-Out. Note that -FASTSRV H is equivalent
to FASTSRV L.
A special condition exists on the CONOB07 flip-flop. Its direct-clear is also used to direct-set that flip-flop. The
two gate delays (MIll) on DXCLRPI permit the direct-setting of that flip-flop after the pulse has gone away.
Therefore, upon every clear of this register, this flip-flop is set to signal OPLO.
5.5.19 General Controls
The general controls are shown on Drawing No. D-BS-DXll-B-24. This circuit comprises the control signals for
the DXII-B. The logic is straightforward and can be reviewed with the flow diagrams discussion in Paragraph
5.4.2.3. Because of this, the logic will not be discussed in great detail. Some signal mnemonics are obscure, such
as the signal BLAST, generated at coordinates Bland used as one possible condition for generating SET PH4
(coordinates C3). This signal is one of the IBM reset conditions which tells the DXll to get off the bus.
Relating one signal on Drawing 24 to the flow diagram Drawing 04, Sheets 6 and 2, DX RESET (Drawing 24,
coordinate B3) can be generated by SIG 17/\-STOP. This is verified on Drawing 04, Sheet 6, coordinate C7, where
SIGl7 implies Phase 7, TS2.
Consider also the signal ON OFFT at B6. This is an on/off transition signal used to get off the channel. To
accomplish this transition in accordance with IBM protocol, LOCKOUT must be down, with no outstanding stack
status, no command chaining indicated, and in-tag lines cleared. This insures that the DXll is not doing a thing
when the on/off transition occurs. Note that on Drawing 11, Sheet 4, if the program raises ONLINA (an on-line
request) it ANDs with ON OFFT to put the DXIl-B on-line (ONLlNB).
All other signals in this circuit can be so related by cross reference.
5.5.20 Signals and Gates
The Signals and Gates are shown on Drawing No. D-BS-DXIl-B-25, Sheets 1 through 3. As with Drawing 24,
the signals generated on this drawing can be correlated in the flows. Some mnemonics may be obscure, such as
BANX, which means the DXBA +-TTNDX, or BANDSO which means the DXBA +-DXND and BUSO, or NDCRSR
which means the DXND+-CUCR and CUSR; for the most part, the logic is straightforward and does not demand
explanation.
Sheet 3 illustrates the means whereby the DXll timeout is set. The M908 connector at F02 is provided for the
installation of external capacitors for this purpose.

5-48

By installing three 180 Jl.F caps across DIlL!, CI/MI, and B IINl, an effective 540 Jl.F of capacity is added to
the M306 to set that oneshot to approximately 5 sec. This functions to take the DXII-B off of the channel
arbitrarily if the DXll holds the channel with Operational-In raised for longer than that time period. The disable
flip-flop for DXTMO is clocked by LDADRL24 with DBUS03 as data. The DXTMO flip-flop is cleared by DXll
RESET OR INIT.
5.5.21 Parity and Address Compare
The Parity and Address Compare is shown on Drawing No. D-BS-DXII-B-26. This circuitry provides the means
whereby the DXII-B recognizes its CU and DEV address and checks the parity of that address.
The MISS Decoder at Al9 is enabled by ADRO (I) and PAROK. This means that address recognition will not be
made unless an address is actually tagged on the BUSO and then only when it has been determined that the parity
on that address is "odd". If parity compares to be "even" after addition of the parity bit, PAROK will not be
generated and the address decoder module will not be enabled.
The parity comparators are standard modules. Notice that parity is generated on both Bus-In and Bus-Out. On
output the EVEN generated by a compare and PARO, which the channel sends, produce PAROK. This represents
"odd" parity.
The parity comparators utilize the eight bits of the IBM hexadecimal address. Although there are IBM bits 0-7,
the DXII-B designates them as bits (07:00) (see the conversion table at the top-left of Drawing 27). This hardwired conversion is made in the DXII-B/IBM Interface on that drawing.
Address decoding is split into two parts: a) Control Unit Address (CUA) utilizing the four IBM bits 0-3
(BUSO (07:04», and b) Device Address derived from IBM bits 4-7 (BUSO (03:00». The first portion of this
module is hardwired, while the second portion can be either hardwired or programmed.
The MISS at Al9 is capable of recognizing up to 16 possible CU addresses (O-F in hexadecimal notation) as set
by BUSO (07:04). These outputs are all made available at an M908 jumper board at A20 which limits the total
number of addresses recognized to 8 of the possible 16.
If 8 CU addresses are to be recognized, jumpers are installed in alphabetical order from any 8 pins (AI through
VI) to V2 through M2 shown as part of the second appearance of A20 in the center of the page (see sample at
left-hand comer of Drawing 26).
If less than 8 addresses are required, all unused pins beyond the last one used are wired to that last pin. The
example illustratesjumpering for just one CU address (IX).
This arrangement responds to just the first digit of a two-digit address. Note that these decoded outputs are
ORed at Ml19B21 as one leg of an AND gate which yields ADRECC (Control Unit Address Compare).
The second digit can be ignored if desired by grounding pins B2, E2, H2, and K2 as shown in the example. If
more than one device address is involved in the installation, this ground can be removed and pins L2 through J2
wired to B2 through K2, allowing recognition of up to 16 device addresses for each of up to 8 control unit
addresses.
This is done by allowing the program to compare the low-order bits in the CUAR with BUSO (03:00).
These bits now AND to form the second leg of the AND at B 18 that yields ADRECC. They are also ANDed as
device compare (DEVCOM) with ADRECC to yield ADRECD. These two outputs then comprise the entire
address recognition in Phases 1 and 2 to process the DXII-B to its next called for phase.

5-49

5.5.22 IBM Interface
The IBM Interface is shown on Drawing No. D-BS-DXII-B-27, Sheets I through 6. It is here that bit numbering
and assertion levels are converted from IBM standard to DEC standard.
The table in the upper right-hand corner of Sheet I gives the conversion of bit numbering. Note that no bits are
shifted or reversed. Bit streams are not altered here, just renumbered to conform with PDP-II format.
NOTE
The fact that the PDP-II numbers bits from right to left does
not in any way alter the significance of any bit with respect to
other numbering schemes. DXII-B bit 00 is equal to IBM bit 07,
etc.
Sheet 1 of this drawing lists all signals received from the channel, and Sheet 2 shows all signals the DXII sends to
the channel. Sheet 3 provides the cable connectors for these signals. Sheets 4 and 5 are devoted to the test bus
signals, with Sheet 6 containing those connectors.
The M597 module, used on Sheet 1, contains an added inverter that performs a double inversion function on
BUSO signals. These signals are high when true. When ONLINE I is high and when BUSOUT 0 is high (true) a
logic mismatch occurs at the input to the OR yielding BUSO 07 H as a default triggering of the logic.
There is no logic mismatch in the lower gate in which the buffered versions can be high when OFFLINE is also
high.

This pattern of logic repeats on all receivers of this interface. Note that it is at this point that the format numbering is converted.
5.5.23 Select Bypass and Power Fail
Select bypass and power fail circuits are shown on Drawing D-BS-DXII-B-29. This is a composite drawing showing the sources for the various signals used by this G890 module at location FO 1. The timing for this operation
is shown in Figure 5-18.
In the IBM 360/370 System, selection of all control units (the DXII-B being one) for communication with the
channel is controlled by the signals SELO and HLDO. This signal is routed serially through the "select" circuitry
of all CUs, permitting each to respond to it sequentially if that CU recognizes its address, decoded elsewhere in the
CU. The HLDO signal is used to provide synchronization of CU selection.
If recognition occurs, the CU seizes SELO and prevents it from being propagated to the next CU on the line.
If recognition does not occur, the signal is passed on down the line. If no CU recognizes the address sent, SelectOut becomes Select-In to the channel,.indicating to the channel that no CU responded. Figure 2 of the IBM OEMI
manual illustrates this scheme.
Additionally, if any CU is powered down, if power has failed, or if the CU is off line, the Select line is automatically routed through normally closed contacts of the relay and the "select-seize" logic is bypassed.
Note from Drawing 29 that if the DXll is on-line (-OFFLINE L) and power is up (-DCLO L), the Select-Out
relay will pick allowing the SEL OUT signal to enable the data input of the SELO flip-flop. Note also that this is,
in turn, latched by the signal Hold-Out (HLDO). This is a parallel signal to all CUs to permit an immediate drop
of the select bypassing relay when Select-Out from the CH drops and normally does not rise for 4 /J.S after it falls.

5-50

ONLINB (1) H is delayed for 5 ms when the DXII-B goes from on-line to off-line or off-line to on-line to
ensure that SELO is propagated by the DXII-B during the period required to change the contacts of the relay
which propagates SELO (see Figure 5-18).
5.5.24 "Bit Slice" and "Select" Loop Trace in Off-Line Cabled Mode
This paragraph is devoted to tracing the Select-Out signal and one bit through the DXII-B when it is operating
in off-line cabled mode. The purpose is to provide familiarity with the general routing of these signals so that any
bit can be traced if needed. This mode of operation is chosen so that all DXII-B circuitry can be covered, including the connectors to and from the IBM channel.
Figure 5-19 illustrates the path for BUS OUT3. Note the bit number conversion as shown on Drawing 27.
Figure 5-20 illustrates the routing of the Select-Out signal as received from the channel bus on Drawing 27.
Note that SEL OUT A, after passing through the G890 at FO, becomes SEL OUT B out to the system, through
the jumper on the last unit. It then returns as SEL IN B and is returned to the channel as SEL IN A.
5.5.25 EPO Panel Operation
The DXII-B miscellaneous control and EPO panel is shown schematically on Drawing D-CS-7008792-0-1, and is
illustrated in Figure 3-1. The panel provides the only I operating controls on the DXII-B, with the exception of the
Power Contactor.on the H740 Power Supply and 861 Power Control and operates in conjunction with the standard IBM\ Power Control Interface. A general description of all IBM Power Interfaces is given in IBM Document File
No. S360-19 GA22-6906-0 "IBM System/360 Power Control Interface Original Equipment Manufacturers' Information". The operation of the DXII-B interface conforms to the requirements described in that document.
In IBM systems, all units are powered from the main CPU of the system. In addition, application of power to these
elements is not applied at once, but rather is applied sequentially to each element thereby reducing overall power
requirements and minimizing noise generation from power surges. Each element is equipped with a set of standard
relays, switches, and indicators, together with a unit power source; and all elements usually operate in some mode
of remote control although most can also operate in a local mode. Finally, each unit can be disabled immediately
by operation of the Emergency Power Off (EPO) button located on the front panel of the 360/370 Console.
Operation of this button is unlikely except in cases of extreme emergency.
Referring to the diagram in Drawing 7008792, the DXII-B Unit Power Source (approximately 12.6 V dc) is provided by Tl feeding an MDA 980-1. Note that this supply is always powered as long as the DXll power cord is
connected to ac power. When operating on 120 Vac, pin 1 of TB2 is left floating. The diagram entitled EPO
TIMING on the drawing describes the sequence of operation.
With the LOCAL PWR ON switch closed, power is complete to the H740 Power Supply.
With the LOCAL/SYSTEM switch in LOCAL position, power from the unit power source is complete through
pin 1 of EPO connector J 1, through the contacts of the EPO switch on the IBM console to the NC contacts of the
LOCAL/SYSTEM switch, through the coil of K3 to -V. This closes contacts 8 and 6 of that relay to apply power
to the H740 Power Supply. The upper switch contact provide a "step by" capability of the IBM stepping switch
if power sequencing is initated by the 360 when the DXll is in LOCAL mode.
With the LOCAL/SYSTEM switch in SYSTEM position, unit source power (always powered) is complete through
the EPO switch, through pin 2 of J 1 (CPO CONTROL) to -V, through the coil of Kl which closes it contacts 1
and 3. When the Power switch is closed, ani when the step control switch is advanced to the DXII-B position,
unit source power is complete through pin 6 of 11 (l:'WR PICK) and the now closed conhcts of Kl to -V through
the coils of K2 and K3. When contacts 1 and 3 of K2 close, system source is complete through pin 5 of J 1
(PWR HOLD) and the PWR HOLD indicator on the :h?0 panel is complete through contacts 8 and 6 of K2.
5-51

5ms -----~.I

r - - - 2 - 3 m s - - -.....oI:

1
1

I
HLDO

SELO _ _ _ _...J

ONLlNA (1) H

SEll BR H _ _ _ _ _-.-J

(FROM

SELO PROP.
BY RELAY _ _ _ _ _...J

RELAY TURNED ON

------',r - -

S~fLOA}l _ _ _ _ _ _ _ _ _ _ _ _ _- - ' / :

SELO PROP. VIA SEll
DRIVER (OFFLINE) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'.

....LJIF ~ 200ns

SELO (1) H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

2::200ns

ONLlNB (l) H

SELO PROP. VIA SEll
DRIVER (ONLINE) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'

ONOFFT _ _....J
ONLINE TO OFFLINE

OFF LINE TO ONLINE

11-3399

Figure 5-18 OFF to ON and ON to OFF Line Transition Timing

r - - - MATED DURING TEST- - - I
(TO THE NEXT UNIT)

-,
I

DARK

r---

-- :1:;----,

BUS OUT 3

ON LINE-+-----------.::..J,!.~...I'i

BUSO 04
OFFLINE-~-----------~~_v

r----------,
I

BUSOB CLKB

I BUSOB 04 (0)

Or--r~~~~~---J

C
M216

A14

~DB~U~S~0~4~_ _~D

1r--+_~B~US~0~B~0~4~(1~)--------_r~
+3V--;...__ ,

I DWG
21 _ _ _ _ _ _ _ ..JI
L..:
__

~~~-------~-------------~
11-1272

Figure 5-19 One Bit Slice Loop Trace

5-52

TURN AROUND JUMPER IN
TERMINATOR,LAST UNIT
TO NEXT CU

FROM/TO
THE CH

,--.....

009 IBM CONNECTOR

ri~r--E~-': - -

- -

- -;;;, ~_;;-- - -

- -

r - - - - - - - -l
DWG 29
GB90
FO.

•

IBM CONNECTOR 009

- J14- -

- LIGH~TI:::DO~9+-~~~

- - -,

P2~;--LI__~~S~E~L~0~~~B~r-~

V2
R2~~-L__~-rS~E~L~IN~B~-.____~
T2

:
L L ________ J J
-... --------L ___________
I

- -

II
L __________________________________ J
~W~!7_ _ _ _ _ _ _ _ _ _ _ _ .JI

11-1273

Figure 5-20 Select-Out/Select-In Loop Trace

When contacts I and 3 of K3 close, stepping relay power is complete through pin 3 of 11 (SYSTEM SRC) and
returns through pin 4 (PWRING COMP) to step the switch to the next unit in the sequence. Power on the DXII-B
is now held on by the unit source through contacts I and 3 of K2, and coil of K3.
Once this sequence is complete, power is removed if either the Power switch is opened or if the EPO contacts are
opened.
If the Power Switch is opened, PWR HOLD is lost dropping both K2 and K3. KI remains energized, ready for
another power-up sequence.
If the EPO contacts are opened, Kl also drops and EPO CONTROL is lost. Under these circumstances, remote

powering of the DXII-B cannot be accomplished until they are once again closed.
The other controls on this panel are all interconnected by PI and TB I. Pin C2 is ground. The SINGLE PULSE
switch interconnects with Drawing 20 where it is used to activate two AND gates in cross-conjunction which, in
turn, clock the SSTF flip-flop.
ACLO and DCLO sensing from the H740 Power Supply is sent to Drawing 18 to yield the signals ACLO and
DeLO.
The ONLINE ENABLED switch sends ground to Drawing 29 where it activates a cross-conjunction flip-flop to
yield ONLINE EN SW Hand L. In the enable position, it causes the ONLINE ENABLE indicator on this panel
to glow.

5-53

CHAPTER 6
MAINTENANCE

6.1 INTRODUCTION
Maintenance philosophy of the DXII-B is based on the premise that an optimum amount of preventive procedures,
performed regularly, can eliminate many costly equipment breakdowns and can forecast failures before they
occur. The design is such that, in the event of failure of a specific item, module replacement can restore the
equipment to service in a minimum of time. This chapter contains both preventive and corrective maintenance
procedures.
6.2 PREVENTIVE MAINTENANCE
Preventive maintenance consists of tasks performed at periodic intervals to ensure proper equipment operation
and minimum unscheduled downtime. These tasks consist of running diagnostics, visual inspection, operational
checks, adjustment, and replacement of marginal components.
The preventive maintenance schedule depends on the environmental and operating conditions that exist at the
installation site. Under normal conditions, recommended preventive maintenance consists of inspection and
cleaning every 600 hours of op~ration or every 4 months, whichever occurs first. However, relatively extreme
conditions of temperature, humidity and dust demand more frequent maintenance. It is recommended that
the IBM 2848 Diagnostic be run once a week as part of the normal preventive maintenance schedule.

6.2.1 Mechanical Checks
Inspect the DXII-B periodically as follows:
a.

Visually inspect the unit for general condition.

Clean the interior and exterior of the rack using a vacuum cleaner or a clean cloth moistened in nonflammable solvent.

Inspect all wiring and cables for cuts, breaks, frays, deterioration, kinks, strain, and mechanical security.
Tape, solder, or replace any defective wiring or cable covering.

6.2.2 Test Equipment Required
Maintenance activities for the DXII-B require the standard test equipment and diagnostic programs listed in
Table 6-1, in addition to standard hand tools, cleaners, test cables, and probes. Special test equipment required
for any adjustments are given as part of the adjustment procedure.

6-1

Table 6-1
Test Equipment Required
Equipment

Manufacturer

Designation

Multimeter
Oscilloscope
XIO Probes (2)
Module Extender
Diagnostic Self-Test Routines

Triplett or Simpson
Tektronix
Tektronix
DEC
DEC

Model 630-NA or 260
Type 453
P6008
Type W980
MAINDEC-II-DZDXA
MAINDEC-II-DZDXB
MAINDEC-II-DZDXC
MAINDEC-II-DZDXD
MAINDEC-II-DZDXE

6.3 CORRECTIVE MAINTENANCE
The procedures that follow are based on standard troubleshooting techniques. Once the defective module has
been located, replace it with a spare module and return the defective module to DEC for repair or replacement.
6.3.1 General Corrective Procedures
Before beginning troubleshooting procedures, ensure that the equipment external to the DXII-B is operating
correctly. Check with IBM CE and refer to PDP-II maintenance manuals to determine status. Also, examine the
DXII-B Maintenance Log to determine if the fault has occurred before and, if so, note what steps were taken to
correct the condition.
NOTE
A recurring fault can indicate a common uncorrected fault elsewhere.
Visually inspect the physical and electrical security of all cables, connectors, modules, and wiring. In particular,
check the security of ground connections between racks. Faulty grounds can produce a variety of faults.

6.3.2 Diagnostic Testing
DEC provides special diagnostic programs (MAINDECs) to assist in localizing faults within the equipment.
Functionally, the programs fall into two categories: test and reliability. Test programs isolate genuine go/no-go
type hardware failures that are easily recognizable; reliability programs isolate failures that are more difficult to
detect, because they are marginal in nature and/or occur infrequently or sporadically. The family of test programs
are written so that, when run successively, they test the equipment beginning with small portions of the hardware
then gradually expand until they involve the entire machine. To accomplish this, they are built around instructions and portions of instructions whose demands on equipment capabilities progress from simple operations to
the most involved manipulations. As portions of the system are proven operable, they become available to succeeding tests for use in checking unproven portions of the machine.

6-2

In the DXII-B there are six programs comprising the diagnostic package. They include:
a.

The CTP that operates in two modes. In OFFLINE mode it exercises all the communication devices
and the DXII-B in test mode. In ONLINE mode it runs all the communication devices with the DXl1-B
driven by the 360 running, e.g., FRIEND.

The DXII-B Diagnostic that provides a detailed off-line logic checkout of the DXII-B hardware.

DECX 11 off line diagnostic.

A RESPONDER for the IBM 2848 diagnostic.

A 360 program to checkout the DXl1-B hardware and software in the 2848 mode of operation.

FRIEND, a 360 CCW generator program that generates arbitrary CCW strings to check operator
requested functions of any IBM Cu.

6.3.3 Vibration Tests
Intermittent malfunctions can be located usually by performing a vibration test. This aggravates a condition that
otherwise might not be located. To perform a vibration test, proceed as follows:
1.

Check switches for immunity from vibration and shock by wiggling them and tapping them with the
fingers.

Check modules for immunity from vibration and shock in two planes. To check the plane perpendicular to the module mounting plane, tap each module handle with the fingers. To check the plane
parallel to the module mounting plane, slide a Teflon rod horizontally across the modules. This should
be done slowly and twice in each direction. The Teflon rod should be approximately 8-in. long, 3/8-in.
in diameter, and should be held between the fingers 6 in. from the end that is applied to the modules.
This test will indicate bad components and poor solder joints.
CAUTION
If vibration tests are applied too vigorously, damage to modules

could result. Do NOT vibrate the IBM connectors or the
G890Fl module.
After localizing the fault to within a functional logic element, run the diagnostic which uses all functions of that
element. Trace signal flow through the suspected element with an oscilloscope by synchronizing the oscilloscope
sweep with control signals or clock pulses. Check for proper levels, durations, rise and fall times, and timing of
all input and output signals.

6-3

CHAPTER 7
ENGINEERING DRAWINGS

7.1

GENERAL

Table 7-1 lists those engineering drawings called out in text. The listing is alphanumeric by drawing number and
does not include all drawings in the manufacturing set.
Table 7-1
DXI1-B Engineering Drawings
Number

Title

D-FD-DX11-B-04

D-BS-DX11-B-05

06
07
08
09
10
11
12
13
14
15
16
17
18

19
20
21

Flow Diagram (9 sheets)
Sheet 1 - Phase Independent Sequences
Sheet 2 - Phase 0 Idle or Requesting
Sheet 3 - Phase I Address Response
Phase 2 Status Preparation
Sheet 4 - Phase 3 Status Presentation
Phase 4 Mark
Sheet 5 - Phase 5 Input
Phase 6 Output
Sheet 6 - Phase 7 Done
Sheet 7 - Disconnect Response
Sheet 8 - Programmed Registers
Sheet 9 - Data Paths
DXDS DX Device Status (2 sheets)
DXCS Control Unit Status (2 sheets)
DXBA DX Bus Address
DXBC DX Byte Counter
CUSR (Control Unit Status Register) (2 sheets)
DXND NPR Data Register (2 sheets)
DXCB DX Control Bits (4 sheets)
DXMO/CONO
DXMI Control In/Bus In (2 sheets)
TTNDX Tumble Table Index
CUAR Control Unit Address Register
CUCR Control Unit Control Register
Unibus Interface (2 sheets)
NPR and INT Control
Data Bus Mux.
Clock, Phase & Time State Gen.
DXMOB - CONO BUFF!BUSO BUFF (2 sheets)
(continued on next page)
7-1

Table 7-1 (Cont)
DXI1-B Engineering Drawings
Number

Title

D-IC-DXII-B-22
D-BS-DXII-B-24
25

26
27
D-IC-DXll-B-28
D-BS-DXll-B-29
D-CS-7008792-0-l

Indicator Conn
General Controls
SIG & Gates (3 sheets)
Parity and Address Compare
IBM Interface (6 sheets)
Unibus Connectors
Select Bypass & Power Fail
Misc Controls & EPO

7-2

APPENDIX A
REFERENCE MATERIAL

This appendix contains selected data for reference by the reader. Included are a glossary of mnemonic terms and
a conversion method for hexadecimal to octal to EBCDIC notation. Further reference material can be found as
part of the appendices to the IBM System/360 Principles of Operation Manual as listed in the Foreword of this
manual.
A.I GLOSSARY
In Table A-I the signals are arranged in alphanumeric order as they appear on the block schematics. In instances
of complex signals the following notation is used:
BANDSO
Signal MLmonic

DXBA

DXND

Gits Middle 2'~tters

First 2 Letters

AND

BuS Out

Last 2 Letters

The left column contains the signal being defined; the right column contains the definition of the actions involved.
In the example, the DXBA (Bus Address Register) receives the contents of (gets) the DXND (NPR Data Register)
and the contents of Bus Out.
These mnemonics can be further clarified by reference to Drawing 04, Sheets 1 through 9.
Table A-I
DXI1-B Signal Glossary
Signal

Definition

ACLO

PDP-ll AC voltage low

ADROUT

Address Out

ADRECC

Control Unit Address Compare

ADRECD

Device Address Compare

ADRI(O)/(l)

Address In

ADRIN

Address In

ADRO

Address Out

ADRSxx

Address (Unibus) xx = 02, 04, 06, 10, 12, 14, 16, 24

ADRS SELO

Address Select Out

ADRSTOBUS

Address to Bus
(continued on next page)
A-l

Table A-I (Cont)
DXII-B Signal Glossary
Signal

Definition

ARSO

CUAR+-BUSO

ATTEN(O)/(l)

Attention

BAAR

DXBA+-CUAR

BADB

DXBA+-DBus

BAINxx

Bus Address In xx = 00-15

BALF(O)/(l)

Bus Alternator Flip-Flop

BANDSO

DXBA+-DXND·BUSO

BANX

DXBA+-TTNDX

BAOR

DXBA+-CUOR

BCMO

Byte Count Minue One

BGIN

Bus Grant In

BGODT

Bus Grant Out

BIAR

Bus In+-CUAR

BISR

Bus In+-CUSR

BIT xCOMP

Bit x Compare x = 0-3

BLAST

A "Get Off' signal resulting from IBMRST

BLLF(O)/(l)

Bus Load Limiting Flip-Flop

BLLM

Unibus Load Limiting Mono

BRODT

Break Request Out

BSY(O)/(l)

Busy

BSYEN(O)/(l)

CU Busy Enable

BSYS

Busy Sent

BUDATA

Bus Data

BUSAxx

Bus Address xx = 00-17

BUS AC LO

BusAC Low

BUS BBSY

Bus Busy

BUSBGxIN

Bus Grant In x = 4-7

BUSBRx

Bus Request x = 4-7

BUSCx

Bus Control Lines x = 0, 1

BUS Dxx

Bus Data xx = 00-15

BUS DCLO

Bus DC Low

BUS INx

Bus In x = 0-7
(continued on next page)

A-2

Table A-I (Cont)
DXII-B Signal Glossary
Signal

Definition

BUS INP

Bus In Parity

BUS INlT

Bus Initialize

BUS INTR

Bus Interrupt

BUS MSYN

Bus Master Sync

BUS NPG IN/OUT

Bus Non-Processor Grant

BUS NPR

Bus Non-Processor Request

BUS OUT x

Bus Out x = 0-7

BUS OUTP

Bus Out Parity

BUSPA

Bus Parity Available

BUSPB

Bus Parity Bit

BUS SACK

Bus Selection Acknowledge

BUS SSYN

Bus Slave Sync

BUSI

IBM Bus In Register

BUSI xx (0)/(1)

Bus In xx = 00-07

BUSO

IBM Bus Out Register

BUSOxx

Bus Out xx = 00-07

BUSOB xx (0)/(1)

Bus Out Buffered xx = 00-07

BUSOB CLKA/B

Bus Out Buffered Clock

BYPAS(O)/(l )

Bypass

CAW

Channel Address Word

CCW

Channel Command Word

Channel End

Channel

CHDEND

Channel Data End

CHEND(O)/(l)

Channel End

CHENDS

Channel End Sent

CHIS(O)/(l )

Channel Initiated Sequence

CLINTR

Clear Interrupt

CLKGATE

Clock Gate

CLKOUT

Clock Out

CLKNI/2/3

Negative Clock

CLKO

Clock Out
(continued on next page)

A-3

Table A-I (Cont)
DXII-B Signal Glossary
Signal

Deimition

CLKPI/2

Positive Clock

CLRCUAR

Clear the CUAR

CLRCUCR

Clear the CUCR

CLRCUSR

Clear the CUSR

CLRDXBC

Clear the DXBC

CLRDXCB

Clear the DXCB

CLRDXCS

Clear the DXCS

CLRDXDS/A

Clear the DXDS

CLRDXMI

Clear the DXMI

CLRFCTN

Clear the Function

CLRIRC

Clear IBM Reset Conditions

CMDOUT

Command Out

CMDCHN

Command Chain

CMDO(O)/(l)

Command Out

CMDREJ

Command Reject

CMDSRV

Command Service

CONI

Control Lines In Register

CONIZ

Control Lines In Zero

CONO

Control Lines Out Register

CONOCLKA/B

Control Lines Out Clock

CONOB xx(O)/(l)

Control Lines Out Buffered xx = 00-07

CONOB CLKA/B

Control Lines Out Buffered Clock

COUNTBA

Count Bus Address

COUNTBC

Count Byte Counter

COUNTTTNDX

Count Tumble Table Index

CRSO

CUCR+-BUSO

CRSRND

CUCR+-CUSR· DXND

CSW

Channel Status Word

Control Unit

CUAxxX

Control Unit Address xx = 00,02,04,06, 10, 12, 14, 16,20,22,24,26,
30, 32; 34, or 36
X - Device Address
(continued on next page)

A-4

Table A-I (Coni)
DXII-B Signal Glossary
Si.gnal

Definition

CUAR xx(O)!O)

Control Unit Address Register xx = 00-07

CUARCLKA!B

Control Unit Address Register Clock

CUAR DATA LOAD

Control Unit Address Register Data Load

CUBSY(O)!( 1)

Control Unit Busy

CUCR xx(O)!( 1)

Control Unit Command Register xx = 00-07

CUCRCLK EN

Control Unit Command Register Clock Enable

CUCRCLKA!B

Control Unit Command Register Clock

CUD

Control Unit Done

CUD END

Control Unit Data End

CUDX(O)!(1 )

Control Unit Data Control

CUEND(O)/( I)

Control Unit End

CUFBM(O)!( I)

Control Unit Forced Burst Mode

CUI5

Control Unit Initiated (Input)

CUI6

Control Unit Initiated (Output)

CUORxx

Control Unit Offset Register xx = 10-15

CUSR

Control Unit Status Register

CUSR CLK EN/ A

Control Unit Status Register Clock Enable

CUSRNZ

Control Unit Status Register Non-Zero

DATA IN

Data In

DATA OUT

Data Out

DATA STROBE

Data Strobe

DATA TO BUS

Data to Bus

DATA WAIT

Data Wait

DATa EN HIGH/LOW

Data Out Enable

DATOK

Data OK

DBUS xx

Data Bus xx = 00-15

DCLO

DC Low

Device End

DEV

Device

DEVCOM

Device Compare

DEVEND(O)!(1)

Device End
(continued on next page)

A-5

Table A-I (Cont)
DXll"B Signal Glossary
Signal

Definition

DIS DXTO(O)/(l)

Disable DX Timeout

DISC IN

Disconnect In

DONE

Done

Data Sequence

DSCRSP(O)/(l )

Disconnect Response

Data Transfer

DXII-B

DXBAxx

NPR Address Register xx = 00-15

DXBACRY

NPR Address Register Carry

DXBC xx

DX Byte Count Register xx = 00-15

DXCA

DX Command & Address Register

DXCB

DX Control Bits Register

DXCLRPI/2/3/4

DX Clear Pulse

DXCS

DX Control Unit Status Register

DXCSCLKA

DXCS Clock

DXCS CLKEN/A

DXCS Clock Enable

DXDS

DX Device Status Register

DXESI/2

DX Extra Signals Register

DXMI

DX Maintenance In Register

DXMO

DX Maintenance Out Register

DXMOB

DX Maintenance Out Buffered Register

DXND xx(O)/(l)

DX NPR Data Register xx = 00-15

DXNDCLKA/B

DXNDClock

DXND STB A/B

DXND Strobe

DXOS

DX Offset and Status Register

DXRESET

DX Reset

DXRESET OR INIT

DX Reset or Initialize

DXTO

DXTimeout

EN DATA TO BUS/A

Enable Data to Bus

EN FCTN

Enable Function

ENABLE

Enable

END CYCLE

End Cycle
(continued on next page)

Table A-I (Cont)
DXI1-B Signal Glossary
Signal

Definition

ENDEN

End Enable

EPO

Emergency Power Off

ERRSTA

Error Status

Ending Sequence

ESEND

Ending Sequence End

ETAP

Emulator Terminal Applications Program

EVEN

Even

FASTCU

Fast Control Unit Response to an ISS while busy

FASTSRV

Fast Service-In Response to Service-Out while in Test Mode

FASTX

Fast Control Unit Response to INFDSC

FCTNCLK

Function Clock

FCTNI /2(0)/0)

Function

FTCU

Fast Control Unit Response While Busy

FUNEQO/I/2/3

Function Equals

HIO

Halt I/O

HLDOUT

Hold Out

HLDO/(l)

Hold Out

IBMRST

IBM Reset

INBA 08

In Bus Address Bit 08

INFDSC(O)/( I)

Interface Disconnect

INIT

Initialize

INMSTR

Interrupt Master

INTEN

Interrupt Enable

INTENCLKEN

Interrupt Enable Clock Enable

IOD

I/O Done

IRCCLR

IBM Reset Conditions Clear

IRS(O)/(l)

IBM Reset Stored

ISS

Initial Selection Sequence

ISSREJ(O)/(l )

ISS Reject
(continued on next page)

A-7

Table A-I (Cont)
DXll-B Signal Glossary
Signal

Definition

LDADRL 24

Load Address Location 24

LOAD BUS DXMI

Load Bus DX Maintenance In

LOADDXBA

Load DXBA

LOADDXBC

Load DXBC

LOCKO(O)/(l)

Lockout

Modifier Bit

MARK IN 1/0

Mark In

METER IN

Meter In

METER OUT

Meter Out

MNCLEN(O)/( 1)

Maintenance Clock Enable

MNCLKF(O)/( 1)

Maintenance Clock Flip-Flop

MPX

MUltiplexer Channel

MUXDxx

Multiplexed Data xx = 00-15

NCLKI/2

Negative Clock

NDCRSR

DXND+-CUCR·CUSR

NDDB

DXND"'<-Data Bus

NODST

No Offset to Device Status Table

NPMSTR

NPR Master

NPRDLY

NPR Delay

NPRT(O)/( 1)

NPR Transfer Direction

NPRTO(O)/(l )

NPR Timeout

NPRX(O)/(l)

NPR Transfer

NPTDON(O)/(l )

NPR Transfer Done

NXM(O)/(l)

Non-Existent Memory

ODD

Odd

OFFLINE

Off Line

OFFRCVREN

Off Line Receivers Enable

ONUNA

On Line A

ONLINB(O)/( 1)

On Line B

ONLINE

On Line

ONLINE ENSW

On Line Enable Switch
(continued on next page)

A-8

Table A-I (Cont)
DXll-B Signal Glossary
Signal

Defmition

ONLINE I

On Line I

ONOFFT

On/Off Transition

OPLIN

Operational-In

OPLOUT

Operational-Out

OPLI(O)/(l)

Operational-In

OPLO(O)/(l)

Operational-Out

OUT HIGH

Out High

OUT LOW

Out Low

PARER

Parity Error

PARI

Parity In

PARO

Parity Out

PAROK

Parity OK

PARSTP

Parity Stop

PCLKI

Positive Clock

PDPTO(O)/( I)

PDP Timeout

PHx(O)/(l)

Phase x = 0, I, 2

PHSx I x 2

Phase State xl =0-7, x 2 = 1,2

PSW

Program Status Word

PWROKRLY

Power OK Relay

RADRI

Received Address-In

RBUSIxx

Received Bus-In xx = 00-07

RBUSIP

Received Bus-In Parity

REQIN

Request-In

REQI(O)/( I)

Request-In

REQIN

Request-In

ROPLI

Received Operational-In

RREQI

Received Request-In

RSELI

Received Select-In

RSRVI

Received Service-In

RSTAI

Received Status-In

SEL

Selector Channel

SELIN/A/B

Select-In
(continued on next page)

A-9

Table A-I (Cont)
DXII-R Signal Glossary
Signal

Definition

SEL OUT/A/B

Select-Out

SEL SYNC

Select Sync

SELECT

Select

SE1I(O)/O)

Select-In

SELO(O)/( 1)

Select-Out

SELRST(O)/( 1)

Selective Reset

SENSE

Sense

SETPHx

Set Phase x = 0-4

SICR

BUSI*-CUCR

SIO

Start I/O

SISR

BuS In*-CUSR

SISREN

BUSI*-CUSR ENable

SOSIEN

Service-Out/Service-In ENable

SPW

Status Pointer Word

SRDB

CUSR+-Data Bus

SRNDH/L

CUSR+-DXND

SRNDEN

CUSR+-DXND ENable

SRSO

CUSR+-BUSO

SRVIN

Service-In

SRVOUT

Service-Out

SRVI(O)/( 1)

Service-In

SRVO(O)/(l)

Service-Out

SSP

Single Step Pulse

SST

Single Step Transition

SSTF(O)/( 1)

Single Step Transition Flip-Flop

SSYN

Slave Sync

STAIN

Status-In

STAIEN

Status-In Enable

STAI(O)/(l)

Status-In

STAMOD(O)/( I)

Status Modifier

STB/ACUSR

Strobe Control Unit Status Register

STKSTA(O)/( 1)

Stack Status
(continued on next page)

A-IO

Table A-I (Cont)
DXII-B Signal Glossary
Signal

Definition

STOP

Stop

STRSYNC

Strobe Sync

SUP OUT

Suppress-Out

SUPO(O)/(I)

Suppress-Out

SYNC(O)/(I)

Synchronization

SYSRST(O)/(l )

System-Reset

TCH

Test-Channel

TESTIO

Test-I/O

TIC

Transfer In Channel

TIO

Test I/O

TPx

Time Pulse x = 1,2

TSFF(O)/( 1)

Time State Flip-Flop

TSTADRIN

Test Address-In

TSTADROUT

Test Address-Out

TSTBUS INx

Test Bus-In x = 0-7

TSTBUS INP

Test Bus-In Parity

TSTBUS OUT x

Test Bus-Out x = 0-7

TSTBUS OUTP

Test Bus-Out Parity

TSTCMD OUT

Test Command-Out

TSTHLD OUT

Test Hold-Out

TSTOPLIN

Test Operational-In

TSTOPLOUT

Test Operational-Out

TSTREQ IN

Test Request-In

TSTSELIN

Test Select-In

TSTSELOUT

Test Select-Out

TSTSRVIN

Test Service-In

TSTSRVOUT

Test Service-Out

TSTSTA IN

Test Status-In

TSTSUPOUT

Test Suppress-Out

Tumble Table

TTNDXxx

Tumble Table Index xx = 00-07

TTNDXCLR

Tumble Table Index Clear
(continued on next page)
A-II

Table A-I (Coni)
DXI1-B Si.gnal Glossary
Definition

Signal
UCHECK(O)/( I)

Unit Check

UCHKS

Unit Check Sent

UEXCEP(O)/( 1)

Unit Exception

XBAxx(O)/( 1)

Extended Bus Address xx = 16, 17

A.2 HEX/OCTAL/EBCDIC CONVERSION CHART
Table A-2 provides a means of converting the hexadecimal representation for the keyboard functions tv .. neir
octal equivalent (Note, ASCII reference implied) and to the EBCDIC representations.
Table A-2
Hex/Octal/EBCDIC Conversion ChaIrt
Hex

Octal

EBCDIC

Hex

Octal

EBCDIC

00
01
02
03
04

000
001
002
003
004
005
006
007
012
013
014
015
016
017
020
021
022
023
024
025
026
027
030
031
032
033
034
035
036
037

NUL
SOH
STX
ETX
PF
HT
LC
DEL
SMM
VT

20
21
22
24
25
26
27
2A
2B
2D
2E
2F
32
34
35
36
37
3B
3C
3D
3F
40
4A
4C
4D
4E
4F
50
SA
5B

040
041
042
044
045
046
047
052
053
055
056
057
062
064
065
066
067
073
074
075
077
100
112
114
115
116
117
120
132
133

DS
SOS
FS
BYP
LF
ETB
ESC
SM
CU2
ENQ
ACK
BEL
SYN
PN
RS
UC
EOT
CU3
DC4
NAK
SUB
SP

as
06
07
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
lA
IB
lC
1D
IE
IF

FF
CR
SO
SI
DLE
DCl
DC2
TM
RES
NL
BS
IL
CAN
EM
CC
CUI
IFS
IGS
IRS
IUS

<
(

+
I
&
!
$

(continued on next page)

A-12

Table A·2 (Cont)
Hex/Octal/EBCDIC Conversion Chart
Hex

Octal

5C
5D
5E
5F
60
61
6B
6C
6D
6E
6F
7A
7B
7C
7D
7E
7F
81
82
83
84
85
86
87
88
89
91
92
93
94
95
96
97
98
99
A2
A3
A4
AS

134
135
136
137
140
141
153
154
155
156
157
172
173
174
175
176
177
201
202
203
204
205
206
207
210
211
221
222
223
224
225
226
227
230
231
242
243
244
245

EBCDIC

Hex

Octal

EBCDIC

A6
A7
A8
A9
C1
C2
C3
C4
CS
C6
C7
C8
C9
Dl
D2
D3
D4
D5
D6
D7
D8
D9
E2
E3
E4
E5
E6
E7
E8
E9
FO
F1
F2
F3
F4
FS
F6
F7
F8
F9

246
247
250
251
301
302
303
304
305
306
307
310
311
321
322
323
324
325
326
327
330
331
342
343
344
345
346
347
350
351
360
361
362
363
364
365
366
367
370
371

w
x
y

)

,
""1

/
,
%
-

>
?

#
@

=
"
a
b
c
d
e
f
g

h
i
j
k

1
m
n
0

p
q

s
t
u

A.3 HEXADECIMAL/OCTAL CONVERSION
To convert a hexadecimal number to octal, proceed as follows:
1.
2.
3.

Convert the hex number to binary.
Partition the binary number in 3-bit groups.
Write the octal equivalent for each 3-bit group.

A-13

A
B
C
D
E
F
G
H
I

J
K

L
M
N
0
P

Q
R
S
T
U

V
W
X

y
Z

0
1
2
3
4
5
6
7
8
9

To convert an octal number to hexadecimal, proceed as follows:
1.
2.
3.

Convert the octal number to binary.
Partition the binary number in 4-bit groups.
Write the hex equivalent for each 4-bit group.

A-14

APPENDIXB
ADDRESS ASSIGNMENTS

B.l FLOATING VECTORS
There is a floating vector convention used for communications (and other) devices that interface with the PDP· 11
computer. These vector addresses are assigned, in order, starting at 300 and proceeding upwards to 777. Table B·l
shows the assigned sequence. It can be seen that the first vector address, 300, is assigned to the first DCll in the
system. If another DC 11 is used, it would then be assigned vector address 310, etc. When the vector addresses have
been assigned for all the DCll s (up to a maximum of 32), addresses are then assigned consecutively to each unit of
the next highest ranked device (KL1l or DPII or DMll, etc.), then to the other devices in accordance with the
priority ranking (Table B·l).
If any of these are not included in a system, the vector address assignments move up to ftIl the vacancies. If a device
is added to an existing system, its vector address must be inserted in the normal position and all other addresses
must be moved accordingly. If this procedure is not followed, DEC software cannot test the system.
NOTE
The floating vectors range from addresses 300 to 777, but
addresses 500 through 534 are reserved for special bus testers.
In addition, address 1000 is used for the DSII Synchronous
Serial Line Multiplexer. Refer to Appendix A of the PDp·ll
Peripherals Handbook, 1973-1974, for a complete discussion
of Unibus addresses.

The DXll·B has four assigned Unibus addresses as follows:
DXll
DXll
DXll
DXll

#1 776200

#2 776240
#3 776300

#4 776340

B·l

Table B-1
Priority Ranking for Floating Vectors
(starting at 300 and proceeding upward)

Rank

Device

Vector
Size
(in octal)

Max. No.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

DC 11
KL11, DL11-A, DL11-C
DPll
DMll-A
DNll
DMll-BB
DR11-A
DR11-C
PA611 Reader
PA611 Punch
DT11
DXll
DL11-C, DL11-D, DL11-E
DJll
DHll
GT40
LPSll
DQll
KW11-W
DUll

10
10
10
10
4
4
10*
10*
4*
4*
10*
10*
10
10
10
10
30*
10
10
10

32
16
32
16
16
16
32
32
16
16
8
4
31
16
16
1
1
16
1
16

*The first vector for the first device of this type must always be on a (10)8 boundary.

B-2

APPENDIXC
INTRODUCTION TO THE DXII-B FLOW DIAGRAMS

This appendix describes the concepts required to understand the flow diagrams on Drawing DXII-B-04, sheets I
through 9.
C.l DETAILED DESIGN FLOWS
The DXII-B is designed into a matrix of time states and logic phases. Each logical operation, gating, or enabling
condition is valid only during particular time states on the leading edge of the clock pulse (Figure C-1). That is, if
all conditions are met to perform an operation then that operation will actually take place when the appropriate
SO ns time pulse occurs. For example, data is usually enabled to the BUSI flops during time state one (TSl) and
those flops are actually changed by the SO ns pulse (TP1).
A Phase is an arbitrary but logical subdivision of the sequence which the DXII-B performs. Each phase has both a
name and a number. For example, Phase 3 is called Status Presentation, and it contains the logic for loading the
appropriate status into the BUSI flops and for receiving the channel response: status accepted or status stacked. Use
of phase controlled logic simplifies the control and facilitates understanding of the sequences involved. Optimum
subdivision also results in logic savings when a phase can be used in several different types of sequences.

50ns CLOCK
PULSES
(OCCURING ONCE
EVERY 200ns)

PHASE 1

Note

FF CLOCK

--..+-------1- - - - -

I
I

-----+--

NOTE:
Flip~Flop Clock must occur at same time

as 50 ns Clock and all enabling conditions

must be met prior to or at the same time as
the rising edge of the 50 ns clock pulses
11-3451

Figure C-I Timing for Setting Flip-Flops
C.2 TIME-PHASE DIAGRAMS
On Sheet 1 is a Major Phase Diagram showing the transitions made by the DX logic. When examining the individual
phase flows in Section II, you may wish to refer back to these definitions:

C-1

Phase 0:
a.

Selection Bypassed
1.
2.

ISS in Progress
Polling Sequence
Status Pending

Asynchronous Operations
1.
2.

Propagate Select·Out
Fast CU Busy Sequence

Selection Sequences
1.
2.
3.

Idle or Requesting - This phase is used for

System Reset
PDP Interrupt Granted

Programmed Interactions
1.
2.

DX Reset
Request Made

Phase 1: Address Response - This phase uses the address from the BUSO flops and the Offset Register
(CUOR) to obtain from PDp·II core the Status/Pointer Word (SPW). The information thus obtained is
used to set certain control flops. Control of the DX is then transferred to Phase 2.

Phase 2: Status Preparation - It is the job of this phase to get ready for a status presentation or, if a
CU request has been granted, to transfer to the appropriate phase (3,5, or 6) from which to proceed with
the request. If a command has been accepted, then the Device Status Table (DST) is accessed. If the
command was rejected for some reason (such as bad parity) then the DST is bypassed. During an ISS,
Phase 3 is used next. If any IBM reset condition is issued during Phase 2, then Phase 4 is used next.

Phase 3: Status Presentation - The logic controlled by time state one, this phase governs the transfer of
information into BUSI flops (and thence onto the Bus In Lines). The logic of time state two makes the
appropriate responses depending upon whether status was accepted or stacked.

Phase 4: Mark - This phase stores the Device Information resulting from the I/O Interface transaction
into a Tumble Table (TT) of data in the PDP·II core. The information consists ofthe DXDS (two bytes
of device status indicators) and the CUCR (command byte) plus the CUAR (address byte).

Phase 5: Input - This phase governs the transfer of information from the Channel into the DX1I. It
contains two separate logic paths which run independently. The left hand path synchronizes the NPR
word transfers to the PDP· 11 with the transfer of data bytes from the I/O Interface. The right hand path
controls the signals required by the CH/CU Interaction.

Phase 6: Output - This phase is similar to input except that data is trnasferred out from the DXII to
the Channel.

Phase 7: Done - This phase synchronizes the termination of the signal sequences and makes the
appropriate response either for a selector CU or for a multiplexer control unit.

C·2

Phase Independent Operations:

These operations synchronize

The various signals that could occur either independently of the DX clock and/or during any
phase and

Flip-flop changes that must be synchronized with the DX clock.

C.3 NOT AnON
Condition - Action - At the lower right of sheet one of Print DXII-B-04 is a Flow Diagram Legend containing the
various symbols used in the design flows. At the upper middle is a symbol for the basic concept used in this
description of how the hardware is intended to operate; condition-right arrow (implies) - action. A condition may
be a Boolean expression containing logical AND, logical OR, the state of flip-flops, and the condition of signals. The
AND is symbolized by a dot and is given higher precedence than a logical OR operation which is symbolized by a
plus sign. Thus, when the OR of two conditions is itself to be ANDed with other conditions, then the entire OR
expression is enclosed in a set of parentheses. In the Boolean Equations as asterisk symbolizes logical AND.

An action or result may be one of five things:
L

A signal level (equals sign);

A flip-flop set to a particular state (a left arrow);

A gating operation in which one byte or a two byte register is given the contents of another byte or
register (double left arrow);

A gating operation in which a byte or register is cleared (reset to zero); or

An action may simply be itself another enabling condition symbolized by a line.

Certain signals that may change in a completely asynchronous fashion like the on-line enable switch or which may be
slightly out of phase with other signal transitions are enclosed in brackets.
C.4 ENABLING CONDITiONS
When a condition is used as an enabling condition, there are three ways in which it may be portrayed. The first two
have the same meaning.
1.

A right arrow and condition in parenthesiS and another right arrow is used when a single condition is
necessary to continue and usually when a symmetric split is made in the flow (i.e., one way or the
other);

A third use of a condition expression, and the most important one, occurs when an enabled path is
broken by a double squiggly line. This means conceptionally that if the above line was enabled then
control will eventually get to this point. However, to actually proceed, the condition to the left of the
right arrow below the squiggly line must be met. Furthermore, this is the full, necessary, and sufficient
condition for proceeding. This provides the method of consolidating signal sequences. The squiggly line
implies that there could be a wait until the condition is met. If a number appears between the squiggly
lines, it indicates approximately how many cycles will be made before the condition is satisfied. A zero
between the lines means that the condition is normally met immediately.

C-3

C.5 PAGE CONNECTORS
When a logic line terminates at a circle with a letter inside, this is a page connector and helps to locate the next
portion of the sequence. It is for information and performs no actual function. The matching circle connector will
be found at the top of a logic path. Again there is no operational meaning attached. Occasionally, two page connectors will be found connected to a single logic line. This is a reminder that either or both paths may now have
become enabled. Beneath each reference to a page connector is a short descriptive commend in parentheses of the
reason for the reference. Similar comments at the top of the page describe categories of the logic paths that follow.
C.6 PHASE TRANSITIONS
A downward pointing triangle indicates that a phase transition will be made. All phase transitions are made by
changing the appropriate bits in the phase control flip-flops when time pulse two appears and the conditions
required during time state two have been met. When a phase transition occurs, only the conditions in the new phase
will be enabled and the conditions in the old phase will be disabled completely.
C.7 SIGNAL NAMES
When a logic path has been enabled, it is often convenient to have a named signal which represents the condition of thi
this logic path. Such signal names, if any, are written vertically along the logic path line. These signals thus shown
include phase and time state conditions.
C.8 SYNCHRONIZATION OPERATIONS
Cettain synchronization operations are phase independent and these are shown on sheet one. For example, when
both IBM signals HLD OUT and SEL OUT equal one, then the flop SELO will be set to a one. All phase independent
actions are done by either TPI or TP2. This sheet also shows various Special Signals that are available. These signals
contain no phase or time state information. This is also an index of the Major Phases Interactions with the sheet
number on which that phase can be found.
C.9 PROGRAM INTERVENTION
Program operations that trigger special responses are emphasized by a pointing hand symbol.
C.IO GATING SIGNALS
Each gate has a footnote number to correlate it with the logic signal name used internally to do the job. These
number-name pairs appear at the right or bottom and are the same as used in the control flows and in the data paths.

C-4

INDEX
Address Assignments, B-1
Address-In, definition, 5-10
Address-Out, definition, 5-10
Address Response, (Phase 1),5-13,5-28
BRs, purpose, 5-12
Cabinet Dimensions 2-4
Cables (list), 2-5
Cabling for test, 2-16
Channel Address, 5-5
Channel Command Word, CCW, 5-4
Channel-Forced Burst Mode, 5-5, 5-11
Channel loading, 5-5
Channel, MPX, 5-3
Channel, SEL, 5-3
Channel Simulator, Operation of, 5-14
Channel Status Word, CSW, 5-7
Checkout, 2-13
Circuit Descriptions, Conventions, 5-40
Clock Frequency, 1-5
Clock, Phase & Time State Generator
Circuit description, 5-47
Command, 5-4
Command Chaining, 5-4, 5-18, 5-27
Command Execution Sequences, 5-4
Command Interleaving, 5-4
Command-Out, definition, 5-10
Communication, CH to DX, 4-2
DX to CH, 4-2
DX to PDP-II, 4-2
Configurations, 2-5
Central Control, operation of, 5-13
Condition Codes, 5-6
Control Lines In Register (CONI)
circuit description, 5-44
Control Lines Out Register (CONO)
circuit description, 5-44
Controls, definition of, 3-8
Controls & Indicators, photo of, 3-2
Control Unit Address Register (CUAR)
circuit description, 5-45
Control Unit Command Register (CUCR)
circuit description, 5-45

Control Unit-Forced Burst Mode, 5-5
Control Unit-Initiated Sequence, 5-19
Control Unit Status Register (CUSR)
circuit description, 5-42
Control Unit Status Register (DXCS)
circuit description, 5-41
Conversion Chart, Hex/Octal/EBCDIC, A-12
Conversion Method, Hex/Octal, A-13
Corrective Maintenance, philosophy of, 6-2
CU Priority, 5-9
Customer Acceptance, Procedure, 2-13
Data Bus Multiplexer, circuit description, 5-47
Data Transfer, 5-29
Data Transfer Modes, 5-26
Data Transfer, read, 5-16
Data Transfer, write, 5-18
Design Flows, explanation, 5-30
Device Address, 5-5
Diagnostics, Required 2-2
Diagnostic Testing, philosophy of, 6-2
Dimensions, access, 1-4
Dimensions, cabinet, 1-4
Done (phase 7), 5-38
DXll-B Diagnostics, 2-3
DXll-B Flow Diagram Explanation, C-l
DXBA, format, 4-11
DXBC, format, 4-11
DX Block Diagram, discussion, 5-2
DX Bus Address Register (DXBA),
circuit description, 5-41
DX Byte Counter (DXBC), circuit
description, 5-42
DXCA, format, 4-7
DXCB, format, 4-14
DX Control Bits Register (DXCB),
circuit description, 5-43
DXCS, format, 4-7
DX Device Status Register (DXDS),
circuit description, 5-40
DXDS, format, 4-4
DXES 1, format, 4-17
DXES2, format, 4-18
DX Features, 1-2

Index-l

INDEX (Cont)
DX formats, 4-3
DX, function of, 1-1,4-2,5-1
DXMI, format, 4-13
DXMO, format, 4-12
DXMOB, format, 4-18
DXOS, format, 4-10
DX Registers, 4-3
DX Register Organization, 5-27
DX "working" condition, 5-26
Ending Sequence, 5-18
Environmental conditions, 1-4
EPO Panel, Operation and
circuit description, 5-52
Equipment Required, 2-2
Fast CU Busy sequence, 5-24
Floating Vector Priority Ranking, B-2
Flow Diagram, conventions, 5-29
Format, 360/-11, comparison, 4-1
General Controls, circuit description, 5-48
Glossary, conventions, A-I
Hex Address, jumper setting, 2-10
Hold-Out, definition, 5-9
IBM addressing, 5-8
IBM Bus-In Lines (BUSl),
circuit description, 5-45
IBM Cable (lines), function, 4-2
IBM Commands
1/0,5-7
Read, 5-8
Read Backward, 5-8
Sense, 5-8
Write, 5-8
IBM Control, Operation of, 5-11
IBM Direction, conventions, 5-16
IBM Instruction
Halt I/O, 5-7
Start I/O, 5-7
IBM Interface, circuit description, 5-50
IBM Interface, operation of, 5-3

IBM I/O Interrupts, 5-7
IBM Mode
Burst, 5-11
Byte, 5-11
Multithread, 5-12
Shared,5-11
Single-Thread,5-ll
Unshared,5-11
IBM Reset Sequence, 5-20
IBM Reset, Stored, Sequence, 5-38
IBM State
Available, 5-11
Busy, 5-11
Not Operational, 5-11
IBM Sequences, 5-15
IBM Sequences, Summary, 5-24
Idle or Requesting (Phase 0), 5-31
Immediate Command, 5-4
Indicators, Definition of, 3-1
Information Requirements, 2-5
Input (Phase 5), 5-36
Inspection, 2-9
Installation, 2-9
Installation Functions, 2-1
Installation, Procedure, 2-9
Interface, CH to DX, 5-9
Interface Disconnect, 5-20
Interface Disconnect, Sequence, 5-39
Interleaved, 5-5
Interrupts, PDP-II, 5-18
Interrupt Vector Jumper Installation, 2-12
I/O Address Formats, 2-10
I/O Cable Requirements, 2-23
I/O Stop, 5-12
Maintenance, 6-1
Maintenance Out Buffered Register (DXMOB),
circuit description, 5-47
Major Phase Diagram, explanation, 5-26
Mark (Phase 4), 5-35
Master/Slave Relationship, 4-3
Mechanical Checks, 6-1
Mechanical Description, 1-2
Mnemonics, significance, 5-27, A-I

Index-2

INDEX (Cont)
Modes of Operation, 1-4
Modifier Bits, 5-7
Multiplexer Channel, differences from
Selector Channel, 5-22
Non-Existent Device, 5-27
Non-Existent Memory, 5-27
NPRs, use of, 5-12
NPR and INT Control, circuit description, 5-46
NPR Data Register (DXND), circuit
description, 5-43
NPR Timeout Mono, Calibration, 2-16
Operation, 3-1
Operational-In, definition, 5-10
Operational-Out, definition, 5-9
Option Designations, 2-3
Output (Phase 6), 5-37
Parity & Address Compare, circuit
description, 5-49
PDP Control, operation of, 5-12
Performance Specs, 1-4
Phase 0, 5-31
Phase 1,5-32
Phase 2, 5-33
Phase 3, 5-34
Phase 4, 5-35
Phase 5, 5-36
Phase 6, 5-37
Phase 7, 5-38
Phase Independent Operations, 5-14, 5-30
Polling, 5-8, 5-20
Power Consumption, 1-4
Power Requirements, 2-3
Preventive Maintenance, philosophy, 6-1
Programming, 4-1
Programming Boundaries, 4-19
Programming, Data Transfer, 4-20
Programming, Hardware/Software Interlock, 4-18
Programming, Interrupt Request, 4-19
Programming, Online/Offline Control, 4-20
Programming, Status Presentation, 4-20

Request-In, definition, 5-10
Select Bypass & Power Fail, circuit
description, 5-50
Select-In, definition, 5-10
Select-Out, definition, 5-10
Selective Reset, 5-21
Selective Channel-Initiated Sequence, 5-15
Sequences, DXll-B, 5-27
Sequences, IBM, 5-15
Sequences of Operation, 5-14
Service-In, definition, 5-10
Service-Out, definition, 5-10
Shared Control Unit, 5-5
Signals and Gates, circuit
description, 5-48
Signal Sequences, 5-6, 5-15
Space Requirements, 2-3
Specifications, 1-3
Stack-Status, definition, 5-19
Start I/O, SIO, 5-4
Status, 5-27
Status-In, definition, 5-10
Status Preparation (Phase 2), 5-28, 5-33
Status Presentation (Phase 3), 5-28, 5-34
Status Types, 5-12
Sub channels , 5-5
Suppress-Out, definition, 5-10
System Cabling, 2-14
System Description, 1-1
System Reset, 5-21
Test Requirements, 2-1
Test Requirement Required, 6-2
Test Schedule, 2-6
Test Procedure,
With IBM, 2-18
Without IBM, 2-13
Time States, 5-13
Transfer Rate, 1-5
Tumble Table, 5-12
Tumble Table Index (TTNDX), circuit
description, 5-45

Index-3

INDEX (Cont)
Turning Power On for First Time, 2-12
Unibus Interface, circuit description, 5-46
Unibus Interface, operation of, 5-12
Unpacking, 2-6
Vibration Tests, 6-3

Index-4

DXll·B System 360/370
Channel to PDP·ll Unibus
Interface Maintenance Manual

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