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XX-A68AB-13

April 1975

230 pages

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Document:	EK-DQ11-MM-002 DQ11 NPR Synchronous Line Interface Manual
Order Number:	XX-A68AB-13
Revision:	000
Pages:	230
Original Filename:	http://bitsavers.org/pdf/dec/unibus/EK-DQ11-MM-002_DQ11_NPR_Synchronous_Line_Interface_Manual_Apr75.pdf

OCR Text

DQ11 NPR synchronous
line interface manual

EK-DQII-MM-002

DQ11 NPR synchronous
line interface manual

digital equipment corporation • maynard. massachusetts

Ist Edition, April 1974
2nd Edition, April 1975

Copyright © 1974, 1975 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

FLIP CHIP
DIGITAL
UNIBUS

PDP
FOCAL
COMPUTER LAB

ApriJ 1975

ERRATA SHEET

DQl1 NPR SYNCHRONOUS LINE INTERFACE MANUAL
(EK-DQI1-MM-02A)

Refer to Paragraph 3.6.6 which contains five sample programs. All programs have
an identical error in line 25.

Line 25 now reads:
25

01032

062737
000200
002002

ADD #200, @ # WENP

Change Line 25 to read:
25

Printed in U.S.A.

01032

062737
000400
002002

ADD #400, @ # WENP

CONTENTS
Page
CHAPTER 1

INTRODUCTION

1.1
1.2
1.2.1
1.2.2
1.3
1.3.1
1.3.2
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.4.1
1.4.4.2
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5

SCOPE . . . . . . . . . . . . . . . . . . . . . .
GENERAL FEATURES AND SPECIFICATIONS
Features . . . . . . . . . . . . . . . . . .
General Specifications . . . . . . . . . . .
PHYSICAL DESCRIPTION AND CONFIGURATIONS
Physical Description
Configurations . . . . . .
FUNCTIONAL DESCRIPTION
Introduction .
Basic Unit . . . . . . . .
Expander Unit . . . . . .
Types of Data Transfers Performed by the DQ 11
Introduction . . . . .
Data Transfers . . . .
BASIC OPERATING PRINCIPLES
Introduction . . .
Transmit Operation
Receive Operation
Error Detection
Protocol Handling

CHAPTER 2

INSTALLATION

2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4

GENERAL '" . . . . . . .
EQUIPMENT CHECKLIST
DQ II-DA Configuration
DQ ll-EA Configuration
DQ l1-AB Configuration
DQI1-BB Configuration
DQ ll-KA Configuration
Accessories . . . . . . .
BASIC UNIT AND EXPANDER UNIT INSTALLATION PROCEDURE
Unit Assembly . . .
Module Installation
POWER REQUIREMENTS
DEVICE ADDRESSES . .
Introduction . . . .
Floating Device Address Assignment
Device Address Selection (M 105 Module)
VECTOR ADDRESSES . . . . . . . . .
Introduction . . . . . . . . . . . . . . .
Floating Vector Address Assignment .. .
Vector Address Selection (M 78 21 Module)
BASIC UNIT AND EXPANDER UNIT SWITCH/JUMPER SELECTIONS
Introduction . . . . . . . . . . .
Module Switch/Jumper Selections
HARDWARE VERIFICATION
Diagnostics . . .
System Exerciser . . . .

22.5
2.2.6
2.3
2.3.1
2.3.2
2.4

2.5
2.5.1
2.5.2
2.5.3
2.6
2.6.1
2.6.2
2.6.3
2.7
2.7.1
2.7.2
2.8
2.8.1
2.8.2

iii

1-1
1-1
1-1
1-2
1-2
1-2
1-3
1-3
1-3
1-3
1-8
1-10
1-10
1-10
1-11
1-11
1-11
1-11

1-11
1-12

2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1

2-2
2-2

2-2
2-2
2-2
2-2

2-2
2-3
2-4
2-4

2-4
2-4

2-5
2-5

2-5
2-8
2-8
2-8

CONTENTS (Cont)
Page

CHAPTER 3

PROGRAMMING

3.1

INTRODUCTION

3-1

DQ 11 REGISTERS AND DEVICE ADDRESS SELECTION

3.7.1.6

INTERRUPT VECTORS . . . .
PRIORITY SELECTION . . . . . . . .
REGISTER BIT ASSIGNMENTS
Receive Status Register (Rx CSR)
Transmit Status Register (Tx STAT)
REG/ERR Register
....... .
Secondary Registers . . . . . . . .
Character Count (CC) and Bus Addressing (BA) Registers
Character Detection (CHAR-DET) Register
Sync Register
......... .
Miscellaneous Register . . . . . .
Transmit Buffer (Tx BUF) Register
Sequence (SEQ) Register . . . . .
Receive/Transmit Block Check Character (BCC) Registers
Rx/Tx Polynomial Register
GENERAL PROGRAMMING PROCEDURES
Introduction . . . . . . . . . . . . .
Basic Unit (DQl1-DA/EA) . . . . .
Error Detection Option (DQ ll-AB)
Protocol Option (DQI1-BB) . . . . .
Operational Features with Programming Significance
Programming Examples
DQ 11 DIAGNOSTICS . . . .
General Information ..
DZDQA-A-D Tests
DZDQB-A-D Tests
DZDQC-A-D Tests
DZDQD-A-D Tests
DZDQE-A-D Tests
DZDQF-A-D Tests

CHAPTER 4

DETAILED DESCRIPTION

4.1
4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.2
4.2.3
4.2.3.1
4.2.3.2
4.3
4.3.1
4.3.2
4.3.3

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M7818 MODULE (HARD-WIRED CHARACTER DETECT AND NPR CONTROL)
Introduction . . . . . . . . . . . . . .
Hard-Wired Character Detection Logic
Functional Description . .
Detailed Logic Description
NPR Control Logic . . . . . . .
Functional Description . .
Detailed Logic Description
M7815 MODULE (DATA SET CONTROL)
Introduction . . . . . . .
Functional Description . .
Detailed Logic Description

3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
"'" r
""."".'+.1
A

3.5.4.2
3.5.4.3
3.5.4.4
3.5.4.5
3.5.4.6
3.5.4.7
3.5.4.8
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.7
3.7.1
3.7.1.1
3.7.1.2
3.7.1.3
3.7.1.4
~ ..,
1 C'
.J. l . l • .J

3-1
3-1
3-3
3-3

3-6
· 3-10
· 3-13

· 3-13
· 3-14
· 3-14
· 3-14
· 3-17
· 3-17
· 3-21
· 3-21
· 3-22
· 3-22
· 3-22
· 3-22
. . 3-22
· 3-23
.. 3-24
· 3-36
· 3-36
· 3-36
· 3-37
· 3-38
· 3-39

· 3-40
· 3-41

4-1
4-1
4-1
4-1
4-1
4-5
4-7
4-7
4-9
· 4-12
· 4-12
· 4-12
· 4-13

CONTENTS (Cont)
Page
4.4
4.4.1
4.4.2
4.4.2.1
4.4.2.2
4.4.3
4.4.3.1
4.4.3.2
4.4.4
4.4.4.1
4.4.4.2
4.4.5
4.4.5.1
4.4.5.2
4.4.6
4.4.6.1
4.4.6.2
4.4.7
4.4.7.1
4.4.7.2
4.4.8
4.4.8.1
4.4.8.2
4.4.9
4.4.9.1
4.4.9.2
4.5
4.5.1
4.5.2
4.5.2.1
4.5.2.2
4.5.3
4.5.3.1
4.5.3.2
4.5.4
4.5.4.1
4.5.4.2
4.5.5
4.5.5.1
4.5.5.2
4.5.6
4.5.6.1
4.5.6.2
4.5.7
4.5.7.1
4.5.7.2
4.5.8
4.5.8.1
4.5.8.2

M7812 MODULE (BUS SELECTORS
Introduction . . . . . . . . . .
Bus Selectors and Control Logic
Functional Description . .
Detailed Logic Description
Miscellaneous Register (MISC) and Internal Clock
Functional Description . . . . . .
Detailed Logic Description . . . .
Transmitter Control and Status Register
Functional Description . . . .
Detailed Logic Description ..
Receiver Control and Status Register
Functional Description . . . .
Detailed Logic Description . .
Register Pointer and Error Control and Status Register (REG/ERR CSR)
Functional Description . . . . . . . . . . . . . . . .
Detailed Logic Description . . . . . . . . . . . . . .
Sync Register (SYNC) and Transmitted Data Output Logic
Functional Description . .
Detailed Logic Description
Transmitter Shift Register
Functional Description . .
Detailed Logic Description
Receiver Shift Register and Receiver Data Register
Functional Description . . . . . . . . .
Detailed Logic Description . . . . . . . .
M7813 MODULE (CC/BA AND SHIFT CONTROL)
Introduction . . . . . . . . . . . . . . . . .
Character Count/Bus Address (CC/BA) Register
Functional Description . . . . . . . . .
Detailed Logic Description . . . . . .
Character Count/Bus Address Control Logic
Functional Description . . . . . . . .
Detailed Logic Description . . . . . .
Clock Loss, Register Select, and Done Control Logic
Functional Description . . . .
Detailed Logic Description . .
Interrupt and Vector Control Logic
Functional Description . .
Detailed Logic Description
Transmit Control Logic
Functional Description . .
Detailed Logic Description
Receive Start Up and VRC Logic
Functional Description . .
Detailed Logic Description
Receive Character Control Logic
Functional Description . .
Detailed Logic Description

. . . 4-16
· 4-16
· 4-17
· . 4-17
· . 4-18
· 4-20
· 4-20
· 4-22
· 4-24
· 4-24
· 4-24
· 4-26
· 4-26
· 4-26
· 4-28
· 4-28
· 4-28
· 4-30
· 4-30
· 4-30
· 4-32
· . 4-32
· 4-32
· 4-34
· 4-34
· 4-34
· 4-37
· 4-37
· 4-38
. . . 4-38
.4-40
.4-46
.4-46
· 4-47
· 4-52
· 4-52
· 4-54
· 4-58
· 4-58
· 4-60
· 4-62
· 4-62
· 4-66
· 4-78
· . 4-78
· . 4-78
· 4-84
· . 4-84
· 4-84

CONTENTS (Cont)
Page
4.6
4.6.1
4.6.2
4.6.2.1
4.6.2.2
4.6.3
4.6.3.1
4.6.3.2
4.6.4
4.6.4.1
4.6.4.2
4.6.5
4.6.5.1
4.6.5.2
4.6.6
4.6.6.1
4.6.6.2
4.6.7
4.6.7.1
4.6.7.2
4.7
4.7.1
4.7.2
4.7.2.1
4.7.2.2
4.7.3
4.7.3.1
4.7.3.2
4.7.4
4.7.4.1
4.7.4.2
4.7.5
4.7.5.1
4.7.5.2
4.7.6
4.7.6.1
4.7.6.2
4.7.7
4.7.7.1
4.7.7.2

M7816 (AB SELECTORS AND BCC CONTROL)
Introduction . . . . . . . . . . .
Bus Selectors and Decoding Logic
Functional Description . .
Detailed Logic Description
Polynomial Register . . . . . .
Functional Description . .
Detailed Logic Description
Receive BCC Generator
Functional Description . .
Detailed Logic Description
Transmit BCC Generator . . . .
Functional Description . .
Detailed Logic Description
TX BeC Control Logic . . . . .
Functional Description . .
Detailed Logic Description
RX BCC Control Logic . . . . . .
Functional Description . .
Detailed Logic Description
M7817 MODULE (CHARACTER DETECT AND SEQUENCE CONTROL)
Introduction . . . . . . . . . . . . . .
Character Detect and Sequence Registers
Functional Description . . . . .
Detailed Logic Description . . .
Transmit and Receive Compare Logic
Functional Description .
Detailed Description ..
Character Detect Control Logic
Functional Description .
Detailed Logic Description
Sequence Decoding Logic
Functional Description . .
Detailed Logic Description
Transmitter Protocol Control Logic
Functional Description . . .
Detailed Logic Description
Receiver Protocol Control Logic
Functional Description
Detailed Description . . . .

APPENDIX A

INTEGRATED CIRCUIT DESCRIPTIONS

APPENDIX B

PDP-II MEMORY ORGANIZATION AND ADDRESSING CONVENTIONS

· 4-86
· 4-86
· 4-86
· 4-86
· 4-87
· 4-92
· 4-92
· 4-92
· 4-94
· 4-94
· 4-95
· 4-97
· 4-97
· 4-97
· 4-99
· 4-99
4-100
4-106
4-106
4-107
4-114
4-114
4-114
4-114
4-115
4-117
4-117
4-118
4-118
4-118
4-121
4-126
4-126
4-126
4-128
4-128
4-129
4-134
4-134
4-135

ILLUSTRA TIONS
Figure No.
1-1
2-1
2-2
2-3
2-4
2-5
2-6
3-1
3-2
3-3
3-4
3-5
3-6
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36

Title
DQ 11 Simplified Block Diagram .
.....
Device Address Format
Switch Locations on M7812 Module
Switch Locations on M7813 Module
Jumper Locations on M7815 Module
Jumper Locations on M7816 Module
Jumper Locations on M7817 Module
DQl1 Register Configurations and Bit Assignments
Receive Control and Status Register Format .
Transmit Control and Status Register Format
REG/ERR Register Format
Miscellaneous Register Format . . . . . . . .
Sequence Register Format . . . . . . . . . .
Block Diagram of Hard Wired Character Detection Logic
Physical Layout of Character Detection Switches
Typical Comparator Circuit
Operation of 8242 Comparator
........ .
Character Detect Control Logic . . . . . . . . .
Block Diagram of NPR Control and Associated Logic
NPR Control Logic and Timing Diagram .
Block Diagram of Data Set Control Logic
Data Set Control Logic . . . . . . . . . .
Typical One-Shot Circuit and Timing Diagram
Block Diagram of Bus Selection Logic
One Bit Slice of Bus Selection Multiplexers
Register Selection Logic . . . . . . . . .
Block Diagram of Miscellaneous Register and Internal Clock
Block Diagram of Internal Clock to DF 11 Interface
Block Diagram of Transmitter Control and Status Register
Block Diagram of Receiver Control and Status Register
Block Diagram of REG/ERR Control and Status Register
Block Diagram of SYNC Register . . . . .
Block Diagram of Transmitter Shift Register
Block Diagram of Receiver Shift Register
Block Diagram of CC/BA Register
4-Bit Section of CC/BA Register . . . .
CC/BA Address Multiplexer (E43) .. .
Block Diagram of the CC/BA Control Logic
Clocks for the CC/BA Control Logic . . . .
Timing Diagram for CC/BA Control Logic .
Pulse Generator In Overflow Detection Logic
Block Diagram of the Clock Loss, Register Select and DONE Control Logic
Register Select Decoder (E44) . . . . . .
Pulse Generator in Register Select Logic . . . . . . . . . . . . .
BR5 Priority Select Card Interconnection . . . . . . . . . . . .
Generation of Two Vector Addresses on M7821 Interrupt Module
Configuration of Vector Bits 03-08 . . . . . . .
Block Diagram of Transmit Control Logic
TX Shift Counter, TX Bit Counter and Load Logic

vii

Page
1-4
2-3
2-6
2-7
2-7
2-9
2-9
3-2
3-3
3-6
3-10
3-15
3-17
4-2
4-2
4-6
4-7
4-8
4-8
· 4-10
· 4-13
· 4-14
· 4-15
· 4-17
· 4-19
· 4-20
· 4-21
· 4-23
.. 4-25
· 4-27
· 4-29
.. 4-31
· 4-33
· 4-35
· 4-39
· 4-41
· 4-42
· 4-46
· 4-47
· 4-48
· 4-51
· 4-53
· 4-56
· 4-56
· 4-59
· 4-63
· 4-64
· 4-65
· 4-67

ILLUSTRATIONS (Cont)
Title

Page

Graphical Representation of TX Shift Counter Load and Count Sequence
Send Enable Flip-Flops and Associated Logic
Sync/Data Enable Multiplexer and Associated Logic
Character Count Logic . . . . . . . . . . . . .
Transmit VRC Logic and Sample Data Character
X-OR Truth Table and State Chart . . .
Data Sync/NPR Logic . . . . . . . . .
RX Bit Counter and Associated Logic
Receiver Start Up Logic . . . . . . .
Receiver VRC Logic . . . . . . . . . .
Sample Message Wit.'1 Received Data Character and VRC
Block Diagram of Receive Character Control Logic
Block Diagram of AB Bus Selectors and Decoding Logic
Block Diagram of Architecture of RX BCC, TX BCC, POLY and SEQ Registers
Typical Two Bit Slice of the High and Low Bytes of the Bus Selectors
Bus Selector Decoding Logic . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration of POLY Register for Polynomial X l 6 + XiS + X 2 + 1 (CRC-16)
Architecture of POLY Register
.......... .
Logic for Generating Clock Signals for POLY Register
Block Diagram of RX BCC Generator
Architecture of RX BCC Generator
Data Input Gating for RX BCC Generator
RX BCC Accumulation Using CRC-16 ..
Simplified Block Diagram of TX BCC Control Logic
TX Total Transparency Control Logic ..
Qualification Logic for TX BCC Counter
TX BCC Shift and Start/Clear Logic ..
Block Diagram of RX BCC Control Logic
RXP and RXS Save Logic . . . . . . . .
RX Transparency Control and BCC Counter Logic
BCC Tum On Logic . . . . . . . . . . . . . . .

· 4-68
· 4-69
· 4-71
· 4-72
· 4-76
· 4-77
· 4-78
· 4-79
· 4-80
· 4-83
· 4-83
· 4-84
· 4-87
· 4-88
· 4-89
· 4-91
· 4-93
· 4-93
· 4-94
· 4-95
· 4-96
· 4-97
· 4-98
· 4-99
4-101
4-103
4-105
4-106
4-107
4-110
4-112
4-114
4-115
4-116
4-117
4-119
4-120
4-122
4-125
4-126
4-127
4-128
4-129
4-132
4-134
4-136

Figure No.
4-37
4-38
4-39
4-40
4-41
4-42
4-43
4-44
4-45
4-46
4~47

4-48
4-49
4-50
4-51
4-52
4-53
4-54
4-55
4-56
4-57
4-58
4-59
4-60
4-61
4-62
4-63
4-64
4-65
4-66
4-67
4-68
4-69
4-70
4-71
4-72
4-73
4-74
4-75
4-76
4-77
4-78
4-79
4-80
4-81
4-82

Test F~X Bee Logic

.......... _ _ _ _ _

Data Flow for Character Detect and Sequence Registers
4-Bit Slice of Character Detect and Sequence Registers
Graphical Representation of RX and TX Character Comparisons
Block Diagram of Comparison Logic . . . . . . . . . . . . . .
Block Diagram of Character Detect Control Logic . . . . . . .
Clock for Incrementing the Character Counter and Testing the Strobe Logic
Clocking and Loading Logic for the Character Counter and Holding Register
One Bit of the Character Detect Flags/CD Address
Logic for Selection of Number of BCC Characters ..
Character Detect Interrupt Logic
......... .
Block Diagram of Transmitter Protocol Control Logic
TX Transparency Control Logic . . . . . . . . .
Block Diagram of Receiver Protocol Control Logic
Character Strip Logic
............. .

viii

TABLES
Table No.
2-1
2-2
3-1

4-1
4-2

Page

Title
Guide for Cutting MI05 Jumpers to Select Device Address
Guide for Cutting M7821 Jumpers to Select Vector Address
Message/Data Used in Programming Examples 4 and 5
Function of Character Detection Switches
Selection of Secondary Registers . . . . . . . . . . .

2-4
2-5

· 3-29

· 4-3
· 4-55

CHAPTER 1
INTRODUCTION

1.1 SCOPE
This manual provides the user with the information
necessary to install, operate and maintain the DQll NPR
Synchronous Line Interface. The manual is organized into
four chapters.

Transmission speeds up to 1 megabaud (Wide band
communications network interface capability)
Full- or half-duplex operation
Vertical Redundancy Check (YRC) - Parity (odd or
even) is switch-selectable

Chapter 1 - Introduction
Chapter 2 - Installation
Chapter 3 - Programming
Chapter 4 - Detailed Description

Data set control
Switch-selectable (one or two) sync characters to
character frame

This chapter contains general specifications, configurations
and an overall functional description.

Programmable sync character
1.2 GENERAL FEATURES AND SPECIFICATIONS
Programmable character size; up to 16 bits per single
character and 8 bits or less for double characters

1.2.1 Features
The DQ 11 is a high-speed, double-buffered communications
device designed to interface the PDP-ll processor to a
serial-synchronous communications channel. This interface
allows the PDP-II to be used for remote batch and remote
concentrator applications. With the DQll, the PDP-ll can
also be used as a front-end, synchronous-line controller to
handle remote and local synchronous terminals.

Double-buffered transmit and receive data registers
Double-buffered character count and bus address
register
Auto idle, strip sync, and half-duplex program
selectable

Transmit and receive data transfers between the PDP-II
Unibus and the DQ 11 are handled as Non-Processor
Requests (NPR). These are direct memory or device access
data transfers without processor supervision. As an NPR
device, the DQII provides extremely fast access to the
PDP-II Unibus and can transfer data at exceptionally high
rates once it gains control. The PDP-ll processor state is
not affected by NPR transfers, since they occur on a
cycle-steal basis.

Diagnostic-controlled, self-testing capabilities
Three switch-selectable control characters for program in terru pts
Interfaces to Bell 201 and 303 or equivalen t modems
Additional features available through expanded hardware:

Standard features:

Programmable error detection using a polynomial of
up to 24 bits to implement Longitudinal Redundancy
Checking (LRC) or Cyclic Redundancy Checking
(eRC)

Non-Processor Request (NPR) data transfers for
transmit and receive

1-1

Programmable character recognition and hardware
sequence control for protocol handling

Clocking
Internal crystal clock option specified at baud rate or
external clock (modem)

Internal crystal clock - set to acconunodate user
baud rate.

Sync Character
Program selected
Sync Detection
Activates on first non-sync character following one or
two successive sync characters, or immediately upon
detecting one or two successive sync characters.

1.2.2 General Specifications
Operational Modes
Full~ or half=duplex

Environmental
Tempera ture
0
0
+50 to +110 F
Humidity
o - 90%, non-condensing

Interfaces
EIA or current mode
Character Transfer Rate
Up to 62,500 characters per second (1 megabaud,
half-duplex with only basic unit)

Power Requirements
Basic Unit
+5 Vat 6.0 A
+15 Vat .04 A
-15 Vat .07 A
Expander Unit
Error detection: +5 Vat 1.2 A
Character recognition: +5 V at 1.6 A

Code Format (Protocol}
IBM Binary SYNCHronous
Capability
ASCII
Character Size
Programmable up to 16 bits with double-character
transfers for characters of 8 bits or less

1.3
PHYSICAL
CONFIGURATIONS

Error Dete ction
Basic Unit - Vertical redundancy check

DESCRIPTION

AND

1.3.1 Physical Description
The DQ 11 consists of a basic system unit and an optional
expander system unit. Each unit consists of a wired
backplane assembly, modules and cables and has the same
basic physical appearance and dimensions; each measures
10.5 in. X 16.5 in. X 5 in. and weighs approximately 15
pounds.

Expander Unit - Programmable polynomial for
longitudinal redundancy check or cyclic redundancy
check
Character Recognition
Basic Unit - Up to 3 switch-selectable control characters
for program interrupts

Each DQll system unit can be mounted in a
PDP-ll/05NC, PDP-ll/35, PDP-ll/40, PDP-ll/45
processor box, or in an H960-type expansion box.

Expander Unit - Up to 16 programmable single- and/or
double-characters for character recognition

The DQ 11 basic unit and the expander unit must be located
next to each other; the basic unit must be the first of the
two on the Unibus. Cables connect the two system units
together.

Bus AddreSSing
Up to 128K (max)
Character Count
Block transfer size
Up to 64K characters

Each of the two system units presents one load to the
PDP-ll Unibus.

1-2

1.3.2 Configurations
A brief description of the DQ 11 options follows:

1.4.2 Basic Unit
Exclusive of the Unibus connectors and backplane, the
basic unit contains the following modules.

Description
Full/half-duplex synchronous
line module set. EIA/CCITT
termination suitable for
direct use with Bell System
201 or equivalent modems.
Transmission speeds up to
10,000 baud. Data set control
included. Supplied with
7.6 m (25 ft) modem cable.

Prerequisite
PDP-II

Full/half-duplex synchronous
line module set. TTL to Bell
System 303 or equivalent
modems. Transmission speeds
up to 1.0 megabaud. Data set
control included. Supplied
with 7.6 m (25 ft) modem
cable.

PDP-II

Cable-connected second
system unit (Error Detection
Expander), with provisions
for error detection of up to
24-bit polynomials for LRC
and CRC checking.

DQll-DA
or
DQII-EA

DQll-BB

Cable-connected second
system unit (Character Recognition Expander), with provisions for character recognition and hardware sequence
control for protocol handling.

DQI1-AB

DQII-KA

Internal Crystal Clock specified at baud rate. Standard
frequencies are 2.0K, 2.4K,
4.8K, 9.6K and 19.2K.

DEC No.
DQl1-DA

DQll-EA

DQll-AB

Size
Single

Number
MI05

Name
Address Selector

Single

M7821

Interrupt Control

Single

M7815

Da ta Set Control

Double

M7818

Hard-Wired Character Detection
and NPR Control

Hex

M7812

Bus Selectors, Control/Status Registers and Shift Registers

Hex

M7813

Character Count Registers, Bus
Address Registers and Shift
Register Control

If the basic unit is to be EIA/CCITT compatible
(DQII-DA), it uses a DFII-A Level Converter; if the basic
unit is to be current mode compatible (DQ ll-EA), it uses a
DF II-G Level Converter.
The major functional areas of each module are discussed
below.

M1OS Address Selector
This standard module contains jumpers that are configured
to respond to the device address assigned to the DQll. It
decodes Unibus address lines A(17:00) and control lines
C(OI :00) to pick a specific DQ register and to indicate the
bus transaction (DATI, DATO, DATOB) to be performed.
The four DQ 11 addresses are:
Register
RX Control and Status
TX Control and Status
REG/ERR Control and Status
Used with bits 8-11 of the REG/ERR register to select 16 secondary registers

1.4 FUNCTIONAL DESCRIPTION

Address
76XXXO
76XXX2
76XXX4
76XXX6

1.4.1 Introduction
The DQ11 functional description is keyed to the simplified
block diagram (Figure 1-1) which shows the complete
DQl1 at the module level. The major functional areas of
each module are discussed along with some operational
concepts.

M7821 Interrupt Control
This module contains two control sections: section A
controls nonprocessor requests (NPRs) and section B
controls bus requests (BRs).

1-3

03
M4050
CRYSTAL CLOCK
. - - - - [X16 S 250K]
X 2 > 250K
CS. CO. ROY. RING

02
M7815
MODEM CONTROL

DTR, RS

E01

CLOCK EXT.

04
M 7812
DQ - . DATA BUS

01
+-___________---i DF11-A OR DF11-G

k-S.:...C_T..,:•....:S....:.C_R_ _ _ _ _
DATA IN

CSR'S

DATA BUS

CONVERTER

DATA OUT

C,D01

RX 1 TX SHI FT REG.
( 15:00

TX 15:00

SYNC REG.

RX
A-F02

DQ~BUS T
1

05
M7813
CC/BA CONTROL
CC/BA REG.
WRITE CNTL
VECTOR CONTROL
en
C1
~ a.----I-I----I RXlTX SHIFT CNTL
z
ADRS.
A-F03
~---------+~-+-~--,
:J
(17:00)
VECTOR
BIT 2

NPR RQ

M7821 03

INTR
~

INTERRUPT CNTL
a.-X_F_E_R-4_RQ_~
C04
CNTL
MASTER A

NOTES:
1. 01 -09 ARE PRINT SET
DISIGNATORS

06
M7818
MSYNC CONTROL
CHAR. DET
(SWITCH)

2. DF11-A IS EIA COMPATIBLE
USE BC01R-XX 1 M594

~ ~ 'v ~
07

BCC
ERR
DATA BUS
(15:00)

MODEM

MSYNC

STD.25
CABLE

ERRORS
CLOCK LOSS, LATENCY,]
VRC, BCC, NON- EX
[
MEMORY

M105
03
I--A_D_R_S~-+-_... ADDRESS SELECT
(17:00)
F01

BUS ..... DQ

15:00

READ CONTROL

{

3. DF11-G IS 303 COMPATIBLE
USE BC01 W - 251 M595

1'j 1'j l' l'

09 ~--------~~~-r--'

4. M7816, AND M7817 ARE EXPANDER UNIT OPTIONS

M 7816
DQ ..... DATA BUS
(EXPANDER)
RX/TX BCC CNTL
POLY REG.
RX 1 TX BCC REG.
A-F02

CM"'BUS

SEQ.
15:00

BCC
ON/OFF

FRAME TIMING
M7817
08
CLOCKS ENABLES
RX/TX PROTOCOL CNTL a..~_--------

--I

CHAR. REG.
SEQ. REG.
A-F03
11-2446

Figure 1-1 DQIl Simplified Block Diagram

1-4

the PDP-II memory. The DQ 11 takes a character from
memory (DATI) for transmission or it sends a received
character to memory (DATO) for storage. This logic also
generates the load signal for the transmitter buffer register
if a transmit operation requested the NPR.

NPRs are requested when a receive or transmit data transfer
is required, that is, when a received character is sent to the
PDP-II memory or a character to be transmitted is
obtained from the PDP-II memory.
BRs are requested when certain conditions are indicated by
flags in the DQ 11. Two vector addresses are genera ted by
the M7821; however, both are level BR5. Receive interrupts
generate a vector address of the form XXO and transmit
interrupts generate a vector address of the form XX4.

M7812 Bus Selectors, Control/Status Registers' and Shift
Registers
This module contains 8 fun~tional circuits:
Bus Selectors and Control Logic
The outputs of 8 registers in the basic DQ 11 are multiplexed to the Unibus data lines through one set of 16 bus
drivers. The registers are:

M781 S Data Set Control
This module generates two control signals to the data
set: Data Terminal Ready (DTR) and Request to Send
(RS). DTR is bit 9 of the TX Control and Status Register;
RS is bit 8 of the same register. In addition, four data set
leads are monitored: Carrier Detect (CO), Clear to Send
(CS), Ring Indicator (RING) and Data Set Ready (DSR).

Receiver Control and Status (RX CSR)
Transmitter Control and Status (TX CSR)
Register Pointer/Error (REG/ERR)
Received Data Register (RX RO)
Transmitter Buffer (TX BUF)
Miscellaneous (MISC)

Circuits are provided to allow changes in the status of CO,
CS, RING and three-user assigned signals to request a data
set interrupt if the. appropriate interrupt enable bit is set.
Data set interrupts generate a vector address of the form
XX4.

Synchronous(S~C)

Character Count/Bus Address (CC/BA)
Refer to Chapter 3 for a discussion of the bit assignments
for these registers. Decoding logic enables the multiplexers
and selects the desired registers.

CS, CO and RING are TX CSR bits 13, 12 and 11,
respectively. The data set interrupt enable Signal is TX CSR
bit 4. The data set interrupt flag is TX CSR bit 15. User
option signals UO 14 and UO 13 are RX CSR bits 14 and 13,
respectively.

Miscellaneous (MISC) Register and Internal Clock
The internal clock and MISC register are discussed together
because several bits of the register are related to operation
of the clock or its output logic during servicing.

M7818 Wired Character Detection and NPR Control Logic
This module contains two functionally separate logic
circuits: the hard-wired character detection logic and the
NPR control logic.

Five bits (4, 5, 12, 13 and 14) of the MISC register are
located on the M7813 module. The 11 bits on this module
are program-controlled.

The character detection logic provides three switchselectable control characters. Maximum character length is
16 bits. Switches are provided to enable the characters, by
bytes, to accommodate single- or double-character operation. The character to be detected is set in to the detector
bit switches and the associated enabling switch is closed.
When the received character matches the switch-selectable
character, a flag is asserted which is sent to the bus selector
logic on the M7812 module where it can be read. Another
switch is provided that allows the detected character to
request an interrupt.

The internal RC clock supplies a 14 Kbaud signal to the
external clock line. This clock could be used as the transmit
clock. Usually, the transmit clock is supplied by the modem
or by the optional crystal controlled clock (M4050) which
can be installed in the DQll. The receive clock is always
supplied by the modem with the incoming characters.
If the external receive or transmit clock is lost, the RC
clock takes over and completes shifting the character into
the RX or TX shift register before the receiver or
transmitter is shut down by the clock loss circuit on the
M7813 module. The last character is not valid.

The NPR control logic allows the DQII to become bus
master and perform a DATI or DATO bus transaction to

1-5

Transmit Control and Status Register (TX CSR)
Six bits of the TX CSR are located on this module: 0, 1, 3,
and 5-7. Bit 14 is not assigned (user option) and is
available on the backplane as a TTL connection. Bit 2 is
located on the M7813 module. Bits 4, 8, 9, and 15 are
located on the M7815 module. Bits 10-13 are signals to or
from the data set and are picked off the DFll level
converter.

Character Count/Bus Address Register
The Character Count/Bus Address Register (CC/BA)
actually consists of eight registers:
Receiver
Primary BA
Secondary BA
Primary CC
Secondary CC

Receiver Control and Status Register (RX CSR)
Eight bits of the RX CSR are located on this module: 0, 1,
3,4-7 and 15. Bits 2 and 12 are located on the M7813
module. Bits 8-11 are located on the M7818 module and
bits 13 and 14 are located on the M7815 module.

Transmitter
Primary BA
Secondary BA
Primary CC
Secondary CC

These registers are 16 bits long and are contained in a
read/write memory on the module. The BA registers are
expandable to 18 bits to allow addressing PDP-II memories
that contain more than 32K words.

Register Pointer and En-or Register (REG/ERR)
All bits except one (bit 12) are located on this module. Bit
12 is located on the M7813 module.

The BA register is loaded with the address of the first
character to be transmitted (from memory to DQll) or the
address of the first received character (sent to memory
from DQ11). The BA register is automatically incremented
during each data transfer which selects consecutive memory
addresses.

Sync Register (SYNC) and Transmitter Data Output Logic
The desired sync character is loaded into the SYNC register
(16 bits maximum). The output of the SYNC register is
compared with the output of the receiver buffer register
which contains the received sync word. If they match, a
signal is sent to the hard-wired character detection logic
(M7818) to set a flag and to initiate an interrupt request if
RX ACTIVE and CHAR INTR ENABLE bits are set.

One or both CC registers are loaded with the 2's complement of the number of characters to be transferred. The
first one is incremented toward overflow, which it reaches
when the desired number of characters have been transferred. If more characters are to be processed, the
associated CC register is activated and the sequence
continues; if the associated CC register shows a zero count,
the transfers stop. The output of the CC/BA register is sent
to the bus selector circuit on the M7812 module where it
can be read.

The serialized output of the SYNC register, transmitter data
register, transmitter BCC generator and VRC circuit are
ORed to become the serial data out to the data set.

Transmitter Shift Register
The transmitter shift register consists of an input buffer,
shift holding register and an output data selector. Data to
be transmitted is brought from the PDP-11 memory and
loaded, in parallel, into the buffer. It goes from the buffer
to the shift holding register to the output data selector
where it is serialized starting with the LSB.

Character Count/Bus Address Control Logic
This logic controls the updating of the CC/BA register
during an NPR cycle. Normally, it loads and increments the
CC register, loads and increments the BA register, then
shuts down until it is started again during the next NPR
cycle.

Receiver Shift Register
The receiver shift register consists of a shift register and two
buffer registers. In addition, the receiver data decoder
enters the serial received data into the correct bit position
of the shift register. This is required because the character
length is selectable. The output (second) buffer places the
data, in parallel, on the Unibus data lines.

When the logic detects the last character to be processed, it
looks at the associated CC register (primary or secondary)
to see if it contains a character count. If it does not, there
are no more characters to be processed. If it contains a
character count, these additional characters are processed
starting with the next NPR cycle.
A section of this logic responds to the NPR request signals
from the transmit control logic and the receive control
logic. It generates signals that are used in the NPR control
logic on the M7818 module.

M7813 Character Count RegistelS, Bus Address RegistelS
and Shift Register Control
This module contains 7 functional circuits:

1-6

Clock Loss, Register Select, and Done Control Logic
The clock loss circuit generates a flag if either the receive or
transmit flag is lost during operation. This logic also turns
on the internal RC clock which continues the shifting
operation until the sequence is ended normally at the end
of the NPR cycle. Under these conditions, the last character
is not valid.

Save Sync Logic - Allows the SYNC register to be
enabled and disabled so that idle characters can be
transmitted.
Vertical Redundancy Checking (VRC) - When
selected, the VRC logic examines the data to be
transmitted and puts a MARK (logical 1) in the MSB
position of each character if required to make the
total number of MARKs, including the VRC bit, even
or odd as selected.

The register select logic decodes signal from the M105
Address Module and generates control signals for the
CC/BA internal memories, MISC register, SYNC register,
and the REG/ERR register.

Fake End Logic - In the double-character mode (~ 8
bits per character) with an odd count, only one byte
of the last word contains a character to be transmitted. This logic allows the other byte to be ignored
and fakes the end of the current transmission. This
permits the next NPR to start sooner.

The DONE control logic generates signals that clear the RX
GO and TX GO bits and set the RX and TX primary /
secondary register DONE bits. It also provides addressing
signals for the CC/BA registers.

Data Sync/NPR Logic - At the start of transmission,
this logic generates a data enable and synchronizes
the loading of the TX shift register. It also generates
an NPR request after data is moved from the TX
buffer to the TX shift register.

Interrupt and Vector Control Logic
This logic is the controlling link between the interrupt
requesting logic in the DQ 11 and the M7821 Interrupt
Module that actually requests the interrupt.
As part of its controlling function, it sends a signal to the
M7821 that determines which vector address is asserted: vector A (XXO) or vector B (XX4).

Receiver Start Up and VRC Logic
In the receive mode, the start-up logic searches for sync
characters and, when the correct pattern is detected, it
asserts RX ACTIVE which indicates that the receiver is in
the data transfer mode. Framing (synchronization) can be
selected to occur on one or two sync characters. RX
ACTIVE can be selected for assertion when framing occurs
or on the first non-sync character after framing.

Transmitter Control Logic
This logic is divided into several functional areas which are
described as follows:
Transmit Bit Counter - The counter is loaded with
the 2's complement of the number of bits per
character selected by the program. Its outputs are
select signals that control the parallel-to-serial conversion of data in the TX shift register.

The VRC logic, when enabled, checks the received character for correct parity. Odd or even parity can be selected.
If incorrect parity is detected, the RX VRC error flag is
asserted.

Send Enable Circuit - Controls the priority of information to be transmitted. The priority, in descending
order, is: DLE, BCC, SYNC, Data, and PAD.
SYNC/Data Enable Circuit - Provides
signals for the SYNC and TX data registers.

Receiver Control Logic
This logic counts a character as being received or not. It
responds to single- and double-character operation. Further
discrimination is made between odd and even character
counts. When this logic determines that the received
character is what was expected (single or double, odd or
even count) an NPR request is generated, the character is
sent to the receiver buffer, and the receive character control
logic is prepared for the next count.

enabling

Character Count Logic - Provides byte control of the
TX data register to accommodate single- and doublecharacter operation.

1-7

The recelvmg station should request that the message be
retransmitted.

1.4.3 Expander Unit
Exclusive of the backplane, Unibus connectors and interconnecting cables, the expander unit can contain two
options. Each one is contained on a hex module as shown
below:
Module
No.
M7816

M7817

Option
Designation
DQll-AB

DQll-BB

Transmit Block Check Generator
The architecture of the TX Bee generator is very similar to
the RX Bee generator. The generator examines the data
being transmitted and accumulates a BCC character. Thls
character is appended to the transmitted data.

Name

AB Selectors and Bee
Control

Transmit BCC Control
This logic is divided into three functional areas:

Character Detection and
Sequence Control

TX Transparency Control - This circuit allows the
transmitter to enter and exit the transparent mode
under control of REG/ERR bits 14 (ENTER T) and
13 (EXIT T). This is a function of the M7816 module
only and is called total transparency to differentiate
it from transparent text which is what the transparent
mode is called when it is controlled by the M7817
module.

The major functional areas of these modules are discussed
below.

M7816 AB Selectors and BCC Control Logic
This module contains 6 functional circuits:

TX BCC Counter and BCC Request - Jumpers on
this module qualify the TX Bee counter to allow
appending of 1, 2, or 3 Bee characters. If the M7817
module is installed, it provides control signals to
qualify the counter.

Bus Selectors and Decoding Logic
The outputs of three registers on this module and one on
the M7817 module are multiplexed to the Unibus data lines
through one set of 16 bus drivers. The registers are:
Sequence Register (M7817)
Polynomial Register (M7816)
Receive Bee Register (M7816)
Transmit Bee Register (M7816)

TX BCC Shift and Clear - This logic generates the
pulses that shift the TX Bee generator. It also
provides a signal to clear the generator.

The decoding logic generates signals to enable the bus
selectors and to select the desired register.

Receive BCC Control
This logic is divided into four functional areas:

Polynomial Register
This register is a 24-bit read/write register that stores the
polynomial used in generating the Bee character during
transmission or checking the Bee character during
reception.

RX P and RX S Save - This logic looks ahead to see
if the receiver is going to enter the total transparency
mode. If it is, the logic allows total transparency to
be turned on one transfer time sooner.
RX Transparency Control and BCC Counter - This
logic allows the receiver to enter and exit total
transparency under control of REG/ERR bits 14
(ENTER T) and 13 (EXIT T). When the receiver
enters total transparency, this logic sends a signal to
the RX Bee turn-on circuit that starts the RX Bee
generator. When the receiver exits total transparency,
this logic enables the RX Bee counter and allows
reception of the selected number of Bee characters
before turning off the RX Bee generator.

Receive Block Check Generator
If a message is processed with error detection, the transmitting and receiving stations must use the same error
detecting code. The RX Bee generator examines the data
and computes a Bee character. It examines the received
Bee character and goes to all Os if the received Bee
character agrees with the computed one. This means that
the message has been received without error.
If the Bee characters do not agree, one or more errors are
present in the message. The RX Bee generator asserts a flag
that denotes that an incorrect message has been received.

RX BCC Tum-On - This logic generates pulses that
shift the RX Bee generator.

1-8

Test RX BCC - This logic responds to a signal from
the RX Bee generator after the data and Bee
characters have been received. If an erroneous
message has been received, the logic asserts a Bee
error flag.

Setting bit 12 or 13 of the sequence register allows the
received character that caused the match to set the
character flag bit (RX eSR bit 15). The address of the
detected character is also stored in the character detect
store register and can be read by the program.

M7817 Character Detection and Sequence Control
This module contains six functional circuits:

Sequence Decoding Logic
This logic examines the outputs of the sequence register to
generate control signals that are used to implement hardware operations. The basic enabling signals for this logic are
the RX and TX strobe signals.

Character Detect and Sequence Registers
The character detect and seqeunce registers are 16-wordby-16-bit random access semiconductor (TTL) memories
that provide non-destructive readout.

Transmitter Protocol Control Logic

This logic is divided into five functional areas:
With character recognition enabled, characters to be
detected are written into the character detect memory by
the program. The desired functions to be performed by the
hardware are selected by setting the appropriate bits in the
corresponding word of the sequence register.

DLE Logic - Stores the representation of a DLE
character that is placed in the character detect
memory. It allows fast access to a DLE when adding a
DLE in the transmit mode or stripping the DLE in
the receive mode.

The output of the receiver buffer register and the output of
the transmitter shift hold register are compared with each
word of the character detect memory in succession.

BCC Exclude Logic - Allows exclusion of a received
character or character to be transmitted from the
Bee accumulation when not in the transparent text
mode. Sequence register bit 11 (RX/TX Bee
EXCLUDE) controls this function.

When a received character (in RX buffer register) or a
character to be transmitted (in TX shift hold register)
matches any character in the character detect memory, a
hardware control sequence is initiated in accordance with
the bits set in the sequence register for the associated word.

PAD Logic - Allows insertion of a PAD character
following the last character to be transmitted. A
jumper allows selection of one or two PAD characters.

Transmit and Receive Compare Logic
Each received character, and character to be transmitted, is
compared with each word in the character detect memory.
When character detection is enabled, only characters of 8
bits or less can be processed. In the receive mode, two
comparisons are made; high byte and word. In the transmit
mode, four comparisons are made; high byte, low byte,
word and saved word.

TX Transparency Control Logic - Allows entry into
transparent text on the next character to be transmitted or on the one following.
TX BCC Control Logic - Excludes the first TX Bee
start-up control character from the Bee accumulation. The next TX Bee start-up control character
within this message is included in the Bee
accumulation.

Character Detect Control Logic
In response to each received character, and each character
to be transmitted, this logic causes the character detect
register to step through all 16 words, starting at word 0 and
ending at word 15. At each step, the character detect
memory word is compared with the character being
processed and a match Signal is generated if they agree. This
match signal, along with other qualifying signals, generates
an RX or TX strobe signal that is used in other logic to
initiate a hardware control function determined by the
status of the bits in the sequence register for the corresponding word.

Receiver Protocol Control Logic
This logic is divided into four functional areas as described
below.
RX BCC Control Logic - Excludes the first RX Bee
start-up control character from the Bee accumulation. The next RX Bee start-up control character
within this message is included in the Bee
accumulation.

1-9

Character Strip Logic - Prevents the detected character from being transferred to the PDP-II memory
but allows it to be included in the RX BCC
accumulation. It also allows stripping the DLE, SYNC
sequence in the receive transparent text mode.

block transfers are handled without character recognition
and idle con trol.

DQll-AB Option
This option allows transparent block transfers with error
detection (LRC/CRC). Character recognition is disabled
when a transparent block is started and is enabled when the
block ends. In this case, character control consists of the
three switch-selectable characters in the basic unit. Disabling and enabling character control during transparent
operation allows the use of idle control without destroying
the integrity of the transparent blocks.

RX BCC Disabling Logic - Stops the RX BCC generator to exclude a detected character from the BCC
accumulation. The categories of characters to be
excluded are listed below:
1.

All D LE characters

A SYNC character following a D LE character

SYNC characters following framing in nontransparent operation

Any detected character if sequence register bit
11 (RX BCC EXCLUDED) is set

The transparent block starts with the first used character
count field provided REG/ERR bit 14 (ENTER T) is set" It
ends in any other character count field provided REG/ERR
bit 13 (EXIT T) is set. These bits are reset by the hardware.

DQll-BB Option
This option provides programmable character detection
that activates hardware functions that are also programmable. Character detection is for single- or doublecharacters with a length of 8 bits or less. Block size,
character sets and error polynomial configuration are
unrestricted.

Clear GO/Set DONE Logic - Allows RX GO to be
cleared and RX DONE to be set at the end of a
transfer only. The circuit is independent of the
clearing of RX ACTIVE.
1.4.4 Types of Data Transfers Perfonned by the DQ 11

With this option installed, the programmer can drop back
to the AB option or the basic unit without hardware
changes. However, character recognition is always software
programmable, regardless of the level of hardware under
program control because when this option is installed the
hard-wired character detection feature is disabled.

1.4.4.1 Introduction - The DQ 11 performs several types
of data transfers, depending on the options selected. The
DQll-DA/EA basic units are expanded by adding the
DQII-AB and DQII-BB options to provide increased
versatility. With the maximum DQll configuration (basic
plus AB and BB options), the programmer can drop back to
the AB option or to the basic unit without hardware
changes.

The BB option provides the following programmable
hardware functions:

1.4.4.2 Data Transfers - The DQll handles typical
messages using the representative message control characters; however, its full capabilities are evident during block
transfers. Such transfers consist of blocks of pure binary
data. Using maximum character counts and high baud rates,
a large amount of data is handled in a short time.

Text transparency
BCC control
Protocol start-up and shut-down
Special character interrupts
DLE insertion and deletion

DLE characters are inserted under the following conditions:

The method of handling block transfers for the basic unit
and AB/BB options is discussed in the following paragraphs.

Basic Unit (DQll-DA/EA)
The basic unit handles typical data transfers with or
without character recognition and idle control. Transparent

1-10

When a binary character representing a DLE is
transmitted during transparent text, the hardware automatically inserts another DLE (called
D LE stuffing).

When going to an idle condition during transparent text, the hardware inserts the sequence
DLE-SYNC, DLE-SYNC, etc.

Insertion of DLE characters during transmission
requires a program function that allows the
hardware to exit the transparent text mode.
This is performed through any new character
coun t provided the EXIT T bit is set. When the
exit transparent text function is detected, the
hardware sends a DLE character preceding the
new character count field. The first character
from the new character count field must be the
control character that ends the block or text
(ETX, ETB, ITB, etc.).

Characters are transmitted until a TX CC overflow is
detected. Control is switched to the associated TX CC if
additional characters remain to be transmitted. If no more
characters remain to be transmitted, the associated TX CC
reads zero. The appropriate TX CC DONE bit in the TX
CSR is set and the hardware clears TX GO which shuts off
the transmitter.
If the IDLE MODE bit in the TX CSR is set, idle characters
are transmitted whenever TX GO is cleared. In the
non-transparent mode, the idle character is the contents of
the SYNC register. In the transparent text mode (requires
BB option), the idle character is the DLE character
followed by the contents of the SYNC register in a
repetitive sequence (DLE SYNC, DLE SYNC, etc.).

1.5.3 Receive Operation
As in the case of transmit operation, the Receive Bus
Address Register (RX BA) and Receive Character Count
Register (RX CC) must be loaded. The RX BA register is
loaded with the starting address in the PDP-II memory
where the first received character is to be depOSited.

1.5 BASIC OPERATING PRINCIPLES
1.5.1 Introduction
The following paragraphs cover some basic operating
principles of the DQ 11 and its options.
1.5.2 Transmit Operation
After initializing the system, the program must select the
desired character length using MISC register bits 11-8. The
Transmit Bus Address Register (TX BA) and the Transmit
Character Count Register (TX CC) must be selected using
REG/ERR register secondary pointer bits 11-8. The TX
BA is loaded with the starting address in the PDP-II
memory of the first character to be transmitted. This
register is incremented as each character is transferred,
which selects consecutive PDP-II memory addresses.

The SYNC register is loaded and, after any required
handshaking with the data set, the RX GO bit in the RX
CSR is set to start the receive operation. The receiver starts
accepting data and is prepared by circuit board jumpers to
be synchronized (framed) after receiving one or two sync
characters. After framing, the RX ACTIVE bit in the RX
CSR is set and data transfers are started.
Received characters are transferred to the PDP-II memory
until at RX CC overflow the associated RX CC register
indicates a zero count. The appropriate RX CC DONE bit
in the RX CSR is set and the hardware clears RX GO which
shuts off the receiver.

The TX CC register is loaded with the 2's complement of
the number of characters to be transmitted. It is incremented by the CC/BA counter, which at overflow indicates
that the character count has been completed.

Clearing RX ACTIVE while RX GO is set forces resynchronization of the receiver.

The SYNC register must be loaded with the sync character
to be used during the transmission. The same sync character
must be the first character transmitted and the most
convenient way to obtain it is by storing it in the PDP-ll
memory.

1.5.4 Error Detection
The DQll-AB option (M78I6 module) provides error
detection using Longitudinal Redundancy Checking (LRC)
or Cyclic Redundancy Checking (CRC). LRC and CRC
error detection processes use a polynomial to represent the
code that both the sending and receiving stations must use
to generate and check the block check character (BCC).

Any required handshaking to establish connection with the
data set should be done now. The program can now assert
the Transmit GO (TX GO) bit in the TX CSR to start
transmission. Data transfers from the PDP-II memory to
the DQ 11 are accomplished during NPR cycles (one per
NPR).

A 24-bit programmable polynomial register (POLY) stores
the code that qualifies both the receive and transmit BCC
generators.

1-11

1.S.S Protocol Handling
The DQll-BB option (M7817 module) provides effective
protocol handling by using programmable character
detection to initiate hardware sequences which are also
programmable. The features of the DQ II-BB option are
discussed in Paragraph 1.4.3.

As one DQ 11 transmits data, its TX Bee generator is
accumulating a Bee character that is appended to the data.
The receiving DQll accepts the data and accumulates a
Bee character in its RX Bee generator. When it receives
the transmitted Bee character, the register in the RX Bee
generator should go to all Os. This indicates that the Bee
characters on both ends are identical and that the message
has been received without error. An error in the message
means that the Bee characters cannot be the same. This
results in a remainder (not all Os) in the RX Bee register.
This condition asserts the RX Bee error flag in the
REG/ERR register. The proper response to this error flag is
to request that the message be retransmitted. As a result of
the error flag, the RX Bee register is cleared.

This option is well suited for handling line protocols, such
as IBM's Binary Synchronous (BISYNC) protocol.
The BB option can be used without error detection to
provide interrupts upon detecting any of the 16 programmable control characters. In this situation (no error
detection), it still provides the hardware control; however,
the error detection module (M7816) must be installed.

1-12

CHAPTER 2
INSTALLATION

2.1 GENERAL
This chapter provides information for installing and testing
a DQll.

(DFII-G) is substituted for the EIA/CCITT level converter
and cable. The DF Il-G consists of an M595 Converter
Module and a BCOIW cable.

2.2 EQUIPMENT CHECKLIST
Mter unpacking, check that all parts are present for the
DQ 11 configuration given in the subsequent paragraphs.

2.2.3 DQII-AB Configuration
Check that the following parts are supplied with the
DQII-AB configuration.

2.2.1 DQII-DA Configuration
Check that the following modules and assemblies are
supplied for the DQII-DA configuration.

7009468 - Wired Backplane Assembly
M920 - Internal Bus Connector

7009467 - Wired Backplane Assembly

M7816 - AB Selectors and BCC Control Logic Module

M920 - Internal Bus Connector

M971 - Cable Connector (6)

MI05 - Address Selector Module

BC08S - I/O Cable Assembly (3)

M7821 - Interrupt Control Module

2.2.4 DQII-BB Configuration
Check that one M7817 Programmable Character Detection
and Sequence Control Module is supplied for the DQII-BB
option.

M7815 - Data Set Control Module
M7818 - Wired Character Detection and NPR Control
Logic Module

2.2.5 DQll-KA Configuration
Check that one M4050 Crystal Clock Module is supplied for
the DQll-KA option. The crystal frequency must be 16
times the required baud rate for rates of 250 Kbaud or less.
Over 250 Kbaud, the frequency must be two times the
baud rate.

M7812 - Bus Selectors, Control/Status Registers and Shift
Registers Module
M7813 - Character Count Registers, Bus Address Registers
and Shift Register Control Module
DF ll-A - EIA/CCITI
BCOIR-XX)

Converter/Cable

(M594

2.2.6 Accessories
Check that the following accessories are supplied with each
DQ11 configuration.

and

2.2.2 DQII-EA Configuration
The DQll-EA configuration has the same parts as the
DQII-DA except that a 301/303 level converter and cable

LIB KIT l1-KQIIA-A-K Software Kit
B-DD-DQI1-0 Customer Print Set
DEC-II-HDQAA-A-D Maintenance Manual

2-1

2.3 BASIC UNIT AND
INSTALLATION PROCEDURE

EXPANDER

exceptions are shown in Paragraph 2.7.2 along with a
description of all switches and jumpers.

UNIT

2.3.1 Unit Assembly
A unit assembly drawing (D-UA-DQl1-0-0) is supplied as
part of the DQ 11 customer print set as an aid to the
installation process. To install the DQll, proceed as
follows:
I.

Install the modules in their respective slots as shown in
drawing D-MU-DQII-O-I for the Basic Unit (DQll-AA)
and drawing D-MU-DQll-0-2 for the Expander Unit
(DQII-AB).

Before installing the system unit, install the
7009563 harnesses, being very careful to install
the Faston connectors on their respective tabs
without catching against or cutting any of the
nearby backplane wiring. Proper connections
are listed on the backplane etch and their
relative positions are shown in drawing
C-IA-70094647-0-0 for the Basic Unit and
drawing C-IA-70094648-0-0 for the Expander
Unit.

2.4 POWER REQUIREMENTS
Basic Unit
+5 Vat 6.0 A
+15 Vat 0.04 A
-IS Vat 0.07 A
Expander Unit
Error Detection (M7816): +5 Vat 1.2 A
Character Recognition (M7817): +5 Vat 1.6 A

With all power off, install the DQ II single- or
double-system unit, containing the wired logic,
in a convenient spot in the expander box or
processor box.

2.5 DEVICE ADDRESSES

Make interconnections between the Basic Unit
and Expander Unit (if supplied) as shown in
drawing D-UA-DQII-0-0.

2.5.1 Introduction
Starting with the DJ1I, new communications devices are to
be assigned floating addresses. The addresses for current
production devices are to be retained.

Without modules installed, apply power and
check supply voltages at the following backplane pins. Adjust if required.

The word floating means that addresses are not assigned
absolutely for the maximum number of each communications device that can be used in a system.

+5 Von pin CIA2
-15 Von pin CIB2
+15 Von pin CIN2

2.5.2 Floating Device Address Assignment
Floating device addresses are assigned as follows:

2.3.2 Module Installation
Before installing modules, jumpers on the MI 05 and M7821
modules must be cut to provide the correct device address
and vector address assignments. Refer to Paragraph 2.5 for
selecting the device address (M 105) and to Paragraph 2.6
for selecting the vector addresses (M7821).
Refer to Paragraph 2.7 for switch/jumper selections for the
DQII basic and expander units (M7812, M7813, M7815,
M7816, M7817 and M7818). The jumper configuration for
the DF II Converter Module and M4050 Crystal Clock
Module are also included in this paragraph.
The diagnostics must be run with the switch/jumper
selections shown in Paragraph 2.7.1 due to a few configurations that are not supported by diagnostics. The

2-2

The floating address space starts at location
760010 and extends to location 764000 (octal
designations).

The devices are assigned in order by
type: DJ1I, DHll, DQll, DUll, and then the
next device introduced into production.
Multiple devices of the same type must be
assigned contiguous addresses.

The first address of a new type device must
start on a modulo lOs boundary, if it contains
one to four bus-addressable registers. The
starting address of the DH II must be on a
modulo 20 s boundary because the DH 11 has
eight registers.

A gap of lOs, starting on a modulo lOs
boundary, must be left between the last address
of one type device and the first address of the
next type device. A gap must be left for any
device on the list that is not used, if the device
following it is used. The equivalent of a gap
should be left after the last device assigned to
indicate that nothing follows.

No new type devices can be inserted ahead of a
device on the list.

Example 2: I DJII, I DUll and 2 DQlls
760010
DJ11 #0 first address
760020
DJ 11 gap
760040
DHll #0 first address
760060
DHl1 gap
760070
DQ 11 #0 first address
760100
DQll #1 first address
760110
Indicates no more DQlls

2.S.3 Device Address Selection (MIOS Module)
A typical DQl1 address (760070) is represented graphically
in Figure 2-1. In the floating address space
(760010-764000), bits 13-17 are always Is (function of
PDP-ll processor). Appendix B shows the PDP-11 memory
organization and addressing conventions. Bits 3-12 are
selected by jumpers on the MI0S module. With the jumper
in, the decoder looks for a 0 on the associated Unibus
address line; conversely, with the jumper out, the decoder
looks for a 1 on the associated Unibus address line. Bits 1
and 2 are decoded to select 1 of 4 registers. They determine
the least Significant digit (octal) of the device address
because bit 0 is not used for address decoding and is
assumed to be O.

If additional devices on the list are to be added
to a system, they must be assigned contiguously
after the original devices of the same type.
Reassignment of other type devices already in
the system may be required to make room for
the additions.

The following examples show typical floating device assignments for communication devices in a system.

Example I: No DJlls, 2 DUlls and 2 DQlls
760010
Cannot be used for DHII starting address
760020
DHll #0 first address
760040
DH11 #1 first address
760060
DHl1 gap
760070
DQ 11 #0 first address
760100
DQll #1 first address
760110
Indicates no more DQ11s

ONES

76XXXO
76XXX2
76XXX4
76XXX6

RX Control and Status Register
TX Control and Status Register
REG/ERR Control and Status Register
Used with bits 8-11 of REG/ERR
CSR to select 16 secondary registers.

*BYSELECTED
JUMPERS

ALWAYS

~
I' I: I' I

The DQII requires four addresses:

-I

I I

1 '

I,r

~
0

I :

DECODED TO
SELECT 1 OF 4
REGISTERS
NOT USED
ALWAYS 0
ADDRESS BIT

I B'NARY
OCTAL

* Jumper In -

Looks for 0 on Unibus
Jumper o u t - Looks for 1 on Unibus

11-2635

Figure 2-1 Device Address Format

2-3

Table 2-1 shows which MI05 jumpers to cut for specific
device addresses.

The devices are assigned in order by
type: DCll; KLll/DLll-A, B; DPll;
DMll-A; DNll; DMll-BB; DRll-A; DRll-C;
PA611 Reader; PA611 Punch; DTll; DXII;
DLII-C, D, E; D11I; DHII; DQII; DUll.

De,ice
Address

760010
760020
760030
760040
760050
760060
760070
760100

If any type device is not used in a system,
address assignments move up to fill the
vacancies.

If additional devices are to be added to the
system, they must be aSSigned contiguously
after the original devices of the same type.
Reassignment of other type devices already in
the system may be required.

Table 2-1
Guide for Cutting MIOS Jumpers to Select Device Address

Jumper
8
7

3
X

X
X
X
X
X

I I

X
X

760200

X
X

2.6.3 Vector Address Selection (M7821 Module)
Each device interrupt vector requires four address locations
(two words) which implies only even-numbered addresses.
A further constraint is that all vector addresses must end in
o or 4. The vector address is specified as a three-digit,
binary-coded, octal number using Unibus data bits 0-8.
Because the vector must end in 0 or 4, bits 1 and 0 are not
specified (they are always 0) and bit 2 determines the least
significant octal digit of the vector address (0 or 4). The
logic on the M7821 module sends only seven bits (2-8) to
the PDP-ll processor to represent the vector address.

760400

X
X

760500
760600

760700
761000
762000

X
X

760300

763000
764000

The DQll is shipped with a BR5 priority selection card
installed in the M7813 module. The BR section of the
M7821 Interrupt Control Module generates two vector
addresses: receiver interrupts generate vector addresses of
the form XXO, and transmitter interrupts generate vector
addresses of the form XX4. For this method of operation,
the bit 2 jumper on the M7821 module must be left
installed. The two most significant octal digits of the vector
address are determined by jumpers in lines 3-8. With the
jumper in, a 1 is generated on the associated Unibus data
line; with the jumper out, a 0 is generated on the associated
Unibus data line. Also, the NPR jumper on the M7821
module should be left in to improve NPR latency time.

Note: X means remove (cut) jumper (logicall on the Unibus)

2.6 VECTOR ADDRESSES
2.6.1 Introduction
Communications devices are asSigned tloating vector
addresses. This eliminates the necessity of assigning
addresses absolutely for the maximum number of each
devic~ that can be used in the system.
2.6.2 Floating Vector Address Assignment
Floating vector addresses are assigned as follows:
1.

The floating address space starts at location 300
and proceeds upward to 777. Addresses
500-534 are reserved.

Table 2-2 shows which M7821 jumpers to cut for specific
vector addresses.

2-4

M7818 Module 5w 9-- _ a>.,.v'.
S5
SW33-SW40 - ON, all others OFF

Table 2-2
Guide for Cutting M7821 Jumpers
to Select Vector Address

Jumper
5
6
X
X
X
X

X
X
X
X
X
X

X
X

X
X
X

M7816 Module
Jumper WI - OUT
Jumper W2 - IN
Jumper W3 - OUT

Vector
Address
300'J
310
320
330
340
350
360
370
400
--500

M7817 Module
JumperWI-0UT
Jumper W2 - OUT
M40S0 Module
Jumper WI0 - OUT
Jumpers WI-W9 - Depends on crystal frequency.
Refer to M4050 listing in Paragraph 2.7.2

2.7.2 Module Switch/Jumper Selections
After all diagnostics have been run successfully, configure
the modules per the customers requirements using the
descriptions listed below.

---

600
---

Note:

700

X means remove (cut) jumper (logical 0 on
the Unibus)

M7812 Module (Figure 2-2)
The operational capabilities of this module are switchselectable and are described below. All the switches are
contained in one dual-in-line package (SI) located between
components E51 and E52.

2.7 BASIC UNIT AND EXPANDER UNIT SWITCH/
JUMPER SELECTIONS
2.7.1 Introduction
The DQll is shipped with the switches and jumpers in the
following configuration:

Switch
SWI

Description
Set to ON to run diagnostics DZDQE and
DZDQF. Following completion of these
diagnostics, SWI should be set to OFF
unless the DQl1-KA option is installed.

SW2

Set to ON only if the DQ is interfaced to a
Bell 308 modem (Tl Carrier).

SW4 - ON only if clock option (KA) is installed and baud rate is> 250K.

SW3

Set to ON if DQI1-KA is equal to or less
than 250 Kbaud (+16).

SW5 - ON only if clock option (KA) is
not installed.

SW4

Set to ON if DQl1-KA is greater than 250
Kbaud (+2).

SW6-0FF
SW7 -OFF
SW8 -OFF

SW5

Set to ON if DQll-KA clock is NOT
installed. This switch provides a 14 Kbaud
RC clock for cable test.

M7812 Module
SI
SWI-0N
SW2-0FF
SW3 - ON only if clock option (KA) is installed and baud rate is ~ 250K.

M7813 Module
SI
SWI - ON
SW2-0N
SW3-SW8 - OFF

NOTE
If the DQ ll-KA crystal clock is installed, it is
used for the cable test.

2-5

rE'i'8I

rE9l
~

SW1 - OPEN to attenuate RC clock when it is connected to external
clock line and crystal clock option is not installed.
SW2 - ON only when type 306 data set is used.
SW3 - With crystal clock option installed, crystal frequency is divided
by 16 when switch is ON.
SW4 - With crystal clock option installed, crystal frequency is divided
by 2 when switch is ON.
SW5 - Connects RC clock to external clock line when crystal clock option
is not installed.
SW6, SW7, and SW8 - Not used.

11-2637

Figure 2-2 Switch Locations on M7812 Module

M7813 Module (Figure 2-3)
The operational capabilities of this module are switchselectable and are described below. All the switches are
contained in one dual-in-line package (SI) located between
components E96 and E97.

Switch
SWI

Description
Set to ON for two sync characters to frame.
Set to OFF for one sync character to frame.

SW2

Set to ON for Receive Active on first
non-sync character after frame has occurred.
Set to OFF for Receive Active when frame
occurs.

SW4

NOTE
If no customer preference is expressed, set SWI
and SW2 to ON and all other switches to OFF.
M7818 Module (Figure 2-4)
The operational capabilities of this module are switchselectable. All the switches are contained in seven dual-inline packages (SI-S7). Refer to print D-CS-M7818-O-1,
sheets 1 and 2 for switch locations. Sheet 2 of this print
also contains basic rules for using the switches. Refer to
Paragraph 4.2 of this manual for a detailed discussion on
the use of the switches.
)

M7815 Module (DQII-BA)
The operational capabilities of this module are jumperselectable and are described below. Refer to print
D-CS-M781 5-0-1 , sheet 1 and Figure 2-4 for jumper
locations.

Set to ON for even VRC and OFF for odd
VRC.

2-6

M7813

EJE]
SW1

E][J
EJE]

SWl - Set to ON for two sync characters to frame.
Set to OFF for one sync character to frame.

SW8

SW2 - Set to ON for Receive Active on first non·sync character after
frame has occurred. Set to OFF for Receive Active when
frame occurs.
SW4 - Set to ON fo; even VRC and OFF for odd VRC.

E]E]
E]E]
A

11-2640

Figure 2·3 Switch Locations on M7813 Module

M7815

Wl - If installed, allows an interrupt to occur when U013 and DATA
SET IE are both set.
W2 - If installed, allows an interrupt to occur when U014 and DATA
SET IE are both set.
W3 - If installed, allows INITIALIZE and MASTER CLEAR to clear
RSand DTR.
W4 - If installed, RING transitions generate a DATA SET flag.

-W3-

-W1-W2-

-W411- 2636

Figure 2-4 Jumper Locations on M7815 Module

2-7

Jumper
WI

Description
If installed, allows an interrupt to occur
when UOl3 and DATA SET IE are both set.

Jumper
WI

Description
If installed, selects two pad characters (all
Is) when SEQ 10 is used.

If installed, allows an interrupt to occur
when UOl4 and DATA SET IE are both set.

If installed, the start BCC (TX) control
character is included in the BCe.

If installed, allows INITIALIZE and
MASTER CLEAR to clear RS and DTR.

If installed, RING transitions generate a
DAT A SET flag.

NOTE
Jumpers WI and W2 installed is not supported
by diagnostics.
M40S0 Module (DQll-KA)
The frequency value of the crystal installed in this module
determines the configuration of the jumpers. Note that
jumper WI0 must always be removed.

NOTE
DQll is shipped with all jumpers in, which is
the normal configuration. Removal of jumpers
W3 and W4 is not supported by diagnostics.

Crystal Frequency
5-38 kHz
38-500 kHz
500 kHz-l MHz
1-5 MHz

M7816 Module (DQII-AB)
This module uses jumpers (WI, W2) to select the number of
BCCs to be tested (receive) or appended (transmit) when
used for block transfers with the error detection feature.
(See Figure 2-5 for jumper locations.) The jumper configuration for the number of BCCs selected is as follows:

WI
IN
OUT

OUT

IN
OUT

W7,W8
WI, W2, W7, W8
WI, W2, W3, W4, W7, W8

*WIO always removed.

DFll Cable Module
Remove all jumpers except the two labeled 202 and the
two labeled 301 when using a Bell 201, Bell 208, Be11303
or equivalent modem. Remove all jumpers except the two
labeled 202 when using a Bell 301 modem or equivalent.

BCCs ~ bits/char. BCCs >8 bits/char.

OUT

Jumpers Removed*

2
2.8 HARDWARE VERIFICATION

When the third jumper (W3) is installed, the start BCC (RX)
control character is included in the BCC. Installation of
jumper W3 is not supported by diagnostics. This jumper is
used with the DQII-BB option only.

2.8.1 Diagnostics
Diagnostics DZDQ-A through -F should all be run with
iterations for a minimum of one pass without errors.
Switch/jumper configuration should be as described in
Paragraph 2.7.1.

M7817 Module (DQI1-BB)
The M78I7 module has two jumpers that can be used for
the following purposes. (See Figure 2-6 for jumper locations.)

2.8.2 System Exerciser
System exerciser DEC/XII should be run without error to
verify that the system and the DQll are ready for
operation.

2-8

M7816

Jumper
W2
W1
OUT
IN
OUT IN

OUT

Number of BCCs
..; 8 bits/char > 8 bits/char
2
3
1
2
1
-

With jumper W3 installed,
the start RX BCC control
character is included in the
BCC.

kJl
WJ-

tv;.

vj }

~~§] ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
A

11-2638

Figure 2-5 Jumper Locations on M7816 Module

M7817

-W1-

-W2-

W J -~
Function with Jumper Installed
Selects 2 TX PAD characters
Start TX BCC character included in BCC

11-2639

Figure 2-6 Jumper Locations on M7817 Module

2-9

CHAPTER 3
PROGRAMMING
3.1 INTRODUCTION
This chapter contains general DQll programming information. It is divided into two sections: one lists the register
bit functions and the other discusses programming
procedures.

Programming Note:
During power-up, the program must clear the following
registers and bits:
Bus address registers (secondary registers 0, 2, 4, and
6) and the related MEM EXT/ENTER T/EXIT T bits
(REG/ERR register bits 13 and 14).

3.2 DQII REGISTERS AND DEVICE ADDRESS
SELECTION
The DQ 11 employs address selection logic to detect one of
four addresses. The first three addresses are used to select
primary registers as shown below:
Address
76XXXO
76XXX2
76XXX4

Character count registers (secondary registers 1,3, 5,
and 7) and the related MEM EXT/ENTER T/EXIT T
bits.

Primary Register
Receive Status Register (RX CSR)
Transmit Status Register (TX CSR)
REG/ERR Register

Sequence register (secondary 14) and character detect
register (secondary 10) if the DQII-BB option is
installed.

The fourth address (76XXX6) is used in conjunction with
the secondary register pointer bits (8-11) of the REG/ERR
register. Selection of a secondary register requires two
DATO transactions. The first one, using 76XXX4, addresses
the REG/ERR register and sets bits 8-11 to pOint to the
desired secondary register. The second one, using 76XXX6,
enables decoding logic in the hardware that uses bits 8-11
to address the selected secondary register. A list of the 16
secondary registers is shown below:
Octal No.

o
1
2
3

4
5
6
7
10
11
12
13
14
15
16
17

3.3 INTERRUPT VECTORS
The DQll generates two vector addresses: receive interrupts generate vector addresses of the form XXO, and
transmitter interrupts generate vector addresses of the form
XX4. The functions that cause the interrupts are:

Receive Status Register (XXO)
Receive Done Primary (Rx Done P)
Receive Done Secondary (Rx Done S)
Character Hag

Register
Receive Bus Address (Rx BA) - Primary
Receive Character Count (Rx CC) - Primary
Transmit Bus Address (Tx BA) - Primary
Transmit Character Count (Tx CC) - Primary
Receive Bus Address (Rx BA) - Secondary
Receive Character Count (Rx CC) - Secondary
Transmit Bus Address (Tx BA) - Secondary
Transmit Character Count (Tx CC) - Secondary
Character Detect (CHAR DET)
SYNC
Miscellaneous (MISC)
Transmit Buffer (Tx BUF)
Sequence (SEQ)
Receive Block Check Character (Rx BCC)
Transmit Block Check Character (Tx BCC)
Receive/Transmit Polynomial

Transmit Status Register (XX4)
Transmit Done Primary (Tx Done P)
Transmit Done Secondary (Tx Done S)
Error Hag
I)a ta Set Hag

3.4 PRIORITY SELECTION
The priority selection for transmit and receive interrupts is
selectable on the M7813 module via plug-in priority
selection card. The DQll is shipped with a priority 5
selection card installed that establishes BR5 as the bus
request level for interrupts.

3-1

00
RXCSR
76XXXO
VECTOR A (XXO)

R/W

READ BUT WRITE ONLY IF
RXANDTX NOT ACTIVE

R/W

TX CSR
76XXX2
VECTOR B (XX4)
R/W

R/W

RI W

R/W

REG/ERR
76XXX4
VECTOR A AND B

MEMORY EXT

ENTER-if EXITT
R

R/W

MISC
R/W

R/W

W(ls)
R(O)

R/W

NOT
USED

R/W

Bce
CLEARI
START

CLR
RX
TRANS

SET
RX/TX
TRANS

R/W

SEQ
ALL BITS R/W
NOT
USED
Secondary registers addressed by using 76XXX6 and REG/ERR
bits 11-8 to specify octal designation.

DOUBLE OR SINGLE CHARACTERS (8 BITS OR LESS) RIGHT JUSTIFIED
(UNUSED B ITS MUST BE ZEROS)

DOUBLE CHARACTERS (8 BITS OR LESS) RIGHT JUSTIFIED ----~

SINGLE CHARACTERS (9-16 BITS) RIGHT JUSTIFIED ---------------~

CHAR DET(R/W)
SYNC (R/W), TX BUF (R)
TX/RX DATA (NPR)

Octal

o
1

2
3
4

UP TO i6 BiTS RiGHT JUSTIFIED - - - - - - - - - - - - - - - - - - - - - - 1
EXPANDABLE TO 24 BITS

BA REGISTERS EXPANDABLE TO 18 BITS
POLY REGISTER EXPANDABLE TO 24 BITS

16 BITS RIGHT JUSTIFIED - - - - - - - - - - - - - - - - - - - - - t

TX/RX BCC
ALL 8 ITS READ ONLY

TX/RX CC (R/W)
TX/RX BA (R/W)
POLY (R/W)

5
6
7
10
11
12
13
14
15

16
17

Secondary Registers
Receive Bus Address (RxBA) - Primary
Receive Character Count (RxCC) - Primary
Transmit Bus Address (TxBA) - Primary
Transmit Character Count (TxCC) - Primary
Receive Bus Address (RxBA) - Secondary
Receive Character Count (RxCC) - Secondary
Transmit Bus Address (TxBA) - Secondary
Transmit Character Count (TxCC) - Secondary
Character Detect (CHAR DET)
Sync
Miscellaneous (MISC)
Transmit Buffer (TxBUF)
Sequence (SEQ)
Receive Block Check Character (RxBCC)
Transmit Block Check Character (TxBCC)
Receive/Transmit Polynomial
11 - 2665

Figure 3-1 DQ 11 Register Configurations and
Bit Assignments

3-2

3.5.1 Receive Status Register (Rx CSR)
The receive status register is a word/byte addressable
register. The register format is shown in Figure 3-2.

3.5 REGISTER BIT ASSIGNMENTS
The register bit assignments for the DQll are shown in
Figure 3-1. A detailed discussion of each register is given in
the following paragraphs.

CHARACTER
DETECTED

RECEIVE
ACTIVE
(Rx ACTIVE)

RECEIVE
DONE
SECONDARY
FLAG
(Rx DONE S)

CHARACTER
INTERRUPT
ENABLE
(CHAR IE)

RECEIVE
PRIMARYI
SECONDARY
(R x PIS)

RECEIVE
RECEIVE
HALF-DUPLEX
DONE
DONE
(HD)
PRIMARY
INTERRUPT
FLAG
ENABLE
(Rx DONE P) (RxOONE IE)

CHARACTER
FLAG

RECEIVE GO
(RxGO)

STRIP
SYNC

11-2643

Figure 3-2 Receive Control and Status Register Format
Bit
00

Function
RECEIVE GO
(RXGO)

Description
When set, this bit enables
receiver data transfers (NPRs)
and framing. When cleared,
receiver data transfers are inhibited from being set by the
hardware. This bit is read/
write and is cleared by:

Bit
01

Function
STRIP SYNC

1. Initialize

Description
When this bit is set, all sync
characters following Receive
Active are stripped from the
incoming serial data. In transparent text and in total transparency, the Strip Sync function is inhibited. In transparent text, all DLE-SYNC
combinations are stripped if
this bit is set.

2. Master Clear

This bit is read/write and is
cleared by Initialize and
Master Clear.

3. The DQI1-BB Character
Recognition option (bit 7
of the Sequence register)
02
4. If Rx Clock Loss, Rx latency, or Rx Non-Existent
Memory are set
5. If the Character Count
(CC) goes to zero (primary
and secondary registers)
Notes:

RECEIVE
PRIMARY/
SECONDARY
(Rx PIS)

Indicates which of the Bus
Address (BA) and Character
Coun t (CC) registers is being
used. A zero indicates that
the primary registers are
active.

If a transfer is prematurely
ended (i.e., the CC did not
increment to zero, as in negating GO, or by a transferending flag, or by bit 7 of the
Sequence register), the Rx
P /S bit does not flip to the
next CC or BA register.

Refer to bit 02 for
CC in forma tion.
Clearing RX GO also
clears Receive Active.

3-3

Bit
02 (Cant)

Function

Description
This bit is read only and is
cleared (set to primary register) by Initialize and Master
Oear.

Bit

Function

06-07 (Cant)

Description
These bits -are read/write and
are cleared by Initialize and
Master Clear.
Note:

HALFDUPLEX

The setting of tJ-lis bit indicates that the DQll is in the
half-duplex mode. When set,
the receiver is inhibited when
Transmit Active is asserted.

This bit is read/write and is
cleared by Initialize and
Master Clear.
04

CHARACTER
INTERRUPT
ENABLE
(CHAR IE)

08-11

When set, this bit allows the
Character Detect Flag to generate a program interrupt on
Vector A (XXO).
For a double-character (~8
bits/char) transfer, the character that/ caused the interrupt may not be transferred
to memory until one character time later.

RECEIVER
DONE
INTERRUPT

If set, this bit allows interrupts to occur on Vector A
(XXO), if Rx DONE P or S is

ENABLE

set~

Basic Unit Only
When applied to the DQll
Basic System Unit only, bits
8, 9, and 10 represent
switch-selected control characters 0, 1, and 2, respectively.

(Rx DONE IE)
This bit is read/write and is
cleared by Initialize and
Master Clear.

06-07

RECEIVE
DONE
PRIMARY/
SECONDARY
FLAGS(Rx
DONE PIS)

These four bits are used to
latch the character address
which caused a character flag.
They represent the switchselected character flags in the
DQll Basic Unit. If the Character Recognition option
(DQII-BB) is installed, these
four bits reflect the binary
address of the character
detected at Character Flag
time.

Character recognition is inhibited if in total transparency mode. Refer to bit
14 of the REG/ERR register
for this function.

This bit is read/write and is
cleared by Initialize and
Master Oear.
05

CHARACTER
DETECTED
(CHARDET)

If Rx DONE is set
by the Sequence
register, RX PIS (bit
2) does not change
state.

These flags are set when their
respective character counts (P
or S) overflow. These bits are
also set by the DQ 11- BB
Character Recognition option
(bit 7 of the Sequence register). Rx Done S is bit 6.

Rules for setting the switches
are as follows:
Switches relating to the High
Byte (HB) should be used for
detecting characters less than
or equal to eight data bits.

3-4

Bit
08-11
(Cont)

Function
CHARACTER
DETECTED
(CHARDET)

Description
High- and Low-Byte (LB)
switches are used for detecting characters with more than
eight bits or double characters. All unused bits must
be set to zero. If less than
three control characters are
required, then one or two
charac ter switch groups
should be set for the same
character. For example, if
only one control character is
needed, all three switch
groups must be set for the
same character.

Bit
08-11
(Cont)

Function
CHARACTER
DETECTED
(CHAR DEl)

Description
Access is via address 76XXX6
with the REG/ERR register
pointer bits (11-8) set to
10 8. The procedure for reading and writing these 16 bits
is:
1. Set the REG/ERR register
pointer (bits 11-08) to
CHARACTER DETECT
(octal 10).
2. Write the character address
into Receive Status register
CHARACTER
DETECTED bits 11-8.

Bit 11 is connected to the
Sync Detection Logic; with
switch selection, detection of
a sync character causes a
Character Detected flag.

3. Read and/or write the
character with select 6.
Select 6 (76XXX6) is used
to access the 16 secondary
registers. Refer to description of bits 08-11 of the
REG/ERR register for
addi ti onal informa tion.

Character Recognition and
Hardware Sequence Control
(Expander Unit)
With the DQ 11-BB Character
Recognition option installed,
bits 8, 9, 10, and 11 contain
the binary address (0-178)
of the character detected
(latched) at CHARACTER
DETECT Flag time. Refer to
description of bits 12 and 13
of the Sequence register. The
binary address of the character detected is guaranteed
for one character time; i.e.,

4. Repeat steps 2 and 3 until
all required characters are
accessed.
These bits are read/write, if
Receive Active or Transmit
Active is not enabled and the
DQII-BB Character Recognition option is installed. Bits
08-11 are cleared by Initialize and Master Clear.

Bi ts / character

- - - - - =(Seconds)
Baud rate

With this option installed, the
character address bits 11-8
may be written, if both
Transmit Active and Receive
Active are not asserted. Any
of the 16 characters to be
detected can be addressed.

3-5

RECEIVE
ACTIVE
(Rx ACTIVE)

The setting of this bit indicates that the receiver is now
synchronized and in the data
transfer mode. The hardware
becomes synchronized (Sl
and S2 are true) with the
incoming data when it recognizes one or two consecutive
sync characters (switch option).

Bit
12
(Cont)

Function
RECEIVE
ACTIVE
(Rx ACTIVE)

Description
At the user's option, the
ACTIVE bit can be set at the
following times:

Bit
Function
13-14 (Cont)

Description
These bits are read/write and
are cleared by Initialize and
Master Gear.

a. When receiver
synchronized.

The Character Flag bit is set
when a character is detected.
(Refer to description of bits
8-11.)

becomes

CHARACTER
FLAG

b. On detection of the first
non-sync character following synchronization.

This bit causes an interrupt if
the
Character Interrupt
Enable bit (bit 4) is set. The
CHARACTER FLAG is
read/write and is cleared by
Initialize and Master Clear.

The conditions for Active to
come
true are switchselectable. Clearing Active
forces resynchronization if
Rx GO is asserted.

If the DQl1 is performing double-character transfers (~8
bits/char), data is shifted in from the MSB of the high byte
(HB) toward the LSB of the low byte (LB). The CHARACTER FLAG bit is set when a special character is
recognized in the HB position; hence, the special character
may not be in memory yet. The special character can either
be in the HB pOSition of the previous data transfer (BA
register) or in the LB position of the next data transfer.

The normal DQ11 configuration is synchronized on
two consecutive sync characters, followed by Rx
ACTIVE becoming true on
the first non-sync character.
This bit is read/write and is
cleared by Initialize, Master
Gear, bit 6 of the Sequence
register, when Rx ACTIVE is
cleared and when Rx GO is
cleared.
13-14

USER
OPTION

DATA SET
FLAG

USER
OPTION

If the DQII-BB is not installed and it is required that the
special character be 'in memory at interrupt time, the
M7818 module can be set for LB position character
recognition; however, diagnostic DZDQ-D will fail the
character detection test in this case. At interrupt time, the
special character can either be in the LB position of the
previous data transfer or in the HB position of the one
before that.

These bits are available as
part of the DQ 11 Data Set
control feature. They may be
used for generating additional
flags
or for providing
additional modem control.

CLEAR
TO
SEND
(CS)

RING
INDICATOR

CARRIER
OR
SIGNAL
QUALITY
DETECTOR
(CO)

The Transmit Status register is a word/byte addressable
register. The register format is shown in Figure 3-3.

DATA
TERMINAL
READY
(DTR)

DATA
SET
READY

3.5.2 Transmit Status Register (Tx STAT)

TRANSMIT
DONE
PRIMARY
FLAG
(Til DONE P)

REQUEST
TO
SEND
(RS)

TRANSMIT
DONE
INTERRUPT
ENABLE
(Til DONE IE)

TRANSMIT
DONE
SECONDARY
FLAG
(Til DONE S)

ERROR
INTERRUPT
ENABLE
(ERR IE)

IDLE MODE

TRANSMIT
TRANSMIT
DATA SET
PRIMARYI
INTERRUPT
GO
SECONDARY
(Til GO)
ENABLE
(DATA SET IE) ACTIVE
(Til PIS ACTIVE)
11-2644

Figure 3-3 Transmit Control and Status Register Format

3-6

Bit
00

Function
TRANSMIT
GO(Tx GO)

Bit
02

Description
When set, this bit enables
transmit
data transfers
(NPR).
Note:

Refer to bit 02 for
character count
information.

Function
TRANSMIT
PRIMARY/
SECONDARY
ACTIVE(Tx
PIS ACTIVE)

This bit is read/write and is
cleared by:

Description
Indicates which of the Character Count and Bus Address
registers (CC/BA) will be or
are being used. A zero indicates that the Primary (P)
register is active; a one indicates that the Secondary (S)
register is active.
The P register is always the
first character count used
following Initialize or Master
Gear.

a. Initialize
b. Master Gear

When Character Count register overflow occurs, the
CC/BA register switches (primary to secondary or secondary to primary).

c. The DQII-BB Character
Recognition option (bit 07
of the Sequence register).
d. By setting the Tx NonExistent Memory, Tx latency, or Tx Clock Loss
flags.

If the transfers are prematurely ended, as when
clearing Tx GO, the CC/BA
register does not switch and is
used again when Ix GO is
reasserted.

e. By both character counts
(CC) going to zero (primary and secondary registers.
01

IDLE MODE

This bit is read only and is
cleared (set to P register) by
Initialize and Master Gear.

If set, this bit allows the
sending of IDLE* characters
whenever Tx GO is zero.

*Non-transparent mode: The
IDLE character is the contents of the Sync register.
*Transparent
text
mode: The IDLE character is
Data link Escape (DLE)
followed by the contents of
the Sync register, followed by
DLE-SYNC, etc. (requires
DQII-BB option).

ERROR
INTERRUPT
ENABLE
(ERR IE)

When set, this bit enables
interrupts on Vector B (XX4)
from the error flag in the
REG/ERR register. The error
flag is asserted when any of
the error indicators are ON.
They are as follows:
VRC error
BCC error
Non-Existent Memory
latency
Gock Loss

3-7

Bit
03 (Cont)

Function

Description
This bit is read/write and is
cleared by Initialize and
Master Gear.

DATA-SET

When set, this bit enables
interrupts (Vector B) fwm
the Data Set flag. The Data
Set flag is set from either the
leading or trailing edge transition of Carrier Detect (CO),
Gear to Send (CS), or RING.

no. T'Y'nn n T TTVJ"
li~ lCl\..l\..Ur 1

ENABLE
(DATA SET
IE)

Ready (DTR) and Request to Send (RS). The user should
be aware of required modem and/or hardware delays before
Request to Send (RS) can be negated. For instance, Bell
20lA modems require a two-bit time delay following the
last bit of transmission before negating RS. Due to
double-buffered hardware, Tx DONE indicates that data
tiatiSfciS have been completed but not all data has been
transmitted. All data has been transmitted only when Tx
Active is negated (one-to-four character times after Tx
DONE).
The function of each of the following Data Set control bits
is given in the format of NAME (EIA/CCITT /PIN EIA/PIN
303).

This bit is read/write and is
cleared by Initialize and
Master Clear.

TRANSMIT
DONE

INTERRUPT
ENABLE (Tx
DONE IE)

Bit
08

If set, this bit allows interrupts to occur on Vector B if
the Tx Done bit (06 or 07) is
set.

Function
REQUEST TO
SEND (RS)
(CA/IOS/4/D)

This bit is read/write and is
cleared by Initialize and
Master Clear.
06-07

TRANSMIT
DONE
PRIMARY/
SECONDARY
(Tx DONE
PIS)

These bits are set when their
respective character counts (P
or S) overflow. Bit 06 is TX
DONE secondary. These bits
are also set by the DQl1-BB
Character Recognition option
(bit 7 of the Sequence register).
Note:

Description
Request to Send (RS) is a
transmit lead to the data
communications equipment
(Data Set). This control function is used to condition the
local data communications
equipment for data transmission and, on a half-duplex
channel, to control the direction of data transmission.
A program state change
directed to RS will be presented to the Data Set on the
next positive transition of the
transmit clock.
When the RS bit is set, an ON
signal is transmitted. When
cleared, an OFF signal is
transmitted.

If Tx DONE is set
by the Sequence
register, Tx PIS (bit
2) does not change
state.

This bit is read/write and is
cleared by Initialize and
Master Gear (if the jumper is
in).

These bits are read/write and
are cleared by Initialize and
Master Gear.
09

NOTE
Bits 08-15 are used for Data Set Control
functions (Request to Send, Clear to Send, etc).
The DQII hardware transmits and/or receive
data independent of these control functions.
The Data Set Control module has a jumper which, when
removed, inhibits Initialize from clearing Data Terminal

3-8

DATA
TERMINAL
READY (DTR)
(CD/I08.2/
20/M*)
*The shield is
the conductor

The Data Terminal Ready
(DTR) bit controls switching
of the data communications
equipment to the communications channel.
Auto dial and manual call
origination: maintains the
established call.

Bit
09
(Cant)

Function
Description
DATA
Auto Answer: allows handTERMINAL
shaking in response to a
READY (DTR) RING signal.
(CD/l 08.2/
20/M*)
This bit is read/write and is
cleared by Master Clear and
Initialize (if the jumper is in).

DATA SET
READY (DSR)
(CC/l 07/6 /F)

Bit
13

Function
CLEAR TO
SEND (CS)

The Data Set Ready (also
referred to as Modem Ready
or Interlock) bit reflects the
current state of the Data Set
Ready lead. The Data Set
Ready lead indicates that the
modem is powered up and is
not in the test, talk, or dial
mode.

This bit is read only; it is not
directly affected by Initialize
or Master Clear (indirectly via
RS).

This bit is read only; it is not
affected by Initialize or
Master Clear.

RING
(CE/125 f22/F*)
*The shield is
the conductor

This bit reflects the state of
the Data Set Ring lead. The
trailing and leading edge of
the ring lead causes the Data
Set flag to be set and an
interrupt request follows if
the Data Set Interrupt Enable
bit is set.

USER
OPTION
(UOI4)

This bit is read only; it is not
affected by Initialize or
Master Clear.
12

CARRIER
OR SIGNAL
QUALITY
DETECTOR
(CO)
(CR/I09/8/M)

Description
This bit reflects the current
state of the modem Clear to
Send (CS) lead. An ON state
indicates that the modem is
ready to transmit data. This
signal is raised in response to
having sent the request-tosend Signal. CS is delayed
from RS as a function of the
type of modem and the type
of lines used (four wire or
two wire). The leading and
the trailing edge of CS causes
the Data Set flag to be set,
and an interrupt request
follows if the Data Set Interrupt Enable bit is set.

This bit is provided at the
backpanel for user connection of a non-standard
status bit and/or program
interrupt via the Data Set
flag. The backpanel connection is TTL only and
represents two standard TTL
loads.
This bit is read/write and is
cleared by Initialize and
Master Clear.

This bit reflects the current
state of the modem Carrier
Control (CO) lead. An OFF
indicates that no signal is
being received or that the
received signal is unsuitable
for demodulation. The leading and the trailing edge of
CO causes the Data Set flag
to be set, and an interrupt
request follows if the Data
Set IE bit is set.

DATA SET
FLAG (DS)

If this bit is set and Data Set
IE is asserted, a Bus Request
(BR) occurs on Vector B. The
Data Set flag is asserted by
the leading or trailing transitions of Ring, CO, and CS.

This bit is read/write and is
cleared by Initialize and
Master Clear.

This bit is read only; it is not
affected by Initialize or
Master Clear.

3-9

3.5.3 REG/ERR Register
The REG/ERR register is a word/byte addressable register.
The register format is shown in Figure 34.

ERROR
INTERRUPT
(ERR INTR)

MEMORY
EXTENSION
OR
EXIT T

MEMORY
EXTENSION
OR
ENTER T

WR!TE
ENABLE
FOR
BITS
13814

NOTE
The error bits described below generate an
interrupt request on Vector B provided that the
Error Interrupt (ERR IE) bit is asserted.

SECONDARY
REGISTER
POINTER
(POINT TO
16 SECONDARY
REG I STERS)

Rx BLOCK
CHECK
CHARACTER
(BCC)
ERROR
Rll VERTICAL
REDUNDANCY
CHECK
(VRC)
ERROR

Tx NONEXISTENT
MEMORY
ERROR

Rx NONEXISTENT
MEMORY
ERROR

Tx
LATENCY
ERROR

Rll
LATENCY
ERROR

Tx
CLOCK
LOSS
ERROR

Rll
CLOCK
LOSS
ERROR
11-264!1

Figure 34 REG/ERR Register Format

Bit
00-01

Function
Tx,Rx
CLOCK
LOSS

Bit

Description
Bits 00, 01 (Tx and Rx
respectively) are set if the
clock stops with Active Set
(Rx or Tx).

02-03
(Cont)

Function
Tx,Rx
LATENCY
ERROR

The Oock Loss flag is set if
GO is asserted without the
clock or if the clock drops for
more than 0.5 second while
GO is true.

Setting these bits clears the
respective GO flip-flop.
These bits are read/write and
are cleared by Initialize and
Master Oear.

Setting these bits clears the
respective GO flip-flop.

04-05

These bits are read/write and
are cleared by Initialize and
Maste r Oear.

02-03

Tx,Rx
LATENCY
ERROR

Description
This error condition implies
that the Unibus is overloaded,
is malfunctioning, or the
baud rate exceeds specifications.

Bits 02, 03 (Tx and Rx
respectively) are set if an
NPR request is not serviced in
less than one transfer time
(two characters if less than 9
bits/char). Setting this bit
clears the respective GO flipflop.

Tx,Rx
NONEXISTENT
MEMORY
ERROR

Bits 04, 05 (Tx and Rx
respectively) are set if the
DQll, during an NPR cycle,
addresses a non-existent core
memory location. This condition implies a program or
hardware error and should be
dealt with accordingly.
Setting these bits clears the
respective GO flip-flop.
These bits are read/write and
are cleared by Initialize and
Master Oear.

3-10

Bit
06*

Function
RxBLOCK
CHECK
CHARACTER
(BCC) ERROR
*Expander unit
only

Description
This bit is asserted if the BCC
generated by the received
message and the received BCC
do not compare.
When this bit is set, the Rx
BCC is cleared (hardware
function) and ready for the
next message. Additionally,
this does not affect Rx GO.

Bits

(11-8)

Via 76XXX6)

Receive Bus Address
(Rx BA) - Primary
Receive Character
Count (Rx CC) Primary

These bits are read/write and
are cleared by Initialize and
Master Clear.
Rx VERTICAL
REDUNDANCY
CHECK (VRC)
ERROR

Function
SECONDARY
POINTER
REGISTER

Description
These bits point to 16
secondary registers for read/
write operations. The selected
register is accessed using
select 6 (76XXX6) with word
transfers only.

Octal
No.

It is recommended that a
message retransmit be initia ted when this form of error
is detected.

Bit
08-11

This bit is set if the last
received character had incorrect character parity. VRC is
jump~r-selectable for even or
odd parity; parity on/off is
progrf.m-selectable by bit 15
of the Miscellaneous register.
If V RC is used with the
DQl1-BB Character Recognition option, the control
characters transferred to the
Transmit Buffer must have
correct VRC.
Also, the SYNC register must
have correct VRC. If the
receiver is operating in the
double-character mode ( ~ 8
bits/char) with an odd character count, the PAD character that immediately
follows the message must
have correct parity. The PAD
character is all 1s so even
parity is required for an 8-bit
PAD character. Otherwise, a
VRC error flag occurs on
reception of the last datal
PAD character combination.

Miscellaneous (MISe)

Transmit Buffer
(Tx BUF)

14 * *

Sequence (SEQ)

Transmit Bus Address
(Tx BA) - Primary

15*

Receive Block Check
Character (Rx BCC)

Transmit Character
Count (Tx CC) Primary

16*

Transmit Block Check
Character (Tx BCC)

17*
4

Receive Bus Address
(Rx BA) - Secondary

Receive/Transmit (Rx/
Tx) Polynomial (Rx,
Tx POLY)

Receive Character
Count (Rx CC) Secondary

Transmit Bus Address
(Tx BA) - Secondary

Transmit Character
Count (Tx CC) Secondary

10**

Character Detect (CD)

SYNC

*Registers at these addresses are
always zero unless the Expander
Unit DQ11-AB LRC or CRC
Error Detection option (M7816)
is installed.
**Registers at these addresses are
always zero unless the Expander
Unit DQl1-BB Character Recognition option (M7817) is installed.

These bits are read/write and
are cleared by Initialize and
Master Clear.

This bit is read/write and is
cleared by Initialize and
Master Clear.

3-11

WRITE
ENABLE FOR
BITS 14 & 13
(14, 13 WRITE
EN)

When set, this bit allows the
data written into bits 14 and
13 to be transferred to the
Bus Address or the Character
Count registers the next time
select 6 is used. This bit is
self-clearing when the writet o-scra tch-pad memory
occurs.

Bit
12 (Cont)

Function

Description
This bit is read/write and is
cleared by Initialize and
Master aear.

13-14

MEMORY
EXTENSION
OR ENTER
T/EXIT T

The Bus Address (BA) and
Character Count (Ce) registers are I8-bit registers. The
17th and 18th bits are used
for memory extension for the
BA and control functions for
the CC. Bits 14 and 13 with
bit 12 provide a means of
reading and/or writing the BA
- -+ -. - -and eel bits lbits 17, 16, are
the bits 14 and 13, respectively). In addition, the register pointer bits (bits 11-8)
determine what CC or BA is
to be accessed.

Bit
13-14
(Cont)

JIEJI0R Y
EXTENSION: Bits 14 and 13 relate
to address lines AI7 and A16,
respectively. These two bits
(14, 13) are the read/write
ports for transmit and receive
extended addresses.

Function
MEMORY
EXTENSION
OR ENTER
T/EXITT

Description
EXIT T (13): If set, this exit
transparency bit allows exit
from the transparent mode,
enables character recognition
and appends the TX BCC or
iesis ihe RX BCC. TI1is function is used as a companion
to ENTER T, a jumper is
provided to start the BCC
generator which tests/
appends one, two, or three
BCC characters (selected by
jumpers). When used with
protocoi hardware control,
EXIT T starts transmission of
a DLE (Data Link Escape)
and enables the character
recognition circuits to recognize ETX (End of Text), ITB
(Intermediate Text Block),
and other control characters,
SEQ 15 would be used here
for character recognition.
The ENTER T and EXIT T
bits execute their respective
functions when the ces are
tested for non-zero by the
hardware. This occurs when
the current CC register goes
to zero and the next CC is
tested for non-zero, or at the
first transfer following the
assertion of GO.

ENTER T (14): Enter transparency forces transparency
(block transfers with BCC)
and inhibits all character
recognition. This function is
used if a message to be transmitted (or received) is completely transparent to all data
and control characters.
Additionally, this function
starts the BCC generation and
requires the DQII-AB
LRC/CRC Error Detection
option.

When read, bits 14 and 13
always represent the contents
of the respective addressed
CC or BA registers. Select 6
must be used to transfer a
write operation from bits 14
and 13 into the CC or BA
registers.
Bits 14 and 13 always represent the contents of the hardware memories until address
76XXX6 is used. Once bits
12, 13, and 14 are set, the
program must not use readmodify-write instructions

tThe two high order bits of the CC registers are used for Enter
T/Exit T control functions rather than increasing the character
block size. Character blocks are limited to 64K (16 bits). However,
the reader must understand that the address for both the CC and the
Enter T /Exit T bits are the same.

3-12

Bit
13-14
(Cont)

Function
MEMORY
EXTENSION
OR ENTER
T/EXITT

Description
(BIS, BIT, etc.) on this register (address 76XXX4) until
address 76XXX6 is used.
During start up, bits 14 and
13 must be cleared by the
program. In operation, these
bits are self clearing. Refer to
programming procedures
(Paragra ph 3.6) in this
chapter.

ERROR
INTERRUPT
(ERR INTR)

This error flag is set if any of
the error bits are asserted.
The error bits are for VRC,
BCC, Rx/Tx Non-Existent
Memory, Rx/Tx-latency, and
Rx/Tx Oock Loss.

A description of each type of secondary register, is given in
the subsequent paragraphs.
3.5.4.1 Character Count (CC) and Bus Addressing (BA)
Registers - Four Character Count (CC) and four Bus
Address (BA) registers are incorporated in the basic unit.
Eight are required because there are pairs of registers for
each function. Such double-buffering serves to reduce peak
load response to CC overflow. The CC registers are loaded
with the 2's complement of the number of characters.
The CC and BA are 16-bit registers. The BA register is
extended to 18 bits by using bit 12 (14, 13 WRITE EN)
and bits 13 and 14 (MEMORY EXTENSION) of the
REG/ERR register. Bits 12, 13 and 14 of the REG/ERR
register are used with the CC registers to perform special
functions. See Paragraph 3.5.3 for an explanation of these
bits.
The BA register for transmit and receive must be started on
even boundaries (multiple of 16-bit words rather than a half
word or 8-bit byte). Ending of the BA (and CC) may be on
odd or even boundaries. In the double-character mode (~ 8
bits/char) with an odd character count, the PAD character
that immediately follows the message must have correct
parity; otherwise, a VRC error is generated (if VRC is
enabled).

This bit is read only and
presents a zero when all error
bits are zero and when Master
Clear or Initialize has been
issued.
3.5.4 Secondary Registers
The secondary registers listed below are addressed by
76XXX6 provided that the previous I/O instruction placed
the appropriate 4-bit binary pointer in bits 8-11 of the
REG/ERR register.
Register

These bits are read/write and are not cleared by Initialize or
Master Clear. They must be cleared by a program initialization procedure.

Function

Octal
Address

o
1

2
3
4

5
6

7
10
11
12

13
14

15
16
17

When an Initialize or Master Clear is issued, the Primary /
Secondary (P/S) flip-flops select the primary CC and BA
registers. When CC overflow occurs, the Secondary register
(Tx or Rx - whichever overflowed) is selected. Data
transfers cease, and GO is cleared when the flip-flop to the
next CC register occurs and is found to be zero. The next
GO starts with the last selected CC (the one that terminated
the last GO).

Receive Bus Address (Rx BA) - Primary
Receive Character Count (Rx CC) - Primary
Transmit Bus Address (Tx BA) - Primary
Transmit Character Count (Tx CC) - Primary
Receive Bus Address (Rx BA) - Secondary
Receive Character Count (Rx CC) - Secondary
Transmi t Bus Address (Tx BA) - Secondary
Transmit Character Count (Tx CC) - Secondary
Character Detect
SYNC
Miscellaneous (MISC)
Transmit Buffer (Tx BUF)
Sequence
Receive Block Check Character (Rx BCC)
Transmit Block Check Character (Tx BCC)
Receive/Transmit (Rx/Tx) Polynomial

NOTE
The hardware does not require or expect the
Primary /Secondary (P/S) registers for transmit
and receive to be in phase except following
Master Clear and Initialize.

3-13

3.5.4.3 Sync Register - The Sync register is programmable for up to sixteen bits. Unused bits must be set to
zero. If characters less than or equal to eight bits are used,
then the odd and even bytes should contain the same sync
character. The least significant bit (LSB) is right-justified, as
are the data bits. If VRC is used, the sync character must
have correct ¥Re.

3.5.4.2 Character Detection (CHAR-DET) Register - The
programmable character recognition option (DQ 11-BB) is
read/write. for up to sixteen single or double characters (16
bits/character maximum). The hardware reaction upon
detection of the characters is also programmable using the
Sequence register. The available character fields are as
follows:

These bits are read/write and are cleared by Master Clear
and Initialize.

Bits 15-8 are used for single-character recognition (Le., STX) or for recognizing the second
character in double-character recognition. Characters should be right-justified and unused bits
must be zero.

3.5.4.4 Miscellaneous Register - This register is used
mostly for maintenance and bits-per-character selection.
The register format is shown in Figure 3-5.

Bits 7-0 are used for recogruzmg the first
character of double-character recognition (Le.,
DLE). Characters should be right-justified and
unused bits must be zero.

NOTE
When the DQII-BB Character Recognition
Option is installed, the three standard jumperselectable characters are inhibited. VRC is not
recommended when the DQ 11-BB option is
being used.

Bit
00*

Function
SHIFT
CLOCK

Description
The Shift Clock is used solely
for maintenance. The transmit shift register shifts when
this bit is set to ONE (transition) and the receiver
strobes data when this bit is
cleared (transition). This bit
is read/write and is cleared by
Initialize and Master Gear.

01*

STEP MODE

This bit selects the clocking
source for the test loop (see
description of bit 3).

A typical character table for interaction with an IBM 2703
might appear as follows:

0
2
3
4
5
6
7
8
9
10
II
12
13
14
15

4
~

....

If this bit is a one, the Shift
Gock (bit 00) is the clock
source. This bit is read/write
and is cleared by Initialize
and Master Gear .

Bits 7-10
DLE

Bits 15-8
STX
ITB
ETB
ETX
EOT
ENQ
*DLE
SOH
NAK
~

DLE
DLE
*DLE

If this bit is zero, the auto
clock source is selected. The
source for the auto clock is
approximately 14 KHz (RC
clock), if loop mode is also
selected. If loop mode is not
selected, the source clock will
be the serial clock receiver
leads.

ACKO
ACKI
RVI
WACK

Not used (SEQ=O)
Not used (SEQ=O)
Not used (SEQ=O)

NOT USED

03*

TEST LOOP

*Required for bit 9 of the Sequence register to identify DLE
characters. Use of DLE with ETX makes up a pseudo double
character.

These bits are read/write and are NOT cleared by Initialize
or Master Gear.

*Used for maintenance function.

3-14

If set, this bit causes the
transmitter shift register to
loop back to the receiver.
This bit is read/write and is
cleared by Initialize and
Master Clear.

....
VERTICAL
REDUNDANCY
CI-ECK (VRC)

BITS PER
CHARACTER
SELECTION

SYNC 1

Tx ACTIVE

SEND DATA
(SO)

MASTER
CLEAR

TEST
LOOP

STEP MODE

POLYNOMIAL
RECEIVE
NOT USED
16- 23 NON- PROCESSOR
REQUEST
(Rx NPR)

SYNC 2

SHIFT CLOCK

11-2642

Figure 3-5 Miscellaneous Register Format

Bit

04*

Function
RECEIVE
NONPROCESSOR
REQUEST
(Rx NPR)

Description
The Rx NPR bit is used for
maintenance and is intended
for use when Receiver Active
is zero.

Bit

Function
POLYNOMIAL

16-23

A one written into this bit
forces an Rx NPR if Receiver
Active is cleared. The data
transferred to core is the contents of the receiving shift
register (not the buffer) and
the Bus Address (BA) and the
Character Count (CC) are updated. If Receiver Active is
set, the data is taken from the
receiver buffer.

If this bit is set to ONE, the
register pointer 178 selects
polynomial bits 16-23 while
pointers 15 8 and 16 8 select
Block Check Characters
(BCC) 16-23. The polynomial and the BCC for bits
16-23 are accessed via bit
positions 0-7 respectively.
This bit is read/write and is
cleared by Master Dear and
Initialize.

This bit is write Is only and
always reads as a O.

MASTER
CLEAR

Description
If set to zero, register pointer
178 selects polynomial bits
0-15. In addition, pointers
15 8 and 16 8 select Block
Check Characters (BCC)
0--15.

The Master Dear function
resets all active functions and
flags in the DQ 11. The CC,
BA, MEM EXT, ENTER T,
EXIT T, CHAR DET, and the
SEQ are not cleared by
Master Clear. They are
cleared by moving Os to the
respective bits.

07*

This bit is write Is only and
always reads as a zero.

*Used for maintenance function.

3-15

SEND DATA
(SD)

This bit always monitors the
transmitted data (contents of
transmit shift register LSB).
If the Transmit Active bit is a
zero and loop mode is
selected, this bit is read/write
and can be used as an input
to the receiver shift register as
a maintenance function. A 0
equals MARK and a I equals
SPACE.

Bit
07*
(Cont)

08-11

Function

Description

Bit

SEND DATA
(SD)

This bit is read/conditional
write and is cleared by Initialize and Master Clear.

BITS PER
CHARACTER
SELECTION

Bits per character selection is
made via bits 11, 10,9, and 8
as follows:
11

o
o

000
0
0 1

o
o
o

o
o
o
1
1
1
1
1
1

0
0

9 8

1 0
1 1
0 0
0 1
1 0

1
1 1
0
0 0
001
0
0
0
1 1
100
1
0 1
1
1

1 0
1

Function
SYNC 2

Description
SYNC 2 is set when the
receiver becomes synchronized (framed).
This bit is read only and is
cieared by Initialize, Master
Clear, and by clearing Active.

Bits per
Char.

SYNC 1

15
14
13
12
11
10
9
8
7
6

A switch is provided on the
M7813 module to allow
framing after reception of
one or two sync characters.
SYNC 1 is set when the
receiver has received one sync
character. With the switch
OFF, SYNC 1 directly sets
SYNC 2 and allows framing
to be completed.
If the switch is ON, SYNC 1
conditions SYNC 2 to be set
if the next received character
is another SYNC. If the next
received character is not a
SYNC, then SYNC 1 is
cleared, and a bit-by-bit
search continues for another
sync character.

5
4
3
2
Not used

If VRC is enabled, the
selected number of bits per
character includes a parity bit
in the most significant
posi tion.
For example,
selection of 8 bits/char gives
7 data bits and a parity bit in
the most significant position.
The transmitter correctly
appends the parity bit. The
receiver accepts the character
(data plus parity bit) checks
for correct parity, and transfers the complete character to
memory.

This bit is read only and is
cleared by Initialize, Master
Clear and by clearing Active.
14

Tx ACTIVE

When set, this bit indicates
ihat the transmitter is in the
process of transmitting a
character; it will remain set
until all characters and/or bits
have been transmitted. The
bi t remains set in the idle
mode.
This bit is read only and is
cleared by Initialize, Master
Clear, and lack of data to
transmit.

These bits are read/write and
are cleared by Initialize and
Master Clear.

3-16

Bit
15

Function
VERTICAL
REDUNDANCY
CHECK (VRC)

Description
When set, the VRC bit
enables parity to be generated
(transmit) or checked
(receive) in the most significant bit position of the
selected character. VRC odd/
even is switch-selectable. The
transmit VRC is corrected, in
serial, as the data is presented
to the serial line. VRC is
corrected on all characters
(data, sync, DLE, etc.) with
the exception of BCC and
PAD. Thus, character recognition is done without corrected VRC and must. be
taken into account when
character recognition is used.

Rx BCC
EXCLUDE

3.5.4.5 Transmit Buffer (Tx BUF) Register - The Transmit Buffer is a 16-bit, read-only maintenance register which
monitors the parallel input to the Transmit Shift register.
These bits are cleared by Initialize and Master Oear.
3.5.4.6 Sequence (SEQ) Register (Figure 3-6) - The
Sequence register (requires DQIl-BB option) is a programmable 16-by-16 bit register which defines hardware functions when a control character is recognized. The control
character recognized and the programmed sequence for that
character must be at the same character detected address.
The SEQ register is used by both the receive and transmit
logic. The following bit des(;ripLions indicate which bits
function for receive, transmit, or both.

NOTE
If a character is detected and no bits are set in
the respective sequence register, no hardware
functions take place and the receive (transmit)
characters are handled in the normal way.

All bits are read/write and are not cleared by Master Oear
or Initialize. All Sequence register bits must be initialized
by the program following power up and preceding the
transmission and/or receiving of data.

Rx/Tx OLE Rx/Tx CLEAR
SJRIP/ADD.
GO/SET
DONE

T x PAD

Description
error flag is generated on
reception of the last datal
PAD character combination.
This bit is read/write and is
cleared by Master Oear and
Initialize.

With VRC enabled, the sync
register must have correct
VRC and the bits/char selection must include parity. The
received characters that are
transferred to memory include the parity bit in the
most significant position.
When operating in the
double-character mode (~8
bits/char) with an odd character count, the PAD character immediately following
the message must have correct parity; otherwise, a VRC

Function

Bit
15 (Cont)

CHA RACTER(S)
STRIP

CLEAR
Rx ACTIVE

CLEAR/START SET Rx/Tx
Rx/Tx BCC TRANSPARENT
MODE
CLEAR Rx
NOT USE D
TRANSPARENT
MODE
11-2641

Figure 3-6 Sequence Register Format

3-17

Bit
00

Function
NOT USED

Description

SET Rx/Tx
TRANSPARENT

Requires double-byte match,
(between Tx/Rx shift register
and character detection register) to function, i.e., Low
Byte and High Byte (LB and
HB). (See description of bit
14.)

MODE

Bit
02 (Cont)

Function

Description
Reference REG/ERR register,
bit 13, for clearing Tx Transparent mode (EXIT T).

CLEAR!
START
Rx/Tx BCC

Dears and starts the BeC
generator with the next character (following the detected
control character) if it is the
occurrence following Initialize, Master Clear, or GO
(OFF to ON). In all other
cases, the BCC starts and includes the current control
character unless the BCC Exclude bit (bit 11) is used.

RECEIVE: Enters receive
transparent text mode and
inhibits strip sync. Strip idle
and DLE in transparent mode
will require the use of bit 9 of
the Sequence register. During
transparency text, character
recognition is disabled except
when preceded by DLE
which is stripped by bit 9.

The first BCC start-up control
character (first STX) is excluded from the BCC. However, the next BCC start-up
character within the same
message is included (second
STX) in the BCC unless the
BCC exclude bit is used.

TRANSMIT: Enters transmit
transparent text mode which
modifies idle from sync character to alternating sync and
DLE characters and inhibits
character recognition unless
preceded by DLE. Using bit 9
also allows DLE stuffing. All
SEQ control is inhibited
except bit 9. Refer to REG/
ERR register to transmit exit
transparency (EXIT T).
02

CLEARRx
TRANSPARENT
MODE

The BCC start control character (first STX) may be included in the BCC, if desired,
via jumpers on the M7816,
M7817 modules; however,
this mode of operation is not
supported by the diagnostics.

Requires a Single-byte match
to function (HB). (See description of bit 15.) Detected
control character must be
preceded by a DLE character.
(This is a pseudo double character match.) Refer to discussion of bit 09 of this
register.

04-05

The use of SEQ 09 to strip a
DLE that is followed by a
control function is treated in
the hardware as a doublecharacter match, thus allowing exiting transparency.

Rx/Tx BCC
TEST/
APPEND

These bits select and actually
enable the testing (receive
mode) or appending (transmit
mode) of the selected number
of BCC characters immediately following the control
character (ETX, ETB, etc.)
The bit selections are:

Bits 5,4
00
10
01
11

3-18

BCC Character
None
Three
Two

One

Bit
04-05
(Cont)

Function
Rx/Tx BCC
TEST/
APPEND

CLEAR Rx
ACTIVE

Rx/TxCLEAR
GO/SET
DONE

Bit
08

Description
Each BCC character is the
same bit length as the bits per
character selection. For
example, using 8 bits/char
and a 16 bit BCC requires
testing or appending two BCC
characters. The received BCC
characters are not transferred
to core and consequently do
not affect the CC. Additionally, Rx interrupts are
suspended while the respective BCC is being processed.
This is particularly useful if
the programmer desires a
character detect interrupt on
the control character which
asserted bits 5, 4 as an indication that a block of data
has been received without
error.

Function
Rx CHARACTER(S)
STRIP

Description
This bit strips received characters from transfers to core
but not from the BCC register
(see description of bit 11 for
BCC exclude).
If bit 15 is a one, a character
less than or equal to eight bits
that compares with the character register (right-justified)
is stripped. If bit 14 is a one,
a double character or a character greater than eight bits is
stripped. When both bits are
set, bit 14 dominates hardware con tro1.

Clears Receive Active, SYNC
1, SYNC 2, which is useful
for forcing re-sync during a
message. GO is not cleared.
When framing again occurs,
transfers resume with the current CC and BA. The control
character that required Receive Active to be cleared is
transferred to core before Receive Active is cleare d.

Rx/TxDLE
STRIP/ADD

RECEIVE: Single character
match (specified by bit 15)
strips the first character as
with DLE when in the transparent text mode. The next
character following DLE is
tested for "Exit Text Transparency" and SYNC character. If the next character is
a SYNC, it is stripped as was
the DLE; however, if the next
character is a DLE, it is
passed as data.
TRANSMIT: Adds another
character which is used for
DLE, DLE in the transparent
mode.

Clears the GO bit and sets
OONE for the current CC
register in use (P or S) after
the control characters are
transferred to core. The CC
does not flip to the next
register when this bit is used.
When framing again occurs,
transfers resume with the curren t CC and BA. If a BCC
test/append is in progress, the
DONE interrupt is held up
until the BCC test/append is
completed.

NOTE
The character detect register must contain DLE
in both bytes at the address where SEQ 9 is set.
This is due to the hardware needing to know
what a DLE is.
DLE stripped (Rx) or added
(Tx) is always deleted from
the error detection logic
(BCC).

3-19

Bit
10

Function
TxPAD

Description

TRANSMIT

Bit
Function
12-13 (Cont)

ONL Y: Insert

pad character(s} following the
last characters to be transmitted, as in EOT, PAD or
EOT BCC PAD. The PAD
character consists of all 1s.
Refer to the appropriate
cautions if VRC is enabled.

If a BCC test/append is in
progress,
the character
detected interrupt is held up
until the BCC test/append is
completed.

A jumper is available for
selecting one or two pad characters. The DQll requires
one NULL (PAD, SYNC,
etc.) character following the
last character to be received.
This is due to the BCC registers and double-character
transfers. The shipping configuration is always set for
one pad.
11

Rx. BCC
EXCLUDE

12-13

Rx. CHARACTER FLAG

Description
character flag if a double or
greater than 8-bit character is
detected.

14-15

Rx/Tx
CHARACTER
MATCH

These bits define bytes in the
character detect register for
comparison with the content
of the transmit and receive
shift registers.
For example, bit 15 should
be set to compare with a
stored STX (HB character
detect), and bit 14 should be
set for DLE STX (LB, HB
character detect respectively).

This bit allows any single
control character (as specified
by bit 15 if less than or equal
to 8 bits and bit 14 if greater
than 8 bits) to be excluded
from the BCC accumulation
when in the non-transparent
mode. When this bit is used,
the baud rate must not exceed 250K.

The effective character detect
storage space can be increased
by using bits 15 and 14 on a
single-character detect address. In this case, the SEQ
control function is dominated
by bit 14 which is important
for character flags, transparency control, etc.

These bits cause the character
nag to be set and also iatch
the address of the control
character into four CHARACTER DETECT bits (11-8)
for a minimum of one character time. The address
changes when the next character is detected.

The advantage of using bits
14 and 15 on a single entry
can be demonstrated on an
entry such as DLE STX. If
STX alone is detected, bit 15
allows SEQ control functions
to be executed. However, if
both DLE and STX are
detected, bit 15 will be ignored and bit 14 allows the
selected SEQ functions to be
executed; that is, a doublecharacter match is required to
enter text transparency.

Bit 13 causes a character flag
if a single (less than or equal
to 8 bits) character is
detected. Bit 12 causes a

3-20

3.5.4.7 Receive/Transmit Block Check Character (BCC)
Registers - The Rx/Tx BCC register (register pointers 15
and 16, respectively) provide a 16-bit, read-only register for
monitoring the BCC register as a maintenance function. The
Rx BCC operates on a one-character delay from the
incoming data. If an error is detected, the Rx BCC register
is cleared immediately, and the Rx BCC error flag is set.
The Tx BCC functions one-bit time behind the transmitted
data. The Tx BCC is right.;justified, and bit zero is the Least
Significant Bit (LSB). The BCC length must be a multiple
of the character size.

Specific instructions for programming the Rx/Tx POLY
register are given below using the CRC 12 polynomials as an
example.

3.5.4.8 Rx/Tx Polynomial Register - A 24-bit prog~am
mabIe register is used to store the polynomial used in
generating the BCC character during transmission or
checking the BCC character during reception. The polynomial must be common to both transmitting and receiving
stations so only one register is required.

Assign polynomial terms to register bit
pOSitions. Assign the second highest term to the
o bit position. The highest term is always
ignored because the hardware automatically
includes it. Proceed from the second highest
term, in descending order, with the last term (1
or XO) in the highest bit position.

Put a 1 in each register bit position that
contains a term in the polynomial. Put a 0 in
each register bit position that does not contain
a polynomial term. All other unused bit positions must contain Os.

The following chart shows the octal value of the Tx/Rx
POLY register for some polynomials up to 16 bits in length.

The basic register is 16 bits long. It can be expanded to 24
bits. MISC register bit 6 is used to access the additional 8
bits (16-23).

Polynomial

x6 + 1 (LRC 6)
X 8 + 1 (LRC 8)
X l6 + 1 (LRC 16)
Xl2 + Xl I + X3 + X2 + X + 1 (CRC 12)
X l6 + XIS + X2 + 1 (CRC 16)
X l6 + X l2 + XS + 1 (CRC-CCITT)

Tx/Rx POLY
Register
(Octal)
000040
000200
100000
007401
120001
102010

Example
Load the CRC 12 polynomial into the Tx/Rx POLY register. The polynomial is Xl2 + XlI + X3 + X2 + X + 1.
In accordance with Step 1 above, the bit assignments are shown below:

115 114 113 112 111 110 1 9 1 8 1 7 1 6 1 5 1 4

Bit Position

In accordance with Step 2 above, the binary values are assigned as shown below:

115 114 113 112 111 110 19
X
x2
10
0

0
0

II II I
7

7
3

6
4

5 4
x6 X7

3-21

3
8

Bit Position
0
IO
XlI
Term
X

X
0

Binary
Octal

3.6 GENERAL PROGRAMMING PROCEDURES

3.6.1 Introduction
This section describes, in general, the operational characteristics of the DQII that have programming significance.
Specific functions are described in relation to the basic
DQll and the DQII-AB and --BB options. Five basic
programming examples are shown:

Assert RX DONE and TX DONE flags to
indicate to the PDP-II processor that reception
or transmission has been completed.

Two character count registers and two bus
address registers are provided for both the
receiver and transmitter which allows maximum
PDP-ll processor/program response time for
RX and TX DONE flags.

Provides three switch-selectable control characters. The Character flag bit is set to notify the
program that the selected character has been
received.

Sets the Data Set flag to notify the program of
a change in the status of the data set.

Example 1: Clearing the DQ 11 after powering up.
Example 2: Starting the transmitter using the test
loop mode.
Example 3: Starting the transmitter and receiver
using the test loop mode.
Example 4: Looping the transmitter and receiver
and using the BCC feature.
Example 5: Looping the transmitter and receiver
and using the BCC and protocol features.

3.6.3 Error Detection Option (DQII-AB)
An additional module (M78I6) provides transparent data
block transfers with error control. Under limited program
control, it performs the following functions.

3.6.2 Basic Unit (DQII-DA/EA)
The basic DQll performs the following functions under
program control.
1.

Bidirectional conversion of signals (voltage
levels) between the data set (EIA or current
loop) and the DQll (TIL).
Controls two data set leads: Request to Send
(RS) and Data Terminal Ready (DTR).
Monitors four data set leads: Carrier Detect
(CO), Clear to Send (CS), Ring Indicator
(RING), and Data Set Ready.

In the receive mode, serial data is converted to
parallel data and transferred to the PDP-II
memory. In the transmit mode, parallel data
from the PDP-II memory is converted to serial
data for transmission.

Provides up to 24-bit polynomials for longitudinal redundancy checking (LRC) or cyclic
redundancy checking (CRC).

Provides two block check character (BCC)
generators. One to test BCCs (receive) and one
to append BCCs (transmit).

The transparent mode is hardware-controlled,
using two bits of the REG/ERR register. When
bit 14 (ENTER T) is set, transparency is
entered when the related character count is
used. When bit 13 (EXIT T) is set, it allows exit
from transparency in any subsequent character
coun t field.
This mode of operation is called total transparency to differentiate it from the same mode
when it is initiated by the protocol option
(DQII-BB). Under protocol control, it is called
transparent text.

Data transfers to and from the PDP-II memory
are performed during NPR cycles at the rate of
one per cycle. Only word transfers are used;
therefore, in double-character operation, a
word transfer contains two characters.

3.6.4 Protocol Option (DQ11-BB)
Adding the M78I7 module to the DQll-AB configuration
provides programmable hardware control for characters
equal to or less than 8 bits in length (single or double
characters ).

Character size is selectable up to 16 bits. Single
characters must contain more than 8 bits.
Double characters are limited to 8 bits or less.

3-22

Under program control, it performs the following functions.
1.

Controls BCC computation. Allows exclusion
of a character from the BCC computation when
operating in the non-transparent mode.

Sets the Character Detect flag when a select
control character is received.

Transmits a PAD character (all Is) following
the last character to be transmitted.

Inserts and deletes DLE characters.

Clearing Registers During Power Up
When the PDP-II system is powered up, the Initialize
(INIT) signal is generated and distributed throughout the
system to clear registers, flip-flops, etc. The character count
and bus address registers and the memory extension bits
(REG/ERR register bits 13 and 14) are not cleared by
INIT. It is imperative that these registers and bits be cleared
before continuing. They are cleared by writing Os into
them.
Preparation for Transmission
The DQll is prepared for transmission by loading the BA
and ee registers. The BA is loaded with the address
(PDP-ll memory) of the first word to be transferred to the
DQII for transmission. Data is transmitted LSB first.

The ee register is loaded with the 2's complement of the
number of characters to be transmitted. The ee/BA
counter is incremented only. When loaded with the 2's
complement of the character count, the number of counts
remaining until overflow (aliOs) is actual number of
characters.

3.6.5 Operational Features with Programming Significance
VRC (Parity Check)
The basic DQll provides Vertical Redundancy Checking
(YRC) or parity checking. YRC in a synchronous communications system is of questionable usefullness; therefore, its use is not recommended.

Preparation for Reception
The DQII is prepared for reception by loading the BA and
ee registers as in preparation for transmission. The BA is
loaded with the address (PDP-II memory) of the first word
to be transferred to memory. The SYNe register must be
loaded with the correct sync character.

Odd or even VRC is switch-selectable. Care should be used
when implementing VRC during double-character operation
in the receive mode with an odd character count. The
receiver shift register must contain two characters before its
contents are transferred to the receiver buffer register and
on to the PDP-II memory. With an odd count, the receiver
shift register contains only one character when the data
ends. Another character must be shifted in to fill this
register so the transfer to the PDP-II memory can take
place. This fill character must have correct parity or an
invalid YRe error flag is generated.

Total Transparency (DQll-AB Option)
As described in Paragraph 3.6.3, total transparency is
implemented by the AB option using REG/ERR bits 14
(ENTER T) and 13 (EXIT T). REG/ERR bit 12 (14, 13
WRITE EN) must be set to allow the state of bits 13 and 14
to be written into the ee/BA register.

3-23

3.6.6 Programming Examples
EXAMPLE 1 - Clearing the DQll after powering up .

1
2
3
4

000000
000000
160010
160012

160014
160016

004010
002000
002002

7
8

16001~

10
11
12
1"
14
10
10
11
18

1771e4
1717e-4
002-400
002200
01~026

20 01000
21 01004
22 01012

001000
1000~7

160010
0127~7

000010
0020"0

0127~7

010000
002002
2\) 01020 013737
2102002
160014

24 0102r5

00:50~7

160016

01032

0627~7

000200
002002
20 01040

0003~7

002000
27 01044 001305
2'; 0104tS Q!00000
2111
000001'

STMSCI.

• AS!CT

.fNi8C AB:t
RXC8R-1C0010
TXciR'loe"12
ERRfG·le001 4

SfCRfr;'16k10i~
WENPil~002

oQRt.G il le0rDl0

ITrtANSMITT CHARACTtR COUNT
,Rt.CtIVE LENGTH
IRt.CflVE BUrfER
'TRANS~ITT BUFfER
;SYNC CHARACTER

TXWC'1777b4
RXWC I 1777C4
RXBI.:1F-2401a
TXBOF.2201.1
SYNC i 1302t>

,,
,

,-11.100

POINTtR TO 0

CL.R~'.DQRtG

;S~T

MOV.lrD".~OUN!

,St.T TO COUNT ., OF REGS TO ~I.EAR

MOV·l"000,'.W~N~

,seT POINTtR AND BIT 12 IN Wt.NP

lSIMUV

~.WtN~".~H~E~

,PUT INTO tRREG

C~R'.~ECR~G

AOD "il00, •• Wt.NP

COUNT

otC.,,(.;OUNl

'O~CREMENT

SNt. 11

,Bfo(ANCH IF NOT DONt.

HALT
fNU
-

TA81.~

CUUNT • 0'Hl1tJ00

• 004010
EHHfli • le001"
RXWC • 17176.
TXtJUF • 002200
• 002002
AtsS.
0010~0

000

000000

001

RXBUF , 01&12400

Ct1AH

St-CHEbl 10lile
TXCSR- 1~11tJ12

•

Wt.N~

•

,CHARACTER LENGTH

CHAkil.010
COUNT.200rD

3-24

• le0fJle
• 013020
,
SYNC
Txwt • 177754
OQREG
RXCSR

le001~

EXAMPLE 2 - Starting the transmitter using the test loop mode. Includes clearing of the DQ 11 per Example 1.

1
2
~

o
6

7
8
i

10
11
1~

1;)
14
10

000010
00"010
tel0t0
160012
180014
t6001e
004010
QH1I2000
002002
160015
1777e4
1177e4
2102400
002200
01"02e

,AlteT

,fNABC ABa

RXC5R-le0010
TXCSR"180012
ERAE.G·160014

S~CH£ij.16"01e

,CHARACTER LENGTH

CHAHit10i0-

COUNT.2000
WENP.1t002
DQRt.G.lt;0010

,THANSMITT CHARACTtR COUNT

Txwt i 1777C4

,RtCflVE LfNGTH
,RtCEIVE BUFfER

Rxwt"171704
RXSOfil2400

;TRANSMITT SOFFER
,SYNC CHARACTER

TXBUF.220ft'1

,,
,

SYN~.1302~

11)01000
111
20 01000 10~0"7
1600U5
21 01004 012737

•• 1~00
CLR~'.OYRtG

;StT POINTtR TO "
,StT TO COUNT # OF REG! TO CLEAR

000010

002000
01012 (1112737
010000
002002
2" 01020 0137~7
002002
160014

,StT POINTtR ANO BIT

00~0;,7

lel016
0627,,7
000200
002002

IN WfNP

ClR",.:SECRtG
..
--

2b 01040 00~~~7

Ot.C./U,;OUNl

,Ot.CREMfNT COUNT

21 01044 001~t):5
26 0104e 000000

aNt 1~
HAL.l

;BWANCH IF NOT OONf

211
30 01050 012737

MOV-5~0~,!#~R~~b

2102000

ITHt

~ULLUWING

CODE IS ADDED TO PROGRAM 1
'SET SEC POINtER TO-MIse REG

00~0"0

160014
012737

lCI-E.AR REGISTt.R

000040
160016
012737

,SfT SEC POINTER TO TXBA REG

011000
160014
012737
002200
160016
34 01100 012737

ILOAD TXBA PRIMARY TO TXSUF
ISET SEC NEG TO TxCt PRIMARY

011400

160014

iLOAO TXCC wITH

0127~7

177764
3-25

TXW~

160016
~e

01114

0127~7

00:5000
ItUI014
37 01122 0121;,1
211214010
160016
315 01130 0121~2~1
160012
351 01134 0327~7
000200
1621012
40 01142 001174
41 01144 210012100
42
002200
026
4'" 022021
026
02201
0221212
001
02203
010
02204
002
0220~
101
02200
102
02207
103
104
02210
02211
105
02212
106
02213
003
44
2100001'

I~HtsOL

MOV"5""0,~.~RHt!

ISET SEC POINTER TO Mlse REG

HOV.4010,!~~~~R~G

18 BITS/CHAR ANU TEST LOOP

INC ••'...1XCSW
-

ISET TX GO 6IT

2SleIT.200".TX~~~

Bt:Q

'LOOK FOR TX DONE
;~RANCH

IF NOT DONE

HALT

,-22""
,8Y!~

2~,26,01,~121,02,11211,1"2,103,11214,le~,106,~3

.~NI)

TA8L.e:

CHAM

• 00421121
EHRtG • le02114
Rx-i; • 171764
TXI:HJF • 002200
Wt.NP • 0022102
•. AtsS. 01212214
0210211210

CUUNT • "02000

OQREG •

StCHEbl lCH"~1e

RXC;SR - 1812112110
SYNC - 01312120

AXBUF • 002400
tXCSR-'

1~01D12

C'l00
12101

3-26

Txwt

le12l01~

177764

EXAMPLE 3 - Starting the transmitter and receiver using the test loop mode. Includes clearing of the DQ 11 per Example 1.

000000
001000
180010
180012
160014
180016
004010
002000
1'02002

a
4

e
e
7

8
g

le001~

10
11
12
I;,

1777e4
1777C4
002400
002200
013026

10
10

.ASe:CT

,fNAeC AB3

RXCSRiilC00UD
TXC5R·leJ0012
ERRt.G 1 le0rt114

s~t~£(j'16rD01tj
'C~ARACTER

CRAM.i0i0
COUNT i 2000

LtNGTH

W!NP12002

OClRt.GIIlb0rt110
TX .. Cil117704
RXWCI177704
RX60Fil2400
TX8UF1220"
SYNC i 13020

1TRANSMITT CHARACTtR CUUNT
1RtCEIVE LENGTH
JRtCtlVE BUFfER
1THANSMITT BOfFER
ISYNC CHARACTER

,
1
I

1';

151
001000
20 01000 10:t037

,11000

IStT POINTER TO "

CLR~'.OlaJRtG

15001~

1StT TO COUNT - Of

21 01004 2112137

REG~

TO CLEAR

000010

002000
012737
2110000

IStT POINTtR AND BIT 12 IN WfNP

2102002

2" 01020 013737

2102002
160014
00~037

CLR._~Et;R~G

160016
2162737

ADO#2ft!10,'"WtN'''

000200
002002

20 01040

00~~37

"'02000
21 01044 001~e5
2i 0104e 0I000qJ0
251

010~0

0127e7

D~t!~~OUN!

'D~CREMENT

BNt 11
HAL.l

'B~ANCH

MOV.~~00,~Rwt~

00~000
1~e736

"'12737
000040

160016
31 01064 012731

010000
160itl14
012737
002400

160016
3" 01100 012131
010400
160014

3-27

COUNT

IF NOT DONt

'SET SEC POINTtR TO MIse REG

34 0110e

0121~7

HOV.RXW~,~_St~H~G

'LOAD RX~C WITH HXWC

MOV~1~e00,'.~~N!G

'Se~!CT

MOV~TXBUF,'.I~~~E~

II.OAO TXt5A

MOV.11400"~t~M~G

'S~~ECT TX~C

MOV.TXW~, •• ~t~R~G

'LOAD TxtC WITH TXWC

MOV.'-~0~, !.~fHCt.!

'St~ECT

MOV.SYN~,!.8~~H~G

,LOAP SYNC REG WITH SYNC

MOV"~H100, !_~Rf(t;.~

,St.I.ECT MISC RfGlSTEW

HUV#~HA~".~~~H~G

,SELECT LENGTH AND Tt.STLOOP 1:51T

INC",.WXCSH

,5fT RX GO BIT IN RXCSR

INC'.,XCSH

,St.T TX GO BIT IN TXCSH

1777e4
1600U5
30 0111--

0127~7

011000
160014
30 01122 012137
002200
100016
37 01130 012737
011400
160014
3" 01138 012731
177164
160016
3Y 0114' 12112137
004400
160014
40 01152 012137
013026
160016
41 01160 012737

TXBA PRIMARY
~lTH TX8U~

PRIMARY

SYNC RtGlSTEW

00~000

160014
0116e 0121.57
004010
16121016
4" 01114 00~231
160010
44- 01~00 00~237
16121012
40 0120' 12132737
12100200
160010
40 01212 001174
47 01214 00121000
4~
002200
4~ 02200
026
026
02201
02202
001
010
0220J
022011
002
4~

0220~

02200
02207
02210
212211

02212
0221J

~'"

3SIBIT.200,'.RX~~R

,BRANCH IF OONe. tsIT NOT SfT

Bt.Q 31
HALT

,.220t!

.t5YiE 20,~~,~1,~0,02,101,102,10J,104,10~,10~,03

lH1
102

103

1"'105

106
003
000001'

;WAIT FOR UONE BIT

,fNU

3-28

SYMisOL TABl.t
COUNT • 002000

• 10.12110
• le0121'.

CI'tAfit

0ld2400
StCWEt;. 100i1e

RX8Uf' •

EHRtG
Rxwe • 17770.

TXC5R-. 1~0ld12

TxeCIf" • 002200
NtNf'

• -ASS,

00212102
(Ut221.

OQRf.G I 180010
RXCSR • lC001"
SYNC • 0i302C
Txwt -177764

000
001

000000

Table 3-1
Message/Data Used in Programming Examples 4 and 5

Symbol
SYN
SYN
SOH
BS
STX
A
B
e
D
E
F
ETX
Bee
Bee

ASCII Character
Binary

Octal

00010110
00010110
00000001
00001000
00000010
01000001
01000010
01000011
01000100
01000101
01000110
00000011

26
26
1
10
2
101
102
103
104
105
106
3

BCC
Function

Protocol
Function

Hardware
Function

None
None
ENTER T
Starts Bee.
All characters
included until
ee overflow
and EXIT T
tests or appends
BCe.

None
None
None
None
STX starts Bee
on next character
(a). Include all
character until
Bee test/append
sequence is
detected. For TX,
add DLE before
ETX then send
Bee. For RX,
strip DLE then
test Bee after
ETX.

{ Syn~hronize
receIVer
RXActive

3-29

EXAMPLE 4 - Looping the transmitter and receiver and using the BCC feature. This example shows how to program the
BCC Option (DQII-AB) using the ENTER T/EXIT T control bits to provide block transfers in the transparent mode.
The polynomial that is loaded into the RX/TX Polynomial Register is arbitrary and is used only to illustrate the
programmability of the register.

1
2
;,
4
:5

e
7
8
9

1"
11

1"
1~

1:)
Ie

000000
000000
160010
160112
160014
160016
004010
002000
002002
16001:5
1777e4
1777e4
002400
002200
"'1~02()

.A8~~!

.!NABL. ABa
RXCSRii160010
TXCSR.18001i
ERRtG-1C0014
SItCHE"ll()00i6

,CHARACTER ~fNGTH

CHAH.~li0

COUNT·200lD
WENPIUl002

OQ~tG-le0010

,THANSMITT CHARACTER COUNT
,RtCEIVE ~ENGTH 'RtCflVE BUFFER
'THANSMITT eOF~E~
'SYNC CHARACTER

TXWC I 177704
RXWC.l1i104
RX60F·2400
TX~OF.220'"

,,
,

SYN~i13020

Ii
151
20 01000

001000
10~0"7

160015
21 01004 0127,,7
000010
002000
22 01012 012737
010000
002002
2" 01020 Qtl~7"7
002002
160014
24 0102e; 0000,,7
160016
2!> 01032 ~62737
000200
002002
20 01040 0003~7
002000
21 01044 0013e55
2a; 01040 012705
000017
2Y 010~2 1127"7
000010
160015
30 01060 00~0J7
160016
31 01064 11273'
01&10014
160015
32 01072 000037
lfH!l016

,-1000

,SET POINTER TO 0

CL.RB.-OQRtG

'S~T

TO COUNT. OF

REG~

TO CLEAR

,StT POINT~R AND BIT 12 IN WENP
lS t HOV

'_WtN~"~tRHEG

'PUT INTO ERRfG

CL.R._:SE~R;G

AOO-20rt1, ."Wtl''H''

Dt.C."LOUNT
- - -..
-

,DtCREMENT COUNT

BNt 1~
MOV-l/,R5

,BHANCH IF NOT DONE
'MOV AcaUNT INTO R~
'St~

CHAR AODRESS

,CL.EAR
,SELECT SEQ ADDRfSS
;CL.EAR
'INCREMENT CD/SEQ POINTER

10~2"7

160010
3-30

34 01102 00~30~
01104 0013e2
30 0110e 1127~7
000017
3~

,oec COUNT

DE.C R~
BNE 21
HOVt"fl7,
'.Dy~t.G
.
-

;GO BACK If NOT DONE

CL.R!~~E~R~G

'CLEAR

,~OAD

POL.Y-SE~ECTOR

1(S001~
~1

01114 el:tI~7

150016
38 01120 "00011
~S; 01122 0127~7
00:tlee
160014
40 01130 0127",

HAL.T

MOV~~1D0l1,!.tRH~~

'SET SEC POINTfR TO MIse REG
'CLEAR REGISTER

000040

160016

41 0113(5

'S~~ECT

0121~7

RXHA PRIMARY

01000e
160014
42 01144 012''''
002400

ILOAD RX6A WITH RX8U~

160016
4\)

011~2

15EL.ECT RXCC REGISTfR
---

0121~7

050400
160014

'LOAD RXCC WITH RXWC

0127~7

177704
160016

'S~LECT

"'127~7

TX6A PRIMARY

011000

160014

;LOAD TX6A WITH

40 01174 0127\)7
002200

160016

TXBU~

,SELECT TXCC PRIMARY

47 01202 0127~7
0~1400

160014

;LOAD TXCC WITH TXWC

41:5 01210 0127~7

177704
160016

'SELECT SYNC RtGISTEW

0127~7

004400
160014

50 01224

'LOAD SYNC RtG WITH SYNC

0127~7
01~026

160016

,SELE.CT MISC

51 01232 121127"7

R~GISTEH

00:t000

16.0~ 14

;SELECT LENGTH AND TtSTLOOP ~IT

0127;,7
"'04010
160016

;St-LEeT ~XWC

121127;,7
032400
160014

0000"7

Stc

'LOAD EXIT T ,CLR wC

CL.R'.~Et,;RtG
. .- ....

160016

'SELECT TXWC stC

0127;,7
033400
160014

3-31

~OAU

CLR'''5ECRt.G

,EXIT T,CL.R

MOY.7 400, !.~·RWt.~

1SfL. BCC POL.Y

MOY.l1~~301!·!t~RfG

IL.OAO

oy el~0e 0002J7

INC!~N)(~Sf(

,SfT RX GO BIT IN RXCSR

61 01J12

0"~2J7

INC!~!)(~SIi(

,SfT TX GO BIT IN TXC:SM

e1"le

0~2737

t5b 0126f5

00~037

160015
01- 01272

0127~7

007400
160iU 4
!51f 01J0e 0127J7
110730
1621016

160010

160012

000200
160010
62 11"24 00177.
6\) 01J2C 0000210
154
002200
tib 02200
025
025
02201
001
02202
010
022o"
212204
002
0220r)
101
02200
102
103
02207
10.
02210
10~
02211
106
02212
003
02213
6b
0rc10001,

JsIBIT.2~0,'''RXC~R

n~AIT

fOR DONE BIT

,BRANCH'IF DONt

BE.Q 31

HALT

~lT

NOT- SET

,-220'"

.8Y!E 2~,~6,,,~,~0,02,101,102,10~,10~,10~,10f5,03

,fNU

TABL.!.

S~Mt50L

Ct1A" • 0214010
EMRt.G
lee014
RXWt,;
1777t54
TX60F • 002200
WtNf'
002002
, - AtsS. 002214
000000

•
•
•

COUNT • 0020021

AxaUF • 0rd2400

St.CRElil 100ile

tXCSR-' 10"~12

000
001

3-32

DQRt:G • 1150010
RXCSR • le00le
SYNC • 01:S02fS
Txwe
177784

•

EXAMPLE S - Looping the transmitter and receiver and using the OCC and protocol features. This example shows how to
program the Protocol Option (DQII-BB) and the OCC Option (DQII-AB) using the Protocol Option to control the BCC
Option.
Detection of STX starts the BCC accumulation on the chracter following the STX. Detection of ETX causes the transmitter
protocol control logic to insert a DLE (excluded from OCC) before the ETX and then generate two OCC characters.
The receiver protocol logic detects a DLE and checks the next character. It is an ETX. This sequence (DLE,ETX) generates
the BCC test function after the ETX is included in the BCC. The DLE is excluded from the BCC .

1
2
3

•

e
ti

7
8
g

10
11
12
1~

14
10
10

000001
01010'
151111
18'012
le0114
100118
004110
012101
012002
16001e
1777e4
177704
0024210
002200
01;'02e

• AS~~~

.~NA8L.

A8~

RXCSR·le0010
TXC$Rwl00012
ERRf.(i·l00014
sr;cRe".ie001CS

CHAHi~ll1

COUNT"20Ie
WENP.2002
CQRt.G-'00"10
TXweil1777c4
RXWc.i777C4
RX8UF.2~0"

T)(60'-2201&1

16001~

21 01014 0127~7
000010
002000
2~ 01012 0127~7
010000
0020212
2~ 01020 0137"7
002002
160014
24 0102e5 00'0~7
160016
20 01032 0027J7
000200
002Vl02
2~ 01040 00~3J7
002000
2' "'1044 0013es5
2i 0104e 0127ee
000017
251 01052 1127;,7
000010
160015
30 01060 00'0~7
160016
31 01064 1127 ~7
000014
16001e

'TRANSMITT CHARACTER COUNT
1RtCflVE LENGTH - .
'RtCfIVE BUfFER
'THANSMITT 60f~ER
'SYNC CHARACTER

SYNt,;·1~02b

Ie
0010210
151
20 01000 10~0;'7

'CHARACTER LENGTH

,-1001&1

CL.R~'.O(,1R~G

,St.T POINTER TO 0

MOV"10,!.~OUN!

;St.T TO COUNT " OF REGS TO CLEAR

MOV.lft'J000,'''W~N~

,St.T POINTt.R AND BIT 12 IN WfNP

lSIMOV

'.~t.N~,'~~~WEG

,PUT INTO t.RREG

CLR'''~ECR~G
A~D"2"'0,'"WtN'''

Dt.~!~C;OUN!

,Ot.CREMENT COUNT

BNt. 11

,BWANCH IF NOT DONt
'HOV ACOUNT INTO R~

MOV"l~,Re
2SIHOV~.10,."OU~~~

'S~L

CHAR ADDRESS

CLR'.~ECR~G

7CLE.AR

MOV~.14, '.O'.U~~G

,StL.fCT SEQ ADDRtSS

3-33

32 01072

00~0~1

leflJ016
3~ k'107e 0627",
0021200
160010
34 01104 01l1~305
30 0111l1e 0013~1
3~ 01110 112,,,7
000017
150iJU5
37 01118 00~0'"
160iJifJ
36 01122 000000
3U 01124 00~e;'7
160010
40 121113121 1127"7
000010
15flJ01e
41 01130 0127~7
001420
160016
42 01144 1127~7
"'021014
16001!5
4" 01152 0127",
041024
160016
44 01160 0127~'
000400
160010
40 0116«5 1127;57
000010

CL.R'''5'ECRt.G
-

'CI-EAR

AOD.2fD0""RXC~~

'INCRt.MENT CD/SEQ POINTER

DfC RO
BNE 21
HUVt,,_ 17, '''[)QR~~

,OtC COUNT
,GO SACK If NOT DONE
'LUAD POL.Y S~LEC!OR

CLR"~~E~R~G

,CL.EAR

HALT

CLR!.HX~SH

,SET CHAR OET POINTEW TO 0

MOV~.,~0""OYR~~

,SEL CHAR REG

MOV.001420,!.~f~RtG

'L.OAD OLE. E.T)(

MOVtH'14, '''C(alR~G

,SEI. SEQ

HOV.04102~""~t~RfG

'LOAD '-'UNCTION 2

MOV"4fD0,'''RX~~R

,SI:.T POINTt.R TO 1

HOYtH, 10, '''DYH~G

,St.L. CHAR REG

MOV.1000,!.~E~H~G

;L.OAD STX

HOVt", ~ 4, '''OQHt.~

,St.L. SEQ

MOY.10012,'.S~~~tG

'L.OAD fUNCTION 1

MOVlH' 17, ,"OQHt.G

,St:L. POLY REG

MOV~10201~"~~~~RtG

,L.OAO CRt CCITT

MOV

,SEL.ECT TXSEt

16001~

4C 01174 0127;,7

41
4t:t
4Y
50
51

00100121
1621016
01202 1127;,7
0002114
160015
01210 0127"7
0121012
150016
0121~ 1127",
000017
16"'015
01224 0121~7
102010
160016
01232 0127"7
033400

.3~40~,'.~HWEu

160014
5~

01240

00~037

CLR".~ECRtG

;ANO SET EXIT T

MOV.5000,!.~RHt.!

ISET SEC POINTER TO MISC REG

MOV.4"".~E~~~~

'CL.EAR REGISTER

160016
53 01244 0127"7

00~000

180014
54 01252 Qt127"7

000040
150016
3-34

01260

0127~7

MOV_l~000,'_tWHtG

'SE~ECT

MOV.RX8uF,'~S~~WEG

ILOAD RXbA WITH

HOV_10400".tWRtG

'SELECT

MOV.RXW~,!.~t~H~G

'~OAO

MOV.l~00e,.~t~R~G

,SELECT TXBA PRIMARY

MOV.TxeUF,'.S~~~E~

'LOAD TXBA WITH

HOV~11400,'.~HR~G

'SELECT TXCC PRIMARY

MOV.TXWC,!_5t~R~G

'LOAD TXCC WITH TXWC

MOV.4~00, •• ~~W.~~

'SE~ECT

HOV.STN~,!.~t~R~G

;LOAO SYNC REG WITH 5YNC

MOV"500rl1,!.~RHt~

,SELECT MIse Rt.GISTEw

MOV~~H.R,.~~t~W~G

,SE.L.ECT LENGTH ANO Tt.STL.OOP BIT

INC'.WXCSW

'SET RX GO BIT IN RXCSR

INC~~!Xt;Sw

ISET TX GO BIT IN TXCSR

010000
160014
~c

0126e

0127~7

002400
160016
~7

01274

0127~7

01m400
18mll"

- 01~02 0127~7
177715'

~ts

180015

ell 01~10 0127~7

011000
16001"

01~1e

01~24

0127~7

002200
160016
0127~7

011400
16001"

62 01~32 0127~7

1777154
1150016

01~40

0127~7

004400
160014
54 01346

0127~7

013025
160016
60

01~~4

0127~7

RX~A

RX~C

PRIMARY
~XBU~

REG~STEW

RXCC WITH RXWC

TX8U~

SYNC RtGlSTEW

00~000

160014
5c

rlI1~62

0127~7

004010
160016
61- 01J70

00~2~7

160010

6es 0137. 00~2~7

150012

eli 01400 0327J7

000200
160010
70 014015 001714
71 01410 000000
002200
72
7~ 11'2200
026
026
02201
001
02202
010
0220~
002
0220·
0220:5
101
022015
102
103
02207
104
02210
105
02211
106
02212
0221~
"03
74
000001 '

3SIBIT.2~0,'''RXC~R

'WAIT FOR DONE BIT
,BRANCH IF DO Nt

BEQ 31

~IT

NOT SfT

HALT

,-2201'0

.BY!E 20,~6,0~,!0,02,101,102,103,104,105,~06,~3

.fNU
3-35

SY'U,OI. TA8'-!:

C"AM • 1141111
EMR!G • 18101'
Rxwt
11778.
TX8Ufl'
Im22111
le2el2
NtH"
.-ASS. 01221.
101010

CUUNT • (UJa""0

RXCSR • 1~Hae10

TXCSR-' 1~0"12

Txwt

0.,2'"0
StCREija 1,,"iles

•
,•

SYNC

•• 1177e4
el~12e

0e0
0e1
Test No.
(Octal)

3.7 DQll DIAGNOSTICS
3.7.1 General Information
Seven diagnostic programs are used to check the DQll.
Each one is supported by a separate document that
discusses its purpose and use. As a convenience to the user,
this section describes the tests performed by each diagnostic. The code and name of each diagnostic is listed
below.
1.

OQRfG • leeel'

RJl8UF •

MAINDEC-II-DZDQA-A-D - Basic
Tests, Part 1

Logic

Function

Address test for primary registers. Each
primary register is loaded with a different
number and read out to verify that the
correct register was addressed.

RX CSR bit 1 read/write test

10-24

RX CSR bits 3-15 read/write test

25-33

TX CSR bits 3-9 read/write test

TX CSR bit 15 read/write test

Test for all Os in TX CSR high byte if Data
Set Control Module M7815 is not installed.

36-51

REG/ERR CSR bits 0-11 read/write test

Secondary register addreSSing test. (With or
without character detect and BCC options
installed.)

MAINDEC-II-DZDQB-A-D - Basic
Tests, Part 2

Logic

MAINDEC-ll-DZDQC-A-D - Interrupt
Tests

Logic

MAINDEC-II-DZDQD-A-D - Receiver
Transmitter Tests

and

MAINDEC-II-DZDQE-A-D - RX,
MISC Register Tests and BCC Tests

and

MAINDEC-II-DZDQF-A-D - Sequence Register Tests

Secondary regIster addressing tesC (Wiih
character detect option installed.)

MAINDEC-II-DZDQG-A-D - DQll Trial Program (Parameter Input)

Secondary register addreSSing test. (With
BCC option installed.)

55-74

SEQ register bits 0-15 read/write test

MISC register bit 0 read/write test

Start-up

MISC register bit 1 read/write test

Address selection test for Receive CSR

MISC register bit 3 read/write test

Address selection test for Transmit CSR

100-105

MISC register bits 6-11 read/write test

Address selection test for REG/ERR CSR

106

MISC register bit 15 read/write test

Address selection test for secondary register

107-126

POLY register bits 0-15 read/write test

3.7.1.1 DZDQA-A-D Tests
Function

Test No.
(Octal)

3-36

Test No.
(Octal)
15

3.7.1.2 DZDQB-A-D Tests
Function

Test No.
(Octal)
Start-up

Memory extension write enable test. Set 14,
13 WRITE EN bit. Select bus address
memory and clear it. Verify that 14,13
WRITE EN bit is cleared.
Memory extension bits read/write test. Read
MEM EXT bits with 14, 13 WRITE EN bit
cleared. Attempt to change MEM EXT bits
and verify that no change occurs.
Memory extension bits read/write test. Read
MEM EXT bits with 14, 13 WRITE EN bit
set. Attempt to change MEM EXT bits and
verify that change occurs.
Bus address memory extension test. Load
each bus address with a different number
and verify.
Bus address and character count memory
test. Put a 0 into each CC/BA word and
verify.
Bus address and character count memory
test. Load 177777 into each CC/BA word
and verify.
Bus address and character count memory
test. Load 125252 into each CC/BA word
and verify.

Bus address and character count memory
test. Load 52525 into each CC/BA word and
verify.

Bus address memory extension data test.
Load 40 into memory extension words in
CC/BA memory and verify.

Bus address memory extension data test.
Load 100 into memory extension words in
CC/BA memory and verify.

Bus address memory extension data test.
Load 140 into memory extension words in
CC/BA memory and verify.

3-37

Function
Character memory addressing test. Each
CHAR MEM word is loaded with its address
and read out to verify that the correct word
was addressed.

Sequence memory addressing test. Each SEQ
MEM word is loaded with its address and
read out to verify that the correct word was
addressed.

Character memory test. Load 0 into each
CHAR MEM word and verify.

Character memory test. Load 177777 into
each CHAR MEM word and verify.

Character memory test. Load 125252 into
each CHAR MEM word and verify.

Character memory test. Load 52525 into
each CHAR MEM word and verify.

Sequence memory test. Load 0 into each
SEQ MEM word and verify.

Sequence memory test. Load 177777 into
each SEQ MEM word and verify.

Sequence memory test. Load 125252 into
each SEQ MEM word and verify.

Sequence memory test. Load 52525 into
each SEQ MEM word and verify.

Receive control and status register master
clear test (Data Set Control Module M7815
installed). Set all RX CSR read/write bits.
Issue MASTER CLEAR and verify that RX
CSR is cleared.

Receive control and status register master
clear test (Data Set Control Module M7815
not installed). Set all RX CSR read/write
bits. Issue MASTER CLEAR and verify that
RX CSR is cleared.

Transmit control and status register master
clear test (Data Set Control Module M7815
installed). Set all TX CSR read/write bits.
Issue MASTER CLEAR and verify that TX
CSR is cleared.

Test No.
(Octal)

Function
Transmit control and status register master
clear test (Data Set Control Module M7815
not installed). Set all TX CSR read/write
bits. Issue MASTER CLEAR and verify that
TX CSR is cleared.
REG/ERR register master clear test. Set all
REG/ERR read/write bits. Issue MASTER
CLEAR and verify that REG/ERR register is
cleared.
SYNC register master clear test - Set all bits
in SYNC register. Issue MASTER CLEAR
and verify that SYNC register is cleared.
MISC register master clear test. Set all MISC
register read/write bits. Issue MASTER
CLEAR and verify that MISC register is
cleared.
POLY register master clear test. Set all bits
in the POLY register. Issue MASTER
CLEAR and verify that POLY register is
cleared.

Receive done primary interrupt flag (RX
DONE P INTR) test

Trans!!ljt done secondary interrupt flag (TX
DONE S INTR) test

Transmit done primary interrupt flag (TX
DONE P INTR) test

Data set interrupt flag (DATA SET INTR)
test

Transmit clock loss interrupt flag (TX
CLOCK LOSS INTR) test

Receive clock loss interrupt flag (RX
CLOCK LOSS INTR) test

Transmit latency interrupt
LATENCY INTR) test

flag

(TX

Receive latency interrupt
LATENCY INTR) test

flag

(RX

Transmit non-existent memory interrupt flag
(TX NON-EX MEM INTR) test

Receive non-existent memory interrupt flag
(RX NON-EX MEM INTR) test

Receive BCC error interrupt flag (RX BCC
ERROR INTR) test

Receive VRC error interrupt flag (RX VRC
ERROR INTR) test

Verify that an interrupt occurs when CHAR
DET INTR and CHAR IE bits are set.

Verify that an interrupt occurs when RX
DONE IE and RX DONE S INTR bits are
set.

Verify that an interrupt occurs when RX
DONE IE and RX DONE P INTR bits are
set.

Verify that an interrupt occurs when TX
DONE IE and TX DONE S INTR bits are
set.

3.7.1.3 DZDQC-A-D Tests
Test No.
(Octal)

Function

Start-up

Step mode verification and clock loss test

Test loop verification

Character interrupt enable (CHAR IE) test

Receive done interrupt enable (RX DONE
IE) test

Error interrupt enable (ERROR IE) test

Data set interrupt enable (DATA SET IE)
test

Transmit done interrupt enable (TX DONE
IE) test

Receive done secondary interrupt flag (RX
DONE S INTR) test

3-38

Function

Test No.
(Octal)

Function

Verify that an interrupt occurs when TX
DONE IE and TX DONE P INTR bits are set.

Verify that an interrupt occurs when DATA
SET IE and DATASET INTR bits are set.

Verify that an interrupt occurs when ERR
IE and TX CLOCK LOSS INTR bits are set.

Receiver basic NPR logic test using primary
BAICC registers.

Verify that an interrupt occurs when ERR
IE and RX CLOCK LOSS INTR bits are set.

Transmitter basic NPR logic test using primary BA/CC registerS.

Verify that an in terru pt occurs when ERR
IE and TX LATENCY INTR bits are set.

Receiver basic NPR logic
secondary BA/CC registers.

Verify that an interrupt occurs when ERR
IE and RX LATENCY INTR bits are set.

Transmitter basic NPR logic test using
secondary BA/CC registers.

Verify that an interrupt occurs when ERR
IE and TX NON-EX MEM INTR bits are set.

Receiver non-existent memory test using
primary BA/CC registers.

Verify that an interrupt occurs when ERR
IE and RX NON-EX MEM INTR bits are set.

Transmitter non-existent memory test using
primary BA/CC registers.

Verify that an interrupt occurs when ERR
IE and RX BCC ERROR INTR bits are set.

Receiver PIS master clear test.

Transmitter PIS master clear test.

Verify that an interrupt occurs when ERR
IE and RX VRC ERROR INTR bits are set.

Transmitter NPR data test (step mode).

Verify that the receiver interrupts before the
transmitter when they are enabled simultaneously.

3.7.1.4 DZDQD-A-D Tests

Verify that the transmitter interrupts only
once when it is enabled.

Test No.
(Octal)

Verify that the receiver interrupts only once
when it is enabled.

Verify that TX ACTIVE can be set and then
cleared by MASTER CLEAR.

Verify that transmitter interrupts at priority
level 7.

Transmit one 8-bit character and verify that
BA and CC registers increment by 1.

Verify that transmitter interrupts at priority
level 6.

4-22

Transmit a character of each length from
2-16 bits and verify that the data out line
goes to a MARK state when transmission is
finished.

Transmitter idle test. Verify idle operation
(transmission of sync characters).

test

using

Function
Start-up

47
50

Verify that transmitter interrupts at priority
level 5.

Verify that transmitter interrupts at priority
level 4.

3-39

Test No.
(Octal)
24

3.7.l.5 DZDQE-A-D Tests

Function

Test No.
(Octal)

Transmitter data reliability test (for characters up to 8 bits in length).

Start-up

Transmitter data reliability test (for characters from 9-16 bits in length).

Test of data reliability through cable and
level converters.

26-44

Receiver character length test (from 2-16
bits per character).

Test of receiver STRIP SYNC function

Memory transfer tests

Verify that SYNC 1 and SYNC 2 set when
RX ACTIVE is set and that they can be
cleared by MASTER CLEAR.

Test of ENTER T and EXIT T functions

Test to force an RX BCC error

TX BCC test using polynomial represented
by 177777.

RX BCC test using polynomial represented
by 177777.

Test of TX BCC and RX BCC using CRC-16
polynomial.

Test of TX BCC and RX BCC using CRC-12
polynomial.

Test of TX BCC and RX BCC using
CRC/CCITT polynomial.

Sync test using an 8-bit character. Verify
that RX ACTIVE, SYNC 1, and SYNC 2 all
set properly.

Sync test using a 16-bit character. Verify
that RX ACTIVE, SYNC 1, and SYNC 2 all
set properly.

Verify that RX CC and RX BA registers
increment properly using an odd character
count.

Verify that RX CC and RX BA registers
increment properly using an even character
count.

Receiver data reliability test (for characters
0-16 bits in length).

Test of TX BCC and RX BCC using LRC-8
polynomial.

Receiver parity error test.

Test of TX BCC and RX BCC using LRC-16
polynomial.

Receiver half-duplex test.
16

Transmitter and receiver data reliability test
using maximum data transfer rate with a 400
character burst.

Test of TX BCC and RX BCC using CRC-16
polynomial and using idle mode to get into
transparency.

Test of hard-wired character detection
(M7817 module not installed).

Test of TX BCC and RX BCC using polynomial represented by 177777 and using idle
mode to getinto transparency.

3-40

Function

Test No.

Test of TX BCC and RX BCC with all
polynomial representations between 000000
and 177777.

Test of MISC register bit 06 (POLY 16-23).

3.7.1.6 DZDQF-A-D Tests

Test function of SEQ bit 6 (CLEAR RX
ACTIVE).

Test function of SEQ bit 7 (RX/TX CLEAR
GO/SET DONE).

Test function of SEQ bit 8 (RX CHAR
STRIP).

Test function of SEQ bit 10 (TX PAD).

Test function of SEQ bit 11 (RX BCC
EXCLUDE).

Test of transmitter transparent text mode.

Verify that the transmitter exits the transparent mode via EXIT T after it has entered
transparency via ENTER T.

Verify that the RX STRIP SYNC function is
inhibited in the transparent mode.

Verify that the RX CHAR STRIP function
(SEQ bit 8) strips characters from core but
not from the BCC.

Function

Test No.
(Octal)

Function

(Octal)

Start-up
Exercises RX and TX interrupts, VRC and
ENTER T /EXIT T if M7816 module is
installed.

Verify that every character from 0-377 can
be detected in character detect address 00.

Verify
that
every character from
400-177400 can be detected in character
detect address 00.

5-24

Verify that character 255 can be detected in
each of the 16 character detect addresses.

Test function of SEQ bit 1 (SET RX/TX
TRANSPARENT MODE).

Test function of SEQ bit 2 (CLEAR RX
TRANSPARENT MODE).

41-43

Test function of SEQ bits 4 and 5 (RX/TX
BCC TEST/APPEND) for 1, 2 and 3 BCCs.

Test function of SEQ bit 3 (CLEAR/START
TX/RXBCC).

Multiple function tests.

3-41

CHAPTER 4
DETAILED DESCRIPTION
4.1 INTRODUCTION
This chapter provides a detailed description of the DQll
logic. It is divided into six major sections which represent
the six DQ II modules.
Module
M7818

Title
Hard-Wired Character Detect and
NPR Control

M781S

Data Set Control

4.3

M7812

Bus Selectors Control/Status
Registers and Shift Registers

4.4

M7813

Character Count Registers, Bus
Address Registers and Shift
Register Control

4.S

M7816

AB Selectors and BCC Control

4.6

M7817

Character Detection and
Sequence Control

4.7

4.2.2 Hard-Wired Character Detection Logic
4.2.2.1 Functional Description - A Simplified block
diagram of the hard-wired character detection logic is
shown in Figure 4-1. The character to be detected is set
into the bit switches of the detectors and the associated
enabling switches are closed. Switch SW39 allows a sync
character to be detected. (The specific rules for setting the
switches are discussed in a subsequent paragraph.) When the
received character, as represented by the output of the
received data buffer register (D4-S RDOH-ISH), matches
the switch selected character, a high is sent to the D input
of the associated flip-flop. If the receiver is framed (DS-7
RX ACTNE (1) H is true), the end of a character is
detected (DS-7 TEST JUMPER MATCH L is true), the
transparent mode is not enabled (D9-6 DIS RX TRANSFER PULSE L is false), and switch SW40 is ON, the
flip-flop is clocked. The output of the flip-flop generates a
signal (D6-1 CD 8H, 9H, 10H or II H) at the associated
output gate that represents bit 8, 9, 10, or 11 of the
receiver control and status register. The signal that clocks
the flip-flop is also sent to the pulse stretcher to increase its
period. This signal becomes D6-11 ~ CHAR INTR L at the
associated output gate and is sent to bit IS of the RX CSR
as a prerequisite for generating an interrupt. The output
gates are enabled when Signal D8-6 BB IT L is false. This
interlock signal is false as long as the M7817 module, which
contains the programmable character detection logic, is not
plugged in.

Paragraph
4.2

Further division within modules is by functionally separate
logic circuits. The discussion of each circuit consists of a
functional description related to a block diagram and a
detailed description related to the circuit schematic that
appears in the DQll print set which is supplied as a
separately bound volume. The revision level of the circuit
schematic at the time that the description was written is
also included. Additional illustrations are used in the
detailed descriptions to supplement the text.

Selector Switches
Manually operated switches are used to select up to three
16-bit characters that set flags in the receiver control and
status register (RX CSR). Each character uses two dual
in -line switch packages containing eight switches each
(Figure 4-2). For example, character 0 uses packages SI and
S4. Package SI contains switches SWl-SW8 that correspond to bits 0-7 (low byte) of character O. Package S4
contains switches SW2S-SW32 that correspond to bits
8-1S (high byte) of character O. Switches SW33 and SW38
of package SS are used to enable the low and high bytes of
character 0 in the character detection logic. Switch SW39 in
package SS allows a detected sync character to be enabled.

4.2 M7818 MODULE (HARD-WIRED CHARACTER
DETECT AND NPR CONTROL)
4.2.1 Introduction
The M7818 module is a double height, extended length,
module that contains two functionally separate logic
circuits - hard-wired character detection logic and NPR
control logic.

4-1

RD 0H

I
CHAR "
LOW BYTE

CHAR 0 L
ENABLE

SW3~~__________~________~

I CHT~R

SWITCHES
AND

RD 7 H

DECODERS

•

TO
CHAR 2

QUAD
FLIP
FLOP

C08H
CD 9 H

OUTPUT
GATES

~ CD 11 H

•

~ 1- CHAR
INTR L

RX ACTIVE
(1) H

I
I
I

CHAR"
HIGH BYTE

S_
W3J

I
I

CHAR ¢ H
ENABLE

SWITCHES
AND
DECODERS

I
RD 15H

BBiT L

SW4f!

~ 0 ......0 ......
~ SW39
-

RX SV:: : : :

PULSE

.... -o-........---i... STRETCHER!-INTR
(ONE-SHOT)
ENABLE

CONTROL
LOGIC

SYNC

~ CD 10 H

CLK

CLR
RD 8 H

LOIS RX TRANSFER PULSE L

TEST JUMPER
MATCH L

11-2554

Figure 4-1 Block Diagram of Hard Wired Character Detection Logic

.a..

Handle end
of module
S5
INTR
SYNC

2nd row
of ICs

../'y-

~L----,-1'v-1
E22
REF

2 HIGH
1 HIGH

EN
EN

o HIGH

OFF
57
CHAR 2H
15

I
I

SW48

I
I
I

I
SW49

OFF

SW24

5W41

I
I
I
I

SWI6
I

OFF

-R52--

OFF

51
CHAR 9"L
SW8
I
I

7
6

I
I

5W1

SW25

52
CHAR 1 L

53
CHAR 2L

I
I

~~~

I
I
I

-R64-

SW32

54
CHAR 9"H

56
CHAR 1 H

5W56

BYTE ENABLES

! ~~: ~~ y~ll~~~ i~ i5-~-1V-l_ AvI

../'y-

EN
EN

SWI7

--R37--

OFF

SW9

---R27--

OFF

--R17--

OFF

--R8--

NOTES:
1. S=component designation
2. SW= switch designation.
11- 2560

Figure 4-2 Physical Layout of Character Detection Switches
4-2

Switch SW40 in package S5 allows any detected character
or sync character to set a flag and generate an interrupt if
other prerequisites have been satisfied. Table 4-1 lists the
switches and their functions.

For characters from 9-16 bits in length, use bit
selections for both high and low bytes. Justify
character to the least significant bit. All unused
bits must be set to O. Use enabling switches for
both high and low bytes.

Three separate characters can be selected. If less
than three are required, repeat a used character
until all three selections are used. For example,
if only two characters are desired, one of them
must be duplicated for the third selection. If
only one character is desired, all three
selections must be identical.

The following rules must be used when setting the switches.
1.

For character detect switches, a 1 is detected
with the switch OFF and a 0 is detected with
the switch ON. These levels are with respect to
the input of the character detection logic.

For characters of 8 bits or less, use bit
selections for high byte (bits 8-15). Justify
character to the least significant bit. All unused
bits must be set to O. Use enabling switch for
high byte.

Table 4-1
Function of Character Detection Switches
Package Number

Switch Number

Function

SI
S2
S3

SW1-SW8
SW9-SWI6
SWI7-SW24
SW25-SW32
SW41-SW48
SW49-SW56
SW33-SW40

Determines low byte of character 0
Determines low byte of character 1
Determines low byte of character 2
Determines high byte of character 0
Determines high byte of character 1
Determines high byte of character 2
SW33 enables high byte of character 0
SW34 enables high byte of character 1
SW35 enables high byte of character 2
SW36 enables low byte of character 2
SW37 enables low byte of character 1
SW38 enables low byte of character 0
SW39 enables a sync compare
SW40 allows character 0, 1, 2 or sync to set a flag and generate an interrupt

S6
S7
S5

Notes:

1. For S1, S2, S3, S4, S6 and S7, a 1 is detected with switch OFF and a 0 is detected with switch ON.
2. For S5, selected function is enabled with switch ON.

4-3

Two typical examples are shown below:
Example 1: It is desired to detect a single 6-bit character 110111 (LSB).
According to the rules, the character must be justified to the least significant bit of the high byte with unused bits set to 0
and all three selections (character 0, 1 and 2) must be identical. The corresponding high byte enabling switches must be set to
the ON position. The format is shown for character 0 and is applicable for" characters 1 and 2 also. The low bytes of
characters 0, I and 2 are not used and their respective enabling switches must be set to the OFF position.

ON ON OFF

OFF

ON OFF

OFF

Switch position

Character 0 H

Switch number

(Package S4)

I0 I 0 I 1

I Binary value

Bit position

31
14

30
13

LSB

Character I H (S6) and character 2 H (S7) are set up the same as that shown for character 0 H (S4). The enabling switches
(SW33, SW34 and SW35) for these three packages are set to the ON position. The interrupt enabling switch (SW40) must be
set to the ON position.

Example 2: It is desired to detect an 8-bit character 10001010 (LSB) for character 0 and a 12-bit character 110000101100
(LSB) for character 1.
The 8-bit character must be justified to the least significant bit of the high byte for character 0 as shown below:

Character 0 H
(Package S4)

OFF

ON ON ON OFF

ON OFF

Switch position

Switch number

Binary number

Bit position

I1
15

I13 I12o I 11
14

26
9

LSB

The enabling switch (SW33) for character 0 H is set to the ON position. The corresponding low byte (character 0 L) is not
used and its enabling switch (SW38) can be set to the ON or OFF position.

4-4

The 12-bit character must be justified to the least significant bit of the low byte for character I. The four least significant bits
of the high byte for character I are also used as shown below:

Character 1 L

Character 1 H

(package S2)

(Package S6)

ON ON ON ON OFF
1

1 0

1 0 1

ON OFF

OFF

ON ON

I 60

I 31

OFF

ON ON ON ON OFF

I 08

I 00

Switch position
Switch number
Binary number
Bit position

Each character is arranged in two 8-bit bytes. The outputs
of the 8 comparators in each byte are connected together
to provide a single output. Each byte can be connected to
the detection control logic by an enabling switch.

The enabling switches (SW34 and SW37) for characters I H
and I L must be set to the ON position. Characters 2 Hand
2 L must be set identically to characters I H and I Land
their associated enabling switches (SW35 and SW36) must
be set to the ON position.

Using character 2 as an example (Figure 4-3), switch SW36
connects the low byte to E23 pin 9 and switch SW35
connects the high byte to the same pin. If a 9-16-bit
character is selected, both switches (SW35 and SW36) are
closed. For each character, the common output of all 16
8242s is connected to +5 V through a pull-up resistor. This
output also goes to an input of E23 which is a 4-input NOR
gate. A high signal on this line indicates a match. The 8242
has a bare collector which facilitates multiple bit comparisons. The output of the 8242 is taken from the
collector and the emitter of this output transistor and is
connected to ground in the IC package (Figure 4-4). When a
match is made, all 8242 output transistors are turned off
and there is no path to ground for the +5 V; therefore, the
output to E23 is held high. When a match is not made, at
least one 8242 output transistor is turned on and the +5 V
is dropped to ground; therefore, the output to E23 is held
low. If only one character is set up for detection and the
other two are not set up identically, two undesirable
possibilities arise. First, if the two non-desired characters
have their enabling switches closed, an erroneous detection
is made if a received character matches the one randomly
set in either of the non-desired characters. Second, if either
non-desired character has its enabling switches open, a high
signal is always present on the associated output line which
falsely indicates a match.

The interrupt enabling switch (SW40) must be set to the
ON position. In this example, the 8-bit character can be
duplicated rather than the 12-bit character.

4.2.2.2 Detailed Logic Description - The circuit
schematic for the hard-wired character detection circuit is
contained in drawing D-CS-M7818-O-1 (Rev C) sheet 3
which is designated D6-1.

Comparator Logic
The bit selector switches are used to define a character that
is compared to the output of the received data buffer
register (D4-5 RD 0 H-15 H). The comparison is on a bit
basis, using 16 exclusive-NOR gates (type 8242) whose
outputs are wire-ORed to provide a high signal when a
successful comparison has been made. Figure 4-3 shows
four bits for character 2. The truth table for the 8242
shows that when both inputs are high or low, the output is
high.

Assume that it is desired to detect a I on bit 14 and a 0 on
bit IS. Switch SW55 for bit 14 should be open (OFF). The
+5 V via R63 puts a high (logical I) on pin I of E20. The
comparison is made when D4-5 RDI4 H is high. Switch
SW56 for bit IS should be closed (ON). The +5 V is
dropped to ground through the switch and puts a low
(logical 0) on pin 5 of E20. The comparison is made when
D4-5 RDI5 H is low.

Control Logic
Figure 4-5 shows the control logic. The outputs of the three
character comparators and the sync character comparator
are sent to the D inputs of quad flip-flop E18. They are also
sent to 4-input NOR gate E23.

4-5

8242 EXCLUSIVE-NOR
Truth Table

l sw38
.\

A
L
L
H
H

+5V

L
H
L
H

L
L
H

R43

R44

SW34

SW35

F rom sync character
detection circuit

To 6 identical
comparators for
char 2 high byte
11-2555

Figure 4-3 Typical Comparator Circuit
Signal D9-6 DIS RX TRANSFER PULSE L is high when
the transparent mode is not enabled. This Signal is inverted
by E22 and sent to pin 5 of E23. When all four inputs of
E23 are low, its output (pin 6) goes high. This positive
transition clocks all four flip-flops in the E18 package. The
o output of each flip-flop is sent to one input of a 2-input
NAND gate (EI9). These gates are shown as iogicaUy
equivalent, negated-input OR gates; they are enabled when
D8-6 BB IT L is high. This occurs when the programmable
character detection option is not installed (module M7817
not installed). When this module is installed, interlock
circuit D8-6 BB IT L is asserted and the hard-wired
character detection logic is inhibited. If a character is
detected, the 0 output of the associated flip-flop is inverted
by the output gate to generate 06-1 CD X H, where X is 8
for character 0, 9 for character 1, 10 for character 2, and
11 for sync character. These Signals (D6-1 CD 8 H, 9 H, 10
H, and 11 H) are bits 8,9,10, and 11 of the RX CSR and
are sent to the bus selection multiplexers on the M7812
module. Another qualifying signal (05-7 RX ACTIVE (1)
H) is sent to the clear input (pin 1) of EI8. If the receiver is
not framed, this signal is low and all four flip-flops in E18
are directly cleared which prevents the character detection
flags from being asserted.

The sync character comparator consists of switch SW39 and
two 2-input NOR gates (E22). When it is desired to detect a
sync character, SW39 is closed (ON position). The +5 V, via
R38, is connected to ground through the switch and holds
input pin 12 of the E22 low. If a sync character is
recognized, signal D4-7 RX SYNC OET H is true. It is
inverted by E22 pins 8 and 10 and is sent as a low signal to
the other in put (pin 11) of E22. The output (pin 13) of this
gate goes high and is sent to E23 and quad flip-flop E18.

If it is desired to set a flag in the Receiver Control and
Status Register (RX CSR) as the result of a detected
character, switch SW40 is closed. Any high at the input of
E23 represents a detected character and drives the output
(pin 8) of E2310w. This signal passes through SW40 to pins
2 and 4 of E23. Two other conditions must be satisfied to
qualify this gate. The first condition is that the receiver
must be framed. The end of a character frame is indicated
when 05-7 TEST JUMPER MATCH L goes low. This signal
is sent to pin 1 of E23. The second condition requires
verification that transmission is not in the transparent mode
because character detection is not applicable in this mode.

4-6

The NPR control logic serves the same purpose as the M796
Unibus Master Control Module. In response to a signal from
the M7821 Interrupt Module, the NPR control logic allows
the DQ 11 to become bus master and perform a DATI or
DATO operation on the PDP-II memory. The EQll takes
a character from memory (DATI) for transmission or it
sends a received character to memory (DATO) for storage.

+5V
SW55 open.
+5V via R63
puts logical1
on E10 pin 1

R42

SW35
~4n__-r-+____~TOE23

,
I

pin 9

Last stage
transistor is
on. +5V goes
to ground.
Output of E1~
is logical 0
(no match >.

The sequence of operation is described below.
1.

When either a transmit operation or a receive
operation desires a character transfer, an NonProcessor Request (NPR) is initiated.

The bus address control logic on the M7813
module generates RX CYCLE H which is high if
it is a receive operation and is low if it is a
transmit operation. The basic function of signal
RX CYCLE H is to generate the Transmitter
Buffer Register Load signal (LD TX BUF (1)
H), if it is a transmit operation.

Also, the bus address control logic generates
NPR RQ Hand NPR EN (1) H which are sent
to the M7821 Interrupt Module to assert BUS
NPRL.

If BUS SACK L is clear on the Unibus, the
processor asserts grant signal BUS NPG IN H.
At the M7821, this Signal clears BUS NPG OUT
H which stops the bus request at this device
(DQl1). It also asserts BUS SACK L and clears
bus request signal BUS NPR L.

The processor receives BUS SACK L and drops
grant Signal BUS NPG IN H. When the current
bus master completes a data transfer, it clears
BUS BBSY L. Signals BUS MSYN L and BUS
SSYN L are also cleared. Under these conditions, the M7821 asserts BUS BBSY L indicating that the DQII is now bus master.

Simultaneously with the assertion of BUS
BBSY L, the M782I asserts MASTER A L
which is sent to the NPR control logic to
initiate a DATI or DATO bus transaction.

The selection of a DATI or DATO operation is
made by selecting the state of Unibus control
lines CI and CO. The selection is performed in
the M78I3 bus address control logic.

Bit 14 set to detect logical1.Shown as no match.

SW55 apen
+5V via R63
puts logical 1
on E1'1J pin 1

+5V
R42

1/
TO E23
9

-~-----"pin

Bit 14 set to detect logical 1. Shown as a match.

Last stage
transistor is
off. Path to
ground is
incomplete.
Output of E10
is logical 1
(match).
11-2556

Figure 4-4 Operation of 8242 Comparator

The positive-going edge from E23 pin 6 that clocks E18
also triggers one-shot E4 that generates a positive pulse of
approximately 500 ns. This pulse is inverted by output gate
E15 to assert D6-1 1 ~ CHAR INTR L. This low pulse is
applied to the direct-preset input of the flip-flop that
represents bit 15 (CHAR INTR) of the RX CSR (M7812
module print D4-4). This bit and RX CSR bit 4 (CHAR IE)
must be set if the detected character is to produce an
interrupt. One-shot E4 is used to provide a long enough
pulse to prevent any Unibus read/write cycle from changing
the state of RX CSR bit 15 during the period required to
qualify the interrupt control logic.
4.2.3 NPR Control Logic
4.2.3.1 Functional Description - A simplified block diagram of the NPR logic and associated logic is shown in
Figure 4-6. The associated logic is discussed briefly because
it is not possible to describe the NPR adequately without
mentioning its interrelation with other logic concerned with
the NPR cycle.

Transmit operation requires DATI (Cl =0, CO=O)
Receive operation reauires DATO (C 1=1. co=(n
4-7

74175
E18
13

+5V

R3(1)
14
R3(0)

R2(1)
11
R2(0)

06-1

CO 9 H

RW)
6
RHO)

06-1

CO 10 H

ROm
3
RO(O)

06-1

CD 11 H

CLR

CLK

06-1 CO 8 H

Character
Detect Flags
C08-11 sent to
M7812 module
to be read by
program.
They are
bits 8-11 af
RX CRS.

06-1 1 - CHAR INTR L
9

L 05-7

Connected to
ground on M7817
module. With M7817
installed, hord-w ired
character detection
Is disabled.

RX ACTIVE (1) H
F rom CHAR 2 com p a rator -----4~+-_+_-t--:;';M
From CHAR 1 comparator-----_+_-t-~
From CHARO comparator------+--t-~

E4
500ns

SW39
S5

11
+3V

04-7 RX SYNC OET H

09-6 EN RX TRANSFER PULSE H

-..-:....a
11-2~92

05-7 TEST

Figure 4-5 Character Detect Control Logic

<:~-----r----------------~~------~-~-,B_-us-_-l--------~l------~:>
NPR EN (1) H
NPR RQ H

~Memory

CONTROL

INV

Address

~
BU,S C1 L
I
~~I-------------~

BUS

SSYN L

~ _ _ _ _ _ _ _ ~~I:'M~D~L:"_J

r ---- - ---,

END NPR CYCLE (1) L
BSSYN H
RX CYCLE H
MASTER A L

NPR
CONTROL
LOGIC

BUS MSYN L
LD TX BUF (1) H

'rr:
u.

r-------------------~

TIME OUT (1) H
M7BIB MODULE
M7B21
INTR
MODULE

TX BUFFER
REGISTER

I
1

REG/ERR
REGISTER

LMJ.!!I~ ~OE~L~ ...I
11-2557

Figure 4-6 Block Diagram of NPR Control and Associated Logic

4-8

Signal MASTER A L is also sent to the M7813
bus address logic to place the selected memory
address on the Unibus address lines.

Approximately 150 ns after MASTER A L is
asserted, the NPR control logic asserts BUS
MSYNL.

10.

The PDP-II memory has already decoded the
address and when it receives BUS MSYN L, it
places the character on the Unibus data lines
(DATI) or accepts the character from the
Unibus data lines (DATa) and after a short
delay, asserts BUS SSYN L.

11.

12.

Normal Operational Sequence
The normal sequence describes how the logic performs
during an NPR cycle that terminates normally.
1.

Prior to starting the operation, D3-1 MASTER
A L is not asserted. This produces a low at E3
pin 1 that directly clears the following elements.
MSYN flip-flop
END CYCLE flip-flop
BUF flip-flop
TIME OUT flip-flop
MSYN TIMER one-shot

The M7813 bus address control logic receives
BUS SSYN L and sends it to the NPR control
logic as B SSYN H to start the sequence that
terminates the NPR cycle.

As a result, the following conditions exist.

The low from the 1 output (pin 9) of the
MSYN flip-flop is sent to three places:

At about the same time, the NPR control logic
drives signal LD TX BUF (1) H high to load the
transmitter buffer register, if a transmit
operation requested the NPR.

(1)

The D-input of the END CYCLE
flip-flop

(2)

The D-input of the TIME OUT
flip-flop

13.

After receiving B SSYN H, the NPR control
logic clears BUS MSYN L.

(3)

The input (pin 2) of the MSYN
TIMER one-shot

14.

When the memory receives the cleared BUS
MSYN L signal, it clears BUS SSYN L.

15.

The NPR control logic continues the termination sequence by asserting END NPR CYCLE
(l) L which is sent to the M7813 bus address
control logic. This signal clears NPR EN (l) H
which inhibits the issuing of another NPR until
NPR EN (1) H is asserted again.

If the DQll addresses non-existent memory, BUS SSYN L
is not asserted by the memory. If BUS SSYN L is not
asserted 20 IlS after BUS MSYN L is asserted, the NPR
control logic terminates the NPR request normally. Normal
termination of the NPR cycle, even though the DATI or
DATa was not completed, is a requirement because
aborting an NPR cycle is not allowed.

4.2.3.2 Detailed Logic Description - The circuit schematic for the NPR control logic is shown in drawing
D-CS-M7818-O-1 (Rev C) sheet 4, which is deSignated D6-2.
Figure 4-7 shows a simplified logic and timing diagram for
the NPR control logic.

4-9

The high from the 0 output (pin 8) of the
END CYCLE flip-flop is sent to two
places:
(1)

The input (pin 10) of one-shot E12
that generates 06-2 END NPR
CYCLE (l) L. At this time, E12 is
at rest so D6-2 END NPR CYCLE
(1) L is not true.

(2)

The input (pin 9) of the CK2
one-shot which inhibits its operation.

Assume that a transmit operation requested the
NPR transaction. The BA control logic on
module M7813 drives DS-3 RX CYCLE H low.
This signal, via the three E3 NOR gates, puts a
low on the K input of the MSYN flip-flop and a
low on the input of the BUF flip-flop.

The MSYN TIMER one-shot is at rest and the
low from its 1 output (pin 13), via gate E22,
puts a high on the J input of the MSYN
flip-flop.

9,..
10

t---;2
~

74123
75 NS
E8
CK2
~S
r- 12
t----

Y'1

+3
03-1 MASTER A L

-=-0

lrc

7402
E3

~- ..)

fo-

74123
E4
START

CI!:

1 ,..

~ 13

'"'

) 7402
E3
6
---1

E8
CK1

CI!: 75NS

7402
E3

n. 8

o~
8

~ 13

Sf' 74HI03
E7
MSYN

--'~ 10
0

p..!-

;-c

74HI03
E7
MSYN

12 ".

\11

93
+3V

J
1
74HI03
E7
1~
LOTX
aUF
~ 12

"'"

8881
E15

8881
EI5

3
+3V- K
) 7402
E22

CD
8U S MSYN L

CD
05-4 8SSYN H

06- 2 END NPR CYCLE (1) L

+3V

11 ~

7402
E3

I----

74123 '- 12
~
E12
~75NS
END
NPR
S
CYCLE

Pii-

~@
o
8

0 13

(;J6

9.r

-r-

./ 74123 ..r---

+3V

05-3 RX CYCLE H

9
J

"" 75NS
~

06 -2 LO TX 8UF (1) L

0 ...... 13

t---'-"-

y2
6

8881
EI5

.AAA

+5V

..)

74123
EI2
MSYM
TIMER
20'"

+!V
4
2

S
1

0
100..

7474
Ell
TIME
OUT

y1
Figure 4-7 NPR Control Logic and Timing Diagram

4-10

p-L
~

6
0 t----

06 - 2 TIME OUT (1) H

When the M7821 Interrupt Module receives an
NPR signal from the processor, it asserts D3-1
MASTER A L. This drives the E3 pin 1 high
and the positive transition triggers the START
one-shot.

The START one-shot generates a 75 ns negative
pulse from its 0 output (pin 4) that is sent to
the input (pin 2) of the CKI one-shot.

The CKI one-shot generates positive and
negative pulses approximately 75 ns each. The
negative pulse from pin 4 goes to the input (pin
10) of the CK2 one-shot. It does not trigger
CK2 because the other input (pin 9) is inhibited
by a high from the END CYCLE flip-flop.
The positive pulse from pin 13 of the CKI
one-shot goes to the clock input of the MSYN
and END CYCLE flip-flops. The END CYCLE
is not clocked because it is in the cleared state
and its D input is low. The negative-going
trailing edge of the pulse clocks the MSYN
flip-flop and sets it because its J input is high
and its K input is low.

BUS SSYN L is sent to the M7813 module,
inverted and sent to E15 pin 9 as D5-4 B SSYN
H. The other input (pin 8) of this NAND gate is
also high so its output goes low. This low signal
directly sets the END CYCLE flip-flop via its
preset input (pin 10). The low transition on the
o output (pin 8) does not trigger one-shot E12
but it does trigger the CK2 one-shot.

10.

When the 75 ns positive pulse from the CK2
one-shot times out, it triggers the CKI one-shot
and clocks the BUF flip-flop which toggles it to
the set state. This drives D6-2 LD TX BUF (0)
L high which is sent to the M7812 module to
clock the character to be transmitted into the
transmitter buffer register. The high from the 1
output (pin 12) of the BUF flip-flop, via two
E3 gates, puts a high on the K input of the
MSYN flip-flop. With the K input high and the
J input low, the next negative transition of the
clock pulse clears the flip-flop.

11.

When the 75 ns positive pulse from the CKI
one-shot times out, it clears the MSYN flip-flop
...t..:~t.. _~~+~~~" +t..~ +~l1~ .. ":~n n~+:~~

Wlll"'ll l''''IIVIHl.> UJ.'" J.VUVW.lH5 a",UVH.

Setting the MSYN flip-flop produces the
following action.

Puts a low on the D input of the END
CYCLE flip-flop.

Signal BUS MSYN L is asserted via bus
driver E13 pin 13.

Clears signal BUS MSYN L.

c.
b.

The D input of the END CYCLE flip-flop
goes high.

Puts a low on the D input of the TIME
OUT flip-flop. This prevents D6-2 TIME
OUT (1) H from being asserted when the
MSYN TIMER one-shot times out.

The J input of the BUF flip-flop goes
high via E3 pin 13.

Inhibits retriggering of the MSYN TIMER
one-shot until another low-to-high
transition occurs at the MSYN flip-flop 1
output.

Puts a low on the D input of the BUF
flip-flop via E3 pin 13.

Input pins 11, 12, 8 and 5 of the three
E15 bus drivers all go high.

The MSYN TIMER one-shot is triggered
and it generates positive and negative
pulses of 20 p.s each. The positive pulse
from pin 13 is inverted by E22 and puts a
low on the J input of the MSYN flip-flop
which conditions it to be cleared at the
proper time.

12.

The DQ 11 is bus master and is in the process of
performing a DATI transaction to obtain a
character from memory. Shortly after receiving
BUS MSYN L, the memory asserts BUS SSYN
L.

4-11

When the 75 ns negative pulse from the CKI
one-shot times out, it triggers the CK2 one-shot
again. When the 75 ns positive pulse from the
CK2 one-shot times out, it triggers the CKI
one-shot again and clocks the BUF flip-flop
which clears it. Clearing the BUF flip-flop
drives D6-2 LD TX BUF (1) H low again and,
via two E3 gates, puts a low on the K input of
the MSYN flip-flop.

13.

14.

The leading edge of the positive pulse from the
CKI one-shot clocks the END CYCLE flip-flop
and clears it. The positive transition at the 0
output (pin 8) of this flip-flop triggers one-shot
EI2 which generates 06-2 END NPR CYCLE
(1) L. This 75 ns pulse goes to the BA control
logic on the M7813 iogic and then to the
M7821 Interrupt Module to clear 03-1
MASTER A L which inhibits further triggering
of the CKI and CK2 one-shots. It also clears
the MSYN TIMER one-shot.
Clearing 03-1 MASTER A L also clears the
MSYN TIMER one-shot. The NPR control logic
is now back in its initial state.

When the MSYN TIMER one-shot times out, its
I output (pin 13) goes low. This signal and the
high from the I output (pin 5) of the TIME
OUT flip-flop are ORed at E22 to keep a low
on the J input of the MSYN flip-flop to qualify
it (J = Land K = H) to be cleared on the next
dock pulse.

When D6-2 TIME OUT (1) H is asserted, it is
also sent to pin 6 of NAND gate EI5 and drives
the output (pin 4) of this gate low. This gate is
wire-ORed with the gate that accepts D5-4 B
SSYN H so the logic now sequences just as if
the memory had responded by asserting BUS
SSYN L.
From this point on, the NPR control logic
terminates the NPR transaction normally.

The above sequence assumes that a transmit operation
requested the NPR transaction. In this case, the BUF
flip-flop is set to generate the loading signal (06-2 LD TX
BUF (1) H) for the transmitter buffer register.

4.3 M781S MODULE (DATA SET CONTROL)
If a receive operation requested the NPR transaction, signal
05-3 RX CYCLE H is high. Via E3 pin 13, it keeps a low
on the J input of the BUF flip-flop which prevents it from
being set.

4.3.1 Introduction
The M7815 module is a single height, extended length,
module that contains logic to control and monitor certain
signals between the data set and the DQII.

Tennination Due to Addressing Non-Existent Memory
If the DQll addresses non-existent PDP-ll memory, BUS
SSYN L is not asserted because there is no response from
the memory. Aborting an NPR transaction is not allowed;
therefore, the NPR control logic must end the NPR
transaction normally even though the DQ II does not
complete its DATI or DATO operation.

4.3.2 Functional Description
A simplified block diagram of the data set control logic is
shown in Figure 4-8.
Three signals from the data set are sent to this
logic: Carrier Detector (CO), Oear to Send (CS), and Ring
Indicator (RING). Each of these signals is sent to a one-shot
that generates a pulse when a positive or negative level
transition of the input signal is detected. The outputs of the
one-shots associated with these signals plus the output of an
unassigned one-shot are sent to the DS INTR selection
logic. This allows any active one-shot to set the Data Set
Interrupt (DATA SET INTR) flip-flop. If the program has
set the Data Set Interrupt Enable (DATA SET IE) flip-flop,
signal OS INTR L is generated when the OAT A SET INTR
flip-flop is set. Signal DS INTR L is sent to the interrupt
and vector control logic on the M7813 module to initiate a
bus request (BR). Signal DATA SET INTR (1) H represents
the state of the OAT A SET INTR flip-flop and can be read
by the program. Assertion of TEST LOOP H, during on-line
testing, prevents the CO, SC, RING and SPARE one-shots
from setting the DATA SET INTR flip-flop which prevents
the generation of interrupts.

Assume that the operation has progressed normally to the
point at which the MSYN flip-flop has been set and the
NPR control logic is waiting for the memory to assert BUS
SSYN. Assume further that the memory does not respond
by asserting BUS SSYN L. The operation continues as
follows.
I.

If BUS SSYN L is not asserted 20 /lS after BUS
MSYN L is asserted, the MSYN TIMER oneshot times out. The trailing edge of the negative
pulse from this one-shot (pin 4) clocks the
TIME OUT flip-flop and sets it which asserts
D6-2 TIME OUT (1) H. This Signal is sent to
the REG/ERR register in the M7812 module to
set either bit 4 or 5 which indicates that
non-existent memory has been addressed.

4-12

•

TEST LOOP H

---.

015 H----.

---.... C

INTR

D4H- r---- 0

DATA

OS INTR
SELECTION
LOGIC

LD TX 7-flJ H-

CO H

.....

CS HI.....

CARRIER
DETECT
CLEAR
TO SEND

RING H1---

RING

.....

SPARE

USER
OPTION

SPARE:

UO
'

014 H-

r---. C SET IE

r--...- 0

.....

013 HLD RX 15-18 H

08 H-

DATA SET
INTR (1) H

o DATA SET

•

OUTPUT
GATING

DATA SET
IE (1) H

P
UO
14

~~
:j~

W1
UO 14 (1) H

•

P
UO
13

f---+ OS INTR L

UO 13 (1) H

-..:t OUTPUT
GATING

REQ TO
SEND H
RS (1) H
DATA TERM

09 H- ~ 0

USER
..... OPTION

DTR
C

OUTPUT
GATING

f---+ ROY H

f---+ DTR (1) H

One Shots
OUT HIGH H .......

INPUT
GATING

TEST LOOP H

SEL2H-.
11-2558

Figure 4-8 Block Diagram of Data Set Control Logic

Signals DTR (1) Hand RS (1) H represent the state of the
associated flip-flops and can be read by the program. Signal
TEST LOOP H, when asserted during on-line testing,
inhibits the generation of DTR and DS.

Two additional User Option (UO) flip-flops are available
that can be used to generate signal DS INTR L. They are
U014 and U013 and are set by associated one-shots. The
state of these two flip-flops and the DATA SET IE flip-flop
can be read by the program. Jumpers WI and W2 allow the
UO flip-flops to generate interrupts. Removing the jumpers
allows the flip-flops to be used only as flags.

4.3.3 Detailed Logic Description
The circuit schematic for the data set control logic is
contained in drawing D-CS-M78 15-0-1 , sheet 2 which is
designated D2-l. A simplified logic diagram is shown in
Figure 4-9.

The DATA SET IE flip-flop is set and cleared by the
program. The DATA SET INTR, U014, and U013 flipflops are set by the hardware and cleared by the program.
Through the program, this logic generates two control
signals to the data set: Data Terminal Ready (DTR) and
Request to Send (RS).

Six identical one-shots are used to allow signals from the
data set to generate interrupts or to set flags. A typical
one-shot is shown in Figure 4-10. The circuit consists of an
RC network, an input inverter and an output exclusive-OR
gate. It is triggered by a positive-going or negative-going
edge and produces a negative pulse of short duration
(approximately 500 ns).

Two flip-flops are used in the logic to generate RS. The
second flip-flop provides a delay to ensure that the Request
to Send signal is asserted on the positive-going edge of the
data terminal clock.

4-13

To clock
input of
OATAS&T
INTR flip flop
04-3 TEST LOOP (1) H

~
04-208 H _ _--1_.;.;12'-1

This line 9011
hiOh when
CO,CS,RING
or SPARE
one-shot
is tiooered

- - - - - - - - - - - - 02-1 DATA SET INTR(1) H
(TXCSR bitl5)

b-dE3">4..:... 02-1 REQUEST
TO SEND H

04-3 TX CLOCK H ---I-+------.---l......J

1O-<a::-n_8_ 02-1 DATA
+&V

TERM ROY H

04-2 09 H ---~~
02-1 OS I NTR L

+3V

+~V

from one-shot

02-1 OTR (1) ~i
(TX CSR bit 9)

02-·1 RS(1) H
CSR bit 8)

L......_ _ _ _ ( T>C

04-2 014 H

f'"

+5V

05-41NI H~3~ET>~4~6-_ _

from one-shot

To clear input of
DATA SET IE,
U013. U014 and
DATA SET INTR
flip flops

r-·+----·-----4-4------- 02-1 U013( 1) H

04-2 013 H

(RX CSR bit 13)
NOTE: All flip- flops ,are t,pe 7474.
Pins 4/10 are preset inputs.
Pins 1/13 are clear inputs.

04-4 LO RX 15-8 H

04-1 04 H -------~--..:~

r::-.t---,--------4~----- 02-1 DATA SET IE (1) H

(TX CSR bit4)

04 -4 LO TX 7 -0 H _ _ _ _ _ _ _-+-_...:3:...i

From
E3
pin 8

From
E7
pin 4

11-2591

Figure 4-9 Data Set Control Logic

The outputs of the CO, CS, RING, and unassigned
one-shots are sent to E8 which is a 4-input NAND gate
(shown as the logically equivalent negated-input OR gate).
Jumper W4 is installed in the input line to the RING
one-shot. If it is removed, RING interrupts are inhibited. A
triggered one-shot drives the output of E8 high and it is
sent to pin 4 of NAND gate E6. The other input (pin 5) is
also high during normal operation, so the output (pin 6) of
E6 is low. This Signal is sent to the preset input (pin 4) of
the DATA SET INTR flip-flop. A low on this input directly
sets the flip-flop. This signal can be inhibited by D4-3 TEST
LOOP (1) H which is inverted and sent to pin 5 of E6. This
signal comes from bit 3 of the Miscellaneous Register
(MISC CSR) on the M7812 module. When the program sets
this bit, the DQl1 operates in the on-line test mode and no
signals from the data set are allowed to set the DATASET
INTR flip-flop and subsequently cause an interrupt. This is
accomplished by asserting D4-3 TEST LOOP (1) H,
inverting it and sending the resulting low signal to pin 5 of
E6.

7486
Exclusive-OR

~
,~

TRUTH TABLE

T
Typical One-Shot Circuit

L
L

L
H

®
Delay

--I I-- -1 t-- Delay

When the DATA SET INTR flip-flop is set, its 0 output, via
gate E8, puts a high on pin 1 of NAND gate E6. The other
input (pin 2) of this gate is high only when the program has
set the DATA SET IE flip-flop: If both of these flip-flops
are set, D2-1 DS INTR L is asserted at E6 pin 3. This signal
is sent to the interrupt control logic on the M7813 module
(drawing D5-5). This logic generates the signals that start
the request for interrupt via the M7821 Interrupt Module.

u u

Timift9 Oiagram

11-2559

Figure 4-10 Typical One-Shot Circuit
and Timing Diagram

The DATASET INTR flip-flop is set by the hardware using
the preset input, and is cleared by the program using the D
input and clock signal (D3-1 OUT H) (D3-1 SEL 2 H). The
1 output of this flip-flop is D2-1 DATA SET INTR (1) H
which is bit 15 of the Transmitter CSR. The state of this bit
is read at bus selector bit 15 on the M7812 module
(drawing D4-2).

Referring to the circuit and timing diagram in Figure 4-10,
assume that input A is low. Points Band C are high so the
output (D) is high because the exclusive-OR, inputs (A and
C) are complementary. Assume now that input A goes high.
Point B goes low, but because of the delay caused by the
RC network, point C remains high. Output D goes low
because the exclusive-OR inputs (A and C) are the same
(both high).

The DAT A SET IE flip-flop is set and cleared by the
program using the D input and clock signal D44 LDTX 7-0
H. The 1 output of this flip-flop is D2-1 DATA SET IE (l)
H which is bit 4 of the Transmitter CSR. The state of this
bit is read at bus selector bit 4 on the M7812 module
(drawing D4-l).

After a delay of approximately 500 ns, point C goes low
and output D goes high again because the exclusive-OR
inputs are again complementary. The circuit is now stable
after generating a negative pulse of approximately 500 ns.
The use of an exclusive-OR gate for the output allows a
negative transition on the input to generate a negative pulse
also.

Both the DATA SET INTR and DATA SET IE flip-flops
are directly cleared by D54 INI H.

4-15

When RS is set, its 1 output is sent to the D input of the
RQ TO SEND flip-flop. The next positive transition of the
external clock (D4-3 TX'CLOCK H) sets the RQ TO SEND
flip-flop. The 1 output of this flip-flop is ANDed with the
inverse of D4-3 TEST LOOP (1) H at NAND gate E2. With
RQ TO SEND set and D4-3 TEST LOOP (1) H not asserted,
the output of E2 is low. This signal is inverted by E3 to
assert D2-1 REQUEST TO SEND H which is sent to the
data set.

Two unassigned one-shots are provided to allow the
presetting of two associated flip-flops, identified as User
Options 13 and 14 (UOI3 and UOI4).
They can be used to provide additional data set control or
to generate additional flags. The 1 outputs of these
flip-flops (D2-1 UO 13 (1) Hand D2-1 UO 14 (1) H) are bits
13 and 14 of the Receiver CSR. These bits are read at bus
selector bits 13 and 14 on the M7812 module (drawing
D4-2). Both flip-flops are set by the hardware using the
preset input, arld are cleared by the program using the D
input and clock signal D44 LD RX 15-8 H. The 0 outputs
of these flip-flops are sent to pins 1 and 2 of E8 via jumpers
W2 and WI respectively. With the jumpers in and DATA
SET IE set, D2-1 DS INTR L is asserted if either UO 13 or
U014 is set.

The RS, RQ TO SEND, and DTR flip-flops are directly
cleared by D54 INI H. This action can be inhibited by
removing jumper W3 at the output (pin 4) of inverter E7.

The 1 output of the DTR flip-flop is D2-1 DTR (1) H
which is bit 9 of the Transmitter CSR. The 1 output of the
DS flip-flop is D2-1 RS (1) H which is bit 8 of the
Transmitter CSR. These bits are read at bus selector bits 9
and 8 on the M7812 module (drawing D4-2).

The data set control logic also generates two control signals
that are sent to the data set: Request to Send (RS) which
conditions the local data communications equipment for
transmission, and Data Terminal Ready (DTR) which
controls switching of the data communications equipment
to the communications channel. Both signals are generated
by flip-flops that are program-controlled.

4.4 M7812 MODULE (BUS SELECTORS)
4.4.1 Introduction
The M7812 module is a hex height, extended length,
module that contains several functionally separate logic
circuits. They are listed below in the order of discussion.

To generate the DTR signal, the program puts a high on
Unibus data bit 9 that is picked up by a bus receiver on the
M7812 module and sent to the D input of the DTR
flip-flop as D4-2 D9 H. The program performs a DATOB on
the high byte of the Transmitter CSR which asserts D3-1
our HIGH Hand D3-1 SEL 2 H at the MI05 Address
Selector Module. These signals are ANDed at pins 9 and·lO
of NAND gate E2. The output of E2 goes low and is
inverted by E3. The positive-going edge of the output of E3
clocks the DTR flip-flop which sets it. The 1 output of the
DTR flip-flop is ANDed with the inverse of D4-3 TEST
LOOP (1) H at NAND gate E6. With DTR set and D4-3
TEST LOOP (1) H not asserted, the output of E6 is low.
This signal is inverted by E7 to assert D2-1 DATA TERM
RDY H which is sent to the data set.
It is a requirement that the RS signal must be asserted by
the positive-going edge of the data set clock. This requirement is met by using two flip-flops to generate the RS
signal. The program sets the RS flip-flop the same way it
sets the DTR flip-flop, except that bit 8 is used to
condition the D input of the RS flip-flop. Setting the RS
flip-flop is asynchronous with the external clock so it is not
allowed to directly generate the RS signal.

4-16

Bus Selectors and Control Logic

Miscellaneous (MIS C) Register and Internal
Clock

Transmitter Control and Status Register (TX
CSR)

Receiver Control and Status Register (RX CSR)

Sync Register (SYNC) and Transmitted Data
Output Logic

Transmitter Shift Register

Receiver Shift Register and Receiver Data
Register

The select and enabling signals are generated by the AA
selection decoding logic. The "AA" refers to the suffix for
the basic DQll option designation (DQll-AA). The
enabling signals turn on the multiplexers and the select
inputs choose the desired register which is a multiplexer
input. The RX CSR, TX CSR and REG/ERR registers are
selected as a function of the SEL a H, SEL 2 H, and SEL 4
H signals respectively, from the MI as Address Selector
Module. The Receiver Data Register is selected during a
receiver-initiated NPR cycle.

4.4.2 Bus Selectors and Control Logic

4.4.2.1 Functional Description - The outputs of the eight
registers used in the basic DQ 11 are multiplexed to the
Unibus data lines through one set of 16 bus drivers. This is
accomplished by using 32 4-line to I-line multiplexers. Two
multiplexers handle 1 bit of all 8 registers which are 16 bits
long; therefore, 32 multiplexers are required. Figure 4-11 is
a simplified block diagram of the arrangement. The
Receiver Control and Status Register (RX CSR) , Transmitter Control and Status Register (TX CSR), Register
Pointer/Error Register (REG/ERR), and the Receiver Data
Register are word- or byte-addressable. The Transmitter
Buffer Register (TX BUF), Miscellaneous Register (MISC),
SYNC Register and Character Count/Bus Address Register
(CC/BA REG) are word-addressable only. Refer to Chapter
3 for a detailed discussion of the bit assignments and
function of these registers.

The TX BUF, MISC, SYNC, and CC/BA registers are
secondary registers and are not selected directly by the
MIaS module. They are selected by bits 8-11 of the
REG/ERR register and SEL 6 H from the MiaS module.
Signal BA IT is an interlock signal that is asserted only
when the M781S Data Set Module is plugged in. It allows
the high byte of the TX CSR register to be read. This byte
(bits 8-15) represents data set functions that require
monitoring only when the M781 5 module is installed.

TX BUF REG
MISC REG
SYNC REG

BUS
B SELECTORS
BITS 00-15 ~------,
C (16 Multi plexers)

CC/BA REG
REG MUX B L
REG MUX A L - - - - - - - '
06REG-BUS L
RX CSR
TX CSR
REG/ERR CSR

BUS
B SELECTORS
16 Unibus
BITS 00-071-----..... Transceivers
C (8 Multi Bits
plexers)
D(15:¢¢)

Unibus
' - - - - -........ data to
internal
logic

RX DATA REG

RX CSR
TX CSR
REG/ERR CSR
RX DATA REG
SEL(012) MUX B L
SEL(0/4) MUX A L
CSR/RD -BUS 8-15 L
CSR/RD-BUS 0-7 L _ _ _ _ _ _ _ _----J
11-2651

Figure 4-11 Block Diagram of Bus Selection Logic

4-17

output of the exclusive-OR gate. The multiplexer output is
inverted by the bus driver before being placed on the
Unibus.

4.4.2.2 Detailed Logic Description - The circuit schematics for the bus selectors and selection logic are
contained in drawing D-CS-M7812-O-O (Rev D) sheets 2, 3
and 4 which are designated D4-1, D4-2 and D4-3.

Register Selection Logic
The register selection logic is shown in the left side of print
D4-3. Figure 4-13 also shows the register selection gates,
plus additional informative comments.

Bus Selectors
The bus selectors for bits 00-07 are shown on print D4-1;
the bus selectors for bits 08-15 are shown on print D4-2.
The multiplexers are arranged similarly on both prints;
namely, in two groups of two columns each. The 16
multiplexers in the left column of each group handle the
secondary registers as shown below.
Register
TXBUF
MISC
SYNC
CC/BA

The top half of the logic generates the select and enabling
signals for the primary registers. The RX CSR, TX CSR,
and PI/ERR registers are addressed directly and are
selected by the appropriate signal from the MI05 Address
Selector Module. These signals are D3-1 SEL 0 H, D3-1 SEL
2 H, and D3-1 SEL 4 H, respectively. They are decoded by
two NOR gates (EI5) to generate multiplexer select signals
D4-3 SEL (0/4) MUX A Land D4-3 SEL (0/2) MUX B L.
The state of these select signals determine which register is
to be read, as shown in the table in Figure 4-13. During the
DATI transaction that is used to read the selected register,
the MI05 module asserts D3-1 IN H. With this signal
asserted and the M7815 Data Set Control Module installed,
both multiplexer enabling signals (D4-3 CSR/RD ~ BUS
0-7 L at E16 pin 6 and D4-3 CSR/RD ~ BUS 15-8 L at
E17 pin 8) are generated when either D3-1 SEL 0 H, D3-1
SEL 2 H or D3-1 SEL 4 H is asserted. When the M7815
module is installed, it asserts D2-1 BA IT L which is a
ground level interlock signal that is sent to pin 10 of NAND
gate E16. It drives the output (pin 8) of E16 high and this
signal is a qualifying input to E 17 pin 9. If the M7815
module is not installed, D2-1 BA IT L is not asserted and
pin 10 of E16 is held high via the +5 V applied to Rl. If the
TX CSR register is addressed, D3-1 SEL 2 H is asserted and
sent to the other input (pin 9) of E16. This drives the
output of E16 low and prevents the assertion of D4-3
CSR/RD ~ BUS 15-8 L at E17 pin 8. This inhibits the
reading of the high byte of the TX CSR register when the
M7815 Data Set Module is not installed. This is a logical
action because the high byte contains data set signals that
are present only when the M7815 module is used.

MUX Input
A
B
C
D

The 16 multiplexers in the right column of each group
handle the primary registers as shown below.
Register
RXCSR
TXCSR
REG/ERR
RECDDATA

MUXInput
A
B
C
D

Figure 4-12 shows bit 00 of all eight registers. Multiplexer
E49 handles the secondary registers. It is enabled when
strobe input D4-3 06 REG ~ BUS L is low. Select inputs
D4-3 REG MUX BLand D4-3 REG MUX A L are decoded
to pick the desired input (A, B, C or D). Multiplexer E65
handles the primary registers. Its enabling signal is D4-3
CSR/RD ~ BUS 0-7 L and its select signals are D4-3 SEL
(0/2) MUX BLand D4-3 SEL (0/4) MUX A L. The
multiplexer truth table is shown in Figure 4-12. Both
multiplexer outputs are sent to exclusive-OR gate E56
which is used as a non-inverting gate to pass the selected
multiplexer output to Unibus driver E4. Because the
primary and secondary registers are not read simultaneously, the enabling input (STB1) to either E49 or E65 is
inhibited (high) while the other enabling input is asserted
(low). The output of the inhibited multiplexer is low which
holds one input of the exclusive-OR gate low. If the output
of the active multiplexer is low, the exclusive-OR inputs are
identical and its output is low. If the output of the active
multiplexer is high, the exclusive-OR inputs are complemented and its output is high. The bus driver (E4 pin 12) is
part of an 8838 quad transceiver. One input of the bus
driver is held high and the other input comes from the

The RECD DATA register is read during a receiver initiated
NPR cycle. During this time, none of the primary registers
are addressed so signals D3-1 SEL 0 H, D3-1 SEL 2 H, and
D3-1 SEL 4 H are not asserted. Both D4-3 SEL (0/4) MUX
A Land D4-3 SEL (0/2) MUX BLare high so the RECD
DATA register is selected. The CC/BA control logic on the
M7813 module asserts D5-3 RX NPR L. This signal, along
with D3-1 SEL 2 H which is not asserted, generates both
multiplexer enabling signals (D4-3 CSR/RD ~ BUS 0-7 L
and D4-3 CSR/RD ~ BUS 15-8 L) whether D2-1 BA IT L
is asserted or not.

4-18

04-5 TB 0 H
(TX BUF REG)

04-3 STEP CLK (1) H
(MISC REG)

04-7 SO (I) H
(SYNC REG)

05-1 CC/BA 0 H
(CC/BA REG)

AI
74153
E49
Bl
fl 9
Cl

x - OR gate used
as a non-inverting
output gate.

01
51
2

SO STB 1
14 15

r--------,

04-3 REG MUX B L

04-3 REG MUX A L

I
I

04-3 06 REG-BUS L

04-4 RX GO (1) H
(RX CSR)

04-4 TX GO (1) H
(TX CSR)

04-6 TX CLK LOSS (0 H
(REG/ERR CSR)

04-7 BRO 0 H
(RX DATA REG)

04-3 SEL (0/2) MUX B L
04-3 SEL (0/4) MUX A L

BUS DATA 00 L

I
I
r---J

74153
E65

f, 9

10104-1 DOH

I
I -=

E4
8838

L _ _ _ _ _ ~~~SCEI~~J

01
51

SO STBI

1415

04-3 CSR/BRO -BUS 7-0 L _ _ _ _ _ _----J

~___ }

10
11
12
13
6
5
4
3

STBI
AI

SEPARATE STROBE(ENABLE)
FOR EACH HALF

STBO

Cl
01

-----AO
BO
fO

DO
51

DATA INPUT
SELECTED

CONTROL
INPUT
STB

*
L

74153 DUAL 4- LINE TO I-LINE MULTIPLEXER

SO
14

SELECT INPUTS COMMON

L..-______ } TO BOTH HALVES

11-2655

Figure 4-12 One Bit Slice of Bus Selection Multiplexers

4-19

All these signals are used in the portion of the logic that
generates the multiplexer enabling signal D4-3 06
REG ~ BUS L at E17 pin 6. The multiplexer select signals
are generated by two dual-input NAND gates (E8) that
require only REG/ERR bits 8, 9, and 11 for decoding. To
verify the selection process, choose a secondary register in
the table in Figure 4-13 to obtain the state of the
REG/ERR bits and follow the signals through the logic.
The D input of the multiplexer can be anyone of eight
registers (four BA registers and four CC registers) which are
selected by the CC/BA control logic on the M7813 module.

03-1 SEL 4 H
03-1 SEL 0 H

03-1 SEL 2 H
MUX SiGNALS
S1 S0 OUTPUT
A
L
L
B
L
H
H
L
C

04-6 REG PT 8 H
04 -6 REG PT 11 H

PRiMARY
REGISTER
RX CSR
TX CSR
REG/ERR
RX DATA

...

~
12

04-3 REG MUX A L

4.4.3 Miscellaneous Register (MISC) and Internal Clock

4.4.3.1 Functional Description - This discussion, and the
detailed discussion that follows, cbvers the operation of the
Miscellaneous Register and its associated logic. A register
bit map and functional description of each bit is covered in
Chapter 3, Programming.
.

~~__ ~3 :~MUX B L

04-6REGPT9H~

••

MUX SIGNALS
S1 S0 OUTPUT
A
L
L
B
L
H
H
C
L
H
H
0

SECONDARY
REGISTER
TX BUF
MISC
SYNC
CC/BA

A simplified block diagram of the Miscellaneous Register
and internal clock is shown in Figure 4-14. The register and
clock are shown together because several bits of the register
are related to operation of the clock or its output logic
during servicing.

II -2652

Figure 4-13 Register Selection Logic

Five bits (4, 5, 12, 13, and 14) of the Miscellaneous
Register are not contained on this module. They are
contained on the M7813 module and are described in the
discussion of the M7813 module.

The bottom half of the logic generates the select and
enabling signals for the secondary registers. There are 16
secondary registers but only 11 are used in the basic DQll
option. They are: TX BUF, MISC, SYNC, 4 BA registers,
and 4 CC registers. The secondary registers are not selected
directly by the MI05 Address Selected Module. They are
selected by addressing the REG/ERR register and using the
states of bits 8-11 of this register to point to the desired
secondary register. Figure 4-12 shows truth tables that
illustrate this selection process.

The remaining 11 bits are contained in two D-type hex
flip-flops (bit 2 is not assigned). All bits are clocked by
signal LD MISC L from the M7813 module. The state of
each bit is controlled by the program via a Unibus data line.
The RC clock supplies a 14 Kbaud signal during the
transmit mode. The receiver clock comes in with the data
from the data set during the receive mode. An optional
crystal-controlled clock (M4050 module) can be installed in
the DQ 11 to be used during the transmit mode in place of
the RC clock. The crystal clock output is counted down by
16 or by 2 to provide baud rates of 250K and under or over
250K, respectively.

The inputs to the secondary register selection logic are:
D3-1 SEL 6 H from the MI05 module which is
asserted when the REG/ERR register is addressed to
set up bits 8-11 for the selected secondary register.
D4-6 REG PT 8 H-l1 H from the REG/ERR register
which represent the octal designation of the desired
secondary register.

The RC clock is also used in the test loop mode during
servicing of the DQ 11. If the external clock is lost when
receiving data, the RC clock is used to shift a character in
completely before the receiver is shut down by the clock
loss circuit on the M7813 module.

D3-1 IN H from the M105 module which is asserted
when a DATI bus transaction is initiated to read the
selected secondary register.

4-20

MISC REG
FLIP FLOPS
DB H

BITS 8 (1)H

09 H

BITS 9(l)H

010 H

BITS 10 (1) H

06 H

BCC 16 -23 (1) H

. - - - - - -.. SER DATA IN l
1ST OUTPUT
MUX

2 NO OUTPUT
MUX

BITS 11 (1) H

011 H

RECO DATA l --+-.-...

*SER ClK TX H--+-·+-'"

RX ClK H

*SER ClK RX H--+-+-....

~--~--t

TX DATA H

01 H - - - - t - - I..

015 H -----if---r--...
t-------f

03 H ---f--t--I..
t-------f

DO H---+---+---..t

lO MISC l
TX ACT (0 H
SW5

07 H
TX ACT (1) H

CRYSTAL
CLOCK
M4050

COUNTER

SW2

HO (1) H

sWJI-----L---'I'-----•.

**SER ClK EXT

SW4

NOTES

*From modem via OFll
*.To modem via OF11
"-2654

Figure 4-14 Block Diagram of Miscellaneous Register and Internal Oock

AO input of multiplexer E60. This input is selected (input
SO low) during normal operation because bit 1 (STEP
MODE) is cleared (D4-3 STEP MODE (1) H is low). The
receiver clock signal passes through multiplexer E60 and is
sent to pin 5 of NAND gate E69. The other input (pin 4) of
this gate is used to inhibit the clock when half-duplex mode
is selected (D4-4 HD (1) H is high) and the transmitter is
active (D5-6 TX ACTIVE (1) H is high). The output of E69
is D4-3 RX CLOCK H which is sent to the receiver shift
register.

During servicing, the test loop mode is initiated by the
program to substitute the RC clock for the normal clock at
the first multiplexer. The program can also initiate a single
step clock operation during servicing. This is done by
setting bit 1 (STEP MODE) while in the test loop mode and
toggling bit 0 (SHIFT CLOCK). This allows controlled
transitions of signals TX CLOCK Hand RX CLOCK H.
4.4.3.2 Detailed Logic Description - The circuit schematic for the Miscellaneous Register and internal clock is
contained in drawing D-CS-M7812-0-1 (Rev D) sheet 4
which is deSignated D4-3.

During a transmit operation, the clock can be supplied by
the DQ 11 or by the data set. If the clock comes from the
data set, it passes through the DF 11 and is sent to the Al
input of E59 as Dl-l SCT H. During normal operation, the
multiplexer A inputs are selected; therefore, Dl-l scr H
passes through E59 and is sent to the Al input of
multiplexer E60. During normal operation, this multiplexer
also selects its A inputs so the Al input appears at the fl
output as D4-3 TX CLOCK H. This Signal is sent to the
transmitter shift register control logic.

Miscellaneous (MISC) Register
The 11 bits of the MISC register, which are contained in
hex flip-flops E61 and E70, are clocked when D5-4 LD
MISe L is asserted. When this signal goes low, it is inverted
by E58 and the positive transition simultaneously clocks all
bits. Signal D5-4 LD MISC L is generated on the M7813
module (print D5-4) by decoder E44 after REG/ERR
register bits 8-11 have been set to 128 (MISC register) and
a write operation has been selected using SEL 6 H. Package
E70 contains bits 6 and 8-11. Bit 6 (D4-3 BCC 16-23 (1)
H) is not used in the DQII-AA option. Bits 8-11 D4-3
BITS 8 (1) H-ll (1) H are sent to the receiver shift register
(print D4-5) and are discussed later. Package E61 contains
bits 0, 1, 2, 3, 7, and 15. Bit 2 is not assigned and bit 15
(D4-3 VRC (1) H) is not used on this module. The other
bits (0, 1, 3, and 7) are related'to the use of the clock,
particularly during servicing, and are covered in the
discussion of the clock.

As previously mentioned, the internal transmit clock source
can be from the RC clock or from the optional crystal
clock. The RC clock consists of a pair of 7404 inverters
(E50), resistor R14 and capacitor CI07. It starts when
power is applied and is self-sustaining. The output frequency is approximately 28 KHz which is counted down by
flip-flop RC+2 (E51) to provide a clock output of
approximately 14 KHz. Switch SW5 (Figure 4-15) must be
closed to direct the RC clock output to the DFl1 as D4-3
SERIAL CLOCK EXTERNAL. Switches SW3 and SW4
must be open because the optional crystal clock is not used.
Switch SWI must be closed to prevent attenuation of the
RC clock signal; switch SW2 must be open. Additional
information concerning switches SWl, SW2 and SW5 is
contained in subsequent paragraphs in this section.

Internal Clock
During a receive operation, the data set sends the receiver
clock along with the data to the DQll. The received data
and receiver clock pass through the DFll converter and are
sent to multiplexer E59 (print D4-3). The data passes
through the DFll and is sent to the A2 input of E59 as
Dl-l RECEIVE DATA. The receiver clock passes through
the DFll and is sent to the AO input of E59 as Dl-l SCR
H. Package E59 is a quad 2-line-to-l-line multiplexer
(74157). It is held enabled by connecting the strobe (STB)
input permanently to ground. During normal operation, the
select (SO) input is low which chooses the A inputs. SO is
low because bit 3 (TEST LOOP) of the MISC register is not
set (D4-3 TEST LOOP (1) H is low) and the clock is
operating properly (D5-4 CLK LOSS SH CNTL H is low).
These two conditions drive pin 4 of E67 high. This signal is
inverted by E58 and applied to the select (SO) input of
E59. Signal Dl-l RECEIVE DATA L passes through
multiplexer E59 and is called D4-3 SERIAL DATA IN L. It
is sent directly to the receiver shift register (print D4-5).
Signal Dl-l SCR H passes through E59 and is sent to the

The optional crystal clock is contained on a module
(M4050) that plugs into the DQl1. Its output (D3-1 KA
CRYSTAL CLOCK H) is sent to inverter E50 (print D4-3).
This inverted clock signal is sent to the CLKO input of E52
which is a 74197 presettable binary counter. The preset
feature is disabled by permanently connecting the LD input
to +3 V. The counter cannot be cleared because the CLR
input is also connected to +3 V. Counter output RO (1) is
connected to clock input CLK1 which configures E52 as a
4-bit ripple-through counter. The input clock signal (D3-1
KA CRYSTAL CLOCK H) is divided by 2 at output RO (1)
and is divided by 16 at output R3 (1). Either output can be
selected as the transmitter clock. With switch SW3 closed
and switch SW4 open, the divide by 16 output is connected
to the DFl1. This is used for a baud rate of 250K or less.

4-22

SW1
SER ClK TRANSMIT

SER ClK EXT
o--~----,...---.------~~-

EXT

- - --

-+--~r--

- - - -,
I

SCR H

...-------1- - - - - .........--+-

COUNTER

SCT H

SW4

SW5

I
I

--- -

OF 11

CRYSTAL
CLOCK
M4050

I
I

-M---t-

CONVERTER

DF11
CONN

_...1
DATA SET

SW2

RC
CLOCK
CLOCK OUTPUT
MULTIPLEXER
! 1-2653

Figure 4-15 Block Diagram of Internal Clock to DFll Interface
DQ 11. The test loop mode of operation can be selected by
setting bit 3 (TEST LOOP) of the MISC register. During
this mode, the transmitter output is fed back to the receiver
input and is not sent to the data set. When bit 3 is set by
the program, signal D4-3 TEST LOOP (I) H is asserted and
selects the B inputs of multiplexer E59. The output of the
RC clock is sent to the BO and BI inputs of E59. These two
clock signals propagate through E59 and E60 to become
04-3 TX CLOCK Hand D4-3 RX CLOCK H. Signal 04-3
TEST LOOP (1) H is also sent to E67 pin 9 (print 04-7)
which holds the output of this gate low. This Signal (04-7
SERIAL DATA OUT L) is sent to the data set. The other
input to this gate is D -7 TX DATA IN which comes from
E23 pin 8. This signal is sent also to E68 pin 9. The other
input (pin 10) of E68 comes from inverter E58 and remains
high as long as bit 7 of the MISC is not set. Under these
conditions, the transmitter data (04-7 TX DATA H)
propagates through E68 to the B2 input of multiplexer
E59. The B inputs are selected so the transmitter data
passes through E59 to the D4-3 SERIAL DATA IN L line
which is the data input to the receiver shift register. Hence,
the transmitter data is looped back to the receiver input
and it is clocked by the internal RC clock.

With switch SW4 closed and switch SW3 open, the divide
by 2 output is connected to the DFI!. This is used for a
baud rate greater than 250K. The actual baud rate is a
function of the crystal frequency. When the crystal clock is
used, switches SW2 and SW5 must be open and SWI must
be closed.
Switch SW2 is closed only when a type 306 modem is used.
This modem requires that the transmitter clock signal be
returned to the modem.
With switch SWI open, it is possible to connect the RC
clock to the 04-3 SERIAL CLOCK EXTERNAL line
(switch SW5 closed) when the transmitter clock is supplied
by the data set. The RC clock signal is attenuated by
resistor RI7 and does not interfere with the data set clock.
It does allow the DQII to be disconnected from the data
set during servicing and to be checked using the RC clock
source. Otherwise, the clock is lost when the data set is
disconnected, if the data set is supplying the clock.
Several bits of the MISC register are interrelated with the
clock to provide special operations during servicing of the

4-23

clocked simultaneously when the register is addressed
during a DATa or DATOB (low byte) transaction.

During the test loop mode, the receiver can be checked
directly by toggling bit 7 (SEND DATA) provided the
transmitter is inactive. Inverter ES8 and E33 (print D4-3)
allow bit 7 in the MISC register to be set only if the
transmitter is inactive (DS-6 TX ACTIVE (1) H is low) and
the program makes bit 7 high (04-7 D7 H is high). The bit
7 output of the MiSe register is inverted by E58 and sent
to E68 pin 10. The other input (pin 9) of this gate is D4-7
TX DATA H and it is held low when the transmitter is
inactive. The output (pin 8) of E68 is the B2 input of ES9
and passes through to become 04-3 SERIAL DATA IN L.
By toggling bit 7, the state of this signal can be changed to
control the input to the receiver shift register.

4.4.4.2 Detailed Logic Description - The circuit schematic for the TX CSR is contained in drawing
D-CS-M7812-0-1 (Rev D) sheet 6 which is designated D4-4.
Bits 1, 3, and S are contained in a 74174 hex, D-type
flip-flop (E36). Three sections of E36 are not used. These
bits have a common clock and clear input. Bits 0,6, and 7
are contained in separate 7474 D-type flip-flops and use the
same clock Signal as bits 1,3, and S. All six bits are directly
cleared by DS-4 INI H which is generated as a result of BUS
INIT L or MASTER CLEAR which is bit S of the MISC
register.

During servicing, data can be single stepped through the
receiver and transmitter shift registers by selecting the step
mode of operation. The program selects the step mode by
setting bit 1 (STEP MODE) of the MISC register. This
asserts D4-3 STEP MODE (1) H and multiplexer E60 now
selects its B inputs. The source for the shift register clock
signals (D4-3 TX CLOCK Hand D4-3 RX CLOCK H) now
becomes the output of bit 0 of the MISC register which is
D4-3 STEP CK (1) H. Toggling bit 0 alternately strobes
data into the receiver and transmitter shift registers. Setting
bit 0 strobes the transmitter shift register and clearing bit 0
strobes the receiver shift register.

The clock signal is generated at the output (pin 3) of AND
gate E33. When the TX CSR is addressed during a DATa or
DATOB (low byte), the MI0S Address Selector asserts
D3-1 OUT LOW Hand D3-1 SEL 2 H. These signals are
sent to E33 pins 2 and 1, respectively. The output (pin 3)
goes high and this positive transition clocks all six bits.
As stated previously, direct clearing of all bits is performed
by DS-4 INI H. This signal is inverted by E2S and sent to
the direct clear input of each flip-flop. A low level clears
the flip-flop. Bit 0 of the TX CSR can be directly cleared
by two other signals: 04-6 TX ERR Land DS-4 0 -+ TX
GO L. These two signals, plus the inversion of DS-4 INI H,
are sent to 3-input AND gate E34 pins 10, 9, and 11,
respectively. This gate is shown as the logically-equivalent
negative OR. When any input signal is low, the output goes
low and bit 0 is directly cleared. Signal 04-6 TX ERR L is
generated in the output gating of the REG/ERR when any
one of several TX errors is detected. Signal DS-4 0 -+ TX
GO L is generated by the character count control logic
when the CC register overflows. Occurrence of these
conditions demands that bit 0 (TX GO) be cleared to
prevent the transmit data transfer.

4.4.4 Transmitter Control and Status Register
4.4.4.1 Functional Description - A simplified block diagram of the Transmitter Control and Status Register (TX
CSR) is shown in Figure 4-16. This discussion, and the
detailed discussion that follows, covers the operation of the
TX CSR and its associated logic. A register bit map Clt'1d
function 1 description of each bit is covered in Chapter 3,
Programming.
Only six bits of the TX CSR are shown on this module. The
remaining 10 bits are located on other modules and are
described in the discussion of the applicable module. Bit 14
is not assigned but it is available on the backplane as a TIL
connection. Bit 2 is located on the M7813 module (print
DS-4). Bits 4, 8, 9 and IS are located on the M781S module
(print D2-1). Bits 10-13 are signals to or from the data set
and are picked off the DF11 (print Dl-l).

Bits 0, 1, 3, and S are set by the program. Bits 6 and 7 are
directly set by the hardware using the flip-flop preset input.
They are cleared by the program using the D-input and
clock input. Bit 6 (TX S DONE) is set when DS-4 1 -+ TX S
DONE L goes low. This signal comes from the CC register
control logic (print DS-4) and is generated when the
transmitter secondary character count register overflows.
Bit 7 (TX P DONE) is set when DS-4 -+ TX P DONE L goes
low. This signal is generated when the transmitter primary
character count register overflows.

The TX CSR is word- and byte-addressable. The six bits on
this module are contained in D-type flip-flops and are

4-24

74174
~----r-- ERR

03 H

IE (1) H

t--------i
~---,---+-- IDLE

D1H

MODE (1) H

t--------i
I-----+-~-TX

D5H

T X P DON E L ---+---+-------,

DONE IE (1)H

.--+-1--- TX P DONE ( 1) H

PRE
07 H ---+---+----i 0

7474
TX P
DONE
CLK

O~----~

INTERRUPT
SELECT
GAT I NG

CLR

TX/ERR INTR L

ERR INTR H
1-

TX S DO N E L ---+--t----~

L....-_ _

L...-_ _ _

PRE

BCC OUT EN L
TX ACTIVE (1) H

t---+--+----- T X SOON E ( 1) H

06 H ---+---+-~ 0

7474
TX S
DONE

K
CLR

+ 3V
DOH ---+---+----i 0

PRE

~---+---

TX GO (I) H

7474
TX GO
OUT LOW H
SEL 2 H

CLOCK
GATING

CLK
CLR

INI H

TX ERR L
-TX GO L

CLEAR
GATING
11- 2721

Figure 4-16 Block Diagram of Transmitter Control
and Status Register

4-25

4.4.5.2 Detailed Logic Description - The circuit schematic for the RX CSR is contained in drawing
D-CS-M7812-0-1 (Rev D) sheet 6 which is designated D4-4.

The outputs of some of these six TX CSR bits are
combined in a 74HSS AND-OR-invert gate (E27) to
generate D4-4 TX/ERR INTR L which is sent to the
interrupt control logic on the M7813 module (print DS-S)
to generate the signal that initiates the request for an
interrupt under vector B (XX4).

Bits I, 3, 4, and 5 are contained in a 74174 hex, D-type
flip-flop (E45). Two sections of E45 are not used. These
bits have a common clock and clear input. Bits 0, 6, 7, and
IS are contained in separate 7474 D-type flip-flops. The
clock for bits 0, 6 and 7 is the same one that is used for bits
1, 3,4, and 5. Bit 15 uses a different clock signal. All eight
bits are directly cleared by D5-4 INI H which is generated
as a result of BUS INIT L or MASTER CLEAR which is bit
5 of the MISC register.

Gate E27 has two input sections; each one is a 4-input AND
gate. One section (pins 10-13) allows error conditions, as
represented by D4-6 ERR INTR H, to generate D4-4
TX/ERR INTR L, provided the error interrupt enable bit
(D4-4 ERR IE (1) H) is asserted. The other section (pins
1-4) allows TX S DONE and TX P DONE to generate D4-4
TX/ERR INTR L, provided the transmit done interrupt
enable bit (D4-4 TX DONE IE (1) H) is asserted. Another
qualifying input to this section is obtained by combining
the 0 output of the TX GO flip-flop and DS-6 TX ACTNE
(1) H at NAND gate E26. With this arrangement, TX S
DONE or TX P DONE cannot initiate an interrupt if the
TX GO flip-flop is cleared and DS-6 TX ACTIVE (1) H is
asserted.

The clock signal for bits 0, 1 and 3-7 is generated at E33
pin 11. A positive transition is generated at this point when
the RX CSR is addressed during a DATO or DATOB (low
byte) transaction. The Signals involved are D3-1 SEL 0 H
and D3-1 OUT LOW H from the MI05 Address Selector.
The clock Signal for bit IS is generated at E33 pin 8. It is
generated when the RX CSR is addressed during a DATO or
DATOB (high byte) transaction. The signals involved are
D3-1 SEL 0 Hand D3-1 OUT HIGH H from the MI05
Address Selector.

4.4.5. Receiver Control and Status Register
As stated previously, direct clearing of all bits is performed
by D5-4 INI H. This signal is inverted by E25 and sent to
the direct clear input of each flip-flop. A low level clears
the flip-flop. Bit 0 of the RX CSR can be directly cleared
by two other Signals. D4-6 RX ERR Land D5-4 0 ~ RX
GO L. These two signals, plus the inversion of D5-4 INI H,
are sent to 3-input AND gate E34 pins 2, I, and 13,
respectively. This gate is shown as the logically-equivalent
negative OR. When any input signal is low, the output goes
low and bit 0 is directly cleared. Signal D4-6 RX ERR L is
generated in the output gating of the REGiERR register
when anyone of several errors is detected. Signal D5-4
o~ RX GO L is generated by the character count control
logic when the CC register overflows. Occurrence of these
conditions demands that bit 0 (RX GO) be cleared to
prevent the receive data transfer.

4.4.5.1 Functional Description - A simplified block diagram of the Receiver Control and Status Register (RX CSR)
is shown in Figure 4-17. This discussion, and the detailed
discussion that follows, covers the operation of the RX
CSR and its associated logic. A register bit map and
functional description of each bit is covered in Chapter 3,
Programming.

Only eight bits of the RX CSR are shown on this module.
The remaining eight bits are located on other modules and
are described in the discussion of the applicable module.
Bits 2 and 12 are located on the M7813 module (prints
D5-4 and D5-7 , respectively). Bits 8-11 are located on the
M7818 module (print D6-l) or on the M7817 module
(print D8-3) if the ooll-BB option is installed. Bits 13 and
14 are located on the M7815 module (print D2-1).

Bits 0, I, 3, 4, and 5 are set by the program. Bits 6, 7, and
15 are directly set by the hardware using the flip-flop preset
input. They are cleared by the program using the D-input
and the clock input. Bit IS (CHAR INTR) is set when D6-1
1 ~ CHAR INTR L goes low. This signal comes from the
hard-wired character detection logic (M7818 module) when
a selected character has been detected or from the
programmable character detection logic (M7817 module) if
the DQII-BB option is installed.

The RX CSR is word- and byte-addressable. On this
module, all eight bits are contained in D-type flip-flops and
are clocked simultaneously when the register is addressed
during a DATO transaction. Bits 0, I and 3-7 are clocked
during a DATOB (low byte) transaction and bit IS is
clocked during a DATOB (high byte) transaction.

4-26

74174
D5H-

BIT5

~--------RXDONEIE(l)H

01 H -

BI T 1

'---------------+- STRIP SYNC (1) H
1----------+- H 0(1) H

03 H D4H-

t-----;
BIT4

CHARIE(l)H

rcu<

ClR

r------------,J

1 - CHAR INTR L - - - 1 - 1 - - - - - - ,

L---

PRE
015 H - - - + - - - 1 I - - - - - i 0

1
7474
CHAR
I NTR

R X BCC CYCLE l

ClK

1 - RX P DONE l i

1
I~i-----+--+--_ _
------'

PRE
1

P
HOLD

CHAR INTR ( 1)H

~~-~~~----~6
D7H---+--~~----~ 0

RX P DONE (1 ) H

7474
RX P
DONE
ClK
0

ClR

1 - RXS D O N E l i

RX BCC CYC lE l

PRE

t- ClKClR Of--

Or-

ClR

INTERRUPT
SELECT
f - - RX/CHAR INTR L
GATING

PRE

1I-----t---L..-JJ"
S
HOLD

PRE
D6H---+-I-I----, 0

RX S DONE (I ) H

7474
RX S
DONE

1- ClK ClR Of-

ClK

ClR

I'
j;+3V
PRE
DOH---4--~~--,

11-------------- RX GO (1) H

7474
OUT HIGH H CLOCK I---RX GO
OUT lOW H - GATING
OrSE l 0 H _
1------'--t------1 ClK
ClR
INIT H
CLEAR
RX ERR l GAT ING t-O-RXGOlL--_~

Figure 4·17 Block Diagram of Receiver Control
and Status Register

4·27

11-2720

Bits 6 and 7 are set when the respective receiver character
count registers overflow (secondary register for bit 6 and
primary register for bit 7). In each case, the signal that is
generated at overflow (D5-4 1 ~ RX P DONE L or D5-4
1 ~ RX S DONE L) is not sent directly to the respective
RX CSR flip-flops; that is, RX P DONE and RX S DONE.
The overflow signal sets a holding flip-flop (P HOLD or S
HOLD) whose output is gated with a signal from the BCC
control logic (module M7816) and is then sent to RX P
DONE or RX S DONE. This logic is used to prevent these
flip-flops from being set until an in=process BCC cycle is
finished. The BCC feature is not part of the basic DQII-AA
option but it is appropriate to mention it in this discussion.
Both holding circuits are identical; only the one associated
with flJp-flop RX P DONE is discussedo

All REG/ERR CSR bits except one (bit 12) are shown on
this module. Bit 12 is located on the M7813 module and is
described in the discussion of this module.
The REG/ERR CSR is word- and byte-addressable. On this
module, 14 bits are contained in D-type flip-flops. The
remaining bit (15) is obtained by ORing the outputs of the
register low order byte (bits 0-7). All 14 bits (bit 15
excluded) are clocked Simultaneously during a DATO
transaction. Bits 0-7 are clocked during a DATOB (low
byte) transaction. Bits 8-11, 13 and 14 are clocked during
a DATOB (high byte) transaction.
4.4.6.2 Detailed Logic Description - The circuit schematic for the REG/ERR CSR is contained in drawing
D-CS-M7812-O-1 (Rev D) sheet 8 which is deSignated D4-6.

When the receiver primary character count register overflows, signal D5-4 1 ~ RX P DONE L is generated. This
signal is sent to the preset input (pin 10) of the P HOLD
flip-flop which directly sets it. The high at the 1 output of
P HOLD is sent to pin 12 of2-input NAND gate E41. If the
BCC cycle is not in progress, the other E41 input (pin 13)
floats high. The low output (pin 11) of E41 sets the RX P
DONE flip-flop via its preset input (pin 10). The positive
transition at the 1 output of RX P DONE is fed back via an
RC delay to clock the P HOLD flip-flop. This clears the
flip-flop because its D-input is permanently connected to
ground.

Bits 0-7 are contained in two 4015 quad D-type flip-flops
(E5 and E6). This type flip-flop has common clock and
direct clear inputs; however, each of the four sections has a
separate preset input labeled SET. Bits 8-11, 13, and 14
are contained in a 74174 hex, D-type flip-flop (E7) which
has common clock and direct clear inputs. All bits in E5,
E6 and E7 are directly cleared by D5-4 INI H which is
inverted by E25 before being applied to the CLR inputs of
E5, E6, and E7.
Bits 0-7 are clocked by Signal D5-4 LD ERR H and bits
8-11, 13, and 14 are clocked by signal D5-4 LD PTEE H.
These clock signals are generated simultaneously on the
M7813 module (print D5-4) when the REG/ERR CSR is
addressed during a DATa transaction. Signal D5-4 LD ERR
H is generated also during a DATOB (low byte) transaction.
Signal D5-4 LD PTEE H is generated also during a DATOB
(high byte) transaction.

The outputs of some of these eight RX CSR bits are
combined in a 74H55 AND-OR-invert gate (E44) to
generate D4-4 RX/CHAR INTR L, which is sent to the
interrupt control logic on the M7813 module (print D5-5)
to generate the signal that initiates the request for an
interrupt under vector A (XXO).
Gate E44 has two input sections; each one is a 4-input AND
gate. One section (pins 10-13) allows CHAR INTR to
generate D4-4 RX/CHAR INTR L, provided the character
interrupt enable bit (D4-4 CHAR IE (1) H) is asserted. The
other section (pins 1-4) allows RX P DONE and RX S
DONE to generate D4-4 RX/CHAR INTR L, provided the
receiver done interrupt enable bit (D4-4 RX DONE IE (1)
H) is asserted.

Bits 0-7 are error bits and are set by the hardware using
the flip-flop preset input. They are cleared by the program
using the D-input and clock input. In all but two of these
bits, the setting Signal is sent directly to the preset input of
the flip-flop. The exceptions are bits 4 and 5 that detect
transmitter and receive non-existent memory errors. When
non-existent memory is addressed, the TIME our flip-flop
on the M7818 module is set which generates D6-2 TIME
OUT (1) H. This signal is combined with D5-3 TX CYCLE
Hand D6-2 TIME OUT H in separate NAND gates (E8).
For example, if non-existent memory .is addressed during a
transmit cycle, both D5-3 TX CYCLE Hand D6-2 TIME
OUT H are asserted.

4.4.6 Register Pointer and Error Control and Status
Register (REG/ERR CSR)
4.4.6.1 Functional Description - A simplified block diagram of the REG/ERR CSR is shown in Figure 4-18. This
discussion, and the detailed discussion that follows, covers
the operation of the REG/ERR CSR and its associated
logic. A register map and functional description of each bit
is covered in Chapter 3, Programming.

The output (pin 6) of E8 goes low and sets bit 4 of the
REG/ERR CSR via its preset input. This generates the
transmit non-existent memory flag (D4-6 TX NON MEM
(1) H).
4-28

4015
02 H

01 H

DO H
1 -TXC K lOSS l
04H
TX CYCLE H
TIMEOUTH

RX CYCLE H

TX lATE (1) H

BIT
1

RX CK lOSS (1) H

0
- SET

BIT
0

TX CK lOSS ( 1) H

BIT
4

1-RX CKLOSS l

h=:

BIT
2

T X lATE l

SET
0
SET

- SET
ClK

03 H
I'

06 H

SET

07 H

,..

lO ERR H

TX NON MEM (1) H
TX
ERROR
GATING
RX
ERROR
GATING

TX ERR l

H
-

ERROR
GATING

BIT
5

RX NON MEM ( 1) H

BIT
3

RX lATE (1) H

RX ER R L-

BIT
6

RX BCC ERR ( 1) H

BIT
7

RX VRC ERR ( t)H

SET
ClK

I ClR

74174
BIT 8

09 H

BIT 9

r--- REG PT 9 ( 1) H

014H

BIT 14

r - - - EE 14(I)H

011 H

BIT 11

r - - - REG PT 11 (I ) H

010H

BIT 10

r - - - REG PT 10 (1) H

013H

BIT 13

r---EEI3(llH

ClK

INI H

r - - - REG PT 8 ( 1) H

08 H

l o PT EE H

ERR H

- SET

VRC E RR OET l

"""""-

4015

SET

B CC ERR l

ClR

05 H

R X lATE l

NOTE
The low byte is
contained in two
quad 4015 flip-flops.
Each section has a
direct set input.

I ClR
•

"""

11 -2719

Figure 4-18 Block Diagram of REG/ERR Control
and Status Register

4-29

The SYNC register is composed of three 74174 hex
flip-flops. Bits 0-5 are stored in E31; bits 6-9 are stored in
E30; and bits 10-15 are stored in E28. The inputs come
from the Unibus data lines via receivers on prints 04-1 and
04-2. The input signals are identified as 04-1 00 H to 04-1
07 Hand 04-2 08 H to 04-2 015 H. All bits are directly
cleared Simultaneously by D4-3 CLR SYN L which is the
inversion of 054 INI H. All bits are clocked simultaneously
by 05-4 LO SYNC L. This signal is generated by the
secondary register pointer decoder on the M7813 module
(print D54). The SYNC register is selected when REG/
ERR CSR bits 8-11 indicate lIs.

The preset input (SET 1) for bit 6 is connected to 09-6
BCC ERR L and to +5 V via resistor R20, in parallel. Signal
09-6 BCC ERR L is not used unless the DQ 11-BB option
(M7817 module) is installed. Without the M7817 module
installed, the preset input is inhibited by the +5 V.
Three receive error flags (bits 1, 3, and 5) are ORed and
three transmit error flags (bits 0, 2 and 4) are ORed to
generate a signal that clears the respective GO flip-flop in
the RX CSR and TX CSR when an error is detected. Signals
D4-6 TX CK LOSS (1) H (bit 0), 04-6 TX LATE (1) H (bit
2), and 04-6 TX NON MEM (1) H (bit 4) are sent to
4-input NOR gate E14 pins 9, 12, and 10, respectively. Pin
13 is permanently connected to ground. If an error flag is
set, the output (pin 8) of E14 goes low and asserts 04-6 TX
ERR L. This signal is sent to the clear input of the TX GO
flip-flop (print 04-4). A similar arrangement is used for the
RX error flags to generate 04-6 RX ERR L which clears the
RX GO flip-flop (print 044).

If the receiver is not framed; a bit-by-bit sync search is
performed by loading the RX shift register outputs into the
RX buffer. In this way, the RX shift register is compared
with the sync register. The SYNC register outputs are 04-7
SO (1) H to 04-7 SIS (1) H. Each output goes to one input
of a 2-input 8242 comparator. The other input of each
comparator is connected to the corresponding bit from the
output of the receiver buffer (print 04-5). These inputs are
identified as 04-5 RD 0 H to 04-5 RO ISH. The SYNC
register is loaded with the desired sync character and when
it is detected in the receiver buffer, both inputs to each
8242 comparator are identical. The comparator is an
exclusive-NOR and its output is high only when both inputs
are identical. It has a bare collector so that several
comparator outputs can be connected together (wire-ORed
connection). The outputs of the comparators for the high
byte (bits 8-15) are connected together and tied to +5 V
through common-collector resistor R13. The wire-ORed
output of the high byte is also sent to pin 2 of NANO gate
E68 and pin 1 of NAND gate E66. A similar arrangement
wire-ORs the low bytes (bits 0-7) comparators and sends
the output to pin 2 of E66. This· hardware configuration
requires that if a sync character of eight bits or less is
desired, the same character must be loaded into each byte.
All unused bits must be set to O. The least Significant bit
(LSB) is right-justified.

Signals 04-6 RX BCC ERR (1) H (bit 6) and 04-6 RX VRC
ERR (1) H are sent to the inputs of NOR gate E15. The
output of this gate is sent to pin 9 of NAND gate E24
which is shown as the logically-equivalent, negated-input
OR. Pins 10 and 11 of E24 are connected to the outputs of
the above mentioned E14 gates. This arrangement allows
anyone of eight error flags to generate 04-6 ERR INTR H
when an error has been detected. This signal is bit 15 of the
REG/ERR CSR and allows an error to generate an
interrupt.
4.4.7 Sync Register (SYNC) and Transmitted Data Output
Logic
4.4.7.1 Functional Description - A simplified diagram of
the SYNC register is shown iT! Figure 4-19. It is a
programmable 16-bit register. The desired sync character is
loaded by the program into the SYNC register. The output
of the SYNC register is compared with the output of the
receiver buffer register which contains the received sync
word. If they match, Signal 04-7 RX SYNC OET H is
generated and goes to the M7813, M7816, M7817 and
M7818 modules.

Gate E66 and two E68 gates form a network that samples
the comparator outputs and bit 11 of the MISC register to
generate 04-7 RX SYNC OET H. This Signal is asserted
when a correct sync character is detected and it is sent to
the M7813, M7816, M7817 and M7818 modules.

The output of the SYNC register is also sent to two 8-bit
multiplexers that perform parallel-to-serial conversion of
the sync character and send it out as a transmitted
character.

Both bytes are used for characters of 9-16 bits. The high
byte only is used for characters of 1-8 bits and the low
byte is ignored. This is an operation function of the receiver
buffer.

4.4.7.2 Detailed Logic Description - The circuit schematic for the SYNC register is contained in drawing
0-CS-M7812-O-1 (Rev 0) sheet 9 which is designated 04-7.

4-30

TX SYNC EN 1 5-8 L1

DI5H-Dl0H

)

........----.1"./

74174
SYNC
15-10
CLK

~-----------------------------------~~
BITS 15-10
)
r---------,p~

~-__------~~,

CLR

BITS 889

....

. . . .------------'t/..

STB
74151
SEND

TX BCC/DLE L VRC/DATA SEL LT X DATA 15- 8 L TX DATA 7-0 L -

DA T A
OUT
GATING

I--

SYNC f
15-8
52 SI SO
SERIAL DATA
OUT L

TEST LOOP (1) H

BITS II (1) H

D9H-D6HI

)

~"""""---'I"t/

74174
SYNC
9-6
CLK

t--

BITS 9-6

SYNC
"') COMPARATOR~--------4-+-~--I---~ DETECT f - - RX SYNC DET H
./
GATING

;.A

CLR

J
RD15HRD 0 H

D5H -DOH

...

)

~,........,,........,t/

74174
SYNC
5-0

CLK

LD SYNC L

CLR

CL.R SYNC L _ _ _ _---L_ _ _ _~

BITS 11 L

TX SYNC
EN 7-0 L
_____...........
,'-

1
STB

)

BITS 5-0

74151
SEND f~~~~_4--~
.........
SYNC
........- - - - - - - - - - - - - - - - - - - - ....
~
7-0
........_______B_'_T_S__
6_8_7__________...".../ 52 SI SO
~

I II

TX BIT CNTR4(OH
TX BIT CN TR 2 (1) H ----L-f--~
TX BIT CNTR 1(1) H _ _ _ _ J'--_ _~
11-2718

Figure 4-19 Block Diagram of SYNC Register

The other input (pin 9) of E67 is D4-3 TEST LOOP (1) H
which is low during normal operation. The information to
be transmitted (pin 8) is thus inverted and is sent to the
data set as D4-7 SERIAL DATA OUT L. When the test
loop mode is used during servicing, D4-3 TEST LOOP (1) H
is asserted and the output of E67 (D4-7 SERIAL DATA
OUT L) is held low.

As stated previously, the wired-OR output of the high byte
is sent to pin 2 of E68 and pin 1 of E66; and the wired-OR
output of the low byte is sent to pin 2 of E66. The other
pin of each gate is connected to the output of bit 11 of the
MISC register. This bit is the MSB of the four bits (8-11)
that select the bits-per-character. It is high if the bits-percharacter selected is 1-8 and is low if the bits-per-character
selected is 9-16. Signal D4-3 BITS 11 (1) H is sent to E68
pin 1 and its inversion D4-S BITS 11 L is sent to E66 pin
13. When a sync character is detected, either E68 pin 3 or
E66 pin 12 goes low, depending on the bits-per-character
selected. These outputs are connected to pins 4 and S, or
E68, so that either one can generate D4-7 RX SYNC DET
H at the output (pin 6) of E68.

4.4.8 Transmitter Shift Register
4.4.8.1 Functional Description - A simplified block diagram of the transmitter shift register is shown in Figure
4-20. This discussion, and the detailed description that
follows, covers the operation of the transmitter shift
register.

During transmission, the selected sync character, which is
stored in the SYNC register, is serialized by two 741S1
multiplexers (E29 and E32) and sent out to the data set.
Each multiplexer handles 8 bits of the SYNC register.
Complementary outputs are provided, but only the output
(pin 6) that is the inversion of the input is used. The same
selection signals are used for both multiplexers: DS-6 TX
BIT CNTR 4 (1) H, DS-6 TX BIT CNTR 2 (1) H, and DS-6
TX BIT CNTR 1 (1) H. These signals represent a 3-bit BCD
code that selects one of eight inputs (DO-D7). They are
outputs of the TX BIT COUNTER (print DS-6) that counts
in accordance with the number of bits-per-character
selected. Each multiplexer has a separate enable input (pin
7) that must be low to enable the multiplexer. The enabling
signal for the low byte (E32) is DS-6 TX SYNC EN 7-0 L
and for the high byte (E29) it is DS-6 TX SYNC EN IS-8
L. The transmitter control logic on the M7813 module
(print DS-6) controls assertion of the enabling inputs to all
of the proper number of bits to be serialized by the
multi plexers.

The transmitter shift register consists of a buffer, shift
holding register and send-data selector. Data to be transmitted comes from the Unibus and is clocked into the
buffer by LD TX BUF (1) H. The data is sent from the
buffer to the shift hold register and is clocked in by LD TX
SH REG H. From this register, the information is sent to
the send-data selector. This register is enabled by bytes
using signals TX DATA EN 7-0 Land TX DATA EN IS-8
L. A counter in the transmitter shift control logic provides
the select signals that ripple through the send-data selector
to serialize the input data by bytes.
4.4.8.2 Detailed Logic Description - The circuit schematic for the transmitter shift register is contained in
drawing D-CS-M7812-O-1 (Rev D) sheet 7 which is
identified as D4-S.
Data to be transmitted comes from the Unibus data lines
via bus receivers (prints D4-1 and D4-2). The information is
identified as D4~1 DO H to D4~1 D7 H and D4~2 D8 H to
D4-2 DIS H and is sent to the transmitter buffer. This
buffer is composed of three 74174 hex flip-flops: EI0 for
bits IS-10, E12 for bits 9-6, and E13 for bits S-O. The
data goes to the D inputs of the 74174s and is clocked to
output on the positive transition of clock signal D6-2 LD
TX BUF (1) H. This Signal comes from the NPR control
logic on the M7818 module.

The output of each multiplexer goes to an input of E23.
This 8-input NAND gate, which is shown as the logicallyequivalent, negated-input OR, is the place where all
transmitted information leaves the DQll for the data set.
This information includes both bytes of the SYNC register,
both bytes of the transmitter data register ,_ VRC bit, and
BCC information. Signal D9-4 TX BCC/DEL L is used only
when the DQl1-AB option (M7816 module) is installed.
When the M7816 module is not installed, pin 12 of E23 is
held high permanently by the +S V through RIO. Gate E23
inverts each input and sends it to pin 8 of NOR gate E67.
The signal on this line (D4-7 TX DATA H) is sent to the
BCC register which is present only in the DQl1-AB option.

The output of the buffer goes to the transmitter shift hold
register that is composed of three 74174 hex flipflops: E19 for bits IS-10, Ell for bits 9-6, and E22 for
bits s-o. The 74174s are clocked by DS-6 LD TX SH REG
H from the transmitter control logic on the M7813 module.

4-32

[

TX DATA EN 15 8l

STB

D15H -010 H

74174
TX
BUF
15-10
ClK

TBI5H-TB10H

)
v

ClR

74174
TX SH
HOLD
15-10
ClK

....
TDI5H-TD10H

TD9H 8 TD8 H

ClR

•

74151
SEND
DATA
SEl
15-8

......)

..)

f C)-- TX DATA 15-8 l

rD9H -D6H

74174
TX
BUF
9-6

TB9H-TB6H

~
/

74174
TX SH
HOLD
9-6
~-

ClK

ClR

ClK

ClR

STB

TD7H 8 TD6H

~
/

D5H -DO H

)

74174
TX
BUF
5-0
ClK

lDTX BUF (1) H
H INI

....
TB5H-TBOH

)

ClR

lD TX SH
REG H

74174
TX SH
HOLD
5-0
ClK

ClR

TX DATA EN 7-0 l

TD5H-TDOH

~
.../

74151
SEND
DATA
SEl
7-0

52 51
TX BIT CNTR 4 ( 1) H
TX BIT CNTR 2 (1) H

~ TX DATA 7-0 l

TX BIT CNTR 1 (1) H
11-2717

Figure 4-20 Block Diagram of Transmitter Shift Register

The receiver shift register is a unique device that allows
serial data to be entered at any 1 of 16 bit positions and
shifted until the character reaches the selected length. It is
composed of four 74175 quad D-type flip-flops, sixteen
2-input X-OR gates and two 7442 octal decoders. It is
called the Lisee Super Shifter (LSS) , which is a name
worthy of its uniqueness.

The output of the shift hold register is sent to the input of
the send-data selector that is composed of two 74151
l-of-8 multiplexers: E20 for the high byte (bits 15-8) and
E21 for the low byte (bits 7-0). The multiplexers have
complementary outputs but only the one that gives the
inverse of the input is used. The select inputs (S2, SI, and
SO) of both multiplexers are controlled by the TX BIT
counter in the transmitter control logic on the M7813
module. The counter ripples through the selected count
(0-7 maximum) to select each input ill order which
performs a parallel-to-serial conversion of data from input
to output. Each multiplexer has a separate enabling (STB)
input from the transmitter control logic: D5-6 TX DATA
EN 7--0 L for the low byte and D5-6 TX DATA 15-8 L
for the high byte. The low byte serial output is D4-5 TX
DATA 7-0 L and the high byte serial output is D4-5 TX
DATA 15-8 L. The transmitter control logic enables the
multiplexers in sequence.

The storage section of the register consists of four 74175
quad D-type flip-flops. Each one handles four bits of the
register as follows: bits 15-12 (E87), bits 11-8 (E86), bits
7-4 (E85), and bits 3-0 (E84). All bits are clocked by the
data set clock that is designated D4-3 RX CLOCK H. All
bits are directly cleared by D5-7 CLR RX L which comes
from the shjft control logic on the M7813 module. The
74175s have complementary outputs. The 1 outputs are
sent to the inputs of the receiver buffer. Each 0 output
(except bit 0) is fed back to one input of a 2-input X-OR
gate that is connected to the D-input of the next least
significant bit. The register is divided into two bytes. On a
byte basis (8 bits), the other input of each X-OR gate is
connected to an output of the 7442 receiver data decoder
(E79 for bits 15-8 and E88 for bits 7-0).

4.4.9 Receiver Shift Register and Receiver Data Register
4.4.9.1 Functional Description - A simplified block diagram of the receiver shift register and data register is shown
in Figure 4-21.

The 7442 is a 4-line-to-IO-line decoder but in this application it is used as a 3-wire binary-to-octal decoder. Three
of the four inputs (DO, Dl and D2) are used to select 1 of 8
outputs that are deSignated fO-f7. The fourth input (D3) is
the enabling input which must be low to enable the
decoder.

The 16-bit shift register stores the received character in
accordance with the number of bits per character selected
(l through 16). Characters of nine bits or over are single
characters; whereas characters of eight bits or less are
shifted into both bytes of the register to provide double
characters. Entry of the received serial data into the correct
bit position of the register is provided by the receiver data
decoder. Bits 8-11 of the MISC register determine the
number of bits per character (Chapter 3). The output of
MISC register bits 8-11 is sent to the receiver data decoder
to control the data entry point.

The selection bits (inputs DO, Dl and D2) come from bits
8-10 of the MISC register which select the number of bits
per character. The enabling signal (input D3) for the high
byte decoder (E77) is D4-3 SERIAL DATA IN L. The
enabling signal for the low byte decoder (E88) is D4-3 BITS
11 (1) H from the MISC register and the 1 output of bit 8
from the receiver shift register combined in NAND gate
E69.

The receiver shift register is clocked by RX CLOCK H
which is the clock signal that comes with the data from the
data set.
The shift register output is loaded into the receiver buffer
by bytes: signal LD RX BUF 15-8 L loads the high byte
and signal LD RX BUF 7-0 L loads the low byte. Loading
by bytes is required because of the character stripping
function. The output of this buffer is again buffered before
being sent to the Unibus data lines.

The operation of the receiver shift register is described in
the following example.

Assume that data is being received and the register has been
selected to process the data as 8-bit characters.
Remembering that characters of 8 bits or less are handled as
double characters, an 8-bit character is loaded into each
byte of the register.

4.4.9.2 Detailed Logic Description - The circuit schematic for the receiver shift register is contained in drawing
D-CS-M7812 (Rev D) sheet 7, which is designated D4-5.

4-34

BITS 8 (1) H

BITS9 (1)H

BITS10(I)H

SERIAL DATA IN L

74175
RX
SHIFT
15-12

74197
RX BUF
15-12

CLK CLR

,LD CLR Cl
LD RX BUF
15-8 L

03
7442
RX DATA
DCDR
15-8

74175
RX
SHIFT
11- 8

+5V

'74197
RX BUF
11-8

LD RX BUF
15- 8L

BITS 11 L

RD15H RD12H

L..---'--_L.--_

RDllHRD 8 H

+5V

RX SHIFT BIT 8

74175
RX
SHIFT
7-4

DO
01
'----102

74197
RX BUF
7-4

LD RX BUF
7-0L

D----~ClD3

L..---'-_.L-_

RD 7HRD4 H

+5V

BITS 11 (1) H
7442
RX DATA
DCDR
7-0
74197
RX BUF
3-0

R X C L 0 C K H ---'---+------"

C L R R X L _ _--'-_ _ _----J

LD RX BUF
7-0L

L..---'-_.L-_

RD3 HRD OH

+5V
11-2722

Figure 4-21 Block Diagram of Receiver Shift Register

4-35

Unibus Data Lines
Low = Logical 1 (Mark)
High = Logical 0 (Space

The output (pin 6) of inverter E58 keeps a high
on input pin 1 of X-OR gate E78 whose output
(pin 3) is sent to the D input of register bit 15
(E87 pin 4). The other input (pin 2) of the
X-OR gate comes from decoder output fO,
therefore, it follows the state of D4-3 SERIAL
DAT A IN L at input D3 because an 8-bit
character length has been selected (output fo
enabled).

The input data (D4-3 SERIAL DATA IN L) is inverted by
the X-OR gates to comply \vith the convention for signa!
states.

Outputs fl-f7 from both decoders rero..ain
high. Each one goes to an X-OR gate input;
specifically, those associated with bits 14-8
and 6-0.

Assume now that received data (D4-3 SERIAL
DATA IN L) and the receiver clock (D4-3 RX
CLOCK H) are present. Each data bit is
accompanied by a clock pulse that clocks
(shifts) the register on the positive transition of
the pulse.

In the following discussion, the state of the received
character bit (O43 SERIAL DATA IN L) is stored in
complementary form in the register; for example, a low
received data bit is stored as a high in the register. This is
done to adhere to the convention of representing a mark
and space properly as shown below.

Mark Data Set
Mark = Low = Logical
Space = High = Logical 0

Prior to receiving data, assume that the register has been
cleared.
1.

The decoder selection signals (D4-3 BITS 8 (I)
H, D4-3 BITS 9 (1) H, and D4-3 BITS 10 (1) H)
are all low. This selects output fO of both
decoders (E79 and E88). Outputs fl-f7 are not
selected and remain high.

For decoder E79, output fO follows signal D4-3
SERIAL DATA IN L which is the strobe input
(D3) of the decoder. Actually, the decoder is
enabled when D3 is low and is disabled when
D3 is high.

For decoder E88, output fO follows strobe
input D3; however, the strobe signal comes
from NAND gate E69 pin 8. This signal is a
function of D4-3 BITS 11 (1) H which is high
and the 1 output of receiver shift register bit 8
(E86 pin 2).

The 1 output of register bit 8 is also combined
with 04-5 BITS 11 L at NAND gate E69 pins
13 and 12, respectively. Signal D4-5 BITS 11 L
is the inversion of D4-3 BITS 11 (1) H and so it
is low. This means, that the output (pin 11) of
E69 remains high, regardless of the state of the
1 output of register bit 8. This keeps a high on
input pin 13 of X-OR gate E76 whose output
(pin 11) is sent to the D input of register bit 7
(E85 pin 12). The other input (pin 12) of the
X-OR gate is low or high depending on whether
the E88 decoder is enabled or disabled.

As the data and clock pulses arrive, the receiver shift
register functions as follows for this example (double 8-bit
characters).

4-36

The receiver starts in the cleared state. Assume
that the first received bit (D4-3 SERIAL DATA
IN L) is low. This signal enables decoder E79
and a low, corresponding to the first received
bit, is generated at decoder output fOe This puts
a low on input pin 2 of X-OR gate E78. The
other input (pin 1) of this gate is held high
permanently by E58. With a low and a high on
its inputs, the output (pin 3) of X-OR gate E78
goes high. This signal goes to the D input of
register bit 15 (E87 pin 4). When D4-3 RX
CLOCK H goes high, bit 15 is set. Its 1 output
(pin 2) is sent to the receiver buffer input. Its 0
output, which is low, is fed back to input pin
13 of X-OR gate E78 that is associated with
register bit 14. The other input (pin 12) of this
X-OR gate is held high by decoder output fl.
The bit 14 X-OR gate is now set up just like the
bit 15 X-OR was set previously. When the
second clock pulse occurs, bit 14 is set. The
high in bit 15 has been shifted down to bit 14.
The state of bit 15, after the second clock
pulse, is determined by the state of the second
bit of the received character and is shifted to
bit 14 on the third clock pulse.

After the first bit of received data is shifted to
register bit 8, the high byte of the register
contains an 8-bit character justified to the least
significant bit position (bit 8). It is desired to '
continue the shifting until this character is in
the register low byte and a new character is
shifted into the high byte.

The 1 output of register bit 8 (E86 pin 2) is
sent to NAND gate E69 pin 9. The other input
(pin 10) of this gate is D4-3 BITS 11 (1) H
which is high because 8 bits per character is
selected. The output (pin 8) of E69 goes to the
strobe input of decoder E88.

Signal D4-5 BITS 11 L is sent to input pin 12
of NAND gate E69. The other input (pin 13) of
this gate comes from the 1 output of register
bit 8. The output (pin 11) of E69 is sent to
X-OR gate E76 pin 13 which is the D input to
register bit 7. With D4-5 BITS 11 L held high,
pin 13 of X-OR gate E76 can be either high or
low, depending on the state of register bit 8.

Under these conditions, a character of 9-16 bits in length
is shifted into the register starting at the high byte and ends
up justified to the least significant bit.
The outputs of the shift register are sent to the inputs of
the receiver buffer that is composed of four 4-bit 74197
latches: E69 for bits 15-12, E95 for bits 11-8, E94 for
bits 7-4, and E93 for bits 3-0. The 74197s are actually
presettable binary counters/latches. In this application they
are used as latches, only so the counting function is
disabled by connecting the clock and clear inputs
permanently to +5 V.

The eighth clock pulse sets register bit 8. The
output of this bit (E86 pin 2) is high, which via
E69 pin 8, drives the strobe input of decoder
E88 low to enable output fOe The signal from
fO goes to input pin 12 of X-OR gate E76. The
other input (pin 13) comes from NAND gate
E69 pin 11 which is held high because one of
its inputs (D4-5 BITS 11 L) is low when 8 bits
per character is selected. The high and low
inputs on X-OR gate E76 drive its output (pin
11) high. This signal is the D input to register
bit 7. The ninth clock pulse sets register bit 7.
The process continues until this high, which
represents bit 1 of the first received character,
reaches register bit O. Now, the first 8-bit
character is in the register low byte (bits 7-0)
and the second 8-bit character is in the register
high byte (bits 15-8).

When the received character has been loaded into the shift
register, the received character control logic on the M7813
module generates two signals that load the received
character into the buffer. The signals are D5-7 LD RX BUF
15-8 L, which is sent to the load (LD) input oflatches E96
and E95, and D5-8 LD RX BUF 7-0 L, which is sent to the
load input of latches E94 and E93. A low signal on the LD
input transfers the information at the inputs to the outputs
which are identified as D4-5 RD XX H.
The outputs of the receiver buffer is sent to another buffer
called the buffered receiver data register (print D4-7). This
register is composed of four 74175 quad flip-flops. The
input data (D4-5 RD 0 H to D4-5 RD 15 H) is sent to the D
inputs of the 74175s and is clocked by D5-3 RX NPR L
from the shift control logic on the M7813 module. The
output of the buffered receiver data register (D4-7 BRD 0
H to D4-7 BRD 15 H) is sent to the Unibus data lines via
the bus selectors (prints D4-l and D4-2).

The register functions as described above for all double
characters (8 bits per character or less). The only change is
the point of entry of data into the register as determined by
bits 8-11 of the MISC register. For 7 bits per character, the
point of entry is register bit 14 via E79 decoder output f1;
for 6 bits per character, it is bit 13 via output f2, etc. For
charaers of 7 bits or less, the higher numbered stages of the
register do not affect the data where it enters the register.

4.5 M7813 MODULE (CC/BA AND SHIFT CONTROL)
For single characters (9-16 bits per character), the shift
register operates the same as described above with the
following exceptions.
1.

4.5.1 Introduction
The M78l3 module is a hex height, extended length,
module that contains several functionally separate logic
circuits. They are listed below in order of discussion.

When characters of 9-16 bits are selected, D4-3
BITS 11 (1) H is always low and D4-5 BITS 11
L is always high.
With D4-3 BITS 11 (1) H low, the strobe input
on decoder E88 is held high via gate E69 pin 8
which disables the decoder. This ineans that all
decoder outputs (fO-f7) remain high.
4-37

Character Count/Bus Address Register

Character Count/Bus Address Control Logic

Clock Loss, Register Select, and Done Control
Logic

Interrupt and Vector Control Logic

Transmitter Control Logic

Receiver Start Up and VRC Logic

Receiver Control Logic

The CC register is incremented by the CC/BA counter as
each character is transferred; therefore, it is counting
character transfers. The CC register and CC/BA counter are
16 bit devices and therefore have 2 16 or 65,536 states
(0-65,535 inclusive). It is not practical to start the counter
at 0 and increment it to the desired character count, then
stop it and use its output to perform some function. The
procedure is simplified by using the 2's complement
method. Assume that the desired character count is 220.
Convert this to binary and determine the 2's complement
of this binary value. Because the counter contains 16 bits,
this is a large negative binary number (equivalent decimal
magnitude is 65,316). This number is loaded into the
counter and it is incremented after each character is
processed. After 219 increments, the counter is at its
maximum count (65,535) which means that the 16 counter
outputs are all Is (minus 1). At this point, the counter
carry-out signal goes high. At the 220th increment, the
counter overflows (all outputs go to 0) and the carry-out
signal goes low. This positive carry-out pulse is used
throughout the logic to perform various functions. All 220
characters have been counted and the fact that the last one
has been counted is shown by the carry-out pulse. The
carry-out pulse is used by the CC/BA control logic to stop
transfers or to continue if the associated CC register
(primary or secondary) is loaded with some value, which
denotes additional characters to be transferred.

4.5.2 Character Count/Bus Address (CC/BA) Register

4.5.2.1 Functional Description - The Character Count/
Bus Address Register consists of eight registers as shown
below.
Receiver
Primary BA
Secondary BA
Primary CC
Secondary CC

Transmitter
Primary BA
Secondary BA
Primary CC
Secondary CC

These registers are 16 bits long and are composed of four
3101 64 bit read/write semiconductor (TTL) memories,
arranged in a 16 word-by-16 bit format. Only eight words
(registers) are used.
NOTE
The system memory is always referred to as the
PDP-II memory. This is where received characters and characters to be transmitted are
stored. All other use of the word memory refers
to DQ 11 hardware memories. The word register
always refers to DQ11 hardware registers.

The operation of the CC/BA register in the transmit mode
is described below in general.

A block diagram of the CC/BA register is shown in Figure
4-22. The memory is addressed by three outputs from the
CC/BA address multiplexer to select the desired register.
The inputs to this multiplexer differentiate between transmit and receive mode, CC and BA, and primary and
secondary to choose the desired register.

Assume that the selected CC and BA registers
have been loaded.

The transmit mode requests an NPR transaction.

The M7813 control logic sends the request
signals to the M7821 Interrupt Module which in
turn generates an NPR to the processor.

When the processor responds with an NPG, the
M7821 asserts MASTER A L.

MASTER A L is sent to the NPR control logic
on the M7818 module to allow the DQll to
become bus master and perform a DATI transaction to bring the first character for transmission from memory to the DQ 11. MASTER
A L also places the bus address on the Unibus
data lines for decoding by the memory during
the DATI transaction.

The BA registers are expandable to 18 bits to allow
addressing memories that contain more than 32K words.
The BA register is loaded with the address of the first
character to be transmitted (brought from PDP-II memory
to DQll) or the address of the first received character (sent
from DQ 11 to PDP-II memory). The BA register is
incremented by the CC/BA counter as each character is
transferred. This selects consecutive memory addresses as
the memory is read or written into.
The CC register is loaded by the program with the 2's
complement of the number of characters to be transferred.

4-38

[LD CC/BA SP15-0L

---aCLR

BITS 3-0

74161
CC/BA
CNTR
3-0

74S158
CCIBA
DATA
MUX
3-0

LD CC/BA CNTR(I) L - - - a LD
CLK CC/BA CNTR H

+ 3V

CLK
CNT ENB
CRY ENB

3101
CC/BA
3-0

D3HDOH

There are three
more identi c 01
circuits for
bits 7-4,11-8
and 15-12.

To ENB inputs of
CC/BA CNTR 7-4

CC/BA CYCLE H - - - - - - - '

ENB

CCIBA 3HCC/BAOH

BUS A3LBUS AOL

CC/BA ADRS 10 L

CCI BA ADRS 9 L - - - - - - '
CC/BA ADRS 8 L - - - - - - .
MASTER A H

LD 5P PORT L

r--.......~-~-......,

INI L - - - 0 CLR
lD CC/BA CNTR (1) l
ClK

eel BA e NTR H

From CO output of
CC IBA CNTR 15 -12

74161
CCI BA
CNTR
17,16

BITS 17 a 16
745158
CC/BA
DATA
MUX
17,16

l D
ClK
CNT ENB
CRY ENB
CO

ENB

3101
CC/BA
17,16

SPPORT13H
and
SPPORT14H

EE13 (1) H
and
EE14(1)H

CC/BA CYCLE H - - - - - - '

BUS A16 L
and
BUS A17 L

CCIBA ADR5 10 l

CCI BA ADRS 9 l
eC/BA ADRS 8 l
MASTER A H
11-2716

Figure 4-22 Block Diagram of CC /BA Register

MASTER A L is also sent to the CC/BA control
logic on the M7813 module to generate the
signals that increment the CC and BA registers.

The CC/BA counter is incremented after the
NPR cycle and the updated information is
written into the ee/BA registers. The BA
register now contains the address of the next
character to be transmitted from the PDP-II
memory and the CC register indicates the
number of characters remaining. The output of
the CC/BA register is sent to the bus selectors
on the M7812 module where it can be read by
the program.

ground to hold it low. The 4-bit data word is sent to inputs
DO-D3. In this application, the enabling input (ENB) is
permanently held low; therefore, for a selected word, a
write operation is performed when the write (WR) input is
low and a read operation is performed when the write input
is high. A write operation places the input data into the
selected word. In a read operation, the complement of the
information that has been written into the selected word is
non-destructively read out at the four outputs which are
MO (1 )-M3 (l). The write input is connected to DS-3 LD
CC/BA SP 15-0 L which is generated by the CC/BA
control10gic.
E7 (CC/BA DATA MUX 3-0) is a type 74S1 58 quad 2-line
to I-line multiplexer. The four outputs (FO-F3) represent
either the A word input or the B word input as selected by
the state of the select (SO) input. The strobe (STB) input is
permanently held low which enables the multiplexer: with
SO low, the A word is selected and with SO high, the B
word is selected.

4.5.2.2 Detailed Logic Description - The circuit schematic for the CC/BA register is contained in drawing
D-CS-M7813'()-1 (Rev H) sheets 3 and 4 which are
designated DS-l and DS-2.
Register Components
The CC/BA register consists of the following major
components:
a.

Five type 3101 64-bit read/write memories (E6,
E16, E26, E36, and E46) with common address
lines and enabling inputs to form a 16 word by
18-bit memory. In this application, only eight
words (registers) are used so only the three least
significant addressing inputs are used.

Five type 748158 quad 2-line to I-line multiplexer (E7, El 7, E27, E37, and E47) with a
common select signal to provide an 18-bit
mUltiplexer.

Five type 74161 synchronous 4-bit counters
(E2, E 12, E22, E32, and E42) are cascaded to
provide an 18-bit synchronous counter.

E2 (CC/BA CNTR 3-0) is a type 74161 synchronous 4-bit
counter. The MSB input is pin 6 and the LSB input is pin 3.
The MSB output is pin 11 and the LSB output is pin 14.
Both count-enable inputs (CNT EN and CRY EN) are held
high by +3 V so that the counter is permanently enabled.
The positive-going edge of DS-3 CK CC/BA CNTR H
applied to the CLK input increments or loads the counter.
Placing a low (DS-3 LD CC/BA CNTR (1) L) on the load
(LD) input disables the counter and causes the outputs to
agree with the data inputs after the next clock pulse. A low
signal at the clear (CLR) input drives all outputs low.
Counters are cascaded by connecting the carry output
(CARRY OUT) of one counter to the enabling inputs (CNT
EN and CRY EN) of the next counter. The carry output
(CO) generates a positive pulse that starts at the minus 1
count and ends at the next count which is overflow (zero).
The counter data outputs are sent to the B inputs of the
multiplexer but they are also sent to individual 7416
open-collector inverters. The outputs of the inverters are
wire-ORed to produce a Signal (DS-l CC OFLOW H) that is
used in the CC/BA control logic.

In terms of devices, a counter, multiplexer, and memory are
interconnected to accommodate 4 bits of the CC/BA
register. All but 2 bits of one group of devices (E42, E47,
and E46) are used to handle the 18 bits of the BA register.
These devices (E42, E47, and E46) are not used as part of
the CC register which requires only 16 bits. A typical4-bit
section of the CC/BA register is shown in Figure 4-23.

The output of the CC/BA register is picked off the 3101
memory and sent to the bus selectors on the M7812
module where it can be read by the program. These signals
are identified as DS-l CC/BA XX H and are also sent to one
input of the associated bus drivers. The other input of the
bus drivers is the inversion of D3-1 MASTER A L which
enables the bus address to the Unibus address lines. These
signals are identified as BUS AXX L.

E6 (CC/BA 3'()) is a type 3101 64-bit read/write semiconductor (TTL) memory organized in 16 4-bit words;
however, only 8 words are used. The 8 words (registers) are
addressed by the 3-bit binary number sent to address lines
A2, AI, and AO. Input A3 is permanently connected to

4-40

9
03-1 MASTER A L -

, - - - - - 05-1 C C OFLOW H
To Overflow
Logic

From Over flow
Logie

~--------------+----------~---1----------------------------------------'

05-3 LO CC/BA SP15-0L
6
5

MSB 11
12

MSB

3 LSB
1
05-4 INI H
E4 ">--+------0 CLR
9
05- 3 LO CCI BA -~--+__-------UJ LO
CNTR(1IL
05-3CKCC/BA-----r-----; CLK
CNTR H

LSB

10
11
13

74161
E2
CC/BA
CNTR
3-0

6
5

CNT EN

3
04 -1 01 H

1--------1 CRY EN

+3V

1 - - - - + - - - 0 5 - 1 CC/BA1 H

2-=

ENB

B2
A2
BI
A1

M3(1)
74S158
E7
CC/BA
DATA
MUX
3-0

M2(1l

3103
E6
01 CC/BA
3-0
DO

13 14

M1(O
MO(l)
A1

9
7

04-1 DO H

04-1 02 H - - _.....

15
To CNT EN
and CRY EN
inputs of
nelt counter

D4 -1 03 H - - - - - - - '

STB

SO
05-3 CC/BA
CYCLE H

05-1 CC/BA AORS 10 L
05-1 CC/BA AORS 9 L
05-1 CCI BA AORS 8 L - - - - - - '
11-27111

Figure 4-23 4-Bit Section of CC/BA Register

CC/BA Address Multiplexer
Multiplexer E43 (Figure 4-24) is used to address the eight
registers in the 3101 memories. These registers are selected
by bits 11-8 of the REG/ERR eSR as shown below.
Because only eight address bits are required, bit 11 is not
used and the MSB address input on the memory is held low
permanently.

10
0
0
0
0
1
1
1

9 8
0 0
0 1
1 0
1 1
0 0
0
1 0
1

Three of the four multiplexer outputs are used to address
the memory as shown below:
Mux
Output
Fl
F3
F2

Selected Register
RX BA Primary
RX ce Primary
TX BA Primary
TX ee Primary
RX BA Secondary
F~X CC Secondary
TX BA Secondary
TX ee Secondary

Octal No.
0

2
3
4
5
6
7

Signal Name
DS-l ee/BA ADRS 10 L
DS-l ee/BA ADRS 9 L
DS-l ee/BA ADRS 8 L

Memory
Input
A2
Al
AO (LSB)

Three inputs to the multiplexer come from bits 8,9, and 10
of the REG/ERR eSR. They are: D4-6 REG PT 9 (1) H to
input B3, D4-6 REG PT 8 (1) H to input A2, D4-6 REG PT
10 (1) H to input AI. Signal DS-3 BA L goes to input B2.
Thls Signal comes from the CC!BA control logic and is low
when the DQll is in the BA cycle. An input gating network
is connected to input Bl. Four signals are sensed by

74S158 MUX
E43
CC/BA AORS 17-0

Outputs F3. F2, and
Fl go to CC/BA
Memory address
inputs. Output is
complement of input.

10
B3
04-6 REG PT9 (1) H

11
13

05-3 TX CYCLE H

04-6 REG PT8(1) H

05-4 TXS (1) H

14
6

05- 4 RXS ( 1) H
04- 6 REG PT 10 ( 1) H
05-3 RX CYCLE H

05-1 CC/BA AORS 9 L

B2
A2
BI

05-1 CC/BA AORS 8 L

05-1 CC/BA AORS 10 L

A1
FO

05 - 3 B A L - - ' - - - - - - - - + _ _ - - - 4 AO
Secondary Register Coding
I

REG/ERRI
BITS
10

STB

SO
05-3CC/BA CYCLE (1) H

RX BA Pri

RX CC Pri

TX BA Pri

TX CC Pri

RX BA Sec

RX CC Sec

H L

TX BA Sec

TX CC Sec

High when in CCIBA
cyel e to sel ect B input.
Low selects A input.

11-2711

Figure 4-24 ee/BA Address Multiplexer (E43)

442

AND-OR-invert gate E38 whose output is then inverted by
EI3 and sent to mux input BI. Two signals indicate
whether the transmit or receive mode is enabled. Signal
DS-3 TX CYCLE H is high if the transmitter requested the
NPR. DS-3 RX CYCLE H is high if the receiver requested
the NPR. Two signals indicate whether the primary or
secondary register for the selected mode is enabled and
they are a function of TX/RX NPR selection. Signal DS4
TX S (I) H is high if the secondary register is enabled in the
transmit mode and signal DS4 RX S (1) H is high if the
secondary register is enabled in the receive mode.

The following discussion covers loading and incrementing
the CC/BA register. Several signals from the CC/BA control
logic (print DS-3) are used but are not explained in detail.
They are covered in the subsequent discussion of the
CC/BA con trollogic.

Loading the BA Register
Assume that it is desired to load the starting address in the
TX BA primary register (address 28)'
The DQ II is not yet in the CC/BA cycle.

In the CC/BA cycle mode (mux B input selected), the
following signals control the CC/BA memory address inputs
(A2, Al and AO) listed below:

DS-3 CC/BA CYCLE H is low which selects the
A input of the CC/BA ADRS mux (E43).
Inputs A3, A2, and Al (LSB) represent 28
because these inputs come from bits 10,9, and
8, respectively, of the REG/ERR CSR which
has selected the TX BA primary register. The
output of mux E43 has therefore selected the
16-bit word in the 3101 memory that represents the TX BA primary register.

DS-3 CC/BA CYCLE H, which is low, also

Input A2 - controlled by inverted output of E38 (function
of RX/TX cycle and primary/secondary selection)

Input Ai - controlled by D4-6 REG PT 9 (I) H
Input AO (LSB) - controlled by DS-3 BA L
As an example, assume that the DQII is in the CC/BA
cyclc which means that D5-3 CC/BA CYCLE (1) II is high.
This selects the B input of multiplexer E43. Assume also
that it is desired to select the RX BA secondary register.
This register has an octal designation of 4 as determined by
REG/ERR bits 10, 9, and 8. The state of the B inputs of
mux E43 should be as follows:
BI=I=H

B3=O=L

__ 1 __ ",,-_

~tat:~L~

...... 1 __

...

..L

_r11

,..,,.,/n.a

T""'Iro.""""'" ...... r.T

LIlt: .f\. InpUL Ul Ul~ \"'\"'/J).f\. Ul\ll\ IVIUA.

The A input represents the 16-bit or 18-bit
address, via Unibus data lines, that the program
desires to load into the TX BA primary register.
The mux is permanently enabled so this address
appears at the data input of the memory.
3.

B2=O=L (LSB)

Input Bi - Signal DS-3 RX CYCLE H is high because the
DQII is in the receive mode. Signal DS4 RX S (1) H is
high because the RX BA secondary register is selected. The
output (pin 8) of E38 is therefore low. It is inverted by EI3
which puts a high on input BI of mux E43.

REG/ERR bits 11-8 are set to give 2 8 • These
bits, via the register selection logic, assert DS4
LD CC/BA L as a pulse, which in tum drives
DS-3 LD CC/BA SP IS-O L low. This signal
goes to the write (WR) input of the memory.
When WR is low, the input data (starting bus
address) is written into the selected word (TX
BA primary register).

Input B3 - Signal DS-3 TX CYCLE H is low which puts a
If extended PDP-II memory is used, 18 address
bits are required. The program sets REG/ERR
register bit 12 which allows DS-3 LD SP PORT
L to be asserted and write the two additional
bits (16 and 17) into the selected BA register.

low on input B3 of mux E43.

Input B2 - Signal DS-3 BA L is low because the DQ II is in
the BA cycle which puts a low on input B2 of mux E43.
The B inputs of mux E43 are set up to select the RX BA
secondary register and the complement of the B inputs
appear at the mux outputs. This inversion of the B inputs
merely means that the physical location of the RX BA
secondary register is word 3. Its address, as selected by
REG/ERR bits 10, 9 and 8, is always 4. The fact that the
register address and the address of the word in memory
where it is stored do not coincide is of no consequence.

443

At the end of the DS4 LD CC BA L pulse,
signal DS-3 LD CC/BA SP IS-O L goes high
which places the complement of the contents
of the TX BA primary register at the memory
output. This output, which represents the bus
address, is enabled to the Unibus via bus
drivers, by the inversion of D3-1 MASTER A L.

Loading the ee Register
Assume that it is desired to load the character count in the
TX CC primary register (address 3 8 ), The DQll is in the
transmit mode but is not yet in the CC/BA cycle.

counter input-preset feature. When the counter is subsequently clocked, the BA register input is incremented by
one again which results in an increment by two. This occurs
only in single-character operation.

The sequence for loading the TX CC primary register is the
same as that described above for loading the TX BA
primary register with the following exceptions:

The logic network (print D5-1) consists of AND-OR-invert
gate E8, negated-input OR gate E9 and inverter E13. The 0
output of the CC ODD flip-flop is always high during the
BA cycle. This high is sent to pins 1 and 10 of E8. Pin 13 of
E8 is connected to D5-3 BA H and is high during the BA
cycle. With pins 1 and 13 high, one input to the NOR
section of E8 is always high. Thus, the output (pin 8) is
held low despite the state of the other input which is the
ANDing of pins 9 and 10. This means that signal D4-3 BITS
11 (1) H, which goes to E8 pin 9, has no effect on the
output of E8 during a BA cycle. Signal D4-3 BITS 11 (1) H
determines whether single or double characters are to be
processed.

The A3, A2, and Al inputs of the CC/BA
ADRS MUX (E43) represent 3 8 which is the
octal address of the TX CC primary register.

The data on the A input of the CC/BA DATA
MUX is the 2's complement of the character
count to be loaded into the register.

The output of the CC register (D5-1 CC/BA 0 H-15 H) is
sent to the bus selectors on the M7812 module where it can
be read by the program.

The output (pin 8) of E8 is sent to pin 10 of negated-input
OR gate E9. This low signal drives the output (pin 8) of E9
high and it is sent to the LSB input (pin 3) of counter E2.
The other input (pin 9) of E9 comes from the LSB of the
BA register (E6 pin 9). The state of this input is irrelevant.
The 0 (low) sensed at the LSB of the BA register has been
fed back to the LSB of the counter as a 1 (high).

Incrementing the BA Register
Transfers to and from the memory are accomplished on a
word basis only. Word addresses occur on even boundaries;
that is, the last octal digit is 0, 2, 4, or 6. This means that
the least significant bit of a word address is always O.

The incrementing (CC/BA register updating) cycle first
requires that the output of the register be loaded into the
counter. Then the counter is clocked once. This sequence is
controlled by the CCIBA control logic (print D5-3). Signal
D5-3 LD CC/BA CNTR (1) L is connected to the load (ill)
input of the counter. When it goes low, the information at
the input is transferred to the output at the next clock
pulse. In this case, the LSB of the counter goes from a 0 to
a 1. During this load cycle, the 0 from the LSB of the BA
register has been forced into the counter LSB as a 1. The
count has been increased by one. Now, signal D5~3 CK
CC/BA CNTR H again goes high and clocks the counter
which increments it by one. The net effect is that the bus
address has been incremented by two. This updated address
is written into the BA register and is put on the Unibus
address lines during the next NPR cycle.

Assume that the starting address has been loaded into the
TX BA primary register. It is sent out to the Unibus and the
memory responds by sending the word located at that
address to the DQll. Mter the word has been processed,
another NPR cycle occurs which requests the next
successive memory word. Remember that the word can
contain one character having 9-16 bits (single-character
operation) or two characters having 8 bits or less (doublecharacter operation). This information is vital to the CC
register but not to the BA register because it deals in word
addresses and is looking only for the next successive word
address. In double-character operation, the BA register is
incremented by one by each character. Since this occurs
twice during the NPR cycle, the next address is even.
The output of the BA register from the CC/BA memory is
fed back to the input of the Ce/BA counter. The output of
the counter is sent via the B input of the CC/BA data mux
to the eCIBA memory input. Once each NPR cycle, the
counter is clocked (incremented) and the updated bus
address is sent to the CCIBA memory where it is written
into the BA register.

The LSB counter bit is not fed back directly to the CC/BA
mux in put as all other bits are; rather, it passes through a
small logic network consisting of two E13 inverters and an
AND-OR-invert gate (E8). This gate provides two paths for
restoring or updating the CC/BA register. The path from
the ODD CNT BYPASS flip-flop is used only for incrementing the CC register by two on an odd count. The path
from the LSB output of the counter is used for incrementing the ec register in all other situations plus
incrementing the BA register.

Clocking the counter only increments its output by one;
however, a logic network connected to the LSB input (bit
0) allows the count to be increased by one using the

444

Incrementing the CC Register
The CC register handles single or double characters and can
be loaded with odd or even counts. As a result, it has the
capability of being incremented by one or two for both odd
and even counts.
In addition to the logic mentioned in the above discussion
of incrementing the BA register, two additional flip-flops
are used in the CC register incrementing and overflow logic.
They are the CC ODD and ODD CNT BYPASS flip-flops
(both labeled E3).

The LSB output of the counter is also low
(even count). This low is sent to E8 pin 5. Both
OR inputs of this gate are low so its output (pin
6) is driven high. This signal is inverted by E13
and sent as a low to input B2 ofCC/BA DATA
MUXE7.

The next event in the sequence is the loading of
the counter, which is performed when D5-3 LD
CC/BA CNTR (1) L goes low and D5-3 CK
CC/BA CNTR H goes high. The CC count does
not change because the LSB is low (0) and a
low (0) is trying to be loaded in.

Now D5-3 CK CCIBA CNTR H goes high again
which clocks the counter and increments it by
one. The LSB output goes high which drives E8
pin 6 low. This signal is inverted by E13 and
sent as a high to the B2 input of mux E7 along
with the other 15 bits of the counter which
represent the updated character count (incremented by one from the previous count).

10.

During the sequence, the CC ODD and ODD

The following examples explain how the CC register is
incremented.
The first example assumes that the CC register shows an
even count, incrementing does not cause overflow, and
single characters are being handled. The desired result is
incrementation by one to produce an odd count.
At the start of the sequence, the assumptions cause the
following results:
1.

The even count is reflected as a low (0) from
th~

"'...... '-'

T <;!R I'\~ th~ ,..,.. "~n1cot",, .. f"ru::• ...; ... 0'\ .... ""; ... " f'""A
~.....,~ V.L
"..1..1.'" """'-" .I.'"'frL.J""".I. \LJV p,LU. . / J U\Jll.l.6 .L""u.

('NT
~

No overflow is to be produced, so the CC ODD
flip-flop is cleared and remains so during the
sequence. The 0 output of this flip-flop puts a
high on pins 10 and 1 of gate E8.

Single characters are being handled so 04-3
BITS 11 (1) H, which is connected to E8 pin 9,
is low.

This is a CC cycle so D5-3 BA H, which is
connected to E8 pin 13, is low.

The conditions in step 4 drive the output (pin
8) of E8 high. This signal is sent to E8 pin 4
and is inverted by E13 and sent as a low to E8
pin 3. This sets up the restore path for bit 0
from the counter not the ODD CNT BYPASS
flip-flop.

•••

RVPA~C;:
~

••

~&~~

f1;n..f1nnCl
~~t'

&&~t'~

~rP

('In('1r~ti

.u _ _

&~_&~-~.

Rnth

~~'U

flip-flops started in the cleared state and are
clocked with their D-inputs low so they do not
change state and have no effect on the incrementing operation.

back to pin 13 of inverter E 13 and the D input
of the ODD CNT BYPASS flip-flop.

The second example assumes that the CC register shows an
odd count, incrementing does not cause overflow, and
single characters are being handled. The desired result is
incrementation by one to produce an even count. This
example proceeds like example 1 except that the counter
LSB input and output are high. When the counter is loaded,
the count does not change because the LSB is high (1) and
a high (1) is trying to be loaded in. When the counter is
clocked, it is incremented by one which drives the LSB
output low (0).
The third example assumes that the CC register shows an
even count, incrementing does not cause overflow, and
double characters are being handled. The desired result is
incrementation by two to produce the next even count.
This example is similar to incrementing the BA register. The
LSB output of the counter is low (0) but the low LSB
output from the CC register is fed back to the counter LSB
input as a high (1). When the counter is loaded, a high is
forced into the LSB which is an increment by one. When
the counter is clocked, it is incremented again. The CC
count, which has been incremented by two, is restored in
the CC register.

The high output (pin 8) of E8 also goes to pin
10 of E9. The high from pin 12 of inverter E13
goes to the other input (pin 9) of E9. This
drives the output (pin 8) of E9 low which
represents an even count (0) to the LSB input
of counter E22.

4-45

The fourth example assumes that the CC register shows an
odd count, incrementing does not cause overflow, and
double characters are being handled. The desired result is
incrementation by two to produce the next odd count. This
example is similar to example 3 except that the counter
LSB input and output are high. When the counter is loaded,
the count does not change. 'When the counter is clocked, it
is incremented by one (LSB output goes low); however, this
low does not get through ES and E13 to the mux. The
ODD CNT BYPASS flip-flop is clocked and it is set because
its D input is high. The 1 output of the flip-flop, which is
high, gets through ES and E13 to the mux. The character
count has been incremented by two which is the next odd
count as desired.

Whenever bit 0 of the CC register is 1, the D input of the
ODD CNT BYPASS flip-flop is high. When this flip-flop is
clocked during the increment sequence, its l-output (which
is high) is sent to pin 4 of AND gate E33. The other input
(pin 5) of this gate is D5-2 CC/BA CARRY 10-0 H. This
signal comes from the carry output of bit 15 of the counter
(E32 pin 15 on print DS-2). It goes high when the counter
reaches minus 1 (all Is). This drives the output (pin 6) of
E33 high so the CC ODD flip-flop is set when it is clocked
by D5-3 TEST ODD CNT H. This sets up the restore logic
path for bit 0 from the counter.
Assuming that the counter is at minus 1 (all Is), all outputs
go to 0 ( overflow) on the next clock pulse. All the
wire-ORed inverter inputs go low and D5-1 CC OFLOW H
is asserted and sent to the CC/BA control logic.

Counter Overflow Detection Logic
When the counter overflows in the CC mode, its outputs go
from all Is (which is a count of minus 1) to alIOs. This
indicates that the character count for the selected CC
register is now zero. The next step is to look at the
associated register (primary or secondary) to see if it
contains anything. If it does, the character count is picked
up from the associated register. The overflow logic
generates D5-1 CC OFLOW H which is used in the CC/BA
control logic (print D5-3) to test the associated register.

When the CC ODD flip-flop is set, it asserts D5-1 CC ODD
(1) H at its 1 output. This signal is sent to the transmitter
control logic (print D5-6) and the receiver control logic
(print D5-S).

CC/BA counter output bits 0-15 are sent to type 7416
bare collector inverters. All bits except bit 0 go directly to
the inverter in puts. Bit 0 goes through the restore logic path
before reaching its associated 7416 inverter. All 16 inverter
outputs are wire-ORed and this point is D5-1 CC OFLOW
H. All inverter inputs must be 0 simultaneously to assert
D5-1 CC OFLOW H.

4.5.3.1 Functional Description - A simplified block diagram of the CC/BA control logic is shown in Figure 4-25.
The primary purpose of this logic is to control the updating
of the CC/BA register following an NPR cycle. Normally, it
loads and increments the CC register, loads and increments
the BA register, then shuts down until it is started again
during the next NPR cycle.

4.5.3 Character Count/Bus Address Control Logic

LD CC/BA CNTR (1) L
BA H

r----+ TEST NEXT CC (1) H
~CC/BA

CYCLE H

CC OFLOW H
CC/BA
CONTROL
LOGIC

MASTER A L

L
--

I
CLOCKS

LD EXTITRANS H ----.
L D CC/BA L ----.

OUTPUT
GATING

CC/BA CYCLE H
CNTR LD PULSE H
TEST ODD CNT H
LD CC/BA SP 15-0 L
LD SP PORT L

CLK CC/BA CNTR H

11-2710

Figure 4-25 Block Diagram of the CC/BA Control Logic
4-46

The normal operating sequence is altered if an overflow is
detected when the CC register is incremented. Overflow
occurs when the CC/BA counter reaches a count of 0 for
the selected CC register. This means that the selected CC
register reads 0 and the last character has been processed.
This is decision time for the CC/BA control logic. The
associated CC register must be tested to see if it contains
additional characters. If it does, control is switched to the
associated register and additional characters are processed
during subsequent NPR cycles. If it is empty, there are no
more characters to be processed. The appropriate DONE
flag is set and the GO bit is cleared.

used in various places in the M7813, M7812, and M7818
modules. This logic is inhibited while the CC/BA register is
being updated.

4.5.3.2 Detailed Logic Description - The circuit schematic for the CC/BA control logic is contained in drawing
D-CS-M7813-O-1 sheet 5 which is designated D5-3.
The major element of the CC/BA updating logic is a string
of five D-type flip-flops that control the loading and
incrementing sequence of the CC register and BA register.
They are: EN START, LD CC/BA CNTR, INCR CC/BA
CNTR, CC/BA SEL, and CC/BA CYCLE. Two additional
D-type flip-flops (OFLOW HOLD and TEST NEXT CC) are
used when overflow is detected. Two one-shot clocks are
used: CLK clocks the CC/BA counter and MODE SEL
clocks all the sequence flip-flops except CC/BA SEL.

The overflow is detected when the CC register is incremented and the overflow indication is held until the BA
register has been loaded and incremented. Another CC load
operation is started and when it is completed the sequence
is shut down until the next NPR cycle. If the associated CC
register indicates 0, no more characters are processed. If the
associated CC register contains a character count, additional
characters are processed starting with the next NPR cycle.

Before discussing the CC/BA register loading and incrementing sequence, the operation of the clock is described.
Two 74123 retriggerable monostable multivibrators (oneshots) are connected back-to-back to form an oscillator
(Figure 4-26). The 1 output of each is used to trigger the
other. Two qualifying signals are required to start the clock
and it is self-sustaining thereafter.

Another section of the CC/BA control logic responds to the
NPR request signals from the transmit control logic and
receive control logic. It generates a group of signals that are

Posi tive transition initially
triggers MODE SEL one-shot
with pin 9 low. With MASTER
A L high, continued triggering
is caused by negative
transition on pin 9.

Clock for EN START, LD CC/BA CNTR,
INCR CCI BA CNTR and CC/BA
CYCLE fl ip flops. Negative transition
triggers CLK one-shot.

From 1 output of
CC/BA CYCLE flipflop.
Must be high to trigger.

03-1 MASTER AL

S
EIO
74123 1t--~---a
MODE
.JL
SEL
7Sns

t-1_3--r-_ _~ DS-3 ClK CC/BA CNTR H
El0
74123
CLK

..r-t.
SOns

Clock for
CC/BA
counter

74193
TRUTH TABLE
MASTER A l
MODE SEl
1-output _ _ _ __
ClK
1-output _ _ _ _ _ _~

l
L

t n

n..

NOTES:
1. H = High level. L = Low level.
Both steady state.
2. t Transition from low
to high level.
3 . .j, Transition from high
to low level.
4. X = Irrelevant (any input
including transition.)
5. JL = One positive pulse.
11- 2714

Figure 4-26 Clocks for the CC/BA Control Logic
4-47

At the start of the NPR cycle, D3-1 MASTER A L goes
low. Thls inhibits the MODE SEL one-shot; however, it sets
the CCjBA cycle flip-flop which triggers the CLK one-shot.
One pulse is produced and the CLK one-shot returns to
rest; this pulse does nothing. Pin 2 of the CLK one-shot
remains high which means that a negative transition at pin 1
will trigger the eLK one-shot. The low from the 1 output
(pin 13) of the CLK one-shot is fed back to pin 9 of the
MODE SEL one-shot. Now, a positive transition at pin 10
of the MODE SEL one-shot will trigger it.

the devices, the MODE SEL one-shot generates 75 ns
positive pulses every 125 ns and the CLK one-shot
generates 50 ns positive pulses every 125 ns.
Updating the CCjBA Register (No Overflow)
Thls discussion covers the operation of the CC/BA control
logic during the sequence that places the bus address on the
Unibus and then updates the CC register and BA register
without overflow. Refer to print D5-3 and the timing
diagram in Figure 4-27.
1.

At the end of the NPR cycle, D3-1 MASTER A L goes high
and triggers the MODE SEL one-shot which generates a
positive pulse at its 1 output. \\11en this pulse times out, its
nega tive-going trailing edge triggers the CLK one-shot which
generates a positive pulse at its 1 output. When the CLK
pulse times out, its negative-going trailing edge triggers the
MODE SEL one-shot again. The clocks are self-sustaining as
long as D3-1 MASTER A L remains high and the CCjBA
CYCLE flip-flop remains set. Ignoring propagation delays in

MASTER A l

Assume that the starting bus address has been
loaded into the selected BA register and this
address appears at the input of the 8881 bus
drivers. D3-1 MASTER A L is hi&~, all CC/BA
control flip-flops are cleared, and both oneshots are at rest. D5-3 CC/BA CYCLE H is low
which means that the A inputs of the CC/BA
data mux and address mux are selected. D5-3
LD CC/BA SP 15-0 L is high which means that
the CC/BA memory is in the read mode.

---,'-_ _ _ _...J

,..--""

*'*' ClK

___ JI C 5 I'- _ _ __

** MODE SEl

.----,
I
I

'-_ oJ M6

L_______ _

BAH ~

* EN START ~
••

'----------------- - - - - - --r-------~~'~A ~~, ..--...J~i-------------'
I

\,0\,01 C~

;:)1:.1..

t: :E:' ~n:
r - ~C-

Shuts off ClK and MODE
i
o.:erflOw occurs

* CCiBA CYCLE ~

\---CC CYCle--...44I.--SA Cycle--4

* lD CC/SA
*' INCR CC/SA CNTR
NOTES
*Flip-Flop 1 Output
**One-Shot 1 Output

Test CC Reg for Overflow

==:4

Restore period
for CC Cycle

't-__

..J

- - --

L______ _

~ Restore period
. ~
\....i Icontinues
If overfl:w has occured,
for one more
I

for SA Cycle

MODE SEl pulse and then
clocks are stopped. logic
on print 05-4 sets proper
DONE bit and clears GO
if associated CC Register
reads O(empty).
11-2713

Figure 4-27 Timing Diagram for CC/BA Control Logic

4-48

D3-1 MASTER A L goes low and enables the
current bus address to the Unibus. The CC/BA
control flip-flops respond as follows:

When the MODE SEL one-shot times out, it
triggers the CLK one-shot which generates pulse
C1. This asserts D5-3 CLK CC/BA CNTR H.
The positive transition of this signal clocks the
CC/BA counter which loads in the character
count. Pulse Cl also drives D5-3 CNTR LD
PULSE H high which clocks the ODD CNT
BYPASS flip-flop in the CC/BA register logic.

INCR CC/BA CNTR - Remains cleared. Dinput is low.

When pulse Cl times out, it triggers the MODE
SEL one-shot which generates pulse M2. The
CC/BA control flip-flops respond as follows:

CC/BA SEL - Set via preset input. D-input is
low.

LD CC/BA CNTR - Cleared. D-input is high.

EN START - Set via preset input. D-input is
low (permanently connected to ground).
LD CC/BA CNTR - Remains cleared. D-input
is high.

INCR CC/BA CNTR - Set. D-input is low.
Drives D5-3 TEST ODD CNT H high at E5 pin
6 which clocks the CC ODD flip-flop in the
CC/BA register logic.

CC/BA CYCLE H - Set via preset input. Dinput is high. Drives D5-3 CC/BA CYCLE H
high which selects the B input of the data and
address multiplexers.

CC/BA SEL - Remains set. D-input is low.
3.

D3-1 MASTER A L goes high at the end of the
NPR cycle which drives D5-3 BA H low to
indicate that the logic has entered the CC
portion of the update cycle. The MODE SEL
one-shot is triggered and it generates pulse Ml
{Figure 4-26}. The CC/BA control flip-flops
respond as follows:

CC/BA CYCLE - Remains set. D-input is high.
This step describes how the logic is set up for
subsequent incrementing of the character
count.

EN START - Cleared {stays cleared through
the end of the updating cycle}.

When pulse M2 times out, it triggers the CLK
one-shot which generates pulse C2. This asserts
D5-3 CLK CC/BA CNTR H which clocks the
CC/BA counter and increments it. Pulse C2 also
drives D5-3 LD CC/BA SP 15-0 L low which
puts the CC/BA memory in the write mode.
The CC register now has been loaded and
incremented; it contains the updated character
count.

When pulse C2 times out, it triggers the MODE
SEL one-shot which generates pulse M3. The
CC/BA control flip-flops respond as follows:

LD CC/BA CNTR - Set. D-input is low. Asserts
D5-3 LD CC/BA CNTR {I} L that goes to the
load input of the CC/BA counter. When the
counter is subsequently clocked with the load
input low, the counter outputs agree with the
inputs; that is, the CC register output from the
memory is loaded into the counter.
INCR CC/BA CNTR - Remains cleared. Dinput is high.
CC/BA SEL - Remains set. D-input is high.
CC/BA CYCLE - Remains set. D-input is high.

LD CC/BA CNTR - Set. D-input is low. Asserts
D5-3 LD CC/BA CNTR (l) L to enable the
CC/BA counter load input.

This step describes how the logic is set up for
subsequent loading of the character count into
the coun ter.

INCR CC/BA CNTR - Cleared. D-input is high.
When this flip-flop is cleared, it clocks the
CC/BA SEL flip-flop.

4-49

[NCR CC/BA CNTR - Cleared. D-input is high.

CC/BA SEL - Cleared. D-input is high. When
CC/BA SEL is cleared, it asserts DS-3 BA H
which indicates the start of the BA portion of
the updating sequence.

CC/BA SEL - Set. D-input is low.
CC/BA CYCLE - Cleared. D-input is high.

CC/BA CYCLE - Remains set. D-input is high.
Updating the CC/BA Register (Overflow Occurs)
Two additional flip-flops (OF LOW HOLD and TEST NEXT
CC) are used to alter the CC/BA updating cycle if an
overflow is detected when the CC register is incremented.

This step describes how the logic is set up for
subsequent loading of the bus address into the
counter.
8.

When pulse M3 times out, it triggers the CLK
one-shot which generates pulse C3. This asserts
DS-3 CLK CC/BA CNTR H which clocks the
CC/BA counter and loads in the bus address.
Pulse C3 also drives DS-3 CNTR LD PULSE H
high which clocks the ODD CNT BYPASS
flip-flop in the CC/BA register logic.

At the start of the updating cycle, both flip-flops are
cleared. The clock signal for these flip-flops comes from the
o output of the INCR CC/BA CNTR flip-flops. The positive
transition that is required for clocking is generated when
the INCR CCjBA CNIR flip-flops go from the set state to
the clear state. This occurs first at the leading edge of pulse
M3. Assuming that an overflow has occurred, the D-input
of OFLOW HOLD is high so the flip-flop is set. The TEST
NEXT CC flip-flop does not change state (remains cleared)
because its D-input was low at the time it was clocked.
When OFLOW HOLD is set, it puts a high on pin 2 of NOR
gate E2S and puts a high on the D-input of the TEST
NEXT CC flip-flop. At this point, this is all that happens.
The indication of an overflow has been recorded and saved
and the logic, via E2S pin 2, has been conditioned so that
pulse MS does not disable the clocks. No further. action is
taken, due to the overflow, until the BA register has been
loaded and incremented.

When pulse C3 times out, it triggers the MODE
SEL one-shot which generates pulse M4. The
CC/BA control flip-flops respond as follows:

LD CC/BA CNTR - Cleared. D-input is high.
[NCR CC/BA CNTR - Set. D-input is low.
CC/BA SEL - Remains cleared. D-input is high.
CC/BA CYCLE - Remains set. D-input is now
low.

When pulse MS occurs, the OFLOW HOLD flip-flop is
cleared. Now, the logic via E2S pin 2 has been conditioned
so that the next MODE SEL pulse (M6) disables the clocks.
The TEST NEXT CC flip-flop is set which asserts DS-3
TEST NEXT CC (1) H. This signal is sent to the logic on
print DS-4 to generate the signal that switches the
addressing from the current CC register to the associated
CC register (primary to secondary or secondary to
primary).

This step describes how the logic is set up for
subsequent incrementing of the bus address.

10.

11.

When pulse M4 times out, it triggers the CLK
one-shot which generates pulse C4. This asserts
DS-3 CLK CC/BA CNTR H which clocks the
CCjBA counter and increments it. Pulse C4 also
drives DS-3 LD CC/BA SP 15-0 L low which
puts the CC/BA memory in the write mode.
The BA register now has been loaded and
incremented; it contains the next bus address to
be used.

The logic IS m the CC load cycle. When pulse CS is
generated, the CC/BA counter is loaded with the contents
of the associated CC register.

When pulse C4 times out, it triggers the MODE
SEL one-shot which generates pulse MS. This
pulse clocks the CC/BA CYCLE flip-flop which
clears it and disables both clocks (CLK and
MODE SEL). This ends the updating cycle. The
other flip-flops respond as follows:

When pulse M6 occurs, the CC/BA CYCLE flip-flop is
cleared which disables the clocks (CLK and MODE SEL).
The contents of the associated CC register have been loaded
but the logic needs to perform two more functions.
1.

LD CC/BA CNTR - Set. D-input is low.

4-50

Generate the appropriate DONE flag to indicate
that it is fmished with the first selected CC
register.

Signal DS-3 NPR EN (1) H must be cleared and then
reasserted before another NPR request can be honored by
the M7821 module. This signal is cleared by D6-2 END
NPR CYCLE (1) L which goes low at the end of the NPR
cycle and directly sets the NPR EN flip-flop which drives
DS-3 NPR EN (1) H low.

Check the contents of the next CC register. If it
contains a count, pick it up at the next NPR
cycle and continue to process characters. If it is
0, reset GO to shut down because there are no
more characters to process.

When the CC/BA CYCLE flip-flop was cleared by pulse M6,
the low at its 1 output directly clears the TEST NEXT CC
flip-flop. The 0 output of this flip-flop is sent to a pulse
generator (Figure 4-28) which generates a positive pulse of
100 ns. This pulse (DS-3 NEXT CC PULSE H) is sent to the
logic on print DS4 to set the appropriate DONE flag. If the
associated CC register is empty, GO is reset and the unit
shuts down.

Two NPR request signals are sensed by this logic: DS-6 TX
NPR RQ (1) L from the transmit control logic and DS-8
RX NPR RQ (1) L from the receive control logic. A request
signal is generated when the associated NPR RQ flip-flop
(TX Of RX) is set. Both request signals are sent to
negated-input OR gate E20. When either signal is asserted,
DS-3 NPR RQ H is generated at the output (pin 3) of E20.
This signal is sent to the M7821 Interrupt Module to
request the NPR, providing DS-3 NPR EN (1) H is asserted.
Signal DS-8 RX NPR RQ (1) L is also sent to the D-input of
the TX/RX CYCLE flip-flop. The clock Signal for this
flip-flop is the ANDing of DS-3 NPR RQ H and the 0
output of the CC/BA CYCLE flip-flop at AND gate ES.

NPR Request Logic
At the top of print DS-3 there is a logic network that
responds to the NPR request signals from the receive and
transmit control logic and generates several signals that are
used throughout the DQ 11.
The NPR EN flip-flop asserts DS-3 NPR EN (1) H when the
CC/BA control logic is not in the CC/BA update cycle.
Signal DS-3 NPR EN (1) H comes from the 0 output of the
flip-flop and goes to the NPR control section of the M7821
Interrupt Module. This signal must be high for the M7821
to respond to an NPR request from the receive or transmit
control logic. The D input of the NPR EN flip-flop is
permanently connected to ground so when it is clocked it is
cleared which asserts DS-3 NPR EN (1) H. The clocking
Signal comes from the 0 output of the CC/BA CYCLE
flip-flop. The required positive transition occurs when the
CC/BA CYCLE flip-flop goes from the set to the cleared
state. This happens at the end of the CC/BA updating cycle
so now the M7821 is ready to respond to an NPR request.

For example, assume that the transmit control logic is
requesting the NPR. Signal DS-6 TX NPR RQ (1) L is low
and it drives pin 1 of ES high. This logic will not generate
any signals until the CC/BA updating cycle is complete
which is indicated when the CC/BA CYCLE flip-flop is
cleared. When it is cleared, pin 2 of ES goes high which
drives its output (pin 3) high. This positive transition is
delayed by R4, CI09 and ClIO and then clocks the TX/RX
CYCLE flip-flop.
The RX control logic is not requesting the NPR so DS-8 RX
NPR (1) L is high, which puts a high on the D-input of the
TX/RX CYCLE flip-flop, so that it sets and asserts DS-3 TX
CYCLEH.

TEST NEXTCC(O)H-..--------.....

05-3 NEXT CC PULSE H
R53
*,C114

100ns positive pulse
oeneroted at C when
A ooes high.

A---f.L---

--+! I+-- 100ns Delay
I

---II

"",---I

11-2712

Figure 4-28 Pulse Generator In Overflow Detection Logic
4-51

the receive and transmit clocks. If either clock signal is lost,
the logic generates a signal (RX CK LOSS L or TX CK
LOSS L) that is used to set the appropriate flag in the
REG/ERR CSR (bit 1 for RX and bit 0 for TX).

The delay allows settling time for the CC/BA control logic
before initiating another NPR sequence. Signal D5-3 TX
CYCLE H is sent to the CC/BA addressing mux (print
D5-1), the DONE logic (print D5-4), the TX control logic
(print D5-6) and the REG/ERR register (print D4-6) on the
M7812 module.

In addition, the RX clock loss logic turns on the OQll
internal RC clock which continues the shifting operation
until the sequence is ended normally at the end of the NPR
cycle. Although received data is lost when the RX clock is
lost, this method can save the good data that was shifted in
before the RX clock loss.

When the NPR cycle is complete, D6-2 END NPR CYCLE
(1) L is asserted. This low signal is sent to E30 pin 6 where
it is ANDed with the low from the TX/RX CYCLE flip-flop
at the other input (pin 5) of E30. This drives the output
(pin 4) of E30 high to assert D5-3 TX NPR DONE H. This
signal is sent to the TX control logic (print D5-6) where it
clears the TX NPR RQ flip-flop and drives D5-6 TX NPR
RQ (1) L high. The transmit control logic no longer
requests the NPR. At the same time, D6-2 END NPR
CYCLE (1) L directly sets the NPR EN flip-flop which
clears D5-3 NPR EN (1) H.

Signal TEST LOOP (1) H is used to disable the clock loss
logic when the OQ 11 is operating in the test loop mode
during servicing.
The register select logic decodes signals from the MI05
Address Module (OUT HIGH H, OUT LOW H, SEL 4 H,
and SEL 6 H) and bits 8-11 from the REG/ERR CSR
(REG PT 8 (1) H-REG PT 11 (1) H), and generates the
following signals:

If the receive control logic is requesting the NPR, the
sequence is identical, with the following exceptions. The
D-input of the RX/TX CYCLE flip-flop is low because D5-8
RX NPR RQ (1) L is low. When clocked, the flip-flop is
cleared and D5-3 RX CYCLE H is asserted. This signal is
sent to the CC/BA addressing mux (print D5-l), the DONE
logic (print D5-4), the RX control logic (print D5-8), the
REG/ERR register (print D4-6) on the M7812 module, and
the NPR control logic (print D6-2) on the M7818 module.
When the NPR cycle is complete, signal D5-3 RX NPR
DONE H is asserted. This signal is sent to the RX control
logic (print D5-8) where it clears the RX NPR RQ flip-flop
and drives D5-8 RX NPR RQ (1) L high.
In addition, during a RX NPR sequence, D5-3 RX CYCLE
H is used to generate two other signals. When the CC/BA
logic is not in the updating cycle: D3-1 MASTER A L is
low. It is inverted by E15 pin 6 and is ANOed with 05-3
RX CYCLE H to generate 05-3 RX NPR L. This Signal
clocks the buffered receiver data register (print D4-7) on
the M7812 module and is used in the register selection logic
(print D4-3) on the M7812 module. These two signals are
also ANDed at bus driver E41 to assert BUS C1 L on the
Unibus. This signal is asserted when the DQll becomes bus
master and performs a DATa transaction to put a received
character into memory.

Load signal for the MISC register (LD MISC L).

Load signal for the SYNC register (LD SYNC
L).

Load signal for the REG/ERR CSR high byte
(LO PTEE H) and low byte (LD ERR H).

LO CC/BA L that provides read/write control
for bits 0-15 of the CC/BA memory.

LD EXT/TRANS H that provides read/write
control for bits 16 and 17 of the CC/BA
memory.

WEN (1) H which is the flag for bit 12 of the
REG/ERR CSR.

The DONE control logic generates the signals that clear the
RX and TX GO bits, RX and TX primary and secondary
register DONE bits, and provides signals (TXS (1) Hand
RXS (1) H) to the CC/BA addressing mux to select the
proper CC and BA registers. The logic has the capability to
pick the correct address and DONE bit when the CC
overflow causes a CC register to switch to primary or
secondary.

4.5.4 Clock Loss, Register Select, and Done Control Logic
4.5.4.1 Functional Description - A Simplified block diagram of the clock loss, register select, and DONE control
logic is shown in Figure 4-29. The clock loss logic monitors

Bit 5 (MASTER CLEAR) of the MISC register is also

shown.

4-52

SEL 6 LD L

OUT LOW H

TXGO(1)H
GATING

SEL 6 H

REG PT
11 (1)H

•

REG PT10 (1) H
REG PT9(l)H

7442
REG PT
WRITE
10-17
DCDR

-LD MISC L

TXCLOCKH

TX CLOCK
LOSS LOGIC

1_ TX CK LOSSL

TEST LOOP( 1) H
-

LD SYNCL

REG PTa(1) H
CC/BA
CYCLE H -'I..0Il.-_ _ '

LD CC/BA L

CLOCK LOSS SH CNTL ( 1) H

RX GO(OH
RXCLOCK
LOSS LOGIC

RX CLOCK H
RX ACTIVE (1)L
+3V

D12H

RX CK LOSS L

RX NPR DONE H

t - - - + - - WEN( 1)H

'.TX S DONEL
7474
WR
SYNC

C
OUT HIGH H
OUT LOW H

Ot-------a..~

TX CYCL E H
LD EXT I TRANS H

_--1"_

1-TXPOONEL

TEST NEXT ---.---------CC(OH

LD PTEE H
GATING

SEL4H

NEXT CC PULSE H - - - - I

o +RX GO/DONE L

LD ERR H

1-RXSDONE L
RX
DONE
LOGIC
RX CYCLE H

'.RX PDONE L

DONE Control Logic
11-2733

Figure 4-29 Block Diagram of the Oock Loss, Register Select and DONE Control Logic

RX GO (1) H is high) and the normal operating mode is
selected (D4-3 TEST LOOP (1) H is low). If the RX clock is
interrupted for more than SOO IDS, one-shot RX CLOCK
LOSS DLY times out. This action clocks the CK LOSS SH
CNTL flip-flop which sets it and asserts DS-4 CLOCK LOSS
SH CNTL (1) H. This signal is sent to the M7812 module
(print D4-3) and turns on the internal RC clock. TPJs clock
continues shifting in the character from the point at which
the RX clock was lost. When the NPR cycle is complete,
DS-3 RX NPR DONE H is asserted. This signal is inverted
by E35 pin 4 and directly clears the CK LOSS SH C~lL
flip-flop which shuts off the internal RC clock. When the
CK LOSS SH CNTL flip-flop is cleared, the positive
transition at its 0 output triggers one-shot RX CLOCK
LOSS PlJLSE. This one-shot produces a 7S ns positive pulse
that is ANDed with D4-4 RX GO (1) Hat E39 to generate
DS-4 1 ~ RX CK LOSS L. This signal goes to the
REG/ERR CSR (print D4-6) where it sets bit 1 and asserts
flag D4-6 RX CK LOSS (1) H. This signal generates D4-6
RX ERR L which clears RX GO and D4-6 ERR INTR H
which is the error flag.

4.5.4.2 Detailed Logic Description Clock Loss Logic
The clock loss logic is shown in the lower-left of drawing
D-CS-M7813-0-1, sheet 6 which is designated DS-4.
The transmit clock signal 04-3 TX CLOCK H is sent to the
input of one-shot TX CLOCK LOSS DLY. The other input
of the one-shot is permanently connected to ground. The
one-shot is a type 74123 which is retriggerable. This means
that if the one-shot has been triggered and another
triggering pulse (positive-going edge at pin 2) occurs before
the one-shot times out, another pulse is generated. The
one-shot pulse duration is set for approximately Soo ffiS.
The duration of the triggering pulse is much shorter, so as
long as signal D4-3 TX CLOCK H is present, the one-shot
remains in the active state. The 0 output (pin 4) remains
low once the one-shot is triggered and is sent to pin 10 of
3-input NAND gate E4S. Pin 9 of E4S is high because signal
D4-4 TX GO (1) H is asserted. The third input (pin 11) is
connected to the inversion of D4-3 TEST LOOP (1) H.
During normal operation, this signal is low; therefore, pin
11 is high. As long as the one-shot remains in the active
state, the output (pin 8) of E4S remains high. This Signal
(DS-4 1 ~ TX CK LOSS L) indicates a loss of the transmit
clock when it goes low.

Register Select Logic
The register select logic is located in the upper left of
drawing D-CS-M78 I 3-0-1 ,sheet 6 which is designated DS-4.

If the transmit clock signal is interrupted for more than
SOO IDS, the TX CLOCK LOSS DLY one-shot times out. Its
o output goes high and D4-4 1 ~ TX CK LOSS L goes low
to indicate the loss of the transmit clock. This signal goes to
the REG/ERR CSR (print D4-6) where it sets bit 0 and
asserts flag D4-6 TX CK LOSS (1) H which is sent to the
bus selectors to be read by the program. This signal also
generates D4-6 TX ERR L which clears the error flag (TX
GO and 04-6 ERR INTR H).

Inputs to the register select logic are: D3-1 OUT LOW H,
D3-1 OUT HIGH H, D3-1 SEL 4 H, and D3-1 SEL 6 H
from the MIOS Addressing Module; and D4-6 REG PT 8 (I)
H -D4-6 REG PT 11 (1) H from bits 8-11 of the
REG/ERR CSR.
When the REG/ERR CSR is addressed, D3-1 SEL 4 His
asserted. If the high byte of the register is selected, this
signal is ANDed with D3-1 our HIGH H to assert D54 LD
PTEE H at the output (pin 3) of AND gate ESO. If the low
byte is selected. D3-1 SEL 4 H is ANDed with D3-1 OUT
LOW H to assert DS-4 ill ERR H at the output (pin II) of
the other ESO gate. DS-4 LD PTEE Hand DS-4 LD ERR H
are asserted simultaneously if the register is addressed with
a word transfer selected.

The clock loss flag is generated also if TX GO is set while
the TX clock is not present.
The RX clock loss logic is more complex. The receive clock
signal D4-3 RX CLOCK H is sent to one-shot RX CLOCK
LOSS DLY. This retriggerable one-shot is identical to the
TX clock loss one-shot. The 0 output of RX CLOCK LOSS
DLY is sent to the clock input of flip-flop CK LOSS SH
CNTL. When the one-shot times out, the positive transition
at its 0 output clocks the CK WSS SH CNTL flip-flop. The
D-input of this flip-flop is connected to the output (pin 8)
of AND gate ESO which is high when RX GO is set (D4-4

When it is desired to select a secondary register, the
REG/ERR CSR is addressed and bits 8-11 are set up to
point to the desired register (Table 4-2). Then D3-1 SEL 6
H is asserted for a word operation to enable the selected
register. This logic generates enabling signals for the MISC
and SYNC registers only.

4-S4

Table 4-2
Selection of Secondary Registers
Octal

REG/ERR Bits
11

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17

For example, assume that it is desired to select the MISC
register (l2s). In accordance with Table 4-2, bits 8-11 of
the REG/ERR CSR are conditioned as follows:

Register
bit 11 = 1 (D4-6 REG PT 11 (l) H is high)
bit 10 = 0 (D4-6 REG PTI0 (l) H is low)
bit 9 = 1 (D4-6 REG PT9 (l) H is high)
bit 8 = 0 (D4-6 REG PT8 (l) H is low)

Rx BA Primary
Rx ec Primary
Tx BA Primary
Tx CC Primary
Rx BA Secondary
Rx ec Secondary
Tx BA Secondary
Tx CC Secondary
Character Detect
Sync
Miscellaneous
Tx Buffer
Sequence
RxBCC
TxBCC
Polynomial

Decoder E44 inputs are therefore:
D2=Low
Dl = High
DO=Low
This selects output f2 (D54 LD MISC L) when the
decoder is enabled (Figure 4-30). The MI05 Address
Module now asserts D3-1 OUT LOW Hand D3-1 SEL 6 H.
These signals go to 3-input NAND gate E45 pins 3 and 4,
respectively. When D5-3 Ce/BA CYCLE H goes high,
one-shot E93 sends a 100 ns positive pulse to the third
input (pin 5) of E45. This action generates a 100 ns
negative pulse at E45 pin 6 (Figure 4-31) that is inverted by
~nr1 ~p.nt to nln '\ of N A N1) o~tp. F,~Q Thp othPT ;nnllt
-F,40
-- ------- . . - r
0--- ---- - .. o

Selection of the MISC and SYNC registers is made with the
REG PT WRITE DCDR (E44). It is a 7442 4-line to 10-line
decoder, but it is connected to function as a 3 wire,
binary-to~ctal decoder. The three least significant inputs
(DO, D 1, and D2) are used as the binary code and the
fourth input (D3) is used as the strobe or enabling input.
The strobe (D3) must be low to enable the decoder.

----_.-

--~.-.

-"r~-

of E39 is held high by D4-6 REG PT 11 (I) H. This drives
E39 pin 6 low which enables the decoder and asserts D54
LD MISe L. The output of E39 is also sent to the DQl1
expander unit as D5-4 SEL 6 LD L.

There are four ce registers and four BA registers designated
0-78- In each case, bit 11 (D4-6 REG PTll (l) H) is low
when a ee or BA register is selected. The inversion of D4-6
REG PTll (1) H and the inversion of the pulse from E45
pin 6 are ANDed at E39 pins 1 and 2 to drive D54 LD
ee/BA L low whenever a ce or BA register is selected. This
signal is sent to E5 pin 10 (print D5-3) to generate D5-3 LD
eC/BA SP 15-0 L that controls the read/write state of the
ee/BA memory.

The input signals are:
DO = D4-6 REG PT8 (l) H
Dl = D4-6 REG PT9 (l) H
D2 = D4-6 REG PTI0 (l) H
D3 = ANDing of D4-6 REG PT 11 (I) H and positive
pulse from E40 pin 4.

Bit 12 (14, 13 WRITE EN) of the REG/ERR CSR is
associated with the register selection logic. The bit is stored
in the 14, 13 WR EN flip-flop. The D-input of the flip-flop
is controlled by the program via D4-2 D12 H. This bit is
used in systems that require 18 bit memory addresses and
allows bits 16 and 17 of the BA registers to be used.

Figure 4-30 shows the decoder and associated truth table.
The binary coded octal designations for the SYNC and
MISe registers are 118 and 12 8 , respectively. In each case
bit 11 is a 1.

4-55

04-6 REG PT11 (1) H
f7

from E40 pin 4

f6
04-6 REG PT 10 (1) H

04-6 REG PT 9 ( 1) H

04-6 REG PT 8 (1) H

E44
REG PT
WRITE
10-17
OCOR

f4
f3

05 -4 LO MISC L

05- 4 LO SYNC L

fO
Used asa 3 wire binary
to octal decoder. Input
03 is a strobe. Output Is
enabled low when 03 Is low.

7442

TRUTH TABLE
OUTPUTS

INPUTS
03 02 01 DO fO f1

f2 f3 f4 f5 f6 f7

H
H

L H H H H

H
11-2728

Figure 4-30 Register Select Decoder (E44)

03-1 OUT LOW H ---------~--......
03 -1 SEL 6 H -...,....----------t

05-3 CC/BA CYCLE H ---..----.
74123

100 os negative
pu Ise oenerated
when E93 fires
and pins 3 and 4
are hiOh

+3V
11-2729

Figure 4-31 Pulse Generator in Register Select Logic

4-56

The following conditions exist through the loading and
incrementing of the current CC and BA registers.

Assume that memory extension is required and the program
asserts 04-2 D12 H. When the high byte of the REG/ERR
CSR is addressed, DS-4 LD PTEE H goes high and clocks
the 14, 13 WR EN flip-flop which sets it. This asserts DS-4
WEN (l) H which is the bit 12 flag. This signal is sent to the
M7812 bus selectors where it can be read by the program.
When the 14, 13 WR EN is set, the low from its 0 output
directly sets the WR SYNC flip-flop. The low from the 0
output of this flip-flop is sent to E3S pin 2. The program
uses address 76XXX6 during a DATO transaction to enable
the selected BA register. The MI0S Address Module asserts
D3-1 OUT LOW Hand D3-1 SEL 6 H which generates the
100 ns negative pulse at E4S pin 6. This pulse directly
clears the 14, 13 WR EN flip-flop via gate ESO. As
previously described, this pulse enables DS4 LD CC/BA L
which controls the read/write operation for bits 0-IS of
the CC/BA memory. DS4 LD CC/BA L also goes to the
other input (pin 3) of E3S which asserts DS4 LD
EXT /TRANS H. This signal controls the read/write operation for bits 16 and 17 of the CC/BA memory. The
positive-going trailing edge of the 100 ns pulse from E4S
pin 6 clocks the WR SYNC flip-flop which clears it and
drives DS4 LD EXTjTRANS H low.

DONE Control Logic
The DONE control logic is located in the right side of
drawing D-CS-M7813-O-1, sheet 6 which is designated DS-4.
The logic is divided into two identical sections: one for the
transmit mode and one for the receive mode. Each section
has four outputs that perform the following functions:
1.

Clear the GO bit.

Set the primary DONE flag.

Set the secondary DONE flag.

Indicate whether the primary or secondary
register is selected.

The TXS flip-flop is cleared because the primary CC register is being used. The low from
the 1 output of the TXS flip-flop inhibits both
ES7 gates. Neither DS-4 1 ~ TXS DONE L nor
DS-4 1 ~ TXP DONE L is asserted.

DS-4 TXS (1) H is low which indicates that the
primary register is being used. This signal goes
to the CC/BA addressing logic (print DS-l).

DS-l CC OFLOW H is high. It was asserted
when the overflow occurred.

DS-3 NEXT CC PULSE H is low which inhibits
gate E48 pin 6. DS-4 0 ~ TX GO L is not
asserted.

DS-3 TX CYCLE H is asserted because a
transmit operation is in process.

DS-3 TEST NEXT CC (l) H is low.

When it is time to load the next CC, DS-3 TEST NEXT CC
(l) H is asserted which clocks the TXS flip-flop and sets it.
This flip-flop is complemented with each clocking pulse.
When TXS is set, DS4 TXS (l) H is asserted which
addresses the TX secondary CC register and it is loaded into
the CC/BA counter. The 1 output of TXS puts a high on
pin 9 of ES7 which qualifies it.
Now, DS-3 NEXT CC PULSE H is asserted which puts a
high on pin 10 of ES7. This drives the output (pin 8) of
ES7 low which asserts DS-4 1 ~ TX P DONE L. This signal
goes to the TX CSR (print D4-4) to directly set the TXP
DONE bit which indicates that the use of the TX primary
CC register has been completed.

These output signals are generated by type 74S0, dual
2-wide 2-input, AND-OR-invert gates. The outputs can be
asserted by signals from the CC overflow detection logic or
by signals from the sequence decoding logic on the M7817
module that is used only in the DQ 11 expander unit. This
discussion deals only with the signals from the CC overflow
detection logic.

If the TX secondary CC register (which is in the CC/BA
counter) is empty, the counter reads alIOs and DS-l CC
OFLOW H remains asserted. This signal puts a high on pin 4
of E48; the other input (pin S) is already high due to DS-3
NEXT CC PULSE H. This drives the output (pin 6) of E48
low which asserts DS-4 0 ~ TX GO L. This Signal goes to
the TX CSR (print D4-4) to directly clear the TX GO bit
which inhibits further NPR cycles because there are no
more characters to transfer to the transmit buffer.

The operation of the logic is explained by discussing a
specific example. Assume that a transmit operation is in
process and the TX primary CC register is selected. In
addition, the present CC updating cycle causes an overflow.

If the TX secondary CC register contains a count, TX GO is
not cleared. At the next NPR cycle, the transmit operation
picks up the count from the secondary register.

4-S7

Signal D2-1 DS INTR L is sent to the interrupt and vector
control logic from the Data Set Control Module M78I8.
When anyone of the following three data set signals are
detected coming on or off, the DATA SET INTR bit (TX
CSR bit 15) is set and D2-I DS INTR L is asserted. The
signals are: RING (ring indicator), CO (carrier or signal
quality detector), and CS (clear to send). In addition, two
user option bits (UOI3 and UOI4) can be connected via
jumpers to assert D2-1 DS INTR L.

4.5.5 Interrupt and Vector Control Logic
4.5.5.1 Functional Description - The interrupt and vector
control logic is the controlling link between the interrupt
requesting logic in the DQII and the M7821 Interrupt
Module that actually initiates the interrupt request.
Rather than discuss the interrupt and vector control logic
alone, its interaction with the requesting logic and the
M782I is discussed for a typical example in the detailed
logic discussion that follows.

Features of the M7821 Interrupt Module
The M782I Interrupt Module does not have two identical
master control sections. In the case of the DQll, master
controi section A (identified by request input pins UI and
VI) is used to allow the DQ 11 to become bus master with
an NPR. Pin U2 is permanently connected to ground so
that the DQll performs one bus cycle per NPR (print
D3-1).

The remainder of this section discusses certain topics that
are prerequisites to the discussion of the interrupt
transaction.
Interrupt Request Signals
Three interrupt requesting signals are used:
D4-4 TX/ERR INTR L
D4-4 RX/CHAR INTR L
D2-I DS INTR L.

Master control section B is used for BRs. The jumper for
vector bit 2 is left installed and pin D2 is connected to D5-5
VECTOR BIT 2 (1) H from the interrupt and vector
control logic. This allows the BR section to generate two
vector addresses per device.

Signal D4-4 TX/ERR INTR L is sent to the interrupt and
vector control logic from the TX CSR. This Signal is
asserted by the following conditions, providing the
appropriate interrupt enable bit is set by the program.
1.

Setting the TX DONE primary or secondary
bits in the TX CSR.

Setting the ERR INTR bit in the REG/ERR
CSR. This bit is set when anyone of the
following error bits is set in the REG/ERR
CSR. The error bits are: RX clock loss, TX
clock ioss, RX iatency, TX iatency, RX nonexistent memory, TX non-existent memory,
~X BCC, and VRC.

The BR section has a special circuit that improves NPR
la tency time. It requires that the NPR jumper associated
with pin 11 be left installed and pin 11 be connected to
BUS NPR L from pin U2 (print D3-I). If D5-5 BG IN His
asserted while BUS NPR L is asserted, the circuit blocks the
grant signal and asserts BUS SACK L. When BUS BBSY Lis
cleared by the last bus master, the M7821 clears BUS SACK
L. The processor now services the NPR which improves the
:N'PR latency time for the DQll. The M7821 keeps D3-1
BR L asserted so that when the NPR transaction is finished
the processor asserts DS-S BG IN H again.
Priority Select Card
Socket E89 on the M78I3 module (print D5-5) is wired to
accept the priority select card. Four cards are available; one
for each BR level (4, 5, 6 and 7). The recommended level
for the DQ 11 is BR5 and it is shipped with a BR5 priority
select card installed. Figure 4-32 shows the BR5 priority
select card and how it interconnects with the M782I
Interrupt Module and the interrupt and vector control
logic. On the BR5 priority select card, the bus request
signals for levels 4, 6, and 7 are not connected. The bus
grant in signals for levels 4, 6, and 7 are directly connected
to the grant out signals for the corresponding levels. This
allows bus grant signals for levels 4, 6, and 7 to pass
through the DQ 11 to other devices.

Signal D4-4 RX/CHAR INTR L is sent to the interrupt and
vector control logic from the RX CSR. This signal is
asserted by the following conditions, providing the
appropriate interrupt enable bit is set by the program.
1.

Setting the RX DONE primary or secondary
bi ts in the RX CSR.

Setting the CHAR INT bit in the RX CSR. This
bit is set when anyone of three hard-wired
characters is detected in the M78I8 module.
This bit is also set by the programmable
character detection logic if the DQll-BB
option is used.

4-58

BUS BG IN H
BUS BG OUT H
BUS BG 4 OUT H
BUS BG 4 IN H

BR5 Priority
Select
Card
1 ---------.16
•
• BUS BR 7 L
2
~ BUS BR6L
3
1-'_4---.,;;B;...;U;...;S;......::,B.;.,;R.....:5:....L~_ _ _----1~ To Un i bu s
BR5 Line
4
~ BUS BR4 L
5
12 BUS BR L
p

BUS BG 5 OUT H

BUS BG 5 IN H

BUS BG 6 OUT H

..!.!.... BUS BG 7 IN H

..!.2.. BUS B G 7 OUT H
••- - - -....... -

BUS BG 6 IN H

From Unibus BG 5 Line
To

Unibus BG5 Line

05-5 BG OUT H

05- 5 BG IN H

I M7821
B
Control

r---

04-4 RX/CHAR INTR L-----04-4 TX/ERR INTR L - - - -

r---- -

03-1 INTR BOONE H -~
M7813
Int errupt
a Vector
Control

03-1 BR L

- - - - 05-51NH INTR B L

- - - 05-51NTR BH

I - - - - - - J - - - 05-5 VECTOR BIT2(1)H

02-1 OS INTR L
11-2727

Figure 4-32 BR5 Priority Select Card Interconnection

4-59

When the M782l is requesting a BR, it asserts D3-l BR L
on pin Pl. This signal goes to pin 12 (BUS BR L) of the
priority card and out pin 14 (BUS BR 5 L) which is
connected to the Unibus. A BR on level 5 has been
requested. The processor responds with the bus grant signal
(BUS BG 5 IN H) to pin 7 on the priority card. It passes
through the card and out pin 2 (BUS BG IN H) to pin E1
(D5-5 BG IN H) of the M7821 module. It is blocked by the
M7821 to start the interrupt sequence. If the DQll is not
requesting a BR on level 5 but another device further down
the line is requesting a BR5, th.e bus grant signal is not
blocked by the DQll 's M7821 module. The grant signal
enters pin El of the M7821 and out pin Al (D5-5 BT OUT
H) to pin 3 (BUS BG OUT H) of the priority card. It passes
through the card and out pin 6 (BUS BG 5 OUT H) which
is connected to the Unibus. The grant travels along this
Unibus line (BG5) until it is blocked by the requesting
device.

Signals D5-5 INTR B Hand D5-5 INH INTR B
L (which are both high) are sent to M7821 pins
K2 and H2, respectively. When both these
signals are high, the M7821 asserts D3-1 BR L
at pin PI (print D3-l).

D3-1 BR L leaves the M7821 module and passes
through the priority card to the Unibus as BUS
BR 5 L (Figure 4-31). This is a request for bus
mastership.

The processor examines BUS BR 5 L and, if it
has the highest request priority, the processor
asserts BUS BG 5 IN H provided BUS SACK L
is clear. BUS BG5 IN H passes througll the
priority card to pin El of the M7821 module
where it is identified as D5-5 BG IN H because
it also goes to the interrupt and vector control
logic. This signal clears D5-5 BG OUT H on pin
Al of the M7821 module which blocks the bus
grant signal and prevents it from reaching any
following devices on the BR 5 level on the
Unibus.

D5-5 BG IN H is sent to pin 13 of NAND gate
E53. It is inverted by this gate and again by
E15. The positive transition at E15 pin 8 clocks
the VECTOR BIT 2 flip-flop. The flip-flop is
cleared because its D-input is low. The D input
of VECTOR BIT 2 is connected to E62 pin 11
which is low (step 2). When the flip-flop is
cleared, it drives D5-5 VECTOR BIT 2 (1) H
low.

D5-5 VECTOR BIT 2 (1) H, which is low, is
sent to pin D2 of the M7821 module. When this
signal is low, the in terrupt is requested on
vector A (XXO). This is described in detail in a
subsequent section.

Signal D5-5 BG IN H on pin El of the M7821
also causes the bus request signal (D3-1 BR L)
to be cleared and BUS SACK L to be asserted
on pin T2.

10.

The processor receives BUS SACK L and clears
BUS BG 5 IN H which prevents the issuance of
further grants from the processor during this
interrupt transaction.

4.5.5.2 Detailed Logic Description - This discussion
covers a typical interrupt transaction and shows the
interaction among the interrupt and vector control logic,
M7821 Interrupt Module, and other sections of the DQll
logic.
Assume that the RX DONE primary bit in the RX CSR has
been set. This event starts the sequence that requests an
interrupt on vector A (XXO).
1.

In order to allow the setting of the RX DONE
primary bit to request an interrupt, the program must first set the RX DONE IE bit in the
CSR. This asserts D4-4 RX DONE IE (1) Hand
when the RXP DONE flip-flop (print D4-4) is
set, D4-4 RX/CHAR INTR L is asserted at the
output (pin 8) of gate E44~
D4-4 RX/CHAR INTR L is sent to the interrupt and vector control logic (print D5-5). This
signal is inverted by E40 and puts a high on pin
12 of E62. The other input (pin 13) of E62 is
already high because the RX/CHAR INTR is
cleared. The output (pin 11) of E62 goes low
which asserts D5-5 INTR B H at E62 pin 6.
Signal D3-1 INTR B DONE H from M7821 pin
M2 is low and is sent to the interrupt and
vector control logic. It is inverted by E40 to
hold D5-5 INH INTR B L high.

4-60

II.

When the current bus master completes its
transaction, it clears BUS BBSY L and BUS
SSYN L. In response to this action, the M7821
asserts its own BUS BBSY L (pin Dl) and clears
BUS SACK L (pin T2). When BUS BBSY L is
asserted, signal MASTER B L is asserted at pin
S2 and is sent to pins P2 and R2 of the M7821
module. This asserts BUS INTR L at pin MI
and places the vector address (XXO) on Unibus
data lines BUS D02-D08 L. The DQl1 is now
bus master.

12.

The processor receives BUS INTR L, reads the
vector address, and responds by asserting BUS
SSYN L.

13.

In response to BUS SSYN L (pin C1), the
M7821 module asserts D3-1 INTR B DONE H
at pin M2 which is sent to pin SI (not labeled
but sometimes identified as B MASTER
CLEAR H). This clears BUS BBSY L, MASTER
B L, BUS INTR L, and the vector address. This
constitutes active release of the bus to the
processor which clears BUS SSYN L when it
receives the cleared BUS INTR L signal. The
processor goes to the interrupt service routine
at the specified vector address (XXO).

14.

Signal D3-1 INTR B DONE H from the M7821
module is also sent to the interrupt and vector
control logic (print DS-S). When it goes high
(step 13), the positive transition clocks the
RX/CHAR INTR flip-flop. It sets the flip-flop
because its D-input is high as a result of the
VECTOR BIT 2 flip-flop being previously
cleared (step 7).

15.

16.

It is possible for the program to leave the RX DONE
primary bit of the RX CSR set (D44 RX/CHAR INTR
flip-flop remains set) and request another interrupt via
signal D2-1 DS INTR L or D44 TX/ERR INTR L (print
DS-S). Assuming that this is done, pin 1 of E62 is high
because one of these request signals is asserted. Pin 2 of
E62 is also high because the TX/ERR/DS INTR flip-flop is
cleared. The output (pin 3) of E62 goes low which asserts
DS-S INTR B H.
The interrupt request sequence proceeds as described in the
previous example. DS-S BG IN H is asserted by the M7821
module and clocks the VECTOR BIT 2 flip-flop. The
flip-flop is set because its D-input is high. When the flip-flop
is set, it drives DS-S VECTOR BIT 2 (1) H high which sets
up the request on vector B (XX4). The 0 output of the
VECTOR BIT 2 flip-flop puts a high on the D-input of the
TX/ERR/DS INTR flip-flop and a low on the D-input of
the RX/CHAR INTR flip-flop. The interrupt transaction
continues and D3-1 INTR B DONE H is asserted. This
signal clocks the TX/ERR/DS INTR flip-flop which sets it
and drives DS-S INTR B H high. D3-1 INTR B DONE H
also clocks the RX/CHAR INTR flip-flop. Because of the
hold-set feature used in this flip-flop, the clocking signal has
no effect. If the clocking signal was effective, the RX/
CHAR INTR flip-flop would have been cleared and it
would have kept DS-S INTR B H asserted despite the action
of the TX/ERR/DS INTR flip-flop.
Both the RX/CHAR INTR and TX/ERR/DS INTR flipflops have the hold-set features. In the situation just
described, the RX/CHAR INTR is set and its D-input is
low. Its 0 output (pin 8), which is low, is fed back to the
preset input (pin 10). As long as this input is low, the
flip-flop remains in the set state. This situation overrides
the clock input; therefore, if the flip-flop is clocked with
the D-input low, it cannot be cleared. If the clear input (pin
13) is made low while the preset input (pin 10) is still held
low, the 1 output does not change state but the 0 output
goes high. This releases the preset input and the 1 output
goes low so the flip-flop now is in the cleared state.

When the RX/CHAR INTR flip-flop is set, it
drives DS-S INTR B H low which prevents the
M7821 from requesting another interrupt until
a requesting signal (D44 TX/ERR INTR L,
D2-1 DS INTR L or D4-4 RX/CHAR INTR L)
is asserted (goes high) again.

This feature prevents the RX/CHAR INTR and TX/ERR/
DS INTR flip-flops from interfering with one another but
allows them to be cleared when the appropriate request
signal is dropped.

The situation that requested the interrupt
(setting the RX DONE primary bit of the RX
CSR) must be cleared by the program. When it
is done, D44 RX/CHAR INTR L goes high.
This signal is inverted by E40 and directly
clears the RX/CHAR INTR flip-flop.

Vector Address Generated by M7821 Module
Each device interrupt vector requires four address locations
(two words) which implies only even-numbered addresses.

4-61

When MASTER B L is asserted, it puts a high on both
inputs (pins 8 and 9) of E9 which drives its output low.
This low signal appears on Unibus data line D03 where it is
represented as a logical 1 (on the Unibus, L = 0 V = logical
1). The 8881 driver (E9) is a bare collector NAND gate.
When both inputs are high, the last stage transistor in the
gate is turned on. The emitter of this transistor is connected
to ground in the device so the +5 V, via the Unibus
terminator network, is connected to ground and the driver
output is low.

A further constraint is that all vector addresses must end in

o or 4. The vector address is specified as a three-digit,
binary-coded, octal number using Unibus data bits
D08-DOO. Because the vector must end in 0 or 4, bits 001
and DOO are not specified (they are always 0) and bit D02
determines the least significant octal digit of the vector
address (0 or 4). The logic on the M7821 module sends
only seven bits (D08-D02) to the PDP-II processor to
represent the vector address.
The vector address is configured by jumpers in the lines for
bits D08-D02. In this case, the M7821 module is required
to generate two vector addresses so the jumper for bit 2
must be left in. The two most Significant octal digits of the
vector address are determined by jumpers in lineS
D08-D03. With the jumper in, a 1 is generated on the
associated Unibus data line. With the jumper out, a 0 is
generated on the associated Unibus data line.

With the jumper out, driver E9 has no effect. The +5 V in
the bus terminator holds Unibus bit D03 high which is
represented as a logical 0 (on the Unibus H = +5 V = logical
0).
4.5.6 Transmit Control Logic
4.5.6.1 Functional Description - A Simplified block diagram of the transmit control logic is shown in Figure 4-35.
The logic performs several functions that are interrelated
but can be described separately. The major functional areas
are listed below in order of discussion.

Figure 4-33 shows the determination of vector addresses for
two DQ lIs in a system. It is desired to have the first DQ 11
generate 300 for vector A and 304 for vector B. The second
DQ11 follows with 310 for vector A and 314 for vector B.
Using the first DQl1 as the example, the jumper configuration is as follows: jumpers 8, 5, 4, and 3 out and
jumpers 7 and 6 in. The circuit above the table in Figure
4-33 shows the gates inside the M7821 module that are
associated with bit D02. Assume that D4-4 RX/CHAR
INTR L is requesting the interrupt. This request is for
vector A (300). As the sequence progresses, the VECTOR
BIT 2 flip-flop (print D5-5) is cleared which drives D5-5
VECTOR BIT 2 (1) H low. This signal is sent to E9 pin 12
in the M7821 module (Figure 4-32). Later in the sequence,
MASTER B L is asserted at pin S2 of the M7821 and fed
back in to pins P2 and R2 of this module. This low signal is
inverted by E7 and puts a high on the other input (pin 11)
of E9. The output (pin 13) of E9 goes high and this signal
appears on Unibus data line 002. The Unibus data lines use
negative logic so this high signal represents a logical o. With
the jumper configuration as shown and bit D02 = 0, the
M7821 module generates vector address 300.

If D4-4 TX/ERR INTR L or D2-1 DS INTR L requests the
interrupt, Signal D5-5 VECTOR BIT 2 (l) H is high and bit
D02 = 1; therefore, the M7821 module generates vector
address 304.

The logic within the M7821 module for vector bits
008-003 is identical and is shown in Figure 4-34. The
output of gate E7 goes to both inputs of the 8881 bus
drivers associated with vector bits 008-003 (bit D03 is
shown as typical). The first case is for the jumper installed.

4-62

Transmit Shift Counter (E81) and Transmit Bit
Counter (E86)
a.

TX Shift Counter (E81). This counter is
loaded with the 2's complement of the
number of bits per character selected by
the program. It counts upward toward
overflow (count 0) which denotes the end
of the character. At overflow, the counter
generates a carry out (CO) pulse which
returns this counter and the TX bit
counter (E86) to the load mode. The CO
pulse also initiates other functions in the
TX control logic.

TX Bit Counter (E86). This counter is
loaded and clocked by the same signals
that load and clock the shift counter
(E81). The TX bit counter is always
loaded with count O. It starts at zero and
is incremented in synchronism with the
shift counter (E81). The TX bit counter
outputs are the select inputs for the
output multiplexers in the TX shift
register. As the counter is incremented,
these outputs change and select each
multiplexer input, in sequence, to perform the parallel-to-serial conversion of
the character to be transmitted.

HiOh when TXI ERR or OS is
requestino. Low when
RX/CHAR is requestino
+5V

02
12,....---.
05-5 VECTOR BIT 2 (1) H
8881
11 E9

o-......L.-,-- BUS 002 L

Positive Looie
L=OV= Looieal 0
H= +5V" Looieal 1

UNIBUS
Neoatlve Looie
L- OV - Log ieal
H= +5V- Logiea I 0

MASTER B L

Asserted when
requestino interrupt

Controlled by
jumpers. X means
remove jumper.

~ Controlled by logic shown above.

r--- Not used. Always O·

r~--~---~

1:1716':1~1:121'101
1\

300 (VECTOR A)
MASTER BL is low.
RX ICHAR requestinoBUS 002 is hiOh (0).

- - _. ---- --- --t

X
0

1 sf OQ11

304 (VECTOR B)
MASTER B L is low.
TX/ERR or OS requestinO.
BUS 002 is low (1).

310 (VECTOR A)

_. 0 0 - - - - - - - - - --

2nd OQ11

~-. ~-.

314 (VECTOR B)

11- 2732

Figure 4·33 Generation of Two Vector Addresses on
M7821 Interrupt Module

4-63

Jumper In
+5V
MASTER BL
from pin S2 -....:....;..::=--~
on M7821

Low

High

h - -............- - - BUS 003L

M7821
Positive Logic
L=OV"O
H=+5V=1

Low when
request ing

"::"

Unibus
Negative
Logic
L=OV='
H=+5V=0

I +5V

High

---'-CW'~ _ ~W
8 E9

0_>---_---I-J-L--r--

L OW
- - - - - - - - BUS 003 L

When inputs are high,
last stage transistor is ON.
+5V goes to ground.
Out put is low.

Jumper Out
+5V

~~10~_-oO

UCJ

o---....L.....~-- BUS

003 L

Jumper3
removed
11-2726

Figure 4-34 Configuration of Vector Bits 03 -08

Send Enable Flip-Flops and Input Priority
Gating. The flip-flop outputs are enabling
signals that are used as inputs to the sync/data
enable multiplexer. These signals are also sent
to other modules. The input gating to the
flip-flops establishes the priority for selecting
the enabling signals based on the type of
character. The priority, in descending order,
is: DLE, BCC, SYNC, Data and PAD.

Sync/Data Enable Multiplexer. The sync and
data signals from the send enable flip-flops are
sent to the inputs of the sync/data enable
multiplexer. They are selected to provide
enabling signals for the sync register and TX
data register. Selection is a function of the TX
counter MSB input and output and the output
of the character count logic.

4-64

Character Count Logic. When handling data in
the double-character mode, this 10gic controls
the select input of the sync/data enable multiplexer to allow both bytes of the TX data
register to be enabled.

Save Sync Logic. The idle character, in the
transparent mode, is Data Link Escape (DLE)
followed by the contents of the sync register;
that is, DLE-SYNC, DLE-SYNC, etc. This logic
allows the sync register to be enabled and
disabled so that idle characters can be transmitted.

Vertical Redundancy Check (YRe) Logic.
When VRC is selected, this logic examines the
data to be transmitted and puts a 1 in the most
Significant bit of each character in which the
selected VRC (odd or even) is detected to be in
error.

EVEN VRC l
BITS

(1) H

MSB

BITS 10(1) H
TX
BIT
CNTR

TX
SHIFT
CNTR

BITS 9 (1) H
BITS 8 (1) H

+3V

ClR
lD

+3V

VRC(1) H

TX BIT CNTH 4(1) H
TX BIT CNTFI 2( 1) H
TXBIT

VRC
CONTROL
lOGIC

CNTI~I(I)H

ClR

CNTEN

1---+-- SYNC EN(ll l
1---+-+--- B CC EN ( 1) l

CRYEN

CRY EN

1----+-+--1---- Dl E EN (1) l

ClK

+3V

SYNC/DATA
ENABLE
SEND
ENABLE

L - - - - - - - - - - - - L + To several places in
TX Control logic

SYNC

TX DATA
EN 7-0 l

BCC
TX ACTIVE ( 1) H
CO PULSE l

lD TX SH REG H
DATA
SYNC
lOGIC

TX CLOCK H

OLE
ClK

TX NPR RQ ( 1) H
TX lATE l

TX TRANS (1) l

TX GO(1)H

TX ACTIVE (1) H

~~VE

SYNC
LlOGIC

ClR

TX FAKE END (I) H

STB

TX DATA
EN 15 - 8 l

INI l

--r

BCC EN (1)l

CLOCK

VRC (11 H
CO PULSE H

CO PULSE H --LGATING

TX CYCLE H
CC ODD (1) H - - ' - -_ _ _--1

TX SYNC
EN 7-0 l
TX SYNC
EN 15 - 8 l

DATA

CHAR PEND (1) H

VRC/DATA
SEl l

r-------<OI lD

TX CLOCK H -+--r----f ClK

TX ACTIVE ( 1) H

rx DATA H

TX BIT CNTf;: 8 (1) H

DATA EN(I) H
CO PULSE H

TX BIT CNTR8 (1) H
11-2731

Figure 4-35 Block Diagram of Transmit Control Logic

Transmit Shift Counter (£81)

Fake End Logic. In the double character mode
with an odd count detected, only one byte of
the last word contains a character to be
transmitted. This logic detects the situation and
allows the empty byte to be ignored and fakes
the end of the current transmission. This
permits the next NPR to be started sooner. It
also sends a signal to the TX BCC logic to allow
the appending of the BCC character in the
correct place.

D4-3 BITS 11 (1) H
D4-3 BITS 100) H
D4-3 BITS 9 (1) H
D4-3 BITS 8 (1) H

Data Sync/NPR Logic. At the start of a
transmission, this logic generates a data enable
and synchronizes the loading of the TX shift
register. It also generates an NPR request after
data is moved from the TX buffer to the TX
shift register.

4.5.6.2 Detailed Logic Description - The circuit schematic for the transmit control logic is contained in drawing
D-CS-M7813-0-1 (Rev H) sheet 8 which is designated DS-6.

The outputs are not used.

The carry out (CO) output is used. This output
goes high at the count of minus 1 (2's complement notation) and goes low at the next clock
pulse when the counter overflows. This denotes
the end of the character. In subsequent references to this operation, it is stated that a CO
pulse is generated at overflow.

Transmit Bit Counter (£86)

Transmit Shift Counter (E81) and Transmit Bit Counter
The transmit shift counter (TX SHIFT CNTR) is designated
E81 and is located in the right center section of print DS-6.
The transmit bit counter (TX BIT CNTR) is designated E86
and is located in the lower left section of print DS-6. Both
devices are 74161 synchronous 4-bit counters. The configuration of these counters is described below.

The data inputs are permanently connected to
ground so that the counter is always loaded
with count O.

The four outputs are listed below.
DS-6 TX BIT CNTR 8 (1) H
DS-6 TX BIT CNTR 4 (1) H
DS-6 TXBIT CNTR 2 (1) H
DS-6 TX BIT CNTR 1 (1) H

Both Counters
Count enable inputs (CNT EN and CRY EN)
are held high by +3 V so that the counter is
permanently enabled.

The clear input (CLR) is disabled by holding it
permanently high with +3 V.

3. -

D4-3 TX CLOCK H is sent to the clock input
(CLK). The positive-going edge of this signal
increments the counter.

When the load input (LD) of the counter is low,
the counter is inhibited and the outputs agree
with the data inputs after the next clock pulse.
The load input is enabled (driven low) under
two conditions; when the TX ACTIVE flip-flop
is cleared or when TX BIT CNTR (E81)
overflows.

(MSB)

(£86)

The data inputs come from MISC register bits
8-11 that select the number of bits per
character. The signals are listed below.

(MSB)

The most significant bit (MSB) is used in the
TX control logic. The other three bits are used
as select signals for the output multiplexer in
the TX shift register and the SYNC register.
3.

The carry out (CO) pulse is not used.

A typical load and count operation for the TX SHIFT
CNTR and TX BIT CNTR is described. Figure 4-36 shows
the counters and some associated logic. The operation that
is described assumes that 12 bits per character has been
selected. Figure 4-37 shows the load and count sequence
graphically.
The TX SHIFT CNTR (E81) is to be loaded with the binary
value of MISC register bits that represent the selection of
12 bits per character (Figure 4-37). The value is 0100 (MSB
to the left) which is the 2's complement of 12 10 •

4-66

05-6 TX ACTIVE (1) H

MSB used in
TX control
100ic

'::"

04-3 BITS 11(I)H
04-3 BITS10(I)H
04-3 BITS 9 (llH
04-3 BITS8(tlH

4
3
9

04-3 TX CLOCK .•

..fI...
+5V

MSB

LSB

74161
E81
SHIFT
CNTR

74161
E86
TX
BIT
COUNTER

MSB

05-6 TX BIT CNTR 2(1) H
LSB

-..,J

+5V enables
counter and
Inhibits CLR

CLK
+5V

CLR
CNT EN
CO
CRY EN

05-6 TXBIT CNTRI (llH

LO
CLK

Three LSBs sent
to select Inputs
of multipl81ers
in TX shift reoister

CLR

0-.

05-6 TX BIT CNTR FI (1) H
05-6 TX BIT CNTR4(1) H

15J1....

CNT EN
Puls-! gene rated
when counter
oller flows. Fed
bock to put counter
in 10-lld mode.

CO
CRY EN

11-2730

Figure 4-36 TX Shift Counter, TX Bit Counter and Load Logic

Example
Select 12 bits / character.
Load 2 's complement
of 12 10 into counter

Data Inputs to
TX SHIFT CNTR (ESl)
MISC Reg Sits
10
9
S
11
0
0
0
0
0
0
1
0
0
0
1
0

1's

12 10
1100
complement .. 001.1

add +1
+ I
2's complement = 0100

Load counter

Coun'•• inc......,.

to overflow and stops.
It hos counted 12 bits.

I
I

0
0
0
0
0
1
1
1
1
1
1
1
1

0
1
1
1

1
0
0
0
0
1
1
1

1
0

0
1

1
0
1
0
1
0
1
0
1
0
1

Sits Per
Char.

16
15

14
13
12

11
10
9

1
0
0

I I 7

1
1
0

0
1
1

0
1

4
3
2
1

Counter overflows after count
15 and generotes a CO pulse
thot puts it back in the load
mode.
11-2754

Figure 4-37 Graphical Representation of TX Shift Counter Load
and Count Sequence

The program sets the value in bits 8-11 of the MISC
register which in turn sends it to the data inputs of TX
SHIFT CNTR (E81). This operation is performed before
the first character is brought in for transmission; therefore,
the TX ACTIVE flip-flop is cleared and OS-6 TX ACTIVE
(1) H is low. This signal, via E79 pin 8, puts a low on the
load input (LO) of both counters (E81 and E86). The next
positive transition of 04-3 TX CLOCK H inhibits both
counters and loads them. TX SHIFT CNTR (E81) is loaded
with the 2's complement of 12 10 and TX BIT CNTR (E86)
is loaded with Os. As long as the load inputs are held low,
the counters are not incremented by the clock signal.
Assume now that the first sync character is transferred to
the OQll for transmission.

sends it out on the serial data line. On the next count, the
counter overflows and generates a positive CO pulse that
permits another load operation. This load, count and
overflow process continues until there are no more characters to transmit.

Send Enable Flip-Flops and Input Priority Gating
The SEND ENABLE flip-flop (E71) is a quad flip-flop
package (74175) with complementary outputs and a
common clock. It produces enabling signals for OLE, BCC,
SYNC and data characters which are sent externally to the
following places.
Output
05-6 OLE EN (1) L
05-6 BCC EN (1) L
05-6 SYNC EN (1) L

Signal OS-6 TX ACTIVE (1) H goes high which inhibits the
load inputs of both counters and allows them to be
incremented by the clock. 05-6 TX ACTIVE (1) H remains
high as long as there is anything to transmit (SYNC, BCC,
data, etc.). Under these conditions, subsequent load operations are accomplished by the CO pulse from TX SHIFT
CNTR when it overflows. Both counters continue to
increment together. The three least significant outputs of
TX BIT CNTR are sent to the select inputs of the SYNC
register output multiplexers (print 04-7). The first value
selects input 4 and as TX BIT CNTR (E86) is incremented
the multiplexers ripple up through input 15 (total of 12
bits). This operation serializes the l2-bit sync character and

Destination
M78l7 Module (08-5)
M7816 Module (09-5)
M7816 Module (09-5)

Some of the E71 outputs are used in the TX control logic
as described below.
Figure 4-38 shows the SEND ENABLE flip-flops with
associated output gating and clock input gating. The input
priority gating is not shown. The gating network (05-6)
that is connected to the SEND ENABLE inputs establishes
the priority for selecting the enabling signals. The priority,
in descending order, is OLE, BCC, SYNC, Oata and PAD.

4-68

E71
74175
SEND ENABLE

------15
R3 (1)
03 DATA
R3 (0)

Inputs connected
to priority gating.
Priority in decending
order is olE,BCC,
SYNC, DATA, PAD.

------12

R2 (1)

02 SYNC
R2 (0)

------5

R1 (1)

01 BCC
R1 (0")

---- --4

RO (1)

DO OLE
RO (0)

~05-6VRCI

05-4 INI H

oATASEll

7
6
2

When the DQ11 is
not actively
transmitting, E30
and E82 keep E52 pin 6
in the MARK state.

-----ClR

Q)---~

ClK

05-6 oL.E I::N (1) l
TO 08-5
05-6 BCe i::N (1) L }TO 09-5
~---- 05-6 SYNC EN (1) l
L...-_ _

I
: CONDITION A :

CON olTlON

I No CO pulse I

TX ACTIVE stays I
high. CO pulse
I
generates clock.

TX ACTIVE I
goes high to
generate clock.

CO PULSE

05-6 TX ACTIVE (1) H

11-2755

Figure 4-38 Send Enable Flip-Flops and Associated Logic

held low to enable the mux. With SO low, the A inputs are
selected; and with SO high, the B inputs are selected. The
outputs are the complements of the inputs. The 1 output
from the SYNC section of the SEND ENABLE flip-flop
(E7l) is sent to inputs A3 and B2. The 1 output from the
Data section of SEND ENABLE is sent to inputs Bl and
AO.

For example, if a DLE character is to be transmitted, D8-5
DLE RQL goes low. This drives the output (pin 3) of E65
high. This signal is sent to input DO of E71. When E7I is
clocked, D5-6 DLE EN (1) L is asserted at output RO (0).
This signal is sent to the M78I7 module (D8-5). The high
signal from E65 pin 3 is sent to E56 pin 12 to block
assertion of the other enable signals (BCC, SYNC and
Data). This signal also drives E25 pin 6 low which, via E60
pin 6, puts a high on the D input of the TX ACTIVE (1) H
which is sent to the 8-input OR gate on the M78I2 module
(D4-7). Enabling any type character (DLE, BCC, SYNC or
Data) allows the TX ACTIVE flip-flop to be set.
The timing diagram in Figure 4-38 shows the two conditions that generate clock pulses for the SEND ENABLE
flip-flops. At the start of transmission, when TX ACTIVE is
set, signal D5-6 TX ACTIVE (1) H goes high which
generates a positive-going transition at EIO pin 2 to clock
E71. During transmission, TX ACTIVE remains set and
additional clocking pulses are generated only by the CO
positive pulse from TX SHIFf CNTR (E8I) counter at
overflow.
When the DQII is not actively transmitting, it is desired to
keep the line to the data set in the MARK state (outside the
DQII, MARK = low = logical 1.) This is done by gating the
four 1 outputs from the SEND ENABLE flip-flops, via E30
and E82, to one section of AND-OR-invert gate E52. All
four 1 outputs are low which asserts D5-6 VRC/DAT A SEL
L at the output (pin 6) of E52. This signal is sent to the
M78I2 module (04-5) and on via the DFII to the data set.

All other inputs (B3, A2, Al and BO) are permanently
connected to ground.
Figure 4-39 shows the SYNC/DATA ENABLE mux and
associated gating for the STB and SO inputs. It also shows
the character count logic which is not active during this
discussion. Operation of the SYNC/DATA ENABLE mux is
explained by showing two typical examples using sync
characters only. Examples using data characters are
described in the subsequent discussion of the character
count logic because it is used in conjunction with the
SYNC/DATA ENABLE Mux only when data is enabled.
Example 1 (Sync character of 8 bits or Jess.)
When a sync character of 8 bits or less is used, it must be
loaded into both bytes of the SYNC register. As a result,
only one byte of the SYNC register output mux has to be
enabled. It happens to be the low byte mux (E32 SEND
SYNC 7-0 on print D4-7).
1.

For characters of 8 bits or less, the MSB output
of TX BIT CNTR (E86) is always low. This
Signal (D5-6 TX BIT CNTR 8 (1) H) is inverted
by EI5 and sent to pins 10 and 11 of 3-input
NAND gate E88. The third input (pin 9) comes
from the 0 output of the CHAR CNT flip-flop.
It is also high because CHAR CNT is cleared.
This drives the output (pin 8) of E8810w. This
signal is sent to the select (SO) input of the
SYNC/DAT A ENABLE multiplexer. The A
input of the multiplexer is selected when this
select input is low.

Because a sync character is to be transmitted,
output R2 (1) of the SEND ENABLE flip-flop
is high. This signal is sent to inputs A3 and B2
ofE76.

The carry (CO) output of TX SHIFT CNTR
(E81) is not active so it is held low. This signal
goes to E6I pin 4 and drives the output (pin 6)
of this gate high. Thi~ high is inverted by E95
to put a low on the STB input of E76 which
enables it.

The 1 outputs of the SYNC and Data sections of E7I are
sent to the inputs of the SYNC/DATA ENABLE multiplexer (E76) which is described below.

SYNC/DATA ENABLE Multiplexer
The SYNC/DATA ENABLE multiplexer (E76) generates
the enabling signals for the output multiplexers in the TX
shift register (D4-5) and the SYN register (D4-6).
These Signals are listed below:
Signal Name
D5-6 TX SYNC EN 7-0 L
D5-6 TX SYNC EN 15-8 L
D5-6 TX DATA EN 7-0 L
D5-6 TXDATA EN 15-8 L

E76 is a quad 2-line-to-I-line multiplexer with common
select (SO) and enable (STB) inputs. The STB input must be

4-70

E76
74S158
SYNC/DATA
ENABLE
10

-----B3

11
SYNC ENABLE input ~-+---I
A3
from E71 R2 (1 )
13
B2
14
A2

- - -

-05-6 DATA EN 15-8L

---~

......

05-6 DATA EN 7-0L

- - --STB

CO PULSE
04-3 VRC (1)H
05-6 BCC EN (1 )L
10

05-6 TX BIT CNTR B (I)H

BO
AO

CHAR

05-6 TX SYNC EN 7-0 L

05-6 TX SYNC EN 15-8L

6
DATA ENABLE Input ~-+---I
B1
from E71 R3 (1 )
5
A1
3

CNT(O)H~

Low selects
A inputs.
High selects
B inputs.

~
11-2753

Figure 4-39 Sync/Data Enable Multiplexer and
Associated Logic

Example 2 (Sync characters of from 9 to 16 bits.)
Characters of this length require both bytes of the SYNC
register output multiplexer to be enabled. This example
assumes 12-bit characters.

The A inputs of E76 are transferred in complemented form to the four outputs (F3-FO).
Disregarding the data enable signals (Fl and
FO), the sync enable signals appear as follows.
D5-6 TX SYNC EN 15-8 L is high at output
F2 because input A2 is low (ground). This
signal is not asserted.
D5-6 TX SYNC EN 7-0 L is low at output F3
because input A3 is high. This signal is asserted.
It is sent to SYNC register output multiplexer
E32 (print 04-7) to enable the low byte.

As the counter is incremented, this byte is
serialized and sent to the serial data out line.

4-71

At the time of loading, the MSB output of TX
BIT CNTR (E86) is low. This signal (D5-6 TX
BIT CNTR 8 (1) H) selects the A input of the
SYNC/DAT A ENABLE multiplexer as
described in step 1 of Example 1.

The SYNC/DATA ENABLE multiplexer is
enabled as described in Example 1. Only signal
D5-6 TX SYNC EN 7-0 L is asserted which
enables SYNC register mUltiplexer E32 (print
D4-7) which serializes the low byte of the sync
character as the counter is incremented from
count 0 through 7 10 ,

On the next count (8 10 ), the MSB output of
TX BIT CNTR (E86) goes high. This drives E88
pin 8 high which selects the B input of the
SYNC/DATA ENABLE multiplexer. This
asserts D5-6 TX SYNC 15-8 L at output F2 of
the mux because input B2 is high.

low and high byte enabling signals for the TX data register
output multiplexers when in the double-character mode (8
bits or less per character).
This logic is not used when TX data is being processed in
the single-character mode (9 to 16 bits per character). When
in this mode, the TX bit counter MSB input (D4-3 BITS 11
(1) H) is always low. This signal is sent to the clear input of
the CHAR PENDING flip-flop and holds it in the clear state
which inhibits the character count logic.

D5-6 TX SYNC 15-8 L enables SYNC register
multiplexer E29 (print D4-7) and the serialization of the high byte starts. It stops at count
11 10 (12th bit) when TX SHIFT CNTR (E81)
overflows and puts itself and TX BIT CNTR
(E86) in the load mode. The 12-bit sync
character has been serialized and sent to the
data out line.

The character count logic is not required when processing
sync characters in the double-character mode as described
in Example 1 of the SYNC/DATA ENABLE Multiplexer
discussion. It is rendered inactive by blocking the clock
pulses for the CHAR PENDING flip-flop. When data is not
enabled, output R3 (1) from the SEND ENABLE flip-flop
is held low. This signal is sent to E66 pin 1 to prevent a
clock pulse when the CO pulse from the counter is
generated.

Character Count Logic
The character count logic (Figure 4-40) is used to switch
the SYNC/DATA ENABLE mux inputs to generate both

+3V
From 0 output of
1 - shot E64 that
is triggered when
TX SH REG is
loaded.

2 D

E67
7474
CHAR
PENDING

3 C
From 1 output of
DATA section of
SEND ENABLE
flip flop. H iOh
when data is
enabled.

4
PRE

12 D

PRE

9
TO E83 pin 9

E67
7474
CHAR
CNT

11 C
CLR
13
From 0 output of

FAKE END flip flop.
This signal is
normally high.

04-3 BITS 11 (1)H

To priority logic
and DATA SYNC

Inhibits this logic

logic.

during single
character mode.

Clock Signals
11-2751

Figure 4-40 Character Count Logic

4-72

To describe the typical operation of the character count
logic, assume that 8 bit data characters are being processed
(double-character mode).
1.

The output of E66 pin 3 that clocks CHAR
PENDING is in the form of a positive pulse
because it is controlled by the CO pulse from
TX SHIFT CNTR. The output of E66 is
inverted by E70 and sent to the clock input of
the CHAR CNT flip-flop. When the positive CO
pulse times out, a positive-going transition is
generated at E70 pin 10 which clocks CHAR
CNT and sets it.

When CHAR CNT is clocked it is set. Its 0
output goes to E88 pin 9 and drives the output
(pin 8) of this gate high.

The high from E88 pin 8 is the select signal for
the S:YNC/DATA ENABLE mux which now
switches from the A input to the B inpu t. This
asserts D5-6 TX DATA EN 15-8 L which is
sent to the TX shift register output mux (E20)
to enable the high byte of the register. This
8-bit character is serialized as the counter
increments toward overflow.

The 0 output of CHAR CNT, via E66 pin 6,
puts a iow on the D input of CHAR PENDiNG
and CHAR CNT. When the overflow occurs
after serializing the high byte, the CO pulse
leading edge clocks CHAR PENDING which
clears it. When the CO pulse times out, its
trailing edge clocks CHAR CNT which clears it
also.

Initial conditions are as follows.
a.

CHAR PENDING flip-flop is directly set
by one-shot E64 when TX shift register is
loaded. CHAR CNT flip-flop is cleared.
The D inputs of both flip-flops are high
via E66 pin 6. This pin is high because
both E66 inputs are high: pin 4 is high
because CHAR CNT is cleared and pin 5
is high because the FAKE END flip-flop
is cleared.
TX SHIFT CNTR (E81) is loaded with
1000 (LSB to the left) to designate that 8
bits per character has been selected. TX
BIT CNTR input MSB is high which
inhibits the clear inputs of the CHAR
PENDING and CHAR CNT flip-flops.

Under the initial conditions, all three inputs
(pins 9, 10 and 11) of EBB arc rJgt'1 wrJch
drives its output (pin 8) low. This Signal puts a
low on the select (SO) input of the SYNC/
DATA ENABLE mux (E76).

The carry out pulse (CO) output of TX SHIFT
CNTR (E81) is low which enable& E76 via gates
E6l and E95. Data is enabled so the R3 (1)
output from the SEND ENABLE flip-flop puts
a high on inputs Bl and AO of the SYNC/
DATA ENABLE mux.

With the mux enabled and its SO input low, the
A input is selected. This asserts D5-6 TX DATA
EN 7-0 L which is sent to the TX shift register
output mux E21 (print 04-5) to enable the low
byte of the register. This 8-bit character is
serialized as the counter increments toward
overflow.

At overflow, TX SHIFT CNTR (E81) generates
a positive pulse at the CO output. This pulse is
sent to E66 pin 2 and drives the output (pin 3)
high. (The other input (pin 1) is high because
data is enabled.) The positive-going transition at
E66 pin 3 clocks the CHAR PENDING flip-flop
which has no effect because it is already set.

The character count logic is now in its original state. Both
8-bit characters have been serialized.

Save Sync Logic
When the DQll is not transmitting (TX GO cleared), idle
characters can be selected for transmission. In the nontransparent mode, the idle character is the contents of the
sync register. In the transparent mode, the idle character is
Data Link Escape (DLE) followed by the contents of the
sync register; that is, DLE-SYNC, DLE-SYNC, etc.
The save sync logic controls the enabling of sync and DLE
characters during the idle mode. This logic consists of the
SAVE SYNC flip-flop and some gating (E70 and E6l) to its
D input. The logic is located at the left center of print
D5-6.
Assume that idle characters are to be transmitted in the
non-transparent mode. SAVE SYNC starts in the set state

4-73

which is accomplished by D5-6 INI L to its preset input
(pin 4). D8-5 TX TRANS (1) L is high and is inverted by
E70 to put a Iowan E61 pin 2. This holds the output of
E61 (pin 12) high which is sent to the D input of SAVB
SYNC. With this flip-flop in the set state and with its D
input held high, it cannot change state when it is clocked
by the CO pulse from TX SHIFT CNIR (E81).

Vertical Redundancy Check (VRC) Logic
When selected, the VRC logic examines the data to be
transmitted and puts a MARK (logical 1) in the most
Significant bit of each character if required to make the
total number of MARKs, including the VRC bit, even or
odd as selected.

With the total transparent mode inhibited and idle mode
active, the output (pin 8) of E65 is low. This puts a Iowan
E56 pin 6. The other input (pin 5) of E56 is also low
because the CHAR PENDING and DATA ROY flip-flops
are cleared. The resulting high from E56 pin 4 drives the
output (pin 1) of the next E56 gate low. This low is sent to
pin 11 of the third E56 gate in the priority iogic. The other
iTlput (pin 12) of this gate is also low because a DLE
character is not being requested. The output (pin 13) of the
third E56 gate is high and is sent to the D input (E71 pin
12) of the sync section of the SEND ENABLE flip-flop.
This sets up the SYNC/DATA ENABLE mux to generate
the enabling signal for the sync register.

Before discussing the VRC logic, the following prerequisite
information is presented.

Assume now that idle characters are to be transmitted in
the transparent text mode; that is, DLE-SYNC, DLE-SYNC,
etc. SAVB SYNC starts in the set state but its D input is
low via E61 pin 12. When the transparent text mode is
selected, D8-5 TX TRANS (1) L is asserted, inverted by
E70, and makes the third input (pin 2) of NAND gate E61
high which drives its output low. This low signal is also sent
to E65 pin 2 which drives its output high regardless of the
state of the other input. This high signal goes to the D input
(E71 pin 4) of the DLE section of the SEND ENABLE
flip-flop. This results in assertion of the DLE enabling
signal. Thus, the signal from E61 pin 12 allows the enabling
of a DLE character without a DLE request being asserted.

Total data character length, with VRC activated, includes a VRC bit in the most significant place. The maximum length of a single
character is 16 bits but only 15 bits contain
data. The data bits/character should be selected
as 15 with the VRC logic adding the last bit.
For double characters, the data bits/character
should be selected as 7.

MARK and SPACE are the terms used to
identify the binary states of a communications
line. Because of the signal inversion performed
by the DFll converters that interface the line
with the DQ 11, MARK and SPACE are defined
as follows.

Outside the DQll. After passing through the
DFll (transmit mode) or prior to entering the
DFll (receive mode), the definition is:
SPACE = HIGH = LOGICAL 0
MARK = LOW =LOGICAL 1

Inside the DQ11. Prior to entering the DFll
(transmit mode) and after passing throug..~ the
DFll (receive mode), the definition is:

The DLE character is counted up and overflow occurs. The
CO pulse from TX SHIFT CNTR (E81) clocks SAVE SYNC
which clears it. The low from the 1 output of SAVB SYNC
is fed back to E61 which drives its output (pin 12) high.
This high goes to E65 pin 2 and drives the output (pin 3) of
this gate low. This Signal inhibits the enabling of DLE. It
also goes to E56 pin 12 which drives its output (pin 13)
high to allow enabling of the sync character.

SPACE = HIGH = LOGICAL 1
MARK = LOW = LOGICAL 0
Internally, reference points for transmit and
receive data are as follows.
TRANSMIT DATA - Signal 04-7 SERIAL
DATA OUT L (Prints D4-7 and Dl-1)

At the end of the sync character, the CO pulse clocks
SAVB SYNC which sets it and allows another DLE
character to be enabled. Hence, the DLE-SYNC cycle is
repeated.

RECEIVE DATA - Signal Dl-1
DATA L (Prints Dl-1 and 04-3)

4-74

RECEIVE

If even parity is selected, the VRC logic counts
MARKs in the character and puts a MARK in
the MSB position only if an odd number of
MARKs is detected. With even parity, the total
number of MARKs, including the VRC bit, is
always even. Similarly, with odd parity, the
total number of MARKs, including the VRC
bit, is always odd.

To describe the operation of the VRC logic, assume the
following conditions.
I.

Even VRC is selected.

An 8-bit character is to be transmitted and that
three MARKs appear in the 7 data bits of this
character.

AND-OR-invert gate E52. The output of E52 goes high
because its other input is held low. This output signal is
D5-6 VRC/DATA SEL L and it is sent to pin 5 of E23 on
the M7812 module (print 04-7). E23 is an 8-input NAND
gate (shown as the logically-equivalent, negated-input OR
gate). The last (7th) data bit has been sent and BCC is not
selected so all 8 inputs are high which drives the output
low. This low is inverted by E67 (print D4-7) to put a high
(SPACE) in the 8th bit of the transmitted character. At this
point (E67 pin 10) the signal is D4-7 SERIAL DATA OUT
1. This is the transmit serial data signal1ine that goes to the
DFII.
The VRC logic detected four MARKs in the 7-bit data
character and put a SPACE in the 8th bit because even
parity is selected.
Fake End Logic
In the double-character mode with an odd count detected,
only the low byte of the last character contains a character
to be transmitted. Under these conditions, it is desired to
end the transmission and not waste time with the empty
byte. This permits the next NPR to be started sooner and
allows the TX BCC logic, if selected, to append the BCC
character in the correct place.

Under these conditions, the VRC logic should detect the
odd number of MARKs and put a MARK in the 8th bit
position.
Figure 4-41 shows the VRC logic and graphical representation of the daia characier used in the example.
The transmitter data to be examined is 04-7 TX DATA H.
It is inverted by E74 and is sent to pin 2 of exlcusive-OR
gate E84. At this point, the data is equivalent to 04-7
SERIAL DATA OUT L which is sent to the DFl1. The
other input (pin 1) of E84 is connected to the 0 output of
the ONES CNT flip-flop. The output of E84 goes to the D
input of this flip-flop.

As an aid to understanding the operation of the ONES CNT
flip-flop, Figure 442 shows the truth table for the X-OR
gate and a chart that shows the conditions necessary to
change the state of the flip-flop. ONES CNT is clocked by
D4-3 TX CLOCK H which is the transmit clock signal.
Input gating to the clear input (pin I) of ONES CNT allows
it to be cleared by the CO pulse when the counter
overflows. If TX ACTIVE is not asserted, ONES CNT is
cleared and held in that state.

The fake end logic consists of the SAVE ODD CC and
FAKE END flip-flops and NAND gate E65.
When the transmit control logic requests an NPR, the
TX/RX CYCLE flip-flop in the NPR control logic is set and
asserts D5-3 TX CYCLE H which is sent to E65 pin 4.
During updating of the CC register, the CC ODD flip-flop is
set if an odd count is detected. This asserts D5-1 CC ODD
(l) H which is sent to the other input (pin 5) of E65. This
drives the output of E65 low which sets SAVE ODD CC via
its present input (pin 4).
The 1 output of SAVE ODD CC puts a high on the D input
of FAKE END. In the process of starting the next NPR, the
DATA SYNC flip-flop is cleared. The positive-going transition from its 0 output clocks both FAKE END and SAVE
ODDCC.
FAKE END is set and its 1 output, which is designated
D5-6 TX FAKE END (1) H, is sent to module M7816 to get
the BCC logic started sooner. The 0 output of FAKE END
is sent to E66 pin 5 to put a low on the D input of the
CHAR PENDING flip-flop to inhibit the character count
logic because there is no need to enable the high byte.

The sample data character (Figure 4-41) is sent to the VRC
logic via Signal 04-7 TX DATA H. As indicated, the I
output of the ONES CNT flip-flop is low during the 7th
(last) data bit. This signal is sent to pin 5 of X-OR gate E84.
The other input of this gate (pin 4) is low because even
parity is selected (SW4 is ON). The output (pin 6) of E84 is
low and is sent to the D input of the VRC HOLD flip-flop.
The TX bit counter overflows at the 7th data bit and the
CO pulse clocks VRC HOLD which clears it. The low Signal
from the 1 output of VRC HOLD goes to input pin 4 of

SAVE CC ODD is cleared when it is clocked. This inhibits
the logic until a subsequent odd count presets SAVE CC
ODD.
4-75

LOGIC LEVELS
Outside the DQ11 (output of OF 111
Inside the DQII (04-7 SERIAL DATA OUT L)
SPACE = H = Logic 0 =+15V
SPACE =H = Logic I =+5V
MARK" L =Logic I =-15V
MARK =L· Logic 0 =OV
+3V

,..3
_ _.....;2-10
7474 1
ONES
CNT
3
4
3
04-3 TX CLOCK H----1r--aF74>---~C

8 CLR

05-6 TX ACTIVE (IlH

+3V
10
E87

~
5
6

0 7474
VRC
HOLD

JL..

~~: j:"::E1EVE: :.:::
I

SW ON =low =even VRC
SW OFF=high=odd VRC

-=
JL.
CO PULSE

04-3 VRC (1) H 3
..rt. CO PULSE 4
05-6 BCC EN (1) L 5

r--------------- I

M7812 MODULE

I
I
I

8
OFI1

To Modem

04- 3 TEST

IL _ _ _ _
' - - - -..... 04-7 TX SERIAL DATA OUT L

' - - - - - - - - - - - - - - - ' - - 04-7 TX DATA H

TX CLOCK

II I I r rI I

VRC
LOGIC

t---,.IL.--. 05 - 6 VRC/OATA SEL L

M7813
TX OAT~ H
E74 pin 1 .."

-;1L...:::...J
02 r;;1 04 ~
..,'" L:J ..,"':..,0 L-

TX DATA H
E74 pin 2

10utput of
ONES CNT
flip flop

---1

L..J

L.J--.J

n ...___t

'--__~

,---------l
:
-Lr i
, !~L

t( ~~!:e~ ~;~:ra~aAt~~~.i~t

INV
E2 3

looks the some as serial
data out of the OF 11.

co PULSE occurs here.

L -M7812 -

VRC logiC adds last bit.

_...J

OFll
(NON -INV)

..s-L To Modem

04-7 SERIAL DATA OUT L

( 04-7)
' - - - - - - - - - ' - - - 04-7 TX DATA H

S
NOTE: 1. VRC logic detects 4 MAR KS.
2. If even parity is selected, VRC HOLD flip flop is cleared.
05-6 VRC/DA T A SE L L goes high and is sent to E23 on
M1812 module (04-1). This makes 04-1 TX DATA H low
which adds a SPACE to the 8th bi t. Data plus VRC bit
shows 4 MARKS (even parity).
3. If odd parity is selected, VRC HOLD flip flop is set.
05-6 VRC/DATA SELL goes low and is sent to E23 on
M1812 module (04-11. This makes 04-1 TX DATA H
high which adds a MARK to the 8th bit. DATA plus VRC bit
bit shows 5 MARKS (odd parity).

04-7 SERIAL DATA OUT L

OF11
(NON-INV)

To Modem

Even Parity Selected

S
M

OFll
04-7 SERIAL DATA OUT L
Odd Parity Selected

(NON-INV)

To Modem
11-2756

Figure 4-41 Transmit VRC Logic and Sample Data Character

4·76

Certain conditions relating to a TX NPR request ar~ sensed
by signals that are sent to NAND gate E4S. This gate and
E79 provide a delay in setting up the DATA RDY flip-flop
to ensure that a transmit NPR is in progress. The CC/BA
register is in the BA mode (DS-3 CC/BA CYCLE H is not
asserted); DS-3 TX CYCLE H is asserted by the NPR
control logic; and DS-6 TX ACTIVE (0) H is asserted
because the TX ACTIVE flip-flop is cleared. The resulting
high from E4S pin 12 is ANDed with the high from the 1
output of DATA SYNC at AND gate E79. This puts a high
on the D input of DATA RDY. The next positive transition
of the inverted TX clock signal from E74 pin 4 clocks
DATA RDY and sets it. The 0 output of DATA RDY sets
up the TX ACTIVE flip-flop and the data section of the
SEND ENABLE flip-flop to allow the next positive
transition of D4-3 TX CLOCK H to set TX ACTIVE which
in turn allows data to be enabled.

TX DATA ~ To D input of
1
E84
.
From 0 output
ONES CNT flIp flop
of ONES CNT
flipflop
X- OR Gate

X-OR Truth Table

5 tate Table for ONES CNT flip flop
ONES CNT flip flop
Present State

D Input

low

cleared

high

set

high

cleared

low

no change

low

set

low

cleared

set

high

no change

TX DATA

high

State After Clock

Return in time to the point at which the DATA RDY
flip-flop is clocked by the positive transition of the inverted
TX clock signal from E74 pin 4. This signal puts a high on
pin 10 of E6O. Pin 12 is high because CHAR PENDING is
cleared; and now pin 9 is high because DATA RDY is set.
With all four inputs high, the output (pin 8) of E60 goes
low. When the inverted TX clock sigtial goes low again, E60
pin 8 goes high. This positive edge is DS-6 LD TX SH REG
H which clocks the data from the transmit buffer into the
shift holding register (E22, Ell and E19 on print D4-S).
This edge also clocks the DATA SYNC flip-flop which
clears it. It also triggers one-shot E64 which generates a
negative pulse that directly sets the CHAR PENDING
flip-flop. The 1 output of DATA SYNC, which is low,
drives the D input of DATA RDY low via E79 pin 6. When
the inverted TX clock signal goes high again, this positive
transition clocks DATA RDY which clears it.

11-2752

Figure 4-42 X-OR Truth Table and
State Chart

Data Sync/NPR Logic
The data sync/NPR logic is shown in Figure 4-43. Although
both sections of this logic are interrelated, they can be
discussed separately in sequence.

The data sync section consists of the DATA SYNC and
DATA RDY flip-flops and associated gating.

When DATA SYNC is cleared, its 0 output goes high. This
positive-going transition clocks NPR RQ and TX LATE
simultaneously. Both of these flip-flops start in the cleared
state. The D input of TX LATE is low because NPR RQ is
cleared and the D input of NPR RQ is high because D4-4
TX GO (1) H is asserted. Therefore, NPR RQ is set which
asserts DS-6 TX NPR RQ (1) L. This signal goes to the NPR
request logic (print DS-3). TX LATE is cleared which keeps
DS-6 TX LATE L unasserted. If NPR RQ is still set when
DATA SYNC gets cleared, TX LATE is set which asserts
DS-6 TX LATE L. This action denotes that the previous
NPR request was not serviced in less than one character
time. DS-6 TX LATE L sets bit 2 (TX LATENCY) of the
REG/ERR CSR which in turn generates an error interrupt
flag and clears TX GO to stop further TX NPR requests.

The discussion begins at the start of a transmit operation
with the following conditions.

DATA SYNC is in the set state. This was
accomplished by DS-3 TX NPR DONE H at the
end of the previous NPR cycle.

DATA RDY is in the cleared state.

The TX shift register is empty_

4-77

TX ACTIVE (0) H

05- 3 CC/BA CYCLE H
+3V

05-3 TX CYCLE H

05-6 TX ACTIVE (I) H 10

L..J"" CO PU LS E 9
CHAR PEND (0) H - - t - - - - - ,

TO PRIORITY
LOGIC

05-6 Lo TX SH REG H

E69
74123
13
STARTO 4

05-6 TX LATE (O)H
CLR

3
04-4TXGO(I)H~--~--~~--~~----~--------------~

+3V

05-6 TX NP RQ (I) L

11-2788

Figure 4-43 Data Sync /NPR Logic

The START one-shot is used to force the NPR request if
044 TX GO (1) H is asserted when DATA SYNC is
cleared. In this situation, D44 TX GO (1) H going high,
triggers one-shot START. The 50 ns positive pulse from the
1 output of START is ANDed with the high from the 0
output of DATA SYNC at E75. The resulting low from the
output (pin 3) of E75 sets NPR RQ directly via its preset
input (pin 4).

Three switches are used in this logic.

Switch
SWI

Description
Set to ON for two sync characters to
frame.
Set to OFF for one sync character to
frame.

4.5.7 Receive Start Up and VRe Logic
SW2

4.5.7.1 Functional Description - In the receive mode, the
start up logic searches for sync characters and when the
proper pattern is detected, it asserts the RX ACTIVE signal
which indicates that the receiver is in the data transfer
mode. It also generates the load signals for the RX buffer
register. Provisions are included to clear the receive start up
logic from three sources: program control of RX ACTIVE,
loss of RX GO, or via the sequence control logic on the
M7817 module.

Set to ON to assert RX ACTIVE on first
non-sync character after framing.
Set to OFF to assert RX ACTIVE when
framing occurs.

SW4

Set to ON for even VRC or OFF for odd
VRC.

4.5.7.2 Detailed Logic Description - The circuit schematics for the receive start up logic and VRC logic are
contained in drawing D-CS-M7813-0-1 (Rev H) sheet 9
which is designated 05-7.

The VRC logic, when enabled, checks the received character for correct parity. If incorrect parity is detected, a
signal is generated that sets the RX VRC error flag (bit 7 of
the REG/ERR CSR).

4-78

Both these signals must be high to permit the counting
function. If they are low, counting is inhibited but the load
function can still be performed.

Receive Start Up Logic
The receive start up logic is discussed by setting up specific
sync detection and framing requirements and following the
sequence of operations.

At the start of the sync detect operation, the SYNC 1
flip-flop is cleared which inhibits counting by putting a low
on the counter CNT EN and CRY EN inputs. The SYNC 1
WAIT flip-flop starts in the cleared state. The high signal
from its 0 output asserts DS-7 ill RX BIT CNTR L at E82
pin 13. This is the load signal for the counter and the
selected number of bits per character is loaded into the
counter because the clock (04-3 RX CLOCK H) is running.
As the sync detect operation progresses, the SYNC 1
flip-flop is set and counter inputs CNT EN and CRY EN go
high which allows RX BIT CNTR to count up. Subsequently, the SYNC 1 WAIT flip-flop is set which puts a
low on pin 12 of E82. Now the counter load signal can be
generated only when the counter overflows and sends the
positive CO pulse to E82 pin 11.

Before discussing the specific example, it is advisable to
describe the operation of the RX bit counter which is an
integral part of the logic.
The RX BIT CNTR (E80) is a 74161 synchronous 4-bit
counter (Figure 4-44). The four inputs (pins 3-6) come
from MISC register bits 8-11 which select the number of
bits per character. The outputs are not used. The counter is
used only to detect the end of the frame which occurs
when the counter overflows and generates the carry out
(CO) pulse. The counter can be cleared by DS-4 INI H or
by the reset logic. In either case, the clear signal comes
from E82 pin 1.
The load signal for the counter is DS-7 ill RX BIT CNTR
L. When it is low, the counting function is disabled and the
outputs are forced to agree with the inputs after the next
clock pulse. The clock signal is D4-3 RX CLOCK Hand
clocks the counter on the positive-going transition. The
count enable (CNT EN) and carry enable (CRY EN) inputs
are connected to the 1 output of the SYNC 1 flip-flop.

04-3 BITS 11 (1) H

6 MSB

04-3 BITS 10 (1) H

5
4

04-3 BITS 9 (1)H
04-3 BITS 8 (1) H

E80
74161
RX BIT
CNTR

The discussion now explains the operation of the start up
logic for a specific situation. Assume that SWI is ON which
requires that two sync characters be detected to ensure
framing and the DQl1 is operating in the single-character
mode with an even number of characters in the message.

From Reset logic

04-3 RX CLOCK H
r---~CllO

,.----,'-----,. CN TEN
From 1 output of
SYNC 1 flip flop.
SYNC 1 starts cleared
so this signal is low.
It permits loading while
inhibiting counting

t----t CRY EN

+3V

~______~~______'-t2 0

E86 1
7474
SYNC 1

04-3 RX ClK H

SYNC 1 WAIT starts cleared.
High signal enables initial
loading of RX BIT CNTR.

WAIT 0 8

i-=----~

ClR
13

X)....13
_ _ _ _--r- 05-7 lO RX
BIT CNTR l

From Reset logic
After a sync character
is detected, SYNC 1
is set. Subsequent
loading is enabled
by CO pulse.
11-2765

Figure 4-44 RX Bit Counter and Associated Logic
4-79

Assume that SW2 is ON which allows RX ACTIVE to be set
on the first non-sync character after framing (Figure 4-45).

The starting conditions are as follows:

D4-4 RX GO (1) H is asserted.

A sync character has not been detected
yet. D4-7 RX SYNC DET H is low. This
puts a low on the D input of both SYNC
1 and SYNC 2.

SYNC 1 and SYNC 2 are both cleared.
The feedback from the 0 outputs of
SYNC 1 and SYNC 2 and one-shot CNTL
PUlSE conditions the clock steering
gates (three E85s) to allow the receiver
clock signal (D4-3 RX CLOCK H) to
reach SYNC 1 and SYNC 2.

SYNC 1 WAIT is cleared. This allows
assertion of D5-7 LD RX BIT CNTR L at
E82 pin 13. The counter is loaded but it
cannot count because the CNT EN and
CRY EN inputs are held low via the 1
output of SYNC 1.

The first sync character is shifted into the RX
shift register and then into the RX buffer at
which point it is detected so D4-7 RX SYNC
DET H is asserted. E96 pin 11 goes high and is
sent to the D input of SYNC 1. The low signal
from the 1 output of SYNC 1 (which is cleared)
goes through SWI to keep a low on the D input
of SYNC 2.

The next negative-going transition of D4-3 RX
CLOCK H is inverted three times by the clock
steering gates and appears as a positive-going
transition at E85 pin 8. This transition clocks
SYNC 1 which sets it. SYNC 2 remains cleared.

+5V
2

04-7 RX SYNC OET H 13
04-4 RX GO (1)H 12

SW2

~----~----+-----------~-----------4--~E95

04-3 RX CLOCK H

From 0 output
of CNTL PULSE
one - shot
SWITCH SETTINGS
S WI ON
SWI OFF

SW 2 ON

2 SYNC Characters to frame
1 SYNC Character to frame

RX ACTIVE set an first non -SYNC
character after framing
SW2 OFF - RX ACTIVE set when framing occurs

04-2 012 H

04 -4 LO RX 15-8 H

F rom Reset Logic ---I'--______________- - J

+3V
,,- 2764

Figure 4-45 Receiver Start Up Logic

4-80

When SYNC 1 sets, the low signal from its 0
output is fed back to E8S pin 2. This drives the
output (pin 3) of E8S high and blocks the
clocking signal for SYNC 1 and SYNC 2. The
high signal from the 1 output of SYNC 1 is sent
to the D input of SYNC 2 via SWI and E96 pin

When the negative pulse from the LD BUP
one-shot times out, its positive-going trailing
edge triggers one-shot CNTL PULSE which
generates complementary SO ns pulses. When
the negative pulse from the CNTL PULSE
one-shot times out it drives E8S pin 8 high
(Figure 4-44). This positive-going transition
clocks SYNC 2 and sets it.

10.

When SYNC 2 sets, the low signal from its 0
output is fed back to E8S pin 10 to block
further clocking of SYNC 1 and SYNC 2. The 1
output of SYNC 2 puts a high on pin S of
3-input NAND gate E88. Pin 3 of this gate is
high because the RX ACTIVE flip-flop is
cleared. The third input (pin 4) of E88 is low
because of the inverted output (pin 11) of E96.
The second sync character has been detected so
this point (E96 pin 11) remains high.

11.

When the first data character is shifted in, D4-7
RX SYNC DET H goes low because this
character is a non-sync character. Pin 4 of E88
now goes high which drives the output (pin 6)
of t!lis gate 10\''1. This si&~al directly' sets the p~
ACTIVE flip-flop via its preset input (pin 4).
The 1 output of RX ACTIVE (DS-7 RX
ACTIVE (1) H) is inverted by E9S, delayed
SOO ns by RC network R44-CllS and drives
the output (pin 6) of E88 high which inhibits
the preset input of the RX ACTIVE flip-flop.

12.

At the last bit of the second sync character, RX
BIT CNTR overflows and generates the CO
pulse which in tum generates another load
pulse for the counter. The second sync character is loaded into the RX buffer register as
described in item 8.

6.
S.

The 1 output of SYNC 1 drives the CNT EN
and CRY EN inputs of the counter high.
Nonnally, this would enable the counter and
allow it to start counting; however, the ioad
(LD) input is still low. This inhibits the
counting operation even when CNT EN and
CRY EN are enabled.
The 1 output of SYNC 1 also puts a high on the
D input of SYNC 1 WAIT. The next positivegoing transition of D4-3 RX CLOCK H sets
SYNC 1 WAIT. The 0 output of SYNC 1 WAIT
puts a low on E82 pin 12. The other input (pin
11) is low because the CO pulse is not enabled.
This drives the output (pin 13) of E82 high
which inhibits the counter load signal (DS-7 LD
RX BIT CNTR L is pjgh.). The next positivegoing transition of 04-3 RX CLOCK H increments the counter which starts the count up
sequence. SYNC 1 WAIT forced a one clock
pulse time delay in allowing RX BIT CNTR to
count after SYNC 1 was set.
Nothing happens in this logic while the second
sync character is shifted in to the RX shift
register until the last bit is counted. At the last
bit, RX BIT CNTR overflows and generates the
positive carry out (CO) pulse. This generates
another load pulse (DS-7 LD RX BIT CNTR L)
for the counter.

The start up logic has accomplished its job; that is, it
recognized two sync characters to frame the message and
set RX ACTIVE on the first non-sync character following
framing. SYNC 1, SYNC 2 and TX ACTIVE remain set
until they are directly cleared by the reset logic.

The positive-leading edge of the CO pulse
triggers one-shot LD BUP which generates
complemen tary 100 ns pulses. The positive
pulse goes to E82 pin S which asserts DS-7 LD
RX BUP IS-8 L at the output of this gate.
This is the load signal for the high byte of the
RX buffer register (D4-S). This signal is sent to
the RX character control logic (print DS-8)
where it is used to assert DS-8 LD RX BUF
7 -0 L which is the load signal for the low byte
of the RX buffer register. The second sync
character has been loaded into the RX buffer
register and is detected at this point.

Force Framing
The start up logic can be conditioned to be framed at the
first received character. This can be accomplished through
program control.
The RX ACTIVE flip-flop is bit 12 of the RX CSR. The
program puts a high on the D input of RX ACTIVE using

4-81

04-2 DI2 H from a bus receiver. When the RX CSR is
addressed, the register decoding logic asserts D4-4 LD RX
IS-8 H which clocks RX ACTIVE and sets it. The 1
outpu t of RX ACTIVE triggers one-shot FORCE FRAME.
The negative SO ns pulse from this one-shot directly sets
SYNC 1 and SYNC 2 via their preset inputs. This

Assume that SWI remains ON but SW2 is now OFF. This
allows RX ACTIVE to be set when framing occurs; that is,
right after the second sync character is detected. With SW2
OFF, pin 4 of E88 is high. When SYNC 2 is set, its 1 output
drives the third input (pin S) of E88 high. The output (pin
6) of this gate goes low and directly sets RX ACTIVE.

synchioilizes the hardware just as if sync characters v/ere
detected.

Resetting the Start Up Logic
Once the start up logic has performed its job, it is not
returned automatically to its original state. The reset logic
performs the task of clearing the start up logic. The reset
action cail be initiated fmm four outside sources:

Assertion of DS-4 INI H which is caused by a
BUS INIT L signal or MASTER CLEAR (MISC
register bit S).

Clearing RX ACTIVE (RX CSR bit 12) by
program control.

Clearing RX GO when character count goes to
zero or if RX GO is inadvertently cleared
during a receive operation.

Assertion of DS-8 CRA DLY L which is a
function of the M78I7 module.

As another example, assume that SWI is OFF which
requires one sync character to frame. With SWI off, pin S
of E96 is high. When a sync character is detected, the other
input (pin 4) of E96 goes high and puts a high on the D
input of SYNC 2. The D input of SYNC 1 is also high.
SYNC 1 and SYNC 2 are set simultaneously. The subsequent setting of RX ACTIVE depends on the state of
SW2. Both conditions (SW2 ON and OFF) have been
discussed previously.
RX VRC Logic
The basic principles of operation of the RX VRC logic are
the same as those described in the TX VRC logic discussion
in Paragraph 4.S.6.2.

When selected, the RX VRC logic examines each received
character to verify that the selected VRC (odd or even) has
been correctly indicated at the source. The RX VRC logic is
shown in Figure 4-46.
For example, assume that the remote location sends an
8-bit character with even parity and that it is received
without error. The sample character is shown in Figure 4-47
and contains four MARKs including the VRC bit in the
MSB position.

The normal way of clearing the start up logic is by program
control of the RX ACTIVE flip-flop. The program forces
the RX ACTIVE flip-flop to the cleared state. When
cleared, the 0 output of RX ACTIVE triggers the ACTIVE
RESET one-shot. The SO ns negative pulse from ACTIVE
RESET drives E83 pin 6 high which in tum drives the
output (pin 1) of E82 low. This low signal directly clears
SYNC 1, SYNC 2, SYNC 1 WAIT, RX ACTIVE, and RX
BITCNTR.

The VRC logic receives this character and it is set to detect
even parity. This is accomplished by setting switch SW4 to
the ON position which asserts D5-7 EVEN VRC L at X-OR
gate E84 pin 12. Assuming that the start up logic has done
its job, the SYNC 1 flip-flop is set and the clear input (pin
13) is high (inhibited). The VRC ONES CNT flip-flop
changes state as it is clocked in accordance with the table in
Figure 4-46. At the last character bit, VRC ONES CNT is
cleared. Its 1 output, which is low, is sent to E84 pin 13.
Because even parity is selected (SW4 is ON), the output
(pin 11) of X-OR gate E84 is low. This drives the output of
E83 high. This signal is DS-7 VRC ERR DET L and goes to
the preset input of the flip-flop that represents the RX
VRC ERR flag (bit 7) of the REG/ERR CSR. Being high, it
does not activate the RX VRC error flag. The message has
been received with the correct parity.

When RX GO is cleared, 04-4 RX GO (1) H goes low and
triggers the GO RESET one-shot. The negative pulse from
GO RESET clears the start up logic the same way that
ACTIVE RESET clears it.
The previous discussion assumed that switches SWI and
SW2 were both ON which required detection of two sync
characters and allowed RX ACTIVE to be set on the first
non-sync character register framing.

4-82

From 1 output of
SYNC 2 flip flop
04-3 VRC (llH
SW4 ON =Iow=even VRC +5V
SW4 OFF =high= odd VRC

09-6 RX BCC CYCLE l
05-7 lO BUF (1)H---,-,,......,,,.-,,,

05-7 VRC ERR OET l

05-7 EVEN VRC l
When asserted, directly
sets REG/ERR bit 7
on M7812 Module. This
is VRC error flag.

04-3 RX ClK H

State Chart for VRC ONES CNT Flip Flop
SERIAL
DATA IN

04-3 RX ClK H 1
from 0 output of 2
SYNC 1 flip flop

VRC ONES CNT Flip Flop
State
Present
o Input After
state
Clock

low

cleared

high

set

high

cleared

low

no change

low

set

low

cleared

high

set

high

no change
11-2763

Figure 4-46 Receiver VRC Logic

At the 8th bit, the counter overflows and the positive CO
pulse is generated. It is double inverted by E85 and E95
and directly clears the VRC ONES CNT flip-flop so that it
is ready to check the next received character.

SERIAL DATA IN

1 output of ONES
CNT flip flop

~n~

1. Even VRC is selected.

Assume that the sample message in Figure 4-47 is received
in error with odd parity. Specifically, assume that the
parity bit is a SPACE. After looking at the whole character,
VRC ONES CNT is set. The output of E84 pin 11, which
goes to E83 pin 10, is high now. The other three inputs to
this 4-input NAND are also high for the following reasons:

2. logic detects 4 MARKS ( data plus VRC bit)
in received character.
3. Character contains even VRC so error flog
is not set.
Example for even VRC and correct RX character

SERIAL DATA IN

1 output of ONES
CNT flip flop

E83 pin 13 is high via AND gate E66 because VRC is
activated and SYNC 1 is set.

E83 pin 12 is high because BCC is not active.
1. Even VRC is selected.

2. logic detects 5 MARKS (data plus VRC bit)
in received character.
3. Character contains odd VRC so error flag Is set.

E83 pin 9 is high because LD BUF is triggered.

Example for even VRC and incorrect RX character

With all inputs high, the output of E83 goes low which
asserts D5-7 VRC ERR DET L. This signal sets the VRC
error flag to indicate that the received character has the
incorrect parity.

11- 2760

Figure 4-47 Sample Message With Received
Data Character and VRC

4-83

4.5.8 Receive Character Control Logic

A specific example is used to describe the operation of the
receive character control logic.

4.5.8.1 Functional Description - A simplified block diagram of the receive character control logic is shown in
Figure 4-48. This logic counts a character as being received
or not. It is conditioned to respond to single-character or
double-character operation. Further discrimination is made
between odd and even character counts.

The initial conditions are as follows:
The receive cycle is just starting. The
SYNC 1 flip-flop is cleared (DS-7 SYNC 1
(1) H is low) which puts a high on E98
pin 4 (top gate) and E98 pin 9 (middle
gate). The clear input (pin 13) of the
SKIP LD NEXT FRAME flip-flop is also
driven low which directly clears it.

When this logic determines that the received character is
what was expected, an NPR request is generated, the
character is sent to the receiver buffer and the receive
character control logic is prepared for the next count.
Additional biasing circuits are used to block character
transfers under certain conditions during character recognition, transparent text or total transparent modes.
4.5.8.2 Detailed Logic Description - The circuit schematic for the receive character control logic is contained in
drawing D-CS-M7813-0-1 (Rev H) sheet 10 which is
designated DS-8.

RX ACTIVE (1) H LD RX BUF (1) L LD RX BUF 15-8 L -

Single-character operation is selected.
D4-3 BITS 11 (I) H is low which puts a
low on E98 pin S (top gate) and a high on
E98 pin 10 (middle gate).

The output (pin 6) of the top E98 gate is
high which inhibits the clear input (pin 1)
of the XFER FRAME START flip-flop.

SKIP LOAD

i
GATING

•

RX SE ARCH DONE L RX TRANS (1) L STRIP SYNC (1) L RX SYNC DET H OLE SAVE (1) L -

NEXT FRAME t - - LD RX BUF 7 -0 L
LOGIC

I
DIS RX TRANS PULSE L

1..

RX TRANS PULSE H

SYNC 1 (1)H

BIASING
LOGIC

TRANSFER
DONE
LOGIC

RX
RESET

-----.

OUTPUT
GATING

r-- CRA DLY L

BITS11(1)H RX CYCLE H CC ODD (1)H -

eRA L -

STRIP DB CHAR L

BIASING
LOGIC

CLR RX L -

RX CCODDL

CLEAR
RX ACTIVE
LOGIC

I - RX N PR RQ (1 ) L

LDMISCHNPR
REQUEST
LOGIC
RX NPR DONE H -

RX LATE L
11-2759

Figure 4-48 Block Diagram of Receive Character Control Logic
4-84

The output (pin 8) of the middle E98
gate is low which puts a Iowan the preset
input (pin 4) of the XFER FRAME
ST ART flip-flop which directly sets the
flip-flop.

No character recognition functions are
enabled; therefore, the clock source for
the XFER FRAME START and XFER
FRAME DONE flip-flops comes from
D5-7 RX TRANSFER PULSE H. XFER
FRAME START is set and XFER
FRAME DONE is cleared but its clear
input (pin 13) is not active now.

Assume that a sync character is the first one
received. The SYNC 1 flip-flop is set which
inhibits the preset input of XFER FRAME
START.

At the end of the character bit count, the RX
start up logic (D5-7) generates D5-7 LD RX
BUF 15-8 L which in tum generates D5-8 LD
RX BUF 7-0 L because SKIP LD NEXT
FRAME is cleared. These signals load the
character in the RX buffer register (04-6). The
outputs of this register go to the inputs of the
buffered RX data register (04-7). Coincident
with the assertion of D5-7 LD RX BUF 15-8
L, the 0 output of the ill BUF one-shot (D5-7
LD BUF (0) H), which is low for 100 ns, is sent
to the clock input of SKIP LD NEXT FRAME.
The positive-going trailing edge of this pulse
sets SKIP LD NEXT FRAME. Normally, this
flip-flop is cleared before the next character
arrives. However, it can remain set if in doublecharacter operation in the character recognition
mode and a subsequent SYNC character is to be
stripped. (This action is described later.)

The 50 ns pulse from the RX RESET one-shot
directly sets the RX NPR RQ flip-flop via gate
E38. When the flip-flop is set, it asserts D5-8
RX NPR RQ (1) L. This signal starts the NPR
request sequence. It also generates D5-3 RX
NPR L that clocks the buffered RX data
register and puts the character on the Unibus
data lines to be transferred to memory during
the NPR cycle.
The negative pulse from the RX RESET oneshot directly clears the XFER FRAME DONE
flip-flop.
Normally, the RX NPR RQ flip-flop starts in
the cleared state. If it was still set when RX.
RESET is triggered, the leading edge of the
positive pulse from RX RESET clocks the RX
LATE flip-flop and sets it. This asserts D5-8 RX
LATE L which denotes that the previous NPR
request was not seIViced in less than one
character time. D5-8 RX LATE L sets bit 3
(RX LATENCy) of the REG/ERR CSR which
in tum generates an error interrupt flag and
clears RX GO which shuts off the receiver.
The other input to AND-DR-invert gate E38
(pins 4 and 5) is bit 4 (RX NPR) of the MISC
register. It is used during seIVicing, when RX
ACTIVE is cleared, to force an RX NPR. In this
mode, the data transferred to memory is the
contents of the RX shift register rather than the
contents of the buffer register. The BA/CC
register is also updated.
In the character recognition mode, certain
conditions bias the logic to prevent an NPR
request from being generated. The received
character is not sent to memory; in effect, it is
stripped from the message.

Approximately 100 ns after D5-7 LD RX BUF
15-8 L is asserted, D5-7 RX TRANSFER
PULSE H is asserted for approximately 50 ns.
When this signal goes high, it generates a
positive-going transition at E99 pin 6 that
clocks XFER FRAME START and XFER
FRAME DONE. The XFER FRAME DONE
flip-flop is set when clocked and its 1 output
triggers the RX RESET one-shot.

If the receiver is not in the transparent mode
(D8-6 RX TRANS (1) L is high) and the strip
sync function is selected (04-4 STRIP SYNC
(1) H is high), sync characters are stripped from
the message. This is accomplished by blocking
the clock pulse to the XFER FRAME START
and XFER FRAME DONE flip-flops. A Iowan
E99 pin 5 via E90 pin 8 blocks the clock signal.
During the DLE-SYNC, DLE-SYNC sequence in
the transparent mode, the sync characters are
also strl pped using the same logic by asserting
D4-6 RX SYNC DET Hand D8-6 DLE SAVE
(1) L.

The high at E99 pin 6 is inverted by E35 and
directly clears SKIP LD NEXT FRAME which
puts this flip-flop in the correct state for the
next character.
4-85

A double character can be stripped (in character recognition mode) when the M7817 logic
asserts D8-4 STRIP DB CHAR L. This signal,
via gates E88 and E98, holds XFER FRAME
START cleared to prevent generation of the
NPR request signal.
SKIP LD NEXT FRAME Flip-Flop
In the non-character detect receive mode, the SKIP LD
NEXT FRAME nip-flop starts cleared. Approximately
100 ns after D5-7 LD RX BtTF IS-8 Land DS-i LD RX
BUF 7-0 L are asserted, SKIP LD NEXT FRAME is
clocked by a pulse from the LD BUF one-shot which sets it.
Shortly after being set, SKIP LD NEXT FRAME is directly
cleared as a result of the DS-7 RX TRANSFER PULSE H
Signal. The SKIP LD NEXT FRAME flip-flop is now in the
proper state for the next character.

When character Data 1 appears, the clock
inhibiting action caused by the sync strip
function is removed. When Data 1 is shifted in,
only the high byte RX buffer load signal is
asserted and DS-7 RX TRANSFER PULSE H
clears SKIP LD NEXT FRAME. The XFER
FRAME START flip-flop is set. Data 1 is
loaded in the RX buffer high byte, which
obliterates the SYNC character that was there.
The SYNC character resides in the RX shift
register low byte but it was not loaded into the
RX buffer because the low byte load signal was
inhibited by SKIP LD NEXT FRAME being set.

When Data 2 is shifted in, it resides in the F~X
shift register and Data 1 is shifted to the low
byte which obliterates the SYNC character. A
normal load sequence moves both bytes (Data 2
and Data 1) to the RX buffer. XFER FRAME
DONE is set and it triggers the logic that
generates DS-8 RX NPR RQ (1) L. This signal
goes to the NPR control logic and generates
DS-3 RX NPR L which clocks the RX buffer
data register (D4-7) and puts Data 2 and Data 1
on the Unibus data lines. These characters are
sent to memory and the SYNC character has
been strl pped from the message.

In the character detect mode, the SKIP LD NEXT FRAME
flip-flop can be held in the set state if the next received
character is a sync to be stripped, provided double
characters are being processed.
Assume that 8 bit double characters are being processed
and that the character detection logic is conditioned to
strip sync characters. The character sequence for this
example is SYNC, Data 1, Data 2.

4.6 M7816 (AB SELECTORS AND BCC CONTROL)

SKIP LD NEXT FRAME starts cleared. Both
XFER FRAME START and XFER FRAME
DONE start cleared. This is the situation for
double characters and requires two clock pulses
to get the XFER flip-flops set so that an NPR
request can be generated.

4.6.1 Introduction
The M7816 module is a hex-height, extended-length,
module that contains several functionally-separate logic
circuits. They are listed in order of discussion.

When the SYNC character is detected, D4-7 F~X
SYNC DET H is asserted. D44 STRIP SYNC
(1) H is also asserted by the program. This
blocks the clock signal for the XFER flip-flop
which normally occurs when the character is
shifted in.
When the SYNC character is shifted in, the RX
bit counter overflows. The RX buffer load
Signals (DS-7 LD RX BUF IS-8 Land 7-0 L)
are asserted, SKIP LD NEXT FRAME is set,
but DS-7 RX TRANSFER PULSE H does not
cause SKIP LD NEXT FRAME to be cleared.
The SYNC character is loaded into the high
byte of the RX buffer and the previous
contents of the RX shift register are loaded into
the RX buffer low byte. The XFER flip-flops
have not changed state because the clock signal
is blocked (step 2).

Bus Selectors and Decoding Logic

Polynomial Register

Receive Block Check Character Generator

Transmit Block Check Character Generator

Transmit BCC Control

Receive BCC Control

4.6.2 Bus Selectors and Decoding Logic
4.6.2.1 Functional Description - The outputs of three
registers on the M7816 module and one on the M7817
module are multiplexed to the Unibus data lines through
one set of 16 bus drivers. This is accomplished by using 8
dual 4-line-to-l-line multiplexers; that is, each multiplexer
4-86

4.6.2.2 Detailed Logic Description - The circuit sche·
matic for the bus selectors and decoding logic are contained
in drawing D-CS·M7816·0·1 (Rev E) sheets 3 and 4 which
are designated D9·l and D9·2.

handles two bits of each register. The registers are listed
below:
Sequence Register (M7817)
Polynomial Register (M7816)
Receive BCC Register (M7816)
Transmit BCC Register (M7816)

Before explaining the details of the bus selectors, it is useful
to show the architecture of the registers that are inputs to
the bus selectors. Figure 4·50 shows the architecture as a
simplified block diagram.

Figure 4-49 is a simplified block diagram of the bus
selectors and decoding logic. The decoding logic generates
enabling signals for the multiplexers and bus drivers. It also
genera tes select signals to choose the proper register.
The SEQ, POLY, RX BCC and TX BCC registers are
secondary registers and are not selected directly by the
MI05 Address Selection Module. They are selected by bits
8-11 of the REG/ERR register and SELECT 6 from the
MI05 module.

Bus Selectors
The bus selectors are shown in print D9.1. Register
selection is the same for both bytes but the method of
enabling the multiplexers and bus drivers is different for
each byte. This is due to the requirement of multiplexing
the low byte (bits 7-0) and extended byte (bits 23-16) of
the POLY, TX BCC and RX BCC registers as inputs to the
low byte of the bus selectors.

The SEQ register contains 16 bits; the POLY, RX BCC and
TX BCC registers contain 24 bits. In these registers, the low
byte (bits 7-0) and extended byte (bits 23-16) are
multiplexed and sent to the low byte of the bus selectors.
For example, POLY MUX 0 H can be bit 0 or bit 16.

Figure 4·51 shows a typical two bit slice of the high and
low bytes of the bus selectors. The high byte example uses
bits 08 and 09 (mux E4); the low byte example uses bits 00
and 01 (mux E8). Because the POLY, TX BCC and RX
BCC low byte and extended byte are multiplexed, these
bits can also represent bits 16 and 17.

SEQ REG

RX BCC REG

TX BCC REG
POLY REG

BUS
SELECTORS
C BITS 15-08

o
S1

CC/BA ADRS 8 L
CC IBA ADRS 9 L
CC/BA ADRS 10 L
AB MUX SEL H

STB

CC/BA ADRS 9H
BUS
SELECTOR
DECODING
LOGIC

MUX-.BUSL

16 UNIBUS

1----+-------------1f------I------.-....... TRANSCE I VERS
BITS 0<15-00)

CC/BA ADRS 8H

IT BB L
SEQ REG
RX BCC REG
TX BCC REG

BUS
SELECTORS
C BITS07-00

POLY REG

li-2761

Figure 4-49 Block Diagram of AB Bus Selectors
!:Inti npf'ntiino T noif'

4-87

BUS SELECTORS

High Byte

Low Byte or Eltended Byte

11-2762

Figure 4-50 Block Diagram of Architecture of RX Bee,
TX Bee, POLY and SEQ Registers

4-88

09-2 MUX-BUS L ---I-~

09-2 POLY MUX 0 H
09-5 TX BCC MUX 0 H
09-6 RX BCC MUX 0 H
OS-I SEQ 0 H
09-2 POLY MUX 1 H
09-5 TX BCC MUX 1 H
09-6 RX BCC MUX 1 H
OS-I SEQ 1H

3
4
5

STBI
DO

. . . - - - - - BUS DATA OOL

STBO
7
fO

09-1 DOH

CO
BO

74153
ES
(BITS
13
01 01 AND 00)
12
Cl
11
Bl
10
fl
6

I
I
I 8838 E7

SO
14

09-1 01 H
L------BUS DATA 01 L

L~~~S~~

____ _

09-2 BCC 23-16H _--L.","",--,

09-2 MUX-BUS l - - - . . , - - - - - - - ,

D9-2 POLY e (1) H
09-4 TX BCC S (1) H
09-3 RX BCC S(1)H
OS-I SEQ S H
09-2 POLY 9 (1) H
09-4 TX BCC 9 (1) H
09-3 RX BCC 9 (1) H
OS-I SEQ 9H

4
5

..------BUS DATA OSl

STBO

3 DO

fO~--~------~~

09-1 oSH

CO
BO

74153
E4
(BITS
13
0109 AND OS)
12
Cl
6

11
10

Al
SI

SO
14

091-09H

I 8838 Ell

L ~~~~I~R _ _ _ ~S OATA-09L

L...--------------~--.....L..---09-2

CC/BA AoRS SH

L...-_ _ _ _ _ _ _ _ _ _ _ _....L...-_ _ _ _ _ _ 09 -2 CC/BA AoRS 9H

74153 TRUTH TABLE
AoRS INPUTS
STROBE
51

SELECTED
INPUT
A (SEQ)

B(RX BCC)

C (TX BCC)

D (POLY)

all outputs low

11-2767

Figure 4-51 Typical Two Bit Slice of the High and
Low Bytes of the Bus Selectors
4-89

The low byte mux (E8) has its strobe or enabling inputs
(STBI and STBO) permanently connected to ground. The
mux outputs are placed on the Unibus via bus drivers that
are enabled when 09-2 MUX -+ BUS L is asserted. The high
byte mux (E4) has its strobe inputs enabled when 09-2
MUX -+ BUS L is asserted and the associated bus drivers are
enabled when 09-2 BCC 23-16 H is not asserted. This
signal is only asserted when bits 23-16 of the POLY, TX
BCC, and RX BCC registers are to be read. When the
multiplexers are enabled, the select inputs (SI and SO)
choose the register to be read. The signals are 09-2 CC/BA
ADRS 9 H for SI and 09-2 CC/BA ADRS 8 H for SO. They
are common for both bytes.

These registers are secondary registers that are selected by
the secondary register pointer bits {I 1-08) of the REG/
ERR CSR as shown below:

Assume that the RX BCC is operating in the 16 bit
configuration and the program desires to read the contents
of this register. The bus selector decoding logic drives SI
low and SO high to select the RX BCC register. This is in
accordance with the mux truth table in Figure 4-51. The
decoding logic asserts 09-2 MUX -+ BUS L and holds 09-2
BCC 23-16 H low. Signal 09-2 MUX -+ BUS L puts the
low byte on the Unibus. This signal also enables the high
byte multiplexers and because 09-2 BCC 23-16 H is low,
the high byte is put on the Unibus. Thus, the contents (bits
16-00) of the RX BCC register have been read.

Bit 11 is a 1 for all five registers. The CHAR OET register is
differentiated from the other four by bit 10. Differentiation between the SEQ, RX BCC, TX BCC, and POLY
registers is accomplished by bits 8 and 9.

REG/ERR Bits
11
1
1
1
1
1

0
1
1

0
0
0
1
1

8
0
0
1
0
1

Octal
10
14
15
16
17

The enabling signal for the CHAR OET register is 09-2
CM -+ BUS H which is generated at gate E32 pin 4. Signal
08-6 IT BB L is an interlock signal that is generated on the
M7817 module which contains the CHAR OET register. If
the M7817 module is not installed, 08-6 IT BB L is not
asserted and pin 1 of gate E73 remains high due to the
connection to +5 V via R21. This inhibits 09-2 CM -+ BUS
H even if the CHAR OET register is addressed.

Assume now that the RX BCC is operating in the 24 bit
configuration and the program desires to read the contents
of this register. Two steps are required to read the 24 bits.
Bits 15-00 are read exactly as described in the previous
example. Bits 23-16 are read as follows. The program sets
bit 6 of the MISC register which results in assertion of 09-2
BCC 23-16 H. This signal inhibits the bus drivers for the
high byte of the bus selectors. Signal 09-2 MUX -+ BUS Lis
asserted by the decoding logic and puts 09-6 RX BCC MUX
7 H-O H on the Unibus. In this case, because MISC register
bit 6 is set, these bits are actually bits 23-16 of the RX
BCC register. Thus, in two steps, the contents (bits 23-00)
of the RX BCC register have been read.

Assume that the program desires to read the POLY register
and it is in the 16 bit configuration. The program addresses
the REG/ERR register and sets bits 11-8 to all Is which
points to the POLY register. The DQll is addressed again
using 76XXX6 and a OATI transaction is performed. As a
result, the MI05 Address Module asserts 03-1 SEL 6 Hand
03-1 IN H which go to pins 5 and 3 of E34 on the M7812
module (print 04-3). The third input (pin 4) of this gate is
04-6 REG PT 11 (l) H which is also high. This asserts 04-3
AB MUX SEL H at the output of E34 and it is sent to E63
pin 3 in the bus selector decoding logic (M7816, 09-2). Pin
5 of E63 is high because it is the double inversion of 04-6
REG PT 10 (1) H. Signal 04-6 REG PT 8 (l) H is double
inverted by the CC/BA AORS mux (print 05-1) and E16 to
assert 09-2 CC/BA AORS 8 H. This signal also goes to E32
pin 3. Signal 04-6 REG PT 9 (I) H is similarly double
inverted to assert 09-2 CC/BA AORS 9 H and is also sent
to the other input (pin 2) of E32. The output (pin 1) of
E32 is driven low and is sent to E73 pin 2. It is inverted by
E73 and sent to E63 pin 4. All three inputs (pins 3,4 and
5) of E63 are high so its output goes low which asserts 09-2
MUX-+ BUS L.

Bus Selector Decoding Logic
The bus selector decoding logic is shown in print
0-CS-M7816-0-1 (Rev E) sheet 4 (09-2). Figure 4-52 also
shows this logic with some additional informative
comments.
This logic also generates the signal (09-2 CM -+ BUS H) that
enables the output of the character detection register on
the M7817 module. The discussion includes the decoding
logic for this register plus the POLY, TX BCC, RX BCC,
and the SEQ registers.

4-90

09-1 +3V------'\-\

> - - - - - - - - - - - , - - - - - . - - - 09-2 CC/BA AORS 10 H

r-----l

04-6 REG PT 11 (1) H
03-1 SEL 6 H
03-1 IN H---:-_ _"

I
04-6 REG PT8 (1) H

E43
745158
CC/BA
AORS

04-6 REG PT9 (1)H
D4~6 REG PT 10 (1)H

I
I

0-=64---09-2 MUX -BUS L
~_+_+------f--04-3

AB MUX SEL H

I
D--+-+-!--'--D5-1 CC/BA AORS 10 L

1-"-+-- 05-1 CC/BA AORS 9 L

L~8~

05-1 CC/BA AORS 8 L

+5V
08-6 ITBB L ----'---t

09-2
CM-BUS H

' - 1 - - - - - 0 9 - 2 CC/BA AORS 8 H
3 V~4..:..-...L.------D9-2 CC/8A ADRS 9 H

;0_8_ _ 09- 2 BCC 23-16 H

04-3 BCC 23-16 (1) H

This is MISC REG
bit 6. Seleots bits
23 -16 when high
and bits 15- 0 when
low.

Select signal for POLY
multiplexers. Selects bits 7-0
when low and bits 23-16
when high.

CHAR OET

SEQ

RX BCC

TX BCC

POLY

11- 2779

Figure 4-52 Bus Selector Decoding Logic

4-91

The decoding logic has asserted D9-2 MUX ~ BUS L which
enables the high byte multiplexers for the bus selectors and
the low byte bus drivers. Signals D9-2 CC/BA ADRS 8 H
and D9-2 CC/BA ADRS 9 H are both high which selects the
POLY register. Because the POLY register is in the 16 bit
configuration, the program did not set MISC register bit 6.
Signal D4-3 Bee 23-16 (1) H is low. It is double inverted
by two E16 inverters to become D9-2 BCC 23-16 H. It is
the enabling signal for the bus drivers of the bus selector
high byte. Being low, it enables the drivers.

Figure 4-54 is a simplified block diagram that shows the
structure of the POLY register. The high byte (POLY 8 (1)
H-POLY 15 (1) H) goes directly to the bus selector high
byte multiplexer. The low byte (POLY 0 (1) H-POLY 7
(1) H) and extended byte (POLY 16 (1) H-POLY 23 (1)
H) are multiplexed and sent to the bus selector low byte
multiplexer as POLY MUX 0 H-POLY MUX 7 H. These
signals can be bits 0-7 or 16-23 depending on the POLY
register decoding logic. This logic also generates two register
clock signals: one for bits 0-15 and one for bits 16-23.

4.6.3 Polynomial Register
4.6.3.2 Detailed Logic Description - The circuit schematic for the POLY register and associated decoding logic is
contained in drawing D-CM-M7816-0-1 (Rev E) sheet 4
which is designated D9-2.

4.6.3.1 Functional Description - The polynomial register
(POLY) is a 24 bit read/write register that stores the
polynomial used in generating the BCC character during
transmission or checking the BCC character during
reception.

The 24 bits of the POLY register are stored in four 74175
quad flip-flops and two 74174 hex flip-flops as shown
below.

Any polynomial, up to 24 bits, can be used; however, there
are a few that are commonly used. Appendix A contains a
general discussion of BCC computation.

Designation
and Name
E12POLY3-O

There are some specific rules for loading the POLY which
are stated below and emphasized by a typical example.
The polynomial is an algebraic representation of a binary
word. The example used is Xl6 + XiS + X2 + 1. It is the
generator polynomial for a cyclic redundancy checking
(CRC) error detecting code called CRC-16. This code is
applied to synchronous systems that use 8-bit characters.
The rules for loading the generator polynomial using
CRC-16 are as follows:
1.

Disregard the polynomial's highest order term.
The hardware automatically i..'1cludes tl'Js bit.
The polynomial is Xl6 + Xl S + X2 + 1. The
highest order term is Xl 6 which is ignored. This
polynomial provides 17 term positions; from
Xl6 (highest order) to XO or 1 (lowest order).
It contains only four terms.

Input Signals

Output Signals

D9-1 DO H09-1 D3 H

D9-2 POLY 0 (1) HD9-2 POLY 3 (1) H

E17 POLY 9-4

09-1 D4 H09-1 D9 H

D9-2 POLY 4 (1) H09-2 POLY 9 (1) H

E6 POLY 15-10

D9-1 DI0 H09-1 DIS H

09-2 POLY 10 (1) HD9-2 POLY 15 (1) H

E19 POLY 19-16

09-1 DOH09-1 D3 H

09-2 POLY 16 (1) HD9-2 POLY 19 (1) H

E18 POLY 23-20

09-1 D4 H09-1 D7 H

09-2 POLY 20 (1) H09-2 POLY 23 (1) H

The 74174 and 74175 flip-flops are D type with common
clock and clear inputs. The 74175s have complementary
outputs and the 74174s do not. All register outputs come
from the 1 side of the flip-flops. The six devices use a
common direct clear signal. It is D9-2 INI L which is the
inversion of D5-4 INI H from gate E58.

Assign the polynomial second highest order
term position to bit 0 of the POLY register.
Assign the remaining term positions in descending order to the register bits in ascending order.
In this example the lowest order term, which is
XO or 1, is assigned to register bit 15.

The POLY register uses two clock signals: one for bits
0-15 and one for bits 16-23. They are both generated by
D9-6 LD POLY L.

Examine the polynomial and for each term
present (except the highest order term) set the
corresponding register pOSition to a 1. Figure
4-53 shows this graphically.

Figure 4-55 shows the logic for generating the clock signals.
It also shows how D9-6 LD POLY L is generated to add
continuity to the discussion.

4-92

Polynomial for CRC-16, is X'6+ X '!5+ X 2+ 1
Octal value is 120001
15

I I

X!5

X 'O

X'I

X'2

X'3

X'4

BIT
POSITION

X'!5

TERM
POSITION
BINARY

OCTAL
11-2774

Figure 4-53 Configuration of POLY Register for
Polynomial X16 + Xl S + X2 + 1 (CRC-16)

3-0

74175
E12
POLY 3-0

09-1 00H-03H

74157
E14

. I

14175
E19
POLY 19-16

09-2 POLY MUX OH-3H

___

BITS 3-0

IQ-IS

....

11--_-_~

BUS

'9-_'6_

SELECTORS
Low Byte
(7-0) or
Extended
Byte (23-16)

09-104H-07H

74175
E18
POLY 23-20

23-20
74157
E28
BITS 7-4

7-4
74174
E17
POLY 9-4

OR
23-20

09-2 POLY MUX 4H-7H

889

09-1 08H 8 09H

09-1 010H-015H

74174
E6
POLY 15-10

09-2 POLY 8(1) H-15(1)H

BUS
SELECTORS
High Byte
(15-8)

11-2780

Figure 4-54 Architecture of POLY Register

4-93

---,
04 - 6 REG PT 11 (1 ) H

05-4 SEL 6 LOL

4
5 E39

r--.J
II 09-2 CC/BA AORS lOH

03-1 OUT LOW H
03-1 SEL 6 H ~---------..-t

09-2CC/BA AORS 9H

05-3 CC/BA CYCLE H

I 09-2 CC/BA AORS 8 H
I

---a...........,.,.

7442
E61
REG PT
WRITE
10-17
OCOR

F7 D - - - r - - 09-6 LO POLY L
F6
F5
F4 0----+- 09-6 LD SEQ L

FO 0----+- 09-6 LO CHAR OET L

+3V

I
M7813
I
---~

10
l------

'
~

~
04-3BCC23-16(I)H ~.-6..L.._ _ _+-~ E32

r--------

Clock for POLY
register bits 15-00

Clock for POLY
register bits 23-16

' - - - - - - - - - - 09- 2 BCC 23- 16 H
11-2781

Figure 4-55 Logic for Generating Clock Signals
for POLY Register

D4-3 Bee 23-16 (1) H is also double inverted and puts a
low on pin 8 of the other E32 gate. D9-6 LD POLY L puts
a low on the other input (pin 9) of this gate which drives
the output (pin 10) high. This positive transition clocks
data into bits 0-15 of the POLY register.

Assume that a polynomial is to be loaded that requires 16
bits. The program selects the POLY register via bits 11-8
of the REG/ERR register. It addresses the DQll again
using 76XXX6 and a DATO transaction is performed. As a
result, the MI05 Address Module asserts D3-1 SEL 6 Hand
D3-1 OUT LOW H which go to the pulse generator on the
M7813 module (Figure 4-55). This produces a 100 ns
negative pulse (D54 SEL 6 LD L) at E39 pin 6. This signal
is sent to the RG PT WRITE 10, 14, 17 decoder (E61) on
the M7816 module (print D9-6). E61 is a 7442 4-1ine-to10-line decoder but it is connected to operate as a 3-wire,
binary to octal decoder. The three least significant inputs
(DO, Dl and D2) are the binary code and the most
significant input (D3) is the strobe or enabling input. The
strobe (D5-4 SEL 6 LD L) must be low to enable the
decoder. Because the POLY register is selected, the binary
code inputs (D9-2 ee/BA ADRS 10 H, 9 Hand 8 H) are all
high. This selects output f7 and asserts D9-6 LD POLY L.

If a 24 bit polynomial is to be loaded into the register, the
sequence is the same. However, D4-3 Bee 23-16 (1) H is
now high (set by program) and only the clock from E32 pin
13 is generated, thus POLY 23--16 is clocked (E17, E18).
4.6.4 Receive Bee Generator
4.6.4.1 Functional Description - A simplified block diagram of the RX Bee generator is shown in Figure 4-56. The
inputs of the Bee generator are conditioned by the outputs
of the POLY register which holds the polynomial that
represents the LRe or eRe code being used. The remote
station sends a message with a Bee character appended.
Both stations must use the same code. The RX Bee
generator examines the received data and computes a Bee
character. It examines the received Bee character and the
register goes to aliOs if the received Bee character agrees
with the computed one. This means that the message has
been received without error.

Because POLY register bits 0-15 are selected, bit 6 of the
MISe REG is not set. As a result, D4-3 Bee 23-16 (1) His
low. This signal is inverted once and sent to pin 12 of gate
E32. This drives the output (pin 13) of this gate low which
inhibits the clock for POLY register bits 23-16. Signal

4-94

Feedback (all but bit 0)

23 X-OR
GATES

POLY 0 (1)H23 (1) H

24 INPUT

RX BCC
REGISTER

(Bit 23
excluded)

RX BCC 0 (1) H23 (1) H

(24 Bits)
Bit 0

AND
GATES
CLR RX BCC L

WIREDOR

SHIFT RX BCC H --~

RX BCC DATA IN L

RX ZERO BCC H

X- OR

11-2772

Figure 4-56 Block Diagram of RX BCC Generator

If the Bee characters do not agree, one or more errors are
present in the message. In this case, RX ZERO BCC H is
low. It is sent to the RX BCC control logic (D9-6) and
generates the BCC ERR L flag which denotes that an
incorrect message has been received. The receiving station
requests that the message be retransmitted.

4.6.4.2 Uetailed Logic Description - The circuit schematic for the RX BCC generator is contained in drawing
D-CS-M7816-O-1 (Rev E) sheet 5 which is designated D9-3.

The BCC accumulation (24 bits maximum) is stored in four
74174 hex D-type flip-flops. These 24 flip-flops operate as
a shift register and are clocked simultaneously by D9-6
SHIFT RX BCC H from the RX BCC control logic. All bits
are cleared simultaneously by D9-6 CLR RX BCC L (The
generation of these control signals is discussed in a
subsequent section.)

The RX BCC generator just checks for errors; it does not
locate them.

To be compatible with the DQII method of handling
characters, the BCC character must be a multiple of the bits
per character selected. For example, CRC-16 is used with 8
bit characters and provides a 16 bit BCC character. Other
common codes also provide a multiple of 2 and some
provide a multiple of 1. The user could implement a code
with a different multiple. The DQll provides multiples of
1,2 and 3 only.

At the remote station, the TX BCC generator produces a
BCC character, using a specific LRC or CRC generator
polynomial, and appends it to the data. The RX BCC
generator regards the complete transmission (data plus
BCC) as a code message polynomial which it divides by the
same generator polynomial. If there is no error, the division
produces no remainder (BCC register reads all Os) and it is
assumed that the message is correct.

The M7817 module provides programmable BCC multiple
selection using bits 4 and 5 of the SEQ register. The M7816
module provides jumpers to select the number of BCCs.
When both modules are installed, either selection method
can be used, depending on system programming.

The inputs to the RX BCC flip-flops are programmable,
using the POLY generator, to allow any generator polynomial up to 24 bits to be used. Of course, the selected RX
BCC generator polynomial must be the same as the one
used by the transmitting station.

4-95

If a particular stage of the RX Bee generator is conditioned
by having its associated POLY register bit set (high or
logical 1), the information stored in that bit is the X-OR
function of the data and feedback from the previous stage.
If the associated POLY register bit is cleared (low or logical
0), the X-OR gate acts as a non-inverting gate and stores
what was hi the previous stage just as if the AND gate was
not there.

Each D-input of bits 0-23 of the RX Bee flip-flops is
connected to the output of an exclusive-OR gate (7486
2-input X-OR). One input of each X-OR gate is connected
to the previous flip-flop output. The single exception is the
MSB (bit 23) which has no exclusive-OR gate. The other
input of each X-OR gate is connected to the output of an
~,\lJ) gate (7408 2-input AND). The single exception is the
MSB (bit 23) whose AND gate is connected directly to the
associated flip-flop input. There are 24 AND gates and 23
X-OR gates (bit 23 has no X-OR gate).

Operationally, these facts are pointed out when a polynomial of iess than 24 bits is used. Assume the use of the
polynomial for eRe 16 which is Xl 6 + Xl 5 + X2 + 1. The
lowest order term is XO or 1 and is assigned to bit 15.
(Refer to rules for loading the POLY register in Paragraph
4.6.3.1). POLY register bits 16-24 must be cleared.
Regardless of the state of the data, stages 16-24 cannot
pass along anything but Os. The RX Bee generator acts as if
itis only 16 bits long.

One input of each AND gate is connected to the associated
output of the POLY register; for example, D9-2 POLY 18
(l) H goes to pin 4 of AND gate E47 which is associated
with RX Bee generator bit 18. The other input of all AND
gates is connected to the output (pin 8) of E58. This is the
inversion of the result of the X-ORing of D4-5 RX Bee
DATA IN L and the output of the 0 bit of the RX Bee
generator.

The serial data into the RX Bee generator is D4-5 RX Bee
DATA IN L which is sent to pin 13 of E48 where it is
X-ORed with the output of bit o. This signal comes from
the output of E97 on the M7812 module (Figure 4-58).
E97 is a 2-wide, 2-input, AND-DR-invert gate (7450). The
qualifying signal for both halves of this gate is D4-3 BITS
11 (l) H which is high for double-character operation and
low for single-character operation. For double-character

Each RX Bee generator output is sent to a 7416 inverter.
All the inverter outputs are wire-ORed to assert D9-3 RX
ZERO Bee H when all bits are O. If the Bee accumulation
is not all Os, this signal is low and results in generation of
the RX Bee ERR flag and ERR INTR signal on the M7812
module (print D4-6). Figure 4-57 shows bits 0, 1, 2, 22 and
23 of the RX Bee generator to illustrate the architecture.

POLY 23(1)H

DATA IN

RX Bee
23 (1) H

11-2773

Figure 4-57 Architecture of RX Bee Generator

4-96

High for double
character s. Low
for single
charac ters.

From 1 output of
bit 8 of RX
SHIFT REGISTER

04-5 RX BCC DATA IN L
04-3 BITS11 (1lH --.r-------~...)

From 1 output of
bit 0 of RX BCC
REGISTER

To RX BCC
REGISTER
Input AND
gates

From 1 output of
bit 0 of R X SHIFT
REGISTER
11-2782

Figure 4-58 Data Input Gating for RX BCC Generator

operation, it is directly ANDed with the 1 output of bit 8
of the RX shift register. For single-character operation, it is
inverted and then ANDed with the 1 output of bit 0 of the
RX shift register. The first bit to be processed by the RX
BCC generator occurs after one complete character has
been shifted into the RX shift register.

Figure 4-59 shows a sample RX BCC accumulation using
CRC-16. A graphical representation of this process is used
because it is the most comprehensible and the least
cumbersome .. The polynomial for CRC-16 is
Xl 6 + Xl 5 + X2 + 1 which puts a 1 on the input of the
AND gates associated with bits 0, 13, and 15. In this
example, a 16-bit data word (two 8-bit characters) and a
16-bit BCC character are received and processed LSB first.
The column on the far right shows the X-OR of the data bit
and the LSB (bit 0) of the RX BCC generator prior to
shifting. This column is the feedback path which goes to all
AND gates in the RX BCC generator. The column on the
far left identifies the time state of the generator. The states
of all 16 bits are shown starting with all Os. Subsequent
rows show the states after shifting. The sample shows the
BCC accumulation after shifting in the 16 data bits. It is the
same as the received BCC character. When this BCC
character is received (after shift number 32), the RX BCC
generator reads all Os which indicates that the message has
been received without error.

4.6.5 Transmit Bee Generator
4.6.5.1 Functional Description - The architecture of the
TX BCC generator is very similar to the RX Bee generator.

The input gating, storage, and feedback system are identical
for both generators. The individual outputs of the TX BCC
generator are not used to generate a flag signal so the 24
inverters are omitted. The output gating is different because
the serial output (BCC character) of the TX generator can
be transmitted.
The TX Bee generator examines the data being transmitted
and accumulates a BCC character. This character can be
transmitted when the TX Bee control logic generates the
BCC enabling Signal.
4.6.5.2 Detailed Logic Description - The circuit schematic for the TX BCC generator is contained in drawing
D-CS-M7816-0-1 (Rev E) sheet 6 which is designated D94.
The BCC accumulation (24 bits maximum) is stored in four
74174 hex D-type flip-flops. These 24 flip-flops operate as
a shift register and are clocked simultaneously by D9-5
SHIFT TX BCe H from the TX BCC control logic. All bits
are cleared Simultaneously by D9-S CLR TX BCC L. (The
generation of these control signals is discussed in a
subsequent section.) The inputs to the TX BCC generator
are programmable, using the POLY register, exactly like the
RX BCC generator. Refer to Paragraph 4.6.4.2 for a
discussion of the conditioning of the inputs and operation
of the feedback loop.
The serial data into the TX BCe generator is D4-7 TX
DATA H which comes from OR gate E23 on the M7812
module. This signal is inverted by E67 (print D4-7) and sent
to the DFll as D4-7 SERIAL DATA OUT L. The
information to be transmitted can be data, VRC bit, PAD
character or BeC character.

4-97

, - - - - - - - D a t a In

SHIFT

NO.

Start

0
0

o
o

o
o
o

9
10
11
12
13
14
15
16
17
18
19
20
21

o
o
o

o
o
o
o

5
6

o
o
o

o
o

o
o
o
o

o
o

000
000
000
000
000
100
010
001
o 0
010
001
000
000
000
000
000
000
000
000
0

22
23
24

27
28
29
30
31

o
o

0
0
0
0
0
0
0
0
0
0
0

o
o
o

o 0 0 0 0 0 0 0 0 O~ -~1
o 0 0 0 0 0 0 0 0 1
1
000000000
0
000 0 0 0 000
0
o 0 0 0 0 0 0 000
00000 0 0 0 0

o0 0 0 0 0 0

o 1 1 0 000 0 0

001
00000
0000000
000 0
000
o 0 0 001 100
o0 0 0 0 0 1 0
o 000 0 001
1
000 0 000 0 1 0
000 0 0 0 0 001
000 0 0 0 0 001
o0 0 0 0 0 0 0 0 0
o 0 0 0 0 0 0 000
1 000 0 0 0 0 0 0
o 1 0 0 0 0 0 0 0 0
00100 0 0 0 0 0
100 1 000 000
o 100 1 0 0 000
o 0
0 0
000 0
000 1 001 000
o 0 0 0 001 0 0
o 0 000 1 001 0
o 0 0 0 001 001
o 0 0 0 0 0 0
0 0
0 0 000 0 0 0 1 0

LSB

Feedback
Before Shift

Arrows Indicate
Exclusive-OR
of Data Bit
and LSB of

Bee Register

DATA

Prior to Shift

o
o

o
o
o

o
o
o
1

o
MSB
LSB

o
o

o
o
o
o

o
o

o
o
o
o

o
o
o
BCC

o
o

o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 l O t -0
.-0---0---0----0---0---0----0-0--0--0-0--0--0-0--0--0~1~ 0

L {

Bee Register ALL Os

16 Bit Data Word
and BCC Received

Received Message Assumed

To Be Correct

NOTE
At shift no. 16, the Bee accumulation in the RX Bee generator
should be identical to the Bee character about to be received.

Figure 4-59 RX BCC Accumulation Using CRC-16

4-98

Assume that it is desired to transmit a Bee character
directly after a block of data. As the data is being
transmitted, it is also sent to pin 13 of X-OR gate E70 as
D44 TX DATA H. The other input (pin 12) of E70 is D94
TX Bee 0 (1) H which is the 0 bit of the TX Bee
generator. The output (pin 11) of X-OR gate E70 is sent to
E64 pin 5. The other input (pin 4) of this gate is connected
to D5-6 Bee EN (1) L. This is the Bee enabling signal
which comes from the Bee SEND ENABLE flip-flop on
the M7813 module. This signal is low when a Bee character
is being transmitted. At this time, D5-6 Bee EN (l) L is
high because data is being transmitted. This enables E64
and allows the X-ORing of data and bit 0 to be fed back to
the TX Bee generator via E58. This permits the Bee
character to be accumulated.

When the data transmission is complete and it is time to
transmit the Bee character, the TX Bee generator control
logic asserts D9-5 Bee RQ L. This signal allows the Bee
SEND ENABLE flip-flop to be set and asserts D5-6 Bee
EN (1) L which holds the feedback signal line low from
E58 pin 6. This action prevents alteration of the contents
of the generator and allows the contents to be shifted out.
With D5-6 Bee EN (l) L low, the contents of the TX Bee
generator (which is the Bee character), are shifted out the
bit 0 position via E64 pin 8 as D94 Bee/DLE L.

4.6.6 TX Bee eontrol Logic

4.6.6.1 Functional Description - A simplified block diagram of the TX Bee control logic is shown in Figure 4-60.
The logic performs several functions that are interrelated
but can be described separately. The major functional areas
are listed below in order of discussion.

D5-6 Bee EN (l) L, which is high, is inverted by E69 and
sent to pin 10 of E64. This inhibits D9-4 Bee/DLE Land
prevents the contents of the TX Bee generator from being
shifted out while data is transmitted.

Bee

TEST NEXT CC (1) H

TX EXIT PULSE H

CNTR LD PULSE H

B CNTR LP H

SP PORT 14 H

TX Transparency

SP PORT 13 H

Control Logic

WI H
W2 H

BCC RQ L

TX BCC 4L
TX BCC 5L

RX CYCLE H
LD TX SH REG H

B TX C L

TX BCC
Counter and
BCC Request
Logic

TX BCC NEXT CHAR L

TX C L

TX FAKE END (1) L
BCC EN (1) H

SHIFT TX BCC H
TX CLK H
TX ACTIVE (1) H
TX BCC SH EN L

TX BCC
Shift and
Clear Logie

INH SH TX BCC L

CLR TX BCC L

SYNC EN L
11-2776

Figure 4-60 Simplified Block Diagram of TX Bee eontrol Logic

4-99

TX Transparency eontrol Logic. This logic
allows the transmitter to enter and exit the
transparent mode under control of REG/ERR
eSR bits 14 (ENTER T) and 13 (EXIT T). This
is a function of the M7816 module only and is
called total transparency to differentiate it
from the control of the transparent text mode
provided by the M7817 module, when it is
installed. When the transmitter enters total
transparency, this logic sends a signal to the TX
Bee shift and control logic that starts the TX
Bee generator and turns off all character
recognition logic. When the transmitter exits
total transparency, this logic generates a signal
that enables the TX Bee counter logic and
allows the selected number of Bee characters
to be appended to the message prior to the
shutdown of the TX Bee generator. It also
turns on the character recognition logic.

TX Bee eounter and Bee Request Logic.
Jumpers WI and W2 on the M7816 module
allow selection of 1, 2 or 3 Bee characters. If
the M7817 module is installed. control signals
are used instead of jumpers to make the
selection. In both cases, qualification of two
TX Bee counter flip-flops by the jumpers (or
M7817 signals) allow the TX Bee generator to
operate long enough to append the selected
number of Bee characters. This logic normally
provides a one character delay to ensure that
the last data character is included in the BCe
accumulation before the Bee characters are
appended.

TX Bee Shift and Clear Logic. This logic
generates the pulses that shift the TX Bee
generator. It also provides a signal to clear the
generator. One section of the logic converts the
TX clock signal to positive 50 ns pulses that
shift the TX Bee generator. It is controlled by
signals from the transparency con trol and
counter logic and by signals from the M7817
module. The other section of the logic generates a signal that clears the TX BeC generator
and a signal that clears various flip-flops in the
transparency control and counter logic.

TX Transparency Control Logic
The TX total transparency control logic is shown in the left
center section of print D9-5. It is also shown in Figure 4-61.
The basic controlling functions for this logic are REG/ERR
eSR bits 14 (ENTER T) and 13 (EXIT T). When bit 14 is
set, the TX transparency control logic forces the DQll into
the total transparent mode and starts the TX Bee
generator. When bit 13 is set, this logic allows the DQ to
exit from the total transparent mode. It triggers the TX
Bee counter logic which allows the selected number of
Bee characters to be transmitted; then it turns off the TX
Bee generator.
Bits 14 and 13 perform their functions when the character
count register is tested for non-zero by the hardware. This
occurs when the current character count register goes to
zero (overflows) or at the first transfer following the
assertion of GO.
The following example is used to discuss the operation of
the logic. It is desired to transmit a message in total
transparent mode with two Bee characters appended. The
transmitter is turned on, bit 14 (ENTER T) is set, the TX
primary ee register is loaded with the specified character
count, and the TX Bee generator is turned on. In this
example, the message length does not exceed the character
count loaded in the TX primary ee register; therefore, the
TX secondary ee register contains a count of zero. When
the last data character is transmitted, the TX primary ec
register goes to zero and bit 13 (EXIT T) is set to take the
transmitter out of the transparent mode. The two Bee
characters are transmitted and then the Bee generator is
shut off.
The operation of the TX transparency control logic during
this example is discussed below.
1.

4.6.6.2 Detailed Logic Description - The circuit schematic for the TX Bee control logic is contained in drawing
D-eS-M7816-O-1 (Rev E) sheet 7 which is deSignated D9-5.

4-100

The program sets REG/ERR eSR bit 14
(ENTER T). This asserts D5-2 SP PORT 14 H
which is sent to pin 5 of 3-input NAND gate
E89. The DQll is in the transmit mode so
signal D5-3 RX eyeLE H is low. It is inverted
by E82 and puts a high on the second input
(pin 4) of E89. Signal D5-3 TEST NEXT ee (1)
H is low (it is asserted only at CC register
overflow). It is inverted by E69 and puts a high
on pin 2 of 2-input AND gate E80. The other
input (pin 1) of this gate goes high when D5-3
eNTR LD PULSE H is asserted. This occurs
when the TX primary ec register is loaded. The
output (pin 3) of E80 goes high and is sent to
the third in put (pin 3) of E89.

09-5 TX TOTAL TRANS (I) L - _ - - - - - - = = - - i -....,

05-3 TEST NEXT CC (1) H--L..-;_ _
4-t
05-3 CNTR LO PULSE H_---'_ _5-t

13 To TX BCC
Counter
E86 1 4 LoOic
74123
BCC
13
STROB~ 4

3
~--.--+-09-5

B CNTR LP H

05-3 RX CYCLE H - - - - - - t

05-2 SP PORT 13 H--------.,;:...=..t_--'

4
.--_....;:2~D

10
12

E94 1 6
7474
EXIT TX
5
3 CTRANSO 6

....o~
....

9
0
E94 1 8
7474
9
EXITI
11 CENTERO 8
13

o E90 1

4
5

7474
TX TOTAL 5
3 TRANS
C OLY O 6

5
1 6
7474
TX
5
TOTAL
3 CTRANSO 6

o E93

To TX BCC
Shift LoOic

l..f"

05-6 LO TX SH REG H - - - - I

09-1

3V--~------------~-----------

----I

05-6 TX ACTIVE (1) H _ _9~_"'1
10
09 -1 + 3 V

5
E85 10.!.12:::......._ _---I
74123
5
BCC
PRESETO 12
11

,)9- 2 INI L
11-2778

Figure 4-61 TX Total Transpa.rency Control Logic

With the three inputs high, the output (pin 6)
of NAND gate E89 goes low. This Signal
directly sets the TX TOTAL TRANS DLY
flip-flop via its preset input.

The high signal from the 1 output of TX
TOTAL TRANS DLY is sent to the D input of
the TX TOTAL TRANS flip-flop. One or two
clock pulses later, D5-6 LD TX SH REG His
asserted and sent to E79 pin 10. The other
input of tl'aJs gate is connected to +3 V so its
output (pin 8) goes high. This signal clocks TX
TOTAL TRANS and sets it.

The high signal from the 1 output of TX
TOTAL TRANS goes to pin 9 of E83. The
other input (pin 10) is also high because D5-6
TX AeTIVE (1) H is asserted. This drives the
output of E83 low and after a delay caused by
Re network e96, e97 and R22, it passes
through E76 and E89 to qualify E71 and allow
generation of the TX Bee shift pulses (D9-5
SHIFT TX Bee H). This turns on the TX Bee
generator.
The transparent data is transmitted and now
the control logic must allow the transmitter to
exit from the total transparent mode.

The program sets REG/ERR eSR bit 13 (EXIT
T). This asserts D5-2 SP PORT 13 H which is
sent to pin 13 of 3-input NAND gate E89. The
second input (pin 1) is high because the DQll
is in the transmit mode (D5-3 RX eyeLE H is
not asserted). When the TX primary ee register
overflows, both D5-3 TEST NEXT ee (1) H
and D5-3 eNTR LD PULSE H are asserted.
They are ANDed at E79 pins 4 and 5 and drive
the third input (pin 2) of E89 high.

With the three inputs high, the output (pin 12)
of NAND gate E89 goes low. This signal
directly sets the EXIT TX TRANS flip-flop via
its preset input. The low signal from the 0
output of EXIT TX TRANS goes to E88 pin 5.
The other input (pin 6) of this gate is also low
so the output (pin 4) goes high. It is inverted by
E91 and is sent to the clock input of TX
TOTAL TRANS DLY.

One or two clock pulses later, D5-6 LD TX SH
REG H is asserted and drives the output (pin 4)
of E8810w. It is inverted and this positive-going
transition clocks TX TOTAL TRANS OLY
which clears it (the D input of this flip-flop is
held low by EXIT /ENTER which remains
cleared).

When TX TOTAL TRANS OLY is cleared, the
low signal at its 1 output directly clears TX
TOTAL TR_ANS. The high signal from TX
TOTAL TRANS triggers the Bee STROBE
one-shot which enables the Bee counter logic
to allow transmission of the two Bee characters and subsequent shutdown of the TX Bee
generator by inhibiting D9-5 SHIFT TX Bee H
pulses.

TX Bee Counter and BCC Request Logic
The TX Bee counter and Bee request logic is shown in the
upper right section of print D9-5. This logic generates a
request signal (D9-5 Bee RQ L) when it is time to append a
Bee to the data being transmitted. 'Pile counter is qualified
to allow 1, 2 or 3 Bee characters to be appended. The
qualification Signals come from the M7817 module (BB
option) or from the M7816 module (AB option).

The qualification logic is shown in Figure 4-62. The preset
input of each counter flip-flop is connected to the output
of a NAND gate. For flip-flop TX Bee eNTR A, the gate is
E87 pin 1. For flip-flop TX Bee eNTR B, it is E87 pin 4.
One input of each of these E87 gates is connected to the 1
output of one-shot Bee STROBE which is triggered when
coming out of total transparency (AB option). The other
input of each gate is controlled by a jumper on the M7816
(print D9-6) to control the number of Bee characters
selected. Jumper W2 (signal D9-6 W2 H) is associated with
TX Bee eNTR A and Jumper WI (signal D9-6 WI H) is
associated with TX Bee eNTR B. Jumper selection of the
number of Bee characters is used for the AB option. the
output of each of the E87 gates is wire-ORed with a signal
from the M7817 (BB option). The signals are: 08-4 TX
Bee 5 L for TX Bee eNTR A and 08-4 TX Bee 4 L for
TX Bee eNTR B. These signals are programmable and are
controlled by bits 4 and 5 of the SEQ register. The truth
table in Figure 4-62 also shows the signal states and jumper
configurations for selecting the number of Bees.

4-102

*08-1 SEQ 5H----.-----f"~
08-3 TX SEQ STROBE B H ----y--+--=--L-J

08-4TXBCC5L

08-3 TX SEQ STROBE A H - r - - - t - - - L - J

08-4 TX BCC4 L
*08-1 SEQ4H-+-~~

NOTE

~Wl

To preset

D----+-+-<~- input of

*These signals are bits 5 and 4 of the
SEQ register. They are inverted three
times coming from the Unibus. SEQ
bits 5 and 4 are shown below as they
appear on the Unibus.
No. of
Bees

SEQ Bits
4

NONE

3
2
1

To preset

~W2

0
0

0
1
0

3
2

No. of
Bees

TX BCC CNTR B
flip flop

+5V

Jumpers

Signals

Wired-OR
Output
W2
Wl

IN
OUT
IN
OUT

IN
IN
OUT
OUT

L
H
L
H

L
L
H
H

H
L
H
L

0 - -........- + - - - input of

I
_~7~O~ ~~81~9-~

TX BCC CNTR A
flipflop

09-5 BCC STROBE(l:J

H
H
L
L

11- 2783

Figure 4-62 Qualification Logic for TX Bee eounter

The wired-OR connection at the outputs of the E87 gates
allows qualification of the TX Bee counter flip-flops by
the M7817 module (BB option) using bits 4 and 5 of the
SEQ register or by jumpers on the M7816 module (AB
option) when coming out of total transparency.
The TX Bee NEXT FR flip-flop in the request logic
provides a one character delay before asserting D9-5 Bee
RQ L to ensure that the last character is included in the
Bee accumulation. In cases that do not require the one
character delay, the TX Bee NEXT FR flip-flop can be
preset by the M7816 or M7817 module to assert D9-5 Bee
RQ L. A similar wired-OR connection is used to generate
the low signal required to preset the flip-flop. For the
M7817 module, the preset signal is D84 TX Bee NEXT
eHAR L. For the M7816 modu1e it is the ANDing of D5-6

TX FAKE END (1) H and the positive pulse from the Bee
STROBE one-shot at NAND gate E87 pin 10.
The following example assumes that the M7817 module is
not installed and that transparency is controlled by the
M7816 module. To describe the operation of the counter
and request logic, assume that the counter flip-flops have
been qualified to select two Bee characters. Qualification is
made by the M7816 module: D9-6 WI H is high Gumper
WI is out) and D9-6 W2 H is low Gumper W2 is in). Assume
that the flip-flops start in the cleared state.

4-103

Mter qualification, TX Bee eNTR A is cleared
and its D input is 10 . TX Bee eNTR B is set
and its D input is low. TX Bee NEXT FR is
cleared and its D input is high.

When the TX bit counter on the M7813 module
overflows, the carry pulse is buffered to
become DS-6 BTXC L which is sent to pin S of
inverter E91. It is inverted again by another
E91 gate. The positive-going trailing edge of
this pulse (E91 pin 12) clocks the TX BCC
NEXT FR flip-flops and sets it.

The high from the 1 output of TX BCC NEXT
FR goes to pin S of NAND gate E83. The other
input (pin 4) is also high because TX BCC
CNTR B is set. This asserts D9-S BCC RQ L at
the output of this gate. The clocking signal does
not affect TX BCC CNTR A because gate E88
is disqualified by a high on its pin 9 input. This
high signal is DS-6 BCC EN (1) L which comes
from the BCC section of the SEND ENABLE
flip-flop (M7813) which is cleared at present.

When D9-S BCC RQ L is asserted, it is sent to
the TX control logic on the M7813 module
(print DS-S). It is inverted and puts a high on
the D input of the BCC section of the SEND
ENABLE flip-flop. The next overflow pulse
from the TX bit counter sets the BCC SEND
ENABLE flip-flop and asserts DS-6 BCC EN (1)
L. This signal is sent to E88 pin 9 which allows
subsequent overflow pulses to clock TX BCC
CNTRA.
The first eight bits of the BCC are shifted out
of the TX BCC genera tor and the TX bit
coun ter overflows again. The TX BCC CNTR A
flip-flop is clocked via E88 pin 10 which sets it.
The TX BCC CNTR Band TX BCC NEXT FR
flip-flops do not change state; therefore, D9-5
BCC RQ L remains asserted and the last eight
bits of the BCC are shifted out of the TX BCe
generator. The D input of TX BCC CNTR A is
low.
When the last bit of the BCC is shifted out, the
TX bit counter overflows again. Both TX BCC
CNTR A and TX BCC CNTR B are cleared.
Exclusive-OR gate E76 puts a low on the D
input of TX Bce CNTR A so further clocking
does not change its state. TX BCC NEXT FR is
still set but its D input is low. The 0 outputs of
TX BCC CNTR A and TX BCC CNTR B puts
highs on pins 1 and 2 of E83 which drives its
output low. In turn, this drives D9-S BCC REQ
Lhigh.

Signal D9-S BCC REQ L, which is high, is sent
to the M7813 module and puts a low on the D
input of the BCC section of the SEND
ENABLE flip-flop. The next overflow pulse
clears the BCC SEND ENABLE flip-flop and
drives DS-6 BCC EN (1) L high which inhibits
further clocking of TX Bee eNTR A and TX
BCC CNTR B. The overflow pulse clears TX
BCCNEXT FR.

All during this operation, the TX TOTAL
TRANS flip-flop is cleared which puts a high on
E89 pin 11. When TX BCC CNTR A and TX
BCC CNTR B were cleared (step 6), E89 pin 9
went high. Signal DS-6 BeC EN (1) L goes to
E89 pin 10 and when it goes high (step 7) the
output of E89 goes low and inhibits the
generation of D9-S SHIFT TX BCe H pulses
which turns off the TX BCC generator.

TX BCC Shift and Clear Logic
The TX BCC shift and clear logic is shown in the lower
right section of drawing D-CS-M7816-0-1 (Rev E) sheet 7
which is designated D9-S.
One-shot BCC PRESET is triggered by the negative-going
transition that occurs when TX ACTIVE is cleared. The
actual signal is DS-6 TX ACTIVE (1) H to input pin 9 of
BCC PRESET. When the one-shot is triggered, a 700 ns
negative pulse from the 0 output directly clears the
following flip-flops in the TX BCC control logic. The
flip-flops are listed below:
EXIT TX TRANS
EXIT/ENTER
TX TOTAL TRANS
TXBCC CNTRA
TXBCC CNTRB
TX BCC NEXT FR
The CLEAR START one-shot clears the TX BCC generator
prior to the accumulation of a BCC character to ensure that
nothing is left over from the previous accumulation. The
BCC EN PULSE one-shot converts the TX clock symmetrical squarewave Signal to positive pulses to shift the TX
BCC generator. These one-shots and associated logic are
shown in Figure 4-63.

The CLEAR START one-shot is triggered when the output
(pin 8) of E89 goes high. The three inputs to this gate
respond to enabling of the BCC function in different ways.

4-104

High when either
TX BCC CNTRA or
TX BCC CNTR B
flip flop is set

8
3
09-5 TX TOTAL TRANS (1)H

5
4

05-6 TX ACTIVE (0 H

R22
C96

C97

08-5 TX BCC SH EN L
04-3TXCLOCKH---+-=~~

11 09-5 CLR
TX BCC L
08- 5 INH SH TX BCC L
05-6 SYNC EN (1) L
09-1 +3V
09-2 INI L---~
11- 2777

Figure 4-63 TX BCC Shift and Start/Clear Logic

Input pin 9 responds when either the TX BCC CNTR A or
TX BCC CNTR B flip-flop is set. This occurs when the TX
BCC control logic is in process of generating 09-5 BCC
REQ L for the condition requiring 2 or 3 BCC characters.
Input pin 10 responds when the BCC SEND ENABLE
flip-flop on the M7813 module is set (D5-6 BCC EN (1) L
asserted). This occurs when the BCC function is requested
via the logic at the top of this print (D9-5) which is
discussed later. This situation is appropriate when one BCC
character is desired. Pin 11 responds in two ways. The first
is when the M78I7 module is installed and asserts D8-5 TX
BCC SH EN L. This signal enters pin 11 of E89 via E76 pin
6. The second method is used when the M7817 module is
not used. The fact that the TX TOTAL TRANS flip-flop is
set and the fact that TX ACTIVE is set (D5-6 TX ACTIVE
(1) H asserted) are ANDed at E83. The resulting low signal
is delayed and sent to E89 pin 11 via E76 pin 6.
When the CLEAR START one-shot is triggered, the 50 ns
negative pulse from its 0 output asserts 09-5 CLR TX BCC
L at E79 pin 11. This signal can also be asserted by D9-2
INI L.
The signal that shifts the TX BCC generator is called D9-5
SHIFT TX BCC H. It is produced at the output (pin 6) of

3-input AND gate E71. Input pin 5 is high whenever the
BCC function is selected, as described above. Pin 3 is high
when two conditions are met at the inputs (pin 1 and 2) of
E76. One condition is that the M78I7 module is not
inhibiting the BCC function; that is, D8-5 INH SH TX BCC
L is high at E76 pin 1. If the M78I7 module is not
installed, this pin is held permanently high by +5 V via
resistor RI9.
The other condition is that the BCC, DLE, or data section
of the SEND ENABLE flip-flop on the M78I3 module
(D5-6) is set. This fact is sensed by using the 0 output of
the SYNC section of the SEND ENABLE flip-flop which
must be cleared if either the BCC, DLE or data sections are
set. In the case of BCC, the TX BCC shift signal is used to
transmit the accumulated BCC character. In the case of
DLE or data, the shift signal is necessary to accumulate the
BCC character while DLEs or data are being transmitted.
With this condition true, D5-6 SYNC EN (l) L is high to
E76 pin 2. The third input (pin 4) of E71 is connected to
the 1 output of the BCC SH PULSE one-shot. Whenever
D4-3 TX CLOCK H goes high, the BCC SH PULSE one-shot
is triggered. The SO ns positive pulse from its 1 output is
the third input to E7I which asserts D4-5 SHIFT TX BCC

4-105

this logic sends a signal to the RX Bee turn-on
logic that starts the RX Bee generator. When
the receiver exits total transparency, this logic
enables the RX Bee counter and allows reception of the selected number of Bee characters
before turning off the RX Bee generator. The
Bee counter logic can be qualified by the
M7816 module (jumpers) or the M7817 module
(signals) to select 1, 2 or 3 Bee characters. This
logic normally provides a one-character delay to
ensure that the last data character is included in
the Bee accumulation. It can be overridden in
case the message contains an odd number of
characters. This prevents a character time delay
between receiving the last data character and
the first Bee character.

4.6.7 RX BeC Control Logic

4.6.7.1 Functional Description - A simplified block diagram of the RX Bee control logic is shown in Figure 4-64.
The logic performs several functions that are interrelated
but can be described separately. The major functional areas
are listed below in order of discussion.
1.

RXP and RXS Save Logic. This logic looks
ahead to see if the receiver is going to enter the
total transparency mode. If it is, the logic
allows total transparency to be turned on one
transfer time sooner. The controlling factor is a
signal that represents the state of REG/ERR
eSR bit 14 (ENTER T).

RX Transparency eontrol and Bee eounter
Logic. The section of the logic that controls
total transparency is a function of the M7816
module only. It allows the receiver to enter and
exit total transparency under control of REG/
ERR eSR bits 14 (ENTER T) and 13 (EXIT
T). When the receiver enters total transparency,

B RX C L

RX Bee Turn-On Logic. This logic generates
pulses that shift the RX Bee generator. It
converts the RX clock signal to positive 50 ns
pulses that perform the shifting operation. It is
controlled by a signal from the RX transparency control and Bee counter logic
(M7816) or a signal from the M7817 module.

RX CLK H BCC ON SYNC (0 L -

WI H -

RX BCC
Turn On
Logic

SHIFT RX BCC H

'--

BCC ERR L

W2 H - RX BCC 5 L RX BCC 4 L TEST JUMPER L STRIP SYNC (1) H SYNC DET H -

RX Transparency
Control and BCC

Counter Logic
RX ZERO BCC H -

B CNTR LP H -

NOT RESTART L -

RX CYCLE H -

RX BCC
Test
Logic

...--- CLR RX BCC L

SP PORT 13 H TX CC ODD L

LD SP PORT L CC/BA ADRS 10 H CC/BA ADRS 9 H -

RX Pond
RXS Save
Logic

REG PT
Decoder

EN RX TRANSFER
PULSE H

CCIB A ADRS 8 H 11-2775

Figure 4-64 Block Diagram of RX Bee eontrol Logic

4-106

Test RX Bee Logic. This logic responds to a
signal from the RX Bee generator after the
data and Bee characters have been received. If
an erroneous message has been received (RX
Bee register not aliOs), the logic generates a
signal that sets two error flags in the REG/ERR
eSR: Bee ERR (bit 6) and ERR INTR (bit
15).

4.6.7.2 Detailed Logic Description RX P and RX S Save Logic
The RX P and RX S save logic is shown in the lower right
section of drawing D-eS-M7816-0-1 (Rev E) sheet 8 which
is designated D9-6.
This logic looks ahead to see if the receiver is going to enter
total transparency mode (block transfers with AA plus AB
option). If it is, this logic allows total transparency to be
turned on one transfer time sooner. Without this logic, time
would be lost because total transparency can only be

entered at the time that the character count is first used
(frrst transfer); and at this time, the character recognition
circuitry is disabled, which inhibits entering total transparency.
Figure 4-65 shows the RX PIS save logic plus the logic that
generates D5-2 DI PORT 14 Land D5-3 LD SP PORT L.
Derivation of these signals is discussed because it is an
important event in the sequence of activating the RX PIS
save logic.
When REG/ERR eSR bit 14 (ENTER T) is set, the RX
Bee control logic is conditioned to force the receiver into
the total transparency mode. The RX P/S save logic
examines signal D5-2 DI PORT 14 L which reflects the
state of REG/ERR eSR bit 14.
Assume that the program sets bit 14 (ENTER T) and 04-6
EE 14 (1) H is asserted by the REG/ERR eSR (M7812
module). This signal is sent to input A3 of ee/BA DATA
MUX 17, 16 (E47 on the M7813 module). This mux is

From 0 output
_6

r- •• r"\

~I"LI

"'I v

LlL..1

flip flop
From output of
CC/BA DATA MUX 17,16.
Low when REG/ERR bit
14 il SIt.

05-2 01 PORT 14L

09-1 +3V

From 0 output of
RX TOTAL
TRANS flip flop

09-6 EN RX
TRANSFER PULSE H

05-3 LO SP PORT L

Asserted when REG/ERR
bit 12 is set and secondary
reoister RX CC P or RX CC S
is 'written into.

E62 f9
7442
f8
PT
OCOR
f7
f6
12

03
09- 2 CC/BA AORS 10 H 13 02
14
09-2 CC/BA AORS 9 H
01

15 DO

09-2 CC/BA AORS BH

f4
Rll

IO-""--'VIIV--

+5 V

fl
fO

05-4 RX 5 (1) H
11-2799

Figure 4-65 RXP and RXS Save Logic

4-107

enabled (D5-3 BA L asserted) when the DQ 11 is not in the
ee/BA cycle. This means that the mux select input (SO) is
low (D5-3 ee/BA eYeLE H not asserted). The A input is
selected, so D4-6 EE 14 (1) H is transformed to D5-2 DI
PORT 14 L at output fl. This mux (E47) is a type 74S158
that provides an output that is the complement of the
input. Signal D5-2 DI PORT 14 L is sent to L'le input (pin
13) of inverter E82 in the RX P/S save logic. It is also
written into the ee/BA 17, 16 memory (E46) and read out
as D5-2 SP PORT 14 H which is used in the TX Bee
control logic.

In order to write into one of the eight secondary registers,
it is necessary to select the register using memory address
inputs AO, Al and A2 and to put a low on the write (WR)
inpu t. In this discussion, only two secondary registers are
involved: RX ee primary (1s) and RX ee secondary (5 s ).
The address selection signals are D5-1 ee/BA ADRS 10 L,
9 L, and 8 L. The read/write control signal is D5-3 LD SP
PORT L which is also the enabling signal for the PT
decoder (E62) in the RX P/S save logic. It is generated as
follows.
REG/ERR eSR bit 12 (14, 13 WRITE EN) must be set to
allow the data in bits 13 (EXIT T) and 14 (ENTER T) of
the same register to be written into the ee/BA memory.
When bit 12 is set by the program and a DATO transaction
is performed on a secondary register (address 76XXX6
asserted), D5-4 LD EXT/TRANS H is asserted by the
register selection logic on the M7813 module. This signal is
sent to NOR gate E25 (M7813 module, print D5-3) to
generate a negative pulse at the output of E25 that is called
D5-3 LD SP PORT L. When this signal goes low, it allows
the data in REG/ERR eSR bit 14 or 13 to be written into
bits 17 and 16, respectively, of the ee/BA memory (E46).
It also enables decoder E62 in the RX PIS save logic. This
decoder is used as a 3-wire, binary-to-octal decoder that is
enabled when D5-3 LD SP PORT L is low. Binary coded
inputs D2, Dl and DO are used to select the outputs. These
signals are D9-2 ee/BA ADRS 10 H, 9 H, and 8 H which
are the inversions of D5-1 ee/BA ADRS 10 H, 9 H, and 8
H. The RX P/S save logic uses only two outputs: f1 and f5
which correspond to the RX ee P (Is) and RX ee S (5 s )
registers.

Assume that the receiver is running and it is using the RX
ee primary register which is nearing overflow. The program
sets REG/ERR eSR bits 14 (ENTER T) and 12 (14, 13
WRITE EN), selects the RX ee secondary register and
loads a character count into it.

4-108

The follOwing conditions exist:
a.

D5-2 DI PORT 14 L is asserted which
puts a high on the D input of the RX (S)
SA VE and RX (P) SAVE flip-flops.

D5-3 ill SP PORT L is high because
neither the RX ee primary or RX ee
secondary registers are being loaded. As a
result, the clock inputs to RX (S) SAVE
and RX (P) SAVE are high because the
E62 decoder is not enabled (input D3 is
low).

Both RX (S) SAVE and RX (P) SAVE are
cleared which drives the output of both
wire-ORed E67 gates high. This signal
inhibits the presetting of the RX TOTAL
TRANS flip-flop via gates E88 and E84.
It also puts a high on pin 11 of E68. The
other inputs (pins 9 and 10) of E68 are
also high so the output of this gate (D9-6
DIS RX TRANSFER PULSE L) is high.
This is a qualifying signal for the programmable character recognition logic
(M7817 module) and the hard-wired character recognition logic (M7818 module).
When D9-6 DIS RX TRANSFER PULSE
L is high, the character recognition can be
enabled at the next character count overflow.

The receiver is using the RX ee primary
register so D54 ~~ S (1) H is low. This
puts a low on pin 8 of E67 and is inverted
to put a high on bit 11 of the other E67
gate.

At overflow, the DONE logic (M7813 print
D5-4) switches from the RX ee primary
register to the RX ee secondary register. When
the RX ee secondary register is written into,
D5-3 LD SP PORT L goes low which enables
output f5 (RX ee secondary register). When
the D5-3 LD SP PORT L negative pulse times
out, its positive-going trailing edge clocks the
RX (S) SAVE flip-flop and sets it.

When the switch was made to the RX ee
secondary register, DS4 RX S (l) H goes high.
This signal is sent to pin 8 of NAND gate E69.
Its other input (pin 9) is high because RX (S)
SAVB is set; therefore, its output (pin 10) goes
low. This signal asserts D9-6 DIS TRANSFER
PULSE L at E68 pin 8 which inhibits the
character recognition logic (M7817 and M7818
modules).
Signal D9-6 DIS TRANSFER PULSE L goes to
E88 pin 11. The other input (pin 10) is also low
because the overflow pulse from the RX bit
counter (M7813 print DS-7) caused the
assertion of DS-7 TEST JUMPER MA TeH L.
The high output of E88 is sent to E84 pin 11.
The other inputs (pins 9 and 10) of this gate are
also high because D4-6 SYNe DET H is low.
This drives the output of E84 low which
directly sets the RX TOTAL TRANS flip-flop
via its preset input. The low from the 0 output
of RX TOTAL TRANS asserts D9-6 RX
TOT AL TRANS (1) L.

The BeC counter logic is conditioned by the transparency
control logic (M7816 only) or by signals from the M7817
module.
The following example is used to discuss the operation of
the logic. It is desired to force the receiver into the total
transparent mode, accept the data, exit total transparency,
accept two BeC characters and shut off the RX Bee
generator. The example assumes that transparency control
is provided by the M7816 module and that the message
contains an even number of characters (odd count logic not
enabled). The M7817 module is not installed.

The program sets REG/ERR eSR bit 14
(ENTER T) which is a requirement to force the
receiver into the transparent text mode. When
the RX ee primary or secondary register is
loaded, the RXP /RXS save logic sends a low
signal to E88 pin 11 (print D9-6). (The
RXP/RXS save logic is discussed in a subsequent section.)

The receiver start up logic (print DS-7) asserts
DS-7 TEST JUMPER MATeH L which is sent
to the other input (piT1 12) of EBB. This drives
the output of E88 high and this signal goes to
pin 11 of 3-input NAND gate E84. The other
inputs of this gate are also high via E64 pin 11
because D44 STRIP SYNC (l) H is low. This
Signal comes from bit 1 of the RX eSR and is
not used when the transparency mode is used;
that is, stripping of sync characters is inhibited
in this mode; however, it is still used between
total transparent blocks.

The output of E84 goes low and directly sets
the RX TOTAL TRANS flip-flop. The 0 output
of RX TOTAL TRANS causes the RX BCe
turn-on logic to generate RX Bee shift pulses
(D9-6 SHIFT RX Bee H) which starts the RX
Bee generator. (The operation of the RX Bee
tum-on logic is discussed in a subsequent
section.)

The RX PIS SA VB logic has looked ahead and determined
that the receiver wants to enter the total transparent mode.
At the next character count overflow, when RX ee
registers are switched, it inhibits character recognition and
asserts the signals to put the receiver in total transparency.
REG/ERR eSR bit 13 (EXIT T) is set by the program to
allow the receiver to exit from the total transparent mode
and to enable character recognition.
At the next character count overflow (which assumed that
the next ee contained an EXIT T character), D9-S B eNTR
LP H clocks the RX TOTAL TRANS flip-flop which clears
it. The details of this operation are discussed in subsequent
paragraphs.
RX Transparency Control and BCC Counter Logic
The RX transparency control and BeC counter logic is
located in the left center section of print D9-6. It is also
shown in Figure 4-66.
The transparency control logic allows the receiver to enter
and exit the transparent text mode by using REG/ERR
eSR bits 14 (ENTER T) and 13 (EXIT T). This mode of
operation is termed total transparency to differentiate it
from the control of transparent text provided by the
M7817 module, when it is installed.

4-109

The receiver accepts the message and examines
each bit via the RX Bee generator. When the
end of data appears, the receiver is brought out
of the transparent mode. The RX Bee counter
logic is enabled to allow reception of the two
Bee characters before the RX BeC generator is
turned off. This sequence is described below.

08-6 RX TRANS L
09-6 RX TOTAL TRANS (1) L

04-4 STRIP SYNC (1) H

04-6 SYNC OET H

o ' r - - - - - - - r - - - 08- 4 RX BCC 5 L.

R2
04-5 B CNTR LP H
05-3 RX CYCLE H
05- 2 SP PORT 13 H

+5V

r-------- 09-6 W1 H

09-2 INI L
- 08-4 RX Bce 4 L
4

0
4

9
05-7 B RXC L

1 8
E74
7474
RX BCC
9
CNTR AO
11 C
8

'o!-09-1 +3V
10
9
8

13
05-8 RX CC 000 L------+----4:lt
04-3 RX CLK H - - -

08-6 BCC ON SYNC (1) L - - - - - + - - - I
10

9
1':.77 1 8
7'474

END OLY
11 C

0 8

To Save Logic

13
L - - - - - - I - - _

11-2797

Figure 4-66 RX Transparency Control and BCC Counter Logic

The program sets REG/ERR eSR bit 13 (EXIT
T) which is a requirement for allowing the
receiver to exit the transparent text mode.
When bit 13 is set and ee/BA is in the ee cycle
signal D5-2 SP PORT 13 H is asserted and sent
to pin 3 of 3-input NAND gate E84. The DQll
is in the receive mode so D5-3 RX eyeLE His
asserted. This puts a high on the second input
(pin 4) of E84. When the ee/BA counter is
loaded after overflow, signal D9-5 B eNTR LP
H is asserted. This is the third input to E84; and
when it goes high, the output (pin 6) of E84
goes low.

Signal D9-5 B eNTR LP H is a pulse so the
output of E84 is a negative pulse. The positivegoing trailing edge at E84 pin 6 clocks the RX
TOTAL TRANS flip-flop and clears it. The high
signal from the 0 output of this flip-flop
enables the two E67 gates associated with
jumpers WI and W2. The jumpers are set to
select two Bee characters (W2 is in and WI is
out). The outputs of these gates are connected
to the preset inputs of the Bee counter
flip-flops. Tn this case, R_X BCC CNTR A is not
affected and remains cleare<l; RX Bee eNTR B
is directly set. This sets up the counter logic to
allow reception of two Bee characters.

The low signal from E84 pin 6 also directly sets
the END TT Bee eONT L flip-flop. The END
DLY flip-flop is set and remains in this state
until cleared by the GLITeH flip-flop. The
outputs of these flip-flops via gates E73 and
E75 put a low on the D input of RX Bee
eNTR A. This provides a one-character delay
before starting the Bee character count.
When the RX bit counter overflows, signal D5-7
B RX e L is asserted and sent to pin 1 of
inverter E69. This inverted signal clocks RX
Bee eNTR A which does not change state
because its D input is low. This represents the
one-character delay. This signal also clocks
END TT Bee eNTL which clears it. This in
turn puts a high on the D input of RX Bee
eNTRA.
The second RX bit counter overflow causes RX
Bee eNTR A to be set. There is no change in
state for RX Bee eNTR B (remains set).

The third RX bit counter overflow causes RX
Bee eNTR A to be cleared. When this occurs,
the 0 output of this flip-flop clocks RX Bee
eNTR B and clears it. At this point, both Bee
characters have been received. Both RX Bee
eNTR A and RX Bee eNTR B are cleared. The
high signal from the 0 output of each flip-flop
is sent to an input of E73. With both flip-flops
cleared, both inputs (pins 12 and 13) of E73
are high which drives the output (pin 11) low.
This low signal goes to pin 8 of E95. The other
input (pin 9) of E95 is also low via the
DEGLITeH flip-flop. This drives the output
(pin 10) of E95 high which is sent to the RX
Bee turn on logic to inhibit D9-6 SHIFT RX
Bee H and thus turn off the RX Bee generator.

The DEGLITeH flip-flop mentioned in step 9 latches the
state of the signal at the output (pin 11) of E73. This signal
is controlled by the states of RX Bee eNTR A and RX
Bee eNTR B and is sent to the Bee start logic. The
DEGLITeH flip-flop prevents transients that could occur
when the counter flip-flops change state. A transient could

arbitrarily change the state of the signal at E73 pin 11 and
cause an unwanted triggering of the Bee start logic.

Bee Tum-On Logic
The Bee turn-on logic is located in the upper right section
of print D9-6. It is also shown in Figure 4-67.

It turns on the RX Bee genera tor by asserting D9-6 SHIFT
RX Bee H which shifts the generator. The Bee turn-on

logic is controlled by the total transparency logic on the
M7816 module or by the M7817 module, if the protocol
option is installed. Once the receiver accepts the required
number of Bee characters, the appropriate control logic
(M7816 or M7817) shuts off the RX Bee generator by
inhibiting the shift pulses.

Operation of the logic is explained by discussing two
examples of Bee turn-on. One example assumes that only
the M7816 module is used (total transparency control logic
activates the Bee turn-on logic). The other example
assumes that the protocol option (M7817) is installed and it
generates the control signals to activate the Bee turn-on
logic.

4-111

+5V
R7

08 -6 DES RX BCC SH l
04- 3 RX CLOCK H ---.::.....----'--ll----r---t

R23

+5V~

?E>B
10

74123
SH RX
BCC

E66

09-6 SHIFT RX BCC H

3
1

09-6 RX TOTAL TRANS (0) H --R-5-+----I

+5V-"'I'tI'v--I

08-6 BCCON SYNC (Ill -----'----~Q

from RX BCC _ _ _ _ _ _-'--_ _-+_ _ _ _ _ _ _--'
counter IOllic

04-3 RX ClK H
05-7 B RX C l - - - - - ' - - < I

11-2790

Figure 4-67 Bee Turn On Logic

As the transparent data is being received by the
OQ11 and transferred to memory, it is
examined by the RX Bee generator. When data
ends, the OQll exits the total transparency
mode and accepts two BCC characters. At this
point, the RX Bee generator is shut off as
follows.

Example 1

M7817 module not installed. The total transparency logic
on the M7816 controls the operation of the Bee turn-on
logic.
1.

When entering RX total transparency, the RX
TOT AL TRANS flip-flop is set. The low from
its 0 output is sent to E76 pin 9 which directly
sets the RX Bee ON flip-flop via its preset
input.

The low from the 0 output of the RX Bee ON
flip-flop is sent to pin 12 of E83 which drives
its output high. (The other input of E83 is held
high until the Bee counter logic is qualified.)

The high from E83 goes to pin 2 of 3-input
AND gate E71. Pin 1 is held high by +5 V
because the M7817 module is not installed and
signal 08-6 DES RX Bee SH L is not present.
The third input (pin 13) is pulsed high for
approximately 50 ns by the 1 output of oneshot SH RX Bee that is triggered by the
receiver clock (04-3 RX eLoeK H). The
positive output pulse at E71 pin 12 is 09-6
SHIFT RX Bee H which shifts the RX Bee
generator.

4-112

When the OQ11 exits the total transparency
mode, the RX Bee control logic clears the RX
TOTAL TRANS flip-flop which puts a high on
E63 pin 9. Pin 10 is high via +5 V because the
M7817 module is not installed and signal 08-6
Bee ON SYNe (I) L is not present.

When the two Bee characters are received, the
Bee counter logic drives the third input (pin
11) of E63 high. Now, with all inputs high, the
output of E63 goes low and directly clears the
RX Bee ON flip-flop. Both inputs of E83 are
now high so its output goes low. This signal is
sent to E71 and inhibits the RX Bee generator
shift signal (09-6 SIDFT RX Bee H is held
low). The RX Bee generator is turned off.

Example 2
M7817 module installed. Protocol logic on the M7817
controls the operation of the Bee turn-on logic.
1.

With the jumper in, the RX Bee ON flip-flop is preset via
E76 pin 8 when D8-6 Bee ON SYNC (1) L is asserted. This
turns on the RX Bee generator at the start of the first
character, which is the control character.

The M7817 module drives D8-6 DES RX Bee
SH L high to produce a qualifying input (pin 1)
for 3-input AND gate E71. At this time, pin 2
of E71 is low because both inputs (pins 12 and
13) to E83 are high, due to the fact that the
RX Bee ON flip-flop and both Bee counter
flip-flops are cleared.

Test RX Bee Logic
The test RX Bee logic is located in the right center section
of print D9-6. It is also shown in Figure 4-68.

The M7817 module asserts D8-6 Bee ON
SYNC (1) L at E63 pin 10 which puts a high on
the input of the RX Bee ON flip-flop (E63 pins
9 and 11 are high).
The clock input of RX Bee ON is connected to
the output (pin 11) of AND gate E76. One
input (pin 12) is connected to the inversion of
D4-3 RX eLK H which is the receiver clock
signal. The other input (pin 13) is connected to
the inversion of DS-7 B RXC L which is the
buffered overflow pulse from the RX bit
('nllntpT
___ "._A (M7Rl~
,A._, ___ mntill1p
•• A___ A_ nnnt
rAA ••• n'\-7)
__ '/'

At the first overflow of the RX bit counter,
DS-7 B RXe L is asserted and puts a high on
E76 pin 13. When pin 12 goes high due to the
RX clock signal, the output (pin 11) of E76
goes high and clocks the RX Bee ON flip-flop
which sets it.

The low from the 0 output of RX Bee ON puts
a high on E71 pin 2 via E83. Now, the positive
pulses from one-shot SH RX Bee assert D9-6
SHIFT RX Bee H which shifts the RX Bee
generator.

As noted in step 4, the RX Bee generator is started one
character time after the receiver enters the Bee mode. This
prevents the protocol character that caused Bee to start
from being included in the Bee accumulation. Jumper W3
on the M7816 module determines whether or not the
control character is included in the RX Bee accumulation.
With the jumper out, the control character is not included.

When the DQ 11 exits the Bee mode and the two Bee
characters have been received, the RX Bee generator is
shut off in a manner similar to that discussed in Example 1,
except that D8-6 Bee ON SYNC (1) L going high is the
controlling factor.

When the last Bee character is received, input pin 2 of the
TEST RX Bee one-shot goes high which triggers it. The
positive pulse from the 1 output of this one-shot goes to
pin 1 of NAND gate E64. The other input (pin 2) of this
gate is connected to the inversion of D9-3 RX ZERO Bee
H via inverter E69. If the received message (including the
Bee character) is received correctly, D9-3 RX ZERO Bee
H goes high. In this case, D9-6 Bee ERR L is not asserted
at the output (pin 3) of E64. If the received message
contains an error, the contents of the RX Bee generator is
not zero and D9-3 RX ZERO Bee H goes low which asserts
D9-6 Bee ERR L at E64. This signal sets two error flags in
the REG/ERR eSR: Bee ERR (bit 6) and ERR INTR (bit
15). These flags indicate that the received message contains
one or more errors. The RX Bee generator only indicates
the reception of an erroneous message. It cannot correct
errors or even locate them. The message must be retransmitted.
If an erroneous message is received, the assertion of D9-6
Bee ERR L in tum asserts D9-6 eLR RX Bee L which
clears the RX Bee generator. This is required to clear out
the bits that contains 1s because an erroneous message has
been received. This must be done before the next Bee
accumulation is started.
Signal D9-6 eLR RX Bee L is also asserted by D9-2 INI L
and D8-6 NOT RESTART L. The latter signal is generated
by the M7817 module and its function is covered in the
discussion of this module. This signal is not present when
the M7817 module is not installed; therefore, +5 V is
applied to pin 3 of E68 to inhibit this function.

4-113

Non -zero contents of
RX Bee generator asserts
this signal. It sets
REGI ERR bit6 ( Bee ERR
flag) and bit 5 ( ERR
INTR flag.)

From RX Bee counter
logic. Goes high
when last Bee
character is recei ved

From E95 pin 10
09-6 Bee ERR L

+3V

11
09-3 RX ZERO Bee H - - - - - - 4 1

+ 5V

08-6 NOT RESTART L _ _ _ _ _ _ _ _ _ _.....JiL.....-_...J!
09-2 IN! L - - - - - ' - " " - H

09-6 CLR RX BCC L

r
Non-zero
contents
of RX Bee generator
asserts this signa!
which clears the
RX Bee generator.

11-2791

Figure 4-68 Test RX BCC Logic

4.7 M7817 MODULE (CHARACTER DETECT AND
SEQUENCE CONTROL)
4.7.1 Introduction
The M7817 module is a hex-height, extended-length,
module that contains several functionally separate logic
circuits. They are listed below in the order of discussion.
1.

Character Detect and Sequence Registers

Transmit and Receive Compare Logic

Character Detect Control Logic

Sequence Decoding Logic

Transmitter Protocol Control Logic

Receiver Protocol Control Logic

4.7.2 Character Detect and Sequence Registers
4.7.2.1 Functional Description - The character detect and
sequence registers are 16 word by 16 bit, random access,
semiconductor (TTL) memories that provide nondestructive readout.

With character recognition enabled, characters to be
detected are written into the character detect memory by
the program. The desired functions to be performed by the
hardware are selected by setting the appropriate bits in the
corresponding word of the sequence register.
The output of the receiver buffer register and the output of
the transmitter shift hold register are compared with each
word of the character detect memory in succession. When a
received character (in RX buffer register) or a character to
be transmitted (in TX shift hold register) matches any
character in the character detect memory, a hardware
control sequence is initiated in accordance with the bits set
in the sequence register for the associated word.
The outputs of the character detect register go to Unibus
drivers on this module so they can be read by the program.
The outputs of the sequence register are read by sending
them to the bus selectors on the M7816 module and then
to the driver section of the bus transceivers. The data inputs
to both memories come from the Unibus to receivers in the
M7816 transceivers and then to buffers on this module.
The character detect register and sequence register use
separate read/write control signals; they use common
address select signals.

4-114

The enable (ENB) input of each 3101 is permanently
connected to ground which holds it enabled. For a selected
word, a write operation is performed when the write (WR)
input is low and a read operation is performed when this
input is high. A write operation places the input data into
the selected word. In a read operation, the complement of
the information that has been written into the selected
word is non-destructively read out at the four outputs
which are MO (1)-M3 (1). The write input for the character
detect register is D8·3 CM WE L and for the sequence
register it is D8·3 SEQ WE L.

Figure 4-69 is a simplified block diagram showing only data
flow for the character detect and sequence registers.
4.7.2.2 Detailed Logic Description - The circuit schematics for the character detect and sequence registers are
contained in drawing D-CS-M7817-O-1 (Rev C) sheet 3,
which is designated D8-1. A typical 4-bit section of the
character detect and sequence register is shown in Figure
4-70.
In each case, 16 4-bit words are contained in a single TTL
64-bit read/write semiconductor memory (type 3101).
The 16 words are addressed by the 4-bit binary number
sent to the address inputs (AO-A3) of the memories and
are represented by signals D8-3 CHAR CNTR 1 (l) H, 2 (1)
H, 4 (1) H, and 8 (1) H. These signals are generated by a
counter and are common to all 3101 memories that make
up the character detect and sequence registers. The counter
increments through 16 states, overflows and continues
incrementing. this provides continual sequential addressing
of the character detect and sequence registers as long as the
character detect logic keeps the counter active.

Both registers use common data inputs (D9·1 DO H-D9-1
DIS H) which are buffered and inverted before being sent
to the 3101 inputs. These signals come from the receiver
section of the bus transceivers on the M7816 module. They
are picked off the Unibus data lines and inverted by these
receivers.
The outputs of the sequence register are sent to the bus
selectors on the M7816 module where they can be read by
the program.

UNIBUS

("M7816

I
I
I
I
I

UNIBUS

CHAR
DET

REG

I
I
L __ _
11- 2792

Figure 4-69 Data Flow for Character Detect and Sequence Registers

4-115

F rom bus rece ivers
on M7816 which
invert sionais
. . . . . - - - - - - - - 08-1 CMO H
7

BUS DATA 00 L

3101
E13
5
MO(1)
DO

.--4------- 08-1 CMl H
BUS DATA 01 L

CHAR MEM
3-0
10

09-1

. . . . . - 4 - - - - - - - 08-1 CM2 H

M2(t) 9

BUS DATA 02 L

M3(t)
03
A3A2 Al AO
13 14 15 1

.....--f------- 08-1 CM3 H

BUS DATA 03 L
8881 BUS
DRIVERS

08-3 SEQ WE L ----Hr-+-t--...,
6

WR
01

Outputs of both
memories sent to
M7816 bus selectors.

EN
7
M' (1) J.!-~I-I-t--------t------- 08 -1 SEQ 0 H

3101
E14
5
MOO) ~~~~~-----~------08-1 SEQ1H
DO

Selects 1 of 16 4 bit
words per each 3101
memory. Common to
CHAR MEM and SEQ MEM

SEQ MEM
3-0
M2(1) ~~~1-1-------t-------08-1
9
SEQ2H
02

M3(t) ~~~~I-------t------11
08-1 SEQ 3 H

A3 A2 A' AO
13 14 15 1

08-3 CHAR CNTR 8(1) H - - -........-+-+---t-~
08 -:3 CHAR CNTR 4(1) H - - - - - + - - t - - t - - -....

08-3 CHAR CNTR 2(1) H
08- 3 CHAR CNTR t( 1) H

09- 2 CM -BUS H

9 E8
_ _____

_8_ _...... ,9
0

E48

NOTE:
For 3101 memories.
1. With WR input low,
input is written Into
selected location.
2. With WR input high,
complement of data
in selected location
Is read.

8
11-2595

Figure 4·70 4· Bit Slice of Character Detect and
Sequence Registers

4·116

In the transmit mode, four simultaneous comparisons are
made using the output of the TX shift hold register. This
register is parallel-loaded on a word basis (double characters). The comparisons are listed below.

The outputs of the character detect register are sent to type
8881 bus drivers. The enabling signal for the drivers is D9-2
CM ~ BUS H which comes from decoding logic on the
M7816 module. This signal is double-inverted before being
applied to the bus drivers.

High byte with character detect high byte.

4.7.3 Transmit and Receive Compare Logic

Low byte with character detect high byte.

4.7.3.1 Functional Description - Each received character
and character to be transmitted is compared with each
word in the character detect memory. When character
detection is enabled, only characters of 8 bits or less can be
processed. Practically speaking, word matches are doublecharacter matches.

Complete word with character detect word.

Saved word with character detect word. This
consists of present low byte with character
detect high byte and previous high byte with
character detect low byte. This comparison is
used to detect a double-character match that
consists of the high byte of the previous word
and the low byte of the current word. That is,
it detects a successive double-character control
sequence that is split between two words.

In the receive mode, two simultaneous comparisons are
made using the output of the receiver buffer. Each
incoming character in the high byte of the RX buffer is
compared to the high byte of the character detect word.
Each RX buffer word is compared with the character detect
word.

CHAR oET REG

TX SH HOLD REG

Figure 4-71 graphically illustrates the various comparisons.

Byte Comparisons

CHAR DET REG

' - - - - . . -.......~r--..,j

TX SH HOLD REG

Word Comparison

CHAR DET REG

"--_-...J..-_-.J

TX SH HOLD REG ~_ _..i-_ _""""_ _ _"""'_ _""

Previous Word

Present Word

Allows comparison of a successive double character
control sequence that is split between two words.
Saved Word Comparison
11-2795

Figure 4-71 Graphical Representation of RX and TX
Character Comparisons
4-117

A simplified block diagram of the comparison logic is
shown in Figure 4-72. Multiplexers are used to select the
received characters and characters to be transmitted for
comparison with the characters in the character detect
register. Bit-by-bit comparisons are made in digital comparators whose outputs are wire-O Red to produce the
desired output only if all bits match. A flip-flop register is
used to store the TX high byte that is to be used in the
saved word match.
The comparator output and two control signals (bits 14 and
IS of the SEQ register) are used in the comparator output
logic to select the desired match configuration.
4.7.3.2 Detailed Description - The circuit schematic for
the transmit and receive compare logic is shown in drawing
D-CS-M7817-O-1 (Rev C) sheet 4, which is designated D8-2.
The 16 outputs of the receiver buffer (D4-S RD 0 H-D4-S
RD ISH) and the 16 outputs of the transmitter shift hold
register (D4-S TD 0 H-D4-S TD ISH) are sent to the
inputs of 4 type 74157 quad 2-input multiplexers (E42,
E46, E19 and E21) that are labeled RX/TX SEL. For each
multiplexer, the strobe (STB) input is permanently connected to ground which keeps the multiplexer enabled. The
select (SO) input is connected to D8-3 RX SEARCH H
which is generated by the character detect logic. This signal
is high when received character matches are desired; hence,
it selects the received character inputs (BO-B3) of the
multiplexers. When transmitted character matches are
desired, this signal is low and it selects the transmitter
inputs (AO-A3) of the multiplexer.
Each of the 16 multiplexer outputs goes to one input of an
8242 exclusive-NOR that is used as a digital comparator.
The other input of each 8242 is connected to the same
numbered bit in the character detect memory. The 8242 is
an exclusive-NOR; hence, its output is high only when both
inputs are the same. The output is a bare collector so
multiple-bit comparisons can be made by a wire-ORed
connection of several 8242s.
The low byte (bits 7-0) comparator outputs are wire-ORed
and the high byte (bits 15-8) comparator outputs are
wire-ORed and the resulting signals are sent to the match
decoding logic.

The high byte of the transmitter shift hold register (D4-S
TD 8 H-D4-S TD ISH) is sent to the TX hold register that
is composed of two 74175 quad flip-flops (E41 and E47).
This byte is held in the register to be used in the saved word
comparison. The clock signal for the TX hold register is
DS-6 LD TX SH REG H and is generated by the TX control
logic on the M7813 module. The output of the TX hold
register is compared with the low byte of the character
detect register using eight wire-ORed 8242s. The match
signal is sent to the match decoding logic.

The match decoding logic consists of four 74Hll 3-input
AND gates and one 7402 2-input NAND gate. The upper
two AND gates (E20 pin 8 and E20 pin 12) produce
byte-match signals. D8-2 LB MATCH H is generated at E20
pin 8 when a match is detected between the TX low byte
and the character detect memory high byte. D8-2 HB
MATCH H is generated at E20 pin 12 when a match is
detected between the RX or TX high byte and the
character detect high byte. However, two qualifying signals
must be present at both gates before the match signals can
be asserted at their outputs. One qualifying signal is D8-1
SEQ ISH which is asserted when bit 15 of the sequence
register is set by the program. The other qualifying Signal is
D8-2 DBL MATCH L from NOR gate ES9 pin 4. This signal
is asserted when a word or saved word match is detected
and bit 14 of the sequence register is set by the program
(D8-1 SEQ 14 H is asserted). Under these conditions,
double-character detections take priority over singlecharacter detections because when D8-2 DBL MATCH Lis
low it inhibits the generation of both D8-2 LB MATCH H
and D8-2 HB MATCH H. This occurs even if D8-1 SEQ IS
H is asserted to qualify the logic for single-character (byte)
detections.
The lower two AND gates (E20 pin 6 and E28 pin 6)
produce word match signals. D8-2 WORD MATCH H is
generated at E20 pin 6 when a match is detected between
the RX or TX word (2 characters) and the character detect
memory word. D8-2 SAVED WORD MATCH H is generated at E28 pin 6 when a match is detected between the
TX saved word and the character detect memory word.
These match Signals cannot be asserted unless bit 15 of the
sequence register is set by the program (D8-1 SEQ ISH is
asserted).
4.7.4 Character Detect Control Logic

The low byte of the transmitter shift hold register (D4-S
TD 0 H-D4-S TD 7 H) is sent directly to eight wire-ORed
8242s to be compared with the high byte of the character
detect register (D8-1 CM 8 H-D8-1 CM IS H). The match
signal is sent to the match decoding logic.

4.7.4.1 Functional Description - A simplified block diagram of the character detect control logic is shown in
Figure 4-73.

4-118

c::::.v) RX/TX
-".

RDt5-8 H

TD15-8 H

SEl 15-8
MUX

...)

RX SEARCH HJ

I \

r------.J

....

15-8

. ""

CM15-8 HI

t\.

RX/TX
15-8

I I
I I
VI

COMPARATOR

TX HOLD
REG
15-8

lD TX SH REG H

,.)

TX 15-8
HOLD

r'\,

I ,
I ,

r------l
CM
7-0 H

I /
1/
V·

DBl MATCH l

l.......-

.....

COMPARATOR
~

.,./

TX 7-0

~,
i \
I

--------l
.A

.,.)

CM
15-8

I I
1/

RD 7-0 H

e L:Jv
"'"
~

RX/TX
SEl 7-0
MUX

RX SEARCH H

~
rV

RX/TX
7-0
CM

HB MATCH H

.-.

LB MATCH H

SEQ 14HJ

V·

SEQ 15 H-

I \
I \

r-------I
7-0

WORD MATCH H

COMPARATOR
TO 7-0 H

SAVED WORD MATCH H
MATCH
DECODING
lOGIC

I I
I /
1/

it
COMPARATOR

CM7-0 HI
11-2596

Figure 4-72 Block Diagram of Comparison Logic

4-119

CHAR CNTR 8 (1l H
CHAR CNTR 4 (1) H

r - - - - - . CM WE L

CHAR CNTR 2 (\) H

SEQ WE L

CHAR CNTR , (1) H
1-

CHAR INTR L

CD "

D11H-

LD CHAR OET L LD SEQ L
B RX ACTIVE H
B TX ACTIVE H

CD 10H
CHAR
CNTR

LOAD
AND
CLOCK
LOGIC

CHAR
DET
HOLD
REG

CD 9 H
CD 8 H

LD RX 15-8 H
CLOCK

TX TRANS (I)L
RX TRANS(t) L

OLE ADD (7-0) L

SEQ 9 H

OLE ADD (15-8) L

RX BCC CYCLE L
RX SEARCH H

TEST JUMPER MATCH L
1-TX SEARCH RQ H
SKP FRAME L

SEARCH
INCREMENT
AND TEST
LOGIC

TX SEQ STROBE A H

TEST PULSE
LB MATCH H

STROBE
DECODING
LOGIC

HB MATCH H

TX SEQ STROBE B H
RX SEQ STROBE H
OLE STRIP H

WORD MATCH H

EN RX TRANSFER PULSE H

SAVED WORD MATCH H
OLE SAVE (1) L

RX SEARCH

DONE L
11- 2793

Figure 4-73 Block Diagram of Character Detect Control Logic

The search, increment and test logic responds to each
received character and each character to be transmitted by
causing the character detect register to step through all 16
words, starting at word 0 and ending at word 15. The
stepping action is controlled by the character counter
which is clocked by this logic. The counter outputs (D8-3
CHAR CNTR 1 (1) H, 2 (1) H, 4 (1) Hand 8 (1) H are the
address lines for the character detect memory. At each step,
the character detect memory word is compared with the
character being processed and a match signal is generated if
they agree. The match signal is sent to the strobe decoding
logic. After clocking (incrementing) the character counter,
the search, increment and test logic generates a pulse that
tests the strobe decoding logic. One of three strobe signals
is generated depending on the type of match that occurred.
The strobe signal is used to initiate a hardware control
function, determined by the bit set in the corresponding
word of the sequence register. When the character counter
reaches a count of 15, the next clocking pulse causes the

counter to overflow (return to count 0) which stops the
search operation until another character (receive or transmit) enables the search, increment and test logic again.
Setting bit 12 or 13 of the sequence register allows the
received character that caused the match to set the
character flag bit (bit 15 of the RX CSR). In this case, the
character counter output is also latched in the character
detect hold register. The output of this register (D6-1 CD8
H-l1 H) represents the address of the control word in the
character detect memory at the time the match occurred.
This address is sent to the bus selectors on the M7812
module where it can be read by the program.
The counter load logic is used to load the character counter
with the address of the word in the character detect register
or sequence register that requires access for a write or read
operation. This logic is enabled only when both the receiver
and transmitter are not active.

4-120

4.7.4.2 Detailed Logic Description - The circuit schematic for the character detect control logic is contained in
drawing D-CS-M7817-O-1 (Rev C) sheet 5, which is
designated D8-3.
Search, Increment and Control Logic
The search, increment and control logic is located in the
left center portion of D8-3. This logic is explained by
describing a typical operation.
1.

TX TOTAL TRANS L not asserted). The
output (pin 8) of E33 goes low and is inverted
by E4. This Signal is applied to the strobe
decoding logic as a qualifying input.
6.

The trailing edge of the negative pulse from the

o output of the INCR one-shot triggers the

TEST one-shot. The positive pulse from its 1
output is sent to all input gates in the strobe
decoding logic as an enabling Signal.

Assume the following conditions
a.

CHAR CNTR is at count O.

The control characters have been loaded
into the character detect register and the
appropriate bits have been set in the
sequence register.

The search operation is to be initiated by
a character to be transmitted.

During a TX NPR cycle, the TX control logic
on the M7813 module generates D5-6 1 -+ TX
SEARCH RQ H which docks the IX SEARCH
RQ flip-flop and sets it because its D input is
held permanently high by E6 pin 6.

The low at the 0 output ofTX SEARCH RQ is
inverted by E73 pin 11 and puts a high on pin
10 of AND gate E65. The other input (pin 9) of
this gate is high because the CARRY HOLD
flip-flop is cleared. This puts a high (via E65 pin
8) on the D input of the CHAR SEARCH
ACTIVE flip-flop, which at this point is cleared
and therefore puts a high on pin 4 of E65.

The high at E73 pin 11 also triggers the INCR
one-shot. The positive pulse from the 1 output
of INCR drives E65 pin 6 high which clocks the
TX/RX SEARCH flip-flop and sets it. The D
input of this flip-flop was high because the RX
SEARCH flip-flop is cleared. This positive pulse
cannot get through E73 pin 3 to clock CHAR
CNTR because this gate is disqualified by the
low from the 1 output of CHAR SEARCH
ACTIVE.

The negative pulse from the 0 output of TEST
is inverted by E43 and clocks the CHAR
SEARCH ACTIVE flip-flop and sets it. The
high from the 1 output of this flip-flop goes to
E73 pin 1. The high Signal qualifies this gate so
that subsequent positive pulses from the INCR
flip-flop to the other input (pin 2) of E73 can
clock CHAR CNTR.

The 0 output of TEST, which is inverted by
E43, is fed back to the input (pin 9) of INCR
which retriggers it. The INCR and TEST oneshots are connected as a multivibrator and
aliernaieiy reirigger uniii ihe IX REQUEST
flip-flop is cleared (Figure 4-74).
SUMMAR Y OF OPERATION

When TX/RX SEARCH is set, the high from its
1 output goes to E33 pin 9. The other input to
this gate is also high because total transparency
is not activated by the M7816 module (D9-5

4-121

The TX search request initiates the increment/
test operation which is to step through the
character register to compare each of the 16
control words in the register with the character
to be transmitted. The character counter starts
at a so word a is to be examined first. The
increment phase is inhibited and word a is
tested for a match. The logic is now set up so
that the next increment phase clocks the
character counter to count 1 and then tests
word 1 for a match.
9.

When the INCR is retriggered, the positive pulse
from its 1 output now gets through E73 pin 3
as a low and is sent to pin 1 of E33. The other
input (pin 2) of this gate is high because D8-5 B
TX ACTIVE H is asserted. This drives the
output (pin 3) of E33 high which clocks CHAR
CNTR and increments it to count 1. This
selects word 1 in the character detect register
for comparison with the character to be transmitted. The INCR one-shot retriggers TEST
which sends the enabling signal to the strobe
decoding logic.

..n.. if 10 is H
This signal is
the clocking
source for the
character counter.

74123
£8'4
INCR

SLif 9
is L

This signal
tests the
strobe logic.

13
74123
E84 1
TEST

o
CLR

o 4

CLR
+3V
+3V
+3V
4
5
2

05-7 TEST JUMPER
MATCH L

E81

RX
SEARCH
RQ
C

74123 TRUTH TABLE

INPUTS
5

This signal goes
low at end of
search operation
to clear request
flip-flops.

t3V
14

+3V

0~-6
1-.TX
SEARCH RQ H

9/1

10/2

5/13

1214

0 6

OUTPUTS

E81

SL '"L.r

0
TX
SEARCH
RQ

0 8

SL
13
11- 2594

Figure 4-74 Clock for Incrementing the Character Counter
and Testing the Strobe Logic

4-122

10.

Because of the INCR/TEST multivibrator, this
process continues until the counter reaches a
count of 15 which means that all 16 words
(0-15) in the character detect register have
been compared with the character to be transmitted.

11.

When CHAR CNTR reaches the count of 15, a
positive overflow pulse is produced at the CO
output (pin 15). This signal puts a high on the
D input of the CARRY HOLD flip-flop. The
TEST pulse associated with the INCR pulse,
which produced the count of 15, clocks
CARRY HOLD and sets it. The low from the 0
output of CARRY HOLD puts a low on the D
input of CHAR SEARCH ACTIVE.

12.

13.

The next INCR pulse clocks CHAR CNTR to
the count of O. It also clocks CARRY HOLD
and clears it because the CO pulse has gone
away and the D input of CARRY HOLD is low
again. The associated TEST pulse clocks CHAR
SEARCH ACTIVE and clears it. The low from
the 1 output of this flip-flop disqualifies E73
and prevents further clocking of CHAR CNTR.
When CHAR SEARCH ACTIVE is cleared, its 0
output triggers the END SEARCH one-shot.
The high pulse from the 1 output of END
SEARCH drives the output (pin 8) of E73 low.
This signal is buffered without a state change
and directly clears TX SEARCH. Both inputs
(pins 12 and 13) of E73 are now high so its
output goes low which inhibits the INCR
one-shot.

SUMMAR Y OF OPERATION
All 16 words in the character detect register
have been compared with the character to be
transmitted. The character counter is at count
0, the increment/test operation is not active
and the TX search request is cleared. The
search, increment and test logic is awaiting
another TX or RX search request to start the
sequence again.

Strobe Decoding Logic
The strobe decoding logic is located in the right center
portion of D8-3.

4-123

This logic generates three strobe signals (one for RX and
two for TX) that are used to enable the hardware
operations chosen by the sequence register. The RX str~be
signal is D8-3 RX SEQ STROBE H. TX strobe signal D8-3
TX SEQ STROBE A H is used for operations to be
performed on the current character. TX strobe signal D8-3
TX SEQ STROBE B H is used for operations to be
performed on the next character. Only one RX strobe
signal is needed because received characters are looked at
on a per-character basis. Characters to be transmitted are
loaded as double characters so two strobe Signals are
required.
The strobe decoding logic also generates three other signals
related to operations performed on DLE characters. If a
DLE character is to be stripped, D8-3 DLE STRIP H is
used. If a DLE character is to be added, two signals are
available to choose the proper location of the DLE. If it is
to be added in the low byte position, D8-3 DLE ADD
(7-0) L is used; for the high byte position, D8-3 DLE ADD
(15-8) L is used.
The enabling input to the strobe decoding logic is the high
pulse from the TEST one-shot, This pulse tests or samples
the strobe dec{)ding logic each time th~ character oot~ct
register is stepped.
Several qualifying signals are sent to the strobe decoding
logic.
1.

Four match Signals are sent from the RX/TX
compare logic (D8-2). They represent low byte,
high byte, word and saved word matches.

Bit 9 of the sequence register is used to control
DLE strip/add. The signal is D8-1 SEQ 9 Hand
when it is asserted the DLE is stripped in
receive mode and added to the specified byte in
transmit mode.

Neither TX strobe Signal can be generated when
the DQll is in the transparent text mode which
is indicated by the assertion of D8-5 TX
TRANS(1)L.

When a TX search request has started the
search, increment and test logic, a qualifying
signal is sent to that portion of the strobe logic
concerned with TX functions (TX strobes A
and B and both DLE add functions).

When an RX search request has started the
search, increment and test logic, a qualifying
signal (D8-3 RX SEARCH H) is sent to that
portion of the strobe logic concerned with the
RX strobe signals. D8-3 RX SEARCH H cannot
be asserted if the M7816 is in the total
transparency mode. This condition is represented by D9-6 EN RX TRANSFER PULSE H
which must be asserted to allow character
detect operation in the receive mode.

The RX strobe signal can be generated when
the DQll is in the transparent text mode which
is indicated by the assertion of D8-5 RX
TRANS (1) L, provided that D8-6 DLE SAVE
(1) L is also asserted.

The DLE strip operation also depends on D8-5
RX TRANS (1) L being asserted along with the
assertion of D8-6 DLE SAVE (1) L.

Character Counter and Character Detect Holding Register
The character counter (CHAR CNTR) , character detect
holding register (CHAR DET HOLD) and associated logic is
located in the top section of D8-3. This logic is shown in
Figure 4-75.
The character counter (E40) is a 74161 synchronous 4-bit
counter. The four inputs (pins 3-6) come from the Unibus
data lines via the receivers on the M7816 module. The
signals are D9-1 D8 H-D9-1 Dll H. The outputs are:
D8-3 CHAR CNTR 9 (1) H
D8-3 CHAR CNTR 4 (1) H
D8-3 CHAR CNTR 2 (1) H
D8-3 CHAR CNTR 1 (1) H

(MSB)

When the search, increment and test logic is operating,
CHAR CNTR is clocked by the INCR one-shot via gates
E73 and E33 pin 3. As CHAR CNTR is incremented, its
outputs are sent to the D inputs of flip-flop register CHAR
DET HOLD. If the program desires to know the address of
the control word in the character detect memory that
resulted in a match, the output of CHAR CNTR can be
latched into CHAR DET HOLD and read as bits 8-11 of
the RX CSR via the bus selectors on the M7812 modu1es.
This operation can be performed only if bit 12 or 13 (RX
CHARACTER FLAG) of the sequence register is set. Under
these conditions, the sequence decoding logic asserts D84
1 ~ CHAR INTR L which is sent to E33 pin 5. The other
input of this gate is high because TX or RX is active. The
output (pin 6) of E33 goes high and is sent to pin 2 of
X-OR gate E32. The other input of this gate is low (via E74
pin 1) because TX or RX is active. This drives the output
(pin 3) of E32 high and the positive transition clocks
CHAR DET HOLD which latches the address of the
detected character in the outputs of CHAR DET HOLD.
The outputs of this register are wire-ORed with signals D6-1
CD 8 H-D6-1 CD 11 H on the M7818 module that
represent character detect flags when only the basic DQ 11
is used (Figure 4-76).

When search is inactive; that is, neither RX or TX is active,
CHAR CNTR can be loaded. This operation is required to
specify the address of the word in the character detect
register or sequence register to be read or written into.
Assume that a control character is to be written into a word
of the character detect register. The following steps are
required.
1.

Address the REG/ERR register (76XXX4) and
set the secondary register pointer (bits 8-11)
to designate the character detect register (lOs).

Access the RX CSR (76XXXO) and write the
address of the selected word into bits 8-11.
The address is represented by signals D9-1 D 8
H-D9-1 D 11 H which are also sent to the
input of CHAR CNTR. When the RX CSR is
addressed, the M7812 module generates D44
LD RX 15 -8 H which is sent to E33 pin 12.
This drives the output (pin 11) of E33 low
which is inverted by E33 pin 3 and sent to the
clock input of CHAR CNTR.

(LSB)

These signals are the address selection bits for the character
detect and sequence registers. Both count enable inputs
(CNT EN and CRY EN) are held permanently high so the
counter is always enabled. A positive-going edge to the CLK
input increments the counter. Placing a low on the load
(LD) input disables the counter and causes the outputs to
agree with the data inputs after the next clock pulse. The
clear (CLR) input is connected to the 0 output of one-shot
E82 which is triggered on the trailing edge of initialize
signal D9-2 INI H. The clear input of the one-shot prevents
triggering of E82 if either RX or TX is active.

4-124

Address selection
signals for both
Character Detect and
Sequence Registers.

, . . - - - - - - - - · - - - - 0 8 - 3 CHAR CNTR 1(1) H
, . . - - - - - - - . - - - - 08-3 CHAR CNTR 2(1) H
, . . - - - - - - - - - 08-3 CHAR CNTR 4(1) H
, . . - - - - - - - - 08-3 CHAR CNTR B(I) H

09-2 INI H
+3V

74123
EB2

09-1011 H-

09-1 010 H09-109H-

5
09-108 H0

6
5
4
3
1

""Lr

MSB
74161
E40
CHAR CNTR
LSB
CLR

MSB 11

11
5

9
2

12
LO

CLK
LSB

Provides clock signol
to lood CHAR CNTR
only when RX and TX
are both inactive

CNT EN

CRY EN

74175
E39
CHAR OET
HOLD
R3(O 15
14
R3(O)
13
03
RO(1) 2
4
3
DO
RO(O)
5
7
01
R1(O
12
6
02
Rl(O)
10
R2(O
11
R2(O)
CLR

06-1 CD 10 H

06-1C09H

06-1C08H

CLK
9

+3V

06-1 CD 11 H

Represent. address
of detected word in
Character Detect
Register if Sequence
Register bit 12 or 13
is set.

3
08-41-CHAR

08-6 BRX ACTIVE H

OB-5 BTX ACTIVE H

from 1 output of
INCR one-shot
11-2597

Figure 4-75 Clocking and Loading Logic for the
Character Counter and Holding Register

+5V

74175
E18

+5V

R3( 1) 15
13 03

R3(0Jt--'4_ _~~

8881

M7818 Module

M7817 Module

Ground provided
only when M7817
is installed.
This disables
8881 driver and
allows E39 to
assert its outputs.

-----.,2

74175
E39
CHAR OET
HOLD

Represents bit 8
of the RX CSR. In
basic OQ 11, It is a
character flag.
With protocol option
installed, it is LSB of
address of detected
character I
a so.
06-1 CO 8 H

R2(Oj-1_0_ _ _---'

~ 02 R2(0)~

11-2593

Figure 4-76 One Bit of the Character Detect
Flags/CD Address

The load (ill) input of CHAR CNTR is low
because RX and TX are both inactive. When
CHAR CNTR is clocked, it is loaded with the
address of the word in the character detect
register into which the control character is to
be written. This address appears at the output
of CHAR CNTR as D8-3 CHAR CNTR 8 (1) H,
4 (1) H, 2 (1) H, and 1 (1) H which are sent to
the address selection inputs of the character
detect register.
With the secondary register pointer bits set for
the character detect register (10s), address
76XXX6 is asserted to gain access to the
character detect register. This results in the
assertion of D9-6 LD CHAR DET L (via some
decoding logic on M7813 print D54). This
Signal is inverted by E43 piI1 2 and is sent to
E60 pin 1. The other input (pin 2) of this gate
is high because RX and TX are inactive. This
drives the output (pin 3) of E60 low which
asserts D8-3 CM WE L. This signal is sent to the
write (WR) input of the character detect
memory. When it is low, a write operation is
performed; therefore, the control word is
written into the selected address of the character detect register.

A similar procedure is used to write into the sequence
memory using its octal deSignation (14s) and write signal
D8-3 SEQ WE L. The octal designation is determined by
the secondary register pointer (bits 8-11) in the REG/ERR
register.

4.7.5 Sequence Decoding Logic
4.7 .s.1 Functional Description - Primarily, the sequence
decoding logic examines the outputs of the sequence
register to generate control signals that are used to
implement hardware operations. The basic enabling signals
are the RX and TX strobe signals. All but three bits (9, 14
and 15) of the sequence register are decoded in this logic.
Bit 9 is used in the character detect control logic (D8-3)
and bits 14 and 15 are used in the TX/RX compare logic
(D8-2).
4.7.5.2 Detailed Logic Description - The circuit schematic for the sequence decoding logic is contained in
drawing D-CS-M7817-O-1 (Rev C) sheet 6, which is
designated D84.
In most cases, the decoding is done simply by ANDing a
signal from the sequence register with the appropriate
stro be signal.

4-126

For example, bit 3 of the sequence register is used to clear
and start the Bee logic during receive or transmit operations. Signal 08-1 SEQ 3 H from the sequence register is
sent as one input to three 2-input NANO gates. This signal
is high when the bit is set which means that the Bee
generator is to be cleared and started. The other input of
each gate is connected to the appropriate strobe signal. If
bit 3 is set and a match is detected, the resulting strobe
pulse enables the gate and generates the hardware control
signal.
Specifically, 084 RX Bee ON L is generated at E54 pin 8
when 08-3 RX SEQ STROBE H is asserted; 084 TX Bee
ON L is generated at E54 pin 6 when 08-3 TX SEQ
STROBE A H is asserted, and 08-4 TX Bee ON NEXT
FRAME L is generated at E54 pin 3 when 08-3 TX SEQ
STROBE B H is asserted.
Most of the decoding is as simple as the example described
above. The resulting control signals are appropriately
named; however, reference to the sequence register bit
assignments in Chapter 3 provides more in forma tion concerning the control functions.

Two sections of this logic require additional discussion
which followsSelection of Number of BCC Characters
Sequence register bits 4 and 5 determine the number of
Bee characters to be tested (receive mode) or appended
(transmit mode) following the control character. This logic
and Bee selection table are shown in Figure 4-77. Signals
084 RX Bee 5 L (E44 pin 10) and 084 RX Bee 4 L
(E44 pin 1) are generated as a function of the state of 08-1
SEQ 5 Hand 08-1 SEQ 4 H, respectively, plus the assertion
of 08-3 RX SEQ STROBE H. These signals (084 RX Bee
5 Land 4 L) are sent to the RX Bee control logic (09-6) in
the M7816 module. The associated signals for the TX mode
(084 TX Bee 5 Land 084 TX Bee 4 L) require more
complex decoding because two TX strobe signals are used.
Signal 08-3 TX SEQ STROBE A H is asserted if the
hardware operation is to be performed on the current
character. Signal 08-3 TX SEQ STROBE B H is asserted if
the hardware operation is to be performed on the next
character. The decoding is accomplished by using two 7450
2-wide 2-input ANO-OR-INVERT gates (E45). The
decoded outputs (084 TX Bee 5 Land 084 TX Bee 4 L)
are sent to the TX Bee con trol logic (09-5) in the M7816
module.

08-1 SEQ 5 H ----.----.--1
6

08-4 TX BCC5 C

08-3 TX SEQ STROBE A H --~-4-_~

08-3 TX SEQ STROBE B H --~+-~~~

8 08-4 TX acc 4 L

To TX BCC
control logic
in M7816
module

08-4 RX BCC 5 L}

~_ _ _ __

08-1 SEQ 4 H ---4"'-~""'-4-~

8
08-3 RX SEQ STROBE H ----If--_ _ _ _9~

E 44

'---

0 - - - - 08-4 RX BCC 4 L

Seq Reg Bit

Number of BCC
Characters

0
1

None

1
2
3

ro
1

To RX BCC
control logic
in M7816
module

11-2609

Figure 4-77 Logic for Selection of Number of Bee Characters
4-127

Character Detect Interrupt
With the M7817 installed, programmable character detection is used and the hard-wired three-character detection
logic in the M7818 module is disabled. When a control
character is detected and it is desired to set the character
detect flag (RX CSR bit 15), signal D6-1 1 ~ CHAR INTR
L is generated and sent to the preset input of the flip-flop
that represents RX CSR bit 15 on the M7812 module (print
D4-4). As a prerequisite, sequence register bit 12 or 13
must be set; that is, D8-1 SEQ 12 H or D8-1 SEQ 13 H
must be asserted. This is the same signal that is generated as
the result of a match when the hard-wired character detect
logic is used (M7818 in and M7817 out). To accommodate
this situation, a wired-OR connection is used for this signal
(Figure 4-78).

If the program has set the character interrupt enable bit
(RX CSR bit 4), an interrupt is generated as a result of
setting the character detect flag (RX CSR bit 15).

4.7.6 Transmitter Protocol Control Logic
4.7.6.1 Functional Description - A simplified block diagram of the transmitter protocol control logic is shown in
Figure 4-79. The logic performs several functions that can
be discussed separately. The major functional areas are
listed below in order of discussion.
DLE Logic
The DLE logic provides a register to store the low byte
output of the character detect memory when the memory
being loaded and the corresponding word in the sequence
register has bit 9 set. Bit 9 is the RX/TX DLE STRIP/ADD
function and when it is set the control word being loaded in
the associated word of the character detect memory
represents a DLE character. This stored DLE is used when a
DLE is to be transmitted. It is also compared with the
received character for fast detection to ensure DLE deletion
from the RX BCC accumulation during transparent text
operation.

Used as clocking
signal for CHAR
OET HOLD register
to latch address of
detected character

08-1 SEQ 12 H
08-1 SEQ 13 H
Sets character flag
bit (15) in RX CSR.
If character interrupt
enable bit (RX CSR 4)
is set t an interrupt is
generated.

08-3 RX SEQ STROBE H

+3V

M7817 module
M7818 module

+5V
.J"'l.. from

06-1 1-+ CHAR INTR L

1-shot E4

Ground provided
only when M7817
is installed. This
disables driver E15
and allows 1-shat
E66 to assert its
output.
11-2610

Figure 4-78 Character Detect Interrupt Logic

4-128

CM 7HCMO H

CLR

SEQ 9 HOLD (1) H
COMPARATOR t - - - - - - - - - - I

OUTPUT
GATING

RX OLE DET L

RX TRANS (1) H

CLK

INI L
TX BCC
EXCLUDE (7-0) L
TX BCC
EXCLUDE (15-S) L
TX C L

RD 15HRD SH

SEQ WE L
09 H

DL E EN (1) L - - r - - - - - - ,

TX BCC
EXCLUDE
LOGIC

INH SH TX BCC L

TX ACTIVE H

STB
TX OLE
MUX
SYNC/DATA EN L
SEND PAD L

TX BIT CNTR 4 (1) H - -.....

PAD
LOGIC

PAD RQ L

TX BIT CNTR 2 (1) H---~
TX BIT CNTR 1 (t)H--------'

BCC EN (1) L

l-TX TRANS
NEXT FRAME L
1-TX TRANS L
TX C H
TX EXIT PULSE H

TX
TRANSPARENCY
CONTROL
LOGIC

TX BCC ON
NEXT FRAME L
TX TRANS (0 L

TX BCC ON L

TX BCC
CONTROL

TX BCC CONT L

LOG!C

TXCL~

LDTX SH REG H-t..._ _ _ _ _~

TX ACTIVE H--1..._ _ _ _

TX BCC SH EN L

~
11-2796

Figure 4-79 Block Diagram of Transmitter Protocol Control Logic

BCC EXCLUDE Logic
This logic allows exclusion of a received character or a
character to be transmitted from the BCC accumulation
when not in the transparent text mode. This function is
controlled by bit 11 (RX/TX BCC EXCLUDE) of the
sequence register. Exclusion can be on the next character to
be transmitted or on the one following.
PAD Logic
This logic allows insertion of a PAD character following the
last character to be transmitted. A jumper allows selection
of one or two PAD characters.
TX Transparency Control Logic
This logic allows entry into transparent text on the next
character to be transmitted or on the one following. It is
tied into the DLE add logic to allow transmission of a DLE
character before exiting transparency.

TX BCC Control Logic
Because of protocol rules, this logic excludes the first TX
BCC start-up control character from the TX BCC accumulation. The next TX BCC start-up control character within
this message is included in the BCC accumulation. It can be
omitted only by using the BCC exclude logic.
4.7.6.2 Detailed Logic Description - The circuit schematic for the transmitter protocol control logic is contained
in drawing D-CS-M7817.Q-l (Rev C) sheet 7, which is
designated D8-S.
DLE Logic
Adding a DLE character to the message being transmitted is
a function provided by the TX protocol control logic. In
order to perform this function, the hardware must be able
to recognize a DLE. The control word representing a DLE
is located only in the character detect memory and cannot

4-129

be retrieved for use by this logic. It is obtained by latching
the low byte output of the character detect memory in a
register (E35 and E37) when this memory is loaded and the
corresponding word in the sequence memory has bit 9 set.
This bit (RX/TX DLE STRIP/ADD) is used to strip (receive
mode) or add (transmit mode) a DLE character. Both the
character detect and sequence memories use common
address lines, so when bit 9 is set in a particular word in the
sequence memory, the control word representing a DLE
character is being loaded into the associated word of the
character detect memory.

EN (1) L. This signal returns to the M7817 module as the
enabling signal for the TX DLE 7-0 multiplexer (E36 pin
7). The select Signals for TX DLE 7-0 are D5-6 TX BIT
eNTR 1 (1) H, 2 (1) H, and 4 (1) H which are the three
least Significant bits of the TX bit counter. The counter
ripples through the selected count (0 to 7 maximum) to
select each input, in ascending order, which performs a
parallel-to-serial conversion of data from input to output.
The serialized DLE character is sent to E44 and emerges as
D9-4 AB TX DATA L. This signal is sent to the M7812'
module (print D4-7) and then out as serial data.

Specifically, when sequence register bit 9 (via the bus
receiver on the M7816 module) is set, D9-1 D9 H is asserted
and sent to the D input of the SEQ 9 HOLD tlip-flop
(Figure 4-79). When the character detect register is loaded
(written into), D8-3 SEQ WE L goes low and is inverted by
E80. The positive-going transition at the output (pin 12) of
E80 clocks SEQ 9 HOLD and sets it. The 0 output of this
flip-flop is fed back to its preset input (pin 10) to latch the
flip-flop in this set state.

When operating in the receive transparent text mode, a
stripped DLE character is not only prevented from being
transferred to the PDP-II memory but it is excluded from
the Bee accumulation. Fast recognition of the DLE is
required to ensure that the Bee generator is turned off in
time to exclude the DLE from the Bee accumulation. In
this case, recognition by the character detect memory is not
fast enough so the DLE stored in E35 and E37 is compared
directly with the high byte of the RX buffer register (D4-5
RD 9 H-D4-5 RD 15 H) using 8242 digital comparators.
When a match occurs (DLE detected), the wired-OR output
of the eight 8242s goes high and is sent to pin 2 of 3-input
NAND gate E86. Pin 1 of E86 is high because SEQ 9 HOLD
is set. The third input (pin 13) is high because the DQll is
in transparent text mode and D8-6 RX TRANS (1) H is
asserted. With all inputs high, D8-5 RX DLE DET L is
asserted at the output (pin 12) of E86. This signal is sent to
the RX protocol control logic (print D8-6) to shut off the
RX Bee generator.

The inversion of D8-3 SEQ WE L is ANDed with D9-1 D9
H at AND gate E88. The output (pin 8) of E88 goes high
and clocks 74175 flip-flops E35 and E37 (DLE 7-1 and
DLE 3-0) which stores the contents of the low byte of the
character detect register (D8-1 eM 0 H-D8-1 eM 8 H). The
8-bit register composed of DLE 7-4 and DLE 3-0 now
contains the control word that represents the DLE character.
If a DLE is to be added to the transmitted message, the
character detect control logic (print D8-3) asserts D8-3
DLE ADD (7-0) L or D8-3 DLE ADD (15-8) L which
control the location of the DLE (after the low byte or after
the high byte). Assume that D8-3 DLE ADD (7-0) L is
asserted. This signal is sent to E77 pin 2 which is a negative
AND gate that serves as a non-inverting buffer. Its other
input is high so the output (pin 3) goes low and directly
sets the DLE NEXT FRAME flip-flop which asserts the
DLE request signal D8-5 DLE RQ L. If D8-3 DLE ADD
(15-8) L is asserted instead of D8-3 DLE ADD (7-0) L, the
TX DLE flip-flop is directly set and DLE NEXT FRAME
remains cleared. When the TX bit counter overflows (end of
character), its overflow pulse generates D9-5 TX eL via the
M7813 and M7816 modules. When this pulse times out, its
positive-going trailing edge clocks DLE NEXT FRAME
which sets it and asserts D8-5 DLE RQ L.
Signal D8-5 DLE RQ L is sent to the TX control logic
(print D5-6) on the M7813 module to generate D5-6 DLE

Bee EXCLUDE Logic
Bit 11 of the sequence register (RX/TX Bee EXCLUDE)
allows a received character to be excluded from the Bee
accumuiation when not in the transparent text mode. The
baud rate must not exceed 250K when this bit is used.
The logic consists of negative AND gate E88 and flip-flops
TX Bee EX (E71) and TX Bee EX NEXT (E70).
If it is desired to exclude the next character to be
transmitted, the sequence decoding logic asserts D8-4 TX
Bee EXCLUDE (7-0) L. This signal directly sets the TX
Bee EX NEXT flip-flop. The low from the 0 output of this
flip-flop is sent to E88 pin 2. The other input (pin 1) of this
gate is high so it acts as a non-inverting buffer and D8-5
INH SHTX Bee L is asserted at its output. This signal goes
to the TX Bee control logic on the M7816 module (print
D9-5) and inhibits the pulses that clock the TX Bee
generator which shuts it off.

4-130

If it is desired to exclude the character after next, D84 TX
BCC EXCLUDE (15-8) L is asserted. This signal directly
sets the TX BCC EX flip-flop which puts a high on the D
input of TX BCC EX NEXT. When the TX bit counter
overflows (end of character), its overflow pulse generates
D9-5 TX CL via the M78I3 and M7816 modules. When this
pulse times out, its positive-going trailing edge clocks TX
BCC EX NEXT which sets it and asserts D8-5 INH SHTX
BCC L. This pulse also clocks TX BCC EX which clears it
because its D input is permanently connected to ground.
Both flip-flops are cleared whenever TX ACTWE is cleared
(D5-6 TX ACTWE (1) H goes low).

PAD Logic
When nothing else is being transmitted, a PAD character is
sent. A PAD character consists of all Is; that is, the serial
data out line is held in the mark state. Protocol control
logic allows insertion of a PAD character following the last
character to be transmitted. A PAD character is required to
ensure that the BCC register is empty (BCC character is
flushed). During an odd-character count, a PAD is required
to fill the receiver shift register so a word transfer can be
made. A jumper (WI) on the M7817 module allows
seieciion of 1 or 2 PAD characiers. The moduie is shipped
with jumper WI out which selects one PAD. Inserting WI
allows two PAD characters but this configuration is not
supported by the DQll diagnostics.

When the TX bit counter overflows again, PAD I is cleared
and the request signal is removed.
TX Transparency Control Logic
To enter TX transparency text requires a TX doublecharacter match, sequence register bit I set and a TX strobe
pulse. TX strobe A allows entry on the next character while
TX strobe Ballows entry on the character after that.
To exit TX transparent text requires the use of REG/ERR
CSR bit 13 (EXIT T). The circuitry is located on the
M7816 module (print D9-5). However, with TX protocol
control, EXIT T allows transmission of a DLE character
and then permits character recognition to function again.
The TX transparency cOl].trol logic is shown in the right
center section of print D8-5 and in Figure 4-80.
In addition to flip-flops TX TRANS NEXT (E61) and TX
TRANS (E60), flip-flop EXIT ONLY (E26) and one-shot
E66 are part of this logic.

As an example, assume that it is desired to enter the IX
transparent text mode during the next character.

Assume that jumper WI is out and it is desired to send a
PAD character. The PAD 2 and PAD I flip-flops start
cleared. PAD I is not involved in this case. When it is
desired to send the PAD character, the sequence decoding
logic asserts D8-5 SEND PAD L. This Signal directly sets
PAD I and asserts D8-5 PAD RQ L. This request signal is
sent to the TX control logic on the M7813 module (print
D5-6) and allows transmission of a PAD character. When
the TX bit counter overflows, pulse D9-5 TX CH is
generated which clocks PAD I and clears it because its D
input is low via the I output of PAD 2. When PAD I is
cleared, D8-5 PAD RQ L goes high which removes the
request for a PAD character.
If two PAD characters are desired, jumper WI must be
installed. When D84 SEND PAD L is asserted, both PAD I
and PAD 2 are directly set. Request signal D8-5 PAD RQ L
is asserted and the first PAD character is initiated. When the
TX bit counter overflows, PAD I and PAD 2 are clocked.
PAD I does not change state and the request signal remains
asserted so the second PAD character is initiated; however,
PAD 2 is cleared and puts a low on the D input of PAD 1.

4-131

At the start, flip-flops TX TRANS NEXT, TX
TRANS, and EXIT DLY and one-shot E66 are
cleared.

The sequence decoding logic asserts. D84
1-+ TX TRANS L which is sent to the E77 pin
5. The other input (pin 4) of this gate is high so
its output (pin 6) goes low and directly sets TX
TRANS.

Setting TX TRANS asserts D8-5 TX TRANS
(1) L which is sent to the strobe logic (print
D8-3). This signal inhibits the character detect
logic but serves as a qualifying input to the
DLE add logic.

D5-6 LD TX SH REG H is generated each time
the TX shift register is to be loaded. This signal
is the clock signal for EXIT DLY and the
trigger for one-shot E66. While in transparency,
EXIT DLY does not change state because D9-5
TX EXIT PULSE H is low and is sent to its D
input. EXIT DLY remains cleared and the low
from its I output inhibits triggering of one-shot
E66 by the negative transitions of D9-5 TX
EXIT PULSE H.

9
10

To OLE ADD 100ic. When comino
out of transparency. this sional
allows a OLE to be transmitted.

5
1 12
E66
74123

o 12

11
08-4 1.... TX TRANS NEXT
FRAME L

5
09 - 5 TX C H --+--f-_ _---I'--_-+-_ _----I

~-+-----T---+---+-- 08 - 5

4
09-5 TX EXIT PULSE H

05-6 LO TX SH REG H

°E69 1 6
7474
TX
5
12
3 TRANS 6
~-------IC
0

+ 3V

°E261 6
7474
EXIT
5
3 COLYO 6

05-6 TX
ACTIVE (1) H

11-2794

Figure 4-80 TX Transparency Control Logic

When coming out of transparency (controlled
by M7816 module), D9-5 TX EXIT PULSE H
goes high. The next TX load pulse (D5-6 LD
TX SH REG H) clocks EXIT DLY and sets it.
The I output of EXIT DLY puts a high on pin
10 of one-shot E66. This same TX load pulse
drives D9-5 TX EXIT PULSE H low via the
M7816 TX Bee control logic.

The next TX load pulse (D5-6 LD TX SH REG
H) triggers one-shot E66 which directly sets
DLE NEXT FRAME to assert D8-5 DLE RQ L
and allows a DLE character to be transmitted.
This load pulse also clocks EXIT DLY and
clears it. The negative-going transition at the I
output of EXIT D LY clocks TX TRANS which
clears it. This drives D8-5 TX TRANS (I) L
high which enables character recognition again.

TX BCC Control Logic
Under protocol control, the first TX Bee start-up control
character is excluded from the TX Bee accumulation. On a
message basis, the first Bee occurrence is the one immediately follOWing Initialize, Master Clear, or the enabling of
TX GO. Within the same message, if the TX Bee generator
is stopped and restarted then the start-up control character
is included in the Bee accumulation.
The first TX Bee start-up control character can be included
in the TX Bee accumulation if jumper W2 is installed on
the M7817 module. This mode of operation is not
supported by diagnostics.
The TX Bee control logic is shown in the lower right
section of print D8-5.

4-132

As an example, assume that the first TX Bee start-up
character desires to turn on the TX Bee generator.
1.

At the start, the following flip-flops are
cleared: TX Bee, TX Bee NEXT, TX Bee
CaNT, TX Bee ON, and Bee SH ON.

With sequence register bit 3 set (eLEAR/
ST ART RX/TX Bee) and a control word
match detected (TX strobe A generated), the
sequence decoding logic asserts DB4 TX Bee
ONL.

DB4 TX Bee ON L directly sets TX Bee
NEXT. The high from the 1 output of this
flip-flop goes to pins 1 and 2 of 3-input AND
gate E2B. The other input (pin 13) is also high
because D9-S TX e L is not asserted (no
overflow pulse from the TX bit counter). The
output of E2B is driven high, inverted by E2
and directly sets TX Bee ON.

The high from the 1 output of TX Bee puts a
high on the D input of Bee SH ON and also
goes to E85 piIl 9. The other two inputs (pins
10 and 11) of this NAND gate are low because
BCC SH ON is cleared. At this point, the
protocol logic has tried to turn on the TX BeC
generator but it has been delayed one character
time.

When the current character has been serialized,
the TX bit counter overflows and generates a
positive carry out (CO) pulse. This pulse is
inverted once on the M7B13 module and twice
on the M7816 module to become D9-5 TX C L
on this module.

The trailing edge of D9-5 TX e L clocks Bee
SH ON which sets it. This drives EB5 pins 10
and 11 high (pin 9 is already high) and asserts
DB-5 TX Bee SH EN L. This is a qualifying
signal for the TX Bee control logic on the
M7816 module (print D9-5). The low from the
o output of Bee SH ON is double inverted by
E55 and E60 and is fed back to its own preset
input (pin 10) which holds it in the set state.
This state can be overridden only by a low to
the direct clear input (pin 13) when TX
ACTIVE is cleared (message completed).

4-133

SUMMARY OF OPERATION
At this point, the TX Bee generator is running
and the Bee character for the particular block
of data within the message is being
accumulated.
Assume now that it is desired to end the current data block,
transmit the required number of Bee characters and restart
the Bee generator immediately to accumulate the Bee for
the next data block. An Intermediate Block Check Character (ITB) appears right after the current data block. It
must tell the logic to append the correct number of Bees
(SEQ bits 4 and 5) and clear and restart the Bee generator
(SEQ bit 3). The word in the SEQ register corresponding to
the ITB in the CHAR DET register must have SEQ bits 3,4
and 5 set to perform these functions. The Bee character(s)
follows the ITB and then the next data block starts. In the
logic, the assertion of DB4 TX Bee ON L allows the Bee
generator to restart without another control character.
7.

The program sets sequence register bits 3,4 and
S to select the required number of Bee
characters to append (transmit) then clear and
restart the Bee generator. When a control word
match is dt:tected (TX strube enabled), the
sequence decoding logic asserts D84 TX Bee
ONL.

D84 TX Bee ON L directly sets TX Bee
CaNT and its 1 output puts a high on the D
input ofTX Bee ON.

The TX Bee control logic on the M7816
module (print D9-S) stops the Bee generator
and automatically appends the required number
of Bee characters. When the last Bee has been
appended, DS-6 Bee EN (1) L goes high and
clocks TX Bee CaNT which clears it and puts
a low on the D input of TX Bee ON. This
flip-flop (TX Bee ON) is clocked simultaneously with TX Bee CaNT, but at that time
its D input is low so it does not change state.
D8-5 TX Bee SH EN L stays asserted so the
TX Bee generator is still running.

SUMMARY OF OPERATION
The current block of data ends and the selected
number of Bee characters have been transmitted. The hardware restarts the Bee generator and it accumulates the Bee for the next
block ofdata.

As previously mentioned, if jumper W2 is installed, the first
TX Bee start-up control character can be included in the
TX Bee accumulation. The jumper completes the circuit
between the 0 output of TX Bee ON and pin 5 of E55.
When TX Bee ON is directly set, the low from its 0 output
is double inverted by E55 and E60 and directly sets Bee
SH ON. This enables D8-5 TX Bee SH EN L without the
character time delay.

Character Strip Logic
This logic prevents the detected character from being
transferred to the PDP-II memory but allows it to be
included in the RX Bee accumulation.
RX BCC Disabling Logic
The RX Bee generator can be stopped by this logic to
exclude a detected character from the Bee accumulation.
The categories of characters to be excluded are listed
below.

4.7.7 Receiver Protocol Control Logic
4.7.7.1 Functional Description - A simplified block diagram of the receiver protocol control logic is shown in
Figure 4-81. The logic performs several functions that can
be discussed separately. The major functional areas are
listed below in order of discussion.

RX BCC Control Logic
This logic functions similarly to the TX Bee control logic
in that it excludes the first RX Bee start-up control
character from the RX Bee accumulation. The next RX
Bee start-up control character within this message is
included in the Bee accumulation. It can be omitted only
by using the Bee exclude logic.

All DLE characters during transparent text
mode.

A SYNC character following a DLE character.

SYNC characters
operation.

Any detected character, if sequence register bit
11 (RX Bee EXCLUDE) is set.

RX OLE DET L

RX GOIDONE L
END NPR CYC LE L

RX BCC ON L

RX BCC
CONTROL
LOGIC

NOT RESTART L

RX CYCLE H

CLEAR GOI
SET DONE
LOGIC

0 - RX GOIDONE L

B RX ACTIVE H

RX ACTIVE (I) H

BCC ON SYNC (I) L

RX BCC CYCLE L

,..----RX TRANS (1) L
RX BCC EX (0) H

1-RX TRANS L
O-RX TRANS L

DES RX BCC SH L

RX BCC EXCLUDE L

STRIP SYNC 0) H

RX TRANS (1) L

B RX C H

SYNC DET H

SKP FRAME L

CHAR STRIP L
OLE STRIP L
RX CLK H
11-2800

Figure 4-81

text

Clear GO/Set DONE Logic
This logic. allows RX GO to be cleared and RX DONE to be
set at the end of an NPR transfer only. The circuit is
independent of the clearing of RX ACTIVE.

RX SEARCH DONE L

RX BCC CONT L

in non-transparent

Block Diagram of Receiver Protocol Control Logic

4-134

4.7.7.2 Detailed Description

Assume that it is desired to end this block of data, receive
the required number of Bee characters and restart the RX
Bee generator immediately.

RX BCC Control Logic
The RX Bee control logic is located in the upper left
portion of print D8-6. In general, it operates similarly to
the TX BeC control logic in that it excludes the first Bee
start-up control character from the RX Bee accumulation
but includes subsequent RX Bee start-up control characters within a message.

As an example, assume that the first RX Bee start-up
control character occurs and the data block within the
message ends with a Bee character.
1.

The program sets sequence register bits 4 and 5
which allows the M7816 RX Bee control logic
to test the selected number of Bee characters.
Sequence register bit 3 is also set to allow
restarting of the RX Bee logic. Actually, the
RX Bee generator does not turn off. This set
of conditions prevents the RX Bee control
logic on the M7817 module from clearing the
RX Bee generator.

When the control character defined in step 5
arrives, D8-4 RX Bee eONT L is asserted. This
signal directly sets Bee eONT and puts a high
on the D input of Bee RESTART.

When the selected number of Bee characters is
tested, the M7816 logic drives 09-6 RX Bee
eyeLE L high. This signal clocks Bee eONT
and Bee RESTART simultaneously. Bee
RESTART does not change state. Bee eONT is
cleared which puts a low on the D input of Bee
RESTART. Signal D8-6 NOT RESTART L
remains high so the RX Bee generator is not
cleared. Instead, it keeps running and the
restart control character is included in the Bee
accumulation.

At the start, the following flip-flops are
cleared: Bee eo NT , Bee RESTART, and
Bee ON SYNe.

When the RX Bee start-up control character is
detected, D8-4 RX Bee ON L is asserted. It
directly sets Bee RESTART and puts a high on
the D input of Bee ON SYNe.

The next positive transition of the receiver
clock (D4-3 RX eLOeK H) clocks Bee ON
SYNe and sets it. The low from its 0 output is
D8-6 Bee ON SYNe (1) L which is fed back to
the preset input (pin 10) of Bee ON SYNe to
hold it in the set state until it is directly cleared
at the end of the message (RX AeTIVE
cleared).

SUMMARY OF OPERA TION
The first RX Bee start-up control character is
excluded from the Bee accumulation but the
first block data is included. The required
number of Bee characters are tested. The RX
Bee generator keeps running so that the next
control character that requested immediate RX
Bee start-up is included in the Bee accumulation for the second block. The data in the
second block is being run through the RX BCC
generator.

Signal D8-6 Bee ON SYNe (1) L is sent to the
RX Bee control logic on the M7816 module
(print D9-6). This Signal is required to turn on
the RX Bee generator. The RX Bee generator
stays on as long as D8-6 Bee ON SYNe (1) L
remains low. A one character time delay is built
into the M7816 RX Bee turn-on logic.
SUMMARY OF OPERATION
The first RX Bee start-up control character
requests that the RX Bee generator be started.
The RX Bee start-up logic on the M7816
module starts the RX Bee generator after a one
character time delay. This excludes the start-up
control character from the RX Bee accumulation. The data in this block is being run
through the RX Bee generator.

4-135

Assume now that it is desired to end the second block of
data, receive the required number of Bee characters and
not restart the RX Bee generator.
8.

The program sets sequence register bits 4 and 5
which allows the M7816 RX Bee control logic
to test the selected number of Bee characters.
Bit 3 of the sequence register is cleared because
it is not desired to restart the RX Bee
generator.

Character Strip Logic
The character strip logic is located in the right center
portion of print D8-6. It is also shown in Figure 4-82.

As in step 6, when the control character arrives,
the M7816 RX BCC control logic tests the
selected number of BCC characters and then
drives D9-6 RX BCC CYCLE L high. Because
sequence register bit 3 is cleared, D8-4 RX BCC
CONT L is not asserted. BCC CaNT remains
cleared and when D9-6 RX BCC CYCLE L goes
high, BCC RESTART is cleared. This puts a
high on pin 10 of 3-input NAND gate E86. Pin
9 is high because BCC ON SYNC is set. After
every character detect search operation, D8-3
RX DONE (SEARCH) H is asserted and via
E88, it drives pin 11 of E86 high. The output
of E86 goes low which asserts D8-6 NOT
REST ART L. This signal directly clears the
BCC generator. The RX BCC generator is
allowed to run and if the accumulation is not
wanted the RX BCC generator is cleared. This is
accomplished on a character basis. This method
is used because in the receive mode only one
character time is available to react to BCC turn
on/off.

Normally, an RX character strip operation prevents the
detected character from being transferred to the PDP-II
memory but allows it to be included in the RX BCC
accumulation.

Sequence register bit 8 (RX CHARACTER STRIP) is used
to control this function. When this bit is set and a control
character match is detected, D8-4 CHAR STRIP L is
asserted as a negative pulse. It directly sets SKP FRAME via
gate E77. The high from the 1 output of SKP FRAME goes
to pins I and 13 of AND-OR-invert gate ES8 which asserts
D8-6 SKP FRAME L at the output of ES8. Signal D8-6
SKP FRAME L is ANDed with D8-3 RX DONE in the
character detect control logic (print D8-3) to generate D8-3
RX SEARCH DONE L. This signal goes to the RX
character control logic on the M7813 module (print DS-8).

Low when SEARCH mode
is completed.

4
08-3 RX SEARCH DONE L

L - - - - - - 0 8 - 6 SKP FRAME L
.-------------~------------~----~+_----------------~---------08-3RX

DONE (SEARCH)H

08-6 OLE SAVE (1) L
10

08-2HBMATCHH ~
TEST PULSE H--:2~-'
08-1 SEQ 9H

13
08-6 B RX ACTIVE H

11-2798

Figure 4-82 Character Strip Logic

4-136

It is this logic that actually inhibits the transfer of the
detected character. When the RX bit counter overflows
(end of current character), it generates a positive carry out
pulse which is double buffered and goes to the M7817
module as 09-6 B RX C H. At overflow, this pulse clocks
SKP FRAME which clears it because its 0 input is
permanently connected to ground. The strip logic is back in
its original state and the detected character has been
stripped.

The low output of E78 directly sets SKP
FRAME which asserts 08-6 SKP FRAME L.
This signal also directly sets OLE SAVE and
asserts 08-6 OLE SAVE (1) L.

Signal 08-6 OLE SAVE (1) L drives 08-3 DLE
STRIP H low which inhibits the stripping of the
next character if it is a OLE.

Signal 08-6 SKP FRAME L generates 08-3 RX
SEARCH DONE L when the RX search operation is fmished. Signal 08-3 RX SEARCH·
DONE L goes to the RX character control logic
on the M7813 module (print D5-8) to strip the
current OLE character.

At the end of the RX search operation, D8-3
RX DONE (SEARCH) H is asserted. This signal
clocks OLE SAVE but it does not change state
because its D input is high via E59 pin 13. This
action saves the fact that a DLE has been
detected and puts a high on pin 9 of E58.

When the RX bit counter overflows, D9-6 B RX
C H clocks SKP FRAME and clears it which
drives 08-6 SKP FRAME L high. At this point,
the OLE character has been stripped and the
strip character logic is conditioned to respond
only to a SYNC character.

10.

When the SYNC character arrives, 04-7 RX
SYNC OET H is asserted on the M7812 module
and goes to pin 10 of E58. The other input (pin
9) is already high (step 8); therefore, 08-6 SKP
FRAME L is asserted and the RX character
control logic on the M7813 logic strips the
SYNC character.

11.

At the end of this RX search operation, D8-3
RX DONE (SEARCH) H clocks DLE SAVE
and clears it because its 0 input is low. The
character strip logic and associated OLE SAVE
logic are now back in their original states.

The character strip logic also includes some associated logic
to strip the DLE, SYNC sequence encountered in the
receive transparent text mode. In this case, the OLE is
stripped; and if the next character is SYNC, it is stripped
also.

To clarify this discussion, some logic on print 08-3 is
shown in Figure 4-82.
1.

The SKP FRAME and OLE SAVE flip-flops are
cleared; therefore, D8-6 DLE SAVE (1) L is
high.
08-6 OLE SAVE (1) L goes to E75 pin 2. The
other input (pin 1) of this gate is high also
because the OQ 11 is in the RX search mode
and the M7816 module is not inhibiting character recognition. This drives the output of E75
low and it goes to E74 pin 9. The other input
of this gate is low also because the OQll is in
the transparent text mode (08-5 RX TRANS
(1) L is asserted). This drives the output of E74
high.
The high from E74 goes to pin 1 of 4-input
AND gate E57. This represents one qualifying
input to the gate that asserts D8-3 DLE STRIP
H. The other three inputs are high, providing
the following conditions have been
met: sequence register bit 9 set, RX search
active, transparent text mode active, high byte
match detected and a TEST pulse generated.

RX BCe Disabling Logic

With all inputs high, the output of E57 goes
high and asserts 08-3 DLE STRIP H. This signal
goes to E78 pin 4 (print D8-6) and drives its
output low.

Once started, the RX BCC generator can be stopped by the
RX protocol logic to exclude a detected character from the
BCC accumulation. This logic is located in the right center
position of print D8-6.

4-137

When the character to be excluded is detected, the logic
asserts D8-6 DES RX BCC SH L. This signal goes to the RX
BCC control logic on the M7816 module (print D9-6)
which inhibits the clock for the RX BCC generator. D8-6
DES RX BCC SH L is the inverted output of E76 and can
be generated by anyone of four inputs to this gate. The
conditions that cause a detected character to be excluded
from the RX BCC accumulation are discussed below.

In transparent text, all DLE characters are
excluded. When a DLE is detected in the
transparent text mode, D8-5 RX DLE DET Lis
asserted, inverted by E80 and sent to pin 1 of
E87. Pin 2 of this gate is high because RX
TRANS is set in transparent text mode. The
third input (pin 13) of E87 is also high because
BCC DLE SAVE is cleared. The output (pin 12)
of E87 goes low and is double inverted by E76
and E67 to assert D8-6 DES RX BCC SH L.

A SYNC character following a DLE is stripped
also because the DLE, SYN sequence is an idle
condition. As a continuation of condition 1
above, the BCC D LE SAVE flip-flop is clocked
when the RX bit counter overflows (end of
current character). This sets BCC DLE SAVE
and puts a high on pin 9 of E87. If the next
character is a SYNC, pin 10 goes high via E79
pin 3 because a SYNC character is detected and
RX CSR bit 1 (STRIP SYNC) is set. The third
input (pin 11) of E87 is also high because RX
TRANS is set. These conditions drive E87 pin 8
low which asserts DS-6 DES RX BCe SH L.

In non-transparent text or non-total transparency operation, SYNC characters can be
stripped from the BCC. When a SYNC character
is detected (D4-7 RX SYNC DET H asserted)
and RX CSR bit 1 is set (D4-4 STRIP SYNC (1)
H asserted), the high from E79 pin 3 is ANDed
with the fact that the DQ 11 is not in total
transparency (D9-6 RX TOTAL TRANS (1) L
is high) to assert D8-6 DES RX BCC SH L.

Any detected character is excluded from the
RX BCC accumulation if sequence register bit
11 (RX BCC EXCLUDE) is set. Setting this bit
generates D8-4 RX BCC EXCLUDE L which
directly sets the RX BCC EX flip-flop. The low
from the 0 output of this flip-flop asserts D8-6
DES RX BCC SH L.

Clear GO/Set DONE Logic
In the character recognition mode, sequence register bit 6
clears RX ACTIVE and sequence register bit 7 clears RX
GO and sets RX DONE. The logic for clearing RX ACTIVE
is shown in print D8-4. The logic for clearing RX GO and
setting RX DONE is located in the lower left portion of
print D8-6. The output of this logic is D8-6 0 -+ RX
GO/DONE L. It goes to the M7813 module (print D5-4)
and when it is asserted RX GO is cleared and RX DONE is
set. Signal D8-6 0 -+ RX GO/DONE L can be asserted only
when the following conditions exist: the RS flip-flop (two
E48 gates) has been set by D8-4 RX GO/DONE L being
asserted, D5-3 RX CYCLE H is asserted, and D6-2 END
NPR CYCLE (1) L is asserted. Signal D6-2 END NPR
CYCLE (1) L is asserted only at the end of an RX transfer;
therefore, RX GO is cleared only after completion of the
transfer.

4-138

APPENDIX A
INTEGRATED CIRCUIT
DESCRIPTIONS
A.I INTRODUCTION
The MSI integrated circuits (ICs) shown in the engineering
drawings are discussed in the following paragraphs. The
descriptions include one or more of the following
items: pin/signal designations, equivalent logic schematic,
and truth table. This information is intended as a maintenance aid for troubleshooting to the IC level. Table A-I
lists the ICs by manufacturer's part number, name, and
paragraph number.

Table A-I
Integrated Circuits
Manufacturer's
Part Number

A-I

Name

Paragraph

3101

64-Bit Read/Write Memory

A.2

4015

Quad D-Type Flip-Flop

A.3

7442

4- line to 10-line Decoder

A.4

7474/74H74

Dual D-Type EdgeTriggered Flip-Flop

A.5

8838

Quad Bus Transceiver

A.6

74123

Retriggerable Monostable
Multivibrator with Clear

A.7

74153

Dual 4-line to 1-line Data
Selector /Multiplexer

A.8

74157/74S158

Quad 2-line to I-line
Data Selector/Multiplexer

A.9

74161

Synchronous 4-Bit
Counter

A.I0

74174/74175

Hex/Quad OoType
Flip-Flop with Clear

A.ll

74197

Presettable Binary
Coun ter /La tch

A.12

A.2 3101 64-BIT READ/WRITE MEMORY
Function Table
ME

Operation

Condition of Outputs

L
H
L
H

Write
Read
Inhibit Storage
Do Nothing

Complement of Data Inputs
Complement of Selected Word
Complement of Data Inputs

.l.J

L
H
H

High

SELECT INPUTS
B

DATA SENSE DATA SENSE
INPUT OUTPUT INPUT OUTPUT
4
4
3
3

SET 3

ClK

ClR

SET 2

R3 (0

SET 1

SELECT MEM WRITE
INPUT •
I
A
ENABLES

DATA SENSE DATA SENSE GND
INPUT OUTPUT INPUT OUTPUT
1
1
2
2

7 R2 (1)

11--1-+--,
15-t----i--t

~--9

Rl (1)

11- 1117

SE T 0
DO

12 --+-+---,
10 RO (1)

A.3 4015 QUAD D-TYPE FLIP-FLOP
The 4015 contains four flip-flops with single-rail outputs (Q
only). Each flip-flop has its own preset input (SET). All
flip-flops are cleared by a common clear input (RESET).
13
CLOCK

:3
ClR

Truth Table
D
0
0

Qn-l

Q
n

0
1
0

0
0
1

Qn-l = time period prior
to clock pulse
114 OF OEV ICE SHOWN
CLOCK AND RESET COMMON TO All FOUR FLIP- FLOPS

Qn = time period following clock pulse

Vee = PIN 16
GNO = PIN B
"-0739

A-2

A.4 7442 4-LINE TO to-LINE DECODER
In the DQll, the 7442 is used as a 3-wire binary to octal
decoder. Input D is used as a strobe and when it is low, data
is taken from outputs 0-7.

A.S 7474/74874 DUAL D-TYPE EDGE-TRIGGERED
FLIP-FLOPS
The 7474/74H74 D-type flip-flops are triggered by the
positive edge of the clock pulse. They feature direct-clear
and direct-preset inputs and complementary outputs.

OUTPUT 0
INPUT

A
Vee

OUTPUT I

2
CLEAR

2
2
CLOCK PRESET

INPUT B
OUTPUT :3

PRESET

CLEAR

OUTPUT 4

CLOCK

OUTPUT 5
INPUT C

OUTPUT 6

1
CLEAR

OUTPUT 7
INPUT 0

1
CLOCK

1
PRESET

GND

POSITIVE LOGIC: LOW INPUT TO PRESET SETS Q TO LOGICAL 1
LOW INPUT TO CLEAR SETS Q TO LOGICAL 0
PRESET AND CLEAR ARE INDEPENDENT OF CLOCK

01'-----t--t-~F OUTPUT 8

Vee = PIN 16
GND=PIN 8

~OUTPUT 9

11-0766

L...-!:<..L.....--'

11-0734

Truth Table (Each Flip-Flop)

Truth Table

BCD Input
B
C

0
0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1
X

0
0

0
1

1
0

0
1
0
1
0
1
X

1
1
1
1
1

0
1
1
1
1

1
0
0

1
1
X

1
1
1
1
1
1

Octal Output
3
4
5
1
1

1
1

0
1
1
1
1
1

1
0
1
1
1
1

1
1

tn
6

1
1
1
1
1
1
1
0
1

1
1

1
1
0
1
1
1

1
1
1
0
1
1

Input
D

Output

1
0

Notes:

X = Irrelevant

A-3

tn+t

1. tn = bit time before clock
pulse
2. tn+l = bit time after clock
pulse

A.6 8838 QUAD BUS TRANSCEIVER
The 8838 consists of four identical receiver/driver combinations in one package for use on the PDP-II Unibus.
Data from the equipment on DATA IN 1, e.g., appearing on
pin 2 will be driven out of pin 1 (BUS 1) to the Unibus (if
enabled). A BUS 1 signal received from the Unibus on pin 1
will be fed out of pin 3 (DATA OlJT i) to the equipment.

A.7 74123 RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH CLEAR
The 74123 Multivibrator provides dc triggering from gated
low level active (A) and high level active (B) inputs. It also
provides overriding direct clear inputs and complementary
outputs. The retriggering capability simplifies generation of
extremeiy iong duration output puises. If the input is
triggered before the output pulse is terminated, the output
pulse is extended. An overriding clear feature allows any
output pulse to be terminated at a predetermined time,
independent of timing components.

Signal/Pin Designations
Signal Name

Circuit

BUS
DATA IN
DATA OUT

1
2

12
11
10

5
6

ENABLE

A
7

GROUND

BUS 1
DATA IN 1
DATA OUT 1
BUS 2
DATA IN 2
DATA OUT 2
ENABLE A

CLEAR

13
B
9

GROUND

VCC
BUS 4

DATA IN 4

DATA OUT 4
BUS 3

poSitive logic

DATA IN:3

Low input to clear resets 0 to low
level and inhibit' data inputs

DATA OUT:3
ENABLE B

11-1864

TRUTH TABLE

INPUTS OUTPUTS
ABO
Q

DATA OUTI

ENABLE A
ENABLE B - - " " ' l L - ' ONE OF FOUR

11-1860

H
X

X L
L L

~I~

H
H

A.8 74153
DUAL 4-LINE-TO-I-LINE
SELECTOR/MULTIPLEXERS

DATA

STROBE lG (1)
(ENABLE)o-_________________________

-a

ICO (6)

lCl (5)

ADDRESS{

OUTPUTS

2CO (IO)

2Cl (11)
DATA 2
2C2 (12)

2C3 (13)

STROBE 2G (15)
(ENABLE)~~--------------------~~

Vee • PIN 16
GND = PIN 8
LOGIC DIAGRAM

Vee
16
CONTROL INPUT

STROBE

LOW

HIGH

LOW

HIGH

LOW

HIGH

TRUTH TABLE

DATA INPUT

OUTPUT

345

OUTPUT

LOW

DON'T CARE

STROBE
A
2G
SELECT
15
14

LOW

HIGH

LOW

(EACH HALF)

2
STROBE
B
IG
SELECT

''------."r~------..JI

DATA INPUT

OUTPUT GND

IY
8E- 0138

A-5

A.9 74157/74S158
MULTIPLEXER

QUADRUPLE

lB
(3)

2-LINE-TO-I-LINE

(5)

(6)

3A
(11)

3B
(10)

4A
(14)

Pin t6=VCC
Pin S=GND

TRUTH TABLE
lY

INPUTS

745158 DIAGRAM
ENABLE
H
L
L
L
L

SELECT
X
L
L
H
H

OUTPUT Y
A B
X X
L X
H X
X L
X H

74157
L
L
H
L
H

H=High level,L=Low level,X=Irrelevont

74157 LOGIC DIAGRAM
1A

(2)

(3)

(5)

(6)

(11 )

(10)

(14)

(13)

SELECT

ENABLE

(15)

Pin 16 .. VCC ' PinS- GND

11-1131

A-6

74S158
H
H
L
H
L

A.IO 74161 SYNCHRONOUS 4-8fT COUNTER

OUTPUTS

CARRY
VCC OUTPUT

CLEAR CLOCK

,_----A...------. ENABLE
QA

ABC

________~~________- J

LOAD

ENABLE GND

DATA INPUTS
II -2201

14,

11])

Oc
OUTPUTS

INPUTS

1--_____000
1111

ENABLE
T

RIPPLE
CARRY

A-7

A.ll 74174 HEX/74175 QUAD D-TVPE FLIP-FLOPS
WITH CLEAR
The 74174 contains six flip-flops with single-rail outputs (Q
only). The 74175 contains four fl.!£:!1ops with double-rail
outputs (complementary Q and Q). Both devices have
common clock and clear inputs.

TRUTH TABLE
INPUT
tn

OUTPUTS
tn +1

H
L

L
H

tn II Bit time before
clock pulse.
t n +1-Bit time after
clock pulse.

°A

(2) QA

TRUTH TABLE
INPUT
tn

CLOCK
CLEAR

B (4)

OUTPUTS
tn +1

H
L

L
H

tn .. Bit time before
cloc k pulse.
tn+1 a Bit time after
clock pulse.

(5) QB

CLOCK
CLEAR

C (6)

(4)

(7) QC

(10)
DO

(5)

(12)

(14)

ClK QC
CLEAR

(15)
QF

<>(_13..;;.)+---t--I OO

QF
CLOCK

(6)

(10)

CLOCK
CLEAR

CLK OB
CLEAR

(12)

(3)

(7)

CLOCK
CLEAR

E (13)

CLK QA
CLEAR

CLOCK
CLEAR

o (11)

(2)

°A

(11)

(15)

I---~"--+--<JCLK QO (14)
CLEAR

CLEAR
Pin (16)· VCC,Pin (8). GNO

Pin (16)- Vce, Pin (8) -GNO

11- 1112

11-1113

74174 Diagram

74175 Diagram

A-8

A.l2 74197
LATCH

PRESETTABLE

BINARY

COUNTER/

JORN DUAL-IN-LiNE OR
W FLAT PACKAGE
(TOP VIEW)*

DATA INPUTS

Vee

CLEAR

COUNT/
LOAD

CLOCK
t

CLOCK

GND

2
DATA INPUTS

ASYNCRONOUS INPUT: LOW INPUT TO CLEAR SETS QA
QS. QC AND QD LOW.

11-0482

A-9

DATA A 0------------1
COUNT I LOAD o------4~

PRESET
QA

CLOCK1 o---------------~--~--------_4----------~T

CLEAR

DATA S

PRESET
QS

CLOCK 2 o---------------~__I----------~----------nT

CLEAR

DATA C O----------------4---I~

PRESET
Q

CLEAR

DATA 0 0 - - - - - - - - - 4 - - 4 - - - 1

PRESET

CLEAR

11-0481

A-IO

APPENDIX B
PDP-II MEMORY ORGANIZATION
AND ADDRESSING CONVENTIONS

The PDP-II memory is organized in 16-bit words consisting
of two 8-bit bytes. Each byte is addressable and has its own
address location: low bytes are even numbered and high
bytes are odd numbered. Words are addressed at even
numbered locations only and the high (odd) byte of the
word is automatically included to provide a 16-bit word.
Consecutive words are therefore found in even numbered
addresses. A byte operation addresses an odd or even
location to select an 8-bit byte.

The highest 8K address locations (760000-777777) are
reserved for internal general registers and peripheral devices.
There is no phySical memory for these addresses; only the
numbers are reserved. As a result, programmable memory
locations cannot be assigned in this area; therefore, the user
has 248K bytes or I24K words to program.

A PDP-ll processor without the memory management unit
provides 16 address bits that specify 2 16 or 65,536 (64K)
locations (Figure B-2). The maximum memory size is
65,536 (64K) bytes or 32,768 (32K) words. Logic in the
processor forces address bits A(17: 16) to Is if bits
A(15: 13) are all Is when the processor is master to allow
generation of addresses in the reserved area with only 16-bit
control.

The Unibus address word con tains 18 bits identified as
A(17:oo). Eighteen bits provide the capability of addressing
256K memory locations, each of which is an 8-bit byte.
This also represents 128K 16-bit words. In this discussion,
the multiplier K equals 1024 so that 256K represents
262,144 locations and 238K represents 131,072 locations.
This maximum memory size can be used only by a PDP-II
processor with a memory management unit that utilizes all
18 address bits. Without this unit, the processor provides 16
address bits which limits the maximum memory size to 64K
(65,536) bytes or 32K (32,768) words.

Bit 13 becomes a 1 first at octal 160000 which is decimal
57,344 (56K). This is the beginning of the last 8K bytes of
the 64K byte memory. The processor converts locations
160000-177777 to 760000-777777 which relocates these
last 8K bytes (4K words) to the highest locations accessible
by the bus. These are the locations that are reserved for
internal general register and peripheral device addresses;
therefore, the user has 57,344 (56K) bytes or 28,672 (28K)
words to program.

Figure B-1 shows the organization for the maximum
memory size of 256K bytes. In the binary system, 18 bits
can specify 2 18 or 262,144 (256K) locations. The octal
numbering system is used to designate the address. This
provides convenience in converting the address to the
binary system that the processor uses as shown below.

Address Bit

Binary

6
Address Word Format

B-1

Octal

08107
16 BIT DATA WORD

HIGH 8YTE

LOW BYTE

000001

000000

000003

000002

-- ----____ r-

757777

757776

760001

760000

*777777

USER ADDRESS SPACE
AVAILABLE USING 18
ADDRESS BITS ON
PDP-11 PROCESSOR
WiTH MEMORY
MANAGEMENT OPTION.
INCLUDES 248K (253,952)
BYTES OR 124K(126,976)
WORDS.

HiGHEST 8K (8192i
BYTES OR 4K(4096)
WORDS RESERVED FOR
DEVICE REGISTER
ADDRESSES.

777776

LLAST ADDRESS IS BYTE NUMBER 262,143
10
MAXIMUM SIZE WITH 18 ADDRESS BITS IS 256K(262,144) BYTES OR 128K(131,072)WORDS.

11-1690

Figure B-1 Memory Organization for Maximum Size Using 18 Address Bits

HIGH BYTE
000001
000003

LOW BYTE

~----------------+-------------~

_ _ r"

000000
000002

--....

157777

157776

160001

160000

* 177777

USER ADDRESS SPACE
AVAILABLE USING 16
ADDRESS BITS ON
PDP-11 PROCESSOR
WITHOUT MEMORY
MANAGEMENT OPTION.
INCLUDES 56K (57, 344)
BYTES OR 28K (28,672)
WORDS.

ADDRESSES 160000177777 ARE CONVERTED
TO 760000 -777777 BY
THE PROCESSOR. THUS.
THEY BECOME THE
HIGHEST 8K (8192) BYTES
OR 4K(4096) WORDS
RESERVED FOR DEVICE
REGISTER ADDRESSES.

--...

177776

LLAST ADDRESS IS BYTE NUMBER 65,535 10
MAXIMUM SIZE WITH 16 ADDRESS BITS IS 64K (65,536) BYTES OR 32K(32,768) WORDS.

Figure B-2 Memory Organization for Maximum Size Using 16 Address Bits
B-2

11-1689

Memory capacities of 56K bytes (28K words) or under do
not have the problem of interference with the reserved area,
because designations less than 160000 do not have a binary
1 in bit A13. No addresses are converted and there is no
possibility of physical memory locations interfering with
the reserved space.
PDP-ll core memories are available in 4K or 8K increments. The highest location of various size core memories
are shown below.
Memory Size
K-Words
K-Bytes

8
12
16
20
24
28

16
24

Highest Location
(Octal)
017777
037777
057777
077777
117777
137777
157777

32
40
48
56

B-3

I
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I
I
I
I
I
I
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DQII NPR SYNCHRONOUS LINE
INTERFACE MANUAL
EK-DQII-MM-002

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