Digital PDFs

EK-DMR11-UG

December 1980

118 pages

Original

4.3MB

Document:	DMR11 Synchronous Controller Users Guide
Order Number:	EK-DMR11-UG
Revision:	000
Pages:	118
Original Filename:	http://bitsavers.org/pdf/dec/unibus/EK-DMR11-UG-002_DMR11_Synchronous_Controller_Users_Guide_Dec80.pdf

OCR Text

DMR11 synchronous
controller user's guide
EK.. DMR11 .. UG-002

digital equipment corporation • merrimack, new hampshire

1st Edition, May 1980
2nd Edition, December 1980

Copyright © 1980 by Digital Equipment Corporation
The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL 's D ECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC

PDP
DECUS
UNIBUS

DECsystem-lO
DECSYSTEM·20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
lAS

Page
PREFACE
CHAPTER 1

INTRODUCTION

1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.4
1.4.1
1.4.2
1.5

SCOPE ............................................................................................................... 1-1
DMRll GENERAL DESCRIPTION ................................................................ 1-1
DMR II SYSTEM OPERATION ....................................................................... 1-3
Command Structure .................................................................................... 1-4
Input Commands ........................................................................................ 1-4
Output Commands ...................................................................................... 1-4
DMR II Operation Sequencing ................................................................... 1-5
Maintenance Mode Operation ..................................................................... 1-5
GENERAL SPECIFICATIONS ........................................................................ 1-5
Power Requirements ................................................................................... 1-5
Environmental Requirements-All DMRlls ............................................. 1-7
EIA STANDARDS OVERVIEW (RS-449 vs RS-232-C) .................................... 1-7

CHAPTER 2

INSTALLATION

2.1
2.2
2.3
2.4
2.4.1
2.4.1.1
2.4.1.2
2.4.2
2.5
2.5.1
2.5.2
2.5.3
2.6
2.6.1
2.6.2
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.8

SCOPE ............................................................................................................... 2-1
UNPACKING AND INSPECTION .................................................................. 2-1
INSTALLATION CONSIDERATIONS ........................................................... 2-1
PREINSTALLATION CONSIDERATIONS .................................................... 2-1
System and Device Placement ...................................................................... 2-2
System Placement ................................................................................ 2-2
Device Placement ................................................................................ 2-3
System Requirements .................................................................................. 2-3
MICROPROCESSOR INSTALLATION .......................................................... 2-4
Backplane Considerations ........................................................................... 2-4
M8207-RA Considerations .......................................................................... 2-4
M8207-RA Insertion ................................................................................... 2-6
LINE UNIT INSTALLATION .......................................................................... 2-7
M8203 Considerations .............................................................................. 2-17
M8203 Insertion ........................................................................................ 2-23
DMR 11 SYSTEM TESTING ............................................................................ 2-28
Functional Diagnostic Testing ................................................................... 2-29
D ECX II System Exerciser ........................................................................ 2-29
Final Cable Connections ........................................................................... 2-32
DMRll Link Testing ................................................................................ 2-32
DMRII-XX INSTALLATION CHECK-OFF LIST ........................................ 2-37

CHAPTER 3

PROGRAMMING

3.1
3.2
3.2.1
3.2.2

INTRODUCTION ............................................................................................. 3-1
COMMAND STRUCTURE .............................................................................. 3-1
Control and Status Registers ....................................................................... 3-1
Initialization ............................................................................................... 3-4

iii

CONTENTS (CONT)
Page
3.2.3
3.2.3.1
3.2.3.2
3.2.4
3.2.4.1
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
3.4.1
3.4.2
3.4.3
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.4.1
3.5.4.2
3.6
3.7
3.7.1
3.7.1.1
3.7.1.2
3.7.2
3.7.2.1
3.7.2.2
3.7.2.3
3.7.2.4
3.7.2.5
3.7.2.6
3.7.2.7
3.8

Input Commands Overview .......................................................................... 3-6
Input Command Handshaking ............................................................ 3-7
Modem Status Read ............................................................................ 3-8
Output Commands Overview .................................................................... 3-13
Output Command Handshaking ........................................................ 3-14
INPUT COMMANDS ..................................................................................... 3-14
Base In ....................................................................................................... 3-16
Control In .................................................................................................. 3-17
Receive Buffer Address/Character Count In (RBA/CCI) ......................... ,,3-18
Transmit Buffer Address/Character Count In (TBA/CCI) ....................... ,,3-19
Halt Request Command ............................................................................. 3-20
OUTPUT CO~MMANDS ................................................................................. 3-22
Receive Buffer Address/Character Count Out (RBA/CCO) ...................... 3-22
Transmit Buffer Address/Character Count Out (TBA/CCO) .... .-............... 3-23
Control Out .............................................................................................. 3-24
PROGRAMMING TECHNIQUES ................................................................ 3-25
Input Command Sequence ........................................................................ 3-27
Base In Command with Resume Feature ................................................... 3-27
Distinguishing DMR II from DMC II ...................................................... .3-30
DDCMP Maintenance Mode Operation ................................................... 3-30
Data Transfer .................................................................................... 3-30
Unattended System Control .............................................................. 3-30
BASE TABLE COUNTERS ............................................................................. 3-31
MODEM CONTROL ...................................................................................... 3-34
Modem Control Implemented in M8203 .................................................... 3-34
Modem Ready Lockout of RTS ........................................................ 3-34
Half-Duplex Mode ............................................................................ 3-34
Modem Control Implemented in DMR II Microprogram ......................... .3-34
Auto-Answer.....................................................................................3-34
Data Set Ready Glitch ....................................................................... 3-35
R TS - CTS Delay .............................................................................. 3-35
Loss of Carrier Detect ...................................................................... .3-35
Receiver I nactive Check ................................................................... .3-35
Modem Status Read During Input Command ...................................3-35
Data Terminal Ready Control ........................................................... 3-36
DMR II DATA LINK FUNCTIONS ............................................................. .3-36

APPENDIX A

FLOATING DEVICE ADDRESSES AND VECTORS

A.I
A.2
A.3

FLOATING DEVICE ADDRESSES ................................................................ A-I
FLOATING VECTOR ADDRESSES .............................................................. A-2
EXAMPLES OF DEVICE AND VECTOR ADDRESS ASSIGNMENT .......... A-4

APPENDIX B

DDCMP IN A NUTSHELL

B.I
B.I.I
B.1.2
B.I.3

DDCMP ............................................................................................................. B-l
Controlling Data Transfers ......................................................................... B-1
Error Checking and Recovery ..................................................................... B-1
Character Coding ........................................................................................ B-3
iv

CONTENTS (CONT)
Page
B.1.4
B.I.5
B.2
B.3

Data Transparency .................................................................................... B-3
Data Channel Utilization ............................................................................ B-3
PROTOCOL DESCRIPTION ............................................................... :............ B-3
MESSAGE FORMAT ....................................................................................... B-6

APPENDIX C

DIAGNOSTIC SUPERVISOR SUMMARY

C.I
C.2
C.3
C.3.1
C.4
C.4.1
C.4.2
C.5

INTRODUCTION ............................................................................................. C-l
VERSIONS OF THE DIAGNOSTIC SUPERVISOR ........................................ C-l
LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC ...................... C-l
Five Steps to Run a Supervisor Diagnostic .................................................. C-2
SUPERVISOR COMMANDS ........................................................................... C-3
Command Switches ..................................................................................... C-4
Control/Escape Characters Supported ........................................................ C-5
WHAT IS THE SETUP UTILITY? .... , ............................................................... C-5

GLOSSARY

FIGURES
Figure No.
I-I
1-2
1-3
2-1
2-2
2-3
2-4

2-5
2-6

2-7
2-8
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12

Title

Page

Typical PDP-II Applications ............................................................................... 1-2
Typical VAX-I 1/780 Applications ....................................................................... 1-3
DMR 11 Operation Sequencing ............................................................................ 1-6
M8207-RA Microprocessor Switch/Jumper Locations ......................................... 2-5
M8203 Switch/Jumper Locations ....................................................................... 2-21
Microprocessor/Line Unit Installation .............................................................. 2-22
DMRII Cable Drawings .................................................................................... 2-23
DMR 11 Turnaround Test Connectors , ............................................................. 2-28
DMR 11 Remote System Cabling Diagram ......................................................... 2-33
DMCII to DMR 11 Integral (Local) Modem Cabling Diagram .......................... 2-35
DMR 11 to DMR 11 Integral (Local) Modem Cabling Diagram .......................... 2-36
UNIBUS Control and Status Registers Format Overview .................................... 3-4
Programming Example for Input Commands ....................................................... 3-9
Input Command Servicing ................................................................................. 3-10
Modem Status Read Format .............................................................................. 3-11
Summary of Control Out Status ......................................................................... 3-14
Output Command Servicing ............................................................................... 3-15
Base In Command Format ................................................................................. 3-16
Control In Command Format ............................................................................ 3-17

Start/Stack Sequence Timer .............................................................................. 3-19
Receive Buffer Address/Character Count In Command Format ........................ 3-20
Transmit Buffer Address/Character Count In Command Format ...................... 3-21
Halt Request Command Format ........................................................................ 3-22

FIGURES (CONT)
Figure No.
3-13
3-14
3-15
3-16

3-17
3-18
A-I
B-1
B-2
B-3
C-l

Title

Page

Receive Buffer Address/Character Count Out Command Format ...................... 3-23
Transmit Buffer Address/Character Count Out Command Format .................... 3-24
Control Out Command Format ......................................................................... 3-25
D M R 11 Protocol State Diagram ....................................................................... .3-28
Down-Line Load Procedure to Remote Station .................................................. 3-32
DMR 11 Base Table Error Counters ...................... , ............................................ 3-33
UNIBUS Address Map ....................................................................................... A-2~
DDCMP Data Message Format. ......................................................................... B-1
DDCMP Sample Handshaking Procedure .......................................................... B-2
DDCMP Message Format in Detail .................................................................... B-5
XXDP+ /Diagnostic Supervisor Memory Layout on a (Min Memory)
16K w System ...................................................................................................... C-2

TABLES
Table No.
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
3-1
3-2

3-3
3-4
3-5
3-6

3-7
3-8

Title

Page

DMR 11 Options ............................................................................................. "... 1-:~
DMR 11 Performance Parameters ........................................................................ 1-7
DMR II Option Packing List .............................................................................. 2-2
D M R 11 Voltage Chart ........................................................................................ 2-3
M8207-RA DMR 11 Jumper Chart ...................................................................... 2-6
Switch Pack E 127 Selections ................................................................................ 2-8
Switch Pack E28 Selections ................................................................................. 2-9
Switch Selectable Features ................................................................................ 2-10
Normal M8203 Configuration (Bootstrap Not Selected) .................................... 2-11
M8203 Jumper Functions .................................................................................. 2-12
Switch Pack E39 (Z) Selections .......................................................................... 2-13
Switch Pack EI21 (Y) Selections ...................................................................... ,.2-14
Switch Pack E 134 (X) Selections ........................................................................ 2-16
Cable Description ............................................................................................. 2-18
Modem Option Jumper Functions .................................................................... 2-27
SEL 0 Bit Functions ............................................................................................ 3-2
BSEL 2 Bit Functions .......................................................................................... 3-5
Input Commands ................................................................................................ 3~7
Modem Status Bit Descriptions ........................................................................ 3-11l
Data Port Descriptions with Control In ............................................................ 3-18
Data Port Bit Descriptions with Control Out .................................................... 3-26
DMR II Command Sequence ............................................................................ 3-29
Invalid Enter MOP Message Response ............................................................. 3-31

PREFACE

This manual describes in detail the installation requirements and programming considerations for the
DMRll Synchronous Controller. Three appendices are also provided to supplement the above.
Other publications which support the DMR II Synchronous Controller are:

•
•
•
•

M8207 Microprocessor Technical Manual (EK-M8207-TM-OOI)
M8203 Line Unit Technical Manual (EK-M8203-TM-OOI)
DMRll Print Set (MP-00911)
Electronic Industries Association (EIA) Specifications

vii

CHAPTER 1
INTRODUCTION

1.1 SCOPE
This chapter contains a brief introduction to DM R II operation. The term DM R II, as used throughout this manual, denotes the communication subsystem which consists of a microprocessor module
and a line unit module.
1.2 DMR II GENERAL DESCRIPTION
The OM R II is designed to be used in a network link for high performance interconnection of V AX11/780 or PDP-II computers. It is a microprocessor-based, intelligent synchronous communications
controller which employs the DIGITAL Data Communications Message Protocol (DDCM P). The
DM R II is program compatible with DMC II and line compatible with either DMC II or any device
that uses DDCMP version 4.0.
Features of the DM R II include:
•

Extensive error reporting,

•

Down-line and remote load detect to attended or unattended PDP-II processors (requires
bootstrap option),

•

Modem control,

•

A uto-answering capabilities,

•

DMC II program compatibility,

•

Switch selection of DMC II line compatibility mode or DDCM P V4.0 compat'ibility mode,

•

Comprehensive diagnostic tests,

•

Support for local or remote, full-duplex or half-duplex configurations,

•

16-bit non-processor request (NPR), direct memory access (DMA) transfers, and

•

DDCMP implementation which handles message sequencing and error correction by automatic retransmission.

The DMRII basic unit consists of the M8207-RA microprocessor and the M82031ine unit. The microprocessor serves as a parallel data interface between the central processor (VAX-II /780 or PDP-II)
and the M8203 line unit. This line unit/microprocessor combination permits either remote or local
computer applications. (For remote operations, computers are connected through external modems
that use common carrier facilities.) See Figure I-I for PDP-II applications and Figure 1-2 for V AX11/780 applications.

1-1

BC55B-10
BC55C-10
COMMUNI- BC05Z-25
CATIONS
LINE
UNIT
SYNCHRO(M8203)
NOUS
SERIAL
DATA
(REMOTE)

BC08S-1
MICROPROCESSOR
(M8207-RA)
8-BIT
DATA
(BIDIRECTIONAL)

SYNCHRONOUS
SERIAL DATA

TO REMOTE STATION
VIA TELEPHONE LINES

(LOCAL)

MICROPROCESSOR
(M8207-RA)
BC08S-1

COMMUNICATIONS
LINE
UNIT
(M8203)

BC55A-10
INTEGRAL
MODEM

SYNCHRONOUS
SERIAL DATA
TO LOCAL STATION
VIA TWINAX OR
TRIAXIAL CABLES

PDP11

MEM

MK-2241

Figure 1-1

Typical PDP-II Applications

The DM R II system consists of a basic subsystem and four options which allow it to accommodate
standard and special interface configurations. With these options, DM R II systems can operate with
speeds ranging from 2.4K bits per second (b/s) to 1M bls (see Table I-I).
Table I-I
Option

DMRII Options
Line Speed

Interface

DMRII-AA

EIA RS-232-C*
EIA RS-423-A/
CCITT V.IO

Up to 19.2K bls
Up to 56K b/s:l:

DMRII-AB

ISO 2593/CCITT V.35 t

Up to 1M bls

DMRII-AC

Integral Modem

56K, 250K, SOOK. I M his

DMRII-AE

EIA RS-422-A/
CCITT V.ll

Up to 1M b/s

* EI A - Electronic I ndustries Association
tlSO - International Standards Organization
CCITT - Comite Consultatif Internationale de Telegraphic et Telephone
:I: Limited to 20K b/s by RS-449 and 9600 b/s by ISO 4902
1-2

SYNCHRONOUS
SERIAL DATA
TO LOCAL
STATION VIA
TWINAX OR
TRIAXAL CABLE
MK-2240

Figure 1-2

Typical VAX-II 1780 Applications

The basic subsystem is designated DMRII-AD and consists of an M8203 line unit, an M8207-RA
microprocessor, a BC08S-1 interconnect cable, an H3254 interface module test connector, and an
H3255 interface module test connector. The M8203 line unit has an Integral Modem which is switch
selectable to operate at speeds of 56K, 250K, 500K, and 1M b/s.
F or local operations through Integral Modems, systems are interconnected by twin ax or triaxial cables in
either half-duplex (one cable) or full-duplex (two cables) configurations. The DMRII-AC option is used
for local operations. A maximum distance of 6 km (18K feet) at 56K bls can be obtained using
recommended cables. For information on recommended cables, data ratesl distance, and fabrication
techniques for twinaxltriaxial cables, refer to the M8203 Line Unit Technical Manual,
EK-M8203-TM-001, Appendix B. For specific information on the installation of the DMRll basic
subsystem and its options, refer to Chapter 2.

1.3 DMRII SYSTEM OPERATION
Operation of the 0 M R II is Initiated and directed by a user program residing in the central processing
unit's (CPU) memory. A user program consists of an application program and a device driver routine
1-3

that interfaces with the OM R II. Communication between the user program and the OMR II is accomplished by four 16-bit control and status registers (CSR) integrated to the microprocessor. These
CSRs are used for initializing, selecting the mode of operation, assigning receive or transmit buffers to
the OM R II, obtaining receive and transmit buffer returns from the OM R II, and error reporting.
The first two registers in the group have a fixed format and serve as a command header for the second
two registers. The second two registers form a two-word data port for the exchange of unique control/status information between the OM R II and the user program. Data port contents are specified
by an identification field in the command header. Other fields in this header control interrupt enabling
and status bits for command transfer handshakes between the main CPU and the OM R Ii.
A user program issues a command to the OM R II by setting up the input command header and
requesting the use of the data port. When the OMR II grants permission to use the data port, the user
program passes the command to the OM R II in the pertinent CSRs. The OM R II interprets the command and performs the specified actions.
The OM R II issues error or status information to the user program by storing the command in the
pertinent CSRs and by notifying the user program that the status is available for retrieval and processing.
Message data received or transmitted by the OMR II is written into or read from the user program
assigned buffers in the main CPU memory. The OMR II accesses these buffers through NPRs to a
UNI BUS address. A UNI BUS address is an 18-bit address used by an N PR device to access a device
on the UNIBUS or a location in main CPU memory.

1.3.1 Command Structure
As previously stated, comm unication between the main CPU resident user program and the D M R II is
accomplished through a set of four 16-bit UNIBUS CSRs. This is accomplished by using these CSRs
to implement an input and output command structure.

There are five input and three output commands. Their functions are discussed in Chapter 3.

1.3.2 Input Commands
Input commands are issued by the user program to initialize, select the mode of operation, and assign
receive or transmit buffers to the DMR II.

1.3.3 Output Commands
Output commands provide a means for the OMR II to report various normal and abnormal (error)
conditions concerning the data transfer operation.

Two basic commands are provided:
I.

Receive or Transmit Buffer Address/Character Count Out and

Control Out

The Buffer Address/Character Count Out command is used to report a successful, error free completion of a receive or transmit buffer and it indicates the actual number of bytes transferred. This
command utilizes both Select 4 (SEL 4) and SEL 6 to identify the address of the completed buffer and
the actual character count of the transfer.

1-4

The Control Out command is used to report specific conditions concerning the DDCM P, the user
program, the hardware, or the modem. Control Out utilizes SEL 6 to inform the user program as to
the nature of the report (refer to the following).
•

Error Status
Identifies the reason for the error condition (errors can be associated with the DDCM P, the
user program, the modem, or other hardware limitations). In some cases the error condition
is non-fatal and normal operations can continue. Other errors are fatal, causing the DM R II
to shut down.

1.3.4 D M R II Operation Sequencing
The normal sequence of operation is represented in the flow chart in Figure 1-3.
The user program initializes the DMR II by issuing the Initialize command with the Master Clear bit
set. When the DMR II has completed the initialization, it sets the Run bit. At this point the user
program assigns a 128-byte Base Table in CPU memory to the DM R II for maintaining error counters
and storage of vital information on shut-down. This is done using the Base In command. The user
program via the Control In command then sets the DMR II for either half-duplex or full-duplex and
either DDCMP Normal or DDCMP Maintenance Mode. If Normal DDCMP Mode is selected.
D M R 11 initiates protocol start up.
The user program should now assign transmit and receive buffers to the DM R II via the Buffer Address/Character Count In command. When a transmit buffer is assigned. the DM R II issues an N PR
to retrieve the data from CPU memory for transmission on the serial line.

If there are receive buffers assigned when the DM R II receives data over the serial line, it issues an
N PR to transfer the data to the CPU memory.
The DM R 11 performs message sequencing, link management. cyclic redundancy check (CRC) error
checking, error connection via retransmission, and some error reporting to the CPU.

1.3.5 Maintenance Mode Operation
A special DDCMP message format, the maintenance message, is used for down-line loading, restarting, or otherwise maintaining satellite computer systems. Messages in this format are subject to error
checking but are unsequenced, unacknowledged, and not retransmitted automatically by the microprocessor.
The user program must initialize the DMR II, give it a Base In with the Resume bit clear, and then give
a Control In to put the DMR 11 in Maintenance Mode.

1.4 GENERAL SPECIFICATIONS
The following paragraphs contain performance, electrical, and environmental specifications for all
D M R II configurations. Table 1-2 lists the performance parameters of the D M R II.
1.4.1 Power Requirements
The M8207-RA and M8203 line unit power requirements are listed below:
Module

Voltage Rating (Approximate Values)

M8207-RA

+ 5 volts @ 5.0 amperes
+ 5 volts @ 3.0 amperes
+ 15 volts @ .11 amperes

M8203

-15 volts @ .2 amperes

1-5

VAX/PDP-ll PROGRAM

INITIALIZE
DMR11

VIA MASTER CLEAR

ASSIGN 128BYTE BASE TABLE

.......... VIA BASE IN COMMAND

SET UP PROPER
MODE
HALF-OR FULL-DUPLEX
AND NORMAL DDCMP OR
DDCMP MAINTENANCE
DMR11 INITIATES THE
PROTOCOL START UP
SEQUENCE
DMR11 IN DDCMP RUNNING MODE
AFTER COMPLETION OF DDCMP START
SEQUENCE

VIA CONTROL IN COMMAND

..
'Ir

ASSIGN TRANSMIT &
RECEIVE BUFFERS

TRANSMIT

............ VIA BUFFER ADDRESS/CHARACTER
COUNT IN COMMANDS

RECEIVE

DMR11 (1) PROCESSES
THE RECEIVED HEADER, (2)
CH ECKS CRC CHARACTERS, (3)
CONTROLS ACKNOWLEDGEMENTS (ACKS) OF
PROPERLY RECEIVED DATA MESSAGES AND NEGATIVE ACKS (NAKS) FOR
ERROR MSGS.

DMRll (1) GENERATES D'DCMP
PROTOCOL HEADER, (2) GENERATES AND TRANSMITS CYCLIC
REDUNDANCY CHECK (CRC)
CHARACTERS

I
THE DMR11 PERFORMS
MESSAGE SEQUENCING,
CRC ERROR CHECKING,
RETRANSMISSION,
SOME ERROR REPORTING
TO THE PDP-11, AND
LINK MANAGEMENT
MK-2323

Figure 1-3

DM R II Operation Sequencing

1-6

Table 1-2

DMR 11 Performance Parameters

Parameter

Description

Operating Mode

Full-Duplex or Half-Duplex

Data Format

Synchronous 0 DCM P

Special Data Rates

Up to 1M bls

Cable Length

Refer to M8203 Line Unit Technical Manual, EK-M8203-TM001, Appendix B

1.4.2 Environmental Requirements - All DMR lIs
The D M R 11 is designed to operate in a Class C environment as outlined in DEC Standard 102.
•

Operating temperature range - 5°C to 50°C (41 ° F to 120° F)

•

Relative humidity - 10 to 90 percent with a maximum wet bulb of 28°C (82°F) and a
minimum dewpoint of 2°C (36°F)

1.5 EIA STANDARDS OVERVIEW (RS-449 vs RS-232-C)
The most common interface standard used in recent years has been the RS-232-C. It does, however,
have serious limitations for use in modern data communications systems: the most critical being speed
and distance.
For this reason, the RS-449 standard has been developed to replace the RS-232-C. It maintains a
degree of compatibility with RS-232-C to accommodate an upward transition to RS-449.
The most significant difference between RS-449 and RS-232-C is the electrical characteristics of signals
used between the data communication equipment (DCE) and the data terminal equipment (DTE). The
RS-232-C standard uses only unbalanced circuits while the RS-449 uses both balanced and unbalanced
electrical circuits. The specifications for these different types of electrical circuits supported by RS-449
are contained in EIA Standards RS-422-A for balanced circuits and RS-423-A for unbalanced circuits.
These new standards permit much greater transmission speeds and will allow greater distances between
the DTE and DCE. The maximum transmission speeds supported by RS-422-A and RS-423-A circuits
vary with circuit length; the normal speed limits being 20K bls for RS-423-A at 200 feet and 2M bls
for RS-422-A at 200 feet. These normal speeds can be exceeded in special applications by trading speed
for distance, or vice-versa.
Another major difference between RS-232-C and RS-449 is that two new connectors have been specified to allow for the additional leads needed to support new circuit functions and the balanced interface circuits. One connector is a 37 pin cinch used to accommodate the majority of data
communications applications. The other is a nine pin cinch used in applications requiring secondary
channel functions. Some of the new circuits that have been added in RS-449 support local and remote
loopback testing, and standby channel selection.
The transition from RS-232-C to RS-449 will take some time. Therefore, any applications that are
interconnected between RS-232-C and RS-449 must adhere to the limitations of RS-232-C, which has
a normal speed of 20K bls at a maximum distance of 50 feet.

1-7

CHAPTER 2
INSTALLATION

2.1 SCOPE
This chapter provides all the necessary information for installing and testing the DM R II microprocessor subsystem. A checklist, which can be used to verify the installation process, is also included.

2.2 UNPACKING AND INSPECTION
The DM R II is packaged according to commercial packing practices. When unpacking, remove all
packing material and check the equipment against the shipping list (Table 2-1 contains a list of supplied items for each configuration). Inspect all parts and carefully inspect the module for cracks, loose
components, and separations in the etched paths. Report damages or shortages to the shipper and
notify the DIGITAL representative.

2.3 INSTALLATION CONSIDERATIONS
Installation of the DMRII microprocessor/line unit subsystem should be done in four phases:
•

Phase I - Preinstallation Considerations
Verify system requirements, system placement. and configuration requirements.

•

Phase II - Microprocessor Installation
Configure, install, and verify microprocessor module via the appropriate diagnostics.

•

Phase III - Line Unit Installation
Configure the line unit module for the customer application and install, cable, and verify it
via appropriate diagnostics.

•

Phase IV - DMR II System Testing
Verify the DMR II microprocessor subsystem operation with the functional diagnostics and
system exercise programs.

2.4 PREINSTALLATION CONSIDERATIONS
The following (Table 2-1) should be considered prior to ordering a DM R II communications interface
to insure that the system can accept the DM R II and that it can be installed correctly. These steps
should also be verified at installation time.

2-1

Table 2-1
Option

DMRll Option Packing List

Parts List

DMRII-AD

DMR II basic subsystem unit containing:
M8203
M8207-RA
BC08S-1
H3254
H3255

Line unit module
Microprocessor module with DMR II micro'code
ROMS
Module interconnect cable
V.35 and integral module test connector
RS-232-CjRS-422-AjRS-423-A module test Iconnector

EK-DMRII-UG-OOI

DMRII User's Guide

MP-00911

Customer print set

ZJ-306-RB

Diagnostic set

DMRII-AA

RS-232-C/RS-423-A interface configuration containing:
DMRII-AD
BC55C-lO
H3251
H325

DMRlI-AB

Basic DMRll unit
EIA RS-232-CjRS-423-A cable
Cable turnaround test connector
Cable turnaround test connector
CCITT V.35 interface configuration containin g:

DMRII-AD
BC05Z-25
H3250
DMRlI-AC

Basic DMRll unit;
CCITT V.35 cable
Cable turnaround test connector
Integral Modem interface configuration cont aining:

DMRII-AD
BC55A-IO
H3257
H3258
DMRII-AE

Basic DMR II unit
Integral Modem cable
BC55A terminators

RS-422-A interface configuration containing:
DMRII-AD
BC55B-IO
H325l

2.4.1

Description

Basic DMR II unit
RS-422-A cable
Cable turnaround test connector

System and Device Placement

2.4.1.1 System Placement - On systems that contain many high speed direct memory access (DMA)
devices, there is a probability of adverse bus latency. To help prevent this occurance, the closer the

2-2

physical placement of the DMRII to the processor, the higher the DMA device priority. A single DMRll
at 1M b/s and in full-duplex mode is capable of transferring 125,000 bytes/second/channel X 2 channels
(Transmit and Receive). Because the DMRII performs 16-bit word transfers via nonprocessor request
(NPR) transactions to memory,' approximately 125,000 NPRs per second at the rate of 8 microseconds/NPR
are generated. Customer applications using speeds greater than 250K bits per second (b/ s) require
UNIBUS placement before all UNIBUS repeaters and before all devices that have a lower NPR rate on
the UNIBUS.
2.4.1.2 Device Placement - The DMRII requires two hex-height. small peripheral controller (SPC)
backplane slots (preferably two adjacent slots). Any SPC backplane [DD II-B(REV E) or later] can
accept the DMRII. The DDII-D can accommodate a maximum configuration of three DMR lis.
CAUTION
Each DMR 11 requires approximately 8 amperes
from the +5 volt source. Check to ensure that the
supply is capable of providing a total of 24 amperes if
a maximum configuration is installed.
2.4.2

System Requirements
I.

UNIBUS Loading
M8207-RA microprocessor

M 8203 line unit

I UNIBUS dc load
5 UNIBUS ac loads

No UNIBUS loads

Power Requirements
Check the power supply before and after installation to ensure against overloading. The
microprocessor/line unit total current requirement for the + 5 volt supply is approximately 8
amperes. Additionally, the unit requires ± 15 volts for the silos. level conversion logic. and
Integral Modem. Power requirements for the microprocessor/line units are listed in Table 22.

Table 2-2

DMRll Voltage Chart

Module

Voltage Rating
(Approximate Values)

Maximum
Voltage

Minimum
Voltage

Back Plane
Pin

M8207-RA

+ 5 Volts @5.0A

+ 5.25

+ 5.0

CIA2

M8203

+ 5 Volts @3.0A

+ 5.25

+ 5.0

CIA2

+ 15 Volts @ .1 A

+15.75

+14.25

CIUI

@ .2A

-15.75

-14.25

CIB2

-15 Volts

2-3

I nterrupt Priority
The interrupt priority is selected by priority plug E77 on the M8207-RA microprocessor
module. This plug is preset to select priority five (BR5). Refer to Figure 2-1 for the priority
plug location.

Device Address Assignment
The DMR II resides in the floating address space of the Input/Output (I/O) page of memory. The ranking assignment of the DMR 11 is equal to the DMCII ranking number seven.
The selection of the device address is accomplished by Switch Pack E 127 on the M 8207· RA
microprocessor module. Refer to Figure 2-1 for the switch pack placement. Since the
OM R II will reside at the same ranking as the DMC II. the operating system can determine
what type of device resides at that address location by reading the second control and status
register (CSR) of the device and examining the high bYle.
If the bootstrapping feature of the OM R II or DMC II is to be used. only the devices that
reside at unit zero and/or unit one address location can implement this feature. unless bootstrap is designed to accept more units.
Refer to Appendix A if more information is needed on the floating address allocation.

Device Vector Address Assignment
The 0 M R II resides in the floating vector space of the reserved vector area of memory. The
ranking assignment of the DMRII is equal to the DMCII ranking number 27. The selection
of the device vector address is accomplished by Switch Pack E28 on the M8207-RA microprocessor module. Refer to Figure 2-1 for the location or the switch pack. Appendix A
contains more information on floating vector allocation.

2.5

MICROPROCESSOR INSTALLATION

2.5.1

Backplane Considerations

Perform the following on the SPC slot that will contain the OM R II. M8207-RA mlcroproc(!ssor
module (selected at preinstallation).
I.

Verify that the backplane voltages are within the specified tolerances listed in Table 2-2.

Turn system power off and remove the N PR Grant (N PG) wire that runs between CA I and
CB I on that backplane slot for the M8207-RA module.

NOTE
Be sure to replace this jumper if the microprocessor
is removed from the system.
3.

2.5.2

Perform resistance checks on the backplane voltage sources to ground to ensure that no
short circuit conditions exist. Refer to Table 2-2 for backplane pin assignments.

M8207-RA Considerations

Perform the following on the DMR II M8207-RA microprocessor module.

Ensure that the module version number is an M8207-RA, which indicates DMR 11 microcode.

2-4

SWITCH PACK E127
DEVICE ADDRESS
SELECTION
A3 - - - - - - - - - - - - - - - - - - -- A 12

SWITCH OFF
LOGICAL 1
(REFER TO TABLE 2-4)

W1
~

W2
c:::::=:l

SWITCH PACK
E85
PRIORITY
PLUG

SWITCH PACK E28
V3 - - - - - - - - - - - V8

SPARES
BSEL 1 LOCKOUT
VECTOR ADDRESS
SELECTION
SWITCH ON = LOGICAL 1
(REFER TO TABLE 2-5)

RUN INHIBIT
CSR DISABLE
MK-2120

Figure 2-1

M8207-RA M icroprocessor Switch/Jumper Locations

2-5

Verify that M8207-RA jumpers W I and W2 are installed correctly (refer to Jumper Table 23).

Configure Switch Pack E 127 to implement the correct device address for the 0 M R II as
determined from the floating address allocation. Refer .to Table 2-4 for the correlation between switch number and address bit. A switch OFF (open) responds to logical one on the
UNIBUS. Refer to Appendix A for additional information on floating address allocation.

Configure Switch Pack E28 to implement the correct vector address for the OM R II as
determined from the floating vector allocation. Refer to Table 2-5 for the correlation between switch number and vector bit. A switch ON (closed) responds to a logical one on the
UNIBUS. Refer to Appendix A for additional information on floating vector allocation.

Verify that the switch selectable features of the M8207-RA are configured as follows (Table
2-6 provides a summary of switch selectable features):
•

Run Inhibit - Switch Pack E28, switch 7; always ON.

•

CSR Inhibit - Switch Pack E28, switch 8; always OFF.

•

Byte Select/Lockout (BST) - Switch Pack E85, switch I, normally ON (allows all functions in Byte Select 1 to be used). If the switch is OFF, the Run bit is always asserted
and will not allow diagnostic testing.

NOTE
Switch Pack E85, switches 2, 3, and 4 are not used.
6.

Verify that the priority plug is a BR5 and is installed correctly in location E77.

Table 2-3

M8207-RA DMR 11 Jumper Chart

Jumper
Number

Normal
Configuration

Always In

Microprocessor Clock Enable - When removed it disables the microprocessor clock. Removed only for automatic module testing at the
factory.

Always In

Bus ac Low Enable - When removed it disables a program asserted
ac low signal passed onto the UNIBUS.

Function

2.5.3 M8207-RA Insertion
Carefully insert the M8207-RA microprocessor module into the selected SPC slot and perform the
following tasks:
I.

Perform resistance checks on the backplane voltage sources to ground to ensure that no
short circuit conditions exist on the module. Refer to Table 2-2 for backplane pin assignments.

Turn system power ON and verify that the backplane voltages are within the specified tolerances listed in Table 2-2.

2-6

Load and execute the M8207 static diagnostics, parts one and two (no test connectors are
required).
A.

PDP-ll System
CZDMP* M8207 Static Test 1
CZDMQ* M8207 Static Test 2

VAX-ll/780 Systems
EVDXA COMM Microprocessor Repair Level Diagnostics
REV *.*

2.6 LINE UNIT INSTALLATION
The M8203 line unit is a universal module with various types of interface capabilities. The M8203 line
unit does not present any ac or·dc loads to the UNIBUS and only draws power from the backplane slot
in which it resides. All data and control signals flow into and out of the line unit via a berg port to the
microprocessor. Because of the various M8203 applications, the configurations for each may be different and are selected via switches, jumpers, and different cables. To provide a better understanding of
these variations, a number of tables describing each switch pack, jumper, and cable function (as listed
below) has been created for reference. Table 2-7 lists the normal M 8203 line unit configurations for the
different types of DMR II options without the bootstrap feature selected. Also, refer to the following:
•

Table 2-8 Jumper Functions - These jumpers are used to select various interface standard
parameters and modem interface signals, depending on application and modem type. Additional jumpers are available on the BC55C (panel) cable for additional interface signal selection.

•

Table 2-9 Switch Pack E39 Functions - This switch pack allows proper selection of interface
driver and receiver control logic and different line speeds for various applications.

•

Table 2-10 Switch Pack E 121 Functions - This switch pack is provided for the selection of the
bootstrap offset address for the remote load detect feature (if used) and for various microcode
switch features.

•

Table 2-11 Switch Pack E 134 Functions - This switch pack is provided for the selection of
the bootstrap password for the remote load detect feature (if used) and for various microcode switch features.

•

Table 2-12 Cable Description - This table lists the functions and uses of each cable used with
the DMRII.

•

Figure 2-2 shows the jumper and switch pack placements on the M8203 line unit.

•

Figure 2-3 shows the microprocessor and line unit installation.

•

Figure 2-4 shows the outline drawings of D MRll cables.

2-7

Table 2-4
Switches

Function

1-10

Device Address Selection:

Switch Pack EI27 Selections

MSB

LSB

15 14 13
1

SWITCH PACK E 12'7

SWITCH
NUMBER

II
II

I
I
I

I
I

•

OFF
OFF
OFF OFF

OFF
OFF
OFF
OFF OFF
OFF OFF OFF

DEVICE
ADDRESS
760010
760020
760030
760040
760050
760060
760070
760100

---

OFF

760200

OFF OFF

760300

OFF
OFF

I
I
I

S10 S9 S8 S7 S6 S5 S4 53 52 51

OFF

---

----760500
--760600
--760700
--761000
--762000
--763000
-764000
760400

OFF

OFF OFF
OFF OFF OFF
OFF
OFF
OFF OFF
OFF
NOTE: SWITCH OFF RESPONDS TO LOGICAL ONE ON THE UNIBUS.

SWITCH PACK E127
DEVICE ADDRESS
SELECTION

A3 - - - - - - - - - - - - - - - - - - - - A 1 2

Switch Pack

E127

2-8

Table 2-5
Switches

Switch Pack E28 Selections

Function
NOTE
Switch ON equals a logical one (1) on the UNIBUS.

1-6

Vector Address Selection:

LSB

MSB

15 14 13 12 11
0 0 0 0 0

10
0

I 7 161 5 I 4 I 3

SWITCH PACK E28

1
0

0
0

••
••
••
•S6 S5 S4 •S3 S2 S1 • VECTOR
SWITCH

NUMBER

ADDRESS

ON ON
ON ON
ON ON
ON ON
ON ON ON
ON ON ON
ON ON ON
ON ON ON
ON

ON
ON
ON ON
ON
ON
ON ON

300
310
320
330
340
350
360
370
400

--ON

ON ON

500

---

600

--ON ON ON

700

NOTE: SWITCH ON PRODUCES LOGICAL ONE ON THE UNIBUS.
SWITCH PACK E2a
V3 - - - - - - •. - - - - va

'--

--J

VECTOR ADDRESS
SELECTION

RUN INHIBIT*eSR DISABLE*-

*Refer to Table 2-6 for switch functions.

2-9

Table 2-6

Switch Selectable Features

Switch
Location
and Number

Normal
Configuration

E28
Switch 7

Run Inhibit - Under normal conditions, switch ON. The initialization of the microprocessor directly sets the run flip-nop
which allows the microcode to be executed immediately. Because
of an internal malfunction or execution of erroneous microcode
during power up, it is possible for the microprocessor to hang the
UNIBUS. Placing the Run Inhibit switch in the OFF position
clears the Run flip-flop and allows the diagnostics to be loaded to
determine the fault. Once diagnostics have been executed and the
problem corrected, return the Run switch to the ON position.

E28
Switch 8

OFF

CSR Inhibit - When the switch is ON it keeps the device from
responding to its address. Used in special applications on other
options.

E85
Switch

BSEL 1 Lockout (BST) - When the switch is OFF, it inhibits the
use of all maintenance test features and keeps the Run bit asserted
at all times. This allows the OM R 11 microcode to run with the
ability to detect a boot request message at all times. This is use:d at
unattended computer sites. This switch must be ON to execute all
diagnostics.

Function

NOTE
Although BSEL 1 Maintenance functions are inhibited, Master Clear (bit 6) is still functional.
E85
Switches
2, 3, and 4

OFF

Not Used

2-10

Table 2-7 Normal M8203 Configuration (Bootstrap Not Selected)
Option Type:
M8203
Configuration

DMRll-AA
EIA RS-232-C
or RS-423-A

DMRII-AB DMRII-AE
CCITTV.3S EIA
RS-422-A

S6K bls

DMRII-AC
Integral
Modem
1 MEG bls

DMRll-AA
Null Modem
Clock
9.6K bls

DMRII-AC
Integral
Modem

Jumper
Configuration·
(refer to Table 2-8)

WI-W6, Wll
WI4-WI7

OUT

W7-WI0
W12,W13

Switch Pack E39

SI-4
S5
S6
S7
S8
S9
S10

OFF
OFF
OFF
OFF
ON
ON
OFF

OFF
ON
OFF
OFF
ON
ON
OFF

OFF
OFF
OFF
ON
.oN
ON
OFF

OFF
OFF
OFF
OFF
OFF
OFF
ON

OFF
OFF
OFF
OFF
ON
ON
ON

OFF
OFF
OFF
OFF
OFF
ON
OFF

SI-8

OFF

S10

OFF

DMRII
to
DMCII-AL

SI-8

OFF

S9
S10

OFF
OFF
OFF
OFF
OFF
ON = Disables Microdiagnostics At Master Clear Time
OFF = Enables Microdiagnostics At Master Clear Time
NOTE: Switch selections for BSEL 1, Bit 13 = 0 at Master Clear Time.

OFF

Cables Required
(refer to Figure 2-4)

BC5SC-I0·
and
BC05D-25

BC05Z-25

BC55B-I0
and
BC55D-33

BC55A-IO
and Twinax
Cables

BC55A-IO
and Triax
Cables

BC55C-10*
and Null
Modem

Module Turnaround
Test Connector
(refer to Figure 2-5)

H3255
IN J2

H3254
INn

H3255
IN J2

H3254
INn

H3254
IN J2

EIA RS-232-C
H325

H3250

H3251

Half-duplex
Switch ON and
Cables
Removed

EIA RS-232-C
H325
Half-duplex
Switch ON and
EIA RS-423-A
Cables
H325 1
Removed

(refer to Table 2-9)

Switch Pack E 121 t
(refer to Table 2-10)

Switch Pack E 134 t
(refer to Table 2-11)

Cable Turnaround
Test Connector
(refer to Figure 2-5)
*Modem variable
t Customer application variable

EIA RS-423-A
H3251

OFF
ON

OFF

DMRll
to
DMCII-AR
OFF

ON
OFF

DMRll
to
DMRll @ 1M bls

OFF

ON
ON

DMRll
to
DMRll

OFF

Table 2-8
Jumper

M8203 Jumper Functions

Normal
Configuration

Function

OUT

Clear to Send EIA/V.35

OUT

Data Mode EIA/V .35

OUT

Receive Data EIA

OUT

Receive Clock EIA

OUT

Receive Ready EIA

OUT

Transmit Clock EIA

Signal Rate Indicate - When removed, opens signal to
interface in RS-422-A and RS-232-C configurations.
Remove when an BC05C-XX* cable is used as this
signal is presented to cinch pin nine, which has a positive
test voltage on some modems.

Data Mode (Data Set Ready) - When removed. opens
signal to interface in RS-422-A/423-A configurations.
It has no effect in RS-232-C. Remove when a BC05CXX* cable is used. as the signal is presented to cinch
pin 18. which is dibit clock on some modems.

Null Modem Clock - When removed the signal amplitude is lowered below the interface standards so as not
to create interference in some modems.

WIO

Terminal Ready - When removed. it opens the signal
to modem in RS-422-A/423-A configurations. Remove when a BC05C-XX* cable is used. as this signal
is presented to cinch pin 10. which is negative test voltage on some modems.

WII

OUT

Receiver Ready (Carrier Detect) - When installed. it
allows this signal to be on at all times. This could cause
a problem with the microcode since the Universal Synchronous Receiver/Transmitter (USYRT) will be enabled all the time.

WI2

Terminal in Service (Make Busy) - When removed. it
opens this signal to the modem. Some modems will not
answer the phone and will be put in Analog Loopback
when this signal is asserted. When a BC05C-XX* cable
is used, this signal is presented at cinch pin 25.

*DM R II does not support the use of a BC05C-XX cable.

2-12

Table 2-8
Jumper

M8203 Jumper Functions (Cont)

Normal
Configuration

Function

WI3

Oscillator Enable - To be removed only for factory
automatic testing. Jumper should always be installed
in the field.

WI4 and
WI5

OUT
OUT

56K Bandpass Filter Enable - With these jumpers installed, the bandpass filter is limited to 56K b/s. Used
in special applications only.

Wl6

OUT

Switched RTS-CTS Enable - When this jumper is installed, it enables the request to send and clear to send
interlock in the M8203 line unit which inhibits asserting RTS, until CTS is dropped. This jumper should
never be installed when the DMRII is operating with a
modem that has the constant CTS option installed.

WI7

OUT

Half-Duplex Lockout Enable - When this jumper is
installed, it enables the M8203 line unit half-duplex
lockout feature when half-duplex mode is selected. The
lockout feature disables the transmitter or receiver
when the other is active. This jumper applies only to
half-duplex applications. It must not be installed for
full-duplex applications.

NOTE
Jumpers WI6 and WI7 are mutually exclusive. Only
one or the other may be installed, not both. Also,
these jumpers are provided only on M8203 modules
REV E or higher. For modules up to REV D, refer to
ECO-M8203-MK-007 for details of similar jumpers.
*DMRll does not support the use of a BC05C-XX cable.

Table 2-9
Switches

Switch Pack E39 (Z) Selections

Function
NOTE
Switch off equals a logical one (1).

1-4

Not used in DMRII.

5-7

Interface Selection - Selects proper drivers and receivers for each interface type:

2-13

Table 2-9

Switch Pack E39 (Z) Selections (Cont)

Function

Switches

Interface Type

SW5

SW6

SW7

RS-232-C, RS-423-A,
Integral Modem*

OFF

V.35

OFF

RS-422-A

OFF

* Integral modem is selected by Be55A cable when installed in J 1 of the
M8203 line unit. Module connector J2 must not have a cable or test
connector installed.
(Switches 8-10)

Line Speed Selection - Selects modem speed for Integral Modem applications, Null Modem applications, and diagnostic testing.

Switch

Switch
Speed
I MEG
500K
250K
56K

ON
OFF
ON
OFF

ON
ON
OFF
OFF

10
ON
ON
ON
ON

Speed
19.2Kt
9.6K
4.8K
2.4K

ON
OFF
ON
OFF

ON
ON
OFF
OFF

10
OFF
OFF
OFF
OFF

t Normal switch setting unless the Integral Modem or Null Modem clock features are used.
Table 2-10 Switch Pack EI21 (Y) Selections
Switches

Function
NOTE
Switch 0 FF equals a logical one (I).

1-8

Bootstrap Offset Address Selection - These switches are physically connected to IBUS
Register 16 with switch I being the least significant bit (LSB) and switch 8 the most
significant bit (MSB). When the remote load detect (RLD) feature is used, Switch Pack
EI21 (switches 1-8) must contain the appropriate offset entry address in the bootstrap
program. The address formed by the DMRII is 173XXX, where XXX is the content of
E 121, switches 1-8. Variations in bootstrap ROMs may require different entry addresses
to boot the DMC 11 JDM R II. If the remote load detect, feature is not used, the offset
must. be set to octal 000, switches 1-8 all ON (closed).
NOTE
When the RLD feature is used, the microdiagnostics
in the bootstrap ROM must be disabled.

2-14

Table 2-10
Switches

Switch Pack EI21 (Y) Selections (Cont)

Function

The following examples are for the M930 1-Y J bootstrap module. Depending on the bootstrap module used, reference should be made to the appropriate manual for specific details.
1. M9301-YJ Bootstrap Technical Manual EK-M9301-TM-00I

2. M9312 Technical Manual, EK-M9312-TM-002

To boot DMR II unit 0 without CPU diagnostics, address 356 must be selected:
LSB
Switch #

MSB

Io~ I02FFlo~Flo~Flo~ Io~Flo7FFlo~FI =356

To boot DMR II unit I without CPU diagnostics, address 374 must be selected:
LSB
Switch #

MSB

IO~ IO~ IO~dO~Flo5FFlo~Flo7FFlo~FI =374

To boot DMRII unit 0 with CPU diagnostics, address 354 must be selected:
LSB
Switch #

MSB

Io~ Io~ IO~dO~Flo~ Io~Flo7FFlo~FI =354

To boot DMRII unit I with CPU diagnostics, address 372 must be selected:
LSB
Switch #

MSB

IO~ I02FFlo~ IO~Flo~Flo~Flo7FFlo~FI=

DMC Line Compatable - Switch is physically connected to IBUS Register II, bit 2. The
DMRII microcode uses this bit to determine whether to implement DIGITAL Data
Communications Message Protocol (DDCMP) version 4.0 or DMC Line Compatible
Mode.
• OFF = DMCII Line Compatible Mode.
• ON = DDCMP version 4.0, DMRII Operating Mode.

372

High Speed Select - Switch is physically connected to IBUS Register II, bit I.
NOTE
The combination of switches 9 and 10 must be appropriately selected to satisfy the configuration requirements as listed below.

2-15

Table 2-10
Switches

Switch Pack EI21 (Y) Selections (Cont)

Function

SW9

SW 10

Configuration

DDCMP version 4.0 (not connected to DMCII) with line speed less than
1M b/s.

OFF

DDCMP version 4.0 (not connected to DMC II) with line speed at 11\1
b/s.

OFF

Connected to low speed DMCII-DA (M8200-YA)

OFF

Connected to high speed DMCII-AL (M8200-YB)

Table 2-11
Switches

Switch Pack E134 (X) Selections

Function
NOTE
Switch 0 FF equals a logical one ( I ).

1-8

Bootstrap Password Selection - These switches are physically con nected to I BUS Register
15 with switch I being the least significant bit and switch 8 the most significant bit. ~n the:
DM R II, this switch will contain the bootstrap password if the bootstrap feature is being
used. Otherwise, it will contain an octal 377 [switches I through 8 OFF (open)].
NOTE
A password of 377 will disable the RLD feature.
Also, if the DMR II is connected to a modem and the
user program has not assigned Base In/Control In to
the DMRII, when the DMRII detects Ring Detect
it will drop DTR to disable answering the call.
Example of a password of octal 012:
LSB

Switches

MSB

IO~ I02FFlo~ IO~Flo~ IO~ IO~ Io~1

Auto-Answer Enable - When the switch is in the ON positon, auto-answer is disabled.
The DMRIl, following a power up or master clear, assests DTR allowing the DMRII to
answer an incoming call for remote load. The call terminates only when the user program
issues a Halt Request or the remote end terminates the call.
When the switch is in the OFF position, auto-answer is enabled. This allows the DMR I n
to monitor ring indicator (RI) and data set ready (DSR) to answer and control incoming
calls. Control is established using a 20 second call set up timer. Refer to section 3.7.2.1 for
additional information.

2-16

Table 2-11
Switches

Switch Pack E134 (X) Selections (Cont)

Function
NOTE
If a D MR II is installed on a switched line, this
switch must be placed in the OFF position to allow
the DMRII to effectively control incoming calls.

Microdiagnostic - Switch is physically connected to IBUS Register 11, bit 5. Microdiagnostic testing is executed when the conditions indicated below are met.

SELO
BIT 13-No

SWI0AT
E1340N
M8203

Execution of Microdiagnostics

Clear

No Microdiagnostics Run

Clear

OFF

Run Microdiagnostics

Set

Run Microdiagnostics

Set

OFF

NO Microdiagnostics Run

NOTE
When installing a DMRII to run under DMCII
software, it is advisable to place this switch in the
ON position. This is necessary where D M C II software is not designed to wait 6.4 ms for microdiagnostic testing to be completed.

*At Master Clear time
2.6.1 M8203 Considerations
Configure all appropriate switch settings and jumpers on the M8203 line unit module according to the
recommendations in Table 2-7.
NOTE
If the customer has additional requirements because
of modem restrictions or a bootstrapping feature, be
sure to configure the line unit to his requirements using the information contained in Tables 2-8 through
2-11.

Table 2-12
Interface

Cable Description

Description

RS-232-C
• Cable Assembly: BC55C-IO
(Refer to Figure 2-4A)
•

M8203 Connector: J2

• Test Connector: H325

A 3 m (10 feet) cable with a 40 pin, berg connector at one end
which is installed into J2 of the M8203 so that the rib.bed side
of the cable faces out. This creates a half twist in the cable
and is required for proper pin connections. The other end has
a panel bracket that includes three different cinch connectors,
JI, J2, and J3. Connector J2 is used for RS-232-C and is connected to the modem with external cable BC05D-25. The
bracket must be mounted on the rear mounting rail of the:
cabinet to ensure proper grounding and for easy access to external cable connections.
The BC55C panel contains several jumpers. Depending on
the modem option selected, certain jumpers must be installed .
Refer to Table 2-13 for detailed jumper configurations.

External Cable
•

BC05D-25 (Refer to Figure
2-4E)

A 7.5 m (25 feet) external cable that connects J 2 of the
BC55C panel to an RS-232··C modem.

• Test Connector: H325
RS-422-A
• Cable Assembly: BC55B-I0
(Refer to Figure 2-4B)
•

M8203 Connector: J2

• Test Connector: H3251

A 3 m (10 feet) cable with a 40 pin, berg connector at one end
which is installed into J2 of the M8203 so that the ribbed sidt:
of the cable faces out. This creates a half twist in the cable
and is required for propel" pin connections. This cable is sim··
Bar to the BC55C in that it has a panel bracket at the other
end. There is, however, only one connector on the panel (J2)
that is used with cable BC55D-33 for external connection to
the modem. The bracket must be mounted on the rear mount·
ing rail of the cabinet to ensure proper grounding and easy
access to external cable connections. The BC55B panel has
two jumpers (WI & W2) for shield grounding connections.
Normally, WI is always out (special application only) and
W2 normally in. For RS-449 applications, W2 can be remov··
ed to place a 100 ohm resistor between circuit ground and
frame ground to dissipate ground currents.

External Cable
•

BC55D-33 (Refer to Figure
2-4F)

A 10 m (33 feet) external cable that connects J2 of the
BC55B panel to an RS-422-A modem.

• Test Connector: H3251

2-18

Table 2-12
Interface

Cable Description (Cont)

Description

RS-423-A
• Cable Assembly: BC55C-IO
(Refer to Figure 2-4A)
•

M8203 Connector: J2

• Test Connector: H3251

Same cable as used for RS-232-C except that panel connector
Jl is used with external cable BC55D-33 for connection to the
modem. The bracket must be mounted on the rear mounting
rail of the cabinet to ensure proper grounding and easy access
to external cable connections. The BC55C panel contains several jumpers. Depending on the modem option selected, certain jumpers must be installed. Refer to Table 2-13 for detailed jumper configurations.

External Cable
•

BC55D-33 (Refer to Figure
2-4F)

A 10m (33 feet) external cable that connects J 1 of the
BC55C panel to an RS-423-A modem.

• Test Connector: H3251
V.35
• Cable Assembly: BC05Z-25
(Refer to Figure 2-4G
•

M8203 Connector: J 1

A 7.5 m (25 feet) modem cable with a 40 pin, berg connector
at one end that connects to J 1 of the M8203. A 37 pin, DataPhone Digital Service (DDS) connector is installed at the other end and connects to the modem.

• Test Connector: H3250
I ntegral Modem
• Cable Assembly: BC55A-I 0
(Refer to Figure 2-4C)
•

M8203 Connector: J 1

• Test Connector: NONE
(Place panel switch to
H DX Position for turnaround)

A 3 m (l0 feet) cable with a 40 pin, berg connector at one end
that plugs into J 1 of the M8203 with the cable strain relief
tab facing out. A BC55A connector panel is installed at the
other end. This panel contains four connectors, two female
and two male. The panel also includes a toggle switch to select either full-duplex or half-duplex. The panel is mounted on
the rear mounting rail of the cabinet to ensure easy access to
external connections and for proper grounding.
Appropriate terminator connectors H3257 or H3258 must be
used. See Figures 2-7 and 2-8.

NOTE
Ensure that all cables mounted in the M8207 and
M8203 are properly installed and seated in the berg
connectors.

2-19

Table 2-12
Interface

Cable Description (Cont)

Description

External Cables
•

BC55N-98 (Refer to Figure
2-4D)

A 29.4 m (98 feet) external twinax cable used to interconnect
a DMCII to a DMRII or a DMRII to a DMRII for a selected data rate of 56K b/s.

• Test Connector: NONE
•

BC55M-98 (Refer to Figure
2-4D)

A 29.4 m (98 feet) external triaxial cable used for the same
purpose as the BC55N, but for data rates above 56K b/s.

• Test Connector: NON E

2-20

AUTO ANSWER
MICRODIAGNOSTIC

~e88eQQea~a

=0
=1

SWITCH ON
SWITCH OFF

SWITCH PACK E134

SEL 0
BIT 13

SW10 AT
E134 ON
M8203

EXECUTION OF MICRODIAGNOSTICS

CLEAR

NO MICRODIAGNOSTICS IS RUN

CLEAR

OFF

RUN MICRODIAGNOSTICS

SET

RUN MICRODIAGNOSTICS

SET

OFF

NO MICRODIAGNOSTICS IS RUN

DMC LINE COMPATIBILITY
CONFIGU RATION

SW9

HIGH SPEED SELECT

~e8~8Q8~H8~

DDCMP VERSION 4.0 (NOT CONNECTED
TO DMC11) WITH LINE SPEED LESS
THAN 1 M B/S.

OFF

DDCMP VERSION 4.0 (NOT CONNECTED
TO DMCll) WITH LINE SPEED AT 1 M
B/S.

OFF

CONNECTED TO LOW SPEED DMC11-DA
(M8200 YA)

OFF

CONNECTED TO HIGH SPEED DMC11-AL
(M8200 YB)

SWITCH PACK E121

W3 W4

o 0

DD~~

wlw{, D DO nDt,
I t \ ~""

D
W160

Wl W2

W17

W12 Wl0

SWITCH
SPEED
8

1 MEG

500K

OFF

250K

OFF

56K

OFF

*19.2K

OFF

9.6K

OFF

4.8K

OFF

W15D

2.4K

OFF

SELECTS DATA RATE
(SEE TABLE 2)
SELECTS RS-422 INTERFACE
RESERVED
SELECTS V-35 INTERFACE

OFF

* NORMAL SWITCH SETTING UNLESS
THE INTEGRAL MODEM OR NULL
MODEM CLOCK FEATURES ARE USED.

SW5

SW6

SW7

R5-232-C OR R&423-A
OR INTEGRAL

OFF

V.35

OFF

RS-422

OFF

INTEGRAL MODEM IS SELECTED BY BC55A
CABLE WHEN INSTALLED IN J1 OF THE
M8203 LINE UNIT. MODULE CONNECTOR
J2 MUST NOT HAVE ANY CABLE OR TEST
CONNECTOR INSTALLED.
MK-2119

Figure 2-2

M8203 Switch/Jumper Locations

CONNECT CABLE BC05Z FOR V.35 INTERFACE OR
BC55A FOR INTEGRAL MODEM.

H3254

I~ ~

H3255

I~ ~

TEST CONNECTOR ~

I
I

M8203
LINE UNIT

M8207

tJ, MICROPROCESSOR
I

CONNECT CABLE BC55C-l0
FOR RS-232-C OR RS-423-A
INTERFACE, OR BC55B-l0 FOR
RS-422-A INTERFACE

t;'J

&.,

til

MAINTENANCE LED'S

TRANSMIT DATA (D13)

RECEIVER DATA (D12)

REQUEST TO SEND (D14)

I J1
I

f!1

CARRIER (Dll)
HEARTBEAT (D15)

DESIGNATION

BC08S-1

SEE TABLE BEL.OW FOR DESCRIPTION

liJ

..,
'--_ _ _ _ _ _-+-_.J.
§ _. ___ .
I___ Jk~
----- = _ . _-_.

SIGNAL QUALITY (Dl0)

DESCRIPTION

013

ON INDICATES DMRll IS TRANSMITTING A STEADY STREAM OF l's.

012

ON INDICATES DMR11 IS RECEIVING A STEADY STREAM OF l's.

014

ON INDICATES THE USYRT IS READY TO TRANSMIT WHEN CTS IS DETECTED.

011

ON INDICATES CARRIER IS PRESENT AT THE RECEIVER.

015

THE HEARTBEAT SEQUENCE IS GRAPHICALLY SHOWN IN THE WAVEFORM BELOW.

010

ON INDICATES CARRIER PRESENCE AND OFF INDICATES CARRIER ABSENCE.

EXECUTION OF
MICRODIAGNOSTICS
IF ENABLED

BASE IN/
CONTROL IN

~ 200 ms

ON
OFF--------------~

MASTER
CLEAR

RUN BIT
ASSERTED

BLINK RATE
5 TIMES/SECOND
(APPROXIMATE)

----1

HEARTBEAT WAVEFORM

REMAINS ON
IF HALT OR
FATAL ERROR
MK-1570

Figure 2-3

Microprocessor /Line U nit Installation

2-22

2.6.2

M8203 Insertion

With system power OFF, carefully insert the M8203 line unit module into the proper backplane slot
(usually adjacent to the microprocessor) and perform the following:
I.

Interconnect the line unit and the microprocessor using the BC08S-1 cable. One end of the
cable is connected to J I of the M8207-RA microprocessor module and the other end to J3 of
the M8203 line unit module. Carefully fold the cable back to the right, tightly against the
component side of either the microprocessor or line unit module, so as to fit it into the
mounting box. Refer to Figure 2-3 for connector layouts.

Insert the appropriate module test connector into the correct line unit connector as specified
in Table 2-7. Be sure to insert with "Sf DEI " (etched on the test connect.or) visible from the
component side of the line unit. See Figure 2-3 for test connector. orientation.
Schematics and outline drawings of each test connector used with the D M R II are provided
in Figure 2-5.

Turn System power ON and perform voltage checks on the line unit backplane slot. Ensure
that the voltages are within the specified tolerances as listed in Table 2-2.

VIEW A

NOT USED
IN DMR11

RS-232-C

RS-423-A

c=JW8

J1
0

c:::J W9

c::J W2

CJW3

0
0

<
<
W1

c:::J

[TIJ

rnJ

cru

CJW10
CJ W11
CJW12
c:::J W13
c:::J W14
c:::J W15

c::J W4

E:J W16

c::J W5

c:::J W1 7

c::J W18

fS3 W6

CJW7

[=:J

rnJ

W19

G3W20
[QJ c:::J W21

CR[J
BC55C-10(RS-23.2-C/RS-423-A) INTERFACE PANEL CABLE
MK·1571

Figure 2-4

DMRll Cable Drawings (Sheet 1 of 4)

2-23

VIEW B

000

BC55B-10 (RS-422-A INTERFACE) PANEL CABLE
MK-2136

VIEW C

FEMALE CONNECTORS

'""[!!=,,,,=I=====~?'>='====:::I::::::=-'t -~. . . __. . .
MALE CONNECTORS

BC55A-10 (INTEGRAL MODEM) PANEL CABLE

CONNECTOR PANEL
(FRONT VI EW)
MK-2137

H3258
TERMINATOR

H3257
TERMINATOR

MK-2244

Figure 2-4 DMRll Cable Drawings (Sheet 2 of 4)

2-24

VIEW D

BC55N TWINAX CABLE

MK-2168

VIEW E

25 PIN
CINCH

BC05D-25 (RS-232-C INTERFACE) MODEM CABLE

25 PIN
CINCH
MK-2139

VIEW F

37 PIN
CINCH

BC55D-33 (RS-422-A/RS423-A INTERFACE) MODEM CABLE

Figure 2-4 DMRII Cable Drawings (Sheet 3 of 4)

2-25

37 PIN
CINCH
MK-2187

VIEWG

BC05Z-25 (V.35 INTERFACE) MODEM CABLE
MK-2'138

Figure 2-4
4.

DMRII Cable Drawings (Sheet 4 of 4)

Load and execute the M8203 static diagnostics, parts one and two, with external maintenance mode selected.
A.

PDP-II System
CZDMR * M8203 Static Diagnostic I
CZDMS* M8203 Static Diagnostic 2

VAX-I 1/780 Systems
EVDMA M8203 Repair Level Diagnostics
REV *.*

Remove the module turnaround test connector and connect the appropriate cable (see Table 27) to the proper berg connector for the DMRII option selected. Refer to Table 2-12 for detailed
information on cable requirements and to Figures 2-6 through 2-8 for system cabling
configurations.

NOTE
When installing panel cables BeSSA, BeSSB, or
BeSSe, it is important that the panel be properly
mounted to the rear mounting rail of the cabinet to
ensure adequate grounding.
When connecting the BCSSC connector panel, verify that the appropriate modemjumpers on
the panel are properly configured for the option selected. Table 2-13 lists each of these options
and required jumper configurations.
Integral Modem options require that a 75 ohm terminator be connected to each receive line
(BC55A panel) at each end of a full-duplex and a half-duplex network. These terminators
are available in both male (H3257) and female (H3258) types to accommodate different
Integral Modem cabling. Selection of the appropriate terminator type is dependent upon
which type of unused panel connector is available on the receive line at the BC55A-1 0 panel.
Refer to Figure 2-7 for DMRII to DMCll cabling and to Figure 2-8 for DMRII to
DMRII cabling.

2-26

Table 2·13 Modem Option Jumper Functions

~
......J2-----~~
Jumper Iljf\J
/~

IN/' IN

2
3
4
5
6

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

W14
W3
W2
W6
W20

W5
W18
W17
W4
W16
W13

101

~....

IN
IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN

W21

IN·
•

WI5
WI0 IN

IN
IN
IN
IN
IN
IN

INt
IN
IN
IN
IN
IN
IN

IN .

W12

IN
IN
IN
IN

IN
IN
IN
IN
IN
IN

BA
BB
CA
CB
CC
AB
CF

SO
RD
RS
CS
OM
SO
RR

103
104
105
106
107
102
109

SCF
SCB
SBA
DB
SBB
DO

SF
SRR
SCS
SSO
ST
SRD
RT

126
122
121
110
114
119
115

141

CE
CH
CI

SRS
TR
SQ
RL
IC
SR
SF

120
108
110
140
125
III
112

116
113
117
142

SCA
CD
CO

IN
IN

Wll'
W9

SB
TM

*RS-232-C defmes both signals for this pin
t CCITT modem A only

2-27

Insert the appropriate cable turnaround test connector in the end of the cable. Refer to
Table 2-7 for the specific test connector. Load and execute the M 8203 static diagnostics
specified in step 4 using the external maintenance mode selected to verify the module and
cable. Upon obtaining a minimum of five error free passes, proceed to the DMR II System
Test Procedures, Section 2.7. Figure 2-5 illustrates the various test connectors used in the
DMRII.

J1
NUll ClK +
REC ClK +
TX ClK +

IiH
C£

NUll ClK REC ClKTX ClK TX DATA R DATA-

TX DATA +
R DATA +

RTS
CTS
REC ROY
TER ROY
DATA MODE
TXINT
RECINT
TXINT
RECINT

-..
-..
--

....

A-A

S
....

KK
.-

K
.....

T
....

Elll

OJ)

SIDE 1
H3254

N....N

M....M

VIEWA

H3254 MODULE TEST CONNECTOR (J1 ON M8203)
MK-2143

Figure 2-5

DMRII Turnaround Test Connectors (Sheet 1 of 5)

2.7 DMRII SYSTEM TESTING
The final step in the installation of a DMR II subsystem is to exercise the microprocessor and line unit,
as one complete unit, on the UNIBUS and over the communications link. This is the first testing that
will use the DMR II microcode.

2-28

000

AUX ClK +
TX ClK DIFF +
RX ClK DIFF +

OBODQA
OC
OFOJOEOH

AUX ClKTX ClK DIFF -

OlONQK
OM
OROTOPOS
OV
OU
W
OZOXoyO
QdOb· Oa
Oc
OIOgOhOP

RX ClK DIFFTX DATA 01 FF +
RX DATA DIFF +
TX DATA DIFF RX DATA DIFF RTS

onOkomOj

CTS
CDET
VIEWB

DTR

000

DSR

..
..-

-..
-

..
...
-

-..

....y

W
A

-a
X
-f

;.:

-~
§
-I

C
.....

.2
-f
t!

H3250
MK-2123

Figure 2-5

DMRII Turnaround Test Connectors (Sheet 2 of 5)

2.7.1 Functional Diagnostic Testing
Ensure that the specific cable turnaround test connector for the selected DMR II option is still installed at the end of the cable. Load and execute the DMR II functional diagnostics with the External
Mode selected. See Chapter 4 for details on this diagnostic test.
A.

PDP-II Systems
CZDMI* DMRl1 Functional Diagnostics

VAX-I 1/780 Systems

EVDCA
REV •.• - VAX Synchronous Link Level 2 Diagnostics
Upon obtaining a minimum of five error free end passes, proceed to section 2.7.2.
2.7.2 D ECX 11 System Exerciser
The DECX 11 system exerciser for the DMR 11 can be run in two different operating modes, Internal
and External. The External Mode selects faster UNIBUS activity. This mode also requires that the
specific modem test connector is installed at the end of the cable and is the preferred mode of operation. Refer to Chapter 4 for additional details.

2-29

SEND COMMON

REC COMMON

TER IN SER

INCOMING CALL

TER ROY +
DATA MODE +

SEND DATA +
REC DATA +

SEND DATA-

REC DATA** NULL ClK +

j...

~
§

-~1:

-8

SEND TIMING +
REC TIMING +

-E~

E...E

SEND TIMING-

..
-

REC TIMING-

...

-Y..

** NUll ClK-

RTS +
CTS +
REC ROY +

T
.:.

.......

SIGNAL QUALITY
SEL SIGNAL RATE

...

SIGNAL RATE IND
* SEC SEND DATA

* SEC REC DATA

*SEC RTS
~

*SEC CTS

LOCAL LOOP

TEST MODE
SELSTAND BY
STAND BY INO
RTS CTS REC RDY-

TER RDY-

+
+

R_R

-Y

N_N

TH2

TH1
H3255

P
....

0
K
.:..:
.:;;;:

--~

....

A...A

'!!

VIEWC

''''';'

H3255 MODULE TEST CONNECTOR (J2 ON M8203)

....U

MK-2122

= TERMINAL TIMING

Figure 2-5

* NOT REQUIRED FOR DMR11
** RS-449 SIGNAL

+
+

SIDE 1

M..M

DATA MODE -

Bj3

H.-H

NEW SIGNAL

DMRll Turnaround Test Connectors (Sheet 3 of 5)

2-30

SHIELD GROUND

-...

SIGNAL RATE INDICATION

•'3
•
2

SEND DATA +
SEND TIMING +
REQ DATA +

REQ TO SEND +

REQ TIMING +
CLEAR TO SEND +

...

i
6
....
7

1
....9

11>

LOCAL LOOP

11:..:

DATA MODE +
RECEIVER READY +

REMOTE LOOP
INCOMING CALL
SIGNAL RATE SEL

TERMINAL TIMING +

TEST MODE

..-

TERMINAL READY +

SIGNAL GROUND

13
14

•

1i
16
:a
17

•

RECEIVE COMMON

•

SEND DATA-

23
:;,,;:
24

...

26
27

....

SEND TIMINGREQ DATAREQ TO SENDREQ TIMINGCLEAR TO SEND TERMINAL IN SERVICE

25
:;,,;:

TERMINAL READY-

..-

RECEIVER READY -

-3i
32

...

33
:;,,;:-

NEW SIGNAL

TERMINAL TIMING-

DATA MODE-

SELECT STANDBY
SIGNAL QUALITY

STANDBY INDICATION
SEND COMMON

Figure 2-5

;.,.

29
A

H3251

;.,.

...

VIEWD

35
36

f1-

H3251 CABLE TEST CONNNECTOR
BC55B, BC55C A NO BC550)

DMRll Turnaround Test Connectors (Sheet 4 of 5)
2-31

MK-2121

H325
SCE324
SCT
15
SCR

SEC XMIT

11
CUT TO TEST
NEW ~ SYNC

SEC R C V = : : J

SI DE

XMITDATA~

RCVDATA~

1--------

•••••••••• •••
••••••••• •••

~~==tJ

CO~
NEWSVNC--~--1_4~
H325
6
DATA SET RDV-.....- ---1
c

CUTTOTEST*
NEWSVNC

VIEWE

DTR-....--~
22
R1-...-.....-----...
H325 CABLE TEST CONNECTOR (BC55C AND BC05D)

Figure 2-5

MK-2124

DMRII Turnaround Test Connectors (Sheet 5 of 5)

2.7.3 Final Cable Connections
The final step in the installation process is to return the 0 M R II to its normal cable connections, either
to the appropriate modem or to the distribution panel. The OM R II system cabling diagrams in Figures 2-6, 2-7, and 2-8, have been included to help show overall cabling for the various D M R II-XX
options. References to specified locations of the various test connectors during diagnostic testing are
also included. After the cables are connected to the appropriate modem or distribution panel, it is
suggested that the Link Test Program ITEP be exercised.
2.7.4 DMRll Link Testing
The OMR 11 can be exercised over a communications link by the Interprocessor Test Program (ITEP).
It is suggested t~at ITEP be configured to run first on a cable test connector and then on a modem with
the modem Analog Loopback test feature selected, if the modem includes this feature. Next, the
overall communications link should be exercised with the remote computer system that contains a
OMRII or a DMCl1.

2-32

RS-232-C INTERFACE
J2
BC08S-1

RS-232-C
MODEM

BC05D-25
J1
J2 TEST
CONNECTOR
H3255·

Ii!iWiI M8207 MICROPROCESSOR

CABLE TEST
CONNECTOR
H325

H325

MK-2131

RS-422-A INTERFACE
J2
BC08S-1

RS-422-A
MODEM

BC55D-33
J1

H3251
H3251

Ii!iWiI M8207 MICROPROCESSOR

H3255

MK-2132

Figure 2-6

DMR II Remote System Cabling Diagram (Sheet I of 2)

BcoaS-1

RS-423-A
MODEM

S
BC55D-33
H3251

J1
H3251

J2 TEST
CONNECTOR
H3255

• limo. Ma207 MICROPROCESSOR

MK-2133

BcoaS-1

V.35 INTERFACE
BC05Z-25

J1 TEST
CONNECTOR
H3254

m:miiI Ma207 MICROPROCESSOR

n::I
~

CABLE TEST
CONNECTOR
H3250

MK-2134

Figure 2-6

DMR II Remote System Cabling Diagram (Sheet 2 of 2)

FULL-DUPLEX
BCOSS-1
INSTALL 7S12
TERMINATOR
CONNECTOR (H3257)

Iiiiil

Ol!!!l

I!!!!!il
MS207 MICROPROCESSOR
J1

J1
MS200-XX
MICROPROCESSOR

I!!!i!il

mmm

Ii!!!iiilI!iEi!il
BCOSS-1
MK-2129

N
I

HALF-DUPLEX

BCOSS-1
INSTALL 7S12
TERMINATOR
CONNECTOR (H3257)

Iiiiil

Ol!!!l
l!1!i!E1

M8207 MICROPROCESSOR
J1

J1
MS200-XX
MICROPROCESSOR

MK-2130

Figure 2-7

DMCll to DMRll Integral (Local) Modem Cabling Diagram

FULL-DUPLEX

BC55A-10

INSTALL 75fl
TERMINATOR
CONNECTOR (H3257)

Ii!iW
M8207 MICROPROCESSOR
J1

J1
M8207 MICROPROCESSOR
miii!J

BC08S-1

BC55A-10

* FOR 56K bps USE CABLE BC55N-98
FOR 250K bps to 1 M bps USE CABLE BC55M-98
MK-2127

HALF- DU PLEX

BC55A-10

INSTALL 75fl
TERMINATOR
CONNECTOR (H3257)

IiimD
M8207 MICROPROCESSOR

J1
M8207 MICROPROCESSOR

mmm

BC55A-10

BC08S-1

* FOR 56K bps USE CABLE BC55N-98
FOR 250K bps to 1 M bps USE CABLE BC55M-98
MK-2128

Figure 2-8

DMRII to DMRII Integral (Local) Modem Cabling Diagram

2.8

DMRII-XX INSTALLATION CHECK-OFF LIST
Date Completed

PHASE I - Preinstallation Considerations:
I.

System placement (2.4.1.1)

Device placement (2.4.1.2)

System requirements (2.4.2)
a.
b.
c.
d.
e.

UNIBUS loading
Power requirements
I nterrupt priority level
D M R II device address determination
DM R II vector address determination

PHASE II - Microprocessor Installation
I.

Unpack DMR II option and verify that all
components were shipped (2.2 and
Table 2-1).

With power ON, verify selected SPC
backplane voltages (2.5.1 and
Table 2-2).

Turn power OFF and remove NPR Grant
(NPG) wire on selected SPC backplane
slot (2.5.1).

Perform resistance checks to ensure
that there are no shorts to ground
on the backplane (2.5.1 and Table 2-2).

Ensure that the module is an M8207-RA
and that W I and W2 are correctly installed (2.5.2 and Table 2-3).

I nstall correct device address as determined in Phase I (2.5.2 and Table 2-4).

Install correct vector address as determined in Phase I (2.5.2 and Table 2.5).

Install correct switch selectable features
(2.5.2 and Table 2-6).

Ensure that Priority Plug E77 is a BRS
and that it is properly installed (2.S.2).

2-37

Date Completed
10.

Install microprocessor module M8207-RA
into selected SPC slot (2.5.3).

11.

Perform resistance checks on backplane to
ensure that no shorts to ground exist on the
module. Turn power ON and verify voltages
(2.5.3 and Table 2-2).

12.

Load and execute M8207 Static Diflgnostics
(2.5.3 ).

PHASE III - Line Unit Installation
1.

Install the correct jumpers and switch
selections for the appropriate DMR 11
option. Use Table 2-7 to initially
set up line unit and if additional
features are required, refer to
Tables 2-8 through 2-11 (2.6.1, Figure
2-2. and Table 2-7).
A Iso refer to:
Table 2-8
Table 2-9
Table 2-10
Table 2-11

Jumper Functions
Switch Pack E39 Functions
Switch Pack E 121 Functions
Switch Pack E 134 Functions

I mportant switch/jumper verifications:
a.

If DMRII is used with a DMCII, make
sure Switch Pack E 121, switch 9 is OFF
(Table 2-10).

If DMR 11 is operating at a speed of 1M
b/s, make sure Switch Pack E121, switch
10 is OFF (Table 2-10).

If microdiagnostics are desired on initialization of the device, ensure that
Switch Pack E 134, switch lOis in the
appropriate position (Table 2-11).

If down-line load or remote load detect
feature is used, install the appropriate
boot offset address in Switch Pack E 121,
switches 1-8, and the system password in
Switch Pack E 134, switches 1-8, at the
remote end (Table 2-10 and Table 2-11).

2-38

NOTE
M9301-YJ or M9312 bootstrap module must be installed at the remote end.
3.

With power OFF, carefully install the M8203
line unit adjacent to the microprocessor
with interconnecting cable BC08S-1 in J3.
The other end is installed in J 1 of the
M8207-RA microprocessor (2.6.2 and Figure
2-3).

Correctly insert the proper module test
connector in J 1 and/or J2 of the M8203 line
unit (2.6.2, Figure 2-3 and Figure 2-6).

Turn Power ON, perform voltage checks, and
adjust if necessary (2.6.2 and Table
2-2).

Load and execute the M8203 static diagnostics
selecting module test connectors H3254 or
H 3255 (2.6.2).

Remove module test connector(s) and install
the appropriate option cable to either J 1
or J2, as required. When installing cables
BC55A, BC55B, or BC55C, it is necessary to
mount the connector panel on the rear
mounting rail of the cabinet. It is important
that the panel be properly mounted to ensure
adequate grounding. Insert the appropriate
turnaround test connector at the end of the
cable.

Load and execute the M8203 static diagnostics
in External Mode to verify cable connections
(2.6.2, Table 2-7 and 2-12, and Figure 2-4
and 2-5).

NOTE
On Integral Modem options, ensure that the 75 ohm
receive line terminators are installed on the BC55A10 panel as shown in Figure 2-7 or Figure 2-8.
PHASE IV - DMRll System Testing
I.

With cable turnaround test connectors still
installed, load and execute the DMR 11
functional diagnostic test (2.7.1).

2-39

Date Completed

Configure and execute the DECX 11 system
exerciser to include the DMR 11 option
(2.7.2 ).

Using ITEP, perform DMR 11 link testing on the
following (if possible):
a.
b.
c.

Cable test connectors installed
Modem Analog Loopback test
Link testing over network
(2.7.4).

Remove all cable test connectors, if
installed, and connect appropriate cables
to the modem or distribution panels
(2.7.3, Figures 2-6,2-7, and 2-8).

2-40

CHAPTER 3
PROGRAMMING

3.1 INTRODUCTION
The information in this chapter is essential when developing a user program that will properly interface to the DMR II.
The command structure and format of input and output commands, as well as data port descriptions,
are described in detail. Some examples of instruction sequences are also provided to demonstrate a
typical method of user program implementation. Other discussions include special programming techniques, user access to maintenance mode, and user interpretation of status/error reporting.
3.2 COMMAND STRUCTURE
The command set for the DMRII is structured into two categories; input commands and output
commands. Brief descriptions of Input/Output commands, including command codes and the handshaking requirements, are provided in this section.
Transfer of control and status information between the main central processing unit (CPU) resident
user program and the DMR II is accomplished through four 16-bit UNIBUS control and status registers (CSR). Input commands are issued to the DMR II by the user program and output commands are
issued to the user program by the D M R II .

3.2.1 Control and Status Registers
Four 16-bit CSRs are used to transfer control and status information. These registers are both byte
and word addressable. The eight bytes are assigned addresses in the floating address space in the I/O
page as follows:
76XXXO, 76XXXI, 76XXX2, 76XXX3, 76XXX4, 76XXX5, 76XXX6 and 76XXX7.
For discussion, these byte addresses are designated Byte Select 0 through 7 (BSEL 0 through BSEL 7).
The four word addresses are the even numbered locations and are designated Select 0, 2, 4, and 6 (SEL
0, SEL 2, SEL 4, and SEL 6). It is recommended that the CSR address be assigned to the floating
address space. Refer to Appendix A if detailed information on floating address space is required.
Figure 3-1 provides an overview of the CSR register format. Detailed bit descriptions of SEL 0 and
BSEL 2 are contained in Tables 3-1 and 3-2 respectively .

3-1

Table 3-1

SEL 0 Bit Functions

Bits

Name

Description

0-3

Input Command
Codes

Bits 0-2 define the type of input command issued
by the user program to the microprocessor (see
Table 3-3). Bit 3 is reserved for future expansion of
the input command set.

Reserved

Request In
(RQI)

Serves as an interlock bit when requesting the use
of the data port -- set by the user program to
request the data port. It is cleared by the program
when the data port has been loaded.

Interrupt
Enable In (lEI)

When set, allows the D M R II to interrupt to vector
address XXO, when RDI (bit i of BSEL 0) is set.

Ready In (RDI)

RDI is a DMR II response to RQI, indicating to
the program that it may load the data ports (SEL 4,
SEL 6). It is cleared by the DMR II indicating that
the data port has been read and the input command transfer is complete.

Step
Microprocessor
(Step J.LP)

When set, this bit steps the microprocessor through
one instruction cycle. The Run flip-flop should be
cleared before executing this control function.

ROM Input
(ROM IN)

When set, directs the contents of SEL 6 as the next
microinstruction to be executed by the microprocessor when Step J.LP or Run is asserted.

ROM Output
(ROM OUT)

When set, modifies the source paths for SEL 6 to
be the contents of the addressed control read only
memory (CROM) or the next microinstruction executed when Step J.LP is asserted.

Line Unit
(LU LOOP)

When asserted, connects the line unit seriallinc~ out
back into the serial line in. This is done at the TTL
level, before level conversion. When the Line Unit
Loop bit is set and Run is cleared, the STEP LU
clock is the only clock available for shifting data
out or in. When LU Loop and Run are set, data is
clocked at the maintenance clock rate (approximately 48K b/s).

3-2

Table 3-1

SEL 0 Bit Functions (Cont)

Bits

Name

Description

Step Line Unit

Used in conjunction with LV Loop. When asserted, the transmitter shifts. When cleared, the receiver shifts.

Microdiagnostics
(MICRO DIAG)

This bit controls automatic execution of internal
microdiagnostics at Master Clear time.
Depending on the position of switch 10 of Switch
Pack EI34 (M8203 line unit) either the Set or
Cleared condition of this bit can enable this feature. Refer to the chart below for specific conditioning.

SELO
BIT 13*

SW IOAT
EI340N
M8203

Execution of Microdiagnostics

Clear

No Microdiagnostics Run

Clear

OFF

Run Microdiagnostics

Set

Run Microdiagnostics

Set

OFF

No Microdiagnostics Run

M aster Clear

When set, Master Clear initializes both the microprocessor and the line unit. This bit is selfclearing.
The microprocessor clock is enabled, and the Run
flip-flop is asserted.
The microprocessor's program counter is also temporarily cleared by M aster Clear.

Run

On power up reset or device Master Clear, this bit
is set by the DMR 11 microcode to inform the user
program that the DMR II is ready to accept input
commands. Run can be cleared for maintenance
states.

*At Master Clear time.

3-3

RDI

RUN

INPUT COMMAND
CODE

•

lEI

I
I

Ral

I MASTR I MICRO I STEP
Jl

ClR

I
ROO

DIAG

LU
I
I lOOP I

•
I

'
I

•
I
I

1
1
,

lEO

ROM

OUT
RCV

; ROM
I
I

aSEl

o
;

ROM

I STEP
lIMP

I
I

OUTPUT
COMMAND

•

MICRODIAGNOSTIC STATUS *

I
I

DATA PORT
I

,
1

DATA PORT
I,

I
I

·
·

,
I

.
6

DATA PORT

,
I

I
I

DATA PORT
I

~_7__~__6
__~___
5 __L -_ _
4 __~__3__~__2__~____~~O~
MK-2221

*Yalid only immediately after Master Clear or Reset.

Figure 3-1

UNIBUS Control and Status Registers Format Overview

3.2.2 Initialization
Initialization places both the DMR 11 hardware and firmware in the initialized (operational) state. In
the initialized state, the DMR 11 does not send or receive messages, but it does check for Enter MOP
messages and for remote load detect (RLD).
Initialization is accomplished by one of the following methods:
1.

System Initialization •

System Reset

•

Power-up/shut-down sequence

By the user program - Set Master Clear bit (BSEL 1)

Initialization of the DMR 11 by the user program is done in two steps. The Master Clear bit is set, and
then waits for the DMR 11 to set the Run bit. Once the Run bit is set the DMR 11 is ready to accept
Base In.

3-4

Table 3-2

BSEL 2 Bit Functions

Bit

Name

Description

0, 1,2

Output Command

These bits define the type of data transfer from the
microprocessor to the user program:
Bit2

Bit I

Bit 0

Description

Transmit
Buffer
Addressj
Character
Count Out
(TBAjCCO)

Receive Buffer
Address
Character
Count Out
(RBAjCCO)

o
o

Control Out

Reserved
Reserved

3-5

Reserved

Interrupt
Enable Out
(lEO)

When set, enables the DMRII, upon asserting
R DO, to generate an interrupt to vector address
XX4.

Ready Output
(ROO)

Asserted by the OM R II to indicate that the data
ports (SEL 4 and SEL 6) contain data for the output command defined by bits 0-2 of BSEL 2. Bit 7
must be cleared by the user program after the data
port is read.

3-5

Internal microdiagnostic testing is automatically executed at this time (during power-up/initialization)
providing that this feature is appropriately enabled as described below:
SWI0 AT
E134 ON
M8203

Execution of Microdiagnostics

Clear

No Microdiagnostics Run

Clear

OFF

Run Microdiagnostics

Set

Run Microdiagnostics

Set

OFF

No Microdiagnostics Run

SEL 0
BIT 13*

*At Master Clear time.
If microdiagnostic testing is disabled, the Run bit will be asserted by the DMR II in about 240 microseconds. However, if enabled, the Run bit will be asserted (if tests pass) in about 6.4 milliseconds.
Test results (listed below) are available to the user program in BSEL 3. The program must check BSEL
3 before proceeding with Base In. If the tests fail, the DMR II will not assert the Run bit and further
operations are prohibited. Corrective action by authorized Field Service personnel is required.

BSELI

BSEL3

Indication

Run bit
Run bit
no Run bit
no Run bit

200 8
1008
0018 or XXX
002 8

Test Complete
Test Inhibited
M8207 Test Failed
M8203 Test Failed

Programming Example:

1$:

MOV

#40000,SELO

;SET MASTER CLEAR

BIT

SELO

;TEST RUN BIT

BPL

;BRANCH IF NOT READY YET
;CHECK BSEL3 FOR MICRODIAGNOSTIC
;STATUS
;PROCEED WITH BASE IN

NOTE
If the Run bit is not asserted within 6.4 milliseconds,
either the M8207 or the M8203 test may have failed
and the user should check BSEL 3.
3.2.3 Input Commands Overview
In general, input commands provide the means for the user program operational modes to assign
receive or transmit buffers to the DMR11. Detailed field descriptions and formats of each input command are provided in section 3.3.

3-6

Input commands are executed by the user program by requesting service and by setting the appropriate
bits of the command code in bits 0-3 of BSEL O. Specific handshake requirements to implement
command transfers are explained in section 3.2.3.1.
Input commands are listed in Table 3-3. The Base In command is the only command that the program
can issue, without causing a procedural error, following intialization.

Table 3-3

Input Commands

BSELO
Bit 3

Bit 2

Bit 1

Bit 0

Transmit Buffer Address/
Character Count In

Control In

Halt

Base In

Receive Buffer Address/
Character Count In

The Base In command must be followed by Control In, then Receive Buffer Address/Character Count
In (RBA/CCI), and then Transmit Buffer Address/Character Count In (TBA/CCI). Section 3.5. Programming Techniques, further defines proper command sequencing.

3.2.3.1 I nput Command Handshaking
At start up time, before the user program can execute any input command. it must initialize the
OM R 11. This is accomplished by the program setting the Master Clear bit in BSEL I and waiting for
the OMR 11 to set the Run bit.
Input command sequencing requires that Base In be the only input command used following initialization. This command must be followed by Control In, Receive Buffer Address/Character Count
In, and Transmit Buffer Address/Character Count In, respectively.
All input commands are issued by the user program in two successive steps. The first step requests the
use of the data ports. The second step identifies the command type and the data port information for
the appropriate command. The specific content of each data port is further defined under each command description in section 3.3. The handshaking procedure for input commands is as follows. (A
typical programming example for an input command assignment is provided in Figure 3-2. The flow
chart in Figure 3-3 further defines this process.)
The user program:
•

Requests the use of the data port to issue an input command by setting Request In (RQI) bit
5 of BSEL O. The user may also set bit 6 of BSEL 0, Interrupt Enable In (lEI). at the same
time (using the same instruction) to allow the OM R 11 to interrupt the CPU when the data
port is available.

3-7

NOTE
Because of interrupt and service time, it is
most efficient for the user program to have input interrupts disabled and to simply scan
RDI a few times (for less than 50 Ils). If RDI
is not set by the DMR 11 in 50 IlS, the user
should set the lEI bit twice and wait for an
interrupt.

When setting the I EI bit, the user program
must use two consecutive bit set byte (BISB)
instructions.

If interrupt mode is not used, the user must
scan for Ready Out (bit 7 of BSEL 2) while
waiting for RDI to set. The user program
must be prepared to accept an output transfer
from the DMR 11 while it is waiting for RDI.

•

When the Data Port is available, the DM R II informs the user by setting Ready In (bit 7 of
BSEL 0) and. if lEI was previously set, the DMR II generates an interrupt to vector XXO.

•

If modem status is desired, the user can, at this time. read SEL 4 and SEL 6 for modem
status.

•

On detecting RDI bit set, the user can load the input command code into bit 0-3 of BSEL 0
and also load the appropriate information into SEL 4 and SEL 6.

•

The user must then clear RQI (bit 5 of BSEL 0) to inform the DM R II to decode the input
command.

•

When the DMRll has read and decoded the input command, it clears RDI (BSEL 0, bit 7).
This completes input command handshaking.

3.2.3.2 Modem Status Read - This feature provides the user program with the option of reading
(monitoring) nlodem status during an input command. Modem status is updated by the DMRll to
SEL 4 and SEL 6 each time RDI is asserted in response to RQI.
Modem status is not guaranteed to be accurate prior to asserting RDI or after the program clears RQI.
Sensing RDI set, the user program can read the status before loading the data port(s) for the particular
command being executed.
Figure 3-4 shows the format for the modem status read feature. Table 3-4 lists the bit descriptions of
modem status read for all four data ports.

3-8

INPUT COMMAND ASSIGNMENT ROUTINE:
THIS ROUTINE COULD BE ENTERED VIA THE FOLLOWING CONDITIONS:
1. APPLICATION PROGRAM ISSUES AN INPUT COMMAND.
2. AT THE COMPLETION OF THE INPUT COMMAND OR OUTPUT
COMMAND PROCESSING BY THE DMR11 DRIVER, THERE ARE
SOME OUTSTANDING INPUT COMMANDS WAITING TO BE ISSUED
TO THE DMR11.

ASSUMPTIONS:
- : R4
CONTAINS DMR11 CSR ADDRESS (SEL 0).
- : R5
SCRATCH REGISTER.
- : ICMD:
.WORD ; ICMD10 -- INPUT COMMAND CODE
.WORD ; ICMD12 -- INFORMATION FOR SEL4 .
. WORD ; ICMD14 -- INFORMATION FOR SEL6 .

=
=

-: MDMS:

. WORD
.WORD

; MODEM STATUS 1.
; MODEM STATUS 2.

- : OUTPUT INTERRUPT IS ENABLED AT ALL TIMES.
INPUT:

10$:

20$:
30$:

40$:
EXIT:

BITB
DNE

# RQI,0(R4)
EXIT

; IS RQI ALREADY SEn
; YES - PREVIOUS INPUT IS NOT DONE YET

MOV
BITB
BEQ

#4,R5
#RDI,0(R4)
20$

; SET UP THE WAIT LOOP COUNT
; IS RDI CLEARED?
; YES - CONTINUE WITH THE INPUT

DEC
BNE
BR

R5
10$
EXIT

; SOME MORE WAITING?
; YES-

MOV
BISB
BITB
BNE
DEC
BNE

#4,R5
#RQI,0(R4)
#RDI,0(R4)
SETINP
R5
30$

BISB
BISB
RETURN

#IEIIRQI,0(R4)
#IEIIRQI,0(R4)

; SET UP THE WAIT LOOP COUNT
; NOW - SET THE RQt.
; IS RDI SET?
; YES - GO ISSUE THE INPUT NOW
; SOME MORE WAITING?
; YES
; RDI WAIT LOOP EXPIRED
; SET INTERRUPT ENABLE
; AGAIN

CAN ALSO BE ENTERED FROM AN INPUT INTERRUPT ROUTINE AFTER
VERIFYING THAT RQI AND RDI ARE BOTH SET.
SETINP:

MOV
MOV
BISB
MOV
MOV
BICB
RETURN

4(R4), MDMS+O
6(R4), MDMS+2
ICMD+O,O(R4)
ICMD+2,4(R4)
ICMD+4,6(R4)
# RQIIIEI O(R4)

Figure 3-2

; GET MODEM, STATUS NOW
; SET THE INPUT COMMAND CODE
; LOAD DATA PORT SEL4
; LOAD DATA PORT SEL6
; CLEAR RQI AND lEI
MK-2246

Programming Example for Input Commands

3-9

ENTER HERETO ISSUEAN INPUTCOMMAND

Y
ASSUMPTION
(1) lEO SET AT ALL TIMES.

SET (SOFTWARE FLAG
FOR) INPUT COMMAND
PENDING.

SET lEI
TWICE
(CONSECUTIVELY)

INPUT INTERRUPT
SERVICE ROUTINE

•

SAVE MODEM STATUS
FROM SEL4 & 6

•

SET INPUT CODE
INTO BSEL 0

•

LOAD SEL 4,6

•

CLEAR Ral & lEI

MK-2230

Figure 3-3

Input Command Servicing

3-10

,,
I

I
I
I

,
I
I

SIG
RATE

I
I

INPUT COMMAND CODE

I
I

,
,
,

I
1

I
I

I TEST I

I MODE I

I
I

SIG
QUAL

SEL2

I
I

I
DTR

HDX

V.35

I
I

SEL4

RTS

I HOLD
,1

I
I

'INTGL I
'MODEMI
1

DET

I RS-232 ,
RS-422 I RS-423 I

I
I
I
I

SELO

I DTR I
J

BSEL

i RTS I HDX I DSR I CTS I STND , CARR

I
RING

I
I

PROG
I SELECT

SEL 6

o
MK-2247

Figure 3-4

Modem Status Read Format

Table 3-4

Modem Status Bit Descriptions

Port

Bit(s)

Name

Description (If Bit is Set)

BSEL 4

Carrier

Valid for both the Integral Modem and the
modem interfaces. Indicates that the receiver is
active.

Standby

References the Standby indication from the
modem (refer to EIA specification RS-449).

Clear to
Send

This is a reply from the modem indicating that
data can be transmitted.

Modem
Ready

Indicates that the modem is in service.

HalfDuplex

This indicates that the line unit is set in halfduplex mode.

3
4

3-11

Table 3-4
Port

BSEL 5

Modem Status Bit Descriptions (Cont)

Bit(s)

Name

Description (If Bit is Set)

Request to
Send

This indicates that the Universal Synchronous
Receiver/Transmitter (USYRT) is ready to start
transmitting data as soon as Clear to Send is
true.

Data
Terminal
Ready

Ring

8,9
10

Indicates that the modem has just been dialed
up.
Reserved - Bit Condition. don't care.

Test Mode

I ndicates that the modem is in the test modI;! (refer to EIA specifications).
Reserved - Bit condition. don't care.

11-13

BSEL 6*

A signal from the line unit to the modem indicating the line unit is available and on-line.

Signal
Quality

A signal from the modem that indicates the presence or absence of the carrier. Usually. when this
signal is ON it indicates the presence of a carner
and OFF indicates an absence of a carrier.

Signal
Rate

A signal from the modem that indicates a data
rate. Usually a negative level indicates a lower
rate while a positive level indicates a higher rate.

RTS Hold

This bit is set for FOX at speeds less than 1M
b/s in OOCMP normal mode. When set. RTS
(EIA CA/CCITT 105) will be held asserted
while the communications link is idle (except
during error recovery).
Reserved~ Bit condition. don't care.

1.2& 3
4

HDX

5
6

When set. indicates that the line unit IS set in
half-duplex mode.
Reserved; Bit condition. don't care.

DTR

When set indicates that the line unit is availabl(!
and on-line.

*BSEL 6 contains data written to the modem register by the OM R II, as opposed to SEL 4 which contains what
was read.

3-12

Table 3-4
Bit( s)

Port

BSEL 7
( applies
only after
Base Table
is assigned)

Modem Status Bit Descriptions (Cont)
Description (If Bit is Set)

Name

Reserved~ Bit condition, don't care.

Program Selected - Used for diagnostic purposes. When set, the modem interface is defined
by other bits in BSEL 7. Used for test purposes
when clear.

9 & 10

Reserved~ Bit condition, don't care.

When set, indicates Integral Modem selected.

When set, indicates V.35 interface selected.

Reserved: Bit condition, don't care.

When set, indicates RS-232-C or RS-423-A interface selected.

When set, indicates RS-422-A interface selected.

3.2.4 Output Commands Overview
Output commands provide a means for the DMR II to report various normal and abnormal (error)
conditions concerning the data transfer operation. Two basic commands are provided:
I.

Receive or Transmit Buffer Addresss/Character Count Out and

Control Out

The Buffer Address/Character Count Out command is used to report a successful, error free. completion of a receive or transmit buffer and indicates the actual number of bytes transferred. This
command utilizes both SEL 4 and SEL 6 to identify the address of the completed buffer and the actual
character count of the transfer.
The Control Out command is used to report specific conditions concerning the DIG ITA L Data Communications Message Protocol (DDCMP), the user program, the hardware. or the modem. Control
Out utilizes SEL 6, as shown in Figure 3-5, to inform the user program as to the nature of the report.
The various conditions are shown below.
•

Error Status

Identifies the reason for the error condition; that is, errors can be associated with the DDCMP,
the user program, modem, or other hardware limitations. In some cases the error condition is
non-fatal and normal operations can continue. Other errors are fatal, causing the DMRll to
shut-down.

3-13

SEL 6
START
RCVD •

: MSG TOO: MAINT:
LONG • I RCVD·

I DISCON I
---+---L-I

I
I

+ __

-L---+-

I HALT

:
TIME
;
NAK
lOUT
I THRES
--L. _ _ -I- _ _ _
•

* = FATAL ERRORS
Figure 3-5

NON

•

I COMPLETE I EX-MEM

NO
BUF

o
MK-2238

Summary of Control Out Status

Oetailed bit descriptions of SEL 6 for Control Out are contained in section 3.4.3.
3.2.4.1 Output Command Handshaking
The OM R II issues output commands in two steps. The data pertinent to the command being issu(~dis
loaded into SEL 4 and 6. Once this is complete. the OM R II sets the Ready Out (ROO) bit and the
command code in BSEL 2. and generates an interrupt through vector XX4 if the lEO bit is set.
Generally. processing an output command involves the following steps:
•

The user program checks for ROO set. This can be done through periodic checking or by
waiting for an interrupt. assuming that interrupts are enabled.

NOTE
I t is strongely recommended that the output interrupt
capability be used to avoid unnecessary delay on the
M8207-RA processor when CSRs are constantly
scanned.

•

To use the output interrupt capability. the user program must set the output interrupt enable
bit in BSEL 2 immediately after it detects that Run bit has been set following Master Clear.
After Base In, lEO must never be changed unless ROI or ROO is set.

•

When a ROO set condition is detected. the user program should read SEL 2. SEL 4. and
SEL 6 into three registers or a storage area and clear ROO in BSEL 2. When ROO is
cleared, the data port (SEL 4 and 6) will be released for more input or output command
processing.

The flow chart in Figure 3-6 illustrates a typical procedure for the user program to implement output
command servicing. The example shown is for interrupts enabled. It also demonstrates user requirements to process each command. This procedure is provided as an example only and should not be
considered as the only method to implement output command servicing.
3.3 INPUT COMMANDS
This section provides detailed descriptions of each input command. Command formats and data port
usages are illustrated and defined in terms of user program execution requirements, command variables, and action taken by the DMR II in response to the command.

3-14

OUTPUT INTERRUPT
SERVICE ROUTINE

NOTE:
THIS FLOW CHART
ASSUMES:
1) lEO IS SET
AFTER MASTER CLEAR.
2) R3, R4, R5 ARE
AVAILABLE FOR USE.

LOG SUPRIOUS
INTERRUPT ERROR

R3 .... (SEL 2)
R4 .... (SEL 4)
R5 .... (SEL 6)
CLEAR ROO IN BSEL 2

001

000
TRANSMIT BA/CC 0

HANDLE THE
SUCCESSFULLY
TRANSMITIED BUFFER
(R4) BUFFER ADDR
(R5) CHAR. COUNT/
BA16, 17

CONTROL OUT

HANDLE THE
SUCCESSFULLY
RECEIVED BUFFER
(R4) - BUFFER ADDR.
(R5) - CHAR COUNT/
BA16,17

YES
(R5 = 10,

20,200,
400,1000)
TAKE APPROPRIATE
ACTION TO CORRECT
ERROR CONDITIONS

- TAKE CORRECTIVE ACTION
- MASTER CLEAR DMR11
- RESTART DMR11

YES

NO
INPUT

INTERRUPT
EXIT
MK-2231

Figure 3-6

Output Command Servicing

3-15

3.3.1 Base In
The Base In command is the only command allowed after initialization. It performs two basic functions:

I.
2.

Assigns a Base Table to the OM R II and
I mplements the Resume feature

The command format for Base In is shown in Figure 3-7. Base In assigns a Base Table of 12810 bytes to
the OM R II, beginning at the address specified in SEL 4. This table remains assigned to the OM R II
until it is initialized or shut-down by the Halt command.
If the Resume bit (SEL 6, bit 12) is asserted by the user program. the OM R II immediately reads the
contents of the Base Table into its random access memory (RAM). At this time. the OM R II also
examines the Base Table for non-existent memory (NXM). If there is a NXM error. the OM R II will
report the error by Control Out/NXM. For additional material concerning Base In with the Resume
feature, refer to section 3.5.2.
NOTE
The user program should not assign the Base Table
at an odd address boundary.

I
I

I
I
I

I
I

I
I
I

I
I

,I
I

I
I

I
,

I
I

SEL 2

4
I

SEL4

BASE ADDRESS HIGH BYTE

BA 17

I
I

I
J.

BA 16

I
~

IRESUME:

I
I

I
I
I
I

SELO

BASE ADDRESS LOW BYTE
I

I
I

BSEL

BASE IN

I
I

SEL6

~_7
___~___
6 __~__
5__~__4__~__3__~__2__~____~___~

MK-2222

Figure 3-7

Base In Command Format

3-16

3.3.2 Control In
This command must be executed following Base In. It provides further definition of the operation by
making specific mode selections in BSEL 7. Command In performs three major functions.

•
•
•

Selects DDCMP Normal or Maintenance Mode,
Selects half-duplex of full-duplex, and
Selects the Start Timer

The command format is shown in Figure 3-8. Table 3··5 lists data port (BSEL 7) bit descriptions for
this command.
I

I
I

I
I
I

0
I

I
I

IDDCMP
I MAINT

I
I

I START I
I TIMER I

SEL2

)

SEL4

)

SELD

I
I

)

I
I
I

CONTROL IN

I
I

BSEl

HDX

.
I

) SEL 6

o
MK·2223

Figure 3-8

Control In Command Format

If selected for DDCMP Normal Mode, the first Control In causes the DMR II to initiate a protocol
start-up sequence and send Start and acknowledge Stack messages. The interval for sending Start
messages can be either one or three seconds and is selected by the user program in Bit 3 of BSEL 7. The
one second timer interval is the default value.
In full-duplex mode, the timer value selection is not critical because Start message collisions on the line
are not possible. In half-duplex mode, however, even though the possibility is slight. Start messages
could be issued by both devices at the same time. With identical time intervals, Stack would never
occur.
To eliminate this remote possibility, the user program can select the three second timer at one end to
offset the interval. In this case, only the first coincident Start message would not return a Stack. The
device set at one second will have priority. This condition is illustrated in Figure 3-9.

3-17

Table 3-5 Data Port Descriptions with Control In
Port

Bit( s)

Function

Description

BSEL7
(Write)

DDCMP
Maintenance

DDCMP Maintenance -- When set by the u ser
program, it causes the microprocessor to enter
the DDCMP Maintenance Mode. It will remain in this mode untilinitialized. When this bit
is "0" the microprocessor will enter DDC~dP
Normal Mode.

Half-Duplex

HDX - When set, half-duplex mode is selected
When cleared by the program, full-dup lex
mode is selected.

Long Start
Timer

When set, a three second Start timer is selected;
when clear, a one second Start timer is selec.ted
( the Start timer is the interval for sending
Start/Stack).

1 & 4-7

Reserved; Bit condition, set to O.

If selected for OOCMP Maintenance Mode, a special OOCMP message format, the maintenance
message, is used for down-line loading, restarting, or otherwise maintaining satellite computer systems. Messages in this format are subject to error checking but are unsequenced, unacknowledged, and
not automatically retransmitted by the microprocessor.
To set the OMR II into Maintenance Mode, the user program must initialize the OM R I I. give it a
Base In with the Resume bit clear, a Control In with the maintenance bit set, and set the half-duplex bit
for HOX or clear for FOX.
In Maintenance Mode the OMR II provides the following functions:
I.

Message framing.

Bit error detection - The header and data block check character (BCC) is checked by the
OMRII. If the BCC is bad, the message is discarded with no notification given to the user
program.

Link management - The OMRII provides proper line turn-around in half-duplex mode.

Some errors are recorded in the OMR II's internal RAM memory and are reported to the
user program by updating the Base Table.

It is the responsibility of the user program to recover from any error via software time outs, since there
is no retransmission attempted in maintenance mode.
3.3.3 Receive Buffer Address/Character Count In (RBA/CCI)
The RBA/CCI allows the user program to assign a receive buffer by giving the OM R II the starting
address of the buffer and the character count in SEL 4 and SEL 6. The DMR II can accept up to 64
receive buffers.

3-18

DMR
(HDX)
1 SEC
TIMER

START
START
START

..-

START

DMR
(HDX)
1 SEC
TIMER

START
START

NO STACK
RETURNED

DMR
(HDX)
1 SEC
TIMER

START
START

START

------ .... \
~STACK

DMR
(HDX)
3 SEC

-/' TIMER

MK-2232

Figure 3-9

Start/Stack Sequence Timer

NOTE
DMCll can only accept a maximum of 7 buffers.
If the Resume feature is to be used, the maximum number of receive buffers is limited to eight. If the
DMR II has more than eight buffers, it will only save up to eight after Resume. For example, if
DMRII has BUF I, BUF 2, .... BUF 20 after a Shutdown/Resume operation, the OMRII will only
retain BUF 1, BUF 2, .... BUF 8. The format for RBA/CCI is shown in Figure 3-10.
The starting address of the receive buffer is contained in SEL 4 and the two most significant bits of
SEL 6. The buffer size is contained in the remaining bits of SEL 6. Buffers range from I to 16,383
bytes. The buffer size should be limited to a practical size large enough to accommodate the longest
message expected. Each buffer corresponds to one OOCMP data message.

NOTE
The user program should give a higher priority to
assigning all receive buffers before it assigns any
transmit buffers. For example, if se)'en receive and
seven transmit buffers are to be assigned, the program should assign all seven receive buffers before
assigning any transmit buffers.
3.3.4 Transmit Buffer Address/Character Count In (TBA/CCI)
The TBA/CCI allows the user program to assign a transmit buffer by giving the OMR II the starting
address of the buffer and the character count in SEL 4 and SEL 6. The OM R II can accept up to 64
transmit buffers.

NOTE
DMCll can only accept a maximum of seven buffers.
If the Resume feature is to be used, the maximum number of transmit buffers is limited to eight. If the
DMRII has more than eight buffers, it will only save up to eight after Resume. For example, if
OMRll has BUF 1, BUF 2, .... BUF 20 after a Shutdown/Resume operation, the OMRII will only
retain BUF I, BUF 2, .... BUF 8. Buffers range from I to 16,383 bytes.

3-19

I
I

BSEL

I
I

I
T

I SELO
2

I
I
I

I SEL 2

I
I
4

BUFFER ADDRESS LOW BYTE

I
I

I
I,

RECEIVE BAiCC IN

I
5

BUFFER ADDRESS HIGH BYTE

I
6

CHARACTER COUNT LOW BYTE

BA17

BA16

ISEL6
7

CHARACTER COUNT HIGH SIX BITS

ISEL4

~_7
___ ~___
6 __~__5__~__4__~__3__~__2__~____~__~
MK-2224

Figure 3-10

Receive Buffer Address/Character Count
In Command Format

The maximum size of the transmit buffer is a factor of the line speed and the reply or selection timer
value. The time (T) required to transmit each buffer should be less than either the reply timer value
(FDX) or the selection timer value (HDX). The user can optimize the buffer size using the following
formula:
T = (Character Count + 20) X 8 or Character = (T X Line Speed) - 20
Line Speed
Count
8
Where:
T = Seconds (should be less than the 3 second REP/Select Timer)
Line Speed = Bits per second (b/s)
Character Count = Number of bytes

Each buffer corresponds to one ODCMP data message. The format for this command is shown in Figure
3-11.
3.3.5

Halt Request Command

The Halt Request command format is shown in Figure 3-12.

3-20

I
I

I
I
I

I
I

SEL 2

I
4

BUFFER ADDRESS LOW BYTE
I
I

I
I

SEL4

BUFFER ADDRESS HIGH BYTE
I

I
I

CHARACTER COUNT LOW BYTE

I
I

SEL 6

CHARACTER COUNT HIGH SIX BITS

BA 17 : BA 16 :
I

I
I
I
I

SELO

I
I

TRANSMIT BAiCC IN

I
I

BSEL

7
I

o
MK-2225

Figure 3-11

Transmit Buffer Address/Character Count
In Command Format

Halt Request allows the user to request a controlled DMRII shut down; that is, in the proper order.
Halt Request is the only formal method used to shut down the OM R.
CAUTION
If the Halt Request command is issued with outstanding transmit buffers, the D M R 11 will abort a
transmission in progress.

The DMR 11 shutdown sequence is as follows:
1.

Clear data terminal ready (DTR). This condition is performed only when a Halt Request
command is issued. It does not occur during a fatal error shut-down.

Return all queued up Control Outs.

Dump the Base Table to local CPU Memory. The DMRll will wait up to three seconds for
data set ready (DSR) to clear, before issuing Control Out with Halt Complete.

Initialize the scratch pads and RAM location 0-400, and reset the M8203 line unit.
Data ports are not used for the Halt Request command.

3-21

I
I

HALT REQUEST

I
I
I

I
I

I
I
I
I
I
I

I
I
I
I

I
I
I

I
I

I
I
I

I
I

I
I
I

I
I
I
I
I

I
I

I
I
I

BSEL

I
I

J
J

I SELO
2

I SEL 2
3

I
I
I
I

I
I

ISEL4

I
I

ISEL6
7

o
MK-2226

Figure 3-12

Halt Request Command Format

3.4 OUTPUT COMMANDS
Output Commands provide a means for the DMRII to report various normal or abnormal (error)
conditions pertaining to the data transfer process. There are two basic commands:
I.

Buffer Address/Character Count Out, which is further categorized into receive or transmit
buffers, and

Control Out.

The Buffer Address/Character Count Out command is used to report normal transfer completions to
the user program. Control Out is used to report abnormal (error) conditions. In either case, if the
Interrupt Enable Out (lEO) bit is set, the DMRII will interrupt the CPU to vector XX4. If the lEO bit
is disabled (0), the user program, by sensing Ready Out (ROO), assumes the responsibility of recognizing that an output command is pending.
When the output command is complete, the user program can execute an Input Command. However,
the DMR II will not recognize an input request until output command servicing is completed.

3.4.1 Receive Buffer Address/Character Count Out (RDA/CCO)
This command is used by the DMR II to report successful completions of receive buffers to the user
program. The format for this command is shown in Figure 3-13.

3-22

I
I

I
j

I
I

I
I
I

I
I

BSEl

I
I

RECEIVE BAICC OUT

i
I

I
I

BUFFER ADDRESS lOW BYTE

4
I

BUFFER ADDRESS HIGH BYTE
l

I
I

-~
I

ACTUAL RECEIVED CHARACTER COUNT lOW BYTE
I

I BA 16 I ACTUAL RECEIVED CHARACTER COUNT HIGH SIX BITS

BA 17
i

o
MK-2227

Figure 3-13

Receive Buffer Address/Character Count
Out Command Format

The address of the completed buffer is contained in SEL 4 and the two most significant bits (MSB) of
SEL 6, while the actual received character count is contained in the remaining bits of SEL 6.
In the normal DDCMP mode, this command indicates that:
•
•
•
•

Cyclic redundancy checks (CRC) are good,
The sequence number is correct,
The protocol requirement checks are good, and·
The data is stored in memory (DMAed).

In DDCMP Maintenance mode, the following is valid:
•
•
•

C R Cs are good,
Protocol requirement checks are good,
Data is stored in memory (DMAed).

3.4.2 Transmit Buffer Address/Character Count Out (TBA/CCO)
This command is used by the DMR 11 to report successful completions of transmit buffers to the user
program. The address of the completed buffer and character count are contained in SEL 4 and SEL 6.

3-23

In normal DDCMP mode, this command indicates:
•

The data was successfully transmitted and

•

An acknowledgement for that message has been received from the remote station.

This command when issued in DDCMP Maintenance mode only indicates:
•

Data was transmitted.

Figure 3-14 illustrates the format for this command.

3.4.3

Control Out

The DMR II informs the user program of unusual or error conditions involving the microprocessor
hardware, user program, physical link, or remote station by means of the Control Out command.
Some error conditions are non-fatal; that is, after taking the appropriate action, such as assigning
more buffers for No Buffer Available, normal data transfer operations may continue. Other 4;!rrOr
conditions are fatal, causing the DMR II to shut down. Fatal errors require the user program to
reinitialize the DMRII. The format for this command is shown in Figure 3-15.
The port (SEL 6) bit descriptions for Control Out are listed in Table! 3-6.
I

I
I

I
I
I

I
I

I
I
I

I
I

,I
I

I
,I

I
I

TRANSMIT BAICC OUT

SEL2

BUFFER ADDRESS LOW BYTE

SEL4

BUFFER ADDRESS HIGH BYTE

I
6

CHARACTER COUNT LOW BYTE
I

I
I

I
I
I
I

SELO

I
I
I

SSEL

I
I
I

SEL6

CHARACTER COUNT HIGH SIX BITS

SA 17 : SA 16 ;
I

7
I

~_7___ ~___
6 __~__
5 __~__
4 __~___3__~___2__~____~__~
MK-2228

Figure 3-14

Transmit Buffer Address/Character Count
Out Command Format

3-24

I
I

I
I
I

I
I

BSEL

CONTROL OUT

I
I
I

I
I

MSG
I
I MAINT I
TOO
I LONG
I RCVD

START I DISCON I
I
RCVD I
I

NO
BUF

I
I

SEL4

)

SEL 6

I TIME f NAK
I OUT I THRES

I
I

I HALT I

NON
COMP I EX-MEM

)

SEL 2

)

I
I

SELO

I
I

)

I
I
I
I
I
I

o
MK-2229

Figure 3-15

Control Out Command Format

3.5 PROGRAMMING TECHNIQUES
This section provides various recommendations and considerations necessary for the user program to
properly interface to the DMRII microprogram.
These considerations are further defined in terms of DDCMP Normal Mode and DDCMP Maintenance Mode. The state diagram in Figure 3-16 shows the relationship of each command to the
DDCMP states.
Specific areas for consideration are summarized below and are explained in detail in subsequent paragraphs.
•
Proper command sequence
•
•

Execution of input commands with the Resume feature
How to distinguish DMRII from DMCII

•

Implementation of DDCMP Maintenance Mode

•
•

Execution of remote load detect
Error detection

3-25

Table 3-6

Data Port Bit Descriptions With Control Out

SEL 6
Bit

Name

Status
Type

Description

NAK
Threshold

Error/NonFatal
(Protocol)

This error is reported when persistent line errors
occur, resulting in protocol NAK to be sent or
received. When consecutive NAK transmissions
or NAK receptions occur, they are counte:d in
their respective threshold counter. When the
threshold value of seven is reached, this error is
reported. Each threshold counter IS cleared
when the threshold is reached or when the operation it is monitoring is performed correctly.

Time Out

Error/NonFatal
(Protocol)

When consecutive REP transmissions occur, they
are counted in the threshold counter. This en'or is
reported when the threshold value of seven is
reached. Each threshold counter is cleared when
the threshold value is reached or when the operation it is monitoring is correctly performed.

No Buffer

Error/NonFatal (User
Program)

This error is reported for the following conditions:

DMR II has received seven NAKs because of
No Receive Buffer Available at the remote end.
There were seven attempts to receive a message
with No Buffer Available.
3

Maintenace
Received

Error Fatal
(Protocol)

A DDCMP Maintenance message format was
received while the DMR II was in DDCMP
Run/Start or ASTRT mode. The message causing this condition is lost and the D M R II is
forced to shut down.

Message
Too Long

Error Fatal
(Program)

A received message or transmitted message is
larger than the assigned buffer (incluuding maintenance messages). The DM R II will have shut
down by the time this error is reported.

Not Used

Disconnect

Error
Non-Fatal
(Modem)

Indicates that an unexpected drop in DSR (EIA
Interface CCITT-I07) was detected.

NOTE
On applications using a switched network via dial-up
modems, the ON-to-OFF transition of DSR could
indicate that the connection has been terminated and
a redial or call set up may be required.

3-26

Table 3-6

Data Port Bit Descriptions With Control Out (Cont)

SEL 6
Bit

Name

Status
Type

Description

Start
Received

Error Fatal
(Protocol)

A protocol Start message was received while the
DMR II was in the DDCMP Run state. The
DMR II will complete shut-down by the time
this error is reported. This error is not reported
when the DMRII is in DOCMP Maintenance
Mode.

NonExistent
Memory
(NXM

Error Fatal
(Program/
Hardware)

A non-existent memory (UNIBUS address time
out) condition has occurred on a receive or
transmit data operation, or a Base Table update/read operation.
The OM R II has completed the shut-down by
the time this error is reported.

Halt
Complete

This condition is reported following completion
of the Halt Request Command or programming
error: that is, a character count of zero on Transmit or Receive BA/CC In, or assigning Control
I n or BA ICC I n before Base In. Refer to section
3.3.5 for the proper shutdown sequence.

10-15

Not Used

Reserved.

3.5. t Input Command Sequence
The sequence in which the user program issues input commands is critical. The following identifies the
proper sequences. The command sequence is listed in Table 3-7. They are shown in the correct order
of program execution.
Initialization is the first function that the program must perform. This action is required to reset both
the OM R II hardware and firmware to the initialized (operational) state.
Base In is the only command that the user can issue following initialization. Any other commands
issued before Base In will cause a procedure error, resulting in a OMR II shut-down. This will require
the program to reinitialize the OM R II.
Control In should be issued following Base In. After issuing Control In, the user program can assign
either receive or transmit buffers to the OM R II. The sequence of issuing one or the other is not
critical, however, the program should give priority to assigning all receive buffers before any transmit
buffers. Halt Request can be issued at any time.
3.5.2 Base In Command with Resume Feature
The Resume feature can be implemented during a Base In by the program setting SEL 6 bit 12.

3-27

MASTER
CLEAR

--.,.---

ISTRT

1 HALT I1-

BASE IN/CON} IN

RECEIVE STRT
RECEIVE STACK

ASTRT

]

'------'

RECEIVE
STRT

RECEIVE STACK
ACK/RESP= 0
DATA MSG/RESP=O

RUN

BASE IN/CONT IN/MAINT

MAINTENANCE

NXM ERROR, STRT RCVD, OLE RCVD,
MSG TOO LONG, HALT COMMAND

NXM
MESSAGE TOO LONG
HALT COMMAND

OLE RCVD

SHUT-DOWN ~--------'

MK-2237

Figure 3-16

DMR II Protocol State Diagram

The proper command sequence to implement a shut-down and then resume. is as follows:
I nput Commands
Halt Request

;shutdown DMR II

Master Clear

;optional (initialized internally by Halt Request)

Base in with Resume set

;resume DMR II

Control In

;To select half-duplex or full-duplex

3-28

Table 3-7

DMRll Command Sequence

Command

Description

Initialization

Master Clears the OM R 11 and places it in the operational state.

Base In

Only command allowed after Master Clear. Assigns the Base
Table to the OM R 11 and prepares for protocol startup.

Control In

Sets OMR 11 in either half-duplex or fullduplex mode and either
OOCMP Normal (Run) or Maintenance Mode. Also establishes
a one or three second Start timer.

Buffer Address/
Character Count In

Assigns receive or transmit buffers. Can assign up to 64 buffers.
All receive buffers should be assigned first.

Halt Request

The Halt Request command can be issued by the user program
at any time to formally shut down the OM R 11.

The Resume feature causes the OMR II to read the Base table content from the CPU memory and
store that data in the OMR II RAM. This information should be the updated Base Table resulting
from the previous shut-down. The information contained in the Base Table will determine whether the
OMRII will Resume operation in the Run, ISTRT, ASTRT or Maintenance State; that is, protocol
start up is not required. However, if the remote end has abandoned the process due to protocol time
out, it will be necessary to reinitialize.
Buffers assigned to the OMRII prior to shut-down (up to a maximum of eight receive and eight
transmit buffers) will still be assigned when the operation resumes. I f there are more than eight outstanding receive or transmit buffers, they will be lost.

NOTE
During shut-down and subsequent Base In
with Resume, the Base Table must NOT be
altered. If modified, the DMR 11 could resume in an undefined state.

To use this feature, the number of transmit or
receive buffers must be less than eight each.

Whenever the Base Table is written to or read
from main memory, resulting from a shutdown or Resume operation, 64 back to back
DMAs (5-10 microseconds apart) are execued
to transfer the Base Table. Therefore the user
must be aware of the effect of the high rate of
DMAs on the rest of the system.

3-29

3.5.3 Distinguishing DMRll from DMCll
I f the user program needs to determine if it is interfacing with a D M C II or a D M R II. The user
program can execute the procedure listed below as part of the initialization sequence.
1.

Load any number (except Is, 2s, 100s or 200s) into BSEL 3,

Set Master Clear bit (with or without microdiagnostics enabled),

Wait for the RUN bit (maximum of 6.4 ms), and

Check BSEL 3.
The unit is a DMRII if BSEL 3 contains either Is, 2s, 100s, or 2008.
NOTE
If the microdiagnostic is disabled, BSEL 3 will contain 1008 (Test Inhibited). If enabled, BSEl, 3 will
contain 18, 28, or 200s.
The unit is a DMCII if BSEL 3 contains the same number that was written in step I.

3.5.4 DDCMP Maintenance Mode Operation
Maintenance Mode provides the mechanism to implement down-line program loading or restarting/maintaining satellite computer systems via remote load detect (R LD). I n this mode, a special
message format (maintenance message) is used to execute this feature. Messages in this format are
subject to error checking but are unsequenced (not numbered), unacknowledged, and not automatically retransmitted by the microprocessor. Because of this, it is necessary for the user program to
recover from any error conditions by utilizing time outs to retransmit the message.
To enter the DDCMP Maintenance Mode, the DMR II must be initialized and issue a Base In with the
Resume bit cleared, followed by the Control In with the Maintenance bit (SEL 6, bit 8) set.

3.5.4.1 Data Transfer - Once in DDCMP maintenance mode, maintenance messages can be sent and
received like data messages. On transmission, the data portion of the message is taken from the assigned
buffer with the DMRll generating the header and CRCs. On reception, only the data portion is plaeed in
the available assigned buffer. Messages not in DDCMP maintenance format, having incorrect CRCs or no
receive buffers are simply discarded.
When operating in conformance with MOP, the DM R II must be operated in a single buffered manner, causing a line turnaround after each message is transmitted. When a host computer wishes to
restart a satellite computer system, it must send the appropriate MOP messages as described in section
3.5.4.2.

3.5.4.2 Unattended System Control- Unattended system control ( down-line load! remote load detect)
is accomplished using the maintenance operation protocol (MOP), version 2.0. There are two basic
considerations when using MOP: down-line load (originating station) to remote end and remote {boot
station) request for down-line load.
The Enter MOP Mode message is used to control an unattended satellite system. This messag4!, together with the appropriately configured hardware, causes the DM R II to stop current operations,
forcing the computer to transfer control to a resident MOP program or bootstrap.

3-30

Whenever the microprocessor is running, it constantly scans the line for a DDCM P maintenace message (DLE) containing an Enter MOP Mode data field.
The data portion of this message contains five bytes. The first byte contains the number code six. The
remaining four bytes contain the password, which must match the password assigned to the line unit.
All four passwords must be the same.
In order to execute down-line load to the remote station, the following conditions must be true:
I.

The password Switch Pack (E 134 on the line unit) is NOT set to 3778.

All four passwords in the Enter MOP Mode message match the password selected by Switch
Pack E 134 on the M8203 line unit (except 377).

The data eRC for the ENTER MOP message is good.

Once these conditions are satisfied, the DMR II will write via direct memory access (DMA) I73XXX
into memory location 24 and zero to location 26 followed by pulling AC La to initiate a power up
recovery. The power up recovery causes the CPU to transfer control to a primary MOP program
residing in a boot module such as the M93I2 with the D ECN ET boot RO M at location 17 3XXX. The
designation XXX is the content of the boot offset which is selected by the offset Switch Pack E 121 on
the M 8203 line unit. (switches 1-8).
If any of the three conditions are not satisfied, the DM R II will treat the Enter MOP mode message as
specified in Table 3-8.
Figure 3-17 illustrates the procedure for remote load detect and the required handshakes to execute
this feature. This procedure assumes that the remote device is configured for the appropriate password
and offset to implement the bootstrap feature.

Table 3-8

Invalid Enter MOP Message Response

Condition

Action

DMR II in Halt or
Initialized mode

No action taken.

DMRII in Run, ISTART
or ASTART mode

D M R II will enter the Halt state and noti fy the program that
a maintenance message (DLE) was received.

DMRII in Maintenance
Mode

If a receive buffer is available and the message contairys a
CRC error, the message will be discarded and the error
counter incremented.

3.6 BASE TABLE COUNTERS
After Base In and Control In are issued by the software, DMR II will periodically update the internal
counters from its RAM location 2 through 42 (see Figure 3-18) to the Base Table assigned. These
cumulative error counters start at 0 and wrap around back to 0 when the maximum count is reached.
These counters are updated approximately every second.

3-31

l-INITIALIZE DMRll
2-BASE IN TO DMRl1
3-CONTROL IN TO DMRll WITH SEL 6 = 2400
4-BAiCCi FOR RECEIVE WITH CHARACTER
COUNT OF 256
5-BA/CCI FOR TRANSMIT WITH CHARACTER
COUNT OF 5. TRANSMIT BUFFER IN PDP-ll
MEMORY SHOULD LOOK LIKE 6 0 0 0 0
(4 PASSWORD THAT = 0)
SEE NOTE 1

SERIAL
LINE

DMRll #1

SOF-TWARE AT HOST

I
I
I
I
I
I
I

I
1-TRANSMIT ENTER MOP
MESSAGE
2-DO A BA/CCO ON TRANSMIT
DONE

IMAGE DATA LOADED = X BYTES
TRANSFER ADDRESS (4 BYTES) = 6
TRANSFER ADDRESS (4 BYTES) = 0
TRANSFER ADDRESS 14 BYTES) = 0
TRANSFER ADDRESS (4 BYTES) = 0
4-SEE NOTE 1

I
I
I

DLE
MOP6
~

SEE NOTE 2

I
I

I
I
DO A BA/CCO RECEIVE TO PDP-ll I.-.

DLE
MOP8

l-TRANSMIT REQUEST SECONDARY
BOOT MESSAGE (MOP 8)
2-DO A BA/CCO TRANSMIT

PROGRAM CONTROL IS PASSED TO DMRll
BOOT CODE WHICH DOES THE FOLLOWING.
l-INITIALIZE DMR11
2-BASE IN TO DMRl1
3-CONTROL IN TO DMR11 WITH SEL6 = 2400
4-BA/CCI FOR RECEIVE WITH A CHARACTER
COUNT OF 4092
5-BA/CCI FOR TRANSMIT WITH CHARACTER
COUNT OF 4. TRANSMIT BUFFER IN PDP-l1
MEMORY SHOULD BE 10, 14, 1, 0
(MOP 8: REQUEST SECONDARY BOOT)
6-SEE NOTE 1

I
I
I

I
I
I
I
I
I
I

I
I
I
I
I

1-CHECK FIRST BYTE = 6
2-COMPARE PASSWORD (PWD)
RECEIVED WITH PWD SELECTED IN LINE UNIT SWITCH PACK Ei 34
3-IF ALL 4 PWD's MATCH, DMA
THE FOLLOWING TO PDP-ll
MEMORY 24/174XXX, 26/0
XXX = LINE UNIT. SW PACK El2l
4-PULL AC LO ON UNIBUS

I
1-CHECK VALIDITY OF REQUEST SECONDARY
BOOT MESSAGE RECEIVED
2-DO A BA/CCI RECEIVE WITH CHARACTER
COUNT OF 256.
l..3-DO A BA/CCI TRANSMIT WITH CHARACTER
COUNT OF (X + 12). THE TRANSMIT
BUFFER CONTAINS MOP 0 MEMORY LOAD
WITH TRANSFER ADDRESS AS FOLLOWS:
CODE (l BYTE) = 0
LOAD NUMBER (1 BYTE) = 0
LOAD ADDRESS (4 BYTES) = 0
0
0
0

I
i

DMRll BOOT CODE IN BOOT ROM
(M9301-YJ/M9312)

DMRll #2

I
I

I
DLE
MOPO

1-TRANSMIT MOP 0 (MEMORY
LOAD WITH TRANSFER
ADDRESS)

2-DO A BA/CCO TRANSMiT

DO A BA/CCO RECEIVE TO
PDP-ll

NOTES·
1) IN DDCMP MAINTENANCE, THERE IS NO RETRANSMISSION;
BA/CCO FOR A TRANSMIT OPERATION DOES NOT ASSURE
SUCCESSFUL RECEPTION AT THE REMOTE END. THE SOFTWARE
MUST KEEP A REPLY TIMER OF 3 SECONDS TO RETRANSMIT THE
MESSAGE WHEN NO REPLY IS RECEIVED WITHIN THAT TIME
2) XXX MUST BE THE OFFSET
FROM 173000 OF THE
DMRll BOOT CODE IN M9301-YJ/M9312

Figure 3-17

Down-Line Load Procedure to Remote Station

I
I

1-VERIFY MOP CODE = 0 AT LOCATION 0
THEN DO A SYSTEM RESET
2-JUMP TO LOCATION 6 TO PASS
PROGRAM CONTROL TO NEWLY
LOADED PROGRAM

BASE
TABLE
ADDRESS

BASE TABLE ALLOCATION
iNAME
i----

000000
000001
000002

i
UPINDX
UPLMT
BASTBL

,. ., BASE TABLE UPDATE INDEX POINTER

000003
000004
000005

NRNBF
NRHCE
NRDCE

BUFFER TEMP UNAVAILABLE (REASON =
i @ NAKS RCVD
(REASON
i@ NAKS RCVD - HEADER BCC ERROR
(REASON =
DATA BCC ERROR
i@ NAKS RCVD

i 1 BASE TABLE UDPATE LIMIT
i# BEGINNING OF BASE TABLE DATA

(ALWAYS

000)
8. )
1. )
2. )

** --- IN DDCMP MAINTENANCE MODE THESE
IN-BOUND ERRORS ARE RECORDED BUT
NO NAKS ARE SENT.
000006
000007
000010

NSNBF
NSHCE
NSDCE

8. )
i @ NAKS SENT
BUFFER TEMP. UNA VA I LAB LE
fREASON
;@ NAKS SENT - HEADER BCC ERROR
(REASON
1. )
**
2. ) **
CREASON
i@ NAKS SENT - DATA BCC ERROR

000011
000012

RST
RRCV

i@ REPS SENT - CUMUL REP SENT.
i@ REPS RCVD - CUMUL REP RCVD.

000013
000014
000015
000016

NRREP
NRROV
NRHFM
NRMTL

i# NAKS RCVD - REP RESPONSE
RCV OVERRUN
i # NAKS RCVD
it NAKS RCVD - MSG HDR FORMAT
MSG TOO LONG
i # NAKS RCVD

CREASON = 3. )
9. )
fREASON
(REASON
17. )
CREASON = 16. )

000017
000020
000021

NSREP
NSROV
NSHFM

i # NAKS SENT - REP RESPONSE
i # NAKS SENT - RCV OVERRUN
it NAKS SENT - MSG HDR FORMAT

(REASON
(REASON
(REASON

000022

XUNDR

i# XMIT UNDERRUN COUNT.

000023

CFAIL

i# CALL SET UP FAILURE COUNT.

000024

CTSCNT

i# CTS FAILURE COUNT.

000025

CDLCNT

i# CARRIER DETECT LOST COUNT
if (WHILE RECEIVING)

000026

RCVIDL

i# RECEIVER INACTIVE COUNT.

000027

STRCNT

it STREAMING TIME-OUT COUNTER

000030

XMBYT

000034

RCBYT

it TOTAL NUMBER OF BYTES TRANSMITTED.
i' .INCLUDING RETRANSMISSION, 32 BIT
if COUNTER)
if TOTAL OF BYTES RECEIVED. tNOT
if INCLUDING DUPLICATE OR OUT OF
if SEQUENCE, 32 BIT COUNTER)

000040
000041

ICSEL
NRSEL

i' INCOMPLETE SELECTION COUNTER
if NO REPLY TO SELECTION COUNTER

Figure 3-18

DMR II Base Table Error Counters

3-33

3. )
9. )
17. )

**
**

3.7 MODEM CONTROL
There are two levels of modem control available in the OM R II. The first level is provided by the
M8203 hardware and the second is provided by the OMR II microcode.
Modem Control Implemented in M8203

3.7.1

3.7.1.1 Modem Ready Lockout of RTS - Bit 3 of line unit Register 13 is data mode (modem ready) or
data set ready (Circuit EIA CC/CCITT-107). Unless modem ready is asserted by the modem, M8203
will not present request to send (Circuit EIA CA/CCITT-I05) to the modem.
3.7.1.2 Half Duplex Mode - Bit 4 of line unit Register 13 is the half-duplex bit: if set, it indicates that
the line unit is set in the half-duplex mode. In half-duplex mode, there is hardware interlock to prevent
the line unit from transmitting and receiving simultaneously. While the receiver is actively receiving or
carrier detect is asserted, the data loaded into the transmit silo will not be loaded into the USY RT for
transmission and therefore RTS will not be presented to the modem. Similarly, while the transmitter is
transmitting, the receiver is disabled from receiving data.
NOTE
This hardware interlock will prevent the M8203 line
unit from being used in half-duplex mode on a fullduplex modem, with the continuous carrier option installed.
3.7.2

Modem Control Implemented in DMRII Microprogram

3.7.2.1 Auto-Answer - When the DMRII is installed on a switched line, Switch Pack EI34 switch 9
should be placed in the OFF position. This enables the DMRII to monitor RI and DSR, utilizing a 20
second timer to answer and control incoming calls. With the switch in the ON (auto-answer disable)
position, the DMR II asserts DTR immediately following system initialization or Master Clear, allowing the DMRII to answer an incoming call. The call, however, is not terminated until the user program issues a Halt Request or the remote end terminates the call.

NOTE
The ON to OFF transition of RI starts the
DMRll 20 second timer. For the auto-answer
feature to be affective, the "Ring Indicator
Constantly ON after Call" option on the
modem must not be installed.
Asserting DTR after Master Clear is required
to maintain compatibility with DMCll.

When the auto-'answer feature is enabled, and when RI is detected, the DMRII takes the appropriate
action as described below:
I.

Before Base In/Control In (Remote Load Detect Enabled)
Remote load detect is enabled when the bootstrap password is not 377. When the DMRII
detects the ON to OFF transition of RI, it starts a 20 second timer. If a valid Enter MOP
message is not recieved before the timer expires, the DMRII drops DTR and waits up to
two seconds for DSR to clear before asserting DTR again for the next call. The number of
call set up failures are counted in the CFAIL error counter.

3-34

NOTE
If RI is not asserted by the modem on an incoming
call and the modem sets DSR, the DMRll starts the
20 second call set up timer.
2.

Before Base In/Control In (Remote Load Detect Disabled)
Remote load detect is disabled when the bootstrap password is 377. When the DMRII
detects RI, it drops DTR to disconnect the incoming call.

After Base In/Control In
When the DMRII detects RI, it asserts DTR and starts a 20 second timer. If the DMRII
does not receive a valid DDCMP header and DSR before the timer expires, it drops DTR
and waits up to two seconds for DSR to clear before asserting DTR again for the next call.
The number of call set up failures are counted in the CFAIL error counter.

3.7.2.2 Data Set Ready Glitch - In ISTRT, ASTR T, Run, or Maintenance M ode, once the D M R II
has received data set ready (Circuit CC/I07), any DSR drop is reported by the DMRII to the user
program via a Control Out/Disconnect Error. It is not a fatal error. When the DMRII drops DTR on
a call set up time out, the DSR drop is not reported by Control Out.

3.7.2.3

RTS - CTS Delay - Any time the DMR II attempts to transmit by presenting RTS (Circuit
CC/ 105) to the modem, it will wait up to two seconds for CTS (Circuit CB/ 106) to be returned. I f the
two second time out occurs, the DM R II will increment a CTS Fail Counter in its memory. If D M R II
is not in the Halt state, this counter will be updated to the Base Table in PDP-II and VAX-II /780
memory.
NOTE

DMR II exits from the HALT state after the user
program has issued Base I n and Control In.
3.7.2.4

Loss of Carrier Detect - Whenever Carrier Detect (Circuit CF/ I 09) is dropped by the modem
for greater than 500 ms while the DMRII is still receiving, the carrier detect lost counter in DMRII
memory will be incremented. If DM R II is not in the Halt state, then the error counter in the Base
Table will also be updated.

3.7.2.5

Receiver Inactive Check - In ISTRT, ASTRT, Run, or Maintenance states, the following

receiver inactive checks are made:
•

In full-duplex mode, if a valid message header, including SOH, ENQ or DLE, has not been
received in 20 seconds, a receiver inactive counter is incremented.

•

In half-duplex mode, if the total selection interval time, before a valid DDCM P header is
received, is about 20 seconds, the receiver inactive counter is incremented.

3.7.2.6

Modem Status Read During Input Command - This feature provides the user program with the
option of reading (monitoring) modem status. Modem status is updated by the DM R II to SEL 4 and
BSEL 6 each time RDI is asserted in response to RQI. Refer to section 3.2.3.2 for details on this
feature.

3-35

3.7.2.7

Data Terminal Ready Control - The DMRll microcode controls the data terminal ready

signal as follows:
I.

DTR is set when:
a.

Master clear is performed,

Auto-Answer (E134 switch 9 OFF) is enabled and the DMRII detects RI, or

The user issues Control In.

DTR is cleared when:
a.

The system powers down,

The user issues Halt Request, or

The 20 second call set up timer expires.

NOTE
If the link is established (DSR asserted) and auto-

answer is enabled, the DMRll drops DTR in 20 seconds following Master Clear (provided that Base
In/Control In are not issued).

3.8 DMRII DATA LINK FUNCTIONS
The OM R 11 implements OOCM P and provides a number of functions to the user during what is
referred to as a session. A session is defined as that period beginning immediately after the user assigns
Base In and Control In and ending when the user issues a Halt Request or a fatal error occurs. forcing
the OMR 11 to shut down.
The functions that are provided during each of these sessions are listed below:
I.

Creates an error-free data path. OM R II transfers data between protocol users over a physical link. while maintaining data integrity within some small undetected error probability.

Transfers messages in proper sequence. Messages will be delivered from one user to the
other in the same order as they are sent. even though the OM R II may require the use of
retransmission for error recovery.

Manages the characteristics of the channel. If the channel requires arbitration of transmission requests. the OMR II is responsible for that management.

Interfaces to modem control signals. The OM R II interfaces with signals necessary for the
operation of the physical channel.

Accesses data in blocks consisting of byte quantities. The OM R II accepts data in blocks
consisting of 8-bit bytes. All 256 8-bit combinations are transmittable and transparent to
OOCMP. However, the CRC-16 error detection polynomial used is most effective with
blocks up to 4093 bytes long.

3-36

Provides restart or initialization notification. I f the other end of the link resets or initializes.
the OM R II will notify the user.

Provides start and stop control. The user controls the protocol and can start (or reinitialize).
and stop (or halt) the operation of the OM R II.

Provides notification of channel error. When a persistent error is detected. the user is notified of such a condition. Such errors might be (a) a high bit error rate: (b) outages: (c)
nonexistent communications; or (d) modem failure.

Provides a maintenance mode. The OM R II creates a data envelope with bit error-detectiononly capability for use in diagnostic testing and system bootstrapping functions.

NOTE
In order to recol'er· from the premature termination
of a session, forcing OM R 11 to shut down, by a
hardware or modem failure, the user should implement higher lel'el protocols to ensure synchronization
of the two communicating del' ices between sessions.
Since the 0 M R 11 or 0 OeM P guarantees these
functions within each session only, it is the user's responsibility to implement a higher lel'el protocol in
order to prol'ide an additional lel'el of error reCOl'ery,
guaranteed delil'ery, and sequentiality.

3-37

APPENDIX A
FLOATING DEVICE
ADDRESSES AND VECTORS

A.I FLOATING DEVICE ADDRESSES
UNIBUS addresses starting at 760010 and continuing through 763776 are designated as floating device
addresses (see Figure A-I). These are used as register addresses for communications (and other) devices interfacing with the PDP-II and VAX-I 1/780.
NOTE
Some devices are not supported by VAX-II/780,
however, the same scheme applies; that is, gaps are
provided as appropriate. The convention for assigning these addresses is as follows:
Floating CSR Address Devices
Rank

Option

DJII
DHII
DQII

2
3
4
5
6
7
8
9
10
II
12
13
14

DUll
DUPII
LKIIA
DMCII/DMRII
DZII * and DZVII
KMCII
LPPII
VMV21
VMV31
DWR70
RLII and RLVII

Decimal
Size

Octal
Modulus

4
8
4
4
4
4
4
4
4
4
4
8
4
4

10
20
10
10
10
10
10
10
10
10
10
20
10
10 (extra only)

A gap of 109 must be left between the last address of one device type and the first address of the next
device type. The first address of the next device type must start on a module 109 boundary. The gap of
109 must also be left for devices that are not installed but are skipped over in the priority ranking list.
M ultipie devices of the same type must be assigned contiguous addresses. Reassignment of device
types already in the system may be required to make room for additional ones.
• DZ 11 E and DZ 11 F are dual DZ 11 s and are treated by the algorithm as two DZ II s.

A-I

777 777

2K
WORDS

DIGITAL EQUIPMENT
CORPORATION
(FIXED ADDRESSES)

DR11-C

770000
767 777

't"

WORDS

USER ADDRESSES

764000
763 777

t
1K
WORDS

FLOATING ADDRESSES
DIGITAL EQUIP CORP (DIAGNOSTICS)

760010
760006
760000
757 777

001 000
000 777
80

VECTORS

FLOATING VECTORS

000 300
000277

48
VECTORS

TRAP & INTERRUPT
VECTORS

000000
MK·2190

Figure A-I

UNIBUS Address Map

A.2 FLOATING VECTOR ADDRESSES
Vector addresses, starting at 300 and proceeding upward to 777, are designated as floating vectors.
These are used for communications (and other) devices that interface with the PDP-II and VAX11/780.
NOTE
Some devices are not supported by VAX-II /780,
however, the same scheme applies. Vector size is determined by the device type.
.
There are no gaps in floating vectors unless required by physical hardware restrictions (in data communications devices, the receive vector must be on a zero boundary and the transmit vector must be on
a 48 boundary).
Multiple devices of the same type would be assigned vectors sequentially. The following chart shows
the assignment sequence.

A-2

Flo'ating Interrupt Vector Devices
Rank

Option

DC11
KL11(extra)
DL11-A(extra)
DL11-B(extra)
DP11
DM11-A
DN11
DM11-BB
DH II modem control
DRII-A
DR11-C
PA611(reader)
PA611(punch)
LPDl1
DT11
DXl1
DLI1-C
DL11-D
DLI1-E
DJ11
DHII
GT40
LPSII
DQl1
KW11-W
DUll
DUPl1
DV11
DV modem control
LK 11-A
DWUN
DMCll/DMRll
DZll
KMCl1
LPPl1
VMV21
VMV31
VTVOI
DWR70
RLl1/RLVl1
RX02
TSII
LPAII-K
IPII/IP300

2
2
2

3
4
5
6
6
7
8

9
10
11
12
13
14
14
14
15
16
17
18
19
20
21

22
23
24

25
26
27
28
29
30
31
32

33
34

35
36
37
38
39

Decimal
Size

Octal
Modulus

4
4
4
4
4
4

10
10·
10·
10
10
10·
4
4
4
10·
10·
10·
10·
10
10·
10·
10·
10·
10·
10·

2
2

2
4
4

2
2
4
4
4
4
4
4
4
4
8
12
4
4
4
4
4

lOt
10
30·

lOt

4
4
4
4
4
4
4
4

10
10·
10·
10·
4
10
10
10·
10·
10
10
10
10

:I:

2
2

2
4
2

10·
4
4
4 (after the first)
10
4

• The vector for the device of this type must always be on a lOs boundary.

t These devices can have either a M7820 or M7821 interrupt control module. However, it should
always be on a lOs boundary.
:I: To be determined.

A-3

A.3

EXAMPLES OF DEVICE AND VECTOR ADDRESS ASSIGNMENT

Example I
The first device requiring address assignment in this example is a DH II (Number two in the device
address assignment sequence; Number 16 in the vector address assignment sequence).
The only devices used are:
2
2
I
I
Device
(Option)

OH lIs
OQlls
OUPII
OMRII
Device
Address

Vector
Address

760010

Comment
Gap left for OJ II (one on device address assignment sequence) which is not used

OHII

760020

300

First OH II

OHII

760040

310

Second OH II
Gap between the last OH II used and the next
device

760060
OQII

760070

320

First OQ II

OQII

760100

330

Second OQII

OUPII

OMRII

760110

Gap between the last OQ II used and the next
device

760120

Gap left for OU II s not used

760130

340

Only one OUPlI

760140

Gap left between OUPII and next device

760150

Gap left for LK II-As not used

760160
760170

350

Only one OMRII
Gap left after the last device (in this case, the
OM R II) to indicate that none follow

A-4

Example 2
The only devices used in this example are:
I
I
2
2
2

OJII
OHII
OQlls
OUPlls
OMRlls

Device
(Option)

Device
Address

Vector
Address

Comment

OJII

760010

300

Only one OJ II

OHII

760020

Gap left between OJ II and the next device

760030

Gap - The next device, OH II, must start on an
address boundary that is a multiple of 20

760040

310

Only one OH II

760060

Gap left between OH II and next device

OQII

760070

320

First OQ II

OQII

760100

330

Second OQII

760110

Gap left between OQ II and next device

760120

Gap left for OU lis not used

OUPII

760130

340

First OUPII

OUPII

760140

350

Second OUPII

760150

Gap left between the last OUPII and next device

760160

Gap left for LK II-As not used

OMRII

760170

360

First OMRII

OMRII

760200

370

Second OMRII

760210

Gap left after the last device (in this case the
OMRll) to indicate that none follow

A-5

Example 3
Only one of each of the following devices are used in this example:
DCII
DJ11
DHII
GT40
DQII
DUPII
DMRII
DMCll
Device
(Option)

Device
Address

DCII
DJII

DHII

760010

Vector
Address

Comment

300

DC II has a fixed device address

310

Only one DJ II

760020

Gap left between DJ II and the next device

760030

Gap - The next device, DH II, must start on an
address boundary that is a multiple of 20

760040

320

Gap left between DH II and next device

760060
GT40
DQII

DUPII

760070

Only one DH II

330

GT40 has a fixed device address

340

Only one DQ II

760100

Gap left between DQ II and next device

760110

Gap left for DU II s not used

760120

350

Only one DUPI)

760130

Gap left between DU P II and the next device:

760140

Gap left for LK II-As not used

DMRII

760150

360

Only one DMRII

DMCII

760160

370

Only one DMCII

760170

Gap left after the last device (DMC II) to indicate that none follow

A-6

APPENDIX B
DDCMP IN A NUTSHELL

B.I DDCMP
DDCMP (DIGITAL Data Communications Message Protocol) was developed to provide full-duplex
message transfers over existing standard hardware.
B.I.I Controlling Data Transfers
The DDCMP message format is shown in Figure B-1. A single control character is used in a DOCM P
message and is the first character in the message. Three control characters are provided in DDCM P to
differentiate between the three possible types of messages:
SOH - data message follows
ENQ - control message follows
DLE - bootstrap message follows
Note that the use of a fixed-length header and message size declaration obviates the requirement for
extensive message and header delimiter codes.

SOH

DATA
CRC-2
COUNT FLAG RESPONSE SEQUENCE ADDRESS CRC-1
(ANY NUMBER OF a-BIT
16 BITS
16 BITS
a BITS
a BITS
14 BITS 2 BITS a BITS
CHARACTERS UP TO 214)

MK-2248

Figure B-1

DDCMP Data Message Format

Figure B-2 shows an example of a data exchange.
B.I.2 Error Checking and Recovery
DDCM P uses a 16-bit cycle redundency check (CRC-16) for detecting transmission errors. When an
error occurs, ODCMP sends a separate negative acknowlege (NAK) message. DDCMP does not
require an acknowledgement message for all data messages. The number in the response field of a
normal header or in either the special NAK or acknowledge (ACK) message specifies the sequence
number of the last good message received. For example, if messages 4, 5, and 6 have been received
since the last time an acknowledgement was sent and message 6 is bad, the NAK message specifies
number 5 which says "messages 4 and 5 are good and 6 is bad." When DDCM P operates in full-duplex
mode, the line does not have to be turned around; the NAK is simply added to the sequence of
messages for the transmitter.

B-1

DMR #1

(2) SENDS A STRT (START) MESSAGE WHICH

MEANS: "I WANT TO BEGIN SENDING DATA
.... -- -TO YOU AND THE SEQUENCE NUMBER OF MY
FIRST MESSAGE WILL BE 1."

-0

DMR #2
SENDS A STRT (START) MESSAGE WHICH
MEANS: "I WANT TO BEGIN SENDING DATA
TO YOU AND THE SEQUENCE NUMBER OF MY
FIRST MESSAGE WILL BE 1."

RECEIVES STRT MESSAGE.

~ SENDS A STACK (START ACKNOWLEDGE)

\::.J MESSAGE WHICH MEANS: "OK WITH ME:."

RECEIVES STACK.
SENDS DATA MESSAGES WITH A RESPONSE FIELD
SET TO 0 AND THE SEQUENCE FIELD SET TO 1.
WHICH MEANS: "I AM LOOKING FOR YOUR
MESSAGE 1." OTHER MESSAGES MAY BE SENT
AT THIS TIME (I.E., MESSAGES 2, 3, ETC.)
WITHOUT WAITING FOR A RESPONSE.

-----------.. f7\ RECEIVES DATA MESSAGE 1 AND CHECKS IT FOR
\..:J SEQUENCE AND CRC ERRORS. IF THERE IS A

SEQUENCE ERROR, GO TO 12. IF THERE IS NO
ERROR, GO TO 9.

f'8\ A CRC ERROR WAS DETECTED. COMPUTI:R B

\:.J SENDS A NAK MESSAGE WITH THE RESPONSE

FIELD SET TO O. WHICH MEANS: "ALL MI:SSAGES
UP TO 0 (MODULO 256) HAVE BEEN ACCEPTED
AND MESSAGE 1 IS IN ERROR."

/
COMPUTER A RECEIVES NAK, RETRANSMITS.
MESSAGE 1 AND ANY OTHER MESSAGES SENT
SINCE (I.E., 2, 3, ETC.) IF ALREADY SENT.

@ RECEIVES ACK AND RELEASES MESSAGE 1.

-----.

f1O\ SENDS ACK RESPONSE OF 1 EITHER IN A

_____ ~ SEPARATIE ACK MESSAGE OR IN THE RESPONSE
...-FIELD OF A DATA MESSAGE.

@CONTINUES SENDING MESSAGES.

t;3\ DISCARD MESSAGE AND WAIT FOR PROPER

________ '-:J MESSAGE 2.

@ TIMES OUT DUE TO LACK OF RESPONSE
FOR MESSAGE 2. SENDS A REPLY FOR
MESSAGE 2.
_______

~ f15\ SEND NACK RESPONSE OF '1 IN THE

_ _ _ _ _ '-::J RESPONSE FIELD.

f16\ RETRANSMITS MESSAGE 2 AND

"-:::J FOLLOWING MESSAGES

MK2250

Figure 8-2

DDCMP Sample Handshaking Procedure

B-2

When a sequence error occurs in OOCMP, the receiving station does not respond to the message. The
transmitting station detects, from the response field of the messages it receives (or via timeout), that
the receiving station is still looking for a certain message and sends it again. For example, if the next
message the receiver expects to receive is 5, but receives 6 instead, the receiver will not change the
response field (which contains a 4) of its data messages. The receiver will say, HI accept all messages up
through message 4 and I'm still looking for message 5.'~

B.l.3 Character Coding
OOCMP uses ASCII control characters for SYN, SOH, ENQ and OLE. The remainder of the message, including the header, is transparent.
B.l.4 Data Transparency
DDCMP defines transparency by use ofa count field in the header. The header is ofa fixed length. The
count in the header determines the length of the transparent information field, which can be from 0 to
16,383 bytes long. To validate the header and count field, it is followed by a CRC-16 field; all header
characters are included in the CRC calculation. Once validated, the count is used to receive the data
and to locate the second CRC-16, which is calculated on the data fidd. Thus, character stuffing is
avoided.
B.1.5 Data Channel Utilization
DDCMP uses either full-duplex or half-duplex circuits at optimum efficiency. In the full-duplex mode,
DDCMP operates as two independent one-way channels, each containing its own data stream. The
only dependency is the acknowledgements which must be sent in the data stream in the opposite
direction.
Separate ACK messages are unnecessary, reducing the control overhead. Acknowledgements are simply placed in the response field of the next message for the opposite direction. If several messages are
received correctly before the terminal is able to send a message, all of them can be acknowledged by
one response. Only when a transmission error occurs, or when traffic in the opposite direction is light
(no data message to send), is it necessary to send a special NAK or ACK message, respectively.
In summary, OOCMP data channel utilization features include:
I.

The ability to run on full-duplex or half-duplex data channel facilities,

Low control character overhead,

No character stuffing,

No separate ACKs when traffic is heavy; this saves on extra SYN characters and intermessage gaps,

Multiple acknowledgements (up to 255) with one ACK, and

The ability to support point-to-point and multipoint lines.

B.2 PROTOCOL DESCRIPTION
DDCMP is a very general protocol; it can be used on synchronous or asynchronous, half-duplex or
full-duplex, serial or parallel, and point-to-point or multipoint systems. Most applications involving
protocols are half-duplex or full-duplex transmission in a serial synchronous mode; that operating
environment will therefore be emphasized in this description.

B-3

The header is the most important part of the message, because it contains the message sequence
numbering information and the character count, the two most important features of DDCMP. Because of the importance of the header information, it merits its own CRC block check, indicat(~d in
Figure B- 3 as eRC 1. Messages that contain data, rather than just control information, have a second
section which contains any number of 8-bit characters (up to a maximum of 16,363) and a second eRC
(indicated in Figure B-3 as CRC 2).
Before the message format is discussed in greater detail, the message sequencing system should be
explained because most of the header information is directly or indirectly related to the sequencing
operation.
In the DDCMP, any pair of stations that exchange messages with each other number those messages
sequentially starting with message number 1. Each successive data message is numbered using the next
number in sequence, modulo 256. Thus, a long sequence of messages would be numbered
1,2,3, ... 254,255.,0,1, ... The numbering applies to each direction separately. For example, station A
might be sending its messages 6,7,8 to station B, while station B is sending its messages 5,6,7 to station
A. Thus, in a multipoint configuration where a control station is engaged in two-way communication
with 10 tributary stations, there are 20 different message number sequences involved - one sequence
for messages from each of the 10 tributaries to the control station and one sequence for messages from
the control station to each of the 10 tributaries.
Whenever a station transmits a message to another station, it assigns its next sequential message
number to that message and places that number in the sequence field of the message header. In addition to maintaining a counter for the sequentially numbered messages which it sends, the station also
maintains a counter of the message numbers received from the other station. It updates that counter
whenever a message is received with a message number exactly one higher than the previously received
message number. The contents of the received message counter are included in the response field of the
message being sent, to indicate to the other station the highest sequenced message that has been
received.

When a station receives a message containing an error, that station sends a negative acknowledge
(NAK) message back to the transmitting station. DDCMP does not require an acknowledgement for
each message, as the number in the response field of a normal header (or in either the special NAK or
positive acknowledgement message ACK) specifies the sequence number of the last good message
received. For example, if messages 4,5, and 6 have been received since the last time an acknowledgement was sent, but message 6 is bad, the NAK message specifies number 5 which says "messages 4 and
5 are good and 6 is bad." When DDCMP operates in the full-duplex mode, the line does not have to be
turned around; the NAK is simply added to the messages for the transmitter.
When a station receives a message that is out of sequence, it does not respond to that message. The
transmitting station will detect this from the response field of the messages which it receives; if the
reply wait timer expires before the transmitting station receives an acknowledgement, the transmitting
station will send a REP message. The REP message contains the sequence number of the most n,cent
unacknowledged message sent to the distant station. If the receiving station has correctly received the
message referred to in the REP message (as well as the messages preceding it), it replies to the REP by
sending an ACK. Ifit has not received the message referred to in sequence, it sends a NAK containing
the number of the last message that it did receive correctly. The transmitting station will then retransmit all data messages after the message specified in the NAK.
The numbering system for DDCMP messages permits up to 255 unacknowledged messages outstanding, a useful feature when working on high delay circuits such as those using satellites.

B-4

NOTE 1

COUNT FLAG
RESPONSE SEQUENCE ADDRESS
CLASS
14 BITS 2 BITS
a BITS
a BITS
a BITS

xxxxxxxx
SOH - DATA MESSAGES
10000001
00000101
ENQ { ACKNOWLEDGEMENT
NEGATIVE ACKNOWLEDGE 00000101

REASONS:

ENQ
DLE

CHARACTER COUNT
00000001000000
00000010--·······

BCC HEADER ERROR
Bec DATA ERROR
REP RESPONSE
BUFFER UNAVAILABLE
RECEIVER OVERRUN
MESSAGE TOO LONG
HEADER FORMAT ERROR

REPLY MESSAGE
START MESSAGE
START ACKNOWLEDGEMENT
MAINTENANCE MESSAGE

00000101
00000101
00000101
10010000

QS
QS
QS

CRC 1
16 BITS

INFORMATION
ANY NUMBER CRC 2
OF a-BIT
16 BITS
CHARACTERS

XXXXXXXX
RESP #
RESP #
RESP #

XXXXXXXX
MESSAGE#
00000000
00000000

XXXXXXXX
ADDRESS
ADDRESS
ADDRESS

00000000
00000000
00000000
00000000

LSTMESS#
00000000
00000000
00000000

ADDRESS
ADDRESS
ADDRESS
ADDRESS

000001
000010
000011
001000
001001
010000
010001

00000011000000
00000110000000
00000111000000
CHARACTER COUNT

QS
11
11
11

NOTES:
1. ONLY THE DATA MESSAGE AND THE MAINTENANCE MESSAGE HAVE CHARACTER COUNTS, SO
ONLY THESE MESSAGES HAVE THE INFORMATION AND CRC2 FIELDS SHOWN IN THE MESSAGE
FORMAT DIAGRAM ABOVE.
2. "RESP #" REFERS TO RESPONSE NUMBER. THIS IS THE NUMBER OF THE LAST MESSAGE
RECEIVED CORRECTLY. WHEN USED IN A NEGATIVE ACKNOWLEDGE·MESSAGE, IT IS ASSUMED
THAT THE NEXT HIGHER NUMBERED MESSAGE WAS NOT RECEIVED, WAS RECEIVED WITH
ERRORS, OR WAS UNACCEPTED FOR SOME OTHER REASON. SEE "REASONS."
3. "MESSAGE#" IS THE SEQUENTIALLY ASSIGNED NUMBER OF THIS MESSAGE. NUMBERS ARE
ASSIGNED BY THE TRANSMITTING STATION MODULO 256; I.E., MESSAGE 000 FOLLOWS 255.
4. "LSTMESS#" IS THE NUMBER OF THE LAST MESSAGE TRANSMITTED BY THE STATION. SEE THE
TEXT DISCUSSION OF REP MESSAGES.
5. " ADDRESS" IS THE ADDRESS OF THE TRIBUTARY STATION IN MULTIPOINT SYSTEMS AND IS
USED IN MESSAGES BOTH TO AND FROM THE TRIBUTARY. IN POINT TO POINT OPERATION, A
STATION SENDS THE ADDRESS "1" BUT IGNORES THE ADDRESS FIELD ON RECEPTION.
6. "Q" AND "S" REFER TO THE QUICK SYNC FLAG BIT AND THE SELECT BIT. SEE TEXT.
MK-2249

Figure B-3

DDCMP Message Format in Detail

B-5

B.3 MESSAGE FORMAT
With the above background, it is now time to explore the various DDCM P message formats in fulll
detail, as shown in Figure 8-3. The first character of the message is the class of message indicator,
represented in ASCII with even parity. There are three classes of messages: data, control, and mainte·,
nance. These are indicated by class of message indicators SOH, ENQ, and DLE respectively. The next.
two characters of the message are broken into a 14-bit field and a 2-bit field. The 14-bit field is used in
data and maintenance messages to indicate the number of characters that will follow the header and
form the information part of the message. In control messages, the first 8 bits of the 14-bit fidd are
used to designate what type of control message it is; the last 6 bits are generally filled up with zeros.
The exception is in N A K messages where the last six bits are used to specify the reason for the N A K.
The 2-bit field contains the quick sync and select flags.
'
The quick sync flag is used to inform the receiving station that the message will be followed by sync
characters; the receiver may wish to set its associated synchronous receiver hardware into sync s·earch
mode and sync strip mode. This will re-establish synchronization and syncs will be discarded until the
first character of the next message arrives. The purpose of this is to permit the receiving station to
engage any hardware sync-stripping logic it might have and prevent it. from filling its buffers with sync
characters. The select flag is used to indicate that this is the last message which the transmitting station
is going to transmit and that the addressed station is now permitted t.o begin transmitting. This flag is
useful in half-duplex or multipoint configurations, where transmitters need to get turned on and off.
The response field contains the number of the last message correctly received. This field is used in data
messages and in the positive and negative acknowledge types of control message. Its function should
be evident from the preceding discussion of sequence control.
The sequence field is used in data messages and in the REP type of control message. In a data message, it
contains the sequence number of the message as assigned by the transmitting station. In a REP message, it
is used as part of the question. "Have you received all messages up through message number (specify)
correctly?"
The address field is used to identify the tributary station in multipoint systems and is used in messages
both to and from the tributary. In point-to-point operation. a station sends address I, but ignores the
address field on reception.
In addition to the positive and negative acknowledgement and REP types of control message, there are
also start and start acknowledge control messages. These are used to place the station which receives
them in a known state. In particular, they initialize the message counters, timers, and other counters.
The start acknowledge message indicates that this has been accomplished.
Figure 8-3 also shows the maintenance message. This is typically a bootstrap message containing load
programs in the information field. A complete treatment of bootstrap messages and start up procedures is beyond the scope of this book.
NOTE

Refer to the D DC M P Specification Order (AAD599A-TC) for a complete detailed description of
DDCMP.

B-6

APPENDIX C
DIAGNOSTIC SUPERVISOR
SUMMARY

C.I INTRODUCTION
The PDP-II diagnostic supervisor is a software package which:

C.2

•

Provides run-time support for diagnostic programs running on a PDP-II in Stand-alone
Mode,

•

Provides a consistent operator interface to load and run a single diagnostic program or a
script of programs,

•

Provides a common programmer interface for diagnostic development,

•

Imposes a common structure upon diagnostic programs,

•

Guarantees compatibility with various load systems such as APT, ACT, SLIDE, XXUP+,
ABS Loader, and

•

Performs non-diagnostic functions for programs, such as console I/O, data conversion, test
sequencing, program options.

VERSIONS OF THE DIAGNOSTIC SUPERVISOR
File Name

Environment

HSAA **.SYS

XXDP+

HSAB **.SYS

APT

HSAC **.SYS

ACT/SLIDE

HSAD **.SYS

Paper Tape (Absolute Loader)

In the above file names, " ** " is for REV and patch level, such as "AO"
C.3 LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC
A supervisor-compatible* diagnostic program may be loaded and started in the normal way, using any
of the supported load systems. Using XXDP+ for example, the program "CZDMRB.BIN" is loaded
and started by typing .R CZDMRB.

*To determine if diagnostics are supervisor-compatible, use the List command under the Setup Utility (see
section C.5.).

C-l

XXDP+ / DIAGNOSTIC SUPERVISOR MEMORY LAYOUT
ON A 16KW (MIN MEMORY) SYSTEM
ADDRESS

100000 (0)
XXDP+

070000 (0)

DIAGNOSTIC
SUPERVISOR
( 6KW)

040000 (0)

DIAGNOSTIC
PROGRAM
( 7.5KW)

002000 (0)

00000o (0)
MK-2216

Figure C-l

XXDP+ /Diagnostic Supervisor Memory Layout on a 16Kw
(Min Memory) System

The diagnostic and the supervisor are automatically loaded to the memory location (as shown in Figure C-l)
and the program is started. The following message is typed by the program:
DRS LOADED
DIAG.RUN-TIME SERVICES
CZDMR-B-O
M8203 STATIC LOGIC TESTS - PART I OF 2
UNIT IS M8203
DR>
DR> is the prompt for the diagnostic supervisor routine. At this point a supervisor command must be
entered (the supervisor commands are listed in section CA).

e.l.l

Five Steps to Run a Supervisor Diagnostic
•

STEP 1 - Enter start command.
When the prompt "DR>" is issued, type:
STA/PASS:l/FLAGS:HOE <CR>
The switches and flags are optional.

C-2

•

STEP 2 - Enter number of units to be tested.
The program will respond to the Start command with:

# UNITS?
At this point the number of devices to be tested must be entered.
•

STEP 3 - Answer hardware parameter questions.
After the number of devices to be tested has been entered, the program will respond by
asking a number of "Hardware Questions." The answers to these questions are used to build
hardware parameter tables in memory. One of these "Hardware P-Tables" will be built for
each device to be tested and the series of questions will be posed for each device.

•

STEP 4 - Answer software parameter questions.
When all the "Hardware P-Tables" are built, the program will respond with:
CHANGE SW?
I f other than the default parameters are desired for the software, type "Y." I f the default
parameters are desired, type "N."
If "Y" is typed, a series of "Software Questions" will be asked and the answers to these will
be entered into the "Software P-Table" in memory. The software questions will be asked
only once, regardless of the number of units to be tested.

•

STEP 5 - Diagnostic execution.
After the software questions have been answered, the diagnostic will begin to run.
What happens next will be determined by the switch options selected with the Start command, or errors occurring during execution of the diagnostic.

C.4 SUPERVISOR COMMANDS
The supervisor commands that may be issued in response to the "DR>" prompt are as follows:
•

Start Command - Used to start a diagnostic program.

•

Restart Command - When a diagnostic has stopped and control is given back to the supervisor, this command may be used to restart the program from the beginning.

•

Continue Command - Used to allow a diagnostic to continue running from where it was
stopped.

•

Proceed Command - Causes the diagnostic to resume with the next test after the one in
which it halted.

•

Exit Command - Transfers control to the XXDP+ monitor.

C-3

•

Drop Command - Drops units specified until an Add or Start Command is given.

•

Add Command - Adds units specified. These units must have been previously dropped.

•

Print Command - Prints out statistics if available.

•

Display Command - Displays P-Tables.

•

Flags Command - U sed to change flags.

•

ZFLAGS - Clears flags.

All of the supervisor commands except Exit, Print, Flags, and ZFLAGS can be used with switch
options.

C.4.1 Command Switches
Switch options may be used with most supervisor commands. The available switches and their function are as follows:
•

.jTESTS: - Used to specify the tests to be run (the default is all tests). An example of the
tests switch used with the Start command to run tests 1 through 5, 19, and 34 through 38
would be:
DR> START/TESTS: 1-5 : 19 : 34-38 <CR>

•

.jPASS: - Used to specify the number of passes for the diagnostic to run. For example:
DR> START/PASS: 1
In this example, the diagnostic would complete one pass and give control back to the supervisor.

•

./EOP: - Used to specify how many passes of the diagnostic will occur before the end of pass
message is printed (the default is one).

•

.jUNITS: - Used to specify the units to be run. This switch is valid only if "N" was entered
in response to "CHANGE HW?"

•

.jFLAGS: - Used to check for conditions and modify program execution accordingly. The
conditions checked for are:
: HOE -Halt an error (transfers control back to the supervisor)
: LO E - Loop on error
:IER - Inhibit error reports
:IBE -- Inhibit basic error information
:IXE -- Inhibit extended error information
:PRI -- Print errors on line printer
: PNT - Print the number of the test being executed prior to execution

C-4

:BOE - Ring bell on error
:UAM - Run in unattended mode, bypass manual intervention tests
:ISR - Inhibit statistical reports
:IOU - Inhibit dropping of units by program

C.4.2

Control/Escape Characters Supported

The keyboard functions supported by the diagnostic supervisor are as follows:
•

CONTROL C (t C) - Used to return control to the supervisor. The "DR>" prompt would
be typed in response to CONTROL C. This function can be typed at any time.

•

CONTROL Z (t Z) - Used during hardware or software dialogue to terminate the dialogue
and select default values.

•

CONTROL 0 (to) - Used to disable all printouts. This is valid only during a printout.

•

CONTROL S (t S) - Used during a printout to temporarily freeze the printout.

•

CONTROL-Q (t Q) - Used to resume a printout after a CONTROL S.

C.S WHAT IS THE SETUP UTILITY?
Setup is a utility program that allows the operator to parameterize a supervisor diagnostic prior to
execution. This is valid for either XXDP+ or ACT/SLIDE environments. Setup asks the hardware
and software questions and builds the P-Tables.
The commands available under Setup are:
List - list supervisor diagnostics
Setup - create P-Tables
Exit - return control to the supervisor
The format for the List command is:
LIST DDN:FILE.EXT
Its function is to type the file name and creation date of the file specified if it is a revision C or later
supervisor diagnostic. If no file name is given, all revision C or later supervisor diagnostics will be
listed. The default for the device is the system device and wildcards are accepted.
The format for the Setup command is:
SETUP DDN:FILE.EXT= DDN:FILE.EXT
It will read the input file specified and prompt the operator for information to build P-Tables. An
output file will be created to run in the environment specified. File names for the output and input files
may be the same. The output and input device may be the same. The default for the device is the system
device and wildcards are not accepted.

C-5

GLOSSARY

ACKNOWLEDGE (ACK):
Indicates that the previous transmission block was accepted by the receiver and it is ready to
accept the next block of the transmission.
ARITHMETIC LOGIC UNIT (ALU):
Allows the microprocessor to perform arithmetic and logic operations.
A PORT:
Read/write input to the multiport RAM.
ASYNCHRONOUS TRANSMISSION:
Transmission in which time intervals between transmitted characters may be of unequal length.
Transmission is controlled by start and stop elements at the beginning and end of each character.
Also called Start-Stop transmission.
BUFFERED ARITHMETIC LOGIC UNIT (DALU):
Operations performed by the ALU are buffered by the BALU and directed to data memory,
respective registers, and the Berg Port.
BERG PORT:
An 8-bit port that allows the microprocessor to communicate with other devices without using the
UNIBUS.
BIT-STUFF PROTOCOL:
Zero insertion by the transmitter after any succession of five continuous ones designed for bitoriented protocols such as 18M's Synchronous Data Link Control (SDLC).
BITS PER SECOND:
Bit transfer rate per unit of time.
B PORT:
Read Address input of the multiport RAM (Read Only Port).
BRANCH REGISTER (BRG):
Temporary card storage register used for branch determination and shifting right.
DUFFER:
Storage device used to compensate for a difference in the rate of data flow when transmitting data
from one device to another.

GLOSSARY-l

CCITT:
Comite Consultatif Internationale de Telegraphie et Telephonie - An international consultative
committee that sets international communications usage standards.
CONTROL AND STATUS REGISTERS (CSRs):
Communication of control and status information is accomplished through these registers.
CRC (CYCLIC REDUNDANCY CHECK):
An error scheme in which the check character is generated by taking the remainder after dividing
all the serialized bits in a block of data by a predefined number.
CROM:
Plug-in control read only memory used as the instruction memory for the processor.
CYCLIC REDUNDANCY CHECK (CRC):
An error detection scheme in which the check character is generated by taking the remainder after
dividing all the serialized bits in a block of data by a predetermined binary number.
DATA LINK ESCAPE (OLE):
A control character used exclusively to provide supplementary line control signals (control character sequences or OLE sequences). These are two-character sequences where the first character is
OLE. The second character varies according to the function desired and the code used.
DATA MULTIPLEXER (DMUX):
An 8-bit wide, 8-to-1 multiplexer used to select data for the B input of the ALU.
DATA-PHONE DIGITAL SERVICE (DDS):
A communications service of the Bell System in which data is transmitted in digital rather than
analog form, thus eliminating the need for modems.
DESTINATION ROM (DROM):
Controls the operand as defined by the destination of the instruction in the instruction register.
DIGITAL DATA COMMUNICATIONS PROTOCOL (DDCMP):
DIGITAL's standard communications protocol for character oriented protocol.
DIRECT MEMORY ACCESS (DMA):
Permits I/O transfers directly into or out of memory without passing through the processor's
general registers.
ELECTRONIC INDUSTRIES ASSOCIATION (EIA):
A standards organization specializing in the electrical and functional characteristics of interface
equipment.
FROM:
Function ROM - Controls up to 16 functions performed by the ALU.
FULL-DUPLEX (FOX):
Simultaneous two-way independent transmission in both directions.
FIELD REPLACEABLE UNIT (FRU):
Refers to a faulty unit not to be repaired in the field. Unit is replaced with a good unit and the
faulty unit is returned to a predetermined location for repair.

GLOSSARY-2

FIFO:
First In/First Out characteristic of the silo hardware buffer.
HALF-DUPLEX (HDX):
An alternate, one-way-at-a-time independent transmission.
IBUS/OBUS:
Microprocessor NPR control, miscellaneous registers. and CSRs.
IBUS* /OBUS*:
Microprocessor NPR control, miscellaneous registers. and CSRs.
INSTRUCTION REGISTER (IR):
Contains the instruction that is being executed. Outputs are used to control the microprocessor.
LINK MANAGEMENT:
The link management component resolves the transmission and reception on links that are connected to two or more transmitters and/or receivers in a given direction.
LU IBUS:
The line unit input data bus provides a path to the DMUX via the berg connector.
MEMORY ADDRESS REGISTER (MAR):
Controls the data memory for buffered arithmetic and logic operations to main memory.
MAIN MEMORY (MEM):
Data storage area for the microprocessor 4K X 8 RAM~ cannot be accessed directly by the CPU.
MAINTENANCE INSTRUCTION REGISTER (MIR):
Provides a destination for an instruction that can be loaded by the CPU during maintenance.
MOP:
Maintenance operation protocol.
MULTIPORT RAM:
Contains all M8207 control and status registers between the microprocessor and the CPU processor.
NEGATIVE ACKNOWLEDGMENT (NAK):
I ndicates that the previous transmission block was in error and that the receiver is ready to accept
a retransmission of the erroneous block (also a Not Ready Reply to a station selection in multiport).
NON-PROCESSOR REQUEST (NPR):
Direct memory access type transfers, see DMA.
PROGRAM COUNTER (PC):
A 14-bit counter used to control the address of the control ROM directly. PC is derived from
Branch and Move instructions.
PROTOCOL:
A formal set of conventions governing the format and relative timing of message exchange between two communicating processes.

GLOSSARY-3

RANDOM ACCESS MEMORY (RAM)
READ ONLY MEMORY (ROM)
RS232-C:
EIA standard single-ended interface levels to modem.

RS-422-A:
EIA standard differential interface levels to modem.

RS-423-A:
EIA standard single-ended interface levels to modem.

RS-449:
EIA standard connections for RS-422-A and RS-423-A to modem interface.

SILO:
First in, first out register. Receive silo is loaded from the USYRT, transmit silo from the microprocessor (64 X 12).

SCRATCHPAD MEMORY (SP):
Read/write memory used for temporary storage of data (16 X 8 bits).

SCROM:
Source ROM - Controls input selection for the DMUX. Also determines if a move instruction is
to be executed (32 X 8 bits).

SYNCHRONOUS TRANSMISSION:
Transmission in which the data characters and bits are transmitted at a fixed rate with the transmitter and receiver synchronized.

SYSTEM CLOCK:
Basic"timing providing clock pulses for microprocessor timing functions.

UNIBUS:
A single high speed bus on which system components connect and communicate with each other.
Addresses, data, and control information are transmitted via 56 available lines of the bus.

USYRT:
Universal Synchronous Receiver/Transmitter - Handles input or output data to the modem, and
the basic protocol framing and error detection.

GLOSSARY-4

DMR11 SYNCHRONOUS CONTROLLER USER'S GUIDE
EK-DMR11-UG-002

Reader's Comments

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our publications.
What is your general reaction to this manual?
wellwr~~n,ett?

In your judgement is it complete, accurate, well organ~zed,

Isiteasytouse?~~~~~~~~~~~~~~~~~~~~~~~~~~~

What faults or errors have you found in the manual? _ _~ _ _ _ _~_ _ _ _ _~~~~~~~_

Does this manual satisfy the need you think it was intended to satisfy? _ _ _ _ _ _ _ _ _ _ _ _ __
Does it satisfy your needs? _ _~~~~~_ _ _ Why? ,_ _ _~~~~~_~~~~~~~~_

Please send me the current copy of the Technical Documentation Catalog, which contains information
on the remainder of DIGITAL's technical documentation,

Street _~~~~~~~_~_ _ _ _ _ __
Name
City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_______________
_________________
Title
_____________________ ______________________________
___ State/Country_~_ _~~_~~~~~~_
~

Company_~

Department _~~~~~_~~~_____~_____

Additional copies of this document are available from:

Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01632
Attention: Communications Services (N R2/M 16)
Customer Services Section

Order No.

EK-DMR11-UG-002

Zip __~_~~~~~~~_~~~~____________

.--------------------.Fold Here----------------------

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Do Not Tear - Fold Here and Staple. -

111111
I

No Postage
Necessary
if Mailed in the
United States

~~c~!sN E ~E~IT ~~; l ~ERR~A!.IN~
POST AGE WILL BE PAID BY ADDRESSEE

Digital Equipment Corporation
Educational Services Development & Publishing
Continental Blvd. (MK1/2M26)
Merrimack, N.H. 03064