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EK-DMCMP-TM

August 1979

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Document:	DMC11 IPL Microprocessor Technical Manual
Order Number:	EK-DMCMP-TM
Revision:	000
Pages:	196
Original Filename:	http://bitsavers.org/pdf/dec/unibus/EK-DMCMP-TM-002_DMC11_IPL_Microprocessor_Technical_Manual_Aug79.pdf

OCR Text

DMC11 IPL
microprocessor
technical
.. manual

EK-DMCMP-TM-002

DMC11 IPL
microprocessor
technical manual

digital equipment corporation. merrimack, new hampshire

1st Edition, May 1976
2nd Edition, August 1979

Copyright © 1979 by Digital Equipment Corporation
The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL's DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC
PDP
DECUS
UNIBUS

D ECsystem-1 0
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
lAS

12/82-15

CONTENTS
Page
PREFACE
CHAPTER 1

INTRODUCTION

1.1
1.2
1.3
1.3.1
1.3.1.1
1.3.1.2
1.3.1.3
1.3.1.4
1.3.1.5
1.3.1.6
1.3.2

SCOPE ................................................................................................................ 1-1
DMCII GENERAL DESCRIPTION ................................................................. 1-1
DMCII SYSTEM OPERATION ........................................................................ 1-2
Command Structure ..................................................................................... 1-4
Initialization Command ....................................................................... 1-4
Base In Command ................................................................................ 1-4
Control In Command ........................................................................... 1-4
Buffer Address In Command ................................................................ 1-4
Buffer Address Out Command ............................................................. 1-4
Control Out Command ........................................................................ 1-4
DMCII Operation Sequencing ..................................................................... 1-4

CHAPTER 2

INSTALLATION

2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.6
2.6.1
2.6.2
2.6.2.1
2.6.2.2
2.6.3

SCOPE ................................................................................................................ 2-1
UNPACKING AND INSPECTION ................................................................... 2-1
MECHANICAL PACKAGING ......................................................................... 2-1
PRE-INSTALLATION CONSIDERA TIONS .................................................... 2-1
Configuration Considerations ...................................................................... 2-1
Power Requirements .................................................................................... 2-4
Backplane .................................................................................................... 2-4
DEVICE AND VECTOR ADDRESSES ............................................................. 2-4
Device Address Assignment ........................................................................ 2-4
Vector Address Assignment. .........................................................................2-5
Examples of Device and Vector Address Assignment. ...................................2-6
Interrupt Priority .........................................................................................2-9
UNIBUS Loading ........................................................................................ 2-9
MODULE INSTALLATION AND CUSTOMIZA TION ..................................2-9
Preinstallation Checkout Procedure ............................................................ .2-9
Installation Procedures ............................................................................... 2-15
Installation in a BAII-K Box ............................................................. 2-20
Installation in a DDII-D Backplane ................................................... 2-20
Checkout Procedure .................................................................................. 2-21

CHAPTER 3

PROGRAMMING INFORMATION

3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4;2.1
3.4.2.2
3.4.2.3
3.4.2.4

INTRODUCTION .............................................................................................. 3-1
INTERRUPT VECTORS ................................................................................... 3-1
PRIORITY SELECTION ................................................................................... 3-1
PDP-II PROGRAMMING INFORMATION ................................................... 3-2
UNIBUS Control and Status Registers ......................................................... 3-2
Command Structure ..................................................................................... 3-2
Input Commands ............................. ~ ................................................... 3-2
Output Commands ............................................................................... 3-4
CSR's Bit Assignments ......................................................................... 3-4
BSEL 0 - Input Register ....................................................................... 3-4
iii

CONTENTS (Coot)
Page
3.4.2.5
3.4.2.6
3.4.2.7
3.4.2.8
3.4.2.9
3.4.2.10
3.4.2.11
3.4.3
3.4.3.1
3.4.3.2
3.4.3.3
3.4.3.4
3.4.4
3.4.4.1
3.4.4.2
3.5
3.5.1
3.5.2
3.5.3
3.5.3.1
3.5.3.2
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9

BSEL 1 - Maintenance Register ........................................................... 3-4
BSEL 2 - Output Register .................................................................... 3-4
BSEL 3 - Reserved ............................................................................... 3-4
Base Input (BASE I) Command Format .............................................. .3-4
Control Input (CNTRL I) Command Format ...................................... 3-9
Buffer Assignment (BA/CCI and BA/CCO) Command Formats ......... 3-9
Control Output (CNTL 0) Command Format ................................... 3-10
Input Commands (Format Descriptions) .................................................... 3-10
Initialization Command ..................................................................... 3-14
Base In Command .............................................................................. 3-14
Control In Command ......................................................................... 3-17
Buffer Address/Character Count In Command .................................. 3-21
Output Command (Format and Field Descriptions) .................................. .3-24
Buffer Address/Character Count Out (BA/CCO) Command ............. 3-24
Control Out (CONT 0) Command ..................................................... 3-24
PROGRAMMING HINTS ............................................................................... 3-27
DMCll Start-Up ....................................................................................... 3-27
DMC11 MASTER CLEAR ....................................................................... 3-27
Error Reporting ......................................................................................... 3-28
Cumulative Error Counters ................................................................ 3-28
Threshold Counters ............................................................................ 3-28
Power Fail Recovery .................................................................................. 3-28
Shutdown of the DMCl1 ........................................................................... 3-29
Modem Control .........................................................................................3-32
Maintenance Mode .................................................................. '" ............... 3-33
Remote Load Detect .................................................................................. 3-35
Performance Degradation on the DMCI1-AL ............................................3-38

CHAPTER 4

DETAILED DESCRIPTION

4.1

SCOPE ................................................................................................................. 4-1
MICROPROCESSOR DESCRIPTION .............................................................. 4-1
Introduction ................................................................................................. 4-1
DMCll/CPU Structures ............................................................................. 4-1
INBUS/OUTBUS and INBUS* /OUTBUS* Register Definition ........ .4-2
Multiport RAM ................................................................................... 4-7
NPR Control Register .......................................................................... 4-7
Microprocessor Miscellaneous Control Register .................................. .4-7
External Connector .............................................................................. 4-8
Microinstruction Word Formats ................................................................. .4-8
Branch Instruction ............................................................................... 4-8
4g - Branch Immediate (I) ..................................................................... 4-8
6s - Branch Memory (MEM) ................................................................ 4-8
78 - Branch Register (BRG) ..................................................................4-9
Move Instruction ................................................................................. 4-9
Os - Move Immediate (1) ..................................................................... 4-12
18 - Move INBUS (lBUS) ................................................................. .4-12
58 - Move INBUS* (IBUS*) .............................................................. 4-12
28 - Move Memory (MEM) ............................................................... 4-13

4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.2.4
4.2.2.5
4.2.3
4.2.3.1
4.2.3.2
4.2.3.3
4.2.3.4
4.2.3.5
4.2.3.6
4.2.3.7
4.2.3.8
4.2.3.9

CONTENTS (Coot)
Page
4.2.3.10
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
4.2.11
4.2.11.1
4.2.11.2
4.2.11.3
4.2.12
4.2.12.1
4.2.12.2
4.2.12.3
4.2.13
4.2.14
4.2.15
4.2.16
4.2.17
4.2.17.1
4.2.17.2
4.2.17.3
4.2.17.4
4.2.17.5
4.2.17.6
4.2.17.7
4.2.17.8
4.2.17.9
4.2.18

38 - Move Branch Register (BRG) .................................................... .4-13
CRaM, MAR, BR, PC and BRANCH MUX ........................................... 4-13
Main Memory (MEM) .............................................................................. 4-15
CRaM and the Maintenance REG ........................................................... 4-16
DMUX and SROM .................................................................................. 4-17
ALU and Associated Logic ....................................................................... 4-17
Scratchpad Memory (PC) .......................................................................... 4-17
Multiport RAM ........................................................................................ 4-19
INBUS/OUTBUS and INBUS* /OUTBUS* Registers ............................. 4-25
NPR Control Register 10 ................................................................. .4-26
Microprocessor Miscellaneous Register 11 ....................................... .4-26
OUTBUS/INBUS Assigned Addresses .......................................... 4-26
Maintenance CSR (BSEL 1) ...................................................................... 4-31
Step LU H ......................................................................................... 4-31
LU Loop H ....................................................................................... 4-31
ROM OUT H ................................................................................... 4-31
Microprocessor Clock ............................................................................... 4-32
Address Selection Logic ........................................................................... .4-34
NPR Control Logic ................................................................................... 4-34
Interrupt Control Logic ............................................................................. 4-35
Line Unit Interface ....................................................................................4-38
LU IBUS 0 H - LU IBUS 7 H .......................................................... .4-38
BALUOL - BALU7L ........................................................................4-38
IBR. L/IBR *H ..................................................................................4-38
OBW L .............................................................................................4-38
OUT * L ...........................................................................................4-38
CROM 0 L - CRaM 7 L ...................................................................4-38
Clear .................................................................................................4-38
LU Loop ...........................................................................................4-38
Step LU ............................................................................................4-38
Typical System Timing ..............................................................................4-38

CHAPTERS

SERVICE

5.1
5.2
5.2.1
5.2.2
5.2.2.1
5.2.2.2
5.2.2.3
5.2.2.4
5.2.2.5
5.3
5.4
5.5
5.5.1
5.5.2

SCOPE ............................................................................................................... 5-1
MAINTENANCE FUNCTIONS/MAINTENANCE MODES ......................... 5-1
Maintenance Register (BSEL 1) ................................................................... 5-1
Maintenance Modes .................................................................................... 5-1
Maintenance Mode ............................................................................. 5-3
System Test ......................................................................................... 5-3
Single Step Internal Maintenance Mode .............................................. 5-4
System Test Internal Maintenance Mode .............................................. 5-4
External Maintenance Mode ............................................................... 5-4
MAINTENANCE PHILOSOPHy .................................................................... 5-5
PREVENTIVE MAINTEN AN CE (PM) ............................................................ 5-5
CORRECTIVE MAINTENANCE .................................................................... 5-6
CZDMC Diagnostics ............................................................. :.................... 5-6
CZDME DMCll Line Unit Tests ............................................................... 5-8

CONTENTS (Cont)
Page
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
5.5.8
5.5.9
5.6
5.7

DZDMF DMCII Bit Stuff Line Unit Tests .................................................. 5-8
CZDMG DMCII CROM and Jump Tests ................................................... 5-8
DZDMH DMCII Free-Running Tests ........................................................ 5-9
DZDMO - DMCII Overlay for Interprocessor Test Program (lTEP) ........ 5-10
DEC/XII DMCl1 Module ........................................................................ 5-11
Soft Error Reports Under DEC/XlI .......................................................... 5-11
Examination of DMCl1 Internal Components ........................................... 5-12
POSSIBLE OVERLOADING OF MAINTENANCE CLOCK SIGNAL ......... 5-13
DDCMP MESSAGE FORMAT FOR DMCll ................................................. 5-13

APPENDIX A

PDP-II MEMORY ORGANIZATION AND ADDRESSING CONVENTIONS

APPENDIX B

LOGIC SYMBOLOGY

B.I
B.2
B.3
B.4
B.5

INTRODUCTION ............................................................................................. B-1
UNIBUS SIGNAL LEVELS .............................................................................. B-1 .
EQUIVALENT GATE SyMBOLS .................................................................... B-1
4-0UTPUT TERMINAL FLIP-FLOP SyMBOLOGy ..................................... B-2
REDEFINED 4-0UTPUT TERMINAL FLIP-FLOPS ..................................... B-4

APPENDIX C

SYNCHRONOUS SERIAL DATA HANDLING

C.I
C.1.1
C.1.2
C.1.3

BINARY DATA TRANSFER METHODS ....................................................... C-l
Parallel vs. Serial ......................................................................................... C-l
Asynchronous vs. Synchronous ................................................................... C-2
Synchronizing at the Receiver ...................................................................... C-4

APPENDIX D

DDCMP IN A NUTSHELL

D.l

D.3

DDCMP ............................................................................................................ D-l
Controlling Data Transfers ........................................................................ D-l
Error Checking and Recover ...................................................................... D-l
Character Coding ....................................................................................... D-3
Data Transparency ..................................................................................... D-3
Data Channel Utilization ........................................................................... D-3
PROTOCOL DESCRIPTION ........................................................................... D-3
MESSAGE FORMAT ...................................................................................... D-6

APPENDIX E

DDCMP BLOCK CHECK COMPUTATION

E.l
E.2
E.3

DDCMP ERROR DETECTION ....................................................................... E-l
THE CRC-16 POLyNOMIAL ........................................................................... E-l
CRC COMPUTATION ..................................................................................... E-l

APPENDIX F

BOOTSTRAP TEST UNDER ITEP

F.l

REMOTE LOAD DETECT ............................................................................... F-l
DMCl1 SETUP FOR REMOTE LOAD DETECT ............................................ F-l
DMCll Addressing .................................................................................... F-l

D.1.1
D.l.2
D.1.3
D.l.4
D.1.5

D.2

F.2
F.2.l

CONTENTS (Cont)
Page
F.2.2
F.3
F.4

DMCII Line Unit Setup ............................................................................. F-l
PROCEDURE TO TEST REMOTE LOAD DETECT UNDER ITEP .............. F-2
PROCEDURE TO TEST DOWN-LINE LOAD UNDER ITEP ........................ F-5

APPENDIX G

LINK TEST

G.I
G.2
G.3
G.4
G.4.1
G.4.2

ABSTRACT ....................................................................................................... G-l
REQUIREMENTS ............................................................................................ G-l
PROGRAM LOADING PROCEDURE ........................................................... G-l
OPERATING PROCEDURES FOR LINK TEST ............................................ G-l
MODE Selection ......................................................................................... G-2
Starting ITEP .............................................................................................. G-3

APPENDIX H

DZDMH DIAGNOSTICS OPERATING PROCEDURE

H.I
H.2
H.2.1
H.2.2

OVERVIEW ....................................................................................................... H-l
REQUIREMENTS ............................................................................................ H-l
Equipment .................................................................................................. H-l
Storage ........................................................................................................ H-l
LOADING PROCEDURE ................................................................................ H-2
Method ....................................................................................................... H-2
STARTING PROCEDURE ............................................................................... H-2
Control Switch Settings ............................................................................... H-3
Startup Switch Register Options .......................................................... H-4
Dynamic Switches ............................................................................... H-5
Starting Address .......................................................................................... H-5
OPERATING PROCEDURE ............................................................................ H-5
Program and/or Operator Action ................. ~ .............................................. H-5
ERRORS ............................................................................................................ H-6
Error Recovery ........................................................................................... H-6
RESTRICTIONS ............................................................................................... H-6
Starting Restrictions .................................................................................... H-6
Operating Restrictions ................................................................................ H-6
Hardware Configuration Restrictions .......................................................... H-6
ADDITIONAL INFORMATION ..................................................................... H-6
Execution Time ........................................................................................... H-6
Pass Complete ............................................................................................. H-6
Key Locations ............................................................................................. H-7
Status Table ................................................................................................ H-7
Method of Autosizing ................................................................................. H-8
Finding the Control Status Register ..................................................... H-8
Finding the Vector and BR Level.. ....................................................... H-9
Software Switch Register ............................................................................. H-9

H.3
H.3.1
H.4
H.4.1
H.4.l.l
H.4.1.2
H.4.2
H.S
H.S.I
H.6
H.6.1
H.7
H.7.1
H.7.2

. H.7.3
H.8
H.8.1
H.8.2

H.8.3
H.8.4
H.8.S
H.8.S.1
H.8.S.2
H.8.6
APPENDIX I

DIFFERENCES BETWEEN DDCMP V4.0 AND DMCll
IMPLEMENTATION OF DDCMP V3.03

vii

CONTENTS (Coot)
Page
APPENDIX J

PROGRAMMING PROCEDURES FOR DMCII-AR OPTION IN AUTO
DIALj AUTO ANSWER APPLICATION

1.1
1 .2
1.3

AUTO DIAL ....................................................................................................... J-l
PREMATURE LINK DISCONNECT ............................................................... J-2
AUTO ANSWER ................................................................................................ J-3

GLOSSARY
INDEX

FIGURES
Figure No.
1-1
1-2
1-3
2-1
2-2

2-3
2-4

2-5
2-6
2-7
2-8
2-9
3-1

3-2
3-2
3-3
3-4

3-5
3-6

3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14

3-15
3-16
4-1

4-2

Title

Page

DMCII Remote Line Unit Interface .................................................................... 1-2
DMCII Local Line Unit Interface ...................................................................... .1-3
DMCII Operation Sequencing ............................................................................ 1-6
Microprocessor Device and Vector Address Switches ......................................... 2-12
Inserting BC085-1 /BC08R-l Cable into Microprocessor .................................... 2-15
Inserting Microprocessor Module (View 1) ......................................................... 2-16
Inserting Microprocessor Module (View 2) ......................................................... 2-1'6
Inserting Line Unit Module and BC085-1/BC08R-l Cable ................................. 2-18
Typical Cable Routing (BAII-F Box) ................................................................. 2-19
DMCll Line Unit Turnaround Test Connectors ................................................ 2-20
DDI1-D Backplane ........................................................................................... 2-21
DMCll Cabling ................................................................................................ 2-23
UNIBUS Control and Status Registers (CSRs)
(Symbolic Addresses and Format) ........................................................................ 3-3
Summary of Control and Status Registers (Input Commands) .............................. 3-5
Summary of Control and Status Registers (Output Commands) .......................... .3-6
Programming Procedure for Initialization Command ......................................... 3-15
Base In Command Format ................................................................................. 3-16
Programming Procedure for Base In Command ................................................. 3-18
Control In Command ......................................................................................... 3-19
Programming Procedure for Control In Command ............................................ 3-20
Buffer Address/Character Count In Command .................................................. 3-22
Programming Procedure for BA/CCI Command ............................................... 3-23
Programming Procedure for Output Commands'Servicing ................................. 3-25
Buffer Address/Character Count OUT FORMAT ............................................. 3-26
Control Out (CNTL 0) Command Format ........................................................ 3-26
DMCll Base Table ............................................................................................ 3-30
Enter MOP Mode Format .................................................................................. 3-35
Example Setup Procedure For RLD ................................................................... 3-37
DMCII Problem in High-Speed Code ................................................................ 3-40
DMCII Register and Data Path Structure ........................................................... 4-3
Microprocessor Block Diagram ........................................................................... 4-4

viii

FIGURES (Cont)
Figure No.

4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12

4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20

4-21
4-22
4-23
4-24
4-25
A-I
A-2
B-1

B-2
B-3
B-4

C-l
C-2
C-3
C-4
D-l
D-2
D-3
F-l
F-2
J-l

Title

Page

Microprocessor Register Timing ........................................................................ , ..4-6
Branch Microinstruction Word Format ..............................................................4-10
Move Microinstruction Word Format ................................................................. 4-11
Block Diagram of Program Counter Control Logic .............................................4-14
Configuration of the B Register .......................................................................... .4-15
Configuration of DR OM ....................................................................................4-16
Configuration of DMUX ....................................................................................4-18
Configuration ofSROM .....................................................................................4-19
ALU and Associated Logic ................................................................................ .4-20
Configuration of FROM .....................................................................................4-21
Multiport RAM .................................................................................................. 4-21
M ultiport RAM Addresses ............................................... '" .............................. .4-22
Block Diagram of Multiport RAM and Associated Logic .................................... 4-24
OUTBUS* /INBUS* Assigned Addresses .......................................................... .4-25
OUTBUS/INBUS Assigned Addresses .............................................................. .4-26
Physical Arrangement of Registers ..................................................................... .4-27
Clock Sequence ...................................................................................................4-32
System Clock Timing Diagram ............................................................................4-33
NPR Output Timing Diagram ............................................................................ .4-35
NPR Input Timing Diagram ...............................................................................4-36
Interrupt Timing Diagram ..................................................................................4-3 7
Typical Output Bus Timing .................................................................................4-39
Typical Input Bus Timing ........................................ , ...........................................4-39
Memory Organization for Maximum Size Using 18 Address Bits ......................... A-2
Memory Organization for Maximum Size Using 16 Address Bits ......................... A-3
Logically Equivalent Gates ................................................................................. B-2
Flip-Flop Logic Symbology ................................................................................ B-3
Electrical Connections to Outputs of 2- Terminal and 4- Terminal Flip-Flops ....... B-3
Standard and Redefined 4- Terminal Flip-Flops ................................................... B-4
Parallel Data Transfer ......................................................................................... C-l
Asynchronous Character Format ........................................................................ C-3
Synchronous Character Format .......................................................................... C-3
Serial Bit Stream ................................................................................................. C-4
DDCMP Data Message Format .......................................................................... D-l
DDCMP Sample Handshaking Procedure .......................................................... D-2
DDCMP Message Format in Detail .................................................................... D-5
Down-Line Load to Remote Node Using Remote Load Detect ........................... F-4
Remote Node Request for Down-Line Load Flowchart ...................................... F-6
Auto Answer Sequence ........................................................................................ J-2

TABLES
Table No.

2-1
2-2

2-3
2-4

2-5

3-1

3-2
3-3
3-4

3-5
3-6
4-1
4-2

4-3

5-1
5-2
G-I
G-2

Title

Page

Microprocessor/Line Unit Options and Parts ..................................................... 2-2
Vector Address Assignments ............................................................................... 2-5
Power Supply Voltages ...................................................................................... 2-10
Guide for Setting Switches to Select Device Addresses ....................................... 2-11
Guide for Setting Switches to Select Vector Address .......................................... 2-13
BSEL 0 Bit Functions .......................................................................................... 3-7
BSEL I Bit Functions .......................................................................................... 3-8
BSEL 2 Bit Functions .......................................................................................... 3-8
SEL 6 Bit Functions ............................................................................................ 3-9
SEL 6 Bit Functions ........................................................................................... 3-11
Cumulative Error Counters ................................................................................ 3-29
NPR Control Register (OUTBUS* /INBUS* Register Group)
REG 10 Bit Descriptions ................................................................................... .4-28
Miscellaneous Register (OUTBUS* /INBUS* Register Group)
REG II Bit Descriptions ................................................................................... .4-29
OUTBUS/INBUS Registers Byte Descriptions ..................................................4-30
BSEL I Bit Descriptions .......................................................................................5-2
DDCMP Message Decode for DMCII-AR&AL ............................................... 5-14
Operational Switch Setting ..................................................................................G-4
Valid Mode Combinations .................................................................................. G-4

PREFACE

This manual provides the user with information concerning the installation, operation, and maintenance of the DMCII microprocessor.
•

Chapter 1 provides an introduction and overall functional description of the 0 M C 11 M icroprocessor.

•

Chapter 2 contains interfacing and installation information for two microprocessor options
and four associated line unit options.

•

Chapter 3 includes information necessary for operation of the DMCII via the PDP-II
program.

•

Chapter 4 contains a detailed description of the DMCII operation.

•

Chapter 5 provides information for servicing the DMCII to the Field Replaceable Unit
(modules and cables). Procedures for running the diagnostics are also included.

•

The Appendices contain appropriate supplementary information.

The DMC 11 I PL Synchronous Line Unit Maintenance Manual (EK-DMCLU-M M-002) and the
DMCII Engineering Drawings (DMCII-O-8) provide additional information which draws the entire
system together.

CHAPTER 1
INTRODUCTION

1.1 SCOPE
This chapter contains a brief introduction to DMCII operation. The term DMCII as used throughout
this manual denotes the communication subsystem consisting of a microprocessor module and a line
unit module.
1.2 DMCII GENERAL DESCRIPTION
The DMCII is a microprocessor-based, intelligent, synchronous communication controller residing as
a Direct Memory Access (DMA) or Non-Processor Request (NPR) device on the PDP-II UNIBUS.
The DMCII ensures reliable data transmission by implementing the DIGITAL Data Communication
Protocol (DDCMP) in firmware using a high-speed microprocessor. The DDCMP detects errors on
the channel connecting the systems by using a 16-bit Cyclic Redundancy Check (CRC-16). Errors are
corrected, when necessary, by automatic retransmissions. Sequence numbers in message headers ensure that messages are delivered in proper order with no omissions or duplications.
A number of advantages are offered by the DMCll over conventional communication interfaces
which require a combination of hardware and software to implement a protocol. Programming is
greatly simplified and extensive communications expertise is no longer required when programming
the DMCll. PDP-II memory and processor time are not wasted with instructions implementing the
protocol. As a direct result, throughput is enhanced because the DMCII operates at high speeds and is
not delayed when the processor has to perform high priority tasks.
The DMCII microprocessor provides parallel data interfaces between any PDP-II family central
processor and a given DMCII line unit. With the microprocessor/line unit combination, computers
can be configured for either remote or local applications. There are two versions of the DMCII
microprocessor: the DMCII-AR (M8200-Y A module) which supports remote applications and the
DMCII-AL (M8200-YB module) which supports local applications. The DMCII-AR microprocessor
operates with either the DMCII-DA or the DMCII-FA line unit (M8201 module); the DMCII-AL
operates with either the DMCII-MA line unit (M8202-Y A module) or the DMCII-MD line unit
(M8202-YD module).
For remote operation, the computers are connected by common carrier facilities. DMCII-ARs can be
configured to interface with synchronous modems of up to 19.2K bps for modems that conform to the
EIA RS232-C interface standard and up to 56K bps for modems that conform to the CCITT
V .35 /DDS interface standard. A typical configuration for remote applications is illustrated in Figure
1-1.
For local operations, DMCII-ALs can be configured for high-speed operation of 56K bps or 1M bps
over triaxial cables. A typical configuration for local applications is illustrated in Figure 1-2.

1-1

DMC11
DMC-11

REMOTE

MICROPROCESSOR

LINE

(MS200.-YA)

UNIT
BCOSS-1

(MS201 )

or
BCOSR-1
CABLE

MODEM
BC05C
or

TO REMOTE STATION
_ _ _ _ ViA TELEPHONE LINES

BC05Z
CABLE

PDP-11

PROCESSOR

PDP-11
MEMORY

MK·0765

Figure I-I

DMCII Remote Line Unit Interface

Both the DMCII-DA and DMCII-FA line unit versions of the M8201 module contain modem control and level conversion logic that is compatible with EIA RS232-CjCCITT V.24 and CCITT
V.35jDDS interface standards. The DMCII-DA is shipped with a cable that accommodates only the
EIA RS232-CjCCITT V.24 interface. This line unit has a maximum speed of 19.2K bps. The DMCIIFA is shipped with a cable that has a maximum speed of 56K bps and accommodates only the CCITT
V .35 jDDS interface standard.
The DMCII-MA (M8202-VA) and DMCII-MD (M8202-YD) line unit versions have built-in integral
modems. The DMCII-MA operates at a speed of 1M bps over triaxial 'cables up to a maximum
distance of 1 km (3281 ft) with a Belden 8232 or equivalent cable and 2 km (6562 ft) with a Belden 8233
or equivalent cable. The DMCII-MD operates at a speed of 56K bps over triaxial cables up to a
maximum distance of 3 km (9843 ft) with a Belden 8232 cable and 6 km (19,685 ft) with a Belden 8233.
The triaxial cable is not included with either option. (This cable is not available from DIGITAL, see
DMCII IPL Synchronous Line Unit Maintenance Manual, EK-DMCLU-MM-002, for cable specifications.)
The line unit is not a stand-alone device. It must be used with a DMC II or equivalent microprocessor.
Refer to the DMCII IPL Synchronous Line Unit Maintenance Manual for complete coverage of the
DMC11 line units.
1.3 DMCll SYSTEM OPERATION
Operation of the DMC 11 is initiated and directed by a user-produced program residing in the PDP-II
[main Central Processing Unit (CPU)] memory. A user program is a device driver or an equivalent

1-2

DMC11

LOCAL

INTE-

MICROPROCESSOR
(MS200-YB)

LINE

GRAL

BCOSS-1
or
BCOSR-1
U

UNIT
(MS202-YA

: MODEM
I

TO LOCAL STATION

......_o_r_Y_D)_~_ _- - ' VIA ONE OR TWO
COAXIAL/TRIAXIAL CABLES

CABLE

I
B

PDP-11

PROCESSOR

PDP-11
MEMORY

MK-0766

Figure 1-2

DMCll Local Line Unit Interface

routine that interfaces to the DMCII. Communication between the user program and the DMCII is
provided by four Control and Status Registers (CSRs), which are integral to the DMC II microprocessor. These four 16-bit registers are used for control input, status output. the receiving or transmitting buffer to the DMCI1, and the receiving or transmitting buffer returns from the DMCll.
The first two registers in this group have a fixed format and serve as the command header for the
second two registers. The second two registers form a two-word data port for the exchange of unique
control/status information between the DMCll and the user program. The contents of the data port
are specified by an identification field in the command header. Other specific fields in the two-word
command header control interrupt enabling and status bits for command transfer handshakes between
the main CPU and the DMCl1.
A user program issues a command to the DMCll by setting up the input command header and
requesting use of the data port when the DMCll grants permission to use the data port. The user
program then passes the command to the DMCll in the pertinent CSRs. The DMCll interprets the
command and performs the specified actions. Similarly, the DMCll issues a command to the user
program by storing the command in the pertinent CSRs and notifying the user program that a command is available for retrieval and processing.
Message data received or transmitted by the DMCll is written into or read from user program assigned buffers in main CPU memory. The DMCll accesses these buffers through NPRs to a UNIBUS
address. A UNIBUS address is an 18-bit address used by an NPR device to access a device on the
UNIBUS or a location in main CPU memory.

1-3

1.3.1 Command Structure
The transfer of information between the DMCII microprogram and the user program requires implementation of a six-function command structure. The functions of commands are described briefly in
this section and in greater detail in Chapter 3.
1.3.1.1 Initialization Command - This command is used to clear all condition-sensitive logic in the
DMCII microprocessor/line unit and place the microprocessor in the initialized state. The Initialization command must be issued by the user program prior to startup of the DMCII or after fatal
error restart.
1.3.1.2 Base In Command - This command is used to assign a starting address of an area in the CPU's
main memory that is 128 words in length where the DMCII can store a snapshot (copy) of its internal
memory. The transfer of the DMCII 's memory contents to core memory only takes place on fatal
error conditions. The DMCII 's internal memory contains DDCMP link information for error reporting and error recovery which can be used when the DMCII enters the protocol start-up sequence. The
Base In command must be the first command issued after MASTER CLEAR via the Initialization
command, system initialization, or power failure. After assigning this Base In command with the
RESUME bit clear, the DMCII enters the protocol start-up sequence and the link can now become
active. There are two reasons for storing this information in both the DMCII 's memory and the
CPU's memory: (1) the DMCII 's memory is volatile (RAM), whereas most of the CPU's memory is
the non-volatile type (CORE), allowing excellent error recovery without a loss of link integrity, and (2)
allowing the operating system easy access to the DMCII 's memory contents without affecting the
DMCII 's operation. Base Table information can only be read for status and must never be altered by
the operating system.
1.3.1.3 Control In Command - This command defines the characteristics of the DMCll such as halfduplex or full-duplex mode and normal DDCMP or DDCMP maintenance mode. The Control In
command must be issued to the DMCII following a Base In command.
1.3.1.4 Buffer Address In Command - The PDP-II program issues this command to assign either a
transmit or receive buffer to the DMCI ~ by specifying an 18-bit address plus a 14-bit character count
for transmit or receive operation. There can be a maximum of seven transmit buffers and seven receive
buffers assigned to the DMCII at any given time.
1.3.1.5 Buffer Address Out Command - When the DMCll has successfully completed a receive operation (the CRC check was good) or a transmit operation (the transmitted message was acknowledged),
the buffer is returned to the PDP-II by a Buffer Address Out command.
1.3.1.6 Control Out Command - The DMCII issues this status command to inform the PDP-II of
some error condition which is either fatal or non-fatal. Non-fatal errors can be corrected by removing
the error condition. Fatal errors cause the protocol to terminate and require initialization of the
DMCII.
1.3.2 DMCII Operation Sequencing
The normal sequence of operation is represented in the flow chart of Figure 1-3.
The PDP-II program initializes the DMCII (MASTER CLEAR), assigns a 128-word Base Table via
the Base In command, sets up the proper mode by the Control In command, and then assigns transmit
and receive buffers via the Buffer Address/Character Count In (BA/CCI) commands. After receiving
the Base In command, the DMCII initiates the protJcol start-up sequence. The Control In command
sets the DMCII in either half-duplex or full-duplex mode, and normal DDCMP or DDCMP maintenance mode.

1-4

NOTE
The start-up sequence involves exchange of STRT,
STACK, and ACK messages between two DMClls
(see Appendix D).
At this point, the DMCII is in the DDCMP running mode. Any transmit buffer assigned to the
DMCII causes the DMCII to NPR (via DMA) the data from the PDP-II memory and be transmitted
on the serial line.
On transmit, the DMCII generates the DDCMP header and generates and transmits CRC characters.
On receive, the DMCII NPRs the received data to the PDP-II memory, provided there are receive
buffers assigned. The DMCII processes the received header, checks the CRC characters, and controls
acknowledgement of properly received data messages. The DMCII performs message sequencing, link
management, CRC error checking, retransmission, and some error reporting to the PDP-II.

1-5

PDP-11 PROGRAM

INITIALIZE
DMC11

VIA MASTER CLEAR

ASSIGN 128WORD BASE TABLE
DMC11 INITIATES THE
PROTOCOL START UP
SEQUENCE

+-+ VIA BASE IN COMMAND

SET UP PROPER
MODE
HALF-OR FULL-DUPLEX
NORMAL DDCMP OR
DDCM P MAINTENANCE

VIA CONTROL IN COMMAND

DMC11 IN DDCMP RUNNING MODE
AFTER COMPLETION OF DDCMP START SEQ.

"4
1~

ASSIGN TRANSMIT &
RECEIVE BU FFERS

TRANSMIT

VIA BUFFER ADDRESS/CHARACTE R

+-+ COUNT IN COMMANDS

RECEIVE

,
DMC11 (1) PROCESSES
DMC11 (1) GENERATES DDCMP
PROTOCOL HEADER, (2) GENERATES AND TRANSMITS CYCLIC
REDUNDANCY CHECK (CRe)
CHARACTERS

THE RECEIVED HEADER, (2)
CHECKS CRC CHARACTERS, (3)
CONTROLS ACKNOWLEDGEMENTS (ACKS) OF
PROPERLY RECEIVED DATA MESSAGES AND NEGATIVE ACKS (NAKS) FOR
ERROR MSGS.

I
THE DMC11 PERFORMS
MESSAGE SEQUENCING,
CRC ERROR CHECKING,
RETRANSMISSION,
SOME ERROR REPORTING
TO THE PDP-11, AND
LINK MANAGEMENT
MK·0767

Figure 1-3

DMCII Operation Sequencing

1-6

CHAPTER 2
INSTALLATION

2.1 SCOPE
This chapter provides all the necessary information for a successful installation and subsequent checkout of the OMCII microprocessor subsystem.
2.2 UNPACKING AND INSPECTION
Inspect the container and contents for damage. If any damage is found, notify the customer, record it
on the LARS form and take appropriate action.
There are two microprocessor options and four line unit options. Ensure that the contents agree with
the required parts associated with the option selected. Table 2-1 identifies the option, related parts and
descriptions.
2.3 MECHANICAL PACKAGING
The OMCII consists of a microprocessor module (hex) and a line unit module (notched hex). These
modules plug into any 0011-B (Revision E or later), OOll-C, 0011-0 or equivalent SPC system
unit. The microprocessor module must always plug into either slot 2 or 3 in the 0011-B or DOll-C.
The line unit module may be installed into any of the remaining slots. If two OMClls are installed into
a single DO II-B, then the line unit module plugs into slot 1 or 4.
The line unit does not interface with the UNIBUS, but picks up power and ground from the backplane, so module edge connectors A and B are not required. As a result, the corner of the module in the
vicinity of the A and B connectors has been removed. This allows the M8201 and M8202 to be installed
in the end SPC slots of the 0011-B, C, or 0 system interfacing units. The module plugs into connectors C, 0, E, and F, and fits over the UNIBUS cable connector or short length (approximately 2
1/2 inches) UNIBUS terminator that is installed in end slot connectors A and B.
The two modules are interconnected by a BERG 40-pin connector and a one-foot BC08S-1 cable. A
BC08R-l cable can be used instead of a BC08S-1 if the need arises (the shipping list requires a BC08S1).
2.4 PRE-INSTALLATION CONSIDERATIONS
Installation of the OMCII microprocessor/line unit should be done in three phases. The microprocessor is installed first, the line unit is installed second, then modules are checked and verified via
the diagnostic programs.
2.4.1 Configuration Considerations
The OMCII is located in the floating address space. Therefore, the address allocation is not the
limiting factor. The total OMCII throughput rate forms a more severe limitation on the number of
OMClls in a system.

2-1

Table 2-1

Microprocessor /Line Unit Options and Parts

Option

Parts

Description

Prerequisite

DMCII-AR

1. M8200-YA

Microprocessor with
DDCMP microcode for
remote applications

PDP-II

Used with M820I line
unit only

DMCII-DA

DMCII-FA

DMCII-AL

2. BC08S-I

Cable to interconnect
microprocessor and
line unit

3. EK-DMCMP-TM-002

DMCII IPL Microprocessor Technical
Manual

4. MPOOO76

Customer Print Set
CDMCII)

5. ZJ-2I6-RB

Software LIB KIT*

1. M820I

Line unit for remote
applications

2. BC05C-25

Cable for EIA/CCITT
V.24 interface

3. H325

Modem test connector

4. EK-DMCLU-MM-002

DMCII IPL Synchronous
Line Unit Maintenance
Manual

1. M8201

Line unit for remote
applications

2. BC05Z-25

Cable for CCITT V.35/
DDS interface

3. H3250

Cable test connector

4. EK-DMCLU-MM-002

DMCII IPL Synchronous
Line Unit Maintenance
Manual

1. M8200-YB

Microprocessor with
DDCMP microcode for
local applications
Used with M8202-XX
line units only

2-2

DMCII-AR

PDP-II

Table 2-1
Option

DMCII-MA

DMCII-MD

Microprocessor /Line Unit Options and Parts (Cont)

Parts

Description

2. BC08S-1

Cable to interconnect
microprocessor and
line unit

3. EK-DMCMP-TM-002

DMCIIIPL Microprocessor Technical
Manual

4. MP-00076

Customer Print Set
CDMCll)

5. ZJ-216-RB

Software LIB KIT*

1. M8202-YA

Line unit with 1 MEG
BPS integral modem

2. 12-12528-00

Cable test connector

3. EK-DMCLU-MM-002

DMCIIIPL Synchronous
Line Unit Maintenance
Manual

1. M8202-YD

Line unit with 56K
BPS integral modem

2. 12-12528-00

Cable test connector

3. EK-DMCLU-MM-002

DMCII IPL Synchronous
Line Unit Maintenance
Manual

Prerequisite

DMCII-AL

*ZJ-216-RB Software Library Kit contains the following diagnostic programs:
•

CZDMC Microprocessor Basic W /R and ~P Test

•

CZDME Line Unit DDCMP Test

•

DZDMF Line Unit Bit Stuff Test

•

CZDMG CROM and Jump Test

•

DZDMH DMCII free-running tests

•

DZDMO DMCII Overlay for Interprocessor Test Program

2-3

A single DMCII at 1M bps and in full-duplex mode is capable of transferring 250,000 X 8-bit characters per second (125,000 character/sec X 2 directions). Because the DMCII performs 16-bit word
transfers via NPR transactions to memory, approximately 125,000 NPRs per second or the rate of 8
microseconds/NPR is generated.
High-speed DMCIIs of 1M bps must be placed before all devices on the UNIBUS (including
UNIBUS repeaters), except unbuffered NPR devices such as RK1Is.
2.4.2 Power Requirements
Check the power supply before and after installation to ensure against overloading. The microprocessor/line unit total current requirements for the + 5 volt supply is approximately 8 amperes.
Additionally, the line unit requires ± 15 volts for the silos, level conversion logic, and integral modem.
Power requirements for the microprocessor/line units are listed below.
M8200 microprocessor + 5 volts @ 5.0 amps
M8201 line unit

+ 5 volts @ 3.0 amps
+ 15volts @ 0.03 amps
- I5volts @ 0.31 amps

M8202 line unit

+ 5 volts @ 3.0 amps
+ I5volts @ 0.18 amps
- 15volts @ 0.46 amps

2.4.3 Backplane
The DMCII requires two hex SPC slots, preferably two adjacent ones (refer to Section 2.3, Mechanical Packaging, for details). Section 2.6.1 provides preinstallation checkout procedures concerning
backplane slots, wire runs, and power supply pin locations.
2.5

DEVICE AND VECTOR ADDRESSES

2.5.1 Device Address Assignment
DMCII addresses are selected from the floating address space and are assigned as follows:
•

The floating address space starts at location 7600108 and extends to location 7640008.

•

The devices are assigned addresses in the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.

DJl1s
DHIls
DQIIs
DUlls
DUPlls
LKII-As
DMClls
DZlls
KMCIls
LPPlls
VMV21s
VMV31s
DWR70s
RL11/RLVII (for second device, only if two or more are used)

2-4

•

The first address of a new device type must start on a module 108 boundary, and a gap of
108 must be left between the last address of one device type and the first address of the next
device type.
The 108 gap must also be left for devices that are not installed in the system, but are passed
in the priority ranking list.

•

Multiple devices of the same type must be assigned contiguous addresses. Reassignment of
other device types already in the system may be required to make room for additional ones.
Examples of DMCII address assignments are provided in Section 2.5.3.

•

Both the DH11 and VMV31 require an address size of 208 per device installed in the system.
Also because of hardware requirements, the DH 11 's address must start on a multiple of 208,
such as 760020, 760040, 760060, and 760100.

2.5.2 Vector Address Assignment
DMC11 vector addresses are selected from the floating vector address space and are assigned as follows.
•

The floating vector address space starts at location 3008 and proceeds up to location 7778.

•

Floating vector addresses are assigned to devices sequentially and by device type as indicated below.
Table 2-2

Vector Address Assignment

Floating Vectors

Vector Size

Octal Modules

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
II.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.

4
4
4
4
2
2
4
4
2
2
4
4
4
4
4
4
8
12
4
4
4

10
10
10
10
4
4
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
4

DCll
KL11jDL11-A,B
DPll
DMII-A
DN11 Lines
DMII-BBjDHll MCU
DR11-A
DR11-C
PA611-Reader
PA611-Punch
LPD11
DT11
DX11
DLI1-C,D,E
DJl1
DH11
GT40
LPSll
DQ11
KWI1-W
DUll
DUPll
DV11
DV11 MCU

2-5

Table 2-2 Vector Address Assignments (Cont)
Floating Vectors

25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.

36.
37.
38.
39.

Vector Size

LK ll-A
OWUN
OMCII
OZII
KMCII
LPPII
VMV21
VMV31
VTVOI
OWR70
RLll/RLVII (for
second device,
only if two or
more are used)
RX02
TSII
LPAII-K
IPll/IP300

Octall\-lodules

4
4
4
4
4
4
4
4
4
4
2

10
10
10
10
10
10
10
10
10
10
4

2
2
4
2

4
4
10
4

•

If any device type is not used in a system, address assignments move up to fill the vacancies.

•

If additional devices are to be added to the system, the same device types must be assigned
contiguously after the original devices; devices not included in the initial system configuration must be assigned addresses which are relevent to their position in the sequence.
Reassignment of devices already in the system may be required. Examples of OMCll vector
address assignments are provided in Section 2.5..3.

2.5.3

Examples of Device and Vector Address Assignment

Example 1
The first device requiring address assignment in this example is a OH II (No.2 in the device address
assignment sequence; No. 16 in the vector address assignment sequence).
The only devices used are:
2 OHlis
20Qlls
1 OUPII
1 OMCll

2-6

Device
(Option)

Device
Address

Vector
Address

760010

Comment
Gap left for DJ11 (No. I on device address assignment
sequence) which is not used.

DHII

760020

300

First DHll

DHII

760040

310

Second DHII

760060

Gap between the last DH II used and the next device.

DQII

760070

320

First DQl1

DQll

760100

330

Second DQl1

DUPII

DMCII

760110

Gap between the last DQ 11 used and the next device.

760120

Gap left for DUlls not used.

760130

340

Only one DUPll

760140

Gap left between DUPll and next device.

760150

Gap left for LKII-As not used.

760160

350

760170

Only one DMCII
Gap left after the last device (in this case, the D M C 11)
to indicate that none follow.

Example 2
The only devices used in this example are:
1 DJl1
1 DHll
2 DQl1s
2 DUPlls
2 DMClls

Device
(Option)

Device
Address

Vector

Address

Comment

DJl1

760010

300

Only one DJ 11

760020

Gap left between DJ II and the next device.

760030

Gap. The next device, DH 11, must start on an address
boundary that is a multiple of 20.

2-7

Device
(Option)

Device
Address

Vector
Address

Comment

DHII

760040

310

Only one DH II

760060

Gap left between DH II and next device.

DQII

760070

320

First DQII

DQII

760100

330

Second DQII

760110

Gap left between DQ II and next device.

760120

Gap left for DUlls not used.

DUPII

760130

340

First DUPII

DUPII

760140

350

Second DUPII

760150

Gap left between the last DUPII and next device.

760160

Gap left for LK II-As not used.

DMCII

760170

360

First DMCII

DMCII

760200

370

Second DMCII

760210

Gap left after the last device (in this case the DMCII) to
indicate that none follow.

Example 3
Only one of each of the following devices are used in this example:
DCII
DJII
DHII

GT40
DQII
DUPII
DMCll

Device
(Option)

Device
Address

DCII
DJII

760010
760020

Vector
Address

Comment

300

DCII has a fixed device address.

310

Only one DJ II
Gap left between DJ II and the next device.

2-8

Device
(Option)

Device
Address

Vector
Address

Gap. The next device, DH II, must start on an address
boundary that is a multiple of 20.

760030
760040

DHII

320

OQII

760070

OUPII

330

GT40 has a fixed device address.

340

Only one DQ II

760100

Gap left between DQ II and next device.

760110

Gap left for DUlls not used.

760120

OMCII

Only one DH II
Gap left between DH II and next device.

760060
GT40

Comment

350

Only one DUPII

760130

Gap left between DUPII and the next device.

760140

Gap left for LKII-As not used.

760150

360

760160

Only one DMCII
Gap left after the last device (DMCII) to indicate that
none follow.

2.5.4 Interrupt Priority
Interrupt priority is selected by a priority plug on the M8200 microprocessor module. This plug is
preset to select priority 5 (BR5).
2.5.5

UNIBUS Loading

M8200-YX microprocessor:
I UNIBUS DC load
3 UNIBUS AC loads
M8201 or M8202-YX line unit:
No UNIBUS loads
2.6

MODULE INSTALLATION AND CUSTOMIZATION

2.6.1 Preinstallation Checkout Procedure
Before installing the microprocessor module, perform the following:
1.

Place high-speed DMClls (1M bps) before any UNIBUS repeaters.

Prepare the backplane slot that will accept the M8200-Y A/YB microprocessor by removing
the NPR GRANT (NPG) wire between pins CAl and CBI.

2-9

Do not remove the wire at the slot that will accept the M8201 or M8202-YX line unit.
When the M8200 is removed, the NPR GRANT wire must be replaced.
3.

Refer to Table 2-3 and ensure that the power supply voltages at the respective backplane pins
are within the tolerances indicated.

Table 2-3

Power Supply Voltages

Backplane
Pin

Minimum

Voltage
Nominal

Maximum

CIA2
CIB2
CIUI

+4.7SV
-14.2SV
+ 14.2SV

+S.OV
-IS.OV
+ IS.OV

+S.2SV
-IS.7SV
+IS.7SV

Verify that jumper WI on the M8200-Y A/YB is installed.
NOTE
This jumper should not be removed in the field. Removal is only done at the factory to inhibit the oscillator in the microprocessor clock logic during
automated module testing.

Refer to Sections 2.5.1 and 2.5.3 to determine the DMCll address. In the floating address
space (addresses 760010 through 764000), bits 13 through 17 are always ones (a function of
the PDP-II processor). Appendix A shows the PDP-II memory organization and addressing conventions. Bits 3 through 12 are selected by switches in the address decoding logic (see
Table 2-4). With the switch ON (closed), the decoder looks for a zero on the associated
UNIBUS address line. Bits 0, I, and 2 are decoded to select one of eight registers. Device
address selection switches are contained in one DIP switch package located in position E113
as shown in Figure 2-1. All 10 switches in the package are used. Correlation between switch
numbers and address bit numbers is shown in Table 2-4. The ON and OFF positions and the
switch numbers are marked on the package. The switches are rocker type and are pushed to
the desired position (see Figure 2-1).

Refer to Sections 2.5.2 and 2.5.3 to determine the DMCll vector address. Each drive interrupt
vector requires four address locations (two words) which implies only even-numbered addresses. A further constraint is that all vector addresses must end in a 0 or 4. The vector
address is specified as a three digit, binary-coded, octal number using UNIBUS data bits 08. Because the vector must end in 0 or 4, bits I and 0 are not specified (they are always 0) and
bit 2 determines the lease significant octal digit of the vector address (0 or 4).
The interrupt control logic generates two vector addresses: ROI interrupts generate vector
addresses of the form XXO, and ROO interrupts generate vector addresses of the form
XX4. For this method of operation, the state of bit 2 is selected by the logic, not by a switch.
The two most significant octal digits of the vector address are determined by switches in
lines 3-8 (Table 2-S). With the switch OFF (open), a 0 is generated on the associated
UNIBUS data line; with the switch ON (closed), a I is generated on the associated UNIBUS
data line.

2-10

The vector address selection switches are contained in one DIP package located in position
E76 (Figure 2-1). Only six of the ten switches in the package are used for the vector address.
The correlation between switch numbers and bit numbers is shown in Table 2-5. The ON
and OFF positions and the switch numbers are marked on the package. The switches are
rocker types pushed to the desired position.

Table 2-4 Guide for Setting Switches to
Select Device Addresses
Switch No.
Bit No.

10
12

9
II

4
6

3
5

2
4

Device
Address

OFF 760010
760020
OFF
OFF OFF 760030

760040
OFF
OFF 760050
OFF
OFF OFF
760060
OFF OFF OFF 760070
OFF

760100

OFF

760200

OFF OFF

760300
760400

OFF
OFF

OFF

760500

OFF OFF

760600

OFF OFF OFF

760700
761000

OFF
OFF

762000

OFF OFF

763000
764000

OFF

•

Switch is OFF (open) to respond to logical 1 on the UNIBUS .

•

Switch numbers are physical positions in switch package l.

2-11

ffil
n
D
3- ~N~:~: ~:;~I~I:~ 1

UNUSED
BYTE SEL 1 LOCKOUT (BS1)
UNUSED

A3 -

-- - - - - UNIBUS ADDRESS

BITS A3-A12

-A12

BITS 03-08

I I
• +

F
SWITCH ON SELECTS LOGICAL 0
DEVICE

ADDRESS

El13

SWITCH ON GENERATES LOGICAL 1

I [~~J

VECTOR
ADDRESS

rL __
Es5 --.J-,

r---'

L~~.J

E76

E75
BR PRIORITY
SOCKET

M8200
MODULE

MK·0768

Figure 2-1 Microprocessor Device and Vector Address Switches

2-12

Table 2-5 Guide for Setting Switches
to Select Vector Address
Switch No.
Bit No.

6
8

5
7

4
6

3
5

2
4

1
3

Vector
Address
300

310
320

330
340

350
360

370
400

500

600

•

Switch is ON (closed) to produce a logical 1 on the UNIBUS.

•

Switch numbers are physical positions in switch package 2.

2-13

700

Refer to vector address DIP - E76 in Figure 2-1. Verify that switches 7 and 9 are both OFF.
•

RUN INHIBIT (RI) switch 7 is normally set to OFF. Initialization of the microprocessor directly sets the RUN flip-flop which allows the microcode to be executed
immediately. If there is an internal malfunction or execution of a faulty microcode, it is
possible for the DMCII to hang the bus. In this case, it would not be possible to load
the diagnostics to determine the fault. Placing the RUN INHIBIT switch 7 to ON
clears the RUN flip-flop and allows the diagnostics to be loaded.

•

BYTE SELl LOCKOUT switch 9 inhibits all maintenance functions and capabilities
to allow the PDP-II program to directly clear the RUN bit and halt the microprocessor.
NOTE
Some diagnostics will not run if switch 7 and / or
switch 9 are ON.

•

Switches I through 6 are used for the vector address.

•

Switches 8 and 10 are not used.

Verify that the 8 ROMS in the upper right-hand corner of M8200- YX are of the correct
number and installed in the proper location.

ROM I
ROM2
ROM3
ROM4
ROM 5
ROM6
ROM7
ROM8

REMOTE
M8200-YA

LOCAL
M8200-YB

630A9
631A9
632A9
633A9
634A9
635A9
636A9
637A9

622A9
623A9
624A9
625A9
626A9
627A9
628A9
629A9

MK·0789

Verify that the BR5 priority plug on the M8200-YA/YB module is installed properly.

2-14

10.

Set up and check all appropriate switch settings and jumpers on the M820 I or M8202- Y A/Y D
line unit in accordance with the recommendations in Chapter 2 of the DMCll IPL Synchronous Line Unit Maintenance Manual (EK-DMCLU-MM-002).

II.

If the DMCll is to be set up for Remote Load Detect (RLD) application, refer to Appendix F
for proper switch settings of SW2 and SW3 on the M8201 /M8202- Y A/YD line unit module.

12.

• SW2

E87 on M8201
E90 on M8202

• SW3

E88 on M8201
E91 on M8202

Refer to DMCll IPL Synchronous Line Unit Maintenance Manual (Part no. EK-DMCLUMM-002) for additional details concerning switch and jumper configurations for M8201
and M8202 modules.

2.6.2 Installation Procedures
Additional illustrations relevant to the following procedures and figures are contained in the D M C II
Engineering Drawings (DMCII-0-8). Perform the following steps taking every precaution in routing
the cables and inserting the modules to ensure that cable wires are not broken (in the cable bending
process) and that ROM chips and the BR plug are not unseated by contact with adjacent modules.
I.

Power down the system.

Using cable BC08S-1/BC08R-l (which is a one-foot long, 40 conductor, flat mylar cable
with H856 female connectors at each end), insert one end of the cable into the H854 male
connector on the M8200-Y A/YB microprocessor module, as illustrated below.

RIBBED SIDE

BCOBS-1 or BCOBR-1

HB56

CABLE

(FEMALE CONN)
./

HB54
(MALE CONN)
MB200
OR
MB200-YA
OR
MB200-YB

HB56
(FEMALE CONN)
----~

(COMPONENT SIDE)

Figure 2-2 Inserting BC08S-1 /BC08R-l Cable into Microprocessor

2-15

MK-0769

LIFT TAB
TO OPEN

..---- LOCK TAB

«
M8200
OR
M8200-YA
OR
M8200-YB
SIDE 1

RIBBED
SIDE

B
A
C
K
P
L
A
N
E

SLIDE INTO
MICROPROCESSOR
SLOT

BC08R-1
or
BC08S-1
CABLE

J1
LU

COMPONENT SIDE

L.I..

• LI FT TAB LOCKS OPEN AS SHOWN
• SLIDE BOARD IN SLOWLY.
• AVOID HITTING ADJACENT
MODULE TO PROTECT
ROM CHIPS AND BR PLUG.

TO OPEN

MK·0770

Figure 2-3 Inserting Microprocessor Module (View 1)
VIEW 2

• ENSURE THAT
MODULE IS PROPERLY
SEATED .
• PRESS LOCK TABS
AS SHOWN.

M8200
OR
M8200-YA
OR
M8200-YB
SIDE 1

BC08R-1
or
BC08S-1
CABLE

COMPONENT SIDE

B
A
C
K
P
L
A
N
E

L.I..

MK-0770

Figure 2-4 Inserting Microprocessor Module (View 2)

2-16

Locate the proper backplane slot and remove the NPG wirewrap jumper between backplane
pins CAl and CBI.
NOTE
The NPG wire must be replaced if the microprocessor is removed from the system.

Insert the microprocessor module MS200-Y A/YB into the proper backplane slot as shown
in views I and 2 which follow (see Figure 2-6).

Locate the proper backplane slot and insert line unit module MS201 or MS202-Y A approximately three-quarters of the way into the slot as shown in the following illustration.
NOTE
Before installing the line unit module, ensure that the
jumpers and switches are set correctly for current installation.
Considerations:
a.

Module type (SPI)

Satellite operation requiring RLD capability,
SP2 = PASSWORD
SP3 = BOOT OFFSET

c.
6.

Physical half- or full-duplex configuration,
W6 on MS202 type line unit

Interconnec~ the line unit and microprocessor by connecting the opposite end of BCOSS-

l/BCOSR-I cable into the line unit as shown in the previous illustration.
7.

Install a BC05C-25 or BC05Z-25 cable into J2 on the MS201 line unit (see Figure 2-6). The
BC05Z-25 cable is a heavier cable and more difficult to route. Ensure that the connector for
either cable is inserted properly; proper orientation is simplified by the label, "this side up"
provided on the connector. The MS202 contains coaxial cables that are soldered and strainrelieved on the module.

Slowly insert the line unit the remaining distance into the slot. Ensure that the module is
seated properly.

Route the cables as shown in Figure 2-6.
•

Allow enough slack on the cables to avoid any sharp bends in any cables. Notice the
long loop recommended in Figure 2-6.

•

Excess cable length of the BCOSS-I/BCOSR-I must be folded very carefully and placed
against appropriate module as shown in Figure 2-6.
NOTE
Steps 11 and 12 are required for checkout procedures.

2-17

LINE UNIT
3/4 OF THE WAY IN SLOT

LINE UNIT

I
I

I/O CABLE {

MICROPROCESSOR

L----

l
I

I
I

SMOOTH
(SHIELDED)
SIDE

I
I
I

B
co

C
K

P
L
A
N

o
BCOBR-1 or BCOBS-1
CABLE

__________ -1- ____ _
LL

MK-0771

Figure 2-5 Inserting Line Unit Module and BC08S-1 /BC08R-l Cable

2-18

SEE FIGURE
2-3

SIDE VIEW OF BA11-F BOX

LOCAL APPL
HALF - FULL
DUPLEX

M8201
LU
M8200-YA
[J.P

M8200-YB
[J.P

M8202-YA
1~+-~~----IIrLU

M8202-YA
COMPo SIDE

----.
BC05C-25
OR
BC05Z-25
CABLE
(SEE FIGURE 2-3)

UPS

FOLD EXCESS
CABLE
AGAINST
LU MODULE

NOTE:
IF SPACE IS NOT AVAILABLE TO FOLD
BC08S-1 CABLES AGAINST LINE UNIT
MODULE, EXTEND EXCESS CABLE ALONG
EDGES OF MODULES. EXERCISE CAUTION
TO AVOID DAMAGING CABLES WHEN
CLOSING DRAWER.

MK-0772

Figure 2-6 Typical Cable Routing (BAII-F Box)

2-19

10.

Power up the system. At the proper backplane pins, ensure that the power supply voltages
are within the tolerances given in Table 2-3.

11.

Tie the two coaxial pigtails together via a 12-12528 test connector. See M8202-YA/YD in
Figure 2-7. This is unnecessary if HDX and W6 on the M8202 are installed.

12.

Connect M8201 cables to the respective test connectors as shown in Figure 2-7.

2.6.2.1 Installation in a BAII-K Box - The installation procedure for modules and associated cabling
is similar to the one given in Section 2.6.2. Cable routing is less of a problem because the cables exit the
module from the handle edge, requiring less cable bending en route to exiting the expander box. More
space is available at the top of the drawer, allowing ease in cable routing without the need for sharp
bending and close fitting of the cables, particularly when a BC05Z-25 one-inch diameter cable is
installed.
2.6.2.2 Installation in a 0011-0 Backplane - The DDII-D is a nine-slot backplane (see Figure 2-8).
When installing the modules in the DDI1-D, follow the cable routing procedures and exercise caution
as indicated in Section 2.6.2.

• • • • • 25 PIN CINCH

•

H325
TEST CONNECTOR

..._ _ _D_M_D_CA_1_1_ __
M8201
• • • • • 37 PIN CINCH

•
•

•
H3250

DMC 11

TEST CONNECTOR
FA
M8201
RECEIVE CABLE

12-12528
• • • • • COAXIAL TEST
CONNECTOR

DMC 11

MA - MD
M8202

TRANSMIT CABLE
MK-0773

Figure2-7 DMC11 Line Unit Turnaround Test Connectors

2-20

SLOTS

VIEWED
FROM MODULE
HANDLES

~----------------y ~---------------)

=
=

SLOTS 1,4, 7
LINE UNIT MODULES
MICROPROCESSOR MODULES
SLOTS 2, 5, 8
NOTE: INSTALL MODULES AND
ROUTE CABLES WITH CARE
AS INDICATED IN PREVIOUS
SECTIONS.

DD11-D
BACKPLANE

MK-0774

Figure 2-8 DD11-D Backplane

The nine slots available in the DD11-D imply that four sets (each set being a microprocessor and a line
unit) can be installed. However, as each set draws approximately 8 amps, four sets may create unserviceable cable routing as well as an overloading problem on certain power supplies. It is recommended
that a maximum of three DMC11 sets be installed in a given DD11-D. Slot selection for a three-set
installation is shown in Figure 2-8.
2.6.3

Checkout Procedure

Run the following diagnostic programs (with the test connector installed) to ensure proper
operation of the microprocessor and line unit (see Chapter 5). Each program should be run
through at least three passes with zero in the console switch register.
CZDMC

DMC11 basic W jR and microprocessor tests

CZDME

DMC11 DDCMP mode line unit tests

DZDMF

DMC11 bit stuff mode line unit tests

CZDMG

DMC11 CROM and Jump Test

DZDMH

DMCll free-running tests

2-21

Run the DEC/XII System Exerciser with the CXDMCBO, DMC-II module to ensure
proper system level operation.
1.

NOTE
To fully exercise the system under DEC/XII
as configured above, it is recommended that
bit 0 of switch register No. 1 (SR 1) be set to 1
and test connector H325, H3250, or 12-12528
be installed. This sets the DMCll to run in
external loopback mode. The data rate for the
M8201 is 10K bps and for the M8202-YX is
the integral modem speed.
An interpretation of a "soft error" as reported
by DEC/XII is provided in Chapter 5 of this
manual.

Remove test connector H325, H3250, or coaxial test connector 12-12528 from the end of the
cable.

Connect the modem cables to the 1110dem or another DMCll as shown in Figure 2-9. For
the M8201 line unit, connect to the modem. For the M8202- Y A/YD, connect to another
DMC11.

Run the Interprocessor Link Test program to ensure proper installation of the cables and
proper operation of the communication channel. Refer to Appendix G for the Link Test
procedure.

2-22

DMC11-AR
MICROPROCESSOR
M8200-YA

BC08R-1or
BC08S-1

DMC11-DA
LINE
UNIT
M8201

BC05C
MODEM

(EIA RS232-C
INTERFACE)

DMC11-AR
MICROPROCESSOR
M8200-YA

BC08R-1or
BC08S-1

BC05Z

DMC11-FA
LINE
UNIT
M8201

MODEM

(CCITT V.35
INTERFACE)

BC05Z =

(f)

:::>

1 INCH DIAMETER
CABLE.

REMOTE
APPLICATION

:::>

DMC11-AL
MICROPROCESSOR
M8200-YB

BC08R-1or
BC08S-1

DMC11-MA
LINE

REC.

REC.r - - - - ,
DMC11 - MA :

UNIT
XMIT\ M8202-YA I
M8202-YA
L--_ _ _~XMIT
L ____ -'I

LOCAL APPLICATION
(FULL DUPLEX)

r-----,

DMC11-MA
DMC11-AL
BC08S-1
REC. REC. I DMC11-MA I
MICROLINE
*W6~--"'" *W6
I
PROCESSOR 1'-----'1 UNIT
I
M8202-YA I
M8200-YB
M8202-YA
L ____

LOCAL APPLICATION
(HALF DUPLEX)

* JUMPER W6 ON
M8202 INSTALLED
MK-0775

Figure 2-9 DMCII Cabling

2-23

CHAPTER 3
PROGRAMMING INFORMATION

3.1 INTRODUCTION
This chapter contains general information necessary for PD P-II programming of the D M C 11 microprocessor. The information is presented by operational categories such as input transfers and output
transfers. Also included are descriptions of the UNIBUS control and status registers, microprocessor
control and status registers, and line unit control and status registers. The following major areas of
concern are discussed.
•

Interrupt vectors

•

Priority selection

•

PDP-II programming information

•

DMCII programming information

3.2 INTERRUPT VECTORS
The DMCII generates two vector addresses: XXO and XX4.
An interrupt through vector address XXO is generated by the microprocessor when:
1.
2.
3.

The PDP-II has set lEI,
The PDP-II requests the port (SEL 4 and 6) for input of a command to the DMC 11, and
The port becomes available, that is, no output command pending and the microprocessor
has no higher priority functions to perform (such as transmit and receive data processing).

The XXO interrupt occurs in conjunction with the setting of READY IN (RDI).
An interrupt through vector address XX4 is generated by the microprocessor when:
1.
2.

The PDP-II has set lEO,
The microprocessor has status or error information to give to the PDP-II (it has placed the
information in port SEL 4 and 6), and
The microprocessor has no higher priority functions to perform (such as transmit or receive
data processing).

The XX4 interrupt occurs in conjunction with the setting of READY OUT (RDO).
3.3 PRIORITY SELECTION
The priority for the interrupts is selectable on the microprocessor via a plug-in priority selection plug.
The microprocessor is shipped with a plug that establishes BR5 as the priority level.

3-1

3.4 PDP-II PROGRAMMING INFORMATION
Programming DMClls is simplified in that the DMCII implements the DDCMP (Digital Data Communication Protocol) in the DMCII microprogram. Although thorough understanding of the
DDCMP is not required, some familiarity with the protocol operation is useful in interpreting the
significance of the various error counters provided to assess the quality of the circuit connecting the
two computers. If a DMCII is to communicate with a different communication device which uses a
software implementation of DDCMP, the person programming the software implementation should
consult the DDCMP standard document, DDCMP, version 4.0 (Order No. AA-DS99A-TC), and
Appendix I.
3.4.1 UNIBUS Control and Status Registers
Communication of control and status information between the PDP-II and the DMCII is accomplished through four 16-bit UNIBUS Control and Status Registers (CSRs). These registers are both
byte and word addressable. The eight bytes composing the four registers are assigned the following
addresses: 76XXXO, 76XXX 1, 76XXX2, 76XXX3, 76XXX4, 76XXXS, 76XXX6, and 76XXX7, with
the ~ord addresses being the four even numbered addresses. The eight byte addresses are designated
BSELO through BSEL 7 and the four word addresses are SELO, SEL2, SEL4 and SEL6. The symbolic
addresses and format of the CSRs are shown in Figure 3-1.
3.4.2 Command Structure
The command set for the DMCII can be categorized as input and output commands. As opposed to
received and transmitted data, input commands are issued to the DMCII by the main CPU; output
commands are issued to the main CPU by the DMCII.
3.4.2.1 Input Commands - Input commands provide the vehicle for the main CPU to initialize, set up,
and assign receive or transmit buffers to the DMCII. These commands are listed below in the correct
order of user program issuance.
Initialization

is used to MASTER CLEAR the DMCII and place it in the initialized
state.

Base In

is the only command allowed to be assigned to the DMCll after initialization; it allows the DMCII to enter the DDCMP start-up states.

Control In

is used to set the DMCII in either half-duplex or full-duplex mode, and
maintenance or normal mode.

Buffer Address In

is used to assign transmit or receive buffers to the DMCl1.

Detailed format and field descriptions of each command are provided in Section 3.4.3.
The PDP-II program requests the data port (SEL 4 and 6) for input commands by setting REQUEST
IN (RQI), Bit S of BSEL O. The DMCII grants the request by setting READY IN (RDI), B7 of BSEL
O. The setting of RDI by the microprocessor may be delayed by any of the following conditions.
•

The DMCII is using the data port for output commands.

•

For a full-duplex DMCll, the DMCII may be busy receiving and transmitting data such
that servicing of input commands or supplying output commands is delayed.

3-2

15
BSEL 1

RDI

---

lEI

IN
RCV

INPUT
COMMAND

BSEL 0
SEL 0

lEO

OUT
RCV

OUTPUT
COMMAND

BSEL ~
RDO

wI
w

--BSEL 2
SEL 2

--BSEL 5

---

BSEL4
SEL4

DATA PORT FOR BA/CC, BASE, AND CNTL FORMATS

---

BSEL 7

BSEL 6
SEL 6

---

--MK·0776

Figure 3-1 Unibus Control and Status Registers (CSRs)

(Symbolic Addresses and Formats)

3.4.2.2 Output Commands - Output commands provide the vehicle for the DMCII to provide information to the main CPU. DMCII uses the output commands to convey two categories of information:
Buffer Address Out

is used to post normal completions of transmit or receive operations to
the user program.

Control Out

is used to convey the detection of error conditions.

Detailed format and field descriptions for each command are provided in section 3.4.4.
3.4.2.3 CSRs Bit Assignments - The four I6-bit CSRs are both word and byte addressable. Bytes
BSEL 0, 1, and 2 are used to set up input commands, maintenance bits, and output commands; BSEL
3 is not used. Bytes BSEL 4, 5, 6, and 7 are data ports which are defined in greater detail in the
following sections. Figure 3-2 is a summary of the control and status registers and data port usage for
input and output commands.
NOTE
The control and status registers are implemented
with Random Access Memory (RAM). At power on,
the CSRs all come up as ones. As part of the microprocessor initialization microprogram, only bytes
BSEL 0, I, and 2 are cleared. Then, bit IS of SEL 0
(RUN) is set by the microprogram at the end of its
initialization subroutine. SEL 0 must not be written
by the PDP-II until bit IS has been set by the microprogram.
3.4.2.4 BSEL 0 - Input Register - BSEL 0 is the low byte of address 76XXXO (see Figure 3-2). Table
3-1 describes the bit functions of BSEL O.
3.4.2.5 BSEL I - Maintenance Register - BSEL 1 (maintenance ·register) is the high byte of address
76XXXO (Figure 3-2). Switch #9 (E76) on the microprocessor module, BSEL 1 LOCKOUT (normally
OFF), can be turned on to prevent the PDP-II program from directly setting or clearing RUN, or
performing other maintenance functions in BSEL 1. BSEL 1 LOCKOUT disables the DMCII 's capability to initialize an unattended PDP-II computer system, but does not inhibit the program MASTER
CLEAR (bit 14). Table 3-2 describes the bit functions of BSEL 1.
NOTE
During program access of BSELI, care must be
taken to avoid inadvertent clearing of the RUN bit.
This stops the MP clock, stopping the D M C II.
3.4.2.6 BSEL 2 - Output Register - BSEL 2 is the low byte of address 76XXX2 (Figure 3-2). This
register contains control information relative to output command transfers from the DMCII to the
PDP-II program. Table 3-3 describes the bit functions of BSEL 2.
3.4.2.7

BSEL 3 - Reserved - This register is not used.

3.4.2.8 Base Input (BASE I) Command Format - SEL4 and bits 14 and 15 of SEL6 provide the first
address of a reserved block of addresses in the PDP-II memory (see Figure 3-2). The block size is 256
bytes. Upon assigning the BASE I address to the microprocessor, the PDP-II program must not
modify any locations within the assigned block.

3-4

RDI

lEI

RQI

INPUT COMMAND

2
IN
RCV

IN
RCV
BIT 2

COM~AND I
0

INPU;

SEL 0

INPU+
COMMAND
BIT 1 I BIT 0

BASE IN

CONTROL IN

RECEIVE BUFFER/CC IN

TRANSMIT BUFFER/CC IN

BASE IN COMMAND FORMAT
SEL 4

BUS ADDRESS

CONTROL IN COMMAND FORMAT

w
C,!)

«
C/)
=>
f-

a:
oa..

C3
BUFFER ASSIGNMENT (BA/CC INl COMMAND Fo.RMAT
BUS ADDRESS

SEL 4

BA 17,16

SEL6

CHARACTER COUNT

I
MK-0777

Figure 3-2 Summary of Control and Status Regist4:
Input Commands (Sheet 1 of 2)

3-5

7
RDO

6
lEO

..
5

2
OUT
RCV

OUT~UT
COM~AND

SEL 0

I
I

I
l
OUT
RCV
BIT 2

OUTPUT COMMAND

OUT~UT
COMMAND
BIT 1 I BIT 0

CONTROL OUT

RECEIVE BAICC OUT

TRANSMIT BAICC OUT

CONTROL OUT COMMAND FORMAT

SEL 4

EX
MEM

w
(.9

START
RECD

MAINT
RECD

BUF

OUT

SEL 6

(f)

::::>
I0::

BUFFER ASSIGNMENT (BA/CC OUT) COMMAND FORMAT

«
«
o

BUS ADDRESS

SEL 4

CHARACTER COUNT

SEL 6

a...

I-

BA17,16
I

MK-0778

Figure 3-2 Summary of Control and Status Registers:
Output Commands (Sheet 2 of 2)

3-6

Table 3-1

BSEL 0 Bit Functions

Bits

Name

Description

Reference
Section

0, I

Input command

These bits are encoded to define the type of input
command from the PDP-II program to the microprocessor.

3.4.3.2
3.4.3.3
3.4.3.4

Bit I Bit 0 Definition

IN RCV

0
I
I

I
0
I

Buffer Address/ Character Count In
(BA/CCI) command
Control In (CNTL I) command
Reserved
Base Input (BASE I) command

Defines the PDP-II buffer address (BA/CCI) command as either a transmit or receive operation:

3.4.3.4

Clear "0" =transmit operation
Set" I "
= receive operaton
Cleared by DMCII upon completion of the input
command transfer.
3,4

RESERVED

Not used (causes no action)

REQUEST IN(RQI)

Serves as an interlock bit in requesting the use of
the data port: Set by the PDP-II to request use of
the data port. Cleared by the PDP-II when the
data port has been loaded.

3.4.3.2
3.4.3.3
3.4.3.4

INTERRUPT
EN ABLE IN (lEI)

When set, allows the DMCII to interrupt to vector
address XXO if RDI (bit 7 of BSEL 0) is set.

3.4.3.2
3.4.3.3
3.4.3.4

READY IN (RDI)

RDI is a DMCII response to RQI indicating to the
PDP-II that it may load the data port (BSEL 4-7).
Cleared by the DMCII (following PDP-II clearing
of RQI) to indicate to the PDP-II that the data
port has been read and the input command transfer
is complete.

3.4.3.2
3.4.3.3
3.4.3.4

3-7

Table 3-2

BSEL 1 Bit Functions

Bit

Name

Description

8-12

Maintenance Bits

Reserved for maintenance use. (Refer to Chapter 5, Section 5.2, for bit descriptions.)

RESERVED

MASTER CLEAR (MCLR)

When set, MASTER CLEAR initializes both the microprocessor and the line unit hardware (this bit is self-clearing). The microprocessor clock is enabled and the RUN
bit is asserted.
The DMCII microcode is also placed in the initialized
state.

RUN

Controls the microprocessor clock. This bit is set by BUS
initialization or MASTER CLEAR which enables the microprocessor clock. RUN can be set or cleared for maintenance purposes from the UNIBUS.

Table 3-3

BSEL 2 Bit Functions

Bit

Name

Description

0, 1

Output Command

These bits are encoded to define the type of data transfer
from the microprocessor to the PDP-II program:
Bit 1 Bit 0 Description

OUT RCV

0
1
1

1
0
1

Buffer Address and Character Count Out
(BA/CCO)
Control Output
Reserved
Reserved

Defines a completed buffer (BA/CCO) by the DMCII as
either a transmit or receive.
Clear "0" = transmit buffer
Set" 1"
= receive buffer

3-5

RESER VED

INTERRUPT ENABLE
OUT (lEO)

When set, enables the DMCII, upon asserting RDO, to
generate an interrupt to vector address XX4.

READY OUTPUT (RDO)

Asserted by the DMCII to indicate that the data port
(BSEL 4-7) contains data for the output command defined by bits 0-2 of BSEL 2. Bit 7 must be cleared by the
PDP-II program after the data port has been read.

3-8

Bit 12 of SEL6 is called RESUME. If this bit is clear when a BASE I command is assigned, the
DMCII is placed in the DDCMP start state. If set when a BASE I command is assigned, the microprocessor resumes DDCMP operation as specified by the contents of the Base Table in the PDP-II
memory. See Section 3.4.3.2 for BASE I information.
3.4.2.9 Control Input (CNTL I) Command Format - The CNTL I format provides a means of setting
the DMCII in half-duplex or full-duplex mode, normal or maintenance mode. The control bits are
located in SEL 6 as shown in Figure 3-2 and described in Table 3-4. CNTL I must be executed
following BASE I.

Table 3-4

SEL 6 Bit Functions Associated
with Control In

Bit

Name

Description

0-7

RESERVED

Unused

DDCMP MAINTENANCE
(DDCMP MAINT)

When set by the PDP-II, the microprocessor enters
the DDCMP maintenance code where it remains until
it is subsequently initialized.

RESERVED

DDCMP HALF-DUPLEX
(DDCMP HD)

11,12,13

RESERVED

When set, DDCMP half-duplex operation is selected.
When cleared, DDCMP full-duplex operation is selected.

3.4.2.10 Buffer Assignment (BA/CCI and BA/CCO) Command Formats - The formats for BA/CCI
and BA/CCO are the same (see Figure 3-2). SEL4 contains the least significant 16 bits (0-15) of the 18bit bus address (BA). The two most significant bits (16 and 17) of this address are contained in bits 14
and 15 of SEL6. The remaining 14 bits (0-13) of SEL6 contain the character count (CC) in positive
notation, not 2's complement notation.
The microprocessor can stack a maximum of seven BA/CCs each for transmitting and receiving.
The BA/CCI command supplies new receive or transmit message buffers to the microprocessor.
For buffer completion reporting, BA/CCO returns the receive or transmit buffers to the PDP-II that
were successfully transferred by the microprocessor.
For buffer assignment commands, the CC represents:

1.
2.

The number of characters to be transmitted, or
The maximum size of a receive buffer.

For buffer completion status, the CC represents:
I.
2.

The number of characters in a buffer which was successfully transmitted, or
The number of characters in a buffer which was received successfully.

3-9

3.4.2.11 Control Output (CNTL 0) Command Format - The CNTL 0 command provides a means of
informing the PDP-II program of error conditions involving the DMCII hardware, PDP-II program,
communications channel, or the remote station.
The control bits and associated octal error codes are located in SEL 6 as shown in Table 3-5.

3.4.3 Input Commands (Format Descriptions)
The DMCII executes the following four forms of input commands (listed in the correct order of user
program issuance):
•

Initialization

•

Base In

•

Control In

•

Buffer Address In

NOTE
The programming procedure flow charts provided in
this section illustrate the non-interrupt mode for input command servicing. The intent is to demonstrate
a way of programming the DMCll, but should not
be interpreted as the only way.

The PDP-II program should set bits 0-2 of BSEL 0 to indicate the type of transfer and set bit 5, RQI,
to request the port. These bits may be set by a single instruction. The microprocessor responds by
setting bit 7, RDI, when the port has been assigned to the PDP-II program. When RDI has been set,
the PDP-II program should load the desired data into the data port (BSEL 4-7); then clears RQI. The
microprocessor takes the data and clears RDI, which completes the transfer.

Bit 6 of BSEL 0, Interrupt Enable Input (lEI), controls whether the PDP-II program receives an
interrupt (to Vector XXO) when the microprocessor has set RDI. Because of interrupt and service time,
it is most efficient for the PDP-II program to have input interrupts disabled and simply scan RDI one
or more times until it has been set by the microprocessor. While the PDP-II program is waiting, it
must be prepared to accept an output transfer because the microprocessor may have seized the port in
the interim (which takes priority over input).

Use of interrupts is convenient if the PDP-II program finds RDI clear after several scans; it can enable
interrupts by setting lEI with a BIS instruction. Following the setting of lEI and while waiting for
RDI, the PDP-II should ensure that lEI was set successfully. The DMCII interrupts the PDP-II (to
vector XXO) when the microprocessor has set RDI. The PDP-II program gets the interrupt in all
cases, even if the microprocessor has already set RDI at the time the program sets lEI. The program
can bypass any scanning if lEI is set when the program sets RQI.

3-10

Table 3-5
Error
Code
(Octal)

Sel 6 Bit Functions Associated
with Control Out
Error
Class

Bit

Name

Description

DATA CHECK

Indicates that a retransmission threshold
has been exceeded at the receiving end.
More than eight consecutive retransmissions have been requested via negative
acknowledgements (NAKs) that were
sent because of bad header, CRC, or bad
data CRC, etc.

Non-fatal

TIME-OUT

Indicates that the DMCll has not received a proper response for some outstanding messages from the remote end
of the link for a specified period (timeout interval), a broken communications
channel or a failure at either end of the
link for a single outstanding message.
This specified period is approximately
eight reply timer intervals, normally
about 24 seconds.

Non-fatal

NOTE
If the DMCll is in half-duplex mode and a message
is retransmitted 8 times due to receipt of a NAK for
any reason (such as line noise or no buffer availability), then the timeout interval will be very short
(approximately equal to the time required to retransmit eight times).
4

NO BUF

Indicates that a message was received
but no buffer was available; reported at
receive end only.

Non-fatal

NOTE
The DMCll will request retransmission via NAKS
eight times before reporting this error.
10

DDCMP
MAINTENANCE
RECEIVED

Indicates that a message in the DDCMP
maintenance format has been received
while running in normal DDCMP mode.
The message causing this condition is
lost and the PDP-II must reinitialize the
DMCII to enter the maintenance mode.

Fatal

LOST DATA

Indicates that the received message is
longer than the supplied buffer; reported
at the receive end only.

Fatal

RESERVED

3-11

Table 3-5 Sel 6 Bit Functions Associated
with Control Out (Cont)
Error
Code
(Octal)

Bit

Name

Description

100

DISCONNECT

Remote operation only; indicates that an
ON-to-OFF transition of the modem
Data Set Ready (EIA Interface Circuit
CC) has been detected after the data link
has been started.

Error
Class
Non-fatal

NOTE
On applications using switched network services via
dial-up modems, the ON-to-OFF transition of the
Data Set Ready could mean the connection has been
terminated and a redial or call setup is required.
200

DDCMP START
RECEIVED

Indicates that a DDCMP start message
was received when the protocol was in
the running state.

Fatal

400

NONEXISTENT
MEMORY
(NXM)

Indicates that a UNIBUS address timeout has occurred. This could have been
caused by the PDP-II program specifying an invalid transmit, receive buffer
address, or count, by a defective PD P-II
memory or other hardware error. This
error will only be reported at the end of
transmit or receive message processing.

Fatal

NOTE
NXM is only checked for data buffers (TX and RX
messages). It is not reported for UNIBUS timeouts
which occur during a Base Table Access or when
writing into locations 24 and 26.
Performance Note
Because NXM is only checked at the end
of a buffer, every access to the NXM
causes a 20 J,lsec pause in UNIBUS activity. This could affect performance of
other system components, such as disks,
tapes, and communication devices.
1000

PROCEDURE
ERROR

Indicates a procedure error on the part
of the PDP-II program where the requested input command cannot be honored because of a programming error.
This error can be caused by the following:

3-12

Fatal

Table 3-5 Sel 6 Bit Functions Associated
with Control Out (Cont)
Error
Code
(Octal)

Bit

Name

Error
Class

Description

•

specifying an invalid code in BSEL
0, bits I and 0 such as a code of I
(2),

•

trying to issue a CNTL I command
before supplying a base address,

•

trying to assign a base address a
second time, or

•

trying to issue a BA/CCI command
before supplying a base address.

The PDP-II program may create a procedure error by issuing a BASE I command a second time as a means of
shutting down the DMCII in an orderly
manner. For remote operation, Data
Terminal Ready (EIA Interface Circuit
CD) will be cleared as a result of this error, ceasing transmit receive activity.

NOTE
On fatal errors, the DMCII will exit from the
DDCMP running state. The DMCII must then
be initialized via MASTER CLEAR, BASE
IICNTL I, and BAICC sequences.
Non-fatal errors are reported by the DMCII to
inform the PDP-II program of some error conditions. Once the error condition is removed,
the DMCII will proceed normally.

3-13

The PDP-II program may clear lEI at any time other than when awaiting RDI.
1.

NOTE
When a MOV instruction is used to write to
SEL 0, bit 15 (RUN bit) of SEL 0 must always be set. In this case a BIS instruction is
recommended.
The PDP-II program should not begin a new
input transfer until the previous transfer has
been completed. If the PDP-II program
wishes to begin a new transfer immediately, it
should check that RDI has been cleared before setting RQI; this can be done by scanning
RDI until it has been cleared.

3.4.3.1 Initialization Command - The initialization command is the first command issued by a user
program at start up time to MASTER CLEAR the DMCII and place it in the initialized state. The
power up sequence and UNIBUS INIT signal also initializes the DMCIL In the initialized state, the
DMCII does not send or receive messages on the serial line but checks the incoming serial data for
enter MOP message for remote load detection.
In the initialized state, only the BASE I command can be assigned to the DMCII without causing a
procedure error. A procedure error causes the DMCII to write the PDP-II physical memory location
o to 400 8 with the content of the DMCII memory. This action could cause the PDP-II operating
system or program to fail because the PDP-II low core has been modified. Never assign any command
to the DMCII other than a BASE I command after power up, system initialization, or DMCII
MASTER CLEAR.
Initialization of the DMCII by the PDP-II is done by setting the MASTER CLEAR bit in BSEL 1.
The program should not access the CSRs for 2 microseconds following MASTER CLEAR. See Figure
3-3 for the programming procedure for initialization command. The recommended procedure is to
write MCLR (bit 14) with a one (1) and then wait for RUN bit 15 to be set by the DMCII to signal the
end of initialization, for example:
.
A:

MOY 040000,SELO
TSTSELO
BPLA

;SET MASTER CLEAR BIT
;WAIT FOR RUN BIT TO BE SET
;PROCEED TO DO BASE IN

NOTE
The MASTER CLEAR bit is self-clearing.
3.4.3.2 Base In Command - Figure 3-4 illustrates the format for the BASE I command which is the
only command allowed after DMCII initialization (Power Up, System Initialization, or MASTER
CLEAR).

3-14

INITIALIZATION COMMAND
ENTER

SET MASTER
CLEAR BIT VIA
MOV/BIS #40000,
SEL 0

WAIT FOR
SETTING OF
RUN BIT

YES

«INITIALIZATION EXIT:
DO BASE IN COMMAND
MK-0779

Figure 3-3 Programming Procedure for Initialization Command

3-15

RDI

lEI

IN
RCV

INPUT
COMMAND
1
1

lEO

OUT
RCV

OUTPUT
COMMAND

BSEL 1

BSEL 3
RDO

0
BSEL 0
SEL 0

--BSEL 2
SEL 2

--BASE ADDRESS

.....

SEL 4

SEL 6

0'\

MK-0780

Figure 3-4

Base In Command Format

The user program:

•

Sets up the BASE I command type (1 1) in SEL 0, bits 1 and 0, and sets bit 5 of SEL for a
request in RQI. Bit 6 of SEL 0, lEI, is set by the user program to permit the DMCII to
interrupt the main CPU when the data port (SEL 4 and 6) is available (RDI is set). This can
be done using the MOVB or BISB instruction.

•

Bit 7 (RDI) of SEL is set by the DMCII in response to the user program setting of RQI
informing the user program that data can be transferred into SEL 4 and 6.

•

. After loading the base address into SEL 4 and 6, the user program clears RQI.

•

After reading the base address from SEL 4 and 6, the DMCII clears RDI.

(See Figure 3-5)
The command BASE I assigns a Base Table (128-word table in PDP-II memory) to the DMCI1. The
Base Table then belongs to the DMCII until it is MASTER CLEARed by INIT or MASTER
CLEAR. The PDP-II program may examine, but must not alter, the contents of the Base Table. The
Base Table is described in Section 3.5.2.
Normally, the BASE I command is issued with the RESUME bit (bit 12 of SEL 6) cleared which
conditions the DMCII to enter the nDCMP start-up state of the DDCMP. With the BASE I command the RESUME bit set command causes the DMCII to:
•

Use the contents of the currently assigned Base Table as the initial state of the protocol.

•

Copy the 2008 bytes of the Base able in the PDP-II memory, starting at the specified Base
Table address, to DMCII internal memory (RAM). The DMCII internal memory is used
to store protocol constants, variables, state variables, error counter, and transmit/receive
buffers.

•

Force the DMCII to resume operation where it Was last stopped by means of an orderly
shutdown of the DMCII (refer to Section 3.5.5, Shutdown of the DMCII). There will be no
DDCMP start sequence in this case.

3.4.3.3 Control In Command - Upon completion of the BASE I command, the PDP-II program must
perform a CNTL I command to set the DMCII in half-duplex mode, full-duplex mode, normal
DDCMP, or maintenance (MOP) mode. Figure 3-6 illustrates the format for the CNTL I command
and Figure 3-7 shows the programming procedure for CNTL I.
The user program:

•

Sets up the CNTL I command type (0 1) in SELO, bits 1 and 0, and sets bit 5 of SEL for a
request in (RQI). Bit 6 of SEL 0, (lEI), is set by the user program to permit the DMCII to
interrupt the PDP-II when the data port is available (RDI is set). These bits can be set using
a BISB or MOVB instruction.

•

When the data port (SEL 4 and 6) is available, bit 7 of SEL
response to the setting of RQI by the user program.

•

Following the receipt of RDI, the PDP-II program loads the control information into SEL
4 and 6.

•

After the half-duplex/full-duplex mode bit 10 of SEL 6 and/or the DDCMP maintenance
bit 8 of SEL 6 is/are set up, the user program clears RQI.

•

After reading the control information from SEL 4 and 6, the DMCII clears RDI.

3-17

(RDI) is set by the DMCII in

BASE IN COMMAND
FROM:
INITIALIZATION
EXIT

SET UP COMMAND
TYPE AND ROI
IN SELB 0 VIA
MOVB/BISB
#43, SELB 0

NOTE: IF INTERRUPT DRIVEN INPUT
SERVICING IS DESIRED,
INTERRUPT ENABLE INPUT
(lEI) COULD BE SET, IN WHICH CASE,
THE INSTRUCTION COULD BE
MOVB/BISB # 143 SELB 0

WAIT FOR
SETTING OF
RDI

YES

..
LOAD 18 BITS BASE
ADDRESS WITH
RESUME BIT CLEARED
TO SEL AND SEL 6

NOTE: IF INTERRUPT DRIVEN INPUT SERVICING
HAS BEEN SELECTED EARLIER,
THE SETTING OF THE RDI
BIT, BY THE DMC11, IS ACCOMPANIED BY INTERRUPTING TO
VECTOR, XXO.

CLEAR ROI BIT
IN SELB 0 VIA
BICB #40,
SELB 0

SET OUTPUT
INTERRUPT
ENABLE BIT
IN BSEL 2

NOTE: FOR INPUT
COMMANDS, NON-INTERRUPT
MODE IS ILLUSTRATED,
FOR OUTPUT COMMANDS,
INTERRUPT MODE IS
ILLUSTRATED.

«BASE IN EXIT:
TO DO CONTROL IN
MK·0781

Figure 3-5

Programming Procedure for Base In Command

3-18

3
BSEL 1

2
IN
RCV

BSEL 3

---

INPUT
COMMAND
1
0

BSEL 0
SEL 0

--BSEL 2
SEL 2

SEL 4
W
I

......

\,0'

SEL 6

MK-0782

Figure 3-6

Control In Command Format

CONTROL IN COMMAND
FROM:
BASE IN EXIT

WAIT FOR
CLEARING OF
RDI

*NOTE: NORMALLY, SETIING OF RDO
(BIT 7) OF BSEL 2 SHOULD BE
_ _ ____._ TESTED HERE. BECAUSE OUTPUT
SERVICING IS INTERRUPT DRIVEN
(lEO IS SET), RDO IS NOT
CHECKED

YES

SET UP COMMAND
TYPE AND RQ1
IN SELB 0 VIA
MOVB/BISB #41
SELB 0

WAIT FOR
SETIING OF
RDI

NOTE: IF INTERRUPT DRIVEN INPUT SERVICING IS
DESIRED, INTERRUPT
ENABLE INPUT (lEI) COULD
BE SET, IN WHICH CASE,
THE INSTRUCTION COULD BE
MOVB/BISB # 141 SELB 0

------.-

* SEE NOTE ABOVE

------.-

NOTE: IF INTERRUPT
DRIVEN INPUT SERVICING
HAS BEEN SELECTED EARLIER,
THE SETIING OF THE RDI
BIT, BY THE DMC11, IS ACCOMPANIED BY INTERRUPTING TO
VECTOR, XXO.

YES

SET MODE DESIRED
(SET BIT 10 FOR
HALF-DUPLEX &
SET BIT 8 FOR DDCM P
MAINT) - INTO SEL 6

CLEAR RQI BIT
IN SELB 0 VIA
BICB #40, SELB 0

«CONTROL IN EXIT
TO ASSIGN RECEIVE/TRANSMIT BUFFERS
OR
SERVICE OUTPUT COMMANDS
MK-0783

Figure 3-7

Programming Procedure for Control In Command

3-20

3.4.3.4 Buffer Address/Character Count In Command - The command format is presented in Figure
3-8. This command provides the user program with the mechanism for assigning transmit and receive
buffers (see Figure 3-9).
CAUTION
In order to assign a transmit or receive buffer to the
DMCII, it is imperative that successful BASE I and
CNTL I commands have been previously issued to
the D M C II. Otherwise, a procedure error will occur
which will write into the PDP-II low memory area
and subsequently crash the operating system software.
The user program:
•

Sets up the command type (0 0) in bits 1 and 0 of SEL O.

•

Bit 2 of SEL 0 is cleared for transmit buffer address and set for receive buffer address. Bit 6
of SEL 0, lEI, is set by the user program to permit the DMCII to interrupt the main CPU
when the data port is available. These bits can be set using the MOVB or BISB instruction.

•

Bit 5 of SEL 0 is set for RQI.

•

When the data port is available, bit 7 of SEL 0, RDI, is set by the DMCII to inform the user
program that data can be loaded into SEL 4 and 6.

•

In response to RDI, the PDP-II program loads SEL 4 with the low-order 16 bits of the
buffer address, bits 15 and 14 of SEL 6 with the high-order bits of the address, and bits 13
through 0 of SEL 6 with the 14-bit character count.

•

After the user program has cleared RQI, the DMCII reads SEL 4 and 6, then clears RDI.

For data transmission, the PDP-II program may queue up to seven buffers by supplying buffers to the
DMCII at a faster rate than the DMCII returns them. The PDP-II program must not assign more
than seven transmit buffers to the DMCII at any given time. Otherwise, data integrity may be lost.
Buffers from 1 to 16,383 bytes long may be used, but the buffer size should be limited to a practical
maximum size which is dependent on the error rate of the communications facility. Each buffer corresponds to a single DDCMP data message. With high speed (1M bps) DMCIls, maximum message size
is limited by CPU type and UNIBUS activity because of the need for prolonged periods of frequent
memory access.
For data reception, the PDP-II may queue up to seven empty buffers by supplying them to the
DMCII at a faster rate than the DMCII returns them. The PDP-II program must not try to assign
additional receive buffers if seven are already outstanding, or data integrity may be lost. The character
count for the receive buffer must be large enough to accommodate the longest message expected. The
PDP-II should ensure that a receive buffer is always assigned.
CAUTION
A receive buffer starting at an odd address boundary
should not be assigned to the D M ell. Doing this
may create a race condition in the DM CII and cause
the system (UNIBUS) to hang. This is a catastrophic
system failure requiring system initialization.

3-21

7
RDI

ROO

--BSEI 0
SEL 0

lEI

IN
RCV

INPUT
COMMAND
0
0

lEO

OUT
RCV

OUTPUT
COMMAND

--BSEL 2
SEL 2

--TRANSMIT/RECEIVE BUFFER ADDRESS

SEL 4

--CHARACTER COUNT

BA 17, 16

SEL 6

W
I

tv
tv
MK-0784

Figure 3-8

Buffer Address/Character Count In Command Format

BA/CC IN COMMAND
FROM:
CONTROL IN EXIT

r----- - - - --.....- - - - - - . . ,
-

*NOTE: NORMALLY, SETTING OF ROO
(BIT 7) OF BSEL 2 SHOULD BE
TESTED HERE. BECAUSE OUTPUT
~ SERVICING IS INTERRUPT DRIVEN

WAIT FOR
CLEARING OF
RDI

(lEO IS SET), ROO IS NOT
CHECKED
YES

SET UP COMMAND
TYPE & ROI IN
SELB 0 VIA
MOVB/BISB #40
SELB 0

SET UP COMMAND
TYPE & ROI IN
BSEL 0 VIA
MOVB/BISB #44
SELB 0

NOTE: IF INTERRUPT DRIVEN INPUT SERVICING IS
DESIRED, INTERRUPT
ENABLE INPUT (lEI) COULD
BE SET, IN WHICH CASE,
THE INSTRUCTION COULD BE
MOVB/BISB # 144 SELB 0

WAIT FOR
SETTING OF
RDI

YES

* SEE NOTE ABOVE
LOAD 18-BIT
BUFFER ADDRESS &
CHARACTER COUNT
INTO SEL 4 &
SEL 6

CLEAR ROI BIT
IN SELB 0 VIA
BICB #40 SELB 0

«BA/CC IN EXIT

L .!'~I~N~~~B~F~R~ _..J

MK-0785

Figure 3-9

Programming Procedure for BA/CCI Command

3-23

3.4.4 Output Command (Format and Field Descriptions)
The DMCII communicates with the CPU by the following two categories of information.
1.

Buffer Address/Character Count Out (BA/CCO) - Information pertinent to the normal
completion of data transfers.

Control Out (CNTL 0) - Information concerning detection of an error condition.
NOTE
The programming procedure flowchart (see Figure 310) illustrates the interrupt mode for output command servicing. The intent is to demonstrate a way of
programming, but should not be interpreted as the
only way.

31.4.4.1 Buffer Address/Character Count Out (BA/CCO) Command - This command is used to post
the normal completion of data transfer operations to the user program. The command format is
presented in Figure 3-11. BA/CCO occurs upon successful completion of a transmit or receive buffer.
RX (Bit 2= 1)

The message has been received with no errors and transferred to the buffer in
main memory. An ACK response is sent to the sending station.

TX (Bit 2=0)

An ACK response has been received for the transmitted message, indicating
error-free reception at the receiving station.

The DMCII issues output commands in two steps. First, the data pertinent to the command being
issued is stored in SEL 4 and 6. Once this data storage is complete, the DMCII sets the RDO bit and
command identity bits in BSEL 2 and generates an interrupt through vector XX4 if the lEO bit is set.
If the command issued is a Buffer Address Out (BAO), the IN RCV (bit 2) is set to 1 to indicate that
the completion posted involves a receive data operation, or cleared to designate a completion posting
for a transmit data operation. Generally, processing an output command involves the following steps:
•

The user program checks for RDO set. This can be done through periodic checking or by
waiting for an interrupt, assuming that interrupts are enabled.

•

When RDO is detected as set, the user program checks BSEL 2, bits 0, 1, and 2, to determine
the type of completion (receive or transmit, fatal or non-fatal error), then reads SEL 4 and 6,
and processes as necessary.

•

Upon reading the data port (SEL 4 and 6), the user program clears RDO to inform the
DMCII of port availability. (See NOTE in Section L of Appendix I.)

3.4.4.2 Control Out (CNTL 0) Command - The DMCII informs the PDP-II program of unusual or
error conditions involving the communications channel, remote end of the link, DMCII hardware, or
PDP-II program by means of a CNTL 0 command. Some errors are advisory in nature and normal
operation may continue. Others are fatal and require the PDP-II program to initialize the OMCI1.
Figure 3-12 illustrates the format for this command.
The OMCII issues a CNTL 0 command in two steps. First, the data error code is loaded into SEL 6.
Then, the DMCII sets the ROO bit in SEL 2. If the lEO bit is set, an interrupt is generated to vector
XX4. The error code is listed and explained in Table 3-5. To process the CNTL 0 command, follow
the steps given in Section 3.4.4.1.

3-24

OUTPUT COMMANDS SERVICING
PROCEDURE*
* NOTE:
IN THIS PROCEDURE, THIS
ROUTINE IS ENTERED VIA

YES

AN INTERRUPT TO VECTOR XX4.

YES

RECEIVE BA/CCO
HANDLE THE
SUCCESSFULLY
RECEIVED BUF

TRANSMIT BA/CCO
HANDLE THE
SUCCESSFULLY

TAKE APPROPRIATE
ACTION TO
CORRECT ERROR
CONDITIONS

TRANSMITTED
BUFFER

CLEAR RDO
IN BSEL 2

LOG ERROR
AS FATAL

RETURN

ON FATAL ERROR. DMC11
EXITS FROM THE DDCMP
RUNNING STATE, THE
DMC11 MUST BE REINITIALIZED
VIA MASTER CLEAR FOLLOWING
ITS OCCURENCE

MK-0786

Figure 3-10

Programming for Output Commands Servicing Procedure

3-25

BSEL 1

7
RDI

---

lEI

IN
RCV

INPUT
COMMAND

BSEL 0
SEL 0

lEO

OUT
RCV

OUTPUT
COMMAND
0
0

--BSEL 3

ROO

BSEL 2
SEL 2

--SEL 4

TRANSMIT/RECEIVE BUFFER ADDRESS

--SEL 6

CHARACTER COUNT

BA 17, 16

MK-0787

Figure 3-11

~
I

--BSEL 1

Buffer Address/Character Count Out Command Format

RUN

RDI

lEI

2
IN
RCV

BSEL 3

---

INPUT
COMMAND

BSEL 0
SEL 0

--BSEL 2
SEL 2

ROO

SEL 4

--EX
MEM

START
RECD

MAINT
RECD

SEL 6
BUF

MK-0788

Figure 3-12

Control Out (CNTL 0) Command Format

3.5

PROGRAMMING HINTS

3.5.1 DMCII Start-Up
Start-up is the process of initializing the protocol states and variables, and synchronizing both stations
on a link. The OOCMP start-up sequence is initiated once the OMCII is assigned a BASE I command
with the RESUME bit cleared. The PDP-II program is not informed of the completion or failure to
complete the start-up sequence. The PDP-II must wait for the buffer return from the OMCII after a
successful transmission or reception of a data message. It is recommended that a BASE I command
with the RESUME bit cleared be issued to the OMCII and be followed by a CNTL I command to set
the DMCII in either full-duplex or half-duplex mode, normal DDCMP, or maintenance mode.
3.5.2 DMCII MASTER CLEAR
DMCII master clear can be performed by either system initialization, power fail, or setting bit 14 of
SEL O. When master clearing the DMCII by the software, consideration must be given to current
activity within the OMCII microprocessor and its line unit.
In DOCMP mode (normal operation), an ROO for a receive buffer completion is given to the PDP-II
as soon as the BCC for the received message is verified. Following PDP-II notification, the ACK for
the message is placed in the transmit silo for response to the station that sent the message. If software
initializes the OMC based on receipt of the ROO, it is likely that the ACK will not be sent; the ACK
message may not have been shifted onto the serial line before the clear signal initialized the line unit.
Similarly, in DOCMP maintenance mode an ROO for transmit completion is indicated to the PDP-II
as soon as the last data character of the message is placed in the transmit silo. Again, software initialization immediately following the ROO clears the line unit and aborts the message.
In both of the above cases there is a worst case delay which must be timed by software, prior to
initialization. The delay consists of the time required to transmit possibly 64 characters in the silo, two
characters of CRC and one character in the shift register, at the serial line rate (a total of 67 characters
or 536 bits).
A timer should be programmed as part of the initialization routine. This code would only be executed
when the DMCII is to be initialized after one of the following:
•

ROO for BA/CCO signaling RECEIVE DONE for ODCMP message, or

•

ROO for BA/CCO signaling TRANSMIT DONE in DDCMP maintenance mode.

To calculate the delay required, the following formula should be used:
T = 536

x
where:
T = the time delay in seconds.
X = the serial line speed in bits per second.
536 = the total number of bits that should be considered as being in transit.
Y = the clear to send (CTS) delay time in seconds.

3-27

Examples
1.

For link with M8202-Y A line units (l M bps):

536
T= - - - +0.0001
1,000,000

T = .000636 sec. or 636 microseconds.

For a link using M8201 and 2400 bps modem, with a 150 ms. CTS delay.

T =

536

+ 0.15

2,400

T = .373 sec. or 373 milliseconds.
When the DMCII is cleared during operation, even with worst case timing, there is no guarantee that
data in the silo reaches its destination, that is, an ACK which is given the time to be transmitted, but
gets garbled on the line, is not recognized at the destination. Clearing the DMCII that sent the ACK
may cause the other end to time out (looking for a valid response). Failure to provide enough delay
time before MASTER CLEARing the DMCII results in a protocol hang -sondition in normal
DDCMP mode and the loss of the MOP message in DDCMP maintenance mode.
3.5.3 Error Reporting
On start up, the DMCII is assigned a BASE I command which allocates to the DMCII a 4008 byte
long Base Table from the PDP-II memory. The DMCII uses part of this Base Table for keeping a
copy of error counters, transmit and receive buffer queues, and protocol constants and variables. The
DMCII Base Table is shown in Figure 3-13.
3.5.3.1 Cumulative Error Counters - The DMCII keeps six cumulative error counters. Upon occurrence of any fatal errors, the DMCII updates the Base Table. Approximately every second an attempt
may be made to update the error counters. This attempt is only successful if the microcode is in its idle
loop. Cumulative error counters are listed in Table 3-6.
3.5.3.2 Threshold Counters - The DMCII has two threshold counters which notify the PDP-II program of a persistent error condition. Threshold counters operate by counting consecutive errors of a
given class and trigger a notification to the user when the threshold value of eight has been reached.
The threshold counters are identified as NAKS Transmitted and REPS Transmitted.
When the NAKS Transmitted threshold counter reaches a count of eight, a CNTL 0 command is
generated by the DMCII with an error code of 1 (DATA CHECK ERROR) or an error code of 4 (NO
BUF) in BSEL 6. When the REPS Transmitted threshold counter reaches a count of eight, a CNTL 0
command is generated with an error code of 2 (TIME OUT ERROR) in BSEL 6. These errors are not
fatal. Once the error condition is removed, the DMCII proceeds normally.
3.5.4 Power Fail Recovery
The DMCII stores the protocol information internally in RAM memory. DMCII power fail recovery
may not be successful because the contents of the DMCll memory will have been lost after power
failure. Therefore, the software should be designed to reinitialize the DMCll using software-maintained information about transmit and receive messages pending.

3-28

Table 3-6

Cumulative Error Counters

PDP-II Base
Address

Trans/Rec

Error

Base + 5

N AKS Received

All

Base + 6

NAKS Sent

No Buffer Available

Base + 7

NAKS Sent

Bad Header BCC

Base + 10

NAKS Sent

Bad Data BCC

Base + II

REPS Sent

Base + 12

REPS Received

No Buffer Available
Bad Header BCC
Bad Data BCC

3.5.5 Shutdown of the DMCII
The PDP-II program may shut down the DMCII by creating a procedure error, that is, issue a BASE
I command a second time. After successfully assigning this second BASE I command (which forces a
procedure error), the DMCII terminates protocol, returns all successfully received data messages, and
all acknowledged transmitted data messages, posts all CNTL 0 currently queued, and finally posts a
CNTL 0 command with an error code of 10008 (Proc Err) in SEL 6. The software should handle all
these buffer returns and CNTL 0 commands from the DMCII until the CNTL 0 with the error code
of 10008 is processed.
NOTE
When shutting down the DMCII, it is the responsibility of the PDP-II program to ensure that there is
no outstanding transmit buffer at either end of the
link. Otherwise, a situation could occur where one
station shuts down after receiving the good message
and sending out an ACK. This ACK could be lost and
the remote station will not complete the transaction.
This is an increasing problem on dial half-duplex
links where the line goes on hook before the transmission is completed.
When a procedure error is forced, the DMCII updates the Base Table in the PDP-II memory via
DMA transfers. If there is a hardware problem in memory or the Base Table assigned to the DMCII is
located in nonexistent memory, the DMCII will not detect this condition.
There are some illegal ways of generating procedure errors on the DMCII, such as issuing the following commands to the DMCII before it is assigned a Base Table via a BASE I command.
•

A CNTL I command

•

A transmit or receive BA/CCI command

•

An invalid code of (I 0) in BSEL 0, bits I and a in an input command

3-29

BASE TABLE
ADDRESS (PDP-ll
BASE ADDRESS

BASE + 0
BASE + 1
BASE + 2
BASE + 3
BASE + 4
BASE + 5
BASE + 6
BASE + 7
BASE + 10
BASE + 11
BASE + 12
BASE + 13
BASE + 16
BASE + 17
BASE + 20
BASE + 25
BASE + 34
BASE + 37
BASE + 44
BASE + 51
BASE + 56
BASE + 63
BASE + 64
BASE + 65
BASE + 73
BASE + 101
BASE + 107
BASE + 115
BASE + 123
BASE + 131
BASE + 137
BASE + 145
BASE + 146
BASE + 147
BASE + 150
BASE + 151
BASE + 152
BASE + 153
BASE + 154
BASE + 155
BASE + 156

MICROPROCESSOR MAIN MEMORY ASSIGNMENTS

INTERNAL DMC·l1
MEMORY
000000
000001
000002
000003
000004
000005
000006
000007
000010
000011
000012
000013
000014
000015
000016
000017
000022
000023
000024
000031
000036
000043
000050
000055
000062
000067
000070
000071
000077
000105
000113
000121
000127
000135
000143
000151
000152
000153
000154
000155
000156
000157
000160
000161
000162

NAKSR=O
NAKST=NAKSR+l
REPSR=NAKST+l
REPST=REPSR+l

NP=REPST+3
NTLR=NP+l
NHDR=NTLR+l
NDATR=NHDR+l
NTLS=N DATR+l
NHDS=NTLS+l
NDATS=NHDS+l
REPCS=NDATS+l
REPCR=REPCS+l
BASE=REPCR+l
SRC=BASE+3
ERC=SRC+l
RCL1=ERC+l
RCL2=RCL 1+5
RCL3=RCL2+5
RCL4=RCL3+ 5
RCL5=RCL4+ 5
RCL6=RCL5+5
RCL7=RCL6+5
STC=RCL7+5
ETC=STC+l
( TML1=ETC+l
TM L2=TM L 1+6
TML3=TML2+6
TML4=TML+6
TML5=TML4+6
TML6-=TML5+6
TML7=TML6+6
TML8=TML7+6
T=TML8+6
ST+T+l
ISP17=ST+l
IMG10=ISP17+1
IMG11=IMG10+1
IMG12=IMG11 +1
IMG14=IMG12+1
IMG16=IMG14+1
IMG17=IMG16+1
TYPTAB=IMG17+1

;NAKS RECD--DYNAMIC
;NAKS TMTED--DY&NAMIC
;REPS RECD--DYNAMIC
;REPS TMTED--DYNAMIC

;CONSTANT 0
;NAKS-MSG NO BUFFERS CUMUL.
;NAKS-MSG HEADER BAD
;NAKS-DATA BAD
;NAK SENT--NO BUFFERS
;NAK SENT BAD HEADER
;NAK SENT BAD DATA
;REPS SENT CUMUL
;REPS RECD CUMUL
;CORE TABLE BASE ADDRESS
;START OF INPUT CHAIN--NEXT RECV DONE
;END OF INPUT CHAIN
;RECEIVE LINK # 1
" #2
" #3

;START OF OUTPUT CHAIN---NEXT TMT DONE
;END OF TRANSMIT CHAIN
;TRANSMIT LINK # 1
" #2
" #3

;TYPE FIELD
;SUBTYPE FIELD
;MSG ACKED IMAGE
;IMAGE OF BIT 1 OF SP10
;IMAGE OF SP11
;IMAGE OF SP12
;IMAGE OF SP14
;IMAGE OF SP16
;IMAGE OF SP17
;TYPE TABLE--;72 TYPE TABLE REP
;73 "
" NAK
M K -0843

Figure 3-13

DMCII Base Table

(Sheet 1 of 2)

3-30

BASE + 160

000164

TYPSTI=TYPTAB+2

;74 TYPE TABLE START
;75
.. STACK

BASE + 163
BASE + 165
BASE + 166
BASE + 167
BASE + 170

000167
000171
000172
000173
000174

BC=TYPSTI+3
ISP11 =BC+2
ISP12=ISP11 +1
INCONS=ISP12+1
RTH RS=I NCONS+1

;RECEIVE BYTE COUNT
;SP11 IMAGE
;SP12 IMAGE
;IN CONTROL CSR IMAGE
;RECV THRESHOLD LINK

;ALL LOCATIONS FROM 200 ON ARE NOT WRITIEN OUT DURING A TABLE UPDATE
000210
000211
000240
000241
000242
000400

*
RCL #

**
TML#

LOCATION
1 BIT 0
2

TABST=210
PRTST=TABST+1
NXTlNT=240
NXTSP=NXTINT+1
INTSTK=NXTSP+1
MMEND=400

;TABLE UPDATE STATE
;PORT STATE
;NEXT INTERRUPT POSITION
;END OF INTERRUPT CHAIN
;STACK OF INTERRUPTS
;MAIN MEMORY END

3
4
5

DESCRIPTION
BUFFER ASSIGNED FLAG
ADDRESS LOW BYTE
ADDRESS HIGH BYTE
EXTENDED MEMORY BIT & CHARACTER COUNT HIGH BYTE
CHARACTER COUNT LOW BYTE

LOCATION
1 BIT 0
BIT 1
2
3
4
5
6

DESCRI PTION
BUFFER ASSIGNED FLAG
TRANSMITIED FLAG
MESSAGE NUMBER
ADDRESS LOW BYTE
ADDRESS HIGH BYTE
EXTENDED MEMORY & CHARACTER COUNT HIGH BYTE
CHARACTER COUNT LOW BYTE
MK-0842

Figure 3-13 DMCII Base Table
(Sheet 2 of 2)

3-31

CAUTION
These illegal procedure errors force the D M C II to
update 200s bytes of its memory to the PDP-II
memory starting at physical location O. This action
corrupts the PDP-II low core area and causes
serious software failure.

NOTE
After a power failure, the operating software must
immediately MASTER CLEAR the DMCII and
assign a BASE I command and CNTL I command
before attempting to use the DMCI1. Otherwise, an
ILLEGAL PROCEDURE ERROR is created and
the operating system fails.

3.5.6 Modem Control
For a DMCII-AR microprocessor, Data Terminal Ready (DTR) is asserted continously after a
DMCII MASTER CLEAR. DTR is dropped as a result of any fatal error or procedure error. The
recommended procedure for disconnecting the link is to assign a second BASE I command and allow a
minimum of 150 ms before issuing the Initialization command. When the DMCll has entered the
DDCMP running mode (start-up sequence completed), an ON-to-OFF transition of DATA SET
READY causes the DMCII to generate a CNTL 0 command with an error code of 1008 (DISCONNECT ERROR). Note that the DMCII-AR, after assignment of a base address, attempts to
send a start message. This causes the M8201 Line Unit to assert REQUEST TO SEND (RTS) and wait
for CLEAR TO SEND and MODEM READY signals from the modems. Problems may result with
some modems and their ability to work with an Automatic Calling Unit (ACU) of the BELL 801 type
or equivalent.

The sequence of events are:
•

A CU makes the call

•

Receiving modem answers

•

Receiving modem puts out a carrier and answer tone simultaneously.

Because the request to send from the DMCII is on, ACU then interprets these events as a line busy
condition and terminates the call. For DMCII-AR programming procedures in Auto-Dial/Auto Answer Applications, see Appendix J.

3-32

NOTE
The DMCII-AR does not monitor a carrier
detect signal.
The DMCII-AR drops REQUEST TO
SEND for about I-bit time at the end of the
last abutted data message before sending a
trailing ACK. The I-bit drop of RTS causes
some delay by the modem in returning
CLEAR TO SEND. The delay could be as
long as a regular RTS - CTS delay of the
modem (typically about 150 ms). To prevent
extra delay for every data message, multiple
buffers can be assigned to the DMCII as opposed to single buffering. Some modems may
react strangely to the I-bit RTS drop and lost
bit synchronization. It is recommended that
users ask the manufacturer about a proposed
modem concerning this occurrence. Modems
adversely affected by the I-bit RTS drop time
should be avoided.

3.5.7 Maintenance Mode
DDCMP maintenance messages are used for down-line program loading, maintenance and control of
satellite computer systems. These functions are controlled and performed by higher level software.
The DMCII provides data link control for Maintenance Operation Protocol (MOP) which requires
error-free transmission and reception on a data link. In DDCMP maintenance mode, the DMCII
provides modem control, message framing, bit error detection (CRC Checking), and CRC generation.
Messages in DDCMP message format are subject to error checking, but are unsequenced, unacknowledged, and not retransmitted automatically by the DMCII. Maintenance messages can only be sent
and received while the microprocessor is in the DDCMP maintenance state. The PDP-II program may
cause the microprocessor to enter this state by a CNTL I transfer with bit 8 (DDCMP MAINT), and
bit 10 (DDCMP HD) of SEL 6 set.
If a maintenance message is received while in the running (DDCMP) state, the microprocessor performs a CNTL 0 transfer with DDCMP MAINT RECD set in SEL 6. The PDP-II program must
then initialize the device to the maintenance state to transfer messages in maintenance format. The
message causing the error notification is lost.

NOTE
Once the DMCII is given a BASE I command, it
sends a start message every second. When the PDPII program sets the DMCII in DDCMP maintenance mode, the start is aborted. A "hang" condition
could be created on a two-wire half-duplex link between the DMCII and a non-DMCII device as
shown in the following example.

3-33

Example
The restart steps of a satellite computer system sequence are:
1.

The Non-DMCII system sends a MOP message.

The DMC system receives MAINT RECV'D. (For a maintenance message other than ENTER MOP, see Section 3.5.8 for a description of the ENTER MOP message.)

The DMC system initializes the DMC and does BASE I.

DMC sends STRT.

The DMC system does CNTL I to set MAINT mode.

DMC aborts STRT.

The Non-DMCII system sees aborted STRT or STRT with a noise HIT.

The DMC system gives maintenance message to the DMC.

DMC transmits the maintenance message and the non-DMCII system resends MOP message simultaneously.

A hang-up occurs because both ends transmit simultaneously on a two-wire HDX link. The problem
can be corrected in a number of ways.
1.

Non-DMCII system does not retransmit MOP request on bad response but instead waits
for a time-out period.
.

DMC system should do a receive buffer BA/CCI command immediately following CNTL I
at step 5 above and wait for the non-DMCII system to time-out and retransmit.

DMC and Non-DMCII systems should transmit at different time-out intervals.

Once in DDCMP maintenance mode, maintenance messages can be sent and received like data messages. On transmission, the data portion of the message is taken from the assigned buffer with the
DMCII generating the header and CRCs. On reception, only the data portion is placed in the available assigned buffer. Messages not in DDCMP maintenance format, having incorrect CRCs or no
receive buffer are simply discarded. No errors are reported when in this mode. In the maintenance
mode, the DMCII transmitter does not wait for the SELECT flag. Line turnaround must be controlled by higher level software, that is, does not transmit until receipt of receive BA/CCO.
The data portion of the maintenance message may contain any data that is desired, but ordinarily it
conforms to the DIGITAL MOP formats. When operating in conformance with MOP, the DMCII
must be operated in a single buffered manner, causing a line turn-around after each message is transmitted. When a host computer wishes to restart a satellite computer system, it must send the appropriate MOP messages as described in Section 3.5.8.
In order to exit maintenance mode, the PDP-II program must initialize the DMCII and supply a base
address with the RESUME bit clear.

3-34

3.5.8 Remote Load Detect
Whenever the microprocessor is running, it is constantly scanning the serial line for a DDCMP maintenance message containing an ENTER MOP MODE data field as illustrated in Figure 3-14. What
happens when this particular message is received depends on the setting of two switch packs on the
DMCII line unit (M820I or M8202).

CODE

PASSWORD

WHERE:
CODE(1 BYTE) = 6
PASSWORD (X BYTES) =

A PASSWORD THAT MUST MATCH BEFORE THE RECEIVING STATION
ENTERS THE MOP MODE. IF THE PASSWORD IS SENT OVER A DDCMP
LINK IN THE MAINTENANCE MODE, THE LINK ENTERS THE DDCMP
MAINTENANCE MODE (DUE TO THE MAINTENANCE MODE ENVELOPE),
BUTTHE MODE ONLY ENTERS THE MOP MODE (E.G., RESPOND TO LOAD
REQUESTS) IF THE PASSWORD MATCHES.
THE PASSWORD NUMBER CAN BE VARIABLE. THE DMC11 CHECKS ANY
PASSWORD NUMBER SPECIFIED BY THE CHARACTER COUNT MINUS
ONE IN THE HEADER. THE MAINTENANCE OPERATION MODE (MOP)
SPECIFICATION (VERSION 2.0) RECOMMENDS THE PASSWORD
NUMBER OF FOUR (4).
MK-0865

Figure 3-14

Enter MOP Mode Format

•

If the DMCll is not currently in the DDCMP running state (given BASE I and CNTL I
commands), this message is ignored.

•

If the DMCll is in the DDCMP running state, a CNTL a command is generated with an
error code of 108, DDCMP MAINT received (a fatal error).

•

If the DMCII is currently in the DDCMP maintenance mode, this message is received and
given to the PDP-II program if a receiver buffer is assigned. If no receive buffer is available,
the message is ignored.

If the line unit switch pack No.2 is set to a value other than all ones (3778), then reception of the enter
MOP message causes the following actions to happen:

•

The DMCll verifies that the first byte is code 6.

•

Each password following code 6 is compared against the content of switch pack No.2 for a
match. If the password and switch pack No. 2 do not match, then the following actions
occur.
If the DMCll is not currently in the DDCMP runningstate(given BASE I and CNTL
I commands), this message is ignored.

3-35

If the DMCll is in the DDCMP running state (start-up sequence completed after
BASE I and CNTL I commands), a CNTL 0 command is generated with an error code
of 108, DDCMP MAINT received (a fatal error).
If the DMCll is currently in DDCMP maintenance mode, this message is ignored.
•

If each password matches the content of switch pack No.2, then 173000 plus the content of
switch pack No.3 (E88 on the M8201, E91 on the M8202) is loaded into location 248 (PDP11 physical memory location) via a DMA. Location 268 is loaded with 00000.

•

The DMCll then generates an AC LO on the system to simulate a system power failure to
transfer control to a primary boot residing in a boot Read Only Memory (ROM). This boot
ROM is an option and is sold separately.
I.

NOTE
Switch pack No. 3 on the line unit contains
three octal digits (XXX) which are used to
form an entry point to a boot ROM. The address formed is 173XXX.

On PDp.. I 1/04, 11/34, and 11/40 CPU
types, RLD is not recommended for unattended satellite operation.

On PDP-I 1/04, 11/34, and 11/40 CPU
types, DMA activities (NPRs) are not allowed
when the CPU is in the halted state. The REMOTE LOAD DETECT (RLD) might not
work if the system halts when the DMCII is
in the process of doing an NPR for transmit,
receive, or base update. In this case, the NPR
is not completed, the DMCII hangs up, and
never sees the ENTER MOP message on the
serial line. To overcome this situation, an operator must reset the system by pressing the
RESET or INIT switch on the CPU console.
On CPUs with a KYII-LB console, operator
action must be in the following sequence:
I. CNTL INIT
2. CNTL HALT
3. CNTL HALT
This action clears the DMCII and KYII-LB,
allowing DMCII reception of enter MOP
and subsequent A C LO simulates the power
fail of the CPU.

Figure 3-15 is an example of the setup procedures and required handshakes to complete an RLD
operation. It is assumed that the DMCll line unit at the remote station has the password for RLD set
up in switch pack No.2 and a correct offset from 173000 to enable entry of the DMCll boot code in
the ROM BOOT.

3-36

SOFTWARE AT HOST

DMC11 #1

SERIAL LINE

DMC11 #2

DMC11 BOOT CODE IN BOOT ROM
(M9301-YJ/M9312)

1 -INITIALIZE DMC11
2- BASE IN TO DMC11
3- CONTROL IN TO DMC11 WITH SEL 6 = 2400
4 - BA/CCI FOR RECEIVE WITH CHARACTER
COUNT OF 256
5- BA/CCI FOR TRANSMIT WITH CHARACTER
COUNT OF 5. TRANSMIT BUFFER IN PDP-11
0 0 0
MEMORY SHOULD LOOK LIKE 6
(PASSWORD = 0)

1- TRANSMIT ENTER MOP
MESSAGE
2- DO A BA/CCO ON TRANSMIT
DONE

1- CHECK THE FIRST BYTE = 6
2- COMPARE PASSWORD (PSW)
RECEIVED WITH PSW SELECTED IN LINE UNIT SWITCH 2
3- IF ALL PSWs MATCH, DMA
THE FOLLOWING TO PDP-11
MEMORY 24/173XXX, 26/0
XXX = LINE UNIT. SW3
4- PULL AC LO ON UNIBUS

NOTE (1)
IN DDCMP MAINTENANCE, THERE IS NO RETRANSMISSION;
BA/CCO FOR A TRANSMIT OPERATION DOES NOT ASSURE
SUCCESSFUL RECEPTION AT THE REMOTE END, THE SOFTWARE
MUST KEEP A REPLY TIMER OF 3 SECONDS TO RETRANSMIT THE
MESSAGE WHEN NO REPLY IS RECEIVED WITHIN THAT TIME

NOTE (2)
XXX MUST BE THE OFFSET
FROM 173000 OF THE
DMC11 BOOT CODE IN
M9301-YJ/M9312

OLE
3 - DO A BA/CCO RECEIVE TO PDP-11
6 - CHECK VALIDITY OF REQUEST SECONDARY
BOOT MESSAGE RECEIVED
7 - DO A BA/CCI RECEIVE WITH CHARACTER
COUNT OF 256.
8 - DO A BA/CCI TRANSMIT WITH CHARACTER
COUNT OF (X + 12). THE TRANSMIT
BUFFER CONTAINS MOP 0 MEMORY LOAD
WITH TRANSFER ADDRESS AS FOLLOWS:
CODE (1 BYTE) = 0
LOAD NUMBER (1 BYTE) = 0
LOAD ADDRESS (4 BYTES) = 0

MOPS

D_LE_ _•
4 - TRANSIT MOP 0 (MEMORY LOAD -+-_ _
MOPO
WITH TRANSFER ADDRESS)
5 - DO A BA/CCO TRANSMIT

1 - TRANSMIT REQUEST SECONDARY
BOOT MESSAGE (MOP 8)
2 - DO A BA/CCO TRANSMIT
3 _ DO A BA/CCO RECEIVE TO

PROGRAM CONTROL IS PASSED TO DMC1l
BOOT CODE WHICH DOES THE FOLLOWING:
1 - INITIALIZE DMC11
2- BASE IN TO DMC11
3 - CONTROL IN TO DMC11 WITH SEL6 = 2400
4 - BA/CCI FOR RECEIVE WITH A CHARACTER
COUNT OF 4092
5 - BA/CCI FOR TRANSMIT WITH CHARACTER
COUNT OF 4. TRANSMIT BUFFER IN PDP-l1
MEMORY SOULD BE 10, 14, 1, 0
(MOP 8: REQUEST SECONDARY BOOT)
6- SEE NOTE 1

PDP-11
7- VERIFY MOP CODE = 0 AT LOCATION 0
THEN DO A SYSTEM RESET
8- JUMP TO LOCATION 6 TO PASS
PROGRAM CONTROL TO NEWLY
LOADED PROGRAM

o
o
o

IMAGE DATE LOADED = X BYTES
6
TRANSFER ADDRESS (4 BYTES)

o
o
o

9- SEE NOTE 1
MK-0869

Figure 3-15

Example Set Up Procedure for RL

3-37

3.5.9 Performance Degradation on the DMCII-AL
The following are some of the conditions which could create performance degradation.
•

When the receiver of DMCII-AL is actively receiving data, there is no port servicing and
therefore the transmit/receive buffer assignments (BA/CCI), transmit/receive buffer returns (BA/CCO), and error reporting via CNTL 0 are delayed.
NOTE
If the DMCIl-AL is receiving a data message and
part of the data is lost because the transmission line
is broken or the other DMCII-AL failed to finish
transmission of the entire message, the receiving
DMCII-AL will not service the port until all the
missing data are received.

•

When, on rare occasion, data traffic is very low on the full-duplex 1M bps DMCII-AL,
acknowledgment of the transmitted data message could take a very long time (up to one
second). The very low condition is defined as single buffering DMCII-AL and the data is
flowing in only one direction where the completion of one data transmission will initiate the
next. This condition can be avoided by multi-buffering the DMCII.

•

When running a 1M bps, full-duplex DMCII on a system with other high-speed DMA
devices, there is a high probability of bus latency occurrence. This may be a problem for
systems which cannot tolerate degradation because of latency errors. In some cases, qMCll
throughput may be reduced to zero, that is, heavy UNIBUS activity may prevent the
DMCII from completing any messages. Latency errors are detected by the DMCII as BCC
errors causing the DMC 11 to initiate automatic error recovery (described below in detail).

If recovery fails because of prolonged latency conditions, the DMCII spends all of its time
attempting to recover. The DMCII must service the character and complete the NPR in 8~s.
If this requirement is not satisfied, Data Late occurs; however, it is more likely to occur on
an 11/70 system when the message size is large.
An even worse case condition may occur for a large size message where the DMCII is single
buffered.
1.

DMCII No.1 sends a large message (for example, 1K byte) to the DMCII No.2.

DMCll No.2 receives part of the message; because of the occurrence of DATA
LATE, a large portion of the message is lost.

DMCII No.2 continues to wait for the data that was lost to satisfy its character count
before ·resetting the receiver.

Because DMCII No.1 is single-buffered (completion of one transmission initiates the
next transmission), DMCII No.1 sends ACK every second and REP every 3 seconds
until the transmitted message is acknowledged or a retransmission is requested by
DMCll No.2.

The ACKs and REPs at DMCll No.2 are counted as part of the lost data until the
missing number of characters is satisfied. Only then will the DMCII No.2 detect a
BCC error and reset the receiver.

3-38

•

At DMCll No.1, for every eight REPs sent out (about 24 seconds), a time-out is
reported via CNTL 0; repeated every 24 seconds.

After DMCll No.2 detects the BCC error and resets the receiver, DMCII No.2
requests a retransmission.

The time required for eventual completion of the message transmission depends on
system activities.

Occurrence of serious system degradation due to latency can be reduced or totally avoided
by careful system hardware and software configurations. Consider the following actions:
1.

Reduce DMC message length. On an 11/70 system, a character count of 256 bytes is
recommended. Optimum count may require empirical derivation using actual system
loading.

Multi-buffer the DMCll. Assign more than one message buffer to both transmitter
and receiver rather than only one buffer assignment at a time.

Reduce DMCll serial line speed; 56K bps may work as well as (or better than) aIM
bps line speed. This action may be true when:
a.

Software overhead prevents keeping the serial line busy.

Excessive latency at 1M bps degrades system performance to a greater degree than
running at 56K bps speeds.

Multiplex UNIBUS DMA activity in software. Synchronize device operation to prevent contention for UNIBUS/MEMORY time.

Off-load main CPU. Modularize system functions into subsystems, such as front end
processing, reducing UNIBUS contention problems.

For a DMCII-AL in half-duplex mode under a No-ReceiveBuffer-Available condition, the
transmitting DMCll generates a time-out via a CNTL 0 after eight retransmissions in less
than a couple of seconds instead of 24 seconds. At about the same time, the receiving
DMCl1 generates a NO BUFFER AVAILABLE via CNTL OUT. The sequence of events
is shown in Figure 3-16.
Because neither time-out nor NO BUFFER AVAILABLE on a DMC11 is fatal, the software can recover from this situation if handled properly. At the receiving station, the software can either assign multiple receive buffers, or on NO BUFFER AVAILABLE
notification from DMC11, assign some more receive buffers. At the transmitting system, the
software must wait long enough for the remote system to assign additional receive buffers
either by counting eight or more time-outs from the DMCll or via other means of waiting.

3-39

CPU #1
ASSIGNS
A TRANSMIT BUFFER

DMC #1

•

DMC #2

TRANSMIT DATA

CPU #2

•
NO RCV BUFFER
SEND NAK
III

SELECT TIME OUT
SEND REP

SEND NAK

•
(REP RECEIVED)
III

RETRANSMIT
DATA

•

REPEATED THE SEQUENCE
6 TIMES

RETRANSMIT
DATA

NO RCV BUFFER,
SEND NAK
III

NO BU F/CONT. O.
SELECT TIME OUT,
SEND REP.
~

SEND NAK
(REP RECEIVED)

TIME OUT/CONT. 0
III

RETRANSMIT
DATA
~

THIS COULD GO ON FOREVER

MK-0870

Figure 3-16

DMCll Problem in High-Speed Code

3-40

•

In half-duplex mode, if the remote DMCII is down or the link is broken, the DMCll may

not report these conditions to the software, via time-outjCNTL 0 with an error code of 2.
Condition A - If at the time of the link or remote DMCll failure, the DMCll has some
outstanding transmit buffers (waiting for acknowledgment), then the conditions are reported as time-out.
Condition B - If at the time of the line or remote DMC 11 failure, the DMC 11 does not have
any outstanding transmit buffers (waiting for acknowledgments), then this condition is not
reported. Even if more transmit buffers are assigned later, they are not transmitted, but
entered into the transmit queue and therefore no time-out is ever reported.
Condition B is not recoverable. In half-duplex mode time-outjCNTL 0 does not work
properly.

3-41

CHAPTER 4
DETAILED DESCRIPTION

4.1

SCOPE

This chapter provides a detailed description of the DMCII logic and a general description of the
DMCII microinstruction word formats.

4.2
4.2.1

MICROPROCESSOR DESCRIPTION
Introduction

The following discussion includes a detailed description of each register and associated logic in the
DMCII microprocessor. Figures 4-1 and 4-2 illustrate a general block diagram showing registers and
all internal data paths. Throughout the chapter, reference these diagrams in all discussion relevant to
data flow.
At times it becomes important to know the contents of registers relative to other registers as well as
machine timing. Figure 4-3 shows this relationship with respect to the master clock.

4.2.2

DMClljCPU Structures

The DMCII microprocessor is a parallel 16-bit instruction, 8-bit data path microcomputer. Its architecture and instruction set are optimized for the character processing environment specific to network
communications and other I/O-oriented systems. The DMCII instruction cycle has a period ranging
from 300 to 330 ns, and microinstructions are executed from a 1K X 16-bit control store referred to as
the control ROM (CROM). Microinstructions executed from the CROM can access all DMCII internal registers as well as a 256 X 8-bit data RAM.
Within the instruction cycle period, the DMCII can (1) execute internal register-to-register transfers,
(2) initiate bus requests (interrupt the main CPU), (3) initiate NPR transactions, and (4) perform
transfers between an internal register and data memory. In addition, the DMCII can perform a wide
range of arithmetic and logical functions on internally transferred data. (The main CPU is defined as
the resident PDP-II processor and its associated memory.)
All internal registers and data paths are 8 bits wide. In addition, the Control and Status Registers
(CSRs) are both word and byte addressable from the UNIBUS, but byte addressable only from the
DMCII.
The microprogram can read from or write into all internal registers and memories, except the microinstruction memory (CROM), the memory address register (MAR), and the program counter (PC).
The CROM can be addressed for microinstruction execution only through the PC, and the MAR can
only be written into.
The DMCII microprocessor executes two major classes of microinstructions: Branch and Move.
Branch class microinstructions implement conditional and unconditional program jumps as well as
subroutine entry and return. Move class instructions provide for interregister and intermemory data
transfers and for logical and arithmetic operations on the transferred data.

4-1

Figure 4-1 is an overall block diagram of the DMCll. It shows the structure of the processor and the
data paths connecting that structure. This section summarizes the structural components accessed
through internal buses, by direct microinstruction execution and over the UNIBUS, as well as the
Arithmetic Logic Unit (ALU), which is accessible to all internal registers.
4.2.2.1 INBUS/OUTBUS and INBUS* /OUTBUS* Register Definition - INBUS/OUTBUS and
INBUS* /OUTBUS* refer to two register groups or categories within, and accessed by, the microprocessor. This terminology is used in microinstruction formatting. It defines the group of registers to
be accessed by the microprocessor aqd whether the particular register is used as a source or destination
for data.
•

The "*,, indicates one register group; the absence of the "*,, indicates the other register
group.

•

The "IN" portion of the term identifies the specific register as the data source.

•

The "OUT" portion of the term identifies the specific register as the destination for data.

•

The "BUS" portion of the term does not refer to a physical BUS.

•

The following terms are synonymous:
OUTBUS and OUT
INBUS* and IBUS*
OUTBUS* and OUT*
INBUS and IBUS

Registers in the "*,, group (lBUS* /OUT*) are located in the multiport RAM:
CSR Bytes 0-7
NPR Control
J.lp Miscellaneous

(Registers 0 to 7 are read/write)
(Register 10 is read/write)
(Register 11 is read/write)

Registers in the INBUS/OUTBUS group located in the microprocessor:
IN DATA LB

IN DATA HB

OUT DATA LB

OUT DATA HB

IN BA <7:0>

IN BA <15:8>

OUT BA <7:0>

OUT BA <15:8>

4-2

DMA data from
memory to the
microprocessor
DMA data from the
microprocessor to
memory
DMA address for
data from memory
to the microprocessor
DMA address for
data from the microprocessor to memory

UNIBUS

,~ - - - - - - - - MicROPROGRAM REAOiwRITE BUS- - - - - - - - - -,

BIT 17 BIT 16

'..r- - - - - - - - - - - - - - ~:: - - - - - - - - - - - - - - - - ,
~

r-I

NPR ADDRESS
AND DATA
REGISTERS 8 x 8

I
I

r:.

TO CONTROL
ROMS

I
MULTIPORT
RAM

CONTROL AND
STATUS
REGISTERS 8 x 8

(/)

OUTBUS*

::>

co
~

INBUS

I
I
I

I
LJ',

L __ ",

--OUTBUS*

OUTBUS*

NPR
CONTROL
REGISTER
1 x 8

BIT 16

f.1 PMISC
CONTROL
REGISTER
1 x 8

BIT 16

INBUS*
BIT 17

INBUS*
BIT 17
SINGLE STEP

BRANCH
REGISTER
(BRG)
1 x 8

DATA
MEMORY

EXTERNAL
DESTINATION BUS 8 BITS WIDE

OUTBUS
CONNECTOR
MK0816

Figure 4-1 DMCII Register and Data Path Structure

4-3

r-____________________________________________________________________________-=C~RO~M~D~A~T~A~0~-1~5~~~ UNIBUS
~BAO-15

DATA

AN NPR

M/P RAM
0-15
--

__ UNIBUS DATA

MUX
(011)

LU I BUS
0-7

r---

0-15 OUT

M/P
RAM

UNIBUS
DATA
I+------------L-- 0-1 5 IN

DATA

ALU 0-7 FOR M/P DATA

MULTI-;;R~RT ~ ~ 0-7

M/P RAM DATA
8-15
B PORT
M/P RAM

or 8-15 NPR IN

RAM
16 BITS X

UNIBUS
CSR WRITE

8 LOCATI~~~O) f4- T240

UP WRITE
T240 - T300

DATA 0·7

OM UX OUTPUT SEL 0-3
CROM 4.7
13,14,15

SOURCE
ROM

MEMORY
ADDRESS
REGISTER

MEMORY
8 BITS X

......

(D1,D2)i-+-_-"--_
256 LOCATIONS"
(D3) ['J)o~.---------------------------,

~ MOVE INSTRUCTION (2 BITS)

~IBUS

!---+ IBUS'

....

o MUX

(D6)
BRANCH
REGISTER

UNIBUS DATA
0-15

~_ _~(_D_l,~D_2~)~-~----------------------4-4---~~--T300

----. BRG FUNCTION (2 BITS)
DESTINATION ----. OUT' L, WRITE OUT
CROM 8,9 ROM
----. MAR CONTROL (2 BITS)
10,11,12
~ SCRATCH PAD

.---

NPR
CONTROL REG.
(D13)4-

- . MEMORY
(Dl)

I-- T270
MICRO-PROCESS. j4-

CROM 4,5

FUNCTION
ROM

MAINT. INSTRUCTION
6,7,14
REG. 16 BITS X
..---

1 LOCATION

(D4,D5)

1---+ ALU FUNCTION (5 BITS)
1---+ ENABLE CARRY
f----+- FORCE CARRY
f----+- CLOCK CARRY

(07)

I+- MISC. REG.
(013)

DMUX
0-7

~ROM 0-7
(06)

8
MK0817

Figure 4-2

Microprocessor Block Diagram (Sheet 1 of 2)

CRaM 0-3~-SP------'

SP ADDRESS 0

Z BIT

ADDRESS
MUX

SCRATCH PAD 14-'------if---+- T240
8 BITS X
1300

(08)

CONTROL ROM
16 BITS X 1 K LOCATIONS

.,J::o.
I

ALU

(04.05)

MICRO PC
BITS 0-9

CRaM 11.12

(01.02)
C BIT

ALU 0-7
C

(07)

BALUO-7(1)H
CRaM 8.9.10

BRANCH MUX

BALU
BALUO-7 (1) L

~__~(D_8~)~--------------~----------------------~~J~1

MISCCONTROL(8BITS) ~
CROMO-7
C=1

Z=1

BRB 1

LINE UNIT
(M8201 or M8202)

LINE UNIT
I BUS

=1
MK 0817
ISHEET 2 OF 21

BRG 0 = 1

Figure 4-2 Microprocessor Block Diagram (Sheet 2 of 2)

T150

T240

T150

T240

BALU

LAST INST RESULT OPERAND

(PC+1) OR LAST INST RESULT OPER

CROM

CURRENT INSTRUCTION

MAR

LAST INST RESULT OPERAND

8RG

LAST INST RESULT OPERAND

SCRATCH PAD

CURRENT INST "A" OPERAND

MULTIPORT RAM

CURRENT INST "8" OPERAND

ALU

CURRENT INST RESULT OPERAND

MK-0790

Figure 4-3

Microprocessor Register Timing

4-6

Registers in the INBUS/OUTBUS group located in the line unit*:
IN DATA SILO

OUTCONT

OUT DATA SILO

INCONT

MODEMCONT

SYNC REG

LNDSWREG

BM873 REG

MAINTREG

4.2.2.2 Multiport RAM - The multiport RAM is a 16-byte random-access memory divided into two
8-byte sections that are addressed as INBUS* /OUTBUS* registers and INBUS/OUTBUS registers.
One section contains the CSRs for the DMCll microprocessor, and the other serves as an address and
data port for NPR transfers. As shown in Figure 4-1, the multiport RAM interfaces directly with the
UNIBUS for bidirectional transfer of data words or bytes and the 16 low-order bits of a UNIBUS
address. This memory is byte addressable from the microprocessor; the two 8-byte sections can be
accessed by the microprogram for both read and write operations. The UNIBUS CSRs are accessed as
INBUS* /OUTBUS* registers and NPR address/data interfaces through the INBUS/OUTBUS registers. From the UNIBUS, the CSRs are both word and byte addressable and can be read from and
written into by the main CPU or anotherNPR device. (A detailed description of the multiport RAM is
provided in Section 4.2.10.)
4.2.2.3 NPR Control Register - The NPR control register is an 8-bit formatted register that enables
the microprogram to control input and output NPR transactions. This register also contains the two
high-order bits of the UNIBUS address for an input NPR transaction. Note that an input NPR
transaction involves the transfer of data from main CPU memory to the microprocessor. Conversely,
an output NPR transaction involves transfer of data from the multiport RAM to main CPU memory.
The NPR control register is a read/write register and is addressed as a register in the
INBUS* /OUTBUS* category. (NPR control bit descriptions are provided in Section 4.2.11.1.)
4.2.2.4 Microprocessor Miscellaneous Control Register - The microprocessor miscellaneous control
(JIPMISC) register is an 8-bit register that contains various control and function bits necessary for
operation of the DMCll. For example, this register contains a one-second interval timer bit and a bit
that flags the addressing of a nonexistent main CPU memory location by the microprocessor (NXM
error).

* Detailed descriptions of these registers are provided in the DMCll IPL Synchronous Line Unit Maintenance
Manual, Part No. EK-DMCLU-MM-002.

4-7

Specific bits are also available to the microprogram to control initiation of bus requests over the
UNIBUS and to specify one of two vectors for appropriate interrupt processing. In addition, this
register contains the two high-order UNIBUS address bits for an output NPR transaction. The
tLPMISC CONT register is R/W and is addressed as a register in the INBUS* /OUTBUS* category.
(See Section 4.2.11.2 for bit descriptions.)

4.2.2.5

External Connector .- The DMCII microprocessor is equipped with an external connector
that supports eight parallel data input lines and eight parallel data output lines. These lines provide the
DMCII with direct access to a high-speed peripheral device such as a DMCII line unit.
Eight internal 8-bit register addresses are assigned to the supported line unit accessible by the microprocessor only. As shown in Figure4-18, these registers (physically located in the external line unit) are
read as IBUS registers and written as OUTBUS registers through the external connector.

4.2.3 Microinstruction Word Formats
T}Vo different microinstructions can be executed by the DMCII microprocessor. They are the Move
and Branch microinstructions. These microinstructions reside as permanent microcodes in a read-only
memory defined as the control ROM (CROM). The CROM has enough storage capacity to store a
microprogram of 1024 words. Each microinstruction word is sixteen bits long.
4.2.3.1

Branch Instruction - Figure 4-4 illustrates the word format of the Branch microinstruction.
Bits 13-15 are the operation code defining the microinstruction as a branch. The operation code
defines further the source operand from which the partial branch address is developed. The branch
address is the address of the next microinstruction, should the branch condition be satisfied.

The condition under which the branch is to occur is defined by bits 8-10. The resultant branch address
is partially defined by bits 0-7 of the microinstruction. These eight bits are combined with microinstruction bits II and 12 to form the complete IO-bit branch address capable of addressing any of the
1024 locations within the CROM.
Three Branch microinstructions exist, each defining a different source operand from which to develop
the eight low bits of the branch address.

4.2.3.2

48 - Branch Immediate (I)

MK-0839

The microprogram branches if the condition specified by microinstruction bits 8-10 is met. The 10-bit
branch address is the result of combining microinstruction bits 0-7 with the Branch Address Bits
(BABs) - bits II and 12.

4.2.3.3

68 - Branch Memory (MEM)

o
MK-0840

4-8

This microinstruction combines two operands in the ALU under control of the ALU FUNCTION bits
(bits 4-7). When combined with microinstruction bits 1 and 12, the result operand produces a 10-bit
branch address. One operand is from a MEM storage location and the other is from the scratch pad
memory (SP). Microinstruction bits 0-3 address the operand in the SP while the MEM operand is
from the location addressed by the current contents of the MAR. The desired address would have been
loaded into the MAR by a previous instruction other than the Branch under execution. The condition
for the branch is defined by the CONDITION CODE, bits 8-10. Figure 4-4 defines the ALU FUNCTION CODES that are possible with this microinstruction.
4.2.3.4
15

78 - Branch Register (BRG)
14

321

MK-0820

With this microinstruction, the contents of the BRG and an SP memory location are operated on to
generate the partial Branch address. Bits 0-3 specify the SP location and bits 4-7 define the ALU
FUNCTION to perform on the two operands.
4.2.3.5 Move Instruction - Like the Branch, Move is a highly versatile microinstruction. When combined with the Branch in a microprogram, the combination produces a DMC-ll microprocessor of
high versatility and power. In all, five variations of the Move microinstruction exist, each specifying a
different source for the operand. The source is defined by the operation code. Figure 4-5 illustrates the
Move microinstruction word format.
The operation code is defined by bits 13-15. Bits 11 and 12 specify the function to perform on the
MAR. According to bits 11 and 12, the MAR can remain unmodified, incremented, or loaded from
the Buffered ALU (BALU). The destination of the result operand is defined by microinstruction bits
8-10. The low byte of the microinstruction is operation code dependent further defining input addresses, ALU function, and output addresses.
The ALU Function field (see Figure 4-5) microinstruction bits 4-7, define the operation to be performed on the two operands. These four bits and operation code bit 14 serve as the address input to the
Function ROM (FROM). The FROM microword controls the ALU inputs. Common to all five Move
microinstructions are the MAR Function field and the Destruction field. The MAR can be unmodified
as per the previous paragraph. The MAR increment and load function sets up the M EM operand for
the next microinstruction where necessary. The Destination field, as the name implies, specifies the
destination of the result operand. Three of the eight possible destination references are microprocessor
discrete registers, that is, BRG, MEM, and BRG shifted and consequently need no further address
definition. The specific location in MEM was predefined with a previous microinstruction. Four destination references require still further address definition. These include OUTBUS, registers OUTBUS*, registers SP, and SP jBRG. The four low order bits (bits 0-3) of the microinstruction provide a
specific destination address within OUTBUS, registers OUTBUS* or the SP memory when any of
these are referenced as a destination.
When destinations OUTBUS register and OUTBUS* register are microprogrammed, SP address 0 is
presented to ALU input A. Thus, if Move instruction MEM or BRG is used, all 16 ALU functions are
available to operate on the two source operands (SPO and MEM or BRG);

4-9

BRANCH
15

: I

>1 : : I

OP CODE
DEFINED

'--y----A

SOURCE
OPERAND

1 0 0
1 1 0
1 1 1

: : : : : : I
0

BRANCH
ADDRESS
BITS

)

BRANCH ADDRESS
BRANCH
CONDITION

SCRATCH PAD
ADDRESS

ALU
FUNCTION

9,8

o 0 0 - RESERVED
o 0 1 - UNCONDITIONAL BRANCH
o 1 0 - BRANCH IF C BIT IS SET
o 1 1 - BRANCH IF Z BIT IS SET
1 00- BRANCH IF BRG BIT 0 IS SET
1 0 1 - BRANCH IF BRG BIT 1 IS SET
1 1 0 - BRANCH IF BRG BIT 4 IS SET
1 1 1 - BRANCH IF BRG BIT 7 IS SET

THESE TWO BITS COMBINED WITH THE
EIGHT BIT ALU OUTPUT FORM THE
COMPLETE TEN BIT ADDRESS.

1 00- IMMEDIATE: BITS 0-7 OF THE MICROWORD
COMBINED WITH BITS 11 AND 12 FORM
THE BRANCH ADDRESS.
10 -

MEM: THE MEM CONTAINS THE SOURCE
OPERAND TO BE COMBINED WITH THE SP
MEMORY OPERAND AS DEFINED BY THE
ALU FUNCTION BITS.

1 1 1 -

BRG: THE BRG CONTAINS THE SOURCE
OPERAND TO BE COMBINED WITH THE SP
MEMORY OPERAND AS DEFINED BY THE
ALU FUNCTION BITS.

CODE

ALU FUNCTION
2's COM SUB
1's COMP SUB
ADD
ADD W/C
SUB W/C
INC A
A PLUS C
2A
2AW/C
DEC A
SEL A
SEL B
A OR 8
A AND B
A OR B
A X OR B

(A-B)
(A-B-1)
(AB)
(AB,C)
(A-B-C)
(A1 )
(AC)
(A.A)
(A,AC)
(A-1 )
(A)
(B)
(A+B)
(AB)
(A+B)
(AEElB)

1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101

NOTES:
C = CARRY
W/C = WITH CARRY
C AND Z ARE SET/CLEARED WITH MOVE INSTRUCTIONS.
A = ARITHMETIC OR SCRATCH PAD (SP) SIDE OF ALU.
B = LOGIC OR DMUX SIDE OF ALU.
MK-0829

Figure 4-4

Branch Microinstruction Word Format

4-10

MOVE

: : : >1

: 13112 : 11 110 :

000

o 0 1
1 0 1
010

IMMEDIATE OPERAND
MAR
FUNCTION
FIELD

DESTINATION
FIELD

INPUT ADRS

OUTPUT ADRS

INPUT ADRS

OUTPUT ADRS

ALU FUNCT

OUTPUT ADRS OR

I---A-L-U-FU-N-C-T-~ SCRATCH PAD AD RS

011

0 0 001 10 o1 110 0 10 1 1 1 0 1 1 1 -

NO OPERATION
BRG
OUTBUS* (SPO+A)
BRG RIGHT SHIFTED ONE BIT
OUTBUS (SPO +A)
MEM
SCRATCH PAD
SCRATCH PAD AND BRG

00- RESERVED NO EFFECT
01- RESERVED NO EFFECT
1 0- LOAD MAR
1 1- INCREMENT MAR

CODE

ALU FUNCTION

000 -

IMMEDIATE OPERAND IN BITS 0-7 OF
MICROINSTRUCTION.

00 1 -

IBUS IS OPERAND SOURCE DEFINED BY
MICROINSTRUCTION BITS 4-7 AND
DESTINATION DEFINED BY BITS 8-10.

10 1 -

IBUS* IS OPERAND SOURCE DEFINED BY
MICROINSTRUCTION BITS 4-7 AND DESTINATION
DEFINED BY BITS 8-10.

o 1 0 - MEM IS OPERAND SOURCE OPERATED ON AS
DEFINED BY ALU FUNCTION (BITS 4-7).

2's COM SUB
1 's COMP SUB
ADD
ADD WIC
SUB WIC
INC A
A PLUS C
2A
2AW/C
DEC A
SEL A
SEL B
A OR B
A AND B
A OR B
A X OR B

o 1 1 - BRG IS OPERAND SOURCE OPERATED ON AS

(A-B)
(A-B-1)
(AB)
(A,B,C)
(A-B-C)
(Al)
(AC)
(AA)
(AAC)
(A-1 )
(A)
(B)
(A+B)
(AB)
(A+B)
(A'l'B)

11 10
11 11
00 00
00 01
00 10
00 11
01 00
01 01
01 10
01 11
1000
1001
10 10
10 11
11 00
11 01

MOV
INST
CLOCK
C
(NOTE 1)

MOV
INST
CLOCK
Z

(NOTE 2)

DEFINED BY ALU FUNCTION (BITS 4-7).
NOTES:
1. IF ADD FUNCTION, C IS SET TO INDICATE CARRY OR OVERFLOW.
IF SUB FUNCTION, C IS CLEARED TO INDICATE BORROW OR SIGN CHANGE.
2. Z IS SET WHEN ALU OUT IS ALL 1 S.
3. C = CARRY
WIC = WITH CARRY
A = ARITHMETIC OR SCRATCH PAD (SP) SIDE OF ALU.
B = LOGIC OR DMUX SIDE OF ALU.

Figure 4-5

Move Microinstruction Word Format
4-11

MK-0830

The BRG right shift destination performs a right shift on bits 7 to o. Bit 0 is passed through the ALU B
side before returning to BRG bit 7 during a Move type BRG instruction. This allows all 16 ALU
functions with the SP to be used for the possible alteration of the data bit which was returned to BRG
bit 7.
Instruction types MOV I, MOV IBUS, MOV IBUS*, and MOV MEM may also be used with a BRG
right shift. However, in these cases, ALU bit 0 is a function of sources I, IBUS register, and IBUS*
register, while MOV MEM, which is similar to MOV BRG, is a function of MEM and SP as selected
by the 16 ALU functions.

4.2.3.6
15

08'- Move Immediate (I)
14

65432

MK-0837

The operand (microinstruction bits 0-7), is moved to the destination as specified by microinstruction
bits 8-10.
With the MOVE IMMEDIATE, the destination reference is normally limited to the BRG, MEM, and
the MAR. The other possible destination references are useable; however, they require special consideration since the same data is used both as an operand and destination address.

4.2.3.7

18'- Move INBUS (IBUS)

MK-0835

The operation code specifies the IBUS register as the source operand. However, since the IBUS register is a block of sixteen 8-bit words, additional address information must be provided by the INPUT
ADDRESS portion of the microinstruction (bits 4-7). In cases where the Destination field specifies
data blocks, that is, OUTBUS, OUTBUS*, or the SP microinstruction bits 0-3 specify the byte position within the block as the destination. In addition, the operand can also be clocked into the MAR
when so indicated by the MAR Function field microinstruction word, bits 11 and 12.

4.2.3.8

58 - Move INBUS* (IBUS*)
15

MK-0838

4-12

This microinstruction is similar to the Move IBUS microinstruction with the exception that the Move
IBUS* addresses the IBUS* register block of words.
28'- Move Memory (MEM)

4.2.3.9
15

MK-0819

The Move MEM microinstruction performs either an arithmetic or logical operation on two designated operands and deposits the result operand into the specified destination address. One of the two
operands is from MEM while the second is from the SP. The specific location within the SP memory is
defined by the microinstruction OUTPUT ADDRESS field (bits 0-3).
The result operand is moved to the destination as specified by the Destination field (microinstruction
bits 8-10).
When the SP or MEM is designated as the destination, then the respective source operand is destroyed
by delivery of the result operand.
4.2.3.10
15

38'- Move Branch Register (BRG)
14

MK-0836

The operation of the Move BRG microinstruction is similar to the Move MEM with one exception.
The two operands of this microinstruction are the contents of the BRG and the SP. If the microinstruction specifies either the SP or the BRG as the destination, then the respective source operand is
destroyed by the delivery of the resultant operand.
4.2.4 CROM, MAR, BR, PC and Branch MUX
The basic microprogram stored in the CRaM is addressed by a 10-bit PC (see Figure 4-6). The PC
operates in two modes. It can be either incremented or parallel loaded from the BALU. The Branch
Multiplexer (Branch MUX) output determines which function occurs. A low condition on the Branch
MUX output causes the PC to load, that is, branch. The PC is always altered on the trailing edge of
T240. Eight bits of the branch address come from the BALU, while the two high order bits come
directly from the microinstruction word (bits 12 and 11).
CRaM bits 8-10 determine which one of eight inputs is selected by the Branch MUX. The truth table
in Figure 4-6 lists the selection codes controlling the MUX. Note that the Branch MUX is disabled
when executing any Move microinstruction. Conversely it would be enabled for all Branch microinstructions.
Using the BRG, the microprocessor has the ability to shift a byte of data one bit position to the right,
each time the appropriate microinstruction is executed. Data is rotated to the right with BALU 0 in the
loop. BALU 0 gates to BRG7 while BRGO passes through the ALU and is subsequently clocked into
BALU O.

4-13

ALU OUT OH-7H ~_ _
T240(1) H _ _ _~

BALU
0-7

(CLOCKJL)
MOV INST H

BALU 0(1) H-7(1) H

BR 7 H
BR 4 H
BR 1 H
BR 0 H

Z(1) H

BRANCH L

BRANCH
MUX

T240(1) L
(CLOCKLS )

0-9

C(1) H

+3V
CROM
11H,12H

10 9 8

BRANCH COND

0 0

RESERVED

0 1

BRANCH ALWAYS

1 0

CARRY BIT SET

1 1

Z BIT SET

BR BIT 0 SET

o 1

BR BIT 1 SET

1 0

BR BIT 4 SET

BR BIT 7 SET

PC 0 H-9H

CROM
8H-10H
CROM
1Kx16BITS

CROM OH-15H
MK-0791

Figure 4-6

Block Diagram of Program Counter Control Logic

Control of the BRG is determined by the two inputs SO and Sl. With these two control signals, the
BRG can load data, shift data, or recirculate data.
See the truth table in Figure 4-7. While SO and S 1 determine what function to perform, the clock
signal, CLOCK MAR, BRG L, determines when to do it. This BRG clock always occurs on the
trailing edge of T240 when executing a MaY microinstruction.
Main memory (MEM) with 256 locations is addressed by the 8-bit MAR. Like the PC, the MAR can
be parallel loaded from the BALU outputs or incremented on the trailing edge of the clock signal
CLOCK MAR, BRG L. Clocking always occurs on the trailing edge of T240 during execution of a
Move microinstruction. Two bits of the Destination ROM (DRaM) microword determine the function to perform on the MAR (MAR LD L and MAR INC EN L).

4-14

R3(1 )

R2(1 )

PARALLEL INPUTS {

R1 (1)

}

OUTPUTS

RO(1 )

74194

SHIFT RIGHT SERIAL IN
NOT USED

10_~9

MODE CONTROL { _ _ _ _

74194 TRUTH TABLE
S1 SO

FUNCTION

PARALLEL LOAD
SHIFT RIGHT

a
a a
1

---

NOT USED
HOLD (INHIBIT CLOCK)

REFER TO
01 & 02 OF
M8200 PR I NT SET

THE BRG IS COMPOSED OF TWO 74194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS.
MK-0793

Figure 4-7

Configuration of the B Register

As previously discussed, the DROM microword controls the MAR and the BRG. It also has four
additional bits to control writing into MEM, SP memory, SP jMAR, and the OUTBUS*. Microinstruction bits 8-12 form the DROM address which in the Move microinstruction represents the
Destination field and MAR Function field. The DROM is shown in Figure 4-8 and the DROM map is
shown in sheet D20 of the print set.
4.2.5 Main Memory (MEM) Eight integrated circuit chips constitute the 256 location main memory. Each chip stores one bit of an
8-bit byte. Stored in the memory are items such as message headers and commonly used protocol
messages.

4-15

5610/6331
DRaM
BRG SO H

08
CRaM 8 H
CRaM 9 H
CRaM 10 H
CRaM 11 H
CRaM 12 H

10
11
12
13
14

02
01

2
3
4
5
6
7
9

BRG S1 H
OUT *L
WRITE OUT H
MARLOENH
MAR INC EN L
WRITE SP H
WRITE MEM H
REFER TO 01 OF
M8200 PRINT
SET

32 WORDS x 8 BITS

SEE PRINT SET SHEET 020 FOR DRaM MAP.
MK-0794

Figure 4-8

Configuration of DROM

Memory addressing is accomplished using the MAR, while write data is gated directly from the BALU
outputs. Write timing is controlled through the function W.RITE MEM L, originating at the DROM.
The memory contents can be sourced with the Move microinstructions and two of the three Branch
microinstructions. Operation code 68 can only read MEM contents.
The MEM output feeds the Data multiplexer (DMUX) input and is selected with a code of 28 for a
Move or 68 for a Branch. The DMUX selects the MEM output during execution of the Move MEM
or Branch MEM microinstruction.
4.2.6 CROM arid the Maintenance REG
The CROM is the heart of the microprocessor system through which complete system control is
exercised. Stored within the CROM is the unique microprogram necessary for execution of the
DDCMP. This stored microprogram utilizes the two powerful microinstructions discussed at the beginning of this chapter. A total of 1024 memory storage locations are available for the microprogram
through the use of eight integrated circuit chips. Each chip stores four bits of the microinstruction in
512 storage locations. Addressing is done with the la-bit PC.
Fields within microinstructions read from the CROM become the addresses for a second-level microword contained within three additional ROMs, DROM, FROM, and SROM (Source ROM).
In addition, certain microinstruction bits directly control gating and timing operations throughout the
mIcroprocessor.

4-16

Each ROM chip has a chip enable input (pin 13) which must be asserted low in order to enable the
chip. Because these chips are tri-state devices, a disabled chip presents a high impedance (high Z)
output allowing the wire ORing of outputs, thus expanding total memory capacity. In the microprocessor, two memory chips (each storing 512 4.-bit words) have their outputs wired together forming
a memory of 1024 locations. The appropriate chip is selected with signal PC9 (pin 13, E34 page 02 of
the Print Set).
A maintenance feature of the microprocessor allows the PDP-II software to simulate the CROM
outputs through the use of the Maintenance Register. The output of the Maintenance Register is wire
ORed with the CROM output. With the CROM disabled and the Maintenance Register enabled, the
contents of the register become the system microinstruction. The register is loaded from the UNI BUS
data receivers when Select 6 (SEL 6) of the CSRs is loaded from the PDP-II and ROM I (Bit 9) in
BSEL 1 is asserted. ROM I also deselects the CROM (high Z outputs).
4.2.7 DMUX and SROM
The OMUX is an 8-bit wide, eight-to-one multiplexer, whose output feeds the B input of the ALU.
Input selection is controlled by three bits originating at the SROM. The OMUX and associated truth
table are shown in Figure 4-9.
The SROM is a 32-location ROM containing an 8-bit microword. The SROM is shown in Figure 4-10
and the SROM map is shown in sheet D20 of the print set. The SROM is addressed directly by the
CRO M (bits 13-15, 4 and 7). Note that three of these bits (15, 14, 13) are the microinstruction operation code.
4.2.8 ALU and Associated Logic
With the ALU, the microprocessor can execute ten arithmetic and six logical operations on any data
presented to its A and B inputs (see Figure 4-11).
The ALU is built around two 74S 181 integrated circuit chips, each accommodating four bits or one
half byte. Four functional inputs feed the ALU while three others output from it. Two of the inputs are
8-bit operands. A third input, CARRY IN, is a carry function which can be inserted under control of
the microprocessor. The fourth and final input is a 5-bit function bus defining the type of operation to
perform on the two operands and carry in. This operation is defined by the FROM microword. The
FROM is shown in Figure 4-12 and the FROM map is shown on sheet 020 of the print set.
The result of any logical or arithmetic operation appears asynchronously at the A LU's output data bus
and on the leading edge of T240, and is clocked into the BALU. Another output Z becomes asserted
when the ALU output is all 1s. The third and final output is the carry bit. Both the carry bit and the
A = B output are clocked into storage flops, under control of the FROM microword.
Insertion of a carry occurs under one of two conditions defined by the FROM. A carry insert can be
forced with FORCE C H or inserted as a function of the C flip-flop with ENABLE C H.
4.2.9 Scratch pad Memory (SP)
The only way to present an operand to the ALU A input is through the SP memory. The SP contains
sixteen locations, all addressable by CROM bits 0-3. Two type 3101 integrated circuits chips, each
storing one-half byte, comprise the complete memory.
Addressing is controlled by a 74157 multiplexer, supplying one of two possible inputs as a 4-bit address
to the SP. Selection is by DI WRITE OUT H, which when asserted selects a hardwired input address
of zeroes. The default input is CROM bits 0-3. This signal is a bit in the DROM microword. The
DROM also controls writing into the SP. Data is written from the BALU output.

4-17

STB
74151

D7
D6

D5
D4

INPUTS

COMPLEMENTARY
OUTPUTS

D3
D2
FO

D1
DO
S2

S1
9

INPUT {
SELECT

- - - - - -.....
74151 TRUTH TABLE
SELECT

INPUT

H
H

D7-/.LP MISC REG

D6-NPR CNTL REG

D5-BPORT ODD BYTE

D4-BPORT EVEN BYTE

D3-BRG

D2-MEM

D1-LU IBUS

DO-CROM 0-7

REFER TO 06
OF M8200
PRINT SET

THE DMUX IS COMPOSED OF EIGHT74151 MULTIPLEXERS.
MK-0795

Figure 4-9

Configuration of DMUX

4-18

5610/6331
S ROM
08
CROM 15 H
CROM 14 H
CROM 13 H
CROM 7 H
CROM 4 H

14
13
12
11
10

9
7

OMUX SRC

6
5
4
3

MOV INST H
MOV INST L
IBUS* H

IBUS H
REFER TO D6
OF M8200
PRINT SET

32 WOROS x 8 BITS
SEE PRINT SET SHEET 020 FOR SROM MAP.

Figure 4-10

Configuration of SROM

4.2.10 Multiport RAM
The multiport RAM is an 8-word random access memory having the capability of being simultaneously accessed from two sources. Each word is sixteen bits in length. A total of four chips comprise
the multiport RAM with each chip containing 8-bit wide storage locations. A functional description of
the chips follow (refer to Figure 4-13).
Two independent read outputs are available, one referenced as the A PORT (pins 8, 9,10, and 11) and
the other as the B PORT (pins 13, 14, 15, and 16). Note that each read bus is four data bits wide.
Associated with each read port is an address input. Valid data appears at the A PORT output for the
location addressed by the A PORT address input (pins 6,5, and 4). A unique feature of this memory is
that another location can be simultaneously addressed by presenting this second address to the B
PORT address output. The read enable input (pin 7 for A and pin 17 for B) is tied low, enabling read
data from either port.
Although data can be read from both ports, it can be written only through one port, the A PORT. This
is done by presenting the desired address to the A PORT ADDRESS INPUT while simultaneously
presenting data to the A PORT WRITE DATA INPUT (pins"3, 2, 22, and 21). The necessary timing is
supplied through pins 1 and 23.

4-19

DMUX

SPOH-7H

DMUX OH-7H

,)7

...

~
./
CRaM

FROM

) FUNCT

CIN

I---

-Z(1)H

_ - C(1) H

ClK Z H -

-ClKC H-

4-7H,14H
AlUOH-7H

~
-

V
BAlU
EN C H

FORCE C H

MK-0797

Figure 4-11

ALU and Associated Logic

4-20

5610/6331
FROM
D1
CRaM 4 H
CRaM 5 H
CRaM 6 H
CRaM 7 H
CRaM 14 H

10
11
12
13
14

D7
D8

S3 L

S2 L

S1 L

SO L

FORCE C H

EN CH

CK C H

ALUINPUTS

REFER TO D7
OF M8200
PRINT SET

32 WORDS x 8 BITS
SEE PRINT SET SHEET D20 FOR FROM MAP.
MK-0798

Figure 4-12

WRITE
CLOCK

Configuration of FROM

825112
MPRAM

A3
BO
B1
82
83

}

A1
A2

DO
"A" PORT WRITE
DATA INPUT

D1
D2
D3

A & B PORT
ENABLE INPUTS

}

AA2 AA 1 AAO BA2 BA 1 BAO

"A" PORT READ
DATA OUT

liB" PORT READ
DATA OUT
REFER TO D9
OF M8200
PRINT SET

6
~ ~
liB" PORT
READ
ADDRESS

"A" PORT
READ/WRITE
ADDRESS

MK-0799

Figure 4-13

Multiport RAM

4-21

HIGH OR .
ODD BYTE

LOW OR
EVEN BYTE

IN DATA

OUT DATA

IN BA

OUTBA

SEL 0

SEL 2

SEL 4

SEL 6

NPR
BA/DATA

OUT/ IN BUS

OUT*/IN BUS*

MICROPROCESSOR
DEVICE

J t

_ _- - L_ _ _ _ _

ADDRESSES

UNIBUS
CSR

.....J

MPRAM
ADRS PINS
6
18

o = OUT/ IN BUS }

4
20

0
0
0
0

0
0
1
1

1
1
1
1

0
0

1
1

READ

0
1
1
1
1

1 = OUT*/IN BUS*

WRITE/READ

f WORD SELECTION

0,2,4,6
MK-0800

Figure 4-14

Multiport RAM Addresses

4-22

The multiport RAM address assignments are shown in Figure 4-14. Note that the memory is divided
into two blocks, one block in four words associated with the OUT jIBUS registers and the other with
OUT* jIBUS* registers. Stored in the memory as OUT jIBUS register addresses are both data and
addresses of the data for NPR transfers with the PDP-II memory. These multiport RAM memory
locations are applicable during NPR cycles. Additionally, the OUT* jIBUS* register addresses shown
are the UNIBUS CSRs as addressed from either the microprocessor or the UNIBUS.
The block diagram in Figure 4-15 illustrates the relative position of the multiport RAM within the
microprocessor architecture. Shown are the three output loads, the two data input sources, and the
addressing schemes.
The B PORT output data bus feeds both the UNIBUS address bus drivers and the DMUX. However,
because the DMUX is only eight bits wide and the RAM output is sixteen bits, the RAM output is fed
to the DMUX on two separate inputs.
When the microprocessor executes NPR cycles, the bus address will be fetched from the RAM through
the B PORT and clocked into the bus drivers by NPR MASTER. The two RAM locations where the
bus address is stored is defined by the B PORT address multiplexer with MP READ CYCLE low. This
results in addressing either location two or three, as determined by OUT NPR. On an OUT NPR, data
comes from the A PORT of the RAM through a multiplexer and onto the UNIBUS.
The remaining input to the B PORT address multiplexer becomes active during a particular Move
microinstruction (X) 1) and in turn gates the addressed data either to the high byte or to the low byte.
input on the DMUX. Bits 5, 6, and 15 determine the RAM address. Bit 15 determines which group is
to be addressed, the IBUS or IBUS* registers. The location within the selected group is addressed by
bits 5 and 6. The appropriate byte is selected by the DMUX.
With the A PORT, both reading and writing must be considered. The A PORT output bus feeds a 2to-l multiplexer which feeds the UNIBUS data bus drivers. Data is written into the RAM through
another 2-to-1 multiplexer which selects either the UNIBUS data receivers or the ALU output as the
data to be written.
There are three conditions under which data is written into the multiport RAM: (1) an input NPR
cycle, (2) loading a CSR by the PDP-II, and (3) writing by the microprocessor. MP WRITE CYCLE is
asserted when the microprocessor executes a write cycle. This condition then selects the ALU output to
be written into the RAM (as illustrated in Figure 4-15). On the other hand, the UNIBUS data receivers
are selected as the RAM input data for both NPR cycles and CSR loading.
A full word from the UNIBUS or one byte at a time from the microprocessor can be written into the
multiport RAM. This is controlled by HB WRITE Land LB WRITE L. When writing the ALU
output, the 8-bit byte can be written into either the high or low byte position. Bit zero of the microinstruction (CROMO) determines the byte position. During NPR cycles, full words are always written
into the RAM. When writing into a CSR, the PDP-II instruction determines the write control condition with CO and AO.
The A PORT addressing is determined through two levels of multiplexing (see Figure 4-15). CRaM
bits I and 2 determine addressing with the first multiplexer when the microprocessor writes into the
RAM. The second input to this multiplexer is an output of another multiplexer under the control of
NPR MASTER. During the execution of NPR cycles, one of two fixed locations (location 0 or I) is
always addressed. Which location is addressed is a function of desired data transfer direction. CSR
addressing is determined by the UNIBUS address bits AOI and A02, and always references the four
high RAM addresses.

4-23

ADDRESS DESTINATION
DURING MICROPROCESSOR
MOV INSTRUCTION.

SOURCE ADDRESS
DURING MOV
OP CODE X01.

MP RAM
B
ADDRESS
MUX

MPRAM

ADDRESS CSR
DATA DURING
READ/WRITE.

ADDRESS
MUX

r------'

r-------'

CROM 5,6,15

OUT NPR,O,l

BUS ADDRESS
DURING MOV

UNIBUS
ADDRESS

OUT NPR,

~_---,

MP ADRS
MUX

WRITE
CONTROL
LOGIC

ADDRESS
LOCATION
DURING NPR.

AADRS

B ADRS

B PORT 0-15

UNIBUS
TRANS·
CEIVERS

B PORT
MPRAM

ALU OUT
0-7

UNIBUS
ADDRESS
BITS AO-A17

A PORT 0-15

MP
RAM
MUX

DATA

A PORT

~------~

2:1
UNIBUS
DO-D15

MUX
CROM 0-15

'------,

UNIBUS
TRANSCEIVERS
UNIBUS
DATA
BITS DO-D15

MK 0801

Figure 4-15

Block Diagram of Multipart RAM and Associated Logic

4.2.11

INBUS/OUTBUS and INBUS* /OUTBUS* Registers

The UNIBUS Control and Status Registers are physically located in the multiport RAM. The RAM
capacity is 128 bits arranged as sixteen 8-bit bytes, which is equivalent to eight 16-bit words.
There are two additional byte-sized hardware registers that are listed in the OUTBUS* /INBUS*
category. They are the NPR Control Register (lOg) and the Microprocessor Miscellaneous Register
(llg). The microprocessor has the capability of addressing 32 byte-sized registers. As a convention, it
has been decided to show 16 assigned under each category, that is, OUTBUS* /INBUS* registers
(Figure 4-16) and OUTBUS/INBUS registers (Figure 4-17). As a result, six undefined registers 12-17
(octal) are listed under OUTBUS* /INBUS*. These registers do not exist physically. The line unit
device registers, 10g-17g have been added to the OUTBUS/INBUS register category. These registers
are physically located in the line unit. Address 109 is listed twice because two line unit registers use the
same address. The In Data Silo is read only and the Out Data Silo is write only. Therefore, there are
nine registers in the line unit.

DMCll
REGISTER
DESIGNATION

BITS
7

o
o

INCON

BYTE 0

MAIN

BYTE 1

OCON

BYTE 2

BYTE 3

PORTl

BYTE 4

PORT2

BYTE 5

PORT3

BYTE 6

PORT4

BYTE 7

NPR
UBBR

BYTE
XFER
BUS VECTOR
RO
XX4

OUT
NPR
PGM
ClK

IN BA IN BA
17
16
OUT OUT
BA17 BA16

R/W
AC
lO

NPR
RO
NON
EX
MEM

UNIBUS CSRS
AS VIEWED FROM
MICROPROCESSOR.

10 NPR CONT
11

p,P MISC

UNASSIGNED.
ADDRESSABLE
BUT NOT PHYSICALLY
PRESENT.

MK-0802

Figure 4-16

OUTBUS* /INBUS* Assigned Addresses

4-25

DMC11 REGISTER
DESIGNATION
7

BITS

INDAT1

IN DATA LB

INDAT2

IN DATA HB

ODAT1

OUT DATA LB

ODAT2

OUT DATA HB

IBA1

IN BA7:0

IBA2

IN BA 15:8

OBA1

OUT BA 7:0

OBA2

OUT BA 15:8

RCVDAT

IN DATA SILO

TMTCON

OUT
CLR

OUT
ACT

OUT
ROY

TEOM TSOM

OUT DATA SILO

TMTDAT
RCVCON

IN
CLR

IN
ACT

LU
LOOP

IN
RDY

MODEM

RING

DTR

MOD
ROY

11
10

BLK
BCC
END MATCH

IN CONT

MODEM CONT

SYNC

SYNC CHAR/SECONDARY ADRS

LlNDSW

PASSWORD (SW PACK #2)

BM873

BOOT-OFFSET (SW PACK #3)

OCOR

ICIR

OUTCONT

LU DDCMP
CLK MODE

LINE UNIT
REGISTERS

MAINT

MK-0803

Figure 4-17

OUTBUS/INBUS Assigned Addresses

The physical arrangement of OUTBUS* /INBUS* registers and OUTBUS/INBUS registers is shown
in Figure 4-18.
The detailed discussion of the Line Unit CSRs is contained in the DMCII IPL Synchronous Line Unit
Maintenance Manual (EK-DMCLU-MM-002).
4.2.11.1 NPR Control Register 10 - Refer to Figure 4-16. NPR Control bit descriptions are provided
in Table 4-1.
4.2.11.2 Microprocessor Miscellaneous Register 11 - Refer to Figure 4-16. Miscellaneous register bit
descriptions are provided in Table 4-2.
4.2.11.3 OUTBUSjINBUS Assigned Addresses - Refer to Figure 4-17. Register byte descriptions of the
OUTBUS/INB-US registers is provided in Table 4-3.

4-26

DMC11 LINE UNIT

DMC11 MICROPROCESSOR

MULTIPORT
RAM LOCATION

INDAT1

INDAT2

ODAT1

ODAT2

IBA1

IBA2

OBA1

OBA2

INCON

MAIN

OCON

2
3

13
14

PORT1

OUTBUS"'j
IBUS'"
REGISTERS

PORT2

PORT3

PORT4

OUTBUS/
IBUS
REGISTERS

RCVDAT

---

[ ~]
- --

TMTCON

TMTDAT

RCVCDN

MODEM

110

OUTBUS/

>IBUS

LNDSW

REGIST14 ERS
15

BM873

LU MAINT

SYNC
NPR

UBBR

111

MK-0804

Figure 4-18

Physical Arrangement of Registers

4-27

Table 4-1 NPR Control Register (OUTBUS* jINBUS*
Register Group) REG 10 Bit Description
Bit

Name

Description

NPR REQUEST
(NPR RQ) (R/W)

This bit can be set only by the microprogram. It initiates an N PR cycle
for data transfers (bidirectional) between the microprocessor and memory. This bit is used in conjunction with OUT NPR (bit 4) and BYTE
TRA NSFER (bit 7) to determine the direction of the data transfer and
whether a word or byte is to be transferred to memory. It is automatically clocked clear by 015 N PR DON E H when the N PR has been
completed. Bit 7 (BYTE XFER) controls word/byte selection.
The data for NPR/DATA IN is loaded into OUTBUS/IN BUS Registers 0 and/or I. The data for NPR/DATA OUT is read from OUTBUS/INBUS Registers 2 and/or 3.
When BYTE XFER is set, the state of the BA least significant bit (0) is
used to select the byte. The truth table for the type of transaction, as
selected by these bits, is shown below.

(Cl )

(CO)

BAO

UNIBUS
TRANSACTION

DATI

Illegal

DATO

DATOB (Low Byte)

DATOB (High Byte)

4-28

Table 4-1 NPR Control Register (OUTBUS* /INBUS*
Register Group) REG 10 Bit Descriptions (Cont)
Name

Description

READ/WRITE (R/W)

This read/write bit provides no function and may be treated in
the microcode as a flag or state indicator.

2,3

IN BA 16 and IN BA
(R/W)

These are the PDP-II memory extension 17 bits used during an
IN NPR (CI = 0) transaction (DMA transfer from memory to
the microprocessor).

OUT NPR (R/W)

This bit is used in association with N PR RQ (bit 0). It controls
the direction of DMA data between the microprocessor and
memory. When set, data direction is from the microprocessor to
memory. The details of the inter-relationship between these bits
are covered in the description of NPR RQ (bit 0).

5,6

RESERVED

Non-existent bits, always read as o.

BYTE XFER (CO)(R/W)

This bit is used in association with OUT NPR to indicate a byte
transfer to the PO P-II memory. When this bit is set, the PD PII uses address bit AO for byte selection. If AO is a 0, OUT
DATA <7:0> is stored in the low byte of the PDP-II memory.
If AO is a I, OUT DATA < 15:8> is stored in the high byte of
the PDP-II memory. If BYTE is clear during an OUT NPR
operation, OUT DATA < 15-0> is transferred to the PDP-II
memory as a word.

Bit

Table 4-2

Miscellaneous Register (REG II)
(OUTBUS* jINBUS* Register Group)
Bit Descriptions

Bit

Name

Description

NON-EX MEM (R/W)

During an NPR, this bit is set approximately 20,us after a nonexistent memory location is addressed by the microprocessor
with no slave SYNC response. At this time, the NPR logic releases the UNIBUS. This is an error condition, indicating:
•
•
•
•

2,3

Incorrect address provided by software
Memory failure
Address Logic failure
UNIBUS failure

AC LOW (R/W)

Set by the microprogram to initiate a power fail sequence at the
main CPU. This bit clears automatically upon completion of
the sequence.

OUT BA 16 and
OUT BA 17 (R/W)

These are the PDP-II memory extension bits used during an
OUT NPR transfer; DMA transfer from the microprocessor to
memory.

4-29

Table 4-2

Miscellaneous Register (REG II)
(OUTBUS* /INBUS* Register Group)
Bit Descriptions (Cont)

Bit

Name

Description

PGM CLK R/W

This bit acts as a timer for the microprocessor. It can be read to
determine lapse time for time out, flag testing, etc. When written, it starts a one- second retriggerable one-shot.
When read, it indicates 0 output of the retriggerable I-shot with
a one-second pulse.
As long as the bit is written to a I at less than one second intervals, the I-shot remains asserted and this bit is read as a O. If the
I-shot times out, this bit is read as a I.
The program clock causes no hardware action. Its use is totally
dependent upon microprogram implementation.

RESERVED

Nonexistent bit, always read as O.

VECTOR AT XX4 (R/W)

If this bit is set when BR RQ (bit 7) is set, vector address XX4 is
generated. If it is cleared when BR RQ is set, vector address
XXO is generated. Address XXO is associated with RDI and
address XX4 is associated with ROO.

BUS RQ (R/W)

When set, this bit initiates a Bus Request via the UNIBUS at
BR level 4, 5, 6, or 7. The microprocessor is shipped with a BR5
priority plug installed. This bit can only be set and is clocked
clear by the hardware after the BR has been completed by signal
016 BR DONE H. This bit is also cleared by BUS INIT, but
not by MCLR (bit 14 of SEL 0).

Table 4-3

OUTBUS/INBUS Registers Byte Descriptions

Name

Description

0, 1

IN DATA

Low byte (register 0) and high byte (register I) of N PR data to be transferred from the PDP-II memory.

2,3

OUT DATA

Low byte (register 2) and high byte (register 3) of N PR data to be transferred to the PDP-II memory.

4, 5

IN BA

Contains BUS Address (BA) bits 0-15 during an NPR transfer from the
PDP-II memory. Bit 0 of register 4 is BA bit 0 and bit 7 of register 5 is
BA bit 15.

6, 7

OUT BA

Contains Bus Address (BA) bits 0-15 during an NPR transfer to the
PDP-II memory. Bit 0 of register 6 is BA bit 0 and bit 7 of register 7 is
BA bit 15.

4-30

4.2.12 Maintenance CSR (BSEL I)
Refer to Figure 16. A number of maintenance features are available for the DMCII through the use of
the MAINTENANCE CSR. The MAINTENANCE CSR address is 76XXXI and can be referenced
via a word or byte transfer. With this feature, the PDP-II diagnostic program can read the contents of
the CRaM, write into the MAINTENANCE INSTRUCTION register (thereby substituting the
CROM microword), step either or both the microprocessor and the line unit, and loop transmitted
data through the line unit back to the microprocessor for verification.

DATA BITS
BSEL 1

2
MK-OS11

DATA BITS AS
VIEWED FROM
THE MICROPROCESSOR.

The MAINTENANCE CSR byte format is illustrated above with the logic shown on drawing 017 of
the M8200 Print Set. Five of the bits are stored in the microprocessor each time the MAINTENANCE
CSR byte is written from the PDP-ll. 009-D12 are stored in a 74174, while DI5 is stored in a 74S74
on the leading edge of LD BSEL OIL (provided the BYTE SEL 01 LOCK OUT switch is off). This
switch must be off to enable all diagnostic features. When on, the RUN INHIBIT switch prevents the
R UN flop from setting. This switch must be off to enable the microprocessor to enter R UN mode. The
two remaining bits 014 and D08 pulse the microprocessor when written as a I by the PDP-II.
NOTE
All eight bits of BSEL I are written to the multi port
RAM, as well as the five internal flip-flops. A read of
BSEL I always gives the contents of the MP RAM,
and may not be representative of the internal flipflops. For example, if BSEL I Lockout Switch is
ON, and the RUN INHIBIT Switch is ON, the
PDP-II moves all ones to BSEL I; examination of
BSEL I reads as all Is, yet the internal flip-flops
have not been set.
4.2.12.1 Step LU H - This signal, a function of bit 12, feeds directly to the line unit interface controlling the stepping of the line linit. When set, it clocks the line unit transmitter and when it is cleared
it clocks the line unit receiver (completes I-bit time).
4.2.12.2 LU Loop H - This signal, a function of bit 11, feeds directly to the line unit enabling the
internal loopback feature. With this feature, the diagnostic program can transmit known data which
the line unit then sends back to the microprocessor as received data. The program then performs a
comparison on transmitted data and received data to determine if any errors had occurred.
4.2.12.3 ROM OUT H - Under control of bit la, the diagnostic program can read the contents of the
CRaM in order to determine the validity of machine cycling. A combination of the CRaM OUT H
and A2H (a read of SEL 4 or 6) gate the CRaM microword specified by the Program Counter through
a multiplexer. The output of the multiplexer is used to drive the UNIBUS data lines. This means that a
second instruction, a DATI with an address of XXXXX4 s , must be executed following the setting of
ROM OUT. This enables the multiplexer on print Oil to select the CRaM microword and feed it to
the UNIBUS data lines.

4-31

NOTE
Detailed bit descriptions of BSEL 1 are provided in
Chapter 5.
4.2.13 Microprocessor Clock
The basic clock consists of six JK flip-flops interconnected as a shift register generating six discrete
time intervals. Each 'time interval is asserted for a period of 60 nsec. However, due to unique docking,
four time intervals overlap resulting in an overall clock period of 300 nsec instead of the expected 360
nsec. Figure 4-19 illustrates the clock sequencing. Note the overlap of T90 with T60 and T240 with
T210. These clock signals are distributed throughout the microprocessor to clock registers and provide
system timing.
A 33.33 Mhz oscillator generates the timing used to clock the shift register. However, before being
applied to the clock inputs of the shift register, the oscillator output (CK) first passes through a control
flop (WAIT SYNC) and a divide-by-two flop (SYSTEM CLOCK). (See drawing D14 in the Print Set.)
Th1e control flop WAIT SYNC stops the clock when the multiport RAM is being accessed and allows
the clock to continue only when the multi port RAM becomes available. This clock hold state is in
effect with WAIT SYNC in the reset state. But with WAIT SYNC set, SYSTEM CLOCK toggles with
each high to low transition on its clock input. Both outputs of SYSTEM CLOCK (Q AND Q) are used
as shift register clocks.

T60

T90

T30

T60

T90

T120

T150

T180

T210

T240

T270

T300

T330

0-60

60-120

90-150

T150

150-210

T210

210-270

T240

240-300
MK-0805

Figure 4-19

Clock Sequence

4-32

T360

Refer to drawing D14 for the following logic analysis. Note that the flip-flops TO through T240 are
wired as a right-shifting shift register with T240's output dropping off into the bit bucket. TO's JK
inputs are wired to toggle TO when the four flip-flops T60, T90, T 150, and T21 are all reset and RUN
SYNC is set. Note that the shift register does not use the same clock source for all positions. T90,
T 150, and T210 are clocked by the Q output of SYSTEM CLOCK, while TO, T60, and T240 are
clocked by SYSTEM CLOCK's Q output. The aforementioned overlap of time intervals is generated
by using these two clocks 180 0 out of phase.

Given the initial conditions of RUN SYNC and WAIT SYNC both set, and the shift register all
zeroes, results in a high condition on both the J and K inputs to TO placing TO in the toggle mode. The
next time SYSTEM CLOCK sets, TO will set. This point in time is refered to as "time 0" (see Figure 420). With TO set, the set input to T60 is qualified while simultaneously the toggle input to TO remains
asserted. Therefore, on the next SYSTEM CLOCK occurring 60 nsec later, T60 sets and TO resets.
From this point, the clock functions as a shift register. When the bit reaches T240, a new bit is regenerated at the inputs to TO.

TO
I

T60

T90

T150

T210

T240
I

T300

CLOCK

SYS CK (1) H

SYS CK (1) L

T60

T90

T150

T210

T240

MK·OB06

Figure 4-20

System Clock Timing Diagram

4-33

The microprocessor cycling can be halted by stopping the SYSTEM CLOCK, this is done by resetting
the RUN flop. When the RUN flop is reset, RUN SYNC allows the clock shift register to complete the
current clock cycle and stop with the shift register cleared.
In Step Mode, each STEP MC L pulse sets RUN SYNC, allowing one complete clock cycle (TO T240) to occur.
4.2. 14 Address Selection Logic
Drawing D16 illustrates the logic used to recognize a DMCII microprocessor address. The JK flop
OSSYN sets upon address recognition. The assigned address is configured with ten switches, each
switch associated with a unique address bit. Address bits A3 through A 12 are available for configuration, allowing an addressing range of four words within the DMCII microprocessor.
The logic compares the switch code with the respective address bits using two comparator chips whose
outputs are wire OR connected. When the inputs are equal bit for bit, the comparator outputs go high.
The remaining high-order address bits, A 13-A 17, all of which must be true, are ANDed with MSYN
to produce a set condition on the inputs to OSSYN. On the next clock (CK) OSSYN sets. BOSSYN is
asserted 130 nsec later, acknowledging bus master.
4.2.15 NPR Control Logic
Initiation of an NPR cycle is under complete control of the microprogram. To initiate an NPR cycle, a
Move microinstruction referencing the OUTBUS* register is executed, moving bit 0 to Register 108.
This microinstruction sets NPR RQ. Once NPR RQ sets, the logic then executes the NPR cycle
asynchronously with respect to the microprogram.
Figure 4-21 illustrates the timing sequence for an output NPR cycle. The requirements for execution
are: (1) a UNIBUS addres.s, (2) data gated to the UNIBUS, (3) a DATO defined via CO and Cl, and (4)
assertion of master sync (MSYNC). Drawing D15 contains the relevant logic. The addressed unit
(slave) then recognizes its address and interprets the control lines. After gating the data from the
UNIBUS, the slave acknowledges receipt of the data by asserting slave sync (SSYN).
Refer to Figure 4-21 and drawing D15 for the following discussion. First, the standard handshake for
bus control takes place. The timing begins with the assertion of NPR RQ (1) which in turn generates
the bus signal DATA BUS NPR L. The central processor then responds with DATA BUS NPG IN H,
provided no other device was already queued up for bus mastership. When BUS NPG IN H does
arrive at the microprocessor, it resets BUS NPR L following a delay of 70 nsec. In addition, further
propagation of the grant signal to other devices is prevented by the microprocessor. The grant signal
also sets selection acknowledge (SACK), acknowledging to the central processor the reception of the
grant signal. At this point, the microprocessor becomes the next bus master as soon as the current
master relinquishes control. The microprocessor monitors BBSY to determine when to take control.
Once the previous bus master relinquishes the bus and provided the microprocessor is queued up to be
next [SACK(1) H], the microprocessor then takes control by asserting BUS BBSY L. Simultaneously,
SACK is reset and NPR MASTER is set. The actual data transfer can now take place.
The address is gated to the UNIBUS with NPR MASTER as well as CO and C 1. Data, on the other
hand, is gated to the data bus under control of DATA BUS L. These three conditions occur simultaneously during an OUTPUT NPR cycle. On the leading edge of NPR MASTER, a 150 nsec delay is
triggered, at the conclusion of which BUS MSYN is asserted. The slave gates in the data off the
UNIBUS and responds with SSYN, indicating acceptance of the data.

4-34

NPR RQ (1) H
BUS NPR L

BUS NPG IN H

BUS SACK L

BUS BBSY L
NPR MASTER H

:
,

(

START
CK 1
CK 2
OMSYN L

SSYN H
NPR DONE (1) H

MK-OB07

Figure 4-21

NPR Output Timing Diagram

INPUT NPR cycle timing illustrated in Figure 4-22 is, for the most part, similar to the OUTPUT NPR
cycle. In this case, the microprocessor waits for the addressed slave to respond with data and BUS
SSYN. The microprocessor then loads the data into the multiport RAM and acknowledges receipt by
dropping BUS MSYN and subsequently terminating the NPR cycle.
4.2.16 Interrupt Control Logic
Execution of an interrupt cycle is accomplished through a two-phase operation. First, bus mastership
must be gained and then the actual INTERRUPT cycle is executed.
Figure 4-23 illustrates the timing sequence for execution of an INTERRUPT cycle. The entire process
is initiated with the assertion of BR RQ in the Microprocessor Miscellaneous Register. A Move microinstruction having an output address of 118, 'with bit 7 of the operand equal to ai, sets BR RQ.
With both BR MASTER and SACK still reset, the condition is satisfied to generate BUS BR L. BUS
BR L feeds the priority plug which in turn generates the appropriate bus request signal to the central
processor. The interrupt logic then stalls, awaiting the bus grant signal from the PDP-II processor.
When bus grant arrives (BUS BG IN), it sets SACK and resets BUS BR L. At this point, the microprocessor becomes the next bus master after the current bus master relinquishes bus control. When this
happens, BR MASTER (1) H sets, beginning the INTERRUPT cycle. BUS INTR L is asserted while
the microprocessor logic simultaneously places the interrupt vector address onto the data bus. The
operation is concluded when the central processor acknowledges receipt of the interrupt with BUS
SSYN.

4-35

NPR RQ (1) H

-.J~

BUS NPR L
BUS NPG IN H

---{

BUS SACK L

---1

BUS BBSY L

---f

NPR MASTER H

---f

START
CK 1
CK 2
OMSYN L
SSYN H

NPR DONE (1) H
NPR LD
MULTIPaRT L
MK-0808

Figure 4-22

NPR Input Timing Diagram

4-36

BR RQ H

BUS BR L

BG IN H

BUS SACK L

BUS BSSY L

BR MASTER (1) H

BUS INTR L

BUS VECTOR ADRS

SSYN H

--------~f~------------------

BR DONE H
MK-0809

Figure 4-23

Interrupt Timing Diagram

4-37

4.2.17 Line Unit Interface
Interconnection between the microprocessor and the line unit is accomplished via the line unit interface. The interface cable carries 33 signal lines between the two units, of which eight originate in the
line unit and the remaining 25 in the microprocessor.
4.2.17.1 LU IBUS 0 H - LU IBUS 7 H - These eight lines are the line unit input bus. This bus
originates in the line unit and deiivers data to the microprocessor from the register addressed by "the
microword (CROM O-CROM 3).
4.2.17.2 BALUOL - BALU7L - These eight lines are the microprocessor output bus. The data goes to
the buffered ALU register and then to the interface on to the line unit.
4.2.17.3 IBR L/IBR*H - This signal acknowledges to the line unit receipt of data, and is asserted
during T240.
4.2.17.4 BT240 - BT240 is used to synchronize the line unit with the microprocessor (not used by
DMCll line units M8201, M8202 - YA/YD).
4.2.17.4 OBW L - This signal is the output data strobe. The line unit uses this signal to clock or
strobe the output data into an internal register (not used by DMCII line units M8201, M8202YA/YD).
4.2.17.5 OUT * L - When asserted low, this signal indicates to the line unit that the destination of
data for the current microinstruction is a register in the OUT* group. The line unit registers are in the
INBUS/OUTBUS group; therefore the line unit register address decoder is disabled by D3 OUT*L.
4.2.17.6 CROM 0 L - CROM 7 L - These CROM bits are the input/output address used by the line
unit to address internal registers. The output registers are addressed by CROM 0-3 and the input
registers with bits CROM 4-7.
4.2.17.7

Clear - This signal initializes the line unit, placing it in a reset state.

4.2.17.8 LU Loop - With this diagnostic function, the line unit loops data from its transmitter to its
receIver.
4.2.17.9
line.

Step LU - This signal commands the line unit to shift data by 1 bit per cycle of the STEP LU

4.2.18 Typical System Timing
Typical system timing is illustrated in Figures 4-24 and 4-25. Figure 4-24 shows applicable signals used
in an output cycle along with typical line unit logic. Note that the address is valid from T90 through
T300 while the data for the cycle in question is valid from approximately T270 through the next T240.
The data is strobed into an internal register with the low-to-high transition of OBW L.
Input bus timing is illustrated in Figure 4-25. Again, the address is valid for the same period as in the
output cycle (T90-T300). The line unit then places data onto the input bus during its T5 time, which
approximately coincides with T160-T240 in the microprocessor. The microprocessor acknowledges
receipt of the line unit data by asserting IBR during T240-T300.

4-38

60 NS

120 NS

180 NS

240 NS

OUT ADRS
(CRaM 0-3)

300 NS

OUT ADRS VALID
TI~

DATA VALID
(Previous data)

OUT DATA
(BALU 0-7)

T3 \~

I~T6=1~

OUT DATA
STROBE (OBW)

DATA STROBED ON LOW
TO HIGH TRANSITION

)
MK-0831

Figure 4-24

Typical Output Bus Timing

60 NS

120 NS

IN ADRS
(CRaM 4-7)

180 NS

240 NS

300 NS

IN ADRS VALID

IN DATA
(IBUS 0-7)

IN DATA
ACCEPTED (IBR)
MK-0810

Figure 4-25

Typical Input Bus Timing

4-39

CHAPTER 5
SERVICE

5.1

SCOPE

Servicing the DMCII is based on the maintenance functions contained in the CSRs and the maintenance philosophy established for this product. This chapter covers the maintenance modes, preventive
ahd corrective maintenance, and includes the DMCII diagnostics.

5.2

MAINTENANCE FUNCTIONS/MAINTENANCE MODES

The maintenance functions are available to the DMCII via the maintenance CSR (BSEL I). Maintenance and system tests constitute the maintenance modes.

5.2.1

Maintenance Register (BSEL 1)

This register contains the high byte of address 76XXXO. A brief description of the CSR byte is provided in Chapters 3 and 4. The byte format and bit descriptions are provided in detail in this section.
DATA BITS
BSEL 1
MK-0812

BSEL I contains all maintenance functions including MASTER CLEAR and is not intended for
normal user communications between the PDP-II program and the microprocessor. These functions
override all other control functions. All bits are read/write; only MASTER CLEAR is functional if the
BSEL I LOCK OUT switch is set (see DMCII Engineering Drawings - DMCII-O-8).
Table 5-1 describes the bit functions of BSEL I.

5.2.2

Maintenance Modes

The DMCII microprocessor can be tested by two basic modes:
•

Maintenance Mode

•

System Test (free-running) Mode

The DMCII line unit can be tested by three basic modes:
•

Single Step Internal Maintenance Mode

•

System Test Internal Maintenance Mode

•

External Maintenance Mode

5-1

Table 5-1

BSEL 1 Bit Descriptions

Bit

Name-

Description

STEP P
(Step Microprocessor)

When bit 8 is set, it steps the microprocessor through one instruction cycle which is composed of five 60 nsec pulses. The RUN flipflop should be cleared before executing this control function.

ROM I
(ROM Input)

Bit 9 is set and directs the contents of BSE-L 6 and 7 as the next
microinstruction to be executed by the microprocessor when STEP
P is asserted.

ROM a
(ROM Output)

Bit lOis set and modifies the source paths for BSEL 4 through 7 to
contain the contents of the addressed CRaM. If ROM OUT and
STEP P are asserted, then the next CRaM address wi11 be output
to BSEL4 through 7.

LU LOOP
(Line U nit Loop)

Bit II is set and connects the line unit's serial line out back to its
serial line in. This loop back is done at the TTL level before level
conversion.
When the LU LOOP bit is set and the RUN bit (bit 15) is cleared,
the STEP LU clock is the only one available for shifting data in or
out.
When the LU LOOP bit is set and the RUN bit is set, data is
clocked at 10K bps for the M 820 I and 20K bps for the M 8202.
If the LU LOOP bit is cleared and the R UN bit is set, the loop
back test connector is required.
LU LOOP

RUN

CLOCK SOURCE bps

Mode

Set

Clear

STEP L U (bit
12) via PROGRAM

Single
Step
Internal
Maintenance

Set

MAINTENANCE 10K
CLOCK
M8201;
20K
M8202

.System
Test
Internal
Maintenance

Clear

Set

MAINTENANCE 10K
CLOCK (M8201) M8201

External
Maintenance

INTEGRAL
line
MODEM CLOCK unit
(M8202)
speed
M8202

5-2

Table 5-1
Bit

Name

BSEL 1 Bit Descriptions (Cont)

Description
NOTE
The DMCll must be set up in full-duplex mode to run in any loopback maintenance mode. For external loopback mode, test connectors H325/H3250 or 12-12528 are required on the M8201 or
M8202-XX respectively.

STEP LU
(Step Line Receiver)

Reserved

MCLR
(MASTER CLEAR)

When bit 14 is set, MCLR initializes both the microprocessor and
the line unit. This bit is self clearing. The microprocessor clock is
enabled and the RUN bit is asserted, placing the D MC U in the
initialized state.

RUN

RUN controls the microprocessor clock: bit 15 is set by BUS initialization or MASTER CLEAR which enables the microprocessor clock. RUN can be cleared for maintenance by RUN
INHIBIT switch (E76). See D 17 of the M8200 Print Set. Switch
BST is provided to prevent RUN from being cleared by a runaway
microcode program when the microprocessor malfunctions. Further discussion of the RUN INHIBIT switch is contained in Chapter 2, Installation.

When bit 12 is asserted, the transmitter shifts; when it is negated,
the receiver shifts. This control function is used in conjunction
with LU LOOP bit 11 to simulate transmit and receive clocks for
line unit maintenance in Single Step Maintenance mode.

5.2.2.1 Maintenance Mode - The Maintenance Mode can be invoked using selected bits of BSEL 1.
These can be used to halt the microprocessor (clear bit 15), step the microprocessor (set bit 8), examine
the current CRaM location (assert bit 10 and examine SEL 6), and override the current CRaM
instruction with a different instruction and execute that instruction (load SEL 6 with the new instruction, assert bits 8 and 9, then clear bit 8).
1.

NOTE
Be sure that BSEL 1 LOCK OUT (switch 9,
E76) is OFF to allow access to the maintenance bits in BSEL 1.
With the LOCK OUT switch ON, it is still
possible to MASTER CLEAR the microprocessor by setting bit 14 of BSEL 1.

5.2.2.2 System Test - System Test Mode tests the functionality of the microprocessor and line unit
running at full speed and utilizing the control ROM.
NOTE
RUN INHIBIT (switch 7, E76) must be off to use
this mode and ensure normal operating conditions.

5-3

5.2.2.3 Single Step Internal Maintenance Mode .- This mode is selected by the PDP-II program setting LU LOOP and clearing RUN bits II and 15 of BSEL I respectively. This mode allows checking of
most of the line unit without disconnecting the M8201 from the modem or the M8202 from the triaxial
cable. Line unit signal D 15 SEND H is asserted to keep the transmitter active. The transmitter output
is looped back at TTL level to become the receiver input. Line unit REQUEST TO SEND (RTS) and
DATA TERMINAL READY (DTR) signals are held unasserted. The clocking source is the DI7
STEP LU signal from the microprocessor which becomes D3 STEP LU at the line unit. The PDP-II
program generates the clock signal which sets STEP LINE UNIT bit 12 of BSEL 1.
5.2.2.4 System Test Internal Maintenance Mode .- This mode is selected by the PD P-I'I program
setting LINE UNIT LOOP bit 11 of BSEL 1. This mode allows the program to perform an off-line
system test by free-running the DMCII and checking the line unit without disconnecting the M8201
from the modem or the M8202 from the triaxial cable. The transmitter output is looped back at TTL
level to become the receiver input. The clock source is the DMCII maintenance clock which is 10 KHz
for the M8201 and 20 KHz for the M8202 line units.
5.2.2.5 External Maintenance Mode - External Maintenance Mode is selected by the PDP-II program setting the DMCII in normal running mode and terminating the cables with a test connector.
For the M8201 line unit:
•

The modem must be disconnected and the test connector must be connected to the BC05C25 cable. For the DMCII-DA option (EIA/CCITT V.24 interface), use connector H325.
For the DMCII-FA option (CCITT V.35 interface), use connector H3250 (see Figure 2-3 in
Chapter 2).

•

The 10 KHz internal clock used for clocking the M8201 is looped back in the H325 test
connector to simulate modem transmit and receive clocks.

•

The modem control signals are tested to ensure the proper level conversion and cable paths
exist. The signals are looped back in the H325 connector as follows:
Transmitted data is returned as received data.
REQUEST TO SEND is returned as CLEAR TO SEND.
DATA TERMINAL READY is returned as RING and DATA SET READY.

For the M8202 line unit:
•

The triaxial cables must be disconnected and the 12-12528 triaxial adapter must be used to
connect the coaxial pigtails attached to the modules. This setup tests all the transmitter and
receiver logic as well as the integral modem and pigtails.

•

The integral modem clock supplies clocking for the M8202.

External Maintenance Mode provides complete checking of the line unit including level conversion
logic and associated cables.

5-4

5.3 MAINTENANCE PHILOSOPHY
The Field Replaceable Unit (FRU) for any DMCII is the failing module or cable. Spare parts are not
stocked for module repair in the field. One reason for this is the time and equipment necessary for
component level troubleshooting and repair.
•

Typical applications of the D M C II do not permit lengthy troubleshooting sessions which
require the associated system to be down for that period.

•

Effective component level repair of a DMC II requires, at a minimum, a I6-channel logic
analyzer.

Training of field service personnel in the maintenance of the DMC 11 is not directed to the logic gate
level, but to functional and application level troubleshooting, using diagnostics for fault isolation to
the FRU. Changing ICs should only be done during implementation of Field Change Orders (FCOs),
a major reason for installing CROMs in sockets.
I

Replacement of CROMs requires removing installed CROMs and inserting new ones. An FCO with
procedures on how to replace CROMs is normally accompanied by a change to the diagnostics.
When replacing CROMs:
•

Be careful not to bend the IC leads.

•

Inspect the IC chip after insertion to ensure no leads are bent under the chip.

•

Ensure that CROMs are firmly seated and are in their proper sockets; otherwise, erratic
operation of the DMCII may result.

5.4 PREVENTIVE MAINTENANCE (PM)
There is no specific DMCII PM schedule. It is recommended that the DMCII be given a general
check (for such things as voltages and connections) and when system PM is performed.
A complete checkout of the device by running all diagnostics and if possible, the interprocessor test, is
required after handling the DMCII modules or cables for the following reasons. Special care must be
exercised in all cases.
•

The DMCll is susceptible to seating problems.

•

Control ROM (CROM) chips installed in sockets are easily dislodged during removal and
replacement of the M8200 module or adjacent modules. The CROM chips may inadvertently come in contact with the etch side of the adjacent module.

•

AMP connectors recommended for use in DMCII cabling permit destruction of pin/wire
connections. Servicing personnel must only twist the ring on the pigtail connector, while
firmly holding the raised ridge portion of the cable and connector. If the wrong part (such as
the body of the cable end connector) is twisted, the wires are separated from the pins.

5-5

5.5 CORRECTIVE MAINTENANCE
Because the FRU is a module or cable, all corrective action should be directed to isolation of the
failing FRU. The DMCII diagnostics are designed as an aid in the isolation process and as such,
should be run starting with the basic microprocessor test and continuing to the interprocessor test. The
diagnostics are listed in the proper sequence of execution below.
Diagnostic

Description

CZDMC

DSC-W JR-Micro-Proc-Test
(formerly Basic Microprocessor Test)

CZDME

DDCMP-MD-LN-UNIT-TST
(formerly Line Unit Test)

DZDMF

DMC Bit Stuff Line Unit Test

CZDMG

DMC ROM and Jump Test

DZDMH

DMC Free-Running Test

DZDMO

DMC ITEP-OVERLA Y Interprocessor Test

The testing sequence allows progressive expansion of testing, based on successful completion of the
previous test. All tests from DZDMC through DZDMG check the DMCII logic without running the
actual CROM microcode.
NOTE
The following sections reference DMCll microprocessor internal components, such as,
IBUSjOUTBUS Registers, IBUS* jOUTBUS*
Registers, Scratch pad Registers (SPX), Branch
Registers (BRG), Main Memory, Memory Address
Register (MAR), and Arithmetic Logic Unit (ALU).
Chapter 4 describes these components in detail.

5.5.1 CZDMC Diagnostics
CZDMC tests operation of DMCII SELO through SEL6 registers, microprocessor instructions, and
NPR operations; DMCII microcode is not used. The microinstruction is loaded into SEL6 and singlestepped to test the IBUS Register, IBUS* Register, SP, Main Memory and ALU.
A summary of tests performed (test numbers in octal) are shown below. For greater detail, refer to
diagnostics listings.
TESTS 1-30 test DMCll register selection; read/write functions of the DMCII registers SELO
through SEL6.
TEST 31 tests the DMCII microprocessor by loading a microinstruction in SEL6 and verifying that
the instruction is executed properly.

5-6

TESTS 32-37 test read/write functions of DMCII IBUS* registers 0 to II.
TESTS 40-50 test read/write functions of DMCII IBUS registers 0 to 7.
TEST 51 tests the read/write function of the DMCII Branch Register.
TESTS 52 and 53 test read/write functions of the DMCII Scratch pad registers 0 to 15.
TESTS 54-57 test the capability of the DMCII to interrupt vectors XXO and XX4, and verify that the
DMCII will only interrupt at its designated priority level.
TESTS 60-62 test the capability of the DMCII to perform NPR/DATO, NPR/DATI, and
NPR/DA TOB transactions.
TESTS 63 and 64 test the extended memory addressing capability of the DMCII by performing
NPR/DATO and NPR/DATI using BA bits 16 and 17.
TESTS 65 and 66 test the capability of the DMCII to report a non-existent memory error by performing an NPR/DATO and NPR/DATI to a non-existent memory location.
TEST 67 is an NPR test using DA TO to NPR a binary count of 0-377.
TESTS 70-73 test read/write functions and addressing of DMCII internal Main Memory and MAR.
TESTS 74-134 test each function of the ALU.
TEST 135 tests the program clock bit in the DMCII Miscellaneous Register (IBUS* Register II).
TEST 136 tests DMCII 's capability to force a power fail and verify that the CPU will trap to location
24.
TEST 137 is a DMCII microprocessor noise test, performed by writing Is and Os in IBUS* Register,
IBUS Register, Scratchpad, Main Memory, etc. and reading them back.
NOTE
CZDMC test 136 asserts AC LO on the UNIBUS to
test the capability of the DMCII to force a power
fail recovery in the system. On PDP-II/40, PDP11/45, PDP-II/60, and PDP-II/70 types ofprocessors, if the bootstrap module has the power-on boot
enabled, the program control is seized by the bootstrap ROM program and diagnostics will not run
successfully. The reason for this is that on the aforementioned PDP-lIs, the AC LO asserted by the
D M C II causes the CPU to assert DC LO on the
UNIBUS, which causes the bootstrap ROM to execute a power-on boot if it is enabled. The POWERON BOOT ENABLE switch on the bootstrap module (switch 2 - SW2 - on the M9301-XX module)
must be set to OFF.

5-7

5.5.2 CZDME DMCll Line Unit Tests
CZDME loads microinstructions into SEL6 and single steps the microprocessor to check the following
functions of the line unit.
•

Read/write functions of the Line Unit Register

•

Line Unit Clock

•

Transmitter and Out Data Silo

•

DOCMP specific transmitter functions

•

Receiver logic and DDCMP specific functions

•

CRC Operation on transmit and receive

•

Half-Duplex Test

•

DDCMP Cable Data Test

5.5.3 DZDMF DMCll Bit Stuff Line Unit Tests
DZDMF loads microinstructions into SEL6 and single steps the microprocessor to check out the
following functions of the line unit.
•

Line unit registers read/write tests

•

Out Data Silo and Bit Stuff Protocol specific transmitter function tests

•

In Data Silo and Bit Stuff Protocol specific receiver function tests

•

CRC Operation and Bit Stuff Cable Data Test

5.5.4 CZDMG DMCll CROM and Jump Test
CZDMG:
•

Verifies the contents of the CRaMs by comparing each CRaM location with a copy of the
correct microcode imbedded in the diagnostic.

•

Verifies code for both the DMCII-AR and AL versions.

•

Has facilities for supporting only one copy of microcode for each microprocessor type (AR
and AL).

•

Identifies the expected version of microcode by listing the chip part numbers at the respective revision level.

Comparison errors are reported if a defective ROM is encountered or if the diagnostic is run on a
wrong revision of microcode. All variations of the Jump microinstruction are also tested by loading
microinstructions into SEL6 and single stepping the microprocessor.
The following list is a summary of the tests performed (test numbers in octal):
TEST 1 types, on the console, the part numbers of the CRaMs which are supported by this revision.

5-8

TEST 2 is run only on a DMCII (DMC with writtable control store) to load the CRAM with the
DDCMP microcode.
TEST 3 tests the DMCII Branch Register right shift.
TEST 4 checks each ROM location and compares it to a software copy of the microcode. Jump
Immediate microinstructions are also tested.
TESTS 5-22 test Jump instructions by loading the microinstructions into SEL6 and single-stepping the
microprocessor.

5.5.5 DZDMH DMCll Free-Running Tests
The DMCII microprocessor and line unit are checked out in freerunning mode. This test is the most
comprehensive check of the DMCII. All error reporting features and interrupt-driven transmit and
receive data are checked.
The DZDMH diagnostic:
•

Is the first diagnostic in the sequence to turn on the DMCII RUN bit and execute CRaM
code.

•

Performs a good functional check of most of the DMCII capabilities.

•

Runs in loopback mode and may be run with or without a turnaround connector.

Note that when DZDMH is used with an M8202 line unit, it is assumed that a turnaround connector is
installed. Errors are reported if no turnaround connector is installed.
If a turnaround connector is installed, the following data rates are used with respective line units:

DMCII-DA/FA - M8201 - 10K bps
DMCII-MA - M8202-YA - 1M bps
DMCII-MD - M8202-YD - 56K bps
For M8202 type line units, the data is transferred from transmitter to receiver at full integral modem
speed. This transfer performs a good check of the DMC 11 's capability to talk to itself at full speed.
For M8201 type line unit, the maintenance clock speed of 10K bps mayor may not be near normal
operating speed; however, use of the H325 or H 3250 turnaround connector allows testing of the level
converters and cables.
Running in local loop mode establishes a confidence level from which expansion to interprocessor
testing may begin.
The following list is a summary of the tests performed.
TEST 1 runs DMC 11 microcode to transmit a message and then receive and check the message using
Line U nit Loop Mode.
TEST 2 is an overrun test which sends a message with no receive buffer available; it verifies that an
overrun error occurs.

5-9

TEST 3 is a lost data test which sends a message of greater length than the receive buffer; it verifies that
a lost data error occurs.
TEST 4 is a transmit non-existent memory test which loads a transmit BA that will time out; it verifies
that a non-existent memory error occurs.
TEST 5 is a receive non-existent memory test which loads a receive BA that will time out; it verifies
that a non-existent memory error occurs.
TEST 6 is a processor error test which does a BASE I transfer request after a BASE I has been set up; it
verifies that a processor error occurs.
TEST 7 is a processor error test which does an RQI with an illegal 10 code; it verifies that a processor
error occurs.
TEST 10 is a half-duplex test which sets half-duplex and LU LOOP, sends a message, and verifies that
none are done.
TEST II is a resume test which sends and receives a buffer and shuts down the DMC. A MASTER
CLEAR is then issued and a BASE I command with the RESUME bit set is given, another buffer is
sent and received, and data is checked.
TEST 12 is a data test (interrupt driven exerciser) which repeatedly queues up to seven receive buffers
and seven transmit buffers and checks data when all seven buffers are received. Transmit counts range
from 2 to 104. Data is a binary count pattern. The resume function is checked in this test. Test 12 uses
the turnaround connector if it is present; otherwise, the LU LOOP bit is set.

5.5.6 DZDMO - DMCl1 Overlay for Interprocessor Test Program (ITEP)
This test is used to isolate various interconnect problems between systems. Through a methodical
series of tests, failures are identified in level converters, cables and connections, modems, lines between
modems, and modem incompatibilities.
ITEP has been useful in identifying new or modified software problems. In this role, ITEP is used to
isolate the hardware from the system software. Typically, if ITEP runs, the system software should
run. ITEP provides a controlled environment for test purposes often unavailable in operating systems.
ITEP can be used for loop testing, providing the ability to incrementally test larger (or smaller) segments of the communications link. For instance, if a failure occurs when running in Modem Analog
Loop Mode rather than in Cable Loop Mode (with an H325 connector), the probability of a modem or
modem interface fault is increased.
ITEP is more of a confidence test than a true diagnostic, and provides a GO INO-GO indication of the
integrity of the communications link. ITEP is often used for installation acceptance, as well as confirmation of a corrective action.
An ITEP feature not provided in any of the stand-alone diagnostics is the capability of checking out
the REMOTE LOAD DETECT (RLD). The DMCII Overlay for Interprocessor Test program is
designed to verify the proper operation of a complete communications link from one PDP-II system
to another or to a communication test center. The program must be used in conjunction with the
Interprocessor Test Monitor program (DZITA) on a PDP-II system with a DLII interface. Two tests
for the D MC II are selectable by the parameter locations provided in ITEP.
TEST I is a link test which provides a GO/NO-GO test (a confidence check) on the communications
lmk (could be either half-duplex or full-duplex).

5-10

TEST 2 is a bootstrap test which checks the ability of a DMCII to boot another DMCll using
Maintenance Operation (MOP) messages. The bootstrap test requires an M9301-YJ (UNIBUS terminator with bootstrap) or equivalent boot module at one station.
The RLD feature of the DMCII is checked out; the host sends an Enter MOP Message to a remote
station to initialize the entire system and cause program control to be transferred to a Boot ROM
program (such as the one contained in an M9301-Y J). The Boot RO M program then requests a
program (or in true on-line application, a secondary Boot program) to be down-line loaded and eventually execute that program.
Only the down-line load feature of the DMCll can be checked; a remote station sends a program
REQUEST MOP MESSAGE, and the Host with its DMCll running ITEP will down-line load a
program to the remote station.
1.

NOTE
Refer to Appendix F for detailed operating
procedures of the Bootstrap testing under the
ITEP program.

Refer to Appendix H for detailed operating
procedures of the link test, ITEP program.

Refer to the diagnostic listings for detailed operating procedures of CZDMC, CZDME,
DZDMF, CZDMG, and DZDMH diagnostics. A copy of the operating procedures for
the DZDMH is included in Appendix I for
ease of reference.

5.5.7 : DEC/XII DMCII Module
The DEC/XII DMCII module, DMCA, is designed to exercise up to and including four consecutively addressed DMC 11 synchronous interfaces. One pass of the DMCA module consists of
transmitting and receiving seven buffers of 100 characters, 100 times for each selected device.
It is recommended that bit 0 of the DMCA switch register 1 (SR 1) be set to 1 and that a test connector
be installed (H325 or H3250 for M8201 line units; 12-12528 for M8202s) when running DEC/XII (as
indicated in the checkout procedures in Chapter 2).

I nstalling the test connector and setting bit 0 of SR 1 allows the D MCA to run in external loopback
mode and therefore generates more activity on the UNIBUS.
External Ioopback mode for:
•

M8201 is run at 10K bps

•

M8202-Y A is run at 1M bps

•

M8202-YD is run at 56K bps

5.5.8 Soft Error Reports Under DEC/XII
Soft errors indicate errors which occurred causing a message retransmission. These errors are not
reported to the PDP-II unless they exceed a threshold of seven on any given message. A cumulative
count of soft errors is kept in DMCll RAM memory. The RAM memory is written to PDP-II
memory (beginning at the assigned base address) whenever a fatal DMC error occurs.

5-11

DEC/XII forces a fatal procedure error on the DMC after each pass. The reason for this is to force a
Base Table update, allowing the DEC/XII module to check the cumulative error counters.
The soft error report may be used in the isolation of certain DMC 11 failures from UNIBUS loading or
latency problems.
The DMC has no Data Late bit or capabilities for detecting the fact that it did not obtain BUS
mastership in time to service the synchronous line. The DMC sees such a condition as an error in the
synchronous data stream (a BCC error) and the DDCMP causes the message to be retransmitted. This
occurrence causes incrementation of the cumulative error counters in DMCII RAM memory.
A process of elimination must be used to determine whether soft errors (BCC) are caused by BUS
latency or possible failing DMC 11 hardware.
Typically, the DMCII should show no errors when running in a local loopback mode. This is normallya noise-free circuit. Therefore, any soft error reports should be examined and the cause isolated.
If soft errors are reported while running a DMC on a fully loaded system (other devices being exercised
simultaneously), they may be due to BUS latency. This may be verified by running only the DMC
DEC/XII module with only one DMC enabled. If the soft errors cease, a latency condition is indicated.

If soft errors persist while running only the DMC DEC/X II module, the DMC device diagnostics
should be run. The problem could be a faulty DMC II or cable.
SR I (bit 0) may be used in the isolation process. If bit 0 is set, DEC/X II does not set line unit
loopback and uses an external turnaround. By running with bit 0 clear, a TTL loopback is performed,
eliminating the possiblity of the cable/turnaround conn'ector being faulty.
With M8201 line units, bit 0 clear eliminates the EIA level converters. The bit rate is 20K bps.
With M 8202 line units, bit 0 clear eliminates the integral modem. The bit rate is 10K bps.
5.5.9 Examination of DMCll Internal Components
Following are some procedure examples for examining DMC II memory and Scratchpad registers.
Example 1: Examine DMCII memory
Procedures

Comments,

Load 0 SELO

;To clear Run bit and stop the
;mlcroprocessor

Load 01 OXXX to SEL6

;Microinstruction LDMAR IMM,OPR
;is loaded into SEL6 where XXX is an
;eight bit memory address which is
;loaded into MAR

Load 1400 to SELO

;Set ROM In and STEP P bits

Load 055224 to SEL6

;Load microinstruction OUT* MAR, SELB, PORTI, INMAR
to SEL6 to read memory content pointed to by MAR to SEL4.
MAR is incremented.

Load 1400 to SELO

5-12

Examine SEtA low byte
for memory content

;Low byte of SEL4 contains content of memory location under
examination.

Example 1 (Cont)
7.

Go to Step 5. for examination of consecutive
memory locations
NOTE
Refer to the DMCll Base Table layout in Chapter 3
for D M C 11 main memory assignments.

Example 2: Examine DMC 11 Scratch pad registers
J?rocedures

Comments

Load SELO with 0

;To clear RUN bit

Load SEL6 with 0606XX

;SEL 6 is loaded with microinstructions. BR, SELA, SPX where
XX is 0-17, Scratchpad Register content of SP is loaded into the
Branch Register.

Load SELO with· 1400

;Set ROMIN and single step the microprocessor.

Load SEL6 with 061224

;Microinstruction OUT BR, SELB, PORTI where content of
SPX (from BR) is loaded into SEL4 low byte.

Examine BSEL4 for content
ofSPX

;Low byte of SEL 4 contains contents of Scratchpad X.

5.6 POSSIBLE OVERLOADING OF MAINTENENANCE CLOCK SIGNAL
During the fault isolation process, it may become necessary to use a serial line monitoring device. Such
a device is often used in verification of transmit/receive data at a point between the modem and the
D MC 11 line unit.
In some cases, the additional load of the monitor on the TRANSMIT SIG ELEMENT TIMING
signal (pin 24) may cause data errors or a complete failure to occur. These conditions are due to
overloading and signal degradation which usually happens when attempting to use an H325 connector
or a null modem with the monitor. The problem may be alleviated by soldering a wire jumper across
R45 (a 75 ohm resistor in series with the clock driver) on the M8201 module. The jumper must be
removed when testing is complete.
NOTE
The DMCll clock output is not normally used as a
clock source except for diagnostic purposes. However, some applications may require use of this clock
source and, as such, could requir.e a jumper across
R45 for reliable operation.
5.7 DDCMPMESSAGEFORMAT FOR DMCll
Table 5-2 reflects the various DDCMP messages as they appear on the serial link. This chart is useful
in data analysis with the use of a serial link analyzer.

5-13

Table 5-2 DDCMP Message Decode
for DMCII-AR & AL

Type of Message

Code

Oass

Count
Bits 7-0

Flag
Count
2 Bits Bit 13-8

Start Message

00000101
JJ 5

a 6

00000110

1 000000
C 0

Acknowledgement

Bits
Hex
ASCII
Bits
Hex
ASCII
Bits

1 000000

Start Acknowledgement

ENQ

ACK

00000101
0 5

00000111
0 7

Response

Sequence

Address Point
To Point

00000000

00000000
0 0

00000001
0 1

o 0

NUL

SOH

00000000
0 0

00000000
a 0

00000001
0 1

NUL
No. Last Good
Msg. Rcvd.

NUL

SOH

00000000

00000001

ENQ

BEL

00000101

00000001

0 5

0 1

C 0

0 0

0 1

ENQ

SOH
No. of Char.

Data Message

Hex
ASCII
Bits

NUL
No. Msg.
Sent

00000001

8 1
SOH

Negative Acknowledgement BCC
Header Error
Negative Acknowledgemen t BCC
Data Error
Negative Acknowledgement Buffer Unavailable
Negative Acknowledgement Receiver Overrun
Negative Acknowledgement Message Too Long
Negative Acknowledgement Header
Format Error

Hex
ASCII
Bits
Hex
ASCII
Bits
Hex
ASCII
Bits
Hex.
ASCII
Bits
Hex
ASCII
Bits
Hex
ASCII
Bits
Hex
ASCII

10000001

00000101
0 5

"
"
00000010
0 2

ENQ

STX

00000101
0 5

00000010
0 2

ENQ

STX

00000101
0 5

00000010
0 2

ENQ

STX

00000101
0 5

00000010
0 2

ENQ

STX

00000101
0 5

00000010
0 2

ENQ

STX

00000101
0 5

00000011
0 2

ENQ

STX

Q No. of Char.

S
S

Q"
Q"

1 000001
C 1

1 000010

SOH

00000000
0 0

00000001
0 I

C 8
H

NUL

SOH

1 001001

C 9
I

"
"
"

00000000
0 0

00000001
0 1

1 001000

1 010000
D 0
p

"
"
00000000
0 0
NUL

C 2
B

SOH

"
"
"
"
"
"
"
"
"
"

1 010001
D 1
Q

"
"
"
"

SOH

00000001
0 1

NUL

SOH

00000000
0 0

00000001
0 1

NUL

SOH

00000000
0 0

00000001
0 I

NUL

SOH

00000000
0 0

00000001
0 1

NUL

SOH

Table 5-2 DDCMP Message Decode
for DMCII-AR & AL (Cont)
Address Point
to Point

Type of Message

Code

Class

Count
Bits 7-0

Flag
Count
2 Bits Bit 13-8

Response

Sequence

Reply Message

Bits

00000101

00000011

00000000

No. Last
Msg. Sent

00000001

Hex
ASCII
Bits

0 5

0 3

C 0

0 0

0 1

ENQ

ETX

SOH

00000101

00000010

NUL
No. Last Good
Msg. Rcvd.

00000000

00000001

0 5

0 2

0 I

STX
No. of Char.

C 3
C
No. of Char.

0 0

ENQ

"
"

Negative AcknowIedgement Reply
Response
Maintenance Message

Hex
ASCII
Bits
Hex
ASCII

10010000
9 0
DLE

1 00000000

1 000011

"
"
00000000
0 0
NUL

NUL

SOH

00000000
0 0

00000001
0 1

NUL

SOH

APPENDIX A
PDP-II MEMORY ORGANIZATION
AND ADDRESSING CONVENTIONS

The PDP-II memory is organized in 16-bit words consisting of two 8-bit bytes. Each byte is addressable and has its own address location; low bytes are even numbered and high bytes are odd numbered.
Words are addressed at even numbered locations only and the high (odd) byte of the word is automatically included to provide a 16-bit word. Consecutive words are therefore found in even numbered
addresses. A byte operation addresses an odd or even location to select an 8-bit byte.
The UNIBUS address word contains 18 bits identified as A(l7:00). Eighteen bits provide the capability
of addressing 256K bytes of memory locations, each of which is an 8-bit byte. This also represents
128K 16-bit words. In this discussion, the multipler K equals 1024 so that 256K represents 262,144
locations and 128K represents 131,072 locations. The maximum memory size can be used only by a
PO P-ll processor with a memory management unit that utilizes all 18 address bits. Without this unit,
the processor provides 16 address bits which limits the maximum memory size to 64K (65,536) bytes or
32K (32,768) words.
Figure A-I shows the organization for the maximum memory size of 256K bytes. In the binary system,
18 bits can specify 2 18 or 262,144 (256K) locations. The octal numbering system is used to'designate
the address. This provides convenience in converting the address to the binary system that the processor uses as shown below.
The highest 4K word address (8K bytes) locations (760000-777777) are reserved for internal general
registers and peripheral devices. As a result, programmable memory locations cannot be assigned in
this area; therefore, the user has 248K bytes or 124K words to program.
A PO P-ll processor without the memory management unit provides 16 address bits that specify 216 or
65,536 (64K)'locations (Figure A-2). The maximum memory size is 65,536 (64K) bytes or 32,768 (32K)
words. Logic in the processor forces address bits A(l7: 16) to 1s if bits A(l5: 13) are all 1s when the
processor is master allowing address generation in the reserved area with only 16-bit control.

17
0

16
0
1

15
1

14
0

13
0
1

12
1

11
1

10
1
7

9
1

8
1

7
1
6

6
0

5
0

4
0
0

3
0

2
0

1
1
2

ADDRESS BIT

BINARY
OCTAL
MK·0813

Bit 13 becomes a 1 first at octal 160000 which is decimal 57,344. This is the beginning of the last 8 K
bytes of the 64K byte memory. The processor converts locations 160000-177777 to 760000777777 which relocates these last 8K bytes (4K words) to the highest locations accessible by the bus.
These are the locations that are reserved for internal general register and peripheral device addresses;
therefore, the user has 57,344 (56K) bytes or 28,672 (28K) words to program.

A-I

08 07

16 BIT DATA WORD
HIGH BYTE

LOW BYTE

000001

000000

USER ADDRESS SPACE
AVAILABLE USING 18
ADDR ESS BITS ON
PDP-11 PROCESSOR
WITH MEMORY
MANAGEMENT OPTION.
INCLUDES 248K(253,952)
BYTES OR 124K(126,976)
WORDS.

~-------+--------~

000003

000002

757777
760001

757776
~------~--------~

760000
HIGHEST 8K(8192)
BYTES OR 4K(4096)
WORDS RESERVED FOR
DEVICE REGISTER
ADDRESSES.

*777777

777776

LAST ADDRESS IS BYTE NUMBER 262,14310
*MAXIMUM SIZE WITH 18 ADDRESS BITS IS 256K(262,144) BYTES OR 128K(131,072) WORD
MK-OS:

Figure A-I

Memory Organization for Maximum Size Using 18 Address Bits

A-2

08 07

16 BIT DATA WORD
HIGH BYTE

LOW BYTE

000001

000000
~------~------~

000003

000002

157777

USER ADDRESS SPACE
AVAILABLE USING 16
ADDRESS BITS ON
PDP-11 PROCESSOR
WITHOUT MEMORY
MANAGEMENT OPTION.
INCLUDES 56K (57,344)
BYTES OR 28K (28,672)
WORDS.

157776
~------~------~

160001

160000

*177777

177776

ADDRESSES 160000177777 ARE CONVERTED
TO 760000-777777 BY
THE PROCESSOR. THUS,
. THEY BECOME THE
HIGHEST 8K (8192) BYTES
OR 4K(4096) WORDS
RESERVED FOR DEVICE
REGISTER ADDRESSES.

LAST ADDRESS IS BYTE NUMBER 65, 535 10
*MAXIMUM SIZE WITH 16 ADDRESS BITS IS 64K (65,536) BYTES OR 32K(32,768) WORDS.
MK-0822

Figure A-2

Memory Organization for Maximum Size Using 16 Address Bits

A-3

Memory capacities of 56K bytes (28K words) or less do not have the problem of interference with the
reserved area because designations less than 160000 do not have a binary 1 in bit A13. No addresses
are converted and there is no possibility of physical memory locations interfering with the reserved
space.
PDP-II core memories are available in 4K word or 8K byte increments. The highest locations of
various size core memories are shown below.

Highest Location
( octal)

Memory Size
K bytes
K words
4

8
12
16
20
24
28

017777
037777
057777
077777
117777
137777
157777

8
16
24

32
40
48
56

A-4

APPENDIX B
LOGIC SYMBOLOGY

B.1 INTRODUCTION
The logic symbology used in the PDP-II manuals and engineering logic is generally consistent with
Graphic Symbols for Logic Diagrams (MIL-STD-806B). Certain symbols are modified by DIGITAL to
allow direct reading of logic functions in detailed logic diagrams that show explicit electrical connections between logic elements. The modifications and other conventions are explained in the following paragraphs.
B.2 UNIBUS SIGNAL LEVELS
The UNIBUS has 56 dedicated signal lines. Negative logic is used for 51 lines and the remaining 5
lines, BG(7:4) and NPG, use positive logic.
The definitions of positive and negative logic are:
Positive Logic
Signal asserted: high = logical 1 = + 3V
Signal at rest: low
= logical 0 = OV
Negative Logic
Signal asserted: low
Signal at rest: high

= logical 1 = OV

= logicalO = + 3V

In the logi-c diagrams, the signal name mnemonic is followed by an H or L to indicate the asserted state
(logical 1) of the signal to be high (+ 3V) or low (ground or OV). Using this convention, a grant line is
called BUS BG2 H and a data line is called BUS D12 L.
B.3 EQUIVA-LENT GATE SYMBOLS
In the detailed logic diagrams, the gate symbols show the active state of the gate output. A small circle
at the output shows that the active state is low (L). The absence of a small circle at the output shows
that the active state is high (H).
A large number of NAND and NOR gates are used in DIGITAL logic. The symbols for the NAND
and NOR gates show an active low output. Frequently, an active high output is required from a
NAND or NOR gate. In this case, a logically equivalent symbol is used to retain the concept of direct
reading of logic functions.
For the NAND gate, the logically equivalent negated-input OR gate is used to show the active high
output. For the NOR gate, the logically equivalent negated-input AND gate is used to show the active
high output. These gate symbols and associated truth tables are shown in Figure B-1.

B-1

VOLTAGE
TRUTH TABLE
A
B

)-c

NAND
C =AB

VOLTAGE
TRUTH TABLE
A
C
B

L ACTIVE

NEGATED INPUT OR
C=A+B

VOTAGE
TRUTH TABLE
A

D-c
NOR
C = A + B

H
L

L
H

H
H

ACTIVE

VOLTAGE
TRUTH TABLE

ACTIVE

:=J

)

NEGATED INPUT AND
C =AS

H ACTIVE

MK-0823

Figure B-1

B.4

Logically Equivalent Gates

4-0UTPUT TERMINAL FLIP-FLOP SYMBOLOGY

The 7474 D-type flip-flops in the engineering logic diagrams are shown as 4-output terminal devices.
Most other users (and the IC manufacturers) show them as 2-output terminal devices, which represents
only the physical output connections. Both the 4-output symbol and the 2-output symbol are shown in
Figure B-2.
The flip-flop is a 2-state device with a pair of complementary outputs. The 4-output terminal symbology defines the polarity of the outputs for each state of the flip-flop. In this discussion, the states are
set and reset which are obtained by clocking the flip-flop with its D input high or low, respectively.
These states can also be obtained by enabling the PRESET and CLEAR inputs which override the
clock. In Chapter 4 of this manual (as in most other DIGITAL manuals) the distinction between
set/reset and preset/clear is not maintained. A flip-flop is said to be either set or cleared, regardless of
the method used to obtain the state.
In the 4-output symbol (Figure B-2), the flip-flop name is NRA and the output signal designations
contain the name, state (asserted or not asserted), and polarity (high or logical 1) or L (low or logical
0); that is, assuming positive logic conventions in which H = 1 = + 3V and L = 0 = OV. For example,
NRA (0) L means that this output is low when the flip-flop is reset (cleared). Usually, the PRESET
input is placed near the I-output because it directly sets the flip-flops; the CLEAR input is placed near
the O-output because it directly resets the flip-flop. Physically, nothing has changed; flip-flop operation
is still the same and there are two electrical outputs (pin 9 for the I-output and pin 8 for the O-output).
The 4-terminal symbol and signal designators allow direct reading of logic functions in detailed logic
diagrams that show explicit electrical connections between the flip-flop outputs and other logic elements. The correct output polarity; pin number, and flip-flop state are read at a glance. This is not
possible with the 2-terminal symbol without mental translations. A comparative example is shown in
Figure B-3.

B-2

10
PRESET

NRA

NRA (1) H

PRESET
9
D
11 - - - - - - NRA (1)

NRA (1) L

NRA

7474

9
11

0
C

NRA(O) L
11

NRA(O) H

0 1 - - - - NRA (0)

CLEAR

4 OUTPUT TERMINAL SYMBOL (DEC USAGE)

2 OUTPUT TERMINAL SYMBOL (OTHER USAGE)
MK-0834

Figure B-2

Flip-Flop Logic Symbology

.---A

~-A

1 9

NRA

NRA
~--B

o8
'\------- B

NRA(O) H

'---- C

l---C

FOUR OUTPUT TERMINAL DESIGNATION

TWO OUTPUT TERMINAL DESIGNATION

MK-0824

Figure B-3

Electrical Connections to Outputs of 2-Terminal and 4-Terminal Flip-Flops

B-3

8.5

REDEFINED 4-0UTPUT TERMINAL FLIP-FLOPS

Logically speaking, a redefined flip-flop is asserted (set) when clocked with a low signal on its D-input.
Graphically, this is accomplished by reversing the output pin assignments and placing a circle on the
D-input. The PRESET and CLEAR input pin designations are interchanged because their logical
functions are reversed: PRESET directly resets the flip-flop, and CLEAR directly sets the flip-flop.
Physically, the flip-flop operation is still the same. Redefinition is used to retain consistency in graphically representing the asserted state of a flip-flop in a detailed logic diagram; specifically, to produce
the asserted state with a low signal on the D-input.
Pin designations and outputs for a standard 4-output terminal flip-flop and a redefined 4-output
terminal flip-flop are shown in Figure B-4.

10
12

PRESET

NRA (1) H

ASSERTED
(SET)
D=1

NON ASSERTED
(RESET)
D=O

NRA (1) L

NRA

9
11

NRA(O) L
NRA(O) H

CLEAR
13
STANDARD FLIP FLOP
NRA (1) = ASSERTED STATE (D = 1)
NRA (0) = NON ASSERTED STATE (D

13
12

PRESET

NRA (1) H

ASSERTED
(SET)
D. =0

= 0)

NON ASSERTED
(RESET)
D
1

NRA(1) L

NRA

----tC

NRA(O) L
NRA(O) H

CLEAR
10
REDEFINED FLIP FLOP
NRA (1) = ASSERTED STATE (D = 0)
NRA (0)

= NON ASSERTED STATE (D = 1)
MK·0825

Figure B-4

Standard and Redefined 4-Terminal Flip-Flops

B-4

APPENDIX C
SYNCHRONOUS SERIAL DATA HANDLING

This appendix contains a discussion of the principles of synchronous serial data transmission and
reception, followed by descriptions of the synchronous receivers and transmitters used in the DVII
Synchronous Multiplexer.
C.I BINARY DATA TRANSFER METHODS
Bits of binary data are commonly transferred between digital machines by changes in current or voltage. Data may be transferred in serial over a single line, or in parallel over several lines at once. The
transfers may be synchronous, in which the exact departure or arrival time of each bit of information is
predictable, or they may be asynchronous, in which case the data may be transferred at non-uniform
rates. Aspects and applications of these data transfer modes will now be discussed.
C.I.I Parallel vs Serial
In parallel transmission, each bit of the set of bits that represent a character has its own wire. An
additional wire called the "strobe" or "clock" lead notifies the receiver unit that all of the bits are
present on their respective wires so that the voltages on the wires can be sampled. Figure C-I schematically depicts the parallel transfer of the 8-bit character, 1100000 1.

+3V

OV
+3V

+3V

+:n

STROBE

MK-0814

Figure C-I

Parallel Data Transfer

C-l

In serial transmission, the bits that represent a character are sent down a single wire one after the
other.
Computers and other high-speed digital machines generally operate on parallel data, so data is transferred in parallel between these devices wherever they are in close physical proximity. However, as the
distance between the. devices increases, the multiple wires not only become more costly, but the complexity of the line drivers and receivers increases, due to the increased difficulty of properly driving and
receiving signals on long wires.
Serial transmission is generally used where the cost of the communication medium (wires) is sufficiently high that a relatively complex transmitter/receiver system is justified. The more complex
system will serialize the bits that represent the character, send them over a single line, and reassemble
them in parallel form at the reception end.
Conversion from parallel to serial and from serial to parallel is typi"cally done with shift registers. In
most data communications applications, serial transmission is preferable to parallel transmission.
C.l.2 Asynchronous vs Synchronous·
Because of the mechanism design in early serial teleprinters, and to facilitate fail-safe operation, serial
teleprinter systems have adopted the convention that an idle line (no data being sent) is one in which
current is flowing. Data transmission occurs when the current in the line is interrupted in a specified
fashion. By convention,the idle (current flowing) state is called the I state or MARK condition, and
the lack-of-current state is called the 0 state or SPACE condition. To start the receiving teleprinter
mechanism, the line is brought to the 0 state for I-bit time. (This is called the START bit.) For the next
eight successive bit times, the line is conditioned to a 1 state or 0 state, as required, to represent the
character being sent. To allow the receiving teleprinter mechanism to coast back to a known position
in time for the beginning (START bit) of the next character, one or more bit times of 1 state (idle) are
sent. This period is called the STOP bit interval.
Except for the requirement that the line be idle for at least the STOP bit interval, the transmission of
the next character can begin at any time. The lack of a continuous synchronous agreement between the
transmitter and the receiver (specifically, the lack of a clocking signal within or accompanying the data
channel) causes this type of transmission to be called asynchronous, literally, without synchronization.
A typical asynchronous receiver contains an interval clock and a system for detecting the I-to-O transition that indicates the beginning of a start bit. The internal clock delays one-half bit time, checks to see
that the start bit condition is still on the line and then makes eight successive samples, I-bit t~me apart,
to determine the eight bits being sent.
Although modern asynchronous receivers do not require a stop interval for mechanism coasting purposes, they do require a stop interval to guarantee that each character will begin with a I-to-O transition, even if the preceding character was all zero bits. This requirement for a I-to-O transition, to
indicate the beginning of each character, causes a complete character to require 10 bit times, only 8 of
which contain real data. The other 20 percent of the line time is used strictly for timing purposes. The
asynchronous character format is shown in Figure C-2.
Synchronous communications require either a separate rate clock lead from the transmission point to
the reception point (in addition to the data lead) or a modem that includes the clock information with
the data. In the case of a modem, the clock is recovered from the signal sidebands by the modem and is
brought out of the modem as a separate lead. This indicates to the data communications hardware
(typically a computer interface) the appropriate instant to sample the data on the received data lead.

C-2

The inclusion of the clock in the data stream or in a separate lead keeps the transmitter and receiver in
sync, hence the term synchronous communication. Synchronous character format is shown in Figure
C-3.

DATA

(LlNE1)

(LINE 0)

STOP BITS
DATA BITS
START BIT
MK-0832

Figure C-2

Asynchronous Character Format

1 BITTIME

MODEM CLOCK

o
DATA

LSB

:+I

.....- ........ 0

I
SYNC CHARACTER -

o
I

...J....
1.t---DATA CHARACTER----"':

I
MK-0833

Figure C-3

Synchronous Character Format

C.I.3 Synchronizing at the Receiver
Since start and stop bits are not required in synchronous communications, all bits are used to transmit
data; therefore, there is not the 20 percent waste characteristic of asynchronous communication. However, the character framing information provided by the start and stop bits is absent, so another
inethod of determining which groups of bits constitute a character must be provided.
In Figure C-4, bits 1-8 might be one character and bits 9-13 part of another character, or bit 1 may be
part of one character, bits 2-9 part of a second character, bits 10-13 part of a third charaGter, and so
on. The delimiting or framing of each actual character is accomplished by defining a sync character.
The sync character is usually chosen such that its bit arrangement is significantly different from that of
any of the regular characters being transmitted. Thus, when a sync character is preceded and followed
by regular characters, there is no possible successive pattern of bits that equal the bit patterns of the
sync character, except those eight bits that actually are the sync character.

C-3

MK-0826

Figure C-4

Serial Bit Stream

Typical synchronous receiver units are placed in a sync search mode by either hardware or software
whenever a transmission begins, or whenever a data dropout has occurred and the hardware or software determines that resynchronization is necessary.
Synchronization is accomplished by the hardware shifting eight bits into a shift register and comparing
those eight bits (as a parallel word) to the sync character which has been set in a register. If a match
occurs, the receiver begins shifting in bits and raising a "character available" flag every eight bits. If no
match is realized, the receiver shifts in a new bit from the line, shifts all bits recorded to date (thus
shifting the oldest bit off the end), and does a new parallel comparison to the sync character. The
process continues until the sync character is framed.
To decrease the probability that a receiver will synchronize on a bit combination that is not the
intended sync character but rather a combination of other characters, synchronous receivers are frequently arranged to synchronize on two successive sync characters.

C-4

APPENDIX D
DDCMP IN A NUI'SHELL

D.1 DDCMP
DDCMP (Digital Data Communications Message Protocol) was developed to provide full-duplex
message transfer over existing standard hardware.
D .1.1 Controlling Data Transfers
The DDCMP message format is shown in Figure 0-1. A single control chC,lracter is used in a DDCMP
message and is the first character in the message. Three control characters are provided in DDCMP to
differentiate between the three possible types of messages:
SOH - data message follows
ENQ - control message follows
OLE - bootstrap message follows
Note that the use of a fixed-length header and message size declaration obviates the requirement for
extensive message and header delimiter codes~

SOH

DATA
RESPONSE SEQUENCE ADDRESS CRC-1
CRC-2
COUNT FLAG
(ANY NUMBER OF 8-BIT
16 BITS
16 BITS
8 BITS
8 BITS
14 BITS 2 BITS 8 BITS
CHARACTERS UP TO 214)

MK-0827

Figure D-l

DDCMP Data Message Format

Figure D-2 shows a simple example of data exchange.
D.1.2 Error Checking and Recovery
DDCMP uses CRC-16 for detecting transmission errors. When an error occurs, DDCMP sends a
separate NAK message. DDCMP does not require an acknowledgement message for all data messages. The number in the response field of a normal. header or in either the special NAK or ACK
message specifies the sequence number of the last good message received. For example, if messages 4,
5, and 6 have been received since the last time an acknowledgement was sent and message 6 is bad, the
NAK message specifies number 5 which says "message 4 and 5 are good and 6 is bad." When DDCMP
operates in full-duplex mode, the line does not have to be turned around; the NAK is simply added to
the sequence of messages for the transmitter.

D-l

DMC#1

DMC #2

f1\ SENDS A STRT (START) MESSAGE WHICH

\.J MEANS: "I WANT TO BEGIN SENDING DATA

f2\ SENDS A STRT (START) MESSAGE WHICH
V

.. -- - -

TO YOU AND THE SEQUENCE NUMBER OF MY
FIRST MESSAGE WILL BE 1."

MEANS: "I WANT TO BEGIN SENDING DATA
TO YOU AND THE SEQUENCE NUMBER OF MY
FIRST MESSAGE WILL BE 1."

RECEIVES STRT MESSAGE.

t;\ SENDS A STACK (START ACKNOWLEDGE)

\J MESSAGE WHICH MEANS: "OK WITH ME."

CD
CD

RECEIVES STACk.

SENDS DATA MESSAGES WITH A RESPONSE FIELD
SET TO 0 AND THE SEQUENCE FIELD SET TO 1.
WHICH MEANS: "I AM LOOKING FOR YOUR
MESSAGE 1." OTHER MESSAGES MAY BE SENT
AT THIS TIME (I.E., MESSAGES 2, 3, ETC.)
WITHOUT WAITING. FOR A RESPONSE.

----------0
V

RECEIVES DATA MESSAGE 1 AND CHECKS IT FOR
SEQUENCE AND CRC ERRORS. IF THERE IS A
SEQUENCE ERROR, GO TO 12. IF THERE IS NO
ERROR, GO TO 9.

f8\ A CRC ERROR WAS DETECTED. COMPUTER B

v SENDS A NAK MESSAGE WITH THE RESPONSE

FIELD SET TO O. WHICH MEANS: "ALL MESSAGES
UP TO 0 (MODULO 256) HAVE BEEN ACCEPTED
AND MESSAGE 1 IS IN ERROR."

/
COMPUTER A RECEIVES NAK, RETRANSMITS.
MESSAGE 1 AND ANY OTHER MESSAGES SENT
SINCE (I.E., 2, 3, ETC.) IF ALREADY SENT.

@ RECEIVES ACK AND RELEASES MESSAGE 1.

-------.@
10 SENDS ACK RESPONSE OF 1 EITHER IN A

______
.---

@CONTINUES SENDING MESSAGES.

SEPARATE ACK MESSAGE OR IN THE RESPONSE
FIELD OF A DATA MESSAGE.

fi3\ DISCARD MESSAGE AND WAIT FOR PROPER

~VMESSAGE2.
TIMES our DUE TO L.,ACK OF RESPONSE
FOR MESSAGE 2. SENDS A REPLY FOR
MESSAGE 2.
- - -_______

f15\ SEND NACK RESPONSE OF 1 IN THE

RESPONSE FIELD.

@ RETRANSMITS MESSAGE 2 AND
FOLLOWING MESSAGES
MK-0866

Figure D-2

DDCMP Sample Handshaking Procedure

D-2

When a sequence error occurs in DDCMP, the receiving station does not respond to the message. The
transmitting station detects, from the response field of the messages it receives (or via timeout), that
the receiving station is still looking for a certain message and sends it again. For example, if the next
message the receiver expects to receive is 5, but receives 6 instead, the receiver will not change the
response field (which contains a 4) of its data messages. The receiver will say, "I accept all messages up
through message 4 and I'm still looking for message 5."

D .1.3 Character Coding
DDCMP uses ASCII control characters for SYN, SOH, ENQ and DLE: The remainder of the message, including the header, is transparent.
D.l.4 Data Transparency
DDCMP defines transparency by use of a count field in the header. The header is of fixed length. The
count in the header determines the length of the transparent information field, which can be 0 to
16,383 bytes long. To validate the header and count field, it is followed by a CRC-16 field; all header
characters are included in the CRC calculation. Once validated, the count is used to receive the data
and to locate the second CRC-16, which is calculated on the data field. Thus, character stuffing is
avoided.

D.l.5 Data Channel Utilization
DDCMP uses either full- or half-duplex circuits at optimum efficiency. In the full-duplex mode,
DDCMP operates as two dependent one-way channels, each containing its own data stream. The only
dependency is the acknowledgements which must be sent in the data stream in the opposite direction.
Separate ACK messages are unnecessary, reducing the control overhead. Acknowledgements are simply placed in the response field of the next message for the opposite direction. If several messages are
received correctly before the terminal is able to send a message, all of them can be acknowledged by
one response. Only when a transmission error occurs or when traffic in the opposite direction is light
(no data message to send) is it necessary to send a special NAK or ACK message, respectively.
In summary, DDCMP data channel utilization features include:
I.

The ability to run on full- or half-duplex data channel facilities.

Low control character overhead.

No character stuffing.

No separate ACKs when traffic is heavy; this saves on extra SYN characters and intermessage gaps.

Multiple acknowledgements (up to 255) with one ACK.

The ability to support point-to-point and multipoint lines.

D.2 PROTOCOL DESCRIPTION
DDCMP is a very general protocol; it can be used on synchronous or asynchronous, half- or fullduplex, serial or parallel, and point-to-point or multipoint systems. Most applications involving protocols are half- or full-duplex transmission in a serial synchronous mode; that operating-envitonment
will therefore be emphasized in this description.

D-3

The header is the most important part of the message, because it contains the message sequence
numbering information and the character count, the two most important features of DDCMP. Because of the importance of the header information, it merits its own CRe block check, indicated in
Figure D-3 as CRC 1. Messages that contain data, rather than just control information, have a second
section which contains any number of 8-bit characters (up to·a maximum of 16,363) and a second CRC
(indicated in Figure D-3 as CRC 2).
Before the message format is discussed in greater detail, the message sequencing system should be
explained because most of the header information is directly or indirectly related to the sequencing
operation.
.
In the DDCMP, any pair of stations that exchange messages with each other number those messages
sequentially starting with message number 1. Each successive data message is numbered using the next
number in sequence, modulo 256. Thus, a long sequence of messages would be numbered
1,2,3, ... 254,255,0,1, ... The numbering applies to each direction separately. For example, station A
might be sending its messages 6,7,8 to station B, while station B is sending its messages 5,6,7 to station
A. Thus, in a multipoint configuration where a control station is engaged in two-way communication
with 10 tributary stations, there are 20 different message number sequences involved - one sequence
for messages from each of the 10 tributaries to the control station and one sequence for messages from
the control station to each of the 10 tributaries.
Whenever a station transmits a message to another station, it assigns its next sequential message
number to that message and places that number in the sequence field of the message header. In addition to maintaining a counter for the sequentially numbered messages which it sends, the station also
maintains a counter of the message numbers received from the other station. It updates that counter
whenever a message is received with a message number exactly one higher than the previously received
message number. The contents of the received message counter are included in the response field of the
message being sent, to indicate to the other station the highest sequenced message that has been
received.

When a station receives a message containing an error, that station sends a negative acknowledge
(NAK) message back to the transmitting station. DDCMP does not require an acknowledgement for
each message, as the number in the response field of a normal header (or in either the special NAK or
positive acknowledgement message ACK) specifies the sequence number of the last good message
received. For example, if messages 4,5, and 6 have been received since the last time an acknowledgement was sent, but message 6 is bad, the NAK message specifies number 5 which says '"messages 4 and
5 are good and 6 is bad." When DDCMP operates in the full-duplex mode, the line does not have to be
turned around; the NAK is simply added to the messages for the transmitter.
When a station receives a message that is out of sequence, it does not respond to that message. The
transmitting station will detect this from the response field of the messages which it receives; if the
reply wait timer expires before the transmitting station receives an acknowledgement, the transmitting
station will send a REP message. The REP message contains the sequence number of the most recent
unacknowledged message sent to the distant station. If the receiving station has correctly received the
message referred to in the REP message (as well as the messages preceding it), it replies to the REP by
sending an ACK. If it has not received the message referred to in sequence, it sends a NAK containing
the number of the last message that it did receive correctly. The transmitting station will then retransmit all data messages after the message specified in the NAK.
The numbering system for DDCMP messages permits up to 255 unacknowledged messages outstanding, a useful feature when working on high delay circuits such as those using satellites.

D-4

RESPONSE SEQUENCE ADDRESS
CLASS COUNT FLAG
14 BITS 2 BITS
a BITS
a BITS
a BITS

ENQ
DLE

INFORMATION
ANY NUMBER
OF a-BIT
CHARACTERS

CRC 2
16 BITS

~--------------------~)

SOH-DATA MESSAGES
10000001
ENQ J ACKNOWLEDGEMENT
00000101
l NEGATIVE ACKNOWLEDGE 00000101-

REASONS:

CRC 1
16 BITS

CHARACTER COUNT
00000001000000
00000010---------

BCC HEADER ERROR
BCC DATA ERROR·
REP RESPONSE
BUFFER UNAVAILABLE
RECEIVER OVERRUN
MESSAGE TOO LONG
HEADER FORMAT ERROR

REPLY MESSAGE
START MESSAGE

00000101
00000101
START ACKNOWLEDGEMENT 00000101
10010000
MAINTENANCE MESSAGE

QS
QS
QS

RESP #
RESP #
RESP #

MESSAGE#
00000000
00000000

XXXXXXXX
ADDRESS
ADDRESS
ADDRESS

00000000
00000000
00000000
00000000

LSTM ESS #
00000000
00000000
00000000

ADDRESS
ADDRESS
ADDRESS
ADDRESS

000001
000010
000011
001000
001001
010000
010001

00000011000000
00000110000000
00000111000000
CHARACTER COUNT

QS
11
11
11

NOTES:
1. ONLY THE DATA MESSAGE AND THE MAINTENANCE MESSAGE HAVE CHARACTER COUNTS, SO
ONLY THESE MESSAGES HAVE THE INFORMATION AND CRC2 FIELDS SHOWN IN THE MESSAGE
FORMAT DIAGRAM ABOVE.
2. "RESP .#" REFERS TO RESPONSE NUMBER. THIS IS THE NUMBER OF THE LAST MESSAGE
RECEIVED CORRECTLY. WHEN USED IN A NEGATIVE ACKNOWLEDGE MESSAGE, IT IS ASSUMED
THAT THE NEXT HIGHER NUMBERED MESSAGE WAS NOT RECEIVED, WAS RECEIVED WITH
ERRORS, OR WAS UNACCEPTED FOR SOME OTHER REASON. SEE "REASONS."
3. "MESSAGE#" IS THE SEQUENTIALLY ASSIGNED NUMBER OF THIS MESSAGE. NUMBERS ARE
ASSIGNED BY THE TRA'NSMITTING STATION MODULO 256; I.E., MESSAGE 000 FOLLOWS 255.
4. "LSTMESS#" IS THE NUMBER OF THE LAST MESSAGE TRANSMITTED BY THE STATION. SEE THE
TEXT DISCUSSION OF REP MESSAGES,
5. " ADDRESS" IS THE ADDRESS OF THE TRIBUTARY STATION IN MULTIPOINT SYSTEMS AND IS
USED IN MESSAGES BOTH TO AND FROM THE TRIBUTARY. IN POINT TO POINT OPERATION, A
STATION SENDS THE ADDRESS "1" BUT IGNORES THE ADDRESS FIELD ON RECEPTION.
6. "Q" AND "S" REFER TO THE QUICK SYNC FLAG BIT AND THE SELECT BIT. SEE TEXT.
MK-0828

Figure D-3

DDCMP Message Format in Detail

D-5

D.3 MESSAGE FORMAT
With the above background, it is now time to explore the various' DDCMP message formats in full
detail, as shown in Figure D-3. The first character of the message is the class of message indicator,
represented in ASCII with even parity. There are three classes of messages: data, control, and maintenance. These are indicated by class of message indicators SOH, ENQ, and DLE respectively. The next
two characters of the message are broken into a 14-bit field and a 2-bit field. The 14-bit field is used in
data and maintenance messages to indicate the number of characters that will follow the header and
form the information part of the message. In control messages, the first 8 bits of the 14-bit field are
used to designate what type of control message it is; the last 6 bits are generally filled up with zeros.
The exception is in NAK messages where the last six bits are used to specify the reason for the NAK.
The 2-bit field contains the quick sync and select flags.
The quick sync flag is used to inform the receiving station that the message will be followed by sync
characters; the receiver may wish to set its associated synchronous receiver hardware into sync search
mode and sync strip mode. This will re-establish synchronization and syncs will be discarded until the
first cparacter of the next message arrives. The purpose of this is to permit the receiving station to
engage any hardware sync-stripping logic it might have and prevent it from filling its buffers with sync
characters. The select flag is used to indicate that this is the last message which the transmitting station
is going to transmit and that the addressed station is now permitted to begin transmitting. This flag is
useful in half-duplex or multipoint configurations, where transmitters need to get turned on and off.
The response field contains the number of the last message correctly received. This field is used in data
messages and in the positive and negative acknowledge types of control message. Its function should
be evident from the preceding discussion of sequence control.
The sequence field is used in data messages and in the REP type of control message. In a data message,
it contains the sequence number of the message as assigned by the transmitting station. In a REP
message, it is used as part of the question, "Have you received all messages up through message
number (specify) correctly?"
The address field is used to identify the tributary station in multipoint systems and is used in messages
both to and from the tributary. In point-to-point operation, a station sends address 1, but ignores the
address field on reception.
In addition to the positive and negative acknowledgement and REP types of control message, there are
also start and start acknowledge control messages. These are used to place the station which receives
them in a known state. In particular, they initialize the message counters, timers, and other counters.
The start acknowledge message indicates that this has been accomplished.
Figure D-3 also shows the maintenance me,ssage. This is typically a bootstrap message containing load
programs in the information field. A complete treatment of bootstrap messages and start up procedures is beyond the scope of this book.
NOTE
Refer to the DDCM P Specification 'Order (No. AAD599A-TC) for a complete detailed description of
DDCMP.

D-6

APPENDIX E
DDCMP BLOCK CHECK COMPUTATION

E.I

DDCMP ERROR DETECTION

Error detection is p.rovided in this protocol by block check bytes after each of the message headers and
message blocks. This block check consists of computing a 16-bit cyclic redundancy check using a
polynomial known as the CRC-16 polynomial and appending the check bits computed to each block.
This polynomial and scheme have been widely used in BiSync and other protocols.

E.2

THE CRC-16 POLYNOMIAL

The CRC-16 polynomial [X16 + XI5 + X2 + 1 = (X + 1) * (X15 + X + 1)] (see Section E.3) has the
following error detection properties:

E.3

It will detect all errors that change an odd number of bits (that is, 1, 3, 5, ... bit errors).

It will detect all errors that change 2 bits, provided that the block length is less than 32767
bits (including the CRC bits). Thus, the maximum count (length of data field) should be
4093.

It will detect all errors that consist of a single burst error of 16 or fewer bits. A burst error is
a group of bits in which the first bit and the last bit are in error and the intervening bits may
or may not be in error. A 16-bit burst error might have as many as 16 bits in error. The
partitioning of bits in error into burst errors is not unique.

It will detect all errors that consist of two occurrences of two adjacent bits in error, provided
that the block length is less than 32767 bits including the CRC bits.

It will detect all except the fraction 1/2 15 of errors that consist of a single burst error of 17
bits.

It will detect all except the fraction 1/2 16 of errors that consist of a single burst error of 18 or
more bits.

It will not detect some errors that change 4 bits. For example, it will not detect the error
pattern that is identical to the CRC polynomial. Thus the minimum hamming distance
between two valid messages (including the CRC bits}"is 4 bits.

CRC COMPUTATION

The algorithm for computing the CRC is as follows:
1.

Consider the header or data portion of the message as it appears on a serial line (LSB of the
first byte first, MSB of the final byte last) and append 16 zeros after the header or data.

E-l

Take the string of bits constructed in 1, and treat each bit as the coefficient of a term of a
polynomial with the LSB of the first byte being the coefficient of the highest order polynomial term. The highest order term is A * X63 for a header block and A * XC8 * <count> +
15) for a data block where A is the least significant bit of the first byte of the header or data.
The lowest order term is 0 * XO for both cases.

Divide the polynomial constructed in 2 by the CRC-16 polynomial X16 + XIS + X2 + 1,
using synthetic division and module 2 arithemtic on the coefficients (that is, addition =
subtraction = XOR. All carries and borrows are ignored) obtaining a quotient that is discarded and a 16-bit remainder.
Transmit the coefficients of the remainder as the block check bytes following the original
message bits, transmitting the coefficients of the highest order term (XIS) first. Thus, the first
byte represents coefficients of the )(8 through XIS terms of the remainder (from left to right)
and the second byte represents coefficients of the XO through X7 terms of the remainder
(also from left to right).

On reception, perform the same algorithm and compare the received block check bytes with
the computed block check bytes. If the bytes are not identical, an error has occurred.

NOTE
On a parallel circuit, the same algorithm is used
and the same block check bytes are computed,
although the bytes are sent in parallel instead of
serially. Notice that for the purposes of the
block check byte computation, the LSB of the
first byte is always treated as the highest order
term (that is, the term with the largest exponent) in the message polynomial.
On reception, the message may be handled with
the block check bytes included (two bytes
longer) and the algorithm computed based on
this longer message. If the remainder is not
zero, an error has occurred.

E-2

APPENDIX F
BOOTSTRAP TEST UNDER ITEP

Interprocessor test programs DZIT A ITEP .monitor and DZDMO ITEP DMC II overlay provide the
capabilities to check out the communications link (refer to Appendix G, Link Test) and to test the
ability of the DMCll to perform both Remote Load Detect and down-line load.
F.l REMOTE LOAD DETECT
Remote Load Detect (RLD) is also referred to as unattended system control in Maintenance Operation (MOP) mode specifications (Spec. No. AA-D60ZA-TC). Unattended system control is defined
as follows:
The Enter MOP Mode message is used to control an unattended system. This message, together with
the appropriate hardware, enables a satellite computer to halt current operation and begin operating in
either the MOP primary or secondary mode. This is accomplished by transferring control to a resident
MOP program or bootstrap. The hardware is used to recognize this message and force the computer
system to transfer control to the MOP program, usually residing in a read-only memory. The password
in this message protects the system from being controlled and loaded by an unauthorized host. Only
messages with a matching password will cause the system to enter MOP mode.
F.2

DMCII SETUP FOR REMOTE LOAD DETECT

F.2.l DMCII Addressing
When using the DMCII with a bootstrap module (M9301-YJ), the DMC must be addressed according
to the rules for floating address assignment. These rules are outlined in the installation section of this
manual. If the address is not set correctly, the (M9301- Y J) will not find the DMC and neither manual
booting of the DMC nor an RLD works.
F.2.2 DMCII Line Unit Setup
DMCll line units (M8201 and M8202), switch packs No.2 and No.3 must be properly set when
DMCll is to be used with a bootstrap module such as the M9301- Y J.
This combination is used in applications where RLD and subsequent down-line loading are required.
Setup of switch packs No.2 and No.3 is only required at the end of the link (satellite station) where
the M9301-YJ is installed.
Switch pack No.2 (E87 on M8201 and E90 on M8202) is set up to contain the 8-bit password specified
by the operatmg system.
•

Switch No.1 is the MSB, switch No.8 is the LSB.

•

Set switches off for a 1.

•

All switches off (SP2=377) inhibits RLD operation.

F-l

Switch pack No.3 (E88 on M8201 and E91 on M8202) is set to the low order 8 bits of the bootstrap
entry point (offset).
•

Switch No.1 is the MSB, switch No.8 is the LSB

NOTE
Switch No. 8 represents bit 0 of the boot address and
should be set to O.
•

Set switches off for a I.

•

Settingfor current M9301-YJ code should be 356 (octal) for booting unit 0 and 374 (octal)
for booting unit I.

NOTE
The bootstrap entry point (offset) may be different
for bootstrap ROM modules other than the M9301YJ.

F.3

PROCEDURE TO TEST REMOTE LOAD DETECT UNDER ITEP

Down-line load should not be attempted unless the DMCll link has been checked out successfully
using the link test under DMCII ITEP. The following are the switch settings required on the M9301YJ and DMCII line unit (M8202 or M8201) when using ITEP.

NOTE
The M930 1- YJ must have both the power-up boot
and diagnostics disabled.
MODULE/SWITCH

SWI

SW2

SW3

SW4

SW5

SW6

SW7

SW8

SP2
M8201/E87
M8202/E90

SP3
M8201/E88
M8202/E91

OFF

SW9

SWIO

In this mode, the originating station (the one running ITEP) will send an Enter MOP message to the
boot station (the one with M9301-YJ) and initiate a down line load. Successfully down-line loaded, the
boot station will print out a boot complete message. See events for RLD under ITEP which follow the
setup requirements below.
1.

Set the Enable/Halt switch on the console of the boot station to enable position. If the boot
station is aPDP-Il/34 or PDP-I 1/04, press Init (followed by CNTL HALT when 'using
KYII-LB).

Under ITEP at the originating station:
•

Modify parameter No.1 to 400

•

Modify parameter No.2 to 0

F-2

•

Deposit 1004 to console switch register

•

Type (CR)

The automatic mode bootstrap test should then complete and print out end pass message.
Events for RLD Under ITEP (See Figure F-I)
I.

At CPU No.1, ITEP steps up DMC 11, then assigns Enter MOP Mode (MOP 6) message.
NOTE
Scope the serial line on DMCll No.2 to see if there
is any message arriving every ten seconds.

2a.

At CPU No.2, DMCII No.2 compares MOP 6 message received to password setup in line
unit switch pack No.2.

If all passwords matched, DMCII No.2 writes 173000 plus the contents of switch pack No.
3 on line unit to location 24, clears location 26, and asserts AC LO on the UN I BUS.
NOTE
Load 125252 into locations 24 and 26. These two locations should be modified if 2.b is occurring.
Scope AC LO on CPU No.2 to see if it is pUlsing
because 2.b is occurring.

CPU No.2 program control is transferred to DMCll boot code in the ROM boot (M9301Y J type). The correct entry into boot code must be set up in line unit switch pack #3 which
contains offset added to 173000.

d. The DMCII boot code sets up the DMCII and sends a Request Secondary Boot (MOP 8)
message.
3.

At CPU No.1, ITEP checks receipt of MOP 8 message and transmits a memory load with
Transfer Address (MOP 0) message.

4a.

At CPU No.2, the ROM boot receives MOP 0 and transfers program control to location 6.

The down-line loaded program is then executed and a 800t Complete message is printed at
the console terminal.

NOTE
The above proc~dure will set the password for
down line load to O. This password is determined by the switch (SP2) settings on
M8201/E87 or M8202/E90 at the boot station or remote station. When doing down-line
load with software, the password used by software must match the password selected on the
DMCll line unit at remote station; in this
case password is O.

F-3

HOST

REMOTE NODE

LINK ACTION

HOST INITIATES DOWN-LINE
LOAD BY SETTING DMC INTO
MAINT. MODE WITH CNTRL I
AND SENDS A MOP 6 MSG. THE
PASSWORD IN MOP 6 MSG. MUST
EQUAL THAT OF THE REMOTE NODE.

DMC-11 RECEIVES MOP 6 MSG. AND
CHECKS PASSWORD. IF EQUAL,
DMC-11 TRIES TO DO AN NPR TO
LOCATION 24 WITH BOOT
ADDRESS FROM THE SWITCH PACK
ON THE LINE UNIT.(ADDRESS =
DMC-11 CODE IN M9301-YJ)
DMC-11 ALSO CLEARS LOC. 26.
NOW DMC-11 ASSERTS AC LO
TO TRAP CPU TO LOC.24 TO
JUMP TO M9301-YJ CODE.
THE M9301-YJ INITIALIZES
THE DMC TO MAINT. MODE AND
ASSIGNS A RECEIVE BUFFER AT
LOC.O WITH CHARACTER COUNT
EQUAL TO 7774. THE M9301-YJ THEN
TRANSMITS A MOP 8 MSG. TO
THE HOST. IF NPR WAS
UNSUCCESSFUL, THEN WHEN AC
LO WAS ASSERTED, THE CPU SHOULD
HAVE TRIED TO EXECUTE WHATEVER WAS IN LOC.24 AND
SHOULD START RUNNING. NOW
A SECOND NPR TO LOC.24 & 26
OCCURS FOLLOWED BY A
SECOND ASSERTION OF AC LO.
THIS SECOND SEQUENCE WILL
START THE CPU IF NO HARDWARE
FAILURE IS AT FAULT.

HOST CHECKS FOR MOP 8 MSG.
AND WHEN RECEIVED
TRANSMITS A MOP 0 MSG. TO
THE REMOTE NODE.
NOTE: MOP 0 MSG. MUST BE
A SELF STARTING MSG. AT
LOCATION 6 AND IF MORE
THAN ONE LOAD IS REQUIR~D
IT MUST ALSO BE ABLE TO
SEND A REQUEST FOR A
TERTIARY BOOT MSG. BACK TO
THE HOST CPU FOR MUTLIPLE
LOADS.

MOP 6 MSG.=

MOP 8 MSG=

MOP 0 MSG=

MEMORY ADRS.

CODE

MOP 0 MSG. RECEIVED.SAME
SEQUENCE AS FOR REMOTE
NODE REQUEST, SEE MOP 0
ON THE FLOW CHART (FIGURE
F-2).

4 BYTES EQUAL TO SYSTEM PASSWORD(PASSWORD=O FOR ITEP)

PASSWORD

CODE

DEVICE TYPE

MOP VERIFY

DMC= 12

CODE

I I
LOAD~

o _

PASSWORD

PROGRAM TYPE
0 SECONDARY LOADER

LOAD ADDRESS 4 BYTES

~ I~
2

PASSWORD

I I
0

PROGRAM IMAGE

DATA

Io I I I

TRANSFER ADDRESS I

6
MK·0867

Figure F-l Down Line Load To Remote .Node Using Remote Load Detect

F-4

For automatic boot (RLD, on successful recognition of the Enter MOP message the remote DMCII will NPR PC and PS to
locations 24 and 26 respectively and then it
will assert AC LO. Switch (SP No.3) setting
in the events sequence sets the bootstrap entry
point (offset) to 356 for booting DMCII unit

o.
3.

On 11/40, 45, 70, the A C LO asserted by the
DMCII will cause the CPU to assert DCLO.
The setting of M9301-YJ SW2 to OFF, prevents the M930 I from attempting to take control of the address bits during the simulated
power-up.

In order to verify switches SP2 and SP3 on
the line unit, run any DMCll diagnostics.
The STAT2 under the MAP OF DMCII
ST ATUS will give the actual set up of the
switches.
STAT2:

Low byte (bits 7-0) = SP2
(PASSWORD)
High byte (bits 15-8) = SP3
(BOOT OFFSET)

F.4 PROCEDURE TO TEST DOWN-LINE LOAD UNDER ITEP
The down-line load should not be attempted unless the DMCII link has been checked out successfully,
using the link test under DMCII ITEP.
I n this mode, the operator at the boot station has to do a boot to M930 1- Y J at the entry point for
DMCll boot code which sends a Request Secondary Boot message to the originating station. (See
Figure F-2).
The originating station running ITEP in bootstrap mode then replies with a Memory Load with Transfer Address message.
The boot station executes that program and prints out a Boot Complete message.

Procedure:
1.

U,nder ITEP at the originating station,
a.

Modify parameter No.1 to 2400

Modify parameter No.2 to 0

Deposit 1004 in Console Switch Register

Type <CR>

F-5

HOST

LINK ACTION

REMOTE NODE

INITIATE REQUEST FOR
SECONDARY BOOT MESSAGE.
1. TYPE XM,
2. LOAD ADDRESS 773356
or 773374 UNIT 1.
3. DEPRESS CONSOLE BOOT
SWITCH IF M9301-YJ
SWITCH PACK IS SET
TO ADDRESS 773356
OR 773374 UNIT 1.

DMC-11 RECEIVES SECONDARY
BOOT MSG. AND INFORMS
CPU THAT A MAINT. MSG.
WAS RECEIVED. DMC MUST
NOW BE INITIALIZED AND
THE CNTRL I FORMAT MUST
SET MAINT. MODE AND
TRANSMIT THE MOP 0 MSG.
TO THE REMOTE NODE.
NOTE: MOP MSG. 0 MUST
NOTE: MOP MSG. 0 MUST BE
A SELF STARTING MSG. AT
LOCATION 6 AND IF MORE
THAN ONE LOAD IS REQUIRED
IT MUST ALSO BE ABLE TO
SEND A REQUEST FOR A
TERTIARY BOOT MSG. BACK
TO THE HOST CPU FOR
MULTIPLE LOADS.

MOP 8 MSG=

MOP 0 MSG.=

MEMORY ADDRESS

NOTE: ADDRESSES ABOVE
SELECT DMC-11 UNIT 0 & 1
RESPECTIVELY WITHOUT
DIAGNOSTICS ENABLED. IF
ONLY DOING BOOT REQUEST
FROM THIS REMOTE NODE
THEN DIAGNOSTIC'S ENABLE
ADDRESS CAN BE USED.
(773354 & 773372 RESP).
ANY OF THE ABOVE PUTS
THE M9301-Y J CODE TO
SEND A MOP 8 MSG VIA
THE DMC-11 LINK.
M9301-YJ CHECKS FOR MOP 0
MSG. AND STARTS LOADING
AT LOCATION O.WHEN
DONE LOADING, THE M9301-Y J TRANSFERS
STARTING ADDRESS OF 6
FROM M9301-YJ TO START
MOP 0 MSG. (SECONDARY BOOT
REQUEST MSG. COMPLETED.)
MOP 0 MSG. MUST NOW REQUEST
TERTIARY LOADER, IF
NECESSARY FOR MORE DATA
TO BE LOADED.
NOTE: MAX DATA/MSG. IS 8K
WORDS OR 16K BYTES.

CODE

DEVICE TYPE

DMC= 12

MOP VERIFY

PROG RAM TYPE

o SECONDARY LOADER

CODE

LOAD#

-0

LOAD ADDRESS 4 BYTES PROGRAM IMAGE
DATA

TRANSFER ADDRESS

I 0 1 6 I 0

6
MK0868

Figure F-2

Remote Node Request for Down-Line Load Flowchart

F-6

At the boot station, boot the M9301- Y J via one of the following methods,
a.

Type XM under the console emulator

Load address 773356 and start

On the PDP-I 1/04 and PDP-I 1/34, when switch setting on the M9301-YJ is set up to
boot the DMCll, a control boot to KYII-LB initiates the boot to the DMCII. This
may take two control boots to occur with KYII-LB (CNTRL BOOT /CNTRL
HALT /CNTRL BOOT).
NOTE
Refer to the M9301-YJ manual for proper switch
setting in each case.

Upon successful completion of a down-line load, the terminal at the boot station prints out a
Boot Complete message.

F-7

APPENDIX G
LINK TEST

G.I ABSTRACT
ITEP (lnterprocessor Test Program) is designed as a maintenance aid to verify the proper operation of
a complete communication link from one PDP-II system to another or to a communication test center
(for remote applications). To run ITEP to check out a DMCll communication link, an ITEP monitor
(OZITA) and DMCII ITEP overlay (DZDMO) are required. Under ITEP, an additional feature
called Remote Load Detect (RLD) can also be checked out.
NOTE
The RLD checkout procedure is described in Appendix F.
REQUIREMENTS

G.2
•

PDP-II system with at least 4K words of memory.

•

OMCII communication interface.

•

Another PDP-II system with DMCII.

G.3 PROGRAM LOADING PROCEDURE
The DZITA monitor and DMCII ITEP overlay (DZDMO) are in absolute format and can be loaded
under an absolute loader, XXDP monitor, or can update two utility programs in the following order.
•

ITEP monitor DZIT A

•

DMCII ITEP overlay DZDMO

G.4 OPERATING PROCEDURES FOR LINK TEST
For detailed operating procedures, refer to the DZDMO listings. The following inputs are required to
run ITEP.
ITEP Questions

Operator Reply

INTERFACE TYPE DMC?

CR carriage return

BUS ADDRESS= 1600IO?

DMCII CSR Address CR

VECTOR ADDRESS=000300?

DMCII Vector Address CR

PRIORITY =000240?

CR for BR5

PARAMS #1 =OOOOOO?

CR for Link Test

G-l

PARAMS #2 =00000 I?

Set Switches

{

CR for Full Duplex
OCR for Half Duplex

Select mode of operation by referring to Table G-l and set
up CPU Console Switch Register.

CR to proceed.

G.4.1 MODE Selection
Three standard messages are selectable by an operator via console switches SW 10 and SW9 as follows:
SWIO

SW9

Data Selected

Get data from the operator.

$A THE QUICK BROWN FOX JUMPED OVER THE LAZY DOG.

$B 0123456789
$C COM-TEST MAYNARD THE QUICK BROWN FOX JUMPED
OVER THE LAZY DOG 0123456789

ITEP has four modules selectable by Console Switch Register SWO-3. The overlay performs the following functions in the four modes.
Internal Loopback Mode
1.

Establishes the modem connection.

Waits to receive a message terminated by the receive terminating character (001).

Verifies the data against the data selected by SW09 and SWIO (SW07=0).

Transmits the data selected by SW09 and SW 10 (SW08 =0), or transmits the received data
(SW08= 1).

Returns to monitor for END PASS (SW04= 1) or goes to step 1 (SW04=0).

Example:
To select message number 3 ($C COM-TEST .... ) and return to the monitor for the end pass
in Internal Loopback Mode, the switch setting should be 3030 or 3430.
External Loopback Mode
1.

The overlay establishes t~e modem connection.

Transmits the selected data.

Enables the receiver.

Waits for the message to be received.

G-2

Verifies the data (SW07=0).

Returns to the monitor for END PASS (SW04= 1) or goes to step 1 (SW04=0).

Example:
To select message number 3 ($C COM-TEST ..... ) and return to the monitor for the end pass
in External Loopback Mode, the switch setting should be 3024.

One-Way-In Mode
1.

The overlay establishes the modem connection.

Enables the receiver.

Waits for the message to be received.

Verifies the data (SW07=0).

Returns to the monitor for END PASS (SW04= 1) or goes to step 1 (SW04-0).

Example:
To select message number 3 ($C COM-TEST ..... ) and return to the monitor for the end pass
in One-Way-In mode, the switch setting should be 3022.

One-Way-Out Mode
1.

The overlay establishes the modem connection.

Enables the transmitter.

Transmits the selected data.

Returns to monitor for END PASS (SW04= 1) or goes to step 1 (SW04=0).

Example:
To select message number 3 ($C COM-TEST ..... ) and return to the monitor for the end pass
in One-Way-Out mode, the switch setting should be 3021.

G.4.2 Starting ITEP
ITEP requires a complete communications loop. Ensure that a loop is established with compatible
equipment. The variable parameters must be the same in each of the two processors. The mode must
be one of the options listed in Table G-2. The system that is to receive data first should be loaded and
started first. If the modem being used on this system has an automatic answer feature, it should be
enabled. The system that is to transmit first should then be loaded and the connection established.
The load address is 200. Refer to the program listing for details regarding restrictions, error messages,
and optional selections.

G-3

Table G-l

Operational Switch Setting

SWI5=1 HALT ON ERROR
SWI4= I SINGLE PASS
SWI4 HAS NO EFFECT IF SW04=0
SWI3=1 INHIBIT ERROR TYPEOUTS
SWI2= I INHIBIT ALL TYPEOUTS EXCEPT ERRORS
IF SW12=0 AND SW04= I END PASS IS TYPED
AND TRANSMITTED/RECEIVED DATA IS TYPED.
SWII = I USE PREVIOUSLY SPECIFIED DATA
SWIO=I DATA SELECT (WITH SW09)
SW09=1 DATA SELECT (WITH SWIO)
00= I GET DATA FROM OPERATOR
01 = I TEST MESSAGE #1 ($A QUICK BROWN FOX)
10= I TEST MESSAGE #2 ($B NUMERICS)
II = I TEST MESSAGE #3 ($C COMTEST /QUICK BROWN FOX/NUMERICS)
SW08= I TRANSMIT RECEIVED DATA (INTERNAL LOOPBACK MODE)
SW07=1 DO NOT TEST RECEIVED DATA
SW06=1 MONITOR TRANSMITTED DATA ON CONSOLE TTY.*
SW05=1 MONITOR RECEIVED DATA ON CONSOLE TTY.*
* IN MANY CASES, NOT ALL DATA WILL APPEAR ON THE CONSOLE
TTY. THIS IS ESPECIALLY TRUE WHEN THE COMM INTERFACE IS
RUNNING AT A FASTER RATE (BPS) THAN THE CONSOLE, BUT EVEN AT
EQUAL OR SLOWER RATES, ALL CHARACTERS MAY NOT APPEAR ON THE
CONSOLE.
SW04= I RETURN TO MONITOR FOR END PASS
WHEN SW04=0 PROGRAM LOOPS IN THE OVERLA Y NEVER RETURNING TO
THE MONITOR.
SW03=1 INTERNAL LOOPBACK MODE
SW02= I EXTERNAL LOOPBACK MODE
SWOI=I ONE-WAY-IN MODE
SWOO=I ONE-WAY-OUT MODE

Table G-2

Valid Mode Combinations

CPU No.1

CPU No.2

One-Way-Out

One-Way-In

One-Way-Out

External Loopback

Internal Loopback

External Loopback

External Loopback
(full-duplex)

External Loopback
(full-duplex with test
connector H3251 /H3250
/12-12528 connected at
the end of the cable

G-4

APPENDIX H
DZDMH DIAGNOSTICS
OPERATING PROCEDURE

H.l OVERVIEW
The function of the DZDMH· diagnostics is to verify that the DMCII option performs according to
specifications. The diagnostics verify that there are no malfunctions and that all operations of the
DMCII are correct in its environment.
Parameters must be set up to alert the diagnostics to the DMCll configuration. These parameters are
contained in the status table and are generated in two ways: (1) manual input, in which the operator
answers questions, and (2) autosizing, in which the program automatically determines the parameters.
DZDMH tests the DMCII-AR and DMCII-AL microprocessors (M8200- Y A and M8200- YB) or the
KMCII microprocessor (M8204). Free-running tests are performed. A line unit (M8201 or M8202)
must be installed. DZDMH can be used as a heat test diagnostic by manufacturing.
Currently five off-line diagnostics must be run in sequence to detect errors at an early stage. The five
diagnostics are:

H.2

CZDMC - basic W jR and microprocessor tests

CZDME - DDCMP Line Unit Test

DZDMF - BITSTUFF line unit tests

CZDMG - CROM andjump tests

DZDMH - free-running tests (heat test tape)

REQUIREMENTS

H.2.1 Equipment
Any PDP-II family CPU (except an LSI-II) with a minimum 8K word memory, and console terminal.
DMCII-AR with DMCI1-DA or DMCl1-FA,
DMCI1-AL with DMCII-MA or DMCII-MD.
H.2.2 Storage
The program uses all 8K words of memory except where the absolute loader and bootstrap loader
reside. Locations 1500 through 1540 contain the status table. This contains information generated at
the start of the diagnostics by manual input (questions) or automatically (autosizing). The status table
is an overlay area and should not be altered by the operator.

H-l

H.3

LOADING PROCEDURE

H.3.1 Method
All programs are in absolute format and are loaded using the absolute loader.
NOTE
If the diagnostics are on a media such as disk, magtape, DECtape, or cassette, follow the instructions
for the accompanying monitor.
The following table summarizes the absolute loader starting address for each memory size available.
MEMORY
SIZE

STARTING
ADDRESS

4K
8K
12K
16K
20K
24K
28K

017500
037500
057500
077500
117500
137500
157500

To load programs, perform the following steps:
1.

For the memory size available, place the starting address of the absolute loader into the
switch register and place the .HALT switch in the up position.

Press the LOAD ADDRESS key on the console and release.

Press the START key on the console and release (the program loads into the CPU).

H.4 STARTING PROCEDURE
To start up the programs, perform the following steps:
1.

Set the switch register to 000200.

Press the LOAD ADDRESS key and release.

Set the switch register as follows:

All bits = 0,

for autosizing

Bit 0 = 1,

for manual input (questions).

Bit 7 = 1,

for using existing parameters set up by a previous start or a previously run
DC 11 diagnostic.

H-2

Press the START key and release. The program prints Maindec Name and program nar
(if this was the first start-up of the program) and also the following:
MAP OF DMCll STATUS
PC

CSR

STATI

STAT2

SlAT3

001500

160010

145310

177777

000000

001510

160070

145320

177777

000000

The program prints the letter R and proceeds to run the diagnostic. The above example illustrate~
status table starting at address 1500 with information for two DM C 11 s.
NOTE
The user must verify the status table if autosizing is
selected.

Refer to Paragraph H.S.S for a description of the status table.

If the diagnostic was started with switch zero equal to one, indicating manual parameter input, th
questions are printed requiring operator response. The following is an example of a manual parame'
input dialogue. Operator responses are underlined.
HOW MANY DMCll'S TO BE TESTED?1
01
CSR ADDRESS?160010
VECTOR ADDRESS?SI0
BR PRIORITY LEVEL? (4,5,6,7)?5
DOES MICRO-PROCESSOR HAV'E CRAM? (Y OR N)N
WHICH LINE UNIT? IF NONE TYPE "N", IF MS201 TYPE "1", IF MS202, TYPE "2"?)1
IS THE LOOP BACK CONNECTOR ON?Y
SWITCH PAC#1 (DDCMP LINE#)?377
SWITCH PAC#2 (SMS73 BOOT ADD)?377
The status map is printed at the end of the dialogue and reflects the answers supplied by the operat
If autosizing is used, the status information must be verified to match the hardware. If it does I
match, the diagnostic must be restarted with switch zero equal to one and the questions answered
the operator.
H.4.1

Control Switch Settings

SW 15 Set:

Halt on error

SW 14 Set:

Loop On Current Test

SW 13 Set:

Inhibit error printout

SW 12 Set:

Inhibit type out/label on error

SW 11 Set:

Inhibit iterations (quick pass)

SW 10 Set:

Escape to next test on error

H-3

SW 09 Set:

Loop with current data

SW 08 Set:

Catch error and loop on it

SW 07 Set:

Use previous status table

SW 06 Set:

Halt in ROMCLK routine before clocking microprocessor

SW 05 Set:

Reserved

SW 04 Set:

Reserved

SW 03 Set:

Reselect DMCIIs desired active

SW 02 Set:

Lock on selected test

SW 01 Set:

Restart Program at Selected Test

SW 00 Set:

Build new status table from questions. If both switches 00 and 07 equal zero, a new status
table is built by autosizing.

Switches 06 and 09-15 are dynamic; they can be changed as needed while the diagnostic is running.
Switches 00-03 and switch 07 are static; they are used only on starting or restarting the diagnostic.
H.4.1.1

Startup Switch Register Options

SW 01

RESTART PROGRAM AT SELECTED TEST. It is strongly suggested that at least one
pass be made before trying to select a test because the program has to clear areas and set up
parameters. When this switch is used, the diagnostic will ask, TEST NO.? Answer by typing
the number of the test desired followed by a carriage return. This begins execution at the
selected test.

SW 02

LOCK ON SELECTED TEST. This switch, when used with switch 01, causes the program
to loop constantly on the selected test. Pressing any key on the console lets the program
advance to the next test and loop until a key is again pressed. If switch 02 equals zero when
switch 01 is used, the program begins at the selected test and continues normal operations.

SW 03

RESELECT DMCIIs DESIRED ACTIVE. A message is typed out for setting the switch
register equal to the active DMCIIs. This means if the system has four DMClls, bits 00,
01,02, and 03 are set in location DMACTV from the switch register. Using switch 00 alters
that location. Therefore, if four DMCIIs are in the system, do not set switches greater than
number 03 in the up position; this causes a fatal error. Do not select more active DMCIIs
than information in the status table.

The method for setting the startup switch register options follows.
1.

Load address 200.

Set switch zero to one. The program types a message.

Set a switch for each DMC desired active. For example, if you have four DMCII s but want
to run only the first and the last, set switch register bits 00 and 03 to one. Press CONTINUE.
The number (if valid) will be in the data lights (except for the PDP-II/OS).

H-4

Make any other switch settings desired. Press CONTINUE.

H.4.1.2

Dynamic Switches

SW 12:

Delete print out/bell on error.

SW 13:

Delete error printout.

SW 15:

Halt on the error.

SW 08:

Go to the beginning of the test (on error).

SW 10:

Go to the next test (on error).

The scope switches are listed below.
SW 06:

Halt in ROMCLK routine before clocking microprocessor instruction. This allows the
operator to scope a microprocessor instruction in the static state before it is clocked. Press
CONTINUE to resume running.

SW 09:

(If enabled by SCOPl) on an error. If * is printed in front of the test number (example,
*TEST NO. 10), SW 09 is incorporated in that test and is therefore recommended for the
scope loop (SW 11 =0, SW 10=0, SW 09= 1, SW 08=0). If SW 09 is not enabled and there
is an error (constant), SW 08 is recommended (SW 14=0, SW 10=0, SW 09=0, SW 08= 1).
For intermittent errors, SW 14= 1 will loop on test regardless of error or no error (SW
14=1, SW 10=0, SW 09=0, SW 08=1,0).

SW 11:

Inhibit interactions.

SW 14:

Loop on current test.

H.4.2 Starting Address
The starting address is at 000200. There are no other starting addresses for the DMCII diagnostics.
NOTE
If address 000042 is nonzero, the program assumes it
is under ACTII or XXDP control and will act accordingly after all available DMClls are tested. The
program returns to XXD P or ACT II.
H.5 OPERATING PROCEDURE
When the program is initially started, messages described in Paragraph H.4 are printed. The program
then runs the diagnostic.
H.5.1 Program and/or Operator Action
Program and/or operator may be required by the diagnostics. Operator action should be as follows:

Halt on error (via SW 15=1) whenever an error occurs.

Clear SW 15.

Set SW 14 (loop on this test).

Set SW 13 (inhibit error printout).

H-5

The test number and program counter will be displayed. Depending on the particular test, an error
message may be displayed to aid the operator in determining the problem. If more information concerning the error report is necessary, look in the listing for the test number which was typed out and
then note the program counter <?f the error report.
H.6 ERRORS
A test number and program counter are displayed at the time of an error (providing SW 13 =0 and SW
12 =0). In most cases, additional descriptive information is supplied in the error message.
H.6.1 Error Recovery
If the DMCII hangs the bus (gains control of the bus so" that console manual functions are inhibited),
an INIT or power down/up is necessary for the operator to regain control of the CPU. When this
happens, inspect location TSTNO (address 1220) for the number of the test running at the time of
error.
H.7

RESTRICTIONS

H.7.1 Starting Restrictions
The status table should be verified regardless of how the program was started. It may also be used with
the information printed on the console terminal to isolate problems.
H. 7.2 Operating Restrictions
The status table must be set up the first time a DMCII diagnostic is loaded into core and run. This is
done by manual input (SW 00= 1) or by autosizing (SW 00=0 and SW 07=0). Thereafter, the status
table need not be set up by subsequent restarts or by loading the next DMC diagnostic because it is
overlayed. The current parameters in the status table are used when SW 07 = 1 on startup.
H. 7.3

Hardware Configuration Restrictions

DMCll(M8200)

Jumper W1 must be installed and switch 7 of E76 must be in the OFF
position.

KMC(M8204)

Jumper WI must be installed.

LINE UNIT(M820 1)

Jumpers WI, W2, and W4 must be installed. Jumpers W3, and W5 must be
removed. SW 8 of E26 must be in the ON position.

LINE UNIT(M8202)

Jumper WI must be installed. SW 8 of E26 must be in the OFF position.

H.8

ADDITIONAL INFORMATION

H.8.1 Execution Time
All DMCII device diagnostics display an END PASS message within four minutes providing no
errors occurred; SW 12=0 and SW 11 = 1 (DELETE ITERATIONS) are set. Actual execution time
depends on the PDP-II CPU configuration and the type of memory in the system.
H.8.2 Pass Complete
Every time the program is started, the tests run as if SW 11 (DELETE ITERATIONS) were up (= 1).
This is to verify no hard errors as soon as possible. Therefore, each time the program is started, the
first pass will be a quick pass until all DMClls in the system are tested. When the diagnostic has
completed a pass, a display similar to the following appears:
END PASS DZD MH CSR: 175000 VEC: 0300 PASSES: 000001
ERRORS: 000000

H-6

NOTE
The pass count and error counts are set to zero only
when the diagnostic is started. Thereafter, the total
passes and errors are cumulative for each DMCll
since the diagnostic was started and are reflected in
PASSES: and ERRORS:.

H.8.3

Key Locations

RETURN (1214)

Contains the address where the program returns when the iteration count is
reached or if loop on test is asserted.

NEXT (1216)

Contains the address of the next test to be performed.

TSTN0(1226)

Contains the number of the test being performed.

RUN (1316)

The bit in RUN always points to the DMCII currently being tested. For example,
(RUN) 1302/0000000001000000
means that DMCl1 number 06 is the DMCl1 now running.

DMCROO-DMCRI7

DMSTOO-DMSTI7
( 1500)-( 1640)
These locations contain information needed to test up to 16 (decimal) DMClls
sequentially. They contain the CSR, VECTOR, and STATUS concerning the
configuration of each DMCll.

DMACTV (1306)

Each bit set in this location indicates that the associated D M C 11 will be tested in
turn. For example, (DMACTV) 1276/0000000000011111 means that DMCll
numbers 00, 01, 02, 03, 04 will be tested. As another example, (DMACTV)
1276/0000000000010001 means that DMCll numbers 00 and 04 will be tested.

DMCSP (1401)

Contains the CSR of the current DMC11 under test.

H.8.4 Status Table
The status table starts at location 1500. It is filled by autosizing or by the manual parameter input. The
locations may also be altered by hand (toggled in) to suit the specific configuration.
The status map example shown below contains information for two DMClls. The table can contain
up to 16 DMClls. Following the map is a condition of the bits for each map entry.

H-7

MAP OF DMC11 STATUS
PC

CSR

STAT1

STAT2

STAT3

001500

160200

140310

177777

000000

001510

160210

016120

000000

Each map entry contains four words with the status information for four DMClls. The PC shows the
core memory location of the first of the four words. In the example above, the first DMC status is in
locations 1500,1502,1504, and 1506. The second DMC status is located at 1510, 1512,1514, and 1516.
The informaHon contained in each four-word entry is defined as follows:
CSR:

Contains DMCII CSR address

STATl:

BITS 00-08

DMCII vector address

BIT 15 = 1 Microprocessor has CRAM
BIT 15 =0 Microprocessor has CROM
BIT 14 = 1 Turnaround connector is on
BIT 14=0 No turnaround connector
BIT 13 =0 Line unit is an M8201
BIT 13 = 1 Line unit is an M8202
BITI2=1 Nolineunit
BITS 9-11 DMCII BR priority level
STAT2:

Low byte is switch PAC#1 (DDCMP line number)
High byte is switch PAC#2 (BM873 boot address)

STAT3:

BIT 0= 1 perform free-running tests on KMC (must be set manually. See test 1.)

H.8.5
H.8.5.1

BIT 1 =0

DMCII-AR (low-speed)

BIT 1 = 1

DMCII-AL (high-speed)

Method of Autosizing
Finding the Control Status Register - The autosizing routine finds a DMCll as follows:

Starting at address 160000, all addresses in increments of 10 up to and including address
167760 are tested.

If the address does not time out, the first CROM address is written to address 125252 and
then read back.

H-8

If the first CROM address contains -1, 125252,626, or 16520, a DMCII or KMCII has
been found. If not, the address is updated by 10 and the search continues. These val~es are
interpreted as follows:
-1

DMCII with no CROM

125252

KMCII with CRAM

626

DMCII-AL

16520

DMCII-AR

Further tests are performed to determine: (1) which line unit, if any, is installed; (2) if a loopback connector is installed; and (3) various switch settings on the line unit. This is why the
status table must be verified by the user. If any of the information does not agree with the
hardware, the diagnostic must be restarted and the questions answered. All DMClls in the
syst~m will be found by the autosizer. If none are found, the diagnostic must be restarted
and the questions answered.
H.8.5.2 Finding the Vector and DR Level - The vector area (addresses 300-776) is filled with the
instruction lOT and .+2 (next address). The processor status is started at 7, and the DMCII is programmed to interrupt. The processor status is lowered by one until the DMCII interrupts. A delay is
made and, if no interrupt occurs at processor status level three (because of a bad DMCll), the program assumes vector address 300 at bus priority level 5. The problem should be corrected in the
diagnostic and the program set up again to obtain the correct vector. If an interrupt occurred, the
address to which the DMC 11 interrupted is reported as the vector.

NOTE
If the vector reported is not the same as set up by the
operator, autosizing should not be done.
H.8.6 Software Switch Register
If the diagnostic is run on a PDP-II /04 or other CPU without a hardware switch register, a software
switch register is used. If the hardware switch register does not exist or it contains 177777, the software
switch register is used.
To obtain control at any allowable time during execution of the diagnostic, the operator types CTRL
G on the console terminal keyboard. This action causes the following to be printed:
SWR=XXXXXX NFW?
The current contents (in octal) of the software switch register appear in place of XXXXXX. The
software control routine then awaits operator action. The operator must type one or more of the
following legal characters: 0-7, line field, carriage return, or CTRL U. No check is made for legality. If
the input character is not a line feed, carriage return, or CTRL U, an octal digit is assumed.
To change the contents of the software switch register, the operator types the new desired val ue in octal
(leading zeroes may be omitted) and te~minates the input string with a carriage return or line feed
depending on the program action desir~. The input value is truncated to the last six digits typed. At
least one digit must be typed per input string prior to the terminator before .a change to the software
switch register occurs.

H-9

When the input string is terminated with a carriage return, the diagnostic continues execution from the
point of interruption. If a carriage return is the only character typed, the program continues without
changing the software switch register. The line feed differs from the carriage return by transferring
control to address 200 and restarting the program.
If CTRL U is typed at any point in the input string, the input value is disregarded and
SWR=XXXXXX NEW? displayed.

To set the software switch register for the starting switches, first load the diagnostic, type CTRL G,
and then start the diagnostic.

H-IO

APPENDIX I
DIFFERENCES BETWEEN DDCMP V4.0
AND DMCll IMPLEMENTATION OF
DDCMP V3.03

This appendix summarizes the known differences between DDCMP V4.0 and DMCII implementation of DDCMP V3.03.
A.

A DMCII receiver does not count characters in the data field of a numbered data message when
the following occurs:
a.

No received buffer" is available.

Received message is out of sequence.

Received message length (character count in valid header) is longer than the assigned received buffer.

The receiver is reset to resynchronize after detecting a bad header CRC. This could cause false
synchronization or message framing if the data field contains SYNC characters followed by a
valid header.

If a receiver buffer is not available when a numbered message header comes in, the header BCC is
not checked. The resulting NAK, no"buffer available message, is queued to the transmitter even if
the header BCC is bad.

In DDCMP Maintenance Operation (MOP) Mode, the maintenance message headers are sent
with Quick SYNCs and select bits cleared, and a number appears in the NUM field.

The reply timer is started at the beginning of a message transmission rather than at the end.

On receive, the DMCII-AL assumes the Quick SYNC bit is always set and cannot receive abutted messages. A synchronization sequence is required for each message.

On DMCll start up, the START message is sent every second. In half-duplex applications this
could cause line contention problems where both stations would send START at the same time,
every second.

All NAKs received are accumulated in a cumulative counter (PDP-II Base Address +5). There is
no NAK received threshold counter.

The receiver ignores ACK with a response number greater than X, where X is the number of the
data message that was last transmitted.
1-1

Skipping of unneeded retransmission is not possible. For example, if DMCll sends out numbered messages 1,2, 3,4, 5, and 6 and there was a noise hit on message No.3 only, DMCll No.2
replies with a NAK (RESP=2) and then DMCll No.1 has to retransmit 3, 4, 5, 6.

On transmit, the DMCll always has Quick SYNC and select bits cleared in a numbered message
header. The transmitter always sends out a separate control message following the numbered
message with both Quick SYNC and select bits set. All unnumbered messages have both QS +
SEL bits set.

On receive, the DMCI1-AR always checks the Quick SYNC and select bits and therefore is
capable of receiving abutted messages.

L. . Quick SYNC and Select must never be set in a numbered message to be received by DMCll, that
is, on messages from non-DMC DDCMP implementations.
NOTE
If Q and S' bits are set in the numbered message
header, both bits will be written into memory extension bits of the Receive Buffer Address (BAjCC 0).
Therefore, RCV VACC/O will have memory extension bits set.
If the Select bit is set in a data message on HDX
link, a NAK may be lost due to collision of receive
data with the transmitted NAK (DMCII-AR only).
This causes the Reply (REP) sequence to be initiated.

Synchronization sequences always consist of eight SYNC characters for DMCII-AR and ten
SYNC characters for DMCII-AL.

The reply to a REP message is always a NAK (with implied acknowledgements).

NAK MSG number = last correctly received MSG number, that is, if NAK MSG number = last
transmitted message number, all messages have been received correctly. (Possibly a lost ACK
occurred.)

ACKs are sent every second for the last message. After completion of START SEQ, Idles ACKs
for message number O.
.

In HDX - The section interval timer is the same at both ends creating a possible deadlock where
both ends are.in contention for the link.

1-2

APPENDIX J
PROGRAMMING PROCEDURES FOR DMCII-AR
OPTION IN AUTO DIAL/AUTO ANSWER
APPLICATION

The DMCII AR option can be programmed to function in autodial/autoanswer applications. The
autodial programming of the associated DN II automatic calling unit interface should be ordered the
same as other communication options, that is, perform the dial sequence and then start the DMCII,
not the inverse. The premature abort of messages via the communication link can be detected by using
dummy messages and the aborted call can be programmed as part of the driver. Details are presented
in paragraphs J.I to J.3 following.

J.t

AUTO DIAL
The DMCII functions with the Bell 801 autodial or equivalent dialer provided the proper programming sequence and 801 options are selected.
When the DMCll is used in conjunction with a Bell 801 autodial, the DMCll must be halted with
MASTER CLEAR or procedure error prior to asserting Call Request (CRQ).
When dialing and modem handshaking are completed, Data Set Status (DSS) in the 80 I dialer is
asserted. Only then should the DMC be given a Base and Control Transfer.
The recommended method of terminating calls is with the 801 dialer strapped to use the CRQ disconnect option. After CRQ is dropped (on hook), the DMCII should be halted again by MASTER
CLEAR or procedure error so the next 80 I dial may take place.
An alternate route to disconnecting is via the DTR disconnect option in the 801 dialer. Disconnect in
this case is caused by dropping DTR in the DMC. The DMCll drops DTR for one second when a
procedural error is asserted, and the DMCII is then left in this state until the next 801 dial takes place.
J.2 PREMATURE LINK DISCONNECT
The DMCII does not monitor the state of the carrier and, therefore, cannot detect line loss during
message framing. This can be programmed around by periodically sending dummy messages and
running a timer on messages received.
J.3 AUTO ANSWER
The DMCII microcode does not test for a premature call abort. An abort occurs when a call is
received but the caller does not enter the data mode (that is, Carrier is not asserted), thereby causing
the call to disconnect.
The user may test for a premature call abort by means of a ring timer. In general, the software must
clear DTR and scan RING. When RING is detected, set DTR, start the DMCll (BASE I, CNTL I,
etc.) and start the software timer. If the software timer expires before the DMC11 interrupts with
DDCMP start received, then MASTER CLEAR DMCll, clear DTR, and scan RING again.

J-l

A flow chart of the auto answer sequence is presented in Figure J-l. This programming technique of
loading microinstructions while the DMCll microprocessor is running is only valid when the DMCll
microcode is in the initialized state.

CLEAR DTR

RING STATE TO
DMC BSEL 3 BIT 7
(EVERY 300 NS)

PROGRAM NOTES

COMMENTS

MOVB # 100, DMC BSEL 1 ;

MASTER CLEAR
DMC11

MOV # 122013 DMC SEL6;
NOP (WASTE TIME)

LOAD MICROINSTRUCTION
TO CLEAR DTR

MOVB # 202, DMC BSEL 1 ;

SET ROM IN

MOV # 21263, DMC SEL6;

LOAD MICROINSTRUCTION
TO WRITE
RING STATE TO BSEL 3

DRIVER DOES RING SCAN

DDCMP START
REC'D TIMER
ON

MOVB # 100, DMC BSEL 1
(ALSO SETS DTR)

BASE I, CONTROL I
RX BUFFER

~.......-

SERVICE DMC AS REQUIRED
MK-0815

Figure J-l

Auto Answer Sequence

J-2

GLOSSARY

ACKNOWLEDGE (ACK):
I ndicates that the previous transmission block· was accepted by the receiver and it is ready to
accept the next block of the transmission.
ARITHMETIC LOGIC UNIT (ALU):
Allows the microprocessor to perform arithmetic and logic operations.
A PORT:
Read/write input to the multiport RAM.
ASYNCHRONOUS TRANSMISSION:
Transmission in which time intervals between transmitted characters may ·be of unequal length.
Transmission is controlled by start and stop elements at the beginning and end of each character.
Also called Start-Stop transmission.
BUFFERED ARITHMETIC LOGIC UNIT (BALU):
Operations performed by the ALU are buffered by the BALU and directed to data memory,
respective registers and the Berg Port.
BERG PORT:
An 8-bit port that allows the microprocessor to communicate with other devices without using the
UNIBUS.
BIT-STUFF PROTOCOL:
Zero insertion by the transmitter after any succession of five continuous ones designed for bitoriented protocols such as IBM's Synchronous Data Link Control (SDLC).
BITS PER SECOND (BPS):
Bit transfer rate per unit of time.
B PORT:
Read Address input of the multiport RAM (Read Only Port).
BRANCH REGISTER (BRG):
Temporary card storage register used for branch determination and shifting right.
BUFFER:
Storage device used to compensate for a difference in the rate of data flow.when transmitting data
from one· device to another.
CCITT:
Comite Consultatif Internationale de Telegraphie et Telephonie - An international consultative
committee that sets international communications usage standards.

GLOSSARY-l

CONTROL AND STATUS REGISTERS (CSRs):
Communication of control and status information is accomplished through these registers.
CRC (Cyclic Redundancy Check):
An error scheme in which the check character is generated by taking the remainder after dividing
all the serialized bits in a block of data by a predefined number.
CROM:
Plug-in Control Read Only Memory used as the instruction memory for the processor.
CYCLIC REDUNDANCY CHECK (CRC):
An error detection scheme in which the check character is generated by taking the remainder after
dividing all the serialized bits in a block of data by a predetermined binary number.
DATA LINK ESCAPE (DLE):
A control character used exclusively to provide supplementary line control signals (control character sequences or DLE sequences). These are two-character sequences where the first character is
D LE. The second character varies according to the function desired and the code used.
DATA MULTIPLEXER (DMUX):
An 8-bit wide, 8-to-l multiplexer used to select data for the B input of the ALU.
DATA-PHONE DIGITAL SERVICE (DDS):
A communications service of the Bell System in which data is transmitted in digital rather than
analog form, thus eliminating the need for modems.
DESTINATION ROM (DROM):
Controls the operand as defined by the destination of the instruction in the instruction register.
DIGITAL DATA COMMUNICATIONS PROTOCOL (DDCMP):
DIG IT AL's standard communications protocol for character oriented protocol.
DIRECT MEMORY ACCESS (DMA):
Permits I/O transfers directly into or out of memory without passing through the processor's
general registers.
DMC:
Data Communications Controlled option designation for the ROM controlled microprocessor
and line units that are run by the micro controller.
ELECTRONIC INDUSTRIES ASSOCIATION (EIA):
A standards organjzation specializing in the electrical and functional characteristics of interface
equipment.
FROM:
Function ROM - Controls up to 16 functions performed by the ALU.
FULL-DUPLEX (FDX):
Simultaneous two-way independent transmission in both directions.
FIELD REPLACEABLE UNIT (FRU):
Refers to a faulty unit not to be repaired in the field. Unit is replaced with a good unit and faulty
unit is returned to predetermined location for repair.

GLOSSARY-2

FIFO:
First In/First Out characteristic of the SILO hardware buffer.
HALF-DUPLEX (HDX):
An alternate, one-way-at-a-time independent transmission.
IBUSjOBUS:
Microprocessor NPR control, -miscellaneous registers, and CSRs.
IBUS* jOBUS*:
Microprocessor NPR control, miscellaneous registers, and CSRs.
INSTRUCTION REGISTER (IR):
Contains the instruction that is being executed. Outputs are used to control the microprocessor.
LARS:
Field Service Labor Activity Reporting System.
LINK MANAGEMENT:
The Link Management component resolves the- transmission and reception on links that are
connected to two or more transmitters and/or receivers in a given direction.
LU IBUS:
The Line Unit Input data Bus provides a path to the DMUX via the Berg connector.
MEMORY ADDRESS REGISTER (MAR):
Controls the data memory for buffered arithmetic and logic operations to main memory.
MAIN MEMORY (MEM):
Data storage area for the microprocessor 4K X 8 RAM; cannot be accessed directly by the CPU.
MAINTENANCE INSTRUCTION REGISTER (MIR):
Provides a destination for an instruction that can be loaded by the CPU during maintenance.
MOP:
Maintenance Operation Protocol.
MULTIPORT RAM:
Contains all M 8200 control and status registers between the microprocessor and the CPU processor.
NEGATIVE ACKNOWLEDGMENT (NAK):
Indicates that previous transmission block was,in error and that receiver is ready to accept a
retransmission of tde erroneous block (also a Not Ready Reply to a Station selection in multiport).
NON-PROCESSOR REQUEST (NPR):
Direct memory access type transfers, see D MA.
PROGRAM COUNTER (PC):
A 14-bit counter used to control the address of the control ROM directly.
PROGRAM COUNTER REGISTER (PCR):
Contains upper six bits to be loaded into the PC on a branch condition and provides extra field
addressing with future expansion capability.

GLOSSARY-3

PROTOCOL:
A formal set of conventions governing the format and relative timing of message exchange between two communicating processes.
RANDOM ACCESS MEMORY (RAM)
READ ONLY MEMORY (ROM)
RS232-C:
EIA standard single-ended interface levels to modem.
RS 422:
EIA standard differential interface levels to modem.
RS 423:
EIA standard single-ended interface levels to modem.
RS 449:
EIA standard connections for RS422 and RS423 to modem interface.
SCRATCHPAD MEMORY (SP):
Read/write memory used for temporary storage of data.
SROM:
Source ROM - Defines the type of instruction to be executed and the source of the data used for
the instruction.
SYNCHRONOUS TRANSMISSION:
Transmission in which the data characters and bits are transmitted at a fixed rate with the transmitter and receiver synchronized.
SYSTEM CLOCK:
Basic timing generated by a 33.33MHz crystal providing microprocessor timing functions.
UNIBUS:
A single high speed bus on which system components connect and communicate with each other.
Addresses, data, and control information are transmitted via 56 available lines of the bus.
V.35:
(CCITT Standard) - Differential current mode type signal interface for high-speed modems.

GLOSSARY-4

INDEX

B
Bootstrap Test Under ITEP, F -1 through F -7
BYTE SEL 1 LOCKOUT, 2-14, 3-4, 5-3

C
Control Status Registers (CSRs), 1-2, 1-3, 3-2
through 3-26
Cyclic Redundancy Check (CRC), 1-5, 1-6,3-34
D
Data Port, 1-3,3-4,3-17,3-20
DDCMP Block Check Computation, E-l, E-'2
DPCMP, D-l through D-6
Description, D-3,through D-5
Message Format, D-6
DMCII
Base Table, 3-28, 3-29, 3-30
Command Structure, 3-2
Base Input (BASE 1) Format, 3-14, 3-16
BSEL 0 - Input Register, 3-4 through 3-7
BSEL 0 Bit Functions, 3-7
BSEL 1 - Maintenance Register, 3-4, 3-5,
3-6, 3-8
BSEL 1 Bit Functions, 3-8
BSEL 2 - Output Register, 3-4, 3-5, 3-6, 3-8
BSEL 2 Bit Functions, 3-8
Buffer Assignment Formats, 3-9
Control Input (CNTL I) Format, 3-9, 3-17,
3-19
SEL 6 Bit Functions, 3-9, 3-11, 3-12, 3-13
Control Output (CNTL 0) Format, 3-24,
3-25, 3-26
Control Bits/Associated Octal Error
Codes, 3-11, 3-12, 3-13
CSR Bit Assignment, 3-4
Input Commands, 3-2, 3-10
Base In, 1-4, 3-14, 3-16, 3-18
ButTer Address In, 1-4, 3-21, 3-22, 3-23
Control In, 1-4,3-9,3-17,3-19,3-20
Initialization, 3-14, 3-15

INDEX-l

DMCII (Cont)
Output Commands, 3-4, 3-24
ButTer Address Out, ·1-4, 3-24, 3-26
Control Out, 1-4, 3-10, 3-24, 3-26
Unibus Control and Status Registers, 3-2, 3-3
Data Terminal Ready, 5-4
Functional Description of Microprocessor,
1-1 through 1-4, 4-1
Address Selection.Logic, 4-34
Branch, 4-8, 4-9, 4-10
Clock, 4-32, 4-33
Data Paths, 4-1, 4-3
DDCMP Running Mode, 1-5, 1-6
DMCII-AL, 1-1, 1-2, 2-2
Local Applications, 1-1 through 1-3
DMCII-AR, 1-1, 1-2, 2-2
Remote Applications, 1..: 1 through 1-3
DMCII-DA, 1-1, 1-2, 2-2
DMCII-FA, 1-1, 1-2,2-2
DMCI1-MA, 1-1, 1-2, 2-3
DMCII-MD, 1-1, 1-2,2-3
Interrupt Control Logic, 2-9, 4-35, 4-37
INBUS/OUTBUS, 4-2, 4-25 through 4-30
INBUS*/OUTBUS*, 4-2, 4-25 .through
4-30
Line Unit Interface, 4-38
Maintenance CSR, 4-31
Move, 4-9, 4-11, 4-12, 4-13
Move Branch, 4-13
NPR, 1-1, 1-3, 2-4, 2-9, 2-17,4-1, 4-7,
4-23, 4-29, 4-34
NPR Control Logic, 4-7, 4-26, 4-28, 4-29,
4-34, 4-35, 4-36
Normal DDCMP Mode, 1-4, 1-5
Typical System Timing, 4-38, 4-39
Installation
Checkout Procedure, 2-21, 2-22
DMC 11 Cabling, 2-22, 2-23
Link Test Program, 2-22, G-l through G-4

DMCll (Cont)
Device and Vector Addresses, 2-4, 2-5
Device Address Assignments, 2-4
Examples of Device and Vector Assignments, 2-6 through 2-9
Interrupt Priority, 2-9
UNIBUS Loading, 2-9
Vector Address Assignments, 2-5, 2-6
Installation Procedures, 2-15
Backplane, 2-4, 2-10, 2-17, 2-20, 2-21
Cable Routing, 2-17, 2-19
Configuration Considerations, 2-1
Inserting Line Unit Module, 2-18
Inserting Microprocessor Module, 2-16
Installation in a BAII-K Box, 2-20
Installation in a DDII-D Backplane,
2-20, 2-21
Mechanical Packaging, 2-1
Option/Parts Description, 2-2, 2-3
Power Requirements, 2-4
Pre-Installation Considerations, 2-1
Unpacking and Inspection, 2-1
Module Installation and Customization, 2-9
Pre-Installation Checkout Procedure, 2-9
through 2-14
Dev;ice and Vector Address Switches,
2-10 through 2-14
Select Device Addresses, 2-1
Select Vector Address, 2-10, 2-14
Maintenance
Corrective Maintenance, 5-6 through 5-14
External Maintenance Mode, 5-4
Maintenance Mode, 3-33, 3-34, 5-1, 5-3
Maintenance Philosophy, 5-1, 5-5
Maintenance Register (BSEL 1), 4-17,
4-31, 5-1
BSEL 1 Bit Description, 4-31, 5-2, 5-3
Preventive Maintenance, 5-5
Single Step Internal Maintenance Mode, 5-4
System Test, 5-3
System Test Internal Maintenance Mode,
5-4
Operation, 1-2, 1-6
Power Fail Recovery, 3-28
Programming Information
Interrupt Vectors, 3-1
Input Interrupts, 3-1
Output Interrupts, 3-1

DMCll (Cont)
Priority Selection, 3-1
Remote Load Detect, 3-35 ,3-36, 3-37
Running Diagnostics, 2-21, 2-22, 5-6
through 5-13
Shutdown, 3-31
Start-Up, 3-27
Threshold Counters, 3-28
DZDMH Diagnostics, 5-9, H-l through H-I0
E
Error Condition, 3-11, 3-12, 3-13
Fatal, 1-4, 3-11, 3-12, 3-13

Non-Fatal, 1-4, 3-11, 3-12, 3-13
Error Counters, Cumulative, 3-28, 3-31
Error Recovery, 1-4
Error Reporting, 1-4, 3-28

F
Field Replaceable Unit, 5-5
Full-Duplex Mode, 1-4, 3-38
H
Half-Duplex Mode, 1-4, 3-39
I
Interrupt Enable Input (lEI), 3-7, 3-10, 3-14,
3-17,3-20,3-23
L
Line Unit Module (Notched Hex), 1-1, 1-2
2-1, 2-4, 2-18
Logic Symbology, B-1 through B-4

M
MASTERCLEAR, 1-5,3-8,3-14,3-17,3-27,
3-32
Microprocessor Module (Hex), 1-1, 1-3, 1-4,
.2-1, 2-4, 2-16
Modems
Control, 3-32
Integral, 1-2, 2-3
Synchronous, 1-3
P
PDP-II
Memory, 1-2, 1-3, 1-4
Organization, A-I through A-4
Protocol Header, 1-5
INDEX-2

R
Ready In (RDI), 3-2, 3-7, 3-10, 3-14, 3-17, 3-20,
3-23
RUN, 3-8, 3-14, 5-3
RUN INHIBIT, 2-14, 4-31, 5-3

U
UNBIUS, 3-21, 3-39,4-7,4-23,4-34
User Program, 1-2, 1-3
Definition, 1-2
Interface to the DMCll, 1-3

S
Synchronous Serial Data Handling, C-l through
C-4

INDEX-3

DMCII IPL MICROPROCESSOR
TECHNICAL MANUAL
EK-DMCMP-TM-002

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