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EK-DHU11-UG-002

November 1986

111 pages

Original

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Document:	DHU11 Interface User's Guide
Order Number:	EK-DHU11-UG
Revision:	002
Pages:	111
Original Filename:	http://bitsavers.org/pdf/dec/unibus/EK-DHU11-UG-002_DHU11_Interface_Users_Guide_Nov86.pdf

OCR Text

EK-DHU11-UG-002

DHU11 Interface
User's Guide

EK-DHU11-UG-002

DHU11 Interface
User's Guide

Prepared by Educational Services
of
Digital Equipment Corporation

1st Edition, June 1984
2nd Edition, November 1986

Digital Equipment Corporation 1984, 1986
All Rights Reserved

The information in this document is subject to change without notice and should
not be construed as a commitment by Digital Equipment Corporation. Digital
Equipment Corporation assumes no responsibility for any errors that may
appear in this document.

Printed in U. S.A.

This document was set on a DIGITAL DEeset Integrated Publishing System.
Book production was done by Educational Services Development and
Publishing in Merrimack, N.H.

The following are trademarks of Digital Equipment Corporation:

~DmDDmD

DEC
DECmate
DEC set
DECsystem-l0
DECSYSTEM-20
DECUS

DECwriter
DIBOL
MASSBUS
PDP

P/OS
Professional
Rainbow
RSTS

RSX
Scholar
ULTRIX
UNIBUS
VAX
VMS
VT
Work Processor

CONTENTS
Page

CHAPTER 1

INTRODUCTION

1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.3
1.3.1
1.3.2
1.3.3
1.3.3.1
1.3.3.2
1.4
1.4.1
1.4.2
1.4.2.1
1.4.2.3
1.4.2.4
1.4.2.5
1.5
1.5.1
1.5.2
1.5.3

SCOPE ............................................................. 1-1
OVERVIEW ........................................................ 1-1
General Description ...................................... _______ 1-1
Physical Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
Versions of DHUll ............................................. 1-2
Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-4
Connections ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-4
SPECIFICATION .................................................. 1-5
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-5
Electrical Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-5
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-6
Data Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-6
Throughput. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-6
INTERFACES ...................................................... 1-7
System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
Serial Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
Interface Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
Serial Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-8
Line Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9
Line Transmitters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9
Speed/Distance Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-10
FUNCTIONAL DESCRIPTION ..................................... 1-10
Control Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-10
UNIBUS Interface. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. 1-10
Serial Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-12

CHAPTER 2

INSTALLATION

2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.5.1
2.3.5.2
2.3.5.3
2.4
2.4.1
2.4.2
2.5
2.6
2.6.1
2.6.2

SCOPE .............................................................. 2-1
DHUII-M ........ , .................................................. 2-1
MODULE CONFIGURATION ....................................... 2-3
Address Switches ................................................. 2-3
Vector Switches .................................................. 2-4
Bus Request (BR) Interrupt-Priority Switches ........................ 2-4
Steal Grant ...................................................... 2-5
Backplane ....................................................... 2-5
Connection to the UNIBUS ................................... 2-5
Bus Grant Continuity Cards ................................... 2-6
NPG Continuity ............................................. 2-6
PRIORITY SELECTION ............................................. 2-6
Non-Processor Request. ........................................... 2-6
Bus Request ..................................................... 2-7
MODULE INSTALLATION .......................................... 2-7
CABLES AND CONNECTORS ...................................... 2-9
Distribution Panel ................................................ 2-9
Staggered-Loopback Test Connector ................................ 2-14

1 Ii ') ')

~ ."T.~.~

iii

2.6.3
2.6.4
2.6.5
2.6.6
2.7
2.7.1
2.7.2
2.8
2.8.1
2.8.1.1
2.8.2
2.8.2.1
2.8.2.2
2.8.2.3
2.8.3

Line-Loopback Test Connector H325 ............................... 2-15
Null Modem Cables .............................................. 2-15
Modem Cables ................................................... 2-1 7
Data-Rate to Cable-Length Relationships ............................ 2-18
MULTIPLE COMMUNICATIONS OPTIONS ......................... 2-18
Floating Device-Addresses ......................................... 2-18
Floating Vectors .................................................. 2-22
INSTALLATION TESTING .......................................... 2-24
PDP-II Installation Tests ......................................... 2-24
PDP-II Installation Test Sequence ............................. 2-25
VAX Installation Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
EVDAI Standalone Diagnostic ................................ 2-25
EVDAH On-Line Diagnostic .................................. 2-25
VAX/VMS System Exerciser UETP ........................... 2-26
VAX Installation Test Sequence ................................... 2-26

CHAPTER 3

PROGRAMMING

3.1
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.2.4
3.2.2.5
3.2.2.6
3.2.2.7
3.2.2.8
3.2.2.9
3.2.2.10
3.2.2.11
3.3
3.3.1
3.3.2
3.3.3
3.3.3.1
3.3.3.2
3.3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
3.3.10
3.3.10.1
3.3.10.2
3.3.10.3
3.3.10.4
3.4
3.4.1
3.4.2

SCOPE .............................................................
REGISTERS .......................................................
Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Register Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Base Control-and-Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . ..
Receive Buffer (RBUF) ..................... ; . . . . . . . . . . . . . . ..
Receive Timer Register (RXTIMER). . . . . . . . . . . . . . . . . . . . . . . . ..
Line Parameter Register (LPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
FIFO Data Register (FIFODATA) ...........................
FIFO Size Register (FIFO SIZE) . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Line Status Register ( STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Line Control Register (LNCTRL) .............................
Transmit Buffer Address Register Number 1 (TBUFFADl) ......
Transmit Buffer Address Register Number 2 (TBUFFAD2). . . . ..
Transmit DMA Buffer Counter (TBUFFCT). . . . . . . . . . . . . . . . . ..
PROGRAMMING FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Transmitting .................. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Programmed Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ..
Methods of Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Receiving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Interrupt Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Auto XON and XOFF ..........................................
Error Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Modem Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Maintenance Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Diagnostic Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Self-Test Diagnostic Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Interpretation of Self-Test Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Skipping Self-Test. ....... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Background Monitor Program (BMP). . . . . . . . . . . . . . . . . . . . . . . . ..
PROGRAMMING EXAMPLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Resetting the DHlJll ..................... , ..... , , ....... , . . . . . ..
Configuration .... , ..... , .. - - . , , ... , , . , ....... , . , .. , .... , , . , , . . ..

3-1
3-1
3-1
3-2
3-3
3-6
3-7
3-8
3-10
3-11
3-12
3-13
3-16
3-16
3-17
3-18
3-18
3-19
3-19
3-19
3-19
3-20
3-20
3-20
3-21
3-22
3-22
3-23
3-23
3-23
3-23
3-25
3-25
3-26
3-26
3-27

3.4.3
3.4.3.1
3.4.3.2
3.4.3.3
3.4.4
3.4.5
3.4.6
3.4.7

Transmitting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Programmed Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DMA Transfer. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Aborting a Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Receiving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Auto XON and XOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Checking Diagnostic Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Modem Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-27
3-27
3-28
3-29
3-29
3-30
3-31
3-32

CHAPTER 4

MAINTENANCE

A 1

SCOPE ............................................................. 4-1
MAINTENANCE STRATEGY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
Preventive Maintenance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
Corrective Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
INTERNAL DIAGNOSTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
Self-Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
Background Monitor Program (BMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
XXDP+ Diagnostics ................................................. 4-3
ZDHU??, ZDHV??, ZDHW??, and ZDHX?? ...................... 4-3
Functions of ZDHU?? ...................................... 4-4
Functions of ZDHV?? ................................. "...... 4-4
Functions of ZD HW?? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
Functions of ZD HX?? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
DECX/ll Exerciser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
PDP-II DiagIlostic Services Summaf'j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
Loading the Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
Four Steps to Run a DRS Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
DRS Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-6
Command Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-7
Control Characters Supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-8
Example Printouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-8
VAX DIAGNOSTICS ............................................... 4-10
EVDAI Standalone Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-10
Running the EVDAI Standalone Diagnostic. . . . . . . . . . . . . . . . . . . . . . .. 4-10
Starting Up ............................................... ", 4-12
Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-12
Event Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-13
Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-13
Error Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-14
EVDAH On-Line Diagnostic ..................................... 4-14
Running the EVD AH On-Line Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . .. 4-15
Starting Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-16
Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1 7
Event Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-18
Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-19
Error Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-19
VAX Test Sequence ............................................. 4-19
EVDAH Test Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-19
EVDAI Test Sequence ...................................... 4-20
FIELD REPLACEABLE UNITS (FRUs) ............................. 4-20

..,..~

4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.1.3
4.4.1.4
4.4.2
4.5
4.5.1
4.5.2
4.5.3
4.5.3.1
4.5.4
4.5.5
4.6
4.6.1
4.6.2
4.6.2.1
4.6.2.2
4.6.2.3
4.6.2.4
4.6.2.5
4.6.3
4.6.4
4.6.4.1
4.6.4.2
4.6.4.3
4.6.4.4
4.6.4.5
4.6.5
4.6.5.1
4.6.5.2
4.7

APPENDIX A GLOSSARY OF TERMS
A.1
A.2

SCOPE ............................................................. A-I
GLOSSARY ........................................................ A-2

APPENDIX B MODEM CONTROL
B.1
B.2
B.2.1

SCOPE ............................................................. B-1
MODEM CONTROL ................................................ B-1
Example of Auto-Answer Modem Control for the PSTN .............. B-2

FIGURES
Figure No.

Title

Page

1-1
1-2
1-3
1-4
1-5
2-1
2-2
2-3
2-4
2-5
2-6
2-7
3-1
3-2
4-1
4-2
4-3
4-4

M3105 Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Example of DHU11 Configuration. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . ....
DHU11 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Serial Character Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DHU11 Functional Block. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . .. . . . . . ..
Switch Locations ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DHUll Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
H3029 Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
H3029 Circuit Diagram ..............................................
Staggered-Loopback Circuit of H3029 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Line-Loopback Test Connector ........................................
Null Modem Cable Connections. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . .. . . . ..
Register Coding ...... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Diagnostic/Status Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Troubleshooting Connection Diagram ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Troubleshooting Flowchart for XXDP+ Diagnostics .....................
Example of Channel Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
EVDAI Troubleshooting Flowchart ....................................

1-3
1-4
1-5
1-9
1-11
2-2
2-8
2-10
2-11
2-14
2-15
2-17
3-3
3-24
4-2
4-11
4-20
4-21

TABLES
Table No.

Title

1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3

DHUll Data Rates. ... . . . . . . . . .. .. .. .. .... .. ... .. . .. . . . . ..... . ...... 1-6
EIA/CCITT Signal Relationships. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-8
Cabinet Kits for the DHUll .......................................... 2-2
Device Address Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
Vector Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-4
Interrupt-Priority Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-4
Backplane Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
H3029 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-12
Data-Rate/ Cable-Length Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-18
Floating Device-Address Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-18
Floating-Vector Address Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-22
DHUll Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
Data Rates .... , ...... , .. , , ... , .. , , , ..... , . , ... , ... , , ............ , . .. 3-10
DHUll Self-Test Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-24
Modem Control Leads ............................................... B- 2

B-1

Page

PREFACE
This document describes the DHUll and its installation requirements. It contains information on userlevel maintenance. A substantial programming chapter and a glossary are included.
This manual was written primarily for the DHUll user. However, information concerning such items as
option installation and checkout is intended for qualified Field Service personnel.
The manual is organized into four chapters plus appendices.
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Appendix .L~
Appendix B

Introduction
Installation
Programming
Maintenance
Glossary of Terms
Modem Control

The following is a list of related titles.
Document

Number

Communications Mini-Reference Guide
Terminals and Communications Handbook
DHUll Technical Manual
DHUll Maintenance Card
DHUll Field Maintenance Print Set

EK-CMINI-RM
EB-20752-20
EK-DHUII-TM
EK-DHUII-MC
MP-01794-01

vii

CHAPTER 1
INTRODUCTION

1.1 SCOPE
Chapter 1 provides general information and specifications. It describes how the module can be configured,
and how it interfaces with the system bus and the serial data lines. Physical and functional descriptions are
also included.
1.2 OVERVIEW
1.2.1 General Description
The DHUl1 option is an asynchronous multiplexer which provides 16 full-duplex, asynchronous, serial
data channels on UNIBUS systems. The option can be used in many applications. These include data
concentration, terminal interfacing, and cluster controlling.
The main features of the DHUll are as follows.

•

Sixteen full-duplex asynchronous data channels

•

A 25 6-entry first-in-first-out (FIFO) butTer for received characters, dataset status changes, and
diagnostic information

•

DMA or programmed transfers on transmit. Each channel has a 64-byte FIFO for output data

•

Programmable delay-timer for receive interrupts

•
•

RS-423-A/V.I0/X.26 and RS-232-C/V.28 compatible
Full-duplex point-to-point or auto-answer dial-up operation

•

Programmable split speed per line

•
•

Total module throughput of 15 000 characters per second
Automatic flow control of transmitted and received data

•

Self-test and background monitor diagnostics
Programmable test facilities

.A.ll communications functions are programmable

1-1

Enough modem control is provided on all 16 channels to allow auto-answer dial-up operation over the
public switched telephone network (PSTN). The DHUll can also be used for point-to-point operation
over private lines. Modem control is implemented by software in the host.
The module provides D MA or programmed transfers from the host system to the serial lines via sixteen
64-byte FIFO buffers (one per channel). A common 256-character FIFO buffer is provided for data
received from the serial lines.
By using microcomputers (referred to as PROC I and PROC 2 in this manual) the DHUII releases the
host system from many of the data-handling tasks.
One 8051 microcomputer controls DMA transmissions from the host system to the DHUII. A second
8051 controls eight DUARTs which carry out the serial/parallel and parallel/serial conversion of data.
The DHUII carries ROM-based diagnostics which are executed independently of the host. A full range
of diagnostic programs is also available for both PDP-II and VAX-II systems.
A green LED gives the GO/NO-GO status of the module. More detailed diagnostic information is also
made available to the host system via the received-character FIFO. Loopback test connectors are
supplied for use with the system-based diagnostics.
I/O addresses, interrupt vectors, and interrupt priority for the module are selected on three switchpacks.
All other DHUII functions and configurations are programmable.
To prevent loss of data at high throughput levels, the DHUII can be programmed for automatic flow
control using XON and XOFF characters.
1.2.2 Physical Description
The D HU II consists of a module kit D HU 11-M, and one of several cabkits. The D HU 11-M consists of:
•
•

A hex-height module (M3105)
The DHUll Interface User Guide (EK-DHUII-UG).

Figure I-I shows major features of the module. Its dimensions are 21.4 cm X 39.9 cm (8.4 inches X 15.7
inches). The module is connected to the backplane via connectors A to F. J I to J 4 are connected to the
communications lines via BC05 L cables, and distribution panels.

1.2.3 Versions of DHUll
To facilitate installation in different system packages, and to allow installation in unshielded cabinets, the
DHUll can be supplied in four upgrade-kit versions. All versions consist of the DHUII-M and cabkit.
The four cabkits are:
CK-DHUII-Al
CK-DHUII-AD
CK-DHUII-AE
CK-DHUII-AF

For unshielded cabinets - (19-inch rack mount)
For general-purpose expansion cabinets
For VAX-llj730 and VAX-llj750 kernel systems
For VAX-llj725 systems

Cabkit details are given in Chapter 2, Installation.

1-2

DIAGNOSTICS PASSED LED (GREEN)
Cf-IANS 0 TO 3

CHANS 4 TO 7

BERG Jl

BERGJ2

-----]
c.
[

l§I

CHANS 12 TO 1 5

CHANS 8 TO 11

BERG J3

-----

[----]
E182
__
2~i81 DUART 0

----J
.

[181

L~~681 DUART 1

E114
~;;:]
2681 DUART 2

E150
2681 DUART 3

Ell
2681 DUART 6

E149

L_..:~~~_J

-;]~

E54
2681 DUAFlT 4-

E83
2681 DUART 5

El0
2681 DUART 7

CRYSTAL
CRYSTAL
3.68964 MHZ~ ~ 24 MHz

r-------, [ ]

BERGJ.

I
I

Ell1
8051 PROC1

r----·---,
E79
8051 PROC2

I
:

E51
EPROM

I
:

1.. _ _ _ _ _ _ .J

IF INSTALLED

IF INSTAL.LED

I
F

DEVICE ADDRESS

n of--J1-

BR PRIORllY

Figure 1-1

M3105 Module

E60

INTERRUPT
VECTOR

JLA

1.2.4 Configurations
Figure 1-2 shows some possible DHU11 configurations. Any or all of the data channels can be connected
to a terminal or to a data-communications line.

HOST

PROCESSOR~~__~~____~_______
U_N_IB_U_S____________________~

DEVICE

1--------

DEVICE

- -I
I
M3105 MODULE
I
t +I + t
f I
I

I
I

116 DATA CHANNELS

I
L ~U2.2 ~~N_

I
I

LOCAL

EQUIPMENT

I
TELEPHONE OR
MODEM

•

-I

A-

REMOTE

MODEM

~ TERMINAL

MODEM

DATA COMMS

" - - - - - ' LI NE

~_---ill---~ LOCAL

REMOTE
EQUIPMENT

TERMINAL

I
MODEM

TELEPHONE OR
---;r
-DATA COMMS

~------' LI NE

REMOTE
DHU11

_ _ _ -.J

REMOTE
PROCESSOR ~____________________________U_N_IB_U_S____________________________~

Figure 1-2

Example of DHU11 Configuration

1.2.5 Connections
Figure 1-3 shows an example ofDHU11 connections. These include normal operating connections and
test connections. More detail is shown in Figure 2-2 in Chapter 2. Installation.

1-4

BACK OF
H3029
DISTRIBUTION
PANEL

CHANNELS
8 TO 15
r'
: "

, ;i :; I)
,I

"
,I

tJ ,,-

i::jlJl-'~3""D
~

H325
LI N E LOOPBACK
TEST CONNECTOR

NOTE:
STAGGERED lOOPBACK CONNECTORS
ARE NOT POLARIZED
BC05L·xx CASLES CAN BE INSTALLED
E;ITHER WAY AROUND IN ,J10/,J1 1

~~ -gg/

~~-

- ~-~\

:: n,~ C-".,.I1.'--I\,J~RT,n

'1-

1,1,

~ I~III--

- \/

L-J

j 0
----::~~~~--.:==~
~:--=-=----_-.L / ------===~LJ j 0
RED LINE

25-PIN D-TYPE
CONNECTORS

CHANS 12 TO 15

Figure 1-3

1.3

DHU11 Connections

SPECIFICATION

1.3.1

Environmental Conditions
•
•
•

1.3.2

Storage temperature: -40°C to 66°C (-40°F to 151°F)
Operating temperature: SoC to SO°C (41°F to 122°F)
Relative humidity: 10% to 95% non-condensing

Electrical Requirements

•
•
•

+S V dc + or - 5% at 6 A (typical)
+15 V dc + or - 4% at 400 rnA (typical)
-15 V dc + or - 4% at 400 rnA (typical)

Loads applied to the UNIBUS are as follows.

•

UNIBUS ac loads
UNIBUS de loads

2.2 ac loads
1.0 dc load

1-5

M3105
MODULE
(J)

CHANS 4 TO 7

:::::>

CHANS 0 TO 3

RED LINE

CHANNELS
o TO 7

....

NORMAL CONNECTION
TEST CONNECTION

1.3.3

Performance

1.3.3.1 Data Rates - Each channel can be programmed to operate at one of a number of speeds. If
needed, the transmission and reception rates can be different (split speed). Table 1-1 shows the data rates
which are possible.
The 16 serial channels are implemented with 8 DUARTs. Channels are paired as follows: 0/1, 2/3, 4/5,
6/7,8/9,10/11,12/13,14/15. Because of the method of data-rate generation within the DUARTs, all
transmit and receive rates for a DUART channel-pair must be in the same group (A or B).

Table 1-1

;~~

DUUll Data Rates

Speed
(Bits/s)

Groups

50
75
110
134.5
150
300
600
1200
1 800
2000
2400
4800
7200
9600
19200
38400

A
B
A and B
A and B
B
A andB
AandB
AandB
B
B
A and B
AandB
A
A and B
B
A

Data-rate selection is covered in Chapter 3 (Programming).

1.3.3.2 Throughput - The approximate maximum throughput figures for DHU11 are quoted below.
•
•
•

Transmit (per channel)
Receive (per channel)
Total aggregate throughput

1 000 chars/ s
4 000 chars/ s *
15 000 chars/ s

Several factors limit DHU11 throughput. Such factors may apply to transmission only, or to both
transmission and reception.
a.

The ratio between a channel's data-signaling rate and the number of bits in a character,
(bits/s)/(bits/char), limits the maximum throughput in both the Transmit and Receive
directions. The following example shows the relationships between two selected data rates and
character formats. In each case, a start bit, a parity bit, and one stop bit are assumed.

* Seven-bit character with start bit, parity bit and one stop bit.
1-6

Data Rate
(Bits/s)

5-Bit Characters
(Chars/s)

7 -Bit Characters
(Charsls)

38400
4800

4800
600

3840
480

The Transmit firmware can supply a maximum of 1 000 charsl s to any channel. Therefore,
unless further limited by factor a or c, the maximum Transmit throughput per channel is 1 000
chars/s.
r'''
.............. l1n',......,t'''n'' f1 .......... U7.., ..0 ,....on ],..,n ....11o .., t ...... t.., 1 ...... f 1,\ (\(\(\ .-"'],"'''''' /" T Tn 10"" l'"",1to....1 h'<7 f..,,....t ........ .., t],';"
'-'"'v.J..J..1.J..1.1IU..1l..J. ....... aL.lvJ..1.Ll .l.J.J. J.J..1. VY u..l "" ....... ".1..1. .lJ.U.J..I.u.J.", u.. "'V"'U.I. V.I. ~..J v v v \"I.I..J.u..1.. 0/..:J. ""'" .1..1..1.,",00 .1..1..1..1..1..1. ... """'" U J .I.U""'LV.l
'-.1..1..1.0

u..,

is the maximum total throughput for the opiion.
NOTES
15000 characters per second is the sum of both
transmitted and received characters on all channels.
This throughput could support continuous transmission or reception on all channels at 9 600
bitsl s, or continuous transmission and reception
on all channels at 4 800 bitsl s.
9 600 bitsl s is equivalent to 1 000 characters * per
second. If a higher data rate is selected for a
Transmit line, the duration of characters will be
reduced but there win be gaps in transmission.
INTERFACES

1.4

1.4.1· System Bus Interface
The M31 05 module can be connected directly to the system-unit (backplane). UNIBUS signals, together
with pin details, are listed in Table 2-5 (in Chapter 2, Installation).
1.4.2

Serial Interfaces

1.4.2.1 Interface Standards - The DHUll provides interface signals which conform to a subset of the
EINCCITT standard RS-232-C/V.24. The electrical characteristics conform to EWCCITT standards
RS-232-C/V.28 and RS-423-A (unbalanced interface). The interface is compatible with X.26/V.I0
standards but does not comply with the slew-rate requirements.
Connections to the external equipment are via 25-pin male subminiature D-type connectors.
By means of suitable cables and connectors (not supplied or supported by DI G ITAL) the channels can be
made compatible with the following.
1.
2.

Subset of EIA interchange standard RS-449
EIA electrical standard RS-422 (balanced)

T~hlp.
~h()w~
R~-?~?-r/v
?4/R~-44Q
~lp-n~l rp.1Ml()n~hln~ ~nc1 nln ~()nnp.~ti()n~ for the
2.:i-nin
m~le
------ 1-?
- ----.. ------ -, ._--,--. -- --0-----------------.--,----.--------------------------r---------

subminiature D-type connectors.

* Seven-bit character with start bit, parity bit and one stop bit.
1-7

Table 1-2

EIA/CCITT Signal Relationships
D-Type
Pin

Signal
Name

RS .. 232-C Circuit
Circuit
CCITT V.24 RS-449

(GND)

Signal Ground

(SIG GND)

102

Transmit Data

(TXD)

103

Receive Data

(RXD)

104

Request to Send

(RTS)

105

Clear to Send

(CTS)

106

Data Set Ready

(DSR)

107

Data Terminal Ready

(DTR)

108/2

(RI)

125

(DCD)

8!:

109

Protective Ground

Ring Indicator
Data Carrier Detect

NOTE
The backward channels listed below are not
supported. However, by using another channel
for this function, and by connecting a suitable
cable (H1200 or H1201, for example), backwardchannel operation is possible.
Circuit No.

118
120
119
121
122

Function
Transmitted backward-channel data
Transmit backward-channel line signal
Received backward-channel data
Backward channel ready
Backward-channel-received line-signal detector

1.4.2.2 Serial Data Format - Serial characters are made up of an encoded sequence of bits which are
enclosed between a start and a stop signal. The start signal is always 1 bit long but the stop signal is
programmable to 1, 1.5, or 2 bits. The duration of a bit is dependent on the selected data rate.
Character codes may be 5, 6, 7, or 8 bits long, optionally followed by a parity bit. Parity can be
programmed as even, odd, or no parity.
On serial data channels controlled via the DHUl1, the data line is held marking when inactive. Transfer of
each character begins with a start bit (space) and ends with one or more stop bits (mark).

1-8

Figure 1-4 shows the reception of an 8-bit character with parity. The Least-Significant Bit (LSB) of the
character code is transmitted first. If another character is not ready for transmission, the line will stay
marking. The figure shows 1, 1.5, and 2 stop bits.

NOTE
This description applies to signals at the DUART
pins. Signals measured on the interchange circuits
will have the opposite polarity to those shown.
The data-rate clock, which samples the serial data, is 16 times the progra..'11med data rate ....<\.rrows show
when the bits are tested for polarity.
STOP BIT(S)

8 DATA BITS
(~

j
MARK

______________

~A~

________________

j j

+~-+-_

,;J---

,-0. . --

SPACE -

START BIT

LSB FIRST

MSB LAST

PARITY BIT
RD1 "144

Figure 1-4

Serial Character Format

The D HU 11 allows the following serial character formats.
•
•
•

Characters of 5, 6, 7, or 8 bits with or without parity and with 1 stop bit
Characters of 5 bits with or without parity and with 1.5 stop bits
Characters of 6, 7, or 8 bits with or without parity and with 2 stop bits

1.4.2.3 Line Receivers- The serial line receivers used in this module are 9637 AC or equivalent. They
convert the EIA input signals to TTL levels suitable for the DUARTs.
Signals are inverted by the receivers.
1.4.2.4 Line Transmitters- The serial line transmitters used in this module are 9636AC or equivalent.
They convert TTL level signals from the DUARTs to EIA levels on the data lines.
Signals are inverted by the transmitters.

1-9

1.4.2.5 Speed/Distance Considerations - The maximum data rate which can be used on a line
depends upon a number of factors. These are:
1.
2.
3.
4.

The characteristics of the line transmitters and receivers
The characteristics of the serial cable
The length of the cable
Noise (interference) which affects the line.

A 'speed against distance' table for typical conditions is provided in Section 2.6.6.
1.5

FUNCTIONAL DESCRIPTION

1.5.1 Control Function
In the DHUll module (Figure 1-5), data is transferred to and from the serial interface by three methods:
1.

By D MA. Blocks of data are transferred from system memory to the serial interface. D MA data
is routed via the UNIBUS data transceivers, the TX FIFO (for the addressed channel), and
PROC2.

In the programmed transfer mode, characters are transferred from the host to the serial
interface. The route for characters is via the UNIBUS data transceivers, the TX FIFO (for the
addressed channel), and PROC2.

Received characters are transferred from the serial interface to the host via PROC2, the RX
FIFO, and the UNIBUS data transceivers.

At the center of the control section is a 1K-word RAM. By writing control words or bytes to registers in the
RAM, the host can configure and command the module. The host can also write data for transmission on
the serial lines, to TX FIFOs (one per" channel) in the RAM. TX FIFO addresses are provided by TX
FIFO control.
Two microcomputers (PROC 1 and PROC 2), which have associated microprogram ROMs, scan the
RAM and the FIFO logic in order to detect a new configuration, or data to be transferred. They also write
status information to the RAM, which can then be read by the host.
PROC 2 configures the DUARTs, and transfers Transmit and Receive data between the FIFOs and the
DUARTs. Received characters are written to the RX FIFO and transmit characters are read from the TX
FIFO.
Among other functions, PROC 1 controls DMA transfers to the TX FIFO. PROC 1 keeps track ofDMA
addresses and character count, and reports to the host when the block has been transferred.
Both microcomputers execute background diagnostics when not busy with other tasks.
1.5.2 UNIBUS Interface
The DHUll module is programmed by the host via a number of I/O registers. When the DHUll
recognizes a valid address, it allows the host to access the FIFOs and the registers. When TX or RX
FIFOs are being accessed, FIFO controllers provide the RAM addresses.
Module address switches are connected to a comparator which monitors the address transceivers. When
an I/O address from the host matches the address on the switches, the DHUll responds to the host.

1-10

UNIBUS
INTERFACE

CONTROL
SECTION

SERIAL
INTERFACES

DMA REQ

PROC1
DMA CONTROL

r------1---,

INT
.......- - - ~

I
I
I
_ I,--"
')L ' \

:;/

DMA ADDRESSES

CONTROL
TRANSCEIVERS 1 ' - - - -....

DECODERS

INTERNAL
CONTROL
SIGNALS

BUS PRIORITY
SELECTION
DMAAND
INTERRUPT
CONTROLLERS

i-;;-HURAM

/'~CONTROL

(f)

::J

III

1-0
I
1-0
1-0

TX FIFO
CONTROL

SIGNALS
AND
REGISTER
"C~~'7 ADDRESSES

::J

,J.....

~;s ~
'IV
:
I

ADDRESS
AND
"DATA
1',~Ir-------~--~
TRANSCEIVERS
I

,--"

DATA

RX FIFO
CONTROL

,ADDRESS
./ COMPARATOR

A
V'/~------------------~

TX FIFO ADDR

DATA AND CONFIG

rA, ' - - - - - - - - - -

to..

RX FIFO ADDR

" I

VECTOH AND
ADDRESS
SWITCHES

TX AND RX
FIFOs
PROCs
1 AND2
COMMON
RAM AREA

LINE
INTERFACE

1
SERIAL
CHANNELS

I
I
I

.. I

'-- _ _ _ _ _ ...J

'-V~~__,~~~ '~r--------I--·--~

/"11

CONTROL
REGISTERS

-1
I

.t.

DATA
AND
CONFIG

I
I
I

PROC2
DUART CONTROL

r----'

I 4K
ROM JI
L
____

R017]3

Figure 1-5

DHUll Functional Block

Vector address switches are indirectly connected to the data transceivers. These allow the DHU11 to
supply one of two interrupt vectors (transmit or receive) to the host during an interrupt acknowledge
sequence.
UNIBUS control signals and register addresses are decoded to generate internal control signals. DMA
and interrupt transactions are initiated by control signals from the DHU11.
1.5.3 Serial Interfaces
Sixteen full-duplex serial interfaces are provided by eight DUARTs. These ICs are configured by
PROC2 as instructed by the host. They carry out the serial/parallel and parallel/serial conversion.

The status of modem control lines for each channel is polled by PROC 2. If programmed to do so, the
DHU11 will report changes of modem status to the host. Such reports are made via the RX FIFO and the
device registers.

1-12

CHAPTER 2
INSTALLATION
2.1 SCOPE
This chapter contains information on how to prepare and install the D HU 11 option. It contains sections
on the following.

•
•
•

•
•
•
•

The selection of vectors and device addresses
The selection of interrupt-priority levels
Rules for backplane positioning
Recommended cables
Test connectors
The assignment of vectors and floating addresses
Testing after installation

2.2 DHUII-M
The DHUII-M may be installed in one of four cabinet kits.
The D HU 11-M consists of:

Part Number

Description

M3105
EK-DHUII-UG

DHUll module
User Guide

Quantity
1
1

Table 2-1 lists the parts for each cabinet kit.
Check that you have received all the items on the packing list. Examine all parts for physical damage.
Report damaged or missing items to the shipper and the DIGITAL representative.

CAUTION
The M3105 module is supplied in a protective
sleeve. Do not remove the sleeve until you are
about to install the module. Protect the module
from static during installation.

2-1

Table 2-1

Cabinet Kits for the DUUll

Cabinet Kit
Number

Description

CK-DHUII-AE
CK-DHUII-Al
CK-DHUII-AD
CK-DHUII-AF

VAX-l 1/730 and VAX-l 1/750 kernel systems------·
Unshielded cabinet - - - - - - - - - - - - - - - .
General-purpose expansion cabinet------.-,
VAX-llj725 s y s t e m - - - - - - - - - _

Contains:
Single-line loopback connector
8-line 25-way distribution panel
40-way ribbon cable
40-way ribbon cable
40-way ribbon cable
19-inch frame and fastenings

H325
H3029
BC05L-03
BC05L-07
BC05L-IO
H9544-SJ

I
1

4
1

NOTE
BC05L-xx cables are 3 ft, 7 ft, and 10 ft as
indicated by xx.

BR LEVELS
5 AND 6
SELECTION

STEAL
GRANT
SELECTION

~---'

' - - ' ' - - - - - - - ' \. ' - - - - - - - '

X = 0 FOR RX INT
X = 1 FOR TX INT

\ \

I 1 I 2 I 3 I 4 I 5 I 6 \1 x
t t t tt t t
MSB

DEVICE ADDRESS

Figure 2-1

LSB

Switch Locations

2-2

1
2

MSB

VECTOR

LSB

2.3 MODULE CONFIGURATION
Figure 2-1 shows the location and function of switchpacks which configure device addresses, vectors, and
interrupt priority. See the previous CAUTION (in Section 2.2) before configuring the module.
2.3.1 Address Switches
The device address for the DHUll is set on switchpack E173. Table 2-2 explains the relationship
between device addresses and switch positions.
Table 2-2

Device Address Selection Guide
IC"D
L';)D

iviSB

1211111019181716151 4

SWITCHES

E173

SWITCH
NUMBER

NOTE:
SWITCH E173-1 0
MUST BE OFF

DEVICE
ADDRESS

OFF
OFF
OFF OFF

760020
760040
760060

OFF

a 1"\ 1 1"\1"\

IVVIVV

OFF

760200

OFF OFF

760300

OFF
OFF

760400
OFF

760500

OFF OFF

760600

OFF OFF OFF

760700

OFF

761000

OFF

762000

OFF OFF

763000

OFF

IOFF

I I I II I I I I

764000
770000

OFF = SWITCH OPEN TO RESPOND TO A LOGICAL 1
RD1744

2-3

2.3.2 Vector Switches
During an interrupt-acknowledge sequence, the DHUll returns a 9-bit interrupt vector to the host. The
six high-order bits of this vector are derived from E60-S1 to S6. Table 2-3 explains how switch positions
relate to the vector.
Table 2-3

Vector Selection Guide
LSB

MSB

I7 I6 I5 I4 I 3

SWITCHES

1/0

~ DATA BIT 2 REFLECTS
THE STATE OF TXIRQ.H WHICH
INDICATES:

SWITCH
NUMBER

E60

NOTE:
SWITCH E60- 7 TO 10
MUST BE OFF

OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

OFF

o RX INTERRUPT

300
310
320
330
340
350
360
370
400

OFF
OFF
OFF OFF
OFF
OFF
OFF
OFF OFF
OFF OFF OFF

OFF

~,;:. \,

1 TXINTERRUPT

VECTOR

OFF

500

OFF OFF

600

OFF OFF OFF

700

OFF = SWITCH OPEN TO PRODUCE A LOGICAL 1
AD1745

2.3.3 Bus Request (BR) Interrupt-Priority Switches
The M31 05 module can be switch-selected to interrupt at BR levels 5 or 6. Table 2-4 indicates how BR
levels are selected.
Table 2-4
BR Level

Interrupt-Priority Switches

State of Switchpack E121-S1 to S8
S5

OFF OFF OFF OFF ON

OFF OFF OFF OFF
2-4

2.3.4 Steal Grant
This facility is used to improve UNIBUS latency by 'stealing' a bus grant (BG) intended for a device
further along the priority chain. If a B-G is received while BNPR is asserted, passive release of the
UNIBUS will occur. Thus the device which raised the NPR will not be delayed.

Steal grant is enabled/disabled by E12l-S9 and S10 as follows.
S9 OFF, SlO ON
SlO OFF, S9 ON
2.3.5

steal grant disabled (default)
steal grant enabled

Backplane

2.3.5.1 Connection to the UNIBUS - The DHUll interfaces with the system via the UNIBUS. The
physical connection is made via the A, B, C, D, E, and F edge connectors on the module.

Backplane signals and pin designations are listed in Table 2-5.
Table 2-5

Backplane Connections

Signal

BUSAOO.L
BUSAOl.L
BUSA02.L
BUSA03.L
BUSA04.L

EH2
EHI
EFI
EV2
EU2

BPB.L

CSl

BUSDOO.L
BUSD01.L
BUSD02.L

CS2
CR2
CU2

BUSA05.L
BUSA06.L
BUSA07.L
BUSA08.L
BDSA09.L

EVI
EUI
EP2
EN2
ERI

BUSD03.L
BUSD04.L
BUSD05.L
BUSD06.L
BDSD07.L

CT2
CN2
CP2
CV2

BUSAlO.L
BUSAll.L
BUSA12.L
BUSA13.L
BUSA14.L

EPI
ELI
ECI
EK2
EKI

BUSD08.L
BUSD09.L
BUSDlO.L
BUSDl1.L
BUSD12.L

CL2
CK2
CJ2
CHI
CH2

BUSA15.L
BUSA16.L
BUSA17.L

ED2
EE2
EDI

BUSD13.L
BUSD14.L
BUSD15.L

CF2
CE2
CD2

BBSY.L
BDCLO.L
BG4IN.H
BGSIN.H
BG6IN.H

FDI
CNI
DS2
DP2
DM2

GROUND
GROUND
GROUND
GROUND
GROUND

BTl
CTI
DTI
ETI
FTI

BG7IN.H
BG40UT.H
BG50UT.H
BG60UT.H
BG70UT.H

DK2
DT2
DR2
DN2
DL2

GROUND
GROUND
GROUND
GROUND
GROUND

2-5

(""""-If")

,-,..LY..I....

AC2
BC2
CC2
DC2
EC2

Table 2-5

Backplane Connections (Cont)

Signal

BR4.L
BRS.L
BR6.L
BR7.L

DH2
DF2
DE2
DD2

GROUND
GROUND
NPGIN.H
NPGOUT.H

FC2
AT1
CAl
CB1

BUSCO.L
BUSC1.L
BINIT.L
BINTR.L
BMSYN.L
BNPR.L
BSACK.L
BSSYN.L

EJ2
EF2
DL1
FM1
EEl
FJ1
FT2
EJ1

+5 V
+5 V
+5 V
+5 V
+5 V
+5 V
+15 V
-15 V

AA2
BA2
CA2
DA2
EA2
FA2
CUI
FB2

2.3.5.2 Bus Grant Continuity Cards - Typical system-units into which the M31 05 module is installed
are DD 11-C (four slots) and DD 11-D (nine slots). For occupied slots, bus-grant continuity is provided by
the installed module. However, unused slots between the first slot and the terminator must have a busgrant card installed to extend the grant.
2.3.5.3 NPG Continuity - On unused SPC slots, NPG continuity is provided by a wire link between
backplane pins CAl and CBl.
NOTE
When installing the M3105 module in a slot, you
must remove this link from the slot If you later
remove the module, replace the link. See also
Section 2.3.5.2.
2.4 PRIORITY SELECTION
The D HU 11 uses BRS or BR6 to request interrupt service.
Non-processor request (NPR) priorities are determined by an option's position on the bus. The bus
position may be a compromise between NPR and interrupt-priority requirements. As a general rule, NPR
priorities should be considered first, and then interrupt requests.

2.4.1 Non-Processor Request
On systems with more than one DMA device there is a chance of bus-latency problems. To minimize this,
a device which will lose data if its NPRs are not serviced quickly should be placed nearer to the CPU than
a device which can wait longer.
DMA latency is unlikely to affect the DHU11. The worst effect would be to reduce device throughput.
Transmit data will not be lost.
If there is only one DMA device on the system, there is no DMA contention.

2-6

2.4.2 Bus Request
The DHU 11 is normally assigned BR level 5 . Requests are made on bus-request line BR5. An arbitrator
(usually in the host CPU) monitors the request lines. If the host CPU is not engaged in a higher-priority
task it grants the use of the bus to the device with the highest priority.
BR contention only occurs between devices with the same BR level. Within any priority group, priority is
decided by bus position. Devices with time-critical interrupts should be nearer the CPU, unless this
conflicts with NPR priority.
The final configuration can be tested by the appropriate system-exerciser diag..l1ostic. Some changes may
be needed for optimum performance.

2.5 MODULE INSTALLATION
Once you have defined the backplane position of the DHUll, you can install the module and check the
backplane with a testmeter.
NOTE
This checkout should be used by trained maintenance personnel only.
CAUTION
Switch off power beiore inserting or removing
modules. Be careful not to snag module components on the card guides or adjacent modules.
The M3105 is a fine-line-etch PCB. Handle it
carefully to avoid damaging the etch.
Take anti-static measures to protect the module.
1.

Remove the backplane NPG link between CAl and CBl.

Using Figures 2-2 and 1-3 as a guide, install the option.
Figure 2-2 shows how to install distribution panels in the H9544-SJ frame. This frame forms
part of the 19-in rack-mounting kit, CK-DHUII-Al, which is listed in Section 2.2.

Make sure that +5 V is present between AA2 and ground.

Make sure that + 15 V is present between CUI and ground.

Make sure that -15 V is present between FB2 and ground.

2-7

STAGGERED
LOOPBACK
CONNECTORS
PIN A

CHANNELS
BACK OF
H3029

8 TO 15

H325
LI N E LOOPBACK
TEST CONNECTOR

J3 CHANNELS 8 TO 11

... o
... o
.~

IV
I

D TYPE
CONNECTOR

...
~

8ERG
CONNECTOR

J2 CHANNELS 4 TO 7

Figure 2-2

..-....

DHUll Installation

<!
00

:,:)

z
:,:)

Jl CHANNELS 0 TO 3

NORMAL CONNECTION

TEST CON N ECTION

NOTE:
STAGGERED LOOPBACK CONNECTORS
ARE NOT POLARIZED
BC05L-xx CABLES CAN BE INSTALLED
EITHER WAY AROUND IN J10/J11

I/O PANEL FRAME
rvPE H 9544-SJ
(FOR 19-INCH RACK)

::.:::

(f)

~ If/

~"---

M3105
MODULE

RED LINE
TO A

CHANNELS 0 TO

2.6

CABLES AND CONNECTORS

2.6.1

Distribution Panel

Each H3029 distribution panel adapts two of the DHUll 's Berg * connectors to eight subminiature
D-type RS-232-C connectors. Noise filtering is provided on each pin of the RS-232-C connectors. This
reduces electromagnetic radiation from the cables, and provides the logic with some protection against
static discharge. Noise-filtering increases line capacitance by 850 pF.
Figure 2-3 shows the layout, and Figure 2-4 shows the circuit. There is no CCITT equivalent of EIA
circuit
--- - --- -AA
-- - {nrotective
,r - - -- - - '-'2:roundt To imolement this circuit. a ~ound strao must be installed between the
/'..L

...

H3029 and the systelTI cabinet. The O-ohm link WI (not installed at the factory) Cful then be installed to
connect this circuit, and removed to disconnect it, as needed.

NOTE
Staggered-loop back connectors are incorporated
in the H3029 distribution panels. The circuit,
which is shown separately in Figure 2-5, is the
same as the H3277 staggered-Ioopback connector.
Table 2-6 gives the pin/ signal relationships for two distribution panels. Information in parentheses applies
to channels 8 to 16.
The following is an example of ihe use of Table 2-6.
•

Signal TXDO is the Transmit Data line for channel O. Its CCITT circuit number is 103. It is
connected to J8 pin B on the H3029 for channels 0 to 7.

•

Signal TXD8 is the Transmit Data line for channel 8. Its CCITT circuit number is 103. It is
connected to J8 pin B on the H3029 for channels 8 to 15.

* Berg is a registered trademark of the Berg Corporation.
2-9

.,.._--/
:W1

VIEW AT REAR

STAGGERED LOOPBACK
TEST CONNECTORS

I
PIN 1

PIN 13

~EIGHT
D TYPE
CONNECTORS
(25 PIN)

Figure 2-3

H3029 Layout
2-10

JO
SIGNAL
GROUND
0/8
-_._
---------

IRANSMIT Q.~TA 0/8 _ __

J2
r-

~
!
!

----.'"
~

QATA TERM~~!\L READ~

!3ING INDIC~~~R 0/8 _ __

REQUEST TO SEND 2/10

~LEAR TO S~~p

•

0/8 _ _ __

-_._----------

DATA SET READY 2/10

CLEAR TO SEND 2/10

RING INDICATOR 2/10

DATA TERMINAL READY 2/10

.----

SIGNAL GROUND 4/12

TRANSMIT DATA 4/12

Q.. ~TA CARRIER DETECT 6/14

D iTA SET READY 6/14

-4

-----------

r--

RECEIVE DATA 4/12

DATA TERMINAL READY 4/12

RING INDICATOR 4/12

R ,QUEST TO SEND 6/14

CLEAR TO SEND 4/12

C :.EAR TO SEND 6/14

REQUEST TO SEND 4/12

R NG INDICATOR 6/14

D ~~TA TERMINAL READY 6/14

DATA SET READY 4/12

R :,CEIVE DATA 6/14

DATA CARRIER DETECT 4/12

-H

•

20
3

RECEIVE DATA 2/10

DATA CARRlEfl DETECT~

H.tJ

TRANSMIT DATA 2/10

T :lANSMIT DATA 6/14

SIGNAL GROUND 2/10

S IGNAL GROUND 6/18

L...-

'---

'------'

SIGNAL GROUND 1/9

;-f,RANSMIT DATA 1/9

----2..

J.
!l

,....--

DATA SET RE~DY 0/8 _ __

!3ECEIVE DA..!.~~ _ __

REQUEST TO SEND 0/8

,----

DATA CARRIER DETECT 2/10

r--...

RECEIVE DAT,ll, 1/9
D~TATERMIN~LREADY1/9

RING INDICATOR 1/9
~LEAR TO SE~ID 1/9

REQUEST TO SEND 1/9

DATA CARRIER DETECT 3/11

r---

SIGNAL GROUND 5/13

TRANSMIT DATA 5/13

D~!\TA CARRIER DETECT 7/15

RECEIVE DATA 5/13

DATA SET READY 7/15

3,.0

'-L

rt.N

REQUEST TO SEND 3/11

RING INDICATOR 5/13

RI:QUEST TO SEND 7/15

CLEAR TO SEND 3/11

CLEAR TO SEND 5/13

C I_EAR TO SEND 7/15

'lR

RING INDICATOR 3/11

3.t

REQUEST TO SEND 5/13

DATA TERMINAL READY 3/11

RECEIVE DATA 3/11

2
1.
1

•

DATA SET READY 3/11

DATA CARR!E.~_DETECT 1/9

TRANSMIT DATA 3/11

SIGNAL GROUND 3/11

V.Y

QATA SET RE~.DY 1/9

DATATERMINALREADY5/13

•

RING INDICATOR 7/15

D O\TA TERMINAL READY 7/15

RECEIVE DATA 7/15

DATA CARRIER DETECT

T RANSMIT DATA 7/15

S IGNAL GROUND 7/15

H3029 Circuit Diagram

---'

'---

r--o-~
I
Wl

'1----,

SS
6

-!i2

--1
2J.

DATA SET READY 5/13

1111 PROTI:CTIVE GROUND

Figure 2-4

Table 2-6

83029 Connections

Signal

Circuit
Number

J8 Pin
Number

SIG GND 0(8)
TXDO(8)
RXDO(8)
DTRO(8)
RIO(8)
CTSO(8)
RTSO(8)
DSRO(8)
DCDO(8)

102
103
104
108/2
125
106
105
107
109

A
B
C
D

SIG GND 1(9)
TXD1(9)
RXD1(9)
DTR1(9)
RI1(9)
CTS1(9)
RTS1(9)
DSR1(9)
DCD1(9)

102
103
104
108/2
125
106
105
107
109

DCD2(10)
DSR2(10)
RTS2(10)
CTS2(10)
RI2( 10)
DTR2(10)
RXD2(10)
TXD2(10)
SIG GND 2(10)

109
107
105
106
125
108/2
104
103
102

DCD3(l1)
DSR3(11)
RTS3(11)
CTS3(11)
RI3(11)
DTR3(l1)
RXD3(11)
TXD3(11)
SIG GND 3(11)

109
107
105
106
125
108/2
104
103
102

E
F
H

K
L

M
N
P
R
S
T

U
W
X

BB
CC
DD

EE
FF

HH
JJ

KK
LL
NN
pp
RR
SS
TT

UU
VV

2-12

Name

Transmit Data
Receive Data
Data Terminal Ready
Ring Indicator
Clear to Send
Request to Send
Data Set Ready
Data Carrier Detect

Table 2-6

H3029 Connections (Cont)

Signal

Circuit
Number

SIG GND 4(12)
TXD4(12)
RXD4(12)
DTR4(12)

102
103
104
108/2
125

Transmit Data
Receive Data
Data Terminal Ready
Ring Indicator

rI"T"'SA/1 " ' )

106

Clear to Send

RTS4(12)
DSR4(12)
DCD4(12)

105
107
109

H
K

Request to Send
Data Set Ready
Data Carrier Detect

SIG GND 5(13)
TXD5(13)
RXD5(13)
DTR5(13)
RI5(13)
CTS5(13)
RTS5(13)
DSR5(13)

102
103
104
108/2
125
106
105
107

RT4(12)
-- -,--/
L, 1

't~ 1,L

".f""'\"~/1 "''\

J8 Pin
Number
A

B
C
D

M
N
P
R
S
T

U
W

11\{\

.LJ\";.LJ.J~ I,))

IV,;?

DCD6(14)
DSR6(14)
RTS6(14)
CTS6(14)
RI6(14)
DTR6(14)
RXD6(14)
TXD6(14)
SIG GND 6(14)

109
107
105
106
125
108/2
104
103
102

DCD7(15)
DSR7(15)
RTS7(15)
CTS7(15)
RI7(15)
DTR7(15)
RXD7(15)
TXD7(15)
SIG GND 7(15)

109
107
105
106
125
108/2
104
103
102

Name

BB
CC

DD
EE
FF
HH
JJ

KK
LL
NN

SS
TT

UU
VV

2-13

2.6.2

Staggered-Loopback Test Connector

See Figure 2-5. Two staggered-Ioopback test connectors are built into the H3029 distribution panel for
use during diagnostic tests. Systems which do not use the H3029 will be supplied with a separate loopback
connector (H3277) which implements the loopback circuits of the H3029. Using these connectors, all
channels can be tested. A channel fault can be traced to one of two channels.
J11

J10
A

0
B

"
D
"
E

!?
E

I F
~

"
H
""
J
0

"
H
~

J
0
K
'-'

'-'

'"'
~

R
"

R
~

T
~

0
W
I

w
....,

I x

y
~

z
~

AA
0

~E
....,

FF
,..

IiH
....,
JJ
0
I5..K
....,

.r-.
....,

Hll

0
~K
~

';..L

NN
....,

N,..N

'-'

RR
'-'

~
uu
~

U"U

'{j'j

~
Figure 2-5

Staggered-Loopback Circuit of H3029

2-14

2.6.3 Line-Loopback Test Connector H325
This connector is shown in Figure 2-6. It can be used during diagnostic tests to trace a fault to a single
channel.
PIN

NAME

CCITT No.

NOT USED
NOT USED
1\11"'\,11('el"'\
1 '\IV 1 U.:1[;;U

NOT USED
NOT USED
103

TXD

104

RXD

105

RTS

106

CTS

109

DCD
NOT USED

107

DSR

108.2

DTR
RI

125

B
17
11

12
2
3

-I
W1

-I

.... .. .. ... .

•••..........

Ej
14

H325
DUV~I""AI

I' •

ADDA~I~CI\IIC~IT

~I"''''''''' ,....I'.'''"'.,.U~IY

..... I,. •

6
W1

W1 IS PERMANENTLY IN
FOR DHU11 TESTING

CONNECTIONS

RD,729

Figure 2-6

Line-Loopback Test Connector

2.6.4 Null Modem Cables
Null modem cables are used for local RS-232-C connection. Because of Federal Communications
Commission (FCC) regulations, the cable specifications for the United States and Canada are different
from those for non-FCC countries. Other countries may also have similar electromagnetic interference
T\ "".... +9",,1 ~eg.. la+~ .......... " DMr'
I "ee App
. . .e.... A~x L"1,
A r.!.l""'sa"",T\J a9"O .... " ....T a"'a" 1a'h.lo
(EM.J...J..J
.J..'-'IIRFI
. sh~elAeA "a'h.~""e+s ,.:>
for systems which conform to FCC requirements.
.l.

,",VJ..lUV.l.l

U.l

UV.l.l':> • .LJ.l.

. l . l . l u · u '"'

l.}J..l.l

2-15

.l.lU.l

,-,.lva

.I.]

.I.,", J..lVVY

J..l

V.I.,",

Recommended null modem cables are as follows.
1.

BC22D (for EMC/RFI shielded cabinets)
•

Round 6-conductor fully shielded cable to FCC specification

•

Subminiature 25-pin D-type female connector moulded on each end

•

Lengths available.
BC22D-10
BC22D-25
BC22D-35
BC22D-50
BC22D-75
BC22D-AO
BC22D-B5

- 3.1 m (10 ft)
- 7.62 m (25 ft)
- 10.72 m (35 ft)
- 15.24 m (50 ft)
- 22.9 m (75 ft)
- 30.48 m (100 ft)
- 76.2 m (250 ft).

BC03M
•

Round 6-conductor (three twisted pairs), each pair shielded

•

Cables over 30.48 m (100 ft) have a 25-pin subminiature D-type female connector at one
end. The other end is unterrninated, for passing through a conduit.

•

Cables 30.48 m (100 ft) and less have a 25-pin subminiature D-type female connector at
each end.

•

Lengths available.
BC03M-25
BC03M-AO
BC03M-B5
BC03M-EO
BC03M-LO

- 7.62 m (25 ft)
- 30.48 m (100 ft)
- 76.2 m (250 ft)
- 152.4 m (500 ft)
- 304.8 m (1000 ft).

BC22A

•

Round 6-conductor cable

•
•

Subminiature 25-pin D-type female connector moulded at each end
Lengths available.
BC22A-10 BC22A-25 -

3.1 m (10 ft)
7.62 m (25 ft).

Cables of groups 1, 2, and 3 are all connected as in Figure 2-7. The cables are not polarized. They can be
connected either way round.

2-16

PIN
NUMBERS

1 0

2 0
3 0
7 0
6 0

20 0

PROTECTIVE GROUND

TRANSM!TTED DATA

RECEIVED DATA

o1
03

RECEIVED DATA

TRANSMITTED DATA

o 2

SIGNAL GROUND

o 7

DATA SET READY

DATA TERMINAL READY
DATA SET READY

DATA TERMINAL READY

020
06
RD1150

Figure 2-7

Null Modem Cable Connections

2.6.5 Modem Cables
Recommended modem cables are as follows.
1.

BC22F (for EMC/RFI shielded cabinets)
•

Round 25-conductor fully shielded cable

•

Subminiature 25-pin D-type female connector on one end, male connector on the other

•

Lengths available.
BC22F-I0
BC22F-25
BC22F-35
BC22F-50
BC22F-75

3.1 m (10 ft)
7.62 m (25 ft)
10.72 m (35 ft)
15.24 m (50 ft)
22.9 m (75 ft).

BC05D
•

Round 25-conductor cable

•

Subminiature 25-pin D-type female connector on one end, male connector on the other

•

Lengths available.
BC05D-I0
BC05D-25
BC05D-50
BC05D-60
BC05D-AO

- 3.1 m (10 ft)
- 7.62 m (25 ft)
- 15.24 m (50 ft)
- 18.6 m (60 ft)
- 30.48 m (100 ft).
CAUTION

In some countries, protective hardware may be
needed when connecting to certain lines. Refer to
the national regulations before making a connection.

2-17

2.6.6

Data- Rate to Cable-Length Relationships

All the recommended cables have data-rate/ cable-length characteristics as in Table 2-7. Cables oflengths
different from those quoted in Sections 2.6.4 and 2.6.5 will have to be specially made. An acceptable nonFCC cable for this purpose is Belden type 8777.

Table 2-7

Data-Rate/Cable-Length Relationships

Data Rate
(Bits/s)

Cable Length
(Meters)

Cable Length
(Feet)

110
300
1 200
2400
4800
9600

914
914
152
152
76
76

3000
3000
500
500
250
250

NOTE
Cables longer than 15.24 m (50 ft), or with a total
capacitance greater than 2.5 nanofarads, violate
RS-232-C and V.28 specifications.

2.7
2.7.1

MULTIPLE COMMUNICATIONS OPTIONS
Floating Device-Addresses

On UNIBUS and Q-bus systems, a block of addresses in the top 4 K words of address space is reserved for
options with floating device-addresses. For UNIBUS systems, the floating-address range is 7600108 to
7637768.
Options which can be assigned floating device-addresses are listed in Tabl~ 2-8. This table gives the
sequence of addresses for both UNIBUS and Q-bus options.
Having one list allows us to use one set of configuration rules and one configuration program.
Devices of the same type are given addresses in sequence, so all DZ11 s have addresses higher than
DUlls and lower than RL11s.
The column 'Size', in Table 2-8, shows how many words of address space are needed for each device. The
column 'Modulus' is the modulus used for starting-addresses. For example, device~ with an octal modulus
of 10 must start at an address which is a multiple of 108. The same rule is used to select a gap-address (see
the assignment rules) after an option, or for a nonexistent device.
Table 2-8
Rank

Device

1
2
3
4
5

DJ11
DH11
DQ11
DUll, DUVll
DUP11

Floating Device Address Assignments
Size
(Decimal)

Modulus
(Octal)

10
20
10
10
10

4
4
4

2-18

Notes

Table 2-8

Floating Device Address Assignments (Cont)

Rank

Device

6
7
8
9
10
11
12
13
14
15
16
17
18

LK11A
DMC11/DMR11
DZ11/DZV11, DZS11, DZ32
KMC11
LPP11
VNiV21
VMV31
DWR70
RL11, RLV11
LPA11-K
KW11-C
Reserved
RX11/RX211,
RXV11/RXV21
DR11-W
DR11-B
DMPII
DPV11
ISB11
DMV11
DEUNA
UDA50/RQDX1
DMF32
KMS11
VS100
TU81
KMVll
DHV11/DHU11
DMZ32, CPI32 (async)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ADV11-C
AAV11-C
AXV11-C
KWV11-C
ADV11-D
AAVII-D

19
20
21
22
23
24
25
26
27
28
29
30
'-"

.)1

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

Size
(Decimal)

Modulus
(Octal)

4
4
4
4
4

10
10
10
10
10

11').

8
4
4
8
4
4

20
10
10
20
10
10

4
4
4
4
4
4
8
4
2
16
6
8
2

10
10
10
10
10
10
20
10
4
40
20
20
4

£.v

8
16
16
64
4
8
4
4
4
4
4
4
2
4
4

20
40
40
100
10
20
10
10
10
10
10
10
4
10
10

Notes

DMC before DMR
A. DZ11 before DZ32

B
B

B. RX11 before RX211
C

B
B

"I{\

B
B

NOTE
When there are no previous floating address space options in a system, the address of the first DHUl1
installed is 7604408.
A.

DZ11-E and DZ11-F are treated as two DZ11s.

The first device of this type has a fixed address. Any extra devices have a floating address.

The first two devices of this type have a fixed address. Any extra devices have a floating address.
2-19

The address-assignment rules are as follows.
1.

Addresses, starting at 7600108 for UNIBUS systems, are assigned according to the sequence
of Table 2-8.

Option- and gap-addresses are assigned according to the octal modulus as follows.
a.

Devices with an octal modulus of 4 are assigned an address on a 48 boundary (the two
lowest-order address bits = 0).

Devices with an octal modulus of 10 are assigned an address on a 108 boundary (the three
lowest-order address bits = 0).

Devices with an octal modulus of 20 are assigned an address on a 208 boundary (the four
lowest-order address bits = 0).

Devices with an octal modulus of 40 are assigned an address on a 408 boundary (the five
lowest-order address bits = 0).

Address space equal to the device's modulus must be allowed for each device which is
connected to the bus.

A I-word gap, assigned according to rule 2, must be allowed after the last device of each type.
This gap could be bigger when rule 2 is applied to the following rank.

A I-word gap, assigned according to rule 2, must be allowed for each unused rank on the list if a
device with a higher address is used. This gap could be bigger when rule 2 is applied to the
following rank.

If extra devices are added to a system, the floating addresses may have to be reassigned in agreement with
these rules.
In the following example, a brief description of UNIBUS address assignment is given. Note that the list
includes floating-vector addresses. These are explained in Section 2.72.
Example: One DUll, one RLll, and two DHUlls
Vector

Address
(Octal)

760010
760020
760030
760040
760050

DJ11 gap
DR11 gap
DQ11 gap
DUll
DUll gap

760060
760070
760100
760110
760120

DUP11 gap
LK11A gap
DMC11 gap
DZ11 gap
KMCll gap

2-20

300

Address
(Octal)
760130
760140
760160
760170
760200
760210
760220
760230
760240
760250

Vector
LPPII gap
VMV21 gap
VMV31 gap
DWR70 gap
RLll

310

RLll gap

LPAII-K gap
KWII-C gap
reserved gap
RXII gap

760260
760270
760300
760310
760320

DRII-W gap
DRII-B gap
DMPII gap
DPVII gap
ISBII gap

760340
760350
760354
760400
760420

DMVII gap
DEUNA gap
UDA50 gap
DMF32 gap
KMSll gap

760440
760444
760460
760500
760520

VSIOO gap
reserved gap
KMVII gap
1st DRUll
2nd DRUII

760540

DRUll gap

320
330

The first floating address is 7600 I O. As the DJII has a modulus of lOs, its gap can be assigned to 7600 I O.
The next available location becomes 760012.
As the DRII has a modulus of20s, it cannot be assigned to 760012. The next modulo 20 boundary is
760020, so the DRII gap is assigned to this address. The next available location is therefore 760022.
A DQII has a modulus of lOs. It cannot be assigned to 760022. Its gap is therefore assigned to 760030.
The next available location is 760032.
A DUll has a modulus of lOs. It cannot be assigned to 760032. It is therefore assigned to 760040. As the
'size' of DUll is four words, the next available address is 760050.
There is no second DUll, so a gap must be left to indicate that there are no more DUll s. As 760050 is on
a lOs boundary, the DUll gap can be assigned to this address. The next available address is 760052.
And so on.

2-21

2.7.2

Floating Vectors

Addresses between 3008 and 7748 are designated as the floating-vector space. These addresses are
assigned in sequence as in Table 2-9.
Each device needs two 16-bit locations for each vector. For example, a device with one receive and one
transmit vector needs four words of vector space.
The vector assignment rules are as follows.
1.

Each device occupies vector address space equal to 'Size' words. For example, the DLV11-J
occupies 16 words of vector space. If its vector was 3008, the next available vector would be at
3408.

There are no gaps, except those needed to align an octal modulus.

An example of floating-vector address assignment is given in Section 2.7.1.
Table 2-9
Rank

Device

1
1
2
2
2
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
17
18
19
20
21
22
23
24

DC11
TU58
KL11
DL11-A
DL11-B
DLV11-J
DLV11, DLV11-F
DP11
DM11-A
DN11

DM11-BBjBA
DH 11 modem control
DR11-A, DRV11-B
DRI1-C, DRVII
PA611 (reader + punch)
LPD11
DT07
DX11
DL11-C to DLVII-E
D111
DH11
VT40
VSV11
LPS11
DQ11
KW11-W, KWVl1
DUll, DUVl1
DUP11
DV 11 + modem control
LK11-A

Floating Vector Address Assignments
Size
(Decimal)

Modulus
(Octal)

4
4
4
4
4
16
4
4
4
2
2
2
4
4
8
4
4
4
4
4
4
8
8
12
4
4
4
4
6
4

10
10
10
10
10
10
10
10
10
4
4
4
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10

2-22

Notes

A
A
A

Table 2-9

Floating Vector Address Assignments (Cont)

Rank

Device

Size
(Decimal)

Modulus
(Octal)

25
26
27
28
29
30

DWUN
DMC11/DMRII
DZll/DZSll/DZVll, DZ32
KMCII
LPPII

4
4
4
4
4

10
10
10
10
10

V~.1V21

VMV31

4
4
4
2
2
4
2
4

10
10
10
4
4
10
4
10
4
4
4
10
10
4
10
10
4
4
4

.)1

40
41
42
43

VTVOI
DWR70
RLll/RLVII
TSll, TU80
LPAII-K
IPll/IP300
KWII-C
RXll/RX211,
RXVll/RXV21
DRII-W
DRII-B
DMPII
DPVll

32
33
34
35
36
37
38
39

A A

.,.,.-T

"t"t

NiL I I

45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71

ISBII
DMVII
DEUNA/DEQNA
UDA50/RQDXl
DMF32

KMSll

t:..

1£\

4
2
2
4
4
4
4
12
12
4
2
2

10
4
4
10
10
10
10
4
4
1
4
4
4
4

PCLII-B
VSI00
TU81
KMVII
KCT32
lEX
DHVII/DHUll
DMZ32, CPI32 (async)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ADVII-C
AAVII-C
AXVII-C
KWVII-C
ADVl1-D

DMC before DMR
DZII before DZ32

1n.

2
2
2
4
4
2
4
4
12
2
16

1 1

Notes

2
2
2
4

B
B
B

B. RX 11 before RX211
B

B
B

10
10
0

4
4

10
10

2-23

Table 2-9

Floating Vector Address Assignments (Cont)

Rank

Device

Size
(Decimal)

AAVl1-D
QDSS
DRVII-J

4
6
32

73
74

Modulus
(Octal)

4
4

Notes

A KLII or DLII used as the console has a fixed vector.

The first device of this type has a fixed vector. Any extra devices have a floating vector.

MLll is a MASSBUS device which can connect to a UNIBUS via a bus adapter.

2.8

INSTALLATION TESTING

This section identifies the diagnostic tests that should be run on PDP-II or VAX systems after the
installation of a DHUII. Chapter 4, Maintenance, contains descriptions of the tests, and more detailed
information on how they should be run.
DHUIl diagnostics are available for both PDP-II and VAX systems. There are four types.

•
•
•
•

Power-up self-test
On-line diagnostics ( VAX systems only)
Functional verification tests
System exercisers

The first three types provide an ascending level of confidence in the option.
As well as providing the highest level of confidence, functional verification tests also provide a means of
quickly identifying a defective FRU.
System exercisers check that the options of a system will work together.

2.8.1 PDP-II Installation Tests
The following diagnostics should be run on PDP-II systems after installation. Note that each diagnostic
name has a revision and a patch level. For example, ZD HU Al identifies test ZD HU, revision level A and
patch level 1. The symbol ? is a global indicator for revision and patch levels.
1.
2.
3.

Self-test
Functional verification tests ZDHU??, ZDHV??, ZDHW??, and ZDHX??
DECX/II exerciser XDHU??

XDHU?? is not directly runnable. The DECX/II exerciser must first be configured into a run-time
exerciser (see Chapter 4, Section 4.4.2). All individual device diagnostics should be run without error
before DECX/II is run.
The self-test runs automatically when the bus or DHUII is reset. If no fault is found, the diagnostic LED
will flash OFF/ON/OFF and then come ON permanently. The first OFF state is very short and may not
be seen. However, if the LED goes OFF before coming ON permanently the diagnostic has found no
faults. This does not prove that the option is serviceable.

2-24

During the self-test diagnostic operation, bytes are written to the RX FIFO. By reading these bytes, the
engineer can receive more detailed information about the state of the DHUll. Diagnostic bytes and their
interpretation are described in Chapter 3 of this document. The self-test can take up to 2.5 seconds.
The ZDHU??, ZDHV??, ZDHW??, and ZDHX?? diagnostics can be used:
•
•
•

F or testing a new installation
For troubleshooting
As a comprehensive confidence check.

The diagnostic listings describe these tests, and how to run then1.

2.8.1.1

PDP-II Installation Test Sequence

Switch on power, or reset the system. Check the diagnostic LED sequence.

Install staggered-Ioopback connectors on the BC05L cables.

Run all the ZDH diagnostics in sequence for one error-free pass. If there are no errors, the
module is probably good.

Run the DECX/ll exerciser to verify that the DHUll will run with other options of the
system.

Re-cable the option for normal operation (see Figure 2-2). The DHUll should now be ready for
connection to external equipment. See Section 2.6 if necessary, for recommended modem and nullmodem cables.
If any of the tests show errors, refer to Chapter 4, Maintenance, Sections 4.4 and 4.5, for diagnostic
information and a troubleshooting flowchart.

2.8.2 V~X Installation Tests
In addition to the self-test, which functions as described in Section 2.8.1, the following VAX diagnostics
are available.
•
•
•

2.8.2.1
used:
•
•
•

Standalone VAX diagnostic EVDAI
On-line VAX diagnostic EVDAH
User Environmental Test Pro~ram (UETP)
EVDAI Standalone Diagnostic - EVDAI is a suite of functional verification tests that can be
As installation tests
For troubleshooting
As a more comprehensive confidence check.

The diagnostic listing ZZ-EVDAI describes the tests and how they are run.

2.8.2.2 EVDAH On-Line Diagnostic - This diagnostic provides a confidence check ofDHUlls in
VAX/VMS systems. Channels which have not been allocated to a process can be checked while the
system is running application programs. The following tests call be selected.
1.
2.

Internal data-Ioopback test on selected channels in sequence.
Internal DMA data-Ioopback test on selected channels in sequence.

2-25

3.
4.
5.

Internal data-Ioopback test on selected channels at the same time.
Externalloopback test (via H325) of modem control signals.
External data-Ioopback via a modem or H3 25. If a modem is used, it must be set up manually.

Diagnostic listing ZZ-EVDAH describes the tests and how to run them.
2.8.2.3 VAX/VMS System Exerciser UETP - This exerciser package checks that there is no
unwanted interaction between the options connected to the system.
2.8.3 VAX Installation Test Sequence
The test sequence after installation is as follows.
1.

Switch on power, or reset the system. Check the diagnostic LED sequence.

Install staggered-Ioopback connectors on the BC05L cables.

Run EVDAI for one error-free pass on all lines, in staggered-Ioopback mode.

Connect the option for normal operation.

Run EVDAH tests 1,2, and 3 in internal-Ioopback mode for one error-free pass on all lines.

Run the system exerciser package UETP to verify that the DHUll will run with other options
of the system.
NOTE
Before EVDAI or EVDAH is run, the DHUtt
must be 'attached' to the system (see the VAX
Diagnostic System User's Guide). The form of the
ATTACH command is:
DS> ATTACH DHUtt DWO TYA xxxxxx yyy 5
where xxxxxx is the device address and yyy is the
vector.

The DHUll should now be ready for connection to external equipment. See Section 2.6 ifnecessary, for
recommended modem and null-modem cables.
If any of the tests show errors, refer to Chapter 4, Section 4.6 for diagnostic information and a
troubleshooting flowchart for the EVDAI diagnostic.

2-26

CHAPTER 3
PROGRAMMING
3.1

SCOPE

This chapter describes the control-and-status registers, and how they are used to control and monitor the
DHU11. The chapter covers:
•
•

The bit functions and format of each register
Programming features available to the host.

Some programming examples are also included.

3.2 REGISTERS
The host controls and monitors the DHU11 module via a number of control-and-status registers.
Command words or bytes written to the registers are interpreted and processed by the firmware. Status
reports and data are also transferred via the registers.

3.2.1

DHU11 registers occupy eight words (16 bytes) of UNIBUS memory-mapped I/O space. However, by
indexing, this is expanded internally to 115 words.
The position of the eight words within the I/O page is switch-selected. on the DHU11. In order to access
the module, bits <12:4> of an I/O address must match the address switch coding.
Table 3-1 lists the DHU11 registers and their addresses. The suffix (M) means that there are 16 of these
registers, one for each channel. When an (M) register is accessed, the channel is selected by the contents of
CSR<3:0>.
The term 'base' means the lowest I/O address on the module, that is to say, when the four low-order
address bits = O.
Registers are accessed by instructions which use 'base + n' as a source or destination. However, before
multiple (M) registers are accessed, the channel number must be written to the CSR The following
example explains this.
To read the line-control register of chan.nel 3, the following PDP~ll instructions are executed:
MOVB #CHAN,@#BASE
MOV @#BASE+10,RO

;WRITE CHANNEL NUMBER (SEE BELOW) TO CSR
;READ THE LINE-CONTROL REGISTER

3-1

In the example:
Where e = the RXIE bit
and r
= the MRST bit (would be 0)
and 00112 = channel number 3

CHAN = OerOOO 112

NOTE
1.

Not all register bits are specified. During a
write, all unspecified bits must be written as Os.
During a read, unspecified bits are undefined.

The exception to the above rule is that a bit
may be written as logical 1 or 0 if it is read as
logical 1. That is to say, read-modify-write
instructions work correctly. Read-modify-write
instructions should not be used on the base
address or base + 2.

Writing to the LPR or LNCTRL registers on
any line impacts the performance of every line.
Table 3-1

DUUII Registers

Register
Control-and-Status Register
Receive Buffer
Receive Timer *
Line Parameter Register
FIFO Data
FIFO Size
Line Status
Line Control
Transmit Buffer Address 1
Transmit Buffer Address 2
Transmit Buffer Count

(CSR)
(RBUF)
(RXTIMER)
(LPR)
(FIFODATA)
(FIFOSIZE)
(STAT)
(LNCTRL)
(TBUFFADl)
(TBUFFAD2)
(TBUFFCT)

Address (Octal)

Type

Base
Base + 2
Base + 2
Base + 4 (M)
Base + 6 (M)
Base + 6 (M)
Base + 7 (M)
Base + 10 (M)
Base + 12 (M)
Base + 14 (M)
Base + 16 (M)

Read/Write
Read
Write (byte)
Read/Write
Write
Read (byte)
Read (byte)
Read/Write
Read/Write
Read/Write
Read/Write

* Only accessible when CSR<3:0> = 0000. See 3.2.2.1.
3.2.2 Register Bit Definitions
The register formats, which precede the definitions of the register bits, are coded as follows.
•

Bits marked with an asterisk (*) may hold data-set status, or special information from the
diagnostic programs. These are covered in Section 3.3.10.

•

Registers which are modified by reset sequences are coded as shown in Figure 3-1.

3-2

D
D

CLEARED BY MASTER RESET

SET BY MASTER RESET

CLEARED BY BIN IT, POWER-UP OR POWER-DOWN
BUT NOT BY MASTER RESET
ROl179

Figure 3-1

3.2.2.1

Base Control-and-Status Register (CSR)
CSR (BASE)

I RJ~ R I R I
TX

ACTiON

DIAGNOSTIC

L41J RJE sL L41J
I

FAil

INT.
ENABLE
(RXIE)

TRANSMIT
LINE NUMBER
TRANSMIT
INT. ENABLE

TRANSMIT
DMA ERROR

RCVE DATA
AVAILABLE

INDIRECT ADDRESS
REG POINTER
(CHANNEL NUMBER)

MASTER
RESET
R01827

Bit

Name

Description

<3:0>

IND.ADDR.REG
(Indirect Address
Register) (RlW)

These bits are used to select the channel when accessing a block of
indexed (M) registers. They form the binary number of the channel
which is to be accessed.

SKIP
(Skip Self-Test)
(RlW)

This bit is used to make the DHU11 skip the self-test operation. This
will shorten the reset/initialization sequence to about 25 milliseconds.
The bit must only be set at the same time as MASTER.RESET
(write 60 to CSR). It must be cleared not less than 20 microseconds
after it is set.

3-3

Bit

Name

Description

MASTER.RESET
(Master Reset)
(RlW)

Set by the host, in order to reset the DHU11 to a known state. Stays
set while the DHUll runs a self-test diagnostic and then performs an
initialization sequence. The bit is then cleared to tell the host that the
process is complete.
This bit is set by BINIT (bus initialization signal), or by the host
processor setting CSR<5>.
The host must not write to any register, or read RBUF, while this bit
is set, except during a 'skip self-test' operation.

RXIE
(Receiver Interrupt
Enable) (RlW)

When set, this bit allows the DHUll to interrupt the host when
RX.DAT A.A VAIL is set. An interrupt is generated under the
following conditions:
1. RXIE is set and a character is placed into the empty RX FIFO
2. The RX FIFO is not empty and RXIE is changed from 0 to 1.
Cleared by BINIT but not by MASTER.RESET.
The receive interrupt may be delayed by use of the RXTIMER
register (see Section 3.2.2.3).

RX.DAT A.A VAIL
(Received Data
Available) (RD)

When set, indicates that a received character is available. This bit is
clear when the RX FIFO is empty. It is used to request an RX
interrupt.
Set after MASTER.RESET because the RX FIFO contains
diagnostic information.

<11:8>

TX.LINE
(Transmit Line
Number) (RD)

If TX.ACTION is set, these bits hold the binary number of the
channel on which one of the following has just occurred.

1. The TX FIFO has become empty.
2. A DMA transfer has been completed normally.
3. A DMA abort sequence has been completed.
If TX.DMA.ERROR is also set, these bits contain the binary
number of the channel which has failed during a DMA transfer.

TX.DMA.ERROR
(Transmit DMA
Error) (RD)

If set with TX.ACTION also set, means that the channel indicated
by C SR< 11 :8> has failed to transfer D MA data within 21.3
microseconds of the bus request being acknowledged, or that there is
a memory parity error.

The TBUFFADI and TBUFFAD2 registers will contain the
address of the memory location which could not be accessed.
TBUFFCT will be cleared.

3-4

Bit

Name

Description

DIAG.FAIL
(Diagnostic Fail)
(RD)

When set, indicates that the DHUll internal diagnostics have
detected an error. The error may have been detected by the self-test
diagnostic or by the BMP.
This bit is associated with the diagnostic-passed LED. When it is set,
the LED will be otT. When it is cleared, the LED will be on.
Thp hit i~ ~pt h" M
..&. ....... ' "

V""'"

...,."'""'"

A C;;:TH'"R "RH'C;;:H'T • ...........
It 1~ 1"'1p<:lrpA ""'
<:lftpr
lntprn<:ll
.I. ..."" ......thp
.1..1."" .I..I..I."''-''.I..I..I.U.1.

.a. • ..&..1. ... ..., .... ~"""".""'-L...I""'.&...J..&.

&.)1

""' .... '"'~'"'''''

diagnostic programs have been run successfully.
DIAG.FAIL is only valid after MASTER.RESET (CSR<5» has
been cleared.
14

TXIE (Transmit
Interrupt Enable)
(RlW)

When set, allows the DHUll to interrupt the host when CSR< 15>
(TX.ACTION) becomes set.
Cleared by BINIT but not by MASTER.RESET.

TX.ACTION
(Transmit Action)
(RD)

This bit is set by DHUll when:
1. The last character of a D MA butTer has been transmitted

2. An abort sequence has been conlpleted
3. A DMA transfer has been terminated by the DHUll because
nonexistent memory has been addressed, or because of a
memory parity error

4. A TX FIFO becomes empty during a TX FIFO output
sequence.
This bit is cleared if the host reads the CSR after the TX Action
FIFO has become empty. To avoid losing TX Action reports, the
host must not let more than 16 reports accumulate. It is advisable to
read the CSR until TX.ACTION becomes clear, otherwise a TX
interrupt will not be generated when further reports are loaded.
Also cleared by MASTER.RESET.
NOTE
L~K contents shouid oniy be accessed by a PDP-II MOV or
MOVB instruction, or the VAX equivalent (MOVW or MOVB).
Other instructions may lose the state of the TX.ACTION bit
(CSR<15».

3-5

3.2.2.2 Receive Buffer (RBUP) - This is a read-only register at address Base + 2. Reading the register
accesses the oldest word in the 256-word RX FIFO. The least-significant bit (LSB) of the character is in
bit O.
RBUF (READ BASE+2)

[ R

IR IR IR

IR IR

FRAMING
ERROR

IR IR IR IR

I
DATA
VALID

RECEIVE
LINE NUMBER

RECEIVED
CHARACTER

OVERRUN
ERROR

PARITY
ERROR

DATA SET
(FROM HIGH BYTE
STATUS FLAGS OF STAT)

I
OR

DIAGNOSTIC INFO

RD' 855

Bit

Name

Description

<7:0>

RX.CHAR
(Received
Character) (RD)

If RBUF<14:12> = 000, these eight bits contain the oldest
character in the FIFO. The character is good.
IfRBUF<14:12> = 001,010, or 011, these eight bits contain the
oldest character in the FIFO. The character is bad.
If RBUF< 14: 12> = 111, these eight bits contain diagnostic or
modem status information. In this case, RBUF<O> has the
following meanings.

o = Modem status in RBUF<7:1> (see Section 3.2.2.7)
1 = DiagnosticinformationinRBUF<7:1> (see Section3.3.10).
If there is an overrun condition, the U ART data buffer for that
channel will be cleared. A null character with RBUF<14> set
(400008) will be placed in the RX FIFO. The cleared data will be
lost.
The DHU11 does not have a break-detect bit. A line break is
indicated to the program as a null character with the FRAME. ERR
set (200008).
<11:8>

RX.LINE
(Receive Line
Number) (RD)

These bits hold the binary number of the channel on which the
character of RBUF<7:0> was received or on which a data-set
change was reported.

3-6

Bit

Name

Description

PARITY. ERR
(Parity Error)

Set if this character has a parity error and parity is enabled for the
channel indicated by bits <11:8> (also see RX.CHAR).

(RD)
13

Set if the first stop bit of the received character was not detected (also
see RX.CHAR).

FRAME.ERR
(Framing Error)

(RD)
14

OVERRUN. ERR
(Overrun Error)

Set if one or more previous characters of the channel indicated by bits

< 11 :8> were lost because of a full FIFO, or failure to service the
DARTs (also see RX.CHAR).

(RD)

NOTE
The 'alii s' code for bits < 14: 12> is reserved. This code indicates
that modem status or diagnostic information is held in RBUF<7:0>.
15

DATA. VALID
(Data Valid)

Set if the FIFO is not empty. Cleared by MASTER.RESET or by
the FIFO becoming empty.

(RD)
After self-test, diagnostic information is loaded into the RX FIFO.
Therefore, this bit is always set after a successful master-reset
sequence.
3.2.2.3 Receive Timer Register (RXTIMER) - The indirect address register (CSR<3:0» must
= 0000 in order to access the receive timer. It can be used by the host to delay the receive interrupt.
Rx TIMER (BASE+2)

I I
RD1774

Bit

Name

Description

<7:0>

RX.TIMER
(Receive Timer)
(WR BYTE)

The receive interrupt is normally raised when a received character is
loaded into the previously empty RX FIFO. The binary number
loaded into RXTIMER modifies this procedure as follows.

Infinite timeout. This timeout will be overridden
by the conditions below.

No timeout.
immediately.

2 to 255

Timer delay in milliseconds

3-7

The interrupt will be raised

Bit

Name

Description
The timer is overridden when the FIFO becomes three-quarters full
(critical) or when a modem status change is written to the FIFO.
Set to 1 by MASTER RESET.

3.2.2.4 Line Parameter Register (LPR) - This register is used to configure its associated channel. Bit
function is as follows.
LPR (BASE+4)

fwfwIRIWIRlWfwfwIRIWIRlWlwvdRIWJRlWIRlWfwl~~
[

[

TRANSMIT
SPEED

STOP
CODE
RECEIVE
SPEED

PARITY
ENABLE

EVEN
PARITY

DIAGNOSTIC
CODE

CHARACTER
LENGTH

Bit

Name

Description

<2:1>

DIAG
(Diagnostic Code)
(RlW)

Diagnostic control codes. Used by the host as follows.
00

Normal operation

Causes the background monitor program (BMP) to
report the DHUll status via the RX FIFO. BMP
reports are covered in Section 3.3.10.

Set to 00 by MASTER.RESET.
<4:3>

CHAR.LGTH
(Character Length)
(RlW)

Defines the length of characters. Does not include start, stop, and
parity bits.
00
01
10
11

5 bits
6 bits
7 bits
8 bits

Set to 11 by MASTER.RESET.

3-8

Bit

Name

Description

PARITY.ENAB
(Parity Enable)
(R/W)

Parity enable. Causes a parity bit to be generated on transmit, and
checked and stripped on receive.
1 =

Parity enabled

o = Parity disabled
Cleared by MASTERRESET.
6

EVEN. PARITY
(Even Parity)
(R/W)

If LPR<S> is set, this bit defines the type of parity.
1 = Even parity

o = Odd parity

Cleared by MASTER.RESET.
7

STOP.CODE
(Stop code)
(R/W)

Defines the length of the transmitted stop bit.

o = 1 stop bit for 5-, 6-, 7- or 8-bit characters
1 = 2 stop bits for 6-, 7-, or 8-bit characters or 1.5 stop bits for
5-bit characters

<11:8>

<15:12>

RX.SPEED
(Received Data
Rate) (RlW)
TX.SPEED
(Transmitted Data
Rate) (RlW)

Set to 1101 by MASTER.RESET. (9 600 bits/s)
Defines receive data rate (Table 3-2).
Set to 1101 by MASTER.RESET. (9600 bits/s)
Defines transmit data rate (Table 3-2).

3-9

Data Rates

Table 3-2
Code

Data Rate
(Bits/s)

Maximum
Error (%)

0000
0001
0010
0011

50
75
110
134.5

0.01
0.01
0.08
0.07

Groups

B
A and B
A and B

0100
0101
0110
0111

150
300
600
1200

0.01
0.01
0.01
0.01

B
A and B
A and B
A and B

1000
1001
1010
1011

1 800
2000
2400
4800

0.01
0.19
0.01
0.01

B
B
A and B
A and B

1100
1101
1110
1111

7200
9600
19200
38400

0.01
0.01
0.01
0.01

A
A and B
B
A

NOTE
The DUUlt 16-channel interface uses eight dualchannel ICs. Channels 0/1, 2/3, 4/5, 6/7, 8/9,
10/11, 12/13, and 14/15 are paired. It is the
responsibility of the user to select transmit and
receive data rates of the same group (A or B), for
any pair of channels.
If channels within the same D U ART are configured
in different groups, the resulting data rates are
undefined.
3.2.2.5 FIFO Data Register (FIFODATA)-A write to FIFODATA is interpreted as a write to a TX
FIFO. To send a character or characters via a TX FIFO, the host writes the character( s) to the FIFO data
register of the appropriate channel. To make sure that there is room in the TX FIFO, the host should first
read the associated FIFO size register (See Section 3.2.2.6). If single characters are sent, they must be
written to the low byte of FIFODATA.
FIFODATA (BASE+6)

IwJwJwJwJwJwJwJwJwJwJwJwJwJwJwJwJ
~

____________

__________

-JA~

_ _ _ _ _ _ _ _ _ _ _ _ _y_ _- -_ _ _ _- -_ _

TX DATA CHARACTER

3-10

Bit

Name

Description

<7:0>

FIFODATA<7:0>
(FIFO Data Byte
Register)
(WRBYTE)

Contains a single character for transfer via the TX FIFO, After a
write-byte action to this register, FIFODATA<7:0> is transferred
to the FIFO.
The least-significant bit of the character is in FIFODATA bit O.
Unused bits must be cleared.
Cleared by MASTER.RESET.

<15:0>

FIFODATA<15:0>
(FIFO Data
Register) (WR)

Contains two characters for transfer via the TX FIFO. After a writeword action to this register, FIFODATA<7:0> ·and then
FIFODATA<15:8> are transferred to the FIFO.
The least-significant bits of the characters are in FIFODATA, bits 0
and 8. Unused bits must be cleared.
Cleared by MASTER.RESET.

3.2.2.6 FIFO Size Register (FIFOSIZE) - This low-byte register holds a number which indicates
the space available in the TX FIFO.
FIFOSIZE (BASE+6)

I I I I I I

ALWAYS 0
l

FIFO SIZE 0 - 64

Bit

Name

Description

7:0

FIFO SIZE
(FIFO Size)
(RD BYTE)

Indicates the available space (in characters) in the TX FIFO. The
range is 0008 (010) to 1008 (6410). This register should be read
before sending a character, or a sequence of characters, to the FIFO
data register.
NOTE
This register can be read (RD WORD) at the same time as the
STAT register.
Set to 1008 by MASTER.RESET

3-11

3.2.2.7 Line Status Register (STAT) - This high-byte register is read from base + 7. It holds modem
status information.
STAT (BASE+7)
15

I I I I I
R

DCD
RI
(RING
INDICATOR)

DSR

ALWAYS 1

CTS

Bit

Name

Description

DHUID
(DHUll Identifier)
(RD)

Tells the host whether a DHUll or a DHVII is installed. This bit is
not valid while MASTERRESET is set.
Always 1 on DHUll (0 on DHVll).

CTS
(Clear to Send)
(RD)

Gives the present status of the Clear To Send (CTS) signal from the
modem.
1

o=
12

DCD (Data
Carrier Detect)
(RD)

ON
OFF

Gives the present status of the Data Carrier Detect (DCD) signal
from the modem.
1

o = OFF
13

RI (Ring Indicator)
(RD)

Gives the present status of the Ring Indicator (RI) signal from the
modem.
1

o = OFF
15

DSR
(Data Set Ready)
(RD)

Gives the present status of the Data Set Ready (DSR) signal from the
modem.
1

o = OFF
NOTE
In order to report a change of modem status, the D HUll writes the
contents ofSTAT<15:9> into RBUF<7:1>. RBUFbitO will be
clear. RBUF<14:12> = 111 totellthehostthatRBUF<7:0> do
not hold a received character (see Section 3.3.8, Modem Control).
This register can be read (RD WORD) at the same time as the
FIFO size register.
3-12

3.2.2.8 Line Control Register (LNCTRL) - The main function of this register is to control the line
interface.
LNCTRL (BASE+ 1O)

i
MAiNTENANCE

BREAK

!AUTO

MODE
MKV86-2002

Bit

Name

Description

TX.ABORT
(Transmitter
Abort) (RlW)

Set by the host to halt the transfer of data.

If a DMA transfer was in progress, the DMA address and count
registers (TBUFFAD1, TBUFFAD2, and TBUFFCT) will be
updated to reflect the number of characters which have been
transmitted. The transfer can be continued by clearing TX.ABORT,
and then setting TX.DMA. START in TBUFF AD2. No characters
will be lost.
The program must make sure that TX.ABORT is clear before setting
TX.DMA.START. Otherwise the transfer will be aborted before
any characters are transmitted.
If a programmed transfer was in progress, characters in the TX
FIFO will be discarded, Because of firmware delays, it is possible to
transmit a few characters before the abort is actioned. Therefore, the
host cannot determine how many characters have been lost.
When an abort sequence has been completed, the DHU11 will set
the TX.ACTION bit in the CSR. If the transmitter interrupt is
enabled, the program will be interrupted at the transmit vector.
See Section 3.3.3.1, DMA Transfers, for the use of TX.ABORT.
Cleared by MASTER.RESET.

IAUTO.FLOW
(Incoming Auto
Flow) (RlW)

This is the auto-flow control bit for incoming characters. If this bit is
set, the D HU 11 will control incoming characters by transmitting
XON and XOFF codes.

If the RX FIFO becomes congested, the DHUl1 will send an
XOFF code to channels with this bit set. An XON will be sent when
the congestion is reduced. See Section 3.3.6, Auto XON and
XOFF.

3-13

Bit

Name

Description
Cleared by MASTER.RESET.

NOTE
An XON code = 218 = DCI = CTRL/Q.
An XOFF code = 238 = DC3 = CTRL/S.
No other codes are specified for the interface.
2

RX.ENA (Receiver
Enable) (RlW)

If this bit is set, this receiver channel is enabled.
If this bit is reset when this DUART channel is assembling a
character, that character may be lost.

Cleared by MASTER.RESET.

BREAK
(Break Control)
(RlW)

If set, this bit forces the transmitter of this channel to the spacing
state.

Transmission is restarted when the bit is cleared.
Cleared by MASTER.RESET.

NOTE
There is a short delay between writing the bit and the channel
changing state. The delay is dependent on the amount ofDHUll
activity. Because of the normal length of a BREAK signal, this
should not cause problems.
4

OAUTO
(Outgoing Auto
Flow) (RlW)

This bit is the auto-flow control bit for outgoing characters. When
OAUTO and RX.ENA are both set, the DHUll will automatically
respond to XON and XOFF codes received from a channel. The
DHUll uses the TX.ENA bit in TBUFF AD2 to stop and start the
flow. See Section 3.3.6, Auto XON and XOFF.
Cleared by MASTER.RESET.

FORCE.XOFF
(Force XOFF)
(RlW)

This bit can be set by the program to indicate that this channel is
congested at the host system (for example, if the typeahead buffer is
full). When it sees this bit set, the DHUll will send an XOFF code.
Until the bit is reset, XOFFs will be sent after every alternate
character received on that channel. When the bit is reset, an XON
will be sent unless IAUTO is set and the RX FIFO is critical. See
Section 3.3.6, Auto XON and XOFF.
Cleared by MASTER.RESET.

3-14

Bit

Name

Description

<7:6>

MAINT
(Maintenance
Mode) (RlW)

These bits can be written by the driver or test programs, in order to
test the channel.
The coding is as follows.
00

Normal operation

Automatic echo mode - Received data is retra...'1S111.itted
(regardless of the state ofTX.ENA) at the data rate
selected for the receiver. The received characters
are processed normally and placed in the RX FIFO.
In this mode, the DHUll will not transmit any
characters (this includes internally generated flowcontrol characters). The RX.ENA bit must be set
when operating in this mode.

Local loopback - The D U ART channel output is
internally connected to the input. Normal received
data is ignored and the transmit data line is held
marking. In this mode, flow-control characters will
be looped back instead of being transmitted. The
data rate selected for the transmitter is used for both
tran.smission tuld reCeption. The TX.Et~A bit still
controls transmission in this mode. RX.ENA is
ignored.

Remote loopback - In this mode received data is
retransmitted at a clock rate equal to the received
clock rate. The data is not placed in the R..X FIFO.
The state ofTX.ENA is ignored but RX.ENA must
be set.

Cleared to 00 by MASTER.RESET.
8

LINK. TYPE
(Link Type)
(RlW)

This bit must be set if the channel is to be connected to a modem.
When the bit is set, any change in modem status will be reported via
the RX FIFO as well as the STAT register.
If this bit is reset, this channel becomes a 'data leads only' channel.
Modem status information is loaded in the high byte of STAT but is
not placed in the FIFO.
Cleared by MASTER.RESET.

DTR (Data
Terminal Ready)
(RlW)

This bit controls the Data Terminal Ready (DTR) signal to the
modem.
1

ON
OFF

Cleared by MASTER.RESET.

3-15

Bit

Name

Description

RTS (Request
to Send) (RlW)

This bit controls the Request To Send (RTS) signal to the modem.
1 = ON

o = OFF
Cleared by MASTER.RESET.
3.2.2.9 Transmit Buffer Address Register Number 1 (TBUFFAD1) TBUFFAD1 (BASE + 12)
15

IRlWIRIWIRIWIRIWI RlWIRIWIRIWIRIWIRIWIRIWIRIWIRIWI RlWIRIWIRIWI RlWI

I I I I I I I I I I I I I I I I
I
TXMIT DMA ADDRESS
"(BITS 0 ..... 15)

Bit

Name

Description

<15:0>

TBUFFAD<15:0>
(Transmit Buffer
Address [Low])

Bits <15:0> of the DMA address (also see Section 3.2.2.10).
Cleared by MASTER.RESET.

(RlW)

3.2.2.10 Transmit Buffer Address Register Number 2 (TBUFFAD2) TBUFFAD2 (BASE+14)
15

TXMIT
ENABLE

TX
DMA
START

3-16

TXMIT DMA ADDRESS
(BITS 17-16)

Bit

Name

Description

<1:0>

TBUFFAD<17:16>
(Transmit Buffer
Address [High])
(RlW)

Bits <17:16> of the DMA address.
Before a DMA transfer, TBUFFADI and the low byte of
TBUFFAD2 are loaded with the start address of the DMA buffer.
This address is not valid during a DMA transfer. When TX.ACTION
is returned, the address will be valid.
Cleared by MASTER.RESET.

TX.DMA.START
(Transmit DMA
Start) (RlW)

Set by the host to start a DMA transfer. The DHUll will reset the
bit before returning TX.ACTION.
Cleared by MASTER.RESET.

NOTE
After setting this bit, the host must not write to TBUFFCT,
TBUFFAD1, TBUFFAD2 <7:0>, or FIFO DATA until the
TX.ACTION report has been returned.
15

TX.ENA
(Transmitter
Fn::lhlp.) (R/W)
,--. ..
-------~

When this bit is set, the DHUll will transmit all characters.
When this bit is cleared, the DHUll will only transmit interna!!y
generated flow-control characters.

In the 0 AUTO mode, this bit is used by the D HU 11 to control
outgoing characters. See Section 3.3.6, Auto XON and XOFF.
Set by MASTER.RESET.

3.2.2.11

Transmit DMA ButTer Counter (TBUFFCT) rBUFFCT (BASE+16)
15

I~~~~~~~~~~~~~~~~
I

I
I
DMA CHARACTER COUNT
(WHEN VALID, HOLDS NO. OF CHARS. STILL TO BE SENT)
RD1854

3-17

Bit

Name

Description

<15:0>

TX.CHAR.CT
(Transmit Character
Count) (RlW)

Loaded with the number of characters to be transferred by DMA.
The number of characters is specified as a 16-bit unsigned integer.
After a DMA transfer has been aborted this location will hold the
number of characters still to be transferred.
See also the previous note (Section 3.2.2.10, TX.DMA.START).
Cleared by MASTER.RESET.

3.3 PROGRAMMING FEATURES
3.3.1 Initialization
The DHUll is initialized by its on-board firmware.
Initialization takes place after a bus-reset sequence, or when the host sets CSR<5> (MASTER.
RESET).
Before starting initialization, the on-board diagnostics run a self-test program. The results of this test are
reported by eight diagnostic bytes in the RX FIFO.

NOTE
This self-test diagnostic can be skipped on
command from the program. This is covered in
Section 3.3.10.3.
The DHUll state, after a successful self-test, is as follows.
1.

2.
3.

Eight diagnostic codes are placed in the RX FIFO
The diagnostic fail bit (CSR< 13» is reset
All channels set for:
a.
b.
c.
d.
e.
f.
g.
h.
l.

j.
k.
1.

m.
n.
o.
p.

Send and receive 9 600 bits/s
Eight data bits
One stop bit
No parity
Parity odd
Auto-flow off
RX disabled
TX enabled
No break on line
No loopback
No modem control
DTR and RTS off
DMA character count zero
DMA start address zero
TX.DMA.START cleared
TX.DMA.ABORT cleared
FIFO SIZE set to 1008

3-18

The DRUII clears the MASTER.RESET bit(CSR<S» when initialization and self-test are complete.
3.3.2 Configuration
After DRUII self-initialization, the driver program can configure the module as needed. This is done via
the LPR and LNCTRL registers.
By writing to the associated LPR and LN CTRL, the program can select data rate, character length, parity,
and number of stop bits for each channel. Individual receivers and transmitters can be enabled and autoflow selected.
For operation with any device which uses modem control signals, LI1'-~K. TYPE of the associated
LN CTRL register should be set.
3.3.3 Transmitting
Data can be transferred to the serial interface by two methods. Blocks of characters can be transferred
under DMA control, or the host can write one or two characters at a time to the FIFO data register. Such
transfers are covered in the following subsections.
3.3.3.1 DMA Transfers - Before setting up the transfer of a DMA buffer, the program should make
sure that TX.DMA.START is not set. TBUFFCT, TBUFFADI, TBUFFAD2, and FIFODATA
should not be written unless TX.DMA.START is clear.
Transmission will start when the program sets TX.DMA.START.
The size of the DMA buffer, and its start address, can be written to TBUFFCT, TBUFFADI, and
TBUFFAD2 in any order. However, TBUFFAD2 contains TX.Et~A and TX.DiviA.START, so it is
simpler to write TBUFFAD2 last. By using byte operations on this register, TX.ENA and
TX.DMA.sTART can be separated. TX.ACTION, when set, indicates the UART has finished transmitting the last character.
The DRUII will perform the transfer, and set TX.ACTION when it is complete. If TXIE is set, the
program will be interrupted at the transmit vector. Otherwise, TX,ACTION must be polled to detect the
end of the D MA operation.
To abort a DMA transfer, the program must set TX.ABORT. The DRUII will stop transmission, and
update TBUFFCT, TBUFFADI, and TBUFFAD2<7:0> to reflect the number of characters which
have been transmitted. TX.DMA. START will be cleared. If the interrupt is enabled, TX.AC)'ION will
interrupt the program at the transmit vector. Ifthe program clears TX.ABORT and sets TX.DMA.START, the
transfer can be resumed without loss of characters.
If aD MA transfer fails because of a memory error, the transmission will be terminated. TBUFF AD I and
TBUFFAD2 will point to the failing location. TBUFFCT will be cleared, and TX.DMA.ERROR and
TX.ACTION will be set. If TXIE is set, the TX interrupt will be raised.
3.3.3.2 Programmed Transfers - Before writing a character or a sequence of characters to the FIFO
data register (FIFODAT A), the program should read the FIFO size register (FIFOSIZE) to check that
there is space in the TX FIFO.
If there is space for characters, they can be written as bytes (one character) or words (two characters) to
FIFODATA. After a low-byte write, FIFODATA<7:0> will be transferred to the FIFO. After a word
write, FIFODATA<7:0> and then FIFODATA<IS:8> will be transferred to the FIFO. Righ-byte
writes to FIFODAT A are not allowed.
The DRUII returns TX.ACTION when the TX FIFO becomes empty. As with DMA transfers, this bit
can be sensed via interrupt or by polling the CSR.
3-19

In programmed-transfer FIFO mode, TX.ACTION is returned when the DRUII transfers the last
character from the RX FIFO to the DUART, not when it has been transmitted. Each channel has a twocharacter buffer. Thus, if modem status bits or line parameters are changed immediately after the last
TX.ACTION of a message, the end of the message could be lost. The program can avoid loss by adding
two null characters to the end of each programmed-transfer FIFO message.
To abort a programmed transfer, the program must set TX.ABORT. The DRUII will terminate the
transfer and then set TX.ACTION. IfTXIE is set, the TX interrupt will be raised. Characters in the TX
FIFO will be discarded, but because offirmware delays the host cannot determine how many characters
have been lost.
3.3.3.3 Methods of Control- Examples of control by polling or by the use of interrupts are given in
Section 3.4, Programming Examples.
3.3.4 Receiving
Received characters, tagged with the channel number and DAT A. VALID, are placed in the RX FIFO
buffer (RBUF). Ifacharacteris put in an emptyRBUF, theDRUII sets RX.DATA.AVAIL.ltremains
set while there is valid data in there. If RXIE is set, the program will be interrupted at the receive vector.
The program's interrupt routine should read RBUF until DATA. VALID is reset.

NOTE
Subject to the RX timer, a receive interrupt is
generated when RX.DATA.AVAIL and RXIE
both become set. If the interrupt routine does not
empty the FIFO, RXIE must be toggled to raise
another interrupt.
If RXIE is not set, the program must poll RBUF often enough to prevent data loss.
3.3.5 Interrupt Control
An interrupt priority level of 5 or 6 is selected by switches on the module. During an interrupt sequence,
the D HU 11 will provide one of two vectors.
1.
2.

A 'base' vector set on the interrupt vector switches
A 'base + 4' vector

Subject to the value in RXTIMER(Section 3.2.2.3), the base vector is supplied whenever data is put into
an empty RX FIFO.
The 'base + 4' vector is supplied when:
1.

A TX FIFO has become empty. This may be because all characters have been transmitted, or
because the program has aborted the transfer.

A complete DMA block has been transferred.

A DMA transfer has been aborted, or terminated due to a memory error.

At the two vectors, the host must provide the addresses of suitable routines to deal with the above
conditions.

3-20

3.3.6 Auto XON and XOFF
X 0 N and X 0 FF codes are commonly used to control data flow on communications channels. To use this
facility, interfaces must have suitable decoding hardware or software.
A channel which receives an XOFF stops sending characters until it receives an XON. A channel which
is becoming overrun by received data, sends an XOFF. It sends an XON when the congestion is relieved.
If the DHUll is programmed for automatic flow control (auto-flow), it can automatically regulate the
flow of characters. Three bits control this function:
1.

LA,.UTO

2.
3.

FORCE.XOFF
OAUTO

LNCTRL<5>
LNCTRL<4>

IAUTO and FORCE.XOFF both control incoming characters. IAUTO is an enable bit which allows the
state of the RX FIFO counters to control the generation ofXOFF and XON codes. The FORCE.XOFF
bit is a direct command from the program.
1.

The DHUll hardware recognizes when the FIFO is three-quarters full and half full. The
firmware uses these states for auto flow control.
If the program sets a channel's IAUTO bit, the DHUll will send that channel an XOFF ifit
receives a character after the FIFO becomes three-quarters full. If the channel does not respond
to XOFF, the DHUll will send an XOFF in reply to every alternate character received. An
XON will be sent when the FIFO becomes less than half full, unless FORCE.XOFF for that
channel is set. XONs are only sent to channels to which an XOFF has been sent.

By inserting XON and XOFF characters into the data stream, the program can perform flow
control directly. However, if the DHUll is in the IAUTO or FORCE.XOFF mode, the
results will be unpredictable.
These internally generated X ON s and X 0 FF s will be transmitted even ifTX. EN A is cleared.

When FORCE.XOFF is set, the DHUll sends an XOFF and then acts as if IAUTO is set
and the FIFO is critical (was three-quarters full, not yet less than half full). When
FORCE.XOFF is reset, an XON will be sent unless the FIFO is critical and IAUTO is set
(see 1, IAUTO).

NOTE
Ifboth FORCE.XOFF and IAUTO become clear
after XOFF has been sent, an XON will be sent
immediately.
3.

If the program sets OAUTO, the DHUll will automatically respond to XON and XOFF
characters from the channel. It does this by setting and clearing the TX.ENA bit.
The program may also control the TX.ENA bit. In this case it is important to keep track of
received XON and XOFF characters.

3-21

Received XON and XOFF characters will always be reported via the FIFO. It is possible
during read/modify/write operations by the program, for the DHUll to change the TX.ENA
bit between the read and the write action. For this reason, if DMA transfers are started while
OAUTO is set, it is advisable to write to the low byte of TBUFFAD2 only.
NOTE
1.

The DUUII may change the state of
TX.ENA for up to 20 microseconds after
OAUTO is cleared by the program.

When checking for flow-control characters, the
DUUII only checks characters which do not
contain transmission errors. The parity bit is
stripped and the remaining bits are checked
for XON (218) and XOFF (238) codes.

3.3.7 Error Indication
The program is informed of transmission and reception errors by means of four bits.
1.

2.
3.
4.

TX.DMA.ERR
PARITY.ERR
FRAME.ERR
OVERRUN.ERR

CSR<12>. See Section 3.2.2.1
RBUF<12>. See Section 3.2.2.2
RBUF< 13>. See Section 3.2.2.2
RBUF<14>. See Section 3.2.2.2.

RBUF < 14: 12> are also used to identify a diagnostic or modem status code.
3.3.8 Modem Control
Each channel of the module provides modem control bits for RTS and DTR. Modem status inputs CTS,
DSR, RI, and DCD are also provided on each channel. These bits can be used for modem control or as
general-purpose outputs and inputs (see Section 3.2.2.7, STAT Register).

CTS, DSR and DCD are sampled by PROC2 every 10 ms, and also when a character is received while
LINK.TYPE (LNCTRL<8» is set. Therefore, to make sure that a change is detected, these bits must
stay steady for at least 10 ms after a change. RI is also sampled every 10 ms, but a change is not reported
unless the new state is held for three consecutive samples. There are no hardware controls between the
modem control logic and the receiver and transmitter logic. Any coordination should be done under
program control. Modem-status-change reports are placed in the RX FIFO at the correct position relative
to the received characters.
By setting LINK. TYPE (LNCTRL<8», a channel can be selected for modem operation. Any change of
the modem status inputs will be reported to the program via the RX FIFO. Modem control bits must be
driven by the program's communication routines. Control bits are written to the LNCTRL register.
Appendix B gives more detail of modem control.

3-22

By clearing LINK. TYPE the channel is selected as a 'data lines only' channel. Modem control and status
bits can still be managed by the program, but status bits must be polled at the line status register. Changes
of modem status will not be reported to the program.

NOTE
When transmitting by the programmed transfer
method, up to two characters can be buffered in
DHDll hardware. Ifmodem control bits are to be
changed at the end of a transmission, two null
characters should be added. When TX.ACTiON
is set after the second null character, the last
genuine character has left the DART.
Status change reporting is done via the RX FIFO as follows.
•

When OVERRUN.ERR, FRAME.ERR, and PARITY.ERR are all set, the eight low-order
bits contain either status change or diagnostic information. In this case:
•

If RBUF<O> = 0, RBUF<7:1> hold STAT<15:9> (see Section 3.2.2.7).

•

If RBUF<O> = 1, RBUF<7:1> hold diagnostic information (see Section 3.3.iO).

3.3.9 Maintenance Programming
As well as using on-board and external diagnostic programs, the LNCTRL register allows each channel to
be configured in normal, automatic-echo, local-loopback, and remote-loopback modes (see Section
3.2.2.8, LNCTRL).
3.3.10

Diagnostic Codes

3.3.10.1 Self-Test Diagnostic Codes - After bus reset or master reset, the DHUll executes a self-test
and initialization sequence. At the end of the sequence, eight diagnostic codes are put in the RX FIFO.
RX.DATA.A VAIL is set and MASTER.RESET is cleared.
After an error-free test, DIAG.F AIL will be reset. The 'diagnostic passed' LED will be on. If an error is
detected, D IA G. FAIL will be set and the LED will be off.
An example program which reads and checks the diagnostic codes from RBUF is included ih Section
3.4.1.

3.3.10.2 Interpretation of Self-Test Codes - All self-test codes in RBUF will have the top four bits set.
Bits < 11 :8> indicate the sequence of the diagnostic byte. That is to say, 0 = first byte, 1 = second byte,
and so on.
Figure 3-2 shows how the diagnostic code in the low byte ofRBUF should be interpreted. Table 3-3 gives
the meaning of each implemented diagnostic byte.

3-23

I ~ 0 = MODEM STATUS CODE

DIAGNOSTIC STATUS BYTE

~ 1 = DIAGNOSTIC CODE

o = PROC1 SPECIFIC ERRORS IN D4- D2
1 = PROC2 SPECIFIC ERRORS IN D4- D2

IF D7 = 1, TH EN:

o = ERROR CODES IN D4-D1
1 = DEFECTIVE CHANNEL NUMBER IN D4-D1
IF D7 = 1, THEN:
1 - - - - ' " 0 = SELF-TEST CODE IN D5- D1

'-----... 1 = BMP CODE IN D5-D1
1 - - - -. . 0 =

ROM VERSION IN D6-D2, D1 IS THE PROC No.
'-----.. 1 = DIAGNOSTIC CODE IN D6-D2, D1 IS THE PROC NUMBER
RD1824

Figure 3-2
Table 3-3

Diagnostic/Status Byte

DUUtt Self Test Error Codes

Code
(Octal)

Test

201
203
205
207
211
213
215
217
225
227
231
233
235
237

Self-test null code (used as a filler)
Self-test skipped
Interprocessor link error detected by PROC 1
Interprocessor link error detected by PROC2
Basic data-path error from PROC2
Undefined UART error
Transmit-character-FIFO logic error
Received-character-FIFO logic error
PROC1 to common RAM error
PROC2 to common RAM error
PROC 1 internal RAM error
PROC2 internal RAM error
PROC1 ROM CRC error
PROC2 ROM CRC error

The odd numbers from 2418 to 2778 indicate a UART access or function error on the channel
indicated by D4 to D 1.
If D7 = 0, the ROM version number is in D6 to D2.
D1 = PROC number (0 = PROC1, 1 = PROC2)
NOTE
Codes not shown in this table indicate undefined
errors.

3-24

After self-test, the eight codes in the RX FIFO will consist of six diagnostic codes and two ROM version
codes.
.
After an error-free test, six 201 codes and two ROM version codes will be returned.
If self-test is skipped (see next section), six 203 codes and two ROM version codes will be returned.
3.3.10.3 Skipping Self-Test - Self-test takes up to 2.5 seconds to complete. Depending on system
software, this may cause a 2.5 second hang-up. The 'skip self-test' facility allows the program to bypass
the self-test diagnostic.
There are two methods of skipping self-test.
•
•

DHVII compatible method
D HU 11 ( direct) method

The DHVII compatible method is as follows.
1.

The program resets the D HU 11.

The diagnostic firmware writes 1252528 throughout the common RAM within eight
milliseconds of reset.

The program waits 10 ms ( + or - 1 ms) after issuing reset. It then writes 0525258 throughout
the control registers (LPR, LNCTRL, TBUFFADI, TBUFFAD2, and TBUFFCT) for lines
o to 7, within the next 4 ms.

The diagnostic firmware waits until 16 ms after reset. It then checks for a 0525258 code in
common RAM.
If it finds the code, self-test is skipped. The DIAG.F AIL bit is cleared and control is passed to
the communications firmware which begins initialization.
If the code is not found, self-test begins.
NOTE
The program must not write to the CSR or the
control registers during the period starting 15 ms
after reset and ending when the MASTER. RESET
bit is cleared. This could cause a diagnostic fail
condition.

The direct method is to set SKIP(CSRbit4) andMASTER.RESET(CSRbit5) at the same time. That is
to say, write 608 to the base CSR. SKIP must not be cleared until at least 20 microseconds after it is set.
SKIP must be cleared by the host to enable the communications firmware to complete the master reset
sequence.
3.3.10.4 Background Monitor Program (BMP) - When not busy with ot..~er tasks, the DHUll '8
microcomputers perform background tests on the option. This is done by checking the timer-generated
interrupts used by the firmware (one interrupt in PROCI and two in PROC2). One of two codes is loaded
into the RX FIFO.
•
•

3058
3078

DHUII running
DHUII defective
3-25

A single diagnostic word is returned via the FIFO. The low byte contains the diagnostic code. In the high
byte OVERRUN.ERR, FRAME.ERR, and PARITY. ERR are all set to indicate that bits<7:0> do not
hold a normal character. The line number (RBUF< 11 :8» = O.
IfPROC2 stops running, PROCI will set DIAG.FAIL and will tum off the LED. The LED will stay off,
even if the fault clears. If PROC 1 stops running, PROC2 will load a 307 code into the FIFO.
Normally, the BMP will only report when it finds an error. However, if the host suspects that the DHUll
is dead, it can obtain a BMP report at any time. This is done by setting DIAG (LPR <2:1» of any
channel, to 0 1. The line number returned is that of the LPR used to request the report.
On completion of the check, the BMP will clear the 01 code in DIAG. The host should not write to the
LPR of that channel until DIAG has been cleared.
NOTE
If an error clears and then recurs, the BMP error
code will be placed in the RX FIFO each time the
error occurs.
3.4 PROGRAMMING EXAMPLES
This section contains programming examples. They are not presented as the only method of driving the
option. These programs are not guaranteed or supported.
3.4.1 Resetting the DUUII
In the following example:
•

DIAG is a routine to check the diagnostic codes. It returns with CARRY set if it detects an
error code (see Section 3.3.10).

•

The loop at 1$ can take up to 2.5 seconds, so the programmer could poll via a timer or poll at
interrupt level zero.

A ROUTINE TO RESET THE DHUll AND CHECK THAT IT IS FUNCTIONING
CORRECTLY.
DHURES: :
1$:

2$:

MOV

#40,@#DHUCSR

BIT
BNE
BIT
BNE

#40,@#DHUCSR
#20000,@#DHUCSR
DIAGER

MOV

#8.,RS

SET MASTER. RESET AND
CLEAR INTERRUPT ENABLES.
WAIT FOR MASTER. RESET TO
CLEAR.
CHECK THE DIAGNOSTICS FAIL
BIT.
NOTE:TEST INSTRUCTION IS
OK BECAUSE THERE ARE
NO TX.ACTS PENDING.
SET UP A COUNT

MOV
JSR
BCS

@#RBUFF,R0
PC,DIAG
DrAGER

GET NEXT DIAGNOSTIC CODE.
PROCESS IT.
CARRY SET ~ MJST HAVE BEEN

l\N ERROR.

3-26

SOB

R5,2$

GO BACK FOR NEXT CODE.

RTS

RETURN - CARD IS RESET.

DHUll HAS FAILED TO RESET PROPERLY, SO HALT AND WAIT FOR
THE FIELD SERVICE ENGINEER.
DIAGER: HALT
BR

DIAGER

3.4.2 Configuration
This routine sets the characteristics of channel 1 as follows.
1.
2.
3.
4.
5.

Transmit and receive at 300 bits/s
Seven data bits with even parity and one stop bit
Transmitters and receivers enabled
No modem control
No automatic flow control.

SETUP: :

3.4.3
3.4.3.1

MOV

#l,@#DHUCSR

MOV

#052560,@#LPR

MOV
MOVB

#4,@#LNCTRL
#200,@#TBFAD2+1

LOAD INDEX REG
WITH CHANNEL NO.
DATA RATE, STOP BITS,
PARITY AND LENGTH
ENABLE THE RECEIVER.
ENABLE THE TRANSMITTER.

RTS

RETURN

CHANNEL 1 DONE.

Transmitting
Programmed Transfer - The following is a program to send a message on channel 1.

The CSR is polled for TX Action reports, but a TX.ACTION interrupt could also be used.
This program functions on a DHUll with only this channel active. If other channels were active, this
program would lose TX Action reports for them. A program to control all channels would be too big to use
as an example.
A ROUTINE TO WRITE A MESSAGE TO CHANNEL 1 USING FIFO OUTPUT
MODE (PROGRAMMED TRANSFERS).
FIFOUT::
MOV

#l,@#DHUCSR

MOV
MOV

#MESS,R0
#MESIZE,Rl

POINT TO CHANNEL WE WISH
TO TALK TO.
POINT TO MESSAGE.
PUT COUNT IN

1$
(R0)+f@#FIFODATA
Rl,l$

CHECK THAT THERE IS SPACE IN
THE FIFO.
MOVE CHARACTER TO TRANSMIT FIFO
GO BACK FOR NEXT CHARACTER.

1$:
rn~mn

.10.1D

BEQ
MOVB
SOB

3-27

2$:

MESS:
MESIZE

MOV
BPL

@#DHUCSR,R2
2$

WAIT FOR TX.ACT

BIC
CMP
BNE

#170377,R2
#000400,R2
2$

ISOLATE CHANNEL NUMBER.

RTS

.ASCII

IA TRANSMIT FIFO MESSAGE FOR CHANNEL II

IGNORE THE TX.ACT IF ITS
NOT OURS (SHOULDN'T HAPPEN)
MESSAGE SENT.

.-MESS
.EVEN

3.4.3.2

DMA Transfer-

THIS PROGRAM SENDS A MESSAGE OUT ON EACH LINE OF THE DHUll AND
HALTS THE MACHINE WHEN ALL TRANSMISSIONS HAVE COMPLETED.
THE MESSAGES ARE TRANSMITTED USING DMA MODE, AND INTERRUPTS ARE
USED TO SIGNAL TRANSMISSION COMPLETION.
DMAINT: :
MOV
MOV

#TXINT,@#TXVECT
#240,@#TXPSW

SET UP THE INTERRUPT VECTORS.
INTERRUPT PRIORITY FIVE.

MOV
CLR

#16.,R0
Rl

SIXTEEN LINES TO START.
START AT LINE ZERO.

MOVB
MOV
MOV
MOV

Rl,@#DHUCSR
#DMASIZ,@#TBFCNT
#DMAMES,@#TBFADI
#100200,@fTBFAD2

INC
SOB

Rl
R0,1$

SELECT THE REGISTER BANK.
SET LENGTH OF MESSAGE.
SET LOWER 16 ADDRESS BITS.
START DMA WITH TRANSMITTER
ENABLED (ASSUME UPPER ADDRESS
BITS ARE ZERO).
POINT TO NEXT CHANNEL.
REPEAT FOR ALL LINES.

CLR
MOVB

R5
#100,@#DHUCSR+l

R5 IS USED BY INTERRUPT ROUTINE.
ENABLE TRANSMITTER INTERRUPTS.

CMP
BNE

f16.,RS
2$

WAIT FOR ALL LINES TO FINISH.

HALT
BR

1$:

2$:
3$:
ALL DONE, SO STOP.

TRANSMITTER INTERRUPT ROUTINE.
R5 IS INCREMENTED AS EACH LINE COMPLETES.
TXINT: :
.MOV
BIT
BEQ

@#DHUCSR,R0
#100000,R0
4$

GET LINE NUMBER OF FINISHED LINE.
CHECK FOR (ANOTHER) TX.ACTION.
IF NOT, GO RETURN AND WAIT.

3-28

BIT
BNE

#010000,R0
5$

CHECK FOR DMA FAILURE.
GO HALT - MEMORY PROBLEM.

INC
BR

R5
TXINT

FLAG THAT ANOTHER LINE HAS FINISHED.

4$:
RTI
5$:

HALT
BR
DMAMES:
DMASIZ

~ASCII

; MEMORY PROBLEM
5$

<15><12><7><7><7>/SYSTEM CLOSING DOWN NOW/
.-DMAMES

• EVEN

3.4.3.3

Aborting a Transmission -

THIS ROUTINE IS CALLED TO ABORT A TRANSMISSION (EITHER DMA OR FIFO)
PROGRESS ON A SPECIFIED LINE. THIS ROUTINE MAKES THE (RATHER RASH)
ASSUMPTION THAT THERE ARE NO OTHER TRANSFERS IN PROGRESS.
ON ENTRY, R0 CONTAINS THE NUMBER OF THE LINE TO BE ABORTED.
TXABRT: :
MOV
BIS

R0,@#DHUCSR
tl,@#LNCTRL

POINT TO THE CHANNEL TO BE ABORTED.
SET THE TRANSMIT ABORT BIT.

MOV
BPL
SWAB
BIC
CMP
BNE

@#DHUCSR,Rl
1$
Rl
#177760,Rl
R0,Rl
1$

WAIT FOR THE TX.ACT

BIC

#1,@#LNCTRL

CLEAR DOWN THE ABORT FLAG
FOR NEXT TIME.

RTS

BUFFER COMPLETELY ABORTED,
IF A DMA WAS IN PROGRESS, THE
DMA REGISTERS REFLECT WHERE
THE DHUll HAD GOT TO.

1 $:

3.4.4

CHECK ITS OUR LINE.
IGNORE IT IF ITS NOT (OUR
ASSUMPTION WAS WRONG!)

Receiving
THIS ROUTINE PROCESSES RECEIVED CHARACTERS UNDER INTERRUPT CONTROL.
IF AN XOFF IS RECEIVED, THE TRANSMITTER FOR THAT CHANNEL IS TURNED
OFF. IF AN XON IS RECEIVED, THE TRANSMITTER IS TURNED BACK ON. ALL
OTHER CHARACTERS ARE IGNORED.
THIS IS JUST AN EXAMPLE, A BETTER WAY TO PERFORM FLOW CONTROL IS TO
USE THE AUTOMATIC CAPABILITIES OF THE DHUll.

RXAUTO: :
MOV
MOV

SET UP THE INTERRUPT VECTORS.
PRIORITY LEVEL FIVE.

#RXINT,@#RXVECT
t240,@#RXPSW

3-29

MOV
CLR

#16.,R0
Rl

ENABLE ALL THE RECEIVERS,
STARTING AT CHANNEL ZERO,

MOVB
BIS
INC
SOB

Rl,@#DHUCSR
if:4,@#LNCTRL
Rl
R0,1$

SELECT THE LINE.
ENABLE THIS RECEIVER.
SET POINTER TO NEXT CHANNEL.

MOVB
MOV

#0,@#DHUCSR
if:20.,@#RXTIMR

SELECT CHANNEL ZERO.
SET DELAY TO 20MS.

MOVB

#100,@#DHUCSR

ENABLE THE RECEIVER INTERRUPTS.

RTS

RETURN -

1$:

INTERRUPTS DO THE RESET.

INTERRUPT ROUTINE TO DO THE MAIN TASK.
RXINT: :
MOV

R0,-(SP)

SAVE CALLERS REGISTERS.

MOV
8PL
MOV
BIC
BNE

@#RBUFF,R0
RXIEND
R0,-(SP)
#107777,(SP)+
RXNXTC

GET THE CHARACTER.
IF NO DATA VALID, WE'VE FINISHED.
CHECK FOR ERRORS, MODEM AND
DIAGNOSTICS CODES.
- JUST IGNORE THEM (BAD PRACTICS),

BIC
SWAB
BIS
MOVB
SWAB
CMPB
BNE

#170200,R0
R0
#100,R0
R0,@#DHUCSR
R0
#21,R0
1$

REMOVE UNNECESSARY BITS.
POINT TO THIS CHARACTERS LINE.
(ADD THE INTERRUPT ENABLE BIT.)
PUT CHARACTER BACK IN LOWER BYTE.
WAS IT AN "XON"?
NO - GO CHECK FOR AN "XOFF"

BISB
BR

#200,@#TBFAD2+1
RXNXTC

ENABLE THE TRANSMITTER.
GO CHECK FOR MORE CHARACTERS.

CMPB
BNE

#23,R0
RXNXTC

WAS IT AN "XOFF"?
NO - GO CHECK FOR MORE CHARACTERS.

BICB
BR

#200,@#TBFAD2+1
RXNXTC

DISABLE THE TRANSMITTER.
GO CHECK FOR MORE CHARACTERS.

MOV
RTI

(SP)+,R0

RESTORE THE DESTROYED REGISTER.

RXNXTC:

1$:

RXIEND:

3.4.5

Auto XON and XOFF

THIS PROGRAM SENDS A MESSAGE OUT ON EACH LINE OF THE DHUl1 AND
HALTS THE MACHINE WHEN ALL TRANSMISSIONS HAVE COMPLETED.
THE MESSAGES ARE TRANSMITTED USING DMA MODE, AND INTERRUPTS ARE
USED TO SIGNAL TRANSMISSION COMPLETION.
AUTOMATIC FLOW CONTROL IS ENABLED ON THE OUTGOING JATA.

3-30

TXAUTO: :
MOV
MOV

#ATOINT,@#TXVECT
#240,@#TXPSW

SET UP THE INTERRUPT VECTORS.
INTERRUPT PRIORITY FIVE.

MOV
CLR

#16.,R0
R1

SIXTEEN LINES TO START.
START AT LINE ZERO.

MOVB
BIS

R1,@#DHUCSR
#24,@#LNCTRL

MOV
MOV
MOV

#AUTOSZ,@#TBFCNT
#AUTOMS,@#TBFAD1
#100200,@#TBFAD2

INC
SOB

R1
R0,1$

SELECT THE REGISTER ~ANK.
ENABLE AUTOMATIC FLOW CONTROL
ON THE TRANSMITTED DATA.
SET LENGTH OF MESSAGE.
SET LOWER 16 ADDRESS BITS.
START DMA WITH TRANSMITTER
ENABLED (ASSUME UPPER ADDRESS
BITS ARE ZERO).
POINT TO NEXT CHANNEL.
REPEAT FOR ALL LINES.

CLR
MOVB

RS
#100,@#DHUCSR+1

RS IS USED BY INTERRUPT ROUTINE.
ENABLE TRANSMITTER INTERRUPTS.

CMP
BNE

#16.,RS
2$

WAIT FOR ALL LINES TO FINISH.

HALT
BR

1$:

2$:
3$:

ALL DONE, SO STOP.

TRANSMITTER INTERRUPT ROUTINE.
RS IS INCREMENTED AS EACH LINE COMPLETES.
ATOINT: :
MOV
BPL
BIT
BNE

@#DHUCSR,R0
2$
#10000,R0
4$

INC
RS
BR ATOINT

GET LINE NUMBER OF FINISHED LINE.
GO RETURN IF NO MORE TX.ACTIONS.
CHECK FOR DMA FAILURE.
GO HALT - MEMORY PROBLEM.
FLAG THAT ANOTHER LINE HAS FINISHED.
CHECK FOR MORE TX.ACTIONS.

2$:
RTI
4$:
HALT
BR
AUTOMS: .ASCII
AUTOSZ
.EVEN

3.4.6

; MEMORY PROBLEM
4$
<lS><12><7><7><7>/SYSTEM CLOSING DOWN NOW/
.-AUTOMS

Checking Diagnostic Codes

THIS ROUTINE CHECKS THE DIAGNOSTICS CODES RETURNED FROM THE DHU1l.
ON ENTRY, R0 CONTAINS THE CHARACTER RECEIVED FROM THE DHU11.
ON EXIT, THE CARRY BIT WILL BE CLEAR FOR SUCCESS, SET FOR FAILURE.

3-31

DIAG: :
MOV

R0,-(SP)

SAVE THE CODE FOR LATER.

BIC
CMP
BNE

#107776,R0
#070001,R0
DIAGEX

CHECK THAT IT'S A DIAG. CODE.

MOV

(SP) , R0

GET THE CODE BACK.

BITB
BEQ
CMPB
BEQ
CMPB
BEQ
CMPB
BEQ

#200,R0
DIAGEX
#201,R0
DIAGEX
#203,R0
DIAGEX
#305,R0
DIAGEX

CHECK FOR ROM VERSION NUMBER.

IF NOT, JUST EXIT NORMALLY.

SELF TEST NULL CODE.
SELF TEST SKIPPED CODE.
DHU RUNNING CODE.
ALL THE REST ARE ERROR CODES.

SEC
BR

AN ERROR CODE WAS RECEIVED, SO
SET THE CARRY FLAG.

DIAGXX

DIAGEX:
CLC

EVERYTHING OK, SO CLEAR CARRY.

DIAGXX:
MOV
RTS

3.4.7

RESTORE THE CHARACTER/INFO.

(SP)+,R0
PC

Modem Control

THIS ROUTINE WILL ANSWER A MODEM CALL, PRINT OUT A MESSAGE AND
HANG UP THE PHONE.
DMA MODE IS USED.
IF FIFO OUTPUT MODE WERE USED, THEN THE
MESSAGE WOULD NEED TO BE PADDED OUT WITH TWO NULLS DUE TO
INTERNAL BUFFERING OF THE DHUll.
MODEM: :
MOV
CLR

#16.,R0
Rl

SET UP ALL CHANNELS FOR MODEMS.

MOVB
MOVB
MOV
INC
SOB

Rl,@#DHUCSR
#125,@#LPR+l
#400,@#LNCTRL
Rl
R0,1$

POINT TO CHANNEL TO BE SET UP.
300 BPS DATA RATE.
SET MODEM DISABLE RECEIVER.
POINT TO NEXT CHANNEL.
SET UP ALL CHANNELS.

MOV
MOV
MOV
MOV
MOV

#MRXINT,@#RXVECT
#240,@#RXPSW
#MTXINT,@#TXVECT
#240,@#TXPSW
#40100,@#DHUCSR

SET UP INTERRUPT VECTORS.
(INTERRUPT LEVEL FIVE)

LET INTERRUPT ROUTINES DO
EVERYTHING

1$:

ENABLE THE INTERRUPTS.

2$:

TRANSMITTER INTERRUPT ROUTINE.

3-32

MTXINT:
MOV

R0,-(SP)

SAVE THE REGISTER WE USE.

MOV
BPL
SWAB
BIC

@#DHUCSR,R0
2$
R0
#177760,R0
#100,R0
R0,@#DHUCSR
#400,@#LNCTRL
1$

GET INTERRUPTING LINE NUMBER.
GO RETURN IF NO MORE TX.ACTIONS.
SELECT THIS CHANNELS REGISTERS.

(SP)+,R0

RESTORE THE REGISTER WE USED.

1$:

EIS
MOVB
MOV
BR

(RETAIN INTERRUPT ENABLE)
DROP DTR, RTS AND CLEAR ABORT.
CHECK FOR MORE TX.ACTIONS.

2$:
MOV
RTI

RECEIVER INTERRUPT ROUTINE.
MRXINT: :
MOV

R0,-(SP)

SAVE THE REGISTER WE USE.

MOV
BPL
MOV
BIC
CMP
BNE
MOV
SWAB
BIC
BIS
MOVB

@#RBUFF,R0
MRXEND
R0,-(SP)
#107776,R0
#070000,R0
MRXNXT
(SP) ,R0

GET INTERRUPTING LINE.
EXIT IF ALL DONE.
SAVE FOR LATER USE.
TEST FOR MODEM INFO.

MOV
BIC
CMP
BNE
BIC

(SP) , R0
#177547,R0
#230,R0
1$
#1,@#LNCTRL

MOVB

#23,@#LNCTRL+l

MOV
MOV
MOV
BR

#NOSYS2,@#TBFCNT
ttNOSYS,@ttTBFADl
ttI00200,@#TBFAD2
MRXNXT

DSR, DCD CTS NOT SET, TRY START.
CLEAR DOWN ABORT BIT (IN CASE WE
SET IT WITHOUT A DMA IN PROGRESS).
ASSERT RTS IN CASE CTS AND DSR
WERE ASSERTED AT THE SAME TIME.
OUTPUT MESSAGE.
(TRANSMITTER INTERRUPT ROUTINE
CLEARS DOWN THE CALL.)
GO LOOK FOR MORE.

BIT
BEQ
MOVB
BR

#200,R0
2$
tt23,@#LNCTRL+l
MRXNXT

CHECK FOR DSR.
NO - GO CHECK FOR NEW CALL.
ASSERT RTS.
GO LOOK FOR MORE.

BIT
BEQ
MOVB
BR

#40,(SP)
3$
#3,@#LNCTRL+l
MRXNXT

CHECK FOR RING INDICATOR.
NO - GO CLOSEDOWN CALL.
ASSERT DTR.
GO LOOK FOR MORE.

EISB

#l,@iLNCTRL
#1,@#LNCTRL+l

ABORT ANY CURRENT DMA TRANSFERS.
DROP MODEM SIGNALS.

MRXLOP:

SKIP IF NOT.
SELECT REGISTERS FOR THIS LINE.

R0
#177760,R0
#100,R0
R0,@#DHUCSR

(RETAIN INTERRUPT ENABLE)
CHECK FOR READY FOR TRANSMISSION.

1$:

2$:

3$:
MOVB

3-33

MRXNXT:
TST
BR

(SP)+
MRXLOP

REMOVE SIGNALS FROM THE STACK.
GO ROUND AGAIN.

MOV
RTI

(SP)+,R0

RESTORE THE REGISTER WE USED.

.ASCII

<lS><12><7><7><7>/SYSTEM UNAVAILABLE, PLEASE TRY LATER/
.-NOSYS

MRXEND:

NOSYS:
NOSYSZ

.EVEN

3-34

CHAPTER 4
MAINTENANCE

4.1

SCOPE

This chapter explains the maintenance strategy and how the diagnostic programs are used to find a
defective field replaceable unit (FRU). The description-is--supplemented by troubleshooting flowcharts.

4.2
4.2.1

MAINTENANCE STRATEGY
Preventive Maintenance

No preventive maintenance is planned for this option. However, if the host system is being serviced, a
visual check should be made for loose connectors and damaged cables.

4.2.2

Corrective Maintenance

The M31 05 module, BC05 L-xx cables, and distribution panels are all FRU s. Corrective maintenance is
therefore based on finding and replacing the defective FRU. However, if the fault is not in the option, it
may be possible to perform tests of external equipment. Figure 4-1 can be used as a basis for
troubleshooting.
Flowcharts 4-2 and 4-4 provide recommended test sequences for PDP-II and VAX systems
respectively.

4.3

INTERNAL DIAGNOSTICS

Internal diagnostics run without intervention from the operator. There are two tests, called self-test and
background monitor program.

4.3.1

Self-Test

This test starts immediately after bus or device reset. It checks the internally accessible parts of the
DHU11 and gives a GO/NOGO indication via the CSR<DIAG.FAIL> bit and the 'diagnostics passed'
LED. Self-test also reports error or status information to the host via the RX FIFO. This information is
used by system-based diagnostics.
During a successful (no defects) self-test, the LED flashes OFF/ON/OFF before coming ON
permanently. The first OFF period is very short and may not be seen. However, if the LED goes OFF and
then comes ON permanently, the diagnostic has found no faults. If self-test is skipped (see Chapter 3,
Section 3.3.10.3), the LED will flash OFF and then come ON permanently.
Because of the limitations of self-test, a correct sequence does not guarantee that all sections of the module
are good.

4-1

STAGGERED
LOOPBACK
TEST
CONNECTIONS ~=~~~

NOTE:
STAGGERED LOOPBACK
CONNECTORS ARE NOT
POLARIZED
BC05L-xx CABLES CAN
BE INSTALLED EITHER
WAY AROUND IN J10/J11

J1D

r::::::::::::J H325

J3
M3105

OR
J2

0
H3029
BC05L-XX
CABLES

( F-(----I TERMINAL

I---~~

----....I

Figure 4-1

Troubleshooting Connection Diagram

4-2

ETC.

4.3.2

Background Monitor Program (BMP)

The BMP performs limited tests of the DHUll when the option is not engaged in other tasks. If it detects
an error, the BMP reports to the host via the RX FIFO. It also switches off the 'diagnostics passed' LED.
By writing codes to the LPR, the host can cause the BMP to report the DHUll status even if an error has
not been detected. It is used if the host suspects that the DHUll is defective.

NOTE
A full description of self-test and BMP diagnostic
codes is provided in Chapter 3, Section 3.3. i O.
4.4

XXDP+ DIAGNOSTICS

In order to run these diagnostics, the host PDP-II system must have at least the minimum configuration
specified. Loopback connectors will be needed for some of the tests. For more information, refer to the
program documentation at the beginning of the ZDHU??, ZDHV??, ZDHW??, and ZDHX?? listings.

4.4.1

ZDHU??, ZDHV??, ZDHW??, and ZDHX??

These programs form a functional verification test (FVT) which runs on UNIBUS members of the
PDP-II processor family. The test runs under the PDP-II Diagnostic Supervisor.
The minimum system requirements are:

•
•
•

•
•

UNIBUS CPU
32K bytes memory
Console terminal
XXDP+ load device with Diagnostic Runtime Services
DHUll option.

In order to test the full DMA address capability of the DHUll, the diagnostic uses the following address
patterns. If the high address lines are to be tested, the host must have memory at the following locations as
well as the 32K bytes defined in the previous paragraph.
Address bits

Memory address
(High bank)

Memory address
(Low bank)

Ifmemory is not available at these locations, some high DMA address bits will not be tested. This will not
be considered as an error. The operator, by answering a prompt, can display information specifying the
bits which were tested.
The ZDHU?? diagnostic has no loopback mode. ZDHV??, ZDHW??, and ZDHX?? function in the
following modes.
1.
2.
3.

Tntprn ~ 1 l{'\{'\nh~{'1<
......... n

... ~~ ....... ~~~ ..u

~'-''-'.t'...,

Staggered loopback
External (H325) loopback

4-3

In addition to the above, ZDHX?? has two extra modes.
4.
5.

Modem loopback
Keyboard echo

In modem-Ioopback mode the modem must be set up manually. The diagnostic will test to where the line is
looped back.
In keyboard-echo mode, received data is retransmitted. This allows the input from a terminal keyboard to
be displayed on a terminal. Modem control signals are permanently set so that modem links can also be
tested.
Each mode can be selected by answering a prompt from the diagnostic program. Example printouts,
together with a summary of the use of the diagnostic supervisor, are provided in Section 4.5.
A troubleshooting flowchart is provided in Figure 4-2.
4.4.1.1 Functions of ZDHU?? - This program checks the reset, skip self-test, and the register-access
functions. It checks the TX-enable function, bus requests, and interrupts. CSR and RXFIFO reports from
the self-test and BMP are also checked. Loopback connectors are not needed for this test.
4.4.1.2 Functions ofZDHV?? - This program checks the operation of the RX-interrupt timer and the
register bits which control the flow of data and the operation of the FIFOs. A staggered loopback
connector is needed for some of these tests.
4.4.1.3 Functions of ZD HW?? - This program verifies the correct operation of the modem controland-status lines, and checks that there is no unwanted interaction between them. The tests will only run if
one of the external loop back modes is selected.
4.4.1.4 Functions of ZDHX?? - This program checks DMA transfers and addressing, split-speed
operation, and the reporting of data errors. Modem loopback and keyboard echo tests can be selected.
ZDHX?? performs extensive data-transfer checks. One of the external loopback modes should be
selected.

NOTE
Each of these diagnostics verifies that the handshake between the D HUll and the host is operating
correctly.
4.4.2 DECX/II Exerciser
When a DHUll or other option is installed or replaced, it is necessary to run the DECX/ll exerciser
XD HU?? The exerciser must first be configured to match the host system. For more information, refer to
the DECX/ll User Manual (AC-F035B-MC) and DECX/ll Cross-Reference (AC-F055C-MC).
DECX/ll should not be run until all modules have passed their own diagnostic tests. Therefore, before
running the exerciser, the DHUll must pass all phases of the PVT.

4-4

4.5

PDP-II DIAGNOSTIC SERVICES SUMMARY

The FVT diagnostics have been written for use with the Diagnostic Runtime Services. DRS provides the
interface between the operator and the diagnostic programs. By answering parameter questions when
prompted, the operator can define the following.
1.
2.
3.

4.5.1

The hardware configuration of the D HU 11 s being tested
The type of test information to be reported
The conditions under which the test should be terminated or continued.

Loading the Diagnostic

The diagnostic program maybe loaded and started in the normal way, using any of the supported load
systems. For example, using XXDP+, the program ZDHV??BIN is loaded and started by typing
R ZDHV??
The diagnostic and the DRS will be loaded and the program started. The program types the following
message.
DRS LOADED
DIAG.RUN-TIME SERVICES
CZDHV""B-O
DHUll FUNCTIONAL VERIFICATION TEST
UNIT IS DHUll
RESTART ADDRESS xxxxxx
DR>
DR> is the prompt from the DRS. At this point a DRS command must be entered (supervisor commands
are listed in Section 4.5.3).
BO on the end of CZDHV indicates the revision level (B) and the patch level (0).

4.5.2 Four Steps to Run a DRS Diagnostic
1.

Enter the start command.
When the prompt DR> is issued, type:
STA/PASS: l/FLAGS:HOE ffi1
The switches and flags are optional.

Answer the hardware parameter questions.
The program prompts with:
CHANGE HW?
You must answer Y to this query if you want to change the hardware parameter tables. The
program will then ask a number of hardware parameter questions in sequence. For example, the
first question is:

# UNITS?

4-5

At this point, enter the number of units to be tested.

NOTE
Some versions of the DRS do not ask the
CHANGE HW? question at the first start
command. Instead they go straight into the
hardware parameter question sequence.
The answers to the questions are used to build hardware parameter tables (P-tables) in
memory. A series of questions is posed for each device to be tested. A hardware P-table is built
for each device.
3.

Answer the software parameter questions.
When all the hardware P-tables are built the program responds with:
CHANGE SW?
If other than default parameters are wanted for the software, type Y. If the default parameters
are wanted, type N.
If you type Y, a series of software questions will be asked and the answers to these will be
entered into the software P-table in memory. The software questions will be asked only once,
regardless of the number of units to be tested.

Diagnostic execution
After the software questions have been answered, the diagnostic starts to run.
What happens next is determined by the switch options selected with the start command, or
errors occurring during execution of the diagnostic.

4.5.3 DRS Commands
The DRS commands that may be issued in response to the DR> prompt are as follows.

•

START

Starts a diagnostic program.

•

RESTART

When a diagnostic has stopped and control is given back to DRS, this command
restarts the program from the beginning.

•

CONTINUE Allows a diagnostic to continue running from where it was stopped.

•

PROCEED

Causes the diagnostic to resume with the next test after the one in which it
halted.

•

EXIT

Transfers control to the XXDP+ monitor.

•

DROP

Drops units specified until an ADD or START command is given.

•

ADD

Adds units specified. These units must have previously been dropped.

•

DISPLAY

Displays P-Tables.

4-6

•
•

FLAGS

U sed to change flags.

ZFLAGS

Clears flags.

All of the DRS commands except EXIT, DISPLAY, FLAGS, and ZFLAGS can be used with switch
options.
4.5.3.1 Command Switches - Switch options may be used with most DRS commands. The available
switches and their functions are as follows.

•

/TESTS:

USed to sPecify the tests to be run (the default is all tests). An example of the
tests switch used with the start command to run tests 1 to 5, 19, and 34 to 38
would be:
DR> START/TESTS: 1-5:19:34-38 ffi)

•

/PASS:

U sed to specify the number of passes for the diagnostic to run. For example:
DR> START/PASS: 1 ffi)
In this example, the diagnostic would complete one pass and give control back
to the DRS.

•

/EOP:

U sed to specify how many passes of the diagnostic will occur before the end-ofpass message is printed (the default is one).

•

/UNITS:

Used to specify the units to be run. This switch is valid only ifN was entered in
response to the CHANGE HW? question.

•

/FLAGS:

U sed to check for conditions and modify program execution accordingly. The
conditions checked for are as follows.
:HOE

Halt on error (transfers control back to the supervisor)

:LOE

Loop on error

:IER

Inhibit error reports

:IBE

Inhibit basic error information

:IXE

Inhibit extended error information

:PRI

Print errors on line printer

:PNT

Print the number of the test being executed before execution

:BO E

Ring bell on error

:U AM

Run in unattended mode, bypass manual intervention tests

:ISR

Inhibit statistical reports

:IOU

Inhibit dropping of units by program.

4-7

4.5.4 Control Characters Supported
The keyboard functions supported by DRS are as follows.
•

eTRL/e ("e)

Returns control to the DRS. The DR> prompt would be typed in response
to CTRL/C. This function can be typed at any time.
.

•

CTRL/Z ("Z)

U sed during hardware or software dialogue to terminate the dialogue and
select default values.

•

CTRL/O ("0)

Disables all printouts. This is valid only during a printout.

•

CTRL/S (" S)

U sed during a printout to temporarily freeze the printout.

CTRL/ Q (" Q)

Resumes a printout after a CTRL/S .

4.5.5 Example Printouts
Three examples of diagnostic printouts follow. The first is error-free. In the second test, the device address
is incorrect but extended error reporting is not selected. In the third test, extended error reporting is
selected.
.
If the answer to the software question 'EXTENDED ERROR REPORTING ?' is 'N' (or default), error
reports will be 'TEST FAILED' only. For example:
'DMA-START BIT TEST FAILED'

'RXTIMER TEST FAILED'

F or more detailed reporting, the answer must be 'Y'.
Note that the question:
'NUMBER OF INDIVIDUAL ERRORS TO BE REPORTED ON A LINE ?'
will not be asked unless the previous answer was 'Y'.
Entries by the operator are underlined. An underline without an entry shows that the operator has pressed
the RETURN key to select the default parameter.
1.

Error-free pass
.R ZDHVB0
ZDHVB0.BIC
DRSD0
CZDHV-B-0
DHU-11 FUNCT TEST PART2
l!NIT IS DHU-l1
RESTART ADDR: 147670
DR>STA/PAS:1
CHANGE HW (L) ? Y

* UNITS

(D)

? 1

UNIT 0

4-8

CSR ADDRESS: (0) 160460 ?
INTERRUPT VECTOR ADDRESS: (0) 310 ?
ACTIVE LINE BIT MAP: (0) 177777?
TYPE OF LOOPBACK (l=INTERNAL, 2;H3029 OR H3277):

(0)

2 ?

CHANGE SW (L) ? L
REPORT UNIT NUMBER AS EACH UNIT IS TESTED:
EXTENDED ERROR REPORTING:
(L) N ?

(L) Y ?

CZDHV EOP 1
o TOTAL ERRORS
DR>

Test with wrong device address selected
DR>STA/PAS:l
CHANGE HW (L) ? Y

# UNITS (D) ? 1
UNIT 0
CSR ADDRESS: (0) 160460 ? 160500
INTERRUPT VECTOR ADDRESS: (0) 310 ?
ACTIVE LINE BIT MAP: (0) 177777 ?
TYPE OF LOOPBACK (l=INTERNAL, 2S=H3029 OR H3277):

(0)

2 ?

CHANGE SW (L) ?:!....
REPORT UNIT NUMBER AS EACH UNIT IS TESTED:
EXTENDED ERROR REPORTING:
(L) N ?

(L) Y ?

CZDHV DVC FTL ERROR 00101 ON UNIT 00 TST 001 SUB 000 PC: 021252
DEVICE REGISTER ACCESS ERRORS
UNIT
0 DROPPED FROM FURTHER TESTING
PASS ABRTD THS UNIT
CZDHV EOP 1
1 TOTAL ERRORS
DR>

Wrong device address selected and extended error reporting enabled.
DR>STA/PAS:1
CHANGE HW (L)

# UN ITS ( D)

? Y
? 1

UNIT 0
CSR ADDRESS:
(0)
160460? 160500
INTERRUPT VECTOR ADDRESS:
(0)
310?
ACTIVE LINE BIT MAP:
(0)
177777? 10000
TYPE OF LOOPBACK (l=INTERNAL, 2=H302~H3277):
CHANGE SW (L)

? Y

4-9

(0)

REPORT UNIT NUMBER AS EACH UNIT IS TESTED:
(L) Y ?
EXTENDED ERROR REPORTING:
(L) N ? Y
NUMBER OF INDIVIDUAL DATA ERRORS TO REPORT ON A LINE:

(D)

"?--..

CZDHV DVC FTL ERR 00101 ON UNIT 00 TST 001 SUB 000 PC: 021252
DEVICE REGISTER ACCESS ERRORS
BUS TIME-OUT TRAP CAUSED BY READ ATTEMPT
BUS TIME-OUT TRAP CAUSED BY WRITE ATTEMPT
DHU MAY BE AT THE WRONG UNIBUS ADDRESS
UNIT

0 DROPPED FROM FURTHER TESTING

PASS ABRTD THS UNIT
CZDHV EOP
1
1 TOTAL ERRS
DR>EXIT

4.6 VAX DIAGNOSTICS
VAX diagnostics for the DHU11 are:
EVDAI
EVDAH
UETP

4.6.1

Standalone diagnostic (level 3)
On-line diagnostic (level 2R)
User environmental test package (exerciser).

EVDAI Standalone Diagnostic

EVDAI is a comprehensive suite offunctional verification tests. The tests run standalone under the VAX
Diagnostic Supervisor (VDS) V6.13 or later. The diagnostic may be used:
•

•
•

F or installation tests
F or troubleshooting
As a more comprehensive confidence check.

EVDAI has five modes of operation.
1.
2.
3.
4.
5.

Internal loopback
External (H325) loopback
Staggered loopback
Modem loopback
Terminal echo

Modes 1, 2, and 3 are used to test the DHU11, whereas modes 4 and 5 are generally used to resolve
line/modem/terminal faults or compatibility problems.
The format of the START command (Section 4.6.2.2) determines which tests are to be performed. A
complete test in modes 1, 2, 3, or 4 takes about five minutes. Terminal echo runs until it is deselected.
The EVDAI diagnostic is supported by the off-line help facility EVDAI.HLP.

4.6.2

Running the EVDAI Standalone Diagnostic

The minimum hardware requirements for EVDAI are:

•

•
•

Any VAX system with a UNIBUS
A console terminal
One to eight DHU11 s.

An extra terminal would be needed to run the terminal echo test.
4-10

c~~

[:=I

~:[J~:T-------------------~
DHU11 IN
CONFIG.A

STAGGERED
LOOPBACK
CONNECTORS

UN EVD,c'-II-O-N--"
(STEP A) ALL LINES IN
STAGGERED MODE

~s_rCONFlG'C

~ REPEAT STEP A

~ INDIVIDUAL
TES~
~:S

---.t

YES

ONFIG. B. '-R-U-N-......'

TESTS 22 TO 26 ON
LINES TO BE TESTED

.&:;:..
I
I--'
I--'

H.3029

ERR?

<~
AL~

::::i~O

STAGGERED
LOOPBACK
CONNECTORS

REPLACE
_H_3_2_5_ _ _

EPLACE ASSOCITED DISTHIBUTION
PANEL

~.~--------.-----------

H3029

EXTERNAL
LINE CHECKS

MODEM LOOPBACK
OR TERMINAL ECHQ
CONFIGURATIO"I 0

Figure 4-2

Troubleshooting Flowchart for XXDP+ Diagnostics

The VAX Diagnostic System User's Guide (EK-DS780-UG) provides instructions on how to load and
run programs under the diagnostic supervisor. For details of the standalone tests, refer to the diagnostic
listing ZZ-EVDAI.
4.6.2.1 Starting Up - Before EVDAI can be run, the diagnostic supervisor must be booted. The
operator must then:

•
•
•
•

Load EVDAI
Attach the DHU11(s)
Select the device( s) to be tested
Start the diagnostic.

An example of how to attach the DHU11, and to load and run EVDAI follows. In the example, TRACE
is set to cause all tests to be reported.
DIAGNOSTIC SUPERVISOR.

ZZ-ENSAA-Y6. 13-510

8-FEB-1983 10:47:03

OS> LOAD EVDAI

load the program

DS> SET TR,H

set trace and halt on error

OS> ATTACH DHU11 DW0 TXA 760460 310 5

L Vector
BR interrupt level (range 4 to 7)
address (range 000 to 770)

The CSR address
Name unit
The option is linked to UBA
Device to be attached
ATTACH command

DS> SEL TXl\
DS> ST

4.6.2.2
a.
b.
c.

select the device for test
start the diagnostic

Options - Once the program starts, the user will be asked to select a number of options.
Lines to be tested
Line speed
Type of loopback

In the following example, default values ALL and 4800 are selected for a and b. Staggered loopback mode
is selected for c. The test starts to run when the type of loopback has been selected.
Program: DHU11 - VAX Functional Verification Test,
revision
1.0, 28 tests, at 10:55:11.30.
Testing: TXA
lines to test [(ALL) or 1,2, ••• 14,15]
Line Speed [(4800),
50,
75,
110,
134.5,
150,
300,
600,
1200,
1800, 2000, 2400, 7 200, 9600, 19200, 38400]
loop type [(INTERNAL), EXTERNAL, STAGGERED, MODEM] STAGGERED
Test 1: Device Register Address Test
Test 2: Master Reset Self test Test
Test 3: Master Reset Skip Self test Test
Test 4: Diag Field (BMP) Test
Test 5: Self test Forced Failure Test
Test 6: ROM Version Printout Test
Micro Processor number 1 ROM version is 1

4-12

Micro Processor number 2 ROM version is 1
Test 7: Register Address Test
Test 8: Id Bit Test
Test 9: Tx Enable Action
Test 10: Rx Data Available/Rx Data Valid/Rx Enable
Test 11: Maintenance Mode Test
Test 12: Rx FIFO Test
Test 13: Interrupts Test
Test 14: Byte Swapper Test
Test 15: RX Interrupt Holdoff Timer Test
Test 16: DMA Start/DMA Abort Test
Test 17: Byte Count Register Test
Test 19: Speed Test
Test 20: XON/XOFF Recognition Test
Test 21: Data Format Test
Test 2"2:--Moaem--STgnal--Te-s-t-Test 23: Framing Error/Break Bit Test
Test 24: Parity Generation/Detection Test
Test 25: Overrun Detection Test
Test 26: Exerciser Test
End of run, 0 errors detected, pass count is 1,
time is 8-FES-1983 10:58:50.63

The default selection of tests to be run is 1 to 26. A sequence of tests, and the number of passes, can be
selected via the start command.
F or example:

4.6.2.3

DS> START/PASS:3/TEST:7

3 passes, tests 7 to 26

DS> START/PASS:0/TEST:7:10

loop on test,

DS> START/TEST:5:5

1 pass, test 5 only

tests 7 to 10

Event Flags - Event flag 1 can be set to disable the ROM version number message.
DS> SET EVENT 1

4.6.2.4 Sections - Section is part of the start command. If the section is not specified, tests from 1 to 26
will be run. By specifying the section, modem loopback tests or terminal echo tests can be selected.
F or example:
DS> ST/SE:MODEM
Program:
DHUl1 - VAX Functional Verification Test, revision
1.0, 28 tests, at 11:22:10.11.
Testing: TXA
lines to test [(ALL) or 1,2, ••• 14,15]
13
Line Speed
[(4800),
50,
75,
110,
134.5,
150,
300,
600,
1200,
1800, 2000, 2400, 7 200, 9600, 19200, 38400] 2400
Put all modems into loopback mode,
type RETURN keys when done
[(No), Yes]
Y
Test 27: Modem Loop Test
•• End of run, 0 errors detected, pass count is 1,
time is 8-FES-1983 11:22:31.48
DS>

4-13

DS> ST/SEC:ECHO
Program: DHUll - VAX Functional Verification Test,
revisjon
1.0, 28 tests, at 11:25:26.34.
Testing: TXA
lines to test [(ALL) or 1,2, •••• 14,15]
14
Line Speed [(4800), 50, 75, 110, 134.5, 150, 300, 600, 1200, 1800,
2000, 2400, 7, 200, 9600, 19200, 38400] 9600

The test will run until either an error or Control Y is detected.
By pressing the break key when the terminal echo test is running, communication between terminal and
DHU11 can be proven. 'Break' causes a framing error which generates an error message.
..
Test 28: Terminal
******** DHUll Pass 1, test 28,
Hard error while

********

break key on terminal pressed

Echo Test
VAX Functional Verification Test - 1.0 ********
subtest 1, error 3, 8-FEB-1983 11:26:27.70
testing TXA: Terminal Echo Test failed

End of Hard error number 3 ********

•• Halt on error at PC 00006F7F(X)
DS>

4.6.2.5 Error Messages - An error message may indicate that the option is defective or that an illegal
parameter has been selected. Error numbers are interpreted in the diagnostic listing ZZ-EVDAI. See the
previous section (4.6.2.4) for an example of an error message.
4.6.3 EVDAH On-Line Diagnostic
This diagnostic runs in the on-line mode under VMS V4.0 or later versions. The operator interface is via
the VAX diagnostic supervisor (VDS), V6.13 or later. EVDAH provides a confidence check ofDHU11 s
in VAX/VMS systems. It consists of five tests.
1.
2.
3.
4.
5.

Internal data-Ioopback test on selected channels in sequence
Internal DMA data-Ioopback test on selected channels in sequence
Internal data-Ioopback test on selected channels at the same time
Externalloopback test (via H325) of modem control signals
External data loopback via a modem or H3 25. If a modem is used, it must be set up manually.

NOTE
Tests 4 and 5 run only when "/section=manual" is
selected at run time.
Before running EVDAH, the user should be aware of the following points.
1.

The tests are on-line, therefore it is essential to define the channels to be tested. The test will not
run if a channel which is allocated to a process is selected for testing. Channel allocations can be
checked by a Show Device command such as SH DEV/FULL TXA. In the typical response
which follows, channels 0 and 1 are free and channel 2 is allocated to job control.

4-14

Device

TXAO:

3-FEB-1984 17:02: 14.04

on line
Error count
Operations completed
Reference count
Device

TXA1:

0
3
0

Owner process id
Owner process name
Default buffer size

3-FEB-1984 17:02: 14.08

on line
Error count
Operations completed
Reference count

0
3
0

Owner process id
Owner process name
Default buffer size

0
9
1

Owner process id
Owner process name
Default buffer size

on line
Spooled
Allocated
Error count
Operations completed
Reference count

00010074

JOB CONTROL
132

If test 4 is to be run, an H325 loopback connector must be installed on the selected channel. By
setting event flag 20, the operator can cause the program to halt between channel tests. This
allows the H325 to be moved to the next channel to be tested. Another event flag (21) causes the
program to halt after each DHUll has been tested.

If test 5 is to be run, a modem or an H325 must be installed on the selected channel. The event
flags also function in this test.

If tests 4 or 5 are run without some form ofloopback installed, error messages will be generated.

In the DHUll hardware, adjacent channels are paired (refer to Chapter 1, Section 1.3.3.1).
Any attempt to change a baud rate that will change the group of an allocated channel will
generate error messages. The baud rate will not be changed.

The EVDAH diagnostic is supported by the on-line help facility EVDAH.HLP.

4.6.4 Running the EVDAH On-Line Diagnostic
The minimum hardware requirements for EVDAH are:
•
•
e

Any VAX system with a UNIBUS
A console terminal
One to eight DHUll s.

The VAX Diagnostic System User's Guide (EK-DS780-UG) provides instructions on how to load and
run programs under the diagnostic supervisor. For details of on-line tests, refer to the diagnostic listing
ZZ-EVDAH.

4-15

4.6.4.1

•
•
•
•
•
•

Starting Up - Before EVDAH can be run, VMS must be booted. The operator must then:

Log into the system maintenance account
Allocate the lines to be tested
Load the diagnostic supervisor
Attach the DHUll(s)
Select the device( s) for test
Start the diagnostic.

An example of how to attach the DHUll and to load and run EVDAH follows. Where appropriate,
commands for different systems are included.
$ ALL TXAO

Allocate lines to be tested

$ ALL TXAI
$ ALL TXA2
$ RUN ESSAA
or
$ RUN ECSAA
or
$ RUN ENSAA

For

(11/780), Supervisor

For

(11/750)

For

(11/730)

DIAGNOSTIC SUPERVISOR ZZ-ENSAA-Y6. 13-510 27-JAN-1984 12:00: 00.00
OS> ATT DW780 S81 DW0 3 4
For 11/780 Attach the UBA on the SBr
or
DS> ATT DW750 HUB DW0
For 11/750
or
DS> ATT DW730 HUB DW0
For 11/730
DS> LOAD EVDAH
DS> ATT DHUl1
DEVICE LINK? DW0
DEVICE NAME? TXA

VECTOR? 300
BR? 5

Load the DHUl1 diagnostic
Attach the DHUll
The option is linked to the UBA
The option named unit:
( range=A-F)
The CSR address:
(range=760000-777776)
Vector address: (range=000-770)
BR Interrupt Level: (range=4-7)

OS> SEL TXA:
DS> START

Select Unit Under Test
Start diagnostic execution

CSR? 760460

The program should now be running
If preferred, the Attach command and parameters can be input as one statement. The following is an

example of such a single-line entry.
DS>ATTACH DHUll DW0 TXA 760460 300 5

L-_ BR interrupt level (range = 4 to 7)

Vector address (range = 000 to 770)
The CSR address
I
Name unit (range = A to H)
The option is linked to DBA
~------------ Device to be attached
' - - - - - - - - - - - - - - - - - - ATTACH command

L - .-

L-_ _ _

L...--_ _ _ _ _ _ _

L...-_ _ _ _ _ _ _ _ _

4-16

4.6.4.2

Options - Once the program starts, the user is asked to select a number of options.

1.
2.
3.
1.

Lines which are to be tested
Baud rate
Type of loopback

Lines which are to be tested
The following question will be displayed.
Lines to test [(ALL),REV,EVE,ODD,O,1,2,3,4,S,6,1,8,9,lO,11,12, 13,14,lS]
Various responses can be given.
ALL

Test all lines (0 to IS) in ascending order. This is the default (press the RETURN
key only).

REV

Test all lines (15 to 0) in descending order.

EVE

Test lines 0, 2, 4, 6, 8, 10, 12, and 14.

ODD

Test lines 1, 3,5,7,9, 11, 13, and 15.

Test line n (where n can be any line number).

n,m

Test lines n,m (where n,m can be any combination of line numbers; for example,
0,15,3,7,1 ). The lines will be tested in the sequence entered.

Any invalid entry will display an error message:

?? Invalid response
followed by a reprompt of the input request.
2.

Baud rate
The following question will be displayed.
Baud Rate [(9600),50,75,110,134,150,300,600,1200,1800,2000,2400,4800,7200,19200,
38400]
One of two responses can be given.
n

- A specific value

(BID

The default rate (9 600 bits/s)

Any invalid entry will display an error message:

?? Invalid response
followed by a reprompt of the input request.

4-17

Type of loopback
The following question will be displayed:
Loop Type [(INTERNAL), MODEM, H325]
Various responses can be given.
INTERNAL

Internalloopback will be used in the test. This is the default response (press
the RETURN key only.

MODEM

A modem preset to loopback.

H325

Externalloopback connector is to be used.

Any invalid entry will display an error message:

?? Invalid response
followed by a reprompt of the input request.

4.6.4.3 Event Flags- Event flags are used to control multichannel ormulti-DHU11 tests. Flags are set
by the Set Event command. For example:
os> SET EVENT 20
Event flag 20

Functions in tests 4 and 5 only. When flag 20 is set, the program is
suspended after each channel is tested. A supervisor message will invite
the operator to transfer the H325 or modem to the next channel to be
tested.

Event flag 21

Functions in all tests. It is useful when more than one DHU11 is being
tested. Event flag 21 has different functions in internal and external
loopback tests.

Test

Flag 21

Function

1 to 3

Only the first DHU11 selected is tested.

1 to 3

All DHU11 s are tested in the selected order. Console messages indicate the
module under test. For example:
INTERNAL LOOPBACK ON UNIT 000
INTERNAL LOOPBACK ON UNIT 001
INTERNAL LOOPBACK ON UNIT 002
INTERNAL LOOPBACK ON UNIT 003

4 and 5

Only the first DHU11 selected is tested.

4 and 5

The program is suspended before each module is tested. Console messages
warn the user to transfer the H325 or modem.

4-18

4.6.4.4 Sections - Section is part of the start command. If the section is not specified, the default is tests
1, 2, and 3. If the section is specified as MANUAL, tests 4 and 5 are selected. For example:
DS> START
DS> START/SEC=MANUAL

runs tests 1, 2, and 3
runs tests 4 and 5

'I.O.'I.~

Error iviessages - If an error is detected during test, the program will output an error message.
This may indicate that the option is defective or that an illegal parameter has been selected. Error numbers
are interpreted in the diagnostic listing ZZ-EVDAH. The error messages below were generated by
running tests 4 and 5 with the incorrect loopback mode selected.
Test 4: Test 4 - Modem Signal Loopback
******** DHUll 16 LINE ASYNC MUX TEST - 1.0 ********
Pass 1, test 4, subtest 0, error 2,
3-FEB-1984 15:50:21.44
S-y-s1:em-fatal errOT -wht-le test-ing -'fXA: IffVAt-Ifl- t-otWB-Ae-K---s-Et--Ee-'fEfr

********

End of System fatal error number 2 ********

[aborted]
Test 5: Test 5 - External Data Loopback
******** DHU11 16 LINE ASYNC MUX TEST - 1.0 ********
Pass 1, test 5, subtest 0, error 2,
3-FEB-1984 15:50:22.71
System fatal error while testing TXA: INVALID LOOPBACK SELECTED

******** End of System fatal error number 2 ********
[aborted]
•• End of run, 0 errors detected, pass count is 1,
time is 3-FEB-1984 15:50:23.89
DS>

4.6.5 VAX Test Sequence
The precise sequence of diagnostic tests will depend on the state of the system and the fault which has been
reported. If the system is on-line, it might be easier to run EVDAH before EVDAI. However, if it is offline, EVDAI would probably be run immediately.
4.6.5.1 EVDAH Test Sequence - Figure 4-3 gives an example ofH3029 distribution panels connected
to a DHUl1. A Show Device command would be used to check for 'owners' of channels 0, 1, and 2.
With the allocation shown:
a.
b.
c.

Run tests 1, 2, and 3 on lines 3 to 15
Run test 4 on lines 3 to 15
Put the modem in loopback mode. Run test 5 on channels 1, and 3 to 15.
NOTE
The event-flag facility would be useful for band c.

4-19

ALLOCATED
FREE

0
1
2
3

ALLOCATED

4
5
6
7

TO
M3105

8
9
10
11

ALL
FREE

12
13
14
15

J
po' 78'

Figure 4-3

Example of Channel Allocation

4.6.5.2 EVDAI Test Seque.nce - Most of the EVDAI diagnostic will run in staggered loopback mode.
Therefore, unless individual channel problems are indicated, tests should start with this mode.
A troubleshooting diagram and a flowchart are provided by Figures 4-1 and 4-4. The flowchart shows a
complete sequence that also checks the distribution panel and loopback connectors. However, if the initial
test of all tines in staggered mode is error-free, the option is probably good.

4.7 FIELD REPLACEABLE UNITS (FRUs)
The FRUs are:
Reference No.ltem
M3105
BC05L-xx
H3029
H325
H3277

Hex-height module
Flat cable, 40-conductor
Distribution panel (includes staggered loopback connector)
Line loopback connector
Staggered loopback connector (if supplied).

Depending on local maintenance strategy, modems and/or external cables may also be FRUs. See
Figure 4-1.

4-20

csw~
~,~~--------------------~

[ g~~~;~~
CONFIG.A

ERROR

jINDT~I~~
NO

STAGGERED
LOOPBACK
CONNECTORS

HIGH CHANS

4·7

OR 12·15

(STEP A) IN SEQUEI\ICE IN
STAGGERED MODE

LOW CHANS

0·3
OR 8·11

UN ALL 4 TESTS'

~7[ES

H3029
J10

J2 OR J4

J11

CONFIGURATION A
SWAP CABLES
CON FIG. C.
REPEAT STEP A

o OR 8

.,.

1 OR 9
2 OR 10
3 OR 11
4 OR 12
5 OR 13
6 OR 14
7 OR 15

LINI~
YES

J2 OR J4

_
CONFIGURATION B

H3029

STAGGERED
LOOPBACK
CONNECTORS

REPLACE

H325

CONFIGURATION C

H:3029
J10
Y

EXTERNAL
LINE CHECKS

MODEM LOOPBACK
OR KEYBOARD ECHQ

J11

CONFIGURATION D

Figure 4-4

EVDAI Troubleshooting Flowchart

APPENDIX A
GLOSSARY OF TERMS
A.I SCOPE
This appendix contains a glossary of terms used in this manual. The terms are in alphabetical order for
easy reference.
A.2

GLOSSARY

asynchronous A method of serial transmission in which data is preceded by a start bit and followed by
a stop bit. The receiver provides the intermediate timing to identify the data bits.
auto-answer

A facility of a modem or terminal to automatically answer a call.

auto-flow Automatic flow control. A method by which the DHUll controls the flow of data by means
of special characters within the data stream.
backward channel A channel which transmits in the opposite direction to the usual data flow.
Normally used for supervisory or control signals.
base address
BMP

The address of the CSR.

Background Monitor Program.

CCITT Comite ConsultatifInternational de Telephonie et de Telegraphie. An international standards
committee for telephone, telegraph, and data communications networks.
dataset
DIL

See modem.
Dual-In-Line. The term describes ICs and components with two parallel rows of pins.

D MA Direct Memory Access. A method which allows a bus master to transfer data to and from
system memory without using the host CPU.
DUART Dual Universal Asynchronous Receiver Transmitter. An IC used for transmission and
reception of serial asynchronous data on two channels.
duplex

A method of transmitting and receiving on the same channel at the same time.

EIA Electrical Industries of America. An American organization with the same function as the
CCITT.
EMC

Electro-Magnetic Compatibility. The term denotes compliance with field-strength, susceptibility,

an.d static discharge stfu'1dards.

FCC Federal Communications Commission. An American organization which regulates and licenses
communications equipment.
A-I

FIFO
First In First Out. The tenn describes a register or memory from which the oldest data is
removed first.
floating address
A CSR address assigned to an option which does not have a fixed address allocated.
The address is dependent on other floating address devices connected to the bus.
floating vector An interrupt vector assigned to an option which does not have a fixed vector allocated.
The vector is dependent on other floating vector devices connected to the bus.
FRU

Field Replaceable Unit.

GO/NOGO

A test or indicator which defines only an 'error' or 'no error' condition.

Integrated Circuit.

I/O

Input/Output.

LSB

Least Significant Bit.

LSI-II bus

Another name for the Q-bus.

microcomputer An IC which contains a microprocessor and peripheral circuitry such as memory, I/O
ports, timers, and U ARTs.
modem
The word is a contraction of MOdulator DEModulator. A modem interfaces a terminal to a
transmission line. A modem is sometimes called a dataset.
MSB

Most Significant Bit.

multiplexer
NPR

A circuit which connects a number of lines to one line.

Non-Processor Request. Requests for control of the UNIBUS for DMA transactions.

null modem
A cable which allows two tenninals which use modem control signals to be connected
together directly. Only possible over short distances.
PCB

Printed Circuit Board.

protocol

A set of rules which define the control and flow of data in a communications system.

PSTN

Public Switched Telephone Network.

Q-bus

A global tenn for a specific DIGITAL bus on which the address and data are multiplexed.

RAM

Random Access Memory.

RFI

Radio Frequency Interference.

ROM

Read Only Memory.

SPC

Small Peripheral Controller.

split-speed
A facility of a data communications channel which can transmit and receive at different
data rates at the same time.

A-2

UART Universal Asynchronous Receiver Transmitter. An Ie used for transmission and reception of
serial asynchronous data on a channel.
UNIBUS

A DIGITAL bus, common to a number of PDP-II and VAX systems.

XOFF A control code (238) used to disable a transmitter. Special hardware or software is needed for
this function.
XON

A control code (218) used to enable a transmitter which has been disabled by an XOFF code.

A-3

APPENDIX B
MOUhM CONIKOL
B.I SCOPE
This appendix contains information useful to both the programmer and the engineer. It defines control
signals, describes typical modem control methods, and warns against likely network faults. A detailed
example of auto-answer operation is included.
B.2 MODEM CONTROL
The DHUll supports sufficient modem control to permit full-duplex operation over the public switched
telephone network (PSTN) and over private telephone lines. Table B-1 lists the control leads supported by
the DHUl1, together with an explanation of their use and purpose. In this appendix, the terms MODEM
and DATASET have the same meaning. They refer to the device which is used to modulate and
demodulate the signals transmitted over the communications circuits.
The DHUll modem control interface can be used in many applications. These include control of serial
line printers, terminal cluster controllers, and industrial II 0 equipment, in addition to the more usual
applications in telephone networks. Use of the control leads described in Table B-1 is therefore
completely application dependent, although there are international standards which telephone network
applications should obey. There are no hardware interlocks between the modem control logic and the
transmitter and receiver logic. Program control manages these actions as necessary.
A subset of the leads listed in Table B-1 could be used to establish a communications link using modems
connected to the switched telephone network. Ring Indicator (RI), Data Terminal Ready (DTR), and
Data Carrier Detected (DCD) are the absolute minimum requirements. In some countries Dataset Ready
(DSR) is also needed. It is usually desirable, however, to implement modem control protocols which will
operate over most telephone systems in the world. Also, some protection should be included to guard
against network faults, particularly in applications such as dial-up time-sharing systems. Such faults
include:
•

Making a channel permanently busy (hung) because of a misdialed connection from a non-data
station

•

Connecting a new incoming call on an in-use channel. This fault might occur, for example, after
a temporary carrier loss, if the host system assumed that the carrier was reasserted by the
original caller.

Modem control with some protection against common faults, and which is compatible with the telephone
networks in most geographic areas, can be implemented by using all the signals listed in Table B-1, in the
way described by the CCITT V.24 recommendations. Section B.2.1 describes a method of implementing
a full-duplex auto-answer communications link via modems over the PSTN. It is provided here only to
show the operation and interaction of DHUll modem control leads in a typical application.

B-1

Table B-1
Name

RS-232-C V.24

Modem Control Leads

25-Pin

Definition

Protective ground. This provides a path between the
modem and DRUll for discharge of potentials such as
static electricity.

GND

102

Signal Ground. This is a reference level for the data and
control signals used at the EIA interface.

TXD

103

From DRUll to modem. This signal contains the
serial bit stream to be transmitted to the remote station.

RXD

104

From modem to DRUIL This signal is the serial bit
stream received by the modem from the remote station.

RTS

105

From DRUll to modem. Causes the modem's carrier
to be placed on the line.

CTS

106

From modem to DRUll. Indicates that the modem
has successfully placed its carrier on the line and that
data presented on circuit BA will be transmitted to the
communication channel.

DSR

107

From modem to DRUll. Indicates that the modem
has completed all call establishment functions and is
successfully connected to a communications channel.

DTR

108/2

From DRUll to modem. Indicates to the modem that
the DRUll is powered up and ready to answer an
incoming call.

DCD

109

From modem to DRUll. Indicates to the DRUll that
the remote station's carrier signal has been detected and
is within appropriate limits.

125

From modem to DRUll. Indicates that a new incoming
call is being received by the modem.

B.2.1 Example of Auto-Answer Modem Control for the PSTN
The system operator determines which DRUIl channels should be configured for either local or remote
operation. Local operation implies control of data-leads only, while remote operation implies that modem
control will be supported. The host software will assert DTR and RTS together with the Link Type bit in
the LNCTRL register for all DRU 11 channels configured for remote operation. DTR informs the modem
that the DRUll is powered up and ready to acknowledge control signals from the modem. RTS is
asserted for the full-duplex mode of operation and causes the modem to place its carrier on the telephone
line when the modem answers a call. Link Type (LNCTRL<8» enables modem status information to be
placed in the receive character FIFO where it will be handled by an interrupt service routine. Modem
status changes are always reported in the STAT register regardless of the state ofLNCTRL<8>, The
modem is now prepared to auto-answer an incoming call.

B-2

Dialing the modem's number causes RI to be asserted at the EIA interface. This informs the DHUll that
a new call is being received. RI has to be in a stable state for at least 30 ms or else the change will not be
reported by the DHUll. Since DTR is already asserted, the modem will auto-answer the incoming call
and start its handshaking sequence with the calling station. The time needed to complete the handshaking
sequence can be in the order of tens of seconds if fallback-mode speed selection and satellite links are
involved. The modem will assert DSR to indicate to the DHUll that the call has been successfully
answered and a connection established.

NOTE
On some older types of modem used on the PSTN,
the opposite effect is also true. The RI signal may
be very short, or it may not even occur if DTR is
previously asserted. When this type of modem
answers an incoming eall it asserts DSR almost-immediately and deasserts RI at the EIA interface.
Programs must therefore expect RI or DSR or
DeD as the first dataset status change received
from the modem when establishing a connection.
As RTS was previously asserted, the modem's carrier will be placed on the line when DSR is asserted.
When the modem has successfully placed its carrier on the line it will assert CTS which indicates to the
DHUll that it may start to transmit data. Should the incoming call be the result of a misdialed number
then it is possible that a carrier signal would never be received. To guard against this, the host starts a timer
when it detects RI or DSR. This is usually in the range of 15 to 40 seconds, within which time the carrier
must be detected. When the modem detects the remote modem's carrier signal on the line, it will assert
DCD which indicates to the DHUll that data is valid on the RXD line.
The modem may now exchange data between the DHUll and the calling station for as long as DCD,
DSR, and CTS stay asserted. If any of these three signals disappear, or if RI should be detected during
normal transmission, it would indicate a fault condition. A change of state of any of these signals would
cause an interrupt via the receive FIFO.
The handling of the fault conditions now becomes country-specific as some telephone systems tolerate a
transient carrier loss while others do not. In the USA it is usual to proceed with a call if carrier resumes
within two seconds. In non-USA areas it is possible for telephone supervisory signals, such as dial-tone, to
be misinterpreted by the modem as a resumption of carrier. In this case the host program would assume
that the connection had been reestablished to the original caller and would cause a 'hung' channel. To
prevent this, DTR should be deasserted immediately after the loss of DCD, CTS, or DSR to abort the
connection. DTR should stay deasserted for at least two seconds, after which time a new call could be
answered.

B-3

Digital Equipment Corporation. Bedford, MA 01730