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EK-DB11A-TM

August 1974

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Document:	DB-11A Bus Repeater Manual
Order Number:	EK-DB11A-TM
Revision:	000
Pages:	20
Original Filename:	http://bitsavers.org/pdf/dec/unibus/EK-DB11A-TM-002_DB-11A_Bus_Repeater_Manual_Aug74.pdf

OCR Text

DB11-A
bus repeater

manual

EK-DBIIA-TM-002

DB11-A

bus repeater
manual

DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS

1st Edition, October 1971
2nd Printing, January 1972
3rd Printing, June 1972
4th Printing, Decem ber 1972
5th Printing, February 1973
6th Printing, (Rev) May 1974
7th Printing, August 1974

The material in this manual is for informational
purposes and is subject to change without notice.

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
UNIBUS

PDP
FOCAL
COMPUTER LAB

CONTENTS
Page
CHAPTER 1 GENERAL DESCRIPTION

1.1
1

,.,

! .L.

1.3

1-1

Introduction
FU!lctio!lal Descriptio!!
DB 11 Specifications

1-1
1-3

CHAPTER 2 INSTALLATION PLANNING

2.3

Bus and Power Connections

2-1
2-1
2-1

2.4

ACLO and DCLO Signals

2-2

2.5

Installation Testing

2-2

2.1

Introduction

2.2

Physical Description

CHAPTER 3 DETAILED DESCRIPTION
3.1

Introduction

3-1

3.2

Bus Repeater Logic

3-2

3.3

Unidirectional Line Logic

3-4

3.4

A Line Logic

3-4

3.5

D Line Logic

3-4

CHAPTER 4 MAINTENANCE
4.1

Introd uction

4-1

4.2

Procedures

4-1

iii

ILLUSTRATIONS

Art No.

Title

Figure No.

Page

1-1

DB 11 Bus Repeater Block Diagram

11-0655

1-2

2-1

DB 11 System Unit Layout

11-0654

3-1
3-2
4-1

A Line Logic Circuit
D Line Logic Circuit

11-0653
11-0652

2-2
3-5

Test Configuration

11-0651

3-5
4-1

TABLES
Table No.
1-1
3-1

Page

Title
DB 11 Specifications

1-3

Unibus Signals

3-1

FOREWORD

This manual provides the user with the theory of operation and logic diagrams necessary to understand and
maintain the DB Il-A Bus Repeater. The level of discussion assumes that the user is familiar with basic digital
computer theory and basic PDP-II operation.
Although PDP-II Unibus signals and data are transferred through the DB 11, this manual does not cover operation of the PDP-II System or the Unibus. A detailed description of the PDP-II is presented in the applicable
PDP-II system manual; a detailed description of the Unibus is presented in the PDP-ll Peripherals Handbook.

This manual is supplied with each DB 11. Throughout this manual various engineering drawings are referenced.
A reduced set of engineering drawings is contained in a separate document entitled DBll-A Bus Repeater Engineering Drawings. This document reflects the updated drawings for the DB 11 at the time the equipment is
shipped and is to be used in conjunction with the DB ll-A Bus Repeater Manual.
This manual is divided into four chapters:

a.
b.
c.

general description
installation planning
detailed description
maintenance

CHAPTER 1
GENERAL DESCRIPTION

1.1 INTRODUCTION

The PDP-II Unibus is capable of handling 18 unit loads (including a DB II-A). The DB II-A Bus Repeater (hereafter referred to as DBll) allows the Unibus to be extended beyond 20 unit loads. An additional 18 unit loads
can be attached to the Unibus using the bus repeater. The bus repeater does not affect the bus cycle time (it adds
zero time) of any device before the DB 11, and it adds a maximum of 375 ns to the cycle time of devices addressed beyond the bus repeater. Though the Unibus is bidirectional, the DB 11 is not symmetrical, and therefore,
the processor must be on the input side (or left side) of the repeater. This is necessitated by certain one-direction
Unibus signals that are implemented in only one direction by the DB 11. All signals that must be bidirectional are
so implemented by the bus repeater.
1.2 FUNCTIONAL DESCRIPTION

The DB 11 is a non-programmable device that interfaces two buses (left and right) in four sections:

a.
b.
c.
d.

Bus Repeater Control
Bus D (data) Lines
Bus A (address) Lines
Bus Unidirectional Lines.

For a detailed description of the Unibus lines refer to the PDP-il Peripherals Handbook. Figure 1-1 shows the
DB 11 interfacing two buses or bus sections (refer to Table 1-3 for Unibus signals). The unidirectional lines are
directly interfaced; the signals between the buses are independently interfaced. The D and A lines interface data
and addresses on the bus through enabling signals generated in the Bus Repeater Control. Thus, the Unibus is
controlled through the DB 11 Bus Repeater Control.
The DB 11 Bus Repeater Control uses the Bus Busy (BBSY) signal of the Unibus as the master controlling signal
of the DB 11 logic. The DB 11 buffers the BBSY signal, enabling it to be bidirectional between the input and output bus. The BBSY signal is used to determine the direction to enable the bus address (A) line circuits. Because
the bus master is always asserting the A lines on the bus, the direction of BBSY through the DB 11 enabling logic
directs the bus A lines through the bus repeater. The BBSY signal combines with bus control line 1 (C 1) and the
interrupt bus signal (lNTR) to determine the direction of the bus D lines. For a DATI bus operation (bus C 1 and
CO both a zero), the bus D lines are enabled by the DBII toward the bus master device. For an INTR signal the
bus D lines are enabled by the DB 11 to the processor. Slave Sync (SSYN) is enabled through a bidirectional circuit. All one-direction bus signals are gated through the logic without a determination of direction by the DB 11.
These signals are:

1-1

AC LO, INTR, SACK

AC LO. INTR, SACK
BUS
REPEATER
CONTROL

C<1:0>, MSYN, SSYN, PA, PB, DClO

C<1 :0>, MSYN, SSYN, PA, PB. DelO

INIT

INIT, NPG
(M72131
NPG. BGBUF <7:4>

I
BUSY

BUS BUSY
(M7248)

BUSY

l.LJ

en
a::
0
en
en

A liNE
ENABLES

l.LJ

ADDRESS
LINES

A <17:00>

a::

a:: I

D LINE ENABLES

....u.

l.LJ
...J

en
m

::;)

DATA
LINES

0<15:00>

z::;)

0<15:00>

(4, M785)

::;)

....

(3, M7212)

Il.

::;)

A <17:00>

I
I

BG BUF <7:4>

NPR

I'VI'"

UNIOIRECTONAL
LINES
BR<7:4>

BR<7!4>

BG<7:4>

BG<7:4>
(M783. M784)

'IIi

'7
11-0655

Figure 1-1

DB 11 Bus Repeater Block Diagram

1-2

a.
b.
c.

INIT
INTR
all Grant
all Bus Request (BR)
SACK
ALCO

The DCLO signal must be bidirectional because the power fail signal can be coming from either side of the buffer;
thus, the DCLO signal must be buffered in the same manner as the BBSY signal.
1.3 DBll SPECIFICATIONS
The DB 11 specifications are listed in Table 1-1.
Table 1-1
DB 11 Specifications
Specification

Description

Bus Timing

Time added to bus cycles with master and
slave on the same side.

Zero

Time added to bus cycles with master and
slave on different sides.

375 ns (worst case)

MSYN signal

This signal arrives at the device 150 ns after
the address lines have asserted. (The A lines
remain until the MSYN signal drops.)

SSYN
signal
u

This signal
arrives no more than 75 ns befor data is asserted to the device.

INTR signal

This signal arrives at the processor no
more than 75 ns before data is asserted.

Bus Load

The DB 11 Bus Repeater represents 2 unit
loads to the primary bus (input side).

Power Requirements
Power Dissipation

At +5V. 3.2A

Environmental Limits
Temperature

Relative Humidity

+40°F to 120°F
Up to 95%

1-3

CHAPTER 2
INSTALLATION PLANNING

2.1 INTRODUCTION
The information necessary to install the DB 11 and to achieve operational status is contained in this chapter. A
physical description of the DB 11 bus and power connections, and installation testing are also included in this
chapter.
2.2 PHYSICAL DESCRIPTION
The DB 11 occupies one PDP-II System unit within the PDP-II mounting box. Each DB 11 Bus Repeater comprises the following:
a.

b.
c.
d.
e.

f
g.

h.
i.

a PDP-II System unit
four M785 Transceiver Modules
a M783 Drivers Module
a M784 Receivers Module
three M7212 Address Buffer Modules
a M7213 Buffer Master Module
a M7248 Unibus BBSY Repeater Module
two M920 Bus Connector Modules
two M930 Bus Terminator Modules

These modules are positioned in the PDP-II System unit as shown in Figure 2-1. (Refer to engineering drawing
D-MU-A-OI for module system utilization diagram.)

2.3 BUS AND POWER CONNECTIONS
The DB 11 bus connections on each side of the bus repeater are provided by two M920 Bus Connector Modules.
The M920 Module is a jumper module that connects the PDP-II Unibus and the PDP-II system units. Two
M920 Modules connect the bus to the DB lIon the output and input side.
On each side of the DB 11, a M930 Bus Terminator Module is used to terminate the bus. (Refer to engineering
drawings D-IC-DB II-A-04 and D-BD-DB II-A-05 for cable connectors.) This prevents the bus from running
through the system unit, which is the case for normal interfaces. All bus information (bus lines) is forced to be
passed through and controlled by the DB 11 logic. For detailed descriptions of the M920 and M930 Modules refer to the PDP-II Peripherals Handbook.

2-1

OUTPUT SIDE

"""v

rr
A

'1/1.

,..,..-

M920
A4

BUS CONN
_B_4_
M785

M785

E4
--

F4
--

BUS TERM

TRANS CVR

M7213

M785
• E3

M930
C4

t----

PWR CONN

M930
A2

BUFFER MASTER

TRANS CVR

M784
E_2_

M783
_F_2_

RCVRS

DRIVERS

_ D_2_

TERM

BUS

M7248
C1
-BUS BBSY
I--

10-

M920
A4

BUS CONN
_B_4_

M785
F3
--

M7212
01

M7212
E1

ADD BUF

INPUT SIDE (PROCESSOR)

M7212
F1
-ADD BUF

11- 0654

Figure 2-1 DB 11 System Unit Layout

Power is supplied to the DB 11 logic through the PDP-II System unit power connection. When power is supplied
to the PDP-II system, the DBIIIogic also receives power. This power connection is discussed in detail in the
PDP-ll Peripherals Handbook.
2.4 ACLO AND DCLO SIGNALS
To retain the power fail capabilities of a system when installing the DBII-A, special attention must be given to
the ACLO and DCLO signals. Engineering Change Order (ECO) DBIIA-OOOOS and G772-00001 must be
installed in the equipment.
The WI and W2 jumpers on the G772 must be cut for all system unit slots except the forwardmost system unit
slot in the box. Cutting these jumpers allows the ACLO and DCLO signals for this mounting box and its
associated power supply to be properly forwarded to the processor. Also, it permits the ACLO and DCLO
signals from boxes behind the DB 11-B repeater to be forwarded throug..h the OB I1-B repeater to the processor,
The DBII-B can then be installed in any of the system unit positions without causing power fail problems.
2.5 INSTALLATION TESTING
The DB 11 is tested to ensure that the unit has been properly installed and is complctc1'y opcrational. This is
accomplished by performing the test in Chapter 4 (Paragraph 4.2).

2-2

CHAPTER 3
DETAILED DESCRIPTION

3.1

INTRODUCTION

The DB II interfaces the Unibus signals between the processor bus side (left) and the extended bus side (right)
through four logical units. These units are:

b.
c.
d.

the Bus Repeater Logic (M7213 and M7248 Modules)
the Bus Repeater A Line Logic (three M7212 Modules)
the Bus Repeater D Line Logic (four M785 Modules)
the Bus Repeater Unidirectional Lines Logic (M783 and M7 84)

Table 3-1 lists the signals interfaced by each logical unit, as well as its source and destination. For a detailed description of the bus signals ;efer to the PDP-}} Peripherals Handbook.
Table 3-1
Unibus Signals
Name

Source

Mnemonic

Destination

BUS REPEATER CONTROL (M7213, M7248) SIGNALS INTERFACED
Data Transfer Signal (for transfer of data to or from master)
Control
Master Sync
Slave Sync

C (1 :0)
MSYN
SSYN

Master
Master
Slave

Slave
Slave
Master

Priority Transfer Signals (for transfer of bus control to a priority selected master)
Selection Acknowledge
Bus Busy (M7248)
Interrupt

SACK
BBSY
INTR

Next Master
Master
Master

Processor
All
Processor

IN IT
ACLO
DC La

Processor
Power

All
All

Initialize and Power Fail Signals
Initialize
ACLow
DC Low

BUS REPEATER A LINE (M7212) SIGNALS INTERFACED
Address

A (17:00)

Master

All

BUS REPEATER D LINE (M78S) SIGNALS INTERFACED
Data

D(15:00)

Master
Slave

Slave (DATa)
Master (DATI)
(continued on next page)

3-1

Table 3-1 (Cont)
I Tnibus Si2;nals
Name

Mnemonic

Source

Destination

BUS REPEATER UNIDIRECTIONAL LINES (M783 and M784) SIGNALS INTERFACED
Non-Processor Request

NPR

Any NPR Devices

Processor

Bus Request

BR (7:4)

Any

Processor

Non-Processor Grant

NPG

Processor

Next Master

Bus Grant

BG (7:4)

Processor

Next Master

In addition to interfacing the signals indicated in Table 3-1, the bus repeater logic also generates the left-to-right
and right-to-Ieft enable signals. These signals qualify the direction of bus flow for the DB II D line logic and A
line logic. The directional indication of BBSY on the M7248 Module determines whether the asserted signal bus
flow is left-to-right or right-to-left. Engineering drawing D-BD-DBII-A-05 shows a block diagram, signal-bysignal interface of the DB 11. The processor side of the DB 11 is indicated as the LEFT side.
3.2 BUS REPEATER WGIC
The bus repeater logic consists of the logic on the M7213 and M7248 Modules (see drawings D-CS-M7213-Q-I
and D-CS-M7248-Q-I, respectively). The M7213 and M7248 Modules interface the signals indicated in Table 3-1,
generate the direction enable signals, and provide the left-to-right buffer gating for the unidirectional bus lines.
The signals INHIBIT BUS and INHIBIT INIT for the DB 11 are always held low (ground). These signals are
only used lNhen the bus repeater is incoroorated (2 bus repeaters) in the Bus Switch. For additional information
refer to the UTI I Bus Switch Manual, DEC-II-HDTAA-A-D.
The DB II uses the bidirectional BBSY circuit as the master controlling circuit. The direction of BBSY on the
bus, whether it inputs the DBII as LEFT BUS BBSY or RIGHT BUS BBSY, determines the direction to enable
the A line circuits (A ENABLE LEFT TO RIGHT or A ENABLE RIGHT TO LEFT, respectively). BBSY is used
as the master controlling signal because the master device always asserts the A lines: therefore, BBSY enable!; the
correct enabling signal direction for the DB 11. (Engineering drawing D-CS-M7248-0-1 shows the basic BBSY enabling circuit including the generation of the A line enabling signals.) When a device master to the left of the
DB 11 asserts BBSY, LEFT BUS BBSY asserts low. Because RIGHT BUS BBSY is unasserted (high), LEFT BUS
BBSY generates LEFT BUF BBSY. Because INHIBIT BUS is held low for the DBII, A ENABLE LEFT TO
RIGHT is generated for the direction of flow on the bus A lines. Thus, RIGHT BUF BBSY is low, because
RIGHT BUS BBSY is unasserted.

3-2

LEFT BUF BBSY (high) moves to the right via the top path, thus putting BBSY on the entire bus. This level remains until LEFT BBSY is dropped by the master device. When LEFT BBSY is dropped, LEFT BUF BBSY goes
low to disable A ENABLE LEFT TO RIGHT and RIGHT BUS BBSY. RIGHT BUF BBSY remains unasserted
and, therefore, enables the output gate to RIGHT BUS BBSY to move any LEFT BUS BBSY signal that occurs
from the left bus. The circuit works in reverse for a RIGHT BUS BBSY with A ENABLE RIGHT TO LEFT being generated.
When the A line direction enable signal is generated, the MSYN circuit is enabled in the correct direction, accordthrough a delay to assert RIGHT BUS MSYN and vice versa. This delay causes the MSYN output (right or left)
to be delayed 160 ns after the MSYN input is asserted on the input bus for deskewing purposes. This delay only
occurs on the assertion or low-going transition of the signal.
The direction to enable the D lines (D LINE RIGHT TO LEFT ENABLE or D LINE LEFT TO RIGHT ENABLE)
is determined from BBSY (A line enabling direction), CO 1, and INTR bus signals. For a DATI or DATIP bus operation (COl is 0), the D lines are enabled to the device master; for a DATO or DATOB, the D lines are enabled
away from the bus master; for an INTR, the D lines are enabled to the processor. The D LINE ENABLE RIGHT
TO LEFT signal is generated by anyone of the three following conditions:
a.

A DATIP or DATI bus operation with no INTR and the presence of the A ENABLE LEFT TO
RIGHT signal (bus master on left or input bus) generates the D line enabling signal (right to left).

A DATO or DATOB with no INTR and the presence of A ENABLE RIGHT TO LEFT (bus
master on right or output bus) generate the D line enabling signal (right to left).

An INTR condition always enables the D lines to the processor (right bus to left bus).

Similarly, to enable the D lines left to right, the absence of RIGHT BUS CO I and A ENABLE RIGHT TO LEFT
is required to generate D LINE LEFT TO RIGHT ENABLE. For D line enabling, the enabling conditions are
ORed conditions in the logic (see drawing D-CS-M72 13-0-1 ). To enable the D lines from left to right (D LINE
LEFT TO RIGHT) either of the following conditions must be present:

A DATI or DATIP with no INTR and the presence of A ENABLE RIGHT TO LEFT (bus master
on right bus) generate the D line enabling signal (left to right).

A DATO or DATOB with no INTR and the presence of A ENABLE LEFT TO RIGHT (bus master on left or input bus) generate the D line enabling signal (left to right).

The SSYN circuit is a completely bidirectional circuit. It provides a 75-ns delay above the gate delays to ensure that
SSYN does not arrive at a device before the data. This delay occurs only on the low (asserted) transition of SSYN.
The generation of the D line enabling signals, in turn, enables the parity of the PA and PB bus signals. The
D LINE RIGHT TO LEFT ENABLE (L) signal enables RIGHT BUS PA and RIGHT BUS PB through to the left
bus, and the D LINE LEFT TO RIGHT ENABLE (L) signal enables LEFT BUS PA and LEFT BUS PB through
to the right bus. These lines are treated as Data Lines. The INTR signal is always moved straight through the
DB 11 from right bus to left bus. because the INTR signal always goes to the processor. This circuit also provides
for a 75-ns deskewing delay.

3-3

Both the COO and COl signals are enabled (in the proper direction) through the DBII by the A line enabling signals. For example, the LEFT BUS COl signal is enabled to RIGHT BUS COl by A ENABLE LEFT TO RIGHT.
The COO and COl circuits provide a deskewing delay of 75 ns in either direction (both assertion and negation).
Thus, LEFT BUS INIT is gated to assert RIGHT BUS INIT (unidirectional), because the INIT signal is generated
only by the processor. Conversely, SACK is gated from right to left (RIGHT BUS SACK (L) to LEFT BUS
SACK (L) delayed) because SACK is always asserted by the next bus master to the processor. Finally, the power
fail AC LO is generated right to left from power to all devices. The INHIBIT AC LO signal is always grounded
for DBll use (used only in DTII Bus Switch). The NPG and BG circuits are used in conjunction with the unidirectionallines and are discussed in the following paragraphs.

3.3 UNIDIRECfIONAL LINE LOGIC
The unidirectional line logic (see drawing D-BS-DB ll-A-02) consists of: gating circuits that gate the bus requests
(BRs), bus grants (BGs), and non-processor request (NPR) and non-processor grant (NPG) signals. The four bus
request levels (BR4, BR5, BR6, and BR7) and the non-processor request signal (NPR) are generated from a device to the processor. Thus, they interface through the DB 11 only from right to left (to the processor). The
non-processor grant signal (NPG) and the four bus grant levels (BG4, BG5, BG6, and BG7) are buffered through
the DB 11 (from the processor) to the device that made the request. The grant signals, therefore, are in one direction, left to right in the DB 11. These signals are buffer-gated in the M7213 Module (see drawing
D-CS-M72 13-0-1), with RIGHT BUF NPG generating NPG on the right bus in the M7213. The BG signals are input from the left bus in the M784 Module and output to the right bus in the M783 Module.

3.4 A LINE LOGIC
The A line logic consists of bidirectional gating with an LC network. The LC circuits are linear phase filters that
provide an equal 75-ns deskewing delay to the assertion and negation of the A lines. These deskewing delays are
required to preserve the guaranteed Unibus timing. Figure 3-1 shows a typical A line circuit (see drawing
D-CS-M72 12-0-1 ). One of these circuits is employed by each of the 18 bus address lines (AOO through Al7 and
by CO and Cl). The LEFT signal, when asserted, gates through to the deskewing delay where the A line enable
signal (A ENABLE LEFT TO RIGHT) generated in the M7213 Module gates with the LEFT signal to generate
the RIGHT bus A line signal. In the right-to-Ieft bus direction, the circuit works exactly the same with
A ENABLE RIGHT TO LEFT enabling the signal to the left bus.
3.5 D LINE LOGIC
The D line logic consists of the bidirectional gating circuits of the M785 Transceiver Modules. A typical circuit
for one line is shown in Figure 3-2 (see drawing D-BS-DB 11-A-03). Each of the 16 data lines (DOO through DIS)
is gated into a circuit where the D line enable signals from the M72l3 Module gate the data lines to the output
bus. For example, the D lines asserted at the left bus are enabled by D LINE LEFT TO RIGHT ENABLE, and all
the left bus signals (LEFT BUS DOO - LEFT BUS DIS) are gated through to assert the right bus signals (RIGHT
BUS DOO - RIGHT BUS DIS). When the D lines ;Jre jnputing at the right side of the DB 11, the D LINE RIGHT
TO LEFT ENABLE signal asserts from the M7213 Module; the D line signals are then gated onto the left bus.
Thus, gating through to the D lines by DB 11 depends on the conditions that generate. the D line enabling signals.

3-4

A ENABLE LEFT TO RIGHT (L) ~

I I

y----j
~

8 (L)

A ENABLE RIGHT TO LEFT (L)
11-0653

Figure 3-1

A Line Logic Circuit

o LINE LEFT TO RIGHT ENABLE (Ll~_

+3~

RIGHT BUS 010 (L)
LEFT BUS

010 (L)

o LINE RIGHT TO LEFT ENABLE (L)
,. - :652

Figure 3-2 D Line Logic Circuit

3-5

CHAPTER 4
MAINTENANCE

4.1 INTRODUCfION
Maintenance of the DB 11 consists of its operational verification in system use. Testing must be done with the
DB 11 in a system because the device is non-programmable. The testing procedure consists of the production
tests and the field tests.
4.2 PROCEDURES
For production or acceptance testing, special test equipment is utilized to verify on-line performance. In particular, Bus Testors are used with the general test program (GTP) software to verify that the DB 11 is responding
correctly to all BR (bus requests) and NPR (non-processor requests) level devices. This test configuration is
shown in Figure 4-1.

UN I BUS

"-065'

Figure 4-1 Test Configuration

4-1

Reader's Comments
DBll-A BUS REPEATER MANUAL
EK-DBIIA-TM-002

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