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EK-KUV11-TM-001

June 1978

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Document:	LSI-11 WCS User's Guide
Order Number:	EK-KUV11-TM
Revision:	001
Pages:	314
Original Filename:

OCR Text

LSI-11 WCS
user’s guide

EK-KUV11-TM-001

digital equipment corporation « maynard, massachusetts

1st Edition, June 1978

Copyright © 1978 by Digital Equipment Corporation
The material in this manual is for informational purposes and is
subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL
DEC
PDP
DECUS
UNIBUS

DECsystem-10

DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX

VMS

MASSBUS

OMNIBUS
0S/8
RSTS
RSX
IAS

PREFACE

This manual provides the user with all
the
information
required
to
write, assemble, debug and execute microprograms on the LSI-11 utilizing the Writable Control Store (WCS) option (KUV11-AA) in
conjunction
with microprogramming support software.

Chapter'l provides an introduction to microprogramming the LSI-11.
discusses
tory

machine-micromachine

glossary

important

Chapter 2 is divided into
LSI-11 machine operation.

relationships

and

definitions.

supplies

introduc-

two parts:
The first

LSI-11 machine architecture
and
part is an LSI-11 family hardware
overview and is included for completeness.
The new
LSI-11
user
can
gain a basic system understanding from this overview, but should refer
to the Microcomputer Handbook for a more
complete
description.
The
second part is recommended reading for all LSI-11 microprogrammers be-

cause it introduces control flow diagrams which explain
control between the LSI-11 machine and micromachine.

the

transfer

Chapter

3 follows the same organization as Chapter 2, but concentrates
on
the
LSI-1ll
micromachine.
The first part covers the LSI-11 micro
processor as implemented in the Control and
Data
chips
and
details
their
internal
organization.
The second part describes the micromachine operation and its relationship to higher
1level
machine
opera-

tion.

Chapter 4 presents
functional basis.

the LSI-11 microinstruction
set,
organized
on
a
The chapter also contains a detailed explanation of
each microinstruction along with an example containing
assembly
mnemonics and assembled octal equivalents.

Chapter 5 concentrates on the Data Access group
of
microinstructions
and
provides details sufficient to accurately determine the execution

times

for

Chapter

microprogrammed
presents

the

I/0

LSI-11

transactions.

Writable

Control

Store

hardware

and

its

relationship
to
the
LSI-11 micromachine.
The discussion includes
description of the data buffer and control/status registers.
Chapter

(1)
(3)

details

the

microprogramming

support

software

the microassembler (MICRO),
(2) the WCS loader
the WC3 Microprogram Octal Debug Tool (MODT).

Chapter

discusses

techniques

which

may

used

consisting

dumper

(WCSLOD)

write

and

micropro-

grams.

Chapter 9 contains information on
checkout.

Chapter

contains

information

the

on WCS

WCS

module

maintenance.

installation

and

TABLE

Chapter

INTRODUCTION

LSI-11,

CONTENTS

PDP-11/03

USER MICROPROGRAMMING

GENERAL
Introductory

LSI-11

Basic

THE

Microprogramming

LSI-11

BENEFITS

Arithmetic

Features

Machine-Micromachine

USER

Structure

MICROPROGRAMMING

Calculations

Critically-Timed
Data

Glossary

Input/Output

Manipulation

and

Control

Operations

Relocation

SYSTEM IMPLICATIONS OF USER MICROPROGRAMMING

1-8

Control

1-8

Flow

Interrupt

Integrity

Response

Content

Processor

Status

Dedicated

Control

Machine

Latency

1-8

Security

1-9

Word

1-9

Updating

Store

Instruction

Locations

Support

1-9
1-10

MICROPROGRAM

CHARACTERISTICS

1-10

Vertical

Horizontal

1-10

Logic

THE

Control

the

Microinstructions

Features

MICROPROGRAMMING

Creating
The

and

Source

1-10

ENVIRONMENT

File

1-11

Microassembler

Writable

Control

Micro Octal

REFERENCES

1-11

Store

Loader

Debugging Tool

Microprogram Trace

1-11

Facility

(MODT)

1-11
1-11

1-12

Chapter 2 THE LSI-11 MACHINE STRUCTURE
GENERAL

MACHINE ARCHITECTURE
System

Bus

2.2.1.1

System Bus Address Space

2.2.1.2

System Bus Data Transfer

2.2.1.3

" System Bus Control Signals

2.2.2

Memory

2.2.2.1

Semiconductor

2.2.2.2

Dynamic Memory Refreshing

2.2.2.3

Magnetic

2.2.3

Input/Output Devices

2.2.3.1

Device Address

2.2.3.2

Enabling

2.2.3.3

DMA Transfer Restrictions

2.2.4

The

2.2.4.1

Arithmetic

2.2.4.2

General

2.2.4.3

Processor

2.2.5

The LSI-11 Writable Control Store

2.2.5.1

LSI-11 System Bus Connection

2.2.5.2

Microinstruction Bus Connection

Memory

Format

Device

LSI-11

Interrupts

Processor

Logic

Unit

Purpose Registers

MACHINE

Control

OPERATION

2.3.1

Basic Machine Cycle

2.3.1.1

Bus

2.3.1.2

External

2.3.1.3

Combined Trap and Interrupt Cycle

Error

Trap

Interrupt

Complete

Machine-Level

Run/Halt

Portion

Trap/Interrupt
Complete

Operating

Portion

Machine-Micromachine

Operating

2.3.3.1

Bus Error Processihg

2.3.3.2

Trap/Interrupt

2.3.3.3

Power-Up

Chapter

TfiE LSI-11 MICROMACHINE STRUCTURE

3.1

GENERAL

3.2

THE

3.3

MICROPROCESSOR

PARTITIONING

3.3.1

Microprocessor

Data

3.3.1.1

Microinstruction

3.3.1.2

3.3.1.3

Arithmetic

3.3.1.4

Status

3.3.2

Microprocessor

3.3.2.1

Microinstruction

3.3.2.2

Microinstruction Address

3.3.2.3

Control

3.4

MICROMACHINE

- 3.4.1

Cycle

Processing

MICROPROCESSOR

File

Bits

and

Logic
and

Chip

Indirect

Addressing

Unit
Condition

Control

Code

Flags

Chip

Generation

Signals

OPERATION

Microinstruction

Bus

Data

Transfer

3.4.1.1

Control

Store

3.4.1.2

Control

Chip Microinstruction

3.4.1.3

Data

3.4.1.4

Complete

(MICROM)

Microinstruction

Chip Microinstruction
Micromachine

Cycle

Bus

Cycle

Bus

Cycle

MICROPROGRAMMING THE BASIC LSI-11 MACHINE CYCLE
Fetch-Execute Machine Cycle Microprogramming

Fetch-Execute-Trap & Interrupt Machine Cycle
Microprogramming

Chapter

4.1

THE LSI-11 MICROINSTRUCTION SET

GENERAL

VERTICAL MICROINSTRUCTIONS

Jump Microinstruction Format

Conditional Jump Microinstruction Format
Literal Microinstruction Format
4.2.4

4.2.4.1

Byte

4,.2.4.2

Word Operand

and Word Microinstructions
Formation

MICROINSTRUCTION SET FUNCTIONAL ORGANIZATION

4.3.1

Data Manipulation Microinstructions

4.3.1.1

Move Microinstructions

4,3.1.2

Increment/Decrement Microinstructions

4.3.1.3

Logical Microinstructions

4.3.1.4

Shift Microinstructions

4.3.1.5

Arithmetic

4.3.2

Data Access Microinstructions

4.3.2.1

Read Microinstructions

4.3.2.2

Input Microinstructions

4.3.2.3

Write Microinstructions

4,3.2.4

Output Microinstructions

4.3.3

Microprogram Control Microinstructions

Microinstructions

4.3.3.1

Jump and

4.3.3.2

Compare

4.3.3.3

Miscellaneous

Chapter

5.1

Return Microinstructions

and

Test

Microinstructions

Control

MICROPROGRAMMING

Microinstructions

LSI-11

SYSTEM

BUS

TRANSACTIONS

GENERAL

LSI-11

SYSTEM

BUS

WSYNC

WWB

BWTBT

BDIN

WDIN

BSYNC

BDOUT

BRPLY

BUSY

BIACK

THE

LOGIC

OVERVIEW

WDOUT

WIAK

INTERFACE

DATA~INPUT

(DATI)

OPERATION

DATI

Operation,

Minimum

Execution

Time

DATI

Operation,

Delayed

Execution

Time

DATI

Microprogramming

Summary

THE

DATA-OUTPUT

(DATO)

5.4.1

DATO

Operation,

Minimum

Execution

Time

5.4.2

DATO

Operation,

Delayed

Execution

Time

5.4.3

DATO

Microprogramming

Summary

THE

DATA-INPUT-OUTPUT

(DATIO)

DATIO

Operation,

DATIO

Microprogramming

OPERATION

Minimum

OPERATION

Execution

Summary

Time

THE

INTERRUPT OPERATION

Interrupt Operation Microprogramming Summary

Chapter

6.1

6 THE

LSI-11 WRITABLE CONTROL STORE

GENERAL

. THE WRITABLE CONTROL STORE MEMORY

Control Store Microword Organization

Standard 22-Bit Microword MI<21:0>
Extended TTL Control Bits MI<23:22>
Control Store Microaddressing Modes
WRITABLE CONTROL STORE MEMORY ACCESS

6.3.1

Microinstruction Bus Access

6.3.1.1

Control Store Access Timing

6.3.1.2

Extended TTL Control Bit Timing

6.3.2

LSI-11

6.4

THE MICROADDRESS TRACE

6.4.1

Microaddress Trace RAM Operation

6.4.2

WCS Enable Bit

LSI-11

System Bus Access

SYSTEM BUS

RAM

INTERFACE

WCS Control/Status Register
WCS Memory Access Registers

Microaddress Trace Register

Microaddress Trace RAM Dump Algorithm
WRITABLE CONTROL STORE MODULE CIRCUIT DESCRIPTION

Clock

Generation

Control

Store

LSI-11

System

Memory
Bus

and

WRITABLE

Trace

CONTROL

Multiplexer

Interface

Microinstruction Bus
Microaddress

Microaddress

Interface

RAM

STORE

HARDWARE

SPECIFICATIONS

Dimensions
Power

Requirements

L5I-11

System

Bus

Microinstruction
TTL

Chapter

7.1

Control

LSI-11

Bit

Backplane

Bus

Connector

Assignments

Summary

MICROPROCESSOR

ASSEMBLER

GENERAL

MICROASSEMBLER

(MICRO)

7.2.1

Statement

7.2,.2

Expressions

7.2.2.1

Numeric

7.2.2,2

Symbols

7.2.2.3

Current

7.2.2.4

Arithmetic

7.2.3

Microinstructions

7.2.3.1

Jump

7.2.3.2

Conditional

7.2.3.3

Literal

7.2.3.4

Two

7.2.3.5

Single

Format

Constants

Location

Counter

Logical

Operators

Instruction

Jump Microinstructions

Microinstructions

Assignment

7.2.3.6

Reset and Set Flags Microinstructions

7.2.3.7

Input Microinstructions

7.2.3.8

No-Operation Microinstruction

7.2.3.9

Load Condition Flags Microinstructions

7.2.3.10

Return From Subroutine Microinstruction (RFS)

7.2.3.11

Reset TSR Microinstruction

7.2.4

Microassembler Directives

7.2.4.1

NXT Directive

7.2.4.2

TITLE Directive

7.2.4.3

SBTTL Directive

7.2.4.4

REG Directive

7.2.4.5

LOC Directive

7.2.4.6

END Directive

7.2.4.7

Equated

7.2.4.8

PAGE Directive

7.2.4.9

MODE Directive

7.2.5

Using the MICRO Assembler

7.2.5.1

Bitmap of Used Memory Locations

7.2.6

Errors

7.2.7

WCS Module Addressing Mode Support

7.3

LOADING AND SAVING WRITABLE CONTROL STORE

7.3.1

Loading Object Modules

7.3.2

Saving the Contents of WCS

(NOP)

(LCF)

(RTSR)

Symbols

MICRO ODT

the

Source

Program

(WCSLOD)

(MODT)

Symbolic Examination and Modifications of WCS Locations
Executing

a Microprogram

Dump Points
Tracing

Microprograms

Transferring

WCSLOD

Using MODT

SAVE

Using MODT with

Chapter

8.1

File

a MACRO-11

MICROPROGRAMMING

Object

Program

TECHNIQUES

GENERAL
USER

MICROPROGRAMMING

ENTRY

Entry

Microaddress

3000

Entry

Microaddress

3001

Entry

Microaddress

3002

Entry Microaddress

3003

Entry Microaddress

Summary

MACHINE

INSTRUCTION

Successive

Modified

DECODING

Comparison

Jump

POINTS

TECHNIQUES

Decoding

PASSING OPERANDS TO USER MACHiNE INSTRUCTIONS
Predefined
Register

Operand

MICROPROGRAMMING

Defining

The

Documenting

Addressing

THE

USER

INSTRUCTION

Instruction
the

Instruction

Temporary

Flag

8.5.4

Executing

Machine-Level

8.5.4.1

Bus

Trap

8.5.5

Scratch

Error

MACHINE

Use

I/0

Control

Usage

Operations

(RSRC)

8.5.5.1

Source Operand Register

8.5.5.2

Destination Operand Register

8.5.5.3

Instruction Register

(RIR)

8.5.5.4

Bus Address Register

(RBA)

8.5.5.5

LSI-11 Processor Registers

8.5.5.6

LSI-11 Stack Pointer

8.5.5.7

Procesor Status Word Register

8.5.6

Interrupt Considerations

8.5.6.1

Testing For

8.5.6.2

Aborting a Microprogram

8.6.6.3

Suspending and Resuming a Microprogram

8.6

PROCESSOR STATUS WORD MANIPULATIONS

8.6.1

Moving the PSW to a Processor Register

8.6.2

Moving 8-Bits to the PSW

Pending

(RDST)

(RO-R5)

(R6) and Program Counter

(R7)

(RPSW)

Interrupts

MICROPROGRAMMING USER~-DEFINED TRAP VECTORS
8.7.1

Creating the Vector Addresses

8.7.2

Joining the Base Microcode

MICROPROGRAMMING SYNCHRONIZED CONTROL SIGNALS
Standard TTL Control Bits
Extended TTL Control Bits

CONTROLLING THE MICROINSTRUCTION FLOW
Leaving User

Control Store

Jump To Subroutine and Return Microinstructions

Conditional Jump Microinstructions

‘Chapter 9 INSTALLATION
9.1

GENERAL

UNPACKING AND

INSTALLATION

9.3.1
9.3.2

PROCEDURE

Switch Configurations

" Cable Configuration

9.3.3

WCS

Installation

PERFORMANCE

Chapter

INSPECTION

CHECKOUT

10-1

10 MAINTENANCE

10.1

GENERAL

10.2

PREVENTIVE

MAINTENANCE

10.3

CORRECTIVE

MAINTENANCE

CORRECTIVE

MAINTENANCE

APPENDIX

10-1

INSTRUCTION

10-1

PHILOSOPHY

10-1

SUMMARY

CHAPTER
~INTRODUCTION

1.1

GENERAL

This

chapter provides
an
microprogramming,

four

and

LSI

cuments

l1.1.1

techniques

(Large

Scale

referenced

Introductory

used

implement

Integration)

USER MICROPROGRAMMING

introduction
to
LSI-11
the
user has access to

Through

sources

LSI-11

this

the

chips.

microprogramming.
all the re-

nearly

LSI-11

Section

architecture

1.6

lists

other

in
do-

manual.

Microprogramming

Glossary

This section contains a glossary of selected terms
which
provide
an
introduction
to the the terminology used to describe LSI-1l1l microprogramming concepts.

Microprocessor

The
set

microprocessor
of

called

large

the

Data

implemented

scale

integrated

and

Control

two-chip

(LSI)

circuits

chips.

The

chip

the ReLSI-11

system

Control

bus

data/address

lines

(DAL).

chip provides the system bus
control
contains the translation array.
Micromachine

Data

contains the Arithmetic Logic Unit (ALU),
gister File and
interconnection
to
the

The

micromachine

cessor,

two

consists
three

The

1lines

and

two-chip micropro-

MICROMs

(Control

Store

chips),
and
the
LSI-11
system
bus
interface
logic.
The first two MICROMS contain the PDP-11
emulation microprogram as well as the console ODT
microprogram.
The optional KEV1l MICROM contains
microprograms which

ating point machine
Machine

Machine

execute

the extended
instructions.

and

flo-

The LSI-11l machine encompasses the LSI-11
Micromachine,
main or program memory and input/output
devices.
Cycle

Machine cycle refers
to
the
smallest
complete
cycle
of
operations performed by the LSI-11l machine.
The three fundamental operations
of
the

INTRODUCTION TO

LSI-11

USER MICROPROGRAMMING

machine
cycle are (1) Fetch machine instruction,
(2) Execute machine instruction (3) Trap and
interrupt service.
The number and type of micromachine operations which must be performed during a
given machine cycle are a function of the fetched
machine instruction and whether a machine
interrupt
or
system fault is present.
Consequently,
the time required to complete the
machine
cycle
is variable.
Microcycle
(Micromachine

Microcycle

Cycle)

refers

the

smallest

complete

cycle

of operation performed
by
the
LSI-11
micromachine.
A
machine
cycle
1is composed of one or
more microcycles.
A microcycle consists of
four
equal phases (PH1-PH4).

Machine Instruction
(Machine Code)

A machine

instruction is a 1l6-bit word stored in
main memory.
Machine instructions
are
commonly
referred to as instructions.

Microinstruction
(Microcode)

A microinstruction

Microassembler

The microassembler is a microprogram
development
tool
which
accepts
as input a source file containing micromachine assembly language statements
with
optional comments.
The microassembler output is an object file which may
be
1loaded
1into
the Writable Control Store.

Fetch

Fetch is the operation of presenting
an
address
to memory and subsequently moving the contents of
the addressed location to the instruction
register contained in the processor.

Execute

The action of performing all
by a machine instruction.

Interrupt

The

Control

22-bit word

stored

Store.

action

diverting

operations

control

from

required

the

normal

(uninterrupted)
machine operating cycle of repeated Fetch-Execute events.
The simplest complete
operating
cycle
is
expressed
as
Fetch-Execute-Interrupt.

Program

Counter

The Program Counter (PC) stores
address
of
the
next
machine

the
main
memory
instruction to be

feched during a machine cycle.
It
1is
automatically
incremented
by
2 as the last part of the
Fetch Machine Instruction phase.
Microprogram

The

Counter

the address of the
fetched
during

Microprogram

Counter

may

pending

upon

Location Counter

loaded

the

(LC)

stores

next
microinstruction
to
be
a
microcycle.
The
Location
from various

type

sources,

microinstruction

de-

being

executed.
Program

oth program and data

Store

in-

Program Store

refers

the

LSI-11

machine

main}

INTRODUCTION TO LSI-11 USER MICROPROGRAMMING

formation.

Program store

referred

core,

LSI-11

Control

Store

1is

accessed

as Main Store,

Memory or

system bus.

Program

store

may

via

the

alternately

sometimes

Control store refers to the storage area for
microcode
and consists, potentially, of 2048 locations.
Control store for the LSI-11
machine
1is
provided
by
two or more MICROMs and the WCS module.

Writable Control
Store

Writable Control Store (WCS) refers to a control
store
which
may
be
altered
by
the
user.
Alterable or writable control store is implemented by read/write random access memory (RAM)
dev-

ices

which

System Bus
Data

Chip

<can

and

accessed by both the LSI-11

the microinstruction bus.

All Data processing occurs within the Data
chip.
It
contains
the ALU and the internal registers.
It also provides bi-directional connection to the
LSI-11 system bus data/address lines (DAL).

Control Chip

The

MICROM Chip

A MICROM (MICrocode Read Only Memory) chip is the
unalterable, non-volatile read only control store
memory.
One or more MICROMs are connected to the
Data
and
Control chips via the microinstruction
bus

System

Bus

Control

chip

functions

controller/sequencer.
It
provides
all control
signals for the system bus
and
also
determines
An impormicroinstructions are executed.
which
tant feature of the ConTrol chip is the
translaThis is a large combinatorial logic
Array.
tion
as
network which accepts the machine instruction
input
and outputs the addresses of the microprogrammed routine appropriate to that instruction.

(MIB).

The LSI-11 system bus

the common,

bidirection-

passes address, data and control
path which
al
all
and
machine
information between the LSI-11
modules which make up a given machine conother
figuration.

Microinstruction
Bus

The Microinstruction Bus
(MIB) is the common biall
between
path
control
directional data and
It is through conelements of the micromachine.

nection to this bus that the WCS module makes

its

control store accessible to the microprocessor.
Instruction
Register

Microinstruction
Register

When an LSI-11 machine

from main memory,

instruction 1is

fetched

it is placed in the Instruction

microinstruction which has been

in the

fetched from

either MICROM or user control store is placed
This register
microinstruction register.
the

1in
is

INTRODUCTION TO

LSI-11

USER MICROPROGRAMMING

implemented on both the Data and
Control
chips.
The
microinstruction
register on each chip contains only the portion
of
the
microinstruction
relevant to the chip's function.
Translation
Register

The Translation Register and the instruction
register (RIR) are loaded simultaneously during a
machine
instruction
fetch.
The translation register holds the machine instruction for input to
the translation array.

Translation Array

The Translation Array is located in the microprocessor
Control chip and receives as input either
the upper or lower byte of the Translation Register,
the
microprogram
Location Counter and the
interrupt register contents.
It
consists
of
a
large
combinatorial
logic
network which determines the starting location
for
microcode
routines
appropriate
to
fetched
machine instructions.

Return

The

Return

(RR)

located

the

micro-

processor Control chip and provides storage for
single microprogram subroutine return address.
Register

1.1.2

File

LSI-11

The register file is located in the Data chip and
contains 26 8-bit registers which are accessed by
a combination of direct and indirect
addressing.
Adjacent
8-bit registers may be sequentially addressed to form word operands.

Microprogramming

LSI-11
Store

Features

microprogramming is provided
module
1in
conjunction
with

by
a
Writable
microprogramming

Control
support

allows one half (1024)
of
the
total
locations to be user microprogrammed.

(2048)

software.
The

WCS
control

module

store

The

microprogramming support software includes a
microassembler,
writable
control store loader and dumper, and a Micro
Octal Debugging Tool which allows simultaneous
debugging
at

the

machine

and micromachine

levels.

The

microprogramming support software also includes the micro
code
for the EIS/FIS machine instructions.
The user may include this microcode in the final writable control store load
module, thus combining the existing advantages of the familiar extended and floating point machine instructions with user
designed instructions.
LSI-11 microprogramming combines the simplicity
of
vertical
microinstructions with the individual bit-control of horizontal microinstructions.
The existing bit-control
field
supported by the micromachine is expanded by two additional bits

INTRODUCTION

with the
facility
cycle,

1.1.3

LSI-11

USER

MICROPROGRAMMING

addition of the WCS module.
This
1is
also
timed
with
respect
to

new
bit-control
the micromachine

thus

control
bus I/0

enabling higher control rates and
more
accurate
timing than can be achieved with normal LSI-11 system
control.

The WCS module is equipped with a 16-word
recirculating
microlocation
Trace
RAM which aids in microprogram debugging.
It contains the last 16 microlocations placed on the microinstruction
bus.
This hardware feature is utilized by MODT to
display the
last
16
microlocations
accessed
prior
to
a
user-specified dump point.
.

Basic

LSI-11

Machine-Micromachine

Structure

Figure 1-1 contains a simplified illustration of the
LSI-11
machine.
The
LSI-11
machine
encompasses the processor, main store or memory,
and the input/output devices.
These three main components are
interconnected
by the LSI-1ll system bus.
The LSI-1l processor is realized
by a micromachine which contains a (micro)processor element, a storage
element
(control
store), and external I/O capability.
The microprocessor is implemented with two chips (called the
Data
chip
and
the
Control
chip).
The
Data
chip
contains
the Arithmetic Logic Unit
(ALU)
,

the

tiplexed
system

bus

sequence.
in detail
The
or

The

which

are

for

the

The

Control

the

microinstruction

the microprocessor

stored

provide

acronym

connection

(DAL).

determines

structure of
3.

MICROMs

provides

control

non-alterable,

MICrocode

chip

chip set

store
Only

mul-

all

execution

is presented

consisting

non-volatile

Read

time

arbitrates

two

memory.

The

Memory.

the

LSI-11
processor,
the MICROM control store contains microcode
performs 2 functions:
(1) PDP-11 emulation and (2) console ODT.
included
on the processor, The KEV1l EIS/FIS option expands the

control

store

structions.

implement

The

Writable Control
cable/plug
assembly

tion

and

in Chapter

term MICROM

CROM

and

1lines

transactions

microinstructions
more

basic
which
When

the

file,

data/address

socket).

This

the

Store

and

(which
gives

extended

connected
replaces the

the

WCS

floating

point

machine

in-

to
the
micromachine
via
a
KEV1l option in the third MI-

module

access

the

microinstruc-

bus
which is the internal bus interconnecting all components of
micromachine.
The WCS then may be accessed by the
microprocessor

in
the
same
fashion as a MICROM.
The total number of control store
locations addressable by the microprocessor is 2048.
The PDP-11
emulation
and
console ODT microcode require only 1024 locations, or two

MICROMs.

cations.

The

bus interface,
registers.

WCS

module

WCS
which

supplies
the

memory

consists

loaded
of

remaining

and

normal

dumped

1024

via

control

its

control/status

store

LSI-11

and

data

lo-

system
buffer

INTRODUCTION TO LSI-11 USER MICROPROGRAMMING

LSI-11 Machine-Micromachine Structure
Figure

1-1

Fisi-11 MACHINE
LSI-11

MEMORY

PROCESSOR

¢
——

INPUT/OUTPUT

DEVICES

LSI-11

SYSTEM BUS

——d]
MR-1014

INTRODUCTION

LSI-11

USER MICROPROGRAMMING

1.2

THE

User
The

microprogramming affords greater control over
user
can
create new machine instructions to

manner

BENEFITS

members

The

USER MICROPROGRAMMING

the

LSI-11,

PDP-11/03

following paragraphs identify
programming may be beneficial.

1.2,1

Arithmetic

specific

machine
be used

machine

areas

operations.
in the same
instruction
set.

in which

user

micro-

Calculations

Many arithmetic calculations are characterized
by a
concisely-defined
‘algorithm
which
is often repetitive in nature.
The execution of the
routine for such an algorithm normally requires
many machine
1instruc-

tion
fetches
and
operand address calculations.
1If the algorithm is
suitable for microprogramming it can be implemented
in microcode which
is
then
executed
in
response to a single, user-defined machine in-

struction.
fetch

This approach
operations because

eliminates

the multiple machine
1instruction
remains entirely within the micromacompletly executed.
A good example of
the

control

chine until the routine is
improvement
available
in this area is the KEV11l EIS/FIS option.
The
EIS/FIS option contains microcoded routines for the
extended and
floating
point machine instructions.
Upon execution of a single machine
instruction, FDIV for example, control is transfered
to the
appropriate
starting point in the FIS microcode.
When the routine has termi-

nated,

control

returned

the

in
the
2
standard
microms.
EIS/FIS microcode ranges from a
able

PDP-11

executed

1.2.2

and

macroinstruction
the

operand

Critically-Timed

LSI-11

The
3 to

emulation

routines,

depending

upon

values.

Input/Output

microcode

contained

speed
advantage realized by the
10 times improvement over compar-

and

Control

the

instruction

Operations

The

rate at which real-time input/output (I/O) operations can
be
performed depends on three factors:
(1) the speed of machine instruction
execution,
(2) the time delays associated with the LSI-11
system
bus
and
(3) the speed of the device or memory being accessed.
The microprogramming facility allows the user to write specializ
ed I/0 routines
for
execution
in
microcode.
In this context, the user employs the

"data access" group of microinstructions which are discussed
generally
in
Chapter 4 with detailed explanations in Chapter 5.
Sufficient in-

formation
ys

occur

delay

provided
non

I/0

time.

allow

identification

microinstructions

can

where

these

inserted

bus

dela-

utilize

the

User-written microcode can make use of a special field of 4
TTL
control
bits within the microinstruction.
Of the 16 possible states encoded in this field, 8 are presently used to control the LSI-11 system
bus logic which interfaces between the system bus and the microproce
ssor chip set.
The other 8 states are available for user-defined func-

tions.

The

LSI-11

module

(PH3

H).

bits

from

this

microinstruction

fingers as does the third
These TTL control bits enable

high rate control
chine cycle.

signals which

are

phase
the

field

appear

the

the microcycle
clock
microprogrammer to produce

timed with

respect

the

microma-

INTRODUCTION TO LSI-11 USER MICROPROGRAMMING

In addition to the 4 control bits (MI<21:18>), the WCS module stores 2
extra bits (MI<23:22>) in each control store location. These two bits
are available as signals directly on the LSI-1ll system backplane - and
may be used for any user-defined purpose. The high-order bit (MI<K23>)
is also used to control the microlocation trace buffer.
Data Manipulation and Relocation

1.2.3

A block move microprogram example is discussed in Chapter 8 in which
the arquments required are (1) the starting address of the block to be
moved, (2) the starting address of the new block location, and (3) the
The execution time saved is proportional to the block
block 1length.
length, because machine instruction fetches are eliminated for each
word moved.

1.3

SYSTEM IMPLICATIONS OF USER MICROPROGRAMMING

With the microprogramming facility, all the resources used to emulate
the LSI-11 architecture and operation are at the user's disposal. The

only resource that cannot be accessed is the Control chip translation
array which is specifically configured to implement the opcodes of the
standard and extended machine instruction set. However, the microprocessor instruction set does provide a means for accomplishing translations in only a few additional microcycles.

1.3.1

Control Flow Integrity

The first responsibility of the microprogrammer is to maintain the integrity of the control flow which implements the machine operating
cycle. Control is transferred to user microcode when the microprocessor control «chip, via the translation array, determines that a the

fetched instruction is a user-defined machine opcode. User microcode
then maintains control until the microroutine has executed, whereupon
control must be returned to the trap interrupt service routine, thus

maintaining the normal Fetch-Execute-Interrupt machine cycle.

An additional requirement arises when the user-microprogrammed routine
performs I/0 operations. 1In executing an I/0 transfer the LSI-11 sys-

tem bus transaction requires that the addressed I/0 device return a
reply signal to the processor, acknowledging its role in the transfer.
If no reply is received by the CPU within 10 microseconds, the processor executes a bus error trap through LSI-11 memory location 4.
the microproBecause a bus error can occur in a number of contexts,

grammer
flag

1.3.2

must

prepare

for the proper response by setting an internal

(see Section 8.6.4.1).

Interrupt Response Latency

Interrupts are recognized by the LSI-11 processor only during the
cycle
operating
machine
normal
the
of
phase
final
inpending
a
g
acknowledgin
in
delay
The
e-Interrupt).
(Fetch-Execut

INTRODUCTION

terrupt
is
phase.
The
external

LSI-11

USER MICROPROGRAMMING

directly
related
microprogrammer is

to
the
length of time of the Execute
provided with a means
of
testing
for
interrupts
and
the
Event
Line
interrupt
during
user-microprogram execution.
If such an interrupt is pending,
control
can
be
transferred
to a user microcode routine.
This routine could
save the interrupted machine state,
decrement the PC and
then
return
control to the last part of the machin
e cycle.

Once

the normal LSI-11
interrupt
user-defined
machine instruction

program

can

then

execute

service
is

fetched

completion.

has
been
again and

The

completed,
the
the user micro-

external

interrupt

test
facility
allows potentially lengthy microcoded
routines to operate in
a time critical environment.
Interrupt testing
is
unnecessary
when
the
microcode to be executed is of known
short duration.
See Section
8.6.7.

1.3.3

Content

The microprogrammer has
well as to the internal

internal

and

registers

should

only

Manipulation
occur

part

access to
registers

have predefined
be

the

Security

uses

modified

standard

the

the LSI-11
processor
in the micromachine.

processor

intended

(e.g.,

function

PSW,

accordance

registers
of

the

registers
Several of

bus

error

with

(R0O-R7)

user-defined

as
the

flags)

those

wuses.

should

only

machine

in-

processor status word (PSW)
in
the
LSI-11
is
a
composite
the
4 PDP-11 Status Flags
(N,Z,V,C) and (2) the Trace Bit
and
the Interrupt Enable bit.
Internally, the PDP-11 Status Flags
are
Plicitly accessed by 2 microinstruc
tions (LCF, CCF) and implicitly

(3)

struction.

1.3.4

Processor

Status Word

Updating

The
(1)

tered

(e.g.,

executing

AWF).

executing

processor

The

Set

microinstruction

Trace Bit
Interrupt (SI)

control

flags

1I4

and
or

Reset

and

cannot be read, a copy of these flags
(RPSWH)

<4>)

the

and

1.3.5
The

the
bit
Interrupt

Dedicated

1024

replaces the
The
LSI-11
array,

Control

2000

EIS/FIS

Store

affecting

these

flags

respectively.

Since

these

flags

is kept in an internal

Store

through

partial

(bit

Locations
locations

3777

MICROM which
emulation
microcode,

performs

exal-

Enable Bit are altered by
Interrupt (RI) for the
micro-

positions that correspond to the
Trace bit
Enable bit (bit <7>) of the LSI-1
1 PSW.

Control

Writable

microaddresses

capable

Interrupt

decode

are

(octal).
responds

normally

The WCS

configured

module

to
addresses
conjunction with the

the

extended

and

therefore

2000-2777.
translation

floating

point

machine
instructions and transfers control
to control store locations
in the 2000-2777 range.
The microprogrammer has the respo
nsibility of
handling such a transfer as a reserv
ed instruction trap.

INTRODUCTION TO LSI-11 USER MICROPROGRAMMING

Machine Instruction Support

1.3.6

A newly defined machine instruction must be explicitly

documented

It
to function, execution characteristics, and operand requirements.
a
by
ed
support
is
which
c
mnemoni
y
assembl
an
should also be assigned
and assemmacro definition to enable the instruction to be programmed8.2).
bled along with the standard instruction set (See Section
1.4

MICROPROGRAM CHARACTERISTICS

Vertical and Horizontal Microinstructions

1.4.1

hine
The user will discover that microprogramming the LSI-11 micromac
requires techniques nearly identical to those used in LSI-11 assembly
milanguage programming. This strong similarity arises because the One
cromachine executes vertical as opposed to horizontal microcode. ons
characteristic of vertical microinstructions is that microinstructi
are executed out of sequential locations in control store, just as machine instruction are executed sequentially out of main or program
store.

Another characteristic shared between vertical microinstructions and
machine instructions is that both perform recognized complete opera-=
tions upon execution. For example, the COMPLEMENT BYTE microinstruction reads the contents of the specified source operand register into
the ALU, forms the complement and places the result in the specified
A horizontal microinstruction, by contrast,
destination register.
would affect (micro) processor control at a much more detailed level,
often with direct control of register read and write circuitry, data
, the
path bus drivers, ALU operating modes, and so forth. In addition
horizontal microcode usually contains a field which holds the address
of the next microinstruction to be executed.

1.4.2

Logic Control Features

The LSI-11 microprogramming option offers a repetoire of 149 nmicroinstructions which support both byte (8-bit) and word (16-bit) opera-

tions. Further, the basic 16-bit vertical microinstruction word is
extended by 6 control bits within the micromachine and by an additional 2 control bits in the WCS module. The 6-bit extension contains 4
bits which may be encoded for direct control of user logic. The
2-bits supplied by the WCS module enhance this logic control capabili-

‘ty.

See Section 6.7.5.

INTRODUCTION

1.5

LSI-11

USER MICROPROGRAMMING

THE MICROPROGRAMMING ENVIRONMENT

1.5.1

Creating

The RT-11
grammer

the

Source

File

Operating

System

environment

works

programmer.

familiar

fundamental

the

in which

experienced

reference

the

LSI-11

PDP-11

micropro-

assembly

microinstruction

des-

this

manu-

text

edi-

cription, which is contained in Chapter 4 and
Appendix A of
al.
Chapter 7 describes the WCS Software Tools
available.
‘The

source

tor,

tion

1.5.2
The
of

file

for

TECO.

EDIT

.MIC

microprogram

The

signifiying

recommended

created

with

extension

source

file.

a microprogram

either

the

file

specifica-

The Microassembler

Microassembler
a

the

language
set

stand

alone

described

pass

in detail
assembler for the

Chapter

LSI-11

7.
It
consists
microinstruction mne-

monics with several assembler directives availabl
e.
The listing shows
the
assembled
octal
for each microlocation and includes a bitmap of
the utilized microaddresses.
The microassembler output
(.0OBJ
extension) is then loaded into the WCS module as described
in the next section.

1.5.3

Writable

Control

Store

Loader

The microprogramming support software provides
a
WCS
1loader
program
which can initially clear the WCS RAM memory and
then load from one to
six specified .OBJ files produced by the Microas
sembler.
The WCS
1loader is described in Chapter 7.

1.5.4

Micro Octal

Debugging

Microprogram debugging
Tool

that

program

(MODT).

user-written

ed.

Since

all

MODT

programs.

Breakpoints

level,
of

all

are

allow

done

This

microprograms

allows

the
may

(MODT)

using

program

microprograms

structions,
examine

Tool

can
are

user

set

the Microprogram Octal

expands

the

familiar

analyzed,

registers

the

dump

points

and

write,

modify

and

machine

instruction

selected
can

ODT so
executmachine in-

examined, modified,
executed in response to
the

execute

program progress at the machine level.
At
the
the user may establish "dump points" which display
internal

Debugging

PDP-11

point.
moved

and

Once

the

short
flow

micromachine

the

contents

dump

results

subsequent

executions

the user to examine
additional
portions
of
microcode.
This
dump-examine
process
continues
until the microprogram is completely
debugged and verified.
MODT is described in detail in Chapter 7.

INTRODUCTION TO LSI-11 USER MICROPROGRAMMING

Microprogram Trace Facility

1.5.5

The microaddress trace hardware on the WCS module is
trolled and examined by the Micro Octal Debugging Tool

normally con(MODT) program.

It consists of a 16-word buffer which stores a sequence of 16 microinstruction locations placed on the microinstruction bus (MIB) during
The 1last 1location to Dbe
the execution of user-written microcode.
stored is designated by the microprogrammer (using MODT). Once the 16
addresses have been stored, MODT may display the contents of the addressed locations in both octal and symbolic forms. See Chapter 7 for
a complete description.

1.6

REFERENCES

The

following

documents

provide

background

information

for

this

manual:

RT-11 System User's Guide, DEC-11-ORGDA-A-D

PDP-11 TECO User's Guide, DEC-11-UTECA-A-D

The Microcomputer Handbook, EB-07948-53

4.
5.

KDl1l-H processor schematic diagram, D-CS5-M7264-0-1

greater)

WCS schematic diagram, D-CS-M8018-0-1

Additional copies of all items above can be ordered from:
Digital Equipment Corporation
444 Whitney Street

Northboro,

Attn:

MA 01532

Communications Services

(NR2/M15)

Customer Services Sections

(revision

CHAPTER

THE

2.1

LSI-11

MACHINE

STRUCTURE

GENERAL

This

discussion of the LSI-11 machine structure covers both the architecture and operation of the LSI-1l.
Architecture relates to the system resources and their configuration.
Operation indicates
how
data

and

address

system

information

moved

between

and

manipulated

resources.

within

the

This chapter is a subset of the Microcomputer Handbook,
which
should
be
consulted
for
additional
detail,
specifically
1in the areas of
LSI-11 options and hardware.
This chapter emphasizes selected
topics

which
are essential to the understanding of the microprocessor contained within the LSI-1ll processor module.
Chapter 3 enhances
the
information
to include the additional information required to microprogram the LSI-11l micromachine.

2.2

MACHINE

The

LSI-11

machine

common

curately

ARCHITECTURE
consists

system bus.

represented

Any
using

three

specific

general

machine

specialized

component

areas

connected

configuration may

components

ac-

these

three

the

system

areas:

The

LSI-11

The

Memory

The

Input/Output

These

bus

Processor

Devices

components and their common,
are illustrated in Figure 2-1.

2.2.1

bidirectional

access

System Bus

The system bus is characterized by the number of memory
cations
addressable, the type of information transfers
by the auxiliary system control signals it contains.

or device
supported,

1loand

THE

LSI-11 MACHINE STRUCTURE

LSI-11 Machine Structure
Figure

2-1

[Lsi11 MACHINE
LSI-11

PROCESSOR

MEMORY

LSI-11 SYSTEM BUS

INPUT/OUTPUT

DEVICES

—— ————
e =]
MR-1014

THE

LSI-11

MACHINE

STRUCTURE

2.2,1.1
System Bus Address Space - The
virtual
(and
physical)
addressing
capability
of
the
system
bus is determined by the 16-bit
width of the binary addressing word.
The system bus supports
both
8
bit
byte
and 16 bit word addressing.
Figure 2-2 illustrates the address space with which the LSI-11 machine operates.
The
bottom
28K
(28,672)
word
addresses
constitute
the
memory
space.
The top 4K
(4096) word addresses are normally dedicated to the input/out
put
devices.
The LSI-11 processor does not occupy any address locations
.

2.2.1.2
ported

sor.

system

tion

System Bus Data Transfer - All data transfer operatio
ns
supthe system bus are under the control of the LSI-11 proces-

portion
bus

and

between

transfers

the

processor

the machine

possible

the

Interrupt-Driven

Direct Memory Access
I/0

are

Transactions

I/0

to
is

control

and

data

I/0)

(DMA

machine

execution

(Interrupt

Transactions

the

informa-

types

(Programmed

programmed
the

address

three

Transactions

Input/Output

response

the

data

machine:

Input/Output

Programmed

There

LSI-11

Input/Output

occurs

dedicated

transfer

components.

within

Programmed

example

the

Programmed
An

administrates

I1/0)

I/0)

instructions.
MOV

instruction

where at least one of the source or destination addresses is in memory
or
in a device register.
If both source and destination operands are
in the processor registers, no bus I/0 transfer is required.
The

simplest

(Data-In)

example

bus

Data/Address

Programmed

operation.

Lines

(BDAL

This

I/0

bus

transaction

operation

<15:00>)

are

illustrates

time-multiplexed

the
how

DATI
the

between

ad-

dress
and
data
information.
The
first event of the DATI cycle is
placing the memory or device address on BDAL L <15:00>.
After the address
information
settles
(or becomes valid), the BSYNC L signal is
asserted.

This signal causes each memory and I/0 DEVICE
module
conto the bus to check whether the address corresponds to its own
address(es).
Recognition by the addressed device is represented by
a

nected

signal
internal
to
that
device which is latched (or stored) by the
assertion of BSYNC L for the duration of the bus
operation.
Storing
this signal constitutes the second event.
The third event of the DATI

cycle
BDIN

removes

DATA-IN
BDIN

cycle

turns

the

This
is

the

BRPLY

address

signal
to

the

performed.

selected

information

informs
device

L<15:00>

and

asserts

selected

device

that

The

places

processor.

from BDAL

memory

The

fourth

its

event

data

assertion

BDAL

response

L<15:00>

BRPLY

and

the

a
to

re-

first

indication to the processor that the addressed component exists and is
putting data on the bus.
Upon receipt of BRPLY L, the
processor
accepts
the
information on BDAL L<15:00> as valid and stores it internally.

was

BRPLY

asserted,

means, the
or
device

fifth
ice

not

received

processor

trap

processor avoids
which
does not

event

subsequent

responds

seventh

and

gating BSYNC

the

final

waiting for
exist or is

accepting and

negation

BDIN

within

occurs

the

1In

the

lcoation

after
10.

BDIN
By

this

a reply from a memory location
malfunctioning.
The bus cycle

the

sixth

L by

processor

microseconds

memory

storing of

negation of BDIN

event,

input

event,

data

the

and

the

selected

dev-

terminating BRPLY L.

terminates

the

bus

cycle

the

ne-

THE LSI-11 MACHINE STRUCTURE

LSI-11 Machine Address Space

Figure

2-2
RESERVED VECTOR LOCATIONS
BUS ERROR, TIME OUT

RESERVED

DEVICE INTERRUPT
AND SYSTEM
TRAP VECTORS

BPT TRAP INSTRUCTION, T BIT
10T EXECUTED

POWER FAIL/RESTART
EMT EXECUTED
TRAP EXECUTED

CONSOLE INPUT DEVICE
CONSOLE QUTPUT DEVICE

376
400

EXTERNAL EVENT
LINE INTERRUPT
FIS TRAP

USER AND SYSTEM
PROGRAMS AND

STACK(S)

MEMORY

ADDRESS

(28K LOCATIONS)

NOTE

DEVICE VECTORS AND DEVICE
ADDRESSES ARE SELECTED BY
JUMPERS LOCATED ON THE DEVICE
INTERFACE MODULES

32K MAXIMUM

WORD LOCATIONS

157776
160000

DEVICE & REGISTER

RECOMMENDED FOR
PERIPHERALS 1/O
DEVICE ADDR., ETC.

LOC 177776

MEMORY ORGANIZATION
NOTE

THERE 1S 32K OF USERS MEMORY SPACE
AVAILABLE; HOWEVER 0-28K IS RECOMMENDED FOR MEMORY ADDRESS
LOCATIONS, AND 28K—32K FOR PERIPHERALS I/0 DEVICE ADDRESSES, ETC.

MR-1202

THE

The

DATI

book
and

bus

along
DATIOB

bus

processor

bus

the

cycles.

from

and

ing

I/0

device

BIRQ

device
rupting

"B"

LSI-11

bus

the

system

bus.

LSI-11

When

vector

address.

execution

device

the

service

Once

resumes

Priority among multiple
ity
is established via
to

the

execution

processor

within

the

asserting

only

DATIOB

cycle

device.

bus

cycles

byte

rather

The

processor

vector

service

interrupt-

asserting

address

program

been

interrupted

tells

1is

the

LSI-11

processor

both
Programmed I/0 and
tership be granted to an
transfer

I1/0

suspended.

and

completed,

program.

the

higher

priority.

The

the device being serviced, thus
priority
devices
impossible.

remains

from memory.

The

device

master

Interrupt I/0,
Input/Output

Interrupt

the

During

I/0

DMA

operations

functioning

DMA I/0
device

of
bus

I/0

the

system

bus

during

requires that bus
for
high
speed
transaction,

LSI-11

master

can

processor.

Note

that

Programmed

I/O
or
operations

during

DMA

I/0,

the

Interrupt

between

CPU

module

mas—
data

the

Pro-

processor
now

waits

are

perform

possible bus cycles (DATI, DATO, DATOB, DATIO,
DATIOB).
DMA
transfer is completed, bus mastership is relinquished

the

located

book.

(such

from higher priority (electrically closer) devices
acknowledged and serviced.
Additional details
regarding
I/0
transactions
are available in the Microcomputer Hand-

still
Interrupt

the

acknowledges

program has
the

posesses

interrupts

may

data

external devices having Interrupt I/0 capabilelectrical position relative to the processor.

interrupt
grant
chain
is
broken by
making further interrupts
from
lower

grammed

the

allows

while

and

bus

The

the

processor

Although

enable

This

processor

the

LSI-11

Further

the

Input/Output

from the

cycles

manipulated

DATOB

bus

location

address

memory.

closer

HandInput-Output)

(Data

asserting the BIACK H signal, it causes the interis electrically closest to the
processor
on
the

device

service

the

The

suffix

same

Microcomputer

operation.

location,

the

output portion

return

where

the
DATIO

(Input-Output)

addressed

initiated

request
by
device that

processor

"IO"

Read-Modify-Write

The

requests

signal

The
a

indicates
that
the
than a word transfer.
Interrupt

STRUCTURE

in detail in
(Data-Out), DATOB,

re-deposited

address.

MACHINE

described
DATO

execute

retrieved

processor,

one

cycle
with

LSI-11

I/0 only.
Any other processor
registers) can continue.

any

When

the

perform

activity

2.2.1.3
required

System Bus Control Signals - In addition to
the
bus
signals
to support Programmed I/0, Interrupt I/0O, and
DMA I/0 several
auxilliary control signals are contained within
the bus system.
System Initialization Signal
The
the

mand

common system initialization signal is
processor whenever BDCOK H is passive

is issued
Power-up

the

tion.
alizae
Power

Two

clear

Supply

signals

is asserted by
the BINIT com-

the processor.
Examples of the
latter
are
during
routine
and in execution of the RESET machine instruc-

All peripheral
and

BINIT L.
It
and whenever

devices

internal

should

flip-flops

use

the BINIT

and

registers.

signal

initi-

Signals

which

indicate

the

status

the

system power

supply

are

THE LSI-11 MACHINE STRUCTURE

part of the bus system.

These signals are generated by the power sup-

ply itself and the processor monitors them to take appropriate action
during Power-Up and Power-Fail sequences. At the beginning of the
BDCOK H 1is
Power-Up sequence, BDCOK H and BPOK H are both passive.
and all
itself
es
initializ
processor
the
whereupon
asserted first,
system components and waits for BPOK H to be asserted. When BPOK H is
asserted, the processor executes the jumper selected Power-Up routine.
During a Power-Down or Power-Fail sequence, BPOK H is negated first,
causing a Power-Fail trap. The processor then executes the program
located at the trap vector address (24). When BDCOK H goes passive,
It should be noted that a proper
the processor asserts BINIT L.
restoring

BPOK H.

The only signal in the bus system directly controlled by the

operator

Power~Fail sequence

will

negate

BDCOK H

before

BDCOK H must go passive to re-initiate the Power-Up sequence.
Processor Control Signal

of the processor is BHALT L.

This signal is asserted by a front panel

(PDP-11/03) switch or alternately by the BREAK key on the console terPressing the BREAK key causes a framing error which asserts
minal.
BHALT L via the console serial line interface. When the front panel
Run/Halt switch is used to halt the processor, it must be reset to RUN

before the processor can proceed.

However, pressing the console BREAK

key asserts BHALT L only as long as the key is depressed.

Processor Monitor Signal

The ability to monitor the Run/Halt state of the processor is provided
by the SRUN signal. The SRUN signal is asserted once each time the
processor performs a Machine Instruction Fetch. This signal 1is the
input to a circuit on the PDP-11/03 console that drives a RUN indicator

light.

Memory Refresh Control

All dynamic MOS memory modules which do not have self-contained refresh capability must be refreshed via the system bus. A signal
called BREF L. is asserted during the addressing portion of the
BSYNC/BDIN transaction to differentiate between memory refresh and the
standard DATI bus cycle.

2.2.2

Memory

The memory component of Figure 2.1 may be implemented with either sem-

Each memory device has operating
iconductor or magnetic devices.
is to be used in a particular
it
how
determine
which
stics
characteri
system.

Most memory devices function as Read/Write memory and may be
by either the processor or a DMA I/0 device.

accessed

THE

LSI-11

MACHINE

STRUCTURE

2.2.2.1
Semiconductor Memory - Semiconductor
memory may be classified
as
either dynamic or static memory.
The most familiar example of dynamic semiconducor memory is the 4K MOS Read/Wr
ite memory
located
on
the

KD1l1l-F

cally

LSI-11

refreshed

Static
doese

processor

order

semiconductor
refreshing.

for

PROM

their

contents

module

contents

special

PROM

UVPROM

also

subsequently

clearing

the

2.2.2,2

Dynamic

its

must

be periodicontents.

contents

module

and on
non-volatile

are

after power has been removed.
fusible link semiconductor memory
1link

MRV11-BA

memory

retain

PROM

UVPROM

fusible

the

can

and

established

grammed,
tents

MRV11-AA

even

contains

are

erased

programming

contents

programmed

memory

and

on the MRV11-BA UVPROM module.
An additionmemory type is Read Only Memory.
Read Only

types are found on the
module.
Both the PROM

retain

Dynamic

memory

memory is also available as Read/Write
An
example
of this type is the 256

16-bit words of RAM found
al
static
semiconductor

Memory
UVPROM

module.

the

by
by

preparation

exposure

for

not
UV

but

light,

Memory Refreshing - Three techniques are
the
requirement
for dynamic memory refreshing.
techniques are:

Processor

Controlled

Refresh

Direct Memory Access

Refresh

Distributed

pro-

The

its

con-

effectively

with

satisfy

Once

altered.

equipment.
to

they

MRV11-aAA
devices whose

re-programming

MRV11-BA

The

equipment.

can

special

the

types;

new

data.

available

These

to
three

Refresh

Processor Controlled Refresh is
a
feature
available
on
the
M7264
LSI-11
processor module.
This refresh mode is normally disabled, but
can be enabled by removing the appropriate jumper
on the module.
When
enabled,
a
600 Hz oscillator causes an internal interrup
t.
This interrupt initiates the execution of a microprogramme
d routine which refreshes
all
dynamic
memory devices used in the system.
The refresh
routine performs 64 BSYNC/BDIN cycles with
BREF L asserted,
occupying
the
system bus for about 130 microseconds.
When processor-controlled
refresh is employed, all dynamic
memory
mocules
should
have
their
Reply
During
Refresh
options disabled, except for the memory module
located farthest from the processor.
This assures
that
the
longest
bus delays will be compensated for during execution
of the refresh microprogram.

systems

Note

that

utilizing

this

lengthy

form

refresh

Direct Memory Access Refresh is performed
the
processor of refresh responsibility.
the

REV11l-A

from

the

refreshed

the
only

dead
may

and REV11-C modules.
processor-controlled

one

row
device

also

assure

perform

that

liseconds

time
controls

the

time,

DMA
1.3 microseconds
time inherent in

the

less.

row

The

DMA

method

instead

not

recommended

for

by a DMA device and relieves
Examples of DMA refresh are
refresh

technique

that

the

memory

all

rows

once.
purposes of

differs

modules

are
Therefore
refresh for

system bus for
thus eliminating the 130
microsecond
former method.
Any user-designed DMA device

refreshing

each

microprograms.

memory

long

proper

refreshed

sequencing

least

once

and

timing

each

mil-

THE LSI-11 MACHINE STRUCTURE

Distributed Refresh is the technique used by the MSV11-CD

memory

mo-

composed

This module is equipped with timing and sequencing circuitry
dule.
which performs refreshing for its own memory devices. - It refreshes
one row at a time every 25 microseconds and isolates itself from the
system during each row refresh. If the LSI-11 processor, or DMA device, requires a memory access when the module is refreshing a row, the
memory module merely delays its response by returning the BRPLY L signal after the row refresh is completed. The relatively short, occasional delays that occur with this technique are compatible with the
essentially asynchronous system bus data transactions.

The memory component of a specific LSI-11l machine may be
more than one memory type to satisfy user requirements.

2.2.2.3

Magnetic Memory - Magnetic Memory is non-volatile, so it does

not require refreshing. Therefore, memory contents stored in magnetic
core are not lost during a power failure. Magnetic memory can maintain the information of a partially-executed program or routine when
power is removed so that the routine may continue to completion when
A Power-Fail routine (which is initiated by the
power 1is restored.
processor Power-Fail trap) must save all volatile machine states
(e.g., the General Purpose Registers) in the magnetic portion of memory before power goes down (BDCOK H goes passive).

Input/Output Devices

2.2.3

to the LSI-11l system bus provide
The Input/Output devices connected

means for interfacing control and data information between the LSI-11
machine and the outside world. An example of an I/0 device which bidirectionally passes both data and control is the DLV1l serial line
unit which connects to the console terminal.

2.2.3.1

Device Address Format - All Input/Output device locations

the LSI-11

system

bus

are

accessed

1in the same manner as memory.

Normally, each I/O device has four sequentially-numbered word locaThese four locations provide for both contions associated with it.
trol and data transfer between the processor and I/0 device according
to the following convention:

Receive Control Status Register
Receive Buffer
Transmit Control Status Register
Transmit Buffer

XXXXX0
XXXXX2
XXXXX4
XXXXX6

The Receive Buffer

(RCSR)
(RBUF)
(XCSR)
(XBUF)

(RBUF) holds data which has been received from

the

1/0 device and which can be transferred to the processor or to memory.
reThe Receive Control Status Register (RCSR) contains control flags

lated

the

device

receive

function.

The Transmit Buffer

holds data which has been transferred to the I/0 device for

(XBUF)

presenta-

The Transmit Control Status Register
tion to the outside world.
(XCSR) contains control flags related to the device transmit function.

THE

2.2.3.2
port

Enabling

Device

interrupt-driven

LSI-11

MACHINE

Interrupts
I/0

before

the

Input/Output

transactions

interrupt-enabling mechanism which

cessor

STRUCTURE

device

must

can

2.2.3.3

DMA Transfer
is

Restrictions

equipped

explicitly

initiate

interrupt-enabling mechanism is reset
or disabled
the system initialization signal BINIT L.

transfer

devices which

are

- A Direct

set

sup-

with

the

pro-

interrupt.

The

Power-Up

Memory Access

time

(DMA)

data

accomplished by the DMA device becoming master
of the system bus (which suspends LSI-11 processor I/0
operations).
If the processor
1s responsible for dynamic refresh, only
single byte or single
word transfers are allowed to give the process
or opportunity
to
execute

cause

the

memory

refresh

lowable
time.
trictions on DMA

2.2.4
The

The

LSI-11

period

areas

are:

long

beyond

burst

the

DMA

transfer

millisecond

not

Figure

2.1

could

maximum

utilized,

al-

res-

Processor

greater

delay

If Processor-Controlled Refresh
transfer are eliminated.

LSI-11

with

routine.

module

internal

which

detail

The Arithmetic

The

general

The

Processor Control

Logic

Purpose

appears

Figure

2.3.

The

three

presented

functional

Unit
Registers

2.2.4.1
Arithmetic Logic Unit - The Arithmetic
Logic Unit (ALU)
performs
the
operations
required
for
the
machine
instruction
set.
Arithmeic operations employ two's comple
ment number representation
in
fixed
point
format.
With
the addition of the KEV11 EIS/FIS MICROM

(Extended/Floating Instruction Set), floati
ng point arithmetic
operaare also performed.
Arithmetic and logical operations are exe-

tions

cuted

both

byte

monitored

Processor

Status

erands

which

Purpose

four

and

word

Condition

Word (PSW)
constitute the

Registers,

data.

The

Code

Flags
register.
inputs

Memory,

results

(N,Z,V,C)
The

the

source

ALU

Input/Output

ALU

operations

which

may

are

part of the
and destination
opbe located in Gener-

device

registers.

2.2.4.2
General Purpose Registers - The Genera
l Purpose Registers are
located
within
the
Processor
and
thus their contents
are accessed
without the use of a system bus operation.
The registers may
contain
data
or
address
information.
Registers R6 and R7 are dedicated to
Stack

Pointer

therefore

(SP)

and

associated

Program

with

Counter

(PC)

use,

respectively,

and

are

Processor Control.
Both byte and word addressing is supported for registers RO
through R5.
Because
of
their
dedicated application, registers R6 and R7
allow word addressing only.

THE LSI-11 MACHINE STRUCTURE

LSI-11 Processor Detail
2-3

Figure

"'"i

isii1prOCESSOR
[

|
|

l
PROCESSOR |

CONTROL

POINTER

R7) esw|

| | REeGISTER [R2)

|RecisTER (R3]

SRocram | |
COUNTER

SOURCE

DESTINATION

OPERAND OPERAND

ARITHMETIC

UNIT

LOGIC

MEMORY

outeut
DEVICES

weur

I
|

[CC]

L—‘%—l——d—__— —-—J

LSI-11 SYSTEM BUS

>
MR-1016

2-10

THE

LSI-1l1l

2.2.4.3
Processor Control functions
peformed
by
the
four areas are:

Processor

Machine

Address Generation

System Bus

These

four

(1)

status

the

PDP-11/03,

the

of
processor

will

performed

1in

the

cause

associated

and

(2)

informed

signals

(see

Power-Up

the

H780

supply

BPOK

either

the

processor resources
are
illusProcessor Control is determined by

Overall

processor

response
in

Control)

Execution

system power

BDCOK

originate

into which
all
divided.
These

Control

means

BPOK

Instruction

and their
Figure
2-4.

STRUCTURE

There are four main areas
Processor Control may be

(Overall

areas

trated

the

Control

MACHINE

status

power

supply

the

power

operator.
supply

Section

Power-Fail

these
and

and

sequence

and

BDCOK

exact

timing details are contained in The Microcomputer Handbook.
al, BPOK H is the last signal to be asserted in
a
Power-Up

and

the

BDCOK

first

supply,

the

signal

passive,

passive

indicating

asserts

BINIT

Reset

state.

When

the

and

the

lowest

forces

the

processor

Power-Fail

state

the

1In genersequence

sequence.

When

system

power

the

microprocessor

1is

The

operation

signals.

their

status

2.2.1.3).

Control

Run

chip

state,

the
change
of
BPOK H from active to passive will cause a Power-Fail trap
to be performed.
The Power-Up mode is determined via jumper
configuration
on the processor module.
The means by which the Processor in-

terprets

are

the

further

the

jumper

configuration

detailed

Machine Operation

Control

over

means:

the

(1)

state

sole

and

the

control

section

Operator

the

(Section

LSI-1l
the

supply

diagram of
2.3).

processor

front

ODT.

power

flow

1is

status

Figure

achieved

panel

Run/Halt

the

switch

signals

2.16-2

through
and

two

(2)

Con-

and

the

Placing the Run/Halt switch in the Halt position
causes
a
interrupt
which
passes control to the microprogrammed ODT routine.
Once the processor has entered the Console ODT/Halt state,
the
Run
state
may
be
reentered by operator execution of the "P" or "G"
Halt

commands.

When

the

Run/Halt

switch

Halt

position

"P"
command
is
repeatedly
issued, single-step program execution is
achieved.
A complete description of Console ODT is in
The
Microcom-

puter
As

Handbook.

shown

Status

Word

areas.

The

the

Figure

(PSW)
four

2.4,

the

ALU

condition

struction

contents

have

been

code

divided

flags

appear

the

LSI-11

and

Processor

allotted

the

Machine

two
In-

execute
sub-area and the Trace Trap and External Interrupt
flags appear in the Trap
& Interrupt
Service
sub-area.
The
complete
PSW, which the operator may access by either the "RS"
("$S")
Console ODT command or under program control via the MFPS or MTPS
maEnable

chine
are

instruction,

conditionally

manipulates data

set

illustrated

the ALU

result

in Figure

moves

any

2.5.

The

processor

data within

the

four

lower

operation

LSI-11

flags
which

machine.

THE LSI-11 MACHINE STRUCTURE

Processor Control Functions
Figure

2-4

PROCESSOR CONTROL

POWER-UP OPTIONS

POWER SUPPLY STATUS

POWER-FAIL TRAP
RUN/HALT SWITCH

OPERATOR CONTROL

CONSOLE ODT

ADDRESS GENERATION

INSTRUCTION EXECUTION

INSTRUCTION ADDRESS

INSTRUCTION TYPES

DATA MANIPULATION
PSW CONTROL
PROGRAM CONTROL

PROGRAM

COUNTER [R7]

FETCH

<+— MACHINE

INSTRUCTION

OPERAND ADDRESS

ARITHMETIC LOGIC UNIT
CONDITION CODES

PSW BITS <3:0>
SOURCE OPERAND
GENERAL PURPOSE

DESTINATION OPERAND

REGISTERS [RO—RS5]

TRAP AND

STACK

POINTER [R6]

INTERRUPT

SERVICE

PSW BIT 7
PSW BIT
4

SYSTEM BUS CONTROL

MR-1017

2-12

THE

LSI-11

Processor

MACHINE

Status

Figure

STRUCTURE

Word

(PSW)

2-5

RESERVED |
|

EXTERNAL INTERRUPT ENABLE
TRACE
TRAP ENABLE

NEGATIVE CONDITION CODE
ZERO CONDITION
CODE

OVERFLOW CONlleION CODE
CARRY CONDITION CODE
MR-1018

2-13

THE LSI-11 MACHINE STRUCTURE

Data moved between a memory location and a device register will affect

the
condition codes as will the execution of an arithmetic or logical
operation.
The specific condition code functions for each machine instruction
are
found
in The Microcomputer Handbook.
The Machine Instruction Execute area performs the operations dictated by the fetched
machine
instruction.
All
members of the LSI-11 Machine Instruction
Set may be classified in the three following groups:
l.

Data Manipulation Instructions

Program Control

Processor Status Word Control Instructions

Instructions

Data Manipulation instructions include all single and
double
operand
exception of the PSW operators MFPS and MTPS.
the
instructions with
All instructions in this group set or reset the ALU condition codes as

a result of the operation performed.
None of the instructions in this
group can change the processor priority, PSW BIT 7, or the trace
trap
enable,

These

PSW BIT

instructions are

listed below.

Single Operand

CLR(B), COM(B), INC(B), DEC(B), NEG(B), TST(B)
General:
Shift & Rotate: ASR(B), ASL(B), ROR(B), ROL(B), SWAB
Multiple Precision: ADC(B), SBC(B), SXT
Double Operand

General:
Logical:

MOV (B),
BIT(B),

CMP(B),
BIC(B),

ADD, SUB
BIS(B), XOR

The KEV1l EIS/FIS (Extended/Floating Instruction Set) adds four
point and four floating point instructions to the group.
Extended Fixed Point:

FADD,

Floating Point:

DIV,

MUL,

FSUB,

ASH,

FMUL,

fixed

ASCH

FDIV

The Program Control Instructions are divided into two sub-groups,

de-

The execution by
the PSW contents are affected.
on whether
pending
the processor of any instruction in the first sub-group has no effect
Branch,
all
includes
sub-group
This
contents.
PSW
the
on
Jump & Subroutine,

Branch:

and Miscellaneous
BR,

BNE,

BEQ,

instructions.

BPL,

Signed Conditional Branch:

BMI,

BVC,

BVS,

BCC,

BGE,

BLT,

BGT,

BLE

Unsigned Conditional Branch:

BHI,

Jump

RTS

Subroutine:

Miscellaneous:

JMP,

JSR,

HALT, WAIT, RESET,

2-14

BLOS,

SOB

BHIS,

BCS

BLO

The

second

sub-group

THE

LSI-11

MACHINE

STRUCTURE

Program

Control

instructions

1is

executed

1in

the Trap & Interrupt Service area shown in Figure 2.4.
These instructions can control every working bit in the PSW by moving a byte to the
PSW register from a vector location or from the stack.
Trap

Processor

Status

the

PSW
set

clear

instruction

Interrupt:

Word

EMT,

Control

any

The

combination

included

BPT,

Instructions

contents.

also

TRAP,

exert

condition

here.

the

IOT,

RTI,

direct

code

RTT

control

operators

condition

may

over

used

flags.

The

NOP

because

their

ex-

code

Condition Code Operators
Clear:

CLC,

CLv,

CLzZ,

CLN,

CCC

Set:

SET,

SEV,

SEZ,

SEN,

SCC

NOP

Two

single operand instructions belong to this
ecution affects the PSW register contents.
Processor

Status

Word

group

Operators

MFPS

MTPS
The

MFPS

(Move

the

PSW

byte

From

Processor

contents

tion.
If the destination
through
the upper byte of
PSW

contents

information

The

MTPS

through

the

is
the

Status

mode
0,
register.

processor

the

Z
V

=
=

if PSW Bit <7>
Set 1if PSW<K7:0>
=
<cleared

not

the

instruction

contained

PSW BIT 7
However,

according

Set

byte

word)

destination

(Move

PSW

the

is
the

destination

the

transfers

the

instruc-

sign
extended
movement of the
will

following

modify

rules.

the

cleared otherwise
cleared otherwise

affected

Processor

Status

word)

instruction

transfers

the
8
bits
of
the source operand to the PSW register.
All working
bits may be set or cleared, except the Trace Trap Enable (PSW Bit <4>)
which may only be cleared.
The

LSI-1ll machine instruction set contains four
additional
instruction
groups
which
have
no assigned mnemonic:
21R,
075040-075777, 076000~-0767717.

The

21R

nal

temporary

inted
the

to
end

opcode

by
of

(where R
registers

the

contents

execution.

is
to

reserved
220-227,

a 0 - 7) causes the contents of the
interbe transferred to consecutive locations po-

internal

registers

not

accessed

restored
by

this

at
in-

struction are illustrated in Figure 2.6, which also shows their
relationship to the Processor Control Functions.
This instruction is used
for diagnostic purposes only and
belongs
to
the
Data
Manipluation
group

listed

above.

THE

Processor

Control

LSI-11

MACHINE

Functions

STRUCTURE

(With

Figure

Internal

Registers)

2-6

PROCESSOR CONTROL

POWER-UP OPTIONS

POWER SUPPLY STATUS

POWER-FAIL TRAP

OPERATOR CONTROL

RUN/HALT SWITCH
CONSOLE ODT

ADDRESS GENERATION

INSTRUCTION EXECUTION

INSTRUCTION ADDRESS

INSTRUCTION TYPES
DATA MANIPULATION
PSW CONTROL
PROGRAM CONTROL

INSTRUCTION

COUNTER [R7]

—® REGISTER

INSTRUCTION

OPERAND ADDRESS

(RIR)

ARITHMETIC LOGIC UNIT
CONDITION CODES
PSW BITS 3—-0

(RPSW REGISTER)
SOURCE OPERAND

GENERAL PURPOSE

(R5RC)

REGISTERS [RO—RS5]

DESTINATION OPERAND
TRAP AND
STACK

INTERRUPT

POINTER [R6]

SERVICE

BUS ADDRESS

(RDST)

PSW BIT
7
PSW BIT
4

(RBA)
SYSTEM BUS CONTROL

MR-1019

THE

Machine-level

control

LSI-11

execution

of
transferred

MACHINE

STRUCTURE

instructions in the range of 220-227 causes
to the microinstruction located at microad-

dress 3000 (in user control store).
If control store is
not
present
(or
1if it is disabled) a reserved instruction trap through memory location 10 will occur.
(See the Microcomputer Handbook for a
description of illegal instruction traps).
Instructions
transferred
user control

disabled),

in the range 075040 through 075777 cause
control
to
to
the microinstruction located at microaddress 3003
store).
1If control store is not present
(or
if
it

reserved

instruction

trap

through

memory

location

be
(in
is

will

occur.

The availability
unique
Machine
0767XX operation

of Writable Control Store enables the user to
Instructions.
These
instructions
are based

design
on the

code assignment, as shown in Figure 2.7.
The
execution
of
this type of instruction causes control to be transferred to
microaddress 3001 where the microprocessor
begins
execution
of
the
user-microprogrammed
076XXX

only

format

opcodes

instructions.
user

routine.

transfer

the

The

lower

range

differentiate

the

microprocessor.

The

Address

Operand

Generation

Address

dedicated

six

bit positions

between

area

user

serves

generation

Note

that
all
instructions
of the
the same microlocation
(3001),
but
076700 to 076777 may be utilized for user

control

both

the

functions.

the

may

then

instructions

be
or

employed
to

carry

the

data

1Instruction

Instruction

Program Counter

(PC)

Address
and
addressing employs

and

1increments

the

counter
by
the
number of word addresses required by the machine instruction currently under execution.
Instruction addressing may
also
be modified by Program Control instructions, Trap & Interrupt Service,
Power-Up routines, or by operator intervention through Console ODT.
Operand

Address

generation

supports

the

eight

General

Purpose

Program

Control

group.

addressing modes and the four Program Counter addressing modes for determing the source and destination operands.
Register
R6,
dedicated
to
Stack
Pointer
use, is employed by the Operand Address generation
function,
Trap & Interrupt
Service
operations,
and
by
the

Jump

2.2.5

Subroutine

machine

The

Writable

LSI-11

instructions

Control

the

Store

The User-Microprogrammed machine
Figure 2.7) transfers control to
Control

Store).

cess

Read/Write

user—-programmed
processor.

and

the

The

Writable

The

user

instruction
format
(illustrated
in
the user control store area (Writable
control store area is composed of random ac-

semiconductor

microinstructions
1interconnection

Control

Store

memory

between

(WCS)

which

accessed

module

contains

the

LSI-11

shown

LSI-11

processor

Figure

the
micromodule

2.8.

LSI-11

THE

STRUCTURE

MACHINE

User~Microprogrammed Machine
Figure

Instruction Format

2-7

USER

(USER-MICROPROGRAMMED MACHINE INSTRUCTION)

OP CODE OCTAL

076700 THROUGH 076777

OPERATION

0/1

]

0/1

071

MR-1020

THE

MACHINE

Processor-Writable

Control

Figure

PROCESSOR

CONTROL
AR

[SGTTER

POI

PROGRAM
COUNTER

[R7] [PSW]

_______T

|
|

\4
SOURCE
OPERAND

DESTINATION
QPERAND

I
|
|

ARITHMETIC /

L—k%

IS GEEES GEIEE GG EEED NS WS SRS

Interconnection

Store

2-8

| LSI-11 PROCESSOR

|
|
I

STRUCTURE

LOGIC

[CC]

UNIT

L__—————————T——_———

LSI-11

WRITABLE
CONTROL
STORE

LSI-11 SYSTEM BUS

MEMORY

INPUT/

OUTPUT
DEVICES

>
MR-

1021

THE

LSI-11

MACHINE

STRUCTURE

The WCS module is connected to the LSI-11 machine in two ways:
1.

LSI-11 System Bus

Micromachine Microinstruction Bus

LSI-11 System Bus Connection - This connection is established
2.2.5.1
the printed circuit contact fingers which insert into the system
by
The WCS module contains 1024 24-bit microlocations which
backplane.

may be read and written via Programmed I/O operations. The LSI-11
system bus interconnection and WCS module control and data registers
are detailed in Chapter

the
2.2.5.2 Microinstrucion Bus Connection - The connection between
control area and the WCS module is established by a
LSI-11 processor
The third MICROM socket on
special MicroInstruction Bus (MIB) cable.

the LSI-11 module

(E32 on the M7264), which is usually occupied by the

control
The processor
EIS/FIS option, provides access to the MIB.
area sends microlocation address information to the WCS module and the
contents of the selected location are returned for use by the microThe processor/WCS port is Read Only;
processor as a microinstruction.
WCS memory contents can be read but not altered by the LSI-11 procesThe WCS memory performs the same function with
via this port.
sor
respect to the micromachine as do the MICROMs located on the LSI-11
The details of microinstruction access are contained in
module.
Chapter

2.3

2.3.1

MACHINE

OPERATION

Basic Machine Cycle

The basic machine cycle

in its simplest form is a

repeating

sequence

of
Fetch Machine Instruction - Execute Machine Instruction operations
DATI
one
The Fetch operation requires
as illustrated in Figure 2.9.
(Data-In)
bus cycle and the Execute operation may require one or more
bus cycles as determined by the instruction being executed.

is
2.3.1.1 Bus Error Trap - Implemented with the basic machine cycle
system bus error trap mechanism, which aids the processor in rethe
the
occurs whenever
error
A bus
covering from a system bus error.
processor addresses a memory (or device) location which does not exist
on the system bus or which does not respond due to a malfunction.
The
bus error trap is initiated by a timeout seqguence which is implemented
in the processor bus control circuitry.
The bus error
condition
occurs
when no memory or device response is received within 10 microseconds after

initiating

the bus cycle.

LSI-11

Basic

MACHINE

LSI-1l1l

STRUCTURE

Machine

Figure

Cycle

2-9

FETCH
MACHINE

INSTRUCTION

EXECUTE
MACHINE
INSTRUCTION

THE

MR-1022

THE

A bus error can occur

for

LSI-11

MACHINE

STRUCTURE

the Fetch DATI bus cycle as well as for

any

The trap which
the Execute operation.
cycles performed during
bus
Program
the
to push
responds to the bus error causes the processor
Counter
(PC)
counter and Processor Status Word (PSW) values onto the
and
(10
locations
stack and to load new values from the trap vector
12).

The

vector addresses contain the new PC and the new PSW.

these operations have been completed, the

processor

will

fetch

When

its

However,
next instruction from the location pointed to by the new PC.
to
pointed
it is also possible that a fetch from the memory location
the stack pointer will also cause a bus error, resulting in a douby

ble bus error condition.

The processor response to this condition

1is

The single and double bus error trap operaenter the Halt state.
to
tions are illustrated in Figure 2.10.

2.3.1.2
External Interrupt - The basic
Fetch-Execute
machine
cycle
can be modified to allow an external event to gain control of the proa
of
execution
the
Once
2.11.
cessor, as illustrated in Figure
fetched machine instruction is completed, control passes to a decision
If an interrupt
path which interrogates the machine interrupt status.

is pending, the processor action is nearly identical to that caused by
the trap (the current PC and PSW values will be pushed
on
the
stack
and
new values loaded from the interrupt vector).
The interrupt vector may be automatically known to the processor (as in the
Event
inor the processor can obtain the vector from the intercase)
terrupt
rupting external device (see Section 2.2.1.2).

the
When the PC and PSW contents are replaced, control is returned to
This control flow enables the creation of an indecision.
interrupt
a
of
terrupt (and trap) priority structure that determines which one

1is to receive service.
1interrupts
simultaneously active
of
number
1is
interrupts
device
external
Note that the granting of service to
upon electrical bus position relative to the procesdependent
still
the decision
top of
the
Since control is always returned to
sor.
are assured of service, in order of decreasing
interrupts
all
path,
priority,

2.3.1.3
between

before normal program execution resumes.

Combined Trap and Interrupt Cycle - Because of the similarity
the
interrupt
and trap operations, a single microprogrammed

1is
The vector information
routine implements the required functions.
An ad1in an internal register before the routine is entered.
stored
ditional flag internal to the processor indicates the double bus error
The combined interrupt and trap control
(see Section 8.9).
condition
flow diagram is illustrated in Figure 2.12.

THE

LSI-11

Single

and

MACHINE

Double

Figure

STRUCTURE

Bus

Errors

2-10

FETCH

MACHINE

INSTRUCTION

BUS ERROR
—s»

(SINGLE)

EXECUTE

MACHINE

IUS
ERROR
INSTRUCTION BUS
ERRO #» (SINGLE)

VEC

004

BUS
ERROR
TRAP

PUSH

PC,PSW

GET

PC,PSW

BUS ERROR
(DOUBLE)

HALT

MR-1023

THE

External

LSI-11

MACHINE

Interrupt

and

Figure

STRUCTURE

Bus

Error

Trap

2-11

FETCH
MACHINE

INSTRUCTION |-BYS ERROR

(SINGLE)

EXECUTE
MACHINE

INSTRUCTION |.BYS ERROR

EXTERNAL
INTERRUPT.”

(SINGLE)

VES

VECTOR

100 OR DEVICE

BUS ERROR
PUSH

PC,PSW

GET

PC.PSW
VEC
sUs

004

ERROR

TRAP I pusH pcpsw
GET

PC.PSW

BUS ERROR

(DOUBLE)

HALT

\
MR-1024

THE

Combined

LSI-11

MACHINE

Interrupt
Figure

STRUCTURE

and Trap Operations
2-12

FETCH

MACHINE

INSTRUCTION }-BYS ERROR

(SINGLE)

EXECUTE

MACHINE

INSTRUCTION

|.BUS ERROR

(SINGLE)

VEC

004

(DOUBLE)
(DETERMINED BY
BUS ERROR

PUSH

PC,PSW

GET

PC.PSW

INTERNAL FLAG)

HALT

MR-1025

THE

2.3.2

LSI-11

MACHINE

STRUCTURE

Complete Machine-Level Operating Cycle

The essential principles of the control flow configuration
in Figure 2.12 may be summarized as follows:
1.

illustrated

The untrapped, uninterrupted machine cycle is a repeating segunce of Fetch Machine Instruction - Execute Machine Instruction operations.

The trap facility allows the
(single) bus error condition.

processor

recover

from

The control flow configuration of the interrupt and trap
operations,
1in conjunction with the hardware stack, implements
the interrupt priority hierarchy.

These principles are also apparent in Figure 2.13, which illustrates a
more
exact
machine-level control flow diagram.
The complete diagram
must detail the transfer of control between the machine
and
micromachine
levels and is presented in a later section.
Figure 2.13 illustrates the Fetch-Execute-Trap/Interrupt machine cycle which is
sufficient
for conventional machine level programming.
It shows the loca-

tion in the control flow of the Trace Trap Bit

(PSW BIT <4>),

paths to the Console ODT/Halt state as well as

the

External

Interrupt

Enable Bit

leave ODT and re-enter

(PSW Bit

<7>).

Also shown are

two

and

paths

the

the Fetch-Execute cycle of the Run state.

the

two

which

2.3.2.1
Run/Halt Portion - The Run/Halt portion of Figure 2.13 is extracted and illustrated in Figure 2.14.
The two means of entering the
Halt state are:
(1) the execution of the HALT machine instruction and
(2)
the
assertion of the Halt interrupt.
The latter is asserted via
the bus control signal BHALT L by setting
the
front
panel
Run/Halt
switch
to Halt or by pressing the console terminal BREAK key.
The PC
contents are printed on the terminal
immediately
upon
entering
the
Halt state.
This gives the location of the next instruction to be exEither the "P" or "G" commands may be entered by the operator
ecuted.
Entering the "P" (PROCEED) command passes
terminal.
console
the
at

"G"
The
control directly to the Machine Instruction Fetch operation.
command loads a new PC value (nnnnnnG) and zeroes the PSW (which
(Go)
enables external interrupts) before passing control to the Machine Instruction Fetch

operation.

2.3.2.2
Trap/Interrupt Portion - The
Trap/Interrupt
portion
of
Figure 2.13
1is
extracted
and illustrated in Figure 2.15.
The Trace
Trap has the highest machine-level priority and affects
control
flow
before any external event.
The Trace Trap uses the same vector value,
(014), as the Breakpoint Trap (BPT) instruction.
The
hardware
Trace
Trap,
implemented
via PSW BIT 4, and the software Trace Trap, implemented via the execution of the BPT instruction, are used
to
support
program debugging.

THE

Complete

LSI-11

MACHINE

STRUCTURE

Fetch-Execute-Interrupt

Figure

Cycle

2-13

FETCH
MACHINE

INSTRUCTION | BUS ERROR

(SINGLE)

EXECUTE

MACHINE

INSTRUCTION |BYS ERROR

(SINGLE)

YES

>
(PRINT PC]
t=

XTERNAD

INTERRUPT > (PSW BIT 7)

CONSOLE

ENABLE

oDT

DEV

100©

004
[LOAPPm

{PSW=0]
PUSH

PC,PSW|BUS

GET

PCPSW|ERROR

[BINIT]

(DOUBLE)

MR-1026

THE

LSI-11

MACHINE

STRUCTURE

Run Halt Portion of Machine Cycle
Figure

2-14

FETCH
MACHINE

INSTRUCTION

EXECUTE
MACHINE

INSTRUCTION

HALT

YES

[PRINT PC]

CONSOLE

OoDT

[LOAP PC]
[PSVIV=0]
[BI l\ll IT]
MR-1027

THE

Interrupt

LSI-11

and

Trap

MACHINE

STRUCTURE

Portion

Figure

Machine

Cycle

2-15

[
MACHINE

INSTRUCTION
FETCH

MACHINE
INSTRUCTION
EXECUTE

TR;E\\\ YES

TRAP BIT

(PSW BIT 4)

EXTERNAL
INTERRUPT
ENABLE

{PSW BIT 7)

YES

EVENT

YES

DEVICE

YES

VEC

DELV

100

VEC
014

PUSH

PC,PSW

GET

PC,PSW

|
MR-1028

THE

The

External

Interrupt

LSI-11

Disable

MACHINE

STRUCTURE

(PSW Bit

<7>=1)

can

divert

control

flow

around
Event
and
device interrupts.
When enabled, the Event interrupt, asserted via the bus signal BEVNT L, will receive service before
any device interrupts.
All external devices having interrupt capability assert the same interrupt request line, BIRQ L.
Interrupt priority
external to the processor is determined by the position of the module in the LSI-1l1 backplane.

2.3.3
The

Complete

complete

Machine-Micromachine Operating

control

flow

diagram which

makes

Cycle
apparant

the

transfer

control
between the machine and micromachine levels is illustrated in
Figures 2.16-1 and 2.16-2.
A greater number
of
machine
instruction
examples
are
used to represent the decisions made during the Execute
Machine Instruction operation of the basic machine cycle.
Many of the
examples
used demonstrate the internal sharing of the microprogrammed
Trap/Interrupt service routine.

2.3.3.1
Power-Up

Bus Error
decision

Processing - The
flow
1in Figure

entry point
at
the
2.16-2 is the result

top
of a

of
the
hardware

reset in the case of a bus error.
A wait state occurs due to
an
unresponding
bus device, but the wait is terminated by a 10 microsecond
timer on the LSI-11] CPU module that resets the
microprocessor.
When
reset, the microprocessor begins executing microinstructions at microlocation 0001.
The FDIN (Fast Data-In) operation is used to to determine how control flow arrived at that entry point, either by bus error
or

Power-Up.

bus

error

was

the

cause,

only

one

the

pos-

sible
bus
error
types will result in a trap through vector location
004.
The first possible bus error is used by
a
microprogrammed
ODT
routine
to
determine
memory
size (Boot Self-Size).
The second bus
error type occurs when the operator attempts to examine (using Console
ODT)
a
memory
or
device
register which does not respond.
1In this
case, control is returned to a point within the ODT
microcode
and
a
"?"
is
printed
on
the
console terminal.
The next three bus error
types are regarded as fatal and result in a processor Halt.
These errors
occur
(1) when an interrupting device does not return a vector,
(2)
(3)

when
when

2.3.3.2

a
a

microprogrammed
double bus error

Trap/Interrupt

refresh
occurs.

Processing

does

The

not

receive

Trap/Interrupt

reply,

decision

flow

indicates
the priority with which the micromachine interrupt register
is interrogated.
This internal micromachine interrupt register is illustrated
1in Figure 2.17.
Of the seven interrupts, four are external
and three are internal.
An internal interrupt in this context is
one
which can be set or reset only under microprogram control.

Complete

L5I-11

MACHINE

Machine-Micromachine
Figure

STRUCTURE

Control

Flow

Diagram

2-16-1

FETCH
MACHINE
INSTRUCTION

IBUSERROR

| EIS/FIS

: b vh

THE

3002
USER CONTROL STORE
ENTRY POINTS

3004|
3003

BINIT

RFRSH

RET

3001

1 3000

YES

LSI-11

MACHINE

INSTRUCTION

EXECUTION

VEC

034

030

020

MR-1029

THE

LSI-11

MACHINE

STRUCTURE

Complete Machine-Micromachine Control
Figure

Flow

Diagram

2-16-2

POWER UP

OR BUS
ERROR FDIN
YES

YES

PC=173000

YES

PSW=200

YES

FROM

BOOT SELF
SIZE

(

PRINT PC

—4

ODT/HALT

F———

VEC004

PUSH PC,PSW

GET PC,PSW

VEC

024

VEC

014

VEC

DEV

VEC

100

“G'

YES

LOAD PC

PSW=0

BINIT

MR-1030

2-32

THE

LSI-11

Micromachine

MACHINE

Interrupt

Figure

STRUCTURE

2-17

LISTED IN ORDER OF DECREASING PRIORITY

I6:

INTERNAL

I0:

EXTERNAL

DYNAMIC

I4.

INTERNAL

TRACE TRAP BIT (PSW BIT-4)

TEST FOR EXTERNAL INTERRUPTS120R
13
MEMORY REFRESH

I5:

EXTERNAL

POWER-FAIL/HALT INTERRUPT

Ib:

INTERNAL

ENABLE EXTERNAL INTERRUPTS | 2

I2:

EXTERNAL

EVENT INTERRUPT

I3:

EXTERNAL

DEVICE INTERRUPT

AND | 3 (COMPLEMENT OF PSW BIT-7)

MR-1032

THE

LSI-11 MACHINE

STRUCTURE

The highest priority interrupt is I6 which is used only at the
micromachine
level
to
determine
whether
an
external
interrupt
(I2: Event, I3: Device) is pending.
This facility enables
a
1lengthy
microroutine
to
abort
execution
and grant interrupt service to the
external Event or Device interrupts only.
If I2 or
I3
1is
asserted,
while 16 is enabled, control is transferred to microlocation 3004 from
any microinstruction which has the RSVC bit (bit <17>) set
to
a
"1"
after
the
next subsequent microinstruction is executed (only if neither one of the microinstructions is a Jump or Return from
Subroutine
microinstruction).
The Refresh interrupt (I0) has the highest priority of all interrupts external to the micromachine.
When enabled via a
jumper on the LSI-11 processor, I0 is asserted every 1.6 milliseconds.
This interrupt is usually transparant to the
machine-level
operation
of

the

processor.

The refresh (RFRSH) operation which follows I0
has
control
transfer
links
to the WAIT (WAT) machine instruction, to the FDIN-POK sequence
and to the ODT/Halt routine.
These links exist by
means
of
special
translations which are implemented in the microprocessor Control chip.
The Trace Trap Bit (I4), the
the two external interrupts,

External Interrupt Enable
Bit
Event (IZ2) and Device (I3), are

(I5)
and
unchanged
external
Halt
the Power-Fail

from their representation in Figure 2.15.,
However, the
interrupt
shown
in
the earlier figure is shared with
function (PFHALT).
The micromachine employs a Fast Data-In
to determine which event has occured.

operation

The Trap/Interrupt priority structure is the composite result
of
the
internal
micromachine
interrupt
register
priorities, the microprogrammed Power-Up and bus error routines, and the over=-all control flow
configuration.
The combined priorities may be ordered as follows:
1.

Bus

Error

Trap

External

Memory

Machine

Hardware

Halt

Power-Fail

Trap

Event

Interrupt

Device

Interrupt

Test

(I16)

Refresh

Instruction
Trace

Traps

Trap

Line

(Bus)

Interrupt

Request

THE

LSI-11

MACHINE

STRUCTURE

2.3.3.3
Power-Up Processing - If the top
decision
in
the
Power-Up
flow
determines that no bus error occured, a Power-Up routine begins.
The first event is to issue an initialization signal
on
BINIT L
and
then
wait
for bus power to come up (BPOK H active).
If enabled, dynamic memory refresh will also occur in this sequence.
When bus power
arrives, the module jumpered Power-Up option is accessed by the micro-

processor
Power

through

modes

MODE

are

the

FDIN

listed

operation

and

performed.

The

four

below:

The

and

the

PSW

are

loaded

from

possible

locations

and 26, respectively, and machine execution
gins.
If BHALT L is asserted, control will
returned

MODE

Control

MODE

The

Console

passes

PC is
(External

ODT/Halt.

immediately

Console

bebe

ODT/Halt.

loaded

with 173000, the PSW with
Interrupts Disabled), and machine

200

execution begins.
As in
MODE 0,
the
processor
will
halt before the first instruction is executed if BHALT L is asserted.
MODE

Control

immediately goes to microlocation 3002,
control
store
entry
point
for
a
user-microprogrammed
bootstrap
routine.
The

the

status

transfer.

that

BHALT
If

microaddress,

occurs.

has

control

effect

store

trap

does

this

not

vector

control

exist

location

CHAPTER
THE

3.1

LSI-11

MICROMACHINE

STRUCTURE

GENERAL

The

LSI-11

processor

illustrated

Large-Scale-Integration

(LSI)

Figure

2.3

microprocessor

emulate

implemented

the PDP-11 architecture.
Emulation is
general
resources of the microprocessor

the

specific

the

architectual

LSI-11.

This

microprocessor which
and

which

one

components

chapter

is made

40-pin

(GP

contains

up of

MICrocode

with

the

technique

are

made

description

Only

chip,

Memory

the

where-

serve

16-bit ALU,

detailed

microprogrammed

registers,

the Control

Read

Data

(MICROM)

etc.)
the

chip,

chips.

For

the purposes of microprogramming, it is useful to view the Control
and
Data chips as a single microprocessor.
The major interconnection
path between the two chips is the MicroInstruction Bus (MIB).
In
addition
to
providing
a common bus for the micromachine instructions,
the MIB is also time-multiplexed to provide auxilliary
control
paths
between the Data, Control, and MICROM chips.

3.2

THE

MICROPROCESSOR

The complete microprocessor is illustrated in Figure 3.1.
There
are
several
similarities which may be drawn between this illustration and
Figure 2.3 (LSI-1ll Processor).
Both figures contain a
register
file

and
dent

an
arithmetic logic unit;
there is also a memory component eviin both figures.
(Figure 2.3 contains the
system
memory
while
Figure 3.1
contains the MICROMs).
However, the programs contained in
the

MICROMs

(along

with

the

translation

array)

efficiently

organize

the
resources
of the microprocessor to emulate the machine-level
chitecture shown in Figure 2.3.
An example of the differences in

two
architectures
may be seen in the register files.
All six of
general purpose registers in the LSI-1l processor are l6-bits wide
support

both

byte

and

word

addressing.

However,

the

file

ar-

the
the
and
in

the microprocessor is composed of 26 8-bit bytes which support a
combination
of direct and indirect addressing techniques.
The microprocessor register labels correspond to the six
general
purpose
registers, the stack pointer, the PC, and the five internal registers indicated in Figure 2.6.
There
ogous

chine

is
to

a master
the

control

section

processor

control

section

instructions,

whether

fetched

Figure
in

3-1

which

Figure

from MICROM

2.3.

from

roughly
All

the

anal-

microma-

WCS

THE

Microprocessor

RBA

LSI-11

Control

and

MICROMACHINE

Data

Chip

Figure

3-1

STRUCTURE

Detail

(Including

MICROM)

H/L

RSRC

H/L

RDST

H/L

RIR

H/L

RPSW

H/L

CNTL

H/L

BITS

H/L

[

[ reTURN REGISTER |

[ [orfs]ap

MIR

INC

[
MODIFY INSTRUCTION

TRAN

RET

JXX

JMP

ADR

REG

ADR

rocationcounter

MASTER

CONTROL

TRANSLATION

ARRAY

{TSR}

58/CC

MICROINSTRUCTION BUS

[trRT1][ tA RO} [ inTRY

{ DA/ADR R1| | DA/ADR RO|

MICROM

WDAL <<07:00>
P

WDAL <15:08f>—I
BUS TRANSCEIVERS AND INTERFACE LOGIC
A

LSI-11 SYSTEM BUS

[SITRTINE)

THE.LSI—ll MICROMACHINE STRUCTURE

module, are loaded into the microinstruction register for execution at
the
micromachine level.
The two Data/Address (DA/ADR) registers, the
two Translation (TR) registers and the Interrupt (INT)
register
provide
register
1interface and buffer functons between the micromachine
and the world of the LSI-1ll system bus.
To complete the analogy
with
Figure

2.3,

the

Input/output

LSI-11

devices

are

system

bus

LSI-11

the

1is

the

microprocessor

the

processor.

Figure 3.2 provides an overview
of
microprocessor
operations.
The
figure
1is
in the same format as Figure 2.4,
(Processor Control Functions).
The Compute and Reset controls and the Microlocation
Address

Generation
functions
are
discussed
1in Section 3.3.2.
The
struction Execution functions are discussed in Section 3.3.1.

3.3

MICROPROCESSOR

Microin-

PARTITIONING

Microprocessor partitioning is illustrated in Figure 3.3.
All
chips
within
the micromachine (Control, Data, MICROMs) receive a four-phase
micromachine clock from the LSI-1l1
circuitry.
The
22-bit
microinstruction
bus
provides a communication path between all micromachine

elements.
Sixteen lines of the MIB
are
common
to
all
three
<chip
types, while MIB<K16> and MIB<17> are connected only between the MICROM
chips and the Control chip.
The last four
1lines,
(MIB<21:18>)
1lead
directly
from the MICROM chips to the TTL control logic on the LSI-11
module.

The

Interface

TTL

Logic

control
shown

logic
in

Figure

composed
3.1.

The

the

Bus

operation

Transceivers
of

this

and

logic

detailed in The Microcomputer Handbook.
The signal paths and
control
functions
on
the LSI-11 system bus side of this logic were discussed
in Chapter 2.
The connections on the micromachine side are listed
in
Figure 3.4.
The

Special

CROM bits
listed in

3.3.1
The

Control

Functions

(MIB<Z21:18>)
Figure 3.5.

are

Microprocessor

Data

components

the

which

are

distributed

generated

the

two

the

major

highest

logic

MI-

areas

Chip

microprocessor

which

are

implemented

the

Data

chip
have
been
extracted
from
Figure 3.1
and
are illustrated in
Figure 3.6.
The Data chip is connected to the sixteen lowest lines of
the
Microinstruction Bus
(MIB<15:00>)
and
to the WAIT signal.
The
Data

chip

access

the

LSI-11l

System Bus

provided

WDAL<07:00>

and
WDAL <15:08>.
Microinstructions
fetched from MICROM are loaded
into the MicrolInstruction Register
(MIR) for
execution
by
the
Data
chip.
The
MIB
also provides a signal path back to the Control chip
for conditional jump instruction results.
The 16 WDAL
1lines
provide
bidirectional
access
to
the LSI-11 system bus lines, BDAL L<15:00>.
The output path of the WDAL lines is
Registers,
DA/ADR RO and DA/ADR R1l,
dress information for the LSI-11 bus

buffered by the two
Data/Address
which hold the output data or addrivers.

THE

LSI-11

MICROMACHINE

Microprocessor

Control

Figure

STRUCTURE

Functions

3-2

MICROPROCESSOR CONTROL

COMPUTE

ALWAYS ASSERTED

RESET

POWER-FAIL TRAP
BUS-ERROR TRAP

CONTROL

O
I

MICROLOCATION

MICROINSTRUCTION

ADDRESS GENERATION

EXECUTION

MICROINSTRUCTION ADDRESS

INSTRUCTION TYPES

DATA

CHIP

DATA MANIPULATION

DATA ACCESS
MICROPROGRAM CONTROL
FETCH

LOCATION

MICROMACHINE

MICROINSTRUCTION

COUNTER

INSTRUCTION

(MICROFETCH)
INCREMENTER
RETURN REGISTER
UNCONDITIONAL JUMP

ARITHMETIC LOGIC UNIT

CONDITIONAL JUMP
MACHINE INSTRUCTION

TRANSLATION REGISTER

STATUS BIT FLAGS

CONDITION CODE FLAGS
REGISTER FILE

TRANSLATION
ARRAY

+— |0—-16

8-BIT WORDS

(TSR)

TRANSLATION ADDRESS

MICROINSTRUCTION BUS CONTROL
CONTROL CHIP CONNECTIONS TO SYSTEM BUS CONTROL

MR-1034

THE

LSI-11

Microprocessor

MICROMACHINE

STRUCTURE

Inter-Chip Wiring
Figure

Detail

3-3

MIB <15:00>
4

MIB <16>

MIB <17>

MIB <21:18>

MICRO-

PROCESSOR | WAIT|
DATA
*

MICROM

PROCESSOR
CONTROL

MICROM

CHIP

0
(CONTROL

CHIP

1
(CONTROL

STORE)

WQAL

R_I'-—’H

<07:00>

1-4

To_

TTL

CONTROL

BITS

o
WDAL

<15:08>

|compuTE

wpourt| NESET

4
S

ADDITIONAL

CONTROL
STORE

WIACk

(MICROMS)

|BUSY

OR WCS)

BUS TRANSC
ANDEIV
INTERFAC
ERS
E LOGIC
4

LSI-11

SYSTEM BUS

MR-1035

THE

LSI-11

Interface

MICROMACHINE

Logic

Reference

Figure

LSI-11 BUS DRIVER/
RECEIVER INTERFACE
DATA CHIP

STRUCTURE

Chart

3-4

BUS I/O CONTROL
SIGNAL LOGIC

INTERRUPT CONTROL
AND RESET LOGIC

SPECIAL CONTROL
FUNCTIONS

CONTROL CHIP

MICROM

WDAL <07:00> (INPUT/OUTPUT)

WSYNC

(OUTPUT)

WDAL <15:08> (INPUT/OUTPUT)

WDIN

(QUTPUT)

WDOUT

(OUTPUT)

WwB

(OUTPUT)

REPLY
BUSY

(INPUT)
(INPUT)

RESET

(INPUT)

WIACK

(OUTPUT)

10
1

RFIRQ
IPIRQ

(INPUT)
(INPUT)

EVIRQ

(INPUT)

10IRQ

(INPUT)

MIB <21:18> (OUTPUT)

1036

THE

Special

LSI-11

Control

MICROMACHINE

Function
Figure

STRUCTURE

Distribution

Chart

3-5

BUS I/0 CONTROL

INTERRUPT CONTROL.

SIGNAL LOGIC

AND RESET LOGIC

INIT

(1)

IFCLR AND SRUN L

INIT

(1)

TFCLR L

RFSET L

INITIALIZE SET
FAST DIN
PFCLR L

EFCLR L
MR-1037

THE

LSI-11

MICROMACHINE

Microprocessor

Data

Figure

RBA

H/L

RSRC

H/L

RDST

H/L

RIR

H/L

RPSW

H/L

Chip

Detail

3-6

—

—
G

H/L

STRUCTURE

e
G}

MIR

|B|A

—

SB/CC

MICROINSTRUCTION BUS

ALU

| pa/aDR R1| [DA/ADR RO|
-

WDAL <07:00>

WDAL <15:08;I
MR-1038

THE

The

major

the

Microinstruction

Arithmetic

Status

3.3.1.1
ered

elements

LSI-1l

File

the

Data

chip

are

chip

STRUCTURE

are:

Addressing

Unit

Bit/Condition

Microinstruction

Data

and

Logic

MICROMACHINE

Code

Flag

Micromachine

into

the

MIR

instructions
delivexecution.
The por-

for

tion of the MIR contained in the Data chip is only 16 bits
wide,
flecting
the fact that only Microlnstruction
Bus lines MIB<15:00>

connected

opcode

The

to the Data chip.
There
formats, as listed below:

Jump Format

Conditional

Literal

Jump

bits

Format

<15:12>

are

four

types
'

reare

microinstruction

Jump Format

Format
Format

and

illustrated

the

jump

Figure

3.7.

The

opcode

(0)

occupies

address is contained in bits <10:00>.
Microinstruction can transfer micromachine control to any of the
microlocations addressable within the control store.

A JMP
2048

The second of the two possible Jump format
by bit <11> of the microinstruction.
When

instructions is
determined
bit <11> is a 1, the microinstruction executes a Return From Subroutine
(RFS)
operation.
The
LSI-11 microprocessor supports only one level of subroutine at
the mi-

croprogramming

level.

The .Conditional

Jump

jump

Format

microinstruction

<15:12>)

(0001).

The

which

shown

indicated

Figqure

when

condition

the

field,

3.8.

opcode

bits

conditional

field

<11:8>,

(bits

1indicate

condition
must
be
satisfied for the jump to take place.
The
condition tests the ALU status bit and condition code
flags as well as
an
Indirect
Condition Status bit.
1If jump conditions are satisfied,
micromachine control is transferred to the microloc
ation contained
in
the
8-bit address field.
Since only 8 bits are available for address
information, control may be transferred within the
current
256
location page only.
The remaining 3 address bits are equal to the corresponding 3 bits of the
(updated) value of the current location counter.
The

Literal

Format

microinstructions,

illustrated

Figure

vide
a
way to generate constants in a microprogram.
the 8-bit literal field MI<K11:4> are determined at the

program

assembly

instruction.
and

determines

port)

The

and

may

not

remaining

which

will

changed

field,

microprocessor

the

other

bits

the

<3:0>,

8-bit

execution

the

called

(accessed

argument

for

the

3.9,

pro-

The contents of
time of
microany

micro-

"A"

through

field

the

"A"

nmicroinstruc-

THE

LSI-11

MICROMACHINE

Unconditional
Figure

3-7

]

JUMP ADDRESS

1/0

Jump Format

STRUCTURE

MR-1039

THE

LSI~1l1

MICROMACHINE

Conditional

Jump

Figure

]

STRUCTURE

Format

3-8

__1

]

CONDITION
L

JUMP ADDRESS
|

i
MR-1086

THE

LSI-11

MICROMACHINE

Literal

Format

Figure

OP CODE
|

STRUCTURE

3-9

]

00
)

LITERAL FIELD

A REGISTER
1

|
MR-1040

THE

The

Format

LSI-11

microinstructions,

contain
a
second
register
field.
Note that the B port
Read

Only

format
case

cles

byte

cycle

operands
A word

The

second micromachine
are supplied by the

plied by
bit
and
eration.
A

and

the

second

complementing

the

3.3.1.2

port

byte

Read/Write

word

microinstruction

are

determined

operation

Figure

pair

lowest

bytes

bit

executes

the

port.

3.10,

instructions.
in

one

1In

the

micro-

the

requires

contents of the A
two micromachine cy-

word

cycle.
Thus the low bytes
contents of Ra (or Rb) and

fields

File

(see

and

file

vide

Section

Indirect
is

operand

field

deter-

during

the

of a
word
1instruction
the high bytes are sup-

These

without

and

system

The

contents
indirectly.
group

bus

cycles

3.3.1.2).

Addressing

composed

temporary storage of
micromachine
programs.

ther

illustrated

the contents of Ra + or = 1 (or Rb + or - 1).
The ALU status
condition code flags reflect the result of a word or byte opDirect and indirect register addressing is supported by both

processor

second

either

fields.

execute.

STRUCTURE

designator field (MI<7:4>) called the "B"
on the microprocessor register file is
a

the

are

operation,

and

mined

whereas

microinstructions

machine
and

port,

MICROMACHINE

data

and

8-bit

The

registers

micro-

which

pro-

address
registers

are,

information for machine
or
supply operands to the ALU
therefore, accessed at high speed.

the register file may
One
group of registers

only

be accessed either
directly
or
may be accessed only directly, a

indirectly, and a third group may be accessed in
illustrated in Figure 3.11.
This illustration uses
that directly addressed registers are preceded by
"R"

way,

convention
indirectly
addressed registers are preceded
indicates the machine- or micromachine-level

by "G".
Figure 3.11
use of each register.

ei-

the
and
also

The three highest bits of either the A and B register fields determine
whether
direct
or
indirect
addressing is in effect for that field.
When the three highest bits are all zero, indirect mode
is
indicated
and
the 3-bit G register contributes its three bits to the final, indirect register address.
Since the lowest bit in each
field
may
be
either a 1 or a 0, indirect word addressing is achieved by complementing ‘the lowest bit during the second cycle of a two-cycle word
microinstruction.
Figure 3.12 illustrates indirect addressing as used with
a Literal microinstruction.
It should be noted that all Literal
format
microinstructions
are
single-cycle
and that since the register
field is in the A position, register access is
obtained
through
the
Read/Write register file port.

Indirect addressing with
trated
1in Figure 3.13.
the

and

used

rect

modes.

the

structions

field

a Register Format microinstruction is
illusThe G register contents are the same for both
indirect addresses.
The register
addressing
modes

Format

Additional

are

supplied

may

specific

any

combination

details

Chapter

direct
Format

and

indi-

microin-

THE

LSI-11 MICROMACHINE

Figure

09
)

OP CODE
)

]

STRUCTURE

Format

3-10

04
T

1/0

]

B REGISTER
|

A REGISTER
I

|
MR 1041

THE

Direct

LSI-]l1l

and

MICROMACHINE

Indirect

STRUCTURE

Figure

Addressing

3-11

HIGH BYTE

LOW BYTE

]
PDP-11 RO

|
[

PDP-11 R1

|
|
PDP-11
R2

|
I
INDIRECTLY

ADDRESSABLE

PDP-11
R3

|
|

PDP-11
R4

|
I
PDP-11 R5

|
17

PDP-11 SP

[
15

PDP-11 PC

|
I
13

RPSW H

RPSW
L

i
11

RIR H

RIR
L

]
7

RDST H

DIRECTLY
ADDRESSABLE

RDST
L

i
5

RSRC H

RSRC
L

|
3

1 |

RBA H

RBA
L

HIGH BYTE OF

TOBYG ——

LOWBYTE OF

1042

THE

LSI-11

MICROMACHINE

Indirect Register Addressing-Literal
Figure

STRUCTURE

Instruction Format

3-12

A REGISTER

FIELD

LITERAL FORMAT
|

OP CODE FIELD

LITERAL FIELD
1

0
~—

1/0

—

INDIRECT:

VIA
G REG

170
\

1/0

170

G REGISTER CONTENTS ——| 1/0

1/0

]

170

]

1/0

]
—

FINAL INDIRECT
A REGISTER
ADDRESS
MR-1043

THE

Indirect

LSI-11

MICROMACHINE

STRUCTURE

Addressing-Register
Figure

Instruction

Format

3-13
A REGISTER

B REGISTER

FIELD
15

OP CODE FIELD
L

G REGISTER CONTENTS
(BOTH SAME)

1/0

1
J

1/0

1§

FIELD

[

]

INDIRECT:

INDIRECT:
VIA
G REG

{

1/0

1/0 |

1/0

1/0
|

1/0

—

VIA
G REG

]

1/0
|

1/0

—

FINAL I‘I\EDIRECT

1/0
]

1/0
1

FINAL INDIRECT

B-PORT REGISTER

A-PORT REGISTER

ADDRESS

ADDRESS
MR-1044

THE

LSI-11

MICROMACHINE

STRUCTURE

Data may be written into specified register locations only through the
A
port.
There
are
four
possible data sources which lead to the A
port, listed as follows:

ALU

Output

The output
file.

ALU

Status

Bit

The

result

the

ALU

and Condition
ALU

WDAL

<07:00>

WDAL

<15:08>

Code

operations

status bit and condition
a specified register.
3)

returned

code

the

Flags
monitored

flags

may

the

stored

Since the Write access to the register file is
only
8
bits
wide,
an
operation which loads a complete
word (low and high byte) from the LSI-11 system
bus
must require at least two micromachine cycles.
The Indirect or
4-bit
1indirect

supplies
address.

the 3 highest bits
The G register is

of
the
final
loaded only via

the Load G Low (LGL) or Input Word (IW)
microinstructions
which
are
described
1in the next chapter.
Note that there is no mechanism which
increments, decrements, or clears the G register contents.

3.3.1.3
Arithmetic Logic Unit - The microprocessor Data chip ALU
accepts
an
8-bit
operand
from both the A and B ports of the register
file.
Both register ports operate in Read mode to supply the operands
and
the ALU result can be stored in a register through the A port (in
the Write mode).
The ALU performs extensive
1logical
and
arithmetic
operations.
Arithmetic operations executed at the micromachine level
may use two's complement or Binary Coded Decimal (BCD)
number
representation.
Byte
operations
are
executed
1in a single micromachine
cycle while word operations require two cycles.

3.3.1.4

Status Bits

and Condition Code

Flags

- The

results

erations
are
monitored
by the status bits and condition code
These flags are organized in a register format and are
updated

each ALU operation.

ALU

op-

flags.
after

Figure 3.14 illustrates the flag register organi-

zation.
The condition code flags,
which
are
also
the
LSI-11
PSW
Flags,
are
updated
selectively.
A Register Format microinstruction
will leave the condition code flags unmodified if the
opcode
1is
an
even
number,
whereas
an odd opcode microinstruction will update the
flags.
This feature is useful in performing intermediate data manipulations
which
do
not affect the PDP-11 condition code flag results.
The ALU status
bit
flags
are
updated
after
Appendix
A lists which Condition Code Flags are
croinstruction.

each
ALU
operation.
affected for each mi-

THE

Arithmetic

Logic

LSI-11

Unit

MICROMACHINE

Status

Bit

Figure

and

STRUCTURE

Condition

Code

Flag

3-14

ALU

STATUS BIT

CONDITION CODE

FLAGS

FLAGS
MR-1045

THE

The

operating

CONDITION

rules

CODE

LSI-11

for

the

MICROMACHINE

condition

STRUCTURE

code

flags

are

result

1listed

below:

FLAGS

This

flag

operation
wise.
N

This

flag

the

result

This

flag

and

carry

word

zero.

This

the

byte

cleared

flag

most

Increment

the

operation.
and

byte

cleared

operation

word

other-

bit

"1".

otherwise.

This

most

significant

word

monitors bits which
shifted as follows:

from

Subtract

the

set

This flag
rowed, or
Add

set

1is

are

flag

significant

This

flag

Decrement

This

carried,

set

bit

bor-

there

byte

cleared

otherwise.

flag

set

there

is
a
borrow
(complement of carry) from the most
significant bit of a byte
or
a
word
operation.
This flag is cleared otherwise.
Shift - This flag is set if the result of a
right
or
left shift operation causes a "1" to shift off
the end of the byte or word.
This flag is cleared
otherwise.

Note

that

tions

This

flag

the

flag

areas

is set

affected

listed

if an

only

arithmetic

ALU

status

and

are

used

example,

during

bit

the

flags

are

updated

microprocessor

a word

after

operation).

each

perform

They

are

opera-

operation

sults
1in an overflow.
This flag is
overflow occurs or if the operation
not an arithmetic operation.
The

for

above.

8-bit

carries

updated

ALU

and

only

This flag
operation

is
is

This

flag

the

result

This

flag

cleared

SRWC)
.

set if the
"0".
This
set

if
a

the

byte

no
is

operation

borrows

for

(for

arith-

metic,
shift,
test
and compare microinstructions.
Appendix A
which status bit flags are affected for
each
microinstruction.
operating rules for the status bit flags are listed below:
ZB

re-

cleared if
performed

lists
The

result of a byte or a word
flag is cleared otherwise.
most
or

significant
word

otherwise

operation

(except

for

bit
is

SRW

of
a

and

THE

LSI~11

MICROMACHINE

This flag is used only
decimal arithmetic.
It
third bit to the fourth
is cleared otherwise.

This

STRUCTURE

for
operations
involving
is set if a carry from the
bit is a "1".
This
flag

flag is
set
1if
the
carry
from
the
most
signficant
bit
1is
a
"1"
or if the result of a
shift operation is to shift off a "1".
This
flag
is
cleared
otherwise.
Note that this status bit
1s not set to borrow for subtract as in
the
case
with the C Condition Code Flag.

Each of the status bit and condition code flags shown
in
Figure 3.14
may
be
tested
by
a conditional jump instruction, except for the C4
status bit.
In place of this bit, there is a
test
of
the
Indirect

Condition
Status (ICS) bit which is used to determine specific microprogram-level jump conditions.
The jump on ICS microinstructions
are
used
to
directly
implement the LSI-1l1l machine-level Branch instructions.
The 16 Conditional Jump
microinstructions
and
the
Indirect
Conditon Status rules are given in the next chapter.
The

Status Bit/Condition Code flag register contents
may
be
written
into a register using the Copy Condition Flags (CCF) microinstruction.
Conversely, the 8-bit contents of a specified register may
be
1loaded

into

the

tion.

1In

flag
the

the

case,

Load

the

Condition

flags

which

Flags

are

controllable.

3.3.2

Microprocessor

Control

(LCF)

loaded

are

microinstrucindividually

Chip

The microprocessor Control chip
functions
primarily
in
two
areas:
(1) it
controls
the
flow
of
micromachine
instructions
which are
fetched from control store (MICROM) and delivered to the Data chip for
execution
and (2) it administrates all LSI-1ll system bus transactions
by means of its connection to the Bus Transceivers and Interface Logic
shown
in
Figure 3.15.
It should be emphasized that Figure 3.15 is a
functionally accurate Control chip representation, but that the actual
Control
<chip
circuitry is somewhat different.
The difference arises
because the data/address line inputs (WDAL <07:00> and
WDAL
<15:08>)
which
lead
to the translation registers (TR RO and TR R1l) do not appear on the Control chip.
The

1l6-line

path

between

the

WDAL

lines

the

Data

chip

and

the

two

translation
registers
on
the
Control
chip
1is
established
by
time-multiplexing the MicrolInstruction Bus.
The primary
function
of
the
MIB
1is
to deliver control store addresses to the MICROMS
(or to
the WCS module) and to retrieve the selected microinstruction for execution.
When
the
MIB is not occupied with its primary function, it
provides the 1l6-line path to the translation registers.
This path
is
established
during
the the execution of the Input Word microinstruction which is part of the Fetch
Machine
1Instruction
operation
discussed
in
the
previous chapter.
The fetched machine instruction is
loaded into the translation register
(s) for examination by the
translation array.

THE

LSI-11

MICROMACHINE

Microprocessor

Control

Figure

STRUCTURE

Chip Detail

3-15

» CONTROL
|

[RETURN REGISTER]

MP | Loc
-

]

TRAN

RET

JXX

Jmp

ATR

REG

ADR

M IR

LOCATION COUNTER

!
L

(MODIFY INSTRUCTION)

TRANSLATION
ARRAY

MASTER

CONTROL

(TSR)

MICROINSTRUCTION BUS

[ —

[TRR1
]| TR RO| [ INT R]
WDAL

WDAL

<15:08> | <07:00>

MR 1046

THE

LSI-11

MICROMACHINE

STRUCTURE

3.3.2.1

Microinstruction
Register - The
microinstruction
register
the Control chip detail of Figure 3.15 contains 18 bits.
The
additional 2 bits (not found in the Data chip microinstruction
register)
correspond to the LRR (Load Return Register) and RSVC
(Read Next

shown

Instruction

Figure

shown

iginates
(bit<1l6>)

at
is

Interrupts

3.15,

Trap

the

the
Location
set it causes a

Service)

path

function.

leading

Counter
value of

into

the

Return

incrementer.
When
LC + 1 (the updated

the
LC)

LRR
to

or-

bit
be

loaded
into
the
Return
Register.
This bit is part of the microinstruction at microprogram assembly time.
The return register is loaded
1in
preparation
for
the
execution of a microprogram subroutine.
Subroutine execution is terminated by the Return From Subroutine (RFS)
microinstruction.

Bit <17> of the microinstruction register is a
direct
input
to
the
translation
array.
The RSVC bit is assembled into the microinstruction sequence one location before the translation is
to
be
invoked.
This
translation causes machine-micromachine control to enter the top
of the interrupt/trap decision chain
shown
in
Figure 2.16-2,
which
will
cause all traps and interrupts to be serviced according to their

priorities.
terrupts,

which

tion

the

control

flow

does

the

proceeds

not

encounter

Fetch

any

Machine

traps

Instruction

causes the next machine instruction to be read into
registers for examination by the translation array.

the

in-

event,

transla-

3.3.2.2
Microinstruction
Address
struction
address produced by the

tion

Counter.

The

Generation - Each
valid
microinControl chip is stored in the LocaCounter contents are gated onto the Micro-

Location

Instruction Bus
at the appropriate phase of
the first part of the microinstruction fetch

tion
Counter
may
described below:

Incrementer

loaded

from

any

A value
Counter

tion

one

Array

The

Counter.

store

possible

The

Translation

inputs,

five

of
1
1is
added
to
output
and written

next
fetched

is,
therefore,
guential control
Translation

the micromachine cycle as
(microfetch).
The
Loca-

store

from

which

the

Location

into

the

Loca-

microinstruction
from the next se-

location.

Array,

determines

sources,

response

location

1its

control

microinstruction

is
to be fetched.
The address of this location (shown as TRA ADR)
1is
1loaded
1into
the Location Counter.
Return

Upon

execution

tine
Return

tion
Conditional

Jump

Field

the

Return

microinstruction,
Register

are

the

loaded

From

contents
into

the

Subrou-

the

Loca-

Counter.

When the conditional jump criteria is
met,
the
8-bit contents of the conditional jump
field are loaded into the lowest 8 bits
of
the
bits

Location
Counter.
are unchanged from

The

the

three

highest

updated

values.

THE

Unconditional

Jump

LSI-11

Field

MICROMACHINE

Upon
the
jump

STRUCTURE

execution of the JMP
microinstruction
1ll-bit
contents
of the unconditional
field are
loaded
1into
the
Location

Counter.

A microlocation address may be determined in one
additional
way,
by
the
execution
of
the Modify Instruction (MI) microinstruction.
The
Modify Instruction path which is labeled in
Figqure 3.15
enables
the
contents of a specified register pair to be ORed with the Unconditional Jump microinstruction (or any other microinstruction) on the MicroInstruction
Bus.
This
microinstruction
1is
discussed
in the next
chapter.
The translation array is a large combinatinal logic network which performs
rapid
examination
of
the
fetched machine instruction in the
Translation Register to determine where microprogram execution
1is
to
begin.
sult is

The examination is completed
translation
address
which

Counter.
The
translation
machine instruction at one

in one machine cycle and the re1is
1loaded
into
the
Location

array can examine only

bits

16-bit

time.
The
translation
state
register,
which
1is
shown
as (TSR) in Figure 3.15, determines which of the two
translation registers (TR RO or TR R1l) is
input
to
the
translation
array.

When
a
new machine instruction is fetched, the TSR is reset
and causes the upper byte of the instruction, which
1is
contained
1in
TR Rl
to
be examined first.
This allows the LSI-11 machine instruc-

tion
The

type to be determined before the the address modes are
examined.
TSR contains 3 bits, one of which controls the translation regis-

ter

input, while the
translation array.

other

two

are

used

for

purposes

internal

The

interrupt register, INT R, is composed of
3
internal
and
4
external
interrupts
which
were
illustrated
Figure 2.17.
The external interrupts are connected to the

the

interrupts
earlier
1in
LSI-1l1l sys-

tem
bus
interface
1logic.
The
3 internal interrupts may be set or
cleared by the Set Interrupt (SI) or the Reset Interrupt
(RI) microinstruction, respectively.
When the translation array initiates service
for a pending external interrupt, an early step in the service
microprogram
1is
to
reset
the interface logic flip-flop which had stored
that external interrupt request.
The flip-flop reset
pulse
1is
produced by the TTL Control Bits as decoded by the Special Function Logic
(Figure 3.5).
Figure 3.16 illustrates the Microprocessor TTL
Control
Bit
Path
as
extracted from Figure 3.1.
Figure 3.2 reveals that the
TTL

Control

Bits

not

actually

appear

the

MicroInstruction

Regis-

ter of either the Data chip or the Control chip.
However, Figure 3.15
emphasizes the association of the TTL Control bits with
the
microinstructions.
These bits must be assembled at the correct positions in
the microinstruction flow to
assure
proper
microprogram
execution.
The
exact
details of timing and sequencing are discussed in the following

3.3.2.3

sections.

Control

Signals

addition

the

external

interrupts,

eight
other signals pass between the Control chip and the LSI-11l processor interface logic.
The operation of these signals are
explained
below
and additional specific details are available in the references
cited in Figure 3.4.

THE

LSI-11

MICROMACHINE

Microprocessor

TTL

Figure

Control

STRUCTURE

Bit

Path

3-16

TTL
CNTR
BITS

(l
MICROINSTRUCTION BUS

MICROM

MR-1047

THE

The

RESET

line

microprocessor

LSI-11

input

operation

quently

MICROMACHINE

the

Control

STRUCTURE

chip

suspended.

and

When

when

the

active,

RESET

causes

input

subse-

goes passive, the first microinstruction to be
executed
will
be
fetched
from
control store location 000l1.
The RESET line is asserted whenever the power supply signal BDCOK H goes passive or when a

bus

timeout
error occurs.
The microprogram executed
goes passive is flow-charted in Figure 2.16-2.

line

The

COMPUTE

signal

sampled

during

This
1line
is
maintained in an
manufacturing for test purposes.

The remaining signals are concerned
tration
of
the
three
types
of
Programmed

I/0,

Interrupt-Driven

interfaced
to
Logic described

The
the

active

the

high

after

the

micromachine

state,

and

RESET

cycle.

used

during

with the control
chip's
adminisLSI-11
system
bus I/O transfers.

I/0,

and

DMA

I/0.

the
LSI-11
bus
system by the
in The Microcomputer Handbook.

These

Bus

I/0

signals

Control

are

Signal

transition of the SYNC signal to its active state
indicates
that
address
data
on WDAL <15:00> is valid.
The sync signal remains

asserted

until

the

I/O

transfer

completed.

Additional

1interface

circuitry assures that the corresponding system bus signal
mains active until after the bus slave
device
terminates
signal.

BSYNC
1its

The

device

signal

originates

the

addressed

memory

I/0

L rereply

and

informs
the
Control chip that the I/0O operation should be continued.
Specifically, this signal must be asserted during PH 3 of the micromachine cycle while an Input or an Output microinstruction is being exe-

cuted.
The state of the reply signal
Read or Write operation is initiated.
ously-addressed device has completely

is also
This is

interrogated
before
a
to assure that a previthe system bus.

released

The DIN (Data-In) signal is asserted by the Control chip after the address
information
1is
removed from WDAL <15:00>, or one micromachine
cycle after the SYNC signal is asserted.
The DIN
signal
returns
to
the
passive
state
at the completion of the Input Byte (IB) or Input
Word
(IW) microinstruction, or when SYNC is made passive.
This signal
causes the addressed device to place its data on BDAL<15:00> for input

The

the

processor.

DOUT

data
until
The

WB
placed

signal

remains

BUSY

asserted

active

during

the

Data-Out

signified.

signal

sampled

ing
the first cycle of
signal is asserted, the
pends

the

Control

placed on WDAL <15:00> by the Data chip
Output microinstruction is completed.

(Write/Byte) signal is asserted when the
on WDAL <15:00> to indicate that a Write

(DATOB)

The

(Data-Out)

1is
the

during

chip

when

remains

output

asserted

address information
operation follows.

portion,

the

and

Byte

micromachine

operation

cycle

a Read or Write microinstruction.
If the
microprocessor enters a wait
state
and

operation
until
BUSY goes
the direct memory access interface
LSI-11 bus can gain control of the

passive.

This

logic,

system

bus.

mechanism

I/O

is
1If

device

dur-

BUSY

susused by

the

THE

The

Interrupt

chip

along

nowledge

LSI-11

Acknowledge

with

the

MICROMACHINE

(WIAK)

SYNC

microinstruction

line

STRUCTURE

signal

when

Read

executed.

asserted

The

Acknowledge
WIAK

signal

the

Control

Write

Ack-

indicates

that

the
microprocessor
is responding to an interrupt.
The LSI-11 interface logic delays the appearance of WIAK as BIACK H
until
BDIN L
is
asserted.
This is to allow the BDIN L signal to stabilize priorities

between the two possible
Microcomputer Handbook).

3.4

MICROMACHINE

requests

the

interrupting

device

(see

The

OPERATION

All

micromachine operations are
micromachine clock.
Each phase

controlled by
has a nominal

the four-phases
of
the
period of 95 nanoseconds

giving a cycle period of 380 nanoseconds.
The clock phases
are
distributed
to the Control, Data, and MICROM chips of the microprocessor
as MOS-level non-overlapping pulses (RPH <4:1>).
True and
complement
TTL

clock

terface

phase

Logic

pulses

are

circuitry

distributed

for

the

synchronization

Bus

with

Transcievers

the

and

In-

micromachine.

Micromachine operating speed is maximized by
the
wuse
of
pipelining
techniques to determine microlocation addresses and to access microinstructions for execution.
The pipeline techniques are implemented
1in
the
context of a time-multiplexed MicrolInstruction Bus, which reduces
inter-chip wiring.

3.4.1

Microinstruction

Bus

Data

Transfer

The

data transfer method employed on the
microinstruction
bus
is
a
precharge-conditional discharge technique which is compatible with LSI
MOS memory and microprocessor devices.
Data is transmitted on the microinstruction
bus
1in logical complement form (the lower voltage represents a Logical 1).
Each microinstruction bus line is unconditionally
precharged
high
at
one
phase and selectively discharged at a
later phase.
The receiving device senses the discharged state
during
the appropriate phase and interprets the lower voltage as a logical 1.
All precharging is performed by the MICROMs.
The receiving device may
be the Control chip, the Data chip, or a MICROM.
In the case of a microinstruction fetch, the Control and Data chips receive the
microin-

struction simultaneously, each
microinstruction register.

3.4.1.1
CROM

Control

operations

Store
as

(MICROM)
function

chip

storing

the

needed

Microinstruction
of

micromachine

portions

Bus

Cycle

clock

phases

The

are

its

MI-

illus-

trated in Figure 3.17.
The Location Counter contents are
gated
onto
the
microinstruction
bus
by the Control Chip during PH 2 and remain
valid during PH 3.
All microinstruction bus lines are
then
unconditionally
precharged
at
PH 4
(by the MICROMs) with the exception of
MIB <15>, which is precharged at PH 3.
mIB <16> was
also
precharged

addition

being

precharged

THE

LSI-11

MICROMACHINE

STRUCTURE

MICROM Access Microinstruction Bus
Figure

Cycle

3-17

ONE
MICRO

CYCLE
PHASE 1

PHASE 2

PHASE 3

PHASE 4
MIB <14:00>
MIB <21:17>
PRECHARGE

‘MIB <15>

/7 N\

PRECHARGE

MIB <16>

VRN

PRECHARGE
MIB <10:00>

MICROLOCATION

INPUT

/ADDRESS
RESN

/" ADDRESS \

MIB <17:00>
MICROM

DATA OUTPUT V'

DATA

MIB <21:18>

TTL CONTROL
BIT OUTPUT

DATA

MR-1048

THE

LSI-11

MICROMACHINE

STRUCTURE

During the execution of a microinstruction which requires only one micromachine
cycle,
the contents of the microlocation addressed during
PH 2 and PH 3 are returned to the Data and Control chips
during
PH 1
of
the
following
micromachine
cycle.
However, if the control chip

discharges MIB 16 at PH 3, the selected MICROM will not
conditionally
discharge MIB <15:00> and MIB <21:18> during the following PH 1.
This
circumstance occurs during the second cycle of
a
two-cycle
microinstruction,
or
1in
response to a WAIT state.
Figure 3.18 illustrates
the disabling of the MICROM during the first
cycle,
resulting
1in
a
delay of one micromachine cycle.
As shown in the Figures, the
PH 1
throughout
PH 3.,
The
Control Bits during PH 3.

3.4.1.2

Control

Chip

TTL Control Bits are valid beginning with
LSI-11 external circuitry latches the TTL

Microinstruction

Bus

Cycle

The

Control

chip

determines
the
micromachine
instruction flow by selectively loading
the Location Counter.
The basic micromachine cycle
of
Control
chip
operations
1is
shown
in Figure 3.19.
The Location Counter is loaded
with a new value during PH 1.
This value can originate from
1
of
5
sources as discussed in Section 3.3.2.2.
The contents of the Location
Counter are output onto the microinstructin bus at
the
beginning
of
PH 2 and remain valid through PH 3.
Also during these two phases, the
translation array is processing its inputs to see if a translation
|is
required.
During
PH 4 the translation address becomes ready to load
into the Location Counter and the translation state
register
may
be
loaded.

An example of Control chip operation effected by
the
WAIT
state
is
shown
in
Figure 3.20.
Events
proceed normally until PH 3 when the
Control chip determines a WAIT state.
This determination is
the
result
of
sampling
the BUSY and REPLY lines during PH 3.
The Control
chip response to the WAIT state is to discharge MIB<16> during PH 3 to
disable
the MICROMs response and to assert the WAIT line during PH 4,
which prevents the Data chip
from
loading
a
new
microinstruction.
Because
of
the
WAIT
state,
the Location Counter value remains unchanged during the second micromachine cycle and the translation array
processing produces the same output which may be a conditional loading
of the translation state register or a translation address.
Since the
WAIT

state

was

not

re-established

during

the

second

cycle, a new Location Counter value will be loaded during
ing
PH 1 and a new microinstruction will be fetched from

micromachine

the
the

followselected

MICROM.

The execution of a
sequence
similar

and the
tions,
PH

Data chip
the
WAIT

two-cycle microinstruction produces a Control
to the above.
However, since both the Control

chip
chip

independently recognize two-cycle
machine
1instrucsignal
1is unneccessary and therefore unasserted at

THE

MICROM

Access

LSI-11

MICROMACHINE

Microinstruction

Figure

Bus

STRUCTURE

Cycle

(Disabled)

3-18

ONE
MICRO

CYCLE
PHASE 1

PHASE 2

PHASE 3

PHASE 4

MIB <14:00>
MIB <21:17>
PRECHARGE

MIB <15>
PRECHARGE

MIB <16>

PRECHARGE
MIB <10:0>

MICROLOCATION
INPUT

-/ ADDRESS

/ ADDRESS N

MiB <17:0>
MICROM

DATA OUTPUT /'

DATA

MIB <21:18>
TTL CONTROL
BIT OUTPUT

DATA

MIB <16>
MICROM

DIABLE INPUT

MR-1049

THE

Control

Chip

LSI-11

MICROMACHINE

Single-Cycle

STRUCTURE

Microinstruction

Figure

Bus

Cycle

3-19

ONE
MICRO
CYCLE

PHASE 1}/

PHASE 2

PHASE 3

PHASE 4
UPDATE
LOCATION |

COUNTER

LOCATION
COUNTER

TO MIB <10:0>

NEW LOCATION

COUNTER VALUE
READY

1050

THE

LSI-11

Control

MICROMACHINE

STRUCTURE

Chip Wait Response
Figure

3-20

ONE
-

MICRO

CYCLE

PHASE 1

PHASE 2

PHASE 3

PHASE 4
UPDATE
LOCATION

COUNTER

LOCATION

COUNTER

TO MIB <10:0>

WAIT

SIGNAL TO

DATA CHIP
MIB <16>
MICROM

/__\

DISABLE
NEW LOCATION

COUNTER VALUE

READY

yd
MR-1051

THE

LSI-11l

MICROMACHINE

STRUCTURE

3.4.1.3
Data Chip
Microinstruction
Bus
Cycle - The
microprocessor
Data
chip is completely controlled by the microinstruction in its microinstruction register and by the WAIT line which originates
in
the
Control
chip.
The basic micromachine single-cycle sequence is shown
in Figure 3.21.
During PH 1 the microinstruction contents
placed
on
MIB<15:00>

instruction
the
the

the selected MICROM are loaded into the Data chip microregister.
The register fields are
decoded
during
PH 2,

selected registers are accessed during PH
operands input to it during PH 4.
The ALU

the
and
ing

When
Data

file

code

via

the

flags

which

and

the

result
next PH 1.

monitor

the

ALU

port

result

ALU

processes

is written
The status

1into
bits

are

dur-

updated

two-cycle Data Manipulation microinstruction is
executed,
chip
retains
its microinstruction register contents during

the
the

second cycle as shown in Figure 3.22.
The low bit
of
each
register
field is complemented during PH 1 of the second cycle which allows the
second cycle of a word microinstruction to be processed in the ALU.
All

Jump

microinstructions

tion

because

value

until

the
PH

Conditional

Location

Jump

the

require

Counter

second

two

micromachine

contents

cannot

cycles

for

loaded with

execu-

new

cycle.

microinstruction

examines

the

flags

which

have

set-

tled
during PH 2 and sends the result to the Control chip via MIB<15>
during PH 4.
If the result is true, the 8-bit address will be
1loaded
into Location Counter bits <7:0> during the following PH 1.
Normal operation of the Data
serts the WAIT signal during

chip
PH 4

is
of

suspended if the
any micromachine

Control
cycle.

chip

as-

3.4.1.4
Complete Micromachine Cycle - The inter-relationship
between
the
«cycles
of
the
Control, Data and MICROM chips is illustrated in
Figure 3.23 for the case of a single-cycle microinstruction.
The
op-

eration
events

sequences

listed
the

for

execution

each

chip

single

are

repetitive,

but

microinstruction

only
are

the

shown

in
the
figure.
The complete sequence begins with a new value being
loaded into the Location Counter during PH 1 of the first micromachine
cycle and ends when the status bit and condition code flags are updated during PH 2 of the third micromachine cycle.
An accurate representation
of micromachine operations can be constructed by combining the
individual chip operation sequences
discussed
previously.
The
sequences

chosen

depend

upon

the

ed.
The

Execution

the

Input

microinstruction

flow

being

represent-

Word

microinstruction changes the
function
bus during its second cycle.
Since PH 1 of
used to update the
microinstrucion
registers

microinstruction

the second cycle is not
with
new
contents, the Data chip uses MIB<15:00> to send the fetched
LSI-11 machine instruction to the translation register
(for subsequent
examination
by the transalaion array).
This is necessary because the
Control chip has no direct connection to the WDAL lines.

THE

LSI-11

MICROMACHINE

STRUCTURE

Complete

Micromachine

Cycle

Figure

3-23

ONE

PHASE 1

ONE

MICRO

CYCLE

PHASE 2 —____/—\
PHASE 3

N\,

PHASE 4

CONTROL CHIP
UPDATES

LOCATION

COUNTER

LOCATION
COUNTER

TO MIB <10:0>> ____/__\

/_\

LOAD MIR
ON DATA AND

CONTROL CHIPS

DECODE
REGISTER

ADDRESSES __/1

/TN

ACCESS
REGISTER

)

DATA

ALY
PROCESSING

ALU

QUTPUT TO

UPDATE

FLAGS

__—/_—\

\
MR 1054

THE

LSI-11

MICROINSTRUCTION

SET

No special register addressing techniques are needed in such cases and
the microinstruction can complete execution in a minimum of one micro-

cycle.

4.2.4.2

Word

Operand

fields, MI<K7:4>
bit operands:
All

word

Formation

and MI<3:0>,

operations

other

are

than

The

microinstruction

interpreted

right

shown

Field

(A)

Even

Normal

Field

(A)

0dd

Bytes

Field

(B)

Even

Normal

Field

(B)

0dd

Sign

shift word

Use

operations:
-

(A)

0dd

Normal

Field

(A)

Even

Not

Field

(B)

0dd

Normal

Field

(B)

Even

Not

Extension

Field

Use:

form

Reversed

A Register

Normal

shifts:

A Register

Right

below

and

Field

argument

Use

Recommended

Use

Recommended
even.

Word operand processing will normally be performed when both the A and
B field register arguments are even.
During the first microcycle of a
word microinstruction, the 2 register fields designate the 8-bit operands.
During
the second microcycle the low-order bit of each of the
register fields is logically complemented, thus pointing to
the
next
register
1locations.
For
example,
if A and B are 00 and 10 (octal)
during the first microcycle, the effective arguments become 01 and
11
during the second microcycle.
This case is illustrated in Figure 4-6.
The
bus

operation on
used,
which
assembles as
If
1,

the B
the

field assembly arguments
register symbol, RBA is

the lower byte of this
also assembles as 12.
13.

reflect
this
convention.
The
equivalent to 12.
To perform an
register, the symbol RBAL would be
RBAH, the corresponding high byte

field argument is assembled with the low-order bit
B
field
contents
point
to the first byte to be

equal
to
processed.

During the second cycle, however, the high byte is formed by extending
the
high-order
bit of the first or low byte through 8 bit positions.
This case is illustrated in Figure 4-7.
The sign extension procedure presented above does
NOT
apply
in
the
case
of an A register field odd argument.
Instead, the low-order bit
of the A field is complemented for the second cycle, and the byte
register
accessed
1is the Next Lower byte.
Thus the word operand input

via

the A

field

byte-swapped,

illustrated

Figure

4-8.

THE

3.5

LSI-11 MICROMACHINE

MICROPROGRAMMING THE BASIC

STRUCTURE

LSI-11 MACHINE CYCLE

The essential characteristics of the microprograms which
emulate
the
LSI-11
microcomputer
architecture
will
be discussed for two simple

cases.
second
and

The first case is the basic two-event machine
cycle
and
the
case
1is the basic machine cycle including external interrupts
error

bus

3.5.1

traps.

Fetch-Execute Machine Cycle Microprogramming

The basic LSI-11 machine cycle, repeated here as Figure 3.24, consists
of a DATI operation followed by a microprogrammed routine which interprets and executes the fetched machine instruction.
The
DATI
operation
1is itself microprogrammed as a Read/Input sequence which is discussed in Chapter 5.
The specific Read microinstruction
employed
1is
Read And Increment Word By 2 (RIWZ2).
This microinstruction places the
contents of the register pair designated within it, PC H and
PC L
on
BDAL
L
<15:00>
and initiates a Data-In system bus cycle.
It subsequently increments the word contained in PC H and PC L by
2,
causing

the
Program Counter to point to the next address from which a machine
instruction is to be fetched.
The
specific
Input
microinstruction
used,
which
comprises the second half of the Read/Input sequence, is
Input Word.
This microinstruction places the fetched machine instruction
into
the instruction register RIR L and RIR H and also loads it
into

the Translation Registers TR RO and TR Rl.

byte
put

the machine

Note

that

the

lower

instruction is put in RIR H and the high byte is

in RIR L.

The Execute Machine Instruction portion of the basic machine cycle begins
with the examination of the Translation Register contents by the
translation array.
The translation array output, which
1is
available
after
one
micromachine
<c¢ycle,
produces
the address of the control
store or MICROM location which contains the first instruction
of
the
microprogrammed
routine
which
will execute the machine instruction.
The translation array may be used one, two or three times
during
the
Execute
Machine Instruction operation, depending upon the type of instruction being executed.
In preparing the ALU operands,
zero,
one,
or
-several DATI operations are performed, depending upon the address-

ing modes used in

the

machine

instruction

source

and

destination

fields.

3.5.2

Fetch-Execute-Trap

Interrupt Machine Cycle Microprogramming

The basic machine cycle of Figure 3.24 is expanded in
Figure 3.25
to
include external interrupts and the single and double bus error traps.
As explained in Chapter 2, a bus error occurs when an addressed device
does
not
respond within 10 microseconds.
This leaves the Read/Input

sequence of the DATI operation uncompleted and the Bus Interface Logic
asserts
the
Control
<chip
reset
line.
As
a result, the Location
Counter is loaded with 0001 and a microprogrammed bus
error
recovery
routine is executed.
Two DATO cycles are performed to push the PC and
PSW contents

onto

new

into the program counter

ters.

values

the

stack,

followed

two DATI

and processor

cycles

which

status word

1load

regis-

THE

LSI-11

MICROINSTRUCTION

Microinstruction with
Figure

Even

SET

4-6

MICROINSTRUCTION OPCODE

LEAST SIGNIFICANT

BYTE OPERATION

6
RB

MOST SIGNIFICANT |
BYTE OPERATION

MR 1067

THE

LSI-11

MICROINSTRUCTION

Microinstruction
Figure

with

O0dd

SET

4-7

MICROINSTRUCTION OPCODE

LEAST SIGNIFICANT
BYTE OPERATION

RB*

MOST SIGNIFICANT

BYTE OPERATION

* THE MOST SIGNIFICANT BIT IS USED FOR
ALL 8BITS OF THE RB ARGUMENT.
MR 1068

THE

LSI-11

MICROINSTRUCTION

Microinstruction with 0dd
Figure

SET

Input

4-8

MICROINSTRUCTION OPCODE

LEAST SIGNIFICANT

BYTE INPUT

MOST SIGNIFICANT
BYTE INPUT

MR-1069

THE

LSI-11

MICROINSTRUCTION

SET

Since

the A field also determines the destination of the
ALU
output,
the
abnormal
reversed
register
coding
sequence is apparent in the
final register file contents.
This case is illustrated in Figqure 4-9,
which shows that the low-order 8-bits of the word result are deposited
in the high or odd byte and the high-order 8-bits are deposited in the
low byte.

Right

Shift Word Operations

Since all Right Shift Word operatiohs begin with the left-most part of

the
word
Shift Word

operand, both the
operations follow

A and B field argument must be odd.
the Normal Use conventions above.

Left

THE

LSI-11]

MICROINSTRUCTION

Microinstruction
Fiqure

with

O0dd

SET

Output

4-9
RB

MICROINSTRUCTION OPCODE

LEAST SIGNIFICANT
BYTE OUTPUT

MOST SIGNIFICANT
BYTE OQUTPUT
MR 1070

THE

4.3

MICROINSTRUCTION

Because

the

large

LSI-11

SET

MICROINSTRUCTION

FUNCTIONAL

number

SET

ORGANIZATION

microinstructions

the

microprocessor

repetroire,
it
1is useful to establish a system of organization along
functional lines.
The three major functional classifications are Data
Manipulation,
Data
Access,
and
Microprogram
Control.
Subclassifications

of microinstructions exhibit variations of a
basic
For
example,
under the Data Manipulation classification
general subclassification "Move".

operation.
there is the

The
final
description
of
a
microinstruction
is
determined
(1) whether it is a byte or word microinstruction,
(2) whether the
dicated operation is performed conditionally or
unconditionally,
(3) whether it updates the ALU condition code flags (N, 2, V, C).

4.3.1

Data

Manipulation

Increment/Decrement,

tions
performed
completed within
croinstructions
the

ALU

status

by
the

and

Microinstructions
°

The microinstructions in this group provide the bulk of
the
chine
data
manipulation
ability.
The subclassifications
Move,

by
in-

Logical,

Shift,

and

Arithmetic.

micromahere are:
The

opera-

all microinstructions in this classification
micromachine and do not require I/0.
These

affect
microprogram
bit and condition code

are
mi-

control only in that they update
flags and that some are executed

conditionally.

4.3.1.1

Move

Microinstructions

The

common

feature

the

Move

Mi-

croinstructions
1is
micromachine.
These

that
they move data between locations within the
locations are exclusively within the microproces-

sor

chips,

Data

and

Control

croinstruction
which moves
a designated register.
The

Microinstruction

with

the

constant

descriptions

are

exception

contained

the

Load

Literal

in microinstruction

follows:

mi-

THE

LSI-11

MICROINSTRUCTION SET

LL
LOAD

LITERAL

0
15

LITERAL FIELD
11

OPCODE:
MICROCYCLES:

06XXXX
1

OPERATION:
DESCRIPTION:

(RA) <-- (LITERAL FIELD)
The 8-bit contents of the

BITS:

NB:
ZB:

set
set

C4:

not
not

C8:

CONDITION

CODES:

if byte result
if byte result
affected

<
=

|
0

1literal

are
loaded
1into
register
bit flags are updated.
The
field are not changed.
STATUS

A REG FIELD

0;
0;

field,
MIK1l1l:4>,
RA.
The NB and ZB status
contents of
the
1literal

cleared
cleared

otherwise
otherwise

affected

N:
Z:

not
not

affected
affected

not

affected

not

affected

200,RSRCH

EXAMPLE:
ASSEMBLY

MNEMONIC:

ASSEMBLED OCTAL:

;MOVE

200

RSRCH

064005
BEFORE

(RSRCH)

NB
0O

ZB
0

C4
0

C8
0

AFTER

000

N
0

Z
0

(RSRCH)

V
o0

C
O

NB
1

ZB
0

C4
0

C8
0

200

N
0

Z2
O

V
O

C
O

THE

LSI-11 MICROINSTRUCTION SET

LGL

LOAD

LOW

"14

"13

"10

UNUSED

[

A REG FIELD

072400-072777
1
(G REGISTER) <-- RA<2:0>
The three lowest-order bits of RA are loaded into the
G
register.
These
3 bits are subsequently used in
indirect register addressing
operations.
With
the
exception of the INPUT WORD microinstruction, the LGL
microinstruction provides the only means for controlling the G register contents.
The contents of RA are
unchanged and the flag register contents are not
af-

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

fected.
STATUS

BITS:

CONDITION

CODES:

NB:

not

affected

ZB:
C4:
C8:

not
not
not

affected
affected
affected

not

affected

Z:
V:
:

not
not
not

affected
affected
affected

EXAMPLE:

ASSEMBLY MNEMONIC:
ASSEMBLED

OCTAL:

LGL
RIRL
072410

; LOAD THE

BEFORE

(RIRL)

(G)
NB

cC4C8
0
1

AFTER

377

(RIRL)

=0
N
0

z
0

V
0

C
1

NB
0

ZB
0

C4
0

377

(G)

C8
1

N
0

2z
0

V
0

C
1

THE

LSI-11

MICROINSTRUCTION SET

LTR

LOAD

TRANSLATION

"12

"1IT

"I0

- 9

B REG FIELD

OPCODE:
MICROCYCLES:

167000-167377
1

OPERATION:

(TRANSLATION

DESCRIPTION:

The 16-bit contents of
translation
register.
unchanged and the flag

<--

A REG FIELD

(RB:RA)

RB:RA
are
loaded
The contents of RB
register
contents

1into
the
and RA are
are
unaf-

fected.
STATUS

BITS:

CONDITION

CODES:

NB:
ZB:
C4:

not
not
not

affected
affected
affected

C8:

not

affected

N:
Z:

not
not

affected
affected

not

affected

not

affected

EXAMPLE:

ASSEMBLY

MNEMONIC:

LTR

ASSEMBLED OCTAL:

RIRH,RIRL

; LOAD

TRANSLATION

BEFORE

NB
0o

ZB
0

071424
AFTER

(RIR)

100200

(TR)

000000

C4
0

C8
1

N
0

Z
0

V
0

C
O

NB
c

ZB
0

(RIR)

100200

(RIR)

100200

C4
0

C8
1

N
0

2z
0

V
0

C
O

THE

LSI-11 MICROINSTRUCTION SET

CCF

FLAGS

COPY CONDITION

15 "14 "1I3 "1z

UNUSED

[

]

071000-071377
1
(RA) <-- (FLAG REGISTER)

OPCODE:
MICROCYCLES:
OPERATION:

The 8-bit contents of the ALU status bit

DESCRIPTION:

A REG FIELD

condi-

and

The flag
flag register are placed in RA.
code
tion
register contents are unaffected by this operation.

The ALU

flags

following

STATUS BITS:

NB:

CONDITION CODES:

ZB:
C4:
C8:

and condition codes are copied

1in

the

format:

not affected
not
not
not

affected
affected
affected

not affected

Z:
V:
C:

not
not
not

affected
affected
affected

ASSEMBLY MNEMONIC:

CCF

RDSTL

ASSEMBLED OCTAL:

071006

EXAMPLE:

; COPY FLAGS TO RDSTL

AFTER

BEFORE

NB 2B C4 C8
1

(RDSTL)

= 000
N
0

Z
0

V
O

(RDSTL)

= 200
N

LSI-11

Machine

Figure

STRUCTURE

Cycle

3-24

Basic

MICROMACHINE

FETCH

MACHINE
INSTRUCTION

EXECUTE
MACHINE
INSTRUCTION

THE

MR-1022

THE

LSI-11

MICROINSTRUCTION

SET

LCF

LOAD

CONDITION

FLAGS

|
[
I
I
13 "12 "1IT "10

OPCODE:

REG

OPERATION:

(FLAG

DESCRIPTION:

The

8-bit

the

ALU

and

<--

contents

A REG

FIELD

flag

(RA)

control

the

condition

code

flags,

affected.

are

not

The

ALU

ing

format:

flag

are

selectively

7
BITS:

CODES:

the

respectively.

format

loaded

Microinstruction

T
IC4 |

CONDITION

071400-071777
1

MICROCYCLES:

STATUS

FIELD

The

loaded

bits

contents

the

loaded

from

RA<7>,

ZB:

loaded

unconditionally

from

RA<6>,

C4:
C8:

loaded
loaded

from RA<5>,
from RA<4>,

unconditionally

follow-

NB:

unconditionally
unconditionally

loaded

from

RA<3>,

when

loaded

(MI<7>)

when

(MIK6>)

V:
C:

loaded
loaded

from RA<2>,
from RA<1>,
from RA<K0>,

when
when

(MIK5>)
(MI<4>)

=1
=1

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

LCF

RDSTL

; LOAD

FLAGS

FROM

RDSTL

071424

BEFORE

(RDSTL)

AFTER

017

(RDSTL)

and

into
4,

017

2Z2

THE

LSI-11

MICROINSTRUCTION

SET

(MBF)

MOVE

BYTE

(UPDATE

CONDITION

"13

OPCODE:

710

OPERATION:

(RA)

<--

DESCRIPTION:

The

8-bit

tents

BITS:

CONDITION
(MBF

CODES:

ONLY)

FLAGS)

(1)|

100000-100377
1l

MICROCYCLES:

STATUS

CODE

REG

FIELD

A REG

FIELD

(100400-~100777)

(RB)

contents

bit

flags

are

tion

code

are

not

are placed in RA.
affected.
The NB and

updated.
MBF causes
flags to be updated.

NB:

set

byte

result

ZB:

set

byte

result

C4:
C8:

not
not

affected
affected

the

cleared
cleared

The

con-

status

condi-

and

otherwise
otherwise

set

byte

result

set

cleared

byte

result

otherwise

cleared

otherwise

not

affected

RDSTL,RSRCL

EXAMPLE
:

ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

;MOVE

BYTE

FROM

RDSTL

RSRCL

100344

BEFORE

AFTER

(RDSTL)

000

(RSRCL)

377

(RDSTL)

000

(RSRCL)

000

THE LSI-11 MICROINSTRUCTION SET

(CMBF)

CMB

(UPDATE CONDITION CODE FLAGS)

CONDITIONALLY MOVE BYTE

13 12 11 "10 ~ 9
102000-102377

OPCODE:

MICROCYCLES:

(1)

B REG FIELD

A REG FIELD

(102400-102777)

(RA) <-- (RB), IF C FLAG =1
C
the
The 8-bit contents of RB are placed in RA, if
The conset = 1 by a previous operation.
was
flag

OPERATION:
DESCRIPTION:

ZB
The NB and
tents of RB are not affected.
bit
flags are updated.
CMBF causes the N and
dition code flags to be updated.

STATUS BITS:

NB:

set if byte result < 0;
set

1f byte result = 0;

C4:
C8:

not
not

affected
affected

ZB:

CONDITION CODES:
(CMBF ONLY)

if byte result < 0
if byte result = 0

N:
Z:

set
set

cleared

not

NOTE:

[4
.

status
Z con-

cleared otherwise

cleared otherwise
cleared otherwise

affected

The

status bit

(and condition code)

flags

updated only if the C flag was initially set = 1.

EXAMPLE:

RDSTL,RSRCL

ASSEMBLY MNEMONIC:

CMB

ASSEMBLED OCTAL:

102144

;IF C = 1, MOVE BYTE
;FROM

RDSTL TO

BEFORE

AFTER

(RDSTL)
(RSRCL)

= 000
= 377

(RDSTL)
(RSRCL)

RSRCL

NB
o

ZB C4
0
o

C8
0

= 000
= 377
N
0

Z
0

V
0

C
O

are

THE

LSI-11

MICROINSTRUCTION

SET

(MWF)
MOVE

WORD

(UPDATE

CONDITION

15 7124 "I3 712 11

CODE

OPCODE:

101000-101377

MICROCYCLES:

OPERATION:

(RA+1:RA)

DESCRIPTION:

The

(RA+1:RA)
tents

()|

REG

BITS:

CONDITION CODES:
(MWF ONLY)

A REG

when

are

1is

(RB+1:RB)

even.

placed

When
and

are

the

con-

high-order

bit

(RA+1l).
The contents of
The NB and ZB status bit

NB:

set

word

result

cleared

otherwise

ZB:
C4:

set
not

if word result
affected

cleared

otherwise

C8:

not

affected

1if

word

cleared

not

result
result

the

updated.
MWF causes
to be updated.

set
set

placed

odd,

flags
are
code flags

N:
Z:

FIELD

5473727170

of RB replaces the 8 bits of
(RB+1:RB) are not affected.

STATUS

(RB+1:RB)

contents

FIELD

(101400-101777)

<--

16-bit

FLAGS)

the

and

condition

cleared
cleared

otherwise
otherwise

:MOVE

WORD

RDST

affected

EXAMPLE
:
ASSEMBLY

MNEMONIC:

MWF

ASSEMBLED OCTAL:

RDST,RSRC

FROM

RSRC

101544
BEFORE

(RDST)
(RSRC)

=
=

AFTER

000000
1777717

(RDST)
(RSRC)

=
=

000000
000000

THE LSI-11 MICROINSTRUCTION SET

CMW

(CMWF)

CONDITIONALLY

"14

MOVE

"12

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

WORD

(UPDATE

710

(1)|]

103000-103377
2
(RA+1:RA)
The 8-bit

CONDITION

CODE

REG

[

FLAGS)

FIELD

A REG

FIELD

(103400-103777)

<-- (RB+1:RB), IF C
contents of RB+1:RB

FLAG =1
are placed

in
RA+1:RA
if
the
C
flag
was set = 1 by a previous operation
when B is even.
When B is odd, the
contents
of
RB
are
placed
in
RA
and the high order bit of RB replaces the 8 bits of RA+1l if the C flag was set=1
by
a
previous
operation.
The contents of RB+1:RB are
not affected.
The NB and ZB status bit flags are updated.
CMWF causes the N and Z condition code flags
to be updated.

STATUS

BITS:

CONDITION CODES:
(CMWF ONLY)

NB:

set

ZB:
C4:

set
not

word result
if word result
affected

C8:

not

affected

N:
Z:

set
set

if word
if word

cleared

not

result
result

<
=

0;
0;

cleared

otherwise

cleared

otherwise

cleared
cleared

otherwise
otherwise

affected

NOTE: the status bit (and condition code)
flags
updated only if the C flag was initially set = 1.

EXAMPLE:

ASSEMBLY

MNEMONIC:

CMWF

RDST,RSRC

;IF

;FROM

ASSEMBLED

OCTAL:

RDST

MOVE
TO

103444
BEFORE

AFTER

(RDST)

177777

(RDST)

177777

(RSRC)

000000

(RSRCL)

177777

NB ZB C4C8
0

WORD

RSRC

NB ZB C4C8
1

are

THE LSI-11] MICROINSTRUCTIQON SET

4.3.1.2
crement

1Increment / Decrement Microinstructions - The Increment / DeNote
only on register contents.
operate
Microinstructions

that there is no means of incrementing or decrementing the G

contents.

The microinstruction descriptions are as follows:

THE

ICB1

SET

(ICB1F)

INCREMENT

LSI-11 MICROINSTRUCTION

BYTE

(UPDATE

(l)!

|
l
l
I
l
"I5 714 713712 IT "I0 " 9~

OPCODE:
MICROCYCLES:

110000-110377
1

OPERATION:

(RA)

DESCRIPTION:

The

<-sum

CONDITION

REG

CODE

FLAGS)

FIELD

l
l
776

A REG

STATUS

BITS:

CONDITION CODES:
ICB1lF (ONLY)

l
|
l
|
l
57473727170

(110400-110777)

(RB)+1
of

the

8-bit

contents

plus

in RA.
The contents of RB are unchanged.
bit flags, except C4, are updated.
ICBlF
N,

FIELD

and

condition

flags

placed

All status
causes
the

updated.

NB:

set

byte

result

cleared

otherwise

ZB:

set

byte

result

cleared

otherwise

C4:
C8:

set
set

1f
if

bit<3> carry out = 1l; cleared otherwise
carry out = 1; cleared otherwise

N:
Z:

set
set

if
if

the
the

byte
byte

set

arithmetic

set

carry

ICBl1

RDSTL,RSRCL

out

result
result
=

0;
0;

cleared
cleared

otherwise
otherwise

overflow;

cleared

otherwise

<
=

cleared

otherwise

EXAMPLE:
ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

;ADD

RDSTL,

SUM

RSRCL

110144
BEFORE

AFTER

(RDSTL)

002

(RDSTL)

002

(RSRCL)

376

(RSRCL)

377

NB ZB
00

C4C8
0
0

N
0

Z
0

V
0

C
O

NBZBC4C8
1
0
0
0

N
0

2z
0

V
0

C
O

THE

ICB2

LSI-11 MICROINSTRUCTION

SET

(ICB2F)

INCREMENT

]2
15

BYTE

OPCODE:
MICROCYCLES:

(UPDATE

(l)|
9

112000-112377
1

OPERATION:

(RA)

DESCRIPTION:

The

<-sum

CONDITION

REG

CODE

FLAGS)

FIELD

A REG

STATUS

BITS:

CONDITION

(ICB2F

CODES:

ONLY)

(112400-112777)

(RB)+2
of

the

8-bit

contents

plus

in RA.
the contents of RB are unchanged.
bit flags, except C4, are updated.
ICB2F
N,

FIELD

and

condition

code

result

NB:

set

byte

ZB:

set

C4:
C8:

set
set

if
if

byte result = 0;
bit<3> carry out

carry

out

flags

cleared

placed

all status
causes
the

updated.

otherwise

cleared otherwise
= 1; cleared otherwise

cleared

otherwise

set

the

byte

result

cleared

otherwise

set

the

byte

result

cleared

otherwise

V:
C:

set
set

if
if

arithmetic overflow; cleared otherwise
carry out = 1; cleared otherwise

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

ICB2

RDSTL,RSRCL

;ADD

RDSTL,

RSRCL

112544
BEFORE

NB
0

SUM

AFTER

(RDSTL)

002

(RDSTL)

002

(RSRCL)

376

(RSRCL)

001

ZB
0

C4
0

C8
0

N
0

2z
0

V
0

C
O

NB
0

ZB
0

C4
0

C8
0

N
O

2z
O

V
o0

C
o

THE

LSI-11 MICROINSTRUCTION

SET

CIB
CONDITIONALLY

INCREMENT

BYTE

I
I3 712 "I1 "I0

I
|

UNUSED

I
I
987

A REG

543

FIELD

2710

OPCODE:

073000-073377

MICROCYCLES:

OPERATION:

(RA) <-- (RA)+1, IF C8 =1
The 8-bit contents of RA are incremented by 1 if
the
C8
status
bit flag was set = 1 by a previous operation.
All status bit flags, except C4, are
updated.
The B register field is unused.

DESCRIPTION:

STATUS

BITS:

CONDITION

CODES:

NB:
ZB:

set
set

C4:
C8:

and
set
set

if
if

byte result
the ZB flag

< 0; cleared otherwise
was set prior to the operation
byte result was = 0; cleared otherwise
if bit<3> carry out = 1; cleared otherwise
1if carry out = 1; cleared otherwise

not

affected

not

affected

not

affected

not

affected

CIB

RDSTL

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

;IF

1,INCR

RDSTL

073006
BEFORE

{RDSTL)

AFTER

002

(RDSTL)

003

THE

DB1

SET

(DB1F)

DECREMENT

LSI-11 MICROINSTRUCTION

BYTE

"14

"13

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

(UPDATE

"1I1

CONDITION

710

(1)!

CODE

REG

[

FLAGS)

FIELD

REG

136000-136377 (136400-136777)
1
(RA) <-- (RB)-1
The 8-bit contents of RB are decremented

contents
of RB are unchanged.
All status
except C4, are updated.
DBlF
causes
the
code flags, except V, to be updated.
STATUS

BITS:

CONDITION

(DB1F

CODES:
ONLY)

result

cleared

FIELD

The

bit flags,
condition

NB:

set

byte

ZB:
C4:
C8:

set
set
set

if
if
if

byte result = 0; cleared otherwise
bit<3> carry out = 1l; cleared otherwise
carry out = 1; cleared otherwise

otherwise

N:
Z:

set
set

if
if

the byte result < 0; cleared otherwise
byte result = 0; cleared otherwise

V:
C:

set
set

if
if

arithmetic overflow; cleared otherwise
a borrow occurs; otherwise cleared

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

DBl

RDSTL,RSRCL

;DECR

RDSTL

PLACE

RSRCL

V
0

C
O

136044
BEFORE

AFTER

(RDSTL)

002

(RDSTL)

002

(RSRCL)

100

(RSRCL)

001

ZBC4C8

V
0

C
O

NB
0

ZBC4C8
0
0
0

N
0

Z
0

THE

LSI-11

External

MICROMACHINE

Interrupt

and

Figure

Bus

STRUCTURE

Error

Trap

3-25

FETCH
MACHINE

INSTRUCTION |LBYS ERROR

(SINGLE)

EXECUTE
MACHINE

ERROR

INSTRUCTION |.BYS ERRO

EXTERNALNG
INTERRUPT.”

(SINGLE)

VES

VECTOR

1000R DEVICE

BUS ERROR
PUSH

PC,PSW

GET

PC.PSW

VEC
BUS

004

ERROR

TRAP 1 pusH Pc,psw
GET

PC.PSW

BUS ERROR

(DOUBLE])

HALT

MR-1024

THE

LSI-11 MICROINSTRUCTION

SET

CDB

CONDITIONALLY

0
15

DECREMENT

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

BITS:

CONDITION

CODES:

1|
9

UNUSED

A REG
3

073400-073777
1
(RA) <-- (RA)-1, IF C8 =0
The 8-bit contents of RA are

decremented

status

tion.
The B
STATUS

BYTE

bit

flag

was

set

All status bit flags, except
register field is unused.

are

the

opera-

updated.

NB:
ZB:

set
set

if
if

byte result < 0; cleared otherwise
the ZB flag was set prior to the operation

C4:
C8:

and
set
set

byte result was = 0; cleared otherwise
1f bit<3> carry out = 1; cleared otherwise
1f carry out = 0; cleared otherwise

not

affected

not

affected

not

affected

CDB

RDSTL

EXAMPLE
:

ASSEMBLY

C4,

FIELD

MNEMONIC:

ASSEMBLED OCTAL:

;IF

1,DECR

RDSTL

073406

BEFORE
(RDSTL)

AFTER

002

(RDSTL)

C4C8

001
N

THE

SET

(ICWI1F)

ICWl1

INCREMENT WORD BY

I
|

LSI-11 MICROINSTRUCTION

(UPDATE

15 14 13 "12 11

CONDITION

()|

REG

CODE

FLAGS)

FIELD

A REG

FIELD

OPCODE:

111000-111377

MICROCYCLES:
OPERATION:

DESCRIPTION:

The sum of the 16-bit contents of RB+1:RB plus
1
is
placed in RA+1:RA when B is even.
When B is odd, the
sum of the contents of RB with its high-order bit extended
through the 8 high-order bits and 1 is placed
in RA+1:RA.
The contents of RB+1:RB
are
unchanged.
All
status bit flags, except C4, are updated.
ICWIF
causes the condition code flags, except V, to be
updated.

STATUS

NB:
ZB:
C4:

set
set
set

if word result < 0;
if word result = 0;
if bit<3> carry out

C8:

set

(RA+1:RA)

BITS:

CONDITION CODES:
(ICB1F ONLY)

N:
Z:
V:
C:

set
set
set
set

<--

if
if
1f
1if

(111400-111777)
(RB+1l:RB)+1

carry

out

1l;

cleared otherwise
cleared otherwise
= 1; cleared otherwise

cleared

otherwise

the word result < 0; cleared otherwise
the word result = 0; cleared otherwise
arithmetic overflow; cleared otherwise
carry out = 1; cleared otherwise

EXAMPLE:

ASSEMBLY MNEMONIC:

ICWlF RDST,RSRC

ASSEMBLED OCTAL:

111544

;ADD

TO RDST,

BEFORE

NB
O

ZB
0

SUM

IN RSRC

AFTER

(RDST)

177776

(RDST)

177776

(RSRC)

000000

(RSRCL)

177777

C4
0

C8
0

N
0

zZ
0

V
0

C
O

NB
l1

ZB
0

C4
0

C8
0

N
1

2z
0

Vv
O

C
O

THE

ICW2

MICROINSTRUCTION

SET

(ICW2F)

INCREMENT

LSI-11

WORD

(UPDATE

CONDITION

(1)]

REG

CODE

FIELD

OPCODE:

113000-113377

MICROCYCLES:
OPERATION:
DESCRIPTION:

2
(RA+1:RA) <-- (RB+1:RB)+2
The sum of the 16-bit contents

placed

FLAGS)

A REG

FIELD

(113400-113777)

in RA+1:RA when B

RB+1:RB

even.

When B

plus

odd,

the

sum of

the contents of RB with its high-order bit extended
through
8 high-order bits and 2 is placed in
RA+1:RA.
The contents of RB+1:RB are unchanged.
All

status
causes

bit
flags,
the condition

except
C4,
code flags,

are updated.
ICW2F
except V, to be
up-

dated.
STATUS

BITS:

CONDITION

CODES:
(ICW2F ONLY)

NB:
ZB:

set
set

if
if

word
word

C4:
C8:

set
set

if
if

bit<3> carry out = 1l; cleared otherwise
carry out = 1; cleared otherwise

result
result

<
=

0;
0;

cleared
cleared

set

Z:
V:

set
set

if
if

the word result < 0;
the word result = 0;
arithmetic overflow;

set

carry

out

otherwise
otherwise

cleared

otherwise
otherwise
otherwise

cleared
cleared

cleared

otherwise

EXAMPLE:

ASSEMBLY

MNEMONIC:

ICWZ2F

ASSEMBLED

OCTAL:

113544

RDST,RSRC

;ADD

RDST,

BEFORE

SUM

RSRC

AFTER

(RDST)

177776

(RDST)

177776

(RSRC)

000000

(RSRCL)

000001

THE

DWl

SET

(DW1F)

DECREMENT WORD BY

LIS-11 MICROINSTRUQTION

~15 "174

(UPDATE

I3 712

CONDITION CODE FLAGS)

"I0

(1)|

137000-137377
2

OPCODE:
MICROCYCLES:

REG

FIELD

A REG

FIELD

(137400-137777)

(RA+1:RA) <-~- (RB+1:RB)-1
The 16-bit contents of RB+1:RB are decremented
by
1
and
placed
1in RA+1:RA.
The contents o f RB+1:RB are
unchanged when B is even.
When B is
odd,
the
contents
of RB with its high-order bit extended through
8 high-order bits minus 1 is placed in RA+1:RA.
All
status
bit
flags,
except
C4,
are
updated.
DWIF
causes the condition code flags, except V, to be
updated.

OPERATION:
DESCRIPTION:

STATUS

BITS:

CONDITION CODES:
(DW1F ONLY)

NB:
ZB:
C4:

set
set
set

if word result < 0;
if word result = 0;
1if bit<3> carry out

C8:

set

1if

N:
Z:
V:
C:

set
set
set
set

carry

out

cleared othe rwise
cleared othe rwise
= 1l; cleared otherwise

cleared

otherw ise

if the word result < 0; cleared o therwise
i1f word result = 0; cleared otherwise
if arithmetic overflow; cleared o therwise
if a borrow occurs; otherwise cle ared

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED OCTAL:

DW1F

RDST,RSRC

;DECR

RDST

PLA CE

RSRC

137544
BEFORE

NB
0

AFTER

(RDST)

000001

(RDST)

000001

(RSRC)

000000

(RSRCL)

000000

ZBC4C8
0
0
0

N
0

2
0

V
0

C
O

NB
0

ZB
1

C4
0

C8
0

N
0

VvV

THE

4.3.1.3

Logical

LSI-11 MICROINSTRUCTION SET

Microinstructions

The

Logical

Microinstructions

perform variations of the basic unary and binary operations:
And, And
Complement, Or, Exclusive Or, Ones Complement, and Twos Complement.

The microinstruction descriptions are as follows:

THE

LSI-11 MICROINSTRUCTION

SET

NL
AND

LITERAL

714

|__!
I3
"12

LITERAL

11T

"I0

OPCODE:

04XXXX

MICROCYCLES:
OPERATION:
_

1
(RA)

<=-=

DESCRIPTION:

The

8-bit

~ 9~

FIELD

I
l
!
l
l
|
543727170

(RA)"AND" (LITERAL

FIELD)

contents

1literal

A REG

the

field,

MI<K1l:4>,

are
ANDed
with the 8-bit contents of RA and the result is loaded into RA.
The content of
the
1literal
field
remains
unchanged.
The NB and ZB status bit
flags are updated.
STATUS

BITS:

CONDITION

CODES:

NB:

set

ZB:
C4:

set
not

byte
byte

affected

C8:

not

affected

not

affected

not

affected

not

affected

ASSEMBLY MNEMONIC:

200,RBAL

ASSEMBLED

044002

result

<
=

0;
0;

cleared

otherwise

cleared

otherwise

affected

EXAMPLE:

OCTAL:

;200

"AND"

RBAL,

BEFORE

(RBAL)
NB
0

ZB
0

C4
0

C8
0

AFTER

377
N
0

INTO RBAL

2z
O

(RBAL)
V
0

C
O

NB
l1

ZB
0

C4
0

C8
0

200
N
0

2z
0

V
0

C
O

THE

LSI-11

MICROINSTRUCTION

SET

(NBF)

AND

BYTE

(UPDATE

CONDITION

OPCODE:

FLAGS)

It
15
14
I3 "12 11
10

CODE

(1)!

140000-140377

REG

OPERATION:
DESCRIPTION:

(RA) <-- (RB)"AND" (RA)
The 8-bit contents of RB

STATUS

BITS:

CONDITION CODES:
(NBF ONLY)

the

condition
byte

code

set

result

ZB:
C4:

set
not

if byte result
affected

C8:

not

affected

the
the

are

ANDed

REG

FIELD

with

RA and placed in RA.,
The status bit flags

NB:

if
if

(140400-140777)

causes

I___1___\___1___1__
1__|___I__
"8
"7
6
5437271770

MICROCYCLES:

contents
of
is unchanged.

FIELD

N:
Z:

set
set

byte
byte

cleared

not

affected

NBF

RDSTL,RSRCL

result
result

flags
0 ;

The
are
be

the

8-bit

content of RB
updated.
NBF

updated.

cleared otherwise

cleared

<
=

0;
0;

otherwise

cleared
cleared

otherwise
otherwise

EXAMPLE:
ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

;RDSTL"AND"RSRCL,

RESULT

RSRCL

140544
AFTER

201

(RDSTL)

201

(RSRCL)

176

(RSRCL)

000

(RDSTL)

(=N

BEFORE

THE LSI-11 MICROINSTRUCTION SET

(NCBF)

NCB

(UPDATE CONDITION CODE FLAGS)

AND COMPLEMENT BYTE

1
15

1
"1I7

0
"I3

1
12

"1IT

710

0
9

(1)|
8

B REG FIELD
Yj

150000-150377

DESCRIPTION:

The complement of the 8-bit contents of RB are

1
(RA)

<--

]

(150400-150777)

OPCODE:

MICROCYCLES:
OPERATION:

A REG FIELD

(RB)"AND" (RA)

ANDed

The
the 8-bit contents of RA and placed in RA.
with
The status bit flags are
content of RB is unchanged.
NCBF causes the condition code flags to be
updated.
updated.

NB: set if byte result < 0; cleared otherwise

STATUS BITS:

ZB:

set

if byte result = 0;

C4:
C8:

not
not

affected
affected

CONDITION CODES:
(NCBF ONLY)

cleared otherwise

:
:

set if the byte result < 0;
set if the byte result = 0;

cleared

not

cleared otherwise
cleared otherwise

affected

EXAMPLE:

ASSEMBLY MNEMONIC:

NCBF RDSTL,RSRCL ;RDSTL"AND"RSRCL, RESULT IN RSRCL

ASSEMBLED OCTAL:

150544
AFTER

BEFORE

(RDSTL)

= 201

(RDSTL)

= 201

(RSRCL)

= 176

(RSRCL)

= 176

NB zZB C4 C8

ZB C4 C8

THE

LSI-11]

MICROINSTRUCTION

SET

(NWF)
AND

WORD

(UPDATE

OPCODE:

CONDITION

"11

710

FLAGS)

CODE

()]

REG

FIELD

141000-141377
2

(141400-141777)

OPERATION:

(RA+1:RA)

DESCRIPTION:

(RB+1:RB) "AND" (RA+1:RA)

The

contents

content

flags

BITS:

CONDITION

(NWF

CODES:

ONLY)

are

flags
STATUS

contents

RB+1:RB

updated.

RB+1:RB

are

RA+1:RA

and

unchanged.

causes

cleared
cleared

NB:

set

word

result

ZB:

set

word

result

C4:

not

affected

C8:

not

affected

ANDed

updated.

The

the

FIELD

placed

NWEF

16-bit
The

<--

16-bit

MICROCYCLES:

REG

with

the

RA+1:RA.

status

bit

condition

code

otherwise
otherwise

set

the

word

result

cleared

set

otherwise

the

word

result

cleared

otherwise

not

affected

RDST,RSRC

EXAMPLE:
ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

;RDST"AND"RSRC,

RESULT

RSRC

141144
BEFORE

AFTER

(RDST)

000000

(RDST)

000000

(RSRC)

177777

(RSRC)

000000

THE LSI-11 MICROINSTRUCTION SET

NCW

(NCWF)

AND COMPLEMENT WORD

(UPDATE CONDITION CODE FLAGS)

Y15 "I4 "13 712 I1 10T

(1)l

I
I
98

151000-151377

OPCODE:

B REG FIELD

I
76

1
|

A REG

FIELD

I
|
170

547372

(151400-151777)

MICROCYCLES:
OPERATION:
DESCRIPTION:

STATUS

(RA+1:RA) <-- (RB+1:RB)"AND" (RA+1:RA)
The 16-bit contents of RB+1:RB are
complemented
and
ANDed
with the 16-bit contents of RA+1:RA and placed
in RA+1:RA.
The content
of
RB+1:RB
is
wunchanged.
The
status
bit
flags are updated.
NCWF causes the
condition code flags to be updated.

BITS:

CONDITION CODES:
(NCWF ONLY)

NB:

set

ZB:
C4:
C8:

set
not
not

if word

result
if word result
affected
affected

N:
Z:

set
set

if
if

the word
the word

cleared

not

<
=

result
result

0;
0;

cleared

<
=

otherwise
cleared otherwise

0;
0;

cleared otherwise
cleared otherwise

affected

EXAMPLE:

ASSEMBLY MNEMONIC:

NCW RDST,RSRC

ASSEMBLED OCTAL:

151144

;RDST"AND"RSRC, RESULT IN RSRC

BEFORE

NB
o

AFTER

(RDST)

000000

(RDST)

000000

(RSRC)

177777

(RSRC)

177777

ZB C4
6
0

C8
0o

N
O

2z
0

V
0

C
O

NB
1

ZB C4
0
0

C8
0

N
1

Z
0

V
0

C
O

THE LSI-11 MICROINSTRUCTION SET

Unconditional

Jump

Microinstruction

Figure

14
|

13
1

0
|

12
T

0
]

11
T

0
1

4-2

]

1/0
1

Format

JUMP ADDRESS
i

MR-1039

THE

ORB

MICROINSTRUCTION

SET

(ORBF)

BYTE

LSI-11

(UPDATE

OPCODE:

CONDITION

OPERATION:

(RA)

<-=-

DESCRIPTION:

The

8-bit

tents

BITS:

CONDITION
(ORBF

CODES:

ONLY)

REG

FIELD

A REG

FIELD

(144400-144777)

contents

unchanged.

STATUS

(1)|

(RB)"OR" (RA)

causes

FLAGS)

144000-144377
1

MICROCYCLES:

CODE

the

and

The

status

condition
byte

placed

are

bit

code

NB:

set

result

ZB:
C4:

set
not

if byte result
affected

C8:

not

affected

ORed

RA.

flags
flags

with

the 8-bit concontent of RB is

The

are
to

updated.

ORBF

updated.

cleared otherwise
cleared otherwise

0 ;

set

the

byte

result

0 0;

cleared

set

the

byte

result

cleared

0 ;7

cleared otherwise

not

otherwise

affected

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

ORBF

RDSTL,RSRCL

;RDSTL"OR"RSRCL,

RESULT

RSRCL

144544
BEFORE

(RDSTL)

AFTER

201

(RDSTL)

(RSRCL) = 176

201

272

IRSRCL) = 377
NB

THE

MICROINSTRUCTION

SET

(ORWF)

ORW

(UPDATE CONDITION CODE FLAGS)

OR WORD

LSI-11

1
~14

o0
13

o0
12

1
11

0
10

1
9

145000-145377

OPERATION:
DESCRIPTION:

(RA+1:RA)
"OR":RB)
(RA+1:RA) <-- (RB+1
are
The 16-bit contents of RB+1:RB

16-bit

contents

are

updated.
are
flags
bit
code flags to be updated.

NB:

ZB:
C4:
C8:

CONDITION CODES: N:
Z:

(ORWF ONLY)

set

set
not
not

if word result

if word result
affected
affected

cleared

not

<
=

0 0;
0 s

The

status

cleared otherwise

cleared otherwise
cleared otherwise

affected

EXAMPLE:

ASSEMBLY MNEMONIC:

ORW RDST,RSRC

ASSEMBLED OCTAL:

145144

;RDST"OR"RSRC, RESULT IN RSRC

BEFORE

AFTER

= 125252

(RDST)

= 125252

" (RSRC)
.= 052525

(RSRC)

= 177777

(RDST)

NB ZB C4 C8
0
0
0
0

N
0

Z
0

the

with

ORed

unchanged.

if the word result = 0;

ORWF causes the condition
'

set if the word result < 0;
set

and placed in RA+1:RA.

RA+1:RA

The contents of RB+1:RB

STATUS BITS:

(145400-145777)

OPCODE:

MICROCYCLES:

A REG FIELD

B REG FIELD

(1)l

V
0

C
O

NB ZB C4 C8
1
0
0
0

N
0

Z
O

V
O

C
O

THE

LSI-11

MICROINSTRUCTION

(UPDATE

CONDITION

SET

(XBF)
EXCLUSIVE-OR

|
]

BYTE

[

(1) |

146000-146377

MICROCYCLES:

OPERATION:

(RA)

<==

DESCRIPTION:

The

8-bit

CONDITION
(XBF

CODES:

ONLY)

FIELD

REG

FIELD

27170

(146400-146777)

(RB)"X-OR"
(RA)

contents

8-bit
of RB

contents
of
is unchanged.

ed.
to be

XBF
causes
updated.

are

EXCLUSIVE-ORed

RA and placed in RA.
The status bit flags

the

condition

NB:

set

byte

result

ZB:

set

byte

result

C4:

not

affected

C8:

not

affected

code

with

The
are

flags,

the

content
updat-

except

BITS:

REG

FLAGS)

cleared

STATUS

OPCODE:

CODE

cleared

set

the

byte

result

cleared

otherwise

set

the

byte

result

cleared

otherwise

cleared

not

affected

XBF

RDSTL,RSRCL

otherwise
otherwise

EXAMPLE:
ASSEMBLY

MNEMONIC:

ASSEMBLED OCTAL:

;RDSTL"X-OR"RSRCL,

RES

RSRCL

146544
BEFORE

AFTER

(RDSTL)

201

(RDSTL)

201

(RSRCL)

201

(RSRCL)

000

NB'ZB
0

C4C8
0

THE

LSI-11 MICROINSTRUCTION

SET

(XWF)

EXCLUSIVE-OR

WORD

'I4

CONDITION

()|

"1I2

OPCODE:
MICROCYCLES:

(UPDATE

"I1

"'I0

l___|
"

CODE

REG

9876

147000-147377

FLAGS)

FIELD

A REG

FIELD

27170

(147400-147777)

OPERATION:

(RA+1:RA)

DESCRIPTION:

The

<--

16-bit

(RB+1:RB)"X-OR" (RA+1:RA)

contents

RB+1:RB

are

EXCLUSIVE

ORed

with
the
16-bit
contents
of RA+1:RA and placed in
RA+1:RA.
The contents of RB+1:RB are unchanged.
The
status
bit flags are updated.
XWF causes the condi-

tion
STATUS

BITS:

CONDITION
(XWF

CODES:

ONLY)

code

flags

NB:
ZB:

set
set

if
if

word
word

C4:
C8:

not
not

affected
affected

result
result

set

the

word

set

the

word

cleared

not

affected

XRW

RDST,RSRC

updated.
<
=

result
result

0;
0;

cleared
cleared

<
=

0;
0;

otherwise
otherwise

cleared

otherwise
otherwise

cleared

EXAMPLE:
ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

;RDST"X-OR"RSRC,

ZB
0

RSRC

147144
BEFORE

NB
0O

RESULT

AFTER

(RDST)

125252

(RSRC)

052525

C4
0

C8
0

N
0

2z
O

V
o0

C
O

NB
0

ZB
1

(RDST)

125252

(RSRC)

000000

C4
0

C8
0

N
0

2z
0

V
0

C
O

THE LSI-11 MICROINSTRUCTION SET

(OCBF)

OCB

ONES

COMPLEMENT BYTE

"14 13

"1Z

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

|l___ |

CONDITION

()|

B REG

l___|I

CODE

FIELD

FLAGS)

1
|

4 -

A REG FIELD

116000-116377 (116400-116777)
1
(RA) <-- (RB)
The ones complement of the 8-bit
content
of
RB
is
placed
in
RA.
The content of RB is unchanged.
The
status bit flags are updated.
OCBF causes the condi-

BITS:

code

flags

NB:
ZB:

set
set

if
if

C4:
C8:

not
not

affected
affected

CONDITION CODES:
(OCBF ONLY)
:

tion

STATUS

(UPDATE

byte
byte

result
result

updated.

<
=

0;
0 :

cleared otherwise
cleared otherwise

N:
Z:

set
set

if the byte result < 0;
if the byte result = 0;

not

affected

cleared

cleared otherwise
cleared otherwise

EXAMPLE:

ASSEMBLY MNEMONIC:

OCB

RDSTL,RSRCL

ASSEMBLED OCTAL:

154144

. ;ONES

COMP OF RDSTL

BEFORE

NB
0o

INTO

AFTER

(RDSTL)

001

(RDSTL)

001

(RSRCL)

000

(RSRCL)

376

ZB
0

C4
0

C8
6

N
60

RSRCL

Z
0

V
0

C
O

NB
1

ZB
0

C4
0

C8
0

N
1

Z
0

V
0

C
O

THE

OCWw

MICROINSTRUCTION

SET

(OCWF)

ONES

LSI-11

COMPLEMENT WORD

(UPDATE

CONDITION

CODE

715 "14 "I3 712 IT TI0 T 9T

(1)l

REG

FIELD

OPCODE:

117000-117377

MICROCYCLES:

OPERATION:

(RA+1:RA) <-- (RB+1:RB)
The ones complement of the

DESCRIPTION:

FLAGS)

A REG

FIELD

473727170

(117400~117777)

1l6-bit

contents

RB+1:RB

are placed in RA+1:RA when B is even.
When B is odd,
the ones complement of the contents of
RB
with
its
high-order
bit extended through 8 high-order bits is
placed in RA+1:RA.
The content
of
RB+1l:RB
is
unchanged.
The
status
bit
flags are updated.
OCWF
causes the condition code flags to be updated.
STATUS

NB:
ZB:

BITS:

CONDITION CODES:
(OCWF ONLY)

set
set

if word
if word

C4:

not

affected

C8:

not

affected

N:
Z:

set
set

not

i1f
if

the
the

result
result

word
word

<
=

0;
0;

cleared
cleared

result
result

<
=

0;
0;

;ONES

COMP

otherwise
otherwise

cleared
cleared

otherwise
otherwise

affected
cleared

EXAMPLE:

ASSEMBLY

MNEMONIC:

OCWF

ASSEMBLED OCTAL:

RDST,RSRC

RDST

ZB
0o

RSRC

157544
BEFORE

NB
6

INTO

AFTER

(RDST)

000001

(RDST)

000001

(RSRC)

000000

(RSRC)

177776

C4
0

C8
0

N
0

z
O

V
O

C
O

NB
l1

ZB
0

C4
0

C8
0

N
1

Z
0

V
0

C
O

THE

TCB

MICROINSTRUCTION

SET

(TCBF)

TWOS

COMPLEMENT

LSI-11

BYTE

(UPDATE

I
I
I
I
I
I
I5 "I4 "I3 12 "IT 10

(l)|

114000-114377

MICROCYCLES:

1
(RA)

<--

DESCRIPTION:

The

twos

I
I
98~

OPCODE:
OPERATION:

CONDITION

REG

CODE

FLAGS)

FIELD

[
I
776

REG

FIELD

|
[
I
I
I
I
5747327170

(114400-114777)

(RB)+1

complement

the

8-bit

content

placed
in
RA.
The content of RB is unchanged.
The
status bit flags are updated.
TCBF causes the condition code flags to be updated.
STATUS

BITS:

NB:

set

byte

ZB:

set

byte

C4:

set
set

if
if

C8:
CONDITION CODES:
(TCBF ONLY)

N:
Z:

set
set

if
if

result

cleared

otherwise

result = 0; cleared otherwise
bit<3> carry out = 1l; cleared otherwise
carry out = 1; cleared otherwise
the
the

byte
byte

result
result

set

arithmetic

set

carry

TCB

RDSTL,RSRCL

out

0;
0;

cleared
cleared

otherwise
otherwise

overflow;

cleared

otherwise

1l;

<
=

cleared

otherwise

EXAMPLE:
ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

;TWO'S

COMP

INTO

RSRCL

134144
BEFORE

AFTER

(RDSTL)

001

(RSRCL)

000

NB ZB C4 C8
0

RDSTL

(RDSTL)

001

(RSRCL)

377

NB ZB C4 C8
1

THE LSI—il MICROINSTRUCTION SET

TCW

(TCWF)

TWO'S COMPLEMENT WORD
|
|

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

(UPDATE CONDITION CODE FLAGS).
0

(1)|

REG

FIELD

REG

115000-115377 (115400-115777)
2
(RA+1:RA) <-- (RB+1:RB)+1
The
two's
complement
of
the
16-bit
RB+1:RB
1is placed in RA+l1:RA when B is

FIELD

contents
even.

When

is odd, the two's complement of the
contents
of
RB
with its high-order bit extended through 8 high-order
bits is placed in RA+1:RA.
The content of RB+1l:RB is
unchanged.

causes
BITS:

CONDITION
(TCWF

CODES:

ONLY)

The
status bit flags
condition code flags to

NB:
ZB:

set
set

if
if

C4:

not

affected

C8:

set

word
word
carry

set if the
set 1if the
cleared

STATUS

the

result
result

<
=

out

1l;

word
word

not

affected

TCW

RDST,RSRC

result
result

0;
0;

are

cleared
cleared

cleared

updated.
updated.

TCWF

otherwise
otherwise

otherwise

cleared

otherwise
otherwise

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

;TWO'S

COMP

RDST

INTO

RSRC

154544
BEFORE

AFTER

(RDST)

000001

(RDST)

000001

(RSRC)

000000

(RSRC)

177777

THE

LSI-1l1

MICROINSTRUCTION

SET

4.3.1.4
Shift Microinstructions - The Shift Microinstruction
g are divided into 8 right shift and 8 left shift operations.
Those shift operations which execute "With Carry" implement 8 or 16 bit shift registers using the C condition code flag as the bit that is shifted in.
The

microinstruction

descriptions

are

follows:

THE LSI--11 MICROINSTRUCTION SET

SLB

(SLBF)

SHIFT

LEFT

BYTE

(UPDATE

l
|
l
I
l
15 714 "I3 712 71T

CONDITION

(1)I

106000-106377
1

OPCODE:

MICROCYCLES:
OPERATION:

(RA)

<-=-

DESCRIPTION:

The

8-bit

CODE

REG

FLAGS)

NB:
ZB:
C4:
C8:

BITS:

CODES:

ONLY)

postion.

causes

the

The

status

condition

set
set
set
set

if
if
if
if

MNEMONIC:

OCTAL:

code

set
set
set
set

if
if
if
if

the byte result < 0; H
the byte result = 0 ;
arithmetic overflo w ;
shifted-off bit = 1 ;

flag

flags

are

flags

receiving

the

SLB

RDSTL,RSRCL

;SHIFT

cleared

otherwise
cleared otherwise

cleared

otherwise

cleared

otherwise

RDSTL

LEFT,

INTO

RSRCL

CARRY

106144
BEFORE

NB
0O

bit

code

byte result < 0; cleared otherwise
byte result = 0; cleared otherwise
bit<3> carry out = 1; cleared otherwise
shifted-off bit = 1; cleared otherwise

s IGNORE

ASSEMBLED

FIELD

(106400-106777)

bit

SLBF

EXAMPLE:
ASSEMBLY

REG

|
I
I
I
I
I
I
I
7657473727170

updated, with the
C condition
high-order shifted-off bit.

(SLBF

2(RB)

low-order

CONDITION

contents of RB are shifted left one bit position
and
placed
in RA.
The content of RB is unchanged.
A
zero
is
1inserted
into
the
vacated

dated.

STATUS

FIELD

AFTER

(RDSTL)

010

(RDSTL)

010

(RSRCL)

000

(RSRCL)

020

ZB
0

C4
0

C8
0

N
0

Z
0

V
0

C
1

NB
0

ZB
0

C4
0

C8
0

N
0

Z
0

V
0

C
O

up-

THE

LSI-11

Conditional

MICROINSTRUCTION

Jump Microinstruction
Figure

14
1

13
I

0
{

12
I

0
|

1
T

}

1
|

SET

4-3

]

CONDITION
1

Format

JUMP ADDRESS
|

l
MR-1086

THE

SLBC

MICROINSTRUCTION

SET

(SLBCF)

SHIFT

LSI-11

LEFT

BYTE

WITH

OPCODE:
MICROCYCLES:

CARRY

(UPDATE

10~

(1)

104000-104377
1

OPERATION:

(RA)

<-=-

DESCRIPTION:

The

8-bit

CONDITION

REG

CODE

FIELD

FLAGS)

A REG

FIELD

left

one

377277170

(104400-104777)

2(RB)+C
contents

are

shifted

bit

po-

sition and placed in RA.
The content of the C condition code flag is placed in the vacated low-order bit
postion.
The content of RB is unchanged.
The status
bit flags are updated.
SLBCF
causes
the
condition
code
STATUS

BITS:

CONDITION

(SLBCF

CODES:

ONLY)

flags

updated.

NB:

set

byte

result

cleared

ZB:

set

byte

result

cleared

C4:
C8:

set
set

if
if

otherwise

otherwise
bit<3> carry out = 1l; cleared otherwise
shifted-off bit = 1; cleared otherwise

set

the

cleared

otherwise

Z:
V:

set
set

if
if

the byte result = 0;
arithmetic overflow;

byte

result

cleared
cleared

otherwise
otherwise

set

shifted-off

cleared

otherwise

bit

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

SLBC

RDSTL,RSRCL

;SHIFT

RDSTL

LEFT,

INTO

RSRCL

104144
BEFORE

AFTER

(RDSTL)

010

(RDSTL)

010

(RSRCL)

000

(RSRCL)

021

THE

SLW

SET

(SLWF)

SHIFT

LSI-11 MICROINSTRUCTION

LEFT

(UPDATE

WORD

CONDITION

I
I
I
I
I
15 12 I3 7127111 T 97

CODE

FLAGS)

(1)|

B REG FIELD

T
|

A REG

FIELD

5473727170

OPCODE:
MICROCYCLES:

107000-107377

OPERATION:
DESCRIPTION:

(RA+1:RA) <-- 2(RB+1:RB)
The 16-bit contents of RB+1:RB

(107400-107777)

are

shifted

1left

one

bit
position
and
placed in RA+1:RA when B is even.
When B is odd, the contents of RB with its high-order
bit
extended
through
8
high-order bits is shifted
left one bit position and
placed
in
RA+1:RA.
The
content
of
RB+1:RB
1is
unchanged.
The status bit
flags are updated.
SLBF causes
the
condition
code
flags
to
be
updated, with the C flag receiving the
high-order shifted-off bit.
STATUS

NB:
ZB:
C4:
C8:

BITS:

N:
Z:
V:
C:

CONDITION CODES:
(SLWF ONLY)

set
set
set
set
set
set
set
set

if word result < 0; cleared otherwise
if word result = 0; cleared otherwise
if bit<3> carry out = 1; cleared otherwise
if shifted-off bit = 1l; cleared otherwise
if
if
if
if

the word result < 0;
the WORD result = 0;
arithmetic overflow;
shifted-off bit = 1;

cleared
cleared
cleared
cleared

otherwise
otherwise
otherwise
otherwise

EXAMPLE:

ASSEMBLY

MNEMONIC:

SLW RDST,RSRC

;SHIFT
; IGNORE

107044

ASSEMBLED OCTAL:

RDST

LEFT,

BEFORE

(RDST)

ZB
0

C4C8
0
0

010000

N
0

RSRC

AFTER

(RDST)

'(RSRC) = 010000
NB
0

INTO

CARRY

Z
0

V
0

010000

(RSRC) = 020000
C
1

NB
0

ZB
0

C4
0

C8
0

N
0

Z
0

V
0

C
O

THE

SLWC

MICROINSTRUCTION

SET

(SLWCF)

SHIFT

LSI-11

LEFT

WORD

WITH

OPCODE:
MICROCYCLES:
OPERATION:

CARRY

(UPDATE

REG

[

FIELD

(105400-105777)

The

the

content

dated.

FLAGS)

REG

NB:

CODES:

ONLY)

flag

The

causes

with

shifted-off
BITS:

code

low-order bit postion.
wunchanged.
The status

SLWCF

updated,

(SLWCF

105000-105377
2
(RA+1:RA) <--

the vacated
RB+1:RB
is

CONDITION

(1) |

CODE

FIELD

2(RB+1:RB)+C
The 16-bit contents of RB+1:RB are shifted
1left
one
bit
position
and
placed in RA+1:RA when B is even.
When B is odd, the contents of RB with its high-order
bit
extended
through
8 high-order bit positions is
shifted left one bit position and placed in
RA+1:RA.

DESCRIPTION:

STATUS

CONDITION

the

condition

the

condition

flag

bit
code

receiving

placed

content
flags
flags

the

are
to

ZB:

set
set

if
if

word
word

C4:
C8:

set
set

if
if

bit<3> carry out = 1l; cleared otherwise
shifted-off bit = 1l; cleared otherwise

set

the

word
the word

set

1if

arithmetic

set

shifted-off

<
=

result

0;
0;

cleared
cleared

cleared

otherwise

overflow;

cleared

otherwise

cleared

otherwise

bit

<
=

otherwise
otherwise

result

otherwise

EXAMPLE:
ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

SLWC

RDST,RSRC

;SHIFT

RDST

LEFT,

INTO

RSRC

105144
BEFORE

upbe

high-order

bit.
result
result

AFTER

(RDST)

010000

(RDST)

010000

(RSRC)

010000

(RSRC)

020001

THE

SHIFT RIGHT

SET

(SRBF)

SRB

LSI-11 MICROINSTRUCTION

BYTE

(UPDATE

“15 "I4 "I3 712 IT "I0

(1)|

FLAGS)

B REG FIELD

A REG FIELD

7654

I
27170

156000-156377 (156400-156777)
1
(RA) <-- (RB)/2
The 8-bit contents of RB are shifted

OPCODE:

MICROCYCLES:
OPERATION:
DESCRIPTION:

STATUS

CONDITION CODE

right
one
bit
position
and placed in RA.
The content of RB is unchanged.
The status bit
flags
are
updated.
SRBF
causes
the
condition code flags to be updated, with

BITS:

CONDITION CODES:
(SRBF ONLY)

the

flag

NB:
ZB:
C4:
C8:

set
set
not
set

receiving

the

if byte result
if byte result
affected
if shifted-off

low-order

<
=

0;
0;

cleared
cleared

shifted-off

bit.

otherwise
otherwise

bit
= 1;

cleared

otherwise

set

the

byte

result

cleared

Z::

set

the

byte

result

not

affected

cleared otherwise

set

1l;

SRB

RDSTH,RSRCH

shifted-off

bit

otherwise

cleared

otherwise

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED OCTAL:

;SHIFT
; IGNORE

RDSTH
CARRY

RIGHT,

RSRCH

156165
BEFORE

NB
0

INTO

AFTER

(RDSTH)

010

(RDSTH)

010

(RSRCH)

000

(RSRCH)

004

ZB
0

C4
0

C8
0

N
0

Z
O

V
o0

C
1

NB
0

ZB
0

C4
0

C8
0

N
O

Z
0

V
o0

C
1

SRBC

LSI-11

BYTE

WITH

CARRY

MICROINSTRUCTION

SET

(SRBCF)

SHIFT

THE

RIGHT

(UPDATE

I
I
I
|
I
I
15 7124 713 712 1T "I0

(1)

I
|
98~

CONDITION

REG

FIELD

776

CODE

FLAGS)

A REG

FIELD

574773727170

154000-154377 (154400-154777)
1
(RA) <-- (C:(RB))/2
The 8-bit contents of RB are shifted

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

position and placed
dition code flag is
bit

postion.

right
one
bit
The content of the C conin the vacated
high-order

in RA.
placed

The

content

unchanged.

The

status bit flags are updated.
SRBCF causes the
condition
code flags to be updated, with the C flag receiving the low-order shifted-off bit.
STATUS

BITS:

CONDITION
(SRBCF

CODES:

ONLY)

NB:

set

result

cleared

otherwise

ZB:
C4:
C8:

set
not
set

if byte result
affected
if shifted-off

byte

cleared

otherwise

bit

cleared

otherwise

set

the

byte

result

otherwise

set

the

byte

result

0;
0;

cleared

otherwise

not

affected

set

cleared

otherwise

shifted-off

bit

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

SRBC

RDSTL,RSRCL

;SHIFT

RDSTL

RIGHT,

INTO

RSRCL

154144
BEFORE

AFTER

(RDSTL)

010

(RDSTL)

010

(RSRCL)

000

(RSRCL)

204

THE LSI~11 MICROINSTRUCTION SET

SRW

(SRWF)

SHIFT

RIGHT

WORD

"14

"13

(UPDATE

"12

"1I1

CONDITION

(1)]

OPCODE:

157000-157377

MICROCYCLES:

OPERATION:

(RA+1:RA)

DESCRIPTION:

The

<--

16-bit

B REG

CODE

]

FLAGS)

FIELD

REG

FIELD

(157400-157777)
(RB+1:RB)/2

contents

RB+1:RB

are

shifted

bit
position
and placed in RA+l1:RA.
RB+1:RB is unchanged.
The status bit

right

one

The content of
flags
are
up-

dated.

SRWF
causes
the condition code flags to be
updated, with the
C
flag
receiving
the
low-order
shifted-off
bit.
A
and
B
must both be odd since
shifting starts with the left byte.

BITS:

CONDITION CODES:
(SRWF ONLY)

NB:
ZB:
C4:

set
set
not

if word result
if word result
affected

<
=

C8:

set

bit

shifted-off

N:
Z:

set
set

if
if

the
the

word
word

not

affected

set

result
result

shifted-off

0;
0;

cleared
cleared

=
N

STATUS

bit

otherwise
otherwise

cleared

otherwise

0;
0;

cleared
cleared

otherwise
otherwise

cleared

otherwise

EXAMPLE:

ASSEMBLY

MNEMONIC:

SRWF

RDSTH,RSRCH

;SHIFT
s IGNORE

ASSEMBLED OCTAL:

RDST

RIGHT,

AFTER

(RDST)

000001

(RDST)

000001

(RSRC)

000000

(RSRC)

000000

C8
0

N
0

2z
0

V
0

C
1

C4
0

ZB
0

RSRC

157565
BEFORE

NB
0O

INTO

CARRY

NB
o

ZB
1

C4
0

C8
0

N
O

2
1

V
o0

C
1

THE

SRWC

SET

(SRWCF)

SHIFT

LSI-11 MICROINSTRUCTION

RIGHT

WORD

WITH

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

CARRY

(UPDATE

(1)

CONDITION

REG

FIELD

bit
position
and placed
the C condition code flag
high-order
bit
postion.

in
is

155000~-155377 (155400-155777)
2
(RA+1:RA) <-- (C:(RB+1:RB))/2
The 16-bit contents of RB+1:RB

CODE

are

FLAGS)

A REG

FIELD

shifted

right

one

RA+1:RA.
The content of
placed
in
the
vacated
The content of RB+1:RB is

unchanged.

The status bit flags are updated.
SRWCF
causes
the
<condition code flags to be updated, with
the C flag receiving the low-order
shifted-off
bit.
A

STATUS

BITS:

CONDITION

(SRWCF

CODES:

ONLY)

and

must

both

the

left

NB:
ZB:

set
set

if
if

C4:
C8:

not
set

affected
if shifted-off

odd

since

shifting

starts

with

byte.
word
word

N:
Z:

set
set

1f
if

the
the

not

affected

set

result
result

word
word

<
=

bit

result
result

shifted-off

0 ;i
0;

bit

cleared otherwise
cleared otherwise
=

cleared

otherwise

0;
0;

cleared
cleared

otherwise
otherwise

1l;

cleared

otherwise

EXAMPLE:
ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

SRWC

RDSTH,RSRCH

;SHIFT

RDST

RIGHT,

INTO

RSRC

155144
BEFORE

AFTER

(RDST)

000001

(RDST)

000001

(RSRC)

000000

(RSRC)

100000

THE

LSI-1l1 MICROINSTRUCTION

SET

4.3.1.5
Arithmetic Microinstructions - The
Arithmetic
Microinstructions consist mainly of operations which either add or subtract values
expressed in twos complement representation.
One microinstruction facilitates decimal arithmetic (CAD).

The

microinstruction

descriptions

are

follows:

THE

LSI-11 MICROINSTRUCTION SET

ADD

LITERAL

o0
714

1
13

"12

"Io0

LITERAL FIELD
9

A REG FIELD
3

02XXXX
1
(RA) <=--

OPCODE:
MICROCYCLES:
OPERATION:

(RA)+(LITERAL FIELD)
The 8-bit contents of the
literal
field,
MI<K1ll:4>,
are added to the 8~bit contents of RA and loaded into
register RA.
The NB, ZB, C4, and C8 status bit flags
are
updated.
The contents of the literal field are

DESCRIPTION:

STATUS BITS:

not

changed.

NB:

set if byte result < 0;

ZB:
C4:
C8:

CONDITION CODES:

set
set
set
not

affected

ASSEMBLY MNEMONIC:

200,RBAL

ASSEMBLED OCTAL:

024202

:
:

not
not
not

cleared otherwise

if byte result = 0; cleared otherwise
if bit<3> carry out = 1l; cleared otherwise
if carry out = 1; cleared otherwise

affected
affected
affected

EXAMPLE:

;ADD 200 TO RBAL

AFTER

ZB C4
0
0

C8
0o

N
0

2
O

NB
0

(RBAL)

= 210
o<

(RBAL)

NB
o

ZB
0

C4
0

C8
1

= 020
N
0

Z
0

V
O

BEFORE

THE

LSI-11 MICROINSTRUCTION

SET

(ABF)

ADD

BYTE

(UPDATE

"14

CONDITION

12 11 710

OPCODE:
MICROCYCLES:

FLAGS)

CODE

(1)I

REG

OPERATION:

120000-120377 (120400-120777)
1
(RA)
<=-= (RB)+(RA)

DESCRIPTION:

The

STATUS

BITS:

CONDITION
(ABF

CODES:

ONLY)

sum

the

8-bit

FIELD

contents

A REG

and

FIELD

are

placed

in
RA.
The content of RB
bit flags are updated.
ABF
flags to be updated.

is unchanged.
The status
causes the condition code

NB:

set

byte

cleared

ZB:

set

byte

C4:
C8:

set
set

if
if

carry

result

otherwise

result = 0;
bit<3> carry out

out

cleared otherwise
= 1; cleared otherwise
cleared otherwise

set

the

word

result

cleared

otherwise

set

the

word

result

cleared

V:
C:

set
set

if
if

arithmetic overflow; cleared otherwise
carry out = 1; cleared otherwise

otherwise

ABF

RDSTL,RSRCL

EXAMPLE
:
ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

;ADD

RDSTL

RSRCL,

RSRCL

160544

BEFORE

NB
0

RES

AFTER

(RDSTL)

001

(RDSTL)

001

(RSRCL)

001

(RSRCL)

002

ZB
0

C4C8
0
0

N
0

Z
O

NBZBC4C8

THE

4,2.3

Literal

LSI-11

MICROINSTRUCTION

Microinstruction

SET

Format

The Literal Microinstruction Format is shown in Figure 4.4.
These microinstructions
provide
8-bit
<constants in the microprogram.
There
are 5 microinsructions in this
group
and
the
octal
opcode
values
(MI<15:12>)
in
the
range
02
to
06.
An
8-bit
literal
field,
(MI<11l:3>), is one operand.
The other operand is specified by
the
A

Register
Field (MI<3:0>) which supports direct or indirect addressing
of any 8-bit byte register through the A Read/Write port.
All literal
format microinstructions require 1 microcycle for execution.

4.2.4

Most of the LSI-1l microinstructions belong to the
Register
Microinstruction Format which is illustrated in Figure 4-5.
The opcode field
occupies 8 bits, MI<K15:8>, and opcode
values
range
from
07
to
37
(octal).
Most
register format microinstructions unconditionally update the status bit flags relevant to the particular
operation.
The
condition code flags are selectively updated by opcode choice, the odd
opcode value (in general) affecting the condition code flags in
addition to the status bit flags.

4.2.4.1
Byte and Word Microinstructions - All register format
microinstructions
belonging
to
the data manipulation and the data access
classifications
are
either
byte
or
word
microinstructions.
The

byte/word distinction is a direct consequence of the fact that the re-

gister file access ports are 8-bits wide.
This 8-bit
width
1is
also
shared
by
the
ALU
inputs and output.
A data manipulation microinstruction which produces a single 8-bit byte as its result can be completed in one microcycle.
An example is the Add Byte microinstruction
which forms the binary addition of the bytes addressed by the B and
A
register
fields
and
places the result in the register designated by
the A field.
The microprocessor Data chip simultaneously presents the
two
8-bit
operands
to
the ALU and restructures the A register port
path to load the ALU output when the result is formed.
In the case of a word microinstruction, the 8-bit
register
port
and
ALU
width
requires a 2-microcycle sequence to complete processing of
16-bit word

operands.

Carry or

borrow

information which

needs

transmitted
between
byte
operations is stored in the ALU status bit
flags.
The ALU status bit flags are unconditionally updated
by
each
byte
operation.
The
Add
Word
microinstruction
1is
the
16-bit,

2-microcycle counterpart of the Add Byte microinstruction.
Since
the
B
and A register fields of the microinstructions each point to a single 8-bit byte within the register file, special techniques
are
used
to form the 16-bit operands for word microinstructions.
These techniques are explained in the next section.

There

are

several

microinstructions which

produce

a word

operand

but

still
fall
1into
the
byte classification.
This is because the Data
chip organization allows the required 16-bit path to be simultaneously
formed
from
two
8-bit paths.
An example is the Write microinstruction, which is able to simultaneously present the contents of two
independently
specified registers to the data address buffers, and thus
to

the WDAL

Data chip

outputs.

THE

MICROINSTRUCTION

SET

(ABCF)

ABC

ADD BYTE

LSI-11

WITH

CARRY

(UPDATE

CONDITION

(1)]

CODE

B REG

FLAGS)

FIELD

A REG

FIELD

OPCODE:
MICROCYCLES:

124000-124377
1

OPERATION:

(RA) <-=- (RB)+(RA)+C
The sum of the 8-bit

contents

placed
status

content of RB is unchanged.
The
updated.
ABCF causes the condi-

DESCRIPTION:

tion

STATUS

BITS:

CONDITION CODES:
ABCF (ONLY)

in
bit

code

(124400-124777)

RA.
The
flags are
flags

set
set
set

if
if
if

byte result < 0;
byte result = 0;
bit<3> carry out

C8:

set

carry

N:
Z:
V:
C:

set
set
set
set

if
if
1f
if

out

and

plus

are

1l;

cleared otherwise
cleared otherwise
= 1l; cleared otherwise

cleared

the word result < 0;
the word result = 0;
arithmetic overflow;
carry

updated.

NB:
ZB:
C4:

out

otherwise

cleared
cleared
cleared

cleared

otherwise
otherwise
otherwise

otherwise

EXAMPLE:

MNEMONIC:

ABCF

ASSEMBLED OCTAL:

RDSTL,RSRCL

;ADD

RDSTL

BEFORE

(RDSTL)

NB
0

RSRCL,

RES

RSRCL

V
0

C
o

164544

001

(RDSTL)

(RSRCL)
= 001

(RSRCL)

= 003

ZB
0

C4
0

C8
0

AFTER

N
O

2Z
0

V
o0

-0

ASSEMBLY

NB
0

ZB
0

C4
0

C8
0o

001

N
60

Z
0

THE

CAB

SET

(CABF)

CONDITIONALLY

LSI-11] MICROINSTRUCTION

ADD

BYTE

(UPDATE

I
|
I
I
I
I
“I5 714 I3 712 71T 10T

(1)|

DESCRIPTION:

l, the
remain

REG

FIELD

6°

add operation will
unchanged.
The

The status bit
condition code

STATUS BITS:

(CABF

CODE

122000-122377 (122400-122777)
1
(RA) <-- (RB)+(RA), IF C =1
The sum of the 8-bit contents
in
RA, if the C flag is a 1.

OPCODE:
MICROCYCLES:
OPERATION:

CONDITION

NB:
ZB:
C4:
C8:
N:
Z:
V:
C:

CODES:

ONLY)

set
set
set
set

if
if
if
if

flags
flags

FLAGS)

1
|

A REG

FIELD

473727170

of RB and
If the C

RA are placed
flag is not a

not take place and RA
will
content of RB is unchanged.

are updated.
to be updated.

CABF

causes

the

byte result < 0; cleared otherwise
byte result = 0; cleared otherwise
bit<3> carry out = 1; cleared otherwise
carry out = 1l; cleared otherwise

set
set
set
set

if
if
if
if

the word result < 0; cleared otherwise
the word result = 0; cleared otherwise
arithmetic overflow; cleared otherwise
carry out = 1; cleared otherwise

CAB

RDSTL,RSRCL

EXAMPLE:
ASSEMBLY

MNEMONIC:

ASSEMBLED OCTAL:

;ADD

RDSTL

; (IF

RSRCL,

PREVIOUSLY

RES

RSRCL

SET)

162144
BEFORE

AFTER

(RDSTL)

001

(RDSTL)

001

(RSRCL)

001

(RSRCL)

001

THE

LSI-11 MICROINSTRUCTION

SET

(AWF)
ADD

WORD

[

(UPDATE

"13

CONDITION

"11

(l)I

[

FLAGS)

B REG

FIELD

A REG

FIELD

121000-121377 (121400-121777)
2
(RA+1:RA) <-- (RB+1:RB)+(RA+1:RA)
The sum of the l6-bit contents of

OPCODE:
MICROCYCLES:
OPERATION:

RB+1:RB and RA+1:RA
is
placed in RA+1:RA when B is even.
When B is odd,
the sum of the contents of RB with its high order bit
extended
through
8 high order bits and the contents
of RA+1:RA is placed
1in
RA+1:RA.
The
content
of

DESCRIPTION:

RB+1:RB

dated.
dated.
STATUS

CODE

BITS:

CONDITION CODES:
(AWF ONLY)

NB:

set

ZB:
C4:
C8:

set
set
set

is
AWF

unchanged.
The status bit flags are
causes the condition code flags to be

word result < 0; cleared otherwise
if word result = 0; cleared otherwise
1f bit<3> carry out = 1; cleared otherwise
if carry out = 1l; cleared otherwise

set

the

Z:
V:
C:

set
set
set

1f
1f
if

the word result = 0; cleared otherwise
arithmetic overflow; cleared otherwise
carry out = 1l; cleared otherwise

word

result

cleared

otherwise

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED OCTAL:

RDST,RSRC

;ADD

RDST

RSRC,

ZB
0

RSRC

161144
BEFORE

NB
0

SUM

AFTER

(RDST)

000377

(RDST)

000377

(RSRC)

000001

(RSRC)

000400

C4
0

C8
0

N
0

zZ
0

V
0

C
O

NB
0

ZB
0

C4
1

C8
1

N
0

2
0

V
0

C
0

up-

THE

AWC

MICROINSTRUCTION

SET

(AWCF)

ADD

LSI-11l

WORD

WITH

CARRY

(UPDATE

OPCODE:

I
I
[
I
|
l
15714 TI3TIZTITTI0O

(1)

l
I
98

125000-125377
2

MICROCYCLES:
OPERATION:

CONDITION

B REG

CODE

FIELD

FLAGS)

|
|

A REG

FIELD

765433710

(125400-125777)

(RA+1:RA) <-- (RB+1:RB)+(RA+1:RA)+C
The sum of the 16-bit contents of RB+1:RB and
plus
C
1is placed in RA+1:RA when B is even.

DESCRIPTION:

odd,

the

sum of

the

contents

of RB with

RA+1:RA
When B

its

order
bit
extended
through
8
high order bits
RA+1:RA plus C is placed in RA+1:RA.
The content

RB+1:RB

dated.

AWCF

unchanged.

causes

The status bit
condition code

the

updated.
STATUS

BITS:

are
to

NB:

set

word

result

ZB:

set

cleared

word

otherwise

result

C4:
C8:

set
set

if
if

cleared

bit<3> carry out = 1; cleared otherwise
carry out = 1; cleared otherwise

otherwise

CONDITION

(AWCF

Z:
V:

CODES:
ONLY)

flags
flags

set
set
set
set

if
if
if
if

the word result < 0; cleared otherwise
the word result = 0; cleared otherwise
arithmetic overflow; cleared otherwise
carry out = 1; cleared otherwise

EXAMPLE:
ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

AWCF

RDST,RSRC

;ADD

RDST

RSRC,

SUM

RSRC

165544
BEFORE

AFTER

(RDST)

000377

(RDST)

000377

(RSRC)

000001

(RSRC)

000401

NB ZB C4 C8
0

high

NB ZBC4C8
0

and
.of
up-

THE LSI-11 MICROINSTRUCTION SET

(CAWF)

CAW

CONDITIONALLY ADD WORD
|

(UPDATE CONDITION CODE FLAGS)

|
I
I
15 714 I3 I2°IT I

9°"

123000-123377

OPCODE:
MICROCYCLES:

()|

B REG FIELD

1
|

A REG FIELD

I
I
10

I
I
|
I
I
|
76 547372

(123400-123777)

(RA+1:RA) <-- (RB+1:RB)+(RA+1:RA), IF C=1
The sum of the 16-bit contents of RB+1:RB and RA+1:RA
is
placed in RA+1:RA when B is even.
When B is odd,
the sum of the contents of RB with its high order bit
extended
through
8
high
order bits and RA+1:RA is
1.
is
flag
placed in RA+1:RA if the value of the C

OPERATION:

DESCRIPTION:

The contents

of RB+1:RB

remain unchanged.

The

status

bit flags are updated.
CAWF
causes
the
condition
code
flags
to
be
updated.
If the C flag is not a
one, the add operation will not
take
place
and
no
flag or register contents will be changed.

STATUS

NB:
ZB:

BITS:

C4:
C8:

set
set

cleared otherwise
cleared otherwise
set if bit<3> carry out = 1l; cleared otherwise
set if carry out = 1l; cleared otherwise

: set
: set
: set
set

CONDITION CODES:
(CAWF ONLY)

if word result < 0;
if word result = 0;

if
if
if
if

the word result < 0; cleared otherwise
the word result = 0; cleared otherwise
arithmetic overflow; cleared otherwise
carry out = 1l; cleared otherwise

EXAMPLE:

ASSEMBLY MNEMONIC:

CAW RDST,RSRC

ASSEMBLED OCTAL:

163144

;ADD RDST TO RSRC,
; (IF

BEFORE

NB
0o

SUM IN RSRC

PREVIOUSLY SET)

AFTER

(RDST)

000377

(RDST)

000377

(RSRC)

000001

(RSRC)

000001

ZBC4C8
0
0
0

N
0

2
0

V
0

C
0

NB ZBC4C8
0
0
1
1

N
0

2
0

V
0

C
0

THE

CAWI

LSI-11l

SET

(CAWIF)

CONDITIONALLY ADD WORD

MICROINSTRUCTION

"14

"12

ICC

"1I1

(UPDATE

710

CODE

FIELD

A REG

(1)|

REG

OPCODE:
MICROCYCLES:
OPERATION:

127000-127377
2

(127400-127777)

(RA+1:RA)

DESCRIPTION:

(RB+1:RB)+(RA+1:RA),

The

sum

<--

FLAGS)

CONDITION

the

16-bit

contents

FIELD

IF ICC
RB+1:RB

=1
and

RA+1:RA

is
placed
in RA+1:RA
if the ICS flag is a 1, when B
is even.
When B is odd,the sum of the.contents of RB
with its high order bit extended through 8 high order
bits and RA+1:RA is placed in RA+1:RA if the ICS flag
is
a
1.
The contents of RB+1:RB remain unchanged.

The

STATUS

BITS:

CONDITION

(CAWIF

CODES:

ONLY)

status

bit

flags

condition code

flags

not

flag

NB:

set

ZB:

set

if
if
if
if

one,

C4:

set

C8:

set

are

updated.

CAWIF
causes
updated.
If the C flag
the add operation will not take place
register contents will be changed.

word

result

word

result

cleared otherwise
cleared otherwise
bit<3> carry out
1; cleared otherwise
carry out
1; cleared otherwise

if the word result < 0; cleared otherwise
if the word result
0; cleared otherwise
if arithmetic overflow; cleared otherwise
if carry out
1l; cleared otherwise

EXAMPLE:
ASSEMBLY

ASSEMBLED

MNEMONIC:

CAWIF

OCTAL:

RDST,RSRC

RDST

; (IF

ICC

167544
BEFORE

;ADD

ICC

RSRC,

SUM

PREVIOUSLY

RSRC

SET)

AFTER

(RDST)

177777

(RDST)

177777

(RSRC)

000001

(RSRC)

000001

C4C8

zZB

THE LSI-11 MICROINSTRUCTION SET

CAD

CONDINTIONALLY ADD DIGITS

I
I
I
15 714 I3 71211 1o
I

I
I
98

OPCODE:

126000-126377

MICROCYCLES:

DESCRIPTION:

NB:
ZB:
C4:
C8:

BITS:

CONDITION

BREG FIELD

A REG FIELD

(RA<3:0>) <-- (RB<3:0>)+(RA<3:0>), IF C4 = 0,
(RA<7:4>) <-=- (RB<7:4>)+(RA<7:4>), IF C8 = 0
This microinstruction divides the designated register
operands
1into
two digits of 4 bits each, bits <7:4>
and bits <3:0>.
Status bit flag C4 must be 0 for the
lower
digit
to
add and C8 must be 0 for the higher
digit to add.
The contents of RB are unchanged.
The
status
bit
flags are updated in all cases.
A carry
out of bit position 3
will
not
effect
the
higher
digit.

OPERATION:

STATUS

CODES:

set
set
set
set

if byte result < 0; cleared otherwise
if byte result = 0; cleared otherwise
if bit<3> carry out = 1; cleared otherwise
if carry out = 1l; cleared otherwise

set

Z:
V:
C:

set
set
set

if the byte result = 0; cleared otherwise
if arithmetic overflow; cleared otherwise
if carry out = 1; cleared otherwise

the

byte

result

cleared

otherwise

EXAMPLE:

ASSEMBLY MNEMONIC:

CAD RDSTL,RSRCL

ASSEMBLED OCTAL:

166144
BEFORE

NB
0o

;ADD RDSTL TO RSRCL,
;DIGIT

SUM(S)

‘

RSRCL

AFTER

(RDSTL)

021

(RDSTL)

021

(RSRCL)

021

(RSRC)

041

ZB C4
0
0

C8
1

N
0

Z2
0

V
0

C
O

NB
o

ZB
0

C4
0

C8
0

N
0

Z
0

V
0

C
O

THE

LSI-1l MICROINSTRUCTION

SET

(SBF)

SUBTRACT

BYTE

"14 "1I3

(SN D

(UPDATE

DY PR

712

OPCODE:

711

CONDITION

~10

(1)

130000-130377
1

MICROCYCLES:

OPERATION:
DESCRIPTION:
_

FLAGS)

B REG

FIELD

]

|
|

A REG

BITS:

CONDITION
(SBF

CODES:

ONLY)

(RA)

<--

(RA)-(RB)

8-bit

contents

are

and

placed

subtracted
in

RA.

from

The

updatupdat-

NB:

set

byte

ZB:

set

result

byte

C4:
C8:

result

set
set

if
if

bit<3> carry out = 1; cleared otherwise
carry out = 1; cleared otherwise

set

Z2:

set

C:set

the

word result < 0;
word result = 0;
arithmetic overflow;

there

borrow;

otherwise
otherwise

cleared
cleared

the

cleared
cleared

cleared

otherwise
otherwise
otherwise

otherwise

EXAMPLE:

ASSEMBLY

ASSEMBLED

MNEMONIC:

OCTAL:

RDSTL,RSRCL

;SUB

RDSTL

;DIF

FROM

170164
AFTER

(RDSTL)

377

(RDSTL)

377

(RSRCL)

377

(RSRCL)

000

NB ZBCAC8
0

RSRCL,

RSRCL

BEFORE

N
0

V
0

C
0

NB ZBC4C8
0

N
0

the

contents

of RB are unchanged.
The status bit flags are
ed.
SBF causes the condition code flags to
be
ed.
STATUS

FIELD

(130400-130777)

The

8-bit

CODE

V
0

C
0

THE LSI-11 MICROINSTRUCTION SET

(SBCF)

SBC

(UPDATE CONDITION CODE FLAGS)

SUBTRACT BYTE WITH CARRY

| 1

0
~14

1
13

1
12

1
"1IT1

0
10

0
9

(1)]
8

|
|

B REG FIELD
i

A REG FIELD
3

(134400-134777)

OPCODE:

134000~134377

DESCRIPTION:

subare
flag
The 8-bit contents of RB minus the C
the 8-bit contents of RA and placed in
from
tracted

MICROCYCLES:
OPERATION:

1
(RA)

<--

RA.

The contents of RB are

code

flags

bit

(RA)-(RB)-C

flags

are

updated.

unchanged.

The

status

SBCF causes the condition

to be updated.

NB: set if byte result < 0; cleared otherwise

STATUS BITS:

ZB:
C4:
C8:

set if byte result = 0; cleared otherwise
set if bit<3> carry out = 1; cleared otherwise
set if carry out = 1l; cleared otherwise

CONDITION CODES: N: set if the word result < 0; cleared otherwise
Z: set if the word result = 0; cleared otherwise
(SBCF ONLY)
V:
C:

set if arithmetic overflow; cleared otherwise
set if there is a borrow; cleared otherwise

EXAMPLE:

ASSEMBLY MNEMONIC:

SBCF RDSTL,RSRCL

ASSEMBLED OCTAL:

134544

;SUB RDSTL, CARRY FROM
;RSRCL,

(RDSTL)

= 377

(RSRCL)

= 002
N
0

RSRCL

AFTER

BEFORE

NB ZB C4 C8
0O
0
0
0

DIF

Z
0

:
V
0

C
1

(RDSTL)

= 377

(RSRCL)

= 374

NB ZB C4 C8
O
0
0
0

N
0

Z
0

V
0

C
O

THE

LSI-]11l

MICROINSTRUCTION

SET

(SWF)

SUBTRACT

I
|

1
15

WORD

"14

(UPDATE

"13 "12 "I1

OPCODE:

CONDITION

710

(1)|

131000-131377

MICROCYCLES:

REG

FIELD

776

the

16-bit

when

content

CONDITION CODES:
(SWF ONLY)

FIELD

1°0

contents

even.

When

flags

are

flags

RB+1:RB

updated.
be

subtracted

of RA+1:RA and placed
is

with its high order bit
subtracted from RA+1:RA

BITS:

REG

" 3

(RA+1:RA) <-- (RA+1:RA) - (RB+1:RB)
The 16-bit contents of RB+1:RB
are

DESCRIPTION:

STATUS

FLAGS)

(131400-131777)

OPERATION:

CODE

odd,

the

extended 8
and placed

1is

SWF

contents

updated.

The

the

status

condition

ASSEMBLED

NB:

set

word

ZB:

result

set

word

cleared

C4:
C8:

result

set
set

if
if

cleared

bit<3> carry out = 1; cleared otherwise
carry out = 1l; cleared otherwise

set

if there

RDST,RSRC

MNEMONIC:

OCTAL:

the

word result < 0;
word result = 0;
arithmetic overflow;

cleared

the

is a borrow;

otherwise
otherwise

cleared

otherwise
otherwise

cleared

otherwise

cleared otherwise

;SUB

RDST

;DIF

FROM

RSRC,

RSRC

131144

bit

code

EXAMPLE:

ASSEMBLY

high order bits is
in
RA+1:RA.
The

unchanged.

causes

from

in RA+1:RA

BEFORE

AFTER

(RDST) = 000001

(RDST) = 006001

(RSRC)

000000

177777

0-0

THE

LSI-11

Literal

MICROINSTRUCTION

Microinstruction
Figure

12
r

Format

4-4

OP CODE
L

SET

LITERAL FIELD
i

]

A REGISTER
|

]

L
MR 1040

THE LSI-11 MICROINSTRUCTION SET

SWC

(SWCF)

(UPDATE CONDITION CODE FLAGS)

SUBTRAC WORD WITH CARRY

15 14 I3 121110

1
"9

135000-135377

OPCODE:
MICROCYCLES:

|
|

B REG FIELD

(1)|!

A REG FIELD
1

[

(135400-135777)

(RA+1:RA) <-- (RA+1:RA)-(RB+1:RB)-C
The 16-bit contents of RB+1:RB minus the value of the

OPERATION:

DESCRIPTION:

C flag subtracted from the 16-bit contents of RA+1:RA
is
B
When
even.
is
and placed in RA+1:RA when B
odd,the contents of RB with its high order bits minus
from RA+1:RA
subtracted
the value of the C flag is
The content of RB+1:RB is unand placed in RA+1:RA.
SWCF
updated.
are
flags
The status bit
changed.
causes the condition code flags to be updated.

STATUS

NB:
ZB:
C4:
C8:

BITS:

CONDITION CODES:
(SWCF ONLY)

N:
Z:
V:
C:

set if word result < 0; cleared otherwise
set if word result = 0; cleared otherwise
set if bit<3> carry out = 1l; cleared otherwise
set if carry out = 1; cleared otherwise
set if the word result < 0; cleared otherwise
set if the word result = 0; cleared otherwise
set if arithmetic overflow; cleared otherwise
set if there is a borrow; cleared otherwise

EXAMPLE:

ASSEMBLY MNEMONIC:

SWC RDST,RSRC

ASSEMBLED OCTAL:

135144

;SUB RDST, CARRY FROM RSRC,
;RESULT

RSRC

AFTER

BEFORE

(RDST)

= 000001

(RDST)

= 000001

(RSRC)

= 000000

(RSRC)

= 177776

NB ZB C4 C8

NB zZB C4 C8

THE

4.3.2
The

Data Access

LSI-11 MICROINSTRUCTION

SET

Microinstructions

provide

the

(DATI)

only

means

for

transfer-

ring
data
into or out.of the micromachine.
The 16-bit transfer path
is formed by the microprocessor Data chip WDAL connections
which
are
bidirectionally
buffered
to
the
16
LSI-11
system bus lines, BDAL
<15:00>.

The

LSI-11

machine

input

operation

croinstruction
followed
machine output operation

implemented

Read

mi-

by an Input microinstruction.
Similarly,
(DATO) is implemented by a
Write-Output

the
sequence
of microinstructions.
These two basic sequences are available
in
seveval
variations
to
accomodate
Byte
transfers
(DATOB)
and
read-modify
write
operations (DATIO,
DATIOB).
Further variations
allow for special handling of interrupt transactions.
It is the data access group of microinstructions (only) which activate
the
microprocessor
control chip I/0 control signal lines.
The lines
which carry control information to the
LSI-11
system
bus
1interface
logic
are WSYNC, WWB, WDIN, WDOUT, and WIACK.
The REPLY and BUSY in-

puts to the Control chip are monitored during a data access operation.
The
1logic circuitry which interfaces these signals to the LSI-11 system bus is discussed in The Microcomputer Handbook.

These microinstructions are
Input,
Write
and
Output.

presented

4.3.2.1

sists

in Chapter

Read

address

organized

Further

Microinstructions
- The

6 microinstructions,

the

data

address

all

lines.

four

basic

sequencing

Read

timing

place

facilitate

Read,

details

are

group

con-

Microinstruction

of which
To

families

and

system bus

sequential

device

address-

ing, four microinstructions automatically increment the registers containing the address arguments.
Because the A and B register ports may
be
read
simultaneously,
all
read
microinstructions place both the
upper

time.

and

lower

All

address word

Byte

the

device

Read microinstructions
execute

one

address

BDAL

<15:00>

except

for

those

which

microcycle.

However,

before

the

same

increment
execution

an
is

initiated, the control chip checks REPLY H and BUSY H at PH3 to verify
that no other system bus operations are still in progress.
Because of
the requirment to check REPLY H and BUSY H during PH3, the address information is not placed on the bus until the following microcycle.
The address information is placed on WDAL <15:00> during
PH1l
cancelled at the end of PH4, thus making the address valid for
crocycle.
All read microinstructions assert WSYNC during PH2

microcycle

which

the

address

becomes

valid.

and

one

mi-

the

The Read Acknowledge

(RA) microinstruction asserts WIACK simultaneously with WSYNC.
1In all
cases WDIN is asserted during the PH4 which follows removal of the address data.
None of the read group microinstructions effect the
condition code flags.
The

microinstruction

descriptions

are

follows:

THE LSI-11 MICROINSTRUCTION SET

READ

OPCODE:
MICROCYCLES:

710

B REG FIELD

A REG FIELD

174000~-174377
1 (MIN)

OPERATION:

(DAL)

DESCRIPTION:

The 16-bit contents of RB:RA are placed on the system
bus
as
a system bus address.
The contents of RB:RA
are unchanged and the flags are unaffected.
This microinstruction
will
execute
only when the BUSY and

<-=-

(RB:RA)

lines

struction
TIOB
STATUS

BITS:

CONDITION

CODES:

system

are

1is

tested

the

bus

NB:

not

affected

ZB:

not

affected

C4:
C8:

not
not

affected
affected

not

affected

Z:
V:
:

not
not
not

affected
affected

low

PH3.

first part of

The

a DATI,

read microin-

DATIO,

cycle.

affected

EXAMPLE:

ASSEMBLY MNEMONIC:

R
IwW

RBAH,RBAL
TG8,RSRC

;START DATI, ADDRESS
;DATA INTO RSRC

RBA

DA-

THE

RIB1

SET

(RIB2)

READ

LSI-11l MICROINSTRUCTION

AND

INCREMENT

"13

BYTE

(1)

"11

710

ONE

OPCODE:

170000-170377

MICROCYCLES:

OPERATION:

(DAL)

DESCRIPTION:

(BY

TWwWO)

]

REG

FIELD

A REG

FIELD

(172000-172377)

(MIN)
<--

(RB:RA)

(RA)

<--

(RA)+1

The

16-bit

contents

RB:RA

are

placed

the

system

bus
as
a
system bus address.
The content of RB is
unchanged but the content of RA is incremtented by 1.
RIB2 causes the content of RA to be incremented by 2.
This microinstruction will execute only when the BUSY

and
REPLY
1lines are tested low at PH3.
The
microinstruction is the first part of a DATI,
or DATIOB system bus cycle.
STATUS

BITS:

CONDITION

CODES:

NB:

set

ZB:

set

C4:
C8:

set
set

if
if carry

byte

result < 0; cleared otherwise
result = 0; cleared otherwise
bit<3> carry = 1; cleared otherwise

byte

not

affected

not

affected

not

affected

out

cleared

otherwise

affected

EXAMPLE:
ASSEMBLY

MNEMONIC:

RIBZ2

RBAH,RBAL

;START

TG8 ,RSRC

;DATA

DATI,
INTO

ADDRESS

SOURCE

RBA

RIB1(2)
DATIO,

THE LSI-11 MICROINSTRUCTION SET

RIWl

(RIW2)

READ

INCREM ENT

AND

WORD BY ONE

15 714 713 12 "1IT1

(1)

"I0

OPCODE:

171000-171377

MICROCYCLES:
OPERATION:

'DESCRIPTION:

(BY TWO)

B REG FIELD

1
|

BITS:

CONDITION

CODES:

(173000-173777)

(MIN)

(DAL)

<=-

(RB:RA)

(RB:RA) <-- (RB:RA)+1 (or +2)
The 16-bit contents of RB:RA are placed on

the

system

bus as a system bus address.
The l6-bit word content
of registers RB:RA is incremented by 1.
RIW2
causes
the 16-bit word content of registers to be incremented by 2.
This
microinstruction
will
execute
only
when
the BUSY and REPLY lines are tested low at PH3.
The RIW1(2) microinstruction may be
a DATI, DATIO, or DATIOB system bus

STATUS

A REG FIELD

NB:
ZB:
C4:
C8:

set
set
set
set

if
if
if
if

the first
cycle.

part of

word result < 0; cleared otherwise
word result = 0; cleared otherwise
bit<3> carry = 1l; cleared otherwise
carry out = 1l; cleared otherwise

not

affected

Z:
V:

not
not

affected
affected

: not affected
EXAMPLE:

ASSEMBLY MNEMONIC:

RIWZ2
Iw

RBAH,RBAL
TG8,RSRC

;START DATI, ADDRESS IN RBA
;DATA INTO SOURCE REGISTER

THE

LSI~-1ll

MICROINSTRUCTION

SET

RA
READ

ACKNOWLEDGE

|
I
I
|
l
!
15714 I3 TIZTII IO

OPCODE:

MICROCYCLES:

[

(DAL)

DESCRIPTION:

The

<--

FIELD

I
I
I
47373710

contents of RB:RA are placed on the system
as
a system bus address.
The contents of RB:RA
unchanged and the flags are unaffected.
This mi-

will

lines

edge

microinstruction

operation

CODES:

A REG

(RB:RA)

croinstruction

CONDITION

!
l
I
77685

16-bit

bus
are

BITS:

FIELD

175000-175377
1 (MIN)

OPERATION:

STATUS

BREG

are

execute

tested

executed with

NB:

not

ZB:

not

affected

C4:
C8:

not
not

affected
affected

affected

not

affected

not

affected

not

affected

low

the

only when

PH3.

The

first

the WIACK

the

read

part

line

BUSY

and

acknowl-

asseted

input

HIGH.

THE LSI-11 MICROINSTRUCTION SET

4.3.2.2

Input Microinstructions - A member of

the Input Microinstruc-

tion
group completes the basic DATI or Read-Input operation.
WDIN is
asserted during PH4 following the removal of address information
from
the bus.
This signal is interfaced to the system bus as BDIN L, which
informs the addressed device to place its data on the bus for input to
1In order for the input microinstruction to be exthe microprocessor.

ecuted to completion, WDINH and REPLY H must be asserted during PH3.
the A port register is capable of writing register conSince only
tents,

input word microinstructions require 2 microcycles to execute.

In some instances it is desirable to have the input operations execute
The
the state of the REPLY H signal.
of
independent
completion
to
input status microinstructions execute immediately without being
preceded by a read operation and without checking the REPLY H signal.
It should be noted that of all the possible
Input
Microinstructions,
only the Input Word (IW) Microinstruction can load the translation register (when the B register field contains the proper
code).
The
B
field
argument
of
the
Input Byte (IB) and Input Word (IW) microinstruction can also specify a Read-Modify-Write operation.
All of
the
Input Microinstructions are available in a flag-affecting version.
The microinstruction descriptions are

follows:

THE LSI-11 MICROINSTRUCTION SET

(IBF)

INPUT BYTE

(UPDATE

~14

CONDITION

l___|
13
12

"11

CODE

(l1)|

|1
10
9

FLAGS)

B REG

FIELD

A REG FIELD

l____|
3
2

I
|

OPCODE:

160000-160377

MICROCYCLES:
OPERATION:
DESCRIPTION:

.
1 (MIN)
(RA) <-- (DAL<15:8> or DALK7:0>)
The 8-bit byte from the
system
bus
data
1lines
is
placed in register RA.
IBF causes the condition code
flags to be updated.
The Read-Input Data Access
operation
1is
terminated
unless
MI<K6>
1is
a 1 which
causes a Read-Modify-Write operation requiring termination by an Output operation.
This microinstruction
will not execute until the REPLY signal has been
received from the I/0 device.
input

(B)
(B)
(B)
(B)
(B)
(B)
(B)
(B)
NOTE:

options

SO
d WO

The

are

specified

Upper

Byte,

DAL<K15:8>

Lower
Upper
Lower

Byte, DAL<K7:0>
Byte if M(0)=1,
Byte if M(0)=1,

Upper

Byte,

DAL<K15:8>,

Lower

Byte,

DAL<7:0>,

Upper
Lower

Byte
Byte

if M(0)=1,
if M(0)=1,

M(0)

defined

address transferred
struction.
STATUS
;

BITS:

CONDITION CODES:
(IBF ONLY)

(160400-160777)

NB:
ZB:
C4:
C8:

set
set
not
not

the

N:
Z:

set
set

if
if

cleared

not

byte
byte

result
result

Lower
Upper

argument.

Byte
Byte

if
if

M(0)=0
M(0)=0

Byte
Byte

if M(0)=0,
if M(0)=0,

RMW
RMW

Lower
Upper

significant

previous
'

<
=

the

least

DAL

if byte result
if byte result
affected
affected

0;
0;

the

cleared
cleared

bit

MNEMONIC:

otherwise
otherwise

affected

UB,RSRCL

;INPUT

UPPER BYTE

INTO

the

Read microin-

EXAMPLE:

ASSEMBLY

RMW
RMW

RSRCL

THE

LSI-11 MICROINSTRUCTION

SET

(IWF)
INPUT

WORD

~15

(UPDATE

"1I3

"12

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

CONDITION

"1I1

CODE

710

FLAGS)

(1)|

B REG

placed
1in
tion code

registers RA+1:RA.
flags,
except
C,

Read-Input

Data

MI<6>

Access

which

I
6
5

161000-161377 (161400-161777)
2
(RA+1:RA) <-- (DALK15:0>)
The l16-bit word from the system

FIELD

bus
data
1lines
is
IWF causes the condito
be
updated.
The

operation

allows

A REG

terminated

Read-Modify-Write.

unless

The

loading
of the translation register and the G register is controlled by MI<5> and
MI<4>,
respectively,
as
1indicated
below.
This microinstruction will not
execute until the REPLY signal has been received from
the
1I/0 device.
The lower byte is loaded before the
upper byte.

STATUS

The

input

options

(B)
(B)
(B)

=0
=1
= 2

Load
Load
Load

Designated Registers Only
TR, DAL<6:4> TO G, Set ICC
TR, DAL<8:6> TO G, Set ICC

(B)

Load

TR,

(B)

READ-MODIFY-WRITE

(B)

Load

TR,

DALK6:4>

Set

ICC

Flag,

RMW

(B)
(B)

=
=

Load
Load

TR,
TR,

DAL<8:6> TO G, Set
Set ICC Flag, RMW

ICC

Flag,

RMW

NB:
ZB:

set
set

if
if

C4:

not

affected

C8:

not

affected

BITS:

CONDITION CODES:
(IWF ONLY)

6
7

N:
Z:

set
set

if
if

cleared

not

are

specified

Set

ICC

byte
byte

the

argument.

Flag
Flag

Flag
(RMW)
TO G,

result
result

<
=

0;
0;

cleared
cleared

otherwise
otherwise

affected

EXAMPLE:

ASSEMBLY

MNEMONIC:

TG8,RSRCL

;INPUT WORD INTO RSRCL
;LOAD TR, LOAD <8:6> TO

THE LSI-~11 MICROINSTRUCTION SET

(ISBF)

ISB

(UPDATE CONDITION CODE FLAGS)

INPUT STATUS BYTE

—15

17 "I3 712 71T 710

162000-162377

OPCODE:

]

B REG FIELD

A REG FIELD

I
|

(162400-162777)

(RA) <-- (DAL<15:8>)
(or DALK7:0>)
The 8-bit byte from the
system
bus
data
1lines
|is
placed
1in
register
RA.
ISBF causes the condition
code except C, flags to be
wupdated.
This
microinstruction will execute regardless of the state of the
REPLY

The

(1)|

MICROCYCLES:
OPERATION:
DESCRIPTION:

input

(B)
(B)
(B)
(B)
STATUS

BITS:

BUSY

options

signals.

are

specified by

the

Byte, DAL<K15:8>
Byte, DAL<K7:0>
Byte if M(0)=1,
Byte if M(0)=1,

4
5
6
7

Upper
Lower
Upper
Lower

NB:
ZB:

set
set

if byte
if byte

C4:

not
not

affected

0 or
1l or
2 or
3 or

C8:

CONDITION CODES:
(ISBF ONLY)

result
result

<
=

0;
0;

argument.

Lower Byte
Upper Byte

if M(0)=0
if M(0)=0

cleared otherwise
cleared otherwise

affected

N:
Z:

set
set

if
if

cleared

not

byte
byte

result
result

<
=

0;
0;

cleared
cleared

otherwise
otherwise

affected

EXAMPLE:

ASSEMBLY MNEMONIC:

ISB

UB,RSRCL

;INPUT UPPER BYTE

INTO RSRCL

THE

LSI-11

MICROINSTRUCTION

Microinstruction
Figure

09
T

[

OP CODE
1

SET

Format

4-5

04
T

1/0

B REGISTER
i

A REGISTER
i

1
MR-1041

THE

ISW

MICROINSTRUCTION

SET

(ISWF)

INPUT

STATUS

LSI-11

1
15

WORD

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

(UPDATE

CONDITION

(1)|
9

CODE

FLAGS)

NOT

USED

|
5

BITS:

CONDITION

(ISWF

CODES:

ONLY)

163000-163377 (163400-163777)
2
(RA+1:RA)
<-- (DAL<15:0>)
The 1l6-bit word from the system
placed
1in registers RA+1:RA.
tion code flags, except C, to
croinstruction
will
execute
of the BUSY or REPLY signals.
aded before the upper byte.

STATUS

NB:
ZB:

set
set

if
if

byte
byte

result
result

C4:

not

affected

C8:

not

affected

set

cleared

not

if
1f

byte
byte

result
result

;
;

<
=

0;
(0;

bus

REG

FIELD

data

MNEMONIC:

ISWF

1lines

cleared
cleared

otherwise
otherwise

cleared

otherwise

cleared

otherwise

affected

yRSRCL

ISWF causes the condibe updated.
This
miregardless of the state
The lower byte is
1lo-

EXAMPLE:

ASSEMBLY

;INPUT WORD INTO RSRCL
; LOAD TR, LOAD <8:6> TO

THE

LSI-11

MICROINSTRUCTION

SET

4,3.2.3
Write Microinstructions - The Write Microinstructions are the
sequence which implements the DATO
Write-Output
the
of
part
first
(Data-Output) transactions.
Because the A and B register ports may be

simultaneously, Write Microinstructions place both the upper and
read
time.
same
the
at
lower byte of the device address on BDAL <15:00>
Write Microinstructions, except for those which increment an adAll

Iis
However, before execution
dress word, execute in one microcycle.
initiated, the Control chip checks REPLY H and BUSY H at PH3 to verify
the
Because of
that no other system bus operations are in progress.
requirement to check REPLY H and BUSY H during PH3, the address information cannot be placed on the bus
until
the
following
microcycle.
is placed on BDAL <15:00> during PHl and is
information
address
The

cancelled at the end of PH4, thus making the address
All Write Microinstructions assert WSYNC
crocycle.
The Write
microcycle in which the address is valid.
microinstruction asserts WIACK H simultaneously with
The microinstruction descriptions are as follows:

valid for one miduring PH2 of the
(WA)
Acknowledge
WSYNC.

THE

LSI-11

MICROINSTRUCTION

SET

WRITE

|
13

"1I2

710

OPCODE:

174400-174777

MICROCYCLES:

OPERATION:

(DAL)

DESCRIPTION:

The

<--

CODES:

contents

a system
unchanged and

REG

FIELD

REG

FIELD

|
2

bus

cycle.

NB:

not

affected

ZB:

not

affected

C4:

not

affected

C8:

not

affected

not

affected

not

affected

not

affected

the

system

unaffected.

This

mi-

only when the

BUSY

and

the

tem

placed

flags

tested

are

the

lines

RB:RA

The

will

MNEMONIC:

address.
are

execute
low

first

part

PH3.

contents

The

DATO

write

affected

RBAH,RBAL

;START

RDSTH,RDSTL

;DATA

DATO,
FROM

ADDRESS

SOURCE

RB:RA

micro-

DATOB

EXAMPLE:
ASSEMBLY

bus

croinstruction

instruction

CONDITION

T 8

(RB:RA)

16-bit

are

BITS:

(MIN)

bus

STATUS

RBA

sys-

'THE LSI-11 MICROINSTRUCTION SET

(WIB2)

WIB1

WRITE AND INCREMENT BYTE BY ONE
I

|
1

(1)

~15 14 713 712 IT

OPCODE:

MICROCYCLES:

B REG

FIELD

A REG

l___|
4
3

FIELD

(MIN)

(RA)

DESCRIPTION:

170400—170777 (172400—172777)
(DAL)

OPERATION:

(BY TWO)

<-~

<--

(RB:RA)

(RA)+l

(or+2)

The 16-bit contents of RB:RA are'placed on the system
bus as
a
system bus address.
The content of RB is
unchanged but the content of RA is incremented by
1.
WIBZ2 causes the content of RA to be incremented by 2.
The flags are not
affected.
This
microinstruction
will
execute
only when the BUSY and REPLY lines are
tested low at PH3.
The WIB1l(2)
microinstruction
is
the first part of a DATO or DATOB. system bus cycle.

STATUS

BITS:

CONDITION

CODES:

NB:
ZB:
C4:
C8:

set
set
set
set

if
if
if
if

byte result < 0 ; cleared otherwise
byte result = 0 ; cleared otherwise
bit<3> carry = l;cleared otherwise
carry out = 1; cleared otherwise

N:
Z:

not
not

affected
affected

not

affected

not

affected

EXAMPLE:

ASSEMBLY

MNEMONIC:

WIBZ2

RBAH,RBAL

; START

RDSTH,RDSTL

;DATA

DATO,
INTO

ADDRESS

SOURCE

RBA

THE

WIwWl

MICROINSTRUCTION

SET

(WIW2)

WRITE

AND

INCRE MENT

LSI-11

WORD

ONE

(1)

I
I
I
|
I
I
15 "I4 I3 712 1T 710

MICROCYCLES:

171400-171777
1
(MIN)

OPERATION:

(DAL)

OPCODE:

<--

l6-bit

bus

REG

(RB:RA)+1

contents

system

registers

bus

RB:RA

will

tested

CONDITION

CODES:

NB:
ZB:

REG

lines

are

bus

are placed on the system
-The 1l6-bit word content

1is

the

are

not

execute

the

low

WIW2

registers

affected.

only when
PH3.
The

first part

causes
be increThis
mi-

the BUSY
WIW1(2)
DATO

cycle.

set

word

set

word

C4:

set

result < 0; ¢ leared
result = 0; c leared
bit<3> carry = 1l;c leared

C8:

set

carry

not

affected

not

affected

not

affected

MNEMONIC :

out

c leared

otherwise
otherwise
otherwise

otherwise

affected

EXAMPLE:
ASSEMBLY

FIELD

(or+2)

incremented

croinstruction

BITS:

address.

16-bit word content
mented by 2.
The flags

STATUS

RB:RA

the

system

FIELD

(173400-173777)

<--

The

TwO)

(RB:RA)

(RB:RA)
DESCRIPTION:

(BY

WIBZ2

RBAH,RBAL

; START

OwW

RDSTH,RDSTL

;DATA FROM SOURCE

DATO,

ADDRESS

RBA

and

miDATOB

THE

LSI-11 MICROINSTRUCTION

SET

WRITE

ACKNOWLEDGE

1514
OPCODE:

"I3
_

I
|
"1I2 '11

l___|
9
8~

BREG

FIELD

I
|

A REG

FIELD

I
|

I
l
I
|I
I
473727170

175400-175777
(MIN)
'
(DAL) <-- (RB:RA)

MICROCYCLES:
OPERATION:

DESCRIPTION:

The

16-bit contents

bus
are

as
a system bus
unchanged and the

RB:RA are placed on
address.
flags are

the

The contents
unaffected.

system

of RB:RA
This mi-

croinstruction
will
execute
only when the BUSY and
REPLY lines are tested low at PH3,.
The
write
acknowledge
microinstruction
1is
the
first part of an
input operation executed with the WIACK line
asseted
HIGH.

However,
the
circuitry on the LSI-11l
does not allow BIACK L to be asserted for this
nowledge" microinstruction.

STATUS

BITS:

CONDITION

CODES:

NB:

not

affected

ZB:

not

affected

C4:
C8:

not
not

affected
affected

not

affected

not

affected

not

affected

not

affected

module

"ack-

THE

LSI-11

MICROINSTRUCTION

SET

4,3.2.4
Output Microinstructions - An Qutput Microinstruction is used
to complete the basic DATO or Write/Output operation, or to complete a

Read-Modify-Write operation (DATIO or DATIOB).
WDOUT is
asserted
by
an Output Microinstruction during PHl1 following the removal of address
information from the bus.
This signal is interfaced to the system bus
as
BDOUT
L,
which
causes
the
addressed device to accept the data
placed on the bus by the microprocessor Data chip.
In
order
for
an
Output

Microinstruction

completed,

must

asserted

the addressed device during PH3.
Both register A and B ports
provide
for
reading
or
accessing
register contents, so for Output Word and
Output Status Word Microinstructions, all 1l6-bits can be output during
one microcycle.
1In some instances it is desirable to complete an output operation independent of the state of the
REPLY
H
signal.
The
Output

Status

ceded by
signal.
The

Microinstructions

a Write

execute

Microinstruction

microinstruction

descriptions

immediately

and

without

are

without

checking

follows:

the

being

pre-

THE

LSI-11 MICROINSTRUCTION

SET

OB
OUTPUT

I
|

BYTE

15 " 14

13 12

OPCODE:

MICROCYCLES:
OPERATION:

"11

)
0

.
9
8

176000-176377
1 (MIN)

<--

(DAL)

(RB:RA)

REG

FIELD

|
6
5

A REG

N
2

FIELD

DESCRIPTION:

-The 1l6-bit contents of RB:RA are placed on the system
bus
as
output
data.
The WDOUT signal is asserted.
The
content
of
registers
RB:RA
is
not
changed.
Because
of the 1l6-bit system bus data path, B must
equal A so that the same byte is placed in both positions.
The
OB microinstruction will not execute to
completion until the REPLY signal has been received.

STATUS

NB:

not affected

ZB:

not

affected

C4:
C8:

not
not

affected
affected

BITS:

CONDITION

CODES:

not

affected

not

affected

not

affected

EXAMPLE:
ASSEMBLY

MNEMONIC:

RDSTL,RDSTL

;OUTPUT

BYTE

FROM

RDSTL

THE

LSI-11

MICROINSTRUCTION

SET

OUTPUT

WORD

BREG

I___1
I
I
I___|
I
I
I
715 714 "I3 IZ IT 7I0 TS T8T 776

OPCODE:
MICROCYCLES:

(DAL)

DESCRIPTION:

The
bus

l6-bit contents of
as
output
data.

<--

A REG

The

content

BITS:

I
|

I
I
I
I
I
I
57473727170

RB:RA are placed on the system
The WDOUT signal is asserted.

registers

RB:RA

CODES:

NB:

not

affected

ZB:

not

affected

C4:
C8:

not
not

affected
affected

not

affected

not

affected

not

affected

not

affected

not
been

not

changed.

execute to
received.

EXAMPLE:

ASSEMBLY

FIELD

(RB:RA)

OW
microinstruction
will
until the REPLY signal has

CONDITION

176400-176777
1l (MIN)

OPERATION:

STATUS

FIELD

MNEMONIC:

OW RDSTH,RDSTL

;OUTPUT

WORD

FROM

RDST

The

completion

THE LSI-11 MICROINSTRUCTION SET

0Ss

OUTPUT STATUS
i

o
1

|
|
|
|
|
15 714 713 712 IT

BREG

FIELD

|
|
T 9 T 8T

I
776

|
|

A REG

FIELD

|
I
|
I
I
|
57473727170

OPCODE:

177000-177377

MICROCYCLES:
OPERATION:

DESCRIPTION

The 16-bit contents of RB:RA are placed
on the system
bus
a&
output data.
The content of registers RB:RA
is not changed.
The OS microinstruction will execute
to
completion regardless of the state of the BUSY OR

(DAL)

<--

tem

signals.

bus

means
STATUS

BITS:

CONDITION

CODES:

(RB:RA)

may

the

I/O

circuitry interfaced
sychronized with this

TTL Control

NB:

not

affected

ZB:

not

affected

C4:
C8:

not
not

affected
affected

N:
Z:

not
not

affected
affected

not

affected

not

affected

bits,

MI<23:18>.

EXAMPLE:
ASSEMBLY

MNEMONIC:

RDSTH,RDSTL

;OUTPUT

WORD

FROM

RDST

to the
sysoperation by

THE LSI-11

4.3.3

Microprogram Control

MICROINSTRUCTION

SET

Microinstructons

The Microprogram Control Microinstructions
croinstruction
flow.
The only available

by this group are
and Trap Service)

(1)
and

4.3.3.1

Return

Jump

and

the
(2)

control or modify
the
micontrol methods not covered
RSVC bit
(Read
Next
Instruction/Interrupt
the microprocessor Control chip RESET line.

Microinstructions

microinstructions
which
alter
tionally and unconditionally).
Jump

(JMP)

microaddress
The

sequence

allows

from data

microinstruction

one

the
The

the

descriptions

This

group

contains

all

microinstruction flow (both condiModify
Microinstruction
(MI)
-

microprogrammer

the
are

micromachine
as

follows:

determine

registers.

the

jump

THE LSI-11 MICROINSTRUCTION SET

JMP

JUMP

(UNCONDITIONALLY)

I
|

UNCONDITIONAL JUMP

I
I
I
l___|
15 712 I3 7127117109
I

OPCODE:

000000~003777

MICROCYCLES:

OPERATION:
DESCRIPTION:

MICROADDRESS

l
I
I
I
|
776574737

(LC) <-= (MIK10:0>)
The ll-bit microaddress stored

tion

this

|
I

27170

microinstruc-

1is placed in the Control Chip Location Counter.

The next microinstruction
to
be
executed
will
be
fetched from the new location.
Execution of this microinstruction requires
2
microcycles
because
the
normal
microaddress generation sequence is modified.
Translations programmed in the translation array
are

ignored.

other

changed.

STATUS

BITS:

CONDITION

CODES:

NB:
ZB:

not
not

affected
affected

C4:

not

affected

C8:

not

affected

N:
Z:

not
not

affected
affected

not

affected

not

affected

flag

contents

are

THE

LSI-11l

MICROINSTRUCTION

SET

RFS

RETURN

FROM

SUBROUTINE

I
[
I

[
|
I

UNUSED
I
I
I
I
I
I
8777657473

I
I
l
|
I
15 714 713 12 71T 7I0 T 9 T

OPCODE:

MICROCYCLES:
OPERATION:
DESCRIPTION:

I
I
327170

|
|
I

004000-007777
2
(LC) <-- (RR<10:0>)
The ll-bit microaddress

placed

Return

the

stored
Control chip
usually

in the return register
Location Counter.
The

loaded

the

time

JMP

microinstruction
is executed.
Execution of this microinstruction requires
2
microcycles
because
the
normal
microaddress generation sequence is modified.
Translations programmed in the translation array
are
ignored.
No
other
register
or
flag contents are
changed.

STATUS

BITS:

CONDITION

CODES:

NB:

not

ZB:

not

affected

C4:

not

affected

C8:

not

affected

not

affected

not

affected

not

affected

not

affected

THE LSI-11 MICROINSTRUCTION SET

JZBF

JUMP

l
|
I

STATUS

BIT

FLAG

0
0
1
0
I
||
l___1___|
15 7174 713 12 IT I0

ZERO

CONDITIONAL JUMP MICROADDRESS

57473727170

OPCODE:

010000-010377

MICROCYCLES:

OPERATION:

(LCK7:0>) <=- (MIK7:0>), IF ZB = 0
The 8-bit microaddress stored in
this
microinstruction
1is placed in the Control chip Location Counter

DESCRIPTION:

the condition

(2ZB=0)

is met.

Execution

this

microinstruction
requires
2 microcycles because the
normal microaddress generation sequence is
modified.

Bits

<7:0> of

translations programmed

" tion array are ignored.
contents are changed.

in the

No other

Note that Ehe upper 3 bits of the

Location

LC<10:8>,

BITS:

not

met.

NB:
ZB:

not
not

affected
affected

C4:
C8:

not
not

affected
affected

CONDITION CODES: N:

not

Z:
V:

not

affected

not

affected

not

affected

unchanged,

pointing

flag

Counter,

256-word
page from which the next microinstruction is fetched.
The page number is determined at the beginning
of the
first microcycle of execution at the time the
microaddress
of
the
next sequential microinstruction is
loaded in the Location
Counter.
This
microaddress
will
be
wused
during microfetch if the condition is

STATUS

remain

transla-

THE

LSI-11 MICROINSTRUCTION

SET

JZBT

JUMP

STATUS

BIT

FLAG

"15 714 713 712 "I1

OPCODE:

010400-010777

MICROCYCLES:

OPERATION:

(LC<7:0>)
The 8-bit

DESCRIPTION:

ONE

CONDITIONAL JUMP

MICROADDRESS

I
l___|
I
57473727

== (MIK7:0>), IF ZB =1
microaddress stored in
this

tion
is
placed
if the condition
microinstruction

I
|

I
I
1TO

microinstruc-

in the Control chip Location Counter
(ZB=1l) is met.
Execution
of
this
requires
2 microcycles because the

normal microaddress generation sequence is
modified.
Bits <7:0> of translations programmed in the transla-

tion

array

contents

are

Note that
LC<10:8>,

ignored.

other

flag

changed.

the upper 3 bits of
remain
unchanged,

the
Location
pointing to a

Counter,
256-word

page from which the next microinstruction is fetched.
The page number is determined at the beginning of the
first microcycle of execution at the time the
microaddress
of
the
next sequential microinstruction is
loaded in the Location
Counter.
This
microaddress
will
be
wused
during microfetch if the condition is

STATUS

BITS:

CONDITION

CODES:

not

met.

NB:

not

ZB:

not

affected

C4:

not

affected

C8:

not

affected

not

affected

Z:
V:

not
not

affected
affected

not

affected

THE

LSI-11 MICROINSTRUCTION

SET

JNBF
JUMP

STATUS

BIT

FLAG

I
I
|
l
|
|
|
~15 ‘II_”I? 12 11 710 — 9

OPCODE:

MICROCYCLES:

ZERO

CONDITIONAL JUMP

|
8 ~ 7

MICROADDRESS

013000-013377
2

OPERATION:

(LC<7:0>)

DESCRIPTION:

The

<=- (MIK7:0>), IF NB =
8-bit microaddress stored in

this

microinstruc-

tion
1is
placed in the Control chip Location Counter
if the condition (NB=0) is met.
Execution
of
this
microinstruction
requires
2 microcycles because the
normal microaddress generation sequence is
modified.
Bits <7:0> of translations programmed in the translation array are ignored.
No other
register
or
flag
contents

are

Note that
LC<10:8>,
page
The

changed.

the upper 3 bits of
remain
wunchanged,

from which
page number

first microcycle
address

loaded in
will
be
not

STATUS

BITS:

CONDITION

CODES:

the

the
is

the
Location
pointing to a

256-word
microinstruction is fetched.
determined at the beginning of the
next

execution

sequential

the Location
Counter.
wused
during microfetch

met.

NB:

not

ZB:

not

affected

C4:
C8:

not
not

affected
affected

affected

not

affected

not

affected

not

affected

not

affected

Counter,

the

time

the

micro-

microinstruction

This
if the

microaddress
condition is

THE

LSI-11 MICROINSTRUCTION

SET

JNBT
JUMP

STATUS

"14

OPCODE:

MICROCYCLES:
OPERATION:
DESCRIPTION:

BIT

FLAG

"11

ONE

013400-013777
2
(LC<7:0>) <--=

CONDITIONAL JUMP MICROADDRESS

(MIK7:0>),

The 8-bit microaddress stored in
this
microinstruction
1is
placed in the Control chip Location Counter
if the condition (NB=1) is met.
Execution
of
this
microinstruction
requires
2 microcycles because the
normal microaddress generation sequence is
modified.
Bits <0:7> of translations programmed in the translation array are ignored.
No other
register
or
flag
contents

are

changed.

Note that the upper 3 bits of the
Location
Counter,
LC<10:8>,
remain
unchanged,
pointing to a 256-word
page from which the next microinstruction is fetched.
The page number is determined at the beginning of the
first microcycle of execution at the time the
microaddress
of
the
next sequential microinstruction is
loaded in the Location
Counter.
This
microaddress
will
be
wused
during microfetch if the condition is

STATUS

BITS:

CONDITION

not

met.

NB:

not

affected

ZB:

not

affected

C4:

not

affected

C8:

not

affected

CODES: N:

not

affected

not

affected

not

affected

not

affected

4-96

THE LSI-11 MICROINSTRUCTION SET

JIF

JUMP

INDIREC T

CONDITION

I
I
I
15 14 13712
IT

CODE

012000-012377

MICROCYCLES:
OPERATION:
DESCRIPTION:

]

" 9

OPCODE:

ZERO

CONDITIONAL JUMP MICROADDRESS

I
|

47327170

(LC<7:0>) == (MIK7:0>), IF ICC =0
The 8-bit microaddress stored in
this
microinstruction
1is
placed in the Control chip Location Counter

if the condition (ICC=0) is met.
Execution
of
this
microinstruction
requires
2 microcycles because the
normal microaddress generation sequence is
modified.
Bits <0:7> of translations programmed in the translation array are ignored.
No other
register
or
flag
contents are changed.
Note that the upper 3 bits of the
Location
Counter,
LC<10:8>,
remain
unchanged,
pointing to a 256-word
page from which the next microinstruction is fetched.
The page number is determined at the beginning of the
first microcycle of execution at the time the
microaddress
of
the
next sequential microinstruction is
loaded in the Location
Counter.
This
microaddress
will
be
wused
during microfetch if the condition is

STATUS

BITS:

CONDITION

not

met.

NB:

not

affected

ZB:
C4:

not
not

affected
affected

C8:

not

affected

CODES: N:
Z:
V:

not
not

affected
affected

not

affected

not

affected

THE

LSI-11

MICROINSTRUCTION

SET

JIT
JUMP

O
15

INDIRECT

CONDITION

CODE

OPCODE:

012400-012777
2
(LC<7:0>)

DESCRIPTION:

The

MICROCYCLES:
OPERATION:

<=--

ONE

CONDITIONAL JUMP MICROADDRESS
7

(MI<7:0>),

ICC

8-bit microaddress stored in
this
microinstruction
1is
placed in the Control chip Location Counter

the

condition

(ICC=1l)

is met.

Execution

this

No other

flag

microinstruction
requires
2 microcycles because the
normal microaddress generation sequence is
modified.
Bits <0:7> of translations programmed in the transla-

tion

array

contents

Note that
LC<10:8>,
page

are

ignored.

changed.

the

upper 3 bits of
remain
unchanged,

from which

The

page

not

met.

NB:

not

affected

ZB:

not

affected

C4:

not

affected

C8:

not

affected

the

Location
Counter,
pointing to a 256-word
the next microinstruction is fetched.
is determined at the beginning of the

number
first microcycle of execution at the time the
microaddress
of
the
next sequential microinstruction is
loaded in the Location
Counter.
This
microaddress
will
be
used
during microfetch if the condition is

STATUS

BITS:

CONDITION

CODES:

not

affected

not

affected

not

affected

THE LSI~-11 MICROINSTRUCTION SET

JC8F

JUMP IF STATUS BIT FLAG C8

I
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|
=I5 7IZ I3 12 I 10T

ZERO

987

OPCODE:

011000-011377

MICROCYCLES:
OPERATION:
DESCRIPTION:

]
|
| CONDITIONAL JUMP MICROADDRESS
I
I
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l

57473727170

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I

(LC<7:0>) <=- (MIK7:0>), IF C8 =0
The 8-bit microaddress stored in
this
microinstruction
1is
placed in the Control chip Location Counter
if the condition (C8=0) is met.
Execution
of
this
microinstruction
requires
2 microcycles because the
normal microaddress generation sequence is
modified.
Bits <0:7> of translations programmed in the translation array are ignored.
No other
register
or
flag
contents

are

Note that
LC<10:8>,

changed.

the upper 3 bits of
remain
unchanged,

the
Location
Counter,
pointing to a 256-word

page from which the next microinstruction is fetched.
The page number is determined at the beginning of the
first microcycle of execution at the time the
microaddress of
the
next sequential microinstruction is
loaded in the Location
Counter.
This
microaddress
will
be
wused
during microfetch if the condition is

STATUS

BITS:

CONDITION

CODES:

not

met.

NB:
ZB:
C4:
C8:

not
not
not
not

N:
Z:
V:
C:

not
not
not
not

affected
affected
affected
affected
affected
affected
affected
affected

THE

LSI-11

MICROINSTRUCTION

SET

JC8T
JUMP

STATUS

BIT

FLAG

ONE

l
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!
l
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15714 71312 TIT TI0 T 9 T8 T

OPCODE:

MICROCYCLES:

CONDITIONAL JUMP

54T

MICROADDRESS

TTICO

011400-011777
2

OPERATION:

(LC<7:0>)

DESCRIPTION:

The 8-bit microaddress stored in
this
microinstruction
is
placed in the Control chip Location Counter
if the condition (C8=1) is met.
Execution
of
this
microinstruction
requires
2 microcycles because the
normal

<0:7>

tion

array

that
LC<10:8>,

page

from

page

first

will

BITS:

CONDITION

CODES:

generation sequence is
modified.
translations programmed in the translaare ignored.
No other
register
or
flag
changed.

the

upper 3 bits of
remain
unchanged,

which

number

microcycle

address

loaded

are

Note

The

(MIK7:0>),

microaddress

Bits

contents

STATUS

<--

in
be

the

Location

Counter,

pointing

to a 256-word
the next microinstruction is fetched.
is determined at the beginning of the

execution

the

time

the

micro-

sequential

Location

microinstruction

Counter.
microfetch

This
if the

wused

during

not

met.

NB:

not

affected

ZB:

not

C4:

affected

not

affected

C8:

not

affected

not

affected

not

affected

not

affected

not

affected

4-100

is
microaddress
condition is

THE

LSI~11l

MICROINSTRUCTION

SET

JNF

JUMP IF CONDITION CODE FLAG N IS ZERO
|

l___|
|
l
I
l
“I5 714 713 712 7IT I0

OPCODE:

017000-017377

MICROCYCLES:

CONDITIONAL JUMP MICROADDRESS

776

OPERATION:

(LC<7:0>)

<=-

DESCRIPTION:

The

microaddress

8-bit

(MIK7:0>),

I
|

57473727170

stored

=0
in

this

microinstruc-

tion
1is
placed in the Control chip Location Counter
if the condition (N=0) is met.
Execution of this microinstruction
requires
2
microcycles
because the
normal microaddress generation sequence is
modified.
Bits <0:7> of translations programmed in the translation array are ignored.
No other
register
or
flag
contents are changed.
Note that
LC<10:8>,

the upper 3 bits of
remain
unchanged,

the
Location
pointing to a

Counter,
256-word

STATUS

BITS:

CONDITION

not

met.

NB:

not

ZB:

not

affected

C4:
C8:

not
not

affected
affected

affected

CODES: N:

not

affected
affected

not

affected

not

affected

4-101

THE LSI-11 MICROINSTRUCTION SET

JNT

JUMP

O
15

0
14

CONDITION CODE

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

FLAG N

ONE

|
8

CONDITIONAL JUMP MICROADDRESS

DN D
5

I
0

017400-017777
2
(LC<7:0>) <--= (MIK7:0>), IFN =1
The 8-bit microaddress stored in
this
microinstruction
1is
placed in the Control chip Location Counter
if the condition (N=1) is met.
Execution of this microinstruction
requires
2
microcycles
because the
normal microaddress generation sequence is
modified.
Bits <0:7> of translations programmed in the translation array are ignored.
No other
register
or
flag
contents

Note

are

that

LC<10:8>,

page

the

changed.

upper

remain

from which

the

bits

wunchanged,

the

Location

pointing

next microinstruction

The page number is determined
first microcycle of execution

at
at

the
the

Counter,
a

256-word

fetched.

beginning
time the

of the
micro-

address
of
the
next sequential microinstruction 1is
loaded in the Location
Counter.
This
microaddress
will
be
used
during microfetch if the condition is
not met.
'
STATUS

BITS:

CONDITION

CODES:

NB:
ZB:
C4:

not
not
not

affected
affected
affected

C8:

not

affected

not

affected

Z:
V:

not
not

affected
affected

not

affected

4-102

THE

LSI-11

MICROINSTRUCTION

SET

JZF

JUMP IF CONDITION CODE FLAG %2

714

"1I3

"12

"11

014000-014377

MICROCYCLES:

OPERATION:

(LC<7:0>)
The 8-bit

<==

ZERO

OPCODE:

DESCRIPTION:

CONDITIONAL JUMP

(MIK7:0>),

microaddress

MICROADDRESS

stored

in
this
microinstruction
1is
placed in the Control chip Location Counter
if the condition (Z=0) is met.
Execution of this microinstruction
requires
2
microcycles
because the

normal microaddress generation sequence is
modified.
Bits <0:7> of translations programmed in the translation array are ignored.
No other
register
or
flag
contents are changed.
Note that
LC<10:8>,

the

upper

bits

address
of
the
next
loaded in the Location
will
be
wused
during

BITS:

CONDITION

CODES:

Location

unchanged,
pointing to a
the next microinstruction is

page from which
The page number is determined
first microcycle of execution

STATUS

the

remain

not

met.

NB:

not

ZB:

not

affected

C4:

not

affected

C8:

not

affected

not

affected

not

affected

not

affected

not

affected

4-103

the

Counter,

256-word
fetched.

beginning

the

at the time the
microsequential microinstruction is

Counter.
microfetch

This
if the

microaddress

condition

THE

LSI-11 MICROINSTRUCTION SET

JZT

JUMP

CONDITION

714

CODE

FLAG

MICROCYCLES:
OPERATION:
DESCRIPTION:

13 12 1T "I0

OPCODE:

ONE

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CONDITIONAL JUMP

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" 9~ 8~ 7

MICROADDRESS

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327170

014400-014777
2
(LC<7:0>)
<-=-= (MIK7:0>), IF Z2 =1
The 8-bit microaddress stored in
this
microinstruction
1is
placed in the Control chip Location Counter

if the condition (Z=1) is met.
Execution of this microinstruction
requires
2
microcycles
because the
normal microaddress generation sequence is
modified.
Bits

<0:7>

translations

tion array are ignored.
contents are changed.
Note that
LC<10:8>,

programmed

No other

the upper 3 bits of
remain
unchanged,

the

the
Location
pointing to a

transla-

flag

Counter,
256-word

STATUS

BITS:

CONDITION

CODES:

not

met.

NB:

not

affected

ZB:

not

affected

C4:
C8:

not
not

affected

not

‘Z2:

not

affected

not

affected

not

affected

4-104

THE

LSI-11]

MICROINSTRUCTION

SET

JVF

JUMP

CONDITION

CODE

FLAG

15 717 713 712 "I1

016000-016377

MICROCYCLES:

OPERATION:

(LC<K7:0>)
The 8-bit

ZERO

I
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7109

OPCODE:

DESCRIPTION:

CONDITIONAL JUMP MICROADDRESS

<K== (MIK7:0>), IF V
microaddress stored

I
I
473727170

=20
in

this

microinstruc-

tion
1is
placed in the Control chip Location Counter
if the condition (V=0) is met.
Execution of this microinstruction
requires
2
microcycles
because the
normal microaddress generation sequence is
modified.
Bits <0:7> of translations programmed in the translation array are ignored.
No other
register
or
flag
contents
Note

are

that

the

changed.
upper

bits

the

Location

Counter,

LC<10:8>,
remain
unchanged,
pointing to a 256-word
page from which the next microinstruction is fetched.
The page number is determined at the beginning of the
first microcycle of execution at the time the
microaddress
of
the
next sequential microinstruction is
loaded in the Location
Counter.
This
microaddress
will
be
wused
during microfetch if the condition is

not met.
STATUS

BITS:

CONDITION

CODES:

NB:

not

affected

ZB:
C4:

not
not

affected
affected

C8:

not

affected

N:
-2:

not
not

affected
affected

V:
:

not
not

affected
affected

4-105

THE

LSI-11

CODE

FLAG

MICROINSTRUCTION

SET

JVT
JUMP

O
15

CONDITION

1l
9

OPCODE:

016400-016777

MICROCYCLES:

ONE

|
8

CONDITIONAL JUMP

OPERATION:

(LC<7:0>)

<K==

DESCRIPTION:

The

microaddress

8-~bit

(MIK7:0>),

stored

MICROADDRESS

=1
in

this

microinstruc-

tion
1s
placed in the Control chip Location Counter
i1f the condition (V=1) is met.
Execution of this microinstruction
requires
2
microcycles
because the
normal microaddress generation sequence is
modified.
Bits <0:7> of translations programmed in the translation array are ignored.
No other
register
or
flag
contents

are

Note that
LC<10:8>,
page
The

changed.

the

upper 3 bits of
remain
unchanged,

from which
page

number

first microcycle
address

loaded

will

STATUS

BITS:

CONDITION

CODES:

the

the
is

wused

met.

NB:

not

affected

ZB:

not

affected

C4:

not

affected

C8:

not

affected

not

affected

not

affected

not

affected

Location
pointing to a
microinstruction is

Counter,

256-word
fetched.

determined

the

beginning

execution

the

time

micro-

Location

not

the

during

affected

4-106

sequential

Counter.

microfetch

the

microinstruction

This

the

the
is

microaddress

condition

THE

LSI-11

CODE

FLAG

MICROINSTRUCTION

SET

JCF
JUMP

]

CONDITION

[

OPCODE:

015000-015377

MICROCYCLES:

ZERO

CONDITIONAL JUMP

OPERATION:

(LCK7:0>)

<==

DESCRIPTION:

The

microaddress

8-bit

(MIK7:0>),

stored

MICROADDRESS

this

microinstruc-

tion
1is
placed in the Control chip Location Counter
if the condition (C=0) is met.
Execution of this microinstruction
requires
2
microcycles
because the
normal microaddress generation sequence is
modified.

Bits

<0:7>

tion

array

are

contents

are

Note that
LC<10:8>,

page
The

page

CONDITION

CODES:

the

upper 3 bits of
remain
unchanged,

number
of

loaded in
will
be

programmed

No other

the

transla-

flag

changed.

microcycle

address

BITS:

ignored.

from which

first

STATUS

translations

the

the
is

Location
pointing to a

microinstruction

determined

the

execution

the

Counter,
256-word

fetched.

beginning

time

the

sequential

microinstruction

the Location
wused
during

Counter.
microfetch

This
if the

not

met.

NB:

not

ZB:

not

affected

C4:

not

affected

C8:

not

affected

not

affected

not

affected

not

affected

not

affected

4-107

the

microis

microaddress
condition is

THE

LSI-1l1

CODE

FLAG

MICROINSTRUCTION

SET

JCT
JUMP

CONDITION

“15 "I4 I3 712 1T 10 9

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

ONE

CONDITIONAL JUMP

MICROADDRESS

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5473727170

015400-015777
2
(LCK7:0>)
<K==

(MIK7:0>), IFC =1
microaddress stored in
this
microinstrucplaced in the Control chip Location Counter

The 8-bit
tion
1is

1f the condition (C=1) is
croinstruction
requires

met.
Execution
2
microcycles

of this
because

mithe

normal microaddress generation sequence is
modified.
Bits <0:7> of translations programmed in the transla-

tion

array

contents

are

Note that
LC<10:8>,

ignored.

other

flag

changed.

the upper 3 bits of
remain
unchanged,

page from which
The page number

the
Location
pointing to a

Counter,
256-word

the next microinstruction is fetched.
is determined at the beginning of the

first

microcycle of execution at the time the
microof
the
next sequential microinstruction is
loaded in the Location
Counter.
This
microaddress
address

will

STATUS

BITS:

CONDITION CODES:

used

not

met.

NB:

not

affected

ZB:

not

affected

C4:
C8:

not
not

affected

during

affected

not

affected

not

affected

not

affected

not

affected

4-108

microfetch

the

condition

THE

LSI-1]l MICROINSTRUCTION

SET

MODIFY

~15

MICROINSTRUCTION

"13

OPCODE:
OPERATION:
DESCRIPTION:

"12

"11

710

BITS:

CONDITION

CODES:

1
|

REG

(|
8
7

FIELD

A REG

FIELD

166000-166377
(MIB<15:0>) <-=- (RB:RA), With Next Microinstruction
The 16-bit contents of registers RB:RA are ORed
with
the contents of the next sequential control store location to form the next microinstruction.
During the
execution of the MI m icroinstruction, the contents of
registers RB:RA are p laced
on
the
Microinstruction
Bus
simultaneously
with
the
next microinstruction
from control
changed

STATUS

NB:

not

ZB:

not

C4:

not

C8:

not

store.

affected
affected
affected
affected

not

not’ affected

affected

not

affected

not

affected

4-109

The

content

RB:RA

un-

THE

LSI-11

MICROINSTRUCTION

SET

4.3.3.2

five
The

Compare and Test Microinstructions - This group
consists
arithmetic compare and five logical test microinstructions.

microinstruction

descriptions

are

4-110

follows:

THE LSI-11 MICROINSTRUCTION SET

COMPARE

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LITERAL

|
I
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Y15 7172 I3 712711710
I

LITERAL FIELD

7765

A REG

FIELD

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I
47737727170

03XXXX
1

OPCODE:

MICROCYCLES:
OPERATION:

(RA)- (LITERAL FIELD), Set Status Bit Flags
The 8-bit contents of the
1literal
field,
MI<K11l:4>,
are
siubtracted from the 8-bit contents of RA and the
result sets the NB, ZB, C4, and C8 status bit
flags.
The
contents
of the literal field and RA remain un-

DESCRIPTION:

changed.
STATUS

NB:
ZB:
C4:

BITS:

set
set
set

C8:

CONDITION

CODES:

if
if
if

set

byte result < 0;
byte result = 0;
bit<3> carry out

1f carry out

not

affected

Z:
V:
C:

not
not
not

affected
affected
affected

1l;

cleared otherwise
cleared otherwise
= 1; cleared otherwise

cleared otherwise

EXAMPLE:

ASSEMBLY MNEMONIC:

200,RBAL

;COMPARE RBAL WITH

zZB C4
0
0O

C8
0

200
N
0

2
O

(RBAL)
(=X
@]

(RBAL)

AFTER

4-111

NB
6

ZB C4 C8
0
0
1

200
N
0

Z
0

V
O

o N

BEFORE

200

0340602

OCTAL:

ASSEMBLED

THE

LSI-11

MICROINSTRUCTION

SET

(CBF)
COMPARE

I
|

BYTE

(UPDATE

"13

"12

OPCODE:

CONDITION

"1I1

"10

CODE

(1)1

FLAGS)

REG

132000-132377
1

(132400-132777)

OPERATION:

(RA-(RB)

STATUS

DESCRIPTION:

The

MICROCYCLES:

8-bit

BITS:

CONDITION

(CBF

CODES:

ONLY)

contents

flags

NB,

ZB,

C4,

flags

registers

BIT

code

nated
STATUS

SETS

8-bit

and

FIELD

REG

are

and

the

subtracted

result

sets

the

C8.

CBF

causes

The

contents

remain

unchanged

result

NB:

set

byte

ZB:
C4:

set
set

cleared

if
if

cleared

C8:

set

byte result = 0;
bit<3> carry out

carry

= 1;
cleared

all

from

the

status

bit

condition
the

desig-

cases.

otherwise

otherwise
cleared otherwise

otherwise

set

the

word

result

cleared

set

otherwise

the

word

result

set

arithmetic

cleared

otherwise

set

carry

out

overflow;
=

cleared otherwise
cleared otherwise

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

RDSTL,RSRCL

;COMPARE

RDSTL

WITH

RSRCL

132144

BEFORE

(RDSTL)

AFTER

000

(RDSTL)

IRSRCL) = 377

000

(RSRCL) = 377

4-112

FLAGS

updated.

out

FIELD

THE

CWw

LSI-11l MICROINSTRUCTION

SET

(CWF)

COMPARE WORD

1
15

1
13

(UPDATE

OPCODE:
MICROCYCLES:
OPERATION:
DESCRIPTION:

[

1
9

(1)
8

FLAGS)

B REG FIELD

|
A REG FIELD
3

|
0

BITS:

CONDITION CODES:
(CWF ONLY)

contents

changed

all

NB:
ZB:

set
set

if word
if word

C4:
C8:

set
set

if
if

the

desginated

registers

remain

un-

cases.
result
result

<
=

0;
0;

cleared otherwise
cleared otherwise

bit<3> carry out = 1l; cleared otherwise
carry out = 1l; cleared otherwise

N:
Z:

set
set

if
if

the word
the word

set

arithmetic

set

carry

out

result
result
=

0;
0;

cleared
cleared

otherwise
otherwise

overflow;

cleared

otherwise

<
=

cleared

otherwise

RDST

RSRC

EXAMPLE:

MNEMONIC:

CWF

ASSEMBLED OCTAL:

RDST,RSRC

;COMPARE

BEFORE

NB
6

WITH

133544

AFTER

(RDST)

000001

(RDST)

000001

(RSRC)

000001

(RSRC)

000001

ZB
0

C4
0

C8
0

N
0

Z
0

V
O

ASSEMBLY

133000-133377 (133400-133777)
2
(RA+1:RA)-(RB+1:RB) SETS STATUS BIT FLAGS
The 1l6-bit contents of RB+1:RB
are
subtracted
from
the
16-bit
contents
of RA+1:RA and the result sets
the NB, ZB, C4, and C8 status bit flags.
op code 267
(CWF)
causes the condition code flags to be updated.
The

STATUS

CONDITION CODE

4-113

NB
6

ZB
1

C4
0

C8
0

N
0

Z
1

V
0

C
O

THE

TEST

LSI-11

MICROINSTRUCTION

SET

LITERAL
|

LITERAL

FIELD

]

OPCODE:

05XXXX

MICROCYCLES:

OPERATION:

(RA"AND" (LITERAL

DESCRIPTION:

The

8-bit

are

ANDED

sult

sets

The

STATUS

BITS:

CONDITION

CODES:

with

the
contents

FIELD)

contents

the

NB,
of

remain

ZB,
the

SETS

field,

8-bit

contents

byte

result

byte

result

C4:

not

affected

C8:

not

affected

;"AND"

RBAL

affected

not

affected

not

affected

the

unchanged.

MI<1l:4>,

and

cleared
cleared

otherwise
otherwise

affected

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

200,RBAL

WITH

200,

SET

FLAGS

054002
BEFORE
=

AFTER

377

(RBAL)

(=N
@]

(RBAL)

4-114

re-

and C8
status
bit
flags.
literal field and the designated

set

not

C4,

set

not

FIELD

FLAGS

1literal

ZB:

BIT

the

NB:

STATUS

REG

377

THE

LSI=-1l

MICROINSTRUCTION

SET

(TBF)

TEST

BYTE

(UPDATE

CONDITION

D
R
Y
e
14 7I3 7127117109

OPCODE:

CODE

1
(l1)|

FLAGS)

REG

7 T 675

142000-142377
1

(142400-142777)

OPERATION:

(RB) "AND" (RA)

SETS

DESCRIPTION:

The

MICROCYCLES:

8-bit

contents

and
the
of

C8 status
condition
the

|
|

FIELD

STATUS
of

and

the

bit flags.
code flags

designated

A REG

3T 33T

BIT

FLAGS

are

ANDed

result

with

sets

the

Op code
305
to be updated.

registers

|
|

FIELD

remain

the
NB,

8-bit
ZB,

C4,

(TBF)
causes
The contents

unchanged

all

cases.

STATUS

BITS:

CONDITION
TBF

CODES:

(ONLY)

NB:

set

ZB:
C4:

set
not

byte result
byte result
affected

C8:

not

affected

cleared

otherwise

cleared

otherwise

set

the

byte

result

set

cleared

the

byte

otherwise

result

cleared

otherwise

not

affected

EXAMPLE:

ASSEMBLY

MNEMONIC:

ASSEMBLED

OCTAL:

TBF

RDSTL,RSRCL

;"AND"

RDSTL

WITH

RSRCL,

SET

FLAGS

142544
BEFORE

AFTER

(RDSTL)

201

(RDSTL)

201

(RSRCL)

176

(RSRCL)

176

4-115

THE

LSI-11

MICROINSTRUCTION

SET

(TWF)
TEST

WORD

(UPDATE

CONDITION

~15 "14 I3 "12 "11 10

CODE

(1)

FLAGS)

REG

[

FIELD

A REG

FIELD

OPCODE:

143000-143377

MICROCYCLES:

OPERATION:

(RB+1:RB)
"AND" (RA+1:RA) SETS STATUS BIT FLAGS
The 16-bit contents of RB+1:RB
are
ANDed
with
16-bit
contents
of
RA+1:RA and the result sets

the
the

NB,

the

DESCRIPTION:

ZB,

C4,

(143400-143777)

and

condition
code
the designated

status

bit

flags.

TWF

causes

flags to be updated.
The contents of
registers
remain
unchanged
1in
all

BITS:

CONDITION

(TWF

CODES:

ONLY)

NB:

set

ZB:

set

if word
if word

C4:

not

affected

C8:

not

affected

N:
Z:

set
set

1f
if

cleared

not

result

the word
the word

<
=

result
result

0
0;

STATUS

cleared

otherwise

—e

cases.

cleared

otherwise

<
=

0;
0;

cleared
cleared

otherwise
otherwise

affected

EXAMPLE:

ASSEMBLY

MNEMONIC:

TW RDST,RSRC

ASSEMBLED OCTAL:

;"AND"

RDST

WITH

RSRC,

SET

FLAGS

143144
BEFORE

AFTER

(RDST)

177777

(RDST)

177777

(RSRC)

177777

(RSRC)

177777

4-116

THE

4.3.3.3

Miscellaneous

LSI-11l

MICROINSTRUCTION

SET

Control

Microinstructions

This

group

mi-

croinstructions affects control of the interrupt flags, and the Translation State Register (TSR) contents.
Also included here
is
the
No

Operation
The

(NOP)

microinstruction.

microinstruction

descriptions

are

4-117

follows:

THE LSI-11 MICROINSTRUCTION SET

RESET

INTERRUPTS

______ |
15

~14 "13 "1Z2 "1I1

B REG FIELD

|
4

UNUSED
3

|
0

OPCODE:
MICROCYCLES:
OPERATION:

070000-070377
1
I4 <-- COMPLEMENT OF

(MI<4>),

I5
I6

(MIK5>),
(MI<7>)

DESCRIPTION:

The Control chip internal interrupts are reset
under
control
of the B register field contents.
The A register field is unused.
The status bit and condition
code flags are not affected.

(B)
(B)
(B)
(B)

<-- COMPLEMENT OF
<~- COMPLEMENT OF

=
=
=
=

01,
02,
04,
10,

TRACE

RESET

1I5

COMPLEMENT OF PSW<7>

RESET

EXTERNAL

B register field may
internal interrupts.

BITS:

CONDITION CODES:

INTERRUPT

TEST

UNUSED

The

STATUS

TRAP

RESET

NB:

not

affected

ZB:

not

affected

C4:
C8:

not
not

affected
affected

N:
:

not
not

affected
affected

V:
:

not
not

affected
affected

4-118

reset

any combination of

the

THE

LSI-1l MICRQINSTRUCTION

SET

INTERRUPTS

"I3

OPCODE:

|
I
|
7121110

MICROCYCLES:

070400-070777
1

OPERATION:

<=~

(MI<4>),

<--

(MIK5>),

<--

(MIK7>)

DESCRIPTION:

The

Control

control

chip

the

REG

internal

(B)

02,

BITS:

CONDITION

CODES:

SET

1Ie6

(B)

04,

SET

(B)

10,

UNUSED

The

internal
STATUS

SET I4

field

not

affected

ZB:

not

affected

C4:
C8:

not
not

affected
affected

not

affected

not

affected

not

affected

not

affected

field

are

bit

|
10

set

contents.

status

UNUSED

and

under

The

re-

condition

TRACE TRAP

- COMPLEMENT OF PSW<7>
EXTERNAL INTERRUPT TEST

interrupts.

NB:

interrupts

gister field is unused.
The
code flags are not affected.

(B) = 01,

FIELD

4-119

may

set

any

combination

the

THE LSI-11 MICROINSTRUCTION

SET

RTSR

RESET TRANSLATION STATE REGISTER

OPCODE:
MICROCYCLES:
OPERATION:

DESCRIPTION:

UNUSED

072000-072377
1
(TSR) <--= 0
Execution of this microinstruction resets
translation state register (TSR).
the
1in
bits
TSR should always contain 0
when
returning

to the LSI-11 machine cycle.

back

contain
will
ditions, the TSR
passed to user control store.
STATUS BITS:

NB:

CONDITION CODES:

N:
:

not
not

affected
affected

not
not

affected
affected

ZB:
C4:
C8:

not affected
not
not
not

affected
affected
affected

4-120

Under normal con-

when

THE

LSI-11l

MICROINSTRUCTION

SET

NOP

OPERATION

I
I
I
I
I
I
151
I3 TIZTITTIO
4
T 978

OPCODE:

MICROCYCLES:

177400-177777
1

OPERATION:

DESCRIPTION:

Execution of this
to
the
register
cause

BITS:

CONDITION

CODES:

UNUSED

T 7T

4TI

OPERATION

useful

STATUS

change

for

microinstruction causes
file or flag contents,
the

inserting

program

execution.

NB:

not

affected

ZB:

not

affected

C4:

not

C8:

not

affected

microinstruction

one-microcycle

flow.

delay

affected

not

affected

not

affected

V:
C:

not affected
not affected

EXAMPLE:
ASSEMBLY

MNEMONIC :

ASSEMBLED

OCTAL:

NOP

:NO

OPERATION

177400
BEFORE

CHANGE

AFTER

ONE

4-121

MICROCYCLE

DELAY

no
nor

change
does it
It

in micro-

CHAPTER
MICROPROGRAMMING

5.1

LSI-11

SYSTEM

BUS

TRANSACTIONS

GENERAL

The

LSI-11

chip

set

processor

module

emulate

uses

PDP-11l.

microprogramable

Since

the

LSI-1l

bus

microprocessor

complex

than the microprocessor I/O structure, additional logic
(external
to
the
chip
set), implements the LSI-11 bus.
LSI-11 bus I/0O operations
are easy to microprogram, but this external logic must
be
understood
to
efficiently
microprogram
LSI-11
bus
transactions.
the Circuit
Schematic diagram of the LSI-11 CPU should be referenced for the
discussion to follow.

5.2
The

LSI-11
LSI-1l

SYSTEM

BUS

INTERFACE

LOGIC

OVERVIEW

processor

module contains logic to interface the
microproLSI-1ll system bus.
This logic performs two functions:
the sequencing and timing of control signals which appear
at
the
Control
<chip, and (2)
it provides an electrical buffer
between the MOS LSI microprocessor and the TTL
system
bus.
Further
discussion
of
this
material is contained in The Microcomputer Handbook.
Figure 5-1, Bus I/0 Control Signal Logic and Figure 5-2, Interrupt Control and Reset Logic, should be referenced for this section.

cessor
(1) it

to
the
modifies

This logic overview lists each control signal first
in
its
original
form and then in its final form.
For example, the microprocessor originates WSYNC H which becomes the system bus signal BSYNC L.

MICROPROGRAMMING

Bus

LSI-11

I/0

SYSTEM

Control
Figure

BUS

Signal

TRANSACTIONS

Logic

5-1

SYNC (1) H

REPLY (1) H—

)

WSYNC H

‘//\\>

DMG CYH
|—0

SYNC H
SYNC
Af

SYNC L
PH3

BSYNC L

INIT()H

L —

SYNC ()
L
SYNCR

Iak L
WWB

)

|——0

H =

SYNCR L

BWTBT

INIT (1) H —d

WDIN H
PROCESSOR

CONTROL

DIN L

1[>_‘> |

4> l

_BDIN L
DINR H

DOUT

LATCH
PH2

INIT (1) H—O )

I.C.

WTBTR

DIN H

DINR L

]

o
4

DC LO L 1
WDOUT H

REPLY (1)

L—

+ DOUT (1) L
DOUT
F/F

PH3

DOUT (1)H|_°

SYNG H_T

BDOUT
DOUT
L

ITUIH

INIT

-~ DOUT (1) H
DOUTR H

1/0 H

REPLY H

——J

(M H

REPLY (1) L4—l
BUSY

F/F

DMR (1) L

__ BRPLY L

1. RPLYR H

le—— PHI

INIT (1) 1_—I

v
MR-1058

MICROPROGRAMMING LSI-11 SYSTEM BUS“‘I'VRANSACTI'[ONS

Interrupt

Control

and

Figure

Reset

Logic

5-2

'ROM CODE 15L—‘L
= FDIN (1)

FAST

DIN

F/F

START

FDIN (1) L

TIMEOUT

SYNC H

ws/

ERROR F/F
TFCLRL (ROM CODE 12) ——

UP MICROCODE

SELECT JUMPERS

—r.L

o (0

INIT (1) L

FAST

WDAL0:3> H

DIN

oata

MUX

TERRUH
PFAIL

PFAIL (1) L

(3)

PH3 H —] 5-STAGE
TIME-OUT
REPLY

Lyt

(1)
H

TERR L

—O

COUNTER

RESET L

o—
RESET

LATCH

pEee——ePH2 H —{(CLK)

+3V —»

BPOKH

BHALT L

‘“D

PWR

l-'vPFAu_ H

POWER

F,_f\,”,;

FAIL/

HALT
CaTen

PFAIL (1)L

D c

IPIRQ H

HALT L

(CLR)

PFCLR L

BDCOK H

*———CD——%

DC LOL

CONTROL

PROCESSOR

CHIP

H— DC LO L

= | ®B1acko L
@m

;

(

JAK L

EDMG CYH rakmH

TAK (1)H E<‘L

INIT ()
H

INT

WIAK H

;

ACK
F/F

IAK (1) L

je—PH| L

DIN H—T
o)

BIRQ

(CLR)
INTERRUPT

10 IRQ (1) H

| REQ LATCH
|

EVENT(OR LTC) W3
—

INTERRUPT

DISABLE

JUMPER

BEVNT

EVENT (1) H

EVNT

F /F

f>
REFRESH

JUMPER

DISABLE

EFCLRL

_T’

MEMORY

REFRESH

REQUEST

T wa

<
oo iz,

EQVES

Pz H—af S

PROC MICROCODE

EVIRQ (1) H

EVENT

'NRTEEQRUREUS':’TT

LATCH

REF

RFIRQ (1) H

REQ

RFOSC H

F/F

L~ RF REQ (1) L

RFSET L

{ROM CODE 13}
MR-103¢

MICROPROGRAMMING LSI-11 SYSTEM BUS TRANSACTIONS

5.2.1

WSYNC

- BSYNC

WSYNC H is asserted by the Control chip as part of
the
execution
of
any Read or Write microinstruction.
1In all cases, this signal appears
at the beginning of PH2 following the microcycle in which the microinstruction
was
executed.
The interface logic circuitry provides the
functions:

following

~DELAYS

the appearance of WSYNC H as BSYNC L

PH3 by

means of the SYNC
trailing edge of PH3 L).

Flip Flop

until

(clocked

after

-MAINTAINS BSYNC L in the asserted state until after BRPLY

the

has been terminated by the slave device at the end
of the transaction.
This serves to keep the
device
recognition
signal
(on
the
device) stable
until the device has completed its role in the bus
transaction.

-INHIBITS

5.2.2

- BWTBT

WWB

the appearance of WSYNC H as BSYNC L during interrupt
operations.
The
two
acknowledge microinstructions, RA and WA, cause the Control
<chip
to
assert
WSYNC
H
simultaneously with WIAK H.
The
WIAK H signal forces the SYNC
F/F
to
the
reset
state which inhibits BSYNC L.

WWB H is asserted by the Control

<c¢hip

places address information on the bus.
ly as BWTBT L
(delayed
only
by
the

during

the

microcycle

which

This signal appears immediateinverting
buffer
propagation

delay)
.

5.2.3

WDIN

- BDIN

WDIN H is asserted by the Control chip during the microcycle following
All Read microinstructions
of address information.
transmission
the
cause this signal to be asserted at the beginning of PH2.
WDIN H
appears
immmediately
as
BDIN L (delayed only by two invertors and the
inverting buffer propagation delay).

5.2.4

WDOUT

BDOUT

WDOUT H is asserted by the Control chip at the beginning of the microcycle
which
follows transmission of address information.
All Output
microinstructions assert this signal asserted at the beginning of PHI.
WDOUT
H
1is also asserted as part of the DATIO bus transaction.
This
logic provides the following 4 functions:
-DELAYS

the appearance of WDOUT H as BDOUT L
PH2, by means of the DOUT F/F (which
the leading edge of PH3).

until
after
is clocked by

MICROPROGRAMMING

-INHIBITS

the

LSI-11

appearance

passive

long

SYSTEM

BUS

BSYNC
L

enough

for

TRANSACTIONS

until

the

BRPLY

has

been

F/F

have

been

reset.
The reset state of the REPLY F/F
ANDed with WDOUT H in order for the DOUT

set.

This

placed

has
-CANCELS

the

bus

1inhibits
until

ended.

BDOUT

ceipt

when

by
addressed
the

the

BRPLY

output

—INHIBITS

mechanism

F/F

BRPLY

the processor
device.

setting

the

DOUT

sive.

5.2.5

BRPLY

bus,

the

bus,

vides

asserted

in
system

the

case

the

case

bus

asynchronous

tne

the

input

-DELAYS

addressed

the

device

appearance

BRPLY

asserted

bling
PH3

also

both

circuitry

the

F/F

when

WSYNC

pas-—-

when

data

placed

the

slave

the

device

cycle.

cause

This

signal

BRPLY

logic

pro-

until

the

be-

appear

the

input

valid

I/0

the BDOUT
(1)

which

F/F.

This

operation

signal

F/F

Control

progress

negating

ANDed with WDOUT
mechanism accelerates
by

the

addressed

chip

only

(BSYNC

the

was

bus

output

REPLY
the

when

signal
to

set
release

device

ac-

the

DOUT

the

case

transaction.

H
the

BUSY

BUSY
and

execution is suspended
the system bus becomes

tration
bus.

accepted

for

the

The

re-

data

state

set
L

BUSY

Read

the

affects

when

action.
of

that

plished

BRPLY

set

of
each
new microcycle.
This is accomby clocking the REPLY F/F with PH1 H.

system

5.2.6

being
action

been

microinstruction

tive).

—-CANCELS

from
device

has

functions:

ginning

-ENABLES

been

indicates

or data has been accepted from
operation.
Propagation delays along

an output
response delays

has

operation,

with

following

slave

and

data

all

must
F/F

when

F/F

input

Write

set

the

and

checked

Control

not

BUSY

Control

chip

the

microinstructions.

chip.

dependent
If

BUSY

master
'

device

has

control

ena-

during

asserted,

and the pending bus transfer is
delayed
free.
BUSY H is also asserted by the DMA

another

any

the

until
arbi-

LSI-11

MICROPROGRAMMING

5.2.7

WIAK

BIACK

LSI-11

SYSTEM BUS

TRANSACTIONS

WIAK H is asserted by the Control chip during execution of either Acknowledge
microinstruction,
RA or WA.
This signal is asserted at the

beginning of PH2 (simultaneously with WSYNC).
Because
BSYNC
L
does
not take part in LSI-11 system bus interrupt transactions, the WSYNC H
- BSYNC L interface logic inhibits BSYNC L.
The interface logic associated
with
the
Control chip WIAK H output provides the following 2
functions:

-DISABLES

the

INT
ACK
F/F
(interrupt
acknowledge)
the appearance of WDIN H.

until

after
-DELAYS

WIAK H
of the

(as BIACK
assertion

H)
of

until one
BDIN L.

microcycle

after

PH2

These two functions assure that BDIN L
arrives
at
the
1interrupting
device before BIACK H.
Note that the Write Acknowledge microinstruciton will never produce a BIACK H 51gnal because WDIN H is not asserted
as part of a write operation.

5.3

5.3.1

THE

DATA-INPUT

DATI

(DATI)

Operation,

OPERATION

Minimum Execution Time

Figure 5-3 illustrates the control signal action relevant
to
a
DATI
operation
which
executes
with minimum possible delay.
The microinstruction sequence presented is Read, Input Word,
Next
Microinstruc-

Rb,Ra

IwW

Microinstruction

The individual
with
the
aid

ADDRESS DEVICE, SIGNAL DIN
INPUT LOW AND HIGH BYTE

-e

tion:

events which occur in
of Figure 5-3, which

the DATI
costains

operation are
the microcycle

discussed
reference

numbers.
Microcycle
The

Read

execution

the

Read

microinstruction

(R)

crocycle causes no change in the Control chip.
tion executes to completion because REPLY H and
asserted during PH3.
Microcycle

Input Word

the

first

mi-

The microinstrucBUSY H
were
not

(Wait)

Because the Read microinstruction executed to
completion
during
Microcycle 1, the address information is placed on BDAL<K15:00> at
the beginning of PH1l.
WSYNC H is asserted at PHZ, causing
BYSNC
L
to
be
asserted at the beginning of PH4.
Since the addressed
device can only respond to BDIN L, which has not yet been asserted,
the
Input Word microinstruction check of REPLY H during PH3
fails

and

initiates

the Wait

state.

MICROPROGRAMMING

LSI-11

Minimum

SYSTEM

DATI

Figure

ONE

CYCLE

BUS

TRANSACTIONS

Cycle

5-3

ONE

CYCLE

}-— MICRO —-%— MICRO —s#— MICRO —wle— MICRO —sle— MICRO

—}e—

ONE

MICRO —»
CYCLE

PHASE
N

ONE
PHASE

/
\_

TWO
PHASE

THREE

PHASE

FOUR

COSYNC H

BSYNC L

WDIN H

BDIN L

BRPLY L }
DEV
RESP

REPLY H

BUSY H

“X

BDAL L

READ

ADDRESS

2INPUT (WAIT)

;L DATA

INPUT (WAIT)4

)L
INPUT LOW
BYTE

INPUT HIGH 6
BYTE

NEXT INST

(WAIT)
MR-1057

MICROPROGRAMMING LSI-11

Microcycle 3

Input Word

SYSTEM BUS TRANSACTIONS

(Wait)

Because the Read microinstruction was completed during Microcycle
1,
WDIN H is asserted at the beginning of PH2.
The assertion of
1In response to BDIN L, the addressed
BDIN L follows immediately.
device places data on BDAL<15:00> and asserts BRPLY L to the pro-

However, the REPLY F/F is

cessor.

REPLY H remains passive

(which

not

clocked

To assure minimum delay in the execution of

BRPLY
here,
illustrated
time to set the REPLY F/F

PHl1

until

and

in turn maintains the Wait state).
the

DATI

operation

L must be received by the processor in
at
the
beginning
of
Microcycle
4.

Otherwise,
the
Wait state will continue throughout Microcycle 4
and the next opportunity to set the
REPLY
F/F
will
not
occur
until the beginning of Microcycle 5.

Input Word

Microcycle 4

(Input Low Byte)

The asserted state of BRPLY L sets the REPLY F/F at the beginning
REPLY H is now active, the Data chip stores the
Since
PHI.
of
low byte

its designated register.

Input Word

Microcycle 5

(Input High Byte)

chip
Data
the
true,
still
1is
Since the PH3 check of REPLY H
stores
the
high
byte in its designated register (determined by
complementing the low-order bit of the
A
register
field).
No
control
signals
are
changed by either the processor or the addressed device.

Next Microinstruction

Microcycle 6

(Possible Wait)

Because the Input Word microinstruction

executed

completion

L goes passive at the end of PH 1.
BDIN
5,
during Microcycle
This causes the addressed device to (1) make BRPLY L go passive,
Since the SYNC F/F is
(2) remove its data from BDAL<15:00>.
and
locked into its Set state due to the set state of the REPLY

BSYNC

F/F,

asserted.

remains

Write
If the Next Microinstruction belongs either to the Read or
of BUSY H is checked and a Wait state will be
state
the
group,

assure
To
Any other microinstruction will execute.
initiated.
minimum
delay in the execution of the DATI operation illustrated
here, BRPLY L must go passive at the processor in time
to
reset
Otherwise the
at the beginning of Microcycle 7.
F/F
REPLY
the
the
until
occur
next opportunity to set the REPLY F/F will not

8, and a possible Wait state initiated
Microcycle
of
beginning
during Microcycle 6 will continue at least into Microcycle 8.

Microcycle

Next Microinstruction

Since BRPLY L was negated by the addressed device during Microcy-

cle

6, the REPLY F/F is clocked to the reset state at the begin-

F/F

also

ning of PHl1l, which cancels BUSY H.
allows

the end of PH3,

the SYNC

F/F

The reset state of the
clocked

which makes BSYNC L passive.

the

reset

state

MICROPROGRAMMING

5.3.2

DATI

Operation,

LSI-11

Delayed

SYSTEM

Execution

BUS

TRANSACTIONS

Time

Figure 5-4 illustrates the control signal action for
a DATI
operation
in
which
execution
1is delayeat
d 3 points.
The delays occur during
the Read microinstruction and in the response of the
addressed
device
assertion
here

Rb,Ra

Read

BUSY

input

Input

BDIN

Word,

ADDRESS
INPUT

events which occur in
of Figure 5-4, which

numbers.

The

negation

Read,

Microinstruction

The individual
with
the
aid

Microcycle

and

the

presented

wme

both

the

control

itted
Microcycle

from

the

AND

microinstruction

Microinstruction:

SIGNAL

HIGH

DTN

BYTE

the DATI
contains

operation are
the Microcycle

discussed
reference

(Wait)
the

signal

conclusion

The

DEVICE,

LOW

Control

chip

tire microcycle causing the PH3 test
instruction to fail.
The Wait state

Other

L.
Next

-y

sequence

actions

figures.

during

I/0

asserted

during

the

en-

performed by the READ microis
initiated
during
PH3.

microcycle

DMA

1 which relate to
transaction have been om-

Read

Since the BUSY H signal goes passive prior to PH, the
BUSY H test
is
passed,
the
Wait
state is terminated and the Read microinstruction executes to completion.
Microcycle

Input Word

Because

the

Read

(Wait)

microinstruction

completed

during

the
address information is placed on BDAL<15:0> at
of PHl.
WSYNC H is asserted at PH2, causing BSYNC
serted

the

only

respond

Input

Word

initiates
Microcycle

BDIN

the

state

Microcycle
In

the Wait

Since

the

asserts

BDIN

Wait

Word
L

yet

asserted,

during

PH3

beginning

L
to
be
addressed device

been
H

completed

beginning

Since
state

as-

can
the

fails

and

there

during
PH2.

1is

Microcycle

The

assertion

change

1in

2,
of

the

maintained.

(Wait)

asserted

BRPLY
L
change in the

the

(Wait)

immediately.
H,

not
of

microinstruction

Input

there is no
intained.

Word

asserted

response

device

Read

follows
of

PH4.

state.

Input

Because

to BDIN L, which has
microinstruction check

WDIN

beginning

Microcycle

and
state

during

places
of

Microcycle

the

addressed

data on BDAL<15:00>.
REPLY H, the Wait state

Since
is

ma-

MICROPROGRAMMING

LSI-11

Delayed

SYSTEM BUS TRANSACTIONS

DATI

Figure

ONE

CYCLE

ONE
PHASE

THREE
PHASE

FOUR

/" \
44//—\\

/\.

//_\\

NN\

//—\

j/_\\

—

AN\

TWO
PHASE

5-4

ONE
ONE
ONE
ONE
ONE
ONE
r¢— MICRO —» l#t—— MICRQ —btg—— MICRO ~—mle— MICRO—»] lé— MICRO —»{a— MICRO
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE

le— MICRO
—le— MICRO
—]
PHASE

Cycle

WSYNC

/N N

CYCLE

—~

J/F\\

ONE

—#14— MICRO -

//_\\

BSYNC L

,/—“
/]

WDIN

BDIN L

3RPLY L

REPLY H

BUSY H

BDAL L

A
A

ij:
1 READ (WAIT}

ADDRESS
READ

;}(fi

3 INPUT {WAIT) 4 INPUT IWAIT)

DATA
5 INPUT (WAIT} 6 INPUT LOW
BYTE

7 INPUT HIGH

8YTE

NEXTINST
(WAIT)

NEXTINST

NEXTINS

(WAIT)
[EITRTIE

MICROPROGRAMMING

BRPLY

have

had

become

been

LSI-11

asserted

active

during

SYSTEM

during

Input

Word

(Input

TRANSACTIONS

Microcycle

ditional delay in device response
execution of the DATI operation.
Microcycle

BUS

adds

Low

one

illustrated,

full

microcycle

would

the

ad-

the

Byte)

- The
of

asserted state of BRPLY L sets the REPLY F/F at the beginning
PHI.
Since REPLY H becomes active, the Wait state is terminated during the PH3 REPLY H check and the Data chip
stores
the
low byte in its designated register.

Microcycle

Input

Since the
the
high

menting

Microcycle

are

changed

Next
the

Input

Word

operation,

immediately,
data

due

the

also

set

the

state

and

the

processor

(Possible

goes

completed

passive.

addressed
SYNC

the

BDIN

F/F,

new

microinstruction

group,

Wait

I/O

state is
operation.

response

Microcycle

Since

the

belongs

state

initiated

Any

negated

BSYNC

would

during

BRPLY

L was

negated

F/F

the

Microcycle

addressed

of PH1, which cancels BUSY H.
also allows the SYNC F/F to be

end

the

PH3,

Response

Note

BRPLY

had

delay

tion

passive

which

been

during

device

the

DATI

the

and

remains

Read or

BUSY

its

set
as-

Write

tested

beginning
of
will execute.

the

addressed

from BDAL<15:00>.
the possible WAIT

Microinstruction

ning
F/F

come

passive

remove
into

(Possible Wait)

maintained.

ad-

Microcy-

the end
during

goes

delays the
microinstruction

Device

which

other

Microinstruction

BDIN

either

cle

the

at
H

locked

device negates
BRPLY
L
and removes its data
» 8ince there is no change in the state of BUSY H
state

during

device

F/F

the

Wait)

made passive
enable REPLY

the

microinstruction

Microcycle

the

Since

serted.

either

and WDIN H are
be asserted to

which informs

microinstruction

from BDAL<15:00>,

state

Byte)

Microinstruction

7,
both WSYNC
H
Since WDIN H must

DATI

High

of REPLY H again passes, the Data chip
stores
its designated register
(determined by compleorder bit of the A
register
field).
No
other

device.

Because

cle
PHl.

low

signals

" dressed

(Input

PH3 test
byte in

the

control

Word

clocked

makes

BSYNC

negated during
Microcycle 9.

response

adds

operation.

one

the

device

reset

during

state

Microcy-

the

begin-

The reset state of the
REPLY
clocked to the reset state at

passive.

Microcycle
As

full

8, BUSY H would beillustrated, the additional

microcycle

the

execu-

MICROPROGRAMMING LSI-11 SYSTEM BUS TRANSACTIONS

DATI Microprogramming Summary

5.3.3

The DATI operation, implemented by the Read-Input microinstruction seqguence, allows for variable delays in addressed device response to the
1In any conventional machine confiassertion and negation of BDIN L.
responses will likely not be the minimums disguration the device
otherwise
To make better use of what would
cussed in section 5.3.1.
be Wait-induced microprocessor idle time, data manipulation microinInput microinstrucstructions may be inserted between the Read and
required to execute the inserted data manipulation
time
The
tions.
the
than,
1less
microinstructions should optimatlly be close to, but
worst case maximum device response to the assertion of BDIN L, so the
In
time.
of
1lengths
LSI-11 bus will not be held busy for abnormal
the microprogram will execute with minimized or even zero
this way
resNo difficulty is encountered if addressed device
overall delay.
causes REPLY H to be asserted before completion of the inserted
ponse
data manipulation microinstruction sequence is completed.

Once the Input microinstruction has completed,
the
addressed
device
The microproessor may be best used
data and negates BRPLY L.
removes
the
check
not
at this point by executing microinstrucitons which do
status of either

To summarize,
DATI

BUSY H,

the delay in execution of

operation may be minimized

if:

micrprogram

containing

The microinstruction immediately preceding the Read
microinstruction does not cause BUSY H or REPLY H to be asserted.

The addressed device responds to the assertion of

The addressed device responds to the negation of

The microinstruction

utilized
and

BDIN L

minimum time.

struction does

As an alternative
Read

REPLY H or

not

immediately following the Input microin-

check REPLY

to condition

BDIN

above,

H or

BUSY

unavoidable

delays

may

inserting Data Manipulation microintructions between the

Input microinstructions.

MICROPROGRAMMING

5.4

THE

5.4.1

DATA-OUTPUT

DATO

(DATO)

Operation,

LSI-11

Minimum

Execution

W
Ow

Word,

Rb,Ra
Rb,Ra

numbers.

Microcycle

Microinstruction:

ADDRESS

OUTPUT

events which occur in
of Figure 5-5, which

DEVICE,

SIGNAL

DOUT

WORD

Microinstruction

The individual
with
the
aid

The

Output

Time
action for a DATO
operation
microinstruction sequence pre-

The

Write,

TRANSACTIONS

signal

BUS

OPERATION

Figure 5-5 illustrates the control
which executes with minimum delay.
sented

SYSTEM

the DATO
contains

operations are
the Microcycle

Write

execution

of the Write microinstruction in the first microcycauses
no change in the control signals.
The microinstrucexecutes to completion because REPLY H and BUSY H are
unas-

cle
tion

serted

Microcycle

during

PH3,

Output

Because

the

Write

Word

(Wait)

microinstruction

completed

during

Microcycle

the address information is placed on BDAL<15:00> at the
of PHl.
The WWB H signal is asserted at the
beginning

indicating
a
byte
immediately.
WSYNC

asserted

only

the

Wora

Because

ing

the

beginning

the

WAIT

Output

BDOUT

at
is

PH4.

which

the

not

check

microinstruction

during Microcycle
The

which

allows
of

Since

microinstruction,

WWB

returns

However,

remains

passive

H
PHl.

the

yet

BWTBT
BSYNC

addressed

been

beginning
of
PHI,

L
L

follows
to
be

device

can

asserted,
during

the

PH3

fails

the

fail-

(Wait)

beginning

asserted.

assertion of
PH2, causing

Since

has

state.

Word

PHl.

microcycle,
F/F

microinstruction

of REPLY H

beginning

this

operation.
The
is asserted at

Output Word

test

DOUT

to BDOUT

initiates

Microcycle

the

respond

Output

and

discussed
reference

PH3.
this

F/F

the

executed

WDOUT H

the

reset

asserted
state

asserted WDOUT H

When
example

and

subsequently
BWTBT L remains

the

DOUT

contains

F/F
the

during

set
is

Output

BWTBT

the
set,
Word

L are
negated
at
the
beginning
of
asserted past this point
only in the case of an Output Byte operation.
Also
during
PH1,
the
Data
chip
simultaneously places two bytes
(a full word) of
data on BDALK15:00>.
In response to the assertion
of
BDOUT
L,
the addressed device accepts the data output by the processor
and
so

BRPLY

the

which

F/F

maintains

only

the

clocked

Wait

state.

PHI1,

MICROPROGRAMMING LSI-11 SYSTEM BUS TRANSACTIONS

Minimum DATO
Figure

ONE

PHASE

PHASE
TWO

PHASE
THREE

ONE

CYCLE

—
«— MICRO —» 4—— MICRO — *+—MICRO
—® <¢—MICRO

CYCLE

ONE

5-5

— N\
N/)

)

N\ /N 4 /N

VNS N\ VA /N

PHASE

——

FOUR

COSYNC

L
BSYNC

WDOUT
H

L
BDOUT

L
BWTBT

r\fQSFf

ONE

+—MICRO—®

Cycle

—

BRPLY
L

|DEV

RESP

REPLY
H

JX{ADDRESS
1

WRITE

DATA

OUTPUT

(WAIT)

OUTPUT

(WAIT)

:)
4

OUTPUT

WORD

NEXTINS
MR-1061

BDAL
L

MICROPROGRAMMING

LSI-11

SYSTEM

BUS

TRANSACTIONS

To assure minimum delay in the execution of
the
DATO
operation
illustrated
here,
BRPLY
L must be received by the processor in
time to set the REPLY F/F
at
the
beginning
of
Microcycle
4.
Otherwise,
the
Wait state will continue throughout Microcycle 4
and the next opportunity to set the
REPLY
F/F
will
not
occur
until the beginning of Microcycle 5.

Microcycle 4
The

| Output Word

asserted

state

BRPLY

sets

the

F/F

the

beginning

of
PHI.
Since REPLY H became active during PH3, the Wait state
is terminated at the PH3 REPLY H test and the Output Word
microinstruction
executes
o completion.
The set state of the REPLY
F/F

also

negates

the

DOUT

F/F

input,

and

«clocked

the

reset
state
at
the
beginning of PH3 which negates BDOUT L and
cancels REPLY H.
Note that the Control chip determines the state
of
REPLY
H
at
the
beginning of PH3, thus recognizing the addressed device response before REPLY H is canceled via the resetting
of
the
DOUT F/F.
1In response to the negation of BDOUT L,
the addressed device negates BRPLY L.
To. assure minimum delay in the execution of
the
DATO
operation
illustrated,
BRPLY L must go passive at the processor in time to
reset the REPLY F/F at the beginning of Microcycle 5.
Otherwise
the
next opportunity to reset the REPLY F/F will not occur until
the beginning of Microcycle 6.
Microcycle

Since BRPLY
clocked
to

Instruction

L was negated during Microcycle
4, the REPLY
the reset state at the beginning of PH1l, thus

ling BUSY H,
Because
during
Microcycle 4,
PH2

and

WDOUT

Data:

chip

removes

PH4,

SYNC

Any type of
since
the
gating BUSY

5.4.2

DATO

the Output Word
WSYNC H is made

made

the

clocked

passive

output word
to

the

microinstruction
completed
passive at the beginning of

the

beginning

from BDAL<K15:00>

passive

state

the

microinstruction may be executed during
REPLY F/F was reset at the beginning of
H.

Operation,

Delayed

Execution

F/F
is
cancel-

PH4.

The.

the

end

PH3.

Microcycle 5,
PHl1l, thus ne-

Time

Figure

5-6 illustrates the control signal action for a DATO
operation
which
execution
1is delayed at 3 points.
The delays occur during

Rb,Ra

Microinstruction

The individual
with
the
aid
numbers.

Rb,Ra

OwW

ADDRESS

OUTPUT

DEVICE,

SIGNAL

DOUT

WORD

‘W

the execution of the Write microinstruciton and in the response of the
addressed
device
to both the assertion and negation of BDOUT L.
The
microinstruction sequence presented here is Write, Output
Word,
Next
Microinstruction:

events which occur in
of
Figure 5-6 which

the DATI
contains

operation are
the microcycle

discussed
reference

MICROPROGRAMMING

LSI-11

Delayed

SYSTEM

DATO

Figure

BUS

TRANSACTIONS

Cycle

5-6

ONE

CYCLE

ONE
ONE
la— MICRO
—le— MICRO
—

f¢— MICRO- —wt@— MICRO —wte— MICRO —-—.L— MICRO ——-’L"— MICRO —
PHASE

ONE
PHASE

AN\

_/\

TWO
PHASE

PHASE

FOUR

CYCLE

THREE

CYCLE

/‘\

WSYNC

BSYNC
L

WDOUT
H

\
\

BDOUT
L

h N

BWTBT
L

DEV

DEV _ |

BRPLY L

’

RESP

REPLY H

BDAL
L

WRITE

(WAIT)

WRITE

RESP

TM+

aporess
X | pata
OUTPUT

(WAIT)

OUTPUT

(WAIT)

)
5

OUTPUT

(WAIT)

OUTPUT

WORD

NEXTINS

(WAIT)

NEXTINS

10062

MICROPROGRAMMING LSI-11 SYSTEM BUS TRANSACTIONS

Microcycle

Write

(Wait)

The BUSY H input to the Control chip (not shown in the timing diagram)
is asserted during the entire microcycle which causes the
PH3 test performed by the Write microinstruction
to
fail.
The
Wait state is initiated during PH3.
Other control signal actions
during Microcycle 1 which relate to the conclusion of a
previous
I/0 or DMA transaction have been omitted from the figures.
Microcycle

Write

Since the BUSY H signal goes passive prior to
PH3,
the
BUSY
H
test is passed, tle Wait state is terminated and the Write microinstruction executes to completion.
Micrcecycle

Output Word

(Wait)

Because the Write microinstruction completed during Microcycle 2,
the address information is placed on BDAL<K15:00> at the beginning
of PHI1.
The WWB

cates

signal is asserted
byte operation.
The

the beginning of PH1 which
indiassertion of BWTBT L follows immedi-

ately.

WSYNC H is asserted at PH2, causing BSYNC L to be asserted at the
beginning of PH4.
Since the addressed device can only respond to
BDOUT L, which has not yet been asserted, the Output Word
microinstruction
check
of REPLY H during PH3 fails and initiates the
Wait state.
Microcycle

Output Word

(Wait)

Because the Output Word microinstruction executed until the failing
test
of REPLY H during microcycle 3, WDOUT H is asserted at
the beginning of PHl.
The REPLY F/F is in the reset state during
this microcycle allowing the asserted WDOUT H to set the DOUT F/F
at the beginning of PH3.
When the DOUT F/F is set,
BDOUT
L
|is
asserted.
Since
this example contains the Output Word microinstruction, WWB H and thus BWTBT L are negated at the beginning of
PH1.
BWTBT L remain asserted past this point only in the case of

a Output Byte operation.
Also during PHl1l, the Data
chip
simultaneously
places two bytes (a full word) of data on BDAL<K15:00>.
Since REPLY H is unchanged in this microcycle, the Wait state
is
maintained.
Microcycle

Output Word

(Wait)

In response to BDOUT L, the addressed device accepts the data
on
BDAL<15:00>
and
returns BRPLY L to the processor.
However, the
REPLY F/F is only clocked at PH1
and
REPLY
H
remains
passive
which maintains the Wait state.

If BRPLY L had been asserted during Microcycle 4, REPLY
H
would
have
become active during Microcycle 5.
As illustrated, the additional delay in device response adds one full microcycle to the
execution of the DATO operation.

MICROPROGRAMMING

Microcycle
The

of
ed

Output

asserted

state

LSI-11

SYSTEM

BUS

TRANSACTIONS

Word

BRPLY

sets

the

F/F

the

beginning

PHl.
Since REPLY H became active, the Wait state is terminatat the PH3 REPLY H check and the Output Word
microinstruction

executes
to completion.
The set state of the REPLY F/F
gates the DOUT F/F input, and it is clocked to the reset
the
beginning
of PH3 which negates BDOUT L and cancels
Note that
beginning

device

the
of

also nestate at
REPLY H.

Control chip determines the state of REPLY H at the
PH3, thus recognizing the response of the addressed

before

cancelled

via

the

resetting

the

DOUT

F/F.

Microcycle

Next Microinstruction

(Possible Wait)

Because the Output Word microinstruction completed during
Microcycle
6,
WSYNC
H
1is
made passive at the beginning of PH2 and
WDOUT H is made passive at the beginning of PH4.
The
Data
chip
removes
the
output word from BDAL<15:00> at the end of PH4.
1In
response to the negation of BDOUT L, the addressed device negates
BRPLY
L.
However, since the REPLY F/F is clocked at PH1l, it remains in the set state which asserts BUSY H.
the

group,

the

Microinstruction

state

BUSY

belongs

either

checked

and

the

BRPLY

had

been

negated

during

Microcycle

Write

Wait

state

will
next
I/0
operaimmediately.

the

be initiated which delays the beginning of the
tion.
Any other microinstruction will execute
If

Read

new

F/F

would
have
been reset at the beginning of Microcycle 7.
As illustrated, the additional delay in device response adds one
full

microcycle
Microcycle
Since

the
Next

BRPLY

was

execution

the

DATO

operation.

Microinstruction
negated

during

Microcycle

the

clocked
to the reset state at the beginning of
ling BUSY H.
The reset state of the REPLY F/F

PH1l,
also

SYNC

negates

F/F

clocked

the

reset

state

which

F/F

thus cancelallows
the
BSYNC

the microinstruction in Microcycle 7 caused the microprocessor
to
initiate
the
WAIT state, the microinstruction will now execute.
Otherwise microinstruction execution proceeds normally.

MICROPROGRAMMING

5.4.3

LSI-11

DATO Microprogramming

SYSTEM BUS

TRANSACTIONS

Summary

The DATO operation, as implemented by the
Write-Output
microinstruction
sequence, allows for variable delays in addressed dev-

ice

response

to both the

However,
there
DATO operations

assertion

and

negation

BDOUT

1is
an important difference between the DATI and
regarding delay handling.
To optimize
micropro-

cessor
performance in the DATO context, the Output microinstruction must immediately follow the Write microinstruction.
This is
necessary
because
BDOUT
L is a function of the Output microinstruction.
In contrast, BDIN L is a function of a Read
microinstruction.
Therefore, there is no opportunity (in the DATO context) to make use of idle time caused by the
delay
of
the
addressed device to respond to the assertion of BDOUT L.
Once BRPLY L is received, indicating that
the
addressed
device
has stored the output data, the LSI-1ll system bus interface logic
proceeds immediately to negate BDOUT L.
This action
accelerates
the
negation
of
BRPLY L by the addressed device.
The microinstructions which follow the Output microinstruction should not be
of the type which check REPLY H or BUSY H,
Otherwise the resulting Wait state(s) will cause microprocessor idle time.
To

summarize,

the

delay

the

execution

- taining a DATO operation may be minimized
1.

if:

microprogram

con-

The microinstruction immediately
preceeding
the
Write
microinstruction
does not cause BUSY H or REPLY H to be
asserted.

The

Write

microinstruction

immediately

followed

The addressed device
L in minimum time.

responds

the

assertion

The

responds

the

negation

‘

Output microinstruction.

addressed

device

BDOUT

in minimum time.

The microinstruction immediately

‘microinstruction does

not check

following

REPLY H or

the

BUSY H.

Output

MICROPROGRAMMING

5.5

THE

5.5.1

DATA-INPUT-OUTPUT

DATIO

Operation,

Figure

5-7

DATIO

operation

struction
data,

LSI-11

illustrates

(DATIO)

BUS

TRANSACTIONS

OPERATION

Minimum Execution
the

which

SYSTEM

control

executes

Time

signal

with

action

minimum

sequence presented is
Read,
Input
Word, Next Microinstruction:

Rb,Ra

;

ADDRESS

Rb,Ra

;

INPUT

LOW AND

Modify the data
OwW
Rb,Ra

;
;

MODIFY
SIGNAL

DATA
DOUT,

[

Microinstruction

The individual
with
the
aid

events which occur in
of Figure 5-7, which

DEVICE,

The

Word,

Output

relevant

delay.

SIGNAL

HIGH

microin-

Modify

the

DIN

BYTES

OUTPUT WORD

the DATIO operation are
contains the Microcycle

discussed
reference

numbers.

Microcycle

Read

The

execution

cle

causes

tion

executes

shown)
Microcycle

are

of
no

the Read
change in

completion

unasserted

Input

The

Control

chip

performed

microinstruction in the first
microcythe control signals.
The microinstruc-

Word

and

BUSY

(not

(Wait)

determines
by

because

PH3.

means

that
of

the

Read-Modify-Write
argument

operation

contained

the

is
re-

gister field of the Input Word microinstruction.
It stores
this
information
internally and will not conclude the DATIO operation
until an Output microinstruction is successfully completed.
Because

the

Read

microinstruction

completed

during

Microcycle

the address information is placed on BDAL<15:00> at
of PHl.
WSYNCH is asserted at PH2, causing BSYNC L

ed
at the beginning of PH4.
'Since the addressed device can
respond to BDIN L (during the input portion), which has
not
been asserted, the Input Word microinstruction test of REPLY
PH3 fails and the Wait state is initiated.
Microcycle

Because

WDIN

Input
the

Read

(not

Word

1is

completed

asserted

the

assertion of BDIN L follows immediately.
the
addressed
device
places
data
on
BRPLY

until
state.

PH1

the

and

processor.

only
yet
H at

(Wait)

microinstruction

shown)

the beginning
to be assert-

However,

remains

the

passive

during

Microcycle

beginning

In
BDAL

response
<15:00>

which

F/F

PH2.

to
and
not

maintains

The

BDIN
L,
returns
clocked

the

Wait

MICROPROGRAMMING

LSI-11

Minimum

SYSTEM BUS

DATIO

Figure

TRANSACTIONS

Cycle

5=7

ONE
ONE
ONE
ONE
ONE
ONL
ONL
j@-— MICRO — t— MICRO -~ 14— MICRO —¥n re— MICRO —r— MICR()
—r— MICRO —re-— MICRO
CYCLE

CYCLE
PHASE

—~

ONE

PHASE
TWO
PHASE
THREE

_/\

/) N~

FOUR

()

ONI

CycClt

—

/) N

MICRO

ONE

cyctLt

—fl P— MICRO —r - MICRO —m—

CYCLt

/N\ L /\

_/\

CYCLE

CYCLt

PHASE

CYCLE

WSYNC

BSYNC L

(

BDIN L

WDOUT H

BDOUT L

RESP TMTM
.

DLy _J

DEV

BWTBT L

RESP

—

DEv

P RESP

BRPLY L

REPLY H

X | Aooress

BDAL L

READ

\
INPUT LOW
BYTL

INPUT HIGH 6
BYTL

MOD

{
N

X pAta

INPUT (WAITI3 INPUT (WAITI 4

OuTRUI
(WALT)

OUTPUT
(WAIT)

OUIPUT

NEXTINS

WORD
MU

MICROPROGRAMMING

Microcycle
The

LSI-11

Input Word

asserted

state

SYSTEM

(Input

BRPLY

BUS

TRANSACTIONS

Low Byte)

sets

the

F/F

the

beginning

of
PH1.
Since REPLY H becomes active, the Wait state is terminated during the PH3 REPLY H check and the Data chip
stores
the
low byte in a designated register.

Microcycle

Input Word

(Input High Byte)

Since the PH3 check of REPLY H is again
passed,
the
Data
chip
stores the high byte in a designated register (determined by complementing the low-order bit of the A register field).
No
control
signals
are
changed
by either processor or the addressed
device.
To

assure the minimum delay in the input portion of the DATIO operation, BRPLY L must be received at the processor in time to set
the REPLY F/F at the beginning of Microcycle
4.
Otherwise
the
Wait state will continue throughout Microcycle 4 and the next op-—
portunity to set the REPLY F/F will not occur until the beginning
of Microcycle

Microcycle

Because

cle

Modify Data
the

Input Word microinstruction completed during MicrocyWDIN
H (not shown) and BDIN L are negated at the end of

PHI1.
The
negation
of
WDIN
H
cancels
REPLY
H.
The
Read-Modify-Write
operation
maintains
WSYNC
H in the asserted
state.
The addressed device responds to the negation of
BDIN
L
by removing data from BDAL<15:00> and negating BRPLY L,
This example of the DATIO operation
allows
one
microcycle
for
modification
of
the
data
retrieved by the Input Word microinstruction.
Normal usage would probably require
manipulation
of
the
entire data word which would necessitate at least 2 microcycles.
Since none
of
the
data
manipulation
microinstructions
check
the REPLY H or BUSY H signals, execution can proceed without

delay.

Microcycle
Since

7
BRPLY

Output Word

(Wait)

was

negated

the

addressed

device

during

Microcy-

cle
6,
the REPLY F/F is clocked into the reset state at the beginning of PH1l, which cancels BUSY H (not shown).
Execution
of
the
Output Word microinstruction proceeds up to the PH3 check of
REPLY

has

been

cancelled

and

the

Wait

state

initi-

ated.
Microcycle

Output

Word

(Wait)

Because the Output Word microinstruction executed up to the failing
check of REPLY H during Microcycle 7, WDOUT H is asserted at

the

beginning

PHl1l.

BDOUT

asserted

the

beginning

PH3.

Since
WWBH

this
and

example

BWTBT

contains

are

not

the

asserted.

Output
In

the

Word
case

microinstruction,
of

Output

Byte

microinstruction, the assertion of BWTBT L would begin at PH1
of
Microcycle
8
and end at PHl1 of Microcycle 9.
Also, as a result

MICROPROGRAMMING

LSI-11

SYSTEM

BUS

TRANSACTIONS

of the partial execution of the Output Word microinstruction, the
Data
chip
simultaneously places two bytes (a full word) of data
on BDALK15:00>,.

response

the

assertion of BDOUT L,

cepts
the
-data
output
However, the REPLY F/F is

by
not

ins passive which maintains

Microcyclé 9
The

the

addressed device

ac-

the processor, and asserts BRPLY L.
clocked until PHl1 and REPLY H rema-

the Wait

state.

Output Word

asserted

state

BRPLY

sets

the

F/F

the

beginning

of
PHI.
Since REPLY H becomes active, the Wait state is terminated at the PH3 REPLY H check and the Output Word
microinstruction executes to completion.
The set state
of the REPLY F/F also
negates the DOUT F/F input and it is clocked to the
reset
state
at
the
beginning of PH3, which negates BDOUT L and also cancels
REPLY

REPLY
device

Note

that

the

Control

chip

determines

the

H
at the beginning of PH3, thus recognizing
response before REPLY H is cancelled via the

the DOUT F/F.
Microcycle
The

negation

cycle
WDOUT

the

removes
BSYNC L

Any
10,

type

BRPLY

PH1

made

causes

the

BUSY

F/F

negates

made passive

beginning

F/F

was

reset

completed

the
of

the

reset

shown).

(not

during

beginning of
PH4.

executed
at

BUSY

word
from
BDALK15:00>
the passive state at the

microinstruction may
the

turn

microinstruction

passive

the
output
is clocked to

which

Output Word

WSYNC

since

negating

9,
H

Next Microinstruction

beginning
Because

state

the addressed
resetting
of

The

at the
end of

Micro-

PH2

and

Data

chip

end of
PH3.

PH4.

during

beginning

the

Microcycle
of

PH1l,

thus

MICROPROGRAMMING

5.5.2
The

DATIO Microprogramming

DATIO

operation,

microinstruction

LSI-11

SYSTEM

BUS

TRANSACTIONS

Summary

implemented

the

Read-Input-Modify~-Output

sequence, allows variable delays in addressed device
response to assertion and negation of both BDIN L and
BDOUT
L.
The
optimizing
considerations
relevant
here
are a combination of those
discussed in the DATI and DATOQO contexts.
To summarize, the
a DATIO operation

delay in the execution
may be minimized if:

microprogram

The microinstruction immediately preceding
struction does not cause BUSY H or REPLY H

2.,

The addressed
minimum time.

device

responds

the

assertion

The addressed
minimum time.

device

responds

the

negation

The

device

responds

the

assertion

device

responds

the

negation

addressed

minimum
5.

The

addressed

minimum
6.

The

time.

the Read
microinto be asserted.

time.

microinstruction

instruction

does

not

immediately

check

following

BUSY

containing

the

BDIN

BDINL

BDOUT

OQOutput

As an alternative to condition 2
above,
unavoidable
delays
utilized by inserting data manipulation microinstructions.

1in

micro-

may

MICROPROGRAMMING LSI-11 SYSTEM BUS TRANSACTIONS

5.6

THE

INTERRUPT OPERATION

Rb,Ra

IwW

Rb,Ra

The

SIGNAL

DIN,

INPUT

VECTOR

individual events which occur

discussed

with

the

numbers.

reference

Microcycle

IACK
LOW AND

HIGH

BYTE

Next Microinstruction

wme

Figure 5-8 illustrates the control signal action relevant to an interrupt
operation.
The microinstruction sequence presented is Read Acknowledge, Input Word, Next Microinstruction.

the

interrupt

transaction

are

aid of Figure 5-8, which contains the Microcycle

Read Acknowledge

The execution of the Read
Acknowledge
microinstruction
in
the
first
microcycle
causes
no change in the control signals.
The
BUSY
microinstruction executes to completion because REPLY H and
H

are

Microcycle

unasserted

during

Input Word

PH3.

(Wait)

Because the Read Acknowledge
microinstruction
completed
during
Microcycle 1, the contents of the designated registers are placed
on BDAL<K15:00> at the beginning of PHl,
Since no address
information
1is
required
in the LSI-11 system bus interrupt transaction, any register
(s) may be designated.
WSYNC H and WIAK H
are

asserted
at the beginning of PH2.
The assertion of WIAK H holds
the SYNC F/F in the reset state thus blocking
the
assertion
of
BSYNC L, as would otherwise occur at the beginning of PH4.
BSYNC
L is inhibited because it is not required in
the
LSI-1l1
system
bus

interrupt

transaction.

The interrupting device only returns BRPLY L in response to BIACK
H, which has not yet been asserted.
Therefore, the Wait state is
initiated at the beginning of PH3.
Microcycle

Input Word

(Wait)

Because the Read Acknowledge microinstruction executed to compleduring Microcycle 1, WDIN H is asserted at the beginning of
tion
PH2.
The assertion of BDIN L follows immediately and is used
to
Since REPLY
the priorities in the interrupting device.
stablize
H remains unasserted, the Wait state is maintained.

Microcycle 4

Input Word

(Wait)

With the assertion of WDIN H during Microcycle 3, the INT ACK
no longer locked in the reset state therefore the INT ACK
is
is clocked to the set state on the trailing edge of PHl (and
serts BIACK H).
1In response to the assertion of BIACK H, the
terrupting device places its device vector on BDAL<K15:00> and
However, the REPLY F/F is not clocked until
L.
BRPLY
serts
of Microcycle

Wait

state.

REPLY H remains

passive
-

which

maintains

F/F
F/F
asinasPHI
the

MICROPROGRAMMING LSI-11 SYSTEM BUS TRANSACTIONS

MICROPROGRAMMING

5.6.1

Interrupt

LSI-11

Operation

The
interrupt
Acknowledge-Input

SYSTEM

BUS

TRANSACTIONS

Microprogramming

operation,
as
microinstruction

Summary

implemented
by
sequence, allows

the
Read
for variable

delays
gation
ation.

in addressed device response to both the assertion and neof BIACK H.
BDIN L also takes part in the interrupt operThe timing relationships between BIACK H and
BDIN
L
is
established by the LSI-11 system bus interface logic. The return
of BRPLY L and the device vector is under control of BIACK H, not

BDIN

normally

before the INT ACK
struction does not
To

summarize,

taining

the

the case.
Because WDIN H must be
F/F can be set, the Write Acknowledge
assert BIACK H on the LSI-11 Bus.

delay

interrupt

the

execution

microprogram

minimized

The microinstruction immediately preceding the
nowledge microinstruction does not cause REPLY
H to be asserted.

The interrupting device responds
BIACK H in minimum time.

The interrupting device
BIACK H in minimum time.

The

microprogram

alternative

does
2

responds

immediately

not

above,

check

the

following

BUSY

unavoidable

con-

if:

instruction
As

operation may

asserted
microin-

the

delays

may

Read
H or

AckBUSY

assertion

negation

Input

micro-

utilized

by
1inserting
data manipulation microinstructions.
However, due
to the largely unpredictable nature of the
interrupt
operation,
it
1is not expected that the freedom to perform data manipulation
between execution of the Read Acknowledge and Input microinstructions would be of any general use.

CHAPTER

THE

6.1

LSI-11

WRITABLE

CONTROL

STORE

GENERAL

The LSI-11 Writable Control Store option consists of a single quad height
(8.5x10
1inch)
printed circuit module (M8018), a WCS cable/plug

assembly

and

an LSI-11

CPU.

The Writable Control Store module is a 1024 x 24 bit microcode RAM for
the LSI-11 CPU which enables user specified machine instructions to be
added to the standard LSI-1l1l (PDP-1ll)
instruction
set.
The
module
also
contains
Trace RAM logic to facilitate microprogram development
and 2 additional TTL Control bits in each microcode word (not found in
an
LSI-11
MICROM) that are available at the backplane for high speed
control applications.
The microaddress range that the WCS responds to
is determined by setting an 8 wide DIP switch on the module.
The WCS

cable/plug

struction bus
The WCS

6.2

option

THE

assembly

the

can be

WRITABLE

LSI-11

connects

the

CPU

Figure

utilized

CONTROL

STORE

(see

WCS

module

the

microin-

6-1).

only with M7264-YC

LSI-11

CPU.

MEMORY

The memory of the Writable Control Store module
(1024
24-bit
memory
words) is implemented by 24 1024 x 1 bit high speed static semiconductor memory devices.
Since the memory is static, no refreshing is
required.
However, the semiconductor memory is volatile, so the control
store must be reloaded after each power up.

6.2.1

Control

Store Microword Organization

The microword organization is determined by the function of individual
bit
fields
and by the access timing.
As shown in Figure 6-2, the 24
bit WCS microword is composed of the standard 22-bit microinstruction,
(MI<21:0>) and 2 additional bits (MI<23:22>) which function as extended TTL control bits.

THE

LSI-11

LSI-1l

WRITABLE

Processor-Writable

Control

Figure

LSI-11 PROCESSOR

-1'

|
|

prOCESSOR

CONTROL

Toe) TER

[R5

SOURCE

DESTINATION

OPERAND OPERAND

:ARITHMETIC
Y4 Z
LoGgic

/" [ce)

WRITABLE

(r7) pswi|

STORE

INPUT/

MEMORY

OUTPUT
DEVICES

|
|

TEL

UNIT

IG- CONTROL

Interconnection

6-1

PROGRAM

COUNTER

—

Store

STORE

STACK

CONTROL

LSI-11 SYSTEM BUS

MR-1021

THE

Standard

LSI-11

WRITABLE

22-Bit Microword

Plus

Figure

23 22 21
T

18
T

k___r___J

CONTROL

STORE

Extended

Control

Bits

6-2

00
T

]

—

]

STANDARD

VERTICAL

TTL CONTROL

MICROINSTRUCTION

BITS

)

EXTENDED

TTL CONTROL

RSVC

L RR

BITS

BIT

BIT
MR-1064

THE

6.2.1.1

Standard

LSI-11

22-Bit

WRITABLE

Microword

CONTROL STORE

MI<21:0>

This

microword

1is

com-

posed of 4 functionally distinct and independent fields, as illustrated in Figure 6-2.
The three lower fields,
MIK17>,
MIK16>,
MI<15:0>
are
read
by the microprocessor Control and Data chips during the microfetch operation at microcycle PHl1l.,
The upper field,
MI<K21:18>
is
accessed
by
the
Special Control Function Logic on the CPU module at
microcycle PH3.
These 4 bits are then decoded to provide TTL compati-

ble

control

For

the

signals

standard

functionally
l.

2.,

22-bit microword,

identical

does

the

not

CPU

MI<K21:18>

pared

the

vertical

the Writable

a MICROM with

precharge

the

MIB

the

lines.

microinstruction.

Control

Store

following
Note

memory

exceptions:

that

all

MICROMs

unconditionally perform precharge.
are

asserted

a MICROM which

PH3.

6.2.1.2

synchronized with

the

WCS

asserts

during

PH2

MI<21:18>

and

PH3

during

PHl1l,

com-

PH2

and

Extended

TTL Control

Bits

MI<K23:22>

The

WCS

memory

provides

storage for two additional control bits not found in an LSI-11 MICROM,
called the Extended TTL Control bits.
Both bits (MI<23:22>) appear at
the
WCS
module
fingers
(AEl and AFl) for user access via backplane
connection.
The highest bit, MI<23>, is also used by the microaddress
trace RAM on the WCS module.
These Extended TTL Control
chronized with micromachine operations.

6.2.2

Control

The WCS

Store Microaddressing

module

lationship

contains

the WCS

wide

memory

are

four address modes which are of
tions for each mode are illustrated
Swl

SW2

SW3

Sw4

are

determines

the

switch

which

LSI-11l microaddress
general

use

and

the

OFF
OFF

ON
OFF

OFF
ON

ON
ON

OFF

"MODE

OFF

explained

The
Note

WCS

memory

that

microcode
MODE

This

responds

MICROMs

and

the

and

respond

paging

mode

SW8

OFF
OFF

MODE

posi-

SW7

OFF
ON

are

switch

SW6

ON
OFF

modes

There

SW5

1
2

address

re-

space.

below:

MODE
MODE
MODE

The

syn-

Modes

DIP

the

bits

follows:
to
1

microaddresses
contain

the

microaddresses
where

the

1024

2000-3777

PDP-11

and

0000-1777
WCS

memory

(octal).

console

ODT

(octal).
1locations

are
treated
as
two
512 microword pages.
Either page can
respond to control store addresses in the 3000-3777
(octal)
range.
The
WCS page from which a microword is accessed is
determined by the WCS page logic.
After this logic is
1initialized
(by
asserting the reset bit in the control/status
register, CSR<15>), all microaddresses point to WCS
page
O

THE

(the
after

LSI-1l

WRITABLE

CONTROL

1initial
page).
The WCS pages are swapped
a microinstruction containing MI<21:18> =

is
accessed
in
control store and
microwords are accessed from page 1
second

read
MODE

occurance

from page

of 07
again.

MI<21:18>

swapped

the

module.

tic
capability
to
execute
physical memory pages.
Note
memory
4

the

respond

modes

system

bus

trates

the

0000-0777
RAM

6.3
The

subsequent control store
(the toggled
page).
A
causes

microwords

MODE

responds to
mode is not

the

same

provides

diagnos-

microaddresses 0000-1777 (octal).
used because LSI-11 MICROMs 0 and

microaddresses.

described

above, the WCS memory is loaded from the LSI-11
RAM addresses 0000-1777 (octal).
Figure 6-3 illusrelationship between the WCS RAM addresses and the respond-

(octal)

address

WRITABLE
memory

MODE

a microprogram out of different
that loading and accessing
WCS

via WCS

ing
microaddresses
always accessed via
WCS

identical

The WCS memory
Normally, this

l
In

immediately
07
(octal)

The WCS memory responds to microaddresses 2000-3777
(octal).
This
1is
similar to MODE 1 except that WCS memory pages are

physically

MODE

STORE

for
each of the four modes.
Note that page 0 is
the system
bus
in
the
WCS
RAM
address
range
and similarly that page 1 is always accessed in the

range

1000-1777

(octal).

CONTROL

STORE

MEMORY

the

module

may

WCS

ACCESS
accessed

two

ways:

(1)

the

microprocessor
chip
set via the microinstruction bus (Read only) and
(2) by the LSI-11 processor via the
LSI-11
system
bus
(Read/Write)
using normal PDP-11 instructions.
'
:

6.3.1

Microinstruction

Bus

Access

Figure 6-4 illustrates the
LSI-11
micromachine
configuration
which
contains both Writable Control Store and MICROMs for microprogram storage.
The first half of the illustration, Figure 6-4-1, appeared earilier
1in
Chapter
3.
The
second
half of the illustration, Figure
6-4-2, shows the interconnections to the WCS module.
1In
addition
to
bus
interconnections
at both the machine and micromachine level, the

WCS

PHZ

module
H

and

also
PH4

croinstruction
Note
tion

connects

Bus

These

two

the processor
module
connections are contained

interconnect

that a Writable
bus
is
Read
control store memory

cable.

clock

phases,

within

the

Mi-

Control Store memory access by the
microinstrucOnly.
There are no microinstructions which alter
via the microinstruction bus.

THE LSI-11 WRITABLE CONTROL STORE

WCS

RAM Address-Microaddress
Figure

WCS RAM

Relationship

6-3

WCS RAM

<0000-0777>

<1000—-1777>

MODE1

MIB<2000—-2777>

MIB<3000—-3777>

MODE2

MIB<3000—-3777>

(INITIAL PAGE)

(TOGGLED PAGE)

MODE3

MIB<2000—-2777>

MIB<3000—-3777>

MODE4

MIB<0000—-0777>

MIB<1000-1777>
MR-1071

THE

WCS

LSI-11

Microinstruction

WRITABLE

Bus

and

CONTROL

System Bus

Figure

STORE

Interconnection

6-4

MIB <15:00>

MIB <16>

‘

MICRO-

[
7

MIB <17>

MIB <21:18>

MICRO-

MICROM

PROCESSOR | WAIT | PROCESSOR

wes

DATA

CONTROL

(CONTROL

CHIP

STORE)

[

4
WDAL

RPH

<07:00>

1-4

WDAL

<15:08>

TTL

10—

CONTROL

Y
\?VD'\IJ,S

WDOUT
WB
WIACK

BITS

COMPUTE
RESET
.

BUSY

EXTENDED

2 ¥ TTL CONTROL
BITS

BUS TRANSCE
AND INTERFACE
IVERS
LOGIC

LSi-11 SYSTEM BUS

MR-1072

THE

The

signal

paths

LSI-11

the

WRITABLE

CONTROL STORE

microinstruction

bus

interconnect

cable

are

listed
in
Figure
6-5.
MIB<10:00>
carries
the
microaddress, MADR<10:00>, to the WCS during
the
control
store
addressing phase of the microcycle (PH2).
The WCS then responds, during
the control store access phase, by asserting the microinstruction word
on
MIB<21:0>.
Note that the MIB<10:0> lines are time-multiplexed for
address and data information.
During the first microcycle of a multiple
cycle microinstruction, a control store disable function (CSD) is
performed with MIB<16>.
If MIB<16> is asserted by
the
Control
chip
during
PH3,
WCS
(or
MICROM) response during the next microcycle is
disabled.
The highest 2 bits of the WCS microword, the
Extended
TTL
Control
Bits, do not appear in Figure 6-5 since they are not utilized
by the LSI-11 CPU module and consequently are not carried by
the
MIB
interconnection cable.

6.3.1.1
Control Store Access Timing - The control store access timing
for
the
WCS
module is shown in Figure 6-6.
As noted in the figure,
the WCS module does not perform precharge of any Microinstruction
Bus

lines.

This

function

Microinstruction

Bus.

is performed
is

important

by every MICROM connected
also

note

bits,
MI<21:18>,
through the end of
MI<17:00>

remain

During the
MIB<16>
1is

response

are asserted (active low) from
PH3 whereas the lower bits of
asserted during PH1 only.

first
microcycle
of
a
asserted by the Control

during

the

following

that

the
the

TTL

beginning
control

the

control

of PH2
store,

multiple
microcycle
operation,
chip to disable the control store

microcycle.

This

The

timing

shown

1in

Figure

diagrams

illus-

6-7.

6.3.1.2

Extended

TTL

Control

Bit

Timing

trated in Figure 6-6 and 6.7 also show the timing for the Extended TTL
Control bits MI<K23:22>.
These bits are latched on the WCS module
and
are available at the backplane (pins AEl and AFl) as described below:
l.

If a
TTL

single cycle microinstruction
Control
bits
are valid from

is executed, the
rising PHl of the

Extended
microin-

struction to the next rising PHl.
Note that multiple
single
cycle
microinstructions
with
the same Extended TTL Control
bit (s) asserted will produce a continuously asserted
control
signal.
2,

multiple

cycle

cycles)

microinstruction

executed, the Extended TTL Control Bits are valid
PH1 of the first microcycle to rising PH3 of that
are cleared to "0" for any subsequent microcycles
croinstruction.

from rising
cycle
and
of that mi-

THE

LSI-11

WRITABLE

Microinstruction

Bus

Figure

CONTROL

Access

STORE

Functions

6-5

SIGNAL

ADDRESS CYCLE

ACCESS CYCLE

MIB<01>

MADR <01>

MI<01>

MIB<02>

MADR<02>

MI<02>

MIB<03>

MADR<03>

Mi<03>

MIB<<04>

MADR<04>

Mi1<04>

MIB<05>

MADR<05>

MI<05>

MIB<06>

MADR<06>

MI<06>

MIB<Q7>

MADR<Q7>

MI<07>

MiB<<08>

MADR<08>

MI<08>

MIB<09>

MADR<09>

MI<09>

MIB<10>

MADR<10>

MI<10>

MIB<11>

MI<11>

MiB<12>

MI<12>

MIB<13>

MI<13>

MIB<14>

MI<14>

MIB<15>

MIB<16>

MI<15>

CSD <16>

MI<16>

MIB<17>

MI<17>

MIB<18>

MI1<18>

MIB<19>

MI<19>

MIB<20>

MI<20>

MIB<21>

MI<21>

PH2 H

WCS TIMING

PH4 H

WCS TIMING
MR-1073

6.3.2

LSI-11

THE

LSI-11

WRITABLE

CONTROL

STORE

THE

LSI-11

WRITABLE

CONTROL

STORE

System Bus Access

The Writable Control Store
by
the LSI-11 system bus.
grammed I/0 data transfers

6.4

THE

MICROADDRESS

RAM memory is Read/Write only when accessed
The WCS interface logic supports only Provia the system bus interface registers.

TRACE

RAM

The Writable Control Store option has a l6-word microaddress trace RAM
to
aid
with
microprogram debugging.
The trace hardware is normally
controlled by the operator under MODT (see Chapter 7).

6.4.1

Microaddress Trace RAM Operation

The hardware
l6-word
RAM

portion
which

of
1is

the
microaddress
trace
continuously loaded with

RAM
consists
of
a
the last microaddress

asserted on the Microinstruction Bus
by
the
microprocessor
Control
chip.
The
RAM,
therefore, contains the last 16 microaddresses presented to the WCS (or MICROM) including the
disabled
<cycle(s)
of
a
multiple cycle microinstruction.
To stop a microaddress trace for examination, the operator (via MODT) sets MI<K23> (one
of
the
extended
TTL

bits)

the

microword

that

the

last

microinstruction

the Trace RAM.
After this microinstruction is fetched by
the
microprocessor
Control
<chip,
the
WCS hardware inhibits the microaddress
trace RAM clock from any further operation.
Once the clock
1is
inhibited, the trace RAM contents remain unchanged.
The operator may then
access the buffer to read the traced microaddresses in
the
order
of
the actual execution.
The Trace RAM is implemented with three 16x4-bit random
access
memories
addressed
by
a 4-bit counter.
The counter is normally clocked
continuously, thus providing a recirculating, increasing
address
sequence
(modulo
16) to the RAM memories.
When the microprogram trace
has been halted, each of the stored microaddresses can be accessed.
The

format

6.4.2

WCS

Trace

Enable

RAM

word

shown

Figure

6-8.

Bit

In addition to providing a record of the last 16 microaddresses on the
MIB, the Trace RAM also indicates whether the WCS responded to the microaddress.
The RAM stores an extra bit,
the
WCS
Enable
Bit
(bit
<11>),
along
with each microaddress.
This bit is a "0" when the WCS
was disabled during the microfetch and set to "1" when the WCS was enabled.
This
1is
useful in determining microprogram execution delays
incurred during data access (system bus I/0) operations.

THE

LSI-11

WRITABLE

CONTROL

Trace

RAM

Word

Figure

6-8

Microaddress

TRACE BUFFER SEQUENTIAL

STORE

Format

MICRO?DDRESS

ADDRESS (MODULO 16)

CONTROL STORE ENABLE BIT
MR 1076

6-13

6.5
The

LSI-11
WCS

SYSTEM

interface

THE

LSI-11

BUS

INTERFACE

the

WRITABLE

LSI-11

bus

CONTROL

STORE

similar

that

other

1I/0

devices
which
support
only Programmed I/0O transactions.
The device
address format is a modification of the general format presented
earlier
1in
Chapter 2.
The primary features of the WCS interface registers are that there is a single control/status register and
that
the
two
other registers provide the 24-bit access path for the WCS microcode RAM.
In addition, one register is multiplexed to provide
access
to the microaddress Trace RAM.
WCS interface register formats are illustrated in Figure 6-9.
The register addresses on the LSI-11
system
bus are 177540 through 177545.

6.5.1

WCS

Control/Status

The

specific

ined

below

CSR<K15>

functions of the WCS control/status
according to the related bit-fields:

as the WCS Reset.
When set to a
paging logic is reset to page 0,
to a "0".
Subsequently clearing

"O0"

paging

logic

and

the

Trace

RAM

Examine

enables

Trace

RAM

the

counter

"1", the conand the Trace
CSR<15> to
a

that

set

bit

a "1",
access

the

functions

"0"

for

normal

the

control

the interface register
a Trace RAM word.
The

store

bit.

operation.

should

located at 177542
Trace RAM word is

When

set

may
Read

be
read
only .

to
to

Read/Write

This

bit

functions

the

Examine

Toggle

for

the

Trace

dress
counter
and is toggled to examine sequential
Its use is further explained later in this chapter.
CSR<K12>

supplies

address.

Read/Write

This

CSR<13>

expla-

Read/Write

This bit functions
trol
store memory
RAM address is set

CSR<14>

are

RAM

trace

ad-

words.

Read/Write

This bit functions as the
Writable
Control
Store
Enable
bit.
When
it is set to a "O" the WCS module cannot respond to the microinstruction bus.
However, the WCS RAM can then be accessed by
the
LSI-11
bus.
When CSR bit <12> is set to a "1", the WCS module responds to microaddresses
1in
1its
switch-selected
range;
and the WCS RAM cannot be altered by the LSI-11 bus.
CSR<11:10>

Read

Only

These

bits

are

unused

and

always

read

"O".

THE

LSI-11

WCS

WRITABLE

Interface

CONTROL

Bit

STORE

Assignments

6-9

177540

READ/WRITE
\

RAM ADDRESS REGISTER
RESET

EXAMINE

UNUSED

(ALWAYS

READ
AS
A "0")

TRACE

ENABLE

UNUSED

{ALWAYS

BIT

MODE

READ

177542

uou)

READ/WRITE IF
177540 BIT <14>=0

MICROCODE LOW WORD
15

177542

READ ONLY IF
177540 BIT <14> =1

TRACE BUFFER ADDRESS

MICRO ADDRESS IN BUFFER

WCS QUTPUT CYCLE

0=O0UTPUT DISABLED (MIB)
1=0UTPUT ENABLED (MIB)

177544

READ/WRITE
N

—

UNUSED

(ALWAYS READ
AS “0")

—

MICROCODE HIGH WORD
USER BIT

USER BIT AND
TRACE STOP
MR.1077

THE

CSR<9:0>

LSI-11

WRITABLE

CONTROL STORE

Read/Write

When CSR<12> is a "0", the WCS module is not enabled.
is then the 10-bit WCS RAM address and is Read/Write.
the low-order bit and CSR <9> is the high order bit.

This field
CSR <0> is

When CSR<12> is a "1", the WCS module is enabled.
This field
|is
then
Read
Only
and contains the microaddress of the actual bus
cycle of the PDP-1l1l instruction (or Console ODT routine) that
|is
used to access the control/status register.

6.5.2

WCS Memory Access Registers

When CSR<K12> is a "0", the WCS module is not enabled to respond to the
MIB.
WCS
RAM
access
by the LSI-11 bus is enabled.
The WCS module
device registers, which also function as WCS RAM
data
access
registers,
are
177542
and
177544, as shown in Figure 6-9.
The lower 16
bits of the microword, MI<K15:0>, are
accessed
via
location
177542,
The
higher
8 bits, MI<23:16> are accessed via location 177544.
Note
that bits <15:8> of location 177544 are unused and are
read
as
"0".
The
address
of the WCS RAM microword accessed via these registers
'is
determined by CSR<9:0> (only when CSR<12> is a "0").
Both WCS memory access registers support Read/Write access
only
when
the
WCS
1s
disabled (CSR<12>=0).
The Write mode, implemented by an
LSI-11 DATO operation, allows WCS memory to be loaded.
The Read mode,
implemented
by
an
LSI-11 DATI operation, allows the WCS memory contents to be examined.

When the WCS module is enabled (CSR<12>=1), both WCS registers (177542
and
177544)
are Read Only, and the data which is read will depend on
the type of PDP-11 instruction (or console ODT) used to access the register.
This is due to the fact that, when enabled, the WCS module is
being addressed only by the MIB, and the microaddress present
on
the
MIB determines

6.5.3

the WCS

Microaddress

When bit <14> of

RAM

Trace

location

that

accessed.

the control/status

set

location

177542 no longer functions as a memory access register, but as a Trace
RAM access register, as shown in Figure 6-9.
The
specifications
of
this register are explained according to the related bit fields:
Bits

<10:0>

This field contains an ll-bit microaddress
(Bit
0
1is
the
1low-order
microaddress bit).
The value read from
Bits <10:0> is the value that appeared on the
microinstruction bus (at microaccess time) while the microprogram was

Bit

Bits

<11>

<12:15>

being

traced.

This bit is the value of the WCS Enable
Bit
which
1is
stored
1in
the
trace
buffer along with each microaddress.
A value of 0 indicates that
WCS
response
was
disabled for the microcycle.

This bit field contains the 4-bit (modulo
16)
of
the trace buffer memory.
The counter value

6-16

address
is made

THE

LSI-11

WRITABLE

CONTROL

available in the trace
word
buffer contents in the proper

STORE

to
aid
order of

1in
dumping
occurrence.

the

6.5.3.1
Microaddress Trace RAM Dump Algorithm - Proper
operation
the microaddress trace RAM hardware requires the following steps:
1.

The trace RAM is initialized
execution of microcode.

(by

The last microinstruction
in MI<K23>.

After

the

trace RAM

initialized,

the

asserting CSR<15>)

traced

contains

trace RAM

prior

value

continually

up-

dated
to
contain the 16 most recent microaddresses placed on the microinstruction bus by the microprocessor Control chip (at
PH2).
The
RAM
contents are frozen when the microinstruction containing MI<K23>=1
is accessed including the address of that microinstruction.
The
RAM
contents
may
be
dumped
by setting CSR<14> to a "1" and then subsequently accessing the trace RAM contents by toggling CSR<13>.
The algorithm
used is illustrated in Figure 6-10.
Note that the RAM memory
address (Trace bits <15:12>) must be saved
before
the
Toggle
store
loop is entered to provide a reference for any subsequent tests.
Also
note that every CSR Write operation must contain a "1" in bit <14>
to
maintain the Trace Examine Enable and count down the Trace RAM address
counter.
The final 2 events in the flow
chart
initialize
the
Page
Logic and the Trace RAM and re-enable the WCS.

6.6

WRITABLE CONTROL STORE MODULE DESCRIPTION

A Block

Diagram of

should be

6.6.1

the WCS module

referred to

Clock

for

the

illustrated

Figure

6-11

and

following Circuit Description.

Generation

The clock generation circuit receives and buffers 2 of the 4
TTL
microcycle
clock phases (PH2 H and PH4 H) from the LSI-1l1 processor module.
These clock signals are connected to the WCS module via the mi-

croinstruction
bus interconnect cable.
Note that only LSI-11 CPU modules of etch revision F (CS Rev Y) or later have the necessary
clock
signals
available
at
the empty MICROM socket, E75 (alternately used
for the KEV-1ll option).
The M7264-YC module satisfies these
require-

ments.

The clock generation circuit then derives 2 clock signals from its inputs,
namely, PHl1 H and PH23 H.
PH23 H is asserted high continuously
during microcycle phases 2 and 3 and is used to
enable
the
standard
TTL
control
bits
to
the
LSI-11
CPU.
PH1 H enables the output of
MI<17:0>

the

CPU.

THE

6.6.2

Control

LSI-11

Store Memory

WRITABLE

and

CONTROL

STORE

Microaddress Multiplexer

The control store memory is implemented with 24 RAM integrated
circuits
each having a l-bit by 1024 organization.
The control store page
organization is established by the microaddress
multiplexer
in
conjunction with the paging logic.

6.6.3

LSI-1l1l

System Bus

Interface

The system bus interface is
1implemented
with
integrated
bus
transceivers
(DC005)
and a protocol logic circuit (DC004).
The register
selected to be read (of the 4 possible registers) is determined by the
read back multiplexer.
The Extended TTL Control Bits are available on
the backplane at pin locations which are normally spare (AEl and AFl).
Note that the WCS module does not respond to bus address 177546 (since

this

is the address assigned to the BDV1l and KPV1l options).

6.6.4

Microinstruction

Bus

Interface

The microinstruction bus interface is
rated
circuits
which
interface the

implemented with special
integMOS logic levels of the Microinstruction Bus to the TTL levels on the WCS module.
Only 12
receivers
are
1implemented
(MIB<K1U:0>
and
MIB<K16>),
and since 22 bits of the
stored microword are returned via the
microinstruction
bus,
22
MIB
drivers
are implemented.
The timing for the MIB driver is determined
by the output enable circuitry.
Control store output is enabled
only

when:

6.6.5

The

appropriate

The WCS

When the control store
by the Control chip on

module

Microaddress

microaddress

microaddress
is

Trace

trace

enabled

has

been

received,

(CSR<12>=1l),

and

disable bit (MIB<16>) was
the previous cycle (PH3).

not

asserted

RAM

facility

implemented

three

16x4

bit

RAM

memories,
one 4-bit counter (which addresses the memories), and associated clocking logic.
Toggling CSR <15> to a "1" and then back to
a
"0"
1initializes the counter and restores the clock input (PH2) to the
counter.
The 16 microaddress RAM locations produced by this
configuration
are
loaded
from
the output of the microaddress multiplexer,
MADR<10:0>.,
Bit <11> is loaded with a "1" when the WCS is enabled
to
respond
to
the MIB or a "0" otherwise.
1In this way the stored Trace
RAM

data

reflects

the

control

store

address

placed

microprocessor
Control
chip
and whether the WCS
buffer contents are examined from the system
bus
read back multiplexer.

the

MIB

responded.
interface

the

The
via

RAM
the

THE

6.7

WRITABLE

CONTROL

LSI-1l

STORE

HARDWARE

this

section

The items contained in
dule hardware details.

6.7.1

WRITABLE

CONTROL

STORE

SPECIFICATIONS
provide

quick

reference

for

mo-

Dimensions

The

KUV11l-AA LSI-11 Writable Control Store option
consists
of
(1) a
standard quad height, 8.5 by 10 inch, multilayer printed circuit board
(M8018) with signal etch on both sides and 2
1inner
layers
(VCC
and
GND) and
(2) a Microinstruction Bus Interconnect Cable/Plug assembly.

6.7.2

Power

Requirements

The only power
Connection
to

blished

supply voltage
the
+5
volt

through

ply

voltage

volt

supply

the module

required by the WCS module is +5
volts.
supply as well as ground return is esta-

finger/backplane

interconnection.

tolerance
is + or - 5% and the current
is 3.A typical (7.34A worst case).

6.7.3

LSI-1ll

Figure

6-12 lists

6.7.4

Microinstruction

System

Bus

Backplane

the WCS module

Bus

The

from

sup-

the

Assignment

(M8018)

Connector

drawn

backplane pin assignments.

Pin Assignment

Figure 6-13 contains a table listing the pin assignments for
the
microinstruction
bus
interconnect
cable/plug
assembly.
All unlisted
numbers have no connection at either end of the cable
assembly.
The

pin
WCS

assignments

module

end

are

the

same

cable.

both

However,

the processor
because

module

two

end

series

and

the

matching

registers
(pins
24,25) on the end of the cable marked "CPU",
(inside
the plug assembly), the cable plugs are NOT
interchangeable
and
the
end
marked
"CPU" must be plugged into E75 of the LSI-11 CPU.
A continuity check of each signal path will produce a low resistence
reading
(less
than
1 ohm) except for pins 24 and 25.
These paths carry
the microcycle clock phases and contain a 100 Ohm series resistence on
each path.

THE

LSI-11

System

WRITABLE

Bus

CONTROL

Backplane

Figure

STORE

Assignments

6-12

AE1

MI<22> (SROM 4 H)

BH2

BDALO4

AF1

MI<23> (SROM 5 H)

BJ2

BDALOS5

AJ1

GND

BK2

BDALO6

AM1

GND

BL2

BDALO7
L

AT1

GND

AA2

+5V

"AC2

GND

AE2

BDOUT L

o
-

BM2

BDALOS

BN2

BDALO9

BP2

BDAL10

BR2

BDAL11

AF2

BRPLY L

BS2

BDAL12

AH2

BDIN L

BT2

BDAL13

AJ2

BSYNC L

BU2

BDAL14

AK2

BWTBT L

Bv2

BDAL15

AM2

BIAKI L (JUMPERED TO AN2)

CJ1 -

GND

AN2

BIAKO L

CM1

GND

AP2

BBS7 L

CT1

GND

AR2

BDMGI L (JUMPERED
TO AS2)

CA2

+5V

AS2

BDMGO L

CC2

+5V

AU2

BDALOO L

CMm2

BIAKI

AV2

BDALO1 L

CN2

BIAKO

BA1

BDCOK H

BJ1

CR2

"GND

BDMG!I

CS2

L (JUMPER
TO ED
CS2)

BDMGO

BM1

GND

DJ1

GND

BT1

GND

DM1

BA2

GND

+5bV

DT1

GND

BE2

BDALO2 L

DA2

+5V

BF2

BDALO3 L

DC2

GND

L (JUMPERED TO CN2)

MR-1080

THE

LSI-11

Microinstruction

Bus

WRITABLE

CONTROL

Interconnect
Figure

Cable

STORE

Assignments

6-13

CABLE
PIN NUMBER

(BOTH ENDS)

FUNCTION

MIB<15>

MIB<14>

MIB<13>

MIB<12>

MIB<16>

MIB<17>

MIB<18>

MIB<19>

MiB<20>

MIB<21>

19
24

GND
PH1 H (100 OHM SERIES RESISTANCE)

PH2 H (100 OHM SERIES RESISTANCE)

MIB<11>

MiIB<10>

MIB<9>

MiB<8>

MIB<7>

31
32

MIB<6>
MIB<5>

MIB<4>

34
35
37
38

MIB<3>
MiB<2>
MIB<1>

MIB<<0>
MR-1081

THE

LSI-11

Standard

WRITABLE

TTL

Control

Figure

CONTROL

Bit

STORE

Functions

6-15

BINARY

ocTAL

FUNCTION

0000

NO FUNCTION

0001

RESERVED

0010

AVAILABLE
AVAILABLE

0011

0100

AVAILABLE

0101

AVAILABLE

0110

AVAILABLE

011

PAGE SWAP

(WCS MODE 2 ONLY)
1000

RESERVED

1001

IFCLR+SRUN L

TFCLR L

1010

1011

RFSET L

1100

INITIALIZE SET

1101

FAST DIN

1110

PFCLR L

EFCLRL
MR-1083

CHAPTER

LSI-11

7.1

-GENERAL

The

WCS

Software

A Microassembler

A WCS

Load/Dump

Debug

WCS

understanding

SOFTWARE

TOOLS

utility

programs:

(MICRO)
Program

Program

(WCSLOD)

(MODT)

MACRO-11

and

ODT

(as

described

the

RT-11

docu-

assumed.

MICROASSEMBLER (MICRO)

7.2.1
The

consist

mentation)

7.2

Tools

Statement Format

basic

LABEL;

statement

OPERATOR

The LABEL
gram
and

format

is:

OPERAND
(S)

in a probe alphabetic, a "$", or a ".".
The remaining characters can be any of
these
or
numerics.
A LABEL may be any length;
however, only the first six
characters are significant and, therefore, must be
unigue
among
all
the
LABELs
in
the
source
program.
All LABELs are terminated by a
colon (:), which is not considered part of the LABEL.
A
symbol
used
as a LABEL must not be redefined in the source program.

The

is a means of
1is optional.

;COMMENT

OPERATOR

field

microassembler
The

OPERAND

OPERATOR

ticular
The

contains

either

field

OPERATOR
field

contains
The

and

must

a location
LABEL must

microinstruction

directive.

field.

COMMENT

symbolically referring to
The first character of a

mnemonic

'
additional

format

the

some

cases

begin

with

information
OPERAND

may
a

field

supplement

depends

the

par-

contain

any

omitted.

semicolon

(;)

and

may

LSI-11

information
a

comment

1.2.2
The

with

help
no

document

other

SOFTWARE

the

TOOLS

microprogram.

The

fields.

entire

line

may

Expressions

OPERAND

expression

field

may

consists

Numeric

Symbol

Current

Arithmetic

7.2.2.1
as

radix

may

octal

one

arithmetic

the

logical

following:

expressions.

Constant

Location

Numeric

preted

contain

Counter

Logical

Constants
unless

specified

(.)

Operators

MICRO

assumes

that

otherwise

specified.

the

one

following

all

numbers

constant

are
a

inter-

different

constructs:

"Dn Decimal
"Bn Binary
Where

one

The

ASCII

ing

construct:

equivalent

numeric

characters

character

may

the

specified

with

radix.
the

follow-

'char
where "char" is
equivalent
1is
101 (8).

the printable ASCII character
desired.
For
example,
the

7.2.2.2

and

Symbols
User-Defined

Predefined

- There are
Symbols.

symbols

consist

Microinstruction

Miscellaneous

two

the

types

for
which
constant 'A

symbols:

the
numeric
evaluates to

Predefined

Symbols

following:

names
Extension

Field

Names

Symbols

names are used to specify an
8-bit
internal
register
(for
byte
microinstruction) or a 16-bit internal register
(for word microinstructions).
The Predefined symbols are listed below:

LSI-11

SOFTWARE

TOOLS

SYMBOL

MNEMONIC

VALUE

MEANING

FOR A

PDP1l

MACHINE

RBA
RBAL

2
2

bus
bus

address
address

lower

byte

RBAH

bus

address

upper

byte

RSRC

source

operand

RSRCL

source

operand

lower

byte

RSRCH

source

operand

upper

byte

RDST

destination

operand

RDSTL
RDSTH

destination
destination

operand
operand

RIR
RIRL

10
10

instruction
instruction

lower

byte

RIRH

instruction

upper

byte

RPSW

program

status

word

RPSWL
RPSWH

12
13

program
program

status
status

lower
upper

stack

pointer

SPL

stack

pointer

lower

byte

SPH

stack

pointer

upper

byte

program

counter

PCL

program

counter

lower

byte

PCH

program

counter

upper

byte

indirect

through

OCTAL

RSVC

VALUE

byte

indirect

through

byte

indirect

through

to
are

specify
Microinlisted below:

MEANING

microcode

LRR

Load

Return

TROFF

200

Stop

Trace

microinstruction(s)

7.2.2.3

Current

include
the
tion will be
period (.).

where

Location

after

are

:
Register

be defined as part of
they

Counter

byte
byte

instruction

the

byte

lower

Exit

The Miscellaneous Symbols will

byte

upper

Microinstruction Extension Field Names are used
struction bits <23:16>.
The predefined symbols
MNEMONIC

lower
upper

the definition of

used.

Expressions

may

constructed

<current lcoation counter (the address where the instrucultimately be located).
The location is indicated
by
a

LSI-11

7.2.2.4

Arithmetic

one

the

above

following

Logical

items

Operators

any of

the

TOOLS

Expressions

above

items

are

composed

connected

by one of

operators:
arithmetic sum
arithmetic difference
arithmetic product
arithmetic quotient
logical AND
logical OR

—

the

SOFTWARE

The expression is evaluated left to right (all
operators
have
equal
priority).
Angle
brackets (<>) can be used to group parts of an expression into a term that is evaluated first as shown in the
examples
below:

1+2*3

equals

1+<2*3>

equals

(octal)
7

(octal)

The negative value of a term may be represented by placing a minus (=)
in

front

7.2.3

the

term.

Microinstructions

In the source formats explained in this
present
the
extension
bit
field and
translation symbol.

7.2.3.1

Jump Microinstruction
label:

7.2.3.2

7.2.3.3

JMP

Conditional

section,
a "t" is

an "x" is used to
used to represent

Format:

address,x, t

;comment

Jump Microinstructions

label:

opcode

address,

Literal

Microinstructions

label:

opcode

x,t

Format:

;comment

Format:

1literal,register,x,t

;comment

rethe

LSI-11

7.2.3.4

Two

label:

When
Z,

N),

that

have

7.2.3.5

"F"

the

Microinstructions

opcode

desired

affect

capability

8Single

label:

opcode

7.2.3.7

available

field:

condition

reference

the

status

bit

100

200

and

Set

Flags

opcode

predefined

may

bits

read

MEANING

into

(!)

;comment

into

ORed

opcodes

Format:

Carry

those

codes).

Carry

may

(i.e.,

(for

label:
following

codes

mnemonic

Microinstructions

Zero
‘

Negative

ADDed

(+)

together

Microinstructions

flags,x,t
symbols

(RF

necessary.

and

SF)

use

Format:

;comment

are

available

for

the

flags

MEANING

1
2
4
be

ORed

(!)

internal
internal
internal
or

Input Microinstructions

code

the

VALUE

The

condition

opcode

aregister,x,t

;comment

Reset

symbols

LSI-11
the

affecting

I4
I5
I6
These

Format:

label:

MNEMONIC

symbols

The following
field:

the

appended
to

MNEMONIC

7.2.3.6

TOOLS

bregister,aregister,x,t

The following symbols are
by the CCF instruction:

These

SOFTWARE

opcode

predefined

ADDed

(+)

interrupt
interrupt
interrupt

together

4
5
6

necessary.

Format:

accesscode,register,x,t
symbols

flag
flag
flag

are

available

;comment

for

use

the

access

LSI-11

MNEMONIC

ACCESS

upper

byte

1
2

upper
lower

byte
byte

conditionally

byte

conditionally

LBC

lower

RMW

read/modify/write

load

from

DAL<6:4>

symbols

IW)
IW)

may

ORed

No-Operation
label:

7.2.3.9

Load

The following
able field:

X,t

Condition

Flags

LCF

ADDed

(+)

(NOP)

symbols

are

(LCF)

Z
N

4
10

zZero
negative

for

(Note

that

Reset
label:

TSR

X, t

RFS

ADDed

instruction

X,t

Format:

use

the

(+)

together

flag

necessary.

(RFS) - Format:'

;comment

Microinstruction

RTSR

necessary.

overflow

Return From Subroutine Microinstruction
RFS

;comment

available

carry

label:

load

meaning

(!)

load

Format:

ORed

Microinstruction

<15:0>,

;comment

value

may

DAL

together

mnemonic

symbols

7.2.3.11

flagenables,

predefined

from

load TR from DAL<K15:0>,
from DAL <8:6>

Microinstruction

7.2.3.10

(!)

NOP

label:

These

MEANING

UBC
LB

TG8 (only

7.2.3.8

VALUE

TOOLS

TG6 (only

These

CODE

SOFTWARE

assembles

(RTSR)

;comment

Format:

JMP

4000)

en-

LSI-11

7.2.4

TOOLS

Microassembler Directives

7.2.4.1
The

SOFTWARE

NXT Directive (next) directive

NXT

the

beginning

used

block

aid

placing

microinstructions.

locating

code

NXT2
NXT4
NXT10
NXT20

NXT40
NXT100

NXT200
NXT400

These directives advance the LC
by
the specified power of two.
dition, it is unchanged.

7.2.,4.2

The

TITLE

Directive

TITLE

program

TITLE

title

used

only

directive

the

top of

for

the

assembler

following

the TITLE

purposes

assembly.
the pages.

Only
the first
Examples of the

programs

the

7.2.4.3

SBTTL Directive

SBTTL subtitle

text

The
page

SBTTL

directive

under

the

title

this

causes
line.

REG

Directive

label:

REG

and

has

list
no

the
other

effect

heading

This
on

section.

is
the

top of
sample

Format:

the text to be listed at the top
of
every
This can be used in multi-page listings to

of the program.
The
SBTTL
assembly.
The maximum length

directive
for a sub

Format:

NAME
, VALUE

The REG directive defines NAME to be a register and
specified.
Also 2 additional names are defined:
NAMEL
NAMEH

program

directive.

30 characters will be listed on the
title directive are shown
in
the

make it easier to locate parts
has
no
other
effect
on the
title is 60 characters.

7.2.4.4

title

every page

documentation

end

divisible
that con-

Format:

heading

causes

to the next address
evenly
If the current LC satisfies

gives

the

VALUE

LSI-11

SOFTWARE

TOOLS

These

additional register definitions represent the low and
high
registers
of a pair.
The high register is set to the VALUE+l.
Because
an additional character is concatenated to the name,
it
can
not
be
more
than
5 characters long.
Also, the value must be an even number
because it will be the lower register of the pair.
Registers generated
by
the REG directive will be listed with an R following the value
in the symbol table printed at the end of the assembly listing.
An

example

the

REG

is:

RSLT,
2

RSLT ,RDST

USE

RSLTH,RSRCH

;

THE

HIGH

RSLTL,RIRL

;

THE

LOW

Note

that

used

interchangably,

the

gram more

7.2.4.5

directive

symbols

RSLTL

and

however,

RSLT

the

THE

have

the

distinction

readable.

LOC

Directive

label:

LOC

PAIR

NAME

BYTE

BYTE
same

values

made

and

make

can

the

pro-

Format:

expression

The

LOC directive sets the assembler's Location Counter to an absolute
value.
If
the expression is omitted, the Location Counter is set to
the value it had prior to the last LOC directive.
This is useful
for

going
out of a sequence of instructions then coming back without having to save the Location Counter.
If a label is present
it
will
be
the
value prior to assembling the LOC directive.
The following example details this:

DECODE:

ERROR:

LOC

3001

;

SET

JMP

DECODE

;

BRANCH

LOC

3040
175,RIRL

;

SET

JZBF

ERROR

;

BRANCH

LOC

3037

;

SET

PLACE

;

TRAP

ILLEGAL

;

SET

LOCATION

0,RDST

;

JMP
LOC

LOCATION
TO

LOCATION
IF

INST

CNTR

ILLEGAL

LOCATION
TO

CNTR TO

MICRO

ENTRY

NEW AREA

OPCODE

COUNTER TO

HANDLE

AREA

DECODING

SINGLE

ERROR

INSTRUCTION
COUNTER

SEQUENCE

BACK

(3042)

LSI-11

7.2.4.6
The

End Directive —

END

directive

causes

SOFTWARE

TOOLS

Format:
the

assembler

input
file.
Any lines following the END
the assembler.
If a file is created with
will be generated by the assembler.

7.2.4.7

Equated
SYMBOL

symbol

may be
examples:

the

Symbols
=

stop

reading

source

statement will be
no END statement,

EXPRESSION

assigned

value

X=3
COUNT=X+16

;
;

X IS GIVEN A VALUE OF 3
COUNT IS GIVEN A VALUE OF

TABLE=,+10

TABLE

using

GIVEN

CURRENT

the

equal

A VALUE

LOCATION

(=)

operator

21(8)

COUNTER

+10.

symbol value may be reassigned later in the assembly.
of
the
symbol
will be its last equated value.
Equates
any code to be generated and only the value of the symbol
of the equal sign is affected.

Directive

The

PAGE

the

Format:

THE

7.2.4.8

from

ignored by
an
error

The
not

value
cause

the

left

Format:

PAGE

The

PAGE

page
no

in
other

7.2.4.,9

directive

MODE

on
for

the
the

This

only

skip

the

top

effects

the

listing

tells the
target WCS module.
mode expression.

assembler

Subsequent

MODE

has

WCS addressing mode is set
addresses must be in the range

EXPRESSION

directive

values

and

what

ADDRESS

for

the

RANGE

2000-3777
3000-3777 or
13000-13777

3
4
If

the

Format:

1
2

other

expression

directive

MODE

assembler

listing.
assembly.

Directive

MODE

The

causes the

the assembly
effect on the

2000-3777
0000-1777
is

present,

mode

the

expression

default

result

mode

error.

mode

Any

LSI-11

7.2.5

The

Using

the

assembler
.R

SOFTWARE

MICRO Assembler

invoked

under

RT-11

the

following

command:

MICRO

The microcode assembler prompts with an
entered in the standard RT-11 format.
*OBJFILE,

The
and

TOOLS

asterisk.

Command

1lines

are

.OBJ

LISTFILE=INPFILE (/SWITCHES)

default
.LST.

input

Both the object
lected with the

file

extensions

file and
switches

loads

generates

print a
sembly.

causes

the listing
are:

.MIC,

file

the

are

output

files

optional.

Options

programs directly into the WCS.
This will
independently of the object file generation.
a

cross

bitmap

the

Bitmap

Used

all

listings

When the assembly is complete
number of assembly errors.

7.2.5.1

reference

the

used WCS

fit

message

Memory

locations

will

Locations

program

se-

happen

symbols.

from

this

as-

with

the

columns.
be

The

printed

assembler

optionally

prints
a
bitmap of memory showing which locations are used and which
have not had code generated fo them.
Each line of the
bitmap
represents
100(8)
microwords.
If a corresponding word had an instruction
assembled into it, a 1 would be printed in the place representing
the
location.
If
no
1instruction
was
assembled into the location, a 0
would appear on the bitmap.
If no locations in a 100(8) word
segment
were used, the line is left completely blank.
The
ify

bitmap is useful for
a program with MODT.

7.2.6

Errors

code

the

detected

the

statement

messages

console

and

the
by

left

Source

the

line

source

free

WCS

memory

locations

mod-

Program

assembler

the

following.
the

locating

which

are

line

listed

and

listing
caused

terminal.

7-10

the

with

one

description

being
error

character

produced,
will

the

error

any

printed

error
on

the

LSI-11

7.2.7

WCS

Module

Addressing

SOFTWARE

Mode

TOOLS

Support

The WCS

module will interpret MIB addresses in one of
four
ways
depending
on
the
setting of a DIP switch on the board.
Each mode defines what MIB addresses will be mapped
to
what
WCS
1locations
for
fetching microinstuctions.
The

micro

assembler

uses

the

MODE

directive

(see

section

7.2.4.9)

indicate what mode the WCS module will be set to when the microprogram
is loaded.
If no MODE directive is present, the assembler assumes the
program is for a mode 1 or mode 3 WCS module.
“
In MODE

the

low

and

the

high

512 word

banks

WCS

map

MIB

ad-

dresses 3000-3777.
To differentiate between the two banks of the RAM,
the assembler uses addresses 13000-13777 to refer to
the
high
bank.
Microcode
assembled
for
the low half of the RAM will be listed with
addresses 3000-3777.
If the program executes a JMP from one
bank
to
the
other,
the assembler inserts a 34(8) in the extension bits field
to cause the WCS module to switch to the alternate bank.
To
set
the
assembler's
Location
Counter to the high bank of RAM, the LOC directive

used.

For

example:

LOC

3040

JMP

HIGH

;JMP

HIGH

;EXTENSION

HIGH:

7.3

The
one

LOADING AND

LOC

13477

RDST,G

SAVING

WRITABLE

loader accepts up to six
loadable output file.

7.3.1

Object

BANK

BITS

EQUAL

; 34 (OCTAL)

CONTROL

object

;THIS

INSTRUCTION

sHIGH

BANK OF

STORE

(WCSLOD)

modules

input

RAM

and

can

generate

Modules

At start up the loader Will, by default, initialize all of WCS with:

JMP

0,200

;

disable trace and trap to LSI—ll LOC 10

Upon termination the loader "enables" WCS thereby allowing
programs to be executed.
The switches available are:
/D

disable

/0
/N

suppress
chain to

suppress notification

not

Examples:

.R WCSLOD
*A,B,C

upon exit
notification of
MODT upon exit

the

WCS

initialize

before
of

memory

overlap

loading
translation

array

conflicts

micro-

LSI-11

WCS

has

been

loaded,

initialized,

and

WCS

has

the

been

SOFTWARE

three

TOOLS

files

enabled

A.OBJ,

for

B.OBJ,

C.OBJ

have

execution.

.R WCSLOD
*PPR3.0BJ/R

WCS

not

initialized

but

PPR3.0BJ

loaded

loaded,

and

the

and

WCS

enabled.

.R WCSLOD
*PPR3.0BJ
/N

MODT

V01.01

WCS

initialized,

PPR3

MODT.

1loader

has

chained

.R WCSLOD
*(CR>

WCS is initialized.

7.3.2

Saving

After

Contents

WCS

a session of debugging a microprogram with MICRO ODT

tion
The

the

7.8.3)

syntax

one

for

might

save

the

contents

this is

for

(see

later

Sec-

execution.

WCSLOD

*ABC=/U

This

creates

WCS.

This

file

can

7.4

MICRO

ODT

(MODT)

MODT
the

RT-11

run

with
All

a symbolic
by

LINK

the

Symbolic

The

commands

are

Stopping

amine
o

chine.

syntax

the

sequential

execution

It can be linked
being debugged or
identical to that
of

MODT.

modification

space

tool.

examination

any

address

program

are:

entire

micromachine.

available

and

the

WCSLOD.

microprogrammer

registers.

Starting

macro

The

additional

any

location

microinstruction
microprogram

microcode

Tracing

command

support

debugging

with

module.
o

containing

reloaded

microcode

itself.

ODT-11l

ABC.OBJ

then

utility)

enhancements

support

file

the

any

cycles
given

1location

(using
it can
ODT-11

features

for

the

WCS

debugging.

location

the

ex-

microma-

LSI-11

Automatic

range
are
consistent
chine.
Invalid

valid

TOOLS

checking on addresses typed to ensure the locations
with the WCS module addressing mode in the host maaddresses will cause an error to be
printed.
The

addresses
WCS

SOFTWARE

are:

MODE

ADDRESS

3000-3777 or
13000-13777

‘

will be described using
microprogram
adds the

and Rl

and

7.4.1

Symbolic

colon

fied

stores

(:)

the
not

*3001:

JMP

Just

cation

and

*3040:
3041:

LGL

3042:

the

result

Examination

command

before

that of
WCS and

2000-3777
0000-1777

These features
example.
The

The

RANGE

2000-3777

the

opens

colon.

in R2.

and

Modifications

the

WCS

The

ODT-11,

the

LIL

WCS

except

this

the

an
RO

Locations

address

command

location

opened

speci-

similiar
is

the

WCS

lo-

(CR)

the

caret

location whose

operation

slash (/) of ODT-1l,
PDP-1l1 main memory.
0,200

a specific microprogram
as
contents of PDP-11 registers

line

()

feed

opens

key

the

opens

the

sequential

location.

0,RDST (LF)
RDST (LF)
G,RDRC (CR)

The commands "commercial at"
(@) and "underscore"
(_) can also be used
with
microinstruction in the same way as in ODT-11.
Since the binary
for the microinstruction JMP is zero, the commercial at can
be used to
examine
the target of a JMP instruction.
The target of a conditional
branch can also be examined with the underscore
().

*3001:
3040:

3155:;

3170:

JMP
LL

3040 @
0,RSRC

RSRC,RDST

JZBT

3170

(CR)

Once a location is opened with the colon, it can then
bolically by typing the new contents of the location.
*30062:

JMP

Terminating
the

Using
as

shown

JMP

3040

modification with

modification

tion.
MODT

0,200

the

and

line

below:

then

feed

modified

sym-

(CR)

line

open

the

allows

feed

entire

caret

program

will

perform

sequential

entered

loca-

with

LSI-11

Example

SOFTWARE

Microprogram

Entered

TOOLS

Completely

*3001:
*3040:
3041:

JMP
JMP
JMP

0,200
0,200
0,200

JMP 3040
(CR)
LL 0,RSRC
(LF)
LGL RSRC (LF)

3042:

JMP

0,200

G,RDST

3043:

JMP

0,200

1,RSRC

3044:

JMP

0,200

LGL

RSRC
G,RDST

Compute
with

(LF)
(LF)
(LF)

3045:

JMP

0,200

3046:
3057

JMP
JMP

0,200
0,200

LL 2,RSRC
(LF)
LGL RSRC,RSVC
(LF)

3050:

JMP

0,200

MW RDST,

Each

microinstruction mnemonic

operands

are

separated

bolically using
ters.
Also the
the

extension

R2=R0O+R1

MODT

(LF)

G,TROFF

commas.

(CR)

followed

Notice

the

one

registers

the same names as the standard
MICRO
predefined symbols RSVC, LRR and TROFF

bits

field.

TROFF

causes

the

hardware

spaces,

are

and

typed

sym-

default
regisare accepted in

stop

tracing

microaddresses.

7.4.2

Executing

Microprogram

Format:

address;M

Normally

microprogram

executes

using

itself

the

invoked

instruction.
M

command.

place
3001.

trol
first

to the microprogram.
To
set the PDP-11 registers

machine

language

microprogram can

Typing

this

command

4
3
0

transfer

execute the
to specific

program

also

causes

microinstruction to the specified address
the PDP-11 instruction 076700 is executed

037246
177640
000243

*$0/
*S1/
*$2/
Then

JMP
Then

0767XX

in
to

Add

which

executed
MODT

microlocation
transfer con-

example

above,

(CR)
(CR)
(CR)

control

the

microprogram.

can

examined

*3040;M
The registers
ed properly.

*50/
*$1/
*$2/

000004
000003
000007

now

(CR)
(CR)
(CR)

see

that

the

microprogram

execut-

LSI-11

7.4.3

Dump

Points

SOFTWARE

TOOLS

Format:

address;D

To aid in debugging a microprogram, a facility
ecution
of a microprogram and examine some of

There

are
1.

three
Only

the

Other

ter

restrictions with
registers

registers,

cannot

Once

The

MODT.

The

restrictions

exist

the

internal

registers

RDST,
the

RBA

and

return

RIR

can

and

displayed.
the

regis-

displayed.

RSRC,
RPSW,

dump point

highest

used

this

is provided to stop exthe internal registers.
facility:

reached,

locations

because
of

the

there

the

second

hardware

no
WCS

allows

way

bank

proceed.
of

memory

way

are

access

micromachine.

The internal micromachine registers may be examined only
following
a
Dump
point.
This is done by typing an ampersand (&) followed by the
register name or number.
Only the registers RSRC, RBA, RIR
and
RDST
may be examined.
For example:
*&RIR/

004367

The register may be
lowing the register

*&RIR\

Dump

010

367

HIGH

LOW

BYTE

points

program

gram.
could

examined as two bytes
name.
For example:

has

can

used

taken

and

to
to

determine which
give

information

In the previous microprogram
be inserted as follows:

(section

typing

several
about

the

7.4.1),

backslash

paths
state

fol-

micro-

dump

pro-

point

*3043;D
The

example

*S0/
*$1/

*$2/

can

037246
177640
000243

then

4
3
0

executed:

(CR)
(CR)

(CR)

*3040;M
DP

@addr

The "addr" displayed is the address following the 0767XX which
caused
microcode to be entered.
The microregisters could then be examined:
*§RSRC/
*§RDST/

000000
000004

LSI-11

7.4.4

Tracing

Microprograms

SOFTWARE

TOOLS

Format:

Another debugging aid is the Trace facility
a
program
1is started, the WCS module will

in the WCS hardware.
When
store the last 16 microaddresses from the microinsruction bus
(MIB).
The
tracing
continues
until an instruction with the TROFF (200) bit is executed.
By setting

this

bit

through
vious

the

last

several

example,

instruction

microinstructions

the

operation

complicated

can

seen.

the

command

sequence,

flow

the

pre-

order.
The
first
Addresses with the

inline

can

executing

seen.

*3040;M
*T

The trace
struction
(WAIT)

output will be in
printed
1is
the

following

indicate

instructions)
or
cycles
base machine microcode.

7.4.5

Transferring

reverse execution
last
executed.

wait

cycles

where

the

WCSLOD

(the

extra

instructions

cycles

were

multicycle

fetched

from

the

Format:

Control

can

command.

The

transferred

command

the

WCS

shorthand

loader

for

the

(WCSLOD)

using

the

sequence:

* (CONTROL/C)
.R

WCSLOD

7.4.6

Using

MODT

MODT can either be linked by itself or
It is provided as a .OBJ file with the

7.4.6.1

must

.LINK

This
.R

MODT as a SAVE
be linked using

File -~ If
the RT-11l

MODT is to
command:

programs.

used

typing:

MODT

will

produce

MODT

MODT
*

Using

first

included with
MACRO
entry point MODT.

VO01.01

SAV

file

which

can

executed

itself

LSI-11 SOFTWARE TOOLS

7.4.6.2

Using

MODT with

MACRO-11

Object

Program

debug

ap-

plication involving both MACRO-11l programs and microprograms, MODT can
be linked with a MACRO-1ll object program in the same way as ODT.
This
allows the microprogram to work with the actual data structures set up
by the MACRO-11 program.
MODT can be linked either before
/TRANSFER switch to the linker.

the

.LINK

(CR)

PROG1l,PROGZ,MODT/TRANSFER

TRANSFER

+LINK

ADDRESS?

MODT

program or

after

using

(CR)

/EXEC:PROG1l,MODT,PROG1l,PROG2

In the second example, the program will automatically start
in
Also the /EXEC switch causes the .SAV file to be named PROG1l.SAV

ead

the

MODT.SAV.

MODT.
inst-

CHAPTER
MICROPROGRAMMING

8.1

8
TECHNIQUES

GENERAL

This chapter
programming.

presents

some

techniques

which

are

basic

LSI-1l1

micro-

Thevre are four entry points to user control store, microlocations 3000
through 3003 (octal).
Techniques for utilizing these entry points are
discussed below.
In addition, the External Device and Event Line
pled
during execution of user microcode and if
control to microlocation 3004 (octal).
The

normal

execute

means

user

transferring

machine

control

instruction

the

interrupts can be sampresent, will transfer

user

range

control

076700

store

through

1is

076777.

Each separate user machine instruction is implemented with a
sequence
of
microinstructions.
In many cases these microinstruction sequences
will be largely independent routines and a decoding
function
1is
reguired to pass control to the appropriate sequence.
Optionally, the microinstruction can set or clear condition code
bits
in
the
Processor Status Word (PSW).
The microprogrammer must decide
which

condition

code

flag

state

properly

reflects

the

operation

just

completed.

The

final

step

the

execution

machine

instruction

rejoin

the
LSI-1l machine operating cycle.
This action provides for servicing traps and interrupts and subsequently for fetching
the
next
machine instruction.

8.2
The

USER
user

MICROPROGRAMMING
control

store

ENTRY

entry

POINTS

points

are

microaddresses

3000

through

3003 inclusive.
Control is transferred to the microinstruction stored
at these locations as explained in this section.
1In the normal application,
not
all entry points will be utilized.
The unused locations
should
tions

contain a JMP 0 microinstruction so that entry at
these
locawill result in a reserved instruction trap to LSI-11 vector lo-

cation

10.

MICROPROGRAMMING

There

(1)

are

two

after

transfer

ways

one of
configuring the

3002

8.2.1

control

three

the

Note
0

microinstruction

3000

cause

that

Entry

these

trap

machine

always

LSI-1ll

instruction in the range

that

the

076777.

JMP

only

vector

076000

8.2.3

Entpy:Microaddress 3002

since

Control

transferred

Mode

selected.

are

tion

microinstruction

which

executes

special

these

are

Control

machine

into

are

the

in-

microlocation

user

microprogramwhenever a machine

fetched
in

the

and

range

microprogrammer
for

any

opcode

by Digital.

decoded.

076700

cause

the

range

microaddress

3002 at power-up when
Power-Up
selection is made via a jumper op(see The Microcomputer
Handbook).

located

operations,

for
3001

076777

start-up

Microaddress

transferred

struction

transferred

10.

opcodes

reserved

Since the WCS memory is volatile, a
not be executed out of User Control

Entry

(2)

fetched and decodreserved by Digital.
A

location

3002

should

strap.

8.2.4

occurs:;

can

assembled

executed

Power-Up Mode
processor module

The

the LSI-11

customer

responsibility

microinstruction

076677

points:

decoded

3001

legal

the

and

whenever

(octal)

instructions

must

Microaddress

3000

000227

3001 is the microcode entry point
Control is transferred to microaddress

Note

entry

control

Microaddress
ming.

the

fetched

(3000,3001,3003)

jumpers,

microaddress

000220

ed.

3000

range

JMP

8.2.2

power-up

Microaddress

transferred

instruction

microaddresses

LSI-1l

transferred

struction

machine

power-up.

Entry

Control

that

appropriate

TECHNIQUES

microcoded
Store.

jump

possibly

microroutine

system

power-up

boot-

routine

can

machine

in-

3003

microaddress

3003

whenever

in
the
range
075040-075777 is fetched and decoded.
Note
that these machine instructions are reserved by Digital and
a
JMP
0
microinstruction
must
always be assembled into microlocation 3003 to
cause

8.2.5

trap

LSI-11

vector

location

10.

EnttyiMicroaddress Summary

Because
cations,
must

all

the

microaddress entry points are positioned
the micrecinstructions located in the entry

unconditional

jumps.

Each

JMP

in sequential loarea 3000 to 3003

microinstruction

then

MICROPROGRAMMING

TECHNIQUES

transfers
control
to a microroutine which implements the
operations.
The source code for the entry area
normally

follows:

LOC
JMP

3000
0

A3001:

JMP

A3002:
A3003:

JMP
JMP

appropriate

appears

;7
;

DECODE

SET MICROASSEMBLER COUNTER LOCATION
TRAP RESERVED OPCODES 00022X

;

PWRUP
0

;
;

ENTER HERE FOR OPCODES 076XXX
ENTER HERE FOR POWER-UP
TRAP RESERVED OPCODES 075040-075777

DECQDE:

;

START

USER

PWRUP:

;

START

POWER

A3000:

8.3

MACHINE

INSTRUCTION

DECODING

OPCODE
UP

DECODE

ROUTINE

TECHNIQUES

Control will be transferred to user entry point 3001
in
response
to
machine
instructions in the range 076000~-076777.
This instruction is
contained in micromachine register RIR.
The low order 8 bits
of
the
instruction
are
in
RIRH and the high order 8 bits are in RIRL.
The
microprogrammer's first task is to determine which machine instruction
has
been
fetched.
Note
that opcodes 076700 to 076777 are the only
legal

customer

opcodes

microinstruction

8.3.1

Successive

and

opcodes

076000

076677

must

cause

JMP

executed.

Comparison

Decoding

One technique for decoding user opcodes is by
successive
comparison.
An implementation of this technique is to use a Compare Literal Microinstruction (CL) for each expected user opcode.
The sequence
of
mi-

croinstructions

this

technique

076400

0767007

175,RIRL

;

JZBF

ERRCR

;

NO,

300,RIRH

;

JZBT

OoP0O0

YES,

GO EXECUTE
GO

301,RIRH

;
7

YES,

302,RIRH

;

JZBT

oP02

YES,

EXECUTE

additional

comparison

for

each

opcode

follows:

0767007

oPO1

TRAP

JMP

JZBT
CL

ERROR:

implements

DECODE:

which

0767017

EXECUTE

0767027

NONE

THEM,

implemented

TRAP

VECTOR

10.

MICROPROGRAMMING

8.3.2
This

Modified

Jump

Decoding

microinstruction

coded

decoding

technique allows user opcodes to be dethan the successive comparison technique, espenumber of opcodes are implemented.

efficiently

cially when

a large

This technique uses the lower
instruction
to
dispatch
to
that

RPSWL

The

assembled

contains

control into a
illustrated in
DECODE:

TECHNIQUES

all

address

six
the

bits of the
appropriate

zeroes

upon

JMP

the

entry

low byte of the
machine
microcode routine.
Note

1into

instruction

user
is

dispatch table of JMP instructions.
the following example:

control

modified

This

store.
transfer

technique

JZBT

175,RIRL
DC1

;
;

IS IT
MAYBE

DCO:

JMP

;

DC1:

;
;

IF NOT, TRAP TO VECTOR 10
IF LEGAL, C8=1 AND RIRH<7:6>=00
NO, GO TRAP

DISPAT:

JC8F

100,RIRH
DCO

RPSWL ,RIRH

;

MODIFY

JMP

3200

;

MACHINE

LOC

3200

LEGAL

THE

USER

JMP

OPCODE?

BITS

INSTRUCTION

;

THIS

TABLE

;

BITS

<5:0>=0

ADDRESS

<5:0>

WITH

BITS

<5:0>

MUST

JMP

OP00

;

JUMP

JMP

FOR

OPCODE

OorPO1

076700

;

JUMP

FOR OPCODE

JMP

076701

OP02

;

JUMP

FOR

076702

OPCODE

In this example, the starting microaddress of the
3200
octal.
Micromachine control is transferred

dispatch

table
a

Control is subsequently
microprogram appropriate

begins.

8.4

076700

PASSING

LSI-11
erand

machine

OPERANDS

memory

general

may

MACHINE

example

data

some

Operand

transferred
to
to the execution

this
word,

means

for

delivering

the

operands

LSI-11

technique
a

the

operands

opmito

Addressing

specific

immediately

machine

INSTRUCTIONS

processing.

applications,

1in
locations.

location(s)
access

USER

provide

for

Predefined

less

tion

must

micromachine

8.4.1
In

when

data manipulation machine instructions allow very flexible
addressing.
In the design of new machine instructions, the

croprogrammer

the

opcode

HAVE

here

opcode of 076700 is decoded.
microaddress
OP00 where the
the

General

1is

following

sequence

the

similar

RIW2

PCH,PCL

;

FETCH

+RSRC

;

PUT

THE

user-defined

Purpose

place

Registers

the

instruction

data

main

the

following

WORD

AND

UPDATE

DATA

RSRC

THE

instruc-

word(s)

memory.

would

machine

used:

MICROPROGRAMMING

8.4.2

Since

user

order

opcodes
bits

particular,
Purpose

Operand

can

the

Registers

the

bits
will

could
be

Purpose

RIRH

;

LOAD

;

PUT

when

this

can

technique

specified

can

one

the

The

l6-bit

following

used,

operand

the

then

accessed

<8:6>

Bits

<2:0>

8.5

can

3rd

number

accessed

PCH,PCL

FETCH

TG8,RIRL

;

LOAD

G,RDST

;

PUT

LGL

RIRH

;

LOAD

G,RBA

;

PUT

Defining

first
functions

step

The

number

tion on

input

possible

all

tuations.

the

and

fol-

the

following:

THE
G

WORD

FROM

AND

BITS

CONTENTS

unigue

specified

instruction

RSRC

UPDATED

main

instruc-

assembling
memory

<8:6>
2ND

RDST

3RD

RBA

CONTENTS

INSTRUCTION

Instruction
the
pro-

first in
LSI-11
machine-level
assembly
usually will also reveal the suitability of
accomplish a desired collection of functions.

approach

the

Instruction

for instruction
functions provided.

for

1In

instruction.

INTO

the

USER MACHINE

requirements
the

1low

General

function(s)

Documenting

LSI-11

creating a new machine instruction is to define
instruction is to accomplish.
One approach is to

microprogramming

8.5.2

the

manner.

the

gram the desired
language.
This

ture

number

RIWZ

The

MICROPROGRAMMING THE

8.5.1

following

2nd

then

the

reduced.

format:

Bits

words

any

the

Additional.General Purpose Registers can be
one

076777,

CONTENTS

through

utilized

specify

G,RSRC

076700

can

used

LGL

that

range

instruction

that

tions

that

The specific General
lowing manner:

Note

Addressing

the

lower

TECHNIQUES

output

documentation

operands,

situations,

and

Such

will vary with
documentation includes

resultant

execution

PSW condition

timing

for

all

the

nainforma-

code

flags

possible

si-

MICROPROGRAMMING

8.5.3

Temporary

During

the

necessary

Flag

execution
to

monitor

TECHNIQUES

Use

user-designed

ALU

results.

machine

These

instructions

results

are

status bit and condition code flag register and may
microprogram
control
via
the
Conditional
Jump

available

often

the

be used to
effect
microinstructions.
However, when the machine instruction operations have been
completed,
additional
microinstructions
may
be
needed to update the Processor

Status

Word

condition

code

flags,

(N,Z%Z,V,C).

sides

Note

that

the

PSW

re-

1in a microprocessor register and that it is partially separated
from the ALU flag register.
The microprogrammer must decide what
PSW
flag
states
accurately
represent the operation executed and provide
for their implementation.

8.5.4

Executing

Machine-Level

The

microprogrammer has
possible
machine-level

TIOB)

part

tion

the

reference
and

Output

new

Operations

complete freedom in implementing any of the
5
1I/0 operations (DATI, DATO, DATOB, DATIO, DA~

machine

instruction,

instruction.

the

Chapter

5.
All
require a

Status,

I/0

designing

microprogrammer

I/0 operations,
response from a

should

the

I/O

make

other

than

Input

system

bus

device

fectively transfer control outside the processor.
tions,
a
non-responding bus device will cause a
microprogrammer must recognize the possibility of
devices.

por-

detailed
Status
and

ef-

Under normal condibus error trap.
The
non-responding
bus

8.5.4.1
Bus Error Trap Control - The
microprocessor
register
RPSWL
contains
flags
designated for bus error trap control.
Prior to executing any of the five I/0 operations (DATI, DATO, DATOB,
DATIO,
DA-

TIOB),

the

contents

bus

timeout

error

tem

memory

location

8.5.5
Many

Scratch
processes

mediate

will

RPSWL

handled

Usage

require

scratch

This

the

Note

used

PDP-11l

zero.

the

section

processor

the

emulation

that

space

discusses

conditions

way,

the

under

microcode

This

normal

results.

must

will

which

and

no way

The

source

store

inter-

each

micro-

may

refect

that

trap

function

names

ensure

the

sys-

used
by
conventions

dictate

required

operand

usage.

8.5.5.1
may

left

Source Operand
used

for

in ye

scratch

conclusion

the

(RSRC)
during

user

microprogram

microprogram.

execution.

may

MICROPROGRAMMING

8.5.5.2

Destination

may

tion.

may

Operand

used

left

for

scratch

any

TECHNIQUES

state

(RDST)

the

- The
during

destination operand
microprogram execuconclusion of the
user
mi-

storage

croprogram.

8.5.5.3

Instruction

whether

standard

gister as
byte
of
high byte
used

user
gram

part

the

instruction,
instruction

re-

of the machine instruction fetch
operation.
The
the machine instruction is loaded into RIRH.
Similarly,
of the machine instruction is loaded into RIRL.
RIR can

low
the
be

for
scratch
storage
after the instruction is decoded.
If the
opcode transmits no information to the micromachine the micropromay then use the upper and lower byte of RIR for scratch storage.

8.5.5.4

used
left

machine
into

Bus Address Register
(RBA)
for
scratch
storage
during
in any state at the conclusion

8.5.5.5

LSI-1ll

General

Purpose

Processor

- The bus address register may
microprogram execution.
It may
of the user microprogram.

Registers

(RO-R5)

- The

through

can

LSI-11

used

for

be
be

processor

scratch

sto-

rage during microprogram execution.
Instruction results can
be
left
in
General
Purpose Registers.
Note that an access of a General Purpose Register requires the G register to contain the
proper
register
number

indirectly

access

the

general

purpose

8.5.5.6
LSI-1ll Stack Pointer
(R6)
and
Stack
Pointer and Program Counter should

instruction

may

the

directly

Program

(without

Counter

Program
Counter
(R7) - The
never be used as scratch repass parameters on the stack.

the G

the

Stack

Pointer

8.5.5.7

Processor

(RPSW)

- The

gisters.

Note

However,

that

word
register
LSI-11 PSW bits
type

The

main

LSI-11

code

flags.

Status Word

serves
<7:4>;

memory

PSW

new

two
(2)

bus

purposes:
(1)
RPSWL contains a

timeout

formed

Therefore,

by
bits

and

the

error

has

RPSWH
code

accessed

processor

status

contains a copy of
to
indicate
which

occurred.

logical

<3:0>

can

OR of RPSWH and
RPSWH must always

four condition
be 0.

Since

a main memory bus timeout can occur not only during machine
instruction
execution, but also during console ODT routines, RPSWL contains a code to indicate which type of bus timeout error has occurred.

Therefore,

will

must

RPSWL
maintained

a 0
during

after a
any I/0

machine

instruction
operation.

fetch

and

MICROPROGRAMMING TECHNIQUES

Block

Move

OO
N DW=

Figure

MICRO

ASSEMBLER

JTHIS

:TO

MOVE

Example

8-1-1

V01,01

LSI=11

BLOCK

0O0W

MICRO

CODE

MEMORY

SUBRCGUTINE

FROM

ONE

PLACE

tELSE,
“o

THIS ROUTINE ILLUSTRATES,..
1) HOW A LONG RUNNING MICROCODE

PENDING

THE INPUT
RO :SOURCE

R1IDESTINATION

R2:#NR,

10
3000

3000

(OF

Lot

000

000000

3Jootl

000

003014

3002
3003

000

000000

000

000000

3004

INTERRUPTS

PARAMETERS
ADDRESS

ERROR:

GET

SOME

PLACE

SUBROUTINE

SERVICED

ENSURES

TIMELY

THAT

FASHION,

ARFE

ADDRESS

WORDS

MDVED

3000
0

JMP
JMe
JMP

JMP

MOV

Loc
3004
sUNNECESSARY ,JUST FOR CLARITY.
JAN INTERRUPT
HAS OCCURRED,
MUST SUSPEND THIS OPERATION
$IN SUCH A wAY AS TU ALLOW THE NPERATION T0 BE RESUMED RATHER
JTHAN RESTARTED AFTER THE INTERRUPT HAS BEEN PROCESSED
$TO ACCOMPLISH THIS IT 18 NECESSARY TO UPDATE THE INPUT PARAMETERS

JAND

BACK

$MICROCODE,

¢THE

WEXT

JONLY

NOW

THE
IN

RASE

THIS

MACHINE

WAY

INSTRUCTION
WITH

THE

FETCH

UPDATED

PROGRAM

3004

000

3005

3no06
3007
3010
3011

COUNTKR,

INTERRUPT

WILL

VALUES

WILlL

AGAIN

THE

sPARAMETERS

EXECUTE

uo0

I.L

000

101100

000

1,RIRH

000

060031
072411

sUPDATE

LGL

RIRH

000

101140

3012

RDST.,G

002
000

027756
073417

3013

376,PCL,RSVC

tDECREMENT

coB

PCH

JAND

tPRUOCKESS

3014

000

033730

3015

000

010003

3016
3017
3020
3o21

000

022011

000

011003

000

060011
072411

3023

0oo
000
000

MOV 3

0,RIRH

sUPDATE

LGL

RIRH

RSRC,G

THE

MOVE

175,RIRL

JZ8F
AL

ERRNR

JC8F
LL

101004

BLOCK

LSI=11

MEXT

sLEGAL

s IF

$COPY

LGL

RIRH

G,RSEC

!GET

CONTENTS

INTO

060031

1,RIRH

tCOPY

101006

LGL

RIRH

G,RDST

:GFT

3026

000

060051

tFROM

THIS

3027

000

072411

2,RIFH

MICRO

1030

LGL

REG

RIRH

3031

nooQ

GeG

!1S

3032

000

143000
010443
173124

3033

Voo

137400

DW1F

*TAKE

3034

[§1eX¢]

JHBA

;COPY

wiwg

RDSTH,RDSIL

ITHEN

RRAH ,RRAL

nQo

176462

POINT

SIZE

TWO

WORD
BASE MACHINE
MICROCODE

CONTENTS

INTU

LSI=11

EX1T
RSRCH,RSKCL

THi

?CALSO

BLOCK

REG

LSI=11

ADDR

WILL

ALWAYS

(WURD

WORD

COUNT

;PUT

SOURCE

HUMPING

SOURCE

REG

1DLE

LSI=11
MOVE

ADDR

REG)

(R2)

ADDR,

DATA

ACCESS LINES.

POINTER).

TIME

UPDATE

UPERAND

BLOCK

PUINT

COUNT

SQURCE

ADVANTAGE

JCUNTENTS

RDST

PUINT

ADDR

MICRUO=REG

DEST

LSI=11
RSRC

BLOCK

072411

000

POINT TO

C8=1

M{CRO=REG

SOURCE

000

303%

INSTRUCTION
AND

INSTRUCTION?

LEGAL

000

3036

EXIT

3024

161002
173566

AND

076000

INSTRUCTION

JZ87T
RIwz

THF

DESTINATION,

DESTINATION

3028

[.OOP:

EXIT

PROCESSED,

WORD

LSI=11

100,RIRH
ERROR

0,RIFPH

SOURCE

THEN

SOURCE,

060011
072411

3022

INTQ

WORD

ALSN

SCRATCH

BACK

BUMPING

OUT
DEST

DEST

ADDR
MR-1319

8~10a

MICROPROGRAMMING

Block

Move

Figure

MICRO

3037

Q00

070500

ASSEMBLER

Example
8-1-2

V01,01

S1I

TECHNIQUES

00w

THIS

FLAG

ALTERS

:SUCH

THAT

AFTER

70F

MICRO

swllLl

63,

CODFE

THE
THE

RSVC,

RETURNED

ONE

;IS

PENDING

TWO

INTHRRUPT

CHAIN

CUNTROL

THE

WAYS.

CONTRUL

DECISION

EXECUTION

MICROCODE
AN

WILL

INTERRUPT

710 MICRO LUCATION 3004,
IF NO
fINTERRUPTS PENDING CONTROL wlLL
GO TO THE INSTRUCTION FOLLOWING

64
65
66

:THE

3040

002

177400

NOP

3041

RSVC

000

JEXIT

070100

THRESET

INSTRUCTION,

SERVICFE

sCONTROI,

3042

000

014032

3043

002

177400

3044

000

177400

3045

ANY

[INTERRUPT

FLAG
RETURNS

HERE

P INTERRUPT.

EXIT:

JZF

Lnop

PIF

NOR

RSVC

ANY

ELSE,

wWOKRDS,

RETURN

NOP

MOVE

RASE

THEM,

MACHINE

«END

0001

MITRU

ASSEMBLER

V01,01

0O0OwWSYMBOL

0040

002y

KRROR

3003

0000R

TARLE

Exyr
15

3043

0000PR

Q001R

0004

0001

LBl

3014

0010

3032

PCL

U0ilnmR

0200

RHA

(002K

OU16R

RDSTH

FRAH

Q007R

(0003R

RDSTL

RRAL

0006k

0002R

FIR

RDST

001Uk

0006R

RIRH

0O0f11R

RIRL

0010R

MOV

0003

LOoP

0001

0002

LRR

0001X

PCH

0017R

RMw

0004

FPSw

Q012R

RPSwH

RSRCH

0013R

000SR

RPSwhL

HSRCL

0012R

0Q004R

RSRC

REVC

0004R

8PL

0014R

0002X

TG6

0001

0014R

SPH

0000

0002

0015SR

TGH

UBC

TGL

0002

N034X

TROFF

0200X

00v2

0004

0100
MRA-1015

8-10b

MICROPROGRAMMING

8.7

New

MICROPROGRAMMING

user-defined

USER-DEFINED

trap operations

TECHNIQUES:

TRAP

may

VECTORS

implemented

the

micropro-

grammer.
This
1is
accomplished
by
setting up a vector address
transferring control to the base microcode routine which executes
other LSI-1l1 trap operations.

8.7.1

Creating

the

Vector

Addresses

The vector address of the special
wuser
trap
1is
l6-bit
source
operand
scratch register, RSRC.

with two
the high

8.7.2

consecutive
byte of the

Joining

the

inserted
1into
Usually this is

Load Literal microinstructions.
vector address and RSRCL the low

Base

and
all

RSRCH
byte.

the
done

receives

Microcode

Once

the 16-bit vector address has been loaded into RSRC, an
unconditional
Jjump
microinstruction transfers control to the base microcode
routine which executes the trap operation.
The
microinstruction
sequence 1s as follows:

8.8

VEC

LOW

VEC

HIGH

JMP

1402

MICROPROGRAMMING

BYTE,

RSRCL

BYTE,

RSRCH

SYNCHRONIZED

;

LOAD

VECTOR

LOW

;

LOAD

VECTOR

HIGH

;

JUMP

CONTROL

TRAP

BYTE
BYTE

ROUTINE

SIGNALS

A microinstruction word contains four TTL Control Bits
ilable
from
the
LSI-11 CPU module at the backplane.

which are
avaTwo additional

Extended

module

TTL

backplane.
of external

8.8.1
The

Standard

standard

the
try.
pages

Control

These
logic.

TTL

possible

Bits

are

available

TTL Control

TTL Control
control

codes,

can

from

the

used

WCS

for

the

MI<21:18>.

high

speed

control

Bits

bit

Bits

codes

are

One additional code, 07,
for WCS address mode 2.

are

employed

assembled

the

into

LSI-11

is used
to
swap
Codes 02 through

interface

user
and

circui-

control
store
10 may be used

by the microprogrammer.
These
codes
must
be
decoded
by
external
hardware
which
1is connected to the system backplane.
Chapter 6 presents information on standard TTL control function codes
as
well
as
hardware

connection

details.

MICROPROGRAMMING

WCS

TTL

extended

same

source

The

assembly

TTL

field
value

0,RSRCL,

Note

that

This has
ging.

8.9

the

bits

standard

corresponding

effect

CONTROLLING

(MI<23:22>)

are

TTL

bits.

shared

THE

control

MI<22>

200.
These values
as shown below:
1411001200

MI<23>

Bits

control

ing
to MIK23> is
control bit code,
LL

Control

may

The

Extended

CONTROL

-y

8.8.2

TECHNIQUES

PLUS

with

the

MI<23>

but

assembled

100

and

ORed with

CODE

MI<22>

MICROINSTRUCTION

trace

complicate

bit

is MI<K17>

Control

chip

and

direct

translation

array.

microprocessor
a
function of

but

this

facility

Control chip can
Location Counter

not

the

The

(1)

avoid

jumps

any

assemble
only a JMP or RFS microinstruction
will override the translation).

8.9.1

Leaving

User

Control

the

bit

invoked
NOP

NOP

Note

only

must

as
RSVC

means
set

shown

well

used
for
user should
locations

the
ei-

(2)

(which

Store

bit

RSVC

locations,

those

of the RSVC bit, MI<K17>, is to return
the
interrupt and trap interrogation

provides

the

disposal.

these
in

The function
ginning
of
The

microinstruc-

also modify microinstruction
flow
and translation register contents,

microprogrammer's

assembling microcode

input

jump

Figure 8-2 contains a list of microlocations (normally
EIS/FIS microcode) that invoke such translations.
The

ther

logic.

available
to
the
jump microinstruc-

control

tions include both conditional and unconditional
Return From Subroutine (RFS) microinstruction.
The
as

RAM

FLOW

tions.

RSVC

TTL

microprogram debug-

controlling microinstruction flow
are:
(1) the RSVC bit and (2) the

The

correspond-

standard

MI<23>

The two means of
microprogrammer
microprocessor

the

03
PLUS

microaddress

may

that

1into

for
one

transferring

control

microinstruction

the

example

;

EXIT

USER

MICROINSTRUCTION

CONTROL

than

the

before

this

the

beRSVC
point.

translation

below:

;

that any microinstruction other
conditional) or RFS can be used with
microinstruction.

control to the
sequence.
The

STORE

AFTER

THE

a jump (conditional
or
unRSVC bit or as the subsegquent

MICROPROGRAMMING TECHNIQUES

EIS/FIS Translation
Figure

Micro-

Locations

8-2

Micro-

address

Translation

address

Translation

2033
2072
2123
2172
2220
2254

Ell
Ell
PSW
PSW
Fll
Fli

2652
2553
2571
2604
2614

RET
RET
DMW
Ell
Ell

2274
2320
2406
2447
2500

Fil
Fll
Fli
Ell
El

2516
2540
2550
2551

PSW
Ell
RET
RET

2622
2630
2644
2654
2700
2710
2714

PSW
PSW
El
Ell
Ell
Ell
PSW

2717
2740
2750

PSW
Ell
EH

2754

PSW
MR 1031

MICROPROGRAMMING

8.9.2
The

Jump

cation

Subroutine

counter

set

(JSR)

contents

loads the Return
microinstruction

(MI<16>)

demonstrates

JSR

SUB:

8.9.3

Return

Microinstruction

with

The

the

Return

also

;

two

;

DUMMY
DUMMY

RFS

;

RETURN

Conditional

Jump

From

SUBROUTINE

;

Location

the

into

entire

MI<10:0>

Subroutine

(RFS)

lo-

and
JSR

bit
microinstruc-—

the
The

Return

Re~
following

microinstructions:

NOP

Conditional

replaces

assembled

Counter contents with
override
translations.

NOP

the

ll-bits

Location

these

SUB

The

Microinstructions

tion replaces the entire
gister contents and will
example

and

TECHNIQUES

JUMP

AND

RETURN

Microinstruction

microinstruction

affects only the lower 8 bits of
upper 3 bits remain the same from the updated Location Counter.
Since only 8 bits may be modified, the conditional
jump page is only 256 microaddresses in length.
The microprogrammer is cautioned against placing conditional jumps in the last location
of
a
(256
microaddress) page because the top four bits will
normally be incremented during the second microcycle, causing
control
to

transfer

Counter.

the

The

page.

CHAPTER

INSTALLATION

9.1

GENERAL

This chapter contains procedures for unpacking,
tial checkout for the LSI-11 WCS options.

9.2

installation and

1ini-

UNPACKING AND INSPECTION

The LSI-11 WCS is packaged in
accordance
with
commercial
packaging
practices.
Remove
all packing material and check the equipment against the shipping list.
Table 9-1 lists the items supplied per configuration.
Report any damage shortages to the shipper immediately and
notify the Digital representitive.
Inspect all
parts
and
carefully
inspect
the
<circuit
boards for cracks, loose components and separations

the

etched paths.

NOTE

If Digital
Field
Service
1Installation
has
been
contracted, then the customer
should not break any seals on the
shipping containers.

9.3

INSTALLATION

PROCEDURE

The following procedures should be followed to
M8018 WCS module option in an LSI-1l1 system.

9.3.1

Switch

properly

install

the

Configurations

The range of microcode addresses to which the WCS will respond on
the
Microinstruction
Bus
(MIB) (when the CSR Enable Bit is a "1") is determined by an 8 wide DIP Switch (SWl) on the M8018 module.

INSTALLATION

Items

Supplied

Per

Table

Configuration

9-1

MODELS
ITEM
KUV11-UH | KD11-WA

11/03-WC

11/03-WD

KD11-H CPU

M8018 WCS MODULE

MODULE

BAT1-NC BOX (115 V)

WCS CABLE
Part NO 17-00124-00
KD11-R CPU

(Includes MSV11-CD
memory)

BDV11-AA BOOT

BA11-ND BOX (230V)

1059

INSTALLATION

Set switches S1 through S7 (S8 is not used) on SW1 as shown
1in
Table
9-2 to select one of the four modes of operation described below:

Mode

The microcode is loaded from the LSI-11 Bus into WCS RAM locations
0 to 1777.
The WCS correspondingly responds to microaddresses 2000 to 3777 on the MIB.

Mode

The microcode is loaded from the LSI-11 Bus into WCS RAM locations 0 to 1777.
The WCS initially responds to MIB microaddresses 3000 to 3777 from the first 512 words of RAM.
If
bits
<21:18>
of
the
microinstruction
are
<coded
to a 7
(octal) then the next microinsturction will be accessed from
the second 512 words of RAM.
A second 7 (octal) will toggle
back to the first 512 words of RAM.
This
swapping
between
512
word
Paging and

when only

blocks
allows

for
1024

the same
words of

512 microaddresses

microaddress
microcode to

are

range is called
be
implemented

available.

Mode

III

This mode is the same as Mode I except that the
of
512
words
of RAM have been interchanged on
Addressing is identical to Mode I.

Mode

The microcode is loaded from the LSI-11 Bus into WCS RAM locations
0 to 1777.
The WCS correspondingly responds to MIB
microaddresses 0 to 1777.
This microaddress space is identical
to
MICROMs 0 and 1, which contain the base PDP-11 microcode for the LSI-11.

9.3.2

Cable

Configuration

Configure the cable/plug assembly
the shape as shown in Figure 9-1.

9.3.3

WCS

two
blocks
the module.

(Digital part number

17-00124-00)

Installation

Install the M8018 WCS
module
1into
the
LSI-11
system
as
follows:
(CAUTION:
Great care must be taken when inserting or removing the 40
pin DIP connector on the cable/plug assembly.
A grounded work area as
well
as other normal anti-electrostatic discharge precautions are recommended)
.

1Insert

the

plug,

not

marked

"CPU",

the

cabe/plug

assembly

into
the 40 pin socket (J1) on the M8018 WCS module with the
chamfer positioned at pin 1 so that
the
edge
of
the
plug
where the cable enters is toward the module handle.

Place the M7264-YC CPU module on the top of the M8018 WCS module between the module and the free plug marked "CPU".
(See
Figure 9-2).

1Insert the plug marked "CPU" into the empty 40 pin DIP socket
(E75) on the M7264-YC CPU module as shown in Figure 9-2.
The
chamfer should be positioned at pin 1 so that the edge of the
plug where the cable enters is toward the handle.

INSTALLATION

WCS

Address

Mode

Switch

Table

9-2

Settings

SWITCH Swi1
MODE

OFF

—

OFF

—

OFF

(Y]

OFF

—
MR 1060

INSTALLATION

Cable/Plug Assembly

IRBR

Figure

X 6 62 X 2 2 8

NRCIABRNXHO5NK0S5

Configuration

9-1

17-00124-00

CPU

MR-1084

INSTALLATION

WCS

CPU

Installation

Figure

9-2

M7264

M8018

]
[

I
I

I
|
|
|

I
I
I
I
|

—- ]
=

‘

——

—
|

{

_r—l I
|

-e

]

[
MR-1085

INSTALLATION

Finally, insert the
and
2 (M7264-YC in

two modules simulataeously into
slots
1
slot 1 and M8018 in slot 2) of the LSI-11

backplane.

9.4

PERFORMANCE

CHECKOUT

The KUV11-AA LSI-11 WCS Module (M8018) can be checked for proper
performance
by
running
the KUV11-AA diagnostic (CVKUA-A).
This is the
only diagnostic for the KUV11-AA and it enables the user to check
out
and trouble shoot the module.
The diagnostic is designed to run on an
LSI-11 (M7264-YC) with a serial line interface,
a
console
terminal,
and
4K
(minimum)
of memory.
It can be run under XXDP, ACT, and APT

monitors and is not supervisor
ter (location 176) is used.

compatible.

The software switch regis-

NOTE

If
of

the diagnostic is run
memory (minimum) will

For operating instructions
nostic listing.

and

under XXDP,
be needed.

test details

refer

the

CVKUA-A diag-

CHAPTER

MAINTENANCE

10.1

GENERAL

Maintenance for the KUV11-AA LSI-11 WCS Module (M8018) is discussed in
this
chapter.
It is expected that all the material contained in previous chapters should be read and understood before performing any maintenance on the KUV1l-AA,

10.2

PREVENTIVE

MAINTENANCE

Preventive maintenance
for
checking
the WCS cable for
both 40 pin plugs are fully

10.3

CORRECTIVE

MAINTENANCE

the
KUV11l-AA
consists
of
periodically
kinks, pinches or bends and to ensure that
inserted in their sockets.

PHILOSOPHY

The KUV11-AA LSI-11 WCS module (M8018) is designed so that module
replacement
can restore the system to operating status in minimum time.
Diagnosing the WCS will consist of first determining that the
CPU
is
properly
operating
(it may be necessary to test the CPU with the Wcs
removed from the system).
Next the WCS module would be tested, and if
it is at fault, it should be replaced with a spare.

10.4

CORRECTIVE

Corrective

CVKUA-A

MAINTENANCE

maintenance

KUV11l-AA

is performed

(LSI-11

WCS)

the WCS

diagnostic

module

(listing

running

part

the

number

AC-E102A-MC, paper tape part number AK-E104A-MC).
In order to run all
the tests most efficiently, a test cable (part number 17-00124-01) and
a quad extender module may be used.
Error
messages
will
print
out
when
a
test sequence fails.
These messages will aid in fault detection.
The diagnostic performs the following tests:
TEST

TEST

Bit Test Registers-Tries
three
device registers.

10-1

re-

to set and clear bits in the
Checks the functionality of

MAINTENANCE

the

CSR

Test,

TEST

RAM

TEST

Address
Tests

enable

Mode
the

respect

TEST

via

Tests

Mode

respect

interface
WCS)

the

and

TEST

Address

Tests
respect

TEST

WCS),

the

Mode

address

microaddress
When

WCS

RAM

operation
output

logic.

WCS

operation

paging

output
logic

and

trace

(both

memory.

WCS)

and

the

and

the

Test-Verifies

range

the

enable

also
microcode

respond

1777

logic.

that

the

which

base

LSI-11

the

bit

with
trace

in Mode 1.
input with

WCS

(octal),

with

Mode

input

and

trace

Mode

input

Mode 3 Test-Verifies WCS operation
the
MIB interface
(both output and

Address

MIB

the

interface

logic.

the

(both

Test-Verifies

MIB

Bus-Tests

Test-Verifies

the

(bit<12>).

LSI-1l1l

MIB

Address

bit

occupies

the

same

microcode.

is set (CSR bit<12>=1), the WCS
to the microaddresses in
the
base
range, its output being ORed with the base
microinstruction accessed.

will

Refer

to
cedures.

the

diagnostic

listing

additional

the

(DVKAB-A

verification
Software
Tools

WCS

and

1loading

into

the

DVKAC-A

the

WCS

test

mode

and

should

address

are

microcode

enabling

WCS

performed

with

mode

description

and

test

pro-

WCS functionallity can be performed when
(QJV40-YY)
and the EIS and FIS diagnostics

tics.
This

further

respectively)

EIS/FIS

module,

for

III

and

give

available.

(included

the

then

WCS

compete

10-2

with

The

executing

module

test

the

set

coverage

consists

Software

the

to
to

two

both
the

Tools)

diagnos-

WCS

address
RAM.

APPENDIX

INSTRUCTION

SUMMARY

OoP

NMEMONIC

OPERATION

0(0)

JMP

LC<--MIR<11:0>

0 (8-F)

RFS

LC<~--RETURN

JZBF

zB=0,LC<--MIR<7:0>

JZBT

zB=1,LC<~--MIR<7:0>

JC8F

C8=0,LC<--MIR<7:0>

JC8T

C8=1,LC<--MIR<7:0>

JIF

ICS=0,LC<--MIR<7:0>

JIT

ICS=1,LC<==MIR<7:0>

JNBF

If NB=0,LC<--MIR<7:0>

JNBT

NB=1,LC<--MIR<7:0>

JZF

2=0,LC<--MIR<7:0>

JZT

2=1,LC<--MIR<7:0>

JCF

C=0,LC<--MIR<7:0>

JCT

C=1,LC<~-MIR<7:0>

JVF

V=0,LC<~-MIR<7:0>

JVT

V=1,LC<--MIR<7:0>

JNF

JNT

If N=1,LC<--MIR<7:0>

Ra<--Ra+LITERAL

Ra-LITERAL

Ra<--Ra&LITERAL

CYCLES

If N=0,LC<--MIR<7:0>

INSTRUCTION

SUMMARY

NMEMONIC

OPERATION

CYCLES

Ra&LITERAL

Ra<--LITERAL

RESET

SET

CCF

Ra<--FLAGS

LCF

FLAGS<--Ra

RTSR

TSR<--0

LGL

G<--Ra<2:0>

CIB

Ra<--Ra+l

CDB

Ra<=--Ra-1

80/81

MB /MBF

Ra<--Rb

82/83

MW /MWF

Ra<--Rb

84/85

CMB/CMBF

C=1,Ra<--Rb

86/87

CMW/CMWF

C=1,Ra<--Rb

88/89

SLBC /SLBCF

Ra<=-2Rb+C

8A/8B

SLWC /SLWCF

Ra<--2Rb+C

8C/8D

SLB/SLBF

Ra<--2Rb

8E/8F

SLW/SLWF

Ra<-=-2Rb

90,91

ICB1/ICB1F

Ra<--Rb+l

92/93

ICW1/ICWLF

Ra<--Rb+1

94/95

ICB2/ICB2F

Ra<--Rb+2

96,/97

ICW2/ICW2F

Ra<--Rb+2

98,/99

TCB/TCBF

Ra<--Rb

9A/9B

TCW/TCWF

Ra<--Rb

9C/9D

OCB/OCBF

Ra<--Rb

INTERRUPTS

INSTRUCTION

SUMMARY

CYCLES

9E /9F

OCW/OCWF

Ra<--Rb

AO0/Al

AB/ABF

Ra<--Ra+Rb

1»

A2/A3

AW/AWF

Ra<-—-Ra+Rb

A4/A5

CAB/CABF

C=1,Ra<--Ra+Rb

*).C

A6/A7

CAW/CAWF

If C=1,Ra<--Ra+Rb

*).C

A8 /A9

ABC/ABCF

Ra<--Ra+Rb+C

AA/AB

AWC/AWCF

Ra<--Ra+Rb+C

CAD

(Ra<--Ra+Rb)<3:0>
(Ra<=-Ra+Rb)<7:4>

ICS=1,Ra<--Ra+Rb

AE /AF

CAWI/CAWIF

BO/B1

SB/SBF

Ra<--Ra-Rb

B2/B3

SW/SWF

Ra<--Ra=-Rb

B4/B5

CB/CBF

Ra-Rb

B6/B7

CW/CWF

Ra-Rb

B8/B9

SBC/SBCF

Ra<-~=Ra-Rb-C

BA/BB

SWC/SWCF

Ra<--Ra-Rb-C

BC/BD

DB1/DB1F

Ra<--Rb-1

BE /BF

DW1/DW1F

Ra<-=-Rb-1

co/cl

NB/NBF

Ra<——RaRb

c2/C3

NW/NWF

Ra<¥éRaRb

C4/C5

TB/TBF

Ra<--Rb

C6/C7

TW/TWF

Ra<--Rb

C8/C9

ORB /ORBF

Ra<--Ra!Rb

CA/CB

ORW/ORWF

Ra<--Ra!Rb

CC/CD

XB/XBF

Ra<--Ra!Rb

CE/CF

XW/XWF

Ra<--Ra!Rb

OPERATION

NMEMONIC

opP

INSTRUCTIO N

SUMMARY

opP

NMEMONIC

OPERATION

D0/D1

NCB/NCBF

Ra<--Ra+"Rb

D2/D3

NCW/NCWF

Ra<--Ra+"Rb

D8/D9

SRBC/SRBCF

DA /DB

CYCLES

Ra<--C:Rb/2

SRWC/SRWCF

Ra<--C:Rb/2

DC/DD

SRB /SRBF

Ra<--Rb/2

DE /DF

SRW/SRWF

Ra<--Rb/2

EO/E1

IB/I1BF

Ra<--DAL

E2/E3

IW/IWF

Ra<--DAL

E4/E5

ISB/ISBF

Ra<--DAL

E6/E7

ISW/ISWF

Ra<--DAL

EC/

MIB!Rb:Ra

LTR

TR<--Rb:Ra

G<--(Rb)8:
(Ra) 7-6

RIB1

M<~--Rb:Ra

Ra<--Ra+l

WIB1

M<--Rb:Ra

Ra<--Ra+l

RIWl

M<--Rb:Ra

Ra<--Ra+l

WIwl

M<--Rb:Ra

Ra<--Ra+l

RIB2

M<{~-=-Rb:Ra

Ra<--Ra+2

WIB2

M<--Rb:Ra

Ra<--Ra+2

Fo6

RIW2

M<--Rb:Ra

Ra<--Ra+2

WIWZ2

M<--Rb:Ra Ra<--Ra+2

M<-=-Rb:Ra

M<--Rb:Ra

Oow

M<--Rb:Ra

INSTRUCTION

SUMMARY

NMEMONIC

OPERATION

CYCLES

M<--Rb:Ra

- - - -

NOP

:
NOTE

does

fect
NOTE:

When two op codes refer to a specific mnemonic
not
affect the condition codes whereas the odd
the condition codes.
M

refers

the

LSI-11l

Bus.

the even op code
op code does af-

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LSI-11 WCS

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