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EK-KT11D-OP-001
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KT11-D Memory Management Option User's Manual
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EK-KT11D-OP
Revision:
001
Pages:
42
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KT11-D memory management option user's manual dlilgliltiall ; EK-KT11D-OP-001 KT11-D | pal—— memory management option | user’'s manual digital equipment corporation - maynard, massachusetts I1st Edition, September 1976 Copyright © 1976 by Digital Equipment Corporation - The material in this manual is for informational purposes and is subject to change without notice. Digital Equipment Corporation assumes no respon- sibility for any errors which may appear in this manual. | | Printed in U.S\A. The folldwing are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: | DECtape DECCOMM DEC DECUS DECsystem-10 DIGITAL DECSYSTEM-20 MASSBUS PDP RSTS @ TYPESET-8 TYPESET-11 UNIBUS CONTENTS Page CHAPTER 1 GENERAL DESCRIPTION 1.1 PURPOSE ANDUSEOFKTI11I-DOPTION 1-1 1-1 1-1 1-1 1-2 1.3 Memory Management . . . . . . . ... Lo KT11-D MEMORY MANAGEMENT UNIT SPECIFICATIONS ............... e e e e e e e e e e REFERENCE LITERATURE . . . . . . 1-2 1-2 1-3 CHAPTER 2 INSTALLATION INFORMATION CHAPTER 3 OPERATION AND PROGRAMMING 1.1.2 1.1.3 .14 1.1.5 1.1.6 1.2 g . . .. ... ... . ... ... e e e e 0o oo e Memory Expansion . . . . .. ... e e e e e e . .« v v v e e e e e Virtual Address Space oo .. .. .. . . Minimal Memory Fragmentation . . . .. e Memory Protection . . . . . . . L e 1.1.1 3.1 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.3.3 334 3.4 3.4.1 34.2 3.4.3 344 3.5 3.5.1 3.5.2 3.5.2.1 3.52.2 3.5.2.3 3.5.2.4 3.5.3 3.54 3.6 3.6.1 3.6.1.1 3.6.1.2 3.6.1.3 3.6.14 3.6.1.5 3.6.1.6 3.6.1.7 3.6.2 3.7 Operating Mode Control e e e e e e[ . . . . .. . ... e -2 MEMORY MANAGEMENT SYSTEM INTRODUCTION . . . ... ... ......... e e e e e i e e e e e e e e e e ... MEMORY RELOCATION . . . . . . e e e e e e e e e e e e e e e e e e e Program Relocation . . . . . .. e e . . . . . . . ... oo e Extended Memory Addressing e e e e e e s e e e MEMORY MANAGEMENT . . . . . . 31 3-1 3-1 3-3 3-3 . . . . . . ... .. oo Dynamic Memory Allocations Memory Management Statistics . . . . . .. ... o000 oL e e e e e e e oo oo Memory Management Instructions . . .-. . . ... o Lo oo e e e e e e MEMORY PROTECTION . . ... ... ... ......... e e e e e e e e i e Inaccessible MEMOIY . . . . .« e e e e e e e e e e e Read-Only Memory . . . . . . o v v i i e i 34 3-5 3-5 3-8 39 3-9 Program Relocation . . . . . . . . . 34 o oL Multiple Address SPace . . « « v v v v e e e e e e e e e 39 oo oo e e e e e e e e 39 Mode Description . . .. . . . oo e e e e e e 3-11 . . . . . . REGISTERS PAR/PDR . . . . . .. ..o Cee .. 312 Page Address Registers (PAR) oo oo 3-12 Page Descriptor Registers (PDR) . . . . . .. . ... e e 3-12 i i Access Confrol Field (ACF) . . . . . . . . . Expansion Direction (ED) . . . . . . . . . ..o oo 3-13 e 3-15 e e e e e e e e e e e e e e Written Into (W) . . . . .. e e e 3-15 . . . ... ... ... ... e Page Length Field (PLF) PLF for an Upward Expandable Page . . . .. .. ... ... ... ... ....... 3-15 PLF for a Downward Expandable Page . . . . ... ... ... ... ... ..... 3-15 'MEMORY MANAGEMENT STATUS REGISTERS . . ... ................ 3-16 Status Register 0 (SRO) . . . . . . . o o o i i . 3-16 e e e e e e e e e e e 3-16 . . . . . . . o o o Abort-Nonresident Abort —Page Length . . . . . . . . .. oo 3-16 e e e e e 3-16 . . . . . . ... oo e Abort-Read Only oo e 3-17 Maintenance/Destination Mode . . . . . . . . ... . . . . . . . . . . 0 e 3-17 Mode of Operation . . . . . . . . . e 3-17 Page Number e e S 3-17 Enable KT11-D . ........... e Status Register 2 (SR2) . . . . . . . o o o e 3-17 . . ... ... ... ... ... 3-17 DETERMINING THE PROGRAM PHYSICAL ADDRESS iii ILLUSTRATIONS Title Figure No. Page 2-1 KD11-A Wiring Change No.1 . . . ... ... .. .. ...... R 2-2 2-2 KD11-AWiring Change No. 2 . . . . . . ... i e 2-2 2-3 KD11-A Wiring Change No.3 . . . . .. ... ... .. ..... e 2-3 24 KD11-A Wiring Change No.4 . . . . . . . . . . . . e 2-3 2-5 KD11-A Wiring Change No.5 . . . . . . . . . e 2-3 2-6 KD11-A Wiring Changes No. 6 and No.7 2-7 KT-3 Fault H Hook In KD11-A . 0 i i i e e e e e e e e e e e 24 . . . . . . . . e e 2-5 LHook InKDI11-A . . ... ... e e e 2-8 KT-7 KTINSTR 2-9 KT-2 PS15(0O)HHook In KD11-A . . . . . . . . . . . . . . . . . . .. ... ..... e e e e . i i e e 2-10 KT-2 PS15(0)L Hook InKD11-A 2-11 KT-6 No MSYN L Hook in KD11-A e e e e e e e e e e e 2-12 KT-2INHPSCLK 2 2-13 KT-9 MFP SMOL Hook In KD11-A 2-14 Console MM Enable Hooks in KD11-A 3-1 Simplified Memory Relocation Example 32 Relocation of a 32K Word Program Into 124K Word Physical Memory . . . . . . . .. .. .. LHookinKDI1-A e e . e s e e 2-5 e 2-6 e e 2-6 .. 2-7 . .. ... ... ... ... ... .. . ...... 2-7 . . . . . . . . . . . . . . .. e e e e i s e, 2-8 PP 2-8 e . . . . ... ... .. ... ... ... ...... 3-3 ... .. .. . .. .. 34 3-3 Construction of an 18-Bit Physical Address 34 KT11-D Memory Management Unit Active Page Registers 3-5 Page Address Register (PAR) 3-6 Page Descriptor Register (PDR) Format 3-7 Example of an Upward Expandable Page . . . . . . . . ... ... ... .. ....... 3-13 . . . . .. ... ... ... ... ........ 3-14 Format . . . . . . . . . . . . 3-2 . . . . . .. .. .. . . . . . e e e e e e e e . 3-10 . . . . . . ... . ... .. ... .. ... ..... 3-11 . . . ... ... ... e 3-8 Example of a Downward Expandable Page 3-9 Format of Status Register O(SRO) . . .. ... ... ... .. e 3-10 Format of Status Register 2(SR2) . . . . . . . . . . . . e e e e 3-12 e e e e e 3-16 o e 3-17 TABLES Title Table No. 1-1 Abridged Specifications Summary 3-1 PAR/PDR Address ASSignments 3-2 Access Control Field Keys 3-3 Relating Virtual Addressto PAR/PDR Set Page . . . . . . ... Lo o 1-2 . . . . . . . . v it v v e e e e e e e e e e e e 3-11 . . . . . . . . . . . . 0 @ iv e e L 3-12 . . . . .. .. ... ... ... .... e 3-17 INTRODUCTION This manual describes the KT11-D Memory Management Unit, which is a hardware option available for use with the M e PDP-11 Programmed Data Processor. The purpose of this manual is to: 1. Provide an overall understanding of how the KT11-D functions in a PDP-11 system. 2. Explain how the KT11-D hardware can be used in the development of the memory management module of a software operating system. 3. | Describe the KT11-D logic in sufficient detail to enable maintenance personnel to perform on-site troubleshooting and repair. The KT11-D interacts with the KD11-A Central Processor Unit and operating system software to achieve PDP-11 system management objectives. The use of the KJ11 Stack Limit option is also utilized for expanded kernel stacking flexibility. For this reason, a background description of memory management system objectives and programming information is included in this manual. Chapter 1 introduces the purpose and use of the memory management unit. Chapter 2 references the installation procedures provided in the PDP-11/40, PDP-I 1/35 System Manual (21 Inch Chassis). There are KT11-D wiring change procedures provided in this manual. Chapter 3 contains operation and programming reference information. It describes the internal registers and their application from a software viewpoint. Programming details, hints, and exceptions of interest to programmers are included. Detailed descriptions of the processor, console, Unibus, and memory logic that interface with the memory management unit are provided in the following related documents. 4\\ N PDP-11/40, PDP-11/35 System Manual (21 Inch Chassis) KD11-A Processor Maintenance Manual EK-11040-TM-002 EK-KD11A-MM-001 CHAPTER 1 GENERAL DESCRIPTION 1.1 PURPOSE AND USE OF KT11-D OPTION The KT11-D Memory Management Unit is a PDP-11 hardware option that: a. Expands the basic 32K-word address capability of the KD11-A to 128K words. b. Provides a “virtual” address space with memory relocation and protection for multi-user timesharing systems. | c. Implements the separate address spaces for the PDP-11 Kernel, and User modes of operation. d. Provides memory management information for use of memory in multi-user, multi-program systems. These features are briefly reviewed in thevfollowing paragraphs. The essential details required to thoroughly understand the memory management option from the PDP-11 system programmer’s viewpoint are presented in Chapter 3, Operation and Programming. 1.1.1 Memory Expansion The KT11-D option extends the basic PDP-11 physical address capability to 128K words. The 16-bit word length of the KD11 limits the memory address capability of the basic PDP-11 to 32K words. (The least significant address bit is used for byte addressing.) The upper 4K of the address space is always reserved for internal register and external device addresses. Therefore, the total memory address capability is extended from 28K to 124K words. This is accomplished by converting the 16-bit virtual address generated by the processor to an 18-bit physical address. Several sets of relocation registers are the key to this feature. A complete description of how the active page address registers (PAR) are used to construct the physical address is provided in Paragraph 3.2.2. 1.1.2 Virtual Address Space Because the KT11-D relocates, if enabled, all addresses automatically, the KD11-A may be considered to be operating in a virtual address space. This means that no matter where a program is loaded into physical memory, it will not have to be “re-linked”; it always appears to be at the same virtual location in memory. 1.1.3 Minimal Memory Fragmentation The virtual address space is divided into eight separate 4K-word pages. Each page is relocated separately. This is a useful feature in multi-programmed timesharing systems. It permits a new large program to be loaded into discontinuous blocks of physical memory. In addition, the KT11-D provides a means of allocating a page as small as 32 words, so that short procedures or data arcas need occupy only as much memory as required. This is a useful feature in real-time control systems that contain many separate small tasks. It is also a useful feature for stack and buffer control. 1-1 1.1.4 Memory Protection Each virtual page has a separate protection key associated with it. There are three possible basic protection levels. These are listed, in order of increasing protection, as follows: 1. All read or write accesses allowed. 2. Only read accesses allowed. 3. No access allowed. | Any attempt to violate any of these forms of protection is prevented by the KT11-D hardware. For example, an illegal “read” attempt (attempting to read from a page that is protection keyed for no access) does not result in obtaining the contents of the location. An illegal “write” attempt does not result in the modification of the contents of the location. All such illegal access attempts cause an immediate trap (called an “abort”) to the Kernel space. The KT11-D hardware records and preserves abort status information so that the offending user can be notified of the violation. It is not generally possible to recover from these aborts. 1.1.5 Operating Mode Control In a multi-programmed, timeshared system, user programs must be prevented from modifying or destroying the operating system and each other. The KT11-D implements the Kernel/User modes of PDP-11 operation upon which the timeshared system is based. A page address register/page descriptor register (PAR/PDR) set is provided for each mode of operation. The KT11-D analyzes every memory reference, based on the processor status word, to enable the correct PAR/PDR set. Thus, a User mode program, for example, is prevented from operating in space assigned to Kernel programs. | Compilers, utility programs, and other shared source programs, might be assigned to User mode address space, with access codes keyed to permit read-only access. 1.1.6 Memory Management In a multi-program, multi-user environment, memory space must be used in the most efficient way, to accommodate as many users as possible with minimum delay. The KT11-D logic maintains a bit which indicates whether the associated page has ever been written into. The software memory management system can interrogate each PDR to determine whether or not that page has been used. If a current active page has been written into, the memory management operating system needs to be informed, so that the modified program can be rewritten into secondary storage before that page is overlayed. 1.2 KT11-D MEMORY MANAGEMENT UNIT SPECIFICATIONS A summary of specifications and technical characteristics for the KT11-D Memory Management Unit option is listed in Table 1-1. Table 1-1 Abridged Specifications Summary Characteristic , | Memory Expansion ~ Interface Delay | Specification or Description Expands PDP-11 memory address capability up to 124K words. Address line outputs compatible with PDP-11 Unibus. | Adds 150 ns to every :fnemory reference. 1-2 Table 1-1 (Cont) Abridged Specifications Summary - Specification or Description Characteristic ~ Modes of Operation Implements the KD11 Central Processor Kernel, and User modes. Available Pages Provides eight pages for each mode. Page Length A page can vary in length from one 32-word block up to 128 32-word blocks, in 32-word | increments. Maximum page length is therefore 4096 words. Program capacity Physical description Eight 4096-word pages will accommodate a 32K-word program. | Option consists of one standard hex module (15 x 8.5 in.) that mounts in PDP-11/40 CPU backplane assembly. Module M7236 Located in slot 8 rows A through F. Environmental Refer to overall PDP-11/40 specifications listed in system manual, EK-11040-TM-002 1.3 REFERENCE LITERATURE The following list of references covers some of the more general aspects of “memory management” tasks of interest to systems programmers. It is part of the recommended blbhography of the National Academy of Engineering for its course outline on “Operating System Principles”. « The following abbreviations are used in the bibliography: ACM Association for Computing Machinery IEEE Institute for Electrical and Electronics Engineers IEEETC IEEE Transactions on Computers CACM Communications of the ACM JACM Journal of the ACM CS Computing Surveys (ACM) FJCC Fall Joint Computer Conference SJCC Spring Joint Computer Conference 2SOSP Second Symposium on Operating Systems Principles (proceedings available from ACM, 1133 Avenue of the Americas, New York, N.Y. 10036. Abate, J., and Dubner, H. Optimizing the Performance of a Drum-Like Storage. IEEE Trans. C-18, 11 (Nov. 1969), 992-997. J/ Belady, L.A. A Study of Replacement Algorithms for Virtual Storage Computers. IBM Sys. J. 5,2 (1966), 78-101. 1-3 Bensoussan, A., Clingen, C.T., and Daley, R.C. The Multics Virtual Memory. Proc. 2SOSP (Oct. 1969). ‘Denning, P.J. The Working Set Model for Program Behavzor Comm. ACM 11,5 (May 1968), 323-333. Denning, P.J. Thrashing: Its Causes and Prevention. AFIPS Conf. Proc. 33 (1968 FICC), 915-922. Dennis, J.B. Segmentation and the Deszgn of Multzprogrammed Computer Systems JACM 12, 4 (Oct. 1965), 589-602. Kilburn, T. et al. One-Level Storage System. IRE Trans. EC-11, 2 (Apr. 1962), 223-235. Knuth, D.E. The Art of Computer Programming (Vol. 1). Addison-Wesley (1969), Ch.2. Mattson, R.L., Gecsei, J., Slutz, D.R. and Traiger, I.L. Evaluatzon Techmques for Storage Hierarchies. IBM Sys. J. 9, 2 (1970), 78- 117 Randell, B., and Keuhner, C.J. Dynamic Storage Allocation Systems. Comm. ACM11, 5 (May 1968), 297-305. Sayre, D. Is Automatic Folding of Programs Efficient Enough to Displace Manual? CACM 12, 12 (Dec. 1969), 656-660. Wilkes, M.V. Slave Memories and Dynamic Storage Allocation. IEEE Trans. EC-14 (Apr. 1965), 270-271. Wilkes, M.V. Time-Sharing Computer Systems. Am. Elsevier (1969). 1-4 CHAPTER 2 INSTALLATION INFORMATION The installation procedure for the KT11-D Memory Management Unit option is included as part of the complete PDP-11 system installation procedure described in Chapter 2 of the PDP-11/40, PDP-11/35 System Manual (21 Inch Chassis). Specific procedures for wiring changes to the Processor are given below with descriptions of hook operations that require no wiring changes. When the KT11-D is included as part of the initial PDP-11 system, the M7236 module is installed prior to shipment. If the KT11-D option is being added to an existing PDP-11 system, the installation procedure is straightforward. The M7236 module is installed in slot 8, rows A-F of the CPU backplane assembly. The wiring modifications to the KD11-A Processor that are necessary are as follows: Refer to Processor Block Schematic K1-6, location A-6, and move jumper W10.to the ground inputs of the 8881 gates. This change disables the KD11-A from giving an address to the Unibus (Figure 2-1). Refer to Processor Block Schematic K1-8, location C/D-8, and remove jumpers W5, W6, and W9. This change enables the correct selection of User and Kernel stacks in either explicit or implicit operations (Figure 2-2). Refer to Processor Block Schematic K1-7, location C/D 3, and remove jumpers Wl W2, W3, and W4... This change enables the KT11-D to use an 18-bit virtual address to decode all internal reglster addressing (Figure 2-3). | Refer to Processor Block Schematic K4-4, location C-5. Remove jumper W2 and connect jumper W2A. This change connects pins 10, 11, and 12 of 74H55 module at location E-6 to AO7H2 (KT-3 FAULT H). This change enables the KT11-D to start a trap sequence for a KT Abort condition (Figure 2-4). Refer to Processor Block Schematic K1 -9, location D-5. Remove jumpers W7 and W8. This change disables automatic operation of console address hghts BA (17: 16) on assertion of K1-6 BA (17:16) from 2-5). the Processor (Figure Refer to Processor Block Schematic K4-4, location C4. Add capacitor C113(680 mmf 100 WVDCQC) DEC Part Number 10-00026. This change extends the CLK MSYN H delay from 150 ns to 300 ns to enable memory management logic to propagate a new address to the Unibus while retaining bus specifications (Figure 2-6). Refer to Processor Block Schematic K4-4, location D-4. Add capa01tor C114 (560 mmf, 100 WVDC) DEC Part Number 10-00025. This change increases the delay of fast MSYNin the Processor from 75 ns to 225 ns (Figure 2- 6) | When the KT11-D Memory Management Option is added to an existing PDP-11 system, the KJ11-A Stack Limit Register Option must also be added. 2-1 o +— P BAMUX REG < 8881 BUS Ai7 L 8881 BUS AO6 L A a— <« MOVE WIO TO HERE | W10 WAS HERE —» | ! ' i K4-5 BUS FM BA H DATA PATHS Y172 BA <15:00 > : | Ki-6 11-1400 bea Figure 2-1 KD11-A Wiring Change No. 1 | —O-- = WS WAS HERE. REMOVE. KT-2 MODE SEL1 H KT-4 RIFO(O) H , - 74H60 l__ WAS HERE. REMOVE. KT-9 S HOOK H Ki-6 BAO3 (1) H K2-4 RIF3(1)H KT-9 D HOOK H W6 WAS HERE. REMOVE. K2-4 SRD({)H = ] i ? | <« D K2-4 k2-4 RIF2(1)H RIF1(1)H | T4H53 IO --—-0— W9 —E__ X Ki8 RADRS3 L - . ————— | K2-4 SRI(1)H DATA PATHS ' m ‘7’2%\ REG <15:00> <15:00> K2-4 SRBA(1)H Ki-8 K2-4 SRS(1)H Figure 2-2 KD11-A Wiring Change No. 2 2-2 i1-1401 Y 7Y {bdd LA — 3 ~--@—— Ki-7 PS ADRS H 8815 \__! W1 WAS HERE. ©—— Ki-7 SLR ADRSH «— D 8815 Wi bdbd BA <15:00> < ! | I W2 WAS HERE. REMOVE. --<-©—— Ki-7 REG ADRS H 8815 \_ | #3 was HERE. REMOVE, --5s-@—— K1-7 SR ADRS H 8815 [4 REMOVE, \_{ W4 WAS HERE. <— ( REMOVE. DATA PATHS DECODING Ki-7 11-1402 M2 +— O Figure 2-3 KD11-A Wiring Change No. 3 K4-4 OVFLW ERR L K4-4 ODA ERRL K4-4 CKODA(1)H m K1-7 BAOO(1)H K5-6 CONSL (1)L K4-4 BUS STOP H KT-3 FAULT H o C MOVE W2 TO HERE —» i \ - TIMING we WAS HERE | BUS DATA CNTL K4-4 m T} 3 '»7;.4 ' 11-1402 ) Figure 24 KD11-A Wiring Change No. 4 5 W7 WAS HERE. REMOVE. Ki-6 BA <17%16>H I I__ 8881 . I, Q o+ Ki1-9 BA<ITx16>L Q——D o8 | W8 WAS HERE. REMOVE. ~ DATA PATHS CONSOLE & MATCH K1-9 m7 2.‘5’ Figure 2-5 KD11-A Wiring Change No. 5 2-3 11-1404 - 4 R5 K | R6 a7 | ‘ 7aH11 2222908 k4 a4 ¢lK MSYNA H . ADD L. c114 T~ <—D _1_ | 4 C107=560mmf 100 VDC S +5V = R3 1K | R4 _ar | - ' 7an1 }-2230008 1 4 oLk MSYN H o | ADD _|_ \ Cl13 T~ T | N ) C106=660mmf 100 VDC 1-1434 Figure 2-6 KD11-A Wiring Changes No. 6 and No. 7 The wiring modifications to the KD11-A Processor that are necessary for the KJ11-A are as follows: a. Refer to Processor Block Schematic K4-4. Move jumper W1 on the M7234 in accordance with the notes on the drawing. This change permits the KJ11-A to create a stack overflow. - b. Refer to Processor Block Schematic K54. Move jumper W1 on the M7235 in accordance with the notes on the drawing. This change allows the stack overflow flip-flop to be set. Once installed, the KT11-D option is ready to be checked out, using the diagnostic programs supplied with the option. Other hooks, that do not include w1r1ng changes but do represent 31gnals sent from the KT11-D to the KDll -A to modify its Operatlon with the Memory Management Option, include the following functions; a. As shown on Processor Drawing K3-2, location B-3, and in Figure 2-7, as a result of KT-3 FAULT H starting a Trap Sequence, KT-3 FAULT L going to FOSM?2 forces a jam to the correct flow path in the Trap Sequence on a UBF 10. b. Asshown on Processor Drawing K3-5, location C-4, and in Figure 2-83, on a detection of an instruction unique to memory management, the KT11-D signals the KD11-A to recycle in the fetch flow to decode the new instruction. c. As shown on Processor Drawing K3-6, location C-3 and in Flgure 2-9, KT-2 PS15(0)H indicates User mode. This signal controls the restricted use ofa reset in User mode and the KT11-D creates the KT INSTR L signal to recycle the Reset Instruction as a NOP Instruction. d. As shown on Processor Drawing K4-4, location D-6 and in Figure 2-10, KT-2 PS15(0)H (when LOW) is used to disable stack overflow detection in User mode. ) J N . As shown on Processor Drawing K4-4, location D-3 and in Figure 2-11, KT-6 NO MSYN L is created by the KT11-D on an internal access and will disable BUS MSYN to the Bus As shown on Processor Drawing K5-2, location C-6 and in Figure 2-12, KT-2 INH PS CLK L disables the clocking of CLK PS (07:T) in User mode. As shown on Processor Drawing K5-5, location B-2 and in Figure 2-13, the signal KT-9 MFP SMO L is a signal that chooses the correct destination stack address on a MFP R6 instruction. As shown on Processor Drawing K5-7, location C-3 and in Figure 2-14, the signal KT-9 RELOCATE ENB L enables the VIRTUAL lamp on the Console. KT-9 PS15 L is used to enable the USER lamp on the Console. Signals KT-9 SR16 L and KT-9 SR17 L are used to enable the BA 16 and BA 17 lamps on the Console. 3 ! +5V e’ 21K J) K2-5 UBF4(1)H sSTB 74150 DO9S KT-3 FAULT L f K3-2 BUBCO (BUT 17:00) L Y _ N , n SO S1 K2-5 UBFO({1)H K2-5 UBF2 ({1)H ’ <«— B - S2 S3 J BUT MUX : K3-2 K2-5 UBF3 (1)H 11-1405 Figure 2-7 KT3 Fault H Hook In KD11-A K3-5 BUBC3(BUT 37) H K3-5 I1K3 L KT-7 KT IR DECODE INSTR L -—C BUBC (INSTR 1) K3-5 11-1406 KT INSTR L Hook In KD11-A Figure 2-8 KT-7 2-5 e 3 KT-2 R4 AMN— +5V PS15(0)H K3-6 IR (15:03)=0H " — 74H10 K3-6 RESET L 74HO4 +«—C - K3-6 RESET H K3-4 IR(02:00)=5”L — , —— 74H10 74HO0O K3-6 HALT+ RESET L _ K3-4 IR(02:00)=0L ‘IR DECODE IRD DISCRETE K3-6 11-1407 N < + KT-2 PS15(0)H (&) KT-2 PS15(0)H Hook In KD11-A <t N Figure 2-9 K4-4 NO DATI H ———— 7T4H11 K4-4 CKOVF H «—— D C}__ CKOVF 7474 O— TIMING BUS DATA CNTL K4-4 f1-1408 KT-2 PS15(0)L Hook In KD11-A \\H-M' Figure 2-10 2-6 AA | 1 —{p K4 -4 BUS STOP H +5V A \ A A4 AAA o A~ +5V - o— 8815 MSYNA L C K4-4 P CLR MSYN L . ? ) | 1 K4-4 CLK MSYN H { D ' e—D 00— 8815 K4-4 B MSYN L B MsYN 74HT4 o —c hi “ o) T T4H74 K4-4 CLK MSYNA H - K4-4 MSYNA L C[) TIMING BUS DATA CNTL KT-6 NO MSYN L K4-4 11-1409 o Figure 2-11 KT-6 No MSYN L Hook in KD11-A +5V R24 KE-5 INH PS CLK 1L R23 | - | AAA- ANA—— KT-2 INH PS CLK 2 L K4-2 PS(P{+P3) H — H 1) K2-6 SP2( K2-6 SP1(1) H —— K2-6 SPO(1)H — c ~ 74H11 | K5-2 CLK PSKO7:T> L / » K5-2 SPS (02:00)=7 H STATUS PS (07:00) K5-2 11-1410 Figure 2-12 KT-2 INHPS CLK 2 L Hook in KD11-A 2-7 (SBC=13) 2 (SBC=12) ———— | l +5V KT-9 MFP SMO L K2-6 SBC3 H — K2-6 ‘ SBC2 H ' o 74H53 K5-5 BCO! H | K2-6 SBCO H K2-6 SBC1 H 74HOR <—B @ STATUS CONSTANTS K5-5 Figure 2-13 KT-9 RELOCATE ENB L 0— KT-9 PS15 L KT-9 KT SR16 KT-9 KT SR17 L =141l KT-9 MFP SMOL Hook In KD11-A > L - — K5-7 VIRTUAL L — K5-7 USER L & K5-7 KT BA16 L — K5-7 KT BAIT L NN o PP +5V MF D 6.8 [ ) 0O o —s ’ STATUS B CABLES e KS-7 1-1442 Figure 2-14 Console MM Enable Hooks In KD11-A 2-8 CHAPTER 3 OPERATION AND PROGRAMMING 3.1 MEMORY MANAGEMENT SYSTEM INTRODUCTION t system. The purpose of this chapter is to describe the capabilities and objectives of the PDP-11 memory managemen functions in The operating characteristics of the KT11-D Memory Management Unit, which performs the hardware the paging system, are described from the system programmer’s viewpoint. Suggested techniques that are included in this chapter are presented only for the purpose of illustrating hardware operating characteristics and as examples of how system programmers can use the KT11-D in developing an operating system. This information is also presented to provide a better understanding of the hardware for maintenance purposes. NOTE The information in this chapter does not describe the DEC Operating System for the PDP-11. In the following paragraphs, the general features of the KT11-D Memory Management Unit are introduced, beginning with the basic memory relocation and extended memory addressing capability. Next, some of the general requirements of a memory management system are described, along with illustrations of how the KT11-D hardware can be used to implement such a system. Following that, the overall memory protection requirements and corresponding facilities provided by the KT11-D are described. The system programmer has the option of using any or all of the KT11-D memory management capabilities, depending upon whether simple relocation into extended memory is required or complex dynamic memory allocation systems are required. 3.2 MEMORY RELOCATION A basic KT11-D function is to perform memory relocation and provide extended memory addressing capability for systems with more than 28K of physical memory. The KT11-D uses two sets of page address registers to relocate virtual addresses to physical addresses in memory. These sets are used as hardware relocation registers that permit several user’s programs, each starting at virtual address O, to simultaneously reside in physical memory. 3.2.1 Program Relocation The page address registers are used to determine the starting address of each relocated program in physical memory. Figure 3-1 shows a simplified example of the relocation concept. A more detailed example of how memory relocation works is shown in Figure 3-3. In Figure 3-1, Program A starting address O is relocated by a constant to provide physical address 64005. 3-1 PROCESSOR | VIRTUAL ADDRESS (VA)=0 | ~— KD11 KT11-D OPTION "RELOCATION CONSTANT A=0064 B=1000 PHYSICAL MEMORY WN ’\/\W PROGRAM B 100000 e e — N PROGRAM A PHYSICAL ADDRESS 006400 B e b ] —— T — 000000 11-1397 Figure 3-1 Simplified Memory Relocation Example If the next processor virtual address is 2, the relocation constant will then cause physical address 64024, which is the second item of Program A, to be accessed. When Program B is running, the relocation constant is changed to 100000g. Then, Program B virtual addresses starting at O, are relocated to access physical addresses starting at 100000g. Using the active page address registers to provide relocation eliminates the need to “re-link” a program each time it is loaded into a different physical memory location. The program always appears to start at the same address. | | In the PDP-11 systems, a program is relocated in pages. A page can consist of from 1 to 128 blocks. Each block is 32 words in length. Thus, the maximum length of a page is 4096 (128 x 32) words. Using all of the eight available active page registers in a set, a maximum program length of 32,768 words can be accommodated. Each of the eight pages can be relocated anywhere in the physical memory, as long as each relocated page begins on a boundary that is a multiple of 32 words. However, for pages that are smaller than 4K words, only the memory actually allocated to the page may be accessed. The relocation example shown in Figure 3-2 illustrates several points about memory relocation. These points are: 1. Although the program appears to be in c‘ontigu'ous address space to the processor, the 32K-word virtual address space is actually scattered through several separate areas of physical memory. As long as the total available physical memory space is adequate, a program can be loaded. The physical memory space need not be contiguous. 2. Pages may be relocated to higher or lower physical addresses,'with respect to their virtual address ranges. In the example of Figure 3-2, page 1 is relocated to a higher range of physical addresses, page 4 is relocated to a lower range, and page 3 is not relocated at all (even though its relocation constant is non-zero). 3. All of the pages shown in the example start on 32-word boundaries. 3-2 i 4. Each page is relocated independently. There is no reason why two or more pages could not be relocated to the same physical memory space. Using more than one page address register in the set to access the same space would be one way of providing different memory access rights to the same data, depending upon which part of a program was referencing that data. Further information about memory protection is provided in Paragraph 3.4. In the example shown in Figure 3-2,note the relocation constant assigned to pages 4 and 6. As a result, virtual addresses within both address ranges access the same physical addresses in memory, using separate page address registers. - PROCESSOR KT11-D VIRTUAL ADDRESS RANGES PAGE |RELOCATION NO. | CONSTANT 160000-177776 | 7 | 1500xX PHYSICAL MEMORY SPACE 400000 - 417776 140000- 157776 6 | 0200xx 320000 - 120000- 137776 5 | 1000XX 250000 : 100000 - 117776 4 0200XX 150000 167776 ) 060000 - 077776 3 | 0600XX 100000 117776 | | 337776 267776 040000 - 057776 2 | 2500XX 060000 077776 020000- 037776 1 3200 XX 020000 037776 000000- 017776 0 | 4000xx 11-13398 Figure 3-2 Relocation of a 32K Word Program Into 124K Word Physical Memory NOTE - ~ Where xx is the address within the block number given by the PAR 3.2.2 Extended Memory Addressing When the KT11-D Memory Management Unit option is added to the PDP-11 system, the 16-bit KD11 address output is no longer interpreted as the direct physical address of a device or a memory location. Instead, it is considered as a 16-bit virtual address that contains information to be used by the KT11-D to construct an 18-bit physical address. Refer to Figure 3-3 which shows how the 18-bit physical address is constructured. Virtual address bits VA (15:13) are interpreted as an active page field (APF) to select one of eight active page registers in a set. Virtual address bits (12:06) provide the block number (0 to 127, ) within the page. VA (05:00) indicate the displacement within each 32-word block. The PAR contains a page address field (PAF) that is written into the PAR under program control at the time the complete PAR/PDR set is defined for a program page. Consider the PAF as the base address of the page. The block number, VA (12:06) is added to the base address PAF (11:00) to provide the 12 most significant bits of the physical address. This, plus virtual address bits VA (05:00) (unchanged by relocation), forms the 18-bit physical address. 3.3 MEMORY MANAGEMENT The following paragraphs describe some of the memory management tasks that might be required of an operating system. The KT11-D hardware features aid the system software in the performance of these tasks. 3.3 1312 EXAMPLE:5460¢g BASE PAGE 1 01 1 , | | | 00 1 1 0 OO FULL ADDER I O ] 17 PHYSICAL IS NOT CHANGED J Y I | g : l A\ 18-BIT }' J Y ADDRESS OF NUMBER (WN) EXAMPLE: 177g PAGE ADDRESS FIELD L\ WORD >’ = , REGISTER (PAR) PAR 6 = BLOCK NUMBER (BN) R APF SELECTS PAGE ADDRESS 00 - —— APF EXAMPLE: 157746 g 06 05 —— 15 16-BIT VIRTUAL ADDRESS FROM: PROCESSOR 06 ADDRESS : PA <17:06 > 05 00 o | | VA <05:00> TO UNIBUS A ADDRESS DRIVERS ' 11-1399 Figure 3-3 Construction of an 18-Bit Physical Address 3.3.1 Program Relocation A timesharing system which swaps programs between physical memory and some backing store (such as an RF11 disk) can be efficiently implemented, because the programs need not be restricted to run in any particular memory locations. | When it is time to swap a program in, all that is required is that there be sufficient memory available in which to read the program and then set up the KT11-D to “relocate” the program so that it thinks it has been loaded at location 0. 3.3.2 Dynamic Memory Allocations The KT11-D provides hardware-implemented features that enable the operating system to dynamically allocate memory upon demand, while a program is being run. These features are particularly useful when running higher-level language programs, such as ALGOL and PL/1, where, for example, arrays are constructed at execution time. No fixed space is reserved for them by the compiler. Lacking the dynamic memory allocation capability, the programmer must calculate and allow sufficient memory space to accommodate the worst case. This is time consuming and in many cases memory space is wasted. | Monitor primitives to allocate (de-allocate) memory, either by adding (deleting) a page or by increasing (decreasing) the size of an existing page, may be implemented. A running program can request, and subsequently return, memory used for a temporary buffer and the like, thus efficiently using the physical store and removing the worst case memory size restrictions. o | o To illustrate how dynamic memory allocation might be used, suppose an assembler initially requests enough memory for 64 symbols, say 256 words. If this symbol table overflows, then the assembler requests an additional 256 words, and so on, until a request is denied, at which time (and only at which time) an actual symbol table overflow has 3.4 / / occurred. This algorithm is clearly more efficient with respect to memory utilization than one which initially grabs a large chunk of memory for symbols. NOTE Any use of page lengths less than 4K words causes holes to be left in the virtual address space. 3.3.3 Memory Management Statistics In a multiprogramming timeshared system, programs tend to be swapped between the main memory and some backing store, such as a disk. Needless to say, the performance of such a system is certainly dependent on the efficiency of the swapping algorithm. Those portions of memory which have not been modified, (i.e., written into) since the last time they were swapped in, need not be swapped out when the space they occupy is required for something else. Instead, the memory can be used as is, because the copy of it on the backing store is still current. Thus, “half” the swapping time can be saved for those unmodified portions of main memory. The KT11-D logic provides two mechanisms to help implement efficient swapping: 1. 2. Pages may be designated read only. Such pages cannot be modified. A flag, the “W-bit”, is automatically set by hardware whenever a potentially writable page is actually written into. 3.3.4 Memory Management Instructions Memory Management provides the ability to communicate between two spaces, as determined by the Extended Processor Status Word, PS(15—12). This capability is implemented by the addition of two unique instructions to the KD11-A Instruction repertoire: MTPI — Move To Previous Space (0066 DD). MEPI — Move from Previous Space (0065 SS). These instructions are operational in a KD11-A system, otherwise an Illegal Instruction Trap will result on an attempted execution. Memory Management does not have to be enabled (SRO bit O set) for interstack communications although relocation and protection will be disabled. If these two instructions are examined from a programmer’s point of view, they appear somewhat complex. However, from a hardware viewpoint, it is evident that they are modified MOV instructions. ‘ In investigating the memory management instructions, the following facts must be kept in mind: 1. There are two possible modes of operation: a. Kernel (Monitor) b. User. 2. The selection of modeis made by expanding and utilizing the Pmcessor Status Word (PSW). The possible machine states specified by PS(15:12) are as follows: PS(15:12) 3. 4. Current Mode (CM) Previous Mode (PM) 00 00 Kernel 1111 User | User Ke_rnel 1100 User Kernel 0011 Kernel User The MFPI and MTPI instfuctions are most likely ’to"be used in current mode Kern_el, previous mode User. The current mode specifies the Page Relocation and Descriptor Rejgister set used to convert the KD11-A virtual address to a KT11-D physical address. Examining the MFPI instruction, the general instruction format is: MFPI i.e., OP CODE and a Source address field. (0065 SS) When MFPI SS is fetched, the KD11-A will transform and encode it into the following: MFPI SS - MOV SS, — (SP) It will send it back to the processor over the RD Bus, reclock it into the IR Register, and execute it in conjunction with Memory Management space selection logic. The calculation of the Source address is donein current space. Thatis, any index word or indirect addresses usedin the address calculation are fetched using the KT11-D Page Address Registers selected by the current mode bits of the PSW. The final fetch of the Source operand in which datais to be moved from is made in previous space, i.e.,using the KT11-D Page Address Registers selected by the previous mode bits in the PSW. Note that if the Source field is mode O Register 6, the SP selected is made by the previous mode bits of the PSW. But with any other mode and R6, the SP selected is by the current mode bits of PSW; since in these cases, the register is part of the address calculation and is not the final operand. The Source operand is then pushed on the current mode stack. Examining the‘MTPI DD instruction, it has the following general format: MTPI DD (0066 DD) i.e., op code and a Destination address field. | A similar transformation to a MOV instruction is dorie to MTPI DD. MTPI DD - MOV (SP) +, DD The calculation of the Destination address is done in current space. That is, any index or indirect addresses used in the address calculation are fetched using the KT11-D Page Address Registers selected by the current mode bits of the PSW. The final fetch of the Destination operand in which data is to be stored, is made in previous space. Note that if the Destination field is mode O Register 6, the SP selected is made by the previous mode bits of the PSW. But with any other Destination mode and R6, the SP selected is made by the current mode bits of the PSW. Since in these cases, the register is part of the address calculation and is not the final operand, this instruction pops a word off the current stack determined by PS(15:14) and stores that word into a Destination address in previous space determined \\4//' by PS(13:12). 3-6 Thus, these instructions are used in memory managed systems to allow the exchange of data between the monitor (Kernel) and a user. The following is an example of how Memory Management instructions can be used in an operating system. In advanced software systems, a user can not be allowed to handle his own I/O directly. The 1/O address space is not available to a user (this is controlled by the contents of the UPAR’s, which are set up bythe monitor). Users initiate | I/O requests to the monitor by means of a trap such as EMT. | Prior to the trap, the user pushes on to his stack (R16) certain parameters such as command, word count, and buffer address. The trap sequence sets up the PS(15:12) such that the current mode is Kernel (monitor) and the previous mode was User. The Kernel must now retrieve the I/O parameters from the user core space, using the MFPI instruction. Example 1 — Retrieve parameter from User stack. KSP Kernel | USP Stack | User Stack (R16) —s{ PARAMETERS (R6) —s XX /MOV #UPCNT, RA STORE NUMBER OF USER PARAMETERS IN A REGISTER. | RN LOOP .GET USER STACK POINTER (USP) | /MFPI R6 CONVERTS TO MOV R16, - (R6) ‘ONTO THE KERNEL STACK. /MOV (R6) +, RN PUT USP IN A REGISTER ‘PUT USER PARAMETERS | /IMFPI (RN)+ CONVERTS TO MOV (RN) +, - (R6) /CMP RN, RA + RB /BLT LOOP ;ONTO KERNEL STACK. ‘HAVE ALL PARAMETERS BEEN | TRANSFERRED TO KERNEL. | ~ IF NOT GET ANOTHER PARAMETER. all of physical core (meaning the ability to access user core), this practice usually is not preferred because the user is subject to being “swapped out” at any time. Therefore, data is normally placed into a monitor (Kemel) buffer. The monitor must then transfer that data to user core by means of the MTPI instruction. N — - The monitor can now initiate the required command to the I/O. Although all devices have the capability of accessing 3-7 Example 2 — Transferring data read from a device to user core. o (RN) ~ - KSP (R6) Rx) MONITOR I/0 I;ffglfL JJOBUFFER [*—— 1/0 BUFF XX \} SPACE /MOV 1/O BUFADR, RN USER | BUFFER 3 ) ;POINT RN TO /O BUFADR. . /MOV UBUFADR, RX 3 ‘POINT RX TO USER / ‘BUFFER. LOOP /MOV (RN) +, - (R6) ‘PUSH I/O DATA ONTO THE | ‘KERNEL STACK. /MTPI (RX) + MOV I/0 DATA TO USER CONVERTS TO MOV (R6) +,(RX)+ ;BUFFER CORE. /CMP RN, I/O BUFADR + WORD CNT ;HAS ALL I/O DATA | ‘BEEN TRANSFERRED - ), - ‘TO USER CORE /BLT LOOP IF NOT GET ANOTHER S :-DATA WORD. Examples 1 and 2 do not reflect any user software system but are meant mearly as examples of the operation and uses of MFPI and MTPL. | 3.4 MEMORY PROTECTION A timesharing system performs multiprogramming; it allows several programs to reside in memory simultaneously, and to operate sequentially. Access to these programs, and the memory space they occupy, must be strictly defined and controlled. Several types of memory protection must be afforded a timesharing system. For example: d. User vpr'ograms must not be allowed to expand beyond allocated space, unless authorized by the system. b. Users must be prevented from modifying common subroutines and algorithms that are resident for all users. C. Users must be prevented from gaining control of or modifying the operating system software. The KT11-D opt»ion provides the hardware facilities to ’implement. all of the above types of memory protection. The | following paragraphs describe the memory protection features afforded by the KT11-D. 3-8 - D 3.4.1 Inaccessible Memory Each page has a 2-bit access control key associated with it. The key is assigned under program control. When the key is set to 0, the page is defined as non-resident. Any attempt by a user program to access a non-resident page is prevented by an immediate abort. Using this feature to provide memory protection, only those pages associated with the current program are set to legal access keys. The access control keys of all other program pages are set to O, which prevents illegal memory references. 3.4.2 Read-Only Memory The access control key for a page can be set.to 2, which allows read (fetch) memory references to the page, but immediately aborts any attempt to write into that page. This read-only type of memory protection can be afforded to pages that contain common data, subroutines, or shared algorithms. This type of memory protection allows the access rights to a given information module to be user-dependent. That is, the access right to a given information module may be varied for different users by altering the access control key. A page address register in each of the sets (Kernel and User modes) may be set up to reference the same physical page in memory and each may be keyed for different access rights. For example, the User access control key might be 2 (read-only access), and the Kernel access control key might be 6 (allowing complete read/write access). 3.4.3 Multiple Address Space There are two completely separate PAR/PDR sets provided by the KT11-D: one set for Kernel mode and one set for ~ User mode. This affords the timesharing system with another type of memory protection capability. The mode of operation is specified by the Processor Status Word current mode field, or previous mode field, as determined by the 2 current instruction. (MTPI and MFPI are the two instructions that use previous mode.) Assuming the current mode PSW bits are valid, the active page register sets are enabled as follows: | PS (15:14) Kernel mode 00 Illegal (all references aborted on access) 01 10 11 PAR/PDR Set Enabled | User mode 3.4.4 Mode Description With memory management the modes of operation provide the following flexibility and restrictions: In Kernel que, the operating program has unrestricted use of the machine except for the added time to a bus cycle created by the KT11-D Logic of a 150ns. The User also sees this delay plus the operating restrictions listed below: 1. Attempted execution of the instruction HALT traps as a Reserved Instruction via location 10; 2. Execution of a RESET instruction results in a no-operation execution of a NOP instruction (1.5usec). 3-9 3. User Processor Status restrictions are as follows: : USER RTI, RTT CC (3:0) | USER TRAPS, EXPLICIT PSW INTERRUPTS ACCESS Loaded from Stack . Loaded from Vector Loaded from Stack Loaded from Vecto‘r Canpot be changed Loaded from Vecto_r PREVIOUS (13:12) Cannot be changed Copied from PS (15:14) Current (15:14) Cannot be changed Loaded from Vector T (4) - PRIORITY__: (7:5) 3 Cannot be changed *» 4. Stack Limit Violations are disabled in User. Stack pfotection provided by memory protect features. Another difference between the two modes is the use of separate stack pointer registers: \‘:W/ * = Explicit operations can be made if the Processor Status is mapped in User space. Kernel — KD11 Register 6 (R6) User — KDII Register 16 (R16) On a trap or an interrupt, the vector is always referenced via Kernel sp'iace and the old PS and PC are pushed onto the stack determined by the new current mode of the PSW from the vector. Thus, a User mode program is relocated by its own PAR/PDR set, as are Kernel programs. This makes it impossible for a program running in one mode to accidentally reference space allocated to another mode when the active page registers are set correctly. For example, a user cannot transfer to Kernel space. The Kernel mode address space may be reserved for resident system monitor functions, such as the basic Input/Output Control (I0OC) routines, memory management trap handlers, and timesharing scheduling modules. By dividing the types of timesharing system programs functionally between the Kernel and User modes, a minimum amount of space control housekeeping is required as the timeshared operating system sequences from one user program to the next. For example, only the User PAR/PDR set needs to be updated as each new user program is serviced. The two PAR/PDR sets implemented in the KT11-D Memory Management Unit option are shown in Figure 34. ~NoOoabdbwnNnN-=0 KERNEL ACTIVE PAGE REGISTER PAR PDR N abhuNn—+0O USER ACTIVE PAGE REGISTER PDR ) - \4 . 11-1396 S PAR Figure 34 KT11-D Memory Management Unit Active Page Registers 3-10 \ww/// 3.5 PAR/PDR REGISTERS The KT11-D Memory Management Unit provides two sets of eight PAR/PDR pairs. Figure 34 shows how the two sets are organized. Each pair consists of a Page Address Register (PAR) and a Page Descriptor Register (PDR). These registers are always used as a pair and contain all the information required to locate and describe the current active pages for each mode of operation. As indicated in Figure 34, one PAR/PDR set is used in Kernel mode and the other is used in User mode. The current mode bits (or in some cases, the previous mode bits) of the Processor Status Word determine which set will be referenced for each memory access. A program operating in one mode cannot use the PAR/PDR sets of the other mode to access memory. Thus, the two sets are a key feature in providing a full-protected environment for a timeshared multi-programming system. 12 1" ' o s 11-1036 RN Figure 3-5 Page Address Register (PAR) Format A specific processor I/O address is assigned to each PAR and PDR of each set. Table 3-1 is a complete list of address o | assignments. NOTE Unibus devices cannot access PARs or PDRs. In a fully-protected multi-programming environment, the implication is that only a program operating in the Kernel mode would be allowed to write into the PAR and PDR locations for the purpose of mapping user’s programs. However, there are no restraints imposed by the KT11-D logic that will prevent User mode programs from writing into these registers. The option of implementing such a feature in the operating system, and thus explicitly protecting these locations from user’s programs, is available to the system software designer. st Table 3-1 )" PAR/PDR Address Assignments No. 0 1 2 3 4 5 6 7 Kernel Active PageRegisters PDR 0 1 2 3 777640 777642 777644 777646 777600 777602 777604 777606 5 777652 777612 PDR 772340 772342 772344 772346 772300 772302 772304 772306 772350 772352 772354 772356 4 772310 772312 6 7 772314 772316 3-11 User Active Page Registers PAR PAR No. 777650 777654 777656 777610 777614 777616 3.5.1 Page Address Registers (PAR) The Page Address Register (PAR), shown in Frgure 3.5, contains the 12-bit Page Address Field (PAF) that specifies the base address of the page. Bits (15 :12) of the PAR are not implemented in the hardware. The Page Address Register may be alternatively thought of as a relocation constant, or as a base register containing a base address. Either interpretation indicates the basic functlon of the Page Address Regrster (PAR) in the relocation scheme. 3.5.2 Page Descriptor Registers (PDR) The Page Descriptor Register (PDR), shown in Figure 3-6, contains information relative to page expansion, page length, and access control. | 14 : . 8 7 6 5 4 7% " %////% 3 2 om 15 @ " PAGE LE(f;fiI_i; FIELD | 1 0 % 11-1395 Figure 3-6 Page Descriptor Register (PDR) Format 3.5.2.1 Access Control Field (ACF) — This 2-bit field, ACF (02:01) of the PDR describes the access rights to this particular page. The access codes or “keys” specify the manner in which a page may be accessed and whether or not a given access should result in an abort of the current operation. A memory reference that causes an abort is not completed and is terminated immediately. Aborts are caused by attempts to access non-resident pages, page length errors, or access violations, such as attempting to write into a read-only page. Traps are used as an aid in gathering memory management information. In the context of access control, the term “write” is used to indicate the action of any instruction which modifies the contents of any addressable word. A “write” is synonymous with what is usually called a “store” or “modify” in many computer systems. Table 3-2 lists the ACF keys and their functions. The ACF is written into the PDR under program control. | Table 3-2 Access Control Field Keys Key 00 | 0 01 2 10 | 4 1.1 6. - . Description Function Non-resident (NR) Abort any attempt tova’ccess this non-resident page. Residenr-read-only (RRO) Abort eny attempt to write into this page. ~ Illegal Abort all accesses. ‘ Resident read/write (RRW) Read or Write allowed. No trap or abort occurs. N | ACF 3-12 3.5.2.2 Expansion Direction (ED) — The ED bit located in PDR bit position 03 indicates the authorized direction in | J which the page can expand. A logic 0 in this bit (ED=0) indicates the page can expand upward from relative zero. A logic 1 in this bit (ED=1) indicates the page can expand downward toward relative zero. The ED bit is written into the PDR under program control. When the expansion direction is upward (ED=0), the page length is increased by adding blocks with higher relative addresses. Upward expansion is usually specified for program or data pages to add more program or table space. An example of page expansion upward is shown in Figure 3-7. 4 PAR PDR 111 000 001 O 0101001 0000 O 110 000 PAF = 0170 —T PLF = 51g = 41,5= NO. OF BLOCKS | ED=0=UPWARD EXPANSION _) ACF=6=READ/WRITE NOTE: TO SPECIFY A PAGE, BLOCK LENGTH OF 42 WRITE HIGHEST AUTHORIZED FOR AN UPWARD EXPANDABLE BLOCK NO. DIRECTLY INTO HIGH BYTE OF PDR. BIT 15 IS NOT USED BECAUSE THE HIGHEST ALLOWABLE BLOCK NUMBER IS 177g ////////////// ’ fl o ////// / .ANY BLOCK NUMBER / LOCK 177 . ADDRESS RANGE EXPANSION CHANGING THE 176/ GREATER THAN 41 (51g) LOCK BY PLF wiLL CAUSE A PAGE /BLOCK S2g4 LENGTH ABORT. ///////// ) 024176 | BLOCK 51g ) 024100 017276 AUTHORIZED ¥ PAGE BLOCK 2 LENGTH = 42,, BLOCKS 017200 OR'O THRU 51g= 017176 017100 | 017076 BLOCK O 017000 j«—BASE ADDRESS OF PAGE 11-1030 Figure 3-7 Example of an Upward Expandable Page 313 When the expansion direction is downward (ED=1), the page length is increased by adding blocks with lower relative addresses. Downward expansion is spemfled for stack pages so that more stack space can be added. An example of page expansion downwardis shown in Fiigure 3-8. l<—ACTIVE PAGE REGISTER CONTENTS—‘! PAR PDR IOOO 001 111 OOO] \ l01010110 0000 1 110] ; PAF =0170 \ , l ' 4 ' PLF=126g = 8640 ED=1= DOWNWARD EXPANSION WRITE LENGTH COMPLEMENT OF FOR A DOWNWARD BLOCKS IN THIS EXAMPLE, A 42-BLOCK PLF IS DERIVED AS REQUIRED PAGE EXPANDABLE INTO HIGH BYTE PAGE,- N TO SPECIFY PAGE OF PDR., IS REQUIRED. FOLLOWS : 4240 = 52g ; TWO'S COMPLEMENT=126g ! 035776 FIRST BLOCK OF DOWNWARD BLOCK 1778 EXPANDABLE PAGE 036700 ) 036676 BLOCK 176g 036600 AUTHORIZED PAGE LENGTH=42 4o BLOCKS BLOCK 036576 175g 036500 P N T T T e TM 031676 BLOCK 126g 031600 * 077777777 BLOCK 125¢g 7 7777 007 ADDRESS RANGE OF POTENTIAL PAGE EXPANSION BY CHANGING THE PLF ?BLOCK 124% A BLOCK NUMBER ////////////////4 /] 54 ///////0 71/76‘ REFERENCE LESS >TH’-\N 126g (VA <12:06> LESS THAN | WILL CAUSE BLOCK ////////,9,17,999/ | 126g) A PAGE LENGTH ABORT. <+— BASE ADDRESS OF PAGE 11-103 Figure 3-8 Example of a Downward Expandable Page 3-14 // . 3.5.2.3 Written Into (W) — The W bit located in PDR bit position 06 indicates whether the page has been written into since it was loaded into memory. W=1 is affirmative. The W bit is automatically cleared when the PAR or PDR of that page is written into. It can only be set by KT11-D control logic. | | ~ In disk swapping and memory overlay applications, the W bit (bit 6) can be used to determine which pages in memory have been modified by a user. Those that have been written into must be saved in their current form. Those that have not been written into (W=0), need not be saved and can be overlayed with new pages, if necessary. NOTE | . The W bit cannot be set by a memory access of a KT11-D internal register (SRO) or a memory access that causes an abort. 3.5.2.4 Page Length Field (PLF) — The 7-bit PLF located in PDR bits (14:08) specifies the authorized length of the - page, in 32-word blocks. The PLF holds block numbers from 0 to 1773, thus allowing any page length from 1 to 128, o blocks. The PLF is written in the PDR under program control. 3.5.3 PLF for an Upward Expandable Page ‘When the page expands upward, the PLF must be set to one less than the intended number of blocks authorized for that page. For example, if 525 (421 o) blocks are authorized, the PLF is set to 51g (41, ) (Figure 3-7) block 0 being the page boundary and the first block of that page. The KT11-D hardware compares the virtual address block number, VA (12:06) with the PLF to determine if the virtual address is within the authorized page length. i j - When the virtual address block number is less than or equal to the PLF, the virtual address is within the authorized page length. If the virtual address is greater than the PLF, a page length fault (address too high) is detected by the hardware and an abort occurs. In this case, the virtual address space legal to the program is non-contiguous because the three most significant bits of the virtual address are used to select the PAR/PDR set. 3.5.4 PLF for a Downward Expandable Page The capability of providing downward expansion for a page is intended specifically for those pages that are to be used as stacks. In the PDP-11, a stack starts at the highest location reserved for it and expands downward toward the lowest address as items are added to the stack. The first block of the downward expandable page being block 177s. When the page is to be downward expandable, the PLF must be set to authorize a page length, in blocks, that starts at the highest address of the page. That is always Block 177g. Refer to Figure 3-8, which shows an example of a downward expandable page. A page length of 42, 5 blocks is arbitrarily chosen so that the example can be compared with the upward expandable example shown in Figure 3-7. x NOTE | T | The same PAF is used in both examples. This is done to y, emphasize that the PAF, as the base address, always determines the lowest address of the page, whether it is upward or downward expandable. The rationale for complementing the number of blocks required to obtain the PLF is as follows: ) MAXIMUM BLOCK NO. MINUS REQUIRED LENGTH EQUALS PLF 177, _ 52, - 125, 3-15 3.6 MEMORY MANAGEMENT STATUS REGISTERS ‘Aborts generated b'y the KT11-D _logic are vectored through Kernel space address location 250. The KT11-D has three status registers of which two are functional; SRO, SR2 and SR1 responding with all zeros. Status Register SRO and SR?2 can be referenced by fault recovery routines to determine why the abort occurred. The following paragraphs describe the formats of both status registers. 3.6.1 Status Register 0 (SR0) SRO contains abort error flags, memory management enable, plus other essential information required by an operating system to recover from an abort or service a memory management trap. The SRO format is shown in Figure 3-9, 15 14 13 12 9 8 W % ABORT : NON-RESIDENT _4 ABORT :PAGE LENGTH ERR ABORT: READ I 6 5 L 7/ 4 3 7/ //\ } —— ONLY VIOLATION 7 7/ o | 2 1 0 b ADDRESS : T b ENABLE KT11-D L | | 777572 | PAGE NUMBER MODE OF OPERATION MAINTENANCE MODE 1-1394 Figure 3-9 Format of Status Register 0 (SR0) Bits (15:13) are the abort fl_ags-and are enabled when an address is being relocated by the KT11-D. This implies that either SRO, bit 0 is equal to 1 (KT11-D operating) or that SRO, bit 8, is equal to 1 and the memory reference is the final one of a destintion calculation (maintenance/destination mode). NOTE Bit 15, 14, or 13, when set (abort conditions) cause KT11-D logic to freeze the contents of SRO bits 1-6 and status reglster 'SR2. Thisis done to determine the cause of the abort. Note that SRO bits 0 and 8 can be set under program control to provide meaningful memory management control information. However, information written into all other bits is not meaningful. Only that information which is automatically written into these remaining bits as a result of hardware actions is useful as a monitor of the status of the memory management unit. Setting bits (15:13) under program control will not cause traps to occur. These bits, however, must be reset to 0 after an abort or trap has occurred in order to resume monitoring memory management. 3.6.1.1 Abort-Nonresident — Bit 15 is the “Abort-NonresidentTM bit. It is set by attempting to access a page with an access control field (ACF) key equal to 0 or 4 and setting PS (15:14) to an illegal mode. 3.6.1.2 Abort — Page Length— Bit 14 is the “Abort-Page Length” bit. It is set by attempting to access a location in a page with a block number (virtual address bits 12:06) that is outside the area authorized by the Page Length Field (PLF) of the PDR for that page. 3.6.1.3 Abort-Read Only — Bit 13 is the “Abort-Read Only” bit. It is set by attempting to write in a “‘Read-Only”’ page having an access key of 2. NOTE There are no restrictions that any abort bits could not be set simultaneously by the same access attempt. 3-16 3.6.1.4 Maintenance/Destination Mode — Bit 8 specifies maintenance use of the memory management unit. It is used for KT11-D diagnostic purposes. For the instructions used in the initial diagnostic program, bit 8 is set so that only the final destination reference is relocated. It is useful to prove that the KT11-D is capable of relocating addresses. | - 3.6.1.5 Mode of Operation — Bits 5 and 6 indicate the CPU mode (User or Kernel) associated with the page causing the abort. (Kernei=00, User=11). These bits are controlled by the KT11-D logic that decodes current previous mode bits of the PSW. 3.6.1.6 Page Number — Bits 3—1 contain the page number of reference. Pages, like blocks, are numbered from 0 upwards. The page number bit is used by the error recovery routine to identify the page being accessed if an abort occurs. 3.6.1.7 Enable KT11-D — Bit O is the “Enable. KT11-D” bit. When it is set to 1, all addresses are relocated and protected by the memory management unit. When bit 0 is set to O, the memory management unit is disabled and Ps addresses are neither relocated nor protected. Status Register 2 (SR2) N 3.6.2 SR2 is loaded with the 16-bit Virtual Address (VA) at the beginning of each instruction fetch but is not updated if the instruction fetch fails. SR2 is read only; a write attempt will not modify its contents. SR2 is the Virtual Address Program Counter (Figure 3-10). Upon an abort, the results of SRO bits 15, 14, or 13 being set, SR2 will freeze until the SRO abort flags are cleared. ADDRESS: 16-BIT VIRTUAL ADDRESS 277576 11-1040 Figure 3-10 Format of Status Register 2 (SR2) 3.7 DETERMINING THE PROGRAM PHYSICAL ADDRESS A 16-bit virtual address can specify up to 32K words, in the range from 0 to 1777765 (word boundaries are even octal numbers). The three most significant virtual address bits designate the PAR/PDR set to be referenced during page address relocation. Table 3-3 lists the virtual address ranges that specify each of the PAR/PDR sets. | To calculate the physical address, disregard the three most significant VA bits and add the remainder to the - PAR contents, right-shifted six places. Example: VA =167456 = xxx0111 100101110 Table 3-3 Relating Virtual Address to PAR/PDR Set Virtual Address Range PAR/PDR Set +(PAR)=3456= 011 100101110 000000-17776 0 PA =355256= 011 101101 020000-37776 1 040000-57776 2 060000-77776 3 100000-117776 4 120000-137776 5 010101110 _, Where x indicates these bits are not used in the calculation. | 3-17 140000-157776 6 160000-177776 7 Reader’s Comments KT11-D MEMORY MANAGEMENT OPTION USER’S MANUAL EK-KT11D-OP-001 Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our publications. What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well written, etc.? Is it easy to use? CUT OUT ON DOTTED LINE What features are most useful? What faults do you find with the manual? Does this manual satisfy the need you think it was intended to satisfy? Does it satisfy your needs? Why? - Would you please indicate any factual errors you have found. Please describe your position. Name Organization Street Department City State _ Zip or Country FIRST CLASS PERMIT NO. 33 MAYNARD, MASS. NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES Postage will be paid by: Digital Equipment Corporation - Technical Documentation Department 146 Main Street Maynard, Massachusetts 01754 dlifgliltiall digital equipment corporation Printed in U.S.A.
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