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Document:	KS10 Technical Manual
Order Number:	EK-KS10-TM
Revision:	PRE
Pages:	211
Original Filename:

OCR Text

EK-KS10-TM-PRE

KS10 TECHNICAL MANUAL

(PRELIMINARY)"
Interim Release

“OMPANY CONFIDENTIAL

U0 NOT DUPLICATE

Fiest Jiefeae (Kevieis) 1/0)78
Stcond Kakeaic (Z}J#fi,’,) 2/zf,//7;

The drawings and speciications hereinare the property of Digital Equipnient
Corporation and shall not be reproduced or copied or used i whole or in part as
the basis for the manutacture or sale of equipment described heretn without
wrtten pernission.

Copr, right @ 1979 by Digital Equipment Corporation

The matenai in this manual is for intormationa
prrposes and is subject to change without notice.
Bigital Equipment Corporation assuines no respon-

siblity for any errors which may appear in this
muinal,
Printed in ULS.AL

The foallowing are trademarks of Digital Equipment
Corporation, Maynard, Massachuseltts:

BINE

DECape

DECCOMM

DECUS

DECsysten: 10
DECSYSTEAM20

DIGITAL
MASSBUS

RSTS

TYPESLT-®
TYPESET-1
UNIBUS

PREFACE

This

document

interim version of

KS10 Technical Manual
been

released

Training

for

Seminar.

and that not

all

been validated.
will

(Preliminary)

the first Field
Note
the

that

that has

Service

not

existing material

A final

released prior

version
FCS.

the

complete
has
document

CONTENTS

SECTION

INTRODUCTION

DESCRIPTION

U PN

PHYSICAL

KS10PA

(o)}

NN
N

OVERVIEW

Operators

BA11-K
Power

System

MASSBUS Transition Plate
Asynchronous Communications

Panel

(B317Es)
1.

Switch

SITE

PREPARATION

2. 1

SITE

PLANNING

ENVIRONMENTAL

SYSTEM

PRIMARY

2. 5

OPTION

SECTION

f—

POWER
DATA

Ut N

(AC)

SHEETS

supplied

AND

INDICATORS

DIFFERENCES

(KS10

KL10)

Public Mode
Addressing
Interrupt

Handling

Paging

KS10

Instruction

Set

KS10 I/0 INSTRUCTIONS
Internal (APR) I/0 Instructions

External I/0 Instructions
PXCT Extensions
KS10

PROCESSOR

Halt
[

REQUIREMENTS

OPERATION/PROGRAMMINC

KS10

NN
NN
N
ww
ww

PLANNING

CONFIGURATION

CONTROLS

e
N
RS R

AND

INSTALLATION

To
SECTION

Panel

Status

STATUS
Word

WORDS

Halt

Page

KS10

EPT/UPT

Status

OPERATION

supplied

TECHNICAL

System

AND

TIMING

Logical

Organization

Timing

Intrasystem

Data

Bus

8646

U1 B~ W

Bus
Bus

Bus

(BACKPLANF)

Bus

I/0

O 00

KS10

Registers

DESCRIPTION

Processor

Bus

Parity

Flow

BUS

Timing

Bus

Transceiver

Arbitration
Usage

Command/Address
Memory

Cycle

Operation

Operation
Operation
Error

MICROCONTROLLER

Microword
Control

Dispatch

Skip

Word
RAM

and

Dispatch

Subroutine

__’_\'-P\.;

IR |

Commands

KLINIK

Mode

Console

Booting
DATA

CONSOLE

Console

RN RN MNDNNN NN N

Block

Word

ORGANIZATION

Ul Lt
o
ot
ot
G
i
bt
bt

oo
o

wwwwwww

u"\J‘iA_\n

Fail

OPERATOR

SECTION

P R

Status

Word

PATH

and

Main
"RAM

Diagnosis

EXECUTE

Arithmetic

Unit

Path
File

Ten-bit

logic

Program

Flags

Logic

Stack

DATA PATH MEMORY
MEMORY

(To

CONSOLE

KS10

(To

ADAPTER

POWER

(To

w N~

Blower

Interconnection

Power
for

PREVENTIVE

To
SECTION

Power

5-P3

Supply
CPU

and

PEM

5-P4
5-P7

Memory

5-P8

and

MAINTENANCE

supplied

541326

(BA11-K)

supplied

CORRECTIVE

5-P1

Supply

supplied)

Control

H7130

SECTION

SYSTEM

Power

H765

supplied)

supplied

861

supplied

i
b
W

UNIBUS

(To

Control

5-P8

SECTION

INTRODUCTION

The DECSYSTEM-2020 is the hardware base for the new low end member
of

and

the DECsystem-10

DECSYSTEM-20

system runs the TOPS20 operating system
differences

from

2040/2050

appear

computers.

families

(Release 3)
the

wuser

such that no
level.

capability provides a new kind of mainframe computer;
machine

with

large

software

computer

power

The

This

that is,

mini-mid

the

computer price range.

OVERVIEW

1.1

The configuration for the end-user version of the 2020 KS10 system

shown

Figure

1-1

1listed

and

Table

1-1.

(Note

that

systems supported by DEC Field Service require a magtape.)

Table 1-1

2020 Configurations

Item

Min System

Typical System

Max System

CPU (KS10)

MEMORY

128K words

256K words

512K words

RM03 or RPO06

TU45

0 (see note)

/=1

KE10 MEM 84K

MEM CTL

. FLAGS

ax PROM

]
b4

1% AAM

J::} 10

wos

CRA

CRAM
x

s
I

UART

UAART

CONSOLE

BOARD

h ——— -—Tm — — L] A L —— L J L] A A S

DPM

OFE

UNiIBUS
‘

ADAPTER

U iBUS

UNIBUS

ADAPTER

“KLINIKTM

RMYITL
@

——

pZN

{1-48)

UNiBUS

MASSBUS

/ 4

|=
—

—_—

USER

TEAMINAL

INALS

AH11-C

.
P

P20

DisK

.
nMO3

KMC11

-8

0-1)
J

[}

LRGS

DuUP1Y

LP14

6-2)

MASSAUS

TAPE

NOTES

TU4E

STRAPPED FOR NONHOG MODE

1041

STRAPFED FOR HOG MODE

Figure

1-1

2020

System

Configuration

SYNC LINES

LPO5/LP14

TERMINAL LINES

NOTE

systems

OEM-serviced

- Software/Hardware

maintain

systems

DEC

only.

Support

will

not

that do not have TU45

Magtape.

The KS10 has an intefnal backplane bus that provides a control and
data path between the prbcessor, memory, console, and peripheral
devices

(via Unibus adapters).

is a multiplexed 2-cycle bus

that allows command and address information to be transmitted by
one

bus

device

another

during

one

bus

cycle;

data

1is

then

transferred to/from the addressed device during a following bus
cycle.

The KS10 processor consists of 4 extended hex modules

(i.e., data

path modules DPE and DPM, and control-store modules CRA and CRM).
The processor uses low power Schottky TTL and features the AM2901
A-bit data path slice.

512-word

Other features include:

virtual-address
4

cache memory.

blocks

Parity

Fast

operations

byte

word

micro-store,

(96-bits/word)
provision

purpose

for

7-bit

registers.

ASCII

writable

data

RAM

time of

memory

single

connects

(array)

modules.

features

Each

consists

the

storage

and

micro-store

with

4K words.

cycle

system

paths,

characters.

Basic micro-instruction

that

general

bus.

module

Memory

fast

checking

address

KS10

backplane

The

backplane
module

bus

300

NS.

extended

hex

control

and

2-8

storage

MOS

memory.

words

maximum

contains

64K

include:

1.050

wsec

Single

bit

error

correction.

Double

bit

error

detection.

cycle

time.

lZBK{pminimum
capacity.

capacity

and

512K

The console consists of a single extended hex module that uses an

8080 microprocessor to perform console and diagnostic functions.
Provision

made

for

connection

KLINIK

that

operates

parallel with the CTY and allows diagnosis of the system via a
remote

link.

KS10 peripheral devices are selected Unibus devices that interface

to the system through Unibus adapters (UBAS).
to

connecting

both

A UBA is a single
backplane

the

and

bus

extended

hex module

Unibus.

Up to three UBAs may be installed in the KS10 although

two UBAs are standard in the end-user 2020 configuration.

(and Unibus)

1is

reserved

is used for

Unibus)

printer,

and

disks only.

for

all other devices;

synchronous

that

asysnchrous

and

One UBA

The second UBA

(and

tape,

line

is,

for

communications

1lines.

Characteristics and features of the devices supported on the UBAs
are

follows:

DISKS

RPO6

Average access time of 36.3 ms.

Average seek time of 28 ms.

Formatted capacity of 176 MB.
/-

Maximum data transfer rate of 166K 36-bit words/second.

128

36-bit words/sector.

Removable

18-bit

(20-surface) disk pack.

(NPR)

data

transfers

over Unibus;

36-bit

(NPR)

data transfers over backplane bus.

RMO3

Average access time of 38.3 ms.

Average seek time of 30 ms.

Formatted capacity of 67 MB.

Maximum data transfer rate of 250K 36-bit words/second.
128 36-bit words/sector.

Removable

18-bit

(5-surface) disk pack.

(NPR)

data

transfers over Unibus;

data transfers over backplane bus.

TAPE

36-bit

(NPR)

TMO03/TU45

Tape

speed

of 75

IPS.

Density of 800/1600 BPI.

9-track

format

Maximum_data transfer rate of 60K 18-bit words/second.

Uses 1/2 inch industry-standard tape.

18-bit

(NPR)

data

transfers

over

Unibus;

data tranfers over backplane bus.

SYNCHRONOUS COMMMUNICATIONS INTERFACE

DUP11 single-line controller (1 per line).

Bit rate of 2000-19200 BPS.

DDCMP data protocolf

KMC11l NPR microprocessor

2 lines/system

(maximum).
/-7

(one per system).

18-bit

(NPR)

bit

(NPR)

data

data transfers over

(NPR)

ASYNCHRONOUS

DZ11

232C

interface

bit

backplane bus.

COMMUNICATIONS

INTERFACE

1800,

2000,

2400,

16,

24,

Character

1.5,

Carrier,

standard.

50,

rates

8 or

8-line controllers.

Baud

transfers over Unibus;

75,

110,

134.5,

3600,

4800,

7200,

lines per

lengths of 5,

150,

300,

600,

1200,

break

MODEM

and 9600.

system.

or 8 bits.

2 stop bits.

ring,

data,

terminal

ready,

silo

receive

buffer

and

control.

0dd/even parity.

Full duplex.

10.

character

/-&

(alarm

characters).

8-bit

11.

I/0)

(register

1.2

PHYSICAL DESCRIPTION

The

KS10

configured

compactly

high-boy cabinet

8-bit

Unibus;

over

transfers

data transfers over backplane bus.

(register I/0)

data

single

This cabinet,

(H7502H-7).

width

corporate

shown in Figure 1-2,

houses the KS10PA, BAllK drawer, power system, MASSBUS transition

communication

asynchronous

plate,

panel,

and

switch

operator's

panel.

1.2.1

KS10pa

The KS10PA assembly card cage

that

is a hybrid style card cage;

It is

is, it contains both extended hex and standard hex modules.

located in the lower front portion of the KS10 cabinet as shown in
This assembly contains the KsS10 CPU,

Figure 1-3.
(128K

minimum,

words

512K

maximum),

words

two

(UBAs), and the RH11C Unibus disk controller.
is

shown

Figure

the MOS memory
adapters

Unibus

Module utilization

1-4.

BAll-K

1.2.2

(Figure

The BAll1-K

drawer

peripheral

controllers.

contains

1-3)

has

the

dedicated

KS10

system's

I/0

for

the

1locations

following:

Dz1ll

asynchronous

communications
/=9
/

controllers:

minimum

FRONT VIEW

2 bers]

0000

SR
LTS e 2

!DUTlQ 0,

[

Figure

cemn

wwp

wen

1-2

/-—//¢

KS10

Cabinet

Tuiu

=s4..Im———eee+esN=_LL|T- b'¥r4B1/ i]NK

;A.Riy:IBRmfiN[E%W1bXMNfl%

/L/ Ll ‘J/-

A+ , 4 :/ ; C . —0—

_ / ! - \L b / - \

D
|

GEN RGNS

/\=2 ~

\s‘v

OPERATON

T~ SWITCH
PANEL

C!13 U
-~

NN,

Frgure

]..ht

i RN

Cabinet

/- 77

(Fronot

View

Skins

Removed)

8 .7 .6 5% 4 3 2

2928 2726252423222120.12 18 17 16 15 14 13.12 1HiI0 9
A

1
A

/s
7

TM 5

]

IERIED
MO

|IOIN

S LR R AR RN R

bl Bl N

)
fea)

[

-—

-i

fm“‘\g:::::
o] S

fa)

olWlojo |

MEIEYR
X

FgRols]z]s =

oy
=|
Sl=1=1={=]

65%35N2N2

g R

~Esgr

[

o
~

’

REGULAR

“

‘

" EXTENDED

HEX BOARDS
M S
BACKPLANET
BOARDS "CARD. CAGE
* .. «HEXRHIIFA
R
)
e
A

Tl RLLB VUT RN

5{12,

Figqure

(8 lines),

’;

DUP11/KMCll
minimum,

1-4

KS10PA

2 DUPils maximum

RHILC

magnetic

nmax imim.

MUL

(2 lines).

controller:

system

tape

controller:

communicationss

synchronous

LP20 line printer

Cage,

{32 lines).

4 maximum

Card

0 minimum,

1 maximum.

controller:

(This option i3 bundled

intc

minimum,

the TAU4S

tape

system.)

BA11-K

module

variations

are

utilizetion
shown

Figure

shown

1-6.

1in

Figure

1-5.

Option

A 23222 2018
]

]

;

Aol
O

1)
e o

Al Al AL !

‘.

N
| =-

o)
=l

M
1519
=

o
o4

Q
Q8

1432110

(TR S

&
o R

1))
=

@
<
=

NI- ER R

NEERE
N

Tioigs! TM ole
g

|9
Wi
w! Dl

O! «
1O101

N B
e
Ololojol

N~
O

r~
CIRGIRG!

KL K]%]| ¥ *

2! 3

@®

Rl E
0 Vi

]
b
SIZIRININININI
RN
YN
iy N g
N

Ololo| TN
MEININEIBIB
IR
- =
-< I
N oo

0| w©|©
sl ==

dlapl

NSt B e

—1

|
Le

]

e e ot Y_.___._.__,)

._._.-.._)

JPTIONAL
LPzO

;

CPTIONAL RHil BACKPLANE
(BUMILED wrTid THAUHAS)

——

J—

DOl -DK .

BAII-K MODULE UTILIZATION
e

EACKFLANE
ApCKE

— -

AE s L wnS Fromr mrodale sl
e

BA11-K Drawer, MUL

Figure 1-5

DOPTION VARIATIONS

‘“LD‘”‘: ASTMC LINESTAS TG LINES| ASYNC LINES! oYNC
B-19

_——

4
s

24-32

o~ 23

_A
e

MRLLT MO
LWT8eT LuP

| MTE19 Du

v | & Panen ST (MRS DEN
R

137

pa A P A gl A N A SIALEL o SLOT
Figure 1-6

f"/j

syhe - 2N°
W) DLPIL

A i W23 LAsTS.
s AAT

BAl11- K Option Variations

1.2.3

Power

System

The major components in the KS10 power system are

the 861 power

control for AC power distribution, the L.H. switcher power supply
for powering the KS10PA, and the H765 switcher power supply for
powering the BAll-K. Component designations for 60 HZ and 50 H2Z
follows:

machines are

KS10AB (230v, 50 HZ)

XS10AA (115Vv, 60 HZ)

8618

861C

* ,,H., P.S.

* ,,H., P.S. (H7130D)

(H7130C)

H765B (powers BAllK)

H765A (powers BAllXK)

NOTE TO DEC IN-HOUSE FIELD SERVICE PERSONNEL

The first of the in-house KS10 systems will contain H7130A
(50 Hz)

(60 Hz)

and H7130B

colored)

models

are

colored)

models

that arve

power

Although

supplies.

input

and output .power specifications for these A and B (blue

differences

the

power

type with another.

same as

for

installed

harness

wiring

the

and

(silver

in all other machines,
prevent

replacing

one

Thus, in the event of failure, replace a

olue power supply with only a blue power supply, and replace

a silver power supply with only a silver power Supp.iy.

/=1 F

MASSBUS Transition Plate

1.2.4

The MASSBUS transition plate is located at the top of the KS10
that
cabinet as shown in Figure 1-7. It is a connection plate
holds three MASSBUS connectors plus two 25 pin communications
t
cable connectors. The MASSBUS connectors are allocated from righ
to

left as follows:

Disk MASSBUS channel

Tape MASSBUS channel

Line printer channel

The two communication cable connectors are allocated as follows:
(BCO3L to BCO3M)

CTY

KLINIK remote maintenance port

(BCO3L to BCO5D)

Asynchronous Communications Panel (H317Es)

1.2.5

The X510 is configured with a minimum of 1-H317E

and a maximum of 2-H3178s (32 lines).
EIA communication only.

MINIMUM CONFIGURATION

Lines

0-7:

line MUX)

- D711 Module

- H317€ distribution panel

- BCOS5W

cable

(up to 16 lines)

It will be configured with

REAR VIEW

(SKINS REMOVEU)

TERMINAL

DISTRIBUTION| |

e Ty oW
PLA7TL

\\\\\

/X
H317-E L]
TERMINAL ~~

- DISTRIBUTION

t
|

L\\\

" BAIIK

UMIBUS
OPTION
DRAWER

M REYe

\Zj'
XX
4
1-7

L SUPPLY
N

Figure

TM~ POWEK

KS10

Cabinet

/- %

I(SWING

MOUNT)

86|
POWEK CONTROLL

(Rear

View

Skins

Removed)

OPTIONAL

Lines

EXPANSION

8-15

(defined

- DZ11 Module

- BCO5W-8

Line

The

line MUX)

as a DZ11lAA):

- D211

- BCO5W-8

- H317E distribution panel

24-32

1.2.6

a DZ11BA):

cable

(defined

Line 16-23

Module

DZ11

BCO5W-8

Module

Operators

line MUX)

cable

(defined

DZ11BA):

line

cable

Switch

Panel

operator's switch

panel

position
functions

the

are

MUX)

KS10

given

cabinet

is
(Figure

Section

/=17

top-most

1-2).

Switch

and

front

indicator

SECTION

SITE PREPARATION AND PLANNING

2.1

Refer

SITE PLANNING

to Section 1

(Subsections

1.1

1.5)

the DECSYSTEM-20

Site Preparation Guide for the following information:

Schedule of site preparation prior to system delivery.

Summary

site

functions

preparation

and

responsibilities.

2.2

Site consideration and selection.

4.,

Building

requirements.

ENVIRONMENTAL REQUIREMENTS

The recommended environmental specifications for DECSYSTEM-20

systems

(including KS10

systems)

are listed

in Table 2-1.

The

environmental specifications for individual KS10 system components

are given on data sheets in Subsection 2.5.
air

flow

rate

internal

fans

are

also

Heat dissipation and
given.

estimate

cooling and other environmental requirements, refer to Subsection
1.6 of the DECSYSTEM-20 Site Preparation Guide.

)

ICATION

tx)

o
=

PARAMETER

Recommended KS10 System Environmental Specifications

192]

Table 2-1

(65 F to 75 F)

Temperature

18 C to 24 C

Humidity

40%

Temperature Rate of Change

2 degrees C/hr

Humidity Rate

60%

(3.6 degrees F/hr)

2%/hr

of Change

1207208

Voltage Tolerance

phase/three phase

VvV

240/380

for

10%

(60HZ)

10%

phase/three phase

NOTE

the

Compliance

specifications
the

system

Agreement.

environmental

above may be
under

DEC

required

for

(50HZ)

60 HZ + 1 HZ

Frequency Tolerance

single

Maintenance

single

2.3

SYSTEM CONFIGURATION

Figure 2-1 shows a typical KS10 system configuration.

Reference

is made on the figure to Tables 2-2 and 2-3, which provide
MASSBUS and device cable data, and to Figure 2-2 and 2-3, which
show interconnections of the asynchronous and synchronous
communications lines.

2-3F

MASSBUS CABLE {SEE TABLE 2.2}

LUEVICE CAEBLE (SEE TABLE 2-3)

TU4S

T PROCESSOR. RCI3M~F

FIIOVIDED WITH TERMINAL.

SEE FIGURE 2.2
CEE FIGURE 2.3
11 DENOTES ONE TERMINATOR

TUL45

(5edve)

S1ODEM DEVICE CABLE (BC050-25)

LOES M-S NS

(AMIASPER)

T]Z

TMO2 /7AMPT

rACK (70-09138) PER MASSBUS.

(Movrrer: m Ths” HM‘?M)

TLIIMINATORS PROVIDED BY 6

RESISTOR PACKS PLACED ON
118921 MODULE OF LAST TUA4S,

‘

TO HHEMOTE
DIAG CONSOLE

)
RPO6

FKLINTR)

RPOG

8 MAX

RMO3

KS10

PROCESSOR

LPOS

LP14

LINE

PRINTER

kY,

MAX

@
LA36
CONSOLE

MMUNICATION

COMMUNICATION

LINES
.

Figure

2-1

MA 0850

Typical

KS10

2-4

System

Configuration

00 00

REHOTE C(FULL MODEM) APPLICATION
it
.

b Lg

S
(4

n
WK TvR
"

10 [0

LOCAL (DATA ONLY) APPLICATION
DZ11-A
(n7819)
¢ PLUPES WY
)

CIRE JOTES 1.3 MO V)

"-a

(C _J

(X O
1 TES 1,2 MO V)

HrD-

S;fi?5§fl§5

D S

R D A S

/)Z

00 8N
SRIvaIDe

§over

.
b e En W wn

HIXTURE OF LOCAL AND REMOTE APPLICATIONS

" BERDETOSE
S 10T P
NS AASTSIN.

-y Tt M R

ey o n e

7O ACMMRO
OF CARLE
LESS
LDITH.

15 SELIOH

8973

Y. 17 DATA BATE 15 2ve0 B OR

T S

DT T o} Din coeimn
9 F1 RESPECTIVELY,

Tl Pax

:O“I’;l.‘ SY;%I:‘W"’IC&"N
& CARE LDETTM,

Figure

2-2

KS10

Asynchronous

Communications

Lines

REMOTE SYNCHRONOUS MODEM CONRECTIONS (SYSTEM TO SYSTEM
PR3-+

M-S

2
T T
ST
L ]
o
T
\
e
~
DUP11-DA
:{}HS—&D—‘”—‘[F
n
L
fl——gy—flfl“g}‘{’fl:»]
DUP11-DA
(H7867)
|
L
¢
.
(M7867)
k——————”'ul—-—-———fl

k—'—-- %" "X » ———-—*

REMOTE -SYNCHRONQOUS MODEM CONNECTIONS ¢(SYSTEM TO TERMINAL)
.

y/4

WD‘!’-’

m—a

OUP11-DA L:#}D—-S

(M7867)

“'-‘

5—-

VT2

mw
¥

MCO-2
Wil
Maln
9

SRS SaS L

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LOCAL SYNCHRONOUS NULL MODEM CONNECTION (SYSTEfi TO SYSTEM)

LOCAL SYNCHRONOUS NULL MODEM CONNECTION (SYSTEM TO TERMINAL)

SHOROOUS mn Q. inlmaToR

DUP11-DA
(17867 )

k
'\

0 . v»

FWDADGUS (00EN €. InTNaTOR

Hfl:-:l DUP11-DA
(MN7867)

DUP11-DA
L:I}H '
(M7867)
L
'\

Voo

nai-e

U D i}—%—
»* m-—————-—*

SYNCHRONOUS LIMITED DISTANCE ADAPTERS (SHORT HAUL
) st srstmct tasue
on sexr o

COMM
comnt
LINK S5 INK

V/A

<
0
=
Ve
H‘%D—;q}
cnv-,uf'-gm
i:]—-“—{]

DUP11-DA

| b
stLL PROVLIDED

(M7867)

r
Figure 2-3

» ""'"'"—’l

REV

RCV

XMIT

sf'

v
Hfl'_———J
DUP1Y 1-DA 2\
(M7867)

“‘_—’l

KS10 Synchronous Communications Lines

2-6

[vr

V162

MASSBUS Cabling

Table 2-2

AVAILABLE

LENGTH

METERS

FEET

4.5

7.5

0.6/0.75

2/2.5

AMP %IF)

4.5

BCO6S (AMP ZIF toO

FROM

CABLE

CPU

RP06

BCO6S

(AMP ZIF to

AMP ZIF)

CPU

RMO 3

BCO6S (AMP ZIF to
AMP ZIF)

RP06

BC06S

(AMP ZIF to

AMP ZIF)

RMO 3

RP06

RMO 3

BCO6S

AMP

(AMP ZIF to

Z1IF)

|
¥

CPU

TM02/TM03

BCO06S

(AMP ZIF to

AMP ZIF)

4.5

Device Cabling

Table 2-3

FROM

CABLE

CPU

LPO05/LP14

7011426

TU45

TUA4S5

METERS

FEET

7.5

25%

100

BCO6R (BERG to
BERG-cabled

TU45

LENGTH

(AMP ZIF to

Winchester)

TM02/7M;1/3

AVAILABLE

internally)

1.8

BCO6R (BERG to BERG)

NOTE

asterisk

(*)

denotes

standard

the

length that will be provided if no cable
information is provided 60 days prior to
scheduled shipment.

2.4

PRIMARY POWER (AC)

Primary power

specifications

for

KS10

system

provided on data sheets in Subsection 2-5.

components

are

Refer to Section 1

(Subsections 1-7 - 1-8) of the DECSYSTEM-20 Site Preparation Guide
for the following information:

Definition of data
leakage current, etc.)

sheet

parameters

(surge

current,

Description of power

Phase

balancing,

regulation

systems.

grounding,

and

service

plugs

specified

outlet

requirements.

Description
sheets)

2.5

OPTION

This

subsection

for

receptacles

KS10

and

(on

data

various

KS10

system components.

DATA SHEETS

contains

system components.
sequence

option

The data

sheets

by device designations

LA36

LPO5

LPl4

KS10-AA/AB Processor

RMO3

RPO06

TU45A

(Master)

TUASA

(Slave)

data

-7

sheets

for

are arranged

follows:

the

in alphanumeric

LA36

DECwriter 1 TERMINAL

MECHANICAL

l Mounting
Weight
‘ Code
| 46.4 kg
f—vE
| 1021bs
|

Depth

Width

Height

61 cm
24 in

70 cm
27.5n

B5cm
33.5in

Cab Type
if Used
VE

Skud
Type
86.4cm »1282c¢m
247 X 501727

POWER (AC)

Curation
1,2 cycie
1.2 cycle 1

Current
60 Amps
30 Amps

Phasels) | Current (RMS)
3 Amps
1
1.5 Amps
|

Low | Nom | Hioh + Tolerance
g0 {115 | 132 ;60Hz 1
180 1230 | 264 1 50Hz=1

Surge

Steady State

Frequency

AC Vo!taAge

POWER (AC)

Interrupt
Tolerance
(Max)

L eakage
Current
(Max)

. PWR Cord
1
Conn
| PWER Cord
Type
Watts | KVA | Length
i

Heat

Dissipation

309 g ca, hr

1220 Bra e

NEMA =

0.107 mA

Rate of Change
Temp- | Rel. Humid.

Air Volume
Inle?

0.35 [ 7.4 m

360

L5 30¢

i 3 it

ENVIRONMENTAL (DEVICE)

Temperature
Storage
Ojperating

- Relative Humidhity
| Operating Storage

)
.
7". C/he
¥©* 10 40" C | -40" 10 66" C| Jo=—0Fw | 0-95% |12"
Fhar
57T > "t

53 10 104° F| 40 10 151°F Ze --f&f()

2%/hr

N
100 Cr

ENVIRONMENTAL (MEDIA)

Rate of Change

Relative Humidity

Temperature

Temp

Stotage
Operating
20-80% | 20 -8C%
;

Storage
Operating
15 1032°C | 15710327 C
59°1090° F | 597 t0 90" ¥

MAXIMUM CABLE LENSTH AND TYPE(S)

Memaory
NCA l*

Masshus
NA

1'0 Bus
.
NIA
=
—
T
it ——
o A
e

o A

LASO

2-19

\
‘
|

Device
3m
9 it

} Ret. Humid.
!
|

{
|
\

Otiher
N'A

LPCE-V.W

LINE PRINTER

MECHANICAL

Mounting
Code

E6cm ||

84 cmn

112 cm
44 5in

155 kg
340 e

Width

Height

Weight

,1 Catr Type t Skide |
Depth | HUsedVE || 33 Typ
x 40.1/2"

! 26 in

33i

POWER (AC)

dy Stat(RMeS)
uencey Phase(s) ‘| Stea
Freqranc
ageHigh { Tole
AC| Volt
Current
Low Nom |
s
137 | 6050 HzHz =+ 11 l 1 4.52.3 Amp
115 | 265
a0180 230
Amps
POWER (AC)

Interrupt

Heat

Tolerance

Surgetion "‘
Dura
1.2 cyciz ‘
l 1/2 cycle

\ PWR Corc

Leakage

PWR Cord | - Conn

I Watts KVA | Length “ Type

Dissipation

{Max)

Surgeent
Curr
s
1¢5 Amp
Amgs

E 525 | 0.525| 4.0m

416 kg cal/hr

‘\ NENA =

Current

{(Max)

551 mA

ENVIRONMENTAL (DEVICE)

of Change
Relative Hunudity \ Rate
Operating ‘ Storage j__ Temp ‘ Rel. Humid.

—

Storaye

Temperature

| Operating

Air Volume

inlet

300 CFN.

‘'{1 2¢2 hr
\Fl 30 - 90" | 5~ 95% \ 127 C.hr
C
u
twb
|-18
C
8
103
107
F'hr
15[)" to 100° Fl 0" 1o 150
ENVIRONMENTAL (MEDIA)

of Change
Relative Humdityage ‘ TemRate
Rel. Humi!.
p
Stor
Operating ‘ Storage l! Operating
‘
45%
‘

Temperature

24° C

\ 75° F

| 75" F

Memory ‘
N/A

45%

\ 24°C

MAXIMUM CABLE LENGTH AND TYPE(S)

1/0 Bus

N/A

Massbus
N/A

LFOG-V A

2-//¢

Device ' E

30 m

100 f1

Othar
N/A

LP14-CD

LINE

PFINTER

MECHANICAL

Mounting

70 cm

864 cm X 1:-35:‘;‘4

Surge

Type

47 XK 5517 _1

)30

33in

45 in

435 1b

84 cm

112cm

198 kg

Skid

It Used

Depth

Wiith

Heiaht

Weight

Code

Cab Type

POWER (AC)

;

Steady State

Freguency

AC Voliage

Phase(s) | Current (RAIS)
7A
1
35A
1

Low | Nom | High { Tol2rance
60 Hz = i
115 | 125
100
50 Hz + 1
240
|
230
200

Duration
1/2 cycie
T2 eyci2

Current
140 A
70 A

;

POWER {AC)

Interrupt

] PWR Cord -

Heat

Tolerance

Watts

Dissipation

(Max)

|r gy

MOkocalhr
2830 Btu.'hr

5 rmis

2615

KVA

Conn

PWR Cord ;

1y NEUS
| 370
|ggas
L5 15P
12 {1
8/
[

0.394 mA

Current
(Max)

Type

Lengih

Leakage

ENVIRONMENTAL (DEVICE)

Qelative Humadhity

Temperature

T
10°038°C |0 150 C | 4r grn

50° 10 100 F| 18° 1066 F | 2990

fiate ot Change

Air Voiume

)

Temp:

' Operating | Storage

Storage

Qirrating !

7Ch

| Rel. Humd. 1
|

e 0 o

inles

39 ¢

;

ENVIRONMENTAL {(MEDIA)

Operating
24 C

757 F

Storage

Operating

24" C

45%

torage

Temp

Rel. Humud.

co-

25" F

Rate of Channe

Relative Humidity

Temperature

45%

MAXIMUM CABLE LENGTH AND TYPE(S)

Memory

1/0 Bus

Massbus

/
N/A

A
N, A

N/A

Device

v
|

LP14CD

2=/ 2.

30m
t
100

Other
)’
NUA

}

S 1= ARt

MECHANICAL

f Maourniting
Code
FS

Weight
262 kg

30 in

27 in

60 in

590 1lbs

Depth
76 cm

Width
69 cm

Height
152 cm

Cab Type
if Used
H9502H-7

Skirl
Type
N/A

POWER (AC)

Frequency

AC Voltage

Steady State

Surge

9.90 Amps
4.95 Amps

25 Bmps
12.5 Amps

6 cycles
6 cycles

PWR Cord
Conn
Type

Leakage
Current
(Max)

Phase(s) | Current (lRMS)

Low | Nom | High | Tolerance

1
1

126 60 Hz + 1
104 ! 115
207 i 230 | 253 | 50 Mz + 7

Current

Duration

POWER (AC)

| Intecupt
Toletance
{Max)

Heat

Dissipation

Length

NEMA #

4.93 ma

Rate of Change
Rel. Humid.
Temp
2%/hr
7 C/hr

Air Volume
Iniet
1100 CFM

15 ft

3648 BTU/hr

KVA

PWR Cord

1070 | 1.14 | 4.5 m

9208%ka cal/hr |

16 ms

i
1
§ Wat s

L5-30P

ENVIRONMENTAL (DEVICE)

Temperature
Storage
Operating
15 to 32C | =40 to 6AC

59 to 90F | -40 to 151F

Relative Humidity
Operating | Storage
0-95%
20-80%

12 F/hr

ENVIRONMENTAL (MEDIA)

Rate of Change

Relative Humidity

Temperature

Operating

Storage

Operating

Storage

Temp

Rel. Humid.

N/A

MAXIMUM CABLE LENGTH AND TYPE(S)
|

;

Niemory

MNAA

1/0.Bus

‘

N, A

Massbus

Taal A-L

See Nete #4
2-13

:
Device

Other

Tt 2-3| VA (/hfm;u;’)

Sece Nowemd#d] Unibus—boo—Ney

_ il |

MECHANICAL
T

Moty

Code

Weight

;

Cab Type

Skid

if Used

Type

Height

Width

Depth

193.5 kg

99 cm

75 cm

83.8 cm

HO9691

430

39 in

29.5 in

(modified)

1bs

POWER (AC)

AC Voltage

L_Lo LNom
|

102 1115

213 %23‘:

{

Frequency

Steady State

High | Tolerance
123

Phase(s) | Current IRMS)

60 Hz +.6

257

50 Hz +.5

6.4 Amps

Surge

Current

Duration

30 Amps

3.1 Amps

14 seconds

23 Amps

14 seconds

PWR Cord

L.eakage

PWR Cord

Conn

Current

Length

Type

(Max)

3.7 m

NEMA #

/218 mar

POWER (AC)

Interrupt
Tolerance

Heat

(Max}

Dissipation

Watts

504 kg- cal/hr

650

2000 BTU/hr

KVA
0.73

12 ft

15-15P

ENVIRONMENTAL (DEVICE)

Temperature

Operating
15

Helative Humidity

Storage

32C | -40

50 to 90F | =40 to

Rate of Chanqge

| Operating | Storage
1

70C ' 20-80%

Temp

5-95%

7 C/hr

1581i

Air Volume

Rel. Humid,

iniet

2%/hr

12 F/hr

ENVIRONMENTAL (MEDIA)

[

Cemperature
Operiting

Relative Humidity

Storage

Operating

Rate of Change

Storage

Temp

Rel. Humid.

MAXIMUM CABLE LENGTH AND TYPE(S)
Memorny

170 Bus

NOA
L

Massbus

N, ‘A
L

8.8 m

(total

160

£t

svstem)

Device

Other

N/A

(TEF i

Mi:CHANICAL
,

CIN‘!.'

Mountinn

}

Weight

Heght

Vaudth

Crepth

ST kg

119 cm

31 win

H1 cm

H00 1bs

a7 an

33 1in

Cab Type

Skid

It Used

Type

12-19%(8-02

32 in

POWLR (AC)

L 0tagn

Frequency

Steady State

Toleranee
;

2
A

P27

ESSIR

rhd

| Cucront (fi%MS)

L_j_’hf*s'*‘fl

{

,'““"y'n .':

)

Y N

Ampr

Suige

Surge

Curremnt

Duritio:s

Amps

172

/2 cyele

POWEL R {AC)

iy
.

R
At

Tere

‘

Aok
e

‘

‘
Pl

e ——

SATE DA

LM Cond
i

| Cact

MW.WT

}
2

Leakan-

ORTHY

*
Currant

Tupe

{Max)

e m —p e

— —1

———

VR Co:d

..__..L..

At
s ol
ks

e
s

4 J

o Ny

et
i+ . s e,
e e e, e

ECVIRONMENTAL (DLVICE)
é

;

’-'m;wmtum

}

Relative Ewnumw

Rate ot Chunge

YT T
T e

i» Oner:.t:
S l

Sturaqge

i‘) '“'| I S B

Wt or(10

)

Operating } Stoiage

Temp

|
JO0%=00 ’P
=)0

7o/ hre | D hre

‘

A Volume
.

Rel. Humid.

Inlet

550 (I'M

12 /hr
»

ENVIRONMENTAL (MEDIA)
!'l npecature
(){)i I )!»nq
Foommmmes

m—

Sturage

-—f—-—

IR NS

Relative Hunndaty

ot
i)

Rate of Change

Operating

Storage

Temp

BRI

204 -R09

Rel. Humid.

Cr/hr

[REVID
\

Goet——
e
s
oo

ol
o
—

rvN e '}

REEAXIMUIN CASEE

'y [RITEN

LENGYH AND TYPE(S)
e

M. :\filmx

Ul’\me'

Otha

Sy |
A —i)

/ . ‘/,'

- 24

-y,

- W/}

—

M/A

TU45A-E
MAGNETIC TAPE SYSTEM

MECHANICAL

Mouiiting

Code
FS
A

Weight

Height

290 ky

152 ¢

63 cm

640 1

76 cm

60 N

27 in

30 in

Widih

Cab Type

Skid

If Used

Type

Depth

HS$502

N/A

POWER (AC)

AC Voltage

Frequency

Steady State

Low | Nom | High | Tolerance

103

151126

267 | 230

263

Phase(s) | Current (RMS)

{

Surge

Current

Duraticn

60 Hz + 1

50 Hz + 1

6.8 Amps

3.4 Apip,

4 A mpe,

7 A5p5

1/2 cycle
1/2 cycle

POWER {AC)

interiunt

Tolerance

Heat

PWR Cord

(Max}

g.’;'fl* Dissipateomn

L aa 2o NC R HEY

Natts

256erG 1

} 720

KVA

Length

45m

PWR Cord

Leakage

Conn

Current

Type

(M:x)

NEMA
=

15 11

L5 30p

316 mA

ENVIRONMENTAL (DEVICE)

Temperature

Operating
16

10 32°C
.

60 1090 F

Refative Humidity

Storage

Rate ot Change

i Opezrating | Storage

Temp

'-40%t0
60
.

,
.
20807,

14070 140 F

U ET

7e
Chir

5-.gK7

g gy

Air Volume

] Rel. Humid.

Inlet
.

SO0 cfm

ENVIRONMENTAL (MEDIA]
Temperature
Operating

60 0 90°F

Relative Humidity

Rate of Change

Storaye

QOperating

Storage

Temp

| -40"t0140°F |

20-80%

5-95"

Rel. Humd.

N A

MAXIMUM CABLE LENGTH AND TYPES)

Memory
(

1O Bus

‘[

]

Masshus

Device

30 m

1.8 m

100 f

6
i

T Uana l‘

= -/¢

RC0GH

Other
,

N-A

TU45A-E

MAGNETIC TAPE SYST

Mounting ‘ | Weight

Code

Heightcm

MECHANICAL

Widcmth

FS \ 60010 | 60in
¥

76 cm

30 in

9502 \ N/A i

Steady State “¢

ge ‘\
Surge | sur
Duration
Current

27 in

152

272 kg

Type ‘| SkiTypde |
—lr Cab
Depth | 1f Used

POWER {AC)

Frequency {

Tolerance Phasc{s) | Curren4.6t Am(RMpsS) \
Low | Nom
125o 50 Hz Hz o£
\
100
ps
Am
23
\
\ 207

95 AuwiAfrsP k 1/2172 cyccyciele

POWER (AC)

‘

{(Max!

Dissipation
385 kg cal’nr

Type
l Watts KVA Length
MA =
m “' NE
‘s 450 0.53 45
15it
15
| 30P
—__

_.———————T_————
______._—-—-—-———'—‘—-"—

1540 Bru'hr I

L,,.,
Operating

16" w0 32 C
|—

40710 60" C

Rate of Change

Temp i Rel. Humid.
7° Citwr

Storage

Operatmg

Storage

107 1o 140 F! 0-80 \ S

127 Fihr

{nlet

500 cfm

Massbus
1/O Bus "
m
\

—

|
Rel. Humid.

59 \ ve \ "o

‘l

MAXIMUNM CABLE LENGTH AND TYPE(S)

Memaory

Air Volume

[

Storage

-40°

' {‘1 OperatRelingative HunudiStotyrage ;Tk TempRete of Change

Temperature

Qperating

urrent

ENVIRONMENTAL (MEDIA)

ti 30 g —Ag 1{(; giok SR
\1360 Io

‘

Leakage

ENVIRONMENTAL (DEVICE)

Relative Humidity

Temperature

Conn

PWR Cord ‘\

‘

PWR Cord

H interrupt ‘ Heat
. Tolerance |

(‘

100 t1

103m1

13) BCOBR

TU4DAE
2-77

[

Device T

oOthmer |

NU/ A

e e

e A

T T

INSTALLATION

SECTION

supplied.

OPERATION/PROGRAMMING

SECTION 4

4,1

CONTROLS AND INDICATORS

The KS10 switch and indicator panel is shown in Figure 4-1.

are

five

which

three

switches,

for powering-up,

provide

resetting, and bootstrapping the system.

There

The fourth switch serves

as an interlock to prevent an inadvertent reset or bootstrap by
the

once

operator

controls

the

remote
listed

system

diagnosis

The

in operation.

link

the

in Table 4-1.

STATE

FAULT

POWER

®©

REM)TE

ROOT

LOrK

H»

DISARLE

:,L—«-f

PENTECT

&}J [Vatmny
:

Figure 4-1

POWER

REMOTE DIAGNOSIS

ENARLE

fll

KS10 Switch and Indicator Panel
97

last

system.

functions are

the

switch

Switch

KS10 Switch Functions

Table 4-1

Switch

Function

POWER

Turns

861

(Causes

on/off,

power

control

power

apply/remove line power to the CPU and BAl1lK pober
supplies.)

RESET

Resets

all

System

components

system.

Performs

KS10

the

(including

8080

console hardware)

BOOT

Bootstraps

the

same

function

console command.

LOCK

Electrically interlocks the RESET and BOOT switches so

that they have no effect.
from

switching

the

Also prevents the operator
'am ustr ma

CTY,/ to

mode

console

(disables

control-backslash command).

REMOTE

Three position key operated switch that controls access

DIAGNOSIS

by the remote diagnosis (KLINIK)

line.

DISABLE position - Prevents access to the system.

PROTECT position - Allow

access

the

system

with

the

system

password.

ENABLE position

- Allows

free

access

without password protection.

4-0

The panel

other

also

has

four

indicators.

One

indicates power-on.

The

three, which are under control of the 8080 console program,

indicate the syétem's run state, when a system fault has been
detected, and when the system's remote diagnosis line is enabled.
Indicator functions are detailed in Table 4-2.

KS10 Indicator Functions

Table 4-2

Indicator

Function

POWER

Lights when dc power

REMOTE

Lights when KLINIK line
password.

(REMOTE

is on.

(-5 V and +12 V)

is enabled with }21: without

DIAGNOSIS

switchA in

ENABLE

PROTECT position.)

FAULT

STATE

Lights

for

the

following

KS10 bus parity error

UBA parity

Memory parity error

4.,

Data path parity

Console parity error

CRA

CRM parity error

Memory

Boot command

5*5"5"*

parity

Indicator
system

error

blinks

"keep-alive"

error

fails

KS10

monitor

error

refresh

Lights, when

conditions:

to start machine.

microcode

loaded

on,

has

second
been

loaded

-3

second

and

dialogue with console.

and

running.

off)

when

maintaining

4.2

KS10 DIFFERENCES

(KS10 vs KL10)

For

the

purpose

this

and

programming

are

best described

are

only

differences

few

uses the same operating
modifications.

The

KL10 do exist,

however.

document,

following

Public Mode

Because

TOPS20

does

not

the

KS10.

machine

4.2.2

Addressing

the

aspects

relation

instruction

differences

public

support

KS10

operation

the KL10.

set

and

(TOPSZO)

There

the

KS10

with minor

between

the

KS10

and

has

not

been

the

mode,

instructions

All

system as the KL10

4.2.1

implemented

some

behave

concealed mode.

Only section 0 addressing is implemented in the KS10; that is,
like the KL10-B
words.

(KL10-PA processor), virtual memory space is 256 K

Extended

implemented
supported

the

addressing,

XPCW,

It does

XJEN,

4.2.3

Interrupt Handling
Priority

interrupt

(KL10-PA processor)

Only

the

support

operation

256

words

is not currently

the model

the

instructions

same

the

KL1l0-B

except for the following:

JSR

XPCW

interrupt instruction;
executed

and SFM.

XJRSTF,

KS10

sections

(KL10-PV processor),

KL10-E

by the KS10.

result

instruction

allowed

that is, as the first instruction
of

interrupt.

instruction will halt the processor
4-4

Any

other

(Subsection 4.4).

the dispatch
KL10-8,

the

(i.e.,

which

dispatches

location

EPT

instrucion

the

address,

the

KS10

determined

the

UBA number

uses

this

word

then

first

specified

(EPT +

arn

100

the

executes

and

references

ags

Unlike

interrupt vector).

function

1is

devices

for

implemented

function

interrupt

only

The

the

by
EPT

vector

location

+ CONTROLLER #).

exec—-virtual

address

Lod

table and executes the instruction at TABLE + VECTQRA@)
The

levels

two

implements

KS10

higher

can

have

level

(1-7)

assigned

devices,

one

PIA

other.

The

interrupting

high level PIA

levels

and

(Unibus)

I/0

for

of PIA

the

than

priority
to

Unibus

devices

is set by

The

(bits 30-32 of UBA status register).

PT level (1-7) for devices interruptidg on RBR levels 5

Table

the

and

UBA

status

4-2

lists

set

the

hard-wired

K510

I/0

also

1indicates

ass¢clate d

with

low

PIA

lesvel

(bits

33-35

rejistert.

wvarious

sys.en,

each

interrupt

(Unibus)

device.

devices

which

PIA,

vectors

in
high

and

fully
o¢r

low

levels

for

configured
level,

|is

I/0 (Unibus) Device Vectors and BR Levels

Table 4-3

Interrupt

Device

UBA #

PIA

Vector

RH11 #1 (RPO06)

254

RH11 #3 (TUA45)

224

LP20 #1

750

DZ11 #1

340

DZ11 #2

350

DZ11 #3

360

DZ11 #4

370

KMC11 #1

540

DUP11 #1

570

DUP11 #2

600

4.2.4

Paging

Both TOPS10 and TOPS20 paging are implemented in the KS10.

paging mode

1is

selected by bit

(Subsection 4.3.1.9).

9-¢

The

in the WREBR instruction

4.2.5

KS10

The KS10 has

Instruction Set

same

the

(i.e.,

instruction set as the KL10-B

Model

PA Processor-section 0 addressing only) except for the following:

The

single-precision

instructions

facilitate

that

floating

rounding)

(without

software

point

double-precision

operations are not supported on the KS10 and will trap as
MUUOs.

These

are:

UFA

(Unnormalized Floating Add)

DFN

(Double Floating Negate)

FADL

(Floating Add Long)

FSBL

(Floating Subtract Long)

FMPL

(Floating Multiply Long)

FDVL

(Floating Divide Long)

The KS10 checks several MBZ

set

(must be zero)

not

are

that

fields in the

instrucion

KL10-B.

Any non zero fields cause an MUUO trap.

In KI paging mode,

was

the

if a MAP instruction is done to a page

with A = 0 in the page table entry,
address

checked

extended

given.

The

KL10

the KS10 returns the
returns

=zero

address.

All KL10 I/O instructions have been replaced by a new I1/0

instruction

set

for

the

7-7

KS10.

Because

the

KS10

I/O

format

been

has

specify

not

instructions do

changed

a device

conform

instruction format of opcode, AC,

The KS10 I/O

instructions

code,

instruction

the

basic

and effective address.

are described

in Subsection

4.3.

NOTE

Appendix A shows KS10 word formats and
lists

KS10

all

betically

instructions

(by mnemonic)

(by opcode).

alpha-

and numerically

algebraic

representa-

tion of the function performed by each
instruction is also given.

4.3

KS10 I/0 INSTRUCTIONS

KS10 I/0 instructions have the same basic format as the rest of

the KS10 instruction set.

(Format is shown in Figure 4-2.)

instruction op-codes are in the range 700 - 777 (octal).
assignments are shown in Table 4-4

1/0

Op-code

08 09

12 13 14

0.C.=700g-777g

AC*

O.C.

=OPCODE (TABLE 4. 4)

= ACCUMULATOR

= INDIRECT ADDRESSING BIT

= INDEX REGISTER

= ADDRESS

* NOTE: AC FIELD USED AS OP-CODE EXTENSION FOR

APR 1/0 INSTRUCTIONS (TABLE 4-5).
M 0228

Figure 4-2

I1/0

Instruction Format

Table 4-4

I/0 Instruction Op Codes

(Octal)

700

APRO

APR1

APR2

UMOVE

UMOVEM

710

TIOE

TION

RDIO

WRIO

BSIO

BCIO

720

TIOEB

TIONB

RDIOB

WRIOB

BSIOB

BCIOB

730

740

750

760

1m0

4-1

4.3.1

The

Internal

internal

‘the AC

4-5.

field

(APR)

I/0

Instructions

instructions

extension

(APR0-2;

the

op code

codes

700

use

in Table

For example, the RDEBR instruction (an APR instruction with
format

given

I/0

702)

indicated

op code = 701 ) is specified by an AC value of 24 .
bit

for

the

various

in Subsections

4.3.1.1

instructions

Table

4-5

are

KS10
-

internal

4.3.1.22.

I/0

Function and

instructions

Any similarities

are

to KL10

noted.

Field Assignments

(Octal)

700

701

702

APRID

RDSPB

" RDUBR

RDCSB

CLRPT

RDPUR

WRUBR

RDCSTM

WRAPR

WREBR

RDTIME

RDAPR

RDEBR

RDINT

RDHSB

WRSPB

WRCSB

WRPUR

WRCSTM

WRPI

WRTIME

RDPI

WRINT

WRHSB

for APR I/0O

Instructions

4.3.1.1

APRID

function

microcode

version

the

is stored in E.

(70000)

APRID

The

APRID

instruction

number

and

CPU

instruction,

for

the

serial

KL10,

number.

similar

reads
The

the

KS10

information

Bit format is shown in Figure 4-3.

APRID (70000)

MICROCODE OPTIONS

LH(E}

RH(E) | HROWR OPTIONS
4

2
i

MICROCODE VERSION

PROCESSOR SERIAL NUMBER
4

08 ; 09

BIT(S)

FUNCTION

0.8
17
18-20

RESERVED FOR MICROCOOE VERSION
MICROCODE VERSION NUMBER

[}

4
i

Efl

HARDWARE OPTIONS (BiTS CURRENTLY = 0)

PROCESSOR SERIAL NUMBER,

2138

MR-0229

Figure

4.3.1.2

used

WRAPR

to control

instruction used

4-3

(70020)

APRID

Instruction

- WRAPR is

the processor.
in the KL10.

immediate mode

instruction

is analogous to the CONO APR

Bit format is shown in Figure 4-4.

WRAPR (70020)
18

‘

SELECTED FLAGS
EN DIS CLR

INT

SET

SELECT FLAG

8080 |pWRF NXM HERR SERR TIM

INT
8080jREQ |

Pl LEVLEL
4

FUNCTION

BIT(S)

ENAGLE CONDITIONS SELECTED BY BITS 26-31 TO CAUSE
iNTERRUPTS.

DISABLE INTE RRUPTS FOR CONDITIONS SELECTED BY

BITS 265 31.
22

CLEAR FLAGS INDICATED BY BITS 26-31,

SET FLAGS INDICATED BY BITS 26-31.

INT£RAUPT 5080 CONSOLE

POWER FAIL

NON-EXISTENT MEMORY ERROR

HARD MEMOHY ERROR (CANNOT BE CORRECYED BY ECC)

SOFT MEMORY ERROR (CORRECT DATA PLACED ON 3BUS)

INTERAL TIMER

8080 CONSOLE

GENERATE INTERRUPT REQUEST

33-35

PIA

-»

MR-Q230

Figave

4-4

WRAPR

2
H-l

Instruction

4.3.1.3

RDAPR

KL10.

Bit

(70024)

corresponds

format

shown

The

RDAPR

the
in

CONI

instruction

APR

stores

instruction

APR

used

status

the

Figure 4-5.

RDAPR (70024)

)
)

‘

PWRF NXM HERR SERR, TIM

8IT{S)

HARD| SOFT|

PWR

8080

TIM

INT

PI LEVEL
1

FUNCTION

POWER FAIL ENABLED
NON-EXISTENT MEMORY ERROR ENABLED

SOFT MEMORY ERROR INTERRUPT ENABLED

HARD MEMORY ERROR INTERRUPT ENABLED

INTERVAL TIMER ENABLED

8080 CONSOLE INTERRUPT ENABLED

POWER FA!L ERROR

. 27

NON-EXISTENT
MEMORY ERROR

. 28

HARD MEMORY ERROR {CANNOT BE CORRECTED BY ECC).

29
30

SOFT MEMORY ERR (CORRECT DATA PLACED ON BUS)
INTERVAL TIMER DONE

31
32

FaiL | Nxm | ERR | ERR |DONE] 8080 | REQ | 4

08
09

8080 CONSOLE INTERRUPT

33.35
* NOTE.

ENABLED FLAGS

LHIE

o7 | o8, 09

INTERRUPT REQUESTED

PIA

PAGE FAIL OCCURS IF ERROR IS RESULT OF CPU MEMORY

REQUEST. NXM FLAG ALSO SETS IN UNIBUS DEVICE IF
ERROR IS RESULT OF UNIBUS NPR REQUEST.

ML Q23

Figure

4-5

RDAPR

41z

Instruction

4.3.1.4

KL10

WRPI

CONO

parity)

are

(70060)

The

instruction

not

implemented.

WRPI

instruction

except
Bit

that

bits

format

identical

18-20

shown

DROP CLR

OFFLON

BIT(S)

SELECT CHANNEL

even

2 ,

REQ TURN CHAN|TURN SYS

INTLSYSllNTlONlON

26 , 27

23 , 24

(write

the

in Figure 4-6.

WRPI (70060)
18

FUNCTION
DROP PROGRAM REQUESTS ON SELECTED

CHANNELS.

CLEAR PI SYSTEM

INITIATE INTERRUPTS ON THE SELECTED

CHANNELS.

TURN ON THE SELECTEO CHANNELS.
TURN OFF THE SELECTED CHANNELS.

25
26

DEACTIVATE THE Pl SYSTEM,
ACTIVATE THE PI SYSTEM.

27
28

29.35

SELECT CHANNELS FOR BITS 22, 24, 26" AND 26.
MR 0232

Figure 4-6

4.3.1.5

RDPI

KL10

CONI

(write

even

Figure

4-7.

(70064)

WRPI Instruction

- The RDPI insstruction is

instruction

parity

except

not

that

bits

implemented).

4= 14

18-20

Bit

identical
read

format

to the
status

shown

RDPI (70064)
N

PROGRAM REQUESTS

LHIL)

[

20 . n

L 27

Pi IN PROGRESS

RHIE)

, 2

, 3

1t 4.2,

{

SYs

, 4,5, 6

4,8,
6,7

CHANNELS ON

7 |JON]1

BITIS)

FUNCTION

1.17

PROGRAM REQUESTS ON CHANNELS 1.7

, 6 2,3,4, 5,6 6,7

INTERRUPTS HOLDING (IN PROGRESS) ON CHANNELS 1-7
ON
PI SYSTEM

n.27
28

ACTIVE CHANNELS 1.7

2935

MA-0233

RDPI Instruction

Figure 4-7

4.3.1.6

RDUBR

the

(UBR)

KL10
and

exactly

- The

PAG

stores

(Subsection

Bit

DATAI

the

directly

(70104)

the

same

format

shown

which

similar

reads

the

user

base

The

word

stored

used

information

4.3.1.8).

instruction,

(by a WRUBR),

format

RDUBR

order

bits 0

and

Figure

4-8.

the

WRUBR

to allow

the

to ONE

are

set

instruction

word

in the

used

result.

RDUBR (70104}

LH{E)

05, 06

|
L

08, 09

CURR AC BLK

PREV
AC BLK

11 12

RH{L)

USER BASE REGISTCH
'

BIT(S])

Figure

FUNCTION

CURRENT AC BLOCK

811

PREVIOUS AC BLOCK

2535

USER BASE BREGISTER

4-8

RDUBR

Instruction

MR-0234

4.3.1.7

CLRPT

KL10

CLRPT

the

There

and

instruction.

reference

Clearing

(70110)

only
the

one

USER mapping.

CLRPT

clears

the

entry

mapping

The

instruction

the

similar

page

table

to
so

the
that

word

will

cause.a

refill

cycle.

the

page

table

for

virtual

page.

information

for

format is

shown

Bit

hardware

Page

any

clears

Figure

both

the

EXEC

4-9.

CLRPT (70110)
18

VIRTUAL ADDRESS TOCLEAR IN HARDWARE PAGE TABLE

18,

23,24

25,

29 ,

BIT(S}

FUNCTION

18 3%

VIRTUAL ADDRESS TO CLEAR IN

32,

HARDWARE PAGE TABLE.
MRA.0235

Figure 4-9

4.3.1.8
to

the

Bit

WRUBR
KL10

(70114)

DATAO

format

CLRPT Instruction

PAG

The

WRUBR

instruction,

shown

Figure

instruction,
loads

4-10.

the

UBR

which

with

the

similar
word

WRUBR (70114)

H(E)

RHI(E)

4 , 2 41

2 4,1

]

25 , 26 , 27 , 28, 2%

PREV AC OLK

CURR AC BLK

)

U8R

05 . 06

USER BASE REGISTER

s _

u | 3 |

3 ;32

BIT(S)

FUNCTION

LOAD AC BLOCK NUMBERS

68
9.11

CURRENT AC BLOCK
PREVIOUS AC BLOCK

LOAD UBR

USER BASE REGISTER (PHYSICAL PAGE NUMBER

25.35

OF UPT.)

MRA-0236

WRUBR Instruction

Figure 4-10

4.3.1.9

WREBR

(70120)

The

WREBR

instruction

1loads

the:

It is similar in function

executive base register (EBR) from E.

Bit format is shown in Figure

to the KL10 CONO PAG instruction.
4-11.

WREBR (70120)
T

23,

PAGE|

EXEC BASE REGISTER

KL10 |TRAP

BIT(S)

, 26 , 27,62

6,3

31,32

3, 64

FUNCTION

KL 10 PAGING MODE

TRAP (AND PAGING) ENABLE

25.35

EXECUTIVE BASE REGISTER (PHYSICAL
PAGE NUMBER
OF EPT)
MR-0237

Figure 4-11

WREBR

4-17

Instruction

4.3.1.10
into

RDEBR

the

right

instruction.

(70124)

half

Bit

format

The
It

RDEBR

shown

instruction

comparable
in

the

reads

the

EBR

KL10

CONI

PAG

Figure 4-12.

ROEBR (70124)
18

AMLE)

KL10|TRAP

PAGE|

BIT(S)
2

Figure

pointer

format

shown

.
1

1. 28 4

30,3, R,

33,

]

KL10 PAGING MODE

4-12

(SPT)

.
]

TRAP {AND PAGING) ENABLE
EXECUTIVE BASE REGISTER

RDEBR

RDSPB. (70200)
table

FUNCTION

22
25-36

4.3.1.11

EXEC BASE REGISTER

base

MR-0238

Instruction

- The RDSPB

instruction

reads the

stores

value

and

the

shared
E.

Bit

Figure 4-13.

RDSP8 (70200)

]

)

14,

LH(E)
1

)]

20,

2,023

RH(E)

“1‘5[“L‘77

]

SPT BASE REGISTER

)

24,25,

26,

27,

28,

BIT(S)

FUNCTION

1438

SPT (SHARED POINTER TABLE) BASE REGISTER

Figure

4-13

RDSPB

4-/8

Instruction

32,

33,

MR-0239

4.3.1.12

RDCSB

status

table

format

(70204)

(CST)

shown

base

The

RDCSB

and

instruction

stores

the

reads

value

the

core

Bit

Figure 4-14.

RDCS8 (70204)
00

csT

LH(E)

1
18

RHIENE

{

4,3.1.13
process

use

shown

CST BASE REGISTER
27

24,625 %

w9 , 20 21,22 ,23

BIT(S)

FUNCTION

1435

CST (CORE STATUS TABLE] BASE REGISTER

Figure

4-14

RDPUR
register

Figure

RDCSB

Instruction

(70210)

RDPUR

(PUR)

and

The

stores

the

)

]

3 432,63 6 34,6 »

MR-0240

instruction
value

)

]

reads

Bit

the

format

4-15,

RDPUR {70210}
"

LHIE)

PROCESS USE REGISTER

0, o1 02,03, 04,6 05,6 06,6076 086 00,10,6 M

6 12 1‘3_1"1 18,

18 17

PROCESS USE REGISTER
Rute)

;23

Figure

28,26

BIT(S)

FUNCTION

035

PUR (PROCESS USE REGISTER)

4-15

RDPUR

4-19

Instruction

33,

MR.024)

4.3.1.14

mask

RDCSTM

Figure

and

(70214)

-~ The

RDCSTM

stores

the value

instruction

in E.

reads

the

CST

Bit format is shown in

4-16.

RDCSTM (70214)

CST MASK REGISTER

()

! ¥

01 ,

]

18
%

23,

CST (CORE STATUS TABLE) MASK REGISTER
4-16

the

instruction

up-counts

30,31 32,633

0-35

RDTIME

the

FUNCTION

4.3.1.15

stores

BIT(S)

Figure

RDTIME

,2 ,27,2 ,

(70220)

double-word
4.096

RDCSTM

mHz.

for

THE

the

wvalue
Bit

CST MASK REGISTER
24,25

612,13, 14,615, 16

]

RHIE)

00,1

08,

05,6 06,07 ,

63,04

MR.-0242

Instruction

RDTIME

KL10.

instruction

reads

the

and

format

shown

similar

time

The

Figure

base

time

4-17.

and

base

RDTIME (70220)
00

)

IGH ORDER TIME BASE
HIGH

Cies | sion

01 102 | 03 | 04 ; 05 | 06 ;) 07 | 08 ; 09 } 10 , 11 4 12, 13, 14,
18

RH(ES]

15 , 16 4, 17

HIGH ORDER TIME BASE

131‘9L2°12’122i23124125126427123129130131132133134|35

8IT(S)

FUNCTION

SIGN BIT: 0 (+),
1 (-)

:
HIGH ORDER TIME BASE (MILLISECONDS)

1-35

00
LH(EN]

LOW ORDER TIME BASE

02,

18
AMIE)

L
03 ,

04 ,

05,

06 , 07

08,

09 ,

10,

,12

13,

LOW ORDER TIME BASE

18 , 19 , 20 ,

TIME BASE FRACTION

, 22 , 23 | 24

, 25

, 26

27 ,

BIT(S)

FUNCTION

SIGN BIT: 0{+),1 (-)

28,

20 ,

30 , 31

1.23

LOW ORDER TIME BASE (MILLISECONDS)

24.35

TIME BASE FRACTION

32 , 33 ,

34 , 35

MR-0243

4.3.1.16

value

in E.

Figure

4-17

RDTIME

RDINT

(70224)

- The

the

Bit

interval

format

timer

shown

Instruction

RDINT

period

instruction

reads

stores

and

the

current

the

value

in Figure 4-18.

RDINT (70224)

LH{E}

19
ANLE)

INTERVAL TIMER

23,

INTEARVAL TIMER

1w,

L 20, 1, 22, 2

BIT(S)

FUNCTION

0.23

INT_ERVAL TIMER PERIOD REGISTER (PERIQD = n MILLISECONDS]

MR 0244

Figure

4-18

FD;N?

Instruction

4.3.1.17
value

RDHSB

the

in Figure

halt

(70230)
status

The

block

RDHSB

address

1instruction

stores

Bit

format

14,

the

shown

4-19.

RDHSB (70230)

AMIE) | SIGN

LHIE)

HS8 ADDRESS
|

‘

4, 15, 16 , 17

" 00

HSB ADDRESS

1.1191 20121122123124_l25|26l27128129130l31132133134135
8ITIS)

FUNCTION

SIGN BIT = 0 = STORE HALT STATUS
SIGN BIT = 1 « DO NOT STORE HALT STATUS

= 0)
HSB8 (HALT STATUS BLOCK) ADDRESS (BIT 00

14.35

MA.-024%

Figure 4-19

WRSPB

4.3.1.18

RDHSB

- The

(70240)

base register from E.

Instruction

instruction

WRSPB

loads

the

SPT

Bit format is shown in Figure 4-20.

WRSPB (70240}

4,
SPY

LHIE)

RR(E)

)

SPT BASE REGISTER

, 5, 18,
14

1‘1‘.12012142212312412512612712.12’130'13‘L3213313‘L35
BITIS)

FUNCTION

14.35

SPT (SHARED POINTER TABLE) BASE REGISTER

Figure 4-20

WRSPB

4 -12-

Instruction

MR-0246

4.3.1.19
base

WRCSB

from

(70244)

The

WRCSB

format

Bit

instruction

shown

loads

Figure

4-21.

13.

the

CST

WRCSB (70244)

csT

LH(E!

)

w,15

16,17

RRE)

® 19

CST BASE REGISTER

2 23,24

25 2

FUNCTION

16-35

CST (CORE STATUS TABLE) BASE REGISTER

WRPUR

from

the

AGER

the

CST

entry

the

CST entry.

(Bit

BITIS)

Figure 4-21

4.3.1.20

27,28, 2 ,3

the

The

shown

left-most

with

MR.0247

WRCSB Instruction

(70250)

format

32 633, M K6 38

WRPUR

bits.

CST mask;

instruction

Figure

These
then

4-22.)

bits
the

are

entire

loads

The

PUR

cleared
PUR

the

PUR

contains

ANDing

ORed

with

WRPUR (70250)

CHES

PROCESS USE REGISTER

oolmlozloalu,osloalw,ocloo,m,11,12,13,14L1

RMIEl

PROCESS USE

igure

4-22

02,

28,

30,31,

FUNCTION

035

PUR (PROCESS USE REGISTER)
Instruction

4—;3

BIT(S)

WRPUR

32,3,

MR.0248

4.3.1.21

mask

for

WRCSTM

every

(70254)

from

the

bit

The

WRCSTM

The CST mask

AGER

and

instruction

one

the

CST

should

contain a

zero

other

bit

all

loads

positions.

Bit format is shown in Figure 4-23.

WRCSTM (70254)
00

‘

[

CST MASK REGISTER

H{E)

‘.
AH(E)

CST MASK REGISTER

"l‘glm121lnjzal2‘l”12‘l271“!”13013lnlnl
BIT(S)

FUNCTION

035

CST (CORE STATUS TABLE) MASK REGISTER

Figure

4-23 WRCSTM

4.3.1.22

WRTIME

(70260)

double-word

Figure 4-24.,)

and

MA.0249

Instruction

The

WRTIME

into

the

time

The Time Base

4-24

up-counts

instruction

base

(Bit

loads

format

at 4.096 mHz.

the

shown

LHiE+1 | sicn

RHEsT)

‘
4

(

1
1.1

00
Lheer | sion

RHIE)

| I

A
1

[

FUNCTION

SIGN BIT: 0 (+),1 (-)

1-35

HIGH ORDER TIME BASE (MILLISECONDS)

i
LOW ORDER TIME BASE

.23

}

4.3.1.23

interval

loaded

]

17 _
]

]

|
i

[

BITIS)

FUNCTION

SIGNBIT: 0 (+), 1 (-}

1.23

LOW ORDER TIME BASE (MILLISECONDS)

Figure 4-24 WRTIME

Instruction

WRINT

The

(70264)

period

determines

milliseconds.

Figure

}

timer

LOW GRDER TIME BASE
i

R |

8IT(S)

I
SR

)

]

HIGH ORDER TIME BASE

1
A

HIGH ORDER TIME BASE

Bit

WRINT

from E.

interval;
format

for

the

is,

)

MR.0250

instruction

The

that

]

1loads

the

binary number

(n)

the

(period)

interval

instruction

that

shown

4-25.

WRINT (70264)

‘M€l

INTEAVAL TIMER

02, 03, 04, 05, 08 07, 08 , 00,10, W ,12,13,
14 16, 16 1

18
RR{(E)

INTERVAL TIMER

WA
'

B R

8IT(S)

FUNCTION

0-23

INTERVAL TIMER PERIOD REGISTER (PERIOD = N MILLISECONDS)

Figure

4-25 WRINT

Instruction

R.0251

4.3.1.24

word

WRHSB

4.7.2).

subsequently be stored.

instruction loads

the halt

negative

word

the

- The WRHSB

address of

the

(70270)

the

signed

status block

(Subsection

no halt

status will

zero,

If the word is positive, the halt status

block (20 words) will be stored starting at the specified address.

the microcode

when

Initially,

loaded

status block address is set to a value of (+)

the

started,

and

376000.

halt

Bit format

for the WRHSB instruction is shown in Figure 4-26.

WRHSB (70270)

LH(E) | SIGN

13
RH{EI

;

w0 ¢

oW
HSB ADDRESS

HSB ADDRESS (8IT 00 = 0)

[

4 4 18 L 16 4 17

“

mlmlzo‘:njzz,n,ztlzslzolzszc.alaol:nlszlzal:ulas

BITs)

FUNCTION

SIGN BIT = 0 = STORE HALT STATUS
SIGN 8IT = 1 = DO NOT STORE HALT STATUS

14.36

MS8 {HALT STATUS BLOCK) ADDRESS IF BIT 00 = 1

Figure

4-26 WRHSB

H4-2L

Instruction

MR-0252

4.3.2
The

External
external

registers

address

I/0

(E)

for

devices

these

holds

implemented.

The

and

use

are

employed

the

transfer

full

only

bits

AC.

The

various

described

Subsections

4.3.2.1

The

address

generated

effective

address

consists

address.

Bit

and

I/O

format

specific

Table

I/0

address

and

AC.

data

The

and

The

I/0

byte

effective

address;

(for

type.

bits

the
test
Both

the

1I/0

eight

are

data

instructions,
device

only

test

instructions

transfer

Unibus

use

which

registers,

right-most

instructions

are

4.3.2.5.

the

externai

controller

general

assignments
for

byte

external

the

addresses

CPU.

instruction

and

addressing

eight

bits

the

instructions

when

modify,

read/write data or mask data

full-word

only

the

épecify

instructions

contents

write,

instructions

depending

(normal)

read,

external

modification)

full-word

Instructions

instructions

KS10

specified AC
or

I/O

are

fully

I/0

number

instructions'
and

ranges

controller

given

Figure

comfigured

KS10

are

number

4-27.

The

listed

4-6.

0--v ---.0

CONTROLLER

NUMBER

ADDRESS

0-077777

NOT USED

100000

MEMORY STATUS REGISTER
NOT USED

1000001-177777

200000

CONSOLE INSTRUCTION REGISTER

20000001-777777

NOT USED

0.3727772

NOT USED

400000.777717

UNIBUS 1 (UBA ANDO DEVICE) REGISTERS

0377727

NOT USED

400000777777

UNIBUS
3 (UBA AND DEVICE) REGISTLRS

2,417

NOT USED
MEL 0253

Figure 4-27 1/0 Address Format
4-27

Table 4-6

External

I/0 Addresses

KS10 Bus

Unibus

Device

Memory Status Register

Memory

Address

100000

Console

200000

UBA Paging RAM

UBA1l

763000-77

UBA Status Register

UBAl

763100

UBA Maintenance Register UBAl

763101

776700%*

Cont.

Console Instruction
Register

Unibus 1

UBAl

RH11 # 1(RPO6)

UBA Paging RAM

UBA3

763000~-77

UBA Status Register

UBA3

763100

UBA Maintenance Register UBA3

763101

772440%

Unibus

UBA3

RH11 # 3(TU45)

UBA3

LP20 # 1

775400%

UBA3

DZ11

760010%*

UBA3

DZ11 # 2

760020*

UBA3

DZ11

760030%

UBA3

DZ11 # 4

760040%

UBA3

KMC11 # 1

760540%*

UBA3

DUP11 # 1

760300*

UBA3

DUP11

760310%

address

NOTE

base

Refer

address.

complete

indicates

(*)

asterisk

list

KS10

for

Appendix

Unibus

device

registers and their addresses.

Note

that an extended address

address

calculation
4-27A)

is as

controllers
for

other

external

I/O

(greater

than

than 18

zero.

instructions

The

required

effective

address

bits)

(diagramed

Figure

follows:

there

is no indexing or

indirection, Y is used

the effective address.

there

1is

indirection

4-29

(or

indirection

and

INSTRUCTION FETCHED

INSTRUCTION

o.C.

XRig.3s+Y

XRpg-35 + Y

FETCH

INDIRECT
WOROD

[

:
VMA

EXTENDED ADDRESS

BITS 18-35 -~ VMA

18 BiT ADDRESS

NOTES.

INDIRECT BIT

X -

INDEX REGISTER BIT

XK ~

Y «

INDEX REGISTER CONTENTS

ADDRESS BITS

VMA =

VIRTUAL MEMORY ADDRESS
MRA-0841

Figure 4-27a
far
-

Effective Address Calculation

w
S xtern

I/0

4-3p

Instructions

indexing),

is used as an address for an indirect word

fetch

and

the

contents

14-35)

are

used

there

left
to

half of
2zero,

there

left

half

The

operations

result

the

an 18-bit or

the

indirect

effective

address.

18-35

index

indexed

used

the

indexing
the

bits

described

Table 4-7

the

effective

an extended

indexed by bits 18-35 of

(and

effective

indexing

indexed
by
as

(or

bits

(and

less

(bits

and

the

than or

equal

index

the

address.

indirection)

the

index

word

indirection)

effective

index

06-35

the

index

and

the

positive,

used

4-7.

The

address.

above

are

address

summarized

calculation,

I/O address

is also

Table

which

can

either

indicated.

Summary of Effective Address Calculation
for

External

I/0 Instructions

Indirection

Indexing

XRL

Effective Address

Comments

18-bit Address

YES

(Y)

Extended Address

YES

(Y+XR18-35)

Extended Address

YES

Y+XR18-35

18-bit Address

YES

Y+XR06-35

Extended Address

It can be seen that to address controllers other

require

extended

indirect

addressing

address,

must

instructions

used.

Examples

(controller

indexing

each

follow,

both

into

an AC with

the RDIO external

(Subsection 4.6.2.3).

I/0 instruction

Example 1

number

using

which

(register address = 763100)

of which read the status register
UBA #1

than zero,

(using

indexing):

RDIO AC,763100(X)

where

the

contents

index

to Y

1000000

The

index

contents

(the

controller

number)

added

(the register address) to give the eitended I/0 address 1736100.

Example

(using

RDIO AC,

An indirect

indirection):

100

word

where

fetch of

the

contents of 100

location

100

is made

1763100

and

the

contents

are used to generate the extended I/0 address 1763100.

4.3.2.1

TIOE

and

TIOEB

(710

and

4-32-

720)

The

TIOE

(or

TIOEB)

instruction

fetches

specified by E,
the

word

(or

byte)

The

from

instruction skips

I/O

address

if the result of the AND

The contents of the AC are not modified.

and

TIONB

(711

and

721)

instruction performs

the

same

function

4.3.2.2

the

with the contents of

(or byte)

and ANDs the word

specified AC.

is zero.

one

TION

The

TION

the T1OE

(or

TIONB)

(or TIOEB)

instruction except that the instruction skips if the result of the
AND is not zero.

RDIO and

4.3.2.3

RDIOB

(712

and

RDIO

(or

RDIOB)

from the I/0 address

instruction fetches the word (or byte)
specified by E and stores the word

The

722)

(or byte)

right-justified in

the specified AC.

WRIO and WRIOB

4.3.2.4

(713

and

The WRIO

723)

(or

WRIOB)

instruction takes the word (or byte) contained in the specified AC
and transfers the word

to the I/0O address specified by

(or byte)

4.3.2.5

instruction

BSIO and

BSIOB

fetches

the

specified by E,

ORs

and

(714

word

AC,

address.

The instruction(s)

byte)

transfers

specified

Unibus device registers.

(or
(or

the word

then

and 724)

the

The

from

BSIO

(or

the I/O

BSIOB)

address

with the contents of the

result

back

the

I/0

may be used to set selected bits in

The contents of the AC are not modified.

4-33

BCIO and BCIOB

4.3.2.6

instruction

similar

- The BCIO

(715 and 725)

the BSIO

(or BSIOB)

(or BCIOB)

instruction

except that the word (or byte) read from the I/0 address is ANDed

with the complement of the AC contents.
to

used

clear

bits

selected

The instruction(s) may be

in Unibus device

registers.

The

contents of the AC are not modified.

4,3.3

PXCT Extensions

The UMOVE and UMOVEM instructions have been originated for

the

KS10 to save time and space in the monitor.

4.3.3.1

- The UMOVE

UMOVE (704)

(move from previous context)

instruction performs the same functions as:

PXCT 4,

4.3.3.2

[MOVE AC,

UMOVEM (705)

- The UMOVEM

(move to previous context)

instruction performs the same function as:

4, [MOVEM AC, E]
PXCT

KS10 PROCESSOR STATUS WORDS

4.4

Whenever

the

PC,

the KS10 processor halts,

and

it writes a halt status word,

1in

18 words)

(of

a halt status block

(optionally)

memory.

The halt status word contains a code indicating the type of halt;

the halt status block contains a read-out of several CPU registers
(HR, VMA, etc.)

include

the

Other KS10 status words

at the time of the halt.

page

fail

which

word,

following a page failure; and the PC word

into

written

UPT

the

(PC with flags), which

in an AC or memory location by certain system level

stored

instructions.

4.4.1

Halt Status Word

A halt status code is stored in physical memory location 0 (not AC

whenever

(octal)
indicate

Codes in the range 0-77

the KS10 Processor halts.

indicate normal halts; codes in the range 100-177

(octal)

greater

software

failures;

1000

codes

indicate microcode or software failures.

(octal)

Bit format and halt code

definitions are given in Figure 4-28.

4.4.2

A processor

halt causes

the PC

physical memory location 1

4.4.3

Halt Status Block

halt

the

status

block

to be

stored

right

justified

(not ACl).

address

4- 35

positive,

processor

halt

HALT STATUS WORD (MEMORY LOCATION 0)
35

HALT CORE
RH{0)

BIT(S)

FUNCTION

HALT CODE

24-35

}

0000

MICROCODE JUST STARTED

0001
0002

HALT INSTRUCTION EXECUTED
CONSOLE PROGRAM HALTED CPU

0100

I/0 PAGE FAILURE

0101
0102

POINTER TO UNIBUS VECTOR IS ZERO

1000

JLLEGAL MICROCODE DISPATCH

1005

MICROCODE STARTUP CHECK FAILED

ILLEGAL INTERRUPT INSTRUCTION

Mi4-0254

Figure

causes

the

block

4~-29

contents

4-28

Halt Status Word

several

K510

memory

shows

the

information

status

block

stored.

address

processor

starting

stored

negative,

the

registers

specified

each

the

stored

address.

location.

halt

status

Fiqure

the

block

halt

not

The WRHSB instruction (Subsection 4.3.1.24) allows the

program

load

any

address

value.

1Initially,

when

the

microcode

is started
the
, halt status block address is set to a value of
376000

(+)

and the halt status blo
is stored.
ck

The first 16'memory locations of the halt status block hold the

the

(also

circuits.

stored

Significant

memory

EBR,

UBR,

microcode

flags,

flags

are

described

read

the
=%

same

that

and

location
Pl

Subsection
by

the

2N
==

4-34

status

1),

system

current

status.

4.4.3.1.
RDPI

information includes

instruction,
The

system

instruction

microcode

status

(Subsection

MEMORY

LOCATION

MAG

X+2

17 18

NN TT

e ////////////////////
HR

CURRENT INSTRUCTION

X+3

AR (36)

X+4

ARX

ARX (36)

X+5

BR (36)

X+6

BRX

BRX (36)

X+7

ONE

X+11

usR

X+12

MASK

X+13

FLG

X+14

X+1§

X+16

X+20

VMA®

VMA FLAGS

X+21

‘E 'bm

Fe/sc

. FE19

1]‘1 Feo|

scie

000 -«

«vvovennes

P ;"

/fii%

ceeries

_pot

001

’233;,

UBR (1)

////%}})////4
m

MICROCODE FLAGS

P1 STATUS (ROPI)

00 «o-reeneenn@

00. .. ....eees
01

Jetser

{;17‘w

S
1.....c1 {sCO
as

" NOTE. X = 376000 WHEN UCODE FIRST LOADED. ADDRESS
MAY BE CHANGED

BY WRHSB INSTRUCTION.
MR-0255

Figure

4-29

Halt

4-37

Status Block

Another processor statué word, the VMA contents (plus
flags),
stored

in the next

to last location of

the halt status block.

is
Bit

definitions for the VMA word are given in Subse
ction 4.4.3.2.

4.4.3.1

Microcode Flags -

the event of a page

flags

and

a page

are

stored

block

X+13.

fail

The

code

page

fail

code,

part

which

failure,

of the

the

halt

contents

three
status

the

microword's maQic number field, specifies the operation for which
the

page

failure

occurred.

code definitions are given

Status word

bit

format

and

page

fail

in Figure 4-30.

MICROCODE FLAGS
00

LH (370013) l

WREF|

CYC | cACH

AH(376013" I
7

]

|
3

)

PAGE FAIL CODE
\

)

BIT(S)

FUNCTION

4.'

WRITE REFERENCE afr FROM PAGE MAP

PI CYCLE

LOOK IN CACHE BIT FROM PAGE MAP

18-38

PAGE FAIL CODE

000000
000001
400002

000003
000004
000008

000008
000007
000010
000011

000012

Pigure 4-30

I
1

SIMPLE INSTRUCTIONS
BLT IN PROGRESS
MAP IN PROGRESS

MOVE STRING SOURCE IN PROGRESS

MOVE STRING FILL IN PROGRESS MOVE STRING DESTINATION IN PROGRESS
FILLING DESTINATION
EDIT SOURCE
EOIT DESTINATION
CONVERTING DECIMAL TO BINARY

COMPARING DESTINATION

Microcode FPlags

4.4.3.2

vaa - The virtual memory address (VMA) and VMA flags are

stored in location
X + 20 'of the halt status block.

Bit format

and definitions
are given inPigure 4-31.
VMA
LH{370020}

UBER| EXEC| INST |READ|
MODE

E|FTCH]|

_“
RK{378020)

WRT

WRT|

1/0 | NOT | PHYS

CYC | TST

]

CYC | R/w

|CACH|

.15

REF

.13

SYTE

PHYS ADDR

]

VIRTUAL ADDRESS (BIT 8 = 0) OR PHYSICAL

ADDRESS (BIT 8=1)

“J“:“lz‘nul2312‘1”1“.2743'1"1”

:3‘13213313‘13

BIT(S)

FUNCTION

USER MODE
EXEC MODE

INSTRUCTION FETCH

READ CVCLE

WRITE TEST
WRITE CYCLE

1/0 READ OR WRITE

DO NOT LOOK iN CACHE
PHYSICAL REFERENCE

UOsrunmnwucnqgégfl

1417

BITS 14.17 OF PHYS!CALM)DRESS (OR O

1838

BITS 18-36 OF VIRTUAL ADDRESS (BIT 8 = 0) OR PHYSICAL
ADORESS (81T 8= 1)

MR-0287

Figure 4-31

4.4.4

PC Word

Several

VMA

the

jump

instructions

(e.g.,

JSR)

save the PC and various procéssor flags in
a memory location or an
AC.

Bit

format

for

this PC word

4-39

shown

figure 4-32.

PC WORD
0
LHirey

JOVF |

CARRY
0

| FLY | FPD

|user|usen

|OVF

TRAP

.13

FLT | NO

UFLO]

DIV

18
1

]

}

RH(PC)

PROGRAM COUNTER

1.119‘30121_122123424L25ia‘27L20429|30[3|132133]3‘|35

BIT(S)

FUNCTION

OVERFLOW

CARRY 0

CARRY 1

FLOATING OVERFLOW

FIRST PART DONE

)

USER MODE

USER IOT (ALSO PCV)

TRAP 2

TRAP 1

FLOATING UNDERFLOW

NO DIVIDE

1838

PROGRAM COUNTER
MR-0258

Figure 4-32

¢.4.5

Page

Fail Word

Following

in-out

failures,

the processor

fail

page

is shown

word

PC Word

location

all

causes
500

in Pigure 4-33.

4 -4

page

a page

(octal)

failures,

except

fail

and

stores

Bit

format

the

trap
UPT.

for

PAGE FAIL WORD (OR MAP AC)
W

LH(800)

uua‘
0

PAGE FAIL CODE OR

PAG

REF

WATL WRTN WREF

I
1

.
R

ADDRESS

16,

R43t800) [

‘
i

~
il

VIRTUAL ADDRESS (PHYSICAL FOR MAP IF BIT
2 = 1)
1

BIT(S)

FUNCTION

USER ADDRESS

]

25(BIT1=0)
2

TRANSLATION VALID

WRITABLE

WRITTEN

WRITE REFERENCE

28(BIT 1=1)

PAGE FAIL COOE
20

AN /O INSTRUCTION SELECTED A NONEXISTENT
OEVICE OR REGISTER. (BITS 14.35 = 1/0 ADDRESS)

PAGE TABLE PARITY ERROR

36
|

1835

HARD MEMORY ERROR
NXM

PAGED REFERENCE

* VIRTUAL ADDRESS (PHYSICAL FOR MAP IF BIT 2 = 1)
MRA.0259

Figure 4-33

4.5

page Fail Word

KS10 EPT/UPT

Bxecutive

process

table

(EPT)

and

user

process

table

(UPT)

configurations for the KS10 are shown in Figures 4-34 and 4-35.

77/

USER PROCESS TABLE

EXECUT!VE PROCESS TABLE

- NOT UBED

STANDARD PRIOMTY INTERRUPT INST

NOT USED
NOT USED

VECTOR INTERRUPT TABLE POINTERS

120

TS PBRUBIGORCRLELEOEBRLS

NOT UBED

USER ARITHMETIC OVF TRAP INST

421

EXEC ARITHMETIC OVF TRAP INST

USER STACK OVF TRAP INST

422

EXEC STACK OVF TRAP INST

USER TRAP 3 TRAP INST

423

EXEC TRAP 3 TRAP INST

FLAGS 1 MUUO OP-AC
MUUO OLD PC

E OF MUUO
MUUO PROCESS CONTEXT WORD

KERNAL NO TRAP MUUO NEW
PC WORD

KERNAL TRAP MUUO NEW PC WORD

SUPERVISOR NO TRAP MUUO NEW PC WORD
SUPERVISOR TRAP MUVO NEW PC WORD

CONCEALED NO TRAP MUUO NEW
PC WORD

NOT USED

CONCEALED TRAP MUUO NEW PC WORD

NOT USED
PAGE FAIL WORD

PAGE FAIL FLAGS
PAGE FAIL OLD PC

PAGE FAIL NEWPC
NOT USED

537
USER SEC O PTR

540

EXEC SEC O PTR

541

NOT USED

NOT USED
m

Figure 4-34

KS10 EPT/UPT

(TOPS20 Paging)

USER PROCESS TABLE

USER PAGE 0

EXECUTIVE PROCESS

USERPAGE 1

NOT USED

|
|
|

STANDARD PRIORITY INT

ERRUPT INST,

NOT UsSED

VECTOR INTERRUPT TAB

LE POINTERS

|
|

NOT USED

USER PAGE 777

EXEC PAGE 341

EXEC PAGE 377

ADDRESS OF LUUO BLOCK

USER ARITHMETIC OVF TRAP

INSY

USER STACK OVF TRAP INST

USER TRAP 3 TRAP INST

MUUO STORED HERE
PC WORD OF MUUO STORED

EXEC PAGE 400

EXEC PAGE 401

EXECPAGE 776

EXEC PAGE 777

NOT USED

§R88

g3
-

EXEC PAGE 240

EXEC PAGE 378

BRSBSGR
OB 885888483

g3
&

USER PAGE 77¢

TABLE

EXEC ARITHMETIC OVF

TRAP INST

EXEC STACK OVF TRAP

INST

EXEC TRAP 3 TRA
P INST

HERE

PROCESS CONTEXT WOR

D STORED HERE

NOT USED
KERNAL NO TRAP MUU

O NEW PC WORD

KERNAL TRAP MUUO NEW

PC WORD

SUPERVISOR NO TRAP MUU

O NEW PC WORD

SUPERVISOR TRAP MUU

O NEW PC WORD

CONCEALED NO TRAP MUUO NEW
CONCEALED TRAP MUUO NEW

PC WORD

NOT USED

PC WORD

NOT USED

EXEC OR USER PAGE FAIL WORD STORED

~ EXEC OR USER OLD PC WORD STORED
PAGE FAIL NEW PC WOR

FiERE

HERE

NOT USED

757

EXEC PAGE 0

execrace 1

EXEC PAGE 336

EXEC PAGE 337

NOT USED
1213

‘
MR-0200

Figure 4-35

KS10 EPT/UPT

49- 913

(TOPS10 Paging)

4.6

OPERATOR CONSOLE

Local

operator

control

the

KS10

set

commands

typed

at the consocle terminal (CTY).' The CTY connects directly to the
8080-based

console

line,

operates

that

connected

remote

the

hardware

commands

diagnosis
console
PROM

and

typed

valid

The

CTY

The

two modes

and

the

Other

(user

the

CTY,

implemented

8080

line.

second

serial

first line, may also be

allow

control
of the

only)

terminals

KS10

connect

(DzZlls).

1link, ‘are

module's

serial

hardware

link.

the KS10 via the Unibus

The

in parallel with

console

diagnosis

via

microprocessor.

entered

the

from

program

The

the

running

program

remote

resident

the
in

at power-up.

remote

diagnosis

link

operate

in either

are:

User

Console mode

mode

NOTE
The

CTY

operate

and
in

remote

diagnosis

the same mode or

modes.

Subsection

OPERATION,

link

may

in different

4.7,

KLINIK

describes how the remote link

gains access to the systém and enters
either

user

mode

2. 44

console

mode.

The

two

modes.

remainder of

this

subsection

4.6)applies

CTY

Commands

the

are

operation

same

link but operation

(Subsection

for

only.

the

remote

restricted
in some

cases.

In user mode,
commands

are

the CTY is a user terminal and
passed

console progi:am.’
which
to

causes

console

the

and

from

the

The exception
console

mode.

All

program

other

KS10

CPU

(with.one exception)
under

is a control
to

switch

commands

control

backslash

the CTY

performed

the

("\"),

from user mode
user

mode

are

function of the operating system (TOPS20) resident in KS10 memory.

console

mode,

8080

console

major

functions:

commands

hardware.

are

directed

operator

Reset

Load

Deposit and examine memofy;‘

Read

and

write

Read

and

write KS10

Start

Single-ste
the
p CPU clock.

and

bootstrap

may

(and

perform

system.

check microcode.

I/0 device

bus.

stop CPU clock.

4-457

executed

registers.

the

by)

the

following

The

Execute a given instruction.

Halt

the machine.

10.

Start the machine at a given location.

ll.

Single-instruct a program.

console

power-up.

When in

execution
user

program

initializes

console

mode,

(ST or CO commands)

mode.

stated

the

CTY

starting

to
or

a control-Z

previously,

mode

continuing

program

switches the CTY to

control

user mode causes a return to console mode.

console

backslash

Also,

("\")

an error which

lights the FAULT indicator causes a return to console mode, as
does any KS10 processor halt instruction.

4.6.1

Console Mode Commands

The console mode command prompt are the characters "KS10"

(KSlO>)

by a greater than sign

',A command,

followed

a string of

commands separated by commas, mayvthen be typed and followed by a
(CR).

The CR causes

carriage

return

commands,

to be executed.

listed in Table 4-8.

The various

the command

string

console mode

commands

are

Error printouts are listed in Table 4-9.

Table 4-8

Load

Commands

(Values

loaded

Console Mode Commands

Function
in

8080 RAM locations
for

subsequent

use

as arguments by

associated deposit
and examine
commands.)

LA xx

Set KS10 memory

address

(0000000-1777777)
.

LC xX
LF xx

Set CRAM address to xx (0000-3777).
Load diagnostic write function xx
function

(0-7).

The

specifies a 12-bit group within a CRAM

address.

CRAM Bits

00-11

12-23

24-35

36-47

48-59

60-71

72-83
/A2

G-77

7
LT

Load

84-95

1/0 address.

control

number

addresses

The

and

accessable

listed below.

Note

address

consists of

address.

from

console

that

the

1I/O

are

address of

the

console instruction register is hot included.
If

the

console

instruction

attempts

access

its own

response occurs.

CTL

Address

100000

Memory status

763000-77

UBA paging RAM

763100

UBA status

763101

UBA maintenance

TXXXXX

Unibus device

Set 8080 memory address

00000-17777;

RAM address =

xx.

registers

(PROM address =

20000-21777).

Deposit Commands

Deposit xx (36 bits) ontb KS10 bus.

Deposit xx

(96 bits)

previously loaded

#-15

into CRAM.

(Appendix C)

Address

by LC command.

Deposit xx

(12-bit group)

into CRAM. Address

and diagnostic function previously loaded by LC
and LF commands.

Deposit xx

(16,

18 or 36 bits)

into an I/O

Address previously loaded by LI

command.

‘Deposit xx

(8 bits)

into 8080 memory.

(Data cannot

previously loaded by LK command.
be deposited

in PROM addresses;

Address

only in RAM

addresses.)

Deposit xx

(36 bits)

into KS10 memory.

Address

previously loaded by LA command.

Deposit xx

into next

(KS10,

8080,

I/O)

address.

Examine Commands

Examine KS10 Bds.

Prints contents of console

registers 100-103, 300, and 301

(Subsection

4.6.2).

Examine current contents of CRAM control
register.

7-77

Examine

contents

xX.

Examine contents of I/0 register.

previously

of CRAM address

loaded

Address

by LI command.

Examine contents of I/0 address XxX.

Examine current CRAM address,

address,

next CRAM

jump address, and subroutine return

address.

Examine contents of 8080 memory.

Address

previously loaded by LK command.

Examine contents of 8080 memory address xx.

Examine contents
of KS10 memory.

Address

previously loaded by LA command.

Examine contents of KS10 memory address xx.

Examine

contents of next

address.

Start/Stop Clock Commands

4-F

(KS10,

8080,

I/0)

Halt

Pulse

CPU clock.

Pulse CPU clock

Start

times.

CPU clock.

Start/Stop Microcode Commands

Pulse microcode.

Performs

execute

a microinstruction

command

CP command

followed

current CRAM

by an EJ

address,

CRAM address, jump address, ahd subroutine
return

address.

Reset

and

start microcode

at CRAM

address

Reset

and

start

address

xx.

Trace.

Repeats

microcode

CRAM

command

until

any CTY

Repeats PM

command

until

CRAM

key

depressed.

Trace.

reached or

depressed.

Start/Stop Program Commands

G-5/

until

any CTY key

address

Halt KS10 program.

Microcode

enters halt

Continue KS10 program execution.

Enter

loop.

user

mode.

Shut down command.

Deposits non-zero data

KS10 memory location 30
down of

Single

into

to allow orderly shut

the monitor.

instruct.

Execute next KS10

instruction.

Start KS10

program

at address xx.

Enter

user

mode.

Select Device Commands

Select disk

for bootstrap.

asks for UBA number
address

(default =

number

(default =

>>UBA?

>>UNIT?

(default = 1),
776700),

<CR>

>>RHBASE? 776700
0

<CR>

S-2

Console program

<CR>

RH1l1l base

and disk unit

follows:

The default value for the RH11l base address is

currently the only value permitted.

Also, a

carriage return in response to any question
retains the current value.

Select tape for bootstrap.

Console program

asks for UBA number (default = 3), RH1ll base

address (default = 772440), tape uhit number
(default = 0), tape density (default = 1600
BPI), and slave number (default = 0) as
follows:

>>UBA?

<CR>

>>RHBASE? 772440 <CR>
>>UNIT? 0

<CR>

>>DENS? 1600
>>SLV?

<CR>

The default value for the RH11 base address is
currently the only value permitted.

Also, a

carriage return in response to any question
retains the current value.

Boot Commands

Bootstrap the KS10 from disk.

Loads and starts

‘microcode and monitor boot program from drive 0
F-53

on UBAl

or drive

(default address)

last DS command;

selected by

starts KS10 at memory address

1000.

Same as BT command

program
and

(not

except

monitor

that diagnostic

boot

program)

boot

loaded

started.

Check the KS10 boot path.

Load

the

selected

monitor

boot

program

1last.

Does

not

the

from

load

disk

microcode.

Program must be started at 1000.

Same as LB command except that diagnostic boot
program

(not monitor

boot program)

1loaded.

Program must be started at 1000.

Load

the

selected

monitor

boot

program

1last.

Does

not

from

load

the

tape

microcode.

Program must be started at 1000.

Bootstrap the KS10 from tape.
microcode

and

monitor

boot

unit 0, slave unit 0 on UBA3

Loads and starts
program

tape

(default address)

‘or drive selected by last MS command.

4- ¢

from

Mark/Unmark Microcode Commands

Mark

microcode

word

(set

word

(clear

bit

95)

CRAM

95)

CRAM

address xXx.

Unmark

microcode

bit

‘address xX.

Master Resét Command
1Issue bus reset.

Master reset.

Execute Command

Execute

the

single

KS10

systems-level

or disable

(xx=0)

cache.

instruction xx.

Enable/Disable Commands

Enable

(xx=1)

Enable or disable parity detection as follows:

Disable all parity detection.

455

Enable KS10 bus parity detection.

Enable DPE/DPM parity detection.

Enable CRA/CRM parity detection.

Enable

Enable
timer

all

(xx=1)

parity detection.

disable

(xx=0)

CPU

interval

interrupts.

Enable

(xx=1)

Following

carriage

or disable

(xx=0)

enable/disable

CPU traps.

command

with

return gives the current value.

Read Cram Commands

Read CRAM data. Pérforms diagnostic read
functions 0-17
contents

(of

to read CRAM addresses and

current address)

Data

CRAM bits 00-11

Next CRAM address

CRAM

subroutine

9-3%

return

follows:

address

Current CRAM address
CRAM bits

12-23

CRAM bits 24-35

(Copy A)

CRAM bits 24-35

(Copy B)

0s
10

Parity bits A-F

KS10 Bus bits 24-35

CRAM bits

CRAM bits 36-47

CRAM bits 48-59

CRAM bits 60-71

CRAM bits 72-83

CRAM bits 84-95

36-47

(Copy A)

(Copy B).

Zero Memory Command

Zero memory.

Deposit 0s

into all KS10 memory

locations.

Repeat Command

Repeat last command,

last command string,

until any CTY key is depressed.

Lamp Test Command

Blink

indicators.

557

Momentarily lights

(1-2

seconds)
FAULT,

are

and

then

turns

REMOTE

returned

off

(1-2

seconds)

indicators.

their

The

STATE,

indicators

original

state.

Password Command

‘Set password xx (xx=maximum of 6 alpha-numeric
characters).

Following

clears

a PW command with

the password

storage

a carriage

return

area.

KLINIK Command

Enables

remote

link with access to system

operate in user mode but not in console mode
(xx=0).

Enables remote

link with access

system to operate in console mode or
mode

in user

(xx=1).

Following

gives

a KL command with a carriage

the current value.

return

- Special Control Characters

control-C

<Console returns command

Abort current command.
prompt.

(type-outs).

control-0

Inhibit CTY output

control-S

Inhibit CTY output and stop 8080 console
program until control-Q is typed at CTY.

control-Q

Enable CTY output and continue 8080 console
program.

control-U

Delete current line.

control-2

Enter user mode.

RUB-OUT

Delete last character.

NOTES

1. An

(*)

asterisk

indicates

that

the CPU clock must be stopped in
order ‘to execute the command.

2. More

than

one

command

entered on a line
commas)

and

command string.

7-57

may

(separated by

executed

Commands
control

(except

for

characters)

and

strings

are

carriage

return

command

execution.

control

special
command

followed
(CR)

characters

to cause
(Special

are

executed

when typed.)

Table 4-7

Console Mode Error Messages

Message

Meaning

?A/B

A not equal

to B

(A and B copies of
a microcode field

did not match.)

Buffer

?BFO

overflow.

(Too

console's 80 character

Bad

number.

many

characters

input buffer

(Character

typed

typed;

is full.)

not

octal

number.)

?BT

BT_command

failed.

(I/0

ERRTEST

8080

address

failed.)

?2C

CYC

Command/address cycle failed.

detected

during

command;

¥-ep

(KS10 bus data failure

good

and

bad

data

printed.)

Data

cycle

failed.

(KS10

bus

data

failure

detected

during DB command; good and bad data printed.)

Did

?DNC

not

complete.

microcode

Did

?DNF

not

(HA

to enter

finish.

command

did

not

cause

halt loop.)

(ST,

CO,

or EX command did not clear

console's CONTINUE bit.)

Illegal

?2IA

address.

(Address typed

Illegal command.

?MEM
ERR

Memory

refresh

cycle.

Error occurs when memory must be refreshed in

error.

(Incomplete

KS10

MOS

memory

state.)

No bus
after

?NDA

(Command typed is not valid.)

REFRSH

hung

?NBR

is out of range.)

response.

(Console

did

not

receive

GRANT

requesting KS10 Bus.)

data

acknowledge.

(Consle

did

not

receive

DATA

CYCLE signal after a data request.)

2NXM

Non-existent

memory.

4?—¢¥

(Deposit

examine

command

referenced non-existent KS10 MOS memory location.)

(CPU

error.

parity

System

clock

stopped

due

xx=contents of the following console

system parity;

status registers in the order indicated:

100, 303, 103

Refer

for

status

bit

(Command

typed

requires

Subsection 4.6.2

format.

argument.

Requires
argument.)

?RUNNING

Clock running.

(Command typed requires CPU clock to

be stopped.)

Unknown

7201

(Console

interrupt.

received

interrupt

but CTY has no character.)

4.6.2

Console Status Registers

The console program reads and prints (at the CTY) the contents of
certain 8080 registers in response to the EB (examine bus) command
and

system parity error

(?PAR ERR).

registers 100-103, 300, and 301.

The

command

prints

Registers 100, 303, and 103 are

printed when the system parity error is detected.
format is shown in Figure 4-36.

4-o2-

100

-C5L

PAR ERR

-UBA 3

PAR ERR

-CRM

-MEM

PAR ERR

-CRA

PAR ERR

i
Pl REQUEST

101
1

107

RESET

MEM REF
]

ERRA

MEM -

BUSY

BAD DATA

BUSY

COM/ADR

cyc

/0 DATA

cYe

DATA

cyc

-usan

PAR LR

BUS DATA

1
PAR RH

300

CTY STP

CTY CHAR

BIT 5w

KLNK STP

LNGTH Sw

KLNK

BIT SW

HALT

LENGTH SW

LOOP

RUN

EXECUTE

INT

305

PARLH

CONT

INUE

BUS

LOCK

REQ

PAR ERR

BOOT

DATA

ACK

PAR ERR

-DPM

MR-0842

Figure

4-36

Console Status Registers

#-¢3

4,7
TO

KLINIK OPERATION
BE

SUPPLIED

4-c%#

"SECTION 5
TECHNICAL DESCRIPTION

%&hé:ofgfihiiational structure
of the KS16 can be viewed as‘ a
hierarchy Qf buses, each of which is a data path shared by a

number of éifferent logical elements.
comprises

four

major

communicate
with one another
subsystem

turn

made

units

over

up of

The overall

subsystems

backpanel

secondary

bus.

cases

level,

tfiese

the

buses

backpanel

are

bus

has

bidirectional.
a

single

set

1limitations

transactions

with

data

flow are

available

the memory. or

bidirectional
one

At the systenm
data

processor,

and

controls

others

between

subsystems
and

lines

in-out

subsystem,

which

storage modules

the most complex

the normal operati

based on
a unidirectional

over

although

can initiate

which directions

a given pair

but occurs between a single

number

The

which

Each

In almost

which any subsystem can communicate with any other,

there are

that

components grouped

around one or more secondary buses or data paths.

all

system

Subsystems.

data

flow

and

any

controller
peripheral

the

devices.

subsystems,

6ff£he.éfi€ire system, is

datavfpéth

that

several

parts, and has several major loops; with many side loops and

with logic elements lying in the various parts of the

data

particular,

the
and

this

system

uescribes

chapter
as

discusses

wholz

tnosc

and

the

overall

the

processor

common

characteristics

)

section
of

)

first

Tne

path.

{low

Bérgpe—y

all

subsystems,

communication

mainly

over

the

timing

backpanel

and

the

bus.

manner

The

remaining

sections give detailed descriptions of

thé

various

devoted

major

5.1

subsystems,
with several

parts

the

ORGANIZATION

Figure

5.1 shows

#aek.

columns

correspond
the

AND

physical

The

slot

system,

numbers

the

also shows

the

connectad
data

Unibus.

11-14,
The
its

and

number

them.

The
its

which

all

Similarly

which

and

comprises

the

connection

to the bus

board
the

the

both

transfers

Unibus

MMC and

that

bus

occur

adapter

system

1is

which are

the movement
four

subsystems:

subsystem based

four
at

boards
the

in slots

DPM

board.

the memory array boards at

memory;

backpanel

all

in-out

bnards

that make

The

system has
an

the

elementary logical

handles

processor

between

the

bus,

console,

connected

subsystems,

The minimal

memory,

right make

to a backpanel

memory control

interface

among

processor,

essentially
bus

and

between

board

boards

tops of the

the

elements

organizatction of a KSl8-based DECSYSTEM-24.
made

the

below

Since

logical

KS10

at the

boards - just’

to the

drawing

are

designations.

well

the

arrangement

the

board

rather

TIMING

representing

three-letter

bus and the

processor.

the

baciiplare

the

sections

MMC

1is

the

the memory array,

memory

control

UBA in slot

bus

and

over

memory.

serves

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55

ARRAN | ORRAY 12N~ SIAK

the

interface

between

the

backpanel

bus

and

the

Unibus

the peripheral deviées.

A second adapter can be mounted

slot

another

adapter

the

for
1

interfacing

handles

other

the

peripheral

disks,

Unibus;

and

adapter

when
3

this

handles

the

all

other

link

the

system

hence

bus,

The

operator

via

purposes.
clock

and

myriad

the

memory

array

console

board,

bus

MMC).

with

for

the

and

all

connecting

board

and

contains

backpanel

bus:

bootstrap

subsystems,

and

including

processor

direct

boards

operating

console

individual
lack

the

all

apart

four

console

arbitration,

other

boards

the

provides

access

timing,

all

the

board

terminal

controls

among

between

Morecver

supplies

signals

and

console

diagnostic signals to
of

especially

processor,

subsystems.

diagnostic
the

the

equipment.

backpanel

that make

1in

done,

Thnere are of course many other interboard connectidns
trom

boards

connections

(only

the

they commméfiicate snlely via the memory

The four boards.that make up the firbceésor'ére organized
two

pairs.

The

-data path boards,

DPM and DPE,

handle

the

execution of the instructions in"the program

undet

the CRA and CRM

the

microcontroller,

which

boards.

DPE contains

the

program

flags,

instruction

containing

the

full

fast memory

comprises

word

arithmetic

(AC blocks),

the

and

control

1logic,

the

cache,

RANM

the

file

and

Pasyennd

microcode
logic

workspace;

for

step

addressing
connect

the

microcode

which

also

boards

counting

logic,

that

DPM

and

byte

the

backpanel

control

contains

bus.

RAM, about

the

18-bit

manipulation,

the cache directory,

microcode

and

arithmetic

the

memory

the transceivers

CRM

is devoted

third

of which

addressing

solely

logic.

CRA,

The

supply many conditions that can be tested by CRA for

sequencing the microcode;
code

contains

selects

locatea

selected

fields

location

DPE,

1is

dispatch

in particular

the

part

word,

a dispatch

the

together

instruction

each. instruction
ROM that,

although

microcontroller.
with

word,

the

provides

The

and

index

CRA

with

information for dispatéhing to appropriate control RAM
locatinns for calculating the
the

operands,

resuit.
under

executing

effective

the

address,

instruction,

These activities are carried out
control

and CRM.

the

microinstruction

and

bits

Some bits are also supplied to

fetchin§

storing

LCPM

and

supplied

CSL

fof

the

D?E
CRA

handling

consoie functions and to control the clock - its period can
be

lengthened

whenever

necessary

for

the .

data

path

oparations.

data

path

the

D bus,

the

RAM

file,

output of

the

three

which

and

the

parts.

supplies

Contained

data

instruction

arithmetic

logic

the

to the various elements on

“

The

the

entirely

arithmetic

available

DPM

board,

vVia

the

DPE

logic,
LCP

the

D bus

and

1including

the

Rage—5

backpanel

bus

transceivers

for

transmission

1/0 equipment. .Data from various
words
is

from

©DPM

to memory or

elements,

the

including

"memory and the DP data with its halves swapped,

available

via

DBM,

which

input

the mixer

for

the

D bus.

The

haraware

schematics,
even

three

code

form

and

1is

Y
DPE

are

after

the

CRA.

than

being

drawing

the

letter

number

letters

"M"

set

referenced

the

block

simply by

circuit

has

engineer,

the

The Yz designations are also

part

used

names to show.tne signal source.

ground

connector

number
by

the

bonard

usually

designation,

such

1indicating

the

alphabetical

diagrams,

board,

letter

and

sometimes

bonard

series;

power

numbers
order

are

when

schematic

at the :ight of the dfafiing number.

and

followed

the

drawings.

off

and

mnemonic

the

schematic

number

nine

signed

1in

entirely

Each

revision

shown

spare pins,

three-letter

followed

appears
text

where

the

individual
first,

devoted

terminators.

are

In every set, the final one, two or

capacitors,

Ww-X-YZ

number,

board

CS.

prints

connactions,
layouts

each

used
there

revised

revision

letter

Throughout the

individual

prints

the

drawing

number.

prefixes

are

signal

The board designations (Y)

are uéed in the names of signals that are generated on the
console

and

supplied

the

other

boards.

Signals

for

Paggeg

Unibus adapters
shown

The

parentheses

adapter

numbers

1 and 3

numbers

used

for

are

designated

Figure

and

addressing

5.1,

are
the

the

mnemonics

namely ACPT@

and ADPT2.

actually

adapters

the

over

subsystem

the

backpanel

bus.

5.1.1

The

Processor

bold

two

line

Logical

across

Organization

the

center

Figure

5.7

divides

major functional areas of the processor:

above,

the microcontroller

figure

are

The

basic

bus,

the

data

the

boundaries

loop on

below.

the

DPE

arithmetic logic,

based

ten

Am290)

adder

and

holas

the

current

shifter,

but

arithmetic

they

are

the

cache

available

expandea by the

with

its, mixer

entire

registers,

general

the

purpose

lines

the

DP.

1logic,

not

count

registers,

and

is
only

file

program

This

which

contains

the

that

PC,

the

verious

Words on the D bus can also be

AC's

for

the data path

the main data path

slices,

the

boards.

is made

arithmetic

constants and control words.
in

individual

microprocessor

instruction,

saved

The dashed

board

and

is not a trivial loop, as the

the

later use.

inclusion of DBM and

RAM

file

from

which

The basié loop can be
the

logic

associated

the

LPM board.

To operations an full

.words, this extension

the

adds

exponents,

manipulation

path

bytes

within

computations

words,

swapping

on
the

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two halves

word,

and

microinstruction

addresses

backpanel

the

bus

operations

word.

transceivers

other

using

the

also

supplies data

for

number

transmission

subsystems.

Data

subsystems passes through the transceivers and
the

memory

path

via

buffer

MB,

which

available

and

over

from

1is

the
other

held

the

data

that

the

LBM.

The microcontroller

addressing
the

from

field

also organized

1logic selects a location

contents

that

1location

wvia

in a

loop

in the control
the

RAM,

and

microinstruction

skipping

actual

address

dispatching

subroutine,

for

but

and

which

This information includes
specification

commands

the

not

of conditions

to call

addressing

return

for

from

1logic employs a

stack.

Together

the

control

two

functional

lohp;

parts

the processor

also

form

The 96-bit microinstruction register not

only supplies a number field as a quantity to the data path,
but

its

1individual

that govern operations

path.

bits

feed a multitude of control

in every nook and

the opposite

direction

cranny of

the data path

lines

the

data

supplies

various conditions'to the microcontroller address logic

for

skipping

the

individual

and

dispatching,

program

but

instruction

principally

words,

taken

supplies

from memory

for

execution

Following

power

the

turn-on,

using

some

CRA

board

the

12-bit

microcontroller.

the

backpanel

load

segments.

the

console

boots

bus

lines

and

transceivers

into

the

control

data

microcode

Following

the

and

system

starting

RAM

the

console, the miérocode initializes the machine,

setting

various

a workspace

the

constants
RAM

can

various

file,

and

respdnd

general

procedures

with

the

that

enters

that

from

all

cases

microwords

the

save

that

location

and

halt

loop

microcode

upon

2xecutes,

executing

are

program

associated
To

the

execute

address

address
in

the

receipt

program

retreival

one

the

some

for

plus

which

There are

microinstruction

determine

to memory,

the

program.

the

these

count

stores

actually

path

from the console.

running

data

address

then

that

commands

instruction,

program

tables

procedures

but

Instructions,
control

separate

instructions,
way

and

the

file,

send

instruction

word, place its left half in thé instruction register.
this

available

the
the

AC,

index

microcontroller

instruction code

selects

which

supplies

turn

quantities

the. address

through

skipping

out

carry

all

and
of

and

the

location
a

operations

are

logic,

the

dispatch

ROHM,

word.

Using

these

sequences

dispatching,

fields

address

dispatch

1logic

f-/?

indirect

From

the

control

necessary

and

the

microcode,
the

data

path

execute

the

instruction.

Figure

5.2

shows

The

ten

29@1s

two

extra

bits

the
but

the

left

The

adder

mixers,
a

word

file

end

from

right.

and

the

adder

two

DPM

adder)
use

for

words

the

The

file,

can

VMA,

these

are
the

extra

words

from

output

direcor
t

shifted

includes

page

table

the

via

address

DP.

For

VMA

indicates

cache

part

the

When

the

reference

bits

16-26 of

the

rest.

RAM

virtual

with

hit,

and

file

1is

the physical
Associated

the

a word

place

also

any

left

shifted

output.

memory

cache

address

directory;

table

and

are

both

a match

the