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DEC-11-HBMAA-E-D

January 1975

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Document:	BM792 Read-only-memory and MR11-DB Bootstrap Loader
Order Number:	DEC-11-HBMAA-E-D
Revision:	000
Pages:	45
Original Filename:	http://bitsavers.org/pdf/dec/unibus/DEC-11-HBMAA-E-D_BM792_Read-only-memory_and_MR11-DB_Bootstrap_Loader_Jan75.pdf

OCR Text

DEC-I1-HBMAA-E-D

BM792
read-only-memory
and MR11-DB
bootstrap loade"r

digital equipment corporation • maynard, massachusetts

1st Edition, July 1971
2nd Printing, December 1971
3rd Printing (Rev), October 1972
4th Printing, December 1972
5th Printing, May 1973
6th Printing (Rev), January 1l)74
7th Printing, August 1974
8th Printing, January 1975

TIll' matl'rial in this manual is for informational
purposes and is subject to change without notice.

Printed in U.S.A.

Th~ following are trademarks of Digital Equipment

Corporation. Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

CONTENTS

CHAPTER 1 INTRODUCTION
1.1
1.2

1-1

SCOPE
GENERAL DESCRIPTION

1--\

CHAPTER 2 DETAILED DESCRIPTION
,~. 1
"

.~ . .3

2.4
~.5

BASIC OPERATION
ADDRESS SELECTION
, WORD SELECTION
DIonE MATRIX AND OUTPUT BUFFER
ANODE RECOVERY CIRCUIT

::1
2-\
., ,
.. - ~"

CHAPTER 3 PROGRAMMING AND OPERATION
3.1

.L2

3-1

GENERAL
PROGRAMMING THE ROM

3-1

CHAPTER 4 ROM ENGINEERING DRAWINGS
APPENDIX A BM792-YA PAPER-TAPE BOOTSTRAP LOADER
APPENDIX D BM792-YB BULK STORAGE BOOTSTRAP LOADER
APPENDIX C BM792-YC CARD READER BOOTSTRAP LOADER
APPENDIX D MRII-DB BULK STORAGE BOOTSTRAP LOADER
APPENDIX E BM792-YF BULK STORAGE BOOTSTRAP LOADER
,\PPENDIX F BM792-YH CASSETTE BOOTSTRAP LOADER

ILLUSTRATIONS
Figure No.
2-1
2-2

2-3
2-4

2-5
2-6

3-1

Title
ROM Block Diagram
ROM Address Word Format
Simplified Logic Diagram of ROM Address Selection Circuits for
Addresses 773400 - 773476
Word Selection Circuit for 773X04 Address
Diode Matrix and Output Buffer, Simplified Logic Diagram
Anode Recovery Circuit
Physical Locations of Addresses and Bits in the ROM Diode Matrix

iii

2- t
2-2

2-3
2-4

2-5
2-6

3-3

TABLES

Title

Table No.
\- t

Pn.·programmed ROMs

~-I

ROM Addn~ssl's

Page

1-2

'- .,

B('I) Ikcolkr Truth Tahk

A-I

BM 7l) ~- VA Pap~r-Tap~ Bootst rap Loader l')rogram

A-3

B-1

BM79::!-YB Bulk Storage Bootstrap Loader Program

B-~

C-I
\)-\

BM792-YC Card R~ad~1' Bootstrap Loader Program
M R II-DB Bulk Storage Program Loader Listing

('-3
\)-3

D-~

Starting Address

0-4

0-3
E-I

Power Up Start Vector Jumper Connections

D-4

BM792-YF Bulk Storag'~.Bootstrap Loader Program

E-2

F-I

BM792-YH Cassette Bootstrap Loader Program

F-2

CHAPTER 1
INTRODUCTION

1.1

SCOPE

This manual provides the lIscr with theory of operation, programming information, and schematics necessary to
understand and program the BM792 Read-Only-Memory (ROM). The level of discussion assumes that the reader
is familiar with basic digital computer theory.

Although the input and output signals of the ROM are carried by the Unibus
it is beyond the scope of this
manual to describe the Unibus itself. A detailed description of the Unibus is presented in the PDP-Ii Peripherals
Handbook.
1.2 GENERAL DESCRIPTION
The BM792 is a 32-word read-only-memory (ROM). The diode matrix and address selection circuits that constitute the ROM are mounted on an extra-width quad-board module. This module is inserted in either one of the
two small peripheral controller slots in the PDP-II processor or in one of the four slots in the DD-II peripheral
mounting panel.
The ROM is available either unprogrammed (designated BM792) or preprogrammed (designated BM792-Y X.
where the letter in the X position identifies the program). The unprogrammed module can be programmed to
form code conversion tables or contain frequently-used mathematical values and subroutines. These applications
of the ROM provide an access time of 100 ns, which can increase the program speed.
Preprogrammed ROMs are used for implementing small standard programs required in PDP-II System opl'ration.
such as bootstrap loaders for paper tape or DECtape. The preprogrammed ROMs that are available at puhlication of this manual are described in the Appendices and listed in Table 1-1. As additional preprogrammed ROMs
become available, additional appendices will be published to describe them.

@. Uni~us is a registered trademark of Digital Equipment Corporation.

1-1

Table I-I
Preprogrammed ROMs

Module

M792-YA

.......

Option

BM792-YA

No. of Words.

Power-Up
Vector

I Address-. Range

773000-773077

! No. 01 Worth

I
I

Devices

I{cad-In

Loading Area

KL nL-A,

I ()2 max.

Highest Memory

DL-B, PC, PR

I
i

M792-YB

BM792-YB

773 I 00-773 I 77

TC, RC, RF,
RK, RP

256

o and up

M792-YC

BM792-YC

773200-773277

CR, CM

Variahle

Variable

M792-YD
M792-YE

MRII-DB

773 100-773277

Yes (Except TM)

TC, TM, RC',
RF, RK, RP

TM:256
Othcrs:512

o and up

M792-YF

BM792-YF

773200-773277

TC,RK,RF

25()

o and up

M792-YH

BM792-YH

773300-773377

Yes

V allu up

(\ ~-..I , , -

CHAPTER 2
DETAILED DESCRIPTION

2.1

BASIC OPERATION.

Th~ ROM diode matrix contains 32 16-bit words, ~ach of which can be applied to the bus under program control.

The ROM responds only to a DATI from the Unibus, DATO, DATOB, and DATIP are ignored. A block diagram
of the ROM is shown in Figure 2-1.
When both a DATI and a ROM address '}fl' sent to the ROM, the word in the addressed location of the diod~
matrix is applied to the Unibus. When th~ ROM address is received. the 5-bit,code on address linl's AO I through
A05 is decoded to apply a signal to the cathodes of the diodes in the addressed word location. The word in the
addressed location is transferred through the output buffer to data lines DOO through 015 of thl' Unibus.

~----------------~.---------

~______~ADDRESS~______~
A <06: 17> SELECTOR
ANODE

UNIBUS

DAT I
MSYN
SSYN

~-..----'

A <01:05>

SELECTOR

RECOVERY
SIGNAL

32 x 16
DIODE
MATRIX

-----+

OUTPUT
BUFFER

WORD
CATHODE
DRIVER
SIGNAL

D<OO: 15>

1\ -02 99

Figure 2-1

2.1

ROM Block Diagram

ADDRESS SELECTION

TIll' addr~'ss \\onl formal for the ROM is shown in Figure 2-2. Octal addresses for the ROM must he or the
--:-JXXX j'orm:lt. Thc ROM reads-out only full 16-bit words and docs not issue byte data; thus, address hit AOO
j.., Il () t lI,>~.'d,

(he addr\.'..,\c:-. arc i'urtiler divided into eight groups, which are determined by address bits A08, A07, alld AO() ;lI1d
li-,kd ill Tabk' 2-1,

2-1

WORD
ADDRESS
OCTAL
ADORES S

GROUP

0-7

SELECTION
8x4 =

0-7

------~

0-7

r-~r--~~"---------'---"'~~

ADOREB~~ \17 \16\15\14\13\12111

\10

\09\08\07106\05\04\03102\ 01\
11-0298

Figure 2-2

ROM Address Word Format

Table 2-1
ROM Addresses
Preprogram med

Address Word Bit
A08

A07

A06

Address Ranges

773000 - 773076

BM792-YA

773 100 - 773 I 76

BM792-YB, YD

773200 - 773276

BM792-YC, YE, YF

773300 - 773376

BM792-YH

773400 - 773476

773500 - 773576

773600 - 773676

773700 - 773776

ROMs

In a PDP-l 1 Syst~m. only ant? ROM module can be used for each of the eight address groups. Jumpers on the
module art? connected in a configuration that causes the module to respond to its designated address group.
For exampk. when a ROM modull' is to be addressed in the group 773400 - 773476, bits A08, A07. and AO() of
the address word contain binary 100 as shown inTable 2-1. The bus lint's for these bits an: shown COt1Ill'dl'd to
the circuits of the ROM in Figure 2-3, a simplified logic diagram of the address selection circuits. Figure 2-3 abo
shows the address selection circuit jumpers connected to respond to address group 773400 - 773476. Asserted
bus lilll'S arc low and ullasserted bus lines arc high, so that the output of gate F 12 at pin 14 is high and the outputs
of pins .2 and 3 arc low when a valid address is received. Each of the three outputs from the E 12 gates is exclusive
NORed with a low or a high level, depending 011 the jumper configuration. The outputs of the three E 13 gates
must ill' high to accomplish address selection; therefore, the jumper configuration shown responds to addresses in
the 773400 - 773476 group.
The signal, which results from the decoding of bits A08, A07, and A06, is gated with a signal generated by the
decoding of an address in the format 773XXX and receiving MSYN (Drawing D-CS-M792-0-1). The resulting
signal (pin 10 of gate E 17) is gated with a signal generated by the decoding of a DATIon the control lines.
Therefore, pin 8 of gate El7 provides a low output signal when the ROM address, MSYN, and DATI are asserted
on the bus. This signal at pin 8 is uscd to accomplish thc following in thc ROM circuits (sec Drawing
D-CS-M792-0-1 ):

I.
}
3.

Assert SSYN on the bus.
Activate the word selection circuits.
Provide a gating signal to the output buffer.

2-2

+ 5V
NO __

;9
-

eN 2 BUS AO 8 L 10

E 1;>

~~~.
______ _

W3
~~._~_-=-~~

~ 9

E13 TRUTH TABLE
EXCLUSIVE NOR

+5V
JUMPER

PIN'~7_-~
------1

CP2

BUS A07L

E12

+5V

ABC

C U 1B
- U-S-A-O-6-~f--3_ _ _-____
W_'_ _2-/)
11-0297

Figure 2-3 Simplified Logic Diagram of ROM Address Selection Circuits
for Addresses 773400 - 773476
2.3 WORD SELECTION
Bits AOS - AO I of the address word are decoded by the word selection circuits to select Olle of the 32 word locations in the diode matrix. A low-level signal is then applied to the diodes in the addressed word location, resulting in 16 bits of data being read out on the data bus lines.
Because address bit AOO is not connected to the ROM, byte addressing is ignored and a 16-bit word is read onto
the bus regardless of the state of AOO. In the octal coding of the address, AOO is considered in designating the
last octal digit. Therefore, the addresses of the words in the ROM use the following sequence:
773XOO
773X02
773X04
773X06
773XIO
773X12
etc.
An address of 773XO 1 would address the same location as 773XOO, and 773X03 would be the same as location
733X02.
A simplified logic diagram for the word selection circuits is shown in Figure 2-4. This diagram illustrates how
the circuits operate for a 773X04 address. Table 2-2 is a truth table for the Binary-Coded Decimal (BCD) decoders that are shown in the diagram and on Drawing O-CS-M792-0-1.
For address 773X04, binary code 000 lOis applied to the word selection circuits on address lines AOS - AO I as
shown in Figure 2-4. The D input of BCD I receives a low signal from the address selector circuits when addressing and bus signal conditions are satisfied. All inputs to BCD 1 are low with the result that output 0 is low (refer
to Table 2-2). Output 0 of BCD I is connected to input 0 of BCD 2. The other inputs of BCD 2 are as shown in
Figure 2-4 when address 773X04 is received. Table 2-2 shows that output 2 of BCD 2 is low with the input signal
configuration shown. Output 2 of BCD 2 is connected to the cathodes of the 16-bit positions of location 04 in

2-3

the ROM. The signal levels on the cathodes of the other 31 word locations are high. Thus, only the diodes in
location 04 arc forward-biased, allowing the word in this location to be read by the output buffers and applied to
the Unibus.
TO CATHODES
OF DIODES IN LOCATION 04

773X04

° IH' ~us '0' L ~ EIG
, (Ll

BUS A02 L

Y---------.--. ---------------.-------

ABC
L
H
L

D
L

-~1:3------_-----

_~~ _ _ _ _ _ _

o (HI

BUS AOI L

O(H)

J!~A04L;al1

~---.
E 14

L
.f-C-13=--_ _ _ _ __=_;

o (H)

BUSAOSL;GS
E 14
.f-"':3_ _ _.--J
4

L
L

B EI8
BCOI

FROM

s~~~~ig~ ----,-L70Wc:-:-:W
7:CH
:":"":E::-:"N:-7==7=-=3::-:"X7:C
X X:-:-:"A"::"O=-=DR=-=E::::S"::"S,---'
MSYN. 8 DATI ARE RECEIVED
"-0296

Figure 2-4 Word Selection Circuit for 773X04 Address

2.4 DIODE MATRIX AND OUTPUT BUFFER
The BM792 ROM is supplied with a complete diode matrix. A diode is wired into each of the 16-bit locations
of all 32 words. The binary content of each word is determined by the presence or absence of the diodes: thus..
the lIser can program the module by cutting Ollt selected diodes. Presence of a diode in a bit location produces
a binary 1 and absence produces a binary O. The pre programmed ROMs are manufactured with the diode con-

figuration required for their programs.

A simplified logic diagram of the diode matrix and the output buffer is illustrated in Figure 2-S. The low output
buffer gating signal is present when the ROM address, MSYN, and DATI are asserted on the bus (refer to Paragraph 2.2). Th.e word select signal is low when the particular word location is selected by the decoding of bits
AOS - AOI (refer to Paragraph 2.3).
Diode D492 for the DO I bit is in the circuit and is forward-biased. Therefore, a low level is gated with the output buffer gating signal,which results in the assertion of a low level on bus line DOl to signify a binary 1. The
diode for the DOO bit is cut out of the circuit. Therefore, a high-level signal is gated with the output buffer gating signal, which results in the assertion of a high level on bus line DOO to signify a binary O. The remaining bit
positions in the word are read out on bus lines D02 through DOIS at the same time. The configuration of diodes
for the bit positions of the word determines the binary content of the word read out on the bus lines.

2-4

Table 2-2
BCD Decoder Truth Table
Input
A

II
L

H
H

L
L

H
H

H
L
H

L
H
H
L

L
H
L

H
L
L
L
L

L
H

L
H
L
H
·L
H

H
L

H
H

Output

L
L
L
L
L
L
.H
H
H
H
H
H
H

H
H
H
H
H

H
L

H
H

II
H

II
H
H

H
H

H
H
H

H
H

L
H
H
H

H
H

H
H
H

H
H

H
H
H
H
H

H
H
H
H
H
H
H

H
H
H

H
H
H
H
H

H
H
H

H
H

H
H
H
H

BUS DOl

H
H

H
H
H
H
H

H
H

L= Low
H = High

TO REMAINING
DIODE POSITIONS
OF THIS WORD
ANODE
RECOVERY
SIGNAL

+5V

LOW
OUTPUT
BUFFER
GAT I N G
51 GNAL

I
R15

0495

1 OUTPUT
0492

RIG

10
BUS 000
0 - - - - - 0 OUTPUl

0528

DIODE
CUT OUT

LOW
WORD SELECT
SIGNAL

Figure 2-5

II - 0295

Diode Matrix and Output Buffer, Simplified Logic Diagram

2-5

2.5 ANODE RECOVERY CIRCUIT
The anode recovery circuit (see Figure 2-6) provides a voltage surge to the anodes of the diodes in the matrix
immediately after a word is read out. This voltage surge charges the capacitance of the diode in the matrix and
ensures that the anode lines in the matrix are at a high level for the next read out.
Transistors Q I. Q~. and QJ (St'e Figure ~-6) art' tUflll'd 01'1' when thl' ROM is IIl)1 being addn.'ssl'd. Pin ~ llf F I 7
gOt'S fWIll low tn high wlll'1l the bus addressing signals arc conduded. The high signal turns on Q 1 and subsequently
Q2, which provides the positivr voltage surge to the anodes of the diodes in the matrix.
Transistor Q3 of the anode recovery circuit is used as a clamp. When the voltage surge from the collector of Q2
reaches a high enough value, Q3 turns on and grounds out the surge.

+5V
+5V
R25
2K

+5V
02

R24

R26
47

1.5K

8.2K

~-""""r-_ _" " " _ -

) 01

+5V

TO ANODES
OF DIODE
MATRIX

R28
100

R27
100

11-0367

Figure 2-6 Anode Recovery Circuit

2-6

CHAPTER 3
PROGRAMMING AND OPERATION

3.1

GENERAL

The ROM operates in a manner similar to other memory devices that can be included in a PDP-II system. When
the ROM is used for storage of constants, the processor may be programmed to address the appropriate ROM
location for the required constant. When the ROM is used for storage of a subroutine, a jump instruction is used
to get into the subroutine and place the first address in the program counter. Then the program counter is
changed to address the other sequential steps in the subroutine. The last step of a subroutine stored on the ROM
should be either a jump instruction to a location out of the ROM or a return from subroutine instruction.
3.2 PROGRAMMING THE ROM
Programming the ROM is accomplished by cutting diodes out of the diode matrix in the configuration required
for the binary data words to be used. The diode must be removed for each bit position that is to read out as a
binary O.
The physical orientation of the diode matrix with respect to the addresses and the bit positions is shown in Figure
3-1. Address 773XOO is shown with diodes removed in a configuration that reads out the binary word 1 010010
011 101 011. With Figure 3-1 and a binary listing of up to 32 16-bit words, the user can program his ROM module.
The ROM module must also be programmed to respond to one of the address groups determined by address bits
A08, A07, and A06 (refer to Table 2-1). Figure 3-1 shows the locations of the three sets of address-bit jumper
terminals which are labeled WI, W2, and W3 on the ROM printed circuit board. The relationship between the
jumper tenninals and the address bit is as follows:
WI
W2
W3

A06
A07
A08

Jumper wires are connected across each of the three sets of jumper terminals on an unprogrammed ROM when it
is shipped from the factory. The jumper wire must be cut out from between the two terminals '[or each address
bit (A08, A07, or A06), that is a binary 1 in the ROM address used.

3-1

W3 (A08)
JUMPER
TERMINALS

. W2 (A07)
JUMPER

TERMINALS

W1 (A06)
----JUMPER
TERMINALS

101

000

1
---I

DATA WORD FOR ADDRESS
773XOO FOR DIODE
} CONFIGURATION SHOWN
Figure 3-1

Physical Locations of Addresses and Bits
in the ROM Diode Matrix

3-3

CHAPTER 4
ROM ENGINEERING ORA WINGS

The following engineering drawings are applicable to the BM792 ROM:
Title

Drawing No.

Rev.

Page

ROM Diode Matrix M792

D-CS-M792-0-1
D-CS-M792-YA-I

4-3
4-5
4-7
4-9
4-11
4-15

ROM Diode Matrix M792-YA
ROM Diode Matrix
ROM Card Reader Bootstrap
ROM Diode Matrix
ROM Diode Matrix
ROM Diode Matrix
Cassette Bootstrap ROM

D-CS-M792-YB-I
D-CS-M792-YC-l
D-CS-M792-YD~1

D-CS-M792'-YE-l
D-CS-M792-YF-l
D-CS-M792-YH-l

4-1

A
A

4-19
4-23

BK2----""l
BL2------1
BM2~

BN2------1

BP2----""l
BR2 --------'

BS2----""l
5

1-"--+-_ _+-____---"'-1

BTz------l

cu: -=-BU:..:S__IW-=--::6-=.L_ _":-=Cl

BUS AIIL
CLI -=---'----'--=------+:=.('j

L-_---ir-_ _ _ _.:::124

EYi
sJ

INDICATED:

<11 :SPLIT LUGS. ---- :JUMPERS
CAfJlCITORS ARE .Olul, IOOV, 20"1.
RESISTORS ARE 8.21<, V4W, 5%
DIODES ARE 0664
E2, E4,E6,ES,EIO, EI2, E14. EI5.EI6:DEC:380
E17' DEC7400N
EI, E3, E5, E7, Ell: DECSSSI
E13: DEC8242
E9- DEC314
E18- E?2: DEca251

--'-_-+---'=c

CFI _ _ _+-_B::::U::S'-'-"A0:..:2:.=L_ _

BUS Mil L

CHI

---+----------+-=c

~I~ I~~~~V ON DEC38J, DEC314
~:~ ~4.' G'N~V ON DEca8SI, DEC8242, ceC7400N
: : ~6: ~~v ON DECS251

E19- 22 PINS 6 AND 7 NOT CONNECTED
EI8 PINS 4,5,6,7,9 NOT CONNECTED
WI, W2., W3 DESIGNATES WIRE J .....PERS

CVI -==-+-4--'«'i

4-3

BK2----,
BL2---.J

:===:!
BP2===:!
BR2

=2==:J

F---+--------:.:'-Ityd

OTHERWISE INDICATED'
=SPLIT LUGS, ----- = JlJ,IPERS
CAPACITffiS ARE .OIUF,IOOV.20"lo
RESISTORS ARE B.2K,1/4W,5%
DIODES ARE D664

E2, E4,E6, EB,EIO,EI2, EI4, EI5, EI6 = DEC3aO
E17=DEC7400
£1, E3,E5,E7, Ell' DEC888I
E13' DECB242
E9= DEC314
EIB- E22' DECB251

CFI

CHI

~:~ ~::riri ON DEC380,OEC3I4

BUS
A04L

~:~ ~4== ~V ON DEC 8881, DECS242,DEC7400
~~ k6; G~b\l ON DEC8251
EI9-E22 PINS 6AND7 ARE NOT CONNECTED
EIB PINS 4,5,6,7,9 ARE NOT CONNECTED

BUS
eVI

A05L

4-5

0;:.2

CK2
CE2
::02
CCi
COl

eEl
e"l
CPI
CRI

BUS C00L
BUS Ar'~
BUS Ai6L
BUS AI5L

E51

BUS AlZL
BUS AI7L
BUS .... StU L
BUS AI4L
B~S l,;~'1

61<2--BUS Af)9L

3L2SWZ---,

CN2

8"'2-----'

BelS A08L

9P2---,
BR~----.i

852---,
8T? -------.J
CP2

CUI

eLi

BUS A07L

BUS A06L

BuS AIIL

r-------------~

+5'1

CA2
0A2

AI>2.

GNC
AC2,ATI

azCTI~~~--~---4---4--~-~--~~~--~~~~~~~--~----~~~--~
OC2,DTI

UNLESS OTHERWISE INDICA TED:
0-SPl..ITwGS, ---- -JUMPERS
:A!'IIIOTORS ARE .Oluf, 100'1, 2O%.
RESISTORS ARE 8.21<, I14W, 5.".
DIODES ARE 0664
E2, E4,E6, ES,EIO, E12, EI4, E15. E16- DEC380
E17. DEC740QN
EI, 0, E5, E7, Ell' DEC8681
El3· DEC6242
E9= DEC314
E18 - E22 • OECB251

CFI

j4: :..~V ON OEcaaal, DEC8242, DEC7400N

'~~

EI6

SUS 1101 L

CH'

~:~ 1~~t~V ON DEC38O, DEe314
~~

_ _ _+---'S::.,:'.I:.:S_A:.;:0::2:=L______--+---":...;

--.-/

I:
i

BUS

CU2

AeJ4L

: : : : ; : ON DEC6251

£19- 22 PINS 6 AND 7 NOT CONNEC TED
£18 PINS 4,5,6, 7, ~ "lOT CCHlE:TED
WI, W2, W3 DESIGNATES WIRE JIMPERS

CVI

Lb~:.~-=_-=_ =
__==t-=±::~·~~==l====---:::±--=

l _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ._._ . - - _ _ _ _ _ _...J

.============

n;:r-~------------------------

-- - - - - -

4-7

BUS S SYN L

CJI

CF2 BUS CIIlIL

CJ2
CK2

CE2
(!)2
CCI
CD!

GEl
CKI

cpo
CRI

BUS COOL
BUS Al3L

BUS Al6L

BUS AI5L
BUS Al2L

BUS AI7L

BUS MSYN L

BUS AI4L

BUS A/0L
BUS Afl9L

:===:J
BMZ----,
BNZ-----.J

CN2

BUS A(II8L

BP2===:J
BIlZ
BS2===:J
BT2

CP2

BUS A07L

WI
CUI

BUS A06L

12
CLI

BUS AIIL
13

GND
AC2,ATI

~,crl~~~--4----4---4--~--~--~---4--~--~--~~~--~---4~~-'--~

OC2,DTI
UNLESS OTHERWISE INDICATED:
0=SPUT LUGS, ---- =JUMPERS
CAFl\CITORS ARE .Oluf, IOOY, 20%
RESISTORS ARE a2K, I14W, 5%
DIODES ARE 0664
EZ, E4,E6,E8,EIO, EIZ, E14, E15, EI6=DEC380
E17· DEC7400N
fl, E3, f5, E7, Ell = DEC8881
EI3 = DEC8242
E9' DEC314
-EI8- E22 = DEC8251

;:~ 1~~t~V ON DEC38D, DEC314
~~ ~4: ~~V ON DEC888I, DEC8242, DEC7400N
::: : : :,;: ON DECa251
E19- 22 PINS 6 AND 7 NOT CCNNECTED
EI8 PINS 4,5,6,7,9 NOT CCltIr<ECTED
WI, W2. W3 DESIGNATES WIRE JLMPERS

-+__~

~~____~__~B~US~~==~______

S_ A
CFI _ _ _+-_B;:.:Uc::
..::0:.:2;::L_ _ _ _-+---"=a

BUS MIL

CHI-----+-----------------r~~

BUS
CU2 A04L

BUS
~I A05L

4-9

8
TlVlesr..irIf.IId~,~-""''''thI~
.rtyo'DiICaIl[~Cor~ancf~~.

.--

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NOTES:

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I

I. FO,#!, DIODe i.OCRTION.5 SEE

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ETCH BOARD REV

IE I

P~RT NO.

DESCRIPTION

FIRST USED ON OPTION MODEL

PARTS LIST

DRN.("};/-J.

.f:

D.\TE?Z

r--------t-----tr------t--------"bu;;.~."'<';.:;,:.:.:~lis;;-rl-;:..:;~

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I PM E NT
CORPORATION

r----t----Jt-----t--~~9j~~2~..;{::;;;·~I4~-~i._-4D.\g~~E2h~,rrmn]li.P===:.::M::::
••H:::.....
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RESPECTIVELY EXCEPTIONS ARE STATED ABOVE

! i

IC PIN LOCATIONS
DEC fORIl NO

DItO'USA

'Ol

~ --f-

t=Z:..:..N:...::3:..:~:..:.3::..:9.'-'='8~....:S.=-A:..:.M:.:...6::........-t!--_ _ _+-___-IB_ DD -M RII-D B
DEC NO

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SEMICONDUCTOR CONVERSION CHART

MATRIX
I~D£I

111£'1;

NUMBER

:DICSIM792-YJ-i
A '}
DISTill I I I I I I T t ,

4-11

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CF2 BUS C0Il

CJ2
CI<2

CE2
CO2
CCI
CDI
CEI
CKI
Cpt
CRI

BUS COOL
BUS AI3L

BUS Al6l
BUS AI5l
BUS AI2 L

BUS AI7l

BUS MSYN l
BUS AI4l

BUS AI0L

BK2-----,
BL2------1

BUS A09l

BM2-----,
BN2------1
CN2

BUS A08L

BP2~
BR2------1
BS2-----,
BT2------1

CP2

CUI

BUS A07l

BUS A06l

12
13

~
""2

+5V
CA2
QI\2

AA2

i:I'
io
>-

.
N

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AT2

INDICATED:
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~CITORS ARE .Oluf, IOOV, 20%

RESISTORS ARE 9.21<. I14W. 5%
DIODES ARE 0664
E2, E4,E6,E8,EIO, E12, E14, E15, E16= DEC380
E17= DEC7400N
EI, E3, E5, n, Ell: DECSS81
E13: DEC8242
E9 = DEC314
EI8- E22 = DEC8251

~:~ I~~;~V ON CEC380, DEC314
~~ ~4:= ~~v ON DEC8S8I, DEC8242, DEC7400N

eFI

----+--=:....:::=-----+--'::q

CHI ----+--~~~------+-::q

BUS

CU2 A04L

E19- 22 PINS 6 AND 7 NOT CONNECTED
EIB PINS 4,5,6,7,9 NOT CONNECTED
WI, W2, W3 DESIGNATES WIRE JlNPERS

CVI A05L

~6: :;.,~ ON DEC8251

BUS

-<.." ~

_"'''ROM DIODE MATRIX
DEClOD"

---

2N!009

EQUiPMENT ...• """"
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.r6n perl'l'1tU1Otl

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11/45

ETCH BOARD REV

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A

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a

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RESPECTIVELY EXCEPTIONS ARE STATED ABOVE

IC PIN LOCATIONS

PART NO.

ITEM
NO_

PARTS LIST

I I I 111 I I 111
DRNaxki

IItO-DO-OEQUIPMENT

~;hz

I~ r-=f-f- ~=========~=========~=========t=========t~~~~~~,~-::-~~7~_~.~~=.'~lZ~A~~~~v.~_TiIn:TLi~==m==.=~=,-,::=.o",..=~=~=:::.:.R=••A=c~. :}=.'?=,~=." "1- A

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8
7 ,
6
.
5
.
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,
3
.
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I
1

4-15

CF2 BUS C01L

CJ2
CK2
CE2

ccz
eel

COt
eEl
eKI
ePI
CRI

BUS C00L
BUS Al3L

BUS AI6L

BUS AI5L
BUS Al2L
aJS AI7L

BUS MSYN L

BUS AI4L

BUS Al0L
BK2-=:=J
BL2

aJS A09L

BM2==:J
BN2
BUS A06L
CN2----

BP2==:J
BR2
BS2==:J

BT2
eP2

CUI

CLI

BUS A07L

BUS A06L

BUS AIIL

GND
AC2,ATI
CC2,CTI -~T-~DC2,DTI

......-~_.......- .....-~___......_~_~_+_~_+-_-......w.4_---l
INDICATED: J

0=SPLIT WGS, - - - - :JUMPERS
~eITORS ARE .Olul,

IOOV, 20"10

RESISTORS ARE 8.21<, V4W, 5%
DIODES ARE 0664
E2,E4,E6,E8,EIC, EI2, E14, EI5, E16: DEC380
E17: DEC7400N
EI, E3, E5, E7, Ell: DEC888;
E13= DEC8242
E9 = DEC314
EI8- E22: DEC8251

eFI

CHI

~:~ I~ =Gt~V ON DEC380, DEe314
~~ j4:= G~~V ON DEC888I, DEC8242, DEC7400N

: ~6: ~f;'

CU2

BUS
AI!l4L

ON DEC8251

E19.., 22 PINS 6 AND 7 NOT CCJIINECTED
EI8 PINS 4,5.6,7,9 NCT COf.t.lECTED
WI, W2, W3 DESIGNATES WIRE JlHPERS

CVI

BUS
A05L

4-17

8
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.......... theprop-

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c ,sn OrGITAL

NOTES:
ON ITEM -1Ft:) USc OVERLAY TO DETERMINE
WHICH c08 DIODES OF DI THRU D529
fiRE USED.
ON ITEM */3 ALL 9 CHIPS MUST B£ EITHER

EGU :PME~T CCRPCRATlON

COMBINATIONS ARE: NOT ALLOWED ON THE ,sAME:

OPTlOIY.

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DATE
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••
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~ =;.
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DEC NO.
EIA NO,
DEC NO,
EIA NO.
SCALE
~;., ~ '"'1 ~ 5
SEMICONDUCTOR CONVERSION CHART
SHE£'!'! ~ z...

IC PIN LOCATIONS

"'r- ~

~TE"

PARTS LIST

C\.:~i~ ~ >-t!.' .J:c~ ., ~ ~ ~2;----.:---------j_r-------------it1t-_:-_;;.-_;:-~-~-;;'tt-;:-;;-;~--;-;:--f~:~~:;/f::;.~
E~~~'~./-" " . .u~ ,1'/~1~ ,2~.~-~iZ~:~:~: ROM DIODE MATRIX
~I

GND '-"'0 5V ARE USUAl.LY PIN 7 ,,"0 14
RESPECTIYE~r EXCEPTIOfIS ARE STATED ABOVE

III: ~

PART NO,

DESCRIPTION

REF DESIGNATION

I FIRST USED ON OPTION MODEL

liTEM

t-mc:r;::;:r--~=p;;----,-......ii"'-t

IDiesl M792~UYF I
OIST.

I I

I s·

1 J J J 1 J

4-19

BUS S SVN L

CJI

CF2 BUS C01l

CJ2

CI<2

CE2
CD2

eel
COl

CEI
CKI
Cpt
CRt

BUS COOL
BUS Al3L

BUS Al6l

BUS AI5l

BUS Al2l

BUS AI7l

BUS M5YN L

BUS AI4l

BUS AI0l

:=::J
:=::J

BUS A09L

BM2----,

BN2---1
CN2

BUS A08L

852----,

BT2---1

CP2

BUS A07L

WI
CUI

Cli

BUS A06L

~
31

~+----+--------~ ~4

BUS AIIL

'------+----..::::..l.12
~

~
EI3
II

______~__________~13 824

C25

22Qpf
5"10

GND
AC2,ATt
CC2,CTI
De2,DTt

-....,=-r--.....

R23
100

.......--......- ......-__4_____4......._+-.......-

----_--+--4~--

......--~..""iov_....- -

BUS Aa..

CFI ____4-__~B=US~A~0=2~L_______+--~

CHI _____4-__~BU~S~A0~IL~_______+_~d

BUS

CU2 A04l
BUS
CVI A05l
14 B EIB

8251

4-21

3
f-fI7NDLE rLIP CHIP

NOTES:

/. FOR DIODE LOCATION 5
SEE
ETCH
BOFtRD SV£RI..RY.
c. ALL DroD~, CATHODE FIICE ~IGHT -tts. W'3 .INSERTED aNt. y

JJI
+

-t

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-m28 -02G2- -0229- -ilI96-D4~
-0228-

-RZ8-RZ7-

Eeo

IREF

--!l323- --!l29O- -0257-

+
-R4- -R3- -R2- -11<165- -0132- -099- -06&- -033-DI3i-0163-· ~30- --re?- -064- -oot-ilE2-

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-047'51-;)418-D5IO- -0477- -o-c«- -0411- -Il378-

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-0372-

(J 2't

CI7P. SfO¢ A/.III" /00 v 5' % OM /0000 ?i__ . j '
CAP.

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'/1- W S %
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R24f

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---

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-{K8-

-0132- -DI49-

~AP. 22.¢ .1.1.111" loa'/" sYo DM

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HISTORY -.---~~MH-.M7"-'t
i£rcHED CIR.CUIT B017RD
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90083:;7-04

~SS'q'DR'LLING HOLE LAYOUT

.~II"lGElVT.A

X-YCOORDINATE HOLE LOGAT/ON K-CO-M792'YH-l ""

REF

-0275- -!l242-02704- -0241- -03»-

--0306- -0273- -iJ240-

-D470- -D437-

-aaD6-oZ7t- -0236- -il205-!l237-

-01«)-

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-Qi06-

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--05-0l0I- -DQ1- --£85-

-cz--

'g'g ~ 'g~ 'g"
h"
'~" I t~ B~'~· 0
lj U} L

'OE9 14

EI2q4U

111....---.---.1'
~.
~1.~ O________________C___ /O.4~
l,---i

_____

,..
A

REF

.1
OTY

L FIRST USE 0 ON OPTION MODEL
I I rO

REF DESIGNATION

DESCRIPTION

TEN
NO.

PART NO.

PARTS LIST
ETCH BOARD REV

I E' I

"B__ ~g~~;R~~,~~_·~A
~------~------_ir-------1_------_l,I~~,~~~.J~~~~A~I~~~i~:~~~~n~~~~~·~-~._.._..~o_M.~

l* ~ t--------t-------t-----r------1::I~~;.:·(w::.J==~·
=;=-~~~~»¥_l/~7J

1
I~.
IS ~ r-------t----1t~--t_--1,1~'~~,..,....~/',::!:I_~W.;~~i..m.@j CA SSE TT E
r . ;

':'14

IC TYPE

8
8

GND

+ 5V

i:;c ~
I

1.(5V,-

.-,.-

J 5

IC PIN LOCATIONS
Ole fOA .. NO
010 LJ!iA

I:)

1~5

GNO A"IO ~v AIlE USUALLY PI'j 7 AND 14
RESPECTIVELY EXCEPTIONS ME STATED ABOVE

"/1 •

DATE

•._.c_""_··_..

mLE

'ii/ .

~1r:~;--t:;;t3;~~---I--i.~~~~~·-;~):""".s-..~~~.;t;I~~f7J.~ BOO TS T R j, P
'~:I.

m:% 0,"

Dti64-

DEC3009B2N3&H

2.N3'3 ~ B

SA ME

DEC NO

EIANO

DEC NO.

EIANO.

SEMICONDUCTOR CONVERSION CHART

~~I~

I "NEXT HIGHER ASSY

ReM

-+----+-

SHEET

01'

I=:=::o-r---..".",,=---r~~
"UMBER
nv.

A-Pl:BM792~YH s!"lEj~'

SCAlE

Dies, M792 YH-I
01ST·1 _l -'
I I I I

4-23

II ... 11-HA~6LIA4 1~£121

C24

56Qpf

~
2

1312

BUS

13 DIS

AD2

[1(;28

6.8.1
35V

I0"Io

B
GND
.QC2,ATI
a::z,CTI

DC2,DTI

Cl6

t r
C26

6.8uf
35V
10%
-~

BUS A82L

CFI

CHI

BUS
CU2 AI/l4L

BUS
CVI AIl5L

CHI(

I
J

,.. ..... ..,
C. 117

~______~2 0 3.~IO~~========================================~================~________________J

It£VISIONS
CHANGE NO

JREV

I
6

I
5

f"HF' M792-YH-l
_e"

IDlesl
_111:AL1

NO N E

OF 2

I"EV.

I DIIT. I I I I I 1 I ITT

4-25

APPENDIX A
BM792-YA PAPER-TAPE BOOTSTRAP LOADER
.

The BM792-Y A ROM is shipped with jumper wires connected for address group 773000 - 773076, and its diode
matrix is pre programmed for a paper-tape bootstrap read-in· loaner program. The BM792-YA can only be used in
a PDP-II System that has at least 4K of read-write memory and either a Teletype@ (KL I I) or a high-speed papertape reader (PR II or PC 11), or both. If neither the high-speed reader nor the low-speed reader (Teletype) is
available. the paper-tape bootstrap loader program will not function properly.
An absolute loader or dump program contained on a bootstrap format paper tape (described in Chapter 5 of the
Paper-Tape Sof/ware Programming Handbook, DEC-II-GGPA-D) is loaded into read-write memory by the papertape bootstrap'loader. The sequence of operations used by the paper-tape bootstrap loader is:

Determines which paper-tape reader is available. Checks the high-speed reader first and then the lowspeed reader. The high-speed reader is considered unavailable if no tape is in it.
Determines the size of the read-write memory of the system.

Stores the device address (determined in Step I above) in the last location of read-write memory.
This action is required by the absolute loader program.

Loads the absolute loader program from the bootstrap format tape into the read-write memory.

Jumps to program loaded, as specified on the bootstrap format tape.

The paper-tape bootstrap loader program and the absolute loader program require the use of 96 locations at the
high end of the read-write memory. Memory locations 4. 14, 16, 20. and 22 are modified during the operation
of the paper-tape bootstrap loader program. Also, the illegal memory reference (bus time-out) trap at location 4

is used ex tensive Iy by this loader.
A program listing for the paper-tape bootstrap loader is provided in Table A-I. Hardware addresses in the PDP-II
usc 18 bits with the result that bits A 15. A 16, and A 17 are considered in designating the most significant octal

digit of the address. The software assembler program uses 16-bit addresses so that only bit A] 5 is used to designate the most significant octal digit of the address. Therefore, the addresses in Table A-I are listed as 173XXX
instead of 773XXX.
The operating procedure for loading a bootstrap format paper tape with the paper-tape bootstrap loader is:
Step

Procedure
Set the HALT/ENABLE switch to HALT, then to ENABLE.

Place the bootstrap format paper tape in the reader to be used, with the special tape
leader placed over the read head.

If the high-speed reader is to be used, set the switch to ON.

@Telctype is a registered trademark of Teletype'Corporation.

A-I

· Step

Procedure

If the low-speed reader is to be used, set the high-speed reader switch to OFF and
set the low-speed reader switch to START.

S. :t till' starting addn.'ss. 77jOOO. into thl' SWITCH RFGISTFR.
Dcprl'ss ti, ..' LOAD ADDR swikh.

Depress the START switch. After a short pause, the paper tape should read in.

A-2

Table A-I
BM792-YA Paper-Tape Bootstrap Loader Program
'Rt:GISTE~S

J00212'2
7001Z1:.::3

t73~.36

1730 4 "
173,,42
173,,44
1731346
17'31/l~21

173;!52
173e54
173~621
~ 73Z62
~7'3a66

17301"
173072

173014
173076

SP~"6

IOnICr;' POI~tER
,S HCK PO I'JTER
,PQOr:RAM COUNTER

HSRII1775~0
l.SR·1715~0

'~J~W SPlED READER A1DRESS
'L~W SPEEO REAOE~ ADDRES~

flC.'"

1715'0
177560
,112701

'l.60iOIH':

~127~2

"'0121006
173100

POI~TER

,TrMPORARV STORAGE
,TfMPORAkV STORAGE

R3-"3
Fl4d4

.:0Z0~~41

,)000<16
J0QHP7

1730el0
17311104
173010
11'3"14
173016
1731/12"
173022
17302"
173e26
17303£1
17;,;:,32

,A~CqESS

Rl-"1
R2."2

(j000~1

SHIHI

"IOV
"'OV

#16001110,Rl,
'~., R2

ISET

tT~Ap

~EMORV ~HECK '-l~ITS
VEC'OR IS ~O~ T ON 'lIb

~0'211

I~e

123221
"£11366
105222

eMf'£;!

R2,'3~'

A~E

,-OOP

TO OEvlCE AJD~ESSES
ICLEAR THAP STATUS AT ~O~A'l~N
,SET TRAP ADD~~SS IN LOCATtO~ 4
IS£T U~ STACK OUT or T~E ~'Y
IGfT DEVIC~ ADDRESS
IC~tCK AVAILABll,.lTY or DEVICE
,BPA"CI-I IF' f.lSR IS OUT ~r TAPf IBIT ~~)
IRrsrT T4AP ADDRESS AT ~OC'T!ON 4
ISPE~IAL ADDHESS U~ED AS MAS~ ~ATl~
'D~ ME~ CHKI READER STATUS A~DRES5 15 ~OV(~
,5fT RiaX7752, MASK IN S.'~4
,5 TOQE OWN AODRESS I~ POtNTlQ
,GFT BYTE POINTE~
,ENAFIL.E HEADF.RITr~T DONE BIT (BIT 071
IWAI· VNTI~ qEADY
IT~EN 'lCK IT UP A~D 5TOQE IT
,BUMP P01NTE~
JSTOQE~ JU"IP OFFSET?
I NOT Vf:T

(H2)'"

J HS,

,I12n3
1105012
,'U742
1121H6
:1413['4
l05714
100175
"1" 7 12
:'127:'0
:l,~4 41

MOV

DEVil

~00142

,R2

"IOV
"'0"8

PIf,-(I'(2)

"'0"
TST
RMt

"Ov
"'OV

'4~6'\1

,1'1('1111
:111;:'2
'1052141
11215714
103376
116"12

LO~PI

'OEV.~,R"5

CI,..

PC,sP
_(R3),R'l

l'H4

DE-Vi

r-tt,'R~

IiIZ4,S,",

"'011

R4, .. (1«1)

tqe
MOV
MOV

SP,R1

INC

IIH(4

Fq,,"R~

9Rl,Ril

TSTB

lIH4

~OVB

2IR4),_H2
"'Hi

fin

I~CB

JMP

,-2

.IR21

,p~t~TrR

IG~

Al.L. OO'IJ[

EXECUTE AS

BRA~CH

'I,.Ow S~EtO RtAOER
IHJG~ SPlED ~EADER

1715621
171550

A-3

APPENDIX B
BM792-YB BULK STORAGE BOOTSTRAP LOADER

The BM792-YB ROM is shipped with jumper wires connected for address group 773100-773 176, and its diode
matrix ispreprogrammed for a bulk storage (disk or DECtape) bootstrap loader program. The BM792-YB is
used in a PDP-l I Systeril that has at least 4K of read-write memory and one or more mass storage devices, such
as disk or DECtape.
The actual bootstrap loader program, stored in the first 256 words of a disk or DECtape, is transferred from the
device into rcad-write memory by the BM792-YB program. The transfer is started from location 0 of the device.
and the loaded routine is assumed to be operative at read-write memory location O. The BM79:!-YB program
jumps to location 0 after a satisfactory completion of the transfer, so that there is automatic starting of the
actual bootstrap loader program. If error conditions occur during the running of the BM792-YB program. the
program starts over again.
The sequence of operations used by the bulk storage bootstrap loader is as follows:
I.

It lktermines whether the device is a disk or DECtape from the address set in the SWITCH REGISTER.

If the device is a DECtape transport, it moves the tape until the front endzone is sensed.
3.

It rcads 256 words stored in the device, starting with address 0 of the device.

The loader then stores the 256 words in read-write memory sequential locations, starting with
location O.

The loader checks for errors and starts the program over if any errors occur.

The loader then jumps to read-write memory location 0 for automatic starting of the actual bootstrap
loader program.

A program listing for the bulk storage bootstrap loader is provided in Table B-1. Hardware addresses in the PDP-II
usc 18 bits: thus. bits A 15. A 16. and AI 7 are considered in designating the most significant octal digit of the address. 'The software assembler uses 16-bit addresses; consequently, only bit A I 5 is used to designate the most significant octal digit of the address. Therefore, the addresses in Table B-1 arc listed as I 73XXX instead of 773XXX.
The operating procedure for use of the BM792-YB bulk storage bootstrap loader is as follows:
Step

Procedure
Set the HALT/ENABLE switch to HALT, then to ENABLE.

Set the ROM address, 773 I 00, into the SWITCH REGISTER.

Depress the LOAD ADDR switch.
(continued on next page)

B-1

Step

Procedure

Set the address of the word count register of the disk or DECtape to be used into the
SWITCH REGISTER. Th,e standard addresses for the word count registers of the DEC
devices are as follows:

777450
777462
777406
776716
777344

RCl] Disk
RFl] Disk
RK] I Disk
RPl] Disk
TC 1] DECtape
5

Depress the START switch. The disk or DECtape data should then read into the readwrite memory.
Table B-1
BM792-YB Bulk Storage Bootstrap Loader Program
J REGISTER ASSIGNMENTS:
000000 R0=10
000001 Rlall

173108 013701
177570
173104 000005- BEGIN:
113186 010100
173110 0.12710
177400'
173114 020027

MOV

U177570"RI

,READ SWITCH REG FOR ••••

RESET
MOV
MOV

RI"R0
#-256. ,,'R0

'FORCE CLEAR IF RETRY
' •• ~.DEVICE WC ADDRESS
JSET TO READ 256 WORDS

CMP

R0,,1I77344

JlS IT DECTAPE?

BNE
MOV

START.
14002,,-(R0)

INO. GO TO START
JYES. MOVE TAPE TO FRONT

TST
BPL
TST
BPL
CMP
MOV

IR0
• -2

'WAlT FOR ERROR 1

~(R0)

BEGIN
(R0)+,,(R0)+
IS,,-(R0>

JIS IT ENDZONE?
JNO. TRY AGA IN
'ADJUST POINTER
'NOW START ACTUAL READ

tR0

'WAIT FOR DONE

1773~4

173120 001007
173122 012740
004002
173126 005710
173130 100376
173132 00574e
173134 100363
173 I 36 022020
173140 012740 START.
000005
173144 105710
t73U6 100376
173150 005710
173152 100754
173154 105010
173156 000137
000000
000001
BEGIN
START

000004R
000040R

T3TB
BPL
TST
BMI
CLRB
JMP

.-'2

'R0
BEGIN
@K0
"0

JERROR ENCOUNTERED?
JIF SO START OVER
JFOR OECTAPE"STOP TRANSPORT
JGO TO ROUTINE LOADED

.END
1<0

x%000000
000062k

B-2

=%000001

APPENDIX C
BM792-VC CARD READER BOOTSTRAP LOADER

The BM792-YC ROM is shipped with jumper wires connected for address group 773200-773276. Its diode
ma trix is preprogrammed for loading binary data into the PDP-II memory from cards using the CR 1 1 or eM I I
Card Reader. If tht' data represents a PDP-II program, the program can be automatically started upon completion of loading. The BM792-YC is used in PDP-II Systems that have at least 4K of read-write memory and a
card reader.
On the card that is read, each pair of columns (column I and column 2; 3 and 4; etc.) beginning with column I
contains two 8-bit bytes which represent one 16-bit word. Also a control bit can be contained in the second
column of a pair. The eight bits that represent each byte are punched or marked in rows 2 through 9 of each
column.
The first column of a pair contains the high-order byte (PDP-II bits 15-8) of the word and the second column
of the pair contains the low-order byte (PDP-II bits 7.,.0) of the word. A control bit punched or marked in row
o of the second column of a pair designates that the word in those two columns is a new Loading Address. Each
Loading Address must be equal to zero modulo two because loading must begin at a word boundary in memory
rather than a byte boundary. Loading is accomplished one word at a time, thus a new Loading Address can
appear anywhere on the card. However, a Loading Address must be in the first two columns of the first card
read.
The absence of control bits in rows 12, II, I, and 0 of the second column of a pair designates the word as a
Data Word to be loaded into the PDP-II memory. The Data Word can represent a machine instruction or data.
After each Data Word is loaded into memory the current loading address is incremented by two.
A control bit in row I of the second column of a pair designates the word as a Transfer Address. When a Transfer
Address is read, the bootstrap program issues a RESET and branches to the Transfer Address. The card which
contains the Transfer Address passes through the card reader, but no other Loading Addresses or Data Words are
read from it.
A program listing for the card reader bootstrap loader is provided in Table C-l. Hardware addresses in the PDP-II
usc 18 bits; thus, bits A 15, A 16, and A 17 are considered in designating the most significant octal digit of the
address. The software assembler uses 16-bit addresses; consequently, only bit A 15 is used to designate the most
significant octal digit of the address. Therefore, the addresses in Table C-I are listed as 173XXX inste~d of
773XXX.

C-I

The operating procedure for use of the BM792-YC card reader bootstrap loader is as follows:

Step

Procedure
Set the HALT/ENABLE switch to HALT, then to ENABLE.

Load the input hopper of the card reader with the cards to be read.

On the card reader set the MODE switch to REMOTE.

On the card reader depn~ss the RESET switch and observe that the associated grel'n
indicator lights. The card reader is now on-line.

Set the starting address, 773200, into the switch register.

Depress the LOAD ADDR switch.

Depress the START switch. After a short pause, the card reader should read the data
on the cards into the computer memory.

C-2

Table C-l
BM792-YC Card Reader Bootstrap Loader Program

1
2
3

;CR BOOTSTRAP

•5

~ 73221"

6
7
8

- :"~?~0

'4:'1002:

"~t:'Il1:~0
:"Jl'I~11I1

:-C?Je02
:'/1(11111113

~"'""0~4

13
14
1'5
16
1.7

00Q1~"I7

1771 60

1732110
173202
1732('16
17321'"
l73214

<'1
il2
23

!7~216
17~22~

:73,22

~ 7322 4

'6
?7
'6
29
l~

!7323e'
:73232
17323 4
:.73236
1732 4 0
1732 4 2
~7't244

:'~'~00!:>
'127~0

:1(102'1
-'3:?721
~ '1371
'" ~ 210

17,32 4 6
i732~2

~:::142'5

173254
173256
17321>e
173262
173264
173266
173272
173274
173276

"~:30Z2

.""

42
43

042l021~

"'O;l~4

";:1421~

1 1 57U
1;}:l373
,""1<'3:"3
151111:3
1:H772
121?!>1

1771~e

. ~~2ZIl1

"31Ql27
{,c 13?;,1

RESET
MOV
MOV
fl! T
BNE
NEXTC: INC
NEXTV: CLR
CL.R
TESTCD: BIT
BNE
WAITCI T5T8
QPL
SWA8
91S8
COM
8MI

0,"002'1

CMP8
BEQ
BCT
MOV

"l;'3~2
,~ :!'~7'57

:"1"1322
n0755
,~31e'27

r.:-:1175
i'Me05

,)ATAI
0 4 01:)"0

,l:?'J113
"(l"lI1'U

f1IT~o

0i.:04~0

E' IT~9

001030
0400210
177160
173262
173216
173220
0"00217 R

8IT1'
CRS
':lAT.

"JElCTC
"EliTV
PC
Q1

Rl
"2
i::4

!,'TART

1732~0

TE"TCO
TRAN~F'
l~

II I TC

TRANSF":

t-IQV

aIT

8EQ
RESET
JMP
.ENO

*CRS.
R0.

FI"
Rl

*B!~08IBIT09,(R1)·

START
(iIIR0
R3
Roll
~R0,

"JEXl('
GtRI1I
TESTCD
R3
(iIIR1,
Roll
WA PC
~PC,

nln.

leRl)

TRA~SF

DATA
R3.
NEXTV
R3.
NEXTV
taR0,
TRAt-./H
(ltR3

0~00210R
0~11I0hR

0k:11I01l2 R
3C00Z3R
01:00Z4 R

ICR STATUS REGISTER ADDRESS

START:

":''1~'3

11
,'2
~5

,-173200
9P08:40'"
BIT09"1000
BI Tl'h40000
R0="0
R1=U
R2=%2
R3="3
R4="4
PC="7
CRS=177160

""'14""0

173224
1732~6

173232

C-3

RI!
(R2).

'BIT1.

:C~EAR A~L PRESENT DEVICES
:~OAD STATUS RECISTER 'DORESS

:MOVE TO Rl
: ~EST CR RUDY AND GET CRB ADDREIS
lAND WAtT 'OR REAOV, ON-\.IN£
lRUO A CUD
lCLEAR OAT' CONTENTS
lAND COLUMN ;LAG
liS CARD DONE 'L4C SET
IYES, READ A C'RO
lIS COLUMN READY 'LAG lET
INO, WAIT ,OR COLUMN AND/D~ CAIIIO DONE
I~EARRANGE THINGS
lAND GET THIS COLuMN
liS THIS SECONO COLUMN or 'AIR
1~IRST, GET ANOT~EIII
ITEST HIGH BYTE 0' CRB
IROW 1 IS TRANlrtR 'LAG
IROW ",1-e IMPLIES DnA
:OTHERWISE Rowell 1"'1'1.1£1 LOAD ADO
lAND START NEW PAIR
ISTORE DATA 'WOAD
lAND GET NEW COLUMN PAIR
IWAIT 'OR CARD DONE
lIN A TIGHT LOOP
ITHEN CLEA~ CR 'LAGS
lAND TRANS'ER TO LOADED PROGRAM

APPENDIX D
MR11-0B BULK STORAGE ·BOOTSTRAP LOADER

The MR II-DB is a 64-word bootstrap loader for the following bulk storage control devices: RFII, RK 11, TC 11,
TMII, RP II, and RC 11. This option can be used in any PDP-II system. It includes a 'feature of special value to
PDP-II /45 systems that are equipped with MS 11 Semiconductor Memory (MOS or bi-polar) Systems. On those
. PDP-II /45 systems, the KB 11-A start vector for power up can be selected for bootstrap load from any of the
above-listed devices, except the TM 11, which loses vacuum on power fail.
The MR II-DB option consists of two programmed ROM diode matrix modules. The M792-YD ROM Diode
Matrix stores the first 32 words of the bootstrap loader program at addresses 773100-773176. The M792-YE
ROM Diode Matrix stores the second 32 words of the bootstrap loader program at addresses 773200-773276.
Table 0-1 is a program listing of the MRII-DB Bootstrap Loader program that is encoded on the two ROM diode
matrix modules. PDP-II hardwar~ addresses use 18 bits. The software assembler uses 16-bit addresses. Therefore. the addresses listed in Tabir 0-1 ure listed as 173XXX, instead·of 773XXX.
KEY START LOADING
Operate the MR II-DB Bulk Storage Bootstrap Loader as follows:
1.

Set the HALT/ENABL switch to HALT, then to ENABL.
Set the console switches to the starting address assigned to the selected bulk storage device control,
as listed in Table 0-2.

Press LOAD ADRS.

Press START.

The processor will start executing the bulk storage bootstrap loader program at the selected address. The program loads the first 512 words or bytes from unit 0 into memory, starting at memory location O. After the
bootstrap is loaded from the bulk storage device, the loader program causes the processor to start executing the
bootstrap at location O.
NOTE
When magnetic tape is the bulk storage medium, magnetic
drive unit 0 must be selected and positioned at the load
point.
Loading from Disks - The program starts at the selected address, then branches to a common routine that resets
all Unibus devices. Thus, disk address registers and current memory address registers are initialized to O. The
pointer to the device's word count register is located in R I. Then, the word count register is loaded with the 2s

0-1

complement of 512. The device command to read and go is issued to the device command register. As the 512\vord record is read into memory from the disk, the loader program checks for errors. If an error is detected,
the entire routine is repeated, starting at the selected address. When no errors are detected and the last word has
been transferred, the PC is cleared. and the bootstrap is executed, starting at memory location O.
Loading from Tapes - The program starts at the selected address for DECtape or magtape; then branches to a
common tape routine which first resets all the device registers. Then, the device's word count register (or byte
count) is decremented by one. If the routine is entered from the TC 11 address, a first command is issued to rewind the DECtape to the forward end zone. If the routine is entered from the TM 11 address, a first command is
issued to advance the magnetic tape one record. After the specified operation is done and checked for errors, the
program branches to the common disk loading routine that reads a 512-word or byte record into memory from
thc selected tape storage device.
POWER UP LOADING
The MR II-DB provides for automatically loading a bootstrap program from a pre-selected bulk storage device
during the power up sequence. This feature is provided for PDP-I 1/45 systems with MOS or bipolar memory
and no power backup. The KB I I-A Central Processor Unit in those systems has a start vector jumper field located on DAP module M81 00. Table 0-3 lists the start vector jumper connections required to select thc specific
MR II-DB starting address for each type of bulk storage device.
START VECTOR PROGRAM OPERATION
The start vector jumpers on the DAP module select bits SY(07:00) of the start vcctor. Bits SY(OI :00) are always

O. High-order bits of the starting address arc generated by CPU sign-extension logic, blocking bits 11 and 8. A
hard-wired addre~s 773XXX with the SY(07 :OO} offset is generated. The power up sequence uses the resultant
address to load. the PC and PS from the address pointed to by the start vector.
For example, jumper selection of the RK II provides start vector 260. The resultant address, 173260, accesses a
location provided by the M R II-DB. to load the PC with starting address 173110 and thc PS with 000340. The
bulk storage program loader proceeds to load a bootstrap from the RK 11. with thc CPU operating at priority
level 7. which preVt'nts extanal devices from int·errupting the program.
INSTALLATION
PDP-I 1/45 Systems -Install the M792-YD and M792-YE modules that comprise the MRII-DB option in two of
the three spaces reserved on the CPU backplane for small pcripheral controllers. The quad-height slots are designated .26, .27, and 28. Refer to Table 0-3 and remove jumpers W I through W6, as required, from the OAP
module to select the bulk storage device that is to provide the bootstrap program during power up.
NOTE
The TM 11 must be restarted manually, with the tape
drive positioned at the load point. Therefore, power
up start vector selection is not provided.
Other PDP-II Systems - Install the MR II-DB modules on a DD Il-A Peripheral Mounting Panel that is connected to the Unibus by an M920 Unibus Connector module.

D-2

Table 0.:1
MR II-DB Bulk Storage Program Loader Listing
1 3lt1
1 31;::
1 31':1
1 31::
1/3l1ii
1~311~

1~3.1~
1~311~

~"':l .. :'5

MOV
BR
177406

TClll

\'~71417

MOV
AR
1773·\4

"-:'!:1C' ~5

1773 44

,114:;,'?3
L~24e'?'~

1(313~
1~314~

"~~4121

1~314~

(l\6"(/'~3

1/j14c:
1'314~

1/31;\(,

1~315~
1 / 315"

1 hl50
1~31"~

1 / 310<::
1i316"

11f'17"2

;16l1 12'11
r0"l2~11l
1~';?:;'<l

4 23
176716
,7 ",~

,;l,l2~0

,1~57212i

~"'5311
~?'5720

r12~4l

.'31:,"11
~"'1776

1~3.::21~

f'157,20

1~3<:::0~

r'31V',41

11'3('100

TAPES:

0:""'(,,25

"12~Qll

173;::~~

QP1l1

"1"!7l2

1/31 H

1; U7~
li31?'"
!.i3170
1;3;::;::

TMlll

172524

li316§

11~14~6

MOV
RR
172524
611J11J11J3
60011
2f1li1J
1000rl10
MOV
8R
176716
RESET
MOV
rST
MOV
OEC
TST
MOV
sIT
9EQ
TST
8IT
BEQ
JMP

l(~q~

f'I'?'~112

AGAIN:

1(3<:::1~
1~3<:::l~

1n1 0e1
, ,71"''''3 4 0

RF'vEC:

RF'11
340

RC111

MOV
BR
177450

OTHER:

RESET
MOV
TST
MOV
MOV
MOV
BIT
BEQ
BMt
CLR

~<:::2

(110702

~~2

C!'l~401

3<::2

17 7 45e

1 3('2

~'H:'t"eI~5

3~3

~1"2~0

1 3<::3
1 3c3
1 3~3
1 3~4
1 3<:::4
1 3;::5
1 3<:::5
1 3~:5

1
1
1
1

3<:::5
3~6
3~6

3~6

1 3<::6
1 3;j:7
1 3~7
1 3~7
1 3e::7

(~(?I57?0

e!121Z2!1
0.112711
0112' 4 1

1 710"fIl

~32711

1rl1Jc2lfll

~?1775

lCiR757
;,,~5IZ1Z7

02":1000
17311rz'

RKVEC:

0(!1~340

173220
t!lM3 40
1731 54
M'2I3 4 111
1731 20
0!'ln3 4 rz'
C":'lllZ!2'l

,rtXED f.lEAD OISI( (256KW)

%7,"?'
OTHER

'MOVING HEAD DISK (CARTRJDGE)
ICOMMAND WORD

%7,"2
TAPES
IADRS OF WORO COUNT
ILAST COMMAND
JrIRST COMMAND
'DONE MASK
IERROR MASK

4003
10002l11J
2411J0'"

1:"?'~, 21;'

1/313~

'" , "2
OTHER

""''''Z'15

1~312~
17312~

qR
17 7 462

RI(111

:'\ 1'~ 7 1 2

1/3l31/:
1~313~

~10V

ll2' 7"'2
":,"':14 45
1774;'6

1/312;.

1~~12"

Rrl11

ll-;,1n2

;';1:1451
17 7 462

RCVEC:
RPVEC:
TeVEC:

Ql
RK11
340
RC11
340
RPll
340
TCll
340

%7,,,?
TAPES

"7,"2
OTHER

IADRS OF BYTE COUNT
'LAST COMMAND
IrIRST COMMAND
'DONE MASK
IERROR MASK
'MOVING HEAD DISK ("Aetc)
ICOMI<IAND WORD

%2,":l

"")
(fIl)·,"1
(1)

(0) •
(0) •. - (11
(0), (1)
.-2
(fIl) •
(Ill) , - (1)

OTHER
(2)

(5 )

JS nlE RESET

IGET H~E ADDRESS or THE 8RANCIoI
,,,0 TO POINT AT LAST COMMAND
IGET nlE WORD COUNT ADDRESS
ISET UP rOR ADVANCE 1 RECORD
IMOVE "0·TO FIRST COMMANO
ICOMMAND WORD TO COMMAND REG.
ILOOI( rOR OONE INDlCATORS
INONE SET, TRY AGAJN
IDONE "IRST COMMAND, C~[etc rOR ERROR
ILOOK F'OR SET [RROR BITS
INO ERRORS
TRY nlE RUD
IRERUN rCR ERRORS

I RF'l1 "OWER uP VECTOR
%7,"2
OTHER

IF'lXED HEAD DISK (UKW)
JADR5 OF" WORD COUNT (COMMAND·2)
'COMMAND WORD (5) IS T~E RESET

%2 ",0

(111) •
(fIl).,"1
#-1000, (1)
(0) ,- (1)
#1fIJ1Zi200, (1)
,-4
AGAIN

,,,0 TO POINT AT WORD COUNT ADRS
IPOINT TO ADDRESS
IWORe COUNT ADRS TO "1
ILOAD WORD COUNT
ICOMMAND TO COMMAND REGISTER
'CHECK rOR ERROR OR DONE
J I". NEITHER. K[E" 1.00KING
IERROR, TRY AGAJN
IrtLLER
JRKll POwER UP VECTOR
IRCa POWER U" VECTOR
IR"l1 "OWE" U" VECTOR
J TCll

,END

D-3

"OWER UP VECTOR

Table D-2
Starting Address
Bulk Storage Device Control

Starting Address
( octal)

RFII (for RSll DECdisk)
RK II (for RK02 DECpack)
TCII (for TU56 DEC tape)
TMII (for TUIO Magtape)
RP I I (for RP02 Disk Pack)
RC I I (for RS64 DECdisk)

773100
773110
773120
773136
773154
773220

Table D-3
Power Up Stmit Vector Jumper Connections
I

Bulk Storage
Control Device

Power Up
Vector Address

RFII
RKII
Tell
TMII
RPII
RCll

773214
773260
773274
None
773270
773220

Jumpers 011 DAP Module
WI

In
Out
In

Out
In
In
In
In

Out
In
In

Out
Out
Out

In
In
In
In
In

Out
Out

In
Out

Out
Out

MAINTENANCE
Diagnostic program MAINDEC-II-DZMRA-D i.s provided with the MRII-DB Bulk Storage Bootstrap Loader
option. The diagnostic program can be used to troubleshoot and maintain the MR II-DB hardware. The available tests are:
PRGO: Logic Tests
PRG I: ROM data dump
PRG2: Single ROM address read data loop
These tests can also be used to check data reliability and as a post-installation checkout procedure. Complete
operating procedure is described in the MAINDEC description supplied as part of the diagnostic program
package.
Module schematics, parts lists, and component location drawings for the M792-YD and M792-YE ROM Diode
Matrix modules are located in the MRII-DB engineering drawing set. Module Schematics of the two modules
are also provided in Chapter 4 of this manual.

D·4

APPENDIX E
BM792-YF BULK STORAGE BOOTSTRAP LOADER

The BM792-YF ROM is shipped with jumper wires connected for address group 773200-773276, and its diode
matrix is pre programmed for a bulk storage (disk or DECtape) bootstrap loader program. The BM792-YF can
only be used on a PDP-I 1 System that has at least 4K of read-write memory and one or more masS storage devices, such as a disk or DECtape.
The actual bootstrap loader program, stored in the first 256 words of a disk or DECtape, is transferred from the
device into read-write memory by the BM792-YF program. the transfer is started from location 0 of the device,
and the loaded routine is assumed to be operative at read-write memory location O. The BM792-YF program
jumps to locll;tion 0 after a satisfactory completion of the transfer, so that there is automatic starting of the actual bootstrap loader program. If error conditions occur during the running of the BM792-YF program, the
progr(im starts over again.
The sequence of operations used by the bulk storage bootstrap loader is as follows:
1.

It determines whether the device is a disk or DECtape fronl the address set in the Switch register.

If the device is a DECtape transport, it moves the tape until the front end zone is sensed.

It reads 256 words stored in the device, starting with address 0 of the device.

The loader then stores the 256 words in read-write memory sequential locations, starting with location O.

The loader checks for errors and starts the program over if any errors occur.

The loader then jumps to read-write memory location 0 for automatic starting of the actual bootstrap
loader program.

A program listing for the bulk storage bootstrap loader is provided in Table E-l. Hardware addresses in the
PDP-II use 18 bits; thus, bits A 15, A 16, and A 17 are considered in designating the most significant octal digit
of the address. The software assembler uses 16-bit addresses; consequently, only bit A 15 is used to designate
the most significant octal digit of the address. Therefore, the addresses in Table E-I are listed as 173XXX instead
of 773XXX.
The operating procedure for use of the BM792-YF bulk storage bootstrap loader is as follows:
Step

Procedure
Set the HALT/ENABLE switch to HALT, then to ENABLE.

Set the ROM address, 7732XX, into the Switch register.
XX
Equipment
00
RKll Disk
06
RFII Disk
14
TCII DECtape

E-l

(continued on next page)

Step

Procedure

Depress the LOAD ADDR switch.

Depress the START switch. The disk or DECtape data should then read into the
read-write memory.

Table E-J
BM792-YF Bulk Storage Bootstrap Loader Program
'REG~STE~S

1n2~0

173204

.'121"'1

1732~6

:'121kll
:l~04"'2

173220
173222
173224
173230
173234
173236
173242
173244
173246
1732!:121
173252

0~~0'1'5

173254
173260
173262
173264
173266
173270
173272

17H~6

"l:I04~5

173212
173214

~12101

USED

Rh%
Rh"1

:)0"21,210
J01HH'l1

RKBOOTI "10V
~R

17746(!
177.544

RF'800TI

MOV

'~77.~2,~1

HlGIN

[)T900rl "'OV
REG 1"41

*~n.ra6,Rl

BEGIN
'1773~~,Rl

RESET

Isq 1.11' f-I1(11 ADDRESS

,SET UP RF'11 AODR(SS

,Sn UP OECTAP£

~DDRE:SS

MOV

Jq.R~

,SET WORO COUNT

312710

177/1::,'

~OV

1I-~'Sf, •• PF<V'I

,Tr

~20"21

171344

eMP

R0, 'H7344

,IS THIS OECTAPE SOOT?
jlr "'OT. SKIP SEAReH coor
,SEARCIoI BACKiIIARD

~101;.10

HNE:

SYAAT

MOV
TST

IIIHe

U'~376

BPL,

TST

.,,2

-eR0)
H~GIN

n202"

BPI..
Ct-1P

~~U~1

!2l12740
::H"7UI

004ii1"2

JQI,,40
Ul0363
;:11214"
U51112J

(HH') '"''

START I

~oV

TSTB

*~BQl2,,,(P0)

(Hill)., (Rr;'Ih
*~, .Oelll)

IIIH"

,-2

Ul~376

tJPL,

<HI5?10
Ul12'1!>4

TST

IIIH",

8M!

JMP

·'0

FlESET

~00"2'5
~~('I1J7

t~ 0Vl '" '" iii

E-2

G1~I

RF~n

25~

~rkDS

IL.OOP UN!l~
I ERROR n.AG
Ilr NO' 'END ZONE' ,

,TRY AGAIN
IRESF'T Rill

, 155 11 £ READ COM~ANO
ILOOI' UNTIl.
IRE'A"Y
IIF' rRROR,
,TfltY Ar;A1N
IS'OP ANY !A'E MOTION
,GO TO TH[ BOO!

APPENDIX F
BM792-YH CASSETTE BOOTSTRAP LOADER

The BM792-YH ROM is shipped with jumper wires connected for address group 773300-773376, and its diode
matrix is preprogrammed for a tape cassette (TAII/TU60 Cassette System) bootstrap loader program. This
quad-sized module is one of the Small Peripheral Controllers (SPC) and can be mounted in any SPC slot in a
DOll-A. DDII-B, or most PDP-II family processors. Any PDP-II System that has 4K of read-write memory
and a cassette can use the BM792-:-YH.
The actual bootstrap loader program, stored in the first 128 bytes of a cassette tape, is transferred from the
cassette into read-write memory by the BM792-YH program. The bytes are consecutively read from the cassette
and loaded into memory locations 0 through 177 (octal). When the loading is complete, program control is
transferred to location 0 so that the loaded program can be executed. At the point when the program control
is transferred, the cassette is positioned at the end of the second block of the first file so that the loaded program
call continue to read in additional data.
The sequence of operations used by the cassette bootstrap loader is as follows:
1.

The cassette is rewound and then spaced forward one block. This action skips the header block
(normally 32 bytes) associated with the first file and positions the tape at the second block of the
first file.
The BM792-YH program consecutively reads 128 bytes from the cassette tape into read-write memory
locations 0 through 177 (octal).

The first byte read is compared to octal 240 (NaP) and if it does not equal octal 240, the program
comes to a halt at location 173350. To restart the program from this halt, the CaNT switch is
depressed.

After the 128 bytes are read, the loader program checks the TA II error bit (block check error, offline error, etc.) and if an error is detected, the program comes toa halt at location 173350 and can
be restarted by depressing the CONT switch.

If no error is detected, program control is transferred to location 0 to execute the loaded program.

A program listing for the cassette bootstrap loader is provided in Table F-l. Hardware addresses in the PDP-II
use 18 bits; thus, bits A15, A16, and Al7are considered in designating the most significant octal digit of the
address. The software assembler uses 16-bit addresses; consequently, only bit A 15 is used to designate the most
significant octal digit of the address. Therefore, the addresses in Table F-I are listed as 173XXX instead of
773XXX.
The BM792-YH program has no provisions for initializing the system since it does not issue a RESET instruction.
Initialization is necessary because other devices may issue interrupts or an internal processor option may be enabled. When the BM792-YH program is started from the console, initialization is performed because the START

F-l

Table F-l
BM792-YH Cassette Bootstrap Loader Program

1
2
3
4
5

17330'"

""0"~"
"002101
"""002

"000213

""ee'"
9 11330a 13127021 177!:>el0
1'" 1733214 "",,,1"
1733m6 211"701
j

17
18
19
2'"

23
24
25
2(>

173310
173314
17332~

PC.",

11 ?" .,..,.
~~

.....

HO~D~ AOr.RES5 OF TAll
JSEI.ECT UNIT 2ERO
JUSE fOR PIC
RESTRT, MOV PC,R1
ADD #TABL.E •• ,f(l ,Rl HCLD~ ADDRESS OF COMMA~D TABLE
,MEMORY POJ~TER AND DATA F~AG
MOV "375,R2
JMOVE TE~T BITS TO RJ
MOVB (Rl'+:R3

112110

L.,OOPll

1021413
1321310

L.OQP21

12
13
14
15

R0.XeJ
Rl-Xl
R2."2
R3."3

0627~1

12!12702

173322
173324
173326
173330
1,73332
3,73334
173336
173342
11334J6

120337
""1761

173350
173352

~il0"021
~0"755

173354
173356
173360

"05710
1"0774

CSOOTI

MOV #17750m,R~
CL.R

MOva (R1) +, CR(1) JMOVE COMMA~Q rROM TA~~E To TAll
,Ir CO~MA~n IS N~GATIVr, THEN ~UTT
8Ml DONE
ITEST REAOV ANn T~ANSFERREQUEST 61TS
BIT8 RJ,(R~)

"01776

SEQ L,OOP2

10"712
1162112

aM I I.OOPl

~tTS ARE NOT SET
;ADVANCE MEM~RV POINTER
J IF' MIN US, T ~ Y AN CTHE R TAB L. E

CMPB R3,1iD#0
SEQ L.OOP2

,fIRST BYTE ~EAD SHOULD BE '24~'
.IF ~QUAl, G~ REA~ A~OTHER BYTE

INCa R2

1215202

29
31

32
3~

34
35
36

173362
173362

STOPl

17·3364
173366
173371

0fJ2415
112024

173374
173376

173300
"'0340

39
421

0e5"'~1

01'640

0'''''~''

J8RA~CH

IofAL.T

BR RESTRT

TABI.EI
,WORD
,WORD
,WORD
.WORD

,CHECK
J8RA~CH

CL.R PC

J JIJMP TO "

037*400 ... 24~
0~5*42J~ ... 2115
224*~0" ... 024

J I LBS ... RE~!l ~iU-t·Gn

ERROR
TO HAI.T ON E~ROR

F~R

LOLtJ BYTE

'H!GH 8YTE

. ~"HJ3421

COM MA'I D

CO~JT I NLJE

TST (R0)

VECTOR! CBoar

TAC~

JHALT ON ERR~R

J RESTART 0""

8MI STOP

~,0

Mova 2(R~),(~2) JREA~ DATA I~TO MEMORY

321

JR~

(R~)

,REAn"'GO
JR~An+ILBS+E~D

TA8~E

JTWO WORnS or rl~I.ER

JPCWER-UP vEr.rOR (pC)
,POWER.UP ~TATVS (PS)

REAOy+TRANSFER ~EQUE~T
SPACE ~O~W~RD AL~CK.GO
REAO.ll.aS

switch initializes the system prior to starting. However, if the BM792-YH program is started by a program
transferring control to location 173300, then that program must issue a RESET instruction prior to the JMP
173300.
Normally. the PDP-II processor's power-up vector is address 24/26; however, processors such as the PDP-ll/40
and PDP-II /45 have jumper selectable power-up vectors that allow the vector address to be-set to an address
within a restricted range in thl' highest 4K-words of Unibus address. Thc power-down vector remains at 24/26.
Tht: Bf\1792-YH provides a power-lip vector at address 173374/6. Whl~n the power-up trap sequence executes
with a vector address set to 173374/6, program execution begins at 173300 with a priority level of 7.
The operating procedure for use of the BM792-YH ca~sctte bootstrap loader when the cassette is operating from
cassette unit number 0 at the standard octal address of 777500 is as follows:
Procedure

Step
Write-lock the cassette for security.

..,

Mount the cassette in cassette unit number 0 (left-hand drive unit on the TU60) .

Set the HALT/ENABLE switch to HALT, then to ENABLE.

Set the ROM address, 773300,-into the Switch register.

Depress the LOAD ADDR switch.
Depress the START switch. The cassette data should then read into the read-write
memory.

The operating procedure to bootstrap load from cassette unit number 1 or from a cassette unit other than onc
at the standard octal address of 777500 is as follows:
Procedure

Step
Write-lock the cassette for security.

Mount the cassette in the selected unit.

Set the HALT/ENABLE switch to HALT, then to ENABLE.

Set the RO address. 777700, into the Switch register.

Depress the LOAD ADDR switch.

Set the address of the cassette unit into the Switch register.

Depress the DEP switch. This ioads RO with the address of the cassette unit.

With the Switch register still set at the address of the cassette unit, depress LOAD ADDR
switch.

Set the octal designation for the cassette unit number into Switch register (000 for unit
number 0 or 400 for unit number I).

Depress the DEP switch. This establishes bit 08, the Unit Select bit, of the TA 11 Command and Status register.

Set the R7 address, 777707 into the Switch register.

Depress the LOAD ADDR switch.
(continued on next page)

F-3

Step

Procedure

Set 773306 into the Switch register.

Depress the DEP switch. This sets the PC to the BM79~-YH restart address.

Depn.'ss the CONT switch. This starts the processor without system initializatioll.
When started at address 773306, the BM792-YH program uses RO to rcfercnC:l' the
cassette rcgisters but does not modify RO or the Unit Sclcd bit.
When the I 28-byte program is loaded from the cassette into the read-write memory,
this 128-byte program determines whether read-in will continue from this same cassett~~.
RO and the Unit Select bit can be modified by the loaded program so that a different
cassette can be accessed for loading.

F-4