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EK-VT240-TM-001

August 1984

316 pages

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7.3MB

Document:	VT240 Technical Manual
Order Number:	EK-VT240-TM
Revision:	001
Pages:	316
Original Filename:	http://bitsavers.org/pdf/dec/terminal/vt240/EK-VT240-TM-001_VT240_Technical_Manual_Aug84.pdf

OCR Text

EK-VT240-TM-001

VT240 Series
Technical Manual

EK-VT240- TM-001

VT240 Series
Technical Manual

Prepared by Educational Services
of
Digital Equipment Corporation

1st Edition, August 1984
Copyright © 1984 by Digital Equipment Corporation.
All Rights Reserved.
Printed in U.S.A.
The reproduction of this material, in part or whole, is strictly
prohibited. For copy information, contact the Educational Services
Department, Digital Equipment Corporation, Maynard, Massachusetts
'H754.
The information in this document is subject to change without
notice. Digital Equipment Corporation assumes no responsibility
for any errors that may appear in this document.
This equipment generates and uses radio frequency energy and if
not installed and used properly, that is, in strict accordance
with the manufacturer's instructions, may cause interference to
radio and television reception. It has been type tested and found
to comply with the limits for a Class B computing device in
accordance with the specifications in Subpart J of part 15 of FCC
Rules, which are designed to provide reasonable protection against
such interference in a residential installation. However, there is
no guarantee that interference will not occur in a particular
installation. If this equipment does cause interference to radio
or television reception, which can be determined by turning the
equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures:
reorient the receiving antenna
relocate the computer with respect to the receiver
move the computer away from the receiver
plug the computer into a different outlet so that computer and
receiver are on different branch circuits.
If necessary, the user should consult the dealer or an experienced
radio/television technician for additional suggestions. The user
may find the following booklet prepared by the Federal
Communications Commission helpful:
"How to Identify and Resolve Radio-TV Interference Problems".
This booklet is available from the US Government Printing Office,
Washington, DC 20402, Stock No. 004-000-00345-4.
The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts.

momoomD

DEC
DECmate
DECnet
DECUS

DECwriter
DIGITAL
LA
MASSBUS
PDP

P/OS
Professional
Rainbow
RSTS
RSX

UNIBUS
VAX
VMS
VT
Work Processor

CONTENTS

INTRODUCTION
CHAPTER 1

SYSTEM INTRODUCTION

1.1
1.2
1. 2.1
1. 2.2
1. 2.3
1.3
1. 3.1
1. 3.2
1. 3.3
1.4

Genera 1

.......•.••..•.

1.6
1. 6.1
1. 6. 2
1. 6. 3
1. 6. 4
1. 6. S
1. 6.6

Physical Description
System Box (VS240)
Keyboard (LK201)
Monitor ...•..•.•
Display Capabilities
Display Characteristics
Text Capabilities .•••.
Graphics Capabilities
Communications Environment
Major Operating States
Operating Modes •..•.••.
VT100 Mode •••.••••
VT200 Mode, Seven-Bit Controls
VT200 Mode, Eight-Bit Controls
VTS2 Mode •.•..
ReGIS Mode
4010/4014 Mode

CHAPTER 2

CONTROLS,

2.1
2.2
2.3
2.4
2.S
2.S.1
2.S.2
2.S.3
2.S.4
2.S.S
2.S.6
2.S.6.1
2.S.6.2
2.S.7

General
System Box (VS240)
Monochrome Monitor (VR201)
Color Monitor (VR241)
Keyboard (LK201)
Main Keypad
Editing Keypad •.....•••••••.
Auxiliary Keypad .....••......•.•
Top-Row Function Keys
Visual Indicators
Audible Indicators
Audible Keyclick •.•••

loS

INDICATORS,

Be 11

1-1
1-1
1-1
1-3
1-3
1-3
1-4
1-4
l-S
I-S
I-S
1-6
1-6
1-6
1-6
1-7
1-7
1-7

AND CONNECTORS

••••••••••••••••

Connector Cable

iii

2-1
2-1
2-2
2-4
2-S
2-7
2-8
2-8
2-9
2-9
2-11
2-11
2-11
2-12

CHAPTER 3

SYSTEM OVERVIEW

3.1
3.2
3.2. 1
3.2.2
3.2. 3
3. 3
3.3.1
3.3.2
3.3. 3
3.3.4
3.3. 5
3.3.6
3.3. 7
3.4

Genera 1

CHAPTER 4

CPU LOGIC

4.1
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.2
4.2. 3
4.2.4
4.2. 5
4.2.6
4.2. 7
4.2.8
4.2. 9
4.2.113
4.2.11
4.2.11.1
4.2.11.2
4.2.11.3
4.2.12
4.2.13
4.2.14
4.2.15
4.3
4.4

Genera 1

CHAPTER 5

SYSTEM COMMUNICATION LOGIC

5.1
5.2
5.2.1

Genera 1

5.2.1.1
5.2.1.2
5.2.1.3

...................••

Operating States ........ .
Set-Up
Local
On-Line
System Architecture
CPU Logic ........••..••••
Video Logic
System Communication Logic
Integral Modem (Opt ion)
Power Supply .....
Keyboard
Monitor
System Interaction ......•.

.•......•..•.......

Major Circuits/Components
Central Processor Unit ....•.
T11 Internal Circuits
T11 Transactions
Mode Register
Control Gates •••••.
Address Latch ........••.
Memory Map
Memory Access Decode
Read Only Memory (ROM)
Ra ndom Access Memory (RAM)
I/O Buffer .....•..
I/O Decode ......•.
Keyboard Interface (I/F)
8251A USART Internal Circuits
•••••
8251A USART Addresses .•.......•••••.
8251A USART Timing Diagrams ..••....•.
Nonvolatile RAM (NVR)
Interrupt Control
Command Register
Clock Generator ..••••••••
Signal Descriptions
Schematic Reference Information

.••••..••••••.....•••..•..•••..•.•••

Major Circuits/Components •.......•••...••..
Dual Asynchronous Receiver/Transmitter
(DUART)
2681 DUART Internal Circuits
2681 DUART Addresses ..••••
2681 DUART Timing Diagrams •....••••••

3-1
3-1
3-1
3-2
3-2
3-3
3-4
3-4
3-5
3-5
3-5
3-5
3-6
3-6

4-1
4-2
4-3
4-4
4-6
4-12
4-12
4-15
4-15
4-18
4-18
4-19
4-22
4-23
4-26
4-27
4-29
4-313
4-31
4-33
4-34
4-35
4-35
4-35

5-1
5-2
5-2
5-4
5-6
5-6

5.2.2
5.2.2.1
5.2.2.2
5.2. 3
5.2.4
5.2.5
5.2. 6
5.2.7
5.3
5.4

Communication/Modem (Comm/Modem) Control ...
Comm/Modem Control Circuits ....•••••...
Comm/Modem Control Addresses .••••••••••
Communication Mul tiplexer (Comm Mux) •••••.•
Printer Interface (I/F) .•••.••••.••••••••••
EIA Host Interface (I/F) ••..........•...•••
20 rnA Interface (I/F) •.••••••••••••••••••••
Integral Modem Option Connector (J5) ......•
Signal Descriptions .•..••••••••.••.••••.•.•••..
Schematic Reference Information .•..••••••.•••..

CHAPTER 6

VIDEO LOGIC

6.1
6.2
6.2.1
6.2.1.1

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Major Circuits/Components •.••••••••••••••.•..••
Character Processor (CP) ••....•..•.••.•••••
8085A-2 Microprocessor Device Internal
Ci rcui ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8085A-2 Microprocessor Device
Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Character Processor (CP) Memory .•.........•

6.2.1.2
6.2. 2
6.2.3
6.2.4
6.2.4.1
6.2.4.2
6.2.4.3
6.2. 5
6.2.5.1
6.2.5.2
6.2.5.3
6.2.5.4
6.2.5.5
6.2.5.6
6.2.6
6.2.7
6.2.7.1
6.2.7.2
6.2.7.3
6.2.8
6.2. 9
6.2.10
6.2.11
6.2.12
6.2.13
6.2.14
6.2.15
6.2.16
6.3
6.4

Video Access

•••••.•.......•.••.•.•..•••....

Graphics Processor •.•..••..•••••••.•.....•••
PD7220 Graphics Display Controller
(GDC) Internal Circuits •....•..•.•••••.
PD7220 Graphics Display Controller
(GDC) Addresses ..••••••.••.•..•.•••••..
PD7220 Graphics Display Controller
(GDC) Transactions ....••.••....•..••••.
Timing and Control Circuits ..••.•.......••.
Clock Generator .......•.••••.•........•
BEN and STOP Gates .•..••.....•••..•.•..
ROM Address Counter .••.•••.•.•..•••.••.
Timing Signal Generator ...•.••••......•
Read-Modify-Write (RMW) Generator .•...•
BLANK Genera tor .•.....•...•....•••••••.
Mode Select

•••••••••....•...••••••••..•....

Bit Map Addressing Circuit .•..••••••.......
Plane and Byte Select ••...........•••••
Address Select . . . . . . . . . . . . . . . . . . . . . . . . .
Row/Column Mux

.....•.......•...•.•.•.••

High/Low (Hi/Lo) Byte Select ......••..•••••
Bit Map Write Enable •...••..•••••....•.••..
Pattern Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Data Select •••...•••.•.•.••••••...•••
Bit Map

•••..........................•••••••

Parallel-to-Serial

(p/S) Converter ..•••••.•

Output Map ....•.•••••.•.•••••.•....•••••••.

Digital-to-Analog (D/A) •.••.........•.•.•.•
Signal Descriptions •.•.•••.........•.•.••••..•.
Schematic Reference Information ..•.•••••••.•...

5-8
5-9
5-11
5-12
5-12
5-14
5-14
5-16
5-17
5-17

6-1
6-2
6-2
6-5

6-6
6-8
6-9
6-12
6-12
6-14
6-18
6-22
6-23
6-24
6-24
6-24
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-32
6-34
6-35
6-37
6-39
6-40
6-41
6-43
6-46
6-47
6-47

CHAPTER 7

LK2131 KEYBOARD

7.1
7.2
7.3
7.3.1
7.3.1.1
7.3.1.2

Genera 1

7.3.2
7.3.2.1
7.3.2.2
7.3.2.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.4.1
7.4.4.2
7.4.5
7.4.6
7.4.7
7.5
7.5.1
7.5.2
7.5.2.1

•.•.....•.•..•.•.•••••••••••••••••••••••

Physical Description ••••••••••••••.••••••••••••
Functional Description •...••••.•••..•.•••••.•••
Keyboard Operation Overview .••••.•......•••
Keyboard Scanning ...•...••••••••••.••••
Control of Audio Transducer and
Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Firmware Functions ••..••••••••.•.•
Functions Not Changed by CPU
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functions Changed by CPU Instructions .•
Firmware Functions Changed by CPU
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed Keyboard Circuit Description •.••••••••
Keyboard Matrix Scanning ..••...••••••••••••
Audio Transducer Control Circuit ..•••••••••
Indicator (LED) Control Circuit ••••••..•.••
Keyboard Communication •••••••••••••••••••••
Keyboard Transmit Mode •••••••••••••••••
Keyboard Receive Mode ••••••••••••••••••
Reset Signal for 81351 Microprocessor •••••••
Hardware Keyboard Identification (ID) ••••••
Voltage Supplies •••.••..••.••••••••••••.••.
Keyboard Programming ••.••••••••••••••••••.••••.
Keyboard Layout and Key Identification .••.•
Modes

••••••••••••••••••••••••••••••••••••••

7.5.2.3
7.5.3
7.5.3.1
7.5.3.2
7.5.4
7.5.4.1
7.5.4.2
7.5.4.3
7.5.5
7.5.5.1
7.5.5.2
7.5.5.3
7.5.5.4
7.5.6
7.5.6.1
7.5.6.2
7.5.6.3
7.5.6.4
7.5.6.5
7.5.7
7.5.7.1
7.6

7-5
7-5
7-5
7-6
7-6
7-6
7-6
7-14
7-14
7-16
7-16
7-16
7-17
7-17
7-17
7-17
7-17
7-23

Special Considerations Regarding
Autorepea t

7.5.2.2

7-1
7-2
7-4
7-4
7-5

............................ .

Special Considerations Regarding
Down/Up Mode •.....••...••••••••.••••..•
Autorepeat Rates •••••••••••.•••••••••••
Keyboard Peripherals ..•.••••.•••.•.••••••••
Aud i 0

••••••••••••••••••••••••••••••••••

Indicators (LEDs) ••.••...••.••..•......
Keyboard-to-System Module Protocol •...•...•
Keycode Transmission .......••.•.....••.
Special Code Transmission ......•.•.••••
Power Up Transmission ....••....•.•.••.•
System Module to Keyboard Protocol ..•.•••••
Comma nd s •••••••••••••••••••••••••••••••

Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Commands •....••...•.•.•••••.
Mode Set Commands ..••.•••••.•.••.•..•••
Special Considerations ..•..•.••••••••••••..
Error Handling .•.•••..•.•..•.•••.•..•••
Keyboard Locked Condition ••..••....••••
Reserved Code .••••..••.•...•........•.•
Test Mode

••••••••••••••••••••••••••••••

Future Expansion ......•.....••••••.....
Default Conditions •....•..••.••.•••••••..••
Audio Volume . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications

7-23
7-25
7-25
7-26
7-26
7-26
7-27
7-27
7-27
7-29
7-29
7-313
7-313
7-31
7-36
7-38
7-38
7-39
7-39
7-39
7-39
7-413
7-413
7-41

CHAPTER 8

MONOCHROME MONITOR

8.1
8.2
8.3
8.3.1
8.3.2
8.4
8.4.1
8.5
8.6
8.7
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
8.7.6
8.7.7
8.7.8
8.7.9
8.7.10

Gener a 1 ••••••••.••••

Physical Description
Functional Overview
VIDEO Da ta
SYNC Da ta
Monochrome Monitor System Communication
Composite Video Signal ••••••••••••
CRT
Yoke ••••.••...•
Monitor Module
Dynamic Focus
Grid Bias
Horizontal Deflection
Linear Regulator
Vertical Deflection
Video Amplifier (Amp)
Flyback Transformer
Jl
J2

CHAPTER 9

POWER SUPPLY

9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7

Major Circuits/Components •...•••
AC Input and Fan Components •••••
Power Supply 1 (PSI)
DC Power Input Connector (Jl)
+5 V Input Circuit
+12 V Input Circuit
-12 V Input Circuit
DC Power Okay Circuit

CHAPTER 10

INTEGRAL MODEM OPTION

10.1
10.1.1
10.1.2
10.1.3
10.1.3.1
10.1.3.2
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7
10.2.8
10.2.9
10.3

General . . . . . . . . . . . . . . . . . . . . . . .
Compatibility and Features
Functional Description
Physical Description
Power Requirements
Temperature and Humidity •••..
Major Circuits ••..•••......
Talk/Data Relay Circuit
Switch Hook Detector Circuit •.•••
Ring Detector Circuit
Hook Relay Circuit
Line Interface Circuit ..•••••••
Dial Tone Detect Circuit
Audio Coupler Circuit
Master Clock Circuit
Modern Control LSI Circuit
••••.
Terminal Interface Signal Description

Pi . . . . . . .

Genera 1

••••••••••••••.•••••••••

vii

8-1
8-2
8-4
8-5
8-5
8-5
8-7
8-10
8-11
8-11
8-12
8-12
8-13
8-13
8-14
8-14
8-15
8-16
8-16
8-16

9-1
9-2
9-3
9-4
9-14
9-14
9-15
9-16
9-16

10-1
10-2
10-2
10-3
10-4
10-4
10-4
10-4
10-6
10-6
10-6
10-6
10-7
10-7
10-10
10-10
10-11

10.3.1
10.3.2
10.3.2.1
10.3.2.2
10.3.2.3
10.3.2.4
10.3.2.5
10.3.2.6
10.3.2.7
10.3.2.8
10.3.2.9
10.3.2.10
10.3.2.11
10.3.2.12
10.3.2.13
10.3.2.14
10.3.2.15
10.3.2.16
10.3.2.17
10.3.2.18
10.3.2.19
10.3.2.20

Signal States •.••••••.•....•.•••••••••••••.
Interface Signals •.•...•••••••••••••.•••...
Transmitted Data (TO) ••••.•••••••••••••
Received Data (RD) ••••••••..•..•.•.••••
Clear to Send (CTS) •••••••••••.•...••.•
Data Set Ready (DSR) •.•••••••.....•..••
Signal and Power Ground ••••••••••••...•
Carrier Detect (CD) ••••••••••••••••••••
Speed Indication (CI) •••••••••••....•..
Data Terminal Ready (DTR) •••.••••••••••
Data Rate (Speed) Select (CH) •.•.......
Dial Tone Detect (DTD) •.•••...•••••.•••
Line Switch (Talk/Data) •••••..••...••••
Data Available (DA) ••.•.•••••••••••.•••
Off Hook Drive (OH-D) •••.••••••••••••..
9- or 10-Bit Character (9/10 SEL) •..•.•
Coupler Cut Through (CCT) •.•.•.•.......
Switch Hook (SW) ••••.....••••••••••••..
Off Hook Modem (OH-M) .•••...•••••••••..
Analog Loop Test (ANL) ••....•.•••••••.•
Remote Data Loopback Test (RDL) ..••••..
Test Mode Indicate (Test IND) •••..•••••

APPENDIX A

SPECIFICATIONS

APPENDIX B

VT240/VT102 DIFFERENCES

APPENDIX C

VT240/VT125 DIFFERENCES

APPENDIX D

APPENDIX E

VIDEO LOGIC WRITE MODE PROGRAMMING OVERVIEW

10-12
10-12
10-12
10-14
10-14
10-14
10-14
10-14
10-14
10-14
10-15
10-15
10-15
10-15
10-15
10-15
10-15
10-15
10-15
10-16
10-16
10-16

FIGURES
1-1
1-2
2-1
2-2

VT240 Series Video Terminals •.•••.••••.••...•••
VT240 Series Terminal Block Diagram .•••...•.•••
System Box Controls, Indicators, and

1-2
1-2

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

VR201 Monitor Controls, Indicators, and
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3

VR241 Monitor Controls, Indicators, and
Connectors (Front and Rear) •.••..•••••••.•.....
Keyboard (North American) ...••.••.••..••.••.•••
Main Keypad . • . • • . . . . . • • • • • . . • • • • • • • • . . . . . . . • . . .
Ed i ti ng Keypad ••••••••.••••••••••••••••••••••••

Auxiliary Keypad •.•...••.•••.•.••.......•.•..•.
Top-Row Function Keys and LEOs .••.•••..••.....•
Connector for BCC01 Cable ••........•..•.•••••..
VT240 Series Terminal System Block Diagram •.•..
System Interaction in Set-up ••.•.......••••..•.
System Interaction in Local (Printer Port
Inactive)

......................................

viii

2-3

2-4
2-6
2-7
2-8
2-8
2-10
2-12
3-3
3-6
3-7

3-4

System Interaction in Local
Output Port)

(Printer Port as

.................................. .

3-5

System Interaction in Local

3-6

3-8

System Interaction in On-Line (Printer Port as
Inactive or Output Port) •..•••.••••••••••••.•••
System Interaction in On-Line (Printer Port as
Inactive or Input Port) •••••••••••.••••••••••••
System Interaction in On-Line (Printer Port as

3-9

System Interaction in On-Line (Printer Port as

Input Port)

3-7

Input Port)

................................... .

Output Port)

.................................. .

3-10

System Interaction in On-Line (Printer Port as

3-11

3-13

System Interaction in On-Line (Printer Port as
Inactive or Output Port) •.•••••...•••••••••••••
System Interaction in On-Line (Printer Port as
Inactive or Input Port) •••••••••••••••••.•....•
System Interaction in On-Line (Printer Port as

3-14

System Interaction in On-Line (Printer Port as

I/O Port)

3-12

..................................... .

Input Port)

................................... .

Output Port)

.................................. .

3-15

System Interaction in On-Line (Printer Port as

4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25

VT240-Series Terminal System Block Diagram •...•
CPU Logic Block Diagram ••••••.••••••••..•••••••
CPU Block Diagram •..•.•••••••.•••••••.....•••••
TIl Internal Block Diagram •••••••....••••••..•.
Power-Up Sequence ••.••..•••••..•..•••••••.•.•••
TIl Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIl 16-Bit Dynamic Read Transaction Diagram •.••
TIl 16-Bit Dynamic Write Transaction Diagram ••.
TIl Refresh Transaction Diagram •.....••••••••..
TIl ASPI Transaction Diagram ••••.••••.••..••••.

I/O Port)

4-26
4-27
4-28

..................................... .

Mode Reg i ster

••••••..••••••••••..••••••••.•.•..

Control Gates Block Diagram •.•••...•.••.••••••.
Address Latch Block Diagram •••.••••••.••..•••.•
Memory Map Block Diagram •••••••••••••••••.•••••
VT240-Series Terminal Address Map •.•••..•••••••
Memory Access Decode Block Diagram ••..•.•••.••.
Read Only Memory (ROM) Block Diagram .•••••...••
Random Access Memory (RAM) Block Diagram ••••••.
Ga t e s ••••••••••••••••••••••••••••••••••
RAM Devices Array ••••••••••••••••••••••••••••••

RAM CAS

I/O Buffer Block Diagram •.•••.••••.•...••••...•
I/O Decode Block Diagram ••...•••••..•.••••••••.
Keyboard Interface (I/F) Block Diagram •..•..•••
8251A USART Internal Circuits Block Diagram ..•.
8251A USART Transmit Data (TxD) Timing
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8251A USART Receive Data (RxD) Timing Diagram •.
Nonvolatile RAM (NVR) Block Diagram ..••••...•..
Interrupt Control Block Diagram ..•••..•.•.•.•.•

3-7

(Printer Port as
3-8
3-8
3-9
3-9
3-10
3-10
3-11
3-11
3-12
3-12
3-13
4-1
4-2
4-3
4-5
4-7
4-8
4-9
4-10
4-11
4-11
4-12
4-14
4-15
4-16
4-17
4-18
4-18
4-20
4-21
4-21
4-22
4-23
4-27
4-28
4-30
4-30
4-31
4-33

4-29
4-30
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31

Command Register Block Diagram ••.••••••••••••..
Clock Generator Block Diagram •..••••••••.••••••
VT240-Series Terminal System Block Diagram •••••
System Communications Logic Block Diagram ••••••
DUART Block Diagram ••••••.••••••••••••.••••••••
2681 DUART Internal Circuits Block Diagram •.•••
2681 DUART: Transmit Data Timing Diagram •.•••••
2681 DUART: Receive Data Timing Diagram ••••••••
Communication/Modem (Comm/Modem) Control Block
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comm Mux Block Diagram •••••••••••••••••••••••••
Printer Interface (I/F) Block Diagram ••••••••••
EIA Host Interface (I/F) Block Diagram •••••••••
20 mA Interface (I/F) Block Diagram ••••••••••••
Integral Modem Option Connector (J5) Pinout •••.
VT240-Series Terminal System Block Diagram •.•••
Video Logic Block Diagram ••••••••••••.•••••••••
Character Processor (CP) Block Diagram •.•••••.•
8085A-2 Microprocessor Device Internal Block
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Character Processor (8085A-2 Microprocessor
Device) Read/Write Transactions ••••••••••••••••
Character Processor (CP) Memory Block Diagram ••
Video Access Block Diagram ••...••••••••••••••••
Graphics Processor Block Diagram .••••••••.•••••
PD7220 GDC Block Diagram •••••••••••••••••••••••
PD7220 GDC Timing Diagram: CPU/CP Write
Transacti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PD7220 GDC Timing Diagram: CPU/CP Read
Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PD7220 GDC Timing Diagram: Display Timing .•••••
PD7220 GDC Timing Diagram: Video Sync Signals ••
PD7220 GDC Timing Diagram: 2-Plane write
Transaction •••••••••••••.••••••••••••••••••••••
PD7220 GDC Timing Diagram: Video DMA write
Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing and Control Block Diagram Circuits ••••••
Clock Generator Block Diagram ••••••••••....••••
BEN and STOP Gates Block Diagram •.•••••••••••••
ROM Address Counter Block Diagram •••••••••.••••
Timing Signal Generator Block Diagram ••••••••••
Read-Modify-Write (RMW) Generator Block
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BLANK Generator Block Diagram ••••••••••••••••••
Mode Select Block Diagram •••••••••••••••••.•.••
Bit Map Addressing Circuit Block Diagram •••.•••
Plane and Byte Select Block Diagram ••.•••••..••
Address Select Block Diagram •••••••••••••••••••
Row/Column Mux Block Diagram •••••••••••••••••••
Hi/La Byte Select Block Diagram ••.•••••••••••••
Bit Map write Enable Block Diagram •••.•••••••••
Pattern Select Block Diagram •••••••••••••.••.••
Logic unit Block Diagram •••••••••••••••••••••••

4-34
4-35
5-1
5-3
5-4
5-5
5-8
5-9
5-10
5-13
5-13
5-15
5-15
5-16
6-1
6-3
6-4
6-5

6-7
6-8
6-10
6-13
6-13
6-18

6-19
6-19
6-20
6-21
6-22
6-23
6-23
6-25
6-25
6-25
6-26
6-27
6-28
6-29
6-30
6-32
6-33
6-33
6-34
6-36
6-38

6-32
6-33
6-34
6-35
6-36
7-1
7-2
7-3
7-4
7-5
7-6
7-7A
7-7B
7-8
7-9
7-10

write Data Select Block Diagram ••••••••••••••••
Bit Map Block Diagram ••••••••••••••••••••••••••
Parallel-to-Serial (p/S) Converter Block
Diagram . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .
Output Map Block Diagram •••••••••••••••••••••••
Digital-to-Analog (D/A) Block Diagram ••••••••••
VT240-Series Terminal System Block Diagram •••••
LK201 Keyboard

F 0 rrna t

7-11
7-12
7-13
7-14
7-15
7-16
7-17
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
10-1
10-2
10-3
10-4
10-5

•••••••••••••••••••••••••••••••••

Keyboard Cable Connections •••••••••••••••••••••
LK201 Keyboard Block Diagram ••••••••••.••••••••
Matrix Scanning Block Diagram ••••••••••••••••••
Example of Ghost Key Generation ••••••••••••••••
LK201-AA Keyboard Layout •••••••••••••••••••••••
LK201-AA Keyboard Layout •••••••••••••••••••••••
Beeper Control Circuit •••••••••••••••••••••••••
Indicator (LED) Control Circuit ••••••••••••••••
Keyboard Transmit and Receive Character
........................................ .

System Module to Keyboard Protocol •••••••••.•••
Indicator (LED) Parameter ••••.••••••••••••.••••
Indicator (LED) Layout •••••••••••••••••••••••••
Audio Volume Parameter •••••••••••••••••••••••••
Set Main Array to Down/Up Example ••••••••••••.•
Set Main Array to Autorepeat Example •••••••••••
Change Rates in Buffer 3 Example •••••••••••••••
VT240-Series Terminal System Block Diagram •••••
Monochrome Monitor Exterior View ••••.•.•••.•••.
Monochrome Monitor Block Diagram •••••••••..••••
Monochrome Monitor System Communications
Diagram . . . • . . . . . . . . • • . . . . . . . • . . . . . . . . . . . . . . . . . .
Composite Video Signal Representation ••••••••••
Composite Video Sync Timing Diagram ••••••••••••
Monitor Module Block Diagram •••••••••••••••••••
Moni tor Modul e Pl Pi nout •••••••••••••••••••••••
VT240-Series Terminal System Block Diagram •••••
Power Supply Block Diagram •••••••••••••••••••••
AC Input and Fan Components Block Diagram ••••••
Physical Location of Power Supply Components •••
Power Supply 1 (PS1) Block Diagram •••••••••••••
Input Regulation Circuitry ••.••••••••••••••••••
DC Output Circuits •••••••••••••••••••••••••••••
+5.1 V Crowbar Circuit ••••.••••••••••••••••••••
PSl Component Layout •••••••••••••••••••••••••••
Logic Board DC Power Input Connector •••••••••••
+5 V Input Circuit •••••••••••••••••••••••••••••
+12 V Input Circuit ••••••••••••••••••••••••••••
-12 V Input Circuit ••••••••••••••••••••••••••••
DC Power OK Circuit ••••••••••••••••••••••••••••
VT240-Series Terminal Block Diagram ••••••••••••
Physical Description •••••••••••••••••••••••••••
Block Diagram . . . . . . . . . . . . . . . . . . . . • • . . . . . . . . . . . .
Talk/Data Relay •.••...•.•••.••••••••••••••••.••
Audio Coupler •••••••••••••••.••••••••••••••••••

6-39
6-40
6-42
6-44
6-46
7-1
7-2
7-3
7-4
7-7
7-8
7-12
7-13
7-15
7-15
7-16
7-30
7-34
7-34
7-34
7-37
7-37
7-37
8-1
8-3
8-4
8-6
8-7
8-9
8-12
8-16
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-7
9-8
9-14
9-15
9-15
9-16
9-16
10-1
10-3
10-5
10-5
10-7

10-6
10-7
10-8
10-9
10-10
10-11
D-l
D-2
D-3
D-4
D-5
D-6
D-7
D-8
D-9
D-10
D-ll
D-12
D-13
D-14
D-15
D-16
D-17
D-18
D-19
D-20
D-21
D-22
D-23
E-l
E-2
E-3
E-4
E-5
E-6

10-9
10-9
10-9
10-10
Modem Control LS I . . . . . . . . . . . . • . . . . • . . . • . . . • • • • . 10-10
Stack Connector ....•.........•••••••••••••••••. 10-12
8251A USART: Command Register (Mode Instruction
D-l
Format, Asynchronous Mode) .••.••••••••••••••••.
8251A USART: Command Register (Command Data
D-2
Format) ••.....•••••••••..•.•••.••••••••••••••••
8251A USART: Status Register •••••••••••••••••••
D-3
2681 DUART: Mode Register 1 (MRl)
(Channel A and B) •••.•••••••.••••••••••••••••••
D-4
2681 DUART: Mode Register 2 (MR2)
(Channel A and B) •.••••••••••••••.•••••••••..••
D-5
2681 DUART: Status Register (SR)
(Channel A and B) •.••••••••••••••••••••••••••••
D-6
2681 DUART: Data Clock Selection Register
(DCSR) (Channel A and B) ....•••...••••••.••.••.
D-7
2681 DUART: Command Register (CR)
(Channel A and B) ..••••••••••••••••••••••••••••
D-8
2681 DUART: Receive/Transmit Data Registers
(RDR/TDR) (Channel A and B) ••••••••••••••••••••
D-8
2681 DUART: Input Change Register (ICR) ..•••••.
D-9
2681 DUART: Input Port Register (IPR) •••.•••..•
D-9
2681 DUART: Counter Timer/Upper (CTUR) and
Lower (CTLR) Registers ••.•••••••.•.•........... D-10
2681 DUART: Auxiliary Control Register (ACR) ••. D-10
2681 DUART: Interrupt Status Register (ISR) •••• D-ll
2681 DUART: Interrupt Mask Register (IMR) .••••. D-ll
2681 DUART: Output Port Configuration Register
(OPCR) •••••••••••••••••••••••••••••••••••••••••
D-12
Comm/Modem Control: Comm Control write (CCWR)
and Read Registers (CCRD) ••••••••••••••••••••••
D-13
Comm/Modem Control: Modem Control write Register
(MCWR) • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
D-14
Comm/Modem Control: Modem Control Read Register
D-14
(MCRD) •••••••••••••••••••••••••••••••••••••••••
PD7220 GDC Status Register •••••.•••••..•.•...•. D-15
Video Logic Mode Select Register 0 ••••••••.•.•• D-15
Video Logic Mode Select Register 1 ••••••••.••.. D-16
Video Logic Unit Register •.•••••••••••••....••• D-16
Mode 0 (Read Back Mode) Programming Values •••••
E-l
Mode 1 (Text Mode) Programming Values ••••.••••••
E-2
E-3
Mode 2 (Vector Mode) Programming Values ••••••..
E-4
Mode 3 (DMA Scroll Mode) Programming Values .•••
Mode 4 (Screen Erase Mode) Programming Values ••
E-5
Mode 5 (Word/Line Erase Mode) Programming
E-6
Values
Originate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Answer Mode ••••••••••••••••••••••••••••••••••••
Te s t Mod e ••••••••••••••••••••••••••••••••••••••
Modem Clock •..•.•••.•.•.••••••••••••••••••.••••

. . . . . . . . . . . .. .. ........ . .. . . . . . . ...... . ...

xii

TABLES
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
5-3
5-4
5-5
6-1
6-2
6-3
6-4
6-5
6-6
6-7
7-1
7-2
7-3
7-4
7-5
7-6
8-1
8-2
8-3
8-4
9-1
9-2
9-3
10-1

DAL Signal Values During Power-Up Sequence ...••
Output Flag Decode Gates Truth Table ••.•••••••.
R/W Decode Gates Truth Table ••••••••••••••....•
I/O Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8251A USART Addresses ••••••••••••••••.•••••••••
CPU Logic Signal Descriptions ••••••••.••••••••.
CPU Logic Schematic References •.•••••••..••••••
2681 DUART Addresses ••••••••.••.••••••••••••••.
Comm/Modem Control Addresses ••••••••.••••••.•••
Comm/Modem Control Definition of Integral Modem
Op t ion Pro toe 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Communication Logic Signal
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Communication Logic Schematic

4-13
4-13
4-14
4-25
4-29
4-36
4-45
5-7
5-11

References

5-25
6-9
6-11
6-15
6-45
6-45
6-48
6-62
7-9
7-18
7-19
7-33
7-39
7-40
8-6
8-7
8-8
8-10
9-9
9-11
9-12
10-13

••••••••••••••••••..•••••••••••••••••

Character Processor Memory Addresses ••••••••••.
Video Access Circuit I/O Addresses •••••••••.•••
PD7220 GDC Commands Summary ...•.••••••..•••••••
Video Output Map (VOM) Addressing .•••••••••••••
Intensity Definition for Output Map Outputs ••••
Video Logic Signal Description .••••.•••••••••••
Video Logic Schematic References •••••••••••••••
Keyboard Matrix

••••••••••••••••••.•••••.•••••••

Keyboard Functional Divisions •••••.••••••••••• ~
Keycode Translation Table ••••••••••••••••••••••
Peripheral Commands in Hexidecimal ••.••••••••••
Keyboard Division Default Modes ••••••••••••••••
Default Rates in Autorepeat Buffers ••••••••••••
J1 Pin-out •••••••••••••••••••••••••••••••••••••
J3 Pin-out •••••••••••••••••••••••••••••••••••••
Composite Video Values •••••••••••••••••••••••••
Composite Video Sync Component ••••••••••••••.••
Power Supply 1 (PSI) Components ••••••.•••••••••
Input Voltage Specifications •••••••••••••••••••
Output Voltage Specifications •••••.••••••..••••
Interface Signal Levels ••••••••••••••••••••••••

xiii

5-12
5-17

INTRODUCTION

GENERAL
This manual provides information to help Field Service engineers,
and other personnel trained by Digital Equipment Corporation,
isolate VT240 Series Terminal malfunctions. This manual documents
hardware functions to the major circuit level, identifying the
major circuits within the VT240 Series terminal and providing
functional descriptions of those circuits.
Summarized operating and programming information is provided where
neccessary to understand the functionality of a hardware component
or circuit.
MANUAL ORGANIZATION
The first three chapters of this manual introduce the VT240 Series
terminal.
Chapter 1
terminal.

System Introduction -- introduces the VT240 Series

Chapter 2,
all
VT240
connectors.

Controls, Indicators, and Connectors -- describes
Series
terminal
controls,
indicators, and

Chapter 3, System Overview
provides an overview of the
VT240 Series terminal system interactions.
Chapters 4 through 10 identify the major logics that comprise the
VT240 Series terminal, and identify and describe the major
circuits within those logics.
Chapter 4, CPU Logic -- describes the logic responsible for
overall control over VT240 Series terminal operation.
Chapter 5, System Communication Logic
describes the logic
responsible for communication with host and auxiliary devices.
Chapter 6, Video Logic -- describes the logic responsible for
developing composite video output to a monitor device.
xv

Chapter 7, LK201 Keyboard -- describes the module responsible
for operator input.
Chapter
8,
Monochrome Monitor
describes
responsible for visual output to the operator.

the

module

Chapter 9,
Power Supply describes the system box power
supply responsible for converting ac input to dc potentials
needed to operate the terminal.
Chapter 10, Integral Modem -- describes the option responsible
for modem communication with a remote host (when installed).
This manual does not provide a technical description of the VR241
color monitor
(used with the VT241 terminal). This monitor is
described in separate Digital Equipment Corporation publications
(refer to Related Documentation) .
The final part of this manual is made up of Appendices which
provide
specifications,
differences
between terminals, and
programming reference data.
Appendix A,
Specifications -- provides VT240 Series terminal
specifications.
Appendix
B,
VT240/VT102
Differences
descrbes the
differences between the VT240 Series terminal and VT100
terminal.
Appendix
C,
VT240/VT125
Differences
describes the
differences between the VT240 Series terminal and VT125
terminal.
Appendix D,
Register Bit Values -- provides a summary of bit
values for register devices.
Appendix E, Video Logic Write Mode Programming Overview -provides a summary of the video logic write modes.

xvi

RELATED DOCUMENTATION
The following related documents supplement the information in this
manual.
VT240 Series Terminal Documentation
VT240
VT240
VT240
VT240
VT240
VT240
VT240

Series
Series
Series
Series
Series
Series
Series

Pocket Service Guide
Programmer's Reference Manual
Programmer's Pocket Guide
Owner's Manual
Installation Guide
Integral Modem Installation Guide
Video Terminal IPB

EK-VT240-PS
EK-VT240-RM
EK-VT240-HR
EK-VT240-UG
EK-VT240-IN
EK-VT24X-IN
EK-VT240-IP

VR241-A Series Documentation
VT241-A
VT241-A
VT241-A
VT241-A

Series Installation/Owner's Guide
Series Installation Guide
Series Mini Maintenance Manual
Series Pocket Service Guide

EK-VR241-IN
EK-TILSW-IN
EK-VR241E-PS
EK-VR241-PS

Maintenance Print Sets
VT240
VS240
VR201
LK201
VR241

(VS240, VR20l, LK201)
(System Box)
(Monochrome Monitor)
(Keyboard Module)
(Color Monitor)

MP-0l807
MP-01597
MP-01410
MP-01395
MP-01893

xvii

CHAPTER 1
SYSTEM INTRODUCTION

1.1

GENERAL

The VT240 Series terminals are quarter page (up to 24 displayable
lines of text) conversational terminals used to create, store, and
edit text and graphic images.
The VT240 Series includes either the VT240 or VT241 terminal.
These terminals are identical in function. The only difference is
that the VT240 has a monochrome monitor (VR201), while the VT241
has a color monitor (VR241).
The VT240 Series terminal uses ANSI standard functions for text
processing, and Remote Graphics Instruction Set (ReGIS) standard
functions for graphic image processing. In addition, the terminal
also has a 4010/4014 mode to support industry-standard Tektronix
software packages.
1.2

PHYSICAL DESCRIPTION

The

terminal
(Figure 1-1) consists of three units: a monitor, a
and a system box.
NOTE
Appendix A provides specifications for
the VT240 Series terminal.

keyboar~,

1. 2.1

System Box (VS240)

The system box is the center of the terminal. Figure 1-2 shows the
major system box components.
•

Logic Board -- contains the components needed to control
terminal operation.

•

Power Supply (PS) Assembly -- converts ac input to the dc
voltages required by the terminal.

•

Integral Modem
system box and
terminal.

optional PCB which mounts inside the
provides modem functionality for the

1-1

Figure 1-1
VT240 Series Video Terminals

SYSTEM BOX

L
KNTEGRAl MaDEJ
(OPTiON)

[

LOGIC BOARD

POWER
SUPPLY
(PS)

ASSEMBLY

MA-1442-83

Figure 1-2

VT240 Series Terminal
Block Diagram

1-2

1.2.2

Keyboard (LK201)

The terminal uses an LK201 keyboard with the following features.

•

4 LEOs
conditions.

•

Typewriter-style
entry.

•

Auxilliary Keypad
contains
programmable function keys.

•

Editing Keypad -- contains 6 screen function keys, and 4
cursor movement keys.

•

Top Row Function Keys -- 20 keys aligned across the top
of the keyboard are provided for various functions.

provide

visual

Keypad

indication
contains
18

operational

keys for text

keys,

including

Chapter 2
(Controls,
Indicators, and Connectors) provides more
detail concerning the functionality of the LK201 keyboard when
used with the VT240 Series terminal.
1.2.3

Monitor

The VT240 uses the VR201, a 12-inch monochrome monitor; The VT241
uses the VR241, a 13-inch color monitor.
1.3

DISPLAY CAPABILITIES

Text and graphic image display is done by raster scan of an 800 X
240 picture element
(pixel)
matrix.
The VT240 Series terminal
display
capabilities are upward compatable with VT102 text
capabilities, and with VT125 graphics capabilities. In addition,
VT240 Series terminals contain an operational mode that supports
industry-standard Tektronix 4010/4014 software packages.
VT240 Series terminals use bit map technology so that each pixel
in the 800 X 240 matrix is individually addressable. In addition,
two bit maps are used so that each pixel is written and read as a
two-bit code, with any given pixel having anyone of four
different values.

1-3

1.3.1

Display Characteristics

The terminal has two basic characteristics that affect both text
and graphics modes.

•

Screen Integration
The terminal provides complete
integration of text and graphic images within the display
matrix

•

Display Area -- The terminal's display area is defined by
a 2-plane bit map, with an 800 X 240 pixel matrix
comprising each plane.

1.3.2

Text Capabilities

The terminal has four text modes. Three modes execute standard
ANSI functions
(VT100 mode, VT200 mode with seven-bit controls,
and VT200 mode with eight-bit controls), and one mode executes
Digital private functions
(VT52 mode). The following major text
capabilities are available within these various modes.
•

24 rows of text with either 80 or 132 characters per row
(characters formed within 7 X 9 dot matrix in 10 X 10
cell for 80 characters per row, and within 5 X 9 dot
matrix in 6 X 10 cell for 132 characters per row)

•

5 character sets of 94 characters each, including DEC
Multinational Character and Special Character Sets

•

Down-line loadable character set

•

Reverse video

•

Underline

•

Double-height/double-width
basis

•

Bold/normal intensity

•

Character blinking

•

ANSI compatable control functions.

1-4

characters

on a line-to-line

1.3.3

Graphics Capabilities

Graphic images are drawn at the terminal by turning on pixels in
patterns that represent points, lines, circles, arcs, and curves,
as well as alphanumeric characters (available for graphic images).
The terminal's major graphics mode capabilities include:

•
•
•

ReGIS mode

•

64 colors available with any 4 displayable, on a pixel to
pixel basis, at a given time (VT241)

•

Four monochrome shades displayable, on a pixel to pixel
basis, at a given time (VT240).

4010/4014 mode
95 character ASCII set and 3 programmable character sets
(each with up to 95 characters) available for ReGIS text
functions

COMMUNICATION ENVIRONMENT

1.4

The terminal's major communications features include:
•

Asynchronous
second

communications

•
•
•
•
•

EIA RS232C host port

19.2K

bits per

20 rnA host port
EIA RS232C auxilliary port
Seven-bit or eight-bit character formats
Optional integral modern.
MAJOR OPERATING STATES

1.5

The VT240 Series terminal has three major operating states.
•
•
•

Set-up
On-line
Local

Chapter 3 (System Overview) describes the operating states in more
detail.

1-5

1.6

OPERATING MODES

The VT240 Series terminal has five major operating modes which can
be selected either from the keyboard (in set-up), or by the host
(via control codes).
•
•
•
•
•

VT100
VT200, seven-bit controls
VT200, eight-bit controls
VT52
4010/4014

In addition, you can access a sixth operating mode, ReGIS, by
using escape sequences in VT100 or VT200 operating modes.
1.6.1

VT100 Mode

The VT100 mode executes standard ANSI functions. This mode is
designed to emulate the text mode functionality of Digital's VT102
terminal
(Appendix B describes differences between the VT240 and
VT102),
and Digital's VT125 terminal
(Appendix C describes
differences between the VT240 and VT125) .
The VT100 mode provides strict backwards compatability with
existing software written for the VT100 Series terminals (VT102
and VT125). This mode restricts keyboard use to keys that have a
direct functional counterpart on the VT102 keyboard. All data is
restricted to seven-bit format, and only ASCII, U.K., or special
graphics characters are generated.
1.6.2

VT200 Mode, Seven-Bit Controls

The VT200 mode, with seven-bit controls, executes standard ANSI
functions to provide the full
range of VT240 Series terminal
capabilities while using seven-bit controls in a seven-bit or
eight-bit communications environment. This mode supports the DEC
Multinational
Character
Set
and
provides
some
backward
compatability with VT100 Series terminals.
1.6.3

VT200 Mode, Eight-Bit Controls

The VT200 mode, with eight-bit controls, executes standard ANSI
functions to provide the full
range of VT240 Series terminal
capabilities while using eight-bit controls in an eight-bit
communications
environment.
This
mode
supports
the
DEC
Multinational
Character
Set
and
provides
some
backward
compatability with the VT100 Series terminals.

1-6

1.6.4

VT52 Mode

The VT52 mode is a
text mode that executes Digital private
functions, and not ANSI. This mode has some compatability with a
Digital VT102 operating in that terminal's VT52 mode.
The VT52 mode restricts keyboard use to those keys that have a
direct functional counterpart on the VT102 keyboard when the VT102
is in VT52 mode. All data is restricted to seven-bit format, and
only ASCII, U.K., or special graphics characters are generated.

1.6.5

ReGIS Mode

ReGIS mode is a graphics instruction set available when the
terminal is in VT100 mode or either VT200 mode. ReGIS provides a
full range of graphic image capabilities, and has a high degree of
compatability with the ReGIS instruction set in Digital's VT125
(Appendix C describes the differences between a VT240 and VT125) •

1.6.6

4010/4014 Mode

The 4010/4014 mode is designed to support
Tektronix 4010 and 4014 software packages.

1-7

industry-standard

CHAPTER 2
CONTROLS, INDICATORS, AND CONNECTORS

2.1

GENERAL

This chapter provides information about the terminal controls,
indicators, and connectors. This chapter also includes information
about various keypads and special function keys on the LK201
keyboard.
2.2

SYSTEM BOX (VS240)
includes

The system box
(Figure 2-1)
indicators and connectors.

the following controls,

•

Power Switch -- turns the system box on or off.

•

EIA Host Port Connector -- connects the system box to a
host computer, either directly, or via an external modem.

-----~

~:::rz:::=:s

POWER SWITCH

INTEG~RAL
MODEM OPTION PANEL

AC ~T CONNECTOR

0~o

0\
IQ!]

l=j'\=~~-

/
\
20 rnA HOST P O R T · POWER OK"
CONNECTOR
INDICATOR

EIA HOST PORT
CONNECTOR

COMPOSITE VIDEO
OUTPUT CONNECTOR
VIDEO MONITOR
CONNECTOR

Figure 2-1

@i~FUSE

@l~

"'"
KEYBOARD
CONNECTOR

VOLTAGE
SELECTION
SWITCH

PRINTER PORT
CONNECTOR

MA-0788-83A

System Box Controls, Indicators, and Connectors

2-1

•

20 rnA Connector -- connects the system box to a nearby
host computer via a 20 rnA loop.

•

Composite
composite
monitor.

•

Video Monitor
system box.

•

Power Okay Indicator -- lights to indicate correct power
is applied to the system box.

•

Printer Port Connector
connects a printer or an
auxiliary input, output, or I/O device to the system box.

•

Keyboard Connector -- connects the keyboard to the system
box. (The keyboard can also connect directly to the VR20l
monochrome monitor for the VT240, or to the connector at
the VR24l color monitor end of the system box connection
cable for the VT24l.)

•

AC Input Connector
system box.

•

Fuse -- protects the system box from electrical damage.

•

Voltage Select Switch
matches the input voltage
selected for the system box to the voltage supplied at
the wall outlet.

Video
video

Output Connector
provides a complete
output signal for an additional slave
Connector

-- connects the monitor to the

connects

the power cord to the

CAUTION
The wrong voltage select switch setting
can cause damage to the system box.
MONOCHROME MONITOR (VR201)

2.3

The VR201 monochrome monitor (Figure 2-2) includes the following
controls, indicators, and connectors.
•

Contrast Control -- adjusts screen contrast.

•

Brightness Control -- adjusts screen brightness.

•

Video Monitor Connector -- connects the system box to the
monitor.

2-2

VIDEO MONITOR
CONNECTOR

b=-~.
nnin nnnnnn\'nn nn nnnn nnn nnnnIl nnn
SCREEN
CURSOR

1'/

BRIGHTNESS
CONTROL

~::::-:.--'"

KEYBOARD
CONNECTOR

CONTRAST
CONTROL

CARRY
HANDLE

PUSH BUTTON

POST

MA-10,304

Figure 2-2

VR201 Monitor Controls,
Indicators, and Connectors

•

Keyboard
monitor.
box. )

•

Pushbutton -- releases a post that drops to provide a 30
degree tilt range for adjusting the monitor angle.

•

Carry Handle
the monitor.

Connector
connects the keyboard to the
(The keyboard can also connect to the system

provides an easy and safe way to carry

2-3

COLOR MONITOR (VR241)

2.4

The VR241 color monitor
(Figure 2-3)
controls, indicators, and connectors.

includes

•

Power Switch -- turns the monitor on or off.

•

Video Cable
monitor .

the following

Connectors -- connect the system box to the

....
POWER "OK"
INDICATOR

MA_0039_84

Figure 2-3

VR241 Monitor Controls, Indicators,
and Connectors (Front and Rear)

2-4

•

Power Okay Indicator -- lights to indicate correct power
is applied to the monitor.

•

Contrast Control -- adjusts screen contrast.

•

Brightness Control -- adjusts screen brightness.

•

AC Input
monitor.

•
•

Fuse

selects

internal

•

Sync
Connectors
connect
source to the monitor.

external

•

Impedence Switch -- selects 75 ohm or high impedence.

•

Voltage Select Switch
matches the input voltage
selected for the monitor to the voltage supplied at by
the wall outlet.

Connector

connects

the power cord to the

protects the monitor from electrical damage.

Sync
Switch
synchronization.

external

synchronization

CAUTION
The wrong voltage select switch setting
can cause damage to the monitor.
2.5

KEYBOARD (LK20l)

The LK201 keyboard (Figure 2-4) consists of the following parts.
•
•
•
•
•
•
•

Main keypad
Editing keypad
Auxiliary keypad
Top-row function keys
Visual indicators
Audible indicators
Connector cable

2-5

Hold
_ Screen

Print
Screen

Set-Up

Talk

Datal

Break

FlO

Fl1

Fll
(ESC)

F12

F12
(BS)

F13

F14

F13
(IF)

F14

Hold Screen
_

Lock
_

ooooonooooonOOoonBI

I
0'1

DD~~~~~~~~~u~~
D~~~~~~~D~~DDD~
DLJ~~~D~~~~DDDD

IShih

1[][][][][]~[]EJDD[]ISh'h

---,1

Figure 2-4

Keyboard (North American)

Compose
_

Walt
_

F17

F18

F19

F20

Inoooo

uuuu
D~~D
~~~D

[][][]Dnte,

1°

2.5.1

Main Keypad

The main keypad (Figure 2-5) operates like a standard typewriter
keyboard and includes the following special function keys on the
main keypad.

•

TAB key
generates a horizontal tab, which normally
moves the cursor to the next tab stop.

•

CTRL
(Control)
key
when pressed with another key,
generates a control code to tell the system to perform a
defined function.

•

LOCK Key
when pressed, depending upon the set-up
feature, serves as either a SHIFT LOCK (all keys generate
shifted value), or a CAPS LOCK (alphabetic keys generate
uppercase characters), until LOCK key is pressed again.

•

SHIFT Key
when pressed with another key, generates
either the key's shifted value
(for alphanumeric and
two-symbol
keys),
or, as with some function keys,
generates a predefined control function (such as SHIFT
and <x which generates a CANCEL control character).

•

RETURN Key
generates a carriage return (or carriage
return and linefeed as selected in set-up). In some
cases, RETURN moves the cursor to the next line during
text editing, or, in other cases, signals the system that
a particular operation is finished.

•

<x (Delete) Key -- generates a DEL character, normally
moving cursor one character to the left and erasing
character at the new cursor position.

•

COMPOSE CHARACTER Key -- generates characters that do not
exist as standard keys.

Figure 2-5

Main Keypad

2-7

2.5.2

Editing Keypad

The editing keypad
(Figure 2-6) is normally used to control the
cursor and edit data already entered.
In a
typical editing
operation, the four arrow keys move the cursor in the direction of
the arrow. The six editing keys can have functions that correspond
to their legends,
or can be defined for special functions,
depending on the application program in effect.
2.5.3

Auxiliary Keypad

The auxiliary keypad
(Figure 2-7)
is used primarily to enter
numeric data.
However,
some keys on this keypad (PFl, PF2, PF3,
and
PF4)
can have different functions depending upon the
application software. The ENTER key causes a carriage return (or a
carriage return and linefeed, as selected in set-up), and is also
used in set-up mode to activate selected features.

Figure 2-6

Editing Keypad

Figure 2-7

Auxiliary Keypad

2-8

2.5.4

Top-Row Function Keys

Most of the top-row function keys (Figure 2-8) have functions
assigned to them by the application software in use. The following
top-row function keys have predetermined values.
•

HOLD SCREEN Key
freezes the display and stops new
characters from being displayed until you press HOLD
SCREEN again to return the terminal to normal operation.

•

PRINT SCREEN Key -- sends the text on the screen to the
printer
(SHIFT and PRINT SCREEN sends the entire screen
image to the printer, while CTRL and PRINT SCREEN sets or
resets the autoprint mode) •

•

SET-UP Key
set-up.

•

DATA/TALK Key
controls use of a switched telephone
line when the optional integral modem is installed in the
system box.

•

BREAK Key -- transmits a BREAK control character to the
host if BREAK generation is enabled in set-up. (SHIFT and
BREAK initiates a disconnect, while CTRL and BREAK sends
the answerback message to the host) •

•

F11
(ESC)
generates an ESC character in either VT100
or VT52 mode (the function is determined by application
programs in either VT200 mode) •

•

F12
(BS)
-- generates a BS character in either VT100 or
VT52 mode
(the function is determined by application
programs in either VT200 mode) .

•

F13
(LF)
-- generates a LF character in either VT100 or
VT52 mode
(the function is determined by application
programs in either VT200 mode) •

2.5.5

causes

the

terminal

enter or exit

Visual Indicators

The keyboard has the following four visual indicators that show
the present status, or operation in progress.

•

HOLD SCREEN Indicator
frozen
(refer to the
sect ion 2.5.4).

•

LOCK Indicator
depressed
(refer
2.5.1) •

HOLD

lights when the display is
SCREEN key description in

lights when keyboard LOCK key is
to the LOCK key description in section

2-9

DDDDDnDDDDDnDDDDnBI
InDDDD

II
N
I
~

Hold

Screen

Set- Up

Datal

Talk

Break

FlO

(ESCI

F12
(SS)

F13
(IF)

F14

Hold Screen

lock

Compose

F17

IS)

Figure 2-8

Top Row Function Keys and LEDs

Walt

F18

F19

F20

•

COMPOSE
Indicator
lights
sequence is in progress.

•

WAIT Indicator
from transmitting
the system).

2.5.6

Audible Indicators

The keyboard generates the
enable or disable in set-up.
•
•

indicate

compose

lights when the keyboard is prevented
information (in effect, locked out of

following

two sounds which you can

Keyclick
Bell

2.5.6.1 Audible Keyclick -- The keyclick is generated each time
you press a key, with the following exceptions.
•

When the SHIFT or CTRL keys are depressed, because these
keys do not generate characters, only modify characters
generated by other keys.

•

When the WAIT indicator
keyboard will be lost)

•

When the keyclick is disabled in set-up

•

When an inactive key is pressed

2.5.6.2
cases.

Bell

The

bell

(characters

from the

tone sounds in each of the following

•

As part of the power-up self-test

•

When the terminal receives a BEL character from the host

•

When a compose error is made

•

When the margin is approached (unless the bell tone is
disabled in set-up).

2-11

2.5.7

Connector Cable

The keyboard module connects
to
the system via a BCC0l cable.
Connection can be at
the system box,
the monochrome monitor
(VR201), or at the cable that connects the system box to the color
monitor (VR241).
Figure 2-9 shows the connector for the BCC01 cable.

+12V IN
PIN 3

SERIAL OUT
PIN 4

SERIAL IN
Pli" 1

CABLE CONNECTOR WIRING
MONITOR END

KEYBOARD END
SIGNAL

PIN NO.

SIGNAL

PIN NO.

SERIAL IN
GROUND
+12 V IN
SERIAL OUT

1
2

SERIAL OUT
GND
+12 V
SERIAL IN

4
3
2

3
4

PIN NUMBERS
,------"---,
4 3 2 1

~
Figure 2-9

TOP VIEW OF KEYBOARD JACK
(SIGNALS ARE REVERSED AT MONITOR)
MA·0740-84

Connector for BCCOl Cable

2-12

CHAPTER 3
SYSTEM OVERVIEW

3.1

GENERAL

This chapter provides an overview of system interactions during
each possible operating state of the VT240 Series terminal.
3.2

OPERATING STATES

The terminal functions in anyone of the following three operating
states.
Set-up mode
Local mode
On-line mode
3.2.1

Set-up

You can
key) to:

select

set-up from the keyboard (by pressing the SET-UP

•

Examine or change terminal operating
(such as transmit and receive speeds)

characteristics

•

Transfer from on-line mode to local mode, or from local
mode to on-line mode.

While in set-up mode, the terminal is functionally disconnected
from the host. Only the keyboard is enabled as an input device,
and only the monitor is enabled for output. Any data received from
the host is buffered until the terminal is placed in the on-line
mode.

3-1

3.2.2

Local

You can select local while the terminal is in set-up mode. This
operating state disables terminal-to-host communications. Any data
received from the host while in local mode is buffered until the
terminal is placed on-line.
In local, the keyboard serves as an input device; displayable data
input from this device is sent to the screen. Also, you can
configure the printer port as either an input or output port
(selected in set-up mode). If you select the printer port as an
input port, information can be input to the terminal from a device
connected to the printer port. If you select the printer port as
an output port,
information can be output from the terminal
(screen or keyboard data), to a device connected to the printer
port.
3.2.3

On-Line

You can select on-line while the terminal is in set-up mode. This
operating state lets the terminal communicate with a host. This
communications link can be in any of the following forms.
•

Null Modem -- Communication is through a direct line link
with the host, either through the EIA host port, or the
20 rnA port.

•

External Modem
Communication is with a remote host,
using the external modem linked to the terminal through
the EIA host port.

•

Integral Modem
Communication is with a remote host;
the terminal
is
linked to the host through telephone
connectors provided by the integral modem option.

When the terminal
is on-line,
data entered at the keyboard is
transmitted to the host. A local-echo feature (selected in set-up
mode) routes keyboard data to the monitor, as well as the host.
You can use the printer port to connect an input, output, or I/O
device
(selected in set-up mode). You can use both the keyboard
and input device to generate data for transfer to the host (with
local-echo at the monitor only for keyboard input if local-echo is
enabled in set-up).
Both the monitor and the output device can receive information
from the host,
but not at the same time. However, data received
for
the monitor can be subsequently transferred to an output
device.

3-2

If an I/O device is connected to the printer port, the terminal is
effectively shut out of the communications and serves only as a
buffer for communications between the I/O device and the host. No
output is made to the monitor, and no keyboard input can be
transfered to the host.
3.3

SYSTEM ARCHITECTURE

Figure 3-1 is a
functional block diagram of the terminal. This
diagram shows the following major components and or logics.
•
•
•
•
•
•
•

CPU logic
Video logic
System communication logic
Integral modem (option)
Power supply
Keyboard
Monitor

SYSTEM BOX

LOGIC
BOARD
/

LOGIC

/ / VIDEO
/
LOGIC

_ _ ..L. / _ _ _ _ _

SYSTEM
COMMUNICATION

EIA
HOST
PORT

PRINTER
PORT

20 mA
PORT

OPTIONAL
HOST
COMMUNICATIONS

MONITOR
(VR201 OR VR241)

MA-OO~4

Figure 3-1

VT240 Series Terminal System
Block Diagram

3-3

3.3.1

CPU Logic

The CPU logic controls overall terminal operation. It interprets
host and operator input and directs terminal functions. The CPU
logic contains the following major circuits/components.
•

TIl microprocessor
operation

•

Associated access logics such as
mappper, and address latch logics

•

Keyboard interface circuitry

•

32K volatile random access memory (RAM) to provide data
buffering and work space for terminal control operations

•

128
byte nonvolatile
information

•

96K byte read only memory (ROM) to contain firmware for
all
terminal
control functions,
including keyboard
handling, screen data handling, set-up, self-test, ReGIS,
4010/4014 mode, VT52 mode, and serial I/O handling.

3.3.2

directly

RAM

responsible

for

terminal

I/O buffers, memory

store

terminal

set-up

Video Logic

The video logic develops the video output signals necessary to
drive the terminal monitor.
The video logic consists of the
following major circuits/components.
•

8085 microprocessor and associated circuits used as a
character accelerator for high speed writing of text
characters into the video logic

•

Video controller to perform (DMA) direct memory access
functions from character and screen RAM to video output,
address buffering for CPU access to screen RAM, and video
timing signal generation

•

Two-plane bit map to allowing each addressable pixel to
have anyone of four values

•

Output map
map values

•

Digital to Analog
(D/A)
converter to change digital
timing signals, and output map values into analog video
signal output for the monitor

allow programmable interpretation of bit

3-4

3.3.3

System Communication Logic

The system communication logic interfaces with the terminal
external devices.
The system communication logic consists of the
following major circuits/components.
•

Connectors for physical connection with the printer (or
other auxiliary device), host
(EIA host port or 20 rnA
port connectors), and integral modem option

•

Interface logics responsible
from various connectors

•

Registers for communication with CPU logic to control and
report on interface activity

3.3.4

for data input and output

Integral Modem (Option)

When installed,
the integral modem interfaces with the terminal
through a
switched or dedicated telephone line for communication
with a
remote host. The integral modem consists of the following
major circuits/components.
•

Two four-pin telephone
with the telephone line

•

Handshake circuits to control communication between the
terminal and remote host

3.3.5

jack connectors for interfacing

Power Supply

The power supply generates the operating voltages required by the
system box,
keyboard, and VR201 monochrome monitor (the VR241
color monitor has its own power supply). The power supply contains
the following major circuits/components.

•
•
•
•
3.3.6

AC input circuits
+5 V development circuits
+12 V development circuits
-12 V development circuits
Keyboard

The keyboard enables operator input to the system. The keyboard
consists of the following major circuits/components.
•

8051 microprocessor to control keyboard operation

•

Serial interface for communication with the system box

3-5

•

Key matrix scanning circuits to determine when a key is
being pressed

•
•

Beeper circuits to generate bell tones and key clicks

3.3.7

LED drivers to enable the keyboard's visual indicators.
Monitor

The moni tor converts a composi te video input signal from the video
logic,
into visual output to the operator. The monitor can be
either a VR201 monochrome monitor or a VR241 color monitor. In
either
case
the
monitor
contains
the
following
major
circuits/components.
•
•
•

CRT device to present the visual output
Electronics to develope drive potentials for the CRT
Brightness and contrast controls

The VR241 also contains its own power supply to convert ac input
to the operating voltages required by this monitor. The VR201
develops its operating voltages from dc voltage provided by the
power supply in the system box.
3.4

SYSTEM INTERACTION

Figures 3-2 through 3-15 provide an overview of the information
flow within the terminal for various system configurations, during
the different operating states (set-up, local, and on-line).

V
1

DATA IS TRANSFERRED FROM THE KEYBOARD TO THE CPU LOGIC.

2. IF SCREEN DISPLAY IS TO BE AFFECTED, CPU LOGIC DIRECTS VIDEO
LOGIC TO ALTER DISPLAY
MA·1443-83

Figure 3-2

System Interaction in Set-Up

3-6

V
1. DATA IS TRANSFERRED FROM THE KEYBOARD TO THE CPU LOGIC.
2. IF SCREEN DISPLAY IS TO BE AFFECTED, CPU LOGIC DIRECTS VIDEO
LOGIC TO ALTER DISPLAY.

MA-1444-83

Figure 3-3

System Interaction in Local (Printer Port Inactive)

V
1. DATA IS TRANSFERRED FROM THE KEYBOARD TO THE CPU LOGIC.
2. IF SCREEN DISPLAY IS TO BE AFFECTED, CPU LOGIC DIRECTS VIDEO
LOGIC TO ALTER DISPLAY
3. IF DATA IS TO BE OUTPUT TO AN AUXILIARY DEVICE, CPU LOGIC
DIRECTS TRANSFER OF DATA AND CONTROLS TO AUXILIARY DEVICE
VIA PRINTER PORT PORTION OF SYSTEM INTERFACE LOGIC.

MA-1445-83

Figure 3-4

System Interaction in Local
(Printer Port as Output Port)

3-7

1. DATA IS TRANSFERRED TD THE CPU LOGIC FROM AN ENABLED
INPUT, EITHER THE KEYBOARD, OR THE AUXILIARY DEVICE (VIA
PRINTER PORT PORTION OF THE SYSTEM INTERFACE LOGIC): IF
DATA IS PRESENT FROM BOTH SOURCES, AND BOTH ARE ENABLED,
CPU LOGIC WILL DETERMINE WHICH DATA TO PROCESS FIRST
2. IF SCREEN DISPLAY IS TO BE AFFECTED, CPU LOGIC DIRECTS VIDEO
LOGIC TO ALTER DISPLAY.

MA-144&-83

Figure 3-5

System Interaction in Local
(Printer Port as Input Port)

1. DATA IS TRANSFERRED FROM THE KEYBOARD TO THE CPU LOGIC.
2. DATA IS TRANSFERRED FROM THE CPU LOGIC TO THE HOST. VIA
EITHER EIA HOST PORT. OR 20 rnA PORT PORTIONS OF THE SYSTEM
COMMUNICATION LOGIC.
3. IF LOCAL-ECHO IS ENABLED, AND SCREEN DISPLAY IS TO BE
AFFECTED, CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY.

MA-1447-83

Figure 3-6

System Interaction in On-Line
(Printer Port as Inactive or Output Port)

3-8

1. DATA IS TRANSFERRED TO THE CPU LOGIC FROM THE HOST, VIA
EITHER EIA HOST PORT, OR20 rnA PORT PORTIONS OFTHE SYSTEM
COMMUNICATION LOGIC.
2. IF SCREEN DISPLAY IS TO BE AFFECTED, CPU LOGIC DIRECTS VIDEO
LOGIC TO ALTER DISPLAY.

MA-1448-83

Figure 3-7

System Interaction in On-Line
(Printer Port as Inactive or Input Port)

1. DATA IS TRANSFERRED TO THE CPU LOGIC FROM AN ENABLED
INPUT, EITHER THE KEYBOARD, OR THE AUXILIARY DEVICE (VIA
PRINTER PORT PORTION OF THE SYSTEM COMMUNICATION LOGIC);
IF DATA IS PRESENT FROM BOTH SOURCES, AND BOTH ARE
ENABLED, CPU LOGIC WILL DETERMINE WHICH DATA TO PROCESS
FIRST.
2. DATA IS TRANSFERRED FROM THE CPU LOGIC TO THE HOST, VIA
EITHER EIA HOST PORT, OR20 rnA PORT PORTIONS OFTHE SYSTEM
COMMUNICATION LOGIC.
3. IF LOCAL-ECHO IS ENABLED, AND SCREEN DISPLAY IS TO BE
AFFECTED, CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY.

MA-1449-83

Figure 3-8

System Interaction in On-line
(Printer Port as Input Port)

3-9

DATA IS TRANSFERRED TO THE CPU LOGIC FROM THE HOST, VIA
EITHER EIA HOST PORT, OR 20 mA PORT PORTIONS OF THE SYSTEM
COMMUNICATION LOGIC

IF SCREEN DISPLAY IS TO BE AFFECTED, CPU LOGIC DIRECTS VIDEO
LOGIC TO ALTER DISPLAY.

3. IF DATA IS TO BE OUTPUT TO AN AUXILIARY DEVICE, CPU LOGIC
DIRECTS TRANSFER OF DATA AND CONTROLS TO AUXILIARY
DEVICE VIA PRINTER PORT PORTION OF SYSTEM COMMUNICATION
LOGIC

MA·1450-83

Figure 3-9

System Interaction in On-Line
(Printer Port as Output Port)

DATA IS TRANSFERRED BETWEEN THE CPU LOGIC AND THE HOST,
VIA EITHER EIA HOST PORT, OR 20 mA PORT PORTIONS OF THE
SYSTEM COMMUNICATION LOGIC

2. DATA IS TRANSFERRED BETWEEN THE CPU LOGIC AND THE
AUXILIARY 1(0 DEVICE, VIA PRINTER PORT PORTION OF SYSTEM
COMMUNICATION LOGIC

MA·1451·83

Figure 3-10

System Interaction in On-Line
(Printer Port as I/O Port)

3-10

V
1. DATA IS TRANSFERRED FROM THE KEYBOARD TO THE CPU LOGIC.
2. DATA IS TRANSFERRED FROM THE CPU LOGIC TO THE HOST. VIA
EITHER INTEGRAL MODEM OR EIA HOST PORT PORTIONS OF THE
SYSTEM COMMUNICATION LOGIC.
3. IF LOCAL-ECHO IS ENABLED, AND SCREEN DISPLAY IS TO BE
AFFECTED, CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY

MA·1452·83

Figure 3-11

System Interaction in On-Line
(Printer Port as Inactive or Output Port)

1. DATA IS TRANSFERRED TO THE CPU LOGIC FROM THE HOST, VIA
EITHER INTEGRAL MODEM OR EIA HOST PORT PORTIONS OF THE
SYSTEM COMMUNICATION LOGIC.
2. IF SCREEN DISPLAY IS TO BE AFFECTED, CPU LOGIC DIRECTS VIDEO
LOGIC TO ALTER DISPLAY.

MA-1453-83

Figure 3-12

System Interaction in On-Line
(Printer Port as Inactive or Input Port)

3-11

(;;;\

1. DATA IS TRANSFERRED TO THE CPU LOGIC FROM AN ENABLED
INPUT, EITHER THE KEYBOARD, OR THE AUXILIARY DEVICE (VIA
PRINTER PORT PORTION OF THE SYSTEM COMMUNICATION LOGIC):
IF DATA IS PRESENT FROM BOTH SOURCES, AND BOTH ARE
ENABLED, CPU LOGIC WILL DETERMINE WHICH DATA TO PROCESS
FIRST.
2. DATA IS TRANSFERRED FROM THE CPU LOGIC TO THE HOST, VIA
EITHER INTEGRAL MODEM, OR EIA HOST PORT PORTIONS OF THE
SYSTEM COMMUNICATION LOGIC
3. IF LOCAL-ECHO IS ENABLED, AND SCREEN DISPLAY IS TO BE
AFFECTED, CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY.

MA·1454-83

Figure 3-13

System Interaction in On-Line
(Printer Port as Input Port)

V
1. DATA IS TRANSFERRED TO THE CPU LOGIC FROM THE HOST, VIA
EITHER INTEGRAL MODEM, OR EIA HOST PORT PORTIONS OF THE
SYSTEM COMMUNICATION LOGIC
2

IF SCREEN DISPLAY IS TO BE AFFECTED, CPU LOGIC DIRECTS VIDEO
LOGIC TO ALTER DISPLAY.

3. IF DATA IS TO BE OUTPUT TO AN AUXILIARY DEVICE, CPU LOGIC
DIRECTS TRANSFER OF DATA AND CONTROLS TO AUXILIARY
DEVICE VIA PRINTER PORT PORTION OF SYSTEM COMMUNICATION
LOGIC
MA-1455-83

Figure 3-14

System Interaction in On-Line
(Printer Port as Output Port)

3-12

1. DATA IS TRANSFERRED BETWEEN THE CPU LOGIC AND THE HOST.
VIA EITHER INTEGRAL MODEM, OR EIA HOST PORT PORTIONS OF
THE SYSTEM COMMUNICATION LOGIC.
2. DATA IS TRANSFERRED BETWEEN THE CPU LOGIC AND THE
AUXILIARY I/O DEVICE VIA PRINTER PORT PORTION OF SYSTEM
COMMUNICATION LOGIC.

MA-1456-83

Figure 3-15

System Interaction in On-Line
(Printer Port as I/O Port)

3-13

CHAPTER 4
CPU LOGIC

4.1

GENERAL

The CPU logic (shaded area in Figure 4-1) directs VT240 activity
in response to either operator input (via keyboard), or host input
(via system communication logic).
In general, the CPU does the
following task.
•

Defines operating parameters for other logic components

•

Directs system communication
keyboard module operation

•

Initializes
programs.

system

logic,

video

power up, and executes self-test

SYSTEM BOX

I'I'

LOGIC

VIDEO
LOGIC

_ _ ..L. / _ _ _ _ _

SYSTEM
COMMUNICATION

EIA
HOST
PORT

PRINTER
PORT

20 mA
PORT

INTEGRAL

OPTIONAL
HOST
COMMUNICATIONS

MONITOR
(VR201 OR VR241)
MA·Q054-84

Figure 4-1

logic, and

VT240-Series Terminal System
Block Diagram
4-1

4.2

MAJOR CIRCUITS/COMPONENTS

Figure 4-2 is a block diagram that identifies the following major
circuits/components that make up the CPU logic.
Central processor unit (CPU)
Mode register
Control gates
Address la tch
Memory access decode
Read only memory (ROM)
Nonvolatile random access memory (NVR)
Volatile random access memory (RAM)

Memory map
Interrupt control
Command register
Clock generator
I/O buffer
I/O decode
Keyboard interface (I/F)

------------------1

CPU

1--==
I

CPU
LOGICI CLOCK

1...--/ ___
INTERRUPTS

CONTROLS

KYBD

DATA ADDRESS

PART OF SYSTEM
"..............
COMMUNICATION + VIDEO LOGIC .......... _ _ _ _ -

//
............

MA-0163-84

Figure 4-2

CPU Logic Block Diagram

4-2

4.2.1

Central Processor Unit

The CPU
(Figure 4-3) is a DCTII-AA, commonly referred to as the
TIl. The TIl is responsible for the terminal's functionality and
does the following tasks.
•

Generates initial control signals.

•

Compares data input to the VT240 against information
stored in ROM memory to determine operations desired

•

Initializes the system
programming
stored in
terminal's readiness

on power up, and executes test
ROM memory to determine the

BCLR

IN IT I-'

INIT L

All H-AI7 H

TO/FROM
RAM,INTR
CONTROL

DALO H-DAL15 H

TO/FROM
CPU LOGIC
CIRCUITS

TO
SYSTEM

DRAS L
FROM
CLOCK
GENERATOR

XTAL 1
Tll
DCAS L
TO
CPU
LOGIC
CIRCUITS

PI L

PI H
R/WLB H
R/WHB H
SEL 0
SEL 1

1-------=-'--

TO
}

CONTROL
GATES

MA-0144-84

Figure 4-3

CPU Block Diagram

4-3

4.2.1.1 T11 Internal Circuits -- Figure 4-4 is a block diagram
that shows the following major TIl internal circuits.
•

General Purpose Registers
(R0--R5)
are used for
various
functions,
including accumulating,
indexing,
autoincrementing, autodecrementing, stack pointers for
temporary data storage, and arithmetic operations.

•

Stack Pointer (SP) Register (R6) -- contains the address
of the last entry in the stack.

•

Program Counter
(PC)
Register
(R7)
contains
address of the next instruction to be executed.

•

Status Register -- contains information that defines the
current processor status.

•

Mode Register -- contains data that defines TIl operating
parameters, with this data loaded from the external mode
register during power-up sequence (refer to section 5.2.2
for a description of the values defined by the external
mode register).

•

Address Register
contains the RAM address
accessed by the next read or write operation.

to be

•

Clock
Buffers
generator.

clock

•

Power Control -- monitors power conditions by generating
a clear signal output for VT240 initialization when
sensing a power on condition.

•

Refresh Counter
defines the RAM address to be accessed
for a refresh operation.

•

Address
Multiplexer
multiplexes inputs from the
refresh counter and address register to generate an
address output to the address/interrupt buffers for
either a RAM refresh cycle (refresh counter input), or
RAM read/write cycle (address register input).

•

Address/Interrupt Buffers
and interrupt control input.

•

Control -- generates the control signals required for TIl
to access VT240 components.

buffers

4-4

timing

input

from

the

buffers RAM address output

16·BIT
INTERNAL
.
, - -BUS
-)

U
RO

VCC
GND
BGND
PUP
INIT

R2
R3
R4

INSTRUCTION REGISTER

---------

R6{SPI

ADDRESS REGISTER

I
=

REFRESH COUNTER

I I

STATUS REGISTERl
INTERNAL
CONTROL

MODE REGISTER

{

ADDRESS MULTIPLEXER

I
XTALI

IDATA/ADDRESS
I
BUFFERS

R/WHB H

DALO H· DAL 15 H

CONTROL

l}
CLOCK BUFFERS

ALU

R7 (PC)

ADD RESS/INTE R RUPT
BUFFERS

AIO H· AI7 H

DCAS L
DRAS L

R/WLB H

SELO·1

MA·0171·84

Figure 4-4

Tll Internal Block Diagram

•

Internal
Control
generates the
required by the TIl internal circuits.

control

signals

•

Data/Address Buffers -- are two I/O devices that provide
buffering between the DAL0 H--DALI5 H external bus and
the TIl internal bus.

•

Instruction Register
contains data that defines the
operation to be initiated by the control circuit outputs.

•

ALU
performs
operations.

all arithmetic and logical instruction

Later in this chapter, Table 4-6 describes the signals shown in
Figures 4-3 and 4-4.
4.2.1.2 Tll Transactions
A transaction is an activity that
performs one of the following functions.

Read
write
Refresh
Assert priority in (ASPI)
No operation (NOP)
Each transaction is made up of either one or two microcycles: two
microcycles for read and write transactions or one microcycle for
refresh, ASPI, or NOP. Each microcycle is the activity required to
execute one micro-instruction. The microcycle performs all the
functions
necessary
for
transferring
data internally and
externally, and for calculating values.
Each read, write, refresh, and NOP microcycle is contains three
clock phases: 01, 02, and 0W. ASPI transactions contain a fourth
clock phase, phase D (0D), which is added between 02 and 0W. All
clock phases have the same duration between assertions, and are
developed from the 7.3728 megahertz (MHz) input supplied by the
clock generator. A three phase microcycle has a 813.6 nanoseconds
(ns) duration; a four phase microcycle has a 1084.6 ns duration.
Figure 4-5 is a timing diagram for the power-up sequence. Figure
4-6 is a timing diagram for Tll transactions. Figures 4-7 through
4-10 show ports of the Tll timing diagram (Figure 4-6) that
identify specific conditions involved in each diagrammed bus
transaction
(no diagram is provided for NOP because no Tll
external operation occurs).

4-6

r-PUP

50}.ts

----J

J-1 r- \L..\....l.\~-'--------IS~S-------<S~S-ss
100

INIT L \ \ \ \ \ \ \ \ \

MODE REGISTER

MODE REGISTER
LOAD

DAL<150>

w,o>

~~AD

=:: ~ ~ ~ X

==]((((({((((((C ))t~ ====
-1((((((((((((((((((::

mmll)lfF m[3"

- - - ,..------------1\5\---------.---j.-l\SI-.,,-----j..--RAS L _ _

\_ ~ . ./

NOTES
1. MODE REG RD 2.6 }.ts AFTER PUP L.
2. OUTPUTS SET 250 ns AFTER PUP H.
3. FIRST FETCH 89}.ts AFTER PUP H
AT ADDRESS: 000000.
4. INIT L 30 ns AFTER BCLR L:
A MAPPER OFF;
B 8085 RESETS;
C. KYBD UART RESET & LPBK OFF;
D. COMM SEL ... EIA CONN;
E. HOST/PRTR UART RESET.
(DISABLES Tx & Rx, STOPS CTR/TIMER,
ALL OUTPUTS HI;
F. MODEM OPTION
(DESELECTED, BELL 212A, 1200 BAUD,
DOMESTIC, 10 BITS, TEST OFF, ANSWER,
AND OFF-D HI,
G, NVR RECALL
MA-0135-84

Figure 4-5

Power-Up Sequence

4-7

DAL 15:0

ADDRESS

521 ns
DAL 15:0

ADDRESS

DATA OUT

335.6 ns
AI 7:0

RAS

"""'<

ROW

87.6 ns

CAS

DATA IN

COL

INTR

1----1 1042 / - -

}o-76 nS--1 -oj
93 ns

1--146 ns

PI H

577 ns

317 ns

501--

1--107.6 nS+-234 ns----l

R/WLB

MEM MAP

68 n s F

DRAS L

__ 94.9 ns

DCAS L
PI L

584 ns

324.5 ns

1--146 ns

1--123 ns--l--249 ns

NOTES

1 RAS PRECHARGE 151 ns <
2. MAX RD DATA AVAIL 493 ns
3. CAS H TO DAL <15:0> 118 ns <
MA·Q252·84

Figure 4-6

Tll Timing Diagram

4-8

DAL<15:0>

AI<7:0>

RAS L
CAS L

CAS L
RAS L

R/WHB H

R/WLB H

'----y---'
ADDRESS STROBES
MA-4849

MA·0134-84

Figure 4-7

Tll 16-Bit Dynamic Read
Transaction Diagram

4-9

DAL<15:0>

DATA OUT

AI<7:0>

RAS L

CAS L

R/-WHB
R/-WLB

RIWHB H
RIWLB H

'---y------J

'---v-----"

ADDRESS
STROBES

DATA STROBES

MA·0137-84

Figure 4-8

TIl 16-Bit Dynamic Write
Transaction Diagram

4-10

DAL < 150>

««<<<<<<<<<<»»»»))))))))))))

AI <7:0>

REFRESH ADDRESS

RAS L

CAS L

SEL <0>

4116K
MODE

SEL <1>
MA-4865
MA-0136-84

Figure 4-9

TIl Refresh Transaction Diagram

INT,
REQUEST

AI <1:4>

RAS L

CAS L

MA-4863
MA-0138-84

Figure 4-10

TIl ASPI Transaction Diagram

4-11

4.2.2

Mode Register

During power-up sequences, the Tll inputs the values of DAL0 H -DAL15 H and loads these values into its internal mode register.
The loaded bits define operating parameters.
The mode register (Figure 4-11) drives five of the DAL lines low
during power up sequences.
INIT L goes low, enabling the mode
register to pass ground values to the five DAL lines. All other
DAL lines remain high, providing "1" states to the Tll for their
values.
Table 4-1 lists the values associated with each of the 16 DAL
lines during a power-up sequence, and defines the Tll operating
modes selected by those DAL values.
Later in this
Figure 4-11.
4.2.3

chapter, Table 4-6 describes the signals shown in

Control Gates

The control gates generate control signal outputs in response to
CPU control and flag signal signals. The control gates (Figure
4-12) consist of the following two decoding circuits.
•

Output Flag Decode Gates -- decode SEL0 -- SELl inputs to
enable either refresh activity (REF H), or address strobe
activity
(RRAS L from DRAS L), with strobe activity
occurring with or without I/O decode operation (BUSOP L).

•

R/W Decode Gates -- decodes CPU read and write control
signals
(R/WHB Hand R/WLB H), and asserts priority
signals
(PI H and PI L)
into read and write control
signal outputs.

Table 4-2 provides a truth table for the output flag decode gates.
Table 4-3 provides a truth table for the read/write (R/W) decode
gates. Later in this chapter, Table 4-6 describes the signals
identified in Figure 4-12.

DAL 0 H
DAL 8 H
MODE
REGISTER

DAL 9 H
DAL 10 H
DAL 13 H

FROM

CPU
DAL BUS
LINES

INIT L

CPU

MA.0140·84

Figure 4-11

4-12

Mode Register

Table 4-1

DAL Signal Values During Power-Up Sequence

Bit

Va 1ue (s)

Mode Selection

DAL0 H

Constant clock timing input

DAL1 H

Standard microcyc1e (3 clock
phases)

DAL2 H -- DAL7 H

All l's

Reserved

DAL8 H

Normal read/write cycle

DAL9 H

Dynamic memory

DAL10 H

4K/16K memory

DAL11 H

16-bit bus

DAL12 H

User

DAL13 H -- DAL15 H

Octal 5

Start address of
000000/restart 000004

Table 4-2

Output Flag Decode Gates Truth Table

SEL 0

Input Values
SEL 1
DRAS L

REF H

Output Values
RRAS L
BUSOP L

= Don't care

4-13

Table 4-3

R/W Decode Gates Truth Table

R/WHB H

Input Values
R/WLB H
PI

RD H

Output Values
DRD L
WLB L

= Don't care

~~~LA7----""1

I DECODE

FROM CPU

{

I GATES

~S=EL_1~;I~

REF H
..::S;:,:EL:....:O'----h_ _ _ _ _-L~~y---+.:.::.:....'-'-----}
TO RAM

>---1Fc:..:....=---....

D RA S L

BUSOP L

L-f-_ _ _ _ _ _ _ _ _""'----~r-+---- TO I/O DECODE

L _______ ~

TO I/O BUFFER
TO RAM
TO NVR

R/WHB H
R/WLB H

TO I/O DECODE
TO CMD REG

FROM CPU

PI H

TO MEM MAP

PI L

}-------+='-"--+-+ TO MEM MAP

I
L _____ --1

~ TO SYSTEM COMM
TO I/O DECODE

MA·0159·84

Figure 4-12

Control Gates Block Diagram

4-14

4.2.4

Address La tch

The TIl uses the DAL signal lines to define an address to be
affected by read or write operations, and to transfer data to or
from that address. The address latch (Figure 4-13) stores the
address to be affected by a data transfer activity.
Later in this
Figure 4-13.

chapter, Table 4-6 describes the signals shown in

5-V

- D-A '-H---LD-A-'
\r-DA- L-,-H--DA-L-'5-H"') ALADTDCRHESS I-L
/

FROM
CPU

[

DRAS L

TO ALL
VT240
ADDRESSABLE
COMPONENTS

I
MA·0139--84

Figure 4-13

4.2.5

Address Latch Block Diagram

Memory Map

The memory map extends TIl addressing from 16 bits (32KW/64KB) to
20 bits
(512KW/IMB), by adding address (from address latch) and
data
(from I/O buffer)
inputs to develop values for the most
significant 8 bits of the mapped 20-bit address.
The
memory
map
(Figure
circuits/conponents.

4-14)

consists

the

following

•

Map Input Mux
is enabled by MEM MAP CS L true (low) to
pass values of LDA12 H -- LDA15 H to the inputs of the
map adders. (When MEM MAP CS L is high, or false, LDAI H
through LDA4 H values are muxed through to the map
adders. But, the map adders are disabled from using these
signals by a high input from the map adders gate.)

•

Map Adders Gate -- ORs MEM MAP CS Land WLB L to generate
read/write control to the map adders, with a write
control
(low output) from the gate only when both inputs
are true (low).

4-15

FROM CPU -,-P.:...I"-.L------1r------\
MEM MAP SEL L
FROM I/O {
DECODE
MEM MAP CS L
FROM CONTROL .:;:D.:..:;RD;:....::...L- - - + - - - f .
GATES
RDAD H - RDA7 H

~~~~ESS{
LATCH

LDAl H - LDA4 H

_ _ _ _ _---""
LDA 1 2 H - LDA 1 5 H
FROM I/O
DECODE

MEM MAP CS L

FROM CONTROL-"W:..=L"-B-=.L------t
GATES

MAP ON H

MDA12 H - MDA15 H

rM~D-A1-6-H----:-:M":"DA~1:-::9""7H-:--"

lOA 1 2 H - LDA 1 5 H

t-...;.;..;.~-----v'

'-T--.-"T'"""I....

} :~~::ORY
ACC ESS
DECODE

MA-0157-84

Figure 4-14

Memory Map Block Diagram

•

Map Adders
are two adder devices, each enabled by a
low input from the map adders gate for write operation.
One adds map input mux inputs to RDA0 H -- RDA3 H inputs
from the I/O buffer, and the other adds map input mux
signals against RDA4 H
RDA7 H inputs from the I/O
buffer. (When a high is present from the map adders gate,
the adders are enabled to read out the value obtained
during the last write operation.)

•

Memory Map Register -- is enabled by ORed MEM MAP CS L
and ORO L low inputs (both true) to output address values
contained in the map adders. This gives Tll the means to
verify value.

4-16

512KW/1 MEG.

3777776

320KW/640KB

2377776

RAM OPT
272KW/544KB

2100000
RAM

256KW/512KB

2000000

96KW/192KB

577776

ROM 3

400000

64KW/128KB

ROM 2
32KW/64KB
30KW/60KB

1///110 PAGE /1,

200000
170000

ROM 1

T11

000377
000000
MA-0151-84

Figure 4-15

VT240-Series Terminal
Address Map

•

Map Control
is set or reset,
depending on the
condition of RDA0 H, by ORed MEM MAP SEL L and PI L low
inputs (both true), with the MAP ON H output acting as an
input select signal for the map output mux.

•

Map Output Mux
consist of two mux devices, each
enabled by MAP ON H high
(true)
to pass map adders
inputs, or, when MAP ON H is low (false), to pass LDA12 H
LDA15 H out as MDA12 H -- MDA 15 H, and all low
conditions
(from ground inputs) out as MDA16 H -- MDA19
H.

Figure 4-15 is an overall address map of the VT240. Later in this
chapter, Table 4-6 describes the signals shown in Figure 4-14.

4-17

4.2.6

Memory Access Decode

Memory access decode generates the select signals for ROM and RAM
access. Memory access decode is enabled by 10 EN H low (false) and
DRAS L low (true) to decode MDA inputs from the memory map into
any of four possible signals. Three ROM select signals, or a
select signal for RAM access (Figure 4-16).
Later in this
Figure 4-16.

4.2.7

chapter, Table 4-6 describes the signals shown in

Read Only Memory (ROM)

ROM stores the firmware required for terminal operation. A ROM can
consist of up to six separate ROM devices, with a total ROM space
of 96K bytes (Figure 4-17).

ROM 1 CS L
MEMORY
ACCESS
DECODER

MDA15 H - MDA19 H*

ROM 2 CS L
ROM 3 CS L
RAM CSL

}TO ROM
TO RAM

*MDA18H
IS NOT USED

FROM
I/O DECODE

I/O EN H

DRAS L
FROM CPU - - - - - /

Figure 4-16

MA·0150-84

Memory Access Decode Block Diagram

FROM
ADDRESS
LATCH

FROM
MEMORY
MAP

FROM
CPU

\MDA12 H - MDA14

ROM
2
(LO!

ROM
3
(LO!

ROM
1
(HI!

ROM
2
(HI!

ROM
3
(HI!

DALO H - DAL 15 H

TO
CPU

'--1-

DCAS
-,
L - - _ L -J

M~~OO~Y {_:_::_:_:_:_~
ACCESS
DECODE

H:>j

ROM
1
(LO!

_ _ _ _ _ _ _ _----J

ROM 3 CS L
MA-0142-84

Figure 4-17

Read Only Memory (ROM) Block Diagram

4-18

Figure 4-17 shows how
the VT240 logic board.
logic board have arrays
X 8 bit devices, and two

ROM is arrayed in the original version of
However, subsequent versions of the VT240
that consist of four ROM devices: two 16K
32K X 8 bit devices.

Regardless of the actual physical array, ROM select inputs (ROMI
CS L
ROM3 CS L), in conjunction with address latch (LDAI H -LDAll H) and memory map inputs (MDA12 H -- MDA14 H), define which
location of ROM is to be read. The read occurs when DRAS L is low
(true) at the same time as a low ROM Select input low (true).
Later in this
Figure 4-17.
4.2.8

chapter, Table 4-6 describes the signals shown in

Random Access Memory (RAM)

RAM provides the TIl with 32K byte/16K words of memory for various
functions,
such as buffer space, scratch pad operations, and data
storage.
RAM is involved in three types of TIl transactions: read, write,
and refresh.
During read and write transactions, addressing a specific memory
location is done by first defining a row address (1 of 128), and
then defining a column address (1 of 16) within that row. (Refer
to Figure 4-6, the TIl timing diagram, and Figure 4-7 and Figure
4-8, the TIl read/write transaction diagrams.)
During refresh transactions, only row addressing is required. RAM
is refreshed after 128 refresh cycles (one cycle for each of the
128 rows).
The RAM circuit (Figure 4-18) consists of the following circuits
and components.
•

RAM CAS Gates -- consists of nine gates that enable read
(read word only)
or write (write upper, lower, or both
bytes). The gates generate CAS L outputs when RAM is
selected and enabled, with one CAS signal for each byte
of RAM to be accessed for a read/write transaction.

•

RAM Address Buffer -- passes five least significant bits
of row and column addresses. The buffer is transparent
during
row
addressing,
and latched during column
addressing
(DCAS L low, or true, is a latch enable that
prevents buffer output values from being affected by new
input values until DCAS L returns high.)

•

RAM Address Input Mux -- is enabled by REF H to select
either liB II or II All
inputs. The input mux selects IIBII
inputs
(ground, AI7 H, and MUX H, which is tied to +5 V)
when REF H is true
(high). The input mux selects IIAII
inputs
(MDA15 H, MDA13 H, and RRAS L), when REF H is low
(false) •
4-19

FROM\
CPU
RAM CS L
FROM
R/W DECO DE

DALOH-DAL15H

RD H

RAM
CAS
GATES

PI H
DCAS L

RAM LO
CAS L
RAM HI
CAS L

i i

RD/WlJl H

RD/WRB H
DRAS L

FROM
CPU

~ RAM

All H - AI5 H

RAMO -RAM4

ADDRESS
BUFFER

MUX H

MDA15 H
FROM
MEM (MDA13H
M,;P
{RRAS L
FROM
CONTROL
REF H
GATES

RAM
DEVICES

RAM7W

AI7 H
+5V

'\
./

RAM6 H
RAM
ADDRESS
INPUT
MUX

f--

FROM
MEM
MAP

RAM
ADDRESS
OUTPUT
MUX

FROM AI6 H
CPU

roe"

MDA14H

RAM5 H

MDA12 H

RAM MUX H

*RAM7
OUTPUT IS
NOT USED

<-;
A

TO CPU

J
DALO H - DAL15 H
MA-0165-84

Figure 4-18

Random Access Memory (RAM) Block Diagram

•

RAM Address Output Mux -- The output mux is enabled by
RAM MUX H to select either "B" or "A" inputs. "B" inputs
(ground,
AI? H passed by input mux, and AI6 H) when RAM
MUX H is true
(high developed from MUX H input to the
input mux during refresh transactions). The output mux
selects "A"
inputs (MDA16 H, MDA14 H, and MDA12 H) when
RAM MUX H is false (low developed from RRAS L input to
the input mux during read/write transactions).

•

RAM Devices -- consist of 16 MOS 16K bit X 1 RAM devices,
arrayed in 2 banks of 8 bits. One bank is for the most
significant byte of memory
(enabled for read/write by
DCAS L,
DRAS L, and RD/WHB H inputs, and for refresh by
RRAS L only). The other bank is for the least significant
byte
(enabled for read/write by DCAS L, DRAS L, and
RD/WLB H inputs, and for refresh by RRAS L only).

Figure 4-19 is a diagram of the RAM CAS gates. Figure 4-20 is a
diagram of the RAM device array. Later in this chapter, Table 4-6
describes the signals shown in Figures 4-18, 4-19, and 4-20.
4-20

FROM
PI H
CPU
FRO M -,-Rc..::D'-'-'.H.---I
CONTROL
GATES

FROMDCAS L
CPU
ACCESS
DECODE

FROM RD/WHB H

RAM LO CAS L

CPU
TO
RAM
DEVICES

RAM HI CAS L

MA-0164-84

RAM CAS Ga tes

Figure 4-19

FROM RAM CAS
GATES RAM LO CAS L

FROM T11 R/WLB H

I r I i DAL
0
DAL 1
DAL 2
DAL 3
DAL 4
DAL 5
DAL 6
DAL 7
FROM RAM CAS
GATES RAM~H~I~C~A~S~L~~--lr--~----r----r----r---~---r--~
FROM Tll R/WHB H

D15

D14

D13

D12

Dll

Dl0

TOI
FROM
Tll

DAL 11
DAL 12
DAL 13
DAL 14
DAL 15
NOTE
ADDRESS AND RRAS L
INPUTS ARE NOT SHOWN
MA·0152-84

Figure 4-20

RAM Devices Array

4-21

4.2.9

I/O Buffer

The I/O buffer provides isolation between the DAL lines (l6-bit
bus, which the TIl uses for memory data transfers, and address
data transfer to the address latch) and the RDA lines (eight-bit
bus, which the TIl uses for data transfer to or from the various
system I/O devices) •
The I/O buffer (Figure 4-21) consists of the following components.
•

I/O Buffer Device -- is a bidirection buffer enabled by
DCAS L to pass data in direction determined by direction
gate input.

•

Direction Gate (DIR GATE) -- determines the direction of
data transfer by the I/O buffer. Data is transferred from
the RDA lines to the DAL lines only when both IO EN Hand
RD H are true (both high). Data is transferred from the
DAL lines to the RDA lines for all other conditions
(during TIl read/write of memory, data is transferred by
the I/O buffer to the RDA lines, but has no effect, as no
I/O device is enabled).

Later in this
Figure 4 -21.

TO/FROM CPU

FROM
I/O DECODE

chapter, Table 4-6 describes the signals shown in

DALD H -

DALl H

I/O
BUFFER

RDAD H -

RDAl H

TO/FROM
CMO REG, NVR
KYBO I/F, VIDEO
LOGIC, AND SYSTEM
COMM LOGIC

10EN H

FROM CONTROL _R_D_H----i
GATES
DCAS L
FROM CPU - - - ' - - ' - - - - - - - - - - '
MA-0141-84

Figure 4-21

I/O Buffer Block Diagram

4-22

4.2.113

I/O Decode

The
I/O decode circuitry decodes control and address inputs to
determine when the TIl is attempting to access an I/O device, then
generates the select signals needed for the access.
I/O
decode
(Figure
circuits/components.
•

4-22)

consists

the

following

I/O Enable Gates -- AND the most significant four bits of
the address
output
from
the address latch, providing
partial
enables
to
the I/O decoder and the I/O buffer,
when all four bits are high (which occurs for octal code
17XXXX addresses).

MEM MAP CS L

TO
=tMEM
MAP

MEM MAP SEL L

LDA5 H - LDA6 H

CMD REG RD L
FROM
ADDRESS
LATCH

TO CMD REG

~~~~~_.TONVR

RD BUF L
WR BUF L

LDAl H - LDA2 H

8085 RESET L

VIDEO
LOGIC

. - - - - - , MEM
MAP L

WR 8UF L
FROM WLB L
CONTROL
GATES

KYBO L
TO
'"'H':"';O"'::S":::'T/"':P-RT-R-L-t-='c.c..:...::'-=---------_ KYBD I/F
FROM
ADDRESS

LDA9 H - LDAll H

LATCH

I/O
DECODER

GRD L
GWRB L

1-"-'-':"';"':""::""---+---,
G85 L
NVR L

MODEM L

NVR

'---__...--' FROM
CONTROL ~W~LB~L!:..lr~--L-~V~ID::"":::AC~C=E~S~S~L.
GATES
INIT L
FROM{
CPU
DRAS L

GWLB L
DCAS L

FROM
CPU

GRD L

} TO
VIDEO
LOGIC

FROM
BUSOP L
CONTROL
GATES

1 - - - - - - + TO I/O BUFFER
FROM
_ _ _2R£D..!::H'-_ _.r---WC:20~M~M~W~R~L~_ _}
CONTROL
LDA 1 H
FROM--,---+j
GATES
ADDRESS
COMM
COMM RD L
RD/WR t-=:.:.:::.:.:...:...;::::....::---.
LATCH
GATES
FROM
DCAS L
CPU

TO
KYBD I/F
AND SYSTEM
COMM LOGIC

MA-0158-84

Figure 4-22

I/O Decode Block Diagram

4-23

•

Decode Gate
ORs DRAS Land BUSOP L, providing one
enable to the I/O decoder when both are low (both true).

•

I/O Decoder
is enabled to decode LDA9 H -- LDAll H
into select outputs when INIT L is high (false), and when
the decode gate and I/O enable gates are providing low
inputs.

•

Mem Map/8085 Decoder
this dual decoder device is
enabled to decode LDA5 H -- LDA6 H inputs into MEM MAP CS
L, MEM MAP SEL L, CMD REG RD L, or NVR STORE L output,
when MEM MAP L input from the I/O decoder is low (true).
Or, the dual decoder device is enabled to decode LDAl H
-- LDA2 H inputs into RD BUF L, WR BUF L, or 8085 RESET L
output, when G85 L input from the I/O decoder is low
(true) •

•

WR BUF Gate -- ties the WR BUF L select signal to WLB L.

•

Graphics R/W Gates -- consists of the AND gate and two OR
gates. The AND gate generates a VID ACCESS L low output
(true) whenever either GRD L or GWLB L is low (true). The
OR gates tie GRD L to DCAS L, and GWLB L to WLB L.

•

Communications (Comm) R/W Gates -- gates DCAS L with LDAl
signals to generate either COMM WR L (LDAl signals true),
or COMM RD L (LDAl signals false). The RD H input is used
to disable COMM WR L when RD H is true (high).
NOTE
The comm R/W gates operate independently
of the remaining I/O decoder circuitry,
but their outputs affect only an I/O
device that is enabled by a specific I/O
decoder select signal output.

Table 4-4 shows the address values for all the I/O decode select
signal outputs.
Later in this
Figure 4-22.

chapter, Table 4-6 describes the signals shown in

4-24

Table 4-4

I/O Addresses

Signal

Octal Address

Destination

MEM MAP L

17exxx

MEM MAP/8e85 decoder

MEM MAP CS L

17eexx

Memory map

MEM MAP SEL L

171313413

Memory map

CMD REG RD L

171311313

Command register

NVR STORE L

17131413

NVR

KYBD L

171eex

Keyboard I/F

HOST/PRTR L

172exx

System comm logic

GRD L

173131313

Video logic

GWLB L

174131313

Video logic

VID ACCESS L

173131313/174131313

Video logic

G8e85 L

175eex

Video logic

RD BUF L

175131313

Video logic

WR BUF L

17513132

Video logic

81385 RESET L

17513134

Video logic

NVR L

176XXX

NVR

MODEM L

177eex

System comm logic

x = Indicates that a specified select signal can be active for
various addresses within the defined range, as different functions
can be addressed while the specified select signal is active.

4-25

4.2.11

Keyboard Interface (I/F)

The keyboard I/F controls the data transfer between the TIl and
the keyboard module.
Parallel data for the keyboard (command or
parameter information for the keyboard module) is written to the
keyboard
I/F,
where it is converted to serial data, and
transferred to the keyboard module. Serial data input from the
keyboard module
(key codes and status) is converted to parallel
data, and read out of the keyboard I/F by the Tli. The keyboard
I/F uses interrupts to inform the Tll (via interrupt control) when
the keyboard I/F is ready to transfer more data to the keyboard
module, or when data from the keyboard module is ready for the
Tll.
The
keyboard
I/F
circuits/components.

(Figure

4-23)

consists

the

following

•

825lA USART Device
is a programmable USART directly
responsible for communications with the keyboard
module.

•

Loopback Gates
are used for testing. The loopback
gates are enabled by 825lA output (LPBK EN L developed
from the DTR output of the 8251A) to route transmit (tx)
data back to the 8251A as receive (rx) data.

•

Keyboard Transmit Data (KYBD TxD) Buffers -- convert TTL
level tx data signals from 8251A into +12 V/-12 V level
outputs to the keyboard module.

•

Keyboard Receive Data (KYBD RxD) Buffers -- convert +12
V/-12 V rx data signals from the keyboard module into TTL
inputs to the 8251A.

•

Keyboard Clock
is a buffered output counter device
which converts CLK2 H input from the clock generator
(3.6864 MHz), into a clock input to the 8251A for general
operation
(1.8432 MHz) and an input for tx and rx timing
(3137.2 KHz).

•

J6
is a four-pin telephone plug-type connector which
provides a direct connection between the keyboard module
and the system box (Figure 4-23 shows a pin-out of J6).
NOTE
The keyboard module can also connect to
the monitor module, with keyboard data
signals routed through J8
(shown in
Figure 4-23).

4-26

KYBD
INTR2 l
TO/FROM
I/O
BUFFER

}

,o
_ _INTR1
K_YB_D_....
/'
l

FROM
ADDRESS
LATCH

lDA2 H

FROM
CPU

INIT H

~~~~!~l

8251A
USART

FROM

{'OMMwee

I/O
DECODE

KYBD l

COMM RD l

KYBD RxDH

4
+12V

GND

KYBD TxDH

TO/FROM
FROM
CLOCK
GENERATOR

ClK 2 H

} (MONITOR
CONNECTOR)
MA-0176-84

Figure 4-23

Keyboard Interface (I/F)

Block Diagram

4.2.11.1
8251A USART Internal Circuits -- Figure 4-24 is a block
diagram that shows the following major 8251A internal circuits.
•

Data Bus Buffer -- buffers data transfer between the TIl
(as
RDA0 H
RDA7
H) and registers within the 8251A
(command,
status,
transmit data,
and receive data
register devices).

•

Modem Control
is used by the TIl to generate the
loopback enable (LPBK EN L, generated by DTR output) for
IIF testing.

•

TxD Buffer -- converts parallel data input to a tx data
register into serial output for the keyboard module.

•

RxD Buffer
converts serial data input to a rx data
register into parallel data for transfer to the TIl.

4-27

TxD L

KYBD INTRl L
DATA
BUS
BUFFER

Tx!RxC

RxD
BUFFER

RxD L

INIT H
LDA2 H
KYBD L

Rx
CONTROL

R!W

KYBD INTR2 L

CLOCK
COMM RD L

LPBK EN L

COMM WR L

MODEM
CONTROL

CTS

MA-0149-84

Figure 4-24

•

825lA USART Internal Circuits
Block Diagram

R/W Control
contains command register programmed by
the TIl to define 825lA operating parameters, as well as
a status register to report operating conditions to the
TIl and circuits required to determine what type of
access is being attempted by the TIl. The TIl can attempt
the following types of access.
•

Data read
or true)

(LDA2 H low, or false, with COMM RD L low,

•

Data write (LDA2 H low, or false, with COMM WR L low,
or true)

•

Command write
(LDA2
true conditions)

4-28

H high and COMM WR L low, both

•

Status read (LDA2 H high and COMM RD L low, both true
conditions)
NOTE
Used
in VT240 Series terminal, TIl
defines a baud rate of 4800 bits per
second
(bps), l0-bit characters (1 stop
bit, 1 start bit, 8 data bits), and no
parity check.

Later in this chapter, Table 4-6 describes the signals shown in
Figures 4-23 and 4-24.
4.2.11.2 825lA USART Addresses -- The TIl accesses various 825lA
internal registers to program control, read status, and transfer
data to and from the 825lA. The TIl does this by addressing either
control/status registers (KYBD L low, with LDA2 H high, both true
conditions), or data registers (KYBD L low, or true, and LDA2 H
low, or false), for either read (COMM RD L low, or true) or write
activity (COMM WR L low, or true).
When programming 8251A operation, the TIl must write two separate
bytes of programming. The first byte written defines the mode
instruction format;
the second byte written defines the command
data for that mode format. Both bytes are written to the 825lA
command register immediately following a power-up sequence, or
following an 8251A internal reset.
Table 4-5 defines the 825lA internal registers that the TIl can
address, the register's address, the type of operation that
affects the register
(read or write), and the 825lA circuit in
which the register resides.
NOTE
provides
a
complete
Appendix
0
description of the bit values for the
status registers. This
command
and
not
give any further
manual
does
description of the data registers.

Table 4-5

825lA USART Addresses

Address

RD/WR

Circuit

171006
171004
171002
171000

WR
RD
WR
RD

R/W control
R/W control
TxD buffer
RxD buffer

Command register
Sta tus register
TxD register
RxD register

4-29

4.2.11.3 8251A USART Timing Diagrams -- Figure 4-25 is a timing
diagram for transmit data transfer activity. Figure 4-26 is a
timing diagram for receive data transfer activity.

tTxE
TxEMPTY

TxREADY

KYBD INTR1 L

LDA2 H
COMM WR L

TxD L

NOTES
1.

KYBD INTR1 L IS SHOWN ENABLED FOR rx READY
CONDITION.

tTxR IS A MAXIMUM OF 8 CLOCK PERIODS.

tTxE IS A MAXIMUM OF 20 CLOCK PERIODS.

Figure 4-25

8251A USART Transmit Data (TxD)
Timing Diagram

OVERRUN ERROR
(STATUS BIT)
KYBD INTR2 L

LDA2 H

COMM WR L

COMM RD L

RxD L

NOTES
KYBD INTR2 L IS SHOWN ENABLED FOR RX READY
CONDITION
2

TRxR IS A MAXIMUM OF 8 CLOCK PERIODS.

COMM RD L IS LOW (TRUE) FOR READING RX DATA, AND
COMM WR L IS LOW (TRUE) FOR WRITING CONTROL FOR RX
DATA INPUT.

LDA 2 H IS SHOWN HIGH (TRUE) FOR WRITING CONTROL FOR
RX DATA INPUT, AND LOW (FALSE) FOR READING RX DATA.
MA-0153-84

Figure 4-26

8251A USART Receive Data (RxD)
Timing Diagram
4-30

4.2.12

Nonvolatile RAM (NVR)

The NVR combines a
256 X 4 bit static RAM with a 256 X 4 bit
electically erasable ROM
(EPROM)
to provide memory for storing
terminal operating parameters, and allow those parameters to be
manipulated by the operator.
During a power-up sequence, data is transferred from the EPROM to
the NVR RAM portion. While in the NVR RAM, the data stored can be
altered. Operator keyboard input defines a new parameter, with the
Tl1 directing a write to NVR to alter the stored value.
Operator keyboard input can direct the terminal to save the
parameters currently stored in the NVR RAM as the new default
values for the terminal. When this occurs, the Tll directs the
transfer of values stored in the NVR RAM to be written into the
EPROM, effectively reprogramming the EPROM. At the next power-up
sequence, the new EPROM values are transferred back into the NVR
RAM, and these values now determine the terminal's starting
parameters.
The
NVR
(Figure
circuits/components.
•

4-27)

consists

the

following

NVR Strobe Gates -- are enabled by NVR STORE L low (true)
and LDA8 H low (false) to generate a store input to the
NVR device. The store input causes the NVR device to
transfer the values stored in its RAM memory into its
EPROM memory, reprogramming the EPROM.
FROM INIT L
CPU ----------------------------~.

FROM
ADDRESS
LATCH

LDA1 H - LDA8 H

r----,
NVR STROBE GATES

NVR
FROM
STORE L
I/O DECODE - - - - \
FROM
LDA8 H
ADDRESS
LATCH

~ ~-----r---I
-:E-

L _ _-

POWER DOWN +5V
..!!!2T~

TO/FROM
I/O
BUFFER

1- -

NVR
DEVICE

......J

RD H
FROM
CONTROL - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
GATES
FROM
I/O DECODE _NV_R_L_--\
DECODE
FROM DCAS L
CPU

Figure 4-27

MA-0148-84

Nonvolatile RAM (NVR) Block Diagram
4-31

•

Power Down Protect -- disables the NVR strobe output upon
sensing power-down condition to prevent the Tll from
accidently writing to NVR.

•

NVR CS Gate -- generates a chip select (CS) to the NVR
device when both NVR Land DCAS L are lows (both true) •
The CS input enables read or write transactions that
affect the RAM memory portion of the NVR device.

•

NVR Device
contains the RAM and EPROM memories that
perform the following NVR functionality.
•

Read Terminal Operating Parameters -- RD H is true
(high), DCAS Land NVR L are both low (both true) ,
and LDAl H -- LDA8 H define the portion of the NVR
device's RAM memory to be affected.

•

write Terminal Operational Parameters -- This is the
same as a read transaction, except RD H is low
(false).

•

Store RAM Values in EPROM
(true), with LDA8 H low (false).

•

Transfer EPROM Values to RAM
(true) during the power-up sequence.

Later in this
Figure 4-27.

NVR STORE L is low
INIT L goes low

chapter, Table 4-6 describes the signals shown in

4-32

4.2.13

Interrupt Control

The interrupt control circuitry provides information about any
pending interrupt requests to the TIl. This information is sent to
the TIl as a four-bit code (All H -- AI4 H) whenever PI L goes low
(true) •
Interrupt
control
components.

(Figure

4-28)

consists

the

following

•

Interrupt
(INTR)
Buffer
is a latched output buffer
device. The value of its inputs are clocked into the
output and latched
(by grounded enable input) at each
DCAS L low (true) condition.

•

Interrupt
(INTR)
Memory -- is a 512 X 4 bit ROM enabled
by PI L low
(true)
to output (as All H -- AI4 H) the
four-bit code at the memory location defined by inputs
from the interrupt buffer (PROD TEST2 L input is always
high, or false, as it is tied to +5 V) with this four-bit
code defining the current interrupt status to the TIl.

Later in this
Figure 4-28.

chapter, Table 4-6 describes the signals shown in

PROD TEST 2 L
+5 V
FROM
VIDEO 8085 RDY L
LOGIC
FROM
[- KYBD INTR2 L
KEYBOARD \: KYBD INTR 1 L
INTR
PRTR INTR2 L
BUFFER
HOST INTR2 L

'1>I~~"f

L
-"\
./

INTR
MEMORY

All H-AI4 H

TO
'" CPU

TIMER INTR L
PRTR INTRl L
HOST INTRl L

DCAS L

FROM(
PI L
CPU

Figure 4-28

MA 0167-84

Interrupt Control Block Diagram

4-33

4.2.14

Command Register

The
command register reports the status of various system
conditions to the T11 when the T11 directs a read transaction that
affects this register.
The command
components.

(Figure

4-29)

consists

of the following

•

Command Register
(CMD REG} Gate -- enables output from
the command register when CMD REG RD Land DRD L are both
low (both true).

•

Command Register
is a latched output buffer device.
The value of its inputs are clocked into the output on
each DCAS L low (true) condition, and those values read
out of the register (as RDA0 H -- RDA7 H) whenever a low
is input from the command register gate.

Later in this
Figure 4-29.

chapter, Table 4-6 describes the signals shown in

FROM MEM MAP

MAP ON H
PGM H

FROM ROM

A7 H

FROM RAM

LPBKEN L

FROM KYBD I/F
FROM VIDEO LOG IC
FROM SYSTEM COMM

MONITOR PRES L

COMMAND
READ
REGISTER

RDAO H - RDA7 H

J
y

I/O
BUFFER

MOD PRES L
8085 RDY L

FROM VIDEO LOG IC [

FROM
C PU

T11 L

FROM
CMD REG RD L
I/O DECODE
FROM
DRD L
CONTROL
GATES

DCAS L

CMD
) REG
GATE

MA-0166-84

Figure 4-29

Command Register Block Diagram

4-34

4.2.15

Clock Generator

The clock generator generates the main clock signals required for
the TIl, keyboard controller, and system communication logic
operations
(separate clock signals are generated for video logic
operations) •
The clock generator
components.

(Figure

4-30)

consists

the following

•

Crystal
(XTAL)
-- generates a 7.3728 MHz output used at
the CPU, and a
3.6864 output used by the keyboard
interface and system communication logic circuits.

•

Clock Buffer
to the TIl.

(CLK BUF) -- buffers the 7.3728 MHz output

(7.3728 MHZI
>---+TOCPU
XTAL

!-'C:.;:.L...:..:K2--,-,H--,-,(3.:..:...68,--64--'-')_ _ TO KYBD IIF
TO SYSTEM
COMMUNICATION LOGIC
MA-016().84

Figure 4-30

4.3

Clock Generator
Block Diagram

SIGNAL DESCRIPTIONS

Table 4-6 gives descriptions of all the signals identified in this
chapter. These descriptions are provided for reference, and are
listed alphabetically by mnemonic (numeric mnemonics are listed
last) •
4.4

SCHEMATIC REFERENCE INFORMATION

Table 4-7 identifies the logic board component coordinate, and the
schematic
page
and
coordinates
for
each
CPU
logic
circuit/component identified in this chapter.
NOTE
The reference listing is based on Rev. C
of the schematics (CS5415495-0-l).

4-35

Table 4-6

CPU Logic Signal Descriptions

Signal
Mnemonic

Signal
Name

Address Bi t 7

Description
Status input from RAM
reserved for use with 64K
RAM (currently tied to
+5 V) •

A12 L -- A19 L

Address Data Lines
12 through 19 Low

Active output from map
address used to develop
mapped address when memory
map is on.

All H -- AI7 H

Address Interrupt
Lines 1 through 7
High

Used by TIl to output RAM
address values and to
input interrupt data from
the interrupt control.

BUSOP L

Bus Operation Low

Control output from
control gates disabling
I/O decode when TIl is in
ASPI cycle.

CLK2 H

Clock 2 High

3.6864 MHz output from
clock generator which
provides general timing
for CPU and system
communication logics
components.

CLOCK

Clock

1.8432 MHz input to 825lA
from keyboard clock
developed from CLK 2 H
signal.

CMD REG RD L

Command Register
Read Low

True (low) output from I/O
decode enabling TIl access
of command register for
read transaction.

COMM RD L

Communication Read
Low

Control signal output from
I/O decode which, when
true (low), partially
enables a read transaction
affecting a communication
device (either the 825lA
keyboard controller, or
the DUART in the system
communication logic).

COMM WR L

Communication Write
Low

Same as COMM RD L, except
enables write transaction.

4-36

Table 4-6

CPU Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

CTS

Clear To Send

Input to 825lA which is
tied to ground to be
always true.

DAL0 H -DAL15 H

Da ta Address Li nes
o through 15 High

Used by TIl for output of
data and address values,
and for input of data.

DCAS L

Direct Column
Address Strobe
Low

Control signal output from
TIl used to enable various
circuits and components
for operation.

DRAS L

Direct Row Address
Strobe Low

Control signal output from
TIl used to enable various
circuits and components
for operation.

ORO L

Delayed Read Low

Control signal output from
the control gates whenever
a read activity involving
a fast I/O device is to
occur.

G85 L

Graphics 8085 Low

Enable to mem map/8085
decoder to allow this
device to decode inputs
into video logic select
signal.

GND

Ground

Operational potential
output to keyboard module
(J6, pin 3, or via J8).

GRD L

Graphics Read Low

Select signal from I/O
decode enabling TIl access
of graphics controller in
video logic for a read
transaction.

GWLB L

Graphics write Low
Byte Low

Select signal output from
I/O decode enabling TIl
access of graphics
controller in video logic
for a write transaction.

Description

4-37

Table 4-6

CPU Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

HOST INTRI L

Host Interrupt I
Low

Interrupt originating at
DUART in system
communication logic and
indicating DUART has data
received from the host
that is ready for the TIl.

HOST INTR2 L

Host Interrupt 2
Low

Interrupt originating at
DUART in system
communication logic and
indicating DUART is ready
to process data for a host
device.

HOST/PRTR L

Host/Printer Low

Select signal output from
I/O decode enabling TIl
access of DUART in system
communication logic for
read/write transaction.

INIT H -- INIT L

Initialize High
and Low

Initialize system during
power-up sequence to known
starting state.

IO EN H
IO EN L

I/O Enable High
and Low

Active outputs from I/O
enable gates whenever any
address within the 17XXXX
octal range is being
output from the address
latch.

KYBD L

Keyboard Low

Select signal output from
I/O decode enabling TIl
access of the 825lA
keyboard controller for
read/write transaction.

KYBD INTRI L

Keyboard
Interrupt 1 Low

Interrupt output from
825lA when receive data is
ready for processing.

KYBD INTR2 L

Keyboard
Interrupt 2 Low

Interrupt output from
825lA when ready to
process transmit data.

KYBD RxD H

Keyboard Receive
Data High

Data input to keyboard
module via J6, or J8.

Description

4-38

Table 4-6

CPU Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

Description

KYBD TxD H

Keyboard Transmit
Data High

Data input from keyboard
module via J6, or J8.

LDAl H -LDA15 H

La tched Address
Lines 1 through 15
High

Address outputs from the
address used to access
memory and I/O devices.

LPBK EN L

Loopback Enable
Low

Test control signal
enabling TxD L from 8215A
to be looped back to the
8251A as RxD L. Also used
as status input to command
register to report
loopback condition.

MAP ON H

Map On High

Enables memory map to
select mapped address
values for output when
true (high), and regular
address values when false
(low). Also used as status
input to command register
to report memory map on or
off condition.

MDA12 H
MDA19 H

Mapped Address
Lines 12 through
19 High

Most significant 8 bits of
mapped 20-bit address
output from the memory
map.

MEM MAP L

Memory Map Low

Enables memory map/8085
decoder to decode inputs
into a select output for
memory map, command
register, or NVR access by
the Tll.

MEM MAP CS L

Memory Map Chip
Select Low

Selects signal output from
I/O decode enabling memory
map address to add data
and address to achieve new
mapped address value.

MEM MAP SEL L

Memory Map Select
Low

Selects signal output from
I/O decode enabling Tll to
turn memory map on and
off.

4-39

Table 4-6

CPU Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

MOD PRES L

Modem Present
Low

True (low) status input to
the command register from
the system communication
logic whenever the
integral modem is
installed in the terminal.

MODEM L

Modem Low

Selects signal output from
I/O decode enabling TIl
access of various comm and
modem control and status
registers within the
system communication
logic.

MONITOR PRES L

Monitor Present
Low

True (low) status input to
command register from
video logic whenever a
monitor is hooked up to
the system.

NVR L

NVR Low

Selects signal output from
I/O decode enabling TlI
access of NVR for read/
write transaction.

NVR STORE L

NVR Store Low

Selects signal output from
I/O decode which enables
transfer of data from NVR
RAM to NVR EPROM.

PGM H

Program High

Status signal from ROM
reserved for use with 32K
ROM.

PI L -- PI H

Priority In Low
and High

Control signal outputs for
the Tll which are active
signals during read,
write, and ASPI
transactions.

PRTR INTRI L

Printer Interrupt I
Low

Interrupt origianting at
DUART in system
communication logic and
indicating receive data
from a device on printer
port is ready for the TIl.

Description

4-40

Table 4-6

CPU Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

PRTR INTR2 L

Printer Interrupt 2
Low

Interrupt originating at
DUART in system
communication logic and
indication DUART is ready
to process data for a
device on the printer
port.

R/WLB H
R/WHB H

Read/Write Low Byte
and Read/Write
High Byte Highs

Read/write control outputs
from TIl defining type of
read/write transaction to
occur.

RAM0 -- RAM4

RAM Address Bits
o through 4

Outputs from RAM address
buffer which provide least
significant four bits of
column and row addresses
to RAM for read/write
transactions (or of row
address for refresh
transaction) .

RAMS H -- RAM6 H

RAM Address Bits 5
and 6 High

Outputs from RAM address
output mux defining the
most significant two bits
of row address for refresh
or read/write
transactions.

RAM7 H

RAM Address Bit 7
High

Reserved for use with 64K
RAM (currently tied to

Description

+5 V).

RAM CS L

RAM Chip Select
Low

True (low) output from
memory access decode
whenever RAM is to be
accessed for read/write
transaction.

RAM HI CAS L

RAM High Byte
Col umn Address
Strobe Low

True (low) output from RAM
CAS gates when active
column address is being
applied to the high byte
array of RAM.

4-41

Table 4-6

CPU Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

RAM LO CAS L

RAM Low Byte
Col umn Address
Strobe Low

True (low) output from RAM
CAS gates when active
column address is being
applied to the low byte
array of RAM.

RAM MUX H

RAM Mux High

True (High) output from
RAM address input mux when
RAM address output mux is
to select address value
for refresh activity, and
false (low) output when
address value is to be
selected for RAM
read/write transaction.

RD H

Read High

Control signal output from
control gates true (high)
for read transactions.

RD BUF L

Read Buffer Low

Select signal output from
I/O decode enabling TIl
access of data buffer in
video logic for read
transaction.

Remote Data Lines

Used for transfer of data
between the TIl (via I/O
buffer) and the various
system I/O devices.

REF H

Refresh High

Control signal output from
the control gates during
refresh transactions
affecting RAM.

ROMI CS L

ROM I Chip Select
Low

True (low) output form
memory access decode
whenever ROMI is to be
accessed for a read
transaction.

ROM2 CS L

ROM 2 Chip Select
Low

True (low) output form
memory access decode
whenever ROM2 is to be
accessed for a read
transaction.

RDA0 H -- RDA7 H

Description

o through 7 High

4-42

Table 4-6

CPU Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

ROM3 CS L

ROM 3 Chip Select
Low

True (low) output form
memory access decode
whenever ROM3 is to be
accessed for a read
transaction.

RRAS P

Remote Row Address
Strobe Low

Control signal output from
the control gates when Til
is to access RAM for
read/write activity.

RxD L

Receive Data Low

Data input to 8251A
originating at the
keyboard module.

SEL0 -- SELl

Select 0 and 1

Til output providing
two-bit code to control
gates with code value
defining the type of
transaction to occur.

Til L

Til Low

Status signal input to
command register, low when
Til has written data to
character processor (CP)
in video logic, and high
when last data written has
been read by the CPo

TIMER INTR L

Timer Interrupt Low

Programmable interrupt
condition orginating at
DUART in system
communication logic.

Tx/Rx C

Transmit/Receive
Clock

307.2 kHz input to 8251A
from keyboard clock used
for transmit and receive
timing and developed for
CLK 2 H (3.6864 MHz).

TxD L

Transmit Data Low

Data output from 8251A for
keyboard module.

VID ACCESS L

Video Access Low

Select Signal output from
I/O decode whenever Til is
to access data buffer for
read or write transaction.

Description

4-43

Table 4-6

CPU Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

WLB L

write Low Byte Low

Control signal output for
the control gates whenever
a write transaction
affecting an I/O device is
to occur.

WR BUF L

write Buffer Low

Select signal output from
I/O decode enabling Tll
access of data buffer in
video logic for write
transaction.

XTAL 1

Crysta 1 1

Clock input to Tll from
clock generator (7.3728

Description

MHz) •

+12 V

+12 V dc

Operating output to
keyboard module (via J6,
pin 2, or via J8).

8085 RDY L

8085 Ready Low

Interrupt condition input
to interrupt control from
8085 at video logic
whenever the 8085 requires
Tll access.

8085 RESET L

8085 Reset Low

Select signal output from
I/O decode to reset 8085
device in video logic
whenever true (low).

4-44

Table 4-7

CPU Logic Schematic References

Circuit/Component

Logic Board
Reference
Numbers

Address la tch
Clock generator
CMO REG gate
COMM RO/WR gates
Command read register
Oecode gate
OIR gate
Graphics R/W gates
INTR buffer
INTR memory
I/O buffer
I/O decoder
I/O enable gates
J6
KYBD clock
KYBO RxO buffers
KYBO TxO buffers
LOA 1 INV
Loopback gates
Map adders
Map adders gate
Map control
Map input mux
Map output mux
MEM map/8085 decoder
MEM map register
Memory decode
Mode register
NVR CS gate
NVR device
NVR store gates
Output flag decode gates
Power down protect
RAM address buffer
RAM address input mux
RAM address output mux
RAM OAS ga tes

E41,E43
E45,Y2
E90
E48,E62
E91
E69
E47
E72,E90
E75
E74
E55
E68
E47,E54
J6
E27,E45
E62,E66,E67
E31,E69
E44
E31,E61,E62,E67
E133,E134
E71
E73B
E152
E132,E151
E89
E135
E35,E53
E40
E69
E56
E50,E70,E83
E44,E47,E71,E72
E50
E42
E87
E86
E28,E35,E48,E49

RAM devices

EI--E16

ROM devices
TIl

E19--E22,E39,
E85,E23,E28,E44

3
1

WR BUF GATE
8251A UART

E62
E44,E61

5
6

4-45

Schematic
Page
Coordinate
1
I
5
6
5

5
1
5
1
1
1
5
1
6
6
6
6
1
6
2
2
5
2
2
5
5
3
1
5
5
5
1
5
4
3
3
3

C2--C3
08
B3
C7
C2
C7
04
04
B2
Bl
03
07
BI--B2
B2
B5--B6
B2--B4
C5--C6
02
B4,03,04
06,C6
B7
02
07
04,C4
C7
B2
A7, A8, B7
05
A5
B4
A5--A7
B5--B6
A7
B7
02
C2
A6,A2,A3,
B2,B3
02-05,
B2-B5
07,04
B7--07/
B6/06
C4
C6-06/04

CHAPTER 5
SYSTEM COMMUNICATION LOGIC

5.1

GENERAL

The system communication logic
(shaded area in Figure 5-1)
interfaces with the printer port, and either the integral modem
option or the host (via the EIA host port or 20 mA port) •

SYSTEM BOX

LOGIC

/ / VIDEO
/
LOGIC

_ _ ..L / _ _ _ _ _

SYSTEM
COMMUNICATION
LOGIC

EIA
HOST
PORT

PRINTER
PORT

20 rnA
PORT

OPTIONAL
HOST
COMMUNICATIONS

MONITOR
IVR201 OR VR241)

MA·0054-84

Figure 5-1

VT240-Series Terminal System
Block Diagram

5-1

Printer interfacing is independent of host and integral modern
interfacing. Host and integral modern interfacing, however, are not
independent: when one interface is enabled (integral modern, EIA
host port, or 20 rnA port), the other two interfaces are disabled.
NOTE
Enabling and disabling the host and
integral
modern option interfaces is
primarily
a
function
of
firmware
response to system configuration data
supplied by set-up features.
System communication logic operation is completely under CPU logic
control. The CPU logic programs operating parameters, reads
status,
and directs data transfer to and from the system
communication logic.
MAJOR CIRCUITS/COMPONENTS

5.2

Figure 5-2 is a block diagram that identifies the following major
circuits/components that make up the system communication logic.

•
•
•
•
•
•
•

Dual asycronous receiver/transmitter (DUART)
Communications/modern control (COMM/MOD CONTROL)
Communication multiplexer (COMM MUX)
Printer interface (PRINTER I/F)
EIA host interface (EIA HOST I/F)
20 rnA interface (20 rnA I/F)
Integral modern option connector (J5)

5.2.1

Dual Asynchronous Receiver/Transmitter (DUART)

The DUART transfers host and printer data between the CPU logic
and the following interfaces.
•

EIA host interface

•

20 rnA interface or integral modern for host data

•

Printer interface for printer data

5-2

I
I
I
\
\
I
I
I
I
\
\
\
\

/
L

«f«

MUX

'='

l:J

S
::J

EIA
HOST

IIF

CONTROLS

___ -.J

_ --.J L

MA-0155-84

Figure 5-2

System Communications Logic Block Diagram

5-3

Figure 5-3 shows the following DUART components.

•

2681
DUART
functions.

•

MOD CD GATE -- consists of two gates, an AND and an OR.

performs

Device

the

data

transfer

OR
disables MODI CD L from EIA HOST I/F during
integral modem operation (CSLI H high gated with MODI CD
L) •

AND -- gates OR output with MOD2 CD L from integral modem
to generate single MOD CD L input to DUART.
5.2.1.1 2681
diagram that
circuits.
•

DUART
shows

Figure 5-4 is a block
2681 DUART internal

Internal Circuits
the following major

Data Bus Buffers
transfer data between the 2681
DUART's internal circuits and the CPU logic data lines.

TO/FROM
CPU LOGIC
DATA LINES

~DAO H - RDA7~
...

COMM RD L

HOST TxD L
)

I/F + J5
}

TO/FROM
EIA HOST
I/F

}

TO/FROM
COMM MUX

}

FROM
J5

MOD1 SI L
HOST DTR L

HOST/PRTR L

HOST INTR2 L

TO EIA HOST

HOST CTS L

~ LDA2 H- LDA5 '"~
TO/FROM
CPU
LOGIC

TO/FROM
COMM MUX

HOST RTS L

COMM WR L

HOST INTR1 L

HOST RxD L
MOD SPD SEL L

HOST DSR L
2681
DUART

MOD2 CTS L
MOD2 SI L
MODCD L

TIMER INTR L
PRTR INTR1 L
PRTR INTR2 L

MOD
CD
GATE

INIT H
CLK2 H

MOD2 CD L
MOD1 CDL
CSL 1 H
PRTR DTR L
PRTR DSR L
TxD B

}M"O"

FROM J5
FROM EIA
HOST I/F
FROM
COMM/MOD
CONTROL

PRINTER
I/F

RxD B

MA·0156-84

Figure 5-3

DUART Block Diagram

5-4

•

Operation Control
decodes read
(COMM RD L), write
(COMM WR L), address (LDA2 H -- LDA5 H), and chip enable
(HOST/PRTR L)
inputs to enable CPU logic access to
control,
status, and data registers within the various
2681 DUART circuits.

•

Timing
generates the
required for operation.

•

Channel A (Host) -- converts host transmit data to serial
data output
(HOST TxD L), and serial host receive data
input (HOST RxD L) to parallel data.

•

converts printer port transmit
Channel B (Printer)
data to serial data output (TxD B), and serial printer
port receive data (RxD B) to parallel data.

clock

and

baud rate signals

HOST TxD L

DATA
BUS
BUFFE"RS

HOST RxD L

DRD L
TxD B

..:..W:..::L=-B..::.L_~~ OPERATION
HOST/PTR L

CONTROL

RxD B

LDA2 H - LDA5 H
INIT H
PRTR DSR L
MOD CD L

CLK 2 H

MOD 2 CTS L
INPUT
PORT

MOD2 SI L
MODl SI L
HOST CTS L
HOST DSR L

TIMER INTR L

HOST DTR L
HOST INTR2 L
PRTR INTR 1 L

OUTPUT
PORT

HOST RTS L
MOD SPD SEL L
PRTR DTR L

PRTR INTR2 L

MA-016S-84

Figure 5-4

2681 DUART Internal Circuits Block Diagram

5-5

•

Interrupt
generates a programmable interrupt (TIMER
INTR L) to the CPU logic.

•

Output Port -- contains eight output ports programmed to
provide interrupt outputs
(HOST INTRI L, HOST INTR2 L,
PRTR INTRI L, and PRNT INTR2 L), data terminal ready
outputs
(HOST
DTR Land PRTR DTR L), and modem
handshaking outputs (HOST RTS L and MOD SPD SEL L).

•

Input Port
contains state change detection devices,
and seven input ports programmed to accept data set ready
inputs (PRTR DSR L and HOST DSR L), and modem handshaking
inputs
(MOD CD L, MODI CTS L, MOD2 CTS L, MODI SI L, and
MOD2 SI L).

Later in this chapter, Table 5-4 describes the signals shown in
Figure 5-3 and Figure 5-4.
5.2.1.2 2681 DUART Addresses -- The CPU logic accesses various
2681 DUART internal registers to program control, read status, and
data transfer to and from the DUART. CPU logic does this by
addressing specific devices (LDA2 H -- LDA5 H), for read (COMM RD
L)
or write
(COMM WR L) operations, while the DUART is enabled
(HOST/PRTR L).
Table 5-1 identifies the registers that can be addressed by
address,
read/write operation, and the involved circuit activity.
(Appendix o provides a complete description of the register bit
values.)
NOTE
Appendix D does not provide information
for the 172~7~,
172~72,
172~74,
and
172~76 addresses. Two of these addresses
are used simply to start (172~7~) or
stop (172~74)
the counter, while the
others are used to set (172~72) or reset
(172~76) the output register bits.
5.2.1.3 2681 DUART Timing Diagrams
Figure 5-5 is a timing
diagram for DUART transmit data activity, and Figure 5-6 is a
timing diagram for receive data activity.

5-6

Table 5-1

2681 DUART Addresses

Address

RD/WR Circuit

172000
172002
172004
172006
172012

RD
WR
RD
WR
WR

Host
Host
Host
Host
Host

Mode register 1 and 2
Mode register 1 and 2
Status
Data clock select
Command

172014
172016
172020
172022
172024

RD
WR
RD
WR
RD

Host channel
Host channel
Input port
Timing
Interrupt

Receive data
Transmit data
Input change
Auxiliary control
Interrupt status

172026
172030
172032
172034
172036

WR
RD
WR
RD
WR

Interrupt
Timing
Timing
Timing
Timing

Interrupt mask
Counter timer/upper
Counter timer/upper
Counter timer/lower
Counter timer/lower

172040
172042
172044
172046
172052

RD
WR
RD
WR
WR

Printer
Printer
Printer
Printer
Printer

Mode register 1 and 2
Mode register 1 and 2
Status
Data clock select
Command

172056
172060
172064
172066
172070

RD
WR
RD
WR
RD

Printer channel
Printer channel
Input port
Output port
Timing

Receive data
Transmi t da ta
Input port
Output port configuration
Start counter command

172072
172074
172076

WR
RD
WR

Output port
Timing
Output port

Output bits command (set bits)
Stop counter command
Output bits command (reset
bi ts)

channel
channel
channel
channel
channel

5-7

TxD BI
HOST TxD L
TRANSMITIER
ENABLED
PRTR INTR2 L
HOST INTR2 L
ITxRDY)
COMM WR L
HOSTCTS LOR
MOD2 CTS L
HOST RTS L

START
BREAK

OPRIO)= 1

STOP
BREAK

D5 WILL
NOT BE
TRANSMITIED

OPRIO)= 1

NOTES
1.

HOST RTS L IS USED ONLY BY AN EXTERNAL MODEM;

ALL MODEM HANDSHAKING SIGNALS ARE CONSIDERED
TRUE FOR EXTERNAL OR INTEGRAL MODEM COMMUNICATION IMOD SPD SEL L OUTPUT AND MOD SI INPUTS
WOULD AFFECT BAUD RATE OF TIMING FOR MODEM
OPERATIONS. BUT NOT RELATIONSHIP OF TIMING SHOWN);

ALL DTR OR DSR SIGNALS ARE CONSIDERED TRUE;

CTS INPUTS ARE ACTIVE ONLY FOR EXTERNAL OR INTEGRAL
MODEM COMMUNICI'.TION;

HOST DTR L IS NOT USED BY THE 20mA I/F;

PRTR DSR L WILL BE SAMPLED BEFORE TxD B OUTPUT
IF PRTR DSR L WAS NOT TRUE AT 2681 DUART POWER-UP.

MA-0145·84

Figure 5-5

5.2.2

2681 DUART: Transmit Data Timing Diagram

Communication/Modem (Comm/Modem) Control

The comm/modem control circuitry provides:
•

Storage for communication and modem control data received
from the CPU logic.

•

Information
and status.

the

CPU logic about comm/modem controls

Except chip select line outputs to the communication mux (CSL0 H
CSL1H, used to define the interface to be enabled for host
communication)
all comm/modem control circuitry is dedicated to
controlling the integral modem option.

5-8

RxD Bf
HOST RxD L
RECEIVER
ENABLED
RxRDY
ISROI _ _ _ _...J

+ _____

FFULL
ISR11 _ _ _ _ _ _ _

PRTR INTR1 L - - - - - - ,
HOST INTR1 L
COMM RD L
STATUS DATA
,

DB WILL
BE LOST

OVERRUN
I
ISR41 _ _ _ _ _ _ _ _ _ _ _ _ _ _-I...-=~

RESET
BY COMMAND

NOTES

INTR1 SIGNALS ARE SHOWN ENABLED FOR RxRDY;
2.

DTR AND DSR ARE CONSIDERED TRUE;

MODEM HANDSHAKING SIGNALS ARE CONSIDERED TRUE
FOR EXTERNAL OR INTEGRAL MODEM COMMUNICATION,
AND DISABLED FOR 20mA PORT, PRINTER PORT, AND EIA
HOST PORT NULL-MODEM COMMUNICATION.

MA-0169-84

Figure 5-6

2681 DUART: Receive Data Timing Diagram

5.2.2.1 Comm/Modem Control Circuits
following breakdown of comm/modem control.

Figure

5-7

shows the

•

Communication
Control
Register
(COMM CTRL REG)
contains a write register for storing control data
written by the CPU logic. The stored control data define
the enabled interface
(CSL0 H -- CSLl H output to the
communication mux). This register also contains controls
for the integral modem, if installed, and a read register
to enable CPU logic to verify the condition of write
register bits.

•

Modem Control Write Register
(MOD CTRL WR REG)
consists of three flip-flops (MOD A/B F/F, MOD SEL F/F,
and OH 0 F/F)
that are set and reset by CPU logic to
provide controls for integral modem operation.

5-9

IPART-;-C;:OGld r;:R:;-; ~E~O~N~TI;;:O:;; - -

INIT

"'" - '"

RD COMM CTRL L

• 6

I I

II
I

CSLO H}
CSLl H

II
II
II
II

(f)

:::;

(f)
(f)

«
f«

0::

0
0

~~I

--'
::::l

ANL TEST H

OH 0 L
OH M H
SW HK H

MOD
CTRL
RD
REG

TEST IND H
CCT H
MOD A/B L
MODE SEL H
DIAL TONE DET H

•

MOD CTKL
WR REG

WR MOD CTR L L
_ _ RD COM M CTRL

I..-_ _-L---IJI\.,
LDAl LDA2

ORO L

TO/
FROM
J5

RD MOD CTRL L

ROAD, RDA5, RDA6

...r WLB L

WR COMM CTRL L

TI I

DATA AVAIL L

RDL TEST H

I I
./

DOM/EUR L'
~

II
II
-

MOD DATA/TALK L
MOD 9/10 H

COMM
CTRL
REG

131\r RD~Q
~ lOT

{»+

ROAD - RDA':;-

:::;

---,

I I'"

COMM/MOD - - RD MOD CTRL L

DECODE

- - WR COMM CTRL

r:i

- - WR MOD CTRL L

MODEM L - - ' _ L -_ _---'

L ____ -.J L ____ ~O~R~T~R~Y~I~E~
MA-017Q-84

Figure 5-7

Communication/Modem
Block Diagram

5-10

(Comm/Modem) Control

•

Modem Control Read Register (MOD CTRL RD REG) -- enables
CPU logic to verify controls written to MOD CTRL WR REG,
and provides integral modem status information.

•

Communication/Modem Decode
(COMM/MOD DECODE) -- enables
CPU logic to access comm/modem control components by
decoding ~ead and write controls.

Figure 5-7 also shows three inverter devices
(MOD DATA/TALK
INVERTER, MOD DOM/EUR INVERTER, and DATA AVAILABLE GATE) used to
invert control outputs from the COMM CTRL REG before sending those
controls to the integral modem (via J5).
The DOM/EUR
implemented
option.
Later in this
Figure 5-7.

NOTE
L signal is not currently
at
the
integral modem

chapter, Table 5-4 describes the signals shown in

5.2.2.2 Comm/Modem Control Addresses -- The CPU logic accesses
various comm/modem control registers to program control, or read
status. The CPU logic does this by addressing a specific register
(LDAI H -- LDA2 H), for read (ORO L) or write (WLB L) operations,
while the COMM/MOD DECODE is enabled (MODEM L).
Table 5-2 identifies the registers that can be addressed by
address and read/write operation. (Appendix 0 provides complete
descriptions of the register bit values.)
Table 5-3 shows how MOD SEL L and MOD A/B H signals combine with a
speed select signal from the DUART (MOD SPD SEL L) to define the
protocol emulated by the integral modem, while in full-duplex,
asynchronous mode.

Table 5-2

Comm/Modem Control Addresses

Address

RD/WE

177004

Comm control

177004

Comm control

177006

Modem control read

177006

Modem control write (MOD SEL F/F, MOD A/B
F/F, OH-D F/F)

5-11

Table 5-3

Comm/Modem Control Definition of Integral Modem
Option Protocol

Protocol

MOD SEL L

MOD SPD
SEL L

MOD A/B H

Bell 212A, 300 BPS

Don't care

Low

High

Bell 212A, 1200 BPS

Don't care

High

Bell 103, Originate,
300 BPS

Low

Bell 103, Answer,
300 BPS

High

Low

5.2.3

Communication Multiplexer (Comm Mux)

The comm mux directs the information flow between the 2681 DUART
and one of the host interfaces: integral modem (via J5), EIA host
interface, or 20 rnA interface. CSL0 H -- CSLl H inputs define
which interface is enabled, with the value of CSL0 H -- CSLl H
determined by CPU logic programming the comm/modem control COMM
CTRL REG.
Figure 5-8 shows the following breakdown of the comm mux.
•

Comm Output Mux -- converts DUART data and ready signals
to data and ready signals to the selected interface (only
the data signal is passed on to the 20 rnA interface) •

•

Comm Input Mux -- converts data and ready signals from
the selected interface into data and ready outputs to the
DUART
(only a data signal is input from the 20 rnA
interface, with HOST DSR L developed from PULL UP).

Later in this
Figure 5-8.
5.2.4

chapter, Table 5-4 describes the signals shown in

Printer Interface (I/F)

The printer interface buffers communication between the terminal
and any auxiliary device connected to the printer port.
Figure 5-9 shows the following breakdown of the printer interface.
•

Line Buffers
provide isolation between terminal and
printer port communication lines.

5-12

HOST TxD L

EIA TxD L
EIA DTR L
COMM
OUTPUT
MUX

FROM
DUART

20m A TxD L

~~ HOST
ifF
TO
20mA I/F

MOD2 TxD L
TO

MOD2 DTR L

HOST DTR L

FROM
{
COMM/MODEM
CONTROL

}

CSLO H
CSLl H

HOST REC L
{
FROM
EIA HOST
EIA DSR L

HOST RxD

ifF
20m A RxD L

FROM
20mA I/F
FROM {

+5 V

MOD2

DSR L

MOD2

RxD L

COMM
INPUT
MUX

PULL UP H

TO
DUART

HOST DSR

MA-0147-84

Figure 5-8

Comm Mux Block Diagram

PRTR DTR L
TxD B
TO/FROM [
DUART

LINE
BUFFERS

RxD B
PRTR

5
I--

DSR L

r-3
r--

r±

CD/108.2/S1.2
BA/103/D1
BB/104/D2
CC1107/M1
AB/102/E2
AA/101/E1

-....:.....

NOTE
J2 PIN 1 IS NOT CONNECTED ON
LOGIC BOARD; J2 PINS 4, 7, AND
9 ARE NOT USED.
MA-0161-84

Figure 5-9

•

Printer Interface (I/F)
Block Diagram

J2
is a nine-pin EIA RS232C/RS423 connector used to
connect the terminal to a local auxiliary device.

La t e r in t his
Figure 5-9.

chapter, Table 5-4 describes the signals shown in

5-13

5.2.5

EIA Host Interface (I/F)

The EIA host interface buffers communication between the terminal
and a host (or modem) connected to the EIA host port.
Figure 5-10
interface.

shows

the

following

breakdown

the

EIA

host

•

Line Buffers
provide isolation between terminal and
EIA host port port communication lines.

•

is a
J3
25-pin EIA RS232C/RS423 connector used to
local or remote host (via
connect the terminal to a
modem) •

Later in this
Figure 5-10.
5.2.6

chapter, Table 5-4 describes the signals shown in

20 rnA Interface (I/F)

The 20 rnA interface buffers communication between the terminal and
a local host connected to the 20 rnA port.
Figure 5-11 shows the following breakdown of the 20 rnA interface.
•

Transmit Optoisolator -- provides isolation between the
TTL level transmit data signal
(20 rnA TxD L) at the
terminal, and 20mA level signals (T+/T-) on the 20 rnA
port communication lines.

•

Receive Optoisolator
provides isolation between the
TTL level receive data signal
(20 rnA RxD L) at the
terminal, and 20 rnA level signals (R+/R-) on the 20 rnA
port communication lines.

•

J4 -- is an eight-pin 20 rnA connector used to connect the
terminal to a local host.

•

Loopback Connector
is a troubleshooting
enables looping J4 signals for testing.

Later in this
Figure 5-11.

aid that

chapter, Table 5-4 describes the signals shown in

5-14

M/101/E1

3
6
-2
-

HOST REC L
TO/FROM {
COMM
MUX

EIA DSR L
EIA TxD L
EIA DTR L
MOD 1 CD L
MOD 1 SI L

LINE
BUFFERS

BA/103/D1
CD/108.2/S1.2

CF/1 09/M5

CI/112/M4

"""i2
-

HOST CTS L
TO/FROM{
DUART

BB/1 04/D2
CC/107/M1

CB/106/M2

-4
-23

HOST RTS L
MOD SPD SEL L

CA/105/SE
CH/111/S4

AB/102/E2

NOTE
J3 PIN 1 IS NOT CONNECTED ON
LOGIC BOARD; J3 PINS 9-11, 13-19,
21-22, AND 24-25 ARE NOT USED.
MA-01S2-84

Figure 5-10

EIA Host Interface (IfF)
Block Diagram

LOOPBACK
CONNECTOR

r'20mA TxD L

TRANSMIT
OPTOISOLATOR

TO/FROM
COMM
MUX

-12A

RECEIVE
OPTOISOLATOR

T-

51-----,
2

-12 V
1

20mA RxD L

T+

R+
RGND

81-----'

NOTE
J4 PINS 1 AND 8 PROVIDE OPERATIONAL
VOLTAGE POTENTIALS FOR LOOPBACK TEST;
PINS 4 AND 6 ARE NOT USED AT J4 OR AT
LOOPBACK CONNECTOR.
MA-0146-84

Figure 5-11

20mA Interface (IfF)
Block Diagram

5-15

5.2.7

Integral Modem Option Connector (J5)

The integral modem option connector, J5, is a 30-pin device that
provides connection between the logic board and an installed
integral modem. Figure 5-12 is a pinout for J5.
Later in this
Figure 5-12.

chapter, Table 5-4 describes the signals shown in

J5
+12V

1 30

+5V

MOD MODE SEL H

2 39

MOD2

MOD2 DSR L

3 28

MOD2 CTS L

MOD2 RxD L

4 27

MOD2 DTR L

MOD2 SI L

5 26

TEST IND H

MOD2 TxD L

6 25

RDL TEST H

MOD2 SPD SEL H

7 24

ANL TEST H

GND

8 23

(NOT USED)

DATA AVAIL L

9 22

OH-M H

OH-D L

10 21

SW HK H

MOD 9/10 H

1120

CCT H

MOD PRESENT L

1219

-12V

MOD DATA/TALK L

13 18

(NOT USED)

MOD AlB L

14 17

DIAL TONE DETECT H

(NOT USED)

1516

DOM/EUR L'

CD L

'DOM/EUR L NOT CURRENTL Y
IMPLEMENTED.
MA-Q143-84

Figure 5-12

5-16

Integral Modem
Option Connector
(J5) Pinout

5.3

SIGNAL DESCRIPTIONS

Table 5-4 describes all the signals shown in this chapter. These
descriptions
are
provided
for
reference, and are listed
alphabetically by mnemonic. Numeric mnemonics are listed last.

5.4

SCHEMATIC REFERENCE INFORMATION

Table 5-5 identifies the logic board component coordinate, and
schematic page and coordinate for each system communication logic
component and circuit identifed in this chapter.
NOTE
The reference listing is based on Rev. C
of the schematics (CS54l5495-9-l).

Table 5-4

System Communication Logic Signal Descriptions

Signal
Mnemonic

Signal
Name

Description

AA/191/El

Protective Ground

Not connected at terminal.

AB/192/E2

Signal Ground

Provides common ground.

ANL TEST H

Analog Loop Test
High

Places integral modem in
data loop test.

BA/103/Dl

Oa ta Output

Serial transmit data to
port device.

BB/104/02

Oa ta Input

Serial data input from
port device.

CA/105/SE

Request To Send

Request a path through
external modem for
transfer of data to remote
host.

5-17

Table 5-4

System Communication Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

CB/106/M2

Clear To Send

Indicates external modem
is ready to transmit to
remote host.

CC/107/M1

Da ta Set Ready

Indicates port device is
ready for communication
activity.

CCT H

Coupler Cut Through
High

Indicates integral modem
senses audio path to
telephone line is ready.

CD/108. 2/S1. 2

Data Terminal Ready

Indicates terminal is
ready for communication
activity.

CF/109/M5

Carrier Detect

Indicates external modem
senses good comm line.

CH/111/S4

Speed Select

Indicates receive speed
greater than 600 bps
selected in set-up.

CI/112/M4

Speed Indicator

Directs terminal to use
transmit and receive
speeds of 1200 bps
regardless of set-up
speeds.

CLK2 L

Clock 2 High

3.6864 MHz clock

COMM RD L

Comm Read Low

Enables read activity when
DUART is selected
(HOST/PRTR L active) •

COMM WR L

Comm write Low

Enables write activity
when DUART is selected
(HOST/PRTR L active) .

CSL1 H

Chip Select Line
High

Disables MOD 1 CD L at MOD
CD GATE when integral
modem (or 20 rnA port) is
selected.

Description

5-18

Table 5-4

System Communication Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

CSL0 H
CSLl H

Chip Select Lines
o and 1 High

Defines interface signals
to be passed by comm mux:
integral modem (CSL0 H -CSLl both high), EIA host
(CSL0 H --C SLl H both
low), or 20 rnA (CLS0 H
LOW, CSLI H high) .

DATA AVAIL L

Data Available Low

Requests data path through
integral modem.

DIAL TONE
DETECT H

Dial Tone Detect
High

Indicates integral modem
senses telephone line
ready for dialing.

DOM/EUR L

Domestic/European
Low

Not currently used.

ORO L

Da ta Read Low

Enables read outputs (RD
COMM CTRL L or RD MOD CTRL
L) when COMM/MOD DECODE is
selected (MODEM L active) •

EIA DSR L

EIA Data Set Ready
Low

Indicates external modem
is ready for communication
activity (buffered
CC/l07/Ml) •

EIA DTR L

EIA Data Terminal
Ready Low

Indicates terminal is
ready for communication
activity (buffered
CD/l08.2/S1.2) •

EIA TxD L

EIA Transmit Data
Low

EIA host port serial
transmit data (buffered
BA/1-3/Dl) •

GND

Ground

Operational voltage
potential outputs (also
used as T+ with 20 rnA port
loopback connector.

Description

5-19

Table 5-4

System Communication Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

HOST CTS L

Host Clear To Send
Low

Indicates host (or
external modem) is ready
to receive transmit data
(buffered CB/106/M2).

HOST DSR L

Host Data Set Ready
Low

Indicates host (or modem)
is ready for communication
activity.

HOST DTR L

Host Data Terminal
Ready Low

Indicates terminal is
is ready to transmit or
receive.

HOST INTRl L

Host Interrupt 1 Low

Indicates host receive
data is present.

HOST INTR2 L

Host Interrupt 2 Low

Indicates DUART is ready
for host transmit data.

HOST/PRTR L

Host/Printer Low

Enables DUART for
read/write.

HOST REC L

Host Receive Low

EIA host port serial
receive data (buffered
BB/104/D2) •

HOST RTS L

Host Request To
Send Low

Requests data path
through remote modem
(buffered CA/105/SE).

HOST RxD

Host Receive Data

Host serial data.

HOST TxD L

Host Transmit
Da ta Low

Host serial transmit data.

INIT H

Initialize High

System initialization
signal.

LDAl H
LDA2 H

Latched Data Lines
1 and 2 High

Address input defining
comm/modem control
register to be written to
(WLB L low), or read from
(ORO L low), when COMM/MOD
DECODE is enabled (MODEM L
low) .

Description

5-20

Table 5-4

System Communication Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

LDA2 H--LDA5 H

Latched Data Lines
2 through 5 High

Address input defining
DUART internal register to
be written to (COMM WR L
and HOST/PRTR L both low) ,
or read from (COMM RD L
and HOST/PRTR L both low).

MOD 9/113 H

Modem 9/113 High

Defines integral modem to
use 9-bi t (high), or
l@-bit characters (low).

MOD A/B L

Modem A/B Low

Defines integral modem
emulation of BELL 212A
(high), or BELL l@3/V.21
( low) •

MOD CD L

Modem Carrier
Detect Low

Indicates good comm line
has been detected by
either the integral modem
(MOD 2 CD L low to MOD CD
GATE), or remote modem
(MOD 1 CD L low to MOD CD
GATE) •

MOD1 CD L

Modem 1 Carrier
Detect Low

Indicates external modem
senses a good receive comm
line (buffered CF/1@9/M5).

MOD2 CD L

Modem 2 Carrier
Detect Low

Indicates integral modem
senses a good receive comm
line.

MOD2 CTS L

Modem 2 Clear To
Sent Low

Indicates integral modem
is ready to receive
transmit data (EIA host
interface uses HOST CTS

Description

L) •

MOD DATA/
TALK L

Modem Da ta/Ta 1 k
Low

Defines integral modem
operation switched line
communication as data
(low), or talk (high).

MOD2 DSR L

Modem 2 Da ta Set
Ready Low

Indicates integral
modem is ready for
communication
activity.

5-21

Table 5-4

System Communication Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

MOD2 DTR L

Modem 2 Data
Terminal Ready Low

Indicates terminal is
ready for communication
activity.

MOD2 RxD L

Modem 2 Receive
Da ta Low

Integral modem serial
receive data.

MOD MODE SEL H

Modem Mode Select
High

Selects mode for integral
modem operation as either
originate (low), or answer
(high) •

MOD PRESENT

Modem Present Low

Low whenever integral
modem is installed.

MODI SI L

Modem 1 Speed
Indicator Low

External modem signal
defining receive/transmit
speeds of 1200 bps
regardless of set-up
selection (buffered
CI/112/M4) •

MOD2 SI L

Modem 2 Speed
Indicator Low

Integral modem signal
defining receive/transmit
speeds of 1200 bps
regardless of set-up
selection.

MOD SPD SEL L

Modem Speed Select
Low

Indicates to modem
(integral or external)
that set-up selection for
receive speed is greater
than 600 bps (buffered
CH/111/S4 for EIA host
port) .

MOD2 TxD L

Modem 2 Transmit
Da ta Low

Integral modem serial
transmi t da ta.

MODEM L

Modem Low

Enable input to COMM/MOD
DECODE.

OH D H

Off Hook Drive High

Drive signal for integral
modem off hook relay.

OH M H

Off Hook Modem High

Indicates integral modem
is off hook.

Description

5-22

Table 5-4

System Communication Logic Signal Descriptions (Cant)

Signal
Mnemonic

Signal
Name

PRTR DSR 0 L

Printer Data Set
Ready 0 Low

Indicates printer port
device is ready for
communication activity. If
inactive at power-on,
DUART tests for active
input before transmitting
each character (buffered
CC/107/Ml) .

PRTR DTR L

Printer Data Terminal
Ready Low

Active ready output to
printer port device from
power on (buffered
CD/108.2/S1.2) •

PRTR INTRl L

Printer Interrupt
1 Low

Indicates printer receive
data is present.

PRTR INTR2 L

Printer Interrupt
2 Low

Indicates DUART is ready
for printer transmit data.

PULL UP H

+5 V Pull Up High

Used by comm mux to
develop HOST DST L during
20 rnA port activity.

R+/R--

Receive +/Receive--

20 rnA port serial receive
data.

RD COMM CTRL L

Read Comm Control
Low

Enables COMM CTRL REG to
output control values.

RD MOD CTRL L

Read Modem Control
Low

Enables MOD CTRL RD REG to
output status.

RDA0 H
RDA7 H

Data Bus Lines
o through 7 high

Data transfer lines.

RDL TEST H
Test High

Remote Data Loop Test

Places integral modem in
data loop test of remote
modem.

RxD B

Receive Data B

Printer port serial
receive data (buffered

Description

B B / 1 0 4/0 2) •

SW HK H

Switch Hook High

5-23

Indicates integral modem
status of telephone switch
hook.

Table 5-4

System Communication Logic Signal Descriptions (Cont)

Signal
Mnemonic

Signal
Name

T+/T-

Transmit +/Transmit-

20 rnA port serial transmit
data.

TEST IND H

Test Indicator High

Indicates integral modem
is in test mode.

TIMER INTR L

Timer Interrupt Low

Programmable interrupt.

TxD B

Transmi t Da ta B

Printer serial data
(buffered BA/103/Dl).

Vcc

Vol tage

+5 V operating voltage.

WLB L

write Low Byte Low

Enables write outputs (WR
COMM CTRL L or WR MOD CTRL
L) when COMM/MOD DECODE is
selected (MODEM L active) .

WR COMM CTRL L

write Comm Control
Low

Enables COMM CTRL REG to
input controls.

WR MOD CTRL L

write Modem Control
Low

Enables MOD CTRL WR REG to
input controls.

+5 V

+5 V dc

Operating voltage output.

+12 V

+12 V dc

Operating voltage output.

-12 V

-12 V dc

Operating voltage output
used at integral modem and
20 rnA port loopback
connector to provide R-.

20 rnA RxD L

20 rnA Receive Data
Low

20 rnA port serial receive
data (isolated R+/R-).

20 rnA TxD L

20 rnA Transmit Data
Low

20 rnA port serial transmit
data (isolated T+/T-).

Description

5-24

Table 5-5

System Communication Logic Schematic References

Circuit/
Component
Comm CTRL RD REG
Comm CTRL WR REG
Comm input mux
Comm output mux
COMM/MOD decode
Data available gate
DUART
EIA host I/P buffers
J2
J3
J4
J5
MOD CD gate
MOD CTRL RD REG
MOD CTRL WR REG (MOD A/B P/P)
MOD CTRL WR REG (MOD SEL P/P)
MOD CTRL WR REG (OH D P/P)
MOD data/talk inverter
MOD DOM/EUR inverter
Printer I/P buffers
Receive optoisolator
Transmit optoisolator

Logic Board
Reference
Numbers
E60
E59
E33
E34
e57
E54
E24
E29-30,E37,
E50-Sl,E66

Schematic
Page Coordi na te
7
7
7
7
5
17
8
8

C7
D7
DS
D3
b7
C4
D4
A7-D7

8
8
7
17
9
7
7
S
7
17
17
8
7

C2-D22
A6-D6
Bl-Cl
C3-D3
B3
B7
AS
D2
A6
C4
D3
C2-D2
B2-BS

E48,E66
ES8
E46
E73A
E46
E6l
E47
E32,E36
E17,ES2,R74-80,
D6,C38,QS-6
E17-l8,E6l,
8
C36-37,D3-S,Q3-4

S-2S

C2-C4

CHAPTER 6
VIDEO LOGIC

6.1

GENERAL

The video logic (shaded area in Figure 6-1) generates the outputs
to drive a monochrome (VR20l) or color (VR24l) monitor device.
The video logic contains the circuits that store display data,
process data out as video, and manipulate the stored video data as
directed by the CPU logic.
The CPU logic communicates with the video logic to initialize
operation, define patterns, define modes, define output color
values, and identify new display data.

SYSTEM BOX

LOGIC
BOARD
/

/ / VIDEO
LOGIC"
LOGIC

_ _ ..4. / _ _ _ _ _

SYSTEM
COMMUNICATION

EIA
HOST
PORT

PRINTER
PORT

20 mA
PORT

INTEGRAL

OPTIONAL
HOST
COMMUNICATIONS

MONITOR
(VR201 OR VR241 I

Figure 6-1

VT240-Series Terminal System
Block Diagram
6-1

6.2

MAJOR CIRCUITS/COMPONENTS

Figure 6-2 is a block diagram that identifies the following major
circuits/components that make up the video logic.
Character processor
Character processor memory
Video access
Graphics processor
Timing and control
Mode select
Bit map addressing
Hi/Lo byte select
Bit map write enable
Pattern select
Logic unit
Write data select
Bit map
Parallel-to-serial (p/S) converter
Output map
Digital-to-analog (D/A) converter
6.2.1

Character Processor (CP)

The TIl is the primary system CPU device. The character processor
(CP)
is a secondary CPU used to cut down TIl system overhead when
the TIl processes data for display at the monitor.
Both the CPU and the CP can access graphics processor circuits via
the video access (refer to section 6.2.3), but only one at a time.
The CPU accesses the graphics processor (and related circuits) to
read status, program operating parameters, or provide graphics
image data for display. The CP processes text characters for
display after the CPU defines which characters to be processed.
This frees the CPU for other system tasks.
The CP (Figure 6-3) consists of the following circuits/components.
•

8085A-l Microprocessor
all CP functionality.

Device

•

Handshake F/F -- coordinates CPU communication with the
8085A-2 and is set by WR BUF L going low (true) to tell
the 8085A-2
(via SI and RST 6.5) that the CPU has data
available.
It is reset when the 8085A-2 reads the data
(85RD BUF L goes low, or true), or when 8085 RESET L goes
low (8085 RESET L is used to tell the 8085A-2 that the
CPU wants to read data from the 8085A-2).

•

8085 Write (WR) Buffer -- passes CPU data to the 8085A-2.
Data is clocked into the buffer by handshake F/F begin
set, and output by 85RD BUF L going low (true).

6-2

-- controls and performs

r---~~------------------------~

I
I

I
I
I
I

:::J
"-

TIMING
AND
CONTROLS

\ R/W

PART OF CPU
I LOGIC

I
I

G~;;70~----------.J
I
W

I
I
I
I

ENABLES

CLOCKS
AND
CONTROLS

CONTROL~

~----

I
I
II

HANDSHAKI.NG:>!

«
f«
o
o

o
>

I
I
I
I
I
I
I
I

IVIDEO
OUTPUTS

L _______________ ~ __________ ___.: _____ ..J
MA-0362-B4

Figure 6-2

Video Logic Block Diagram

TOI
FROM
CPU

FROM
{85WR BUF L
VIDEO
1/0
85 RD BUF L
DECODE
RD BUF L

~~8M

W_R_B_U_F_L+-_,
{
RSRT6.5
Sl

TOI
FROM
CPU

{

}

TO
VIDEO
ACCESS

T11

A15

FROM
TIMING
CONTROL

r--------~~.

TO
ROM

+
RAM

85AD8 H-85AD 14 H
GVS H
FROM
{
GRAPHICS
PROCESSOR

GBLK H

RD L

(RST 5.5)

101M

85 lORD L
85 10WR L

TO
VIDEO
ACCESS

IR/W~O~
MA-0363·84

Figure 6-3

Character Processor

(CP)

Block Diagram

•

8085
Read (RD) Buffer -- Passes 8085A-2 to the CPU. Data
is
clocked into the buffer by the transition of the 85WR
BUF
L trail
edge,
and
read out by RD BUF L going low
(true) .

•

Address
Latch
Generates the address used by 8085A-2
(85LA0 H through 85LA7
H)
to access either graphics
processor
I/O devices,
or CP memory, with the address
value clocked into latch by ALE.

•

Read/Write
(R/W)
Control
generates
the read/write
controls used by 8085A-2 to access I/O devices.

•

Clock Buffers
buffer and convert single CK 8 MHz input
into
two
opposingly phased clocks
(Xl and X2) to the
8085A-2.

6-4

8085 RDY L
SERIAL

1/0

INCREMENTER/I-----'
DECREMENTER

RST 6.5 ,.-------,
GVS H
IRST 7.5)
GBLK H
IRST 5.5)

A15

INTERRUPT
CONTROL

85AD8 H-85AD 14

INTERNAL
CONTROLS

-,
I

I
I

RD L

I
~~~~Y______________

I
I

TIMING
AND
CONTROL
INSTRUCTION
DECODE

WR L
101M
ALE
8085
RESET L

MA-0364-84

Figure 6-4

8085A-2 Microprocessor Device Internal
Block Diagram

6.2.1.1 8085A-2 Microprocessor Device Internal Circuits -- Figure
6-4 is a block diagram that identifies the following major 8085A-2
internal circuits.
•

Serial I/O Control -- is used for handshaking between the
8085A-2 and the TIl.

•

Interrupt Control
monitors interrupt signal inputs
(RST 5.5, RST 6.5 and RST 7.5) determine when an
interrupt condition exists, and to force 8085A-2 to
access the relevant interrupt handling instruction code
in CP memory.

•

Register Array -- includes six general purpose register
devices for 8085A-2 functions, as well as a stack pointer
and program counter.

•

Incrementer/Decrementer -- generates the value to be used
for addressing external memory and I/O devices.

6-5

•

ALU
Circuitry
arithmetic functions.

•

Instruction
processed.

•

Instruction Decode
decodes instruction information
contained in the instruction register, and encodes the
instruction requirements in terms of 8085A-2 machine
cycles.

•

Timing and Control -- generates all internal and external
controls and timing signals.

•

Data/Address Buffer
is bidirectional buffer device
used to input or output data, or to output the least
significant eight bits of a memory or I/O device address.

•

Address Buffer
outputs the most significant eight bits
of a memory or I/O device address.

responsible
stores

for

all

8085A-2

the instructions to be

Later in this chapter, Table 6-6 describes the signals shown in
Figures 6-3 and 6-4.

6.2.1.2 8085A-2 Microprocessor Device Transactions -- The 8085A-2
is involved with the following three types of transactions.
Read/write by CPU logic
Read/write of CP memory
Read/write of graphics processor I/O device circuits
The CPU reads data from the 8085A-2 to determine operating
conditions. The CPU writes data to the 8085A-2 to define the
specific CP memory address of a character to be processed over to
the graphics processor circuits.
The 8085A-2 reads data from the CP memory to either access
instruction codes, acquire character format data, use for scratch
pad operations, or store character data for later processing.
The 8085A-2 reads data from the graphics processor circuits to
obtain status information. The 8085A-2 writes data to the graphics
processor circuits to define new data for display.
8085A-2 communicates with the CPU through handshaking. The CPU
sets the handshaking F/F when the CPU has data to be written to
the 8085A-2. The 8085A-2 resets this F/F when the data has been
accepted. The 8085A-2 generates a ready signal (8085 ROY L low)
when it has data to be read by the CPU.

6-6

8085A-2 communication with the graphics processor circuits is
synchronized to the vertical synchronization (sync) period. The
graphics processor generates two signals (GVS Hand GBLK H). These
signals are used as interrupt inputs to the 8085A-2, one true at
the start of the vertical sync period (GVS H high), and the other
true while the screen is blanked during vertical sync (GBLK H
high).
During the vertical sync period the 8085A-2 can affect the
information to be displayed during the next screen refresh cycle.
Figure 6-5 is a timing diagram for 8085A-2 read/write transactions
that involve either the CP memory,
or graphics processor I/O
circuits. Note that although memory access can occur at any time,
the 8085A-2 is limited to I/O access only during vertical sync
time (defined by GVS Hand GBLK H interrupt inputs). Later in this
chapter Table 6-6 describes the signals identified in these timing
diagrams.

(CLOCK)

101M

ALE
RDL

RDLlWRL

INSTRUCTION FETCH
CYCLE

READIWRITE
CYCLE

NOTES
1.

101M SIGNAL FOR MEMORY READIWRITE TRANSACTIONS;

101M SIGNAL FOR 1/0 DEVICE READIWRITE TRANSACTIONS;

ALE LATCHES THE LOW ORDER BYTE OF ADDRESS INTO THE
ADDRESS LATCH ON THE TRAILING EDGE;

RD L GOES LOW (TRUE) FOR READ TRANSACTIONS, WHILE
WR L GOES LOW (TRUE) FOR WRITE TRANSACTIONS.

Figure 6-5

Character Processor
(8085A-2 Microprocessor Device)
Read/Write Transactions

6-7

6.2.2

Character Processor (CP) Memory

CP memory provides the RAM and ROM memory needed for CP (8085A-2)
functions.
The CP memory (Figure 6-6) consists of the following
components.

•

Character Processor
(CP)
RAM -- is a 2K X 8-bit device
that provides for 8085A-2 scratchpad operations, and
stores data to be transferred to the graphics processor
circuits
during
vertical
synchronization
periods,
(including data for smooth scroll operations).

•

Character Processor (CP) ROM -- has up to 32K X 8 bits of
ROM
that
contains
firmware
that directs 8085A-2
operations as well as character pattern data.
NOTE
CP ROM can consist of a single 32K
device or two ROM devices with up to 32K
storage.
If a
32K ROM is used, it is
installed in the ROM 7 position, and ROM
8 is not used.

FROM
ADDRESS
LATCH

.....

S 85LAOH-85LA7H )
V

c.P.
ROM

FROM
"\
8085A2 \ 85AD8H-85AD13H /

.....

TO/FROM
85A0AD7;> 8085A-2

,.
y

A15r

C.P_
MEMORY
DECODE

ROM7 OE L
ROM8 OE L
ROM OE L

FROM
8085A2

85AD14H
IO/M

FROM
ADDRESS
LATCH

FROM
8085A-2

.....

S 85LAOH-85LA7H )
V

S
· ~
85AD8H-85AD lOH /

C_P_
RAM

MA-0366-84

Figure 6-6

Character Processor (CP)
Memory Block Diagram

6-8

•

Character Processor (CP) Memory Decode -- decodes A15 and
85AD14 H inputs into either a ROM (ROM7 OE or ROM8 OE) or
RAM (RAM OE) enable signal, when memory is to be accessed
(IO/M low) .

Table
6-1 identifies the address ranges of the CP memory
components. Later in this chapter, Table 6-6 describes the signals
shown in Figure 6-6.

Table 6-1

Character Processor Memory Addresses

Device
CP
CP
CP
CP

ROM 7
ROM 8
ROM 7
RAM

6.2.3

(16K)
(16K)
(32K)
( 2K)

Hex Address Range

A15

85AD14 H

0000H--3FFFH
4000H--7FFFH
OOOOH--7FFFH
8000H--87FFH

Low
Low
Low
High

Low
High
Low
Low

Video Access

The video access circuit provides shared access of the graphics
processor circuits by the CPU or character processor (CP). The CP
also uses the video access circuit to generate read/write control
signals used to communicate with the CPU (85 RD BUF Land 85 WR
BUF L).
Only one processor can use the video access circuit at given time.
Control over enabling access is the VID ACCESS L signal from the
CPU logic. When VID ACCESS L is low (true), the CPU has access;
when VID ACCESS L is high (false), the CP has access.
The video access
components.

circuit (Figure 6-7) consists of the following

•

Video Address Mux
consists of two mux devices that
select CPU address values
(LDAl H -- LDA8 H, when VID
ACCESS L is low), or CP address values (LDA0 H -- LDA7 H,
when VID ACCESS L is high)
to generate outputs that
define an I/O circuit to be accessed (VA0 H -- VA7H).

•

Video RD/WR Mux -- selects either CPU read/write control
signals
(GRD Land GWLB L, when VID ACCESS L is low), or
CP control signals
(85 lORD Land 85 IOWR L, when VID
ACCESS L is high) to generate video read/write control
signals (VIa RD L and VIa WR L).

•

Video I/O Decoders
decode address (VA4 H -- VA7 H)
into specific read/write access signals for I/O circuits.

6-9

FR OM
~
CP U . ~ LDA 1H-LDA8H/

FR OM(..
CP U

....

VIDEO
ADDRESS I
MUX

VAOH-VA~ VIDEO 1/0

DEVICES

r-----,85

LAOH-LA7H)

VIO

GRD L
FROM{ GWLB L
CPU
8510RD L
FROMf
8510WR L
CPU

VIDEO
RD/WR
MUX

't;

VIO

~.!:-

ri""""V"

iWRGDCL

'WR VOM L

I WR CHAR BUFF L
WR RATWWLT L

IWR MASK L

:WR VPAT L

TO
VIDEO 1/0
DEVICES

I WR LU L

WR REGO L
WR REG1 L

I
I
I

TO
CP

R D G DC L

tt:
I V

}

RD VDM L
RD INIT CBADDR L

RD BUF L

85WRBUF L

WR HB SCROLL D.A.L
WR LB SCROLL D.A.L

VIDEO

~~~~~.J

1<:
TOIFRO M
CPU

RDAO H-RDA7H

VID
ACCESS L

85 RD
FRO M
VIDE 0110 BUF L
DEC ODERS

CPU
VIDEO
DATA
BUFFER

~ VDBO H-VDB7H I\. TOIFROM
VIDEO 1/0
"f

DEVICES

~
ATy

TOIFR
OM
CP

-r;

....

85 ADO H-85 AD7H

CP
1/) VIDEO 0-DATA
BUFFER

MA-0367-84

Figure 6-7

Video Access Block Diagram

6-10

•

CPU Video Data Buffer -- is a bidirectional buffer device
enabled by VID ACCESS L low for data transfer. The
condition of GRD L defines the transfer direction (from
VDB 0 H -- VDB 7 H to RDA 0 H -- RDA 7 H, when GRD L is
low) •

•

CP Video Data Buffer -- is a bidirectional buffer device
enabled by CP gate when the CPU is not accessing graphics
processor circuits (VID ACCESS L is high), and the CP is
not reading the 85 RD data buffer (85 RD BUF L is high) •
The direction of data transfer is determined by 85 lORD L
(from VDB 0 H -- VDB 7 H to 85 AD0 H -- 85 AD7 H, when 85
lORD L is low, or true).

Table 6-2 identifies the CPU and CP addresses used to generate the
various I/O read/write enable signals. Later in this chapter,
Table 6-6 describes the signals shown in Figure 6-7.

Table 6-2

Video Access Circuit I/O Addresses

CPU Address
Signal

CP Address
Octal

Hex

Destination Device

RD GDC L
WR GDC L
RD VOM L
WR VOM L
85 RD BUF L

173000/173002
174000/174002
173040--173076
174040--174076
(Not accessed)

00/01
00/01
10-1F
10-1F
20

GDC
GDC
Video output map
Video output map
85 RD data buffer, CP
gate, handshake F/F
85 WR data buffer
Character buffer
Character buffer
Pattern multiplier
Write mask register
Vector pattern register
Logic unit register
Register 0
Register 1
Scroll address
Scroll address

(Not accessed)
85 WR BUF L
173140
RD INIT CB ADDR L
174140
WR CHAR BUFF L
174400
WR PAT MULT L
174440
WR MASK L
WR VPAT L
174500
174540
WR LU L
174600
WR REG0 L
174640
WR REGl L
174700
WR HB Scroll DA L
WR LB Scroll DA L
174740

6-11

20
30
30
80
90
A0
B0
C0
D0
E0
F0

6.2.4

Graphics Processor

The graphics processor is a PD7220 Graphics Display Controller
(GDC). The GDC is a microprocessor device that performs the
following tasks.
•

Generates the basic video timing, including blanking and
sync signals

•

Directs modification of bit
drawing and data move activity

map

memory values during

Figure 6-8 identifies the signals involved in GDC operation, as
used in the VT240. Later in this chapter, Table 6-6 describes the
signals shown in Figure 6-8.
6.2.4.1 PD7220
Graphics
Display
Controller
(GDC)
Internal
Circuits -- Figure 6-9 is a block diagram that shows the following
major GDC internal circuits, as used in the VT240.

•

System Interface
(I/F)
-- communicates with either the
CPU or CP via video access circuit to transfer data or
status to the requesting device, or receive data or
commands from the microprocessor device.

•

FIFO Buffer
is a 16-byte device that stores command
information
(communication between the system IIF and
FIFO is on a separate bus from the PD7220 internal bus).

•

Command Processor -- accesses and decodes commands stored
in the fifo, distributing parameter information to the
various internal circuits.

•

Internal Bus Interface -- buffers communication between
the system IIF and other internal circuits, and between
the FIFO and the command processor.

•

Parameter RAM -- is l6-byte RAM used to store parameters
to
be
used
repetitively during display and draw
processes.

•

Video ' Sync Generator -- generates raster timing signals,
with timing based on clock input.

•

Memory Timing Generator -- generates control signals for
read-modify-write (RMW) bit map memory cycles.

•

Drawing
Processor
calculates the addresses and
positions of pixels for various graphic images to be
drawn from a starting point and appropriate drawing
parameters.

6-12

FROM
TIMING
AND
CONTROL

}

TO
CP

}

TO
TIMING
AND
CONTROL

G BLK H
GVS H
GDBEN L
PD7220
GDC

G HS H
GRAS L

RD GDC L
WR GDC L
FROM
VIDED
ACCESS

VDBO H- VDB7 H )

TO
BIT MAP
ADDRESSING

A16

VAO H

GADO H-GAD 15 H

'"
"

TO/FROM
I/O AND MUX
DEVICES

MA-0368-84

Figure 6-8

Graphics Processor Block Diagram

RDGDC L
WRGDC L
VAO H

CK 2MZ L
GND
+5V

SYSTEM
I/F

GBLK H
VIDEO
GHS H
SYNC
G ENE R A TO R f--=Gc.:V-=S..:.H'--_ _ _+

FIFO
BUFFER

MEMORY
TIMING
GENERATOR

GRAS L
GDBEN L

DRAWING
PROCESSOR

A16
COMMAND
PROCESSOR

PARAMETER
RAM

MA-0369-84

Figure 6-9

PD7220 GDC Block Diagram

6-13

•

Display Memory Controller -- multiplexes the address and
data information in and out of bit map memory, and
modifies, as necessary, the bit map contents during the
read-modify-write (RMW) cycles.

Later in this
Figure 6-9.

chapter, Table 6-6 describes the signals shown in

6.2.4.2 PD7220 Graphics Display Controller (GDC) Addresses -- The
GDC can be accessed, through the video access circuit, by either
the CPU or the CP for read and write transactions at either of the
following two addresses.
•

173000
for a write of commands to GDC FIFO (WR GDC L
and VA0 H, both low), or a read of data from FIFO (RD GDC
L low and VA0 H low).

•

173002
for a write of parameter data to GDC FIFO (WR
GDC L low and VA0 H high), or a read of status data from
GDC status register (RD GDC L low and VA0 H high) •

All write operations are to the GDC FIFO with the VA0 H signal
defining the data as either commands
(VA0 H low, for address
173000), or parameters (VA0 H high, for address 173002). Commands
define a specific operation, type of parameter information to
follow, or type of data to be read from the GDC by the CPU or CP.
Table
GDC.

6-3 is a summary of the commands that can be written to the
NOTE
Appendix
D
provides
a
complete
description of the bit values for the
GDC status register. The manual does not
give any further description of any
other GDC register device.

6-14

Table 6-3

PD722~

Command

GDC Commands Summary
Bi t Values
7 654 3 2 1

Description
~

Video Control
RESET

13 13 13 13

Resets GDC to idle state;
Reset command can be followed
by up to eight parameter
bytes defining mode of
operation, active display
words per line, horizontal
and vertical sync widths,
horizontal and vertical front
and back porch widths, and
active display lines per
video field.

VSYNC

13 13 13 13 1 1 1 1

Generate and output vertical
sync.

CCHAR

13 1 13 13 1 13 1 1

Cursor and character
characteristics command
followed by three parameter
bytes: parameter bytes define
cursor on or off, lines per
character row, cursor blink
rate, blinking or steady
cursor, cursor top and bottom
line numbers in the row.

START

13 13 13 13 1 13 1 1

Start display scanning.

STOP

13 13 13 13 1 1 13 13

Blank display.

CURS

13 1 13 13 1 13 13 1

Cursor position command
followed by three parameter
bytes: parameter bytes define
the high and low byte of
display address for both
graphic and character
operations, and in the case
of graphic image cursor, an
additional two bits of
display address, and the dot
address within the the
defined address word.

Display Control

6-15

Table 6-3

PD7220 GDC Commands Summary (Cont)

Command

Bit Values

Description

7 654 3 2 1 0
PRAM

o1 1 1 x x x x

Defines a parameter RAM load
command, with the starting
address for loading into the
RAM. From 1 to 16 parameter
bytes can follow, each
defining specific operational
parameters.

PITCH

o1 0 0 0 1 1 1

Pitch specification command
followed by a single
parameter byte defining the
the pitch as a number of word
addresses in the horizontal
direction.

WDAT

o0 1 0 0 0 1 0

write data into display
memory, with data transfer
defined as a word and RMW
cycle logical operation
defined as reset to zero.

MASK

o 1 001 13 1 13

Mask register load command
followed by two parameter
bytes defining a mask to
control which bits can be
modified in the bit map
memory during RMW cycles.

FIGS

13 1 13 13 1 1 13 13

Figure drawing parameters
specify command followed by
up to 11 parameter bytes:
parameter bytes define type
of drawing operation (such as
straight line, or arc and
circle), and various drawing
parameters.

FIGD

13 1 1 13 1 1 13 13

Figure draw start c9mmand
loading drawing parameters
from the parameter RAM into
the drawing processor, and
starts drawing at the point
defined by cursor and dot
address values.

Drawing Control

6-16

Table 6-3

PD7229 GDC Commands Summary (Cont)

Command

Bit Values
7 654 3 2 1 9

Description

GCHRD

(3 1 1 (3 1 (3 (3 (3

Graphics character draw and
area filling command
initiates drawing or area
filling based on pattern
stored in parameter RAM,
starting at point defined by
cursor and dot address
values.

RDAT

1 (3 1 (3 (3 (3 (3 (3

CPU/CP read of data from
display memory command
defining data read cycle to
be a word, with first low
then high bytes read.

CURD

1 1 1 (3 (3 (3 (3 (3

CPU/CP read of cursor
position, with position of
word and dot addresses
supplied to CPU/CP in five
bytes.

DMAR

1 (3 1 (3 (3 1 (3 (3

CPU/CP DMA read request
command defining transfer as
a word, with low then high
byte.

DMAW

9 (3 1 (3 (3 1 (3 (3

CPU/CP DMA write request
command defining transfer as
a word, with low then high
byte, and defining RMW cycle
for defined word as replace
with pattern supplied by the
word.

Data Read

DMA Control

6-17

6.2.4.3 PD722~ Graphics Display Controller (GDC) Transactions
The GDC is involved in the following three basic transactions.
•

Communication with either the CPU or CP to transfer
command or display data to the GDC, or to transfer status
or FIFO read back data to the CPU or CP

•

Managing display data stored in bit map memory

•

Providing basic control for display synchronization

Figures 6-l~ through 6-15 are timing diagrams for various GDC
operations. Later in this chapter, Table 6-6 describes the signals
shown in these diagrams.

VAOH
WRGDCL

VDBOH-VDB7H

~~~~~~~~t~j~~~~~~~~.

~I'----------TWCY----------~

Figure

SYMBOL

PARAMETER

MIN.

TAW

ADDRESS SETUP TO WR

a
a

MAX. UNITS
NS

TWA

ADDRESS HOLD FROM WR

TWW

WR PULSE WIDTH

100

TOW

OAT A SETUP TO WR

TWO

DATA HOLD FROM WR

TWCY

WR PULSE CYCLE

6-1~

NS
4-TCLK

PD722~ GDC Timing Diagram:
CPU/CP Write Transaction

6-18

VAOH~~~~~
~~

}-T_R_~~______________~

RD GDC L

VDBOH-VDB7H~~~~~~1<~~~~~~~~~~~~------t----(HIGH IMPEDANCE)
(HIGH IMPEDANCE)
~------------TRCY------------~

PARAMETER

SYMBOL

MIN.

MAX.

UNITS

TAR

ADDRESS SETUP TO RD

TRA

ADDRESS HOLD FROM RD

TRRI

P DPULSE WIDTH

TRDI

DATA DELAY FROM RD

TDG

DATA FLOATING FROM RD

TRCY

RD PULSE CYCLE

TRDI+20

140

120

100

4.TCLK

TCLK

MA-0371-84

PD7220 GDC Timing Diagram:
CPU/CP Read Transaction

Figure 6-11

2 X CK 2MZ L

--+~,==:=}~---~---<

GADO H-GAD 14 H
GAD15 H. A16

GRAS L

TDD

GHSH
GBLK H
GVS H

SYMBOL

)(
~
_______J_ ....
________A -

PARAMETER

MIN.

MAX.

UNITS

130

TAD

ADORESS/DATA DELAY FROM: 2 X CCLK t

TOFF

ADDRESS/DATA FLOATING FROM: 2 X CCLK t

130

TRR

RAStDELAY FROM 2 X CCLK t

110

TRF

RAStDELAYFROM2XCCLK t

TDD

VIDEO SIGNAL DELAY FROM 2 X CCLK

120

MA-0372-84

Figure 6-12

PD7220 GDC Timing Diagram:
Display Timing

6-19

2XCK2MZ L

JlSL.rUl..JL ____ ~ ____ Jl.Jl.r _____ IlJL _ --IL

GBLK L

_________-_-_-_-~

----l

___ r-

GHS H

GADOHGAD14H
LCOA

===x

x= : : =:J<

x::= ====x

>C ~ =: : : : x=:::: ~ =t

1><=

I
AI HORIZONTAL

'"
I

IV
(Sl

r--~-1 H--~~
-v-v-v-v- ___ ~
--~--==------~--GAO," GAO''" ~ - - _
_ __ ~ ~ _ _ _ _ _ _ _ _
_ _ _ -=x=
LCOA

(ROWI

G BLK L
GVS L

______

=:x:

----J(

=xl

*--

=:X
I

,-I

- - -

---

----

x=:=:::::::x

~--

./\...- __________ _
V-

-X

=::J<

__ _

__
----=x=::
__ _
--l

-----

---

--l

BI VERTICAL
MA·0373·84

Figure 6-13

PD7220 GDC Timing Diagram: Video Sync Signals

DBENL ________________________________,
62NS

-I

CK2MZ

:-1

I I I

GRASL-----.l1

GAD15-0H---~.1im

I I I

\~~----------------------------------~
ADDRESS OUT D'-----------"""""

GDBENL-----------------~~~~~_ _ _ _ _~

RMWH--------------------------------~

ENDH------~!l~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

RASL-----~r--l~---------------------------------------------------RAHH----~

LAS L
(A15) EPSH -----~
DAD3

(A14) EBSH/DAD3 --------------~
(DATA OUT

Figure 6-14

---------0--0-0--0----------------------------

PD7220 GDC Timing Diagram: 2-P1ane Write Transaction

6-21

62NS

CK2MZ L

-1 r-

RAS H
DBEN L

END H
SOURCE ADDR
FROM GDC

AD15-0H
RMW

(SCROLL COUNTER

RAS L

RAH H
CAS L

(DATA OUT)

(DATA IN)

EPS H

EBS H
MA-0375-84

Figure 6-15

6.2.5

PD7220 GDC Timing Diagram: Video DMA write
Transaction

Timing and Control Circuits

The timing and control
following circuits.

circuits

Clock generator
ROM address counter
Timing signal generator
BLANK generator
BEN and STOP gates
Read-modify-write (RMW) generator

6-22

(Figure

6-16) consist of the

CLOCK
GEN.

CLOCKS

,----------,
I
I
ROM
ADDRESS
COUNTER

)

ENABLES:>!I

TIMING
SIGNAL
GEN

BEW

c:JLANK
GEN

AND
STOP

II >
00,,"0'"

RMW
GEN

G~~

L___C~R~I~T-=--

I
~

MA-0376-84

Figure 6-16

Timing and Control
Block Diagram Circuits

, - - - - - CK16MZL
L10
CK16MZH

C47

l'
CK8MZL

Y1
(16.097280 MHZ)

DIVIDER
CK2MZL

Figure 6-17

Clock Generator Block Diagram

6.2.5.1 Clock Generator -- The clock generator provides the basic
timing signals used by various video logic components. The clock
generator (Figure 6-17) consists of the following components.
•

Yl
is an oscillator
(16.097280 MHz).

•

L10, C47 -- is a filter for 16 MHz clock outputs.

•

Divider -- generates 8 MHz (CK 8 MZ L) and 2 MHz
L) clocks from buffered input from Yl.

6-23

that

provides

basic

clock

(CK 2 MZ

6.2.5.2 BEN and STOP Gates
The bus enable (BEN) and stop
(STOP) signal gates (Figure 6-lB) consist of two inverters and two
gates.
•

The inverters buffer a bus enable input from the GOC (GO
BEN L) into bus enable outputs to the RMW generator.

•

The gates generate STOP Land OBEN L control outputs
based on timing signal generator inputs and buffered GO
BEN L signal.

Later
in this
Figure 6-lB.

chapter, Table 6-6 describes the signals shown in

6.2.5.3 ROM Address Counter -- The ROM address counter circuit
provides a
cyclical address output used by ROM devices in the
timing signal generator and parallel-to-serial converter circuits.
The ROM address counter (Figure 6-19) consists of the following
circuits/components.
•

Clear F/F
clears the count of the ROM address clock
whenever STOP L input from STOP gate is true (low).

•

ROM Address Clock Counter
generates address value
output (A0 H -- A3 H) from CK 16MZ H input.

Later in this
Figure 6-19.

chapter, Table 6-6 describes the signals shown in

6.2.5.4 Timing Signal Generator -- The timing signal generator
provides control for video logic activity by generating control
outputs based on cyclically addressed ROM based firmware. The
timing signal generator
(Figure 6-20) consists of the following
components.

•

SCROLL/STOP F/F -- determines high order bit of address
to the timing signal ROM (TM0) with a low address bit
(SCROLL EN L low) or stop (STOP L low)
during scroll
conditions.

•

TM0 -- is a 32 X B-bit ROM device that contains firmware
cyclically addressed by inputs from ROM address counter
(A0 H -- A3 H);

•

Timing Signal
16MZ H input.

Later in this
Figure 6-20.

Buffer -- buffers TM0 outputs based on CK

chapter, Table 6-6 describes the signals shown in

6-24

FROM GD BEN
GDC

~~~~G

TO ROM
ADDRESS
COUNTER

STOP L
{

END H

SIGNAL
GENERATOR

L-____
DBEN L

--a

}
TO TIMING
SIGNAL
GENERATOR

,....=.D=-BI:.:.N:...:L=---_ _

TO
BIT
MAP
MA-0378-84

Figure 6-18

BEN and STOP Gates Block Diagram

+5V
FROM
CLOCK

ROM
ADDRESS
CLOCK

CK 2MZ L

FROM
GDC

GRAS L

FROM
STOP
GATE

STOP L

TO
TIMING
SIGNAL
GEN
TO
P-S
CONVERSION

CK 16MZ H

FROM
CLOCK
MA-0379-84

Figure 6-19

ROM Address Counter Block Diagram

+5V

FROM
MODE
SELECT

RAS H

SCROLL!
STOP
F/F

FROM
CLOCK
FROM (
BEN
AND
STOP
GATES

END H

SCROLL EN L

CAS H

TMO
DBEN L

TIMING
SIGNAL
BUFFER

GAS H
DBIN L
LLB L

TO
VARIOUS
CIRCUITS

SYNCH H

STOP L

SEL LB

FROM
ROM
ADDRESS L.._ _ _......
COUNTER
MA-0380-84

Figure 6-20

Timing Signal Generator Block Diagram

6-25

6.2.5.5 Read-Modify-Write
(RMW)
Generator -- The RMW generator
generates RMW control signals used during RMW cycles that affect
the bit map. The RMW generator
(Figure 6-21) consists of the
following components.
•

RMW F/F
generates RMW outputs based on the condition
of bus enable inputs (GO BEN Hand BGD BEN L which are
always the inverse value of each other) on the trailing
edge of END H input, or based on jamset input from ERASE
F/F.

•

ERASE F/F
is clocked by the trailing edge of RAS H
input, with a low output (when ERASE L input is true)
forcing RMW F/F to output true RMW control signals.

Later in this
Figure 6-21.

chapter, Table 6-6 describes the signals shown in

FROM
TIMING
SIGNAL
GENERATOR
FROM
MODE
SELECT

RAS H

ERASE L
ERASE
F/F
+5V

RMW H

FROM
TIMING
SIGNAL
GENERATOR
FROM
BEN
GATES

RMW
F/F

END H

RMW L

}

TO
VARIOUS
CIRCUITS

GDBENH
(

BGD BEN L
MA-0381-84

Figure 6-21

Read-Modify-Write (RMW)
Generator Block Diagram

6-26

6.2.5.6 BLANK Generator -- The BLANK generator outputs blanking
control signals which are based on blank input from GDC (G BLK H)
and synchronized by timing signal generator inputs. The BLANK
generator (Figure 6-22) consists of the following components.
•

S BLANK F/F -- generates S Blank L from inverted GBLK H
input, with output synchronized to RAH H input.

•

BLANK F/F -- generates BLANK L and BLANK H from inverted
GBLK H input, with outputs synchronized to SYNCH H
input.

•

BLANK Generator
consists of BLANK I
F/F, which
output from BLANK L input, and D
generates BLANK I
L
BLANK buffer, which generates D BLANK L output to D/A
(Both are clocked by CK l6MZ H, with three clocks needed
to reflect any change in BLANK L input at D BLANK L
output. )

Later in this
Figure 6-22.

FROM
Gac

chapter, Table 6-6 describes the signals shown in

G BLK H

SBLANK L
SBLANK
F/F

FROM
TIMING
(RAH H
SIGNAL
SYNCH H
GENERATOR

TO
VARIOUS
CI RCUITS
BLANK L
BLANK
F/F

FROM
CLOCK

BLANK H
CK 16MZ L

BLANKI
F/F
FROM
CLOCK

BLANKI L

~~=-,-,--,=-_TO

alA

CK 16MZ H

aB~~~R _ _ _ _

-.J

* SHARES SAME PHYSICAL COMPONENT (2918)
AS P-S INPUT BUFFER IN OUTPUT MAP
MA-0382-84

Figure 6-22

BLANK Generator Block Diagram

6-27

6.2.6

Mode Select

The mode select circuit
(Figure 6-23) consists of two register
devices, register zero (REG 0) and register one (REG 1).
The mode select registers are programmed by the CPU or CPo The
register values are used in conjunction with values programmed
into the following video logic devices to define the video logic
write mode.
•

GDC (refer to section 6.2.4)

•

Logic unit register
section 6.2.11)

•

Write mask latch in bit map write enable circuit (refer
to section 6.2.9)

•

Scroll address counter in
(refer to section 6.2.7.2)

•

Vector pattern register in pattern select circuit (refer
to section 6.2.10)

logic

unit

bit

circuit (refer to

map addressing circuit

Depending upon how these various components are programmed, the
video logic can operate in one of the following six different
write modes.
•

Mode 0 (Read Back Mode) -- defines a read back of bit map
for hardcopy and diagnostic purposes.

SCROLL EN H

....

SCROLL EN L

.~ SEL SO H

REG 1

VDBl H-VDB3 H )
V

DIR H

WR REGl L
-~

WR REGO L

FROM
VIDEO
ACCESS

VOMOH
VOM1H

TO
VARIOUS
VIDEO
LOGIC
CI RCUITS

EN VOM H

)

J
"-

VDBO H-VDB7 H

REG 0

rl>

VEC L
VEC H
SEL EXT LU H
SELGDCH
SELVPATH
ERASE L
MA-0383-84

Figure 6-23

Mode Select Block Diagram

6-28

•

Mode 1
(Text Mode)
patterns one byte at
appropriate values.

•

Mode 2 (Vector Mode)

•

Mode 3
(DMA Scroll Mode) -- defines byte write mode for
scrolling with write mask set to all zeros.

•

Mode 4
(Screen Erase Mode)
entire
displayed
frame to
intensity.

•

Mode 5
(Word/Line Erase Mode) -- defines erasing of a
l6-bit word location to a specifed background intensity
in single GDC write cycle.

defines a write of character
time with write mask set to

-- defines vector writing

defines erasing of the
specified backgraound

Appendix
D and Table 6-6
(later in this chapter)
provide
descriptions of the bit values for the mode select registers.
Appendix E provides descriptions of the bit values of for the
various components used for each of the six write modes.
6.2.7

Bit Map Addressing Circuit

The bit map addressing circuit generates row and column addresses
for accessing the bit map. The bit map addressing circuit (Figure
6-24) consists of the following circuits.
Plane and byte select
Address select
Row/column mux

FROM
VARIOUS
CIRCUITS '-----'-~

FROM

PLANE
AND
BYTE
SELECT

GDC

FROM
VIDEO
ACCESS

ROW/
COLUMN
MUX

GADa H-GAD15 H
A16

----'--'--'-"------.1

MADa H-MAD7 H

TO
BIT
MAP

ADDRESS
SELECT
I------~

VDBa H-VDB7 H
FROM
TIMING
AND
CONTROL

RAH H

FROM
CONTROLS
VARIOUS
CI RCU ITS " - - - - - - - - - - - - '

Figure 6-24

Bit Map Addressing Circuit Block Diagram
6-29

6.2.7.1 Plane and Byte Select
The
circuit has the following two functions.

plane

and byte select

•

Generate plane (EPS Hand EPS L) and byte select (EBS L)
controls used by various video circuits

•

Generate generate plane and byte select values used by
row/column mux in the output of bits three and six of the
high order byte of addressing.

The plane and byte select circuit (Figure 6-25) consists of the
following circuits/components.
•

DAD Generator
ANDs inversion of LAD16 H with VEC L,
and inversion of LB H with VEC H to output true DAD3
signals
(DAD3 H high, DAD3 L low) when either ANDed pair
are both highs.

FROM
RMW L
TIMING
AND
FROM
CONTROL
MODE
SEL GDC H
SEL DAD L
SELECT
DAD!
FROM
LAD
..;;eS~BL::;:.A.::.:Nc:.:K..;;eL_ _ _ _--t DECODE R SEL LAD L
TIMING
AND
CONTROL
FROM
SCROLL EN L
MODE
SELECT

r---=_-+__
EPS H
FROM
{
TIMING
AND
CONTROL

RAS H
CAS H

EPS!
EBS
GEN

rgGIC
UNIT

j-=E"-'PS=--=L'---_ _----'
EBS H

J-=-'-'-'------+I

~:$~H E D {:::.LAc..:Dc.:.:15::...:H-'--_ _ _ _ _ _-----'
ADDRESS
MUX

TO
} BIT MAP
WRITE
ENABLE
-+--l---l.::.:EP..;;eS..:.;Hc..TO P-S
EPS L
EPS H

PLANE
AND
BYTE
MUX

CONVERTER
(PLANE
SELECT) JTO
(BYTE
ROW!
COLUMN
SELECT)
MUX

EBS L

LAD16 H
TO PS
CONVERTER

FROM
{
MODE
SELECT

DAD3 L

FROM LB H
HI!LO
BYTE
SELECT

L _______

MA-0385.-84

Figure 6-25

Plane and Byte Select Block Diagram

6-313

•

EPS/EBS Generator -- consists of two serial F/Fs enabled
by RAS H high
(both reset whenever RAS H is false) to
output true EPS Hand EPS L signals on the trail edge of
the first CAS H input (following RAS H going high), and
true EBS Hand EBS L signals on the trail edge of the
second CAS H input.

•

DAD/LAD Decoder
decodes SEL GDC H input during screen
blank intervals
(S BLANK L input low) when enabled by
SCROLL EN L true (low), with SEL DAD L output decoded for
SEL GDC H low (with decode output ANDed with RMW L to
output SEL DAD L that is tied to RMW L time), and SEL LAD
L decoded for SEL GDC H high.

•

Plane and Byte Mux
selects plane and byte select
values to be used by row/column mux for bits three and
six of the high order byte of addressing.

Later in this
Figure 6-2S.

chapter, Table 6-6 describes the signals shown in

6.2.7.2 Address Select
following two functions.

The

address

select circuit has the

•

Select address values to be output to the row/column mux

•

Generate LAD1S H -- LAD16 H output values based on GDC
input whenever GDC address values are selected for output
to the row/column mux LAD1S H -- LAD16 H values are used
at the plane and byte select circuit to determine plane
and byte select values to be supplied to the row/column
mux.

The address select circuit (Figure 6-26) consists of the following
components.
•

Scroll Address Counter - consists of four counter devices
clocked by RMW L that bare either down (DrR H true) or up
(DrR H false) from a value loaded by either the CPU or CP
(VDB0 H -- VDB7 H, WR LB SCROLL DA L, and WR HB SCROLL DA
L inputs from video access), with the counter value
output to latched address mux.

•

Latched Address Mux
consists of four mux devices
selecting either scroll address counter (SAD0 H -- SAD
l3H) or GDC inputs (GAD0 H-GAD13H, GAD1S H, and A16), RAS
H latch the selected input values into the mux, and
SCROLL EN H,
in conjunction with RMW H, selects which
values are latched (GDC for SCROLL EN H low).

Later in this
Figure 6-26.

chapter, Table 6-6 describes the signals shown in

6-31

{

GAD 15 H

FROM
GDC

\GADOH

GAD1~

WR LB SCROLL DA L

FROM
VIDEO
ACCESS

VDBO H-VDB7 H")

WR HB SCROLL DA

FROM
MODE

{

SELECT
FROM
{
TIMING
AND
CONTROL

DIR H
SCROLL EN H

SCROLL
ADDRESS
COUNTER

LATCHED
ADDRESS
MUX

To
LAD15H }PL ANE
LAD 16 H
A ND
BYTE
SE LECT
TO
I'\.
ROW;
IADDRESV COLUMN
MUX

I'\.
SADO H-SAD13 H

RMW L
RMW H
RAS H

Figure 6-26

Address Select Block Diagram

6.2.7.3 Row/Column Mux
The row/column mux
(Figure 6-27)
consists of the following two mux devices, each selecting inputs
based on value of RAH H.
•

RAH H high (true) -- the mux devices select "B" inputs to
mux for row address values.

•

RAH H low (false) -- The mux devices select "A" inputs
for column address values.

Later in this
Figure 6-27.
6.2.8

chapter, Table 6-6 describes the signals shown in

High/Low (Hi/La) Byte Select

The hi/l a byte select circuit selects either GDC low order byte
GAD7 H) or GDC high order byte data (CAD8 H -data
(GAD0 H
for output to the mask select and write data select
GADlS H)
circuits (GD0 L -- GD7 L), during RMW cycles.
The hi/lo byte select
following components.

circuit

(Figure

6-28)

consists of the

•

is enabled by RMW L low (true) to
Hi/La Byte Mux
select either low byte (select input low) or high byte
(select input high) for output as GD0 L -- GD7 L
inputs
(GD0 L -- GD7 L are all high when RMW L is high) •

•

ANDs SEL GDC H with EPS L, and invert
Mux Select Gate
SEL GDC H with LB H to output select value to the hi/lo
byte mux.
6-32

FROM
D{
PLANE AN
BYTE
SELECT

(PLANE SELECT)

MAD 3 H

(BYTE SELECT)

MAD 6 H

J\.
LAD12H-LAD13H )
V

LAD4H-LAD7H

ROW/
COLUMN
MUX

MAD 5 H
MAD4 H
TO
BIT
MAP

FROM
GDC

....

i LAD8H-LADllH V)
....

LADOH-LAD3H

)

MAD 7 H
ROW/
COLUMN
MUX

MAD 2 H
MAD1H

MADO H

FROM
TIMING
AND
CONTROL

RAH H

i
MA-0387-84

Figure 6-27

Row/Column Mux Block Diagram

GADOH-GAD7H

~~~M { ; - - - _ - - ' "
GAD8H-GAD15H

FROM
TIMING
AND
CONTROL
FROM
BIT MAP

HI/LO
BYTE
MUX

~R~M~W~L~______________~

---,

EPS L

TO
WRITE
DATA
SELECT
TO
BIT MAP
WRITE
ENABLE

MUX
SELECT

I
II

-----~~--'
LB H

r-------------------~~----.BITMAP

ADDRESSING

FROM
ANY
GAD
BUS
DEVICE

MA-0388-84

Figure 6-28

•

Hi/La Byte Select Block Diagram

LB H Generator -- monitors GADS H -- GADl5 H bus lines to
generate high (true) LB H output when anyone of the high
byte GAD signals is an active high (true).

Later in this
Figure 6-2S.

chapter, Table 6-6 describes the signals shown in

6-33

6.2.9

Bit Map write Enable

The bit map write enable circuit generates up to eight write
enable signals for the bit map. This allows writing to the bit map
to involve only a specific bit or bits, no bits, or all bits of a
data byte during any given RMW cycle.
The bit map write enable circuit (Figure 6-29) consists of the
following components.
•

Mask Select Mux -- generates a write enable mask value
based on either CPU/CP inputs (VDB0 H -- VDB7 H, when VEC
H is low), or hi/lo byte select inputs originating at the
GDC (GD0 L -- GD7 L, when VEC H is high) .

•

write Mask Latch -- generates the write enable outputs
during RMW L low, with the write enables based on the
last enabled mask select mux input to the latch.

FROM
VIDEO
ACCESS
FROM
HI/LO

VDBOH-VDB7H

MASK
SELECT 1--_....,

MUX

WRITE
MASK
LATCH

WRITE
ENABLES
TO
BIT MAP

GDOL-GD7L

BYTE
SELECT

FROM
TIMING RMW L
AND
CONTROL

FROM

EPS H

BIT MAP
ADDRESSING

FROM
MODE

[VEC H

SELECT

VEC L

WR MASK L

VIDEO
ACCESS

MASK

L --ENABLE
GATE

I
I
~
MA-0389-84

Figure 6-29

Bit Map write Enable Block Diagram

6-34

•

Mask Enable Gate -- ANDs EPS H true with VEC H true to
enable loading of GD0 L -- GD7 L mask values passed by
the mask select mux. Also ANDs VEC L false and WR MASK L
true to enable loading of VDB0 H -- VDB7 H mask values
passed by the mask select mux.
NOTE
Write mask values from the mux are
actually clocked into the latch by a low
to
high
on the enable input: the
trailing edge of EPS H when VEC inputs
are true and the trailing edge of WR
MASK L when VEC inputs are false.

Later in this
Figure 6-29.
6.2.10

chapter, Table 6-6 describes the signals shown in

Pattern Select

The pattern select circuit stores character and vector patterns
loaded by the CPU or CP and selects between these patterns for
output to the logic unit.
The pattern select logic (Figure 6-30) consists of the following
circuits/components.
•

Character Pattern Address Counter -- counts up from a
zero starting value
(loaded by RD INIT CB ADDR L low)
with incrementing output used as the address value for
character pattern buffer.

•

Counter Clock Gate
enables counting by character
pattern address counter only when the character pattern
bufffer is not being loaded.

•

Character Pattern Buffer
consists of two 32 X 4-bit
RAM devices that provide 32 bytes of character pattern
storage with patterns loaded (WR CHAR BUFF L low) or read
(WR CHAR BUF L high) sequentially.

•

Pattern Multiplier Register -- is programmed by the CPU
(WR PAT MULT L low)
with a multiplication factor (1
through 16) to be used for each vector pattern bit.

•

Pattern Multiplier Counter -- enables the register clock
gate whenever the number of clock inputs defined by the
multiplication factor have been counted.

6-35

FROM
VIDEO

VDBOH-VDB7H

ACCESS~------~~~~~~---'

FROM {

RD INIT CB ADDR L

VIDEO
ACCESS

WR CHAR BUFF L

CHARACTER
PATTERN
BUFFER

8-BIT
PATTERN
TO LOGIC
UNIT

ICOUNTER
CLOCK GATE

FROM
SELVPATH
MODE
SELECT

PATTERN
REGISTER

VDBOH-VDB3H

PATTERN
MU LTI PLI ER
REGISTER

PATTERN
MULTIPLIER
COUNTER

FROM
VIDEO
ACCESS

WR PAT

e°'::=T~

MULT L

MULTIPLEXER
CLOCK & LOAD

~T'::"'" _ - '
MA-0390-84

Figure 6-30

Pattern Select Block Diagram

6-36

•

Multiplier Clock and Load Gates -- enables clocking of
the pattern multiplier counter on RMW L cycles, and
whenever a new pattern is loaded into the pattern
register
(WR VPAT L low). Reloads the pattern multiplier
counter whenever the correct count has been achieved, or
when a new pattern is loaded into the pattern register.

•

Register Clock Gate -- enables RMW L to clock the pattern
register only when the correct multiplication factor
count has been sensed by the pattern multiplier counter.

•

Pattern Register
is an eight-bit recirculating shift
register loaded by the CPU (WR VPAT L low) with vector
pattern
(the pattern is shifted through the register),
and then output to the pattern select mux, one bit at a
time (MSB first).

•

consists of two mux devices
Pattern Select Mux
outputting eight bits of either character (SEL VPAT H
low)
or vector
(SEL VPAT H high) pattern value to the
logic unit.

Later in this
Figure 6-30.
6.2.11

chapter, Table 6-6 describes the signals shown in

Logic Unit

The logic unit converts data input from the bit map into new write
pattern data output to the write data select circuit. This
conversion is based on the pattern (either character or vector)
input from the pattern select circuit, bit map data input from the
bit map, and control values loaded into the logic unit circuit by
the CPU or CPo
The logic unit circuit
circuits/components.

(Figure 6-31) consists of the following

•

Logic Unit Register
is loaded by CPU or CP (WR LU L
low). Control values define write mode (M0 H -- Ml H at
0H for replace, IH for overlay, and 3H for complement) ,
single (SP H high) or two-plane (SP H low) writing, plane
selection in single-plane mode of plane zero (PS H low)
or plane one (PS H high), background intensity values for
each plane
(IB0 Hand IBl H), and foreground intensity
values for each plane (IF0 Hand IFl H).

•

Intensity Select Mux -- outputs background and foreground
intensity values to the logic unit with plane zero values
output when EPS H is low, and plane one values output
when EPS H is high.

6-37

FROM
"PATTERN )ICHARACTER OR VECTOR PATTERV
SELECT

FROM
BIT MAP

)

MDOH-MD7H

LOGIC
UNIT
WPOL-WP7L

TO
WRITE
DATA
SE LECT

M1H

2 VDBOH- VDB7

MO H

IF1 H
LOGIC
UNIT
REGISTER

FROM
VIDEO
ACCESS

IFO H
IB1 H
IBO H

SP H
PS H

WR LU L

IF H

INTENSITY
SELECT
MUX

IB H

~-t-~-l

~I
~
J
GATES

FROM
EPS H
BIT MAP
ADDRESSING

---

MA-0391-84

Figure 6-31

Logic unit Block Diagram

•

Plane Management
(PM)
Gates
are used only during
single-plane writing (SP H high) to provide a low output
to the logic unit when EPS Hand PS H are opposite
values, and high to the logic unit when both signals have
same
value.
Low to high transition indicates that
intensity values for the selected plane are being passed
by the intensity select mux.

•

Logic unit
consists of two four-bit algorithm logic
unit
(ALU)
devices that manipulate inputs from the bit
map
(MD0 H
MD7 H), pattern select, and other logic
unit components into a write pattern (WP0 L -- WP7 L)
output to write data select circuit.

Appendix D provides a description of the logic unit register bit
values.
Later in this chapter, Table 6-6 describes the signal
shown in Figure 6-31.

6-38

FROM
HilLa
BYT~

TO
BIT MAP
FROM
LOG IC
UNIT
FROM
MODE
SE LECT

r-~

___-'

SEL EXT LU H
SEL SD H
-"=:..=:.."'-C----.--_ _--'

FROM
BIT

DMA
BUFFER

MAP

MA-0392-84

Figure 6-32

6.2.12

Write Data Select
Block Diagram

write Data Select

The write data select circuit passes data to the bit map from
either the logic unit (when data is manipulated external to the
GDC) ,
to the hi/lo byte select (when data is manipulated internal
to the GDC) , or to the bit map (during DMA write mode) .
The write data select
following components.

circuit

(Figure

6-32)

consists of the

•

DMA Buffer -- generates data output to the bit map when
DMA is enabled (SEL SD H high) •

•

Write Data Select Mux -- generates data output to the bit
map when DMA is disabled (SEL SD H low), from either the
hi/lo byte select (SEL EXT LU H low) or logic unit (SEL
EXT LU H high) •

Later in this
Figure 6-32.

chapter, Table 6-6 describes the signals shown in

6-39

6.2.13

Bit Map

The bit map provides the memory space for two-plane display. Each
plane is an 800H X 327V pixel memory array, with two 800H X 240
pixel arrays for actual display and the remainder for set-up
display purposes.
The bit map
components.

circuit

(Figure

6-33)

consists

of the following

•

Bit Map Memory -- is eight 64K X I-bit RAM devices that
provide 64K bytes of memory or the two-plane pixel array.

•

Buffer Gates -- is enabled by VEe L high to pass bit map
data outputs to the read back buffer.

FROM

~C~A~S~H________- .

TIMING
[LLB L
AND
~~-------.
CONTROL
DBEN L

TO
GDC

GADO H-GAD15 H

TO
WRITE DATA
SELECT

FROM
MODE

VEC L

SELECT

TO
LOGIC UNIT

TO
P-S CONVERTER
FROM
BIT MAP ~_ _ _---JI"'"
(WRITE ENABLES)
WRITE
ENABLE
FROM
BIT MAP
~MADO H-MAD7
ADDRESSING
FROM
[CASH
TIMING
AND
CONTROL
RAS H

-------,
I

~
H

MDO

MD1

MD2

MD3

~
I

MD4

MD5

MD6

MD7

I
I
I

~~~~~FROM
WRITE
DATA
SELECT

____ -.J

MDIO H-MDI7 H
MA-0393-84

Figure 6-33

Bit Map Block Diagram

6-40

•

Read Back Buffer
is two eight-bit buffers, one for
high byte output to the GDC (GAD8 H -- GAOlS H when DBEN
L and CAS H are both low), and one for low byte output to
the GDC (GAD0 H -- GAD7 H when DBEN Land LLB L are both
low) •

Later in this
Figure 6-33.
6.2.14

chapter, Table 6-6 describes the signals shown in

Paralle1-to-Seria1 (P/S) Converter

The piS converter circuit changes parallel data input from the bit
map into serial data output to the output map.
Four bytes of parallel data are input to the PIS converter
circuit, two bytes for each plane (high byte and low byte). The
parallel data is then converted to four bits of serial data
output, two bits for each plane (high bit and low bit), and output
as a
two-bit value to the output map. Either the high-bit values
for each plane or the low-bit values are passed to the output mux
at one time.
The piS converter circuit (Figure 6-34) consists of the following
circuits/components.
•

Bit Select (BS) Gate -- gates EBS 1 and DAD3 1 input with
Scroll enable inputs to generate a BS H value to the gate
decoder
(BS H low for selecting the low order bit, BS H
high for the high order bit) •

•

Gate Decoder -- is enabled by RMW L low to decode plane
(EPS H)
and bit
(BS H) inputs into single gate enable
output for the selected plane and bit (G0 one for plane
zero low bit, G1 L for plane one low bit, G2 L for plane
zero high bit, and G3 L for plane one high bit) •

•

CT0/CTl
consists
of
two 64-byte ROM devices
sequentially addressed by A0 H through A3 Hand RMW H
inputs to generate mode select value outputs to the PIS
mode
select
buffer. One ROM is for screen blank
conditions
(CTl enabled by BLANK L low) and one is for
nonblank conditions (CT0 enabled by BLANK H low).

•

PIS Mode Select Buffer -- outputs mode select values to
piS converters (four pairs of S0 H -- S1 H signals, pairs
A through 0, with one pair for the four PIS converter
devices) •

6-41

CK16MZ H
BLANK L

P-S
MODE
SELECT
BUFFER

SOA-DH-S1A-DH

FROM
TIMING
AND
CONTROL

P-S
CONVERTERS P1LBH
RMW L

FROM
BIT MAP
ADDRESSING

FROM

P1HBH

H _ _ _ _ _ _ _..
.....;E",-P.::...S'-C
GATE
DECODER

(

MODE
SELECT

GOL-G3L

P-S
OUTPUT
MUX

TO
OUTPUT
} MAP

FROM
TIMING SEL LB L
AND
CONTROL

SCROLL EN L
SCROLL EN H

i~:~~:'''G{_~_:_:_:_L

---t--t

• SHARES SAME PHYSICAL COMPONENT (74S139)
DAD/LAD DECODER IN PHONE AND BYTE SELECT
MA-0394-84

Figure 6-34

Parall~l-to-Serial

(P/S) Converter

Block Diagram

•

piS
Converters
consists
of
four
eight-bit
shift/storage registers, one high byte and one low byte
PIS converter for each plane. Each register is clocked by
CK 64MZ H, gated by gate decoder input, and controlled by
PIS mode select buffer input. Serial output from each is
sent to the PIS output buffer.

•

PIS Output Buffer -- selects either plane zero and one
high bit values
(P0 HB H, and Pl HB H when SEL LB L is
high)
or plane zero and one low bit values (P0 LB Hand
Pl LB H, when SEL LB L is low) for output to the output
map.

Later in this
Figure 6-34.

chapter, Table 6-6 describes the signals shown in

6-42

6.2.15

Output Map

The output map generates color
(blue, green, and red)
and
monochrome values to the O/A or conversion to video output for
either a color (VR24l) or monochrome (VR240) monitor.
The color and monochrome values are based on data programmed into
the output map by the CPU or CP, and are accessed for output to
the O/A by map select (VOM0 H -- VOM1 H signals that originate at
mode select) and bit-plane select (either P0 HB H -- PI HB H or P0
LB H
pI LB H signals that originate at the PIS converter)
values.
The output map memory space is organized into four 4 X 8-bit maps
(map0 through map3).
Each map contains four bytes of O/A output
values, two bits for each color and two bits for monochrome. Map
select inputs define which map is to be selected, while bit plane
inputs define the byte within that map to be output to the O/A.
The output map circuit
circuits/components.

(Figure 6-35) consists of the following

•

Video Output Map (VOM) -- consists of two 16 X 4-bit RAM
devices that provide memory for output map values, one
RAM device for the upper four bits of map0 through map3,
and one for the lower four bits. Memory is written to by
CPU or CP when WR VOM L is low, and VOM output when WR
VOM L is high.

•

VOM Address Select -- enables CPU or CP access when EN
VOM H is low (address mux device passes VA0 H -- VA3 H
inputs), and video logic access when EN VOM H is high
(address mux passes VOM0 H -- VOMI H while the PIS input
buffer passes P0 HB H -- P 1 HB H or P0 LB H
PI LB H).

•

VOM Buffer
buffers VOM data to the O/A and VOM read
back register as four sets of two-bit cones (VR0 H -- VRI
H for red, VG0 H -- VGl H for green, VB0 H -- VBl H for
blue, and VM0 H -- VMl H for monochrome.

•

VOM Read Back Register -- is enabled by RO VOM L low to
pass values input from VOM (via VOM buffer) out to the
CPU or CPo

Table 6-4 defines the VOM accessing scheme for both the CPU or CP
and video logic access of each byte for each output map. Table 6-5
defines the intensity value associated with each of the two-bit
color and monochrome values output to the O/A. Later in this
chapter, Table 6-6 describes the signals shown in Figure 6-35.

6-43

FROM
CK 64MZ H
TIMING
AND
CONTROL

rvo;I

ADDRESS

1
I

SELE-;::.C..:..T_ _...L..,

P-S
INPUT
BUFFER

FROM
MODE
SELECT

FROM
VIDEO
ACCESS
VBDOH-VDB7H
FROM
MODE
SELECT

TO
VIDEO
ACCESS

VOM
READ BACK
REGISTER

FROM
VIDEO
ACCESS

VOM
VDBOH-VDB7H
VOM
BUFFER

TO
D/A
VBOH-VB1H

WR VOM L
VMOH-VM1H

* SHARES SAME PHYSICAL COMPONENT (2918)
WITH DBLANK GENERATOR OF TIMING AND CONTROL
MA-0395-84

Figure 6-35

Output Map Block Diagram

6-44

Table 6-4

Video Output Map (VOM) Addressing

Processor Access
Video Output Access
(EN VOM H LOW)
(EN VOM H HIGH)
MAP/Byte
CPU Address
CP Address
VOM13 H--VOMl H P13

H--P1 H*

MAP13/BYTE13
MAP13/BYTE1
MAP13/BYTE2
MAP13/BYTE3

17713413
1771342
1771344
1771346

113H
11H
12H
13H

13
13
13
13

13
1
13
1

13
13
1
1

MAP1/BYTE13
MAP1/BYTE1
MAP1/BYTE2
MAP1/BYTE3

17713513
1771352
1771354
1771356

14H
15H
16H
17H

1
1
1
1

13
13
13
13

13
1
13
1

13
13
1
1

MAP2/BYTE13
MAP2/BYTE1
MAP2/BYTE2
MAP2/BYTE3

17713613
1771362
1771364
1771366

18H
19H
1AH
1BH

13
13
13
13

1
1
1
1

13
1
13
1

13
13
1
1

MAP3/BYTE13
MAP3/BYTE1
MAP3/BYTE2
MAP3/BYTE3

17713713
1771372
1771374
1771376

1CH
1DH
1EH
1FH

1
1
1
1

13
1
13
1

13
13
1
1

Table 6-5

Intensit~

Definition for Output Map Outputs

Vx13

H-Vx1 H*

Intensity

1
13
1
13

1
1
13
13

13
1
2
3

(bright)
(norma 1)
(dim)
(dark)

* x is either R, G, B, or M.

6-45

6.2.16

Digital-to-Analog (D/A)

The D/A circuit converts two-bit color and monochrome value inputs
from the output map into analog video signals output to the color
(VR24l) or monochrome (VR240) monitors.
The
D/A
(Figure
circuits/components.
•

6-36)

consists

the

following

J8 -- is a l5-pin connector that provides video output to
either color or monochrome monitors.
NOTE
J8 can also be used
keyboard data output.

for

output

J8
FROM{ TxDH
KY8D
R D H
IIF
x
TO MONITOR PRES L
CPU
+12VC
GVS H

15
14
13
8
TO
MONITOR

1-6

FROM
GDC [ GHS H

11
10

9
12

VRO H

VR1 H

VR INPUT
STAGE

I STAGE
VR OUTPUT

VGO H
VGINPUT
STAGE

VG OUTPUT
STAGE

VB INPUT
STAGE

VB OUTPUT
STAGE

VG1 H

VBO H

VB1 H
VMOH

J7
VM INPUT
STAGE

VM OUTPUT
STAGE

MA·0396-84

Figure 6-36

Digital-to-Analog (D/A) Block Diagram

6-46

•

J7 -- is a BNC connector for video output to a monochrome
monitor when keyboard data is not being output through
J8,
or
for output to a slave monochrome monitor
(monochrome monitor configured in addition to color
moni tor) •

•

Input Stages -- consists of four identical circuits, one
for each color and monochrome values. Each stage provides
a variable positive value biasing to the base of the
corresponding output stage transistor (D BLANK L low or
two low inputs from the output map will both result in
cutting output stage voltage output to a level below the
voltage needed for display) •

•

Sync Gates -- encode vertical (G VS H) and horizontal (G
HS H)
into monochrome and green
(VG) outputs to the
monitor by providing additional positive biasing to the
output stage transistors and cutting output stage voltage
to a value below the output for screen blanking.

•

Output Stages
consist of the following four similar
PNP transistor networks that generate the actual video
outputs to the monitor.
VR output stage

shown in Figure 6-36

VB output stage

identical to VR

VG output stage -- has the 348 ohm resistor replaced
by a 332 ohm resistor for input of sync value
VM output stage -- has the 348 ohm resistor replaced
by a
200 ohm resistor for input of sync value, and
the capacitor is replaced by an NPN transistor
network for developing two monochrome video outputs.
Table 6-6 describes the signals shown in Figure 6-36.
6.3

SIGNAL DESCRIPTIONS

Table 6-6 describes all the signals shown in this chapter. These
descriptions
are
provided
for
reference, and are listed
alphabetically by mnemonic. Numeric mnemonics are listed last.
6.4

SCHEMATIC REFERENCE INFORMATION

Table 6-7 identifies the logic board component coordinate, and
schematic page and coordinate references for each video logic
circuit and component identified in this chapter.
NOTE
The reference listing is based on Rev. C
of the schematics (CS 5415495-0-1).
6-47

Table 6-6

Video Logic Signal Description

Signal
Mnemonic

Signal
Name

A0 H -- A3 H

Address 0 through 3
High

Sequential counter derived
address used by ROM devices
in timing and control
circuit (TM0) and piS
converter (CT0 and CTl).

A15 H

Address Bit 15 High
( CP)

Defines whether CP ROM (A15
H low) or CP RAM (A15 H
high) is enabled when IO/M
is low.

ALE

Address Latch Enable

Enables address latch to
input 85AD0 H -- 85AD15 H
signals from CPo

BGD BEN L

Buffered GDC Data Bus
Enable Low

Buffered version of GO BEN L
from GDC.

BLANK H/L

Blank High and Low

True control signals during
screen blank periods
developed from G BLK H high
as synchronized by SYNC H
and CK 16 MZ L.

BLANK I L

Blank Inverted Low

True (low) signal during
screen blank periods
developed from BLANK Land
used to develop 0 BLANK L.

BS H

Bit Select High

Used by gate decoder in piS
converter circuit to define
whether high (BS H high) or
low (BS H low) order byte
bit is to be gated.

CAS H

Co 1 umn Address
Strobe High

Timing signal generator
output used to coordinate
EPS Hand EBS H generation
with column address strobe
of bit map (also disables
input of bit map data into
high order byte of bit map
read back buffer when high) •

Description

CK2

MZ L

Clock 2 MHz Low

Clock used by GDC.

CK8

MZ L

Clock 8 MHz Low

Clock used by CPo

6-48

Table 6-6

Video Logic Signal Description (Cont)

Signal
Mnemonic

Signal
Name

Description

CK16 MZ H/L

Clock 16 MHz High and
Low

Clocks used by various video
logic circuits.

DAD3 H/L

Display Address Bit 3
High and Low

Used to generate byte select
address value to row/column
mux when SEL DAD L is low
(scroll addressing of bit
map rather than GDC access) ,
and developed from LB Hand
VEC H during text mode, or
VEC Land LAD16 H during
vector mode.

D BEN L

Data Bus Enable Low

Enables GDC access to GDC
data bus lines gated from
BGD BEN L (buffered version
of GO BEN L from GDC) and 0
BIN L are both true.

o BIN L

Data Bus Input Low

Control signal output of
timing signal generator
coordinating GDC access to
GDC data bus lines by
providing enable (0 BIN L
low) or disable (0 BIN L
high) to 0 BEN L gate.

o BLANK L

Display Blank Low

Active low during screen
blank periods used at D/A to
force all video signal
outputs to blank level.

DIR H

Direction High

Control output from register
one which defines whether
scroll address counter is to
increment (DIR H low) or
decrement (DIR H high) •

EBS H/L

Enable Bit Select High
and Low

Coordinates byte select
activity with EBS Hand EBS
L going to true condition
on second CAS H true after
RAS H true condition.

EN VOM H

Enable VOM High

6-49

Table 6-6

Video Logic Signal Description (Cont)

Signal
Mnemonic

Signal
Name

END H

End High

Control output from timing
signal generator used to
generate STOP L low when GDC
is not seeking access to GDC
bus lines (BGD BEN L is high
to stop gate), or to start
RMW cycle when GDC is
seeking access to GDC bus
lines (GO BEN H high to RMW
genera tor) .

EPS H/L

Enable Plane Select
High and Low

Coordinates plane select
activity with EPS Hand EPS
L signals going true on
first CAS H true after RAS
H true condition.

ERASE L

Erase Low

G0 L -- G3 L

Gate 0 through 3 Low

Gate inputs to each of the
four PIS converter devices,
one gate for each, and one
gate at a time active,
defining which bit of which
plane is processed.

GAD0 H -GAOlS H

Gate 0 through 15
High

GDC Address/Data Lines zero
GDC bus lines used for
transfer of data and address
values.

G BLK H

GDC Blank High

GDC output defining screen
blank condition.

GD0 L
GD7 1

GDC Data 0 through
7 Low

Data originating at GDC as
either GAD0 H -- GAD7 H or
GADS H -- GAOlS H and used
for write data to bit map
during GDC access of bit
map.

GO BEN L

GDC Bus Enable Low

GDC output requesting access
of GDC bus lines.

G HS H

GDC Horizontal Sync
High

GDC output defining
horizontal sync period.

Description

6-50

Table 6-6

Video Logic Signal Description (Cont)

Signal
Mnemonic

Signal
Name

GRAS L

GDC Row Address Strobe
Low

GDC control output used at
ROM address clock generator
to start counter.

G RD L

GDC Read Low

Low input from CPU to video
access circuit to access a
video logic component for
a read transaction.

G VS H

GDC Vertical Sync High

GDC output defining vertical
sync period.

G WLB L

GDC Write Low Byte Low

Low input from GDC to video
access circuit to access a
video logic component for a
write transaction.

IB H

Intensity, Background
High

Defines background intensity
factor to logic unit for
either plane zero (developed
from IB(3 H) or plane 1
(developed from IBI H).

IB(3 H
IBI H

Intensity Bit (3 and 1,
Background High

Background intensity values
from logic unit register.

IF H

Intensity, Foreground
High

Defines foreground intensity
factor to logic unit for
either plane zero (developed
from IF(3 H) or plane one
(developed from IFI H).

IF(3 H
IFI H

Intensity Bit (3 and 1,
Foreground High

Foreground intensity values
from logic unit register.

IO/M

I/O or Memory

CP output defining access of
I/O device (IO/M high) or
memory (IO/M low).

LADIS H

Latched Address Bit IS
High

Output from latched address
mux during GDC access of bit
map addressing defining
plane selected (plane zero
when LADIS H is low, plane
one when high) .

Description

6-S1

Table 6-6

Video Logic Signal Description (Cont)

Signal
Mnemonic

Signal
Name

LAD16 H

Latched Address Bit 16
High

Output from latched address
mux during GDC access of bit
map addressing defining
which byte to be selected in
text mode (low byte select
when LAD16 H is low, high
byte select when high, with
LAD16 H value ignored in any
mode other than text).

LB H

Low Byte High

Active high whenever any GDC
bus high order bit (GAD8
H -- GAD15 H) is an active
high.

LDA1 H
LDA8 H

Latched Address Bit 0
through 8 High

Address values to be routed
through map with value
originating at GDC (SCROLL
EN H low input to latched
address mux) or scroll
address counter (SCROLL EN H
high) .

LLB H

Load Low Byte High

Timing signals generator
output enabling bit map
output data to be loaded
into bit map read back
buffer when low.

M0 H -- Ml H

Mode Select Bit 0 and 1 Control outputs from logic
High
unit register defining mode
of operation to logic unit.

MAD0 H
MAD7 H

Memory Address Bit
o through 7 High

Bit map address inputs for
column and row addressing.

MD0 H
MD7 H

Memory Data Output
Bit 0 through 7 High

Bit map data output.

MDI0 H
MDI7 H

Memory Data Input 0
through 7 High

Write data select circuit
output to bit map from
either GDC (GD0 L -- GD7 L),
logic unit (WP0 L -- WP7 L),
or bit map itself (MD0 H
MD7 H).

Description

6-52

Table 6-6

Video Logic Signal Description (Cont)

Signal
Mnemonic

Signal
Name

MONITOR
PRES L

Monitor Present Low

Status signal from monitor
to CPU logic routed through
monitor connector (J8).

p(3 HB H

Plane

High Byte High

PIS converter devices output
for single bit of plane (3
high order byte.

p(3 LB H

Plane (3 Low Byte High

PIS converter devices output
for single bit of plane (3
low order byte.

PI HB H

Plane 1 High Byte High

PIS converter devices output
for single bit of plane 1
high order byte.

PI LB H

Plane 1 Low Byte High

PIS converter devices output
for single bit of plane 1
low order byte.

PAT L

Pattern Low

Vector pattern based on
pattern register data as
multiplied by factor in
pattern multiplier
register.

PS L

Plane Select Low

Logic unit register value
used during single plane
write operations to define
plane to be affected as
plane (3 (PS L low) or
plane 1 (PS L high) •

RAH H

Row Address High Byte
High

Timing signals generator
output enabling row/column
mux to pass low order
address byte for row
addressing (RAH H low), or
high order address byte for
column addressing (RAH H
high) .

RAM OE L

RAM Output Enable Low

Output from CP memory
decoder enabling CP access
of RAM.

Description

6-53

Table 6-6

Video Logic Signal Description (Cont)

Signal
Mnemonic

Signal
Name

RAS H

Row Address Strobe Low

Timing signals generator
output coordinating activity
during row addressing of bit
map.

RD L

Read Low

Low output from CP when
accessing either I/O device
(IO/M high) or memory (IO/M
low) for read.

RD BUF L

Read Buffer Low

Low input from CPU to read
data from 81385 RD buffer
(also resets handshaking

Description

F /F) •

RD GDC L

Read GDC Low

Low output from video access
circuit when CPU/CP is to
access GDC for read.

RD INIT CB
ADDR L

Read to Initialize
Character Address
Low

Low output from video access
circuit when CPU/CP wants to
initialize character buffer
address counter.

RD YOM L

Read YOM Low

Low output from video access
logic when CPU/CP is to
access YOM for read.

RDAf3 H
RDA7 H

Remote Data Bit 13
through 7 High

Data bus lines for transfer
of data between video logic
and CPU.

RMW H/L

Read-Modify-Write High
and Low

Control signals true during
RMW cycles.

ROM7 OE L
ROM8 OE L

ROM 7 and 8 Output
Enables Low

Low output from CP memory
decode when CP is to access
ROM (either ROM7 OE L low
for 32K ROM or first 16K of
ROM, or ROM8 OE L low when
more than one ROM device is
used and access is to be for
data stored above first 16K
of ROM).

RST 5.5

Reset 5.5

See G VS L.

6-54

Table 6-6

Video Logic Signal Description (Cont)

Signal
Mnemonic

Signal
Name

Description

RST 6.S

Reset 6.S

See S1.

RST 7.S

Reset 7.S

See G HS L.

RxD H

Receive Data High

Serial keyboard data input
routed through the monitor
connector (J8).

S BLANK L

Screen Blank Low

Control signal low during
screen blank periods and
developed from G BLK H high
inverted input synchronized
to RAH H.

S0 A H -- Sl
A H

Select Mode Bit 0
and 1 A High

Mode select input to piS
converter device used to
convert plane zero low order
byte to serial data (P0 LB
H) •

S0 B H -- Sl
B H

Mode select input to PIS
converter device used to
convert plane one low order
byte to serial data (PI LB

Select Mode Bit 0
and 1 B High

H) •

C H

Select Mode Bit 0
and 1 C High

Mode select input to PIS
converter device used to
convert plane zero high
order byte to serial data
(P0 HB H).

S0 D H -- S 1
D H

Select Mode Bit 0
and 1 High

Mode select input to PIS
converter device used to
convert plane one high order
byte to serial data (PI HB

S0 C H -- S 1

H) •

SAD0 H -SADIS H

Scroll Address Bit 0
through IS High

6-SS

Address values input to bit
map addressing from scroll
address counter and used to
develop bit map address
values when GDC is not
accessing the bit map.

Table 6-6

Video Logic Signal Description (Cont)

Signal
Mnemonic

Signal
Name

SCROLL EN
H/L

Scroll Enable High
and Low

Control outputs from
register one used to
coordinate access of bit
map, and with SCROLL EN H
used with SEL SD H, with
signals defining either DMA
scroll of bit map (bit map
data writen back into bit
map without modification
when both controls are
true), GDC access of bit map
(GDC modified data written
into bit map when both
controls are false), or
logic unit access of bit map
(logic unit modified data
written to bit map when
SCROLL EN H is high and SEL
SD H is low).

SEL DAD L
SEL LAD L

Select Display Address
Low and Select
La tched Address
Low

Low outputs from DAD/LAD
decoder only when SCROLL EN
H is low (for GDC access of
bit map), screen is
blanked (S BLANK L low),
with SEL LAD L low when read
back mode is selected (SEL
GDC H is high) and SEL DAD L
low tied to RMW cycles (RMW
L low) during other than
read back mode (SEL GDC H
low), with DAD/LAD outputs
used at plane and byte mux
to define select values for
addressing the bit map,
either EPS H and DAD 3 H
(GDC access for other than
read back mode, SEL DAD L
low and SEL LAD L high), EPS
H for both select values
(GDC access for read back
Mode, SEL DAD L high and SEL
LAD L low), or EPS Hand EBS
H (access by other than GDC,
both signals high) •

Description

6-56

Table 6-6

Video Logic Signal Description (Cont)

Signal
Mnemonic

Signal
Name

SEL EXT LU H

Select External Logic
unit High

Control output from register
zero enabling write data
select mux to select logic
unit data for output to the
bit map in other than DMA
scroll mode (SEL SO H low).

SEL GDC H

Select GDC High

Control output from register
zero defining read back mode
(SEL GDC H high) or other
than read back mode (SEL GDC
H low).

SEL LB L

Select Low Byte Low

Timing signals generator
output to piS converter
selecting P0 HB H -- PI HB H
output to output map (SEL LB
L high) or P0 LB H -- PI LB
H (SEL LB L low).

SEL SO H

Select Screen Data
High

Control output from register
one used to enable write
data select circuit to
output data to bit map from
bit map (SEL SO H high), GDC
(SEL SO H low and SEL EXT LU
H low), or logic unit (SEL
SO H low and SEL EXT LU H
high) .

SEL VPAT H

Select Vector Pattern
High

Control output from register
zero used to enable pattern
select mux to output
character (SEL VPAT H low)
or vector (SEL VPAT H high)
data to the logic unit.

Serial Input

High input to CP whenever
handshaking piP has been
set by CPU.

SP H

Select Plane High

Control output from logic
unit register defining
single plane (SP H high)
or two-plane write tasks (SP
H low).

Description

6-57

Table 6-6

Video Logic Signal Description (Cont)

Signal
Mnemonic

Signal
Name

STOP L

Stop Low

Low signal when END H is
high and GDC is not seeking
access to bus (BGD BEN L
high), with STOP L used to
clear timing signal
generator to initial
condition for start of new
cycle.

SYNC H

Sync High

Control output from the
timing signals generator
used to synchronize blank
signal generation.

TxD H

Transmit Data High

Serial keyboard data output
routed through the monitor
connector (J8).

VA0 H
VA3 H

Video Address Bit 0
through 3 High

Address bits originating at
CPU/CP and used to address
VOM when VOM access by
CPU/CP is enabled by EN VOM
H low (VA0 H is also used
for address input to GDC) .

VA4 H
VA7 H

Video Address Bit 4
through 7 High

Address bits originating at
CPU/CP and used by video
access to decode video logic
I/O device to be enabled for
read (VIO RD L low) or write
(VIO WR L low).

VB0H
VBlH

Video Blue Output Bit
o and 1 High

Output map two-bit value to
D/A CPU/CP blue.

VDB0 H
VDB7 H

Video Da ta Bi t 0
through 7 High

Data lines for transfer of
data between video logic I/O
devices (or VOM) and video
access circuit.

VEC H/L

Vector Mode High and
o Low

Control outputs from
register defining vector
mode (signals true) or
text mode (signals false).

VG0 H
VGl H

Video Green Output Bit
o and 1 High

Output map two-bit code to
D/A CPU/CP green.

Description

6-58

Table 6-6

Video Logic Signal Description (Cant)

Signal
Mnemonic

Signal
Name

VID ACCESS L

Video Access Low

Low input to video access
from CPU whenever CPU is
to access video logic for
read or write.

VIO RD L

Video I/O Read Low

Low to video I/O decode
whenever CPU/CP is to access
I/O device for read.

VIO WR L

Video I/O write Low

Low to video I/O decode
whenever CPU/CP is to access
I/O device for write.

VM(3 H
VMl H

Video Mono Output Bit
(3 and 1 High

Output map two-bit code to
D/A for mono.

VOM(3 H
VOMl H

VOM Map Select Bit (3
and 1 High

Output from register zero
defining which output map is
to be addressed (map(3 -map3) during video logic
access of VOM.

VR(3 H
VRl H

Video Red Output Bit (3
(3 and 1 High

Output map two-bit code to
D/A for red.

WP(3 L
WP7 L

Write Pattern (3
through 7 Low

Data output from logic unit
used as data for bit map
when write data select
circuit is enabled to pass
logic unit inputs (SEL EXT
LU H high and SEL SD H low).

WR L

Write Low

Low output from CP for write
to I/O device (IO/M high) or
memory (IO/M low) •

WR BUF L

Write Buffer Low

Low input from CPU setting
handshake F/F when CPU wants
to write to CPo

Description

WR CHAR BUF L Write Character Buffer
Low

Low output from video access
for CPU/CP write to
character buffer.

WR GDC L

Low output from video access
for CPU/CP write to GDC.

Write GDC Low

6-59

Table 6-6

Video Logic Signal Description (Cont)

Signal
Mnemonic

Signal
Name

WR HB SCROLL
DA L

write Scroll Display
Address High Byte Low

Low output from video access
for CPU/CP write of high
byte data to scroll address
counter.

WR LB SCROLL
DA L

write Scroll Display
Address Low Byte Low

Low output from video access
for CPU/CP write of low byte
data to scroll address
counter.

WR LU L

write Logic Unit Low

Low output from video access
for CPU/CP write to logic
unit register.

WR MASK L

write Mask Low

Low output from video access
for CPU/CP write to write
mask register.

WR PAT MULT L write Pattern
Multiplier Low

Low output from video access
for CPU/CP write to pattern
multiplier register.

WR REG0 L

write Register 0 Low

Low output from video access
for CPU/CP write to register
zero.

WR REGI L

write Register I Low

Low output from video access
for CPU/CP write to register
one.

WR VOM L

write YOM Low

Low output from video access
for CPU/CP write to VOM.

WR VPAT L

write Vector Pattern
Low

Low output from video access
for CPU/CP write to vector
pattern register.

Xl -- X2

Clock Bit I and 2

Opposing phased clock inputs
to CPo

85AD0 H
85AD7 H

8085 Address/Data Bit
o through 7 High

Data and low byte address
lines (for address values
to be latched into address
la tch) .

Description

6-60

Table 6-6

Video Logic Signal Description (Cont)

Signal
Mnemonic

Signal
Name

Description

85AD8 H -85AD13 H

8085 Address/Data Bit
8 through 13 High

Address values output to CP
ROM and RAM devices.

85AD14 H

8085 Address/Data Bit
14 High

Address value used at CP
memory decode to define
enable 0 ROM7 (ROM7 OE L
low) or ROM8 (ROM8 OE L low)
and as most significant bit
of ROM address.

85 lORD L

8085 I/O Read Low

Low input to video access
from CP R/W control when CP
is to access I/O device for
read.

85 IOWR L

8085 I/O write Low

Low input to video access
from CP R/W control when CP
is to access I/O dvice for
write.

85LA0 H
85LA7 H

8085 Latched Address
Bit 0 through 7 High

Low order address for
memory or I/O access by CPo

85RD BUF L

8085 Read Buffer Low

Low output from video access
when CP is to read data from
8085 WR buffer input from
CPU (also resets handshaking
F /F) •

85WR BUF L

8085 write Buffer Low

Low output from video access
when CP is to write data to
8085 RD buffer for CPU.

8085 RDY L

8085 Ready Low

Status signal output from CP
to CPU.

8085 RESET L

8085 Reset Low

Reset input to CP from CPU.

6-61

Table 6-7

Video Logic Schematic References

Logic Board
Circuit/Component
Address latch
Ben and stop gates
Bit map memory
Blank F/F
Blank I F/F
BS gate
Buffer gates
Character pattern address
counter
Character pattern buffer
Clear F/F
Counter clock gate
CP
CP gate
CP memory decoder
CP RAM
CP ROM 7
CP ROM 8
CP video data buffer
CPU video data buffer
CT13
CT1
D blank buffer
DAD 3 generator
DAD/LAD decoder
Divider
DMA buffer
EPS/EBS generator
Erase F/F
Gate decoder
GDC
Handshaking F/F
HI/La byte mux
Intensity select mux
J3
J8
Latched address mux
LB H generator
Logic unit
Logic unit register
Mask enable gate
Mask select mux
Multiplier clock and load
gates
Mux select gate
Pattern multiplier counter

Schematic
Reference
Numbers

Page
Coordinate

El133
E136,E137,E1S9
E141,E1713-E177
E137,E1S7,E1S9
El16
E1413
E1313,E14S
E178

9
18
14
18
18
18
13
IS

CS
A4-A6/B3
D1-D3
A1-A4
Al
CS
BS-CS
C7

E18S,E192
E1S8,E1S9
E77,El139
El131
El139
E1S13
El132
Ell313
E131
El138
El137
E187
E188
EllS
E77,E78,E93
E136,E138
E167,E169
E141,E179
E1613
E94,E121
E138
E129
El16
E142,E143
E164
J3
J8
El139,El14,E124,E12S,
E127
E78,El17,E141,E1S3,
E1S4
E182,E183
E163
E93
E161,E162
E66,E72

IS
18
lS
9
113
9
9
9
9
113
113
18
18
16
13
18
18
13
18
18
18
11
9
13
lS
17
17
11

CS/DS
B7
B7
A7-D7
AS
B4
A2
C2
C2
A3
A6
D3
C3
04
C1-C3
C1-C2
DS-D6
B7
B3-B4
B7
B2
A8-D8
C7
C7-D7
B7
AS
BS-DS
AS-CS

A2-B2

IS
lS
14
14
12

C2-D2
BS
C7
C7-D7
B4

E78,E1413
E65

13
12

C7
B4

6-62

Table 6-7

Video Logic Schematic References (Cont)

Logic Board
Circuit/Component
Pattern multiplier register
Pattern register
Pattern select mux
Plane and byte mux
PM gates
PIS converters
PIS mode select buffer
PIS output mux
Read back buffer
Register 0
Register 1
Register clock gate
RMW F/F
ROM ADDRESS CLOCK
Row/column mux
R/W control
S blank F/F
Scroll address counter
Scroll/stop F/F
Sync gates
Timing signal buffer
TM0
VB input stage
VB output stage
VG input stage
VG output stage
Video address mux
Video I/O decoders
Video RO/WR mux
VM input stage
VM output stage
VOM
VOM address select
VOM buffer
VOM read back buffer
VR input stage
VR output stage
write data select mux
write mask latch
Yl
8085 read buffer
8085 write buffer

Schematic
Reference
Numbers
E64,E78
E79
E186,E190
E139
E94,E109
E146,E147,E165,E166
E189
E129
E126,E144
E96,E191
E122,E141
E69
El19
E168
E120,E128
El17,E136
E157
El10-El13
E137,E158,E159
E77,E83
E148
E149
E82,R100,R101
E84,R98,R99,R102,
R103,C45
E82,R96,R97
E84,R92-R95,C44
E88,E104
E76,E92,El17
El18
E83,R106,R107
E84,R104,R105,R108,
R109,Rl12-Rl14,C46,
C48,Ql
E97,E98
E77,E95,El15
E99
E80
E81,R87,R88
E84,R89-R91,R190,C43
E180,E181
E156
Yl,E167
E105
E106

6-63

Page
Coordinate
12 B5
12 C2
15 C4/04
11 04
15 B2
16 A7-07
18 02
16 06
13 A4/04
16 B5-B6
12 04-05
12 B2
18 A7
18 B6
11 B3-C3
9 A6
18 B2
A7-07
18 C6-C8
17 B 7/07
18 B5
18 B5
17 C7
17 C6
17
17
10
10
10
17
17

C7
C6
C6-06
C3/03
B6
B7
B6

16
16
16
16
17
17
14
14
18
9
9

A3/C3
B5/C5/04
B2
Bl
07
06
A7-B7
06
C8
04
02

CHAPTER 7
LK201 KEYBOARD

7.1

GENERAL

The LK201 keyboard module
(shaded area in Figure 7-1) is the
user's interface to the terminal. The keyboard detects keystrokes,
encodes them, and transmits and receives information to and from
the CPU logic in the system box.
Communication
between
the
keyboard and the CPU logic is
full-duplex,
serial, and asynchronous at 4800 bits-per-second
(bps). The communication lines conform to EIA standard RS-423,
which applies to imbalanced voltage interfaces.

SYSTEM BOX

LOGIC

/ / VIDEO
LOGIC

_ _ ..L / _ _ _ _ _

SYSTEM
COMMUNICATION

EIA
HOST
PORT

PRINTER
PORT

20 mA
PORT

OPTIONAL
HOST
COMMUNICATIONS

MONITOR
IVR201 OR VR241)

MA-OOS4-84

Figure 7-1

VT240-Series Terminal System
Block Diagram
7-1

7.2

PHYSICAL DESCRIPTION

The keyboard used in the VT240 Series Terminal has 105 keys
arranged in the following four groups (Figure 7-2).
•
•
•
•

Main keypad (57 keys)
Numeric keypad (18 keys)
Special function keypad (20 keys)
Editing keypad (10 keys)

NUMERIC
KEYPAD

KEYPAD

Figure 7-2

LK201 Keyboard

7-2

You can install the keycaps manually, but you need a special tool
to remove them.
The keyboard circuitry is contained in a low profile cabinet that
has a 30 mm nominal height from table top to home row. The
keyboard case is made of two plastic shells that you can separate
with a screwdriver. Nonslip plastic strips along the bottom
prevent the keyboard from sliding on a table top. You can manually
insert two feet in holes to raise the back edge of the keyboard.
You can lift a plastic window along the top edge above the special
function keys to insert a user function label. The label, a thin
paper strip, fits into the indented space and varies according to
the application program.
A coiled cable
(PN BCC01), with a four-pin modular connector on
each end, connects the keyboard to the video monitor. The keyboard
transmits four signals to the monitor, which pass unchanged to the
system box via the video cable (Figure 7-3). The four signals are
as follows.
•
•
•
•

+12 V power to keyboard
Ground to keyboard
Serial out (transmit line from keyboard)
Serial in (receive line to keyboard)

You can place the cable in a channel in the bottom case and the
modular type telephone connector fits into jack J4. You can insert
the cable in the channel on either side of the keyboard. Section
7.6 provides keyboard specifications.

r
KEYBOARD
CIRCUIT
BOARD

I
I
I

I
I
I
I
I

'MONITOR

I
I

I SERIAL OUT
I
I SERIAL IN

I
I
\

4 WIRE
KEYBOARD
CABLE

,- \
I

I
I
I

, CONNECTION TO SYSTEM BOX
TOUCH MONITOR IS OPTIONAL

+12V
GND

SYSTEM
BOX

r-------,
CENTRAL
PROCESSOR

I
I
I

f-------'

PART OF
VIDEO
CABLE
MA-0270-82A

Figure 7-3

Keyboard Cable Connections

7-3

FUNCTIONAL DESCRIPTION

7.3

This section
keyboard.

provides

functional

description

the LK201

Keyboard Operation Overview

7.3.1

Figure
7-4 is a simplified block diagram of the keyboard
circuitry.
Everything except the block marked KEYBOARD SWITCH
MATRIX is on the printed circuit board. This block represents the
connections between the keyboard switches and the signals from the
8051 microprocessor.
The firmware in the 8051 eight-bit microprocessor controls the
following three major keyboard operations at the same time.
1.

Scans the
matrix

r- -1

BCD TO
DECIMAL
DECODER

0 1

~ I

(

keyboard

) CONN.

KEYBOARD
MATRIX
18 X 8 LINES

,I
P

CONN.
.,--.. KB

I R
I 2
I

DATA
0·7

'-"

I
-1

changes in the keyboard

detect

KEYBOARD
LEOs
CONTROL
CIRCUIT

KB DRIVE
0·17

+5V LED
SUPPL Y

BEEPER

3
ON/OFF

BEEPER
CONTROL
CIRCUIT

---IL

S~EEP=BELL

i 2 KHZ

P 1

1
~ 1
o1

8051
MICROPROCESSOR

BEEP=KEYCLICK

2 MS

TIMING
NETWORKS

125 MS

TIMER
NO.1

I---

TIMER
NO.2

·lOV
SUPPLY

190 KHZ

f--. 10V

II
I P

JUMPERS FOR
HARDWARE 10

10
I R
IT

+5V -10

POWER UP
RESET
SIGNAL
CIRCUIT

I 3
I
I
I
RESET

1
1

.,--..

RECEIVE

TRANSMIT

RECEIVER

""""

DRIVER

SERIAL OUT

·10V

4KB ROM
128 BYTES RAM

+12V
+5V
SUPPLY

'-"

J4
KEYBOARD
CABLE
CONNECTOR

LK201 Keyboard Block Diagram

7-4

CO NFORMS
TO RS-423

t
GND

Figure 7-4

}

f---+ +5V

Transmits results of the keyboard scan to the CPU

Receives information from the CPU

7.3.1.1 Keyboard Scanning -- The keyboard switches are connected
at the intersections of an 18 X 8 line matrix. This provides a
fixed position identifier for each key.
The firmware scans the 18 line axis and detects a pressed or newly
released key by reading the eight-line axis. The firmware then
verifies
the
detected keystroke and changes this position
information into an eight-bit code that is unique to that key.
7.3.1.2 Control of Audio Transducer and Indicators -- Two circuits
control the audio transducer and the indicators. One circuit
receives its inputs from the 8051 and controls the transducer
(beeper).
A long beep represents the bell and a short beep
represents the keyclick.
A separate circuit, controlled by a signal from the 8051, controls
each of the four indicators. The firmware, responding to commands
received from the CPU, turns the indicators on or off.
7.3.2

Keyboard Firmware Functions

This section describes the keyboard firmware functions.
The
functions are divided into two categories: functions that cannot
be changed by CPU instructions, and functions that can be changed
by CPU instructions.
7.3.2.1 Functions
Not
Changed by CPU Instructions
The
following
functions cannot be changed by instructions from the
C~.

Powerup test
Keycodes
Special codes
Power-Up Test
Upon power-up, the firmware performs a self-test in less than 70
ms. The test results are transmitted to the CPU in four bytes.
The
keyboard indicators are lit during the self-test. The
indicators blink once during the self-test routine. The indicators
remain lit if the test is failed,
but go off if the test is
passed. The system module can also request a self-test at any
time.

7-5

Keycodes
The keycodes represent fixed positions in the key switch matrix.
The key associated with a particular matrix position is always
represented by the same keycode.
Special Codes
There are 13 special codes transmitted by the keyboard. Four codes
transmit the results of the power-up self-test. The other nine
codes are status indicators or command acknowledgements.
7.3.2.2 Functions Changed by CPU Instructions -- The CPU can
issue
instructions
to
change
some
keyboard transmission
characteristics and to control the keyboard indicators and beeper.
Upon completion of a successful power-up self-test, the firmware
sets certain functions to predetermined conditions. These are
referred to as default conditions. The conditions can be changed
but they always come up to the default condition after a
successful power-up self-test.
7.3.2.3 Firmware Functions Changed by CPU Instructions -- Certain
firmware functions can be changed by commands (instructions) from
the CPU. These commands are categorized as transmission commands
and peripheral commands. Transmission commands contain a mode set
command and an autorepeat rate set command. Peripheral commands
contain a variety of commands. Refer to section 7.5.5.3 for more
information on peripheral commands.
7.4

Detailed Keyboard Circuit Description

This section describes the keyboard circuit. Figure 7-4 shows the
keyboard block diagram.
7.4.1

Keyboard Matrix Scanning

The key locations are arranged in an 18 X 8 line matrix. Each key
switch is connected across a matrix intersection. This gives a
fixed position for each key connected in the matrix. This matrix
accommodates all 105 keys in the keyboard.
Figure 7-5 is a simplified block diagram of the matrix scanning
circuit. Eight lines from PORT 1 of the 8051 microprocessor go to
the
binary
coded
decimal
(BCD)
inputs
of two 74LS145
BCD-to-decimal decoders. Ten outputs from one decoder and eight
outputs from the other decoder provide the drive lines for the
matrix. These 18 lines are called KB DRIVE 0 -- 17.

7-6

.------'WV--~+5V

2 TYPE
74LS145
DECODERS

80511l P

r--I PORT 1
I SCANS
IL MATRIX
____

8 LINES

'"
/

(8 BCD
INPUTS
AND18
DECIMAL
OUTPUTS)

I\.

18 LINES V
KB DRIVE 0-17

~~TO-

~
KEY
~LOSUR-== '\..,

18 X 8 LI NE
-MATRIX

I READS

8 LINES
KB DATA 0-7

TYPICAL SWITCH
CONNECTION AT
MATRIX
INTERSECTION

Figure 7-5

Matrix Scanning Block Diagram

The other axis of the matrix consists of eight lines tied to +5 V
through pull-up resistors. These lines go to PORT 0 of the 8051
microprocessor and are called KB DATA 0 -- 7.
The 8051 scans the 18 drive lines. Key closures are detected by
reading the eight data lines. The complete matrix is scanned every
8.33 ms.
When a key closure is detected, it is scanned again to verify that
it is really a key closure and not electrical noise.
Once the key closure is verified, the 8051 firmware translatea the
position information into a key code and transmits it to the cpu.
Transmission is handled by the Universal Asynchronous Receiver
Transmitter (UART) in the 8051.

7-7

A ghost key indication can occur when three of the four corners of
a matrix rectangle are closed (Figure 7-6) causing what is known
as a sneak path. The key positions in the matrix are arranged to
avoid sneak paths. However,
if a sneak path does occur, the
firmware prevents the keycode for the key that caused the sneak
path to be transmitted until one of the involved keys is released.
This prevents transmission of ghost keys entirely.
Table 7-1 shows the keyboard matrix on the LK201-AA (American)
keyboard.
Keycap designations are listed for reference only; you
can compare them to Figure 7-7 (A and B) .

---.--~~------~--~----3

DRIVE
LINES

---'--r-~------~--~----2

DATA
LINES
1. CONDITIONS ARE: SWITCHES B2, B3, AND C3 CLOSED,
SWITCH C2 OPEN; LINE 2 IS BEING DRIVEN AND LINE C
IS BEING READ.
2. INTERSECTION C2 IS BEING LOOKED AT. IT SHOULD NOT
SHOW A KEY CLOSURE BECAUSE SWITCH C2 IS OPEN.
3. HOWEVER A SNEAK PATH IS PRESENT FROM LINE 2
TH ROUGH SWITCHES B2, B3, AND C3 TO LINE C
A GHOST KEY IS READ AT INTERSECTION C2.
MA-0273-82

Figure 7-6

Example of Ghost Key
Generation

7-8

Table 7-1

Keyboard Matrix

Refer to Figure 7 (A and B). It shows the international matrix for the LK201 keyboard.
The legends provided are from the LK201 keyboard and are provided for convenience
only.
KB

KB DATA

Drive

Reserved

F19

Reserved

F20

PF4

N
(Note 1)

ENTER

G23

E23

023

C23

A23

022

B17

C22

B22

A22

021

C2l

B1B

B2l

N0
(See
Note 2

REMOVE

E1B

C17

020

C20

B20

A20

PREV
SCREEN
017

{

Reserved

G22
16

-.J
I

\.0

F18

PF3

G2l

E22

F17

PF2

G20

E2l

PFl

NEXT
SCREEN
018

E20
13

INSERT
HERE
E17

Ell

Reserved

G16

NOTES
1. Note that N0 -- N9, N_, N"

[

011

Cll

refer to the numeric keypad.

2. N0 of the numeric keypad can be divided
keyswitch is implemented as a double size key.

into two keys. Normally only the N0

3. The RETURN key also canb e divided into two keys. The one that is decoded as return
is the RETURN (C13) key.

Table 7-1

Keyboard Matrix (Cont)

KB
Drive

KB DATA
7

FIND

HELP

SELECT

}
]

RETURN

E12

GIS

016

012

C13

B16

C12

ADDTNL
OPTIONS
G14

X
(delete)
E13

Reserved

)

See
Note 3

;

Reserved

F12

Reserved

E16
11

lr.J

r.J
Elr.J

G12
9

Reserved

Fll

Reserved

Dlr.J

Clr.J

F13

(

G13

9
Er.J9

Dr.J9

Cr.J9

Blr.J

Br.J9

8
Er.J8

Dr.J8

Cr.J8

Br.J8

EXIT

Gr.J9

7
Er.J7

Dr.J7

Cr.J7

Br.J7

Reserved

-...J

GIl

I
f-'

r.J

Reserved

MAIN
SCREEN
Gr.J8

Reserved

CANCEL

Reserved

Gr.J7
6

Reserved

SETUP
Gr.J2

Reserved

FS
G03

RESUME
Gr.J6

Reserved

6
Er.J6

Dr.J6

Cr.J6

Br.J6

INTERRUPT
Gr.JS

S
Er.JS

Or.JS

Cr.JS

Br.JS

SPACE

4
E04

004

C04

B04

A01-Ar.J9

Table 7-1

Keyboard Matrix (Cant)

KB
Drive

KB DATA
7

Reserved

PRINT
SCREEN
G00

Rese'rved

BREAK

HOLD
SCREEN
G99

@
2
E02

Reserved

G01

E03

D03

C03

B03

TAB

D00

D02

C02

B02

>
<

B00

C01

B01

E00

--.J
I

.....
.....

CTRL

LOCK

COMPOSE

C99

C00

A99

E01

Reserved

SHIFT
B99,Bll

NOTES
1. Note that N0 -- N9, N_, N"

refer to the numeric keypad.

2. N0 of the numeric keypad can be divided
keyswitch is implemented as a double size key.

into two keys. Normally only the N0

3. The RETURN key also canb e divided into two keys. The one that is decoded as return
is the RETURN (C13) key.

Hold
Screen

Print
Screen

Break

Set-up

F10

Interrupt

Resume

Cancel

Main.
Screen
EXit

F11

F11
(ESC)

F12

F12
(BS)

F13

F13
(IF)

F14

Addit
Options

Hold Screen
_

lock
_

DDDOOnODODDnODODnBI

Compose
_

Waii_

____
F~.?

F18

F19

F20

II IULJUU

IDD~~~~~~~~~u~~

LJLJLJLJ

LJLJEJ[][]D[]E][][]DDDD
IShih 1[][][]D[J~[]~DD[]IShih 1

[][][]D

D[JEJ[][]~rJ[]D[J[]D[]D·tu,"

--------, i _

[]~[][]

[][][]D"t.'

i
i

1°
Figure 7-7A

LK201-AA Keyboard Layout

____

8B8GB

886GB

G8GB

GGGGG6GGGGGGG~

[:JGGGGGGGGGGGGD
IGc:JGGGGGGGGGGGG
I IGGGGGGGGGGGI I
~I
I
I
C13

699

611

A99

A0l1oA09

NOTE" THE GRAPHIC CHARACTERS ARE SHOWN FOR ILLUSTRATION PURPOSES ONLY
AND ARE NOT MEANT TO ASSIGN KEYCAP USAGE OR LEGENDS.

Figure 7-7B

LK201-AA Keyboard Layout

G16

1 8BBB

GGG
BBB
G
GGG

GGGG
BBBB
GGGG
GGGn
I IGl:J
A20

7.4.2

Audio Transducer Control Circuit

Figure 7-8 shows the audio transducer or beeper control circuit.
The beeper is driven by a transistor whose base is connected to a
2 kHz square wave from a 556 timer IC. This signal is biased by a
network of four type 74LS05 open collector inverters. The 8051
microprocessor controls all four inverters via the firmware. The
on/off inverter connects directly to the transistor base. When the
8051 puts a high on the on/off inverter input, its output goes low
and removes the 2 kHz square wave from the transistor base. This
cuts off the transistor and disables the beeper.
To turn on the beeper, the 8051 puts a low on the ON/OFF inverter
input.
Its output goes high and allows the 2 kHz signal to reach
the transistor base; this turns on the beeper. The firmware
generates a keyclick (on for 2 ms) or a bell tone (on for 125 ms) •
The 8051 sets up the three level control inverters by putting one
of eight binary combinations on the inverter inputs. All highs
give the softest sound and all lows give the loudest sound.
The
firmware
controls
the
keyclick
and
the bell tone
independently. The bell tone is sounded only upon request from the
system
control
processor. The keyclick is sounded
(unless
disabled) under the following conditions.
•
•
•

7.4.3

When a key is pressed
When a metronome code is sent
When a command to sound the keyclick is received from the
system control processor
Indicator (LED) Control Circuit

Figure 7-9 shows the LED indicator control circuit.
The control signal for each LED comes from PORT 2 of the 8051 to
the input of a type 74LS05 open collector inverter. The inverter
output goes to the LED cathode; its anode is connected to +5 V. A
separate +5 V source relieves the LED's load on the main +5 V
supply.
A low signal from the 8051 drives the inverter output high, which
cuts off the LED. A high signal from the 8051 drives the inverter
output low. This provides a path to ground from the +5 V through
the LED. The LED then turns on.

7-14

,...------.----- +12V
8EEPER
74LS05
INVERTERS
ON/OFF CONTROL

8051
PORT 2

2KHZrlS

MA·0267·82

Beeper Control Circuit

Figure 7-8

74LS05
INVERTERS
"\--,..--+ 12V

8051
PORT 2

L--.l...II~+5V

HIGH

~E1/
r _ _ . ______

+5V

+ HIGH SIGNAL FROM 8051 PROVIDES
PATH THROUGH LAST STAGE OF
OPEN COLLECTOR INVERTER TO TURN
ON LED.
MA-0268-B2

Figure 7-9

Indicator (LED) Control Circuit

7-15

7.4.4

Keyboard Communication

This section describe the keyboard communication.
7.4.4.1 Keyboard Transmit Mode -- The keyboard codes and a few
other special codes are transmitted via a serial line output in
PORT 3 of the 8051. The transmitted signal goes from the 8051 to a
driver,
through the keyboard cable, monitor, and video cable to
the CPU. A UART within the 8051 controls the transmission.
Transmitted
characters
conform to a
specific format.
Each
character is 10 bits long. The first bit is the start bit. It is
always a
logical zero (space). The next eight bits represent the
encoded data. The last bit is the stop bit. It is always a logical
one (mark). Figure 7-10 shows the character format.
7.4.4.2 Keyboard Receive Mode -- The firmware contains features
that can be enabled by commands from the CPU. There are two
categories
of
features:
one
sets
keyboard
transmission
characteristics and the other controls keyboard peripherals. A
peripheral command covers indicator control, bell and keyclick
loudness,
keyboard ID code, and reinstate keyboard. The commands
come from the CPU and pass through the video cable, monitor, and
keyboard cable to the receiver and into the 8051 via PORT 3. The
commands go to the UART in the 8051.
Received characters conform to the same 10-bit format used for
transmitted characters.
The eight data bits are arranged in a
specified protocol, depending on the command type.

CHARACTER

°1

8 DATA BITS

r - r - T- T-,-,-T-, -,---,-

MARK ( l I L J
I
SPACE (0)

t __

.L_.l._.l_.l._.l._.l._L_J

STOP
BIT

START
BIT

MA-026982

Figure 7-10

Keyboard Transmit and
Receive Character Format

7-16

Reset Signal for 8051 Microprocessor

7.4.5

Whenever the system is turned on, the 8051 microprocessor in the
keyboard must be reset. This allows the 8051 to start operating.
The reset signal generator is active only during powerup. The
input is +5 V. The output is connected to the RESET input of the
8051.
When power is turned on, the +5 voltage starts to rise from
zero. The reset signal circuit output follows it and drops off
when a steady state of +5 V is reached. This circuit holds the
8051 RESET input high (+3.5 V to +5 V) long enough to enable the
reset action in the 8051. This action occurs only during powerup.
7.4.6

Hardware Keyboard Identification (ID)

At powerup, the keyboard performs a self-test and sends the
results to the cpu.
One piece of information to be sent is the
keyboard hardware ID, which is read from hardwired jumpers.
There are six jumpers. Each jumper line goes from an input in PORT
3 of the 8051 to ground. All jumpers are installed so the keyboard
hardware ID is zero.
7.4.7
The
-10
V.

Voltage Supplies

only voltage sent to the keyboard is +12 V. However, +5 Vand
V are also required. These voltages are derived from the +12

There is a +5 V supply that handles most of the requirements for
this voltage. The four keyboard LEDs have their own +5 V supply. A
-10 V supply provides voltage for the driver in the serial out
line.
7.5

KEYBOARD PROGRAMMING

This section describes the functions that the keyboard performs
under
system
central processor control. This section also
describes keyboard programming machine language, but does not
describe high level user programming.
7.5.1

Keyboard Layout and Key Identification

Each keyboard key has a unique location. Each location is scanned,
and when closure or release is detected, the location is verified.
This is then decoded to an eight-bit keycode. Figure 7-7 shows the
keyswitch locations. Table 7-2 shows the 14 functional divisions
of the keyboard.
Table 7-3 shows the divisions, keycaps, and
keycodes.

7-17

Table 7-2

Keyboard Functional Divisions

Division

Description

Representation

48 graphic keys Spacebar

0001

Numeric keypad

0010

Delete character (E12)

0011

Return (C13) Tab (000)

0100

Lock (C00) Compose (A99)

0101

Shift (B99 and B11) CTRL (C99)

0110

Horizontal cursors
(B16 and B18)

0111

vertical cursors
(B17 and C17)

1000

Six keys directly above
the cursor keys
(016 -- 018 and E16 -- E18)

1001

.10

Function keys (G99

G03)

1010

Function keys (G05

G09)

1011

Function keys (GIl

G14)

1100

Function keys (G15

G16)

1101

Function keys (G20

G23)

1110

7-18

Table 7-3

Keycode Translation Table

Division

Position

Keycap

Keycode
Decimal

Keycode
Hexidecimal

Hold screen
Print screen
Break
Setup
F5
Reserved

086
087
088
089
090
091--098

56
57
58
59
SA
5B--62

G05
G06
G07
G08
G09

Reserved
Interrupt
Resume
Cancel
Main screen
Exit
Reserved

099
100
101
102
103
104
105--110

63
64
65
66
67
68
69--6E

GIl
G12
G13
G14

Reserved
Reserved
Fll (ESC)
F12 (BS)
F13 (LF)
Addi tional
Options
Reserved

III
112
113
114
115
116

6F
70
71
72
73
74

117--122

75--7A

GIS
G16

Reserved
Help
00

123
124
125

7B
7C
70

G20
G21
G22
G23

Reserved
F17
F18
F19
F20
Reserved

126--127
128
129
130
131
132--135

7E--7F
80
81
82
83
84--87

Reserved
Find
Insert here
Remove
Select
Previous screen
Next screen
Reserved

136--137
138
139
140
141
142
143
144

88--89
8A
8B
8C
80
8E
8F
90

Function Keys
10

G99
G00
G01
G02
G03

6 Basic Editing Keys
9

E16
E17
E18
016
017
018

7-19

Table 7-3

Keycode Translation Table (Cont)

Division

position

Keycap

A20

Reserved
0
Reserved

Keycode
Decimal

Keycode
Hexidecima1

PFI
PF2
PF3
PF4
Reserved

145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165

91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
Al
A2
A3
A4
A5

Reserved
Left
Right

166
167
168

A6
A7
A8

Down
Up
Reserved

169
170
171--172

A9
AA
AB--AC

Reserved
Shift
CTRL

173
174
175

AD
AE
AF

Lock
Compose
Reserved

176
177
178

B0
Bl
B2

Keypad
2
A22
A23
B20
B21
B22
C20
C21
C22
C23
D20
D21
D22
D23
E20
E21
E22
E23

Enter
1
2
3
4
5
6
7
8
9

Cursor Keys
7
B16
B18
8

B17
C17

Shift, Lock CTRL, A99, and A10
6
B99,B11
C99
5

C00
A99

7-20

Table 7-3

Keycode Translation Table (Cont)

Division

position

Keycode
Decimal

Keycode
Hexidecimal

All ups
Metronome
Output error
Input error
KBD Locked
acknowledge
Test mode
acknowledge
Prefix to keys
down
Mode change
acknowledge
Reserved

179
180
181
182
183

B3
B4
B5
B6
B7

184

185

186

187

Delete (X)

188

Return
Tab

189
190

BD
BE

191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

Keycap

Special Codes

Delete
3

E13

Return and Tab
4

C13
D00

48 Graphics Keys and Spacebar
1

E00
E01
D01
C01
B01
E02
D02
C02
B02
B00

Tilde
!1
Q
A
Z

Reserved
@2
W
S
X

><
Reserved
#3

E03
D03
C03
B03

E04

Reserved
$4

7-21

D0
Cl
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0

Table 7-3

Keycode Translation Table (Cont)

Division

Position

Keycap

D134
C134
C134
A131--A139

R
F

E135
0135
C135
B135
E136
0136
C136
B136
1

E137
0137
C137
B137
C138
0138
C138
B138
E139
0139
C139
B139
El13
0113
Cl13
Bl13

Space
Reserved
%5
T
G

B
Reserved
"'6
y

H
N

Reserved
&7
U

J
M

Reserved
*8
I

, ,

Reserved
(9
13
L

Reserved
) 13
P
Reserved

: ,
? /

Reserved
E12
012
C12

+ =
} ]

I \

Reserved

7-22

Keycode
Decimal

Keycode
Hexidecimal

2139
2113
211
212
213
214
215
216
217
218
219
2213
221
222

01
02
03
04
05
06
07
08
09
OA
DB
DC
DO
DE

223
224
225
226
227
228
229
2313
231
232
233
234
235
236
237
238
239
2413
241
242
243
244
245
246
247
248

OF
E13
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F13
Fl
F2
F3
F4
F5
F6
F7
F8

Table 7-3

Keycode Translation Table (Cont)

Division

position
Ell
Dll
Cll

Keycap

Keycode
Decimal

Keycode
Hexidecimal

249
2513
251
252-255

F9
FA
FB
FC-FF

Reserved

NOTE
The legends under "keycap" are taken from the keycap legends of
the LK2131-AA (American).
Keycodes
unused.

1313

7.5.2

Modes

through

64 are reserved. Keycodes 65 through 85 are

This section describes the function of the keycode transmission
modes. The mode set command allows anyone of the 14 keyboard
divisions to be set to anyone of the following three modes.
(Refer to section 7.5.7 for division defaults.)
•

Down Only Mode -- The keyboard transmits a keycode when
the key is pressed.

•

Autorepeat Down -- The keyboard transmits a keycode when
the key is first pressed. If the key is held down past
the specified timeout period (usually 31313 to 51313 ms), a
fixed metronome code is sent at the specified rate until
the key is released.

•

Down/up
The keyboard transmits a keycode when the key
is pressed and an "up code" when the key is released. If
any other DOWN/UP keys are pressed, the "up code" is a
repeat of the "down code." If no other DOWN/UP keys are
pressed, the keyboard sends an ALL UPS code.

7.5.2.1 Special
autorepeat rate
autorepeat mode.

Considerations
Regarding Autorepeat
The
set command allows the following changes in the

•

Autorepeat
association
division.

•

The timeout and interval values can be changed in anyone
of the four autorepeat rate buffers.

rate
buffer
association
The buffer
can be changed for the selected keyboard

7-23

•

If multiple autorepeating keys are held down, metronome
codes are still generated. The metronome codes apply to
the keycode transmitted most recently. If the last key
pressed is released, and any other keys are still down,
the keycodes for those keys are retransmitted.

Example 1
The a key is held down. This produces the following transmission.
a metronome metronome
Now the b key is pressed. This produces the following
transmission.
a metronome metronome b metronome metronome
Now the b key is released. This produces the following
transmission.
a metronome metronome b metronome metronome a metronome
met. • •
While metronome codes are being generated for an autorepeating
key,
a
nonautorepeating
keycode
or special code may be
transmitted.
The keyboard transmits this special code instead of
the next metronome code, and then returns to the autorepeated
code. The keycode to be autorepeated is always the last byte
transmitted.
Example 2
The a key is held down. This produces the following transmission.
a metronome metronome
Now the SHIFT key is pressed. This produces the following
transmission.
a metronome metronome shift a metronome
Now the SHIFT key is released. This produces the following
transmission.
a metronome metronome shift a metronome ALL UPS a
metronome. • •
•

If an autorepeating key is not to autorepeat (CNTL C for
example), the system module must issue a temporary
inhibit autorepeat command. This halts the transmission
of any metronome codes or keyclicks for that key only.
Metronome codes continue when another key is pressed. The
command
must be issued after the keycode for the
autorepeating key is received.
7-24

•

Autorepeat can be enabled and disabled independently of
the
division
settings by using the enable/disable
autorepeat commands. These commands apply to all keys on
the keyboard. When autorepeat is disabled, internally the
keyboard continues to autorepeat characters. However, it
does not transmit metronome codes or keyclicks. When
autorepeat
is
enabled,
the keyboard transmits the
metronome
codes
from
the point they were before
autorepeat was disabled. This may be within either the
timeout or interval period, depending upon the time
elapsed since the key was pressed.

•

If the keyboard receives a request to change a division
mode to autorepeat while a key is pressed, the keyboard
makes the change immediately. After the specified timeout
period,
the keyboard transmits metronome codes for the
pressed key.
In place of the first metronome code, the
keyboard transmits the keycode of the autorepeating key.

All autorepeating division modes can be changed to only down with
one command. This and other autorepeat commands are grouped with
the peripheral commands (refer to 6.5.5.3).

7.5.2.2 Special Considerations Regarding Down/Up Mode -- If two
DOWN/UP keys are released simultaneously (within the same scan) ,
and there are no other DOWN/UP keys down on the keyboard, only one
ALL UPS code is generated.
7.5.2.3 Autorepeat Rates
There are four buffers in the
keyboard to store autorepeat rates. They are numbered zero through
three. Each buffer stores the following two values. These values
can be changed by the system module.
The timeout value
The interval value
The timeout value is the amount of time between the detection of a
down key and the transmission of the first metronome code
(defaults range from 300 to 500 ms). The interval value is the
number of metronome codes per second (defaults to 30).
Each division is associated with one of the four buffers. Rates
are taken from the associated buffer each time the autorepeat
timers are loaded.
This buffer-to-division association can be
changed by the system module, or left to default.

7-25

7.5.3

Keyboard Peripherals

This section describes the peripherals available on the keyboard.
The
keyclick,
bell, and LEOs are all considered keyboard
peripherals. Refer to section 7.5.5.3 for information on system
module control over these peripherals.
7.5.3.1 Audio
The keyclick is a 2 ms beep and the bell is a
125 ms beep. The bell is sounded only upon request from the system
module. The keyclick (if not disabled by the system module) sounds
under the following three conditions.
When a key is pressed
When a metronome code is sent
When the system module receives a sound keyclick command
If either the B11 or B99 keys (the left and right SHIFT keys on
the LK201) or the C99 key (the CNTL key on the LK20l) are pressed,
the keyclick is not generated. However, if a command is sent from
the system module to enable the keyclick on the C99 key, the
keyclick is generated (refer to section 7.5.5.3). Figure 7-7 shows
the positions of these keys.
The keyclick or bell (or both) may be disabled. When the keyclick
or bell is disabled, it does not sound. If the system module
requests sound (refer to section 7.5.5.3) the keyclick or the bell
does not sound.
Both the keyclick and bell may be independently set to one of the
following eight volume levels.
000
highest
001
default
010
011
100
101
110
III -- lowest
7.5.3.2 Indicators (LEOs) -- The system module normally transmits
indicator control commands. However the following are exceptions.
•

Upon powerup, the keyboard turns all LEOs off.

•

After receiving the inhibit transmission command, the
keyboard turns on the keyboard-locked LED. The LED is
turned
off
after
the keyboard receives a resume
transmission command.

7-26

7.5.4

Keyboard-to-System Module Protocol

This section describes the keyboard-to-system module protocol.
7.5.4.1 Keycode Transmission
The keyboard transmits single
byte keycodes that reflect the keyboard matrix status. The
eight-bit codes above 6410 are used for keycodes. Every key is
identified by a unique keycode. There are no special codes for
shifted or control keys.
Refer to Figure 7-7 and Tables 7-1 and 7-2 for complete keycode
matrix translation table information.
7.5.4.2 Special Code Transmission -- There are 13 special codes.
Nine codes have values above 6410 and four codes have values
below.
The following
value range).

nine special codes have values above 6410 (keycode

ALL UPS

Keycode 179 (decimal),
B3 (hexidecimal)
Keycode 180 (decimal),
B4 (hexidecimal)
keycode 181 (decimal),
B5 (hexidecimal)
Keycode 182 (decimal),
B6 (hexidecimal)
Keycode 183 (decimal),
B7 (hexidecimal)
Keycode 184 (decimal),
B8 (hexidecimal)
Keycode 185 (decimal),
B9 (hexidecimal)
Keycode 186 (decimla),
BA (hexidecimal)
Keycode 127 (decimal),
7F (hexidecimal)

METRONOME CODE
OUTPUT ERROR
INPUT ERROR
KBD LOCKED ACK
TEST MODE ACK
PREFIX TO KEYS DOWN
MODE CHANGE ACK
RESERVED

ALL UPS -- indicates to the system module that a DOWN/UP MODE key
was just released and no other DOWN/UP keys are pressed.
METRONOME CODE -- indicates to the system module that an interval
has passed, a keyclick has been generated, and the last key
received by the system module is still pressed.
OUTPUT ERROR -- indicates an output buffer overflow to the system
module. The overflow occurred after receiving a keyboard inhibit
command from the system module, and some keystrokes may be lost.

7-27

INPUT ERROR CODE
indicates to the system module that the
keyboard received a meaningless command, too many parameters, or
too few parameters.
KEYBOARD LOCKED CONFIRMATION
indicates to the system module
that the keyboard received an inhibit transmission command (refer
to section 7.5.5.3).
TEST MODE ACKNOWLEDGE -- indicates that the keyboard has entered
test mode. This is a special mode used during the production test.
If the system module receives this acknowledgement, it sends 80
hexidecimal. This terminates the test mode and jumps to powerup.
PREFIX TO KEYS DOWN -- indicates that the next byte is a keycode
for a key already down in a division which has been changed to
down/up (refer to section 7.5.5.4).
MODE CHANGE ACKNOWLEDGE
received and processed a
7.5.5.4) •

indicates that the keyboard has
mode change command (refer to section

RESERVED -- keycode 7F is reserved for internal use.
The following four special codes have values below the 6410 range.
KEYBOARD ID (firmware)
KEYBOARD ID (hardware)
KEY DOWN ON POWER UP ERROR CODE
POWER UP SELF-TEST ERROR CODE

Keycode 01 (decimal),
01 (hexidecimal)
Keycode 00 (decimal),
00 (hexidecimal)
Keycode 61 (decimal),
3D (hex idecima 1)
Keycode 62 (decimal),
3E (hex idecima 1)

KEYBOARD ID
is a two byte identification code, transmitted
after the power-up self-test
(refer to section 7.5.4.3). It is
also sent on request from the system module (refer to section
7.5.5.3).
KEY DOWN ON POWER
pressed on power up.

ERROR

CODE

-- indicates that a key was

POWER UP SELF-TEST ERROR CODE -- indicates to the system module
that the ROM or RAM self-test of the system module failed (refer
to section 7.5.4.3).

7-28

7.5.4.3 Power Up Transmission
Upon powerup,
the keyboard
performs a self-test in less than 70 ms, then transmits the
self-test results to the system module in 4 bytes.
Byte 1

KBIO
(firmware)
This is the keyboard
identification (IO) stored in the firmware

Byte 2

KBIO
(hardware)
This
read from hardware jumpers

Byte 3

ERROR
Two error codes indicate either the
failure of the ROM or RAM self-test within the
processor
(3E hexidecimal) , or a keydown on
powerup
(3D
hexidecimal) •
No
error is
indicated by 00.

Byte 4

KEYCOOE
This byte contains the first
keycode detected if there was a key pressed on
powerup. No error is indicated by 00.

is the keyboard IO

If the ROM self-test (CHECKSUM) fails and the error is critical,
the keyboard is unable to transmit. Noncritical errors let the
keyboard continue operating.
If the keyboard finds a key pressed on the first scan, it
continues to look for an ALL UPS condition. The keyboard sends the
corrected four-byte power-up sequence when the pressed key is
released.
This avoids a fatal error condition if a key is pressed
by mistake while powering up.
The keyboard LEOs are lit during the power-up self-test. If the
self-test passes, the keyboard turns the LEOs off. If a bell is
selected on powerup, the system module can transmit a sound bell
command to the keyboard. However, this should not be done until
the system module receives the last byte of the four-byte
sequence. The request for self-test tests the serial line and
system module connection. The power-up self-test takes 70 ms or
less.
The system module can request a jump to powerup at any time. This
causes the LEOs on the keyboard to blink on and off (for the
power-up self-test) •
7.5.5

System Module to Keyboard Protocol

The system module controls both the peripherals associated with
the keyboard and the keyboard transmit characteristics. Figure
7-11 shows the protocol for command and parameter transmission
from the system module to the keyboard.

7-29

COMMAND
07

REPRESENTATION

PARAMETERS
DATA

I I

DATA
MA-0178-82

Figure 7-11

System Module to
Keyboard Protocol

7.5.5.1 Commands
There are two kinds of commands, commands
that control keyboard transmission characteristics and commands
that control keyboard peripherals. The low bit of the command is
the TYPE flag.
The TYPE flag is clear if the command is a
transmission command, and set if the command is a peripheral
command.
Transmission Commands

Peripheral Commands

Mode set

Flow control

Autorepeat rate set

Indicator
Audio
Keyboard ID
Reinitiate keyboard
Some autorepeat control
Jump to test mode
Reinstate defaults

The high order bit of every command is the PARAMS flag. If there
are any parameters to follow, the PARAMS flag is clear. If there
are no parameters to follow, the PARAMS flag is set.
7.5.5.2 Parameters
The high order bit of every parameter is
the PARAMS flag.
This flag is clear if there are parameters to
follow, and set on the last parameter. The remaining seven bits of
the parameter are for data.

7-30

7.5.5.3 Peripheral Commands
The following two commands can
turn the data flow from the keyboard off and on.
•

Inhibit Keyboard Transmission -- This command shuts off
or locks the keyboard and turns on the keyboard locked
LED.
After receiving the inhibit command, the keyboard
sends a special command to the system central processor.
If the system central processor receives this code
without requesting it, this indicates that noise on the
line was interpreted as the inhibit command. The central
processor then responds immediately with the resume
keyboard transmission command.

•

Resume Keyboard Transmission -- This command turns on or
unlocks the keyboard and turns off the keyboard locked
LED.
If any keystrokes are lost, the keyboard responds
with an error code.

Each keyboard LED can be turned on and off.
The following eight commands control the keyclick and bell sounds.
Disable keyclick
Enable keyclick and set volume
Disable CNTL keyclick
Enable CNTL keyclick
Sound keyclick
Disable bell
Enable bell and set volume
Sound bell
The following four
autorepeat mode.

commands

are

control over the

•

Temporary Autorepeat Inhibit -- stops autorepeat for a
specific key only. It resumes automatically when another
key is pressed.

•

Enable Autorepeat Across the Board -- starts transmission
of metronome codes without affecting autorepeat timing or
keyboard division.

•

Disable Autorepeat Across the Board -- stops transmission
of metronome codes without affecting autorepeat timing or
keyboard division.

•

Change All Autorepeat to Down Only
changes
keyboard autorepeating divisions to down only mode.

7-31

all

The following are three other miscellaneous commands.
•

Request Keyboard ID -- causes the keyboard to send the
two byte ID
(firmware and hardware). The keyboard does
not jump to the power-up sequence.

•

Reinitiate Keyboard -- causes the keyboard to jump to the
power-up sequence. Transmission to the keyboard should be
held until the host processor receives the last byte of
the power-up self-test.

•

Reinstate Defaults
sets the following functions back
to the default settings after a successful power-up
self-test.
Division mode settings
Autorepeat interval and timeout rates
Autorepeat buffer selections
Audio volume
Control key keyclick

To send a peripheral command, set the TYPE flag (low order bit).
Bits six -- three contain a command representation from the chart
below. Bits two and one specify on (01), off (00), or sound (11).
Bit seven should be set if there are no parameters to follow.
Table 7-4 lists the peripheral commands (in hexidecimal) •
Command

Representation

Flow control
Indicator (LEDs)
Keyclick
Bell
Keyboard ID
Keyclick for CNTL key
Temporarily inhibit autorepeat
Jump to test mode
Change all autorepeat characters to down only
Enable/disable autorepeat

0001
0010
0011
0100
0101
0111
1000
1001
1010
1100

The Jump to power-up command is FD hexidecimal.

7-32

Table 7-4

Peripheral Commands in Hexidecimal

Function

Hex

Parameters

8B
89

None
None

13
11

Bit pattern
Bit pattern

99
lB
B9
BB
9F
Al

None
Volume
None
None
None
None
Volume
None

Flow control
Resume keyboard transmission
Inhibit keyboard transmission
Indicators
Light LEOs
Turn off LEOs
Audio
Disable keyclick
Enable click, set volume
Disable CTRL keyclock
Enable CTRL keyclick
Sound keyclick
Disable bell
Enable bell, set volume
Sound bell

Autorepeat
Temporary autorepeat inhibit
Enable autorepeat across keyboard
Disable autorepeat across keyboard
Change all autorepeat to down only

Cl
E3

El
09

None
None
None
None

Other
Request keyboard 10
Jump to power up
Jump to test mode
Reinstate defaults

AB
FD
CB
03

7-33

None
None
None
None

The following are some of the peripheral commands.
•

Flow Control -- The system module can lock the keyboard
with the inhibit keyboard transmission command. When the
keyboard is unlocked, it responds with an error code if
any keystrokes were missed (refer to section 7.5.6.2).

•

Indicators (LEOs) -- Figure 7-12 shows the LED parameter.
Figure 7-13 shows the LED layout on the LK201 keyboard.

•

Audio -- Figure 7-14 shows the audio volume parameter.

MA-0179-82

Figure 7-12

Indicator (LED) Parameter

LED 4

LED 3

LED 2

LED 1
MA-0176-82

Indicator (LED) Layout

Figure 7-13

I I

I I I BI~ VOL~ME
0

MA-0177-82

Figure 7-14

7-34

Audio Volume Parameter

The audio has the following volume levels.
000 -- highest
001
010
011
100
101
110
111 -- lowest
Either keyclick or bell
(or both)
can be disabled. When the
keyclick or bell is disabled,
it does not sound, even if the
system module requests it.
The following are additional peripheral commands.
•

Temporary Autorepeat Inhibit -- Stops autorepeat for this
key only. Autorepeat automatically continues when another
key is pressed.

•

Disable/Enable Autorepeat Across Keyboard -- stop/start
metronome code transmission without affecting autorepeat
timing or division settings.

•

Change All Autorepeat to Down Only -- changes division
settings for all autorepeating divisions to down only.

•

Request Keyboard IO -- causes keyboard to send a two-byte
keyboard ID. Keyboard does not jump to powerup.

•

Reinitiate Keyboard
causes keyboard to jump to its
powerup routine. The system module should not try to
transmit anything to the keyboard until the last byte of
the power-up sequence is received.

•

Jump To Test Mode
production test.

•

Reinstate Defaults -- sets the following functions back
to the default settings after a successful power-up
self-test.

special

Division mode settings
Autorepeat interval and timeout rates
Autorepeat buffer selections
Audio volume
Control key keyclick

7-35

test

mode

for

7.5.5.4 Mode Set Commands -- This section describes the mode set
commands. This section does not provide information about division
mode settings. Refer to section 7.5.2 for an explanation of
transmission modes and rates.

•

Each division on the keyboard has a unique four-bit
representation
(refer to section 7.5.1). Table 7-2
describes these representations.

•

Each mode has a unique two-bit code .

Modes

Representation

Down only
Autorepeat down
Down/up

00
01
11

To set the key transmission mode on a particular keyboard
division,
the system module must send the PARAMS flag, then the
keyboard division representation with the mode code, and then the
TYPE flag (cleared).
Figure 7-15 shows a set main array to down/up.
The PARAMS flag is set to one if there are no parameters. The
PARAMS flag is clear if there are parameters.
Autorepeat Rate Buffer Association
If autorepeat mode is
selected, the system module can transmit a parameter to change the
buffer association of the selected division. Refer to section
7.5.2.3 for autorepeat rates and section 7.5.7 for default
values.
Figure 7-16 shows a set main array to autorepeat, changing buffer
association to buffer 3.
Autorepeat Rate Buffer Values -- At keyboard power-up time, the
four autorepeat rate buffers contain default values (refer to
section 7.5.2.3 for autorepeat rates and section 7.5.7 for
defaults). The system module may change these values.
In the command byte,
six
three are
command), bits two
bit zero (TYPE flag)

bit seven (PARAMS flag) should be clear, bits
1111
(to indicate that this is a rate set
and one should be the buffer number (0 -- 3),
is clear.

There should be two parameters carrying the rate set data.
Figure 7-17 shows change rates in buffer 3.

7-36

03
1

I
J

PARAM

02
1

01
1

'--v------' I
MODE

DIVISION

TYPE
MA-0180-82

Figure 7-15

PARAM

Set Main Array to
Down/Up Example

DIVISION

MODE

TYPE

0
1

MA-0181-82

Figure 7-16

Set Main Array to
Autorepeat Example

RATE CHANGE
COMMAND

PARAM

,...-A----,r,_ _ _ _A'-_ _
07
0

06
1

BUFFER NO. TYPE
~)~

I I I I I I
1

PARAMETER 1 (TIMEOUT)

PARAMETER 2 (INTERVAL)

MA·0182·82

Figure 7-17

7-37

Change Ra tes in
Buffer 3 Example

The first parameter specifies the timeout to the store in the
selected buffer. The second parameter specifies the interval.
(Refer to section 7.5.2.1 for definitions of these parameters.)
For example, to set the autorepeat rate in buffer one, the system
module firmware transmits 00000011 followed by two bytes of
numeric parameters.
The autorepeat timeout is the transmitted number times 5 ms. To
specify a rate of 5 ms delay, the first parameter received is
00000001.
The maximum allowable time is 630 ms (01111110). The
system module must not send 635 (01111111).
NOTE
This code (635) is reserved for internal
keyboard use. 00 is an illegal value.
Autorepeat timeout is implemented as a multiple of 8.33 ms (the
keyboard's internal scan rate). Timeout rates can vary ~ 4.15 ms.
The autorepeat interval is the number of metronome codes per
second. in order to specify a speed of 16 Hz, the second parameter
received is 10010000. note that the high order bit is set because
it is the last parameter. the highest value which may be sent is
124 (11111100).
The lowest rate which can be implemented by the keyboard is 12 Hz.
values as low as 1 can be transmitted, but are translated to 12
Hz.
The system
(11111101) •
command.
7.5.6

NOTE
module must not send 125
This code is the power-up

Special Considerations

This
section
considerations.

describes

the

special

codes

and

rela ted

7.5.6.1 Error Handling -- There are four error codes. The first
two are sent at powerup if the self-test fails (refer to section
7.5.4.3). The other two codes are the INPUT ERROR code and the
OUTPUT ERROR code.

The OUTPUT ERROR
(B5 hexidecimal)
is sent after the keyboard
receives a resume transmission
command, if the output buffer
overflowed while the keyboard was locked.
The INPUT ERROR (B6 hexidecimal) is sent when the keyboard detects
noise (unidentified command or parameter) on the line. B6 is also
sent if the keyboard detects a delay of more than 100 ms when it
expects a parameter.
7-38

7.5.6.2 Keyboard Locked Condition -- When the keyboard receives
an inhibit transmission command,
it lights the LOCKED LED and
transmits one more byte. This is a special code that indicates the
keyboard is locked
(KEYBOARD LOCKED ACKNOWLEDGE). If the system
module receives this code without a request, the code indicates
that noise on the line was interpreted as an inhibit transmission
command. The system module should immediately send the resume
transmission command to unlock the keyboard.
The output first in the first out (FIFO) buffer in RAM is four
bytes. When the keyboard is locked it attempts to store characters
received from the keyboard. The keyboard stops scanning its
matrix. When the keyboard is unlocked by the system module, it
transmits all four bytes in the output buffer. If any keystrokes
have been missed due to buffer overflow, the keyboard transmits an
error code as the fifth byte (OUTPUT ERROR). Any keys that were
not transmitted and are being pressed when the keyboard is
unlocked are processed as new keys. An error code upon unlocking
the keyboard indicates a possible loss of keystrokes to the system
module.
The keyboard stops scanning its matrix when its buffer is full.
However, it processes all incoming commands.
7.5.6.3 Reserved Code -- The number 7F (hexidecimal) is reserved
for the internal keyboard input and output buffers that handle
routines.
7.5.6.4 Test Mode
The keyboard jumps into a test mode by
command during production test. The keyboard transmits a special
code to the system module to confirm the test mode. If the system
module
receives
this
code,
it should send the byte 80
(hexidecimal) to continue. This causes a jump to power up.
7.5.6.5
use as
codes.

Table 7-5

Future Expansion -- Some keycodes are reserved for future
special codes or keycodes. Table 7-5 lists these reserved

Keyboard Division Default Modes

Keyboard Division

Mode

AR Buffer

Main array
Keypad
Delete
Cursor keys
Return and tab
Lock and compose
Shift and control
Six basic editing keys

Autorepeat
Autorepeat
Autorepeat
Autorepeat
Down only
Down only
Down/up
Down/up

o
o

7-39

1
1

7.5.7

Default Conditions

The LK201 has the following default conditions.
•

Certain keyboard divisions have specific default modes.
Some divisions default to the autorepeat mode. Therefore,
they have an associated buffer that contains the default
values for timeout and interval. Timeout is the amount of
time
that
the
keyboard waits before starting to
autorepeat a character. The rate of autorepeating a
character is called the interval. Table 7-5 shows the
default modes and Table 7-6 shows the default rates in
the four keyboard division autorepeat rate buffers.

•

The volume levels for the keyclick and bell have an
eight-step range. The default volume levels for the
keyclick and bell are the third loudest.

•

For the LK201 keyboard, the CNTRL (control) key defaults
to the no keyclick state.

Both keyclick and bell volumes are two
7.5.7.1 Audio Volume
by default. The key in position C99 of the
decima 1
(010 binary)
keyboard
(the CNTL key in the LK201) does not generate a click
unless enabled by the system module. The keys in position B99 and
Bll (SHIFT keys on the LK201) never generate a keyclick.

Table 7-6

Defaul t Ra tes in Autorepeat Buffers

Buffer
Number

Timeout
(ms)

Internal
(Hz)

0
1
2
3

500
300
500
300

30
30
40
40

7-40

SPECIFICATIONS

7.6

Functional
Electronics

8-bit microprocessor, 4 KB of ROM, 256
bytes of RAM, 4 LEOs, transducer

Cord

1.9 m (6 ft) coiled, 4-pin
telephone-type modular connectors,
plugs into display monitor (PN BCC01)

Keypad

Sculptured key array

Home row key height

30 mm (1.16 in) above desk top

Keys

105 matte textured finish keys

Main keypad

57 keys

Numeric keypad

18 keys

Special function keypad

20 keys, firmware and software driven

Editing keypad

10 keys

Spacing

1.9 cm (0.75 in) center to center
(single width keys)

Wobble

Less than 0.5 cm (0.020 in)

Diagnostics

Power-up self-test, generates
identification upon passing test

Physical
Height
Length
Width
Weight

5 cm (2.0 in) at highest point
5 3 . 3 cm ( 2 1 in)
17.1 cm (6.75 in)
2 Kg (4.5 1 b)

7-41

CHAPTER 8
MONOCHROME MONITOR

8.1

GENERAL

This chapter
Figure 8-1).

describes the VR201 monochrome monitor (shaded area
NOTE
This manual does not describe the VT241
color monitor. Refer to the list of
related documents in the introduction to
this manual to identify VR241 documents.

SYSTEM BOX

LOGIC

/ ' VIDEO
/
LOGIC

_ _ ..L. / _ _ _ _ _

SYSTEM
COMMUNICATION

EIA
HOST
PORT

PRINTER
PORT

20 rnA
PORT

INTEGRAL

OPTIONAL
HOST
COMMUNICATIONS

MONITOR
(VR201 OR VR241)

MA-0054-84

Figure 8-1

VT240-Series Terminal System
Block Diagram
8-1

The
VR201 monochrome monitor is a raster scan device for
displaying alphanumeric and graphic video information. It provides
a video display dependent on the composite video signal input from
the video logic in the system box.
8.2

PHYSICAL DESCRIPTION

The VR201 monochrome monitor is enclosed in a wedge-shaped
cabinet. The CRT face provides a 12.7 X 20.3 cm (5 X 8 inches)
viewing area on a screen that measures 30.5 cm (12 inches)
diagonally.
A plastic button covers a screw on the cabinet rear.
This screw holds the cabinet to the internal wire frame. The CRT
and the monochrome monitor module are mounted inside this frame.
The frame has a metal shield and a metal finger stock that presses
against the screw mounting bracket. This shield covers the entire
inside of the cabinet to prevent electromagnetic radiation. A
folding carrying handle is on the bottom rear of the cabinet.
The glass front of the monitor, the CRT face, is specially treated
to reduce glare.
The monitor viewing angle is adjustable between +5 to -25 degrees.
To adjust the angle, the operator pushes a release button on the
right side (Figure 8-2). This causes a friction-lock foot to lower
from the bottom of the cabinet housing.
The contrast and brightness controls are on the rear panel. Two
connectors, Jl and J3, are on the rear of the monitor. Jl is a
IS-pin D-type connector that connects to the system box with a
cable
(PN BCC02). J3 is a modular telephone jack that connects to
the keyboard with another cable (PN BCC02).
The monochrome monitor has the following dimensions.
Height
Width
Depth
Weight

24.38 cm (9.75 in)
29.33 cm (11. 73 in)
30.57 cm (12.23 in)
6.6 kg (14.5 lb)

8-2

_ - : - - : - - : - - CRT FACE

CABINET

:....,;;;~-J3

J1
CONTRAST

BRIGHTNESS

FRICTION LOCK
RELEASE

Figure 8-2

FOLDING HANDLE

FOOT

MA 10,500

Monochrome Monitor Exterior View

8-3

8.3

FUNCTIONAL OVERVIEW

The VR201 monochrome monitor consists of two main components: a
12-inch diagonal CRT with a yoke assembly mounted on it, and an
electronics module (Figure 8-3).
The monitor's primary function is to display.
The monitor's
secondary function is to route information between the system box
and the keyboard. The keyboard connects with the monitor via J3
(Figure 8-3). J3 is hardwired on the module to Jl, which connects
to the system box.
The monitor module controls the CRT and the yoke assembly. A
composite video signal is input to the module from the system box
(Figure 8-3). This signal consists of two types of information:
video data
(refer to section 8.3.1), and sync data (refer to
section 8.3.2).
The monitor module provides the following power to the CRT.

•
•
•
•
•
•

Anode vol tage
Grid 1 vol tage (br ightness)
Grid 2 vol tage ( cutoff)
Grid 4 vol tage ( focus)
Heater voltage
Ca thode vo 1 tag e

The control inputs to the CRT refine the electron beam. The anode
voltage attracts the beam to the faceplate and provides a single
connection between the CRT and the module
(Figure 8-3). Pl
provides all other CRT inputs. Pl is mounted directly on the CRT
and is hardwired to the module. Refer to section 8.7.7 for more
information.

TO/FROM
SYSTEM BOX

MA 10,231

Figure 8-3

Monochrome Monitor Block Diagram

8-4

8.3.1

VIDEO Data

The monitor module uses the video portion of the signal to
generate outputs to the CRT cathode. The CRT responds to the video
by generating various intensities in the electron beam. The
intensity of the beam depends on the amplitude of the video signal
provided.
8.3.2

SYNC Data

The sync portion of the video synchronizes the generation of
horizontal
and vertical signals to the yoke assembly. The
horizontal and vertical processor chips use peak detector circuits
to separate the synchronizing signals. The yoke assembly, which
connects
to
the
electronics
board
via J2, consists of
electromagnetic coils
(Figure 8-3). These coils use the signals
output by the module to generate magnetic fields which position
the electron beam generated by the CRT. The horizontal signal to
the yoke controls the sweep of the electron beam horizontally
across the faceplate
(each sweep is called a scan line). The
vertical signal controls the positioning of the beam to a new scan
line for vertical positioning.
8.4

MONOCHROME MONITOR SYSTEM COMMUNICATION

The monochrome monitor connects with both the system box and the
keyboard. The system box connects to the monitor via Jl, a IS-pin
D-type subconnector. The keyboard connects via J3, a modular
telephone jack.
Jl has three basic functions: supply video input used only at the
monitor, supply operating voltages used by both the monitor and
the keyboard, and transfer keyboard data
(Figure 8-4). The
operating voltage and keyboard data lines are hardwired from Jl to
J3 on the electronics board.
Table
8-1 provides a pin-out for Jl that includes signal
identifications and functional descriptions. Table 8-2 provides
the same information for J3.

8-5

~~ECTRONICS

M VIDEO

TO/FROM{

~~20VUDNCD

SYSTEM

GROUND

BOX

DATA SEND

~-----r-. }

GOARD
CIRCUITS

~--+----..

DATA RECEIVE

DATA RECEIVE
DATA SEND

TO/FROM
KEYBAORD

,...:..:H0:...2V~D~C_ _---l

{

GROUND

MA-10,113

Figure 8-4

Table 8-1

Monochrome Monitor System
Communications Diagram

J1 Pin-out

pi n (s)

Signal

Description

1--3

Not used

None

Ground

Video signal ground potential

5,6

Ground

Operational voltage ground potential

7,8

+12 Vdc

Operational voltage input

9--11

Not used

None

M Video

Composite video (refer to section
8.3.1)

Ground

Tied to pins 5 and 6

Da ta Receive

Serial data line from the keyboard
output to the system box (via J3)

Data Send

Serial data line from the system box
output to the keyboard (via J3)

8-6

Table 8-2

J3 Pin-out

Signal

Description

Data Send

Serial data line for output from the
system box to keyboard (via Jl, pin 15)

+12 Vdc

Output of operational voltage to keyboard
(from Jl, pins 7 and 8)

Ground

Operational voltage ground potential
(from Jl, pins 5, 6, and 13)

Data Receive

Serial data line for input from keyboard
to system box (via Jl, pin 14)

8.4.1

Composite Video Signal

The video input to the monitor is a composite of two types of
signals,
video
and
sync.
There are different levels of
illumination within the video signal, ranging from totally black
to maximum brightness.
Figure 8-5 represents a
typical composite video signal and
identifies the major terms associated with it. This signal, used
with the monochrome monitor,
is dc-coupled to ground at the
monitor module. Table 8-3 lists typical signal values.
Figure 8-6 shows the composite video signal and the sync portion
of this signal. Table 8-4 describes the values for the sync
components identified.

REFERENCE W H I T E - - - - - - - - - - - - - - - - -

REFERENCE B L A C K - - - - BLANKING L E V E L - - - - - - -

SYNC LEVEL- - - - - - - - - ' - - - - - 1 - - - - - - - - -

Figure 8-5

Composite Video Signal Representation

8-7

Table 8-3

Composite Video Values

Characteristics

Value

Output impedance

75 ohms, dc coupled to 0 V

Amplitude

1.0 V peak-to-peak nominal (monitor accepts
signals with peak-to-peak values of 0.9 V
through 1.5 V)

Reference black

Low limit of display value. It equals 30
percent of peak-to-peak value (0.3 V
nominal), and is lowest voltage value
amplified linearly at the electronics board.

Reference white

High limit of display value. It equals 100
percent of peak-to-peak value (1.0 V
nominal), and is highest voltage value
amplified linearly at the electronics board.

Blanking level

Voltage value which reduces CRT electron beam
current below cutoff.

Sync level

Voltage level at which sync actions can take
place; 0 V nominal (dc coupled video to
ground) •

Continuous input

+2.0 V maximum (2.0 V saturates the video
amplifier unless the contrast thumbwheel
adjustment is reduced).

8-8

EVEN FIELD:

60 Hz NON~INT

22 SCANS}

50 Hz INT

74 SCANS

~g ~~ ~NOTNINT :;~ ~g~~~

I+-_ _ _ _V_E_R_T_IC_A_L_B_L_A_N_K_IN_G_I_N_T_E_R_V_A_L____

----I

{

LAST DISPLAYED SCAN OF
PREVIOUS FIELD

1.0 V

{

FIRST OF 240 DISPLAYED
SCANS IN EVEN FIELD

60 Hz NON~INT = 2 SCANS
60 Hz INT
= 2 SCANS
50 Hz NONINT = 25 SCANS
50 Hz INT
= 24 SCANS

Inn 1--~---

:\;\

TIME _ _

I
:

ODD FIELD:

START OF
EVEN FIELD

: VERTICAL BLANKING INTERVAL

LAST DISPLAYED SCAN OF

FIRST OF 240 DISPLAYED
SCANS IN ODD FIELD

~--------+----------------------------+

EVEN F I E L J A A

{60 Hz INT

50 Hz I NT

10 V

., ,

'lrLJin1+------

2.5 SC,;NS
24.5 SCANS

VERTICAL INTERVAL

-----~

I--

!\n

TIME_

START OF
ODD FIELD

H PERIOD

63.56

.01%

NOTES
IN NON~INTERLACED OPERATION THE
EVEN FIELD IS REPEATED CONTIN~
UOUSLY AND THE ODD FIELD IS NOT
USED
IN THE INTERLACED OPERATION THE
EVEN FIELD ALTERNATES WITH THE ODD
FIELD

H BLANK {11.84 ~s ± 50 ns /80 COLUMN
12.34~s±50ns / 132 COLUMN

BLACK
SYNC

.29 V _
0.00-

~ U ------1.1,u~·f~U

.-------, .-------,

,..-1--1

~ 1.54 ~s ± 50 ns $~
l
H SYNC
4.71
± 50ns

FRONT PORCH

ALL FIELDS CONTAIN 240 DISPLAYED
SCANS

~Q ~ 2.33 ~s ± 50 ns -.J I-

H PERIOD ~ 63.56 ~s ± .01%

Figure 8-6

Composite Video Sync Timing Diagram

8-9

~I_~n

-1

I-V SYNC

~ 27.28 ~s

± 200 ns

Table 8-4

Composite video Sync Component

Component

Description

vertical blanking
interval

Period of time vertical retrace activity
blanks the screen. Vertical retrace
completes in less than 1.0 ms, and within
an allowed frequency range of 49 -- 61 times
per second.

V Sync

Period of time the vertical deflection
circuitry on the electronics board takes to
synchronize the next frame.

H Sync

Time the horizontal deflection circuitry on
the electronics board takes to synchronize
for retrace.

H Period

Period of time for the horizontal scan
plus horizontal blanking (63.5 -s)

Equalizer pulse that synchronizes vertical
deflection circuitry on electronics board
for vertical retrace activity.

Front porch

Delay value between start of blanking and
start of sync pulse.

vertical interval

Period of time the actual synchronizing of
the vertical deflection circuitry on the
electronics board takes place. Consists
of six EQ pulses, six V sync pulses, and
six more EQ pulses.

8.5

CRT

The CRT provides the final video output, an electron beam, fired
at a phosphor-coated faceplate.
Electron beam generation is controlled directly by the monitor
module inputs. The module controls the yoke, which in turn
controls positioning the beam at the faceplate.
The CRT contains an electron gun. The gun consists of the heater
element, a cathode, three grids (Gl, G2, and G4), an anode, and
the faceplate, all encased in a vacuum.
The three grids control the beam generated by the gun, Gl for
brightness, G2 for beam cutoff and G4 for focus.

8-10

Gl is directly affected by the brightness control thumbwheel. This
lets operator adjust the background intensity of the display. G2
provides video sharpening capabilities. To do this, G2 acts as a
gate, or valve, to the electron beam. A voltage, provided to G2,
prevents the electron beam from passing to the faceplate unless
the beam is a specific minimum intensity. G4 focuses the electron
beam.
The CRT plugs directly into Pl which is hardwired onto the module.
Through Pl,
the operating voltages for the heater element, the
cathode, and the three grids are provided. The anode voltage is
provided by a separate connection between the module and the CRT.
Its ground goes to the CRT case. This ground reduces shock hazard
and consists of three parts: a connection between the module and a
terminal block on the yoke, a connection between the block and the
CRT case, and a connection between the block and Pl.
8.6

YOKE

The yoke is a set of electromagnetic devices mounted on the CRT
neck. One device is for horizontal deflection of the electron
beam, the other is for vertical deflection.
Currents to control the horizontal scan line are applied to the
yokels coil
(inductance)
through the width inductor and the
linearity inductor. The vertical trace control current comes from
the vertical processor chip.
The yoke connects to the electronics board through J2: pins two
and three for the horizontal deflection magnetic coils, and pins
one and four for the vertical.
8.7

MONITOR MODULE

The monitor module is made of discrete analog components. It can
be divided into seven circuits to control the CRT and yoke.
Figure 8-7 is a block diagram of the module that shows the seven
circuits. The figure also identifies the fuse for the power input
(Fl)
and three connectors (a fourth connector, J3, which routes
signals between Jl and the keyboard is not shown). The following
sections describe each item shown in Figure 8-7.

8-11

FROM {
SYSTEM
BOX

TO
CRT
+lQ3VDC

ANODE

TO
YOKE
ASSEMBLY

MA-10,114

Figure 8-7

8.7.1

Monitor Module Block Diagram

Dynamic Focus

This circuit creates different focus voltages for different areas
on the screen. Output from this circuit is tied to focus biasing
circuitry within the grid bias circuit. This output offsets focus
biasing based on horizontal and vertical deflection values. The
circuit is primarily a single transistor which acts as a mixer for
parabolic inputs from the horizontal and vertical deflection
circuits. This changes focus biasing as a function of the position
of the beam on the tube.
8.7.2

Grid Bias

This circuit generates CRT biasing values: focus (G4), cutoff
(G2), and brightness (Gl). These voltages are developed from the
flyback transformer. Voltages from this transformer are routed to
the G4 and G2 circuits. There are two resistor networks that each
contain potentiometers for adjusting the bias in question, R43 for
G4 (focus) or R120 for G2 (cutoff). The remaining bias circuit, Gl
(brightness), is a resistor network between two voltage sources,
+40 Vdc and -150 Vdc. This adjustment allows the operator to
adjust the display background intensity. The voltage on Gl is
adjustable from approximately 0 to -47 Vdc.

8-12

8.7.3

Horizontal Deflection

This
circuit
drives
the
CRT
beam across the faceplate
horizontally. This circuit contains the following elements.
•

A horizontal processor

•

A sync buffer circuit

•

A horizontal driver and output

•

RC networks that bias circuits internal to the horizontal
processor

•

A horizontal deflection generator output stage (width and
linearity inductors, horizontal output transistor, damper
diode, retrace capacitor, and yoke inductor)

An
oscillator
within
the horizontal processor allows the
horizontal deflection circuit to free run. The sync pulses then
synchronize the operating running rate to the video input.
The sync buffer circuit amplifies the sync pulse and then applies
it to the horizontal processor. When the horizontal output turns
off, the electron beam flies back, returning the beam to the left
of the screen. At the end of retrace, the conducting of the damper
diode establishes a ramp of current in the yoke inductor. To make
sure the output transistor is turned on at the proper time, the
horizontal deflection IC also provides the correct timing on its
output pulse. This allows the current ramp to continue after the
damper diode stops conducting. The width coil portion of the
output stage adjusts the width of the display. Two of the RC
networks
contain potentiometers for adjusting their biasing
values: R2l1 for hold (horizontal) and R218 for centering (phase).
A secondary output from the generator is provided to the vertical
deflection circuitry as a vertical sync signal.
8.7.4

Linear Regulator

This circuit provides power to the flyback transformer during
initial powerup and also regulates the input voltage. During
initial powerup, the +12 Vdc voltage is applied to the regulator.
The voltage input (rising from 0 V to +12 Vdc) is shunted through
a series of 4 diodes and then through the flyback transformer.
This generates 40 Vdc at the input of L300 to the regulator field
effect transistor (FETs) sources. The FETs are then turned on and
conduct the load current instead of the diodes. A precision zener
diode plus the regulator transistor's VBE cause the circuit to
provide 10.3 Vdc regulated output.

8-13

8.7.5

Vertical Deflection

This
circuit
positions the CRT beam across the faceplate
vertically. This ciruit contains the following elements.
•

A vertical processor

•

Various RC networks
vertical processor

•

An output filter network.

that bias circuits internal to the

An oscillator within the vertical processor allows the vertical
deflection circuit to free run. The sync pulses synchronize the
vertical deflection to prevent vertical roll.
Three of the RC networks contain potentiometers for adjusting
biasing values: R48 for hold (vertical), R50 for height, and R53
for linearity.
At the beginning of each refresh cycle, the
vertical processor receives a vertical sync pulse from the
horizontal processor circuit. The horizontal processor detects the
vertical sync pulse and sends it to the vertical processor. This
sync pulse comes from the composite video input to the monitor
module. The vertical sync pulse causes the beam to fly back
vertically and begin a new frame.

8.7.6

Video Amplifier (Amp)

The video amp consists of an input and output stage. The video
signal is applied to an input push/pull transistor network which
is part of an encapsulated transistor array. The input is provided
from R5,
the contrast thumbwheel potentiometer. The operator can
adjust the potentiometer for personal contrast preference. The
potentiometer, Rl19, provides a preamplifier adjustment to preset
the range that can be affected by the contrast thumbwheel. Biasing
the input stage affects biasing the output stage, which is another
transistor network. The more positive the input to the input
stage, the more positive the output from the transistor network.
This output is provided to the video output stage.
The video output stage provides the operating voltage for the CRT
beam. The video output stage uses the voltage from the flyback
transformer
(40 Vdc)
to generate its output. The sync pulses
(horizontal and vertical)
set the video output to or below the
cutoff voltage so the operator does not see the retrace lines.
Applying increased positive video amp signal decreases output to
the CRT. This also increases the intensity of the CRT display.

8-14

8.7.7

Flyback Transformer

The flyback transformer is the high voltage power supply and is
synchronized to horizontal deflection. The transformer generates
the voltages used by the grid bias circuit (Gl, G2, and G4), the
anode voltage
(12.5 kV nominal), and the 40 Vdc voltage used by
the linear regulator and video amplifier.
WARNING
The monochrome monitor contains shock
hazard voltages. Use extreme caution
when servicing the monitor.
There is a high voltage (12 kV nominal)
on the anode lead and the anode cup on
the side of the CRT.
To
avoid
shock, use the following
procedure when discharging the anode.
1.

Turn off system power and connect
the monitor cable.

Attach the clip lead of the anode
discharge tool to the metal frame.

Hold
the tool by its insulated
handle. Using one hand, carefully
slide the tip of the tool under the
plastic anode cap until it touches
the
anode.
Avoid scratching or
poking the glass CRT envelope.

Once discharged, remove the tool and
clip lead.

There is also 700 Vdc on the monitor
module near the flyback transformer. Use
caution when performing adjustments in
this area. This area is covered with a
protective shield.
CAUTION
Before
removing
the
system module
monitor cable, turn off system power.
Static discharge in the CRT can damage
the
monitor
module and/or keyboard
electronics.
Make sure the system power is off before
connecting
or
disconnecting
the
monitor's cable for service or to move
the

8-15

the
monitor.
When
performing
adjustments, secure the monitor's cable
to the monitor with its thumbscrews so
the cable does not loosen.
If you do not follow this procedure, you
can
damage
monitor and/or keyboard
components.
8.7.8

This connector provides the
electronics board. Refer to
signal descriptions.
8.7.9

voltage and video signals to the
section 8.4 for the Jl pin-out and

This connector provides the horizontal and vertical deflection
currents between the electronics board and the yoke assembly. It
is a four-pin connector. Pins one and four are used for vertical
deflection, pins two and three are used for horizontal deflection.
8.7.19

This connector mounts on the electronics board that the CRT plugs
into. Figure 8-8 shows the PI pin-out.

TO GRID 1
VIDEO

+12 VDC
GROUND RETURN

TO BEAM
TO HEATER
FROM HEATER

TO GRID 2
TO GRID 3

MA·l0,115

Figure 8-8

Monitor Module PI Pinout

8-16

CHAPTER 9
POWER SUPPLY

9.1

GENERAL

The system box power supply (shaded area in Figure 9-1) converts
ac input to the dc voltages required by the logic board.

SYSTEM BOX

LOGIC

/ / VIDEO
/
LOGIC

_ _ ..L / _ _ _ _ _

SYSTEM
COMMUNICATION

EIA
HOST
PORT

PRINTER
PORT

20 rnA
PORT

INTEGRAL

OPTIONAL
HOST
COMMUNICATIONS

MONITOR
(VR201 OR VR2411

MA·Q054-84

Figure 9-1

VT240-Series Terminal System
Block Diagram

9-1

9.2

MAJOR CIRCUITS/COMPONENTS

The power supply (Figure 9-2) consists of various components and
circuits, including circuits physically mounted on the logic
board. The power supply has the following major circuits and
components.
•
•
•
•
•
•
•

AC input and fan components.
Power supply 1 (PS1)
DC power input connector (Jl)
+5 V input circuit
+12 V input circuits
-12 V input circuit
DC power Okay

+5V
INPUT
CI RCUIT

P.S.1

+12V
INPUT
CI RCUITS

-12V
INPUT
CIRCUITS

+12V
+12VC

-12V
+5.1V

ACINPUT
AND FAN
COMPONENTS
DC
POWER
OK

FROM
AC
SOURCE
LOGIC
BOARD
MA-0397-84

Figure 9-2

Power Supply Block Diagram

9-2

9.2.1

AC Input And Fan Components

The ac input components provide for ac input, including voltage
range selection (115 Vac or 230 Vac) , while the fan (Bl) provides
neccessary cooling for the PSI (refer to section 9.2.2).
The AC input and
following items.

fan

components

(Figure

9-3) consist of the

•

Fan Assembly -- includes the fan (Bl, a +12 Vdc powered
device) and connector Pl.

•
•

provides PSI connector for fan assembly.

provides the voltage selection switch.

•

S2
provides the power on/off switch that connects ac
input to the PSI
(via the PSI LN connector, a two-pin
quick disconnect jack).

•

F2 -- provides a 3 amp, 250 Vac input line fuse.

I~----,
FAN ASSEMBLY
I
FAN

230V

_--1

L1A
115V

IB1I

26 INO CONNECTION)
COMMON
2 1--"-'-----'-----'
2A
115V

NOTFS
1. S2 SHOWN IN N.O.,
2. Sl SHOWN FOR 115VAC CONFIGURATION
1230VAC HAS NO CONNECTION)

PS1

Sl
INOTE 2)

CHASSIS
GROUND
LOGIC

FROM
AC
SOURCE

Figure 9-3

MA-0398-84

AC Input and Fan Components Block Diagram
9-3

•

Line Filter 1
(LFl)
-- filters the ac input, which is
connected by the system box power cord directly into the
LFl.

•

Chassis Ground Lug
provides a ground connection for
the ac input ground from LFI.

Figure 9-4 shows the physical
components, as well as the PSI.
9.2.2

location of the ac input and an

Power Supply 1 (PSI)

The PSI is manufactured by Astec Corporation for the VT240 Series
terminal according to specifications outlined in the VT240 Power
Supply Purchase Specification (PS 3021383-0-0).
The PSI electrical components (Figure 9-5) are all located on a
single PCB. The PSI consist of the following circuits/components.

•

Jl
fan.

•

J2
provides the 19-pin connector for
potentials to the system box logic board.

•

J3 -- provides the two-pin connector to input ac from the
on/off switch.

provides

the connector for routing +12 VA to the

S2
Jl/Pl

FAN
(SHOWN
TRANSPARENT)

PSl

LFl
F2

J2
CHASSIS
NOTE
CHASSIS IS DEPICTED AS REMOVED FROM SYSTEM BOX
WITH COMPONENTS FACED UP.

Figure 9-4

MA-0399-84

Physical Location of
Power Supply Components
9-4

routing dc

•

Switch Pin Connectors -- connect to the voltage selection
switch
(Sl, pins 2 and 2A), for 115 Vac, and have no
connection for 230 Vac (the power supply recognizes 230
Vac selection with no connection to the voltage select
switch, or when connection is made to 115 Vac pins of
switch and switch is in 230 Vac position) •

•

Input Regulation
consists of components responsible
for
ac input, and regulation of isolation, inrush
current, undervo1tage, overvo1tage, and high voltage
transient conditions.

+5V
CROWBAR

1-------,

FROM
ON/OFF
SWITCH
(51)

+12VA

INPUT
REGULATION

TO
LOGIC
BOARD
(J1 )

o 230V
COMMON
115V

PS1
COMPONENT
CARD

SWITCH PIN'
CONNECTORS
'CONNECTED TO 51 FOR 115V SELECTION;
NOT CONNECTED FOR 230V.
MA·Q400-84

Figure 9-5

Power Supply 1 (PS1) Block Diagram

9-5

•

T2
transforms regulated ac input into secondary
voltages used by the dc output circuits to generate the
required dc potentials.

•

DC Output Circuits -- generate the dc potentials output
from the PSl (+12 VA, +12 VB, +5.1 V, and -12 V).

•

+5.1 V Crowbar -- provides overvoltage protection on +5.1
V output of maximum output of 6.9 V.

Figures 9-6 is a circuit schematic of the input regulation
circuits; Figure 9-7 is a circuit schematic of the dc output
circuit, and Figure 9-8 is a circuit schematic of the +5.1 V
crowbar
circuits. Figure 9-9 shows the layout of the PSl
components on the PCB.

DBl
FROM
ON/OFF
SWITCH
(52)

~~Vr+rrv~~-r-4~

TMl

+~~__~ur.-.-__RN2~-.__. - - . - - .

--*_

O+------L-.L.rrYY'--'---+,....,~

TO
DC
CIRCUITS

~~LTAGE ~»-=-"-'-'-----+-------+---------+---+----+--'-"WY-,
C4

SE LECT
SWITCH
(51)

230V

115V

~"-..:...-----+------'

} iL5.1V

~--------+----+---+--

CROWBAR

+C8

NOTE
WINDING SHOWN IS SECONDARY OF Tl.
MA-0401-84

Figure 9-6

Input Regulation Circuitry

9-6

T2
SECONDARY
WINDING

I ~9

;;1'

S{~

R23

""F'

~1\ "'

SRl

+12VB

~27

+C20

..D13

,...'"

Ll0

+12VA

~26

¥21

,...

-:~18 f.:-.

....

+5.1V

~28
;;r:

r,r'

C16~ C17

"' ,...

SCRl

,..."

R24
FROM
11
AC
GROU ND

GROUND

J,
T
~22

... D15

....

+C25

ICl

-12V

•
TO +5.1V
CROWBAR
MA-0402-84

Figure 9-7

DC Output Circuits

FROM
T2
+5.1V
OUTPU T
D6

R15

R16

130

-:~13 ~

,...'"

R19

R17

~iI'

GRO UND
LINE

R25

D16

R20

f---

R14
03

R21

/.
-:
FROM T1
{
SECONDARY
WINDING

R18

~
R26

:J'

R27

R30

C29

Ici ....

r-=-=-'l

R22

MA-0403-84

Figure 9-8

+5.1 V Crowbar Circuit

9-7

()()t#)

ASTEe

D-~-IJ7C=~\)~2:~CJ~c~~\!~~~IJI1=L=~QQ~lJ~15~LlO~~·

CI:J ZI

R24

4c::::J

MADE IN HONG KONG

SCRlc:::::J IC1LiJ

,~<l1981ASTEC

Jl0

\J13

R R

~;',,~I ~ ":~0.r"""u" liiionro~D
r--------':.:..---R12c::::lR13~

D0mJ

'Q O~~
g~
r
I]]
~OB0I15V ~
r-'\O
~ ~~~\!..J

c:::::JA4

R15r--\IIIII1
17 R20 ' C2
\.V

C31

L.....-..------'O'G
c::::::J ~

'9 !

016 R19

+
TMI

c:::::J

R30

B01~~D

B* I

r::::::::2R25

2~c::::::JC~

1'1

Fl 25A

J26

250V D~g~~

<.!»""

~i~~

IC3
IC4 ~
~

R3
MA-0404-84

Figure 9-9

PSl Component Layout

Table 9-1 lists the component values for the PSl components shows
in Figures 9-6,
9-7, and 9-9. Table 9-2 provides specification
information for the ac voltages. Table 9-3 provides the same
information for dc voltages. Refer to section 9.2.3 (a description
of Jl on the logic board) for a pin-out for J2.

9-8

Table 9-1

Power Supply 1 (PSI) Components

Code

Type

Description

Cl
C2
C3,C4
C5
C6-C9
C10
Cll
C12,C14,C19,C23,
C24,C32-C34
C13
C15-C18,C20,C21
C22
C25
C26,C27
C28
C29
C30
C31

MP capaci tor
MP capaci tor
MP capaci tor
Poly capacitor
Elect capacitor
Elect capacitor
CER capacitor

0.1 uF, +20%, 250 V
0.22 uF, +10%, 250 V
2200 pF, +10%, 250 V
0.1 uF, +10%, 400 V
100 uF, +20%, 250 V
470 uF, +50, -10%, 250 V
1000 pF, +20%, 3 KV, Z5P
Not used

Poly capacitor
Elect capacitor
Elect capacitor
Elect capacitor
Elect capacitor
Elect capacitor
Poly capacitor
Poly capaci tor
CER capacitor

0.22 uF, +10%, 100 V
1000 uF, +100, -10%, 10 V
220 uF, +100, -10%, 25 V
100 uF, +50, -10%, 25 V
680 uF, +100, -Y0%, 16 V
1000 uF, +50, -10%, 25 V
0.022 uF, +20%, 100 V
0.22 uF, +10%, 100 V
0.01 uF, +20%, 100 V, Z5U

D1
D2-D4
D5,D13
D6,D7,D16
D8,D9
D10,D12,DI4,D17-D19
D13

Rectifier
Rectifier
Rectifier
Silicon diode
Rectifier
Schottky diode

RGP10A
RGP10M
RGP15B
1N4606
3S4M
Not used
S15S4

DB1

Bridge rectifier

KBL08

Fuse

2.5 A, 250 V

IC1
IC2
IC3,IC4

Regulator
Regulator

L1
L2,L3
L4
L5
L6,L8,L11
L7,L9,L10

Choke
Choke
Choke
Choke

Q1
Q2
Q3

NPN transistor
NPN transistor
PNP transistor

Not used
Common mode assy
Toroid
BASE, 2.2 uH
1. 5 mH
Not used
Coil assy

Choke

9-9

2SD592NC or 2SD467C
2SB621NC or 2SB561C

Table 9-1

Power Supply 1 (PS1) Components (Cont)

Code
Rl,R27,R28,R31-R33
R2
R3,R4
R5
R6
R7
R8
R9,R20
R10,Rll
R12,R17
R13
R14
R15
R16
R18
R19
R21
R22
R23
R24
R25
R26
R29
R30

Description

Type
Metal film
Metal oxide
Metal oxide
Carbon film
Metal oxide
Carbon film
Carbon film
Carbon film
Carbon film
Metal film
Carbon film
Carbon film
Metal oxide
Carbon film
Carbon film
Carbon film
Carbon film

film
film
film

film

Carbon film
Metal film
Carbon film
Carbon film

Not used
0.75, +5%, 1 w
100 K, +5%, 1 w
39, +5%, 2 W
1. 2 K, +5%, 2 W
120, +5%, 2 w
5.6, +5%, 1/4 W
68, +5%, 1/4 W
10, +5%, 1/4 W
8.2, +5%, 1/4 W
0.33, +5%, 1 W
33, +5%, 1/4 W
270, +5%, 1/2 W
220, +5%, 1 W
330, +5%, 1/4 W
56, +5%, 1/4 W
12 K, +5%, 1/4 W
470, +5%, 1/4 W
220, +5%
12, +5%, 1/4 W
2.7 K, +1 %, 1/4 W
2.1 K, +1%
680, +5%, 1/4 W
68, +5%, 1/4 W

SCl
SCRl
SRl

CER capacitor
0.01 uF, +20%, 100 V, Z5U
Rectifier
SCR C122U
Carbon film resistor 10, +5%, 1/4 W

TM1,TM2

Thermistor

4, +10%

VORl

Voltage rectifier

VDR 260 Vac

Zener diode

5.6 V, +5%, 1 W at 40 rnA

9-10

Table 9-2

Input Voltage Specifications

Specification

Value

115 Vac
Nominal voltage
Minimum voltage
Maximum votage
Input line current
Line frequency
Power factor
Inrush current

Surge Current
Input Power
Efficiency
Undervoltage
Overvol tage
Transients

120 Vac
90 Vrms
128 Vrms
2.2 Arms (maximum)
47 Hz
63 Hz
Watts = (RMS V X RMS A)
>0.60 surge current at first
application of input voltage may be
reached for 1/2 cycle of input line,
with repetitive peaks of
exponentially decaying amplitude for
up to 10 more cycles.
25 A (peak) (thermisters cold)
120 W (max) at full rated dc
output load of 77 W.
0.65 (minimum) output power to
input power ratio.
Provides minimum of 5 millisecond
hold-up at 90 Vrms during power
outage.
150 Vac for 1 second (maximum)
Low energy transient of 300 V peak
spike with no more than 0.2 watt
seconds of energy per spike;
High energy transient of 1 KV peak
spike with no more than 2.5
wattseconds of energy per spike.

230 Vac
Nominal voltage
Minimum voltage
Maximum votage
Input line current
Line frequency
Power factor
Inrush current

Surge current
Input power

240 Vac
180 Vrms
268 Vrms
1.1 Arms (maximum)
47 Hz
63 Hz
Watts = (RMS volts X RMS amps)
>0.60 surge current at first
application of input voltage may be
reached for 1/2 cycle of input line,
with repetitive peaks of
exponentially decaying amplitude for
up to 10 more cycles.
25 A (peak) (thermisters cold)
120 W (maximum) at full rated dc
input load of 77 W.

9-11

Input Voltage Specifications (Cont)

Table 9-2
Specification

Value

Efficiency

0.65 (minimum) output power to input
power ratio.
Provides minimum of 5 millisecond
hold-up at 180 Vrms during power
outage.
300 Vac for 1 second (maximum)
Low energy transient of 300 V peak
spike with no more than 0.2
watt seconds of energy per spike;
High energy transient of 1KV peak
spike with no more than 2.5
watt seconds of energy per spike.

Undervo1tage
Overvo1tage
Transients

Table 9-3

Output Voltage Specifications

Voltage

Specification

Value

+5.1 V

Nominal output
Minimum load
Maximum load
Ripple and noise

+5.1 V

Tota 1 regula ti on
Long term stability
Overcurrent

Overvo1 tage
+12 Va

Nominal output
Minimum load
Maximum load
Ripple and noise
Total regulation
Long term stability
Overcurrent

4 A

6.5 A
50 mV peak-to-peak (maximum) (see
note)
+3% to -5%
0.1%/1000 hr
No damage for any permanent
overcurrent averaging 7.8 A or less,
with peak current of 10 A or less in
any 10 second period, or for a
permanent short circuit.
6.9 V (maximum) with crowbar
protection
+12 V
0.2 A
1.0 A (includes 0.12 A fan load)
150 mV peak-to-peak (maximum) (see
note)
+5% to -5%
0.1%/1000 hr
No damage for any permanent
overcurrent averaging 1.2 A or less,
with peak current of 2 A or less in
any 10 second period, or for a
permanent short circuit (short
circuit current specified as
0.5 A maximum) •

9-12

Table 9-3

Output Voltage Specifications (Cont)

Voltage

Specification

Value

+12 VB

Nominal output
Minimum load
Maximum load
Ripple and noise

+12 V
oA
2.35 A
100 mV peak-to-peak (maximum) (see
note)
-5% to +16.66% for 0 A to 0.2 A, -5%
to +5% for 0.2 A to 2.35 A
0.1%/1000 hr
No damage for any permanent
overcurrent averaging 2.8 A or less,
with peak current of 3 A or less in
any 10 second period, or for a
permanent short circuit (short
circuit current specified as 1 A
maximum) •

Total regulation
Long term stability
Overcurrent

-12 V

Nominal output
Minimum load
Ma x imum load
Ripple and noise
Total regulation
Long term stability
Overcurrent

-12 V
0.03 A
0.3 A
50 mV peak-to-peak (maximum) (see
note)
+5% to -5%
0.1%/1000 hr
No damage for any permanent
overcurrent averaging 0.5 A or less,
with peak current of 2 A or less
in any 10 second period, or for a
permanent short circuit (short
circuit current specified as 500 rnA
maximum) •

NOTE
Ripple and noise values are shown as
measured
with
Tektronix
P6046
differential probe, with scope set for
>100 MHz bandwidth.

9-13

9.2.3

DC Power Input Connector (Jl)

Jl provides dc input to the logic board. Jl connects with J2 of
the PSI via a ribbon cable (PN 17-00428-01). Figure 9-10 shows the
connection between the logic board and the PSI, including pin-outs
for both connectors.
9.2.4

+5 V Input Circuit

The +5 V input circuit develops all +5 V operating potential
required
by the logic board components from +5.1 V input
originating at the PSI.
Figure 9-11 shows the components
circuit, as well as the various
developed by this circuit.

) """m

5
6

-12V
-12V
GROUND
GROUND

8
9
10
11
12
13
14
15
16
17

FOR PRODUCTION
TESTING

OH DL

3
4

that make up the +5 V input
+5 V operating potentials

GROUND
GROUND
GROUND
+12VB
+12VA
KEY
+12VA

4
5

-12V
-12V

}

TO
-12V
INPUT

6
7

8
9

GND
TO
LOGIC
COMPONENTS

10
11
12
13

TO
+12V
INPUT

GROUND
+5.1V
+5.1V
+5.1V

PART OF
PS1

PART OF
LOGIC BOARD
MA-0405-84

Figure 9-10

Logic Board DC Power
Input Connector

9-14

9.2.5

+12 V Input Circuit

The +12 V input circuit develops all +12 V operating potential
required by the logic board components, as well as the +12 V sent
from the logic board to the keyboard module, from +12 V inputs
originating at the PSI.
Figure 9-12 shows the components that make up the +12 V input
circuit, as well as the two +12 V operating potentials developed
by this circuit.

,-----...".----.-------.------++5B
~

C39-C42
O.IUF

r----~---------..GB

r-<:i;:=c--..... +5 D
16

+5.1V

+5V
C12
150UF,
15V

C9
560PF

C222 R30
.22UF IK

C1,C2,C7,C8,C19,C27,C14,
C203-C207,C211-C219,
C221-C231,C23B,C239,
C241-C244,C246-C253,
C25B.C259.C264,C221
t4---.22UF - - - - + I

+VC
+VB

MA-0406-84

Figure 9-11

+5 V Input Ci rcui t

+12V
+12V
+12V
+12V

TO KEY BOARD CONNECTOR (J61
TO EIA PORT IIF
TO PRINTER PORT IIF
TO INTEGRAL MODEM CONNECTOR (J51

r-~~---r--L-~-'TODCPOWEROK

~ +12BV

+12VC • TO MONITOR CONNECTOR (J81
.JC10

:::.:..:..:"--_ _---']' 560PF
~1-GND
_
J1
PINS
MA·0407-84

Figure 9-12

+12 V Input Circuit

9-15

9.2.6

-12 V Input Circuit

The -2 V input circuit develops the -12 V and -5.1 V operating
potential required by the logic board components from -12 V input
originating at the PS1.
Figure 9-13 shows the components that make up the -12 V input
circuit, as well as the three operating potentials developed by
this circuit.
9.2.7

DC Power Okay Circuit

The dc power Okay circuit provides visual indication of dc input
to the logic board. Figure 9-14 shows that +5 V, +12 V, and -12 V
potentials are applied as inputs to the dc power okay circuit.
When all three inputs are present, Q2 is properly biased, and 02,
a light emitting diode (LED), lights.

08
IN4004
1-'=-:,----,---rlIIIt---.-------------~--12V

R38

220

L - - - - - , - - - - , - - - - - - - , - - - +__ -5.1V
J1
PINS

01
IN5231B
5.1V 5%
1/2W

-12A

C24
.22UF

C240
560PF

MA-0408-84

Figure 9-13

-12 V Input Circuit

+5V

J12V

E6.3
4.7K

~02

R43
3.3K

(6.78V)

R42
270

07
IN4745A
-12V----~-------.J

MA-0409-84

Figure 9-14

DC Power OK Circuit

9-16

CHAPTER 10
INTEGRAL MODEM OPTION

113.1

GENERAL

The Integral Modem/Auto Dialer option (shaded area in Figure 113-1)
enables the same communications line to be used by a telephone for
normal voice communication or by the VT2413 terminal for data
communication.
Also,
this option lets the user dial up a host
computer by using the terminal keyboard instead of a telephone
set.
The modem has three operating modes accessible through the VT2413
terminal: data mode, talk mode, and dialer mode.

SYSTEM BOX

LOGIC

/ / VIDEO
/
LOGIC

_ _ ...L / _ _ _ _ _

SYSTEM
COMMUNICATION

EIA
HOST
PORT

PRINTER
PORT

20 mA
PORT

OPTIONAL
HOST
COMMUNICATIONS

MONITOR
(VR201 OR VR2411
MA·Q054-84

Figure 10-1

VT240-Series Terminal Block Diagram

10-1

DATA MODE
This mode sets the terminal for communicating data with the host
computer.
In this mode, you cannot use the telephone for voice
communication.
TALK MODE
Talk mode allows
communication.

you

use

the

telephone

for normal voice

DIALER MODE
This mode lets you:
•

Use the keyboard to dial a telephone number

•

Use a single
number dialed

•

Recall and dial stored telephone numbers

10.1.1

keystroke

redial

the last telephone

Compatibility and Features

The integral modem is operationally compatible with the following
two devides.
•
•

Bell l03J data set
Bell 2l2A data set

The modem contains the following features.
•
•
•
•
•
•
10.1.2

Direct connect telephone line interface
Automatic answer
Automatic originate (dialing)
Test modes
Speed control
Keyboard control
Functional Description

The integral modem connects to the system communication logic on
the system logic board. This modem is a full-duplex, asynchronous,
binary serial data communications device. It is used to transmit
and receive data over a two-wire switched telephone network (in
compliance with FCC part 68) at 300 or 1200 bits per second.
Low-speed
operation
(300 bps)
is asynchronous, binary, and
frequency shift keying (FSK). High-speed operation (1200 bps) is
bit-synchronous
(character-asynchronous)
and
quaternary
differential phase shift keying (QDPSK).

10-2

1~.1.3

Physical Description

The modem board is a 5.2 inch X l~ inch PC board that contains the
modem and telephone line interface (TLI). The modem connects to
the system logic board via a 3~-pin stacK connector (Figure 1~-2).
The telephone line and the telephone set connect to the TLI
standard miniature telephone jacKs.

STANDOFFS

Figure 10-2

Physical Description
10-3

10.1.3.1 Power Requirements -- The Integral Modem option has the
following voltage requirements.
+12 Vdc +5% at 200 rnA
-12 Vdc +5% at 200 rnA
+ 5 Vdc +5% at 200 rnA

100 mV peak-to-peak (maximum) ripple
100 mV peak-to-peak (maximum) ripple
50 mV peak-to-peak (maximum) ripple

10.1.3.2 Temperature and Humidity -- The Integral Modem option
has the following temperature and humidity requirements.
Operating temperature

500C

Relative humidity

95%

MAJOR CIRCUITS

10.2

The Integral Modem has the following major circuits (Figure 10-3).

••
•
•

•
•
•
•
•

Talk/data relay
Switch hook detector
Ring detector
Hook relay
Line interface circuit

10.2.1

Talk/Data Relay Circuit

Dial tone detect
Audio coupler
Master clock
Modem control LSI chips

The talk/data relay circuit (Figure 10-4) connects the telephone
line to either the handset or the modem. The position of the
talk/data switch on the VT240 keyboard determines whether the
handset or modem is connected. When the talk/data switch is
pressed, the TALK/DATA signal is inverted and passed through the
stack connector to the modem module.
When the TALK/DATA signal is low, the relay circuit is in talk
mode. The telephone circuit's tip/ring leads connect to the
telephone handset, and disconnects the modem. When the talk/data
signal is high, the talk/data circuit is in data mode. The
telephone circuit's tip/ring leads connect to the modem and the
telephone handset is disconnected and unusable.
The TALK/DATA signal is inverted and becomes the output signal
Talk. This signal is sent to the modem LSI circuit.

10-4

RING

DIAL
TONE
DETECT

DETECT

HOOK RELAY

TALK/DATA RELAY
TELEPHONE
,. LINE

RING

TIP

0--

LINE INTERFACE

RING

TIP

} ~

~TAJ

lDTO

I
"0---

AUDIO H

DA OHO OHM

TELEPHONE
HANDSET

Ia==D

AUDIO
COUPLER

lAAt

OHD -

TEST
w

TIP

SWITCH
HOOK
DETECT

RING

:;; x 0

SW
lLCRD

z ~

(fl

....

MODEM
CONTROL
LSI

::J
0

c::
l!J

;0
N
N
> <'l
"I + "'+ ~

'" :r:

Ol Ol

:r: :;;
:r:

(fl

~
Z

:;;

-MOD

'"
is

(fl

c:: c::
:r: f(fl

Ol
U

(fl

c::

Block Diagram

LINE INTERFACE
RING

0-+---;

}

-+____+_T.::Ic..P_-l

TALK
TALKIDATALr--r--r
DA OHO OHM

RING
TIP

SWITCH
HOOK
DETECT

MA-0415-84

Talk/Da ta Relay

10-5

TERM

TELEPHONE r----l--J.~~
RING
LINE
~ t----It---'rY
0 - - I--'..Tc:.IP_ _

STACK
CONNECTOR

HOOK RELAY

Figure 10-4

c::

DEMOD

TELEPHONE
HANDSET

~.
614.4 KHz
ffiTERCLK
Ol
Z

Figure 10-3

MODEM
CLOCK

113.2.2

Switch Hook Detector Circuit

The Switch Hook Detector circuit (Figure 113-4) senses current flow
in the telephone handset circuit and generates the signal SHe If
the telephone handset is in the off-hook state, current will flow
through the telephone tip/ring circuit. The off-hook current flow
is detected by the switch hook detector and the SH signal is
generated. This signal is passed to the modem control LSI circuit
and also to the terminal (via the stack connector) •
113.2.3

Ring Detector Circuit

The ring detector circuit (Figure 113-4) senses the high voltage,
(213 Hz)
ringing signal from the telephone circuit's tip lead and
generates the ring indicate signal RI. The high voltage ringing
signal is sampled from the tip lead. This lead is common to the
telephone handset connector and the telephone line connector
(RJll). The RI signal is sent to the modem control LSI circuit.
The automatic answer mode is initiated when a valid RING signal is
detected (assuming a DTR signal is also present) •
113.2.4

Hook Relay Circuit

The hook relay circuit (Figure 113-4) connects the tip/ring leads
from the talk/data relay to the protective circuit and is used to
"pulse dial" the telephone system during the automatic dialing
mode. The signal OHD is passed from the terminal through the stack
connector, and operates the Hook Relay. The signal OH is inverted,
becomes OHM, and is returned to the terminal through the stack
connector.
During the pulsed dialing sequence, data from the terminal
keyboard is pulse-formed by the terminal microcode. This generates
the signal DA, data available.
113.2.5

Line Interface Circuit

The line interface circuit (Figure 113-4) terminates the telephone
company's tip/ring circuit. It provides lightning protection and a
full duplex interface between the coupler cut through (CCT)
circuit and the telephone system. The protection circuit is used
to transmit and receive frequency modulated multiplexed data
signals. During auto answer mode, this circuit is the source for
the dial tone signal for the modem.
Since the line interface circuit is full duplexed, it converts the
telephone systems's tip/ring current loop signal to the hybrid
ground reference signal
(AUDIO H). It also converts the AUDIO H
signal to the telephone system current loop standards.

113-6

10.2.6

Dial Tone Detect Circuit

When a
350 Hz dial tone is present on the AUDIO H line (Figure
10-4), the dial tone detect circuit outputs the signal DTD. This
signal is passed to the terminal via the stack connector. The
terminal's microcode senses the DTD signal, and during auto
originate
(AUTO-CALL) mode detects the presence of an available
telephone l i ne.
10.2.7

Audio Coupler Circuit

The audio coupler circuit contains the following elements (Figure
10-5).

•
•
•

Hybrid amplifier
High/low filter
Filter circuit

Coupler cut through relay
Mix circuit
Limiter amplifier threshhold
detector

Hybrid Amplifier
The hybrid ampifier
( IC E2)
splits the signal AUDIO H into
full-duplex transmit data (AUD XMIT), and receive data (FILTER A)
channels.

AUDIO H

0--

cL
OHD -

AUDIO
COUPLER

ANALOG
TEST
UJ

0
0

:;;

(fJ

:;;

f0-

>
N
u

:;;
X

MA-0416-84

HYBRID
AMPLIFIER

LIMITER
AMP

CCT RELAY

THRESHOLD
BEZEL

AUDIO H

XMIT A

X MOD

CCT
ANS MODE
MIX
MA-0417·84

Figure 10-5

Audio Coupler
10-7

High/LOW Filter
The high/low filter
(IC E10)
is a combination high and low
bandpass filter. The high bandpass frequency is 1900 to 2900 Hz
with a center frequency of 2400 Hz. The low bandpass frequency is
700 -- 1700 Hz, with a center frequency of 1200 Hz.
Filter Switch
The filter switch (IC E7) is an analog switch which reconfigures
the
high/low
bandpass
filter's
inputs
and outputs. The
configuration of the bandpass filters depends on which of the
following three possible modes the modem is in.
•

Orginate
When the modem is in the orginate mode (Figure 10-6) ,
the transmit data signal (XMOD) has a carrier frequency
in the 700 to 1700 Hz range. The receive data signal
(FILTER A) may have a carrier frequency of 1900 -- 2900
Hz. The filter input switch routes the XMOD signal into
the low bandpass filter and outputs the signal XMIT A to
the hybrid amplifier. The FILTER A signal is routed to
the high bandpass filter and output as the signal REC.

•

Answer
When the modem is in the answer mode (Figure 10-7), the
transmit data signal
(XMOD) has a carrier frequency in
the 1900
2900 Hz range. The receive data signal
(FILTER A) has a carrier frequency in the 700 -- 1700 Hz
range. The filter input switch routes the XMOD signal
into the high bandpass filter and outputs the signal XMIT
A to the HYBRID amp. The FILTER A signal is routed to the
low bandpass filter and output as the signal REC.

•

Loopback Test
When the modem is in the loopback test mode (Figure
10-8), the data signal XMOD is passed through the low
bandpass filter and inputs to the mix circuit. The mix
circuit, when in the test mode, doubles the frequency of
the XMIT A signal and is outputted as the signal AUD
XMIT. The AUD XMIT signal loops back through the hybrid
amplifier.
AUD XMIT then is input to the high bandpass
filter as receive data.

Coupler Cut Through Relay (CCT)
The coupler cut through relay circuit (Figure 10-5) extends the
AUDIO H signal path from the protective circuit to the audio
coupler. The relay is open during test mode and when the modem is
idle. The CCT relay is operated by the CCT signal. The CCT signal is
generated when the DA and OHD signals are asserted from the
terminal. CCT is sent to the terminal via the stack connector and is
sensed by the terminal microcode.

10-8

HYBRID
AMPLIFIER

FILTER SWITCH

AUDIO H
AUDIO
X MOD

ANS MODE
MA·0418·84

Figure 10-6

Originate Mode

HYBRID
AMPLIFIER

CCT

MA-0419-84

Figure 10-7

Answer Mode

HYBRID
AMPLIFIER

FILTER SWITCH

CCT

XMIT A

X MOD

ANS MODE
MIX
MA-0420-84

Figure 10-8

Test Mode

10-9

Mix Circuit
During normal
transmit data
loopback test
transmit data

operation the mix circuit (Figure 10-5) receives the
signal XMIT A and outputs the AUD XMIT signal. In
mode, the mix circuit doubles the frequency of the
signal.

Limiter Amplifier Threshold Detector
The receive data signal REC is presented to a threshold and zero
crossing detector (Figure 10-5), and output as the signals RX CAR
and TD0.
10.2.8

Master Clock Circuit

The master clock circuit (Figure 10-9) consists of the components
Yl and E43.
Yl generates a
square wave clock signal with a
frequency of 4.9152 MHz which is then divided into the following
four subfrequency signals.
CLOCK A
CLOCK B
FILTER CLOCK
614.4 kHz
10.2.9

Modem Control LSI Circuit

The modem control LSI circuit (Figure 10-10) consists of two large
scale integration (LSI) chips that perform the following tasks.

ANS
MODE

MIX

TOO

XMOD

ClK
MODEM

614.4 KHz

CLOCK

FilTER ClK

MODEM
CONTROL
lSI

MA·0421-84

Figure 10-9

w
f-

Modem Clock

<t:

~u~ 8~~

(J)

w
fMA-0422-84

Figure 10-10

10-10

Modem Control LSI

Data Modulation/Demodulation
The data signal transmit data (TO) is received by the LSI chips
from the terminal via the stack connector and outputs as the
signals MODI, MOD2, and MOD3 to the summing amplifier. The summing
amplifier outputs the signal X MOD to the audio coupler. Received
data is demodulated from the signals TOO and RX CARR and output to
the terminal as the signal RD via the stack connector.
Modern Control and Configuration
The modem control circuit configures the modem for the desired
mode and speed of operation: test mode, originate mode, and
autoanswer mode. The signal data rate select (CH), is input from
the terminal via the stack connector and causes the modem control
LSI circuit to set the high or low speed originate mode. If the
modem is in the autoanswer mode, the modem control LSI circuit
self-configures the modem to the speed of the remote modem. The
signal speed mode indication (CI) is output to the terminal via
the stack connector and detected by the terminal's microcode.
Modern Control Signal Generator
The circuit also detects the presence of a valid received data
carrier and inputs the signal carrier detect (CD) back to the
terminal.
The circuit generates the control signals CTS and DSR.
These signals are sent to the terminal. The input control signals
DTR,
9/10 SELECT, and CH are received from the terminal. These
signals inform the modem control LSI circuit of the bit count of
the transmitted data byte. This is necessary for the transmission
of high speed QDPSK di-bits.
10.3

TERMINAL INTERFACE SIGNAL DESCRIPTION

The interface signals are those signals transmitted through the
30-pin stack connector, either from the system logic board to the
modem, or from the modem to the system logic board (Figure 10-11).
NOTE
The signal states and impedances for the
interface circuits are in accordance
with
TTL
low
power
Schottky
specifications.
Output high level
Output low level
Output low current sink
Output high current
source
Input low level
Input high level
Input high current
Input low current source

10-11

2.4 V minimum
5.25 V maximum
0.4 V maximum
8.0 rnA maximum
400 rnA maximum
0.8 V maximum
2.0 V minimum
0.1 rnA maximum
0.4 rnA maximum

STACK
CONNECTOR

+12
TD
CH
DA
OHD

9/10 SEL
TALK/DATA

-12 V
ANL

+12

TRANS, DATA
DATA RATE SEL
DATA AVAIL
OFF-HOOK DRIVE

9/10 BIT CHAR
LINE SWITCH

-12 V
TEST ANALOG LOOP
REMOTE DIGITAL LOOP

RDL
DTR

+5 V

DATA TERM READY

+5 V

DATA SET READY

DSR

RECEIVE DATA

SPEED INDICATOR

OPTION INDICATOR

DIAL TONE DETECT

DTD

COUPLER CUT THROUGH

CCT

SWITCH HOOK

OFF HOOK

OHM

TEST MODE INDICATOR

TEST IND.

CLEAR TO SEND

CTS

CARRIER DETECT

25
27
30
I

TERMINAL

MODEM
MA-0423-84

Figure 10-11

10.3.1

Stack Connector

Signal Sta tes

Table 10-1 shows
interface signals.

the

active

and

initialized

states

the

The transmitted and received data signals are considered in the
marking state when the circuit voltage is more positive than +2 V
with respect to signal ground, and in the spacing condition when
the voltage on the circuit is more negative than +2 V with respect
to signal ground. The signal is considered off when it is more
positive than +0.8 V with respect to signal ground.

HJ.3.2

State

Vol tage

Ma rki ng
Spacing
Off

> +2 V
< +2 V
> +.8 V

Interface Signals

The following sections describe the interface signals.
10.3.2.1 Transmitted Data
(TO)
Signals on this circuit are
generated by the terminal and transmitted to the modem. A positive
voltage signal is considered a binary one (or mark) condition. A
zero voltage signal is considered a binary zero
(or space)
condition. The transmitting terminal holds this circuit in the
mark state when no data is being transmitted. This is true during
intervals between characters and words as well.
10-12

Table 19-1

I
I-'
W

Initialized
Level

Name

Description

Source Active Level

1
2
3

+12 V

Vol tage

Term

DSR
RD
CI
TD
CH
GND
DA
OHD
9/19.SEL

Modem
Modem
Modem
Term
Term

Low
Low=space
Low=1299 bps
Low=space
High=1299 bps

High
High

Term
Term
Term
Modem
Term

Low=CCT
Low=OH relay
Low=19 bit

High
High
Low

TALK/DATA

Da ta set ready
Receive data
Speed indicator
Transmit data
Da ta ra te select
Vol tage
Da ta avai lable
Off hook--drive
9 or 19 bit char C
Option indication
Line switch

Low=data

High talk

DTD
Hybrid Out
12 V
CCT
SH
OHM

Dial tone detect
Reserved
Vol tage
Coupler cut through
Switch hook
Off hook

Modem
Modem
Term
Modem
Modem
Modem

H=Acti ve

ANL
RDL
Test Ind
DTR
CTS
CD
+5 V

Test analog loop
Remote digital loop
Test mode indicator
Da te term ready
Clear to send
Carrier detect
Vol tage

Term
Term
Modem
Term
Modem
Modem
Term

4
5
6
7
8
9
I-'

Interface Signal Levels

19
11
12
13
14
15
16

17
18
19
29
21
22

High
High

L=Attached
L=Line Current
L=Off hook

24
25
26
27
28
29
39

H+Test
H-Test
L=Test
L=On
L=On
L=On

Low
Low

10.3.2.2 Received Data
(RD)
Signals on this circuit are
generated by the demodulator in response to telephone line
signals. The received data circuit is clamped to the marking state
whenever the interface circuit carrier detector (CD) is idle.
10.3.2.3 Clear to Send
(CTS) -- An on condition of the clear to
send circuit indicates to the terminal that the modem transmits
any signal present on the transmit data (TD) circuit. If CTS is
off, the modem internally clamps transmit data to the mark
condition and ignores the TD circuit. If a remote digital loop is
initiated, the local CTS circuit turns off until the remote modem
is in the digital loop test mode.
10.3.2.4 Data Set Ready
(DSR)
-- This signal originates in the
modem to indicate its status. The on condition indicates the modem
is in the data mode and is connected to the communication channel
(or is in analog loop test mode). The on condition does not mean
that a communication channel has been completely established,
however.
10.3.2.5 Signal and Power Ground -- This circuit establishes a
common ground reference for interface circuits and dc power.
10.3.2.6 Carrier Detect (CD) -- Carrier detector on indicates that
a data carrier is being received and has been received for at
least 155 milliseconds. This circuit differentiates a good data
carrier from message circuit noise or out-of-band signals. This
circuit turns off if the received data is clamped to the marking
state.
10.3.2.7 Speed Indication
(CI)
This circuit is on when the
modem is in the high-speed data mode (or the high-speed analog
loop test mode).
At all other times the circuit is in the off
state.
Since an answering modem automatically adapts to the speed of the
originating station, it ignores its own speed selector. In this
case, the speed selector and the speed mode circuit will not
match.
10.3.2.8 Data Terminal Ready
(DTR)
This circuit provides a
means for the terminal to control the connection of the modem to
the communication channel
(and to control the analog loop test
mode). The on condition is required to maintain a connection to
the communication channel. The on condition must also be present
to enter the data mode, either manually or automatically. If this
circuit is off for more than 50 milliseconds during a data call, a
disconnect sequence is initiated.
10-14

For automatic answering applications, the presence of an off
condition on this circuit does not inhibit the operation of the
ring indication (RI) circuit. This circuit (DTR) must be turned on
to automatically answer an incoming call.
For the analog loop test mode, this signal must be on at the same
time with the analog loop (ANL) signal.
10.3.2.9 Data Rate (Speed) Select (CH) -- This signal enables the
terminal to select high-speed mode
(1200 bits per second), or
low-speed mode (300 bits-per-second) via the modern A/B speed mode
circuit.
10.3.2.10 Dial Tone Detect (DTD) -- This signal is generated by
the modern whenever the phone line is ready for dialing (dial tone)
after off hook. The terminal checks this condition before dialing.
10.3.2.11 Line Switch (Talk/Data) -- This signal is generated by
the terminal's firmware and is activated by a dedicated keyboard
switch. This signals talk mode or data mode to the modern.
10.3.2.12 Data Available (DA) -- This signal is generated by the
terminal to request a data transmission path cut through. For
pulse dialing, the terminal disables the DA signal after detecting
a dial tone before generating the dial pulses corresponding to the
called number.
10.3.2.13 Off Hook Drive
(OH-D) -- The terminal generates this
signal to drive the off hook relay. When the signal is low, the
relay is on.
10.3.2.14 9 or 10 Bit Character
(9/10 SEL) -- This signal is
generated by the terminal to select 9 or 10 bits-per-character
mode. A low signal indicates 10-bit mode.
10.3.2.15 Coupler Cut Through (CCT) -- The modern generates this
signal after off hook.
It indicates that the audio path to the
telephone line is ready.
10.3.2.16 Switch Hook
(SW)
The modern uses this signal to
indicate to the terminal the status of the switch hook.
10.3.2.17 Off Hook Modern (OH-M) -- The modem uses this signal to
indicate to the terminal that it (the modern) is "off the hook".

10-15

10.3.2.18 Analog Loop Test (ANL) -- This interface signal tests
modem A by forcing the transmitter
(modulator) and receiver
(demodulator)
into the same mode. This allows data from the
terminal to loop through the modem and back for a local modem
test.
10.3.2.19 Remote Data Loopback Test
(RDL)
This interface
signal causes the local 2l2A modem to put the remote 212A modem
into a data loop. Data from the terminal is then transmitted from
the local modem to the remote modem and back again, thus checking
the local and remote modems and the line.
10.3.2.20 Test Mode Indicate (Test IND) -- The modem generates
this signal whenever it is in the test mode.

10-16

APPENDIX A
SPECIFICATIONS

GENERAL
This
appendix
specifications.

lists

the

VT240/VT241

video

terminals

Physical
System box

Height: 10.2 em (4
Width: 45.7 em (18
Depth: 30.5 em (12
Weight: 7.2 Kg (16

in)
in)
in)
1bs)

Keyboard

He i g h t: 5. 1 em
wi d th: 53. 3 em
Depth: 17.1 em
Weight: 2.0 kg

Monochrome monitor

Height: 29.2 em (11.5 in)
Width: 34.9 em (13.75 in)
Depth: 31.1 em (12.25 in)
Weight: 6.4 kg (14 1b)
Adjustable Tilt: +5° -- _25°

Color monitor

He i g h t : 3 2 • 4 em ( 1 2 • 7 5 in)
Width: 38.0 em (15 in)
Depth: 42.1 em (17.0 in)
Weight: 16.6 kg (36.6 1b)

( 2 • 0 in)
(21. 0 in)
(6.75 in)
(4.5 1bs)

Environmental

Opera ti ng

Temperature: 10 -- 40 C
(50° -- 104°F)
Relative Humidity: 10% -- 90%
Maximum Wet Bulb: 28°C (82°F)
Minimum Dew Point: 2°C (36°F)
Maximum Altitude: 2.4 km (8000 ft)

Storage

Temperature: _40° -- 66°C
(140° -- 151°F)
Relative Humidity: 0%
95%
Maximum Altitude: 9.1 km (30000 ft)

A-I

Electrical
Line voltage
(switch selectable)

90 -- 128 Vac (100 -- 120 RMS
nominal) single-phase, 3-wire
180 -- 268 Vac (220 -- 240 RMS
nominal) single-phase, 3-wire

Line frequency

47 -- 63 Hz

Power cord

Detachable, 3-conductor, grounded

Display
Format
Character

24 lines X 80 characters or 24 lines
X 132 characters
7 X 9 dot matrix in 10 X 10 cell for
80 columns
5 X 9 dot matrix in 6
132 columns

Character size

X 10 cell for

3.35 mm X 2.0 mm for 80 columns
3.35 mm X 1.3 mm for 132 columns

Active display size

202 mm X 115 mm (8

X 5 in)

Character set

ASCII, DEC Supplemental, Special
Graghics, UK, loadable 80 or 132
column font
Control characters (using control
representation mode) 80-column font
only

Character attributes

Reverse video, underline, bold,
blinking (maximum of 100
characters), alternate character ROM

Cursor Type

Blinking block cursor or blinking
underline cursor

A-2

Keyboard Characteristics
General

105 key detachable unit with a 1.9 m
(6.0 ft) coiled cord with a 4-pin
telephone-type modular connector.
Word processing and data processing
versions are available in 15
languages.

Keypad

Sculptured key array, matte texture
finish keys, home row key height is
30mm (1.18 in) above desk top

Key Size

1.27 cm (0.5 in) square

Key Spacing

1.9 cm (0.75 in) center-to-center
(single-width keys)

Numeric keypad

18 keys

Function keys

36 keys, firmware and software
dr i ven

Visual indicators

4 LED indicators: hold, lock, wait,
and compose

Audible signals

Keyclick: provides audible feedback
for each keystroke.
Bell: sounds when BEL character is
received, when approaching right
margin, and for compose errors.
Multiple Bell: sounds on error in
set-up save or recall operation.

A-3

APPENDIX B
VT240/VT102 DIFFERENCES

This appendix describes the major differences between a VT102
terminal and the VT240 terminal operating in a VT100 mode.
Feature

VT102

VT240

LEOs

Programmable

Not programmable

Alternate
character ROM

Socket for OEM
supplied
character ROM

Down-line loadable
character set

Screen freeze

NO SCROLL key

HOLD SCREEN key

Printer port
connector

25 pin

9 pin

Screen refresh

50/60 Hz

60 Hz only

Set-up

Display in
English only

Display in three
languages, and display
does not affect software

RIS function

Performs power-up
self-test

Does not perform
power-up self-test

132 Column font
horizontal
resolution

7 pixels with
2 pixels between
characters

5 pixels with
1 pixel between
characters

Off-line/local

Off line mode
disconnects modem

Local mode does
not disconnect modem

B-1

Feature

VT102

VT240

Communication

Full-duplex and
half-duplex mode

Full-duplex mode only,
and does not affect
softwa re

Transmit speed
limitation of 60
characters-persecond, regardless
of baud rate

Optional transmit speed
limitation of 150
characters-per-second

Selectable passive
or active 20 rnA

Passive 20 rnA only

ESC [ ? 6 c

CSI ? 62; 1;2;3;4;6;7;8 c
(primary)
CSI > 2;Pv;Po c
(secondary)

Termi na 1 IDs

B-2

APPENDIX C
VT240/VT125 DIFFERENCES

This appendix describes the functional differences between a VT125
terminal and a VT240 terminal operating in a ReGIS graphics mode.
Di fference Area

VT125

VT240

Screen size
(displayed
pixels)

768 X 240 displayed
pixels

800 X 240 displayed
pixels

Screen clipping

Pixels outside
defined screen
addressing range but
inside visible screen
are drawable

Pixels outside
defined screen
addressing range
but inside visible
screen are not
drawable (clipped)

Offscreen bit-map
memory

Offscreen memory for
graphics

No off screen memory
for graphics

Screen addressing
(picture aspect
ratio)

Scales X and Y
directions
independently
when mapping

Maintains picture
aspect ratio when
mapping

Screen addressing
(integral scaling)

Uses integral
divisions to map
screen addressing
range to physical
pixels

General scaling
algorithm for
mapping screen
addressing range to
physical pixels

Screen addressing
(decima 1
fractions)

Ignores digits after
a decimal point in
screen addressing
parameters and
coordinates

Fractional digits
significant in screen
addressing parameters
and coordinates

Screen scaling
(zoom)

Supports screen
scaling

Does not support
scaling

C-l

Di fference Area

VT125

VT240

Screen offset

Images moved off
screen eventually
wrap back

Images moved off
screen are lost

Allows offset on
single-pixel
boundaries
horizontally and
vertically

Scrolls image on
16-pixel boundaries
horizontally, and
single-pixel
boundaries vertically

When image is moved
origin moves
with image

When image is moved
origin remains
fixed at point
defined by screen
addressing command

Shading

Shading to
horizontal base
line only

Shading to horizontal
and vertical baseline

Character shading

Uses italic
attribute when
drawing shaded
area with character
fill

Does not use italic
attribute when
drawing shaded
area with character
fill

Size of position
stack

10 entries

32 entries
Images that rely on
on position stack
overflow at eleventh
entry may not execute
on VT240
Stack underflow and
overflow are
reportable errors

writing controls

Custom writing
control command
ReGIS W(W)

Default writing mode

Graphics text

Zero character is
slashed

Zero character is
not slashed

C-2

Difference Area

VT125

VT240

Image control
on optional
external monitor

Provides for:
• Optional external
monitor on which
same image is
displayed

Provides only for
optional external
monitor on which same
image is displayed as
on standard monitor

• Optional external
monitor on which
only graphics
image (no text
image) is displayed
(can be controlled
separately)
VT105 emulation

Yes

ANSI text and
graphics

Can scroll text
over graphics

Text and graphics
must scroll together

Display ReGIS

Graphics images and
ReGIS commands used
to generate them
can appear simultaneously on entire
screen

ReGIS commands used
to display graphics
images appear on line
24 of screen

Overlaying text
and graphics

Text can overlay
graphics in same
display region

Text drawn in
display region as
graphics replaces
graphics image

Erasing command

Erases text and
graphics separately

Erases text and
graphics at same time

Changing output

Changes only
presentation of
graphics image

Changes presentation
map of text as well
as graphics image

Terminal IDs

ESC [ ? 12;Pvt00;Pf;Pvc

CSI ? 62;1;2;3;4;6;
7; 8 c (pr imary)
C S I > 2; Pv; Po c
(secondary)

C-3

APPENDIX D
REGISTER BIT VALUES

171000 (WR)
07

PEN

(RDA7H) ~~~--------------------------------------~~ (RDAOH)

NOTE
FOLLOWING A POWER UP SEQUENCE, OR AN INTERNAL RESET CONDITION
IN THE 8251 A. THE 8251 A MUST FIRST BE PROGRAMMED FOR MODE OF
OPERATION, AND THEN FOR COMMAND INFORMATION, WITH BOTH
ACTIONS OCCURRING AT ADDRESS 172000.

BIT VALUES

BIT 6-7

00
10
01
11

INVALID
1 STOP BIT PER TRANSMIT CHARACTER
1 y, STOP BITS PER TRANSMIT CHARACTER
2 STOP BITS PER TRANSMIT CHARACTER

BIT 5

ODD PARITY GENERATION CHECK
EVEN PARITY GENERATION CHECK

BIT 4

PARITY DISABLED
PARITY ENABLED

BIT 2-3

00
10
01
11

5 BITS PER CHARACTER
6 BITS PER CHARACTER
7 BITS PER CHARACTER
8 BITS PER CHARACTER

BIT 0-1

00
10
01
11

SYNC MODE
BAUD RATE FACTOR OF 1 X
BAUD RATE FACTOR OF 16X
BAUD RATE FACTOR OF 64X
MA-0178-84

Figure D-l

8251A USART: Command Register
(Mode Instruction Format,
Asynchronous Mode)

D-l

171000 (WR)
07

RTS

SBRK

RxE

DTR

TxEN

(RDA7H) ~.~--------------------------------------.~. (RDAOH)

NOTE
FOLLOWING A POWER UP SEQUENCE, OR AN INTERNAL RESET CONDITION
IN THE 8251 A, THE 8251 A MUST FIRST BE PROGRAMMED FOR MODE OF
OPERATION, AND THEN FOR COMMAND INFORMATION, WITH BOTH
ACTIONS OCCURRING AT ADDRESS 172000.

BIT VALUES

BIT 7

DISABLE SEARCH FOR SYNC CHARACTERS
SEARCH FOR SYNC (NO EFFECT IN ASYNC)

BIT 6

INACTIVE
I NTE RNAL RESET

BIT 4

INACTIVE
RESET ERROR FLAGS

BIT 3

NORMAL OPERATION
FORCE TxD CONSTANT LOW

BIT 2

RECEIVE ENABLE DISABLED
RECEIVE ENABLE ENABLED

BIT 1

DTR DISABLED
DTR FORCED LOW (GENERATING LPBK EN L)

BIT 0

TRANSMIT ENABLE DISABLED
TRANSMIT ENABLE ENABLED

BIT 5

NOT USED

MA-017g.84

Figure 0-2

8251A USART: Command Register
(Command Oata Format)

0-2

171000 (RD)
07

DSR

SYNDET

Tx
EMPTY

Rx
RDY

Tx
RDY

(RDA7H)

~4~--------------------------------------~~ (RDAOH)

BIT VALUES
BIT 7

DSR INPUT IS NOT USED

BIT 6

SYNDET OUTPUT IS NOT USED

BIT 5

NO FRAMING ERROR (FE FLAG, ASYNC ONLY)
FE FLAG SET, NO STOP CHARACTER DETECTED

BIT 4

NO OVERRUN ERROR (OE FLAG)
OE FLAG SET, CPU FAILED TO READ Rx CHARACTER
BEFORE NEW Rx CHARACTER

BIT 3

NO PARITY ERROR (PE FLAG)
PE FLAG SET (PARITY ERROR SENSED)

BIT 2

NOT READY FOR Tx DATA (TxD)
READY FOR TxD (GENERATES KYBD INTR2 L)

BIT 1

NO Rx DATA (RxD) PRESENT
RxD PRESENT (GENERATES KYBD INTR1 L)

BIT 0

TxD BUFFER FULL
TxD BUFFER EMPTY
MA-0181-84

Figure D-3

8251A USART: Status Register

D-3

(MRl A) ADDRESS 1 72000( RD)/l 72002(WR)
(MRl B) ADDRESS 172040(RD)/172042(WR)
07

I
Rx
RTS
(RDA7 HI

RxlOT

ERROR

SEL

MODE

PARITY MODE

I
PARITY

BITS PER

TYPE

CHAR1CTER

•

(ROAD HI

BIT VALUES

BIT 7

RxRTS DISABLED

BIT 6

INTERRUPT ON RxRDY
INTERRUPT ON FFULL

BIT 5

CHARACTER ERROR MODE
BLOCK ERROR MODE

BIT 3--4

00
01
10
11

WITH PARITY
FORCE PARITY
NO PARITY
SPECIAL MODE

BIT 2

EVEN PARITY
ODD PARITY

BIT 0-1

00
01
10
11

RxRTS ENABLED

5 BITS PER CHARACTER
6 BITS PER CHARACTER
7 BITS PER CHARACTER
8 BITS PER CHARACTER

MA_0182_84

Figure D-4

2681 DUART: Mode Register 1
(MR1) (Channel A and B)

D-4

(MR2AI ADDRESS 172000(RDI/172002(WRI
(MR2BI ADDRESS 172040(RDI/172042(WRI
07

I
Tx
RTS

CHANNEL
M01DE

CTS
ENABLE
Tx

STOP BIT LENGTH

(ROA7H) ••~--------------------------------------~~(ROAOH)

BIT VALUES
BIT 6-7

00
01
10
11

NORMAL MODE
AUTO ECHO MODE
LOCAL LOOP MODE
REMOTE LOOP MODE

BIT 5

TxRTS DISABLED
TxRTS ENABLED

BIT 4

NO CTS REQUIRED FOR Tx
CTS REQUIRED FOR Tx

BIT 0-3

0000' 0.563 BIT STOP CHARACTER
0001' 0.625 BIT STOP CHARACTER
0010' 0.688 BIT STOP CHARACTER
0011' 0.750 BIT STOP CHARACTER
0100' 0.813 BIT STOP CHARACTER
0101' 0.875 BIT STOP CHARACTER
0110' 0.938 BIT STOP CHARACTER
0111' 1.000 BIT STOP CHARACTER
1000 1.563 BIT STOP CHARACTER
1001 1.625 BIT STOP CHARACTER
1010 1.688 BIT STOP CHARACTER
1011 1.750 BIT STOP CHARACTER
1100 1.813 BIT STOP CHARACTER
1101 1.875 BIT STOP CHARACTER
1110 1.938 BIT STOP CHARACTER
1111 2.000 BIT STOP CHARACTER
, ADD .5 BIT FOR 5 BITS PER CHARACTER OPERATION
MA_0183_84

Figure 0-5

2681 OUART: Mode Register 2
(MR2) (Channel A and B)

0-5

(SRA) ADDRESS 172004(RD)
(SRB) ADDRESS 172044(RD)
07

Tx
EMT

Tx
ROY

FFULL

Rx
ROY

(RDA7 H) •

• (RDAO H)

PARITY
ERROR

RECEIVED
BREAK
FRAMING
ERROR

OVERRUN
ERROR

BIT VALUES

BIT 7

NO BREAK DETECTED
RECEIVE BREAK DETECTED

BIT 6

NO ERROR
FRAMING ERROR

BIT 5

NO ERROR
PARITY ERROR

BIT 4

NO ERROR
OVERRUN ERROR

BIT 3

Tx NOT EMPTY
Tx HOLDING AND SHIFT REGISTERS EMPTY

BIT 2

Tx HOLDING REGISTER FULL
Tx HOLDING REGISTER EMPTY

BIT 1

Rx FI FO NOT FU LL
Rx FIFO FULL

BIT 0

NO Rx DATA WAITING
Rx DATA IN FIFO

MA-0234-84

Figure D-6

2681 DUART: Status Register
( SR) (Channel A and B)

D-6

DCSRA ADDRESS 172006 (WR)
DCSRB ADDRESS 172046 (WR)
07

TRANSMITTER CLOCK SELECT

RECEIVER CLOCK SELECT

(RDA7H) ••--------------------------------------~. (RDAOH)

BIT VALUES
BIT 0-3
OR 4-7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1100
1101
1110
1110
1110
1110
1111
1111
1111
1111

BAUD RATE SET 1

BAUD RATE SET 2

50
110
134.5
200
300
1200
1050
2400
4800
7200
9600
38.4K
TIMER
IP4-16X(RxCA)
IP6-16X(RxCBI
IP3-16X(TxCA)
IP5-16X(TxCB)
I P4-1 X( RxCA)
IP6-1 X(RxCB)
I P3-1 XITxCA)
IP5-1 X(TxCB)

75
110
134.5
150
300
1200
2000
2400
4800
1800
9600
19.2K
TIMER
IP4-16X(RxCA)
IP6-16X(RxCB)
IP3-16X(TxCA)
I P5-16X(TxCB)
I P4-1 X( RxCAI
IP6-1 X(RxCB)
IP3-1XITxCA)
IP5-1 XITxCB)

NOTES
1. RxC AND TxC ARE ALWAYS 16X EXCEPT FOR 1111 CONDITION;
2. SET SELECTION MADE BY ACR BIT 7.
MA-023S-84

Figure D-7

2681 DUART: Data Clock
Selection Register (DCSR)
(Channel A and B)

D-7

(CRA) ADDRESS 17201 2(WR)
(CRB) ADDRESS 172052(WR)
07

NOT
USED

DISABLE
Tx

ENABLE
Tx

DISABLE
Rx

ENABLE
Rx

MISe. COMMANDS

(RDA7H) ~~r-------------------------------------"~ (ROAOH)

BIT VALUES

BIT 7
BIT 4-6

ALWAYS 0
000
001
010
011
100
101
110
111

NOT USED
RESET MODE REGISTER (MR) POINTER
RESET Rx
RESET Tx
RESET ERROR STATUS
RESET CHANNEL BREAK CHANGE INTERRUPT
START BREAK
STOP BREAK

BIT 3

NO COMMAND
TERMINATE Tx AND RESET TxROY AND
TxEMT STATUS BITS

BIT 2

DISABLE Tx
ENABLE Tx

BIT 1

NO COMMAND
TERMINATE Rx IMMEDIATELY

BIT 0

DISABLE Rx
ENABLE Rx

MA-0236-84

Figure D-8

2681 DUART: Command Register
(CR) (Channel A and B)

(RDRA) ADDRESS 172014(RD)
(RDRB) ADDRESS 172056(RD)
(TDRA) ADDRESS 172016(WR)
(TDRB) ADDRESS 172060(WR)
07

(RDA7H) ~~~------------------------------------•• (RDAOH)

BIT VALUES

BIT 0-7

DATA RECEIVED FROM HOST (RDRA)
DATA RECEIVED FROM PRINTER (RDRB)
DATA TO TRANSMIT TO HOST (TORA)
DATA TO TRANSMIT TO PRINTER (TORB)

MA-0237·84

Figure D-9

2681 DUART: Receive/Transmit
Data Registers (RDR/TDR)
(Channel A and B)

D-8

ADDRESS 172020 (RD)
07

DELTA
IP3

DELTA
IP2

DELTA
IPl

DELTA
IPO

IP3

IP2

IPl

IPO

(RDA7H)~~~--------------------------------------~~.(RDAOH)

BIT VALUES

BIT 7

NO CHANGE OF STATE DETECTED AT IP3
CHANGE OF STATE DETECTED AT IP3

BIT 6

NO CHANGE OF STATE DETECTED AT IP2
CHANGE OF STATE DETECTED AT IP2

BIT 5

NO CHANGE OF STATE DETECTED AT IPl
CHANGE OF STATE DETECTED AT IPl

BIT 4

NO CHANGE OF STATE DETECTED AT IPO
CHANGE OF STATE DETECTED AT IPO

BIT 3

0/1

CURRENT STATE OF IP3

BIT 2

0/1

CURRENT STATE OF IP2

BIT 1

0/1

CURRENT STATE OF IPl

BIT 0

0/1

CURRENT STATE OF IPO

MA-0238-84

Figure 0-110

2681 OUART: Input Change
Reg i ster (ICR)

ADDRESS 172064 (RD)
07

I I

IP6

IP5

IP4

IP3

IP2

IPl

IPO

NOT
USED •

(RDA7 H) ..

(RDAO H)

BIT VALUES
BIT 6

0/1

CURRENT STATE OF IP6 (MOD2 SI L)

BIT 5

0/1

CURRENT STATE OF IP5 (HOST DSR L)

BIT 4

0/1

CURRENT STATE OF IP4 (MOD2 CTS L)

BIT 3

0/1

CURRENT STATE OF IP3 (MOD SI L)

BIT 2

0/1

CURRENT STATE OF IP2 (MOD CD L)

BIT 1

0/1

CURRENT STATE OF IPl (PRTR DSR L)

BIT 0

0/1

CURRENT STATE OF IPO (HOST CTS L)

MA-0239-84

Figure 0-11

2681 OUART: Input Port
Register (IPR)

0-9

(CTUR) ADDRESS 172030(RD)/172032(WR)
(CTLR) ADDRESS 172034(RD)/172036(WR)

(RDA7HI ~4'---------------------------------------~~ (RDAOHI

BIT VALUES
BIT 0--7

LEAST SIGNIFICANT BYTE OF COUNTER OR TIMER MODE (CTLRI
MOST SIGNIFICANT BYTE OF COUNTER OR TIMER MODE (CTURI

MA-0240-84

Figure 0-12

2681 OUART: Counter Timer/Upper
(CTUR) and Lower (CTLR) Registers

ADDRESS 172022(WR)

07
BAUD
SET SEL

COUNTER/TIMER
MODE AND SOURCE

DELTA
IP3

DELTA
IP2

DELTA
IPl

DELTA
IPO

INT

INIT

(RDA7HI ~
• .-------------------------------------~~. (RDAOH)

BIT VALUES
BIT 7

BIT 4-6

000
001
010
011
100
101
110
111

SELECT BAUD RATE SET 1
SELECT BAUD RATE SET 2
COUNTER MODE - EXTERNAL (lP21 SOURCE
COUNTER MODE- TxCA AT 1 X CLOCK OF CHANNEL A Tx
COUNTER MODE- TxCB AT 1 X CLOCK OF CHANNEL B Tx
COUNTER MODE - CRYSTAL OR EXTERNAL CLOCK (CLK)
DIVIDED BY 16
TIMER MODE - EXTERNAL IIP2) SOURCE
TIMER MODE - EXTERNAL (lP2) SOURCE DIVIDED BY 16
TIMER MODE - CRYSTAL OR EXTERNAL·ICLK) SOURCE
TIMER MODE - CRYSTAL OR EXTERNAL ICLK) SOURCE
DIVIDED BY 16

BIT 3

NO INTERRUPT ON CHANGE OF STATE
SET ISR BIT 7 ON DETECT OF CHANGE OF STATE AT IP2

BIT 3

NO INTERRUPT ON CHANGE OF STATE
SET ISR BIT 7 ON DETECT OF CHANGE OF STATE AT IP2

BIT 3

NO INTERRUPT ON CHANGE OF STATE
SET ISR BIT 7 ON DETECT OF CHANGE OF STATE AT IP3

BIT 2

NO INTERRUPT ON CHANGE OF STATE
SET ISR BIT 7 ON DETECT OF CHANGE OF STATE AT IP2

BIT 1

NO INTERRUPT ON CHANGE OF STATE
SET ISR BIT 7 ON DETECT OF CHANGE OF STATE AT IPl

BIT 0

NO INTERRUPT ON CHANGE OF STATE
SET ISR BIT 7 ON DETECT OF CHANGE OF STATE AT IPO

Figure 0-13

2681 OUART: Auxiliary Control
Register (ACR)

0-10

ADDRESS 1 72024( RD)
07

INPUT
PORT
CHANGE

DELTA
BREAK
B

RxRDY/
FFULL
B

04
TxRDY
B

COUNTER
READY

DELTA
BREAK
A

RxRDY/
FFULL
A

TxRDY
A

(RDA7H) ~~,-----------------------------------------~•• (RDADH)

BIT VALUES

BIT 7

NO INTERRUPT
INPUT PORT CHANGE OF STATE DETECTED

BIT 6

NO INTERRUPT
CHANGE IN BREAK STATE DETECTED (CH. B)

BIT 5

NO INTERRUPT
RxRDY/FFULL CONDITION (CH. B)

BIT 4

NO INTERRU PT
TxRDY CONDITION (CH. B)

BIT 3

NO INTERRUPT
COUNTER READY CONDITION

BIT 2

NO INTERRUPT
CHANGE IN BREAK STATE DETECTED (CH. A)

BIT 1

NO INTERRUPT
RxRDY/FFULL CONDITION (CH. A)

BIT 0

NO INTERRUPT
TxTDY CONDITION (CH. A)

MA-0242-84

2681 OUART: Interrupt
Status Register (ISR)

Figure 0-14

ADDRESS 172026(WR)
07

INPUT
PORT
CHANGE

DELTA
BREAK
B

RxRDY/
FFULL
B

TxRDY
B

COUNTER
READY

DELTA
BREAK
A

RxRDY/
FFUL
A

TxRDY
A

(RDA7 H) ..

•

(ROAD H)

BIT VALUES
BIT 7

INTERRUPT DISABLED
INPUT PORT CHANGE OF STATE INTERRUPT ENABLED

BIT 6

INTERRUPT DISABLED
CHANGE IN BREAK STATE INTERRUPT ENABLED (CH. B)

BIT 5

INTERRUPT DISABLED
RxRDY/FFULL INTERRUPT ENABLED (CH. B)

BIT 4

INTERRUPT DISABLED
TxRDY INTERRUPT ENABLED (CH. B)

BIT 3

INTERRUPT DISABLED
COUNTER READY INTERRUPT ENABLED

BIT 2

INTERRUPT DISABLED
CHANGE IN BREAK STATE INTERRUPT ENABLED (CH. A)

BIT 1

INTERRUPT DISABLED
RxRDY/FFULL INTERRUPT ENABLED (CH. A)

BIT 0

INTERRUPT DISABLED
TxTDY INTERRUPT ENABLED (CH. A)

MA-0243-84

Figure 0-15

2681 OUART: Interrupt
Mask Register (IMR)
0-11

ADDRESS 172066(WR)
07

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OPO

(RDA7H)

~4~--------------------------------------". (RDAOH)

BIT VALUES

BIT 7

NOT USED
CONFIGURE OP7 AS COMPLIMENT OF TxRDYB

BIT 6

NOT USED
CONFIGURE OP6 AS COMPLIMENT OF TxRDYA

BIT 5

NOT USED
CONFIGURE OP5 AS COMPLIMENT OF Rx INTERRUPT

BIT 4

NOT USED
CONFIGURE OP4 AS COMPLIMENT OF Rx INTERRUPT
(RxRDY/FFULL A)

BIT 3

COMPLIMENT OP3 FOR MOD SPD SEL L FALSE OUTPUT
COMPLIMENT OP3 FOR MOD SPD SEL L TRUE OUTPUT

BIT 2

COMPLIMENT OP2 FOR HOST DTR L FALSE OUTPUT
COMPLIMENT OP2 FOR HOST DTR L TRUE OUTPUT

BIT 1

COMPLIMENT OP1 FOR PRTR DTR L FALSE OUTPUT
COMPLIMENT OP1 FOR PRTR DTR L TRUE OUTPUT

BIT 0

NOT USED
CONFIGURE OPO AS COMPLIMENT OF ENABLED RTSA

(RxRDY/FFULL B)

MA-0244-84

Figure D-16

2681 DUART: Output Port
Configuration Register (OPCR)

D-12

ADDRESS 177004(WR)
ADDRESS 177004(RD)
07

REMOTE
TEST

ANALOG
TEST

DATA
AVAIL

MODEM
TYPE

NO. OF
BITS

DATAl
TALK

COMM SELECT

I
(RDA7H)

.4.---------------------------------------..
~ (RDAOH)
BIT VALUES

BIT 7

REMOTE TEST DISABLED

BIT 6

ANALOG TEST DISABLED

BIT 5

NO DATA AVAILABLE
DATA AVAILABLE

BIT 4

DOMESTIC MODEM TYPE BELL 103
EUROPEAN MODEM TYPE V.21

BIT 3

10 BITS PER CHARACTER
9 BITS PER CHARACTER

BIT 2

TALK MODE
DATA MODE

BIT 0-1

00
01

EIA HOST PORT
NO CONNECTION

10
11

20 mA PORT
INTEGRAL MODEM

REMOTE TEST ENABLED

ANALOG TEST ENABLED

NOTE:
BIT 4 IS OVERRIDDEN BY MCWR
BIT50N(1)
MA-0245-84

Figure D-17

Comm/Modem Control: Comm Control Write
(CCWR) and Read Registers (CCRD)

D-13

ADDRESS 177006(WR)
07

NOT
USED

MODE
SELECT

MODEM
EMULATE

NOT
USED

OFF
HOOK
DRIVE

(RDA7HI ~4'---------------------------------------~~~(RDAOHI

BIT VALUES

BIT 6

ORIGINATE MODE
ANSWER MODE

BIT 5

EM ULA TE V.21 OR BELL 103
EMULATE BELL 212A

BIT 0

ENABLE OFF HOOK DRIVE
DISABLE OFF HOOK DRIVE

NOTE:
BIT 5 ON 111 OVERRIDES CCWR
BIT 4

Figure 0-18

Comm/Modem Control: Modem Control
write Register (MCWR)

ADDRESS 1 77006( RD)
07
DIAL
TONE
DETECT

06
MODE
SELECT

05
MODEM
AlB

04
CUT

03
TEST
IND

SWITCH
HOOK

OFF
HOOK
MODEM

OFF
HOOK
DRIVE

IRDA7HI .4~--------------------------------------~. IRDAOHI

BIT VALUES

BIT 7

DIAL TONE DETECTED
NO DIAL TONE DETECT

BIT 6

OUTPUT OF MCWR BIT 6 SELECTS ORIGINATE MODE
OUTPUT OF MCWR BIT 6 SELECTS ANSWER MODE

BIT 5

OUTPUT OF MCWR BIT 5 SELECTS BELL 103 OR V.21
OUTPUT OF MCWR BIT 5 SELECTS BELL 212A

BIT 4

COUPLER CUT THROUGH CONDITION

BIT 3

INTEGRAL MODEM IN TEST MODE
INTEGRAL MODEM IN NORMAL MODE

BIT 2

SWITCH HOOK CONDITION
NO SWITCH HOOK CONDITION

BIT 1

OFF HOOK MODEM CONDITION
NO OFF HOOK MODEM CONDITION

BIT 0

OUTPUT OF MCWR BIT 0 ENABLES OFF HOOK DRIVE
OUTPUT OF MCWR BIT 0 DISABLES OFF HOOK DRIVE

NO COUPLER CUT THROUGH CONDITION

MA-0247-84

Figure 0-19

Comm/Modem Control: Modem Control
Read Register (MCRD)

0-14

ADDRESS 173000 (RD/CPU)
(RD/CP)
ADDRESS OOH
07

NOT
USED

H
BLANK

DMA

DRAW

FIFO

FIFO
FULL

DATA
READY

EMPTY

(VDB7H) 44~--------------------------------------"~ (VDBOH)

BIT VALUES

BIT 7

NOT USED

BIT 6

1
0

HORIZONTAL BLANKING ACTIVE
HORIZONTAL BLANKING INACTIVE

BIT 5

1
0

ENABLE VERTICAL RETRACE
DISABLE VERTICAL RETRACE

1
0

DMA TRANSFER OCCURRING
NO DMA TRANSFER OCCURRING

BIT 3

1
0

GRAPHIC FIGURE DRAWING IN PROGRESS
NO DRAWING IN PROGRESS

BIT 2

1
0

ALL COMMANDS PROCESSED
COMMAND AVAILABLE FOR PROCESSING

FIFO FULL
FIFO NOT FULL

BIT 4

BIT 1

0
BIT 0

1
0

DATA AVAILABLE FOR CPUICP
NO DATA AVAILABLE

Figure 0-20

P07220 GOC Status Register

ADDRESS 174600 (WR/CPU)
ADDRESS COH
(WR/CP)
07

ERA

SVP

SGDC

SLU

SVEC

EVOM

SM1

SMO

(VDB7H) ~4'---------------------------------------~. (VDBOH)
BIT VALUES
BIT 7

ERASE SCREEN ENABLED

BIT 6

SELECT CHARACTER BUFFER PATTERN FOR LOGIC UNIT
SELECT VECTOR PATTERN REGISTER PATTERN FOR
LOGIC UNIT

BIT 5

SELECT OTHER THAN READ BACK MODE
SELECT READ BACK MODE

BIT 4

BYPASS EXTERNAL LOGIC UNIT

BIT 3

ENABLE TEXT MODE AND WRITE MASH BATCH
SELECT VECTOR MODE

BIT 2

DISABLE VOM OUTPUT. ENABLE WRITING TO VOM
ENABLE VOM. NORMAL DISPLAY

BIT 0-1

00
01
10
11

DISABLE SCREEN ERASE.

SELECT EXTERNAL LOGIC UNIT

SELECT MAP 0
SELECT MAP 1
SELECT MAP 2
SELECT MAP 3

MA-0249-84

Figure 0-21

Video Logic Mode Select Register 0
0-15

ADDRESS 174640 (WR/CPU)
ADDRESS DO H
(WR/CP)
07

NOT

NOT
USED

NOT

USED

SENO

SEN1

SDI

00
NOT
USED

(VDB7H) ~4~--------------------------------------~. (VDBOH)

BIT VALUES

BIT 3-2

00
01
10

BIT 1

DISABLE DMA SCROLL AND LINE ERASE MODES
NOT USED
ENABLE LINE ERASE

ENABLE DMA SCROLL

COUNT UP (INCREMENT)
COUNT DOWN (DECREMENT)
MA-0250-84

Figure 0-22

Video Logic Mode Select Register 1

ADDRESS 174540 (WK/CPU)
ADDRESS BOH
(WR/CP)
07

IF1

IFO

IB1

IBO

(VDB7 H)

~4~--------------------------------------". (VDBO H)

BIT VALUES

BIT 6-7

00
10
01
11

REPLACE WRITING
OVERLAY WRITING
(NOT USED)
COMPLIMENT WRITING

BIT 5

0/1

FOREGROUND INTENSITY VALUE PLANE 1

BIT 4

0/1

FOREGROUND INTENSITY VALUE PLANE 0

BIT 3

0/1

BACKGROUND INTENSITY VALUE PLANE 1

BIT 2

0/1

BIT 1

BIT 0

BACKGROUND INTENSITY VALUE PLANE 1
2 PLANE WRITING
SINGLE PLANE WRITING
PLANE 0 SELECTED
PLANE 1 SELECTED

MA-0251-84
.\

Figure 0-23

Video Logic Unit Register

0-16

APPENDIX E
VIDEO LOGIC WRITE MODE
PROGRAMMING OVERVIEW
REGISTER 0

(EN

(ERA)

(SVP)

(SGDC)

(SLU)

(SVEC)

(EVOM)

V~M

(VOJ2 H)

(SM17)

I (SMa)

(SEL JTW L)

(SEL VPAT H)

(SEL GDC H)

(VEC H)

(VOM1 H)

SELECTED MAP

(ERASE L)

(SENO)

(SEN1)

sCRolL EN H)

x
(SDI)

(DI! H)
(NOT USED)

(SELSDH)

WRITE MASK LATCH
06
07
05

(WE 7 LI ....> - - - - - - - - - - - - - - - - - - -...... (WEO L)

LOGIC UNIT REGISTER

(M1)

(MO)

(IF1 )

(IFO)

(IB1 )

(IBO)

(SP)

(PS)

1
(M1 H)

(IB1 H)

(IF1 H)
(MO H)

(IFO H)

(JH)
(IBO H)

(PS H)

NOTES
1, GDC COMMANDS:
• USE CURS COMMAND TO SET WORD ADDRESS AND PLANE SELECT:
• USE FIG COMMAND TO SET DIRECTION AND BYTE COUNT:
• USE WDAT COMMAND TO EXECUTE WORD/BYTE READ THEN
READ THROUGH FIFO:
2, "X" INDICATES DON'T CARE,
MA-0173-B4

Figure E-l

Mode 0 (Read Back Mode)
Programming Values
E-l

01
I

IERA)

ISVP)

ISGDCj

ISLU)

ISVECj

IEVOM)

lEN VlM H)

ISEl VPAT H)

ISEl GDC H)

IVEC H)

IVOMl H)

I ISMO)

ISEl E1T W L)

IVOJ2 H)

SELECTED MAP
ISM17)

IERASE l)

00
X

ISENO)

ISEN1)

ISDI)

SCRoL EN H)

IDIR H)
INOT USED)

ISEl SD H)

WRITE MASK LATCH
06
07
05

IWETL)~.~--------------------------------------•• IWEOl)

LOGIC UNIT REGISTER

ISET APPROPRIATELY)
IPS)

IMl H)

IIFl H)
IMO H)

IIBl H)
liFO H)

ISP H)
IIBO H)

IPS H)

NOTES

1. GDC COMMANDS:
• USE CURS COMMAND FOR SETTING WORD ADDRESS;
• USE FIG AND WDAT COMMAND FOR GENERATING WRITE ADDRESS;
• USE A16 FOR lOW/HIGH BYTE CONTROL;
2. "X' INDICATES DON'T CARE.

MA-0172-84

Figure E-2

Mode 1 (Text Mode)
Programming Values

E-2

I
1

(ERA)

(SVP)

(SGDC)

(SLU)

(SVEC)

(EVOM)

(SEL VPAT H)

(SEL GDC H)

(VEC H)

(VOM1 H)

II'

I (SMO)

(SEL EL W L)

(VOL H)

(EN VOM H)

SELECTED MAP
(SM17)

(ERASE L)

00
X

(SENO)

(SEN1)

(SDI)

SCRolL EN H)

(DIR H)
(NOT USED)

(SEL SD H)

WRITE MASK LATCH
07

4----------------------------------------._ (WEOL)

(WE T LI •

LOGIC UNIT REGISTER
07

(SET APPROPRIATELY)
(PS)

(M1 H)

(IF1 H)
(MO H)

(IB1 H)
(IFO H)

(SP H)
(IBO H)

(PS H)

NOTES

1. PROGRAM GDC FOR PATTERN OF ALL 1's, REPLACEMENT MODE;
2. "X" INDICATES DON'T CARE,

MA-0175-84

Figure E-3

Mode 2 (Vector Mode)
Programming Values

E-3

(EN

(ERAI

(SVPI

(SGDC!

(SLUI

(SVEC!

(EVOMI

V~M

(SEL VPAT HI

(SEL GDC HI

(VEC HI

(VOM1 HI

I (SMOI

(SEL JTW LI

(VOM2 HI

SELECTED MAP
(SM171

(ERASE LI

SCROLL
DIR
(SDII

(SENOI

(SEN 11

SCRoL EN HI

(DIR HI
(NOT USEDI

(SEL SD HI

WRITE MASK LATCH
07

• (WEO LI

(WE T LI •

LOGIC UNIT REGISTER
07

(M11

(Mal

(IF11

(IFOI

(IB11

(IBOI

(SPI

(PSI

(IB1 HI

(IF1 HI
(MO HI

(M) HI

(IFO HI

(IBO HI

(PS HI

NOTES
1 GDC COMMANDS:
• USE CURS COMMAND TO SET START OF SOURCE ADDRESS:
• USE FIG COMMAND TO SET WORD COUNT:
• USE WDAT COMMAND TO EXECUTE.
2. 'X' INDICATES DON'T CARE.

MA-0177-84

Figure E-4

Mode 3 (OMA Scroll Mode)
Programming Values

E-4

(ERA)

(SVP)

(SGDC)

(SLU)

(SVEC)

(EVOM)

(VOJ2 H)

(EN VOM H)

SELECTED MAP
(SM17)

I (SMa)

(SEL JT W LI

(SEL VPAT H)

(SEL GDC H)

(VEC H)

(VOM1 H)

(ERASE L)

(SENO)

(SEN1)

(SOl)

sCRolL EN H)

(DIR H)
(NOT USED)

(SEL SO H)

WRITE MASK LATCH
07

• (WEO L)

(WE T L) •

LOGIC UNIT REGISTER
07

INTENSITY

(M1)

(MO)

(IF1)

(IFO)

(M) H)

DESI~ED
(IB1)

I (IBO)

(IB1 H)

(IJ H)
(MO H)

(IFO H)

(SP)

(PS)

(JH)

(IBO H)

(PS H)

NOTES
1, SET VECTOR PATTERN REGISTER TO ALL a's:
2, REGISTER a VALUES IN EFFECT FOR ONE FRAME TIME:
3, "X" INDICATES DON'T CARE,

MA-0174-84

Figure E-5

Mode 4 (Screen Erase Mode)
Programming Values

E-5

(EN

SELEC+ED MAP

(ERA)

(SVP)

(SGDC)

(SLU)

(SVEC)

(EVOM)

V~M

(SEL

(VOM2 H)

(SM17)

1 (SMO)

W L)

(SEL VPAT H)

(SEL GDC H)

(VEC H)

(VOM1 H)

(ERASE L)

00
X

(SENO)

(SEN1)

(SOl)

(SCROL EN H)

(DI! H)
(NOT USED)

(SEL SO H)

WRITE MASK LATCH
07

• (WEO L)

(WE T L) •

LOGIC UNIT REGISTER
07

DESIRED
INTENSITY

(M1)

(MO)

IIF1)

liFO)

IIB1)

(M) H)

(lF1 H)
(MO H)

I (IBO)

IIB1 H)
(IFO H)

(SP)

(PS)

(JH)
(IBO H)

(PS H)

NOTES
1. USE FIG COMMAND TO SET WORD COUNT AND DIRECTION;
2. SET VECTOR PATIERN TO ALL O·s;
3. ·X· INDICATES DON·T CARE.
MA-018Q-84

Figure E-6

Mode 5 (Word/Line Erase Mode)
Programming Values

E-6

VT240 Series Technical Manual
EK-VT240-TM-OO 1

READER'S COMMENTS
Your comments and suggestions will help us in our efforts to improve the quality and usefulness of our
publications.
1. Which of the following most closely describes your job?
(a) Administrative support

(d) SCientist/Engineer

(b) Programmer/Analyst

(e) Systems Manager

(f) Sales

1 ,a

(g) Educator/Trainer

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(h) Computer Operator
(i) Other _ _ _ _ _ _ _ _ __

2. How many years of experience do you have with computers?
(a) Less than 1

(b) 1 to 3

(d) 7 to 9

(e) 10 or more

3. What did you like most about this manual?

4. What did you like least about this manual?

5. How do you rate this manual?
Indicate your opinion of the quality of the manual. For each aspect of quality, darken your response on the five-point scale,
where (1) = POOR and (5) = EXCELLENT
(a) Accuracy".""""""""".".""""""""""" ................... .
(b) Completeness .................................................................. .

c 1~

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c5,

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L2-,

,-3-,

,4)

,-5-,

c1-,

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c4::1

:::5::1

(d) Clearness of Language ................................................. .

,-1~

,-2::1

,-3-,

( 4)

c5-,

(e) Helpfulness of Index/Table of Contents ..................... .

(1:0

e2:o

e3:o

c4:o

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(f) Consistency in Presenting Information ................... .

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c2,

(3-,

c5_)

(g) Logical Organization ............................................ .

( 1)

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e3_)

c4::J

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(h) Visual Appeal ................. " ............................... .

( 1-,

c2:J

(3)

c4-,

(i) Relevance of Information .......................................... .

( 1-,

e2:J

(3)

c4=:J

c5)

U) Ease of Learning ........... .

,1-,

,2-,

c 3-,

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(m) Quality Relative to Other Digital Manuals

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( 5-,

(n) Quality Relative to Other Companies' Manuals.

,1:J

e2:J

c 3::J

c4)

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(k) Ease of Use ....................

. ..................... .

(I) YOUR OVERALL IMPRESSION ..... .

5_)

6. List any errors you found in the manual. (Reference page, table, or figure numbers.)

7. Do you have any additional comments?

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