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EK-VT220-TM-001

November 1984

226 pages

Original

11MB

Document:	VT220 Technical Manual
Order Number:	EK-VT220-TM
Revision:	001
Pages:	226
Original Filename:	http://bitsavers.org/pdf/dec/terminal/vt220/EK-VT220-TM-001_VT220_Technical_Manual_Nov84.pdf

OCR Text

EK-VT220-TM-001

•

VT220
Technical Manual

EK-VT220-TM-001

VT220
Technical Manual

Prepared by Educational Services
of
Digital Equipment Corporation

1st Edition, November 1984

Copyright 0 1984 by Digital Equipment Corporation
All Rights Reserved
Printed in U.S.A.
The reproduction of this material, in part or whole, is strictly
prohibited. For copy information, contact the Educational Services
Department, Digital Equipment Corporation, Maynard, Massachusetts
01754.
The information in this document is subject to change without
notice. Digital Equipment Corporation assumes no responsibility
for any errors that may appear in this document.
The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts.

mamaama
DEC
DECmate
DECnet
DECSsystem-10
DECSYSTEM-20

DECUS
DECwriter
DIGITAL
LA
MASSBUS
PDP

p/OS
Professional
Rainbow
RSTS
RSX
UNIBUS

VAX
VMS
VT
Work Processor

This equipment has been certified to comply with the limits for a
Class B computing device, pursuant to Subpart J of Part 15 of FCC
Rules. Only peripherals (computer input/output devices, terminals,
printers, etc.) certified to comply with the Class B limits may be
attached to this computer. Operation with noncertified peripherals
is likely to result in interference to radio and television
reception. It has been type tested and found to comply with the
limits for a Class B computing device in accordance with the
specifications in Subpart J of part 15 of FCC Rules, which are
designed to provide reasonable protection against such
interference in a residential installation. However, there is no
guarantee that interference will not occur in a particular
installation. If this equipment does cause interference to radio
or television reception, which can be determined by turning the
equipment off and on, the user is encouraged to try to correct the
difference by one or more of the following measures:
reorient the receiving antenna
relocate the computer with respect to the receiver
move the computer away from the receiver
plug the computer into a different outlet so that computer
and receiver are on different branch circuits.
If necessary, the user should consult the dealer or an experienced
radio/television technician for additional suggestions. The user
may find the following booklet prepared by the Federal
Communications Commission helpful:
"How to Identify and Resolve Radio-TV Interference Problems".
This booklet is available from the US Government Printing Office,
washington, DC 20402, Stock No. 004-000-00345-4.

CONTENTS

INTRODUCTION
CHAPTER ·.1

SYSTEM INTRODUCTION

1.1
1.2
1. 2.1
1. 2. 2
1. 2.3
1.3
1.4
1.5
1.6
1. 6.1
1. 6.2
1. 6. 3
1. 6.4

General

CHAPTER 2

CONTROLS, INDICATORS, AND CONNECTORS

2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.6.1
2.3.6.2
2.3.7
2.4

General . . . . . . . . . . . . . . . . .
Monitor Assembly (VT220)
Keyboard (LK20l)
Main Keypad
Editing Keypad
Auxiliary Keypad
Top-Row Function Keys
Visual Indicators
Audible Indicators
Audible Keyc1ick
Be 11 • . . . . . . . . • . . .
Connector Cable
Modem Option (VT22X-AA)

CHAPTER 3

SYSTEM OVERVIEW

3.1
3.2
3.2.1
3.2.2

General •••••••••
Operating States
Set-Up
•••••
Local

••.•••.••••••••.••••••

Physical Description ••.••••••
Monitor Assembly (VT220)
Keyboard (LK20l) ••••••..
Modem Module Option (VT22X-AA) •••••
Display Characteristics and Capabilities
Communication Environment
••••••
Major Operating States
Operating Modes ••••••••••••
VT100 Mode ••••••••••••••
VT200 Mode, 7-Bit Controls
VT200 Mode, 8-Bit Controls •••••••••
VT52 Mode ••••••••••••••••••••••

1-1
1-1
1-2
1-2
1-3
1-3
1-4
1-4
1-4
1-5
1-5
1-5
1-5

2-1
2-1
2-3
2-5
2-6
2-6
2-6
2-8
2-8
2-'9
2-9
2-9
2-10

3-1
3-1
3-1
3-2

iii

3.2.3
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.4

On-Line ••••••.••
System Architecture
CPU Logic ••••••
Video Logic •••••
System Communication Logic
Modem Option (VT22X-AA)
Power Supply .•.•••••
Keyboard
••••••
Monitor Components
System Interaction •••••

CHAPTER 4

CPU LOGIC

4.1
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
4.3
4.4

Major Circuits and Components
Central Processor unit (CPU)
8051 CPU Internal Circuits
8051 CPU Transactions
Address Latch ••••••••.
Read Only Memory (ROM)
Data Buffer
•••••
Screen RAM
Attribute RAM
Select Decoder ••••••.•••.
Keyboard Interface (I/F)
Nonvolatile RAM (NVR) ••••••••••
Configuration Register ••••.
Signal Descriptions .•••••••
. •••••••
Schematic Reference Information
•.••••••••

CHAPTER 5
5.1
5.2
5.2.1

Genera 1

.••••••••••••••••••.•••.•

3-2
3-2
3-3
3-4
3-4
3-5
3-5
3-5
3-6
3-6

4-1
4-2
4-3
4-4
4-5
4-8
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-16

SYSTEM COMMUNICATION LOGIC
General

.••.•••••••.•••••...••...•.•.••...••.

5.2.1.1
5.2.1.2
5.2.1.3
5.2.2
5.2.3
5.2.4
5.2.5
5.3
5.4

Major Circuits and Components •••.••••••••.••
Dual Asynchronous Receiver/Transmitter
(DUART)
2681 DUART Internal Circuits
2681 DUART Addresses ••••••
2681 DUART Timing Diagrams
Host Data Mux ••••••••••
Printer Interface (I/F)
EIA Host Interface (I/F)
20 rnA Interface (I/F)
Signal Descriptions •••••••
Schematic Reference Information

CHAPTER 6

VIDEO LOGIC

6.1
6.2
6.2.1
6.2.1.1
6.2.1.2

General . . . . . . . . . . . . . . . . . . . . . .
Major Circuits and Components
CRT Controller ••••••••.•••••
9007 VPAC Internal Circuits
9007 VPAC Addresses ••••••••

5-1
5-2
5-3
5-4
5-6
5-7
5-8
5-10
5-12
5-13
5-14
5-19

6-1
6-2
6-4
6-5
6-6

9007 VPAC Transactions ••••••••••.•.••.••
6-8
Timing Generator •••..•••••••••••••••••••••••• 6-11

6.2.1.3
6.2.2
6.2.3
6.2.4
6.2.4.1
6.2.4.2
6.2.4.3
6.2.5
6.2.6
6.2.6.1
6.2.6.2
6.2.7
6.3
6.4

Character Output Circuit ••••••••••.•.•••
Attribute Circuits •••••••••••••••.•••••••••••
Video Converter ••••••••••••••••••••••••••••••
Conversion Control .•.•••••.•.•••••••.••••
Parallel-to-Serial (p/S) Converter •..•••
Video Output ••.•••.••••••••••••••••••••••••••
Signal Descriptions •••••••••••.•••••••••••••••••••
Schematic Reference Information •••••••••••••••••••

CHAPTER 7

KEYBOARD (LK201)

7.1
7.2
7.3
7.3.1
7.3.1.1
7.3.1..2

Physical Description .•••.••..•.•••••••••••••••••••
Functional Description •••••••••••••••••••••••••.••
Keyboard Operation Overview •••..••.•••••.••••
Keyboard Scanning ••.••••.••••••.••••••.•
Control of Audio Transducer and

7.3.2
7.3.2.1

Keyboard Firmware Functions ••.••••••.•••••••.
Functions Not Changed by CPU

7.3.2.2
7.3.2.3

Functions Changed by CPU Insructions ••••
Firmware Functions Changed By CPU

7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.4.1
7.4.4.2
7.4.5
7.4.6
7.4.7
7.5
7.5.1
7.5.2
7.5.2.1

Detailed Keyboard Circuit Description •..••••••••••
Keyboard Matrix Scanning .•••••••••••••••••.••
Audio Transducer Control Circuit •••.••••.•.••
Indicator (LED) Control Circuit ••••••••••••••
Keyboard Communication ••••.••..••••••••.•••••
Keyboard Transmit Mode ••••••••••.••••••.
Keyboard Receive Mode •.•••••••••••••••••
Reset Signal for 8051 Microprocessor •••••••••
Hardware Keyboard Identification (ID) ••.•••••

Blank Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15

Character Generator ••••••••••.•••••••••••••.• 6-15
Access Mux ••••••••••••••••••••••••••.••• 6-17
Line Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ind ica tors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol tage Suppl ies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Keyboard Programming .••••••••••.••••••••..••..••••
Keyboard Layout and Key Identification •.•••••
Me des

••••••••..•••••••.•.•.•••.•..•.•......•.

6-21
6-24
6-26
6-26
6-28
6-30
6-31
6-41

7-1
7-2
7-4
7-4
7-5
7-5
7-5
7-5
7-6
7-6
7-7
7-7
7-14
7-14
7-16
7-16
7-16
7-17
7-17
7-17
7-17
7-17
7-23

Special Considerations Regarding
Autorepeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23

7.5.2.2
7.5.2.3
7.5.3
7.5.3.1
7.5.3.2
7.5.4
7.5.4.1

Special Considerations Regarding
Down/Up Mode •••••••.••••••••.••••.•••.•• 7-25
Autorepeat Rates •••••••••••••••••••••••• 7-25
Keyboard Peripherals ••••.•.•••.•••••••••••••• 7-25
Audio . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . 7-25

Indicators (LEOs) •••••••••••••••••••.•.• 7-26
Keyboard-to-System Module Protocol ••••••••••• 7-26
Keycode Transmission •••••.•..•••.•••.••• 7-26

7.5.4.2
7.5.4.3
7.5.5
7.5.5.1
7.5.5.2
7.5.5.3
7.5.5.4
7.5.6
7.5.6.1
7.5.6.2
7.5.6.3
7.5.6.4
7.5.6.5
7.5.7
7.5.7.1
7.6

Special Code Transmission •••••
• •••••• 7-26
Power-Up Transmission
•••••••••••
7-28
System Module to Keyboard Protocol •••••••
7-29
Commands •••••••••••
• ••••••••••••••
7-30
Parameters •••••••••
••••••
• ••••
7-30
Peripheral Commands ••••
7-30
Mode Set Commands ••••••••••
• ••••
7-35
Special Considerations
•••••••••• 7-37
Error Handling •••••••••••••••••••••••••• 7-37
Keyboard Locked Condition
••••••••
7-37
Reserved Code ••••••••••••••••••••••••
7-38
Test Mode
•••••••••
• ••••
7-38
Future Expansion ••••••••
• •••••••••• 7-38
Default Conditions
••••••
7-38
Audio Volume
7-38
Specifications
•••••
7-39

CHAPTER 8

MONITOR CIRCUITS

8.1
8.2
8.2.1
8.2.2
8.2.2.1
8.2.2.2
8.2.2.3
8.2.3
8.2.4
8.2.4.1
8.2.4.2
8.2.5
8.2.6
8.2.7

General ........................... .
Major Circuits and Components ••••••
Video Amplifier (Amp) Circuit
Horizontal Deflection Circuit
Horizontal Processor Circuit ••••
Horizontal Driver Circuit
Horizontal Output Circuit •••••
Flyback Transformer Circuit
vertical Deflection Circuit
•••••
vertical Processor Circuit ••••••••
Vertical Output Circuit •••••••
Dynamic Focus •••••••••••••
• •••••
Brightness Control ••••••••

.. . . . . . . . . . . . . .
.. . .

...

CRT Dev ice •••••••••••••••••••••••

CHAPTER 9

POWER SUPPLY

9.1
9.2
9.2.1
9.2.2
9.2.2.1
9.2.2.2
9.2.2.3
9.2.2.4
9.2.2.5
9.2.3
9.2.4

Major Circuits and Components •••••
• ••
AC Input Components ••••••••••••••
AC Conversion Circuits ••••••••••
+12 V Start Up Circuit •••••
Input Rectification Circuit •••••••••
DC Output Circuits ••••••••••
Overcurrent Protect Circuit •••••
Pulse Width Modulator Circuit
DC OK Circuit •••••••
• ••••••••
DC Input Components •••
• ••••••••

General •••••••.•..•.•.••••.•.••••••••••.

8-1
8-2
8-3
8-4
8-4
8-6
8-7
8-11
8-12
8-12
8-14
8-15
8-16
8-17

...... . 9-1
9-2
9-3
9-4
9-6
9-7
9-8
9-11
9-12
9-13
9-14

APPENDICES
A
B

SPECIFICATIONS •••••••••••••
VT220/VT102 DIFFERENCES
REGISTER BIT VALUES •••••

.........

A-l
B-1
C-l

FIGURES
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3
3-4
3-5
3-6
3-7
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-19
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-19

VT229 Series Terminals •••••••••••.•••••••••••••••••
1-1
Monitor Assembly Major Components •••••••••••••••••
1-2
Monitor Assembly Controls, Indicators,
and Connectors •.••••••••••••••••••••••••••••••••••
2-1
Display Controls and Tilt Leg Release Button ••••••
2-2
LK291 Keyboard Module •••••••••••••••••••••••••••••
2-4
Ma i n Keypad •••••••••••••••••••••••••••••••••••••••
2-5
Editing Keypad ••••••••••••••••••••••••••••••••••••
2-6
Auxiliary Keypad ••••••••••••••••••••••••••••••••••
2-6
Top-Row Function Keys •••••••••••••••••••••••••••••
2-7
BCC91 Cable Connector (Keyboard End) ••••••••••••••
2-9
Modem Module Controls, Indicators, and
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
VT229 Series Terminal Functional Block Diagram ••••
3-3
System Interaction in Set-Up ••••••••••••••••••••••
3-6
System Interaction in Local •••••••••••••••••••••••
3-7
System Interaction On-Line: Data to Host
(Null-Modem) ••••••••••••••••••••••••••••••••••••••
3-7
System Interaction On-Line: Data from Host ••••••••
3-8
System Interaction On-Line: Data to Host (Modem) ••
3-8
System Interaction On-Line: Data from Host
(Modem) •••••••••••••••••••••••••••••••••••••••••••
3-9
VT229 Series Terminal Functional Block Diagram ••••
4-1
CPU Logic Block Diagram •••••••••••••••••••••••••••
4-2
CPU Block Diagram .......•......•....•••.•••.•••••.
4-3
8951 CPU Internal Block Diagram •••••••••••••••••••
4-4
8951 CPU Instruction Fetch Timing Diagram •••••••••
4-6
8951 CPU Read Transaction Timing Diagram ••••••••••
4-6
8951 CPU Write Transaction Timing Diagram •••••••••
4-6
8951 CPU Address Map: ROM •••••••••••••••••••••••••
4-7
8951 CPU Address Map: Non-ROM •••••••••••••••••••••
4-7
Address Latch Block Diagram •••••••••••••••••••••••
4-8
ROM Block Diagram ••..••.•.••.••••.•••....••••••••.
4-8
Data Buffer Block Diagram •••••••••••••••••••••••••
4-9
Screen RAM Block Diagram •••••••••••••••••••••••••• 4-19
Attribute RAM Block Diagram ••••••••••••••••••••••• 4-11
Select Decoder Block Diagram •••••••••••••••••••••• 4-12
Keyboard I/F Block Diagram •••••••••••••••••••••••• 4-14
NVR Block Diagram ••••••••••••••••••••••••••••••••• 4-15
Configuration Register Block Diagram •••••••••••••• 4-16
VT229 Series Terminal Functional Block Diagram ••••
5-1
System Communications Logic Block Diagram •••••••••
5-3
DUART Block Diagram •••••••••••••••••••••••••••••••
5-4
2681 DUART Internal Circuits Block Diagram ••••••••
5-5
2681 DUART: Transmit Data Timing Diagram ••••••••••
5-8
2681 DUART: Receive Data Timing Diagram •••••••••••
5-9
Host Data Mux Block Diagram •••••••••••••••••••••••
5-9
Printer I/F Block Diagram ••••••••••••••••••••••••• 5-19
Logic Board (Jl)/PS and Monitor Board (J2)
Interconnection Diagram ••••••••••••••••••••••••••• 5-11
EIA Host I/F Block Diagram •••••••••••••••••••••••• 5-12

vii

5-11
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
7-1
7-2
7-3
7-4
7-5
7-6
7-7A
7-7B
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
8-1
8-2
8-3
8-4
8-5

20 rnA I/F Block Diagram •••••••••••••••••••••••••••
VT220 Series Terminal Functional Block Diagram ••••
Video Logic Block Diagram •••••••••••••••••••••••••
CRT Controller Block Diagram ••••••••••••••••••••••
9007 VPAC Internal Block Diagram ••••••••••••••••••
9007 VPAC: DMA Transaction Diagram ••••••••••••••••
9007 VPAC: Composite Sync and Blanking Timing
Diagram •.•..............................•.•.......
9007 VPAC: Horizontal Timing ••••••••••••••••••••••
9007 VPAC: vertical Timing ••••••••••••••••••••••••
Timing Generator Block Diagram ••••••••••••••••••••
DMA and Visible Line Timing Diagram •••••••••••••••
Blank Circuits Block Diagram ••••••••••••••••••••••
Character Generator Block Diagram •••••••••••••••••
Access Mux Block Diaqram ••••••••••••••••••••••••••
Line Buffer Block Diagram •••••••••••••••••••••••••
Line Buffer RAM Memory Map ••••••••••••••••••••••••
Data Input Buffers Block Diagram ••••••••••••••••••
Character Output Circuits Block Diagram •••••••••••
Character ROM Map: Overview •.••.••.••..••.•...•..•
Character ROM Map: CRM32-255 and
Special Graphics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Character ROM Map: CRM0-31 ••••••••••••••••••••••••
Attribute Circuits Block Diagram ••••••••••••••••••
Video Converter Block Diagram •••••••••••••••••••••
Conversion Control Block Diagram ••••••••••••••••••
Dot Matrix Display and Dot Stretching •••••••••••••
Effects of Dot Stretching •••••••••••••••••••••••••
P-S Conversion Block Diagram ••••••••••••••••••••••
Video Output Block Diagram ••••••••••••••••••••••••
VT220 Series Terminal Functional Block Diagram ••••
LK201 Keyboard

••••••••••••••••••••••••••••••••••••

Keyboard Cable Connections ••••••••••••••••••••••••
LK201 Keyboard Block Diagram ••••••••••••••••••••••
Matrix Scanning Block Diagram •••••••••••••••••••••
Example of Ghost Key Generation •••••••••••••••••••
LK201-AA Keyboard Layout •••••••••••••••••••••••• ~.
LK201-AA Keyboard Layout ••••••••••••••••••••••••••
Beeper Control Circuit ••••••••••••••••••••••••••••
Indicator (LED) Control Circuit •••••••••••••••••••
Keyboard Transmit and Receive Character Format ••••
System Module to Keyboard Protocol •.•.•.•.•.••••••
Indicator (LED) Parameter •••••••••••••••••••••••••
Indicator (LED) Layout ••••••••••••••••••••••••••••
Audio Volume Parameter ••••••••••••••••••••••••••••
Set Main Array to Down/Up Example •••••••••••••••••
Set Main Array to Autorepeat Example ••••••••••••••
Change Rates in Buffer 3 Example ••••••••••••••••••
VT220 Series Terminal Functional Block Diagram ••••
Monitor Circuits Block Diagram ••••••••••••••••••••
Video Amplifier Circuit Diagram •••••••••••••••••••
Horizontal Deflection Circuit Block Diagram •••••••
Horizontal Processor Circuit Diagram ••••••••••••••

viii

5-13
6-1
6-3
6-4
6-5
6-9
6-9
6-10
6-10
6-12
6-13
6-15
6-16
6-17
6-18
6-20
6-20
6-21
6-22
6-23
6-24
6-25
6-27
6-27
6-28
6-28
6-29
6-30
7-1
7-2
7-3
7-4
7-7
7-8
7-12
7-13
7-15
7-15
7-16
7-29
7-33
7-33
7-33
7-35
7-35
7-36
8-1
8-2
8-3
8-5
8-5

8-6
8-7
8-8
8-9
8-10
8-11

Horizontal Driver Circuit Diagram •••••••••••••.•••
Horizontal Output Circuit Diagram •••••••••••••••••
Horizontal Deflection Waveform •••••••••••••••••.••
Horizontal Trace: Scan from Center to Right
Side of Screen (T0 Time) ••••••••••••••••••••.•.•••
Horizontal Retrace: Move to Center from
Right Side (Tl Time) •••••••••••••••••••••••••••.••
Horizontal Retrace: Move to Left Side from
Center

8-12
8-13
8-14
8-lS
8-16
8-17
8-18
8-19
9-1
9-2
9-3
9-4
9-S
9-6
9-7
9-8
9-9
9-10
9-11
C-l
C-2
C-3

C-4
C-S
C-6
C-7
C-8
C-9
C-10
C-ll
C-12
C-13

C-lS

••••••••••••••.••••••••.••••••••••

CRT Dev ice •••••.•••.•••••.•.••••••••••••••••••••••

VT220 Series Terminal Functional Block Diagram •.••
Power Supply Block Diagram ••••••••••••••.•••••.•••
AC Input Components Block Diagram ••••••••••.••••••
AC Conversion Circuits Block Diagram ••••.•••••••••
+12 V Start Up Circuit Diagram ••••••••••.•••••••.•
Input Rectification Circuit Diagram •••••••••••••••
DC Output Circuits Diagram •••••••••••.••••••••••••
Overcurrent Protect Circuit Diagram •••••••••••••••
Pulse width Modulator Circuit Diagram •••••••••••••
DC OK Circuit Diagram •••••••••••••••••••••••••••••
DC Input Circuits Diagram .•••••••••••••••.••••••••
2681 DUART: Mode Register 1 (MRl)
(Channel A and B) •.•••.•••••.•••••••••••••••••.•••
2681 DUART: Mode Register 2 (MR2)
(Channel A and B) •••••••••••••••••••••••••••••••••
2681 DUART: Status Register (SR)
(Channel A and B) •.••.••••••••••••••••••••.•••••••
2681 DUART: Data Clock Selection Register
(DCSR) (Channel A and B) •••••••••••••••••••••.•.••
2681 DUART: Command Register (CR)
(Channel A and B) ••••••••.••••••••••••••••••••••••
2681 DUART: Receive/Transmit Data Registers
(RDR/TDR) (Channel A and B) •.••.••••••••••.•••••••
2681 DUART: Input Change Register (ICR) •••••••••••
2681 DUART: Auxiliary Control Register (ACR) ••••••
2681 DUART: Interrupt Status Register (ISR) •••••••
2681 DUART: Interrupt Mask Register (IMR) •••••••••
2681 DUART: Counter Timer/upper (CTUR)
and Lower (CTLR) Registers ••••••••••••••••••••••••
2681 DUART: Input Port Register (IPR) •••••••••••••
2681 DUART: Output Port Configuration Register
( 0 PC R )

C-14

(T2 Time)

Horizontal Trace: Scan to Center from Left
Side of Screen (T3 Time) •••••••••.•••••••.•.••••••
Flyback Transformer Circuit Diagram •••.•••••••••••
vertical Deflection Circuit Block Diagram •••••••••
vertical Processor Circuit Diagram •••••••••..•.•••
vertical Output Circuit Diagram •••••••••••••••••••
Dynamic Focus Circuit Diagram •..••••••••••••••••••
Brightness Control Circuit Diagram •••••••.••••••••

••••••••••••••••••••••••••••••••••••••••••••

8-6
8-7
8-8
8-9
8-9
8-10
8-10
8-11
8-13
8-13
8-14
8-lS
8-16
8-17
9-1
9-2
9-3
9-4
9-7
9-7
9-8
9-11
9-12
9-13
9-14
C-l
C-2
C-3

C-4
C-S
C-S
C-6
C-7
C-8
C-8
C-9
C-9
C -10

9007 VPAC: Characters Per Horizontal
Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-l0'
9007 VPAC: Characters Per Data Row Register ••••••• C-ll

C-16
C-17
C-18
C-19
C-20
C-21
C-22
C-23
C-24
C-25
C-26
C-27
C-28
C-29
C-30
C-31

9007 VPAC: Horizontal Sync Delay Register •••••••••
9007 VPAC: Horizontal Sync Width Register •••••••••
9007 VPAC: vertical Sync width Register •••••••••••
9007 VPAC: vertical Sync Delay Register •••••••••••
9007 VPAC: Configuration/Skew Register ••••••••••••
9007 VPAC: Data Rows Per Frame Register •••••••.•••
9007 VPAC: Scan Lines Per Data Row Register ••...••
9007 VPAC: Scan Lines Per vertical Period
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9007 VPAC: Control Register ••••••••••.•••••••••.••
9007 VPAC: Table Address Register •••••••••••••••••
9007 VPAC: Row Attribute Register •••••••••••••••••
9007 VPAC: Data Row Start Register ••••••••••••••••
9007 VPAC: Data Row End Register ••••••••••••••••••
9007 VPAC: Smooth Scroll Offset Register ••••••••••
9007 VPAC: Vertical/Horizontal Cursor Registers •••
9007 VPAC: Status Register •••••••••••••••••••••.••

C-11
C-12
C-12
C-12
C-13
C-13
C-14

8051 CPU Addresses (Non-ROM) •••••.•.••••••••••••••
CPU Logic Signal Descriptions ••••••••••••••••••.••
CPU Logic Schematic References ••••••••••••••••••••
2681 DUART Addresses ••••••••••••••••••••••••••••••
System Communication Logic Signal Descriptions ••.•
System Communication Logic Schematic References •••
9007 VPAC Internal Addresses ••••••••••••••••••••••
Video Logic Signal Descriptions •••.•••••••••••••••
Video Logic Schematic References •••••••.••••••••.•
Keyboard Matrix . . . • . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . .
Keyboard Functional Divisions .••••••••••••.•••••••
Keycode Translation Table •••••••••.•••••••••••••••
Peripheral Commands in Hexadecimal •••••••••••••••••
Keyboard Division Default Modes •••••••••••••••••••
Default Rates in Autorepeat Buffers •••••••••••.•••
Input Voltage Specifications •••••••••••••••••.••••
Output Voltage Specifications •••••••••••.•••••••••

4-13
4-17
4-22
5-7
5-14
5-20
6-7
6-32
6-42
7-9
7-18
7-19
7-32
7-39
7-39
9-5
9-9

C-14
C-15
C-15
C-16
C-16
C-17
C-17
C-18
C-18

TABLES
4-1
4-2
4-3
5-1
5-2
5-3
6-1
6-2
6-3
7-1
7-2
7-3
7-4
7-5
7-6
9-1
9-2

INTRODUCTION

GENERAL
This manual provides information to aid field service engineers
and other personnel trained by Digital Equipment Corporation in
the isolation of VT22~ Series terminal malfunctions. To this end,
this manual identifies the major circuits within the VT22~ Series
terminal and provides functional descriptions of those circuits.
Where appropriate, only summarized discussions of operating and
programming information is presented; and only to the extent
necessary to understand how a specific hardware component or
circuit functions.
MANUAL ORGANIZATION
The first three chapters of this manual provide an introduction to
the VT22~ Series terminal.
Chapter I
terminal.

provides

brief

introduction

the VT22~ Series

Chapter 2 provides brief descriptions of all VT22~ Series terminal
controls, indicators, and connectors.
Chapter 3 provides an overview of the VT22~ Series terminal system
interactions.
Chapters 4 -- 9 provide a functional breakdown and description of
the major logic circuits that comprise the VT22~ Series terminal.
Chapter 4 explains the CPU logic, responsible for overall control
of VT22~ Series terminal operation.
Chapter 5 explains the system communication logic, responsible for
communication with host and auxiliary devices.
Chapter 6 explains the video logic, responsible for developing
output to monitor circuits.
Chapter 7 explains
operator input.

the

LK2~1

keyboard module, responsible for

Chapter 8 explains the monitor circuits and the cathode ray tube
(CRT), responsible for visual output to the operator.
Chapter 9 explains the power supply, responsible for converting ac
input to dc potentials needed for terminal operation.
The final part of this manual is made up of appendices which
provide specification, differences information, and programming
reference data.
Appendix A describes specifications for the VT220 Series terminal.
Appendix B describes differences between the VT220 Series terminal
and the VT102 terminal.
Appendix C provides summary of bit values for register devices.
RELATED DOCUMENTATION
The following is a list of related documents for the VT220 Series
terminal.
VT220 Series Documentation
Pocket Service Guide - EK-VT220-PS
Programmer Reference Manual - EK-VT220-RM
Programmer Pocket Guide - EK-VT220-HR
Owner's Manual - EK-VT220-UG
Installation Guide - EK-VT220-IN
Video Terminal IPB - EK-VT220-IP
Modem User's Guide - EK-VT22M-UG
Maintenance Print Sets
VT220 (terminal assembly) - MP-01732-01
LK201 (keyboard module) - MP-01395-00
VT22X-AA (modem module) - 70-21205-01

xii

CHAPTER 1
SYSTEM INTRODUCTION

1.1

GENERAL

The VT229 Series terminal is a 1/4-page (up to 24 displayable
lines of text)
conversational terminal that uses ANSI standard
functions to create, store, and edit text.
1.2

PHYSICAL DESCRIPTION

The VT229 terminal (Figure 1-1) consists of up to three units: a
monochrome moni tor/terminal module, a keyboard, and an optional
modem module.
NOTE
Specifications
for the VT229 Series
terminal are provided in Appendix A.

MA·1460-838

Figure 1-1

VT229 Series Terminals

1-1

MONITOR
MODULE

PS AND
MONITOR
BOARD

LOGIC
BOARD

Figure 1-2

1.2.1

Monitor Assembly
Major Components

Monitor Assembly (VT220)

The monitor assembly is the center of the terminal. Figure 1-2
shows the major monitor assembly components.
•

Logic board -- contains the components needed to control
terminal operation.

•

Power supply (PS)
and monitor board
contain the
components used to convert ac input to the dc voltages
required by the terminal, as well as circuits used to
drive the cathode ray tube (CRT).

•

Cathode Ray Tube
terminal operator.

•

Communication ports
provide for cable connection
between the monitor assembly and a local host (ErA or 20
rnA connection), remote host (via a modem), keyboard, and
printer.

1.2.2

(CRT)

provides

visual output to

Keyboard (LK201)

The VT220
features.

terminal

uses

the

LK201 keyboard with the following

provide

visual indication of operational

•

Four LEOs
conditions.

•

Typewriter-Style
entry.

•

Auxiliary keypad
which
have
their
programming.

keypad

contains

keys for text

contains 18 keys, including 4 keys
function assigned by application

1-2

•

Editing keypad -- contains 6 screen function keys, and 4
cursor movement keys.

•

Top-Row function keys -- are 20 keys aligned across the
top of the keyboard which are provided for various
functions.

A description of controls and indicators (Chapter 2) explains in
greater detail how the LK201 keyboard functions when used with the
VT220 terminal.
1.2.3

Modem Module Option (VT22X-AA)

The optional modem provides telephone line communication with a
remote host. The module mounts beneath the monitor assembly,
raising the actual height of the monitor by about 1 1/2 inches.
1.3

DISPLAY CHARACTERISTICS AND CAPABILITIES

The VT220 terminal's display capabilities are upward compatible
with the text capabilities of the VT102 terminal.
The terminal has four text modes. Three modes execute standard
ANSI functions
(VT100 mode, VT200 mode with 7-bit controls, and
VT200 mode with 8-bit controls), and one mode executes Digital
private
functions
(VT52
mode) •
The following major text
capabilities are available within these various modes.
•

24 rows of text with either 80 or 132 characters per row
(characters are formed within a 7 X 9 dot matrix in a 10
X 10 cell for 80 characters per row, and within a 7 X 9
dot matrix in a 9 X 10 cell for 132 characters per row)

•

Hard character set of 288 characters, with set made up of
256 characters in Digital's control representation mode
(CRM)
set, 31 characters from Digital's special graphics
set, and one character, the reverse question mark, used
as an error character

•

Down-Line loadable character set

•

Reverse video

•

Underline

•

Double height/width characters, on a line-to-line basis

•

Bold/normal intensity

•

Character blinking

•

ANSI compatible control functions
1-3

1.4

COMMUNICATION ENVIRONMENT

The major
following.

communications

features

the terminal include the

communications

•

Asynchronous
second

•

EIA RS232C host port

•

host
20
rnA
communications

•

9-pin EIA RS232C printer port

•

7- or a-bit character formats

•

BNC connector
slave monitor

port

for

passive

19.2K

only

bits per

rnA

loop

for composite video output to an optional

NOTE
The
composite
video
output is an
RS179-1ike output; however, the use of
dc coupling is not in strict agreement
with RS179 specifications.
1.5

MAJOR OPERATING STATES

The VT220 Series terminal has three major operating states.
•
•
•

Set-Up
On-Line
Local

The operating states are described in greater detail in the system
overview (Chapter 3).
1.6

OPERATING MODES

The VT220 Series terminal has four major operating modes which can
be selected either from the keyboard (while in set-up), or by the
host (via control codes).
•
•
•
•

VT100 mode
VT200 mode, 7-bit controls
VT209 mode, a-bit controls
VT52 mode

1-4

1.6.1

VT1~~

Mode

The VT1~~ mode executes standard ANSI functions and emulates the
text mode functionality of Digital's VT1~2 terminal. (VT1~2/vT220
differences are described in Appendix B).
The VT10~ mode provides some backward compatibility with existing
software written for the VT1~2 terminal (when in VT100 mode, the
VT22~
responds as a service level, class 2 terminal, and VT1~~
programs
which
do
not
recognize this class of terminal
functionality will not execute on the VT220). This mode restricts
use of the keyboard to those keys which have a direct functional
counterpart at the VT102's keyboard. All data is restricted to
7-bit format, and only ASCII, UK, or special graphics characters
are generated.
1.6.2

VT2~~

Mode, 7-Bit Controls

This mode supports Digital Multinational Characters or National
Replacement Character sets, depending on the character set mode
selected. Both character groups can be accessed via the keyboard
or from the host computer via control codes. This operating mode
also provides some backward compatibility for existing VT10~
software.
1.6.3

VT2~~

Mode, 8-Bit Controls

This mode supports Digital Multinational Characters or National
Replacement Character sets, depending upon the character set mode
selected. As in the VT200 mode, 7-bit controls, both character
groups can be accessed via the keyboard or programmed control
codes.
1.6.4

VT52 Mode

The VT52 mode is a text mode that executes Digital private
functions, but not ANSI. This mode has a degree of compatibility
with a VT1~2 operating in that terminal's VT52 mode.
The VT52 mode restricts use of the keyboard to those keys which
have a direct functional counterpart at the VT102's keyboard when
the VT1~2 is in VT52 mode. All data is restricted to 7-bit format,
and only ASCII, UK, or special graphics characters are generated.

1-5

CHAPTER 2
CONTROLS, INDICATORS, AND CONNECTORS

2.1

GENERAL

This chapter provides information about the terminal's controls,
indicators, and connectors, including those for the VT22X-AA modem
option.
It also includes information on the various keypads and
special function keys of the LK201 keyboard.
2.2

MONITOR ASSEMBLY (VT220)

The monitor assembly controls, indicators, and connectors (Figures
2-1 and 2-2) are as follows.
Power controls, indicators, and connectors
•

Power on/off switch -- turns the terminal on or off.

•

"Powe~
OK" indicator
lights to indicate power is
applied to the terminal and all dc voltages are present.

II I

"POWER OK"
/INDICATOR

t:=:::::::==~~

"",--

MODEM

PLUG

CONNECTOR~

"·'---==--====oor
)~r,;,

POWER ON/OFF
SWITCH

~D _i:~o~7 ':.:':. I \\ \ ~~C:;T~~N
'\JIIII '-~~~~r-J
rc~~
_-- ,)
_0

COMPOSITE VIDEO
OUTPUT CONNECTOR

ACPOWERINPUT

,
EIA HOST PORT
CONNECTOR

~/~-

20mA HOST
PORT CONNECTOR

Figure 2-1

SWITCH

FUSE

PRINTER PORT
CONNECTOR

KEYBOARD
CABLE CONNECTOR

MA·086~83A

Monitor Assembly Controls, Indicators, and Connectors

2-1

max

men

max

men

( ••~•• ••••• ~1111111t)

'¥~~
CONTRAST
CONTROL

BRIGHTNESS
CONTROL

TI L T CONTROL
MA-0843-83

Figure 2-2

Display Controls and
Tilt Leg Release Button

•

AC power input -- connects the power cord to the monitor
assembly.

•

Fuse
damage.

•

Voltage selection switch
matches the input voltage
selected to the voltage supplied by the ac source.

protects

the

monitor assembly from electrical

CAUTION
An incorrect setting of the voltage
select switch can damage the monitor
assembly.

2-2

Communication connectors
•

EIA host port connector -- connects the terminal to a
local host computer, or an external modem for remote host
communication.

•

2~
rnA host port connector -- connects the terminal to a
local host computer via a passive only 2~ rnA loop.

•

Composite video output connector -- provides a complete
composite video output signal for an additional slave
monitor;
(composite video output is an RS17~-like output
using dc coupling not in strict agreement with RS17~
specifications) •

•

9-pin printer port connector -- connects a printer to the
terminal.

•

Keyboard cable connector
monitor assembly.

•

Modem plug connector -- connects shorting plug portion of
modem connection cable to monitor assembly.

connects the keyboard to the

CRT display controls

•

Contrast control
screen.

•

Brightness control -- adjusts the degree of brightness on
the screen.

•

Tilt
control
releases a tilt leg that drops to
provide a -5 to +15 degree tilt range for adjusting the
angle of the monitor.

2.3

KEYBOARD

The
LK2~1
components.
•
•
•
•
•
•
•

adjusts the degree of contrast on the

(LK2~1)

keyboard

(Figure

2-3)

Main keypad
Editing keypad
Auxiliary keypad
Top-Row function keys
Visual indicators
Audible indicators
Connector cable

2-3

consists

the

following

MA-0271-82

Figure 2-3

LK20l Keyboard Module

2-4

DD[J[J[[][](][](][][]EJ(]I~ I
DEJEJ[][J[J[]~D[J~[][]D·turn

LJu[][][]DEJ~[][]DDD[]

ISh,ft

1[][][]D[][J~~DD[]lsh,ft

I
Figure 2-4

Main Keypad

2.3.1
The main
keyboard.
keypad.

keypad (Figure 2-4) operates like a standard typewriter
These special function keys are located on the main

•

TAB key
generates a horizontal tab, normally moving
the cursor to the next tab stop.

•

CTRL (Control)
key
when pressed with another key,
generates a control code to tell the system to perform a
predefined function (such as CTRL -- <X, which generates
a CANCEL control character).

•

LOCK key -- function determined by set-up feature so that
when pressed,
it can serve as either a SHIFT LOCK (all
keys to generate their shifted value), or a CAPS LOCK
(alphabetic keys generate uppercase characters), until
LOCK key is pressed again.

•

SHIFT key
when pressed with another key, generates
either the key's shifted value (for alphanumeric and
two-symbol keys), or, in the case of some function keys,
generates a predefined control function.

•

RETURN key -- generates a CR (or a CR and LF, as selected
in General Set-Up), or, in some cases, moves the cursor
to the next line when editing text. In other cases, it is
a signal to the system that a particular operation is
finished.

•

<X (Delete)
key -- generates a DEL character, normally
moving cursor one character to the left and erasing
character at the new cursor position.

•

COMPOSE CHARACTER key -- generates characters that do not
exist as standard keys.
2-5

Figure 2-5

Editing
Keypad
Figure 2-6

2.3.2

Auxiliary
Keypad

Editing Keypad

The editing keypad (Figure 2-5) is normally used to control the
cursor, and edit data already entered. In a typical editing
operation, the four arrow keys move the cursor in the direction
indicated by the arrow. The six editing keys can have functions
corresponding to their legends, or can be defined for special
functions, depending on the application program in effect.
2.3.3

Auxiliary Keypad

The auxiliary keypad (Figure 2-6)
is used primarily to enter
numeric data. However, some of this keypad's keys (PF1, PF2, PF3,
and PF4) can have functions assigned to them by the application
software in use. The ENTER key causes a CR (or a CR and LF, as
selected in General Set-Up), and is also used while in set-up mode
to activate selected features.
2.3.4

Top-ROW Function Keys

Most of the top-row function keys (Figure 2-7), have functions
assigned to them by the application software in use. The following
top-row function keys have predetermined values.
•

HOLD SCREEN key
freezes the display and stops new
characters from being displayed until pressing HOLD
SCREEN again returns the terminal to normal operation.

•

PRINT SCREEN key -- sends the text on the screen to the
printer (CTRL-PRINT SCREEN sets or resets auto print
mode) •

•

SET-UP key -- causes terminal to enter or exit set-up.

2-6

- - --InODDD
DODDonOODODnDDDDnBI

Hold

_ Screen

I
--..J

Print
Screen

Set-Up

Datal
Talk

Break

Fll

FlO

(ESC)

F12
(BS)

F13

(LF)

F14

Hold Screen

----------

-----

Lock

---

Compose Walt
--

Figure 2-7

Top-Row Function Keys

F17

F1B

Fl.

F20

•

DATA/TALK key
controls use of a switched telephone
line when the optional modem is installed.

•

BREAK key -- transmits a BREAK control character to the
host
if
BREAK
generation
is
enabled in set-up
(SHIFT-BREAK initiates a disconnect, while CTRL-BREAK
sends the answerback message to the host).

•

Fli
(ESC)
-- generates an ESC character in either VT100
or VT52 modes
(function is determined by application
programs in either of the VT200 modes) •

•

FI2
(BS)
-- generates a BS character in either VT100 or
modes
VT52
(function is determined by application
programs in either of the VT200 modes) •

•

FI3
(LF)
-- generates a LF character in either VT100 or
VT52
modes
(function is determined by application
programs in either of the VT200 modes) •

2.3.5

Visual Indicators

The keyboard has four visual indicators to show the present status
or operation in progress.
•

HOLD SCREEN indicator -- on when display is frozen (refer
to HOLD SCREEN key description in section 2.3.4)

•

LOCK
indicator
on when keyboard's LOCK key
depressed (see LOCK key description in para. 2.3.1)

•

COMPOSE indicator -- on to indicate a compose sequence is
in progress

•

WAIT indicator
on when keyboard is prevented from
transmitting information
(in effect, locked out of the
system)

2.3.6

Audible Indicators

The keyboard generates two sounds, both of which can be enabled or
disabled in set-up.
•
•

Keyclick
Bell

2-8

2.3.6.1 Audible Keyc1ick
with the following exceptions.

sounds each time a key is pressed,

•

When the SHIFT or CTRL keys are depressed, because these
keys
do
not generate characters, but only modify
characters generated by other keys

•

When the WAIT indicator
keyboard will be lost)

•

When the keyclick is disabled in set-up

•

When an inactive key is pressed

2.3.6.2

(characters

from the

Bell -- sounds in each of the following cases.

•

During the power-up self-test

•

When the terminal receives a BEL character from the host

•

When a composing error is made

•

When the margin is approached (unless bell is disabled in
set-up)

2.3.7

Connector Cable

The keyboard module connects to the system via a BCC9l cable.
Figure 2-8 shows the connector for the BCC91 cable.

SERIAL OUT
PIN 4

CABLE CONNECTOR WIRING
KEYBOARD END
PIN NO.

SIGNAL

SERIAL IN
PIN 1

MONITOR END

SERIAL IN
GROUND
+12 V IN
SERIAL OUT

3
4

SIGNAL

PIN NO.

SERIAL OUT
GND
+12 V
SERIAL IN

4
3
2
1

PIN NUMBERS

~
Figure 2-8

TOP VIEW OF KEYBOARD JACK
(SIGNALS ARE REVERSED AT MONITOR)

BCC9l Cable Connector (Keyboard End)

2-9

MA-074Q..84

2.4

MODEM OPTION (VT22X-AA)

The VT22X-AA modem
2-9) are as follows.

controls, indicators, and connectors (Figure

Front panel controls and indicators
•

Test LED
when lit, provides visual indication of
either on-going analog or remote loop test condition.

•

Analog loop test button -- puts modem into test of local
loop when depressed.

•

Remote loop test button -- puts modem into test of remote
loop when depressed.

TEST LED

ANALOG LOOP

REMOTE LOOP

TEST BUDON

\3~

~~c~~~~@~@~

VT22X·AA FRONT PANEL

FILLER
PANEL

MOOEM
MODULE
EIA CABLE

TELEPHONE
\ JACK

TELEPHONE
CABLE JACK

H r.1QJ1Ql- C

SHORTING PLUG
VT22·AA REAR VIEW

CONNECTOR CABLE
MA·0614-84

Figure 2-9

Modem Module Controls, Indicators,
and Connectors

2-113

Rear panel connectors
•

Connector cable
consists of shorting plug (which
connects to receptacle covered b¥ filler panel) and EIA
cable (which routes host communIcation between the EIA
connectors on the monitor and the modem) •

•

Filler panel
is a removable panel covering monitor
assembly receptacle for shorting plug of modem connector
cable.

•

EIA connector
is a 25-pin connector on both monitor
assembly
and modem with host communications routed
between the two EIA connectors by the connector cable.

•

Telephone
modem.

•

Telephone cable jack -- connects telecommunications line
to the modem.

jack

connects

2-11

telephone

device

the

CHAPTER 3
SYSTEM OVERVIEW

3.1

GENERAL

This chapter
each of the
terminal.
3.2

provides
possible

an overview of system interactions during
operating states of the VT220 Series

OPERATING STATES

The terminal functions in anyone of three operating states.

•
•
•

Set-up
Local
On-Line

3.2.1

set-Up

Set-up is selectable from the keyboard (SET-UP key) for performing
the following functions.
•

Examining or changing terminal operating characteristics
(such as transmit and receive speeds)

•

Transferring
on-line

from

on-line

local,

or from local to

While in set-up, the terminal is functionally disconnected from
the host. Only the keyboard is enabled as an input device, and
only the monitor is enabled for output. Any data received from the
host is buffered until the terminal is placed in an on-line
operating state.

3-1

3.2.2

Local

Local is selectable while in set-up. This operating state disables
terminal-to-host communications. Any data received from the host
while in local is buffered until the terminal is placed on-line.
While in local, the keyboard serves as an input device, with
displayable data input from this device sent to the screen. In
addition,
information can be output from the terminal (either
screen or keyboard data), to the printer (via printer port).
3.2.3

On-Line

On-line is selectable while in set-up. This operating state lets
the terminal communicate with a host. This communications link-up
can take the following two forms.

•

Null modem
communication is through a direct line link
with the host, either through the EIA host port, or the
20 rnA port

•

External modem -- communication with a remote host, via
EIA host port connection with the modem option

When the terminal is on-line, data entered at the keyboard is
transmitted to the host. A local-echo feature (selectable in
set-up)
routes keyboard data to the monitor, as well as to the
host.
Both the monitor and the printer can receive information from the
host, but not both at the same time. However, data received for
the monitor can be subsequently transferred to the printer.
The printer port can be placed in controller mode while on-line
(via set-up feature). When the printer port is selected for
controller mode, the terminal is essentially a buffer for host to
printer communications. In such a case, no output is made to the
monitor, and no keyboard input is transferred to the host.
3.3

SYSTEM ARCHITECTURE

Figure 3-1 provides a functional block diagram of the terminal
that identifies the terminal's major components or logics.
•
•
•
•
•
•
•

CPU logic
Video logic
System communication logic
Modem option
Power supply
Keyboard
Monitor (monitor circuits and CRT)

3-2

PSAND
MONITOR
BOARD
POWER
SUPPLY

CPU
LOGIC

MONITOR
CIRCUITS

I
I

VIDEO
LOGIC

____ ...1 ___ _
SYSTEM
COMMUNICATION
LOGIC

EIA
PRINTER
HOST PORT
PORT

LOGIC
BOARD

20mA
PORT

OPTION

• CONNECTOR PHYSICALLY MOUNTED ON
PS AND MONITOR BOARD

MA-0613-840

Figure 3-1

3.3.1

VT220 Series Terminal
Functional Block Diagram

CPU Logic

The CPU logic controls the overall operation of the terminal. It
interprets host and keyboard input and directs terminal functions.
The CPU logic contains the following major components/circuits.
•

8051 microprocessor with internal RAM (128 bytes) and ROM
(4K),
directly
responsible for terminal operation,
including direct interface with the keyboard module

•

Associated decoding logic

•

256 byte nonvolatile
information

•

24K byte of ROM containing firmware for all terminal
control functions, such as keyboard handling, screen data
handling, set-up, self-test, VT100 and VT52 modes, and
printer control

RAM

3-3

for

storing terminal set-up

•

8K of volatile screen RAM used for storage of characters
to be displayed, as well as for data buffering, and
scratch pad operations

•

8K of volatile atribute RAM used for storage of attribute
data associated with characters stored in the screen RAM
NOTE
The volatile screen and attribute RAMs
are also accessed by the video logic to
obtain character and attribute values
stored in these RAMs.

3.3.2

video Logic

The video logic develops the video output signals required to
drive the terminal monitor. The video logic consists of the
following major components/circuits.

•

A 9007
video processor that performs DMA transfers
(character and attribute transfers from CPU logic RAMs to
the video converting circuit), and generation of basic
video timing signals

•

A video converting circuit that transforms display data
into video output to the monitor circuits, and composite
video output to a slave monitor

3.3.3

System Communication Logic

The system communication logic interfaces the terminal with
external devices. The system communication logic consists of the
following major components/circuits.
•

Connectors for physical connection with the printer, host
(EIA host port or 20 mA port connectors), and modem
option (via EIA host port)

•

DUART
CPU

•

Interface components responsible for input and output of
data from the various connectors

for

control of communication as programmed by the

3-4

3.3.4

Modem Option (VT22X-AA)

When installed, the modem interfaces the terminal with a switched
or dedicated telephone line for communication with a remote host.
The
VT22X-AA
modem
consists
of
the
following
major
circuits/components.
•

Two four-pin telephone
with the telephone line

•
•

EIA connector for interfacing with the monitor assembly

3.3.5

jack connectors for interfacing

Handshake circuits to control the communication between
the terminal and the remote host
Power Supply

The power supply generates the operational voltages required by
the monitor assembly, keyboard, and the modem module option. The
power supply contains the following major components/circuits.
•
•
•
•
•
•
3.3.6

AC input circuits
+5 V development circuits
+12 V development circuits
-12 V development circuits
Pulse modulation and feedback control circuits
Overcurrent protect circuit
Keyboard

The keyboard enables operator input to the system. The keyboard
consists of the following major components/circuits.
•

8051 microprocessor for control of keyboard operations

•

Serial interface
assembly

•

Key matrix scanning circuits for determining when a key
is being pressed

•

Audio circuits for generating bell tones and key clicks

•

LED
drivers
indicators

for

communication

enabling

3-5

the

with

the

keyboard's

monitor

visual

3.3.7

Monitor Components

The monitor components convert separate video and sync input
signals from the video logic into visual output to the operator.
The monitor contains the following major components/circuits.
•

CRT device for presenting the visual output

•

Monitor
CRT

•

BNC connector
monitor

•

Brightness and contrast controls

3.4

circuits for developing drive potentials for the
for

composite

video

output

to a slave

SYSTEM INTERACTION

Figures 3-2 through 3-7 provide an overview of the information
flow within the terminal for various system configurations during
the different operating states (set-up, local, and on-line).

1. DATA IS TRANSFERED FROM THE KEYBOARD TO THE CPU LOGIC
DEFINING PARAMETERS TO BE AFFECTED.
2. IF SCREEN DISPLAY IS TO BE AFFECTED, CPU LOGIC DIRECTS VIDEO
LOGIC TO ALTER DISPLAY.
MA_1443-83A

Figure 3-2

System Interaction in Set-Up

3-6

1 DATA IS TRANSFERRED FROM THE KEYBOARD TO THE CPU LOGIC
2. IF SCREEN DISPLAY IS TO BE AFFECTED. CPU LOGIC DIRECTS VIDEO
LOGIC TO ALTER DISPLAY.
3. IF DATA IS TO OUTPUT TO A PRINTER, CPU LOGIC
DIRECTS TRANSFER OF DATA AND CONTROLS TO PRINTER
VIA PRINTER PORT PORTION OF SYSTEM INTERFACE LOGIC.

MA·1445-83A

Figure 3-3

System Interaction in Local

8
1 DATA IS TRANSFERRED FROM THE KEYBOARD TO THE CPU LOGIC
2. DATA IS TRANSFERRED FROM THE CPU LOGIC TO THE HOST. VIA
EITHER EIA HOST PORT, OR20 rnA PORT PORTIONSOFTHE SYSTEM
COMMUNICATION LOGIC
3. IF LOCAL-ECHO IS ENABLED, AND SCREEN DISPLAY IS TO BE
AFFECTED, CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY.

MA·1447-83A

Figure 3-4

System Interaction On-Line: Data to Host (Null-Modem)

3-7

1. DATA IS TRANSFERRED TO THE CPU LOGIC FROM THE HOST. VIA
EITHER EIA HOST PORT, OR20 mA PORT PORTIONS OFTHE SYSTEM
COMMUNICATION LOGIC.
2. IF SCREEN DISPLAY IS TO BE AFFECTED, CPU LOGIC DIRECTS VIDEO
LOGIC TO ALTER DISPLAY.
3. IF DATA IS TO BE OUTPUT TO THE PRINTER DEVICE, CPU LOGIC
DIRECTS TRANSFER OF DATA AND CONTROLS TO PRINTER
DEVICE VIA PRINTER PORT PORTION OF SYSTEM COMMU·
NICATION LOGIC.

MA·145()'83A

Figure 3-5

System Interaction On-Line: Data from Host

C-:\

DATA IS TRANSFERRED FROM THE KEYBOARD TO THE CPU LOGIC.

DATA IS TRANSFERRED FROM THE CPU LOGIC TO THE HOST EIA
PORT.

DATA IS ROUTED FROM EIA HOST PORT TO MODEM OPTION.

IF LOCAL·ECHO IS ENABLED, AND SCREEN DISPLAY IS TO BE
AFFECTED, CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY.

MA-1452-83A

Figure 3-6

System Interaction On-Line: Data to Host (Modem)

3-8

(;:::\

DATA IS ROUTED TO EIA HOST PORT BY MODEM OPTION.

DATA IS TRANSFERRED TO THE CPU LOGIC FROM THE EIA HOST
PORT.

IF SCREEN DISPLAY IS TO BE AFFECTED, CPU LOGIC DIRECTS
VIDEO LOGIC TO ALTER DISPLAY.

IF DATA IS TO BE OUTPUT TO THE PRINTER DEVICE, CPU LOGIC
DIRECTS TRANSFER OF DATA AND CONTROLS TO PRINTER
DEVICE VIA PRINTER PORT PORTION OF SYSTEM COMMUNICATION LOGIC.
MA-1455-83A

Figure 3-7

System Interaction On-Line: Data from Host (Modem)

3-9

CHAPTER 4
CPU LOGIC

4.1

GENERAL

The CPU logic (shaded area in Figure 4-1) directs VT22~ activity
in response to either operator input (via keyboard), or host input
(via system communication logic). In general, the CPU performs the
following functions.

•

Defines
operational
components

•

Directs system communication
keyboard module operation

parameters

for

logic,

video

PSAND
MONITOR
BOARD
POWER
SUPPLY

MONITOR
CIRCUITS

VIDEO
LOGIC

SYSTEM
COMMUNICATION
LOGIC

EIA
PRINTER
HOST PORT
PORT

LOGIC
BOARD

20mA
PORT

OPTION
• CONNECTOR PHYSICALLY MOUNTED ON
PS AND MONITOR BOARD

Figure 4-1

MA-0613-84E

VT22~ Series Terminal
Functional Block Diagram

4-1

other

logic

logic, and

4.2

•

Manages screen and attribute RAMs

•

Initializes
programs

system

power up, and executes self-test

MAJOR CIRCUITS AND COMPONENTS

Figure 4-2 provides a block diagram identifying the major circuits
and components that make up the central processing unit (CPU)
logic.

•
•
•
•
•

•
•
••
•

Central processing unit (CPU)
Address latch
Program ROM
Data buffer
Screen RAM

Attribute RAM
Select decoder
Keyboard I/F
Nonvolatile RAM (NVR)
Configuration register

ROM

ADDRESS
LATCH

~-----'"

CPU

KEYBOARD
I/F

DATA
TO/FROM
KEYBOARD

SELECT
DECODER

CONFIGURATION
REGISTER

CONTROLS CONTROLS

CONTROLS ADDRESS
T

DATA

TO/FROM
VIDEO AND SYSTEM COMM LOGICS
MA·0615-84

Figure 4-2

CPU Logic Block Diagram
4-2

4.2.1

Central processing unit (CPU)

The CPU (Figure 4-3) consists of the following components.
•

8051
microprocessor
services interrupt and DMA
requests, interprets host and keyboard data, generates
address and read/write controls for system components,
and initializes system on power up.

•

RD gate -- generates RD L from either CPU RD L, when CPU
is attempting to read from an I/O device or RAM, or from
DMA L, when character and attribute data is to be
transferred out of the RAMs over to the video logic.

r-------~~~P~S~EN~L--.TOROM
ADO H
ADl H
AD2 H

ADDRESS/
DATA
LINES
TO
SYSTEM

AD3 H
AD4 H
AD5 H
AD6 H
AD7 H
AB H

A9 H
Al0 H
ADDRESS
LINES
TO
SYSTEM

All H
A12 H
A13 H
A14 H
A15 H
A15 L

ALE t----:A~L;::..E..:...:H_ _.. TO ADDRESS LATCH

Rl
+5V-""",,"--QEA

Pl.l j-:N..:..:V.:.;.R..:.;R.::;EC:::.;A:::;:LL:....:L,-+} TO
Pl.2

NVR STORE L

RESET
XTAL1

NVR

.......
~RDL

TO SYSTEM
PROD/DATA/TALK
COMM LOG IC ----'-----'---'~--f Pl.4

~ WRL

}

P3.6
DMA L
Pl.01--'-..,.-t--_ TO VIDEO
CPU RD L
P3.70--t-'-"'"'-'-"';";':"-'+
XTAL2

RD/WR
TO
SYSTEM

MAH:o VIDEO LOGIC
~
ND
ADDRESS LATCH

PROD RESET H*

*PRODUCTIO~ TEST SIGNAL
MA-0616-84

Figure 4-3

CPU Block Diagram

4-3

•
•

Power reset

resets the 8051 on power up.

CPU clock
basic timing.

provides 11.0592 MHz input to ~051 CPU for

4.2.1.1
8051 CPU Internal Circuits
Figure 4-4 provides a
block diagram showing the major 8051 CPU internal circuits.
•

Port 0 -- is eight bidirectional lines used for output of
lower byte of address and for input and output of data.

•

Port 1
is eight quasi-bidirectional lines used for
input of status information and output of controls.

•

Port 2 -- is eight lines used for output of high byte of
address.

~~
~

.....

'\
vi

ROM

V
ALU
AND
REGISTERS

PROGRAM
CONTROL

r---

PORT

(ADO H-AD79

.....

.,/
...

[

)
r

PORT
2

A8H-A15H

.,/

(0)

"-/

/
'...

(1)

RAM

(2)
PORT
1

(3)
(4)
(5)

(6)
(7)

SERIAL
PORT
CONTROL
CONTROLS

fI
CONTROL

(0)

It "
.,/

.....

(1)

(2)

~
~

PORT
3

(4)

(6)

A
TIMING
"\I

(3)

(5)

(7)

DMA L
NVR RECALL L
NVR STORE L
LBF DISABLE H
PROD/DATA/TALK
CHRG SEL H
RESET CRT L
CAR DET H

Rx D
Tx D
DMA REQ L
CMM INT L
VERT SYNC L
HOR SYNC L
WRL
CPU RD L

OSC

XTAL 1

XTAL 2

TIMING
MA-0617-B4

Figure 4-4

8051 CPU Internal Block Diagram

4-4

•

Port 3 -- is eight lines used for input of status, output
of controls, and transfer of serial data between the 8051
and the keyboard I/F.

•

Oscillator
(OSC)
Fnd timing
signals based on 11.0592 MHz
clock.

•

Program control
controls sequence of program memory
execution (internal ROM and external ROM).

•

Control -- interprets instructions and generates controls
to 8051 circuits based on that interpretation.

•

Serial
port
functionality
keyboard.

•

ROM
provides
programming.

•

RAM -- provides l28K bytes of memory for scratch pad and
register/stack functions.

•

ALU and registers -- provide processing logic, including
special function registers.

control
for serial
4K

generates 8051 timing
input from external CPU

provides full-duplex UART
data communications with the
bytes

internally

stored

Later in this chapter, Table 4-2 describes the signals shown in
Figures 4-3 and 4-4.
4.2.1.2
8051 CPU Transactions -- The 8051 performs the following
transactions.
•

Instruction fetch -- reads internal or external ROM.

•

Read/write transaction -- reads or writes data for system
I/O devices, screen RAM, or attribute RAM.

•

DMA transaction
grants control of the data buses to
enable video logic access of CPU logic RAMs, for access
of character and attribute values.

Figures 4-5 through 4-7 provide timing diagrams for instruction
.fetch, read, and write transactions. No diagram is provided
concerning DMA transactions, as DMA transactions are described in
greater detail in the video logic description (refer to the CRT
controller description in Chapter 6).

4-5

OSC

ALE H

PSEN L

A8H-A15H

ADDRESS

~liUIK(

_illlll~

FLOAT

ADOH-AD7H(

P.C. LOW BYTE
ADDRESS OUT

INSTRUCTION
IN

ADDRESS

_lliiDC(

_lit

FLOAT
INSTRUCTION
IN

!lil~~

FLOAT

P.C. LOW BYTE
ADDRESS OUT

FLOAT

INSTRUCTION
IN
MA-0618-84

Figure 4-5

8~51

CPU Instruction Fetch Timing Diagram

T10 T11

T12

OSC

__________________

~r--

WRL

..-JX'-_______A_D_DR_E_S_S_ _ _ _ _ _ ___'X

A8H-A15H _ _

ADOH-AD7 H

(

X .

(ADDRESS
OUT

INSTRUCTION
IN

MA-0619-84

8~51

Figure 4-6

DATA OUTPUT

~----------------'~

CPU Read Transaction Timing Diagram

OSC
~

ALEH _ _.....

T10

T11

T12

______________________

~r---

CPU RD L
A8 H-A15 H
ADOH-AD7 H

ADDRESS

)(

----~/'~--~~~------------------------

~LO@(

'-... INSTRUCTION
IN

r_FLOATWdX

DATA INPUT

fiFLOATWJ(

ADDRESS
OUT
MA-0620-84

Figure 4-7

8~51

CPU write Transaction Timing Diagram

4-6

Figure
4-8
provides an address map for instruction fetch
transactions
(ROM access). Figure 4-9 provides an external data
memory map for system non-ROM read/write transactions. As shown in
Figure 4-9, several address ranges are mapped for each specific
device or transaction. This is due to a "don't care" condition for
some bits when addressing these devices. The addresses actually
used are identified in Table 4-1 in conjunction with the select
decode description (section 4.2.8).

FFFF H

64K

FFFF
(UNUSED)
F800
F7FF
DUART
COOOH
BFFFH

48K

FOOO
EFFF
E800
E7FF

ROM 1

EOOO
DFFF
D800
D7FF
8000H
7FFFH

32K
ROM 0

SCREEN
RAMO
CHARACTER
GENERATOR

COOO
BFFF

ATTRIBUTE
RAM 1
ATTRIBUTE
RAMO

DUART
7000
6FFF
6800
67FF
6000
5FFF
5800
57FF
5000
4FFF
4800
47FF
4000
3FFF

A800
A7FF
1000H
OFFFH
OOOOH
MA·0621·84

Figure 4-8

8051 CPU
Address Map: ROM

AOOO
9FFF
9800
97FF

8800
87FF
8000

SCREEN
RAM 1
SCREEN
RAMO
CHARACTER
GENERATOR

ATTRIBUTE
RAM 1
ATTRIBUTE
RAMO

cb
Figure 4-9

4-7

RESET TIMING
GENERATOR
CRT
CONTROLLER
CHARACTER
ADDRESS REGISTER
CONFIGURATION
REGISTER

DUART
3000
2FFF
2800
27FF
2000
lFFF
1800
17FF

NVR
9000
BFFF

SCREEN
RAMO

3800
37FF
DUART

8000
AFFF

SCREEN
RAM 1

(UNUSED)

(UNUSED)
8800
87FF

Q
(UNUSED)

7800
77FF

NVR
DOOO
CFFF
C800
C7FF

6000H
5FFFH

SCREEN
RAM 1

7FFF

1000
OFFF
0800
07FF
0000

SCREEN
RAM 1
SCREEN
RAMO
RESET TIMING
GENERATOR
CRT
CONTROLLER
CHARACTER
ADDRESS REGISTER
CONFIGURATION
REGISTER

MA-0622-84

8051 CPU Address Map:
Non-ROM

4.2.2

Address Latch

The address latch (Figure 4-10), is used by the 8051 for storing
the lower byte of address to be used for access of any 8051
addressable component, including external ROM. Address is input to
the latch by ALE H and enabled as output as long as DMA H is
false. The address latch is inhibited during DMA transactions to
prevent any value stored in the latch from affecting the address
being generated by the video logic for access of the RAM.
Definitions of the signals identified in Figure 4-10 are provided
in Table 4-2.
4.2.3

Read Only Memory (ROM)

ROM provides storage for the firmware required for terminal
operation. The ROM (Figure 4-11) consists of two ROM devices, ROM
0, containing 8K bytes of firmware, and ROM 1, containing 16K
bytes.
ROM access occurs when PSEN L is true, with ROM 0 enabled for A15
L true, and ROM 1 enabled for A15 H true.

ADDRESS
LATCH

AO H - A7 H

FROM
CPU

TO ALL
VT220
ADDRESSABLE
COMPONENTS

ALE H
DMA H
MA-0623-84

Figure 4-10

Address Latch Block Diagram

FROM
AO H - A7 H
ADDRESS
LATCH
~----..,

\--_ _ _ _1'\ TO
CPU

A8H-A13H
FROM [
8051

A15 H

CPU

PSEN L
A15 L

MA-0624-84

Figure 4-11

ROM Block Diagram

4-8

Later in this
Figure 4-11.
4.2.4

chapter, Table 4-2 describes the signals shown in

Data Buffer

The data buffer provides isolation between the AD0 H-AD7 H lines
used by the 8051 CPU for program memory, addressing, and access of
either of the two attribute RAMs in the video logic (refer to
Chapter 6), and the BAD0 H-BAD7 H lines used for all other read,
write, and DMA transactions.
The isolation between the AD0 H-AD7 H bus and the BAD0 H-BAD7 H
bus provided by the data buffer enables the video logic to use
both buses during DMA transactions. The BAD0 H-BAD7 H lines are
used for accessing character address data stored in the screen
RAM, while the AD0 H-AD7 H lines are used for accessing attribute
data stored in the attribute RAM.
As shown in Figure 4-12, the data buffer is a bidirectional device
enabled whenever the attribute RAM is not being accessed (SEL ATR0
Land SEL ATRl L both false), with the direction of data transfer
determined by RD L (out as BAD signals when RD L is false, and in
as AD signals when true). The data buffer is disabled either
during 8051 CPU access of the attribute RAM, or during DMA
transactions, when the video logic is accessing the stored
attribute data.
Later in this
Figure 4-12.

chapter, Table 4-2 describes the signals shown in

FROM
SELECT
DECODER

TO
VIDEO
LOGIC

SEL RAMl L

FROM
r----~I"
ADDRESS

TO/FROM
DATA
BUFFER

FROM RD
GATE

FROM
SELECT
DECODER

Figure 4-12

* AO H - A 10 H ARE GENERATED
BY CRT CONTROLLER IN VIDEO
LOGIC DURING DMA TRANSFERS

Data Buffer Block Diagram

4-9

4.2.5

Screen RAM

The 8051 uses the screen RAM to store character address data for
output to the video logic and for scratch pad operations.
Character address data stored in the screen RAM is transferred to
the video logic during DMA transactions (along with attribute
values associated with the defined character address, as stored in
the attribute RAM).
It also defines an address value for a
character generator within the video logic, with that address
defining the character to be processed for display (refer to the
video logic description in Chapter 6).
The screen RAM (Figure 4-13) consists of two static RAM devices,
each providing 2K bytes of RAM space. Each is selected by separate
select signals (SEL RAM0 L or SEL RAM1 L), and enabled for 8051
write by WR L, or enabled for read output by RD L (with RD L
generated either from CPU RD L, for CPU access, or from DMA L, for
DMA transfer to the video logic).
Later in this
Figure 4-13.

chapter, Table 4-2 describes the signals shown in

TO/FROM
RAM, NVR,
I/O DEVICES

TO/FROM

CPU
FROM
{SEL ATRO L
SELECT
DECODER
SEL ATRl L
FROM
RD
GATE

.:.:;RD::.....::....L_ _ _ _ _- - '

Figure 4-13

MA·0626-84

Screen RAM Block Diagram

4-10

4.2.6

Attribute RAM

The 8051 CPU loads attribute values for specific characters into
attribute RAM at addresses directly corresponding to character
address values loaded into the screen RAM. Whenever character
address values are loaded into the screen RAM, the 8051 CPU will
write attribute values associated with those character address
values into the attribute RAM.
During DMA transactions, the video logic generates a single
address which is applied to both the attribute and screen RAMs.
The attribute data is output from attribute RAM and sent to the
video logic in conjunction with the character address being output
from the screen RAM on the same DMA transaction (attribute value
on the AD data lines, and character data on the BAD data lines).
The attribute RAM (Figure 4-14)
consists of two static RAM
devices, each providing 2K bytes of RAM space. Each is selected by
separate select signals (SEL ATR0 L or SEL ATRl L), and enabled
for 8051 write by WR L, or enabled for read output by RD L (with
RD L generated either from CPU RD L, for CPU access, or from DMA
L, for DMA transfer to the video logic).
Later in this
Figure 4-14.

chapter, Table 4-2 describes the signals shown in

TO
VIDEO
LOGIC

FROM
SELECT
DECODER
FROM
ADDRESS

TO/FROM

8051
CPU

FROM
SELECT
DECODER

• AO H - Ala H ARE GENERATED
BY CRT CONTROLLER IN VIDEO
LOGIC DURING DMA TRANSFERS
MA-0625-84A

Figure 4-14

Attribute RAM Block Diagram

4-11

4.2.7

Select Decoder

The
select
decoder generates access enables for 8051 CPU
read/write transactions, and for video logic DMA transactions. The
select decoder (Figure 4-15) consists of the following components.
•

RAM/DUART decoder
is enabled by A13 H true, during
805lCPU read/write transactions to decode All H-A12 H
address inputs into enable of either the screen RAM (SEL
RAM0
L
or
SEL RAMI L)
or the DUART in system
communication logic
(SEL DUART); it is also enabled by
DMA H true during DMA transactions for selecting screen
RAM to be accessed
(address input for DUART is not
presented during DMA transactions).

•

RD/WR decoder -- is enabled by RD L or WR L for 8051 CPU
read/write transactions, when Al3 H is false, to decode
A15 L, All H-A12 H into access output to NVR (SEL NVR L),
configuration register
(SEL CONF REG L), attribute RAM
(SEL ATR0 L or SEL ATRI L), or to various video logic
components
(EN CHR GEN L, CHR ADDR WR L, SEL CRT L, and
RESET TIM L)i
it is also enabled by RD L, during DMA
transactions
(A13 H false during DMA, with address value
for either of two attribute RAMs presented to decoder) •

RAM/DUART SEL RAMO L
DECODER
SEL RAMI L
B
SEL DUART L
A

A12 H*
All H*

DMA H . - A13 H* )
......

-L../"

FROM
CPU
A15 L

G2B

SEL ATRO L

RD/WR
DECODER

SEL ATRI L

A12 H*

All H*

SEL NVR L
EN CHRGEN L
SEL CONFREG L

CHR ADDR WR L
SEL CRT L

FROM
RD
GATE

WRL
RD L

RESET TIM L
G2A

:::J
"'"
----../

* All H -A 13 H ARE GENERATED
BY CRT CONTROLLER IN VIDEO LOGIC
DURING DMA TRANSACTIONS.
MA-0627-B4

Figure 4-15

Select Decoder Block Diagram

4-12

During DMA transactions, the RD/WR decoder and the RAM/DUART
decoder will both be enabled for output of corresponding screen
RAM and attribute RAM s~lect signals, as these two RAM circuits
are read simultaneously by the video logic.
Table 4-1 identifies the address values for all of the access
enable signals. Later in this chapter, Table 4-2 describes the
signals shown in Figure 4-15.

Table 4-1

8051 CPU Addresses (Non-ROM)

Enable Signal

Hex Address (es)

Device (Logic)

SEL RAM0 L
SEL RAMI L
SEL DUART L
SEL ATR0 L
SEL ATRI L
SEL NVR L
EN CHR GEN L
SEL CONF REG L
CHR AD DR WR L

A000-A7FF
A800-AFFF
B7F0-87FF
8000-87FF
8800-8FFF
9700-97FF
9FF0-9FFF
07FF
0FFF

SEL CRT L
RESET TIM L

1700-17FF
1FFF

RAM 0 (CPU)
RAM 1 (CPU)
DUART (system communication)
Attribute RAM 0 (video)
Attribute RAM 1 (video)
NVR
Character generator (video)
Configuration register (CPU)
Character address register
(video)
CRT controller (video)
Timing control (video)

4.2.8

Keyboard Interface (I/F)

The keyboard I/F buffers communication between the keyboard module
and the 8051 CPU. Serial data is output to the keyboard as KBT
(originating at A051 as TxD), and input to the 8051 as RxD
(originating at keyboard as KBR).
Keyboard
terminal
I/F.

I/F components are physically located on both of the
PCBs. Figure 4-16 provides a breakdown of the keyboard

•

EIA driver and receiver -- interface TTL level logic with
EIA level communication lines.

•

J1
(logic board)/J2 (PS and monitor board) -- are 26-pin
connectors used for routing signals between the two
system PCBs.

•

Output components -- are ferrite beads tied to keyboard
connector pins that are used for radiation suppression.

•

J6
is a 4-pin telephone plug-type connector that
provides direct connection between the keyboard cable and
the monitor assembly.
4-13

KEYBOARD
CONNECTOR

IJ61

PART OF
LOGIC BOARD

Figure 4-16

PART OF
PS AND MONITOR
BOARD

MA-0628-84

Keyboard IIF Block Diagram

Figure 4-16 provides a pin-out for the keyboard connector (J6) and
identifies the J1/J2 pins used for keyboard IIF functions. A
complete pin-out of J1/J2 is provided in the system communication
logic description presented in Chapter 5 (refer to Figure 5-9).
Later in this
Figure 4-16.
4.2.9

chapter, Table 4-2 describes the signals shown in

Nonvolatile RAM (NVR)

The NVR combines a 256 X 4 bit static RAM with a 256 X 4 bit
electrically alterable ROM (EAROM) to provide memory for storing
terminal operational parameters, and allowing those parameters to
be manipulated by the operator.
During a power-up sequence, data is transferred from the EAROM to
the NVR RAM portion (NVR RECALL L), and then to the CPU logic RAM
for use in defining terminal parameters. While in the CPU logic
RAM, the data stored can be altered. Operator keyboard input
defines new parameters, with the 8@5l directing a write to alter
the data stored in the CPU logic RAM. During a save parameters
operation, the data stored in the CPU logic RAM is written to the
NVR RAM by the 8@51 (SEL NVR Land WR L), and then stored as new
parameter values in the NVR EAROM by NVR STORE L from the 8@51.

4-14

FROM
ADDRESS
LATCH

TO/FROM
DATA
BUFFER

FROM
CPU
FROM
SELECT
DECODER
FROM
CPU

MA·0629-.84

Figure 4-17

The
NVR
circuit
components/circuits.

NVR Block Diagram

(Figure

4-17)

consists

the

following

•

NVR device
contains the RAM and EAROM memories for
storing and transferring of parameter values.

•

Power up protect
prevents inadvertant write to NVR
device by the 8051 during a power up sequence by forcing
NVR RECALL L low until full dc power is applied and all
circuits operational
(NVR RECALL L places NVR in recall
mode and prevents a low at NVR STORE L from being acted
on) •

Later in this
Figure 4-17.
4.2.10

chapter, Table 4-2 describes the signals shown in

Configuration Register

The configuration register is programmed by the 8951 with control
values to affect system communication and video logic operations.
The configuration register (Figure 4-18) consists of two devices,
both loaded by SEL CONF REG L: A F/F device for controlling which
host communications port is to be enabled (reset for ENA EIA H,
set for ENA 29 rnA H), and a register for generating miscellaneous
video logic controls (NOR FIELD H, LBA CLRS H, EN CHR GEN RW H,
ALT SEL H, and LBA CLKS H), as well as a reset to the DUART in the
system communications logic (RESET CMM H).
Descriptions
Table 4-2.

the

signals identified in Figure 4-18 follow in

4-15

r---

FROM
SELECT
DECODER

SEl CONF REG l

ENA 20mA H
COMM
F/F

ENA EIA H

RESET CMM H

TO
} SYSTEM
COMM
lOGIC

NOR FIELD H

BAD6 H

LBA CLRS H
FROM {
DATA
BUFFER

....
\

BADO H - BAD5 H

CONTROL
REGISTER

)

t--

EN CHR GEN RW H

AlT SEl H

VIDEO
lOGIC

lBA ClKS H

MA·063O-84

Figure 4-18

4.3

Configuration Register Block Diagram

SIGNAL DESCRIPTIONS

Table 4-2 provides descriptions of all the signals identified in
this chapter. These descriptions are provided for reference, and
are listed alphabetically by mnemonic, with numeric mnemonics
listed last.
4.4

SCHEMATIC REFERENCE INFORMATION

Table 4-3 identifies the logic board component coordinate, and the
schematic page and coordinates for each of the CPU logic circuits
and components identified in this chapter.
NOTE
The reference information is based on
Rev. A of the logic board schematics (CS
5415653-9-1), and Rev. A of the PS and
monitor
board
schematics
(CS
5415651-9-1).

4-16

Table 4-2

CPU Logic Signal Descriptions

Mnemonic

Signal

Description

A8 H-A15 H

Address bits
8-15 high

High order byte of
address

A15 L

Address bit 15 low

Inverted most significant
bit of address used as
enable for ROM 1, and for
decode input to select
decoder

Address/data bits
~-7 high

Bidirectional CPU lines
used for output of
address, output of data
being written, and for
input of data being read.

Address latch
enable high

Enables loading of
H-AD7 H into address
latch for low order
address value

Alternate select
high

Enables CPU selection
of alternate character
generator for read/write
when CPU access of video
logic is enabled (refer
to EN CHR GEN RW H)

Buffered data bits
~-7 high

Bidirectional lines for
transfer of data between
the data buffer and RAM,
NVR, video logic, and
system communication
logic components

CAR DET H

Carrier detect high

Status input to CPU from
modem (via EIA host I/F
in system communication
logic) indicating a good
communication line is
detected by the modem

CHR ADDR WR L

Character address
write low

Enables CPU write of data
to attribute latch in
video logic when CPU
access of video logic is
enabled (refer to
EN CHR GEN RW H)

AD~

H-AD7 H

ALE H

ALT SEL H

BAD~

H-BAD7 H

AD~

4-17

Table 4-2

CPU Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

CHRG SEL H

Character generator
select high

Defines most significant
bit of address to
character generator in
video logic

CMM INT L

Communication
interrupt low

Interrupt to CPU from
DUART with value
programmable at the
DUART

CPU RD L

CPU read low

CPU control for read
access of non-ROM system
components

DMA H-DMA L

Direct memory
access high low

Acknowledgment from
CPU relinquishing
control of AD0H-AD7H and
BAD0H-BAD7H bus lines to
the CRT controller in the
video logic for access of
screen characters and
attribute data

DMA REQ L

Direct memory
Access Request Low

Interrupt input to CPU
from CRT controller in
video logic requesting
CPU give up buses so CRT
controller can access
screen character and
attribute data

EN CHR GEN L

Enable character
generator low

Enables CPU write access
of alternate character
generator in video logic
when CPU access to video
logic is enabled (ref.
EN CHR GEN RW H), and
alternate character
generator is selected
(refer to ALT SEL H)

EN CHR GEN
RW H

Enable character
generator read and
write low

Enables CPU read/write
of video logic
components

ENA EIA H

Enable EIA
communication high

Defines EIA host port
as enabled for
communication

4-18

Table 4-2

CPU Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

HDR SYNC L

Horizontal sync low

Input to CPU from CRT
controller in video
logic defining horizontal
sync period

KBR

Keyboard receive
data

Serial data input from
the keyboard to the
keyboard IfF for input to
CPU (as RxD)

KBT

Keyboard transmit
data

Serial data output from
the keyboard IfF to the
keyboard (originating as
TxD at CPU)

LBA CLKS H

Line buffer address
clocks high

Clock inputs to line
buffer address counter in
video logic when CPU
access to video logic is
enabled (refer to
EN CHR GEN RW H)

LBA CLRS H

Line buffer address
clears high

Clear input to line
buffer address counter in
video logic when CPU
access to video logic is
enabled (refer to EN CHR
GEN RW H)

LBF DISABLE H

Line buffer disable
high

Disables chip select input
to line buffer in video
logic

NDR FIELD H

Normal field high

Output to attribute
latch in video logic
defining background of
display as normal

NVR RECALL L

NVR recall low

CPU output defining
transfer of stored
NVR EAROM data into
NVR RAM for definition
of terminal operational
parameters

4-19

Table 4-2

CPU Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

NVR STORE L

NVR store low

CPU output defining
transfer of NVR RAM data
into NVR EAROM to provide
new definition of stored
terminal operational
parameters

PROD RESET

Production reset

Provides biasing for
NVR POWER UP Protect
circuit

PSEN L

Program source
enable low

CPU output enabling
access to ROM

RD L

Read low

Read control generated
either in response to
CPU RD L, for CPU read
transactions, or DMA L,
for video access of
screen data stored in RAM

RESET COMM H

Reset comm high

Reset signal to DUART in
system communication logic
to initialize to known
start condition

RESET CRT L

Reset CRT low

Reset signal to CRT
controller in video logic
to initialize to known
start condition

RESET TIM L

Reset timing low

Reset signal to timing
circuit in video logic to
initialize to known start
condition

RxD

Receive data

Serial data input to
CPU from keyboard I/F
(refer to KBR)

SEL ATR0 L

Select attribute
RAM 0 low

Enables CPU read/write
access or video logic
access (during DMA
transaction), of
attribute RAM 0

4-20

Table 4-2

CPU Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

SEL ATRI L

Select attr~bute
RAM 1 low

Enables CPU read/write
access or video logic
access (during DMA
transaction), of
attribute RAM 1

SEL CONF REG L

Select configuration
register low

Enables CPU write access
of configuration register

SEL CRT L

Select CRT low

Enables CPU read/write
access of CRT controller
in video logic

SEL DUART L

Select DUART low

Enables CPU read/write
access of DUART in system
comm logic

SEL NVR L

Select NVR low

Enables CPU read/write
access of NVR

SEL RAM0 L

Select RAM 0 low

Enables CPU read/write
access of RAM 0, during
CPU read/write
transactions, or video
logic read access of RAM 0
during DMA transactions

SEL RAMI L

Select RAM 1 low

Enables CPU read/write
access of RAM 1, during
CPU read/write
transactions, or video
logic read access of RAM 0
during DMA transactions

TxD

Transmit data

Serial data output from
CPU to keyboard I/F
(refer to KBT)

VERT SYNC L

vertical sync low

Input to CPU from CRT
controller in video logic
defining vertical sync
period

WR L

write low

CPU control defining write
access of non-ROM system
component

4-21

Table 4-3

CPU Logic Schematic References

Circuit/
Component

Logic Board
Reference No. (s)

Schematic
Page Coordinates

Address Latch
Communication F/F
Configuration Register
CPU
CPU clock
Data buffer
Jl
J2*
Keyboard connector*
KYBD driver, receiver
NVR
Output components*
Power reset
RAM ~
RAM 1
RAM/DUART decoder
RD gate
RD/WR decoder
ROM ~
ROM 1

E2
E32
E26
El,E24,Ll,Rl
Yl,C8,C9
E9,E38
Jl
J2
J6
ES4,ESS
E17

1
2
2
1
1
1
1
1
1
1
2
1
1
2
2
1
1
1
1
1

L6~S-L6~8

C2,CS,C44~1,L2,RZ

Ell
El~

E33,E39
E31
E23,E31
E4
E3

BS
BS
B7
BS-B7
B7
Cl
A8
08
Cl
A7-A8
C4
Cl
B7
C7
CS
B3
AS
A4-AS
CS
C6

* indicates references are for components physically mounted on PS
and monitor board; all other references are for components on
logic board.

4-22

CHAPTER 5
SYSTEM COMMUNICATION LOGIC

5.1

GENERAL

The system communication logic (shaded area in Figure 5-1)
interfaces with the printer, via the printer port, and with the
host (via either the EIA host port, or 2~ rnA host port).

PSAND
MONITOR
BOARD

EIA
PRINTER
HOST PORT
PORT

20mA
PORT

OPTION
• CONNECTOR PHYSICALLY MOUNTED ON
PSAND MONITOR BOARD

Figure 5-1

VT229 Series Terminal
Functional Block Diagram

5-1

Printer interfacing is independent of host interfacing. EIA port
and 20 rnA port interfacing, however, are not independent. When one
interface is enabled (EIA host port or 20 rnA port), the other is
disabled.
NOTE
The enabling and disabling of the host
interfaces is primarily a function of
firmware
response
to
system
configuration data supplied by set-up
feature selection.
In addition to communication functions, part of the system
communication logic is programmed by the CPU logic to provide
control and status report functions for the video logic (refer to
the DUART description provided in section 5.2.1).
Operation of the system communication logic is completely under
control of the CPU logic. The CPU logic programs operational
parameters, reads status, and directs transfer of data to and from
the system communication logic.
5.2

MAJOR CIRCUITS AND COMPONENTS

Figure 5-2 provides a block diagram identifying these five major
circuits and components that make up the system communication
logic.
•
•
•
•
•

Dual asycronous receiver/transmitter (DUART)
Host data mux
Printer interface (PRINTER I/F)
EIA host interface (EIA HOST I/F)
20 rnA interface (20 rnA I/F)

5-2

TO/FROM
VIDEO LOGIC
MA-0631-84

Figure 5-2

5.2.1

System Communications
Logic Block Diagram

Dual Asynchronous Receiver/Transmitter (DUART)

The DUART transfers host and printer data between the CPU logic
and the following interfaces: EIA host interface, 20 mA interface
(with host data transferred between the DUART and the host port
via the host data mux) , and the printer interface (for printer
data) •
Figure 5-3 identifies the DUART components.
•

2681 DUART -- is a device that performs the data transfer
functions.

•

DUART clock
is a crystal oscillator device that
provides 3.6864 MHz input for 2681 DUART timing.

The 2681 DUART device is also used in video logic operations. Some
of the 2681 DUART's input and output ports are programmed by the
CPU logic for control register (output ports) and status register
(input ports) functions.

5-3

BAD 7 H

BAD 4 H

BAD 2 H

02
01

A2 H
A1 H
AO H
WRL
CPU RDL
SEL DUART L
RESET CMM H
CMM INT L
TVB H

OP2

OP1

OPO

IPO

WRN

IP1

RDN

IP2

CSN

IP6

SPD SEL H
DTR H
TO/FROM
EIA
HOST

RTS H
CTS H

ifF

DSR H
SPD IND H
INOT USEDI

REST
INTRN
IP3

TBLK H

IP4

132 COL H
BNK SO H

OP4
OP5

BNK Sl H
DIS VIDEO H
BLINK H

2681
DUART

A3 H

CONTROLS
TO/FROM
VIDEO
LOGIC

TO/FROM
HOST DATA
MUX

}

BAD 3 H

BAD 0 H

CONTROLS{
TO/FROM
CPU
LOGIC

HOST RxD H

BAD 1 H

ADDRESS {
FROM
CPU
LOGIC

HOST TxD H

RxDA

BAD 5 H
DATA
TO/FROM
CPU
LOGIC

TxDA

BAD 6 H

OP6

'TxDB

OP7

RxDB

OP3

IP5

TxDB
RxDB

}

PTR DSR H

TO/FROM
PRINTER

ifF

,.. ~-l
I

HB~ I
II
L~~~KJ
C7

-...

Figure 5-3

MA-Q632-84

DUART Block Diagram

5.2.1.1
2681 DUART Internal Circuits -- Figure 5-4 provides a
block diagram showing the major 2681 DUART internal circuits.
•

Data bus buffers
transfer data between the 2681
DUART's internal circuits and the CPU logic data lines.

•

Operation control -- decodes read (CPU RD L), write (WR
L),
address
(A0 H-A3 H), and chip enable (SEL DUART L)
inputs to enable CPU logic access to control, status, and
data registers within the various 2681 DUART circuits.

•

Timing
generates the
required for operation.

5-4

clock

and

baud rate signals

f'0---J\

....

DATA
BUS
BUFFERS

~DO H-BAO~

( ....

'-r---v'

ir
SEL DUART L

OPERATION
CONTROL

....
\

X2
TIMING

"l.

IINTERRUPT
CONTROL

----

DTR H
SPD SEL H
BLINK H

RxDB

fo-

f0Z

...J
e(

~ ~ r--

CTS H

(0)

~h>

~ -

(1)
INPUT (2)
PORT (3)
(4)

....

(5)

(6)

....

DSR H
SPD IND H
TVB H
TBLK H
PRTR DSR H
(NOT USED)

If
RTS H

TxDB
CHANNEL
B
(PRINTER)

{

RESET CMM H

CMM INT L

~
I-- 510

AOH-A3H)

HOST RxD L

LJ'

WRL
CPU RD L

HOST TxD L
CHANNEL
A
(HOST)

(0)
(1)
(2)

(4)
OUTPUT
PORT

(5)
(6)

(7)

(3)

132 COLH
BNK SO H
BNK S1 H
DIS VIDEO H

MA-0633-B4

Figure 5-4

2681 DUART Internal Circuits Block Diagram

•

Channel A (host) -- converts host transmit data to serial
data output (HOST TxD H), and serial host receive data
input (HOST RxD H) to parallel data.

•

Channel B (printer)
converts printer port transmit
data to serial data output (TxD B), and serial printer
port receive data (RxD B) to parallel data.

•

Interrupt
generates a programmable interrupt (CMM INT
L) to the CPU logic.

•

Output port -- contains eight output ports programmed to
provide video logic control register functions (132 COL
H, BNKS0 H-BNK Sl H, DIS VIDEO H, AND BLINK H), an EIA
host port data terminal ready output (DTR H), and modern
handshaking outputs (RTS Hand SPD SEL H).

5-5

•

Input port -- contains state change detection devices and
six active input ports (port six is not used) programmed
to accept data set ready inputs (PRTR DSR Hand DSR H),
video logic status register functio'ns (TVB Hand TBLK H),
and modem handshaking inputs (CTS Hand SPD IND H).

Later in this chapter, Table 5-2 describes the signals shown in
Figures 5-3 and 5-4.
5.2.1.2 2681 DOART Addresses -- The CPU logic accesses various
2681 DUART internal registers to perform any of the following
functions.
•

Provides program control for the communication functions

•

Provides program control for
defining output port values

•

Reads communciation function status

•

Reads video logic status by reading input port values

•

Transfers host and printer data to and from the DUART;
CPU logic access is done by addressing a specific device
(A0 H-A3 H), defining a read (CPU RD L) or write (WR L)
transaction while the DUART is enabled (SEL DUART L).

video logic functions by

Table 5-1 defines the registers that can be addressed, with
definition provided by address, read/write operation, and the
involved circuit (Appendix C provides a complete description of
the register bit values).
NOTE
No information is provided in Appendix C
for the BF7E (RD or WR) or BF7F (RD or
WR). Two of these addresses are used
simply to start (BF7E RD) or stop (B7FF
RD) the counter, while the other two are
used to set (BF7E WR) or reset (BF7F WR)
all output register bits.

5-6

Table 5-1

2681 DUART Addresses

Address

RD/WR

Circuit

B7Fr.JH
B7Fr.JH
B7F1H
B7F1H
B7F2H
B7F3H
B7F3H
B7F4H
B7F4H
B7F5H
B7F5H
B7F6H
B7F6H
B7F7H
B7F7H
B7F8H
B7F8H
B7F9H
B7F9H
B7FAH
B7FBH
B7FBH
B7FDH
B7FDH
B7FEH
B7FEH

RD
WR
RD
WR
WR
RD
WR
RD
WR
RD
WR
RD
WR
RD
WR
RD
WR
RD
WR
WR
RD
WR
RD
WR
RD
WR

Host channel
Host channel
Host channel
Host channel
Host channel
Host channel
Host channel
Input port
Timing
Interrupt
Interrupt
Timing
Timing
Timing
Timing
Printer channel
Printer channel
Printer channel
Printer channel
Printer channel
Printer channel
Printer channel
Input port
Output port
Timing
Output port

B7FFH
B7FFH

RD
WR

Timing
Output port

Mode (1 & 2) A
Mode (1 & 2) A
Status A
Data clock select A
Command A
Receive data A
Transmi t data A
Input change
Auxiliary control
Interrupt status
Interrupt mask
Counter timer (upper)
Counter timer (upper)
Counter timer (lower)
Counter timer (lower)
Mode (1 & 2) B
Mode (1 & 2) B
Status B
Data clock select B
Command B
Receive data B
Transmit data B
Input port
Output port configuration
Start counter command
Output bits command (set
bi ts)
Stop counter command
Output bits command (reset
bits)

5.2.1.3 2681 DUART Timing Diagrams -- Figures 5-5 and 5-6 provide
timing diagrams for DUART transmit data (Figure 5-5) and receive
data (Figure 5-6) activity.

5-7

TxDBI
HOST TxD H
TRANSMITIER
ENABLED
TxRDY

WRL

05 WILL I
NOT BE
TRANSMITTED

CTSH

HOSTRTSH~
OPRID

l,J

OPRID

NOTES

HOST RTS L IS USED ONLY BY AN EXTERNAL MODEM.

ALL MODEM HANDSHAKING SIGNALS ARE CONSIDERED TRUE
FOR MODEM COMMUNICATION (SPD SEL H OUTPUT AND SPD IND
H INPUT WOULD AFFECT BAUD RATE OF TIMING FOR MODEM
OPERATIONS, BUT NOT RELATIONSHIP OF TIMING SHOWN).

ALL DTR OR DSR SIGNALS ARE CONSIDERED TRUE.

CTS INPUT ACTIVE ONLY FOR MODEM COMMUNICATION.

DTR H IS NOT USED BY THE 20mA I/F.

PRTR DSR L WILL BE SAMPLED BEFORE TxDB OUTPUT IF PRTR DSR
L WAS NOT TRUE AT 2681 DUART POWER-UP

MA...()634-84

Figure 5-5

5.2.2

2681 DUART: Transmit Data Timing Diagram

Host Data Mux

The host data mux routes serial data between the 2681 DUART and
either the 20 mA I/F or the EIA host I/F. The I/F selected for
data transfer is dependent on control signal inputs from the CPU
logic (ENA EIA H or ENA 20 mA H).
The
host data
components.

(Figure

5-7)

mux

consists

the

following

•

RxD mux
gates RxD inputs from the host I/Fs with
control inputs from the CPU logic to generate HOST RxD H
input to the 2681 DUART (from EIA RxD H when ENA EIA H is
true, or from 20 mA receive circuit when ENA 20 mA H is
true) •

•

TxD mux -- routes HOST TxD H input from 2681 DUART out as
either 20 mA TxD H (when ENA 20 mA H is true) or as EIA
TxD H (when ENA 20 mA H is false).

Later in this
Figure 5-7.

chapter, Table 5-2 describes the signals shown in

5-8

RxDB/
HOST RxDH
RECEIVER
ENABLED
RxRDY
(SRDY) _ _ _ _- - '
F FULL
(SRl)

--------t------.......

RxRDY
CPU RD L
STATUS DATA

'------'

D1
OVERRUN
(SR4) -----------------...;;;;:~

RESET BY COMMAND

NOTES

DTR AND DSR ARE CONSIDERED TRUE.

MODEM HANDSHAKING SIGNALS ARE CONSIDERED TRUE FOR
MODEM COMMUNICATION.

MA·0635-B4

Figure 5-6

2681 DUART: Receive Data Timing Diagram

FROM (20mA RECEIVE)
20mA..:..:.:..........;.;..;.::...;..~

IIF

rx~---I
HOST RxD H

FROM
EIA
HOST

'---L--,)O--~~~~~---'DUART
EIA RxD

ifF

_ _ --1

FROM {

ENA EIA H

CPU
LOGIC

ENA 20mA H

EIA TxD H

TxD
MUX

FROM
DUART

~;;..;....~...;.;...----. . EIA HOST

I/F
~20;...m;...A..;...;.;Tx;...D:........H_ _ _ TO 20mA IIF

HOST TxD H

MA-0636-84

Figure 5-7

Host Data Mux Block Diagram

5-9

5.2.3

Printer Interface (I/F)

The printer I/F buffers communication between the terminal and a
printer connected to the printer port. Serial control and print
data is output to the printer as TxDB, while serial flow control
data is input from the printer as RxDB.
Printer I/F components are physically located on both of the
terminal PCBs. Figure 5-8 provides a breakdown of the printer
interface.
•

EIA driver and receivers -- interface TTL logic with
EIA level communication lines.

•

Jl (logic board)/J2 (PS and monitor board) -- are 25-pin
connectors used for routing signals between the two PCBs.

•

Printer
port (J4)
is a 9-pin EIA RS232C/RS423
connector, physically mounted on the PS and monitor
board; it is used to connect the terminal to the printer.

•

Printer port loopback connector
is used for test
purposes; it also routes ready and data signals back into
the terminal.

PRINTER
PORT
(J4)
TxDB

PTR T

EIA DRIVER
'==----i AND
PTR DSR RECEIVERS
RxDB

I-------<~ 1

PTR R
PTR DSR

R250

+12V
PART
OF

3
4

(RTS)

(DTR)

'-----;6

(SGND)

(NC)

(NC)
'CONNECTED
TO CHASSIS
GROUND

PART OF
LOGIC BOARD

PRINTER PORT
LOOPBACK CONNECTOR

.....

(PGND)'

1+-----1 2

PART OF
PS AND MONITOR
BOARD

""~

LOOPBACK PIN· OUT
FROM PIN

TO PIN

6
MA-0637-84

Figure 5-8

Printer I/F Block Diagram

5-HJ

Figure 5-8 also provides a pin-out for the printer port loopback
connector.
Figure
5-9 provides a complete pin-out of the
interconnection between the logic board and the PS and monitor
board. This connection is used for rQuting signals between the
video logic and the monitor circuits, between the power supply and
the logic board, between the keyboard connector and the CPU logic,
and between the 20 rnA I/F components, as well as between the
printer I/F components.
Later in this
Figure 5-8.

chapter, Table 5-2 describes the signals shown in

PRODUCTION {

PROD/DATA/TALK

TEST
SIGNALS

"'m"I' {
SIGNALS

KEYBOARD {
SIGNALS
PRINTER (
I/F
SIGNALS

}

PROD RESET H
20mA T26
2
20m A T+

PROD RESET

20m A R-

20mA R-

20mA R+

20mA T20mA T+

KBT

KBR

TxDB

PRT T

PRT DSR

RxDB

PRT DSR

PRODUCTION
TEST
SIGNALS

} "'m"I'

SIGNALS

}

KEYBOARD
SIGNALS

}

PRINTER
ifF
SIGNALS

PRT R
+5V

+5V

POWER
SUPPLY
POTENTIALS

GND

+12V
-12VA

"",0
LOGIC

[

SIGNALS

VIDEO GND

HOR SYNC L

HOR IN

VER SYNC H

VERT IN

VIDEO OUT

VIDEO IN

PART OF
LOGIC BOARD

}

MO"W"

CIRCUIT
SIGNALS

PART OF
PS AND MONITOR
BOARD

NOTE
POWER SUPPLY, PRODUCTION TEST, VIDEO
LOGIC, KEYBOARD, AND MONITOR CIRCUIT
SIGNALS ARE IDENTIFIED FOR REFERENCE
ONLY
NO
FURTHER
DESCRIPTION
IS
PROVIDED IN THIS CHAPTER CONCERNING
THESE SIGNALS.
MA-0638-84

Figure 5-9

Logic Board (Jl)/PS and Monitor Board (J2)
Interconnection Diagram

5-11

5.2.4

EIA Host Interface (I/F)

The ETA host interface buffers communication between the terminal
and a host (or modem) connected to the ETA host port.
Figure 5-10 provides a breakdown of the ETA host interface.
•

ETA driver and receiver -- interface TTL logic with ETA
communication lines.

•

J2 -- is a 25-pin ETA RS232C/RS423 connector, physically
mounted on the logic board; it is used to connect the
terminal to a local or remote host (via modem).

•

Data loopback connector -- used for test purposes, routes
signals back into terminal.

•

J4 -- is a a-pin connector with jumper plug inserted when
VT22X modem option is installed; it provides output of
operational
voltages
and
data/talk
signal
(PROD/DATA/TALK)
to the modem (J4 pins are shorted by
jumper as shown in Figure 5-10).
EIA'
HOST
PORT
(J2)

XMIT DATA
I-'-~....::..;..;.;..;..;...------t 2
REC DATA

EIA TxD H
EIA RxD H

1+'""'""-::.:.;.;"-'-------1 3
I -RTS
'-"'-"---------t 4

RTS H

CTS
~..;..;;..--------I
5
EIA DRIVERS
DSR
1+"..;.....--------16
AND
SPDIND
RECEIVERS
7
DTR

CTS H
DSR H

00' '0"[
DUART

TO
CPU
LOGIC

SPD IND H
DTR H
SPD SEL H

SPD SEL

CAR DET H

CAR DET

'PINS 11.
15-19. 21.
22. 24-26.
NOT USED

.-------18

ri-----t 9

13
14

L---+--+-+-+-t 20
L---+-+-+-1-+I23
J4
PART OF

J1
LOOPBACK PIN-OUT
PROD
TEST
INPUT

+5V
R59

-12VA

FROM PIN

TO PIN

MA-0639-84

Figure 5-10

ETA Host T/F Block Diagram
5-12

Figure 5-10 provides a pin-out for the EIA host port loopback
connector. Later in this chapter, Table 5-2 describes the signals
shown in Figure 5-10.
5.2.5

20 mA Interface (I/F~

The 20 mA interface buffers communication between the terminal and
a local host connected to the 20 rnA host port. Serial data is
output to the host as 20 rnA TxD H, and input from the host as ~0
rnA RxD H.
20 rnA I/F components are physically located on both of the
terminal pcbs. The 20 rnA interface (Figure 5-11) is composed of
the following parts.
•

Transmit
TTL/20 rnA converter
provides isolation
between the TTL level transmit data signal (20 rnA TxD H)
at the terminal, and 20 rnA level signals (T+/T-) on the
20 rnA port communication lines.

•

Receive 20 rnA/TTL converter -- provides isolation between
the TTL level receive data signal (20 rnA RxD H) at the
terminal, and 20 rnA level signals (R~/R-j ~n the 20 rnA
port communication lines.

Ir--l
-12V

I R402 I
I
I

TTL/20mA
CONVERTER

20mA
RxD H

(J5)

I ~~+-t 1 (NC)'

L-I---JVVV~'"

..JV'orY'\......L......I

3
4 (NC)

L.JV""'"'-4-al5

20rnAmL
CONVERTER

PART
OF
J1

(NC)

20 rnA LOOPBACK CONNECTOR
B (PROT GNO)"
"USED BY
LOOPBACK
CONNECTOR

PART OF
LOGIC BOARD

PART OF
PS AND MONITOR
BOARD

Figure 5-11

20mA
PORT

20 rnA I/F Block Diagram

5-13

LOOPBACK PIN-OUT
FROM PIN

TO PIN

MA"064~84

•

Jl
(logic board)/J2 (PS and monitor board) -- are 25-pin
connectors used for routing signals between the two PCBs.

•

Output components -- provide control signals and voltage
potentials required for 2~ rnA loop operation, and lessen
radiated high frequency noise.

•

2~
rnA host port
(J5)
is a a-pin 2~ rnA connector,
physically mounted on the PS and monitor board, used to
connect the terminal to a local host.

•

2~
rnA loopback connector -- is used for testing, routes
signals back into the terminal

Figure 5-11 provides a pin-out for the 2~ rnA loopback connector.
For a complete pin-out of the connection between the logic board
and the PS and monitor board, refer to Figure 5-9.
Complete descriptions
in Table 5-2.
5.3

of the signals shown in Figure 5-11 follow

SIGNAL DESCRIPTIONS

Table 5-2 provides descriptions of all the signals identified in
this chapter. These descriptions are provided for reference, and
are listed alphabetically by mnemonic, with numeric mnemonics
listed last.
System Communication Logic Signal Descriptions

Table 5-2
Mnemonic

Signal

A~-A3

Address bits
~-3 high

BAD~-BAD7

BLINK H

BNKS~-BNKSl

Description
~-3

high

Input to DUART from CPU
logic defining DUART device
to be accessed for read
(CPU RD L~ or write (WR L)
transaction

Bus lines for transfer of
data between DUART and CPU
logic

Buffered data bits
through 7 high

Control output from DUART
to video logic defining
blinking attribute

Blink H

H bank select 0-1 high

5-14

Control outputs from DUART
to video logic providing
two most significant bits
of address to line buffer
memory in that logic

Table 5-2

System Communication Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

CAR DET H

Carrier detect high

Status input from modem,
routed to CPU logic by EIA
IIF, indicating modem has
detected a good
communication line

CMM INT L

Communication
interrupt low

Programmable interrupt
output from DUART

CPU RD L

CPU read low

CPU logic input to DUART
defining a read transaction
when DUART is selected for
access (SEL DUART L)

CTS H

Clear to send high

Handshaking input from
modem, routed to DUART via
EIA host IIF, indicating
modem is ready to receive
transmit data (EIA TxD H)

DIS VIDEO H

Disable video high

Control output from DUART to
video logic defining
disabled video

DSR H

Data set ready high

Handshaking input from
modem, routed to DUART via
EIA host IIF, indicating
modem is ready for
communication activity

DTR H

Data terminal
ready high

Two outputs, one for printer
and one for modem;
Handshaking output from
DUART to modem, via EIA host
IIF, indicating terminal is
ready for communication
activity; output from
printer port developed from
+12 V whenever terminal is
powered

EIA RxD H

EIA receive data high
data high

Serial data input from the
EIA Host port (as REC DATA)
to the EIA host IIF, from
either a local host or
modem, and routed to DUART
(as HOST RxD H), via host
data mux

5-15

Table 5-2

System Communication Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

EIA TxD H

EIA transmit
data high

Serial data output from the
EIA host port (as XMIT DATA)
to either a local host or
modem, originating at DUART
(as HOST TxD H), and routed
to EIA host port via host
data mux and EIA host I/F

ENA EIA H

Enable EIA high

Control input from the CPU
logic enabling host data mux
to pass data between the
DUART and the EIA host I/F

ENA 20 rnA H

Enable 20 rnA high

Control input from the CPU
logic enabling host data mux
to pass data between the
DUART and the 20 rnA I/F

HOST RxD H

Host receive
data high

Serial data input to the
DUART from the host data
mux (refer to EIA RxD Hand
20 rnA RxD H)

HOST TxD H

Host transmit
data high

Serial data output from the
DUART to the host data mux
(refer to EIA TxD Hand
20 rnA TxD H)

PGND

Protective ground

Printer port ground
potential output to printer

PROD/DATA/
TALK

Production/data/talk

Modem control signal
high for talk mode and low
for data mode

PROT GND

Protective ground

20 rnA port output used for
loopback testing (ties T+ to
ground)

PTR DSR

Printer data
set ready

High input to DUART from
printer I/F when printer is
ready for communications
activity

PTR R

Printer receive

Serial data input from
printer port routed to DUART
by printer I/F (as RxDB)

5-16

Table 5-2

System Communication Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

PTR T

Pr i nter

R-/R+

Receive -/receive +

20 rnA loop serial data
inputs to the 20 rnA I/F sent
to host data mux (as 20 rnA
RxD H) where it is routed to
DUART (as HOST RxD H)

REC DATA

Receive data

Serial data input to EIA
host port (refer to EIA RxD

transm~t

Serial data output to
printer port from printer
I/F originating at DUART (as
TxDB)

H)
RESET CMM H

Reset communication
high

CPU logic input to DUART
resetting DUART to known
start condition

RTS H

Request to send
high

Two outputs, one for printer
and one for modem:
Handshaking output to modem
from DUART, via EIA host
I/F, when DUART has data to
be transmitted; Output to
printer developed from +12 V
whenever terminal is powered

RxDB

Receive data
channel B

Serial data to DUART
originating at printer port
(refer to PTR R)

SEL DUART L

Select DUART low

Enable to DUART from CPU
logic for read (CPU RD L) or
write (WR L)

SGND

Signal ground

Ground output from printer
port

SPD IND H

Speed indicator high

Handshaking input from modem
to DUART, via EIA host I/F,
defining receive and
transmit speeds of 1200 bps,
regardless of the speeds
selected by set-up feature

5-17

Table 5-2

System Communication Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

SPD SEL H

Speed select high

Handshaking output from
DUART to modem, via EIA host
I/F, when set-up selection
of receive speed is greater
than 600 bps

T-/T+

Transmit -/transmit +

20 rnA serial data outputs
from 20 rnA I/F originating
at DUART (as HOST TxD H),
and routed to 20 rnA I/F by
host data mux (as 20 rnA TxD
H)

TBLK H

Test blank high

Status input to DUART from
video logic indicating video
blank circuitry is
functional (used only during
self-test)

TVB H

Test video bits high

Status input to DUART from
video logic indicating video
serial steam is functional
(used only during self-test)

TxDB

Transmit data

Serial data output from the
DUART Channel B for the
printer (refer to PRT T)

WR L

Write low

Selects DUART for write
transaction when DUART is
enabled (SEL DUART L)

X1/X2

Crystal 1/crysta1 2

Crystal input to DUART for
timing

XMIT DATA

Transmit data

Serial data output from
EIA host port (ref.
EIA TxD H)

-12 V

-12 Vdc

Voltage potential output
from 20 rnA port developed
across two resistors and
used for loopback testing
(ties R- to -12 V)

+12 V

+12 vdc

Voltage potential used to
develop RTS and DTR outputs
from printer port

5-18

Table 5-2

System Communication Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

20 rnA RxD H

20 rnA receive
data high

Serial data input from the
20 rnA port (as R-/R+) to the
20 rnA I/F from a local host,
and routed to DUART
(as HOST ~xD H), via host
data mux

20 rnA TxD H

20 rnA transmit
data high

Serial data output from
the 20 rnA port (as T-/T+)
to a local host, originating
at DUART (as HOST TxD H),
and routed to 20 rnA port
via host data mux and
20 rnA I/F

132COL H

132 column high

Control output from DUART
to video logic defining
screen attribute of
132 columns enabled

5.4

SCHEMATIC REFERENCE INFORMATION

Table 5-3 identifies the logic board and PS and monitor board
component coordinate, and the schematic page and coordinate for
each of the system communication logic components and circuits
identifed in this chapter.
NOTE
The reference information provided in
Table 5-3 is based on CS 5415653-9-1,
Rev.
A, for logic board references, and
on CS 5415651-9-1, Rev. A, for the PS
and monitor board.

5-19

Table 5-3

System Communication Logic Schematic References

Circuit/
Component

PCB
Name

Board
Ref. Numbers

Schematic
Page Loc.

DUART (2681)
DUART clock
ErA host port
J1

Logic
Logic
Logic
Logic

E15
Y2,C7
J2
J1

6
6
6
6

J2
ErA drivers,
receivers (ErA)
ErA drivers,
receivers (PRTR)
Output components

PS/MTR
Logic

Printer port
Rx 20 mA/TTL
converter
RxD mux
Tx TTL/20 mA
converter

PS/MTR
Logic

TxD mux
20 mA port

Logic
PS/MTR

Logic
Logic

J2
E52-E57,R27-R31,
R35,R53,C22,C23
E51,E52,R32,R33,
C14,C15
L601-L604,R402,
R403
J4,R250
E40,Cl1,D7,
R46-R51,Q5,Q6
E24,E31,E39,E48
E47,E48,C12,C13,
D6,D8,R44,R45,
R52,Q3,Q4
E33
J5

5-20

D7
C7
D3
A7,B1,
B5,C6
B1
A8
D8
D6-D2/
C5-C2
C6

1
6

D1
B6

6
6

2
1

A4
C1

5
1
1
6

B6-B8

CHAPTER 6
VIDEO LOGIC

6.1

GENERAL

The video logic
(shaded portion of Figure 6-1) generates the
outputs needed to drive the monitor circuits and CRT (video and
sync signals). It can also drive an optional slave monitor device
(composite video output).

COMPOSITE
VIDEO

PSAND
MONITOR
BOARD
AC
I N PUT L-.-r----.

LOGIC
BOARD

EIA
PRINTER
HOST PORT
PORT

20mA
PORT

TO/FROM~~~~~
EIAHOST
PORT

MODEM
OPTION
'CONNECTOR PHYSICALLY MOUNTED ON
PS AND MONITOR BOARD

Figure 6-1

MA-0613-84A

VT220 Series Terminal
Functional Block Diagram
6-1

The video outputs are developed from character address and
attribute values stored in a line buffer memory within the video
logic. As each scan line of display is processed, the character
address values are used to select the characters to be processed
for
the scan line, while the attribute values define the
attributes to be associated with the characters being processed.
Character and attribute data is defined by CPU write transactions.
Character address data is stored in the CPU logic screen RAM.
Attribute values associated with each character are written into
the CPU attribute RAM at an address directly corresponding to the
address of the character address value stored in the screen RAM.
During DMA transactions, the video logic transfers the character
and attribute values to the line buffer memory for processing.
DMA transactions occur during the first scan line of each row of
screen data. The data is read out of the screen and attribute RAMs
in the CPU logic and transferred to a line buffer in the video
logic. At the same time the character address and attribute data
is applied to character generator and attribute circuits to get
the character dots for the first scan line. The remaining scan
lines are processed from the data stored in the line buffer.
MAJOR CIRCUITS AND COMPONENTS

6.2

The
video
logic
components/circuits.

•
•
•
•
•
•
•

(Figure

6-2)

consists

the

following

CRT Controller
Timing generator (TIMING GEN)
Blank circuits
Character generator (CHAR GEN)
Attribute circuits
Video converter
Video output

The video logic also uses input and output ports of the system
communication logic's 2681 DUART for status reporting (input
ports) and control register (output ports) functions (refer to the
description of 2681 DUART in section 5.2.1).

6-2

I VIDEO -

LOGIC

I I

---,

LOGIC

RESET TIM L

TIMING

--------~--~----------------------~ GEN

TIMING

BLANK
CIRCUITS

BLANK
CONTROLS

STATUS CONTROLS

_...J

--I
TO/FROM
SYSTEM COMM
DUART

Figure 6-2

Video Logic Block Diagram

6-3

VIDEO
OUTPUTS
MA-0641-84

6.2.1

CRT Controller

The CRT controller (Figure 6-3)
is a 9~~7 video processor and
controller (VPAC) device. The 9~~7 VPAC generates address and
control signals for the following functions.
•

Request for DMA transactions

•

Address values used during DMA transactions to access
character address and attribute data to be transferred to
the character generator circuit

•

Synchronization
controls
horizontal retrace periods

•

Address values to define specific scan line of an
addressed row of characters to be processed out for video
by the character generator

•

Controls for screen blanking

for

defining

vertical

and

The 9~~7 VPAC is not involved in cursor positioning. In the VT22~,
cursor positioning is a function of CPU logic firmware.
+5V
R5SnR5 7
A13 H
A12 H
All H

HS
CSYNC

A9H

DRB

TQ. VIDEO
OUTPUT

}

TO
S051 CPU

L-

DMA REQ L

A5H

A4H

VLT

A3H

A2 H

AOH

VLTH

~VLTL

CRT
9007
VPAC

A1H

TO
CHAR GEN

AO
SL3

BAD7 H
BAD6 H
SAD5H
BAD4H

SL2

SLl

SLO

SAD3 H
BAD2 H
BAD1H

CURS

CSLANK

BADOH

}

A6 H

FROM CPU
LOGIC
FROM
TIMING GEN

ASH

TO/FROM
S051CPU
AND FROM
CPU LOGIC
RAM

HOR SYNC L
CSYNCL

Al0

A7 H

CPU LOGIC
TO
RAM
AND FROM
S051CPU

A12
All

Al0H

TO
CPU LOGIC
RAM

A13

VERT SYNC L

DO
RST CS

RESET CRT L
SEL CRT L

TSC CLK

SC3 H
SC2H
SCl H
SCO H
CURS H
CBLANK H

}

TO
VIDEO
CONVERTER
TO
BLANK
CIRCUITS

DMAH
CRTCLK H

Figure 6-3

MA.o721-84

CRT Controller Block Diagram
6-4

9997 VPAC Internal Circuits -- The 9997 VPAC (Figure
6-4), as used in the VT229 series terminal, consists of the
following components/circuits.
6.2.1.1

•

Decode -- decodes CPU address inputs to determine type of
operation to occur, bf register device to be accessed.

•

Timing and control
generates control and address
values needed for overall video logic functionality.

r--------.,
I
I
PARAMETER REGISTERS
CHARS/HORZ PER

"""SC-A-N-L-IN-ES""':/-DA-T-A-R-OW-'

CHARS/DATA ROW

SCAN LlNESIVERT PER.

SCROLL'7:0NT'ROL

HORZ SYNC DELAY

CONFIGURATION

REGISTERS

HORZ SYNC WIDTH

SCROLL OFFSET

VERT SYNC WIDTH

DATA ROWS/FRAME

L-~_---'

VERT SYNC DELAY

BADD HBAD7 H

CURS H

rA;;;;E~~C~I~S-

I'---~-~~=----,
I
I
CSYNC L

ADH-A13H

HORZ SYNC L
REGISTER
ENABLE

RESET CRT l

TIMING
AND

CRT ClK H
DMAH----------------------~--------~

VERT SYNC L
VLT H
DMA REQ L
CBLANK H
SCD H-SC3 H
MA·0642·84

Figure 6-4

9997 VPAC Internal Block Diagram

6-5

•

Address control registers
generates address values
used to address CPU logic screen and attribute RAMs,
including registers containing the starting address of
character and attribute values (table address register)
and the current address to be accessed (video address
register) •

•

Cursor control registers -- generate CURS H output (used
for double height/double width data row function) based
on comparison of horizontal and vertical cursor position
values in relation to portion of screen display currently
being processed.

•

Parameters registers
operational
parameters
format.

•

Scroll control registers -- define start and stop display
data row values for scroll or screen blanking operations.

•

Row attribute register
defines height and width
processed

•

Status register -- contains flags concerned with whether
or not vertical retrace is in progress, or whether or not
the final table address has been read (all data to be
displayed during a given complete scan of the screen has
been read out of CPU logic RAM).

•

Control register
9007 VPAC.

contain information defining
concerning video control and

is a two-bit register that
values for data row being

defines

operational modes for the

Later in this chapter, Table 6-2 describes the signals shown in
Figures 6-3 and 6-4.
6.2.1.2 9007 VPAC Addresses -- The CPU uses write transactions to
program operational modes, parameters, cursor register values,
scroll and screen blanking row values, display memory position,
and row width and height values, as well as two commands affecting
entire 9007 VPAC operation (start and reset). Read transactions
are used by the CPU to obtain status or to verify current cursor
register values.
Access to internal 9007 VPAC registers is enabled by a low chip
enable input (SEL CRT L) accompanied by a valid address. No read
or write enable is used, as the address not only defines the
device to be accessed, but also determines whether it is to be
accessed for read or write.

6-6

Table 6-1 provides a complete listing of the 9007 VPAC addresses,
with identification of the addresses which are valid for 9007 VPAC
operation, as this device is used in the VT220, and the device or
command the address affects.
NOTE
A complete description of the bit values
associated with the various 9007 VPAC
registers is provided in Appendix C.
Table 6-1

9007 VPAC Internal Addresses

Address (hex)

RD/WR

Device/command

l7C0
l7Cl
l7C2
l7C3
l7C4
l7C5
l7C6
l7C7
l7C8

WR
WR
WR
WR
WR
WR
WR
WR
WR

l7C9
l7ca
l7CB
l7CC
l7CD
l7CE
l7CF
1700
1701
1702
1703-1704
1705
1706
1707
1708
1709
l70A-17F7
l7F8
l7F9
l7FA
l7FB-17FF

Characters/horizontal row register
Characters/data row register
Horizontal sync delay register
Horizontal sync width register
vertical sync width register
vertical sync delay register
Configuration/skew register
Oata rows/frame register
Scan lines/data row and scan
Lines/vertical period registers
Scan lines/vertical period register
(not used in VT220)
Control register
Table address register (low byte)
Table address register (high byte)
(not used in VT220)
Row attribute register
(not used in VT220)
Oata row start register
Oata row end register
(not used in VT220)
Start command (see note)
Reset command (see note)
Smooth scroll offset register
Vertical cursor register
Horizontal cursor register
(not used in VT220)
Vertical cursor register
Horizontal cursor register
Status register
(not used in VT220)

WR
WR
WR
WR
WR
WR
WR
WR
WR
WR
WR
RO
RO
RO

NOTE
start and reset commands are not written
to any specific device. They are decoded
into start or reset operations by the
9007 VPAC.
6-7

6.2.1.3
9997 VPAC Transactions -- The 9997 VPAC is responsible
for the basic control of video logic operations, including all of
the following functions.
•

Requesting access of CPU logic screen and attribute RAM's
for DMA transactions using DMA REQ L, with DMA H granting
access

•

Accessing character address and attribute values using A9
H-A13 H address outputs

•

Defining of trace and retrace periods through VLT H,
CSYNC L, HORZ SYNC L, and VERT SYNC L outputs

•

Controlling screen blanking using CBLANK H output

•

Controlling smooth and jump scroll operations

•

Defining
H output

double width/double height data rows using CURS

Smooth
and
jump
scroll operations are controlled by CPU
programming of 9997 VPAC registers. During jump scroll, new data
lines are displayed as soon as they are received. During smooth
scroll, the screen is offset by a specified number of scan lines
for each vertical retrace (for example, five retrace periods are
required to display a complete new data row when offset is two
scan lines per retrace period), resulting in each scroll being
done in increments over a longer period of time.
Double height/double width is also controlled by CPU programming
of 9997 VPAC registers. The CPU programs the cursor positioning
registers with the address of the data row to be double width, and
programs the row attribute register for single height/double width
or double height/double width functions (refer to Figure C-26 in
Appendix C for row attribute register values and functionality
associated with those values). The 9997 VPAC will then perform
appropriate DMA transactions to process a data row for single or
double height, while generating CURS H output during CBLANK H time
to define double width operation (refer to Section 6.2.7.1 for
description of how CURS H is used by the conversion control
portion of the video conversion circuit to control double width).
Figures 6-5 through 6-8 provide transaction and timing diagrams
for 9997 VPAC DMA, sync, and blanking operations. Additional
timing diagrams concerning video logic operation are provided in
the description of the timing generator circuitry (refer to
section 6.2.2).

6-8

HORZ SYNC L

, ' - -_ _ _.........

....J

VLTL

~~_ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _~

DMAREQL

~r-Jr------------------------------------------------~\~~--~_______

DMAH

00: 00: 00:

0
.....
co
00: 00:

>< >< ><

Wo Wo
Qo Qo
>< ><

'".....0:

Wo Wo Wo
Qo Qo Qo

A<13·00> H
I

BAD <7·0> H

0...J

~g; ~g;

0:
<

00 00

0:< 0:<

'"0:<

0
co
0:
<

J:
U

JlJU1J1. _____ Jl..11.. _____ _
CHR/ATRH

-- -

-- - - -

• = TRISTATE DRIVERS ENABLED

Figure 6-5

MA·0643-84

gee7 VPAC: DMA Transaction Diagram

LAST DISPLAYED SCAN

"'~or

CSYNC L

FIRST OF 240 DISPLAYED
SCANS IN NEXT FIELD
VERTICAL BLANKING INTERVAL- 22 SCANS

I-FI_EL_D_---I

---I

/--HORZ PERIOD = 63.EB p.s

_ J

. HORZ BLANK {11.S4 p.s/SO COLUMN

r--

~~~~~:~AL ~

12.34 p.s/132 COLUMN

r-l

r-l~__--,

CSYNCL~
irr-FRONT PORT = 1.54 p.s
-"'1r-HORZ SYNC = 4.71 p.s
1.4 p.s (22 SCANS)

VERTICAL
BLANKING

I I~---------'n ~-----------,Ir-1L -

VERTSYNCL-,ir-------_ _ _~r-------------~

-..j

It-- 127 p.s (2 SCANS)

-1r-- VERT SYNC = 5.6 p.s
MA·0644-84

Figure 6-6

ge07 VPAC: Composite Sync and Blanking
Timing Diagram

6-9

t - - - - - - O N E SCAN LINE

-------1

~-----R1------~

(RO-R1)

~---------RO-_1----~

VLTH~

ACTIVE DISPLAY TIME

HORZSYNCL----..,

~______________~~R3~

NOTES
R1

CHARACTERS PER DATA ROW REGISTER VALUE
(SO OR 132)

RO-R1

CHARACTERS PER HORIZONTAL PERIOD REGISTER
VALUE
HORIZONTAL RETRACE DEFINED BY RO VALUE LESS
R1 VALUE

HORIZONTAL DELAY REGISTER VALUE

HORIZONTAL SYNC WIDTH REGISTER VALUE
MA-0645-84

Figure 6-7

9007 VPAC: Horizontal Timing

~----ONE COMPLETE FRAME-----~

R7XRS~
~---------R9---7------~

CBLANK H

---,L.! ____________
DATA ROW DISPLAY TIME
I
.J

VERT SYNC L - - - - - ,

~________________~~R4~

NOTES
R4

VERTICAL SYNC WIDTH REGISTER VALUE

VERTICAL DELAY REGISTER VALUE

R7XRS

VISIBLE DATA ROWS PER FRAME REGISTER
VALUE (R7) TIMES SCAN LINES PER ROW
REGISTER VALUE (RS)

SCAN LINES PER FRAME REGISTER VALUE
MA-0646-84

Figure 6-8

9007 VPAC: vertical Timing

6-10

6.2.2

Timing Generator

The timing generator provides all timing signals required for
video logic operation. Where the 9007 VPAC provides basic control
for video logic operation, the timing generator provides the
timing required to carry out those operations.
Timing outputs depend on whether the video logic is processing 80
or 132 characters per row display (defined by l32COL H input from
2681 DUART). During 80-column timing, ten dot clocks (DOT CLK H)
are used to process a complete character. During l32-column
timing, nine dot clocks are used.
Figure 6-9
generator.

identifies

the

components

that

make up the timing

•

Dot clock generator -- generates basic timing (as DOT CLK
H)
from either 22.896 MHz source (for l32-column) or
15.288 MHz source (for 80-column).

•

LBF WR gates -- are enabled during DMA transactions (SYNC
DMA H)
to provide low input to T5 H latch for LBF WR L
generation to load character and attribute data into line
buffer memory in character generator.

•

Tl gates
are enabled to generate low input to T5 H
latch for Tl H false on either T4 H (for l32-column) or
T5 H (for 80-column).

•

T5 H latch -- generates active high timing signals and
active low line buffer memory load signal (LBF WR L).

•

T5 L latch -- generates active low timing signals.

•

SYNC DMA latch -- latches value of DMA H input on ATR/CHR
going low, synchronizing DMA transaction activity.

Later in this chapter, Table 6-2 describes the signals shown in
Figure 6-9. Figure 6-10 provides a diagram of DMA and visible line
timing for 80-column display. A l32-column display is identical
except that all action occurring at the tenth dot clock in
80-column display occurs at the ninth dot clock in l32-column
display.

6-11

FROM
DMA H
SYNC DMi;
CPU ---;:.;,;,;c;..;,.:------.I
LATCH
LOGIC

R.6.~2rr________+~5~V__;

+5 V ~

r -

I
I
SYNC DMA H

~~~

R75

T5 L
+5V

T3 L

T1 H

...

I
I

r~r-~:----+-----~

LBF WR
GATES I

I-- - - - - - - - - - - - - - - 1
I
Tl
I

I
FROM
DUART

132 COL H

~~
T4 H

LBF WR L
T5 H

T3H
T2 H

T5 H
LATCH

X~>_~I--~~_r_+~

>T1 H

,..

T2 H

_____________ --.JI

---

FROM
CPU
LOGIC

RESET TIM L

• SHARES SAME PHYSICAL COMPONENT (LS174 LATCH) AS SERIAL AND SIN LATCHES IN VIDEO CONVERTER.
•• SHARES SAME PHYSICAL COMPONENT (LS174 LATCH) AS ATTRIBUTE LATCH 2

Figure 6-9

T4 H
T3H

].--

T4 H

GATES

T3 L

R60

T3H~

T5H

CRT CLK H

---1----------,

+5/
R6 ~

CRT
CLK

+5 V

SYNC DMA H

ATR/CHR

2Fz4Z _
~

132 COL H

Timing Generator Block Diagram

6-12

MA·0711·84

10 1 2

PIXELS

5 6

9 10 1 2

9 10 1

DOT ClK H

_______.....I

--.J
T2 H ----1
Tl H

T3H _ _ _-'

LL
I

T4H _ _ _ _....

T5Hl
LATCH CHARACTER INTO CHAR LATCH 2

LATCH CHARACTER INTO CHAR LATCH 2

I....___y.....l

T5lY

LATCH ATTRIBUTE INTO ATTR. LATCH 2

ATR/C,HR - ,
CRT ClK H.
VIDEO LATCH H.
lBA ClK l

LATCH ATTRIBUTE INTO ATTR. LATCH 2

L
r

--l

VITH-'~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

lBF WR l

SYNC DMA H.J

PIXELS

1 2

7 8

1 2

DOT ClK H

_______.....IrTl H--.J

'--_ _.....II

T2 H - . - J

~_---'r

T3H _ _ _....
T4 H

T5 H

-----'
l

LATCH CHARAC
...T-E-R-IN-T-O-C-H-A.....
R LATCH 2

r,LATCH CHARACTER INTO CHAR LATCH 2

O"""'-----.::!.....I

l
...J

T5 l
LATCH ATTRIBUTE INTO ATTR. LATCH 2
ATR/CHR
CRT ClK H.
VIDEO LATCH H•
lBA ClK l

VITH1~

LATCH ATTRIBUTE INTO ATTR. LATCH 2

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

lBF WR l

SYNC DMA H

J
MA-0643-84

Figure 6-10

DMA and Visible Line Timing Diagram
(Sheet 1 of 2)

6-13

PIXELS

10 1

9 10 1

DOT ClK H

'--__. . r.
T3 H

----'

T4 H

LL
- -.....' 1
L

-----'
I

T5Hl

LATCH CHAR (CHAR LATCH 2)

T5 l

':I

LATCH ATTRIBUTE (ATTR. LATCH 2)

(.LATCH ATTRIBUTE

1L.___':i...l

ATR/CHR

LATCH CHAR

I-f___

CRT ClK H.
VIDEO LATCH H.~
lBA ClK l
V~l -,~______________________________________

u--

CHR lD l

I...__.;.CH"""A_R_A.;.CT_E_R_1_ _ _ >C

CHARACTER ROM DATA H _ _ _ _ _ _ _ _ _ _....

MA·0649-84

PIXELS

DOT ClK H

'--__....Jr-

---.J

T1 H

T2H~

'--__.....r

T3 H _____..I

T4 H

----...I
lL.~~~~

T5 H
LATCH CHAR (CHAR LATCH 2)
T5 l

--"

'--

'::I

LATCH CHAR

I'--__y.....
I
Y
LATCH ATTR
Y IL.____y..,J

LATCH ATTRI8UTE (ATTR. LATCH 2)
ATR/CHR - ,
CRT ClK H.
VIDEO LATCH H
lBA ClK l
V~l

CHR lD l

-.J
IL.______________________________

CHARACTER 1
CHARACTER 2
CHARACTER ROM DATA H ______________..../~_-_-_..:;._;;.;._;.;._;.;;._;.;;._.;.;._;.;.._;..;._-_-_-_-.....
;;..,Xl...____
MA·065Q.84

Figure 6-10

DMA and Visible Line Timing Diagram
(Sheet 2 of 2)

6-14-

TBLK L
TBLK L
BLANK
LATCH
01
1Q
CLK
FROM
TIMING _T5_L_ _ _ _ _-t-_~

CLK

GEN.

TO
VIDEO
OUTPUT
TO
DUART

CG BLANK H

CBLANK L
(CLEAR)

}'"

VIDEO
CONVERTER

FROM
CBLANK H
CBLANKL } TO
9007 -O-IS-V-ID-E-O-H~'x)-'----------L-----+....L..--_
(CLEAR)
ATTRIBUTE
FROM
CIRCUITS
DUART
MA·0651·84

Figure 6-11

6.2.3

Blank Circuits Block Diagram

Blank Circuits

The blank circuits (Figure 6-11), generate blanking control
signals in response to blank input from either the 9007 VPAC
(CBLANK H)
or the 2681 DUART (DIS VIDEO H). In addition, a clear
signal is output to attribute and video output circuits to clear
those circuits for new processing.
Later in this
Figure 6-11.
6.2.4

chapter, Table 6-2 describes the signals shown in

Character Generator

The character generator processes character dot matrix values to
the video conversion circuit based on character address values
stored in a line buffer during DMA transactions. This processing
is done on a scan line to scan line basis for each row of screen
data.
DMA transactions occur at the first scan line of each row of
screen data. During DMA transactions, character address values
from the screen RAM, and attribute values from the attribute RAM,
are input to the character generator.
As each character address and associated attribute value is
transferred into the character generator circuit, it is stored in
a line buffer RAM. At the same time, character address data is
also passed to a character ROM (or alternate character RAM) for
output of the dot pattern associated with the first scan line of
the character address being stored. The associated attribute value
being stored in the line buffer is output from the character
generator, at the same time as it is being stored, to provide for
attributes affecting the dot pattern being output by the character
ROM (or RAM).

6-15

This process repeats for all characters being DMA'ed into the line
buffer RAM, until the first scan line for all characters in the
screen row has been processed (DMA transaction completed). The
remaining scan lines of the data row are processed by accessing
the character address and attribute values stored in the line
buffer RAM during the DMA activity. Once all the scan lines for
the screen row have been processed, a new DMA transaction will be
used to input the next screen row for display.
The character
circuits.
•
•
•

generator

(Figure

6-12)

consists

of three main

Access mux
Line buffer
Character (CHAR) output circuit

FROM
9007

,"OMt
CPU
LOGIC

FROM
DUART

SCO H-SC3 H

TO/FROM
CPU LOGIC

AO H-A3 H
CHRO H-CHR7 H
CONTROLS

TO
VIDEO
CONVERTER

BNKSO H-BNKS1 H

FROM
8051 CPU ~_ _--,

FROM
SCREEN RAM

TO
ATTRIBUTE
CIRCUITS

.1.------1

FROM
ATTRIBUTE
ADO H-AD7 H
~..;.;;;.;...;...;.;;;.;..;..~
RAM
FROM r--~~~-I
TIMING
TIMING
GEN

MUX
FROM
(ALT SELl
ATTRIBUTE --'---'---~
CIRCUITS
L -_ _.....

Figure 6-12

MA-0652-84

Character Generator Block Diagram

6-16

The access mux
(Figure 6-13) selects
6.2.4.1
Access Mux
outputs based on select input
(EN CHR GEN RW H) from the CPU
logic. video logic inputs when select is low and CPU logic inputs
when select is high.
The video logic accesses character generator circuits to load
character and attribute values during DMA transactions, and to
process those values out. The CPU logic accesses the character
generator to load alternative character formats into the character
output circuit, or to read back previously loaded characters.
Later in this
Figure 6-13.

chapter, Table 6-2 describes the signals shown in

FROM
ATIRIBUTE
CIRCUITS

(ALT SEL ATIRIBUTEI
4A

ALT SEL
4Y

4B
3A
FROM
TIMING
GEN
FROM

T5 L

VLT L

ALTSELH

{

ACCESS
MUX

,---. 28

9007

LBA CLKS H

FROM
CPU
LOGIC

LBA CLK L
3Y

3B
2A

TO
CHAR
OUTPUT

VIDEO
LATCH H
2Y

1A
1B

}

TO
LINE
BUFFER

LBA CLR H
1Y
SEL

CHR ADDR WR L
LBA CLRS H

ENCHRGEN RW H
MA-0653_B4

Figure 6-13

Access Mux Block Diagram

6-17

6.2.4.2
Line Buffer -- The line buffer circuit is used to store
character address and attribute values during DMA transactions,
and to process those character address and attribute values out to
the character output (character address data)
and attribute
(attribute data) circuits.
The line buffer
components.

circuit (Figure 6-14) consists of the following

•

Line buffer address counter -- is clocked by LBA eLKS L
to generate a sequential address value to address buffer.

•

Address buffer
loads new address value on each TS L
time to provide sequentially incrementing address input
to the line buffer RAM.

FROM
TIMING
GEN

{:::~:A

.....;T..:.;5L~_ _ _ _ _.....,

LBF WR L
FROM
CPU LOGIC

LBF DISABLE H

BNKSl H
~------+-+-~A10
FROM { ilNKSO H
DUART -------+-+-~

rLi'NE"'B'UFFER ,

I
I

ADDRESS
COUNTER

LBA CLR H

FROM {
ACCESS
MUX

DATA
INPUT
BUFFERS

FROM
B051 CPU
OR
SCREEN RAM
FROM
ATTRIBUTE
RAM
TO
ATTRIBUTE
CIRCUITS

TO
CHAR
GEN
ADDRESS
BUFFER

LBA CLK L

MA-0654-84

Figure 6-14

Line Buffer Block Diagram

6-18

•

Line buffer RAM -- is a 2K X 8-bit wide RAM device that
provides for storage and processing of the following
character address data and attribute values:
•

A0-A7 inputs define the 8-bit position into which
character address or attribute data will be loaded;

•

AS input
(ATR/CHR) defines character address data
(ATR/CHR high)
or attribute value (ATR/CHR low) is
being loaded;

•

A9-A10 inputs define one of four banks of memory
space, each bank containing 512 bytes of memory space
for character address and attribute values (256 bytes
for each).

Figure 6-14 also shows the data input buffers which consist of two
latch devices.
•

Attribute latch
is used during DMA transactions to
transfer attribute values to the line buffer RAM and to
provide the attribute values to the attribute circuits
for the first scan line of the screen row undergoing DMA.

•

Character latch
is used during DMA transactions to
transfer character address data to the line buffer RAM
and
to provide the character address data to the
character output circuit for the first scan line of the
screen row undergoing DMA.

Loading character address and attribute values into the line
buffer RAM is enabled by SYNC DMA H high, LBF WR L low, and LBF
DISABLE H low. During read out of character address and attribute
values, SYNC DMA Hand LBF DISABLE H are both lows. LBF DISABLE H
is only high when the CPU logic is accessing the alternate
character generator in the character output circuit.
Figure 6-15 provides a memory map of the line buffer RAM. Figure
6-16 shows the attribute and character latches. Later in this
chapter, Table 6-2 describes the signals shown in Figure 6-16.

6-19

r - - - - -.... 7FF H
BANK 3
CHARACTER
(A8=1)
(A9=1 , A10=1)
-

- BANK 3
ATTRIBUTE
(A8=0)
(A9=1, A10=1)

700 H
6FF H

----BANK 2
CHARACTER
(A8=1)
(A9=O, A10=1)

600H
5FF H

BANK 2
ATTRIBUTE
(A8=0)
(A9=O, A10=1)
BANK 1
CHARACTER
(A8=1)
(A9=1, A10=0)

500 H
4FF H

400 H
3FF H

Figure 6-15

Line Buffer RAM
Memory Map

FROM

TO
CHAR
OUTPUT
FROM {SYNC DMA H
TIMING T5L
GEN
FROM
ACCESS VIDEO LATCH H

TO
LINE
BUFFER

MUX
LBF DISABLE H
FROM
CPU LOGIC

FROM
ATTRIBUTE ",-AD_O_H_-_A_D_7_H_ _.,
RAM

LATCH
1

TO
ATTRIBUTE
CIRCUITS
MA-0656-B4

Figure 6-16

Data Input Buffers Block Diagram
6-20

6.2.4.3
Character Output Circuit -- The character output circuit
generates the dot matrix character pattern used for the display.
The character output circuit
(Figure 6-17)
consists of the
following components.
•

Character latch 2
provides address of character
position
being accessed by character latch 1 (for
processing of the first scan line of a character address
being transferred to the line buffer RAM during DMA
transaction), line buffer RAM (during processing of
second and subsequent scan lines of a stored screen row),
or by the CPU logic (for read/write access of character
generators) .

•

Address mux -- provides address of scan line of character
being addressed by character latch 2 input, from either
the 9007· VPAC input
(during scan line processing), or
from the CPU logic
(during accessing the character
generators) .

•

Read/write buffer -- provides for data transfer between
the character generators
(ROM and RAM)
and the CPU
logic.

FROM
9007

SCO H-SC3 H

READ/
WRITE
BUFFER

ADDRESS
MUX
AD H-A3 H

TO/FROM
CPU
LOGIC

DIR

EN CHRGEN RW H
FROM
CPU
lOGIC

WRl

TO
VIDEO
CONVERTER

EN CHRGEN l

RDl
CHRG SEl H
FROM
ACCESS
MUX

ALT SEL H

FROM
(ADDRESS DATA)
LINE
BUFFER
FROM
TIMING
GEN

CHAR
LATCH

T5l
R73

NOTE:
WRITE LINES FROM READ/WRITE BUFFER ARE SAME LINES AS CHROH- CHR7H.
THEY ARE ILLUSTRATED SEPARATELY FOR CLARITY OF BUFFER FUNCTION.
MA-0657-84

Figure 6-17

Character Output Circuits Block Diagram

6-21

•

Alternate character generator RAM
contains "soft"
character set (down-line loadable characters), with font
storage of up to 94 characters (each character consisting
of 10 bytes of data, one byte for each scan line).

•

Character generator ROM -- contains "hard" character set.

Which character generator is selected for character data output
(CHR0 H-CHR7 H)
is determined by the AtT SEt H signal from the
access mux, with AtT SEt H developed either from CPU logic input
(during
CPU logic read/write access of alternate character
generator)
or from attribute circuits input developed from bit 5
of the attribute associated with the character to be processed.
Character latch 2 provides the base address for characters being
accessed from either of the two character generators, while the
address mux provides the scan line address.
The character ROM contains two identical pages of character format
data, with each page containing 256 rows of data, each data row 16
bits wide (which page is to be accessed is defined by CHARG SEt H
input) •
Figure 6-18 provides a general map of the character ROM. As shown
in this figure, 288 characters are packed into each page of 256
data rows: 256 characters, packed one per data row, and 32

DATA
DATA
DATA
BYTES
BYTES
BYTES
0-9
A+B
C-F
,....---A-.. ,,..._ _---'A'--_ _~....._'__.. ~
DATA
ROW
ADDRESS

SPACE (CRM 32)

l00X H/o()OX H
101X H/001X H

SPECIAL GRAPHICS

CRM
(0)

FILL
CHARACTERS

.....
"""'"
"".. ~

SPECIAL GRAPHICS
llFX H/01FX H
CRM
1 20X H/020X H REVERSE QUESTION (CRM 26) (7)
121X H/021 X H
ASCII

FILL
CHARACTERS

17EX H/07EX H
ASCII
CRM
17FX H/07FX H 1 - - -(1-27---16-0-)- - \ (25)
C-RM

FILL
CHARACTERS

- .....

CRM

FILL

(127-160)
CRM_
lAOX H/OAOX HI-_ _
_ _ _ _,(31)
- CHARACTERS
lAl x H/OAI X H

1 FDX H/OFDX H
1 FEX H/OFEX H
1 FFX H/OFFX H

DEC
SUPPLEMENTAL

.....
DEC
SUPPLEMENTAL
CRM (254)

FILL
CHARACTERS

CRM (255)
MA-06S8-84

Figure 6-18

Character ROM Map: Overview

6-22

characters (CRM0-CRM31) packed one character per each 5 data rows
(ROM space not taken up by character font data is filled with FFH
data) •
Figure 6-19 shows that each of the '256 characters packed one
character per data row consist of 10 bytes of data, one byte for
each scan line of the character. When addressing one of these
characters, a single base address is provided to the character ROM
by character latch 2, and each of the 10 scan lines is addressed
by the address mux input.
However, addressing the remaining 32 characters
(CRM0-CRM31)
requires a separate base address input from character latch 2 for
every two scan lines of the character to be processed. Figure 6-20
shows that each of the 32 characters packed into five different
data rows consist of 10 bytes of data, one byte for each scan
line, but only two bytes per data row.
Later in this
Figure 6-17.

chapter, Table 6-2 describes the signals shown in

SCAN LINE
ADDRESS

,
BASE
ADDRESS

SLl
X=O

I I I

1oox H/OOOX H
101X H/001X H
i-102X H/002X H
i-103X H/003X H
104X H/004X H

i--

rr-

110X H/Ol DX H
'-11 EX H/O 1 EX H
11 FX H/01FX H
120X H/020X H
121X H/021X H
122X H/022X H
123X H/023X H

170X H/07DX H 17EX H/07EX H 17FX H/07FX H
1 80X H/080X H
181X H/081X H

19EX H/09EX H
19FX H/09FX H
1AOX H/OAOX H
1Al x H/OA1 X H
1A2X H/OA2X H
1A3X H/OA3X H

1 FBX H/OFBX H
I1 FCX H/OFCX H
i-1 FOX H/OFDX H
1 FEX H/OFEX H
1 FFX H/OFFX H

Figure 6-19

SL2
X=1

SL3
X=2

SL41 SL5
X=3 X=4

SL61 SL71 SL81 SL9
X=5
X=6 X=7 X=8

tS~10
X-9

(CRM 32)
(SGC 96)
(SGC 97)
(SGC 98)
(SGC 99)

(SGC 124)
(SGC 125)
(SGC 126)
(CRM 26)
(CRM 33)
(CRM 34)
(CRM35)

(CRM 158)
(CRM 159)
(CRM 160)
(CRM 161)
(CRM 162)
(CRM 163)
(CRM 251)
(CRM 252)
(CRM 253)

0 EC
SPECIAL
GRAPHICS
CHARACTERS
(96-126)
REV, QUESTION
- ( ERROR

CHARACTER)

=}'
-

(CRM 125)
(CRM 126)
(CRM 127)
(CRM 128)
(CRM 129)

-~SPACE

SCII
CHARACTERS

-)=~
_

=
-

CRM
HARACTERS
27-160)

EC
UPPLEMENTAL
HARACTERS

Character ROM Map: CRM32-255 and
Special Graphics
6-23

ODD
SCAN LINE
ADDRESSES

EVEN
SCAN LINE
ADDRESSES

CRM
(0-31)

~....-----A----~
1aOA H/OOOA H

SLI

lOlA H/OOIA H

SL3

102A H/002A H

SL5

103A H/003A H

SL7

104A H/004A H

SL9

105A H/005A H
10M H/006A H
107A H/007A H
10BA H/OOBA H
109A H/009A H
10AA H/OOAA H

SL2

r--

100B H/OOOB H

101 B H/OOI B H
- 1-102B H/002B H
SL6
SL4

1-SLB
1--

SLIO

103B H/OO3B H
100B H/004B H

-.- .....

105B H/005B H
106B H/006B H
107B H/007B H
108B H/OOBB H
109B H/009B H
10AB H/OOAB H

CRM
(29)

193B H/093B H
194B H/094B H

CRM
(1)

193A H/093A H
1 94A H/094A H

195B H/095B H

195A H/095A H
196A H/096A H
197A H/097A H
1 98A H/098A H
1 99A H/099A H
j 9AA H/09AA H
19BA H/09BA H
19CA H/09CA H
19DA H/09DA H
I!lEA H/09EA H
19FA H/09FA H

196B H/096B H
197B H/097B H
198B H/098B H
199B H/099B H
19AB H/09AB H
19BB H/09BB H
19CB H/09CB H
19DB H/09DB H
19EB H/09EB H
19FB H/09FB H

CRM
(30)

CRM
(31)

MA·066Q-84

Figure 6-20

6.2.5

Character ROM Map: CRM0-31

Attribute Circuits

The attribute circuits output the attribute control values to be
considered in processing each character for display. As each scan
line of a character is output from the character generator,
attributes associated with that character, as loaded into the
attribute circuits by the line buffer RAM in the character
generator,
are output to video output and video converter
circuits.
The attribute
components.

circuits

(Figure

6-21)

consist of the following

•

Attribute latch 2 -- latches character generator input at
ATR/CHR going high to provide attribute value for the
next character to be processed to attribute latch 3 for
loading.

•

Attribute latch 3 -- loads attribute value from attribute
latch 2 on leading edge of T5 L (blink attribute input is
enabled or disabled by being gated with BLINK H input
from 2681 DUART).

6-24

FROM

BLINK H

DUART

FROM
CPU
NORM FIELD H
LOGIC

FROM

ATR
LATCH

BLINK ATR H

REV ATR H

ATR
LATCH

BOLD ATR H

}

TO
VIDEO
OUTPUT

REV/NORM
ULATR H

(ALT SEL)

CLK
CONVERTER

FROM
ATR/CHR
TIMING {
GEN
T5L
FROM

{

BLANK
CIRCUITS

FROM

9007

CHAR
GEN

(CLR)
CBLANK L

1~~::

...;...;,.--------'------+1
~S~C1~H~_ _ _ _ _~~

~~-

MA·0661-84

Figure 6-21

Attribute Circuits Block Diagram

•

CLR gate
clears value stored in attribute latch 3
whenever the screen is being blanked (CBLANK L) and
active line time (VLT H) is not occuring.

•

UL ATR gates -- gates underline attribute with scan line
address values input from the 9007 VPAC to define an
underline output only during the ninth and tenth scan
lines of the character being processed.

•

Attribute latch 4
is the output stage of attribute
circuits, clocked on leading edge of T5 L to latch inputs
provided by attribute latch 3 and UL ATR gates, with the
reverse attribute input from attribute latch 3 exclusive
ORed with NORM FIELD H control input from the CPU logic.

Later in this
Figure 6-21.

chapter, Table 6-2 describes the signals shown in

6-25

6.2.6

Video Converter

The video converter transforms parallel character dot matrix data
input from the character generator into serial data output to the
video output circuit. The video converter (Figure 6-22) consists
of the following circuits.
•
•

Conversion control
Parallel-to-serial (PIS) converter

6.2.6.1
Conversion Control
The conversion control circuit
controls loading of parallel character dot matrix data into the
PIS converter. The conversion control circuit (Figure 6-23)
consists of the following components.
•

INH latch
is latched at TS L time, with output
alternately enabling and disabling the INH gate.

•

Cursor skew F/F
is set by CURS H during horizontal
retrace time, when double width row is to be processed,
with high output partially enabling INH gate and set
input to INH F/F.

•

INH gate
is used during processing of double width
rows to jamset the load F/F, preventing load of a new
character until each bit of the current character is
processed twice.

•

INH F/F -- is used during processing of double width rows
to inhibit shift activity at the PIS converter so that
each bit of data input from the character generator
requires two dot clocks to process instead of one.

•

Load F/F -- defines a shift condition (CHR LO L high) or
load condition (CHR LO L low) to the piS converter.

Later in this
Figure 6-23.

chapter, Table 6-2 describes the signals shown in

6-26

FROM
Ul ATR H
ATTRIBUTE
CIRCUITS
FROM
CHAR
GEN

...

\ CHR1 H-CHR7 H )

{

;~~,.{

TO
VIDEO
OUTPUT

(SERIAL DATA)

CHRO H

CBLANK l

(ClR)
DOT ClK H

P-S
CONVERSION

S1
ClR CK C/llNH

~ 1

T5l
FROM
{
TIMING
GEN

T3H
T2l

~1
CONVERSION I - - CONTROL

FROM
9007

{

CURS H
CBLANK H

MA·0662-84

Figure 6-22

Video converter Block Diagram

INH
LATCH

T5l
, ...-.loL..---'CHR lD l

FROM {T3H
TIMING _T_2_l_ _ _

I-_+__+-_+1

GEN
DOT ClK H

-----~~~-r_-+----~

TO
P-5
CONVERTER

CURSOR
SKEW
FROM

CG BLANK H

BLANK-----~L-

FIF
____~

CIRCUITS
'SHARES SAME PHYSICAL COMPONENT
(LS174 lATCH) AS ATTRI3UTE lATCH 4 IN CHARACTER
GENERATOR, AND BLANK lATCH IN BLANK CIRCUITS.

T3H
T2l
MA-0663·84

Figure 6-23

Conversion Control Block Diagram

6-27

6.2.6.2
Parallel-to-Serial (PIS) Converter -- The PIS converter
performs the actual parallel-to-serial conversion of dot matrix
data, and in the process performs dot stretching. It converts
single "on" dots into two adjacent "on" dots (and, due to
construction of the dot stretching circuit, converts the last "on"
dot of a sequence into two dots as well) •
Dot stretching (Figure 6-24) occurs only on the horizontal plane,
and does not increase the number of dots in the vertical plane of
a character matrix.
It also does not increase the size of the
horizontal plane of a character matrix. Dot stretching simply
compensates for monitor risetime being too slow to reach maximum
brightness for single "on" dots. Figure 6-25 shows that stretching
each "on" bit increases the amount of time allowed for the monitor
to respond, allowing brightness to achieve its maximum.

SCAN
NUMBER

CHARACTER AS STORED IN
CHARACTER GENERATOR ROM

1········ . . . . . . . . . . . .
2· . . . • . . . . . . . . . . . . . . .
3· . . . . . . . . . . . . . . . . . . .
4· . • . . . • . . . . • . ••••. ..

5·.· ....•.. .••.. ..•..
6· ••••••• · . .••. . . . • . .

7·.· ....•...•. ••••. ..

8 ................... .
9· . . . . . . . . . . • . . . . . . . .

10· . . . . . . . . . . • . . . . . . . .

.-..------- -----.-.
.- --

ACTUAL CHARACTER DISPLAYED
AFTER DOT STRETCHING

. ...
. ..

............. .

............ .
.. ...
.... ..
...
..
...
....
..
....
.. ...... .
. .......... ...... .
. .......... ...... .

20 DOTS FOR 2 CHARACTERS
IN 80 COLUMN MODE
MA·4663A

Figure 6-24

Dot Matrix Display and Dot Stretching

-.LBRIGHTNESS LOSS

SIMPLE LOGIC ADDS ONE PULSE TO THE
TRAILING EDGE OF ANY INCOMING PULSE.
INPUT

INPUT
RESPONSE
PULSE
THE MONITOR RESET TIME IS TOO SLOW TO REACH MAXIMUM
BRIGHTNESS BEFORE THE SHORT PULSE FALLS.

OUTPUT

JTL

_SOn

BY STRETCHING ALL PULSES TO A MINIMUM
OF TWO DOT TIMES, FULL BRIGHTNESS IS ATTAINED.

Figure 6-25

MA-4665

Effects of Dot Stretching

6-28

The piS converter (Figure 6-26) circuit consists of the following
components.

•

Shift register -- loads parallel data on CHR LD L low,and
serially shifts d~ta through on each DOT CLK H input,
when INH input is low. It also outputs shifted data to
serial latch.

•

SIN latch
initiates serial shifting by loading bit 0
of the parallel dot matrix data into the serial input of
the piS converter.

•

Serial latch -- performs dot stretching by feeding back
the output developed from the shift register input to add
a high output to the gate at the trailing edge of each
high input (either for a single high input from the shift
register, or at the end of a series of high inputs).

The outputs from the serial latch are gated with the underline
attribute
(UL ATR H) to provide all high output to video output
circuit during processing of the ninth scan line of a data row
when underline attribute is selected.
Later in this
Figure 6-26.

chapter, Table 6-2 describes the signals shown in

FROM
Ul ATR H
ATTRIBUTE - - - - - - -_ _ _ _ _ _ _---,
CIRCUITS

(SERIAL
DATA)

FROM{
CHAR

TO
VIDEO
OUTPUT

CHR1 H-CHR7 H

GEN

CHRO H

FROM
TIMING
GEN

DOT ClK H

FROM
{(ClR)
BLANK
CBLANKl
CIRCUITS
---"-----+-I---tL...-./
CHR lD l
FROM
{
CONVERSION
(INH)
CONTROL
--------'
• SHARES SAME PHYSICAL COMPONENT (LS174 LATCH)
AS LATCH IN TIMING GENERATOR

Figure 6-26

P-S Conversion Block Diagram

6-29

MA-06604-84

Video Output

6.2.7

The video output circuit converts serial data input fTom the video
converter into video outputs to the monitor circuits and an
optional monitor device.
The video output circuit (Figure 6-27) consists of the following
components/circuits.
•

Data gate -- is an exclusive OR's serial input from video
converter with REV/NORM condition from attribute logic to
generate a high output (bit "on" condition) when REV/NORM
is low.

FROM
9007

liNPUr' -

I
I
I

CSYNC l
+5V----l.-.-~

STAGE

(REV/NORM)
FROM
{
ATTRIBUTE
CIRCUITS
FROM
BLANK
CIRCUITS

TO
DUART

+12 V

R14
C

'+ 55 13
R

BOLD H

TBlK l

IL-------...J

(SERIAL DATA)

i ~~~~

I
I

rvll5EO OUTPUTSTAGE""I

+12 V
RIB

=.-= -= _J

~---:'-'---i-----j

CONVERTER

OUTPUT STAGE

II
II
II

BLINK H

r-- - -

FROM
VIDEO

TVB H

.., r COMPOStr'EVIDEO -

TO MONITOR
CIRCUITS ON
PS AND MTR
BOARD

HOR SYNC l
FROM {
9007

SYNC

_---"VE:;,;.R'-T..:..SY.;.;.N.;.;;C...::l_1...B~U~F:..:FE:..:RS:.JI---------t

MA·0665-84

Figure 6-27

Video Output Block Diagram

6-30

•

Input stage
gates data gate value with blink, bold,
and
blank
attribute inputs to provide biasing to
composite video output and video output stages.

•

Composite video output stage
develops a composite
video output to be used by an optional monitor device
connected to J3 from input stage biasing and composite
sync (C SYNC L) inputs.

•

Video output stage
develops video output to monitor
circuits from input stage biasing inputs.

•

Sync buffers -- buffer sync outputs to monitor circuits.

•

Jl -- provides interconnection between logic board and PS
and monitor board.
NOTE
A complete pin-out for Jl is provided in
the
system
communication
logic
description
presented
in Chapter 5
(Figure 5-9).

Descriptions
6-2.
6.3

the signals shown in Figure 6-27 follow in Table

SIGNAL DESCRIPTIONS

Table 6-2 provides descriptions of all the signal identifed in
this chapter. These descrip~ions are provided for reference, and
are listed alphabetically by mnemonic, with numeric mnemonics
listed last.

6-31

Table 6-2

Video Logic Signal Descriptions

Mnemonic

Signal

Description

A0--A3 H

Address bits 0-3 high

Input to address mux in
character generator
from CPU logic defining
scan line of alternate
character generator RAM
to be accessed for read
(RD L) or write (WR L)
transaction

A0--A5 H

Address bits 0-5 high

Input to 9007 VPAC from
CPU logic defining
internal register to be
accessed (SEL CRT L)
for read or write
transaction (type of
transaction defined by
address)

A0--A13 H

Address bits 0-13 high

Address outputs from
9007 VPAC during DMA
transactions defining
CPU logic RAM and
attribute RAM addresses
to be accessed for read
of character and
attribute data

AD0--AD7 H

Address/data bits 0-7
high

Data bus lines used to
transfer attribute data
from attribute RAM to
character generator
during DMA transactions

ALT SEL H

Alternate select high

Select signal to
character generator ROM
(ALT SEL H low) and
alternate character
generator RAM (ALT SEL
H high) developed by
character generator
access mux from either
CPU logic input (when
CPU is accessing
alternate character
generator RAM), or from
input defined by
attribute of character
being processed for
output

6-32

Table 6-2

Video Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

ATR/CHR

Attribute/cqaracter

Timing generator output
controlling transfer of
attribute (ATR/CHR low)
and character address
values (ATR/CHR high)
into line buffer RAM
(during DMA
transactions) or out of
line Buffer RAM to
attribute latch 2 and
character latch 2
(during active line
time)

BAD0--BAD7 H

Buffered data bits 0-7
high

Data bus used by CPU
logic to transfer data
to and from 9007 VPAC,
or to and from the
alternate character
generator RAM, and by
video logic to transfer
character address data
from the CPU logic RAM
to the character
generator circuit

BLINK H

Blink high

DUART signal which
produces blink rate at
screen; BLINK H is
gated with blink
attribute (BLINK ATR H)
at attribute circuits
with BLINK H high for
blink off at screen and
low for blink on

BLINK ATR H

Blink attribute high

Enables blinking
display at screen
through biasing of
video output stage
circuit (int~nsity of
video output increased
for BLINK ATR H high
and decreased for BLINK
ATR H low)

6-33

Table 6-2

Video Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

BNKS0--BNKSl H

Bank select 0-1 high

DUART signals defining
the two most
significant bits of
line buffer RAM
address

BOLD H

Bold high

Enables bold display at
screen through biasing
of video output stage
circuit (intensity of
video output increased
for BOLD ATR 'H high and
decreased for BOLD ATR
H low)

CBLANK H

Composite blank high

CRT controller output
defining screen
blanking during
vertical and horizontal
retrace periods

CBLANK L

Composite blank low

Control defining screen
blanking developed from
either CBLANK H, during
retrace periods, or
from DIS VIDEO H,
during self-test

CGBLANK H

Composite gated blank
high

Gated from CBLANK Land
used as clock to cursor
skew F/F in video
output circuit to reset
double width control at
start of each
horizontal and vertical
retrace period

CHR0--CHR7 H

Character bits 0-7 high

Parallel dot matrix
data output from
character generator to
video converter
defining dot pattern of
display characters on a
scan line-to-scan-line
basis

6-34

Table 6-2

Video Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

CHR ADDR WR L

Character address write
low

Input to access mux in
character generator
used to develop VIDEO
LATCH H when CPU is
supplying address value
to character generator
to be used to access
alternate character
generator RAM for
read/write transaction

CHR LD L

Character load low

Input to pis converter
enabling load of
parallel character dot
matrix data (CHR0-CHR7
H)

CHRG SEL H

Character generator
select high

Input to character
generator ROM providing
MSB of address, with
bit defining which
character set is to
accessed during
character processing
for screen display
(ASCII or DEC
multinational)

(CLEAR)

(Clear)

Output from blank
circuit (developed from
CBLANK L) to clear
input of piS converter
and attribute latch 4
at start of each
retrace period

CRT CLK H

CRT clock high

Timing generator clock
output to CRT
controller generated at
T5 time

CSYNC L

Composite sync low

CRT controller output
to video output circuit
to be gated with video
data to define vertical
and horizontal sync for
composite video output
to optional slave
monitor

6-35

Table 6-2

Video Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

CURS H

Cursor high

CRT controller output
used during horizontal
retrace periods to
define a double width
data row to be
processed

DIS VIDEO H

Disable video high

DUART signal used to
generate blanking
signals during
self-test

DMA H

DMA high

Acknowledgement from
CPU relinquishing
control of AD0-7 Hand
BAD0-7 H data bus lines
to the CRT controller
for access of screen
character address and
attribute values

DMA REQ L

DMA request low

Interrupt to CPU from
CRT controller
requesting CPU give up
data buses for video
logic access of screen
character address and
attribute values

DOT CLK H

Dot clock high

Timing generator signal
providing basic timing
for video logic with
one active clock for
each dot of screen
display

EN CHR GEN

Enable character
generator read/write
high

CPU logic signal to
access mux character
generator selecting for
CPU logic inputs during
CPU access of character
genenerator

Enable character
generator low

CPU logic signal to
alternate character
generator RAM and
read/write buffer in
character generator
enabling CPU access for
read/write transactions

RW H

EN CHR GEN L

6-36

Table 6-2

Video Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

HOR SYNC L

Horizontal sync low

CRT controller output
defining horizontal
sync time

INH L

Inhibit low

Control within video
converter conversion
control circuit which
prevents serial
shifting of dot matrix
display data during
double width row
processing

LBA CLK L

Line buffer address
clock low

Clock input to line
buffer address counter
developed from either
LBA CLKS L (from CPU
logic) or T5 L (from
timing generator) by
character generator
access mux

LBA CLKS H

Line buffer address
clocks high

Clock input from CPU
logic to character
generator access mux
used to develop LBA CLK
L during CPU access of
character generator

LBA CLR L

Line buffer address
clear low

Clear input to line
buffer address counter
developed from either
LBA CLRS L (from CPU
logic) or VLT L (from
CRT controller) by
character generator
access mux

LBA CLRS H

Line buffer address
clears high

Clear input from CPU
logic to character
generator access mux
used to develop LBA CLR
L during CPU access of
character generator

6-37

Table 6-2

video Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

LBF DISABLE H

Line buffer disable
high

Control input to
character generator
enabling character
address values being
presented to character
generator to be passed
to alternate character
generator RAM without
being inadvertently
written to line buffer
RAM

LBF WR L

Line buffer write low

Timing generator output
enabling write of
character address and
attribute values into
line buffer RAM during
DMA transactions

NORM FIELD H

Normal field high

Control input from CPU
logic defining dark
screen background

RD L

Read low

CPU logic input to
character generator
read/write buffer
defining direction of
data transfer between
CPU and alternate
character generator RAM

RESET CRT L

Reset CRT controller
low

CPU logic signal
resetting CRT
controller to known
start state

RESET TIM L

Reset timing generator
low

CPU logic signal
resetting timing
generator to known
start state

REV ATTR H

Reverse attribute bit
high

Defines reverse display
at screen for character
being processed
(character dot matrix
"on" dots at same value
as screen background)

6-38

Table 6-2

Video Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

(REV/NORM)

(Reverse/normal)

NORM FIELD H and REV
ATTR H exclusive ORed
and gated with SERIAL
DATA L for display "on"
for "on" dots (REV/NORM
high) when NORM FIELD
H/REV ATTR Hare
opposing states
(reverse on light
screen or normal on
dark), or for display
"on" for "off" dots
(REV/NORM low) when
NORM FIELD H/REV ATTR H
are identical states
(reverse on dark screen
or normal on light)

SC0-SC3 H

Scan address bits 0-3
high

Address inputs to
character generator
address mux from CRT
controller defining
scan line of character
to be processed from
either character
generator ROM or
alternate character
generator RAM

SEL ATR0 L

Select attribute RAM 0
low

Enable to attribute
RAM 0 when CPU logic is
accessing the RAM for a
write, or when being
accessed for DMA
transaction

SEL ATRl L

Select attribute RAM 1
low

Enable to attribute
RAM 1 when CPU logic is
accessing the RAM for a
write, or when being
accessed for DMA
transaction

SEL CRT L

Select CRT controller
low

Enable to CRT
controller when CPU is
accessing this device
for read/write
transaction

6-39

Table 6-2

Video Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

(SERIAL
DATA L)

(Serial data stream low)

Bit stretched serial
dot matrix data output
from p/S converter to
video output defining
"on" and"off" bits of
display

SYNC DMA H

Synchronized DMA high

Timing generator output
developed from DMA H
synchronized to ATR/CHR
time

Tl-T5 H,T2 L
T3 L, T5 L

Timing signals 1-5 high,
2-3 and 5 low

Timing generator
clocking signals
outputs to video logic
circuits

TBLK L

Test blank low

Blank control to video
output circuit
developed from CBLANK L
(CBLANK L low for
either retrace periods,
from CBLANK H, or
during self-test, from
DIS VIDEO H), and
preventing video output
from turning display on

TVB H

Test video bits high

Status output to DUART
from video output
circuit used during
self-test to sample
condition of video data
stream

UL ATR H

Underline attribute
high

Enables generation of
underline at display by
being gated with SERIAL
DATA L to turn all dots
"on" during ninth and
tenth scan lines of a
processed character

VERT SYNC L

vertical sync low

CRT controller output
defining vertical sync
time

6-40

Table 6-2

Video Logic Signal Descriptions (Cont)

Mnemonic

Signal

Description

VIDEO LATCH H

Video latch Ihigh

Character generator
access mux output
enabling either CPU
access of alternate
character generator RAM
(VIDEO LATCH H
developed from CHR ADDR
L) or video logic
transfer of character
address and attribute
values to line buffer
RAM (VIDEO LATCH H
developed from T5 L)

VLT H/L

Visible line time
high low

Control outputs from
CRT controller defining
screen data processing
time (horizontal trace
periods)

WR L

write low

CPU logic input to
alternate character
generator RAM enabling
CPU access for write
transaction when that
device is selected (EN
CHRGEN L)

132 COL H

132 column high

Control input to timing
generator from DUART
defining number of
characters per screen
data row

6.4

SCHEMATIC REFERENCE INFORMATION

Table 6-3 identifies the logic board component coordinates and
schematic page and coordinate for each of the video logic
components and circuits identified in this chapter.
NOTE
The reference information provided in
Table 6-3 is based Rev. A of the logic
board schematics (CS 5415653-9-1).

6-41

Table 6-3

Video Logic Schematic References

Circuit/
Component

Board
Ref. No.'s

ACCESS MUX
ADDRESS BUFFER
ADDRESS MUX
ALT CHAR GEN RAM
ATR/CHAR GATE
ATTRIBUTE RAM
ATTRIBUTE LATCH 1
ATTRIBUTE LATCH 2
ATTRIBUTE LATCH 3
ATTRIBUTE LATCH 4
BLANK CIRCUITS
CHAR GEN ROM
CHAR LATCH 1
CHAR LATCH 2
CLR GATE
COMPOSITE VIDEO
OUTPUT STAGE
CRT 9007 VPAC
CRT CLK GATE
CURSOR SKEW F/F
DATA GATE
DOT CLOCK GENERATOR
INH F/F
INH GATE
INH LATCH
INPUT STAGE
JI
J3
LBF WR GATES
LINE BUF ADDRESS CO'UNTER
LINE BUFFER RAM
LOAD F/F
piS CONVERTER
READ/WRITE BUFFER
SERIAL LATCH
SIN LATCH
SYNC BUFFERS
SYNC DMA LATCH
Tl GATES
T5 H LATCH
T5 L LATCH
UL ATR GATES
VIDEO OUTPUT STAGE

E30
E8
E25
E12,E22,E24,R74
E46,R62
E5,E6
E21,E38
E29
E28,E38
E50,E46
E22,E39,E44,E50
E13,R73
E19,E22,E39
E20
E22
E49,C55,C56,L3,Q1,
R4,R12-R17
E16,E24,R57,R58
E34,R75,R6
E32,E38
E46
E24,E34,R60,Y3,Y4
E35,E37
E37
E50
E45,E49
J1
J3
E42
E7
E14
E35,E41
E27
E18
E36,E45
E36,E41
E44,E48,R9,R10
E29
E42
E43
E36,E44
E37,E44,E45
Q2,R18-R20,R23-R25

6-42

Schematic
Page Loc.
4
4
4
4

3
1
4
4
4
5
5
4
4
4

4
5

2
3
5
5
3
5
5
5
5
5
5
3
4
4
5

5
4

5
5
5
4

3
3
5
5
5

B3
06
04
D4/C3/B3
B4
C3-C2
B7
B6
B4
07/06
C8-C5
C3
C7/A4
C4
A4
03-01
B2-C2
B3
B8
04
B6-B4
A6/A7
B7
C6
D4-C4
C1-A1
C1
06
D7-C7
05
B7/B6
B5
02
B4-B3
B5/B4
B3
B6
C6
C4
B4
C8-C7
C3-C2

CHAPTER 7
KEYBOARD (LK201)

7.1

INTRODUCTION

The LK201 keyboard module (shaded area in Figure 7-1) is the
user's interface to the terminal. The keyboard detects keystrokes,
encodes them, and transmits and receives information to and from
the CPU logic in the system box.
Communication
between
the
keyboard and the CPU logic is
full-duplex, serial, and asynchronous at 4800 bits per second
(bps). The communication lines conform to EIA standard RS-423,
which applies to imbalanced voltage interfaces.
PSAND
MONITOR
BOARD
AC
INPUT

L..-"T"'""'"""

MONITOR
CIRCUITS

LOGIC
BOARD

'CONNECTOR PHYSICALLY rAOUNTED ON
PS AND MONITOR BOARD
MA-0613·B4B

Figure 7-1

VT220 Series Terminal
Functional Block Diagram
7-1

7.2

PHYSICAL DESCRIPTION

The VT240 Series terminal keyboard
arranged in the following four groups.
•
•
•
•

(Figure

Main keypad (57 keys)
Numeric keypad (18 keys)
Special function keypad (20 keys)
Editing keypad (10 keys)

Figure 7-2

LK201 Keyboard

7-2

7-2) has 105 keys

You can install the keycaps manually, but you need a special tool
to remove them.
The keyboard circuitry is contained in a low profile cabinet that
has a 30 mm nominal heig~t from table top to home row. The
keyboard case is made of two plastic shells that you can separate
with a screwdriver. Nonslip plastic strips along the bottom
prevent the keyboard from sliding on a table top. You can manually
insert two feet in holes to raise the back edge of the keyboard.
You can lift a plastic window along the top edge above the special
function keys to insert a user function label. The label, a thin
paper' strip, fits into the indented space and varies according to
the application program.
A coiled cable (PN BCC0l), with a 4-pin modular connector on each
end, connects the keyboard to the video monitor. The keyboard
transmits four signals to the monitor, which pass unchanged to the
system box via the video cable (Figure 7-3). The four signals are
as follows.
•
•
•
•

+12 V power to keyboard
Ground to keyboard
Serial out (transmit line from keyboard)
Serial in (receive line to keyboard)

You can place the cable in a channel in the bottom case and the
modular type telephone connector fits into jack J4. You can insert
the cable in the channel on either side of the keyboard. Section
7.6 provides keyboard specifications.

4WIRE
r-KEYBOARD
CABLE
\

I
KEYBOARD
CIRCUIT
BOARD

I
I
I
I
I

,-,
I

I
I
ISERIAL OUT
I
I SERIAL IN

MONITOR

I
I
I

I
I
I
I

+12V
GND

SYSTEM
BOX

1-------,
CENTRAL
PROCESSOR

I
I
I

-------'

PART OF
VIDEO
CABLE
MA-0270-82

Figure 7-3

Keyboard Cable Connections

7-3

FUNCTIONAL DESCRIPTION

7.3

This section
keyboard.

provides

functional

description

the LK201

Keyboard Operation Overview

7.3.1

Figure
7-4 is a simplified block diagram of the keyboard
circuitry. Everything except the block marked KEYBOARD SWITCH
MATRIX is on the printed circuit board. This block represents the
connections between the keyboard switches and the signals from the
8051 microprocessor.

BCD TO
DECIMAL
DECODER

P ,

, P

1 ,

, R
,T
, 2

(

) CONN.

KB DRIVE
0·17
KEYBOARD
MATRIX
18 X 8 LINES

CONN.
,...... KB
DATA
8

0·7

.......

,,
I

'--

KEYBOARD
LEDs
CONTROL
CIRCUIT

+5V LED
SUPPL Y

BEEPER

3
ON/OFF

BEEPER
CONTROL
CIRCUIT

JL ""'''YOU''
2 MS

y~EEP=BELL

T 2 KHz

P I

0 1

8051
MICROPROCESSOR

TIMING
NETWORKS

125 MS

TIMER
NO.1

TIMER
NO.2

·10V
SUPPLY

190 KHz

f-. 10V

,rJUMPERS FOR
HARDWARE ID

I P

IR
IT
I 3

+5V

POWER UP
RESET
SIGNAL
CIRCUIT

,
I
,,

-=
RECEIVE

RESET

TRANSMIT

""" '"
SERIAL OUT

DRIVER

L_
·10V

4KB ROM
128 BYTES RAM

RECEIVER

}

CO NFORMS
TO RS-423

f
+12V

+5V
SUPPLY

r- +5V

GND

'-'

J4
KEYBOARD
CABLE
CONNECTOR
MA-0272-82

Figure 7-4

LK201 Keyboard Block Diagram

7-4

The firmware in the 8051 8-bit microprocessor controls
following three major keyboard operations at the same time.
1.

Scans the
matrix

keyboard

detect·

Transmits results of the keyboard scan to the CPU

Receives information from the CPU

the

changes in the keyboard

7.3.1.1 Keyboard Scanning -- The keyboard switches are connected
at the intersections of an 18 X 8 line matrix. This provides a
fixed position identifier for each key.
The firmware scans the l8-line axis and detects a pressed or newly
released key by reading the 8-line axis. The firmware then
verifies
the
detected keystroke and changes this position
information into an 8-bit code that is unique to that key.
7.3.1.2 Control of Audio Transducer and Indicators -- Two circuits
control the audio transducer and the indicators. One circuit
receives its inputs from the 8051 and controls the transducer
(beeper). A long beep represents the bell and a short beep
represents the keyclick.
A separate circuit, controlled by a signal from the 8051, controls
each of the four indicators. The firmware, responding to commands
received from the CPU, turns the indicators on or off.

7.3.2

Keyboard Firmware Functions

This section describes the keyboard firmware functions. The
functions are divided into two categories: functions that cannot
be changed by CPU instructions and those that can.
Not
Changed by CPU Instructions
The
7.3.2.1 Functions
following functions cannot be changed by instructions from the
CPU.
Power-Up test
Keycodes
Special codes

7-5

Power-Up Test
Upon power-up, the firmware performs a self-test in less than 70
ms. The test results are transmitted to the CPU in four bytes.
The
keyboard indicators are lit during the self-test. The
indicators blink once during the self-test routine. The indicators
remain lit if the test is failed, but go off if the test is
passed. The system module can also request a self-test at any
time.
Keycodes
The keycodes represent fixed positions in the key switch matrix.
The key associated with a particular matrix position is always
represented by the same keycode.
Special Codes
There are 13 special codes transmitted by the keyboard. Four codes
transmit the results of the power-up self-test. The other nine
codes are status indicators or command acknowledgements.
7.3.2.2 Functions Changed by CPU Instructions -- The CPU can
issue
instructions
to
change
some
keyboard transmission
characteristics and control the keyboard indicators and beeper.
Upon completion of a successful power-up self-test, the firmware
sets certain functions to predetermined conditions. These are
referred to as default conditions. The conditions can be changed
but they always come up to the default condition after a
successful power-up self-test.
7.3.2.3 Firmware Functions Changed by CPU Instructions -- Certain
firmware functions can be changed by commands (instructions) from
the CPU. These commands are categorized as transmission commands
and peripheral commands. Transmission commands contain a mode set
command and an autorepeat rate set command. Peripheral commands
contain a variety of commands. Refer to section 7.5.5.3 for more
information on peripheral commands.

7-6

7.4

Detailed Keyboard Circuit Description

This section describes the keyboard circuit. Figure 7-4 shows the
keyboard block diagram.
7.4.1

Keyboard Matrix Scanning

The key locations are arranged in an 18 X 8 line matrix. Each key
switch is connected across a matrix intersection. This gives a
fixed position for each key connected in the matrix. This matrix
accommodates all 1~5 keys in the keyboard.
Figure 7-5 is a simplified block diagram of the matrix scanning
circuit. Eight lines from PORT 1 of the 8~5l microprocessor go to
the
binary
coded
decimal
(BCD)
inputs
of two 74LS145
BCD-to-decimal decoders. Ten outputs from one decoder and eight
outputs from the other decoder provide the drive lines for the
matrix. These 18 lines are called KB DRIVE ~ -- 17.
The other axis of the matrix consists of eight lines tied to +5 V
through pull-up resistors. These lines go to PORT ~ of the 8~5l
microprocessor and are called KB DATA ~ -- 7.

r - - - - - - - - - "__--.-+5V

2 TYPE
74LS145
DECODERS

80511lP

r--I PORT 1
I SCANS
I MATRIX

L ____

jP~TO I READS
KEY
l.:LOSURES

....

8 LINES .,

(8 BCD
INPUTS
AND18
DECIMAL
OUTPUTS)

....
18L1NES .,
K8 DRIVE 0-17

( .....

18 X 8 LI NE

- -MATRIX

8 LINES
KB DATA 0-7

TYPICAL SWITCH
CONNECTION AT
MATRIX
INTERSECTION
MA-0276-B2

Figure 7-5

Matrix Scanning Block Diagram

7-7

The 8051 scans the 18 drive lines. Key closures are detected by
reading the eight data lines. The complete matrix is scanned every
8.33 ms.
When a key closure is detected, it is scanned again to verify that
it is really a key closure and not just electrical noise.
Once the key closure is verified, the 8051 firmware translates the
position information into a key code and transmits it to the cpu.
Transmission is handled by the Universal Asynchronous Receiver
Transmitter (UART) in the 8051.
A ghost key indication can occur when three of the four corners of
a matrix rectangle are closed (Figure 7-6), causing what is known
as a sneak path. The key positions in the matrix are arranged to
avoid sneak paths. However, if a sneak path does occur, the
firmware prevents the keycode for the key that caused the sneak
path to be transmitted until one of the involved keys is released.
This prevents transmission of ghost keys entirely.
Table 7-1 shows the keyboard matrix on the LK201-AA (American)
keyboard. Keycap designations are listed for reference only; you
can compare them to Figure 7-7 (A and B) •

--~-+--~------r-~----3

DItIVE
LINES

--~-+--~------r-~----2

DATA
LINES
1. CONDITIONS ARE: SWITCHES B2, B3, AND C3 CLOSED,
SWITCH C2 OPEN; LINE 2 IS BEING DRIVEN AND LINE C
IS BEING READ.
2. INTERSECTION C2 IS BEING LOOKED AT. IT SHOULD NOT
SHOW A KEY CLOSURE BECAUSE SWITCH C2 IS OPEN.
3. HOWEVER A SNEAK PATH IS PRESENT FROM LINE 2
THROUGH SWITCHES B2, B3, AND C3 TO LINE C.
A GHOST KEY IS READ AT INTERSECTION C2.
MA-0273-B2

Figure 7-6

Example of Ghost Key Generation

7-8

Table 7-1

Keyboard Matrix

Refer to Figure 7
(A and B). It shows the international matrix for the LK201
keyboard. The legends are from the LK201 keyboard and are provided for convenience
only.
KB
Drive

KB DATA
7

Reserved

F19

Reserved

F20

PF4

N
(Note 1)

ENTER

G23

E23

023

C23

A23

D22

B17

C22

B22

A22

D2l

C2l

B18

B2l

N0
(See
Note 2

REMOVE

E18

C17

020

C20

B20

A20

PREV
SCREEN
017

{
[

Reserved Reserved

011

Cll

G22
16

-...J

F18

PF3

G2l

E22

F17

PF2

G20

E2l

PFI

NEXT
SCREEN
018

Reserved

I
1.0

E20
13

INSERT
HERE
E17

Ell

G16

NOTES
1. Note that N0 -- N9, N_, N"

refer to the numeric keypad.

2. N0 of the numeric keypad can be divided into two keys. Normally only the N0
keyswitch is implemented as a double-sized key.
3. The RETURN key also can be divided into two keys. The one that is decoded as
return is the RETURN (C13) key.

Table 7-1

Keyboard Matrix (Cont)

KB
Drive

KB DATA
7

FIND

HELP

SELECT

GIS

ADDTNL
OPTIONS
G14

X
(delete)
E13

Reserved

F12

Reserved

F11

}

RETURN

Reserved

C13

B16

C12

)

See
Note 3

C19

B19

019
(

G13

9
E99

099

C99

E98

098

C98

B98

EXIT

G99

7
E97

097

C97

B97

Reserved

GIl

lSI

Reserved

MAIN
SCREEN
G98

Reserved

CANCEL

Reserved

SETUP

G92

G93

Reserved

INTERRUPT
G95
$
4
E94

B99

6
E96

D96

C96

B96

5
E95

095

C95

B95

SPACE

094

C94

B94

A91-A99

RESUME
G96

G97

F13

012

-.....J

.....

016
9
E19

G12
9

]

E12

E16

Table 7-1

Keyboard Matrix (Cont)

KB
Drive

KB DATA
7

Reserved

PRINT
SCREEN
G99

Reserved

BREAK

G91

#
3
E93

093

C93

B93

Reserved

TAB

-.J
I
I-'
I-'

HOLD
SCREEN
G99

2
E92

Reserved

092

E09

1
E91

Reserved

CTRL

LOCK

COMPOSE

C99

A99

SHIFT
B99,B11

099

Reserved

C92

B92

B99

C91

B91

HoW---Pilirt-

Screen

Break

·s-at-up

Interrupt

Resume

Cancel

Mam
Screen

EXit

f11
(ESC)

F12
(8S)

-1='-'-3

Addit--

(LF)

Options

Hold Screen
_

Lock
_

ooooonooooonoooonBI
DD~~~~~~~~~~~~

-..J
I
I-'
N

D~~~~~~~D~~DDD~
uLJ~~~D~~~~DDDD

IShIft

1[J[][][][J~[]~DD[]ISh~

-,,-

Figure 7-7A

Compose Walt
_
_

F17

LK201-AA Keyboard Layout

F19

F20

Inoooo

088

uuuu
D~~D
~~~D

[][][]Dnto,

1
0

F18

BEJG0G
~

880GB

G0GG

BBGGBBBBBBBGB~

c:JGGGGGGGGEJGGGD
~ Gc::::JGGGBBEJG[:][:JBGG '"
L: IBc:JGGGGBc:Jc:JG[:JI I
I A~

AD1 toAOO

NOTE

811

THE GRAPHIC CHARACTERS ARE SHOWN FOR ILLUSTRATION PURPOSES ONLY

AND ARE NOT MEANT TO ASSIGN KEYCAP USAGE OR LEGENDS

Figure 7-7B

LK2~1-AA

Keyboard Layout

G16

- . _,

I BG0B

BGG
8GB
G
Gc:JG

GGGG
88GB
86GB
BGGn

A20

IBlj

7.4.2

Audio Transducer Control Circuit

Figure 7-8 shows the audio transducer or beeper control circuit.
The beeper is driven by a transistor whose base is connected to a
2 KHz square wave from a 556 timer IC. This signal is biased by a
network of four type 74LS05 open collector inverters. The 8051
microprocessor controls all four inverters via the firmware. The
on/off inverter connects directly to the transistor base. When the
8051 puts a high on the on/off inverter input, its output goes low
and removes the 2 KHz square wave from the transistor base. This
cuts off the transistor and disables the beeper.
To turn on the beeper, the 8051 puts a low on the on/off inverter
input.
Its output goes high and allows the 2 KHz signal to reach
the transistor base; this turns on the beeper. The firmware
generates a keyclick (on for 2 ms) or a bell tone (on for 125 ms) •
The 8051 sets up the three level control inverters by putting one
of eight binary combinations on the inverter inputs. All highs
give the softest sound and all lows give the loudest sound.
and
the bell tone
The
firmware
controls
the
keyclick
independently. The bell tone is sounded only upon request from the
system
control
processor. The keyclick is sounded
(unless
disabled) under the following conditions.

•
•
•
7.4.3

When a key is pressed
When a metronome code is sent
When a command to sound the keyclick is received from the
system control processor
Indicator (LED) Control Circuit

Figure 7-9 shows the LED indicator control circuit.
The control signal for each LED comes from PORT 2 of the 8051 to
the input of a type 74LS05 open collector inverter. The inverter
output goes to the LED cathode; its anode is connected to +5 V. A
separate +5 V source relieves the LEOs load on the main +5 V
supply.
A low signal from the 8051 drives the inverter output high, which
cuts off the LED. A high signal from the 8051 drives the inverter
output low. This provides a path to ground from the +5 V through
the LED. The LED then turns on.

7-14

.------.----+12V
BEEPER
74LS05
INVERTERS
ON/OFF CONTROL

8051
PORT 2

2KHz...JLJ

MA-0267-82

Figure 7-8

Beeper Control Circuit

74LS05
INVERTERS
1r--.---+ 12V

8051
PORT 2

L--..l...I*-+5V

HIGH

~wE1/

~___• _ _ _ _ _ _ +5V

- + HIGH SIGNAL FROM 8051 PROVIDES
PATH THROUGH LAST STAGE OF
OPEN COLLECTOR INVERTER TO TURN
ON LED.
MA-0268-82

Figure 7-9

Indicator (LED) Control Circuit

7-15

7.4.4

Keyboard Communication

This section describe the keyboard communication.
7.4.4.1 Keyboard Transmit Mode -- The keyboard codes and a few
other special codes are transmitted via a serial line output in
PORT 3 of the 8051. The transmitted signal goes from the 8051 to a
driver, through the keyboard cable, monitor, and video cable to
the CPU. A UART within the 8051 controls the transmission.
Transmitted
characters
conform to a specific format.
Each
character is 10 bits long. The first bit is the start bit. It is
always a logical zero (space). The next eight bits represent the
encoded data. The last bit is the stop bit. It is always a logical
one (mark). Figure 7-10 shows the character format.
7.4.4.2 Keyboard Receive Mode -- The firmware contains features
that can be enabled by commands from the CPU. There are two
categories
of
features:
one
sets
keyboard
transmission
characteristics and the other controls keyboard peripherals. A
peripheral command covers indicator control, bell and keyclick
loudness, keyboard 10 code, and reinstate keyboard. The commands
come from the CPU and pass through the video cable, monitor, and
keyboard cable to the receiver and into the 8051 via PORT 3. The
commands go to the UART in the 8051.
Received characters conform to the same l0-bit format used for
transmitted characters. The eight data bits are arranged in a
specified protocol, depending on the command type.

MARK

I.. 14
(T)LJr t __
I

SPACE (0)

CHARACTER
8 DATA BITS

T - T - T-T-T-T-T - r-T
I
I
I
I
I
I
I
I

.1.._.1._.L_.J._.l._.l._l._J

START
BIT

STOP
BIT
MA-0269-82

Figure 7-10

Keyboard Transmit and
Receive Character Format

7-16

7.4.5

Reset Signal for 8951 Microprocessor

Whenever the system is turned on, the 8951 microprocessor in the
keyboard must be reset. This allows the 8951 to start operating.
The reset signal generator is active only during powerup. The
input is +5 V. The output is connected to the RESET input of the
8951. When power is turned on, the +5 voltage starts to rise from
zero. The reset signal circuit output follows it and drops off
when a steady state of +5 V is reached. This circuit holds the
8951 RESET input high (+3.5 V to +5 V) long enough to enable the
reset action in the 8951. This action occurs only during powerup.
7.4.6

Hardware Keyboard Identification (10)

At powerup, the keyboard performs a self-test and sends the
results to the CPU. One piece of information to be sent is the
keyboard hardware 10, which is read from hardwired jumpers.
There are six jumpers. Each jumper line goes from an input in PORT
3 of the 8951 to ground. All jumpers are installed so the keyboard
hardware 10 is zero.
7.4.7
The
-19
V.

Voltage Supplies
only voltage sent to the keyboard is +12 V. However, +5 V and
V are also required. These voltages are derived from the +12

There is a +5 V supply that handles most of the requirements for
this voltage. The four keyboard LEOs have their own +5 V supply. A
-19 V supply provides voltage for the driver in the serial out
line.

7.5

KEYBOARD PROGRAMMING

This section describes the functions that the keyboard performs
under
system
central processor control. This section also
describes keyboard programming machine language, but does not
describe high level user programming.
7.5.1

Keyboard Layout and Key Identification

Each keyboard key has a unique location. Each location is scanned,
and when closure or release is detected, the location is verified.
This information is then decoded to an 8-bit keycode. Figure 7-7
shows the keyswitch locations. Table 7-2 shows the 14 functional
divisions of the keyboard. Table 7-3 shows the divisions, keycaps,
and keycodes.

7-17

Table 7-2

Keyboard Functional Divisions

Division

Description

Representation

48 graphic keys and spacebar

(3(3(31

Numeric keypad

Delete character (E12)

(3(311

Return (C13) Tab (D(3(3)

(31(3(3

Lock (C(3(3) Compose (A99)

(31(31

Shift (B99 and Bll) CTRL (C99)

(311(3

Horizontal cursors
(B16 and B18)

(3111

vertical cursors
(B17 and C17)

Six keys directly above
the cursor keys
(016 -- 018 and E16 -- E18)

1(3(31

1(3

Function keys (G99

G(33 )

1(31(3

Function keys (G(3S

G09)

1(311

Function keys (G1l

G14)

11(3(3

Function keys (GIS

G16)

11(31

Function keys (G2(3

G23)

111(3

7-18

Table 7-3

Keycode Translation Table

Division

Position

Keycap

Keycode
Decimal

Keycode
Hexadecimal

Hold screen
Print screen
Break
Setup
F5
Reserved

086
087
088
089
090
091--098

56
57
58
59
5A
5B--62

G05
G06
G07
G08
G09

Reserved
Interrupt
Resume
Cancel
Main screen
Exit
Reserved

099
100
101
102
103
104
105--110

63
64
65
66
67
68
69--6E

GIl
G12
G13
G14

Reserved
Reserved
F11 (ESC)
F12 (BS)
F13 (LF)
Additional
Options
Reserved

111
112
113
114
115
116

6F
70
71
72
73
74

117--122

75--7A

Reserved
Help
00

123
124
125

7B
7C
70

Reserved
F17
F18
F19
F20
Reserved

126--127
128
129
130
131
132--135

7E--7F
80
81
82
83
84--87

Reserved
Find
Insert here
Remove
Select
Previous screen
Next screen
Reserved

136--137
138
139
140
141
142
143
144

88--89
8A
8B
8C
80
8E
8F
90

Function Keys
10

G99
G00
G01
G02
G03

13
G15
G16
14
G20
G21
G22
G23
6 Basic Editing Keys

9
E16
E17
E18
016
017
018

7-19

Table 7-3

Keycode Translation Table (Cont)

Division

position

Keycap

A20

Reserved
0
Reserved

Keycode
Decimal

Keycode
Hexadecimal

PFI
PF2
PF3
PF4
Reserved

145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165

91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
A0
Al
A2
A3
A4
A5

Reserved
Left
Right

166
167
168

A6
A7
A8

Down
Up
Reserved

169
170
171--172

A9
AA
AB--AC

Reserved
Shift
CTRL

173
174
175

AD
AE
AF

Lock
Compose
Reserved

176
177
178

B0
Bl
B2

Keypad
2
A22
A23
B20
B21
B22
C20
C21
C22
C23
D20
021
022
023
E20
E21
E22
E23

Enter
1
2
3
4
5
6

7
8
9

Cursor Keys
7
B16
B18
8

B17
C17

Shift, Lock CTRL, A99, and A10
6
B99,Bll
C99
5

C00
A99

7-20

Table 7-3

Keycode Translation Table (Cont)

Division

position

Keycode
Decimal

Keycode
Hexadecimal

All ups
Metronome
Output error
Input error
KBO Locked
acknowledge
Test mode
acknowledge
Prefix to keys
down
Mode change
acknowledge
Reserved

179
180
181
182
183

B3
B4
B5
B6
B7

184

185

186

187

Delete (X)

188

Return
Tab

189
190

BO
BE

191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211

BF
00
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
00
01
02
03

Keycap

Special Codes

Delete
3

E13

Return and Tab
4

C13
000

48 Graphics Keys and Spacebar
1

E00
E01
001
C01
B01
E02
002
C02
B02
B00
E03
003
C03
B03
E04
004
C04
C04

Tilde
!l
Q

A
Z

Reserved
@2
W

S
X

Reserved
*3
E
0
C
Reserved
$4
R
F
V

7-21

Table 7-3

Keycode Translation Table (Cont)

Division

position

Keycap

A13l--A139

Space
Reserved

E135
D135
C135
B135

%5
T

G
B

Reserved
E136
D136
C136
B136

"'6
y
H
N

Reserved
&7

E137
D137
C137
B137

U
J
M

Reserved
C138
D138
C138
B138

*8
I
K

, ,

Reserved
(9
13

E139
D139
C139
B139

Reserved
) 13

El13
Dl13

Reserved

·· .,

Cl13
Bl13

? /
Reserved

+ =
} ]

E12
D12
C12

I \

Reserved
Ell
D11
C1l

·,

Reserved

Keycode
Decimal

Keycode
Hexadecimal

212
213
214
215
216
217
218
219
2213
221
222

D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE

223
224
225
226
227
228
229
2313
231
232
233
234
235
236
237
238
239
2413
241
242
243
244
245
246
247
248
249
2513
251
252-255

DF
E13
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F13
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC-FF

NOTE
The legends under "keycap" are taken from the keycap legends of
the LK213l-AA (American).
Keycodes
unused.

1313

through

64 are reserved. Keycodes 65 through 85 are

7-22

7.5.2

Modes

This section describes the function of the keycode transmission
modes. The mode set command allows anyone of the 14 keyboard
divisions to be set to anyone of the following three modes.
(Refer to section 7.5.7 for division defaults.)
•

Down only mode -- The keyboard transmits a keycode when
the key is pressed.

•

Autorepeat down -- The keyboard transmits a keycode when
the key is first pressed. If the key is held down past
the specified timeout period (usually 300 to 500 ms), a
fixed metronome code is sent at the specified rate until
the key is released.

•

Down/up
The keyboard transmits a keycode when the key
is pressed and an "up code" when the key is released. If
any other DOWN/UP keys are pressed, the "up code" is a
repeat of the "down code." If no other DOWN/UP keys are
pressed, the keyboard sends an ALL UPS code.

7.5.2.1 Special
autorepeat rate
autorepeat mode.

Considerations
Regarding Autorepeat
The
set command allows the following changes in the

•

Autorepeat rate buffer association can be changed for the
selected keyboard division.

•

The timeout and interval values can be changed in anyone
of the four autorepeat rate buffers.

•

If multiple autorepeating keys are held down, metronome
codes are still generated. The metronome codes apply to
the keycode transmitted most recently. If the last key
pressed is released, and any other keys are still down,
the keycodes for those keys are retransmitted.

Example 1
The a key is held down. This produces the following transmission.
a metronome metronome
Now the b key is pressed. This produces the following
transmission.
a metronome metronome b metronome metronome
Now the b key is released. This produces the following
transmission.
a metronome metronome b metronome metronome a metronome
met • • •
7-23

While metronome codes are being generated for an autorepeating
key,
a
nonautorepeating
keycode
or special code may be
transmitted. The keyboard transmits this special code instead of
the next metronome code, and then returns to the autorepeated
code. The keycode to be autorepeated is always the last byte
transmitted.
Example 2
The a key is held down. This produces the following transmission.
a metronome metronome
Now the SHIFT key is pressed. This produces the following
transmission.
a metronome metronome shift a metronome
Now the SHIFT key is released. This produces the following
transmission.
a metronome metronome shift a metronome ALL UPS a
metronome. • •
•

If an autorepeating key is not to autorepeat (CTRL C for
example), the system module must issue a temporary
inhibit autorepeat command. This halts the transmission
of any metronome codes or keyclicks for that key only.
Metronome codes continue when another key is pressed. The
command
must be issued after the keycode for the
autorepeating key is received.

•

Autorepeat can be enabled and disabled independently of
the
division
settings by using the enable/disable
autorepeat commands. These commands apply to all keys on
the keyboard. When autorepeat is disabled, internally the
keyboard continues to autorepeat characters. However, it
does not transmit metronome codes or keyclicks. When
autorepeat
is
enabled, the keyboard transmits the
metronome
codes
from
the point they were before
autorepeat was disabled. This may be within either the
timeout or interval period, depending upon the time
elapsed since the key was pressed.

•

If the keyboard receives a request to change a division
mode to autorepeat while a key is pressed, the keyboard
makes the change immediately. After the specified timeout
period, the keyboard transmits metronome codes for the
pressed key. In place of the first metronome code, the
keyboard transmits the keycode of the autorepeating key.

All autorepeating division modes can be changed to only down with
one command. This and other autorepeat commands are grouped with
the peripheral commands (refer to section 6.5.5.3).
7-24

7.5.2.2 Special Considerations Regarding Down/Up Mode -- If two
DOWN/UP keys are released simultaneously (within the same scan),
and there are no other DOWN/UP keys down on the keyboard, only one
ALL UPS code is generated.
7.5.2.3 Autorepeat Rates
There are four buffers in the
keyboard to store autorepeat rates. They are numbered zero through
three. Each buffer stores the following two values. These values
can be changed by the system module.
The timeout value
The interval value
The timeout value is the amount of time between the detection of a
down key and the transmission of the first metronome code
(defaults range from 300 to 500 ms). The interval value is the
number of metronome codes per second (defaults to 30).
Each division is associated with one of the four buffers. Rates
are taken from the associated buffer each time the autorepeat
timers are loaded. This buffer-to-division association can be
changed by the system module, or left to default.
7.5.3

Keyboard Peripherals

This section describes the peripherals available on the keyboard.
The
keyclick,
bell, and LEOs are all considered keyboard
peripherals. Refer to section 7.5.5.3 for information on system
module control over these peripherals.
7.5.3.1 Audio
The keyclick is a 2 ms beep and the bell is a
125 ms beep. The bell is sounded only upon request from the system
module. The keyclick (if not disabled by the system module) sounds
when a key is pressed, when a metronome code is sent, or when the
system module receives a sound keyclick command.
If either the B11 or B99 keys (the left and right SHIFT keys on
the LK20l) or the C99 key (the CTRL key on the LK20l) are pressed,
the keyclick is not generated. However, if a command is sent from
the system module to enable the keyclick on the C99 key, the
keyclick is generated (refer to section 7.5.5.3). Figure 7-7 shows
the positions of these keys.
The keyclick or bell (or both) may be disabled. When the keyclick
or bell is disabled,
it does not sound. If the system module
requests sound (refer to section 7.5.5.3) the keyclick or the bell
does not sound.

7-25

Both the keyclick and bell may be independently set to one of the
following eight volume levels.
999
highest
991
919
default
911
199
191
119
111 -- lowest
7.5.3.2 Indicators (LEOs) -- The system module normally transmits
indicator control commands. However the following are exceptions.

•

Upon powerup, the keyboard turns all LEOs off.

•

After receiving the inhibit transmission command, the
keyboard turns on the keyboard-locked LED. The LED is
turned
off
after
the keyboard receives a resume
transmission command.

7.5.4

Keyboard-to-System Module Protocol

This section describes the keyboard-to-system module protocol.
7.5.4.1 Keycode Transmission
The keyboard transmits single
byte keycodes that reflect the keyboard matrix status. The
eight-bit codes above 6419 are used for keycodes. Every key is
identified by a unique keycode. There are no special codes for
shifted or control keys.
Refer to Figure 7-7 and Tables 7-1 and 7-2 for complete keycode
matrix translation table information.
7.5.4.2 Special Code Transmission -- There are 13 special codes.
Nine codes have values above 6419 and four codes have values
below.
The following
value range).

nine special codes have values above 6419 (keycode

•

ALL UPS

•

METRONOME CODE

•

OUTPUT ERROR

Keycode 179 (decimal),
B3 (hexadecimal)
Keycode 180 (decimal),
B4 (hexadecimal)
keycode 181 (decimal),
BS (hexadecimal)

7-26

•
•
•
•
•
•

INPUT ERROR

Keycode 182 (decimal) ,
B6 (hexadec imal)
Keycode 183 (decimal) ,
B7 (hexadec imal)
Keycode 184 (decimal) ,
B8 (hexadec imal)
Keycode 185 (decimal) ,
B9 (hexadecimal)
Keycode 186 (decimal) ,
BA (hexadec imal)
Keycode 127 (decimal) ,
7F (hexadecimal)

KBD LOCKED ACK
TEST MODE ACK
PREFIX TO KEYS DOWN
MODE CHANGE ACK
RESERVED

ALL UPS -- indicates to the system module that a DOWN/UP MODE key
was just released and no other DOWN/UP keys are pressed.
METRONOME CODE -- indicates to the system module that an interval
has passed, a keyclick has been generated, and the last key
received by the system module is still pressed.
OUTPUT ERROR -- indicates an output buffer overflow to the system
module. The overflow occurred after receiving a keyboard inhibit
command from the system module, and some keystrokes may be lost.
INPUT ERROR CODE
indicates to the system module that the
keyboard received a meaningless command, too many parameters, or
too few parameters.
KEYBOARD LOCKED CONFIRMATION
indicates to the system module
that the keyboard received an inhibit transmission command (refer
to section 7.5.5.3).
TEST MODE ACKNOWLEDGE -- indicates that the keyboard has entered
test mode. This is a special mode used during the production test.
If the system module receives this acknowledgement, it sends 80
hexidecimal. This terminates the test mode and jumps to power-up.
PREFIX TO KEYS DOWN -- indicates that the next byte is a keycode
for a key already down in a division which has been changed to
down/up (refer to section 7.5.5.4).
MODE CHANGE ACKNOWLEDGE
received and processed a
7.5.5.4) •
RESERVED
use.

indicates

that

indicates that the keyboard has
mode change command (refer to section
keycode 7F is reserved for internal

7-27

•

KEYBOARD ID (firmware)

•

KEYBOARD ID (hardware)

•

KEY DOWN ON POWER-UP ERROR CODE

•

POWER-UP SELF-TEST ERROR CODE

Keycode 01 (decimal),
01 (hexadec imal)
Keycode 00 (decimal) ,
00 (hexadecimal)
Keycode 61 (decimal),
3D (hexadec imal)
Keycode 62 (decimal) ,
3E (hexadec imal)

KEYBOARD ID
is a two byte identification code, transmitted
after the power-up self-test
(refer to section 7.5.4.3). It is
also sent on request from the system module (refer to section
7.5.5.3).
KEY DOWN ON POWER-UP
pressed on power-up.

ERROR

CODE

indicates that a key was

POWER-UP SELF-TEST ERROR CODE -- indicates to the system module
that the ROM or RAM self-test of the system module failed (refer
to section 7.5.4.3).
7.5.4.3 Power-Up Transmission
Upon power-up, the keyboard
performs a self-test in less than 70 ms, then transmits the
self-test results to the system module in 4 bytes.
Byte 1

(firmware)
This is the keyboard
KBID
identification (ID) stored in the firmware.

Byte 2

KBID (hardware)
This is the keyboard ID
read from hardware jumpers.

Byte 3

ERROR
Two error codes indicate either the
failure of the ROM or RAM self-test within the
processor
( 3E hexadecimal) , or a keydown on
powerup
( 3D
error is
hexadecimal) •
No
indicated by 00.

Byte 4

KEYCODE
This byte contains the first
keycode detected if there was a key pressed on
power-up. No error is indicated by 00.

If the ROM self-test (CHECKSUM) fails and the error is critical,
the keyboard is unable to transmit. Noncritical errors let the
keyboard continue operating.

7-28

If the keyboard finds a key pressed on the first scan, it
continues to look for an ALL UPS condition. The keyboard sends the
corrected four-byte power-up sequence when the pressed key is
released. This avoids a fatal error condition if a key is pressed
by mistake while powering up.
The keyboard LEOs are lit during the power-up self-test. If the
self-test passes, the keyboard turns the LEOs off. If a bell is
selected on powerup, the system module can transmit a sound bell
command to the keyboard. However, this should not be done until
the system module receives the last byte of the four-byte
sequence. The request for self-test tests the serial line and
system module connection. The power-up self-test takes 70 ms or
less.
The system module can request a jump to powerup at any time. This
causes the LEOs on the keyboard to blink on and off (for the
power-up self-test).
7.5.5

System Module to Keyboard Protocol

The system module controls both the peripherals associated with
the keyboard and the keyboard transmit characteristics. Figure
7-11 shows the protocol for command and parameter transmission
from the system module to the keyboard.

COMMAND
07

REPRESENTATION

PARAMETERS
DATA

I I

DATA
MA-0178-82

Figure 7-11

System Module
to Keyboard Protocol

7-29

7.5.5.1 Commands
There are two kinds of commands, commands
that control keyboard transmission characteristics and commands
that control keyboard peripherals. The low bit of the command is
the TYPE flag. The TYPE flag is clear if the command is a
transmission command, and set if the command is a peripheral
command.
Transmission Commands

Peripheral Commands

Mode set

Flow control

Autorepeat rate set

Indicator
Audio
Keyboard 10
Reinitiate keyboard
Some autorepeat control
Jump to test mode
Reinstate defaults

The high order bit of every command is the PARAMS flag. If there
are any parameters to follow, the PARAMS flag is clear. If there
are no parameters to follow, the PARAMS flag is set.
7.5.5.2 Parameters
The high order bit of every parameter is
the PARAMS flag. This flag is clear if there are parameters to
follow, and set on the last parameter. The remaining seven bits of
the parameter are for data.
7.5.5.3 Peripheral Commands
The following two commands can
turn the data flow from the keyboard off and on.
•

Inhibit keyboard transmission -- shuts off or locks the
keyboard and turns on the keyboard locked LED. After
receiving the inhibit command, the keyboard sends a
special command to the system central processor. If the
system central processor receives this code without
requesting it, this indicates that noise on the line was
interpreted as the inhibit command. The central processor
then
responds immediately with the resume keyboard
transmission command.

•

Resume keyboard transmission -- turns on or unlocks the
keyboard and turns off the keyboard locked LED. If any
keystrokes are lost, the keyboard responds with an error
code.

Each keyboard LED can be turned on and off.

7-30

The following eight commands control the keyclick and bell sounds.

•
••
•
•
••
•

Disable keyclick
Enable keyclick and set volume
Disable CTRL keyclick
Enable CTRL keyclick
Sound keyclick
Disable bell
Enable bell and set volume
Sound bell

The following four
autorepeat mode.

commands

are

control over the

•

Temporary autorepeat inhibit -- stops autorepeat for a
specific key only. It resumes automatically when anoth~r
key is pressed.

•

Enable autorepeat across the board -- starts transmission
of metronome codes without affecting autorepeat timing or
keyboard division.

•

Disable autorepeat across the board -- stops transmission
of metronome codes without affecting autorepeat timing or
keyboard division.

•

Change all autorepeat to down only
changes
keyboard autorepeating divisions to down only mode.

all

The following are three other miscellaneous commands.
•

Request keyboard ID -- causes the keyboard to send the
two byte ID
(firmware and hardware). The keyboard does
not jump to the power-up sequence.

•

Reinitiate keyboard -- causes the keyboard to jump to the
power-up sequence. Transmission to the keyboard should be
held until the host processor receives the last byte of
the power-up self-test.

•

Reinstate defaults
sets the following funct~ons back
to the default settings after a successful power-up
self-test.
Division mode settings
Autorepeat interval and timeout rates
Autorepeat buffer selections
Audio volume
Control key keyclick

7-31

To send a peripheral command, set the TYPE flag (low order bit).
Bits six -- three contain a command representation from the chart
below. Bits two and one specify on (@l), off (@@), or sound (11).
Bit seven should be set if there are no parameters to follow.
Table 7-4 lists the peripheral commands (in hexadecimal).
Table 7-4

peripheral Commands in Hexadecimal

Function

Hex

Parameters

8B
89

None
None

13
11

Bit pattern
Bit pattern

99
lB
B9
BB
9F
Al
23
A7

None
Volume
None
None
None
None
Volume
None

Cl
E3
EI
09

None
None
None
None

AB
FD
CB
03

None
None
None
None

Flow control
Resume keyboard transmission
Inhibit keyboard transmission
Indicators
Light LEOs
Turn off LEOs
Audio
Disable keyclick
Enable click, set volume
Disable CTRL keyclick
Enable CTRL keyclick
Sound keyc1ick
Disable bell
Enable bell, set volume
Sound bell
Autorepeat
Temporary autorepeat inhibit
Enable autorepeat across keyboard
Disable autorepeat across keyboard
Change all autorepeat to down only
Other
Request keyboard 10
Jump to powerup
Jump to test mode
Reinstate defaults

7-32

Command

Representation

Flow control
Indicator (LEOs)
Keyclick
Bell
Keyboard IO
Keyclick for CTRL key
Temporarily inhibit autorepeat
Jump to test mode
Change all autorepeat characters to down only
Enable/disable autorepeat

9991
9919
9911
9199
9191
9111
1999
1991
1919
1199

The jump to power-up command is FO hexadecimal.
The following are some of the peripheral commands.
•

Flow control -- The system module can lock the keyboard
with the inhibit keyboard transmission command. When the
keyboard is unlocked, it responds with an error code if
any keystrokes were missed (refer to section 7.5.6.2).

•

Indicators (LEOs) -- Figure 7-12 shows the LED parameter.
Figure 7-13 shows the LED layout on the LK291 keyboard.

•

Audio -- Figure 7-14 shows the audio volume parameter.

MA-0179·82

Figure 7-12

Indicator (LED) Parameter

LED 4

LED 3

LED 2

LED 1
MA-0176-82

Figure 7-13

Indicator (LED) Layout

I I I I
0

3-B:IT

VO~UME
MA-0177-S2

Figure 7-14

Audio Volume Parameter

7-33

The audio has the following volume levels.
000 -- highest
001
010
011
100
101
110
111 -- lowest
Either keyclick or bell
(or both)
can be disabled. When the
keyc1ick or bell is disabled,
it does not sound, even if the
system module requests it.
The following are additional peripheral commands.
•

Temporary autorepeat inhibit -- stops autorepeat for this
key only. Autorepeat automatically continues when another
key is pressed.

•

Disable/enable autorepeat across keyboard -- stops/starts
metronome code transmission without affecting autorepeat
timing or division settings.

•

Change all autorepeat to down only -- changes division
settings for all autorepeating divisions to down only.

•

Request keyboard ID -- causes keyboard to send a two-byte
keyboard ID. Keyboard does not jump to powerup.

•

Reinitiate keyboard
causes keyboard to jump to its
powerup routine. The system module should not try to
transmit anything to the keyboard until the last byte of
the power-up sequence is received.

•

Jump to test mode
production test.

•

Reinstate defaults -- sets the following functions back
to the default settings after a successful power-up
self-test.

special

Division mode settings
Autorepeat interval and timeout rates
Autorepeat buffer selections
Audio volume
Control key keyc1ick

7-34

test

mode

for

7.5.5.4 Mode Set Commands -- This section describes the mode set
commands. It does not provide information about division mode
settings.
Refer
to
section
7.5.2 for an explanation of
transmission modes and rates.

•

Each
division on the keyboard has a unique 4-bit
representation
(refer to section 7.5.1). Table 7-2
describes these representations.

•

Each mode has a unique two-bit code •

Modes

Representation

Down only
Autorepeat down
Down/up

To set the key transmission mode on a particular keyboard
division, the system module must send the PARAMS flag, then the
keyboard division representation with the mode code, and then the
TYPE flag (cleared).
Figure 7-15 shows a set main array to down/up.
The PARAMS flag is set to one if there are no parameters. The
PARAMS flag is clear if there are parameters.
Autorepeat Rate Buffer Association
If autorepeat mode is
selected, the system module can transmit a parameter to change the
buffer association of the selected division. Refer to section
7.5.2.3 for autorepeat rates and section 7.5.7 for default
values.
Figure 7-16 shows a set main array to autorepeat, changing buffer
association to buffer 3.

II I
1

PARAM

0
T

DIVISION

I :
1

TYPE
MA-Q18o-a2

Figure 7-15

DIVISION

MODE

TYPE

11 0

''---y--J
MODI;:

PARAM

Set Main Array
to Down/Up
Example

Figure 7-16

7-35

00
0
1

Set Main Array
to Autorepeat
Example

Autorepeat Rate Buffer Values -- At keyboard power-up time, the
four autorepeat rate buffers contain default values (refer to
section 7.5.2.3 for autorepeat rates and section 7.5.7 for
defaults). The system module may change these values.
In the command byte, bit seven (PARAMS flag) should be clear, bits
six
three are 1111 (to indicate that this is a rate set
command), bits two and one should be the buffer number (0 -- 3),
and bit zero (TYPE flag) is clear.
There should be two parameters carrying the rate set data.
Figure 7-17 shows change rates in buffer 3.
The first parameter specifies the timeout to the store in the
selected buffer. The second parameter specifies the interval.
(Refer to section 7.5.2.1 for definitions of these parameters.)
For example, to set the autorepeat rate in buffer one, the system
module firmware transmits 00000011 followed by two bytes of
numeric parameters.
The autorepeat timeout is the transmitted number times 5 ms. To
specify a rate of 5 ms delay, the first parameter received is
00000001. The maximum allowable time is 630 ms (01111110). The
system module must not send 635 (01111111).
NOTE
This code (635) is reserved for internal
keyboard use. 00 is an illegal value.
Autorepeat timeout is implemented as a multiple of 8.33 ms (the
keyboard's internal scan rate). Timeout rates can vary + 4.15 ms.
The autorepeat interval is the number of metronome codes per
second. in order to specify a speed of 16 Hz, the second parameter
received is 10010000. Note that the high order bit is set because
it is the last parameter. The highest value which may be sent is
124 (11111100).

RATE CHANGE
PARAM
COMMAND
BUFFER NO. TYPE
r-"'---.r,-----""~---..v--/O--_y__A__..

07
0

I I
1

04
1

111

I I

PARAMETER 1 (TIMEOUT)

PARAMETER 2 (INTERVAL)
MA-0182-82

Figure 7-17

Change Rates in
Buffer 3 Example

7-36

The lowest rate which can be implemented by the keyboard is 12 Hz.
Values as low as 1 can be transmitted, but are translated to 12
Hz.
The system
(11111101) •
command.
7.5.6

NOTE
module must not send 125
This code is the power-up

Special Considerations

This
section
considerations.

describes

the

special

codes

and

7.5.6.1 Error Handling -- There are four error codes. The first
two are sent at power-up if the self-test fails (refer to section
7.5.4.3). The other two codes are the INPUT ERROR code and the
OUTPUT ERROR code.
The OUTPUT ERROR (B5 hexadecimal)
is sent after the keyboard
receives a resume transmission command if the output buffer
overflowed while the keyboard was locked.
The INPUT ERROR (B6 hexidecimal) is sent when the keyboard detects
noise
(unidentified command or parameter) on the line. B6 is also
sent if the keyboard detects a delay of more than 100 ms when it
expects a parameter.
7.5.6.2 Keyboard Locked Condition -- When the keyboard receives
an inhibit transmission command, it lights the LOCKED LED and
transmits one more byte. This is a special code that indicates the
keyboard is locked
(KEYBOARD LOCKED ACKNOWLEDGE). If the system
module receives this code without a request, the code indicates
that noise on the line was interpreted as an inhibit transmission
command. The system module should immediately send the resume
transmission command to unlock the keyboard.
The output first in the first out (FIFO) buffer in RAM is four
bytes. When the keyboard is locked it attempts to store characters
received from the keyboard. The keyboard stops scanning its
matrix. When the keyboard is unlocked by the system module, it
transmits all four bytes in the output buffer. If any keystrokes
have been missed due to buffer overflow, the keyboard transmits an
error code as the fifth byte (OUTPUT ERROR). Any keys that were
not transmitted and are being pressed when the keyboard is
unlocked are processed as new keys. An error code upon unlocking
the keyboard indicates a possible loss of keystrokes to the system
module.
The keyboard stops scanning its matrix when its buffer is full.
However, it processes all incoming commands.
7-37

7.5.6.3 Reserved Code -- The number 7F (hexidecimal) is reserved
for the internal keyboard input and output buffers that handle
routines.
7.5.6.4 Test Mode
The keyboard jumps into a test mode by
command during production test. The keyboard transmits a special
code to the system module to confirm the test mode. If the system
module
receives
this
code,
it should send the byte 80
(hexidecimal) to continue. This causes a jump to power up.
7.5.6.5
use as
codes.

Future Expansion -- Some keycodes are reserved for future
special codes or keycodes. Table 7-5 lists these reserved

7.5.7

Default Conditions

The LK201 has the following default conditions.
o

Certain keyboard divisions have specific default modes.
Some divisions default to the autorepeat mode. Therefore,
they have an associated buffer that contains the default
values for timeout and interval. Timeout is the amount of
time
that
the
keyboard waits before starting to
autorepeat a character. The rate of autorepeating a
character is called the interval. Table 7-5 shows the
default modes and Table 7-6 shows the default rates in
the f~ur keyboard division autorepeat rate buffers.

The volume levels for the keyclick and bell have an
eight-step range. The default volume levels for the
keyclick and bell are the third loudest.

For the LK201 keyboard, the CTRL (control) key defaults
to the no keyclick state.

7.5.7.1 Audio Volume
Both keyclick and bell volumes are two
decimals
(010 binary) by default. The key in position e99 of the
keyboard
(the CTRL key in the LK201) does not generate a click
unless enabled by the system module. The keys in position B99 and
Bll (SHIFT keys on the LK201) never generate a keyclick.

7-38

Keyboard Division Default Modes

Table 7-5

Keyboard Division

Mode

AR Buffer

Main array
Keypad
Delete
Cursor keys
Return and tab
Lock and compose
Shift and control
Six basic editing keys

Autorepeat
Autorepeat
Autorepeat
Autorepeat
Down only
Down only
Down/up
Down/up

""1

Table 7-6

Default Rates in Autorepeat Buffers

Buffer
Number

Timeout
(ms)

Internal

5""
3""
5(3"
3""

3(3
3"
4"
4"

7.6

(Hz)

SPECIFICATIONS

Functional
Electronics

8-bit microprocessor, 4 KB of ROM, 256
bytes of RAM, 4 LEOs, transducer

Cord

1.9 m (6 ft) coiled, 4-pin
telephone-type modular connectors,
plugs into display monitor (PN BCC"l)

Keypad

Sculptured key array

Home row key height

3(3 mm (1.16 in) above desk top

Keys

1(35 matte textured finish keys

Main keypad

57 keys

7-39

Numeric keypad

18 keys

Special function keypad

20 keys, firmware and software driven

Editing keypad

10 keys

Spacing

1.9 cm (0.75 in) center to center
(single width keys)

Wobble

Less than 0.5 cm (0.020 in)

Diagnostics

Power-up self-test, generates
identification upon passing test

Physical
Height
Length
Width
Weight

5 cm
53.3
17.1
2 kg

(2.0 in) at highest point
cm (21 in)
cm (6.75 in)
(4.5 1b)

7-40

CHAPTER 8
MONITOR CIRCUITS

8.1

GENERAL

The monitor circuits and CRT (shaded areas of Figure 8-1), along
with the yoke assembly, are responsible for actual display to the
VT220 operator. The monitor circuits, located on the PS and
monitor board, develop the drive potentials for both the CRT and
the yoke assembly. The CRT generates an electron beam to provide
actual visual output; the yoke assembly controls the positioning
of the electron beam generated by the CRT.
COMPOSITE
VIDEO

AC
INPUT I....-~....,

I
LOGIC

VIDEO
LOGIC

____ ..l ___ _
SYSTEM
COMMUNICATION
LOGIC

EIA
PRINTER
HOST PORT
PORT

20mA
PORT

'CONNECTOR PHYSICALLY MOUNTED ON
PS AND MONITOR BOARD

Figure 8-1

LOGIC
BOARD

ITOR
ASSEMBLY

MA-0613-84

VT220 Series Terminal
Functional Block Diagram
8-1

8.2

MAJOR CIRCUITS AND COMPONENTS

The monitor circuits
components/circuits.
•
•
•
•
•
•
•
•
•

(Figure

8-2)

consist

the

following

Video amp
Horizontal deflection circuit
Flyback transformer
vertical deflection circuit
Dynamic focus
Brightness control
CRT
Yoke assembly
+12 V filter

The yoke assembly is described in conjunction with the horizontal
and vertical deflection circuit descriptions. No description is
provided concerning the +12 V filter.
NOTE
Circuit illustrations provided are based
on REV A of CS 5415651-9-1.

BRIGHTNESS
THUMBWHEEL

FROM VIDEO IN
VIDEO - - - - . . ,
LOGIC
VIDEO
AMP
TO
VIDEO
VIDEO _
_GND
_ _....1..----1
LOGIC

FROM HOR IN
HORIZONTAL
VIDEO :.:.=c..;,.;,.;,...-.jDEFLECTION 1------.---1
LOGIC
CIRCUITS
TO PS

FLYBACK
TRANS.

(BIAS)

r -+12V-'

DYNAMIC
·FOCUS

FROM +12V 1~3~~
FILTER
PS
~+12V

~3~~fJ
":'

FROM
VIDEO VER IN
LOGIC

":'

VERTICAL
DEFLECTION I----------'---r--L.:.~
CIRCUITS
MA·0722-84

Figure 8-2

Monitor Circuits Block Diagram

8-2

8.2.1

Video Amplifier (Amp) Circuit

The video
the video
the CRT.

amp is a two-stage circuit converting video input from
logic on the logic board into an emitter pote'ntial at

The video amp (Figure 8-3) consists of the following circuits.
•
•
•
•
•

Video input (R10l-R103)
Input stage (Q10l and R105)
Output stage (Q102, C102, R109, and R108)
Voltage divider (R106, R107, C150, and C15l)
Frequency compensation (C10l and R104)

Video input
(a 2.5 V peak to peak signal, from 0 V to +2.5 V) is
supplied to the base of Q10l through the contrast thumbwheel
potentiometer
(R10l). C10l provides for frequency compensation
when Q10l and Q102 are conducting. A +60 V input from the flyback
transformer to R109 provides the voltage supply for emitter output
to the CRT.
With no signal input, Q10l is off, and Q102 has a bias of 7.2 V on
its base from R106 and R107. When a video signal is applied to the
base of Q10l, Q10l is turned on, forward biasing Q102. With Q102
on, the potential developed across R109 is dc coupled to the CRT
emitter through R108 (R108 protects Q102 from transients that can
occur as a result of high voltage arcing at the CRT anode) •

J2
PIN
FROM
VIDEO 11
LOGIC

0102
BF457

0101
2N2369A
R101
250B

'14---""----+1
R103
75

R106
1.BK

Rl02
150

C150
IUF
100V

R109
820
2W

FROM
FLYBACK
TRANSFORMER
(0100)
FROM
+12V
FILTER

J2
PINS

Figure 8-3

R10B
2201/2 W

Video Amplifier Circuit Diagram

8-3

8.2.2

Horizontal Deflection Circuit

The horizontal deflection circuit develops the potentials supplied
to the horizontal windings of the yoke assembly. These potentials
provide for deflection of the CRT electron beam during horizontal
trace and retrace times. Horizontal retrace time is defined by a
horizontal sync signal input from the video logic (HOR IN).
The horizontal deflection
following circuits.
•
•
•

circuit

(Figure 8-4) consists of the

Horizontal processor
Horizontal driver
Horizontal output

8.2.2.1 Horizontal Processor Circuit -- The horizontal processor
circuit provides the base control for defining trace and retrace
periods. It develops a square wave output that is low during the
second half of trace time, and high at all other times.
The horizontal processor
following circuits.

circuit

(Figure

8-5) consists of the

•

Horizontal processor device (E201)

•

Horizontal sync input network (C200, R200, and R202)

•

Horizontal hold
C203, and C204)

•

Horizontal
and C207)

•

Voltage
ZDl)

network

centering

divider

(R203, R204, C202, R205, R208,

(phase) network (R2l5, R211, C208,

network

(R206,

C206,

C205, R210, and

The horizontal hold network provides for adjustable control (R203)
of the base frequency of the processor (E201). The horizontal
centering network provides for adjustable control (R2Il) of the
feedback from the horizontal output, which is compared by E201
against the HOR IN from R200, to determine the phase difference
between the HOR IN and horizontal output circuit conditions. The
voltage divider network defines the output duty cycle of E201 (20
us, +lus) , with this duty cycle reflected as a square wave output
from E201, pin 1, to the horizontal driver circuit (the output
from E201, pin 1 is also sent to the pulse width modulator in the
PS as a sync signal).

8-4

FLYBACK
TRANSFORMER
PRIMARY

(TlI
FROM
VIDEO
LOGIC

HOR IN

HORIZONTAL
DRIVER

HORIZONTAL
PROCESSOR

HORIZONTAL
OUTPUT

HORIZONTAL
WINDINGS
L-____________________________________~ (YOKE ASSY)
MA·0724-84

Figure 8-4

Horizontal Deflection Circuit Block Diagram

R210
1001/2W

L
HOR
FROM
IN
12
VIDEO
LOGIC J2
PIN

C200
.'
300 P/500V

R206
1.2K
ZDI
3.6V

R203
5K

_~6

R204
16.5K
1%

R200
1.8K

~'"

r----

8
1

R205
150K
R202
18K

470
16V

R209
820

TO
HORIZ
DRIVER
(R212)
FROM
HORIZ
OUTPUT
(Q202
COLLECTOR)

R215
18K

2
-C207

5
R208

,,, C203
.0047

C204 .... ,
1/100V

.068
200V

~g~7~T

250V

.r.R211
100B
GND8

• OUTPUT TO PULSEWIDTH MODULATOR FROM
E201, PIN 1, IS NOT SHOWN IN SCHEMATICS;
THIS OUTPUT SYNCHRONIZES PULSEWIDTH
MODULATOR OPERATION TO HORIZONTAL
RETRACE PERIODS.

Figure 8-5

.1
100V

E201
MC1391P

-::

GND

~~205

,
C206

~
C202
;:;r- .0056

FROM
+12V
FILTER

MA·0725-84

Horizontal Processor Circuit Diagram

8-5

8.2.2.2 Horizontal
Driver Circuit
The horizontal driver
circuit converts the square wave input from the horizontal
processor to a bias potential to the horizontal output circuit.
The horizontal driver circuit
following components/circuits.
•
•
•
•

(Figure

8-6)

consists

the

Driver (Q201)
Base bias resistor (R212)
Power source filter (C210)
Output network (T201, R213, R214, and C211)

A high input is applied to the base of Q201 for horizontal retrace
and first half of trace, a low for second half of trace. A high
input forward biases Q201, placing 10 volts across the primary of
T201,
with
the
resulting secondary potential turning the
horizontal output circuit off. When a low input turns Q201 off,
current is reversed at the secondary of T201, turning on the
horizontal output circuit.
R213 limits the current through
voltage across this transistor.

Q20l, and R2l4 and C211 limit

FROM
+12V
FILTER
R213
10
1/2W
TO
HORIZ
r--.l...--, , . - - - - - - - OUTPUT
(L200)

FROM
HORIZ
PROCESSOR
(E201
PIN 1)

R212
470

R214

----+--+-4

68
1!2W
C211
.1

C210
4.7
100V

GND

l00V

ar-~--~-~--~-+GNDG)
MA-0726-84

Figure 8-6

Horizontal Driver Circuit Diagram

8-6

8.2.2.3 Horizontal
Output Circuit
The horizontal output
circuit is turned on and off by the horizontal driver circuit to
generate the potential applied to the horizontal windings of the
yoke assembly. The horizontal output circuit potential is also
used to control flyback transformer activity (refer to description
in section 8.2.4).
The horizontal output
components/circuits.

(Figure

8-7)

consists

of the following

•

Input network (R216 and L200)

•

Drive transistor (Q202)

•

Collector
R218)

•

Charge pump circuit (C106, D101, D102, and C105)

•

Horizontal linearity (L201, L202, R217, and C212)

•

Yoke connector (Jl)

•

Output components (C216, C213, D200, R231, and C224)

voltage

network

(Tl primary, D201, C214, and

TO
BRIGHTNESS
CONTROL
(Rll0)

PART OF F L YBACK
TRANSFOMER
(Tl)

TO
DYNAMIC
FOCUS
(R221)

S207
PUR

r-- -,

I 5~207

~~
S207
P207
YEL

Q202
MJE
13006
FROM
HORIZ
DRIVER
(T201)

L201
WIDTH

L200
R217
100
l/2W
R216
22

GND

Cl05
10
250V

C212 " L202
LIN
.1
100V

C213
.022
250V

~~~~~~~~~~~I
C216
R231
I
10
25V

TO
HORIZ PROC
(C207)

TO
DYNAMIC FOCUS
(D203)

FROM
+12V FILTER

270
C224
6SOP
lKV

TO
DYNAMIC
FOCUS
(C223)

PART
OF
Jl

PART
OF
YOKE
ASSY

MA·0727·84

Figure 8-7

Horizontal Output Circuit Diagram
8-7

Q2~2
T2~1

is turned on and off by current flow through the secondary of
in the horizontal driver circuit. During the second half of
retrace, Q2~2 is turned on to saturation. At other times, Q2~2 is
backbiased
by
T2~1,
quickly turning Q2~2 off to minimize
dissipation.
The Q2~2 collector voltage is 'sourced at +12 V and boosted throu9h
the collector voltage network to +15.5 V.
The charge pump circuit inverts the large positive voltage swings
at the collector of Q2~2 into -17~ V bias used by brightness
control and dynamic focus circuits.
The
horizontal linearity circuit provides adjustable
(L2~1)
control of current flow through the horizontal windings of the
yoke assembly during trace and retrace scanning. L2~1 provides
variable inductive reaction for adjusting current flow and varying
the trace width. L2~2 provides nonlinear reactance that varies
with changes in yoke current. R217 and C212 provide correction for
nonlinearity caused by the decaying exponential rate of current
increase in the yoke.
The output components switch yoke current back and forth between
C213 and C216.
Figure 8-8 provides an illustration of the waveform developed at
the horizontal windings of the yoke assembly during trace and
retrace periods. Points T~ through T3 are identified in this
figure as references within the waveform. Figures 8-9 through 8-12
provide
illustrations and descriptions of the current flow
conditions that result in the waveform shown in Figure 8-8.

CURRENT
THROUGH
YOKE
- 0 AMPS

t=jfml=~~;:;=::~n:~~~~~~;:E
ACROSS
YOKE
T1 T3
T2

TO
MA-4t30

Figure 8-8

Horizontal Deflection Waveform

8-8

YOKE
0202
+15.5
C216

ACTIVITY DESCRIPTION

INITIAL CONDITION:

1.
2.
3.

0202 OFF;
CURRENT THROUGH YOKE AT ZERO;
C216 CHARGED TO +15.5V.

ACTION:
1.
2.
3.
4.
5.

0202 TURNED ON;
CURRENT STARTS FLOWING THROUGH YOKE SUPPLIED
BY CONSTANT VOLTAGE AT C216;
CURRENT INCREASES IN LINEAR FASHION THROUGH
YOKE, DEFLECTING BEAM TO RIGHT OF THE SCREEN;
INDUCTIVE ENERGY IS STORED IN YOKE;
C213 IS GROUNDED BY SATURATED 0202.
MA-0729-84

Figure 8-9

Horizontal Trace:
Scan from Center to
Right Side of Screen
(T0 Time)

EJYOKC
ACTIVITY DESCRIPTION
I NITIAL CONDITION:
1.
2.
3.

0202 SATURATED;
CURRENT THROUGH YOKE AT MAXIMUM;
C216 CHARGED TO OV.

ACTION:

1.
2.
3.
4.
5.

0202 TURNED OFF;
YOKE CURRENT CONTINUES FLOWING DUE TO INDUCTIVE
INERTIA AS STORED MAGNETIC FIELD COLLAPSES;
C213 OUICKLY CHARGES TO fjlGH VOLTAGE;
HIGH VOLTAGE AT C213 CAUSES FAST REDUCTION IN
CURRENT FLOW THROUGH YOKE;
CRT BEAM IS OUICKLY MOVED TO CENTER OF THE SCREEN
ITO).
MA-0730-84

Figure 8-10

Horizontal Retrace:
Move to Center from
Right Side (Tl Time)

8-9

+17[0l

YOKE

ACTIVITY DESCRIPTION
INITIAL CONDITION:

1.
2.
3.

Q202 OFF;
CURRENT THROUGH YOKE AT ZERO;
C213 CHARGED TO +175V.

ACTION:
1.
2.

C213 VOLTAGE DISCHARGES THROUGH YOKE;
QUICK RISE IN YOKE CURRENT MOVES BEAM TO LEFT
SIDE OF SCREEN.
MA-0731-84

Figure 8-11

Horizontal Retrace:
Move to Left Side
from Center (T2 Time)

YOKE

D200

+15.5
C216

ACTIVITY DESCRIPTION
INITIAL CONDITION:

1.
2.
3.
4.

Q202 OFF;
CURRENT THROUGH YOKE AT MAXIMUM;
C213 DISCHARGING;
VOLTAGE ACROSS C216 EQUALS OV.

ACTION:
1.
2.
3.
4.

INDUCTIVE INERTIA FORCES TOP OF YOKE SLIGHTLY
NEGATIVE;
NEGATIVE FROM YOKE FORWARD BIASES D200
PROVIDING FOR CURRENT PATH THROUGH C216;
YOKE CURRENT GRADUALLY DECREASES AS
MAGNETIC FIELD COLLAPSES, DISCHARGING INTO C216;
BEAM MOVES IN LINEAR FASHION TO CENTER OF THE
SCREEN.
MA_0732_84

Figure 8-12

Horizontal Trace:
Scan to Center from
Left Side of Screen
(T3 Time)

8-113

8.2.3

Flyback Transformer Circuit

The flyback transformer circuit provides high voltage anode
(12,500
V), cutoff grid
(+750 V)
and variable focus grid
potentials to the CRT, as well as operational voltage (+60 V) for
the video amp and brightness c6ntrol circuits.
The flyback transformer circuit
following components/circuits.

(Figure

•

Flyback transformer (Tl)

•

+60 V output (0100 and L204)

•

Cutoff grid
and C220)

•

Focus grid bias network (R220-R221)

8-13) consists of the

bias network (L203, 0202, R219, C219, R224,

The outputs from the flyback transformer are controlled by Q202 in
the
horizontal output portion of the horizontal deflection
circuit. When Q202 cuts off, a 175 V pulse is passed across the
primary of T1. This pulse results in the anode, cutoff and focus,
and video amp and brightness control voltage outputs.
HV
ANODE
POTENTIAL
TO
CRT

TO
BRIGHTNESS
(R 113, Cl07)
Dl00
RG1J

TO
VIDEO AMP
(Rl09)

TO
CRT
(CUTOFF
GRID)

l204

r---

[--Til
S207 PUR

) P207

o..'l

S207 YEl

) P207

P207

41 l203

,.llQ.L 21'S207 RED
';[

TO/FROM
HORIZONTAL
OUTPUT

S207 BRN )P207

7
8

S207 BlU

P207

D201 I]P207
l,!115M S201 GRN

1;/

R219
1M

R224
lOOK

D202
IN5623

R223
6.8M

R220
1M

S207
BlK

C219

;:: "-.02

-T-...J

R221
5M
C218
.02 'i"
lKV

GN D

TO
CRT
(FOCUS
GRID)

lKV

C220
;;: ,.02
lKV

R222
lOOK

-170V
FROM
HORIZONTAL OUTPUT
(CHARGE PUMP)

FROM
DYNAMIC
FOCUS
(C222)
MA·0733-84

Figure 8-13

Flyback Transformer Circuit Diagram

8-11

The anode output is rectified internal to Tl, and filtered by
graphite coatings at the CRT end of the anode wire, which can
connect or disconnect only at the CRT end.
The operational voltage (+6~ V)
used
brightness control circuits is output
regulated and filtered by Dl~~ and L2~4.

by the video amp and
from pin 2 of Tl and

The cutoff grid potential is taken from pin 4 of Tl and regulated
by L2~3 and D2~2. The regulated potential (+75~ V) is routed to
the CRT cutoff grid via a voltage divider network (R219 and R224,
filtered by C219 and C22~), and to R22~ in the dynamic focus
circuit.
The focus grid potential is picked off of the focus potentiometer
(R221) with a voltage range at R221 from +5~~ V to -17~ V. The
positive range is developed from the same Tl output used for the
cutoff grid potential, while the negative range is developed from
input from the charge pump circuit in the horizontal output
circuit. The actual focus grid value sent to the CRT is developed
across R222 in conjunction with the value supplied by the dynamic
focus circuit (refer to section 8.2.5).
8.2.4

Vertical Deflection Circuit

The vertical deflection circuit develops the potentials supplied
to the vertical windings of the yoke assembly. These potentials
provide for deflection of the CRT electron beam during vertical
trace and retrace times.
vertical deflection is a linear current rise to the vertical yoke
windings during a complete scan of the screen (each scan line of
the scan defined by horizontal trace and retrace activity). A
complete scan of the screen occurs at a rate of 6~ vertical trace
periods per second. vertical retrace time is defined by a vertical
sync signal input from the video logic (VER IN). VER IN results in
a steep drop in the current supplied to the vertical yoke
windings, returning the placement of the CRT beam to the top of
the screen.
The vertical deflection
following circuits.

•
•

circuit

(Figure

8-14) consists of the

Vertical processor
vertical output

8.2.4.1 vertical Processor Circuit
The vertical processor
circuit provides the base control for defining trace and retrace
periods. It develops a ramping output used by the vertical output
to move the CRT beam from the top to the bottom of the screen
through linear increase of current flow through the vertical
windings of the yoke assembly.
8-12

TO
DYNAMIC
FOCUS
(C313)
VERTICAL
1---'--................ WINDINGS
OF
t - -........... j YOKE
~----~
A$Y

FROM
VERTICAL
VIDEO - - - - - I PROCESSOR
LOGIC

VERTICAL
OUTPUT

MA_0734-84

Figure 8-14

FROM
+12V
FIL TER

vertical Deflection Circuit
Block Diagram

+12V
D301 "
IN4004

C303
;::,100
25V
J2
PIN

R254
lK

15
FR OM

VER IN

VI DEO
LO GIC
R301
4.7K

R305
221K
196
C305
300PF'" ,
500V

11
4

--..2

R310

3.31/m
C3r[10100V

10
8

E301
TDA 1170S

9
r--

R306
562K

C304
... i'.1
150V

V-LIN
n.R307
lOOK

R308
47K

7 112
R304
390K
VHEIGHT

267K
UfJ6
1%

c307
.1150V
C306

C308 -:~
.1
;;;1'
150V

R303
R309
r-: 250K
;;; i'2200P 820K
100V

GND c

Figure 8-15

TO/FROM
} VERTICAL
OUTPUT

vertical Processor Circuit Diagram

The vertical processor circuit
following components/circuits.

(Figure

8-15)

consists of the

(E3~1)

•

vertical processor device

•

Vertical sync input (R254 and

•

Voltage regulator

•

Oscillator synchronizer

•

Current regulation

•

Ramp sensor

•

Power amp stabilization network
and C31~)

(R3~5,

R31~,

C3~5,

•

vertical linearity control

(R3~8,

R3~7,

C3~7,

and C3~8)

(D3~1

(R3~3

R3~1)

and

(R3~2

and

and C3~4)
R3~4)

(R3~6)

8-13

C3~6,

The vertical sync input initiates retrace each time it goes low
(60
times
per
second). However, the E301 is capable of
free-running trace and retrace, in the event no retrace sync
signal is sensed from the video logic. R302 and C304 define E301
internal free-running oscillation at 60 Hz (+1 Hz).
At the start of a vertical trace, E301 outputs a voltage potential
on pin 4. This potential is stabalized and output to the vertical
output circuit. Feedback from that circuit is input to E301 at pin
10. This feedback is applied across R306 and compared with the
adjustable (R307) vertical linearity value at pin 1 of E301. The
feedback at pin 10, and the value at pin 1 are used by E30l to
monitor gain and to compensate for any drift in output voltage
value.
The output potential at pin 4 of E301 is ramped upward throughout
the trace period. At vertical retrace, the output is returned to
zero, removing the ramped potential from the vertical output
circuit.
Current regulation on the output of E301 is controlled by an
adjustable regulator (R303), which can increase or decrease the
height of the area of the screen scanned during a vertical trace.
8.2.4.2 vertical Output Circuit -- The vertical output circuit
develops the potentials used to drive current through the vertical
windings of the yoke assembly.
The
vertical output
following circuits.
•
•

circuit

(Figure

8-16)

consists

the

Voltage divider network (R31l-R314 and C309)
Yoke current drive components (C311, C312, R317, and Jl)
R311
4.7K
1%
TO/FROM
{
VERTICAL
PROCESSOR

TO
OYNAMIC
FOCUS
(C313)

----.----+----r---,
C311
1000

R312
56.2K
1%

C309
47
10V

PART
OF

R313
16V
C312
47.5K
1000
1-1%--If----I 16V
R314

R315
R317
100
1/2W

4
PART
OF
YOKE
ASSY
MA-0736-B4

Figure 8-16

Vertical Output Circuit Diagram
8-14

Output from the vertical processor circuit is applied to the
voltage divider network. The resulting voltage drop caused by
current flow through R314 and R315 is reflected back to the
vertical processor circuit at R313.
During vertical trace, the output capacitors are incrementally
charged, with a resulting incremental flow of current through the
vertical windings of the yoke assembly. This moves the CRT beam
from top to bottom of the screen during the trace.
At the start of retrace, the input from the vertical processor
returns to zero. This results in C311 and C312 discharging through
the vertical windings of the yoke assembly. This reverse in
current flow quickly moves the CRT beam back to the top of the
screen.
8.2.5

Dynamic Focus

The CRT beam travels further when deflected to a corner of the
screen than when scanning near the center. The dynamic focus
circuit optimizes focus in the corners.
The dynamic focus circuit (Figure 8-17) consists of the following
components/circuits.
•
•
•
•
•
•

Operating voltage network (D203 and C221)
Horizontal component coupling (C223 and R230)
vertical component coupling (C313 and R316)
Focus transistor (Q203)
Bias resistors (R225-R229)
Output coupler (C222)
---.---TO
FROM
HORIZ
FLY BACK
OUTPUT
TRANSFORMER
0203
(Q202)
(Tl. PIN 6)
RGIJ

TO
CRT
(FOCUS
GRID)

C3l3
47
10V

l~,

R3l6
FROM
470
VERTICAL ------.J
OUTPUT
---,t--+-Nr-~
(C3l2)

C22l
0.22
600V

600V

TO
• YOKE
ASSY
C223
(Jl. PI N 2)
.047

r----r--------------~

R226
2.2K

R230
lK

R229
360

GND

a 1--"----.......

GND

c / - - - - - - - - - ' - + GND8

Figure 8-17

FROM
HORIZ
OUTPUT
(C2l6)

Dynamic Focus Circuit Diagram
8-15

0203 and C22l rectify and filter an operational voltage input of
+160 V supplied to the base and collector of Q203 through the bias
resistors.
The horizontal component of the focus value is coupled to the base
of Q203 by C223 and R230, and developed from the charge condition
of C2l6
(refer to section 8.2.2.3, and Figures 8-9 through 8-12)
during scanning. The vertical component of the focus value is
coupled to the base of Q203 by C3l3, and developed by the charge
condition of C3ll and C3l2 during vertical deflection (refer to
section 8.2.4). The output resulting from· the biasing of Q203 is
coupled to the focus grid potential developed by the flyback
transformer circuit through C222.
8.2.6

Brightness Control

The brightness control circuit allows the brightness
display at the CRT to be adjusted by the operator.
The brightness control circuit
following components/circuits.
•
•
•

(Figure

8-18)

of the

consists of the

Reference voltage network (0103, Rl13, C104, and C107)
Voltage divider (Rl10-Rl12)
Bypass capacitor (C103)

Rlll
lOOK

Rl12
47K

Cl04

D103

~~ IN4004
Cl03
.... ~ 0.1
100V
Rll0
lOOK

"I' 22

100V

Rl13
4.7K

TO
VIDEO
AMP
(Rl09)

GND

TO
CRT
(INTENSITY
GRID)

f~"

100V
FROM
FLYBACK
TRANSFORMER
(Dl00)

GND8

-170V
FROM
HORIZONTAL
OUTPUT
(CHARGE PUMP)
MA-0738-84

Figure 8-18

Brightness Control Circuit Diagram

8-16

The
voltage divider network, which includes the brightness
thumbwheel
(RIll), provides for a variable bias (from +9.5 V to
-8~
V)
to the intensity grid of the CRT. The bias is developed
from -170 V input from the charge pump in the horizontal output
circuit
(refer to section 8.2.2.3) a'nd +60 V input to the
reference voltage network from the video amp operational voltage
developed by the flyback transformer.
C103 provides for bypassing transients that occur as a result of
internal CRT arcing, as well as for bypassing video signals from
the intensity grid that would interfere with the frequency
response of the CRT cathode.
8.2.7

CRT Device

The CRT device (Figure 8-19) provides for actual output to the
operator. Video input to the monitor circuits is converted to
emitter potential to the CRT emitter. FOcus, intensity, and cutoff
potentials applied to the three grids of the CRT inhibit (cut off
input from flyback transformer circuit), refine (focus input from
the focus circuit of the flyback transform~r coupled to the value
developed
by
the dynamic focus circuit), and control the
brightness (intensity input from brightness control)
of the
display generated by the CRT beam from the emitter potential
provided by the video amp.

r-----,
I CRT

FROM
VIDEO
AMP
(R10B)

EMITTER

FROM
FlYBACK
TRANSFORMER

YEl

1
II

ANODE

......

(n)

FOCUSGRID
CUTOFF GRID

.
~

...

BlU

RED

....

GRN

......

3 :

BRN

BlK

WHT

INTENSITY GRID
+12V

III
III

.....

L ____
FROM
DYNAMIC
FOCUS
(R222)

FROM
FlYBACK
TRANSFORMER
(R224)

Figure 8-19

FROM
BRIGHTNESS
CONTROL
(R111)

CRT Device

8-17

GND

8
MA-0739-84

CHAPTER 9
POWER SUPPLY

9.1

GENERAL

The power supply (shaded area of Figure 9-1) converts ac input to
dc voltages required for VT22~ terminal operation.

COMPOSITE
VIDEO

PSAND
MONITDR
BOARD
AC
INPUT

I
VIDEO
I
LOGIC
_ _ _ _ ...1 _ _ _ _
SYSTEM
COMMUNICATION
LOGIC

EIA
PRINTER
HOST PORT
PORT

LOGIC
BOARD

20mA
PORT

TO/FROM~~~
EIAHOST
PORT

MODEM
OPTION
'CONNECTOR PHYSICALLY rAOUNTED ON
PS AND MONITOR BOARD
MA-0613-84C

Figure 9-1

VT22~ Series Terminal
Functional Block Diagram

9-1

9.2

MAJOR CIRCUITS AND COMPONENTS

The power supply (Figure 9-2) consists of various components and
circuits, including circuits that physically mount on the logic
board.
•
•
•
•
•

AC input components
AC conversion circuits
Interboard connectors (J1 and J2)
DC input circuits
DC power ok
NOTE
Circuit illustrations in this chapter
are based on REV A of CS 5415651-0-1.

PS AND MONITOR
BOARD

LOGIC
BOARD

AC
CONVERSION
CIRCUITS

1----,. .

fDcl

AC INPUT
COMPONENTS

AC
INPUT

Figure 9-2

MA-0666-84

Power Supply Block Diagram

9-2

9.2.1

AC Input Components

The ac input components provide for ac input, including voltage
range (115 Vac or 230 Vac)
selection. Figure 9-3 shows the
following ac input components.
•

EMI filter
filters ac input which is connected by
power cord directly into the EMI filter.

•

Sl
is the power on/off switch (Sl is shown in off
position in Figure 9-3).

•

S2 -- is the voltage selection switch (S2 is shown at 115
Vac selection in Figure 9-3).

•

Fl -- is a 2, 250 Vac input line fuse.

•

Chassis ground lug -- provides ground connection of ac
input ground from LMI filter.

J501
(230VAC)

S1
AC
INPUT

AC
INPUTS
TO
PS

EMI
FILTER

CHASSIS
GROUND
LUG

PS AND MONITOR
BOARD

Figure 9-3

AC Input Components Block Diagram

9-3

9.2.2

AC Conversion Circuits

The ac conversion circuits convert ac input into three dc voltage
outputs: +5 V, +12 V, and -12 V. The ac conversion circuits,
(Figure 9-4) which are all located on the PS and monitor board,
are as follows.
•

J50l
is the
selectionswitch.

connector

for

•

+12 V start up -- provides operational voltage potential
for
overcurrent protect circuit, and also provides
initial power for pulse width modulator during power up
sequence (until +12 V circuit is operational).

•

Input rectification -- consists of components responsible
for rectification and filtering of ac input into the
pulse width modulator controlled switching transistor
circuit, which provides ac input to primary of T50l.

FROM{ 1115VAC)
S2
TO
F1
FROM CHASSIS
GND

F~~M{

RETURN
GND
1115VAC)
1230VAC)

PART
OF
J2

G-50;---'

J501

1230VAC)

input from voltage

INPUT
RECTIFICATION

""2

3
-4
-5

-.E
T504

-6

Ei
~

-12V
OUTPUT

+5V
OUTPUT

ro 7

+5V

.......

+12V
OUTPUT

~I -

I
L: ---.!=
.J

....

PULSE
WIDTH
MODULATOR

+5V
+5V

+12V

f--

.Ig
I--

.10

r-ru

GND
GND

'--

GND
GND

--'

':"

l-I +5V

TO
LOGIC
BOARD

I--

r- 16

OVERCURRENT
PROTECT

i:-

f--

..... f-19

507

+12V
START
UP

....

-12V

It~

12V

+12V

};

o
C
K

ISYNC)
+5V
-12V

TO (FROM
MONITOR
CI RCUITS

+12V
MA-0668-84

Figure 9-4

AC Conversion Circuits Block Diagram
9-4

•

T50l
transforms regulated ac input into secondary
voltages used by the dc output circuits to generate the
required dc potentials.

•

DC output circuits -- generate the dc potential outputs
(+12 V, +5 V, and -12 V).

•

Part of J2
are the pins of interconnection between PIS
and monitor board and logic board used for routing of dc.

Overcurrent
protect
monitors
for +5
overcurrent and +5 V overvoltage conditions.

V/+12

•

Pulse width modulator -- monitors overcurrent protect and
dc output circuits conditions to control width of ac
pulses supplied to T50l by switching transistor network
within the input rectification circuit.

•

T504
provides means for pulse width modulator to
control width of rectifed ac pulses supplied to T50l.

Table 9-1 provides specifications for the ac inputs. Figure 9-4
shows the pinouts for J50l and J2. Each of the ac conversion
circuits
are
described
separately (with the exception of
components J50l,
J2, T50l, and T504, which are discussed only as
they relate to the other circuits).

Table 9-1

Input Voltage Specifications

Voltage

Specification

Value

115 Vac

Nominal voltage
Minimum voltage
Maximum votage
Input line current
Line frequency
Power factor
Inrush current

120 Vac
87 V rms
134 V rms
1 A rms (max.)
47-63 Hz
(watts) -- (rms V X rms A) > 0.55
Surge current at first application
of input voltage may be reached for
1/2 cycle of input line, with
repetitive peaks of exponentially
decaying amplitude for up to 10 more
cycles.
25 A (Thermisters cold)
60 watts (max.) at full rated dc
output load of 40 watts.
0.65 (min.) output power to input
power ratio.
Provides minimum of 10 millisecond
hold-up at 90 V rms during power
outage.
150 Vac for 1 second (max.)

Peak inrush
Input power
Efficiency
Undervoltage
Overvoltage

9-5

Table 9-1
Voltage

230 Vac

Input Voltage Specifications (Cont)
Specification

Value

Transients

Low energy transient of 300 V peak
spike with no more than 0.2
watt-seconds of energy per spike;
High energy transient of 1 kv peak
spike with no more than 2.5
watt-seconds of energy per spike.

Nominal voltage
Minimum voltage
Maximum voltage
Input line current
Line frequency
Power factor
Inrush current

220 Vac-240 Vac
174 V rms
268 V rms
0.5A rms (max.)
47-63 Hz
(watts) -- (rms V X rms A) > 0.55
Surge current at first application
of input voltage may be reached for
1/2 cycle of input line, with
repetitive peaks of exponentially
decaying amplitude for up to 10 more
cycles.
25 A (Thermisters cold)
120 watts (max.) at full rated dc
output load of 77 watts.
0.65 (min.) output power to input
power ratio.
Provides minimum of 5 millisecond
hold-up at 180 V rms during power
outage.
300 Vac for 1 second (max.)
Low energy transient of 300 V peak
spike with no more than 0.2
watt-seconds of energy per spike;
High energy transient of 1 kv peak
spike with no more than 2.5
watt-seconds of energy per spike.

Peak inrush
Input power
Efficiency
Undervoltage
Overvoltage
Transients

9.2.2.1 +12 V Start Up Circuit -- The +12 V start up circuit
(Figure 9-5) consists of the following components/circuits.
•
•
•
•

AC input transformer (T502)
Rectifier (E50l)
Filter capacitors (C50l and C502)
+12 V regulator components (E502, 0501, and 0502)

The +12 V start up potential provides an operational potential for
the comparator within the overcurrent protect circuit. The +12 V
start up potential is also supplied to the pulse width modulator
where it provides initial power for operation of this circuit
until the +12 V dc circuit is operational.
9-6

TO/FROM

{. . ;:. .; :0-T~;. .:

1 T502 4

E501

...
:-2""\lilr--..,

J501

TO
t-r-t~I--r--PULSE WIDTH

I
....;1...
1 5;...V_A_C-..;;,3..11 I

1N4004
C502
10
25V

MODULATOR
TO
OVERCURRENT
PROTECT

MA-0669-B4

Figure 9-5

+12 V Start Up Circuit Diagram

R501

230VAC
E503
MDA206
3
TO/FROM
J501

T501

R503
100K
1W

C505
10
25V

PART OF
T504

C503
220
250V

'"OM
{
PULSE
WIDTH
MODULATOR

5·

RETURN 2

R506
56
2W
C507

115VAC

1KV
3300P
C530
3300
1KV 6

C522
.51
400V
R502
100K
1W

C504
220
250V

PART OF
T504
FROM

~~~~
R500

C506
10 25V

"D505
{

N·~H~g"~t-R-5-i05H

11c-!7:1

MODULATOR. 8

Q502
2SC
2335

MA-0670-84

Figure 9-6

Input Rectification Circuit Diagram

9.2.2.2 Input Rectification Circuit -- The input rectification
circuit rectifies and filters the ac input to produce positive,
negative, and neutral "dc type" signals. These signals are then
used as a power supply for two switching transistors. The
switching transistors produce an ac signal applied across the
primary of T501, with the width of the ac signal controlled by
input to the switching transistors from the pulse width modulator.
The input rectification circuit
following components/circuits.

(Figure

9-6)

consists of the

•

Rectifier (E503)

•

Thermistors (R500 and R50l)

•

Filter networks (R503 and C503, R502 and C504, and R506,
C507, and C530)

•

Switching transistor networks (Q501 and Q502, and related
components)
9-7

Q501 and Q502 are coupled to the pulse width modulator in reverse
polarity via T504. Current is induced in T504 by the pulse width
modulator, with the effect on the switching transistors determined
by the direction of the current flow. When current in T504 is
induced from pin 6 to pin 5 and pin 7 to pin 8, back biasing of
Q502 occurs, turning this transistor off, which results in Q50l
being turned on (with charge of C505 speeding up the transition).
When current is the reverse, Q50l is back biased and turned off,
with Q502 turned on
(with charge of C506 speeding up the
transition).
The result is an ac signal to the T501 primary
controlled by the width of pulses output from E505, the pulse
width modulator.
9.2.2.3 OC Output Circuits -- The dc output circuits (Figure 9-7)
consists of the following components/circuits.
•

-12 V output circuit containing a rectifier (0507 and
0508), filter networks
(L501 and C508, and C509, R525,
and R526), and a voltage regulator (E504).

•

+5 V output circuit containing a rectifier (0509), and
filter networks
(T503 and C510, and L502, C523, and
C513) •

D507
RG1J

T501

I
I

L501

3
2

1----.--....---.-- -12V
C508
330
50V

D508
RG1J

C509
.47

R525
1K

R526
1K

I
I
I

r - -, D509
9

I
I

IFE16D
I
I

r--_ _ PULSE WIDTH
MODULATOR

r-I----r---i......-.,-t-"'+-'l:n"""~__._-+--....---.---t-- +1 2V

I
I
~
Figure 9-7

ID510

IFE16D
I

C511
1000
25V

TO
OVERCURRENT
PROTECT

C510
1000
10V

C512
.47

C518
.1

C513
47

MA-0671-84

DC Output Circuits Diagram
9-8

•

+12 V output circuit containing a rectifier (0519), and
filter networks (R598 and C529, and T593, C511, C512, and
C518).

•

Sensing resistor

(R~97).

DC outputs are generated from T591 secondary potentials and output
to the logic board
(via J2), monitor circuits, and the dc ok
circuit. In addition, +12 V, along with an output from the +5 V
circuit, is sent to the pulse width modulator, and +5 V, along
with the sensing resistor potential, is sent to the overcurrent
protect circuit. These outputs are monitored to control the pulse
width of the T591 primary potential to compensate for any
overvoltage, undervoltage, or overcurrent condition.
Table 9-2 provides specifications for the three dc outputs.
Table 9-2

Output voltage Specifications

Voltage

Specification

Value

+5 V

Nominal output
Minimum load
Maximum load
Ripple

+5.9 V
1 A
2.2 A
159 MV p-to-p for < 66 KHz (max)
(see note 1)
1% of peak for > 199 KHz (noise is
super imposed on ripple) (see note 1)
+5.9%
+5.9%
+5.9%
9.1%/1999 hr (see note 2)
+9.925% per degree centigrade (see
note 2)
+2.2% (see note 3)
Current limit with foldback (limit
point of 6.5 A max. and foldback at
3.3 A max.)

Noise
Total regulation
Static line reg.
Static load reg.
Long term stability
Thermal Drift
Dynamic load reg.
Overload protection

NOTES:
1.

Ripple and noise must be measured with wide band oscilloscope
such as TektroQix P6946 differential probe, with scope set for
>199 MHz bandwidth, and specification applies only to
repetitive voltage variations occuring while operating with
constant input voltage and fixed load.

Long term stability and thermal drift specifications apply
after five minute warm up and are measured at the dc
distribution buses with an averaging meter.

Dynamic load regulation is measured in +25% load steps from a
starting point of 75% of full load, with measurements made at
power suppy terminals.
9-9

Table 9-2

Output Voltage Specifications (Cont)

Voltage

Specifications

Value

+12 V

Nominal output
Minimum load
Maximum load
Ripple

+12 V
1 A
2.2 A
240 MV p-to-p for < 66 kHz (max)
(see note 1)
1% of peak for > 100 kHz (noise is
superimposed on ripple) (see note 1)
+5.0%
+0.5%
+0.2%
0.1%/1000 hr (see note 2)
+0.025% per degree centigrade
(see note 2)
+2.0% (see note 3)
Current limit with foldback (limit
point of 6.5 A max. and foldback at
3.3 A max.)

Noise
Total regulation
Static line reg.
Static load reg.
Long term stability
Thermal drift
Dynamic load reg.
Overload protection

-12 V

Nominal output
Minimum load
Maximum load
Ripple
Noise
Total regulation
Static line reg.
Static load reg.
Long term stability
Thermal drift
Dynamic load reg.
Overload protect

-12 V
0.0 A
0.2 A
240 MV p-to-p for < 66 kHz (max)
(see note 1)
1% of peak for > 100 kHz (noise is
superimposed on ripple)
(see note 1)
+5.0%
+0.5%
+1. 0%
0.1%/1000 hr (see note 2)
+0.025% per degree centigrade
(see note 2)
+2.0% (see note 3)
Internal current limit by
regulator

9-10

9.2.2.4 Overcurrent Protect Circuit -- The overcurrent protect
circuit monitors the +5 V dc output to sense an undervoltage
condition, and the dc output circuits sensing resistor (R507)
potential to sense overcurrent condition resulting from a short in
either the +5 V or +12 V output circuits.
The overcurrent protect
following circuits.
•
•

circuit

(Figure

9-8)

consists of the

Summing network (R514, R523, and R524)
Voltage comparator components (E506 and R509)

The sensing resistor potential, +5.1 V reference voltage input
from the pulse width modulator, and +5 V input are summed to
provide biasing to the plus input of the comparator. This bias is
reflected in the output from the comparator, which is sent to the
pulse width modulator.
If overcurrent or overvoltage conditions
exist, the output of the comparator will go low, caused by a
negative value present at the comparator's positive input. This
will cause the pulse width modulator to output a minimum pulse
width, effectively shutting off the power supply to prevent
further damage.

FROM

+12V
START UP

+S.lV
FROM
PULSE WIDTH
MODULATOR FROM
CURRENT
SENSING
RESISTOR
(R507)

R524
16K 1%
_ _-~
R523
4871%

R509
TO
>7,--03>M30_____ PULSE WIDTH
MODULATOR

RS14
lSK
1%

SV
MA-0672-84

Figure 9-8

Overcurrent Protect Circuit Diagram

9-11

9.2.2.5 Pulse
width
Modulator Circuit
The pulse width
modulator monitors the +12 V output potential, along with inputs
from
the +5 V output, overcurrent protect, and horizontal
processor in the monitor circuits, to control the width and
frequency of pulses passed through the primary of T501 by biasing
of the switching transistors in the input rectification circuit
(via T504).
The pulse width modulator (Figure 9-9) consists of the following
components/circuits.
•

Pulse width modulator device (E505)

•

Power input components (0511 and C521)

•

Summing network (R5l7-R520)

•

Pulse control output network (R5l0, 0512, and 0513)

•

Oscillator
054)

synchronization

•

Oscillator
C514-C5l6 )

frequency

•

Biasing components (R515 and R516)

•

Start-up delay capacitor (C517)

input network (R54, C54, and

control

components

r-- FROM +12V
OUTPUT

+5V OC
OUT PUT

~~PUT

C521~
.47 ~

RECTIFICATION {

r-;--

111

0512
0664 ~~

I-~7

15
R510

~72

11
14

0664

E505
SG3525A

R511
4.75K
1%

R518
5.11 K
1%

R520
5.11 K
,iP 1%

FROM
HORIZ
--PROCESSOR
C54
IN
680P
MONITOR
CIRCUITS
054
j~ 1 N4004

~
R516
33K

~
~
;;1'
:;:1' C515;::~ ;1'
C514
C516
C517
4.7
100V

R519
6.49K
1%

t3~
~

.!2

R527
500B

R517
5.11 K
1%

~0513

FRO M+12V
OUT PUT

CIRCUIT

I-FROM +12V
STARTUP
PART OF
T504

1000P

.0047

R527,

FROM

TO
OVERCURRENT
PROTECT

0511 L~ Ir
1 N4004

(R511,

.01

R515
470K
R54
2.2K

f--

FROM
OVERCURRENT
PROTECT
MA-0673_S4

Figure 9-9

Pulse width Modulator Circuit Diagram

9-12

The pulse width modulator circuit generates two outputs: Biasing
to the switching transistors in the input rectification circuit
(via T504) and +5.1 V reference voltage to the overcurrent protect
circuit.
The input to the pulse width modulator from the horizontal
processor in the monitor circuits is a sync input to the pulse
width modulator's internal oscillator. This input synchronizes
modulator operation to horizontal retrace time.
The switching transistor bias output is directly affected by the
biasing supplied to the pulse width modulator device by the
overcurrent protect circuit
(pin 8 input to modulator), summing
network input
(developed from +12 V potential summed with input
from +5 V output circuit), and the power sensing components.
The power sensing components provide for operational voltage input
from
either the +12 V start up circuit
(during power up
situations), or from the +12 V dc output circuit (when fully
operational following a power up). C517 inhibits operation during
the power up sequence by holding pin 8 of E505 low until this
capacitor can be charged up.
This prevents operation of the pulse
width modulator during the time that initial surge conditions may
occur.
9.2.3
DC OK Circuit
The dc ok circuit provides visual indication of the presence of dc
in the monitor module. The dc ok circuit (Figure 9-10) consists of
the following components.
•
•
•
•

LED indicator (0400)
Connector (J7)
Drive transistor (Q400)
Biasing components (R400, R401, and 0401)

+5V

+12V

R400

12K

R401

1.5K

-12V

Figure 9-10

9-13

MA-0674-84

DC OK Circuit Diagram

+5 V, +12 V, and -12 V potentials are applied as inputs to the dc
ok circuit. When all three inputs are present to turn on Q400,
0400, which is mounted on the front panel of the VT220, and
connected to Q400's collector via J7, it will light.
9.2.4
DC Input Components
The dc input components located on the logic board provide for
additional filtering of dc potentials to be used by the monitor
module logic board components, and for the +12 V potential to be
output to the LK201 keyboard module. They also develop a fourth dc
potential, -6 V, from the -12 V input.
The dc input
components.

components

(Figure 9-11) consist of the following

•

+5 V filter capacitors (C41 and C47)

•

+12 V filter capacitor (C42)

•

-12 V components (OS, C43, and C45)

•

-6 V regulation components (R42 and 04)

•

Individual IC +5 V decoupling capacitors (Cl, C3, C4,
Cll, C14-C39, and C48-C54)

-12 VA
board.

an unfiltered version of the -12 V input to the logic

PART OF

,r J1
+5V
+5V

~--~~~~--~----------'+5V

+5V
FROM
PS AND
MONITOR
BOARD

+12V

C1.C3.C4.C11
C14-C39.C48-C54

C41

+5V

.22J.tF

.01J.tF

1---,.---+---+-----+--------- +12V

GND
GND

C45

C43

GND

10J.tF

22J.tF

h------+III---+----...1....----.1..-----_ -12V
D4
1 N753A
~~~~------------------.-6V

L------------------------__.-12VA
MA-0675_84

Figure 9-11

DC Input Circuits Diagram

9-14

APPENDIX A
SPECIFICATIONS

GENERAL
This appendix lists the specifications of the VT220 terminal.
VT220 SPECIFICATIONS
Physical
Terminal
Height: 28.3 cm (11 1/8 in)
Width: 33.3 em (13 1/8 in)
Depth: 38.7 em (15 1/4 in)
Weight: 11.8 kg (26 1bs)
Adjustable
Tilt: +5 to -15 degrees
Keyboard

Height: 5.1 em
width: 53.3 em
Depth: 17.1 em
Weight: 2.0 kg

(2.0 in)
(21. 0 in)
(6.75 in)
(4.5 lbs)

Environmental
Operating Temperature:

100 to 400 C
(500 to 1040 F)
Relative humidity: 10% to 90%
Maximum wet bulb: 280 C (820 F)
Minimum dew point: 20 C (360 F)
Maximum altitude: 2.4 km (8000 ft)

Storage

Temperature: -400 to 660 C
-40 to 1510 F
Relative humidity: 0% to 95%
Maximum altitude: 9.1 km (30,000 ft)

A-1

Electrical
Line voltage
(switch selectable)

90-128 Vac (100-120 rms nominal)
single phase, 3-wire
180-268 Vac (220-240 rms nominal)
single phase, 3-wire

Line frequency

47-63 Hz

Line current

0.48 Arms @ 120 Vac rms
0.24 Arms @ 240 Vac rms

Input power

60 W maximum

Power cord

Detachable, 3-conductor, grounded

Power cord receptacle
BTU

EIA specified CEE22-6A
215 Btu/hr, 63 W

Display
CRT

30.5 cm (12 in) diagonal measure
monochrome

Active display size

Horizontal: 20.3 cm (8 in)
Vertical: 12.7 cm (5 in)

Format

24 lines of 80 or 132 characters

Character

7 X 9 dot matrix with 2 descenders

Character size

80 column mode:
3.35 X 2 mm (0.132 X 0.078 in)
132 column mode:
3.35 X 1.3 mm (0.132 X 0.051 in)

Character sets

ASCII, UK National, DEC Special
Graphic, and DEC Supplemental
Character Sets (each 94 characters)

Video attributes

Reverse video, underline, bold, and
blinking -- selectable individually
or in any combination

Cursor type

Blinking block character or blinking underline

A-2

Keyboard
General

105 key detachable unit with a 1.8 m
(6 ft) coiled cord with a 4-pin
telephone-type modular connector.
Word processing and data processing
versions available in 15 languages

Keypad

Sculptured key array. Matte texture
finish keys. Home row key height
30 mm (1.18 in) above desk top

Key size

12.7 mm (0.5 in) square

Key spacing

19 mm (0.75 in) center-to-center
(single width keys)

Numeric keypad

18 keys

Function keys

36 keys, firmware and software
driven

Visual indicators

4 LED indicators: hold, lock, wait,
and compose

Audible signals
Keyclick:

Audible feedback for each keystroke

Bell:

Sounds when BEL character received,
when 8 characters from right margin
and for compose errors

Multiple bell:

Sounds on error in set-up, save, or
recall operation.

A-3

APPENDIX B
VT102/220 01 FFERENCES

This appendix describes the major differences between a
terminal and the VT22~ terminal operating in a VTl~~ mode.

VTl~2

Difference Area

VTl~2

VT22~

LEOs

Programmable

Non-programmable

Alternate
character ROM

Socket for OEM
supplied
character ROM

Down-line loadable
character set

Screen freeze

NO SCROLL key

HOLD SCREEN key

Printer port
connector

25-pin

9-pin

Screen refresh

5~/6~

Set-up

Display in
set-up "bits."

Display in three
languages. Different
display. Has no effect
on software.

RIS function

Performs power-up
self test

Does not perform
power-up self test

Off-line/local

Off-line mode
disconnects
modem

Local mode does not
disconnect modem

Communication

Full duplex and
half duplex

Full duplex only.
Does not affect
software

Transmit speed
limitation of 6~
char/s
regardless of
baud rate

Optional transmit speed
limitation of 15~
char/s

Selectable passive
or active 2~ rnA

Passive

B-1

Hz only

rnA only

Difference Area

VT102

VT220

Terminal 10

Responds to
primary device
attributes with:
ESC [ ? 6 c

Responds to primary
device attribute with:
CSI ? 62;1;2;6;7;8;9 c

NOTE
If the terminal is in VT100 mode and an
10 other than VT220 10 is selected, then
the following primary exchanges apply.
VT220 to host
(VT100 10
selected in
set-up)

ESC [ ? 1 i 2 c

VT220 to host
(VT101 10
selected in
set-up)

ESC [ ? 1; 0 c

VT220 to host
(VT102 10
selected in
set-up)

ESC [ ? 6 c

Secondary device
attribute not
supported

Responds to secondary
device attribute with:
CSI > liPvi 0 c
where Pv is firmware
version number

B-2

APPENDIX C
REGISTER BIT VALUES

This appendix contains figures illustrating bit values for the
various register devices within the system box logic board
circuits. The figures are provided for reference only, and are not
meant as a guide to programming the VT220 Series terminal.

MR1A ADDRESS
MR1 B ADDRESS

B7FOH (RD)/B7FOH (WR)
B7FBH (RD}/B7FBH (WR)

01
I

Rx
RTS

RxlDT
SEL

ERROR
MODE

PARITY MODE

PARITY
TYPE

I
(BAD7 H)"

BITS PER
CHARACTER
I

.. (BADO H)

BIT VALUES
BIT 7

RxRTS DISABLED
RxRTS ENABLED

BIT6

INTERRUPT ON RxRDY
INTERRUPT ON FFULL

BIT 5

CHARACTER ERROR MODE
BLOCK ERROR MODE

BIT 3-4

00
01
10
11

WITH PARITY
FORCE PARITY
NO PARITY
SPECIAL MODE

BIT 2

EVEN PARITY
ODD PARITY

BIT 0-1

00
01
10
11

5 BITS PER CHARACTER
6 BITS PER CHARACTER
7 BITS PER CHARACTER
8 BITS PER CHARACTER
MA-0676-84

Figure C-l

2681 DUART: Mode Register 1
(MR1) (Channel A and B)

C-l

B7FOH (RD)/B7FOH (WR)
B7FBH (RD)/B7FBH (WR)

MR2A ADDRESS
MR2B ADDRESS
07

06
I

CHANNEL
MODE

Tx
RTS

CTS
ENABLE
Tx

01
I

STOP BIT LENGTH
I

(BAD7 H) ...
4 f - - - - - - - - - - - - - - - - - - - - - 4•• (BADO H)
BIT VALUES

BIT 6-7

00
01
10
11

NORMAL MODE
AUTO ECHO MODE
LOCAL LOOP MODE
REMOTE LOOP MODE

BIT 5

Tx RTS DISABLE
Tx RTS DISABLE

BIT4

o
1

NO CTS REQUIRED FOR Tx
CTS REQUIRED FOR Tx

0000'
0001'
0010'
0011'
0100'
0101'
0110'
011 1 •
1000
1001
1010
1011
1100
1101
1110
1 11 1

0.563 BIT STOP CHARACTER
0.625 BIT STOP CHARACTER
0.6B8 BIT STOP CHARACTER
0.750 BIT STOP CHARACTER
0.813 BIT STOP CHARACTER
0.875 BIT STOP CHARACTER
0.938 BIT STOP CHARACTER
1.000 BIT STOP CHARACTER
1.563 BIT STOP CHARACTER
1.625 BIT STOP CHARACTER
1.688 BIT STOP CHARACTER
1.750 BIT STOP CHARACTER
1.813 BIT STOP CHARACTER
1.875 BIT STOP CHARACTER
1.938 BIT STOP CHARACTER
2.000 BIT STOP CHARACTER

BIT 0-3

• ADD.5 BIT FOR 5 BITS
PER CHARACTER OPERATION

Figure C-2

2681 DUART: Mode Register 2
(MR2) (Channel A and B)

C-2

SRA ADDRESS
SRB ADDRESS

B7F1 H (RD)
B7F9H (RD)

RECEIVE
BREAK

FRAME
ERROR

PARITY
ERROR

OVER
RUN
ERROR

Tx
EMT

Tx
ROY

FFULL

Rx
ROY

(BAD7 H)..
4t------------------.~ (BADO H)

BIT VALUES

BIT 7

0
1

BIT 6

0
1

BIT 5

0
1

NO BREAK DETECTED
RECEIVE BREAK DETECTED
NO ERROR
FRAMING ERROR
NO ERROR
PARITY ERROR

BIT4

NO ERROR
OVERRUN ERROR

BIT 3

Tx NOT EMPTY
Tx HOLDING AND SHIFT REGISTERS EMPTY

1
BIT 2

0
1

BIT 1

0
1

BITO

Tx HOLDING REGISTER FULL
Tx HOLDING REGISTER EMPTY
Rx FIFO NOT FULL
Rx FIFO FULL
NO Rx DATA WAITING
Rx DATA IN FIFO
MA-0678-84

Figure C-3

2681 DUART: Status Register
(SR) (Channel A and B)

C-3

B7Fl H (WR)
B7F9H (WR)

DCSRA ADDRESS
DCSRB ADDRESS
07

06
I

05
I

RECEIVER CLOCK SELECT

00
I

TRANSMITIER CLOCK SELECT
I

(BAD7 H) ...._-----------------_~~ (BADO H)

BIT VALUES
BIT 0-3
OR 4-7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1101
1110
1110
1110
1110
1111
1111
1111
1111

BAUD RATE SET 1
50
110
134.5
200
300
600
1200
1050
2400
4800
7200
9600
38.4K
IP4-16X(RxCA)
IP6-16X(RxC8)
IP3-16X(TxCAI
I P5-16X(TxCB)
I P4-1 X( RxCA)
IP6-1 X(RxCB)
IP3-1X(TxCAI
I P5-1 X(TxCB)

BAUD RATE SET 2
75
110
134.5
150
300
600
1200
2000
2400
4800
1800
9600
19.2K
IP4-16X(RxCAI
IP6-16X(RxCBI
IP3-16X(TxCA)
I P5-16X(TxCB)
IP4-1 X(RxCAI
IP6-1 X(RxCB)
IP3-1 X(TxCAI
IP5-1X(TxCB)

NOTES:
1. RxC AND TxC ARE ALWAYS 16X EXCEPT FOR 1111 CONDITION.
2. SET SELECTION MADE BY ACR BIT 7.
MA_0679_84

Figure C-4

2681 DUART: Data Clock
Selection Register (DCSR)
(Channel A and B)

C-4

CRA ADDRESS
CRB ADDRESS

B7F2H(WRI
B7FAH(WRI

NOT
USED

MISC COMMANDS

DISABLE
Tx

ENABLE
Tx

DISABLE
Rx

ENABLE
Rx

I - - - - - - - - - - - - - - - - - - -•• (BADO H)

(BAD7 H) .....

BIT VALUES

BIT 7

ALWAYS 0

BIT 4-6

000
001
010
011
100
101
110
111
0

NOT USED
RESET MODE REGISTER (MR) POINTER
RESET Rx
RESET Tx
RESET ERROR STATUS
RESET CHANNEL BREAK CHANGE INTERRUPT
START BREAK
STOP BREAK
NO COMMAND
TERMINATE Tx AND RESET TxRDY AND TxEMT
STATUS BITS

BIT 2

0
1

DISABLE Tx
ENABLE Tx

BIT 1

0
1

NO COMMAND
TERMINATE Rx IMMEDIATELY

BITO

DISABLE Rx
ENABLE Rx

BIT 3

MA·0680-84

Figure C-5

RDRA ADDRESS
RDRB ADDRESS
TDRA ADDRESS
TDRB ADDRESS

2681 DUART: Com~and Register
(CR) (Channel A and B)

B7F3H(RDI
B7FBH(RDI
B7F3H(WRI
B7FBH(WRI
05

I - - - - - - - - - - - - - - - - - - -•• (BADO H)

(BAD7 H).....

BIT VALUES
BIT 0-7

DATA RECEIVED FROM HOST (RDRA)
DATA RECEIVED FROM PRINTER (RDRB)
DATA TO TRANSMIT TO HOST (TDRA)
DATA TO TRANSMIT TO PRINTER (TDRB)
MA-06B1-B4

Figure C-6

2681 DUART: Receive/Transmit
Data Registers (RDR/TDR)
(Channel A and B)

C-5

leR ADDRESS

B7F4H(RD)

DELTA
IP3

DELTA
IP2

DELTA
IP1

DELTA
IPO

IP3

IP2

IP1

IPO

(BAD7H)~~~----------------------------------~~.(BADOH)

BIT VALUES
BIT 7

NO CHANGE OF STATE DETECTED AT IP3
CHANGE OF STATE DETECTED AT IP3

BIT6

0
1

NO CHANGE OF STATE DETECTED AT IP2
CHANGE OF STATE DETECTED AT IP2

BIT5

NO CHANGE OF STATE DETECTED AT IP1
CHANGE OF STATE DETECTED AT IP1

BIT4

0
1

NO CHANGE OF STATE DETECTED AT IPO
CHANGE OF STATE DETECTED AT IPO

BIT 3

0/1

CURRENT STATE OF IP3 (TVB)

BIT 2

0/1

CURRENT STATE OF IP2 (SPD IND)

BIT 1

0/1

CURRENT STATE OF IP1 (DSR)

BITO

0/1

CURRENT STATE OF IPO (CTS)
MA·oa82·84

Figure C-7

2681 DUART: Input Change
Reg i ster (ICR)

C-6

ACR ADDRESS

B7F4H(WR)

BAUD
SET
SEl

COUNTER/TIMER
MODE AND SOURCE
I
I

03
DELTA
IP3
INT

02
DELTA
IP2
INT

DELTA
IPI
INT

DELTA
IPO
INIT

I - - - - - - - - - - - - - - - - - - - - - i•• (BADO H)

(BAD7 H) ....

BIT VALUES
BIT 7

a
1

BIT 4-6

000
001
010
011
100
101
110
111

SELECT BAUD RATE SET 1
SELECT BAUD RATE SET 2
COUNTER MODE - EXTERNAL (IP2) SOURCE
COUNTER MODE - TxCA AT 1 X CLOCK OF
CHANNEL A Tx
COUNTER MODE - TxCB AT IX CLOCK OF
CHANNEL B Tx
COUNTER MODE - CRYSTAL OR EXTERNAL
CLOCK (ClK) DIVIDED BY 16
TIMER MODE - EXTERNAL (IP2) SOURCE
TIMER MODE - EXTERNAL (IP2) SOURCE
DIVIDED BY 16
TIMER MODE - CRYSTAL OR EXTERNAL (ClK)
SOURCE
TIMER MODE - CRYSTAL OR EXTERNAL (ClK)
SOURCE DIVIDED BY 16

BIT 3

NO INTERRUPT ON CHANGE OF STATE
SET ISR BIT 7 ON DETECT OF CHANGE OF
STATE AT IP3

BIT 2

NO INTERRUPT ON CHANGE OF STATE
SET ISR BIT 7 ON DETECT OF CHANGE OF
STATE AT IP2

BIT 1

NO INTERRUPT ON CHANGE OF STATE
SET ISR BIT 7 ON DETECT OF CHANGE OF
STATE AT IPI

BITO

NO INTERRUPT ON CHANGE OF STATE
SET ISR BIT 7 ON DETECT OF CHANGE OF
STATE AT IPO
MA·0683-84

Figure C-8

2681 DUART: Auxiliary Control
Register (ACR)

C-7

ISR ADDRESS
07

INPUT
PORT
CHANGE

DELTA
BREAK
B

B7F5H (RD)
05

CNTR
READY

DELTA
BREAK
A

RxRDY/
FFULLB

TxRDYB

RxRDY/
TxRDYA
FFULLA

(BAD7 H) ....I---------------------I~~(BADO H)
BIT VALUES

BIT 7

0
1

NO INTERRUPT
INPUT PORT CHANGE OF STATE DETECTED

BIT 6

0
1

NO INTERRUPT
CHANGE IN BREAK STATE DETECTED (CH. B)

BIT 5

0
1

NO INTERRUPT
RxRDY/FFULL CONDITION (CH B)

BIT 4

0
1

NO INTERRUPT
TxRDY CONDITION (CH. B)

BIT 3

0
1

NO INTERRUPT
COUNTER READY CONDITION

BIT 2

0
1

NO INTERRUPT
CHANGE IN BREAK STATE DETECTED (CH A)

BIT 1

0
1

NO INTERRUPT
RxRDY/FFULL CONDITION (CH. A)

BITO

NO INTERRUPT
TxRDY CONDITION (CH. A)
MA-0684.84

2681 DUART: Interrupt Status
Register (ISR)

Figure C-9

IMR ADDRESS

B7F5H (WR)

INPUT
PORT
CHANGE

DELTA
BREAK
B

RxRDY/
FFULLB

CNTR
READY

DELTA
BREAK
A

RxRDY/
FFULLA

TxRDYB

TxRDYA

(BAD7H) ..
41-------------------~~~(BADOH)

BIT VALUES

BIT 7

INTERRUPT DISABLED
INPUT PORT CHANGE OF STATE INTERRUPT
ENABLED

BIT6

INTERRUPT DISABLED
CHANGE IN BREAK STATE INTERRUPT ENABLED
(CH. B)

BIT 5

0
1

INTERRUPT DISABLED
RxRDY/FFULL INTERRUPT ENABLED (CH. B)

BIT4

0
1

INTERRUPT DISABLED
TxRDY INTERRUPT ENABLED (CH. B)

BIT 3

0
1

INTERRUPT DISABLED
COUNTER READY INTERRUPT ENABLED

BIT 2

INTERRUPT DISABLED
CHANGE IN BREAK STATE INHRRUPT ENABLED
(CH. A)

BIT 1

0
1

INTERRUPT DISABLED
RxRDY/FFULL INTERRUPT ENABLED (CH. A)

BIT 0

0
1

INTERRUPT DISABLED
TxRDY INTERRUPT ENABLED (CH. A)
MA·06SS84

Figure C-10

2681 DUART: Interrupt Mask
Reg i ster (IMR)
C-8

CTUR ADDRESS
CTlR ADDRESS
07

B7F6H (RD)/B7F6H (WR)
B7F7H (RD)/B7F7H (WR)
05

: I

(BAD7 H)"~I-------------------." (BADO H)

BIT VALUES

BIT 0-7

LEAST SIGNIFICANT BYTE OF COUNTER OR TIMER MODE
(CTLR)
MOST SIGNIFICANT BYTE OF COUNTER OR TIMER MODE
(CTUR)

Figure C-11

IPR ADDRESS

2681 DUART: Counter Timer/Upper
(CTUR) and Lower (CTLR) Registers

B7FDH (RD)

I ~,~~ I

IP6

IP5

IP4

IP3

IP2

IPl

IPO

(BAD7 H)~

.. (BADO H)

BIT VALUES

BIT 6

0/1

(NOT USED)

BIT 5

0/1

CURRENT STATE OF IP5 (DTR DSR)

BIT 4

0/1

CURRENT STATE OF IP4 (TBLK)

BIT 3

0/1

CURRENT STATE OF IP3 (TVB)

BIT 2

0/1

CURRENT STATE OF IP2 (SPD IND)

BIT 1

0/1

CURRENT STATE OF IPl (DSR)

BIT 0

0/1

CURRENT STATE OF IPO (CTS)

Figure C-12

2681 DUART: Input Port
Register (IPR)

C-9

B7FDH (WR)

OPCR ADDRESS

OP7

OP6

OP5

OP4

OP2

OP1

OPO

•

(BAD7 H)"

(BADO H)

BIT VALUES

BIT 7

COMPLIMENT OP7 FOR DIS VIDEO H TRUE.
COMPLIMENT OP7 FOR DIS VIDEO H FALSE.

BIT 6

COMPLIMENT OP6 FOR BNKS1 H TRUE.
COMPLIMENT OP6 FOR BNKS1 H FALSE.

1
BIT 5

COMPLIMENT OP5 FOR BNKSO H TRUE.
COMPLIMENT OP5 FOR BNKSO H FALSE.

BIT4

COMPLIMENT OP4 FOR 132 COL H TRUE.
COMPLIMENT OP4 FOR 132 COL H FALSE.

BIT 3

COMPLIMENT OP3 FOR BLINK H TRUE.
COMPLIMENT OP3 FOR BLINK H FALSE

BIT 2

COMPLIMENT OP2 FOR SPO SEL H TRUE.
COMPLIMENT OP2 FOR SPO SEL H FALSE.

BIT 1

COMPLIMENT OP1 FOR DTR H TRUE
COMPLIMENT OP1 FOR DTR H FALSE.

BITO

COMPLIMENT OPO FOR RTS H TRUE.
COMPLIMENT OPO FOR RTS H FALSE.
MA-06B8-B4

Figure C-13

2681 DUART: Output Port
Configuration Register (OPCR)

17COH (WR)

ADDRESS
07

I-----------------......,•• (BADO H)

(BAD7 H) ....

BIT VALUES

BIT 0-7

BINARY DEFINITION OF NUMBER OF CHARACTER
TIMES PER HORIZONTAL PERIOD (TRACE AND
RETRACE).
NOTE:
VALUE STORED IN CHARACTERS PER DATA
ROW REGISTER SUBTRACTED FROM ABOVE
VALUE DEFINES CHARACTER TIMES IN
RETRACE PERIOD.
MA-D689-B4

Figure C-14

9~~7 VPAC: Characters Per
Horizontal Period Register

C-1~

17C1 H (WR)

ADDRESS
07

(BAD7 H) ......- - - - - - - - - - - - - - - - - -... (BADO H)

BIT VALUES

BIT 0-7

BINARY DEFINITION OF NUMBER OF CHARACTER
TIMES PER DATA ROW, LESS ONE (4FH, FOR
BO COLUMN, OR B3H FOR 132 COLUMN).

4FH
OR
B3H

NOTE:
THIS REGISTER VALUE SUBTRACTED FROM
CHARACTERS PER HORIZONTAL RETRACE
REGISTER VALUE DEFINES CHARACTER TIMES
IN HORIZONTAL RETRACE PERIOD.
MA-D69Q.84

9007 VPAC: Characters Per
Data Row Register

Figure C-lS

17C2H (WR)

ADDRESS

_ - - - - - - - - - - - - - - - - - - I..~ (BADO H)

(BAD7 H) .......

BIT VALUES

BIT 0-7

BINARY DEFINITION OF NUMBER OFCHARACTER
TIMES FROM LEADING EDGE OF HORIZ SYNC L
TO LEADING EDGE OF VLT H.
MA·0691·84

Figure C-16

9007 VPAC: Horizontal Sync
Delay Register

C-ll

ADDRESS
07

17C3H (WR)
04

. :0' ,"":m' "M:'

(BAD7 H).

•

(BADO H)

BIT VALUES

BIT 0--7

BINARY DEFINITION OF NUMBER OF CHARACTER
TIMES IN HORIZONTAL SYNC WIDTH
MA_069:z,.84

9007 VPAC: Horizontal Sync
width Register

Figure C-l7

17C4H (WR)

ADDRESS
07

(BAD7 H)'....- - - - - - - - - - - - - - - - -..... (BADO H)

BIT VALUES

BIT 0--7

BINARY DEFINITION OF NUMBER OF
HORIZONTAL PERIODS IN THE VERTICAL SYNC
WIDTH.
MA-0693-84

9007 VPAC: vertical Sync
width Register

Figure C-l8

ADDRESS
07

17C5H (WR)
06

•7"0'"0;' ' ""~O'

: I

.. (BADO H)

(BAD7 H).

BIT VALUES
BIT 0--7

BINARY DEFINITION OF NUMBER OF
HORIZONTAL PERIODS. MINUS ONE. FROM
LEADING EDGE OF VERT SYNC L TO LEADING
EDGE OF VLT H (FOR THE FIRST SCAN LINE OF
FIRST DATA ROW).
MA-0694-84

Figure C-l9

9007 VPAC: vertical Sync
Delay Register

C-12

17C6H (WR)

ADDRESS

04
I

PIN
CONFIGURATION

CURSOR SKEW

00
I

BLANK SCEW
I

(BAD7 H) ....I--------I-------------I.~ (BADO H)

BIT VALUES
BIT 6-7

DEFINES PINS AS SC3H (28). SC2H (29).
SC1 H (30). SCOH (31). CSYNC L (32). AND
DMA H (33).
NOT USED IN VT220.
NOT USED IN VT220.
NOT USED IN VT220.

01
10
11
BIT 3-5

VALUE OTHER THAN 0 USED DURING
HORIZONTAL RETRACE TO INDICATE START OF
DOUBLE WIDTH OR DOUBLE HEIGHT DATA NOW
(VALUE NOT USED IN VT220 DURING
HORIZONTAL TRACE PERIOD).

BIT 0-2

BINARY DEFINITION OF NUMBER OF CHARACTER
CLOCKS (0 TO 5) THAT DELAY HORIZONTAL
BLANKING PORTIONS OF CBLANK H WITH
RESPECT TO THE DEASSERTEDVLTH INTERVAL.
MA-0695-84

Figure C-29

17C7H (WR)

ADDRESS
07

9997 VPAC: Configuration/Skew
Register

I - - - - - - - - - - - - - - - - - - -... (BADO H)

(BAD7 H) ....

BIT VALUES

BIT 0-7

17H

BINARY DEFINITION OF NUMBER OF VISIBLE
DATA ROWS DISPLAYED DURING EACH
VERTICAL TRACE (17H CODE FOR 24 DATA
ROWS)
MA·0696-B4

Figure C-21

9997 VPAC: Data Rows
Per Frame Register

C-13

17C8H (WR)

ADDRESS
07

(BAD7 H) ....._ - - - - - - - - - - - - - - - - - -•• (BADO H)

BIT VALUES

BIT 0--4

BINARY DEFINITION OF NUMBER OF SCAN LINES,
MINUS ONE, IN EACH DATA ROW (SH for
10 SCAN LINES).

NOTE:
BITS 5 THROUGH 7 ARE USED AS 3 MSBs OF
SCAN LINES PER VERTICAL PERIOD REGISTER
AND ARE WRITTEN TO AT SAME TIME AND
ADDRESS AS BITS 0-4 ABOVE.
MA-0697-84

Figure C-22

17C8H (WR, 3 MSB'sl
17C9H (WR, LOW BYTE)

ADDRESS
ADDRESS
07

9007 VPAC: Scan Lines
Per Data Row Register

:
15

BIT
10

BIT
9

BIT
8

,:'" "":'

(BAD7 HI"

I
08

• (BADO H)

BIT VALUES

BIT 0-10

BINARY DEFINITION OF NUMBER OF SCAN LINES IN
ENTIRE VERTICAL PERIOD (TRACE AND RETRACE).

NOTES'
1. VERTICAL BLANKING PERIOD IS DEFINED BY
SUBTRACTING THE TOTAL NUMBER OF SCAN
LINES PER VERTICAL TRACE (VALUE OF DATA
ROWS PER FRAME REGISTER X VALUE OF
SCAN LINES PER DATA ROW) FROM ABOVE
VALUE
2

FIVE LSBs OF HIGH BYTE ARE USED AS SCAN
LINES PER DATA ROW REGISTER
(REF FIGURE C-22)
MA-0698-84

Figure C-23

9007 VPAC: Scan Lines
Per vertical Period Register

C-14

ADDRESS

17CBH (WR)

NOT
USED

SCROLL
OR
BLANK

05
I

OPERATING
MODE

INTERLACE
MODE
I

01
I

CURS
HEIGHT

(BADl H)..
4 - - - - - - - - - - - - - - - - - - -•• (BADO H)

BIT VALUES

BIT 6

BIT 4-5

ENABLE SMOOTH SCROLL FOR SELECTED DATA
ROWS.
ASSERT CBLANK H FOR SELECTED DATA ROWS.

NON·INTERLACED MODE
NOT USED IN VT220
NOT USED IN VT220
NOT USED IN VT220

01
10
11
BIT 1-3

000

REPETITIVE ADDRESSING MODE (NO OTHER
CODES USED IN VT220).

BIT 0

DOUBLE HEIGHT CURSOR ON DOUBLE HEIGHT
ROW. SINGLE HEIGHT ON SINGLE HEIGHT ROW
SINGLE HEIGHT ON SINGLE HEIGHT ROW.
SINGLE HEIGHT ON TOP OF HALF OF DOUBLE
HEIGHT ROW.
MA-0699-84

Figure C-24

ADDRESS
ADDRESS

9007 VPAC: Control Register

1 7CCH (WR. LOW BYTE)
17CDH (WR. HIGH BYTE)

(BADlH) ..
4~-----------------~•• (BADOH)

BIT VALUES

BIT 14-15

00
01
10
11

SEQUENTIAL ADDRESSING MODE
NOT USED IN VT220
NOT USED IN VT220
NOT USED IN VT220

BIT 0-13

BINARY DEFINITIONS OF FIRST ADDRESS OF
THE ROW TABLE STORED IN RAM.
MA-07QO..84

Figure C-2S

9007 VPAC: Table Address Register

C-lS

17CFH (WR)

ADDRESS

,,,..:.,,"
SI~E

I - - - - - - - - - - - - - - - - - - - - - I... IBADO H)

IBAD7 H) .....

BIT VALUES

BIT 6-7

SINGLE HEIGHT/SINGLE WIDTH
SINGLE HEIGHT/DOUBLE WIDTH
ODD DATA ROWS ARE DOUBLE HEIGHT/
DOUBLE WIDTH ON TOP HALF. EVEN DATA
ROWS DOUBLE HEIGHT/DOUBLE WIDTH ON
BOnOM HALF.
EVEN DATA ROWS ARE DOUBLE HEIGHT/
DOUBLE WIDTH ON TOP HALF. ODD DATA
ROWS ARE DOUBLE HEIGHT/DOUBLE WIDTH
ON BOnOM HALF.

01
10

Figure C-26

1701 H (WR)

ADDRESS

9007 VPAC: Row Attribute Register

IBAD7 H) .....t _ - - - - - - - - - - - - - - - - - - I•• IBADO H)

BIT VALUES
BIT 0-7

BINARY DEFINITION OF FIRST DATA ROW
NUMBER TO BE AFFECTED BY SMOOTH SCROLL
OR BLANK OPERATION.
NOTE
TYPE OF OPERATION IS DEFINED BY BIT 6
OF CONTROL REGISTER.
MA·Q702·84

Figure C-27

9007 VPAC: Data Row Start Register

C-16

17D2H (WR)

ADDRESS

~ (BADO H)

(BAD7 H) ..

BIT VALUES

BIT 0-7

BINARY DEFINITION OF LAST DATA ROW
NUMBER TO BE AFFECTED BY SMOOTH SCROLL
OR BLANK OPERATION.
NOTE
TYPE OF OPERATION IS DEFINED BY BIT 6
OF CONTROL REGISTER.
MA·0707-B4

Figure C-28

17D7H (WR)

ADDRESS
07

9007 VPAC: Data Row End Register

(BAD7 H) .....I-----------------~~~(BADO H)

BIT VALUES
BIT 0-7

Figure C-29

BINARY DEFINITION OF NUMBER OF SCAN LINES
PER DATA ROW; USED TO OFFSET SCREEN ON
EACH VERTICAL SCAN BY ONE DATA ROW
WHEN BIT 6 OF CONTROL REGISTER IS SET.

9007 VPAC: Smooth Scroll
Offset Register

C-17

17D8H (WR, VERTICAL)
17D9H (WR, HORIZONTAL)
17F8H (RD, VERTICAL)
17F9H (RD, HORIZONTAL)

ADDRESS
ADDRESS
ADDRESS
ADDRESS
07

(BAD7 H)I ..........-----------------.~ (BADO H)

BIT VALUES

BIT 0--7

BINARY DEFINITION OF DATA ROW (VERTICAL
CURSOR REGISTER) OR COLUMN NUMBER
(HORIZONTAL CURSOR REGISTER) OF THE
CURSOR.
MA-0709-84

Figure C-30

ADDRESS
07

9007 VPAC: Vertical/Horizontal
Cursor Registers

17FAH (RD)
06

INTR
FLAG

I
VERT
RETRACE

FRAME
TIMER

(NOT USED)
I

(BAD7 H) .....I--------------------.~ (BADO H)

BIT VALUES

BIT 7

NO OTHER STATUS BIT SET.
OTHER STATUS BIT SET.

BIT 6

NO VERTICAL RETRACE IN PROGRESS.
VERTICAL RETRACE IN PROGRESS.
NOT USED

BIT 1-5
BIT 0

o
1

FINAL TABLE ADDRESS NOT READ.
FINAL TABLE ADDRESS READ.
MA-071Q-B4

Figure C-3l

9007 VPAC: Status Register

C-l8

· Digital Equipment Corporation. Maynard, MA 01754