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Document:	KMC11 General Purpose Microprocessor User's Manual
Order Number:	EK-KMC11-OP
Revision:	PRE
Pages:	100
Original Filename:

OCR Text

KMC11 general purpose
microprocessor

user's manual

EK-KMC11-OP-PRE

KMC11 general purpose
microprocessor

user’'s manual

digital equipment corporation - maynard, massachusetts

Preliminary Edition May 1977

Copyright © 1977 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP
RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11

UNIBUS

CONTENTS

CHAPTER

INTRODUCTION

1.1

SCOPE

1.2

GENERAL

DESCRIPTION

KMC11-A

MICROPROCESSOR

CHAPTER

INSTALLATION

2.1

SCOPE

2.2

UNPACKING

2.3

OPTION

2.4

MECHANICAL

2.5

PRE-INSTALLATION

2.5.1

General

2.5.2

Pre-Installation

2.6

INSTALLATION

2.7

DEVICE

2.7.1

Introduction

2.7.2

Floating

2.7.3

Device

Address

2.8

VECTOR

ADDRESSES

2.8.1

Introduction

2.8.2

Floating

2.8.3

Vector

2.9

INSTALLATION

AND

INSPECTION

DESIGNATIONS
PACKAGING
PROCEDURES

Information

Checkout

Procedures

2-12

ADDRESSES

2-12

Device

Address

Assignments

Selection

2-12

2-15
2-18
2-18

Vector

Address

Address
Selection

CHECKLIST
e

Assignment

2-18
2-19

CHAPTER

UNIBUS

CONTROL

AND

STATUS

3.1

INTRODUCTION

3.2

BSEILL,

CHAPTER

MICROPROCESSOR

REGISTERS

MAINTENANCE

CONTROL

STATUS

AND

4.1

INTRODUCTION

4,2

OUT

BUS*/IN

BUS*

4.3

NPR

CONTROL

4.4

MICROPROCESSOR

3-1

REGISTERS

4-1
REGISTERS

0-7

4-2

MISCELLANEOUS

4-8

4.5

NPR

BUS

ADDRESS

AND

DATA

REGISTERS

4-10

CHAPTER

MICROINSTRUCTION
PROGRAMMING

FORMATS

AND

INFORMATION

SCOPE
MICROINSTRUCTION

Branch
Move

Microinstruction
SAMPLE

Programming

KMC11-A
DMC11

ADDRESSING

PROGRAMMING

Samples

for

Accessing

CSRs

Microcode

APPENDIX

FORMATS

Microinstruction

KMC11-A

the

WORD

Programming

PROGRAMMING

LINE

PDP11

UNIT

MEMORY

CONVENTIONS

Samples

NOTES

PROGRAMMING

NOTES

ORGANIZATION

AND

CHAPTER

INTRODUCTION

1.1

SCOPE

This

manual

operate

the

five

KMC11-A

chapters

the

information

General
and

one

Purpose

Chapter 1

Introduction.

Chapter

Installation.

Chapter

Unibus

Chapter

Microprocessor

Chapter

Microinstruction

Control

necessary

install

Microprocessor.

appendix

into

provides

and

organized

follows:

Status

Control

Registers

and

Status

Registers.

Formats

and

Programming

Organization

and

Addressing

Information.

Apeendix

PDP

Memory

Conventions.

1.2

The

GENERAL

KMC11-A

DESCRIPTION

(Module

M8204)

KMC11-A

MICROPROCESSOR

Unibus

compatible

general

purpose

microprocessor with writeable control storage. It is used primarily
to

reduce

hence,

the

input/output

KMC11

functions

load

the

KMC11

CPU

data

PDP-11

handler

system;

than

data

processor.

The

functions

performed

microprogram

contained

does

The

the

KMC11

not

stand

by
in

its

allow

alone

are

instruction

device

modify

and

can

determined
memory.

its

own

The

the
architecture

instruction

programmed

area.

the

user
a

DMC11

perform

appropriate

Synchronous

line

Line

unit

Unit.

control

the

Digital

Data Communications

protocols.

There

local

unit

(M8202)

cables

local

are

for

two

network

The

interconnects

applications.

interconnects

common

carrier

facilities.

There

unit;

however,

the

version

programming.

These

M bps

four

Table

Line

Unit

remote

options

1-1

DMC11

can

Protocol

versions

which

KMC11

can

The

are

two

are

the

Unit

Table

for

DMC11-MA

Coaxial

Mbps*

Integral

Local

(6000

DMC11-MD

Coaxial

unit

Kbps

Integral

non-Digital

Bell

(18,000 ft. max)

DMC11-DA

RS-232-C

Remote

CC1TT V.24

Kbps

19.2

208,209,

eguivalent

and

line

max)

Cable

the

coaxial

Options

Modem

Local

1-1.

Speed

ft.

each

Interface

Cable

One

remote

stuff

via modems

recommended
in

with

DEC's

or bit

computers

variations

not

used

unit.

computers

listed

Line

line

other

PDP-11

such

(DDCMP)

the

PDP-11

also

microprogrammed

type protocols

Message

(M8201)

The

KMC11

character

basic

which

task.

Table

Line

Unit

DMC11-FA

1-1

DMC11

Line

Unit

Interface

Speed

CC1TT

V.35

Remote

Options

(Cont)

Modem

250

GTE/Lenkurt

Kbps

L500Aa-5,

WECO

(Bell)

500A

L1/5,

equivalent

modem

the

used

oOn

Digital

Data

service
*Not

The

recommended

KMC11

control
memory

1is

storage
and

shown

non-DEC

programming

enchanced

version

place

provisions

relinquishing
are

for

Unibus
Table

Table

time

complete

Main

1-2

for

instruction

Memory

ROMs.

The

performing

mastership.

DMC11

KMC11

with

has

consecutive

Comparative

writeable

increased
NPRs

main

without

KMC11/DMC11

specifications

1-2.

Function

Cycle

for

the

KMC11/DMC11

Comparative

Specifications

DMC11

KMC11-A

(M8200)

(M8204)

300ns

orx

330ns

1if

330ns

multiport

access

256

bytes

1-2

Table

Scratch

KMC11/DMC11

Pad

Instruction

length

Comparative

Specifications

(Cont)

bytes

bits

words

N/A

Control

ROM

Control

RAM

N/A

words

bits

Data

paths

NPR

address

bits

bytes

Interrupt

Vectors

CSR

microcode

(RAM)

bits

defined

ALU

functions

NPR

data

byte

word

byte

word

CSR

transfers

byte

word

byte

word

(use

NPR

transfers

Program

timer

Multiple

NPRs

1.0

second

yes

Control

/=4

bit

Table

MAR

load

CSR

Sel

(WRITE

1-2

KMC11/DMC11

Comparative

high

bit

Specifications

ves

yes

hex

(Cont)

CRAM)

functional)

Assert

I/0

DMC11

Line

Unit

compatible

MAR

and

status

bits

Module

size

Voltage/current

Figure

The

1-1

KMC11

device

shows

typical

microcoded

the

flag

pointer

and

program

the

device

via

NPRs

device

~combining

+5Vv

character
KMC11.

service

that

count
The

initiated

is,

field

data
by

microcoded

the

converted
with

+5V

KMC11/peripheral

mode;

high

device

normally

interrupts
are

moved

KMC11.

throughput
KMC11.

/=5

configuration.

interrupt-driven
turned

transfered

then

off.

from

to/from

effect,

block

the
the

buffer
PDP11

peripheral

character-by-character

transfer

device

> PERIPHERAL

———— - |

DEVICE

: NPRS
e

~ | #mcr /o

(/<
N

1> PROCESSOR

— — —

5 I NPRS

> |————= | ppp-y
<‘],

> MEMORY

POP-1/

> PROCESSOR

Figure

1-1

KMC11-A

I/0

Microprocessor

Figure
Local

1-2

shows

stations

" half-duplex

Remote

stations

1=4

located

the

two

typical

are

cables

Line

single

for

KMC11/DMC11

interconnected

simplified

basic

interfaces

cable.

The

self-contained
load

the

The

KMC11

processor

between

with

KMC11

the

via

Unit

coaxial

full-duplex

application.
cable

forx

operation.

Remote

Line

Unit application.

modems

that

use

performs

request

diagram

elements

the

Unibus

device

interfaces

micro-program

PDP-11

transactions.

block

controlling

functionally

port

foot

Local

common

facilities.

shows

T/0

shows

KMC11/DMC11

interconnected

operation

1~3

Figure

typical

are

Figure

carrier

Processor

direct

(NPR)

the

and

(line

and

fast

operating

reduced

transactions.
between

Microprocessor.

KMC11

and

I/0

port.

unit,

the

access

KME11

its

with

memory

Communications

etc)

Unibus

how
The

through

and,

KMC11

because

speed,

the

1is

one
of

its

input/output

significantly.

(DMA)

also

the

operations

performs

PDP-11

using

hon

interrupt

Processor

and

the

microprocessor's Unibus Control and Status Registers (CSRS) is done
through

data

out

byte

The

data

major
1.

(DATI)

transactions

(DATOB)

functional

transactions

areas

of
and

Main

Memory

(MEM)

main

memory

that

KMC11

used

for

executed

the

data

reading

for

KMC11

Memory

1024

instruction
as

for

and

data

out

(DATO)

writing.

Microprocessor

Address

are:
(MAR)

word-by-8

bit

random

storage

area.

This

area

cannot

the

stored

data

storage

instruction.

nor

can

access

The

memory

be
be

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AFTASONYTONS5
026W)(&

OSIIW STO I0NHY

/10

0DL/|0IO/W4oOI1O)D2/S
<

)

S|V3I/XqVOID

“

IN/T

D=~

/-8

DUV

08 ¥0SST

FLOWTY

(r028W)

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/1IN

—

AV %

=T —~Q>v

UN/BUS

PROGRAM |

DATA

COUNTER

OATH

CRAM

FUNCT7/ON

SOURCE

ROM

DESTINATION

KOM

<W7E‘)F‘}‘f > REGISTERS </
T

UN/BUS

Figure

1-4

AND DATA

Microprocessor

Simplified

/0 FPORT

Block

Diagram

This

memory

addressed

Memory

Address

Branch

and
of

temporary

for

only
the

from
the

data

rotate

operation:

comes

(BRG)

BRG's

This

right

8-bit
for

buffered

right,

ALU

the

branch

operation.

shift

most

outputs

except

three

hold.

during

significant

bit

the

used

determination

It.has
and

modes

Input

data

shifting

sourced

from

ALU

the

when

ALU.

Output

data

goes

input

Counter,

Address

are

used

Maintenance

Multiplexer

The

address

the

(CRAM). The

program

counter

case

program

going

selects

CRAM

BRANCH,

counter

the
the

CRAM.

address

mux

program

counter

random

can

address

normal

During

loaded,

multiplexer

operation,

Unibus
the

memory

outputs

micro-program

selects

The

and

outputs

access

parallel

incremented.

During

the

Address

control

the

outputs.

verifying,

maintenance
CRAM

via

multiplexer.

Program

the

load,

the

data,

source

the

via
for

RAM,

Instruction

RAM

Data

The

/=1

and

control

Maintenance
RAM

1024

the

before

mux

addresses.

Control

the
the

=16

bit

random

micro-program
used

load

access

storage
the

outputs

wire-ORed

are

area.

CRAM

instruction

from

instruction

substituted

for

Data

Multiplexer

and

data

multiplexer

(DMUX)

Logic

Arithmetic

DMUX

read

only

Scratchpad

the

Unit

(ALU).

the

scratchpad memory

(SP)

also

presented

through

the

scratchpad

memory.

through

multiplexer.

During

(FROM)

address
the

Logic

The

0000

servicing

the

Memory

wide

the

input

for

the

32-by-8

determines

line-to-1

KMC11.

(SROM)

selection

the

1if

The
line

the

bit

move

Multiplexer

the

input

data.

the

addressing

CRAM.

The

read/write

storage

normal

the

bit

1is

operation,
During

automatically

ALU

only

done
the
output

presented

ALU.

Unit

and

arithmetic

microprocessor

that
be

temporary

controlled

Its

can

16-by-8

can

Arithmetic

for

operand

input

Unibus.

contents

Addressing

used

outputs

Only

1is

maintenance

CRAM

Input

the

The

the

goes

that

from

8-bit

memory

transfer,

the

executed.

and

data

SROM which

SROM

Memory

addressing

RAM

Read

output

The

8-bit

memory.

instruction

loaded

Source

controlled by

that

Unibus.

CRAM during

the

Its

The
the

with

maintenance

multiplexer.

memory

Function

logic

perform

unit

Read

(ALU)

arithmetic

and

Only

Memory

allows

logic

the

operations

its

read

and

only

the

connected

indication

the

FROM.

The

output

flip-flop

and

inputs.

memory,

performed
ALU

The

controls

which

ALU.

The

flip-flop

occurs

Bit)

store

inputs

FROM;

during

the

carry

the

store

move

ALU

32-by-8

functions

output

indication

ALU

Bit)
the

bit

the

carxry

forced

connected

equality

the

MOVE

occurs

during

instruction.

Multiport
RAM

RAM

and

random

Associated

access

Logic

memory

that

The

multiport

contains

all

the

KMC11 status registers exéept two. They are the NPR
Contrql

multiport

RAM

and

has

the

two

Miscellaneous

ports

and

can

accessed simultaheously for a read operation;
only

the

consists

port

written

into.

read/write

control

and

multiplexers

can

which

allow

access

the microprocessor and the PDP-11
multiport
that

are

program.

data

RAM

accessible
It

buffers

System

contains

Clock

also

microprocessor.

The
It

are

the

accessible

clock

provides

generates

however
logic

addressing
the

multiport

and

KMC11

NPR

associated

Processor.

control

both

contains

that

the

The

buffer

only

clock

series

registers

the

PDP11

pointers

the

and

KMC11.

pulses
five

The

status
and

RAM

for
non

the

overlapping
Tt

SELO

RAM

started

while
of

set.

being

the

NPR

ns
by

tries

Request

11.

and

data

Interrupt

and

from

Address

decode

this

the

a write

operation

progress

multiport

This
NPR

and

the

RAM.

logic

under

Suspension

allows

the

microprogram

can

transfer

memory.

This

logic

the

allows

PDP-11

two

the

Processor

programmable
The

space.

and

locations

vector

selectable.

priority

Logic

and

factors,

signals

ns.

the multiport

NPR

300
CSR

address

address.

in progress.

can

level

This

the microprocessor

these

directed

either

shipped

Selection

specify

control

for

operation

interrupt

selected

switch

KMC11

mastership

PDP-11

Logic

suspended

Logic

initiate

the

when

Unibus

interval

write

Control

KMC11

Using

read

time

bit

the

occurs

program when

a write

floating‘*vector

the

however,

12.

has

assume

vectoring

address

The

PDP11

operation

also

microprocessor

cause

during

accessed by

micro-processor

control

pulses
the

Its

PDP11

operation

KMC11

10.

This

type

the

implement

Unibus

control

device.

consists

switches

device

address

plus

logic

also

Unibus

logic

level

decodes

transaction

generates
read

lines.

the

write

the

requested.

appropriate
operation

CHAPTER

INSTALLATION

2.1

SCOPE

This

chapter

check

out

provides

the

KMC11

combination

UNPACKING

The

microprocessor

arrives

part

When

arrives

line

unit

and

cables

carton

the

visually

(if

device

unit

combination

site

carton

M8201

*3,

BC08S-1

one

system

of
or

option,

ordered),

the

*2.

add-on

any

signs

are

and
a

Cable

line

unit.

BC05C-25

Cable

DMC11

option

fi);;

single

the

add-on

option.

mounting

carton.

Inspect

damage.

module,
hardware
the

Included

following:
Module.

Unit

DMC11-DA

has

either

microprocessor

physical

Line

ways;

the

interconnect

for

two

associated

Microprocessor

M8202

This

alone

microprocessor/line

for

KMC11

only.

stand

and

Unit.

packaged

M8204

*4,

install

Line

computer

and

INSPECTION

arrive

DMC11

necessary

Synchronous

customer

module

contents

the

AND

complete

information

Microprocessor

with

2.2

the

Module.

microprocessor

(M8201)

EIA/CCI1TT

Line

V.24

Unit

interface.

*5.

BC05Z-25

only.

Cable

This

*6.

H325

*7.

H3250

*8.

12-12528

Test

option

Test

Data

DMC11-FA

has

Connector

DZKCC

Paths

(M8201)

CCI1TT

for

Connector

Coaxial

MAINDEC-11

and

for

V.35

DMC11-DA

for

Line

interface.

(M8201)

DMC11-FA

only.

(M8201)

Cable

Test

KMC11

Microprocessor

Static

Unit

Connector

only.

(M8202

Basic

only).

W/R

Tests.

10.

MAINDEC-11

DZKCA

KMC11

Free

Run

*11.

MAINDEC-11

DZKCE

DMC11

Line

Unit

Static

Character

DMC11

Line

Unit

Static

Bit

Protocol

*12.

*13.

DZKCF

DZKCG

Line

Unit

Free

Running

Tests

Under

Mode.

14.

MAINDEC-11

KMAA

DEC/X11

*15.

MAINDEC-11

DZKCB

ITEP

16.

Stuff

Tests.

MAINDEC-11

DDCMP

Diagnostics.

Tests.

MAINDEC-11
Protocol

Micro

EK-KMCMP-0P-001

KMC11

Module

System

for

Microprocessor

2-7

Test.

KMC11

User's

with

live

Manual.

unit.

*17.

EXK-DMCLU-0OP-001

18.

MAINDEC-11-DZKCD

Static

*Used

2.3

only

with

OPTION

The

Line

Unit

User's

Microprocessor

Manual.

CRAM

and

Branch

Tests

KMC11

Microprocessor/DMC11

Line

Unit

Table

2-1

combination.

DESIGNATIONS

microprocessor

and

designated

line

unit

KMC11-A.

options.

Table

2-2

lists

the

the
line

unit

cables.

2.4

MECHANICAL

The

KMC11

DMC11

Microprocessor

Line

modules

PACKAGING

Unit

plug

consists

into

any

consists
of

single

notched

DD11-C,

DD11-D

SPC

hex
hex

system

module.
module.

unit

The
These

equivalent

backplane. The microprocessor module must always plug into either
slot
in

any

the

DD11-C.

remaining

unit

combinations

unit

modules

into

plug

The

slots.

installed
slots

line

unit

Should
in
and

module

two

single
4.

may

installed

microprocessor/line
DD11-C,

then

the

line

Table

Microprocessor
Option

2-1

and

Line

Unit

Designations

Option

Module

Description

Prerequisite

KMC11-A

M8204

Microprocessor

PDP-11
D

DMC11-DA

M8201

Line
for

DMC11-FA

DMC11-MA

M8201

M8202-YA

unit
EIA

M8202-YD

cable

Line

unit

for

v35/DDS

interface

Line

unit

Line

unit

integral

with

cable

bps

KMC11-=A

KMC11-A

modem

with

modem

56K

bps

DD11-C,

equivalent

interface

integral

DMC11-MD

with

KMC11-A

Table

Line

Option

BCO3N-AO

Unit

2-2

Cables

Description

100

£ft.

coaxial

connectors.

Line

BC05C-25

ft.

for

BC05zZ-25

Unit

use

ft.

with

cable

with

M8202

V.24

cable

Used

Module.

EIA/CCITT
with

CCITT

DMC11-FA

DMC11-DA

V.35

Line

cable

Unit.

for

Unit.

use

The

line

unit

connectors
module
This
of

and

the

allows

the

does

the

DD11-C

cable

connector
that

not

result,

and

connectors

installed

used.
the

and

M8202

System

Interfacing

and

short

are

installed

and

BC08S-1

and

length

line

cable

Units.

and

end

fits

unit

slot

modules

connects

the

module

corner
has

over

the

2-1/2

the

removed.

end

module

connectors

are

been

the

edge

This

(approximately

that

Unibus

slots

Unibus

in.)
A

Unibus

and

interconnected

BERG

connector

module.

2.5

PRE-INSTALLATION

2.5.1

General

After

installing

device,

devices

DEC/X11

installed
DZKCD,
checked

three

DZKCA,
as

DZKCD,

can

Test

the

for

proper

and

DZKCA.

Its

checked

for

the

phases.

First

and

KMAA.

stand-alone

the

verified
this

module

stand-alone

operation

interaction
running

KMAA

running

with

the

which

other

KMC11.

microprocessor/line

checked
and

microprocessor

checked

Unibus

then

KMC11

System

Installation

done

the

DZKCC,
the

PROCEDURES

Information

should

diagnostics

are

microprocessor

one-foot

the

connectors

terminator

each

with

M8201

and

into

interface

vicinity

plugs

The

not

unit

combination

microprocessor
with

manner,
apart

diagnostics
the

from

should

physically
DZKCC,

microprocessor
the

line

unit.

1is
Next,

the line unit module is installed and operationally verified with
diagnostics

DZKCE

and

DZKCF

confidence

factor

for

the

execution

status

running
unit

both

test.

pairs,;

minimum

MAINDEC

Check

the
If

both
may

unit
the

power

supply

requires
integral

Installation

either

the

2-1/2

in.

slot

while

The

which

and

The

the

using

necessary

additional

third

verifies

station

unit

for

modem.

total

the

Refer

requires

unit

consist

involves

operational

free

identical

diagnostic

for

phase

the

line

two

The

KMC11

unit

can

DZKCB

execution

PDP-11/34

installing

the

and

requirements

the

KMC11/line

(ITEP).

the

2.9

for

one

any

slot

the

installed
an

equivalent

for

the
line

logic

and

details.

which

the

can

modules

regquires
in

the

conversion

slotfiif

microprocessor
into

The

Additionally,

level

slots,

terminator

Such

overloading.

Amperes.

paragraph

fits

backplanes.

adjacent

line

against

current

silos

input

less.

insure

approximately

+15V

the

Preinstallation

Before
must

UNIBUS

PDP-11/04

2.5.2

tested

memory

supply

microprocessor

equivalent

the

ends
be

provides

diagnostics.

the

volt

DZKCG

microprocessor

microprocessor/line
+5

also

microprocessor.

diagnostic

they

which

the

DD11-C,
backplane

DD11

are

full

hex

backplane.

DD11-D
is

that

used

Computers.

Checkout

Procedures

microprocessor

performed.

2-7

module,

the

following

functions

that

should

not

factory

the

The microprocessor
accordance

automated module

device

address must be

The microprocessor vector

address must be

accordance

2.8.

Verify

with

that

paragraph

BR5

logic.

clock

selected

2.7.

paragraph

with

testing

the microprocessor

oscillator

the

inhibit

during

removed only

field.

the

removed

jumper

This

installed.

jumper W1

M8204

Verify

priority

card

installed

in position

E74.

NOTE

Before

installing

remove

the

CA1

and

CB1

that

going

the

wire

for

the

must

Microprocessor

M8201

and M8202

Line

power

requirements.

microprocessor
wire

the

slot

that

runs

backplane
the

that

(M8201

M8202).

removal

the

unit

requires

M8204

Grant

pins

line

The

NPR

the

slot

not

remove

M8204,

going
a

between

for

M8204.

(M8204),

system

the

NPR

the

change

Grant

wire

replaced.

presents

Units

present

one

load

the

Unibus

and

the

load

the

Unibus

except

for

The local configuration(KMC11—A Microprocessor and DMC11-MA
or

DMC11-MD

PDP-11

Line

Unit)

Processor.

This

transactions
Unit

NPR

every

that

Mbps)

are

due

bus

required.
in

the

For

full

placement
high

rate

example,

duplex

nearest
of

the

requires

After

completing
2.5.2,

On
are

the

pre-installation

proceed

with

backplane,

within

Min

the

check

checkout

installation

that

following

DMC11-MA

Line

average

the

procedures
as

supply

follows:

voltages

tolerances.

Backplane

Nominal

Max

+4.75

+5.0

+5.25

C1A2

-14.25

-15.0

-15.75

C1B2

+14.25

+15.0

+15.75

c1U1

Insert

the

backplane

the

NPR

Voltage

SPS.

INSTALLATION

operating

2.6

paragraph

requires

Run

microprocessor

the

proper

slot.

diagnostics

order

module

listed

DZKC,
verify

microprocessor.

2-9

DZchgDZKCA
correct

and

KMAA

operation

the

one

DIAGNOSTIC

the

installation

NOTE

system

using

a PDP-11/04 ér other PDP-11 Processor that
does

not

switch

the

have

same

the

software
the

line

Chapter

options.

but

switch

allow

contains

the

user

switch

all

software

diagnostic

(177777),

used.

Refer

document

for

details.

appropriate

the

used

appropriate

further

all

switch

available

Check

switch

unit
2

module

switch
in

settings

accordance

INSTALLATION

the

and

with

line

jumpers

the

unit

recommendations
manual

(EK-DMC11LU-0P-001)
.

Insert

the

line

Interconnect
BC08S-1

cable

connector
male

H856

and

the

unit

and

one=-foot

female

the

J1.

module

line

connector.

designated
J2

the

which

with

unit

the

the
the

long

M8202

connectors

and

Line

Unit

each

line

Unit,
is

using

conductor

microprocessor,
M8201

backplane

microprocessor

microprocessor
On

proper

J1.

end.

unit

this
it

slot.

cable

flat

mylar

The

mating

H854

connector

designated

the

cable

DMC11-DA(M8201)
to

connect

the

cable

the

which

H325

test

connector
the

H3250

M8202,
ties

install

the

two

M8202,

check

the

line

Run

Line

unit

install

other

end

the

BC05C-=25

this

cable,

the

install

other

12-12528

soldered

that

DZKCE

Unit,

end

the

BC05Z-25

this

cable,

coaxial

test

connector

conmector.

specifications.

diagnostics

the

coaxial

are

Unit,

connector.

test

cables

Run

J1.

3-foot

within

10.

the

J1.

DMC11-FA(M8201)

connect

connector

Line

pigtails
to

the

Refer

and

the

together.

DZKCF

two

M8202.

integral
to

These

modem

the

line

verify

clock

unit

1is

manual.

correct

operation.

diagnostic

DZKCG

verify

correct

line

unit/microprocessor

operation.

11.

Remove

For

the

test

M8201,

customer

connector.

connect

the

supplied

211

BC05C-25

modem.

BC05Z-25

cable

CAUTION

The

maximum

BCO5C

For

and

allowable

length

BCO05Z

cables

the

M8202,

connect

coaxial

cables

the

for

feet.

pigtails

optional

100

the

foot

customer

BCO3N-AO0

cable.

12.

Diagnostic

between

DZKCB(ITEP)

stations

DEVICE

2.7.1

run

interconnected

Microprocessor/DMC11

2.7

can

Line

Unit

check

operation

KMC11

combinations.

ADDRESSES

Introduction

Starting

with

assigned

floating

devices

The

word

for

the

used

2.7.2

Floating

are

the

floating

maximum
a

DJ11,

new

communications

addresses.

The

devices

addresses

&are

for

current

not

assigned

production

retained.

means

number

that

addresses

are

each

communications

Address

Assignments

device

absolutely

that

can

system.

Floating

Device

device

addresses

The

floating

and

extends

are

address

assigned

space

location

starts

764000

follows:

(octal

location

760010

designations).

The

devices

o111,

the

are

bU11,

devices

DUP11,

device
of

assigned

the

LK11-A,

type

DMC11,

introduced
same

order

into

must

type:

DZ11,

DJ11,

KMC11

production.

assigned

DH11,

and

then

Multiple

contiguous

addresses.

The
a

first

modulo

address
108

new

boundary,

bus-addressable

registers.

DH11

must

has

eight

gap

modulo

type

device

contains

The

208

must
one

starting

boundary

start

four

address

because

the

the
DH11

registers.

10 g’

starting

modulo

108

boundary,

must

be left between the last address of one type device.and
the

first

left

for

address
any

device

the
on

the

list

device following it is used.
should
that

the

left

nothing

new

type

after

the

type

last

device.

that

not

gap

must

used,

the

The equivalent of a gap
device

assigned

indicate

follows.

devices

can

inserted

ahead

device

list.

additional

system,

they

devices
must

213

the

assigned

list

are

contiguously

added
after

to
the

original

other

devices

type

required

The

devices

make

following

assignments

Example:

the

already

room

example

for

DH11s,

same

for

type.

the

show

DQ11s,

typical

system may

floating

devices

DUP11,

and

760010

DJ11

gap

760020

DH11

first

address

760040

DH11

first

address

760060

DH11

gap

760070

DQ11

first

address

760100

DO11

first

address

760110

gap

760120

gap

760130

DUP11

760140

DUP11

gap

760150

LK11-

760160

DMC11

gap

760170

DZ11

gap

760200

KMC11

760210

Indicates
other

2=/
4

first

device
system.

KMC11

address

gap

first

devices

additions.

communications

Reassignment

address

KMC11s

follow.

and

2.7.3

Device

the

floating

always

PDP-11

memory

are
With

the

The

device

switch

space

switches
on

Unibus
8

(760010-764000),

PDP-11

organization

switch

associated

Selection

address

(function

selected

select

Address

and

address

the

line.

Appendix

addressing

the

(closed),
address

processor).

13-17
A

conventions.
logic

looks

and

for
2

are

shows

decoding

decoder
Bits

bits

the

Bits

3-12

(Table
on

2-3).

the

decoded

registers.

address

package

selection

located

package

are

used.

address

bit

numbers

and

the

switch

are

rocker

type

The

position

correlation

numbers

and

switches

are

shown
are

pushed

c=15

E116.

contained
All

between

Table

marked

are

the

The

one

DIP

switches

numbers

and

switch

2-3.
the

the

and

OFF

package.

The

switches

desired

position

positions

(Figure

2-1).

2—/6

Switches
Address
Vector
and

Figure

2-1

loenicalion‘. s
ck
h pa
(Shows swlc
'
|
We
and swilch sigrnacio#5)

Microprocessor Device

70 e SU/c;}@/fif cd

Table

Guide

Switch

Bit

No.

2-3

for

Setting

Switches

Select

Device

Address

Device

Address

760010

7060020

760030
760040

P T

760060

7060200

760300

760400

760500

760600

760700

761000

760070
760100

760050

762000

763000

764000

NOTES
:

means

Switch

switch

off

(open)

numbers

are

physical

respond
positions

2=17

to
in

logical
switch

the

package

Unibus.
1.

2.8

VECTOR

2.8.1

ADDRESSES

Introduction

Communications
This
for

devices

eliminates
the

the

maximum

are

assigned

necessity

number

each

floating

assigning

device

that

vector

address
can

addresses.
absolutely

used

the

system.

2.8.2
Floating

Floating

Vector

Address

vector

addresses

are

The

floating

address

and

proceeds

upward

Assignment

assigned

space
to

follows:

starts

777.

Addresses

location

300

500-534

are

resexved.

The

devices

are

KL11/bDL11-A,
DR11-A;

assigned

type:

DC11;

DP11;

DM11-A;

DN11;

DM11-BB;

DR11-C;

PA611

Reader;

PA611

Punch;

DL11-C,

DO11;

KW11-W;

DU11;

DUP11;

DZ11;

DWR70,

VTVO01;

KMC11.

any

DX11;

order

type

assignments

device

move

DJ11;

not

DH11;

GT40;

DV11,

used

£ill

the

LPS11;

LK11-A;

DT11;

VT20;

DMC11;

system,

vacancies.

address

additional

they

2.8.3

must

devices

assigned

devices

already

Vector

the

Address

Each

device

interrupt

(two

words)

which

same

implies

The

address

binary-coded,

the

vector

always

and

octal

digit

logic

represent

The

KMC11
the

the

XX0,

and

output

XX4.

For

this

the

logic

the

vector

(Table

2-4).

associated
generated

of
a

address
With

the

vector

the

system,

after

the

original

other

type

required.

address

specified

bit

bits

determines

address

bits

must

three

data

and

locations

addresses.

addresses

bits

are

the

end

digit,
0-8.

not

least

Because

specified

significant

4).

The

interrupt

(2-8)

the

PDP-11

processor

address.

BR5

logic.

interrupts

Unibus
on

all

interrupts

even-numbered

control

not

may

four

with

method

requires

seven

vector

input

system

Unibus

only

shipped

added

Reassignment

using

vector

send

interrupt

addresses:

number

end

are

that

must

(they

control

octal

type.

only

vector

contiguocusly

the

vector

constraint

Selection

further
or

are

priority
This

operation,

switch.
are

logic

generate

The

vector
the

switch

OFF

data

line;

with

associated

Unibus

2=/9

(open),

the

addresses
of

vector

of
2

significant

switches

the

form

octal

lines

digits

3-8

generated

switch

(closed),

line.

form

selected

data

bit

installed

two

addresses

state

two most

card

generates

vector

determined

the

selection

the

4is

The

vector

DIP

package

the

The

correlation

in
are

Table

The

2-4.

marked
to

selection

located

switches

pushed

2.9

address

on
the

the

and

the

package.

2-1).

vector

numbers

and

bit

numbers

positions

and

the

switch

The

switches

are

one

Only

the

rocker

address.

shown

numbers

type

and

are

position.

and

M8204

+5v

M820 1

+5V@ 3.0 A

checklist

Line

Unit

the

important

installations.

5.0A

+15v

0.03

-15v

0.31

+5v

3.0

+15v
@

0.18

-15v

0.46

concise

KMC11/DMC11

Requirements

M8204

present

(Figure

for

Power

The

contained

used

represent

KMC11

Unibus

are

CHECKLIST

items

the

OFF

E65

are

switch

The

M8202

package

desired

following

position

between

INSTALLATION

features

switches

presents

one

Unibus

loads.

2-20

Unibus

load.

The

M8201

and

M8202

Guide

Switch
Bit

for

Switch

Setting

No.

Table

2-4

Switches

Select

Vector

Address

Vector

Address

300
310

320
330

340

350

360
370

400

500

600

700

Notes:

means

switch

off

(open)

numbers

are

physical

produce

logical

the

Unibus.

Switch

2-2/

positions

switch

package

E65.

Special
ao.

Installation

Requirements

M8204

Microprocessor

Before

installing,

continuity

wire

and

CB1

the

going

change
wire

M8204

backplane

the

are

before

Grant

between
the

M8204.

pins
slot

CAT
that

system

the

M8204,

the

Local

Line

Units

replaced.

with

DMC11-MD)

closest

because

NPR

for

removal

configuration

Unibus

that

the

runs

Microprocessor

(DMC11-MA

This

that

requires

must

remove

the

must
the

high

required.

DB11-A

Bus

placed

PDP-11

rate
It

must

the

Processor

NPR
also

Repeater

transactions
be

one

placed

used.

4.,

M8204
a.

Microprocessor
Address

Switch

Selection

Address

|
(open)

Switch

Vector

Selection

Switch

No.

to respond to logical

(closed)

respond

Vector
3

Switch

OFF

(open)

Switch

(closed)
Switches

logical

on Unibus.
0

Unibus.

(E65)

Remaining

Bit

Switch OFF

Settings

(E116)

No.

Switch

to
in

2-23

Bit

produce

produce
E65

are

logical

unused.

the

Unibus.

Line

Unit

Switch

Shipped

Switch

(1)

(2)

(3)

The

Pack

All

switches

Pack

No.

All

switches

Pack

No.

The

switches

M8202)

Switch

M8202)

shown

jumpers

Figure

Jumper

No.

M8202)

Switch
on

and

Configuration

Settings

Switch
on

Settings

2-2,.

(E87

(E88

(E26

Figure

should be

M8201

and

E90

should

OFF.

M8201

and

E91

should

OFF.

M8201

and

E29

should

positioned

2-2.

configured as

shown

DMC11-DA

Switch

No.

DMC11-FA

DMC11-MA/MD

M8201

M8202

OFF

OF
F

OFF

OF F

OFF

OuUT

ouT

OUT

OuT

OUT

OuT

ouT

Jumper

No.

Not

Present

Not

Present

OuT

~IN

(FD)

(HD)

NOTES
:

Switch

pack

no.

located

E26

M8201

and

M8202.
FD

Full

Duplex

Half

Duplex

Figure

2-2
Switch

Configuration

Pack

Line

No.

2-24

Jumpers
Unit

and

E29

CHAPTER
UNIBUS

3
CONTROL

AND

3.1

INTRODUCTION

Eight

byte

the

exchange

PDP-11

sized
of

program

76XXX0

KMC11

control

and

are

Words

the

KMC11

general

CSRs

his

BSEL

Figure
for

3.2

This

which

3-1

BSEL

Microprocessor.

point

PDP-11

for

SEL

all

program

from

denotes

Byte

the

between
They

transfers
the

KMC11

information

from

for

address

0-7

and

SEL

KMC11.
the

used

the

are

Select

SEL

and

are

OUT

PDP-11

the

PDP-11

are

purpose

undefined

particular

shows

the

microprocessor.
and

can

application.

Maintenance

Unibus

Seven

programmed

The

of
by

the
the

one

exception

the

bit

eight
user

1is

CSRs

including

assignments

BSEL

exception

the

and

KMC11

information

indicated

information

(CSRs)

KMC11.

byte-sized
satisfy

the

transfer

the

are

Registers

referred

reference

between

program.

The

status

76XXX7

denotes

and

Status

KMC11-A

transfer

program

and

the

information

Control

REGISTERS

and

(BSELO-BSEL7).

The

STATUS

MAINTENANCE

contains

MASTER
should

only

CLEAR
not

maintenance

(bit
be

14).

used

for

functions,

intended

normal

with

for

the

servicing

communications

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2WHKWOY.)STHITY(T=0
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0 4

between
in

the

PDP-11

Multiport

the

KMC11

The

bit

All

bits

logic

program

RAM

for

read/write.

the

implement

assignments

are

but

and

KMC11.

imaged

the

NOTE

when

set,;

Description

STEP

This

MICROPROCESSOR

through

one

(STEP

60-ns

ROM

(ROM

MP)

INPUT

bit,

five

ROM

executing

this

When

directs

6=7

(ROM

OUTPUT

O0O)

the

When

set,

SEL

LINE

UNIT

LOOP

(LU

LOOP)

This

bit

and

the

listed

below.

descriptions.

steps

the

microprocessor

cycle,

composed

pulses.

The

RUN

cleared

before

function.

contents

microinstruction

microprocessor

SEL

write
new

the

CRAM

via

asserting
is

functions.

bit

the

modifies

the

read

with

BSEL
to

when

asserted.

locations.

and

the

write

contained

the

control

STEP

and/or

clock

should

set,

1is

interact

are

instruction

flip-flop

executed

end

Name

maintenance

the

Bit

hardware

specified

Maintenance

See

This

paths

enabling

the

into

BSEL

accomplished

reading

output

accessible

a
A

SEL

the

read

accomplished
data

for

specified

bit

PC,

i1s

CRAM

source

CRAM
SEL

flip-flop
of

the

Berg

Bit

Name

Description

(Cont)

connector

the

M8202

Line

has

specific

Unit

LINE

UNIT

LOOP

When

this

bit

connected,

internally.
level,
LU

LOOP

STEP

bit

single

set

10K

For

bps

the

data
level

with

M8201

serial

its

serial

input

This

done

level

set

data

1is

RUN

under
in

set,

the

M8202

output

TTL

logic
logic.

cleared,

diagnostic
out.

data

line

conversion

and

used,

RUN

bit

called

units

M8201

cable
is

and

this

When

the

control,

clocked

the

loop

LOOP

rate.

connector
modem

used,

LOOP).

set,

the

M8201

line

step

and

assignment

being

(LU

before

When

for

function

the

connected

KMC11

However,

user.

the

Line

installed
with

clocked

RUN
at

conversion

exercised

Unit,

the

end

set

and

10K

bps

rate

logic

and

back

the

LOOP

cable

cleared,

and

the

are

also.

For the M8202 line Unit, thé coaxial adapter
is

used

provide

the

clocked

integral

interconnect
loop

the

modemnm.

F—<

the

back.

operating

pigtail
this

speed

cables

case,

the

data

Bit

Name

STEP

LINE

Description

(Cont)

This

the

and

UNIT

(STEP

LU)

the

user.

specific

STEP

LINE

This

bit

LOOP.

unit

When

the

(ROM

i1s

STEP

Berg

assignment

M8201

used,

and

this

LU).

conjunction

with

transmitter

single

cleared,

bit

called

asserted,

this

MASTER

When

set,

CLEAR

the

bit

the

line

allows

loaded

the

stepped.

unit

also

receiver

the

SEL

set

CLEAR

microprocessor

CRAM

Bit

accomplish

initializes

both

and

the

line

unit,

bit

not

self

clearing

cleared

the

PDP11

This

and

must

The

microprocessor

RUN

flip-flop

also

cleared

BSEL

contents

procedure.

MASTER

installed.

the

into

specified

must

the

1is

the

set

for

being

(STEP

used

address

KMC11

flip=-flop

stepped.

set,

SEL

single

function

UNIT

When

line

When

Unit

However,

has

Line

WRITE

the

output

accessible

M8202

CRAM

connector
by

bit

is
by

clock

cleared.
MASTER

use

N
iyt

CLEAR.

MOVE

program.

halted

The

and

CRAM's
If

other

instruction

the
is
bits

that

Bit

Name

Description

(Cont)

sets

CLEAR

MASTER

and

clears

all

other

bits.

MASTER

CLEAR

without

status

raising

XX4).

procedure
Request

when

RUN

may

the

MASTER

BUS

The

use

hang

the

asserted
processor

KMC11-A

incorrect

Unibus
in

1is

cleared

which

clock.

required

1is

Requests

Bus

progress

1issued.

microprocessor

CLEAR,

CLEAR

the

microprocessor

cleared

the

perform

MASTER

bit

PDP11

transaction

controls

This
or

not

the

level

programmed

(XX0

should

BUS

initialization

stops
RUN

the

can

the

clock.

PDP11

set

program.

NOTE

The

PDP11

Multiport

hardware

Multiport

program

writes

RAM

the

BSEL

reads

only

the

but

RAM.

writes

only

cannot

write

hardware.

and

the

The

KMC11

Multiport

into

the

into

the

reads

and

RAM.

actual

BSEL

CHAPTER

MICROPROCESSOR

4.1

Unibus

the

8-bit

RAM

can

CSRs

bytes,
be

called

which

CSRs

they

identified

the

Data

Microprocessor

the

called

and
CSRs

are

two

additional

listed

the

OUT

and

BUS?*

128

located

bits

arranged

as
The

eight

16-bit

words.

from

two

sources.

One

microprocessor.
are

viewed

Microprocessor

which

These

are

specified

sized

hardware

category.

the

CSRs.

0-7

Specifically,

(octal).

8-bit

bytes,

registers
as

OUT

are

BUS/IN

registers

They

source

Therefore,

from

registers

registers.

byte

BUS*/IN

physically

capacity,

are

capacity

RAM

There

the

also
BUS

that

NPR

are

Control

and

the

Microprocessor

Miscellaneous

microprocessor

has

the

sized

(108)

RAM

OUTBUS*/INBUS*

(octal).,

Chapter

equivalent

are

0-7

registers.

assigned

and

REGISTERS

(BSEL1-BSEL7)

multiport
NPR

other

registers

The

STATUS

simultaneously

the

Unibus

remaining

contains

The

and

microprocessor,

are

RAM.

accessed

Unibus

these

they

described

multiport

the

when

The

AND

INTRODUCTION

The

CONTROL

OUT

addresses

BUS/IN

BUS.

convention,

under

capability

each

has

category;

result;

<+-/

six

addressing
been
that

decided
is,

undefined

OUT

byte
to

show

BUS*/IN

registers

16
BUS*

12-17

(octal)

are

listed

under

exist physically.

The

108—108

added

have

been

OUT

BUS*/IN

M8201/M8202
to

the

BUS*.

Line

OUT

These

Unit

BUS/IN

registers

device

BUS

not

registers,

category.

These

registers are physically located in the line unit. Address 108 is

The

Therefore,

The

there

are

arrangement

4, 2

OUT

These

eight

registers

microprocessor.

Note
the

that

are

not

4.3

The

They

the KMC11

Multiport

image BSEL

RAM

and

REGISTERS

are

the

0-7

Unibus

CSRs

identical

are

The

changes

state.

actually

control

viewed

REG),

(MAINT

from

described

those

into BSEL

may write

4-1.

in Figure

shown

the hardware

in Chapter

however,

only

that

gates

and

flip-flops

the

(RUN,

MASTER CLR,

etc)

affected.

NPR CONTROL

bit

BUS*

unit.

line

the

registers

the Microprocessor CSRs

BUS*/IN

nine

address.

is write only.

Silo

Out Data

the

and

same

the

use

registers

unit

read only

Silo

In Data

line

two

because

twice

listed

assignments

for

(OUT

the

BUS*/IN

NPR Control

BUS*

10)

are

described

below.

Bit

Name

Description

NPR REQUEST

This

(NPR

cleared

RQ)

been

bit

can be
by

the

set

hardware

NPR

via

the

OUT

NPR

(bit

set,

Unibus

transferred

from

NPR

(bit

transferred

the

PDP-11
data

PDP-11

NPR has

bit

requests

PDP-11

memory.

this
the

automatically

the

cleared,

from

7-2

when

When

completed.

only.

data

1is

memory.

OUT

1is
memory.

SN RN O~
g

BYTE @
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2
BYTE
T
BYTE

4+
BYTE

S
BYTE
6
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Unibys CSKs

as viewed Hon
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ouT IN GA /N GA

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/6 Registers Assigned Lo ourBusmeusTMategory

Figure

4-1

Microprocessor

Registers

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SWITCH SELECTALLE

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SWITCH SELLCTABLE

OCOR ICIR|

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CLK MOOE

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Lin PyUfiif

17 MANT

MBE0/ or
MB202 1S, ,

6 Registers Assigned Lo ouTaus/ingus (ategory

Figure 4-1

Microprocessor Reglisters

Sync

(Cont)

1NSta //@of)

Bit

Name

Description

(Cont)

NPR

data

set,

PDP-11

memory.

Bit

transferred

word/byte

selection.

For

NPR,

OUT

For

OUT

BUS/IN

data

that

BUS/IN

OUT

NPR,

BUS
is

from

OUT

DATA

registers

BUS
the

BUS/IN
and

and

for

(bit

When

BYTE

XFER

set,

The

transaction,
shown

OUT

truth
as

and

table

selected

transaction

DATA.

OUT

line

the

used

for

the

these

NPR

and

line

the

bits,

BYTE

XFER

of
1is

KMC11-A

(C0)

BAOQ

Illegal

OUT

below.

NPR

CO.

select

type

(C1)

and

BUS

Control

state

The

BUS/IN

Unibus

(0)

the

and

registers

Control

bit

OUT

XFER

byte.

address

with

from

BYTE

significant

memory

BUS

the

Unibus

controls

address

registers

the

XFER)

registers

(bit

least

PDP-11

associated

comes
for

the

(BYTE

Transaction*
NPR

NPR

Bit

Description

Name

OUT

NPR

BYTE

XFER

KMC11-=-A

(C1)

(CO0)

BAQ

Transaction

ILLEGAL

* %

OUT

NPR

(Destination

low

byte)

OUT

NPR

(Destination
high
*Reference

LAST

NOT

from

BUS/IN

**Source

OUT

This

used

bit

(NOT

execution

multiple

NPRs.

Setting

allows

multiple

NPR

following

completion

the

NPR

case

and

BaAa

multiple

followed

the

XFR

the

When

NPR

cleared

used

are

NOT

the

during

4 -6

LAST

XFR

with

mastership

NPRs,

the

NPR.

1last

asserting

clearing

NOT

instruction.

again,

Unibus

the

KMC11.

extension

memory
(C1

perform

each

KMC11

NPR

Unibus

relinguished

PDP-11

NPRs

performed

LAST

These

KMC11

following

order

maintaining

NPR

mastership

required

NPR

performed

the

mastership

BUS

permit

maintain

LAST

Unibus

byte)

KMC11-A

TRANSFER

XFR)

bits

transaction.

Bit

Description

Name

OUT

NPR

This

NPR

(bit

used

0).

The

association

details

inter-relationship

between

are

MAR

bit

covered

(bit

This
bit

the

these

the

description

only

bit

bits

NPR

0).

with

the

Memory

used

Address

monitor

(MAR)

MAR

This
a

read

flag

bit

use

for

During
the

only

specific

can

MAR

bits

but

(MEM

time.

Only

0-9

MAR

are

bit

incrementing

output

bits

the

MAR

KMC11.

the

bits

clock

pulses
the

7=/

MAR

the
0-9

pulse,

counting

required

starting

determined.

know

MAR

and

either

always

the

address,

the

valuable

loaded

clock

out

read.

location

goes

address)

unknown

brought

debugging

debugging,

contents

point

loaded
from

1024th
are

the

MEM
1s.

bit

number

drive
the

some

all

output

bit

MAR

can

to
be

Bit

Name

BYTE

Description
XFER

This

bit

OUT

NPR

the
the

is
to

association

indicate

PDP-11

memory.

When

PDP-11

uses

selection.

used

stored

memory.

the

low

bit

bit
A0

for

set,
byte

OUT

DATA

7-0

byte

the

PDP-11

OUT

DATA

7-0

1is

PDP-11

the

byte

high

transfer

this

address

the

stored

byte

with

memory.

BYTE

1is

cleared

operation,
to

4.4

the

OUT

PDP-11

MICROPROCESSOR MISCELLANEOUS
Name

Description

NON-EXISTENT

During

'MEMORY

approximately
MEM)

memory

LOW

15-0

memory

is
a

NPR,

this

bit

after

microprocessor.

this

set

triggers

1-shot

the

Unibus

recovery
The

0.5

procedure

LOW

bit

non DEC use.

with

second.

and

non-existent
by

time,

bit.

only

11)

the

NPR

the

Unibus.

i1is

bit

duration

the

BUS*

set

addressed

releases

NPR

word.

This

OUT

transferred

location

logic

DATA

Bit

(NON-EX

during

not

the

goes

pulse

power

PDP-11

recommended

%%fl“éa

set,

pulse

This

initiates
in

When

fail

processor.
for

Description

Bit

Name

OUT

oUuT

PROGRAM

(PGM

and

CLOCK

These

are

bits

used

This

bit

the

PDP-11

during

acts

microprocessor.

CLK)

determine

etc.

This

bit

1-shot

bit

the

1-shot

triggering

and

the

with

this

50us

times

OUT

timer

out,

time

for

pulse

the

this

bit

When

microprogram,

long

along

less

flag

retriggerable

duration.

1-shot

read

time-out,

KMC11

come

the

read

triggered.

pulses

bit

50us

transfer.

for

can

output

set

extension

NPR

intervals,
this

elapsed

testing,

memory

remains
0.

the

than

asserted
1-shot

read

when

XX4

generated.

RESERVED

VECTOR

XX4

this

set,

bit

vector

address

cleared

address

XX0

set

when

generated.

(bit

set,

vector

Bit

Name

Description

BR REQUEST

When set, this bit initiates a Bus

(BR

Request

RQ)

via

the

Unibus

The

microprocessor

with

shipped

installed.

4.5

NPR

BUS

ADDRESS

AND

This

and

cleared

the

has

DATA

Description

Low

byte

OUT

DATA

from

the

Low

byte

the

PDP-11

Bus

Bit

and

+=/0

1is

set

only

hardware

BUS

high

after

and
to

0-7)

byte

transferred

memory.

data

and
to

high

byte

transferred

memory.

Address

NPR

memory.
bit

card

BUS/IN

data

(register

Contains
during

PDP-11

(register
to

level

completed.

(register

can

the

REGISTERS (OUT

Name

DATA

priority

bit

been

BR5

(BA)

transfer

from

bits

0-15

the

is
BA

PDP-11

bit

15.

6, 7

OUT BA

Description

Contains Bus Address (BA) bits 0-15
during

memory.

and

bit

NPR

Bit

+=1/

transfer

the

PDP-11

bit

BA bit

15.

CHAPTER

MICROINSTRUCTION
PROGRAMMING

SCOPE

This

chapter

instruction

word

diagram

5.2
The

provides
word

formats

and

BRANCH

are

and

simplified

and

MOVE.

and

five

with

diagram

three

the

types

Memory

versions

two

the

MOVE

(I)

block

microprocessor.

microinstructions:

the

BRANCH

micrq—

microinstruction

Immediate

(MEM)

(BRG)

Bus

BUS*

(IBUS*)
(MEM)

(BRG)

1024-by-16

assist

timing,

bit

the

are

random

reader

access

(Figure

simplified

5-2)

are

5~/

the

control

RAM

(CRAM)

which

memory.

visualizing

microprocessor

diagram

stored

(I)

(IBUS)

Memory

timing

information.

MOVE

micro-

below.

Immediate

KMC11

simplified

variations

BRANCH

The

the

FORMATS

executes

uses

programming

along

timing

WORD

description

general

presented

Microprocessor

instruction

shown

detailed

formats

MICROINSTRUCTION
KMC11

AND

INFORMATION

5.1

The

FORMATS

microprocessor

data

block

(Figure

included

diagram
in

this

flow

section.

and

5-1)

and

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LAST INST RESULT OPERAND

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CRAM

MAR

LAST INST RESULT OPERAND

BRG

LAST INST RESULT OPERAND

SCRATCH FAL

// CURRENT INST4 OPERAND

MULTIPORT RAM

7| CURRENT INST'8" OPERAND

CURRENT INSTRUCTION

CURRENT INST RESULT OPERAND

Figure

5-2

Microprocessor

Timing

BRANCH

5.2.1

Figure

5-3

jllustrates the word format of the BRANCH microinstruction.

13-15

Bits

are

The

branch.

Microinstruction

the

operation

code

which

the

partial

branch

being

the

address

condition

The

defines

further

address

the microinstruction
the

source
The

developed.

next microinstruction,

resultant

which

microinstruction bits
capable

the

branch

the microinstruction.

address

defining

operand

branch

should

from

address

the

branch

satisfied.

condition under

8-10.
of

the

code

branch

address

These
and

any

form
of

occur

defined

partially defined

eight bits

addressing

are

the

combined

complete

1024

by bits

0-7

with

ten bit

locations

branch

within

the

CRAM.

Three

BRANCH microinstructions

source

operand

branch

address.

5.2.1.1

]

from which

develop

the

low

eight

different

bits

the

CONDITION

BAB

each defining

(I)

Immediate

BRANCH

exist,

IMMEDIATE ADDRESS

11 -4393

The microprogram branches
bits

8-10

is met.

The

microinstruction bits

the

condition

specified

ten bit branch address

the

by microinstruction
result of

0~-7 with the Branch Address Bits

(BAB)

combining

and

12.

BRANCH

I
15

l
13

J\_

OP CODE

r
11

|
~

J\_

]

DEFINED

SOURCE
OPERAND

BRANCH

110
1

BRANCH ADDRESS

ADD-

BRANCH

:.ETSSS

CONDITION

9.8

ALU

SCRATCH PAD

FUNCTION

ADDRESS

000

Reserved

001

Unconditional Branch

010

Branch if C bit is set

011

Branch if 2 bit is set

100

Branch if BRG bit O is set

101

Branch if BRG bit 1 is set

110

Branch if BRG bit 4 is set

111

Branch if BRG bit 7 is set

These two bits combined with the

ALU Function

Code

eight bit ALU output form the

complete ten bit address.

/
100

—

(A-B)

2's COMP SUB

(A-B-1)

ADD

1110
1111

(A,B)

0000

ADD W/C

(A,B,C)

0001

SUB W/C

(A-B-C)

0010

combined with bits 11 and 12 form

INC A

(A,1)

0011

the branch address.

A PLUSC

(A,C)

0100

2A
2A W/C
DEC A
SEL A

(A,A)
(A,A.C)
(A-1)
(A)

0101
0110
0111
1000

Immediate:

Bits 0—7 of the microword

110 — MEM: The MEM contains the source
operand to be combined with the SP
memory operand as defined by the
ALU function bits,
111

suB

BRG:

SEL B
A or B

The BRG contains the source

(B)
(A+§)

1001
1010

operand to be combined with the SP

A and B

(AB)

1011

memory operand as defined by the

AorB

(A+B)

1100

ALU function bits.

A XorB

(A+B)

1101

Notes:

C = Carry
W/C = With Carry

C and Z are set/cleared with MOVE Instructions.

A = Arithmetic or scratch pad (SP) side of ALU.
B = Logic or DMUX side of ALU.

Figure

5-3

Branch

Microinstruction

Word

Format

11 -4374

BRANCH

L=
N

(MEM)

Memory

l
ALU FUNCTION

CONDITION

11 - 4394

This

microinstruction

Logic

Unit

4-7).

The resultant operand,

bits
is

from

Pad

(ALU)

combines

a MEM

(SP).

storage

branch
the

0-3

the MEM operand

while

the

Arithmetic

bits

(bits

combined with microinstruction

and

bits

the ALU FUNCTION

when

location

Microinstruction

Scratch Pad,

operands

ten bit

produces

12,

and

under control

two

other

address

from

the

from the

operand

One

address.

the

operand

Scratch

1in

the

addressed

location

by the current contents of the Memory Address Register (MAR). The
desired

address

would

instruction other

branch

for

the

5-3

defines

5.2.1.3

have

than

been

the

defined

loaded

BRANCH under

the

the MAR by

execution.

CONDITION CODE,

a previous

The

condition

8-10.

bits

Figure

the ALU FUNCTION CODES possible with this microinstruction.

—

BRANCH

(BRG)

SP ADRS

ALU FUNCTION

CONDITION

into

1
11 -4395

With

this microinstruction,

the

contents

the

BRG

and

Scratch

Pad memory location are operated on to generate the‘partial branch
address.
4~7

Bits

define

the

0-3
ALU

specify the Scratch Pad memory location and bits
FUNCTION

be performed

the

two

operands.

5,2.2

MOVE

The

MOVE

with

the

Microinstruction

microinstruction
BRANCH

versatility

and

all,

microinstruction

exist,

each

the

operand.

source

5-4

illustrates

The

operation

the

function

12,

the

from

MAR

the

operand
of

the

code

can

defined

defines

input

The

Function

ALU

operation
plus

operation

inputs.

The

Field,

FROM

bit

microword

all

five

FIELD

and

the

DESTINATION

sets

microinstruction

MOVE

the

The

are

Operation

code.

Figure

address

where

Bits

the

necessary.

and

bits

incremented,

bits

code

8-10.

output

bits

ALU

MAR

MEM

byte

further

addresses.

defines
four

(FROM)

the
bits

address

inputs.

are

the

MAR

increment

operand

for

and

loaded(HI/LO)

low

and

These

ROM

specify

resultant

The

4-7,

operands.

the

dependent

and

microinstructions
The

format.

According

Function

controls

FIELD.

word

destination

the

MOVE

the

MAR.

two

the

for

function,

the

produces

source

13-15.

combined

different

microinstruction

Common

function

bits

operation

ALU

performed
code

When

microinstruction

addresses,

combination

variations

unmodified,

microinstruction

versatile.

microinstruction

(BALU).

five

defined

performed

ALU

the

specifying

defined

remain

Buffered

1is

MOVE

highly

microprogram,

power.

The

also

FUNCTION

and

the

load

MOVE

|
15

|
13

]

MAR

FUNCTION

]

IMMEDIATE OPERAND

DESTINATION
FIELD

FIELD

1.0
.

000

—

No operation

001

—

BRG

OUTBUS*(SPO—A)

INPUT ADRS

QUTPUT ADRS

INPUT ADRS

OUTPUT ADRS

ALU FUNCT

OUTPUT ADRS OR

ALU FUNCT

SCRATCH PAD ADRS

010

—

011

—

BRG right shifted one bit

100

—

OUTBUS (SPO
- A)

101

—

MEM

110

—

SCRATCH PAD

111

—

SCRATCHPAD and BRG

—

No effect

—

Load MAR Hi

—

Load MAR Low

— Increment MAR

ALU Function

Code

000

Immediate operand in bits 0—7 of
..

(A-B)

2's COMP SUB

(A-B-1)
(A,B)

0000

ADD w/C

(A,B,C)

0001

INST

SUB W/C

(A-B-C)

0010

CLOCK

ADD

microinstruction,

001

SuUB

IBUS is operand source defined by

1110

111

MOV

microinstruction bits 4—7 and

INC A

(A,1)

0011

destination defined by bits 8—10.

A PLUSC

(A,C)

0100

(Note 1)

IBUS* is operand source defined by
microinstruction bits 4—7 and destination
defined by bits 8—10.

2A
2A W/C
DEC A

(AA)
(A,AC)
(A-1)

0101
0110
0111

MEM
g
o
|§ gpera:S :OUTC? oper?te on as

SEL A
SEL B

(A)
(B)

1000
1001

AorB

(A+B)

1010

011

BRG is operand source operated on as

A and B

(AB)

1011

defined by ALU function (bits 4—7).

A or B

(A+B)

1100

A XorB

(AeB)

1101

101

efined

by A

unction (bits 4—7).

MOV

INST

(Note 2)

Notes:

If ADD function, C is set to indicate carry or overflow.

Zisset when ALU out isall 1s.

If SUB function, C is cleared to indicate borrow or sign change.

C=_Carry
W/C = with Carry
A = Arithmetic or scratch pad (SP) side of ALU.
B = Logic or DMUX side of ALU,

Figure

11 - 4375

5-4

Move

Microinstruction

Word

Format

CLOCK

The

DESTINATION

FIELD,

destination

references

BRG,

MEM,

and

definition.
previous

BRG

The

resultant
are

shifted

specific

address

and

SCRATCH

BUS,

the

OUT*

BUS

referenced

MEM

BRG

source

The

BRG

right

bits

side

with

OUT

the

1is

two

be used
is

types

with

ALU

MOV

further

references

OUT

BUS,

bits

when

i.e.,

address

with

require

still

OUT*

BUS,

SCRATCH

(bits

0~3)

of the

address

any

possible

registers,

destination

the

right

source

BRG,

bits

BRG

all

within

these

OUT

are

ALU

Thus,

and

are

bit
ALU

passed

during

the

data

MOV

IBUS*

IBUS

However,
and

function

functions.

IBUS*

MEM

are
or

right

MOVE

with
bit

and

the

type

the

shift
ALU

on
B

BRG

returned

BRG

for

MOV

these

while

BRG).

available

instruction

through

available

hardware

BRG

shift.

MOVE

MEM

functions

IBUS,

functions

(SPO0O

7-0

microprogrammed,

unshifted

are

performs

alteration

MOV

BRG

all

BUS*

operands

BRG

allows

Additionally,

function

similar

input

returning

possible

the

Instruction

ALU

Unshifted

used

destination

This

bit

OUT

used,

instruction.
for

eight

predefined

four

memory

and

source

shift

bit

Pad

BUS

presented

operate

specific

Scratch

need

was

include

low order

the

discrete

destination

These

The

MEM

the

destination.

destinations

address

Four

specifies

Three

consequently

location

implies,

operand.

and

PAD/BRG.
provide

name

microprocessor

definition.

microinstruction

When

the

microinstruction.

further

PAD,

the

MEM

MAR

may

load.

also

cases ALU bit

MOVE

MEM,

which

selected

0
1is

the

5.2.2.1

MOVE

(I)

]

IMMEDIATE OPERAND

DEST

MFF

Immediate

11 -4396

The

operand,

specified

With

the

limited

microinstruction
by

MOVE

bits

microinstruction

IMMEDIATE,

bits

and

the

BRG,

references

are

usable;

however,

MAR.

same

data

used

both

MOVE

BUS

(IBUS)

they

moved

the

destination

8-10.

destination

the

since

MEM,

0-7,

reference

The

other

require

possible

special

operand

normally

and

destination

consideration

destination

address.

5.2.2.2

l
0

|
0

|
1

MFF

DEST

[

INPUT ADRS

OUTPUT ADRS

|
11 - 4397

The

operation

because

code

specifies

the

IBUS

information

must

provided

microinstruction

specifies
memory,

the

IBUS

sixteen

the

8-bit

INPUT

4-7).

cases

where

blocks,

i.e.,

OUT

BUS,

OUT*

bits

the

destination.

into

the

MAR

microinstruction

word

when

bits

0-3

specify

and

12.

5=/0

operand.

However,

words

additional

address

the

BUS
the

additionjthe

indicated

source

ADDRESS

(bits

microinstruction

block

clocked

data

block

the

portion

DESTINATION

or
byte

the

MAR

FIELD

Scratch

position

operand

the

can

FUNCTION

Pad

within

also

FIELD,

5.2.2.3

MOVE

BUS*

MFF

]

(IBUS¥*)

DEST

INPUT ADRS

]

OUTPUT ADRS

]

|
11 -

This

microinstruction

with

the

exception

that

similar
the

MOVE

the

IBUS*

MOVE

IBUS

addresses

4398

microinstruction
the

IBUS*

block

words.

5.2.2.4

MOVE

Memory

MMF

(MEM)

DEST

ALU FUNCTION

OUTPUT ADRS

|
11 - 4399

The

MOVE

logical

MEM

operation

resultant

operand

the

two

Pad

memory.

The

Scratch

i1f

The

bits

microinstruction

operands

0~-3

two

into

address

are

0000

of
ALU

designated

the

from

Pad

selection

determined

performs

when

while

0000

one

arithmetic

function

operands

specified

MEM

field

either

arithmetic
deposits

the

destination

address.

One

from

the

Scratch

OUT,

OUT*,

second

the

destination

other

logical
bits

and

the

5-//

six

destinations

operation

through

the

are

defined.

operand

The

resultant

operand

the

DESTINATION

and

MAR

Pad

memory

Scratch

then

the

respective

resultant

operand.

5.2.2.5

MOVE

the

destination

bits

specified

8-~10

and/or

bits

loaded.

MEM

designated

source

operand

destroyed

BRANCH

MFF

microinstruction

the

moved

field,

When

DEST

the

destination,

delivery

the

(BRG)

ALU FUNCTION

OUTPUT ADRS

l
11 - 4400

The

MOVE

operation

MEM

with

one

microinstruction

memory.

memory
operand

or
1s

the

MOVE

BRG

exception.
are

the

microinstruction

The

contents

microinstruction

BRG

destroyed

the
by

two
of

the

delivery

5=/2

the

this

and

the

Scratch

Pad

either

the

Scratch

Pad

then
of

similar

BRG

specifies

destination,
the

operands

the

respective

resultant

source

operand.

5.3

5.3.1

KMC11-A

SAMPLE

Programming

Example

PROGRAMMING

Samples

MOV
32

#20
and

Accessing

CRAM

verify.

performed
Write

for

the

KMC11

The

CSRs

program

functions

counter

and

location

procedures

are:

Functions
a.

Clear

Load

CRAM

Set

bit

SEL

address

Set

bit

SEL

write

at
f.

Programming

BSEL1

#32

desired.

into

data

specified

SEL

(20)

4.
into

SEL

6.
CRAM.

data.into

location.

Clear

BSEL

Write

Functions

MOV

#32,

SEL

i set

CRAM

address

MOV

#20,

SEL

;set

data

MOV

#4,

BSEL

jselect

BISB

#40,

BSEL

CLRB

BSEL

Read

Functions

Repeat

Read

J .

Clear

Programming

Read

steps

SEL

BSEL

CRAM

;jwrite

CRAM

jreset

select

and

CRAM

¢,

and

load

and

write

CRAM

verify.

Functions

MOV

#32,

SEL

;set

MOV

#4,

BSEL

;select

S-/3

CRAM

address

CRAM

to
32

read.

CMP

#20,

SEL

;compare
with

BNE

ERROR

CLRB BSEL

Example

Program

;if

not

clear

the

execute

code

location

MOVB

#100,

BSEL

;set

MOVB

#200,

BSEL

creset

Example

ouT

Example

original

equal,

CRAM

address

data.

then

branch.

select CRAM PC.

KMC11-A
CRAM

contents

and

from

then

set

program

RUN

counter

Procedure

Microcode

105

the

:reset

Master

the

Programming

Write

SELA,

OPORT

clear.

master

clear

SP0O

operand.

SPO0

OUT

using

the

IBUS,

IOBA1,

OUT

INCA,

OBAI1

IBUS,

1IoBAZ2,

OuT

APLUSC,

;write

output
SPO

SPO

OBAZ

(18

bits).

;read

low

byte

;write

out

;read

low

byte

;jbranch

IBUS,

BWRTE

IMM,

BR,

ADD,

BWRTE

IMM,

set

RUN.

Always

Exit

SPO

;read

UBBR,

;jadd carry from low byte

and

Samples

BSEL

Increment

master

carry

from

extended

high

byte

;
SPO

115

5=/

;increment

;jmask

and

NXM

them

save

state

XX4

Alwavs

BR,

AANDB,

Always

Example

OBR

(Cont)

swrite

extended

back

Exit

Perform

NPR

BRWRTE

IMM,
O

OoUT

BR,

SELB,

BRWRTE

IMM,

OouT

BR,

SELB,

IBUS,

BRWRTE

IMM,

101

OuT

BR,

AANDB,

OUT

20,000

OBAT1

OBAZ2

UBBR,

SPO

OBR

;clear

extended

memory
BRWRTE

bits

ot]

OUT

Exit

IMM,

;data

DATAL

bits

write

20000

ouT

BR,

BRWRTE

IMM,

OUT

BR,

SELB,

BRWRTE

IMM,

ouT

BL,

SELB,

ONPR

Unibus

Example
SP

Perform

SELB,

OUTDA1

DATAH

IBUS,

;high

byte

;start

the

OUTDAZ

UBBR,

SPO

NPR

XX4
;read

the

Miscellaneous

IMM,

;save

state

memory
SP

BR,

AANDB,

BRWRTE

IMM,

300

ouT

BR,

AORB,

bits

extended

and

NXM

SPO

i BR
OBR

5=/5

request

and

XX4

bit

Example

Branch

BRG

bit

MEM

source

for

BRWRTE

MEMX,

(requires
PC

shift)

bits

SELB

and

use

07:00.

;

BRSHFT
BR4

Example

ourT

XXX

Send

characters

MEMI,

SELB,

from

MEM

TMTDAT

the

Line

;ilncrement

Unit.

memory

address

:
5§

BRWRTE

IBUS,

BR?

108

ALWAYS

TMTCON

;read

xmit

status

;ready

;not ready wait

10S:

OouT

MEMI,

SELB,

155
:

BWRTE

IBUS,

TMTCON

BR?

208

;

ALWAYS

15¢

TMTDAT

S5=/6

;

5.4

KMC11-A

PROGRAMMING

NOTES

The

following

information

represents

programming

the

The

KMC11

with

allow
for

KMC11-A

Control

multiport
the

that

the

Since

bits

the

PDP11

functions.

CSRs

are

random

power

microcode

procedure

outlined

LLoading

BSEL

RAM,

BSEL

for

the

before

all

Load

CRAM

Set

ROM

up,

the

random
bit

Control

data.

15)

Random

Therefore,

should

not

resides

CRAM.

the

O0s

into

(right

words

portion

byte

the

hardware.
leaves

all

the

any

control

Access

Memory

the

CRAM

and

following

asserted

verifying

Procedure

Write

and

requirement,

below.

CSRs

only

sequence

minimum

These

requirement

This

implemented

microprogram

the

define.

power

clear

KMC11

defined

are

bytes,
only

user.

(RAM).

The

the

(CSR)

bits,

the

aspects

attempted.

contains
(BSEL

and

memory

transfer.

and

should

value

cannot

states.

Following

RUN

user

are

known

bit

transfers

up,

selection

program

practical

Registers

access

PDP11

program

(CRAM)

random

the

Status

data

that

Maintenance

and/or

the

CSRs

will

and

arbitrary

control

agree

that

some

BSEL

justified)

data

into

(BSEL

SEL

bit

into

10).

$=/7

SEL

power

until

its

contents

e .

Set

ROM

bit

13).

Clear

Repeat

Reading

ROM

(BSEL

and

CRAM

through

steps

Write

Load

Set

ROM

Read

Clear ROM O bit.

Repeat

code

all

O
6

and

WRITE

CRAM

WRITE

(BSEL

bits.

the

time.

The

bit

required.

through

between

possibility

occurrence

data.

into

required.

PDP11

should
for

write

CRAM

code

destructive

sequence

SEL

the

with

into

0).

contains

transfers

The

wanting

filled

control

KMC11

BSEL

justified)

which

transfer

allow

into

(BSEL

steps

procedures.

not

0O0s

(right

SEL

could

These

10)

Procedure

Control

bit

the

race

the

same

KMC11

conditions.

interlocked

control

both

and

sequential

transfer

PDP11
byte

condition

should

and

the

would

same

cause

lost

data.

A
be

race-free
as

control

transfer

initiated

the

PDP11

could

follows.

The

PDP11

transfer

program asserts

Request bit and encoded

type.

The

KMC11

responds

with

. Co.

The

PDP-11

program

loads

Request

bit.

clears

the

acknowledgement

data

5—/8

into

predefined

proceed.
bytes

and

Observing

accepts

the

completes

Single

bit

data

the

control

could

exist

bits

When

the

entered,

the

bits

This

procedure

the

CSR

it.

All

bits

may

not

The

KMC11

have

the

bit,

the

acknowledge

KMC11

bit

which

Type

the

from

either

free.

However,

item

transfer

and

bits

service

the

a race condition

includes

along

should

side

with

one

the

request.

subroutine

read

again

1is

insure

lost.

because

that

the

written

the

KMC11

PDP11

may

program

simultaneously

KMC11

but

the

NPRs

power

fail

traps

be
is

additional

reading
writing

the

into

request

function

bits

detected.

Unibus,

and

failure.

include

some

able

common

bit

(NPR

cause
a

precaution,

diagnostic

before

Most

extended

type

time

cannot

Request

asserted

used

required

clears

detected

same

detected

function

been

the

request

the

transaction.

Transfer

that

to be race

define

request

and

functions

are guaranteed

CSRs

clearing

system

Control
bits

KMC11

interacts

troubles

occur

17)

are

bit
not

bit
a

address,

function

microcode

any

18
as

capability;

(16,

any

package

least

way

with

the

because
used

the

Not

the

hardware
should

start

PDP11

program.

Last

Transfer

incorrectly

maintained.

hang

the

bits

(except

the

Not

Last

Transfer

bit)

should

changed in the KMC11's NPR Control Register,‘if the NPR
Request

Bit

introduced.
Last

10.

bits

i1if

12.

ACLO

the

will

bit

changed

the

KMC11's

BR
be

Request

the

are

used

follows:

bits

NPR

from

NPR

not

* 1

Byte

the

used.

OUT

DATA

low

position

the

Not

Miscellaneous

asserted

Miscellaneous

BYTE

OUT

LSB

Unibus

because

race

not

XFER

(C0)

and

OUT

NPR

(C1)

NPR

DATA

OUT

Unibus

transfer

BA
BA

address.
address.

use.

Also,

contents

the

Function

byte

DEC.

from

bit

KMC11's

explanation

will

introduced.

Control

code

condition

for

NPR

LSB

race

except

*The

item

recommended

because

bit.

should

condition

The

asserted,

Refer

Transfer

11.

the

address
byte

are

OUT

must

the

high

then

the

byte

always

LSB

the

remains

contents

5~20

address.

always

transfer

transfered

and

unless

sourced
then

the

destinations'

undisturbed.
OUT

DATA

transferred

byte

13.

The

remains

KMC11-A

following
intended
moving

the

destinations'

capable

execution
allow

data

the

maintaining

NPR

KMC11

minimum

the

Last

Transfer

locks

the

Unibus..

The
It

the

operations
Not

following
is

that

the

are

maintained.

Assert

NOT

LAST

Bits

and

the

NPR.

this

period.

That

other

The

required

followed

perform

time

the

low

user

(NOT

LAST

XFER)

should

the

than

NPRs

NPR

clearing

instruction.

used

for

NPRs

Read-Modify-Write
is

cautioned

left

multiple

NPRs.

NPR

data

NPR

(NPR

Control

The

NPR

bit

and

may

reasserted

Unibus

other

controlled

performed

registers

mastership

Unibus

the

for

during

transactions

that

asserted

and

NPR

for

retains

is,

feature

multiple

the

and

mastership

This

However,

proper

KMC11

possible

last

transaction.

respectively).

The

Unibus

enable

XFER

completion

each

KMC11

and

Unibus.

procedure

assumed

byte

undisturbed.

high

are

KMC11.

asserting

NOT

LAST

XFER

the

Clearing

NOT

LAST

XFER

drops

NPR

next
BUS

SACK and allows Unibus arbitration for the next master
while

the

last

NPR

progress.

5=2/

When NPR RQ

cleared

again,

Unibus

mastership

1is

relinquished.

cleared

also

XFER may

LAST

NOT

already

NPR RQ

cleared and the KMC11 is Unibus master. In this casé,

5.5
1.

Unibus

in violation

Transmit

PROGRAMMING

NOTES

Start

of Message

(TSOM)

are

TEOM

These

this

sent

from

the

Out Control

when

the microprocessor

data,

etc.)

into

the

bit

control

load

However,

the

TSIP

flip-flop which

the

Out

Control

Therefore,

signal

load

before

Control

control

information

the

Out

Data

the

Bit

Stuff

Silo with
function

either
that

for

goes

the

clears

Out

the

Silo

TSOM

character

loads

set,

character.

along

with

the

Data

Silo

also

TSOM and

the

clocks

TEOM bits

always

TEOM)

(TSOM

Buffer

Out Data

Message

the microprocessor.

into

Transmitter

(sync,

Control

loaded

are

bits

and Transmit End

Out

the

and

bits

are

(TEOM)
and

UNIT

LINE

DMC11

Specifications.

Unibus

the

sequence

this

However,

mastership occurs.

relinquishing

SACK and

of BUS

clearing

immediate

the

Silo

the

TSOM

cleared

the

Out

from

this

TSOM or
performed

TEOM

Data

into

the

Silo.

Out

The

automatically

data.

the

data

TEOM bit

the

accepts

mode,

written

into

the

lost.

This

automatically by

522

the

Out

Data

internal

transmitter

control
the

logic.

place

control

logic

i1t

sends

set.

MATCH

shift

the

both

TEOM

BLOCK

the

flag

BLOCK

END

are

lost.

are

Shift

output,

check

TSOM

set

character

when

TEOM

set,

are

sent.

and

part

When

bits

inhibiting

transmitter

when

the

zeroes

the

are

read

the

3341

data

microprocessor,

These

the

character

are

accomplished

Data

bits

Silo.
the

CRC

TSOM

they

read

Control

FIFOs

bits

BCC

MATCH

part

that

the

and
the

Therefore,
reading

the

END

Data

are

the

and

Silo

transmitter

Data

Control

Physically,

constitute

this

Transmitter

transmits

and

the

and

BCC

Physically,

always

the

DDCMP

CRC

check

read

Data

mode,

the

Control

before

Silo.

the

BCC

character

MATCH

that

flag

produced

presented

the

with

match

information.

In the Bit Stuff mode,
the
with

terminating
the

high

flag

byte

the BLOCK END bit

has

been

the

CRC

received.
Check

asserted when

This

bit

Character.

1is

loaded

Therefore,

the BCC MATCH bit along with the BLOCK END bit should be
used

indicate

reception

errorless

messagde.

The

Request

microcode.
data

function

The

line

unit

control

logic

the

before

the

Out

Data

assertion

time

that

serial

the

Line

the

DMC11-MA

transmitter

underrun

condition

and

present

transmit

the

bottom

logic

ready

flagged

the

not

EOM

The

transmitter

not

minimum

DMC11-DA

used

one

and

determined

Line

bits.

bit

ABORT

character

the

for

character

Line

the

(CS)

has

provide

silo

starts.

occurs

delay

data

Silo

when

the

This

can

sends

all

before

about

not

condition

occur

all

used.
stream

mode,

the

all

sequence

only

524

are

for

data

For

data

dropping

mode,

Send

about

Data

between

the

all

oriented

delay

100us.

the

The

and

modem/DSU

because

when

data

the

sequence

a message.

time

Units,

asserts

character.

hardware

terminate

the

Out

DMC11-MD

delay

automatically

Units,

stuff

Units,
The

only

Silo.

Clear

transmission

and

read

microcode

used.

the

modem

and

DMC11-DA

function

(RS)

determines

For

Send

available

assertion

depth

the

occurs

a
RS.

For

stream

length

DMC11-MA
for

recognized

protocols

and

least

stuffed.

those

the

with

proper

error

condition.

The

Such

Data

assumed

detection

precludes

the

Protocols

with

DDCMP,
that

message

may

loose

For

bit

(TSOM)

not

high

proper

this
a

overrun

speed

the

for

and

bit

overrun

detection

sequence

detect

Transmit

control

transfers

are

always

new

characters

line.

block
be

such

size
the

messages

overrun.

Start

information.
on

Protocols

terminate

required

transmitted

indicator.

error.
to

two

this

microprocessor

methods,

CRC

protocols,

from

indicator.

KMC11

indeterminate

unable

easily

DDCMP.

condition

with

recover

have

error

specific

data

can

stuff

flag

output

the

protocols

transmission
two

does

requirement

detect

rely

a protocl

Silo

that

methods

the

Message

to
This

start
causes

serial

APPENDIX

PDP-11

MEMORY

ORGANIZATION

AND

ADDRESSING

The

PDP-11

8-bit

memory

bytes.

location;

low

numbered.

organized

Each

byte

bytes

are

Words

and the high
provide

CONVENTIONS

are

(0dd)

16-bit

i1is

addressable

even

numbered

addressed

byte

word.

numbered

addresses.

even

location

select

byte

8-bit

locations

each

128K

16-bit

1024

131,072
PDP-11

processor

A-1

this

The

with

which

odd

locations

only

included to

therefore

addresses

found
odd

identified as A(17:00).
addressing

byte.

262,144

the

size

management

unit,

limits

the

maximum

This

the

can

unit

also

memory

represents

equals

and

238K

represents

used

only

that

processor

memory

256K

multipler

locations

memory

this

the

are

two

address

are

automatically

discussion,

memory

bytes

numbered

18 bits

8-bit

maximum

own

byte.

Without

(32,768)

shows

its

high

words

capability

represents

bits.

bits

256K bytes.
262,144

256K

the

which

locations.

bytes or 32K

Figure

words.

that

address

provide

consisting

has

operation

The Unibus address word contains
bits

and

the word is

words

and

even

Consecutive

even

Eighteen

16-bit

size

utilizes

provides

64K

all

(65,536)

words .

organization

for

the

maximum

memory

size

In the binary system, 18 bits can specify 218 or

(256K)

locations.

The

octal

numbering

system

used

designate
the

the

address

shown

The

address.

the

address

binary

provides

system

convenience

that

the

processor

converting
uses

below.

highest

internal

general

physical

memory

reserved.

for

result,

this

area;

words

program.

PDP-11

these

locations

registers

assigned

This

processor

and

(760000-77777)

peripheral

addresses;

only

programmable
therefore,

without

the

devices.
the

memory

the

user

memory

are

reserved

for

There

cannot

numbers

locations
has

248

management

are

bytes

unit

provides

16 address bits that specify 216 or 65,536 (64K)

1locations

(Figure

A=2).

(64K)

32,768

(32K)

A(17:16)
is

master

with

only

to
to

The

maximum

words.

bits

allow

16=-bit

Logic

memory

size

processor

the

A(15:13)

generation

are

all

1is

addresses

65,536

forces

when
in

the

bytes

address

the

bits

processor

reserved

area

O|\ADORESS 81T

0\0{/ |0 | B/INARY

control.

[7/16115|/41131e|//
/0|9

124K

OC TAL

|15
08|07
00
lke— 16 BIT DATA WORD —
HIGH BYTE

000001

LOW BYTE

000000

000003

000002

USER ADDRESS SPACE
AVAILABLE USING 18
ADDRESS BITS ON

|
)

POP-11 PROCESSOR

.,_____—/’T

WITH

MEMORY

MANAGEMENT OPTION,

INCLUDES 248K (253,952)

BYTES OR 124K (126,976)
WORDS.

757776

760001

76 0000

\
)

757777

____/’1

HIGHEST 8K (81392)

BYTES

4K (4096)

WORDS RESERVED FOR

DEVICE REGISTER
ADDRESSES.

*777777

777776

LAST ADDRESS IS BYTE NUMBER 262,143,

MAXIMUM SIZE WITH 18 ADDRESS BITS IS 256K(262,144) BYTES OR 128K (131,072) WORDS.
11-1690

Figure

A-1

Memory

Organization
18

Address

A=3

for
Bits

Maximum

Size

Using

00|
08|07
lis
le— 16 BIT DATA WORD —
HIGH BYTE

LOW BYTE

000001

000000

000003

000002

USER ADDRESS SPACE

AVAILABLE

USING 16

ADDRESS BITS ON
PDP-11

PROCESSOR

WITHOUT MEMORY
MANAGEMENT OPTION,

INCLUDES 56K (57, 344)
BYTES OR 28K (28,672)
WORDS.
157777

157776

160001

160000

T
ADDRESSES 160000177777 ARE CONVERTED

~—

TO 760000 -777777 BY
THE PROCESSOR. THUS,
THEY BECOME THE

HIGHEST 8K (8192) BYTES
OR 4K(4096) WORDS
RESERVED FOR DEVICE

177776

*177777

LAST ADDRESS IS BYTE NUMBER 65.53510

* MAXIMUM SIZE WITH 16 ADDRESS BITS IS 64K (65,536) BYTES OR 32K(32,768) WORDS.
I1-1689

Figure A-2

Memory Organization for Maximum Size Using
16

Address
A-4

Bits

Bit

becomes

(56K) .
byte

This

memory.

highest

locations

bytes

Memory
the

the

28,672

less

are

addresses

memory

locations

PDP-11

core

location

56K

interfering

(28K

the

bus.

bytes

the

bytes

64K

These

user

(4K words)
are

has

the

and

57,344

words)

under

the

reserved

area,

because

not

have

there

with

the

size

core

binary

not

possibility

(56K)

increments.

memories

are

shown

Highest Location
(Octal)

8
16
24

017777
037777
057777

077777
117777
137777
157777

A13.

physical

space.

have

bit

reserved

Size
K-Bytes

32
40
48
56

57,344

160000-177777

general

the

decimal

available

various

last

program.

and

locations

internal

with

160000

are

which

last

therefore,

bytes

converted

Memory
K-Words
4
8
12
16
20
24
28

words

than

these

for

addresses;

memories

the

accessible

reserved

160000

converts

interference

designations

relocates

(28K)

capacities

octal

processor

are

device

beginning

locations

problem

highest

first

which

that

peripheral

The

760000-777777
the

The

below.

digital equipment corporation

Printed

U.S.A.