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EK-2LA36-MM-001

November 1976

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Document:	LA36 DECwriter II Maintenance Manual Volume 2
Order Number:	EK-2LA36-MM
Revision:	001
Pages:	210
Original Filename:	http://bitsavers.org/pdf/dec/terminal/la36/EK-2LA36-MM-001_LA36_LA35_DECwriter_II_Maintenance_Manual_Volume_II_197611.pdf

OCR Text

EK-2LA36-MM-001

LA36 DECwriter II
MAINTENANCE MANUAL
Volume II

digital equipment corporation • maynard, massac~usetts

1st Edition, November 1976

Copyright© 1976 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon·
sibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL's DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem-IO
DECSYSTEM-20

DECtape
DECUS
DIGITAL
MASSBUS

6/77-14

PDP
RSTS
TYPESET-8
TYPESET-11
UNIBUS

CONTENTS
Page
CHAPTER 9

UPGRADED LA36

9.1
9.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.4
9.4.l
9.5
9.6
9.7
9.8
9.8.1
9.8.2
9.8.3
9.8.4

GENERAL . . . . . . . . . . . . . . . . . . .
LA35/LA36 MODEL VARIATIONS
.... .
EASY IDENTIFICATION OF LOGIC BOARDS
Major Functional Differences Between M7722 and M7723 Logic Boards
M7723 Jumper Configurations . . . . . . . . . . . . . . . . . .
Functional Differences Between M7723 and M7728 Logic Boards .
M7728 Jumper Configurations .
M7728 Cabling Configurations .
MAJOR POWER SUPPLY CHANGES
New Power Transformers
NEW KJWBOARD BEZELS
CAPS LOCK KEYBOARD . .
LA35/LA36 OPTIONS . . . .
UPGRADED LA36 FUNCTIONAL DESCRIPTION
New Transmit Path . . . . . . . . . . . .
New Receive Path
Transmit Operation with Options Installed
Receive Operation with Options Installed

CHAPTER 10

COMPRESSED FONT OPTION KIT (LAXX-KJ)

10.1
10.2

INTRODUCTION TO COMPRESSED FONT
LAXX-KJ PRINT SET . . . . . . . . . . . . .

CHAPTER 11

FORMS CONTROL OPTION KIT (LAXX-KV)

11.1
11.2
11.3
11.3.1
11.3.2
11.4
11.4.l
11.4.2
11.4.3
11.5
11.6

FORMS CONTROL INTRODUCTION
FORMS CONTROL FUNCTIONAL DIAGRAM
FORMS CONTROL BASIC BLOCK DIAGRAM
Counter Circuit
Option Timing . . . . .
OPERATI ON AL SEQUENCES
Any Character Received
Line Feed Code Decoded
Form Feed Code Decoded
TROUBLESHOOTING
LAXX-KV PRINT SET

CHAPTER 12

SELECTIVE ADDRESSING OPTION (LAXX-KW)

12.1
12.1.1
12.1.2
12.l .3
12.2
12.3
12.3.1
12.3.2
12.3.2.l
12.3.2.2

SELECTIVE ADDRESSING INTRODUCTION
Transmit Conditions
Receive Conditions . . . . . . . . . . . .
Operational Modes . . . . . . . . . . . .
SELECTIVE ADDRESSING FUNCTIONAL BLOCK DIAGRAM
SELECTIVE ADDRESSING BASIC BLOCK DIAGRAM
Power-Up Sequence
Address Mode
Broadcast Slaves
Group Slaves . .

iii

9-1
9-1
9-2
9-2
9-2
9-4
9-4
9-4
9-4
9-4
9-4
9-4
9-4
9-7
. 9-10
. 9-10
. 9-14
. 9-14

10-1
10-1

11-1
11-1
11-3
1-4
1-4
11-5
11-5
11-5
11-7
11-7
11-7

12-1
12-1
12-1
12-2
12-2
12-4
12-4

12-6
12-6
I 2-6

CONTENTS (Cont)

Page
12.3.2.3
12.3.2.4
12.3.2.5
12.4
12.5

Unique One-Way Slaves
Unique Two-Way Slaves
Select Add-On Slaves .
TROUBLESHOOTING
LAXX-KW PRINT SET

CHAPTER 13

AUTOMATIC ANSWERBACK OPTION (LAXX-KX)

13.1
13.2
13.2.1
13.2.2
13.2.3
13.3
13.3.1
13.3.2
13.3.3
13.4
13.5

AUTOMATIC ANSWERBACK INTRODUCTION ..
ANSWERBACK OPTION FUNCTIONAL BLOCK DIAGRAM
Operation of LF Transmit Section
Operation of LF Receive Section
. . . . . . . . . .
Operation of Answerback Section . . . . . . . . . .
AUTOMATIC ANSWERBACK BASIC BLOCK DIAGRAM
LF Transmit Section Basic Block Diagram
LF Receive Section Basic Block Diagram
Answerback Section Basic Block Diagram
TROUBLESHOOTING
LAXX-KX PRINT SET
. . . . . . . . . . . .

CHAPTER 14

FORMS CONTROL, VERTICAL TABULATION, AND HORIZONTAL TABULATION
OPTION (LAXX-KY)

14.1
14.2
14.3
14.3.1
14.3.2
14.3.3
14.4
14.4.1
14.4.1.1
14.4.1.2
14.4.2
14.4.3
14.4.3.1
14.4.3.2
14.4.3.3
14.4.3.4
14.4.4
14.4.4.1
14.4.4.2
14.4.4.3
14.4.5
14.4.5.1
14.4.5.2
14.4.5.3
14.4.5.4
14.5
14.6

TABS OPTION INTRODUCTION . . . . . . .
TABS OPTION FUNCTIONAL DIAGRAM ..
SIMPLIFIED OPERATION OF TABS OPTION
Horizontal Tabs Operation ..
Top of Form (TOF) Operation . . . . .
Vertical Tabs Operation . . . . . . . .
TABS OPTION BASIC BLOCK DIAGRAM .
Decoding and Generating Circuits Basic Block Diagram
Decoding . . . . . . . . . . .
Generating . . . . . . . . . . . . . . .
Timing Circuits Basic Block Diagram . . . . .
Horizontal Tabs Circuits Basic Block Diagram
Monitoring . . . . . .
Setup . . . . . . . . . . . . . . .
Horizontal Tab Action . . . . . .
Clearing Horizontal Tabs . . . . .
Top of Form (TOF) Circuits Basic Block Diagram
Monitoring . . . .
. . . . .
Form Feeding . . . . . . . . . . . .
Setup and Wake-Up . . . . . . . .
Vertical Tabs Circuits Basic Block Diagram
Monitoring . . . . .
Vertical Tab Setup . . .
Vertical Tab Action
Clearing Vertical Tabs
TROUBLESHOOTING
LAXX-KY PRINT SET
. . . . . .

12-7
12-7
12-7
12-7
12-7

13-1
13-1
13-3
13-3
13-5
13-8
13-8
13-10
13-11
13-14
13-14

14-1
14-1
14-3
14-4
14-4
14-5
14-5
14-5
14-6
14-8
14-8
14-8
14-12
14-12
14-12
14-13
14-13
14-13
14-14
14-16
14-16
14-16
14-20
14-20
14-21
14-22
14-22

CONTENTS (Cont)
Page
CHAPTER IS

AUTOMATIC LINE FEED OPTION (LAXX-LA)

15.1
15.2
15.3
15.3.1
15.3.2
15.4
15.5

AUTOMATIC LINE FEED INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . 15-1
AUTOMATIC LINE FEED FUNCTIONAL BLOCK DIAGRAM
. . . . . . . . . . . . . . 15-1
AUTOMATIC LINE FEED BASIC BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . 15-3
Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Receive Section
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
TROUBLESHOOTING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
LAXX-LA PRINT SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

CHAPTER16

EXPANDER OPTION MOUNTING KIT (LAXX-LB)

16.1
16.2
16.3
16.3 .1
16.3.2
16.4
16.5

EXPANDER OPTION MOUNTING KIT INTRODUCTION . . . . . . . . . . . . . . . . . 16-1
EXPANDER BOARD DATA DISTRIBUTION
. . . . . . . . . . . . . . . . . . . . . . . 16-1
EXPANDER BOARD CONTROL SIGNAL DISTRIBUTION . . . . . . . . . . . . . . . . 16-2
Routing of DATA AVAILABLE Signal . . . . . . . . . . . . . . . . . . . . . . . . 16-2
Routing of KEYSTROBE Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
TROUBLESHOOTING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
LAXX-LB PRINT SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5

CHAPTER 17

EIA INTERFACE OPTION KIT (LAXX-LG)

17.1
17.2
17.3
17.3.1
17.3.2
17.3.3

EIA INTERFACE INTRODUCTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
EIA INTERFACE FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . 17 -1
EIA INTERFACE BASIC BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . 174
Data Path
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
Connection Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
Disconnect Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
TROUBLESHOOTING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
LAXX-LG PRINT SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7

17.4
17.5
CHAPTER 18

20 mA INTERFACE CABLE OPTION KITS (LAXX-LK DEC 10
AND LAXX-LH STANDARD)

18.1

20 mA INTERFACE CABLE INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . 18-1

CHAPTER 19

ACOUSTIC COUPLER OPTION KIT (LAXX-LM)

19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8

INTRODUCTION TO THE ACOUSTIC COUPLER . . . . . . . . . . . . . . . . . . . . . 19-1
TYPICAL ACOUSTIC COUPLER OPERATION
. . . . . . . . . . . . . . . . . . . . . . 19-1
ACOUSTIC COUPLER FUNCTIONAL BLOCK DIAGRAM
. . . . . . . . . . . . . . . . 19-2
ACOUSTIC COUPLER BASIC BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . 19-3
TRANSMIT SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
RECEIVE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
TROUBLESHOOTING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
LAXX-LM PRINT SET
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6

CHAPTER20

APL OPTION KIT (LAXX-PK)

20.1
20.2
20.3

APL INTRODUCTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
APL FUNCTIONAL BLOCK DIAGRAM • . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
APL BASIC BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
CHARACTER STORAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2

20.4

CONTENTS (Cont)
Page
20.5
20.6
20.7

CHARACTER SET SELECTION
TROUBLESHOOTING
LAXX-PK PRINT SET

CHAPTER21

M7728 PRINT SET

APPENDIX A

REFERENCE DATA

A.I
A.2
A.3

ABBREVIATIONS
.....
SIGNAL GLOSSARY .....
IC PIN LOCATION DRAWINGS

20-6
20-9
. 20-9

A-1
A-1
A-1

ILLUSTRATIONS
Figure No.
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
11-1
11-2
11-3
11-4
11-5
11-6
11-7
12-1
12-2
12-3
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
14-1
14-2
14-3

Title
Physical Characteristics of M7722, M7723, and M7728 Logic Boards
Location of Jumpers on M7723 Logic Board
Location of Jumpers on M7728 Logic Board
Cabling Configurations for the M7728 Logic Board
LA36 Keyboard Bezel . . . . . . . . . . .
Basic Block Diagram of M7728 Logic Board
M7728 Control Logic Diagram . . . . . .
Steering of Keyboard Data . . . . . . . .
Receive Operations of M7728 Logic Board
Forms Control Functional Block Diagram
Forms Control Basic Block Diagram
Timing Sequence for Forms Control Option
Forms Control Operational Sequence When Any Character Received
Forms Control Operational Sequence When Line Feed Code Received
Forms Control Operational Sequence When Form Feed Code Received
LAXX-KV Form Feed Diode Matrix . . . . . .
Selective Addressing Functional Block Diagram . . . . . .
Selective Addressing Basic Block Diagram
. . . . . .
Timing Diagram for Transmit Enable and Disable Sequence
Automatic Answerback Option Functional Block Diagram
Operational Sequence for LF Transmit Section
Operational Sequence for LF Receive Section
Operational Sequence for Answerback Section
LF Sections of Answerback Option
LF Transmit Section Timing Sequence . .
LF Receive Section Timing Sequence
Answerback Section Basic Block Diagram
Typical Answerback Character Programming
Answerback Section Timing Sequence . . .
Tabs Option Functional Block Diagram
Decoding and Generating Circuits Basic Block Diagram
Timing for ESC Command Decoding . . . . . . . . .

Page
9-2
9-3
9-5
9-6
9-7
9-11
9-12
9-13
9-15
11-2
11-3
11-5
11-6
11-6
11-8
11-10
12-3
12-5
12-8
13-2
13-4
13-6
13-7
13-9
13-10
13-11
13-12
13-14
13-15
14-2
14-6
14-7

ILLUSTRATIONS (Cont)
Figure No.
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
15-1
15-2
15-3
15-4
15-5
15-6
16-1
16-2
16-3
16-4
17-1
17-2
18-1
18-2
19-1
19-2
19-3
19-4
20-1
20-2
20-3
20-4
20-5
20-6
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
A-11
A-12
A-13
A-14
A-15
A-16

Title
Timing Circuits Basic Block Diagram
Horizontal Tabs Circuits Basic Block Diagram
Horizontal Tabs Circuits Operational Sequence
Top of Form Circuits Basic Block Diagram
Top of Form Circuits Operational Sequence
Vertical Tabs Circuits Basic Block Diagram
Vertical Tabs Circuits Operational Sequence
Common Components of Vertical Tabs and TOF Circuits
LAXX-KY Diode Matrix . . . . . . . . .
Automatic Line Feed Functional Diagram . . . . . . . .
Automatic Line Feed Block Diagram
......... .
Operational Sequence for Automatic Line Feed Transmit Section
Transmit Line Feed Control Timing Sequence . . . . . . . . .
Operational Sequence for Automatic Line Feed Receive Section
Receive Line Feed Control Timing Sequence
ASCII Data Distribution on Expander Board
. . . . . .
Data Available Signal Distribution on Expander Board
Methods of Switching Data Available Signal into Options
Keystrobe Distribution on Expander Board
EIA Interface Functional Diagram . . . . . . . . . . . .
EIA Interface Block Diagram
. . . . . . . . . . . . . .
20 mA Interface Cable Option (LAXX-LK) Pin Assignments
20 mA Interface Cable Option (LAXX-LH) Pin Assignments
Typical Telephone Communication Configuration . . .
Acoustic Coupler Functional Block Diagram . . . . . .
Acoustic Coupler Transmit Section Basic Block Diagram
Acoustic Coupler Receive Section Basic Block Diagram
APL Character Set Functional Block Diagram
Bit Assignments for ASCII and APL Character Sets
APL Option Basic Block Diagram . . . . . . . . .
Typical ASCII/ APL ROM Mapping and Print Pattern
Jumper Control over Character Set Selection
Operational Sequence for OCS Set
380 Quad 2-Input NOR Gate
..... .
1702A 8-Bit Reprogrammable ROM . . .
2627P A6-01 Character Generator Alpha
3101 Random Access Memory . . . . . .
7400 Quad 2-lnput Positive NAND Gate
7401 NAND Gate-Quad 2-Pin Open Collector
7404 Hex Inverter . . . . . . . . . . .
7408 Quad 2-Input Positive AND Gate
7410 Triple 3-Input Positive NAND Gate
7413 Schmidt Trigger . . . . .
7416 Hex Inverter Buffer/Driver
7417 Hex Buffers/Drivers
7420 NAND Gate-Dual 4-Input
7423 . . . . . . . . . . . . .
7437 NAND Gate-Quad 2 In Buffer, 14 Pin
7442 4-Line-to-l 0-Line Decoders
.....

vii

Page
14-8
14-10
14-11
14-14
14-15
14-17
14-18
14-19
14-24
15-2
15-3
15-4
15-5
15-6
15-7
16-2
16-3
16-4
16-5
17-2
17-5
18-1
18-2
19-2
19-3
19-3
19-4
. 20-3
. 20-4
. 20-5
. 20-7
. 20-8
20-10
A-13
A-13

A-14
A-15
A-16
A-16
A-16
A-17
A-17
A-18
A-18
A-19
A-19
A-20
A-20
A-21

ILLUSTRATIONS (Cont)
Figure No.
A-17
A-18
A-19
A-20
A-21
A-22
A-23
A-24
A-25
A-26
A-27
A-28
A-29

Title
7474 Dual D-Type Edge-Triggered Flip-Flop
7489 64-Bit Read/Write Memory
7493A Counter Asynch Up, Binary
74123 Monostable Multivibrator .
74150 Data Selector/Multiplexer
74154 4-Line-to-26-Line Decoder/Demultiplexer
74161 4-Bit Binary Counter . . . . . . . . . . .
74175 Quad D-Type Flip-Flop with Clear
74190 Counter, Synch Up/Down Decade, 16 Pin
74193 Synchronous 4-Bit Up/Down Counter
Universal Asynchronous Receiver Transmitter
301 AN DIP Operational Amplifier
309 K Regulator . . . . . . . . . . . . . . .

Page
A-22
A-22
A-22
A-23
A-23
A-24
A-24
A-25
A-26
A-27
A-28
A-28
A-29

TABLES
Table No.
9-1
11-1
12-1
13-1
14-1
14-2
14-3
144
15-1
16-1
17-1
17-2
17-3
19-1
20-1
20-2
A-1
A-2

Title
LA35/36 Options
. . . . . . . .
. ........ .
Troubleshooting for Forms Control Option Kit (LAXX-KV)
Troubleshooting for Selective Addressing Option (LAXX-KW)
Troubleshooting for Automatic Answerback Option (LAXX-KX)
Codes Decoded By Tabs Option . . . . . . .
Control Commands for Major Tab Operations . . . . . . .
Timing Sequencer Major Events . . . . . . . . . . . . . .
Troubleshooting for VT, HT, and TOF Option (LAXX-KY)
Troubleshooting for Automatic Line Feed Option (LAXX-LA)
Troubleshooting for Expander Option Mounting Kit (LAXX-LB)
Effect of Tri-State Line Levels . . . . . . . . . . . . .
Standard EIA Modem - Terminal Interface Connections
Troubleshooting for EIA Interface Option (LAXX-LG)
Troubleshooting for Acoustic Coupler Option (LAXX-LM)
OCS Jumper Configurations . . . . . . . . . . .
Troubleshooting for APL Option Kit (LAXX-PK)
Glossary of Abbreviations
Signal Glossary . . . . . . . . . . . . . . . . . .

viii

Page
9-8
11-9
12-9
13-16
14-3
. 14-3
. 14-9
14-23
15-8
16-6
17-3
17-8
17-9
•' 19-7
. 20-7
10-11
A-3
. A-7

CHAPTER 9
UPGRADED LA36

9.1 GENERAL
The purpose of this chapter is to upgrade the maintenance manual for the LA36 DECwriter II so that it reflects
the equipment changes incurred since the original publication. Changes of significant importance include:

I.
2.
3.
4.
5.
6.
7.

M 7723 Logic Board
M7728 Logic Board
Power Board Changes
Constant Voltage Transformer
New Bezel
Caps Lock Keyboard
Addition of Options

9.2 LA35/LA36 MODEL V ARIA TIO NS
The variations and associated model numbers for the LA35/LA36 a listed below.
Model No.

Variation

Designation
LA35

LA35-CE
LA35-CF
LA35-CH
LA35-CJ
LA35-DE
LA35-DJ

90-132 V, 60 Hz
180-264 V, 60 Hz
90-132 V, 50 Hz
180-264 V, 50 Hz
90-132 V, 60 Hz
180-264 V, 50 Hz

LA35
LA35
LA35
LA35
LA35
LA35
LA36

LA36-CE
LA36-CF
LA36-CH
LA36-CJ
LA36-DE
LA36-DF
LA36-DH
LA36-DJ

LA36 with Numeric Pad and Paper Out
LA36 with Numeric Pad and Paper Out
LA36 with Numeric Pad and Paper Out
LA36 with Numeric Pad and Paper Out
LA36
LA36
LA36
LA36

9-1

90-132 V, 60 Hz
180-264 V, 60 Hz
90-132 V, 50 Hz
180-264 V, 50 Hz
90-132 V, 60 Hz
180-264 V, 60 Hz
90-132 V, 50 Hz
180-264 V, 50 Hz

9.3 EASY IDENTIFICATION OF LOGIC BOARDS
There are three possible Logic Board models that can be installed in a DECwriter: M7722, M7723 and M7728.
The M7722 board is typically factory installed in earlier LA36s while the M7723 and M7728 boards are found in
newer terminals. The M7728 performs all functions of the M7722 and M7723 and is backward compatible for a
direct replacement for either board. Replacing either board with an M7728 does not enhance the capabilities of
the terminal in which the M7728 board is installed.
Figure 9-1 shows the obvious physical differences between the three Logic Boards that permit easy identification.
The M7722 and M7723 boards each have four connectors while the M7728 has five connectors. The M7723 and
M7728 boards have solder dot test points around the perimeter and the M7722 does not have these test points.

SOLDER DOTS
TEST POINTS

.................
M7 722

M7723

M7728

LOGIC BOARD

LOG IC BOARD

LOGIC BOARD

...................
5
4

CONNECTORS

CP-2391

Figure 9-1

Physical Characteristics of M7722, M7723, and M7728 Logic Boards

9.3.1 Major Functional Differences Between M7722 and M7723 Logic Boards
There are three major functional differences between the M7722 and the M7723 Logic Boards:
l.

Local Copy Feature
M7722 - No local capability when terminal is operating on-line (sometimes called half-duplex mode)
M7723 - Has local copy feature. Three-position front panel rocker switch permits printing when in
local or on-line in half- or full-duplex mode.

Parity Selection
M7722 - No received parity capabilities. Only even or no parity selection on transmission. No eighth
bit spacing capability.
M7723 - Choice of even or odd parity for both receiving or transmitting.

Paper Out Option
M7722 - No provision for accepting the Paper Out Switch.
M7723 Compatible with Paper Out Switch.

9.3.2 M7723 Jumper Configurations
Figure 9-2 shows the location and function of all jumpers ori the M7723 Logic Board.

9-2

Jumper Configurations for M7723 Logic Board
Function

W9 WI3 Wl4

Full-Duplex Active

Full-D upl ex Passive

Passive Receive/
Active Transmit

Active Receive/
Passive Transmit

Half-Duplex Active*

Half-D uplex Passive*

*Con nect user-ma nufactured cable between 13-3 an d 5 an d operating system .

Function

8th BIT MARKING
8th BIT SPACING
EVEN PARITY
ODD PARITY

WIO

Wll

WIS

0
0

x
x

I
I

0
I

Legend :

x
W10

W13

W14

I = Jumper Installed
0 = Jumper Not Installed
X = Do Not Care
- Standard Bell Volume
WI Installed
WI Not Installed - Lower Bell Volume
W I2 Not Used
- No Function

Figure 9-2 Locat ion of Ju mpe rs on
M7723 Logic Boa rd

9- 3

9.3.3 Functional Differences Between M7723 and M7728 Logic Boards
In addition to having all the features of the M7723 board, the M7728 can also provide the data and signal
interface required when options are installed in an upgradable LA35/LA36. The M7728 has the same possible
transmit and receive parity configuration as the M7723. In addition, the received parity error print indication
(three vertical bars) can be suppressed in certain instances when the eight level bit is used as a control code for the
options.
9.3.4 M7728 Jumper Configurations
Figure 9-3 shows the location and function of all jumpers on the M7728 Logic Board.
9.3.5 M7728 Cabling Configurations
The possible cabling configurations for the M7728 Logic Board are shown in Figure 9-4.
CAUTION
The ribbon cables between the Logic Board and the
Expander Board must be installed so that one cable end
(either end) has the ribbed side of the cable facing up and
the other end has the smooth side up. Ensure that A con~
nects to A at each cable end. Failure to observe this polarity may cause a Logic Board failure.
9.4 MAJOR POWER SUPPLY CHANGES
There are four major changes to the power supply:
1.

The rating of the ac line fuse was increased from 2 A SB to 3 A SB for 115 V and from 1 A SB to 1.5 A
SB for 230 V.

The two 1 A SB fuses in the line feed motor drive circuit were replaced with four 3/4 A SB fuses.

The 18000 ,uF capacitor in the capacitor bank was replaced with a 37000 ,uF capacitor.

A Constant Voltage Transformer (CVT) replaced the original power transformer.

9.4.1 New Power Transformers
Upgradable LA35/LA36s have constant voltage power transformers installed to accommodate the increased
power requirements of the options. There is a unique transformer model for 50 Hz operation and another model
for 60 Hz operation. Both models function on either I I5 or 220 Vac primary voltage and provide ±24 and +I I
Vdc at the secondary.
9.5 NEW KEYBOARD BEZELS
The keyboard bezel associated with the upgradable LA36 is shown in Figure 9-5. There is no change in the bezel
for upgradable LA35s. The LA36 also has another bezel configuration that accepts the 14-Key Numeric Keypad
Option which mounts to the right of the standard keyboard.
9.6 CAPS LOCK KEYBOARD
The Caps Lock Keyboard has a CAPS LOCK key substituted for the SHIFT LOCK key normally found on
office equipment. When the CAPS LOCK is depressed, the 26-letter keys transmit only upper case codes; all
other keys print in lower case.
9.7 LA35/LA36 OPTIONS
All options listed in Table 9-I can be installed in a LA35/LA36 DECwriter except for the I4-Key Numeric
Keypad and the Paper Out Options.

9-4

Jumper Configurations for M7728 Logic Board
Function

ws W6 W7 W8 W9 WJ3 Wl4

Full-Duplex Active

Full-Duplex Passive

Passive Receive/
Active Transmit

Active Receive/
Passive Transmit

Half-Duplex Active*

Half-Duplex Passive*

W16

W17

*Connect user-manufactured cable between J3-3 and 5 and operating system.

Function

WIO

Wll

WIS

0
0
I
I

x
x

0
I

x
x

8th BIT MARKING
8th BIT SPACING
EVE PARITY
ODD PARITY
Legend:
I = Jumper Installed
0 = Jumper Not Installed
X = Do Not Care

W12

WIS

Wl9

W20

Print Parity Error Indication

Eight Bit Control Over Options
(No parity detection)

Function

WI Inserted
WI Not Inserted
WI 2 Inserted
WI 2 Not Installed
WI 6 Not Used
Wl7 Not Used

W14 W4

- Standard Bell Volume
- Lower Bell Volume
- Print all characters typed whether LOCAL or ON LINE
in Full or Half Duplex
- Position of FDX / HDX switch establishes whether
transmitted characters are printed
- No Function
- No Function
Figure 9-3 Location of Jumpers on
M7728 Logic Board

9-5

TO J1
POWER BOARD

20mA SERIAL
INPUT (IF USED)
20mASERIAL - - - INPUT (IF USED)

EIA INPUT
(IF USED)

TO J2 FRONT
CONTROL
BOARD

~---+-- PANEL

M772B LOGIC BOARD
M772B
LOGIC BOARD
EXPANDER MOUNTING
OPTION ( LAXX- LBJ

A. NO OPTIONS INSTALLED

B. ANY OPTION
AND AUTO LI NE FEED OR AUTO ANSWER BACK OPTIONS
NOT INSTALLED
\Q
I

O'I

TO J1
POWER BOARD
20mA SERIAL
INPUT (IF USED)

EIA INPUT
(IF USED)

TO J2
~---1--PANEL

FRONT
CONTROL

BOARD
M7728
LOGIC BOARD
EXPANDER MOUNTING
OPTION
(LAXX-LBl

C. ANY OPTION AND
AUTO LINE FE.'EDOR AUTO ANSWERBACK OPTIONS INSTALLED
C P-2102

Figure 9-4 Cabling Configurations for the M7728 Logic Board

POWER

I o•
f""''°•

OFF

f-- MOD£ ---f- BAUD RAT£ -i
UN(

LOC•

HOX•

CH.tA

SET

'°''

CHAlt

£SC
!SEU

AUTO

Hf RE

CTRL

CAPS
LOCK

SHIFT

w
A
s

lOO

(Q>

z x c v

T
8£Ll

)

[

SPA.CE

I
\

.....

(

LIO£
fEEO

811.(U.

onm
\

R£l0Rll

?
I

&Kin

WUT
\

STD

ALT
PAPER DEVICE SELECT
CHARACTER SET OUT SELECT AVAIL

7622 -28

Figure 9-5

LA36 Keyboard Bezel

9.8 UPGRADED LA36 FUNCTIONAL DESCRIPTION
The following LA35 / LA36 printers are designated as option-upgradable DECwriters.
LA36 Manufactured in U.S.A. - Serial numbers 02-21933 and higher
LA36 Manufactured in Ireland - Serial numbers 04-10450 and higher
LA35 Manufactured in U.S.A. - Serial numbers 5001 and higher
These printers have the increased power supply capability and the M7728 Logic Board required to accommodate
the various available options.
The basic block diagram for the M7728 Logic Board is shown in Figure 9-6. The major difference between this
diagram and the diagrams for the M7722 and M7723 boards is in the Data Conversion Block. All other functional areas operate in the same manner as in the other boards. The three items added to the data conversion are are:
I.

2.
3.

Expander Board
Options
Tri-State Buffer

The Data Conversion Block still performs its basic function of taking Serial In (SI) ASCII data and converting it
to a 7 X 7 dot pattern that drives the print head. Transmitted keyboard data is converted to Serial Out (SO)
ASCII data by the Data Conversion Block . These functions do not change in an upgradable printer; only now,
certain options exer"cise control over both the receive and transmit data lines by blocking, inserting, or allowing
data to pass.

9-7

Table 9-1
LA35 /36 Options

Options

Name

Control
Switch/Indicator

LAXX-LB

Expander Option

None

The Expander Option Mounting Kit
includes the logic, cables, and mounting
hardware required to expand the LA36 to
include options LAXX-LA, LAXX-KV,
LAXX-KW, LAXX-KX, LAXX-KY,
and LAXX-PK.

LAXX-PK

APL/ ASCII Dual
Character Set

ALT CHAR SET,
CHAR SET LOCK,
and STD/ALT
CHARACTER SET
Indicators

This option provides an APL alternate
character set for use with the standard
character set in the LA35 /LA36.

LAXX-LA

Auto LF After CR

AUTO LF

When the AUTO LF switch is activated,
the printer will automatically insert a line
feed after each carriage return code typed
during transmission. The LAXX-LA
option can also be configured to execute a
line feed after each received carriage
return code. Any combip.ation of these
options can be used.

LAXX-KV

Top of Forms
Control

FORMS LENGTH
Switch and SET TOP
OF FORM
Pushbutton

Controls mounted under the top cover
provide the operator with a method of
selecting the length of the paper to be
used. After the desired setting is selected·
and the paper is lined up for proper vertical alignment, the operator presses the
SET TOP OF FORM switch so that the
internal logic will be preset to the paper
length defined by the operator.

LAXX-KW

Selective
Addressing

DEVICE SELECT
and SELECT AVAIL
Lamps

The Selective Addressing Option allows
the LA36 to communicate with other terminals on a single data communications
channel.

LAXX-KX

Auto Answerback
and Auto LF
Options

HERE IS, AUTO LF

The Automatic Answerback Option
allows the terminal to transmit a preprogrammed message of 20 characters
(maximum). The message is initiated by
pressing the HERE IS pushbutton, or
upon receipt of the ENQ control code
from another device. The LAXX-KX also
incorporates the features of the Auto LF
option (LAXX-LA).

9-8

Description

Table 9-1 (Cont)
LA35 /36 Options
Control
Switch/Indicator

Options

Name

LAXX-KY

Forms Control and
Vertical and
Horizontal Tabs

Keyboard Keys

The Forms and Tabbing Option enables
the terminal to set horizontal and vertical
tab positions either locally or via the system software. This option also
incorporates features of the Top of Forms
Option (LAXX-KV) and operates in the
same manner.

LAXX-LG

EIA/CCITT
Interface

None

The LAXX-LG interface provides the
user with an RS/232-C interface with
modem control and includes a 9-ft (3.54m) cable terminated with a standard EIA
connector.

LAXX-KH

DFl 1 Mounting
Kit

None

The DFl 1 Mounting Kit enables the user
to mount one of the DIGITAL series
DFl l Communication Options in the
LA36.

LAXX-KJ

Compressed Font
Option

None

The Compressed Font Option is a
mechanical option that provides the LA36
with the ability to print 132 columns on a
form 8-1/2 in. (21.59-cm) wide.

LAXX-KX*

14-Key Numeric
Keypad

Keyboard Keys

The 14-Key Numeric Keypad is located to
the right of the keyboard and provides the
operator with a convenient method of
entering mathematical number sequences.

LAXX-LZ**

Paper Out

PAPER OUT
Lamp

Provides a visual indication for a paperout condition. Prevents keyboard and
received data from printing.

LAXX-LC

TTL to CCITT
(V28) Converter
and Modem
Protector

None

The TTL to CCITT (V28) Converter and
Modem Protector is a BPO DATEL services interface that meets the requirements
of CCITT (V28) with BPO-required modem protection circuitry.

LAXX-LH

Current Loop
Cable

None

20 mA current loop with Mate-N-Lok.

LAXX-LK

Current Loop
Cable

None

20 mA curt'ent loop with 4-pin plug for
DEClO.

*Not available on the LA35
**Standard on the LA35

9-9

Description

Table 9-1 (Cont)
LA35 /36 Options

Options

Name

Control
Switch/Indicator

LAXX-KG

EIA Interface

None

The LAXX-LG interface includes a 9-ft
(3.54-m) cable terminated with a standard
EIA connector (no modem control
features).

LAXX-LN

Scale, Pointer,
and Window
Kit

Column scale,
Line Indicator, and
Column Pointer

Operator convenience items that assist in
positioning the print head on preprinted
forms and in locating horizontal tabs.

LAXX-LM

Acoustic Coupler

Carrier Detect
Lamp

Provides a data interface between DECwriter and standard telephone handset.

Description

The control logic for the M7728 board is shown in Figure 9-7. As stated previously, there is no difference in the
operation, configuration, or programming of the Microprogrammed Controller. New identification numbers are
assigned to the components and their physical location on the circuit board are changed, but the basic function of
each remains the same. The new numbers and schematic sheet locations are noted on Figure 9-7.
The major area of change effects the receive and transmit data paths.
9.8.1 New Transmit Path
Keyboard data now passes through the Expander Board before it is applied to the transmit section of the UART.
As this data is routed across the Expander, two switching methods are employed to ensure that installed options
can break this data path and insert characters into the transmit data. This keyboard steering is shown in Figure 98. Hardware steering is accomplished by physically moving the cable to the UART between connectors J1 and J2
on the Expander Board. When inserted in J2, keyboard data and the keystroke is routed right across the Expander without any interruptions. When the Automatic Answerback Option or the Automatic Line Feed Option is
installed, the cable is moved to J l and the data path is now through these options. There is a logic switch in these
options that allows the options to break the keyboard data path and insert either an answerback message or a
line feed command. After inserting the option-generated characters and keystrokes, the logic switch allows keyboard data to pass out to the UART again.
9.8.2 New Receive Path
On the M7728 board, received data and parity error are routed through the UART to the Tri-State Buffer rather
than right to the Character Buffer as on the M7722 and M7723 boards. This Tri-State Buffer permits the options
to sample the UART output data before the Character Buffer receives it. The options monitor the incoming data
on the bi-directional line and can insert data on this line to be applied to the Character Buffer. The output of the
Character Buffer can be sampled by an Optional Character Set Option which can substitute a new dot matrix
pattern for the pattern normally generated for this character by the Character Generator ROM.

9-10

SET/CLR

BEL

2. 4 KHz

LF/LF HOLD
MIRCRO-

c~~g~~L

,.____1._6_B9_6_M_H_z_ __. PROGRAMMED
CON TROLLER

BELL
SYSTEM

LINE FEED
STEPPER
SYSTEM

..__..:.CA:..;.R:..;.R.:...Y:...:/...cB::.;O:.:.R.:.:.R:...:0:..;.W;._.:.:.IN:...:Cc..:R.=E.:.cM.=E:..:.NT'--~

CMPC)
SPEED DATA
DATA BUS

CARRIAGE
SERVO
SYSTEM

f--

(/)

:;)

CHARACTER
ADDRESS

a:i

;:!

I
-1

r'OA-rr- - , roATA I COMMUNICATIONS
I CONVERSION

INTERFACE

SERIAL
INPUT

SERIAL
OUTPUT

I
L

I
II

RIBBON
DRIVE
SYSTEM

ADDRESS
REGISTER

RECEIVE
LOOP

PRINT HEAD
SYSTEM

~-- - ...J I
I
I

UART

TRANSMIT
LOOP

COLUMN INCREMENT COUNT
EXPANDER BOARD

I
I

OPTIONS

_____ J

L
ti

KEY
STROBE

(/)

"'
KEYBOARD
SYSTEM
CP- 2333

Figure 9-6

Basic Block Diagram of M7728 Logic Board

9-11

ADDRESS

512XB
CONTROL
ROM
E15
CMPC3l

CONTROL~!--+-~~~ :~g~~~~
(MPC 3 l

4 BITS

-1

REG

4 BIT
REGISTER
(REQ)
ES (MPC4)

ZERO
DETECTOR
E4 (MPC4)

BITO
BIT 1
BIT2
BIT3

SET BELL
CLR BELL

BELL
SYSTEM
(MPCB)

2.4 KHz

LOAD DAC
CARRY (Cl
BORROW(Bl

LINE FEED
STEPPER
SYSTEM
Ct-lPCBl

INC
LOAD C.B.
ADDRESS

3 BIT COLUMN INCREMENT COUNT

CHARACTER
BUFFER
ADDRESS
REGISTER

PNTABL

SET HOE---~

CLR DA
1024 X B
CHARACTER
GENERATOR
ROM E48,
E53(MPC9)

TRI-STATE
BUFFER
E46 E51
(MPC6)

SERIAL
OUTPUT
SERIAL
INPUT
XMT
ROY L

1-----•'
DOT MATRIX

DOT
MATRIX ..---~---

EX PANDER BOA.RD AND OPTIONS

OPTIONAL CHARACTER SET
CR

OPTION CLOCK

CLR DA

BELL

DA
CP-2334

Figure 9-7

M7728 Control Logic Diagram

9-12

UART

I
SERIAL
OUT

I
I

XMIT
- - - -.... SECTION

-------------- --------1

KEYSTROBE

I
I

EXPANDER
OPTION
MOUNTING
BOARD

AUTO LINE FEED
LINE
FEED
CONTROL

LINE

KEYBOARD

KEY
,____ ___. BOARD

/ /"'I

DATA
ANSWER
BACK
MESSAGE
GENERA10R

/ "

II
I
I
I
I
I

ANSWER
BACK
CONTROL

AUTO ANSWERBACK

L
CP-2335

Figure 9-8 Steering of Keyboard Data

9-13

9.8.3 Transmit Operation with Options Installed
Options that insert data into the keyboard data path between the keyboard and the transmit section of the
UART require a timing control signal to ensure that the UART is ready to accept more data. This control signal
is the XMIT RDY L signal which is a high level when the UART is not ready to accept another character and is
low when another character can be processed. This signal is used to stroke both the option-generated character
and keystroke out of the option. The XMIT RDY L signal associated with the last chaaracter generated by the
option causes the logic switch to revert back to the normal position and allow keyboard data to pass again.
9.8.4 Receive Operation with Options Installed
Figure 9-9 shows the signals and components that effect the receive operation. After the UART converts
incoming serial data into seven parallel bits, it places these bits on the data lines to the Tri-State Buffer. Normally, as the UART is ready to output data the DATA AVAILABLE (DA) line goes to a low level. The
microprocessor uses this low level to load the seven bits into the Character Buffer. In the M7728 board this DA
signal is applied serially through all receive options before it is sent to the microprocessor.
At each option the DA signal initiates an option-decoding function on the character present on the bidirectional
lines from the Tri-State Buffer. If the character is a command or code that is not recognized by the first option,
the DA signal is passed along to the next option to be used to decode the character at that option.
After being routed through all options to the microprocessor, the character is loaded into the Character Buffer
through the Tri-State Buffer. The remaining processes to the print head ai;e the same as in the M7722 and M7723
boards.
If the character present at the output of the UART is decoded by an option, this option blocks the data through
the Tri-State Buffer (using the UART ENAB signal). The option then places a character on the bidirectional
lines to the Character Buffer and issues the DA signal to the microprocessor. As before, the microprocessor
commands the Character Buffer to load, but now the character loaded is taken from the option, not from the
UART through the Tri-State Buffer.
After processing a character, the microprocessor issues the CLEAR DATA AVAILABLE (CLR DA) signal
which causes the UART to place the next incoming character on the lines to the Tri-State Buffer. If an option is
going to insert more than one character (as when performing a top-of-form operation), the option holds the TriState Buffer disabled, places another character on the bidirectional line and issues another option-generated DA
signal. This action continues until the option has finished inserting characters. The CLR DA signal associated
with the last character inserted enables the Tri-State Buffer and received data now passes through in a normal
manner.

9-14

r----

M112a LOGIC BOARD
UART

SERIAL
IN

(

7 BITS

RECEIVE
SECTION

TRI-STATE UARTDATABITS1-7
DA

BUFFER

CHARACTER
BUFFER

TO
CHARACTER
GENERATOR
ROM

CLR
DA

\
I

_,\

MICROCONTROLLER

L..- Bl-DIRECTIONAL
LINES

~X;;E;;T;;1MOUNTING BOARD

I
I

UART ENAB

DATA AVAILABLE

ALL OPTIONS
IN RECEIVE
PATH

CLR
DA

OPTION
DA

CLEAR DATA AVAILABLE

L---

CP-2336

Figure 9-9

Receive Operations of M7728 Logic Board

9-15

CHAPTER 10
COMPRESSED FONT OPTION KIT (LAXX-KJ)

10.1 INRODUCTION TO COMPRESSED FONT
The Compressed Font Option permits a DECwriter to print 132 characters on a 8-1/2 in. line. (Normally, the
DECwriter prints 132 characters in 13.2 in.)

The option does not make any electrical or functional changes to the basic operation of the DECwriter. Only
slight mechanical changes are required to modify the character spacing along a line. These changes include
replacing the two timing pulleys with new pulleys having a greater number of teeth and installing a timing belt
that matches these new pulleys.
All timing sequences and printing speeds remain the same. The printed characters retain the same vertical height;
only their horizontal width is decreased.
10.2 LAXX-KJ PRINT SET
The figure at the end of this chapter is the LAXX-KJ print set.

10-1

NOTES•
I. SPACE AT END OF SCREW TO SE -LESS
TMAN .010 INCHES

2. PULLEY (ITEM e) USES SAME CLAMP
AS PRE"SENTLY VSEO
3. ITEMS 2 IS tJSED ONLY TO tJP&RADE
tJNITS WITH tJNREVISEO SIDE PLATES

l GROMMET, STRIP. .70 L6.
I PULLEY. TIMING, 30 TEETH

2 NUT KEP "'I0-32

LA"!tO
DEC.WRITER ll

MATERIAL

--~

SEE PARTS LIST

10-2

900703G-OO
1212446-00

CHAPTER 11
FORMS CONTROL OPTION KIT (LAXX-KV)

11.1 FORMS CONTROL INTRODUCTION
The Forms Control Option adds a top-of-form capability to a DECwriter. The primary function of the option is
to locate the top of form by monitoring the number of line feed actions performed by the printer mechanism.
Then, when commanded by a form feed code, this option issues the correct number of option-generated line feed
(LF) codes required to advance the paper to the next top of form.
The option samples data out of the UART and performs all internal incrementing, resetting, and line feed
generating functions before the character is passed on to the Character Buffer for normal terminal action.
11.2 FORMS CONTROL FUNCTIONAL DIAGRAM
Figure 11-1 shows the Forms Control Option in a typical installation. The Forms Control Assembly is physically
attached to the right side of the printer mechanism and the circuit board is connected by an edge connector at
location B of the Expander Option Mounting Kit. A cable harness connects the two assemblies. At each end of
this harness is a Mate-N-Lok connector and a pair of Faston terminals. One connector is connected to Jl on the
option circuit board, the other end to the FORMS LENGTH switch on the Forms Control Assembly. The
Faston terminals connect to lugs on the SET TOP OF FORM switch and lugs on the option circuit board. The
FORMS LENGTH switch is a 12-position rotary switch and the SET TOP OF FORM switch is a momentarycontact pushbutton. Each position of the FORMS LENGTH switch represents the length (in inches) of a preestablished format (such as a preprinted form) that can be used with the option. In normal operation, the
FORMS LENGTH switch is set to the length of the.form being used; then the SET TOP OF FORM switch is
depressed to load this value into the Counter on the option circuit board.
Data processed by the UART, whether incoming SI or locally generated at the keyboard, is available at location
B on the Expander Option Mounting Board. The option monitors this data for either a line feed code or a form
feed code. All other codes or characters do not effect the option.
When a line feed code is detected (indicating that the paper will advance one line), the Counter holding the form
length value is incremented by one line. Each successive line feed code increments the Counter until its value
equals the preset value established by the FORMS LENGTH switch. At this point the print head is at the top of
the next form and the Counter is automatically preset with the value of the FORMS LENGTH switch again.
When a form feed (FF) code is detected by the option, four major events occur:
I.

2.
3.
4.

UART is disabled.
Line Feed Code Generator is enabled.
Counter is incremented.
Option-generated Data Available (DA) signal is sent to the Character Buffer.

11-1

------,
I
I

S.I.--1,___ _ _ _ __
CHAR
BUFFER

S.0.:4--tt--------1

___ J
,, ',
____.,... r•
I

KEYBOARD

-- -

EXPANDEROPTION

I
I
I

I
I
I I....
I
I
I
I

_______ .J

SETIOP

IOTRM

FORMS CONTROL OPTION
LAXX-KY

I
I
I
I
I
I
I
I
I
I

FF
DETECTOR

LF
DETECTOR

COUNT
FULL

INCREMENT
LOAD

FF
CONTROL

COUNTER

SWITCH SETTING

INCREMENT

LF COO£
GEN

L ------------

_J
CP-2343

Figure 11-1

Forms Control Functional Block Diagram

11-2

The option holds the UART disabled, continues to generate line feed codes, and increments the Counter until the
count overflows. At this time the printer mechanism is at the top of the next form and the following three events
occur:
1.
2.
3.

Counter is preset to the value of FORMS LENGTH switch setting.
Line Feed Code Generator is disabled.
UART is enabled.

With the UART enabled again, data passes from the UART to the Character Buffer and the option monitors for
line feed and form feed codes.
11.3 FORMS CONTROL BASIC BLOCK DIAGRAM
The basic block diagram for the Forms Control Option is shown in Figure 11-2. This diagram is a simplified
representation of the forms control circuit schematic (D-CS-M7735-0-l). Circuit designations and pin numbers
indicated on Figure 11-2 correlate with corresponding components on the schematic. Buffers, inverters, and
other components that do not have major operational functions are omitted from the block diagram.

LOC

RESET
CONTROL
E11

1 SRC
2

11 FFS + LF 5

8 LF 12

LF
DECODER

SRB 4

E11

SRB

INCREMENT 6
CONTROL

COUNTER 12

E11

FULL COUNT

ES, E12

FFS

TOF

SRB

FF
1-'6'-----~
DECODER
E3

FROM
LOGIC
BOARD

SRB lO

AND
E7

LF
CODE
GEN

UART DISABLE

FFS
DATA AVAIL

TIMING
SEQUENCER

SRA
SRB
SRC

SRO

9
10

OR
E11

CP-2344

Figure 11-2 Forms Control Basic Block Diagram

11-3

The Forms Control Option can be divided into the following three functional areas:
l.
2.
3.

Counter Circuit
Option Timing
Operational Sequences

11.3.1 Counter Circuit
The Counter circuit consists of the following four units:
l.
2.
3.
4.

Counter (E8 and El2)
Increment Control (El 1)
Reset Control (Ell)
SET TOP OF FORM and FORMS LENGTH Switches on Forms Control Assembly

The Counter chips (E8 and El2) form a 256-bit (line) up counter that is incremented by a low signal transition on
E8-8. The Counter accepts one of 12 preset values as determined by the position of the FORMS LENGTH
switch. Each switch position loads a number that is 128 minus the maximum number of lines on a specific form.
For instance: if an 11-in. form is to be used, the FORMS LENGTH switch is set to position No. 11 and the SET
TOP OF FORM switch is depressed. On an 11-in. form, the maximum number of printable lines is 66 (11 in.
times 6 lines per inch). The 256-line Counter is preset with 62 lines from switch position No. 11, leaving 66 lines
to be filled. Each line feed code received by the option increments the count upwards by one line. So, if after
printing 45 lines (45 line feed codes received) a Top of Form command (form feed code) is received, the paper
must be advanced 21 lines to reach the top of the next form. As the option generates these 21 line feed codes, the
Increment Control Ell increments the Counter. When the Counter overflows (after 128 increments: preset value
plus the number of option-generated line feed codes), the Reset Control Ell reloads the value of the FORMS
LENGTH switch back into the Counter again.
11.3.2 Option Timing
The Timing Sequencer E9 establishes all control timing for the Forms Control Option. The timer is a 4-bit shift
register that produces the following four sequential timing signals at the designated outputs:
pin 5; SRA
pin 7; SRB
pin 9; SRC
pin 12; SRD
A high level signal on the LD and SHF pins (1 and 13) of E9 cause the high level at pin 4 to be shifted right at the
rate of the Option Clock input at pin 6 (approximately 1.2 µs per shift). Either the Data Available signal from the
UART or the Form Feed Stored signal from FF flip-flop E4 activates the Timing Sequencer.
The following events occur at each of the four sequencer outputs:
Time

Event

SRA

• Not used - but provides a 1.2 µs delay for data stabilization

SRB

•
•
•
•

SRC

• Reload Counter

SRD

• Issue Data Available signal to Character Buffer

Decode line feed code
Decode form feed code
Increment Counter
Enable Line Feed Code Generator

Figure 11-3 shows the timing sequence for the Forms Control Option.
11-4

SRB TIME

DETECT LF OR
FF CODE
INCREMENT
COUNTER E11-6
ENERGIZE LF
CODE GENERATOR E5 - - - - - - - - - - - '

SRC TIME _ _ _ _ _ _ _ _ _ __.,C,......__ _ _ _ _ ___,,
LOAD TOF

SRO TIME
OPTION-GENERATED
DATA AVAILABLE

-------------~,...,'-------!
1------'

CLEAR DATA
AVAILABLE
CP-2345

Figure 11-3 Timing Sequence for Forms Control Option

11.4 OPERATIONAL SEQUENCES
The Forms Control Option has three basic operational sequences that are dependent on what character is being
sent by the UART. These are:
1.
2.
3.

Receive any character but line feed code or form feed code
Decode a line feed code
Decode a form feed code

11.4.1 Any Character Received
Figure 11-4 shows the operational sequence performed when any character is received. When the option receives
a Data Available signal from the UART, a character code is present on the data lines at location B. If this code is
for any character, but neither a line feed nor form feed code, the only action on the option is the initiation of the
Timing Sequencer by the Data Available signal. At SRD time (approximately 4.8 µs after receiving the Data
Available signal) the option issues the option-generated Data Available signal which is sent to the microprocessor. The character can now pass out from the UART in a normal manner.
11.4.2 Line Feed Code Decoded
Figure 11-5 shows the operational sequence performed when a line feed code is received. A line feed code and
Data Available signal from the UART are decoded during SRB time by LF Decoder E3. The output from pin 8
of the LF Decoder is applied through the Increment Control Ell to the Counter ES and El2. Each line feed code
increments the Counter by one line. If the Counter increments to a full count, which indicates having reached the
top of the next form, the Counter outputs a TOF signal on pin 12. This TOF signal is '1sed at SRC time to reset
1
the Counter with the value set by the FORMS CONTROL switch.
11-5

DATA FROM UART

ANY CHARACTER
FROM UART
(EXCEPT LF OR FFI

START TIMING
SEQUENCER

ATSRC RESET
COUNTER

AT SRO TIME
ISSUE DATA
AVAILABLE

ATSRDISSUE
DATA AVAILABLE

SEQUENCE COMPLETED

SEQUENCE COMPLETED
CP-2346

CP-2347

Figure 11-4 Forms Control Operational Sequence
When Any Character Received

Figure 11-5 Forms Control Operational Sequence
When Line Feed Code Received

11-6

If the Counter does not overflow (no TOF signal) when incremented, no further action is taken until SRD time
when the option-generated Data Available signal is sent to the microprocessor. The Character Buffer now
accepts the line feed code from the UART and processes it in a normal manner.
11.4.3 Form Feed Code Decoded
Figure 11-6 shows the operational sequence performed when a form feed code is received. A form feed code and
the Data Available signal from the UART are decoded during SRB time by FF Decoder E3. This action initiates
the major function of the option: issuing the proper number of line feed codes to advance the paper to the next
top of form position. The output of FF Decoder E3 sets FF flip-flop EA which causes the following three actions
to occur during SRB time.
l.
2.
3.

Disables the UART (held disabled until FF sequence completed)
Enables the Line Feed Code Generator ES
Increments the Counter E8 and El2

Disabling the UART prevents incoming data from being applied to the Character Buffer and allows optiongenerated line feed codes to be sent to the Character Buffer. As the Line Feed Code Generator E5 is energized,
the Increment Control El 1 increments the Counter by one line. If the Counter increments to a full count, it
outputs a TOF signal on pin 12. This TOF signal is used to clock E4 pin 5 to a high level and to reset the Counter
with the FORMS LENGTH switch value at SRC time. At SRD time the option-generated Data Available signal
is issued and a line feed code is sent to the microprocessor. When the CLR DA signal is sent back to the option
indicating that the line feed code was processed, the CLR DA signal resets E4 at pin 1. The TOFSL signal
generated when E4 resets causes the FF flip-flop E4 to reset also.

If the Counter does not overflow after being incremented (no TOF signal), the FF flip-flop E4 remains set,
holding the UART disabled and the Line Feed Code Generator E5 enabled. The CLR DA signal returning after
the first line feed code was processed resets the Timing Sequencer. But because the FF flip-flop is still set, the
Form Feed Stored (FFS) signal immediately restarts the Timing Sequencer again. At SRB time, the Counter is
incremented again and the Line Feed Code Generator issues another line feed code. If this increment still does
not overflow the Counter, the line feed code generation sequence is repeated again and again until the TOF signal
is present at pin 12 of the Counter. When the CLR DA from the last LF returns, the Counter resets and the
option removes the disable from the UART and disables the Line Feed Code Generator E5. The option has
completed the top of form sequence and is now waiting for line feed or form feed codes before starting any action

11.5 TROUBLESHOOTING
The troubleshooting chart in Table 11-1 lists the common trouble symptoms that could be observed during
installation checkout or normal operation.
11.6 LAXX-KV PRINT SET
Figure 11-7 is the supporting diode matrix for the LAXX-KV print set. The print set is shown at the end of this
chapter.

11-7

DATA FROM UART

1. DISABLE LF
CODE GEN
2. RESET TIMING
SEQUENCER

1. RESET,E4
2. ENABLE UART
NO

STORE FF
COMMAND
START TIMING
SEQUENCER
DURINGSRB
1. DISABLE UART
2. ENABLE LF
CODE GEN

ENABLE
LFCODE
GENERATOR

INCREMENT
COUNTER

LF LOOP
FF SEQUENCE
COMPLETED
NO

DURINGSRC

1. RESET COUNTER
2. STORE TOFSL
COMMAND IN E4

AT'SiiD.
ISSUE DATA
AVAILABLE

CP-2348

Figure 11-6 Forms Control Operational Sequence
When Form Feed Code Received

11-8

Table 11-1
Troubleshooting for Forms Control Option Kit (LAXX-KV)
Symptom

1. After installation improper
operation or no operation
of terminal

2. Terminal does not advance
to TOF when CTRL L or
FF is received

Problem Area

Probable Cause

Action

Cabling

Wrong cabling connections

Check all cabling between
M7728 Logic Board, Expander Board, and TOF
Assembly beneath top _cover

Option location

Option inserted in wrong location on Expander Board

Install TOF option in locations A and B

Data Available
signal distribution

Signal path interrupted

Check for Data Available
signal at El 1 pin 10 and at
E9 pin 12 for the output

D-CS-M7735-0-l,
Sheet 3

Form Feed Decoder

FF not being decoded

Check E3 pin 6 for indication
of FF code

D-CS-M7735-0-1,
Sheet 2

LF Code Generator

LF code not being generated

Check ES and E2 for the LF
code

D-CS-M7735-0-1,
Sheet 2

Reference
Figure 9-4

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J~ ~ ~ 8 ~ ~ ~
;3

BINARY PATTERN/FORMS LENGTH SELECTED

Figure 11-7 LAXX-KV Form Feed
Diode Matrix

11-10

J1 M7735
Sheet 3 of 3

NOTES:

1
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11-13

CHAPTER 12
SELECTIVE ADDRESSING OPTION (LAXX-KW)

12.1 SELECTIVE ADDRESSING INTRODUCTION
The Selective Addressing Option allows a DECwriter to communicate with other terminals in a multipoint
communications network. Generally, it operates in conjunction with the EIA Interface Option (LAXX-LG) and
the Automatic Answerback Option (LAXX-KX) to provide the user with a versatile network that is easily
configured to receive or transmit data to and from each terminal.

The Selective Addressing Option has two primary functions in the terminal in which it is installed:
1.

To allow or inhibit the terminal from transmitting data out from the keyboard.

To allow or inhibit the terminal from responding to received data.

12.1.1 Transmit Conditions
A terminal is able to transmit (transmit enabled) when it is the master in the communications network or when it
is a uniquely selected slave that has been addressed by the master using its unique address code. As the master,
the terminal can select which slave terminals are going to receive and print messages sent from the master's
keyboard. When operated as an uniquely selected slave, the terminal's keyboard is activated and two-way conversation can take place between the master and this slave. Only one uniquely selected slave is transmit enabled
in the network at any one time and it is always the last slave terminal selected by the master. All other slaves in
the network are transmit disabled.

12.1.2 Receive Conditions
The ability of a slave terminal to receive data transmitted by the master is determined by the address class of the
terminal. There are three possible address classes for each terminal that permit received data to print.
1.

Broadcast Slaves - All terminals in the network receive data transmitted by the master.

Group Select Slaves - Group Address is established by setting switch S2 on the option circuit board.
All slaves with the same Group Address receive data transmitted by the master.

Unique Select Slaves - Each terminal can have a Unique Address which is different than its Group
Address and is established by the setting of switch Sl. When addressed by the master using this
Unique Address, it is possible to have communications between these two terminals and no other
terminals in the network. In addition, the master can sequentially address multiple Unique Addresses
to form a specific group that receives data from the master.

A terminal prints transmitted characters if it is selected as a slave and is not in the address mode. If not selected,
all received characters are automatically converted to the non-printing, non-spacing ACK code. The only exception is if the terminal is in the address mode and an ENQ code is received. This code is not converted to an ACK
but is allowed to pass through the Selective Addressing Option to the Answerback Option where it is used.

12-1

12.1.3 Operational Modes
Slave terminals operate in either the address mode or the data mode. In the address mode, terminals respond to
codes for their Broadcast, Unique Address, or Group Address. In the data mode, slave terminals do not
acknowledge their addresses, even though the address is present on the communications line. The master terminal establishes whether the slave terminals are in one mode or the other.
NOTE
After power-up sequence, terminal is in the data mode.
Six commands (generated by five codes) are sent from the master terminal to control the operation of the slaves.
Three commands switch the slave terminal from the data mode to the addres mode:
I.
2.

EOT (CTRL D - 004 8)
ETX (CTRL C - 003 8 )

The STX (CTRL B - 002 8 ) command switches the terminal from the address mode back to the data mode. The
BELL (CTRL G - 007 8 ) configures all the slaves in the broadcast mode. The ENQ (CTRL E - 005s) code is used
with Unique Select Slaves to request the stored answerback message. It is also used to transmit disable a Unique
Select Slave.
NOTE
Refer to the LA35/LA36 DECwriter II User's Manual
for a complete description of these codes.
12.2 SELECTIVE ADDRESSING FUNCTIONAL BLOCK DIAGRAM
Figure 12-1 shows the functional block diagram of the Selective Addressing Option. Received data is monitored
at the output of the UART for address codes and mode switching commands. When in the address mode, the
terminal only responds to codes that select it to receive data. These codes are the Unique or Group Address codes
that match addresses stored in the two 7-bit dip switches or the BELL code. When the terminal is not conditioned
to receive data transmitted by the master (not selected), it disables the UART and substitutes an A CK code
(006 8 ) for each received ASCII character or command. This ACK code is a non-spacing, non-printing code that
has no effect on the terminal. As discussed in the description of the Expander Mounting Board, all incoming data
passes through the Selective Addressing Option before the other options in the terminal monitor the data.
Therefore, when the terminal is not selected to receive data and all incoming characters are converted to ACK
codes, the other options never have a chance to decode their respective commands and the terminal appears to be
off-line to the transmitted data.
When the terminal is the master or a transmit-enabled slave, the data from the keyboard is monitored by the
EOT Decoder for an EOT code. This code indicates that the transmitted message has ended and the terminal is
relinquishing the master or transmit-enable status.
The trilevel line that interconnects the EIA, Auto Answerback, and Selective Addressing Options is used to
disable the keyboard (by inhibiting the keystroke) when the terminal is a transmit-disabled slave. When the
Selective Addressing Option places an "O" level on this line (transmit disabling the terminal), it cannot be
overridden by any of the other options and the "O" level remains until the terminal becomes the master, switches
to local, or becomes a transmit-enabled slave.
The DEVICE SELECT and SELECT A VAIL front panel indicators provide a visual indication of the terminal's
status. When the DEVICE SELECT light is illuminated, it indicates that the terminal is transmit enabled. When
the SELECT AV AIL light is illuminated, the communications network is available and the terminal can become
master. When both lights are illuminated, the terminal is the master.

12-2

------------~----

rM772B-LOGlC-BOARD- -

-- - ---- --- --- -- -

-- -

s.r.----

-- ,

I
CHARCTER
BUFFER

UART

I
I

I
I
I
I

------------------~

----------------,

EXPANDER MOUNTING
OPTION BOARD
SELECTIVE ADDRESSING
OPTION LAXX-KW
KSTB
DISABLE L

I
I
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I
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CODE
GENERATOR

TRANSMIT

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CONTROL

N
I

I
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CONTROL

FUNCTION
DECODER

FRONT PANEL
DEVICE
SELECT

SELECT
AVAIL

GROUP
UNIQUE
KEY
BOARD

....___,,,

---------------1
EQT
DECODER

SELECTIVE

ENABLE/ DISABLE

ADDRESSING
LOGIC

EQT

I
I

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SEQUENCER

I
I
I

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T1

I
I

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Figure 12-1

- -

- - - - - - - - - - - - - - - - __ .J

Selective Addressing Functional Block Diagram

_J
CP·2360

12.3 SELECTIVE ADDRESSING BASIC BLOCK DIAGRAM
The basic block diagram for the Selective Addressing Option is shown in Figure 12-2. This diagram is a simplified representation of the selective addressing circuit schematic (D-CS-M7737-0-l). Circuit designations and
pin numbers indicated on Figure 12-2 correlate with corresponding components on the schematic. Buffers,
inverters, and other components that do not have major operational functions are omitted from the block
diagram.
12.3.1 Power-Up Sequence
The selective addressing power-up sequence is initiated by the WAKE UP L signal which performs the following
four events:
1.

Clocks Address flip-flop Ell at pin 3 and places the terminal in the data mode

Resets Master flip-flop Ell and places a high level on pin 8 which is applied through Faston connector A to the EIA Interface to indicate that the terminal is not the master

Resets SELECT AV AIL flip-flop ElO and places a high level on pin 8 which qualifies half of AND
gate E4 at pin 4. The low level from pin 9 of ElO illuminates the SELECT A VAIL light

Resets Device Select flip-flop El6 and places a low level on pin 5. This low level sets Xmit No. 1 flipflop ElO and Xmit No. 2 flip-flop El6

After the wake-up sequence is completed, the terminal can be configured as the master by typing CTRL D and
CTRL SPACE or as a slave (non-selected) by receiving a character from another master.
NOTE
If the terminal powered up while another terminal in the
network was transmitting, the SELECT AV AIL light
would not illuminate or flicker and the terminal would not
receive the transmitted data. The extinguishing of the
SELECT AV AIL light indicates that there already is a
master terminal established in the network. Therefore, the
terminal just powering up cannot become the master. The
terminal does not print because it was never properly
addressed; at wake up it went directly into the data mode.
All incoming characters are converted into ACK codes
which are disregarded by the terminal.
Typing a CTRL Don the keyboard produces the EOT code which is detected by the EOT Decoder El, E9, El4,
EIS, and applied to E4 at pin 5. If no characters have been received by the terminal since wake up, there is a high
level at pin 4 of E4. These two high levels qualify AND gate E4 and clock Master flip-flop Ell. Pin 8 of El 1 goes
to a low level which is applied through Faston connector A to the EIA, establishing this terminal as the master.
The low from pin 8 of Ell also sets Device Select flip-flop El6 and produces an H level on the trilevel line
(KSTBDISABLE L) through NOR El 7 and Inverter ES. As Device Select flip-flop sets, the low level on pin 6
and the H level on the KSTB DISABLE L line combine through Ql and Q2 to illuminate the DEVICE SELECT
light. The terminal has now established itself as the master in the communications network.

If after powering up and before typing CTRL D, the terminal receives a character sent by an already-established
master, the Data Available signal (DA IN L) associated with this received character starts the Timing Sequencer
El3. This sequencer is a 4-bit shift register that shifts the high level on pin 4 to the right at the Option Clock rate
(approximately 1.2 µs per shift). Between Tl and T3 the terminal can decode incoming commands. At T2 time,
the high level on pin 8 of Master flip-flop Ell (E 11 reset at wake up) is clocked through SELECT AVAIL flipflop EIO to extinguish the SELECT AVAIL light. As SELECT AVAIL flip-flop ElO clocks, a low level from pin

12-4

TO EIA
INTERFACE

LOC
E

FRONT PANEL

KSTRB

EOT
DECODER
E1,E9,
E14, E15

FROM
KEYBOARD

SELECT
AVAIL

NOT MASTER

DEFFERENTIATOR
C23,Rv

S2flllll11111

r----1
ON WHEN
E10 PIN 9LOW

SELECT DEVICE
AVAIL SELECT

1
1

<--.::.;.:_:....:.:..:....=---I_____.
8

0 •MASTER

I
I
1

L ____ .J

1; TERMINAL SELECTED

ON WHEN
E16 PIN 6 LOW
AND KSTB DIS
L AT" H" LEVEL

DEVICE
SELECT

8
E12,E18

COMPARATOR
AND

01, 02

1•XMIT ENABLE
H

FROM
UART

XMIT
ENABLE
#1
6

UNIQUE
COMPARATOR

KSTB DIS L

"X~L--+ TO LOGIC BOARD

E2,E6

8
11

LOCAL
FROM FRONT
PAN EL SWITCH

tlll 1111111
UART ENO STORED

LOC

1 •TERMINAL SELECTED

EOT
ETX

FUNCTION
DECODER
E5

ACK
CODE
GEN

NULL
ENO

E7, EB

STX

TO
CHARACTER
BUFFER

UART DISABLE L

T3
T4 (DA OUT L)
TIMING
SEQUENCER
E13

T3
T2

CLEAR DA
OPTION CLOCK - - - - - - '
DA
CP-2361

Figure 12-2 Selective Addressing
Basic Block Diagram

12-5

8 is applied to pin 4 of A ND gate E4 to inhibit any attempt by the terminal to become master by typing CTRL D
on the keyboard. At this time the terminal is not master and has not been selected as a slave (because at wake up
it went directly into the data mode not the address moe). Therefore, at T4 time AND gate E9 is qualified and
enables the ACK Code Generator E7, E8; disables the UART through E8 pin 12; and issues the option-generated
Data Available signal out of El3 pin 12. Thus, the incoming character code is converted to an ACK code and the
terminal does not respond to any data on the line. This action continues until the master ends its transmission
with an EOT code (CTRL D). This EOT code is recieved by all terminals in the network and causes the previously selected slave terminals to become deselected. The EOT indication from the Function Decoder ES is
applied through El 7 pin 9 to reset Master flip-flop Ell, SELECT AVAIL flip-flop ElO, and Device Select flipflop El6. As ElO resets, the SELECT AVAIL light illuminates and as El6 resets, the terminal becomes deselected. The EOT indication also sets the Address flip-flop Ell and applies a high to E4 pin 4. This high is inverted
once through E4 pin 11, then again through E4 pin 8, and coupled through El 7 pin 6 to combine at AND gate E9
at T3 time to disable the UART, enable the ACK Code Generator, and issue the Data Available signal at T4.
This action substitutes an ACK code for the incoming EOT code.
12.3.2 Address Mode
In the address mode, the Function Decoder ES and the Group El2, El8 and Unique E2, E6 Comparators are
monitoring the incoming data for their respective address codes. Prior to transmitting an address code the master
issues a NULL code (CTRL SPACE) which places all slaves in the address mode. The NULL code is detected by
Function Decoder ES during Tl and T3 then applied through ElS to set Address flip-flop El 1. As Ell sets, the
high level from pin S initiates the following four actions:

Disables the UART and enables the ACK Code Generator. This action takes place through E4 pin
12, E4 pin 10, El7 pin 3, and E9 pin 11. This converts the NULL code to an ACK code.

The high level enables both the Group and Unique Address Comparators, which are exclusive ORs
that compare the programmed setting in the 7-bit dip switches to the code present on the UART lines.

The high is also applied to pin 10 of AND gate E9. If either a Group or Unique Address or BELL
code is detected when the terminal is in the address mode, E9 is qualified and it clocks Device Select
flip-flop El6. This action causes the terminal to be selected as a slave.

The other location where the high level from pin S of the Address flip-flop is applied is to the D input
(pin 2) of Xmit No. 1 flip-flop E 10.

After being selected as a slave, there are four possible types of slaves; Broadcast, Group, Unique one-way, and
Unique two-way.
12.3.2.1 Broadcast Slaves -These slaves are addressed by the master using the BELL code which is detected by
the Function Decoder ES, coupled through E3 and E9 to clock El6. The low level from El6 pin 6 is applied to
Q 1, Q2, which act as both an AND gate and a Comparator. The Comparator Section monitors the status of the
trilevel line. To illuminate the DEVICE SELECT light, the trilevel line must be at the H state and the output of
El6 pin 6 must be low.

Receiving an STX code resets Address flip-flop Ell and places the terminal in the data mode. All received
characters now print.
12.3.2.2 Group Slaves - Receiving an address code that corresponds to the code setting of switch S2 produces a
group indication that is transferred through El4, E3, and E9 to clock Device Select flip-flop El6. Again the
received Group Address code is converted to an ACK code and sent on to the Character Buffer. Also all group
slaves are transmit disabled in the same manner as the Broadcast Slaves. (Trilevel line is "O".)

Decoding an STX code places the terminal in the data mode and all received characters are printed.

12-6

12.3.2.3 Unique One-Way Slaves - Receiving the Unique code that matches the Sl switch setting produces the
same action as the Broadcast and Group Address codes; the UART is disabled, the Unique code is converted to
an ACK code, and it is transferred to the Character Buffer at T4 time. In addition, the Unique code indication
resets Xmit Enable No. l flip-flop ElO, placing a low level on pin 5. This low level from pin 5 is applied through
El7 and ES to transmit enable the terminal (the trilevel KSTB DISABLE L signal goes to the "H" level providing the EIA is clear to send). The next code received is the ENQ code (CTRL E) which resets Xmit Enable No. 2
flip-flop El6 placing a low level on pin 9. To transmit disable this terminal the next character received must be
any character but a valid address. The Data Available signal for this character starts the timing sequence and at
T2 El6 clocks a high level out on pin 9. This high causes Xmit Enable No. l flip-flop ElO to clock the high level
on pin 2 (established when the terminal is in the Address Mode) out on pin 5. The high level from pin 5 of Ell is
applied through El 7 pin l to ES and forces the trilevel line to the "O" state which transmit disables the terminal.
The master then sends the STX code (CTRL B) which places the terminal in the data mode. The terminal can
now receive but not transmit back to the master.
12.3.2.4 Unique Two-Way Slaves - The master establishes two-way communications with a designated slave by
typing the Unique Address code, then the ENQ code, then the STX code. The only difference between this
configuration and the one-way configuration is that there is no character sent between the ENQ and the STX
codes. The action at the slave terminal is the same except that when the terminal goes to the transmit enable
condition as the Unique code is detected (Xmit Enable No. l flip-flop ElO resets and places a low level on pin 5)
it stays transmit enabled. The ENQ code resets Xmit Enable No. 2 flip-flop El6 in the same manner placing a
low level on pin 9 which does not cause ElO to clock. The next character received is the STX code which resets
Address flip-flop Ell and causes the terminal to switch to the data mode. As Ell resets, a low level is placed on
pin 2 of ElO. At T2 time El6 clocks, causing ElO to clock this low level out pin 5 to El7 to keep the terminal
transmit enabled (trilevel line stays at "H" level providing the EIA is clear to send). The terminal can transmit to
and receive from the master.
Figure 12-3 contains the timing diagram for the code sequence that establish unique one-way or two-way slaves.
12.3.2.5 Select Add-On Slaves - To add other terminals already selected - without having to readdress all
previously selected terminals - the ETX code (CTRL C) is used. This code resets all terminals in the address
mode and allows the new terminals to respond to their addresses. The ETX code affects the terminals just as the
ENQ code does. The last terminal addressed is also transmit enabled if the last unique address is not followed by
a non-valid dummy address.
Refer to the LA35/ LA36 DECwriter ll User's Manual for complete programming instructions for terminals
containing the Selective Addressing Option.
12.4 TROUBLESHOOTING
The troubleshooting chart in Table 12-1 lists the common trouble symptoms that could be observed during
installation checkout or normal operation.
12.5 LAXX-KW PRINT SET
The figures at the end of this chapter are the LAXX-KW print set.

12-7

XMIT
DISABLE SEQUENCE
UNIQUE ADDRESS

ENQ

ANY CHARACTER

STX

ADDRESS MODE
E11 PIN 5
DATA AVAILABLE

n
T2

UNIQUE ADDRESS

E10 PIN 2

ADDRESS
MODE

E10 PIN 5

XMIT ENABLE

DATA MODE

E16 PIN 9

XMIT
EN ABLE SEQUENCE
UNIQUE ADDRESS

STX

ADDRESS MODE
E11 PIN '5
DATA AVAIABLE

UNIQUE ADDRESS

ADDRESS
MODE

DATA MODE

E10 PIN 5

XMIT ENABLE

E16 PIN 9
CP-2362

Figure 12-3 Timing Diagram for Transmit Enable and Disable Sequence

12-8

Table 12-1
Troubleshooting for Selective Addressing Option (LAXX-KW)
Symptom

N
I

'°

Probable Cause

Action

Reference

Cabling

Wrong cabling connection

Check all cabling between
M7728 Logic Board and Expander Board

Option location

Option inserted in wrong
location on Expander Board

Install Selective Addressing
Option in location F

Data Available
signal distribution

Signal path interrupted

Check E8 pin 5 for incoming
Data Available signal and E13
pin 12 for output to next
option

D-CS-M7737-0-1,
Sheen

2. Does not respond to any
address

Address mode

Not switching to address
mode

Check Ell pin 5 for a high
level at EOT, NULL, or ETX

D-CS-M7737-0-1,
Sheet 1

3. Responds to Group
Address when Unique
Address sent - or vice
versa

Address switches

Addresses are in wrong
locations

Interchange addresses between
switches Sl should have
Unique Address and S2 should
have Group Address

D-CS-M7737-0-1,
Sheet 2

4. Will not switch out of
address mode to data
mode

Address flip-flop

Not being reset

Check Ell pin 5 for a low
level at STX

D-CS-M7737-0-l,
Sheet 1

5. Data is printed when not
selected

Tri-State Buffe~ on
Logic Board not
disabled

UART ENA H signal from
option not sent to Logic
Board

Check E8 pin 12 for the
UART ENA H signal when
selected

D-CS-M7737-0-l,
Sheet 1

ACK Generator

ACK Code Generator not
energized

Check E7 for ACK code

D-CS-M7737-0-l,
Sheet 1

1. After installation, incorrect
operation or on operationSELECT AVAIL light not
illuminated at power-up

.....

•

Problem Area

Figure 9-4

...

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"THIS DRAWING ANO SPECIFICATIONS, HEREIN, ARE THE
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"THIS DRAWING ANO SPECIFICATIONS, HEREIN, ARE THE
PROPERTY OF DIGITAL EQUIPMENT CORPORATION AND
SHALL NOT BE REPROOLICED OR COPIED OR USED IN WHOLE

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12-13

CHAPTER 13
AUTO MA TIC ANSWERBACK OPTION (LAXX-KX)

13.l AUTOMATIC ANSWERBACK INTRODUCTION
The Automatic Answerback Option performs two distinct functions: the storage of a 20-character preprogrammed message and the insertion of line feed codes as in the Automatic Line Feed Option LAXX-LA.
The answerback message has up to 20 character positions (spaces are counted as characters) that can be programmed by utilizing slide switches located on the option circuit board. The message is activated by depressing
the front panel HERE IS key or by receiving the ENQ code (005 8). When the terminal is on-line, the answerback
message is transmitted down the line. When in local, the message is printed out at the terminal.
NOTE
When operating on-line in the echo mode, the answerback
message is also printed out at the terminal in addition to
being transmitted.
The Line Feed Section of the option can be configured to automatically insert a line feed code after each transmitted carriage return and insert a line feed code after each received carriage return code. The Option Board
contains jumpers that can be removed to inhibit both or either of the insertion functions. The normal action of
the AUTO LF switch can also be overridden by these jumpers.
The Answerback Section of the option interacts with two other DECwriter options (EIA Interface, LAXX-LG
or Selective Addressing, LAXX-KW) if they are installed. The trilevel line (KSTRB DIS L signal) interconnects
these options and establishes whether the Answerback Section can respond to a command requesting the answerback message. The EIA interface can inhibit the Answerback Option when the modem is not ready to accept
transmitted data. The Selective Addressing Option can, if the terminal is not selected as the master or a transmitenabled slave, also inhibit the Answerback Section from responding to received codes. Refer to the EIA description for a complete discussion of this interaction.
NOTE
When operating in the local mode, these options have no
effect on the operation of the Answerback Option.
13.2 ANSWERBACK OPTION FUNCTIONAL BLOCK DIAGRAM
Figure 13-.1 shows the Answerback Option in a typical DECwriter instailation. The option's circuit board installs
in locations C and D on the Expander Option Mounting Board and has an edge connector at each location to
couple signals between the two boards. A variation in the basiccoupling configuration between the M7728 Logic
Board and the Expander Board is required when the Answerback or Auto Line Feed Options are installed.
Normally, without either of these options, ASCII data from the keyboard is routed right across the Expander
Board (in from the keyboard on J3 and out to the Logic Board on J29). When the Answerback Option is
installed, the keyboard data path is now through this option and out to the Logic Board on Jl.

13-1

s.r.-t--.1

UART

I 1-- _

TRI
STATE
BUFFER

~--------~~~

-li-------------vv

so I.__~..--__.

,---

I
I

~Oc;;:;O-N- - - -

I
I
I
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lf.-//'/L~~=============~~====:;;:::~~~~==:..--.

(.)

"m'I ~1 -F_u_N_c_T_1o_N_

ENABLE

''°

XMIT LF
CODE GEN

w
!+----+-'C~O~N~T~RO~L=-t---i~l---t--~
U)
U)

ANSWER
BACK
CONTROL

XMIT CR
CONTROL

::;

(.)

er
w

ENABLE

20
MESSAGE
SWITCHES

DECODER

r - - -,

cR coDE

I HERE IS I
WT

l+--------'~__J_.,___l____
L __ _J

REC LF
CODE GEN

ENABLE
TIMING
SEQUENCER

INCREMENT

Ill

XMIT CR
CONTROL

LF CODE

~ROL

LINE
DRIVERS

.----:..<----.

I
I
I
I
I
I
I

-Tn:-_:--.--60_C_A;- -

KEYSTROBE
GENERATOR

KEYBOARD

'-r-r"

KEYSTROBE

tCATION

_______ J

---------------J5
J5

I
I
I

CHARACTER
BUFFER

I
I
~ CHARACTER
~
SELECTOR

ENABLE KEYSTROBE

I
I
I

LF TRANSMIT SECTION

ANSWERBACK SECTION

LF RECEIVE SECTION

L L __________________________________

--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- __J
CP-2369

Figure 13- l

Automatic Answerback Option Functional Block Diagram

As shown in Figure 13-1, the Answerback Option is divided into the three following functional sections:
I.
2.
3.

LF Transmit Section
LF Receive Section
Answerback Section

13.2.1 Operation of LF Transmit Section
ASCII data from the keyboard is applied to both the Line Drivers and the Xmit CR Decoder through location
D. Normally this data is routed right through the option to the UART. Two conditions cause the Line Drivers to
block this data path.
I.
2.

When the LF Transmit Section is issuing a line feed code.
When the Answerback Section is issuing the answerback message.

If a carriage return code from the keyboard is detected and the front panel AUTO LF switch is depressed and
Jumper W3 is installed, the Xmit CR Control initiates the following three actions:
I.

Disables the Line Drivers blocking the data path from the keyboard to the UART.

Enables the Xmit LF Code Generator placing an LF code on the lines to the UART.

When clear to send from EIA is high, generates the keystrobe that transfers the LF code to the
UART.

After the LF code is accepted by the microprocessor, the Xmit LF Code Generator is disabled and the Line
Drivers are enabled, allowing normal data flow from the keyboard.
As shown in Figure 13-1, Jumper W3 is in series with the AUTO LF switch. If this jumper is removed, all control
is removed from the switch and the LF Transmit Section of the option is disabled.
Figure 13-2 contains the operational sequence for the LF Transmit Section.
13.2.2 Operation of LF Receive Section
The LF Receive Section of the option monitors the data out of the UART and, if Jumper Wl is installed,
automatically inserts a line feed code after each received carriage return code. When the Function Decoder
detects a carriage return code out of the UART, the Rcvr CR Control initiates the following three functions:
I.

After the carriage return code is processed, disables the UART.

Enables the Rcvr LF Code Generator, placing an LF code on the bidirectional lines to the Character
Buffer.

Issues an option-generated Data Available signal out on OP IN line. (Refer to Expander Board
description for discussion of Data Available signal steering.)

After the LF code is processed by the microprocessor, the UART is enabled and the LF Code Generator is
disabled.
Removing Jumper WI disables the LF Receive Section of the option.

13-3

DATA FROM KEYBOARD

•

•
•

YES

NO DATA FROM

DISABLE LINE
DRIVERS
ENABLE LF CODE
GENERATOR
ENABLE TIMING
SEQUENCER

ATSRD ISSUE
KEVSTROBE

~~~• KEYBOARD

•
NO

•
•

DISABLE LF CODE
GENERATOR
ENABLE LINE
DRIVERS
RESET TIMING
GENERATOR

DATA TO UART
CP-2370

Figure 13-2 Operational Sequence for LF Transmit Section

13-4

If the terminal is operated in the local mode, with the front panel AUTO LF switch depressed and Jumpers Wl
and W3 inserted on the option circuit board, a carriage return code from the keyboard causes a carriage return
and two line feed increments at the printer mechanism. This action occurs because the LF Transmit Section of
the option adds a line feed code after the carriage return from the keyboard, then the LF Receive Section of the
option inserts another line feed code as the carriage return code leaves the UART for the Character Buffer. Thus,
two line feed codes are acted on by the printer mechanism.
NOTE
When the terminal is on-line, transmitting in an echo
mode, and the AUTO LF switch is in the down position,
the option generates a line feed code after each carriage
return. In this operational configuration, the printer mechanism advances two lines for each carriage return even
though only one line feed code is being transmitted out
from the terminal. The second line feed occurring at the
terminal is generated by the returning (echoing) carriage
return as it is processed by the LF Receive Section of the
option. This same action occurs when the terminal is operated in the local mode.
Figure 13-3 contains the operational sequence for the LF Receive Section.
13.2.3 Operation of Answerback Section
The Answerback Section utilizes the Function Decoder to detect received requests (ENQ code) for the stored
answerback message. In the local mode, depressing the HERE IS key activates this section and causes the
message to be printed out at the terminal. The AB Control initiates the following sequence when commanded to
output the answerback message:
I.
2.
3.
4.
5.

Disable the Line Drivers blocking all keyboard data.
Increment the Character Selector by one (from zero to first character in message).
Enable the Timing Sequencer.
Monitor for last character in message.
Produce option-generated keystrobe to transfer answerback character to UART.
NOTE
As can be seen in Figure 13-1, the answerback message is
applied to the UART just as if it were typed on the keyboard. The message is NOT applied on the bidirectional
lines to the Character Buffer as in the case of other
options.

After the microprocessor has accepted the first character, the next character and its keystrobe are ready to be
processed in the same manner. This action continues until the last character of the answerback message is
transferred out. At this time the Line Drivers are enabled again and normal terminal action i~ resumed.
Figure 13-4 contains the operational sequence· for the Answerback Section.

13-5

DATA FROM UART

• DISABLE UART
• ENABLE LF CODE
GENERATOR
•GENERATE DA

•

DISABLE LF
CODE
GENERATOR
ENABLE UART

DATA TO UART
CP-2371

Figure 13-3 Operational Sequence for LF Receive Section

13-6

DEPRESS
HERE IS
SWITCH

DECODE
ENO CODE

NO
•
•

DISABLE LINE
DRIVERS
BLOCK ANY
FURTHER INCOMING HERE
IS OR ENO
COMMANDS

STORE REQUEST
FOR ANSWERBACK
MESSAGE IN E12
AND E9 UNTIL
KSTRB DIS L
GOES TO A "H"

ENABLE TIMING
SEQUENCER

ANSWER BACK
MESSAGE
LOOP

AT SRA
INCREMENT
CHARACTER
SELECTOR
BY ONE COUNT

•

RESET TIMING
CONTROL
FLIP-FLOP
CLEAR TIMING
SEQUENCER
TO ZERO

AT SRC CHECK
FOR NULL CODE

ATSRD
GENERATE
KSTRBAND
ISSUE
CHARACTER

•
•

•

RESET AB
FLIP-FLOP
RESET TIMING
CONTROL
FLIP-FLOP
CLEAR TIMING
SEQUENCER

• ENABLE LINE
DRIVERS
• RESET CHARACTER SELECTOR
TO CHARACTER
#{)

ANSWERBACK MESSAGE TO UART

NO ACTION
BY OPTION

Figure 13-4 Operational Sequence for Answerback Section
13-7

CP-2372

13.3 AUTOMATIC ANSWERBACK BASIC BLOCK DIAGRAM
The basic block diagrams for the Automatic Answerback Option are shown in Figures 13-5 and 13-8. These
diagrams are simplified representations of the automatic answerback circuit schematic (D-CS-M7733-0- l ). Circuit designations and pin numbers indicated on these figures correlate with corresponding components on the
schematic. Buffers, inverters, and other components that do not have major operational functions are omitted
from the block diagrams.
The Answerback Option is divided into three areas:
I.
2.
3.

LF Transmit Section
LF Receive Section
Answerback Section

13.3.1 LF Transmit Section 8asic Block Diagram
The basic block diagram for the LF Transmit Section is shown in the top half of Figure 13-5. Normally, ASCII
data from the keyboard passes through the Line Drivers E 17, E23 to the UART. If the Answerback Section is not
generating the answerback message, the keystrobe for each character from the keyboard passes through El5 to
the microprocessor. When a carriage return is typed, the keystrobe associated with the carriage return is utilized
by the Xmit CR Decoder E22 to detect the CR code. If the AUTO LF switch is depressed and Jumper W3 is
installed, the carriage return indication passes through functional AND gate E3 and sets Xmit No. 1 flip-flop
E24. After the carriage return is processed and the UART is ready to accept the next character, the XMIT ROY
L signal is applied to pin 5 of Inverter E21. This inverted signal clocks the Xmit No. 2 flip-flop E24, producing
the LF ON H and LF ON L signals.
The LF ON H signal performs the following four actions:
I.

Disables the Line Drivers through E3 blocking any further data from the keyboard.

Enables the Xmit LF Code Generator Ell, producing the zero bits of the line feed code (bits 1, 3, 5, 6,
7).

Clocks Timing Controller E9 in the Answerback Section starting the Timing Sequencer E2.

Conditions NANO gate ElO at pin 9 so that after the LF code is accepted by the microprocessor, the
returning XMIT ROY L signal can clock and clear both sections of E24.

The LF ON L signal from E24 pin 8 is applied to pin 15 of Line Driver E23 and produces the two 1-level bits of
the LF code (bits 2 and 4).
At SRD time, the KSTRB OUT signal is generated at E7 pin 10. After the UART accepts the LF code, the
leading edge of the returning XMIT ROY L signal clocks a low through E24 to pin 5 and the trailing edge clocks
this low through Xmit No. 2 flip-flop to enable the Line Drivers, disable the LF Code Generator, and allow
keyboard data to pass through the option again. The XMIT RDY H signal clears Timing Sequencer E2 and
resets Timing Controller E9.
The timing sequence for the LF Section is shown in Figure 13-6.

13-8

LF TRANSMIT SECTION
LOCATION
E23

"o"

ASC11

DATA BITS 1-7

FROM
KEYBOARD

XM IT
CR
DECODER
E22

fA~O~F 1

-L0---1'---"_...,_,

LF ON H

--0

L_ -

LF
9 ON H

12
XMIT
#2
E24

XMIT ROY L

XMIT
LF
CODE
GEN
Ell

LF ON L

.___ _ _ _ _ _ _ _ _ _ _ _ _.._____ _ XM IT ROY H
GATED KSTRB

TO AB CKTS

LF ON H
TO
AB CKTS

LOCATION

"ell
10

KSTRB

OUT

AB ON L
FROM AB CKTS

TO
UART

TO
CHAR
BUFFER

LOCATION

"o"

1 - - - - • ENQ TO AB CKTS

ASCII
DATA BITS
1-7

12 UART ENA H
FUNCTION
DECODER
E16

FROM
UART
REC
LF

DA IN L

1--~--1 CGOEDNE
REC
#2

E18

E1B

BITS 1,3,5,6,7

E13

CODE
GEN
E17

BITS 284

OPTION GENERATED
DATA AVAILABLE

LF RECEIVE SECTION

CP-2373

Figure 13-5

LF Sections of Answerback Option

13-9

CR KBRD L
E24-4

E24-5

XMIT
ROY L

E21-5
{
E21-6

---+------~

LF
ON H _ _ __...__ _ _ _ _ _ _ _ _ __ _ _ , _ 1 - - - - - - - ' ;
E24-9

KSTRB OUT
E10-3
-------'
(STROBE)
\FOR CR

~STROBE)
FOR LF
FROM
E2

CP-2374

Figure 13-6

LF Transmit Section Timing Sequence

13.3.2 LF Receive Section Basic Block Diagram
The basic block diagram for the LF Receive Section is shown in the bottom half of Figure 13-5. This section
monitors the received data at a point that is between the output of the UART and the input to the Character
Buffer. This data is present at the option on the bidirectional line through the edge connector at location D.
Receiving both a carriage return code and the DA IN L signal (data available signal from the UART) at the
Function Decoder El6 produces the CR UART L signal that is coupled through Jumper Wl to set Rec No. l
flip-flop El8.
After the carriage return code is processed by the terminal, the microprocessor sends the CLR DAL signal back
to the option at Inverter E21-9. The leading edge of this signal clocks the high level on El8-12 through to El8-9
and forces El8-8 to a low level. The trailing edge of CLR DA resets El8 at pin 3. The high through pin 13 of Ell
produces the signal UART ENA H which disables the UART. This high level also generates the zero bits of the
LF cod,p (bits l, 3, 5, 6, 7) through El3. The I level bits of the LF code are generated by the OP IN L signal which
is applied to El 7 pin 15. The option-generated data available signal is represented by the low level of the OPT IN
L signal. (The steering gates on the Expander Option Mounting Board convert this OPT IN L signal to a
signalthat has the same effect as the Option Data Available signal.) After the microprocessor accepts the optiongenerated line feed code and data available, it sends a second CLR DAL signal back to the option. This resets
flip-flop El8 at pin 11 which then allows the UART to pass received data to the Character Buffer in a normal
manner.
The Timing Sequencer· for the LF Receive Section is shown in Figure 13-7.

13-10

CR UART L
EIS-4

E18-5

3
IST

(EIS-

CLR
DA
L

E18-11

~-------------\

E18-9

\r----.5 ). . .---~
-----_j\
~-\-

2NDCLR------------~~-------1--------.1

DA L
E18-11

UART ENA H
E 11-12

OPT IN L
(OPTION GENERATED DATA AVAILABLE)

Figure 13-7

CP-2375

LF Receive Section Timing Sequence

13.3.3 Answerback Section Basic Block Diagram
Figure 13-8 contains the basic block diagram for the Answerback Section. When the HERE IS key is depressed
or the ENQ command is received, either of these two indications is coupled out ofE14 pin 8 to AND gate EIO. If
the KSTRB DISABLE L signal level is either an Hor M level and AB ON H is not set, EIO is qualified and both
sections of flip-flop E12 set. The high level produced on pin 5 of E12 (AB ON H signal) initiates the following
three events:
'
I.

Disables Line Drivers El 7, E23 through E3.

Blocks any other incoming requests for the answerback message by placing a low on EIO pin 5
through E7.

Conditions E14 pin 4 with a high level so that when the last character in the answerback message is
detected E 13 can reset.

The low level on pin 6 of E12 (AB ON L) initiates the following events:
I.

Disables the keyboard by blocking the KSTRB IN H signal path through EIS.

Enables the Character Drives E 1, ES which send the answerback message to the UART through
location C.

13-11

COMPARATOR
AB ON H
TO
LF XMIT SECTION

n ~5

i./:o"

AB J--J
FLIP
FLOP
AB ON L
- l E12

HERE JS
ENO

AND

El4

~
KSTRB DIS L

AND

(TRI-LEVEL LINE
SEE NOTE)

•.,r-- SHIFT

OR
E15

Cl,

LF ON H
FROMLF XMIT CKTS

1--- SR D
I--- SR c
~SR B

I--- SR A

I-

CLR

DSO

TIMING
CONT

1--

SHF

TIMING
SEQUENCER
E2

H-

\NV

FLIP
FLOP
LF
ONH

AND

l,9

E\0

LF XM\T CKTS

XMIT 5
READY-I
L

E1
+3.75 v

4
OR
XMIT ~
ROY H

E15

AB ON H

1:i

AND
SRC-

t----i

E14
WU--1

CLR

i..---i DATA
OR

SRA----l CLK

SRA

CHARACTERS
#1-#8

CLK

SRA

d
rI

CHARACTERS

#9-#16

#17-#20

ASCII DATA

CHARACTER
SELECTORS

LcLR

CLK
~om
E6

E\5

dff o'"

CLR

CHARACTER
DRIVERS

LOCATION
"c"

Et, E8

NOTE:
"o" no answerback message

20
ANSWER BACK
STORAGE
SWITCHES

,..--,
~

TO UART
ANS WERBACK
MES SAGE

"Mu store request for
answerback message

"H .. message sent

_.a.i

L...-J

NULL
DETECTOR
E20

-Figure 13-8 Answerback Section
Basic Block Diagram

13-12

CP-2 376

As Shift flip-flop E 12 sets, a high level on pin 9 (AB SHIFT 0) is applied to Character Selector ES. E4, ES, and E6
are configured as a shift register that ripples a high level up through each output line every time the register is
clocked. The AB SHIFT 0 signal from pin 9 of E12 is inverted by E7 and passed through the functional OR ElS
on pin 11 to set E9. When E9 sets, a high level is applied on the DSO input ofE2. The Timing Sequencer E2 is a 4bit shift register that shifts the high DSO level to the right at the rate of the Option Clock (approximately 1.2 µs
per shift) when the CLEAR TO SEND signal is applied to the shift and load inputs (pins 13 and 10 respectively).
The CLEAR TO SEND signal is only present when the KSTRB DIS L signal is in the H level. When at the M
level the KSTRB DIS L signal does not overcome the 3.7S V bias level on Comparator El and the CLEAR TO
SEND signal is not produced.
NOTE
The M level allows E12 to set and hold a request for the
answerback message but the message is not trasmitted
until the tri-state line becomes an H level.
At SRA time, the Character Selector ES increments from character no. 0 to character no. l and a high level is
applied to one side of each of the seven slide switches that comprise character no. 1. A closed switch produces a
"1" in the bit position and an open switch a "O." Figure 13-9 shows the switch settings for the letter A in
character no. 1. To produce the code 1000001 for the A, the switches in bits l and 7 are closed while all the rest
are open. The Character Drivers send this code out of location C to the UART. The Null Detector E20 monitors
these.lines for the null code (0000000) and, when decoded, produces the AB DONE signal which resets El2 and
the Timing Sequencer at SRC time. At SRO time, the KSTRB OUT signal is generated at E7 and character no. l
is sent to the UART. As the UART accepts this character, the XMIT ROY H signal is sent back to the option at
El S pin S and initiates three actions:
1.

Shift flip-flop El2 resets and removes the high from ES (El2 remains reset until message is sent).

Timing Controller E9 resets and removes the high level from the DSO input of the Timing Sequencer.

Timing Sequencer clears to zero.

After the UART has processed the character, the XMIT RDY L signal is sent to the option where it combines
with the AB ON L signal at functional AND gate E3. When E3 is qualified, a low pulse from pin 11 of functional
OR EIS sets the Timing Controller E9. As E9 sets, a high level is applied at the DSO input of the Timing
Sequencer. If the CLEAR TO SEND signal is present, the Timing Sequencer starts and at SRA the Character
Selector increments a high level to the switch containing the next character and at SRD this character is strobed
to the UART.
This character generation continues until the Character Selector increments to the twenty-first character location, which does not exist. Therefore, a null is detected at E20 and at SRC time AND gate El4 couples this last
character indication through ElS to reset the AB flip-flop El2, Timing Controller E9, and Timing Sequencer E2.
At this time the Answerback Sequence is completed.
NOTE
If an answerback message of less than 20 characters is
stored in the switches and the last character is coded as a
null, the Answerback Section will reset after detecting this
null rather than sequencing through the remaining
uncoded switch positions.
Figure 13-10 contains the timing sequence for the Answerback Section.

13-13

ANSWERBACK
CHARACTER
#1

CHARACTER
SEL!'ClOR
E5

~·

~ D68

LOCATION

"C'1

r--

CHARACTER
DRIVERS
E1
ES

----

BIT 1

n.D5

---

BIT 2 __.

nD2

(

BIT 3

---

TO
UART

nD21

(

BIT 4

-----

nD6

BIT5

-----

BIT 6

-----

BIT7

n.D87

'--

~ D13

¢
(

"A"= 1000001
ON 7

'---

!~~~~~~~

L-

NULL
DETECTOR
E20

AB DONE

r--

CP-2377

Figure 13-9 Typical Answerback Character Programming

13.4 TROUBLESHOOTING
The troubleshootng chart in Table 13-1 lists the common trouble symptoms that could be observed during
installation checkout or normal operation.

13.5 LAXX-KX PRINT SET
The figures at the end of this chapter are the LAXX-KX print set.

13-14

.------------+-------------1- - - - - +--------

HERE IS
SWITCH

. - - - - - - - - - - - + - - - - - - - - - - - t - - - - - -\---------

ENQ
CODE

~-.l------------+--------------1

KSTRB DIS L
E21-3

______ ,_________

~-----------1----------------1------1--------.
AB ON H
E21·5 - - - - - '
XMIT RDY L

+-----------r--

E3-5 _ _

START TIMING
SEQUENCER E9-9 - - - . I \

CLEAR TO SEND
E1·13

SRA

SRB

SRC

- - - - - -1----+--+!'--\___NULL
DETECTED

SRD

- - - ---f---+--->,:---

AB SHIFT 0
E12-9 - - - - '

L-4--1----+---+------+-- - - - - - -1----+----t--

READ
SWITCH _ _ _ ___,

- - - - - -1----1---+-

KSTRB OUT
E10-3 - - - - - - - - - -

AB DONE H
E20-8

---------------1---------------1 - - - - --1------.....-1.1
1ST CHARACTER OF
ANSWERBACK MESSAGE

2ND CHARACTER

ALL OT HER
CHARACTERS
IN MESSAGE

21ST CHARACTER
OR NULL CODE

CP-2378

Figure 13-10 Answerback Section Timing Sequence

13-15

Table 13-1
Troubleshooting for Automatic Answerback Option (LAXX-KX)
Symptom
1. After installation, characters typed on keyboard
not transmitted

......
wI
......

2. After installation, received
characters not printing

3. Line feed code not inserted
after carriage return typed

Problem Alea

Probable Cause

Action

Cabling

Wrong cabling connections

Check all cabling between
M7728 Logic Board and Expander Board

Option location

Option inserted in wrong location on Expander Board

Install Answerback Option in
locations C and D

Keystrobe signal
distribution

Signal path interrupted

Check for Keystrobe signal
into Option Board at EIS pin
10 and out of board at ElO
pin 3

D-CS-M7733-0- l,
Sheet 3

Line Drivers

Line Drivers on option not
enabled

Check E3 pin 11 for low level

D-CS-M7733-0-l,
Sheet 1

Data Available
signal distribution

Signal path interrupted

Check for Data Available
signal at El 6 pin 15

D-CS-M7733-0-l,
Sheet 1

Tri-State Buffer on
M7728 Logic Board

Tri-State Buffer held disabled
by option

Check El 1 pin 12 for high
level when option not performing answerback or line
feed operation

D-CS-M7733-0-l,
Sheet 2

AUTO LF switch

Al fO LF switch not
depressed

Depress switch - if depressed
and W3 installed and still no
LF code, replace switch

Keystrobe signal

Signal not being generated
by option

Check El 0 pin 3 for keystrobe
signal associated with line feed
code

D-CS-M7733-0-l,
Sheet 3

Line Feed Code
Generator

Line feed code not being
generated

Check for line feed code at
El 1 and E23

D-CS-M7733-0-1,
Sheet 1

Reference
Figure 9-4

Table 13-1 (Cont)
Troubleshooting for Automatic Answerback Option (LAXX-KX)
Symptom

Probable Cause

Action

Reference

Jumper Wl

Wl not installed

Connect Wl

D-CS-M7733-0-l,
Sheet 1

Data Available signal

Option not generating Data
Available signal

Check for pulse at E18 pin 8

D-CS-M7733-0-1,
Sheet 2

Line Feed Code
Generator

Line feed code not being
generated

Check for line feed code at
El3 and El 7

D-CS-M7733-0-1,
Sheets 1 and 2

5. No message is printed when
HERE IS switch is depressed in local or CTRL E
is received when on-line
and Carriage Return/Line
Feed Section does not
operate

Option activation

Timing Control flip-flop not
setting

Check that E9 sets on either
line feed or answerback
operation

D-CS-M7733-0-1,
Sheet 3

Timing Sequences not
operating

Check E2 for outputs at
pins 5, 7, 9, and 12

D-CS-M7733-0-l,
Sheet 3

6. Same as no. 5 above except
Carriage Return/Line Feed
Section operates

Answerback Section

AB flip-flop or Shift flip-flop
not operating

Check both sections of El 2
to ensure that they set when
answerback message activated

D-CS-M7733-0-1,
Sheet 3

7. Message prints on received
CTRL E but not when
HERE IS switch is depressed in local

HERE IS switch

Faulty switch or cabling

Check switch operation and
signal path to El 4 pin 10

D-CS-M7733-0-1,
Sheet 3

8. Depress HERE IS switch no answerback message just last character typed
prints

Message storage

Shorted diode in one of the
20 character switch positions
or any malfunction that shorts
any two lines of shift register
E4, ES, E6 together

Check for shorts in message
array

D-CS-M7733-0-l,
Sheets 5, 6, or 7

9. Message starts to print,
then stops without
finishing

Shift register

Shift register not able to
sequence through complete
message

Check all 20 outputs of E4,
ES,E6

D-CS-M7733-0- l,
Sheets 5, 6, or 7

4. Line Feed Code not
inserted after received
Carriage Return

w
I

Problem Area

......
-.J

]

l r

1-lll=\IJ-~

1 --- -

+
1--

B
U T S R P N M L K J H F E D C B A

_NDT~ES:- - - - ~

' ' V :u. T S· R P .N _M:L K' ,J -wF -E D C :B A

_____._._/.-==-])O~NOTI=NS'T'."'-=ALL---'-'-"'-W'l._ _
NO HalJDLES

1-..1-r!Z
'""

0CHK'D~
~~~~-ES ~~:~

- - - - - - - - -

ENG:-;;;: .. ;;_

===========

~a:

--------t

ZJ;TA>17i

[2/;,h°o

Id ·I_g_ It lol
-

1·

TITLE

PRDJ~NG.,,..~
ANSWERBACK OPT
PROD.~~~

~~- - - - - - - - - 1
SCALE 271
sr_zETco_oij
NUMBE~ ,;. IR~V
- - - - - ~
SHT.
I OF I
D IUAIM7733-:_;:.i_~iuJD
~=====,____gu~========'---------~-----------c--~N:rr.Y-l~El'J;:]EtRST USED ON
LA36
,
-

13-18

0
.,,,

8
''THIS DRAWING AND 5PECl11CATIONS. HEREIN, ARE Ti*
PROPER.TY OF DtrilTAL EQUIPMENT CORPORATION AND
SHALL NOT IE REPRODUCED OR COPIED CR USED IN WHOLE

Non:: SIGtvAt...S MARl<El> "*" ARE·

OR IN PART AS THE WIS FOR THE MANUFACTURE CR SALE

~~~l>l976~=~=:~M':r CORPORATION"

/ll3¢3

AB ON H

AB4>2

LF ON H

\/I/IRED -ORE"D

Bsl

K'BRD DATA IN BIT I

AS/ --*AB4JI

KBRD DATA IN BlT 2 :.
. ~B~P-1'-------------------'---+--------------------------------+--t-''-I
BNI
l<BRD DA/A TN BIT3 .:_ .~B~R~l'--------+-----------r--+---------------------------------t---+-"'-l
KBRD 'DATA IN "SIT+
>:a; I Lo&IC H - - - - - - - ! - - + - " - - - <

1<8Rll JJATA
KBRD "DATA

IN BITS'
IN .BIT-0

KBRD DATA IN. EflT 7

..-

•

To<SE:/HeR..

------,1 7.-'--f~t.32. >----~-----~

A'B'P2

LF ON

KBRD "DAiA OUT BIT I

API ="'AS.Pl l<BFID "DATA OUT BIT 2
AN/
*A'Bl/JI Kl!Rl> :DATA 01/T BIT 3
AP.l_.'4-AB~I KBRD :bATA OUT il:ZT 4

AB~/

J<BRD DATA our 'BIT 2.

AB!p I

l<llR ]) J)ATA OUT BIT 'I-

f=-----1--+-~----·-A_F_l__-ll ABqJI KBRD

BFI

JlATA

OUT BITS'

f=-'---+-+--l--.----'-"=£:.:..l-1-.,.,..,..All~' KBR?> 'DATA our BIT b

BEi

~---+--l---l--+---'-Ao:C.:!/-1_...,_AB4>I l<BJ<D DATA OUT ]3:t:i 7

BCI

RlcfJ

>-'------+--+---1--+---+--'B_!>_:z.--<,__ AB<:JI UART DATA
'BF2~
t--'----l--+---l--+-+-~--1~
. . 'l>J5'11 UART JJATA

. IK

+sv -vv.

OUT BIT 2

OVT 'BIT +

'c
AB</>2. OP IN

------+--------'

W2.
'.J

---0

14-

~---<J)J

1¢
71"32..
2>

.AB¢3 5ATEIJ

l<.1

+.sv

7+4-2.

.,;:,;:r1

Elb

BL2.

UART PER H
., BK2.
UART DATA SIT 7
-BJ"2.
UART DATA BIT b
. . 13H2.
'BITS
UART DATA
BF:Z.
13·
VART 'DATA 13IT -4 ~----~---~------~------~l>2.
1lE2.
VART DATA 'BIT 3
I+
1ll>2
------------iDI
VART DATA 'B:IT 2.

UART DATA BIT I

b
$~.X:>-"'--------......1...-+-I----~·
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CHAPTER 14
FORMS CONTROL, VERTICAL TABULATION,
AND HORIZONTAL TABULATION OPTION (LAXX-KY)

14.1 TABS OPTION INTRODUCTION
This option (hereinafter called Tabs Option) provides a DECwriter with three major functions:
l.
2.
3.

Forms Control - Top of form capability
Vertical Tabs - Storage of vertical tab locations
Horizontal Tabs - Storage of horizontal tab locations

The Forms Control Section of the option stores the preset form length and compares it with the number of line
feed actions performed by the printer mechanism. Then, when commanded by a form feed code, it issues the
correct number of option-generated line feed codes required to advance the paper to the next top of form.
The Horizontal Tab Section stores tab locations and monitors the position of the print head in the 132 printable
columns. When a Horizontal Tab command is received it issues the; proper number of space codes to move the
print head to the right to the next horizontal tab location.
The Vertical Tab Section stores tab locations and monitors the number of lines the paper advances. This section
operates in conjunction with the Forms Control TOF setting which establishes the maximum number of printable lines for the form being used. A vertical tab can be established on any line on a form. On receipt of a Vertical
Tab command this section issues the proper number of line feed codes to advance the paper to the next vertical
tab location.
Each section of the option performs all internal housekeeping functions (incrementing, line feed, or space code
generating, etc.) before option-generated data is passed on to the Character Buffer for normal terminal action.
14.2 TABS OPTION FUNCTIONAL DIAGRAM
Figure 14-1 shows the Tabs Option in a typical installation. The Forms Control Assembly is physically attached
to the right-hand side of the printer mechanism and the circuit board is connected by an edge connector at
location A of the Expander Option Mounting Kit. A cable harness connects the two assemblies. At each end of
this harness is a Mate-N-Lok connector and a pair of Faston terminals. One connector is connected to J1 on the
option circuit board, the other end to the FORMS LENGTH switch on the Forms Control Assembly. The
Faston terminals connect to lugs on the SET TOP OF FORM switch and lugs on the option circuit board. The
FORMS LENGTH switch is a 12-position rotary switch and the SET TOP OF FORM switch is a momentarycontact pushbutton. Each position of the FORMS LENGTH switch represents the length (in inches) of a preestablished format (such as a preprinted form) that can be used with the option. In normal operation, the
FORMS LENGTH switch is set to the length of the form being used, then the SET TOP OF FORM switch is
depressed to load this value into the Vertical Position Counter on the option circuit board.
Data processed by the UART, whether incoming serial information or locally generated at the keyboard, is
available at location A on the Expander Option Mounting Board. All option-generated output signals (line feed
or space codes and control signals) are also available at location A. No edge connector is installed at location B;
the exposed fingers of the circuit board provide convenient locations for monitoring circuit signals.

14-1

------------r----------------

--,

1 M7728 LOGIC BOARD

I
I

S.l.-1--------

CHAR
BUFFER

TRISTATE
BUFFER

UART

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OF FORM

FORM
LENGTH

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I FORMS CONTROL
ASSY
I

TABS OPTION
LAXX-KY

SP AND LF CODES

I
I

I
I
I
I

VERT
TABS
CKTS
COMMANDS

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I

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CKTS

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L

FORM
FEED
CKTS

L-------

LOAD
TOF
SWITCH
SETTING

TIMING AND
CONTROL
SIGNALS

-~------------.J

_J
CP-2349

Figure 14-1

Tabs Option Functional Block Diagram

The Decoder Circuits monitor the incoming data for commands and other pertinent codes that are required in
the three operational sections. Table 14-1 lists the various codes detected by the Decoder Circuits and the sections where these codes are used.
Table 14-1
Codes Decoded By Tabs Option
Codes
Detected

Horizontal Tabs

CR
FF
VT
HT
BS
LF
ESCl
ESC2
ESC3
ESC4

Section Used in
Vertical Tabs

Forms Control

Yes
Yes

Yes

Yes
Yes
Yes
Yes
Yes
Yes

The Line Feed Code Generator and Space Code Generator send codes back up the. bidirectional line to the
Character Buffer on the Logic Board. The Space Code Generator is controlled by the horizontal tab circuits and
the Line Feed Code Generator by either the vertical tab or forms control circuits.
The timing circuits establish the controlling signals for all functional sections of the option. Sequential timing is
required for the critical storage, loading, resetting, and .clearing functions performed in typical tabbing operations. The timing circuits utilize the Data Available signal from the UART plus commands from the functional
section of the option and the Option Clock timing pulses to initiate these timing sequences. Whenever the option
is performing one of its three major functions, the UART is disabled by a signal from these timing circuits.
14.3 SIMPLIFIED OPERATION OF TABS OPTION
Each of the three option functions (VT, HT, and TOF) can be set to a value (store a location), commanded to
perform a function (go to next top of form), and cleared of all positions or settings. Table 14-2 shows the
commands, both local and remote, that set, command, and clear each of the functions.
Table 14-2
Control Commands for Major Tab Operations
Function
Section

Local

Set Up By
Remote

Controlled By
Remote
Local

Horizontal
Tabs

ESCI

033sand
06ls

TAB key
(HT)

Olls

ESC2

033s and
062s

Vertical
Tabs

ESC3

033s and
063s

CTRLK
(VT)

Ol3s

ESC4

033s and
064s

Top of
Form

Set length
Depress TOF
or at wake-up

None

CTRLL
(FF)

014s

Change
length
Depress TOF

None

14-3

Local

Cleared Bi
Remote

14.3.1 Horizontal Tabs Operation
The Horizontal Tabs Section of the option can be considered as a counter with 132 locations; each location
represents one of 132 printable positions the print head passes through on each horizontal printing line. When
the print head is at the left-hand margin (just after a carriage return or a power-up sequence), this Horizontal
Position Counter is at zero. As the print head moves across to the right, the counter increments; back spacing
(movement to the left) decrements the counter. The Horizontal Position Counter always contains the count of
the column in which the print head is positioned.
To set a horizontal tab, the print head must by physically positioned at the location of the desired tab; then the
storage command is either typed locally (ESC 1) or received (033s and 061 8). This action causes the HT RAM that
is monitoring the output of the Horizontal Position Counter to store this print head position. Any number of
horizontal tabs (up to 132) can be stored on a line.
Typing the TAB key in local or receiving an HT code (011 8) causes the option to block any incoming data from
the UART and issue space codes until the print head moves to the right to the first location where a tab had been
set. This location is determined by the output of the HT RAM. If a Horizontal Tab command is given and there
are no tabs set between the present print head location and the right-hand margin, the option generates space
codes until the print head reaches column no. 132. The print head remains there until either a carriage return or
line feed code is received. The printing function is disabled while the head is at column 132.
All horizontal tab locations are cleared when either an ESC2 is typed locally or 033 8 and 062 8 is received. The
horizontal tab clearing action initiates the following sequence:

1.
2.
3.
4.

Value of Horizontal Counter is stored in latch.
Horizontal Counter is reset to zero.
Horizontal Counter is incremented up to 132 and all horizontal tabs stored in HT RAM are erased.
Value in latches is loaded back into Horizontal Counter.

This action ensures that the Horizontal Counter always contains the actual position of the print head and is
ready to accept new tab locations right after the old tabs are erased. For, if the clearing command is given when
the print head is in the middle of a line and the Counter is just reset to zero and not reloaded with the actual
position, any tabs set on this line are not accurate because of the discrepancy between head position and Counter
value.
14.3.2 Top of Form (TOF) Operation
The primary component of the TOF Section is a 128-bit Counter. Each bit of this counter represents a printable
line on a form. This Vertical Counter accepts one of 12 preset values as determined by the position of the
FORMS LENGTH switch. Each switch position loads a number that is 128 minus the maximum number oflines
on a specific form. For instance; if an 14-inch form is to be used, the FORMS LENGTH switch is set to position
no.14 and the SET TOP OF FORM switch is depressed. On a 14-inch form the maximum number of printable
lines is 84 (14 inches times 6 lines per irich). The 128-line counter is preset with 44 lines from switch position no.
14, leaving 84 lines to be filled. Each line feed code received by the option or each line feed code generated by the
Vertical Tabs Section of the option increments the count upwards by one line. So, if after advancing 61 lines (61
line feed codes received or generated), a Top of Form command (form feed code) is received the paper must be
advanced 23 lines to reach the top of the next form. As the option generates these 23 line feed codes, the Vertical
Counter is incremented once for each line feed code. When the Vertical Counter overflows (after 128 increments
- preset value plus the number of option-generated line feed codes) the value of the FORMS LENGTH switch is
reloaded back into the Vertical Counter again.
NOTE
There is no way to completely clear the DECwriter of a
TOF value. Everytime the Vertical Counter overflows, the
FORMS LENGTH switch setting is automatically
reloaded to establish a new top of form.

14-4

14.3.3 Vertical Tabs Operation
The Vertical Tabs Section can be considered as a unique variation of the TOF function. Both respond to operator commands and advance paper through the DECwriter by issuing line feed codes until a· specific number of
lines have been advanced. The TOF circuits stop the paper from advancing when the Vertical Counter is full,
indicating that the next top of form has been reached. The vertical tabs circuits stop the paper from advancing
when the location of a previously set vertical position is reached. Thus, the FORMS LENGTH switch setting
used in the TOF circuits actually establishes the boundaries where vertical tabs can be set.
A vertical tab is set by either typing ESC3 or receiving 033s and 063 8 • At the time when this storage comman_d is
received, the vertical location of the print head is stored in the VT RAM that is monitoring the output of the
Vertical Counter.
Typing CTRL L in local or receiving 014s activates the vertical tab function. This action causes the Vertical Tabs
Section to block any incoming data from the UART and issue line feed codes until the paper advances to the next
verti'cal tab location as determined by the VT RAM. If a VT command is given and there are no vertical tabs set
between the present head location and the next top of form, the paper advances to the next top of form.
All vertical tab locations are cleared when ESC4 is typed locally or 033 8 and 0648 is received. The vertical tab
clearing action initiates the following sequence:
l.

2.
3.
4.

Value of Vertical Counter is stored in a latch.
Vertical Counter is reset to zero.
Vertical Counter is incremented to overflow and all vertical tabs stored in VT RAM are erased.
At TOF (overflow) the value in latches loaded back into Vertical Counter.

This action ensures that the Vertical Counter always contains the actual position of the print head and is ready to
accept TOF commands or new tab locations right after the old tab locations are cleared. This prevents discrepancies between head position and Vertical Counter values. If the clearing command was given in the middle
of a form and the Vertical Counter was just reset to zero and not reloaded with the actual position, any TOF or
VT command given before the next top of form was reached would not perform correctly.
14.4 TABS OPTION BASIC BLOCK DIAGRAM
The basic block diagrams for the Tabs Option are shown in Figures 14-2,-14-4, 14-5, 14-7, 14-9, and 14-10. These
diagrams are simplified representations of the HT, VT, TOF circuit schematic (D-CS-M7736-0-l). Circuit designations ano pm numbers indicated on these figures correlate with corresponding components on the schematic.
Buffers, inverters, and other components that do not have major operational functions are omitted from these
block diagrams.
The Tabs Option can be divided into the following five functional areas:
I.
2.
3.
4.
5.

Decoding and Generating Circuits
Timing Circuits
Horizontal Tabs Circuits
Top of Form Circuits
Vertical Tabs Circuits

14.4.1 Decoding and Generating Circuits Basic Block Diagram
The basic block diagram for the decoding and generating circuits is shown in Figure 4-2. Incoming ASCII-coded
data present on the bidirectional UART data lines connects to the decoding circuits. Outgoing data, either a line
feed or space code generated by the option is sent back to the Character Buffer via these lines too.

14-5

NOTA
DELETE

ASC11
BITS
1- 7

LOC
A

UART
DATA
LINES

DELETE
DECODER
E7

NANO
E26

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BITS
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OR
E26

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11
DA 11
FROM
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CKTS

OR
E14

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TO
HT CKTS

SRC

FROM HT
CKTS

SPACE
CODE
11

LINE
FEED
CODE
GEN

SPACE
CODE
GEN

85 11

C"R

}

TO
HT CKTS

}

TO
VT CKTS AND TOF CKTS

(HTl
FF
FUNCTION
DECODER

ENABLE
FROM
VT AND
TOF CKT
SRA

ENABLE
FROM
HT CKTS

E3
E9

2
AND
E23

DA 11
FROM
TIMING CKTS

3
4

ESC
1,2,3,4

FLIP
FLOP
E11

OR
E4

CLOCK

TO
ESC 2 } HT CKTS

TO
HT
CKTS

ESC 1
NANO
E22

ESC 3

~--E_SC~4 ~
..}

CKTS

SRB
CP-2:350

Figure 14-2

Decoding and Generating Circuits Basic Block Diagram

14.4.1.1 Decoding - The decoding circuits perform two main functions: (1) detecting commands that the option
requires for operation and (2) monitoring the UART data lines for characters or codes that cause the print head
to move either forward or backward. The Function Decoders E3 and E9 sample the seven ASCII bits when the
DA signal and the SRA timing pulse are present.
NOTE
Both bit 7 and Parity Error are required at AND gate E23
before DA and SRA allow the decoding action.
Decoding of standard codes (HT, CR, LF, etc.) is performed in a normal manner but the special commands
ESC 1, 2, 3, al).d 4 require a somewhat different decoding scheme. Each of these commands consist of two codes
(the ESC code and either 1, 2, 3, or 4) which must be decoded in the correct sequence to be recognized by the
options as legitimate commands. When the ESC code is detected at SRA time, E16 sets placing a high level on
pin 2 of E22. This high level out of E 16 pin 5 remains high through the duration of the ESC decoding. It appears
that at SRC time E16 will clock but it does not because SRC has no effect while the ESC code is keeping E16 set.

14-6

If the next character after the ESC code is either l, 2, 3, or 4, the Function Decoder detects these codes and
applies one of them to El I. At SRB time of this second character N AND gate E22 is qualified and clocks the
second character through E 11 to the appropriate circuit. If the character following an ESC command is not l, 2,
3, or 4, there is no decoded signal at the input of Ell to be clocked through at SRB time. In either case, at SRC
time of the second character El6 clocks low. Now, even if the third character received is 1, 2, 3, or 4, and after
being decoded is applied to Ell, there is no clock signal from El6 to transfer it through El I. Therefore, only
these specific combinations of the ESC code and 1, 2, 3, or 4 are decoded as option-operational commands. The
timing diagram for ESC command decoding is shown in Figure 14-3.

----1st

CHARACTE R _ _ _ _ _ _ _2nd CHARACTER_____.:
ES C
1, 2, 3 or 4
1

I
DA
FROM UART

SRA

E SC
command

code

1,2,3, or 4
CODE

------+----------+-----+--------'

CLOCK SHIFT
REGISTER E11
ESC SET
E16 PIN 5 _ _ _ __,

SRB

SRC

SRD

CDA
FROM UART
CP-2351

Figure 14-3

Timing for ESC Command Decoding

The other decoding function is performed by E7 and El4 which are also monitoring the incoming ASCII data.
The function of these Decoders is to detect all characters or codes that cause the print head to move either to the
left or right. Only two gates are required to decode all these possible character combinations. This is because of
the unique bit assignments in the ASCII structure where all of these characters (except three) have a 1 in bit 6 or
7. The characters that move the head and do not have this 1 in bit 6 or 7 are: delete, back space, and horizontal
tab. Back space and HT are decoded by the Function Decoder E3, E9. The delete code (all bits are 1) is detected
by E7. Therefore, if a character is detected having a 1 in either bit 6 or 7 and it is not the delete code, the DA
signal from the timing circuits qualifies AND gate E26. A back space, horizontal tab, and head moving
indication is passed through OR gate E26 to the data input (pin 2) of ES. At SRC time, ES clocks this information out to the horizontal tabs circuits. After clocking, ES resets and awaits another indication that the next
character will cause the print head to move.

14-7

14.4.1.2 Generating - The option-genera~ed line feed codes and space codes are issued by the combination of E 1
and ElO. Enabling the Space Code Generator places the binary code 0100000 on the UART lines. The line feed
code (0001010) is also generated by these same gates but uses EJO in a different manner.
NOTE
Both codes have the same bit pattern in four locations (bits
1, 3, 5, and 7) and always use El to generate these four.
bits.
14.4.2 Timing Circuits Basic Block Diagram
The basic block diagram for the timing circuits is shown in Figure 14-4. The primary component of this circuit is
the Timing Sequencer E19, a 4-bit shift register that produces four sequential timing signals (SRA, SRB, SRC,
SRD). Any of four signals applied to the reset pin of flip-flop E25 enables the Timing Sequencer and causes the
high level at pin 4 to shift right at the rate of the Option Clock input at pin 6 (approximately 1.2 µs per shift). The
four possible enabling signals are:
1.
2.
3.
4.

HT' Horizontal Tab command
VT' Vertical Tab command
FF' Form Feed command
DA (Data Available) signal

OPTION---------------------.,
CLOCK

TIMING
ENABLE
E25
t--------tC

FROM HT'
HT CKTS

VT CKfti~ VT' + FF' 4
TOF CKTS

VT' + HT' + FF'

E21

OR
E14

(INHIBIT)

2
13

FROM - - - - - - - - + - - - - t
UART

NOO

E15

"DA" TO
DECODING
ANO
GENERATING
CKTS

UART ENABLE H

g
OR

SRO
TIMING
SEQUENCER

SRC
SRB
SRA

OPTION CLOCK

TO UART

CLEAR

CDA· lO
CP-2352

Figure 14-4 Timing Circuits Basic Block Diagram
The DA signal from pi~ 12 ofE15 (which is the Data Available signal from the UART) is only present when the
other three signals are not present. This blocking action ensures that once a tab or TOF routine has started, no
other incoming command or character is processed until the option function is completed. Table 14-3 contains
the major events of each option function that occurs during each timing period.
14.4.3 Horizontal Tabs Circuits Basic Block Diagram
The basic block diagram for the horizontal tabs circuits is shown in Figure 14-5 and the operational sequence
flow diagram is shown in Figure 14-6.

14-8

Table 14-3
Timing Sequencer Major Events
Functional Sections of Option
Timing Sequencer
Periods

Decoding and
Generating Circuits

Horizontal Tabs
Circuits

Vertical Tabs
Circuits

SRA

• Enable Function Decoder

• HTcommand
detected

• VT command detected

• FF command detected

• CR code resets
HT Counter

• FF command detected

• VT command detected

• BS code detected

• LF code detected

• Disable UART

• ESC 1- decoded

• ESC 3 decoded

• Enable Line Feed Code Generator

• ESC 2 decoded

• ESC 4 decoded

• Clock VT Counter

• Enable Space
Code Generator

• Enable Line Feed Code
Generator

• Set HT tab in HT
RAM(ESC 1)

• Clock VT Counter

SRB

• Clock ESC command

Top of Form
Circuits

SRC

• Reset ESC FF

• Clock HT Counter

• Load VT Counter with
switch setting after
TOF

• Load VT Counter with switch
setting after TOF

SRD

• Generate DA

N/A

• Set VT tab in VT
RAM(ESC 3)

N/A

STORAGE
LATCHES

FROM { ESC 1,2,3,4
DECODING a . GENERATING CKTS
(HT)

I--

9 ;...·- - - - .
OR

5 HORIZONTAL

!--'-'----<

FORWARD
OR
BS _ _ __.., BACKSPACE

POSITION
DATA

DOWN

COUNTER

HT
FF
E25

ENABLE

1---------1

CDA

.!.£,

~
ESCI ~
SRC

CR~
WU~
AND

RESET

13
AND

CDA2I

i----2

•

HT'

E27

L!.!___ TO DECODING Bo
,-------

GENERATING
CKTS

SRB

~TO

E2·1 TIMING CK TS
AND E26
.
DECODING a GENERATING
CKTS

E27

WU~

E31

E39

E26
LOAD

E17

AND

MEM

·LOAD

'----rI

HT
RAM

E32 E38
E22 E23

E33,E37
CLOCK
FROM COUNTER
DEiCODING a
GENERATING CKTS

ENAB'LE SPARE
AND

8
OR

E23

.-9
H-J
1~
WllESC 2 _::__

.._ E29 ....

6
1-"'--L----!C E40

E14

- L-..,,-

CARRY~
FROM E32

OR
E14

l---

.......-2nD

If-ES

-C

O LOAD

WU
CP-2353

Figure 14-5 Horizontal Tabs Circuits
Basic Block Diagram

14-10

DATA FROM UART

1.ENABLE UART
2.ENABLE DA LINE
NO

HORIZONTAL TABS
SEQUENCE
COMPLETED

STORES ESC
COMMAND
IN E16
DURING SRA
1. DISABLE UART
2. BLOCK INCOMING DA

DURING SRB
ENERGIZE SPACE
CODE GEN

ATSRC CLEAR
ESCCOMMAND
AT E16

DURING SRC
INCREMENT
HT COUNTER
BY 1

1. INCREMENT
COUNTER TO
OVERFLOW
2. WRITE "0" IN
ALL RAM
ADDRESSES
BETWEEN SRB AND
SRC WRITE "1" IN
PRESENT RAM
ADDRESS

START TIMING
SEQUENCER

1. RESET TIMING
SEQUENCER
2. DISABLE SPACE

AT OVERFLOW
1. RESET E40
2. LOAD COUNTER
WITH LATCH
VALUE

CP-23548

CP-2354A

Figure 14-6 Horizontal Tabs Circuits
Operational Sequence

14-11

The horizontal tabs circuits perform the following four functions:
l.

2.
3.
4.

Monitoring the horizontal position of the print head
Setting horizontal tab locations
Tabbing action
Clearing horizontal tab locations

14.4.3.1 Monitoring - Each time the decoding circuits detect a character or command that moves the print
head, the Clock Counter pulse from E8 is applied to the forward or back space steering gates E22 and E23. If the
motion is forward, the Horizontal Counter E32, E38 is incremented by one count; if back space, the Counter is
decremented by one. As the Counter changes, the position value is present on the output lines that are hardwired
to the input address lines of HT RAM E39. Therefore, the RAM's address is representative of the current print
head position.
NOTE
These Counter values are not written into the RAM, just
present at the address lines.
When a carriage return is performed, the Horizontal Counter resets to zero and the HT RAM is at address zero
also.
14.4.3.2 Setup - The command that establishes a horizontal tab is ESCl. When this command is given it is
detected by the decoding circuits and applied to pin 9 of E23. Between SRB and SRC time it enables the write
input (pin 12) of the HT RAM. At this time there is a high level on the data input (pin 13) of the HT RAM and a
1 is written into the HT RAM location that is addressed by the Horizontal Counter output. As the print head is
advanced to the right to another tab location, the Horizontal Counter output increments the HT RAM pointer
to new addresses. During this incrementing the HT RAM is not storing new locations; only when the ESCl
command is received are ls stored in the HT RAM.
NOTE
When the ESCl command is typed the print head moves as
the 1 is depressed but the horizontal tab location is set at
the column location established when the ESC key was
depressed.
14.4.3.3 • Horizontal Tab Action - A Horizontal Tab command is decoded, then applied to the horizontal tabs
circuits as the (HT) signal. This signal sets HT flip-flop E25, which remains set until the tab function is completed. Four events occur as a result of E25 storing the Horizontal Tab command:
l.
2.
3.
4.

UART is disabled.
Data Available signal path is blocked.
Horizontal Counter is ready to be incremented by one count.
Space Code Generator is enabled at SRB.

The HT signal from pin 6 of E25 is applied to the timin~rcuits where it blocks the Data Available signal path
through EIS and disables the UART through El. The HT signal level is also applied to E26 of the Decoder
Circuits to clock the HT Counter by l. This level on the data input (pin 2) of E8 is clocked through E8 at SRC
time of each Timing Sequencer cycle. At SRB time the HT signal enables the Space Code Generator El, ElO
which places the ASCII code for a space on the bidirectional lines to the Character Buffer. At SRD time the

14-12

option-generated Data Available signal is produced and this space code is ready to be processed and move the
print head one space to the right. As the Horizontal Tab command increments the Horizontal Counter, a new
HT RAM address is accessel If this new address contains a zero (indicating that a horizontal tab was set at this
position), the MEM signal is present at pin 6 of the HT RAM. This MEM signal combines at E27 with the Clear
Data Available (CDA) signal associated with the space code that just incremented the Horizontal Counter and
resets the HT flip-flop E25. This resetting action enables the UART, clears the Data Available signal path, and
removes the increment signal from the Horizontal Counter at E26 pin 1.
If the MEM signal is not present at the HT RAM, the horizontal tabs circuits increment the counter at SRC,
i~ space code at SRO, and continue this spacing cycle until the next horizontal tab location is reached
(MEM signal out of the HT RAM).

14.4.3.4 Clearing Horizontal Tabs - Horizontal tab locations are cleared (erased) by either of two events: receiving an ESC2 command or during a power-up sequence (wake-up routine).

The ESC2 command is detected by th_e decoding circuits and is applied as a clearing pulse to E14 in the horizontal tabs circuits. The leading edge of this clearing pulse enables the Storage Latches E33 and E37 which load and
store the current value in the Horizontal Counter. The trailing edge of this pulse clocks JK flip-flop E40. The
high level output of E40 (Q) resets the Horizontal Counter to zero for the duration of CDA. Then the Counter
starts counting ·up from zero at the Option Clock rate. As the Horizontal Counter increments, the low level on
the write input (pin 12) of the HT RAM writes Os into each address location the Counter advances through.
Zeros are written because pin 8 of E40 is low during a clearing function. When the Horizontal Counter overflows, the CARRY signal is applied through El4 to set E8. As E8 sets, the JK flip-flop (E40) is reset, removing
the writing function from the HT RAM and reloading the Horizontal Counter with the print head value previously stored at the outset of the clearing action. Now the HT RAM is cleared of any tab settings and the
Counter contains the value of the column in which the print head is positioned.
During a power-up sequence the Wake-Up command (WU) performs a function similar to the ESC2 command.
All actions are the same except that the Horizontal Counter value stored in the latches at the beginning of the
sequence is zero because the print head is always at column position 0 after a wake-up; therefore, the Counter
value is zero also.
14.4.4 Top of Form (TOF) Circuits Basic Block Diagram
The basic block diagram for the TOF circuits is shown in Figure 14-7 and the operational sequence flow diagram
is shown in Figure 14-8.

The TOF circuits perform three major functions:
1.
2.
3.

Monitoring the vertical position of the print head
Form feeding
Setting form length values

14.4.4.1 Monitoring - This section of the option monitors the incoming data for codes that affect the vertical
position of the print head. It responds to four codes:

1.
2.
3.
4.

Vertical tab store4._:. VT at pin 6 of E29
Line feed code - L£..at pin 1 of E21
Form feed code - FF at pin 10 of E28
Set TOF command - TOF at pin 3 of EIS

14-13

F"F

FROM
DECODING
ANO
GEN CKTS

TO
TIMING CKTS
VT'+FF'

5
FORMS
CONTROL
ASSEMBLY
AND
E2

OR
E21

E29

TOF

5
SET TOP OF
SET TOF
3
FORM
1--="___:_::..:...._-.,+-1
SWITCH
FORMS
LENGTH
SWITCH

E16

VT'
SRC

TOF

FROM DECODING
AND GEN
CKTS

r---1
!MULTI -1

I PLEXER I

VERTICAL
'-'-,---+-I-+-------COUNTER

E36 J

E34
E35

L-~~J

3
WU
(NOT USED IN
TOF OPERATION)

6 LOAD

SRB

E15

ANO
E2

ENABLE
LF CODE GEN
TO DECODING
AND GEN CKTS

CLOCK

ff 13
CDA 12

OR
E12

CP- 2355

Figure 14-7 Top of Form Circuits Basic Block Diagram
The VT and LF signals applied to E29 and E21 respectively enable the Line Feed Code Generator and increment
the Vertical Counter E34, E35 at SRB time. The VT' signal is a low level that remains low as long as the option is
performing a vertical tab, but the LF signal is a pulse that exists long enough to clock (increment) the Vertical
Counter.
NOTE
The LF code also energizes the Line Feed Code Generator
El and ElO through E2 which places an LF code on the
bidirectional lines to the Character Buffer. This optiongenerated code is actually in parallel with the LF code
generated by the UART. Both codes are available to the
Character Buffer because the UART is not disabled by the
Tabs Option when an LF code is detected. The VT' signal
from pin 4 of E29 that is applied to the timing circuits does
cause the UART to be disabled and, in this instance, the
Character Buffer accepts the LF code generated· by the
Tabs Option.
14.4.4.2 Form Feeding - A Form Feed command detected by the decoding circuits sets Form Feed flip-flop
E28. When E28 sets and stores the FF command, a high level from pin 9 initiates the following four actions:
1.

2.
3.
4.

UART is disabled.
Data Available signal path is blocked.
Vertical Counter is ready to be incremented by one count.
Line Feed Code Generator is enabled.
14-14

DATA FROM UART

ATSRD ISSUE
DATA AVAILABLE

START TIMING
SEQUENCER

CP-2356

Figure 14-8 Top of Form Circuits Operational Sequence
14-15

The FF' signal from pin 4 of E29 is applied to the timing circuits where it blocks the Data Available path through
E15 and disables the UART through El. The FF' high level at pin 10 of AND gate E2 is clocked through at SRB
time to energize the LF Code Generator and increment the Vertical Counter by one count. If this increment
overflows the Counter, the TOF signal is present at pin 12 of E34. This TOF signal is used to clock E16 pin 8 to a
low level and to load the Vertical Counter through Multiplexer E36, E42 with the FORMS LENGTH switch
value at SRC time. At SRD time the option-generated Data Available signal is issued and a line feed code is sent
to the microprocessor. When the CDA signal is sent back to the option indicating that the line feed code was
processed, the CDA signal resets E16 at pin 13. The TOFSL signal generated when E16 resets causes the FF flipflop E28 to reset also.
If the Vertical Counter does not overflow after being incremented (no TOF signal), the FF flip-flop E28 remains
set and holds the UART disabled. The CDA signal, returning after the first line feed code was processed, resets
the Timing Sequencer. But, because the FF flip-flop is still set, the Form Feed Stored (FF') signal immediately
restarts the Timing Sequencer again. At SRB time the Vertical Counter is incremented again and the LF Code
Generator issues another line feed code. If this increment still does not overflow the Vertical Counter, the line
feed code generation sequence is repeated again and again until the TOF signal is present at pin 12 of the
VerticalCounter. When the CDA from the last LF returns, the Counter resets to the value of the FORMS
LENGTH switch and the option removes the disable from the UART. The option has completed the top of form
sequence and is now waiting for line feed or form feed codes before starting any action again.

14.4.4.3 Setup and Wake-Up - Initial setup of the TOF circuits is accomplished when the setting oft.he FORMS
LENGTH switch is parallel loaded into the Vertical Counter as the SET TOP OF FORM pushbutton is
depressed. This places a low level pulse on pin 1 of E34 and E35 (the load inputs) through E16 and E20. The
Vertical Counter loads just as if a TOF occurred. The Wake-Up (WU) signal generated on the Logic Board
during a power-up sequence performs the same parallel loading action and also ensures that the FF flip-flop E28
is cleared.
14.4.5 Vertical Tabs Circuits Basic Block Diagram
Figure 14-9 shows the basic block diagram for the vertical tabs circuit. The operational sequence for these
circuits is shown in Figure 14-10.
The vertical tabs circuits perform the following four major functions:
1.
2.
3.
4~

Monitoring the vertical position of the print head
Setting vertical tab locations
Tabbing action
Clearing vertical tab locations

As discussed earlier, vertical tab functions are very similar to top of form actions and in many instances both
circuits share common components. This circuit sharing is shown graphically by the shaded components in
Figure 4-11. As shown, most of the shaded components are relative to the major functions of monitoring,
Counter incrementing, and Counter reloading. The unshaded components primarily process the unique commands associated with the vertical tabs circuits.
14.4.5.1
1.
2.
3.
4.
5.

Monitoring - The following five incoming codes affect the function of the vertical tabs circuits:
Vertical Tab command -_yT at pin 4 of E28
Form Feed command - FF at pin 10 of E28
Line Feed code - LF at pin 1 of E21
Set HT command - ESC3 at pin 12 of E6
Clear HT command - ESC4 at pin 2 of El 7 and at pin 3 of E18

14-16

FORMS CONTROL
ASSEMBLY
SET TOP OF
FORMS SWITCH

SET TOF

t-------1
FORMS
LENGTH
SWITCH

AND

I---;

TOF

[

TOF

LATCHES

1----r--'

NANO

1 5
H-ID
ESC4
FLIP
_ _ 3 FLOP 6
ESC4- C E180

VERTICAL
COUNTER

L _ . MULTIPLEXER

r;:

4 SRC

E34,E35

E36, E42
DIFFERENTIATOR
RIO
.___ C43

0t'c6i~ ~

AND

,--?.

E12

LOAD

~
5

WU~

E15

"02"

E30, E41

"DA" 11
FROM --IC
TIMING
CKTS

WOO]

"02"

µL

- "[l

VT
RAM

E28
0 t--

r-----1 c

E24

[

..L.,i;:-

1
CDA-

E29

AND
E12

wu.3,
11

OR
E6

.....

1 5

VT
E28

L-.c
~

VT' 8 FF'

1 9

SRO~

E12

no~

FROM
DECODING AND
GENERATING (
CKTS
1MEM

CLOCK

l
AND

CDA !..£

E17

ESC3~

FF@._

AND

E18

TO TIMING
CKTS

6
CDA--2.,

E16

9 LOAD
±D
1t--TOMUX
-=
LOAD

CLEAR

1 t-

.--.2-

t---'

'--i;r-'

LOAD FROM E18
1" LOADS LATCHES
O" LOADS SWITCHES

E12

OR
E29

~
9
SRB-

AND
E2

ENABLE
LF COD E
GENERA TOR
8
TO DECODE AND
GENERATING CKTS

LF
FROM DECODING
AND GENERATING
CKTS

01--

02"
CP- 2359

Figure 14-9 Vertical Tabs Circuits
Basic Block Diagram
14-17

DATA FROM UART

NO
NO

NO
DURINGSRC
1. LOADVT
COUNTER
WITH SWITCH
VALUE
2. STORE TOFSL
IN E16

START TIMING
SEQUENCER

ATSRDWRITE
"O" INTO PRESENT·
VT RAM ADDRESS

NO
ATSRD
ISSUE DATO
CHARACTER
BUFFER
STORE VT
COMMAND
IN E28

END SETUP
ROUTINE
GOTO HT
SEQUENCE
(FIG.14-6)

STORE FF
COMMAND
IN E28
NO
NO

DURING SRA
1. DISABLE UART
2. BLOCK INCOMING DA

LOAD VT
COUNTER
VALUE INTO
LATCHES

1. DISABLE LF

YES

CODE GEN
(IFSETl
2. RESET TIMING
.SEQUENCER

NO
DURINGSRB
ENABLE LF
CODE
GENERATOR

ATCDA OF ESC4
CLEAR VT
COUNTER TO
ZERO

INCREMENT VT
COUNTER TO
OVERFLOW

STORE ESC
IN E18
YES
DURINGSRB
INCREMENT
VT COUNTER
BY 1

NO
WAIT FOR NEXT
CHARACTER
FROM UART

CL-EAR ESC
IN E18

WRITE "1" IN
ALL VT RAM
ADDRESSES

1. RESET E28
2. ENABLE UART

1. START TIMING
SEQUENCER
2. ENABLE LF
CODE GEN

VERTICAL TABS
SEQUENCE
COMPLETED

LF LOOP

CP-2358A

ATTOF LOAD
VT COUNTER
WITH VALUE
IN LATCHES

END CLEAR
ROUTINE

CP-23588

Figure 14-10 Vertical Tabs Circuits
Operational Sequence

14-18

FORMS CONTROL
ASSEMBLY
SET TOP OF
FORMS SWITCH

SET TOF

t------FORMS
LENGTH
SWITCH

AND

I--

TOF

I;:

4 SRC

H-D
1
ESC4
FLIP
FLOP 6

MULTIPLEXER

LATCHES

1-----r--

r---'2---- 9 L 0 AD

11- TO M UX
LOAD

"""
E34,E35

E36, E42
DIFFERENTIATOR
RIO
C43

L-....

0t~6i~ ~

AND

E12

LOAD

~
5

WU~

E15

9
10

E30, E41

"DA" 11
FROM - C
TIMING
CKTS

CLEAR

CLOCK
8 UP

"02"

AND

E17

ESC3~

AND

SRO~

CDA!..£

E12

VT
RAM

FROM
DECODING AND
GENERATING<
CKTS

FF
E28

f----c

w
~

±D
1
VT
E28

...£_
13

E29

CDA __!__

AND

H
E12
wu3.,

OR
E29

4
2
t-----'-1

E24

VT' a FF'

TO TIMING
CKTS

01-

6
coA-2.

FF~

L____. c

E18

11-E16

.,i;;- D

LOAD FROM E18
1" LOADS LATCHES
O" LO AD S SW ITCHES

'-c;r-

I--

E12

"02"

ESC4~ C E18 0
VERTICAL
COUNTER

NANO

__["""

OR
E29

SRB~
LF
FROM DECODING
AND GENERATING
CKTS

AND
E2

ENA BL E
LF COD E
GENER ATOR
TO DECODE AND
~ GENERATING CKTS

01-

:=y-

02 11
CP-2359

NOTE
Shaded components common to
both TOF and Vertical Tabs Circuits.

Figure 14-11 Common Components of
Vertical Tabs and TOF Circuits

14-19

The line feed code at E21 pin 1 causes the Vertical Counter to increment by one count at SRB time.
NOTE
The only function of a received line feed code is to
increment the Vertical Counter. As in the TOF circuits, at
SRB the Line Feed Code Generator is enabled and the
UART is not disabled. Thus, the parallel LF code generation occurs at the input to the Character Buffer again.
14.4.5.2 Vertical Tab Setup - The ESC3 command establishes a vertical tab at the line location of the print head
when the command is given. At SRD the ESC3 command enables the write input (pin 12) of the VT RAM. At
this time there is a low level on the data input (pin 13) of the VT RAM and a 0 is written into the VT RAM
location that is addressed by the Vertical Counter output. Whenever the ESC3 command is detected, a 0 is
written into the VT RAM location corresponding to the print head position. A vertical tab can be set on any or
all printable lines of a form.
14.4.5.3 Vertical Tab Action - A Vertical Tab command detected by the decoding circuits sets VT flip-flop E28.
When E28 sets it causes the same action through E29 pin 5 as when the FF flip-flop sets. These actions are the
same as in the TOF circuits.
l.
2.
3.
4.

UART is disabled through El.
Data Available signal path is blocked through El5.
Vertical Counter is incremented by one count at SRB time.
Line Feed Code Generator El, ElO is enabled at SRB time.

As the Vertical Counter increments, a new VT RAM address is accessed. If this new address contains a
(indicating that a vertical tab was set at this position), the MEM signal is present at pin 6 of the VT RAM. This
MEM signal combines with the CDA signal associated with the line feed code that just incremented the Counter
and resets VT flip-flop E28. Again, this resetting action enables the UART, clears the Data Available signal path,
and removes the increment signal from the Vertical Counter.
If the MEM signal is not present at the VT RAM, the vertical tabs circuits increment the Counter at SRB, issue
an LF code at SRD, and continue this paper advancing cycle until the next vertical tab position is reached (MEM
signal out of VT RAM) or the top of form is reached (TOF signal out of Vertical Counter). If a TOF occurs
during.a vertical tab operation the same loading and resetting events take place as in a normal TOF function.
These actions are:

The TOF signal out of Vertical Counter:
a.

Clocks a high through E16 to clear E28 at CDA time.

Is not passed through NAND gate E12 pin 9 (the reset for LOAD flip-flop) because pin 10 is
held low.

Loads the Vertical Counter with value of FORMS LENGTH switch at SRC time.

The switch setting is selected (not the latches) because the steering Multiplexer E36, E42 has a 0 on
pin 1.

14-20

14.4.5.4 Clearing Vertical Tabs - Vertical tab locations are cleared (erased) by either of two events: receiving an
ESC4 command or during-a power-up sequence (wake-up routine).
The negative-going ESC4 pulse generated by the decoding circuits is applied to El 7 pin 2 and E18 pin 3. The
leading edge through E 17 enables the Latches E30, E41 and the current print head position value of the Vertical
Counter is transferred into these latches. At the trailing edge of the ESC4 pulse E18 clocks a high level out on pin
5 (the Q2 signal). This Q2 signal initiates the following actions:
I.
2.
3.

Vertical Counter clears to zero count at CDA (of the 4 in the ESC4 command) through El 7 pin 6.
Vertical Counter increments up from zero at the rate of the Option Clock through E12 pin 6.
All VT RAM addresses written with ls through E29 pin 13.

As E 18 sets, the high level load signal on pin 9 is applied to the Multiplexer E36, E42. This load signal conditions
the multiplexer to pass the data stored in the latches and load the Vertical Counter with this data.
NOTE
The value in the latches is the vertical position of the print
head at the time the ESC4 command was given. Thus, this
position is not lost as the counter is incremented to erase
the VT RAM.
The low level on pin 8 of E18 is used to reset the ESC4 flip-flop El8. The DA signal associated with the next
character received resets E18 at pin 11 to complete the vertical tab erasing action.
The clearing sequence performed when a wake-up occurs is somewhat similar to an ESC4 command and is as
follows:
1.

ESC4 flip-flop E18 sets and forces Q2 to a high level at the leading edge of the wake-up pulse.

At this time the load signal at E18 pin 9 is 0 and the Wake-Up signal transfers the FORMS LENGTH
switch value through the multiplexer to load the Vertical Counter (WU at EIS pin 4) and then enables
the latches (WU at El7 pin I) to store this switch setting.

During this time the Option Clock cannot increment the Vertical Counter because the loading action
overrides the clocking function.

At the trailing edge of the wake-up pulse the Vertical Counter starts incrementing through El2 at the
Option Clock rate.

Each VT RAM address is written with a 1 because Q2 signal is still high on pin 13 of the VT RAM.

At TOF (Counter overflow) E18 sets, making the Load signal high and resetting the ESC4 flip-flop
(Q2 is now low).
·

The high level Load signal causes the multiplexer to select the value stored in the latches and E15 pin
5 loads this value into the Vertical Counter.

DA signal from the next character received resets E18 and the wake-up clearing routine is completed.

After wake-up the vertical tabs circuits are cleared and are set with the value of the new form and consider the
print head to be positioned at the top of this new form.

14-21

14.5 TROUBLESHOOTING
The troubleshooting chart in Table 14-4 lists the common trouble symptoms that could be observed during
installation checkout or normal operation.
14.6 LAXX-KY PRINT SET
Figure 14-12 is the supporting diode matrix for the LAXX-KYprint set. The print set is shown at the end of this
chapter.

14-22

Table 14-4
Troubleshooting for VT, HT, and TOF Option (LAXX-KY)
Probable Cause

Action

Cabling

Wrong cabling connections

Check all cabling between
M7728 Logic Board, Expander Board, and TOF
Assembly beneath top cover

Option location

Option inserted in wrong
location on Expander Board

Install Tabs Option in locations A and B

Data Available
signal distribution

Signal path interrupted

Check for Data Available
signal in at El 5 pin 13 and
out at El9 pin 12

LF Code Generator

LF code not being generated

Check El and ElO for LF
code

D-CS-M7736-0-1,
Sheet 3

Vertical Counter

Vertical Counter not loading
proper value

Check E34 and E35 for proper
operation during load

D-CS-M7736-0-1,
Sheet 2

Set TOF assembly

Incorrect value being loaded

Check operation of SET TOP
OF FORM switch and FORMS
LENGTH switch

3. Performs TOF and VT
operations but not HT
operations

Space code

Space code not being
generated

Check El and ElO for the
space code

D-CS-M7736-0-1,
Sheet 3

Horizontal Counter

Horizontal Counters not
loading proper value

Check E32 and E38 for proper
operation during load

D-CS-M7736-0-l,
Sheet 5

4. Performs HT and TOF
operations but not VT
operations

LF code

LF Code Generator not
energized

Check E28 pin 5 for a high
level on VT command

D-CS-M7736-0-1,
Sheet 2

Vertical tabs circuits

VT tabs not being cleared
by ESC 4

Check El 8 pin 5 high at
ESC4

D-CS-M7736-0-1,
Sheet 2

Check all circuitry not
common with TOF circuits

Figure 14-11

Symptom
1. After installation, improper
operation or no operation
of terminal

2. Performs HT operations
but VT and TOF operations not correct

Problem Area

Vertical tabs circuits

Reference
Figure 9-4

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Figure 14-12

LAXX-KY Diode Matrix

14-24

J1 M7735
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14-29

CHAPTER 15
AUTOMATIC LINE FEED OPTION (LAXX-LA)

15.1 AUTOMATIC LINE FEED INTRODUCTION
The function of the Automatic Line Feed Option is to insert a line feed code after receiving or transmitting a
Carriage Return command.
In the transmit mode of operation, this feature eliminates having to type the keyboard LINE FEED key after
each Carriage Return command at the end of each line. With this option installed and the front panel AUTO LF
switch depressed, typing the CARRIAGE RETURN key causes a line feed code to be transmitted after the
carriage return code.
In the receive mode of operation, an incoming carriage return code is detected by this option and it automatically
inserts a line feed code after the carriage return code. This is a convenience feature for existing programs that do
not normally follow a carriage return code with a line feed code. A wire jumper (Wl) located on the automatic
line feed option circuit board permits the automatic insertion of a line feed code after a received carriage return
code. Removing this jumper disables the automatic insertion of line feed codes when operating in the receive
mode but does not affect the transmit mode, which is controlled by the AUTO LF switch.
15.2 AUTOMATIC LINE FEED FUNCTIONAL BLOCK DIAGRAM
Figure 15-1 shows the functional block diagram of the Automatic Line Feed Option in a typical installation.
Incoming data (SI) is processed by the UART on the M7728 Logic Board then routed through the Expander
Option Mounting Board to the Receiver Section of the Automatic Line Feed Option Board. This section of the
option monitors each incoming character and, after receiving a carriage return code, generates a line feed code.
This line feed code is inserted right afier the carriage return code and is sent back to the Character Buffer on the
bidirectional line. The Character Buffer accepts both the carriage return and the line feed codes as if they were
sent into the terminal from an external source. The printer mechanism reacts to this internally generated Line
Feed command in a normal manner.
In the transmit mode of operation, charapters typed at the keyboard pass through J3 on the Expander Option
Mounting Board to the Transmit Section of the option. When the CARRIAGE RETURN key is depressed, the
option detects the carriage return code and inserts an option-generated line feed code after the carrige return
code. The carriage return from the keyboard and the line feed from the option are routed to the UART on the
M7728 Logic Board. The UART processes and transmits these two codes just as if both were originally generated
by two separate keys.

15-1

I DECWRITER TERMINAL

'M7128LoG'iC'BoA~R-D___ -

S.I.

UART

TRISTATE
BUFFER

CHARACTER
BUFFER

TO
PRINTER
MECHANISM

S.0.-"------~

I
I

"0Pr10Nl

EXPANDER
MOUNTING BOARD

LOCATION

"C"

"Du

TRANSMIT

RECEIVE

SECTION

AUTOMATIC
LINE FEED
OPTION

KEY
BOARD

I
I
I
I
I

L----------'

CP-2363

Figure 15-1

Automatic Line Feed Functional Diagram

If the terminal is operated in the local mode, with the front panel AUTO LF switch depressed and Jumper Wl
inserted on the option circuit board, a carriage return code from the keyboard causes a carriage return and two
line feed increments at the printer mechanism. This action occurs because the Transmit Section of the option
adds a line feed code after the carriage return from the keyboard then the Receive Section of the option inserts
another line feed code as the carriage return code leaves-the UART for the Character Buffer. Thus, two line feed
codes are acted on by the printer mechanism.

NOTE
When the terminal is on-line and transmitting in an echo
mode and if the AUTO LF switch is in the down position,
the option generates a line feed code after each carriage
return. In this operational configuration, the printer mechanism advances two lines for each carriage return, even
though only one line feed code is being transmitted out
from the terminal. The second line feed occurring at the
terminal is generated by the returning (echoing) carriage
return as it is processed by the Receiver Section of the
option.

15-2

15.3 AUTOMATIC LINE FEED BASIC BLOCK DIAGRAM
The basic block diagram for the Automatic Line Feed Option is shown in Figure 15-2. This diagram is a simplified representation of the automatic line feed circuit schematic (D-CS-M7738-0-l). Circuit designations and
pin numbers indicated on Figure 15-2 correlate with corresponding components on the schematic. Buffers,
inverters, and other components that do not have major operational functions are omitted from the block
diagram.
The Automatic Line Feed Option can be divided into two functional areas: Transmit Section and Receive
Section.
LOC
11011

LOC

"c"
LINE
DRIVERS
E4, E5

KEYBOARD DATA
FROM
KEY
BOARD

r-----,
TRANSMIT
CR
DECODER
E10, E11
KEYSTROBE

AUTO LF:

_J_

I
I

FRONT :
PANEL

TRANSMIT 1-'H"'-IG;;.;..H;___

_, DISABLE

LF
CONTROL
ES

ENABLE

TO
Ul\RT

LF CODE
GENERIUOR
E1, E2

L.------J
OR
E3

KEYSTROBE

TRANSMIT SECTION

LOC

"o"
..... .-"-

11011

,.....:::..

UART DISABLE

FROM
LOGIC

..
h.

UART

DA~)

CARRIAGE
RETURN
DECODER
E10,E11

RECEIVE
LF
CONTROL
ES

UART DATA AVALIABLE

LF CODE

~ GENERATOR
Q2,Q3,E7

LF CODE

--'\.

OPTION GENERATED DATA AVAILABLE

'---'

1-- CHARACTER
BUFFER

'---'

RECEIVE SECTION

Figure 15-2 Automatic Line Feed Block Diagram

15-3

CP-2364

15.3.1 Transmit Section
Figure 15-3 shows the operationa\ sequence of the Transmit Section. The Transmit Section accepts keyboard
characters and their associated keystrokes from the Expander Option Mounting Board through an edge connector at location D. If the front panel AUTO LF switch is not depressed, each keyboard character is passed
through Line Drivers E4 and E5 then out through location C to the UART on the M7728 Logic Board. The
corresponding keystrobe for each character is also passed through without any action being taken by the option.
Transmit Carriage Return Decoders EIO and Ell monitors these characters from the keyboard and when a
carriage return is detected and the front panel AUTO LF switch is depressed, the CR KBRD L signal is generated. This signal is applied to Transmit LF Control E6 where it initiates the line feed code insertion sequence
after the carriage return code is sent out. First the Line Drivers E4 and ES are disabled (preventing data from the
keyboard from being passed to the UART), then the LF Code Generator El and E2 is allowed to place a line
feed code on the outgoing line to the UART. At the same time the Transmit LF Control generates the KSTB
OUT signal which is interpreted by the UART as a valid keystrobe command. After the UART accepts the line
feed code, the XMIT ROY L signal resets the Transmit LF Control which removes the disable condition from
the Line Drivers and allows keyboard data to pass through the option again.

DATA FROM
KEYBOARD

YES

1. CR PROCESSED
BY UART
2. TURN LINE
DRIVERS OFF
3. GENERATE
LFCODE
4. GENERATE
KEYSTROBE

DATA TO UART
CP-2365

Figure 15-3 Operational Sequence for Automatic Line Feed Transmit Section

15-4

The timing sequence for the Transmit LF Control E6 is shown in Figure 15-4. When a carriage return code from
the keyboard is defected, the CR KBRD L signal at E6-4 sets the first flip-flop and causes E6-5 to go high.
During this time the carriage return code is passed through the option to the UART. The XMIT ROY L signal at
E 12-1 is held high by the UART, indicating that the carriage return is being processed and that the UART is not
ready to accept another character. When the UART is ready for another character, the XMIT ROY L signal at
E 12-1 goes low indicating that the UART has accepted the CR. This low level is inverted by E 12 and then applied
to the clock input of E6-11. When clocked, a high level (LINE FEED ON H) is present at E6-9 and a low level
(LINE FEED ON L) is present at E6-8. The low level performs two functions: (1) enables the LF Code Generator El and E2 which places a line feed code on the output lines to the UART, and (2) combines at E9 with the
XMIT ROY L signal to produce the KSTB OUT pulse and simultaneously resets E6 at pin 3. The high level at
E6-9 disables the Line Drivers E4 and ES which prevents data from the keyboard from passing through the
option. As the option-generated line feed code and keystrobe are processed by the UART, the XMIT ROY L
signal clears flip-flop E6 (pin 11) in the LF Transmit Control. Thus, the LF Code Generator is disabled and the
Line Drivers are enabled again, allowing keyboard data to pass through the option.

E9-:3

X~b~

{
E6 -11 - - - - - - - - .

LINE FEED ON H

---------i-----1 1--~

E6-9
LI NE FE ED ON L
E9-2

---------.'-----'I 1----.

KSTB OUT
(KEY STROBE OUT) _ _ ___,
E9-1
(STROBE
FOR

(STROBE
FOR
LF)

CR)

CP-2366

Figure 15-4 Transmit Line Feed Control Timing Sequence

15-5

15.3.2 Receive Section
Figure 15-5 shows the operational sequence for the Receive Section of the Automatic Line Feed Option. The
Receive Section monitors the received data at a point that is between the output of the UART and the input to
the Character Buffer. This data is present at the option on the bidirectional line through the edge connector at
location D. Receiving both a carriage return code and the signal UART DAL (Data Available signal from the
UART) at the Receive Carriage Return Detector ElO and Ell produces an output signal that is applied to the
Receive LF Control E8, if Jumper Wl is installed. The Receive LF Control initiates three actions:

1.
2.
3.

Disables the UART
Enables the LF Code Generator Q2, Q3, and E7
Issues an option-generated data available signal

Disabling the UART prevents it from sending data to the Character Buffer while the option is issuing a line feed
code. The LF Code Generator places a line feed code on the bidirectional line to the Character Buffer. The
option-generated Data Available signal is interpreted just the same as a UART-generated data available and the
Character Buffer accepts the option-generated line feed code as if it was received by the terminal. After the line
feed code is processed, the CLR DA signal from the microprocessor in the terminal returns the option to the
monitoring condition and it waits for another carriage return code.
RECEIVED DATA
FROM UART

YES

1. DISABLE UART
2. GENERATE
LF CODE
3. SEND DATA
AVAILABLE
SIGNAL FROM
OPTION

DATA TO
CHARACTER
BUFFER
CP-2367

Figure 15-5 Operational Sequence for Automatic Line Feed Receive Section
15-6

The timing sequence for the Receive LF Control E8 is shown in Figure 15-6. A decoded carriage return generates
the CR UART L signal which is passed through Jumper WI to E8-4. This signal sets E8, placing a high level on
both E8-5 and E8-12. After the carriage return code is processed by the terminal, the microprocessor sends the
CLR DAL s·ignal back to the option at inverter El2-9. The leading edge of this signal clocks the high level on E812 through to E8-9 and forces E8-8 to a low level. The trailing edge resets E8 at pin 3. The high on the base of QI
forces the signal UART ENA H to disable the UART. The high/low outputs of E8 that are applied to the LF
Code Generator Q2, Q3, and E7 produce a line feed code. The option-generated data available signal is represented by the low level of the OPT IN L signal. (The steering gates .on the Expander Option Mounting Board
convert this OPT IN L signal to a signal that has the same affect as the Option Data Available signal.) After the
microprocessor accepts the option-generated line feed code and data available, it sends a second CLR DA L
signal back to the option. This resets flip-flop E8 at pin 11 which, then allows the UART to pass received data to
the Character Buffer in a normal manner.

2ndCLRDA

EB-11

UART ENA H

01
OPT IN L
(option generated
data avaiable)
CP-2368

Figure 15-6

15.4

Receive Line Feed Control Timing Sequence

TROUBLESHOOTING

The troubleshooting chart in Table 15-1 lists the common trouble symptoms that could be observed during
installation checkout or normal operation.
15.5

LAXX-LA PRINT SET

The figures at the end of this chapter are the LAXX-LA print set.

15-7

Table 15-1
Troubleshooting for Automatic Line Feed Option (LAXX-LA)
Symptom
1. After installation, characters typed on keyboard
not transmitted

2. After installation, received
characters not printing

Problem Area

Probable Cause

Action

Cabling

Wrong cabling connections

Check all cabling between
M7728 Logic Board and Expander Board

Option location

Option inserted in wrong
location on Expander Board

Install Llne Feed Option in
locations C and D

Keystrobe signal
distribution

Signal path interrupted

Check for Keystrobe signal
into Option Board at E 12 pin
11 and out o.f board at E3
pin 3

D-CS-M7738-0-l,
Sheet 3

Llne Drivers

Llne Drivers on option not
enabled

Check E6 pin 9 for low level

D-CS-M7738-0-l,
Sheet 3

Data Available
signal distribution

Signal path interrupted

Check for Data Available
signal at E9 pin 5

Tri-State Buffer on
M7728 Logic Board

Tri-State Buffer held disabled
by option

Check collector of Ql for high
level

AUTO LF switch

AUTO LF switch not
depressed

Depress switch - if depressed
and still no LF code, replace
switch

Keystrobe signal

Signal not being generated
by option

Check E3 pin 3 for Keystrobe
signal associated with line feed
code

D-CS-M7738-0-l,
Sheet 3

Llne Feed Code
Generator

Line feed code not being
generated

Check for line feed code at El,
E2

D-CS-M7738-0-l,
Sheet 2

JumperWl

Wl not installed

Connect Wl

D-CS-M7738-0-1,
Sheet 2

Data Available signal

Option not generating Data
Available signal

Check for pulse at E8 pin 8

D-CS-M7738-0-l,
Sheet 3

Line Feed Code
Generator

Line feed code not being
generated

Check for line feed code at E7

D-CS-M7732-0-1,
Sheet 3

3. Llne feed code not inserted
after carriage return typed

4. Llne feed code not inserted
after received carriage
re tum

Reference
Figure 9-4

i
I D-CS-M7738-0- l,
Sheet 2
D-CS-M7738-0-1,
Sheet 3

8
"THIS DRAWING ANO SPECIFICATIONS, HEREIN, ARE THE

NOTES:

PROPERTY OF D!GITAL EQUIPMENT CORPORATION AND SHALL

NOT BE REPRODUCED OR COPIED OR USED IN WHOLE OR IN
PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF
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B
3

15-l l

CHAPTER 16
EXPANDER OPTION MOUNTING KIT (LAXX-LB)

16.1 EXPANDER OPTION MOUNTING KIT INTRODUCTION
The Expander Option Mounting Kit provides an interface between an upgradable DECwriter and various
options that enhance the printer's operation. The Expander Option is a printed circuit board that functions as a
motherboard for the following options:

l.
2.
3.
4.
5.
6.

APL/ASCII Dual Character Set LAXX-PK
Selective Addressing LAXX-KW
Automatic Answerback LAXX-KX
Automatic Line Feed LAXX-LA
Forms Control LAXX-KV
VT, HT, and TOF LAXX-KY

These options install on top of the Expander Board and connect to the Expander through type H8S l Edge
Connectors. There are six locations on the Expander Board for edge connectors.
NOTE
Even though there are six locations and six options, it is
not physically possible to have all options installed at any
one time. This is because some options are double width
and occupy two locations. In addition, options are
assigned to unique locations on the Expander Board and
cannot be installed in any other location. The Answerback
and Line Feed Options are assigned 10 the same locations
(C and D) while the Forms Control and VT,HT, and TOF
Options occupy locations A and B.
The Expander Board mounts on hinged rails above the M7728 Logic Board and can be lifted to provide access to
the Logic Board. The options installed do not have to be removed when the Expander Board is raised.
16.2 EXPANDER BOARD DATA DISTRIBUTION
ASCII-coded characters and option commands are applied to and from the Logic Board through ribbon cables
that connect to the connectors on the Expander Board. Figure 1'6-1 shows the data distribution paths on the
Expander Board. Received serial data into the terminal is converted to parallel data by the UART, routed onto
the Expander Board through JS, and applied simultaneously to locations A, B, D, and E. The parallel data
applied back to the UART from the options is also routed through JS. The path between JS and locations A, B,
D, and Eis bidirectional, while there are separate paths to and from JS and location F. The bidirectional line
through JS intersects the data path between the Tri-State Buffer and the Character Buffer on the Logic Board.
This allows the options to sample the incoming characters before they are processed by the terminal. Separate
data paths are connected to location F. The input to location Fis from the output of the Character Buffer and
the output from F is applied back through JS to the Print Head Drivers. This routing permits an optional
character set option installed in location F to substitute incoming characters with characters from the alternate
set.
16-1

OUTPUT OF
CHARACTER
BUFFER

Bl- DIRECTIONAL
TO AND
FROM LOGIC
BOARD

TO TRANSMIT
SECTION OF UART

FROM
KEYBOARD

TO PRINT
HEAD DRIVERS

EXPANDER
OPTION
MOUNTING
BOARD

OPTION LOCATIONS~LOC

OPTIONAL
CHARACTER
SET
OPTION

SELECTIVE
ADDRESSING
OPTION

Figure 16-1

ANSWERBACK
OPTION
OR
AUTO LINE
FEED OPTION

i ~
B

FORMS
CONTROL
OPTION

VT,HT AND
TOF OPTION

CP-2337

ASCII Data Distribution on Expander Board

Transmitted characters from the keyboard are connected to the Expander Board at J3 and are routed directly
across the board to exit out J2. All typed characters are presented at location E for monitoring by the option. If
either the Answerback or Line Feed Options are installed, no cable is connected to J2. Therefore, the data path is
now: in through J3, through location D into the option, out of the option through location C, and out to the
Logic Board through J 1. This routing places either of the two options in series with the keyboard characters and
allows them to insert data (answerback messges or carriage return codes) into the transmitted output.
16.3 EXPANDER BOARD CONTROL SIGNAL DISTRIBUTION
In addition to distributing ASCII data, the Expander also routes the control signals to the options. The two
control signals are the Data Available signal associated with each received character and the Keystroke signal
sent with each typed character.
16.3.1 Routing of DATA AVAILABLE Signal
The Data Available signal is issued by the Receive Section of the UART after a serial character is converted to
parallel and is ready to be transferred to the Character Buffer. This character is applied to all options in parallel
(Figure 16-1) but the Data Available signal for the character is applied to the options sequentially. This method
of distribution is commonly called a daisy chain. The Data Available signal distribution is shown in Figure 16-2.

16-2

The Data Available signal enters the Expander Board through J5 and is routed, in order, to locations E, D, A,
and B. If there is an option installed at a location, the Steering Gates for that location diverts the Data Available
signal into the option. If no option, these gates direct the signal on to the next location.

DATA AVAILABLE
,-SIGNAL TO
MICROPROCESSOR

DATA AVAILABLE
SIGNA L FROMUART

[

EXPANDER
OPTION
MOUNTING--.......
BOARD
DATA
AVAILABLE

STEERING
GATES

A_
-----

STEERING
GATES

_----1--..___

OPTION
BOARDS~

-•

l l

l
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---

I
I
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L ___ _J

E
I

I
I

L ___ _J

I
I
I
I
I
I
L ___ _J

I
L ___ __J

CP-2338

Figure 16-2

Data Available Signal Distribution on Expander Board

There are two methods employed by these Steering Gates to divert the Data Available signal. These methods are
shown in Figure 16-3. Method No. 1 is used at locations A and E and utilizes the OP IN signal as the control
signal. With no option installed, the Data Available signal is coupled right past this location to the next location
in the daisy chain. Installing an option grounds the OP IN signal causes the Data Available signal to be diverted
into the option. The option delays the Data Available signal long enough to establish whether the ASCII code
contains a command recognizable for that particular option. The Data Available signal exits from the option on
the DA OUT line and is applied to the next option in the chain.
In Method No. 2 (used at location B), the Data Available signal passes right through the Steering Gates when no
options are installed. Installing an option in either of these locations grounds the DA OUT line (rather than the
OP IN line as in Method No. 1). The OP IN line of Method No. 2 is held high until the option has generated the
ASCII character it is inserting into the transmit data, then the OP IN line pulses low. This pulse is the optiongenerated Data Available signal that is applied to the next option in the chain.

16-3

DA IN

TO NEXT
)---OPTION IN
DAISY CHAIN

+ V ~AA-----J

r-....t.--,

I oP~?oN I
L,_,_J
II

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L_~::..:..:.._~.i.-,.---r~~

I
DA

OUT

A. Method No. 1 - Option Not Installed

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>----OPTION IN
DAISY CHAIN

1 oPTION

I
OP IN

DA OUT

B. Method No. 1 - Option Installed

DA IN

r-i-1

TO NEXT

+ v -'\/11"--r---I

~--OPTION

IN
DAISY CHAIN

NO
I OPTION
I
L1--r1
1

1L _

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I
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TO NEXT
>----OPTION IN
DAISY CHAIN
METHOD
#2
OPT ION
INSTALLED

OPTION

OP IN

CP-2339

D. Method No. 2 - Option Installed

Figure 16-3

Methods of Switching Data Available Signal into Options

16-4

16.3.2 Routing of KEYSTROBE Signal
Distribution of the Keystrobe signal on the Expander Board is shown on Figure 16-4. As each character is typed,
its ASCII code and associated Keystrobe signal are applied through J3 and routed out J2 (if the Answerback or
Line Feed Options are not installed). The Selective Addressing Option at location F monitors all typed characters but is not in series with the data path as are either the Answerback or Line Feed Options which are installed
at locations C and D. These options can break and insert characters and keystrobes into the transmit data line to
the UART.
TO TRANSMIT
SECTION OF UART

FROM
KEYBOARD

mJJ
J2

EXRINDER
OPTION
MOUNTING
BOARD

LOC F

I
SELECTIVE
ADDRESSING
OPTION

I
I

IL _ _ _ _ _ _ _ __JI

ANSWERBACK OR
AUTO LINE FEED
OPTIONS
CP-2340

Figure 16-4 Keystrobe Distribution on Expander Board

16.4 TROUBLESHOOTING
The troubleshooting chart in Table 16-1 lists the common trouble symptoms that could be observed during
installation checkout or normal operaton.
16.5 LAXX-LB PRINT SET
The figures at the end of this chapter are the LAXX-LB print set.

16-5

Table 16-1
Troubleshooting for Expander Option Mounting Kit (LAXX-LB)
Symptom

°'
°'

Probable Cause

Action

Reference

1. With no options installed on
board, cannot receive

Cabling

Wrong polarity of bidirectional
cabling

Check polarity between JS of
Expander Board and JS of
Logic Board

2. With no options installed
on board, cannot transmit
from keyboard

Cabling

Wrong cabling connections

Check all cabling between
M7728 Logic Board and Expander Board

Figure 9-4

Circuit board etch

Open circuit

Check continuity between J2
and J3 on Expander Board

D-CS-S4 ll 668-0-1,
Sheet 3

Signal distribution
problem

Short or open in etch or
cabling - or possibly a fault
on Logic Board

To isolate between Logic
Board and Expander Board,
perform the following:

3. With no options installed
on board, not able to transmit or receive
I

Problem Area

1. Remove cable from JS
on Expander Board
2. Remove keyboard cable
from J3 on Expander
Board and plug into J2
on Logic Board
If still not able to transmit or
receive, troubleshoot Logic
Board. If able to transmit and
receive, check continuity of all
cables and etch on Expander
Board.

8
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16-9

CHAPTER 17
EIA INTERFACE OPTION KIT (LAXX-LG)

17.1 EIA INTERFACE INTRODUCTION
The EIA Interface Option provides a signal interface between a DECwriter and most modems, acoustical couplers, or other interfacing devices that use EIA levels. The EIA interface converts the level of the transmitting and
received data from TTL to EIA bipolar (when the DECwriter is transmitting) or from EIA bipolar to TTL (when
the D ECwriter is receiving).
The EIA interface circuits provide the connect and disconnect control signals required in a communicationsswitched network environment and the carrier frequency selection command required in a multipoint network.
The EIA interface also monitors the operational status of both the terminal and the modem and, if either changes
to a non-operational condition, the other is notified by the EIA.
17.2 EIA INTERFACE FUNCTIONAL BLOCK DIAGRAM
Figure 17-1 shows the EIA interface in a typical installation. Transmitted and received data signals are converted
from one voltage level to another (TTL to EIA or EIA to TTL) as they "pass through the EIA board. Status and
control lines are monitored by the EIA circuits and, in the event of either a not ready or disconnect condition,
appropriate commands are generated by the EIA.

17-1

loE~I;;; ~;,;A~

- - - - - - - -,

SELECTIVE
ADDRESSING
OPTION
(LAXX-KW)

I
EIA

LOGIC
BOARD
M7728

INTERFACE
(LAXX- LG)
KSTRB DIS L
(TRI LEVEL SIGNAL)

I
I

TYPICAL
MODEM
CONTROL AND
STATUS

AUTO
ANSWER BACK
OPTION
(LAXX-KX)

TERMINAL STATUS

__ .....t-, I-------''
XMIT

TRANSMITTED DATA

- - ..,...... t - - - - - - - - ,

'----------,-------!
,_..,__ -RECEIVED DATA

REC

L ______________ _J

CP- 2341

Figure 17-1

EIA Interface Functional Diagram

The major command from the EIA to the terminal is the KSTRB DIS L signal. This command connects directly
to the Logic Board in the terminal and also, if they are installed, to the Selective Addressing Option (LAXXKW) and Answerback Option (LAXX-KX) as shown in Figure 17-1. The KSTRB DIS L command is a trilevel
signal capable of attaining three distinct voltage levels: 0, M, or H. (0 = 0 V to 0.4 V; M = 2.0 Vto 3.0 V; H = 4
V to-' V. Voltage values are approximate and vary with the number of options on the trilevel line.) Each level is
the result of a specific operational status and effects certain functions in the terminal and in the options connected to the line. Figure 17-1 shows this trilevel line as an input-only to both the Logic Board and the Answerback Option, and both an input and output from the Selective Addressing and EIA Options. Table 17-1 contains
the various levels of this trilevel line and the effects on the overall system at each level.

17-2

Table 17-1
Effect of Tri-State Line Levels
Tri-State
Signal
Level

Generated
by
Option

Selective
Addressing

Terminal is not the
master and not able to
transmit as a slave
(transmit disable)

Prevents DEVICE
SELECT light from
illuminating

All requests for the
answerback message are
disregarded

Prevents Request to
Send signal from being
sent to modem

Inhibits transmitting
from keyboard

EIA
interface

Modem is not properly
set up to pass data
from terminal (Clear
to Send signal not
present at EIA)

Prevents DEVICE
SELECT light from
illuminating

Stores any received
request for answerback
message then transmits
message after Clear to
Send signal is received
by EIA (The Tri-State
signal is H).

Permits a Request to
Send signal to be sent
to modem

No effect - Able to
transmit from keyboard

EIA
interface

Modem is able to
pass data from
terminal (Clear to
Send signal has been
received by EIA)

Allows the DEVICE
SELECT light to be
turned on

Answerback message
can be transmitted
when request is
received

Permits a Request to
Send signal to be sent
to modem

No effect - Able to
transmit from keyboard

When

Selective
Addressing

Effect on Other Options
Auto
EIA
Answer back
Interface

LogiC
Board

The EIA can only generate an M or H level but not a 0 level. The Selective Addressing Option only generates a 0
level and only responds to an H level. Also, the Selective Addressing Option has overriding control on the trilevel
line in all cases of dispute. For example: if the EIA is generating an H (when modem is ready to accept transmit
data) and at the same time the Selective Addressing Option is generating a 0 (when terminal not selected as a
master or transmit enabled slave), the O level takes precedence and the terminal is transmit disabled.
In installations where the Selective Addressing Option is not included, the trilevel line has only two states, M or
H. The absence of the Answerback Option has no effect on the trilevel line because this option only uses the line

as an input not as an output.
When the EIA is configured in a switched network environment (where calls are either automatically or manually
established), disconnect signals are sent to the modem by the EIA when the terminal is not in the normal
operating mode or the data carrier is not present at the modem.

17.3 EIA INTERFACE BASIC BLOCK DIAGRAM
The basic block diagram for the EIA Interface Option is shown in Figure 17-2. This diagram is a simplified
representation of the EIA interface circuit schematic (D-CS-5411771-0-1 ). Circuit designations and pin numbers
indicated on Figure 17-2 correlate with corresponding components on the schematic. Buffers, inverters, and
other components that do not have major operational functions are omitted from the block diagram.
The EIA interface can be divided into the following three functional areas: data path, connection protocol, and
disconnect functions.

17-4

MASTER

---------------2-•1oo~if}\,.l1--

3- - - - - - - - - - - - - - • • ORIGINATE

CLEAR
TO SEND

!OJ

OR
E2

KSTRB
DIS L

s. I.

AND
E5

TTL LEVEL
CONVERTER
E3

REQUEST
TO SEND

s.o.
BREAK KEY
DETECTOR
L--.
CIRCUIT
QB a Q9

230MS
PULSE

SWITCH
E5

RECEIVED
DATA

.---

EIA LEVEL
CONVERTER
E4

XMIT

I - - DATA

230MS
PULSE

NOT READY
PULSE
GENERATOR
Q4

W2·

DATA
TERM
READY

r--1

PULSE
GENERATOR
Q3

'------!

5SEC
TIMER
Q7

70 MS PULSE

DISABLE

15 SEC
TIMER
QG

~ DISCONNECT
OR
4

DATA
~ ElA
TERM READY

LEVEL
CONVERTER
E3

~ CARRIER
DETECT

LEVEL
CONVERTER
E3

~ RING
INDICATOR
CP-2342

Figure 17-2

EIA Interface Block Diagram

17-5

17.3.1 Data Path
Received EIA-level data is converted to TTL levels by E3 and then applied to the terminal as the SI signal. TTL
output data (SO) from the terminal is generated at the keyboard and converted to EIA levels by E4. Two
additional circuits can produce an effect on this output data signal: Break Key Detector Circuit and Not Ready
Pulse Generator.
The Break Key Detector Circuit formed by Q8 and Q9 monitors the data out of the terminal and when a high
level signal from the keyboard BREAK key appears, this circuit truncates this signal after 233 ms. This action
ensures that if the BREAK key is depressed f.qr a relatively long period of time (approximately 1 second) the
receiving unit does not interpret this time break as a terminal disconnect signal and terminate the communications operation. This feature is desirable in environments where the Carrier Detect signal from the modem is
not used to initiate terminal disconnects. The Break Key Detector Circuit generates a 233-ms time break pulse
that is inserted on the Xmit Data line which overrides the actual pulse width caused by the BREAK key.
The other circuit that effects the Xmit Data line is the Not Ready Pulse Generator circuit formed by Q4. This
circuit monitors the operational status of the terminal (DATA TERM READY) and, ifthe terminal changes to a
not ready status, generates a 233-ms-wide pulse on the Xmit Data line. Anyone of the following four terminal
actions can cause this pulse:
1.
2.
3.
4.

Paper out
Line/Local switch in LOC
Terminal power OFF
Power-up sequence not completed.
NOTE
Terminal actions that cause DATA TERM READY pulses of less than 233 ms wide are not extended but pulses
wider than 233 ms are truncated to 233 ms.

When jumper W2 is installed, this pulse is applied on the Xmit Data line and is interpreted by the receiving unit
as a Break command.
17.3.2 Connection Protocol
Five signals are used in conjunction with the Selective.Addressing Option (LAXX-KW) and interfacing modems
to establish data connections in typical multipoint networks. These signals are:
1.
-2.
3.
4.
5.

Data Term Ready (from terminal)
Request to Send (to modem)
Clear to Send (from modem)
KSTRB DIS L (bidirectional, to and from EIA interface)
Originate (to modem)

A terminal with EIA and Selective Addressing Options installed becomes the master terminal in the network by
typing CTRL D. This causes two actions on the Selective Addressing circuit board. First the Master signal is sent
through the EIA to the modem as the Originate signal. This signal causes the modem to switch to a transmitting
carrier (frequency) so that the master terminal can transmit on the frequency that all the other terminals (slaves)

17-6

are receiving on. The Selective Addressing Option also removes the 0 level signal on the trilevel line (KSTRB DIS
Lat ES pin 2 of the EIA switches to the M level). If the terminal is ready for normal operation (power ON, paper
installed, on-line, and wake-up completed), the Data Term Ready signal and the M level signal at ES generate the
Request to Send signal. After the modem has switched to the transmitting frequency and established the channel,
it sends the Clear to Send signal back to the EIA. The Clear to Send signal through OR E2 forces the KSTRB
DIS L signal to the H level and the terminal front panel DEVICE SELECT light illuminates. The terminal has
established a proper connection and can transmit data out the SO line.
The other input signal at E2 (pin 9) is the DATA TERM READY from the DECwriter terminal. This signal is
used to monitor the local/line condition of the terminal. When in the local mode of operation and the EIA
interface is not installed, the KSTRB DIS L signal connecting the Answerback and Selective Addressing Options
is normally at the H level. This allows the answerback message to print locally and the Selective Addressing
Option to control the front panel DEVICE SELECT and SELECT AVAIL lights. To prevent the installation of
the EIA from inhibiting these functions, the local indication on the DATA TERM READY line is applied
through OR gate E9 to hold the KSTRB DIS L signal at an H level even though the CLEAR TO SEND signal
may not present from the modem. (In local mode, status of modem is not considered for normal operation.)
At the end of the transmission, typing CTRL D removes the Originate signal (terminal no longer is the master),
causing the modem to switch the carriers back to the answer mode.
17.3.3 Disconnect Functions
When the EIA interface is used in a switched network environment the interconnect signals typically used are:
1.
2.
3.
4.

Data Term Ready (from terminal)
EIA Data Term Ready (to modem)
Carrier Detect (from modem)
Ring Indicator (from modem)

The EIA Data Term Ready signal is the primary interface between the EIA and modem. It functions as both the
terminal status monitor and as the Disconnect signal. With Jumper Wl installed, EIA Data Term Ready signal
reflects the operational condition of the terminal (paper out, local mode, etc.) and remains low as long as the
improper terminal condition occurs. The disconnect action of the EIA Data Term Ready signal is indicated by a
70-ms pulse out of E2. This disconnect occurs when the carrier of the telephone connected to the modem is
removed. In automatic answer applications (where calls are automatically answered), the Ring Indicator signal
from the modem starts the lS-second timer circuit Q6. If at the end of lS seconds, the Carrier Detect signal is not
asserted high (indicating that a carrier is present at the modem), Pulse Generator Q3 applies a 70-ms disconnect
pulse on the EIA Data Ready line. During normal operation (after communications have been established) ifthe
carrier is removed or disconnected, the S-second timer Q7 starts. At the completion of its count, a 70-ms disconnect pulse is applied on the EIA Data Term Ready line. This automatic disconnect feature prevents
incorrectly terminated calls from tying up the communications line.
17.4 TROUBLESHOOTING
The troubleshooting chart in Table 17-3 lists the common trouble symptoms that could be observed during
installation checkout or normal operation.
17.5 LAXX-LG PRINT SET
The figures at the end of this chapter are the LAXX-LG print set.

17-7

Table 17-2
Standard EIA Modem - Terminal Interface Connections

Name

Function

EIA Circuit
Designation

I
2
3

FG
TD
RD
RTS
SG
DCD
None
DTR
RI

Frame Ground
Transmitted Data
Received Data
Request To Send
Signal Ground
Data Carrier Detect
Unassigned
Data Terminal Rea<!Y_
Ring Indicator

AA
BA
BB
CA
AB
CF
None
CD
CE

7
8
11
20
22
Notes:

1. Positive voltage equals binary zero, space, on
2. Negative voltage equals binary one, mark, off

17-8

Data Terminal
Equipment

Sent To
Data Communications
Equipment

x
x

Table 17-3
Troubleshooting for EIA Interface Option (LAXX-LG)
Symptom

Problem Area

Probable Cause

Action

Reference

1. No operation of terminal
on-line

Connections

EIA connector in wrong
location

Plug EIA connector into J4 of
Logic Board

2. Not receiving incoming
data

Level conversion

EIA to TTL converter defective

Replace E3

D-CS-5411771-0-1

3. Not transmitting typed
data

Level conversion

TTL to EIA converter defective

Replace E4

D-CS-5411771-0-1

4. With no other options
installed not able to
type from keyboard
when on-line

Keystrobe disable

Keyboard inhibited by KSTRB
DIS L signal from EIA

Check E2 pin 10 for Clear to
Send signal from modem

D-CS-5411771-0-1

THIS DllAWIMG lllMD SH:CIFICfllTIOMI. llEftllM, Ml Tttl.
~ON:ltn

llOT H

Il ~

0-0-ILLllt>~ OJ 2

Of' OIGITM. l!QUlflllEMT tOltl"OlllllTIDM MtD SllflLL

Mll"lllOGUCR Dfll CDl'IEO Oft UUD I" •NOLI! Oii JM

NRT M Tiii MSll FOR THE lflllrlUMCTillll Dll SflU OF
lTHI HTMOUT IRITTl!M l"P•ISSIOH.
Gllf'YlllGHT •

Ig 7 5

COMPONENT SIDE VIEW

DlGITM. EQUIPll!tll COllPOll:flTIDH

t--

c
8.00
F.B.S.

I~
• rr-

J---1

~~~~~~~~~~~!

r~---2.44 F.B.8.----~1

>
Wu
a:

NOTES:

ENG.::'§::J

1~; TITLE

~=g~:e~~~- lR:"·'!!LAXX-LG EIA INTF

SCALE 2: 1
s1zEfcoDEf
NUMBER
SHT. I
OF I
D jUA j5411771-0-0
ETCH REV D jF IRST USED ON LAXX-LG

17-10

TREV

MS#3-0l8_9

"THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE
PROPERTY OF DIGITAL EQUIPMENT CORPORATION ANO
SHALL NOT BE REPRODUCED OR COPIED OR USED IN WHOLE
OR IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE

rc~~~~ii'@ftj~5~R~TJ1~1~i~~:~~~~ CORPORATION"

MASTER. L

+sv
RI

47ep

~
H
> - - + - - - - - - - - - - - r l l R E . Q U E S T iO SEND

KSTRB DIS L

( PZ-"')

+ sv

+5V

~M~

R24

4.7K

+sv

+sv
R5
4.1 K

W2.

+ 5V

8- - - - - - - v i D )(MIT DATA
>-=

1$1-1
--"·"'~--I
H

-<ili

v i

SEE NOTE 3

L - __ J1i
( P\·'3

TIL "-.LL

<>-'lo------+-------l-=<'3.y 7~f~ >--11- - - - - - - - - - - v i (DATA. rn) (P2/2.)

+1'2..V

R9
24K

RI\

+<:>V

+12-V
47.JL

1-J
I 1\14¢¢4
+12.V~r;---

RZ.2

l; =233_,,_ SEC

(P2.-1)

+sv
CA~R1t:R

\Jn
(Pl- 8)

RI¢
241<
DI
IN148A
3.9\/

R25
47

+ Cl
100.u..I'

CITHRUC4

L T·Qll.M.f~
GND 0 - - ' - - - - - ElA 5IGNALGND
(PZ.-1)
(Pl-1)

+sv

Cl\

+5V

PROTE.<::TIVE. GI.JD

Rll

r-\211.k.f

(Pl- I J

4.f K

~(j)

80
~o

11 -------<..<lF EIA DATA TERM RDY
/-'-'-

R29

(Pl-'U;z\)

470

"t~ 5 SEC

I
0

+SV 0~-~-----~--- + sv

(P2.-5)

\_ CIS

1' (o.8Mf
s

Rl5
4151.

+1'1.V

D<o
<o. e.u.f
T
tN-4¢¢4
-::-12.Ve---Kf-------,--- -\IV

Rl
4 7 ft

+llV

CT C\4

(P2.-lo)

4.1 K

1:, 7417
El

RltJG I'lDlCATOR
( Pl-22)

(Pl-2.)

( PZ.-4)

Dl\1.1\

010
G64

TTL S.0.L

R~C.V 1 D

(DATA o u 1 ) 0 p - - - - - - - - - - - - - - - - - - - - - - . - - - - - - - - - - - - - - - - - - - ' - - I

E
CLEAR TOSrnD<L>--------'i
( Pl-":;)

R:,
7.4K

C\3

.1TL DATA TERM READY H (})----f------J-_ _ _ _ _ _+~1~'5.J.(~
( P2- e I
'WI

+SV

(SPLIT LUGSJ

(Pl-4)

R2
390

Q7
<>S31

Rl4

2.4 K
R2.<i,
lr/>K

NOTES:

...

I. ~~kl~N~~~~ ~.[ '(Pl) IS THE:,
C.. SPLH LUGS L·U (Pz.) IS T\-\E.
DATA TERMlf-l"-L U.lTERFAC.E...

3. SWITCH SI ONLY INSTALLED
IN FIELD USE" AS REQUIRED
BY SPECIFIC CUSTOMER
APPLICATIONS.

LAXX-LG
EIA INTERFACE
SIZE CODE

t'":':C~~~-r-~.,
SHEET
OEC FORM NO.

l)RO 102·0

NUMBER

D CS 5411771-0-1
DIST.

2
17-11

REV.

CHAPTER 18
20 mA INTERFACE CABLE OPTION KITS
(LAXX-LK DEC 10 AND LAXX-LH STANDARD)

18.1 20 mA INTERFACE CABLE INTRODUCTION
The only difference between these two cable options is the termination connectors at the cable ends.
The LAXX-LK Option has a Mate-N-Lok connector at one end and a 283B connector (for interfacing to a DEC
I 0) at the other end as shown in Figure 18-1.

From

2838
Connector
Pin No.

Wire
Color

Description

Mate-N-Lok
Connector
Pin No.

Pl-R
Pl-Y
Pl-GN
Pl-BK

Red
White
Green
Black

Negative side of Transmit Line
Negative side of Receive Line
Positive side of Transmit Line
Positive side of Receive Line

P2-2
P2-3
P2-5
P2-7

TO
p2

_..LOGIC
BOARD
J3

CP-2389

Figure 18-1

20 mA Interface Cable Option (LAXX-LK) Pin Assignments

18-1

The LAXX-LH Option has a Mate-N-Lok connector at each cable end. Refer to Figure 18-2.

From

Logic Board
J3
Pin No.

Wire
Color

Description

Computer
Pin No.

i>l-2
Pl-3
Pl-5
Pl-7

Black
Red
White
Green

Negative side of Transmit Line
Negative side of Receive Line
Positive side of Transmit Line
Positive side of Receive Line

P2-3
P2-2
P2-7
P2-5

PIN# 1

TO
LOGIC
BOARD-J3

TO
--COMPUTER

PIN# 1
CP-2390

Figure 18-2

20 mA Interface Cable Option (LAXX-LH) Pin Assignments

18-2

CHAPTER 19
ACOUSTIC COUPLER OPTION KIT (LAXX-LM)

19.1 INTRODUCTION TO THE ACOUSTIC COUPLER
The Acoustic Coupler provides an interface between telephone data and the DECwriter. The coupler is a bidirectional device that converts incoming data into serial pulses acceptable to the terminal and converts data transmitted by the terminal into a data format compatible with standard phone requirements. The Acoustic Coupler
assembly is incorporated in a special cover that replaces the standard cover supplied with each terminal. The
coupler consists of a Muff assembly that accepts the telephone h~ndset and a circuit board that contains the
transmit and receive circuits. The coupler interfaces with the Logic Board through J4, the EIA connector.
NOTE
The Acoustic Coupler Option (LAXX-LM) is compatible
with LA35 and LA36 terminals with either the M7722,
M7723, or M7728 Logic Boards installed. The coupler
does not require that the Expander Option Mounting Kit
be installed for proper operation.
19.2 TYPICAL ACOUSTIC COUPLER OPERATION
The telephone system is a single wire system; therefore, to simultaneously transmit and receive over this wire, two
distinct frequencies are used by Acoustic Couplers. By utilizing receivers with high selectivity, both frequencies
can be present on the wire at the same time without noticeable interference.

19-1

Figure 19-1 shows a typical telephone data communications configuration between a DECwriter terminal and a
computer installation. The Acoustic Coupler Option is always configured in the originate mode of operation
(transmitting on l kHz and receiving on 2 kHz). The computer, or any other device or terminal communicating
with the Acoustic Coupler Option, therefore, must be configured in the answer mode (transmitting on 2 kHz and ·
receiving on 1 kHz).

REMOTE COMPUTER
ANSWER MODE
TRAN SM IT FREOUENC IES "'2 KHz
RECEIVE FREQUENCIES "' 1 KHz

ACUSTIC
COUPLER
OPTION - LAXX-LM
.....-........__....._..__,
DECWRITER TERMINAL
ORIGINATE MODE
TRANSMIT FREQUENCIES"' 1KHz
RECEIVE FREQUENCIES "' 2KHz

CP-2379

Figure 19-1

Typical Telephone Communication Configuration

Frequency Shift Keying (FSK) is used to modulate the transmitting frequencies as follows:
Originate Mode
1070 ± 10 Hz = High = Space = Binary Zero
1280 ± 10 Hz= Low= Mark= Binary One
Answer Mode
2025 ± 10 Hz = High = Space = Binary Zero
2225 ± 10 Hz = Low = Mark = Binary One
19.3 ACOUSTIC COUPLER FUNCTIONAL BLOCK DIAGRAM
The functional block diagram for the Acoustic Coupler is shown in Figure 19-2. Output data from the keyboard
is converted to serial out (SO) by the UART and applied to the Transmit Section of the coupler. The Transmit
Section applies the 1 kHz carrier and FSK information to the speaker in the Muff assembly. The telephone
handset has a microphope in the mouthpiece which receives the data from the Muffs speaker. This data is
transmitted out over the telephone line to the other device.
Received data is coupled through the speaker in the earpiece of the telephone to the microphone in the Muff. The
Receiver Section of the coupler converts the received 2 kHz signal into serial in (SI) pulses and applies them to
the UART on the Logic Board. The UART handles the received data in a normal manner and applies it to any
installed options.
\

19-2

19.4

ACOUSTIC COUPLER BASIC BLOCK DIAGRAM

The basic block diagram for the Acoustic Coupler Option is shown in Figures 19-3 and 19-4. These diagrams are
simplified representations of the Acoustic Coupler circuit schematic (D-AD- 7012356-0-0). Circuit designations
and pin numbers indicated on these figures correlate with corresponding components on the schematic. Buffers,
inverters, and other components that do not have major operational functions are omitted from the block
diagrams.
The Acoustic Coupler can be divided into two functional areas:
I.
2.

Transmit Section
Receive Section
ACOUSTIC
COUPLER OPTION
LAXX-LM

ID'EcWRiTERITRMiNAL

-------,

LOGIC BOARD

II SECTION
RECEIVER
I
MUFF I

TRI
STATE
BUFFER t--""7<:'.--V

UART

1----1
I

TO
CHAR
BUFFER

I
IJ3

TO/FROM
OPTIONS

TELEPHONE
HANDSET

KEY
BOARD

I
I
I
I
I
I
I
I
I
I
_J

CP-2380

Figure 19-2

Acoustic Coupler Functional Block Diagram

W5
J3

J1
SERIAL OUTPUT
PULSES FROM
LOGIC BOARD

TRANS
FREQ.
SELECTOR

1 kHz
TRANSMITTER 1--'l/l/v~'--I
R63
ES

233 fLSEC
DATA TERMINAL
READY FROM
LOGIC BOARD

W13

BREAK
PULSE
GEN

E7,E9

L_J TRANSMITTER
DISABLE
FROM
RECEIVER
SECTION

ALLOW

1070 Hz
OR

1270 Hz
TO SPEAKER
IN
MUFF ASSY

SWITCH

CP- 2381

Figure 19-3

Acoustic Coupler Transmit Section Basic Block Diagram

19-3

JI
2070 Hz
DISCRIMI·
NATOR
E4

2070 Hz
OR
2270 Hz
FROM
MICROPHONE
IN MUFF

-"""
\0
I

PRE
AMP

2KHz
BAND
PASS
FILTER

AMPLI·
TUDE
LIMITER
E3

02
~--__,

COM PARATOR

SHAPER

NANO

SERIAL
IN TO
UART

+sv

2270 Hz
DISCRIMINATOR
E4

Wl2

04
CARRIER
DETECT
CIRCUIT
E5,Q1

TIMER

C20

R~~

TRANSMITTER

i - - - - - ~~~~~1lO
SECTION

CARRIER
DETECT

CP-2382

Figure 19-4 Acoustic Coupler Receive Section Basic Block Diagram

19.5 TRANSMIT SECTION
The basic block diagram for the Transmit Section of the Acoustic Coupler is shown in Figure 19-3. Keyboard
ASCII characters are applied through Inverter E9 (W5 is normally removed), then through OR gate E7 to the
Transmitter Frequency Selector Q3. A binary zero in the ASCII code selects the 1070 Hz output frequency and a
binary one selects the 1270 Hz frequency. Resistor R63 permits adjustment of the output level that is applied to
the speaker in the Muff assembly. This adjustment matches the circuit board to the Muff.
The Data Terminal Ready (DTR) signal from the Logic Board when the terminal goes not ready only (which is
available from the M7728 board, not from the M7722 or M7723 boards) is coupled through W13 to enable the
Break Pulse Generator E7, E9. This pulse generator produces a negative-going, 233 ms wide pulse. It extends
DTR pulses shorter than 233 ms and truncates DTR pulses that are longer than 233 ms.
The transmitter is not permitted to output the 1 kHz carrier signal until the Receiver Section of the Acoustic
Coupler has detected a valid carrier on the incoming receiver line. This action ensures that a proper communications channel has been established.

19.6 RECEIVE SECTION
The basic block diagram for the Receive Section is shown in Figure 19-4. Incoming data from the microphone in
the Muff is applied through J2 to the Preamplifier El. The Band. Pass Filter, consisting of E2, E3, and the
associated tuned circuits, passes only 2 kHz signals and rejects all others. Limiter E3 removes all noise-induced
amplitude modulation on the 2 kHz signal. Each section ofE4 forms a discriminator that detects the presence of
2025 Hz and 2225 Hz. The output of each discriminator is a wave whose amplitude is proportional to whether the
incoming signal is a one or zero. The discriminator outputs are applied through positive rectifier Dl and negative
rectifier 02 then compared at E6. As the amplitude out of one section of E4 becomes greater than the other
section, the signal produced at E6 pin 7 approximates a square wave. This signal is passed through Shaper E6 to
make the square wave more precise, then applied to NANO gate E7 which acts like a diode and only passes onehalf of the square wave, producing a series of pulses at pin 10 of NANO E7. The other input to E7 (pin 9) is
connected to the carrier detect circuitry of the Receiver Section. When a valid carrier is present for the required
period of time, pin 9 becomes high and allows the series of data pulses to pass through E7 to Q2. The output of
Q2 is applied through Jl to the receiver half of the UART on the Logic Board.
The carrier detect circuit (composed of E5 and Ql) also monitors the output of the two E4 discriminators. This
detector circuit does not care whether the discriminator output is positive or negative, just that there is an output.
This output is rectified by 03, 04 and applied to E5 pin 6. A negative output signal is present at E5 pin 1 when a
valid carrier is detected. This negative voltage causes the carrier detect light on the cover assembly to illuminate.
The negative voltage becomes a high level through Inverter E9 and enables the receiver at E7. This high level,
which enables the receiver, is also applied through a timer circuit that is composed of E9, R60, and C20. This
circuit controls whether the transmitter in the acoustical coupler is able to transmit.
When the output of E9 pin 6 is at a high level, the transmitter is enabled because Q4 is conducting. When E9 pin 6
is low Q4 conducts removing+ 12 V from E8 pin 5 and the transmitter is disabled. The carrier monitoring circuits
are the controlling circuits for both the Transmit and Receive Sections of the coupler. After detecting a valid
carrier for approximately 5 seconds, the Receiver Section is enabled and incoming data is passed onto the
UART. If, while receiving data, the carrier is lost, the Receive Section is disabled 0.5 second after the carrier
disconnects. The Transmit Section of the coupler is enabled after the 5 seconds that valid carrier is detected
andremains enabled for about 4 seconds after the carrier is lost during transmission.
This non-symmetrical timing for connecting and disconnecting ensures that the coupler is properly configured
before data is either transmitted or received. It also permits a fast disconnect for the Receiver Section so that
spurious noise cannot enter into the receiver if the carrier is lost. The slower disconnect on the Transmit Section
(if the received carrier is lost) permits momentary lost of input carrier without a break in the output data.

19-5

19.7 TROUBLESHOOTING,
The troubleshooting chart in Table 19-1 lists the common trouble symptoms that could be observed during
installation checkout or normal operation.
19.8 LAXX-LM PRINT SET
The figures at th_e end of this chapter are the LAXX-LM p.rint set.

19-6

Table 19-1
Troubleshooting for Acoustic Coupler Option (LAXX-LM)
Symptom

Problem Area

1. After installation, does not
receive or transmit

Set up configuration

2. Random errors appear in
printing or transmission

Signal level or noise
interference

Probable Cause

Action

Wrong baud rate

Match baud rates between
sending and receiving units

Terminal not on-line

Place terminal on-line

Incorrect cabling

Connect Acoustic Coupler
Cable to 14 on the Logic
Board

Telephone not inserted in
Muff correctly

Cord end of handset inserted
in Muff with "dot" and/or
word "CORD" next to it

No carrier being sent to
Acoustic Coupler

Listen for carrier in handset

Poor telephone connection

Hang up and try connection
again

Mechanical noise

Check for printer cover rubbing on tractor shaft

Loose equipment

Check tightness of Paper
Advance knob

High ambient noise level

Refer to Acoustic Coupler
Specification for acceptable
sound levels

Reference

....

"THIS ORA.WING AND SPECIFIC\TIONS. HEREIN, ARE THE

PROPERTY OF DIGITAL EQUIPMENT CORPORATION AND
SHALL NOT IE REPRODUCED OR COPlm OR USED IN WHOLE
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CHAPTER 20
APL OPTION KIT (LAXX-PK)

20.1 APL INTRODUCTION
The APL Option is a distinct character set, which is one in a series of optional character sets that can be installed
in a DECwriter. The APL Option provides a DECwriter with the ability to produce the 95 printing or spacing
characters in the APL set. This feature adds a complete character set to the existing character set in a standard
terminal. The two sets are: the standard ASCII set and the APL set.
The APL Option contains special characters and symbols not found in a standard set. In addition, the APL also
contains the standard numerals (0 through 9) and a complete alphabet in small capital letters. (Print is 5 dots high
and 7 dots wide rather than 7 X 7 dots as in a standard sized capital letter.)
Normal timing, print head configuration, and mechanical operation of the DECwriter is uneffected by the
installation of an Optional Character Set (OCS) such as the APL. The option simply substitutes the incoming
ASCII character with a print head pattern that causes a different character or symbol to print.
There are two methods of changing from one character set to the other: by local control using front panel
switches or by remote control utilizing codes in the incoming data. Local character set selection always takes
precedence and overrides all selection codes on the incoming data.
The optional character set circuit board has provisions for installing either of two character memory configurations. One configuration uses two ROMs, while the other uses three PROMs. Generally the ROMs are
more costly than the PRO Ms (because the storage of the character pattern is actually a physical characteristic of
the chip) and only become cost effective when many sets of the same character style are to be programmed.
PRO Ms are less expensive (because they have a programmable memory) and are usually only used when a small
number of terminals are having a distinctive character set installed. This is because the programming cost of each
PROM is relatively high and is not justifiable for large numbers of PROMs.
The APL Option (LAXX-PK) is always installed in the ROM configuration.

20-1

20.2 APL FUNCTIONAL BLOCK DIAGRAM
Figure 20-1 shows the functional block diagram of the Optional Character Set (specifically, the APL Option) in a
typical installation. The major difference between this installation and installations for the other DECwriter
options is the point at which the Optional Character Set samples the data on the M7728 Logic Board. Most other
options utilize a bidirectional line that monitors the incoming character data on the lines between the UART and
the Character Buffer. these options also utilize the Data Available signal as a strobe to transfer either incoming
characters out of the UART or option-generated characters into the Character Buffer. Figure 20-1 shows the
Optional Character Set monitoring the data after the Character Buffer. Therefore, all other options have performed their functions (inserting messages or codes for carriage returns, spacing, or line feeds) before the data is
available to the OCS option. This incoming data, whether serial in (SI) from an external source or local keyboard
data, is cabled from the Logic Board to the Expander Option Mounting Board and is present at the input of the
Optional Character Set at location F. This data also contains the column count codes from the Column
Increment Counter on the Logic Board. These three lines represent 8 of the 10 possible positions of the print head
in each character cell and are used by the option to synchronize the 7-column dot output for each character with
the print head's actual physical position. The APL ROM (or OCS PROM) converts the 7-bit ASC!I data into the
print head dot pattern for APL characters. The ASCII-to-APL conversion is shown in Figure 20-2.
The output of the ROMs is applied to Line Drivers where the Remote Control Circuit samples the lines and
. decodes remote commands that switch from one character set to the other. The code SO (017s) switches to APL
and the code SI (016s) switches to standard ASCII.
The Local Control Circuit monitors the positions of the front panel CHAR SET LOCK switch and the ALT
CHAR SET switch. These switches provide operator control over the selection of which character set will print
and override all set selection codes on the incoming data line. When the CHAR SET LOCK switch is in the up
position, the incoming data can control set selection irrespective of the position of the ALT CHAR SET switch.
Depressing the CHAR SET LOCK switch establishes local control and locks the option into the set established
by the position of the ALT CHAR SET switch. If the ALT CHAR SET switch is up, the standard ASCII set is
selected; when down, the APL (or OCS) set is selected.
The Character Set Control Logic determines which set the terminal will print and, ifthe APL is selected, disables
the Line Drivers on the M7728 Logic Board and enables the Line Drivers on the option. Conversely, if the
standard ASCII set is selected, the option Line Drivers are disabled and the Logic Board Line Drivers are
enabled.
The character set selected (whether by local or remote control) is indicated by the illumination of either the front
panel STD or ALT lights.
20.3 APL BASIC BLOCK DIAGRAM
The basic block diagram for the Optional Character Set (APL Option) is shown in Figure 20-3. This diagram is a
simplified representation of the optional character set circuit schematic (D-CS-M7732-0-l). Circuit designtions
and pin numbers indicated on Figure 20-3 correlate with corresponding components on the schematic. Buffers,
inverters, and other components that do not have major operational functions are omitted from the block
diagram. The discussion of this option is divided into two major sections: character storage and character set
selection.
20.4 CHARACTER STORAGE
One of two character storage memory configurations can be installed on the OCS board. In the APL Option,
ROMs in sockets ElO and Ell store the dot pattern for each character in the APL set. For any other set, three
PRO Ms can be programmed for a unique set and installed in sockets E4, E7, and El2. The installation of E15 is
also required when using PROMs. Only one configuration is installed at a time.

20-2

~~~~~~~--------------------

-----,
I~---------------------------M7728 LOGIC BOARD

I
I

I
S.I.

I
I

I
I
I

'EXPANDER OPTION -

- __ J
- - ---1

MOUNTING BOARD

I
I

CONTROL

L _________ _

TO
POWER
BOARD
PRINT
HEAD
DRIVERS

CHAR
ROM 1-------•/

OCS BOARD
(APL OPTION l
REMOTE
CONTROL

I
I
I
I

~RONTPANEL -

I I

PR1

"SEC

I
I
I
CONTROL

CHAR SET
LOCK

ALT
CHAR
SET

--'---

-'-

I
I
I

CHAR
SET
CONTROL I - I - + - - - - - - - '

LOCAL
CONTROL1--.i---------------~

L_ L-------------------..J

_J
CP-2383

Figure 20-1

APL Character Set Functional Block Diagram

~
~·

ETX

I
I

1
0

1
1

1
0
0

....

DLE
DCI

SP .

()

)

,.,A:,.

DC2

.l.

(

-~
....

)

f.;

::r
v
/\

...

Fo:

I..

·I-

·-·

7
8

I:;'

(.)

t.>

::>

~-~

·1

:i:

I
I

Alternate (APL) Character Set

0
0

c:·

,.)

(

•

,.J
I<

{

•··

[]

I-·

I..•

··i

··~

}
1~

DEL

•

.?..

(;>

-·

(:J

1
0

1
Figures and
Numbers

Upper Case

DLE
DCI

(!1

:I.

DC2

,.,
.::.

"°'
B

:JI'

1::·

&
;

I
I

.. so

DC3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS

Standard (ASCII) Character Set

Control Codes

1·l

"y"

·--

NUL
SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR

1'.

0
0

Lower Case

'!>

:I.

1•·

1
1
0

Upper Case

EOT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR

Figµres and
Numbers

DC3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS

~··

0
1
0

Control Codes

NUL
SOH
STX

0
0

1
0

1
1

Lower Case

1:;;

("'

,:)

("'

~:;

,,.I

<-:~

1..1

·7
I

f'.,

~:.~

(

~-~

)

~:t

*
+

,.)

2'.

:i.
,.i

{

I...

....

.. ..

::r

Irr

}

..!)

,.,

-·

DEL

CP-2384

Figure 20-2 Bit Assignments for ASCII and APL Character Sets
20-4

LOC F
CONTROL

FRONTPANU

CODES

CHARACTER DOT PATTERN

ALT
CHAR
SET

PR1

SEC

COLUMN POSITION

a ASCII 1 -7

APL
ROM
E10
E11

r- COLUMN
POSITION

ASCII
1-B
COLUMN
POSITION

COLUMN
HOLDING
REGISTER
E15

E2,E3
AND
E1

ocs

ASCII

TOI
N

FROM
LOGIC
BOARD

1-5

ASCH
BIT B

PROMS
E4,
E7,E12

6W6

-- -

ENABLE
SI/SO
DECODER

13
9

3 PRIMARY
ENABLE

3
4

AND

ocs

CONTROL B
EB

E9
NON
PRINTABLE

CHARACTER
TEST

B
ACSII
BIT B

OR
E9

AND
E13
SELECT ALT

CHARACTER SET

DISABLE LINE DRIVERS ON LOGIC BOARD

C P-2385

Figure 20-3

APL Option Basic Block Diagram

In the APL Option, 7-bit ASCII character codes and 3-bit column position data is applied to the APL ROMs
EIO, Ell. The dot pattern for each ASCII character is substituted with the dot pattern for the APL character by
the ROMs. (ElO stores upper and lower case letters and Ell stores the figures and numbers.) Figure 20-4 shows
the print head dot pattern for the ASCII character "H" and its corresponding APL symbol delta(~).
Below each character are the ROM data words that are required to print each character. The information in rows
1-7 define a row of the character and the information in row 8 determines whether the character is printable or
non-printable (such as a control character). As the print head moves across the 10 column increments that make
up each character, the Column Increment Counter on the Logic Board outputs positioning data for each of the
seven possible printing locations. Because columns 8 and 9 are always blank, only three binary-coded lines are
required for proper spacing between characters to define the remaining eight column increments. The three
column position lines plus the ASCII lines are applied either directly to the RO Ms or through storage Latch El5
to the three PRO Ms, if they are used. The eight possible codes are used by the RO Ms as addresses to access the
proper dot pattern for the coinciding head position. For example: if an ASCII "H" is typed and the APL Option
is installed, the ASCII "H" code accesses the "~" location in the APL ROM and the head position addresses the
column increments starting with column 0 and continuing to column 7. At column 2 the dot pattern code
accessed is 000 000 which causes the solenoids in the print head to produce the dot display as shown in column 2.
After the head reachl?s column 10 (which is actually column 0 of the next character), another ASCII character is
ready to be converted to APL and the Column Increment Counter is back at zero, ready to start addressing the
increments in the new character. Data stored in the eight row of each character determines whether the character
is a printable character (i.e., any character or command that causes the print head to move). All non-printable
control commands are detected in the character ROMs on the Logic Board. Character set switching commands
pertaining to the option (SO or SI) are also detected by these ROMs and the dot information is applied to the
option on the bidirectional SEL lines that are connected to the option at the output of the Line Drivers E2, E3.
Jumpers W3, W4, and W5 (which are normally installed) can be used to selectively override the character substitution from either the ROMs or the PROMs. Normally, with the OCS set selected, an ASCII character is
automaticaly substituted with a character from the optional storage location. But by utilizing these jumpers,
selective parts of the optional character storage can be removed from this automatic substitution. When a certain
portion of the OCS set is prevented from being accessed, the characters are then taken from the standard character set stored in the ROMs on the Logic Board.
Table 20-1 lists various jumper configurations for both ROM and PROM configurations. As shown by this table,
with Jumper W3 installed and W4 and W5 cut out, the selection of either the upper or lower case characters
stored in the option's RO Ms or PROMs is prevented. This means that even if the OCS set is selected, the print
head pattern for these upper and lower case characters are always taken from the standard character set and only
the figures and numbers of the OCS set will print.
Even though Jumpers W3, W4, or W5 can be cut and eliminate part of the OCS from being selected, when the
OCS is selected the front panel ALT CHARACTER SET light still illuminates as if no jumper were cut.
20.5 CHARACTER SET SELECTION
The selection of either of the character sets installed in a DECwriter can be controlled locally or remotely. Local
switching is controlled by the positions of the.front panel CHAR SET LOCK and ALT CHAR SET switches.
The output of these switches connects to the set and reset pins of Primary Enable flip-flop E8. Remote switching
control is connected to the clock and data pins of E8. The set and reset signals take control over the signals on the
clock and data input pins of E8. When the CHAR SET LOCK switch is depressed and the ALT CHAR SET
switch is up, E8 is set by the low signal on pin 4. This action places a high level on pin 12 of the OCS Control flipflop E8. The OP CLK signal on pin 11 of E8 clocks this high out on pin 9 of E8. As the high level on pin 9 is
applied through E13 to illuminate the front panel STD CHARACTER SET light, a low level from pin 8 is
applied to pin 9 of AND gate El3. This low level produces a high on pin 10 of E13 which holds the Line Drivers
(E2 and E3) on the OCS board disabled and enables the Line Drivers on the Logic Board to pass the dot pattern
of the standard character set to the print head drivers.

20-6

ASC11 CHARACTER

3
4

5
6
7
0

APL SYMBOL

"H"

1'811

PRINT PATTERN
.COLUMNS

PRINT PATTERN

•
•
•
•
•
•
• • • •
•
•
•
•
•
•
2

•

2
3
ROWS

•

7
8

9 -

•

•
•
• • • •

PAPER
POSITIONS -

• •

PRINT HEAD DIRECTION
ROM PATTERN

ROM PATTERN

0
0

0 ~o

7 -'MEMORY COLUMNS -

+PRINTABLE INDICATION+B

0
0

DIRECTION OF
COLUMN INCREMENT

ROM CODE
FOR COLUMN # 2

COUNTER SCAN

CP-2386

Figure 20-4 Typical ASCII/ APL ROM Mapping and Print Pattern

Table 20-1
OCS Jumper Configurations

Specified Secondary
Group Selected

Storage Device
Installed
RO Ms OR
PRO Ms

Figures and Numbers
Upper Case
Lower Case

ElO
Ell
Ell

IN
OUT
OUT

OUT
IN
OUT

OUT
OUT
IN

E4
E7
E12

Jumper Status

Note: Normal configuration has W3, W4, WS installed; selecting all secondary groups.

20-7

If the ALT CHAR SET switch is depressed (while the CHAR SET LOCK switch is in the down position), a reset
signal is applied to E8 pin 1 and the next pulse from the Option Clock transfers a low level through E8 onto pin 9.
In this instance the low on pin 9 extinguishes the STD CHARACTER SET while the high level on pin 8 causes
the ALT CHARACTER SET light to illuminate. This high level is also applied to pin 9 of AND gate E13 where
it combines with a high level generated by the PROM Select E5 to produce the control signal that disables the
Line Drivers on the Logic Board and enables the Line Drivers on the Option Board. Thus, the dot pattern for an
optional character is sent to the head drivers to be printed.

Figure 20-5 shows why Jumpers W3, W4, and W5 have such an overriding effect on the selection of the OCS set.
When the OCS is selected (whether by local or remote command), the input to E13 on pin 9 is always a high level.
Another high level is required on pin 8 to force the desired low level on the output of E8 that causes the OCS Line
Drivers to energize and supply the optional character. If pin 8 of E13 is held low through E9, the OCS can never
be selected because the output of El3 is always forced to a high level which enables the Line Drivers on the Logic
Board. The level on pin 8 is established by Prom Select E5 and the W3, W4, and W5 jumper configuration. The
Prom Select E5 places a low level on one of the three output lines for each printable character. The low levelpasses through one of the jumpers to OR gate E9 where it is inverted and applied as a high level to El3. Cutting
out the jumper in this signal path prevents the Prom Select output from qualifying AND gate E13. Therefore,
anytime a jumper is cut, all characters from the section of the PROM the jumper is in series with do not print
because the low out of Prom Select for the section chosen never forces El3 high.

FROM PIN 8
OF' EB

FIGURES 8 NUMBERS
FROM
PROM { UPPER CASE
SELECT - E5
LOWER CASE

ALWAYS HIGH
WHEN OCS
SELECT

ONLY ONE LINE
LOW WHEN A
PRINTING CHARACTER
SELECTED

CONTROL LINE
TO LINE
DRIVERS ON
BOTH LOGIC
AND OCS BOARD
L = ALT SET
H =STD SET

+v
CP-2387

Figure 20-5

Jumper Control over Character Set Selection

20-8

Remote character set selection, when the CHAR SET LOCK switch is up, is accomplished either by inserting
command codes in the incoming data or by utilizing the eighth level bit in each ASCII character code.
Depending upon the configuration on the Logic Board, the eighth level bit is used either as a switching command
or for parity error detection. The LAXX-PK is shipped ready for installation into a system that utilizes the eighth
bit as a parity error bit. Should parity error occur when the OCS set is selected, the option's substitution is
inhibited and the logic board controls the insertion of the parity error printout indication.
The two command codes used to .change character sets are: Shift In (SI - 017 8 ), shift into standard character set
from alternate (APL or OCS) character set and shift out (SO - 016 8) shift out of standard character set into
alternate. These two commands are decoded by the character RO Ms on the Logic Board and are sent to the OCS
board via the interconnecting bidirectional lines (sections 1, 2, 3, 6, and PRINT ABLE). These lines are decoded
by E6 and, depending on the command, a low level signal is applied to OR gate E9. If an SO command is
detected, a low is applied to the data input of E8 (pin 2) and the CHAR TEST signal from the Logic Board is
used to clock this low through to pin 12 of OCS Control flip-flop E8. The OP CLK signal clocks this low through
ES, forcing pin 9 low and pin 8 high. The option switches out of the standard character set and into the alternate
set. When the SI code is received, the action is similar; pin 2 of E8 is now high and is clocked through both flipflop sections to cause the option to switch back into the standard character set.
NOTE
If the eighth bit method of control is used, provisions for
monitoring parity errors are eliminated.
When the eight level code is used to switch character sets, Jumpers Wl and W2 must be cut and Jumpers W6 and
W7 must be installed. This action removes the effect of all other switching controls (even front panel switches
have no effect now). With W6 installed, the level of bit 8 is applied directly to the data input (pin 12) ofOCS
Control ES. This level is clocked through ES by the OP CLK signal and effects the option just like any other
switching command: bit S high, switch into standard set; bit 8 low, switch out of standard set. Note that Jumpers
W3, W4, and W5 still have the final conrol irrespective of the method of character set selection.
Figure 20-6 shows the complete operational sequence for the OCS set character selection.
20.6 TROUBLESHOOTING
The troubleshooting chart in Table 20-2 lists the common trouble symptoms that could be observed during
installation checkout or normal operation.
20.7 LAXX-PK PRINT SET
The figures at the end of this chapter are the LAXX-PK print set.

20-9

CHARACTER FROM
LOGIC BOARD

YES

STANDARD
CHARACTER
SET SELECTED
YES

YES
NO

ILLUMINATE
STD LIGHT

YES

ILLUMINATE
ALT LIGHT

YES

CHARACTER FROM
STANDARD (ASClll
SET

CHARACTER FROM
ALTERNATE
(APLISET

CP-2388

Figure 20-6 Operational Sequence for OCS Set
20-10

Table 20-2
Troubleshooting for APL Option Kit (LAXX-PK)
Symptom
1. After installation, improper operation or no
operation of terminal

Problem Area

Probable Cause

Action

Reference

Cabling

Wrong cabling connections

Check all cabling between
M7728 Logic Board, Expander Board, and Front
Panel Control Board

Option location

Option inserted in wrong
location on Expander Board

Install APL Option in location
F

ROMs

Improper insertlon

Check jnsertion of ROMs for
proper fit

2. With ALT CHAR SET and
CHAR SET LOCK switches
down and terminal printing
in APL, the PRI light
remains illuminated

Control Board

Jumper W1 not cut out

Remove WI

3. Able to switch between
character sets using
switches but not with
CNTL N or CNTL 0
codes when CHAR SET
LOCK switch is in up
position

Function Decoder
E6

Not decoding commands

Check E6 for SI at pin 7 and
SO at pin 6

D-CS-M7732-0-1,
Sheet 2

Timing between Logic
Board and Option
Board

CHAR TEST pulse not
being received

Check E14 pin 11 for the
50-ns CHAR TEST pulse

D-CS-M7732-0-1,
Sheet 2

Cabling

Cable between Expander
Board and Front Panel Control
Board defective or inserted
incorrectly

Check for continuity
between ends

4. Able to switch between
character sets using
control codes but not
using switches

Figure 9-4

7
NOTES:

EQUIPMENT CORPORATION"

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20-13

CHAPTER 21
M7728 PRINT SET

21-1

8
"TlllS DRAWING AND
PROPERTY OF DIGITAL
NOT BE REPRODUCED OR
PART AS THE BASIS FORT

ITEMS WITHOUT WRITTEN

ICATIONS, HEREIN, ARE THf
CORPORATION ANO SHALL
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NOTES:
I. CONNECTORS:
J 1 - J I POWER BOARD
.JZ - - KEYBOARD
J3--..20MA. SERIAL LINE
J 4 OPTIONAL 1.NTERFACE PORT
JS JS EXPANDER OPTION MOUNTING BOARD

DIGITAL EQUIPMENT CORPORATION"

COMPONENTS 'WITH IN OUTLINE NOT
INSERTED IN PREFERRED CONFIGURATION

SEE NOTE

RU DES NOT USED ARE:

MAX I MUM REF DES USED ARE:

91
92

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1209340·00

JI ,J1,J5

CONN 40 PIN BEiii

1209941-02

f-l-f--l_;_f-E_2_3_ _ _ _ _ _ _ _ _ _ . ·- !_C 1_4_42_ _ _ _ ·-----·--·. , 1910046 ·-·
I
I
E61
I C. 1431
: 1910091

SOCKET. IC.24 Pl~

1209456·01_
1210693

R50

RES 41 ~ 5S CC

1300202

R7 ,R33,R58,R91.R"4lD

RES 100 ~ 5% CC

1300229

l
2

AA_1_ _ _ _ _ _ _ _-+_RE_s_15_0:.·c..:~_5%_cc_ _ _ _ _ _.j__1JOD_250
_ _ _ _ _j_2_B_,
R66,R69
RES /BO )11 5S CC
1300260
29

AA9,R89

RES 220 ~ 5% CC

1300211

R30

RES 330 ~ 5% CC

1300295

E22,E33

EIB

E5.E9 Ell

-------J-'....'IC 14154

I .C

E14,E29

I .C. 14150

E6, E12, E16, E42. E64

I C. 740B

El 3, Ell E2l

l.C

E3.E36,E41

I C l4B9

1910396

-+!..'..--

El 9

1 C. 14123

'1910436

7~--

E55

._ _ _ _ _ _ _,__1_c_u_A_RT

. 1910459

E63,E6l

I C 1416·;·

I19~0~0 _

1--

E2. EB

I C 74175

1910651

Bl __

E46 ,E51

I .C

1910831

--- 82- -

E59

1.C. 8640
I C SO Cl 5, 4N26

RES 470 ~ 5S CC

1300316

1----1--t----·-

Rl·AA,R32,R35,R45,R52,R55,R61-lli5
R76,R94,R99,Rl 12,Rl IB- RIZ3 1 R+4

RES IK ~ 5S CC

1300365

2
2 __,_____
El, El
,___,

!llil,1118,R70,R71

RES IK IW 5S CC

1300368

2!0

R37-1Me,R53,R93,R96,R102;RI09,

RES /OK~ 5S CC

1300419

RIG

RES 59.0K ~ 1% IOOPl'M MF llti5D·F

131l0525

R97,R911

RES 10 ~ 5S CC

1301317

Rl3,R22,R2S

RES 180 ~ 5S CC

1301322

1301327

40
41
42

l--8--t-B'--~R.:.7=-2·.:.R7-'5~,R:.79~·R8:..:..:.1·:.R95c..::__ _ _ _+_:RE:=..S~47c.:K~l#l::_:5':....::CC:: _______ . ___
'
6
R82•R8l ," . .
RES 2K ~ 5S CC
RES 470K ~ 5S CC

1302398

R2l,R'l3

RES511l#ll'folllll'l'llMF/tl550·F

1302411

RES IODK %fl 5% CC

1302'466

1
2

I
2

RIB
R12,R14

RES 1•. lK ~ 1% lllDPl'll MF 1tl55 D·F
1302941
48
RES 1.00K ~ 1% lOll'Pll MF 1t155 D·F-- ·-IJ0.-31_1_4_ _ _ __,_48__,

R24,R211

RES 5.11K lit IS 11111'1'11MF1tl55 D·~

R19

RES 3.48K ~ 1% lllll'AI MF 1Hi5 O·F

2
I

f-_;_---t-----------+-------------+.

14190

'1910095

_ _ 73

_f.19!01_5~---- __ 11._
1910155

+;;;·-----------+-'·

LM301ANOIP

·11910282

8093

~-_BO_

·-.+2!Jl.1~~·-·-·

I 91 I 99B

23.i!!~A~ -··-- -··· :_ B5
230B3A4
BG

PROM, 1702A. PROGRAMMED PROMS
PROM, 17 02A. PROGRAMMED PROM I

11I
E53
1 -·--f---t---

------

0l_-+-'-1-E_4B____ ..
I
0
EIS

-----+RO_M.:.·:cMKc.:2:.:6.:.26:.:("'N.:.O:..:.S:.::Ec:.T:.
. ..:.A.:.S:.Cc.:l_,_J_ _-1"'2:3:011~- __ _

-------~OM.MK262l(ALPHA SET.ASCII)

·-·-·-· Bl
__
BB

23070A6

ROM MK262B(CONTROL PROGR~~ 230B~···

__ . ··-- ~~

··------~W SLOTTED BIND HD 4.40 K5/119QQ~~Q:~---··-···-f9.Q__

·-~9~
_

9_2_

>-4--+_4_,...._____

EYELET(MATE·N·LDCK MOUNT~.-~.O.Q.~ _ . ___ .~ _

FASTON TERMINAL

9001113

94_

r2--t-_2--j-----------+E_Y.:.EL_E~T-"(F.:.A.:.ST~E~N.:.M~O~U~N:.Tl~N=G~)_ _ _ +9:.:0=0.:.90:.:0.,o_____ . ~
(
7 Wl·W5,W18,W20
WIRE, INSULATED JUMPER
90a.!185
91

C95

CAP ./ Uf" 1oov cO)'o

RIO/

R,E5 aJo

C~4

CAP 39UF" IOV 10,% S.TA'lf
10000~"'
WIRE, INSULATED JUMPS" 30All/G 9105740

I
A/R. A/I>,

1/4W

DISC 1000030

130197a

··-~1
JO
IOI

LA_i_R._._A~/"RCJ.___ __:...___ ~-----+-c_eM-"~w~rCLPc..:ER.....:..M~A....:..s~o~~~~~·....:..'o::.::a_.i...:9~0~0~9~1~5~7----1~1o~a:..Jl

..• J.... - - - - - - - ' - - - '

1
1

I
5

I---

t0,---+A_l_R-+------------+T~H=E~RM=A=L~C:.:O=M~PO:.:U~N.:.D_ _ _ _ _-19~0:.:0:.B2~6:.:8:.._____ .~

]REV.

I--

B3
B4

REVISIONS

!+-

---·-· -·---

0
I
. · - - - · · - · · _ N_U_T_,_K~---······ _ 9006557 .
>-4--+_4_ 4 , _ _ _ _ _ _
WASHER. FLAT. NYLON #6
·- --+9.Q0670_! __ ··-

i~
50
-------4--J
1305114

1302_17_7_ _ _ _-.J._4_3~
1302388
44

R51

ll
72

E43

R29,R34,RBB

RES 88K ~ 5% CC

____ '711_

R48

'.19!1101~

-_!+-i-9_0_99~B~9___ ·_==li~=

,_2__,__,2--l_R_ll..c,R9_2_ _ _ _ _ _ _ _-+_RE_S_820_~'--5%-CC
_ _ _ _ _ _ _~ /301775
6
6
R36,R54,R56,R57,R59,R60
RES 5.6K ~ 5% CC
1301874

R11D,R11 \R113·R117, RIOO

'.:_C:c...._l4_1_3_ _ _.. ______

_ _ _ _ _ _ _._l_.c.. _7_4_19_3_ _ _ _ _ _ _ _

1---f----<-~---··

____ 23_
24

I C 1401

t-2--+-_2__,_E_66_._E_6B_ _ · - - - - - · - · _ I C l493A
l-6-+-6--f-E.4__
.E_2_1_.E_2_B ~35.E56,E62
1.C 1404

-~KE_T_._MA_TE·N_·LOC_K_61320·3_____

r·6-+-6--l_E_32_._E_3B;_:Ec..:_39 .cE_4:..:9..:.'ccE6:..:0..:.,ccE6:.:5:..__+l....:.C_:l..:.40::0:..__ _ _ _ _ _ _-+col9~0~55e.'.l.:'.5_ _ _ _ ~

l--l--l1--1--t~R~31,-----------+-RE,.,,-S-1-.5K-,.l#l-5S-a;-------l--1300--3-9-l~----l-,,.35-

CHANGE NO.

I---

3
5

l-'l--l-~l--t~J.:.3_ _ _ _ _ _ _ _ _ _+-KEY~l~NG"-'-'PWG""'-~MA~T~E·~N~·LOC~Kc..__ _ _.j_~l2~1~15~95:'....._

Kl
l

NO.

1-AH·MJ7211·M

,_1.:.2+.:.l=-2+--------·-·--·
2
4
E48,E53

NO.

ASSY!URILLING HOLE LAYO.ff

PAR1

REF

53 54 ~3,C6B,CJ4 ClB,C89,C92-C91

HEM

DESCRIPTION

REF. DESIGNATION

REF

....V1

ITEM

1
1

[TITLE

LA36

jSCALE

]SIZ~
DB

MPC
l SHEET ::.£
2

NUMBER

M7728-0-I

REV.

Ji ]01ST]]] 1111 I 11

21-3

5
+& 0--, -

r -

?~s

TPXS~ ~D

g"or!v~o.J'~SWR~Tcrl~ALPE~::s~ CORPOltATION"

747'1-~·

_~--+-3~~Jter

l ·
R0,_

i3f!>JJ-1_1
MPC4 CSI b L

TP~(,I

MPC'I C515 l

CRY '&TioJ"'

'l
741''3
lllPC4 REG 3 H ---+- 03 E<:l

R:,(J)

l'IPCB \JU L

TPY2

MPC4 CS!/!3 L

4 -·~

MPC4 C504 L

l '-<1l?z4

(+'OV

EZfu

El(,/'.J
X>-----<C

_G:J IS

-::!,-

El~

l~?"TPXbb

h-u------u

~IPC3

?.>MB05

4
2 'k4~t h-3;c...---------~
s 7400

MPC 3 l'>MB(il·r

E32

MPC5 CLK H

10~

'l ]141210

li'.':.o.'"
I~ :i"
t-1--~r++-f-+------+-+-_l_-+-----~
CR'l'BRW

L -

1 - - - - - - + - + - + - + - - - - - - - - - - MPC3 1'1Bi21'>
B4 >-B'.>

VGG

OTPX42

MPC3 l'iMB1212

~DZ

MPO l'iMB121 I

~DI AOORESS, RI (i) t---2-..--+-+-+-+-+-+-------t-+-_J_-+--------~

f---orPx4r..

f---o-12V

TPX3'?J
3
R0(1) t----+-+-+-+-+-+-+-------t-+--+------------'

TPX'.00

CLR CUP LO CON

17
._________. A 7
18 Aro

PGM
1702A
E24

~A?
t8 Alo

2121

11
00B 10

21
I

121:377 Dii!o>--"---Ao PROM(I)
B

l'?J

~------<AS

TPY17

EZI

TPX47

--,

t-------t----t-----------

1TPX':>I
113

I
I
I

~--------iA4

'-------~2c-1 AZ

~--------< A I

~-------3--; A0

D07t------~

D_i!St----7 --~
0041---

003~

'"j;: :::~

I
I
I

~lb

R'S

D(l)1t-1~(1)-1--r-------- MPC.:, MB(I)~

'-----2--11 A'.> =~i7 0(1)(,1-9--+-+.....------- MPC3 MB05
D05t-8: - - + + - t - r - - - - - - - MPC:. M'B04
'-------2--1AI
0(1)4t-7--++-t-+~----- MPC:, M?.03
' - - - - - - - 3 - - i A(I)
011l3t-"'--++-t-++.----- MPC3 MB02-

~:~ t-~--++-t-++-t-+~---

]~3

'------1~ AZ

@~~
fil

I
I
I

RIB
IK

~"·

;;u

1TPl41
MPC'o &MBQl3

I
I

•CD

1TPYI(,

~(\j
'i'-

t'IPC3 BMl'>1212-

('-.

~
(f)

1TPYIS
7'T04
E4

MPCO> B~IB(il I

MPC" Ml'i0 I

MPC3 Ml'i/110

TP"Yl'.>

11~2

"'2
~60 VGG

MPCo l'>M1'>04

ISl

1~~'1
~

Dl2l8>--,---~-------- MPC'.> MB07

TPX4S

l'GM

'----2~(1)~A4

+sv 0

VOD VGG CS

IJ~~A

7404
E21

TI~ ~2

1-it

'----~AS

MPC'> Bl'll'Q)i,

1TPX:'i7

~~-1_1u1404 >-l_Ol_~--- Mrc.:, P,Ml'\1215

J +B

o+sv

I~>19~
-~---

~---M-PC_"_w_u_H_ _ _ _ _~_1~~s'(i~4

__l_Jo

1TPX21'

.,,,~>--(,-~--- MPC'J l'>MBl2ll
TPl47

'-' <JV

I
I

I
I
t----_J

OTPX4'1-

Ml'C'i MB02

QTPM0

B2t-5-~1 ---,-+-+-t-!r-t--+---------MPC3 1'11'>1211
4 1 ~-+-+-+-+-+-+-+---------- MPC;, Ml'>Qli21
BI t--I

RZ(ll>--f,---+-+-+-+-+-------+-+-_J_-+-------~
REG
Ill''.>
-

0:171

D45CB

I
I

MPC3 MB05
MPC.'.> l'IB(l)'I

R':J(il

1---------- -- - - - - ------------ - - - - - - - - ! H

El">
CROM

~ AI

~ 03

MPC'l BMBIZl(I) ~ 00

Z!/JA2

PROGRAM

MPO BMBil)3

',iJllS(2)~

TPi04"

I{, Afo
11 AS
I~
0
A4
19 A3

L:3'1'.J5Ji4L:.+B

S.G K

BI--b~:7412~

Ill

4
~
10 j_
7408
5
£12

MPC4 CSll l

~ R5"

I'.>

OTf'lb'I
__l_

LOCUPCLRCDN

TP9(,'t

BB 1-1
,,,1, . . - , . - - - - - - - - - , . - - - - - - - - - - MPC3 MB07
1'>7 l(I)
MPC'.i 1'11'>0(,

0 112 CSZ
B5 B
3,CS3
t-----~_t::::L:I--'-_
MKZl..ZIO

MPC4 R£G 2 H ~ D2
R2 (ll >-------+-------+-+-_l-+------1
I
PROGRAM
.J:_TPXfo'.>
2
MPC4 REG I H -t-- O I A~EEG<?.S RI (I)
~
OTPX4'.>
MPC4R£G0H~00 4:1 R0(1lt--3---..--+-+-+------+-+-__l_-+----~

r'IPC3CLOCKA

9
hB

13 A'?J
22 CS0

TPl(ll

12 D I
1474 t-'

MPC4 5KIP L

.i1r~

PREFERRED CONFIG>URATION

~
14 All
OTPllob~--------'--l"i'-1 AT

7
i;

')O 2

"THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE
PROPt:RTY OF DIGITAL EQUIPMENT CORPORATION Ne
SHALL NOT IE REl'RODUCID OR COPIED OR USED IN WHCU
OR IN PART AS THE IASIS FOR. THE MANUFACTUl.E Oil SALE

I
I

1TPl57

B
MPC" B 0 1B0i2)

I
I

I
I
I

TPX410<>--~~---------------------+~

SUBSTITUTE

CDNFIGUl<ATION

L __ - - - - - -~-----------------------------------------------------------_J
REVISIOl\IS

CHK

CHANGE NO.

REV.
TITLE

SCALE
l>CC,onNO.
DllDI,.

LA36

+--+

,NUMBER

MPC

M7728-0-I
SHEET

21-4

REV.

a 2

''THIS DRAWING AND SPECIFICATIONS, HEREIN, AAE THE
"°"6.TY OF Dl&ITAL EQUU'MENT CXJRPOltATION AHO

SHALL N:)'I' IE lD'RODIJCS) OR COPHI> OR USED tN WHOU
OR IN PART AS THE llASIS FOii. THE IMNUFACTVltE Oii: SALE

g'°~~~6~Al~:rCOAIOllATION"
MPC3 BMB(/)5
MPC4 CSl!il L

b-1'----------+---+---Ef*~~----------1 DI

RI (I) ,_z=----~-+--+- MPC4 REG

I'll (I)

1 5 Diil
1"10(1l n-:5=---------+---+---+---E+e~+---------1
13

l'I

12
]

CUP LO

4 5
l'IPCG WU H ~ J
MPC4 -I REG L ___j

-----~--~-t-----+--t--rl--11 E10

~')cf.'.:::'..~-1:-,:-l-1.-+-+-+--"1:-J 1:~ II ,_B____45_,7;~a

MPC4 +I REG L

TP'f31

141111

MPC4 CSiiJ(I) L

+lsv

-v

r;,J_t'IPC4 ZERO H

TP'fl

~')().=--L-Gl~~-

t15VR2

T?'f3

~101

TPYl(ll

141118
El{;,

MPC4C51212L

R3
IK

I H

R0(¢)f-3--~+-+-+-- MPC4 REG i1l H

CLR CON

Afl)

l'IPC-:'.> BMBQ)S

!OMl'.>(2!3

R2(1) ._"----~-+--MPC4 REG 2 H

l(l> 02

AO>

~11-'C '.>

MZCil h_g

CRAM

R3(1l ...1
-----~- MPC4 REG 3 H

1-1 ----·--_:~HpH------------------'3'-l m
M3 (I) u-

1(1)
7489
'---'-I DZ E :,

CRY BRW

ENB

:y65
~
_l_l______~.,.g~~~~~

L----3-1~

+Jsv
RI
IK

TPY4
-v
I:'>

12.

14013
E6

TPl\31

i~}~~

MPC4 SKIP L

----nTPXS3
---.nTPX52

Tl''f2 3

TPXSB
TPX0i11
Tf'X02

lPY20

+SV<>
. -

MPC4 REG 2 H

~DIS

r\l~t:,~

MPU, KBH

_'.! 012

7415111
E 14

~ DI I

SKIP

£.!._ D\0

MUX

~ D:I
MPCT CARR'f H ~DB
MPC':> PNTABL H ~DI

li11K

l~~;ri')

~IPC '.'.! l'>S L

~ 01 I

SKIP

MPC1 BORROW H

_?.?._ 0'}

~ Dl2

\:12 n-1-4-1--+--+--+-+--+~--- ~IPC4 STEP LF L

l'llf-' 13
f 1111 I I
f '} h 1111

Oil

_;.,03

MPC~ LF H

_2, DI

MPC'l llH H
MPC 5 Z0B H

~DZ.

MPC4 REG I H
£2

Si1l

05
-04

~03
~ D2

z I 02

+3 h 4

'----------1-11_1_13--14-'--15_ _ _ _ _ _ _ _ _ _ _ _ _ _ _1_1_1_±_1_3_14--'-15
___

1;2

MPC:'> BMB(l)6

21 D2

MPC:'> l'll'IBQ\5

MPC4 CLl1DAL

S'IBI

___.l~~;::::i ·:

MPC4 CSQ)3 L

MPC3

fl!PC3 BMB(l)4

(DEC I)

I 111

-1'5

('',m I)

5 _ _ _ _ MPc+ c'-'04 c (SKP:·,
.i;4 n....::.
4
f:'>
'1Pl"l C··0o _(SKF,)

22 DI

'<2

23 0121

"'>

"'FC4 csi;J: c(BNl +)

+0 l"'\...'----'--'-1---.

1'3
MPCS

CLK L

'TPY7

Tl'! :i
' - - - - n T:- XS':J

'-----n-p)(5"
R"ll
10121
-"""""""--L--n TPX 34

CHAR 1E5T L

REVISIONS
CHK

CHANGE NO.

REV.
TITLE

IMC,_ ...
-Ill

STl'>I 5Tll0

-OTPX3111
-"11'1\'.>2
~ TPY I I

(JMPZ.)

MPC4 LOAD CBA L
MPC4+1HECL
MPC4 CLR KBH L

MPC4 [''15 l

.\B .,_9
__,_ _ _ _ MfH CSl,21 L

MPC4 llR\lE WFF L

f l h_Z

L \JMP '>)

r>-'1-'1+ - 1 - - - - MPC4 CSl2

2¢ D:'>

+121h I
ST 5 C11 !"""

L (JMP4)

4+-1----(Jl"IP 1)
.\I Z n-'1-"
13

''J

BMBV\I

z; Dill

HPC4 CS 12 L

SEL

MPC4 CLR BELL

i;5p6
+ 4 !"" 5

\ ( " JIB
52

-1'13n...~_,__.__ _

CLK

MPC4 SE1 HDE L
MPC4 LOAD DIAL

I' G ho--7- - - ' - - - - - - - - MPC4 -I 11EG L

~DI

~ 0111

flS r>-'l-'7--+--+--+--1--'-l t:,

-'il4 n...1-5--+--"-'-'--

MPC4CLRHDEL

W D3

-------IDI

E22

~<>-~--+-!-''-------- MPC4 SET BELL

~0G

MPCf INC H
MPC'j CRH

~04

SO>

-¥-i

ff)

DEC

~Ui

14154

pr>-1-5-1--+-+-+-+--+-i-~-- MPC4 SEl HOLD L

FUNC

MPC4 REG0 H - O T

~OS

~ 0121

i.,; DIS

~Dl"l

Wll

~ OG

MPC4 lERD H
MPCID DA H

llilK

ST5

MPC~ HT L ~ 010

'It I

TE431~4

____i:i_"
R3 B

_.[----<D;- ~-<t>"'----'----11- Dl4

MPC4 REG 3 H _!2_ Dl4

~013

l MPCoBMB!ilS----,
<"

R'iT

TPX24
IT
r-OTPX'lb
fl5 pn-:---1--Hl-++-H-+-j+-_J__'----"'
MPC4 CLR !NIT L
.i; 14
I(;
MPC4 ClR Cll'> L

LA36 MPC

NUMIEA

M7728-0-I

21-5

REV.

: : :~R~AS~=~~ ~~~ACTURE OR SAU

i)' /'f75 DIGITAL EQUIPMENT CORPORATION"

~+sv
tSV

Ck>'13

.005UF

·~~~----11----.L:..4

TPl\b

E1,"
4 BIT
RIPPLE

RI (ll

Tl'VI I

12.

R'1l(tl

TPi!:i;;i2)

TPY2B

R'f-,
22(1)

OPTION CLK L
R1,7
IK
IW

-lEJ°-20V

'W7

RSI
470K

R'2

!320
G.4
MP5A05

RS3
lli'IK

R"8
\K,IW

20MA
LOOP

t5V
'l

RS!il
'.12

Ri;,(21
5·bK

'IN21,

:i.:iv

RECE\\IE

MPCS l-1'84US H

"'"

MPC7 \.\84US L

CLl<ii! CLKI
14

TPY?A

tl4
74C..A

5":l2 NS

8
R2lll

CLR

I 'fl~

MHi!:

Ro(ll

10~

CR I
HB,G.'1)0

TPl\3

R55
IK

D
7t~3

::-

MPCS CLK H
i'IPCS CLK L

112'

JCJOOUIS

R'-b
180

C§?
3 PF

R5b
5.GK

.005UF

a 2

'.l l-0-8ZLLV'-4
""''

ci;,s

"THIS DRAWING AND SPECIFICATIONS. HEREIN,. ARE THE
PROPERTY OF DIGITAL EQUIPMENT CORPOltATION NCI
SHALL NOT IE REPRODUCm OR COPIED OR USED IN WHOt.E
COPYlllGHT

TPB0
Tl'XS7
tSV

c
+c

Rill(ll
Rl(ll
R2(1l

1't 'l,,
l'IPPLE
R3(1)

LD
CLK

12.

R121(1l

_ ___

':.

JZ-U JZ-F
._____..
_,_

4NZb

MPSAill'O

4N!IPF

G.Z

FUN:TluN

LINE

(21
LC,~AL

MPCS Q../3 KHl

7t I b I
E" Oi

~d~~~~R

R70
\K.IW

R4B

l./3K

-~-20V

+11

MPC5 Zlilll H

\HI
\K.IW

~<..)

TPll

TPt.7

C!l>.

TPX I

R2(1l
CLK(ll

CLR

MPCS 7l US

Rl(ll
~

R"'>(il

TPX'l

Et;,13
4 Bii

\J\4

TRANSM II

C'll

Db
IN4121(;14

TTL !1EC DATA (S.I.)
l< l'IARK

CL~ I

MPC\

IPlG

MPCf> REG TO SEND H

WIZ

3
4

R0(1)

RI (ll

12
RZ(il
II

R "'>Ul

C95

n-+--~-0--~

I .1uF

TP1.12
LOCAL L

+sv
MPCS \.7 G KHi"

----

14\bl
H.1
BINAR'I
COUNTER
CLK
+IS
CNTEN

TPVl't

+12v

MPCl. s.o.
RST

-12V

W2
IZI

FULL DUrLE.X l'ASl;IVE

LEGEND:
CHANGE NO.

MPCll REf\DY M

WI:'> IJ\4
TTL DATA TERMINAL R"EAD'f

IZI

(1l

'1)

(1l

Ill

I: JUMPER INSERTED

IZI: JUMPER NOT INSERTED

REVISIONS
CHK

"'0" 0 0

IPl"B

T?r:I'+

NOTE: FOR OTHER CONFIGURATIONS SEE LA3b StRVICE MANUAL
JUMPER

REV.
TITLE

SCALE

r-----..

MPCG ~REAK t L

MPCI

FULL aJPLEX ACTIVE

1 •••

tSV

Cf/J.

21-6

NUMBER

LA36 MPG
-f----1-

M7728-0-I
SHEET

REV.

"THIS DRAWING ANO SPEcrFICATIONS. HEREIN, ARE THE

PllOPEUY Of OIGITAl EQUIPMENT CORPORATION ANO
SHALL NOT flE REl'RODUCEO OR COPlm OR USEt> IN WHOLE
OR IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE

FUNCTION

ra~~i~~~m5~~1~'!.~;:~M~ CORPORATION"

150 BAUD

J2- JZV
T .
<;!)
(];

8TH Bl1 M~RK ING

300 BAUD

B~UD

110

FUNCTION

300) n1s

BTH Bl1 Sl'ACEING

(];

EVEN PARIT'i

\lJ
\lJ

i;1)

R'l-3
1(il K
OPTION INSERT _;:
+sv~n---'Vl11r--~----------------------------------------l~:;cvJv
oPT10N DAL

LEGEND: IZl ~ LIUMPER INSERTED
I o JUMPER NOT INSERTED

X ~ DON'T CARE

'1PC4 'WRITE BUFF L

,.1_S D 10~
I f-8~----------------,~I
74'J1
o

IH
-IZV

+sv --

II E31Z> h 3
--jC IZ>f--1'-' ~

MPC'\ CLR DA l

1-EREAKp,

MPCl'l WU l

-T

tv-H---~-~{lTPt13

:+-· I

~j-'-'!I_

lI==_

Tf'VZI

r-----0TPYlb

-----OTPVZ3

R4-I
JJ
10K
r,_~~H-----------~-'V'IV---0--{) +sv

4
2

r-"-

~- 01"741 !--'h [,

EOC

[I TX

~ ~~~13)>-°'--+-----+<S>-+-MPCc- UART DATA 4

--------ps

TPXZI

s0:n
ESI

lo -+-----+-<FH- MPCG LJART l'ATA '

101<

-v

r-----V\l\c---0-t-SV

R42
10K

~~[/)-<,-0>-'.)----~

-=-

°'T ',/\I

t'.'>V

f\%

ESl>

>---+------+v">-+-- MFC (, U/\RT []Al'A "\

2242

'o7HB 35 ""13~ R•o

Jz1 p 4

>-+-- l'IPCb UAR> DA>A /o

~
100
,~~r----~-----------'V\Ar--~-KE1 STBH
L_L

~511~(,::> G
'
U0 p ~
' ~ x CLK
XRO'i I I
I
-~>---~~.-~-<C ~.__._.,_~,--MPCf, KEH H
cm Loe NBz NEI NP 2sB EP !
L-2.qn04
s
TPVIB
6
6
11

~TPVZ7

clPCG 'WU H --~-t---~

ot----~--~

'-----~---"12~
lo
11

25
MPC' "
SERIAL OUT)-----~
u
~ 0

~~0-o LO XO

: : dfusuF

RD I 12

MPC"- CLR KEH

rlH

,J~ )1-5-f------+,c~c

TPVIS

~ 1---~----+-v-u-+--MPCb uAR> DATA 1

RDZ>-1_1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

RD3~-

XD5

l\D I

~--(-?-~---; 'c4J:,f 3

5
~
'
G

=~: :8:~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~------~---_-·;fl

K_E_'!_4_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____,_f-2-+~ X04

r·--MPCG REG TO SEND H

~,____'>_ _ _ _ ___,__~'-">-+-- "1\-\"b UART r. ERR rl

Ess

Kn 3
28
- O T P l 2 1 j - - - - - - - - - - - - - - - - - - - - - - - - - - f - - f - - 1 . l\D 3
~----K_E_l_2_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-+-+-2-+7 XDZ
KE1 I
2b

'~->-+---~-"'~TPYZb
~ I

IJARI

l'--_ _ _ _ _K_E_1_5_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-+-+-3-+0 l\DS

'--______

-0

_J-

:~~1-"'=-___M_P_c~"-R_o_5____________________________

i 31

TP X 2

I c~:'~~~J)N

~~~.----0-w~i~s~~~~~~~~~~~0_~_0K-_-_-_-_-_:1c-_-+-!,1-_3!0-~~ ~~~

KEY G

-- MPC6 DA \I

PERR > - - - - - - - - - - - - - - - - - - - - - - - - - - - ·

~
!

V~-

FR ERR

UART DA L

_0.

OR rnR t--

STB STATUS

z 74~8
E42

r i R CLK

MlPc~s~-r II !

I ~
]1400
:,
l'tr/JIZ> i-r-6---,---z--j E3B ,,__ _ _ _ _ _ _ _

R DONE t-l-~-----,---4-j E3B

_K_E_1_1_ _ _ _ _ ___

i'lPn_J_IM ___ _J__--OTPi'20

MPCB REAm H

0c.,0'1r----J~--t-~~-l--<1 STB RD

0--------.z

J;;:'---"l

CLEAR DA l

~------------------t--------------~------------------------~~J

_::__j_

CLR ti DONE

--~-----<--1~4~:

OTP i' 11

-12V

RO,"o

l wvzc
::.:,
J ~ ·-~I

lTPV?~

FUNCTION GNO

z EGI

MPCG~~FFL

~ MPC[, 5BEAK + l

a 2

1-0-8 LLlfi

"10 VIII W15

DDD 'PARITY

I
1]

~B
I
1----+-----+---.;-V--t-- r1PC G lJ A fn DA'TA 2

12
~---------~---=~
I
II

C<~~H-----------------------------------t-----------~---------------f---~0TPLI'

0 TPY24-

MPlS 4-B KHl

JS
DD

11~

+5 v

RC,I
IK

Rb4
IK

4
Bf>40 1-3::__

+',V v-

FUNCTION 2

UART ENAl:,LE H

[J~404
E'ZB

lf----+-CHl--+--- St'ARE fUNC110N I

'-----1-~-.,_,-<'-'f--- Sl'ARE

(_)-(} - - ' V V V - - - <

>-+--~

J\.J

___:1.:c2_j

I I ]7401
ES 7

S
E'.:i'J
f--------0

umn nATR

R44

TPX'l-

_l_

110 !:JAUO

(_)

F·

f---+------1-0-+-- MPU.

)(ROY L

RGZ
IK

)

+5V

MPCS 211ll3 H

7
8b4(Z)

1--------'a E59

MPC5 1.76 KHl

TPY7

8
74-01

I \lJ

ES7_/'
~

REVISIONS

1---.--CHK
CHA NG ENO

REV.
TITLE

NUMB EA

LA36 MPC

M7728-0-I

AEV,

lL:-~-~-::'-,-,~~~8~~~--L~~~..-~~~~~.L..~7~~~~~~~~~~~~~~-6~~...J~~~~--.~~~~...l..~~-5~~~~~~..J..-.-~-~--~~4~.l--~-~~---.-~~..J.~~--::,----3-----l.S=C=A=LE;_,,,.__:__:___~...l.:S=H=EE=;-""-.....:~-"'~-'-.;;.,_;...;..i~1---..__._..._.....__.~.__.__.__

21-7

7
"THIS OAAWING ANO SPECl'FICATIONS, HEREIN, ARE THE
PROPERTY OF OM;ITAI.. EQUIPMENT CORPORATION ANO
SHALL NOT If RU'RODUCED OR co;>llO OR U5m IN WHOLE
OR IN PART AS THE BASIS FOR THE MANUFACTURE OR SA.LE

g"or!~~~~ff7$R~~~'j_~~:~ ~l'ORATION"

PRIN°\ MOTIO)'l

(.010')

RETURN MOTION

(.010")

'1-16} RETURN YIOTION
'i-17,

TP.!"51
TP'AIB

PTI COLL

tSV

TP), llO

.'co 1.ov P·P

C72
.041UF

RO,(ll t-7~------------<

9 D3
12

D2
DI

RZ(ll r--'°---MPCl COL lNC CNT 2
R I (il

MPCl COL INC CNT I

R i2)(Jl

:o,

MPCl COL INC CNT l1l

MPCl CARR\ H

741~0

+12V

INl~.SA

+sv

;,.~v

t - - - - - + - - - - + - - - - + - - - - - - - - - - + - - - - - - - - + - + - - - + - - + -5
---4DN

R'JB

::::

TPX20

10
MPCS

SINK

Cl'f
.. -~

R2S
IM

COLL

'"'IUF TzsuF
L:°_ ----j_ 2 5 y

CLK

COUNTER

CNl3

f---+-----4 1 CLK

TPYIO

R CLK

MAX/1"11N

TPXll

+sv

COL~~~ INC

RZ7

511.

MPC4 CLR C/5 L

1 •;,

C75

R28

.(2l47UF

5.1 IK
Ir.

I
+A

::::

Dl0

TPX22

MPCo CLK A

1Nl4BA

3-CJY

l
8

MPCS I. IB'f US H

TPY',2.

TPY°',0

RFC INFORMATION LOADED lNTC f/A

TPY2B

DIA Ct PRINT <RETURN M0118N)
0

REG3REG2 REGI REGO

Rl(ll
Z32K
I "lo

7'fll5

EB
DIA
i"IPC4

REG

D:>

TPYl'.J
MPCT 1-184 US l

::::

MPC'f REG

z H

Ro (I l f-----1--+--+-->----'\/IJl,-------i-<

R\5

Rl'J

Rl4
IK

:'i.48.l<

IZIK
1%

1°/•

REG

0 H

R0 @
CLK

0
0

NOMINAL

SPEED (lf"o)

0
0

-3- 8

rJ;

(il

-7.G

-1s.2

-l'HZI

RZ0
Z.l':>K

-ZZ.8

R'l
232K, I"/•
Rll

G.S
NPSAQlS

8211)

(2)

(2J

-'i4· 2

CB2
ZZUF

CLR

111

-41. 8
-'fS.6

1(2';¢K

MPC 4 LOAD [)IA L

0
0

iZ)

TI'to Slo

R8k.

R0(1)t-----~--'\/\rv-~

(!J

I'/•
~PC'f

(1)

-11.4

R2Cl2il 11
RICI)

(1)

rJ;
r/J

10-~-+-f---'V\,'V--------+--_,_,
R 2 (I) t--

I Z D2

(I)

(/J

R3(0l
MPi''f P.EG

(1)

MPC8 W·LI. L
RB:'>

OS
RBZ

0~0,4

ZK
::::

REVISIONS
CHK

CHANGE NO

TPXllZ)

REV.

TITLE

SCALE

NUMBER

LA36 MPC

M7728-0-I
SHEET

21-8

REV.

....a 2

"TH.IS DRAW1NG ~ Sl'ICIFICATIOMS. HEREIN. AAI THE

~ ()I DNil'l'M. IQUIPMENT COltPORATION NilO
QlllllODUCID Oii. COPllD OR US&> IN WHOL1
OR IN PAAT AS THE WIS FOii. THE IMNUF.ACTURE OR SALE

SMALL

NOT'•

LF2 LFI

~W7~~=~:==..cOAPORATIOH"

HOLD

LFI

STP LF

I
I

STP LF

(ZI

HOLD

JI
TPZ48

LF2

(ZI

(/l

MPCB LF2
TPZ53

l(/l

MPC8 LFI

+sv

1Pl55

Gl't
MPSl\05

+sv

Dl2
0(,b4

MPM ,,FT HOLD L
RB~

R32
IK

Ql5

Ml'C't SET HOE L

\J.U. L

MPSA:.6

1P1.'tb
Rll2

CBI

22(/l
+SY

PARITX ERROR H

MPC.2 COL lNC COUNT ill

MPS ASS

25UF

MPC~

Q8
MP5AS5
l'IPCB \J.U. L

MPC4 CLR MOE L

+sv

R%
5.GI<

Roi

1(/)0

R'-5
IK

Cl.litl
MPSA(2J5

'vii

-=-

+sv

-::-

TPZ,S'I-

R58

RBB
4711J

I.SK

Db'-'1-

+sv

Rl00

IC!IK

2.7¢
PAPER OUT SWITCH

C~'t

39UF
THI!

I
S)

RIQll

0-''-:_..__l_K_ _.___ _-+<:D>+--MPCB HD EN L

Ro4
47121

I
=-

R
+sv

Tl'l2~~

'lie JUMPER MAY BE CUT FOR
LOWER VOLUME' BELL

TPl24

Tl'B3

F/\STON

GND

FR5TDN

Tl'l.3

-OTPH

Tl'B't

TPZ">

TPB">

TPl2'

A
REVISIONS
CHK

CHANGE NO.

-R

REV.

TITLE

M7728-0-I
1

SCALE

-·"

21-9

REV.

- -----

- --

MPC 4 WRITE 'BUF l

+5V 0

_6_ 2

111'r.b UART Dl\TA I

MPn, UAR7 DATA 2

~ 00
~ DI

ASC11 I

M 1(1) h..7

ASCH 2

J:t

ASCII 3

M20)

ROB

MPc~
MPC~

~WI~.,,.

----0-

WR
12
10

Uf\'R"T DAT A 7

Jl\RT DAT A I,

MPCI, UART DA"T A 5

ASCI14
M~l COL

+svr..

Ji2

II
M3(0
tF
748'l
E3b
MZ(I)
02
I{. CHAR
h. 7
BUF
MJ(ll
DI
03

rt
I

R\11
ll!IK

ENB

ll'IC COUNT 2

A4
Bl
r,
17
AS
B2
16
Afo
l'>3
15
T
Al
M
14
MK2"2"P
AB
E'l-B
13
A' CG ROM I
l'l
Ao NUMERIC
20
A2

MPC1 COL INC CoUNT Ill

LO-

~Rl(ll8

RIJill

J0K

lllJK

Rlf/JI,
Jfj!IK

Rll!!'l
llllK

ASCII

W2Cll

..,..
n."
..,..
5

ASCII 5

AS.CI.I ,;,

R
-...,-

EE
-...,-

13
I~

Ml'C'I REG I H

2-i DI

1404
E5"

1121

22
21

MPC"J PARITY ERROR H

MPC4 ~EG0 H ~ Diil

~
~

-12V

cg;,,

.-!-!--~

RO(J)

o-1,
• -c'

RIO) 7
Rl(0)

11'>

C51
Al

SEL5

l+sv
lt5V~ l+sv

5EL6

+'B
l'!PC4 LOAD C"BI\ L

l+sv

l'1

Rll4
111lK

E52

RIIS

~lfllll1lK

l+sv

SEL 7

·~

FF
-0

R"J5
41K II

8741211

_,';

PRINTABLE

E">2f

l+sv

1142

RlllO
IJZIK

I4'1-

TPVH

MrC'J f'>S L

Ml'f":l HI l

PNTl\BL H
~---MPC9
I
7442
E2'.l i;-9 p11

cm ri_~C0li2_=y1

U>'>

+sv

'l-1k'

.l/ll UF

C"J/Zl
25 Uf

l1<11:i
10K

l+sv
RI~

llB

VGG

SEL:.

C7B
.Qll UF

Bf.
111
B7

CSl1l

SEL4

R8Ql
41K'

LIU

RBI
41K

CS3
CS2

SEL 2

T
B4 ·--·

Riii

IQ)

MK2C.21P
ES-.,
CG ROl1 2
ALPHA

10
R2(0 t------'
R2(111)

Bl
B2

RllJZI

~1311111(

---j~

A4
A5

llO
Ab
JS
A7
14

TPV6

12
MPC'I REG2 H --1 02

R'.l&
lr/JK

SEL I

-...,-

E47 /

-v TPZ27

'B13

~7401

10K

R15
411(

A'>
20
A2

-0 TPY25
-..., TPY27

'Bl

R'B

R74
47K B -

VGG

CBA
R..,(I)

CSI

C511l
21 Al

J..

lf-J

B5
'Bb

a 2

JZIS

l+sv
1t5V
l+sv ~r/JlllK
l+sv

cs~

C52

l+sv
l+sv

i]1:~ 1

1+5V
R73
471(

.4175

R3/0)

-...,-

Ml'CT COL 1NC COUNT I

ASCII 7

-0 TPY3..,

~ 03

PRIM H

(5!8)

1'13(1) ~I

M00)
00
A-., A2 Al A0

E41

Rll'JS
li!IK

MQl(I) h.5

A3 A2 Al All!
15 I
Jl3J'4

.,,.w1a_,,.

Rlfl4
llllK

_;!.

1·u~,.,

~ Rl22

Rl1112
Rllll3
~ ll'JK < ll'JK

ENB

I{. CHAR
10
JllPC,;, UARTDATA 3 _____, 02 BUF
(1:4)
MPC" UART 01\TA4 ~ 03

MP':!; hR"T f> ER1' H

(

r+~

R72
4TK

+5V

1-0-SULVll
tBIWflN

·..u·

J+sv

CICl'e m l8D r. 'MD.a:

THE~CllSMI

6~c~~E HJ p10
n ~

~ 03

f'I-

fS h.b
~

13
'----I 02
14
'-----101

n P"
.-2 tF 3

~ D0

fD I"

pz
I

:l~T
-

1404

Mf'C1 LF H

E28

TPl"2

1'104

E28

MPC"J C'< H

TPi!:'lB

~61
~

a.:

---

CHANGE NO.

REV.
TITLE

SCALE

21-10

NUMBER

LA36 MPC
+--J-

M7728-0-I

SHEET

REV.

8
COPYRIGHT(/'J 1974 DIG/ TJ'/L
£Ql.J/PME.NT CORPORl'/TION

NOT£S."

/. H£19TAPPL/£D TO Q/ ~ND G2 OUR/NG
SOLDERING SHALL NOT £YC££0 285° C
FOA ,q PEA/00 OF 15 SECONlJS.
2.F/N!SH£D HOL£ SIZE FOA MOUNT/NG QI AND Q2
SH/1Ll BE: .078 MIN.,.083 M"9X.
3. Al IJND fi.2 MUST BE OFVENTEO AS SHOWN,

3
REf:

)(-Y COOROINl1TE HOLE LOCflTIOl'l K-C0-5411"49-6-i

REF

/155Y/ORILL/NG HOLE LAYOUT D·/IH-5411"49-(/)-5 2

REF

MODULE ECO HISTORY"

~F"

ETCHED CIRCUIT BOARD

Rl,R2

POTt;.NTIOMETER.

Ql,Q2

PHOTO Tei!!NSISTOR.

!OK

13091'50-12.

151190CO

~-+--'-'----·---+------------t---

WITH NOTCH TOWAAD C£NT£A OF BOAIW.

c
NOTE 3
.750
REF

t
NOTES lf'2

__ry

{TRIM TO .03 MA>
Ir-

1--. 920 Rff__j

iu
I-=
I

(})

•<:!"

_ _ _ _ _ _ _ _ _ _ _....,_ PT COLL. 1

+5V ....

~-------<~~PT

RI
POT
10K

COLL 2

l!POT
10K

t----

QTY

REF DESIGNATION

PART NO.

DESCRIPTION

JITEM
NO.

PARTS LIST
ETCH BOARD REV

j 8]

]

l J

]

J J

~--+-----i+----t-------tlm~ ~~;~ENCODER PC BOARD
1----t------it----r-----,•RO~~ ~~~

PHOTOT RANS IS TOR

~----+----!!-----+----;NEXT HIGHER ASSY

21-11

3
DO NOT SCALE

DRAWING

NOTE._S:
I. ITEM"S , SHIPPING CARTON , TO BE VS[D
ONLY FOR SEPERATE: KEYBOARD
SHIPMENT.

o·

-CC>NN ECTOR

1<.E"... - -;;- 2

.54- RE.F

-.------

-"'110

."580

c
,,-.38 DI f>... BOSS

2. F'LA.C.E S

l
-'-----~~~=======~----''----------------'------+---J---J~t---·

3.900

,,5.so

.189 DIA

PLACE$

REF

.4115

I"'
-~~~1:1~~~~~~=====1_'2_._6_q_R_£_r:::,3-_-a-5--~-F========================l~~l~ 5~ O~NL

'188 2 ?UICES

B
.25 REF

.2.

""-

70 t2..:>25~--. .

-------6. 7 2 . S - - - - - - - - . . J

J.20

1.110 '

,750 TYP

--' -.::'>SO
--1.085--1.520----'

j L.458
B

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"THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE
PROPERTY OF DIGITAL EQUIPMENT CORPORATION AND·
SHALL NOT BE REPRODUCED OR COPIED OR USED IN WHOLE
OR IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE
OF ITEMS WJl.HOUI_y/RITTEN PERMISSION.
COPYRIGHT 1&)1975_, DIGITAL EQUIPMENT CORPQRATION"

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21-15

REV.

APPENDIX A
REFERENCE DATA

A.l ABBREVIATIONS
The abbreviations used in this manual are listed in Table A-1.
A.2 SIGNAL GLOSSARY
The signal names used in this manual are listed in Table A-2.
A.3 IC PIN LOCATION DRAWINGS
The pin locations of the Integrated Circuits used in the LA36 are illustrated in Figures A-1 through A-29.

A-1

Table A-1
Glossary of Abbreviations
2SB

Two Stop Bits

AKO

AMP
AR

Any Key On
Amplifier
Address Register

BCD
BEL
BS
BUF
BUFF

Binary Coded Decimal
Bell
Backspace
Buffer
Buffer

C/B
CB RAM
CBA
CG ROM
CHAR
CLK
CLR
CM
CNTR
COL
COL HI
COL LO
CONTROL RAM
CRAM
CTRL

Carry/Borrow
Character Buffer Read Access Memory
Character Buffer Address
Character Generator Read Only Memory
Character
Clock
Clear
Centimeter
Counter
Column
Column High
Column Low
Control Read Access Memory
Control Read Access Memory
Control

D/A
DAC
DEC
DIR
DM
DRVR

Digital to Analog
Digital to Analog
Decoder
Direction
Down
Driver

ENB
ER

Enable
Error

F/F
FIFO

Flip Flop
First In/First Out

HDE

High
Head Drive Enable

INC
INIT
IPS

Increment
Initialize
Inches Per Second

A-3

Table A-1 (Cont)
Glossary of Abbreviations
KBD
KBH
kHz

Keyboard
Keyboard Hold
Kilohertz

L
LCV
LF

Low
Last Character Visibility
Line Feed
Least Significant Bit

LSB
M
MHz
mm
MPC

µs
ms
MSB
MUX

Meter
Megahertz
Millimeter
Microprogrammed Controller
Microseconds
Milliseconds
Most Significant Bit
Multiplexer

NB
ns

Number Of Bits
Nanoseconds

POSHI
POSLO
POSMD
POS
POSIT
PT

Position High
Position Low
Position Middle
Position
Position
PRINT Timer

ROM

Read or Register
Read Access Memory
Receive
Receiver
Read Address
Read or Register
Receive Data
Register
Read Only Memory

ST
SYNC

Status
Synchronize

TACH
TTL

Tachometer
Transitor To Transistor Logic

UART

Universal Asynchronous Receiver Transmitter

VREF

Voltage Reference

RAM
RCV
RCVR
RDADR
RD
RD
REG

A-4

Table A-1 (Cont)
Glossary of Abbreviations
WC
WDCNT
WTADR

Word Count
Word Count
Write Address

Read Access Memory Transmit Data
Transmit

XMIT

A-5

Table A-2
Signal Glossary
Mnemonic

Definition

Source

Destination

BELL SINK

Bell Return

J5-2

Speaker

BELL SOURCE

+5 V to Bell

Rl 18

J5-l, Speaker

COMMON

From LF Motor

J5-4

LF Motor

PHASE 1

To LF Motor

J5-7

LF Motor

PHASE2

To LF Motor

J5-6

LF Motor

SOL 1:7

Solenoid Driver Outputs to Head
Solenoids

MPC3 BMBOO

Buffered Memory Bit 0

E584 or E614

E49-9, E2l-2
E31-l 5, E 15-15

MPC3 BMBOl

Buffered Memory Bit 1

E58-5 or E61-5

E49-5, E21-5
E31-14, El5-14

MPC3 BMB02

Buffered Memory Bit 2

E58-6 or E61-6

E49-3, E21-8
E3 l-13, E15-13

MPC3 BMB03

Buffered Memory Bit 3

E58-7 or E61-7

E49-l, E21-l 1
E31-l l, E15-11

MPC3 BMB04

Buffered Memory Bit 4

E58-8 or E61-8

E54-13, E46-23
E50-15

MPC3 BMB05

Buffered Memory Bit 5

E58-9 or E61-9

E54-1 l, E46-22
E50-14

MPC3 BMB66

Buffered Memory Bit 6

E58-10 or
E61-10

E54-9, E53-l
E46-21, E50-13

MPC3 BMB07

Buffered Memory Bit 7

E58-11 or
E61-l 1

E54-5, E53-2
E46-20

MPC3 MBOO

Memory Bit 00

E584 or E614

MPC3 MBOl

Memory Bit 01

E58-5 or E61-5

MPC3 MB02

Memory Bit 02

E58-6 or E61-6

MPC3 MB03

Memory Bit 03

E58-7 or E61-7

MPC3 MB04

Memory Bit 04

E58-8 or E61-8

MPC3 MB05

Memory Bit 05

E58-9 or E61-9

A-7

Table A-2 (Cont)
Signal Glossary
Mnemonic

Definition

Source

Destination

MPC3 MB06

Memory Bit 06

E58-10 or
E61-10

MPC3MB07

Memory Bit 07

E58-l l or
E61-l 1

MPC4CLRBEL

Clear Bell

E44-9

E36-3

MPC4 CLRC/B

Clear Carries or Borrows

E44-16

El 1-13

MPC4CLRDA

Clear Data Available

E44-2

E60-11

MPC4CLRHDE

Clear Head Drive Enable

E44-13

E39-1 l, E30-1 l

MPC4 CLR INIT

Clear Initialize

E44-17

E5 l-1

MPC4CLRKBH

Clear Keyboard Hold

E44-l

E51-10

MPC4CLR 568

Clear 568

E44-6

E15-23, E31-4
E30-4

MPC4 CSOO

Clocked Selector 04

E46-1

E42-1

MPC4 CSOl

Clocked Selector 04

E46-2

E42-2

MPC4 CS02

Clocked Selector 04

E46-3

E42-13

MPC4 CS03

Clocked Selector 04

E46-4

E37-4

MPC4 CS04

Clocked Selector 04

E46-5

E37-5

MPC4CS10

Clocked Selector 04

E46-9

MPC4CS11

Clocked Selector 04

E46-10

E27-3

MPC4 CS12

Clocked Selector 04

E46-11

E44-18, 19

MPC4 CS13

Clocked Selector 04

E46-13

E44-18, 19

MPC4CS14

Clocked Selector 04

E46-14

E42-5

MPC4 CS15

Clocked Selector 04

E46-15

E37-1, E42-3

MPC4 CS16

Clocked Selector 04

E46-16

E37-2, E37-13
E42-4

MPC4 CS17

Clocked Selector 04

E46-17

E53-4

A-8

Table A-2 (Cont)
Signal Glossary
Mnemonic

Definition

MPC4 LOAD CBA

Load Character Buffer Address

E444

E52-9

MPC4 LOAD D/ A

Load Digital/ Analog

E44-10

E14-9

MPC4MAX

Maximum

E23-6

E31-5, E 14-4, 5,
12, 13

MPC4 REG0:3

E32-2, 3, 6, 7

E524, 5, 12, 13
E38-l,5,9,10

MPC4 SOOO

Selector 0

E50-l

E22-2

MPC4 SOOl

Selector 1

E50-2

E27-2

MPC4 S002

Selector 2

E50-3

E21-3

MPC4 S003

Selector 3

E50-4

E31-9

MPC4 S004

Selector 4

E50-5

E15-9

MPC4 SET BEL

Set Bell

E44-9

E364

MPC4 SET HDE

Set Head Drive Enable

E44-11

E39-10

MPC4 SET HOLD

Set Hold

E44-15

E40-4

MPC4 STEP LF

Step Line Feed

E44-14

E24-3, 11, E29-5

MPC4 SKIP

Skip

E40-l l

E60-2

MPC4 WRITE BUF

Write Buffer

E44-5

E60-10, E56-3

MPC4ZERO

Zero

E23-8

E18-13, E31-3, 6

MPC4-l REG

Decrement Register

E44-7

E32-4

MPC4 +1 REG

Increment Register

E44-3

E32-5

MPC5 CLK

Clock

E64-5, 12

E46-18, 19,
E29-10, E49-13

MPC5 S.I.

Serial In

E66-6

E55-20

MPC5 1.184 µs

1.184 µs

E13-12

E37-10, E13-l,
E64-9, E7-13,
E9-3, 11

MPC5 1.76 kHz

1.76 kHz

E68-11

E30-3, E59-3

Source

A-9

Destination

Table A-2 (Cont)
SignalGlo~

Mnemonic

Definition

Source

Destination

MPC5 4.8 kHz

4.8 kHz

E63-ll

E26-14,El74

MPC5 19

E26-9

E67-5, E31-21, 22

MPC5 76µs

76 µs

E26-l l

E3-3, E5-3

MPC5 208

208

E26-12

E40-10, E67-l l,
El7-7,El5-7,
E31-19

MPC5 568

568

E30-5, 6

E64-l 0, E9-4, 10
E13-14, E37-9

MPC5 592 ns

592 ns

El 7-13

E20-l

MPC6BEL

Bell

El9-l

El5-6

MPC6 BS

Back Space

El9-9

El5-20

MPC6CR

Carriage Return

El9-3

E25-13, El5-4

MPC6DA

Data Available

E55-19

E31-7

MPC6 HS1:7

Head Select

E284 to 11 and
E334 to 11

Head Solenoid
Drivers

MPC6HT

Horizontal Tab

El9-7

El5-21

MPC6KBH

Keyboard Hold

E51-8

E31-20

MPC6LF

Line Feed

El9-6

E25-l, El5-5

MPC6PNTABL

Printable

E33-ll

E25-ll, E31-l

MPC6 S.O.

Serial Out

E55-25

E29-12

MPC7 BORROW

Borrow

E12-3

El 2-1, E15-22
E31-18

MPC7CARRY

Carry

E7-6

E31-23

MPC7 COL INC
COUNT0:2

Column Increment Count

E16-2, 3, 6

E28-l 9 to 21,
E33-19 to 21

MPC7 INC

Increment

E30-9

El5-3

MPC7 PT COM +5 V

Print Timer Common

Jl-U,V

Jl-13, 17
(Rl, R2)

A-10

Table A-2 (Cont)
Signal Glossary
Definition

Mnemonic

Source

Destination

MPC7 SUM

Sum

El-6 (Jl-B)

MPC8 BEL

Bell

R58

Jl-TT, Jl-38

MPC8 HDE (HDEM)

Head Drive Enable

E39-8

JS-2

MPC8 INIT

Initialize

ES 1-5, 6

El 1-2, E31-8

MPC8 LFl

Line Feed 1

E24-9

Jl-JJ

MPC8 LF2

Line Feed 2

E24-5

Jl-P

MPC8 LF HOLD

Line Feed Hold

E29-6

Jl-HH

MPC8W.U.

Wake Up

Q9-C

E53-5, El0-12,
E36-l, Jl-DD,
E14-1

P.T. COLL 1

Print Timer Collector 1

Ql-C (Jl-21)

Jl-Y (E34-2)

P.T.COLL 2

Print Timer Collector 2

Q2-C (Jl-25)

Jl-CC (E35-2)

A-11

Vee

GND

IC-0013

Figure A-1 380 Quad 2-Input NOR Gate

PIN CONFIGURATION
A2
A1

vDD
2

Vee
Vee

*DATA OUT 1

4(LSe)

*DATA OUT 2

*DATA OUT 3

*DATA OUT 4

*DATA OUT 5

*DATA OUT 6

VGG

*DATA OUT 7

Vee

*DATA OUT 8

11(M.e)

PROGRAM

Vee

*mis PIN IS THE DATA INPUT DURING PROGRAMMING

Figure A-2 l 702A 8-Bit Reprogrammable ROM

A-13

PACKAGE "A" -

BENT LEADS

IC-0123

PACKAGE "B" - BRAZED LEADS

INDEX MARK
OR
"'; ~
VGG e 1
NOTCH
cs 2 2
cs 3 3
Oo
4
01
5
02
s
03
7
04
8
05
Os
07
11
Voo 12

24
23
22
21
20
19
18
17
lS
15
14
13

Vss
CS1
cs0

Ao
Al
A2
As
A4
A5
As
A7
As
IC-0120

IC-0124

Figure A-3 2627P A6-01 Character Generator Alpha (Sheet 1 of 2)

A-14

FUNCTIONAL BLOCK DIAGRAM
1110987654

CHIP SELECT
0 7 0 6 0 5 0 4 03 02 01 Oo

TRI-STATE
OUTPUT STAGES

23
512 X 8

R0 M

NOTE: Choice of connection A or B for each chip select
is available as a mask option.

13 14 15 16 17 18 19 20 21

IC-0121

Figure A-3 2627P A6-01 Character Generator Alpha (Sheet 2 of 2)

SCHEMATIC
TOP VIEW
FREQUENCY
COMPENSATION
INVERTING
INPUT

NON-INVERTING
INPUT

OUTPUT

PIN LOCATOR
IC-0106

Figure A-4 3101 Random Access Memory

A-15

A PACKAGE
14 13 12 11

J PACKAGE

10 9

VAC

14
2

GND

IC·OO 22

Figure A-5 7400 Quad 2-Input Positive NAND Gate

tr'c.::.

4 '( 4B

'IA

3..8

I e,

2./3 GND

3 fl

IC-0129

Figure A-6 7401 NAND Gate-Quad 2-Pin Open Collector

GND

POSITIVE LOGIC: Y, A
IC-0011

Figure A-7 7404 Hex Inverter

A-16

GND

POSITIVE LOGIC: Y•AB

Figure A-8 7408 Quad 2-Input Positive AND Gate

GND

POSITIVE LOGIC: Y • ABC
IC-0010

Figure A-9 7410 Triple 3-lnput Positive NAND Gate

A-17

BI NARY SELECT

tND

POSITIVE LOGIC: Y= ABCD
IC-0008

OUTPUTS

IC-0009

Figure A-10 7413 Schmidt Trigger

GND

POSITIVE LOGIC: Y= AB
IC-0012

Figure A-11 7416 Hex Inverter Buffer/Driver

A-18

Vee

GND

POSITIVE

LOGIC: Y•A
IC-OOS7

~---+------oVcc

4Kil

3Kil

OUTPUT Y

INPUT A

2Kil

,___ _ _ __.___...,__..__-oGND
Component values shown ore nominal.
IC-0056

Figure A-12 7417 Hex Buffers/Drivers

Vc:.c

0.770 MAX

---..I

j@@®®~~~I

IC-0128
IC-0130

Figure A-13 7420 NAND Gate-Dual 4-Input

A-19

No Package Drawing Available

Figure A-14 7423

Vee

CND

IC-0126

Figure A-15 7437 NAND Gate-Quad 2 In Buffer, 14 Pin

A-20

INPUTS

OUTPUTS

GND

OUT PUTS
IC- 0 164

OUTPUT 0
INPUT A

INPUT B

OUTPUT 4

OUTPUT 5
INPUT C

OUTPUT 6

OUTPUT 7
INPUT D
OUTPUT 8
D

Vee• PIN 16
GND•PIN 8

OUTPUT 9

IC·0016

Figure A-16 7442 4-Line-to-10-Line Decoders

A-21

'10

de
CLEAR

de
SET

Vee

FLIP -FLOP 2
FLIP -FLOP 1
de
CLEAR

de
SET

GND

PIN LOCATOR
(TOP VIEW OF IC)
IC-0001

Figure A-17 7474 Dual D-Type Edge-Triggered Flip-Flop

DATA SENSE DATA SENSE
INPUT OUTPUT INPUT OUTPUT

IC-0007

Figure A-18 7489 64-Bit Read/Write Memory

GND

'(3

RESET
ZERO

PIN LOCATOR
(TOP VIEW OF IC)

IC-0100

Figure A-19 7493A Counter Asynch Up, Binary

A-22

Vee

,
CLEAR

CLEAR

2
Cext

2 Rex1/ GND
Cext

FUNCTIONAL LOGIC/PIN LOCATOR

Figure A-20 74123 Monostable Multivibrator

DUAL-IN-LINE PACKAGE

(TOP VIEW)

DATA INPUTS
Vee

DATA SELECT
13

DATA INPUTS

STROBE W
D
GND
OUT DATA
PUT SELECT

POSITIVE LOGIC
w=sl(A8coE 0 +A8coE 1+ .Aecf>E 2 +AecfiE 3 +A8cfiE 4 +AEicfiE 5 + .AecoE 6 + AecfiE 7
+ABCoEe +ABCDEg +ABCDE1o+ABCDE11 +ABCDE12+ABCDE13+ABCDE14 +ABCDE15)
tC·0117

Figure A-21 74150 Data Selector/Multiplexer

A-23

DUAL-IN-LINE PACKAGE (TOP VIEW)

INPUTS

OUTPUTS

OUTPUTS
IC-0044

Figure A-22 74154 4-Line-to-26-Line Decoder/Demultiplexer

No Package Drawing Available

Figure A-23 74161 4-Bit Binary Counter

A-24

Vee

CLEAR 10

CLOCK

GND
IC-0167

TRUTH TABLE
INPUT

OUTPUTS

tn+1

H
L

L
H

tn =Bit time before

ctoc k pulse.
tn1-1 -=Bit time ofter
clock pulse.

o-(_4_)- - - - ! D A

(5)

(2)

(7)

CLK 0 6
CLEAR

(12)
De

(6)

(10)

(11)

o-1_13~l+--+--1DD

oD !15l

CLOCK

CLEAR
Pin (16)• Vee. Pin (B)•GND
IC-0018

Figure A-24 74175 Quad D-Type Flip-Flop with Clear

A-25

INPUTS
,.-"-..

INPUTS
OUTPUT _ _ _...__ _'"'

DATA
RIPPLE MAX/
A
COUNT COUNT MIN
LOAD

D~TA

EN~BLE D~~N

DATA
C

DATA

GND

..___,. '-..,--' ~ '-..r-1
INPUT

OUTPUTS

INPUTS

OUTPUTS

IC-0127

,c;93 ~-----+---~
IVl)/11.

a .;~o-----+---~
),/{)tr;

Figure A-25 74190 Counter, Synch Up/Down Decade, 16 Pin

A-26

}
\...

f
DATA
INPUT A

..,.

"'V

BORROW
OUTPUT

-()

CARRY
OUTPUT

-v

OUTPUT QA

-0

OUTPUT Oe

-0

OUTPUT Oc

PRESET
QA

DOWN
COUNT

-0 T
UP
COUNT

DATA
INPUT B

'.J>E?

PRESET

~n ~
Oe

Oe h

DATA
INPUT C

..,.

~n
DATA
INPUT D

CLEAR

LOAD

PRESET

Oc
rJ T

QC ICLEAR

~,,-

~
-

,-6-.,
PRESET
QD
-OT

Oo h

Figure A-26 74193 Synchronous 4-Bit Up/Down Counter (Sheet 1of2)

A-27

OUTPUT QD

INPUTS

~OUTPUTS~
DATA CLEAR ~ LOAD
A
BORROW CARRY

CLEAR
CARRY
BORROW
LOAD

DATA
C

DATA
I

QA . COUNT COUNT

N~UT '-----y----' ~ '--v---'
OUTPUTS

IN PUTS

GNO

OUTPUTS

LOGIC' LOW INPUT TO LOAD SETS
QA•A, Os•B, Oc•C, AND QD•D

IC·0101

Figure A-26 74193 Synchronous 4-Bit Up/Down Counter (Sheet 2 of 2)

TOP VIEW

IC-0119

Figure A-27 Universal Asynchronous Receiver Transmitter

/111UI - DJP
( Dltl9L

ll'U

.en~llX'.e

UIU£)

C'O/?? PEIUS/971011)

t:>o/17PEIUS,qr;61U
//l.J l/£RTllU6

//VPUT
/VO/U-/11JJ/£RT/llJG
//lJPUT

OU7Pt.IT

vIC-0122

Figure A-28 301 AN DIP Operational Amplifier

A-28

TERMINAL CONNECTIONS
PIN I " INPUT
PIN 2" OUTPUT
CASE" GROUND
IC-0168

Figure A-29 309 K Regulator

A-29

Reader's Comments

LA36 D ECwriter II
Maintenance Manual
Volume II

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