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Document:	KE11-E and KE11-F Instruction Set Options Manual
Order Number:	EK-KE11E-TM
Revision:	002
Pages:	116
Original Filename:

OCR Text

KE11-E and KE11-F
instruction set
options manual

dlilgliltiall

EK-KE11E-TM-002

KE11-E and KE11-F
instruction set

‘options manual

digital equipment corporation - maynard, massachusetts

First Edition, January 1973

2nd Printing (Rev), June 1973
3rd Printing, December 1974
4th Printing, January 1975

The material in this manual is for informational
purposes and is subject to change without notice.

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

INTRODUCTION

This manual describes the KE11-E Extended Instruction Set (EIS) and KE11-F Floating Instruction Set (FIS)
Options to the KD11-A Programmed Data Processor for the PDP-11/40 System. These two options are described in
one manual because of their interdependency, in that KE11-F cannot be installed without the KE11-E being first
installed. The purpose of this manual is to:

Provide an overall understanding of the functions of these options in a PDP-11/40 System.

Explain how the KE11-E and KE11-F can be used in software operating systems.

Describe

the

options in sufficient detail to enable maintenance personnel to perform on-site

troubleshooting and repair.

In this manual each chapter is split in two with the first half of the chapter presenting information concerning the
KE11-E Option and the second half being devoted to comparable information for the KEI11-F Option. This
organization is intended to facilitate greater ease in use by those customers who utilize only the EIS hardware. Note
that due to the dependency of FIS hardware on the inclusion of EIS hardware, this split is not used in Chapter 4.
Chapter 1 provides an introduction to the options and lists brief specifications. Chapter 2 contains programming
information, listing instructions and illustrating their formats. Chapter 3 gives a discussion of the theoretical

principles implemented by these options. Chapter 4 comprises a block diagram discussion, a flow diagram discussion,

and detailed descriptions of the logic functions. Content and organization of this chapter are based on the block
schematics contained in a separate Engineering Drawings volume. Chapter 5 references the installation and
maintenance procedures provided in the PDP-11/40 System Maintenance Manual. Specific procedures are given for

modifications necessary to the processor, and for use of the Maintenance Module Overlay for these options.

Detailed descriptions of processor, console, Unibus, and memory logic that interface with these thiOns are provided
in the following related documents:

PDP-11/40 System Maintenance Manual

DEC-11-H40SA-A-D

KD11-A Central Processor Unit Maintenance Manual

EK-KD11A-MM-001

CONTENTS
Page

GENERAL DESCRIPTION

CHAPTER 1

1.1

1.1.1

1.1.2
1.1.3
1.2

1.2.1
1.2.2

1.2.3

KE11-E Extended InstructionSet . . . . . .. .. ... .. .. e e e e e e e e e e
. . . .. ... P P
Purpose

1-1
1-1

KE11-F Floating Instruction Set . . . . . v v v v v v o v oo e e R

1-2

Configuration
Specifications

. . . . . . . . . . oo e e e e e e e e
e ee
. . . ... ..o e e

e e e e e e
e . e
. . . ... . ... ooe
Purpose
. . . . . v v i iP
- Configuration
e e
e
e e e e e e e e e e e e e e e e
. . . . . e
Specifications

1-1
1-1

1-2
1-2
1-3

CHAPTER 2

PROGRAMMING

2.1

2.2.4

e e e e e e 2-1
ee
KE11-E Extended Instruction Set . . . . . e
e e e e e e e e e 2-1
e
e
e
e
e
e
e
e
e
. ... ... ... e
Operation
e e e e e 2-1
e
e
e
e
e
e
e
e
e
e
e
.. ..e
. .. ...
Formats
e 2-2
e
e
e
e
e
e
e
e
e
0oL
. . . .. . ...
Instructions
e 2-5
e
e
e
e
e
e
e
e
e
e
..
..
...
...
..
.
.
KE11-F Floating Instruction Set . . .
O
. . . . . . ... ...
Operation
e e e e e e e e e e e e e e e e e e e 2-5
. ... .. ....... e
Formats
e 2-6
e e e e e e
e e e e
..o
. . . . . . ..
Instructions
2-8
o
..
..
.
.
.
.
.
.
.
.
Programming Example

CHAPTER 3

THEORY OF OPERATION

3.1

KE11-E Extended Instruction Set

2.1.1

2.1.2
2.1.3

2.2

2.2.1
2.2.2
2.2.3

3.1.1
3.1.2
3.1.3
3.1.4
3.1.5

3.1.5.1
3.1.5.2
3.1.5.3
3.1.54
3.2

3.2.1
3.2.2

3.2.2.1

3.2.2.2
3.2.3
3.2.3.1

3.2.3.2

3.2.3.3
3.2.3.4

. .e e
. . . . . ...

3-1

Binary 2’s Complement Notation . . . . . . . . oot v vt L3

e 3-2
. . . . .. .. ... .. .. e
Multiplication
e e e e e e 3-3
0 o0 e
. . . . . .. ..
Division
e e 3-5
e e
. . . . . . . . . ... . ... e
Basic Shift Operation

Algorithms For KE11-E Operations

. . . . . .. . .. .. oo 35

. A 3-6
. . .. ...
Multiplication
DIVISION « v v v e e e e e e e e R . 338
Arithmetic Shift . . .. .. .. . 3-10
e 3-11
. . . . . & o v i i
Arithmetic Shift Combined
KE11-F Floating Instruction Set . . . . . .. e e e e e e e e e e e 3-12

PolishMode

. . . v v v v i it e 3-12

Floating-Point Arithmetic

. . . . . . . . . . ..«

o oo 3-13

Floating-Point Addition and Subtraction O 3-13

Floating-Point Multiplication and Division . . . . . . . . .. . ... ... ... 3-14
. . . . . . . ... ..o 3-15
Algorithms for KE11-F Operations
Floating-Add and Floating-Subtract . . . ... ... .. .. [P 3-16
e e e e e 3-18
. . . .. ... e e e e e ee
Floating-Multiply
Floating-Divide . . . . . . . . o . oo 3-18
Normalize, Roundand Store . . . . . . . . .. o320

CONTENTS

(Cont)
Page

CHAPTER 4

LOGIC DESCRIPTION

. o

4.1

SCOPE

4.2

Functional Block Diagram Discussion

e e e e e e e e e e e e

4.3

Detailed Block Diagram Discussion

4.4

Interface

4.5

ROM Programming Philosophy

4.6

Control ROM

4.6.1
4.6.2
4.7

e e e e e e

. . . . . . . .

KEII-E/FROM Word

e e e

. . . . . . . .

4.7.3

KE11-E Flow Diagram Discussion

4.7.3.1

Destination Calculation

4.7.3.2

Arithmetic Shift and Artihmetic Shift Combined
Multiply

. . . . . . . .. .
. . . ...

. . . . . .

FISEntry

4.7.4.2

FADDand FSUB

4.7.4.3

FMUL

4.7.4.4

EDIV

e e

v v

e 4-11

e e e e e 4-18

.. PO L. . 424

. . . . . . ... ...

. . . . . . . . . . . . ..

. . . . . .

..., 4-26

. .

e, 4-27

. . . . . . ... ... ... . 4-27

KE11-F Flow Diagram Discussion

e e e e

e e e e e e e

e ... 430

e e 4-33

. . . . . . . .. ... ... ... .... e
e
4-36

e e

e e e e e e e 4-36

. . .. ... . . . .. ... ... .. ..... PP . 4-38

... ... ...

... ......e
X

. e
e e e e
e
e 4-45

Normalize, Roundand Store
Logic Descriptions

e e 4-11

. . . . ... ... S e ... 418

.. ............... e e

4741

4.7.4.5

e e e e e e e e

e e e e e e e e e e e

KDI11-A Flow Discussion

Divide

. . . . .. ... ... . ........ e

Symbology of the Flows

4.7.3.4

4-4
4-6

. . . .. R
S B|

Flow Diagram Discussion

4.7.3.3

e e e e

. . . ... ... ... .. [P 4-10

. . . . . o

KD11-AROM Word

4-1

e e 4-1

. . . . . . . . PS

4.7.2

4.8

e e

. . . . . . . . ... .. e e e e e e

4.7.1

4.7.4

e e

v v i v i i

. . . . . . ... ... ... e e e e e e e e e e 4-47

. . . . . . . . . . 0 0 L

4.8.1

Basic CPUTiming

4.8.2

BR and DR Registers (Dwg KE-2)

4.8.3

RDMUX (DwgKE-3)

4.8.4

EUBC Control (Dwg KE-4)

4.8.5

Control (DwgKE-5)

e e

e e e e e e e e 4-50

. ... ... .. ... ....... e e

. . . . . . . . . . . .

. ... ...

. . . . . . . . .

... ........ e

e e e e e e 4-50

4-51

.. BT o452
e e e e

e e

e e 4-53

e e e 4-54

4.8.6

EPS and Count (DwgKE-6)

. ...

4.8.7

KE ROM Word (DwgKE-7)

. ... ........ S 4-57

... ... e

e ee

4.8.8

KD ROM Word (Dwgs KE-8 and KE-9)

4.8.9

HSR and MSR(DwgKF-2)

... ... e

. . . . . . . . .

e e

e e e e e

e e

FRDMUX(15:00) (DwgKF-3)

.. .......... e

e e e e e e e

4.8.11

ROM and Control (DwgKF-4)

... ... ee e e e e

e e e e

Installation

5.2

Maintenance

5.2.2

APPENDIX A
Al

e e 4-60

e e e

e e 4-60

INSTALLATION AND MAINTENANCE REFERENCE INFORMATION

5.1

5.2.1

e .. 4-58

. it
e et .. 459

4.8.10

CHAPTER 5

e e 4-56

. ... ... e e e e S e
. ... .. e

Diagnostic Programs

e e e e e eS

. . . . .e e e e e

Troubleshooting Test Procedures

e e e e e e

a b e e e e e e e e ..

541

5-1

e e e

. . . . . ...
.. .. e

e e e

e e e e

5-2

e e e e e e

A-1

e e e e e e

5-2

GLOSSARY OF TERMS
General

. ... ... ... ... ...

..., e

e e

e e e e e e e

ILLUSTRATIONS

2-1

2-2
2-3

2-4
2-5
2-6
3-1

3-2

3-3

3.5
3-6
3.7

3-8
3.9

3.10
4-1

4-2
43
4-4
4-5

4-6
4-7

4-8
4-9
4-10
4-11

4-12
4-13
4-14

5-1

" Page

Title

Figure No.

. . . . .« v v v v v v v v oo e e ee 2-2
EIS Number Formats
. . . ... ... .... e e e e e e e e e e e e e e e e - 2-3
Format
EIS Instruction
24
e e e e F
.... e
...
.
.
.
.
ASH Operation
2-5
e
e
t
e
e
e
e
ett
o
v
v
v
v
v
v
.
.
.
ASHC Operation
2-6
E
e
e
...
..
...
..
..
.
.
Format
FIS Number
26
O
P
..
..
...
..
.
.
Format
FIS Instruction
MUL Algorithm . . .. ... ... e e e e e e e e e e ee e e e e e 3-6
KE11-E
KE11-EDIV Algorithm . . . .« . v v v v v i o e e e P e 3-8
e e 3-11
KE11-EASH Algorithm . . . . . . . . . o i ettt et
et e e e e e e 3-12
KE11-E ASHC Algorithm . . . . . . . . o o i e

o oo 3-14
Floating-Point Representation . . . . . . . . .. . ...
Floating Entry Algorithm . . . . . . . . ... .. . v 3-15
317
. . . . ... ... ... ... ....... e
KE11-F FADD and FSUB Algorithm
3-19
e
e
e
et
e
o
.
.
.
.
.
.
.
.
.
.
Algorithm
KE11-F FMUL
319
2
e
e
e
e
e
e
e
e
e
e
et
e
e
e
e
e
v
v
v
o
o
.«
«
F
ALGOrithin
FDIV
KEI1KE11-F Normalize, Round & Store Algorithm . . . . .. .. ... ... ... ....... 3-19
. . . . . . . . . . . oo v v v i v i e it 4-2
EIS/FIS Functional Block Diagram
. . . . ... ... e e e e e e e e e e e e 4-7
Signals
Interfacing
A
KE11-E/F/KD11e e 4-12
e
.. e
...
..
...
.
.
Format
ROM
KD11-A
e e e e e e e e e e e 4-15
e
e
e
e
e
et
et
i
e
e
i
v
v
¢
.
.
.
.
.
Format
KEI1-E/F ROM
........ 4-16
..........
(Sample)
Options
the
by
Generated
KD11-A ROM Words
.. 4-16
...
..
..
..
..
.
.
.
.
(Sample)
Words
Comparable EIS/FIS ROM
4-19
e
e
bt
v
vt
vt
v
v
v
ot
.
.
.
.
.
.
.
.
.
Flow Diagram Conventions
4-28
...,
...
..
...
..
.
.
.
.
.
.
Answers
and
Operands
of
ASH and ASHC Locations
4-30
it
v
it
v
o
o
.«
.
.
.
.
.
.
.
MUL Flow, Block Diagram
4-33
e
it
i
v
i
o
¢
.
.
.
.
.
.
.
.
DIV Flow Block Diagram
4-37
..
............
..
...
..
.
.
.
Stack
the
on
Order
Floating-Point Arguments
4-44
tt
it
0
.
.
.
.
.
.
.
.
.
.
Diagram
Block
FMUL Flow,
e 4-46
e
FDIV Flow Block Diagram . . . . . . . . o v v v v it v e e
e 4-51
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
..
.
.
.
Timing
Basic KD11-A
54
...
...
...
..
..
...
.
.
.
.
.
.
Overlay
Module
Maintenance
KE11-E/F

gagre

TABLES

1-1

1-2
4-1
4-2

4-3
4-4

4.5

4-6
4-7

4-8

Page

Title

Table No.

e e e e e e e e e e e 1-1
KE11-E (EIS) Specifications . . . . .. ... ... ... e
t 1-3
itt
v
v
v
v
v
v
.
.
.
.
.
.
.
.
Specifications
(FIS)
KE11-F
e 4-8
e
e
e
e
e
e
it
i
i
i
v
o
o
o
.
.
.
.
.
Interface
KE11-E/F/KD11-A
.. 4-13
e
e
e
e
e
e
e
e
e
et
e
e
e
e
e
e
e
e
e
e
e
e
ot
v
.
.
.
KDI1I-AROMWOId
e 4-17
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
i
o
o
o
.
.
.
.
Ord
KEII-E/[FROMWo
4-51
e
e
i
o
v
o
o
.«
.
.
.
.
.
Signals
KE-2Output
4-52
e
e
e
oo
.
.
.
.
.
.
.
KE-3O0utputSignals
KE4Output Signals . . . . . . o o oo i it oo e 4-53
KE-5Output Signals . . . . . . . o o i i e 4-54

KE-6 Qutput Signals

. . . v v v v o v v e

e e 4-56
ee

TABLES (Cont)

4-10

411

4-12
- 4-13

Page

Title

Table No.

KE-7 Output Signals

4-57

KE-8 and KE-9 Output Signals . . . . . . .. ...« ... .. ce e

e e e e e 4-58
4-59

KF-2 Output Signals
4-60
KF-3 Output Signals ------------------------------------4-60
ooooo
oooooooo
oooooooo
oooooooo
KF-4 Output Signals oooooooo
5-2
.....
.......
.......
.......
‘KE11-E and KE11-F Diagnostic Programs

5-2

KE11-E/F Maintenance Module Indlcators ...... Ce e . .

Glossary of Terms

......
................................

5-3

A-1

CHAPTER 1

GENERAL DESCRIPTION

This chapter contains a general description of both the KE11-E and KE11-F Options. Mechanical descriptions are
given together with engineering specifications for each option. The chapter is divided in half with the EIS
information presented first, followed by comparable information for the FIS hardware.
1.1

KE11-E EXTENDED INSTRUCTION SET

The KE11-E Extended Instruction Set is a hardware option to the basic PDP-11/40 Computer System. It is supplied
as a pluggable opt1on to the KD11 A Central Processor.
1.1.1

Purpose

‘The KE11-E Option expands the instruction set of the KDll -A Central Processor to provide extended manipulation
of fixed-point numbers. When installed, it adds the capability of Arithmetic Shift, Arithmetic Shift Combined,
Multiply, and Divide. With these additional instructions, the system can multiply and divide signed 16-bit numbers,
and can shift signed 16-bit or 32-bit numbers. Condition codes are set in the processor on the result of each
instruction.

1.1.2

Configuration

The KE11-E Option consists of one module. The single-hex
X 8-1/2 in. M7238 module plugs directly into slot 2
(A—F) of the processor system unit. This is a dedicated prewired slot such that no other modules need be moved to
accommodate its installation. When installed, the module functions as an extension of the basic KD11-A data paths,

branch control, and control ROM. Basic timing of the processor is not degraded by use of this module, nor is the
NPR latency affected when its instructions are being executed. Interrupts are serviced at the end of each instruction
- in the standard manner.
1.1.3

Specrficatlons

Specifications for the KE11 E Optron are given in Table 1-1.

Table 1-1

KE11-E (EIS) Specifications

Instructions
|

Arithmetic Shift (ASH)
Arithmetic Shift Combined (ASHC)
Multiply (MUL)

Divide (DIV)
Operations

Multiplication and division of signed 16-bit numbers
Arithmetic shifting of signed 16-bit or 32-bit numbers

1-1

Table 1-1 (Cont)

KE11-E (EIS) Specifications
Addressable Registers

None 1n option. Operands fetched from core or processor general registers.

Timing

Time = SRC Time + EF Time
SRC Mode

SRC Time

0.28 us

0.78 us

0.98 us

1.74 us

0.98 us

1.74 us

Instr
MUL
DIV

ASH (right)

Siié :

Power Required
1.2

KE11-F

EF Time

| Notes

8.88 us

11.30 us

ASH (left)

2.64 us
e

2.58 pus
-

2.78 us

ASHC (no shift)

2.78 us

ASHC (shift)

3.26 us

+0.30 us/shift
-

+0.30 us/shift
|
+0.30 us/shift

Single Hex module (M7238)

o +5’V, 2.3A

FLOATING INSTRUCTION SET

The KE11-F Floating Instruction Set is a hardware option to the basic PDP-11/40 Computer System. It is supplied
as a pluggable option to the KD11-A Central Processor and requires that the KE11-E descrlbed above be 1nstalled as

: .1.2.14 Purpose
The

KE11-F

Floating

Instruction

Set (FIS)

enables

direct

operations

smgle-precmon

32-bit words in

floating-point arithmetic. Since the KE11-E is a prerequisite to the KE11-F, extended manipulation of fixed-point
numbers is available as well. The KE11-F Option further extends the PDP-11/40 instruction set to include Floating

Add, Floating Subtract, Floating Multiply, and Floating Divide. As with the KE11-E, condition codes in the
Processor Status Register are set on the result of each instruction. The prime advantage of this option is increased

speed without the necessity of writing complex floating-point software routines.
1.2.2

Configuration

The KE11-F Option consists of one single-quad X 8-1/2in. M7239 module with the KE11-E Option described above
being a prerequisite. This FIS module plugs directly into slot 1 (A—D) also a dedicated prewired slot in the basic
KD11-A. No degradation of processor timing or NPR latency is effected by the use of this option. Floating

instructions are aborted if a BR request is issued before the instruction is within approximately 8 us of completion,
at which time the Program Counter (PC) is adjusted to point to the aborted floating instruction so that the
instruction will be restarted upon return from the interrupt.

1-2

N’

a prerequisite.

1.2.3

Specifications

Specifications for the KE11-F Option are given in Table 1-2.

Table 1-2

KE11-F (FIS) Specifications
Prerequisite

KE11-E Extended Instruction Set Option

Instructions

Floating-point Addition (FADD)
Floating-point Subtraction (FSUB)

Floating-point Multiply (FMUL)

Floating-point Divide (FDIV)
Operations

Single-precision floating-point addition, subtraction, multiplication,
and division of 24-bit numbers

Addressable Registers

None in option. Operands fetched from core.

Size

Single-quad module (M7239)

Power Required

+5V, 1.1A (typical)

Timing

Time = Basic Time + Binary Point Alignment Time + Normalization Time
Instr

Basic

Binary Point

Normalization Time

Time* us

Alignment Time

Per Shift us

FADD

18.78

0.30

0.34

FSUB

19.08

0.30

0.34

FMUL

29.00

——

0.34

FDIV

46.27

—

0.34

*Basic instruction times for FADD and FSUB assume exponents are equal or differ by one.

1-3

2
CHAPTER
PROGRAMMING

This chapter is devoted to general programming information for the KE11-E and KE11-F Options. It provides

general descriptions of their operation, the formats and instructions for each. In addition, programming examples are
supplied for each option. This chapter is intended merely as an introduction to the programming of this hardware.
For more detailed information refer to the pertinent software documentation generated for these options. As with
Chapter 1, information has been separated for each option.
2.1

KEII1-E EXTENDED INSTRUCTION SET

There are no addressable registers in the KE11-E Optron EIS operands are fetched from either core memory or from

the general processor registers. The result of each operation is storedin the general registers.
2.1.1

Operation

When the Arithmetic Shift (ASH) instruction is used the contents of the selected register is shifted rrght or left the

number of places specified by a count. This shift count is a 6-bit, 2’s complement number which is the least
significant 6 bits of the source operand. If the count is positive, the number is shifted left; if it is negative, the
number is shifted right. This allows for shifts from 31 positions left to 32 positions right (+31 to -32) although a
shift of greater than 16 places loses all significance. A count of O causes no change in the number.

When the Arithmetic Shift Combined (ASHC) instruction is used, the contents of the register (R) and the reglster

~ ORed with 1 (RV1) are treated as a single 32-bit word. Register RV1 represents bits (15:00), register R represents

bits (31:16). This 32-bit wordis shifted right or left the number of places specified by a count. This shift count is the
same as that described for the ASH instruction and permits shifts from +31 to-32. If the selected register (R) is an
odd number, then R and RV1 are the same. In this case, the right shift becomes a rotate and the 16-bit word is

rotated right the number of bits specified by the count for up to 16 shifts.

When the MULtiply (MUL) instruction is used, the contents of the Destination Register and the source are

multiplied as 2’s complement integers. The result is storedin the Destination Register R and the register ORed with
1 (RV1). If the register is odd, only the low-order productis stored. This instruction multiplies full 16-bit numbers.
When the DIVide (DIV) instruction is used a 32-bit dividendin R and RV1 is divided by a 16-bit divisor to provide
a 16-bit quotlent and a 16-bit remainder. The sign of the remainder: is always the same as the sign of the dividend
unless the remainder is 0. Overflow is indicated if more than 16 bits are required to express the quotient. In this
case, the instruction is aborted. If the content of the Source Register is O, indicating divide by 0, an overflow is
|
o
indicated.
2.1.2

Formats

The number formats for the KE11-E Option are shown in Flgure 2-1. A single word is 16-bits long and a double
word is 32-bits long. In the single word, bit 15 is the sign of the number andin the double word, the sign bitis bit
15 of the high number part. The S bitis O for positive quantities andis 1 for negative quantrtres

/——DOUBLE. WORD SIGN BIT

15 14

1514

)

LOW OPERAND PART

HIGH OPERAND PART

ls l

0 15

)

/——SINGLE WORD SIGN BIT

- ]
0

‘Figure 2-1 EIS Number Formats

2.1.3

Instructions

The EIS instruction format is shown in Figure 2-2. It is a double operand instruction in which bits (15:09) comprise
the Op code, bits (08: 06) designate the Destination Register field (RRR), bits (05:03) indicate the Source Address
Mode (SSS) and bits (02:00) specify the Source Address Reglster (SSS). The octal codrng is in the form 07XRSS.
There are four EIS instructions, as follows:
MUL

070RSS

- MULtiply
"R, RV1 < R X(SRC)

Operation:

set if productis= O cleared otherwrse

setif product is <O; cleared otherwise.

~ Condition Codes: |

cleared

-215 or is greater than or equal to 215-1cleared
set if the result is less than

| _otherw1se

- Description:

The contents of the Destrnat1on Reglster R and source taken as 2’s complement 1ntegers
-

are multiplied and stored in the Destination Register R and the succeeding register RV1
(if Ris even). If R is odd, only the low-order productis stored. Assembler syntax is:

- MUL S, R. (Note that the actual destmatmnis R, RVl whrch reduces to just R when R is
odd.)

Example:

16:bit product (R is 0dd)

000241
012701,400

- 070127,10
1034xx

;
,

,
~,

|
;Clear carry condition code

CLC
MOV #400,R1

S
|
:Carry will be set if

MUL #10,R1
‘BCSERROR

is less than
sproduct

=215 or greater than or
equal to 2*3
:no significance lost

Before

(R1)=000400

2-2

o After

(R1)=004000

I0]111|||X X le R Rls S s|s s sj
|

J‘——jf"—"""——flr——'

SOURCE

OP CODE

SOURCE MODE FILED - %
DESTINATION
REGISTER FIELD
-

11-1604

*Note that for the EIS instructions the Source Register is
considered the Destination since the answer is stored in that

PDP-11 family instruction formats but is used throughout the
discussions of the EIS instructions in this manual.
Figure 2-2

DIV

EIS Instruction Format

071RSS

DIVide

R <R, RV1 % (SRC) RV1 « Remainder

Operation:
Condition Codes:
|

N: setif quotient < 0; cleared otherwise.

setif quotient= 0; cleared otherwise.

set if source = 0 or if the absolute value of the register is larger than the absolute
value of the source. (In this case, the instruction is aborted because the quotient
would exceed 16 bits.)

setif divide by O attempted; cleared otherwise.

The 32-bit 2’s complement integer in R and RV1 is divided by the source operand (SSS).

Description:

The quotient is placed in R; the remainder is placed in RV1 with the same sign of the
dividend. R must be even.

Example:

- 005000

Before

(R0)=000000

(Rl)'—f020001

ASH

CLR RO

MOV #20001,R1
DIV#2,R0

,
,

012701,20001
071027,2

|
-

After

(R0)=010000

(R1)=000001

072RSS

~ Arithmetic SHift

Quotient

Remainder

- Operation:

R < R shifted arlthmetlcally NN places to right or left where NN
= low-order 6 bits of

source.

Q<N
Z

Condition Codes:

Description:

set if result < 0; cleared otherwise.
set if result
= 0; cleared otherwise.

set if sign of register changed during left shift; cleared otherwise.
loaded from last bit shifted out of register.

The contents of the register are shifted right or left the number of times specified by the
shift count. The shift count is taken as the low-order 6 bits of the source operand (SSS).
This number ranges from -32 to +31. Negatlve is a nght shift and positive is a left shift

(F1gure 2-3).

Example:

ASHRO,R3
Before

After

(R3)=000003

(R0)=001234

(R0)=012340

RIGHT

SHIFT

IF COUNT

NEGATIVE
0

LEFT SHIFT
IF COUNT IS POSITIVE

11-1605

Figure 2-3

ASHC

ASH Operation

O73RSS

“Arithmetic SHift Combined
- Operation:
|

R, RVI1 « R, RV1. The double wordis shifted NN places to the right or left, where NN
=
|

low—order six bits of source.

Condition Codes:

Description:
o

setif result < 0; cleared otherwise.

set if result = 0; cleared otherwise.

setif sign bit changes during the left shift; cleared otherwise.

C:.

loaded with the last bit shifted out of the register.

The contents of the register and the register ORed w1th 1 are treated as one 32-bit word.
|

RV1 (bits 15:00) and R (bits 31:16) are shifted right or left the number of times
specified by the shift count. The shift count is taken as the low-order 6 bits of the source

operand. This number ranges from -32 to +31. Negative is a right shift and positive is a
left shift (Figure 24). When the register chosen is an odd number, the register and the

register ORed with 1 are the same. In this case, the right shift becomes a rotate. The
16-bit word is rotated right the number of bits specified by the shift count for up to 16
shifts.

N R

"RIGHT SHIFT

IF COUNT

7-—»l

iS NEGATIVE

4_.[1

—r

—

]

[l L I'V.':l[ b,:,' i lll | 1;14—0‘ RV 1
LEFT SHIFT IF COUNT IS

POSITIVE
11-1606

| Figure 2-4 ASHC Operation

2.2

KEI11-F FLOATING INSTRUCTION SET

thereby reducing the number of operations necessary to achieve a result.

There are no addressable registers in the KE11-F Option. FIS operands are fetched from core memory and the result
of each operation is storedin core memory. Operands are ordered on the stackin Pohsh Notation (Paragraph 3 2)

2.2.1

Operation

For Floatrng ADD, the A argument from the stackis added to the B argument from the stack w1th the result stored
in the A argument posmon on the stack.

For Floating SUBtract, the B argument from the stack is subtracted from the A argument on the stack with the |
result stored in the A argument position on the stack.

The Floating MULtiply mstructlon multiplies the A argument on the stack by the B argument on the stack and
stores the resultin the A argument position on the stack.

The Floating DIVide instruction divides the A argument on the stack by the B argument on the stack and stores the
result in the A argument position on the stack.

2.2.2

Formats

The number format for the KE11-F Option is shown in Figure 2-5. The KE11-F word is 32 bits long with bit 15 of

the high argument designating the sign of the fraction. Note that the 8-bit exponent separates the fraction from its
associated sign. In floating point, representation of binary numbers is in three parts: a sign bit, an exponent, and a
mantissa. The mantissa is a fraction expressed in sign and magnitude format with the binary point positioned to the
left of the most significant bit of the mantissa. The mantissa is assumed to be normalized. The MSB of the mantissa

is not stored in core because it is redundant. Leading Os are removed by shifting the mantissa left; however, each left
shift of the mantissa must be followed by a decrement of the exponent value to maintain the true value of the
number. The exponent value represents the power of 2 by which the mantrssa is multiplied to obtain the value to be
used.

2-5

I5 14

| OW ARGUMENT
—

(HIGH PART)

(EXCESS 2008)

—

,
FRACTION

.. FRACTION (LOW PART)

0 15

HIGH ARGUMENT

EXPONENT

FRACTION

SIGN BIT \ [

Y
[}

23-BIT FRACTION

H=1: Inserted ’b'y hardware before operating on’

)

— I 23
BINARY POINT
*

operands if exponent field # all zeros.

11-1607

o Figure 2-5 FIS Number Format

The KE11-F Option stores the exponent in excess 2005 (128, ) notation. As a result, exponent values from -128 to
+127 are represented by the binary equivalent of 0 to 255 (octal 0—377). Mantissas are represented in sign
magnitude form.

The binary radix point is to the left. The results of the floating-pornt operatrons are always rounded away from O,
S

increasing the absolute value of the number.

‘

If the exponent is equal to O the number is assumed to be 0 regardless of the srgn brt or fractron Value The

hardware generates a clean 0 (32-bitword of all Os)in th1s case.
Instructions

2.2.3

The FIS instruction format is shown in Figure 2-6. It is a double operand instruction in which the low three bits
(R,R,R) specify a register that is utilized as a stack pointer for the floating-point operands. The register may be any
one of the eight general registers, but some caution must be used if using the PC (R7). It is unlikely that the PC
would be desirable as a pointer.

lolf'1
1|1 L
o 1|o L1
0 OIx Ll
X xIR'R
R] b
L
R
-

e e

STACK
POINTER

OP CODE
.

11-1603
-

Figure 2-6 FIS Instruction Format

The operands are located on the stack as follows:

= High B Argument

(Ryt6

= Low A Argument

/15

«g

(R)+2 = Low B Argument

~ (R)+4 = High A ArgumentZ

~——————S

| HIGH FRACTION|

EXP

IR,

____ _LOWFRACTION
|

J
\\\‘a/,

(R)

The floatrng pornt answers are stored as follows
(R)+4
= High Answer
- (R)+6= Low Answer

The floating-point stack pointer is repositioned to point to (R)+4 (High Answer).
The floating-point octal coding is in the form 0750XR. There are four FIS instructions, as follows:
FADD

07500R

Floating-ADD

Operation:

[(R) +4 O (R) +6]
< [(R) +4 O (R) +6] + [(R) O (R) +2] if result >2-128;
else [(R) +4 [ (R) +6] <0

- Condition Codes:

setif result <O; cleared otherwise.

(See Note Below)

setif result
= 0; cleared otherwrse

Description;

cleared

'Adds the B argument to the A argument and stores the resultin the A argument position
on the stack. A < A+B

FSUB

0750IR

Floating-SUBtract

(R +4 D(R) #6] < [(R)+4 O (R) #6] - [® 0(R) 421, if resilt > 2125

Operation:

clse [(R) +4 0 (R) +6]
<0

Condition Codes:

- (See Note Below)

- Description:

setif result <O; cleared otherwise.

cleared

setif result = 0; cleared otherwise.

Subtracts the B argument from the A argument and stores the result in the A argument
position on the stack. A < A-B

FMUL

07502R

Floating-MULtiply

Operation:

[(R) +4 u (R) +6] < [(R) +4 D (R) +6] * [(R) El (R) +2] if result > 2-128;

else [(R) +4,(R) +6]

Condition Codes:

(See Note Below)

setif result <0; cleared 'otherWise.
setif result
= 0; cleared otherwrser

cleared

2-7

Description:

Multiplies the B argument by the A argument and stores the result in the A argument

position on the stack. A < A*B. If the resultis <2 '2® then underflow occurs and the
-

FDIV

destination address will contain the A argument.

07503R

Floating-DIVide

[+ O(R) 6] < [(R) + D(R)+6] | [(R) D (R) +2], i et3212

Operion:

O (R) +6]
else [(R) +4

Condition Codes:

set if result <0; cleared otherwise.

- (See Note Below)

setif result = 0; cleared otherwise.

cleared

‘

Description:

Divides the A argument by the B argument and stores the result in the A argument

position on the stack. If the B argument (divisor) is equal to O, the stack is left
untouched. A < A/B. If the result is < 2" '2®, then the destination address will contain
the A argument.

NOTE

If a trap occurs as a function of a floating instruction, the
condition codes are reinterpreted as follows: .
N:

set if underflow, cleared if overflow.

cleared

set if underflow, overflow, divide by 0 (error

C:"

set if dmde by 0, otherwme cleared

conditions).

Traps occur through the vector 244 (R)is reset to point to
high

B argument on the stack. The arguments are left

untouched.
2.2.4

Programming Example

A sample floating?point program is given below.

pepopa’

,CSECT

3
4
5

' TITLE FISEXM
3
;

}

7
8

;
;

1%
1

}
;

}

MAYNARD,

EXAMPLE OF PDPw= 11/40

COMPUTE

LARGER

AuX®X

"AlLLGQR]THM

ROOT1

BaX

ISy

DIGITAL

FLQATING

RooT

3 ¢

C
|

CORPORATIONo

!NSTRUCT!ON

QUADRACTIC

SET

EQUATIONI

(=B
+ SQRT(B#B

2-8

EQUIPMENT

MASSACHUSETTS.

44AsC))/(244)

USAGE

cP!S)

INITIAL VALUES OF A, B, AND C ARE
PLACED
RESULT

IN MEMQRY LOCATIONS A, By
IS COMPUTED AND STORED AT

AND G,
ROOTY,

NQRMAL TERMINATION IS A HALT AT LOCATION DaNE,

1F DISCRIMINANT IS NEGATIVE THEN HALT AT LOCAT!ON

IMAG.,

20202
20p201
geong2
gooa@3
P00004
g200@%
geoRge
gaoag7

]

RO
R}
R2
R3J
R4
R5.
SP
PG

}

HALT

AZERQ

poad4
pog1@
geegl4

02020
44
45

46
47

2%0

2%1
=X%2
a%3
z %4
%5

=%6
2%7

PROGRAM STARTS HERE
MoV

#STACK,SP

)INITIALIZE PROCESSOR STACK -

P16746

MQV

B#2,=(SP)

pap2a4
216746
6
ABR1L7

MQV

By=(SP)

MQV

B#2,=(SP)

MOV

By=(SP)

212706 START:
22p442"’

216746
4
PEP1L7
916746
Aap166

peg24 75026
gup2e pesP4e6
ega3p 212746

gee34 g16746

ooR44
ao@Aas6

22215¢

Pl16746

200142
Q21457

Pl16746
gag146
peps52 016746
geoi4n
pees56 75026
greéd @75026
pogee 275016
veQ64 120446
pRO66

912667

ege72

gap132
912667
P2B0126

CLR
MOV

»(SP)

#eF4.8,=(SP)

MOV

A+2,=(SP)

MOV

Ar=(SP)

BEQ

MOV

AZERO
C#2,=(SP)

MOV

Ci=(SP)

FMUL

JHALT
IF A 3
JC TO STACK

IFORM

AsC

4 ,eAeC

(SP)+,TEMP1+2
R5,SQRTY

pa126

STACK

MOV

Q20222

gR122

MOV

Aag401

JBRANCH IF NEGAT!VE
JSTORE DISCRIMINANY

JCALL FORTRAN SQUARE ROOT ROUTINE

210067

WORD

MOV

TEMP1
R@, TEMPZ2

210167

MOV

R1:TEMP2%2

sCOMPUTE

JFORM BQB-Q wAsC (DISCRIMINANT)

PR124
2a106

g16746
pepR72
P16746
g2p064
n&2716
1202002

JFORM BeB
14,0 TO STACK

SP
IMAG
(SP)+,TEMP]

golee

gepiie

JAGAIN

BMI

JSR

32114

STACK

JFORM

gr4567
2000046

gn1le

FMUL
FSUB

pBa7é6

ga112

FMUL

740600

gag4Q

=5 0,

NQRMAL REGISTER DECLARATIQNSI

eeegog

ISTORE

RESULT

ROOQT]

MOV

Be2,=(SP)

MOV

By=(SP)

ADD

#1000p0, e8P

2-9

T0 STACK

INEGATE

STACK

gol3e

g16746

MOV

gi6746

MOV

gepr72

eR136

gR14z2

pop064
@75206

PU159

716746

71
72

02154

73 gaie6a

_FADD:

P16746

gogred

86
87
88

pogRa3e

JA' TO STACK

IFORM

SP
(SP)+,R00T1

JFORM
;SAVE

2,4A

CRB*SORT)/(Z $A)

RESULT

(SP)+,R00T1+2

po204 90002 AZERO:
.

pO226

pe212
20216
gp2e2

TEMPL
TEMP2:

CONST;:

ROOTL:

IFORM sB+SQRT

CONST#2,=(SP) 12,8 10 STACK

Ag'(SP)

P16746

gp226
pa232 $40402
pa234 gogoaa
89 BB236
90

TEMP2,%(SP)

A$2,={SP)

216746

83
84

JSQUARE ROOT TO STACK

CONST,=(SP)

gapese

gegr22
74 2164 775026
75 gniéé p75236
76 RA17@ #12667
geR042
77 po174 012667
pApo4r
78 po2ae gopdge DONE?
79 902082 Poo208 IMAG!

TEMP2#2,%(SP)

JEXTERNAL SUBROUTINE

SQRT
102

JROOM

FOR

STACK

JSTART OF STACK

STACK

go442

- gapegy’

2-10

IS TOP OF AREA

CHAPTER 3
THEORY OF OPERATION
ThlS chapter descrrbes KE11-E and KEll -F theory of operation with the EIS prmcrples descr1bed first followed by
those principles applying to the FIS hardware. A review of the basic requirements for the operations is presented as
well as the algorithms for those operations. Each algorithmic description is first given in basic terms, followed by a
|

more specific treatment of the operation involved.
3.1

KE11-E EXTENDED INSTRUCTION SET

The KE11-E Option is used for fixed-point operations in the KD11A Central Processor The prrncrples 1nvolvedin

these instructions are given in the following paragraphs.
3.1.1

Binary 2’s Complement Notation

The KE11-E Option requires a numerical notation that expresses both the sign and the magnitude of each number in
binary digits. The simplest class of notation that meets this requirement is based on the followmg property: a
number added to its own negative equals 0. Thus, adding the negative of a number to another numberis the same as
subtracting the number. The 2’s complement of a number is created by complementing and incrementing the
number, i.e., replacing each 0 bit with a 1 and each 1 bit with a 0, and then adding a 1 to the resultant numberin the
least significant position. Adding a number and its negative in 2’s complement notation always produces all Os (the
only representatron of the quantity O in 2’s complement)

It is 1mportant to remember that the representatzon of a number drffers greatly from quantity represented For
example: the quantity-1 is represented in 2’s complement notation by 11 111 111 (in eight bits). The quantity +1
has a 2’s complement representation of 00 000 001.
Example 1

Adding +1 to -1 yields the following:
00 000 001 = +1
+11 111111 =-1

100 000 000 =0

(The left-most (carry) bit is not a significant bit and is ignored.)

Example 2

Adding +5 and -3 yields the following:
00 000 101 =45
+11 111 101 =-3

100 000 010 =+2

(Carry bit not significant.)

A disadvantage of 2’s complement notation is that the representation of numbers is not symmetrical. That is, one
more negative number than positive number can be expressed In n bits, the maximum positive number that can be

expressedis ot , but the maximum negative numberis -1 (because thereis no negative 0).
3-1

3.1.2

Multlphcatlon

Multiplication is repeated addition. Multiplying 3 times 7 is srmply adding 7 three times. However, 2'° times a
number requires 2' ° additions (the KE11-E uses a short-cut method that requires only 16 operations).

In practice, the KE11-E adds multiples of the multiplicand. The multiples are formed by shifting. Each time a binary

number is shifted one bit to the left, it is multiplied by two; thus, if it is shifted 5 places to the left, it is multiplied
by 2° (32). The multiplier is broken down into 1nd1v1dual bits that determine which multiples of the multiplicand
are added to form the product.

The multiplication process is complicated by tiic representation of negative numbers used in the PDP-11 Systems.
Negative 2’s complement numbers cannot be multiplied by the addition of multiples unless a correction step is
added at the end. To avoid this step, the KE11-E uses a method that provides for negative numbers and produces the
same results as the addition-of-parts method for positive numbers. This methodis based on a dlfferent breakdown of
a binary number into positive and negatrve parts

In binary numbers, 10-1=1. Representing each 1 bit of a binary number as the difference between that bit and the
next most significant bit produces a string of alternating positive and negative powers of 2.
For example:

1101011 1=100000000- 10000000+ 10000000~ 1000000+100000~10000
+1000-100+100-10+10-1

=100000000-1000000+100000-10000+1000-1

Multrplymg a multiplicand by each of the numbers in the last string (preserving the signs) and then addmg the
products of the multiplications is equivalent to multiplying the chosen multiplicand by the original number
(11010111). This can be done by shifting the multlphcand left and adding or subtractlng at each pos1tron that
corresponds to one of the numbers in the series.

The series
of alternating positive and negative powers of 2 is easily generated because:

a.
"

Each pair of powers of 2, one positive and a smaller negative, represents a string of 1s. The positive
number is one digit higher than the most significant 1 in the strrng, and the negatwe number is in the
same position as the least significant 1 in the string.
For example, in the number 11010111:
100000000~ 1000000=11000000
100000~

10000=00010000

10000~

1=00000111
11010111

Strings of 1s are separated by strings of Os. Each string is one or more digits long.
For example, in the number 11010111:

~1000000+100000=0X 25
-10000+ 1000=0X2°
11010111

3-2

Thus, each string of 1s can be replaced by a string of Os with a -1 in the least significant place, and each

string of Os can be replaced by Os with a +1 in the least significant place.

Replacement:

1
-1

-1

Original digit:

For example, the digits in the number 11010111 can be replaced as follows:
-1

Therefore, if for any bit of the multiplier the previous (less significant) bit is the same, the multiplicand

is not added to the partial product (or it is multiplied by O and O is added to the product). If the

previous bit is a 1 and the current bit is a 0, the multiplicand is added; if the previous bit is 0 and the

current bit is 1, the multiplicand is subtracted (negated and added). In each case the multiplicand is
shifted (with respect to the product) before the addition, because the number added to the product is

actually the multiplicand multiplied by some power of 2.

For example, to multiply N by 11010111, the sum of the products of N times each replacement digit,
)

times the appropriate power of 2, is the product as follows:

NXl1010111=NX(OX27—1X26+1X25—1X24+1X23+O><22+0X2‘—1X2°)
3.1.3

Division

Division is repeated subtraction. Division is more complicated than multiplication for two reasons:

The product of two integers is always an integer; the quotient of two integers is rarely an integer.
Division produces two results, a quotient and a remainder, that interact. The correct quotient is
|
«
|
dependent on a correct remainder.

The maximum value that results from the multiplication of two numbers can be no larger than the
source of the maximum number. However, the maximum value that can result from a division is infinite,
because the divisor can be much smaller than the dividend. Some quotients cannot be expressed in the
number of bits available in the physical representation and are considered to have overflowed.

The quotient in a division is the number of times that the divisor can be subtracted from the dividend without going
beyond O (changing sign). The result can be determined by counting subtractions until the remainder does go
beyond O (which produces a condition called underflow), then reducing the count by one. The remainder must also
)

be corrected by restoring the value of one subtraction.

Rather than do as many as 2'5 subtractions, the KE11-E uses a short-cut method similar to that used in

multiplication. The results of dividing by multiples of the divisor, where each multiple is a power of 2 times the
,

divisor, can be combined to form the quotient.

If the
This division procedure operates by subtracting a large multiple (2“"1) of the divisor from the dividend.

remainder does not go beyond O (there is no underflow), the next smaller power-of-2 multiple of the divisor is

subtracted. For each successful subtraction, the quotient is increased by the same multiple (the same power of 2) as
-

the multiple of the divisor used in the subtraction.

If a subtraction causes underflow, however, the corresponding quotient bit is cleared (the corresponding power of 2
is not added to the quotient). However, rather than restoring the previous value of the dividend, the KE11-E now
approaches the correct remainder from the opposite direction. Successively smaller multiples of the divisor are added
to the remainder (instead of subtracting) until the remainder again underflows, thus restoring the original sign. When
the KE11-E is adding, instead of subtracting, the corresponding quotient bits are set only if the sign of the remainder
returns to its original value; if the remainder does not change sign, the quotient bit is set to 0.

3-3

For example, dividing 17 (21g) by 5 yields a quotient of 3 and
a remainder of 2 as follows:

Subtract divisor X 23 from the dividend.
00010001 = 215
11 011000 =-5 X 2% =-504
11 101 001 (The partial remainder has the wrong sign, underflow occurred.)

Add0 X 23 to the quotient = 0.

3. Add divisor X 2* to the partial remainder.
11101001

00010 100=5 X 22 =245
11111 101

(The partial remainder has the wrong sign, no underflow.)

'Add 0 X 22 to the quotient = 0.

Add divisor X 2! to the partial remainder.
11111101

00 001 010=5 X 2! =125
00000 111 (The partial remainder has the right sign, underflow occurred.)
6.

Add1 X 2! to the quotient= 2.

Subtract divisor X 2° from the partial remainder.
OO 000111

11111011 =-5X2° =—5
00 000 010 (T he remamder has the nght sign andis 2 no underflow )
8.

Add1X 20 to the quotlent 3.

- This procedure is valid for posmve or negative numbers, prowded that the d1V1dend and d1v1sor have the same sign.
- However, if the signs are originally different, subtracting multiples of the divisor drives the remainder away from O.
Therefore, the KE11-E adds multiples of the divisor until the remainder underflows (at which point, a quotient bit is
set) and then subtracts until the remainder regains its original sign.
NOTE

In the KE1 l-E if the dividendis negative, its 2’s complement
is taken before dividing. Adding the 2’s complement is the
|

same as subtractlng

This procedure can handle any combination of binary numbers, regardlesscof sign. Implementation of the procedure

is s1mp11fied by the following considerations:

a. - If the signs of the divisor and the d1v1dend are ongmally the same, the KE11-E subtracts until they differ
- (because the sign of the remainder changes), then adds until they are the same. If the signs are originally
different, the KE11-E adds until they are the same, then subtracts until they differ.
-

._Therefore for each operatlon the KEll-E compares the signs of the remamder and d1v1sor If they

differ, the KE11-E adds the divisor, shifted to form the proper multlple (power of 2 times the divisor); if

the signs are the same, the KE11-E subtracts.

A quotlent b1t is set if the s1gn of the remamder remains the same after a subtractlon or changes after an

addition; the quotient bit is cleared if the sign changes after a subtraction or remains the same after an
addition.

A subtraction is done if the signs of the remainder and divisor are the same, and an addition is done if
the signs are different. A changed sign after an addition means that the signs are now the same, while no
change after a subtraction also means the signs are the same.

. Therefore, after each operation, the corresponding bit of the quotient is set if the signs are the same or
cleared if the signs differ.

3.1.4

Basic Shift Operation

In the KE11-E, a basic shift operation is used as a primary operation in the sequences for all other operations. The

register that is being shifted is treated as a sequence of bits, each shifted separately. The following descriptions
illustrate the features of a basic shift:

In general, the bit at a particular location is replaced by another bit that is shifted into that location. No

bit of information is moved more than one location.

One bit is shifted out of the register and is lost.

One bit is vacated. The original contents of that -bit are shifted to the neXt bit, and a O replaces the

prewous bit 1f shlftmg left.

The bit lost is at the end toward Wthh the bits are shifted, and the bit vacatedis at the end away from

which the bits are shifted (bit positions are numberedin ascending order from right to left).

3.1.5 Algorithms For KE11-E Operations
Figures 3-1 through 3-4 illustrate the sequence of operations for multiplication, division, and shifting. These flow
charts emphasize the conceptual organization of the device that does each calculation. Chapter 4 relates the KE11-E
logic to these algorithms and explains how the logic structure reduces the hardware and timing requirements. All
KE11-E arithmetic operations are performed in the 16-bit ALU in the PDP-11/40 Central Processor KD11-A. This
ALU has two 16-bit inputs. The B input is supplied (for the sake of the following discussions) by the B Register. The

- Alinput is supplied by all of the following sources:

The CPU general registers (175 — 008)

The KE11-E registers BR, DR, and (BR (14 00) DR15)

The KE11-E also supplies a carry-in signal to bit O of the CPU ALU. The BRis simply a holding reglster whereas the
DRis a left/right shift register.

The ASH right operation is implemented by the right data port of the CPU DMUX. Similarly for ASHC the high half
of the operand is shifted by the DMUX while the DR shifts the low half of the operand.

The high half of the operand for ASHC left and the entire operand for ASH left are shifted by the ALU function A
plus B, while the low half of the ASHC operand is shifted by the DR Register.

3-5

In MULtiplication, the DR holds the multiplicand and, therefore, controls the summation of partial products; as the

multiplicand is shifted out, the low order word of the productis shiftedin. In DIVision, the DR holds the low order
dividend, and is used to assemble the quotrent, as the drvrdend 1_s being shrfted out, the quotrent is bemg shiftedin.
3.1.5.1

Multiplication — As shownin Figure 3-1, as the flowis entered at MUL, the multrplrcandis loaded, as is the

Step Counter, and the C bitin the Extended Processor Status Regrsteris cleared

'LOAD MULTIPLIER.
LOAD STEP COUNTER.

EPS(C) < 0

MULTIPLIER

=100000?

SWAPMULTIPLICAND

I LOAD MULTIPLICAND ]

& MULTIPLIER.

MULTIPLICAND

YES

DR00(1), EPS(C)(0) Ao& DR0O0(0), EPS(C)(1)
“

EPS(C)=?

]

PARTIAL PRODUCT —
MULTIPLIER. SHIFT

PARTIAL PRODUCT

RIGHT. EPS(C)—~ DROO |

DECREMENT COUNT.

SHIFT

PARTIAL PRODUCT +

PARTIAL PRODUCT -

MULTIPLIER. SHIFT

RIGHT. EPS(C) — DROO

PARTIAL PRODUCT

'DECREMENT COUNT.

RIGHT. EPS(C) « DR0OO

DECREMENT COUNT.

.
SPECIAL CASE

GENERATE & STORE
RODUCT

(

040000, 000000

‘

)

COUNTER=0?
NOTE:

EPS(C)=LOCALC

BIT. DROO = LSB OF

- MULTIPLICAND.

STORE PRODUCT

SET LOCAL CONDITION

CODES

;

TRANSFER LOCAL
CONDITION CODES TO
CPU STATUS

(

'DONE

)

Figure 3-1 KE11-E MUL Algorithm
36

‘11'-1608

At this point, a test is made to determine if the multlphcandis equal to 100000 (the most negatrve number) Ifitis

not, the multiplier is loaded and the multiply loop is entered; if it is equal to 100000, the multrpher and

multiplicand are swapped and the multiplieris tested to see if it is the most negative number If the multiplierproves
to also be the most negative number, a special case exists in which the answer can be generated The product is
stored, local condition codes are set and transferred, and the operation is done.

If the multiplier is not the most negative number, the multiply loopis entered as above. At this point, the hardware

looks at the two least significant bits (DROO and EPS(C)) to decide whether to either add or subtract and then shift,
or to just shift. In all cases, DROO is sent to EPS(C)as the hardware executes the loop. This action continues, each
time testing to see if the Step Counter is equal to 0. When it is, the operation in the loop is complete. To conclude
the operation, the loopis left, the productis stored, and local condition codes are set before being transferred to the
|

CPU Status Register.

In the KE11-E hardware, the multiplier (the contents of the calculated destination address) is in B and the

multiplicand (from R(SF))is in DR. BR and EPS(C) are clear.

If DROO (the LSB of the multrphcand) is (1), B is subtracted from BR. The result, shifted one place to the right, is
loaded back into BR with the LSB of the result shifted into DR15. The DR is shifted right so a bit of the
multiplicand is shifted into EPS(C). The sign of the resultis loaded into BR15 and BR14. If DROOis (0), the BR and
DR are shifted right one place, with BROO being shifted into DR15. The BRis shifted by the DMUX rlght data port.

In each subsequent step, only the shlft is performed if the bits in DROO and EPS(C) are the same. If they are
different, addition or subtraction is performed along with the shift. If DROO= (O) and EPS(C)= (1), Bis added to
= (1) and EPS(C) =0, Bis subtracted from BR.
BR. If DR0OO

Consequently the low order bits of the running sum of the partial products are shifted into DR as the multiplicandis

shifted out. At each step,-the effect of the multiplier in B on the partial sum in BR15 is binarilly one order of
magnitude greater than in the preceding step because the partial sum was shifted right. B can consequently be
combined directly with BR. The first arithmetic operation will always be subtraction. If DROO is initially (0), no
subtraction will be performed until a (1) is shifted into it. Sh1ft1ng will then continue until DROOis (0) and EPS(C)
is (1).

This process continues, subtractlng when DROOis (1) and EPS(C)is (0) adding when DROOis (0) and EPS(C)is (1),
and simply shrftmg when DROOis the same as EPS(C)

After 16 steps the DR holds the low half of the productand the BR holds the h1gh half of the product
The followmg example shows that the above procedure produces the correct product.
10011001= Blnary Integer

7654321 0=Powers of 2 for each position

This number is equal to

)

10000000
+
11000
+

A string of 1s whoseI1%ht-most bit corresponds to 2K s equal to pk¥n_ok o equivalently 2k(2n—20), ie., 20~ 20 isa
string of n 1s and the 2% shifts the string left k places. Therefore,

=28-27
10000000=2771-27
11000=23%2-23 =25-73

1..21'*'0 20_21 20

28 27+25 23+21 20

In the last representation, each power of 2 thatis subtracted correspondsto a transition from (0) to (1) (from right
to left) whereas each power of 2 thatis added corresponds to a(1) to (0) transition. The largest term corresponds to
the transition to. the sign bit, which is (0) for a positive number. The multiplication algorithm interprets the

multrphcand in the above manner, alternatrvely subtractmg and addrng the multrpher to the partial sum 1n the
order-of-magnitude positions correspondrng to the transrtrons

3.1.5 2 D1v1s1on — As shown in Frgure 3 2 as the flow is entered at DIV the drvrsor dividend, and step count are |
all loaded. At this point, a test is made to determine ifthe divisoris equal to 0. If it is, the local condition codes are
set to mdlcate the error, they are transferred to. the.CPU Status Regrster and the flow ends at that point.

LOAD DIVISOR, LOAD- |
1S

DIVIDEND. LOAD STEP

‘COUNTER.

'REMAINDER

CORRECT?

DIVIDEND

NEGATIVE?

=07

CORRECT REMAINDER

YES

DIVISOR

—

2SCOMPLEMENTOF |

- DIVIDEND

(SIGN & VALUE) -

NOTE: SIGN OF
REMAINDER MUST BE

. L STORE REMAINDER ] ~ SAME AS DIVIDEND

DIVIDEND

IS s

=1000007

OF QUOTIENT

(DIV QUIT)
'

CORRECT?

2'S COMPLEMENT OF
QUOTIENT

NEGATIVE

SHIFT DIVIDEND LEFT

SHIFT DIVIDEND LEFT
DIVIDEND + DIVISOR

. POSITIVE - ~

STORE QUOTIENT

DIVIDEND ~ DIVISOR

I E.
'

R “SET LOCAL CONDITION | - '

CODES

'
{

‘NO

‘

UNDERFLOW

SET LOCAL CONDITION

CODES TO INDICATE

‘|

’

ERROR

CODES TO INDICATE

QUOTIENT WOULD BE
TOO LARGE

‘

DROO# B15

DRO0 = B15

TRANSFER LOCAL
,

SHIFT DIVIDEND LEFT
DIVIDEND + DIVISOR

CONDITION CODES TO

CPU STATUS
l

SHIFT DIVIDEND LEFT
DIVIDEND - DIVISOR

COUNTER

=07

Figure 3-2

KEI11-E DIV Algori’thm_._‘

3-8

11-1609

If the divisor is not equal to 0, a test is made to see if the dividend is negative. If it is not, the flow continues to test

the sign of the divisor, but if it is a negative dividend, the 2’s complemeritistaken of it to determine if it is the most
negative number (=100000). If this condition exists, divisionis impossible and the DIV QUIT pathis taken to set the
local condition codes to indicate that the quotient would be too large. The codes are then transferred to the CPU
and the flowis ended.

If, however, after 2’s complementing the dividend, it proves not to be the most negative number, the flow continues
to test the sign of the divisor as above. This is the first division step; and, if the divisor is negative, it is necessary to
add it-to the dividend since adding a negative number is equivalent to subtracting a positive number. But if the
- divisoris positive, itis simply subtracted. Before either the add or subtract operatron however the dividendis shifted
left.

At this point, the hardware is caused to look for the result of this initial add or subtract operation as indicated by
the presence of or absence of a carry-out from the ALU. If a carry-out is not seen, this indicates that the scaling of
the dividend vs the divisor will produce the proper number of bitsin the quotient. If acarry-out is seen (underflow),
however, it indicates that more than 16 bits are required to display the answer and the DIV QUIT pathis taken to
»

set local condition codes before they are transferred, and the flowis terminated.

If the first division step does not produce an underflow, the division loop is entered and the operation continues. In
the divide loop, two conditions are monitored for each pass through the loop.These conditions are DROO (which

represents the carry-out result of the last pass through the loop), and B15 (the sign of thedivisor). This test is made

for each pass through the divide loop, up to the number set in the step count. Each pass, the two bits are sampled
and the appropriate action taken. If the divisor is indicated as being negative and a carry--out was detected for the
last pass, the indication is that too much was either added or subtractedin that last step, causing the reverse action
to take place in the currrent step. This continues until the step count reaches O at whrch time the loop is left and
the flow contmues

At thrs pomt in the flow, a test is made to see if either the 81gn or value of the remarnder is mcorrect This is the
fix-up step in which the sign or value of the remainderis corrected. The sign of the remainder should match the sign
of the dividend. Once done, the remainder is stored and the sign of the quotient is tested for correctness. If it is
incorrect, the 2’s complement of the quotient is taken and, in either case, the quotient is stored.
The flow endsin the usual manner with the local condition codes berng set and transferred
In the KE11-E hardware, the divisor (the contents of the calculated destmatron address)is in the B Regrster The BR
and DR hold the high and low dividend, respectively. If the dividend is negative, the 2’s complement is taken and
loaded into BR and DR.

Before the division processis initiated, a check for the divisor being 0 is made. If a 0 divisoris detected, the division
»

1s aborted with the condition codes (Z, V, C) set to 1nd1cate the error.

The first step of division is performed so that a test for underflow may be made to determine if the quotient is too
large to be expressed in 16 bits. If underflow does not occur, the instruction is aborted. If not, the remarmng 15
»

division steps are performed

Note that the dividendis shrfted left one place before each addrtlon or subtractron dropprng the current MSB of the
dividend. As the dividendis shifted out, the quotient is shiftedin.

The test for underflow that determines whether theALU should add or subtract is based on the following
considerations:

If the divisor is negative and the dividend is positive, adding the divisor to the dividend should produce a

result closer to O than the original dividend. If the result is negative, underflow has occurred and a 0 is

shifted into the DR.

3-9

If the divisor is negative and the dividend is also negative, an underflow condition already exists. The
divisor is subtracted from the dividend to return the dividend to a positive number. If the result is still
‘negative, a 0 is shrfted into the DR; if the resultis positive, the underflow has been corrected and a 1 isshiftedin.

For a positive divisor and dividend, a subtractionis performed. If the resultis posrtlve alis shrfted into
the DR, but if the result is. negatrve underflow has occurred anda 0 is shiftedin.

If the divisor is positive and the dividend is negative, an addition _is performed to correct.an existing-.'
underflow. If the result is positive, the underflow has been corrected and a 1 is shifted into the DR,

otherwise a O is shifted in.

or if
As a result of these considerations, if the divisor is positive (B15 is 0) and there is no underflow (DROO is 1),
the divisor is negative (B15 is 1) and there is underflow (DROO is 0), the KE11-E performs a subtract operation and
shifts the carry-out of the ALU into DR0O. A carry-out of the MSB of theALU indicates that no underflow has
occurred; if an uncorrected underflow existed, the carry indicates that it has been corrected.

If the opposite conditions exist (d1V1soris positive and DROOis O or d1v1soris negatrve and DROO is 1) an additionis
performed, followed by a shift of the carry-out of the ALU into DR0O. Note that the cases for Wthh a carry-outof
the MSB of the ALU exrsts are equrvalent to the cases described above for whrch DROOis- set

If, after the last division step, the LSB of the quotient is a 0, an underflow condition still exists. This condition can
be corrected (unless an overflow condition also exists) by adding a positive divisor or subtracting-a negative divisor
to correct the remainder. If no remainder correction is needed and the remamder has the wrong srgn or has the
wrong srgn after correctron the remamderis complemented and stored

is negative because the
If EPS (N) is set, the original dividend was negative. The complemented remainder, which
corrected remainder is positive (if all underflow conditions are corrected), is stored as the final value of the

remainder. If both the dividend and the divisor were positive, the quotient, which is also positive (the most

significant bit of the quotient must be positive or an 1mmed1ate overflow condition aborts the division), is written

into the appropriate general register.

Similarly, if both dividend and divisor are negative, the quotient should be positive andis written in its present form.
If the original signs of the dividend and divisor were different, the quotient should be negative. One special case 1n_
which the quotient is the most negative numberis considered an error.

3.1.5.3 Arithmetic Shift — As shown in Figure 3-3, as the flow is entered at ASH, the Shift Couhter is loaded with

the number of bit posrtrons to be moved (1f any). A test is then made to determrne the direction of shrft or whether
no shift will occur at all.

If no shift is called for (no count set in the Shift Counter), the local condition codes are set and transferred to the
-

CPU Status Register as the flow concludes.

If a shift left is called for, the operand is shifted left one bit position, stored and the count incremented. This repeats
until the shift count is exhausted, at which time the local condition codes are set and transferred.

3-10

LOAD SHIFT COUNTER ]

LEFT

SHIFT

|
|

SHIFT OPERAND LEFT |

—

NOSHIFT

& STORE. INCREMENT

COUNT.

RIGHT

DmEcT/KV

—
:

SHIFT OPERAND RIGHT
& STORE. DECREMENT

COUNT.

SET LOCAL CONDITION
CODES

»
'

TRANSFER LOCAL
CONDITION.CODES
TO
CPU STATUS

1H-1610

Figure 3-3 KE11-E ASH Algorithm

If a right shift is called for, the opp051te occurs with the shift count bemg decremented on each pass through the
loop

In the KE11-E hardware, the operand to be shifted is in R(SF) and is sent first to the D Register and from there to

both the BR and to a precleared B Register. The contents of BR (05:00) determines the direction of shift. I these
contents are greater than 0, the shift will be to the left. If they are less than 0, a right shift is called for. If they are 0,
'no sh1ft1ng will occur. Setting of condltlon codes for transferralis 1mplemented 1dent1cally to MUL and DIV
3.1.5.4 Arithmetic Shift Combined— As shown in Figure 34, as the flow is entered at ASHC 1t can be seen that
the flow is similar to the ASH flow except that in this case the hardware is dealing with 32 bits instead of 16. The
Shift Counter is loaded from the least significant 6 bits of the source operand and the lew shlft operand is sent to
“the shift reglster

As in ASH, the value of the shift count with respect to O is tested to determine right
or left shift. If a right shift is
called for, the operand is shifted right one position and the partial high answer is stored while the count is
decremented for each pass through the shift loop until the shift count is exhausted. For the left shlft cond1t1on the
count is incremented; for the rlght shift, it is decremented for each pass through the loop.

‘When the shift count is exhausted for either loop, the low answer is stored (the high answer is already stored) the
cond1t10n codes are set, transferred to the CPU Status, and the flowis terminated.

LOAD. SHIFT COUNTER
LOW SHIFT OPERAND TO
SHIFT REGISTER

SHIFT

LEFT

—

"RIGHT

DIRECTION?
- -

{

NO SHIFT

‘

&
SHIFT OPERAND LEFT

e
-

STORE HIGH ANSWER.

INCREMENT COUNT.

&
ISHIFT OPERAND RIGHT
|STORE HIGH ANSWER. .

IDECREMENT COUNT.

SHIFT

COUNT =0?

l STORE LOW ANSWER l i

'SET LOCAL CONDITION

copes

TRANSFER LOCAL
\q@//

CONDITION CODES
TO
CPU STATUS

DONE

4)
I1-16il

Figure 34 KE11-E ASHC Algorithm

In the KEll -E hardware the contents of the regrster des1gnated by the source field (R(SF)) and that reglster ORed
~ with one (R(SFV1)) are loaded into the BR and DR Registers concatenated such that the high operandis in the BR
and the low operand is in the DR. These are then shifted until the count is exhausted, at which time the low answer

“is storedin the odd register and the high answer is already storedin R(SF) by the shrftmg action within the loop.
Settmg condrtron codes and transferralis 1dent1ca1 to ASH

35 KE1LF FLOATING INSTRUCTION SET
The KE11-F Option is used for floating-point operations in the KD11-A Centeral Processor. The principles involved

~ in these instructions are given in the following paragraphs.

321

Pohsh Mode

In the KE11-F, floating operations take place on the top of a hardware stack by whatis termed Polzsh Accumulator
" Technique. This techniqueis based on a form of mathematical notation developed by the Polish logician
Lukasiewicz. The procedure allows complex logical expressions to be statedin a nonambiguous manner without the

312

necessity of relying on hierarchical delimiters such as parentheses. Its use in the KE11-F greatly simplifies scanning
mechanisms. By determining interrelationships between operands in various mathematical operations, Lukasiewicz’s
technique allowed rearrangement of terms so that ordering of operands on the stack minimized the number of
operations required to achieve the desired mathematical result. Operations could then be performed in sequence
with intermediate results being stored automatically by the stack, then used in the next sequential operation until
calculation was complete. Without this scheme, each equation term would have to be calculated separately, stored,
|
‘
then called for use in sequential steps.

Polish notation permits the writing of algebraic or logical expressions in a manner that eliminates the need for
grouping symbols and conventions as to operator precedence.

In the expression X(Y+Z), the parentheses are necessary so that the reader (or interpreting device) can understand

the grouping intended, and the precedence of operations to be performed.

Certain operators have precedence over others. For example in the expression X+Y/Z, the divide operator (/) is
‘\.nflw‘,/’

understood to have higher precedence than the add operator (+) so that it is understood that the operation is to be
a

interpreted as X+(Y/Z) rather than (X+Y)/Z.

In right-hand Polish notation, the operators are-located to the right of the operands. For example, the expressidn

X+Y is written XY+. Similarly the expression X+Y+Z can be written either as XY+Z+ or XYZ++. In this latter
example, the first add operator adds Y and Z while the second adds X to that sum.

In Polish notation, the following juxtapositions can be made to basic logical expressions:

Polish Notation

Basic Expression

X(Y+7)

X+Y/Z

Q=X(Y-Z)/(R+S)

Either YZ+XX, or XYZ+X

Either YZ/X+, or XYZ/+

XYZ-XRS+/Q=

The last listing is an example of how Polish notation can be used to reorder many variables.
3.2.2 Floating-Point Arithmetic

Floating-point representation of a binary number consists of three parts; a sign bit, an exponent, and a mantissa. The

mantissa is a fraction in magnitude format with the binary point positioned to the left of the most significant bit of
the mantissa. All mantissas are assumed to be normalized; therefore, all leading Os are eliminated from the binary
e are assumed to be normalized, the
all mantissas
representation. The most significant bit is thus a logical 1. Sinc
MSB, which will always be a 1, is not stored because it is redundant. Leading Os are removed by shifting the mantissa
left; however, each left shift of the mantissa must be followed by a decrement of the exponent value to maintain the

s power of 2 by which the mantissa is multiplied to
the
true value of the number. The exponent value represent
number in floating-point notation and then the same
unnormalized
an
shows
3-5
obtain the value to be used. Figure
number after it has been normalized.

3.2.2.1 Floating-Point Addition and Subtraction — For floating-point addition or subtraction operations, the

“exponents must be aligned or equal. If they are not aligned, the mantissa with the smaller exponent is shifted fight
until they are. Each shift to the right is accompanied by an incrementing of the exponent value. When the exponents
are aligned or equal, the mantissas can be added or subtracted, whichever the case may be. The exponent value
indicates the number of places the binary point is to be moved to obtain the actual representatiofn the number.

24 BITS

OF UNNORMALIZED MANTISSA

'ro‘OOO'O"01‘011‘11001'11-'000‘0001]
|

BECOMES

{

EXPONENT=00

100

{

]

O11

24 BITS OF NORMALIZED MANTISSA(SHIFTED 6 PLACES TO THE LEFT)
.

_°

!tt

HIDDENT ! O ¢

00 4 4 1 000000 10 '0-.0,0 o o.]»

EXPONENT= 00

011

101

’

(ORIGINAL EXPONENT DECREMENTED 6 TIMES)
23 BITS OF NORMALIZED MANTISSA

HIDDEN 1
REMOVED_"O',‘
22

SIGN

EXPONENT

l'x oo o1t 1
]

1loo 1|1

R
.
i ooooloo1looolooo]
|

EXPONENT=00 011 {101

HIGH MANTISSA

{+{o0o1lo1 ¥ 1+t
|

0Ol

0
HIGH ARGUMENT

AS‘STOR:_ED (16 BITS)

]

OO0 OOOOIYT
|

|
_

LOW MANTISSA

OO0OO0OTO0OTO o
-

LOW ARGUMENT

AS STORED (16 BITS)-

NOTE

Mantissa becomes 24 bn'fs cfter hldden {is inserted by the hardware.
1H-1612

Figure 3-5

Floating-Point Representation

In the example below, the number 7,, is added to the number 40,,, using floating-point representation in
binary-octal notation. Note that the exponents are first aligned and then the mantissas are added; the exponent value
dictates the final location of the binary point.

40,, =505 =0.101 000 X 26

+ 7,0 = 75 =0.111 000
X 2°
a.

To align exponents, shift the mantissa with the smaller exponent three places to the right and increment
.

‘the exponent by 3.

- 4010—508--0101000><26 |
+ 7,0= 75=0.000111X26
710=575 =0.101 111 X2°

Move the binary point six pla_cés fQ the right_.w |

2. 1,

0.101 111.

3222 FloatmgPomt Multlphcatlon and D1v1sxon — In floating-point multlphcatlon the mantissas are multlphed
and the exponents are added. For floating-point division, the mantissas are divided and the exponentsare subtracted

There is no requirement to align the binary point in the floating-point multiplication or division.

3-14

In the followrng example, the number 7,4 is multrphed by the number 510 An 8-bit register is assumed for
srmphcrty

710 =75 =0.1 110000 X2°
xao-sg-orounmoxf
00000000

1110000
0
1110000

X 2°¢
0.10001100000000
Move the binary point six places to the right.

35,¢ =435 =0.100011,00000000

3.2.3

Algorithms for KE11-F Operations

| Figures 3-6 through 3-10 illustrate the sequences of operation for the floating-point operatrons Note that to
~

complete its function, the KE11-F hardware utilizes much of the KE11-E hardware
‘

’

FiS

| FETCH A ARGUMENTJ

| FETCH B ARGUMENT I

DISASSEMBLE HIGH

WORD OF B ARGUMENT

‘

WORD OF A ARGUMENT |

SAVE A EXPONENT IN
SCRATCH PAD REGISTER

SAVE B EXPONENT IN
SCRATCH PAD REGISTER

INSERT HIDDEN 1IN HIGH

INSERT HIDDEN 1IN HIG

PART OF B MANTISSA

PART OF A MANTISSA

B EXPONENT

A EXPONENT

=0?

GENERATE ZERO A

GENERATE ZERO B

ARGUMENT (SIGN,

‘

EXPONENT, MANTISSA)

HICH

INSTRUCTION
IS BEING

EXECUTED
2

=)
Figure 3-6

o T

Floating Entry Algorithm

3-15

[-1613

When a floating instruction is executed the flow is entered at FIS (Figure 3-6). The B argument is fetched from

core, high B first and then low B. The high B argument consisting of sign, exponent, and high mantissa is then

disassembled separating the sign, exponent and mantissa. The exponent is saved in the low byte of one of the

Scratch Pad Registers.

As previously stated, all mantissas are assumed to be normalized, meaning that the most 31gn1flcant b1t of the

mantissa is always a 1. Therefore, the MSB (referred to as the hidden 1) of the mantissa is not storedin core. This

hidden 1 is now reinserted into the mantissa.

Next, a test to determine if the B exponent is equal to 0 is made. If it is 0, a clean O is generated as the B argument

(sign, exponent, and mantissa).

The A argument is now fetched from core and the same procedure described aboveis followed A test is now made

to determine which floating instruction is to be executed.

3.2.3.1 Floating-Add and Floating-Subtract— As shown in Figure 3-7, the floatmg subtract flow enters at FSUB

and immediately complements the sign of the subtrahend. From that point on, it prooeeds as in floatmg add. Thisis

mathematically valid since adding the negative of a numberis identical to subtracting it.

The floating-add flow is entered at FADD. A test is then made to see first
if the B Addend is negative and then if the

A Addend is negative. If either or both are, the 2’s complement is taken of either or both.

The A exponent is subtracted from the B e.XpOrlent and a test is made
to see if the B exponent is equal to or greater
so that the mantissa with the smaller exponent is in position to be shifted later to align the binary points. Since there
are only 30g bits of mantissa, an attempt to align binary points by shifting the smaller mantissa right more than 30

than the A exponent. If it is not, then the A and B Addends and exponents must swap positions. The swap is made

places would result in that mantissa being lost. Because of this, another test is made to see if the exponents are in
range (difference <30g). If they are not in range,'the,argument with the larger exponent is taken as the answer.

If the exponents are in range (difference <308) a check is made to see if they are equal to each other. If so, A
Addend is added to B Addend next. If the exponents are unequal, then the Addend with the smaller exponent is
shifted right. This corresponds mathematically to lining up the decimal (binary) points. The larger exponent then
becomes the initial exponent of the answer. The term° 1n1t1al” exponent is used because normalization of the answer
has not as yet taken place.

‘

At this point, the A Addend is added to the B Addend. The sign of the answer is checked, and the answer is

complemented if the sign is negative. The answer is then normalized, rounded, and stored, as describedin Paragraph
3.2.3.

As stated before, floating subtract is implemented by changing sign of the subtrahend and adding.

It should be noted that there are two extra bit positions on the low end of the mantissa for rounding purposes.
These bits hold the last two bits shifted out of the mantissa when aligning binary points. One of these bitsis dropped
before going to the normalize round and store flow. It will be seen in Paragraph 3.2.3.4 that the rounding bit is
added to the remaining extra bit. The second extra bit was maintained in case the answer was negatlve When the
answer was complemented, the lower extra bit could affect the upper extra bit.

3-16

COMPLEMENT SIGN OF

SUBTRAHEND
J

7
:

)

FSUB

( |

FADD

‘

_ SHIFT ADDEND WITH

SMALLER EXPONENT
RIGHT. INCREMENT

EXPONENT.

ADDENDB -

N\,

NEGATIVE?

YES

2'S COMPLEMENT OF

VES

ADDEND A

" ADD ADDEND A TO
;

ADDEND B

NEGATIVE?

_‘

'2'S COMPLEMENT OF

apbpEnD A

ADDENDB

“

|
.

B EXPONENT MINUS
A EXPONENT

2'S COMPLEMENT OF

‘
-

B EXPONENT
>

A EXPONENT?

l |

.
ADDEND
& EXP. B

—X

CHANGE PLACES WITH

NORMALIZE

( ROUND & STORE

|
-

ANSWER

)

ADDEND & EXP. A

IS DIFFERENCE \\_

IN EXPONENTS
< 30,?

ARE

EXPONENTS'

EQUAL?

11-1614

Figure 3-7 KE11-F FADD and FSUB Algorithm
| For eXample:
Mantlssa
Negatlve Answer (uncomplemented)
(complemented)

Extra Bits

0111101
100011

Roundmg b1t added to this p0s1t10n —

It can be seen from the above example that the second extra bit can have an effect on the mantissa when roundmg
|

takes place i.e., cause a carry into the mantissa.

3-17

3.2.3.2 Floating-Multiply
— As shown inFigure 3-8, the flowis entered at FMUL and a checkis made to determine
if either argument is equal to 0. If so, there is no need to go any farther with the operation and a O answer is
generated. The local condition codes are set and the flow proceeds toSTORE on Figure 3-10.

If neither argument is equal to 0 the XOR of the sign bitsis saved and the exponents of the A and B arguments are
added to produce the unnormahzed exponent of the answer.

At this point, the step counter is loaded W1th 308 and the multiply loopis entered. In this 1oop, the state of the least
significant bit of the multiplier (MSROO) is monitored. In any pass through the loop, if this bit is a (0), both the
multiplier and the partial product are shifted right one position and the step count is decremented. If, however, on
any pass through the loop the LSB of the multipher is seen to be a (1), both the multiplierand partial product are
shifted right one position and then the multiphcand and partial product are added before decrementmg the Step
Counter.

‘

This process continues until the :count"is'"eXha'usted (each bit of the multipiier‘ has been fnonit_Oredj, at which time

the flow proceeds to the NORMALIZE, ROUND & STORE floW in Figur_e 3-10.

It can be seen from the above descnption that multiplication of the mantissas is identical to the way in which it was
taught in Grade School. The multiplicand is added to the partial product each time a 1 is encountered in the
multiplier, followed by a right shift of the partial product. For each 0 encountered in the multipher the partial
productis simply shifted right.

3.2.3.3 Floating-Divide _ Asshown
in l'j‘igure 3.9, the flow is entered at FDIV. At this point, a test is made to see if
either the divisor or dividend are équalto ‘0.' If "they are, there.is no reason to continue the -computation.

If the divisor is equal to O (divide by 0), the local cond1t1on codes are set to 1ndicate an underflow, then are
transferred to the CPU Status Word. At this point the flow terminates.

If the dividend is equal to 0, a O answer is generated, the local condition codes are set, anvd the flow proceeds to
|

STORE on Figure 3-10.

If, however, neither argument is equal to 0, the XOR of the signs of the arguments is saved, the exponents are
subtracted to produce the initial exponent of the answer, and the Step Counter is loaded. The divisor is then
subtracted from the dividend and the carry-out of the ALUis saved. Both the dividend and quotient are shifted left
one bit position as the saved carry-out is shifted into MSROO, and as the LSB of the quotient and the Step Counteris
decremented.

At this point the divide loop is entered.
In this loop, the state of the least significant bit of the quotient (MSR00) is
monitored. In any pass through this loop, if this bit is a (1), the divisor is subtracted from the dividend and the
carry-out of the ALU is saved. Both the dividend and quotient are shifted left, the carry-out of the quotient is sent
to MSROO, and the Step Counter is decremented. If, however, upon entering this loop the LSB of the quotient
(MSRO0) is seen to be a (0), the divisor is added back into the dividend and the carry-out of the ALU is saved. Once
again the dividend and quotient are shifted left, the saved carry-out of the ALU is sent to MSROO, and the Step
Counteris decremented.

This process continues until the step count is exhaustedat Wthh t1me the flow proceeds to the NORMALIZE
ROUND & STORE operation describedin Paragraph 3.2.3 4

Note that division of the mantissas is also identical to the method taught in Grade School. The divisor is subtracted
from the high part of the dividend and, if the divisor was smaller than or equal to the portion of the dividend being

subtracted from, a1 is shifted into the answer. The quotient and dividend
are then shifted left.
If the divisor was

larger than the dividend, a O is shifted into the quotient. Since the hardware cannot look ahead to determine how
many places the dividend must be shifted left before the next subtraction will be successful, the divisor will be added
back into the dividend until the dividend is larger than or equal to the divisor and then a 1 will be shifted into the
answer.

3-18

(

FDIV

)
|

DIVISOR

DIVISOR =0

DIVIDEND = 0

OR DIVIDEND

NORMALIZE

ROUND & STORE )

STORE

=0
?

MANTISSA

DR09 =1

NORMALIZED?

;

EITHER

ARGUMENT
=0?

SET LOCAL CONDITION

YES

SAVE XOR OF SiGN BITS |

CODES TO INDICATE

UNDERFLOW (DIVIDE BY

‘

ZERO)

CODES

P'OAD STEP COUNTER 3°8I
.

REEI

‘

CPU

LSB (MSR00)

SHIFT DIVIDEND LEFT.

SHIFT QUOTIENT LEFT.

MANTISSA

NORMALIZED?

DECREMENT STEP CTR.

=10R 0?

ROUND MANTISSA

IS
MANTISSA

LSB (MSROO)

NORMALIZED
?

=10R 02

SHIFT MULTIPLIER RIGHT

SHIFT PARTIAL PRODUCT

SHIFT MULTIPLIER RIGH
*

|RiGHT. DECREMENT STEP

COUNTER.

ADD MULTIPLICAND TO

PARTIAL PRODUCT.

DECREMENT STEP CTR.

DIVIDEND. SAVE CARRY

SHIFT MANTISSA LEFT

;

DRO9 = 1

DECREMENT EXPONENT
r

[assemBLE riGh answeR]

lisign ExPoNENT

CARRY OUT OF ALU.

‘

FROM DIVIDEND. SAVE

OUT OF ALU.

NO
DRO9 = 0

STILL

-1

OF QUOTIENT

DRO9= 1

(MANTISSA + 1)

OF MULTIPLIER

—

DECREMENT EXPONENT

DIVISOR

DR09=0

| SHIFT MANTISSA LEFT

DIVIDEND MINUS

1
'

STATUS

1
:

CONDITION CODES TO

TRANSFER LOCAL

OF A AND B ARGUMENTS.
,

ADD EXPONENTS.

CONDITION CODES
'

COUNTER
i

‘

I\Dn'lclltéz Extg;N\El\;TTg:

SET LOCAL CONDITION
SAVE XOR OF SIGN BITSS

ANSWER. SET LOCAL

EXPONENT OF DIVIDEND
,

GENERATE ZERO ANS

GENERATE ZERO

OF A AND B ARGUMENTS.

‘

UNDERFLOW

OVERFLOW,

OVERFLOW

UNDERFLOW,

SHIFT DIVIDEND LEFT.
SHIFT QUOTIENT LEFT.

CARRY OUT TO LSB OF

SET LOCAL CONDITION

QUOTIENT (MSR00).
s

SET LOCAL CONDITION

CODES TO INDICATE

DECREMENT STEP CTR.

SETLOCAL CONDITION

OVERFLOW

STEP

;

COUNTER

.
\._

NORMALIZE

STORE

ROUND & STORE

—

‘

———
-

161

(

o
'

DONE

’
o

(

STEP

COUNTER

‘

,‘

TRANSFER LOCAL

CONDITION CODES TO

)

|
NORMALIZE

ROUND & STORE

)

r—

STORE

CODES TO INDICATE

UNDERFLOW

)

STORE ANSWER
’

L_cPUSTATUS

‘

DONE

|
)

1-1617

11-1616

Figure 3-8 KE11-F FMUL Algorithm

Figure 3-9 KE11-F FDIV Algorithm

Figure 3-10 KE11-F Normalize, Round & Store Algorithm

3.2.3.4

Normalize, Round and Store — As shown in Figure 3-10, the flow can be entered either at NORMALIZE,

ROUND & STORE, or at STORE. The STORE flow is entered from FDIV after determination that the dividend was
equal to 0, or from FMUL after it has been determined that one of the arguments was equal to 0. In these flows

(FDIV & FMUL), local condition codes were set and upon entering this flow the answer is stored, the local

condition codes are transferred to the CPU Status Word, and the flow terminates.
The NORMALIZE, ROUND & STORE entry is made from all other flows if no unusual conditions are detected in
the process. The first test is made to see if the mantissa is normalized. This is indicated by the state of DR09, the
MSB of the mantissa. If this bit is not set, the mantissa is not normalized and, as a result, is shifted left one bit

position while decrementing the exponent. This is formed into a loop until DR0O9 becomes set, at which time the
mantissa is normalized and ready to be rounded.
|

As noted earlier, an extra bit position is carried on the low end of the mantissa. This bit is the position the rounding
bit
is added to. If the extra bit is a 1, then there will be a carry into the least significant bit of the mantissa, thus
increasing the absolute value of the number. If the extra bit is a O, there will be no carry-in.

For example:
Mantissa

Extra Bit

1001001

1001010

Rounding Bit

The extra bit position is dropped before the mantissa is stored. After rounding, a test is made to see if the mantissa is
still normalized. It is possible for the mantissa to become unnormalized as a result of rounding, i.e., carries could

propagate all the way through and beyond the most significant bit of the mantissa.
For example:

1111111 1J1
+

10"OOOOOOO|0
If this happens, the mantissa must be shifted right one place and the exponent incremented to renormalize the
mantissa.

e 43 b o

The high answer (comprising the sign, the exponent, and the mantissa) is now assembled. Remember that the

mantissa is always assumed to be normalized, which means that the most significant bit is always going to a (1).
Because of this, there is no point in storing the most significant bit in core. This (1) in the MSB of the mantissa is
termed the hidden 1 and is dropped when the high answer is assembled.

Next a check for either overflow or underflow is made. If underflow is indiCated', the local condition codes are set
appropriately, transferred to the PSW, and the flow terminates. Likewise if overflow is indicated, the same action
- occurs. If, however, neither is indicated, the local condition codes are set and the answer is stored in core. The flow
terminates after transfer of condition codes to the CPU Status Word.

3-20

4
CHAPTER

'~
LOGIC

4.1

DESCRIPTION

SCOPE

This chapter describes the hardware associated with both the KE11-E and KEll -F. Because of their
interdependence, these two options are not separated in this chapter as they are in other chapters but rather are
described as one entity. The options are described at both a block diagram level and a logic level. In addition, the
philosophy behind ROM programming is discussed together with a guide to reading the flows. Where necessary,
interaction on a flow level with the KD11-Ais also given. For convenlence loglc descnptlons are ordered as to thelrp

appearance in the Drawing Set.

4.2 FUNCTIONAL BLOCK DIAGRAM DISCUSSION

F1gure 4-1 is a functional block dlagram of the KE11-E and KE11-F showmg the 1nterc0nnect10ns W1th the KDll A
Central Processor. Both Opthl’lS are shown. The dotted line separates the EIS on the left and the FIS on the nght
- The KE11-E compnses one 16 b1t input regtster (BR) a holdlng reg1ster that receives data from the KD11-A; a
16-bit left/right shift register (DR); an 8-bit up/down counter that receives data from the input register; a local

condition code register that records the status of the KE11-E operations; a dual 4:1 multiplexer (RDMUX) that
channels data via BUS RD drivers from the two KE11-E registers and status to the KD11-A; and a 256-word by
68-bit ROM that is used to control both the KD11-A and KE11-E during the executlon of the EIS 1nstruct10n The
two 16-bit registers (BR and DR) are s1mp1y an expansmn of the basic KDll -A data path o

The KEll -F comprlses all KE11-E hardware plus two 16-bit left/nght shift reglsters (HSR and MSR) that functlon

also as holding registers; a dual 4:1 multtplexer (FRD MUX) that assembles data for channeling from the KE11-F
registers to the KD11-A via separate bus drivers; a constants generator that creates the offsets required in FIS
computations; and a 256-word by 8 bit ROM used together with the EIS ROM to control both the KD11-A and

KEI1-F durmg the execution of an FIS 1nstruct10n

The input to the BR Register (DMUX(15:00)) is one
of the buses in the KD11-A. All data to the KE11-E or KE11-F
options is received over this bus. The BR Register is similar to theB Register in the processor in that it is clocked
by
the P1 and P3 timing pulses from the basic machine. Normally, without the KE11-E/F installed, data in the KD11-A
might be moved from the scratch pad, over the BUS RD through the buffer and the ALU. From the ALU, it would
move to the D Reglste'r onto the DMUX, and into the B Register (this can be followed by referring to drawing

KD11-A-BD). With the KE11 E/F installed, however, if one of the EIS or FIS instructions were issued, the data on

the DMUX might not enter the B Register but mlght continue on and into the BR Reglsterin the EIS optlon The

BR.is merely a holding register and every register within the option is loaded from it.

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The BR feeds the DR, the- RD MUX concatenated with DR15, and the RD MUX straight through It feeds the

counter with bits (07:00) to keep track of the number of steps performed. When the FISis installed, the BRis used

to feed the “assemble” mput of the FRD MUX and to load both the HSR and MSR Registers.

NOTE

For the EIS optlon only bits (05:00) are requrred for the
counter even though bits (07:00) are loaded. Bits (07:00) are
required for the FIS option.

In multiply and divide operat1ons the counter keeps track of how many steps have been executed in the various
loops. In arithmetic shift and arithmetic shift combrned 1nstruct1ons it holds the count or number of shifts that are

to be made.

The DR Register is clocked by P1 + P2 and is fed directly from the BR Register. The mode selected determines
it will shift right, shift left, or simply be loaded. At times it is used concatenated with the BR to hold the
whether

lower portion of the operand being shifted while the upper portion is shifted in the DMUX of the basic machine.
The DR can feed either the RD MUX (EIS) or the FRD MUX (FIS), depending upon the mode of operation. The
DR Reg1ster feeds the BUS RD via the RD MUX for transmrssron back to the basic machrne

The RD MUX is a multiplexer with four 1nput ports From rrght to left, dependmg upon the combination present at
|

its select 1nput it is fed with the followmg

Local status (EPS(N:C)). This input records the condition codes of the instruction as to whether it is
negative or equal to O, or whether there is any carry bit, or if there is overflow. This information is

assembled here and transferred back to the basic machine as the last event when an instruction is
|
|
complete From here it is loaded into the basic machme J Status Register.

The entire 16 bits of the DR Register are put on the RD BUS and fed either through the ALU or into

the general registers, or any place in the basic machine accessible from BUS RD.

3. . The BR shrfted left one place concatenated with DR15 (BR(14:00),DR15). As in the case of Arrthmetrc

Shift Combined, the BR and DR are concatenated and shifted left through that port wrth the DR bemg

~ the lower reglster :

The entire 16 bits of the BR Register where it is fed, W1th no shrftmg, onto the BUS RD.

‘The EIS ROM word is physically 68 bits wide (i.e., the ROM bits that are actively being used), but the KD11-A

ROM contains 56 bits while the KE11-E ROM has 24 bits of its own. Since the KE11-E must control the KD11-A
data path, most of the 56 ROM bits in the basic machine must be duplicated. Not all need be duplicated, however,
just those that are to be used by the optron The others are driven low by hardwarein the option, thereby effectively
‘loading Os into those positions in the U Register. As a result the KE11-E effectively sends 56 ROM bits back to the
~ basic machrne not all of which are active, and generates 24 bits of its own which it feeds to its own U Register.

These bits are used to control the EIS data path to clock the BR and DR Regrsters to control which way the DR
Register will shift, to load the counter, and to cause the counter to count. They are used further to control what
port on the RD MUXis active, and to clock the status bits (see ROM U word descriptionsin Paragraph 4.6.2).

4-3

The option also containsa branch microtest multiplexer (BUT MUX) which is used for testing conditions that
determine selectable changes in microprogram flow. This BUT MUX is similar to the one in the KD11-A and is
duplicated here to control conditions peculiar to the option. Bits in the ROM are used to control inputs to the

multiplexer which, in turn, checks for the true or false state of some testable condition. The result of that test then
is used to alter the “next addressTM residing in the present ROM word UPF field. The output of the BUT MUX goes

back to the basic machine to an OR gate in front of the UPP Register where 1s may be inserted in appropriate

positions to alter that base address to as many different addresses as there are branches called for.

In the KE11-F, the HSR and MSR Registers are both fed by the BR when an FIS instruction is called for. Their
mode of operation is selected similarly to the DR in the EIS option except that here three bits are used to control

two registers. In operation, normally the HSR can be loaded at any time unless conditions require that both the HSR

and MSR be loaded. In this event, the MSRis loaded before the HSR. An examination of the mode selection for the

'HSR and MSR on print KF-2 illustrates why the latter statement is true.

The FRD MUX is similar to the RD MUX in the EIS option. In this case, a constants generator is also multiplexed to

the BUS RD. Select bits control the inputs from the HSR or MSR Registers, the constants generator, or the assemble
input from BR and DRin which the high 7 bits of the mantissa are in the DR Regrster the 8-bit exponent is heldin

~the BR Regrster and the srgn is taken from the EPS(N) brt

The BUS RD drivers (74HO1s) are identical to those used in the EIS option but are enabled only when an FIS
instruction is called for.

The FIS ROM is a further horizontal extension of the microinstruction word. It supplies the extra control_ bits
required for floating-point operation. It should be noted that the ROMs on the EIS board are also used to execute
the FIS instructions.

Additional control logic
is provided in this optron to allow branch control of bit 1 of the ROM address from this

hardware rather than from the EIS option. Provision is also made to enable DATO operatrons on the bus so that
answers may be stored backin core. This featureis not neededin the EIS option.

4.3 DETAILED BLOCK DIAGRAM DISCUSSION
The descriptions in this paragraph are intended to supplement those in Paragraph 4.2. The detailed block diagrams
for the KE11-E and KE11-F are shown on drawings KE11-E-BD and KE11-F-BD, respectively. These block diagrams
have been arranged such that the inputs and outputs match the outputs and inputs of the KD11-A block diagramin
drawing KD11-A-BD. Note that each block contains the drawing number on which the logic may be found, e.g., the
BR Registeris found on drawing KE-2 of the EIS schematics.

As shown on KE11-E-BD, the option is fed from the processor DMUX output. This is sent directly to the BR
Reglster through Wh.lCh all data to both optlons is fed.

The output of the BR Regrster feeds the RD' MUX and the DR Register. All 16 bits
of the
BR go to the DR while

bits. (07:00) go to the counter. As explained earher BR(14:00) can be shifted left one position and fed to the RD

'MUX with bit 15 of the DR sent to the low bit position. BR(IS OO) is also sent off the page to the FIS block
dragram as is DR(15:00). The RD MUX is selected by combinations of SRDMI and SRDMO, two bits in the FIS

extension of the ROM word. Its output feeds a 74HO1 driver which is in turn enabled by STRDM(1)H, the latter
being the ERD freldin the extension ROM word When asserted this datais enabled out onto BUS RD from the RD
MUX.

by LD COUNT L
The COUNT, fed by DR(07:00), is used in both the KE11-E and KE11-F. The counter is loaded

and is clocked by CLK COUNT H. It is used to test whether or not the count is equal to 0, thereby keepmg track of

where the operdtion is in a loop.

The EPS(N,Z,V,C) block is used to compile the local condition codes (EPS means External Processor Status) for
transmission back to the Processor Status Word via the RD MUX at the conclusion of each instruction. An inhibit
‘signal (KE 5 INH PS CLK (1) L) is also generated at this timethat prevents clocking any other bits in the basic

machine status. In the case of an aborted instruction, these bits are not transferred but rather are stored here for

information after servicing the abort. This leaves the basic machine’s cond1tron codes untouched as further

informationin servicing the abort.

The AUXILIARY ROM CONTROL block consists of some combinational logic that looks at a general purpose code

(GPC=2) and the decoding of the MUL and DIV instructions to feed ESALU(3:0) back to the processor. These are

select bits sent to the basi¢ machine’s ALU via a multiplexer into which the ROM bits are also sent. When selected,
this auxiliary combinational logic replaces ROM word control of the ALU, causing the add, subtract or strarght
| through operatrons to be controlled by spec1a1 condrtlons during the multrply and divide instructions.

The box CLOCK ENABLE GATESis shown to indicate that P1, P2, and P3 from the basrc machrne are used to gate
internal conditions when generatrng the clocking srgnals for the various reg1sters in the option.

The EUBF MUX box is a multiplexer that looks at 5 EUB_F bits in the extended ROM word. These bits serve a

similar function to the EUB bits in the basic machine ROM word. They are used for microbranch testing within the

option. When just the EIS is installed, only 4 bits are used with the 5th bit pulled up. When the FIS optron is
installed, all 5 bits are used. Signals EUBC(4:1) are sent back to the basic machine for branch control.

The box marked U WORD CONTROL ROM stands for the KE11-E U Word ContrOl ROM, comp’rising 256 words X

80 bits. Its output feeds a KE11-E U WORD REGister, which is 24 bits wide, with the EIS ROM bits (bits 57

through 88). The lower 56 bits are sent back to the KD11-A U Word Regrster (K2) over BUS UxxL. Thisis actually
44 bits since in the KE11-E U Word some of the bits are used to drive two bits back to the basic machine. The BUS

U is a wired-OR of the CPU ROM output. Eight bits (BUS U(07:00)) are sent back to the Mrcroprogram Pointer |
|

Registerin the processor for feeding the KD11-A U Word Control ROM.

There are eight non-duplicated ROM bits that are hardware drrven They may be consrdered as wire-ORed wrth the
.
ROM outputs. Note that they are not ROM bits but rather open-collector gates.
The FIS block diagram on drawmg KEll -F-BD contains all that was contarned on the EIS block dlagram plus the
hardware representations for the FIS option. The EIS descriptions will not be repeated here.

As shown, BR(15:00) are used to feed both the HSR Reglster and the MSR Register. Both are clocked by

E(P1+P2)H. This clock comes from the EIS board andis always present at both registers. It is not effective, however,
until a register is selected by select bits generated in the FIS ROM Register. The same is true of the MSR Reglster
|

except thdt an additional select brtis required to enable this register.

Both the HSR and MSR Registers feed the FRD MUX whrchis similarin operatlon to the RD MUXin the EIS. BUSV

RD is fed with either HSR(15:00) straight-through; with the MSR(15:00) straight-through; with the input from the
9-bit constants generator; or it will assemble the EPS(N) bit (which is the sign bit) with the 8-bit exponent field
(BR(07:00)) and with the high 7 bits of the mantissa (DR(O6 OO)) all of whrch constrtute the hrgh answer from a
floating operation.

The output from the FRD MUX is fed through an enabled driver similar to the drivers for the EIS option. In this

case, a special enable is provided (STFRDM(1)H) thatis called up for only floating instructions. The FUB MUX box

is an 8:1 branch multiplexer that controls EUBC1 for the FIS operations. When enabled, it disables its counterpart”
in the EIS option and allows this multiplexer to control bit 1 of the ROM address

‘The KE11-F U Word Control ROM (256 words X 8 bits) provides the additional extension of the microinstruction
word for the FIS option. It interfaces the processor data path and controlin similar fashion to the ROMin the EIS
option. This ROM is addressed by another buffered version of the Microprogram Pointer (BUPP(8:07)) rather than

~ the (EUPP(8:0)) used for the EIS ROM. Thls ROM feeds an 8-bit wide U Word Register similar to the register used
in the EIS.

4 4 INTERFACE

The KE11-E Optlon (M7238 module) and the KE11-F Optlon (M7239 module) both 1nterface the KD11-A Central
Processor via module slots in the KD11-A (A—F2 for the KE11-E and A—D1 for the KE11 -F). In addition three (3)
“over-the-back” cables from the M7238 module (EIS) connect the 40-pin Berg connectors on the M7232 (U Word)
module at location A—D3. These cables wire-OR the outputs of the “main” KD11-A ROM with the “auxiliary”
KE11-E and/or KEI 1-F ROMs.

The KE11-E receives data from the KD11-A via DMUX(15 :OO)H. The KE11-F, in turn, receives data from the

KE11-E. Data is returned from both options over the wire-ORed bus BUS RD(15:00)L.

When the KE11-E is installed, J1 on the processor module M7233 (IR DECODE) at location A—F5 must be
removed. When the KE11-F is installed, jumpers W1, W2, and W3 on the EIS option must also be removed. For more

information on installation, refer to Paragraph 5.1.

When either the KE11-E or KE11-F are in operation, the KD11-A ROMs are disabled and both the KD11-A and the

~options are controlled by the auxiliary ROMs. The processor fetches instructions from core and decodes them. If the
instruction contains a reserved code, the KD11-A ROM address bit UPP8 is set when BUT(INSTR 1) in the basic
PDP-11/40 ROM flow is executed. The setting of UPP8 disables the ROMs in the U Word (M7232) module and
enables the auxiliary ROMs on the EIS module (M7238).

“The KE11-E does another decode of the instruction, and if the instruction is in the EIS or FIS (if installed) group, it
will branch to the specified address calculation. If the instruction does not fall within these groups, main ROM
address UPPS is cleared, thus disabling the option ROMs and re-enabling the KD11-A ROMs. The KD11-A will then

‘execute a reserved instruction trap. This sequence of events can be followed by tracing words FET03, FET04, and
FETO5 on the KD11-A flows and word EIO on the KE11-E flows. This flow sequence is describedin more detailin
Paragraphs 4.7. 2 and 4.7.3.

.The mterfacmg s1gnals between the KEll -E/F and the KDll A are shown in Flgure 4-2 and listed with their
definitionsin Table 4-1.

"EUBC 5 pf

K2-3
_K2-7

CLKD(1)H_

Ki-7

D (15:00)=0H

. KE-2,6

Ki-5

BIS (1)
H

_KE-4,5, KE-4

L
BUS RD (15:00)

Ki-5

CoOuT 15 L

_K3-8

DAD
(3 %2)

{_Ki-5

, KF-2
KE-2
_KE-2,6~'
KEfS,KF-4

KE-4

D15 (1) H

Ki-2,3,4,5

DMUX (15:00)=0 H

KE-2

ECINOO H

KE-5

__ECLK UL

KE-5

K4-2

BUS U (56:00) L

K2-2

KE-2,4

ECOMUXS! L

KE-5

_ECOMUXSO L _

KE-5

ENPRCLK L

KE-5

ESALU (3:0) L

" KE-5

EUBC (4:1) L

KE-4

EUBC 8 L

KE-4

VK3

KD11-A. L

PROCESSOR

KE-4, KF-4

ALU 00 H

-~ K2-2,3

K2-3.

EUPP (B:O)H

K2-2,3

KE-5

IR 15
L

KE-4

K3-6

IR (14:12)=7 H

KE-4

_K3-3

IR (109)(1) H

KE-4

K3-3

IR (05:03)(1)
H

KE-4, KF-4

H
_ (P1, P2, P3)

EIS/FIS
OPTIONS

KE-5

__INH PS CLK L

K3-4

/
KEN—E
KE11-F

. KE-7,8

EXTP CLR TRAP L
K5-2

KE11-F

KF-4

Ki-2

Ki-2,3,4,5

. CENTRAL

KF-4

KE-5,KF-4
kKE;s

‘_K4-2‘_

H
Part PEND

Ké4-2-

P CLK UPP8 H

' KE-5

K4-2-

PEND H .

. KE-5

K3;6 '

__RSVD INSTR L

K2-2,3

H
BUPP (7:0)

K5-3

BUT 37 H

JKE~5"

KE-7,8,9,KF-4

1-1619

~ Figure 4'-2} KE11-E/ F/KD11-A Interfacing Signals |

Table 4-1

KE11-E/F/KD11-A Interface
Signal

ALUOO H

Definition

Bit O output from the CPU ALU used to shift into the BR Reglster

B15(1)H

~ Bit 15 from the CPU B Regrster

BUS RD(15:00)L

Sixteen lines over which data is transferred from the KEll-E/F to the CPU. A
~wire-ORed bus.

The carry-out from bit 15, of the 'CPU ALU.

COUTIS L

DAD(3*2) L

Bits 3 and 2 of the CPU DAD code field. Allows option auxflrary control of the CPU

ALU rather than d1rect (KD11-A) ROM control.

Dlé ()H

Bit 15 from the CPU D Register. Used in the branch table.

D(15 :00)=Q H

A signal from the CPU which indicates when the CPU D Register is equal to 0. The

resultant output from comb1nat10nal loglc (D(15 00)—0) is used on the branch

DMUX(15 :00) H

Sixteen lines from the CPU over which datais transferred to the KE11-E BR Reglster

From here, it is sent to the KEll F When 1nsta11ed

ECINOO H

An external carry-in from the option to bit 0 of the CPU ALU. Thisis the signal line
| from which thejumper is removed on the M7233 module when the EISis installed.

ECLK UL

A clock pulse from the CPU that is gated with an enable to generate the UReglster

BUS U(56:00) L

BUT(D=0).

clock for the EIS and FIS.

' Fifty-six ROM output lines that wire-OR the option ROM outputs with the KD11-A
ROM outputs over three 40-pin Berg connectors on the back of the module. Note that

the option ROM always controls the basic machine when activated. The basic machine

ROM never centrols the option.
ECOMUXS1

ECOMUXSO0

ENPRCLK

“External Carry-Out Mux Select” —Two signals to the CPU that allow the optlon to
- control the carry-out multiplexer of the CPU data path

“EXternal NPR Clock”— A signal from the option thatall'ews clocking of the CPU
NPR flag and BR flag, and clears the CPU BBSY flag so that NPRs may occur during
the EIS and FIS instructions.

“External Select ALU” — Four signals to the CPU that allow the KE11-E auxiliary
ALU control to specify what arithmetic function to perform. Used only in special

situations such as loops during which external control is needed. Normally, the ALU is
controlled by the CPU ROM word in which case the EIS feeds bits directly into the

CPU U Register for ALU control.

ESALU(3:0) L

4.8

Table 4-1 (Cont)

;

KE11-E/F/KD11-A Interface
Definition

Signal

EUBC(4:1)L

Four signals to the CPU that may modify the base ROM address when a branch test is
executed. When an address is brought out of the ROM, i.e., 100, the 6 lower bits of
this address would be Os. The EIS would OR 1s into any of bits 04:01 to modify that

base address. Note, bits 04:01 are the only bits available for modification
by the EIS.
A signal to the CPU that is essentially the reserved instruction gated back to the CPU.
When true, it is used as data, causing the ROM address bit UPP8 to be clocked set,

EUBC8 L

thereby disabling the CPU ROM and enabling the KE11 -E ROM. Whenever UPP8 is
clocked after that, it clears, reversing the conditions.

'EUPP(7:0) H

| Erght 31gna1s to the option which specify ‘the ROM address currently in the UPP
Register. UPPS controls which ROM is enabled while bits 7:0 control which addressis
in the ROM. In the CPU, addresses range from O to 377; in the auxiliary, they range
from 400 to 777. This is because of bit 8. Address 400 is actually bit 0 msrde the
ROM, wrth bit 8 being the enable for the ROM.

A s1gna1 to the CPU that allows the option to clear the CPU trap flag on a reserved

EXT P CLR TRAP L

1nstruct10n that the optlon has decoded as bemg either an EIS or FIS instruction.

A s1gnal to the CPU that 1nh1b1ts clockmg of CPU status b1ts (07 04). This s1gnal |

INHPS CLK (1) L

allows the modification of the N, Z, V, and C bitsin that word by comparable bitsin

the option EPS Register-but protects the priority bits already resident
in the Processor

IR15L

IR(14:12)=7H
IR(11:09)(1) H
IR(05:03)(1) H

(P1P2P3)H

Status Word. If the KT11-D Memory Management Unit is also installed, this signal also
inhibits clocking of bits (15:12) in the CPU status as well. Permlts clockmg only of
CPU status bits (03:00).

Selected bits and conditions of the IR Register that are used to decode whether or not
~ the reserved instruction is really an EIS or FIS instruction. Bits 0, 1, and 2 are not
“essential for this decoding process.

- Three clock pulses from the CPU that are gated with enabling signals from the ROM
word U Register to generate the various clocking signals for the registers and flip-flops
in the optrons

Part P END H

A srgnal from the CPU generated as a functron of the END pulse for cycle length 2 and
cycle length 3. It is equal to P2 or P3.

P CLK UPP8 H

A 31gna1 from the option that clocks ROM address bit UPP8 in the CPU Thrs srgnal
results from P END (described below) gated with CLOCK UPPS, bit 64 of the EIS

"ROM word. Once the option is active, by virtue of UPP8 having been set, asserting
CLOCK UPPS8 in the ROM will result in this srgnal which, in turn, will disable the
‘option ROM and enable the CPU ROM.
PENDH

A signal from the CPU thatis equal to (P1+P2+P3) Thrsis the end pulse in each cycle
length. In a cycle length 1, it is P1;in a cycle length 2, it is P2;in a cycle length 3, it is
P3, even though a P2 exists.

4.9

Table 4-1 (Cont)

KE11-E/F/KD11-A Interface

‘Signal
'RSVDINSTRL

Definition

A signal to the option that indicates that the CPU has fetched a reserved instruction

code and that the instruction may be an EIS or FIS. This signal is used as data gated

with EUPPS H to y1eld EUBCS8 L descnbed above.
BUT37H

A signal from the CPU Wthh when gated with PART P END produces the mgnal P
CLK UPPS8 H.

B EUBCSL

| CLK D ( npeHE

o .A 81gna1 from FIS to CPU that is used to mod1fy the base ROM address on branch

tests.

]

A signal’from the CPU to FIS which is used to enable cloeking the ARGA flip-flop.

4. 5 ROM PROGRAMMING PHILOSOPHY
The PDP-11/40 System, and consequently the KE11-E and KE11-F Optlons uses the pr1n01p1e of read- only-memory
(ROM) microprogramming in their basic architecture. The use of this technique drastically reduces the requirements
for discrete combinational logic.and results in a system that is easier to understand and to maintain.

'In h1therto convent10nal processor design, each control 31gna1 was the output of a comb1nat1ona1 network that
- detected all the machine states and conditions for which the signal should be asserted. The machine state represented
the contents of a number of storage elements (e.g., flip-flops) that had been loaded from signals that were, in turn,
the outputs of other combinational networks. These outputs were based on such conditions as current state, sensed
~ internal conditions, and sensed external conditions. Although many times the number of logical elements could be

~ reduced by sharing outputs of networks, thereby reducing the size of the processor, this often increased the
complexity of the machine and the difficulty in maintaining it.

In the PDP-11/40 System, however, the principle
of microprogrammed control has been implemented in which the
- various control signals are stored in a self-contained ROM at time of manufacture.
This storage is separate from the
data storage element. Since each control signal can be completely defined if its value
is known for each machine

state, the ROM becomes the function generator divided into words. There is a word for each machine state and for
each functional step of all operations. Fach word contains a bit for every control signal. During each machine state,
~the contents of the corresponding word in the ROM are transmitted on the control lines. For most control signals,

- the output of the ROM is the control signal and no additional logic is required.

The two tasks of a sequence control section are to select the next machine state, and to provide information about

the current machine state to the function generator. The only information that the function generator in a

microprogrammed processor requires is which word to use as control signals. The sequence control then merely
supplies an address that selects the correct word. The sequence control must also select the address of the next word

to determine the machine state sequence.

- Because the next machine state is determined in part by the current machine state, information is stored in the
microprogram that aids in the selection of the next state. In a ROM programmed device, the microprogram word
contains the control signal values and the address and sensing control information required by the microprogram
address generation logic. Thus, this logic functions as the sequence control.

4-10

4.6

CONTROL ROM

The KEH -E control ROM word consists of 256 X 80 bit words. The KE11-F control ROM comprises 256 X 8 bit
words. In the EIS, 24 ROM bits are used to control the KE11-E itself while 44 bits actively control 47 of the 56 bits
in the CPU ROM word. The remaining 9 bits of the CPU ROM word are not utilized by the KE11-E or KE11-F and
are driven low when the options are enabled. The outputs of the ROM and driver that duphcate the CPU ROM bits
are wire-ORed to the outputs of the CPU ROMs.

The low eight bits of each ROM word specifies the next address of the microprogram. Occasionally there may be a

desire to branch to one of several possible microroutines. Based upon certain conditions, the branch may be effected

by executing a Branch Micro-Test (BUT) to test the desired condition. If a condition is met, the base address
specified by the ROM will be modified by ORing a (1) into a (0) bit of the address and the microprogram will
branch to the modified address If the branch conditionis not met, the next address will be the one specrfred by the
'

control ROM.

Certain condrtrons can cause the microprogram to jam to a ‘speeific ROM address, thus aborting the normal

microflow. The jam may be caused by a bus data timeout or an odd address error occurrrng on a bus data cycle A
red zone stack overflow error wrll also cause thej]am

- 4.6.1 KDM-A ROM Word

The KDI 1-A ROM microinstruction format is shown in Frgure 4-3 and described in Table 4-2 Although much of
- this information is included in the KDI1-A Maintenance Manual, it is repeated here for clarity and also to permit
- specral reference as regards the KE11-E and KE11-F Options. Referenceis also made to drawrng KDI 1-A-BD, sheet
2 of 2 for more rnformatron and tabular data not includedin Figure 4-3.

4.6.2 KE11-E/F ROM Word

The KEII -E/F ROM rmcrornstructron format is shownin Frgure 4-4 and descrrbedin Table 4-3. Note that thisis an

extension of the basic KD11-A format shown in Figure 4-3 and describedin Table 4-2. The option ROMs duplicate
all bits shown for the basic ROMin addition to generating these bits. Referenceis also made to drawrng KEI 1-E-BD,
sheet 2 of 2 for more 1nformat10n and tabular data not 1ncludedin Figure 4-4

In both the figure and the drawrng, the bits are represented 1dentrca11y to the representatron for the processor Note that in the top box of the drawing, the mnemonic for the fieldis given while the mnemonics below‘that are the bits
in that field. For example, the field EUB contains bits EUBF(3:0). Their states represent an octal number appearing

in the flow diagrams. Refer to word EIO on the EIS flows, drawing KE11-E-F, sheet 1 of 5. Nete that for a branch ,A

I, EUB must equal 175.
microtest of Extended INSTRuction I,

A line printer prrntout showing a]l the octal values of each field of every ROM wordin the flows has been made part

of the print set. A portion of the first page of this printout is shown in Figures 4-5 and 4-6, with a legend to aidin
their use. Arrangement is by U Word Addressin numerical order. Note that the addressis the basic address and does
not include the 4005 offset, e.g., in Figure 4-5, NOM14 on F6 lists the address as 140 butin the flow it is shown as
540. This holds for all addresses in this printout, as they represent only the states of ROM bits during an EIS or FIS
instruction. Figure 4-6 gives the EIS/FIS ROM words while Figure 4-5 lists the KD11-A ROM words as generated by
the EIS and FIS. Frgure 4-6is the extension left of Figure 4-5.

4-11

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Table42

KD11-A ROM Word
Bit No.

(Uxx(D)H)

Field

Definition.

Bit

Mnemonic

- Mnemonic

(07:00)

UPFx

g Eight bits that yield the 256 basic locations. Note that they

designate the next unmodified address of next
microinstruction in the flow. Modified as a result of a branch

“test.

UPF8

Note, this is hardware, not in ROM. When clear, enables basic
machine ROM. When set, disables basic machine ROM and
‘enables the option ROMs. Controls which ROM will control
the basic machine.

(12:09)

RIFx

RIF

registers. In conjunction with a bit in the SRX field, these 4

bits provide 16 p0531ble addresses to select one of the general
-

(16:13)

SRX

registers.

SRI

Select Register Immediate. When set, designates the RIF bits
as the address of the scratch pad.

'SRBA

-Allows BA(03: OO) to be used as source of general reglster

SRD

~ Select Register Destmatlon Uses the destmatlon field of the

address.

instruction IR(02:00) to select the Scratch Pad Register in a
destination address calculation.

Select Register Source. Uses the source field of the instruction
- IR(08: 06) to select the general reglster to be used.
N OTE

The RIF fleldis 4 blts wide and the SRBA enables 4 bitsin the
~ BA. Therefore, these functions can access all 16 registers. The
"SRD and SRS bits, however, enable only 3 bits each;
- therefore, these functions can access only the lower 8 registers.

(21:17)

UBF-

| UBFx

‘The microbranch field. Allows microbranch'conditions to be
tested so next address can be modified. This field is not used
by the EIS or FIS. See EUB field in Table 4-3.

SBA

(24:23) |

SDM

SBAM

Select BA Mux. Selects source of input to Bus Address Mux,
either via BUS RD or via the ALU.

~ SDMx

Select DMUX Selects DMUX input Whether D Reglster
straight through, the RD bus, D Register shifted right, or the

Unibus. This function is used primarily in the basic machine.

4-13

Table 4-2 (Cont)

KD11-A ROM Word

(Uxx(1)H)

' Field

Bit

Definition

SBM
.

(28:25)
SR

SBMHx and
- SBMLx

|
Selects mput to hrgh side of BMUX
the two 8 b1t
Controls
BMUX.
of
side
low
~ Selects- input to

Mnemonic

Mnemonic
-

B
bytes of the BMUX independently. The BMUX can load the
into
constant
a
load
ALU,
the
into
Register straight through

the ALU, swap the two halves, or extend bit 7 of the B
Register into the upper byte and load the lower byte with its
sign extended into the wupper byte. In addition, any
combination of these can be used and are used by EIS and FIS
operations.

Select B Constant. Allows microprogram to specify one of 16

(32:29)

' SBC

SBCx

. (37:33)

ALU

SALUM and

‘constants to be loaded into B IN of the ALU via the BMUX.

Select ALU mode (arithmetic or logical).

SALUx

Select ALU operation (add, subtract, OR, AND, etc). There
are 16 operations for each mode.

(40:38)

SPS

SPSx

‘Select Processor Status. Controls 1oading and clocking of the

- (44:41)

DAD

DADx

Discrete Alteration of Data. Allows microprogram to alter

SRR

PSW. Various combinations of these 3 bits perform separate
operations on the PSW. See table on engineering drawing.

operation of the data path. For example, allows checking for

stack overflow during a data cycle, or allows execution of an
odd address, or control of the ALU by an auxrlrary function
rather than d1rectly, etc

(47:45)

BUS

BGBUS

Bus Control Bits.

Begin Bus. When set, permits DATI, DATIP, DATO, or

DATOB, depending upon setting of C1 BUS and CO BUS.
When cleared, sets AWBBY (Await Bus Busy) or restart on
- perrpheral release dependmg upon setting of C1 or CO BUS.

- CiBUSand |

Un1bus control brts wh1ch perform the standard PDP-11

- COBUS

functionsin conjunction with BGBUS bit.

- CBA

- CLKBA

- Clock Bus Address. Gated to clock ’rhe Bus Address.

CD. |

CLKD

Clock D Register. Allows clocking ALU into D.

- 50

‘ CB |

CLKB

~ Clock B Register. Allows clocking DMUX into B.

(52:51) |

WRL and

Write enables for the general registers. 01 enables the low byte

WRH

of the DMUX to be written, 10 enables the high byte to be

written, and 11 enables both bytes to be written.

4-14

pa—

Table 4-2 (Cont)v-'
-KD11-A ROM Word

Bit No.

Field

Bit

(Uxx(1)H)

Mnemonic

Mnemonic |

CIR

CLKIR
|

(56:54)

~Definition

CLK

Clock the Instruction Register. Allows Unibus data to be
clocked into the IR.

CLKOFF

Clock Off. When asserted, allows mlcroprogram to shut off
Processor clock..

Clock length control. 00 or 01 enables a cycle length 1. 10
enables a cycle length 2 and 11 a cycle length 3.

cont | cono.| FciBus) EusFa
.

CONTROLS THE

H"Ig'

ALLOWS EXTENDS

80 .

—

RIGHT SHIFT OR~
- .DATA
LOAD OF MSR
& HSR ONTO RD

"REGISTERS

BUS

SNZM_1. SNZMO |cLk Nz | cLk v
L

ALLOWS INPUT

SELECTION

FOR THE NZ

MUX

E—

BUS

—

CLK C ALLOWS CLOCKING

OF EXPANSION C BIT

—

GENERAL PURPOSE

CODE TO DECODE

SELDOM PERFORMED

FUNCTIONS

]

ALLOWS THE D

BUS

ALL

QCPLPKe

LCNT | ECNT | EUBF3
!

v ALLOWS ALLOWS
UPP8

TO BE
COUNTING OF
CLEARED THE COUNTER

SELECTION FOR
THE CV MUX

| EUBF2 | EUBFY

CLK

EUBFO

—

FIELD-ALLOWS MICROBRANCH

CONDITION TO BE TESTED (BUT)

EUBF(3:0)EXTERNAL MICROBRANCH
:

)

ALLOWS INPUT

ENABLING AND

LEFTOR NOT AT

—

SDRMO | scvM2 | scvmi | scvmo

- ONTO RD

INPUT TO
‘BE 'GATED -

cLk ¢ | epc2 | ePct | GPCO

‘CLOCK CONDITION CODES-

SELECTS

STROBES

:DATA
:
ONTO RD

EIS ROM-

72T

| STROM srom1 | sromo | sorm1 |

CONTROLS LEFT OR | STROBES

GENERATION OF A DATO EUBF IN
CONSTANTS
FOR FIS EIS
'

————EIS ROM

- |

FIS ROM —

CLK1 and
CLKO

—

ALLOWS

CLOCKING
OF THE BR

CLK V ALLOWS CLOCKING
OF EXPANSION V BIT

CLK NZ ALLOWS CLOCKING
OF EXPANSION N 8
z BITS
11-1621

Figure 44 KE11-E/F ROM Format

4-15

183

NOM]

154

NOMB

156

00
00

00
14

00
-00

00
00

23
Q0

00 00
00

00
00

cooo

005

O OO
O

20
00

o000

UPF

244

275

142
177
332

00
00

13 252

062

15
13

365

000

135

153

324

2 ABH15

{77

00
00

00-

oIV

00
00

15 176
00 340

O OO

i1
00

[eBeNe¥ o)

oNnNOo
O

00
00

nNo oo

o o

OO0

OO
O O

s
e
.

- 0O

175
174

107

344

256

165
202
350

00
00

143

27t

10
10

042

2io
00 $31

273
567

COO0O

00"

11
00

Qo
O O

179

O
O

g176

174

NOM3

FP7

O 00O

0
0
0

OO0
O

CNOM9

0
0
0

00 - 00
00.
00

2
2
6

coo0o

178
172
378

00
01
00

~No
o o

170

Fovit
FMLB
FOVIZ

(e]

0ST4

L ]

167

IO
D OO

MUL20

= 3N o N -

[

166

165

OO
=

164

ADJ6

FOy3

"2 ADDS

00
00

OO0
O

OO0

163

O -

161

ADD13

162

EXI4

Foys

4 0

157

160

-0

DIv2y

FDV6

= O

155

OO Oe

FP6

OO
== O

OO
O O

DIvao

00
00

ooV

[ 3N \CR

150

OO0 o0

147

OO0 OO

OO0
o

146

cocoo

OC OO0

—_0
O

144

0
0

145

OO
O O

FP4

0
0

DIVi4

FMLS

2
4

FPL0

141
142
143

CD CBA BUS DAD SPS ALU SBC sBM SDM SBA UBF SRX RIF

DST12

140

OO O

FPi2

OmreO

NOMi4

MUL26

CEXI0o
MULI1

)
P
s

ADR CLK CIR

OO OO0

FLONWS STATE

2eo

ses

KD1 1 _-A ROM Words Géne'r,ated by-the ‘;Opti‘o‘ns (Sample)

Figure 4-5

FR7

475

Fe
Fa

NOM3
ASHI5

176
177

0
0

{
0

oo
o

R-X-¥-¥-

e oNoNe

OO0
O O

coo
o

O o

e
e

t‘.—‘.oo

v o
cooo| o

OO =D
O —oo.

coo0o

OO0
o

OO OO
OO O D
NN O WO

O OO

cocooo
> B =N e |
[
=P
= « 3 -}
O

OO O
wo oo
o oo
OC DO
o0 QO

00
00

1
-0
10

{6
00
05
00

10
00

OO
-0

O r O O
OO

o0
O o
No oo

O
ool oNe)
O

OO0 OO
oo oo

s G

o NoReNa)

o
= e
O
O
O
QDO

O
O

00
00

Figure 4-6 Comparable EIS/FIS ROM Words (Sample)
4-16

00
00
00

§2

ocoooo

e lle ]

= Nla

00
-

F6 NOM9. 174

oo oo

173

OoOCcod

FDVI3

COO0OO0

Fu FMLB

0
0

172

00
00

O
& O

.
00.

171

0
0

FOVILT

0o
0

3
0
0

OO
O O

0§
0

—_—00
O

-0

0
-

[« JF —l e N o)

0
0

O OO
O .

167

170

OO0
O

MUL20

DST4

O NOoOo

0
0

0o
0

el eNe]

f-l

166

o Wall oW

165

164

ADD6
FOVS

WO OO

ADDS

F2
FS

DLoo

2
0
0

QDO

161
162
163

160

OO
O

FS FDV6

157

QO
O

DIv2l

O 0O
O

-0

oo oco

Fo EXI4
FS FOVS
F2a ADD13

00O

155

154
156

]

FPa

NOMB

o B

Fo NOMI

0
0

ogs2
DIV20
153

0
0

O 0OD

151

FP4

OO0

147

150

QOO
e

146 .

DIvid

0 0

OO0
O

S B4 FMLS

145

-0
0 D

F1 FP1O~

o144

oo
o

FUFP12

0
-

143

MULI1

DO
O

Bl UST12

o000

O OO

e B oo

142

141

EXIO

=Nl

MUL26

el o]

140 - 0

CFe NOM{4

FLOWS STATE ADR CON FC{ FUB MHR FRD ERD SRD SDK CVM NZM CCC GPC CEE CNT EUB CBR

Table4-3
KE11-E/F ROM Word

Bit No.

(Uxx(1)H)

Definition

Mnemonic

CBR

CLK BR

BR Register clock.
Enabling signal for the

(61:58)

"EUB

EUBFx

External Microbranch Field — Allows extended microbranch

- (63:62)

CNT

= v

Bit

Field

Mnemonic

condition to be tested.

Load Counter.

LCNT and

'Enable Counter — Allows loading and enabling of counter so

- ECNT

that it may count up or down.

CLKUPP8

Clock Expansion Enable. Enables clocking of UPP8 to disable

CEE

(67:65)

GPC

GPCx
-

(70:68)
-

CCC

CLK NZ

Clock | the N and Z bits in the External Processor Status
Register. In the option, both are clocked simultaneously.

CLK V

Clock the V bit in the EPS.

CLK C

Clock the C bit in the EPS.

»(72:71)
|

(75:73)

expansion ROM and enable basic ROM.

General Purpose Code — Decodes seldom performed functlons |

(see table on engineering drawing).

N Z Multiplexer Select— Control the source of data for these

NZM

SNZMx

) CVM

) SCVMX N

C V Multiplexer Select — Control the ssource of data for these

- SDRMx

- Select DR Register — Control whether the DR Reglster will

two EPS b1ts (C V)

‘two EPS bits (N,Z).

- (77:76)

SDR

(79:78)

SRD

~ SRDMx

~ Select RD Multlplexer — Selects Wthh source W111 be. gated

ERD

STRDM

Strobe RD Multiplexer — While the SRD determines what data

load, shift right, shift left, or do nothing.

out onto the RD bus.

will be put on BUS RD, this bit enables the dnvers to that bus

and actually gates the data to BUS RD.
NOTE

The following signals are available only when the KE11-F is
o
‘
|
installed.

FRD

STFRDM

Strobe FloatmgRD Multiplexer — Performs the same functlon
as the ERD doesin the EIS option.

4-17

Table 4-3 (Cont)

'KE11-E/F ROM Word

Bit No. "

(Uxx(1)H)

(84:82)

.Definitirone o

Field

Bit

Mnemonic

MHR

'SMSR and

Select MSR Register
— Is gated with the Shift HSR Register

SHSRx

bits to enable the same function in the MSR Register as
selected for the HSR Register. The x bits determine whether
the HSR (and MSR when selected) will shrft left, shift right,
load Or Nno op.

FUB

Extension of EUB field in EIS, providing the additional branch

- EUBF4

tests for FIS option. When asserted, it disables the low bit

multiplexer in the EIS and enables a similar multiplexer in the
-

FIS to control the low bit of ROM address modification.

There are six tests with this function, see table on engineering
drawrng

Fc1

FciBUs

| This replaces the FC1 bit of the basic machine. Note that in
the EIS no DATOs are required since nothing is stored back

into core. This enables the FIS to do a DATO for writing
~

(88:87)
4.7

CON

CONx

answers back into core.

Constants decoding bits. See table on engineering drawing.

FLOW DIAGRAM DISCUSSION

‘The flow diagram in conventional computer design has always played a major role in the understanding of the
operation of the equipment. It is in a sense a road map of operation guiding the reader from one event to the next
based upon sets of intervening condrtrons In the PDP-11/40 System, however, the flow diagram plays a much more
important role than before since it ties the operatlons to the major sequencing device in the machine, the ROM.
Indeed, understanding the flowis a major prerequisite for the understanding of the KE11-E and KE11-F Options.

Because of the added responsibility intrinsic to this portion of the documentation, some changes have been made to
the conventional flow diagram symbology to accommodate the added functions it serves. In this paragraph, these
new conventions are discussed and explained. In addition, representative operations are followed through the flows
so that, once familiar with the procedure the reader can follow any operation through from its initiation to
completron

4.7.1 Symbology of the Flows

- Figure 4-7 111ustrates the common drawing. eonventrons used in both the KD11-A and KE11-E/F flow diagrams.

General flow
is from top to bottom unless further continuation is required, in which case it is carried to the top of
the page before continuing.

Horizontal flow is indicated and limited by the direction of the arrow on the line. Branching flow is dictated by the
~prevailing conditions that result from the branch test. The conditions for the branch are indicated to the right of
each branch flow. For the most part, to the degree possible, the branches have a priority with the highest priority to
the left and the lowest to the right. A double squiggley line in any flow line indicates that a time delay
is
experienced before continuing.

SOURCE FLOW

(#) PAGE NUMBER

CENTRY POINT )
o

FLOW LINE

,——— U WORD ADDRESS
# AEFE

U WORD MNEMONIC————
XX #

FLOW STEP BLOCK

DESCRIPTION OF ACTIONI CONSOLE DISPLAY

CYCLE LENGTH: ACTION/S

" BRANCH TEST MNEMONIC AND CODE

(NOTE REF)

###<———0R BRANCH

~
WORD —T|
INTERVENING

RANCH POINT
PO

BRANCH

T BRANCH COND.1

BASE U WORD ADDRESS

—

'J.«

=)
L

0 —e

0Os
INDICATE NOTHING
NGNS
08DAt

INDICATES A

N\ T WAIT FOR THE BUS
BRANCH COND.3

2
BRANCH COND.
|

DIRECTION _

LIMITATION

A «——— TIME DELAY

XX #

‘

A A

NEXT U WORD.

]

(#£)

(#¢) «—— DESTINATION FLOW PAGE NUMBER

FHAHE

### «—— ADDRESS OF MICROPROGRAM CONTINUATION
H-1622

Figure 4-7 Flow Diagram Cdnventions |

Entry into the flow is indicated by a lolzenge (ellipse) containing the name of the operation to be performed in the

flow. A decimal number in parentheses above this indicator refers to the number of the page from which the flow

enters. In some instances, this is accompanied by a description of the flows if they are for a different piece of

equipment than that described by the flow page.

Each Step of the sequence is designated by the Flow Step Block, which contains either two or three divisions. The

top division contains a general description of the action taken by the step, with a description of what is displayed on
the console within a further subdivision of that area. This data is visible only in maintenance clock mode.

The second division of the Flow Step Block contains a description of the actions taken by that step in ISP notation.

~ This is preceded by the cycle length for the action expressed by either P1, P2, or P3.

The third division of the block does not always appear. It is set aside to indicate that a branch test is to be made and
expresses that test in mnemonic form. This block occurs in all cases two-words prior to the branching point.

The octal number at the upper right-hand corner of the block indicates the Micro-Word Address of that word in the
ROM.

The number at the lower right-hand corner of the block is given only when branch tests are made. It indicates the

base ROM address for the branch before modification by the branching conditions.

4-19

Exit from the flow is indicated by a diamond containing the mnemonic used in the entry point of the destination. A
decimal number within parentheses below the diamond indicates the page number of that continuation. An octal
number appearing below this page number designates the address of the microprogram continuation.

References to notes on the flow sheet are either given within the general description subdivision of the Step Block or
are located to the right of the block opposite the subdiVision that they illuminate.

The symbology used in the operator division of each block follows the convention of ISP notation as definedin the
Appendix of the PDP-11/40 Processor Handbook, 1972. To supplement this information, a few examples of the
more complex statements are given and described here. From these sources, the reader can decipher any statement in
the flows.

The use of the back arrow (4—) or data transnnssmn operator is shown at word EI2 on page 1 of the EIS flow
diagram.

UPP8<0

Basically, this means that the UPP8 bit in the basic machine is cleared. There are several ways of stating this such as
“UPPS8 gets 0 or “0 is sent to UPP8.”

Brackets are used to further define a quantity in the statement. For example at word ADD20 on page 2 of the FIS
flows, the following statement is used:

P2:D<R[14]

This means that at time P2 the contents of register 14 are sent to the D Register.
The definition, however, may be indirect as shown in the following example at word DST2 on page 1 of the EIS
flows:

P2:BA<R[DF]
In this case, DF means “Destination Field.” This statement then is saying, “The contents of the register designated

by the destination field of the IR is sent to the BA Register.” The P2 preceding that statement means that the BA
Register will be loaded upon the occurrence of P2. During the cycle length of that word, the data pathis steerlng the

data to the BA Register. Once it is set up, the pulse does the loadmg

The bracket can be used on the left -hand side of the transmission operator. Thisis illustratedin word DSTl on page

1 of the EIS flows The followmg statement appears

Pl BR, BR[DEST] <D

This statement means that at P1, the contents of register D are sent to three reglsters l) the BR, 2) the B, and 3)
the register specified by the contents of the destmatlon field of the IR

In some instances, the use of the bracket can produce confusion on the part of the reader, if the specific use is not
clearly defined An example of th1s is shown at word DST2 on sheet 1 of the EIS flows That statement reads as
follows:

D<R[DF]PLUS 2
In this instance, the bracket pertains to “the contents of.” This statement says that the contents of a register
designated by the destination field of the IR will be incremented by two then sent to the D Register. Note that it
does not say that the D Register W1ll receive the contents of a reg1ster two locations away from the register
des1gnated by DF.

4-20

An example of the use of two types of brackets is seen at word MUL9 on sheet 3 of the EISflows. This also
illustrates that conditional transfer can be a function of more than one variable.
P2:D<f(DR0O0 & EPS(C)

BR&B

;

This statement says that the BR and B Registers
are to be sent to the D Register in a cycle length 2; but they will be
acted upon in that transfer as a function of bit DROO and bit EPS(C). On that same sheet, off to the right, a table is
given for the four possible sets of conditions for these two function bits. From this, it can be seen that for two
conditions of these bits, the contents of BR will be put into D; but for the other two sets B will be either added to
BR or subtracted from BR and that result will be put into D.

The semicolon is used to designate separate action(s) to occur at the same time pulse:
P2:D,BA<R[DF] MINUS 2;DATI
P3:CLKOFF

This is shown at bST9 of sheet 1 of the EIS flows. DATI follows the semicolon for P2, indicating that a DATI will

be performed also on P2. In that same word, the clock will be turned off (CLKOFF) at pulse P3.

Note also at DST9 the notation SBC=1 in the lower r1ghthand corner of the block ThlS refers to the SBC (or Set B
‘Constant), indicated by ROM bits U(32:29)in the basic machine (see table on KD11-A-BD). Although this refers to
the basic machine, it should be remembered that these bits are being driven by the duplicating bits of the ROM in
the option. In this case, it brings in a constant for the MINUS 2 condition. The ALU is performmg the operatlon
A-B-1. This bringsin a 1, causing the ALU to perform an A-1-1 or A-2.

A comma to the left of the back arrow separates the blocks that recelve data smultaneously A comma to the right
of the back arrow separates the sets of data to be transferred

At word EI2 on sheet 1 of the EIS flows, the following statement'is made:
- D<f(SBC=00(STPM))

STPM refers to what the signal is everttually called in the hardware. SBC=00 is sent to the D Register and becomes

signal STPM. The SBC=00 looks at discrete logic in the processor and could get any one of several values. The
SBC=00 does not always select the same value to be sent to the D Register. This word is actually forming a trap
vector, with the error that is set at the time determining what that vector shall be.

In many places in the flows, a general statement is cften made before a branch and then is further defined after the
proper branch is entered. An example is shown in ASH1 on sheet 2 of the EIS flows.

‘

; CLOCK COUNT

Note that this indicates that the clock will be caused to count, but that it does not indicate wh1ch way If the flow
enters ASH3, the following notation is given:

P1:COUNT<PLUS 1

This indicates an incrementing count. If the flow enters ASHS, the following notation is given:
P1:COUNT<MINUS1
This indicates a decrementing count.

421

At ASH4 on that sheet thereis an example of a number of things occurring at the same time, yet not necessarlly as a
result of each other, stated as follows:

P2:D<R[SF] ;D(C)«ALU15;EPS(C)<ALU00

These are separated by semicolons, and a transmission operator is given for each. This says: at P2, the contents of
the register specified by the source field of the IRis sent to D; at the same time, ALU b1t 15 is sent to the D(C) flop;
and 31multaneously, ALU bit 00is sent to the EPS(C) bit.
The comma 1ndrcates inclusion as 1llustrated by the P3 operat1on of that same word

P3:BF,B,R[SF]<D(C),D[15:01]
In this case, all the information on the right-hand side of the arrow is being sent to all the destinations on the

~ left-hand side of the arrow. Only bits D(15:00) are being sent from the D Register. The 16th bit is the D(C) bit. By
referring to the ROM output, it can be seen that the right data port of the DMUXis being selected and that datais
being shifted right. Bit 1 of the D Regrster becomes the new bit 00, and everythmg elseis shifted right.

In ASH7 of this page the followmg notatlon is given which indicates another use of the bracket in spec:1fy1ng a
,

BR<—R[SFV1]

This states that the BR receives the contents of the regrster specrfied by the source field of the IR ORed with 1. This
is of course the odd regrster being specified.

Many times in the flow, it isnot always obvious what is contarned in a specified reg1ster unless the flow is traced

back a few steps to see what was last put into that register. A case in point is at word ASH17 of this same page.
P2:D<R[SF]PLUS B

This says: at P2, the contents of the register specified by the IR sourcefield plus the contents of B are sent to D.

This means little unless the contents
of B at that moment are known. Looking back in the flow to word ASHS8 will
show that at P2, R[SF] went to D, and at P3 of the same word, it went from D to B. This means that in ASH17
what is really happemng is that the contents of R[SF] are be1ng added to itself. Thisis equrvalent to shifting it left
one place.

ThlS same word (ASH17) also 1llustrates the use of the “IF” statement in the next llne
EPS(V)*—I IF BR15#BR14

This means that EPS(V) the overflow bit in the status word will be set ifa drfferencein BR15:14
sensrng an 1mpend1ng transition in the bit stream

The next l1nein that word’s statement deserves mention also:

DR<DR[14:00] ,0

This indicates that the DR is being shifted left and (0) is being shifted into the low bit.
In contrast to this, the notation at word MUL24 on sheet 3 of the EIS flows is as follows:
' DR<0,DR(15:01)

422

is noticed, thus

a (0) being shifted into the high bit.
In this notation, the DR Register is being shifted right with

A functional condition can be implied without the use of the “f” operator. A case in point is shown in ASH20.
EPS(Z)«D=0

Back in ASH19, both the BR and R[SF] were ORed on the RD BUS to determine the zeroness of the answer.
(P2:D<R[SF] ,BR). In this word then the condition set in the Z bit is determined by the result of that test. If the D
|

An example of the role played by the arrows on flow lines, to reduce confusion as to Wthh direction to take is
illustrated on sheet 3 of the EIS flows at the output of word MUL3. The horizontal flow line entering the output of
MULS shows that the MULS flow cannot go to MUL4 whereas the output of MUL3 can go to either MUL4 or
MUL19. Likewise the decision notes on these lines pertain to the output conditions of MUL3 and not of MULS.
Thisis further indicated by the fact that the D15 BUT was made back in MUL2.

In word MULL11, the following notation is made:
P2D<— BR

The use of ~BR indicates that the 1’s complement of the contents of BRis sent to D. To indicate 2’s complement, 0

MINUS 1 is used as illustrated on sheet 4 of the EIS flows at word DIV6:
P2:D<(0 MINUS B

An instance of multiple branches in sequence is given also on sheet 3 of the EIS flows at MUL20. In this word, a
BUT. for DR15 is made, and in the next word MUL11, a BUT for D=0 is made. This resultsin four branches: two
for DR15 and two each for D=0. The BUT(D"O) in MULL11 tests for the branch at MUL16 while the BUT(D=0)in
MUL1?2 tests for the branch at MUL13.

For customers with the FIS option as well, certain terminology in those flows is illuminating to the understanding of
the flows. These examples are separated here to avoid confusion on the part of those customers with only the EIS
option.

T —

The bracket can be used to designate a choice of registers, based upon other variable conditions defined by the
symbol “f’ which means “as a function of.”” This is illustrated at word FP10 on page 1 of the FIS flows.

P3:BR,B,FARGA(R[12+13])<D

In this case, the contents of reg1ster D are sent to the BR Register, to the B Register, and to e1ther register 12 or
register 13 as determined by the condition of the ARGA flip-flop. The ROM will always select the odd reglster in the
floating hardware if the ARGA flip-flopis clear. If it is set, the even register will be selected.
is illustrated in word FP15 on page 1 of the FIS flows. The statement is as follows:
The XORfunction
P2:D<BVMSR

In floating multiply or floatihg divi'de, the XOR of thesign is used to give 2 negative sign toithe answer if the ’signs of
|

the two operands are unlike.

An example of a parenthetical statement used as a description is seen in word FP7:

P2:D(15:08)«fSBC00; (ZERO)
D(07:00)<B(15:08)

4-23

loading the low byte of the D Register with the high byte of the B Reglster

The insertion of the hidden 1 is illustrated in word FP9.
P2: D<-4OO PLUS(OOO B(O7 OO))

This means the high byte on the B leg of the ALUis equal to 0 and the low byte wrll be B(O7 OO) The constant 400
is added to insert the hidden 1.

Concatenation is illustrated in word FMLlZlon sheet 4 of the FIS flows. The statement is as follows:
~

P1:MSR<HSRO0,MSR(15:01)
HSR<DROO,HSR(15:01)
DR<«BR00,DR(15:01)
BR<«D(C),D(15:01)

From this it can be seen how the four regrsters are concatenated with MSR the LSB and BR the MSB. This is a
SHIFT EVERYTHING RIGHT operation. A comparison can be made with the notations llstedin FDV 16 on sheet 5
of the FIS flows for a SHIFT EVERYTHING LEFT operation..

4,7.2

KD11-A Flow Discussion

A complete discussion of the KD11-A

is contained in both the PDP-11/40, PDP-11/35 System Manual (21"’ Chassis)

(EK-11040-TM-002) and in the KD11-A Maintenance Manual (EK-KD11A-MM-001). The discussion here is general,

containing merely that mformatron necessary for an understanding of the KE11-E/F OpthIlS and the ways that they
lnteract with the processor.

Referring to the KD11-A block diagram on drawing KD11-A-BD, the Unibus is shown
on the left with its 16 data

lines received and driven, and its 18 address lines that are driven onto the Unibus. In addition, the Unibus is driven

by the Switch Register KY11-D (which can oftentimes be addressed to retrieve data, e.g., in diagnostics) and by
processor status from the PS Regrster (K5 5)

The heart of the processor data path is the arithmetic logic unit (ALU). This unit has two inputs: “the AIN fed by
BUS RD(15:00) through a buffer and the BIN fed by the BMUX. Note that the BUS RD is also the bus on Wthh
data from the EIS and FIS Optlons are fed back into the processor.

The BMUX is fed by 1) the B Reglster stralght' through 2) the B Register with bit 7 extended into the high byte (a
sign extension), 3) the B Register with the two bytes swapped, and 4) the B constants of which there are many
including address increments, switch regrster address, and masks.

There are five ALU control bits originating in the control ROM. The SALUM determines the mode (arithmetic
or
logical). The other four (SALUX) select one of 32 functions that the ALU can perform (16 in idle mode). These
include (among others) carry-in logic from the EIS (only if the ALU is in arithmetic mode) and carry-out
multiplexing of four inputs to the D(C) flip-flop. The latteris usedin ASH rightin which the datais loaded into the

D Register through the ALU and the D(C) gets bit 15 of the D Registerso that the sign can be extended down _'
through the DMUX during shifting.

NOTE

ThlS is used on word operations. In byte operations, carry-out
I
|
7 is used for this purpose.

424

’ \\g;//'/

This says: at P2, bits D(15:08) will get Os as a function of SBC0O while bits D(07:00) get B(15:08). In effect the
high bits of the constant called for by SBCOO are 0, thereby putting Os into the upper byte of the D Reglster while

The COUT MUX also receives the C bit of the processor status for use in rotates.
During any of these operations, the B Register, which feeds the BMUX, functions as a storage register. Note that this

is the only holding register on the BIN side of the ALU. The general registers are on the AIN side via the BUS RD,
although they can feed the BIN side through the BMUX and B Register by virtue of a feed back through the DMUX.
Note also that the DMUX can also feed the options. The DMUXis not wire-ORed, it is TTL andis used to feed data
to the EIS and FIS.

BUS RD also feeds the bus address multiplexer (BA MUX). An address can be brought out of the general purpose
registers and fed directly into the BA through the BA MUX, or can be fed through the AIN of the ALU, added to,
subtracted from, or operated on in the many ways possible, and then fed to the BA via the BA MUX.

The processor status is also fed to the BUS RD for internal use, e g for a condition code instruction, and does not

have to be fed out onto the Unibus. It can be operated on in similar fashion as above without interrupting the
Unibus.

The BA Register contains logic on its output for decoding processor status address, stack limit register address (an
option), register address (internal registers are being addressed), and switch register address. There is also logic on the
D Register output to determine whether or not the D Register is equal to 0. The latter is used in the EIS option as
“described later.

The instruction register feeds logic to decode all the discrete instruction Op codes. These 16 bits are converted into
many signals which are then encoded back down into the U Branch Control which is 6 bits wide. The IRD code then

is used in the first FETCH branch so that the proper U Word can be accessed to perform the proper instruction.
The ALU control block
is actually an auxiliary ALU control fed by the ALU field in the ROM and by some discrete

logic. This is functionally a multiplexer used in common routines in which the discrete logic is used to control the
ALU rather than a separate ROM word for each 1nstruct10n In th1s case, a common ROM wordis used to’ pomf to
auxiliary control.

The U Word Control ROM contains
256 words, 56 bits wide, 8 bits of which comprise an address which doubles

back to a NOT OR into a pointer register (UPP). This register functions as a PC for the ROM with these 8 bits
specifying the next ROM address to be looked up. The rest of the ROM bits (48) control the internal machine and
the data paths, clock the BA and D Registers, and determine which multiplexer port will be active. Some bits are
gated with the basic clock pulses to control cycle length, others enable different reglsters to be clocked such as
CLKD whichis gated with P2 to clock the D Register.

The JAMUPP logic is used to jam the UPP Register to specific addresses for specific error conditions.

The PUPP Register holds the previous microprogram pointer or the address of the word that is in the U Reglster
Thisis used to feed the maintenance console d1splay

The condition codes input block is used to set up the condition code bits in the PS Register to indicate the results of
the last operation or instruction.

The Data Display on the console is fed by the DMUX. Since the DMUX can contain either Unibus data, the
D
Register straight through, the D Register shifted right, or the contents of the BUS RD, there are basically four
sources for display; and since the BUS RD can have many things on it such as the general registers, status, or option
data, the range of data displayed is very w1de In single instruction mode, processor status is displayed at the end of
the instruction.
-

NOTE

On a HALT instruction, the contents of RO are displayed and
not PS, even if in single instruction mode.

4-25

By referring to sheet 1 of the KD11-A flows (drawing KD11-A-F), the way in which the EIS/FIS options are enabled

can be followed. Entry is at FETCH A and proceeds to word 013 (FET00). This is the “Fetch Next Instruction”
word
in which, during a cycle length P1, the contents of the program counter (R[PC]) are loaded into the BA, a
DATI is performed,
the clock is turned off (CLKOFF), and the R[PC] is ’displayed. |
_.

NOTE

FETCH OVERLAP does not apply to EIS or FIS instructions.

A wait is indicated in the flow followed .by entry into word 001 (FETO03) to “store the instruction.” Here, in P1, the

Unibus data is sent to the B Register, to the general register, to R(IR) which holds a copy of what is to be loaded
into the IR, and to the instruction register. Bus data (Instruction Word) is displayed.
NOTE
o
The R[IR] copy provides a convenient way to access this
information when the IR is not accessible.

In the next word (FETO04), the PC is incremented (R[PC]+2) and put into the BA and D Registers. In addition a

branch test is made (BUT(INSTR I)), numerically BUT 37, to determine which flow exit indicator to take. Once
agarn the R[PC] is displayed.

The flow then goes to FETOS to store the modified R[PC] This is done by transferring the R[.P,‘C] +2, which Was
put in D in FETO04, fromD back into R[PC] in FETO5.

Normally, without the options installed, an EIS or FIS instruction would not be recognized by the processor. The
machine would branch off to address 100, the base U Word address for the branch, and take the TRAP B exit. But
when the options are installed, the BUT(INSTR I signal (BUT 37) is sent to the option where it is gated with a pulse
and sent back to the KD11-A to UPP bit 8 as the clock for bit 8 of the ROM address. The signal RSVD INSTR,

gated with EUPPS8, is sent back to the KD11-A as the data for UPP8. Setting bit 8 modifies the next address to be
~ looked up from 100 to 500. Note that now the flow exits through the expansion diamond and enters the EIS flows

at word EIO (location 500). Bit 8 remains set to enable the option ROM and disable the basic ROM.

If the option is installed and a reserved instruction is issued, the flow still follows this path and exits to TRAP D.
4.7.3

KEI11-E Flow Diagram Discussion

The KE11-E flows are shown on drawing KE11-E-FD, sheets 1 through 5. The format of these flowsis identical to
that of the KDll A and the conventrons follow those describedin precedmg paragraphs.
-

As descrrbed in Paragraph 4.7.2, entry into the expansion flows is at EIQ after the CPU has stored the EIS/FIS or
Reserved Instruction in the IR, decoded the IR, made a branch microtest, set R()M bit UPP8 modified the address
to 5008 , and set the CPU Trap flag.

At this point the KE11-E ROMs are enabled and EIS ROM word EIO is present on the wire-ORed BUS U(56 00)
lines at the input of the CPU U Register, as are the outputs of the KE11-E Control ROMs U(80:57) at the input of
the EIS U Register. The KE11-E performs another decode of the CPU IR and does a branch mrcrotest
(BUT(EINSTR I)) to determine what address calculation flow to enter. The CPU Trap flagis cleared
NOTE

If the instruction was not one of the EIS instructions, the CPU
‘Trap flag would not be cleared here in order that a RSVD
INSTR trap would occur upon exit back into the CPU Trap
~
flow,

4-26

The above sequence occurs for each EIS instruction. Upon completion of the EIS instruction, the microflow returns

to the basic KD11-A microprogram at rmcroword SER,, at ROM address 175.

Note that if it had been a reserved instruction and not an EIS/FIS instruction, the flow would be from EI1 to

address 640 (EI2) to form the vector 10 and clear the UPP8 bit. Then at EI3, the Special Trap Pointer Marker

(STPM) previously sent to D is stored by transfer to Scratch Pad Register R[VECT] and B. Exit is to TRAP D at
microprogram address 7.on sheet 6 of the KD11-A flows. The entry point of TRAP D into traps differs from that of
the TRAP B, used by the basic machine. TRAP B forms the vector and stores it, Whereas at TRAP D this has already

been donein the option.

There is an overlap in this transition back to the basic machine that is similar to the transition from the basic
machine to the option. At the end of EI2, UPP8 was cleared and at that instant the expansion ROM was disabled
and the basic ROM enabled. In word EI3, while the data path is setting up to store the vector, a new ROM word is
being looked up. That new word comes from the basic ROM so that the last expansion word is being executed at the
same time that the basic ROM word is being fetched. The same thing happened when the CPU vectored for the
expansion. Bit UPP8 was set at the end of FET04 and the contents of FETOS were loaded into the U Word Register.
While the FET05 was being executed in the data path, the next word being looked up was in the expansion ROM.

4.7.3.1

Destination Calculation —

Sheet 1 of the EIS flows describes the destination calculation operations

required to perform the four fixed-point instructions.
- NOTE

The FIS exit is directly from word EI1.

The BUT(EINSTR I):EUB=17 in EIO tests the path to be taken in terms of destination mode of addressing (DMO
through DM7) as determined from the destination mode bits in the instruction. Each path performs the functions
necessary to calculate the destinations as a function of these modes. In all paths, two words prior to the instruction
exit, the branch test BUT(EINSTR I):EUB=16 is made to determine which instruction is called for. This is
determined from the Op code of the instruction.

The operation of this flow
is almost identical to the basic DEST flow for the processor as described in the KD11-4
Muaintenance Manual (EK-KD11A-MM-001). One exception is word DST8, through which all other paths flow

before branching. In this word, the Unibus data (which is the data from the final destination address) is sent to
R[DEST] (the register specified by the destination field of the instruction). It is also sent to B and BR. The
exception is word DST1 which does not go through DST8. Note that both words accomplish the same operation
except that DST8 gets data from the Unibus and DST1 gets it from an internal reglster In DMO, there is no need to
go to the bus for data since the register contains the operand.

At the conclusion of this flow, the data retrieved from the calculated destination resides in BR, B, and R(DEST).
4.7“.3.2 Arithmetic Shift and Arithmetic Shift Combined — The shift flows are shown on sheet 2 of the EIS flows
and in Figure 4-8. In this operation, the data fetched from the calculated destination is a shift count that also
indicates the direction in which to shift. The bits to be shifted are in a register designated by the source field of the

instruction. If the instruction is ASH, 16 bits are to be shifted and the result will be storedin BR, B, and R(SF) If
the instruction is ASHC, 32 bits are to be shifted, with the high 16 bits taken from an even register specified by the
source field and the low 16 bits from that register ORed with 1. The results are stored in BR, B, and R(SF) (high

answer) andin R(SFVl) (low answer)

427

NOTE

‘

In ASHC, 1f an odd regrster is specified by the source field of

\__///

the IR, the ORing process
in the hardware will resultin two

duplicate operands being fetched. If an odd Source Registeris
specified, the low 16 bits of the answer will overlay the high
16 bits of the answer.

ASH is entered at word ASHO at location 605. At P1, the 8 bits of data in the BR(07:00) are loaded into the
counter and the BR is cleared Prror to that pulse, however, bits(05: 00) of the BR are tested (EUB=13) to determine

the branch after ASHL.

~
-

ASH

ASHC

LOCATION

OF OPERAND

BR, B, R[SF]
OPERAND

|BR, B, R[SF]
|

DR (R[SFVI])

LOCATION

ANSWER

HIGH OPERAND | LOW OPERAND

OF ANSWER

BR, B,R [5F]

LOCATIONS OF OPERANDS

LOCATIONS OF ANSWERS

8RB, RISF]
HIGH

| ho (R sFVIT)

ANSWER

11-1625

Figure 4-8 ASH and ASHC Locations of Operands and Answers

In ASH1 at P2, the register specified by the source field (R [SF]) is sent to the D Register, the V bit in the local

‘status is cleared, and the count is clocked one time. At P3, the contents of the D Register (R[SF]) are loaded into
the BR and B Reg1sters This is the data to be shlfted

If, back in ASHO the result of that BUT indicated that bit 05 of the BR was set, a shift rrght operatlon was

“indicated, causing the flow to proceed now to ASH3 where the count is incremented and the branch microtest

(EUB=10) is set up for the shift loopin ASH4. The count is clocked at this point so that the shift loopin ASH4 will
not be executed more than the specified amount. Note that in one word loops, the wordis always executed one time

more than the count on initial entry would indicate. This is because of the overlap of executing the present word
while looking up the next word and by the fact that branch tests are made two words ahead of the actual branch
point.

In ASH4, the rrght shiftis implemented by putting the general register specrfied by the source field through a buffer
and through the AIN¢of the ALU into the D Register. At the same time, ALU bit 15 is sent to the D(C) flop via the
COUT MUX and ALU bit 00 is sent to EPS(C) This occurs at P2 of a cycle length 3. At P3 of that word, D(C) and
' D(15:01) are fed through the DMUX right shift data port baek into the general register R(SF). Remember, in this

operation D(C) is equal to D15. In addition to this, data is sent to the B and BR Registers and the count is

answer is in three places: R(SF), B, and D. Note that the counter is dlsabled from counting when count brts 5

through O are equal to O.

incremented. This operation continues, shifting right one bit position for each pass through the loop, extending the
sign down and putting the low bit of the ALU into the EPS(C) bit until the count is equal to 0. At this point, the

428

of B are sent to D for the zeroness test at P2, and the flow progresses to ASH20 where
In ASH14, the contents
BR15 (the sign of the answer) is sent to the N brt of the EPS and the result of the zeroness is sent to EPS(Z) If the
contents of D were 0, EPS(Z) will be set.

)

This word continues on to ASHIS 1in which the status bits EPS(N) through EPS(C) are transferred to the processor

status in the basic machine. Note that in ASH20 there is no need to set either the V bit (setin ASH1) or the C bit
(setin ASH4) In ASH15, the UPP8 bitis also cleared to transfer ROM control back to the basicmachine.
ASH2l is a No Op word that loads Os into the upper 24 brts of the ROM Regrster Thrs is done for housekeepmg
reasons so that upon reentry to the Optron no extraneous bits will be leftin that reglster

From here the flow exits to SERVICE C (location 173) on sheet 10 of the KDll A flows Everytrme the optron is
exited, the flow is through this route to test 1f an 1nterrupt or trap is pendlng If one is pendrng, it is serviced before
-

ontrnurng to the next instruction.

If, back in ASHO b1t 05 of the BR was cleared and BR(O4 00)#0 a shrft left operatron was 1nd1cated causmgthe
flow to proceed from ASH1 to ASH5 where the count is decremented instead of being 1ncremented as in ASH3. The
|

same BUTis made (EUB=10) and ASH6is entered for a shift left operatron

In thrs case, shifting does not take place in the DMUX but rather in theALU by the function A PLUS A. In this
case, BR15 goes to C rather than ALUQO. The statement EPS(V) gets 1 if BRIS#BRM refers to the sensing for sign
change. If when shifting, these bits are different, an impending change in sign is indicated and the EPS(V) bit will be
set. This bit will then remain set even if more shifting is necessary so that at the end of shifting the programmer has
an indication of sign change. This shifting continues with the count being decremented for each pass until the count
~
is exhausted. The sequence from that pornt on is 1dentrcal to-a right shrft

In the instance of no shift (BR(05:00)=0), the EPS(V) and EPS(C) bits are both cleared, BRIS is sent to the EPS(N) |
bit, and the EPS(Z) bit is conditioned by the zeroness test of D. This progresses to ASH15 for transfer, ASH21 for
cleanup, and out to SERVICE C.

The ASHC flow is similar to the ASH flows except that now 32 bits are involved instead of 16. Entryis at ASHC to

word ASH7 at location 607. At P1, the low 8 bits of the BR are loaded into the counter and the low operand
(R[SFV1]) is put in the BR. At the same time the EPS(V) bit is cleared. Prior to that, before the count has been
transferred out of the BR, a BUTis made to determine what branch to take (shift rrght shift left or no shift).

In ASHS8, the low 16 bits that are now in the BR are sent to the DR Register and the hrgh operandis taken from the

even register (R[SF]) and put into the D Register. These operations occur on P2. On P3 of that word, the high 16
bits, now in D, are transferred to the BR and B Registers. At the same time the count is clocked. At this point, the
data to be shifted comprises 16 bits of low operand in the DR and 16 bits of high operand in the BR and B
Registers. Note that the low operand went through the BR and was moved out to the DR before the hrgh operand
,

was put:into it.

If the result of the BUT indicates no shift, the flow is to ASH9 where the R(SFV1) and BR are simultaneously sent

to D, effectively ORing the high and low operand on the BUS RD to determine zeroness of the full 32-bit operand.
In ASH2, the local status is set and moved to the processor in ASH15 as before.

If a rrght shift is 1nd1cated the count is tested for zeroness in ASHIO the BUT is set up for theloop and the rlght .
shift loop is entered (ASH11). Here the lower 16 bits are shifted in the DR Register while the high 16 bits are sent
through the ALU and shifted in the rrght data port of the DMUX. This operation is identical to thatin ASH. Since
the BR and DR are concatenated, BROO goes into the high bit position of the DR while the low bit of the DR is put

into the EPS(C) bit. All this occurs on P2. At P3, the right data port of the DMUX is fed back into the source

(R[SF]), the B, and the BR Registers, and the count is incremented. This loop continues until the count equals 0

(EUB=10) at Wthh time the loopis left and the flow continues to ASH12.,

4-29

The low answer in the DR is sent to D in ASH12 and stored into the odd Source Registerin ASHI3. In ASHI19, the
high answer (BR) and the low answer (R(SFV1)) are sent to D so that the zeroness test of the 32-bit answer can be
- made by ORing on the BUS RD; and in ASH20, the EPS(N) and EPS(Z) bits are loaded prior to transferin ASHIS

Operation of ASHC leftis similar to ASHC right except that the count is decremented and the operatron of the shrft
loop differs in the same way that it didin the ASH instruction. In shift left ASHC, the low halfis shiftedin placein
the DR Register, with O being put in the low bit (DR00). The high halfis shifted by the A PLUS A function of the
ALU. At P3 of ASH17, the D is put back in the BR, B, and Source Registers. In ASH18 the low answer is put into
:

D (same as ASH1?2) and the flow continues as in ASHC rrght

Note thatin ASHC operatron the hrgh part of the answer does not have to be stored as that was accomphshedin the
loop

4.7.3.3 Multlply The multrply flow is shown on sheet 3 of the EIS flows andin Frgure 4-9. In this operatron the
data fetched from the calculated destination is the multiplier, and the data from the register specified by the source
field (R(SF)) of the instruction is the multiplicand. The two 16-bit numbers are multrplred and the 32-bit resultis
|

storedin R(SF) (high product) and in R(SFVI) (1ow product)
NOTE

~In MUL, if an oddR(SF) is specifiedin the 1nstructlon the
low product will overlay the hrgh product

Entry is at MUL to MULO at location 601. The multiplier from the destination address had been loaded into the BR,

B, and R(DEST) Registers during DST1 or DST8. The count (17g) is generated and put into D at P2 and into BR
.

from D at P3 A BUTis set up for the srgn of the multrplrer (EUB—3)

—

* (MULTIPLIER)

DMUXSHIFT RIGHT

1} muLTiPLICAND e
"1 HIGH PRODUCT |———
= Low PRODUCT |
e

()
11-1626

- Figure 49 MUL Flow, Block Diagram = In MULl the 2’s complement of the multiplier is taken. This is done at this point in case the negative multrplrer
'branch 1s called for In thrs word, the EPS(C) bit 1s cleared and the count is transferred from the BR to the counter..
If BRIS was set on the BUT, the next word is MULZ in whrch the multrphcandis put mto the BR from the source
‘field desrgnated regrster and a BUTis made for the state of D15 (EUB—I)

4-30

‘

In MUL3, the multlpllcand is put into the DR and the contents of the Source Field Register is put into D. If as a
result of the BUT in MUL2 D15 was 1 (note, this was what was in D at that time or the 2’s complement of the
multlpher) then the multiplier is determined as being the most negatwe number since thatis the only number that
can be 2’s complemented and remain negative. In this event, the flow goes to MULA where the copy of the

| multrpherin R [DEST] is now sent to the BR.

NOTE

‘Thisis the uncomplemented multiplier, The complementatlon
donein MUL1 was for testing purposes.

Another test for D15 is made in this word, and in MULS the multiplier (in BR) is sent to DR and BR is cleared.
~

NOTE

Normally the multlpller would be put in B when the loop was
started, but the most negative multiplier must be put in the
~ normal position of the multrphcand to produce the correct
result

If the multlpher had proven to be posmve in MULO, flow would have gone to MUL7 where the Source Reglster
would have been loaded into the BR Register, and from BR into DRin MULS, and then the count would have been
|
decrementedin MUL19 to take care of the one-word loop drscrepancy describedin ASH.

In MULS, returning once again to the flow for the most negative multrpller the flow branches again as to the 31gn of
the multiplicand. This is indicated by the state of D15 since the multiplicand (R[SF]) was loaded into D back in

~ MULS3. In this flow, the sign of the multiplicand must be tested also since a most negative number can never be
placed in the B Register. Since one operand has been determined to be most negative, the other Operand must be

| tested for that characteristic as well.

If D15 is clear at MULS, no problem exists and the mult1p11candis put into B as the count is decremented If D15 is

set, however, the flow goes to MUL21 where it (the multiplicand)is tested for being the most negative number. This

time the 2’s complement is taken by subtracting the Source Field Reg1ster from the B Reglster (already estabhshed

~as being the most negative number).

‘NOTE

BUT(COUNT—O) EUB=10
is done here to clock the NPR and
Bus Request flags and to clear the Bus Busy flag in the
KD11-A (see Note 2 on sheet 3 of EIS flows).

If the result of the comparison just done in MUL21 is 0, the indicationis that the multrplrcand is also the most
negative number and the answer can be generated at this point in the flow without contmumg w1th the
-

multiplication.

After zeroing the low answer in MUL23, the flow branches to MUL24 and the hlgh product is shlfted rlght one
place

NOTE

The most negative number times the most negative numberis

equal to that number. shifted right one place as the high
product and with 0 as the low product

- 4-31

In MUL25, the answer in DR is put into D and stored in the Source Field Registerin MUL26. The local condition

codes are set and the flow exits to the MOVE EPS point in the ASH/ASHC flows. This is ASHIS, the common

transfer point to the Processor Status Word before returning to the service routine.

If, back in MUL23, the multiplicand proved not to be the most negative number (-D=0), it is put into the B Register
at MUL27 and the count is decremented.

This brings the flow to the common pornt of all flows descrrbed for multiply so far Thrs is the entry point to the
multiply loop at MULO.

The multlply operation is essentially a rrght shift operation through the right data port of the DMUX It is a

functional operation of the ALU, determined by the instantaneous conditions of bit 00 of the DR Register and the
EPS(C) bit. (See the table to the right of this block.) The contents of BR and B will be either subtracted or addedin
the ALU before being shifted one bit postion to the right through the DMUX, or the ALU will put the data straight
through before it is shifted.

One of these operations will occur prior to each shift for each pass through the loop, depending upon the states of |

the two conditioning bits for the ALU. At P3 of each pass, the high product is being assembled in the BR and the
count is decremented. This continues for 16 passes, at which time the count equals 0 and the loop is left.
NOTE

The notation GPC=2; DAD=14 at P3 of MUL9 pertams to

generation of auxiliary ROM control. The DAD codeis for the

“basic machine auxiliary ROM control enable and the GPC code
is for the option auxiliary ROM control enable.

In MULlO, the high product 'that has been assembled in BR is sent to D; in MUL?20, it is stored in the even Source

Field Register. At this word, a test is made of the sign of the low product (BUT(DR15):EUB=5) in preparation for

setting the C bit in the EPS. If the result is less than -2'* or is greater than or equal to 2' ®-1, this bit must be set,
otherwise it is cleared The result is represented in BR (high product) concatenated with DR (low product) and to

determine the proper setting of the EPS(C) bit, the high bit of the DR (bit 15) must be compared with the entire
contents of the BR. IF BR contains all 1s and DR15 is also a 1, the answer can be represented by just the low 16
bits. Similarly, if DR15 is 0 and the BR is all Os, the high 16 bits are still an extension of the MSB of the low 16 bits
and the answer can still be expressedin one word.

In MULL11, the high product is complemented and sent to D. The EPS(V) bit in the local status is cleared, and the

BUT for D equal to O (EUB=4) is made. This is done because if D is equal to 0 after complementmg, then it was all
Is.

- Coming out of MUL11, the branch is made. If DR15 was 0 the low product wasposrtrve and the flow proceeds to

MULI16 where the EPS(C) bitis set and the DRis put into D, At the branch coming out of MUL16, the result of the
test for the state of D in MUL11 determines the flow. If it had not been 0, the EPS(C) bitis left set, the other status
bits are set, and the low product now in D is sent to the odd Source F1e1d Register. This occurs in MUL18 from
which the flow exits to MOVE EPS on sheet 2 of these flows

If D in MUL11, had been 0, the flow is to MUL17 where the EPS(C) bitis cleared once agarn, the other status bits
are set, and the low productis sent to R(SFV1) as in MUL18.

If, back in MUL20, DRIS was seen to be 1, "similaraCt,ions take place in MUL12,AMUL13, and MUL14 or 15. The

EPS(Z) bit is set if the productis equal to 0 andis cleared otherwise. The EPS(V) bitis cleared and the EPS(C) bitis
~

set or cleared according to the already stated criteria.

432

‘status bits are set accordingly with the EPS(N) bit set if the product is less than O or cleared if it is more than 0. The

From all of these flows ‘the resultant status is transferred to the Processor Status Word (MOVE EPS), the high

product was storedin the even register in MUL20, and the low product in the odd register in the steps Just described.
The flow then proceeds to SERVICE as in other operatrons |

4.7.3.4 Divide — The dlvrde flow is shown on sheets 4 and 5 of the EIS flows andin Flgure 4- 10 In thls operatron
the data fetched from the calculated destination is the divisor, and the data from both the register specified by the
source field of the instruction and thatregister ORed with 1 is the dividend. The high dividend is taken from the
even register and the low dividend from the odd register. The 32-bit dividendis dmded by the 16 brt divisor and the
o

results are storedin R(SFVl) (remarnder) and R(SF) (quotrent) |
NOTE

In DIV, an even R(SF) must be specnfred

Entry is at DIV to DIVO at location 603 In this word, the count is generated from the SBC code of 12. This
generates an octal 17 or decimal 15, prov1d1ng the 16 passes through the divide loop Thisis loaded into D at P2 and
.

from there to the BRin P3.

ALy

omux

———

RDMUX

| SHIFT LEFT
lorss

BR
HIGH DIVIDEND

_DIVISOR

;

|
l

QUOTIENT

REMAINDER

LOW DIVIDEND

| \ BR [14:00]

n-1627

- Figure 4-10 DIV Flow Block Diagram

At DIVl the divisor in B is sent to D; and in DIV2 the count is loaded from BR. At the same time (P2), the hrgh
dividend in the even Source Register is loaded into BR and a test is made of the D Register which holds the divisor.
If it is 0, then the divisor is O and the flow will go through DIV3 (a No-Op) to DIV4 where the EPS(ZV ,C) bits are
set before exrtrng to MOVE EPS D1V1de by 0is undefined andis not executed

If the divisor is not 0, DIVS is entered where the low d1V1dend (R(SFVl))is putinto B and the EPS(N) bit is set to‘
the state of BR15. Thisis the sign of the dividend. The test BUT(BRIS) EUB 3is set to test the srgn of the dividend
for the branch from DIV6.

In DIV6 the 2’s complement of the low drvrdend is taken. This is done in the event the negatlve dividend path at
DIV7 is to be taken, and it affords a chance to make the dividend positive before operating on it. If the negative

~ path is not taken, nothingis destroyed by this complementlng At the same time, the carryout of b1t 15 of the ALU
|

(COUT15) is storedin EPS(C) for future use.

4-33

At P3 of DIV6, the complemented drvrdend is put into the BR and the BUT(COUNT"()) is made to clear any
|

hinderances to NPRs..

If BR15 was (1) in word DIVS5, the flow is to DIV7 where the high dividend is sent to B so that a 2°s complement of
it can be taken in DIV8. Note that the carry-out stored in EPS(C)
in DIV6 is now used as a carry-in to effect the 2’s
complement. This arrangement provides the 2’s complement of the total 32-bit dividend. A BUT is made here to
=3) which tests bit 15 of the BR.
determrne whether or not the d1v1dendis the most negatrve number (EUB

| In DIV10, the drvrsor in R(DEST) is sent to B for use in DIV16 but 1f BR15 proved to be a (l)in DIV9 its not

needed and the DIV QUIT path is taken to DIVI1I (a No-Op) and DIV12 where the condition codes are set

approprrately and the flow exits to MOVE EPS.

NOTE

DIV QUIT is taken because division into the most negative

number results in more than 15 bits of answer.

If BR15 proved to be a (0) in DIV9, the 1nd1catronis that the dividendis not the most negatrve number and DIV16
|

is entered for the first division step.

Before entering DIV16 in this discussion, the flow is taken back to DIV13 which would be entered if the dividend
was determined, in DIV3, to be positive. In this case, the low dividend is moved to BR and from BR to DR in

DIV14. At the same time, the high dividend is put into BR. Then in DIV15, the divisor is put into the B Register.

From either path, the entrance into DIV16 sees the divisor in B and the full d1V1dend in BR and DR, with BR
holding the high 16 bits.

The first division step is done at DIV16. The operatronin thrs step, in DIV19 andin the loop of DIV?20, is to shift
then add, or shift then subtract.

Note from the statement in DIV16 that the D Register will be loaded with BR(14:00), DR15 and B as a function of
B15. This process can be followed on the block diagram to the top right of the sheet. There it can be seen that the
BR concatenated with DR15, shifted left one bit position through the RDMUX and fed to the AIN of the ALU,
while the B Register (the divisor) is fed to the B input of the ALU. Depending upon the state of B15, the ALU will
add B to or subtract B from the AIN data of the ALU and feed it to D, through the DMUX to BR. The carry-out, bit
15 of the ALU, is shifted into the low end of DR as the partial quotrent while a remainder (if thereis any)is being
formed in the BR.

For divide, there are two possible criteria that determine auxiliary ALU functions. One has already been mentioned

(B15) and this is the determinant whenever DAD=14 in the basic ROM is asserted. The ALU functions for the two
‘states of B15 are given in a table to the right of word DIV16. The other criteria are given in the table to the left of
'DIV20 in which the dual conditions. of both B15 and DROO are the determinants. These are used upon the
simultaneous assertion of GPC=2in the optronROM and DAD=14in the basic ROM. Note DROOis the result of the

last add or subtract.

At DIV16, just the state of B15 is used (DAD=14 is asserted) Since the 2’s complement of the divisor has already

been taken, and since if after complementing the high bit was still a 1, the most negative number would have been

‘indicated; it is known at this point that B15 is 0. Thus, the first shrft wrll take place followed by a subtract
operation. The count is decremented, making the count equal to 14.

‘The flow then progresses to DIV17 where the size of the quotient is determined with respect to the abilityof the
‘hardware to express it. If it is greater than 16 bits, it exceeds the capability of the machine and the DIV QUIT path
is initiated. As such, DIV17is.a No-Op merely to establish the test BUT (DIV QUIT): EUB=7. This test looks for the

three possible sets of conditions expressed in the formula to the right of this word. Thisis really a test for overflow.

434

In DIV18, the count is decremented and the C bit is cleared to indicate that divide by O was not attempted. This
reduces the count to 13.

At this point , if DIV QUIT was not indicated back in DIV17‘, the flow is to DIV19 which is the second division

step. Here another shift is accomplished as described above except that now both B15 and DROO are used as criteria
for adding or subtracting after the shift (GPC=2 is asserted). The count is decremented, putting the count at 12.

Word DIV20 is the divide loop in which the arithmetic operations are performed according to the same determinants
(BR15 and DROO) until the remaining 14 passes are completed. The BUT for count equal to O is also set in this
|

word.

Upon completion of the count, the flow exits to DIV A on sheet 5 of the EIS flows for the completion of the divide

- operation.

The object of the steps on this sheet is to ensure that the sign of the remainder is the same as that of the dividend. If
the remainder must be stored as a negative number and vice versa. Further, the sign of the
the dividend is negative,

quotient must follow the algebraic rule that division of two negative number (or of two positive numbers) produces

a positive quotient, whereas one of each produces a negative quotient. Furthermore, since the division process

* subtracts ascending orders of the divisor, an excess operation may occur. Therefore, the remainder might have to be
corrected away from O before it is stored.

Entering the flow on this page shows the remainder stored in D (DIV21) and then stored in the odd register

(DIV22). The test in DIV21 (EUB=12) is made to determine which path to take at the branch from DIV22. This test

looks at the states of B15 (the sign of the divisor) and DROO (the low bit of the quotient). The latter indicates
whether or not a correction must be made. If DR00=1, no correction is required, but if DR0O0=0, a correction is
required. If B15=0, a positive divisor is indicated; if B15=1, a negative divisor is indicated.

Note that the extreme left-hand path to DIV23 is taken if the divisor is positive and no remainder correction is

needed. The next path is taken if the divisor is positive and remainder correction is required. Note here (DIV27) that
the correction adds the divisor (B) to the remainder (BR), correcting away from 0. The next path to DIV31 is taken

if remainder correction is required for a negative divisor in which correction away from O results in the divisor being
subtracted from the remainder. And the last path to the right is taken to DIV23 if the divisor is negative and no
remainder correction is called for.

" The second word in these two central correction paths stores both the corrected remainder in D in the odd Source
Register and in the BR Register. The copy in BR is used for 1’s complementing and is transferred to D in case the
dividend is deemed to be negative by the BUT (EUB=2) in either words DIV23 or DIV33. In words DIV24 or
|

DIV34, the complemented remainder is returned from D to B and BR.

At this point in either DIV23 or DIV33, the results of the BUT(SDIV) are used to guide the flow either to the
positive dividend paths (-SDIVD) or the negative dividend paths (SDIVD). Note that at this point the sign of the
|

divisor is already implicit in the path.

The path from DIV24 to DIV25 is taken if both the dividend and divisor are positive. This indicates that the
quotient will also be positive. In DIV25, therefore, the quotient is sent to D and BR from DR; in DIV26, it is stored
in the even register from D, while the status bits are appropriately set before exit to MOVE EPS.

The path from DIV34 to DIV35 is taken if both the dividend and divisor are positive. Once again the quotient will
“be positive and the same exit path as above is taken through DIV26, after the remainder is 2’s complemented in
DIV35 and stored in DIV36.

The other two paths (from DIV24 to DIV29 and from DIV34 to DIV37) are taken if the signs of dividend and

divisor are different, yielding a negative quotient. From DIV34 to DIV37, no complementing of the remainder is
4-35

‘required before complementing the quotient. The corrected remainder was already stored back in DIV32:-however
from DIV24 to DIV37 the remainder must be complemented before complementing the quotient. ThJS is done in
DIV29 and DIV30 where the remainderis storedin the odd register.

Entering DIV37, the remainder has been properly stored and the flow is concerned with storing the quotient as a

negative number, together with determining if that quotient is or is not the most negative number (100000).

At DIV37, the quotient is 1’s complemented (1n the event that it needs to be at the branch out of DIV39) in
- DIV38, it is stored in the even register (as well as in B) DIV38 also sets up the BUT for D15 (EUB=1), the high bit
~ of the complemented quotient. This is done to see whether or not the quotient is negative after 1’s complementing.
In DIV39, at P2, 1 is added to the 1’s complement of the quotient to see 1f it is a most negative number after 2 S
complementing. This test occurs between P2 and P3 of that word.

NOTE

This is one of the few cases in which a BUT is made in the
same word with the modification of that data. The data is
modified on P2 and tested from
P2 to P3.

At P3 the 2’s complemented quotient is stored in the even register. If the result of the BUT in DIV38 found D15 set,
the quotient is not the most negative number and the quotient is stored in DIV26 where the status bits are also set

before exiting to MOVE EPS. If, however, the result of the BUT in DIV38 found D15 cleared, the quotient was
indicated to be a negative number,
and in DIV40, the local condition codes are set to indicate that.

Coming out of DIV4Q0, the results of the BUT in DIV39 come into play and if D15 tested to be clear, the quotient is
deemed to be negative but not the most negative. This flows through a No-Op at DIV42 to MOVE EPS; but if D15
tested to be set in DIV39, the quotient is the most negative number andin DIV41 the EPS(V) bit is altered to (1).

The flow exits to DIV QUIT.

4.7.4 KE11-F Flow Diagram Discussion

The KE11-F flows are shown on drawings D-FD-KE11-F-FD, sheets 1 through 6. The format of these flows is

identical to that of the KDI11-A and the KE1l E and the conventions follow those described in preeedmg
paragraphs.

Entry into the FIS flows is through the KE11-E, initialized in a similar manner to that described for the EIS option
in which the flow follows through FETCH and then BUT 37 sets bit 8 of the ROM address. This sends the flow over

into the expansion ROM entering the EIS flows as described before. When BUT(EINSTR 1) is raised in the EIS,
decoding takes place to recognize whether it is an EIS or FIS instruction; and if the outputs of that decoding yield
IR=75xxxx, that signal is sent to the FIS hardware where it is gated with the proper IR bits for an FIS instruction. If
they compare, a signal is sent back to the EIS branching logic forcing a branch to the FIS EXIT and from there to
the FIS entrance on sheet 1 of the FIS flows.

4.7.4.1

'F IS Entry Sheet 1 of the FIS flows describes the FIS entry operation Entry to this flowis at FIS to FPO

at location 642. Here the floatrng stack pointer (R(DF)), pointed to by the destination field of the instruction, is put

into the BA. Also the DATI is initiated and the clockis shut off to await memory response. The contents of R(DF)

point to the high B argument on the stack containing the sign, the exponent and the high part of the mantissa.

4-36

There are two passes through this flow in fetchjng and storing the arguments. The first from FPO through FP13

fetches and adjusts the B arguments. The second from FP1 through FP14 fetches and adjusts the A arguments

(Figure 4-11).

R+6

]

LOWA ARGUMENT

R+ 4

A ARGUMENT

LOW MANTISSA

SIGN,

EXPONENT,

HIGH

MANTISSA

LOW B ARGUMENT | LOW MANTISSA

HIGH B ARGUMENT -

SIGN,
EXPONENT, HIGH MANTISSA

R+ 2

HIGH

11-1624

- Figure 4-11

Floating-Point Arguments Order on the Stack

FP1 strobes the argument in off the bus and places it in three places 1) in BR, 2) in B, and 3) in R(11), the odd
register. Note that the general purpose register that is used for storage (10 or 11) is a function of ARGA. The ROM
always specifies the odd register in this flow, but when ARGAis set (only during the second pass through the flow)
its setting diverts the argument fetched to the even register.

In FP2 at P2 the hrgh B argument in the BRis put into the DR the pointer is 1ncremented by 2, and a DATI is
initiated in preparation for getting the low B argument. At P3 of FP2, the incremented pointer is returned to R(DF )
and the clock is turned off. After a wait for memory response, FP3 strobes the low B argument into R(13) and into

The low B argument is sthted left in FP4 by addrng it to itself. Note that in FP3 the low B argument is sent to B,
and in FP4 those contents are added to the same data in R(13), then sent to D as the carry-out 15 is saved in

EPS(C) At FP3 then, the shifted datais returned to R(13)

FPS puts the high B argument which was storedin R(11)in FP1, in B and FP6 shifts it left. This srngle bit-shift to

the left puts the entire exponent that was partially in the low byte into the high byte. In so doing, the sign bit is

shifted out (not lost, stillin BR) and the EPS(C) bitis inserted at the low end. The carry-in to the ALUis enabled by

GPC=4. This double-precision shift operation makes it appear that the full 32 bits were shrfted at once and provrdes
an extra bit position on the low end of the low B argument for future rounding purposes. At P3 of that word, the
shifted high B argument is returned to B and R(1 1)

Word FP7 is used to separate the exponent and thh mantissa and to put the exponent in the low byte of a testable
word. To do this, the high byte of D is forced to 0 (SBC00) and the exponent (B(15:08))is sent to the low byte of
D. This is done for future overflow or underflow testing. These conditions will be 1ndlcated by what happens to the
high byte of D (1s from the right
= overflow, 1s from the left= underflow).
|
~

In FP8, the separated exponent'is sent from D to R(15) and if D was equal to 0 (0 exponent) the EPS(Z) bitis set.
Note that ZB is not relevant on the first pass through this flow. The zeroness of the exponent is also tested for
branchrng at FP10 (BUT(D=0):EUB=4) so that if it is 0,a 0 argument will then be generated
3

4-37

At FP9, the hidden 1 is inserted (all numbers are assumed to be normalized). A CON field=0 is asserted, generatinga

constant of 4005 which is gated onto the BUS RD to AIN of the ALU and then added to Os for the high byte, and
to B(07:00) for the low byte of the BIN port of the ALU.
|
NOTE

At this point, the B Register holds the high mantissa (shifted
left in FP6). The previously separated exponent is in R15, and
the sign is in the copy of the hlgh B argument storedin BR
backin FPl

Word FP9 also BUTs the state of the ARGA flop which for this first pass is cleared. Coming out of FP9, the results
of the test for exponent (D=0) in FP8 are felt.

If the exponent was O at that time, the flow goes to FP10 where a O is generated for the whole argument. The D

Register is first zeroed and that is then used to O every appearance of the low B argument (BR, B, and R(13)). At
FP11, the D is used to zero the high B argument in R(11) and the ARGA flopis set. Note that the ARGA BUT was

in FP10, however, directing the flow now to FP13.

If, back in FP8, the exponent proved to be not equal to O the flow from FP9 is to FP12 where the pure high B
mantissa in D is storedin R(11) and the ARGA flopis clocked before proceedmg to FP13.
NOTE

The hidden 1, inserted at FP9, is used only if the exponent #

0. If exponent is 0, the 1 is destroyed in FP10 and FP11.

In FP13, the sign of the B argument, still in BR, is saved in MSR and in EPS(N).; The stack pointer is updated'in the

D Register to point to the high A argument, and then put back in R(DF) at P3 of this word. Once again the DATI is

initiated and the clock is turned off to wait for memory to respond.

From FP13, the flow is to FP1 to fetch the A argument. The fact that ARGA flop is now set overrides the low bit of

the register address and causes the even general registers to be selected. Now fARGA will select R(10) for storage of
the high A argument, R(12) for the low A argument, and R(14) for storage of the A exponent. All other operations

are identical to the fetching of the B arguments previously discussed, except that this time in FP8 the zeroness of the

B exponent in EPS(Z)is transferred to ZB, and the zeroness of the A exponentisput into EPS(Z). Now the status of
both exponents can be used in FMUL and FDIV to determine automatic generat10n of a O answer. Also, this time
the ARGA flop is clocked to the clear state so that odd or even register selectlon can be determined by the ROM or
‘the 1nstruct10n

Commg out of FP11 or FP12 in th1s pass flow is to FP14 since ARGA was set at FP9 In this word, the high A

argument (storedin DR at FP2)is sent to B and the decodmg of the instruction is made (BUT(FINSTR I):EUB=15).

At FP15, the high A argument in B and the high B argument in MSR (stored in FP13) are sent through the ALU to

be XORed. The MSR is also sent to the BR via the DMUX. The XORis taken at this pomt to determine the S1gn for
FMUL and FDIV.

From here, the floW exits to the appropriate pa_ge as determined by the BUT in FP14.

4.7.4.2 FADD and FSUB— Entrance to this flow is either at FADD or FSUB. As shown in the diagram, the

operations are identical except for one extra step in floating subtract instructions. This is SUBO at location 522 in
which the high B argument in MSR (subtrahend) is complemented in D (merely to change sign), and put into BR
Flowis then diverted to the add flow at ADDO.

4-38

Ina floatmg-add mstructron, entrance »through FADD is to ADDO at location 520. Here 'the low B argument in

R(13) is sent to B and the sign of the B argument-(BR15) is tested for the branch out of ADD1.For FADD
1nstruct10ns BRis loaded with the hrgh B argument at FP15 and for FSUB instructions it is reloaded at SUBO.
- In ADDI, the 2’s complement of the low-B argument is taken DAD=10 inserts the carry into the ALU, and the
carry-out is saved. This whole operation is done in case the B argument is negative. In that case, the branch is to
| ADD4 where the 2’s complement of the low B argument is storedin R(13)

At ADDS, the high B argument (R(l 1)is put into B and complementedin ADD6 with the carry-out of the previous

- 2’s complement inserted to yield a 32-bit 2’s complement. In ADD7, this complemented hrgh B argument is stored
|

| backin R(11) and flow proceeds to ADD2

If BR15 was (0) in ADDO the B argument would have been posrtrve flow would have gone drrectly to ADD2 and
-

complementing of the high B argument would not have occurred.

At ADD?2, the low A argument (R( 12)) is put in B and BR, and the high A argument sign is tested (DR15). The DR

was loaded with the high A argument at FP2. The low A argument is then put in HSR in ADD3, the 2°s complement
is also taken (in case the argument is negatrve) and put into BR, and BUT(COUNT"O) is done for NPRs.

If the A argument is posrtrve the flow proceeds to ADD8 where the hrgh A argument uncomplemented is put into

the BR. If it is negative, ADD?9 is entered instead where the complemented low A argument is stored in HSR and the

high A argument (R(10)) is put into B. The 2’s complement is then taken in ADD10 and put into BR. Note that
either flow (DR1 5(0) or DRlS(l)) resultsin the hrgh A argument berng storedin BR

" -Now the exponents are consrdered (they were separated backin the fetchmg of the arguments) andin ADDll the

high A argument is put. mto the DR while the A exponent in R(l4)is put into B. At the same time, the EPS(Z) bitis
cleared for later use,

In ADD12 the A exponent in B is subtracted from the B exponent in R(lS) and that drfference (whlchis used as a
shift count for lining up binary points)is put into B and BR. Note that between P2 and P3, D15, which indicates the
- relatronshrp of argument exponents is tested for the branch out of ADD13

If in ADD12 D15 was set, it 1nd1cated that the A exponent (R(l4)) was greater than the B exponent (R(lS)) and‘
~in that case, positions of all arguments and exponents must be swapped. This is necessary later on when bmary
pomts are lined up SO that the proper argument is in position to be shifted.

| ADD13 performs a 2’s complementin case A>B and. the flow proceeds to erther FADDA exrt 1f B=A, or to ADD14

where the general swapping operation begins. Note that if the exponents are equal (D—O) the settrng of EPS(Z)in
this word (ADDl 3) 1nd1cates that fact.

"If Aand B arguments must change places, ADD14 moves the A exponent in D (actual count)»to BR, ADDI15 moves

it from BR to the count, and moves the low A (in HSR) to D. In ADD16, the low B argument is put into the BR,

| andin ADD39 the low Ais put inR(13) from D
NOTE

At thls pomt low A is where low B was.

At ADD17 low: Bin BRis put in HSR SO that low B is now where low A used to be and at the same trme the hrgh A

in DRis sent to D

In ADDI18, the high B in R(ll) is put in BR in ADD19 it is put in the DR whrle the hrgh Ain Dis put in R(ll) |
Now both arguments»are swapped and in ADD20 and ADD?21 the A exponent is put where the B exponent was. This

439

completes the swap of arguments and exponents. Only the A exponent is movedin this operatron The B exponent 1s

lost since therr difference was determmedin ADDl 2 and A has been determined to be the larger.

NOTE
If B was
>A R(15) would still contam the larger exponent

(B).
Flow then proceeds through the exit FADDA to the next sheet of this flow

The floatmg add and floatrng subtract flows continue on sheet 3 of the FIS flows, then on through FADDA to
ADD?22 at location 740. Here the low B argument is shifted left to provide an additional bit position on the low end
for rounding. This is done by adding R(13) to itself, saving the carry-out, and putting the resultin B and BR. Thrs '
makes two extra rounding positions, as the first was gainedin fetchmg the arguments
NOTE

- Although arguments are identifiedin the dlscussron from this
- point on, it must be remembered that due to swapping, whatis

called the low B here may be the low A. What is termed the
-

low B should be thought of as the larger of the two argumentsv
|

to avoid confusron

Since a Shlft is performed, the counter is ehecked for a count greater than 30g. This condrtron would exceed the
range of the machine. The mantissa consists of 24 bits including the hidden 1 (24,,=303). If the difference in
exponents exceeds this, the hardware will not perform any shifting but will take the argument wrth the -larger
exponent as the answer before rounding and normalization.

The BUT (COUNT>30) FUBI EUB3 is made at P2 of ADD22 and at P3 of that word the count is decremented
ADD23 performs the same shift of the high B argument by adding R(l 1) to 1tself W1th the carry-in inserted from the
previous word, yielding a resultant 32-bit left shift of Wthh only 24 bits are looked at. The hrgh blts are consrdered
sign extensron

Coming out of ADD?22, if the count was sensed greater than 308 , the pathto ADD29is takenthereby bypassing the
binary point alignment procedure and putting the low answer in HSR and the high answer in BR. BUT COUNT=0

accommodates NPR servicing and the flow proceeds to ADD33. Note that this enters the flow after the stepsthat
would have been taken if the exponents had been in range. If thrs were the case, flow would be to ADD24 from
ADD23.
'
a

At that point in the flow, the DR (high mantissa) is concatenated with HSR (low mantissa). When these bits are
shifted right, the sign of the DR must be duplreated The statement at P1 (ADD24) performs that function by
placing DR15 (sign) into BROO. As shifting continues, the state of DRIS is duplicated. The BUT in this word is
testing for the equality of exponents. EPS(Z) and ZB have previously been set to indicate this equality. If the
exponents are equal, EPS(Z) will be set, no shifting due to exponent difference is requrred and the flow is to
ADD?28 through ADD25 where the count is decremented again. Note that no shifting due to exponent differenceis
required, but that binary points still require lining up due to the two extra rounding bits already added to the low ~
end of the B argument. Thus, the A argument (that picked up one extra bit in fetching) must pick up an additional
extra bit to be aligned with the B argument Thisis done in ADD28 where the high A argument in DR and the low A
argument in HSR areshifted left one plaee HSROO picks upa 0 from MSRIS This word then carries off to ADD3O
to begin the add operat1on |

4-40

If as a result of the BUT in ADD24 the exponents were determined not to be equal the 1ndrcatronis that sh1ft1ngis

required to align the binary points. In this event, the flow would proceed through a decrement in ADD25 to
ADD26. The count, however, had also been decrementedin ADD22 so that the original differencein exponents was
reduced by one. Thus, if the BUT(COUNT=0) in ADD25 is true, an original difference of one in exponents existed
and no alignmentis required; i.e., an additional bit position was prcked up on the B argument in ADD22 and, by not

shifting the A argument right one place to exhaust that difference, an extra place on the A argument has effectively
been gained. In this event, the flow out of ADD26 will not be to ADD27 but rather to ADD30.

In the event that the result of the BUT(COUNT=0) in ADD25 was # 0 (note: this BUS is after the decrement in

ADD?22 but before the decrement in ADD25), the decrement in ADD25 will cause the BUT in ADD26 to indicate
that an original difference of two existed and just one pass is required through ADD27, thereby shrftmg the A

argument one additional position to account for the extra bit on the low end.

In ADD2-7, the number of passes Will_“aIWays' be one less than the original count for the reasons just stated, and in the
example just given, the decrement in ADD26 will carry the flow out of ADD27 to ADD30.

An add of the low A and low B arguments is performed in ADD30 and the results (low answer) are storedin BR.

The low answer is then sent to HSRin ADD31 and the hrgh B argument (R(11))is put in B.
An add of the hjgh A and high B arguments is performed in ADD32 and the results (high answer) are stored in BR.
The high answer is sent to DR in ADD33 and the low answer in HSR is put in B. The sign of the answer (BRIS) is

put in EPS(N)

A 2’s complement of the low aqnswer_in B is taken at ADD34 and stored
in the BR. This is done in case the answer is
negative. At the same time, BUT(BR15) is made to test the sign in the high answer for the branch out of ADD35.

In ADD35, P2, the high answer in DR is ORed with the low answer in B through the ALU to D. This is done to
accommodate the BUT(D—O) test in the first word in the normalrze flow At P3 the hrgh answer in DR is sent
through the DMUX to B.

At this point, the effects of the sign of the answer are felt. If the answer is positive, it is shifted right in ADD38 to

get rid of the second extra bit on the low end and the flow exits to NORMALIZE If the answer is negative, the 2’s |
complement of the high answer is taken in ADD36, and in ADD37, the answer is put in DR and B for the ORing

operation again in ADD35. This time the BUT (BRI 5) W111 find a posrtrve answer (because of the complementatron)

and exit through ADD38 to NORMALIZE

There are exits in this flow for bus requests These tests, made by hardware assertion of GPC=7, are not made on the
BUT MUX. This code will assert bit 5 in the UPP and cause the ROM to branch to BRQifa bus request has been
clocked in. The bus data cycle master sync would have clocked the BR request flags in the processor. The

BUT(COUNT=0) in the option also clocks that flag and throughout these flows that BUT appears perrodrcally |

whenever the length of t1me for an operatlon has taken a considerable perrod

If a bus request had been flagged at ADD25 when the flow was to proceed to ADD28 for example, the GPC 7
would have been asserted in ADD25, causrng bit 5 of the UPP to be asserted thereby changing the next address from

717 (ADD30) to 757 (BRQI)

If the flow was from ADD25 through ADD26 to ADD27, rather than go to 713 (ADD27) the flow would proceed
to 753 (BRQO). Also in ADD27, this codeis asserted for each pass through the loop 50 that anytlme a bus request is
present, the flow will immediately branch to BRQO.

When a bus request is sensed by a GPC=7 code, the instructionis aborted, the stack pointer is backed up to thethh
B argument, and the PC is backed up to the floating instruction. This allows return to a restart of the floatrng
instruction after servrcrng the request.

441

Both BRQO and BRQ1 perform this same operation by generating a constant of 6g (fCON=2) to decrement the
pointer. It exits through BRQ to BRQ4 at location 755 where the constant in B is subtracted from R(DF) the stack

pointer. UPP8 is cleared to swflch ROMs and word BRQS decrements the PC by 2 to point to the floatmg
N

mstructlon

The final exit is to SERVICE C_in the KD11-A flows.

FADD Example o
|

R[3]= 7000
7000/040000

Hi B

17002/000000
7004/040000

LoB
HiA

7006/000000

Lo A
)

SOOO/FADD3

Bop fraction '=?1"/2 | exp =0

exp = 0

Aop fraction = 1/2

A+B=12X2°+12X2°=1X2=1

Since hidden bit is stfll implied in result:

1=2'X 1/2 Therefore the result stored must be:

Arithmetic:

7004/040200 |

Ihans

7006/000000

Lo ans

The following chart lists the contents of the various registers for each flow diagtam step of this example.
Step

FP1

FP2

040000

FP3
FP4

000000

FP5

040000

. 040000\

007002

FPO
'FP12
FP13
FP1
FP2

040000

000400

FP4
FP5

000000
040000

FP7

000200

FP3

"FP6

FP8
FP9

FP12

FP14

|
|
._R [13]=000000
= oooooo EPS(C)=0
R[13]

007004
=

040000\

040000

000400
000000

R [15] =200;EPS(Z)= OZB-0

InserthiddenbitinD
"R[11] =400 ARGA <1
EPS(N)<—-O R [3] = 7004
~ R[10] = 040000
R[3] =7006

R [12] = 000000

=000000, EPS(C) 0
- R[12]
o
,

R[lO] = 100000

100000
|

R [3] = 7002

" R[14]=200;EPS(Z) =0,ZB=0

040000

Registers&Note”s

R[11] = 040000

R[11] = 1,00000'

000000

100000

040000

MSR

FP6
FP7

~HSR

000000

100000
100000
000200

'FP8

040000

442

Insert hidden bit
RT10] = 000400 ARGA <R
o

S’

Consider hidden bit:

Step

ADDO

EPS(C)=0

000000
000200

ADD12

000000
000000

000000

000400

000000

“count=0

000000

ADD25
ADD28

000000

ADD30

001000

EPS(C)=0
- 000000

002000

000000

ADD34

002000

ADD38
000000

NOM1

000000

001000

ADD32

000201

000000

EPS(N)=0

002000

'EP5(C)=0

001000

000000

R[15] =201

NOM4
000400
000001

- Go to normalize

DR9(1) so do not normalize

NOM?7

NOMS

DR=HI A
FRACT
HSR=10 A

R[11] = 001000
~

ADD24

EPS(Z)=1
EPS(C)=0

000000

001000

ADD23

NOMO

EPS(Z) < 0

000400

000000
000000

ADD13

ADD35

EPS(C)=0

000000

000400

ADDI11

ADD33

| _RegiSters & Notes

000000

ADDS

ADD31

MSR

- 000000
000000

- ADD3

ADD22

"HSR

000000

ADD1.

ADD?2

000000

- Round up EPS(C)=0

000001

NOM9

000400

NOM10

000400

NOM11

000400

NOM12
NOM13

000200

000201

1000201

000201

EXIO

/000000

040200

EXI1

000244

- 000000

~ EPS(C)«0, EPS(Z)=1
R [14] =244

EXI2
000000

DATO, Lo Ans to 7006

EXI9

007004

R[3] =7004

EXI10

040200

DATO, Lo Ans to 7006

EXI8

040200

EXI11

EPS(N) =0, EPS(Z) =0, EPS(V,C) =0

ASH15

PS(N:C)« EPS( N:C) :

ASH21

NO-OP

SERVICE C
- *Here we agree with original calculation from sheet 1

7004040200

7006/000000.

443

4.7.4.3 FMUL — The floating multiply flow is shown on sheet 4 of the FIS flows and in Figure 4-12. Entry to this

flow is through FMUL to FMLO at location 524. In this word, the contents of the D Register is put into the BR.
This is the result of the XOR of B and MSR performed on sheet 1 at FP15 pnor to entry and represents the sign of
|

the answer.

r"'o_'
‘T

DMUX
SHIFT RIGHT

BR
g

HIGH PRODUCT

MULTIPLICAND |

ORM1]

R[13]

HIGH

LOW

[

__HSR

" LOW PRODUCT

—

HIGH MULTIPLIER

ROMUX

MSR
LOW MULTIPLIER

[1-1628

Figure 4-12 V,FMUL Flow, Block Diag:am |

In FMLI1, the B exponent (R(14)) is put in B and the sign of the answer (BR15)

is put in EPS(N). The zeroness of

the A and B exponents is tested with BUT(ZB+EPS(Z)). These bits were set while fetchmg the exponents in FP8

Word FML2 adds the A‘ and B exponents and then proceeds to either FML3 or FML4. Note that adding tWo

- exponents, each of which is expressedin excess 200 notation, yields a result thatis in excess 400 notation. This will
'

be correctedin subsequent steps

If the result of the BUTin FMLI indicated that one or both exponents (arguments) was equal to 0, the flowis taken
to FML3 where the answer is zeroed before exiting to ZERO A on the NORMALIZE flow. In this case, the fact that |
the addition of exponents produced excess 400 notation has no meaning andis ignored.

If neither argument was determined in FML1 to be equal to 0, the flow
is to FML4 where the exponent is corrected

to excess 200 notation by forming a constant of 200. That value is then subtracted in FML5. Note that the
subtraction includes a “MINUS 1”°. Subtracting this additional 1 is done to accommodate the entry to normalize.

The multiply loop couht is formed in FML6 as generated by fCON=3 (305 or 24, ) so that once the multiply loop

is entered at FMUL11, the hardware will keep track of the number of passes through the loop until all 24 bits of
significant mantissa have been monitored.
‘
|

444

- FML7 loads the count and puts the low multiplier (R(12)) into BR. This proceeds to FML8 where the low multiplier
is transferred from BR to MSR to make room for the high multiplier (R(10)) from which it is put in HSR in FMLD9,
where the BRis also cleared. At this point, the full multiplieris in MSR concatenated with HSR.

At FMLI10, the zeroed condition of BRis used to clear the DR, and the low multiplicand (R(13))is put into B. This
sets up the full 64-bit concatenation with the BR and DR cleared ready to receive the product, and with the
multiplier in HSR and MSR. The flow is then to the entry of the multiply loop at FML11.
In this word, a shift right through the DMUX is done with D(C) getting ALU15. The D Register gets the low partial
product (BR) and the count is decremented. Note that the state of MSRO1 is tested in this word rather than MSROO.
This is because MSROOis actually the extra bit picked up by shifting during the fetching of the arguments on sheet 1
of these flows andis consequently not significant at this time.

On each pass through the multrply loop, this bit pos1tron always contains the current least significant bit of the
multiplier. It is this bit that is used to determine whether to add and then shift or to just shift without adding.
Whenever MSRO1 is a (1), the multiplicand must be added to the partial product before shifting. If it is (0), a simple
shift of the partial product and multiplieris executed.

~ In this multiply loop, the flowis from FML12 to FML14 through FML17 and back to FML11 whenever MSRO1 is a

(1); or whenever MSRO1 is a (0), the route is FML12 to FML13 and then back to FML11. In each pass the count is
tested and when COUNT=0, the loopis exited and flowis to FML18 to store the products for normalization.

There are two bus request escapes. These are BRQ2 (653) and BRQ3 (657). BRQ2 is used for breakouts during any
pass through the loop except the last. On the last time through, however, coming out of FML13, the base address
613 can be modified from two sources at the same time. The fact that COUNT=0 modifies 613 to 617 (FML18) and
a bus request can modify that address to 657 or BRQ3. Once entered the BRQ routine is identical to that descnbed
for FADD and FSUB.

| Dunng the multrply loop, data is swapped from reglster to regrster to accommodate the instantaneous needs of the.
operation. The low multiplicand is always being added to the partial product held in the DR and the BR. As the
operation progresses, the low multiplicand is added to the DR, the carry is saved, that sum is loaded into the D
Register, and the BR is loaded into the DR. The high part is brought up where it can be operated on, the two halves
- are added and then everythingis moved around again.

In FML14 and FML15, the low multiplicand (B<R(13)) is added to the partral product (D<DR PLUS
|
B:EPS(C)<COUT 15). The contents of BR are saved in the DR to make room for the low partial productin D.

At FML16, the high multiplicand (R(12)) is put into the B Register, and at FML17, the rest of the double-precision

add is done with the previous carry-out (EPS(C)) being used as the carry-in. This is sent to D. The low partial

product in BR is put back in DR and the high partial product in D is put back in BR. The flow then goes back to

FML11 to look at the next LSB of the multiplier and continues for a count of 308 , unless interrupted by a bus

request

When the count is exhausted, the flow proceeds to FML18 where at P2 the low product in DRis put into the D

to BR.

- In FML19, the low product in BR is sent to the HSR while the B and BR Reglsters are cleared. This resultsin the
final assembly of the product in the DR and HSR Registers concatenated where it needs to be for the normalization |
process.

4.7.4.4 FDIV— The floating divide flow is shown on sheet 5 of the FIS flows and in Figure 4-13. Entrance is

through FDIV to FDVO at location 526. Asin multiply, this word takes the XOR of the high A and B arguments put
in D at FP15 and loads that result (sign of the answer) into BR.
445

//A
'

ALU
B

B
)

DMUX
|

BR
HIGH DIVIDEND

romwx

DIVISOR

CRM]

R [13]

HIGH

LOW

‘D‘R‘ .

LOW DIVIDEND

HSR
fe—

HIGH QUOTIENT

MSR
|e—]

LOW QUOTIENT

|e—o

H-1629

Figure 4-13

FDIV Flow Block Diagram

‘Word FDV1 sends the B exponent R(15) to B, and the sign of the mantissa (BR15) is put in EPS(N). The BUT in
this word differs from the similar test in FMUL-in that this is the ANDing of ZB and EPS(Z) whereas in multiply it

was an OR function. This test of the A and B exponents determines whether either the divisor or the dividend, or
neither is equal to O. If the divisor is O, an underflow is indicated; and if the dividend is O, a 0 answer will be

generated without going through the divide loop.

In FDV2, the B exponent (divisor) put in the B Register m FDV1 is subtracted from the A exponent (dividend) in

R(14) and the difference is put
in B. This will be the “initial” exponent, so called because it has not as yet been

modified by normalization. This subtraction removes the excess 2005 factor in the notation and will be corrected
later.

If, at FDV1, the ZB flop was set, the indication is that the divisor (B argument) is 0 and flow is to FDV3 where the
trap vector for the floating point (244) is formed by fCON=1 and the EPS(C) bit is set to indicate division by 0. The
vector is stored in FDV4 and exit is to the underflow routine on sheet 6 of these flows.

If, at FDV1, the mdleatlon was that the dividend (A argument) was 0 (ZB= 0 and EPS(Z)=1), flowis to
a O answer is generated by zeroing D, BR, B, and R(15), and then exiting to ZERO A on sheet 6.

FDV5 where

If, at FDV1, both ZB a_nd EPS(Z) were found to be clear, this would indicate that neither the dividend nor the

divisor were 0 and flow would proceed to FDV6. Here the exponent is returned to excess 2005 notation by adding

2005 to the difference in exponents. GPC=6 generates the constant 2005.

Word FDV7 stores the corrected exponent and FDV8 forms the constant 325 or 26, (the number of times the
d1v1de loop must be executed).
At FDV9, the count is loaded from the BR, and BR gets the low dividend (R(12)) The low dividendis then put in
the DR at FDV10 and the BRis cleared. The fact that BRis all Osis then usedin FDV11 to clear the HSR and MSR

“after which the high dividend (R(10)) is put into BR. FDV23 then puts the low divisor (R(13)) into B. The datais
~ now set up for the first division step in FDV24.

446

The first dmsron step is always a subtract operation, and in FDV24 the low half of a double-premsron subtract of
the low arguments is performed. The high dividend (BR) goes to DR, the low divisor (B) is subtracted from the low

dividend (DR), the carry-out is savedin EPS(C), and the resultis put in BR.

In FDV21, the high divisor (R(11)) is put in B while the count is decremented before proceedmg to FDV22. Here
the result of the low subtraction (BR) is put in DR. At the same time, the high divisor (B) is subtracted from the
high-dividend (DR), and the carry-in is inserted from the previous carry-out. At the same time, the carry-out 15 from
this result is stored in EPS(C) which will now become the MSB of the quotient. Later on this bit will shift into the
MSR Register as part of the quotient. At P3 of FDV22, the result of this subtraction (high result) is put into BR.
The BUT(COUNT=0)is done both for NPRs and to see if thisis the last time through the loop.

The flow here is to FDV16 where everythrng is shifted left. Note that these regrsters are concatenated and that |
- EPS(C) goes into MSROO. That is the carry-out from the subtraction that indicates whether or not the division step
was successful. If it is, a carry-out is seen and a (1) is shifted into the answer. If the step is not successful no
-

carry-out occurs and a 0 is shifted into the answer.

If this is not the last pass through the loop (COUNT=0), flowis to FDV12 where the low divisor (R(13))is put in B
=7).
and the BUT for BRQis made (GPC

At FDV13, the dmsron step for the low d1v1dend is done The BR is put into DR then DR and B are processed
according to the function of MSROO (see table at bottom of sheet). MSROO, remember, is the result of the last
subtraction or addition andis an indication of whether lelSlOIl was successful or not.

On each pass through the divide loop, the hardware determines whether the last subtraction was successful. If it was,
a subtraction at FDV13 and FDV22 will occur on the next pass through the loop. If it was not, an addition at

FDV13 and FDV15 occurs on the next pass. If a carry-out occurs, a subtractronis tried on the next pass andalis

1nsertedin the answer. If no carry-out occurred, a 0 is mserted

Each pass decrements the count and the loop continues until the count is exhausted. Note that a BUT for COUNT—O
is doneiin either FDV22 or FDV15 since in the last pass the flow could be through erther word

When COUNT-—O the flow is to FDV17 to set up the quotrents for normalrzatron In FDV17 and FDV18 the hrgh
quotient in HSR is put in DR. In FDV19 and FDV20, the low quotient in MSRis put in HSR. The last operation
before exit to NORMALIZE is to zero the B and BR Registers so that they may be usedin the roundmg routine on
sheet 6 of these flows.

The one BRQ breakout facrhty in this flow is tested at FDV12 where, if a bus request has been clockedin,the UPP
Register addressis modified from 731 to 771 (BRQ6)

4.74.5 Normahze Round and Store — Sheet 6 of the FIS flows contams the routlnes for normalization, rounding,
and storing; the flows for FADD, FSUB, FMUL, and FDIV all exit to this flow before storrngtheir answers. Their
points of entry drffer however, dependrng upon the 1nstruct10n being performed..

Entrance to ZERO Ais from FMUL or FDIV (the only 1nstruct10ns that detect whether one or the other argument
equals O so that a0 answer may be stored)

Upon entenng at ZERO A, the 0 answer has already been generated and flowis to NOM3 at locatlon 576. Here the

BR, already cleared, is used to O the HSR and DR. BR15is used to O the sign (EPS(N)). The FC1BUSis set to enable

a DATO. Note that it is enabled one word early because it is double buffered by the FIS U Register and CPU U
Regrster

f The statement BA<—R(DF)‘DAD=6 is done to check overflow. R(DF)is the stack pointer and if it should happen to

be register 6, as specified by the destination field of the IR, a decrement into a protected area could occur later on
447

\\\.“-—-/

when answers are stored. The BA is loaded here so that the CLOCK BA signal will be generated which, with DAD—?6‘
will set the Check Overflow flag and check for overflow if R(DF) is reglster 6. Flow thenis to the STORE routrne
described later at the end of this discussion.

~ Entry at NORMALIZE is from the FADD or FSUB flow and enters word NOMO at location 727. In thi.s ?word, the |
BR and B Registers are zeroed for use later in rounding. BUT(D=0) tests fora O answer as set up previously in

ADD?35. If D=0, it indicates that a O answer should be generated and the flow s through NOM1 and NOM2 where a
0 answer is generated

Entry at NORMALIZE A is from the FMUL or FDIV flows and enters word NOMI1 at location 554 This entry
bypasses the zerorng action in NOMO because this has already been donein FMUL or FDIV

In NOMI the exponent (R(IS)) is adjusted by incrementation in D and restored to R(15). In thatsame Word the
BUT(NORMALIZED) test is made with GPC=1 also asserted. This combination looks at DR09 for the branch out of
NOM4. DRO9 is the MSB of the mantissa and, if it is set, it indicates that the mantissa is normalized. If it is O, the

RNy

~ mantissa is not normalized.
NOTE

Most BUTSin this option look for a condition to be asserted to
OR a 1 into the ROM address. In this case, assertion does not
-modify (705) whereas non-assertion does (707).

Flow is then directly to NOM4 and not to NOM2 because the BUT(D=0)
is not felt by the NORMALIZE A entry.
NOM4 sets up the R6 overflow-check as described for NOM3 and takes the appropriate normalization branch. -

If the BUT in NOMI1 indicated that the mantissa was not normalized, NOMS is next where the exponent is
decremented because the mantissa is shifted left. GPC=5 allows HSR15 to be concatenated with DROO. As HSR is*

shifted left one place, a O is brought in. Note that the BUT(NORMALIZED) does not assert GPC=1 in this word.
This causes the hardware
to check normalization before the shift by looking at DROS8, If DROS8 is set at this time,

DRO9 will be set after the shift and, as a result, the flow will be to NOM7 after the decremented exponent is stored
in NOM6. Of course it could take several passes to normalize the exponent (up to 31g places), so the

BUT(COUNT:O) in NOM6 serves to clock NPRs. Note also that the exponent is decremented for each pass.

At NOM?7, the answer is shifted right one place to put the extra bit on the low end in position for rounding. NOMS
answer is returned to HSR.

At NOM10, the high answer is rounded by adding O to the DR, and bringing in the previous carry-out (EPS(C)) as |
the carry-in. In NOM11, the result is sent via the BR to DR. By adding O to the high part and bringingin the carry,
the effect of adding the 1 may ripple up from the low answer to the high answer via the carry. At thrs pomt the
rounded high answer is in the DR and the rounded low answer is in the HSR

Now that rounding has been done, the extra bit on the low end is no longer needed so in NOM12 it is dropped by

shifting everything right one place. The BR is also cleared. At the same time, normalization is checked by looking at

DRO9 (at this point DRO8 is the MSB). This is to be sure that it is still normalized after rounding. If, as a result of
rounding, the added 1 had rippled all the way across, the answer would have become unnormalized. To become
renormalized, an additional shift is required along with an increment of the exponent, NOM13 sends the exponent

(R(13)) to the D, BR, and B Registersin case: ad]ustmentis not requ1red

Commg out of NOM13 the effects of the BUT in NOMI12 are felt and, if the answer was not still nOrmalized :

(DR09(1)), NOM14 is entered to effect renormalization and to 1ncrement the exponent. The adjusted exponent is

then storedin R(15), B and BR.

|
——’

rounds the low part of the answer by addmg 1 and the carry-out is saved in EPS(C). In NOM9 the rounded low

If, however, the answer was normalized (DR09(0)), the ROM address is modified to 542 and the flow exits to EXIO.

'NOTE

At this point, the answer has been rounded and normalized,
the exponent has been adjusted to the correct value, and the
- hardware is ready to assemble the answer and store it.

EXIO assembles the high answer by putting the sign bit (EPS(N))in BR15, the exponent (BR(O7 OO))1n BR(14 07)
and the high mantissa minus the hidden bit (DR(06: OO))in BR(06 00).

Word EXIl4 sets up the D Reg1ster for the BUT to be made in EXI1 for underflow overflow or store ThlSis done

by zeroing the upper 8 bits of the D Register with SBC=00. The EPS(Z) bit is loaded with whether or not the
exponent is equal to O as set up at P2 of NOM13. This establishes one of the conditions for underflow. The low 8

bits of the D Register are loaded with the high byte of the register that held the exponent (R(lS)) (prevlously loaded
into the B Register at P3 of NOM13 or NOM14). In add1tlon EPS(C)1s zeroed
|
At EXII1, the trap vector 244 is formed (fCON=2) in case underflow or overflow are 1ndlcated by the BUTin that,

word, andin EXI2 that vector is stored along with settmg the DAT() control bit (FClBUS)

If, at EXI1, the D Reg1ster contains any data, overflow exists 1nd1cat1ng that what was the hlgh byte of the exponent

had some carryover from the low byte of the exponent. In this event, flow will be to EX112 Underflowis 1ndlcated

if either EPS(Z) is set, indicating a 0 exponent; or B15 is set, 1nd1cat1ng that decrementation of the exponent

produced a negative number. In this case, the flow will be to EXI3. If neither underflow or overflow are indicated,
- the answer is determlned to be legal and flowis to EXI7 for a store operat1on

If overflow or underflow are indicated, the FCI1BIT set in

EXI2 will have no effect since on the next bus cycle the bas1c
- ROMis used and the FIS U Registeris cleared.

If overflow is indicated, EXI12 and EXI14 load the EPS(N) bit via BR with a 0 (top bit of 2445 in D is a 0). If
underflow is indicated, EXI4 generates the stack pointer adJustment constant of 6, zeros the EPS(Z) b1t and sets the
|
-

EPS(V) bit. The cond1t1on codes for overflow and underflow are as follows

Condi_tion Codes for Overflow and Underflow

UNFL

OVFL

EPS(Z)

-0

~ EPS(C)

EPS(V)

FDIV By Zero
0
1

By referring to the condition codes in the table above, it can be seen that all codes are properly set by these word
combinations, including the divide by 0 combination in which the EPS(C) bit was set prior to entry at UNFL A. In
this same path then, EXI15 moves EPS to the Processor Status Word and clears the extension ROM enable bit UPP8

while EXI16 ad]usts the stack po1nter and exits to KDl l-A Trap D flow
If the STORE path is taken flowis to EXI7 where the low answer in HSRis sent to D, a DATOis 1mt1ated and the

clockis shut off to wait for the memory response.

449

AtEXIl 8#_, the 'hjgh'answer astsernbled 1n BR in word EXIO 1s brought into the B "Register, and at EXI19 the stack

pointer is decremented by 2 and put into the BA. The DAD=6 checks for a register 6 stack overflow, the modified
|
stack pointer is put back in R(DF), and the FC1BUS is set.

At EXI10, the assembled high answer (sign, exponent, and high rnantissa) in'B is stored in D, the DATO is initiated,

~and the clock is turned off. Then at EXI11 the local condition codes are set before exiting to MOVE EPS.
4. 8

LOGIC DESCRIPTIONS

The KE11-E logic diagrams are shown in drawmg D-CS M7238 -0- 1 sheets 2 through 9 The sheets are de51gnated
|

| KE-2 through KE9 as follows:

BR(15:00).DR(I5:oO)A', )

" KB2
KE-3

'RDMUX(15:00)

KE4

EUBC MUX AND CONTROL

KE-5

CLOCKING AND CONTROL

KE-6
KE-7

EPS AND COUNTER
~
KE ROM AND U WORD REGISTER

KE8

KE9

KD ROM EXPANSION=
KD ROM EXPANSION AND CONNECTORS

KE- 1() 17

- EIS ROM LISTING

The KEll -F logic dlagrams are shown in drawmg D-CS M7239 O 1 sheets 2 through 4.The drawmgs are de31gnated
KF-2
KF-3
KF4
|

KF-S 12

KF-2 through KF4, as follows:

HSR&MSR,’
ROM

FRDMUX(15:00)
& CONTROL
FIS ROM LISTING

-'In these paragraphs the logrc is describedin. thls sequence for convemence only The sequence bears no relatronshrp »

‘to their logical arrangement. These descriptions, together with the Glossary in Appendix A, prowde an adequate
description of the loglc dragrams assomated with the KEll -B and F Optlons
4.8.1

Basic CPU Trmlng

As the KE11-E and KE11 F operate on the bas1c tnnlng of the KDI I‘A a brief descr1ptlon of this t1m1ng is given at
thrs point.

There are three basic timing cycle lengths used in the KD11-A. For a descrrptlon of thelr generatlon refer to the
-

KDI 1 -A Mam tenance Manual EK KDl 1A-MM-001.

| The 'three c:ycl.e'; lengths are- designated.‘ CLl, CL2-, ..and‘CL3 . Cycles CL1 and CL2 have one clocking pulse which
occurs at the end of the cycle. Cycle CL3 has two pulses associated with it. The time relationship of the cycle
lengths and their respective pulses are shown in Flgure 4-14. All clockmg actlon takes place on the trarhng edge of
the clock pulse.

140ns

)

cLi

——fl ~40ns [e—

—_—

U
200ns

- — ®40ns

cL2

je—

300ns

—

- 200ns

— ®40ns

‘—4M60ns——fl 240ns je—

|P3.5
]

f1-1623

Figure 4-14 Basic KD11-A Timing

4. 8 2

BR and DR Regxsters (Dwg KE- 2)

The BR Reglster is a 16-b1t holding register which receives data from the CPU via DMUX(15: 00) H. The BRis used

" to hold data durlng the _EIS. and FIS instructions. This register is loaded on the tralhng edge of Pl or P3 pulses.

The DR Reglster is a 16 bit left-rlght shift reglster which receives data from the BR. The DRis also used as a holding

register. During the multiply instruction, the low productis shlfted into the DR via DR15 as the multiplieris shifted
out at DR0O. During a divide, the quotient is shifted into the DR via DROO wh11e the low d1V1dendis shifted out at
| DRI 5. Output s1gnals are hstedinTable 4-4
Table 4-4
KE2 Output Slgnals

Mnemomc

BR(IS 00) H

Descnptlon o

- Output from the BR Reglster fed to DR(IS OO) and through the EIS optlon Also to pins
for dlstrlbutlon to EIS and FIS options.

- DR(15:00) H

]

'Output from the DR Reglster Used in ASHC MUL and DIV operationsin the EIS andin
all FIS 1nstructlons

On the left-hand side of this sheet are shown the three heX flip-flop registers, 74174s that comprise the BR Registe-r.

~ Inputs
to this register are. DMUX(15:00) coming from the basic machine. All'input data from the KD11-A comes
into this register from Wthh 1t is distributed to the rest of the EIS and FIS optlons It functlons as a holding reglster
and buffer

The outputs of the BR Reglster feed four 74194s that comprise the DR Reglster These are left- nght shlft reglsters
having the ability to also be loaded in parallel. The DR is used extensively in ASHC, MUL, and DIV to shift and
store data Likewise, it is usedin FIS instructions to temporarlly store and shift data.

. The shiftmput to b1t 00 of the DR Reglster has several sources, some from the EIS and others from the FIS; one is
enabled during an ASHC 1nstruct10n

4-51

The bit 00 1nput to the DR Reglster is important only if a left shrft operatlon is being performed. In a rrght shift,
|

this lineis insignificant.

In ASHC, while 'shrftrng left, Os must be shifted into the LSB. The DR holds the lower portion of the operand being

shifted, and as the data is being shifted left, the ASHC L on the gate at E48 keeps a constant O asserted at the shift
input so that each succeeding shift brrngsin another 0.

Another source for this shift input is at gate E42. The jumper W1 is present if just the EIS is installed and is removed

if the FIS is installed as well. When inserted, it disables the upper input to the gate. When removed, a floating divide
instruction in combination with GPC=5 L will cause a O to be shifted into the DR on a left shift operation.

This action can be referred to the flow diagrams in sheet 5 of the FIS flows at word FDV16. Here the high quotient
is being assembled in the HSR as the concatenated low dividend is being shifted left in the DR. Everything is being
shifted left after the add or subtract. A O is brought into the O shift-in of the DR Register. If GPC=5 is not true, Os
will be enabled through. If GPC=5 is true, HSR15 is enabled to the shift input of bit 0. Since the use of HSR15 as a
shift input is not dependent upon any particular instruction, but ratheris supphed by the GPC code, it can be used
at anytime that particular combinationis set in the ROM word.

The DR Reglster is clocked by E(P1+P2) H, generated on drawing KE-5 at location D 6. There is no srgnal in the
basic machine called P1+P2, these two signals are ORed here for this function.

The BR Regrster is clocked by CLK BR H, generated on KE 5 at locatron C 6 Itis a function of P1 or P3 and CLK |
BR(1)H generated on KE-7.

DR Regrster bit 15 shrft 1nput is used for sh1ft1ng the register right. Normally BROO is enabled into DR15. Thrsis
when the BR and DR are concatenated with the BR holding the higher bits. In this case, everythingmay be shifted
right with BROO going into DR15. During multiply instructions, however, ALUOO is used as the shift-in wrth ALUOO0
providing the partial answer being shifted into the DR.

There are two select lines on the DR Register, KEV—7 SDRO and KE-7 SDR1. The truth table for these two signals is-

given on the right-hand edge of sheet KE-2. If both select signals are low, nothing will occur when the register is

clocked (No-Op). Note that the clock pulse is always present on any P1 or P2. A binary 1 combination produces a
shift right, a binary 2 combination produces a shift left, and a brnary 3 permits parallel loading of the reglster These
two bits are generatedin the EIS ROM

Both the DR and BR Regrster outputs are brought out to pins for use elsewhere in the options and for testing
purposes.

The BR can be used for buffering the loadrng into erther the count or DRin the EIS, or into erther the HSR or MSR
in the FIS optron

483

RDMUX (Dwg KE- 3)

The RDMUX is a 16-bit-wide 4:1 multiplexer which selects one of four sets of 16-bit 1nputs to be fed to the CPU via
the 16-bit wire-ORed BUS RD(15:00). Output srgnals are listedin Table 4 S.

" Table 4-5

KE-3 Output Signals

Mnemonic
BUS RD(15:00) L

Descnptlon

Output of the RDMUX ‘Feeds data drrectly back to the processor.

452

This rs the hardware that enables data onto the BUS RD to be sent back to the basic machine. These are 74153 dual
4:1 multiplexers controlled by comblnatrons of SRDMI and SRDMOas generated in the Expansron U Word (see
PO

truth tableon thls sheet)

A brnary 0combrnatron sends the EIS status (EPS(CVZ, and N)) back to the basrc machrne‘This operation is called |
out in the flows as MOVE EPS Note thatin this mode the upper 12 b1ts of the multrplexer 1nputs are grounded.
A brnary 1 sends the contents of the DR Regrster straight through and back to the basic machine.

A binary 2 concatenates the BR and DR Reglsters essentlally shrftrng both regrsters left, and erther losrng the high
)

bit of the BR or using it elsewhere.

A brnary 3 sends the BR Regrster straight through and back to the processor

| Note that these enables are set up-one word before the enable for the 74H01 drrvers where possrble Th1sis the AND

of EUPP8 (set if the option is enabled) and STRDM(I) H, another bit set in the ROM word. This allows putting data
out to the RDMUX as quickly as possible without any timing problems. Note that the multrplexer strobe inputs

(STB) are grounded (always enabled).

The outputs of the 74HO01s feed BUS RD(ISOO) of the CPU.

4. 8 4 EUBC Control (Dwg KE-4)

This is the External Microbranch Control that serves as a supplement to the branch control logic.in the basm

machine. The EUB field of the KE11-E ROM is used to select various inputs to the EUBC multiplexer for testingin
order to enable the rmcroprogram to branch to alternate paths of flow. Output signals for this sheet are hsted in
~

Table 4-6.

Table 4-6

'KE-4 Output Signals

M_nernonic |

| Description

'EUBC(S *4)ENB L

| Enables EUBC(4:3) MUX. Used as a partial enable on KE-5 8-D 7402 gate at El9l |

D(15';00)=10 L

1 Inversron of D(15:00)=0 H from the basrc machine. Is used by FIS board as part of3

EUBC(4:1)L

OVFL/UNFL test on that board

o Four bits that modlfy a base address on a mrcrobranch test They are sent to OR gates on
- the M7232 modulein the basrc machine

IR?075xxka

- ~ The Op code that 1ndrcates a floating 1nstruct10n Itis sent to FIS board where it is gated -

and is returned as FIS INSTR L at location D-6. If true allow the branch to the FIS flow.

In the upper left-hand corner of this sheet is the 8251 decoder whrchis enabled by a 07 conditionin the upper two

octal digits of the IR (IR(15:12)). It then decodes IR bits 11:09 to detect whether an EIS (070 through 074) or FIS
(075) instruction is called for. Any other code is not recognized and results in a reserved instruction trap. The
| IR—O75xxxL srgnal goes out to the FIS module decoder logrc
The four decoded instructions are fed to a 7420 NOT ORgate that yrelds EIS INSTR H used to feed the
condltronlng inputs of the input gates on the EUBC multiplexers.

4-53

The EUBC MUX comprises four multiplexers. The 74153 dual 4:1 multiplexer controls EUBC(4:3) while a single
8:1 74151 controls EUBC2. EUBCI1 is controlled by two 74151s operated in tandem. When EUBC1 MUX B is

operating, EUBC1 MUX A is disabled and vice versa. EUBC1 MUX A at E37 provides testing of octal combinations 0
through 7 of the EUBC field and EUBC MUX B at E24 tests combination 10 through 17 (see table at right-hand side

of this sheet, KE-4). This provides 16 possible conditions that may be used to control EUBC1. Note that when the

FIS option is installed, the EUBF consists of 5 bits. When it is not installed, the 74H10 AND gate at location C-3 on

‘the drawing has pin 03 (EUBF4(0)H) held high via R2 (1K). There is an additional 8:1 multiplexer in the FIS to be
described later that provides 8 more branch conditions for EUBC1 control. If EUBF4 from the FIS board is asserted,

the BUBC1 MUX A is drsabled

The outputs of these multrplexers (EUBC(4 I)L) are sent to OR gates on the M7232 module in the basrc machine
- where they are used to modify the base address on a branch.,

| Conditioning of the inputs to these multiplexers is effected by combinations of EUBF(4:0) as set in the Expansion
U Word. These are fed to the multiplexers as selection signals. The operation performed by their combination may
be derived by reference to the truth tables at the bottom of the page and the BUT chart at the rrght of the sheet

4.8.5

Control (Dwg KE-5)

This sheet contains much of the discrete logic used to generate the many control signals used throughout the EIS
logic. It utilizes inputs from the ROM, together with clock pulses generated by the basic machine, to generate these

control signals. Most of the input signals on this drawing are fairly obvious and as such are not described. Some are
enables from the ROM Word others are covered elsewhere as 1nterfacmg signals. Output signals are described in
Table 4-7.

In the center of the sheet is the 825 1 GPC decoder with inputs GPC(2 0). These bits are set in the Expansion U
Word.
The input logic in the upper right-hand corner of this sheet at location C-4 pertains to auxiliary ALU control where
several conditions are monitored to determine what function the CPU ALU will perform. The jumper W2 is normally

inserted unless the FIS option is installed. When removed, it allows the FIS option to control auxiliary ALU control
also.

Table 4-7
KE-5 Output Signals

Mnemonlc |

EXT PCLRTRAPL
CLKEPSNZ)H

- DeScription |

Clears the Trap flagin the Processor whrch was set as a result of EIS or FIS instruction

being sensed durrng a FETCH.

| Clocks the EPS N and Z bits. Made up of the enable bit of the EIS microregister and
Pl or P2 from the CPU.

CLKUPPEH
IR

| ~Is sent back to basic machine to clock UPP bit 8. Gated with an enable bit from the

EIS ROM word and a clock pulse. Once the option has been enabled, br1ng1ng up the

-enable bit allows UPP bit 8 to be clocked clear.

CLK EU(88:57) H
-

This is the clock pulse for the external U Regrster b1ts 88 through 57. (Bits 88 81 are
-

on the FIS board, M7239)

454

Table 4-7 (Cont)
KE-5 Output Signals

Description

- Mnemonic

o External Select ALU. These are the select bits for the ALU when operatedin auxiliary
control mode. Discrete ALU control is provrded by bits in the ROM word where it is
‘known ahead of time what function the ALU should perform. Auxiliary ALU control
“is providedin instances where the operation to be performed by the ALUis dependent
upon incidental conditions of the operation. These signals then are made dependent
‘upon combinational logic that decodes conditions within the operation. The functions
- performed by the ALU for the various states of these signals are given in a table to the
right of the print (KE-5). Note that the four signals are really two srgnals each of

ESALU(3:0)L

which are brought out to two separate p1ns

ECINOOH

:External Carry-ln to the CPU ALU. Used in auxrlrary control mode of the ALU to

L
GPC=2

Output combmatrons of the GPC decoder These are used for specral case applrcatlons
such as operations to be performed only once or twice in a flow. Some. of these srgnals

insert a carry-in to correct the A MINUS B MINUS 1 function dunng subtraction.

go to the FIS board

.INHPS CLKL

Used to inhibit clockmg all brtsin the Processor Status Word except PS(N,7 vV C) This

'EUPPRBH

External rmcroprogram pomter bit 8. Used in the EIS and FIS optrons as an enable

51gnalis also usedin the memory management option (KT11-D).

signal.

'EUPPS L

EUBCSL

| ‘Same as above.

External microbranch code bit 8. Used as data in the basi_c machine to set or clear

- UPP8 when clocked by P CLK UPPS.

| External Carry-Out Mux (Same source to two pms) Selection srgnal to the 4: 1 :

ECOMUXSO L

multiplexer on the output of the CPU ALU, causing ALU bit 15 to be selected into

_the Carry-Out Mux.

Same as EUPP8 B H above. Duplication for loading purposes.

EUPPS AL

ENPRCLLK-

External NPR Clock. Provides the clock for the NPR and Bus Request flags in the

~ basic machine while the EIS and FIS options are active. Made up of the branch

" microtest BUT(COUNT=0) performed periodically in the flow, partrcularly in loops

| where long periods of time could be consumed

CLK EPS(V)H

CLKBRH

| The P1 and P2 from the basrc machrne used to clock the DR and the counter. Also
clocks the MSR and HSR Registers in the FIS board M7239.

A clock for the EPS(V) brt Made up of CLK(V) (1)H from the EIS U Word gated
1 - with P1 or P2 from the CPU.

fClock for the BR Regrster enabled from the EISU Word and Pl or P3 from the CPU
4-535

Table 4-7 (Cont)
KE-5 Output Signals

| Mnemofni,c”’ |

LD COUNT L

Descrlptron |

3 Load Count. When true loads the counter with BR(O7:OO).

CLKEPS(C)H

A clock for the EPS(C) b1t Gated wrth an enable by 2 brt from the EIS U Regrster and

P1 orr P2 from the CPU.

BEUPPS AH

Buffered external mlcroprogram pomter A. Another source for bit 8 of the ROM

- address to enable various pornts in the logic.

| CLK COUNT H

This is essentially the end pulse in each c‘yCle»length, Generated by an enable from the
-

EIS U Register and with the fact that the counter is not equal to 0. When the count

goes to 0, this clock is dlsabled preventing any further countmg durmg testmg of that

condrtlon

4.8.6 EPSand Count (Dwg KE-6)
This drawing contains the external processor status, which records the condition codes of the EIS and FIS
instructions;
and the count, an 8-bit up-down counter used to count the number of shifts for the ASH and ASHC
instructions and to keep track of the number of steps in the MUL and DIV instructions, The count is loaded from
the BR. The logic contains multrplexers for gating 1nformatton into the external status. Output signals are listedin
Table 4-8.

Table 4-8

KE-6 Output Signals

Mnemonic

Description

EPS(N) (1) H

The output'of the exte-rnal 'processm status N bit Used to sto.re the sign of operands

EPS(Z) (1) H
|

- The output of the external processor status Z brt Used to store whether an opcrandis
|

equaltoOornot

EPS(V) (1) H

The ‘output of the external processor status 'V bit. Used to record overflow conditions.

EPS(C) (1) H

~ The output of the'ext-ernal-’processor‘-s’tatu’s C bit. Used to store carry data. -

COUNT(7:0) (1) H
S

‘COUNT=0 H

The outputs of the counter used to keep track of the number of steps executedinthe
|

EIS and FIS mstructrons These srgnals also go to the FIS board (M7239)

'Thrs srgnal is asserted when COUNT(S ())is equal to Zero. |
i

The counter consists of two 74191s at E64 and ES6, operatedin tandem and fedby BR(O7 00) H. It is an up/ down
counter that can be loaded by LD COUNT L. Thisis not a clock type load but rather a write type loadin which the
‘counter is loaded without a clock whenever pin 11 is low. Pin 05 is used to determine direction of count. Note that

this signal is derived from bit 5 of the count through a 74H04 inverter at E52. When bit 5 is set, the output of the
inverter is low, causing the counter to count up. When bit 5 is clear, the count is down. Thisis usedin ASH SO that a
nght shrft will count up and a left shrft wr]l count down (always toward 0)

456

The counter always counts if it is clocked (CLK COUNT at pin 14). If the load input is low it will override the clock input. The clock is enabled by COUNT=0 L inverted. This way whenever the count has reached
0, counting ceases.

The 74H50 at E46 operated as an XOR of BR15 and BR14 is used durmg an ASH or ASHC left operatron to

forecast an impending change in sign. The output-of this gate feeds an OR (7402) whichis also fed by the EPS(V) |
bit. This provides a latch: path for the EPS(V) flip-flop so that once it is set it will remain set regardless of what .
happens at the XOR from that point on.

Each output of the counter is fed to the FIS board (M7239) for use in branch tests durlng floatmg instructions.

There are three multrplexers on thrs sheet each used to set control flip-flops for each external status b1t in the

option. The flip-flop outputs go to the RDMUX and the EPS(Z) is also fed to the FIS board. The dual 4:1
multiplexers are used to control the bits. Because there were more than four conditions required to control the C.
bit, an additional half 74153 is ORedin to control the (EPS(C)) bit flip-flop. In the CV MUX at E53,the V portron
of that multiplexer is always enabled but-the C portion is disabled by SDVMZ(I) H when the C MUX at E66 is
enabled.

| The combinations of the basic select b1ts (SCVM(2 0) and SNZM(I O)) requrred to perform multrplexmg operatrons'
are listed with their resultsin the truth tables provrded on this. drawrng

487 KEROM Word (Dwg KE-7)

~ This logic contarns the basic KE ROM word (U80 57), 24 bits of ROM that control the KE11-E. All outputs from
the ROMs are fed into 74174 hex regrsters except bit CLK UPP8 whrch is a drscrete flrp flop Output srgnals are

{

listedin Table 49,

This sheet contams six 4-bit ROMs (23 BXXA?2), feeding 24 brts into four 74174 hex register gates. One exception,

EUPPS at coordinate C-2, is fed to a discrete flip-flop. The enable for the ROMsis EUPP8 L. The signal CLR EU H is
just a pull up for the registers. Regrsters are clocked by CLK EU (3357) H generated on KE-5.-

The boxes 1abe1ed 13- 11003-02 on the outputs of each ROM bit are resrstor drvrder networks whrch are part of a_

16-pin IC package (see table on this drawing (KE-7) for schematic and values)

|
Table 4-9
~ KE-7 Output Signals . -~

- Mnemonic

. Description

CLKBR(1)H

- An enable for the clocking'of the BR -Re-éister— Gated with P3 on KES

EUBFO(1)H | |

External Microbranch Field. Used on KE4 for the EUBC MUX Also used on FIS

board for the one EUBC MUX on that board

2
3

ECNT()H

o ‘.Enablve Count An enable to clock the count gated with P END H on KE-5.

CLK UPPS(1)H |

Enable for clocking bit 8 of the UPP. Gated with ECLK U L on KE-S.

LCNT(I) H

Load Count An enable for the srgnal thatis gated to load the counter. Gated with P1
N

and P2 on KE-S

4-57

Table
4-9 (Cont)

GPCo(1)H

CLKC(1)H

| |

-1

" Clock NZ. Enable'for the EPS(N,Z) bits clock.

as above for the C, V multiplexer.
> Same

- |

-1t

STRDM(I) H

Select bits for the N,Z multiplexer used on KE-6.

) SCVMO(1) H N o

. Clcck,V. Enabl-e for the EPS(V) bit clock.

~ CKLNZ(1) H B

SRDMO(I)H

decoder.

EPS(C).

CLKV(I) H S 1

V'SDRO(I) H

The three bits in the GPC field of the U Word used on KE-5 as an 1nput to the GPC

Clock C. Used on KE5 gated with P1 and P2 to generate the clockrng signal for the

- SNZMO(1)H

| | Descrlptron

»»Mnie‘.m'onic' B

)

' KE7 Output Signals

| .'

Select bits for the DR Register that determme a shift left, a shift rrght a load or
|

NoOp. UsedonKE6

Select bits for the RD MUX. Determines wh_rch MUX mput is sent back to the basic

machine via the BUS RD(15:00). Used on KE-3 and KF-3

_’Strobe RD Mux. Used on KE3. Enables the 74H01 drrvers to the BUS RD(15 00)

48, 8 KDROM Word(DwgsKEtandKE 9)

‘This logic (2 sheets) contains only those ROM bits in the basic machine that are actively duphcated Those that are

~ bits control the inputs to the basic machine U Register rather than thosein the KD11-A ROM WhJChis drsabled by
|

- the settrng of UPP8 Output srgnals are lrstedin Table 4- 10

Table4-10

Descnptron

KE-8 and KE-9 Output Signals

,‘

Mnememc I

| 'BUS U(43 00) L

;

. Mrcrobus output srgnals All go tothe three Berg 40-pin connectors on the back of the

‘module. There are three cables to the basic machme The connectors are shown on

4-58

\\\w‘/,f

not actively duplicated are driven low by the KE11-E during the time that the option is enabled. These outputs are
~ wire-ORed with the outputs of the basic machine ROMs; and when the option is enabled (by UPP8 being set), these

An example of one ROM bit feeding two U Register bits.is seen at coordinates C-6. Here one bit from the ROM is

feeding two bits back to the basic machine through a pair of 74HO1 gates (BUS U40 L and BUS U39 L).
It is not
necessary to actively duplicate all the bits in the basic machine, but they
do have to be driven low if they are not

used. As long as the option
is enabled, these bits are driven low and always register Os. These bits are the SPS field (a
3-bit field) in the basic machine U word from which only 2 codes are required in the EIS. The terminators for the
- BUS U bits are not shown on this sheet because they are located in the basic machine. There is a terminator,

however, for the signal feedmg the 74H01-1s on this drawing because that signalis not sent d1rectly back to the basic
machme The 74HO1- 1is an open collector gate and its termmator is backin theprocessor. |

On sheet 9 at coordinates D-6, the jumper W3 must be removed when the FIS option is installed. This
is used when

fetching the floating arguments. A common flow is provided for fetching both arguments, and the first time through,
the ROM always specifies an odd general register address in which to store the argument. The first time the odd
address is used and the second time through the even address is used. Thisis done by input signal ARGA at D-7. It
enables that gate when ANDed with an active option to drive BUS U9 low. Thisis the low b1t of the register address
thatis being negated to yield an even reglster address.
|

489 HSR and MSR (DwgKF-2)
This is the first drawmg for the M7239 modulc constltutmg the FISoptlon The same t1m1ng prevails for th1s 0pt10n

as that described for the FIS optlon (Paragraph 4.8.1). These paragraphs pertam to only those customers utilizing
the Floating-Point Option.

VDrawmg KF2 contams the HSR and MSR Reg1sters Both are left/rlght shlft reglsters and both are fed from the BR
_V1n the EIS optlon They are used as elther holdmg reglsters or shlft reglsters Output 51gnals are hstedin Table 4- 11
Table 4-11

KF-2 Output Slgnals

* Mnemonic B

MSR(15: OO)(I)H
MSROO L

o Descnptlon

The outputs from the MSR left/right shift registers.
The inverted output of MSR00. Used on KE-5 to determme aux111ary ALU functions
for floatmg divide mstructlons

HSRISL

| HSR(IS :00)(1)H

The 1nverted output of HSRIS Used on KE-2 as DROO shlft 1nput data.

The outputs from the HSR left/rlght shift reglsters

These reglsters consist of 74194s fed in parallel by BR(IS 00)(1) H. Both registers are clocked by E(P1+P2) H
generated on the EIS board. This clock is always present at both registers but no.action will occur until the proper
select bits are present on the register. Selection is accomplished by a 3-bit combination of SHSRO(1) H, SHSRl(l)
H, and SMSR(1) H. The HSR select bits are fed directly to the HSR Register, and are also gated into the MSR

SMSR is asserted as well, the MSRis also loaded. Thisis whyin the flows whenever both reglsters are to be used, the
'MSRis loaded first and then the HSRis loaded without affectmg the MSR

The clear inputs to ‘these registers are tied to pull ups. There are shift inputs to the high bit and low bit of both

- registers.

Generally, these reglsters are used to shift data. In. FMUL, they are concatenated
with the MSR being the lower

register and the HSR the higher. In this apphcatlon HSROO(1) H enters the shift input of MSR15 at DS3,
coordinates D-7. The low shift input to the MSRis EPS(C) at coordinates C-3 usedin shifting left.

4-59

The high bit shift input to the HSRis DROO(I) H at coordinates B-7. In FMUL, the lowv DR bit will enter the high
~shift input of HSR. The low shift input of the HSRis either MSRIS gated wrth the code GPC=5, or Os. When GPC=5
- is not present Os are shifted into the HSR. .
|
l
~
'4 8. 10

FRDMUX(IS 00) (Dwg KF 3)

The FRDMUX is a 16-bit wrde 4:1 multiplexer that selects one of four sets of 16 brt 1nputs to be fed to the CPUvia |
the BUS RD(15 00). This operates similarly to the RD MUXin the EIS option, using the same select bits as usedin

that logic with a separate strobe (STFRDM) to enable this set of drivers instead of the EIS drivers. Qutput srgnals are
listedin Table 4-12.

Table 4-12
KF-3 Output Si_gnal’s

Mnemonic

BUS RD(I'S:OO) L

)

Descnptlon

The outputs of the 74HO1-1 drivers to the BUS RD over whrch data frorn the FIS
optron is transferred to the CPU.

Outputs of the dual 4:1 multiplexers (7415 3) are fed to open collector NAND gates (74H01-1). These then drive the
BUS RD where the datais transferred back to the processor. Asin the RDMUX of the EIS, the F RDMUXis selected
by combinations of SRDM1(1) H and SRDMO(1) H but information is not transferred to the BUS RD until the
drivers are enabled by STFRDM(1) H. A similar enable is provided on the FIS counterpart, whose input to the

multiplexers is transferred to the bus and is listed in t_he ‘truth table on this sheet as a function of the select bits.
A 00 combrnatron selects the MSR Register while a 01 selects the HSR Register. If the combinationis 10 the C input

is selected. Here the high argument of the floating point is assembled into one 16-bit word. A 11 combination selects
the constants as generated on KF4. Note that not all bit postrons are needed for this transfer Those that are not
requrred are tied to ground.

4.8.11 ROM and Control (Dwg KF-4)
This logic provides the extra control needed for the FIS 1nstructrons It comprises combinational logic and two
ROMs that supply the extra ROM bits required by the FIS logic. The logic controls the registers in the FIS and
generates the constants. Output signals are grven in Table 4-13.

Table 4-13

KF-4 Output Slgnals ol

‘Mnemonic

STFRDM(:l) H

o - |

Descnptlon

o »»Str(‘)be ;floating RD rnultiplexer brt,' uSed env KFLS to"enahle],thé FRDMUX to the BUS RD

SHSRO(1)H

SMSR(1) H

||| -

Select bits for the HSR 'Register.'

Select bit for the MSR Regrster Enables the SHSR(1 0) (1) H brts to control the MSR
Reglster

4-60

Table 4-13 (Cont)

“KF-4 Output Signals
Description

Mnemonic

Provides additional branch test conditions for the FIS. Disables the EUBCI branch

EUBF4

multiplexer in the EIS and enables FUB MUX on this print (KF-4). Allows the FIS to

“control brt 1 (EUBCI) of the ROM address rather than its counterpart in the EIS

FCIBUS(‘-O) H
CONO(1) H
1
|

Sets the appropnate bt (BUS Cl) on the C hnes to mrtrate a DATO operatlon for
floatrng -point operations.

These are the two bits that select the constants generated by the FIS option. These together
with GPC=6 combine in the logic to generate CONxx srgnals that are used to generate the
octal constants 400, 244, 6, 30, and 200.

FAUX ALUH
-

FDIVH

Floating auxiliary ALU control. Used in the floating divide loop to enable auxiliary ALU
control on KE-5 of the EIS prints.

Floatrng divide. Used here to enable the generatron of FAUX ALU H, and on KE-2 of the |

EIS board as one of the shift input enables for the DR Register.

FIS INSTR L

Allows a floating instruction to enable the option ROM and to branch to the FIS flow.

EUBCS L

Inputs to the M7232 module U word in the basic machiné When low, ORs into the ROM

address to modify the address Used only to abort the floating instruction in event of a bus

request.

FUBC1

Controls the lowest modifiable bit (1) of the ROM address to provide addrtlonal branch tests

ZB+EPS(Z) H

The OR of ZB (previous) and EPS(Z) present Z status information.

AB(1)H

Output of the ZB flop (see above).

"ARGA(1)H |

Sent to the EIS, gated with bit 8 of the ROM address. When set, forces selection of the even

- UNFLH

Underflow, indicated by either the EPS(Z).bit being set or B15(1).

. OVFLH

for the FIS 0ptron

regrster for storage of floating arguments even though the ROMis selectrng the odd regrster |

Overflow, indicated by both B15 being clear and the D Register not equal to O

The two ROMs (23-BXXA2) are fed by BUPP(7:0) H and are enabled by EUPP8 H. Their outputs feed two 74175

quad registers that supply the resultant outputs to the logic. The clear inputs to these registers are tied to a pull up
resistor and they are clocked by CLK EU(88:57)
H, generated on KE-5 of the EIS board.
|

The 74151 (FUB MUX) is an 8:1 multiplexer that controls bit 1 (EUBC1) of the ROM address, thereby providing
extra branch tests not available with the EIS logic. This MUX is strobed by EUBF4(1) H ANDed with bit 8 of the

ROM address. When EUBF4.is asserted, the O side of that bit disables the multiplexer EUBC MUX A on KE-4 of the

EIS board and enables the FUB MUX. Inputs to this MUX are selected by combinations of EUBF(2:0)(1) H. The
table on this sheet (KF-4) gives the results of these combinations.

461

When DO is selected the state of ARGA flip-flop is tested durlng floatrng argument fetching to determine if the A
» argument has been fetched. When D1 is selected MSRO1 is tested. This is used in the floatrno multiply loop to
| 'determrne the need for addttron

D2 tests the OR of ZB and EPS(Z). Note that the ZB flrp -flop gets its 1nput from the EPS(Z) flop andis clocked at
the same trme as EPS(Z) D3 looks at counter b1ts 7 O to determine when the count exceeds 305.

D4 tests to see if the answer is normahzed There are two tests here: 1) is the answer now normalized? (DRO9(1)

H), or 2) will the answer be normahzed after the shift? (DRO8(1) H). The 74H50is a NOT OR AND gate in which
~one of the mputs on each OR gate must be satisfied. If GPC=1 is asserted, pin 02 of E09 will be enabled causing the
logic to look at DR0O9 on pin 05 If GPC-—l 1s not asserted, the inverter outputat pin 04 will be low causing DROS at
~

pin 03 to be exammed

If D5 is selected MSROO(I) H is tested. ThlSis used to deterrmne whether to add or subtract the hrgh drvrsorin the
'FDIV loop

4-62

CHAPTER 5

INSTALLATION AND MAINTENANCE
REFERENCE INFORMATION

5.1

INSTALLATION

When the KE11-E is included as part of the initial PDP 11/40 System the M7238 module is 1nstalled prror to
shrpment If it is bemg added to an exrstmg system proceed as follows:

Insert the M7238 modulein 2(A—-F)

b. Remove thejumper (Wl) on processor module M7233 (IR DECODE) at locat1on S(A—-F ).

- C. |

Install the three° ‘over the back” cables from J l J2, and 13 of the M7238 module to J1, J2, and J3

e respectrvely of the M7232 (U Word) module at locatron 3(A-—D)

L When the KEl l-F is to be added to a system, the KEll -E must also be added Proceed as follows

| ,a'.» » Perform steps a. throughc above

b, . Insert the M7239 modulein 1(A—D)
- C. | On the M7238 module, remove the followihg. jumpers: o
| 1. Wlf‘ fromC_OZFZ.to _'gr’ound..._f |

2. Wa2from AO2B1 to ground.
3. W3 from D02L1 to:-grouhd.p
If these jumpers are notremoved the KEI l-E Optlon wrll stlll

execute EIS mstructrons but will not execute FIS mstructrons

When the above steps are performed the KEllE and KEll F Optrons are ready to be checked out usrng the.

‘dragnostrc programs supphed wrth the optrons

52 MAINTENANCE
The deSrgn' corrstructron‘and implementation of the M7238 and M7239 modules used in these options are simil.ar to
those used in the KD11-A Central Processor and other options. Maintenance procedures for the entire system are

describedin the PDP-I 1 /40 Sysz‘em Manual, Chapter 7. There are no specral maintenance procedures for these'
;

optrons |

5.2.1

Dlagnostlc Programs

Table 5-1 lists the KE11-E and KEI 1-F diagnostic programs These programs are part of a complete package of basic
processor and option diagnostics. The sequence of running the diagnostics is set up to completely test the KD11-A
Central Processor before attempting to run the diagnostic programs for these options, thus ehmmatmg the KD11-A
as a possible cause of failure.

Table 5- 1

KEll -E and KE11-F Dlagnostlc Programs

MAINDEC No |

- Funetion

KEI 1-E EIS Optlon

MAINDEC-11-DCKBL

MAINDEC-11-DCKBK-A-PB

“MAINDEC-11-DCKBJ
MAINDEC-11-DCKBI

MAINDEC-11 DCQA

| .

Divide instruction

Arithmetic shift combined mstructmn
Arithmetic shift instruction

) |
|

Multiply 1nstruct1on

MUL/DIV Exerciser

KEll -F FIS Optlon

MAINDEC-11.DBKEA

MAINDEC-11-DBKEB

MAINDE_C-AI-I-,DBKEO_

Basic instruction tests

Exerciser

GTP overlay

The MAINDEC (maintenance descriptions) for each diagnostic program indicates how the -progtefn is to be loaded

and run. The program listing indicates the functional logic that is being tested by each routine. The diagnostic

programs are written along functional lines to test and exercise all of the KE11-E and KE11-F logic.
5.2.2 Troubleshooting Test Procedures

The KM11-A Maintenance Module (also referred to as the mamtenance console) provides the user w1th a means of
manually operating the system and monitoring status during maintenance operat1ons

The maintenance module isa Wi 30/W131 board containing4 switches a-nd 28 -indieators that monitor various signals
within the processor. When an indicator is lit, it means that the associated
logic level is high. An overlay can be
attached to the module to indicate what signals are being monitored. This overlayis necessary because the moduleis designed as a general-purposedevice and can be used, without modification other than using different overlays, in
many PDP-11 devices. The specific functlons momtored by the module depend onthe logic signals ered to the
device receptacle that receives the module

When the module is used for momtonng operatlon of the KEll -E Extended Instruction Set and KEll -F Floatmg
Instruction Set Opt1ons addition of the KE11-E/F overlay (Figure 5-1) isnecessary. In this application, the module

is inserted into processor slot E1 and the 12 indicators on the right of the overlay are used for the KE11 ‘E/F
functions. Note that none of the switches are operational when the module is used for this purpose The functions
momtored by the indicators are hstedin Table 5-2.

The functions descnbed in Table 5-2 indicate the general

purpose of the indicator. At times, a single indicator may show

~a number of functions, depending on the current state of the
- processor and option. This is why in orderto use the

maintenance module properly, the flow dlagrams should be

followed to determme the s1gmficance of an mdlcatlon atany

~ one time.

~ Table 5-2‘

KE11-E/F Maintenance Module Indicators

Ihdicator' |

Indicati()n

B15

Bit 15 of CPU B register. In divide, used with DROO to

K1-5

ECIN 00

An external carry-in tothe ALU.

'KE-5

EXP UNFL

- Indicates exponentlal underflow during EXI1 of floatmg point

- KF4

Indicates exponential overflow during EXI1 of floating point

'KF-4

Used in conjunction With‘ other bits to indicate various

KE-2

determine the ALU function to be performed in division loop.

flows. .

EXP OVFL

flows.

| DROO

conditions, e.g., with Bl5 in divide to determine ALU
functions and to determine need for divisor correction. See

EPS(C) for other use.

,Used as test for normalization (see floating point flows page

KE-2

MSR0O0

B»it,OO of MSR' register. Indicates ALU function in FDIV.

KF-2

MSRO1

Bit 01 of MSR register. Indicates ALU function in FMUL.

KF-2

DRO9

EPS(C)

C bit of extended processor status. In MUL, used with DROO

~ to determine ALU function in multiply loop.

- EPS (V) B

" Overflow bit of the extended processor status

KE-6

EPS (Z) B

Zero bit
of the extended processor status

- KE-6

EPS (N)

Negativebit of the extended processor status

5-3

KE-6

T EPS s
A
PBAY
A
A
PBS
.
K
s 12 L4,
9 4 e o B15 | DROO | Fg
o

| EPS
ECIN | pRog
/PBA//PBA f/ PBA %/PBA/
09 | )
/.7/_00--

/16 /f13./y’1o

S
ZPF%A Z/P“BA Z% PBA é/PBA'/ EXP
a

8 7/

0
4////
4////%//////%
) T
A U
%ROM/

ROM%% ROM%/ROM/

UNFL
|

E XP

///é/% ///B/.//,////S/A ///Q/A' lOVFL

|—

MSR

EPS

MSR

|°- EPS

, ot

(z)

(N)

11-1630

'Figute 5-1 KEI11-E/F Maintenance Module Overlay

5-4

APPENDIX A.

GLOSSARY OF TERMS

A.l

GENERAL

Table A-1 contains a co]lectron of some of the terms usedin this manual that may need defrnmg It does not include
all terms, only those that it is thought might be confusrng Listingis in alphabetical order

Table A1
| Glossary of Terms

) S

Term

Defimtlon

~ADD
ADR

Add (mstructron)
Address
|

ALU

Arithmetic Logic Unit

ALUM

Arithmetic Logic Unit Mode

~ARGA

Argument
A (f/f) .

“ASH

Arithmetic shift (instruction)

- ASHC
BBSY

Arithmetic shift combined (instruction)
Bus busy
L

BRQ

BUS

Bus request

Unibus

BUSU

. Bus mrcroprogram

Yoo

BUT

Branch microprogram test

CIN

Carry-in (ALU)

CLK
- CLKB
- CLKBA

- CLKD

CLKOFF

CLR
~CON
COUT MUX

Clock
‘Clock
B Register
Clock BA Register

Clock D Regrster

Clock off

Clear C,VN,Z(1nstruct10n)
‘Constant
“Carry-out multiplexer (ALU)

C1BUS
DAD =

~ C1 of Unibus
Discrete alteration of data

DIv DMUX

- Divide (instruction)
~ Data multiplexer

DEST

- EINSTR

Destination

Extended Instruction

)

‘

Extended arithmetic instruction set

(Cont)

‘Glossary of Terms

Term

Definition

. 'EPS

‘Extended Processor Status

~ EUB

Extended microprogram bus

- EUPP

EXP

Extended microprogram pointer
Exponent

Function of

FADD

Floating add (instruction)

FC1BUS

Floating C1 Bus

FDIV
FETCH

Floating divide (instruction)
Fetch (Processor State)

FINSTR

Floating Instruction

- FIS
-~ FMUL
FSUB

Floating instruction set
'Floating multiply (instruction)
Floating subtract (instruction)

FUB

Floating microprogram bus

IR
ISP
JAMUPP
MUL

- Instruction register
- Instruction set processor
- Jam microprogram pointer
Multiply (instruction)
“

- MUX

Multiplexer

NO-OP

No operation

OVFL

Overfiow

‘PC

- Program Counter

Processor Status Register

R(x)

Scratch Pad Register

Reserved instruction
Select arithmetic logic unit
Select arithmetic logic unit mode

RSVDINSTR =
SALU
SALUM
SBC

Select B constant

SERVICE

SET COND CODES '

SF
~ SFV1
SRC

Service

Set condition codes

o
o

Source field
Source field ORed with 1
Source (processor major state)

STPM

Special Trap Pointer Marker

TRAP

User call
Microprogram

UBF

Microprogram branch field

UNFL

Underflow

UPP

Microprogram pointer

U WORD

- Microprogram word

VECT

Vector

XOR

Exclusive OR (V)

“Z” bit previous state (flip-flop)

A-2

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EK-KE11E-TM-002

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