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Document:	KDJ11-D/S CPU Module User's Guide
Order Number:	EK-KDJ1D-UG
Revision:	002
Pages:	151
Original Filename:

OCR Text

EK-KDJ1D-UG-002

KDJ11-D/S CPU Module
User's Guide

dlilgliftiall}

EK-KDJ1D-UG-002

KDJ11-D/S CPU Module

User's Guide

Prepared by Educational Services

of
Digital Equipment Corporation

First Edition, April 1986
Second Edition, May 1987

The information in this document is subject to change without notice and should not be
construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation
assumes no responsibility for any errors that may appear in this document.

Using Digital’s networked computer services, this book was produced electronically by the
Educational Services Development and Publishing department in Reading, England.
The following are trademarks of Digital Equipment Corporation:

digliltiall]
DEC
DECmate
DECUS
DECwriter
DIBOL
MASSBUS

PDP
P/OS
Professional
Rainbow
RSTS
RSX

RT
UNIBUS
VAX
VMS
vT
Work Processor

Contents
Preface

Chapter 1
1.1

1.2

1.3

1.4

1.5

ARCHITECTURE

FEATURES . . . . .. e

1-2

1.1.1

Features Not Supported

1-2

1.1.2

Registers

. . .. ...

...

... ...

. . . .. ... .. ..

SYSTEM CONTROL REGISTERS . . . ... ... ... . ... ... ..

1-3

1-7

. . .. ...... ... ... ... ... ...

1-7

1.21

Processor Status Word

122

Program Interrupt Request . . . .. ... ... ... .. e

123

CPUError Register.

. . ... ...

1.2.4

Maintenance Register . . .. ... ...

12,5

Line Time Clock Register

1-9

... . ... ..., 1-10

... . ...

.. ... ... ... ... .... 1-11

. ... ... ... .. ... ... ... ........... 1-12

126

Native Register . . ... ...

127

DLART Registers . . . . ... ...

... .. ... ... ... 1-13

... .. .

1.2.7.1

Receiver Control/Status Register

1.2.7.2

Receiver Data Buffer

1-14

. ... ................
... 1-14

. . ... ...... ... ... ... ... ... ... ..... 1-15

1.2.7.3

Transmitter Control/Status Register

1.2.7.4

Transmitter Data Buffer

. ............ e 1-16

. ... ... .. ... .. ... ... .. ... .. ..... 1-17

GENERAL PURPOSE REGISTERS . . . . . .. ... .. i 1-17
1.3.1

Stack Pointer.

1.3.2

Program Counter . . .. ......
... ...
......
,
. 1-19

. . . ... ...

. ... . L 1-18

INTERRUPTS . ... ... ... e 1-19

141

HaltLine

14.2

HALT Instruction . . . . ... ...

... .. ... ..

1-21
..

MEMORY MANAGEMENT . . . .. ... ...

1.5.1

Physical Address Space

. . 1-21
.

1-22

. .................
. o 1-22

1511

UOPage . ... ...

1.5.1.2

Selftest ROM

1.5.1.3

Bootstrap

. . ... ... ..

1-23
.

1-24

... ..... . ... 1-25

Virtual Memory Mapping . . ... .. ... .. 1-25
1.5.2.1 16-bitMapping . . . ... ... 1-26
1.5.2.2 18-bit Mapping . . . . . . .. .. 1-26
1.5.2.3 22-bit Mapping . . . . . . .o 1-27
Compatibility . .. ... ... 1-28
1.53
Virtual Addressing . . . ... . ... 1-29
1.5.4
Interrupts Under Memory Management Control . . ................. 1-29
1.5.5
Building a Physical Address . . . ... ...... ... ... o 1-30
1.5.6
Management Registers (PARs and PDRs) . . ...................... 1-32
1.5.7
1.5.7.1 Page Address Register . . .. ... ... . 1-33
1.5.7.2 Page Descriptor Register. . .. .. ... 1-35
Fault Recovery Registers . . . .. ......... .. ... ... 1-36
1.5.8
1.5.8.1 Memory Management Register 0 . . . .. ..................... 1-36
1.5.8.2 Memory Management Register 1 . . . . ...................... 1-38
1.5.8.3 Memory Management Register 2 . . . . ...................... 1-38
1.5.8.4 Memory Management Register 3 . . . .. ..................... 1-38
1.5.8.5 Instruction Back-up/Restart Recovery . .. .................... 1-39
1.5.8.6 Clearing Status Registers After an Abort . . ................... 1-40
1.5.8.7 Multiple Faults . . . ... .. ... . 1-40
1-40
Typical Usage . . .. .. ..
1.5.9
... 1-40
1.5.9.1 Typical Memory Page . ... ... ...
.......... 1-42
......
....
..
..
.
Pages
1.5.9.2 Non-consecutive Memory
1.5.9.3 Stack Memory Pages . . ... ... . ... 1-43
1-44
MEMORY SYSTEM REGISTERS . . . . . . ...
Memory Error Register . . . ... ... .. ... 1-44
1.6.1
FLOATING-POINT . . . .. e 1-45
Floating Point Registers . . . .. ... ... .. ... ... 1-45
1.7.1
1.7.1.1 Floating-point Status Register . ... ........................ 1-45
1.7.1.2 Floating-point Exception Registers . . .. ..................... 1-47
..... 1-48
...
1.7.1.3 Floating-point Accumulators . ... .. ....

1.5.2

1.6
1.7

Chapter 2
2.1

INSTALLATION

CONFIGURATION . . . . e 2-1
Power-ur OpHONS . . . . ... o 2-5
2.1.1
2.1.1.1

2.2
2.3

Power-up SEqQUENCE . . . . . ... . . 2-5

2.1.1.2 Power-down SEqUENCE . . . . . ... .. 2-5
Bootstrap Options . . .. ... ... 2-5
2.1.2
2-9
HALT Option . ... ..o
2.1.3
2-10
.
Factory Configuration . . .. . .. ... .
2.1.4
e e e 2-11
DIAGNOSTIC LEDS . . . . .
MODULE EDGE CONNECTOR PINS . . ... e 2-1

2.4

HARDWARE OPTIONS

241
2.5

2.6

. . ..

Restricted LSI-11 Optons . . ... ... ...

KDJ11-D/S INSTALLATION

e 2-16

i 2-16

. . . . . e
s 2-19

2.5.1

Pre-installation Considerations . . . ... .. ... ... ... ... .. .. ....... 2-19

2.5.2

System Differences

253

Installation Procedure . . . .. .. ... ... ...
. 2-20

. .. ... ...

... ... .

2-20

SPECIFICATIONS . . . . .
s e s
s, 2-21

Chapter 3

FUNCTIONAL DESCRIPTION

3.1

INTRODUCTION

3.2

DCJ11 MICROPROCESSOR

321

. . ... .
e e
e
e

DCJIL Cycles
3211

3.3

e e e

3-1

. .. ............ e

3-4

. ...

3-8

NIO . ... e, R

3-9

3212

BusRead......

... ... .. . .. ...,

3213

BusWrite

. ... . .. ... 3-10

3214

GPRead . ........ ... ... ... .3-10

3215

GPWrite.

3216

TAK

. ...

3-10

. ... 3-11

ATODECODER . . . ... e, 3-11

3.4

GP DECODER.

3.5

MEMORY DECODER . . .. ... 3-14

. . . . ..

3-13

3.6

HODECODER

. .. . ., 3-16

3.7

CYCLEDECODER . . . ... 3-18

3.8

IO READIWRITE LOGIC

. . ... e, 3-20

3.9

IAK DECODER AND VECTOR GENERATION LOGIC . . . .. ................ 3-22

3.10

MEMORY STATEMACHINE.

3.11

BUS STATEMACHINE

3.12

SACKTIMEUP, NXM, BBS7, BTWT

SACKTIMEUP and NXM

3122

BBS7and BWTBT

PARITY AND ABORT

3.14

REGISTERS

... .. ... . .. ... . 3-26

. ......... S 3-26

... ...... .. ... ..., 3-26

. ... .. e 3-29

. . . . e 3-29

3.14.1

Memory Error Register . . . ...........
.. .. . .. .. ... ... 3-29

3.14.2

Maintenance Register . . ... ...

3.14.3

Native Register . . .. ...

3.14.4

Line Time Clock Register

RAM ADDRESSING

3.15.1
3.16

... . o, 3-24

. .. ... . i 3-26

3.121

3.13

3.15

. . . ...

DLARTS

3.16.1

Refresh

...

... ... ... 3-32

.. ... .., 3-32

. . ... .....
.. ... ...............
.... 3-32

. ... ... e, 3-32

.. ... ... . . . ... 3-34

. .

DLART Registers . . . .. ...

3-35

... .. 3-35

Chapter 4
4.1

INTRODUCTION . ..t

4.1.1

4.2

4.2.3

4.3

4.4

et e

e e e e

Terminal Requirements . . . . ......... ...

e e e

e 4-1

4-2

Console Mode .. ..... ...
i
4.22.1 Manual Start . ... ... .. .. . ..
ROM Part and Version Numbers

e
e

e 4-5
e 4-6

. . ... ... .........
.. ... ..., 4-6

424
MessageFormats . .. ....... ...
CONSOLE MODE . . . . .

... . 4-6
e e e e e
e
e
e 4-7

431

Entering Console Mode Commands .. ......................... 4-8

4.3.2
433

HELP Command . . . . . ... ...
e
e e 4-9
BOOT Command . .. .. ... ... ...t 4-9

434

LIST Command . . . . . . . . .

435

MAP Command

4.3.6

TEST Command . . . . . . .. .

4.3.7

WRAP Command

. ... .. . ... .

441

Test T Errors . . . . . . o

442

Test 2 BrrOrs . . . . .

443

Tests3through6Errors

4432

e e 4-11

. ... .. .. .. e 4-12

TEST RESULTS . . . . .

4.43.1

BOOT SELECT . . . .
i
e
e e e e
e 4-2
4.2.1
Automatic-boot Mode . . . . . ... ... 4-5
4.2.2

BOOT AND DIAGNOSTIC ROM

e e

e 4-13

e 4-14

4-15

e e 4-15

. ... ...... ... ...................... 4-15

Test3 Through 6 Error Messages . . . .. ................
..... 4-15
CommandstoOverride Errors. . . . ... ... ... ... . ... ........ 4-17

AUTOMATIC-BOOT MODE . . . .. . .

e 4-17

4.5.1

Boot Code . ... ... ... . .
e 4-17

4.5.2

Automatic-boot Sequence (Autoboot) . . . . ... .. oL 4-19

4.5.3

Bootstrap Error Messages

4.5.4

Disk and Tape Autoboot (Except TU58) . .. ................
... ... 4-20

4.5.5

DPV11, DUV11, DLV11-E/F and TU58 Autoboot

4.5.6

DEQNA Autoboot . . . .. .. . . e 4-22

45.7

Bootable Media . . . . . . .. ... . . . 4-22

. . ... ....... ...

... ... 4-19

. ... ............... 4-21

4.6

LANGUAGE SELECTION . . . . . . . e
e 4-22

4.7

TROUBLESHOOTING . . . . . ..

Index

e e

e 4-23

Examples
4-1

Typical Automatic-boot Message

4-2

Typical Power-up to Console Mode Message

.. ............................

.. ....................

4-6

4-7

4-3

Console Mode Prompt . .. ........ ... . ... ... ... .. ... ... .. ...

4-7

4-4

Invalid Entry Message

. .. .. ...,

4-9

4-5

HELP Command . ............
. ... ...

4-9

4-6

BOOT Command Argument Prompt . . . ......................... 4-10

. . ... ... . ...

4-7

BOOT Command Using DL2 . . ... ...

4-8

LISTCommand

........... ... . ... ... ... 4-11

4-9

MAPCommand

. .......... .. ... .., 4-13

4-10

TEST Command . .. ...

...

... ...

.. ... ... .......... 4-11

.. . .. ., 4-14

4-11

WRAP Command Without Switch . . .. ...,

4-12

WRAP Command With Switch . . . ... ... .. .. ... .. ... .. ... ...... 4-14

... ...

... ........... 4-14

4-13

On-board RAM Test Error Message . . . ... ....................... 4-16

4-14

Q22-bus RAM Test Error Message

. . ... ........................ 4-16

4-15

J11 Unexpected Trap Error Message

. . .. . ... .................... 4-16

4-16

Language Inquiry and Error Prompt.

. . . ... ...

...

.. .. ... ..... 4-17

4-17

Unsuccessful Automatic-boot Message . . .. . ...................... 4-19

4-18

Console Mode Boot Error Message (L of 2) . . ... ................... 4-20

4-19

Console Mode Boot Error Message 2 0f2) . . .. .................... 4-20

4-20

Language Inquiry . ... ... ...... . ... ... ... ... 4-23

Figures

_____

1-1

Registers

1-2

PSW (Processor Status Word) Register . . . . .. .. ...................

1-8

1-3

PIRQ (Program Interrupt Request) Register . . . ... ..................

1-9

1-4

CPU Error Register

1-5

Maintenance Register . . . ... ...

1-6

LTC (Line Time Clock) Register BEVNT) . . . .. ... ... .. ... .......... 1-12

. ... ... ... ... .

1-3

. .. .....
... .....
... ...... ... ..
. ..... 1-10

...

... ... .. ... .. 1-11.

1-7

Native Register . . ... ... ... ... ... ... ... . 1-13

1-8

Receiver Control/Status Register RCSR)

. . . .. ..... ... ............. 1-14

1-9

Receiver Data Buffer (RBUF)

1-10

Transmitter Control/Status Register (XCSR)

1-11

Transmitter Data Buffer (XBUF)

1-12

Physical Address Space

1-13

Self-test ROM Space

1-14

Bootstrap Space

. ... ... ... .. ... ... . . ............. 1-15
... ... ...... ... ........ 1-16

. . . ... ... ... .. . .. ... . .. . ... ... 1-17

. ......
...
......
... ... .. ...
.. 1-23

. ... ...... ... ... ... ...

1-24

. ......... .. .. ... 1-25

1-15

1l6-bit

1-16

18-bit Mapping . . .. ...

Mapping . .. ......

... ... ... .. ...

1226

1-17

22-bit Mapping . . ... ... ... 1-28

1-18

Virtual to Physical Address Mapping . . . . .. ...................... 1-29

. ... ... 1-27

Vil

e e 1-30
e e e
Virtual Address Fields . . . . . . . . . . .
Virtual Address Displacement Field ... ... ...................... 1-31
Physical Address Assembly . . .. .. ..... ... ... ... ... . o0
1-32
Management Registers (PARsand PDRs) . .. .. .................... 1-34

Page Address Register (PAR) . ... ...

...

.. ...

1-35

Page Descriptor Register (PDR) . . . . .........
... .. ... ... ...... 1-35
.... 1-37
................
..
.
.
.
MMRO)
O
Register
Management
Memory

Memory Management Register 1 (MMR1). . . .. ..............
... ... 1-38
..... 1-39
................
..
.
(MMR3).
3
Register
Management
Memory
Typical Memory Page . . . . ... ... ... 1-41
Non-consecutive Memory Pages . . . . .. ... ... ... ... . .o 1-42
Typical Stack Memory Page . . ... ....... .. . ... ... . ... ... 1-43
... ........ 1-44
........
Memory Error Register (MER) . . ........
Floating-point Status Register (FPS) . . . . ... ...................... 1-46
2-2
.
KDJ11-D/S Module (M7554) . . . ... ... .
KDJ11-D/S Module - Early version (M7554) . . . . ... .. ...

.. ...

... 2-3

Console ODT Exit Sequence . ... ..... ... ... ... ..., 2-10
.. . . 2-17
......
... ...
Module Edge Connectors . .. ......
. ... .. . ..

KDJ11-D/S Block Diagramu . . . . ... ... ..
DCJITCPU . ..

...

3-2
3-3

Ul b
N

Memory Decoder

IO Decoder . .. .. ..o 3-17
3-19
Cycle Decoder . ... ... . ... . . ...

<
e

e
N

Bus State Machine . . . . . ... ... 3-27

e
W

SACKTIMEUP, NXM, BBS7, and BWTBT

Parity Error and Abort . ... ... .. ... .. ..

Memory Error Register Access . . . ... ... ...
Maintenance Register Access . . . ... ...

Native Register Access . ... .. ... ...... P 3-34

LTC Register ACCESS . . . . oot 3-35
Memory Address Multiplexer. . . . . ... .. ... oo 3-36
3-37
e
e
DLARTS . .

NG
D

W
W

W
|

Memory State Machine . . . .. ...

ey:

IAK Decoder and Vector Generation Logic . .. ..................... 3-23

3-21

e
W

.. .

e
|63]

. . ... ... ...

e
(@)}

IO Read/Write logic.

el
g

. ... ... ... .. ... ... 3-15

b
R

rrYrT

ATO Decoder . . ... . .
3-12
GP Decoder . . . . .. e 3-14

3-7

|
N

KDJ11-DA Block Diagram . . .. ... ...

Power-up SEqUENCE . . . . . ... .ttt 2-6
Power-down Sequence . . ......... ... ... ... 2-7

vill

.. ... . .. .

3-25

... ..................... 3-28
3-30

... .. oo 3-31
. ... oo 3-33

Tables
1-1

KDJ1lwversions . . ... ... ... ... ........... T

1-2

Address Map

1-3

PSW (Processor Status Word) Bits . . . .. .. ... .. J

1-4

PIRQ (Program Interrupt Request) Bits . . . . . ... ... ... ...

. . ... .. ... ...

CPU Error Register Bits

1-5

. . . . . . .. ...

. .. ...

1-8
. ... . .... 1-10

. .

1-11

Maintenance Register Bits . . . . .. ... ... ... . ...

L oL 1-12

Transmitter Control/Status Register (XCSR) Bits.
Transmitter Data Buffer (XBUF) Bits

General Purpose Registers . . . . .. ... ... ...

... ............ 1-15

. . . . ... ............. 1-16

. . ... .. ... ... ... ... .. .. ..... 1-17

e
e

Synchronous Interrupts . . . . ... ..
Interrupt Priorities . . .. ... ...

KDJ11-D/S Compatibility

N
<o

-19

—

Asynchronous Interrupts . . . ... .. ..

... .. ... .. . ... . . ... 1-18

Stack Pointer Selection . . . . ... ... . oL 1-18

. . ... ... ... ..e 1-14

. . ... ... ... ...

e
e
ped

Receiver Data Buffer (RBUF) Bits

Receiver Control/Status Register (RCSR) Bits

. . . .. ... ....................1-13

Native Register Bits . . . ... ... ... ... .. e 1-13

LTC (Line Time Clock) Register Bits

1-4

1-21

1-19

L L 1-20

...

1-21

. . .. ... ... ... .. ... ... . ... 1-28

Virtual Address Description.

. . . .. ...

Displacement Field Description

...

. . .. ... ...

L o 1-30

...

Page Descriptor Register (PDR) Bits . . . ... .. ...

...

.. ... ...... 1-31

... ... ... .. ..... 1-35

1-22

Memory Management Register 0 (MMRO) Bits . . . .. ........
... ...
.. 1-37

1-23

Memory Management Register 3 (MMR3) Bits . . . . . ................. 1-39

1-24

Memory Error Register MER) Bits

1-25

Floating-point Status (FPS) Bits . . . . .. ... .. ... ... . ...
Jumpers.

. . . . .. ...

.. ... ... ... ......... 1-44

. ... .. ... . 1-46

. ...

2-4

Boot Select Options . . . . ... ... ... .. ... .

2-8

Self-test ROM Display Codes.
J1Pin Assignments

. . . . ...

...

. ... . ... ............ 2-11

. . .. .. ... 2-12

Module Edge Connector Pin Assignments

. . ... ................... 2-13

Restricted or Non-compatible LS1-11 Options
KDJ11-DIS Specifications

. . . . .. ...

DCJ11 Input and Output Signals.

. . ... ................. 2-18

... ... ... ... .. 2-21

. ... ... . ...

.. ...

.. ..........

3-4

AlO<3:0> Codes . . ... .. ... . ...

3-8

BS<1:0> Codes . ... ... .. .. .

3-8

GP Codes

3-10

. . .. ... . . .

AlO Decoder OQutputs

GP Decoder Outputs

. .. ... ... ..

. . ... ... ...

. .. 3-13

. ... . ... 3-14

Memory Decoder Outputs . . . . .. ... ...

...

/O Decoder Outputs . . .. ... .. ... .. ...

...

. ... ... ... 3-15

3-17

Cycle Decoder Outputs

. ... ... i 3-19

I/O Read/Write Logic Outputs . . .. ... ... ...

.. .. 3-21

IAK Decoder OQutputs .. . . . . ... ..o 3-24
Vector Generation logic Outputs . . . .. ... ...

Terminal Requirements.

... ...

. . .. ...... ... .. ...

...

. ... . ..... 3-24

... ...

. ... 4-2

Native Register Boot Select Codes . ... .. ..........
... ........... 4-3
ROM Status Codes . . . ... ... .. i 4-4
Manual Restart Addresses . . . . ... ... .. ...
4-6
Console Mode Commands . . ... ...... .. ... .. . ... 4-7
BOOT Command Interpretation . . . .. .............
... .......... 4-10
Error Override commands . . . . ... ... ... ... .. .. .

Q22-bus Boot Devices

Boot Device Errors . . . .. . . . . .
4-10

4-11

4-17

. .. ... ... ... .. e 4-18
. e 4-20

Disk and Tape Boot List . . ... ........ ... ... ... ... .. .... 4-21
DPV, DUV, DLV, TU58 and RK05 Autoboot List . . . ............. L4221

Preface

INTRODUCTION

The KDJ11-D/S CPU module is a low-cost quad-height processor module for use in extended
1.51-11 bus (Q22-bus) systems. It is based on the DCJ11 microprocessor, and executes the
PDP11/73 instruction set.

PURPOSE

This user’s guide provides first-time and sophisticated users of the KDJ11-D/S CPU Module
with the information to install, test, operate, and troubleshoot the module.
INTENDED AUDIENCE

This user’s guide is written for end users, COEMs, TOEMs, and Field Service.
REViSION NOTES

This manual has been revised to reflect the re-engineered KDJ11-DA. The re-engineered
version is refered to in this manual as the KDJ11-D/S. Where differences occur, both the
new and the previous version will be described.

GUIDE CONTENT

This user’s guide contains four chapters and an index. The following list describes the primary
content of each chapter.
1.

Architecture

Describes KDJ11-D/S features, registers, interrupt scheme, and memory management.
2.

Installation

Describes module configuration, options, power-up/down sequences, specifications, backplane pin-out, and installation.
3.

Functional Description

Briefly describes the functional operation of the major module components.

Boot ROMs and Diagnostics

Describes boot ROM routines and micro-diagnostics.
RELATED INFORMATION
This guide does not replicate generic PDP-11 information often found in other MicroPDP-11

CPU User’s Guides. Such related information and its source documents are listed below.
®

PDP-11 Architecture Handbook, EB-23657-18

—

Addressing modes

—

Instruction set.

—

Floating-point instructions set.

—

Programming techniques.

—

Extended LSI-11 bus description.

PDP-11 UNIBUS Processor Handbook, EB-26077-41

—

Console ODT (On-line Debugging Technique) command descriptions and examples.

ASSOCIATED DOCUMENTS
Order
EB-26077-41

PDP-11 UNIBUS Processor Handbook

EB-23657-18

PDP-11 Architecture Handbook

EK-DCJ11-UG

DCJ11 Microprocessor User's Guide

CONVENTIONS
The notational conventions used in this guide are described in the following table.

Convention

Meaning

NOTE

Contains general information.

CAUTION

Contains information to prevent damage to equipment.

<mm:nn>

Read as ““mm through nn.”” This use of angle brackets and the colon indicates a
bit field, or a set of lines or signals. For example, A<17:00> is the mnemonic for
address lines ""A17 through A00.”

Addresses

Unless otherwise noted, all addresses in this guide are in octal notation.

k, M

Abbreviations for kilo, Mega. When used with bytes and words, k and M represent
the actual decimal value of quantities. For example:

8 kbytes

8192 bytes

not

8000 bytes

32 kwords

32768 words

not

32000 words

512 kbytes

524288 bytes

not

512000 bytes

4 Mbytes
<CTRL/n> or 'n

Control sequence.
same time.

Abbreviations

= 4194304 bytes

not 4000000 bytes

Press the <CTRL> key and the appropriate typing key at the

Abbreviations are in accordance with DEC STD 015, 3 February 1983.

X111

Chapter

ARCHITECTURE
This chapter describes features of the KDJ11-D/S module, its registers, interrupt
memory management.

scheme, and

The range of three modules has been expanded to four modules, as shown in
the following
table.

Table 1-1;:

KDJ11 versions

Old version
KDJ11-DA

Q-bus 0.5 Mb 15 MHz

New version

Comments

KDJ11-DA

Re-engineered

KDJ11-DB

Q-bus 1.5 Mb 15 MHz

KDJ11-SA

BA200 0.5Mb 15 MHz

Replaced by KDJ11-SC

KDJ11-SB

BA200 0.5Mb 18 MHz

Replaced by KDJ11-SD
KDJ11-8C

BA200 1.5 Mb 15 MHz

KDJ11-SD

BA200 1.5 Mb 18 MHz

The are three main differences between the previous versions and the new
versions of the
boards. All the PALs and most of the discrete logic has been replaced
by two gate arrays.
This has made room on board for an optional increase in on-board memory
from 0.5 Mb to
1.5 Mb. As a result of the change in physical layout, the position of the
jumpers has been
changed, although the previous numbers have been retained. Details of
the jumpers will be
covered in Chapter 2

ARCHITECTURE

1-1

1.1 FEATURES
The KDJ11-D/S CPU module (part number M7554) is a low-cost quad-height single board
computer for use in extended LSI-11 bus (Q22-bus) systems. It is based on the DCJ11
microprocessor chip, and executes the PDP11/73 instruction set. The module includes the
CPU, memory management, local memory, and 1/O.

The CPU executes the full PDP11 integer instruction set. Floating point instructions are
standard on the KDJ11-D/S; however, the FPA (Floating-point Accelerator) is not an option.
Full 22-bit memory management is provided for both instruction and data references in three

protection modes: kernel, supervisor, and user. (These are also called operating modes.)

The KDJ11-D/S can address up to 4 Mbytes of memory. The module includes 0.5 Mbytes or
1.5 Mbytes of local memory, as shown below:
e

KDJ11-DA — 0.5 Mbytes
KDJ11-DB — 1.5 Mbytes

KDJ11-SA — 0.5 Mbytes
KDJ11-SC — 1.5 Mbytes

KDJ11-SD — 1.5 Mbytes (BA200 only)

An additional 3.5 Mbytes/2.5 Mbytes of memory can be addressed over the Q22-bus interface.
Local (on-board) memory is 0.5 Mbytes/1.5 Mbytes of dynamic RAM with no battery back-up.
Its starting address is fixed at 0.

All Q22-bus transaction types are supported. The KDJ11-D/S is the Q22-bus arbiter, and
services only level 4 interrupts. Interrupt requests on levels 5, 6, or 7 are serviced at level 4
< 5:7> are terminated and not connected to on-board logic).
(BIRQ

The CPU supports power-up mode 2, bootstrap on power-up. The bootstrap starting address
is fixed at 17773000 in the I/O page. Bootstrap and self-test routines are included in the
on-board ROM. The ROMs can be either 32 kbytes (two 16-kbyte ROMs) or 64 kbytes (two
32-kbyte ROMs). Bootstrap options are selectable with on-board jumpers or through a remote
switch. Seven indicator signal lines are provided to drive remote indicators for diagnostic
purposes.

The HALT/trap option is supported with an on-board jumper. With the jumper removed, the
CPU will trap through location 4 when a HALT instruction is executed in kernel mode. If the

jumper is installed, the CPU will enter console ODT mode.

The module includes two DLARTs (DL-style UARTs (Universal Asynchronous Receiver/
Transmitter)) for console and printer SLUs (Serial Line Units). DLART baud rate is selectable
with on-board jumpers or remote switch. Halt on BREAK is jumper selectable in the console
DLART.

1.1.1 Features Not Supported

The KDJ11-D/S CPU module does not have a cache memory. The FPA (Floating-point
Accelerator) is not an option. Power-up modes 0 (power-fail), 1 (ODT), and 3 (user-defined
starting address) are not supported.

1-2

ARCHITECTURE

1.1.2 Registers
User-visible registers are shown in Figure 1-1. They are classified as: System Control, General
Purpose, Memory System, Memory Management, and Floating Point registers. The addresses
for the memory-addressable registers are listed in Table 1-2. These are user-visible registers

which can be accessed with a 22-bit physical address. The other user-visible registers are
referenced with the instruction set. Table 1-2 is an address map and lists the addresses and

vectors for registers and other system devices.

Figure 1-1:

Registers

GENERAL PURPOSE

SYSTEM CONTROL

PSW

PIRQ

CPU ERROR

LTC

MAINTENANCE]| *

KSP

FLOATING POINT
FPS

FEC

FEA

ACCUMULATORS

NATIVE

DLART REGS

SSP
USP

MEMORY SYSTEM

MEM ERROR

MEMORY MANAGEMENT

MMRO

KERNEL

MMR1

MMR2

MMR3

SUPERVISOR

PAR PDR

PAR

0-7 0-7 |

|0-7 0-7

PDR

USER

PAR PDR

PAR

0-7 0-7 |

|0-7 0-7

PDR

PAR

D
i

PDR|

0-7 0-7 |

|PAR PDR

|0-7 ,0-7

* EXTERNAL TO THE DCJ11
RE3547

ARCHITECTURE

1-3

Table 1-2:

Address Map

Address

Vector

FPP (Floating Point Processor)

244

PSW (Processor Status Word)

17777776

PIRQ (Program Interrupt Request)

17777772

240

17777766

Maintenance

17777750

Memory Error

17772100

PAR 7

17777676

250

PAR 6
PAR S5
PAR 4
PAR 3
PAR 2
PAR 1
PAR O

17777674
17777672
17777670
17777666
17777664
17777662
17777660

250
250
250
250
250
250
250

PAR 7
PAR 6
PAR 5
PAR 4
PAR 3

17777656
17777654
17777652
17777650
17777646

PAR 2
PAR 1
PAR O

17777644
17777642
17777640

250
250
250
250
250
250
250
250

User Data

PDR 7

17777636

250

User Instruction

PDR 7

17777616

250

DR 3
PDR 2
PDR 1
PDR 0

17777606
17777604
17777602
17777600

250
250
250
250

MMR2 (MMU Status 2)

17777576

250

MMR1 (MMLU Status 1)

17777574

MMRO (MMU Status 0)

17777572

250

CPU Error

MMU (Memory Management Unit)

User Data

User Instruction

SLU 0 (Console Serial Line Unit 0)

1-4

ARCHITECTURE

PDR 6
PDR 5
PDR 4
PDR 3
PR 2
PDR 1
PDR O
PDR 6
PDR 5
PDR 4

17777634
17777632
17777630
17777626
17777624
17777622
17777620
17777614
17777612
17777610

250
250
250
250
250
250
250
250
250
250

Table 1-2 (Cont.):

Address Map

Address

Vector

Transmitter Buffer

17777566

Transmitter CSR
Receiver Buffer

Receiver CSR

17777564
17777562

64
60

17777560

LTC (line time clock)

17777546

100

KDJ11-D/S Native Register

17777520

Transmitter Buffer
Transmitter CSR

17776506
17776504

304

Receiver Buffer
Receiver CSR

17776502

300

17776500

300

Bootstrap (512 bytes)

17773776

SLU 1 (General Purpose Serial Line Unit 1)

304

through
17773000

MMU (Memory Management Unit)

MMR3 (MMU Status 3)
Kernel Data

Kernel Instruction

Kernel Data

17772516

250

PAR 7

17772376

250

PAR 6

17772374

250

PAR 5

17772372

250

PAR 4

17772370

PAR 3

250

17772366

250

PAR 2
PAR 1

17772364

250

17772362

250

PAR 0

17772360

250

PAR 7
PAR 6

17772356

250

17772354

250

PAR 5

17772352

PAR 4

250

17772350

250
250

PAR 3

17772346

PAR 2

17772344

250

PAR 1

17772342

PAR O

250

17772340

250
250

PDR 7

17772336

PDR 6

17772334

250

PDR 5

17772332

PDR 4

250

17772330

PDR 3

250

17772326

250

PDR 2

17772324

250

PDR 1

17772322

250

PDR 0

17772320

250

ARCHITECTURE

1-5

Table 1-2 (Cont.):

Address Map

Address

17772316

250

PDR 6
PDR 5
PDR 4
’DR 3
PDR 2
PDR 1
PDR O

17772314
17772312
17772310
17772306
17772304
17772302
17772300

250
250
250
250
250
250
250

Supervisor Data

PAR 7

17772276

250

Supervisor Instruction

PAR 7

17772256

Supervisor Data

Supervisor Instruction

1-6

PDR 7

Veclor

ARCHITECTURE

PAR 6
PAR 5
PAR 4
PAR 3
PAR 2
PAR 1
PAR O
PAR 6
PAR 5
PAR 4
PAR 3
PAR 2
PAR 1
PAR O

17772274
17772272
17772270
17772266
17772264
17772262
17772260
17772254
17772252
17772250
17772246
17772244
17772242
17772240

250
250
250
250
250
250
250

250

250
250
250
250
250
250
250

250

PDR 7

17772236

PDR 6
PDR 5
PDR 4
PDR 3
PDR 2
PDR 1
PDR O

17772234
17772232
17772230
17772226
17772224
17772222
17772220

250
250
250
250
250
250
250

PDR 7

17772216

250

PDR O

17772200

250

PDR 6
PDR 5
PDR 4
PDR 3
PDR 2
PDR 1

17772214
17772212
17772210
17772206
17772204
17772202

250
250
250
250
250
250

Table 1-2 (Cont.):

Address Map

Address

Self Test ROM (120 kbytes)

17400000

Vector

through
17757777

User RAM (0.5 Mbytes)

00000000

through
01777777
User RAM (1.5 Mbytes)

00000000
through

05777777

1.2 SYSTEM CONTROL REGISTERS
These registers, shown in Figure 1-1, control system functions.

1.2.1

Processor Status Word

Address: 17777776
The PSW (Processor Status Word) Register contains:

Current and previous operating mode

General purpose register group in use
Current priority level
Condition code status

Trace/trap bit for debugging
The PSW is initialized at power-up and cleared with a console start.

Table 1-3.

See Figure 1-2 and

ARCHITECTURE

1-7

Figure 1-2:

1§

PSW (Processor Status Word) Register

]

CURRENT
MODE

o | o

05
T

_J T

]

PRIORITY
LEVEL

GENERAL PURPOSE
REGISTER GROUP

PRIORITY

PREVIOUS
MODE

Table 1-3:

06
T

N|]Z|V]ecC
[N

TRACEBIT

CONDITION
CODES

SUSPENDED
INFORMATION

MR-11042

PSW (Processor Status Word) Bits

Bit

Access

Description

<15:14>

R/W

Current Mode—Indicate the current operating mode as follows:
Bit

Mode

15 14

Kernel
Supervisor

llegal

<13:12>

RIW

User

Previous Mode—Indicate the previous operating mode, and are coded the same
as bits <15:14>.

<11>

R/W

<10:09>

<08>

<07:05>

1-8

not used
Suspended Information—reserved

R/W

ARCHITECTURE

Priority Level—Indicate the processor’s current priority level, as follows:

Table 1-3 (Cont.):

PSW (Processor Status Word) Bits

Bit

Description

Access

Bit

Level

07 06 05
1

<04>

R/W

110

1
0 1
100

5
4

0 11
010
0 01
0 00

3
2
1
0

Trap—Inactive when cleared. When set, the processor traps to location
14 at
the end of the current instruction. Used for debugging and setting breakpoints,

this bit cannot be explicitly set by writing the PSW: it can be changed only with
the RT/RTT instructions.

<03>

R/W

Condition code N—Set when the result of the previous operation is negative.

<02>

R/W

Condition code Z—Set when the result of the previous operation is zero.

<01>

R/W

Condition code V—Set when the previous operation resulted in an overflow.

<00>

R/W

Condition code C—Set when the previous operation caused a carry-out.

1.2.2 Program Interrupt Request
Address: 17777772

The PIRQ (Program Interrupt Request) Register implements software

interrupts. Setting one
of bits <15:09> corresponds to a request on one of the priority levels 7:1.
See Figure 1-3
and Table 1-4.
Hardware sets bits <07:05> and <03:01> to the encoded value of
the
highest priority request pending. When the interrupt is acknowled
ged, the processor vectors
to location 240 for the service routine. (The service routine must clear the
interrupt request.)
The PIRQ Register is cleared by power-up, console start, or the
RESET instruction.

Figure 1-3:

PIRQ (Program Interrupt Request) Register

PIR |

PIR

PIR { PIR

ENCODED

V‘ALUE ‘

ENCODED

VALUE

05
T

01
T

R-5013

ARCHITECTURE

1-9

Table 1-4:

PIRQ (Program Interrupt Request) Bits
Access

Description

<15>

RI/IW

Priority Level 7—When set, requests an interrupt on level 7.

<14>

R/W

Priority Level 6—When set, requests an interrupt on level 6.

<13>

RIW

Priority Level 5—When set, requests an interrupt on level 5.

<12>

R/IW

Priority Level 4—When set, requests an interrupt on level 4.

<11>

R/IW

Priority Level 4—When set, requests an interrupt on level 3.

<10>

R/W

Priority Level 2—When set, requests an interrupt on level 2.

<09>

R/W

Priority Level 1—When set, requests an interrupt on level 1.

Bit

<08>

<07:05>

not used

Encoded Value—Indicate the highest priority level set in bits <15:09>.

<04>

<03:01>

not used

Encoded Value—Same as bits <07:05>.

<00>

not used

1.2.3 CPU Error Register
Address: 17777766

The CPU Error Register indicates the source of any trap or error condition that caused a trap
through location 4. See Figure 1-4 and Table 1-5. The register is cleared by any write
reference, power-up, or console start. It is not changed by the RESET instruction.
Figure 1-4:

CPU Error Register

ILLEGAL HALT

ADDRESS ERROR

NON-EXISTENT MEMORY
I/0 BUS TIMEOUT
YELLOW STACK VIOLATION

RED STACK VIOLATION
MR-9326

1-10

ARCHITECTURE

Table 1-5:

CPU Error Register Bits

Bit

Access

Description

<15:08 >

not used

<07>

lllegal HALT—Set when an attempt is made to execute a HALT instruction in
user or supervisor mode. (See Maintenance Register<03>, Table 1-6.)

<06>

Address Error—Set when an attempt is made to either word-access an odd byteaddress or to fetch an instruction from an internal register.

<05>

Non-existent Memory—=Set when a reference to main memory times-out.

<04>

/O Bus Time-out—Set when a reference to the 1 /O page times-out.

<03 >

Yellow Stack Violation—Set on a yellow-zone stack-overflow trap (kernel mode
stack reference less than 400g).

<02>

Red Stack Violation—Set on a red stack-trap (a kernel stack-push abort during
an interrupt, abort, or stack sequence).

<01:00>

not used

1.2.4 Maintenance Register
Address: 17777750

The Maintenance Register allows software to determine which power-up options are selected
and if an FPA (floating point accelerator) is installed. See Figure 1-5 and Table 1-6.

Figure 1-5:

Maintenance Register

|
0

NOT USED
[

I
0

FPA
0

MODULE TYPIE
I

]

HLT

|OPT|

PUM
1

]

POK

0
RE3548

ARCHITECTURE

1-11

Table 1-6:

Maintenance Register Bits

Bit

Access

Description

<15:09>

not used—always read zero

<08>

FPA Here—Always reads zero. The FPA is not a KDJ11-D/S option.

<07:04>

Module Type Number—Encoded value indicating the module type number. The
KDJ11-D/S is module type four (0100;).

<03>

Halt Option—Indicates how a HALT instruction will execute in kernel mode. It
jumper W1 is not installed the bit is set; when a HALT is executed, the KDJ11DIS traps through location 4, and sets CPU Error Register<07> (Table 1-5).
If jumper W1 is installed, the bit is cleared; when a HALT is executed, the
KDJ11-D/S enters console ODT mode.

<02:01>

<00>

Power-up Mode Option—Indicates the selected power-up mode option. The
KDJ11-D/S supports only power-up mode 2 (102), bootstrap at starting address
17773000.
Power OK—When set, indicates that Q22-bus signal BPOK is asserted H (system
power is within tolerance and stable).

1.2.5 Line Time Clock Register
Address: 17777546

The LTC (Line Time Clock) Register controls recognition of the Q22-bus signal, BEVNT. See
Figure 1-6 and Table 1-7.

Figure 1-6:

LTC (Line Time Clock) Register (BEVNT)

08
|

NOT USED
0 inOlOIO

EIF | EIE

00
|

{

NOT USED

{

01010101010
REIBL

1-12

ARCHITECTLUIRE

Table 1-7:

LTC (Line Time Clock) Register Bits

Bit

Access

Description

<15:08>

not used—always read zero

<07>

Event Interrupt Flag—Indicates the state of the Q22-bus BEVNT signal when bit
<06> is not set. If set when <06> is set, causes an interrupt through vector
100, at priority level 6. Must be deasserted and asserted (BEVNT asserted and
deasserted) to cause another interrupt.

<06>

R/W

Livent Interrupt Enable—When set, enables level 6 interrupts through vector

100. Cleared by power-up, reboot, or the RESET instruction.
<05:00>

not used—always read zero

1.2.6 Native Register
Address: 17777520
The Native Register (Figure 1-7) provides the test and boot functions described in Table 1-8.
Figure 1-7:

Native Register

13
T

MODULE
lFNCTI

BOOT SWITCH
4

ST
O

| ENB|

00
T

]

INDICATOR BITS !
4,

I
1

0
RE3550

Table 1-8:

Native Register Bits

Bit

Access

Description

<15:13>

15 =1
14 =90

0.5 Mbyte memory (on board)

14 =1

1.5 Mbyte memory (on board).

Bit 14 reflects the setting of jumper W25. The jumper is installed when there is

0.5 Mbytes of memory, and is removed when there is 1.5 Mbytes of memory.

0
I

Normal
For special applications.

Bit 13 reflects the setting of jumper W4.
Bits <15:13> are always zero on early versions.

ARCHITECTURE

1-13

Table 1-8 (Cont.):

Native Register Bits

Bit

Access

Description

<12:08>

Boot Switch <4:0>—Binary coded value read by firmware to direct self-test
and bootstrap program execution. Up to 32 routines can be selected, either with
on-board jumpers W22, W2, W3, W5, and W8 (bits <12:08>, respectively), or
with W22 (bit <12>) and a remote 16-position switch (bits <11:08>). See
Table 2-2.

<07>

R/IW

Self-test Enable—When set, enables the Self-test ROM; that is, physical addresses 17400000 through 17757777 access Self-test ROM space. When cleared,
disables the Self-test ROM; that is, physical addresses 17400000 through 17757777
access Q22-bus memory space. Cleared by power-up or reboot; not affected by
the RESET instruction.

<06:00>

R/W

Indicator <6:0>—Indicate the state of lines IND<6:0>. Cleared on power-up
or reboot; not affected by the RESET instruction. The lines are connected to J1,
to drive remote LEDs. The Self-test program reports its progress on IND<3:0>.
See Table 2-3.

1.2.7 DLART Registers
Each DLART contains the following registers.
RCSR (Receiver Control/Status Register)
RBUF (Receiver Data Buffer)
XCSR (Transmitter Control/Status Register)
XBUF (Transmitter Data Buffer)

1.2.7.1 Receiver Control/Status Register
Address: 17777560 (SLU 0), 17776500 (SLU 1)
Figure 1-8:

Receiver Control/Status Register (RCSR)

12
I

]

NOT USED'
0

08
I

NOT USED
L

RD | RIE

'
|

''NOT'USED'
l

!
I

0
RE3GH1

Table 1-9:

Receiver Control/Status Register (RCSR) Bits

Bit

Access

Description

<15:12>

not used—always read 0

<11>

Receiver Active—When set, indicates that a start bit has been detected. Cleared
when a stop bit is detected, or on power-up or reboot.

1-14

ARCHITECTURE

Table 1-9 (Cont.):

Receiver Control/Status Register (RCSR) Bits

Bit

Access

Description

<10:08>

not used—always read 0

<07>

Receiver Done—When set, indicates that the serial interface has received
a
character; and requests an interrupt if <06> is set. Cleared by reading
the
receiver data buffer, or on power-up or reboot.

<06>

R/W

Receiver Interrupt Enable—When set, receiver interrupts are enabled
(see
<07>). When cleared, receiver interrupts are disabled. Cleared by power-up,

reboot, or the RESET instruction.

<05:00>

not used—always read 0

1.2.7.2 Receiver Data Buffer

Address: 17777562 (SLU 0), 17776502 (SLU 1)
Figure 1-9:

Receiver Data Buffer (RBUF)

OE | FE

08
T

NU | RB

NOT USED

]

RECEIVER DATA BUFFER
|

l
RE3552

Table 1-10:
Bit

Receiver Data Buffer (RBUF) Bits

Access

<15>

Description

Error—Set when <14> or <13> is set.

cleared.

Cleared when the error condition is

<14>

Overrun Error—When set, indicates that a new character was received
before
an old character was read. Will be set if Receiver Done (RCSR <07 >)
was not
cleared when a character was received. Cleared when a character is received
and RCSR<07> = 0 (cleared), or on power-up or reboot.

<13>

Framing Error—When set, indicates that a received character did not
have a
valid stop bit. Cleared when a character with a valid stop bit is received, or on

power-up or reboot.

<12>

not used—always read 0

<11>

Received Break—When set, indicates that the received signal has
gone from a
MARK to a SPACE, and stayed in the SPACE condition for 11 bit-times.
Cleared
when the received signal returns to a MARK, or on power-up or reboot.

<10:08>

not used—always read 0

ARCHITECTURE

1-15

Table 1-10 (Cont.):
Bit

Access

<07:00>

Receiver Data Buffer (RBUF) Bits
Description

Receiver Data Buffer—Set to the value of the most recently received character.

Cleared by power-up or reboot.

1.2.7.3 Transmitter Control/Status Register
Address: 17777564 (SLU 0), 17776504 (SLU 1)

Figure 1-10:

Transmitter Control/Status Register (XCSR)

0,0

"' NOT USED'
0

TR | TIE|

BAUD RATE

1,0

M | BRE|

AE3563

Table 1-11:

Transmitter Control/Status Register (XCSR) Bits

Bit

Access

Description

<15:08>

not used—always read 0

<07>

Transmitter Ready—When set, indicates that the Transmitter Buffer is empty
and can accept a new character for transmission; and requests an interrupt if
<06> isset. Set on power-up or reboot. Cleared by writing into the Transmitter
Buffer.

<06>

R/W

Transmitter Interrupt Enable—Sel to enable transmitter interrupts (see <07>).
Cleared to disable transmitter interrupts. Cleared by power-up, reboot, or the
RESET instruction.

<05:03>

RIW

Baud Rate Select—In the KDJ11-D/S, these bits are ALWAYS CLEARED (see
<01>).

(In other applications, if <01> is set, these bits determine the transmit/receive
baud rate under program control, and are cleared when <01> is cleared, on
power-up, or on reboot.)

<02>

RIW

Maintenance—When set, the external receiver input is disconnected and the
transmitter output is connected to the receiver input. Cleared by power-up,
reboot, or the RESET instruction.

1-16

ARCHITECTURE

Table 1-11 (Cont.):

Tran_smitter Control/Status Register (XCSR) Bits

Bit

Description

Access

<01>

R/W

Baud Rate Enable—In the KDJ11-D/S, this bit is ALWAYS CLEARED. The baud

rate is selected by remote switch or on-board jumpers W4, W6, and W9 for
DLARTO and W10, W7, and W12 for DLART1 (baud rate select BRS2, BRS1, and

BRSO, respectively).

(In other applications, if this bit is set, <05:03> can select the baud rate under
program control.

When <01> is cleared, the baud rate is selected by remote

switch or on-board jumpers. Cleared on power-up or reboot.)

<00>

R/W

Transmit Break—When set, causes the output signal to go to a SPACE condition.
A SPACE longer than a character-time causes a framing error ond is interpreted

as a break.
Transmit Ready and Transmit Interrupl continue to operate,
allowing software to time the break. Cleared by power-up, reboot, or the RESET
instruction.

1.2.7.4 Transmitter Data Buffer

Address: 17777566 (SLU 0), 17776506 (SLLL 1)
Figure 1-11:

Transmitter Data Buffer (XBUF)

08
T

NOT USED

00
T

TRANSMIiTTERIDATA BUFFER

OIIO‘OHOIOIOIOIOMSBI‘I

LSB
RE3554

Table 1-12:

Transmitter Data Buffer (XBUF) Bits

Bit

Access

Description

<15:08>

not used—always read 0

<(07:00>

R/W

Transmitter

Data

Buffer—When

byte

written

into

this

buffer,

the

Transmitter Ready bit (XCSR<07>) is cleared. This byte is copied into the
transmitter serial output register when it is empty and XCSR <07 > is cleared.

Copying the byle into the serial output register sets
cleared on power-up or reboot.

XCSR <07>. These bits are

1.3 GENERAL PURPOSE REGISTERS
As shown in Figure 1-1 and listed in Table 1-13, there are 16 general purpose registers.
Only eight are visible to the user at any given time. All these registers can be used for

accumulators, deferred address, index references, autoincrement, autodecrement, and stack
pointers; however, registers 6 and 7 normally have the specific functions described below.

ARCHITECTURE

1-17

Table 1-13:

General Purpose Registers
Mnemonics

RO’

R1’

R2’

R3’

R4’

R5’

KSpP

sSSP

USP

PSW<15:11> (Table 1-3) determine which eight registers are currently selected. Six of the
registers are selected by PSW< BITMAP >(11) as follows:
Bit<11>

RO through R5

RO" through RS’

1.3.1 Stack Pointer

Three stack pointers are available, one for each

protection mode; however, only one is visible to the user at any given time. For most
instructions, PSW<15:14> determine the active stack pointer. In MIPL, MIPD, MTPI, and
> select R6 as the destination, PSW<13:12> select the
MTPD instructions, when PSW<15:14
stack pointer. See Table 1-14.

Table 1-14:

Stack Pointer Selection

PSW <15:14> or

PSW <13:12>

Selected Stack Pointer (R6)

KSP (Kernel Stack Pointer)

SSP (Supervisor Stack Pointer)

illegal—USP selected

USP (User Stack Pointer)

ARCHITECTURE

1.3.2 Program Counter
Register R7 is the PC (Program Counter), and controls the instruction sequence. It contains the
16-bit address of the next word to be processed in the instruction stream. The PC is directly
accessible by single and double operand instructions. Although the PC is a general purpose
register, it is not normally used as an accumulator.

1.4 INTERRUPTS
The trap, hardware, and software interrupts are listed in Tables 1-15 and 1-16. The priority

scheme is shown in Table 1-17.
The Q22-bus provides four interrupt request lines (BIRQ <7:4 >) to allow hardware to interrupt
the processor; however, the KDDJ11-D/S interprets only priority level 4 (BIRQ4) hardware
interrupts. BIRQ<5:7
> are not used but are terminated on the module.

The PIRQ Register provides seven levels of software interrupt requests.

Vectored traps are

provided to flag error conditions.
Table 1-15:

Asynchronous Interrupts
Vector

Priority

Address?

Level®

Interrupt

IE!

Red stack trap

250

Parity error (PARITY, ABORT)

114

Trace trap

[

Power fail (PWRF)

Floating point exception (FPE)

244

CPU Error Register<02>
Address error

CPU Error Register<06>
Memory management violation

MMRO<15:13>
Timeout/non-existent memory

CPU Error Register <05:04 >

PSW<04>
Yellow stack trap

CPU Error Register<03>

'l = internal, E = external

INU = not used, UD = user-defined
3NM = non-maskable interrupts, unaffected by priority specified in PSW <07:05 > .

ARCHITECTURE

1-19

Table 1-15 (Cont.):

Asynchronous Interrupts
Vector

Priority

Address®

Level’

Interrupt

I/E'

PIR 7 (PIRQ<15>)
IRQ 7 (BIRQ7)
PIR 6 (PIRQ<14>)
BEVNT

I
E
|
E

240
NU
240
100

7
4
6
4
4

IRQ 6 (BIRQ®6)

PIR 5 (PIRQ<13>)

240

IRQ 5 (BIRQ5)

PIR 4 (PIRQ<12>)
IRQ 4 (BIRQ4)

|
E

240
uD

4
4

PIR 3 (MRQ<11>)
PIR 2 (PIRQ
< 10>)

|
|

240
240

3
2

PIR 1 (PIRQ<09>)

240

Halt line (BREAK)*

none

1 = internal, E = external
INU = not used, UD = user-defined

*NM = non-maskable interrupts, unaffected by priority specified in PSW <07:05>.
*Places system in Console ODT mode if jumper W11 is not installed.
enables/disables BREAK.)

Table 1-16:

Synchronous Interrupts

Interrupt

Vector
Address

EP Instruction Exception

244

TRAP Instruction

EMT Instruction

BPT Instruction

CSM Instruction

HALT Instruction

WAIT Instruction’

r—

)

Fomd

[ ]

‘Does not trap, but frees the bus when waiting for an external interrupt.

ARCHITECTLIRE

(W11 has no affect on Halt line; it only

Interrupt Priorities
Level

Highest

Power Fail
BEVNT

Device

none

SLU 0 Receiver

&)B

Priority

Table 1-17:

SLU 0 Transmitter

SLU 1 Receiver

Lowest

1.4.1

SLU 1 Transmitter
Q22-bus Devices

Halt Line

The Halt line (BHALT) usually has the lowest interrupt priority, except during vector reads
when it has the highest priority.
This allows the user to break out of potential infinite
loops. An infinite loop could occur if a vector has not been properly mapped during memory
management operations.

The Halt line is driven by the BREAK signal from the Console SLU (DLARTO) if jumper W11
is not installed. If W11 is installed, BREAK is disabled (tied low).

When enabled and asserted, the Halt line forces the KDJ11-D/S into Console ODT mode.

1.4.2 HALT Instruction
HALT instruction execution behavior depends on the current protection mode and the Halt
Option jumper, W1.

The HALT instruction is not legal in supervisor and user modes. If executed in either of these
modes, the processor traps to location 4, and sets CPU Error Register<07>.

When a HALT instruction is executed in kernel mode:
*

If Halt Option jumper W1 is not installed, the processor sets up an emergency stack at
location 4, traps through location 4, and sets CPU Error Register
<07 >.

If jumper W1 is installed, the processor halts and enters console ODT mode.

ARCHITECTURE

1-21

1.5 MEMORY MANAGEMENT
The MMU (Memory Management Unit) provides access to all of physical memory with
complete memory management and protection in kernel, supervisor, and user modes. It
provides relocation and memory protection for multi-user, multi-programming systems. The
basic characteristics of the MMU include:
*

16 kernel mode memory pages (8 data, 8 instruction)

16 supervisor mode memory pages (8 data, 8 instruction)

16 user mode memory pages (8 data, 8 instruction)

page length from 64 to 8192 bytes

full protection and relocation for every page

transparent operation

3 memory access control modes

memory access up to 4 Mbytes

The three protection modes permit layered software protection.
Memory management
separately manages each mode, allowing each mode to access different sections of memory;
and each section can have different access protection. The protection scheme allows a higher
mode to enter a lower mode, but a lower mode cannot enter a higher mode. Kernel mode has
full privileges and can execute all instructions. The two lower modes, supervisor and user,
cannot execute certain instructions.

1.5.1

Physical Address Space

The 4-Mbyte physical address space is allocated to several memory types and/or functions, as
shown in Figure 1-12. All memory, except Q22-bus memory, is on-board. Q22-bus memory
is optional.

1-22

ARCHITECTURE

Figure 1-12:

Physical Address Space

0.5 MBYTE

17777777

I/0 PAGE

17760000

1.5 MBYTE

SELF-TESTROM

Q22-BUS MEMORY

17777777

¥ | @

17757777

)

17400000

17760000

\ 2

o g

17377777

2 |
¥

)
|

17757777

1/0 PAGE

SELF-TESTROM

Q22-BUS MEMORY

17400000

17377777

> s
=

_Q22-BUS MEMORY
"

02000000

__Q22-BUS MEMORY"

]

01777777

[WE]

06000000

)

05777777

] .

[

— ON-BOARD RAM

[

as]

ON-BOARD RAM ~

00000000

00000000
~

RE3555

1.5.1.1

1/0 Page

The 1/0 page is the top 4 kwords (8 kbytes) of memory, and always at physical address

locations 17760000 through 17777777 (Figure 1-13). Immediately below the /O page is 22bus memory space and Self-test ROM space. Q22-bus memory is accessed if Self-test Enable
(Native Register<(07>) is not set, and Self-test ROM space is accessed if Self-test Enable is
set.

ARCHITECTURE

1-23

1.5.1.2 Self-test ROM

Self-test ROM space extends from 17400000 through 17757777. The addresses are “‘wrappedaround’’ on 32-kbyte boundaries if 16-kbyte ROMs are installed, and on 64-kbyte boundaries
if 32-kbyte ROMs are installed. (During manufacture, either 16-kbyte ROMs and R16 are
installed and W13 is removed, or 32-kbyte ROMs and W13 are installed and R16 is removed.)

Because the 8-kbyte I/O page resides at the top of Self-test ROM space, the starting address

must be 17400000, 17500000, or 17600000 to access all the 16-kbyte ROM locations; or
17400000 to access all the 32-kbyte ROM locations.

Figure 1-13:

Self-test ROM Space

17777777
/0 PAGE

17760000

I/0 PAGE

17757777

32 KBYTE ¢

SELF-TEST ROM
17700000

17677777

32 KBYTE ¢

SELF-TEST ROM

17600000
17577777

32 KBYTE {

Q22-BUS
ACCESS

SELF-TEST ROM

17500000
17477777

32 KBYTE {

SELF-TEST ROM

17400000

SELF-TEST ENABLE = 1

SELF-TEST ENABLE = 0
RE3556

1.5.1.3 Bootstrap

The bootstrap program resides in a 512-byte section of Self-test ROM. Its location is 17673000

to 17673777 when 16-kbyte ROMs are installed, and 17573000 to 17573777 when 32-kbyte
ROMs are installed (Figure 1-14). It is also accessible from locations 17773000 to 17773777
in the 1/0 page. Although the bootstrap program can be read from two locations, it executes
only in the I/O page (that is, from starting address 17773000).

Figure 1-14:

Bootstrap Space

16 KBYTE ROMS

32 KBYTE ROMS

17777777

17774000

/0
PAGE

17773777

BOOTSTRAP

17773000
17772777

17760000
17757777
A

SELF-

TEST

BOOTSTRAP

ROM

17674000

17574000

17673777

17573777

17673000

17573000

17672777

17572777

BOOTSTRAP

de‘
2%

17400000
RE35567

1.5.2 Virtual Memory Mapping
To access memory, the processor can perform 16-, 18-, or 22-bit address mapping.

ARCHITECTURE

1-25

1.5.2.1

16-bit Mapping

In the lowest 28-kwords, the virtual and physical address are the same (Figure 1-15). The /O
page occupies the upper 4-kword block.
Figure 1-15:

16-bit Mapping

/ 17777777
4K
17760000

177777

160000

o
00157777

VIRTUAL

(16 BITS)

000000
INCOMING

ADDRESS

28 K
00000000
PHYSICAL ADDRESS

SPACE (22 BITS)

RE3558

1.5.2.2 18-bit Mapping
Kernel, supervisor, and user modes are each allocated 32-kwords, mapped into physical
address space. The 128-kword physical address space, including the 4-kword I/O page, is
shown in Figure 1-16.

1-26

ARCHITECTURE

Figure 1-16:

18-bit Mapping

17777777
4 K
17760000

— loo757777
177777

VIRTUAL

(16 BITS)

000000

INCOMING

ADDRESS

~ MEM

MGMT

124 K

00000000

PHYSICAL ADDRESS

SPACE (22 BITS)

RE3559

1.5.2.3 22-bit Mapping

The full 22-bit address is used to access all of physical memory. As Figure 1-17 shows, the
I/O page remains at the top.

ARCHITECTURE

1-27

Figure 1-17:

22-bit Mapping

17777777
4 K

17760000
INNEYEEN]

177777

2044 K

VIRTUAL

MEM

(16 BITS)

MGMT

000000

00000000

INCOMING

PHYSICAL ADDRESS

ADDRESS

SPACE (22 BITS)
RE3560

1.5.3 Compatibility
Compatibility with other PDI'11 computers is provided by the 16-, 18-, and 22-bit mappinF.

Software written and developed for other PDP11 systems can be run on the KDJ11-D/S. Table
1-18 lists the compatible systems.

Table 1-18:

1-28

KDJ11-D/S Compatibility

Memory

Systems:

Mapping

Management

rDrii/

16-bit

OFF

03, 05, 10, 15, 20

18-bit

23, 35, 40, 45, 50

22-bit

23 PLUS, 24, 44, 70, 73, 83, 84

ARCHITECTURE

1.5.4 Virtual Addressing
Using memory management, memory is dynamically allocated in pages, each having 1 to
128 blocks of 64 bytes (that is, from 64 to 8192 bytes per page). The contents of the 16-bit
virtual address is combined with relocation information from a PAR (Page Address Register),
to provide a 22-bit physical address (Figure 1-18). The starting physical address for each page
is an integral multiple of 64 bytes.

Pages can be located anywhere in the physical address

space.

Figure 1-18:

Virtual to Physical Address Mapping

PHYSICAL
ADDRESS SPACE

PAGE 5
VIRTUAL

INSTRUCTION/DATA
ADDRESS SPACE

K
32

PAR 7

PAR 6

PAR 5

PAR 4

PAR 3

PAGE 6

7\\

PAGE 7

PAR 2

PAGE 4

PAR 1
PAR 0
VIRTUAL ADDRESS

PAGE ADDRESS REGISTERS

(16 BITS)

PHYSICAL ADDRESS

(22 BITS)

PAR = PAGE ADDRESS REGISTER
RE3561

1.5.5 Interrupts Under Memory Management Control
All addresses with memory relocation enabled reference either I space (instruction space) or

D space (data space). I space is used for instruction fetches, index words, absolute addresses,
and immediate operands. D space is used for all other references. 1 space and D space each
have 16 management registers: eight PARs (Page Address Registers) and eight PDRs (Page

Descriptor Registers), in each operating mode (kernel, supervisor, and user).
(Table 1-23) can disable D space, mapping all references through I space.
The current mode of operation (kernel,

supervisor,

MMR3 <02:00>

or user) and the type of reference

(instruction or data) determines which set of 16 page registers (8 PAR and 8 PDR) is used

to provide the physical address.

ARCHITECTURE

1-29

Memory management relocates all addresses. When it is enabled, all traps, aborts, and
interrupt vectors are mapped using the kernel-mode D-space mapping registers. Therefore,
when a vectored control transfer occurs, the new PC and PSW values are read from two
consecutive physical locations at the trap vector mapped with the kernel-mode D-space
registers.

The current PC and PSW are pushed onto the stack specified by new PSW<15:14 >. These bits
also indicate the new mapping register set. The kernel mode program has complete control
for servicing all traps, aborts, or interrupts. The kernel program can assign the service of some
nf these conditinne tn a enpervienr or user mode program: it sets the new PSW mode bits in
the vector, to return control to the appropriate mode.

1.5.6 Building a Physical Address
The physical address is obtained from the virtual address (Figure 1-19, and Tables 1-19 and
1-20) and the appropriate PAR set.
Figure 1-19:

Virtual Address Fields

14
|

]

)

APF
}

—~——

ACTIVE PAGE

——

DISPLACEMENT FIELD

FIELD
RE3564

Table 1-19:

Virtual Address Description

Bits

Description

<15:13>

Active Page Field—Selects one of the eight PARs to use in forming the physical address.

<12:00>

Displacement Field—Contains an address relative to the start of a page. The maximum
number of bytes is 8192, therefore the largest address is 1777. This field is sub-divided into
two fields (Figure 1-20 and Table 1-20).

1-30

ARCHITECTURE

Figure 1-20:

Virtual Address Displacement Field

BLOCK NUMBER

DISPLACEMENT IN BLOCK
RE3565

Table 1-20:

Displacement Field Description

Bits

Description

<12:06>

Block Number—Selects one of the 128 64-byte blocks in the page.

<05:00>

Displacement in Block—Selects one of the 64 bytes in a block.

Figure 1-21 shows how a physical address is assembled. The sequence for building a physical

address is:
1.

The PAR set is selected according to the protection mode and type of reference (instruction

or data).

One of eight PARs is selected by the virtual address APF (Active Page Field).

The PAF (Page Address Field) of the selected PAR contains the starting address of the
currently active page. This address is a block number (64 bytes/32 words per block).

The BN (Block Number) from the virtual address DF (Displacement Field) is added to the
PAF; the result is the number of the block in physical memory. This is bits <21:06> of

the 22-bit physical address.

The DIB (Displacement In Block) field (bits <05:00>) from the virtual address DF is
appended to the physical block number (bits <21:06>) to provide the full 22-bit physical
address.

ARCHITECTURE

1-31

Figure 1-21:

Physical Address Assembly

1312
1

06 05
L

16-BIT VIRTUAL ADDRESS | APF

—

PAR

DIB
W

—

00
L

PAF
i

111

1§

¥
>

PAGE
-]

|
1

NS DU U

§F

|
A

Is
po Bl

TPHYSICALL

—
T

ADDRESS

|1 W

—vy
T

06 05

117

B
00
RE3566

1.5.7 Management Registers (PARs and PDRs)
There are three sets of 32 16-bit management registers (Figure 1-22), one set for each operating
mode (kernel, supervisor, user). Each set of 32 is divided into 16 I-space registers and 16 D-

space registers. Each set of 16 comprises 8 PARs and 8 PDRs.
selected in pairs, by the virtual address APF, bits <15:13>.

1-32

ARCHITECTURE

PARs and PDRs are always

space; that i

in the I/O page. Table 1-2 lists the addresses assigned to the management register

The management registers are locaied in the top 8 Kbytes of physical address
1.5.7.1 Page Address Register

The PAR (Page Address Register) contains the 16-bit PAF (Page Address Field).

See

Figure 1-23. The PAF specifies the starting address of the page as a block number in physical
memory (Section 1.5.6). The contents of the PARs are undefined at power-up, and are not
changed by console starts or the RESET instruction.

ARCHITECTURE

1-33

Figure 1-22:

Management Registers (PARs and PDRs)

PROCESS STATUS WORD Q
15

KERNEL (00)

SUPERVISOR (01)

PAR

PDR

PAR

PDR

USER (11)
PAR

PDR

1 SPACE

PAR

PDR

PAR

PDR

PAR

PDR

0SPACE

RE3567

1-34

ARCHITECTURE

RE3568

1.5.7.2 Page Descriptor Register
The PDR (Page Descriptor Register) contains page exp ansion, length,

See Figure 1-24 and Table 1-21,

Figure 1-24:

and access information.

Page Descriptor Register (PDR)

PLF '

]

'
]

NU
0

ED
0

ACF

0
RE3569

Table 1-21:
Bit

<15>

Page Descriptor Register (PDR) Bits

Access

Description

R/W

Bypass Cache—Conditional cache bypass.

If set in the PDR accessed during a

relocation operation, the reference will go directly to main memory.
write hits will result in invalidation of the accessed cache location.

not used in the KDJ11-D/S.)

<14:08>

R/IW

Read or
(Cache is

Page Length Field—Specifies the block number defining the page
boundary. The
virtual address BN field is compared against the PLF to detect length
errors.
An error occurs when expanding upward if BN>PLF, and when expanding

downward if BN<PLF.

<07>

Attention—When set, indicates a memory management trap condition.
Set by
specific codes (trap conditions) in bits <02:01> to collect memory
management
statistics. Automatically cleared by a write reference to the page’s PAR or
PDR.

<06>

Page Written—When set, indicates the page has been written into
(modified)
since it was loaded into memory. This bit is automatically cleared by
a write
reference to the page’s PAR or PDR.

<05:04>

not used

ARCHITECTURE

1-35

Table 1-21 (Cont.):

Page Descriptor Register (PDR) Bits

Access

Description

<03>

R/W

ds from block
Expansion Direction—When set, the page expands downwar
cleared, the page

<02:01>

R/W

access code specifies
Access Control Field—Contains the page access code. rThe
access should cause the

Bit

number 127, to include blocks with lower addresses. When
expands upwards from block number 0, to include blocks with higher addresses.

how a page can be accessed, and whether a particula
~Adnn Ao
curreni vperation to aboit, The codes
Ld

Access

Bit
02 01

0 0
01

Non-resident—abort all accesses
Read only—abort on writes

Read/write access

<00>

not used—abort all accesses

not used

1.5.8 Fault Recovery Registers

kernel virtual
Aborts generated by the memory management hardware are vectored through
why the
indicate
0:3)
registers
status
(MMU
MMR3
and
MMR2,
MMR1,
MMR0O,
250.
location
abort occurred, and provide for program restart.

Note—Aborts

An abort to a location which is itself an invalid address will cause another abort. The
kernel program must ensure that kernel virtual address 250 is mapped to a valid address;
otherwise a loop will be entered and require console intervention.

1.5.8.1 Memory Management Register 0
Address: 17777572

MMR0 (Memory Management Register 0) provides MMU control and indicates status. See
Figure 1-25 and Table 1-22.

1-36

ARCHITECTURE

Figure 1-28:

Memery Management Register 0 {MMRJ)

0o}

00
¥

ABORT READ-ONLY

—

ACCESS VIOLATION

ABORT PAGE
LENGTH ERROR

PAGE MODE

ABORT
NON-RESIDENT

PAGE NUMBER

PAGE ADDRESS

SPACE I/D

ENABLE RELOCATION
MR-8926

Table 1-22:
Bit
<15>

Memory Management Register 0 (MMRO) Bits

Access

Description

R/W

Non-resident

Abort—Set by an attempt to access a page with the ACF
(PDR<02:01>) = Oor 2, or an attempt to use relocation when processor mode

(PSW<15:14>) = 2. '
<14>

RIW

Page Length Abort—Set by an attempt to access a location in a page with a BN
(virtual address<12:06>) exceeding the PLF (PDR<14:08>) for the page.’

<13>

R/W

Read Only Abort—=Set by an attempt to write into a read-only page (PDR
< 02:01 >

= 01). '

<12:07>

<06:05>

not used

Processor Mode—Indicate the processor mode associated with the page causing
the abort. If the illegal mode is specified, an abort is generated and bit <15>
is set. The modes are:
Bit

Mode

06 05

00
0 1

Kernel
Supervisor

Illegal

User

<04>

Page Space—Indicates the address space associated with the page causing the
abort. If set = D space, if cleared = I space.

<03:01>

Page Number—Indicate the page number of the page causing the abort.

<00>

R/W

Enable Relocation—If set all addresses are relocated.

management is disabled, and addresses are not relocated.

If cleared,

memory

"Bits <15:13> can be set with an explicit write, and not cause an abort. If set explicitly or by an abort, setting

any of these bits causes memory management to freeze the contents of MMRO<06:01

registers remain frozen until MMR0<15:13> are cleared with an explicit write.

>, MMR1, and MMR2. The

ARCHITECTURE

1-37

1.5.8.2 Memory Management Register 1
Address: 17777574

MMR1 records any autoincrement or autodecrement of a general purpose register, including
explicit references through the PC. The increment/decrement value is stored in 2’'s complement
(Figure 1-26). The lower byte is used for all source operand instructions; the destination
operand can be stored in either byte, depending on the mode and instruction type. MMR1 is
normally cleared at the start of each instruction fetch. If its contents are frozen by an abort
posted in MMRGO, it remains so until MMR0<15:13> are cleared by an explicit write.
Memory Management Register 1 (MMR1)

Figure 1-26:

L
L

{

]

AMOUNT CHANGED

{2'S COMPLEMENT)

L
A

NUMBER

_]
~

(2'S COMPLEMENT)

AMOUNT CHANGED

NUMBER

MR-8924

1.5.8.3 Memory Management Register 2

Address: 17777576

MMR? is loaded with the PC value of the current instruction, and is frozen when any abort
condition is posted in MMRO, and remains so until MMR0<15:13> are cleared by an explicit

write.

1.5.8.4 Memory Management Register 3
Address: 17772516

MMR3 enables the D space for all three operating modes, enables the request for the
supervisor macroinstruction (CSM instruction), and selects either 18- or 22-bit mapping.
MMR3 is cleared by power-up, console restart, or a RESET instruction. See Figure 1-27
and Table 1-23.

1-38

ARCHITECTURE

riyuie

n -

i~ s
o ooo

1—c<s.
{

- om

m —mm

UNINTERPRETED
ENABLE 22-BIT

MAPPING

ENABLE
CSM iNSTRUCTION
KERNEL

SUPERVISOR
USER
MR-8925

Table 1-23:
Bit

Memory Management Register 3 (MMR3) Bits

Access

<15:06>

<05>

Description
not used

R/W

Uninterpreted—Can be set and cleared by software but is not interpreted by the
KDJ11-D/S.

<04>

R/W

Enable 22-bit Mapping—When set, 22-bit memory addressing is enabled (the
default is 18-bit addressing).

<03>

R/W

Enable CSM Instruction—When set, enables recognition of the CSM instruction.

<02>

R/W

Kernel Data Space——When set, mapping for the kernel data space is enabled.

<01>

R/W

Supervisor Data Space—When set, mapping for the supervisor data space is
enabled.

<00>

R/W

User Data Space—When set, mapping for the user data space is enabled.

1.5.8.5 Instruction Back-up/Restart Recovery

Backing-up and restarting a failed instruction includes:

Performing the appropriate memory management tasks to clear the cause of the abort; for
example, loading a missing page.

Restoring the contents of the general purpose registers indicated in MMR1< 10:08,02:00
>

to their value at the start of the instruction (the increment/decrement in MMR1<15:11,07:03 >

is subtracted/added).
3.

Restoring the contents of the 'C by loading R7 with the value in MMR2.

This procedure relies on the use of different general purpose register sets for the program
segment and the recovery routine.

ARCHITECTURE

1-39

1.5.8.6 Clearing Status Registers After an Abort

MMR0
< 15:13 > must be cleared (set to zero) at the end of a fault service routine in order for
MMR0, MMR1, and MMR2 to resume their monitoring functions.
1.5.8.7 Multiple Faults

The first abort will freeze the contents of MMR0, MMR1, and MMR2. Subsequent errors
will not change the contents of these registers, until the first error has been cleared, and
MMRO0O< 15:13
> have been cleared.

1.5.9 Typical Usage
The following sections describe three typical uses of memory management, where a supervisory program operating in kernel mode dynamically assigns various sized memory pages in
response to system needs.

1.5.9.1 Typical Memory Page

When the MMU is enabled, the kernel mode program, a supervisor mode program, and
a user mode program are each assigned eight active pages for data and eight active pages
for instructions. These pages are described by the appropriate PARs and PDRs. Each page

contains from 1 to 128 blocks, and is pointed to by the PAF (Page Address Field) in the
corresponding PAR. Figure 1-28 shows a typical page in an 128 block segment. The page has
the following attributes:

1-40

Page Length = 40 blocks

Virtual Address range = 140000:144777

Physical Address range = 312000:316777

The page has not been modified (not written into)

Read-only access

Upward expansion

ARCHITECTURE

Figure i-28:

Typicai Miemory Page

VA 157777

PA 331777

BLOCK 177

BLOCK 176

VA 144777

PA 316777
BLOCK 47

fJJ

BLOCK 1

BLOCK 0

VA 140000

PA312000

PAR 6

VA 140000

3120

PAF
PDR 6

olo

0ol

PLF

A W

ED ACF

RE3570

The attributes are determined as follows:
1.

PAR 6 and PDR 6 are selected by the VA (virtual address) APF (Active Page Field). That
is, VA<15:13> = 6.

The PAF (Page Address Field) of PAR 6 determines the page starting address:
3120g X 100g bytes/block = 3120004

The PLF (Page Length Field) of PDR 6 determines the page length:

block number 47g + 1 = 50g blocks

ARCHITECTURE

1-41

Any attempt to reference beyond 50g blocks will cause a page length error, resulting in an
abort vectored through kernel address 250.

The physical addresses are assembled as shown in Figure 1-21.

The W bit (PDR6<06>) indicates that this page has not been modified. The state of this
bit determines if the page must be written back to mass storage in a swapping or memory
overlay scheme.

The ACF (Access Control Field) (PDR6<02:01>) 1 ndicates this page is protected by read.

Ulu_y

T o]

[ S LN N WS 7%

Agarr

ALHJ

~tbnrvnint boy

Llll\.kitt/t

v ATl frareibn)

control violation abort.

\brriiny

!
any
*J
T

~
[

Antinn iny tHhia maoe will faiee an acceae
Wk

balar

azl

t‘"to‘-

e
maA

The ED (expansion direction) bit (PDR6<03>) is zero, indicating upward expansion. If
additional blocks are required for this page, blocks with higher addresses will be assigned.
these attributes can be determined by software. The parameters are loaded into the
In normal applications, the page containing
app ropriate PAR and PDR under program control.
All

the PARs and PDRs is assigned to kernel mode program control.

1.5.9.2 Non-consecutive Memory Pages

Higher virtual addresses do not necessarily map to higher physical addresses.

A single

memory page must comprise a block of contiguous locations, but consecutive virtual memory

pages do not have to reside in contiguous blocks of physical memory. See Figure 1-29.
non-overlapping physical

The assignment of memory pages is not restricted to consecutive,

address locations.

Figure 1-29:

Non-consecutive Memory Pages

VA 037777

PA 460000

I
i
i
i
1

PAR 7

VA 020000

PA 467777

VA 017777

PA 560777

PAF

|
]

i
PAR 1

PAF

PAR 0

PAF

VA 000000

PA 541000
RE3E71

1-42

ARCHITECTURE

1.5.9.3 Stack Memory Pages

Program variables are often isolated from “pure code” (that is, instructions) by placing the
variables in a register indexed stack. The variables are then “’pushed’” on or ““popped’” off the

stack as needed. Because stacks expand by adding memory locations with lower addresses,
a memory page containing stacked variables must expand downward when it needs more
room. That is, blocks with lower relative addresses must be added to the page.

Therefore,

the expansion direction bit (’'DR<03>) is set to 1. Figure 1-30 shows a stack memory page
with the following parameters.

PAF = 31204

PLF = 1754

ED =1

W = 0or1 (set by hardware)

ACF = determined by programmer

Figure 1-30:

Typical Stack Memory Page

157777

331777

331500

312000

BLOCK 177
BLOCK 176
BLOCK 175
VA

157500

—l

"WA

BLOCK
O
VA

140000

PAR

PDR

PAF
SLF

ED| ACF

MR-0486-0380

The stack begins 128 blocks above the relative origin of the memory page and extends
downward for three blocks. A page length error abort will occur if a location below the
assigned area is referenced; that is, when the BN (Block Number) from the virtual address
(VA<12:06>) is less than the PLF (PDR6<14:08>).

ARCHITECTURE

1-43

1.6 MEMORY SYSTEM REGISTERS
In the KDJ11-D/S, the MER (Memory Error Register) is the only memory system register used
(Figure 1-1). Cache is not an option on the KDJ11-D/S, and the CCR (Cache Control Register),
and the Hit/Miss Register are not used.

1.6.1 Memory Error Register
Address: 17772100

The MER (Memory Error Register) controls and monitors the memory parity function. Bits in
the MER can be used to disable parity error detection, and to force parity errors for diagnostic
purposes. See Figure i-31 and Table 1-24.

Memory Error Register (MER)

Figure 1-31:

PAR | EXT

0 NU

erR | REN

05
I

]

ERROR ADDRESS

]

0 NU

WWP

NU
o

00
PE

ENB

]
MR-0486-0381

Table 1-24:
Bit
<15>

Memory Error Register (MER) Bits

Access

Description

R/W

Parity Error—When set, indicates a parity error has occurred. This bit is not

automatically cleared when the CPU responds to a parity error; it must be

explicitly cleared by writing a zero into it.

It is also cleared by power-up or

bus INIT.
RIW

Extended MER Read Enable—See <11:05>. Cleared by power-up or bus INIT.

<13:12>

not used—always read 0

<11:05>

R/IW

Error Address—If a parity error occurs, A<17:11> are stored in these bits,
and A<21:18> are latched. When MER<14> = 0, reading the MER transfers
MER<11:05> (A<17:11>) to the CPU. Software must then set MER<14> = 1;
and read the MER a second time to transfer A<21:18> through MER <08:05> .

<04:03>

not used—always read 0

<02>

R/W

Write Wrong Parity—When set, wrong parity data will be written into on-board
RAM on a DATO or DATOB bus cycle. Cleared by power-up or bus INIT.

<01>

not used—always reads 0

<00 >

R/IW

Parity Error Enable—When set and a parity error occurs on a Q22-bus DATI or
DATIO(B) cycle from a bus master to RAM, BDAL<17:16> are asserted on the
bus at the same time data is asserted. When the CPU is reading on-board RAM,
5 parity error causes a Parity Error trap. This bit is cleared by power-up or bus

<14>

INIT.

1-44

ARCHITECTURE

Table 1-24 (Cont.):

Memory Error Register (MER) Bits

Bit

Description

Access

Note—Parity Errors
A parity error on Q22-bus data is asserted during the current instruction cycle. A parity
error on local memory data is asserted during the next instruction cycle.

1.7 FLOATING-POINT
The processor uses the floating-point instruction set to perform all floating-point arithmetic
operations, and converts data between integer and floating-point formats. Similar address

modes and the same memory management facilities are used. Floating-point instructions can
reference the floating point accumulators, the general registers, or any locations in memory.

See the Associated Documents listed in the Preface for more details on floating-point.

1.7.1

Floating Point Registers

The floating-point registers are shown in Figure 1-1, and are defined as the FPS (Floatingpoint Status Register), FEA (Floating-point Exception Address Register), FEC (Floating-point
Exception Code Register), and six accumulators.
1.7.1.1

Floating-point Status Register

The FPS (Floating-point Status) Register provides mode and interrupt control for the FPP and
conditions caused by previous instruction execution. See Figure 1-32 and Table 1-25,

The FPP recognizes six exceptions:
Floating opcode error
Floating divide by zero

Floating or double-to-integer conversion error
Floating overflow

Floating underflow
Floating undefined variable
Illegal opcode and divide by zero interrupts can be disabled only by setting FPS<14>.
The other four exceptions can be disabled by clearing the appropriate exception bit in
FP5<11:08>.

The four condition codes FPS <03:00> are equivalent to the CPU condition codes (PSW<03:00>).
The FPP sets the error flag and condition codes (PPS<15,03:00>) as part of the output of a
floating-point instruction. The bits <15:14,11:05,03:00> can be set and cleared by the LDFPS

instruction.

ARCHITECTURE

1-45

Figure 1-32:

Floating-point Status Register (FPS)

INT
FL
ERR | DIS

INT | INT | INT
ov
UF
uv

NU
4

NU
FL
FL
INT | FL
DPM | LIM | CHM | O
IC

FL
N

FL
z

FL
A

FL
C

MR-©377

Table 1-25:
Bit

<15>

Floating-point Status (FPS) Bits

Access

Description

R/W

Floating Error—Set by a floating-point instruction if any of the following occur:
*

divide by zero

illegal opcode

any of the remaining exceptions with the corresponding interrupt (bits
<11:08>) enabled

The FPP never resets this bit. If set, it can be cleared only by an LDFPS
instruction. Therefore, this bit is up to date only if the most recent floating-point
instruction produced an exception.
This bit is independent of <14>.

<14>

RIW

Interrupt Disable—If set, all floating-point interrupts are disabled. Primarily,
this is a maintenance bit, and should normally be cleared. It must be cleared in
order {o generate an interrupt if the FPI’ stores a negative 0.

<13:12>

<11>

not used

R/W

Interrupt on Undefined Variable—An interrupt occurs if this bit is set and a
negative 0 is obtained from memory as an operand of an ADD, SUB, MUL,

DIV, CMP, MOD, NEG, ABS, TST, or any LOAD instruction. The interrupt

occurs before execution. When cleared, negative 0 can be loaded and used in
any FPP operation.

The interrupt is not generated by negative 0 in any AC operand of an arithmetic
instruction; in particular, trap on negative 0 never occurs in addressing mode
0.

The FPP will not store the result of negative 0 without a simultaneous interrupt.

<10>

R/W

Interrupt on Underflow—When set, floating underflow will cause an interrupt.
The fractional part of the result will be correct. The biased exponent will be too
large by 4003, except for the special case of 0, which is correct (see the LDEXP
instruction for an exception).

If an underflow occurs when cleared, the interrupt is disabled, and the result is
set to exact 0.

1-46

ARCHITECTURE

Table 1-25 (Cont.):
Access

Bit

<09
>

RIW

Floating-point Status (FPS) Bits
Description

Interrupt on Overflow—When set, floating overflow will cause an interrupt.

The fractional part of the result will be correct. The biased exponent will be
too small by 4003. (See the MOD and LDEXP instructions for special cases of
overflow.)

If an overflow occurs when cleared, the interrupt is disabled, and the result is
set to exact 0.
>
<08

RIW

Interrupt on Integer Conversion—An interrupt occurs when this bit is set and
a conversion to integer instruction fails. If an interrupt occurs, the destination
is set to 0; all other registers are unaffected.

If this bit is cleared, the operation is the same as above, but no interrupt occurs.

The conversion instruction fails when it generates an integer with more bits
than can fit in the long or short integer word specified by <06>.
<07
>

R/IW

< (06>

R/W

Floating Double-precision Mode—When set, double-precison is used for calculations; when cleared, single-precison is used.

Floating Long Integer Mode—Used in conversion between integer and floatingpoint format. When set, integer format is 2’s complement double-precision (32bit); when cleared, integer format is 2’s complement single-precision (16-bit).

<05>

Floating Chop Mode—When set, the result of any arithmetic operation is

<04
>

not used

“’chopped”’ (truncated). When cleared, the result is rounded.

<03>

RIW

<02>

R/IW

<01>

RIW

<00>

R/IW

Floating Negative—Set if the result of the last floating-point operation was
negative; otherwise cleared.

Floating Zero—Set if the result of the last floating-point operation was zero;
otherwise cleared.

Floating Overflow—Set if the last floating-point operation resulted in exponent
overflow; otherwise cleared.

Floating Carry—Set if the last floating-point operation resulted in a carry from
the most significant bit. This can only occur in a floating or double-to-integer
conversion.

1.7.1.2 Floating-point Exception Registers

One interrupt vector (244) is assigned to process all floating-point exceptions. There are six
possible errors, encoded in the 4-bit FEC (Floating-point Exception Code) Register:
02 Floating opcode error
04 Floating divide by zero
06 Floating or double-to-integer conversion error
08 Floating overflow
10 Floating underflow
12 Floating undefined variable

The FEA (Floating-point Exception Address) Register stores the address of the instruction that
produced the exception.

ARCHITECTURE

1-47

One of the following updates the FEC and FEA Registers:
*

Illegal opcode.

Divide by zero.

Any of the other exceptions with the corresponding interrupt enabled.

If any of the four exceptions, code 06 through 12, occurs with the corresponding interrupt
disabled, the FEC and FEA Registers are not updated. Updating is not inhibited if the FID bit
(FPS<14>) is set. The FEC and FEA Registers are not updated unless an exception occurs.
Lhis means that the STORE STATUS (STST) instruction will return current information only
if the most recent floating-point instruction produced an exception. There are no instructions
for storing into the FEC and FEA Registers.
1.7.1.3 Floating-point Accumulators

The six 64-bit accumulators, ACO through ACS5, provide for temporary storage and manipulation of 32- and 64-bit floating-point data types.

1-48

ARCHITECTURE

Chapter 2
INSTALLATION
This chapter describes how the KDJ11-D/S is configured and installed in an LSI-11 system.
The module can be installed in systems using either the standard LS1-11 bus backplane or the
extended LSI-11 bus (Q22-bus) backplane. Before installing the KDJ11-D)/S:
1.

Configure the user-selectable features.

Be sure that the backplane, mounting box, and options are compatible with the KDJ11-D/S.

Consider any system differences between the KDJ11-D/S and the LSI-11 processor it may
be replacing. See Section 2.5.2.

2.1 CONFIGURATION
The KDJ11-D/S has 16 jumpers for its user-selectable features (see Figure 2-1 and Table 2-1).

Earlier versions of the module have 13 jumpers, and a different module layout (see Figure 2-2
and Table 2-1). There are some additional jumpers which are factory set. Jumpers are installed
by pushing an insulated jumper wire (part number 12-18783-00) onto two wirewrap pins on

the module.

INSTALLATION

2-1

Figure 2-1:

KDJ11-D/S Module (M7554)

rararararcarrararrarca

CONNECTOR

LdLaLdLdLrdLaLsbacd

FArariririrararcara

o1l

r_1

. e .. Oy . e o s 0
« o e . . o ® LdudiLdu
auas

0.5 MB/1.5 MB RAM

LJLdLJuJ

Faririririrararars.

. ' Y . e . @ .« o .o .o

Cilidbtsvitivitivins

rirarararirirairara
. &

* ®

LaLJLJLJLJLJLJILJL a

_R14-

W12

W 6

W11

W10

W23

W22
W2

DC7064

DCCSU

DC7063

[

] L

I L

] 1

1§ L

J L

] L

fi:ET_flTT_[

ool

0
000000000000t
RE3662

2-2

INSTALLATION

Figure 2-2:

KDJ11-D/S Module - Early version (M7554)

W30

W80

ows

34-PIN CONNECTOR

oW20

ow22

NATIVE AND MAINTENANCE
REGISTERS
E99|E94
©

E74

owi13

BOOT/ |

OoWs

ow9

DLART1[DLARTO|

ES8

ow4a

W70

MAINTENANCE

ROMS

wi2o0

—

DIAGNOSTIC

E108|

W100

E41

E31

W11

E26

O—O0 w1

DCJ11

STATE
MACHINE

512 KBYTE RAM

W21 0—o0

Eg PLS
|
E3

E46

o0——o0 W20
C

A r

SIDE
1
MR-0486-0382

INSTALLATION

2-3

Table 2-1:

Jumpers

Comments

Jumper/Position
HALT

Trap on HALT disabled'

In
Boot
Select

Baud Rate

Out

T'rap on HALT enabled

W2
W3

Boot select—see Table 2-2
Boot select—see Table 2-2

W10

W6é

Out

Out
Out
Out
In
In
In
In
BREAK

Boot select—see Table 2-2
Boot select—see Table 2-2
Boot select—see Table 2-2

W5
W8
w22

Out
In
In
Out
Out
In
In

W13

R14

In
Out

Out
In

W20

W21

600
1200
2400
4800
9600
19200
38400

32-kbyte self-test ROMs
16-kbyte self-test ROMs

Backplane pin CM2 to pin CN2'
Backplane pin CR2 to pin CS2'

~12 V connected to ]1
no power to J1

w24
in
out

RAM Size®

300"

W23

in
out

Special Applications®

Baud Rate?

Console BREAK enabled’

In
-12V

DLART1

Console BREAK disabled

Backplane®

In
Out
In
Out
In
Out
In

DLARTO

W11

Out
ROM Size®

W12

Special application
Normal

W25
in
out

0.5 Mbyte of on board RAM
1.5 Mbyte of on board RAM

IFactory setting or default
2To use remote switch, remove all jumpers

3W13, R14, and ROMs are factory installed

*Not user selectable—soldered in
W24 and W25 are only on the re-engineered versions, and are factory installed

2-4

INSTALLATION

2.1.1 Power-up Options
Unlike other KDJ11 modules, the KDJ11-D/S does not have a power-up option jumper, but
supports only power-up mode 2, bootstrap on power-up. (Maintenance Register<01> input
is tied to ground and <02> input is tied HIGH.) The bootstrap starting address is fixed
at 17773000.
The processor sets PC<15:10> to all ones, and PC<09:00> to all zeros
(that is, 173000). The processor’s priority level is set to seven by loading 340g into the
PSW (Figure 1-2). The processor then either services pending interrupts, or starts program
execution, at the memory location pointed to by the PC. The processor reads the bootstrap
option in Native Register<12:08> (Figure 1-7), to direct the bootstrap program.
2.1.1.1 Power-up Sequence

The power-up sequence is shown in Figure 2-3.
2.1.1.2 Power-down Sequence
The power-down sequence is shown in Figure 2-4.

2.1.2 Bootstrap Options
The bootstrap options selected by jumpers W22, W2, W3, W5, and W8 or remote switch are
as shown in Table 2-2.

INSTALLATION

2-5

Figure 2-3:

Power-up Sequence

TURN OFF D1

TURN ON D2, D3, D4

ASSERT BINIT L
WAIT 10 4S

EXPLICITLY READ

MEMORY LOCATION

THE CACHE AND CLEAD

177700

CCR<15:9, 7:0>

EXPLICITLY CLEAR
MISER

NEGATE BINIT L

CLEAR MMR

]

EXPLICITLY SET

CCR<8> TO FLUSH

CLEAR MMR3

NXM ABORT

CLEAR PS

TURN OFF D3

SET CPU ERROR REG

MEMORY LOCATION

TO 177766

EXPLICITLY READ CPU

WAIT 90 uS

CLEAR CPU ERROR REG

EXPLICITLY READ

177560

ERROR REGISTER

NXM ABORT

YES

EXPLICITLY CLEAR
PIRQ

READ

CLEAR FPS

EQUAL
WRITTEN

READ JUMPERS

TURN OFE D2

TURN OFF D4

POWER UP

PC@®24

OPTION O

PS@26

CLEAR CPU ERROR REG
EXPLICITLY READ

BEGIN
EXECUTING

MEMORY LOCATIONO

CODE

BPOK H

POWER UP

ASSERTED
NXM ABORT

YES

OPTION 1

:\E/]':Ig:g oDT
PS=0

POWER UP

PC = 173000

OPTION 2

PS = 340
BEGIN
EXECUTING

CODE

PC<15:12> = USER BOOT
PC<11:0>=0
PS
= 340

BEGIN EXECUTING CODE

2-6

INSTALLATION

MR.11062

Figure 2-4:

Power-down Sequence

POWER DOWN j

CLEAR POWER FAIL

FLIP-FLOP

l
TRAP THROUGH

VECTOR 24

CONTINUE EXECUTING CODE

le—
-

HALT
INSTRUCTION

EXECUTE
INSTRUCTION

READ JUMPER OPTIONS

SET CPU ERROR

KERNEL

REG<7>; TRAP

MODE

VECTOR 4

BPOK H

INITIATE POWER UP
SEQUENCE

ASSERTED

HALT

OPTION JUMPER
REMOVED

YES

SET CPU ERROR
REG<7>; TRAP

VECTOR 4

ENTER MICRO-ODT

MR-11063

INSTALLATION

2-7

Table 2-2:

Boot Select Options

Jumper W:

Switch

Position?

2358'

Description

W22 Installed

0000

Test, enter console mode using English text’”

0001

Test, enter console mode using French text

0010

Test, enter console mode using German text

0011

Test, enter console mode using Dutch text

0100

Test, enter console mode using Swedish text

0101

Test, enter console mode using Italian text

0110

Test, enter console mode using Spanish text®

0111

Test, enter console mode using Portuguese text

1000

Test, enter console mode (reserved)

1001

Test, enter console mode (reserved)

1010

Test, enter console mode (reserved)

1011

Test, enter console mode (reserved)

1100

Test,® autoboot tapes & disks,” user selects language

1101

Test, autoboot DPV11, DUV11, DLV11-E/F, TU58 & RKO05

1110

Test, autoboot DEQNAs 0 and 1

1111

Manufacturing test loop

W22 Removed

0000

Test, autoboot tapes & disks® using English text®

0001

Test, autoboot tapes & disks using French text

0010

Test, autoboot tapes & disks using German text

0011

Test, autoboot tapes & disks using Dutch text

10 = Installed, 1 = Removed
ZJumpers W2, W3, W5, and W8 removed to use switch
3Only English (positions 00000 and 10000) and Spanish (positions 00110 and 10110} can be selected with version 1.0)
ROMSs. Eight languages can be selected with version 2.0 ROMs.

4Factory or default setting
SHigh speed autoboot, memory address/shorts test bypassed

6 ‘tapes & disks’’ = DU 0-255, DU 0-255 at floating addresses, DL 0-3, DX 0-1, DY 0-1, MU 0), and MS ). For DU,
removable media is booted before fixed media.

2-8

INSTALLATION

Table 2-2 (Cont.):

Boot Select Options

Jumper W:

Switch

2358'

Position

0100

0101

0110

Test, autoboot tapes & disks using Spanish text®

0111

Test, autoboot tapes & disks using Portuguese text

1000

Test, autoboot tapes & disks (reserved)

1001

Test, autoboot tapes & disks (reserved)

1010

Test, autoboot tapes & disks (reserved)

1011

Test, autoboot tapes & disks (reserved)

1100

Emulate Power-up mode 24 with no messages

1101

Halt & enter ODT if trap-on-halt disabled, else loop’

1110

Test, autoboot DEQNAs 0 and 1

1111

Test, enter console mode, user selects language

Description
Test, autoboot tapes & disks using Swedish text
Test, autoboot tapes & disks using Italian text

10 = Installed, 1 = Removed
2Jumpers W2, W3, W5, and W8 removed to use switch

3Only English (positions (0000 and 10000) and Spanish (positions 00110 and 10110)
ROMs. Eight languages can be selected with version 2.0 ROMs.
i

roaew

can be selected with version 1.0

removed, disabied = instalied)

2.1.3 HALT Option
The HALT option determines whether the action taken after a HALT instruction
is executed in the

kernel mode. When the HALT instruction is executed, the processor checks
the HALT option in
Maintenance Register<03>. This bit is set (its input is tied HIGH) when jumper
W1 is removed,

and the processor traps to location 4 in the kernel data space and sets CPU Error
Register< 07>
(Figure 1-4). If jumper W1 is installed, Maintenance Register<03>
is cleared (its input is tied
to ground), and the processor enters console ODT mode when a HALT instruction
is executed.
Console ODT mode is exited with the G command (for more information on
ODT, see the
Associated Documents listed in the Preface). The exit sequence is shown
in Figure 2-5.

INSTALLATION

2-9

Figure 2-5:

‘

Console ODT Exit Sequence

MICRO-ODT ‘G’ )
1

TURN OFF D1

CLEAR FPS

ASSERT BINIT L

WAIT 10 uS

READ JUMPERS

CLEAR CPU ERROR REG

NEGATE BINIT L

:
CLEAR MMRO

M
CLEAR MMR3

BPOK H
ASSERTED

EXPLICITLY SET

]

CCR<8> TO FLUSH

WAIT 90uS

EXPLICITLY CLEAR

THE CACHE

MSER

PIRQ

CLEAR PS

‘BEGIN EXECUTING CODE
MR-11064

2.1.4 Factory Configuration

The factory, or shipped, configuration of the option jumpers is shown in Figure 2-1 and
described in Table 2-1.

2-10

INSTALLATION

2.2 DIAGNOSTIC LEDS
The module has seven indicator lines, IND<6:0>, driven by Native Register<0
6:00>
(Figure 1-7). These lines are connected to the on-board connector J1 (Table
2-4), to drive
remote LED indicators for monitoring module status. The self-test program
reports its status
in bits Native Register<03:00>, Table 2-3. An error is indicated when the display remains
set to a value for more time than is normally required to run the associated test.

Table 2-3:

Self-test ROM Display Codes

Bits

Value!

Description

0000

HALT switch on, CPU fault, power supply fault, or control has passed from ROM
code to secondary boot

0001

Preliminary CPU testing—limited
error messages

0010

Console SLU testing

0011

CPU testing

0100

On-board memory testing

0101

<03:00>

0111

Floating-point, LTC interrupt, SLUO interrupt, and SLU1 interrupt testing

1000

not used

1001

not used

1010

not used

1011

not used

1100

not used

1101

Wrap mode in progress

1110

m oM

0110

External memory testing

Boot in progress

1111

not used

Console mode in progress

"Hexadecimal value

INSTALLATION

2-11

Table 2-4:

J1 Pin Assignments

To/From

Function

Signal Ground

+5F H

+5 Vdc Fused

+5F H

+5 Vdc Fused

+12F H

+12 Vdc Fused

-12 Vdc

BHALT L

Q22-bus Processor Halt L.

BREAK H

Console Break Signal

DLARTO

CBROH

Console Baud Rate 0

DLARTO

CBR1 H

Console Baud Rate 1

DLARTO

CBR2 H

Console Baud rate 2

DLARTO

INDO H

Indicator Bit 0

Native Reg

INDT H

Indicator Bit 1

Native Reg

IND2 H

Indicator Bit 2

Native Reg

IND3 H

Indicator Bit 3

Native Reg

IND4 ti

Indicator Bit 4

Native Reg

INDS H

Indicator Bit 5

Native Reg

IND6 H

Indicator Bit 6

Native Reg

PBRO H

Printer Baud Rate O

DLART1

PBR1 H

Printer Baud Rate 1

DLART1

PBR2 H

Printer Baud Rate 2

DLART1

RECVDLOH

Console Receive Data +

DLARTO?

RECVDLOL

Console Receive Data -

DLARTO?

RECVDLT H

P’rinter Receive Data -

DLARTI-

RECVDLTL

Trinter Receive Data -

DLART1

Signal Name

pEU

Table 2-4 (Cont.):

J1 Pin Assignments

Signal Name

Function

STBO H

Boot Switch Bit 0

Native Reg

STB1 H

Boot Switch Bit 1

Native Reg

STB2 H

Boot Switch Bit 2

Native Reg

STB3 H

Boot Switch Bit 3

Native Reg

TXMTDLOL

Console Transmit Data +

DLARTO?

TXMTDL1 L

Printer Transmit Data +

DLART1?

To/From

Indirectly
T
T

2.3 MODULE EDGE CONNEC
TO

R PINS

The KDJ11-D/Sis a quad-height

C, and D, corresponding to the

module, meaning it has four back

plane edge-connectors: A, B,
re 2-6). The Q22-bus signals

backplane connector rows (Figu

are carried in connector rows
A and B. In certain configurat
ions, backplane rows C and
D

form the CD interconnect for certa

in slots. The component side
of the module is side 1 and
the solder side is side 2. Fach conne
ctor has 18 pins on each side of
the module, labeled A
through V (36 pins per connector)
. For example, pin BE2 is:

B—connector (row) B

E—pin E (fifth from top)
2—side 2 (solder side)

Table 2-5 lists the edge connecto

r pin assignments for the KDJ1

Table 2-5:

—

1-D/S.

Modu
ie Edge Connector Pin
VT

Component Side
Pin

Signal Name

AA1

BIRQ5 L'?

AB1

BIRQ6 L'?2

AC1

T =VYE LONnector Fin Assignments
Assi
]

Solder Side
Pin

Signal Name

AA2

45V

AB2

-12V!

BDALI16 L

AC2

GND

AD1

BDAL17 L

AD2

+12V

AEl

SSPARE 1!

AE2

BDOUT L

AF1

SRUN H

AF2

BRPLY L

AH2

BDIN L

BSYNC L

AK2

BWTBT L

AH1
All

GND

AK1

MSPARE A'

'Not connected on the module
Z"I'ermirmted but not used

INSTALLATION

2-13

Table 2-5 (Cont.): Module Edge Connector Pin Assignments
Component Side
Signal Name
Pin

Solder Side

Signal Name

ALl

MSPARE A'

AL2

BIRQ4L

AM1

GND

AM2

BIAKI L

AN1

BDMR L

AN2

BIAKO L

AP1

BHALTL

AP2

BBS7L

AR1

BREFL

AR2

BDMGIL

AS1

+12B!

AS2

BDMGOL

ATl

GND

AT2

BINITL

AU1

PSPARE 1

AU2

BDALOL

AVl

+5B

AV2

BDAL1L

BA1

BDCOK H

BA2

+5V

BB1

BPOKH

BB2

-12V'

BC1

BDALISL

BC2

GND

BD1

BDAL19L

BD2

+12V'

BEl

BDAL20L

BE2

BDAL2L

BF1

BDAL21L

BF2

BDAL3L

BH1

SSPARE 8'

BH2

BDAL4L

Bjt

GND

B]2

BDAL5L

BK1

MSPARE B

BK2

BDAL6L

BLl

MSPARE B!

BL2

BDAL7L

BM1

GND

BM2

BDALSL

BN1

BSACKL

BN2

BDAL9L

BP1

BIRQ7 L!?

BP2

BDALIOL

BR1

BEVNTL

BR2

BDALI1L

BS1

PSPARE 4'

BS2

BDALI12L

BT1

GND

BT2

BDALI13L

BU1

PSPARE 2’

BU2

BDALI4L

BVl

+5V

BV2

BDALISL

CA2

+5V

CA1l
INot connected on the module

2Terminated but not used

2-14

INSTALLATION

Table 2-5 (Cont.):

Module Edge Connector Pin Assignments

Component Side

Solder Side

Signal Name

CB1

CB2

CC1

CC2

CD1

CD2

CE1

CE2

CF1

CF2

CH1

CH2

CJ2

CK1

CK2

CL1

CL2

CM1

CM2

AK L?

CN1

CN2

IAK L?

CP1

Ccr2

CR1

CR2

DMG L?

CS1

CS2

DMG L}

CT1

GND

CT2

Ccu1l

Cu2

Cv1

CV2

DA1

DA2

DB1

DB2

DC1

DC2

DD1

DD2

DE1

DE2

DF1

DF2

DH1

DH2

DJ2

DK1

DK2

DL1

DL2

DM1

DM2

45V

GND

3Soldered-in jumper W20 connects these pins
*Soldered-in jumper W21 connects these pins

INSTALLATION

2-15

Table 2-5 (Cont.):

Module Edge Connector Pin Assignments

Component Side

Solder Side

Signal Name

DN1

DN2

DP1

DP2

DR1

DR2

DS1

DS2

DT1

GND

Signal Name

DT2

DU1

DU2

DV1

DV2

2.4 HARDWARE OPTIONS
The KDJ11-D/S module can be configured into an operating system using a variety of
backplanes, power supplies, enclosures, and L5I-11 type modules.

2.4.1

Restricted LSI-11 Options

LSI-11 options not compatible or restricted for use with the KDJ11-D/S are listed in Table 2-6.

Backplanes, memories, or /O devices which do not use 22-bit addresses may generate or
decode erroneous addresses if installed in systems that use 22-bit addresses.
Memory-addressing devices which use only 16- or 18-bit addresses can be installed in a 22-bit
backplane; however, system memory size must be restricted to the address range of such
devices (that is, 64 kbytes with 16-bit devices, and 256 kbytes with 18-bit devices).

Caution—16-bit and 18-bit Memories
Neither 16-bit nor 18-bit memories can be used with the KDJ11-D/S. Such memories
would be “’invisible’’ to the CPU. However, the address space for such memories would
overlap on-board memory address space, causing DMA problems.

Devices using backplane pins BC1, BD1, BE1, BF1 or DC1, DD1, DE1, DF1 for signals other

than BDAL<21:18> are not compatible with the Q22-bus.

Such devices cannot be used

without modification.

Note—18-bit DMA Devices
Eighteen-bit DMA devices have the potential to work in Q22-bus systems if 1/O is

buffered in the 18-bit address space.

2-16

INSTALLATION

Module Edge Connectors

AA1

< o

sA/iy& 1)).\,“Yr>\Y”\n

Figure 2-6

W/A
o

SIDE 1

VI,

ROW C

COMPONENT SiDE

R SN

S 2

ROw B

R Y

qiimiiig

ROW A

SIDE 2

SOLDER SIDE
ROW D

bv2

MR 5456

INSTALLATION

2-17

Table 2-6: Restricted or Non-compatible LSI-11 Options
Option

Module

Description

Backplanes (18-bit addressing only)

DDV11-B

6 * 9 Backplane

H9270

4 X * Backplane

HI9273-A

4 » 9 Backplane

VT103 BP

4 * 4 Backplane (54-14008)

Memory (16-bit addressing only)

MMV11-A

G653

Core memory (Q22-bus required on C/D backplane connectors)

MRV11-AA

M7942

ROM

MRV11-BA

M8021

UV PROM-RAM

MSV11-B

M7944

MOS

Memory (18-bit addressing only)

MRV11-C

M8048

PROM/ROM

MSV11-C

M7955

MOS

MSV11-D/E

M8044/M80

MOS

MXV11-A

M8047

Multifunction module (18-bit addressing only on memory; the

AAV11

A6001

ADV11

A012

D/A converter (BC1 not used for BDAL18)
A/D converter (BC1 not used for BDAL18)

BDV11

M8012

memory can be disabled)

Options

Bootstrap/terminator (CS Rev D or later for use with KDF11-A, or
KDF11-B, EDD M8012-ML0002. CS Rev E or later for use in 22-bit

systems, ECO M8012-ML005)

2-18

DLV11-]

M8043

Serial line interface (CS Rev E or later for use with KDF11-A, or

DRV11-B

M7950

DMA interface (18 -bit DMA only)

KPV11-B,-C
KUV11
KWV11-A

M8016-YB,-YC
M8018

M7952

INSTALLATION

KDF11-B, ECO M8043-M8002)

Power-fail/LTC terminator (18-bit termination only)
WCS (For use only with KD11-B and KD11-BA processors)
Programmable real-time clock (BC1 not used for BDALI1 8)

Table 2-6 (Cont.):

Restricted or Non-compatible LSI-11 Options

Option

Module

Description

REV11

M9400

Terminator, DMA refresh, bootstrap (Bootstrap for use only with
KDF11-B and KD11-HA processors. Termination for 18 bits only.
DMA refresh may be used in any system.)

RKV11-D

M72609

RKO05 controller interface (16-bit DMA only)

RLV11

M8013 & M8014

RLO1, 2 controller (18-bit DMA only.

BC1 and BL1 not used for

BDAL18 and BDAL19. Requires CD-interconnect on C/D connectors.)

RXV21

M8029

RX02 interface (18-bit DMA only)

TEV11

M9400-YB

Terminator (18 bits only)

VSvil

M7064

Graphics display (18-bit DMA only)

Bus Cable Cards

M9400-YD

Cable connector (18-bit bus only)

M9400-YE

Connector with 240 Ohm terminators (18-bit bus only)

M9401

Cable connector (18-bit bus only)

Boot ROMs

MXV11-A2

Boot ROMs

MXV11-B2

Bool ROMs

2.5 KDJ11-D/S INSTALLATION
2.5.1 Pre-installation Considerations
Before installing a KDJ11-D/S in an existing or new system, the following must be considered:
e

The boot mechanism

18- or 22-bit addressing

Bus loading

Power requirements

Single or multiple box system

System differences (Section 2.5.2).
Note—Bus and Power Supply Loading
The ac and dc loading for the final configuration should be conform to the Q22-bus
loading rules. Power supply ratings should not be exceeded.

INSTALLATION

2-19

2.5.2 System Differences
Note—Parity Errors
A parity error on Q22-bus data is asserted during the current instruction cycle. A parity
error on local memory data is asserted during the next instruction cycle.

In addition to parity error assertion noted above, the following is a list of major KDJ11-D/S

features, for comparison with other processors using the DCJ11 chip.

On-board memory (0.5 Mbytes/1.5 Mbytes). (Optional, additional 3.5 Mbytes/2.5 Mbytes
accessible over Q22-bus.)
No cache memory.
On-board bootstrap and self-test ROM (32-kbyte or 64-kbyte).

Jumper or remote switch selectable bootstrap routine.
Two on-board DL-type serial line interfaces (console and general purpose).
Jumper or remote switch selectable serial line baud rate.

Jumper selectable halt-on-BREAK option.

Jumper selectable trap-on-HALT option.
Mechanization of LTC <07 > differs from other DCJ11-based processors.
Supports only Power-up mode 2 (bootstrap on power-up).

Q22-bus arbiter. Accepts only level 4 (BIRQ4) external interrupt requests.
No on-board diagnostic LEDs (seven lines are provided to drive remote indicators).
The FPA is not an option.

2.5.3 Instaliation Procedure
Caution—Memory Overlap
KDJ11-D/S on-board memory addresses are in the range 00000000 through 1777776.

Other system memory devices should not be configured to overlap this range. Bootstrap
does not check for such memory overlap; if it exists it may result in system disk

corruption.

The following guidelines should be followed when installing or replacing a KDJ11-D/S.

Verify that the correct dc power is available before installing the module.

Be sure that dc power is not applied to the backplane when removing or inserting the
module.
Verify the jumper configuration.
Install the KDJ11-D/S in backplane slot 1.

2-20

INSTALLATION

2.6 SPECIFICATIONS
Table 2-7 lists the physical, electrical, and environ

mental specifications for the KDJ11-D/S.

Table 2-7:

KDJ11-D/S Specifications

Physical Specifications

Module Number:

M7554

Module Type:

Q22-bus, quad-height

Dimensions:

Height: 26.56 cm (10.45 in)

Length: 30.25 cm (11.91 in)

Width:

Weight:

1.27 cm ( 0.50 in)

0.91 kg (32.0 oz)

Electrical Specifications
Power (early version):

+5.0 Vdc / 3.15 A (typical) 3.47
+12.0 Vdc / 0.17 A (typical) 0.19

A (maximum)
A (maximum)

Power (KDJ11-DA):

+5.0Vdc/2.50 A (typical) 2.80 A (maximum)
+12.0Vdec / 0.18 A (typical) 0.20 A (maximum)

Power (KDJ11-DB):

+5.0 Vdc / 2.90 A (typical) 3.20 A (maximum)
+12.0 Vdc / 0.17 A (typical) 0.19 A (maximum)

Power (KDJ11-SD):

+5.0 Vdc / 3.20
+12.0Vdc / 0.16

Bus Loading:

A (typical) 3.50

A (typical) 0.18

A (maximum)

ac: 3 unit loads
dc: 1 unit load

Environmental Specifications

Temperature
Storage Range:

Operating Range:

-40° to 66° C (-40° to 150.8° F)'

5° to 60° C ( 41° to 140.0° F)>

Humidity

Storage Range:
Operating Range:

10% to 95%
10% to 95% non-condensing

Altitude

Storage:
Operating;:

Airflow:

The moduleis neither mechanically nor electric

(16100 ft).

The module can be operated up to 2.4 km

ally damaged up to 4.9 km

(7900 ft).?

Provide adequate airflow to limit the inlet-t

the module to 10° C (50° F).

"Before operating a module that is not at an operating

modulein an operating range environment
for at least

o-ou tlet temperature rise across

range te mperature, stabilize its temperature by placing the

five minutes.

2De-rate maximum operating temperature 1.82° C/km (1.0°

F/3300 ft) above sea level.

INSTALLATION

2-21

Chapter 3

FUNCTIONAL DESCRIPTION
This chapter describes the functional areas of the KDJ11-D/S at the block diagram level. All
the block diagrams apply to both the early versions and the re-engineered versions of the
modules. The dashed lines show which functional units are contained within a gate array for
the re-engineered versions.

3.1

INTRODUCTION
The KDJ11-D/S CPU module is a quad-height, single-board computer for use in Q22-bus
systems. Based on the DCJ11 microprocessor chip, it executes the PDP11/73 instruction set

and includes the CPU, memory management, local memory, and I/O. The module does not
support cache nor an FPA (Floating-point Accelerator). Figures 3-1 and 3-2 are block diagrams

of the module showing the major functional areas and interconnections, for the early and reengineered versions. Note that most of the functional areas are connected to one or more of

five major sets of signals:
*

BUS STATE—signals to/from the Bus State-machine which controls Q22-bus cycle timing.

BUS LOGIC—signals to/from Q22-bus combinational (not including BDAL <21:00 > logic).

DAL<21:0>—22 data and address lines between the major functional areas.

LA<21:0>-—22 latched address lines (latched from DAL <21:0>).

CPU-—signals to/from the DCJ11 and its associated logic.

For earlier versions of the KDJ11-D/S (see Figure 3-1), most of the module’s functions are
implemented with large-scale integration, including PALs (Programmable Array Logic), PLAs
(Programmable Logic Array), and PLSs (Programmable Logic Sequencer).
The re-engineered
version of the KDJ11-D/S (see Figure 3-1) uses very large-scale integration to implement the
module’s functions, in the form of two gate arrays. These gate arrays are the DC7063 for control
functions, and the DC7064 for the data paths.

FUNCTIONAL DESCRIPTION

3-1

Figure 3-1:

KDJ11-DA Block Diagram

DAL 21:00

BUS

BuS

STATE

LOGIC

MACHINE

PLS
LA21:00

| ADDRESS

LATCH

DCJ11
CPU

Q22

‘-

BUS
XCVRS

15:00

BUS

21:16

—

- |—

PAR

CSRO

512

GEN

MUX [~

KBYTE

RAM

-»{

MEM

STATE
MACHINE

AlIO
—_

| — |||
o

ABORT —

—p

PAL

MEM

-»| DCD

—

o] PAL

——|—

PLS

DCD

RFR

—»

RER B

CTR

CLK

| — |—

STE —— |-

|—n

—
T N T

TEST
ROM

- DCD
PLA

seLr

]

ABORT—%

CyC
beco
pap

]

NATIVE

REW

REG

PAL

—_—
—_—

~—

—_—

—»
GP

ocD

MAINT

REG

—»

PAL

LTC
REG
—

L] y

—

le——

OLARTS

SWITCHES

<
—

LEDs

CONSOLE

1AK

PAL

PRINTER

VEC

—

GEN

PAL

MR-04856-0383

3-2

FUNCTIONAL DESCRIPTION

CONSOLE DLART

]<—>

lt—o SWITCHES

@ é

e I .

5 MB/1.5 MB

MEMORY

DCJ11

DAL<21:00>

|<——>~

—» LEDS

MICROPROCESSOR

PRINTER DLART

weiBeiqg yooig S/a-LLraX

~ |«~—=]

PR M

‘

15:00
>

<15:00>

:
»

Q-BUS

‘3

[NTER-

FACE

<21:00>

—-»| CONTROL GATE ARRAY

DATA PATH GATE ARRAY

€-¢€

l«——————— SWITCHES

DC7064

REGISTERS
o

VECTOR GENERATION

STATE MACHINES

PARITY GENERATION/CHECK

—

INTERRUPT

[
" REQUESTS

MEMORY

Q-BUS
CONTROL
Y

NOILdRIOS3d T¥YNOILLONNA

DC7063

Z-¢ eanBi4

—

DLARTS

PROM

RE3563

3.2 DCJ11 MICROPROCESSOR
Note—DCJ11 Information
For DCJ11 features not implemented in the KDDJ11-D/S, and more detail on features
described below, see the DC[11 MICROPROCESSOR USER’S GUIDE, EK-DCJ11-UG. The
following subsections are specific to the KDJ11-D/S.

The DCJ11 executes the PDP11/73 instruction set (see the Associated Documents listed in
the Preface), and controls the rest of the module. It initiates all KDJ11-D/S data transfers and
operations. The DCJ11 is a 60-pin VLSI chip. The input/output signals are shown in Figure 3-3

and described in Table 3-1.

Table 3-1:
Signal

DCJ11 Input and Output Signals
Description

Input Signals
RHALT

Receive Ialt—Asserted by either the console BREAK line (if jumper W11 is not
installed) or Q22-bus BHALT. HALT is the lowest priority non-maskable interrupt

except during vector read cycles when it is the highest priority.

LTC

Line Time Clock—(Event) Asserted by Q22-bus BEVNT (via the LTC Register). When
enabled and asserted, this priority level 6 maskable-interrupt causes the DCJ11 to trap

through vector address 100.

Parity Error—Asserted when a parity error is detected in local memory or Q22-bus

data.

PE also asserts ABORT (described below).

When both PE and ABORT are

asserted, a parity error abort is generated and the DCJ11 traps through vector address
114, without completing the current instruction.
PE is sampled only during the
stretched portion of a cycle. PE is asserted as follows:

Q22-bus data error—during the CURRENT instruction cycle.
Local memory data error—during the NEXT instruction cycle.
PWRE

Power Fail—Asserted when Q22-bus BPOK is deasserted, indicating an ac power
failure. This non-maskable high priority interrupt causes a trap through vector address

24.
IRQO

Interrupt Request 0—Asserted by Q22-bus BIRQ4 or a transmit or receive interrupt
request from either DLART. All such interrupts are level 4 priority interrupts.

Data Valid—Generated by the Bus State Machine and the Memory State Machine.
Latches DAL data into the DCJ11.

DCOK

DC power OK (INIT)—Asserted by Q22-bus BDCOK to initialize the DCJ11. DCOK
forces the DCJ11 to execute the power-up sequence.

RDMR

Receive DMA Request—Asserted by Q22-bus BDMR (and BPOK). The DCJ11 samples
RDMR at the start of all cycles.
If the cycle does not include a write operation, the DCJ11:
Stretches the cycle.

Places DAL<15:0> in the high-impedance stale.

3-4

FUNCTIONAL DESCRIPTION

Table 3-1 (Cont.):
Signal

DCJ11 Input and Output Signals

Description

Asserts MAP during the second part of the cycle, to acknowledge the request.
If the cycle includes a write operation, the DCJ11 stretches the cycle, but does not
place DAL<15:0> in the high-impedance state, and does not assert MAP.

CONT

Continue—Generated by the Bus State Machine and the Memory State Machine.
CONT is asserted by either of the state machines when it has finished using the

DALs. CONT terminates a stretched cycle (see SCTL, below), enabling the DCJ11 to
continue on to its next cycle.
XTAL<1:0>

Crystal—Input connections for the external 15.206 MHz (or 18 MHz) crystal oscillator.

Input/Output Signals
ABORT

Asserted either internally by the DCJ11, during the first part of a DCJ11 /O cycle; or

externally, during the stretched portion of a DCJ11 non-I/O cycle (see SCTL, below).
When ABORT is asserted:

Internally because a memory management error occurred,
through vector address 250.

the DCJ11 traps

Internally because an address error occurred, the DCJ11 traps through vector

address 4.

Externally by PE (above), the DCJ11 traps through vector address 114 (parity

error abort).

Externally by NXM (Non-existent Memory), the DCJ11
'

address 4.
DAL<15:0>

traps through vector

Data/Address Lines—These time-multiplexed 1/O lines are the 16-bit DCJ11 data and
address bus. During the first part of a DCJ11 /O transfer cycle, the type of cycle

determines what is on DAL<15:0>:

Bus Read or Bus Write—16 bits of physical address <15:0>.

GP Read or Write—8-bit GP code <7:0>.
Interrupt Acknowledge—priority level <3:0>.
During the second part of an 1/O transfer cycle, DAL<15:0> carry 8 or 16 bits of

data. On read cycles, external logic asserts the lines. To read a byte, the DCJ11 reads
the full word, but ignores the unwanted byte. On write cycles, 16 lines are asserted
to write a word, and 8 lines are asserted to write a byte.

FUNCTIONAL DESCRIPTION

3-5

Table 3-1 (Cont.):
Signal

DCJ11 Input and Output Signals

Description

Output Signals
JDAL<21:16>

Data/Address Lines—These six time-multiplexed output lines are the six most significant bits of a 22-bit physical address. The address is valid at the start of every
DCJ11 bus cycle. During the second part of the cycle, internal status is asserted on

JDAL<21:16> (for manufacturing test).
ALE

Address Latch Enable—Asserted to indicate that MAP, DAL<21:0>, AlIO<3:0>, and

STRB

Strobe—Asserted one clock period after ALE is asserted. The deassertion of STRB is

MAP

BS<1:0> are all valid. Used by external logic as a latch enable.
the end of one microcycle and the start of another.

Map Enable—Time-multiplexed.

Asserted during the first part of a cycle to set

MMR3<5> and enable the external /O map (not used in the KD]11-D/S). Asserted

during the second part of a cycle to acknowledge assertion of input RDMR.
SRUN

(Predecode) Asserted to indicate that the contents of the DCJ11 PB (Prefetch Buffer)
are valid and being decoded. In the KDJ11-D/S it is wired to backplane pin AF1, to
drive a remote RUN-indicator.

AlQ<3:0>

BS<1:0>

CLK2

Address Input/Output—The code asserted on these lines identifies the type of the

current DCJ11 cycle. See Table 3-2.

Bank Select—Time-multiplexed. During the first part of a DCJ11 Bus Read or Bus
Write cycle, BS<1:0> identify the type of device being physically addressed on
DAL<21:0>. See Table 3-3. During the second part of a DCJ11 /O cycle, BS<1:0>
carry cache access information (not used by the KDJ11-D/S).

Clock 2—The system clock for external logic. CLK2 has the same frequency as the

oscillator connected to XTAL<1:0> inputs, and the same state of the DCJ11 internal
clock.

SCTL

Stretch Control—Asserted during the stretched portion of a DCJ11 cycle. Used to:
Latch data with the leading or trailing edge of SCTL during write cycles.
Enable externally generated ABORTSs.

SCTL is deasserted when input CONT (above) is asserted.
BFCTL

Buffer Control—Asserted when the DCJ11 is not driving the DAL lines. This occurs
during the portion of a read cycle when data is on the DAL lines and during the
stretched portion of any non-write cycle. Not asserted when the DCJ11 is driving the
DAL lines.

3-6

FUNCTIONAL DESCRIPTION

Figure 3-3:

DCJ11 CPU

Q22 BUS

>
RSYNC

—RSACK

pcroesa

DCJ11 CPU

PARITY

- A

—

]

PARITY

HALT

STRB

PW RF

PWRF

ABORT
¢

LTC
‘

ALE

RHALT

EVENT

IRQO

MAP

IRQO

> MAP

—» ABORT
g
>

PRDC

Al03:0
DLARTS

ALE

» STRB

SRUN

- A|03:0

BS1:0

CLK2

—»

CLK2

SCTL

BFCTL

DAL21:16

— » JDAL21:16

| DAL15:0 «—{¢ DAL15:0

————

DC7063

]

MEMAND | |
BUS

MACHINES

DECODER

INIT

ol oy

CONT

CYCLE

DCO K

RDMR

I
[

CTALT

DRVR

15.206 MHz
1

——xTaL0

ENJDAL

Y——

»DAL21:16

RE3673

FUNCTIONAL DESCRIPTION

3-7

AlO0O<3:0> Codes

Table 3-2:
Al0

Cycle

1111

NIO

Non-1/0O, DCJ11 internal operation

1110

GP Read

1101

IAK

Interrupt acknowledge, vector-read

1100

Bus Read

Instruction stream request-read

1011

Bus Read

RMW (read/modify/write), no bus lock

1010

Bus Read

RMW, bus lock

1001

Bus Read

Data stream read

1000

Bus Read

Instruction stream demand-read

0101

GP Write

GP word-write

0011

Bus Write

Bus byte-write

0001

Bus Write

Bus word-write

Table 3-3:

BS<1:0> Codes

Device

Internal Register—DC]J11 internal, memory-addressable registers, including the PSW, PIRQ, CPU
Error, MMU, and Hit/Miss' registers.

External I/O Device—Any device or register external to the DCJ11 and resident in 17760000

through 17777777 (the 1/O Page), but excluding internal and system registers (BS<0> = 1).2

0 1

System Registers—Memory-addressable registers in the range 17777740 through 17777750.

0 0

Memory—Any location in the physical address space in the range 00000000 through 17757777
(below the 1/O Page).

IThe Hit/Miss register is not used in the KDJ11-D/S.
2The Maintenance Register (17777750) is accessible as both an External I/O Device and a System Register.

3.2.1 DCJ11 Cycles
The DCJ11 executes six basic types of cycles (see Table 3-2). These cycles (also called
“‘microcycles’”” and “’bus cycles’’) are classed according to the type of activity on DAL<16:0>
(also called the “1/O Bus”’). Each microcycle is associated with the execution of one DCJ11
microinstruction. The execution of one DCJ11 macroinstruction (that is, PDP11 instruction)
can require several microcycles. The basic DCJ11 cycles are:

3-8

FUNCTIONAL DESCRIPTION

NIO (non-I/Q)

Bus Read

Bus Write

GP Read

GP Write

Interrupt Acknowledge

A cycle starts (and ends) when STRB is deasserted. All cycles require at least four clock
periods; however, cycles can be extended, or stretched, by an internal event or external logic.
When stretched, a cycle is extended for at least four clock periods; beyond that, a cycle can

be stretched indefinitely in increments of two clock periods. SCTL is asserted at the start of
the stretched portion of the cycle. A stretched cycle is ended when CONT is asserted.
A cycle will not be stretched if it is an NIO cycle, and RDMR is not asserted during the cycle.

The “first”” or “early” part of a cycle is defined as the first two clock periods of the cycle. The
“second” or “late”” part of a cycle is the remaining clock periods—two in a normal cycle, six
or more in a stretched cycle.

The DCJ11 asserts a code for the current cycle on AIO<3:0> (see Table 3-2). The AIO
Decoder (Section 3.3) decodes AlO<3:0>, and generates signals to control other module
functions. The DCJ11 cycles are described in the following sections.

3.2.1.1 NIO
During an NIO (non-I/O) cycle the DCJ11 is performing an internal operation, and is not using
DAL<21:0>. The cycle is stretched if RDMR is asserted.

3.2.1.2 Bus Read
These cycles include:
*

Instruction siream request-read or demand-read.

The DCJ11 executes a request-read to prefetch information. All other types of reads are
demand-reads. If external logic generates an abort during a request-read, macroinstruction
flow is not affected (the abort is ignored). Aborts generated during a demand-read or
by on-board logic during a request-read are recognized and serviced through the vectors
listed in Table 1-15.
*

Read/modify/write (read portion).

An AlQ read code is asserted during the first part of the cycle. The second part of the
cycle is a Bus Write cycle with a different AIO code asserted.
¢

Data stream read.

The DCJ11 asserts BS<1:0> to identify the type of device being read as either an 1/O device,

memory, or a memory-addressable register. The DCJ11 always reads a full word, and ignores

the unwanted byte if necessary. The cycle will be stretched for any of the following conditions.
*

Anything other than a memory reference (BS<1:0> not = 00).

DMA grant (MAP is asserted during the second part of the cycle).

FUNCTIONAL DESCRIPTION

3-9

ABORT is asserted during an instruction stream demand-read, data stream read, or readmodify-write cycle.

The DCJ11 latches the read data at the start of the third clock period or when DV (Data Valid)
is asserted during the stretched part of the cycle.
3.2.1.3 Bus Write

These are either word-write or byte-write cycles. The DCJ11 asserts BS<1:0> to identify
the type of device being written as either an I/O device, memory, or a memory-addressable
register. The DCJ11 drives all 16 bits of DAL<15:0> for byte-write cycles. The address
specifies which byte has valid data; data in the other byte is undefined. All Bus Write cycles
are stretched. The write data is valid when SCTL is asserted.

3.2.1.4 GP Read

The DCJ11 executes this cycle to read the low byte of the Maintenance Register; that is,
power-up mode, HALT/trap option, POK (Power OK), and module type number. The DCJ11
asserts a GP code on DAL <7:0> (see Table 3-4). This code is decoded by the GP DECODER
(Section 3.4). The DC]J11 reads a full word; however, the high byte is driven to zero by external
logic, and ignored by the DCJ11. The GP Read cycle is always stretched. The DCJ11 latches
the data at the start of the third clock period or when DV (Data Valid) is asserted during the
stretched part of the cycle.
Table 3-4:

GP Codes

Code'

Type

Function

000

READ

Power-up mode, HALT/trap option, POK

002

READ

Power-up mode, HALT/trap option, POK

214

WRITE

Negate INIT

014

WRITE

Assert INIT

100

WRITE

Acknowledge BEVNT

140

WRITE

Acknowledge PWRF

"Unlisted codes are not implemented in the KDJ11-D/S

3.2.1.5 GP Write
The DCJ11 executes this cycle to:

(Clear the Event interrupt enable flip-flop.

Assert or negate Q22-bus BINIT.

(lear the Event interrupt request flip-flop.

(lear the power-fail flip-flop.

The GP code asserted on DAL<7:0> (Table 3-4) during the first part of the cycle is decoded
by the GP Decoder (Section 3.4). The cycle is always stretched. The GP Write data can be
either a word or byte, and is asserted in the stretched part of the cycle. The write data is valid
when SCTL is asserted.

3-10

FLUNCTIONAL DESCRIFPTION

3.2.1.6 IAK
This cycle is also called a “‘vector read cycle,” and is executed
to service an interrupt request on
IRQO. The DCJ11 asserts the bit-encoded acknowledged level on DAL<3:0
> in the first part
of the cycle (for IRQO, DAL<3:0> = 0001). The cycle is always stretched.
The interrupting
device asserts the interrupt vector on DAL<15:0>, during the stretched
part of the cycle.
The DCJ11 latches the vector at the start of the third clock period or
when DV (Data Valid) is

asserted during the stretched part of the cycle. External logic
can abort the cycle during the
stretched part of the cycle. If ABORT is asserted, the DCJ11 ignores
the interrupt request and
continues processing.

3.3 AlO DECODER
Figure 3-4 shows the AIO Decoder. Its inputs are:
1.

AlO<3:0> from the DCJ11, to determine the current DCJ11

RSACK. A Q22-bus DMA device asserts BSACK to acknowle
dge bus mastership when it
has received a DMA grant (BDMGO) from the KDJ11-D/s.

RBS7. A bus master asserts Bank 7 Select (BBS7) along with DAL<12:
0> to reference a
location in the I/O Page.

cycle (see Table 3-2).

FUNCTIONAL DESCRIPTION

3-11

Figure 3-4:

AIO Decoder

_—:

l_;)c7063/DC7064
|

—» MEMSEL

|
|

RBS7 l.

|—

T heAkTM

NXM

PARITY

‘

ABORT —

—| D

R —» IOSEL

¢
>

R
READ
R —» DEMAND

R —» GP

TM0
D

SFH—*| D

R }—» BYTE

R — BUS

A|03:0|——

OF——» D

R IAK

DCJ11

CPU

{

R —» rRMW

> D

| —

|
|

LATCH

DECODER

AS—®1

HOLD
EN

|
|

RE3674

Table 3-5 describes the conditions for asserting the AIO Decoder outputs. The AIO Decoder
outputs are latched by AS (Address Strobe—see Figure 3-3).
NOTE
The AIO decode logic is implemented in both gate arrays.

3-12

FUNCTIONAL DESCRIPTION

Table 3-5:

AIO Decoder Outputs

Output

Conditions

MEMSEL

Memory Select—Asserted for all Bus Read and Bus Write cycles. MEMSEL is a direct input
to the Memory Decoder, and a latched input (IOSEL) to the 1/O Decoder. MEMSEL can only

be asserted if RSACK is not asserted. MEMSEL is not asserted:
For NIO, IAK, GP Read, or GP Write cycles.
[f ABORT is asserted.

If both RSACK and RBS7 are asserted (that is, a Q22-bus device is attempting a DMA
reference to the 1/O Page).

Note—Q22-bus References to On-board I/0
All Q22-bus device references to on-board 1/O devices are illegal.
READ

Asserted for all Bus, 1AK (vector), and GP read cycles. Note that the complement of READ
(that is, -READ) can be interpreted as a write cycle signal (see Table 3-9).

DEMAND Asserted for all cycles except NIO, GP Read, and Instruction Stream Request-read.

General Purpose—Asserted for GP Read and GP Write cycles.

BYTE

Asserted only for a Bus Byte Write cycle.

BUS

Asserted for all bus read and write cycles.

RMW

Read/Modify/Write—Asserted for both RMW cycles.

IAK

Interrupt Acknowledge (vector read)—Asserted only for an 1AK cycle.

3.4 GP DECODER
Figure 3-5 shows the General Purpose Decoder. It decodes LA<7:0>; that is, the latched
DAL<7:0> value, asserted in the first part of a GP cycle (Table 3-4). The GP Decoder outputs
are described in Table 3-6. Note that signals INIT H and INIT L are both outputs and inputs
(feedback), and are complements of each other.

FUNCTIONAL DESCRIPTION

3-13

Figure 3-5:

GP Decoder

16-BIT
LATCH

DAL15:0

DCJ11

HOWD |

cpPU

R
EN

> LA15:0

———— i
/=
P————

SCTL

BFCTL

!
H

DC7064

La7.0

| DECODER

—» pvoDE

O = INTH
o INITL

® | ACKLTC

[A©

LOGIC

& > ACKPF

l
|

|
|

B INITH

|
|

]
RE3675

Table 3-6:

GP Decoder Outputs

Output

Conditions

PMODE

(GP code 000 or 002) Power-up Mode—Asserted during the stretched part of a GP’ Read cycle.
It is one of the inputs which setsup the /O Read/Write logic (Section 3.8) to read Maintenance
Register <07:00> (Module Type, Halt/Trap Option, Power-up Mode, and POK—see Table
1-6).

INIT

(GP code 214)—Asserted during the stretched part of a GP Write cycle. It asserts Q22-bus
BINIT, clears certain DLART register bits (see Section 1.2.7), and is part of the clear input to
the DMG (DMA Grant) flip-flop. Cleared by GP code 014.

INIT

(GP code 014)—Asserted during the stretched part of a GP Write cycle. 1t clears Memory
Error Register<15:14> and <02:00> (Table 1-24) and the Event Interrupt Enable flip-flop.
Cleared by GP code 214,

ACKLTC

(GP code 100) Acknowledge 1.TC—Asserted during the stretched part of a GP Write cycle. It
clears the Event Interrupt Request flip-flop. Also asserted by INIT L.

ACKPF

(GP code 140) Acknowledge Power-fail—Asserted during the stretched part of a GP Write
cycle. It clears the PWRF (Power-fail) flip-flop. Also asserted by INIT L.

3.5 MEMORY DECODER
Figure 3-6 shows the Memory Decoder. It decodes BS<1:0> (Table 3-3) and DAL<21:9>
to generate three outputs which are part of the logic to select either on-board ROM, on-board
RAM, or Q22-bus memory (Table 3-7). All the Memory Decoder outputs are latched by AS
(Address Strobe—see Figure 3-3).

3-14

FUNCTIONAL DESCRIPTION

Figure 3-6:

Memory Decoder

022 BUS

| DC7064

-I

MEM

DECODER

DAL21:9

AIO

DECOD

RSACK

NATIVE
REG

MEMSEL

STE
BS1:0

|
|

— RAMSEL

|
|

LATCH

ggd”

[

* ROMSEL

> QSEL

8-BIT

———————————

}

DECODER

562 —#

+ RAM

» oBUS

IT'

» L A18:16

» ROM

> LBS10

HOLD

e OBUS

e acve

ACKQ

o RO

—

QIO PAGE

}>acyc

|
|
RE3676

Table 3-7:

Memory Decoder Outputs

Output

Conditions

ROMSEL

ROM Select—Asserted when:
The bootstrap is referenced:
BS<1:0> = 10 and
DAL<12:9> = 13 and

MEMSEL is asserted, and RSACK is not asserted.

Self-test ROM is referenced:
DAL<21:17> = the range 17400000 through 17777777 and

BS<1:0> = 00 and
Native Register<07> = 1 (STE) and
MEMSEL is asserted, and RSACK is not asserted.

FUNCTIONAL DESCRIPTION

3-15

Table 3-7 (Cont.):

Memory Decoder Outputs

Output

Conditions

RAMSEL

RAM Select—Asserted when On-board RAM is referenced:
BS<1:0> = 00 and

DAL<21:19> = the range 00000000 through 01777777 (00000000 through 5777777 if 1.5

Mb of RAM) and

MEMSEL is asserted, and RSACK is not asserted.

DAL<21:19> = the range 00000000 through 01777777 (00000000 through 5777777 if 1.5
Mb of RAM) and both
MEMSEL and RSACK are asserted.

QSEL

Q22-bus Select—Asserted when:

MEMSEL is asserted, and RSACK is not asserted and
BS<1:0> = 00 and
Q22-bus memory is referenced:
DAL<21:19>

the range 02000000 through 17377777 (0.5 Mbyte modules)

DAL<21:19> = the range 06000000 through 17377777 (1.5 Mbyte modules)
or

DAL<21:17> = the range 17400000 through 17777777 and
Native Register<07> = 0 (not STE).

QSEL is not asserted for the same input conditions that assert ROMSEL and RAMSEL. In

addition, QSEL is not asserted anytime that:
RSACK is asserted or

MEMSEL is not asserted or
BS<1:0> = 01 or 10 or 11,

3.6 1/0 DECODER
The 1/O Decoder, Figure 3-7, is an 825100 PLA. It performs the initial selection to access a
specific External 1/O Register, or System Register (Maintenance Register). It also prevents Q22bus devices from accessing these registers, the bootstrap, and internal registers by inhibiting
QIOPAGE (see Table 3-8).

3-16

FUNCTIONAL DESCRIPTION

Figure 3-7:

/O Decoder

{

Q22BUS

)

DC7064

DECODER

L RSACK —
AIO

DECODER

ADDRESS

MEMORY

IDSEL

—» LIO

—*

—® MER
—» NR
—

RLTC

—® MAINT

—T® DLO

DECODER }——— | BS1:0 —

LATCH

(CONSOLE)

> DL
T QIOPAGE

I
|

SG2 —»

I7DLO(CONSOLE)

:; QIO PAGE

RE3677

Table 3-8:

1/O Decoder Qutputs

Output

Conditions

LIO

Local I/QO—Asserted when:

IOSEL is asserted and RSACK is deasserted, and either:
BS<1:0> = 11
or

Any of the following outputs are asserted: MER, NR, RLTC, MAINT, DL1, DLO
MER

Memory Error Register select—Asserted when I0SEL is asserted and RSACK is not asserted,

and:

BS<1:0> = 10.
DAL<12:1> = 12100.

Native Register select—Asserted when IOSEL is asserted and RSACK is not asserted, and:

FUNCTIONAL DESCRIPTION

3-17

Table 3-8 (Cont.):
Output

1/O Decoder Outputs

Conditions

BS<1:.0> = 10.
DAL<12:1> = 17520.
RLTC

Read LTC select—Asserted when IQSEL is asserted and RSACK is not asserted, and:
BS<1:.0> = 10.
DAL<12:1> = 17546.

Note that this signal is used as enable for both reads and writes (see the /O Read/Write
Decoder, Table 3—-10).

MAINT

Maintenance Register select—Asserted when IOSEL is asserted and RSACK is not asserted,
and:

BS<1:0> = 01.
DAL<12:1> = 17750.
DL1

DLART 1 select—Asserted when I0QSEL is asserted and RSACK is not asserted, and:
BS<1:0> = 10.
DAL<12:3> = 1650.

DAL<2:1> select the specific DLART register.
DLO

DLART 0 select—Asserted when 10SEL is asserted and RSACK is not asserted, and:
BS<1:0> = 10.
DAL<12:3> = 1756.

DAL<2:1> select the specific DLART register.
QIOPAGE

Q22-bus 1/O Page reference—Deasserted when any of the above are asserted. That is, a Q22bus device cannot reference any of the registers resident in the 1/O Page. QIOPAGE is also
not asserted when any of the following conditions exist:
RSACK is asserted.
IOSEL is deasserted.
BS<1:0>
11 or 00.

BS<1:0> = 10 and DAL<12:9> = 13.

QIOPAGE is asserted when IOSEL is asserted and RSACK is not asserted, and:
BS<1:0> = 10.
DAL<12:9> = none of the above addresses.

3.7 CYCLE DECODER
Figure 3-8 shows the Cycle Decoder. Three of its outputs define the type of operation
performed on the devices selected by the I/O Decoder. In addition, the CYCLE output is
used in the Memory State Machine as part of the logic to exit its Idle loop and enter one of

its major sequences. The Cycle Decoder also provides the output enable for DAL<21:16>
(latched JDAL<21:16> from the DCJ11).

3-18

FUNCTIONAL DESCRIPTION

Figure 3-8:

Cycle Decoder

rT)C7063/DC7064

CYCLE

fiETDCZEss L

LAD——

:;\EKCODER L VHB ————>]

DECODER

:DOECODER L L0 ——

|
L~

lowLB

|—>

IOWHB

& |—»> IOREAD

—>

CYCLE

> ENJDAL

P — &

DECODER
YTE
|latcw
|— BUS ——

— READ ———>

| | MEMORY

DCJ1
cPU

— BFCTL

|DECODER|— ROM —»0
LATCH
'

PARITY [~ ABORT |

—

— SCTL

NXM

"1®

|
__
RE3678

Table 3-9:

Cycle Decoder Outputs

Output

Conditions

IOWLB

1/O Write Low Byte—Asserted when SCTL and LIO are asserted, and either:
BYTE is asserted (byte only), and
READ and LAQ are not asserted (write low byte).
or

READ and BYTE are not asserted (write word).

IOWHB

1/O Write High Byte—Asserted when SCTL and LIO are asserted, and either:
BYTE and LAQ and are asserted (high byte only), and
READ is not asserted (write).
or

BYTE and READ are not asserted (write word).

FUNCTIONAL DESCRIPTION

3-19

Table 3-9 (Cont.):

Cycle Decoder Outputs

Output

Conditions

IOREAD

Asserted to read a byte or word when SCTL and BFCTL. are asserted, and either:
LIO is asserted (register read).
or

ROM is asserted (ROM read).

CYCLE

Asserted for all the above conditions. That is, any time that LIO or ROM is asserted to access
External 1/O Registers, Internal Registers, System Registers, or ROM. Also asserted when:
VHB is asserted (see IAK Decoder, Table 3-11).

GP is asserted (GP read or write—see GP Decoder, Table 3-6).

ABORT is asserted.

ENJADD

Asserted when both SCTL and BFCTL are not asserted (includes the IOWLB, ITOWHB, and
IOREAD conditions above).

3.8 1/O0 READ/WRITE LOGIC
Figure 3-9 shows the 1/0O Read/Write logic. All but one of its outputs are enables to read or
write either the Maintenance, LTC, Memory Error, or Native register. Its ZHB output grounds
the inputs to DAL<15:8> when the Maintenance or LTC registers or an inlerrupt vector is
being read.

3-20

FUNCTIONAL DESCRIPTION

1/0 Read/Write logic

DC7064

DECODER

RLTC
NR

MER

l
|

GP
DECODER

PMODE

IAK

VHB

DECODER

CYCLE

IOWLB
IOWHB

—» MAINTRD

> LTCWLB

REW

—— MERWT

MAINT

—J—D NRRD

—» NRWLB

—® LTCRD

—® MERRD

——» ZHB

I S|

Figure 3-9:

NRRD

RE3€79

Table 3-10:

1/0 Read/Write Logic Outputs

Output

Conditions

MAINTRD

Maintenance Register Read—Asserted when either:
IOREAD and MAINT are asserted, or
PMODE is asserted (see GP Decoder, Table 3-6).

LTCRD

LTC Register Read—Asserted when IOREAD and RLTC are asserted.

LTCWLB

LTC Register Write Low Byte—Asserted when IOWLB and RLTC are asserted.

MERRD

Memory Error Register Read-—Asserted when IOREAD and MER are asserted.

MERWT

Memory Errot Register Write—Asserted when IOWLB and MER are asseried.

NRRD

Native Register Read—Asserted when IOREAD and NR are asserted.

NRWLB

Native Register Read—Asserted when IOWLB and NR are asserted.

FUNCTIONAL DESCRIPTION

3-21

Table 3-10 (Cont.):
Output

/0O Read/Write Logic Outputs

Conditions

Zero High Byte—Asserted when the Maintenance or LTC registers are read, and when VHB

ZHB

is asserted for a vector read.

3.9 IAK DECODER AND VECTOR GENERATION LOGIC
Figure 3-10 shows the Input Acknowledge Decoder and Vector Generation Logic. The basic
sequence of operation is:

When either (or both) of the DLARTS asserts (high) an interrupt request (DLORX, DLOTX,
DLIRX, DL1TX), IRQO is asserted to the DCJ11, requesting an interrupt.

For the rest of this sequence, assume DLORX is asserted.

1.
2.

Eventually, the DCJ11 will execute an IAK—Vector Read cycle, causing the AIO Decoder

to assert IAK.

IAK does two things:

it latches DLORX

it's ANDed with BECTL from the DCJ11 to assert VEC.

In the IAK Decoder:

Latched-DLORX asserts VHB (Vector High Byte) high.

VEC,VHB (feedback), and latched-DI.ORX deassert the corresponding output (that is,
-DLORX is asserted low). This pulls the DLORX line (from the DLART, not from the
latch) low.

c.
4.

Assuming there are no other requests pending, IRQO is deasserted.

In the Vector Generator:

Both VEC and VHB must be asserted to enable any of the outputs.

Latched-DLORX asserts (high) DAL<5:4>; that is vector address 60.

Note that the IAK Decoder is mechanized so that the four DL outputs are either not asserted
and in the high-impedance state, or asserted low, negating the DL input from the DLARTS.
In addition, the mechanization is such that the requests are prioritized:
DLORX highest
DLOTX
DLIRX
DL1TX
QBIRQ lowest

If the interrupt request is a Q22-bus level 4 request, QBIRQ is asserted, asserting IRQQ. In this
case, the request is not latched, but IAK and BFCTL assert VHB as in 3.b. above. Assuming
neither DLART is requesting an interrupt, only IAK Decoder output ACKQ is asserted and

input to the Q22-bus State Machine.

3-22

FUNCTIONAL DESCRIPTION

8-BIT

NOILdRIDS3d TYNOILDONNA
£€C—€

»-

& —L— paLo

OF——>npAL1

S—Lw»pa2

O——=opa3

SIEOCODER

LATCH

IAK

HOLD

Sl—L—=pas

"
o

secTL

CPU

L1
o paLy

DECODER

DLITX

DLORX _ |
DL1RX

DLART1

PAL

LATCH

DLOTX

GEN

DLARTO

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—:
VECTOR

}

Of——wDAL5

> DALE
» \VHB

ACKQ

DAL7
DALO
DAL1

DAL2
DAL3

DAL4

DALS

DALG6

- ACKQ

AND
»

VEC
I

|
IRQO

Q22 BUS

QBIRQ

|
|

!
|

|
|

|
——————————————————————————————————————————

—

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Table 3-11:

|AK Decoder Outputs

Output

Conditions

VHB

Vector High Byte—Asserted when any DLART interrupt request is asserted.

DLORX

DLART 0 Receiver Interrupt Request—Deasserted low (-DLORX is asserted) when VEC, VHB,
and latched-DLORX are asserted. When not low, this line is in the high impedance state.

DLOTX

DLART 0 Transmitter Interrupt Request—Deasserted low (-DLOTX is asserted) when VEC,
VHB, and latched-DLOTX are asserted, and DLORX is in the high impedance state. When not
low, this line is in the high impedance state.

DL1RX

DLART 1 Receiver Interrupt Request—Deasserted low (-DLIRX is asserted) when VEC, VHB,
and latched-DLIRX are asserted, and DLORX and DLOTX are in the high impedance state.
When not low, this line is in the high impedance state.

DLITX

ACKQ

DLART 1 Transmitter interrupt Request—Deasserted low (-DLITX is asserted) when VEC,
VHB, and latched-DL1TX are asserted, and DLORX, DLOTX, and DLIRX are in the high
impedance state. When not low, this line is in the high impedance state.
Acknowledge BIRQ—Asserted when VEC is asserted and latched-DLORX, latched-DLOTX,
latched-DL1RX, and latched-DL1TX are all deasserted.

Table 3-12:
Vector

Vector Generation logic Outputs

Conditions

DAL<5:4> = H. Asserted when VEC, VHB, and latched DLORX are asserted.

DAL<5:4> and <2> = H. Asserted when VEC, VHB, and latched DLOTX are asserted.

300

DAL<7:6> = H. Asserted when VEC, VHB, and latched DLIRX are asserted.

360

DAL<7:6> and <5:4> = H. Assgerted when VEC, VHB, and latched DL1TX are asserted.

3.10 MEMORY STATE MACHINE
Figure 3-11 shows the Memory State Machine. All the inputs and outputs are used.
The logic states define four major sequences:

Refresh

Local I/O

3-24

Write

Read

FUNCTIONAL DESCRIPTION

LA<2019>

LATCH

CYCLE

STATE

MACHINE

}
|

DCJ11
CPU

DECODER

BUS

—» RAS

QWRITE

» QDV

» MEMDV

» RWRITE

> REFADD

RAM

F/F
+3v—+{D

F/F
1

— CLK

NOILdRDS3d TYNOILONIA

MEM
DECODER

»{ CLR

F/F
1

—»{D

CLK

CLR

L CLR

|
|

oLx

DMG

—

MPE

—

acye

—

LAO

|
I

ol clK

|
—> REFRESH

BIN CTR

|
BT

—f

|
|

[
[

——

»f CLK

AND

|
|

CLR

= RFADD

> REFREQ

CAS<5:0>

|——= RAS

CAS

> LB

—» MEMCONT

CLK2,

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READ

614 KHz

\nD

» HB

SCTL |

DCOK.L

f——e COLL

CAS

BUS

r
—

STATE
QREAD
MACHINE | QBYTEWRITE _

60 ns b——

» COLSEL

20 s

MEM

DELAY

——————————— —]l

—

I
|

AND

+ DLCLK

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3.11 BUS STATE MACHINE
The Bus State Machine, Figure 3-12, consists of two parts, a Master and a Slave.
There are three Master/Slave interconnections. Slave output QCONT is input to the Master,
and Master outputs TDIN and TDOUT are input to the Slave. Slave output QREAD is fed
back to its input.

The bus state machine implements the functions of a Q22-bus arbiter and generates the signals
required of a Q22-bus master and slave device, including:
TSYNC—Transmit SYNC
TDIN—Transmit Data In
TDOUT—Transmit Data Out
TIAK—Transmit Interrupt Acknowledge
TDMG—Transmit DMA Grant
TRPLY—Transmit RPLY

Note—Q22-bus or Local Memory
The KDJ11-D/S setsup the address portion of a Q22-bus transaction for every memory
In the Master state machine, TSYNC is asserted only for a Q22-bus
reference.

transaction. If the memory address is an on-board reference, TSYNC (and BSYNC)
will not be asserted, effectively aborting the bus transaction.

3.12 SACKTIMEUP, NXM, BBS7, BTWT
This section describes the SACK time-out timer, and the mechanization for BBS7 and BWTBT
(Figure 3-13).

3.12.1 SACKTIMEUP and NXM
The SACKTIMEUP counter is a 16-state binary counter. It starts counting as soon as the clear
input is removed; that is as soon as the Bus State Machine Master asserts either TDIN, TDOUT,
or TDMG. The counter is clocked by the 614.4 kHz oscillator. As soon as the counter reaches
state 8, SACKTIMEUP is asserted. In other words, SACKTIMEUP is asserted approximately
13 us after the counter is started.

NXM (Non-existent Memoty) is asserted if RRPLY is not asserted within 13 us after TDIN or

TDOUT is asserted.

A NXM error asserts ABORT (see Figure 3-14).

3.12.2 BBS7 and BWTBT
At the start of a bus transaction, the bus master asserts the slave device address, BBS7
to reference the 1/0O Page, and either asserts or deasserts BWTBT to indicate the type of
transaction. During the address portion of a bus transaction, the Bus State Machine Master
asserts JDATALTCH which selects the ‘1" inputs to the BBS7/BWTBT input multiplexer.

BBS7 is asserted if the I/O Decoder has asserted QIOPAGE (Table 3-8). That is, the device

address is in the [/O Page (but not a KDJ11-D/S register address).

BWTBT is asserted if the AIOQ decoder has not asserted READ (Table 3-5). That is, the
transaction will be a data-out (or write) transaction. If READ is asserted, BWTBT is deasserted.
When JDATALTCH is not asserted, BBS7 is deasserted, and BWTBT is either asserted or
deasserted by BYTE from the AlO Decoder, to indicate a byte or word transfer.

3-26

AIO

RMW

|
|

MASTER

l
|

DC7064

I—————_——

MEM

DECODER

DMG

_‘

SYNC

NXM

—_—
e e
|

I_ _____ —_—

READ

RMW

—» QBDV

BUS

—» TDOUT

QIOPAGE

RRPLY

STRB
SCTL
ACKQ

QBUS

SLAVE

DV
Qbv

RAM

RSACK

RDOUT

—> SLAVE
—» QBYTEWRITE

]

* QREAD

LWTBT
RSYNC

CLK2

DCOK

|
I

—

+ TRPLY

1 > TRANSO E

RWTBT

-+ QCONT
— QWRITE

RRPLY

ROIN

TIAK

JDATALTCH

TDIN

RSACK

|
I

-» QBCONT

_‘

SACKTIMEUP

AND

QDV

MEMDV

MACHINE

| state

lw}

MEM

DMG

T??TI_—_——I“_"“'""

1 p——%
i CLK

INIT

ALE

CLK
OE

—_—]

Bus State Machine

Figure 3-12:

+ QRCVOE

RE3683

FUNCTIONAL DESCRIPTION

3-27

ciorace

I
l

READ

/SIEOCODER

BYTE

JDATALTCH

BUS

STATE

)
|

' :;

%] SEL
oF

SLAVE
RPOK

hetNET

T
E

B
R

leBROUT

>»E

XCVR BBS7

[

MACHINE

8641

AND

l
I
|

TDOUT

TDIN

TOMG

I
|

+ RBS7

l
'

—_— e

; + RDIN

' .| AND
OR

_—

CTR

R3 |

> NXM

SACKTIMEUP

CLK
e

I
|, RDOUT

—» T B et

l DLCLK
|

o qwrer

RRPLY

]

Q22 BUS

———

DC7063

——»

AND

:
BDMGO

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3.13 PARITY AND ABORT
Parity is generated on all data written into RAM, and parity bits 16 and 17 are set accordingly.
See Figure 3-14. If the low byte, DAL<7:0>, has an even number of bits, PDI16 (Parity Data
In) is asserted. If the high byte, DAL<15:8>, has an odd number of bits, PDI17 is asserted.
When RAM is read, PDO16 and DAL<7:0> should contain an odd number of bits. If not,
ERROR is asserted. Similarly, PDO17 and DAL <15:8> should contain an even number of
bits; an odd number of bits will assert ERROR.
A parity error asserts ABORT and PE to the DCJ11 (Table 3-1). For DCJ11 reads, a RAM
parity error causes an unmaskable interrupt through vector 114. For Q22-bus controlled RAM
reads, parity errors are reported by asserting DAL<17,16>.

Note—Parity Errors
A parity error on Q22-bus data is asserted during the current instruction cycle. A parity
error on local memory data is asserted during the next instruction cycle.

Parity detection is enabled by MER<00> (CSR<0>). CSR<2> is a diagnostic bit and forces
a parity error. (See Section 3.14.1).

3.14 REGISTERS
This section describes how the following registers are accessed:
MER—Memory Error Register
MAINT-—Maintenance Register
NR—Native Register

LTC—Line Time Clock Register

3.14.1

Memory Error Register

The MER bits are described in Chapter 1, Figure 1-31, and Table 1-24. Figure 3-15 shows
the MER access paths.
MER
< 15,14,02,00
> comprise four flip-flops set by TDAL<15,14,2,0>.
(TDAL<15:0> is
DAL<15:0> fed through a pair of tristate octal drivers.) These four bits assert respectively
CSR<15,14,2,0
> (Control/Status Register). MER
< 11:05 > comprise two sets of 8D flip-flops.

CLERR (Clock Error—Figure 3-14) is the preset input to MER
< 15>. During a RAM read, MER

is not asserted, and inputs LA<17:11> are selected through the multiplexer. The multiplexer

feeds the first set of MER<11:05> flip-flops. When enabled, this set stores address bits
<17:11>. LA<18> is directly input to MER< 05> in the second set of MER<11:05> flip-

flops. Ground is input to MER<11:06
> in this set.

When a parity error occurs, CLERR is asserted, setting CSR<15>. At the same time, CLERR
enables both sets of MER<11:05> flip-flops, storing address bits <21:5>. (Although ground
is input to bits <11:06> in the second set of flip-flops, these bits represent address bits
<21:19> and must be zero to address RAM.)
To read the MER, MERRD is asserted through the 1/O Read/Write logic (Table 3-10) enabling the output of the latch for MER<15,14,02,00> to DAL< 15,14,2,0>. CSR<14> is
normally cleared, and MERRD enables the output of the first set of MER<11:05 > flip-flops to
DAL<11:5>. In other words, bits <17:11> of the error address are asserted on DAL<12:5> .
To read the second set of MER<11:05> flip-flops, CSR<14> is set to 1, and the MER is read
a second time, putting address bits <21:18> on DAL<8:5>.

FUNCTIONAL DESCRIPTION

3-29

I
|

I
I

|
l

PDO16

-+ MPE

CLR

CLK

AND

]

AND
>

RAM

-»>

Qbv

CSRO

—~

_______ __ __
PAR

GEN

»{ 3 OD

—#IX0R

}

—ofxon

7.0

7:0

CSR2

T» ABORT
OR

PE-L

|
ABOR-L

> CLERR |

—

» PERR

DRVR

AND

) AND

QREAD

}

BUS ——] AND

RAM

SCTL ——

F/F

QRDV

DAL7:0

TDIN

|
PDO17

—|—-— CLK

BFCTL

ec?06¢a

DAL15:8

MEMDV

OWRITE

TM AND I | CLR

DEMAND

F/F

]
I

» DAL17
— DAL16

|
|

|
I

]

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"7/ V7
1
» PERR

» PDI17

- PDi16

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|
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ocress
|

To write the MER, MERWT is asserted from the 1/O Read/Write logic, clocking the inputs

to MER<15,14,11:05,02,00>.
At the same time MEFR is asserted from the I/Q Decoder
(Table 3-8), selecting TDAL<11:5> through the multiplexer to the first set of MER<11:05>
flip-flops. MER<11:05> are written only for diagnoslic purposes.
Figure 3-15:

Memory Error Register Access

[bc706a T
T T T T T ——i

> CSR15

> CSR2
» CSRO

DAL15

DAL14

DAL2
DALO

F/F

—s{D

R} DaL14

»{ D

R L pAL2

R |-+ DALO

RF>DALI3, 4,31

CLR

l —> CLK

INIT

IUNTRY
MER

MERWT

e ——
OR

o MUX

CSR14
mereD

%
AND

—

F/F

I
|

EN |

|
RI—»DALITS
R|

DAL12

|
I

> EN

CLK

AND |—

> DAL15

l-—-b HOLD

—
5L

CLERR

—|—|—{D

[_ ______ —)

LATCH

|
l

DAL11:5

CSR14

—

—
=
TMP

-1 EN

R
DAL12:6
RITTM DALS

-{cix

|
|

]
RE3685

FUNCTIONAL DESCRIPTION

3-31

3.14.2 Maintenance Register
The Maintenance Register bits are described in Chapter 1, Figure
1-5 and Table 1-6.
Figure 3-16 shows Maintenance Register access. The Maintenance Register is two quad drivers
with inputs strapped to ground, +3 V and jumper W1. It is read when MAINTRD is asserted
by the 1/O Read/Write logic (Table 3-10).
When HALT option jumper W1 is removed, Maintenance Register <03 > is set. When a HALT
instruction is executed, the processor traps to location 4 in the kernel data space and sets CPU
Error Register
<07 > (Chapter 1, Figure 1-4). When jumper W1 is installed, bit<03 > is cleared
and the processor enters console ODT mode when a HALT instruction is executed.

3.14.3 Native Register
The NR (Native Register) bits are described in Chapter 1, Figure 1-7 and Table 1-8. The NR
comprises 16 drivers and eight flip-flops (Figure 3-17).
The eight flip-flops are NR<07:00> and are set from TDAL<7:0> by the trailing edge of
NRWLB when it is asserted by the 1/O Read/Write logic (Table 3-10). NR<07> is the Selftest Enable bit, and NR<06:00> are the remote indicator bits. IND<6:0> go to the 34-pin
connector (Table 2—4). The flip-flops are cleared if DCOK is not asserted.

The “contents”” of the NR are placed on DAL<15:0> when NRRD is asserted by the 1/O
Read/Write logic.
NR<15:13> indicate the KDJ11-D/S revision level, and NR<12:08>
indicate the bootstrap option. Jumpers W22, W8, W5, W3, and W2, or jumper W22 and
STB <3:0> select the bootstrap option. STB<3:0> come from the 34-pin connector.

3.14.4 Line Time Clock Register
The LTC Register bits are described in Chapter 1, Figure 1-6 and Table 1-7. The LTC Register
comprises two flip-flops and eight drivers (Figure 3-18).

LTC<05:00> are not used. LTC<06> is the event interrupt enable. The first flip-flop is
the enable flip-flop, and is set from TDAL<6> by the trailing-edge of LTCWLB from the I/O
Read/Write logic (Table 3-10). The output of the enable flip-flop is input to the LTC<06>
driver and the request flip-flop. If LTC<06> is set, LTC will be asserted (low) to the DCJ11
EVENT input (Table 3-1) when REVNT (Receive BEVNT) is asserted. Note that the state of
REVNT is also indicated by the NR< 07> driver. The enable flip-flop is cleared by INIT and
the request flip-flop is cleared by ACKLTC, both from the GP Decoder (Table 3-6).
When LTCRD is asserted by the 1/O Read/Write Decoder, the driver inputs are gated onto
DAL<7:0>.

3.15 RAM ADDRESSING
The 512-kbyte on-board RAM is addressed by LA<18:1> through the Memory Address Mux
(multiplexer), Figure 3-19. The address comprises a 9-bit row address and a 9-bit column

address, MUX<7:0>. The row address, LA<18,16:9>, is selected through the mux when
COLSEL is not asserted (Figure 3-11). When COLSEL is asserted, the column address is
selected. The column address comprises LA <17,8:5> and the output of an up/down counter.
The counter supplies the four least significant bits of column address. The counter allows a
16-word block to be written into RAM from the Q22-bus by lalching a single row address in
RAM, and incrementing the column address with the trailing edge of TRPLY.

3-32

FUNCTIONAL DESCRIPTION

:9l-£ 8inbig
DC7064

T 1

DRVR

+3V

DAL7

———l—»

DALS6

+ 5V

$S000Yy 49)sibay aoueusUIRY

DAL5

MODULE

TYPE

(4)

DAL4

DAL3
DAL2
DAL

RPOK

DALO

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NOILARIDSIA TVNOILONNA

MAINTRD

- HALT OPTION

} POWER-UP MODE
(2 = 173000 START ADDRESS)
~ POWER OK

RE3686

Figure 3-17:

Native Register Access

ANy

;fso

[

| DC7064

STB1

e i

e o

e e e

STB2

}

| =

STB3

DRVR

—OW220—|—|—|—

L
ows

o——|—|—

—OWwW3 O

NRRD

IAV DAL9

—> DALS8

e paeo

—|—TM EN

|
|

F/F

—}

»{ D

+» STE

TDAL6:0—

+ IND6:0

~ DCOK

DAL11

r: DAL10

L= DAL7

——————— _J

fi DAL12
+

——O W8 O—

® DAL15:13

——OW5 O
L

TDAL7

—]

»{ CLR

— NRWLB —#JCLK

I
RE3687

3.15.1 Refresh
The RAM must be refreshed at least once every 4 ms. The refresh is done by asserting RAS,
and strobing each of 256 column addresses (MUX<7:0>).
The refresh cycle is controlled by the Memory State Machine, Figure 3-11. When the Memory

State Machine asserts REFADD, the Memory Address Mux is disabled, and its outputs go to
the high-impedance state. REFADD also enables the Refresh Address Counter, and its outputs
are now gated to MUX<7:0>, as the RAM column address (Figure 3-19).
The eight-bit Refresh Address Counter is clocked by REFRESH, which is the output of the
Refresh Counter, Figure 3-11. REFRESH has a period of approximately 15 us.

3-34

FUNCTIONAL DESCRIPTION

Figure 3-18:

LTC Register Access

ocroes

]

DAL6 —

o 7
LTCWLB —{CLK

|NT

CLK

—>|CLR

REVNT J

o
CLR

‘

I > LTC

DOFVR

I ACKLTC
I LTCRD

DAL7

DAL6

—:: DAL5:0
EN

RE3688

3.16 DLARTS
The two DL-style UARTs, Figure 3-20, are identical except for the Halt-on-Break option
implemented with jumper W11 in DLART0. The DLARTSs are enabled respectively by DLO
and DL1 from the I/O Decoder (Table 3-8). Serial data in and out is fed from and to the 34-pin
connector through receivers and drivers. Parallel data is carried on DAL <15:0>.
The baud rate is selected either externally through the 34-pin connector, or with on-board
jumpers W12, W10, W9, W7, W6, and W4. The DLARTSs are clocked by the 614.4 kHz
oscillator (Figure 3-11).

3.16.1

DLART Registers

The DLART register bits are described in Chapter 1, Figures 1-8 through 1-11 and Tables 1-9
through 1-12. Each DLART (Figure 3-20) contains four registers:
RCSR—Receiver Control/Status Register

RBUF—Receiver Data Buffer
XCSR—Transmitter Control/Status Register
XBUF—Transmitter Data Buffer

To access the registers, the DLART is enabled by either D10 or DL1. The Cycle Decoder asserts
either IOREAD or IOWLB (Table 3-9), and the specific register is addressed by LA<2:1>.
The register read/write data is on DAL<15:0>.

FUNCTIONAL DESCRIPTION

3-35

Figure 3-19:

Memory Address Multiplexer

512 KBYTE
RAM

LOW BYTE

ADDR

RWRITE

MUX8:0

—

DIN

DOUT

DouT

RAS

CAS1

CAS

DAL15:8

DIN
DOUT

RAS

CAS

PDI17

PDO17

ADDR

‘ ‘ T l A

HIGH BYTE

PDO16

PDI16

o, SN

LA18

LA17

MUX8

LAS9

MUX

DAL7:0

[)

CAS

MUX7

LAG

LAY

LA15

LA14

LA16

LAB

MUX6

MUX5

LAS

MUX4

MUX3

LA12

LA13

MUX2
LATT

MUX1

LA10
MUXO
o

MAX/MIN

BLEND

INCADD — CLK
LOAD

CTR

REFRESH

|
|

REGCTR

REFADD

|
|

AND

L
FUNCTIONAL DESCRIPTION

3-36

!
|

— COLSEL

|
|
|

—AS —»

DC7063

BIN CTR
o000

—»

v i

LAT

+ B

—»

e B

—

LA2

LA3

—®

Us/D CTR
LA4

BLEND

INCADD

|
|
I

I
I

Figure 3-20:

DLARTs

DLART O

IOREAD

OWLE

DLO

LAZ:1

INIT

DAL15:.0 ¢

+ DAL15:0

-DLOTX

———— WR

TIRQ ——"—|—

A2:1

BRKIRQfF—|—

o1 |PLORX_|

BREAK

—j—|—
¥ CLR

DLCLK

—DCOK

CLK

— |—|—]————®] TEST

O——

— [ —[—

BRS2

we O———|—|—|—|—

BRS1

W9 O

BRSO

—|—

— ===

|| —| | — | — | —]—

DAL15:0 ¢

—[{— "TM WR

TIRQ

DLOSO

—

—_

—|

—J

|
|

DLART
1

DL1TX

RIRQ
DECODER

A2:1

BRKIRQ

—}—|—»{
CLR

—|—|—»
CLK

—|—

W7 O—

—|—|—

W120—

—l——|—

BRS2

L4y

TEST

W100—

BRS1

BRSO

DL1SI

RCVR

DLOSI

DL1SI

CBRO

34PN

CBR1

CONN

CBR2

TXMTOL!

TxmtDLO | DRVR

PBRO
PBR1

PBR2

RECVDL1H
RECVDL1L
RECVDLOH

RECVDLOL

RE3690

FUNCTIONAL DESCRIPTION

3-37

Chapter 4

BOOT AND DIAGNOSTIC ROM
This chapter describes the commands and displays for the diagnostic and bootstrap routines
resident in ROM on the KDJ11-D/S module.

4.1

INTRODUCTION
Bootstrap and diagnostic programs are resident in two ROMs (read-only memories) on the
KDJ11-D/S. The programs (ROM code) test the module and memory at power-up or restart,

and boot user’s software from various devices.

The ROM code has three general areas:

The first area includes the diagnostics which are run when the ROM code is started.
The diagnostics verify that the KDJ11-D/S and additional Q22-bus memories (if any) are

working correctly. Note that test run time is longer if additional memories are installed.

The second area includes bootstrap routines for most DIGITAL tape, disk and network
products.

The third area includes all of the support routines and user commands.

The ROM code tests only the KDJ11-D/S CPU module and additional Q22-bus RAM modules;

it does not test any other modules in the system. The ROM code does not test Q22-bus logic
directly. If additional memory is installed, Q22-bus logic test coverage is increased. Generally,

many Q22-bus logic problems in the KDJ11-D/S CPU will appear as boot-routine failures. The
ROM code does not provide fault isolation to the chip level.

BOOT AND DIAGNOSTIC ROM

4-1

4.1.1 Terminal Requirements
In order to correctly display messages in various languages the console terminal must have
the capabilities described in this section. Language selection depends on the self-test ROM
version (see Section 4.2.3).

For version 1.0 ROM code, the terminal needs to display only standard ASCII for both English
and Spanish (bit 7 of all input is ignored).

For version 2.0 ROM code, certain languages require the terminal to have MCS (multinational

character set) capability in addition to 7-bit ASCII. A terminal with MCS capability is required

to correctly display all the language selections (see Example 4-20). The terminal characteristics
should be such that characters 0 through 127 are ASCII and characters 128 through 255 are
MCS. As listed in Table 4-1, certain languages also use 8-bit input.

Table 4-1:

Terminal Requirements

Language

Output

English

ASCII

French

ASCH

German

ASCII

Dutch

ASCH

Swedish

ASCI

Italian

ASCII

Spanish

ASCHH

Portuguese

ASCII

Input
7 bit

7 bit

MCS

& bit

7 bit

MCS

8 bit

8 bit'

7 bit

8 bit

8 bit'

7 bit

MCS

8 bit

7 bit

MCS

8 bit

7 bit

MCS

17-bit input can be used if bit 7 is set to 0, and the user enters only the minimum characters required to uniquely
identify each command

If a VT220 is used, it must be set to VT220 mode to display MCS characters.

4.2 BOOT SELECT
The CPU automatically executes the ROM code each time the KDJ11-D/S is powered-up or
restarted (using a remote RESTART switch). The bootstrap sequence and subsequent ROM
code execution mode is determined by the value of NR<12:08 > (Table 4-2). These boot-select
bits are set by jumpers or a remote switch.

During ROM code execution, NR<03:00> contain a status code (Table 4-3).
available for remote indication on lines IND
< 03:00> .

4-2

BOOT AND DIAGNOSTIC ROM

This code is

Table 4-2:

Native Register Boot Select Codes

Switch

<12:08>

Position

Description

W22 Installed’

00000

Test, enter console mode using English text’

00001

Test, enter console mode using French text

00010

Test, enter console mode using German text

00011

Test, enter console mode using Dutch text

00100

Test, enter console mode using Swedish text

00101

Test, enter console mode using ltalian text

00110

Test, enter console mode using Spanish text’

00111

Test, enter console mode using Portuguese text

01000

Test, enter console mode (reserved)

01001

Test, enter console mode (reserved)

01010

Test, enter console mode (reserved)

01011

Test, enter console mode (reserved)

01100

Test,” autoboot tapes & disks,* user selects language

01101

Test, autoboot DPV11, DUV11, DLV11-E/F, TU58, & RK05

01110

Test, autoboot DEQNAs 0 and 1

01111

Manufacturing test loop

10000

Test, autoboot tapes & disks® using English text’

10001

Test, autoboot tapes & disks using French text

10010

Test, autoboot tapes & disks using German text

10011

Test, autoboot tapes & disks using Dutch text

10100

Test, autoboot tapes & disks using Swedish text

W22 Removed

INR <12> = W22 (1 = removed, 0 = installed). NR<11:08> = W2, W3, W5, W8 (1 = Removed, () = Installed),
or remote switch position with W2, W3, W5, and W8 removed.

20nly English (codes 00000 and 10000) and Spanish (codes 00110 and 10110) can be selected with version 1.0 ROMs.
Eight languages can be selected with version 2.0 ROMs.

High-speed autoboot, memory address/shorts test is bypassed.
4”tapes & disks”” = DU 0-255, DU 0-255 at floating addresses, DL 0-3, DX 0-1, DY 0-1, MU 0, and MS ). For DU,
removable media is booted before fixed media.

BOOT AND DIAGNOSTIC ROM

4-3

Table 4-2 (Cont.):

Native Register Boot Select Codes

Switch

<12:08>

Position

10101

Test, autoboot tapes & disks using Italian text

10110

Test, autoboot tapes & disks using Spanish text’

10111

Test, autoboot tapes & disks using Portuguese text

11000

Test, autoboot tapes & disks (reserved)

11001

Test, autoboot tapes & disks (reserved)

11010

Test, autoboot tapes & disks (reserved)

11011

Test, autoboot tapes & disks (reserved)

11100

Emulate power up mode 24 with no messages

11101

Halt & enter ODT if trap-on-halt disabled, else Ioop‘r’

11110

Test, autoboot DEQNAs 0 and 1

11111

Test, enter console mode, user selects language

Description

2Only English (codes 00000 and 10000) and Spanish (codes (00110 and 10110) can be selected with version 1.0 ROMs.

Eight languages can be selected with version 2.0 ROMs.

W1 = Trap-on-Halt (disabled = installed, enabled = removed)

Table 4-3:

ROM Status Codes

<03:00>

Value'

0000

Description

HALT switch on, CPU fault, power supply fault, or control has passed from ROM

- code to secondary boot

0001

Preliminary CPU testing—limited error messages

0010

Console SLU testing

0011

CPU testing

0100

On-board memory testing

0101

External memory testing

0110

Floating-point, LTC interrupt, SLUO interrupt, and SLU1 interrupt testing

o111

not used

'Hexadecimal value

4-4

BOOT AND DIAGNOSTIC ROM

Table 4-3 (Cont.):

ROM Status Codes

<03:00>

Value'

Description

1000

not used

1001

not used

1010

not used

1011

not used

1100

ODT in progress

1101

Wrap mode in progress

1110

Boot in progress

1111

Console mode in progress

Hexadecimal value

4.2.1 Automatic-boot Mode
In this mode, the ROM code automatically loads and starts a program from the user’s disk
or tape. After user software is started, ROM code is not entered again until the KDJ11-D/S is
powered-up or restarted. Automatic-boot mode is described in Section 4.5.

4.2.2 Console Mode
Console mode can be entered in two ways:
*

Depending on the contents of NR<12:08>,

console mode is entered after testing is

completed. In console mode, the ROM code allows the user to determine the execution
sequence by entering keyboard commands through the console terminal.
*

Console mode can also be entered if the user types <CTRL/C> during testing or during
the boot sequence; in this case the Native register bits are ignored.

Console mode is described in Section 4.3.
Note—User Input Ignored
User input from the console keyboard is ignored until the first digit of the memory
test count is displayed (Example 4-1), indicating that ROM code is monitoring the
keyboard.

BOOT AND DIAGNOSTIC ROM

4-5

4.2.2.1 Manual Start
This code allows the user to start the ROM code and enter console mode without running any

tests. The user can then attempt to bootstrap test media if a fatal error occurs. (The media
should be write protected.) To manually start, select the boot ODT option (Table 4-2, position

NR<12:08> = 11101) and give the following command to micro-ODT:
173xxxG

where 173xxx is defined in Table 4-4.

(For more information on ODT, see the Associated

Documents listed in the Preface.)

Table 4-4:
Address
173000

Manual Restart Addresses
Description
Normal entry point for power-up or restart. Subsequent action is determined by boot select

jumpers or switch.
173002

Relocate ROM code to RAM. Start the code and run from RAM to allow changes to be made.
The memory test for the first 40 kbytes of memory is bypassed.

173004

Enter console mode with no testing. For maintenance purposes, this overrides testing errors
to allow booting external diagnostics.

4.2.3 ROM Part and Version Numbers
ROMs in sockets E26 and E34 on the KDJ11-D/S module (M7554) have the following part

numbers:

Part Number

Version Number

23-204E5-00

23-205E5-00

1.0

23-261E5-00

23-262E5-00

2.0

Socket:

E26

E34

Byte:

High

Low

4.2.4 Message Formats
The ROM code displays various messages on the console terminal during a normal power-up

sequence. Example 4-1 shows the messages for a typical system bootstrap in automatic-boot

mode. The user’s software is RT11 and is booted from device DU unit 0.

Example 4-1:

Typical Automatic-boot Message

9876564321

DUo

RT-11FB (8) VO5.01

4-6

BOOT AND DIAGNOSTIC ROM

The descending number sequence (987 . . . ) is displayed to indicate that tests are executing.
Messages following the device name and unit number (DUQ) are generated by the booted
software, not the ROM code. At that point the ROM code is not executing and all commands
and messages are determined by the user’s software.
Example 4-2 shows the messages displayed when a typical system is powered-up, runs the
internal diagnostics, then enters console mode. The ROM code will wait for the user to select
the next action.

Example 4-2:

Typical Power-up to Console Mode Message

987654321
Commands

are Help,

Boot,

List,

Map,

Test

and Wrap.

Type a command then press the RETURN key:

4.3 CONSOLE MODE
Console mode allows the user to select a boot device, list available boot programs, run ROM-

resident tests, obtain a map of all memory and 1/O page locations, and “‘wrap’’ the console
SLU to the second SLU.

When console mode is entered, the ROM code displays the message shown in Example 4-3
and waits for the user to enter a command.

Example 4-3:

Console Mode Prompt

Commands are Help,

Boot,

List,

Map,

Test

and Wrap.

Type a command then press the RETURN key:

Console mode provides the user with a choice of six commands, listed in the prompt message.
For a brief description of the commands, the user can type either:

? <RETURN> or

Table 4-5 lists the console mode commands and control characters. The six commands and
control sequences are described in Sections 4.3.2 through 4.3.7.

Table 4-5:

Console Mode Commands

Command

Description

HELP

List console mode commands

BOOT

Boot from selected device

LIST

List ROM boot programs

MAP

Size memory and map 1/O page

TEST

Run tests 3 through 6

WRAP

Wrap SLUO to SLU1

Alternate form of HELP command

BOOT command switch: non-standard CSR address

BOOT AND DIAGNOSTIC ROM

4-7

Table 4-5 (Cont.):

Console Mode Commands

Command

Description

WRAP command switch: wrap SLUO to specified SLU

BOOT command switch: override boot block definition

Delete previous command character

<RETURN > Command delimiter

Aborts operation. Enters/restarts console mode

Aborts WRAP and reenters console mode

Selects hardcopy terminal mode'

Display language inquiry message

Redisplay command line

Delete command line

Selects video terminal mode'*?

TAffects result of deleting characters
ZDefault on ROM restart

4.3.1 Entering Console Mode Commands
All of the commands can be executed by typing any or all of the command characters in
the correct sequence, starting with the first, and followed by <RETURN>. For example, the
WRAP command can be executed by typing any of the following:
W <RETURN>

WR <RETURN>
WRA <RETURN>
WRAP <RETURN >

<CTRL/H> selects hardcopy console terminal mode causing deleted characters to be identified with / (slash) characters when <DELETE> is used.

<CTRL/R> redisplays the command line.
<CTRL/R> is normally used on hardcopy
terminals to reprint command lines that have been obscured by / when using <DELETE>.

<CTRL/V> selects video console terminal mode causing deleted characters to be erased
from the screen when <DELETE> is used. This is the default setting when the ROM code is
restarted.

Input is limited to 26 charaeters (including spaces). None of the commands needs more than
26 characters. If more than 26 characters are entered, the ROM code deletes all of the input
characters, redisplays the prompt, and waits for input.

On input, all lower case letters are converted to upper case. Leading spaces and tabs are
ignored. Two or more tabs or spaces in sequence are treated a single space. All labs are
converted to and echoed as spaces.

4-8

BOOT AND DIAGNOSTIC ROM

Example 4-4:

Invalid Entry Message

Commands are Help, Boot, List, Map,
Test and Wrap.
Type a command then press the RETURN
key: MP
Invalid input

Commands are Help,

Boot, List, Map, Test and Wrap.
Type a command then press the RETURN key:

If an invalid command is entered (such as
MP—see Example 4-4), an invalid message
is
displayed and the prompt is re-displayed to request
additional input.

4.3.2 HELP Command
The HELP command, Example 4-5, displays
a brief description of all console mode commands. It can be executed by typing either:

? <RETURN> or

H <RETURN >

Console mode is restarted at the end of this comma

nd.

Example 4-5:
Commands

HELP Command

are Help,

Boot,

List,

Map,

Test

Type a command then press the RETURN key:
Command

Boot

List
Map

and Wrap.

Description

Load and start a program from a device

List boot programs

Map memory and I/0 page

Test

Run continuous self

Wrap

Wrap Console to SLU1,

test

Type CTRL C to

type CTRL D to

exit

Commands are Help, Boot, List, Map,
Test and Wrap.
Type a command then press the RETURN
key:

4.3.3 BOOT Command
The BOOT command allows the user to select
a boot device. The command uses argume
nts
and optional switches.

Arguments to the command specify the device
name and unit number. The device name
is a two letter mnemonic which describes the
device. An optional third letter specifies the

controller. If the device name is omitted, the
program will prompt for it and the unit number
(Example 4-6). If the unit number is omitted, the
program assumes unit zero. The unit number

range is 0 through 255, depending on the
device and the boot progra

The BOOT command can be entered in two

ways:

B <RETURN >—The system will prompt for the

device name and unit number, as shown

in Example 4-6. Type the device name and
unit number and

B <SPACE> device-name unit-number

The optional switches that can be used with

< RETURN >.

< RETURN > —see Example 4-7.
the BOOT command are:

[/A—Request that the user type in a non-standard
CSR address for the controller.
ROM code prompts for the non-standard address
.

The

BOOT AND DIAGNOSTIC ROM

4-9

/O—OQverride the standard boot block definition.

The switch is typed immediately after the BOOT command and before the device name and
unit number, for example:
B/A

When the BOOT command is entered without an argument, the ROM code prompts for the
additional information, as shown in Example 4-6.

Example 4-6:

BOOT Command Argument Prompt

Enter device name and unit number then press the RETURN key:

The device name and unit number are then entered. If a ? is typed at this point, the ROM code
will list the boot programs available, redisplay the argument prompt, and wait for a selection.
Table 4-6 lists examples of BOOT commands and the corresponding ROM code action.
Table 4-6:

BOOT Command Interpretation

Command Entered

ROM Code Action

B DU

Boot DUO using standard controlier address

B DUA

Boot DUO using standard controller address

B DUB

Boot DUO using first floating controller address

B DU1

Boot DU1

B DUA1

Boot DU

B/A DU10

Boot DU10 with non-standard CSR address = 17760400

Address = 17760400

B/A/O DU10

Address
= 17760400

Boot DU10 with non-standard CSR address = 17760400 without boot block
validity check

B/O DU8

Boot DUS8 and start the program without boot block validity check

BDUO

Invalid format (illegal space in device name DU)

BDUO

Invalid format (space required between BOOT command and device name)

B DU 10:

Boot DU10 (colon after the unit is ignored)

Example 4-7 shows a boot from a DL2.

4-10

BOOT AND DIAGNOSTIC ROM

Example 4-7:

BOOT Command Using DL2

Commands are Help,

Boot,

List,

Map,

Test

and Wrap.

Type a command then press the RETURN key:

B DL2

DL2

RT-11FB (8)

V05.01

.SET TT QUIET

.R DATIME

Date?

[dd-mmm-yy]?

Example 4-8:

LIST Command

Commands are Help,

Boot,

List,

Map,

Test

and Wrap.

Type a command then press the RETURN key:
Device

Units

Description

0-256

RDnn,

RXnn,

0-3

RLO1,

RLO2

RX01

0-1

RX02

0-1

TUB8

0-7

RKOB

0-26b

TKB0

RG25,

0-3

TK25,

0-1

DECnet ETHERNET
DECnet DPV11

TSOb

0-1

0-16

DECnet DUV11

0-16

DECnet DLV11-E

0-16

DECnet DLV11-F

Commands are Help,
Type

Boot,

List,

Map,

RAnn

Test

and Wrap.

a command then press the RETURN key:

4.3.4 LIST Command
This command, shown in Example 4-8, displays a list of all available boot programs found in
the ROM. The list includes the device name, unit number range, and a short device description.
The device name is usually a two letter mnemonic. The valid letter range is A through Z. The
ROM code converts lower case letters to upper case at input.
The unit number range is the valid range for a particular boot program. The range varies from
0 to 255, depending on the device.

The description, or device type, is intended to be the name on the outside of the physical
device. For example, device name DL is described as an RL02.
Console mode is restarted at the end of the LIST command.

BOOT AND DIAGNOSTIC ROM

4-11

4.3.5 MAP Command
The MAP command, shown in Example 4-9:

displays the current ROM code version number

determines and displays the size of ("’sizes’’) consecutive memory

identifies all memory in the system

maps all locations in the 1/O page

identifies the ETHERNET controllers and displays the station addresses

identifies disk (DU) and tape (MU) MSCP devices at their standard addresses of 17772150/2

indicates whether the BEVNT signal is present in the LTC register.

and 17774500/2.

Memoty is mapped from location 0 to the 1/O page, in 1-kbyte increments. Every location
is not mapped because it takes too much time. The map routine will try to identify the size
of each system memory and each memory’s CSR address (if applicable). (Note that if two
memories share some common addresses or have CSRs with the same address, the MAP
command will not work correctly.)

If two or more non-contiguous memories are present,

ROM code will display their descriptions separated by a blank line. If a Q22-bus memory is
installed and shares addresses with on-board memory, the MAP command will not see the
Q22-bus memory addresses which overlap on-board memory addresses.
Caution—Memory Overlap

KDJ11-DIS on-board memory addresses are in the range 00000000 through 17777776
(00000000 through 57777776 for 1.5 Mbyte modules). Other system memory devices
should not be configured to overlap this range. Bootstrap does not check for such memory

overlap; if it exists it may result in system disk corruption.

After all memory is mapped, the ROM code waits for the user to press <RETURN>. The
command will then continue the map, displaying all responding 1/O page addresses. The 1/O
page map addresses are 17760000 to 17777776. In addition, all responding CPU addresses
are listed with a short description.

With the exception of memory CSRs, and devices DU, MU, and XH, responding Q22-bus
addresses are not described. Disk and tape MSCP devices DU and MU are identified only
at their standard addresses of 17772150 and 17772512 (DU) and 17774500 and 17774502
(MU). ETHERNET devices XH are identified at addresses 17774440, 17774456, 17774460, and
17774476.

When an ETHERNET device is identified during the 1/O page part of the MAP command, the
hexadecimal station address is read (and displayed) from bits <07:04> and <03:00> of the
six consecutive bytes starting at address 17774440 or 17774460,

When the LTC register is read during the I/O page part of the MAP command, BEVENT =
0 or BEVENT = 1 will be displayed following the L.TC display. This indicates the presence
(1) or absence (0) of the Q22-bus BEVNT signal. The LTC test will not fail if BEVNT is not
present.

To prevent displayed data from being scrolled off the screen, the ROM code waits for the
user to press <RETURN>. The ROM code assumes the terminal display is at least 24-lines *
80-columns.

Conscle mode is restarted at completion of the MAP command.

4-12

BOOT AND DIAGNOSTIC ROM

Example 4-9 shows the MAP command in English language format. The descriptions are

mnemonic and not translated. For other than English languages, only the console mode

prompt is translated.

Example 4-9:

MAP Command

Commands are Help, Boot, List, Map, Test and Wrap.
Type & command then press the RETURN key: M
KDJ11-D/S ROM V1.0
612 K Bytes

00000000 - 01777776

512 KB

CSR = 17772100

Press the RETURN key when ready to continue
17772100
17772160 - 177721562

17772200 17772220 17772240 17772260 -

17772216
17772236

MCSR

SIPDRO-7
SDPDRO-7

177722566

SIPARO-7

17772260

SDPARO-7

17772300 - 17772316
17772320 - 17772336

KIPDRO-7

17772340 - 177723566
17772360 - 17772376

KIPARO-7

17772616

MMR3

17773000 - 17773776

CPU ROM

KDPDRO-7

KDPARO-7

17776600 - 177765608

SLU1

17777620

17777546

LTC CSR

17777660 - 177776566

SLUO

17777672 - 17777676

MMRO,1,2

17777600 - 17777616

UIPDRO-7

17777620 - 17777636
17777640 - 17777666
17777660 - 17777660

UDPDRO-7
UIPARO-7
UDPARO-7

17777750

MREG

17777766

CPUER

17777772

PIRQ

17777776

PSW

Commands are Help, Boot, List, Map, Test and Wrap.
Type a2 command then press the RETURN key:

4.3.6 TEST Command
This command causes the ROM code to run most of the power-up tests in a continuous loop.
The ROM code starts at test 3, runs all applicable tests and sub-tests, then restarts the loop after
test 6 is complete. Testing can be aborted and console mode restarted by typing < CTRL/C>

at any time. If an error occurs, the Tests 3 through 6 error routine is entered (see Section 4.4.3).
Two actions are possible at this point:

Console mode can be restarted by typing < CTRL/C>

Loop through all of the tests, ignoring errors, by typing L <RETURN> (see Table 4-7).

On exit from the test loop, the ROM code displays the total number of loops (passes) and the

total number of errors (if any) in the following format:
nnn/xxx

BOOT AND DIAGNOSTIC ROM

4-13

where 111 is the number of errors and xxx is the number of times the tests were attempted.
In Example 4-10 the TEST command is entered to run all loopable tests. After
four passes,
the testing sequence is aborted with no errors by entering < CTRL/C>.

Example 4-10:

TEST Command

Commands are Help, Boot, List, Map, Test and Wrap.
Type a command then press the RETURN key: T
Continuous self test

Type CTRL C to exit

0/4
Commands are Help,

Boot,

List,

Map,

Test

and Wrap.

Type a command then press the RETURN key:

4.3.7 WRAP Command
This command takes all input from the console terminal (DLARTO0) and transmits it to
the
second SLU (DLART1), or a selected SLU. All input from DLART1 or
the selected SLU is
sent to the console terminal. This allows the user at the KDJ11-D/S console to communicate

with another system through KDJ11-D/S DLART1 or another SLU selected by the user.
command has one optional switch, /A.

The

Entering the WRAP command without the switch, as in Example
DLART1 (address 17776500).

4-11, wraps the console to
Entering the WRAP command with the switch, as in Example

4-12, causes the ROM code to request an alternative SLU address (instead of DLART1).
The
valid alternate address range is 17776500 to 17776676.
All characters are wrapped, with the exception of <CTRL/D>.

Entered from the console,
<CTRL/D> aborts the WRAP command and restarts console mode.

Example 4-11 shows the WRAP command being entered without the switch. The
console will
be wrapped to the second SLU at address 17776500.

Example 4-11:

WRAP Command Without Switch

Commands are Help,

Boot, List, Map, Test and Wrap.
Type a command then press the RETURN key:. W
Wrap Console to SLU1,

type CTRL D to exit

Example 4-12 shows the WRAP command being entered with an alternate

Example 4-12:

WRAP Command With Switch

Commands are Help,

Boot, List, Map, Test and Wrap.
Type a command then press the RETURN key: W/A

Address =

17776520

Wrap Console to

4-14

SLU1,

type CTRL D to exit

BOOT AND DIAGNOSTIC ROM

SLU address.

4.4 TEST RESULTS
4.4.1 Test 1 Errors
When started, the ROM code runs a series of tests which verify the basic MMU operation
and the ROM code. At this point in the testing sequence, the comprehensive error message
display routines are disabled. If an error occurs during Test 1, the ROM code displays the
following error message:
KDJ11-D/S

1.00

This message indicates that a fatal error condition occurred. The ROM code ignores any
keyboard input, except to redisplay the error message each time input is received. The
message is the same in any user-selected language.

4.4.2 Test 2 Errors
This test checks the console SLU. When the SLUO test is running, the ROM code assumes
that error messages cannot be displayed. Therefore, if an error occurs, the ROM code will
loop on the error.

4.4.3 Tests 3 through 6 Errors
These are the main CPU and memory tests. These are also the tests which continuously loop
when the TEST command is entered. If an error is detected during these tests, the ROM code
displays a brief error message. All errors are treated as fatal errors; the user is expected to fix
the problem before continuing. The error messages are described in Section 4.4.3.1. Section

4.4.3.2 describes how errors can be bypassed for troubleshooting.
4.4.3.1 Test 3 Through 6 Error Messages

Three examples of the error message format are shown in Examples 4-13 through 4-15. In
each of the examples, the three lines of the message are interpreted as follows (the fourth line
is the KDJ11-D/S prompt—see Example 4-16 and Section 4.4.3.2).
e

Linel

KDJ11-D/S is the CPU identifier, and is the same in any error message. 3.15 is the fest.subtest number and is test-dependent.
(Table 4-3).
*

The test number is also contained in NR<03:00>

Line2

This line is ““standard” in any error message.
*

Line3

This line has four parts:
1.

A short description of the failed area:
J11

= J11 test error

J11 FP

= floating point test error

J11 MMU

= memory management test error

BOOT AND DIAGNOSTIC ROM

4-15

J11 nnn

= unexpected trap to virtual address nnn

LTC CSR

= line time clock test error

SLUO

= console SLU test error

SLU1

= second SLU test error

ROM

= ROM checksum test error

RAM

= onboard memory test error

RAM CSR

= onboard memory parity test error

Qbus RAM

= Qbus memory test error

Qbus CSR

= Qbus memory parity test error

All areas except Qbus RAM and Qbus CSR are on the KDJ11-D/S module.
2.

The virtual PC of the failure. Generally, this information is useful only with a program
listing.
Physical address of the failure.

Generally, this information is useful only with a

program listing.

Only displayed with RAM errors, this part displays:
address/found data <> expected data

that is, the failing location, the bad data, and the expected data.

Example 4-13:
KDJ11-D/S
Error,

RAM

On-board RAM Test Error Message

3.16

see troubleshooting section in Owner's manual for assistance

VPC=024722

PA=17604722

01000000/126200 <>

125252

KDJ11-D/S>

Example 4-14:
KDJ11-D/S
Error,

Q22-bus RAM Test Error Message

3.15

see troubleshooting section in Owner's manual for assistance

Qbus RAM CSR

VPC=nnnnnn

KDJ11-D/S>

Example 4-15:
KDJ11-D/S
Error,

J11

004

J11 Unexpected Trap Error Message

3.16

see troubleshooting section in Owner's manual for assistance

VPC=024722

KDJ11-D/S>

If an error occurs and a user language has not been selected, the ROM code will prompt for a
language, then display the error message, as in Example 4-16, which shows English selected.

Note that each line of the language inquiry is displayed in the associated language.

4-16

BOQOT AND DIAGNOSTIC ROM

Example 4-16:

Language Inquiry and Error Prompt

English

Type

Francais

Tapez 2

Deutsch

Geben Sie 3

Nederlands

Typ 4 en druk op <RETURN>

Svenska

Skriv b och tryck sedan pa <RET>

and press the <RETURN> key

appuyez sur <RETOUR>
ein und drucken Sie

Italiano

Introdurre 6 e premere <RITORNO>

Espanol

Presione el

Portuguese

Escreva 8

KDJ11-D/S>

KDJ11-D/S

7 y

<WR>.

luego la tecla <RETORNO>

seguido de

3.015

Error,

see troubleshooting section in Owner's manual for assistance

ROM

VPC=024722

KDJ11-D/S>

4.4.3.2 Commands to Override Errors

When the error message is displayed, the ROM code displays the KDJ11-D/S prompt and
waits for input. The available commands are listed in Table 4-7.

Table 4-7:

Error Override commands

Command

Result

<CTRL/O>4

Override error and enter console mode.'

Restart tests at Test 2.

loop.z

Loop through tests ignoring errors.

Type <CTRL/C> to exit

'The 4 is included with the < CTRL/O
> override command to avoid accidental entry of the command.
2Do not confuse the L (loop) error override command with the L(IST) console mode command

Caution—Bypassing Errors
System media should be either removed or write-protected before bypassing an error.

4.5 AUTOMATIC-BOOT MODE
This section describes the automatic-boot sequence and boot routines.

4.5.1

Boot Code

This part of the boot and diagnostic ROM code provides the primary bootstrap for the devices
listed in Table 4-8.

BOOT AND DIAGNOSTIC ROM

4-17

Table 4-8:

Q22-bus Boot Devices

Mnemonic

Device

RA60/8n, RX50, RD5n, RC25

RLO1, RLO2

RX01

RX02

TU5$

RK05

TK50

TS05, TK25

ETHERNET

DECnet

DPV11

DECnet

DUV11

DECnet

DLV11-E

DECnet

DLV11-F

DECnet

Disk MSCP!

Tape MSCP?

'DU is a general purpose boot device mnemonic for disk MSCP (Mass Storage Control Protacol) devices.

2MU is a general purpose boot device mnemonic for tape MSCP devices.

The primary boot program normally reads a 256-word secondary boot program, from the
device into memory (starting at location 0).
Following successful load of the secondary
bootstrap, the bootstrap is started with the contents of general purpose registers:

RO = the unit number booted
R1 = the controller address
The controller address contained in R1 at the start of the bootstrap is not always the first

address of the controller. Before it is started, the secondary bootstrap program is checked
to see if it is in the expected format for bootable media. (Bootable media is defined in
Section 4.5.7). The secondary bootstrap is started at location 0 for all bootstraps except:
DPV11, DUV11, DLV11-E and DLV11-F, which are started at location 6.

4-18

BOOT AND DIAGNOSTIC ROM

4.5.2 Automatic-boot Sequence (Autoboot)
In the autoboot (automatic-boot sequence), the ROM code continuously tries to load the

secondary bootstrap from an ordered list of devices, as described in Sections 4.5.4 and 4.5.5.
The specific boot device list is determined by the boot select jumpers/switch (Table 4-2). The
load is attempted until a bootable device is found or until the user aborts the autoboot by
typing

< CTRL/C>.

Note—DEQNA
The DEQNA is not included in either boot device list because autoboot

will

not

terminate if there is no response over the Ethernet. It will continuously retry.
DEQNA is selected separately and runs by itself. See Section 4.5.6.

The

If a secondary bootstrap is successfully loaded, NR<03:00> is set to 0.

The ROM code

displays the boot device’s mnemonic and unit number before transferring control to the

secondary boot.

4.5.3 Bootstrap Error Messages
There are two types of bootstrap error messages. One is associated with autoboot at power-up
or restart, and the other with the console mode BOOT command.

If the autoboot is not successful after two passes, the ROM code displays the message in
Example 4-17, indicating that the autoboot was not successful but will make continuous passes

(until successful or aborted). The example shows the power-up or restart count-down sequence
and the unsuccessful autoboot message. Note that if a language had not been selected and

the autoboot failed, only the first line of the message:
KDJ11-D/S

E.Oi

would be displayed.
Example 4-17:

Unsuccessful Automatic-boot Message

987654321

KDJ11-D/S

E.Ot

No bootable devices found.
Boot

in progress,

type CTRL C to exit.

When an error occurs in a boot program called with the console mode BOOT command, the
ROM code displays a specific error message for the failing device and unit number. Table

4-9 lists the possible error messages. Note that all the errors listed may not apply to all boot

programs.

BOOT AND DIAGNOSTIC ROM

4-19

Table 4-9:

Boot Device Errors

Drive not ready

Media not bootable

Non existent controller, address = 177nnnnnn
Non existent drive
Invalid unit number
Invalid device

Controller error
Drive error

Examples 4-18 and 4-19 show console mode BOOT command error messages.
Example 4-18:

Console Mode Boot Error Message (1 of 2)

Commands are Help,

Boot,

List, Map,

Test and Wrap.

Type a command then press the RETURN key:

B DL3

KDJ11-D/S E.0b
Non existent drive

Commands are Help,

Boot,

List, Map,

Test

and Wrap.

Type a command then press the RETURN key:

Example 4-19:

Console Mode Boot Error Message (2 of 2)

Commands are Help,

Boot,

List, Map,

Test and Wrap.

Type a command then press the RETURN key:

B DUl

KDJ11-D/S E.04
Non existent controller,

address = 177721560

Commands are Help,

List, Map,

Boot,

Test and Wrap.

Type a command then press the RETURN key:

4.5.4 Disk and Tape Autoboot (Except TU58)
When disk and tape autoboot is selected, the ROM code attempts to boot software from the
first available device that is present and ready with bootable software. Table 4-10 lists the
devices in the order in which they are checked. The table also lists the unit numbers checked
for each bootstrap.

4-20

BOOT AND DIAGNOSTIC ROM

Table 4-10:

Disk and Tape Boot List
Unit

Order

Name

Range

Address

Description

0-255

172150

Disk MSCP' (removable media)

0-255

172150

Disk MSCP (fixed media)

0-255

FFA?

Disk MSCP (removable media)

0-255

FFA

Disk MSCP (fixed media)

0-3

174400

RLO1/02

0-1

177170

RX01

0-1

177170

RX02

174500

Tape MSCP

172520

TSV05/TK25

IMSCP devices are listed in Table 4—8
2First floating address

If the autoboot comes to the end of the list without booting a device, it will return to the

top of the list and continuously loop through the list, until successful or aborted by entering
<CTRL/C>.

Note that the boot select jumpers/switch also select the language for displayed messages.

4.5.5 DPV11, DUV11, DLV11-E/F and TU58 Autoboot
When disk and tape autoboot is selected, the ROM code attempts to boot software from the
first available device that is present and ready with bootable software. Table 4-11 lists the
devices in the order in which they are checked. The table also lists the unit numbers checked
for each bootstrap.

Table 4-11:

DPV, DUV, DLV, TU58 and RK05 Autoboot List
Unit

Order

Name

Range

Address

Description

Floating (rank 22)

DPV1

DECnet

Floating (rank 4)

DUV11

DECnet

175610

DLV11-E

DECnet

175610

DLV11-F

DECnet

0-1

176500

TUS58

0-7

177404

RKO05

BOOT AND DIAGNOSTIC ROM

4-21

These devices are in a separate selection because they all tend to slow-down the autoboot.
The DECnet boots are included because of the relatively long device-response times between
attempted boots. For a similar reason, the TU58 is included in this list. The TU58 controller
has the same address as SLU1 (17776500), and the autoboot does not know whether it is
present until the TU58 fails to respond to a request. Because this requires a relatively long
time, the TU58 is included in this list.

This selection does not include a language for messages. If the boot is successful, a message

is not required. For error or status messages, the ROM code will prompt the user to select a
language (see Section 4.6).

4.5.6 DEQNA Autoboot
The DEQNA is not included in either boot device list because autoboot will not terminate if
there is no response over the Ethernet. It will continuously retry. If the first DEQNA is not
present, or fails the citizenship test, the autoboot will try the second DEQNA. The DEQNA is
selected separately and runs by itself.

This selection does not include a language for messages. If the boot is successful, a message
is not required. For error or status messages, the ROM code will prompt the user to select a
language (see Section 4.6).

4.5.7 Bootable Media
After the first block is read from a disk or the second record is read from a tape, the ROM
code checks the first two words in memory. If the data is not correct, the ROM code generates
a non-bootable media error.

The boot block is bootable if the first word (memory location 0) contains a value in the range
2403 to 2773, and the second word (memory location 2) contains a value in the range of 400g to
777g. This definition applies to all disk and tape boots in the ROM code, but does not apply
to the DECnet boots for the DPV11, DUV11, DLV11-E and the DLV11-F. These four DECnet
boots are considered bootable if the value of memory location 0 is 0.

If the /O switch is used with the console mode BOOT command, the ROM code verifies only
that location 0 is not 0 (HALT) before starting a secondary boot. (This does not apply to the
DECnet boots for DPV11, DUV11, DLV11-E and DLV11-F.) The /O switch allows software that
does not meet the bootable media standard to be booted. The switch can only be selected with
the console mode BOOT command; there is no similar switch or function for the automaticboot sequence.

4.6 LANGUAGE SELECTION
If a local language has not been selected, the ROM code will prompt the user to select a
language as required for messages and commands. If version 1.0 ROMs are installed, only
English and Spanish are available. If version 2.0 ROMs are installed, eight languages are
available.
:

Certain boot selections do not include a language selection because these modes are normally
automatic; messages requiring translation are not normally displayed. When <CTRL/C> is
typed to abort one of these modes, the ROM code enters console mode and prompts the
user to select a language, as in Example 4-20. The example shows the selected language is
German.

At any time in console mode, the user can select another language by typing < CTRL/L> to
display the language inquiry message and prompt.

4-22

BOOT AND DIAGNOSTIC ROM

Example 4-20:

Language Inquiry

English

Type

Francais

Tapez 2

Deutsch

Geben Sie 3

Nederlands

Typ 4 en druk op <RETURN>

Svenska

Skriv b

Italiano

Introdurre 6 e premere <RITORNO>

and press the <RETURN> key

appuyez sur <RETOUR>
ein und drucken Sie

<WR>

och tryck sedan pa <RET\TEXT>

Espanol

Presione el 7 y luego la tecla <RETORNO>

Portuguese

Escreva 8

KDJ11-D/S>

seguido de

4.7 TROUBLESHOOTING
The ROM code is limited to detecting errors on the KDJ11-D/S module or external Q22-bus
memory. If the KDJ11-D/S is failing, the module would normally be replaced. If the problem
is in external RAM, system-level diagnostics may provide further isolation. The documentation
for systems with the KDJ11-D/S installed should define the system maintenance philosophy
and describe system-level diagnostic programs. The message:
Error,

see troubleshooting section in Owner's manual for assistance

in Examples 4-13 through 4-15, refers to such system-level documentation.

BOOT AND DIAGNOSTIC ROM

4-23

Index
A

Block nutmnber, 1-31

ABORT, 3-5
Aborts note, 1-36

Access control tield, 1-36, 1-42
ACF, 1-36, 1-42
ACKLTC, 3-14
ACKPE, 3-14

BN, 1-31
Bootstrap starting address, 1-2

BS 1:0, 3-6
Buffer Control, 3-6

BUS, 3-13
Bus

Cycle, 3-8

ACKQ, 3-24

Loading note, 2-19

Active page field, 1-31

State Machine

Address

Output signals

Bootstrap starting address, 1-2

TDIN, 3-26

Input/Qutput, 3-6

TDMG, 3-26

Latch Enable, 3-6

TDOUT, 3-26

Local memory starting address, 1-2

TIAK, 3-26

Modes, xii

TRPLY, 3-26

AlO

3:0, 36
Decoder output signals
BUS, 3-13
BYTE, 3-13

DEMAND, 3-13

GP, 3-13
IAK, 3-13
MEMSEL, 3-13

TSYNC, 3-26
Bypassing errors caution, 4-17
BYTE, 3-13

C
Cache, 1-2
Control register, 1-44
Hit/Miss register, 1-44

READ, 3-13

CCR, 1-44

RMW, 3-13

CD interconnect, 2-13

ALE, 3-6

CLERR, 3-29

APF, 1-31

CLK2, 3-6

1A switch, 4-9, 4-14

Clock 2, 3-6

Autoboot, 4-19

Clock Error, 3-29

B
Bank Select, 3-6
BFCTL, 3-6

BHALT, 1-21

16-bit and 18-bit memories caution, 2-16
18-bit DMA devices note, 2-16

Commands

Console mode
IA switch, 4-9, 4-14

BOOT, 4-9

CTRL/C, 4-5, 4-13,

4-14

CTRL/D, 4-14
CTRL/H, 4-8

Index-1

Commands
Console mode (cont’d.)
CTRL/L, 4-22
CTRL/R, 4-8
CTRL/V, 4-8
HELP, 4-9

LIST, 4-11
MAP, 4-12

10 switch, 4-10
TEST, 4-13
WRAP, 4-14
Error override

CTRL/O 4, 4-17
L, 4-13, 4-17

CONT, 3-5
Continue, 3-5
Control and Status Register, 3-29

Crystal, 3-5
CSR, 3-29
CTRL/C command, 4-5, 4-13, 4-14

CTRL/D command, 4-14

CTRL/H command, 4-8
CTRL/L command, 4-22

CTRL/O 4 command, 4-17
CTRL/R command, 4-8
CTRL/V command, 4-8

CYCLE, 3-20
Cycle Decoder
Output signals

CYCLE, 3-20
ENJADD, 3-20

IOREAD, 3-20
IOWHB, 3-19
IOWLB, 3-19

DCJ11
Inputs (cont’d.)

CONT, 3-5
DCOK, 3-4
DMR, 3-4
DV, 3-4

EVENT, 3-4
HALT, 3—4
INIT, 3-4

IRQO, 3-4

LTC, 3—4
PARITY, 3-4

PE, 3-4
PWRF, 3-4

RDMR, 3-4
RHALT, 3-4

XTAL 1:0, 3-5
Macroinstruction, 3-8

Microcycle, 3-8
Microinstruction, 3-8

Outputs
AlO 3:0, 3-6
ALE, 3-6

BFCTL, 3-6

BS 1:0, 3-6

CLK2, 3-6
DAL 21:16, 3-6

JDAL 21:16, 2-6
MAP, 3-6
PRDC, 3-6

SCTL, 3-6
SRUN, 3-6

STRB, 3-6
DCOK, 3-4

DC power OK, 3-4

DEMAND, 3-13

DAL 15:0, 3-5

Demand-read, 3-9

Data/Address Line, 3-5, 3-6

DEQNA note, 4-19

Data Valid, 34

DF, 1-31

DC7063, 3-1

DIB, 1-31

DC7064, 3-1

Displacement
Field, 1-31

DCJ11

Bus cycle, 3-8

Cycle, 3-8

Stretched, 3-9
Vector read, 3-11
/O Bus, 3-8

In block, 1-31

DLO, 3-18

DLORX, 3-24
DLOTX, 3-24
DL1, 3-18

Information note, 3-4

DLIRX, 3-24

Input/Outputs

DL1TX, 3-24

ABORT, 3-5

DLART, 1-2

DAL 15:0, 3-5

Dl-style UART, 1-2

Inputs

Index-2

DMA Request, 3~4

D space, 1-29

Decoder

DV, 3-4

Output signals (cont’d.)

LIO, 3-17
MAINT, 3-18

ENJADD, 3-20

MER, 3-17

ERROR, 3-29

NR, 3-17

Errors

QIOPACE, 3-18

Bypassing caution, 4-17

RLTC, 3-18

Extended LSI-11 bus, xi, xii

Read/Write logic

Output signals

LTCRD, 3-21
LTCWLB, 3-21

FEA, 1-47

FEC, 1-47

MAINTRD, 3-21

Floating-point

MERRD, 3-21

MERWT, 3-21

Accelerator, 1-2
Exception address register, 1-47

NRRD, 3-21

Exception code register, 1-47

NRWLB, 3-21

Instruction set, xii

Status register, 1-45

ZHB, 3-22

IAK, 3-13
Decoder

FPA, 1-2

Output signals

FPS, 1-45

ACKQ, 3-24

DLORX, 3-24
DLOTX, 3-24

Gate arrays, 3—1

DLIRX, 3-24

General Purpose, 3-5

DL1TX, 3-24

GP, 3-5

VHB, 3-24

Codes
000, 3-14

INIT

H, 3-14

002, 3-14
014, 3-14
100, 3-14

140, 3-14
214, 3-14
Decoder output signals

ACKLTC, 3-14
ACKPF, 3-14
INIT H, 3-14
INITL, 3-14
PMODE, 3-14

L, 3-14
Initialize, 3-4

Instruction set, xii

Interrupt Request 0, 3—4
IOREAD, 3-20

IOWHB, 3-19

IOWLB, 3-19
IRQO, 3-4

I space, 1-29

J
JDAL 21:16, 3-6

HALT/trap, 1-2

Jumper part number, 2-1

K
Kernel

Bus, 3-8

Decoder

Output signals

Mode, 1-2

Stack pointer, 1-18
KSP, 1-18

DLO, 3-18

DL1, 3-18

Index-3

Non-1/0, 3-8

L
L. command, 4-13, 4-17
Line time clock, 1-12, 3-4
LIO, 3-17
Local memory starting acddress, 1-2
LTC, 1-12, 3~4, 3-32
Interrupt request, 3—32
LTCRD, 3-21

NR, 3-17
NRRD, 3-21

NRWLB, 3-21

O
/O command switch, 4-10

ODT, xii, 1-2

LTCWLB, 3-21

On-line Debugging Technique, 1-2
Operating mode, 1-2

M7554, 1-2

Macroinstruction, 3-8
MAINT, 3-18

MAINTRD, 3-21
Management registers, 1-29
MAP, 3-6
Map Enable, 3-6
MCS, 4-2
Memory

16-bit and 18-bit memories caution, 2-16
Cache, 1-2
Decoder output signals

QSEL, 3-16
RAMSEL, 3-16
ROMSEL, 3-15
Local, 1-2

On-board, 1-2
Q22-bus or Local Memory note, 3—26
Memory error register, 1-44

MEMSEL, 3-13
MER, 1-44, 3-17
MERRD, 3-21
MERWT, 3-21
Microcycle, 3-8
Microinstruction, 3-8
Mode

Kernel, 1-2
Power-up

01,3, 1-2
2, 1-2
Protection modes, 1-2

Supervisor, 1-2
User, 1-2
Module part number, 1-2
MSCP, 4-18
Multinational character set, 4-2
MUX 7:0, 3-32

N
NIO, 3-8

Index—4

PAF, 1-31, 1-33

Page

Address field, 1-31, 1-33
Address register, 1-29
Descriptor register, 1-29, 1-35
Length field, 1-35
PAlL, 3-1

PAR, 1-29
Parity

Data In bit 16, 3-29

Data In bit 17, 3-29
Data Qut bit 16, 3-29
Data QOut bit 17, 3-29
Error, 3—4

Error note, 3-29
I’art number

jumper, 2-1
Module, 1-2
ROM, 4-6

PB, 3-6

PcC, 1-19
PDl116, 3-29
PDN7, 3-29

PDO16, 3-29

rpo1iz, 3-29
PDR, 1-29, 1-35

PE, 3-4
PIRQ, 1-9
PLA, 3-1

PLF, 1-35

PLS, 3-1

PMODE, 3-14
Power Fail, 3—-4

Power supply loading note, 2-19
Power-up mode

0,1,3,

1-2

2, 1-2
Predecode, 36

Prefetch Buffer, 3—6
Processor status word, 1-7

Registers
Memory (cont’d.)

System, 1-3

Program

MER, 1-44

Counter, 1-19

MMROQ0, 1-36

Interrupt request, 1-9

MMR1, 1-38

Programmable

MMR2, 1-38

Array Logic, 3-1

MMR3, 1-29, 1-38

Logic Array, 3~1

MMU status, 1-36

Logic Sequencer, 3-1

Native, 1-13

Programming techniques, xii

PAR, 1-33

Protection modes, 1-2

rc, 1-19

PSW, 1-7

PDR, 1-35

PWRF, 3-4

PIRQ, 1-9

PSW, 1-7
R6, 1-18

Q22-bus, xi, xii

R7, 1-19

QIOPAGE, 3-18

RBUF, 1-14

QSEL, 3-16

RCSR, 1-14
Receiver

Control/status, 1-14
Data buffer, 1-15

RAMSEL, 3-16
RBUF, 1-14

sSSP, 1-18

RCSR, 1-14

Stack pointer, 1-18

RDMR, 3-4

System control, 1-3, 1-7

READ, 3-13

Transmitter

Control/status, 1-16

Read/Modify/Write, 3-8

Data buffer, 1-17

Receive

User-visible, 1-3

DMA Request, 3—4

uspP, 1-18

Halt, 3—4

XBUF, 1-14

Receiver

XCSR, 1-14

Control/status register, 1-14

Request-read, 3-9

Data buffer, 1-14

RHALT, 3-4

Registers

RLTC, 3-18

ACO:AC5, 1-48

CCR, 1-44

RMW, 3-8, 3-13

CPU error, 1-10

ROM, 4-1

DLART registers, 1-14

Code, 4-1

Fault recovery, 1-36

Part number, 4-6

FEA, 1-47

ROMSEL, 3-15

FEC, 1-47

RUN indicator, 3—6

Floating point, 1-3
FPS, 1-45

General purpose, 1-3, 1-17
Hit/Miss, 1-—-44
KSP, 1-18
LTC, 1-12

Maintenance, 1-11
Management, 1-29
Memory

Addressable, 1-3
Management, 1-3, 1-32

S
SCTL, 3-6

Serial Line Unit, 1-2

SLU, 1-2
SRUN, 3-6

sSSP, 1-18
Stack pointer
KSP, 1-18
SsP, 1-18

System, 1-18

Index-5

Stack pointer (cont’d.)
uspP, 1-18

STRB, 3-6
Stretch Control, 3-6
Stretched cycle, 3-9
Strobe, 3-6

U
UART, 1-2

Universal asynchronous receiver/transmitter, 1-2
User

Mode, 1-2

Supervisor
Mode, 1-2

Stack pointer, 1-18

System stack pointer, 1-18

Stack pointer, 1-18
usPr, 1-18

VHB, 3-20, 3-24
TDAL 15:0, 3-29
TDIN, 3-26

TDMG, 3-26

XBUF, 1-14

TDOUT, 3-26

XCSR, 1-14

TIAK, 3-26

XTAL 1:0, 3-5

Transmitter

Control/status register, 1-14

Data buffer, 1-14

ZHB, 3-22

TRPLY, 3-26

TSYNC, 3-26

Index—6

Digital Equipment Corporation « Bedford, MA 01730