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EK-KD11K-TD-PRE
January 1978
128 pages
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KD11K Processor (PDP-11/60) Technical Description Manual Section 6 Maintenance Features
Order Number:
EK-KD11K-TD
Revision:
PRE
Pages:
128
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OCR Text
EK-KD11K-TD-PRE KD11K PROCESSOR (PDP-11/60) TECHNICAL DESCRIPTION MANUAL SECTION 6 MAINTENANCE FEATURES 1st Edition, January 1978 Copyright © 1977 Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice. Digital Equipment Corporation assumes no responsibility for any errors which may appear in this manual. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC DECtape DECCOMM DECUS PDP RSTS DECsystem-10 DIGITAL TYPESET-8 DECSYSTEM-20 MASSBUS TYPESET-11 UNIBUS CONTENTS Page CHAPTER 1 INTRODUCTION 2 TROUBLESHOOTING 1.1 1.2 o LOG CUA (CsPl) LOG FLAG/INTERRUPT O~ ........... ....................... ......... ........ cececcsace e e (CSP4) LOG WHAMI (CSP5)..ceceeeccesen LOG CACHE DATA (CSPb6).ceeeececccesaacacnse W LOG TAG/HIT (CSP7)ecccecccccns PDP-11/60 Error and Status Reglsters ......... PROCESSOR STATUS WORD (777770) ccceccacacs MEMORY STACK CPU Bit OWOoO~JAHhUtd o MANAGEMENT LIMIT STATUS REGISTER REGISTERS....... (777774)..... ERROR REGISTER (777766).¢ce... @& (ILLEGAL INTERNAL ADDRESS)..... MEMORY ERROR REGISTER (777744).... CACHE HIT REGISTER (777752)..¢.... SWITCH REGISTER (777570)..... ............ WCS (Writeable Control Store) Status — =2 Register {(777740) i it eeeeeeseaacosnosnncnse MICROBREAK REGISTER (777770-Write Only).. PDP-11/68 Control Registers..... cececan CACHE CONTROL REGISTER ACTIVE PAGE N = [] [] [} [] o s [] [] o e L] L] » e [] L] [] o s 8 [] [] o o . DO N RN DD RO L] [] B W W W N W (CSP2) » PBA NN BN bt bt e pd et et et [] LOG o [] Microaddress (777746).... REGISTERS. .. ccccocecococccces Match and Microbreak Register [K3ll].....‘ ..... ® © @ @ & © & &6 & 5 & & 6 3 O 0 O O B O 5 O 6 6 6 e s 0 MED INSTRUCTION o W N TOGGLE-IN o WWwWwwwh ......... JAM (CSP@)...... SERVICE (CSP1) o [] e L] [) e e [ [] [] [] et et et b ® . * [ o et pd e b [] e [} [] ot b [] S [] [] L[] b= bt b L] [] L] [] STATUS REGISTERS...¢ceccceosee Logging Registers... LOG LOG N [ ® [] [] NN NN AIDS ERROR SERVICING AND PDP-11/6% Error [] NN NDERNDNDNDNDNDNDNDNDNDND DN N CHAPTER AND ITS USE...... ROUTINES.... RKO5 Manual BoOOt....cceceeecccoosccccccscncsccs RKOH6 Manual BOOt .. iecceececeesoccascscosccnsocscsse Branch Console Self...... . Echo Routine....... iii CONTENTS (CONT) Page CHAPTER 3 3.1 COLD START TROUBLESHOOTING INTRODUCTION. 3.1.1 3.1.2 AC 3.1.3 Console and 4.1.1 POWEIL .ttt eoeeeeecncncncses ceees e Operation..eeeieeeecseseceeccacccacnesse Initialization to Console LOOD..eveeeeens Console MiCrotest...eeeeeieeeeeeooeenns o ue 4 MICRODIAGNOSTICS (XXDP) 4.1 DC Cablinguieeeeeeeneeeeeeeeonness ceeccsessecccan 3.1.3.1 3.1.2.2 CHAPTER ... v.o... e e e e s eeec e s s s esceaan es s .o - (DCS), MAINTENANCE MICRODIAGNOSTICS = MACRODIAGNOSTICS AIDS.....0etceeeceeeccacccans DCS (M7871) ittt eeeesccocaceeses Documentation/ListingsS....c.eeeeeeeses ceeeeoaas 4.1.2 4.1.2 4.1.3.1 Starting ProceduUre...cceeeeeceeneeecennss ceecoe Startup Via the Operator's Console 4.1.3.2 (KY1l=P) it eieeeeeeeeeeeoeoaanono cesecaee Startup Via the DCS Switches......cc..... 4.1.3.3 4.1.4 Using 4.1.4.1 "INIT"...eeeereeeeecnnnnenn ProceduUre..i.ie. . eeeeeeeeeeeeenoneesns DCS Indications While Executing on the KD11-K Operator's Console.....c.cov... e ee e 4.1.4.2 4.1.5 Console Onerating DCS DCS 4.1.5.1 Indications ExX2CUtion While Executing.......... TiMA.eeeeeeeeeeeeeeoooooancasaes "CNTRL/DIAG" Start from Operator's 0 3 ¢ 1= 0 4.1.5.2 4.1.6 DCS Start from DCS Switches.....cceee... ceeos "END-OF-PASS" and "ERROR" Indications.... 4.1.6.1 On the DCS 4.1.6.2 On the Operator's 4.1.7 Module......... cecessesacsnnas Console....cceeeeeeenann ResStricCtionNS...eieeeeceeececesceceeses Hardware 4.1.7.1 Cache 4.1.7.2 4.1.8 MOS Software 4.1.9 Error Handling. 4.1.10 FAULT DIRECTORY 4.1.10.1 4.1.10.2 4.1.11 and Memory Memory Management Battery (KT)......... Backup..oeeeeeeeeeenees ResStriCtioOnNS....ceeeeeeaceccocccecenees ... ei ittt et eeeeeeecencecncceses Format and Use...veeeeeeeeeen Basic Structure.....iiieieenenececscccnnes Basic Use - With an Example.....c.eeeeenn 4.1.11.2 "SCOPE LOOP" Facility..eeeeeeeoeeeeacocascnns General Information..... cececsesscsccsenn Implementation and Us€e..uoeeeeeeenn ceenens 4.1.12 DCS 4.1.11.1 4.1.12.1 4.1.12.2 4.2 4.2.1 Verification/Self-TesSt...ceeieeeeeeeeennnn RequirementsS...ceeeeeeeeeens ceeecceecnane Verification Method. ...t enneeneennn MACRODIAGNOSTICS (PDP-11/69 XXDP) . v eeeeeeoencanns PDP-11/68 XXDP.veeeooeooo e e s s e s esec s ssassene iv CONTENTS (CONT) Page 4.2.2 PDP-11/60 DiagnostiCS..eeveeeeeeecooens e "DQKDA" - KD1l1-K Basic Logic TestS....... 4.2.2.1 4.2.2.2 "DQKDB" 4.2.2.4 - 11/60 Trap TestS....eeeeoens “oe "DQKTA" - PDP-11/60 Memory Management Diagnostic...ceeeeeen.. et eceesescanae s "DZQMC" - 8-124K Memory Exerciset........ 4.2.2.5 4.2.2.6 "DQKAA" "DQFPA" 4.2.2.3 - 11/60 11/69 Cache Diagnostic......... Floating Point Unit, 4.2.2.8 Basic Instruction TestS....eeeeeeennn. . "DQFPB" - 11/60 Floating Point Advanced Instruction TeStS..iieeeeeeeeeeneeoonnnen "DQFPC" - 11/68 Floating Point Unit 4.2.2.9 Instruction Exerciser........... cesesecane "DQFPD" 11/68 Floating Point 4.2.2.10 ADD/SUB/MUL/DIV EXe€rCiSeree.eeeeeeeeess .o "DZDLD" - DL11-W DiagnostiC.....c... ceeen 4.2.2.7 4.2.2.11 "DQKDC" - 11/60 4.2.2.12 Series CPU "DZKAQ" - 11/6% Power Fail 4.2.2.13 "DZM9A" - 11/6 Bootstrap/Terminator DiagnoStiC. e eeeeeeeeeeeeceeasoeeaansees - 4.2.2.14 "DZKUA" 4.2.2.15 4.2.2.17 4.2.2.18 5.1.1 5.1.2 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.3 5.3.1 System Exerciser........ "DQMO9A" - Program. e eeeeeeeeeneecseacscececoncaccoaness PDP-11/684 ROM Bootstrap/Test “DQKUA" - 11/60 WCS Dlagnostlfl ........... "DQKUB" - KD11-K Micro-diagnostics....... Perivheral DiagnosStiCS.....eeeeeeeeeeeecennns 4.2.2.19 4.2.3 5.1 Unibus "DZKUB" - Unibus Exerciser Module DiagnoStiC.e e e eeieeeeeeeeeeecaseooaononsse "DZMML" - MS11-K MOS Memory TestS........ 4.2.2.16 CHAPTER - Exerciser..... TeSt..eeeeeee. 5 REMOVAL AND REPLACEMENT PROCEDURES INTRODUCTION . ¢ v ettt teeececccceccceccecoanccncccsess Module Removal and Replacompnt ............... Console Disassembly....ieieeeeeeneeeneccennss EQUIPMENT CONFIGURATION Mechanical ECO Status STATUS . ... ceeeecosoccocsses Status Sticker......ceeeeeeeeeeens Sticker......... ceseetecesseeneens Module ECOs....... Ce e s escesesesanaasacsesne s Module Utilization List (MUL) Sticker....cee.. REMOVAL AND REPLACEMENT OF ICs..... DESCRIPTIONS, IC DesSCriptioNS.ceeeeeeeceeeeeeececeoncacnasen 5.3.1.1 74189 64-Bit Random 5.3.1.2 745194 4-Bit Shift Access Memory........ Register.......ceeee.. CONTENTS (CONT) . L w N -~ . . Do o8 [\ [} ww . . L] L ww . [ (9] Removal and Replacement of ICs......cccceeenn Location O0f ICS.cceeeececoscsccccccnocess .. IC ConnectioNS.ceeeecessocccocccans ceeaes IC and Component Removal and Replacement.....ceceeeceee ceserssasassene w oo Page Removal and Reolacement of Plastic Case ICS.....Q..... ..... ® & ©® & & & 6 & & & T & & O & O o o e & o ° vi TABLE Title WNN N | W Table No. Maintenance Equipment Required........c...c.. LOgaing REegiSteIS..cceeeecscescsccocccocccses PAR/PDR Address AssignmentS....eee... Access Control Field KeyS.ceeeeeeooeoeeooconcocnns PDP-11/60 Micro-Addresses from INIT to Console 3-2 Key 4-1 PDP-11/608 5-1 Available....ciieeeereeascccccaanesns ceeseseceosns . Completing the ECO Status Sticker....ceceeceeecs . 5-2 Completing Loop.......................................'..... SwitCh COGeS.cteiercceeccossscccscsocccsccnsas Peripheral MUL Devices Having XXDP StiCKer.c.eieeeeescsocecosoconccsns vii NOTICE The technical information in this document has been reviewed and approvad by engineering and field service. This information will be published in final typeset form as section 6 of the KD1]-K Processor (PDP-11/69) Technical Description Manual. CHAPTER 1 INTRODUCTION 1.1 SCOPE This section of the detailed description built-in features microdiagnostics, KD1l1lK of Technical the PDP-11/60 are both etc.) and registers, microbreak, PDP-11/68 troubleshooting approaches. to isolate l. Each of single these Diagnosis processor, upon cache, loading micro-switches 2. On-Line be bits as may of be main disabled Module. Diagnosis -- More 99 and to through the Deposit Procedure. in some of be used for console, the internal using Error internal system major microdiagnostics memory M93A1-YH than three diagnostics the stored data, but status are: on accessed Examine 1Internal 28K error using implementes approaches and These etc.). approaches =-- a diagnostics, (parity, accomplished The provides Features. (system hardware clock, Manual Maintenance software is faulty modules. Self Description error check the automatically by altering registers the may Maintenance, flags and control registers are treated analysis. While the checking system When a. b. is one single-bit is is in performed employs mation is system on operation, recorded parity data and memory addresses. bit for every eight errors are detected, parity parity extensive (Error Logging). Byte bit error parity The byte. infor- checking provided: For all data in Between memory cache, the (cache and and on data processor and core); in on addresses and core cache for cache data and tag. Diagnostic Control containing its own microdiagnostics array, with 14 total), four employed to M7875 Cache Module a. DIAG key processor the can indicator be is in basic has LEDs the Console - halt state; with the CNTRL on the indication console hex board indicator and LEDs interface; (except the macrodiagnostics). following manner: When PDP-11/68 the key microdiagnostics. "confidence check" A modules own the the (32 logic its in -- in a 2K X 52 bit ROM processor utilized on module's on Module control which switch conjunction DCS (DCS) switches, module) DCS the error check The in Store the DIAG Kkey switch, This switch, initiates provides a system and gives a go/no-go by predefined displaying a octal number (1.2.3.3.2.1), with Verify/Norm Control switch switch, put the when to in DCS module perform This can be DIAG key while holding Run/Stop control switch Control switch on initiated on from - This allows check of (pressing the CNTRL key) or located above the in the DCS module. LED and displayed in the remaining Module. If the Verify console displays decimal points Also, illuminate 12 1is number the if by the Verify/Norm octal are code is on the successful, the 2.1.2.1.2.1, with Error the the Errors error pass octal an the itself. console Error LEDs module 1lit. the the Pass) points position, a diagnostic by 1lit. DCS Verify indicated the decimal LEDs and EOP Verify (End of routine is successful. MED (Maintenance, Access - To processor, employed. initiate by Maintenance, the This a 11410 DIAG/CNTRL and key Deposit by address procedure the same Instruction of the diagnostics, the check procedure loading (Write This switches. Deposit) confidence performed (starting in and Module's Register, diagnostics). diagnostics is a DCS Examine Micro-Address) with Examine the Function of the manner as be NUA (Next Code 358), DCS initiates may Module's the micro- utilizing the The main detail purpose in engineer the to of following maintain module replacement. module isolation 1.2 Table MAINTENANCE 1-1 PDP-11/640. these lists maintenance Sections) the 11 With is Family's these to aids (to allow repair be the discussed Field philosophy maintenance of features, in Service faulty faulty is made possible. EQUIPMENT REQUIRED special/standard equipment required to maintain a Table 1-1 Maintenance Equipment Required Model, Equipment or Tool Manufacturer or Oscilloscope Tektronix 465* Digital Weston 6000 Voltmeter (DVM) (or Volt/Ohmmeter Unwrapping (VOM) Tool the Type Part No. Part like) Triplett Gardner-Denver (DEC DEC 29-135190 505 244-475 29-18387 Catalog #H812A) Hand Wrap Tool Gardner-Denver (DEC A-28557-29 29-18391 Catalog #H811A) Diagonal Cutters Utica 47-4 29-13469 Diagonal Cutters Utica 466-4 29-19551 (modified) Miniature Nose Needle Pliers Utica 23-4-1/2 29-13462 No. 181S 29-13467 Standard 29-13451 Paragon 615 29-13452 Paragon 605 29-19333 16-Pin IC Clip AP Incorporated AP923700 29-10246 24-Pin IC Clip AP Incorporated AP923714 29-19556 Module Extender DEC Wire Strippers Millers Solder Solder Extractor Soldering Iron Pullit (30W) Soldering Boards Iron Tip w949 (3) *Tektvonix type 454 oscilloscope procedures: type 465 or measurements. equivalent, is adequate may be for required most test for some CHAPTER TROUBLESHOOTING 2.1 ERROR SERVICING AND Error logging stores STATUS selected machine Pad (CSP) for certain types errors which will cause logging can Errors The Jam will Errors jam, microcode reasons cause and Service group (i.e., routine), internal the to current a result machine for the a Microbreak 2. Memory 3. Cache Parity 4, Slave Sync 5. 1Illegal 6. Red 7. Memory 8. 0dd Address 9. WCS Parity Parity of is of be processor. to Error Error?* Timeout Internal Address Management Abort Zone Error a in errors. divided machine forced number instruction 1. registers the Constant The types into two of groups, Errors. is the AIDS REGISTERS Scratch Jam 2 be to jam. jump of Unibus The following aborted and to The PDP-11/60 a particular errors and other conditions cause logging: will The two will remaining not logging The cause to an Service Error the Error conditions instruction group current 2. Cache Parity Errort* the Parity Error Abort Register, group and then then causes to Up and aborted; logging be Internal nor to will Address, they occur, but The two aborted. (CPE-bit-7) this the error current condition cause the will not Error Servicing and 2-1, cause error and following be this group; Table Power cause will not Service are: Zone set, to instruction Yellow Errors in will 1. Control not conditions, occur. cause *If jam and Status paragraphs. set, falls instruction to falls the current along is condition registers described, bit into instruction which with are their in the Cache into the Jam abort. If it's to Service abort. logged bit Errors are maps, listed in the Table Location in CSP Register Name CSP(B) LOG Read/Write Error Log Contents Code 160/300 Jam 101/301 Service SERVICE CSP(2) LOG Registers register of status JAM CSP (1) LOG Logging 2-1 register of status 102/302 PBA Physical Bus Register (Bits located in Address Log 17, 16 Service Register) CSP (3) LOG CUA CSP (4) LOG WHAMI Current Microword Address 104/304 FLAG/INTERRUPT CSP (5) LOG 183/303 105/3085 Flag Request Register Address (Status Vector Serviced) Logging Last instructions, internal option of flags status Processor CSP(6) LOG CACHE CSP(7) 166/306 DATA 107/307 Logs Cache data being addressed at Logs Field, Tag Register TAG/HIT Status CSP(11) LOG DS 111/311 at of jam Hit LOG and Valid time Data stored; ever was in ister at the jam time of logs the D time Bit jam whatreg- of the TIMEOUT | ADDRESS TIMEOUT WCSs PARITY RED ZONE ILLEGAL INTERNAL SLAVE SYNC KD (PWR) DISCHARGE RED ZONE SLAVE SYNC oDD ADDRESS o 1 2 3 4 5 6 7 8 9 10 1 12 13 14 15 ERROR oDD YELLOW ZONE UNUSED wCs PARITY MEMORY PARITY ERROR ERROR MICRO BREAK MEMORY ADDRESS MANAGEMENT CACHE PARITY ABORT ERROR MA-0375 Figure 15 DATI UNUSED BG SERVICE 10 11 12 13 14 2-1 DATO TIMEOUT Figure Jam 8 7 9 /0 PAGE/PA 17| DATOB NPR SACK Log Register 5 6 HIBYTE PARITY TAG PARITY ERROR ERROR 1/0 PAGE/PA 16 LOW BYTE PARITY Bit Map 4 3 2 CACHE PARITY FLPT SERVICE CONSOLE SERVICE PWR FAIL ERROR 2-2 Log Service Register 0 1 YELLOW Z0NE MA.0376 Bit Map 2.1.1 The PDP-11/68 following These 16 purpose Error descriptions registers, registers. Floating Point concern, is Those bits their bit Scratch second purpose, for Logging Unibus which are not (CSP@) - or that of processor self-explanatory are Pad, are storing which error are 1logged. is dual special our main information. described below maps. Figure conditions 9, the battery KD(PWR) up. (A instruction Log Jam error register that the bit positions occur in the PDP-11/68. DISCHARGE, is looked may "1" (used means on that INTERNAL tries LOG The processor shows backup ILLEGAL 2.1.1.2 or 2-1 that Bit systems the address an SERVICE (CSPl) - by with battery ADDRESS, to at is caused the memory) reflect PDP-11/680 of the to was jam see good to if upon good.) whenever internal address. 2-2 the to processor set Figure used indicative MOS is is shows a floating point the Service Error indicators. 2.1.1.3 Address are "C" their Unibus bit the which Constants; of 5, in registers is the Bit contained to purpose JAM power apply first LOG jam. Registers Their 2.1.1.1 type Logging LOG at found PBA the in (CSP2) time the of Log - This the register abort. Service The register. contains upper the two This Physical bits of register Bus the PBA may not 15 14 UNUSED 13 12 CUA <10> 1 10 |CUA < 8> 9 8 |CUA K 6> 7 6 |CUAK 4> 5 4 |CUA K 2> 3 2 1 |CUA K 0> 0 EXTRA FLAG 1 CUA K 7> CUA <11> CUA < 9> CUAK 5> CUAK 3> EXTRA CUAK 1> PREFETCH FLAG 2 MA-0377 Figure 15 2-3 12 13 14 Log Current 1 10 Micro-Address 7 8 9 6 \ 5 Register 3 4 Bit 2 Map 1 0o J N~ LAST INTERRUPT MICROBREAK| FLAG 6 CSP MTPI-MFP! (JAM ENABLE)] UNUSED INVALID FLAG 1 SERVICE REQUEST HOT FLOATING MTPI-MFPI FLAG 2 VECTOR T-BIT FLAG POINT FLAG PRESENT MA-0378 Figure 2-4 Log Flag/Interrupt Register Bit Map reflect the group. Since could if logging the instruction LOG CUA (CSP3) microword logging, which this 2-3 shows Bit @ the Log Overlap to is was not caused by the Service aborted in this case, register the jam. not contain set, signifies the time of the signal: processor contains If Micro-Address when at point This will Current control floating - caused register (PREFETCH) Fetch used PBA Error the PBA address of change. 2.1.1.4 the error the the 1log. FLPT PROC is available. be used a the Service meaningful Error caused data. Figure register's bit map. processor was executing Bit H, 1 (EXTRA which (A"1" FLAG specifies means that 1) a is which FP11-E is present.) Bit 2 ing bit. (EXTRA FLAG 2) can 2.1.1.5 LOG register logs the contents the time of Vector at Bit (T-BIT 8 Bits 9 and Move and 18 from FLAG/INTERRUPT FLAG) the when Previous a microprogrammer (CSP4) - Figure of the Flag 2-4 register as shows and a branch- where the this Interrupt jam. set, (MTPI/MFPI by T-bit FLAGS) Traps - The Instruction are Move flags to disabled. Previous perform two Instruction functions: 15 14 13 12 \ 1 10 9 8 7 6 5 4 3 2 1 0o J T PROCESSOR NUMBER LOG CCR <00> MICROBREAK| ECS/WCS WCS ENABLE ENABLE PRESENT FIRST UNUSED TRAP IN PROGRESS FLAG DCS UNUSED PRESENT ECS HOT ERROR LOG PRESENT FLOATING ON ERROR FLAG ENABLE POINT PRESENT MA-0379 Figure 2-5 Log WHAMI 2-7a Register Bit Map 1. MTPI-MFPI FLAG 2. 2 1 ) MTPI ) 1 Control Pass of FD the Double Precision stored 1 )] Force'FD to @ 1 1 FD invalid), the CSP, LOG administration are WHAMI is set (CSP5) - the LOG indicates, if set, logged, if Log Enable Bit (CCR<00>) WHAMI only logs the The Floating Point WHAMI register LOG regarding instructions represents when (bit 9) constants, invalid. information logging Register. FLAG 1 2.1.1.6 13 19) (bit-9) bit. Bit in machine, (bit 1 (FD) 2 (CSP Directly 2 Mode g Invert 11 FLAG MFPI FLAG Bit (bit-10) and some registers the first (bit @) is the status the options internal bit map. that flags. Bit system/processor also set. of bit-8 from the 15 contains are in the Fiqure 2-5 (LOG FIRST) error will Cache Control be Bits 12, 11 and 14 microcode, which servicing. This Bit on 9 processor, is (MICROBREAK a (PROCESSOR NUMBER) a hook For a a for ENABLE), micromatch. in register (Chapter 2.1.4). Bit 7 (ECS/WCS ENABLE) is WCS or ECS. Bit 2 ON ERROR error; it will the MED another the section on Bit @ ENABLE), (LOG tional; WHAMI if it <15>. is it allows set set, until when cleared (Chapter DATA (CSP6) occurs the an cleared specifies logging machine to is set the microprogrammer FLAG) is to environment, see a if specify, description by Instruction clear Bit-@ set, set stay to multiprocessor complete break (ERROR used the it is multiprocessing. when more are error by the trap micro- enable trap MED the causes code, see 2.2). that logging depending first the to time on is the through uncondi- state the of logging flow. 2.1.1.7 LOG CACHE that being was caused by relevant a addressed Service because Error the PBA at - This register the time of then may this have the data jam. will changed logs not the cache data If logging was necessarily since the time shows the LOG of be the error. 2.1.1.8 LOG TAG/HIT (CSP7) - Figure 2-6 TAG/HIT 14 15 12 13 1 10 9 6 7 8 3 4 5 0 1 2 N\ HIT REGISTER TAG FIELD UNUSED CACHE VALID UNUSED MA-0380 Figure 15 14 13 12 11 10 9 N k‘\/‘J k\/"/ \ CURRENT MODE Log 2-6 NOT USED PREVIOUS MODE Tag/Hit 8 7 -/ \— Map Register Bit 6 5 4 3 2 1 0 T N 4 \' C \ \/—'—J PRIORITY " CONDITION CODES J TRAP MA-0381 Figure 2-7 Processor Status Word Bit Map register's contents bit of not be LOG DS (CSP1l1) Hit register relevant register jam. This the may This map. in it different 2.1.2 The also Error register and Status paragraphs information have diagnostic purposes. on Unibus Processor contains information the includes the current condition instruction, Status and be the an instruction to Bits 12-15 (PREVIOUS and These bits indicate the Memory Management unit an register at as well the as descriptions field time of operands the are used for Figure 2-7 - a to at status of the shows This the and the bit register PDP-11/69. and results of the These control current detecting registers PDP-11/60. register. priority, for of of (PSW) It previous the execution 1last of an program debugging. MODE) relocation the The Tag the instruction. and current CURRENT jam. and holds data to be passed (777776) during at D data describing trapped a Field instance. status Word indicator Tag Registers processor codes of that addresses on time contain PROCESSOR STATUS WORD the the the execution of registers modes, in times during following of is a was 1logs Error intermediate containing map the holds PDP-11/60 2.1.2.1 at Service logs whatever The D register memory; a register present 2-9 and protection time (current) mode of the and prior to the last mode on Memory (Trap or Management Handbook, Document 3it 5-7 The central Interrupt) operation Number processor The sor Status Word register Bit 4 The trap the details PDP-11/68 Processor current at any priority bits one of 1levels is eight maintained in of the Proces- program control 5-7. (TRAP) bit (vectoring (T) be instructions through PSW can will be The Condition codes CPU operation. The =1, 1(V) = 1, if if on cleared When =1, if a of processor an trap instruction will and =2 especially useful for provides an efficient method of contain information on the bits set as it CODES) the are operation the as resulted operation the result was result of the last follows: in resulted flow. 2(2) set, completion This under 1is breakpoints. (CONDITION or bit installing @(C) 14 1loaded. programs @-3 set only). location debugging Bits to For EB@06498. operates @-7. new refer (previous). (PRIORITY) priority, occur change zero. a carry in an from the arithmetic MSB. over- 15 12 13 14 \ 10 11 V UNUSED 9 7 8 6 5 MODE PAGE NUMBER ABORT- ABORT- UNUSED READ NON-RESIDENT 0 Y k‘\/—/ J 1 2 4 ONLY ACCESS VIOLATION MAINTENANCE MODE ABORT- ENABLE UNUSED PAGE MANAGEMENT LENGTH ERROR MA-0382 Figure 2-8 Memory Management 2-11a Register 0 Bit Map 3 (N) l, 2.1.2.2 the protection the MEMORY MMR@ hardware Status abort occurred. MANAGEMENT essential from an MMR@ bit map is Bits 13-15 These bits "priority should routine Length are would Abort # abort the Figure flags ignore service Page a are kernal used to management by an memory They to the example, Length routine #2 generated 15, 14, conditions) the contents status and would operating management may be right a determine plus system trap. considered are less Non-Resident Access ignore or 13, when cause the 1logic of MMR8 register MMR2. facilitate virtual enable, to The recovery bits from This the be a significant service control flags. A Access control fault. an 1 to Abort NOTE Bits by 2-8. that For Aborts through memory service - 777572 required Flags. ignored. and (MMR@) Abort in #0 flags, or in REGISTERS vectored Registers error shown negative. STATUS information queue" be was are REGISTER abort recover and result 2549. contains other the MEMORY MANAGEMENT location why if set (Abort to freeze to 6 and done to is abort. Page Bit 15 is set when an access control field attempt is to made address bits the Page Length Field Bit 13 set page having Bit 8 For the when an so It is useful Bits 5 with the Bits 1-3 the if an Bit @ that 6 page is indicate causing the from recovery page with an when an or 4. Bit 14 is a page with a block in outside made the of the area Register to the initial write Memory in number authorized for that a by page. "Read Only" Management unit. diagnostic destination capability CPU mode abort. @ a of number (User of upwards. to reference relocating (Kernel program, = is or Kernel) 00, User identify page the 8 relocated. addresses. = reference. The bit number pags associated 11.) Pages, 1like bit used being is accessed occurs. relocated and protected set the Memory neither is use routine Enable O, in is access 2. page the to of the the 8 to Descriptor final the numbered error abort the to that attempt used made location Page key prove contain are a maintenance only to and Blocks, by an instructions set of is equal 6-12) access specifies is key access (virtual is attempt relocated bit. nor by When the it is Memory Management protected. unit set to 1, Management is disabled all addresses unit. and When it addresses are is are MEMORY MANAGEMENT MMR2 is loaded each instruction fails. MMR2 REGISTER with 1is the 2 (MMR2) 16-bit fetch but is read only; Upon an being set, the logic MMR@ abort flags are cleared. LIMIT REGISTER 2.1.2.3 Limit STACK Register violation has alter memory Bits 15 are value the are The of by lower (400) Programmable of the the at the - stack the will MMRA The beginning instruction not bits 15, of MMR2 contents (777774) to if attempt result (although contents address to fetch modify its 14, 13 or until of the references that limit information. the Stack determine memory of if 2 do not These bits allowed). contain System Address updated write freeze compared always 8 not the will occurred through cleared tion. are abort, Virtual a contents. 777576 the Reset, stack Console 8 bits are not or (256) . For Stack Limit, Start, or the used. Bit 2 detailed more 8 Reset instruc- corresponds to description refer to the PDP-11/68 (777766) - This register, a of Processor Handbook. 2.1.2.4 CPU shown Figure in register ERROR REGISTER 2-9), was included used with minimal 2.1.2.5 Bit be # 1s in a the word accessiblzs PDP-11/69 so only. PDP-11/74 The (bit map CPU Error software could change. (ILLEGAL INTERNAL ADDRESS) - This bit is set when a 14 15 13 N\ 0 1 2 3 4 5 6 8 9 10 1 12 _J \fi UNUSED WCS |UNDEFINED UNUSED MICROBREAK| PARITY ERROR ILLEGAL INTERNAL ADDRESS RED ZONE UNIBUS TIMEOUT oDD ADDRESS ERROR MA-0383 14 15 13 Figure 2-9 11 10 12 g Register Bit Map CPU Error 0 1 2 _ J ' 3 4 5 6 8 9 J W UNUSED UNUSED CPU LOW BYTE PARITY ABORT ERROR HIGH BYTE TAG PARITY PARITY ERROR ERROR MA-0372 Memory Error Register Bit Map Figure 2-10 14 15 13 \__\r MODULE PARITY 12 I\ o 1 2 3 4 5 6 7 8 9 10 11 J —~ UNUSED 1.D. (10) UNUSED ERROR WRITE ENABLE (READ MAINTENANCE PARITY PARITY 1 UNUSED DISABLE ONLY) ENABLE PARITY WRITE GENERATOR WRONG PARITY2 PARITYO PARITY MA-0371 Figure 2-11 WCS Status 2-14a Register Bit Map Floating The Point instruction tries errors 1listed remaining to address in an the internal bit map address. are all self-explanatory. 2.1.2.6 bit map correct of the of only by whether Register an is The abort, set. parity i.e., If a error bits are CPE Abort bit the cache parity error is not set and will be CACHE HIT REGISTER (777752) - This register most recent references by the processor hit; a six A one flow the forced a write. The cycles. All or after SWITCH up. the REGISTER running. A read lower bit numbered are will be read zero bits (0) are only. indicates were hits indicates for The a the more bits are up. (777578) pads. register Abort ones. a bits power scratch This is a the CPU to indicates of program been (1) 2.1.2.8 power has Register. bits undetermined one there Control the miss recent in if Error service misses. read Memory the parity 2.1.2.7 or the Cache handled the MEMORY ERROR REGISTER (777744) - Figure 2-10 shows the It can DATO - be to The is Switch 1initialized loaded this Register from register to the will is a stored zero upon console while load Display the a Register. 2.1.2.9 Figure the WCS 2-11 (Writeable shows PDP-11/63 a bit Processor Control Store) map the of Handbook Status WCS for a Status Register (777740) Register. simplified - Refer to description of the PDP-11/68's microprogramming 2.1.2.160 MICROBREAK REGISTER Register is a the microaddress; next twelve bit capabilities. (777778-Write register when Only) - The Microbreak whose contents are compared with there is a match. The machine will respond in a number of different ways depending on how the machine was set up options and a more Chapter 2.1.3 The and what detailed available. description of the For set up Microbreak conditions Register seec 2.1.4. PDP-11/608 Control Registers following paragraphs contain descriptions on control the accessing of data system recovery from errors, and information. description 2.1.3.1 CACHE capability operation to in a have from cache degraded mode if occur of locations or of cache the note after the Cache Processor Control and (777746) a If data - The parity section found modes, of the and location program execution fail, is possible to bits, Figure using the Force Miss paragraph describing the Force Control Register (CCR). Refer to detailed description Register. for a more system is can proceed. the Handbook allow refe:ence to (see the in cache does to it store has to memory a in cache allowing PDP-11/69% parity, allow to program relocation errors, in a backing registers used User memory protection, recover number all Kernel REGISTER <correct automatically in CONTROL not operating properly. not are turn Miss the of If a off part 2-12 and Bits) of PDP-11/69 the Cache 16 14 13 12 N 1 10 9 8 7 6 5 J/ " 4 \ UNUSED 3 2 1 0 ) UNUSED PARITY FORCE ERROR MISS 1 UNUSED ABORT WRITE FORCE DISABLE WRONG MISS 0 PARITY PARITY TRAPS MA-0370 Figure Bit 7 This (PARITY bit tenance 1is Register up. It is diagnostics and will cause an abort up. It is write wrong (WRITE is diagnostics Bit Map ERROR ABORT) power Bit bit Control on occurs. This Cache cleared error 6 2-12 WRONG only when a during main- cache parity PARITY) cleared on power and, set, will if set used during parity in maintenance the tag, high byte and low Bits 2 3 & byte when cache (FORCE MISS 0 Setting these attempts to forces @ to bits 511. on words Setting both updated. 1) forces invalidate misses & is misses the cache 512 to bits on on reads NPR DATO* Bit 2 1023. forces to the cache and references. forces misses all cycles to main of cache should on Bit on 3 words memory. NOTE Disabling only be either used PDP-11/66 either Bit @ (DISABLE Set by disable the 2.1.3.2 ACTIVE two sets consists of a Register (PDR). all current active is in the tool. The properly parity error handler of as a result REGISTERS eight Active Address with registers pages bits for nonfatal - The Page are required each mode when of Register information Kernel Processor run disabled. These the mode not cache PAGE Page contain current diagnostic of occuring provides used a TRAPS) cache traps as will half half of and always to desired (APR). a Page used as locate to errors. Management Registers (PAR) is cache Memory and Unit Each APR Descriptor a pair and describe the operation. One PAR/PDR set User mode. The mode and the other is (and in some cases, the Word (see Chapter Status it used in previous 2.1.2.1) mode bits) determine of which set will be referenced operating in one for mode cannot access memory. This employed in 11/60 a *Setting either mode to cache the use is memory the one access. PAR/PDR of the A sets of the protection time-shared multiprogramming will prevent invalidate I/0 address 1is program other features systemn. on NPR DATO's for ALL and PDR locations. A specific of each processor set. Refer assignments. these bit for each The addresses breakdowns of to Table following for both the registers PAR (Kernel, 772340-56) PAR (User, assigned 2-3 paragraphs Kernel bit and for to each PAR the PAR/PDR indicate the User modes, ranges along maps. 777649-56) Table 2-3 PAR/PDR Address address Assignments Kernel Active Page Registers User Active Page Registers No. PAR PDR No. PAR PDR g 772340 772300 ) 777640 777607 1 772342 772302 1 777642 7776832 2 772344 772384 2 777644 777404 3 772346 772306 3 777646 777685 4 772350 772319 4 777658 777619 of with 5 772352 772312 5 777652 777612 6 772354 772314 6 777654 777614 7 772356 772316 7 777656 777616 Address Register, The Page 12-bit Page Address the page. The PAR may or as a base pretation tion The be (PAF) alternatively register indicates PDR (Kernel, PDR (User, Page 2-13, contains the specifies the base address of thought basic Figure a of as base function a relocation address. of the PAR 1in Fiqure constant, Either in the interreloca- 7723060-16) 7776006-16) Descriptor control. relative The functions Processor Register, to following of the page PDR; give more page brief details, 2-14, length, contains and access descriptions refer to of the the 11/60 Handbook. & 1 (ACCESS This 2 bit field of particular page. The access in which a expansion, for 2 specify shown paragraphs Bits not that containing the in scheme. information bit Field shown the given operation. manner CONTROL access the FIELD) PDR should describes codes, a page result the shown may in be an access rights in Table 2-4, accessed and abort of or to this "Keys" whether the or current 12 15 1 PAGE ADDRESS FIELD | | MA-0392 15 14 Figure 2-13 13 11 12 - Page Address Register 8 6 7 _ V b Bit Map 3 2 4 \ )l ACCESS LENGTH UNUSED 0 ee—— UNUSED PAGE 1 CONTROL FIELD UNUSED EXPANSION ' 'ELD DIRECTION WRITTEN UNUSED INTO MA-0384 Figure 2-14 Page Descriptor Register Bit Map Table 2-4 Access Control AFC Key Description Function 29 Y/ Non-resident Abort Field any attempt non-resident 1 2 Resident Abort any read-only this page. all 19 4 (unused) Abort 11 6 Resident Read read/write or or abort Keys to access this page. attempt to write into Accesses. Write Allowed. occurs. ©No trap Bit 3 (EXPANSION The ED DIRECTION) indicates expand. A logic relative 0. A toward relative Bit 6 (WRITTEN The W bit it was that the Bits 14-8 The 7-bit word blocks. page PDR under 2.1.4 The authorized direction # 1indicates the logic indicates the which can expand page can the page can upward expand from downward INTO) whether into memory. page has (PAGE PLF been PLF from program with A logic has 1, been in bit written positon into 6, since indicates into. the holds 0 to authorized block length numbers 128 blocks. and Microbreak from The of the pag=2, @& to 177 ; PLF is written in 232 allowing in the control. Microaddress Microaddress page FIELD) specifies The the written LENGTH length engineer 1 page in 0. indicates loaded any the Match Match three and Microbreak different Register Register ways of [K311] provides examining a customer 2ny single microstate. The heart The comparator microbreak break of this feature compares register register is and loaded is a each twelve microaddress microaddress indicates from bit the when they console. to the 2re equal. comparator. contents The of a micro- Loading three UCON by provided is control and WR PROC The @9. are: features Dynamic Testing: a obtained, synch Each time pulse is a microaddress match 1is This BO3M2. at generated internal signal on pulse allows the dynamic scoping of an any UCON selected microword. second the be stopped* in loaded previously the following microstate can clock processor The Static Testing: microword address when B#3M2 is jumpered to E@6K1l on the This feature allows microstate conditions Timing Module. to be accumulated be stopped at normal before just faulty microcode. Once single stepped for closer To single microstep, Module the top advance (M7876), so switch up, one run again, will cause and then to a suspected area of the processor can be reach they stopped, speed examination. flip the bottom switch on the Timing that it points down, then To microword. and allow switch the clock up and to free down Then flip processor will to free downward. the processor the flip the bottom switch up, the top (flip processor and microstep twice twice). run again. NOTE In Single Micro Step, the clock |is This action stopped the immediately Register which are When this be If Flag trap 2.2 MED MED is to the user The MED when bit box #546) the machine will log the is logged completed via bit console 8 four or a for the or WHAMI upon also. a Log machine the bit MED 9 8 in is set various Jam or will the Log halt. Service. Flag are set the machine bit be set via console Examine and Deposit. can bit 8 instruction. occurs 9 a registers Logging WHAMI Flag upon micro-match. AND ITS in will this or the USE to and write read is primarily instruction being the MED for MED many of the internal a diagnostic tool. is a two instruction; the MED instruction code for function instruction a Jam): Flows Maintenance, opcode 2Xxecute break for the MED last 1instruction. being The (u acronym instruction the to INSTRUCTION an before of used). normally set instance MED (and loading (Refer micro-match can was Dump: register, 4. the next microword, microword 3. after will instruction only in word the work User in mode It allows registers. This (#76600), specific Kernel will the first word the second word operation mode, cause a an desired. attempt trap to 1@. to To use the function read, data code the in RA Reading MED in will will be and function codes in be the internal READ Internal Register 1. Load the code of the key. This Register Press the console WRITE Internal l. Load registers the for the MED specifies a write a the register. can also key. be The diagnostic procedures from Switch the performed read/write purposes describe are how to console: the that keypad transfers Register Switch display will display the Register function the read be read. holding of the in function the Temporary CNTRL Switch Register. holding the code to while contents while with desired switch the Console is key the code specifies MAINT used precede Procedure (L)SWR by it desired MAINT specified should function if following register to MED RA; registers Temporary the opcode the via The and 3. into registers 2-1. Press in 1internal read 2. write MED the stored console for Table If written writing from the memory. data directly listed instruction in in the contents step CNTRL key. of the the write The register 1. Procedure Temporary Switch Register with func- tion code of the register (L)SWR key Press the This transfers Register to Load Temporary the written by Press the the the MAINT key while Switch the is of display will written into specified to the write. CNTRL Temporary key. Switch Register. Register holding display in the applicable while desired holding Switch console the it contents Console pressing that with the numeric in the register. data to be keys. the CNTRL key. The data that has been 2.3 A TOGGLE-IN few ideas processor attempt ing to should aid presented in here. debugging The failures in the troubleshooter of course to run the use the methods that are outlined properly, then the user or them with 1. that are load modules ROUTINES run the cache disabled; Cache a. standard and/or that Sweep the diagnostics here. should If try bootstrap before should attempt- these will not load and run to loader & terminator is: Bypass Installing ground. to PDP-11/60 PDP-11/60 a jumper from E@2P2 This jumper must be taken "BUS DIN" prevent damage to microcode will go is off. The Slide & (Force taken into a (Bus safety DIN, off after 14) must until be the in to starting (TRISTATE). loop switch bit The jumper the HALT position. b. Setting bits Control Register to cache, the matically c. 2. When 3 2 Miss (UBA-777746) and a backing stepping Bootstrap/Terminator on Bypass & 08) of the Cache forces misses on reads store reference 3auto- occurs. single 1 power-up. a. The toggle and RK@5 in routines, disk drives Bootstrap/Terminator the microswitches PDP-11/6@0 upon not to have description 2.3.1 If RK@5 the manner, Manual the Overation the the the M9301-YH diagnostics; therefore bypass the operations Refer the to for microswitch cannot console 1is boot the RKA5 operational, in the toggle in CNTRL key. routine: Address Data 301069 012737 p31e02 a00035 201004 777404 901096 gaaeadl l. Load address 2. Press START 3. Wailt 4. Press 5. Load address 6. Press START 5 001000. while holding in the seconds. the of Bootstrap Manual M93@81-YH actions RK96 & the do PDP-11/69 detailed settings. Boot troubleshooter and and to boot determine alterred. and of Module's that here, will Power-up be Installation shown HALT key. 000900. while holding the CNTRL Kkey. conventional the following 2.3.2 If RK#6 the manner Manual Boot troubleshooter and the cannot console is boot the RK@®6 operational, in the toggle in routine: Address Data 0019000 012737 001002 000003 001004 777449 0010906 132737 nal1019 200200 001012 177440 0010614 701774 001016 p12737 901029 200021 901022 177449 001024 0000081 Load address Press START Wait Press 1 99410860. while holding in the CNTRL key. in the CNTRL key. second. the HALT Load address Press START key. 0000060. while holding conventional the following Branch Self 2.3.3 This routine is 188 microwords toggle in check following 36299 600240 200202 P0A776 200204 2000920 2. Press routine pring the Address be HALT/SI key exercises 1If the console in the CNTRL through the display holding observed instruction. key switch It approximately is operational, 000200. START while can CPU. routine: Data Load of some CPU logic. Address This the easy and the 1. HALT/SI an This (stopping switch is the again key. accomplished instruction), will initiate a by by and single step- pressing the the pressing of single instruction step, with the program counter pointing at one of the two instruc- tion addresses. heading (Branch Self) implies, This operation, will occur Echo Routine is simple as as often the as section the key switch is Module and its HALT/SI pressed. 2.3.4 This Console routine a input/output lines. following routine: check of the DL11-W If the console is operational, toggle in the Description Address Data 009290 105737 0080202 177569 000204 106375 020206 113737 003210 177562 put keyboard data buffer to 206212 177566 printer data buffer 700214 105737 2080216 177564 00308220 108375 000222 008766 wait for keyboard flag wait for printer done branch ADDR 1. Load address 000200. 2. Press START key switch while holding in the CNTRL key. 3. Type any key on the LA36 terminal's keyboard. If character key was pressed, it-should print out. If function key was pressed, the stated function should have been performed. 2-31 C sanr ) B ERROR CUSTOMER TURN ON LOG INPUTS AVAILABLE AVAILABLE POWER DC ATTEMPT TO POWER IDENTIFY NO ON PROBLEM L PAR. 6.3.1 POWER SUPPLY PAR 6.6.1 PROBLEM YES DISABLE o/ BASED ON CONSOLE PROBLEM MODE LITE IDENTIFIABLE CUSTOMER DATA T0 FRU CcpPU ‘ YES INIT, HALT, \ START cPU RUN APPROPRIAT PROBLEM PERIPHERAL OR PAR 6.6.6.3 CONSOLE YES RUN CONSOLE MICRO TEST PAR 6.6.3.2 CONSOLE EXECUTE CONSOLE LOGIC, U CODE DOES CcpPU ON PROBLEM BASE MACHINE ENABLE @ 200 INTERFACE CACHE SWEEP YES DCS AVAILABLE CONSOLE —*CPU BR DOT SOLVED MODE LITE NO PROBLEM IN PROBLEM PROBLEM IN MEMORY DIAGNOSTIC . —— PAR 6.6.3 LOC. 200 PERIPHERAL BASIC. — PAR 6.3.3 IF AVAIL YES INTO PERIPHERAL PROBLEM EX: "] REMOVE WCS LOAD BR DOT CPU OR VERY NO CACHE SWEEP & NO ON L/ GO TO ENTRY DCS AVAILABLE INIT NOT INIT" PROBLEM IN YES DCS AVAILABLE ERROR ves | BASE MACHINE MICRO CODE CONTROL, NO M3301 RUN M9301 DCS DISABLE CACHE & CONSOLE RETRY DEP & MODE LITE ON EXAM TO SAME LOGICCROM, ETC. HALTED CACHE OR CACHE INITIALIZATION INSERT WCS NO IF AVAIL AVAILABLE ‘ YES NO PROBLEM IN ADDRESS AVAILABLE DIAGNOSTIC INITIALIZATION OR BASE MACH INIT POSSIBLE CACHE LOAD CPU DIAG m/C | HALTED W/0 USING PTP OR XXDP BOOTING PROBLEM M7875 CHECK WCS —» YES CONSOLE MODE LITE ON B.M. INTERFACE wceCs INITIALIZATION MA-0374 Figure 3-1 Guidelines 3-1a For Troubleshooting (Sheet 1 -of 3) REFER TO M9301 MEM ' 6.5.2.11 SINGLE STEP PAR SWITCH ON 6.3.1.4 M7876 CHECK BOOT DEVICE ERROR APPROP DIAGNOSTIC ACTIVITIES L PAR 6.5.2.1 DAKDC ‘ CASH LOAD g:)AKGDl:\OSTICS MACHINE } ERROR CPU EXECUTE CPU HALT THE LISTING & FIND IF — PAR ERROR REGISTER 6.5 LOG. MED. ETC POSSIBLE TO FIX CPU PROB OPERATIONAL HIT CONTINUE FIX OR BYPASS DIAGNOSTIC THEN UP TO — PAR 6.3.1 BRING y CODE 6.3.2 TO 777 NO . ANY POWER DOWN USE SCOPE YES | LoOPS, ERROR RECTIFY YES ERROR THE LOAD & RUN PROBLEM MEMORY DIAG. SINGLE STEP TO TRACE MICRO CODE DzaMC-B PROBLEM DROP & SELECT VARIOUS sooT YES ° DEVICE OR CONTROLLER ERROR CONTROLLER BOOTSTRAP FROM — PAR 6.3.3 DEC-X-11 FIX MEMORY DEVICE MODULES TO DETERMINE APPROPRIATE MODULE DIAGNOSTIC BACKPL‘;NE' OR UNIT & FIX UNIT TRACE SIGNALS NO ERRORS IF AVAIL CACHE DIAG l AT ALL CHANGE TO LOAD & RUN :;’;::“:’SLEM’ POINTING NO ANOTHER DRIVE l RUN TO A FAILING IDENT FAILING UNIT(0) ERROR TOGGLE IN YES ERROR ENABLE CACHE 1 |—PAR SWEEP IF DISABLED, PUT BACK WCS IF AVAIL, 6525 DQKKA PTP OR DEVICE PAR [ 6.3.1.4 RUN CUSTOMER FIX DEVICE PROBLEM USING APPROPRIATE ACTIVATE SOFTWARE FIX POWER DOWN, CACHE uP M7875 DIAGNOSTIC — PAR 6.3.1.4 SINGLE STEP ERROR YES SWITCH M7876 : THE DEV/CONT POWER DOWN PROG FROM THEN BRING UP ANOTHER DEVICE TO u CODE I KT DIAG. PROBLEM USING SINGLE STEP ETC. — PAR 6.3.1.4 APPROPRIATE TO FIX PROBLEM DIAGNOSTIC * L — PAR | NO 6.5.2.3 YES FIX CONSOLE MODE LITE ON REEXAMINE RETURN ERROR 8 YES DQKTA DEVICE/CONT USE MICROBREAK PROBLEM LOAD & RUN FIX 1 TO 777 NO NO TRY TO BOOT YOUR PROCEDURE SYSTEM TO CUSTOMER CALL REGION KT FOR SUPPORT M7875 * * NO LOAD AND *SF WCS IS INSTALLED, REMOVE IT CONFIGURE TO AVOID SCS SWEEP IN INIT ;. CODE DEC-X-11 *#[F BY THIS TIME YOU HAVE MADE NO REPAIRS THE PROBLEM IS START & RUN INTERMITTANT DEC-X-11 FOR AT LEAST 1/2 HOUR L MA-0373 Figure 3-1 Guidelines For Troubleshooting (Sheet 3-1b 2 of 3) \ ACTIVATE DCS START — PAR 6.4.3.2 SWITCH READ REFER TO ERROR ERROR CODE DIRECTOR PAR 6.4.4.2 REPLACE MODULES IN SEQUENCE INDICATED PROBLEM SOLVED ALL MODULES NO REPLACED M9301-YH AVAILABLE PROBLEM ALWAYS ON INTERMITTENT NO INTERACTION PROBLEM 1ST PASS ACTIVATE M9301 YES |g SWAP ALL ) WHICH TEST YES CPU? MODULES CHECK FOR INDICATED AS BACKPLANE A GROUP PROBLEM CACHE MEMORY? \ NO GET ERROR CODE YES NO REFER TO u CODE LISTING & DOCUMENTATION MA-0393 Figure 3-1 Guidelines For Troubleshooting 3-1¢c (Sheet 3 of 3) CHAPTER COLD 3.1 INTRODUCTION When a system is checked and 1. AC 2. Signal 3. Console The repaired and flowchart be taken can be to AC dc power PDP-11/6@ 3.1.2 Cabling Unibus and PDP-11/60 3.1.3 necessary power and DC on things that should be include: cabling a Figure dead and 3-1 machine fixed with maintenance and suggests to a a some steps at which point field replaceable that the unit, could problem (FRU). Power Cabinet troubleshooting and Power Supply dc) cabling power (ac and Cabinet and Power Console first functions identified and if the START TROUBLESHOOTING cabling bring AC the dc shown 3.1.1 and inoperative, 3 Operation Supply are explained in Manual. is Manual. also described in the 3.1.3.1 1Initialization micro-addresses that Loop (HALT from level INIT #58. To notes the cycling CPU's the will to will START Cache help the Console CPU and bypass following to you Loop go -- Table through switches). sweep to Console refer determine Loop. to 3-1 get This to is list of to the Console list is for Chapter where a you 2.3. are ROM The during Table 3-1 PDP-11/60 Micro-Addresses from INIT to Console Loop 3466 3557 1265 1520 3453 3524 1254 1522 1924 3467 3525 1255 1524 1825 3076 3547 1256 1526 1837 3424 3434 1257 1534 1121 3117 3327 1266 1536 1124 3511 3435 1270 1544 1126 3474 3449 1269 1546 1138 3116 3441 1262 1550 1132 3425 3442 1271 1551 3007 3137 3257 1272 1463 3615 2136 3256 1273 1552 3045 3837 3277 1274 1553 3653 3035 3526 1275 1554 3246 3157 3275 1003 1464 3913 3153 3313 1276 1465 3420 3426 3357 1300 1479 3412 3427 3539 1932 1472 3421 3177 3641*Note 1344 1471 3422 3175 3532 1611 3617 3213 3643 1473 3816 3439 3247 1474 3423 3537 3443 1987 3977 3475 3677 1475*Note 3444 3504 1856 1520 777 1020*Note 1 3 4 3445 3505 1060 1557 1582 3446 3510 1061 1214 1504 3447 3512 1064 1460 1962 3450 3514 1865 1461 3452 3515 10780 1462 34640 3516 1477 15085 3470-%* 3517 1655 1506 3461 3071 1049 1507 3462 3520 1000 1514 3463 3522 1004 1515 3464 3527 1664 1516 3465 3431 1263 1517 3471-%%* 1264 *No op. C.S. **DCS/WCS/ECS Installed 1. Holding shown in the will cause the CPU maintenance Jumper EMA2P2 Console is 256 3 of contains a detailed 3.1.3.2 Console base the must single off in single is NUA is 1lights. = 1024; reset it will be the be Releasing cycle this by to is because unit set 2gain out of mode and to it stop now to get Installation and the loop. cycles. PDP-11/68 operational machine even with used test and codes, be Microtest console, ROM the -- base allows machine that of is the repair 1In particular of it can the be 1is generating is meant to be used only after it has been initialization is 3-2) is not and switches resident generating initialization console and Manual KY11l-P console. permanently checking down. Operation are Table It description This feature and verify (see correct characters. if latch NUA 0777 Loop. Section operate to cause 1121). to 4. that go CPU will clock. Loop verified mode Module's the to keys two microcycles before 3. correct Micro-word though (3615 to START even the the HALT, keys, takes in the the the 2. in the working. display This functioning. diagnostic will not When invoked, the Temporary switch is this Switch the is read. This and left shifted Tne diagnostic cedure l. of then the digit goes back Register. other shows how key to the STD BY 2. Put clock 3. Jumper 4. Turn 5. Remove 6. The 7. When The through switches set to up and PDP-11/68 with by a 1low zero codes order pressed. initiate the turning the in of a key key pad bit <5> Register. keypad are contents Whenever continuously the OFF, the generated Switch then drifting code together Temporary moves display. linked the as Turn seven to into Switch appearance display, code continuously Register pressed, is Temporary diagnostic displaying the then have the of the following pro- 16-bits The console the micro-test. rotary switch to the machine by position. in Bus free to (see Chapter 2.1.4). ground. ON. jumper, (put on in step microdiagnostic through pressing mode, DINK13>(E@2M2) machine console run HALT, using START the key is 3). now running. diagnostic, switches. INIT the Table Octal 3-2 Key Switch Codes Code Key Display Position Display 2 Position Switch 1 Name Not Used *DIAG *BOOT *START *CONT DEP *MAINT (L)ADRS EXAM (D)ADRS (D) SWR * (L)SWR HALT/SI 9 1 2 4 4 2 5 5 2 6 6 2 7 7 *Code generated in conjunction with the CNTRL key. NOTE Damage in to Step 3 hardware is may attached result while if jumper machine is running. The first that the Once thing the jumper the is console removed Jjumper has microdiagnostic from been Bus does is check to see machine is DINK13>. removed the entire initialized. The microdiagnostic pressed. entire It pressed the has service then contents checks accomplished machine requesting then the of been 1is this see by testing initialized the console. microdiagnostic the to Temporary the If proceeds Switch if a keyswitch service. only a thing keyswitch to load Ragister. the has been Since the that has can be not been display with CHAPTER MICRODIAGNOSTICS MACRODIAGNOSTICS 4 (DCS), (XXDP) - MAINTENANCE AIDS 4.1 MICRODIAGNOSTIC The 'DCS' (Diagnostic specifically sor. microcoded internals Error with for PDP-11/60 are of the an executed the to information FAULT 1level, when possible. resolving the benefits of error this and by errors specific micro Proces- control store, the are approach To Memory/I-0O . Direct . Extremely fast . Excellent coverage use the DCS, Device/UNIBUS independence hardware microcontrol the load and and following and execution visibility times resolution hardware is required: within hardware. DCS module; resolved information be: . errors functional diagnostic tool Central datapath Additional a diagnostic isolate provided DIRECTORY, to a word and control 1is is [KD1l1l-K] 2048 detect processor indexed Significant Module alternate an module provided Store) as indication coupled the tests (M7871) Control designed Functioning the - DCS logic are is to also block. seen to DCS (Diagnostic PDP-11/68 DL11-W [KD11-K] Line Clock Store) Central Module M7871 (KUll16-BB) Processor (required) (required minimum) 4K memory bank First Documentation/Listings 4.1.1 The Control available following documentation for the DCS module user comprises the items: DCS User's Guide (portions of which are discussed in this . Chapter) FAULT DIRECTORY Listing; for module level debug replacement information DCS Microcode DCS Maintenance tion on KD11-K level DCS Listing; debug, Manual, hardware Processor when IC Print Set; is necessary for detailed informa- operation Maintenance Manual, Print base machine hardware specific Set; for IC information Specific MAINDEC component part numbers for the DCS documentation are as follows: MD-11-DQKUB-*-D; User's Guide, FAULT DIRECTORY (PAPER, 8 pages) MD-11-DQKUB-*~-LA; DCS Microcode Listing (PAPER, 450 pages) MD-11-DQKUB-*-FA; User's Guide, (FICHE, 4.1.2 The an Loading DCS ECS DCS, the UCS DIRECTORY, DCS Microcode Listing cards) Procedure occupies or 4 FAULT slot 1 in option is present, following Power sequence down Remove the the the KD1l-K it should processor must be be backplane; removed. thus if To load the slot #1, if employed: CPU ECS/UCS option from processor slot #1. present Insert the inserting DCS the module DCS module, require some gentle Orient the DCS 'NORMAL/VERIFY' Now power up the into as maneuvering 'RUN/STOP' switch CPU a to Us2 slightly to switch 'NORMAL' seat to caution bowed it in while board may place. 'STOP', and the Starting Procedure 4.1.3 DCS execution be initiated CPU the KY11-P (If no in “CONSOLE" operator's DCS/ECS/UCS console happens Chapter 4.1.3.2 operator's console while this distinct methods: mode, be (below) DCS is start keys to the -- With (KY11l-P) simultaneously "CNTRL/DIAG" to the to fails method two ("HALTed") effect.) If by the Operator's Console Startup Via 4.1.3.1 KD11-K can start depress the DCS. present, there should be no interprets the display on the executing, and after stops. the to proceed DCS, it the next for some paragraph. 4.1.3.2 to bypass use of reason the Startup Via the DCS Switches -- DCS, used, for an alternative example, in The 1. On the is desired the KY11-P operator's console means is (using procedure DCS it provided. This the event that starting console was not possible malfunction. If "CNTRL/DIAG") to method initiate would be from the operator's due to some hardware is: module, set the 'NCRMAL/VERIFY' switch to "NORMAL' 2. Now set the 'RUN' 'RUN/STOP' switch (on DCS module also) position, or flip it from to the 'RUN'->'STOP'->'RUN' The DCS should now assume control of the KD11-K CPU, regardless of the previous state of the CPU ("CONSOLE", "RUN", or whatever). NOTE If the DCS in the 'RUN' pected have 'RUN/STOP' that no switch was position, the then operator's effect - the already it is ex- console keys DCS 1is already en.abled to execute, and is controlling the CPU. monitor The the DCS microcode does keypad for operator produces a 'RUNNING' indication then proceed to console not input. If neither of the above the DCS (as per methods Chapter 4.1.4.1 the of next paragraph. 4.1.3.3 in Using Chapter processor and 4.1.3.2 "INIT" "START" initialize 'RUNNING' the (i.e., on CPU indication no 'RUNNING' in the power by the Set and DCS and 'RUN'). Chapter is switches as Now depressing console. restart the This DCS, detailed generate the a "HALT" should now producing a 4.1.4.1). now system clocks, Procedure the simultaneously operator's 1logic (see -- 'NORMAL' indication supply, Operating "INIT" signal keys If 4.1.4 Console present, then DCS module, a or problem ?2?27. exists 4.1.4.1 DCS Indications Console -- display should The While the be as "PROCTM" - BLINKing "USER" - BLINKing "CONSOLE =~ OFF "BATTERY" - <indeterminate> digit 06 ON octal 608 any of the ) console 2. The DCS DCs important LEDs: - In In DCS Operator's operator's console follows: DCS hung necessarily Indications indicators in in 1: passes are is an 2-64. not met, inoperable, 'error/scope that While to read: pass hardware The 4.1.4.2 - should conditions 1. (Not the KD11-K Continuously above is the Continuously display 080 on executing, - 6 "EOP' is approximately (.0.0.0.0.0.0) two DCS Executing "RUN" (@ If While either: or loop' order) Executing watch then at this -- On the DCS module, the time are the and 'ERROR' LEDs 'ERROR' '‘EOP' State OFF OFF Probable OFF ON * EQOP ON OFF * ERROR ON ON Probable Note the 'Probable DCS should be 1lit: that nor indicates (e.g., Handling). Both MODE' to indication. 'NORMAL' Chapter 4.1.5 The (if 4.1.12 DCS * that clocks ERROR OFF processor DCS ERROR 'VERIFY MODE' Either or both 'EOP' ON the and/or suppressed) and Make sure 'EOP' intended); (Verify Mode) for 'ERROR' Neither processor are Chapter the standard 'NORMAL/VERIFY' and then further on the non-standard See 1is the DCS or indication indicate investigation. DCS HUNG EOQOP further 'ERROR' is and/or Genuine notation. both this DCS Successful require condition ERROR * ---' conditions 'EOP' Comment 'ERROR' in a 4.1.9 (Error DCS 'VERIFY switch restart HUNG the is set DCS. See its mode of information. Execution Time execution time of the DCS will vary devending upon initiation. 4.1.5.1 "CNTRL/DIAG" started via "CNTRL/DIAG" no for errors, DCS will Start from Operator's Console from the operator's console, execute approximately 6 seconds with console display as -- When and assuming detailed above (64. passes at 100 milliseconds/pass, about 356,008 control microcycles/pass). should return to just been powered up that the machine will actual slide slide end up in switch settings console and successful 'END-OF-PASS' Switches to 'RUN' on the not time, the detailed. When execute for a proceed as 4.1.6.1 1is to reset -- When module, the the of KD1l1-K directly and by the two LEDs end of assuming 'ERROR' has not running situation, thus will appear DCS returned 6 Indications end to of be will the on 'EOP' successful yet been be first continuously. most pass 'ERROR' pass execute until &a2s previously the off. (assuming the In an Note no may and then mode. and 'ERROR’. on. DCS 'ERROR' directly thru the Throughout "CONSOLE" and turned on; for will 'END-OF-PASS' indicated labeled 4.1.6 setting seconds; 'ERROR' each 'EOP' more entering are the via position. above, DCS of time, microcode 'STOP' approximately the the the 'STOP', by at started to DCS on delay 1is detected comes this had Note Chapter the maximum CPU regardless be switch the indications. the to after elapsed, "HALT". will 'END-OF-PASS' at to mode On the DCS Module -- 3Successful on set if indications describ=d module as has execution conditions turned DCS returning switch DCS 'ERROR' DCS 'RUN/STOP' 4.1.6 displays from continuously, switch console Start '"RUN/STOP' time (RUN/BOOT/HALT). DCS and this microcode, the the this KD1ll1-K with interprets 4.1.5.2 the After on the 'EOP' 1is DCS code - error-free that 'EOP' errors), and In the event the DCS turned on, and the latched such in a ‘'EOP' that a ‘'flaky' treatment it The be timing error), Scope-looping. 4.1.6.2 On the Operator's Console 'ERROR' conditions 'ERROR' off thus (Error on the will be LED will be if the error retaining Handling) conditions: -- Successful indicated LED 'ERROR' turned 4.1.9 error Indication, are the cannot various the of error, See Chapter indication of an error. full an LED turned off. way (i.e., disappears detects the for a Detection, 'END-OF-PASS' and console as operator's follows: 1. A successful microcode 64. control, passes by and return to KD1ll-K processor a (.1.2.3.3.2.1) 2. in the in "CONSOLE" An error in pass indicated by a (0 0 in console display, 28060 the and the KD1l1-K processor "HALTed" mode. 2 1 will ) console display. usually (but not always) be An 3. in error be always) 2 pass through -- will wusually (but not indicated by a (.0.0.0.9.0.0) in Note the console display. the gqualifications For a successful in the previous 'END-OF-PASS' only one display control, statements: and exit back to KD11l-K microcode is valid: (.1.2.3.3.2.1) For any module the other display except "(.1.2.3.3.2.1)", check the DCS 'EOP' and 'ERROR' LEDs for the most reliable indication of result of execution. See Chaoter 4.1.9 for a full explanation of error processing. Hardware Restrictions 4.1.7 4.1.7.1 Cache and Memory Management (KT) -- The DCS executes with both Cache and KT disabled: 1. Cache, by setting both the "Force Miss" bits The 2. KT, DCS checks the data paths. internal available by clearing for 4.1.7.2 backup MOS (if Otherwise, detecting fault an Return to Battery must macro diagnostic the UNIBUS to/from programs and Memory The MOS be "Good", or code WILL Backup either diagnostic -- ERCD=5621/TNUA=7400, oare Management NOT memory else battery disabled. execute without "HALT" in TEST62AC. Restrictions Console/DCS mode End-of-Pass Processing is exit the machine microcontrol. l. DCS, upon ONLY This provided action is due from an error, locks up in way that manual operator 1is such a required for DCS back to (and the to: detecting processor) the from diagnosis. micro are: Software The path error. 4.1.8 base basic bit (MD-11-DQKKA-*) Memory the "Enable" Further present) Indications Console most Cache (MD-11-DQKTA-*) the return itself intervention to base by machine microcontrol. 2. The DCS completely processor, alters destroying its the internal previous microstate contents, and of the leaving 4.1.9 The "garbag=2" in power-up "INIT" "clean-up" the Error and the DCS an 'ERROR' use of the The The 11/68 'ERROR' ENUA the after The of TNUA prior all register (12 bits) test control of a DCS to control. of test (12 in is a the EMIT field register of to loaded rom ("BUT") with 1is the the DCS the a the extension the is EMIT field of the bit. It set up "EXPECTED" is micro address executed. loaded continuously as the progress of the the value the "RECEIVED" is valus (17), following: up of DCS microaddr=oss micro executed. from under counts is from the microword, register does to determine it reflect bits) continuously this and the 1local NUA), directly microbranch loaded are (Tracking in- cannot the is which TNUA It fact, after DCS-CNTR NUA), simple. over address The very control DCS TRACKING test is no contains TNUA, returning by has register and to machine clear. microbrancyh executes, of base 1itself This contents full generated terms of processor or under DCS field. This the 1is (Expected 'ERROR'; register microcode ENUA set beginning the in is microword, at sequence registers; setting/clearing whether Thus processor of COUNTER module. place. Handling concept volves 1its DCS every the DCS (80)-(17) rom (octal), extension microcycle. herdware from control. When compares the ENUA if DCS-CNTR=(17) 'ERROR'="1" Set else leave 'ERROR' and ENUA TNUA unchanged from its previous value. This is the manner by which DCS is able to set 'ERROR'. this method. use tests Note also that the DCS hardware "locks up" and registers TNUA after Thus only the FIRST tents. All DCS 'ERROR' is set, the loading of the ENUA their preserving con- There is no 'ERROR' will be recorded. provision to detect subsequent errors until the previous ones are eliminated. See the DCS Maintenance Manual and Print Set for more information. detailed FAULT DIRECTORY Format and Use 4.1.19 4.1.18.1 Basic Structure -- The FAULT DIRECTORY is essentially A tabular summary of all ERROR codes the DCS is able to generate - 23 total of .52 pages. 432 entries occupying Each individual ERROR code entry in the FAULT DIRECTORY contains a short description of the test, and the test. For organized into that module ease of information replacement reference, ascending the numerical pertaining ERROR codes order, in have the to been range 4900 (8)-6777(8) . 4.1.16.2 Basic Use - With an Example -- This section describes how to use the FAULT DIRECTORY after the DCS has been run, and has indicated an error Assume for and returned has the is present purpose the of in following 4616 (Error TNUA 7405 (Tracking EOP=<OFF>, Goin g to the code 4616 to Some general KD11-K explanation ERCD with the processor. that the DCS was started, values: Code) and NUA) ERROR=<ON> FAULT DIRECTORY, be page on 9, information we find entry about the number the entry for ERROR is first 73. fa2iling test reference to the DCS instance TEST 115 A2. to the line where the obta ined: a. 'Symbolic label' which failed, in 'Line number' - DCS microcode located (here, A reference 1listing line - 7412. Note that the test's as A this '"ENUA' same the - number Expected the NUA numb2r failing in the test is 59383). of obtained ENUA microtest this test, TNUA (7412); thus in (7405) the this is not ERROR. case the The remainder tion of the instance portion We now note of find listed specific to 'Module ning note the that in the the TNUA test we as fourth TNUA particular sequence' to - the eliminate the fault(s). out percentages 5%, and may the module IC right of information and are listed #=the slot) ., the percent module 1is ("41"):; are will the then rounded not always is summarized add to up 100%. of information effort column therefore processor choice the nearest the best (scan- locate particular first the To where the that to choices in Note of indicate The etc. exactly to this "#2" to K#, we obtained: contain order module test, information, be in factor" replacing this now columns (i.e., that celled Scanning 7405. choices The confidence module was 3+ fault(s). "confidence ALU top the a the can 3+ correct and diagnosing More inspect/replace, notation this entry. to "slot" in for modules using descrip- test; entries error, These right) was short this obtained of this by a module. column the contains performed DATA-PATH the the left line function we downward it of obtained choices from the the DCS/KD11-K (signified is referenced to a FAULT by the INSERTION "FI"). particular module IC by the notation: K4=E19, E22, E24, E98; K3=E84 NOTE Callout of specific --NOT-- IC's intended on a module is be an to "Exhaustive-Only-These-Are-The-Ones" list. It is reference to a of a module, 1intended specific and give IC's which caused STUCK-HIGH/-LOW functional and to be inclusive of Another type of the hard do not assume list faulty those ADJACENT-PIN-SHORT Again, for to of effort faults. choices area failure during type all provide reference the insertion fault to this the possible IC's. entry is K4904=ALU/CARRY-LOOKAHEAD; of the format: or Kmpp=functional-description-of-logic-block which references (#pp) in notation is not the is a particular KD11-K used available when for a Processor specific test. (#m) module page set. This insertion data Print fault and In the instance of those provided wild-card any octal 7407. These If or when there TNUA, obtained lists under a ("?") obtained given has does not test/ERROR code been used to 7407? entries should be used specific TNUA is not present. listed which matches wildcard entry is no TNUA no about along the with TNUA, an will some TNUA's TNUA CAUSE 4000 DCS functional be for to its the present; of the a The obtained starting .... informa- obtained then test such the (from of following in a match 7401, further any entry, interpretation required. be 7400, nature intelligent that might forced matches match allow Thus also information TNUA digit. a is and above), the character with tion when a the table case: address 4777\ 4756 > an unexpected JAMUPP in UNIBUS function when expected condition occurred tests, a JAMUPP target area 4747/ occur the "standard" 17 | 7400 - > 7361 BUT() for did DCS not 7777 micro-tests 4.1.11 "SCOPE Loop' Facility 4.1.11.1 General Information provided by 1is standard MAINDEC does is code; to DCS allows signals in The 'SCOPE There -- are all The an (three, 4.1.11.2 bit is DCS code zero-in options set up are in the in particular) Implementation used to enable execution. provided program. What the the These and range and ALWAYS the as of in 'SCOPE the loop' diagnostic appropriate test logic fault. fixed be are 'scope' the been to sequence to change have implementation that same on ONLY to been Most the loop' to technician occurs parameters have possible. some user these to 'SCOPE identical execute loop' The diagnostic the effort no loops macro repeatedly this DCS almost -- when size in range microcode tight, of or 'ERROR' and 10-30 as of and is set. the loop hardware. useful, microwords, as was although larger. Use 'SCOPE -- A loop' points are DCS extension check at recognized rom selected by the control points in following: SCCPE123: {possible NEXT, The two will some other functions> BUTD [SCOPE], INO ERROR: "TEST124" [+1. WORDS] J/TEST124 ! ERROR: "LOOP123" [~5. WORDS] comments branch, "ERROR/NO-ERROR" depending upon tell the the user current where state the DCS of 'ERROR'. code (e.g., the 'NO-ERROR' +1. words). backwards (i.e., detected). The number This Either mode switch set code the can be must be enter the loop. mode and the which to sync. this tight the 11/60 processor prints) an oscilloscope, determination of an appropriate The to DCS microcode allow observation cycle speed. and DCS DIAG" the static. ‘'RUN/STOP' DCS the undefined buttons logic were analyzer, logic signal on automatically remains 1in the of the same manner in faulty suspected as dynamnic; but after- feature of the two switches - see 1s ((on enabled. under K6 This user (2) "free" details. LEDs. the module, TIMING allows control. the DCS can now be employed; further then of jump. generally "CNTL was "SINGLE-MICROSTEP/MAINTENANCE-CLOCK" micro-stepped, the are of is entered wards results error enables then this word ALWAYS count the the use processor Static mode of next 1is the dynamic the the 1loop in and 1loop at -- use as the relative 'STOP', requires etc., signals, to The a modes position, the backwards the to point where gives two via case, the words in continuously. set to toward entered through 'ERROR' micro used is falls notation 'RUN' the to page, of switch Dynamic and the "-number" to execute used of up the the processor to be The additional debug single features the BUSDIN/DOUT display LEDs the See Also available 1N if For (approximately) facility condition are | Usually, 20 DCS Manual for (Next-U-Address) LEDs Maintenance the NUA (16), on the 11/60 processor 'point' at NEXT microword 4.1.12 DCS the MODE' operation of indication support 4.1.12.1 Requirements so good that test, b2 the errors a DCS be used module its -- due to and This system to by current. designed to verify perform test/verify DCS other such a Method -- through the counter 'Verify Counter'. At start of value; by the is microcode, hardware to these the detection/ is DCS module, host system. of the (or algorithm) setting to execute the DCS from a Pass', this counter that when microcode, so this of used to follows: module predetermined under good known DCS 'Verify module a also a module, set This the DCS DCS a The or conditioned via a that components. method as requires the position. on DCS system The DCS module due verification the 'VERIFY' are diagnostics, on the error to Hardware DCS associated used self-verification signaled the operation DCS specific not of the the that mode be the the macro Verification to Note executed, mode perform switch (K2). logic. processor 4.1.12.2 to self-check detected not PDP-11/69 can 1is PDP-11/68 and module Verification/Self-Test 'VERIFY known "UWORD' counter a single 'NORMAL/VERIFY' alters 'Pass pass the 12 bit Counter' to the is preset to 'END-OF-PASS' will have a value a 1is of octal As (7777), the DCS or be at executes in 'VERIFY the point of overflow MODE', this (carry out) counter is enabled. incremented whenever: The 1. A microword is executed from page 7, 2. A microword is executed with the 'VERIFY' DCS only DCS bits have incremented at code the number of the Physically, A executes counter only will the low (done To DCS followed: page of the verify mode, this a the 'VERIFY' random, will 'Verify Pass'. per 4095 the only microword DCS microcode. the following uvon cencountered) overflow in be pass;: (depending references module 4-6 counter times used page at microwords successful the 1less Counter' count matches in 7 retained considered once) 2-85 (a These or during 358,008 ‘'Verify is exactly only in / bits Thus between and count be point 'END-OF-PASS' the bits order will overflow run overflow verify more intervals approximately bit asserted. microcode. random 'END-OF-PASS' the bit) scattered, DCS 'VERIFY' verification counter been the the with extension throughout thus before ROM or (12 match. bits), comparison. if a verify which signals procedure is Install the DCS in the DCS switches: PDP-11/68 as detailed in Chapter 4.1.2 Set the 'RUN/STOP' and 'STOP' = 'NORMAL/VERIFY' = 'VERIFY' set: Now 'RUN/STOP' = 'RUN' The DCS now executes At the end of the loop, in which: - An error is forced with specific code 'ENUA', - 'END-OF-PASS' - A At 'TNUA', 'Scope this with Loop' time their a single 'Verify and is Pass' 'ERROR the code' Pass' DCS a micro- values examine is the executed DCS module contents, as LEDs noted for comparison below. To return control to the PDP-11/60 after position: enters repeatedly signaled branch expected 'Verify a 'Verify Pass', 'RUN/STOP' 'STOP' = "NCRMAL/VERIFY' = and 'NORMAL' And then generate a "CONSOLE INIT' ("START/HALT") on the operator's console Only the status described below is acceptable to signal a success- Assuming a known good PDP-11/6A system, any ful DCS verification. deviation from the description (below) should be considered an indication of a fault in the DCS module under test. After a 'Verify Pass', '"TNUA' (7522) 'ERROR' (4255) (Note LED '"ERROR' This the alternating ON/OFF pattern) = (7523) was loaded to force an 'ERROR' indication '"ENUA' 'EOP' indications on the DCS module will be: LED - ON, will 'ERROR' - ON, be the Approx. 1/2 brilliance continuously only instance when LEDs should be on simultaneously. both the 'EOP' and Indications on PDP-11/60 - OFF continuously "PROC" LED - OFF continuously "USER" LED - OFF continuously "CONSOLE" LED - OFF/ dimly "BATTERY" LED - <indeterminate> display = voints (212121), either MACRODIAGNOSTICS 4.2.1 for PDP-11/60 is a a loading of the and 1listed permanent XXDP is loaded for bypass tained 2.3 in XXDP the off. XXDP) XXDP packages User have a group of in Table 4-1. All LA36, etc.), and of the previously stated requirements are The diagnostic package implementing Chapter the (teletype, media. running diagnostic monitor for device package for or (PDP-11/60 name devices console diagnostic 1lit with on be: XXDP catch-all loading quire The should LED decimal XXDP console "RUN" Octal 4.2 the via the Manual, They on packages XXDP a2lready are programs M9301-YH routines. been programs media. patches binary also when bootstrap Complete available packages one stored re- in ona sufficient for rtequired. The module; documentation refer to is con- purposes only. MAINDEC-11-DZQXA. designed for diagnostic The software PDP-11 other used family than is not software; the manner intended any to be compatible nondiagnostic described in the uses XXDP of with the user any other software menual in are not vprovide the supported. The XXDP PDP-11 packages family Documentation must be obtained the for the documents binary diagnostic obtained at are each programs of the separately. same and packages time programs as the They various programs stored However, said the are in only. at in an described. XXDP documentation package, in the rev. same media order to level. package must ensure be that Table 4-1 Device PDP-11/60 Code Peripheral Devices Having Model Description TTM11/TU16 Magnetic TC11/TUS6 DECTAPE RK11/RK@5 DECPACK RP11/RP@3 DISK RK611/RK@6 DISK RH11/TU1l6 MAGTAPE RH11/RP04 DISK 19 RH11/RS04 Fixed 11 RX11/RX91 DISKette 12 PC1l1 High XXDP Available (Octal) Tape DISK Head Speed Cartridge Disk Reader 4.2.2 The PDP-11/60 Diagnostics diagnostics able on all that the described of the XXDP diagnostics the following all diagnostics be in except run the in contained in KDl1-K Basic "DQKDA" - diagnostic program designed faults the KD11-K to the It consists of 524(19) designed and sequenced to detect at a partitioned minimum into four listed Basic Instruction 3. Comprehensive 4. Combine Instruction 4.2.2.2 "DQKDB" - codes and and Tests sections Tests 6 correct is on Tests instructions are Verification of tested the for each program. and identify of 1is a logic the PDP-11/649 tests carefully to identify These logic tests are below: saved (CIT) -- This program checks is decremented the stack, correct. to "RTT" see Both that the all instruction the that priority are placed on the stack and are listings 1in Exerciser register codes appear (BIT) Instruction operations condition they (BCPT) 11/60 Trap Tests PC as suggested "DQKDA" individual major avail- -- unit level. 2. the report, hardware/software CPU that Tests attempt Basic trap Logic a2re is and for and 1. all which MAINDECs processing system. faults in It procedures daztect, central varagraphs cassette. order Operating 4.2.2.1 in following media paragraphs. are the correct the that "TRAP" old on amount, condition the new status and combinations (80023) that which "EMT" trap will trao. 1is used for software debug routines: checked to if tions are correct the it checked. "DQKTA" will stack causes The - all of to module. assumed be is 20@¢. pass the of The passes. memory management are on of the and red zone instructions sre checked Yellow RTT Memory Management memory the and correctly, and that is turned will is back logic. This and the been the check - "DQKAA" Diagnostic is violafor for for between memory management the second on expose and known from first and sub- detection looping also is started earliest enable program may the This service or is off -- replaceable tested, turned the a of the error faults that other 0-124K - sections comprised the cache's on the of a data Bus Exerciser Cache 11/68 is logic Memory Diagnostic series paths Control on of tests the module. -- The 11/68 currently running test will depend Cache which were designed Cache/KT board and The tests are in a logical order such that they build on one another. the bit including field to program on provide errors logic, failures has cache related interface enable detected series Diagnostic management CPU This "DZIQMC" 4.2.2.5 control Also, computer. 4,.2.2.4 to trace the 11/68 minimum the the that program and sequent involving and 1logic, isolate functioning address done. trap. the register representative to RTI PDP-11/60 test 1limit It a is operations. stack 4.2.2.3 program see ODT,DDT, on logic its arranged That is, exercised by previous lowed tests. by address extensive amounts the program. Basic cache operations and data functions. of cache This testing of fault isolation. 4.2.2.6 "DQFPA" - 11/68 Floating -- This PDP-11/60 status program floating registers 1is point and (e.g., rippling reference tests). All ing source, floating bit verification no-operand and single their functionality units option) can be 4.2.2.7 Tests and -- This tionality to - for the the all PDP-11/64 (PDP-11/68 Floating covered testing 1is (PDP-11/608 of not tions PDP-11/62 remainder set arithmetic, all comparison, bit very for the of all tests verify their unique destination, float- correct Finally, are FPU a of tests, for affects. instructions extends instruction 1in tested end Instruction test to alternating (source, the the basic to insure Both "HOT" floating point tested modes. microcode) operand testing. 11/68 program the in performed are side operand "“WARM" selected "DQFPB" of Basic fol- requiring provide Functionality modes destination) n=zar functional are tests, address and (FP11-E basic processor. reference, full the done Unit, first tests should Point accumulators operation are procedure degree exercised Those functioning effective Tests are in FRU and Point testing the Advanced of of all integer to float Both "HOT" microcode) floating point 4-39 floating instruction modes performed. instruction PDP-11/68 basic (FPll1-E units the 1Instruction conversion can be point tests. multiple option) func- and Full operand instruc"WARM" selected for testing. 4.2.2.8 "DQFPC" - Exerciser -- processor instruction complete ment, ware This configurations point checked for floating point interrupts clocks) option) be and selected 4.2.2.9 for floating point and truncate enabled before and condition 1is developed, DL11-W tests. floating point microcode. microcode) tests and the environ- common Every point soft- conceivable the response interaction betwe~n and/or correct (PDP-11/68 in interrupts, 1line floating exerciser the 2ddition, 1Instruction program instructions insure and base XWll-P programmable processing Both floating machine by both "HOT" point the (FPll-E units can testing. This - 11/68 program add, patterns are are is operated mode, used double with Point exerciser multiply, as the to and insure program of pass" will run indication, the hardware obtained correctness. floating and PDP-11/60 instructions. and results single the divide operands, underflow The ADD/SUB/MUL/DIV for and against routines in and "end an checked software an Floating subtract, disabled. giving an to results is in for tested point PDP-11/68 exerciser basis the "WARM" -- floating the of Unit PDP-11/6@ set execution, "DQFPD" generated instruction instruction and number This In Exerciser Random as Point the correctness. also machine contains combinations error (using 1is Floating exerciser. point various floating base program floating using 11/686 mode, overflow for so 488 (8) that from The round conditions "subpasses" a sufficient number at of this random time, operands (FP11-E units patterns optional selected option) can be be for on - DL11-W Diagnostic 4.2.2.11 "DQKDC" - 11/68 Series CPU be a comprehensive cluster. The modes includes and memory program deselected, the (0-124K) . Also, using available Since worst cautions must be "DZKAQ"TM the Fail 4.2.2.13 diagnostic rom redundancy Also of random Both "HOT" floating wvoint console. the -- This PDP-11/68 program 1is s=ries CPU 1instruction in traps, interrunts, floating the Unibus 2and deselected, the address Massbus. code RKO5, RP#4, RS23/4). occurs with all ensure the protection 11/68 Power Fail Test If will switches to point, throughout program -- all not memory relocate down, pres- of user disks. This test checks out System. "DZIM9A"TM program bootstrap of test testing - types microcode) the (RP@3, taken operands. each relocates not disks 4.2.2.12 Power if case for memory, program the Exerciser check executes tests management, on as testing. "DZDLD" to use the (PDP-11/68 4.2.2.10 designed for information printed "WARM" selected obtained status can and are - 11/68 1is intended modules. character Bootstrap/Terminator and The a to verify program Diagnostic -- This the rom contents of computes and checks cyclic longitudinal parity character a for the the in an M9361 or M9400 module. contents of the rom storage available A separate of the routine included rom storage on allows the user the teletype as an aid Unibus System Exerciser to type the to debugging. 4.2.2.14 “"DZKUA" - 4.2.2.15 "DZKUB" - Unibus Exerciser Module Diagnostic 4.2.2.16 "DZMML" - 4.2.2.17 "DQM9A" - for the M9301-YH 4.2.2.18 program MS11-K Memory Tests PDP-11/68 ROM Bootstrap/Test Program - WCS Diagnostic to used for intended 11/68 be -- checking store option of the PDP-11/60 processor. It verify that the WCS operates correctly and fzaults that may occur therein. The WCS is a ability to do loaded and tions from 4.2.2.19 Chapter PDP-11/67% his stored the 4.1. (Listing Module) "DQKUA" is MOS contents own in base "DQKUB"TM option that WCS and executed WCS diagnostic the writable has been attempts provides micro-programming. the The the control designed to to diagnose user The micro~-code upon specific with an can be instruc- machine. - KD1l1l-K Micro-diagnostics -- Refer to 4.2.3 Peripheral Diagnostics Diagnostic programs for peripherals and I/0 devices in the system are listed and described in their associated maintenance manuals. \ o- #* - o = S 88 559.%RE&88 0%35 fo. =4 o 0 WM N 2C o> -] -w - — e\ o N (=] 0 -4 " pANEL \ ol (=4 0 MA-0404 Figure 5-1 KY11-P 5-1a Console Location Exploded View CHAPTER REMOVAL 5.1 No REPLACEMENT PROCEDURES INTRODUCTION special most procedures are required assemblies of the components and Cabinet or processor mounting procedures for removing and the required to disassemble Cabinet and Power removing and replacing Module Removal 5.1.1 The AND 5 multilayer lock/release and center The card inserted the and modules handles, guides gquides at Supply an that in each the slot the the great that Even though these and the modules carefully. 5.1.2 Console Refer to assemble detailed and H7429 outlines and to Corporate the the the steps PDP-11/69 procedures power on supplies. PDP-11/60 in the backplane to be modules module features are are with has edge card installed are or equipped not removed or slots are connector provided, easily. always install Disassembly Fiqure the modules modules that damaged. remove boxes Section Refer for reassemble PDP-11/6#"'s This console. and Replacement allow so the replacing BAll1-P ensure angle disassemble in box. Manual used and to 5-1. console: The following steps are required to dis- To l. Turn 2. Remove front 3. Remove the power OFF at two screws Plate. 4. Lift console 5. Unplug the console filter remove frame, the unscrew up four The following paragraphs and the equipment sticker provides wire-wrap shows 5.2.1 The the current Mechanical Mechanical handle side of ECO Status Status each Console the KY1l1l-P from Jl. board the of rear the Change from the Module Order serial number, about the revision status connector The system module the frame. sticker. information devices; secure circuit describe Status complement on that the console frame. STATUS Engineering Mechanical from connector screws CONFIGURATION the away printed EQUIPMENT sticker, D) harness board 5.2 (MUL) breakers. (Item and console console's the circuit panel. Mounting the the of Utilization (ECO) MUL status sticker List sticker, 1lists etc.; the ECO current ECC status status (Mechanical the module. see Figure 5-2, box. A the status of Status) Sticker sticker, BAll-P mounting is letter located on the designates the MECHANICAL STATUS BOX TYPE REVISION LEVEL AT MFG. FIELD INSTALLED MECHANICAL ECOS ECO NUMBER MA-0369 Figure 5-2 Mechanical Status Sticker koo sarus e Device_@_ Ser. No._@__ NO/DATE|INIT, A COMMENT 4 A DECI12 -(7176)-11097-N172 11-1498 Figure 5-3 ECO Sticker MODULE UTILIZATION UNIT SERIAL UNIT SERIAL vt SERIAL SU .6 ¥ v SU. =5 su =4 [ | 2 ‘ v\ UNIT ¢ SERIAL DATE INSTALLED —=Twen| konk v src/ \ DATE INSTALLED | | | FLOATING POINT P ey FPHE -~ - |~ CENTRAL PROCESSOR XCS Jrow — e Y M7881|M7880|M7879|M7878|M 7877 b M7876|M7875M7874|M7873[M7872]M7870] A FALU | MuL-| Ex- |FNualsTaTs|TiM- | k17 [pata|oE- | u |wcs NET | PON ING lcacH lpATH JCODE JWORD} [ NOTT BUs | BUS OR e _\ /4\ _ \3 DATE INSTALLED 4 DATE INSTALLED DATE INSTALLED | sysTem N\ SYSTEM SERIAL% \ spc | spc | spc N B BE 20 BB I INDICATE NON STANDARD VOLTAGES PRESENT B B C D \ E \ : K U.S. PATENT NUMBERS 3,614,740; 3,614,741; 7,710,324 11l Tol Joo| los| o] Jos| los| Jos] Jos| Jo2| Jor 3614309 MA-0394 Figure 5-4 MUL Sticker (Base BA11-P) MODULE UTILIZATION | SYSTEM ¥ ) UNIT UNIT UNIT UNIT SERIAL SERIAL SERIAL SERIAL DATE INSTALLED DATE INSTALLED DATE INSTALLED DATE INSTALLED SU.%6 SU. #5 SU. =4 | svstemseriaL / v | oate INsTALLED 4 UNIT UNIT SERIAL SERIAL DATE INSTALLED SU. %3 N DATE INSTALLED SU. #2 SU. =1 row A CD B C 24 e E F 29] 128] 271 3614310 260 125] 24l 23]l lo2 21 201 |19 18 17] hel bs |14 13] |2 11 |1o 09] o8] fJo7| Josl [los| loal lo3l lo2 01 SP MA-0395 Figure 5-5 MUL Sticker (Expander 5-3c¢ BA11-P) revision entered 5.2.2 level as at manufacturing. Status The ECO Status on the rear Sticker, center This wire-wrap devices Table describes the 5.2.3 Each to Module module module from frame such is Figure member filled as the the the out wvarious for 5-3, of KD11-K responsible with circuit shipped from is for or is located is PDP-11/68's installation the columns filling 1installed letters from the module. revision F of the module revision E of the module out and the Module These stickers, be located corporate of ECOs various system are be out to these of BAll-P in Utilization boxes; in the (except revisions factory, on to units. filled out items. to the actual handle. When scratch for a G, and 0) module. When 2 revision letter ECOs revise For example, if an ECO corresponding to was installed and an ECC corresponding to was not E would remain List (MUL) Sticker Figures providing a 5-4/5-5, quick, the the that field, installed, off I, the letter shown alphabet schematic stamped are 5.2.4 the the modules the in is how stamped production scratched should ECOs various 1is shown sticker department record ECO's Sticker cabinet. and installed performed. ECO 5-1 Field letter appropriate F would be on the top intact. are located convenient the various equipment located within the system. tabulization of Table 5-1 Completing the ECO Status Sticker Item No. Responsibility Description Production Option designation code for applicable device. Production Davice serial number. Production Original wire wrao revision letter (e.g., ORIGINAL REV. B.) Production/ Numerical portion of ECO/FCO number. Field Service¥* Production/ Installation date of ECO/FCO. Field Service* Production/ Tnitials of person installing ECO/FCO. Field Service* Production/ Necessary comments about ECO/FCO or Field Service* its installation, installed). (e.g., only part 2 *If an option is installed in the an ECO responsibility for filling out an the field, field add-on through NOTE: door sticker. service will production If fill the has option 1is items 4 out 7. ECO of in factory, Status the Sticker mounting is boxes. located on the inside of the module Additional information such tios, installation of and sticker. to be filling Table filled out 5-2 out the as partial describes and various serial the indicates items. number, comments, ECOs is also manner in which the department technical shown the on sticker responsible the 1is for Table 5-2 Completing MUL Sticker Item No. Responsibility Description 1 Production System Serial Number, Unit Serial Number 2 Field Service Acceptance customer 3 None Not 4 Firld Service Date of installation at site Used Comment area. installed, laneous Note partial ECO/FCOs ECO/FCOs, information about miscel- module or slot. 5 Production/ Field *To be filled device type as installed. Service* out by installed. If service complete will Enter option production or device these if is items. option an or add-on device in the is factory field, field DESCRIPTIONS, REMOVAL AND REPLACEMENT OF ICs 5.3 IC Descriptions 5.3.1 The following (ICs) Circuits Integrated described are in this Section: (74161) 93516 Synchronous 4-Bit Binary Counter 74189 64-Bit Random Access Memory with 3-State Outputs 74194 4-Bit Shift Register (74161) 93516 64-BIT RANDOM ACCESS MEMORY 74189 5.3.1.1 64 Synchronous 4-Bit Binary Counter memories active-element bit transistor-transistor logic (TTL) are (Figure 5-6) (Figure 5-7) - These Schottky-clamped monolithic arrays organized as 16 words of They are fully decoded and feature a chip-enable four-bits each. input to simplify decoding required to achieve the desired system organization. the memories feature p-n-p input transistors that low-level reduce the -0.25 milliamperes, standard load one-eighth only factor. The to requirement input current that chip-enable of a circuitry a maximum 54S-74S Series is of implemented with minimal delay times to compensate for added system decoding. The three-state output collector with the combines the convenience speed of a totem-pole output; of an open- it can be bus 74161 SYNCHRONOUS 4-BIT BINARY COUNTER (Cont) TYPICAL CLEAR, PRESET, COUNT, AND INHIBIT SEQUENCES CLEAR ' I ILLUSTRATED BELOW IS THE FOLLOWING SEQUENCE: 1. CLEAR OUTPUTS TO 0. 3. COUNT TO 15, 16, 17,0, 1, AND 2. 2. PRESET TO BINARY 14, 4. = —_——_— INHIBIT. (ASYNCHRONOUS) I | LOAD I - | A | - ] | I | B DATAJ | r~ If 1 INPUTS — - e —_ e - — e e = — o o = - —= - - - - —_— —— — —— o T, | c D . I —l T | | : _ - - - = - = - = = -_——— e eo e e e e e e e e T——___ |I Lo - ——————— e = e e e e — e - - - —————_——— | ll'llllllllllll'lllllll cLOCK { I ! [ | cLock ENABLE P ! } ! | ENABLE T i 1 il 4 Ca - ——-—_—— — — —— Qg “c . o I [ | l | | I[ | | iL .| 1| | | I | ] | fi _____ 1 i 1 ' | | | I } | | ! | | OUTPUT | l ——— == I I RIPPLE CARRY T | I | | ourpurs< ————— I[ ! 14 CLElAR PRLSET 15 16 lle I I 17 0 ! ! 1 COUNT 2 | + INHIBIT ———— & IC-741618B Figure 5-6 74161 Synchronous 4-Bit Counter connected to other similar outputs, yet it retains the fast-rise- time of characteristic the TTL totem-pole output. (15) 64 BIT MEMORY e ADDRESS INPUTS (1) ADDRESS 1 OF 16 MATRIX BUFFERS DECODERS ORGANIZED 16X 4 (14) LD (13) CHIP ENABLE (CE) {2) ———Q WRITE AND SENSE (3) READ/WRITE (R/W) AMPLIFIER CONTROL ——0 o] (D1 D2 DATA INPUTS fi D3 P4 12 _q WB ENB D3 o) (6) (10) (12) (7) Y1 lZ o] (4) (5) l3 o] - (9) Y2 (11) Y3 OUTPUTS V Y4 J 11 M3(1) 745189 10 —Q D2 M2(1) 6 9 7 —C D1 M1(1) 4 5 ——-Q DO MOo(1) A3 13 A2 A1 14 A0 15 1 MA-0368 Figure 5-7 74189 64-Bit Random Access Memory 5.3.1.2 The with 74S194 74S194 left accomplished contains an is 4-BIT a parallel shift by SHIFT and REGISTER 1load, right positive-edgs inhibit function (Figure parallel shift output, capability. triggering. and 5-8) direct In shift register Clocking addition, overriding clear the input. 1is IC 74194 4-BIT SHIFT REGISTER The 74194 is a parallel load, parallel output, shift register with left shift and right shift capability. Clocking is accomplished by positive-edge triggering. In addition, the IC contains an inhibit function and direct overriding clear input. MODE CONTROL SHIFT RIGHT SERIAL [10 St . 03 IOS Y] o]} 04 DSR 15 RO (1) D1 PARALLEL 74194 INPUT lOZ R1 (1) N 14 > PARALLEL INPUTS OQUTPUTS 05 26 D2 R2 (1) lp3 R3 (1) 13 |—12 ~ J CLR VCC= PIN 16 GND= PIN CLK T I DSL o~ SHIFT @8 LEFT SERIAL INPUT MODE CONTROL s1 | so PARALLEL LOAD H H SHIFT RIGHT (IN THE DIRECTION RO TOWARD R3) L H SHIFT LEFT (IN THE DIRECTION R3 TOWARD RO) H L INHIBIT CLOCK (DO NOTHING) L L IC-74194 Figure 5-8 745194 4-Bit Shift Register 5.3.2 Removal The PDP-11/60 four layers and Replacement modules consist multilayer etched two (power ground) of etched circuit external and ground planes form and ground planes, providing and reducing One advantag2 the need component to board. IC a the using route and eliminated, 1in allowing and layers (Figure decoupling this and type of signals etching on two a greater much the2 noise module The inner the etched and/or outer component each etched and power power circuit cross-talk. construction to The planes, between betw=2en of boards. internal 5-9). ground the circuit capacitor shielding possibility powsr via ICs are two layers of 1is that individual boards density on 1is each L~~ A1 A A1 A1 A AN A A A A1 A A1 A1 A1 A1 A1 LAYER —»( %— GLASS EPOXY ) P 5.3.2.1 Location of ICs -- physical location of the last in locating The first layout ICs during sheet showing of the When possible, these spare that if tions are When spare locations tion has number must also an IC a be the are as on a as end row is the is ICs and discrete on most boards a space change on the more ensure involving addi- each locating ICs on board. because number of the numbered IC locations IC of location at spare spare an loca- locations Thus, ECO), into the locations, on easily. module, the physical basis, The other aid us=d; 1ICs. all to not available orders) a are the (e.g., the components of board board, E-numbered schematic implemented one of troubleshooting. circuit provided when the well and the be like preassigned Thus, board, can just to each 1locations they handle in (engineering counted added of provided ECOs required, installed. the IC locations, future is assumes some IC module location module. the maintenance each that On the 1IC it is end of which handle always when remain the Same. 5.3.2.2 IC Connections power and/or ground Figure 5-18A. The layers in manner easily replaced. this -- inner ICs and to IC and layers component are components allow the connections normally are IC or made connected compcnent as to to the shown in the to be inner more When a component is tied directly to an Figure of connecting instead 5-10B, layer, inner through an as shown in shown as etch in Figure 5-10A, it is difficult to remove the component because most of from the preventing the the layer, IC heat from melting. soldesring solder iron around To minimize this is absorbed by the inner leads of the component or the difficulty, direct connections to the inner layer are made by a vein-type connection as shown in Figure This 5-11. type of connection the reduces connected between the plated-through hole and the inner layer. the transfer to the inner 1layer amount of heat to the plated-through hole when melting applied ing component been removed. leads, or removing excess solder This reduces when solder once area heat and the 1is remov- lead has ETCH CONNECTION CONNECTION MADE TO GROUND 1c LAYER\ ) éL\ \\ _ N\ \__) N\ ) NO \{\ TO CONNECTION INNER PLANES \ A. NO NORMAL COMPONENT PLATED CONNECTION CONNECTION TO INNER GROUND LAYER—\ SOV CAP AN AN QA NN CONNECTION AT INNER POWER LAYER CONNECTED . MADE TO LAYER v T PLATED DIRECTLY HOLES LAYER Z_INNER GROUND CONNECTION MADE TO__/ B. COMPONENT TO INNER THROUGH TO THROUGH HOLES INNER LAYERS 11-0961 Figure 5-10 Component Connections to Inner Layer COMPONENT LEAD INSULATING LAYERS PLATED THROUGH HOLE INNER GROUND PLANE CLEARANCE HOLE THROUGH THE INNER PLANE | VEIN CONNECTION BETWEENSINNER PLANE AND PLATED THROUGH HOLE 11-2300 i { Figure 5-11 Made Top View of Component Connection Directly to Inner Layer 5.3.2.3 IC etch plated-through and and should be layer modules, taken ponents. use during The Small in layer should board, be list the Utica so and their equivalent) and type of of and pvart the extra care of the multi- unsoldering are ICs Because small, repair soldering replacement on com- recommended the number for multilayer of each tool below: Utica No. 47-4 615 Replacement of ICs -- To case to preclude damage to the multi- IC and procedure strictly are -- 23-4 a plastic the eyelets Paragon No. and Replacement when cutters, No. and maintenance (or and iron, Removal replace the manufacturer Soldering and hole tools diagonal Pliers, Removal especially removal indicated 5.3.2.4 during Certain modules. are Component adhered described Plastic by Case Figqures 5-12 remove through 5-18 to. ~— _~— ) o, XN Y '/‘%”éz’}: /4 / ! \) > \ MA-0385 Figure 5-12 Removing a Defective 5-19 IC From Module e NE JE e EE S ) A AN BA :i ~ H_ H H A - BA S O S < \F :\ ;EE N N RSE-R=R=0 ;SE :)\ A g kS - B RMESHES = — — HF NS — = B4 SHfRe—= Y Y i Y 2 Gl Y Y : fi_'E ‘AEEERERERER %%:3w<4::x3 ) \\ ' IC Defective 5-13 Removed "] Ralkabalsl zzz»vfivfl“ Figure fi—-E g__E A E E fi 4 E fl S N e Figure H H d~ P:\ Removing 5-14 IC \\ W Leads u =X d :\E H A A }EE -N HNN ;fg= N N R N ~ N 3 \4§§§§S 3 RSHISHES SRIE ~F = S~ < a_—E 5_—5 i g—‘E R E TF = T \\ . Figure 5-15 IC 5-20 Lead Removed A A0F 408 R0F RO ADSEERES RN BN R ¥R NN BN R L= R\ o) — o R ) =3 NN B N ‘ I~ = A A H ~ B3A SC F g\‘: A A B A P_A . ~. NN DEE :J% NS :'EF X N S ENCOYED O\ N R& — - ;\ - 4 o fifim)d’%fifim flflfl§E§E§E§EMMI1nW - MA-0389 N s A F 4 Sl N 7 ? 5-16 Applying fi:fl_LF DE B )= [= Figure == S 4 K5 BSH e P_H SRS £ S NN %__,:;%_S PH AULPS to Refill Eyelet AORSERAH 4] R 3&@ H Solder X a\\ B%—/@J:\o =S ) ¢ =3 " > o S fifi_fiWT\fi\.fifim FETETEAET BT B B o> M M MA-0391 Figure 5-17 Removing Excess Solder From Eyelet Lod)E s A ROF e — = 108 A0\ AR = 405 Sl2 cIN H bB3rVEN 3:\5: §H SI ESH ~ BXF E A b RS A F A -;;E h ~Ad px S §§ 2 X N o] = o—"\ RIS NN i o—o0 ‘{;- ) D ~ =\ “Hl: S—0 3% §:§==fi “ —£ o J ) ) N £ flflflfiEQEflEQEMMI\A\rl Figure 5-18 IC Location Ready For Insertion of New IC Defective IC leads are cutters (Utica, Part body of the as removed more IC location IC leads leads of IC clipped, No. (Figure 47-4). possible to 5-12) using small Cut the leads as allow the remaining close leads Apply after the the in IC IC the just has IC been leads removed removed still on the being removed from side 1 lead until the lead by the to be with the Locate the easily. still heat to leads (Figure in 5-13) the board. soldered (back) side board and cut all leads to avoid difficulty during their IC diagonal the to the lead pinching 615) and pliers with (Utica, the of the iron the removal. (Figure 5-14) Then remove loose. becomes soldering Part No. board, of (Paragaon, Part No. 23-4). CAUTION are Leads that layer require the heat It to heat to add causing more solder in the because is absorbed by the is helpful first more much inner of layer. solder to the to be conducted heat the inner an to connected eyelet around 1lead the lead. Lead directly iron and after pliers, removal (Figure from 5-15). the eyelet using the soldering After all of the excess new IC. after the IC solder This all the leads remaining figure leads heat of plated-through Once the Figure eyelets 5-16, extractor no keeps shown connection to applied. However, layer made, the are solder heat module sides IC the location (Figure 1. be after being applied being The to 5-16) remove inserting to extra applied refilled using 5-17. inner side cases must the the eyelets solder absorbs directly a of the soldering 1In direct from as to the etch thus, described iron figure, to connections side the opposite 1layers. position to of to the side In allow eyelet the this 1in solder solder which one and the the to inner vertical this module applied the solder, the where be with layers; of extracted in module solder from board 1in be prior removed. Figure same heat eyelets solder properties should of the must sinking the the from (Figure the been been in extracted removed, holes. have remove as it been in shows have excess the and have has can be heat is the inner module and due to the case, the access to both simultaneously. all the eyelets have been cleared of solder, excess solder 5-18). Inspect the eyelets to all the solder is described in Figure 5-16 remains. hole again as If as procedure described as in required, ensure Figure until that not no removed, and 5-17. all of remove refill the solder Continue the the eyelets this are cleared of excess Use a cleaning of any excess solder. solvent solder and brush inspect the IC for splash and damage through holes. Ensure that none replacement IC of in placement IC into opposite side of the IC easier, clean the IC location flux. Thoroughly solder to the the is be surrounding lines bent, When avoid it and etch holes. module; should to leads place, the location and the makes plated- insert 1inserting bending this and the the re- on the leads future area removal of necessary. CAUTION If the in position for the leads more than 45 one 1lead at each the IC. only leads opposite Solder in module. good sides the Use cause a IC enough to on hold avoid the end the to fill using an the top side under the body IC bending degrees, from solder Avoid short bent soldering, new overflow be of connection. prevent could must using and on opposite the side holes and excess of of board, of the the IC. of the make solder a to which Once the all defects made, Take necessary corrective action found. that are CAUTION After faulty short and installing the ECO or IC on circuit ground a module, exists planes of replacing a ensure between the that no power the module. this before replacing the module equipment. clean and Cut off IC leads close inspect the area for any damage. to the board. are connections solder Do in the for any
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