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Document:	VAX-11/780 KC780 Console Interface Technical Description
Order Number:	EK-KC780-TD
Revision:	001
Pages:	85
Original Filename:

OCR Text

EK-KC780-TD-001

VAX-11/780
Console Interface Board
Technical Description

digital equipment corporation - maynard, massachusetts

1st Edition, March 1978

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:

DEC

DECtape

PDP

DECCOMM
DECsystem-10

DECUS
DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

RSTS
TYPESET-11

UNIBUS

CONTENTS

Page

CHAPTER 1

INTRODUCTION

1.1

SCOPE ...ttt
crte s serae s s erae s ssbae e s s ae e s st ae e e rbe e e s beee e s bbeeennes 1-1

1.2

1.5

CONSOLE SUBSYSTEM OVERVIEW........ccooviiiviiiiiieiiieeccriee
snneeennn 1-2
CONSOLE MODES........cooiiiiritiiinirireinnirreeecnnineessnireee
e snnseneees rerereesnreeeranens 1-2
VAX-11/780 CPU STATUS ...ttt
et e esinressstte e s srse s sare e nns 1-5
PANEL FUNCTIONS ...ttt snrenssiresssiaeessineessiree s ssnneesennessnns 1-5

1.6

ID (INTERNAL DATA) BUS OVERVIEW ................... RPN
£ |

1.3
1.4

1.6.1

ID Bus Structure and Operation ...........ccccceevieeviiiiiieeiisicncciiriieee
e eeesnneeeeees 1-7

1.7

VBUS OVERVIEW ...ttt
sttt sssiree s sesntee e s s sntae e s s ennsaeeenn1-8

1.8

Q BUS OVERVIEW ...ooiiiiiiiiiieeniniiree
ettt sssirree s seabbee e e s earaee e eenns 1-10

CHAPTER 2

CIB FUNCTIONAL DESCRIPTION

2.1

CIBOVERVIEW.... ..ottt sttt eirae e s s s e e s e nveee e 2-1

2.2

CONSOLE/VAX-11 INTERACTION VIATHECIB ..........ccccovvvriviirriiieninnn, 2-1

2.2.1

VAX-11/780 CPU Status: Halted and Running..............ccccoevevverveninnnn
e,2-3

2.2.2

LSI-11 Operating Modes ...........ccoovviriieiiniiiieeiiniieeec
et
s 2-3

223

Use Of CIB REZISIETS .....uvveeivviiriiirreieiieecitteeiteeessnerecsinreeennrreessnsreesnnseesinns 2-5
ID BUSREGISTERSON THECIB .......ccoooiiiiiienitreccree
e siveee s2-5
System Identification Register...........ccccvevviiiieriiniiiiiriciineiee
e2-5

2.3

2.3.1

2.3.2

Receiver Control/Status Register.........cccccvvvveernieeniiiinniiinniienneennneenreeeenes 2-5

233

TOID Register = R/O...ccccuiiiiiiriiiiiiiiciiecciecstees
et
eanee 2-5

2.34

Transmit Control/Status Register .............cccevviiiviviviviieecniiernree
e, 2-6

2.3.5

From ID Register = W/O ......cooviiiiiiiiiiiiiiiicciec

2.3.6

Use of the TO ID and FM ID RegiSters ...........cccovvvviiiiiiiineeeiiiirreerenninieeeins 2-6

e 2-6

QBUS REGISTERSON THE CIB........coooiiiniiiriiiiiiiviinnie
e e sreeseree s 2-8

24.1

Read Only MemOTY.....cccvvviiiviieeriiiieiee

24.2

ID DATA LO and ID DATA HI Registers...........ccoovvvvvrieniinireeiniinnieeeinnens 2-8

ettt sanesesnree e 2-8

243

Receiver Done Register = R/W.....oooovviiiiiiiniiiiirie

244

Transmitter Ready Register = R/W .......ccccoovviiiiiiiiiiieieer
e, 2-8

24.5

TOID LO and TO ID HI Registers = R/W........ccccovvviriviiirnnieeeenee
e 2-11

s 2-8

2.4.6

FM ID LO and FM ID HI Registers = R /O .........cccovvvevrvvvvreecrrreirenenn, we.2-11

2.4.7

ID Control Status Register, ID C/S.......c.ccoccevviiiviinviiiniiniee
e, 2-11

248

Machine Control Register, MCR...........cccooviivviiiiieiriirrecccciriec
i 2-12

249

Miscellaneous Control and Status Register, MCS ..............c.......... e 2-14

24.10

2.5

V BUS REZISLET ......couiviiriiiiiiiiiiiiniieeccrec s 2-16
DIALOGUE: LSI-11 PROGRAM 1/O0 - VAX-11/780 MACROCODE............ 2-16

2.5.1

LSI-11 Sends a Character to the VAX-11/780........ccccceevvvvvnvveenvveenneeennnens 2-16

25.2

VAX-11/780 Sends a Character to the LSI-11..........cccccoovvvvevvvriinieennen
e, 2-18

iii

CONTENTS

Page

2.6

DIALOGUE: LSI-11 CONSOLE 1/O0 MODE - VAX-11/780

2.7

1% 8(61170
160 ) D ) 3o
U
PO 2-18
DIRECT ID BUS REFERENCE ...ttt
cvnr s 2-21

2.7.1

ID Bus Reference with the Clock Running..........cccccceeevvvvinivieiinicciiieeeennns 2-21

2.7.2

ID Bus Reference with the Clock Stopped...........ccccvvevrennnene. e [RUPT 2-21

2.7.3

ID Bus Reference without use of Console Command
Language INStIUCLIONS ......cccuvuririrnirireiriiiiireiiiiieesensinneeessrsreeeeseineeecsssseesans 2-22

CHAPTER 3

CIB DETAILED LOGIC DESCRIPTION

3.1

CONSOLE INTERFACE BOARD LOGIC..........cccovviiiiiieeeicctiree
e 341

3.2
33

Q BUS ADDRESS DECODER AND TIMING LOGIC.........cccccceceevvrerenrrerennnnnns 3-1

3.3.1
3.3.2
333
3.34
33.5
336
3.3.7

ID BUSINTERFACE LOGIC........cooooreiiecrtenireec
e seccnree e ceineeeecnneessans 3-1

Interface Address Decoder LOIC.........ccovvveervuveeriieriniiieeiiierenineeccieeesneeeans 3-1
QMUX LOBIC....cciiciuriiieriireerieniiieresieiiereeisiseeeeesissseesesesssesssssssasssssssssasssnnes 34

One of Twelve Decoder LOGIC........ccccuveeeerieeiinereenirireniiereneeeseneeesnnecsneeens 34
Strobe Signals Developed on a Q Bus Read Transfer.............cccccvveeerenvennnnee. 3-7
Clocking the Registers on a Q Bus Write Transfer............ccccccevunvvveiinnenninnen, 3-7
Transfer Synchronization LOGIC............cccccvviivriieeiniiiinneeccniiireeecenieecneiee s 3-7
Q Bus Transfers when the VAX-11/780 CPU is Stopped........c.ccceeeeuvveennnenn. 3-13

ROM LOGIC ......coeiiiiiitiiiccntrteeeccreteesseerse
s ssenrsesessnneessessssaessessasssessessssesenss 3-13

CIB REGISTER LOGIC .........coocrtreeiiiiicccinreece
s scecntnneeeesssenesnnsensessssnannens 3-13

3.5.1

TO ID RegiSter LOGIC .....cuvviiiiiiiiiinniiiiireeeiiecirrieeeeeeessssnrneeeeeeseesssnsssseeesenans 3-13

3.5.2

FM ID RegiSter LOZIC ....ccccunniiiirieiiiiiiiiiiirietecniccerineeesessesnnnsneesessensnseesens 3-17

3.53

ID C/S ReGIiStEr LOZIC.....uuuveeiiriiirieieiiiireeiiiiiereeereiireeesesnenesssesseseessnsseesnns 3-17

354

MOR REZISLET .....cceiiirreeiiiiciineeeenccriteeesestneeeesereeeeesssasenessesssraessessssnsesennes 3-20

3.5.5

MCS Register LOIC .......cccovvvvummrrreeeeiieinnnneineeenennsSOOI 3-20

356

V Bus Register LOZIC ........ccciiiiiriiiiiiiiniiiicciineeecitieeceree
e ceneeeeetreeeenneeessenens 3-20

3.5.7

ID Data Register LOGIC.......cccccvuvrrinuriinniuniiniienicnneeeninessniineeenisnessennesenseens 3-24

358

INtEITUPL LOGIC ... .uuviiiiiiiniiiiiiciiiieieininreeercsirneeesesssreeesesesseeeesessnseesssseesenns 3-25

3.6

TYPICAL CIB TRANSFER OPERATIONS .........ccovtrieicreeecccnrreeccieeeeens 3-29

APPENDIX A

Q BUS TECHNICAL DESCRIPTION

A.l

GENERAL.........ooviiiitiiininiiciinciitiesssssieecssssrressssssraneesesssssneesssssssssssssnsanesen A-1

TRANSFER OPERATIONSONTHEQBUS ........coooiiiiiteecccreee
e, A-3

A2.1

INPUL OPErations........cccceviirriniiiiiiciinnieeerininrersenrreeeessssseesessssssesesenssssesessnnes A-4

A22

OULPUL OPETALIONS .....ovvrieiiiiiiinnieiiiriiireeereiineeeessssrnreeesssisseesessssesesessssasssns A-5

A23

INtEITUPLS .ot

A24

Bus Initialization .........ccccccoveiiiiiiiiiiieeeienniieeccccereeeccsrnree
e
e et e sane A-8

ce e rrrrreee e se s s s aste e e e e e e ses e sbaraaaseeseensrnnas A-5

A2S5

Power-Up/Power-Down Sequence...............cccvervennen. Feveeseereeneeresreerenrans A-8

A.2.6

Memory Refresh Operation..........ccccvveiiieviieeeriecinieeinnciineeeccieee
e eecnnesesenees A-8

2-8

2-9
2-10
3-1
3-2

3-3

3-5
3-6

3-8
3-9
3-i0

3-11
3-12

3-13
3-14

3-15
3-16
3-17

3-18
3-19

3-20
3-21

3-22
3-23
3-24

3-25

3-26
3-27

WD DD em
B
wm

VN WO N
2-7

-y

FIGURES

Titie

Page

Console Subsystem Configuration...............c.coevveeueeeeeeeeeeee oo, 1-3
VAX-11/780 Control Panel...........cccovvvueieuiieiniie
e iiiieiieteee
eeee e
e 1-6

ID Bus Control Logic, BLOCk DIiagram .............ccceeeuevvvvveeieeeeeeeireerseesoeseeseeoeos 1-9
V Bus Block Diagram..........cceceeeevienieiiiniinieniec
e seeeseeseneesseese
e s, ... 1-9

CIB, BIOCK DIagram.........cccoouiiiiviiiii
e s eeseeeeressees
irciiecc
e es e rese
eeees 2-2

CIB Data Paths, Simplified Biock Diagram...........c.ooveeveveeeeeoeeoeeooes oo 2-3
VAX-11/780 and LSI-11 Interaction and Operating Mode Combinations ............ 2-4
ID Bus Registers 0n the CIB............couviiiiiriieie
e oo eeeees oo
eeeeeteee 2-7

Use of the TO ID and FM ID Registers When the VAX-11/780 CPU
1S RUNMING. ...tett
e e e e s2-7

Lower Eight Q Bus Registers: Addresses and Bit Configurations.......................... 2-9

Upper Eight Q Bus Registers: Addresses and Bit Configurations......................... 2-10
LSI-11 Sends a Character to the VAX-11/780 CPU, Flowchart ..............c.......... 2-17

VAX-11/780 Sends a Character to the LSI-11, FIowchart ........ooovvvoooeeeeoieeoin, 2-19

LSI-11 Responsetoa VAX-11/780 CPU Halt ..........coovoovrveeveeseeeiereeeereerennns 2-20
ID Bus Address Decoder LOZIC ...........coovive
e eeeeeeeeeeee
iieeeeeee
oo,
eee 3-2

ID Data MultipleXer LOZIC........ccuveuviiiieii
e eee e,
iiieeeeeeee 3-3

Q Bus Address Decoder Logic Interface Chips............cccveveveeeeeeeeeseseeeseeseeninns 34
QMUX LOGIC. c..cuveiiiii
etttiiiiic
e eeee e et eessee e esssesssesssesssesess
eistii
sseseseeeeeees
itic
oo 3-5

One of TWelve Decoder LOGIC.........coouiiviiieiiireieeeee
oo
eeeeeeeeeee
e eeees e 3-6

Register Strobe LOZIC........ccviviiuiiiiiitiiieteeeeee e, 3-8
Transfer SyNnchronizer LOGIC ...........c.cviviiv
e eeee
eeieieeeee
oo e
eeeeee 3-9

DATO/B Transfer Timing on the Q BUS.............ocveeveeivuevereeeeeeeeeeeereeseeeeenns 3-10
Synchronized DATO Transfer Timing Diagram ............ocoeeeevvvevroerorereoeoin, 3-11

DATI Transfer Timing onthe Q BUS ..........coceeueeveeeeeeeeeeeeeeeeeeeee oo, 3-12
Synchronized DATI Transfer Timing Diagram................. e 3-12

ROM LOGIC.....ciii
sttt
iiniiii
eteeeeestessesesesse
nteniin
eeseeseessessssesess
tieei
sseeesesss s 3-14

ROM Address Selection LOGIC.........c..ccvevivrirreeeieeeeeteeeeoo
eeeseseerees
e enessseens 3-15
TO ID ReEZIStEr LOZIC.......coiiuirtiirienr
e iniiiiiis
eeeeteeeeessesseesserseeestessesse
tecteseeenes 3-16

Development of CIBU CLK FMIDH ..o 3-18

FM ID ReiSter LOGIC......c.cciviuiiuiiuiiiiniieieteceieeeeeeeeeesesseessesetsseesosesossesessseseas 3-18
ID C/S REIStEr LOGIC. .....c.coveviiiriiririiiitiictiieeee
e ee e eteeeeeeeeee
s e es e es s s, 3-19

Machine Control Register LOIC..........ccuevviuieeeuieeree
e oo e,
eeeeseee 3-21
MOCS ReEZISLET LOZIC .....vevueeuririeiiiitiiiiitiistceeeeeeeeeseseeeeesesseessesoees
e s sssese
e 3-22

V BUS ReGIStEr LOIC .....ccvev
ettt
iiiiiiriii
oo
iiir
t 3-23
V Bus Clock Timing Diagram............ccccoeevveeeieeirinreereseeeeeereessesesserseessssssesns 3-24

ID DATA HI and ID DATA LO Register Loglc ................................................ 3-25
VAX-11/780 CPU INterrupt LOGIC......cvevivirireirieeeeeeereeeeeeeeeeeeeesseseeeesons 3-26
Ready and Done MultipleXer LOGIC............coerveeeereereeesesreeeereseeeeeseeessoessesnos 3-27
LSI-TT INterrupt LOZIC ..ccuveveeriecriei
e eeeeseeeeteseneese
iinieeiee
e e
iece
s. 3-28

LSI-11 Sets TX READY, DATOB Transfer on Q BUS ..........ccoovvvvveveevieeieeriinns 3-30
VAX-11/780 Software Sends a Character to the FM ID Register for

Transmission to the Console Terminal, Write Transfer on the ID Bus................. 3-31

FIGURES (CONT)

Figure No.
3-28

3-29
3-30
3-31

A-1

A-2
A-3

A-4

Page

Title

i, 3-32
Interrupt Dialogue on the Q Bus........cccooiiiiiiiniiiniiic
LSI-11 Interrupt Subroutine Reads the FM IDLO Register, DATI

iic 3-33
e
einiiriii
e
Transfer on Q BUS .....coeiviviiiiii
Transmission
for
Register
IDLO
TO
the
to
LSI-11 Writes a Character
to the VAX-11/780 Software, DATO Transfer on the Q Bus.........cc.oceevineneee 3-34
VAX-11/780 Interrupt Subroutine Reads the TO ID Register, Read
Transfer on the ID BUS .......cuuueviviririiriieiiiiiiniieiniiiiiiieseeeseeeesessesssnsonens 3-35
nniiiiee A-4
cinirecssrate st esssssiesesssassessns
itieriiiiiii
DATIBUS CYCIE......ueiiiiire
enineesssneeens A-6
iriniiieiniiiiecniinee
......cccovvuiiiiiniie
Cycle
DATIO or DATIOB Bus
sns A-7
niennesseeinessssnneess
DATO or DATOB BUs CyCle.......ooceieiiiieiiiiiiiiniiiieiniinnece
Interrupt Request/Acknowledge Sequence............coovveniiniienneiniinicnnciiinen, A-9

TABLES

101

> uuut.omw.—._.._.
W N = W N == LI N) =

Table No.

Title

Page

eemeiei 1-1
s
Related Hardware Manuals...........cccceeeiieiiiiiniiiiininiiiiiinienimieiiin
CONSOIE FUNCLIONS ....uvvereriiiriiriniiiiirieeeeeeieeeeennssiiiiiessesssssisssisssssmeresssessassassssssssssans 1-4
ID Bus Register Address ASSigNMENt .........ccovvuiiiiiiiniinniienniinnie 1-8
e 2-13
Clock Frequency Control ........c.cccoviiniiiniiiniiiininiennieninncseeess
UseS Of PROCEED .......uuuiviiiiiiiieeiiiieeeiesinsesssssisaesessssnesssssisssssssssssesassssasesssss 2-14
Panel Switch Sense Bit FUNCLIONS......cccccovvurmmemmerinrieiiieiiiiieiieinnnnsesen 2-15
e brenreaens 3-17
e et
Generation of the CLK FM ID H Signal ............cccceuueen.e
i 3-24
iiiiiiinnnnni
....ccooooevi
Generation of the SDMS Clock HSignal......
nn,
Interrupt Related Register Bit Functions..........cccooveeiinniiniennenniniinin 3-29
Q BUS SIZNAIS .....ooiiiicriiereiiie et A-1

CHAPTER 1
INTRODUCTION

1.1 SCOPE
This manual provides an overview of the VAX-11/780 Console Subsystem and a comprehensive description of the Console Interface Board on the functional and logical levels. A description of the Q
bus is provided as an appendix. The manual will serve as a resource for appropriate branch and
support level courses of the Field Service and Manufacturing training programs and as a field reference. Table 1-1 lists related hardware manuals.

Table 1-1

Related Hardware Manuals

Title

Document

Notes

Microcomputer Handbook

EB 06583

Available on hard copy.*

LSI-11,
Manual

EK-LSI11-TM-003

Available on hard copy. Hard copy
ships with device.*

EK-LA3635-OP-003

In Microfiche Library. **Available on
hard copy. Hard copy ships with device.

KA780 Central Processor
Technical Description

EK-KA780-TD-PRE

In Microfiche Library.**

PDP-11/03

LA36/LA35
TT_

USCI S

RA_

User’s

DECwriter

Ividnudl

*The documents can be ordered from:
Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01532
Attention: Communication Services NR2/M15
Customer Services Section
**For information concerning Microfiche Libraries, contact:
Digital Equipment Corporation
Micropublishing Group, PK3-2/T12
129 Parker Street
Maynard, MA 01754

1-1

1.2

CONSOLE SUBSYSTEM OVERVIEW

Five major components make up the VAX-11/780 Console Subsystem: an LSI-11 microprocessor
(KD11-F), which includes a 4K by 16 semiconductor RAM; a single floppy disk and a controller
(RXV11); a terminal and one or two serial line unit interfaces (DLV11-E), one for communication
with a remote terminal (optional); a VAX-11/780 CPU console interface (CIB), which includes 4K by
16 bits of ROM for the LSI-11; and a control panel on the VAX-11/780 cabinet. The Console Subsystem provides three major functions:

Traditional lights and switches functions such as EXAMINE, DEPOSIT, HALT, START,

Diagnostic and maintenance functions, including the capability to load diagnostic microcode into writable control store (WCS), control execution and monitor results, control
single step clock functions, and examine key system points via a serial diagnostic bus (V
bus).

Materialize the terminals and floppy disk I/O registers in the processor register space. These
console I1/O registers are located on the CIB module; they are addressable both from the
LSI-11, via the Q bus, and from the VAX-11/780 CPU, via the ID bus. This port is therefore
used for terminal and floppy disk transfers to the VAX-11/780 CPU and all other software
defined communications between the console and the VAX-11/780 CPU.

and Single Instruction.

The user can perform the lights and switches and diagnostic and maintenance functions through a set
of keyboard commands and responses at the terminal. The LSI-11 in turn interprets the commands
and controls and monitors the VAX-11/780 CPU through a set of control /status and data registers on
the CIB module in the Q bus I/O space. These registers connect to the ID bus, the V bus, and points
fv_vithin the VAX-11/780 CPU and on the control panel. Figure 1-1 shows the console subsystem coniguration.

1.3

CONSOLE MODES

The LSI-11 normally operates in one of two modes, each of which is implemented through a set of
MACRO-11 routines. When the LSI-11 is in the program I/O mode it functions as a character handler, passing characters between the console terminal and the VAX-11/780 CPU. The console terminal
therefore functions as the VAX-11/780 VMS operator’s terminal.

When the LSI-11 is in the console I/O mode, it interprets all console terminal output in order to

perform the lights and switches and maintenance functions and implement the console command
language (CCL) capability.

Table 1-2 lists the console functions implemented through the console command language.

1-2

ID BUS

MICROSEQUENCER

CLOCK CONTROL

‘—l

—

V BUS

CONSOLE/CPU
INTERFACE

CONTROL

P
|

PANEL

ROM

t Q-BUS
LSI-11

4K MEM

RXV11

FLOPPY

CONTROLLER

DLV-11

(OPT)

EIA CONNECTION

RX01

TERMINAL

FOR REMOTE

TERMINAL

TK-0192

Figure 1-1

Console Subsystem Configuration

1-3

Table 1-2

Console Functions

Virtual examine byte, word, longword
Virtual deposit byte, word, longword
Examine general register

Deposit general register
Examine processor register

Deposit processor register

Continue
Initialize TB, cache, etc. (result of CPU initialize signal)
Quad clear

SBI unjam
Stop clock

Start clock

Step one time state
Step one SBI cycle (stops in CPT 0)
Select one of four clock frequencies

Assert VAX-11/780 CPU initialization signal
Interrupt VAX-11/780 CPU (terminal registers)
Halt at end of current instruction
Step single instructions

Stop clock upon microbreak match (in CPTO of match state)
Force UPC<12> to WCS on microtrap

Force NOP on selected ROM fields
Clock V bus

Assert V bus loopback bit
Load V bus shift registers

Read V bus serial channels
Sense positions of auto-restart, boot, lock, and remote switches

Time-out from VAX-11/780 interrupt strobe signal, used to assert RUN light
Provide a write-only register on the ID bus (FM ID) (as a responder)
Provide a read-only register on the ID bus (TO ID) (as a responder)
Write to any ID bus address (requires console control and clock running)
Read any ID bus address (when clock is stopped or running)

Synchronize use of FM ID and TO ID via ready and done bits
Read clock states

Sense assertion of console acknowledge (reply to halt request)
Sense when system clock is stopped
Maintenance return (forced jump to UPC off top of microstack)
Turn floppy disk power on or off

Read ID bus address and direction lines (clock stopped only)

Materialize JMP into ROM at 163000 and 163002 or 173000 and 173002 (LSI-111/0 address space)

Table 1-2

Console Functions (Cont)

The capability to read/write at any ID bus address permits register accesses to implement the following functions (and others):
Push microstack
Pop microstack

Write microbreak
Read microbreak
Read WCS address
Write WCS address
Write WCS data

Read WCS status

Specify defaults
numeric radix
addressing modes
data length

Display console and CPU status

Control the number of fill characters to be added after special characters sent to the console terminal.
Command repetition

Execute commands from an indirect command file (an ASCII file containing console commands)
Invoke microdiagnostics

Implement
the remote console access command set.

VAX-11/780 CPU STATUS

The VAX-11/780 CPU may be either halted or running. When it is halted, it enters the console command mode, executing a microcode loop which enables the console to perform the lights and switches
and maintenance functions. When the VAX-11/780 CPU is running, it is running at the ISP level,
executing macroinstructions.
1.5

PANEL FUNCTIONS

With the exception of the OFF position of the key switch and the POWER light, the lights and
switches on the control panel are connected to other parts of the computer through the miscellaneous
control status (MCS) register, a Q bus register on the Console Interface Board. The OFF switch
controls a relay in the power supply. The POWER light is connected between +5 volts and ground.
ATTN indicates that the VAX-11/780 CPU is not running and/or needs operator intervention. RUN
indicates that the VAX-11/780 CPU is strobing interrupts, and thus not caught in a microcode loop.
The REMOTE light reflects the position of the 5 position key switch, indicating which of the two
console terminals is on line. Figure 1-2 shows the control panel.

1-5

2 POSITION

SWITCH

LOCAL

oFF

RED

GREEN

RED

e
ATTN

RUN

POWER

LOCAL

REMOTE

DISABLE

OFF

REMOTE

ON
BOOT

AUTO
RESTART

5 POSITION

KEY SWITCH

MOMENTARY

CONTACT
ROCKER

SWITCH

Figure 1-2

VAX-11/780 Control Panel

1-6

TK-0193

AUTO RESTART is a two position switch which controls bit 2 in the MCS register. BOOT is a
momentary contact rocker switch, which when pressed sets MCS bit 11; LOCAL DISABLE, LOCAL,
REMOTE DISABLE, and REMOTE control MCS bits 1 and 0. These MCS register bits in turn

control and initiate specific LSI-11 operations, as follows:

1.6

AUTO RESTART - when on, causes the LSI-11 processor to jump to a designated ROM
location on power up.

BOOT - causes the LSI-11 to boot VMS, the operating system. When the boot routine is
completed, the console comes up in the program 1/O mode.

LOCAL - when the 5 position key switch is in LOCAL, it enables the LSI-11 to designate
the local terminal as the console terminal or as the VAX-11/780 VMS operator’s terminal
(enabling either the console 1/O or the program I/O mode, according to the wishes of the
terminal operator).

LOCAL DISABLE - this position of the switch causes the LSI-11 to select the local terminal
as the VAX-11/780 VMS operator’s terminal, while inhibiting console operation in the
console I/O mode.

REMOTE - this switch position causes the LSI-11 to select the remote terminal, allowing
operation in both the console I/O and the program 1/O modes.

REMOTE DISABLE - when the key switch isin REMOTE DISABLE, it causes the LSI-11
to designate the remote terminal as the VAX-11/780 VMS operator’s terminal, while disabling use of the terminal in the console I/O mode.

ID (INTERNAL DATA) BUS OVERVIEW

The ID bus is a high speed data path between the major functional areas of the VAX-11/780 CPU and
provides the following functions:
1.

Transfers data to and from the internal registers of the VAX-11/780 CPU and the Translation Buffer.

2.
-

Transfers data in the form of displacement and short literals from the Instruction Buffer to
the VAX-11/780 CPU’s data paths and FPA.

Transfers data between the VAX-11/780 CPU’s data paths and the FPA.

Transfers data from the internal registers to the CIB under console control during the
maintenance operation.

1.6.1 ID Bus Structure and Operation
The ID bus consists of 32 data lines, 6 address lines, and 1 write control line. The address lines specify
which internal register has been designated as the source or destination. Address assignments are listed
in Table 1-3.

The write control line specifies directional control, indicating whether an internal register is to be read
onto the bus or data is to be clocked from the bus into an internal register.
During a normal read operation, data is transferred from the addressed internal register to the Q
register of the data paths via the ID bus. During a normal write operation, data is transferred from the
D register of the data paths to the addressed internal register via the ID bus.

Table 1-3

ID Bus Register Address Assignment

IBUF DATA

CNSL RXCS

01
02
03

TIME OF DAY
-RSVD SYSTEM ID

CNSL RXDB (TO ID)

04
06
07
08

0A
OB
0C
0D
OE
OF
10
11
12
13
14
15
16
17
8
19
1A
1B
IC
ID
IE
IF

21
22
23
25

CNSL TXCS

CNSL TXDB (FROM ID)
DQ (ID MAINT ONLY)

NEXT INTERVAL REGISTER
CLOCK CS
INTERVAL COUNTER
CES
VECT
SIR
PSL
TBUF DATA
-RSVDTBUF REG 0
TBUF REG 1
ACC REG 0
ACCREG 1
ACC MAINT REGISTER
ACC CONTROL/STATUS
SBI SILO
SBI ERR REGISTER
SBI TIMEOUT ADDRESS
SBI FAULT/STATUS
SBI SILO COMPARATOR
MAINTENANCE
CACHE PARITY
-RSVD-

USTACK

UBREAK
WCS ADDRESS
WCS DATA/STATUS

POBR
PI1BR

SBR

ESP

27
28

2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F

RSVD FOR SYS SPACE
KSP
|
,

SSP
USP
ISP
FPDA
D.SV
Q.SV
TO
Tl
T2
T3
T4
TS
T6
T7
T8
T9
PCBB
SCBB
POLR
PILR
SLR
RSVD FOR SYS SPACE

The ID bus may be controlled from the console interface logic in a maintenance mode operation as
shown in Figure 1-3. This allows access to writable control store, the microstack (USTACK) and
internal registers from the console. In maintenance mode operation only, the D and Q registers of the
data paths may be addressed as internal registers over the ID bus. Note that the left and right sides of
the address and direction lines are functionally identified, since they are separated only by buffer driver
gates in the VAX-11/780 CPU.
When the Console Interface Board generates the ID MAINT signal, it initiates a maintenance operation, allowing the console to assert ID bus address and write signals (and data, if appropriate).
1.7 V BUS OVERVIEW
The V bus consists of eight serial data lines, a load signal line, a clock signal line, and a self test line.
Each of the participating VAX-11/780 CPU modules contains at least one V bus shift register chip.
The data input lines to the shift register monitor specific test points on the CPU module, as shown in
Figure 1-4. The LOAD signal causes the shift register to parallel load from the test points when the
VAX-11/780 CPU is in a stable condition. The clock signal can then be used to read the latched data
serially from each of the shift registers into a register on the CIB. The LSI-11 must read the register
before clocking in the next serial bit from each of the shift registers. See Sections 2 and 3 for more

detail.

’

1-8

VAX-11 CPU

(L=1)
FROM CIB

}

flh

XMT ADRS <56:0> L

ADDRESS <5:0>GENERATED

H=1

(R0

BY MICROCODE

FROM MICROCODE

(H=1)

OR DATA PATH

ID RIGHT ADDR <5:0> H

ID LEFT ADDR <5:0> H

ID MAINT (1) L4>_
TK-0200

Figure 1-3

ID Bus Control Logic, Block Diagram

TYPICAL VAX-11 CPU MODULE
MODULE TEST

POINTS
—

SELF TEST

;

SELF -

PARALLEL SHIFT REGISTER
LOAD

]

CLOCK
GEEEEED

aruad

armiEd

TEST

GEIERD

EnEEls

CGEETED

GEEED

GEEEND

GEEEED

GEANEED

GEENED

CAEEND

ChEED

ONE OF EIGHT

SERIAL DATA LINES
CIB MODULE V BUS REGISTER

SELF

TEST

LOAD | CLOCK

TK-0194

Figure 1-4

'V Bus Block Diagram

1-9

1.8

Q BUS OVERVIEW

The Q bus (LSI-11 bus) connects the LSI-11 processor (and its ROM and RAM memories), the console terminal interfaces, and the floppy disk interface to the Console Interface Board, and thus to the
VAX-11/780 CPU. The 16 address signals and 16 data signals share the same bus lines. Fourteen other
LSI-11 signal lines are used in the VAX-11/780 configuration for control signals (note that the DMA
control lines are not used).

A master-slave relationship defines communication between the processor and the other devices on the
bus. Each control signal issued by a master device must be acknowledged by a slave device in order to
or write
complete a transfer. The LSI-11 processor must therefore become bus master in order to read
in
structure
addressing
an
permits
bus
Q
The
bus.
Q
the
on
location
memory
or
register
any interface
locamemory
as
addressed
directly
are
devices
peripheral
for
registers
data
and
status,
which control,
tions. Therefore, all operations on these registers are performed by normal memory reference instructions. No system clock is used on the Q bus, and all communications on it are asynchronous. However,
when one of the interface units such as the serial line interface for the console terminal must transfer
data (i.e., a character) to or from the LSI-11 processor, it must interrupt the processor and thereby
'
invoke a service routine which will handle the actual data transfer.

Note that the serial line interfaces and the floppy disk interface cannot communicate directly with the
Console Interface Board, nor can the CIB communicate directly with them. All transfers initiated from
the interfaces begin with interrupts to the LSI-11 processor.

1-10

CHAPTER 2
CIB FUNCTIONAL DESCRIPTION

2.1 CIB OVERVIEW
The Console Interface Board connects the console subsystem to the VAX-11/780 central processor.
The CIB contains interfaces for the Q bus (LSI-11 bus), the ID bus, and the V bus; registers accessible
to each bus; and all the hardware necessary to implement the various console functions. In addition,
the CIB contains a 4K by 16 bit ROM which provides the bulk of the console LSI-11 software, and
internal buses and multiplexers. The buses and multiplexers connect the various registers and bus
interfaces. Figure 2-1 shows the CIB in block diagram form.
The LSI-11 software has access (read and/or write access) to the ROM matrix and all of the registers
shown (except SYSID). The Q bus address decoder logic on the CIB identifies the register addressed.
When the LSI-11 writes to a CIB register, the data is routed via the Q bus transceivers directly to the
register specified. On a read, the contents of the register addressed are asserted on the Q bus by the
same transceivers.

NhWUN
e~

The VAX-11/780 software has access to the five following registers:
SYSID register
Receiver Control/Status register (RXIE, RX DNE)
TO ID register
Transmitter Control/Status register (TXIE, TX RDY)
FM ID register.

On a read transfer, the contents of the register addressed are gated via the ID MUX logic to the ID bus
transceivers. When the VAX-11/780 software writes to the FM ID register, or one of the ID control/status registers, the data is gated from the ID bus transceivers directly to the register addressed.

2.2 CONSOLE/VAX-11 INTERACTION VIA THE CIB
All data transfer operations between the VAX-11/780 CPU and the console LSI-11 are routed via the
TO and FM ID registers on the CIB, as shown in Figure 2-2, with two exceptions. First, the LSI-11
may look at various points in the VAX-11/780 CPU via the V bus. Second, it may look at the data on
the ID bus via the ID DATA HI and LO registers when the VAX-11/780 CPU clock is stopped.
However, the interaction of the console subsystem and the VAX-11/780 CPU is directly related to the
states of the two processors. The VAX-11/780 CPU may be running or halted, and the LSI-11 may be
in the program I/ mode or the console 1/0O mode.

2-1

* CNSL RESET

< ROM NOP, UPC12
» CLK CNTRLS

—»
V BUS CNTRL

>\ BUS CLK

SCP SWITCHES +——

ID ADDRS

ICLC INTR

AND CNTRL

" ACK

—u‘ogglwv BUS DEL CLK

V BUS SER DATA +—

————<—=PF SIGNALS

+5V

V,JA

/1D MUX

/DMUX
\

?gs

VAX11

INPUTS

CNTRL

XCVRS

{}

QBUS

D/;TA
D

ROM

MUX:L

_’[

ADDRS REG

INTR

LOGIC

4
ID BUS
XCVRS

|
a

Q MUX

—_

DATA

MCR

MUX

LOGIC

wnl

GDJ

Q BUS

INTR

| o

—

CNTRL

ONE

EHOT
ID C/S

TO ID

TO 1D

{}

| .

]

Tie|l

|roy|

|onNE

FWD

F",’_'(')D

MCS

MCR

V-BUS

I
|

|riEl

Q BUS

::I\rjvTT’:aL

TERM-

INATOR

]

Q BUS

PROTOCOL

LOGIC

CLOCKS, ENABLES
‘

TIMING

Q BUS

ADDRS
DECODE

TERM-

INATOR
nnnnnnn

Figure 2-1

CIB, Block Diagram

2-2

VAX-11/780

CPU ‘
1

/ ID MUX \

amMux \

S
~BUS
D@ [qrraNs21

V BUS

|CEIVERS
SYSID

TO:

QBUS
o
o
P t— TRANS. [O-{2

CEIVERS

r=
ID :DATA

FN;HD
LO

N
TK-0196

Figure 2-2

CIB Data Paths, Simplified Block Diagram

2.2.1
VAX-11/780 CPU Status: Halted and Running
When the VAX-11/780 CPU is halted, it enters the console comman

d mode. The VAX-11/780 micron (ATTN) indicator on the panel lights up.

processor jumps to the console wait loop and the attentio

When the VAX-11/780 CPU is in this mode, the console subsyst
em may control the ID bus by asserting the ID MAINT signal. The LSI-11 software then provides
the source of the ID bus address lines
and the ID bus write control line. Note that the VAX-11 /780 system
clock may or may not be running
when the VAX-11/780 CPU is in this mode.
When the VAX-11/780 CPU is not halted, it is running

at the instruction set processor (ISP) level,
agnostic or maintenance routines. The console software does not pass any commands to the ISP level software
. When the LSI-11 is in the console
I/O mode, it will not accept any output from ISP level software
running in the VAX-11/780 CPU.
Therefore, the VAX-11/780 software cannot communicate with
the console floppy disk or the console
terminal when the LSI-11 is in the console I/O mode. Figure
2-3 shows the various types of interaction
executing macroinstructions, unless it is executing microdi

of the two processors.

2.2.2 LSI-11 Operating Modes
The LSI-11 normally operates in either the program 1/O mode or the console
I /O mode. When the
LSI-11 is in the program I/O mode, the VAX-11 /780 CPU is always executing
macroinstructions, and
the LSI-11 passes the console terminal input, character by character, to the
VAX-11/780 software. All
data sent from the VAX-11/780 software to the terminal is passed by the
LSI-11 software directly to
the terminal.
When the LSI-11 operates in the console I/O mode, the LSI-11 software
interprets all input from the
console terminal, invoking specific console functions as appropriate.

VAX-11/780

CPU

ciB

ISP LEVEL

ASC11 CHARACTERS

LSI-11

PASSING

PROGRAM

SOFTWARE

1/0

MODE

(MACRO)

“HALT”
l

“CONTINUE"

“SET

“CTRLP"
l

TERMINAL
MODE"

HALT STATE

(CONSOLE
COMMAND MODE,
CONSOLE WAIT

LOOP)

CONSOLE
1/0
CONSOLE COMMAND

LANGUAGE

MODE

(egq. EXAMINE)

TK-0197

Figure 2-3

VAX-11/780 and LSI-11 Interaction and
Operating Mode Combinations

When the VAX-11/780 CPU is executing macrocode, the console may be in either the program I/0
mode or the console 1/O mode. In the program I/O mode, the terminal operator can execute programs, and in other ways interact with the ISP level software. However, when the console is in the
console 1/O mode and the VAX-11/780 CPU is executing ISP level software, the range of functions
which may be performed by the console is limited to those that require no direct response by the VAX11/780 CPU (except HALT). These commands include the following:
SHOW
SET
HALT
WAIT DONE
HELP
EXAMINE/VBUS
CLEAR

Other console commands, such as EXAMINE, cannot be implemented until the VAX-11/780 CPU is
halted (note that typing in HALT will do this).

When the VAX-11/780 CPU is executing macrocode, the operator at the console terminal can shift
from the console 1/O mode to the program I/O mode by typing “SET TERMINAL PROGRAM.”
He can shift from program I/O mode to console I/O mode by typing control-P (AP).

2.2.3

Use of CIB Registers

When VAX-11/780 ISP level software is running and the console

is in the program I/O mode, commuCPU is accomplished by means of interrupt transfers. Data is passed via the lower halves of the TO
ID and FM ID registers; the status of the
interrupt processes is controlled and monitored via the interrupt
enable and disable and ready and
done bits in the various control and status registers on the CIB.

nication between the console subsystem and the VAX-11 /780

In this respect the Console Interface Board functions like a conventi
onal communications controller
(e.g., a DLI11), except that interrupts are generated on both sides of
the interface and data is passed in
parallel.

However, the console can make more extensive use of the facilities
provided by the Console Interface
Board when the VAX-11/780 CPU is in the console comman
d mode and the LSI-11 is in the console
I/O mode. Then the control signals developed on the ID control /status
register (ID C/S), the machine
control register (MCR), the miscellaneous control and status register
(MCS) and the V bus register are
all accessible to the LSI-11 as it interacts with the VAX-11 /780 CPU.,
2.3 ID BUS REGISTERS ON THE CIB
Of the five ID bus registers on the Console Interface Board,
all but the SYS.ID register are dual
ported, allowing VAX-11/780 CPU access via the ID bus and
LSI-11 access via the Q bus. This section
describes these registers as they appear on the VAX-11/780
CPU side of the interface. Figure 2-4
shows the addresses and bit configurations of the five registers.
:

2.3.1 System Identification Register (SYS.ID, ID03)
This register makes the system identification available in the processo
out to pins for back panel switches. Pull-up resistors

r register space. The 32 bits come
are provided on the CIB.

2.3.2 Receiver Control/Status Register (RXCS, ID04)
The VAX-11/780 software and LSI-11 software use this register to
synchronize data transfers from the
console subsystem to the VAX-11/780 CPU through the TO ID
register. RXCS contains two bits.
RXCS<7> Receiver Done (RX DNE) - R/0O
The LSI-11 sets this bit to indicate to the VAX-11/780 microcode that
valid data is available in the TO
ID register. This is a read only bit from the ID bus side; the CIB hardwar
e clears the bit automatically
when the VAX-11/780 microcode reads the TO ID register. System
initialization also clears the bit.
RXCS<6> Receiver Interrupt Enable (RXIE) - R/W
When set, this read /write bit enables an interrupt at IPL 14,4 and vector
FC¢ to the VAX-11/780 CPU
each time the RX DNE bit makes a transition from 0 to 1. Each transitio
n generates one interrupt. If
RX DNE is already set and RXIE goes from 0 to 1, the interrupt
will also occur. System initialization
clears this bit.

2.3.3 TO ID Register (TO ID, RXDB, ID05) - R/O
This data buffer register serves two functions. First, it may be loaded by the LSI-11
with data from the
console terminal, one ASCII character, to be read by the VAX-11/780 microcode
. The data is valid
only when the RX DNE bit is set, and when the microcode reads TO ID, the CIB
hardware automatically clears RX DNE. Second, the LSI-11 may write to any ID bus address through
the TO ID register
by executing an ID maintenance cycle return function when the VAX-11/7
80 CPU is halted (see
Paragraph 2.7 for further details). Note that the terms TO and FROM are used
with respect to the
VAX-11/780 CPU.

2.3.4 Transmit Control/Status Register (TXCS)
The VAX-11/780 CPU and the LSI-11 software use this register to synchronize data transfers from the
VAX-11/780 microcode to the console subsystem through the FM ID register. TXCS contains the
following two bits:

TXCS<7> Transmitter Ready (TX RDY) - R/O
The LSI-11 sets this read only bit to indicate to the VAX-11/780 microcode that it is ready to accept
another character in the FM ID register. The CIB hardware clears this bit automatically when the
microcode writes data into the FM ID register. System initialization clears the TX RDY bit.
TXCS<6> Transmit Interrupt Enable (TXIE) - R/W
When the VAX-11/780 microcode sets this read/write bit it enables an interrupt at IPL 1416 and
vector F8,4 each time TX RDY goes from 0 to 1. Only one interrupt occurs for each 0 to 1 transition.
If TX RDY is already set and the TXIE bit makes a 0 to 1 transition, the interrupt will also occur.
TXIE is cleared by system initialization.

2.3.5 From ID Register (FM ID, TXDB, ID07) - W/0
Like the TO ID register, this data buffer register serves two functions. First, it may be loaded by the
VAX-11/780 microcode with data to be passed to the console subsystem. It should be loadedin this
way only when the TX RDY bit is set. The CIB hardware automatically clears TX RDY when the
VAX-11/780 microcode writes to the FM ID register. Second, the LSI-11 may read any ID bus register
through the FM ID register by executing an ID maintenance cycle when the VAX-11/780 CPU is
halted.
2.3.6 Use of the TO ID and FM ID Registers
Under normal circumstances, when the VAX-11/780 CPU is running, executing ISP level software and
the LSI-11 is in the program 1/0 mode, only the low order portions of the TO ID and FM ID registers
are used, as shown in Figure 2-5.
The low order eight bits of the TO ID register (RXDB<7:0>) will contain data coded as an ASCII
character to be passed from the LSI-11 to the VAX-11/780 CPU. Bits <11:8> specify the console unit
at which the data originated. Logical unit 00 is reserved for the operator terminal.

The FM ID register is used in the same way when the VAX-11/780 CPU is running. Bits <7:0>
contain the ASCII character to be passed to the LSI-11. Bits <11:8> specify one of the logical units in
the console subsystem.

All references to the RXCS, TO ID, TXCS, and FM ID registers when the VAX-11/780 CPU is
running result from microcode interpretation of MFPR and MTPR instructions. However, the VAX11/780 microcode does not test the READY and DONE bits before referencing the TO ID and FM ID
registers when executing MFPR and MTPR instructions. To do so would affect interrupt latency
times. The macro level instructions should test the READY and DONE bits before the microcode
references the data buffer registers.
When the VAX-11/780 CPU is halted, the microcode and the LSI-11 software may use all 32 bits of
the TO ID and FM ID registers to transfer parameters and other information. The VAX-11/780
microcode has responsibility for testing the appropriate synchronizing bits before referencing the registers. Note that the READY or DONE bit must be set before the transfer can take place.
Note also that since the LSI-11 cannot read the TXIE and RXIE bits, it must disable interrupts to the
VAX-11/780 CPU while the TO ID and FM ID registers are being used for examine functions and the
like. The reader should also understand that the bits in the TXCS and the RXCS registers are totally
divorced from the corresponding bits in the DLV-11E. When the LSI-11 is in the program I/O mode,
it simply passes data to and from the CIB and to and from the DLVI11-E.

2-6

03,6 SYS.ID

SYS.ID <31:00>
31

08 07 06 05

04,., RXCS

oy
n

DNE RX
31

05,, TO

ID (RXDB)

0 ID<31:00>
31:

08 07 06 05

06, , TXCS

RDY TX
31

07 FM
ID

(TXDB)
FM

<31:00>

TK-0198

Figure 2-4

31
TO ID (RXDB)

12 11

ID Bus Registers on the CIB

08 07

RX SEL <3:0>

RX DATA

31
12

FMID (TXDB)

TX SEL <3:0>

TX DATA
TK-0199

Figure 2-5 Use of the TO ID and FM ID .Registers
When the VAX-11/780 CPU is Running

2-7

2.4

Q BUS REGISTERS ON THE CIB

The Console Interface Board contains sixteen 16 bit registers which are addressable from the LSI-11.
Six of these registers are dual ported, allowing VAX-11/780 CPU access as well as LSI-11 access. This
section describes the registers as they appear on the LSI-11 side of the interface. Figures 2-6 and 2-7
show the addresses and bit configurations of the Q bus registers.

2.4.1

Read Only Memory

The Console Interface Board contains 4K words of ROM, starting at Q bus location 140000g. This
ROM contains the bulk of the LSI-11 console operating system, including the power up routines,
drivers, look-up tables, and basic console command routines, such as EXAMINE, DEPOSIT, and
HALT.

The first two words of the ROM are also addressable as registers at locations 163000 or 1730005 and
1630023 or 173002g. These two words contain a JMP X instruction for the LSI-11, where X is the
starting address of the power up routine in the ROM. These two words are located at ROM addresses
0 and 2, and they therefore appear also at Q bus addresses 1400003 and 140002g. The LSI-11 is jumpered to fetch at 163000 or 1730005 upon power up, so that it can execute the jump to the power up
routine.

2.4.2 ID DATA LO and ID DATA HI Registers (163006/173006, 163010/173010g)

If the VAX-11/780 system clock is stopped when the LSI-11 initiates an ID maintenance cycle in order
to read an ID bus register, the LSI-11 reads the data through the ID DATA LO and ID DATA HI
registers. These two Q bus registers allow the LSI-11 to look directly at the data currently asserted on
the ID bus. They are read-only registers and the data is valid only when the VAX-11/780 CPU clock is
stopped. ID DATA LO contains ID bus data bits <15:00>. ID DATA HI contains data bits
<31:16>.

Receiver Done Register (163014/173014g) - R/W

2.4.3

The receiver done register contains one bit in bit position 07, RX DONE. This bit is the backside of the
RX DNE bit of the RXCS register on the ID bus (the same flip-flop is used for each) making this
synchronization bit available to both the LSI-11 and the VAX-11/780 CPU. From the Q bus side, RX
DONE is a read/write bit. The LSI-11 sets the bit to indicate to the VAX-11/780 microcode that valid
data has been placed in the TO ID register. RX DONE is cleared automatically by a read reference to
TO ID on the ID bus or by system initialization. The 1 to 0 transition of RX DONE will interrupt the
LSI-11 if interrupts to the console are enabled.

2.4.4 Transmitter Ready Register (163016/173016g) - R/W

The transmitter ready register also contains one bit in bit position 07, TX READY. This bit is the
backside of the TX RDY bit of the TXCS register on the ID bus, and is thus available on both buses.
From the Q side TX READY is a read/write bit. The LSI-11 sets this bit to indicate to the VAX11/780 microcode that it is ready to accept another longword in the FM ID register. TX READY is
cleared automatically when the VAX-11/780 CPU writes to FM ID on the ID bus, or when the system
is initialized. The 1 to O transition of TX READY will interrupt the LSI-11 if enabled.

The following constraints apply to these ready and done bits:

The VAX-11/780 interrupt enable bits, RXIE and TXIE, are not visible to the LSI-11.

!f the VAX-11/780 CPU clock is running, clocking RX DNE and TX RDY from Q bus data
is done at CPT 60 -~ CPT 90. These bits will therefore be stable at CPT 0 when read on the ID
bus. This feature enables the VAX-11/780 microcode to execute a tight loop, branching on
the setting of RX DNE and TX RDY. The LSI-11 can set the bit from the Q bus while it is
being referenced on the ID bus.

RXDONE and TX READY are not set automatically by references on the Q bus to the TO
ID and FM ID registers. These bits must be explicitly set by the LSI-11.
2-8

ID BUS

Q BUS

ADDRESS ADDRESS

163

173

(%)

000 ROM 0

163
173

163

173

002 ROM 1

ROM 1 DATA <15:0>

R/O
0

044 SPARE

0061D

DATA LO

SPARE

TIME

ID DATA <15:0>

R/O

010 1D

DATA Hi

ID DATA <31:16>

R/O

012 SPARE

SPARE
15

(04) (173) 014 RX DONE 0«
163

o (12)

R/O

163

173

ROM 0 DATA <15:0>

163
173

016 TX
READY

=0 [pnef

8
0 -

—0

TIME OUT

— Of R/W

TX
[£5,]0 -

-> o|rRW

*START ADRS DETERMINED BY
JUMPER W1 ON M8236. SEE PAGE

CI1BB OF M8236 PRINTS FOR
JUMPER DEFINITION’
TK-0204

Figure 2-6

Lower Eight Q Bus Registers:
Addresses and Bit Configurations
(Address Bit 4 is False)

2-9

ID BUS

ADDRESS

Q BUS

ADDRESS

(05)

173

020 TO
IDLO

163

02270

173

ID HI

163

00
R/W

TO ID <15:0>

(05)

00
R/W

TO ID <31:16>

15
(05)

163

024 FM

173

ID LO

00
R/O

FM ID <15:0>

(07)

163

026 FM

173

1D HI

163) 030D C/S

5
.

(INVERTED)

MAINT

RCV
WRITE

R/W

IDI

CYCLE

ID ADDRS <5:0>

RCV ID ADDRS <5:0>

<17:D 032 MCR

R/O

FM ID <31:16>

ID
WRITE

163

R/W

DISAB

HLT

UPC12

REQ

<0->

STPD
06

SBC

FREQ

CLK

ROM

NOP

PROCEED

STS

soMvm | FREQ
<1>

MAINT | STAR
INTR
RET

CPU
RESET

R/W

BOOT

AUTO
RST

DNE
IE

HALT
STATE

CNSL
CMND

LOCK

REMOTE

RDY
IE

RUN

FLPY
ON

00
R/W

V BUS SER CHNL <7:0>

CPT

v
SLFTST |

CPT
3

CPT
1
CPT

v
CLK

LOAD
TK-0205

Figure 2-7 Upper Eight Q Bus Registers:
Addresses and Bit Configurations
(Address Bit 4 is True)

2-10

2.4.5 TO ID LO and TO ID HI Registers (163020/173020g, 163022/ 173022)
- R/W
These two registers together contain 32 data bits which the LSI-11 can write
via the Q bus when
sending data to the VAX-11/780 CPU. When the microcode reads the TO ID register, it
loads the data
into the Q register in the VAX-11/780 CPU. The LSI-11 also places data in the TO ID LO
and TO ID
HI registers before performing an ID MAINT cycle to execute an ID bus write cycle. TO
ID LO and
TO ID HI are read/write registers from the Q bus side. They are readable for diagnostic
purposes.
2.4.6 FM ID LO and FM ID HI Registers (163024/173024g, 163026,/1730265) - R/O
These two registers form the Q bus side of the FM ID register. They permit the LSI-11
to read data
loaded into the FM ID register by the microcode as a result of a write reference to ID bus
address 07¢.
In addition, the LSI-11 reads data placed in the FM ID LO and FM ID HI registers when
performing
an ID maintenance cycle to execute an ID bus read cycle. FM ID LO and FM
ID HI are read only
registers, from the Q bus side.

2.4.7 ID Control Status Register, ID C/S (163030/173030g)
The LSI-11 software uses this register to monitor the ID bus address and direction lines and
to control
console generated ID bus functions directly. In combination with the ID DATA registers,
the TO ID
registers, and the FM ID registers, the ID C/S register permits the LSI-11 to read or write
any ID bus

11 to read any ID bus register when the clock is stopped. Note that writing to ID bus

stepping the clock, if the clock is not running.

registers requires

ID C/S register bit descriptions follow.

ID C/S <15> ID CYCLE - R/W
When the LSI-11 writes ID CYCLE as a |, it causes the Console Interface Board to
assert the ID
MAINT signal for one clock cycle (CPT 0 to CPT 0) if the clock is running. ID
MAINT will be
asserted at the next occurrence of CPT 0 if the clock is being single stepped. The ID
CYCLE bit is
cleared automatically at the end of the ID bus cycle. This means that the LSI-11 will read
the bit as a
zero unless the clock is in the single time state mode. See the description of the ID
MAINT bit for
further explanation.

ID C/S <14> ID RCV WRITE - R/Q, and ID C/S <13:08> ID ADRS <5:0> - R/O
These seven bits allow the LSI-11 to read the state of the ID bus left address and direction
lines. They
are valid only when the clock is stopped. Note that because of receiver gate inversions,
these bits must
be read as the complements of the logical states of the corresponding bus wires.
ID C/S <07> ID MAINT - R/W
The CIB hardware will assert the ID MAINT bit automatically, after the LSI-11 sets the
ID CYCLE
bit, at the next occurrence of CPT 0. ID MAINT will remain set for one clock cycle. The following
CPT 0 will clear it. The ID MAINT signal steers the multiplexer in the VAX-11/78
0 CPU which
selects the source of the ID bus address and direction lines. During the time that the ID
MAINT signal
is asserted, the ID bus address and direction (WRITE) lines will be sourced from bits <06:00> of the
ID control/status register.

If the VAX-11/780 CPU clock is running, ID MAINT is a read-only bit and writing to it has
no effect.
However, it will be read as a 0 by the LSI-11 since it is asserted only for a 200 ns cycle.
If the VAX-11/780 CPU clock is not running (the CLOCK STOPPED bit in the MCR is set), the LSI-

11 may set or clear the ID MAINT bit by writing a 1 or a 0 to it. This feature enables the LSI-11
to
statically read ID bus registers via the ID DATA LO and ID DATA HI registers. The address
and
WRITE fields may be written by the LSI-11 together with ID MAINT or ID CYCLE,
in the same
instruction.

LSI-11 initialization clears both the ID MAINT and the ID CYCLE bits.

2-11

ID C/S <06> ID WRITE - R/W, and ID C/S <05:00> XMT ADRS <05:00> - R/W
These seven bits form the ID bus address and direction lines during an ID cycle invoked by ID
CYCLE or ID MAINT, enabling the LSI-11 to control the ID bus. ID C/S <06>, the WRITE bit,
should be set to invoke a write cycle and cleared to invoke a read cycle. The LSI-11 software loads the
XMT ADRS bits in true form (high true). These bits are cleared by LSI-11 initialization.
When the LSI-11 writes to an ID bus register, the data is sourced from the TO ID register. For static
reads (clock stopped) the LSI-11 reads the data in the ID DATA LO and ID DATA HI registers. On
dynamic reads the data is available to the LSI-11 in the FM ID LO and FM ID HI registers on the
following cycle.

2.4.8

Machine Control Register, MCR (163032/173032g)

The LSI-11 software uses the machine control register to control and monitor several functions of the
VAX-11/780 CPU. The following bit descriptions outline these functions.

MCR <15> Halt Request - R/W
The LSI-11 sets this bit to force the VAX-11/780 microcode to jump into the console wait loop. The.
VAX-11/780 CPU recognizes the assertion of HLT REQ and sets the halt pending flip-flop in the
interrupt control logic of the VAX-11/780 CPU. When the CPU passes through the instruction register decode (IRD) state and the halt pending flip-flop is set, the microcode will set the console command mode (CNSL CMND MODE) bit and enter the console wait loop. This mode is indicated on the
CIB by the assertion of HALT STATE (MCS bit <07>) and on the control panel by the lighting of the
ATTN indicator. Later, when the microcode invokes the CONTINUE function, in response to a
command from the LSI-11, the halt pending flip-flop and the CNSL CMND MODE bit are both reset,
and the VAX-11/780 CPU enters the IRD state. If the Halt Request signal is still enabled on the CIB,
the halt pending flip-flop will set again, but not until the VAX-11/780 CPU leaves the IRD state.

This means that the invocation of a CONTINUE function with HLT REQ asserted results in a single
instruction execution. In order to cause the VAX-11/780 CPU to resume normal instruction execution, the LSI-11 software must first clear HLT REQ and then issue a CONTINUE command. The
LSI-11 system initialization clears HLT REQ.

Note that the VAX-11/780 microcode can branch on the state of the CNSL CMND MODE bit. This
enables the microcode to determine, when in various error routines, whether the routine was entered as
a result of some console requested function or normal machine execution.
MCR <14:13> Reserved

MCR <12> CPU RESET - R/W
When the LSI-11 sets CPU RESET, it forces the assertion of the internal initialization signal (DC LO

equivalent) within the VAX-11/780 CPU. Upon the negation of CPU RESET, the microcode enters
the power-up initialization routine. LSI-11 system initialization clears this bit.
MCR <11> Reserved

MCR <10> Maintenance Return Enable - R/W
When the LSI-11 writes a 1 to this bit, it causes the VAX-11/780 CPU to perform a maintenance

return function. The VAX-11/780 CPU pops the top element of the microstack and disables the J-field
inputs. The result is a forced jump to the location addressed by the word at the top of the microstack.
MAINT RET ENABLE remains asserted at the microsequencer approximately 100 ns, from CPT 150
to CPT 50. When the VAX-11/780 CPU is in the single time state mode, MAINT RET ENABLE will
remain asserted from the time it was written as a one until the next occurrence of CPT 50. Note that
the LSI-11 should not attempt a maintenance return function unless the VAX-11/780 CPU is in the

console wait loop.

2-12

MCR <09> Trap to Writable Control Store - R/W
|
When the LSI-11 sets TRAP TO WCS, it forces bit 12 of the UPC to a one whenever a microtrap
occurs, in turn forcing the trap into writable control store. This bit should be set or cleared only when
the VAX-11/780 CPU is in the halt state or the clock is stopped. LSI-11 system initialization clears the
TRAP TO WCS bit.
MCR <08> Star Interrupt Disable - R/W
When the LSI-11 sets this bit, it disables the TX RDY and RX DNE interrupts to the VAX-11/780

CPU, regardless of the state of the interrupt enable bits, TXIE and RXIE. It furthermore inhibits any
change in the state of the interrupt pending flip-flops in the terminal interrupt control logic on the CIB.
STAR INTR DISAB allows the LSI-11 use of the TO ID and FM ID registers and the ready and done
bits for console functions (when the LSI-11 is in the console I1/O mode) without causing extraneous
interrupts to the VAX-11/780 CPU.

MCR <07> ROM NO-OP - R/W
When the LSI-11 sets this bit, it generates the CLR UWORD and ABORT CYCLE signals in the
microsequencer, producing the same effect as STALL. ROM NOP thus forces NOPs on the various
subsystem control fields so that random patterns from WCS will not produce undesired side effects
during testing. If the bit is set while the clock is stopped, the clock must be stepped to CPT 0 before the
ROM NOP signal takes effect. This bit is cleared by LSI-11 system initialization.
MCR <06> Stop on Microbreak Match - R/W
If the VAX-11/780 CPU detects a match between the microbreak register and the UPC and the LSI-11
has set the SOMM bit, the clock will stop in CPT 0 of the cycle in which the match occurs. This in turn
causes the assertion of the CLK STPD signal. The SOMM bit is cleared by LSI-11 system initialization.
MCR <05> Clock Stopped - R/O
This read only bit is formed by a signal which originates in the clock control logic. It is set when the
clock is not running. CLK STPD is also used in several circuits on the Console Interface Board for
determination of whether or not synchronization to the VAX-11/780 CPU clock is necessary. LSI-11
system initialization clears this bit.

MCR <04:03> Frequency Select <1:0> - R/W

The LSI-11 software sets these two bits to control the VAX-11/780 CPU clock frequency, as shown in
Table 2-1.

Table 2-1

Clock Frequency Control

FR 1

FRO

Frequency

0
0
1

0
1
0

10.0 Mhz (normal)
10.525 Mhz (5% short)
8.925 Mhz (12% long)

External Source

FR 1 and FR 0 should not be changed when the clock is running. LSI-11 system initialization clears
both bits.

2-13

MCR <02> Single Time State - R/W

If the LSI-11 software sets the STS bit when the VAX-11/780 CPU clock is running the clock will stop
in any of the four time states. As long as the STS bit is set, and regardless of the state of the Single Bus
Cycle bit, writing a 1 to the PROCEED bit will step the clock one time state (e.g., from CPT 100 to
CPT 150). LSI-11 system initialization clears the STS bit.
MCR <1> Single Bus Cycle - R/W

If the LSI-11 asserts this bit (and the STS bit is 0) while the clock is running, the clock will stop in CPT
0. As long as SBC is set and STS is cleared, writing a 1 to PROCEED will step the clock to the next
CPT O (i.e., one ROM/SBI cycle). LSI-11 system initialization clears the SBC bit.
MCR <0> Proceed - W/O

When the LSI-11 software writes a 1 to the PROCEED bit, it will affect the clock in any of three ways,
depending on the states of the STS and SBC bits, as shown in Table 2-2.
Uses of PROCEED

Table 2-2

STS

SBC

Clock

—

start clock running immediately

—

step clock one time state

PROCEED

—

step clock one cycle

step clock one time state

Writing a 1 to the PROCEED bit when the clock is running has no effect. LSI-11 system initialization
clears the bit. Note that CPT 0 = SBI T1. In other words the SBI leads the CPU by one time state.
Constraints on Clock Control

The proper method for stopping the clock is to write a 1 to the SBC bit. In this way the stopped clock
state is known to be CPTO.

Clearing the STS and SBC bits will not start the VAX-11/780 CPU clock. The LSI-11 software must
write a 1 to the PROCEED bit after STS and SBC have been cleared in order to start the clock.
2.4.9

Miscellaneous Control and Status Register, MCS (163034/173034g)

The miscellaneous control and status register enables the LSI-11 software to control and monitor some
of the console subsystem functions and the interaction between the LSI-11 and the VAX-11/780 CPU.
Descriptions of the bit functions follow.

MCS <15:13> Reserved

MCS <12> Floppy On - R/W

The FLPY ON bit controls power to the console floppy disk drive through a relay. When the LSI-11
sets the bit, it turns on power to the floppy. Clearing the bit turns the floppy off. The LSI-11 system
initialization clears FLPY ON.
MCS <11> Boot - R/W

This read/write-one to clear bit is set by a 0 to I transition of the signal from the BOOT switch on the
control panel. The bit will be cleared when the LSI-11 writes a 1 to the bit location and when the LSI11 system is initialized.

2-14

MCS <10> Reserved
MCS
<00>
r‘nnsala Cammand Mada
VAL A
NUST
S

LUBIUIY

L Ulliilgiiu

iVAUUE

—

D /N

I\YAVS

This read-only bit permits the LSI-11 to determine the state of the VAX-11/780 CPU. The CNSL
CMND MODE bit is set by the VAX-11/780 microcode together with the assertion of HALT STATE.
The bit remains set until cleared by the microcode while executing a CONTINUE function. When set
this bit lights the ATTN indicator on the control panel.
MCS <08> Run - R/O
This read-only bit is the *“1” side of a retriggerable one-shot. The one-shot is clocked by the VAX11/780 interrupt strobe signal, and it will remain set as long as the VAX-11/780 CPU is strobing
interrupts at least every 0.423 ms. When the VAX-11/780 CPU enters the console command mode, the
RUN one-shot times out. Also, while the VAX-11/780 CPU is running and executing macrocode, the
negation of RUN generally indicates some type of problem. For example, the microcode might be
hung in a loop or there might be a hardware failure. The RUN one-shot is also used to light the RUN
indicator on the control panel.
MCS <07> Halt State - R/O
The HALT STATE bit is the raw decoded output of a ROM field which is asserted if and only if the
microcode is in the console wait loop. This bit is required because the CNSL CMND MODE bit,
which is set upon entry into the console wait loop, will remain set even if the microcode leaves the loop.
The LSI-11 software therefore is able to use the HALT STATE bit to determine whether or not the
microcode has returned to the console wait loop following a console microcode function (other than
CONTINUE). The LSI-11 must also test the HALT STATE bit to be sure that the microcode is in the
console wait loop before performing a console ID maintenance cycle.
MCS <06> Transmit Ready Interrupt Enable
The LSI-11 sets the TX IE bit in order to enable interrupts from the VAX-11/780 CPU to the LSI-11

upon a I to 0 transition of the TX RDY bit. If the TX RDY bit is already 0, and the TX IE bit goes

from a 0 to a I, the interrupt will occur. LSI-11 initialization clears the TX IE bit.

MCS <05> Receiver Done Interrupt Enable
The LSI-11 sets the RX IE bit in order to enable interrupts from the VAX-11/780 CPU to the LSI-11
upon a 1 to 0 transition of the RX DNE bit. If the RX DNE bit is already 0, and the RX IE bit goes
from a 0 to a 1, the interrupt will occur. LSI-11 initialization clears the RX DNE bit.
MCS <04:03> Reserved

MCS <02:00> Panel Switch Sense - R/O
These three bits sense the positions of control panel switches, as shown in Table 2-3.

Table 2-3

Panel Switch Sense Bit Functions

Bit

Related Panel Switch

MCS <02>
MCS 01>
MCS <00>

Auto Restart Switch (AUTO RST)
Remote Mode (REMOTE)
Lock (Lock = disable)

These bits are set when the corresponding switches are on. They are not affected by system initialization.

2.4.10

V Bus Register (163036/173036g)

The V Bus register allows the LSI-11 software to perform the data load, serial shift, and self test
functions on the V bus by writing to the V Bus register. The serial data retrieved from polling stable
internal state VAX-11/780 CPU test points is then available when the LSI-11 software reads the
register. A description of the V Bus register bits follows.
V-BUS <15:08> Serial Data Bits - R/O

These eight bit positions are loaded with serial data from shift registers on the eight V bus data
channels which originate within each of the VAX-11/780 CPU subsystems.
V-BUS <07>: CPT 0 - R/O

V-BUS <06>: CPT 1 - R/O
V-BUS <05>: CPT 2 - R/O
V-BUS <04>: CPT 3 - R/O

These four bits enable the operator to determine the state of the VAX-11/780 CPU clock when the
clock is stopped.
V-BUS <03> Reserved

V-BUS <02> SDMS Self Test - R/W-:
This signal feeds the data input to the most remote bit of the shift register connected to each of the V
bus channels. The LSI-11 software uses the self test bit to assure correct operation of the V bus system
by shifting a known bit pattern through each channel (as shown in Figure 1-4). The bit can be set or
reset only by writing a 1 or a 0 to the bit location.
V-BUS <01> SDMS Load - R/W

The LSI-11 software sets this bit in order to parallel load machine state information into each of the
shift registers on the V bus channels. If the LSI-11 asserts bits | and 0 with the same instruction, a load
function is guaranteed. Bit 1 must be reset by the LSI-11 software for a shift to take place.
V-BUS <00> SDMS Clock
- W/O

When the LSI-11 software writes a 1 to the SDMS CLOCK bit, it causes a 2 us pulse to be applied to
the clock inputs to all V bus channel shift registers. If the LSI-11 software asserts the SDMS CLOCK
bit, and the SDMS LOAD bit is reset, a shift will take place on each V bus channel shift register,
causing the next bit of data from each of the shift registers to be available in the upper byte of the V
Bus register.

2.5

DIALOGUE: LSI-11 PROGRAM 1/0 - VAX-11/780 MACROCODE

When the LSI-11 is in the program I/O mode and the VAX-11/780 CPU is executing macrocode, the
two processors use the TO ID and FM ID registers as the RXDB and TXDB, respectively. Interrupt
service routines on each side handle the transfers.

2.5.1

LSI-11 Sends a Character to the VAX-11/780

When the console terminal operator types a character, the terminal interface interrupts the LSI-11. An
LSI-11 interrupt service routine then loads the ASCII code for the character into the lower eight bits of
the TO ID LO register on the CIB and then sets the RX DNE bit to interrupt the VAX-11/780 CPU.
Figure 2-8 is a flowchart showing the dialogue between the VAX-11/780 macrocode, the VAX-11/780
microcode, and the LSI-11 software.

2-16

VAX-11/780 MACROCODE

VAX-11/780 MICROCODE

LSI-11 SOFTWARE

LSI-11
INTERRUPTS
VAX-11/780

:
ENTER
RX DNE
INTERRUPT

SUBROUTINE

ERROR

’:;g:

QREG «

STORE

TOID

RX DNE <0

REG

INTERRUPT

RX DONE
INTERRUPT

SUBROUTINE

LSI-11

VIA ID BUS

ERROR

ANOTHER

CHARACTER

FROM

TERMINAL

LOAD
CHARACTER
INTO

RT1

ENTER
RX DNE

LSI-11

INTERRUPTS VAX-11/780 CPU

INTERRUPT

SUBROUTINE
TK-0201

Figure 2-8
'

LSI-11 Sends a Character to the

VAX-11/780 CPU, Flowchart

2-17

The VAX-11/780 CPU responds to the interrupt by invoking an interrupt subroutine. This routine
tests the RX DNE bit on the CIB. If the bit is set, the subroutine executes an
MFPR instruction to read
the TO ID register (RXDB) and stores the data in the Q register in the VAX-11/780 CPU. This action
causes the RX DNE bit on the CIB to reset, thus causing the CIB to send an interrupt signal to the
LSI-11. This interrupt in turn invokes an LSI-11 interrupt subroutine which tests the RX DNE bit on
the CIB. If the RX DNE bit is reset, as it should be, the subroutine determines whether or not the
terminal is waiting to send another character to the VAX-11/780 CPU. If the terminal does have
another character to send, the subroutine loads the ASCII equivalent into the TO ID register on the
CIB and then sets the RX DNE bit, causing another interrupt to the VAX-11/780 CPU. The LSI-11
software then returns from its interrupt subroutine.
2.5.2 VAX-11/780 Sends a Character to the LSI-11
When the VAX-11/780 software is transmitting a series of characters to the LSI-11, the LSI-11 will set

the TX RDY bit on the CIB each time it reads a character. The setting of TX RDY then generates an
interrupt signal to the VAX-11/780 CPU, invoking a transmit interrupt subroutine, as shown in Figure 2-9.

The transmit interrupt subroutine executes an MTPR instruction to load the character into the TXDB
(FM ID register on the CIB) and return from the interrupt to the main program. The VAX-11/780
microcode implements the MTPR instruction, loading the FM ID register from the Q register. The
loading of FM ID automatically resets the TX RDY bit, generating an interrupt to the LSI-11. The
LSI-11 receive interrupt subroutine checks the TX RDY bit and then reads the data in the FM ID
register and sets the TX RDY bit.

The LSI-11 then returns from the receive interrupt subroutine. The setting of the TX RDY bit generates another interrupt signal to the VAX-11/780 CPU, notifying the VAX-11/780 software that the
FM ID register is empty and ready for another character.
2.6 DIALOGUE: LSI-11 CONSOLE I/0 MODE - VAX-11/780 MICROCODE
When the VAX-11/780 CPU is halted (in the console wait loop) and the LSI-11 is in the console I/O
mode, the LSI-11 may direct VAX-11/780 microcode routines to perform various functions which
implement console command language instructions, such as an examine virtual address instruction.
The TO ID and FM ID registers on the Console Interface Board are used to pass the parameters
needed by or supplied by these routines, and the transfers are interlocked through use of the ready and
done bits. However, when the LSI-11 sets the TX RDY bit or the RX DNE bit, no corresponding
interrupt to the VAX-11/780 CPU is generated. Instead, the VAX-11/780 microcode assumes the
responsibility for determining that the TX RDY bit or the RX DNE bit is set before writing or reading
data in the FM ID register or the TO ID register.
The LSI-11 software invokes the VAX-11/780 microroutines needed to execute a console command
language instruction by writing the starting address of the microroutine to the microstack, thus pushing the address on the microstack. The LSI-11 software then writes a 1 to the MAINT RET ENABLE
bit in the MCR register on the CIB, popping the microstack and forcing a jump to the address specified. All VAX-11/780 microroutines invoked from the console except CONTINUE must return to the
console wait loop.
Three types of events will cause the VAX-11/780 CPU to enter the Halt State (console command
mode).

The VAX-11/780 CPU may execute a HALT instruction which is coded within a Macro
program listing.

The VAX-11/780 CPU may halt as the result of an error condition.

The console terminal operator may type a HALT command on the terminal while the LSI11 is in the console I/O mode, causing the VAX-11/780 CPU to halt.
2-18

VAX-11/780 MACROCODE

VAX-11/780 MICROCODE

ENTER

TX RDY

INTERRUPT VAX-11/780 CPU

LSI-11 SOFTWARE

INTERRUPT

SETS TX READY

SUBROUTINE

BIT

DY - 1

ERROR

TX READY « 0

INTERRUPT LSI-11

YES

MTPR,

DATA,

ENTER

TX READY

FM ID < DREG

INTERRUPT
SUBROUTINE

TXDB

ERROR

READ FM ID
REGISTER

TX READY « 1

ENTER

RTI

TX READY
INTERRUPT
SUBROUTINE

TK-0202

Figure 2-9 VAX-11/780 Sends a Character
to the LSI-11, Flowchart

In any case, the microcode will load the D.SV register on the ID bus with a code which identifies the
reason for the halt. If the LSI-11 is in the program I/O mode, and the VAX-11/780 CPU enters the
halt state because of a programmed halt or an error condition, the LSI-11 software will sense the halt
by reading the HALT STATE bit (MCR <10>) when it goes through a null loop, and thus branch out
of the program 1/0 mode in order to display the reason for the halt on the terminal and enter the
console 1/O mode.
However, the LSI-11 software must determine whether or not the TO ID and FM ID registers contain
valid data, and if so, save that data, before using those registers to read the contents of the D.SV
register. The flowchart given in Figure 2-10 shows the steps taken by the LSI-11 software in response
toa VAX-11/780 CPU halt.
2-19

LSI-11 RUNS IN

PROGRAM I/0

TX READY « 1

MODE (VAX-11/780

MACROCODE)

’
NO

TOID «TMP1
RX DONE
« 1
.

YES

RX DONE <0

LSI-11 ENTERS

CONSOLE 1/0
MODE

STAR INTR
DISAB <0
ENABLE LSI-11

INTERRUPTS

READ FM 1D

TX READY <«

INITIATE

CONTINUE
MICROROUTINE

IN VAX-11/780 CPU

YES

DONE=0

NO
TMP1«<TOID
TMP 2 « RX DONE

STAR INTR
DISAB « 1
I

:
USE CiB
REGISTERS FOR

CONSOLE
FUNCTIONS

CONTINUE

YES
TK-0203

Figure 2-10

LSI-11 Response to a VAX-11/780 CPU Halt

2-20

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Then, if the RX DNE bitis 2, indicating that the TO ID register contains data from the LSI-11 which
the VAX-11/780 microcode has not yet read, the LSI-11 must save the data and the state of the RX
DNE bit.
The LSI-11 then sets the STAR INTR DISABLE bit (MCR <08>), freezing the state of the VAX11/780 interrupt control logic on the CIB. The TO ID and FM ID registers and the READY and
DONE bits are available to the LSI-11 software for other functions. At this point, the LSI-11 software
can read the D.SV register and the operator can execute the various console command language
instructions.
Some time later, when the console terminal operator issues
software takes the following steps.

a CONTINUE command, the LSI-11

Sets TX RDY.

Reloads data saved from the TO ID register and sets the RX DNE bit, if RX DNE was set at
the time of the halt.

Reenables interrupts to the VAX-11/780 CPU, enables interrupts to the LSI-11, and executes CONTINUE by pushing the starting address of the continue routine onto the microstack and then setting the MAINT RET ENABLE bit.

This sequence is necessary for two reasons. It prevents false interrupts to the VAX-11/780 CPU, and it
ensures that interrupts do occur when the single instruction step mode is used.
2.7 DIRECT ID BUS REFERENCE
When the LSI-11 is in the console I/O mode and the VAX-11/780 CPU is in the console wait loop, the
LSI-11 software references certain ID bus registers in the execution of some of the console command
language instructions.
2.7.1 1D Bus Reference with the Clock Running
When the VAX-11/780 system clock is running, the LSI-11 software can write to any ID bus location

by loading the data to be written into the TO ID LO and TO ID HI registers and then writing the
register address and setting the WRITE and ID CYCLE bits in the ID C/S register. Note that the ID
CYCLE bit may be set on a following instruction. In either case the ID maintenance function causes
the data in the TO ID register to be written into the register addressed.

The LSI-11 software reads ID bus registers similarly, except that the WRITE bit of the ID C/S register
must be 0. At the completion of the ID bus cycle, the data from the register addressed is available in
the FM ID LO and FM ID HI registers.

2.7.2 ID Bus Reference with the Clock Stopped
The LSI-11 can read any ID bus register with the clock stopped by placing the desired address in the
ID C/S register, clearing the WRITE bit, and setting the ID MAINT bit. However, since all ID bus
register strobe signals are disabled in CPT 0 it is necessary to step the clock to the time state in which
the desired strobe will enable the data onto the ID bus. As long as ID MAINT is set, the clock is in the
correct time state, and the WRITE bit = 0, the addressed register may be read through the ID DATA
LO and ID DATA HI registers. The address may be changed even while ID MAINT is set, enabling
data from a newly addressed register onto the ID bus as long as the clock is in a time state which
enables the appropriate strobe. The ID MAINT bit should be cleared before the clock is started again.

2-21

The LSI-11 software cannot write to ID bus registers when the clock is stopped without stepping
through time states. But the LSI-11 software can accomplish write functions with the clock stopped by
first ensuring that the clock is in CPT 0, then loading the data to be written into the TO ID LO and TO
ID HI registers, and then setting the WRITE and ID MAINT bits and loading the desired address into
the ID C/S register. Invoking a single bus cycle via PROCEED will then write the data into the
registeraddressed and clear the ID MAINT bit. The LSI-11 software can accomplish read functions in
a similar manner.

2.7.3

ID Bus Reference without use of Console Command Language Instructions

The console terminal operator may circumvent the LSI-11 console I/O mode software by moving the
HALT/ENABLE switch on the LSI-11 control panel within the cabinet to the HALT position. This
causes the LSI-11 to jump to the ODT (Octal Debugging Technique) routine, permitting read and
write access to any Q bus register, and thus, indirectly, to the ID bus. The LSI-11 will also jump to the
ODT routine if the operator presses the BREAK key on the console terminal. See Section 2, Chapter 2
of the Microcomputer Handbook for details of ODT.

2-22

CHAPTER 3
CIB DETAILED LOGIC DESCRIPTION

3.1 CONSOLE INTERFACE BOARD LOGIC
The Console Interface Board logic falls into four categories: ID bus interface, Q bus interface, ROM
logic, and register logic, each of which is described in one of the four following subsections. A fifth
subsection, consisting primarily of flowcharts, traces typical transfer operations at the detailed level.
3.2 ID BUS INTERFACE LOGIC
When the VAX-11/780 CPU asserts an address on the ID bus, the ID bus address decoder logic on the
CIB becomes active only if the address falls within the range of 03¢ to 07,4, as shown in Figure 3-1.
Notice that address bits 3, 4, and 5 must be false.
Two full 32 bit registers can be read from the ID bus, SYS.ID and TO ID. When either of these
registers is addressed on a read, or the CIB is writing to an ID bus register on an ID MAINT cycle,
CIBM ID ENDAT ALL L and CIBM ENDAT (7,6) L go true, enabling the transmit function of the
ID bus transceivers between CPT 100 and CPT 0. Normally, the state of CIBM SYS.ID DECODE L
generates CIBM ID MUX SEL L, governing the output of the 2:1 multiplexer shown in Figure 3-2,
and determining whether the contents of SYS.ID or TO ID are asserted on the bus. However, when the
CIB performs an ID MAINT cycle write transfer, the CIBM SYS.ID DECODE L signal is overridden,
and the TO ID register is automatically selected by the multiplexer. A 4:1 2-bit multiplexer selects one
of four sources for data bits 7 and 6 on all read transfers initiated by the VAX-11/780 CPU.
When the VAX-11/780 CPU writes to bit 6 of the RXCS or TXCS registers, the bit will set or clear
with the assertion of CIBM CLK RXIE L or CIBM CLK TXIE L at CPT 100, as shown in Figures 3-1
and 3-23. See Paragraph 3.5.2 for an explanation of the logic involved in a write transfer to the FM ID
register.
3.3 Q BUS ADDRESS DECODER AND TIMING LOGIC
The Q bus address decoder logic consists of three closely related circuits: the interface chips, the
QMUX circuit, and a one of twelve decoder circuit.

3.3.1 Interface Address Decoder Logic
When the LSI-11 processor initiates a read or write transfer to one of the CIB registers, it asserts the
address on BDAL <15:00> L and then asserts BBS7 L and BSYNC L. If the asserted address falls
within the range of the jumpered address inputs to the DCO005 interface chips, these chips will assert
MATCH H, as shown in Figure 3-3. Note that the jumper, W1, determines whether MATCH H is
asserted in response to addresses in the range of 1730XXg or 1630X X3, as follows.
W1 installed:
W1 removed:

Address 1730XXg
Address 1630XXg

Note: W1 is normally installed.
The DCO0S chips also gate the address to the tristate BUS QDATA <15:00> H lines. Bits <12:01>
are latched as CIBJ LADRS <12:01> H with the receipt of BSYNC L. The ANDing of the MATCH
H and BSYNC L signals within the DC004 interface chip enables CIBJ TRPLY L after a slight delay.
3-1

CIBFIDADRS 1L
CIBFIDADRSOL

3:8
DECODER

CIBFID ADRS 3L

CIBFIDADRS 4 L

TTTT7Y

CIBFIDADRS 2 L

CIBM SYSID DECODE L
CIBVCPT 100 H
CIBM RXCS DECODE L

CiBF RCVWRITEH
CIBM TO ID DECODE L

—0_}

CIBM TXCS DECODE L

CIBM FM ID DECODE L

CIBM RXCS DECODE L

CIBFID ADRS5 L

CIBM CLK TXIE L

CIBM CLK RXIE L

—O0

CIBM SYSID DECODE L

D CIBM ID MUX SEL L

CIBFIDADRSOL

CIBFIDADRS 1L

CIBMID (7.6) SELOH

CIBMID (7,6) SEL1 L
al!
CIBF XMT WRITE L

ro{>4

CIBF ID MAINT (O} H

“ HIGH ON ID MAINT CYCLE WRITE

CIBF ID CYCLE (O)H

CIBF RCV WRITE H

MBM ID WRITE L

CIBM ID ENDAT (7.6) L

CIBVCPTOL

\
\

ENABLE ID BUS

TRANSCEIVERS,

SENDING DATATO

VAX-11/780 CPU
/

CiBVCPT 100 L

CIBM ID ENDAT ALL L
CIBF XMT WRITE H

CIBF ID MAINT (1) H

TK-0208

Figure 3-1

ID Bus Address Decoder Logic

3-2

CIBH SYSID SW <31:08.05:00> H B\ =777
aEnd

—

OEEED

CIBH TO IDLO <15:08,05:00> H

CIBH TO IDHI <15:00> H

—‘ N

CIBM ID MUX SEL L

CIBM ID ENDAT ALLL

et
4

TRUE FROM
CPT100
TO CPTO

|
:

CIBH SYSID SW <07:06> H

|
D\ I

CIBS <RDY(1)H:TXIE(DH>

}

CIBH TO IDLO <07:06> H

CIBS <DONE
(1) H:RXIE
(1) H>

CIBMID(7.6)SEL1L

cismiD (.61 sELOH

’
}

D' >

l
|

51
3P

111

\u CIBM ID ENDAT (7.6) L

—

_
o
@

BUS TRANSCEIVERS

TK-0207

Figure 3-2

ID Data Multiplexer Logic

Q BUS BDAL <15:00> L

P‘*’z 0y

JUMPERED
ADDRESS

DCO05

INPUTS

CHIPS

CIBA. CIBB MATCH H

BUS QDATA

<04:03> H
I

2:4
2

DECODER

70 2:4
.

I -

DECODER

O- ( Loaic

SYNC

@ | BUS QDATA

<12:01>H
LATCHES

CLR

L CIBJ LADRS <12:01> H

CLK

"N\
CIBV INIT L

BSYNC L———CD—
TK-0254

Figure 3-3

Q Bus Address Decoder Logic
Interface Chips

3.3.2 QMUX Logic
Eight registers form input signals to the QMUX, as shown in Figure 3-4.
When the LSI-11 processor performs a read transfer to one of these registers, latched address bits
<03:01> are used to select outputs of the register addressed, as shown in Figure 3-4. When CIBR
QMUX STROBE L is asserted, it enables the contents of the selected register on the tristate output of
the QMUX. Refer to Paragraph 3.3.4 for further details.

3.3.3

One of Twelve Decoder Logic

The LSI-11 processor can also read six of the CIB reglsters which do not feed the QMUX and it can
perform write transfers to a total of eight CIB registers. The one of twelve decoder loglc shownin
Figure 3-5 selects the register addressed.

3-4

BUS Q DATA <15:00> H

CIBR QMUX STROBE L

\{TB
VBUS REGISTER
D7

MCS REGISTER

MCR REGISTER
ID

D56

C/S REGISTER

TRISTATE
OUTPUT

FM IDHI REGISTER

FM IDLO REGISTER

TO IDHI REGISTER

TO IDLO REGISTER

P
pd

CIBJ LADRSO3H

CIBR QMUX
SEL 2 H

CiBJ LADRS 02 H

CIBRQMUXSEL 1 H

CiBJ LADRSO1 H
CIBRQMUXSELOH
Hl ——
TK-0209

Figure 3-4

QMUX Logic

2:4
DECODERS

— CIBJ SELROM O L

CiBJ LADRS 02 H

—CIBJ SEL ROM 1 L
D—

CIBJ LADRS 01 H

D—CIBJ SEL ID DATA LO L

- g

N—CIBJ SEL ID DATA HI L

BUS QDATA

03 H

D—CIBJ SEL DONE L

—
—

D—CIBJ SEL READY L

.
D—CIBJ SEL TO IDLO L

D—- CIBJ SEL TO IDHI L

DC004

O—
——

—CIBJ SEL ID C/ST L
-

BUS

QDATA |

D—CIBJ SEL MCR L

04 H

D—CIBJ SEL MCS L

—

P—cmBisELvBUS L

T
|

MATCH H
TK-0255

Figure 3-5

One of Twelve Decoder Logic

3-6

A decoder on the DC004 chip interprets the address bits on BUS QDATA <04:03> H, enabling one
of four low true nufnute when MATCH H is asserted.
i

Thege eggnn‘qinturn enable one of four
2:4
Awww

decoders. As shownin Figure 3-5, CIBJ LADRS <02:01> H select 1 of the 4 outputs of the enabled
2:4 decoder, enabling 1 of 12 select register signals. The following signals will enable a strobe signal
gating the contents of the selected register onto the BUS QDATA <15:00> H lines when the LSI-11
processor performs a read transfer.
CIBJSELROMOL
CIBJSELROM1IL
CIBJSELID DATALOL
CIBJSELID DATAHIL
CIBJSELDONEL
CIBJ SEL READY L
When the LSI-11 processor performs a write transfer to one of the CIB registers, only the one of twelve
decoder logic is used, enabling one of the following signals:

CIBJSEL DONEL
CIBJ SEL READY L
CIBJSELTOIDLOL
CIBJSELTOIDHIL
CIBJSELIDC/STL
CIBJSEL MCRL
CIBJSEL MCSL
CIBJ SEL VBUS L
See the descriptions of the specific registers for further details on read and write transfers from the LSI11 processor to the CIB registers.
3.3.4 Strobe Signals Developed on a Q Bus Read Transfer
On a Q bus read transfer the LSI-11 processor negates the address after the CIB address logic has had
time to decode and latch it. The LSI-11 then asserts BDIN L. The DCO004 chipin turn enables CIBJ
'Wn
L. Tl‘ns fr!gnnfo a nna_ch
T
hin
" An fkn tra
o~ arlna ~Aftha
<ha
gers a one-shot which
setsa flxy-flGp
On wnc tra fi5
Gge O1 i punSc, as shown
in
Figure 3-6.
4

111

If CIBJ GATE ROM H is false and CIBJ LADRS 04 H is true, CIBR QMUX STROBE L is asserted,
enabling the tristate output of the QMUX onto the BUS QDATA lines. The logic for CIBR ID DATA
STRB L, CIBR QDATA <7> STRB L, and CIBR ROM ENAB L is similar.
3.3.5 Clocking the Registers on a Q Bus Write Transfer
When the LSI-11 processor performs a write transfer to a CIB register, it replaces the address on the
BDAL lines with data to be written and asserts BDOUT L, after the CIB has decoded and latched the
address. BDOUT L enables CIBJ OUTHB L or CIBJ OUTLB L or both on the DC004 chip, depending on the states of address bit 0 and BWTBT. These signals are ANDed with a synchronizing flip-flop
signal (see Paragraph 3.3.6) to produce CIBT CLK HB L and CIBT CLK LB L. And these signals are
in turn ANDed with one of the select signals from the one of twelve decoder logic (Figure 3-5) to
produce | of the 15 register clock signals shown on sheet CIBU of the print set. Note that the data to
be written is not latched until the clock signal(s) develop a rising edge.
3.3.6 Transfer Synchronization Logic
The VAX-11/780 CPU and the LSI-11 processor may happen to perform data transfers to the same
register simultaneously. The synchronization logic shown in Figure 3-7 ensures that the transfer of
unstable data will not result by making sure that CIBT XMT RPLY H and BRPLY L are not asserted
until the CPT 50 following the CPT 150 which follows the assertion of CIBJ TRPLY by the DC004
interface chips.
3-7

_TP3L

CIBJ SEL ID DATA HI L

}cma ID DATA STRB L

CiBJ SEL ID DATA LO L

CiBJ GATE ROM H

/
CIBJ LADRS 04 H

CIBR QMUX STROBE L

—

HI
TP1 L
|
TE
R ROM L
ClBJ
GATE

CIBR QDATA <7> STRB L

CIBJ SEL DONE L

CIBR QBUS XMT H

CIBJ SEL RDY L

CIBT XMT RPLY H —

Hi ——

—Qq__/

ONE-

SHOT| LT
0

CLK 0O ._O
CLR

CiBJ INWD L

CIBV INIT H
CiBJ GATE ROM L

CIBR ROM ENAB L

)
‘

TP2 L

NOTE:
TP1, TP2, AND TP3 ARE TEST POINTS WHICH
MAY BE GROUNDED BY THE MAINTENANCE PERSON TO

DISABLE THE RELATED CIRCUITS.
TK-0266

Figure 3-6

3-8

CLKN STOPPED Hi

CIBT CLK STOPPED L

CIBN SBC L

CIBN STS L
>_\

e
CIBP VECTOR H

CIBT XMT RPLY H

CIBJ TRPLY L
HI

CIBV INIT H

|
)

‘

hmenrnad

CIBJ GATE ROM H
CIBJJ INWD L

CIBJ SPARE H

(L
0

SET

—Q
|,

CIBV

CPT CPT 150 H

e’
FLIP-

CIBJ TRPLY L

FLIP—Q

FLOP
1

CLKcip Of
I

FLOP
2

CIBJ OUT HB L

CIBT CLK HB L

ciBv CPT 50 HCLK.,- O}
N

]

)}cm CLK LB L

CIBJ OUT LB L
TK-0257

Figure 3-7

Transfer Synchronizer Logic

3-9

The two flip-flops shown in Figure 3-7 make up the core of the synchronization logic. A read or write
transfer to any Q bus addressable CIB register will cause the first flip-flop to set on the CPT 150
following the assertion of CIBJ TRPLY L, if the VAX-11/780 CPU clock is running. The second flipflop sets 100 ns later with the assertion of CPT 50. The output of the second flip-flop qualifies CIBT
XMT RPLY H and BRPLY L.

If the transfer is a write, the rising edge of the output of the second flip-flop or the rising edge of CIBJ
OUT HB L and/or CIBJ OUT LB L will produce a rising edge on CIBT CLK HB L and/or CIBT
CLK LB L and thus on the clock signal(s) for the selected register, latching the data to be written.
Figure 3-8 shows the sequence of Q bus signals developed on a write transfer. Figure 3-9 shows how
the timing developed by the synchronizing flip-flops ensures proper coordination with the VAX11/780 CPU clock. Note that a delay between the LSI-11 write and the VAX-11/780 CPU read is built
in. The data must be valid on the ID bus between CPT 131 and CPT 188.
If the transfer is a read to any Q bus readable register except TX READY or RX DONE, CIBT XMT
RPLY H is ANDed with CIBR QDATA (7) STRB L (false) to qualify CIBR QBUS XMT H. This
signal enables the transmit function of the transceiver gates on the DCO005 chips, gating the data from
the BUS QDATA <15:00> H lines to the Q bus. For further discussion of transfers to TX READY
and RX DONE, refer to Paragraph 3.5.8. Figure 3-10 shows the sequence of Q bus signals developed
on a read transfer. Figure 3-11 shows how the synchronization flip-flops affect the timing of the
transfer. Note that a minimum of 100 ns delay between a VAX-11/780 CPU write and an LSI-11 read
is certain.

R SYNC

R DOUT

>25 —+f

BUS T RPLY

res7 [ /[

R DATA

RDAL __ XRADORSY
s

_; o :CLOCK RCVD DATA

X__asserion=evre___X//

/777777777 /777777777

DATO/B TRANSFER CYCLE
TK-0231

Figure 3-8

DATO/B Transfer Timing on the Q Bus

3-10

CPT 50
LATCH DATA —

LATCHED DATA IS
GATED TO ID BUS

FROM Q BUS

woas XERBERX R
AA A'l'f‘H

(

om0 7777777777777
)

'
{

{ f—

R DOUT

FF1*

{

CPT 150

j‘ ’_M

FF2*

;5—\_‘ .

XMT RPLY

OUT HB L

R SYNC

BUS T RPLY

(

)

\¥

{ ¢ CPT 150

) "m

fl7 —

{}

- 50 NS MIN

ST
150 NS MIN—

CPT 50

CLKHB L

/ —\

CPT 100

*FF1and FF2 ARE FLIP-FLOPS SHOWN IN FIGURE 3-7, ABOVE.
TK-0232

Figure 3-9

Synchronized DATO Transfer Timing Diagram

R/T DAL

R SYNC

raoors X/////
1

>7%

toata X///////7//
/)X ~oors X//

>Ole—

>25

R DIN

res7 _X

——>300

BUS T RPLY

—

X777
7T T T T T T T T 7T
DATI TRANSFER CYCLE
TK-0231

Figure 3-10

DATI Transfer Timing on the Q Bus

DATA RECEIVED FROM __ __LATCHED DATA IS

ID BUS IS LATCHEDT

GATED TO Q BUS

)

1) \f

) )

{

BYY

[

R SYNC

—¥

—

R DIN

w1 oan
X aoors X777 V777777007X TR X

fi !

(

TRPLY

CPT 150

(V77T

CPT 50

FF2*

)

BUS

100 NS MIN ~*|

(

TRPLY

——i}
L

[ {

1)
‘

‘ o

)}

)]

TN
1)

{(

—{(

) T

*FF1 AND FF2 REFER TO FLIP-FLOPS SHOWN ON FIGURE 3-9

Figure 3-11

Synchronized DATI Transfer Timing Diagram

3-12

CPT 150
CPT 50

L
TK-0233

3.3.7 Q Bus Transfers when the VAX-11/780 CPU is Stopped
When the VAX-11/780 CPU clock is stopped, the synchronizing flip-flops are both cleared by the
ANDing of CLKN STOPPED H and CIBJ TRPLY L (false). If the transfer is a write, CIBT CLK HB
(and/or LB) L will be asserted low with the enabling of CIBJ OUTHB L and/or CIBJ OUTLB L. The
D input to the first synchronizing flip-flop is also the signal which is ANDed with CLKN STOPPED
H or CIBN SBC L or CIBN STS L, to produce CIBT XMT RPLY H and BRPLY L, as shown in
Figure 3-8. This circuit becomes active when the DCO004 interface chip asserts CIBJ TRPLY L in
response to the initiation of a Q bus transfer, thus circumventing the synchronizing flip-flops when the
clock is stopped. Note that on a write transfer the signal which clocks the data into the register will not
develop a positive edge until CIBJ OUTHB L and/or CIBJ OUTLB L go high following the negation
of BDOUT L by the LSI-11.
34

ROM LOGIC

The first two ROM locations have two sets of addresses: 163000(or 173000)/140000 and 163002(or
173002)/140002 (octal). These locations contain a JMP X instruction and they are addressed on power

up through addresses 163000/173000g, 163002/1730023. When the LSI-11 places 163000/173000g or

163002/173002g on the Q bus address lines, CIBJ SEL ROM 0 or 1 L will be generated to perform the

following functions.
1.
2.
3.

Disable CIBR ROM AD <9:10> H.
Select ROM Bank 0 or 1, depending on the state of CIBJ LADRS 11 H.

Enable CIBJ GATE ROM L, generating CIBR ROM ENAB L after a delay following the
receipt of BDIN L (CIBJ INWD L), enabling the tristate output of the selected ROM bank
onto the BUS QDATA <15:00> H lines.

Figure 3-12 shows the ROM address logic.

When the LSI-11 processor subsequently reads ROM addresses in the 14XXXX range, BSYNC L sets
the flip-flop shown in Figure 3-13 to generate CIBJ GATE ROM H and enable the output of one of
the four ROM banks, selected by the latched address signals (CIBJ LADRS <12:01> H).
3.5

CIB REGISTER LOGIC

Not all of the CIB registers are discrete registers in the typical hardware sense. The illustrations which
accompany the following descriptions should be useful in identifying the components and operations
of the registers.

3.5.1

TO ID Register Logic

The TO ID register is the buffer used for data transmission from the LSI-11 to the VAX-11/780 CPU.
The LSI-11 can write and read the contents of the register at Q bus locations 163020/173020g and
163022/1730224, 16 bits at time. The VAX-11/780 CPU can read but not write the TO ID register at
ID bus address 05,¢. Figure 3-14 shows the TO ID register logic.

When the LSI-11 writes to the TO ID register one or two of four clock signals are needed to handle
these transfers, as shown in Figure 3-14.

Note that the BUS QDATA signals are latched in the register flip-flops on the rising edge of a clock
signal at CPT 50.

3-13

BUS QDATA <15:00> H

TRISTATE

OUTPUT

—

TRISTATE

OUTPUT

-——

HI —{

HI—1D

ONE
SHOT
—

CLR

ROM

BANK

ROM

BANK

ROM

BANK

EN1

EN2

EN1

EN2

EN1

EN2

EN1

CiBJ LADRS

EN2

<08:01> H

CiBJ INWD L
CIBVINITH

CIBR
ROM ENAB L

CiBJ GATEROM L

TP2
L

CIBJ LADRS 09 H

CIBJ SELROM 1 L
CIBJSELROMOL

CIBR ROMAD9H

CIBJ LADRS 10 H
CIBR ROMAD 10 H

CIBRBNKOENB L

2:4
DECODER
CIBJ LADRS 12 H

CIBRBNK 1 ENB L

CIBRBNK2 ENBL

CiBJ LADRS 11 H

CIBRBNK 3 ENB L

TK-0210

Figure 3-12

3-14

ROM Logic

CIBJ GATE ROM H

CIBJSELROMOL

_Decm GATE ROM L

CIBJSELROM 1 L

BUS Q DATA 13 H

cisJ
BUS Q DATA 14 H

BUS Q DATA 15 H

o BSYNCL

SET FOR ADDRESS

{D_

€L’ -

14XXXXs

REPLY D

CIBJ TRPLY L

CIBVINIT L

e
CIBJ INWD L

DCO05
Vec

TK-0211

Figure 3-13

ROM Address Selection Logic

3-15

BUS QDATA <15:00> H

QMU
X el

BUS QDATA <15:08> H

CIBH TO IDHI <15:08> H

CLR CLK

CIBR QMUX SEL2 H

CIBU CLK TO IDHI
HB L

CIBR QMUX SEL 1 H

CIBR QMUX SEL
O H

BUS QDATA <07:00> H

CIBH TO IDHI <07:00> H

CLR CLK

CIBH SYSID SW <31:00> H

CIBU CLK TO IDHI LB L
ID
A

O
BUS QDATA <15:08> H

CIBH TO IDLO <15:08> H

CLR CLK
CIBU

CLK TO

CIBM ID MUX SEL L

fl/

172)

IDLO HB L
RXCS<07:06> H

CIBH TO ID <07:06> H

BUS QDATA <07:00> H

CIBH TO IDLO <07:00> H
CLR CLK

TXCS<07:06> H

SYSID <07:06>

MUX

BUS TRANSCEIVERS

CIBM ID (7.6) SEL 1L
CIBM ID (7.6) SELOH

CIBV INIT L
CIBUCLKTOIDLOLBL

TK-0212

Figure 3-14

TO ID Register Logic

3-16

When the VAX-11/780 CPU places the address of the TO ID register on the ID bus address lines to
read the regisier, the address decoder logic asseris CIBM ID MUX SEL L selecting the A inpuis to the
2:1 ID multiplexer shown in Figure 3-2. Notice that bits 7 and 6 are handled separately in the 4:1
multiplexer. The decoding of the TO ID register address also enables CIBM ENDAT ALL L and
CIBM ENDAT (7, 6) L at CPT 100, enabling the data through the ID bus transceivers.
:

TETN

3.5.2 FM ID Register Logic
The FM ID register is a write-only register from the VAX-11/780 CPU side and a read-only register
from the LSI-11 side. The FM ID register is made up of positive edge triggered flip-flops. The clock
input signal (CIBU CLK FM ID H) develops a positive edge under only two types of conditions, as
shown in Tabie 3-1. Figure 3-15 shows the logic involved.

Table 3-1

Generation of the CLK FM ID H Signal

FMID

XMT

(O)H

H
H
X

X
X
H

H
X
H

X
H
X

X
X
X

H
H
H

DECODE | WRITE

Note:

MAINT | WRITE

CPT

CLK

100

FMIDH

COMMENTS
VAX-11 CPU writes to

FM ID register.

CIB initiates a Mainte-

nance Read Function.

On all other signal combinations no positive
edge is developed.

X = don’t care condition

The ID bus data, therefore, will be latched from the ID bus transceivers only when the VAX-11/780
CPU writes data to the FM ID register or when the CIB performs a maintenance read cycle on the ID
bus. Figure 3-16 shows the FM ID register logic.
The output of the FM ID register feeds the QMU X. When the LSI-11 performs a DATI transfer to the
high or low portion of the register, the contents of the FM IDLO register or the FM IDHI register are
enabled on the BUS QDATA <15:00> H lines and sent to the LSI-11 with BRPLY L, at CPT 50.
3.5.3

ID C/S Register Logic

ID C/S

bits <14:08> are not latched on the CIB, but fed directly from ID bus receivers to the QMUX.

The ID C/S register enables the LSI-11 to control and monitor activity on the ID bus. When the LSI11 performs a read transfer to the register, the Q bus address decoder logic and the QMUX select lines
enable the output of the ID C/S register through the QMUX and on the BUS QDATA <15:00> H
lines to be asserted on the Q bus together with BRPLY L.

Figure 3-17 shows the ID C/S register logic.

The setting of ID CYCLE causes ID MAINT to set at the next occurrence of CPT 0. ID MAINT (1) H
then resets ID CYCLE at CPT 150 automatically, unless the VAX-11/780 CPU clock is stopped. The
LSI-11 writes to the ID MAINT bit through the direct set and direct clear inputs to the flip-flop.

3-17

CIBM FM ID DECODE L

CIBM IDWRITE L

CIBF ID MAINT (O) H
CIBF XMT WRITE H
CIBU CLK FM ID H

CIBVCPT 100 L

TK-0214

Figure 3-15

Development of CIBU CLK FM ID H

h/\j

FM IDHI

CIBE, CIBD, RCV ID

BUSIDD<31:16> L

CIBC,CIBD

<31:16> H

FM IDHI <15:00> H
Pa—

BUS

XCVR

CLR CLK

CIBV INIT L

0}
MUX

CIBU CLK FM ID H

RISING
EDGE

OCCURS AT

CPT 150

<
[

(o]

o
12}

IDLO

CiBD. CIBC.RCVID -

BUSIDD<15:00> L

CIBC. CisD

FM IDLO <15:00> l-u

<15:00> H

BUS

XCVR

CLR

CIBVINIT L

CIBUCLKFMIDH

CLK

=X
.
TK-0216

Figure 3-16

FM ID Register Logic

3-18

RIUIC ANATA

- &

V7T

CIBUCLKIDC/STLBH

CLKN STOPPED H
—e QMUX BIT 7

(R/W)
BUS QDATA 16 H

CIBUCLKIDC/STHB L

6 (R/W)

(ID C/S <15>)

CIBF ID CYCLE (O) H
CLR

(IDC/S <07>

SET , |CIBF ID MAINT (1) H

CIBF ID CYCLE (1) H

CiBVCPTOH
—e QMUX BIT 15

CIBFIDMAINT(OH_\\ |
CLR

vax
- 11/780 CPU)

CIBV CPT150 H

(R/0)

__ICLJ ID LEFT WRITE L

CIBV CLK STOPPED L

CIBVINIT H

(ID C/S <14>)
CIBF RCV WRITE H

- QMUX BIT 14

CIBVINITH

_
ICLJID LEFT ADDR <5:0> H
»

CiBU CLK ID C/ST LB H

BUS QDATA 07 H 1|>(’L

(ID C/S <13:08>)
CIBF RCV ADRS <5;0> L

> QMUX BITS<13:8>

CLKN STOPPED H

(R/W)

(ID C/S <06:00>)
CBF XMT WRITE H
BUS QDATA <06:00> H

LATCHES

CIBF XMT ADRS <5:0> H

> Q MUX BITS <6:0>

CIBF XMT WRITE L

CLR CLK
CIBVINITL

CIBF XMT D ADRS <5:0
: > L; (ICLJ,

VAX -11/780 CPU)

CIBUCLKIDC/STLBL
TK-0216

Figure 3-17

ID C/S Register Logic

3-19

3.5.4

MCR Register

The machine control register (MCR) enables the LSI-11 to control and monitor certain VAX-11/780
CPU functions. The LSI-11 reads the MCR register through the QMUX. Figure 3-18 shows the MCR
logic.

When the LSI-11 processor writes a 1 to MCR bit 10, MAINT RTN EN, a second flip-flop sets when
CPT 150 H goes high, enabling CIBN DMAINT RTN H. The 1 output of this second flip-flop also
loops back to clear the MAINT RTN EN flip-flop, putting a low level on the D input to the second
flip-flop. CIBN DMAINT RTN is thus disabled after one bus cycle at the next occurrence of CPT 150.
MCR bit 5 is not latched on the CIB but formed directly from CLKN STOPPED H.

MCR bit 0, PROCEED, does not feed the QMUX and thus cannot be read. As soon as the LSI-11
writes 2 1 to PROCEED, the VAX-11/780 CPU clock starts. CIBT STOPPED L then goes high
immediately, clearing the flip-flop.

3.5.5

MCS Register Logic

The LSI-11 uses the miscellaneous control status (MCS) register to monitor conditions on the control
panel (SCP) and in the VAX-11/780 CPU and to enable or disable interrupts from the CIB to the LSI11. Figure 3-19 shows the MCS Register logic.

The LSI-11 reads the MCS register through the QMUX. Notice that LOCK, REMOTE, AUTORESTART, CNSL ACK, RUN, and ATTN are read-only bits.

MCS bit 8, the RUN signal, is developed from a series of two one-shots. The 1 side of the first one-shot
feeds negative inputs of both one-shots. When the VAX-11/780 CPU starts running, ICLD ISTR H
goes high, firing both one-shots and enabling CIBN RUN H. At this point the 1 output of the first
one-shot disables the negative inputs to both one-shots. The first one-shot therefore times out after
211.5 us, whether or not ICLD ISTR H cycles again, thus reenabling the negative inputs to both oneshots. The second one-shot carries for 423 us without retriggering, however, so that RUN remains
asserted. ICLD ISTR H will be asserted again, before the second one-shot times out, if the VAX11/780 CPU is still running. This fires the first one-shot, retriggers the second one-shot, and keeps
CIBN RUN asserted.

Notice also that the LSI-11 can clear, but not set, the BOOT bit.

The LSI-11 reads the MCS register regularly when going through a null loop and on power up in order
to take appropriate action in response to a change in the status of the VAX-11/780 CPU or the control
panel.

3.5.6

V Bus Register Logic

The LSI-11 can read the V bus register at any time, and it can set and clear the self test and load bits at
any time, but it should write a 1 to the clock bit (bit 0) only when the VAX-11/780 CPU clock is
stopped and the CPU is in a stable state. Setting the clock bit at any other time may result in the receipt
of invalid data on the eight V bus channels. Figure 3-20 shows the V bus register logic.
The LSI-11 reads the V bus register through the QMUX. Bits <15:04> are not latched, but fed directly
from the VAX-11/780 CPU to the QMUX. CPT 0, 50, 100, and 150 H do not form a part of the V bus;
they are included on the V bus register so that the maintenance person can determine the state of the
VAX-11/780 CPU clock during the reading of the V bus lines.

The CIBU CLK VB LB L signal clocks the data to be written into bits 0, 1, and 2 on a write transfer.
Notice that bit 0, the SDMS CLOCK bit, can be written as a 1 only, and is self clearing, but that the
output, CIBH SDMS CLOCK H is normally high, and goes low when the bit is clocked, for the period
of the one-shot, as shown in Table 3-2. Figure 3-21 shows the timing involved.
3-20

R/W

BUS Q DATA 15 H

BUS

CIBN HALT REQH (MCR <15>)

Q DATA 12 H

CIBN CNSL RESET H (MCR <12>) e QS MUXBIT
15
MUX BIT 12

ATCHES

BUS Q DATA 09 H

ChE

CIBN UPC 12 (1) H (MCR <09>)

BUS Q DATA 08 H
CLR

Q MUXBIT9

CIBN S TAR INTR DISAB H (MCR (MCR <08>
<08>) _ o MUXBITS

CLK

CIBV INITH

CIBU CLK MCR HB L

CIBN MAINT RTN EN (1) H (MCR <10>) —+ Q MUX BIT 10

R/W

BUS Q DATA 10 H

CIBVINITH

0] =

CIBV CPT 150 H

CIBN DMAINT RTN H
>

CIBVCPT50H

DO—
R/W

BUS Q DATA 07 H
——
BUS Q

CIBN ROM NOP H (MCR<07>)
= Q MUXBIT7
CIBN SOMM H (MCR<06>) _ ) v BIT 6

BUS Q DATA 04 H

BUS Q DATA 03 H
B US Q DATA 02 H

CIBN FR 1 H (MCR<04>)

LATCHES

BUS Q DATAO1 H

CLR

CIBV INIT L

CIBN FR O H (MCR <03>) Q MUXBIT 4
IBN STS
H (MCR<02> > QMUXBIT3

C(::IBN :B(s;: ((MCR<01 >)$e QQ MUXBIT2
MUXBIT1

CLK

CIBU CLK MCR LB L
R/O
CLKN STOPPED H

CIBT CLK STOPPED L

OPPED H { MCR<05> ) e QMUXBITS

CLKN STOP
W/0

BUS QDATA OO H

CIBV INITH

CIBT STOPPED L

o
cC

CLR

CIBN PROCEED L

(MCR <0>)

TK-0217

Figure 3-18

Machine Control Register Logic

3-21

R/W

BUS QDATA 12 H

CIBU

{> o

UCLKMCSHBL
C

Hi——

FLOPPY ON (1 Hr

ofCIBPFLOPPY

CLR

ON(1)H

\CIBP FLOPPY ON H

]

(MCS <12>)

- QMUX BIT 12

R/W!
"

CIBP BOOT (1) H

QMUX BIT 11

MCS <11>)
HI

SCPABOOTSWH

)——-—CCLRO—'

HI
CIBU CLK MCS

.
H

(CONTROL PANEL)

ICLFCNSLCMD M L

ICLD ISTR H

CIBN ATTN H

+ QMUX BIT 9

(MCS<09>)

113 SEC.

=D FIRST

CIBN RUN H

OND
ONE-

ONESHOT

SHOT

2 us

4 ps

R/0

ICLF CNSLACK L

OD CIBP CNSL ACK H

o QMUX BIT 7

(MCS <07>) (HALT STATE)

R/W DC003

BUS QDATA 06 H f'D

; | CIBP RDY INTR ENAB H

CIBUCLKMCSLBL _

|(MCS <06>)

e QMUX BIT 6
-

: c o I
BUS QDATA 05 H

7|L.CIBP DNE INTR ENAB H

QMUX BIT 5

| (MCS <05>)

L
—

R/0

)
,;SCPA AUTO-RESTARTH

( M CSR/<002>)

» QMUX BIT 2

.. SCPA REMOTE H

‘MC:/EO‘ >)

» QMUXBIT
1

- SCPA LOCK H

(MCS <00>)

» QMUX BIT O
TK-0218

Figure 3-19

MCS Register Logic
3-22

SDMS CHNL 7 H

FCIM SDMS CHNL
6 H

«QMUX BIT 14

SBLV SDMS CHNL
5 H

e OMUX BIT 13

CAMV SDMS CHNL
4 H

e OMUX BIT 12

-—

TBMY SDMS CHNL3 H

=~ QMUX BIT 11

DAPR SDMS CHNL 2 H

= QMUX BIT 10

CEHS SDMS CHNL 1 H

~QMUX BIT
9

USCS SDMS CHNL
O H

e OMUX BIT
8

CIBV CPTOH

—OMUX BIT
7

CIBV CPT 50
H

A~ OMUX BIT
6

CIBV CPT 100 H

- QMUX BIT 5

CIBV CPT 150 H

= QMUX BIT 4

BUS QDATA 02 H

BUS QDATAO1 H

(VBUS REG <02>)

CIBH SDMS

LATCHES

L QMux
BIT2 ||

CLR CLK

QMUX

(])

BIT 1

LOAD (1) H

W/0
|

‘

CIBH SDMS

LOAD H

CIBH SDMS

CLOCK H

.
-

—4—.—_1/7

SLFTTSTH

(VBUS REG <01>) [/
CIBH SDMS

CiBUCLKVBLBL

BUS QDATA 00 H|

SLFTST (1) H

CIBVINIT
L

p—

= QMUX BIT 15

_[—0

ONE

SHOT

(VBUS REG <00>)

|2ys|

_I:‘QD ONE1
SHOT

__ CIBH SDMS DEL CLK H
TK-0219

Figure 3-20

V Bus Register Logic

3-23

Table 3-2

Generation of the SDMS Clock H Signal
One-shot
Output 0

CIBU
Clock
V Bus

Bus Q Data

LBL

H
H

L
H

One-Shot

CIBH
SDMS

(Pin2)

Comment

Normal condition

H
¥

LSI-11 writes a 1 to bit 0
Negative pulse on output clock-

Input

i
1

Clock

ing shift register on leading edge
(through receivers)

INPUT TO FIRST ONE-SHOT (PIN 2)
(NORMALLY HIGH)

CIBH SDMS CLOCK H

(NORMALLY HIGH)
CLOCK INPUT TO V BUS
CHANNEL SHIFT REGISTERS
ON CPU MODULES

CIBH SDMS DEL CLK H

(NORMALLY HIGH)

DELAYED INPUT TO V BUS CHANNEL

SHIFT REGISTERS ON CPU MODULES
TK-0258

Figure 3-21

V Bus Clock Timing Diagram

When the one-shot fires, the CIBH SDMS CLOCK H signal stays low for about 2 us. The CPU
modules which use this signal to clock the V bus shift registers invert the signal to develop a positive
pulse on the clock inputs to the shift register chips. The positive edge of the one-shot 0 output also
triggers a second one-shot, providing the CIBH SDMS DEL CLK H. The delay produced is 2 pus.
3.5.7

ID Data Register Logic

The ID data register provides a window to the ID bus for the LSI-11. It is unique in that it contains no
storage elements and is a read-only register, as shown in Figure 3-22.

3-24

TRISTATE

OUTPUT

BUSIDD <15:00> L

CIBC,
D RCV ID <15:00>
H

A/Eg/

BUS Q DATA <15:00> H

ID BUS

BUSIDD <31:16> L 4D CIBD.ERCVID <31:16> H \

CIBRID DATA STRB L
CIBJ SELIDDATALOL

TK-0221

Figure 3-22

ID DATA HI and ID DATA LO
Register Logic

When the LSI-11 performs a read transfer to either the ID DATA LO register or the ID DATA HI
register, the Q bus address decoder logic enables CIBJ SEL ID DATA (LO or HI) L, selecting the A or
B inputs to the 2:1 multiplexer shown in Figure 3-22. CIBR ID DATA STRB L enables the tristate
output of the multiplexer on the BUS QDATA <15:00> H lines after a delay following the receipt of
BDIN from the LSI-11.

3.5.8 Interrupt Logic
The interrupt logic enables the LSI-11 and the VAX-11/780 CPU to interrupt each other. It involves
two ID bus registers and three Q bus registers. Like other registers on the CIB, the RXCS and TXCS
registers permit access by the VAX-11/780 CPU, and the RX DONE, TX READY, and MCS (described above) registers permit access by the LSI-11 via the address decoder mechanisms.
When the VAX-11/780 CPU writes a 1 to bit 6 of the RXCS register or the TXCS register, the ID bus

address decoder logic clocks the bit at CPT 100, enabling interrupts to the VAX-11/780 CPU. Then,
when the LSI-11 writes a 1 to the READY or DONE bit, the latched signal is ANDed with the
corresponding interrupt enable bit to clock an interrupt pending flip-flop and enable an interrupt
signal to the VAX-11/780 CPU, if the CIBN STAR INTR DISAB H signal is false.
Later, when a VAX-11/780 interrupt subroutine reads the TO ID register or writes the FM ID register,
the DONE or READY flip-flop will clear automatically when the corresponding ID bus address
decoder signal is enabled, as shown in Figure 3-23. ICLC CNSL RCV ACK L (which indicates the halt
state in the VAX-11/780 CPU), CIBV INIT H, or CIBN CNSL RESET H will reset the interrupt
pending flip-flops, preventing inadvertent interrupts.

3-25

CAN BE READ

ON ID BUS

SET | (TXCS <07>)

BUS QDATA 07 H

CIBN STAR INTR DISAB HDO_

CIBS RDY (1) H

READY

CIBU CLKRDY L

CLKN STOPPED H

CIBVCPT 100 L

ol.C!BS RDY (0) H

CLR

TO DCOO3

TRANSMIT INTERRUPT

CIBMFMID DECODE L

e |

:')l

)

CIBS CNSL

XMIT INTR H

X
r

TXIE

CIBM CLK TXIE L

(TXCS <06>)

SET 1 | ciBS TXIE(1) H
D

CIBE RCVIDDO6 H

CIBM ID WRITE L

/ PENDING FLIP-FLOP

O
CLR
?

ICLC CNSL XMIT ACK L

INTERRUPT SIGNALS

DSET :

(RXCS <07>)

CIBS DONE (1) H

TO VAX-11 CPU
CAN BE READ
ON ID BUS

DONE

CIBJ CLK DONE L

C | BS\DONE (0) H /

CLR

CIBF RCVWRITE H

_ r~———

HI
HI

—O

| SET

(RXCS </oe>;

CIBS CNSL

RXV INTR H

CIBMTOIDDECODEL

TO DCOO3

\_/

CLKN STOPPED H
CIBVCPT 100 L

Jyy!

CIBV INITH

CIBS RXIE (1) H

RXIE

CIBN CLKRXIE L

CIBVINIT H
CIBN CNSL RESET H

CLR

o}—

RECEIVE INTERRUPT
PENDING FLIP-FLOP

TK0222

Figure 3-23

VAX-11/780 CPU Interrupt Logic

3-26

Also, the READY and DONE bits are included in two sets of registers so that they are accessible to
both the LSI-11 and the VAX-11/780 CPU. From the ID bus side they are read-only bits which clear
automatically. From the Q bus side they are read/write bits.
The LSI-11 processor reads the READY and DONE bits through a 2:1 tristate multiplexer as shown in
Figure 3-24. Note that the other data inputs to the multiplexer are grounded. CIBR QMUX SEL 0 H
selects the A or B input to the multiplexer. CIBR QDATA <7> L enables the data onto the tristate
BUS QDATA lines (see Paragraph 3.3.4 for an explanation of the way this signal is developed), and
thus to the data inputs to the corresponding DCO005 interface chip. The transmit enable signal for this
DCO005 chip is CIBT XMT RPLY H (not CIBR QBUS XMT H, as for the other DC005 chips). Figure

3-7 shows the development of this signal.
When the VAX-11/780 CPU reads or writes one of the two CIB data buffer registers, clearing the
corresponding READY or DONE bit, the interrupt logic generates a transmit interrupt or receive
interrupt signal to the LSI-11 on the DCO003 interface chip, as shown in Figure 3-25, if the corresponding interrupt enable bit is set.

Table 3-3 shows the functions of the five interrupt related registers.

| L_—EB\ BUS QDATA 01 H |, BDAL 01 L
CIBS RDY

STATE

SUTP.|BUS QDATA 08 H

BDAL 09 L

BUS QDATA 09 H

(1) H

BUS QDATA 07 H

DCOOS| N gpaL 0 07 L {BUS
XMIT

C}BDAL 06 L

CIBS DONE

DONE (1) H

CIBR QDATA <7> STRB L—

CIBT XMT RPLY H—

CIBR QMUX SEL O H
TK-0259

Figure 3-24

Ready and Done Multiplexer Logic

3-27

VCCI'1—8[

DCO03

CIBS RDY (0) H
BUS QDATA 06 H

vcC

RCSTA H =
ENDATA Hr—

SET
D !

CIBU CLK

RDY

ENACLK H

CLR
o)

VECTORHL1

INT
PEND

)

o0 _Do_

]

CLR
o]

VECRQSTB H ]2
BDINL

TX INT
c

CLR
Q

BIAKI

CIBP RDY INTR ENAB H

|
MICS LB L

(MCS <06>)

Tg|ENAST H

18}

vce

17
16

RQSTA H
h

—

151 ENADATA H

BIAKI L (7

12 P ENBDATA H

GND

101 RQSTB H

BiRQ L O8

}

ENACLK H
ENBCLK H

11D ENBST H

L —

—

BIAKO L

BINIT L@-(DO-‘

BDIN L@_OD

{_DG

DATA 05 H

ENBDATA Hr—

&
—°

CIBS DONE (0) H

CLRO
o

GND

CIBP DNE INTR ENAB H

‘

VECTOR 300 (TX RDY)

PEND

SEND RECEIVE INTERRUPT ~

'fLXT
|

Cn CLR O
@)

RQSTB H[—
{5_5]

S7L.VECTOR H

SET

DNE IE
ENBCLK H

)

08}

——= BIRQ L

T71ENBST H

BUS Q

AX INT

‘vee

VECRQSTB H

\
“\

SEND TRANSMIT INTERRUPT “/

VECTOR 304, (RX DNE)

— INITO L
!

TK-0223

Figure 3-25

LSI-11 Interrupt Logic

3-28

INITO L g4

BINITL 5 Dcoo3 14
BIAKO L 06
13

—

ENAST

Table 3-3

Interrupt Related Register Bit Functions

Ready and Done
Bits

Interrupt
Enable
Bits

RXCS
(ID bus 04¢)

RX DNE-R/O
(bit 7)

RXIE R/W | If both bits are set, in(bit 6)
terrupt the VAX-11.

Comments

same flop-flop |
RX DONE
(Q bus 1630145/1730143)

RX DNE-R/W
(bit 7)

If this bit is reset and
MCS <05> is set, interrupt the LSI-11.

TX CS
(ID bus 061¢)

TX RDY-R/O
(bit 7)

TXIE R/W | If both bits are set, in(bit 6)
terrupt the VAX-11.

same flip-flop

TX RDY
TX READY-R/W
(Q bus 163016g/173016,¢) | (bit 7)

MCS
(Q bus 1630343/173034g)

If this bit is reset and

MCS <06> is set, interrupt the LSI-11.

RDY IE-R/W
(bit 6)

DNE IE-R/W| Enable or disable in(bit 5)
terrupts to the LSI-11.
These bits are implemented on the DC003
chip.

3.6 TYPICAL CIB TRANSFER OPERATIONS
.
When the VAX-11/780 software and the LSI-11 transfer data and control signals via the Console
Interface Board, the transfer operations occur in predictable and logical sequences. For example, when
the VAX- 11/780 CPU is running macrocode and the console terminal operator types ‘“‘set terminal
program,’ " switching from the console I/O mode to the program 1/0 mode, the following sequence

will occur.

The LSI-11 sets the READY bit (7) in the CIB TX READY register, informing the VAX11/780 that the console terminal is ready to accept a character (Figure 3-26).
The VAX-11/780 writes to the FM ID register, clearing the READY bit in the TX READY
register, interrupting the LSI-11 (Figure 3-27).

The LSI-11 and CIB hold an interrupt dialogue on the Q bus (Figure 3-28).
An LSI-11 interrupt routine reads the character in the FM ID register and transfers the
character to the console terminal (Figure 3-29).

The console terminal completes printing the character and interrupts the LSI-11 (not

shown).

The LSI-11 sets READY in the TX READY register, thus completing one transfer (not
- shown).

3-29

ciB

LSI-11
ADDRESS LOCATION 163016,
ON QBUS
e ASSERT BDAL <15:00> L

WITH ADDRESS 163016
e ASSERT BBS7 L

e ASSERT BWTBT L

(WRITE CYCLE)

« ASSERT BSYNC L

OUTPUT DATA
. :g’rf"’(fig%%ff_s FROM

DECODE ADDRESS

e DCOO5 MATCH H OUTPUT « 1

e 1Lfiff;s*’ IS ASSERTED ON BUS QDATA
P ~” « ADDRESS BITS <12:01> ARE LATCHED
e CIBJ SEL MCS L ENABLED

« NEGATE BBS7 L
o LEAVE BWTBT ASSERTED,
N

INDICATING DATOB

ACCEPT DATA

e, ASSERT BDAL <7> L TRUE \\\
N

* ASSERT BDOUT L
TERMINATE OUTPUT TRANSFER

e REMOVE DATA FROM
BDAL <15:00> L

e ASSERT BRPLY L

y
~
~

~ __ OPERATION COMPLETED

TERMINATE BUS CYCLE

e NEGATE BYSNC L

\/ e LATCH READY HIGH ON DC003

_- -7

e NEGATE BDOUT L

e ENABLE CIBU CLK RDY L

_—

* NEGATE BRPLY L

-t

e NEGATE BWTBT L
TK-0224

Figure 3-26

LSI-11 Sets TX READY, DATOB Transfer on Q Bus

3-30

ciB

VAX-11 CPU
WRITE TO LOCATION 07,4

ON ID BUS

* ASSERT ASCIl CHARACTER

ON ID BUS <7:0>
* ASSERT Os ON ID BUS <11:08>

(DESIGNATING OUTPUT TO TERMINAL)
* ASSERT 07,6 ON ID ADDR <5:0> H
e ASSERT ID WRITE L

DECODE ADDRESS AND ACCEPT DATA

« ID BUS ADDRESS DECODER LOGIC ASSERTS

.=~

CIBM FMID DECODE L AND
CIBM 1D WRITE L DRIVING

CIBU CLK FM ID H LOW AT CPT100
AND THEN HIGH AT CPT150

CIBM FM ID DECODE L

CPT100

{
|

CPT150
*

DATA IS LATCHED IN FM ID REGISTER

e CIBM FMID DECODE L AND
CIBM ID WRITE L

CLEAR TX RDY FLIP-FLOP

(CIBS RDY (1) H « 0)
INITIATING AN INTERRUPT TO

THE LSI-11

\\
N

TERMINATE TRANSFER

NEGATE ID WRITE L
*

NEGATE ADDRESS ON ID ADDR <5:0> H

NEGATE DATA

TK-0225

Figure 3-27 VAX-11/780 Software Sends a Character to the FM ID Register
for Transmission to the Console Terminal, Write Transfer on the ID Bus

3-31

LSI-11

cie
INITIATE REQUEST
* TXRDY « 0O

STROBE INTERRUPTS

e ASSERT BDIN L

RECEIVE BDIN L

GRANT REQUEST
e

e CLOCK TRANSMIT INTERRUPT
FLIP-FLOP ON DCO003

PAUSE AND

e ASSERT BIAKO L

DCOO3 ASSERTS BIRQ L

RECEIVE BIAKI L
RECEIVE BIAKI L AND
RECEIVE VECTOR AND

INHIBIT BIAKO L

TERMINATE REQUEST
*

DCOO3 ASSERTS CIBP VECTOR H

LATCH VECTOR

NEGATE BDIN L

NEGATE BIAKO L

CAUSING DCOO5 TO ASSERT BDAL <07, 06> L
(VECTOR 300,)
ASSERT BRPLY L

NEGATE BIRQ L

PROCESS THE INTERRUPT

COMPLETE VECTOR TRANSFER

e SAVE CURRENT PROGRAM PC
AND PS ON STACK

”

* LOAD NEW PC AND PS FROM

”

DCOO3 NEGATES CIBP VECTOR H

DCOO5 NEGATES VECTOR ON Q BUS

VECTOR ADDRESSED LOCATION
*

EXECUTE INTERRUPT
SERVICE ROUTINE FOR
READ TO FM IDLO REGISTER

Figure 3-28

TK-0226

Interrupt Dialogue on the Q Bus

3-32

cis

LSI-11
ADDRESS FM IDLO REGISTER
e ASSERT 1630245 ON
BDAL <15:00> L

DECODE ADDRESS

e ASERT BBS7 L

» ASSERT BSYNC L

e DCOO5 MATCH H OUTPUT « 1
S

_ -

REQUEST DATA

‘ ';f)i’:‘_Tifs‘?oD:isLs ON P

« ASSERT BDIN L

ON THE QMUX

OUTPUT DATA
N

e DCOO4 ASSERTS CIBJ INWD L

TERMINATE INPUT TRANSFER

e NEGATE BDIN L

OF THE FM IDLO REGISTER

LATCHED

SELECTING THE OUTPUT

* ACCEPT DATA

ADDRESS BITS <12:01> ARE

— CIBR QMUX SEL <2:0> H

¢ NEGATE BBS7 L

BUS QDATA LINES

« CIBJ LADRS <03:01> H

* 163024, IS ASSERTED ON

ENABLING CIBR QMUX STROBE L,
AFTER CIBR ONE-SHOT DELAY,

ENABLING CONTENTS OF FM IDLO

e CIBJ TRPLY L A CPT150, CPT50

— CIBT XMT RPLY H

’

CIBR QBUS XMT H

ENABLING DATA ONTO BDAL <15:00> L

o ASSERT BRPLY L

\ o OPERATION COMPLETED
o NEGATE BRPLY L

TERMINATE BUS CYCLE

- -

« REMOVE DATA FROM BDAL <15:00> L

e NEGATE BSYNC L
TK-0227

Figure 3-29

LSI-11 Interrupt Subroutine Reads the FM IDLO Register,
DATI Transfer on Q Bus

3-33

Some time later, another sequence might occur, as follows:
1.

LSI-11 writes to the TO IDLO register (Figure 3-30).

LSI-11 sets DONE (not shown).

VAX-11/780 CPU reads the TO ID register (Figure 3-31).

The flowcharts which follow trace the operations basic to each transfer.

LSI-11

ciB

ADDRESS TO IDLO REGISTER

ON Q BUS
e ASSERT 1630205 ON

BDAL <15:00> L
e ASSERT BBS7 L

e ASSERT BWTBT L

e ASSERT BSYNC L

DECODE ADDRESS

OUTPUT DATA

REMOVE ADDRESS FROM

DCOO5 MATCH OUTPUT « 1

1630205 IS ASSERTED ON

BUS QDATA LINES

BDAL <15:00> L

e ADDRESS BITS <12:01>

NEGATE BBS7 L

ARE LATCHED

NEGATE BWTBT L

e ASSERT CIBJ SELTO IDLO L

ASSERT DATA ON BDAL <15:00> L \\
ASSERT BDOUT L

ACCEPT DATA
e

TERMINATE OUTPUT TRANSFER

« REMOVE DATA FROM
BDAL <15:00> L

ENABLE CIBU CLK TO IDLO LB L
CIBU CLK TO IDLOHB L

-t
—

LATCH DATA IN TO IDLO REGISTER

e ASSERT BRPLY L

e NEGATE BDOUT L

OPERATION COMPLETED
o

TERMINATE BUS CYCLE

NEGATE BRPLY L

e NEGATE BSYNC L
TK-0228

Figure 3-30 LSI-11 Writes a Character to the TO IDLO Register
for Transmission to the VAX-11/780 Software, DATO Transfer on the Q Bus

3-34

THE LSI-11 WRITES A 1 TO

THE DONE BIT ON THE CIB

(RX DONE <07>, 1630144)
ENABLING CIBS CNSL RCV INTR H,
WHICH INTERRUPTS THE VAX-11 CPU.
SOME TIME LATER THE VAX-11 CPU
INVOKES AN INTERRUPT SUBROUTINE

CiB

VAX-11 CPU
INITIATE READ TRANSFER

DECODE ADDRESS

TO ID BUS LOCATION 0516

* ENABLE CIBM ID MUX SEL L

(C'BM SYSID DECODE L IS FALSE)
SELECT OUTPUTS FROM TO ID

¢ ENABLE TO ID DECODE L,
ENABLING CIBM ENDAT ALL L

AND CIBM ENDAT (7.6) L.
ENABLING BUS TRANSCEIVERS

AND ASSERTING CONTENTS OF

TO ID REGISTER ON ID BUS
AT CPT 100

(|D WRITE L IS FALSE)

,
/

7.6 MUX

/ * ASSERT 05,5 ON ID ADDRS <5:0> H

4
\

\y ACCEPT DATA

% REMOVE ADDRESS FROM

ID ADDRS <5:0> H,

TERMINATING BUS CYCLE

e DISABLE BUS TRANSCEIVERS
AT CPT O, REMOVING
DATA
TK-0229

Figure 3-31

VAX-11/780 Interrupt Subroutine Reads the TO ID Register,
Read Transfer on the ID Bus

3-35

APPENDIX A
Q BUS TECHNICAL DESCRIPTION

A.1 GENERAL
The Q bus is the I/O and memory bus for the LSI-11 and the VAX-11/780 console subsystem. The
Q bus multiplexes address and data signals on the 16 BDAL lines. In addition individual control
signals are used to sequence I/0O transfers and interrupt transfers. Table A-1 lists the important Q bus
signal lines.

Table A-1

Q Bus Signals

I/O Transfer Control Signals

Name

Description

BSYNC L

Synchronize - The bus master (LSI-11 processor) asserts BSYNC L to indicate that it has placed an address on BDAL <15:00> L. The transfer is in
progress until BSYNC L is negated.

BDIN L

Data Input - The LSI-11 asserts BDIN L for two types of operations:

BDOUT L

When it is asserted during BSYNC L time, BDIN L
specifies an input transfer with respect to the processor. It requires BRPLY L as a response. The processor asserts BDIN L when it is ready to accept data
from the slave device.

When the processor asserts BDIN L without BSYNC
L, it is requesting an interrupt vector from an interrupting device.

Data Output - When the LSI-11 processor asserts BDOUT L, valid data is
on the bus for an output transfer from the processor to an I1/0 slave device.
The slave device deskews BDOUT L (pauses) before latching the data. The
slave device responding to the BDOUT L signal must assert BRPLY L to
complete the transfer.

Table A-1

Q Bus Signals (Cont)

I/0 Transfer Control Signals
Name

Description

BWTBT L

Write/Byte - The LSI-11 processor uses BWTBT L to control bus cycles in
two ways:

BRPLY L

The processor asserts BWTBT L on the leading edge

The processor asserts BWTBT L together with
BDOUT L, on a DATOB cycle, for byte addressing.

of BSYNC L to indicate that an output sequence
(DATO or DATOB) is to follow.

Reply - A slave device asserts BRPLY L in response to BDIN L and
BDOUT L on data transfers and in response to BIAKO L during interrupt
transfers. BRPLY indicates that the slave has asserted input data on the bus,
accepted output data from the bus, or asserted an interrupt vector on the
bus.
Interrupt Control Signals

BIRQL

Interrupt Request — A device asserts this signal when its interrupt enable and
interrupt request flip-flops are set. BIRQ L informs the processor that a
device has data to send to the processor (input) or that the device is ready to
accept output data from the processor. If the processor’s PS word bit 7 is 0,
the processor responds by acknowledging the request, asserting BDIN L and
BIAKO L.

BIAKO L
and BIAKI L

Interrupt Acknowledge Output and Interrupt Acknowledge Input - The processor asserts this signal in response to an interrupt request (BIRQ L). The
processor asserts BIAKO L which is routed via the Q bus to the BIAKI L pin

of the first device on the bus. If this device is requesting an interrupt (asserting BIRQ L), it will block the passing of BIAKO L to the next device and
then place the interrupt vector on the bus. At the same time the device will
negate BIRQ L and assert BRPLY L. If the device is not asserting BIRQ L, it
passes BIAKI L to the next device via its own BIAKO L pin and the BIAKI
L pin of the lower priority device.

Address and Data Signals

BDAL <15:00> L

These 16 lines form the data/address path. Address information is first
placed on the bus by the bus master (processor). The processor then either
receives input data from or transmits output data to the addressed slave
device or memory location over the same 16 bus lines.

BBS7 L

Bank 7 Select - The bus master asserts BBS7 L when an address in the upper
4K bank (address in the 28K-32K range) is placed on the bus. BSYNC L is
then asserted, and BBS7 L remains active for the duration of the addressing
portion of the bus cycle.

A-2

Table A-1

Q Bus Signals (Cont)

Initialization, Power Fail Signals
Name

Description

BPOK H

Power OK - The power supply asserts this signal when primary power is
normal. If BPOK H is negated during processor operation, the processor
initiates a power fail trap sequence.

BDCOK H

DC Power OK - The power supply asserts this signal when there is sufficient
dc voltage available to sustain reliable system operation.

BINIT L

Initialize - The processor asserts BINIT L to initialize or clear all devices
connected to the Q bus. The signal is generated in response to a power up
condition (the negated condition of BDCOK H).
Halt and Refresh Signals

BHALT L

Processor Halt - When BHALT L is asserted, the processor responds by
halting normal program execution. External interrupts are ignored, but
memory refresh interrupts are enabled if W4 on the processor module is
removed. When the processor is in the halt state, it executes the ODT microcode, invoking console device (terminal) operation.

BREF L

Memory Refresh — This signal can be asserted by a processor microcodegenerated refresh interrupt sequence (when enabled) or by an external device.
BREF L forces all dynamic MOS memory units to be activated for each
BSYNC L/BDIN L bus transaction.

A.2 TRANSFER OPERATIONS ON THE Q BUS
A master-slave relationship defines communication between the processor and the other devices on the
Q bus. Each control signal issued by a master device must be acknowledged by a slave device in order
to complete a transfer.
Every processor instruction requires one or more I/O operations. The first operation required is a data
input transfer (DATI), which fetches an instruction from the location addressed by the program
counter (PC or R7). This operation is called a DATI bus cycle. If no additional operands are referenced in memory or in an I/O device, no additional bus cycles are required for instruction execution.
However, if memory or a device is referenced, additional DATI, data input/output (DATIO or DATIOB), or data output transfer (DATO or DATOB) bus cycles are required. In addition, the processor
can service interrupt requests only prior to an instruction fetch (DATI bus cycle) and if the processor’s
priority is zero. (PS word bit 7 is 0.)

The following paragraphs describe the types of bus cycles. Note that the sequences for I/O operations
between processor and memory or between processor and I/O device are identical. DATO (or DATOB) cycles are equivalent to write operations, and DATI cycles are equivalent to read operations. In
addition, DATIO cycles include an input transfer followed by an output transfer. The DATIO cycle
provides an efficient means of executing an equivalent read-modify-write operation by making it unnecessary to assert an address a second time.

A.2.1

Input Operations

The sequence for a DATI operation is shown in Figure A-1. DATI cycles are asynchronous and
require a response from the addressed device or memory. The addressed memory or device responds to
the input request (BDIN L) by asserting BRPLY L. If BRPLY is not asserted within 10 us (max) after
BDIN L is asserted, the processor terminates the cycle and traps through location 4.

BUS MASTER (PROCESSOR)

SLAVE (CONTROLLER)

ADDRESS RXV11

o ASSERT BDALO-15 L WITH
ADDRESS AND

e ASSERT BBS7 IF THE ADDRESS
IS IN THE 28 - 32K RANGE
e ASSERT BSYNC L

—

DECODE ADDRESS

e DECODE BASE ADDRESS
e

___—
/

—

STORE BDAL

1,2 FOR REGISTER

SELECTION

REQUEST DATA

REMOVE THE ADDRESS FROM
BDALO-15 LAND NEGATE BBS7
L

e ASSERT BDIN L

——— —_
—
—
\

INPUT DATA

e PLACE DATA ON BDALO-15 L
-o ASSERT BRPLY L

TERMINATE INPUT TRANSFER

e ACCEPT DATA AND RESPOND
BY NEGATING BDIN L

—
\

TERMINATE BUS CYCLE
e NEGATE BSYNC L

OPERATION COMPLETED
e TERMINATE BRPLY L

11-3138

Figure A-1

DATI Bus Cycle

Note that BWTBT L is not asserted during the address time, indicating that an input data transferis to
he ayecuted
Ve

wiswwesvwewse

A DATIO cycle is equivalent to a read-modify-write operation. An addressing operation and an input
word transfer are first executed in a manner similar to the DATI cycle; however, BSYNC L remains in
the active state after completing the input data transfer. This causes the addressed device or memory to
remain selected, and an output data transfer follows without any further addressing. A fter completing
the output transfer, the master (processor) terminates BYSNC L, completing the DATIO cycle. The
actual sequence required for a DATIO cycle is shown in Figure A-2. Note that the output data transfer
portion of the bus cycle can be a byte transfer; hence, this cycle is shown as DATIOB.

A.2.2

Output Operations

The sequence required for a DATO or the equivalent output byte (DATOB) bus cycle is shown in
Figure A-3.

As on the input operatlons failure to receive BRPLY L within 10 us after assertmg BDOUT L is an
error and resultsin a processor time-out trap through location 4.
Note that BWTBT L is asserted during the addressing portion of the cycle to indicate that an output
data transfer is to follow. If a DATOB is to be executed, BWTBT L remains active for the duration of
the bus cycle; however, if a DATO (word transfer)is to be executed, BWTBT L is negated durmg the
remainder of the cycle.

A.2.3

Interrupts

Interrupts are requests made by peripheral devices which cause the processor to temporarily suspend
its present (background) program execution to service the requesting device. Each device which is
capable of requesting an interrupt has a service routine which is automatically entered when the processor acknowledges the interrupt request. After completing the service routine execution, program
control is returned to the interrupted program.

A device can interrupt the processor only when interrupts are enabled. The processor’s priority in the
PS word is 4 when external interrupts are disabled and 0 when external interrupts are enabled. Device
puvlu_y is hxshvot for devices e'ectn""""
closest to the processor alnng the bus.

Any device that can interrupt the processor can also interrupt the service routine execution of a lower
priority'devicc if the processor’s priority is 0 during that execution; hence, interrupt nesting to any level

is possible with this interrupt structure. Each device normally contains a control status register (CSR),
which includes an interrupt enable bit. A program must set this bit before an interrupt request can
actually be made by a device.

An interrupt vector associated with each device is hard-wired into the device’s interface/control logic.
This vector is an address pointer that allows automatic entry into the service routine without device
polling.

When an interrupt request is issued via the external event signal line, the processor automatically
services the request via location 100g; it does not input a vector address as done for other external
interrupt devices.

BUS MASTER

SLAVE

(PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE/MEMORY
®

ASSERT BDALO-15L WITH

ADDRESS
®
®

ASSERT BBS7 AND IF THE

ADDRESS IS IN THE 28 - 32K RANGE
ASSERT BSYNC L

= B~ DECODE ADDRESS
e

STORE “DEVICE SELECTED"

OPERATION

" — — —

REQUEST DATA
e

REMOVE THE ADDRESS FROM

BDALO-151L
®

ASSERT BDIN L

—_——
INPUT DATA
e

PLACEDATAONBDALO-15L

ASSERT BRPLY L

TERMINATE INPUT TRANSFER
®

ACCEPT DATA AND RESPOND BY

TERMINATING BDIN L

COMPLETE INPUT TRANSFER

OUTPUT DATA

PLACE OUTPUT DATAONBDALO-15L

(ASSERTBWTBT L IF ANOUTPUT

ASSERT BDOUTL

REMOVE DATA

TERMINATE BRPLY L

—

BYTE TRANSFER)
\\\

TAKE DATA

‘ -

RECEIVE DATA FROM BDAL LINES

ASSERT BRPLY L

- /’

TERMINATE OUTPUT TRANSFER
e

TERMINATE BDOUT L, AND REMOVE

DATA FROM BDAL LINES
/

———

OPERATION COMPLETED
e

—

—_—

- - -

TERMINATE BRPLY L

TERMINATE BUS CYCLE
e

NEGATEBSYNCL

(AND BWTBT L IF IN
A DATIOB BUS CYCLE)

Figure A-2

11-3139

DATIO or DATIOB Bus Cycle

A-6

BUS MASTER (PROCESSOR)

‘

SLAVE (CONTROLLER)

ADDRESS RXVii

e ASSERT BDALO-15 L WITH
ADDRESS

e ASSERT BBS7 L (IF ADDRESS IS
IN THE 28 -32K RANGE)
e ASSERT BWTBT L (WRITE
CYCLE)
e ASSERT B SYNC L

T~ -

el -

OUTPUT DATA
e

—

DECODE ADDRESS

DECODE BASE ADDRESS

REMOVE THE ADDRESS FROM
BDALO-15 LAND NEGATE BBS?7
L AND BWTBT L

PLACE DATA ON BDALO-15 L

e A ASSERT BDOUT L

—
\

e
TAKE DATA
e

RECEIVE DATA FROM BDAL
LINES

— ® ASSERT BRPLY L
/

“TrfASIALATTE ALITTMM) T e
TERIVIINAITE

UUIFVI

A RSN

I RANOSIrER

REMOVE DATA FROM

BDALO-15 L AND NEGATE

BDOUT L

—
\
\

OPERATION COMPLETED

TERMINATE BUS CYCLE
e

" —_

/ -

e TERMINATE BRPLY L

NEGATE BSYNC L

11-3140

Figure A-3

DATO or DATOB Bus Cycle

A-7

The interface control and data signal sequence required for interrupts is shown in Figure A-4. A device
requests interrupt service by asserting BIRQ L. The processor can acknowledge interrupt requests only
between instruction executions. It does this by generating an active (low) BDIN L signal, enabling the
device’s vector response. The processor then asserts the BIAKO L signal. The first device on the bus
receives this daisy-chained signal at its BIAKI L input. If it is not requesting service, it passes the signal
via its BIAKO L output to the next device, and so on, until the requesting device receives the signal.
The device that does not pass the BIAKO L signal responds by asserting BRPLY L (low) and placing
its interrupt vector on data/address bus lines BDALO-15 L. Automatic entry to the service routine is
then executed by the processor as previously described.

A.2.4

Bus Initialization

Devices along the I/O bus are initialized whenever the system dc voltages are cycled on or off, or when
a RESET instruction is executed. Initialization during the power-on/power-off sequence is described
in Paragraph A.2.5. When the RESET instruction is executed, the processor responds by asserting
BINIT L for approximately 10 us. Devices along the bus respond to the BINIT L signal, as appropriate, by clearing registers and presetting or clearing flip-flops.

A.2.S

Power-Up/Power-Down Sequence

Power status signals BPOK H and BDCOK H must be asserted or negated in a particular sequence as
dc operating power is applied or removed. Initially, BDCOK H and BPOK H are passive (low). As dc
voltages rise to operating levels, BINIT L is asserted by the processor module. Approximately 3 ms
(min) after +5 V and +12 V power are normal, an external signal source, or the H780 power supply in
PDP-11/03 systems, produces an active BDCOK H signal; the processor responds by negating BINIT
L, and waits for BPOK H. The BPOK H signal, produced by an external signal source or the H780
power supply, goes true (high) 70 ms (min) after BDCOK H goes high. The processor responds by
executing the user-selected power-up routine; if BHALT L is asserted, the console microcode is executed.

During a power-down sequence, the external signal source first negates BPOK H, causing the processor to execute the power-fail trap (PC at 024g, PS at 026g).

Approximately 3 ms (max) later, the processor initializes the bus by asserting BINIT L in response to
the external signal negation of BDCOK H.

A.2.6

Memory Refresh Operation

A complete refresh operation requires 64 BSYNC/BDIN transactions which must be completed every
2 ms. The processor (or other device controlling the refresh operation) first asserts BREF L for each
BSYNC/BDIN transaction during the addressing portion of each refresh operation. BREF L causes
all dynamic MOS memory devices to be simultaneously enabled and addressed, overriding local bank
selection circuits. Refresh is then accomplished by executing 64 BSYNC/BDIN transactions, in a
manner similar to the DATI bus cycle, incrementing the “row’ address (bits 1-6) once for each transaction. Address bit 0 is not significant in the refresh operation. When refresh is controlled by processor
microcode, the operation takes approximately 130 us.

INITIATE REQUEST

—* ASSERT BIRQ L
/ /

STROBE INTERRUPTS

o ASSERT BDIN L

—

\
\
\

|
'

RECEIVE BDIN L
o STORE “INTERRUPT SELECTED"

‘

IN DEVICE

GRANT REQUEST
«

PAUSE AND ASSERT BIAKO L

RECEIVE BIAK L
e«

RECEIVE BIAK | L AND INHIBIT

BIAKO L
¢

PLACE VECTOR ON BDAL 0-15 L

o ASSERT BRPLY L
__« TERMINATE BIRQ L
/

RECEIVE VECTOR & TERMINATE
REQUEST

INPUT VECTOR ADDRESS

o TERMINATE BDIN L AND
BIAKO

L
——

—

COMPLETE VECTOR TRANSFER
e
/

REMOVE VECTOR
TERMINATE BRPLY L

PROCESS THE INTERRUPT
e SAVE INTERRUPTED PROGRAM
PC AND PS ON STACK
e

LOAD NEW PC AND PS FROM

VECTOR ADDRESSED LOCATION
e

EXECUTE INTERRUPT SERVICE
11-3142

ROUTINE FOR THE DEVICE

Figure A-4

Interrupt Request/Acknowledge Sequence

A-9

VAX-11/780 CONSOLE INTERFACE BOARD

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