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EK-KA820-TM-003

April 1987

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Document:	KA820/KA825 Processor Technical Manual
Order Number:	EK-KA820-TM
Revision:	003
Pages:	266
Original Filename:

OCR Text

EK-KA820-TM-003

KA820/KA825
|

Processor

Technical Manual

EK-KA820-TM-003

KA820/KA825 Processor

Technical Manual

April 1987
This manual is written for people who install and replace the KA825 module

(

in the field and for people who incorporate KA825 modules into their own
products or systems. The manual gives detailed information about mainte-

nance functions. It also tells how to customize the processor and write system

software, including exception handlers 1nterrupt handlers, and device driv-

ers for dedicated devices.

digital equipment corporation ®* maynard, massachusetts

First Edition, December 1985
Second Edition, May 1986
Third Edition, April 1987

Information in this manual is subject to change without notice and should not
be construed as a commitment by Digital Equipment Corporation. Digital
Equipment Corporation assumes no responsibility for any errors that may
appear in this manual.

Digital Equipment Corporation makes no representation that the interconnection of its products in the manner described herein will not infringe on
existing or future patent rights, nor do the descriptions contained herein imply the granting of license to make, use, or sell equipment constructed in accordance with this description.

Printéd in U.S.A.

The following are trademarks of Digital Equipment Corporation:

DEC

|
DECnet
DECsystem-10
DECSYSTEM-20
- DECtape

VAX

Bililolijtlal
DECUS
DECwriter
DIBOL
ULTRIX
UNIBUS

M474000

|
|

VAXBI
VAXELN
VMS
VT

Contents

Preface

- Chapter 1

Introduction to the KA820 Module
KA820 Functional Sections

1.1

CPUSection .......... ...
VAXBI Interface Section. .. ...........ccuu..... .

1.1.3

Port Controller and PCI Bus Devices Section.........

1.2

Customer Options. . ...

1.3

VAXBIL OVervVIiewW . .ot vt ittt

... it
et

e e e e e e e

e e e

1.3.1

VAXBI Addressing .............00

1.3.2

VAXBI Timing and Arbitration .. ... ...............

KA820 Module Layout. . ... vvvve et

1.4

Chapter 2

1.1.1
1.1.2

1.5

Power Requirements

1.6

Environmental Requirements

KA820 Module Detailed Description
CPU Section . ..ot
i e e
e et

2.1

2.1.1

IEChipFunctions ...............
... ... .. ... ...

2.1.2

M Chip, BTB, and Cache Functions. ................
2.1.2.1

213
2.14

BTB (Backup Translation Buffer)...........

2.1.2.2

Cache ....... e
e

2.1.2.3

Internal Processor Registers...............

2124

Serial-LineUnits........................ |

F ChipFunctions. ............
... ...,
Communication between the Processor Chip Set
andthe VAXBIBus......................... .

2.1.5
2.2

Control-Store Operation..........................

VAXBIInterface........ ..o,
221

VAXBIAddressSpace...............cciuiiin....

2.2.2

KA820 Registers Accessible to Other VAXBI Nodes

2.2.3

VAXBITransactions . ............cciiiinnunn. .

2.2.3.1

KAB820-Initiated Transactions. . ............

2.2.3.2

KA820 Slave Responses. ............... .

2.2.3.3

Device Interrupt Sequence ................

1ii

2.3

Port Controller and PCI Devices. . . . ..o i i ittt ittt i it e
2.3.1
2.3.2
2.3.3

2.34

Chapter 3

ene s 2-19

PCIBus Addressing . ........cciiiiiineiiiininnnnen 2-20
EEPROM Functions . . ......cciiiiiiinnnnnn . 2-21
Watch Chip Interface ..............
...
... 2-21

RCX50 Controller Interface . . . ..o oo oot 2-21

Sequences and Options on Power-Up
3.1
3.2

3.3

Power-Up Sequence and Related Signals and Jumpers............... 3-2
Self et . ot
e e
e e
e e e 3-4
Initialization........................e
e e
e 3-8

3.3.1
3.3.2
3.3.3
3.4

it 3-9
.....
... ..o
Power-Up Initialization ........
i 3-9
o
.. ... .....
Processor Initialization. .......
i 3-11
o
... .. .....
System Initialization .......

Restartand Bootstrap ............cciiiiiiiiiiiie.....3-14

3.4.1
3.4.2

i, 3-14
... .. o ..
Restart Function (Warm Start). . .........
Bootstrap Function (Cold Start)..................e 3-15
3.4.2.1

EEPROM and Boot RAM Bootstrap

Considerations . . .. o.vvent vt e, 3-16
3.4.2.2 Software Responsibilitiesin the Bootstrap ........ 3-17
3.4.2.3 Loading Secondary Control-Store Patches......... 3-17

3.5

Console Functions
4.1

4.2

ConS0le States . ot t
Console Entry. ...
4.2.1

4.3

4.5
4.6

vttt

e 4-1
e
e 4-2
e

e e et et et 4-3

e L..4-4
e e
tt
ittt
Console Commands .. ...civ it
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
4.3.14
4.3.15
4.3.16
4.3.17
4.3.18

4.4

Halt Codes. ..o v

e e e
e
i

Change Console Baud Rate Command ((BREAK)) .......... 4-6
e 4-17
e t
i
Boot Command (B) . ... itt
Continue Command (C). . ... . ittt i e e 4-9
Deposit and Examine Commands(Dand E) ................ 4-9
... ... e 4-13
... ... ...
HaltCommand ) .......
Initialize Command (I) . . ... .. it 4-13
4-13
Next Command (N) . ..... FE
4-13
Start Command (S) .......... FR
et i e 4-14
e
Test Command (1) . ... .o it
Test with Menu Command (T/M) . ....... ... 4-15
Binary Load and Unload Command (X). . ................ 4-15
VAXBIForward Command (Z) ... .....cuiiiiiinnnn 4-16
... ... ... ...4-18
Console Comment Command (). ..........
Enter Console Mode Command ((CTRL/P)) ............... 4-18
Forward Next Character Command ((ESC)) .......e e 4-18
Stop Console Output Command ((CTRL/S))............... 4-18
Restart Console Output Command ((CTRL/QY)............ 4-18
Abort Command Line Command ({(CTRL/U)) ............. 4-19

it et e et et 4-19
Console Error Codes. . ... oottt
Loading Control-Store Patches from the Console. . ................. 4-20
Logical Console Operation. . .........c.ouuuvrininiinenenennennnns 4-21

Chapter 4

Sample Multiprocessor Configuration Start Sequen‘ce' .............. 3-21

Chapter 5

Handling Exceptions and Interrupts
5.1

System Control Block. .. ...

5.2

Machine-Check Exceptions . ...
5.2.1

... . e 5-3
... 5-5

Machine-Check Stack .. .........
... ...
.. 5-7

52.1.1

ByteCount,(SP)....... ..., 5-7

5.2.1.2

Parameter 1, (SP) + 8, MTEMPB Register ......... 5-8

5.2.1.3

Virtual Address Register,

5.2.1.4

Virtual Address Prime Register,

SP) + C, MTEMP13 Register. .. ................. 5-8

(SP) + 10, MTEMPPSL.TEMP Register. ........... 5-8
5.2.1.5

Memory Address Register, (SP) + 14,

MTEMPO Register.

5.2.1.6

.. ........
. ...
... 5-8

Status Word, (SP) + 18, MTEMPC Register......... 5-8

5.2.1.7

Program Counter at Failure, (SP)+ 1C........... 5-11

5.2.1.8

MicroPC at Failure, (SP) + 20 thex) . . ............ 5-11

5.2.1.9

Current Program Counter, (SP) + 24 (hex)......... 5-11

5.2.1.10 Current Processor Status Longword,
SP)+28thex) ......... 5-11

Chapter 6

9.3

CPU Double-Error Halt Considerations. ......................... 5-11

5.4

Power-Up and Console Mode Errors . .........
... . ... .. ... 5-12

Dedicated I/O and Memory Devices
6.1

Serial-Line Units ........ e

6.1.1

e e 6-2

Bit (7) DON (Done, Read Only) . ................. 6-4

6.1.1.3

Bit (6) Interrupt Enable (Read/Write)............. 6-5

Receive Data Buffer Registers (Read Only)................. 6-5
Bit (15) ERR (Error on Received Character,
ReadOnly) ......

...

6-5

6.1.2.2

Bit (14) BRK (Break,ReadOnly) ................ 6-5

6.1.2.3

Bits (7:0) DATA (Received Data, Read Only) ....... 6-6

Transmit Control and'Status Registers (Read/Write)......... 6-6
6.1.3.1

6.1.4

Bit (12) LP (Loopback Enable, Read/Write) .. ...... 6-4

6.1.1.2

6.1.2.1

6.1.3

Receive Control and Status Registers (Read/Write) . ......... 6-3
6.1.1.1

6.1.2

Bit (13) LP (Loopback, Write Only). .............. 6-"7

6.1.3.2

Bit (12) BRK (Break, Write Only)................ 6-"7

6.1.3.3

Bits (11:9) Baud Rate (WriteOnly)............... 6-7

6.1.3.4

Bit (8) BRE (Baud Rate Enable, Write Only).

6.1.3.5

Bit (7) RDY (Ready, Read Only).................. 6-8

... ... 6-7

6.1.3.6

Bit (6) IE (Interrupt Enable, Read/Write). . ........ 6-8

Transmit Data Buffer Registers (Write Only). . ... e 6-8
6.1.4.1

Bits (11:8) of TXDB (ID Field, Write Only)......... 6-9

6.1.4.2

Bits (7:0) of TXDB,

6.1.4.3

(Command or Transmit Data, Write Only). . ........ 6-9
Bits (7:0) of TXDBI1, 2, and 3

(Transmit Data, Write Only). .. .................. 6-9

6.2

Using the EEPROM. . . ..ottt

6.3

Boot RAM ... e
e 6-11

6.4

Usingthe Watch Chip ........ ...

6.5

e e D .6-9
i

i 6-11

6.4.1

Watch Chip CSR A, Address200B8014 .................. 6-14

6.4.2

Watch Chip CSR B, Address 200B 8016 ................. .6-15

6.4.3

Watch Chip CSR C, Address 200B 8018 ............. R 6-15

6.4.4

Watch Chip CSR D, Address 200B801A .................. 6-15

6.4.5

Bootstrap Software Date and Time Responsibilities ........ 6-16

- 6.4.6

Compatibility with VMSand ULTRIX ................... 6-16

Controlling the RCX50 Controller ...........
... ... .
... 6—-16
6.5.1

Data Transfer Examples. . ... e

. 6.5.2

e 6-18

RX5CS0 Command Function ................... 6-19

6.5.2.2

RX5CS0 Data Transfer Status and
Maintenance Status. . . .. PO 6—22

6.5.3

RX5CS1 Command Function, Track Reglster ...... 6—-23

6.5.3.2

RX5CS1 Data Transfer and

Maintenance Status Format, Error Register....... 6—-24
6.5.4

RX5CS2 Data Transfer Format, Sector Register. .. .6-25

6.5.4.2

RX5CS2 Data Transfer and
Maintenance Status Format, Current Track

RX5CS3, Address 200B000A . .................. 6—-26

6.5.5.1

RXbHCS3 Data Transfer Status Format,

6.5.5.2

RX5CS3 Maintenance Status Format,

Current Sector Register. . ............
... ....... 6—-26
Current Status Register ....................... 6—-26

6.5.6

6.5.6.1
|

RX5CS4 Data Transfer Status,
Incorrect Track Register ....................... 628

6.5.6.2

RX5CS4 Maintenance Status,
System Configuration Register.................. 6-28

6.5.7

6.5.8

Register RX5CS5, Address 200BO00OE ............... ....6-29
Register RX5EB, Empty Sector Buffer Register,
Address 200B 0010 . ..ottt
e 6-30

6.5.9

6.5.10

6.5.11

e 6-30

Chapter 7

;‘KA820 Diagnostics
7.1

LoadPaths ....... ... .o

7.2

Test Sequence and Repair Recommendations ...................... 7-3

7.3

EVKAA, Hard-Core InstructionTest . . . ........cci

7.4

Appendix B

Appendix C

Appendix D

Appendix E

.. 7-4

7.3.1

Booting EVKAA on the Primary Processor e 7-4

7.3.2

EVKAA Prerequisitesand Functions . . ................... 7-4

Using VDS Stand-Alone ..........c
74.1

Appendix A

i i 7-2

ittt 7-5

Booting VDS Stand-Alene on the Primary Processor......... 7-5

7.4.2

Booting VDS Stand-Alone on an Attached Processor......... 7-6

7.4.3

Help................S @

7.4.4

Attaching and Selecting the KA820 Module. ............... 7-7

7.4.5

Flagsin VDS . . ... .. ..

7.4.6

Test Repetitions............. e
e e 7-8

e e 7-6

7.5

Using VDS On-Line. ...ttt
it e it e, 7-9

7.6

EVKAB, VAX Basic Instruction Exerciser. ..............
... .. . 7-10

7.7

EVKAC, Floating—Point Instruction Exerciser .................... 7-11

7.8

EVKAE, VAX Privileged Architecture Exerciser ............. e 7-11

7.9

EBKAX, VAX 8200-Specific Cluster Exerciser .................... 7-12

7.10

EBDAN, KA820 Serial-Line Unit Diagnostic ..................... 7-12

KA820 Module I/0 Pins and Cables
Al

Module I/O Pin Definitions. .............. e

Cables Related to the KAB20 . ..ottt
e e e
eA-4

e ettt A-1

Module Installation and Access to Cables
B.1

Module Installation and Replacement . ........................... B-1

B.2

Gaining AccesstotheCables ................... I B-2

Drive Load Characteristics of Off-Board Signals
C.1

Serial-Line UnitSignals....................... et

C.2

PCIBusOff-BoardSignals ............cciiiiiiiiiiiiiiiinnnnnn. C-1

e C-1

BlIC Registers
D.1

Device Register, DTYPE (R/W, DMW, DCLOL)..................... D-1

D.2

VAXBI Control and Status Register, VAXBICSR

D.3

Bus Error Register, BER (W1C, DCLOC).......... e EEEETR D-5

........ e D-2

D.3.1
D.3.2

Bus Error Register Hard Error Bits .. ....... [ D-6
Bus Error Register Parity Mode . ........................ D-8

D.3.3

Bus Error Register Soft Error Bits . .. .................... D-8

D.4

Error Interrupt Control Register, EINTRCSR. ..................... D-8

D.5

BCI Control and Status Register, BCICSR ...... T D-10

D.6

Receive Console Data Register, RXCD. ...... et
e
e D-14
'D.6.1

MFPR Instruction for the RXCD Register ., ............... D-15

D.6.2

MTPR Instruction for the RXCD Register . ............... D-15

Port Controller Control and Status Register

vii

Appendix F Internal Processor Registers on the KA820 Module
Appendix G

- Appendix H

Appendix |

Software Boot Control Flags

Appendix J

Sample BoOtstrap Code
J.1l

Appendix K

EEPROM Bootsti'ap Dispatcher ........... e e J-1

J.2

Sample RX50 BootstrapCode . . ......... ... i J-4

J.3

- Sample DU Series Bootstrap Code (MSCP Devices). .. ......ovvunn... J-7

Unexpected Error Conditions
K.1

ID Parity Error Interrupts Following Retry Timeout. ............... K-1

K.2

Clearing the Bus Error Register ...........
.. ... .. ... .. ... ... ... K-1

K.3

Interrupts Following Initialization ................
... .. ... ..... K-1

Glossary

lndex
System Initialization Console Output. .........
... ... ... ...... 3-12
Loading a Patch Block into the Control-Store RAM ................ 3-19
Reading Control-Store Patches .. ... e e e . e

e e e

i 3-20

Sample Console Output Following Entry to the Console Mode ........ 4-4
Representative Boot Commands..............
... ... .. ...
... 4-8

CODN

Commands to Start an Attached Processor ................ e 3-22

00 00 00 00

Examples

Sample Console Dialog Using the D and E Commands.............. 4-12

CODN

NS S S ST ST T

R R R

H 0013000

Console Output Showing a Successful Slow Self-Test ...............4-14
Console Output Showing a Slow Self-Test Failure.................. 4-14
Loadmg and Checking Control-Store Patches from the Console ....... 4-21
Logical Console Dialog Displayed on the Terminal . .. .............. 4-21
Primary Processor Software Performs Logical Console Functions. . . .. 4-22

Booting EVKAA on the Primary Processor . .......... FR

7-4
Booting VDS Stand-Alone on the Primary Processor ................ 7-5

Booting VDS Stand-Alone on an Attached Processor . . e 7-6
Running VDS On-Line from the SYSMAINT Directory .............. 7-9

~ Running VDS On-Line from RX50 Diskette Drive . ................ 7-10
Running EBKAX.. .............. e S 7-12

‘Running EBDAN . ...... R I 7-13

WO WD

l\')[\')[\f)[l\f)l\?b—*l—*l—*

Figures

viii

KA820 Block Diagram...... e

e 1-3

VAXBI Physical Address Space. . . ...ovviit

i, 1-5

KA820 Module Layout. . .. ... e
e
e 1-6

KA820 CPU Section, Block Diagram . ...............ciiiiiien.... 2-3
BTB and BTB Tag Addressmg ...... e e 2-5

Page Table Entry Format ........... A e e ... .2-6
Cache and Cache Tag Addressing.......... e 2-7
KA820 VAXBI Interface, Block Diagram . ........................ 2-11

LN
ORN0 o LN o))

POReTRYREELEERRRRY

I/O Address Space on the VAXBIBuUS . ... ..o oo
2-12
BIIC Internal Register Addresses Used on the KA820 Module
....... 2-14
Port Controller and PCI Devices, Block Diagram ................
.. 2-19
PCIDevice Address Map . ..........ouuuun
2-20
BI ACLOL and BIDCLO L Sequencmg ...... e

Ot W WN

=IO

PYPPYPRR
=

H o

Transmit Control Status Register Format . ... ............
.....
.
Serial-Line Units 1, 2, and 3 Transmit Data Buffer (TXDBI1, 2, 3)

CFormat ...

OY O OY O SO
Oy O
I
[
.
N S G
= = © 00 -3 O
0O J0C Ot
Wi - O

PTLTUt

B WO DN =030
O
W

Power-Up Microcode Flow . ......
...
...i
...
.....
System Initialization Sequence............
... .. ...
.....
...
3-13
Restart Parameter Block Format . ... ........
...
....
... .... 3-15
Control-Store Patch Block Format . .......... eS
3-18
WCSL Register Format. ............
... . ....
... ... .... 3-19
WCSA and WCSD Register Formats . ..............oo.o. ...
3-20
Sample Multiprocessor Configuration . .................... L...3
Use of (ESC) withthe
ZCommand .......................
..
4-17
Machine-Check Status Word Bit Layout .....................
.. .
Receive CSR Bit Format ............ T

Serial-Line Unit 0 Transmit Data Buffer (TXDB) Format ........
....
Watch Chip Bit Rotation on the PCI Bus...... F
6-12
Watch Chip CSRAFormat .. ...............
... .. . e 6-14
Watch Chip CSRBFormat ................. FO
6-15
Watch Chip CSRD Format . ............
... .......
.. .
. 6-15
Register RX5CS0 Command Function Format ....................
6-19

Register RX6CS0 Status Format ........................
..
6—22
RX5CS1 Command Function Format. .. ..................
.. . . 6-23
RX5CS2 Command Function Format: Sector Register ..............
6-25
RX5CS2 Status Format: Current Track Register . . . . .. e
6—-26
RX5CS3 Data Transfer Status Format: Current Sector Register. ... .. 6-27
RX5CS3 Maintenance Status Format: Current Status Register
. .. ... 6-27
RX5CS4 Command Function Format: Incorrect Track Register.
. ... .. 6—28

RX5CS4 Maintenance Status Format System Configuration
Register. ... ... ...
6-29
RX5CS5 Format: Extended Function . .. .. .. ..........
.
.... 6—29
RX5EB Format: Empty Sector Buffer Reglster ................
.... 6-30
RXS5FB Format: Fill Sector Buffer Register. ... ..............
...
.. 6-31
Module I/O Pins on Segment A Viewed from the Backplane ........
. A-1
Module I/O Pins on Segment B Viewed from the Backplane.......
... A-2
Module I/O Pins on Connectors C1 and C2 Vlewed from the
Backplane ........ .. ... ...
A-2
Module I/0 Pins on Connectors D1 and D2 Vlewed from the
Backplane .......... ... . ... .
A
Module I/0 Pins on Connectors E1 and E2 Viewed from the
|
Backplane .......... ... ... ...
A
A Backplane Slot Shown from the Backplane Side of the Card
Cage .. .A

Cabling for C and D Connectors. ...............oonooono.
A
Device Register ODTYPE) .. ......v
....co0 ....D
VAXBI Control and Status Register (VAXBICSR). .. ......
.....
..
D
Bus Error Register BER) .. ........
......
i .... D-5
Error Interrupt Control Register . ............
... .......
.. .
D-9
BCI Control and Status Register . ... ..................
...
L..D-11
RXCD Register ......... ...
D-14

Tables

3-3
4-1
A4-2
4-3
4-4

..... 1-7
... .oy
KA820 Module Power Requirements . ......
Environmental Requirements.............. e e 1-7
Time Required for Read and Write Data Transactions . .............. 2-8
ity 2-13
Node Space Base Address Assignments . .................
BIIC Register Functions on the KA820 Module. . .................. 2—-15
ineneenns 2-16
it
KA820-Initiated Transactions. . ... ......i
KA820Slave Responses. ... ....ccvuiiiiiii i, [ 2—-18
External Signals Affecting the Power-Up Sequence . ................ 3-3
PCM Module Jumper Configurations Affecting the
. 3-4
..
......
... .
EEPROM Update Function....
3-7
e
e
e
Slow Self-Test Checks ........... e
4-2
...
.....
...
PCntl CSR Bits Relatedtothe Console ......
e 4-3
e e e e e
Halt Codes .. .o ittt it
... 4-6
..............
.
Symbols Used in Console Command Descriptions.
Accessible
EEPROM Customer Option Section Addresses

4-5
5-1
5-2
5-3
5-4
6-1
6-2

ConsoleErrorCodes. ........ ... PP 4-19
Interrupt Priority Levels on the KA820 Module .. .................. 5-2
System Control Block Vector Assignments on the KA820 Module. . .. .. 5-3
e 5-6
e
Machine-Check Stack............ e
...... 5-10
..............
(20:16)
Bits
Word
Status
VAXBI Event Codes:
6-1
oot
......
.
...
ity.......
Accessibil
and
PCI Device Addresses
6-3
.t
..
.
Serial-Line UnitRegisters.

6-3

6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6—-12
7-1
7-2
C-1
C-2
C-3
C-4
C-5
C-6
C-7
C-8
D-1

withthe D/E and E/E Commands . . ................. eL .4-11

Setting the Baud Rate for a Serial-Line Unit.............. e .. .6-T

e e .6-10
e e
EEPROMMap ...........covvnnn. e
6-12
y
.o
........
Watch ChipRegisters.
6—-13
i,
.
............
.
Interpretation
Data
Watch Chip
6-13
.
e
..
......
......
Sample
Time
and
Date
Watch Chip
...6-17
......
.....
...
.......
..
Functions
Register
Controller
RCX50
Diskette Surface Selection Code Interpretation.................... 6-20
RCXB0OFunction Codes ... v vi ittt ittt it e aaa s 6-21
RCX50 Extended Functions .......... ... 6—21
RCX50 Error Codes Available in Register RX56CS1 ................ 6—24
Diagnostic Program Categories Related to the VAX 8200............. 7-1
Diagnostic Programs Described in this Chapter .................... 7-2
Serial-Line Unit Output Signal Characteristics . . .................. C-1
PCIBusOff-BoardSignals ......... ..., C-2
Other Off-Board Signals ... ... C-3
... e C-3
Driver Output Voltages..................
G2
.. U
.
....
...
DriverOutputCurrent ....
PCI DAL (7:0) Lines Bidirectional Voltage Levels. . ................ C-4
PCIDAL (7:0) Lines Bidirectional Current Levels . .. .............. C-4
PCI Bus Input Signal Voltage and Current Levels . ................. C-4
Arbitration Control Codes . ........ ..., D-4

i //_\\x

1-1
1-2
2-1
2-2
2-3
2-4
2-5
3-1
3-2

Preface

This manual tells what you need to know about the KA820 processor to use
console commands for maintenance functions and to customize the processor
to suit your needs. It also gives information you need to write system software
tailored to the KA820 module, including device drivers for dedicated devices,
exception handlers, and interrupt handlers.

Intended Audience
This manual is for:

* People who install and replace the KA820 module in the field.

* Engineers and system programmers who incorporate KA820 modules into
their own products or systems.

Before You Use This Manual
You should be familiar with the basic concepts and features of VAX computers, including the:

1. VAX instruction set and data types
2. VAX addressing modes
3. VAX memory management system

4. VAX process structure

You can find this information in the VAX Architecture Hdndbook.
Structure of This Manual
Although the organization of this manual is tutorial, you can use the manual
as a reference as well. It consists of seven chapters and a set of appendixes:

Chapter 1

Describes the major functions, characteristics, and components of the KA820 module. Together with the detailed description in Chapter 2, it gives you a context for assimilating

the programming and operating information in Chapters 3

through 7.

Chapter 2

Completes the overview begun in Chapter 1. It describes the
operation of the KA820 module as a whole and explains the
function of each part.

Chapter 3

Defines the power-up functions and options available to you on
the KA820 module.

Chapter 4

Describes the console functions for the KA820. Console com-

mands such as Examine and Boot help you to maintain the
system.

Chapter 5
Chapter 6

Gives information you need to write exception and interrupt

handling software for the KA820.

Provides programming information for the dedicated devices
on the KA820 module: serial line units, boot RAM, EEPROM,

watch chip, and RCX50 diskette controller.
Chapter 7

Gives an overview of the diagnostic software that tests the
KA820 and tells what you need to know to run the VAX
cluster exerciser programs and the serial-line unit diagnostic
|

program.

- Appendixes A through K contain lists and tables too lengthy to include in the
text of the manual. A glossary and an index follow the appendixes.

The KA820 module is one of a family of processors, memories, and adapters
that use the 32-bit VAXBI bus. For a technical summary of all VAXBI modules, system components, and integrated circuits see the VAXBI Options
Handbook.

Other related technical manuals are the:
VAX 8200 Owner’s Manual
MS8200 Memory Technical Description

DWBUA VAXBITO-UNIBUS Adapter Technical Description
- VAX Architecture Handbook

VAX Diagnostic

Supervisor User’s Guide

VAX Diagnostic System User’s Guide |

xii

Related Manuals

Conventions Used
CTRL/x

You form a control character by pressing the CTRL
key and typing another key at the same time.

Number bases

Most numbers in the text are expressed in decimal
form. Addresses are expressed in hexadecimal form.
Bit patterns are expressed in binary form. Numerals

for which the context does not make the number base
clear are labeled decimal, hex, or binary.
Your input

Examples show your input in red.

Uppercase

Command formats show literals in uppercase.

Lowercase

Command formats show variables in lowercase.

[]

Command formats show optional qualifiers and
parameters enclosed in square brackets.

(CR)

Carriage return.

(LF)

Line feed.

RET

Return key. Pressing

on the terminal sends
(CR) (LF) to the system. Most console commands

terminate with ®ED. The

key is not shown in
command examples, but you should assume that you
must press

after typing a command, unless the

text indicates otherwise.
Special

fant

Text in this font indicates what you see on the console

terminal.

xiii

‘ Chapter 1
Introduction to the KA825 Module

The KA825 module is a single-board VAX processor used in the VAX 8250 and
8350 computer systems. It performs at approximately 1.2 times the speed of

the VAX-11/780. A set of very large scale integrated circuits on the module
implements the VAX instructions. The KA825 module communicates with

other nodes in the system on the 32-bit VAXBI bus.
An earlier version of this module, the KA820, ran at approximately VAX-11/
780 speed. The KA825 is distinguished by bit 23 of the System Identification

Register being set. For the rest of this manual, the term KA820 refers to the
KA825 module; the terms VAX 8200 and VAX 8300 refer to VAX 8250 and
VAX 8350, respectively.
This introduction describes major features of the KA820 module and identi-

fies the options available to you. Chapter 2 completes this overview and provides a background for the operating and programming details that follow.
In multiprocessor systems, the first processor is called the primary processor;
it is installed in VAXBI slot K1J1. Additional processors are called attached
processors, and they can be installed in any slot in the VAXBI backplane. The

multiprocessor system can be symmetrical, where all processors share the
workload equally, or asymmetrical, where each processor is dedicated to specific functions such as I/O control or computation.

The KA820 module is designed to support three operating systems: VMS,
ULTRIX-32, and VAXELN. VMS and ULTRIX-32 are general-purpose, time-

sharing systems. VAXELN systems are dedicated, real-time systems developed under VMS. As a fourth alternative, you may prefer to develop your own
system software for the KA820 module.

The KA820 module protects the integrity of data and processes by checking
extensively for:

e Parity errors
¢ VAXBI transaction errors
¢ Unforeseen microcode conditions
e Interrupts that occur at unexpected levels
The machine-check function, which is invoked following detection of a hardware error, passes control to appropriate exception-handling software. This

lets the software evaluate the situation and respond as required. In addition,
the KA820 module uses a microcode-based ASCII console and provides a
serial-line unit for the console terminal.

The KA820 module implements a self-test program in microcode. Self-test
runs automatically on power-up and in response to a console command, and it
checks the KA820 hardware thoroughly.

1.1

KAB820 Functional Sections

The KA820 module consists of three major sections:
1. CPU section

2. VAXBI interface section

3. Port controller and port controller interface (PCI) bus devices section

1.1.1 CPU Section
Three processor chips carry out processor functions according to 40-bit

microinstructions in control store.

~ e I/E chip (instruction decoding and execution)

e Mchip

(memory management, processor registers, and four serial-line

e Fchip

(floating-point accelerator)

units)

Control store consists of a 15K ROM and a 1K RAM implemented in five
ROM/RAM chips and protected by parity. The RAM stores microcode patches,
making microcode changes as simple as software changes: DIGITAL distributes microcode patches along with software updates on RX50 diskettes. The
MIB bus, which connects control store and the processor chip set, is also pro-

tected by parity.

An on-board translation buffer (BTB) stores virtual-to-physical address
translation information (page-table entries) for 512 pages of memory. The
BTB backs up a mini-t/ranslation buffer (MTB) in the I/E chip that stores five
page-table entries. And an on-board 8K-byte data cache stores data from the
most recently accessed locations in memory. The processor chips communicate with the BTB and the cache on the parity-protected 32-bit DAL bus.

1.1.2

VAXBI Interface Section

The VAXBI interface forms a second section of the KA820 module. It consists
of the 32-bit, parity-protected BCI bus and the bus interconnect interface chip
(BIIC). The BIIC implements the VAXBI bus protocol, including the distributed arbitration scheme and bus error checking facilities.

1-2

Introduction to the KA820 Module

—
-

and the VAXBI interface.

The port controller and dedicated PCI bus devices make up a third section of
the KA820 module. The port controller buffers the transfer of addresses and
data between the CPU and the PCI bus devices, as well as between the CPU

1.1.3 Port Controller and PCI Bus Devices Section

//—\“

SERIAL-LINE
O

EIA

DRIVERS

CONTROL:

CPU CLK

STORE

fe—s SERIAL-LINE
1

RECEIVERS

~ OSCILLATOR

}e—s SERIAL-LINE 2

te—s

<‘

| N

MIB <40>

S
[y

{
[v

CHIP

A
<,,

PAL <7>l> M
V]

[

SERIAL-LINE 3

L
(g

CHIP.|

L
)

cp
|[OK

CAL <11>

CACHE

BTB

J> RAM

RAM

DAL
< 32>

)

r CTRL
A

BCl <32>

-/|

PORT

CONTROLLER

(3PORTS)

PCl <16> DAL

<8>DAL.
]

BIIC

BUFFERS

116 DAL
/

BOOT
RAM

<8>DAL
J

EEPROM

L——a RCX50 INTERFACE
& WATCH CHIP INTERFACE
-

VAXBI BUS < 32>
h|

)

MLO-383-85

Figure 1-1:

KAS820 Block Diagram

The EEPROM is a 16K-byte nonvolatile memory on the PCI bus. It stores

choices for KA820 options, VAX bootstrap macrocode, and a set of patches for

control-store microcode. A write-protection circuit keeps you from changing

EEPROM data by mistake. Microcode copies the bootstrap macrocode to an
8K-byte boot RAM on the PCI bus at the beginning of the boot process.

Introduction to the KA820 Module

1-3

The PCI bus also runs off the KA820 module to connect to the battery-backedup watch chip and the RCX50 controller for the RX50 diskette drive. The

watch chip keeps the time of year for up to 100 hours without system power,

and the diskette controller and drive let you install software and microcode

updates.

1.2 Customer Options
The KA820 module offers a variety of options that let you customize your

computer system. Data stored in the EEPROM and signals that run off the
module to switches on the control panel define the action and characteristics

of the KA820 module on power-up:

o Perform the slow self-test or the fast self-test on power-up.

e Restart or halt on power-up following self-test.

Restart — If battery-backed-up memory has retained valid data during the

preceding power outage, and no VAXBI node is faulty, try a warm start to

continue the process that was executing when power failed. If memory does
not contain valid data or a VAXBI node fails its self-test, boot the system,
loading and starting a fresh copy of the operating system.

Halt — Enter the console mode instead of beginning program execution. In
this mode, the KA820 module accepts console commands from the console

terminal. Console commands are useful when you want to perform system
maintenance functions such as installing software or running diagnostics.

e Set the default console baud rate to one of eight values ranging from 150 to
19200.

e Select the processor node that serves as a logical console for an attached
KA820 processor in a multiprocessor system.

e Enable or disable self-test on the RCX50 diskette drive controller.

1.3

VAXBI Overview

The VAXBI bus is a 32-bit synchronous bus. It joins the KA820 module to the
rest of the computer system. The important characteristics of the VAXBI bus
are its low cost, high bandwidth, moderate number of logical connections,
large address space, and high data integrity.

All devices in the VAXBI system can arbitrate for control of the bus, so no
processor is dedicated specifically to controlling bus use. Distributing the arbitration maximizes the multiprocessing capability of the bus and lets you
configure systems to meet a variety of needs.

Each device on the VAXBI bus is called a node. A single VAXBI bus can have
16 nodes, which can be processors, memories, and adapters. An adapter is a
node that connects other buses, communication lines, and peripheral devices
to the VAXBI bus. Each of the 16 nodes can control the VAXBI bus, and slot

—

1-4

Introduction to the KA820 Module

placement has no effect on the relative priority of the node. A node receives
its priority and node ID, a number from 0 to 15 (decimal), from a plug on the

VAXBI backplane slot where the node is inserted.

1.3.1

VAXBI Addressing

The VAXBI bus supports 30-bit addressing, giving 2**30 addresses (1 gigabyte of physical address space). This address space is split equally between
memory and I/O space (512 megabytes each).

HEX
ADDRESS

0000

MEMORY SPACE
512M-BYTES

1FFF

FFFF

2000

0000

3FFF

FFFF

/O SPACE

512M-BYTES

MLO-384-85

Figure 1-2: VAXBI Physical Address Space |
In I/O space, each node has an 8K-byte block of addresses known as its node-

space. The first 256 bytes of each nodespace are allocated to registers on the
BIIC. In addition, each node is allocated 3.75 megabytes of node private

space. The dedicated devices on the KA820 module PCI bus use addresses in

the node private space.
1.3.2

VAXBI Timing and Arbitration

Events occur on the VAXBI bus at fixed intervals. Data is clocked onto the bus

at the leading edge of a transmit clock signal and received and latched with a
receive clock signal at the end of a bus cycle. Information processing occurs

during the cycle following the one in which data is transmitted and latched.

Bus arbitration and address and data transmissions are time multiplexed

over 32 data lines. Interrupt sequences use command transactions and can be
directed to a single processor or to several processors. Arbitration logic is dis-

tributed among all the nodes and follows a dual round-robin priority scheme.

1.4

KA820 Module Layout
Figure 1-3 shows the major components of the KA820 module. The five segments along the bottom edge of the module provide a total of 300 external I/O

pins to connect with the rest of the computer system. Segments A and B carry
the VAXBI bus signals.

Introduction to the KA820 Module

1-5

OPTION

CONTROL

NUMBER

STORE

MODULE SERIAL
NUMBER

F CHIP

NUMBER

I/E CHIP

FIRST
EEPROM

SECOND
EEPROM

SEGMENT

SEGMENT ~ SEGMENT

pomy

CONTROLLER

Figure 1-3:

1.5

SEGMENT

yaxa)

KA820 Module Layout

Power Requirements
The KA820 module requires three voltages with the voltage regulation
shownin Table 1-1. The current and power columns indicate conditions at 70
degrees C (worst case). The maximum voltage rippleis 400 millivolts peak
to peak.

1-6

Introduction to the KA820 Module

Table 1-1: KA820 Module Power Requirements

1.6

Voltage

Regulation

Current

+5.0

+/- 5%

9.0 amps

+12.0

/- 10%

36 milliamps

0.4 watts

~12.0

+/- 10%

40 milliamps

0.5 watts

46.4 watts total |

)

Power

(415?.5 watts

Environmental Requirements
The KA820 module requires air movement of at least 200 linear feet per minute, at a maximum ambient temperature of 50 degrees C. Temperature, rela-

tive humidity, and altitude requirements depend on use of the RX50 diskette

drive with the KA820 module.

Table 1-2:

Environmental Requirements
Relative

- Configuration

Operation without the

Temperature

Humidity

= 5-50 degrees C

10%-95%

RX50

(10-122 degrees F)

| Operation with the

15-32 degrees C

RX50 installed and in ~ (59-90 degrees F)

use

0-2400 meters

(0-8000 feet)

20%-80%

0-2400 meters

(0-8000 feet)
|

Operation with the

10-40 degrees C
(50-104 degrees F)

10%-90%

0-2400 meters
(0-8000 feet)

in use

—40 to 66 degrees C
(—40 to 151 degrees F)

10-95%

0-9000 meters
|

(0-30000 feet)

conditions

Altitude

RX50 installed but not

Allowable storage

Introduction to the KA820 Module

1-7

Chapter2
KA820 Module Detailed Description

The KA820 central processor executes the full set of VAX instructions. Two

address translation buffers, a data cache, and a floating-point accelerator
help to make this processor efficient. The KA820 module can translate a vir-

tual address to its physical equivalent and access cached data in 160 nanoseconds when there is a hit in the mini-translation buffer (MTB). When there
is a miss in the MTB but a hit in the backup translation buffer (BTB), access

to cached data requires 320 nanoseconds. In comparison, a read memory access with misses in both translation buffers and the cache requires at least

3.84 microseconds (24 CPU bus cycles).
- Three functionally distinct sections make up the KA820 module:

)

o CPU section
e Interface to the VAXBI bus
¢ Port controller and related memory and I/0 devices

The CPU section consists of a three-chip processor unit, control store, the
backup translation buffer, and a cache. A 160-nanosecond CPU clock cycle,
~divided into eight phases, controls timing for the CPU section.

The BIIC (bus interconnect interface chip) coordinates the transfer of information between the KA820 module and the VAXBI bus. A separate 200nanosecond clock cycle controls timing for the VAXBI bus.
The port controller (PCntl) acts as a buffer and traffic director, routing ad-

dresses, control signals, and data between the BIIC and the CPU section. The
port controller communicates with the processor chips, the BTB, and the
cache on the 32-bit DAL (data and address lines) bus. It communicates with
the BIIC on the BCI bus. And it drives the 16-bit PCI, an asynchronous bus
that connects the port controller to external devices as well as devices on the
KA820 module:

* 8K-byte on-board boot RAM used to store bootstrap code during processor
initialization
* 16K-byte on-board EEPROM that provides permanent storage for bootstrap code, control store patches, and configuration data

* RCX50 diskette controller external to the KA820 module

» Battery-backed-up watch chip external to the KA820 module

2-1

2.1

CPU Section
The KA820 module implements the VAX architecture in the CPU section,

~ and the heart of this section is the processor chip set. The chip set consists of
three custom-made, integrated circuits:
1. I/E chip (instruction/execution)

2. M chip (memory interface)

3. F chip (floating-point accelerator)

These chips carry out the VAX instruction set. Each VAX instruction involves

a sequence of steps to access and manipulate data. Microcode for each VAX

instruction controls the coordinating and sequencing of the steps. The

control-store hardware contains the microcode in an array of 40-bit words arranged as 15360 words of read-only memory (ROM) and 1024 words of
random-access memory (RAM). The RAM locations contain patches that update the microcode.

The two translation buffers (BTB and MTB) and the cache supplement the
processor chip set with on-board storage that speeds execution time. The
translation buffers contain address translation information copied from main
memory. The cache holds program instructions and data, also copied from
main memory.

Figure 2—1 shows the CPU section of the KA820 module block diagram given
in Chapter 1.

Four buses connect the CPU components: MIB, DAL, PAL, and CAL. The
parity-protected MIB (microinstruction bus) carries microinstructions, control signals, and addresses between control store and the processor chip set.
Like the microword, it is 40 bits wide. The 32-bit DAL bus is also parity protected; it carries data and addresses among the processor chip set, the cache,
~ and the backup translation buffer RAMs, and from them to the rest of the
KA820 module through the port controller. The PAL bus carries address sig-

nals for the backup translation buffer tags and cache tags in the M chip. And

the CAL bus carries address signals from the M chip to the backup transla‘tion buffer and cache RAMs.

- 2.1.1

I/E Chip Functions

Four logically distinct areas make up the I/E (instruction/execution) chip:
Instruction buffer
Microsequencer

Execution unit

MTB (mini-translation ‘buffer)
The instruction buffer is a silo that holds up to two longwords of prefetched
VAX instructions. This lets the CPU execute sequences of instructions rapidly, without waiting for memory read cycles to fetch instructions. The hard-

2-2

KA820 Module Detailed Description

ware attempts to keep the instruction buffer full. When it is not full and there
is no other activity on the DAL bus that takes precedence, the instruction
buffer initiates a read function. In addition, the instruction buffer sends information
it gathers from decoding VAX instructions to the execution unit
and the F chip.
The microsequencer in the I/E chip determines the address of the next mi-

croinstruction to be executed, except at the beginning of a VAX instruction
and when the first part done (F'PD) flag is set following an interrupt or excep-

tion. When a new VAX instruction is being decoded, the microaddress generator determines the entry point of the microroutine to be executed, based on
the VAX opcode, the operand specifiers, and the current microinstruction.
The I/E chip drives the microaddress over the MIB bus during the first half of

the CPU clock cycle, and control store sends the addressed microinstruction
word on the MIB bus to the execution unit during the second half of the cycle.
This prefetch function assures that the execution unit never waits for a mi-

croinstruction. A new microinstruction is available
at the beginning of each
160-nanosecond CPU clock cycle.
The execution unit contains the general purpose registers (RO through R15),

the arithmetic and logic units, the shifter, and the data paths. It executes the
microinstructions needed to implement the macroinstructions in the instruc-

tion buffer, moving data and addresses to and from the registers and on the

DAL bus to the:

f=— SERIAL-LINE O

EIA

DRIVERS

CONTROL

CPU CLK

STORE

| !

OSCILLATOR
"

MIB <40>

:
RECEIVERS

'
|e— SERIAL-LINE
2

<—=

SERIAL-LINE

CHIP

<‘

<— SERIAL-LINE
1

I/E | PAL <,__7>J> M

CHIP

[

(

V.| cHIP

]
_{

(T e

CACHE

CAL <11>>RAM |

BTB

RAM

PORT

CONTROLLER
MLO-385-85

Figure 2-1:

KA820 CPU Section, Block Diagram

KA820 Module Detailed Description

2-3

F chip
M chip

BTB (backup translation buffer)
Cache
Port controller

When the execution unit derives a virtual address to be accessed, it sends
that address to the MTB for translation to a physical address.
The MTB stores physical address translations for five pages of virtual mem-

ory: four data-stream pages and one instruction-stream page. The informa-

tion for each address translation is called a page table entry (PTE). Each MTB
location contains a tag and a page table entry. The tag tells whether thereis a
valid page table entry (a hit) in the MTB for a given virtual address. The page
table entry includes a 21-bit page frame number identifying the 512-byte
page of physical memory to be used on references to the virtual address. On a
hit, the MTB generates the physical address from the page table entry and

makes the required physical address available on the DAL bus without any
delay. See Section 2.1.2 for more information on address translation.

2.1.2

M Chip, BTB, and Cache Functions

The M (memory interface) chip functions complement the functions per-

formed by the I/E chip; they include:

o BTB tag store

e Cache tag store

e Internal processor register (IPR) implementation
e Interrupt handling

e Memory management
e CPU clock generation

¢ Serial-line unit implementation

o Port controller interface

2.1.2.1 BTB (Backup Tfanslation Buffer) — The BTB backs up the MTB with

512 page table entries (PTEs). The BTB has two sets of storage locations: tag
storage in the M chip and PTE storage in the BTB RAMs. Each BTB tag tells
whether four corresponding PTEs are valid.
|

The BTB RAM contains 256 PTEs for system-space pages and 256 PTEs for

process-space pages. This RAM is arranged as 128 blocks of four longwords.

Each longword contains one PTE. The M chip contains 128 BTB tags, one for
|
-

each block of four PTEs.

2-4

KA820 Module Detailed Description

When there is a miss in the MTB, the I/E chip puts a 32-bit virtual address on

the DAL bus. At the same time, the I/E chip sends virtual address bits (31,
16:11) on the 7 PAL lines to identify one of the 128 BTB tags in the M chip.
Each tag consists of 14 virtual address bits (30:17) and 4 valid bits, one for

each PTE. The M chip compares the BTB tag entry with the address asserted
on the DAL bus. If the bits in the tag match bits (30:17) in the virtual address, and the valid bit is set, there is a hit in the BTB. On the same CPU
clock cycle the M chip puts the address of the appropriate BTB RAM location

(virtual address bits (31, 16:9)) on the 11-bit CAL bus, even if there is a BTB
miss. Virtual address bits (10:9) identify one of the four longwords in the

four-longword block. The BTB RAM responds by sending the PTE to the
MTB, and the MTB updates the corresponding location. On the next cycle
the MTB gets a hit on the same virtual address, converts it to a physical address, and asserts it on the DAL bus. Therefore with an MTB miss and a BTB

hit, the address translation is delayed by one cycle. Figure 2-2 shows the relation of the tags to the BTB.

VIRTUAL ADDRESS

DAL bits |31I30 COMPARE WITH TAGBITS
e

17} |16

VALID
-

PARITY

TAG

PARITY
BIT

128 BTB TAGS IN M CHIP

PAL-—-—[ A< 31,16:11> JI

=130

TAG ADDRESS
BITS

17| pviv2iv3iv4 p

ADDRESS TAG

ARRAY

512 BTB ENTRIES IN RAMs

A<31,16:9> I—————a—
,

ADDRESS BTB

16 BYTE BTB BLOCK

PTE1

-] 4 VALID
BITS

PTE 2

PTE 3

PTE 4

CAL—|

MLO-386-85

Figure 2-2:

BTB and BTB Tag Addressing

KA820 Module Detailed Description

2-5

If a reference to a virtual address misses in the MTB, the BTB may or may not
yield a hit. The MTB will be updated when there is a hit in the BTB. If there is
a miss in the BTB as well, the KA820 module begins a BTB fill cycle, performing a longword read transaction to the appropriate page table in VAXBI memory. The CPU then updates both the BTB and the MTB with a new page table
entry. Since the four PTEs associated with one BTB tag identify contiguous

pages in virtual memory, a change in the 14-bit address stored in the tag invalidates the other three PTEs, in the same block, that were not accessed.
Figure 2—-3 shows the format for each page table entry.
3130

27 26 25

21 20

V(VALID)

PROT(PROTECTION CODE)

M (MODIFY)

RESERVED TO DIGITAL
PFN (PAGE FRAME NUMBER, PHYSICAL ADDRESS BITS <29:0>)
MLO-387-85

| Figure 2-3:

Page Table Entry Format

See the VAX Architecture Handbook for an explanation of memory management.

2.1.2.2

Cache — The cache RAM stores copies of data from main memory

and, like main memory, uses physical addresses to access the data. The cache
operation resembles the BTB operation, and the cache tag storeis also implementedin the M chip.

The cache consists of an 8K-byte array, divided into 128 blocks of 4 octawords
(16 longwords or 64 bytes) each. The cache tag store contains 128 tags: one for

each 4-octaword block of data. Each tag includes:

e 16 bits of a physical address (bits (28:13)) with a parity bit

® 4 valid bits with a parity bit; the four valid bits apply to the four octawords
within a block of cache data

Figure 2—-4 shows the cache and cache tag addressing scheme.
When the I/E chip begins a reference to a physical memory location, it puts

the entire physical address on the DAL bus. At the same time it asserts 7
address bits (12:6)
on the PAL bus to identify one of the 128 cache tag locations in the M chip. The M chip compares the tag entry with the address as-

serted on the DAL bus. If the addresses match, and the valid bit is set, and

physical address bit (29) is 0 (not I/O space), there is a hit in the cache. This
means that the data in the corresponding location in the cache is valid.

2-6

KA820 Module Detailed Description

PHYSICAL ADDRESS

DAL BITS |28

I |12

COMPARE WITH TAG BITS
K

VALID
BIT

TAG

PARITY

{
128 CACHE TAGS IN M CHIP
/

PAL—

A< 12:6>

& 28

TAG ADDRESS BITS

13| plviv2iv3ivaivo

ADDRESS TAG
ARRAY
\

2048 CACHE DATA LONGWORDS

CAL—

A<12:2>

I-_——>
|

ADDRESS CACHE

OCTAWORD # 1

OCTAWORD # 2

OCTAWORD # 3

64 BYTE

BITS

OCTAWORD # 4
|

Figure 2-4:

4 VALID

- —

‘

CACHE BLOCK

IN RAMs

MLO-387A-85

Cache and Cache Tag Addressing

On the same CPU clock cycle the M chip puts the address
of the appropriate
cache RAM location (physical address bits (12:2)) on the 11-bit CAL bus,
even if there is a miss. On a read transaction, the cache data is asserted on the
DAL bus for use by the I/E chip. On a write transaction, new data is written
both to the cache and to the corresponding location in main memory.
On a cache miss (read transaction only) the KA820 module begins a cache fill
cycle, reading an octaword from main memory to update the cache. The CPU
first reads the longword that was missed in the cache, completing the refer-

ence requested by the I/E chip. The CPU continues the cache fill cycle by reading the remaining three longwords in the given octaword block. The address
in the tag entry will change to reflect the address of the new data, and the
valid bits will show that the other three octawords in the 64-byte cache block

are now invalid.

KA820 Module Detailed Description

2-7

Note that a write transaction with a cache miss does not involve updating the
cache.

Table 2-1 shows the number of CPU clock cycles and the time required for

data access with hits and misses in the MTB, the BTB, and the cache, when
there is no other activity on the VAXBI bus.

Table 2-1:

Time Required for Read and Write Data Transactions

Read
or

CPU Clock
|

Cycles to

Transaction Time

Write

MTB

BTB

Cache

Free DAL

Longword

Octaword

Read

Hit

—

Hit

160 ns

—

Read

Miss

Hit

320 ns

—

Read

Miss

Hit

12+

1.92 us+

—

Read

Hit

—

Miss

13+

2.08 us+

—

Read

Miss

Hit

Miss

14+

2.24 pus+

—

Read

Miss

24+

3.84 us+

—

Write

Hit

—

lor4

160 ns

640 ns

Write

Miss

Hit

—

20rd

3.20 ns

Write

Miss

—

12+ or 15+

1.92 us+

800 ns
2.4 us+

If another device on the VAXBI bus writes data to a memory location that is

cached by the KA820 module, the cached data becomes obsolete. To deal with
this condition, the BIIC monitors the VAXBI bus for write transactions initiated by other devices. When a write transaction occurs, the BIIC forwards the

address to the port controller, which in turn forwards it to the M chip. If the

cache contains data for the address in question, the M chip changes the tag to
mark all four octawords invalid.
2.1.2.3

Internal Processor Registers — In addition to tag storage, the M chip

contains 26 of the internal processor registers (IPRs). The microcode uses
these registers for temporary storage during the execution of long and complex VAX instructions. Appendix F lists the IPRs, their addresses, and their
bit configurations. Note that privileged user software can read and write the
IPRs with MFPR and MTPR instructions.
2.1.2.4

Serial-Line Units — The four RS423-compatible serial-line units on

the M chip connect terminals and modems directly to the KA820 processor.

Signal lines from the serial-line units are converted to the standard RS232
format off the module. You can set the baud rate of each serial-line unit sepa-

rately by writing to the appropriate TXCS Register. In addition, you can
change the baud rate on serial-line unit 0, when the primary processor is in
the console mode, by pressing the
key on the console terminal. Avail-

2-8

KA820 Module Detailed Description

able baud rates range from 150 to 19200 (see Chapters 4 and 6 for details). You
can change the default baud rate for serial-line unit 0 by writing a location in

the EEPROM (see Table 4—4).

The serial-line units are not buffered. Each serial-line unit interrupts the
CPU each time it sends or receives a character.
Serial-line units are available only on the primary processor.

2.1.3

F Chip Functions

The F chip, a floating-point accelerator, increases the arithmetic efficiency of
- the KA820 module by speeding up execution of the integer and floating-point

arithmetic instructions:

. ADD(F,D,G)
e CMP(ED,G)
o CVTL(ED,G)
* DIV(FD,G,L)

e EDIV

» EMOD(D,G,H)
e EMUL
e INDEX

e MUL(2,3XE,D,G,H,L)
e POLY(ED,G,H)

e SUBFED,G)

The F chip operates in parallel with the I/E chip. The I/E chip makes decisions concerning the instruction being executed, while the F chip makes

calculations.

The MIB bus feeds the F chip with VAX opcodes from the I/E chip and microinstructions from control store. The DAL bus carries operand data for the F chip

to and from memory or to and from the general purpose registers (GPRs) on
the I/E chip. Operation of the F chip is transparent to users.

2.1.4

Communication Between the Processor Chip Set and the
VAXBI Bus

The processor chip set communicates with the VAXBI bus through the port
controller and the backplane interconnect interface chip (BIIC). When the
KA820 module accesses a memory location or an I/O location, the I/E chip
sends the address to the port controller on the DAL bus. Then the M chip
TN

asserts the CMISS (cache miss) signal to indicate that a memory reference is
required. Four command lines transmit the required transaction type from

the M chip to the port controller.

KA820 Module Detailed Description

2-9

On a read transaction with a cache miss, the port controller initiates a read
on the VAXBI bus. At the same time it stalls the DAL bus until it retrieves
the data and can send the data to the I/E chip and the cache. The port controller includes a 4-longword data silo that buffers data during the transfer process. When the VAXBI memory responds to the read command by sending four
longwords in four consecutive VAXBI cycles, the port controller stores them

in the data silo until it can transfer them. The requested longword goes
to the
I/E chip and the entire octaword goes to the cache.
On a write transaction to memory, the port controller stores the data to be
written in the silo until the BIIC can send it on the VAXBI bus, freeing the
processor chip set to continue processing.

2.1.5

Control-Store Operation

Control store on the KA820 module provides microcode for three sets of
functions:

¢ VAX instruction execution control

'1
i

e KA820 module initialization, bootstrapping, and console functions
e KA820 self-test

Five custom-made ROM/RAM chips make up the control-store hardware. Al-

together they contain 15360 40-bit locations in ROM, 1024 40-bit locations in
RAM, and 160 14-bit locations in contents-addressable memory (CAM). The

.15K ROM contains an initial version of the microcode. The 1K RAM lets you

add patches that change the microcode without replacing the control-store
chips. The CAM locations contain the addresses of ROM words that begm
sequences of microword patchesin RAM.

During the first half of each CPU clock cycle the I/E chip puts a 14-bit address

on the microinstruction bus (MIB). If the current microword comes from the

control-store ROM, the address is asserted on MIB (13:0).
In the second half
of each CPU clock cycle, control store checks for a match in the CAM and puts
the addressed microword on the MIB bus. If there is no match in the CAM,
this microwordis used for the next microinstruction. However, if the CAM
does find a match, it signals the I/E chip to abort the current microinstruction
fetch cycle. The I/E chip then readdresses control store to read from the patch
- RAM, leaving address bits (9:0) unchanged and asserting ones on bits
(14:10). The I/E chip continues to read microinstructions from the RAM until it reaches the end of the patch sequence. The last instruction in a patch
sequence causes a jump back to a ROM location for the next microinstruction.

The KA820 module loads patches into the patch RAM in two sets: primary

patches and secondary patches. Microcode in the control-store ROM loads the
- primary patches from the EEPROM at the beginning of the power-up initialization sequence. The primary patches modify basic microroutines that are
~ necessary to continue the processor initialization sequence. They may in-

volve such functions as self-test, console implementation, and loading the

bootstrap code. Secondary patches are not essential to the initialization process. The macrocode in the primary bootstrap program loads these patches.

2-10

KA820 Module Detailed Description

The 1024 patch RAM locations are mapped against all 15360 ROM locations.
Each RAM location can patch any of 15 ROM locations, all of which use the

same ten low-order address bits ((9:0)) on the MIB bus. The RAM cannot contain patches for two ROM locations for which these ten address bits match.
For example, if ROM location 35C (hex) has been patched, another patch can-

not be written for ROM location B5C (hex) without overwriting the patch for
location 35C.

2.2 VAXBI Interface
The BIIC (backplane interconnect interface chip) mediates all VAXBI transactions in which the KA820 module participates by implementing the VAXBI
‘protocol and sending and receiving commands, addresses, and data. It com-

municates with the port controller on the BCI bus, allowing the port controller to act as a buffer between the BIIC and the processor chip set. Figure 2-5

shows the VAXBI interface portion of the KA820 module block diagram given
in Chapter 1.

DAL< 32>

<‘A“BCI <32> ‘B CONTROLLER
'

PORT

-y

BIIC

VAXBI BUS < 32>

(

‘

MLO-388-85

Figure 2-5:

KA820 VAXBI Interface, Block Diagram

- The BIIC also contains a set of control and status registers. The software
uses them to handle device interrupts, interprocessor interrupts, and error
conditions.

2.2.1

VAXBI Address Space

VAXBI address space is divided into two major sections: memory space and
I/O space. Physical addresses with bit (29) set refer to I/O space; addresses
-

with bit (29) clear refer to memory space. The following map shows the allo-

cation of I/O address space among the VAXBI nodes.

KA820 Module Detailed Description 2-11

HEX

ADDRESS

MEMORY SPACE

0000
1FEF

0000
FFFF

NODESPACE (SEE TABLE 2-2)

2000
0001

0000
EFEF

RESERVED TO DIGITAL

2002
2007

0000
FFFF

2008

0000

2008

O0O0FC

2008

0200

2008
2008

0204
FFFF

2009

0000

2009

1FFF

KA820 BIIC INTERNAL REGISTERS

(SEE FIGURE 2-7)
RXCD REGISTER

RESERVED TO DIGITAL
BOOT RAM

(SEE FIGURE 2-9)
RESERVED TO DIGITAL

EEPROM

2009

|
|

(SEE FIGURE 2-9)

2000

0009

7FFF

2009

8000

2009

FFFF

200A

0000

200A

FFFF

200B

0000

(SEE FIGURE 2-9)

200B

0017

RESERVED TO DIGITAL

200B

0020

200B

8000

200B

807F

RESERVED TO DIGITAL

RCX50

WATCH CHIP

(SEE FIGURE 2-9)

200B 8080

RESERVED TO DIGITAL

203F

2040 0000

WINDOW SPACE
(SEE THE VAXBI OPTIONS HANDBOOK)

RESERVED TO DIGITAL

FFFF

207F

FFFF

2080 0000

3FFF

FFFF

MLO-389A-85

1/0 Address Space on the VAXBI Bus

The first 128K-bytes are allocated to the 16 VAXBI nodes, so that 8K-bytes
are available to each node. The nodespace for the KA820 module depends on
the node ID plug inserted in the backplane at its slot. The primary processor
uses slot K1J1. In addition, each node is allocated 3.75 megabytes for node
private space, ranging from address 2004 0000 to 203F FFFF (hex). Each
node can use this space to address its own registers and devices. The KA820
module implements PCI bus device addresses and one set of BIIC register

2-12

KA820 Module Detailed Description

Figure 2-6:

addresses (not accessible to software)in the portion of this space ranging from

~ address 2008 0000 to 200B 807E. When a node generates a reference to an
address in the node private space, it is a local reference (loopback transaction), confined to that node. No corresponding VAXBI transaction takes place.

No node can access another node’s private space.

2.2.2

KAB820 Registers Accessible to Other VAXBI Nodes

The KA820 module implements the addresses for the RXCD Register and the
BIIC internal registers in the VAXBI nodespace and in the node private

space. However, software should access these registers only through the

VAXBI nodespace. Software access to the RXCD Register and the BIIC internal registers through node private space will produce errors.

Note that when you use console commands, you can access the RXCD Register and the BIIC internal registers on the primary processor through their
node private space addresses as well as through their VAXBI nodespace ad-

dresses. Figure 2-7 shows the BIIC internal registers and the two sets of corresponding addresses. Under the heading VAXBI nodespace address, bb
stands for the nodespace base address of the VAXBI slot used. Table 2-2

shows the nodespace base address for each node.
Node Space Base Address Assignments

Node

Address

HEHOOQmE
> ©0 -0 Tk W
= O

Table 2-2:

2000 0000
2000 2000
2000 4000

2000 6000
2000 8000

2000 A000

2000 C000
2000 E000
2001 0000
2001 2000
2001 4000

2001 6000
2001 8000

2001 A000

2001 C000
2001 E000

Table 2-3 gives a brief .description of the BIIC registers as they are used on
the KA820 module. See Appendix D for the bit functions and configurations
of relevant registers.
As the map in Figure 2-7 shows, the KA820 module leaves many of the registers and addresses in the BIIC unused. The RXCD Register, at address bb +

200 and 2008 0200 is implemented in the port controller, not the BIIC (see
Chapter 4 and Appendix D for more information). Note that software should
not access address 2008 0200.
|

KA820 Module Detailed Description

2-13

VAXBI NODESPACE
HEX ADDRESS

|
31

|
'

04 93

16 15

08 07

DEVICE REGl:‘STER (DTYPE)

bb + 00

bb+ 04

bb +08

bb+OC

bb-F 14
" bb+18
bb+1C
bb+20
bb +24

bb+28

bb +2C
bb +30

bb+ FO

BUS ERROR REGISTER (BER)

2008 0008

| ERROR INTERRUPT C;ONTROL (ElNTRCSR)I

2008 000C
|

FOF'?CE IPINTR/STOP SOU'RCE REGISTER (UNUlSED)
|
© STARTING ADDRESS (UNUSED)
|
- ENDING ADDRlESS (UNUSED)
|

| BCI CONTROL R.E'GISTER (BCICSR) |

)

4 GENERAL PURPOSE REGISTERS (UNUSED)

2008 0010

2008 001C
2008 0020
2008 0024

2008 0028

2008 0026
2008 0030
2008 0040

‘

2008 O0OFO
through

2008
L

USER INTlIERFACE |NTERRUPT CIONTROL REGISTER (l:JlNTRCSR)
|

< '

2008 0014
2008 0018

_' |

" WRITE STATUS REGISTER (UNUSED) |
FOR(.DE IPINTR/STOP COMI\'/lAND REGISTER (FIPS.CMD)
I

2008 0004

- 'IP INTERRUPT MASKlREGiSTER (UNUSE.D)'
.kF_ORCé IPINTR/STOP DEST||\|JAT|ON REGISTER (UNIUSED)

SPACE ADDRESS

2008 0000

7 If\'lTERRUPT DESTINATlON REGISTER (|NTRDéS)

bb + 40

through
bb+ FC

VAX'BI CONTROL AND STA:TUS REGISTER (VAXB]CSR)

bb+10

NODE PRIVATE
00

O0OO0OFC

| MLO-390-85

Figure 2-7: BIIC Internal Register Addresses Used on the KA820

Module (2008 0000 to 2008 0200 not accessible to software)

2.2.3

(

VAXBI Transactions

K A820 module microcode initiates transactions on the VAXBI bus to implement steps in VAX instructions and to respond to conditions and events on the
bus. When the KA820 module responds as a slave to VAXBI transactions initiated by other nodes, VAX instructions and microcode are not involved; cir“cuits in the BIIC and the port controller generate slave responses.

Each VAXBI transaction involves a sequence of three kinds of cycles:

1. Command/Address cycle
\,

2. Embedded arbitration cycle

3. Data cycle

2-14

KA820 Module Detailed Description

(

Table 2-3:

BIIC Register Functions on the KA820 Module

Node

Private

VAXBI

Space

Nodespace

Address

Name

Function

2008 0000

bb+0

DTYPE

DTYPE defines this node as a KA820.

Software can read it, but should not
write it except when loading secondary

patches (as described in Chapter 3).
2008 0004

Dbb+4

VAXBICSR

Initialization software should load

2008 000C

bb+C

EINTRCSR

these registers to enable the KA820’s

2008 0010

bb+10

INTRDES

BIIC to interrupt the KA820 when it

detects VAXBI errors.
2008 0008

Dbb+8

BER

When the BIIC on the KA820 inter|

rupts the KA820, the BER contains

error information. Software should
read and write this register whenever
~

a VAXBI error interrupt or machine

check occurs.

2008 0014

bb+14

IPINTRMSK

These four registers are designed for

2008 0018

bb+18

IPDES

transmission of VAXBI IPINTR and

2008 001C

bb+1C

IPINTRSRC

VAXBI STOP transactions. However,

2008 0030

bb+30

FIPSCMD

system software can ignore these

registers because the KA820 module
supplies internal processor registers
(IPIR and BISTOP)
for these functions.

2008 0020

bb+20

SADR

System software should ignore these

2008 0024

bb+24

EADR

registers.

2008 0028

bb-+28

BCICSR

Microcode loads this register and
system software should not change it.

2008 0040

bb+40

UINTRCSR

System software should normally
ignore this register, since the KA820

is not normally an I/O device.

2008 002C

bb+2C

WSTAT

These five registers are unused and

2008 O00F0

bb+Fo0

GPRO

system software should ignore them.

2008 00F4

bb+F4

'GPR1

2008 O0F8

bb+F8

GPR2

2008 O0FC

bb+FC

GPR3

During the first cycle of a VAXBI transaction the master node sends a command code on VAXBI lines I (3:0) and a slave address on VAXBI lines D

(31:0). If the command specifies a read or write function, the 32-bit field contains a physical address. On an interrupt, the master sends its interrupt pri-

ority level and a destination mask to the slave during the command/address

cycle.

During the embedded arbitration cycle (the second cycle in all VAXBI transactions), other nodes contend for control of the bus following the current

transaction.

KA820 Module Detailed Description

2-15

One or more data cycles complete the transaction. During a data cycle the
function of the 32-bit field depends on the transaction type. For example, the
master sends data to the slave on a write. The slave sends data to the master
|

on a read.

In all VAXBI transactions the slave returns one of four confirmation codes on
VAXRBI lines CNF (2:0):

ACK

Transaction acknowledged.

NO ACK

No node has been selected.
-

RETRY

Busy, try later.

Need more time, wait till data is ready.

STALL

The port controller monitors activity on the VAXBI bus. When an error oc-

curs, the port controller interrupts the CPU. Microcode then initiates a trap
and jumps to an error-handling microroutine. It stores machine-state information on the machine-check stack in memory, making the information
available to exception-handling software. The software can evaluate the data
on the stack and take appropriate action.

2.2.3.1 KA820-Initiated Transactions _ Table 2-4 shows what transactions

the KA820 module can initiate, together with corresponding data lengths.
KA820-Initiated Transactions

Table 2-4:

Data Length
Octaword
Longword

VAXBI Transaction Initiated
Command Function

Cache fill

RCI

Read with cache intent

I/0 space or

BTB fill

IRCI

Interlock read with cache intent

Memory and/or

WCI

Write with cache intent

Memory only

UWMCI

Unlock write mask with cache

Memory and/or

None

WMCI

Write mask with cache intent

intent

Cache fill

I/O space

I/0O space

I/O space or

None

memory

STOP

Stop

IPINTR
|

Interprocessor interrupt

INTR
IDENT

- 2-16

~ Interrupt
Identify interrupting node

KA820 Module Detailed Description

'Not applicable

Not

Not applicable

Not
applicable

Not applicable

Not
applicable

Longword

None

applicable

Write mask transactions involve a read-modify-write sequence, unless the
mask is all ones, because a portion of the data in the target location must
remain unchanged. The port controller changes a WMCI transaction with a

mask of all ones to a WCI transaction.

When the KA820 module performs an IRCI transaction, the slave normally
sets a lock that remains set until the KA820 module issues a UWMCI command to the same address. The KA820 module issues an IRCI/UWMCI transaction pair as part of each of the seven VAX interlocked instructions:

ADAWI
BBCCI

BBSSI
INSQHI
INSQTI

REMQHI

REMQTI
The KA820 module can initiate a STOP transaction but cannot respond to
one. STOP is generally used for diagnostic functions. See the VAXBI Options
Handbook for more information.

As the VAXBI master, the KA820 module can interrupt another processor
with either an INTR or IPINTR transaction. However, KA820 modules in a
multiprocessor system normally communicate with each other by writing
data in the RXCD Registers.

2.2.3.2 KAB820 Slave Responses — Table 2-5 shows VAXBI transactions and
the confirmation codes with which the KA820 module responds to each.
As a safety feature the RXCD lock is not set unless the interlock read transaction is completed successfully. But the RXCD is unlocked by an unlock write
transaction, even if the transaction is not completed successfully.

The KA820 module can respond to both the interrupt and interprocessor interrupt transactions.

2.2.3.3

Device Interrupt Sequence — When a VAXBI node (typically an I/O

device) needs to interrupt the KA820 module, it arbitrates for control of the
VAXBI bus according to its node number. When the node gains control of the
VAXBI bus, it initiates an INTR transaction, sending its interrupt priority
level on VAXBI lines D (19:16) and the decoded ID of the target processor on
VAXBI lines D (15:0).

The KA820 module compares its own decoded ID with the one sent by the
interrupting node and returns an ACK confirmation two cycles later if there
is a match (NO ACK otherwise).

KA820 Module Detailed Description

2-17

Table 2-5:

KA820 Slave Responses

KA820 Response

Command

VAXBI Transaction Received
Description

READ or

Read or read with cache' intent to a BIIC

ACK

Write or write with cache intent to a BIIC

ACK

Interlock read with cache intent to RXCD

ACK

RCI

WRITE or

WCI

IRCI

internal register or RXCD

(

on BI CNF
(2:0) L
|

internal register or RXCD

(with RXCD unlocked)

IRCI

Interlock read with cache intent to RXCD
(with RXCD locked)

UWMCI

Unlock write mask with cache intent to RXCD
(with RXCD unlocked)

UWMCI
-

RETRY

Unlock write mask with cache intent to RXCD

ACK
|

ACK

(with RXCD locked)

‘

INTR

Interrupt

ACK

IDENT

Identify interrupting node

ACK

IPINTR

Interprocessor interrupt

ACK

STOP

Stop

NO ACK

INVAL

Invalidate

BDCST

Broadeast

(

"ACK

NO ACK

(

On a match, the KA820 module also sets one of four interrupt pending flags
in the port controller, corresponding to the interrupt level of the transaction.
The port controller then forwards the states of these flags (note that more

than one may be set) to the M chip. The M chip compares the interrupt level of

the highest flag with the priority of the process the KA820 module is currently executing. When the priority of the current process drops below that of

the highest-priority pending interrupt, microcode initiates an IDENT trans-

action to identify the interrupting node. The BIIC on the KA820 module then
arbitrates for control of the VAXBI bus, and eventually the KA820 module

becomes bus master.

As bus master, the KA820 module asserts the IDENT command code on
VAXBI lines I (3:0) and the level of the highest pending interrupt on VAXBI
lines D (19:16) during the command/address cycle. The second cycle of
IDENT allows arbitration for control of the VAXBI bus for the next transac-

tion. The master asserts its decoded ID on the bus during the third cycle.
Then, on the fourth cycle, IDENT arbitration takes place. If several nodes
~ have interrupts pending at the level indicated, each asserts its decoded ID
(used here as an interrupt sublevel) on VAXBI lines D (31:16). The arbitrating node with the lowest ID (highest priority) wins the arbitration. This node
returns its vector on the next cycle. If the winning node cannot respond imme-

2-18

KA820 Module Detailed Description

(

diately, it sends a STALL confirmation on VAXBI lines CNF (2:0) until it can
send its vector as read data. KA820 microcode uses this vector to find the
interrupt service routine for the interrupting node.

Interrupting nodes that lose an arbitration must start again, regenerating
interrupt transactions. The winning node must also interrupt again if it fails

to receive an ACK confirmation from the KA820 module in response to its
~

vector.

If the port controller detects a VAXBI error condition, it interrupts the M

chip. The M chip then initiates a microtrap to jump to error-handling microcode (see Chapter 5 for details).

2.3

Port Controller and PCI Devices
The three ports of the port controller (BCI port, DAL port, and PCI port) make

it central to the operation of the KA820 module. The BCI port connects the
port controller to the VAXBI bus through the BIIC. The DAL port connects
the port controller to the CPU. And the PCI port connects the port controller
to the 8K-byte boot RAM, a 16K-byte EEPROM, a watch chip, and an RCX50
diskette controller. The timing for each of the three ports is separate: the BCI
bus runs synchronously with the VAXBI clock cycle; the DAL bus runs on the
- CPU clock cycle; and the PCI bus is asynchronous. The port controller keeps
the timing independent by buffering control signals, addresses, and data.

Three gate array chips make up the port controller: two data path chips and a

control chip. Figure 2-8 is a portion of the KA820 block diagram given in

Chapter 1; it shows the port controller and the devices that sit on the PCIbus.

a0
PORT

(3PORTS)

N—

CONTROLLER (

’)
v

'
,

BUFFERS

<8>DAL
v

PCI<16>DAL
16 DAL
:

<8>DAL

BOOT
RAM

EEPROM

———a RCX50 INTERFACE 8 WATCH CHIP INTERFACE
MLO-291A-85

Figure 2-8: Port Controller and PCI Devices, Block Diagram

KA820 Module Detailed Description

2-19

A 32-bit control and status register (PCntl CSR) and the 4-longword data silo
contribute to the central function of the port controller. The data silo buffers
octaword transfers on the VAXBI bus. The PCntl CSR contains status information for use by the microcode and software, control bits accessible to the
CPU, and control signals from the control panel. The status bits tell when an
interrupt is pending, when VAXBI transaction errors occur, and whether the
KA820 module has passed self-test. See Appendix E for details. The PCntl
CSR is located in the KA820 node private space at address 2008 8000 (hex); it
on the VAXBI bus.
is inaccessible to other nodes
2.3.1

PCI Bus Addressing

Devices attached to the PCI bus have I/O addresses in the KA820 node private space. They are accessible only to the KA820 CPU, through the DAL
port on the port controller. Other nodes on the VAXBI cannot read or write to
these devices. Figure 2-9 is a map showing PCI device addresses.

HEX

ADDRESS
2009

0000

BOOT RAM

(BK-BYTES)

2009 3FFC

(UNUSED; THESE ADDRESSES ACCESS
THE BOOT RAM)
EEPROM

(16K-BYTES)

2009

8000

2009 FFFE

RESERVED TO DIGITAL

RCX50 REGISTERS

2008

0000

200B

0016

200B

8000

200B

807E

(UNUSED; THESE ADDRESSES ACCESS
THE RCX50 REGISTERS)

WATCH CHIP REGISTERS

MLO-391-85

Figure 2-9: PCI Device Address Map
The 16 bits of the PCI bus are multiplexed for addresses and data, but address
‘bit 0 is unused. This means that all PCI devices are accessed on word boundaries. However, software can access the packet buffer with all data types. The
EEPROM, RCX50 controller, and watch chip are byte-oriented devices. They
are accessible only with byte-length or word-length instructions on word
boundaries. When word-length instructions are used, data in the high-order
byte is undefined.

2-20 KAS820 Module Detailed Description

2.3.2

EEPROM Functions

The EEPROM (electrically erasable programmable read-only memory) on

the PCI bus contains 8K-bytes of information defining options, the physical
configuration, primary microcode patches, and VAX boot code. The data in
the EEPROM remains valid when power goes down, so that on power-up the
microcode can initialize the KA820 and boot the system according to the requirements of the configuration and the user.

DIGITAL distributes updates for the EEPROM together with software and
microcode patches on diskettes. You can use the EEPROM Utility to load the
update data into the EEPROM (see the VAX 8200 Owner’s Manual for
details). You can read and write 24 EEPROM locations with console D/E and
E/E commands (see Chapter 4). In addition, you can use kernel mode software
Instructions to access any EEPROM location by using the EEPROM node pri-

vate space address. You can also read and write EEPROM data with the
EEPROM Utility (see the VAX 8200 Owner’s Manual for details. The KA820
module protects the EEPROM, so that you cannot inadvertently write in it.

2.3.3

Watch Chip Interface

The eight low-order PCI bus lines and several control lines run from the
KA820 module, through the backplane, to the watch chip. The watch chip lets
the KA820 module keep time through a power outage or system shutdown
that lasts up to 100 hours. The KA820 module stores a 32-bit time value in

the TODR (Time of Day Register) in the M chip, but the TODR loses this value
when the power goes down. The watch chip maintains the time after power is

removed because a battery keeps it going for up to 100 hours.
Three 8-bit control and status registers on the watch chip are accessible to

software, providing control that lets software write the time in the watch chip
registers during installation. Then, in normal operation, software reads the

watch chip to set the time in the TODR following a bootstrap operation. .
Because the watch chip stores time information in units of seconds, min-

utes, hours, days, and months, the operating system must convert this data to
a 32-bit format before updating the TODR Register.

2.3.4 RCXS50 Controller Interface
Like the watch chip, the RCX50 diskette controller is located off the KA820
module, and the low-order eight lines in the PCI bus run off the module to

connect to the controller through the backplane. This device is normally used

to load software updates and microcode patch distributions from DIGITAL.
However, some system configurations do not use the RCX50 controller.
The RCX50 controller contains control and status registers and a buffer capa-

ble of storing data for one 512-byte sector on the diskette. Software can transfer commands, addresses, and data to or from the RCX50 controller in

byte-length register-to-register moves (see Chapter 6 for more information).

KA820 Module Detailed Description

2-21

Chapter 3
Sequences and Optlons on Power-Up

On power-up the KA820 processor tests and initializes itself and then initial1zes the rest of the computer system. Initialization leaves the hardware in a
well-defined state (see Appendix G), ready for any of several courses of action.
You can define in advance what action the processor takes during self-test

and after initialization by choosing from a variety of options. Each option corresponds to a combination of inputs to the module I/O pins. In the VAX 8200
system the inputs come from switch settings on the control panel and jumper
connections on an auxiliary module.

The power-up optmns mclude

e Slow self-test — Test the functlons of the KA820 module. In case of failure,
report faults on the console terminal and enter console mode (if enabled).

Complete the testin 10 seconds.

e Fast self-test — Quickly test the critical functions of the KA820 module. |
Enter console mode (if enabled) on failure. Complete the testin 0.25 second.

® Auto Start — Attempt to restart (warm start) the processor so that it continues executing the process that was running when the power failed. In
systems with battery backup for memory, memory retains power for up to
10 minutes. If the contents of memory remain valid, the warm start suc-

ceeds. If the contents of memory are no longer valid, the warm start fails.

Bootstrap (cold start) the system.

¢ Halt after initialization and enter console mode.
¢ Enable or disable the console.

e Use the physical console (serial-line unit 0) or the logical console (another
VAXBI node).

e Enable or disable writing to the EEPROM.
The KA820 microcode follows a sequence of steps for each of these options.

One other option you can specify in the EEPROM affects the efficiency and
behavior of the KA820 module after power-up, when it is running macro-level
software or console functions. You can preset the default baud rate for the
console serial-line unit. See Chapters 4 and 6 of this manual and the
VAX 8200 Owner’s Manual for information on selecting the console baud rate
and writing to the EEPROM.

A typical system with a single KA820 processor might be set up to take the
steps listed here on power-up:
1. Perform a slow self-test.

2. Initialize the KA820 processor and the rest of the computer system.

3. Attempt to restart the software that was running before the power failure.
4 . Bootstrap the system if the restart attempt fails, loading the operating

system from a disk drive.

3.1

Power-Up Sequence and Related Signals and Jumpers
The KA820 power-up sequence occurs when the BIDC LO L and
BIACLOL
signals are cycled from true to false. The deassertion of BI DC LO L indicates

that power to the VAXBI backplane is steady. B AC LO L is deasserted next
to indicate that dc power will remain steady for at least 4.2 milliseconds. Fig-

ure 3-1 shows the sequential relation of these two signals.

CONTINUE
INITIALIZATION
SEQUENCE

BIACLOL

\4.2MS

/7__

\ (7 !

BEGIN
INITIALIZATION

SEQUENCE

MLO-392-85

Figure 3-1:

BI AC LO L and BI DC LO L Sequencing

A Restart push button on the control panel lets you simulate the power-down/
power-up sequence to boot the system without actually removing power. See
the VAXBI Options Handbook for more complete power sequence information.

Table 3-1 shows the external signals that implement the power-up options.
Table 3-2 lists the PCM module jumper configurations that affect the EEPROM update function. These jumpers control the external signal PNL ENB
WT EEPROM H, listed in Table 3-1.

3-2

Sequences and Options on Power-Up

Table 3-1:

External Signals Affecting the Power-Up Sequénce

External
Signal

Module
I'OPin

BI STF L —

D55

fast self-test

PNL RSTRT

D51

HLTH —

Accessible

Standard Sources

to Software
As

onthe VAX
8200 System

PCntl CSR

Jumpers W1, W2,

bit (27)

If False

W3 on the PCM

test on power-

Perform self-

Perform slow

module

up — jumper

power-up —

W2 to W3

jumper W2 to
Wi

PCntl CSR

Control-panel lower

bit (31)

key switch —

RESTART

|
If True

Update/Halt/ Auto
Start

Enable an
automatic
restart or
bootstrap on

power-up —
lower key
switch is in

the Auto Start
position

self-test on

Halt on
power-up —

lower key
switch is in

the Halt
position; this
signal is false

by default on
attached
processors

PNL CNSL
ENBH —
console enable

D53

PCntl CSR
bit (29)

Control-panel upper
key switch —
Standby/ Enable/

Secure

Enable the
console —
upper key

Disable the
console —
upper key

switch is in

the Enable
position

the Secure
position; this
signal is false
by default on
attached
processors

PN ENB WT
EEPROM H —
EEPROM write
enable

D50

—

Control-panel lower
key switch —
Update/ Halt/ Auto
Start and jumpers

W4, W5, W6, WC
on the PCM module

Enable writes
to the
EEPROM —
lower key

Disable writes
tothe
EEPROM —
lower key

switch is in

the Update
position

the Auto Start
or Halt
position; this
signal is false
by default on
attached
processors

BIRESET L —

B54

reset system

PCntl CSR
bit (28)

PRIM circuit on the
PCM module,

Imitate powerup and

—

control-panel

perform self-

Restart push button
'

test and
initialization

PRIM circuit on the
PCM module

Power has
failed; stop

dc power to
the backplane

processing

is steady;
begin self-test
when BI DC

sequence

BIDCLOL —
dc power low

—

LO L becomes
false
BIACLOL —

B40

—

PRIM circuit onthe

ac power low

PCM module

Power is
failing, save

state

Incoming
power is

steady;
proceed with
self-test and
initialization
when BI AC
LO L becomes
false

Sequences and Options on Power-Up

3-3

Table 3-2:

PCM Module Jumper Configurations Affecting the
EEPROM Update Function

Jumper

W4 to W6
W4 to W5

W4 to W7

Use

Normal

position

Action

Drive PNL ENB WT EEPROM H high or low according to

the lower key switch on the control panel

Enable

Enable writes to the EEPROM, overriding the control

position

panel

Secure

Disable writes to the EEPROM, overriding the control

position

panel

Note that in computer systems where two or more KA820 modules are inserted in a VAXBI backplane, the control-panel functions and the console
functions on serial-line unit 0 are available only for the primary processor
placed in VAXBI slot K1J1. The external signal enabling the physical console
function is PNL CNSL LOG H (module I/O pin D52). The PCM module drives
this signal false on the primary processor to enable the control-panel and console functions on the KA820 module in slot K1J1. On attached processors
'PNL CNSL LOG H is true, enabling the logical console function.
Figure 3-2 shows the sequence of events and optlons on power-up. The remainder of this chapter describes these sequences in detail.
NOTE

In Figure 3-2, W/C refers to the state of the warm start (restart-inprogress) and cold start (bootstrap-in-progress) flags handled by
microcode. I emd, T cmd, and N cmd refer to the Initialize, Test, and
Next commands (see Chapter 4).

3.2

Self-Test
Self-test is the first step in the KA820 power-up sequence. It consists of micro-

code that checks major KA820 functions. If self-test is successful, microcode

indicates success by lighting two yellow light-emitting diodes (LEDs) on the
module and printing messages on the console. Self-test then passes control to
the initialization and restart routines. If self-test detects an error, it fails to
light the yellow LEDs and enters console mode. (The red LEDs are lit when
the processor is in console mode, regardless of the self-test result.) The red
FAULT LED on the control panel lights during self-test and remains lit if any
VAXBI node fails self-test.

Self-test begins when the BIDC LO L signal becomes false, in response to any
of five events:
1. Normal power-up.

2. An operator pushes the Restart button on the control panel, simulating
power-up.

3. Console T command.

8-4

Sequences and Options on Power-Up

DC LO DEASSERTED,

BEGIN SELF-TEST

— ]
AC LO

DEASSERTED

YES

SEND ASCHl # TO
CONSOLE SET DEFAULT

OPTIONS FROM EEPROM,
INIT CAM, RAM,

LOAD PATCHES,

" FAST OR SLOW

SLOW SELF-TEST

SELF-TEST

FAST SELF-TEST

]

| COMMAND

—

SEND ASCIHl # TO CONSOLE, POWER-UP IN|TIALIZATION, PROCESSOR INITIALIZATION,
SYSTEM INITIALIZATION

PROCESSOR

INITIALIZATION

LOWER KEYSWITCH =

LOWER KEYSWITCH =
AUTO START WITH

.V
T COMMAND

——

- AUTO START, NO NODE
BROKEN W/C = 00.

W/C = 11
BOOT

CONSOLE MODE

UPDATE

LOWER KEYSWITCH =
AUTO START; W/C = 10

B COMMAND

N COMMAND

SET WARM FLAG

DECISION

OR HALT OR

SYSTEM

INITIALIZATION

FIND RESTART

COLD START
SET COLD FLAG

PARAMETER

BLOCK

YES

‘PROCESSOR

INITIALIZATION

LOAD PC FROM RPB
START
Y

'CTRL/P COMMAND

VAX PROGRAM MODE,
RUN LIGHT ON

ERROR HALT

RESTART BUTTON
MLO-393-85

Figure 3-2: Power-Up Microcode Flow

Sequences and Options on Power-Up

3-5

4. Software sets the Reset bit (PCntl CSR bit (28)).

5. The KA820 module or another node sets the Node Reset (NRST) bit
(VAXBI CSR bit (10)).
BI DC LO L in turn:

Sets the Broke bit (BIIC CSR bit (12)). This bit makes the self-test status of
the KA820 module available to other nodes on the VAXBI bus.

Clears the Self-Test-Pass bit (PCntl CSR bit (25)). When clear, this bit
drives the wired-OR signal BI BAD L, which lights the red FAULT light on
the control panel. When set, this bit drives the two yellow LEDs on the
module and clears the Broke bit.
|
|
Sets the hardware-fault-state bit (HFSB). This bit lights the two red LEDs
on the module.

Microcode then waits for the deassertion of BI AC LO L before proceeding.
When BI AC LO L becomes false, microcode performs the following functions:
1. Set the console serial-line unit baud rate.

2. Send (CR) (LF) to the console.
3.

Send a # character to the console, indicating that self-test has begun.

4 . Calculate a checksum on the control-store patches stored in the EE-

PROM.

Compare the stored checksum with the calculated checksum. If the comparison fails, print the error code ?4A on the console terminal and halt.
. Initialize the control-store CAM and RAM.

. Load and check primary control-store patches from the EEPROM into
the control-store RAM. On failure, print the error code ?4A on the console
terminal and halt.

. Enable control-store patches.

. Check the operation of the console serial-line unit for all baud rates in
loopback mode (see Chapter 4).
10. Clear the hardware-fault-state bit and turn off the red LEDs on the mod-

ule.
11. Read the EEPROM and set defaults according to the options specified

there:

F chip enable or disable
BTB enable or disable

Cache enable or disable

RCX50 self-test enable or disable

3-6 Sequences and Options on Power-Up

Then the self-test microcode branches according to the state of the BI STF bit,
port controller CSR bit (27).
If BI STF L is true, fast self-test is already complete.

If BI STF L is false (the normal cond1t1on) or m1crocodeis executing a

console T command, slow self-test continues, performing a comprehensive check of the KA820 module.

Thirteen sections make up the slow portion of self-test. On the successful com-

pletion of each section, microcode sends an uppercase ASCII character (A
through N, skipping L), corresponding to the hardware tested, to the console
terminal. If microcode detects an error, it passes control to the console microcode. Table 3-3 lists the slow self-test functions and the corresponding characters displayed on the console terminal.

Table 3-3:

Slow Self-Test Checks

Test

Control-store test

Code
A

Hardware Tested‘

Control store, primary patches;
MIB bus, I/E chip

I/E chip internals test

I/E chip

DAL interface test

Interface of I/E and M chips and
interconnecting DAL bus

M chip internals test
BTB array test; disable or enable BTB

according to data in EEPROM; skip

M chip, and DAL, PAL, and CAL
buses

- BTB array, and DAL, CAL, and
PAL buses

test if BTB is disabled
Cache array test; disable or enable
cache according to data in EEPROM,;

Cache, and DAL, CAL, and PAL

buses

skip test if cache is disabled
I/E chip and M chip interaction test;

I/E chip, M chip

skip test if BTB or cache is disabled
Port-controller CSR test

Port controller

EEPROM test

EEPROM, EEPROM boot code,
port controller, PCI bus

Boot RAM test

Boot RAM, port controller PCI
bus

F chip test; disable or enable F chip

F chip and interconnecting DAL

according to data in EEPROM,; skip

bus

test if F chip or cache is disabled
RCX50 controller test; skip test if
RCX50is disabled

RCX50 controller, interface

driver circuitry, port controller,
PCI bus, cable

BIIC test

BIIC, port controller, BCI bus

Sequences and Options on Power-Up 3-7

Ifa dev1ceis disabled, self test skips the corresponding test and prints adot (.)

on the console terminalin place of the letter.
After successful completion of either the fast self-test or the slow self-test, the
microcode:

1. Sends another ASCII # character to the console
2. Sends (CRY(LF) to the console
3. Clears the Broke bit (VAXBI CSR bit (12))

4. Sets the Self-Test-Pass bit (PCntl CSR bit (25)), which lights the yellow
LEDs on the module to indicate success

5. Passes control to the power-up initialization microcode
The following example shows console output indicating a successful slow selftest.
#

HABCDEFGHIJK
. MN#

‘'The # characters mark the beginni‘ng and end of self-test.
If any KA820 module component is missing or disabled, self-test skips the
corresponding test and prints a dot instead. For example, if the BTB is not

enabled, the console output for successful self-test is ¥ ABCD.FGHIJK.MN#.

The next example shows console output indicating a self-test failure.
#
HARCDE
740
>

This shows that test F failed and there is a fault in the cache array or a related bus. 740 is a console error message indicating that self-test failed on

power-up (see Chapter 4 for a list of console error codes). The three greaterthan signs, 22 make up the console prompt symbol.

The followmg example shows console output on a successful fast self-test.

NOTE

Occasionally, on power-up, the console may print a few random
characters before printing the self-test.

Note that in multiprocessor computer systems, attached KA820 processors in
- VAXBI slots other than slot K1J1 will automatically execute the slow selftest when BI DC LO L and BI AC LO L are cycled, unless the BI STF L signal
is asserted on the VAXBI bus. However, attached processors will not report
self-test status on the console. You can check the LEDs on these KA820 modules to determine self-test status, and software canread the Broke bit for each
module.

3.3

initiaizaticn
Initialization microcode takes control of the KA820 processor at the end of
self-test. Initialization occurs in three phases:

3-8

Sequences and Options on Power—Up

1. Power-up initialization

- 2. Processor initialization

3. System initialization

At the end of this sequence the processor and main memory are ready to begin
executing VAX instructions and restart or bootstrap the operating system.

) 3.3.1 Power-Up Initialization
Power-up initialization‘ microcode performs five steps:

1. Load the power-up halt code 03 in the Argument Pointer (AP).
2. Clear the restart-in-progress and bootstrap-in-progress flags in the M
|

chip.

3. Clear the Busy bit in the RXCD Register in the port controller.

4. Read the control-store patch revision number and CPU revision number
from the EEPROM and load them into the VAXBI Device Register
(DTYPE) in the BIIC (see Appendix D).

5. Load the BCI Control and Status Register in the BIIC, setting seven bits:
Bit (3),

RTOEVEN

Bit(4), PNXTEN
Bit (5,

IPINTREN

Bit (6),

INTREN

Bit (8), UCSREN
Bit (9),

WINVALEN

Bit (10), INVALEN

This setting prepares the KA820 module for VAXBI transactions. See Ap-

(

pendix D for an explanation of these bit functions.

- 3.3.2

Processor Initialization

on the KA820 processor in a known state, ready to
puts
Processor initializati
execute VAX instructions. The KA820 module must be initialized after an
error halt before it resumes processing. Microcode performs this step auto" matically on power-up (or simulated power-up), after a console T command,
|
and in response to a console I command.
Processor initialization involves 24 steps:

1. Turn off test mode features.

2. Load the value 041F 0000 (hex)in the Processor Status Longword (PSL)

(see the VAX Architecture Handbook for details).

Sequences and Options on Power-Up

3-9

Clear the Map Enable Register (MAPEN).

Enable memory-management microcode traps.

Ensure that the hardware-fault-state bit (HFSB) is clear.

< |

Clear the MTB and BTB tags.

Ensure that the M chip refresh function is working.

Halt prefetching of VAX instructions.
Load the POLR Register with 0400 0000 (hex), setting the AST level
(ASTLVL) to 4 (see Appendix F and the VAX Architecture Handbook for

details).
10. Set the Interval Clock Control/Status Register (ICCS) to:

Turn off the interval timer.

Disable interval timer interrupts.

Clear the interval timer error bit.
11. Turn on the Time of Day Register (TODR).

. Clear software interrupts.
13. Clear the Software Interrupt Summary Register (SISR).
14. Clear the Receive Interrupt Enable bit and the Transmit Interrupt En-

able bit for serial-line units 0, 1, 2, and 3.

(

15. Clear pending interrupts at levels 14, 15, and 16 in the ISTATUS

Clear the P1LR Register, \disabling the performance monitor enable
(PME) function.

17. Clear the first part done (FPD) restart codein the M chip. The FPD code

tells whether the processor has been 1nterruptedin the middle of a long

instruction.

18. Clear the machine-check frame in the MTEMP Registers in the M chip.
19.

Invalidate the BTB by clearing the tags in the M chip.

20. Invalidate the cache by clearing the tags in the M chip.
21.

Inthe PCntl CSR:

e (Clear the CRD (corrected .read data) interrilpt bit, bit ¢0).
¢ Clear the CRD interrupt enable bit, bit (2), to disable CRD interrupts.
Clear the IP (interprocessor) interrupt bit, bit (3).
e (Clear the write-wrong-parity bits, bits (15) and (23).

Clear the console-interrupt bit, bit (08).

3-10

Sequences and Options on Power-Up

(

e Clear the remote-console-interrupt bit, bit (10), to disable RXCD
-

interrupts.

e Unlock the VAXBI event code by clearing bit (22).

¢ Clear the Run bit, turning off the RUN light on the control panel, bit
-

(24).

22. Load (or réload) the BCI Control and Status Register as explained in Section 3.3.1, step 5.

23. Load the Device Register (DTYPE) from the EEPROM.

24. Copy the bootstrap section of the EEPROM to the boot RAM, starting at
location 2009 0000 (hex) in the boot RAM.

3.3.3

System Initialization

- KA820 microcode initializes the computer system to prepare for restarting

the operating system and user programs (or the VAX Diagnostic Supervisor)

or for bootstrapping the system. The processor performs this function under

four conditions:

1. As part of the power-up and simulated power-up sequences

2. In response to a console B command

3. In response to a console T command
4. In response to a console T/M command

Every node on the VAXBI bus tests itself when the BI AC LO L and BIDC LO

L signals are cycled from true to false.

The KA820 processor initializes the system by polling each VAXBI node,
reading the Device Register, to determine which slots are occupied and which
ones contain memory nodes. If bits (15:0) are set to FFFF or 0000 (hex), the
node is initializing or Broken. Microcode waits for a ten-second timer to expire before declaring any node faulty. If bits (14:8) in the Device Register are
zeros, the device is a VAXBI memory node.

If a slot contains a VAXBI memory node, the KA820 microcode reads the
VAXBI Memory Control and Status Register to find the amount of memory on
the node and determine whether the node passed its own self-test (the Broke
the memory size in 256K-byte inbit should be clear). Bits (28:18) indicate
crements. From this value the microcode calculates the starting and ending

addresses of this memory node and loads them in the Starting and Ending
Address Registers in the node’s BIIC. The routine adds the memory size to
the maximum memory count (initially zero). It then initializes the BCI Control and Status Register of this memory node by setting bit (8) (UCSREN)
and bit (13) (STOPEN).

If a slot contains a nonmemory node, KA820 microcode reads the VAXBI Control and Status Register, checking the Broke bit to see if the node has passed
its own self-test.

Sequences and Options on Power-Up

3-11

If any VAXBI node has its Broke bit set, the KA820 module does not attempt a
warm start sequence. However, the processor may be capable of performing
the bootstrap function.

If slow self-test is enabled, microcode prints a node number and a space on the
console after finishing with each node that has passed self-test. If a VAXBI
slot contains a node with the Broke bit set, microcode prints a minus sign in
front of the corresponding node number on the console. If a slot with an ID
plug inserted in the backplane is empty, the microcode prints a dot on the

console, instead of a node number, in the position corresponding to the ID
number for that slot. Microcode also prints a dot if it cannot read the VAXBICSR for the node (this can happen if the BIIC fails its self-test and turns off
its driver circuits). Note that if fast self-testis enabled microcode suppresses
this console output.

When the microcode has examined all the nodes on the VAXBI bus, the value
stored in the maximum memory count represents the size of VAXBI memory.
System initialization microcode prints this value on the console terminal on
the line following the VAXBI node status information, before passing control
to the bootstrap microcode. Figure 3—-3 shows the sequence of events in the
system initialization process.

Example 3-1 shows console output for initialization ofa particular system.
at1z2..-5.
20422029

Example 3-1:

System Initialization Console Output

- This console message indicates that:
Nodes 0, 1, 2, and B are good.

Node 5 is faulty.
VAXBI slots with node ID plugs 3,4,6,7,8,9, A,C, D, E, and F
are empty, or the nodes do not respond When mlcrocode reads the
VAXBICSR.

The maximum usable VAXBI memory address is 0040 0000 (hex). This
indicates that there are four megabytes of physical memory.

When the microcode finishes the system initialization sequence, it branches,
depending on the settings of the control-panel switches, as shown in Figure
3-2. If the lower key switch is in the Auto Start position, control passes to the
restart microcode. Otherwise the KA820 module enters console mode. The
console may be enabled or disabled, according to the position of the upper key
switch.
|
Appendix G lists the contents of the processor registers when the KA820 module enters console mode after power-up.
|

3-12

Sequences and Options on Power-Up

START AT VAXBI
NODE
0

LOAD TIMEOUT
CONSTANT FROM
EEPROM

TM
READ VAXBI
NODE DEVICE

DEVICE TYPE OF

0000 or FFFF (HEX)

NONEXISTENT VAXBI

NODE

VAXBI MEMORY NODE

PRINT . “

VAXBI DEVICE NODE

ON CONSOLE

READ MEMORY CSR

FOR SIZE AND

READ BCICSR

BROKE BIT

gfl'?:%TRBNR(?DKEE
|
|

UPDATE MAXIMUM
MEMORY COUNT

LOAD BIIC START/END
ADDRESS REGISTERS
INITIALIZE BCICSR

IF SLOW SELF-TEST

PRINT “n

" ON

CONSOLE (n = NODE

NUMBER)

TIMEOUT

YES

>—

ZERO

PRINT ““n

" ON

CONSOLE (n = NODE
NUMBER)

[

DECREMENT TIME-

OUT REGISTER

INCREMENT
VAXBI NODE

NUMBER

PRINT <CR><LF>
ON CONSOLE
PRINT MAXIMUM

MEMORY ADDRESS

PRINT <CR><LF>
ON CONSOLE

<END>

MLO-394-85

Figure 3-3: System Initialization Seqlisence

Sequences and Options on Power-Up

3-13

3.4

Restart and Bootstrap

KA820 microcode tries to restart (warm start) the software after initializa-

tion, if the RSTRT/HALT bit (PCntl CSR bit (31)) is clear (the lower key
switch is in the Auto Start position), in response to four kinds of events:
1. Power-up.

2. The processor executes a VAX HALT instruction.

3. The processor halts when it detects a machine-check error.
4. Software writes a 1 to the Reset bit (PCntl CSR bit (28)).

If the restart attempt fails, the microcode tries to bootstrap (cold start) the
system. If the bootstrap attempt fails, the KA820 processor halts. The microcode makes only one warm start attempt and only one cold start attempt.

Internal flags that indicate whether a restart or a bootstrap attempt is already in progress keep the processor from looping continuously.

See Appendix G for the contents of the pi'ocessor registers when the KA820

module begins executing VAX macrocode.

3.4.1

Restart Function (Warm Start)

The KA820 microcode does not try to warm-start the system if any VAXBI
node has its Broke bit set, since the faulty node might have failed following
the power failure and might contain data structures or hardware critical to
the process that was running.

The warm start function consists of nine steps:

1. Check the restart-in-progress and bootstrap-in-progress flags in the M
chip. If either flag is set, the warm start fails.

9. Set the restart-in-progress flag. Although microcode sets this bit, software
should clear it by writing 0F03 to the TXDB Register (IPR 23) after a suc-

cessful warm start.

3. Search main memory for a valid restart parameter block (RPB). The operating system writes the RPB when BI AC LO indicates that power is failing. The RPB lets microcode restart the software where it left off, if the
memory is backed up by a battery. If microcode fails to find a valid RPB,
the warm start fails. Figure 3-4 shows the four longwords that make up
the RPB.

4. If a valid RPB is found, check the software restart-in-progress flag at RPB
+ C (hex). The warm start fails if the flag is set. Note that restart software
should set this flag as soon as possible in the restart sequence. If the warm
start is successful, software should clear this flag before passing control to
the interrupted process.

5. Load the Stack Pointer (SP) with the physical address of RPB + 200 (hex).

3-14 Sequences and Options on Power-Up

RPB+0

PHYSICAL ADDRESS OF THE RPB, MUST BE PAGE ALIGNED

RPB+4

PHYSICAL ADDRESS OF THE RESTART ROUTINE, CANNOT BE 0

RPB+8

CHECKSUM OF THE FIRST 31 LONGWORDS OF THE RESTART ROUTINE

RPB+C

SOFTWARE RESTART-IN-PROGRESS FLAG, BIT <0>
MLO-395-85

Figure 3-4:

Restart Parameter Block Format

6. Load the Argument Pointer (AP) with the halt code (see Chapter 4) describing the reason for the warm start.

7. Execute the processor initialization routine listed in Section 3.3.2.
8. Turn on the control-panel RUN light.

9. Start the processor at the address found in the second longword ofa the
RPB.

When the microcode searches for a valid RPB (step 3), it begins by looking for
a page of memory that contains its own address as the first longword. The
search for this page begins at address 0000 0200 and continues through the

end of memory.

If the search yields a page that contains its own address as the first longword,
microcode checks the second longword of the page. If it contains a valid ad-

dress that is not 0, this is the address of the restart routine. If the second
longword is an invalid address or 0, microcode resumes the search for a page

that contains its own address as the first longword.

Microcode then reads the first 31 (decimal) longwords of the restart routine

and calculates a 32-bit unsigned sum of the contents. If the sum matches the
third longword of the page, microcode has found a valid RPB. Otherwise, the
search continues.

If the search for a valid RPB fails, microcode tries to bootstrap (cold start) the
system

3.4.2

Bootstrap Function (Cold Start)

The KA820 module tries to bootstrap the system if a warm start attempt fails
or if an operator types the B command on the console. Note that unlike the

warm start attempt, the bootstrap attempt will occur even if one of the

VAXBI nodes has its Broke bit set.
The bootstrap algorithm involves six steps:

1. Check the bootstrap-in-progress flag in the M chip. If the flag is set, the
bootstrap fails. The KA820 processor remains halted and control passes to
the console microcode.

Sequences and Options on Power-Up

3-15

2. Set the bootstrap-in-progress flag in the M chip, to prevent looping continuously.

3. Find a 64K-byte block of good memory that is page aligned. Note that this
search leaves the locations that get checked in an unpredictable condition.

If the search fails, the bootstrap fails.

4. Load the general purpose registers as follows:
R3 — Boot device. In response to a B (ddxn) command from the console, microcode loads R3 with (ddxn). This is the boot device identifier, where dd indicates the device type, x is a hexadecimal digit
identifying the VAXBI node to which the device is attached, and n is
a hexadecimal digit identifying the device unit number. If the default device is used to bootstrap the system, microcode loads R3 with
zeros. Note that this boot device identifier is not necessarily the device type code used by the VMS operating system.

R5 — Boot parameter. Microcode loads R5 with a boot parameter
(boot control flag) in response to a B/R5:(data) command from the
console (see Chapter 4 and Appendix I).

R10 — Halt PC. On a bootstrap following power-up, R10 is unpredictable.

R11 — Halt PSL. On a bootstrap following power-up, R11 is unprediotable. )

AP — Halt code. See Table 4-2 in Chapter 4 for details.

— Starting address of the prlmary bootstrap (200 (hex) bytes past
SP

the start of good memory).

Microcode leaves the other general registers untouChed.
5. Turn on the RUN light on the control panel.
6. Start executing bootstrap macrocode beginning at physmal address
2009 0104 (hex)in the boot RAM. The codein the boot RAM loads a boot
block which brings in the primary bootstrap routine (generally VMB)
from the boot device into main memory, beginning at the second page of
the 64K-byte block of good memory. The boot device containing the primary bootstrap may be a localmass-storage device, such as an RX50 diskette. The primary bootstrap then loads a secondary bootstrap, whichin
turn bringsin the operating system or the VAX Diagnostic Supervisor.
3.4.2.1 EEPROM and Boot RAM Bootstrap Considerations — At bootstrap time
the boot RAM contains information that lets the KA820 module load the operating system from any of up to ten devices. Microcode copies this information from the EEPROM to the boot RAM as step 24 of the processor
initialization sequence.

3-16

Sequences and Options on Power-Up

Ten device designations in the form ¢(ddxn) and ten corresponding boot code

addresses occupy EEPROM space beginning at location 2009 8040. The first

device listed is the default bootstrap device. The last nine designations iden-

tify bootstrap devices that you can select as arguments to the console boot
command in the form B (ddxn). The address corresponding to each device

designation points to macrocode in the boot RAM that loads the boot block
from that device. Chapter 4 of this manual and the VAX 8200 Owner’s Manual explain how to change the bootstrap information in the EEPROM. Appendix H shows the contents of the EEPROM in detail.
3.4.2.2

Software Responsibilities in the Bootstrap — In addition to loading and

starting the operating system, standard bootstrap software is responsible for

several other functions:

* Loading the secondary control-store patches into the control-store RAM
(before turning on memory management). Section 3.4.2.3 explains this

procedure.

* Loading microcode fc)r other VAXBI nodes.
® Checking main memory for all single-bit and double-bit errors, mapping
out pages that contain errors.

* Clearing the hardware restart-in-progress and bootstrap-in-progress flags'
by writing 0F03 and then 0F04 (hex) to the TXDB Register with the MTPR
instruction.

® Reading the time in the watch chip, calculating the corresponding 32-bit

time value, and loading this value into the TODR Register.

® Clea‘ringvthe software restart-in-progress flag, RPB + C, bit ¢0).
3.4.2.3

Loading Secondary Control-Store Patches — Bootstrap software can

load secondary control-store patches in one block and then read the patches

back to make sure there are no errors. The secondary patches normally over-

write the primary patches loaded into control store from the EEPROM on
power-up. The KA820 processor makes three internal registers available to

software for handling control-store patches: WCSL, WCSA, and WCSD.

The software can use MTPR and MFPR instructions to write and read these

registers.

First the bootstrap softWare should write the entire block of secondary

patches into contiguous physical locations in main memory in the format

shown in Figure 3-5.

The patch for each control-store word requires seven bytes: five bytes for the

microword and two bytes identifying the ROM address that the patch is re-

placing. The bit order shown in Figure 3-5 is irregular, but it must be followed exactly. In addition to the seven bytes for each patch, the block requires

a 7-byte header telling the number of patches in the block, the CAM address
to be associated with the beginning of the block, and a checksum.

The number of patches must be an unsigned number in the range of 0 to 3FC

(hex).

Sequences and Options on Power-Up

3-17

4847

4039

3231

NUMBEROF | CAM
|ADDRESS
PATCHES

PATCH1

|clo|

ROM
ADDRESS

2423

CHECKSUM OF PATCHES

PATCH3 lclo|

BASE +7

ROM

40-BIT MICROWORD PATCH

+ 14
BASE

RoOM

40-BIT MICROWORD PATCH

| BASE +21

ADDRESS
ADDRESS

..........Q.....C.....
PATCH n-1lclo|
PaATCHn |clo]

(

| BASE OF
BLOCK

40-BIT MICROWORD PATCH
<16:9, 8:0, 39, 17:38>

<0:13>

PATCH?2 j|clo{

ADDRESS

1615

ROM

40-BIT MICROWORD PATCH

ROM

40-BIT MICROWORD PATCH

ADDRESS

ZERO PADDED TO LONGWORD BOUNDARY

+ (7+n)
BASE

MLO-396-85

<‘

Figure 3-5: Control-Store Patch Block Format

The CAM address is a number in the range of 0 to 9F (hex) that indicates the
CAM location that will contain the ROM address corresponding to the first
patch.

The checksum stored in the header, when added to the unsigned longword
sum of the rest of the patch block, must equal 6969 6969 (hex):

patch-block-sum + checksum = 6969 6969

You can calculate the number of longwords (X) to be summed according this
formula:

X = ((number-of-patches + 1) *7 + 3)/ 4

The letter C shown in bit 55 in each patch in Figure 3-5 tells whether the

CAM should be loaded with the ROM address being patched. A 1 means load
the CAM. Note that the CAM should be loaded only for the first patch in a
sequence.See Section 2.1.5 in Chapter 2 for an explanation of control store
and the CAM function.

After bootstrap software loads the block of patches into main memory, it can

load the whole block into the control-store RAM with one MTPR instruction,
as shown in Example 3-2.

3-18 Sequences and Options on PoW'ef-Up

(

WCSL =

; Identify the WCSL address.

MTPR (patch-block-base), WCSL
Example 3-2:

Load the entire patch block.

Loading a Patch Block into the Control-Store RAM

This instruction loads the physical address of the base of the patch block into
the WCSL Register. Figure 3-6 shows the WCSL Register format.
WCSL IPR #2E

PHYSICAL ADDRESS OF THE BLOCK OF PATCHES
MLO-397-85

Figure 3-6:

WCSL Register Format

Microcode executes this MTPR instruction by reading main memory, beginning at the patch-block base address. It calculates a checksum, compares this

with the stored checksum, and loads the entire block into the control-store
RAM, if the checksums agree. If the checksums do not agree, microcode does

not load the patches. Software can check the condition codes in the Processor
- Status Longword (PSL) to determine whether the patch load has succeeded.

Condition codes on a successful patch load:

N (— patch-block base address is less than 0

Z, {(— patch-block base address equals 0

V (— 0 = success

C(-C
Condition codes on a patch-load failure:

‘N (— patch-block base address is less than 0
Z, (— patch-block base address equals 0

V (— 1 = failure

C(=C
Next the bootstrap software should check the accuracy of the patches loaded
by reading them back from the control-store RAM. The WCSA and WCSD
registers let the software look into the control-store RAM. The software can

compare the data read against the patch block in memory. Figure 3-7 shows
the formats for WCSA and WCSD.

~ Sequences and Options on Power-Up

3-19

WCSA IPR #2C

8 7

2221

DATA BITS <16:9>

ADDRESS BITS <0:13>

WCSD IPR #2D
0

232221

DATA BITS <17:38>

DATABITS<8:0> | |
<39>

MLO-398-85

Figure 3-7: WCSA and WCSD Register Formats
To read a control-store RAM location the bootstrap software should write the
WCSA Register with an MTPR instruction. Bits (21:8) of the longword must
contain the address ¢0:13) of the control-store ROM location being patched
(note that the normal bit orderis reversed). Other bitsin the longword do not
matter. Next the software should use an MFPR instruction to read the WCSD
Register to retrieve microword bits ¢8:0, 39, 17:38). The software should then
use another MFPR instruction to the WCSA Register to retrieve microword
bits (16:9). Example 3-3 shows this sequence.
|

WCSA = 2C
WCSD = 2D

~; Identify the WCSA address.
~; Identify the WCSD address.

: Get the patch for ROM

MTPR #@B@2172402, WCSA

:
:

address 93A (hex)
(bits are reversed).

;

17:38).

MFPR WCSD, R1

: Read bits (8:0, 39,

MFFR WCSA, R2

; Read bits (16:9).

Example 3-3: Reading Control-Store Patches

Note that the software must execute these three instructions in the order
shown to read each control-store patch. No ihterrupfi;s or exceptions are allowedin this sequence.

Control-store ROM addresses range from 0000 to 3BFF (hex) RAM addresses
range from 3C00 to 3FFB (hex). Addresses 3FFC to 3FFF (hex) refer to the
diagnostic CAM Match Register and should not be used.

When the software reads a control-store ROM address that has been patched,
the microcode returns the microword stored in the patch RAM, not the original ROM microword. After loading and checking secondary patches, software

3-20

Sequences and Options on Power-Up

should set bit (16)in the Device Register and bit (8)in the System Identification Register.

3.5

Sample Multiprocessor Configuration Start Sequence
In a multiprocessor VAXBI computer system only one KA820 module (the
processor in VAXBI slot K1J1) attempts to restart or bootstrap the system
when BI DC LO L and BI AC LO L are cycled or when an operator types the B

command on the console terminal. Figure 3-8 shows a specific multiprocessor
configuration.

(SLOT K1J1) AUTO START

|CONSOLE ENABLE

CONSOLE

TERMINAL

KA820

|
CONSOLE ISON
SERIAL-LINE UNIT 0

VAXBI

HALT

kas20

| CONSOLE ENABLED

|LOGICAL CONSOLE IS
| IN VAXBI SLOT K1J1

—V
HALT

| MEMORY

DISK

KAg20

| CONSOLE ENABLED

| LOGICAL CONSOLE IS
IN VAXBI SLOT K1J1
MLO-399-85

Figure 3-8:

Sample Multiprocessor Configuration

In this configuration processor A is the primary processor. B and C are attached processors. On power-up all three KA820 processors perform self-test,
power-up initialization, processor initialization, and system initialization se-

quences. Each processor polls the VAXBI bus, sizing memory and loading
starting and ending addresses in the memory BIICs.

The primary processor then tries to restart the software. If this fails, it tries to
bootstrap the system.

The attached processors enter the console mode automatically. Microcode in
each attached processor reads the logical console byte in the EEPROM and
sends the following 3 lines of characters to the RXCD Register of the primary
processor (the logical console).
203

FC = 0000

)

Sequences and Options on Power-Up

3-21

An attached processor waits a maximum of one second for the primary proces-

sor to read each character and then sends the next character. If the primary
processor is not in the forwarding console mode or running software that
reads its RXCD Register, the characters sent from an attached processor are
ignored and unavailable to the console operator. If you enter the console mode
on the primary processor and then use the console Z command (see Section
4.3.12 in Chapter 4) the console terminal will display characters as it receives
them from the attached processor you have accessed. If you wait until the
attached processor has finished sending characters before using the console Z
command, the console terminal will display only ), the last character sent in
the console prompt, »)).

If the primary processor succeeds in restarting or booting, software running
in the primary processor can respond to the prompts from the attached processors and start them. The primary processor should send console commands
to the RXCD Registers in the attached processors to set up their internal registers, load their secondary control-store patches, and start the processors
running.

Example 3-4 shows a sequence of console commands that might be used to
start an attached processor.
I<(CR)

! Initialize the attached

!
D,sI

{(address)

{(data){(CR}

! Set up internal processor

§ (address){CR)

registers.

! Start the attached processor
!

Example 3-4:

processor.

running.

Commands to Start an Attached Processor

See Chapter 4 for an explanation of these console commands.

3-22

Sequences and Options on Power-Up

-Chapter 4
Console Functions

KA820 microcode emulates the control-panel lights and paddle switches of

older computer systems with an ASCII console. The KA820 console functions
are compatible with those of other VAX consoles; they let you:
e Start and stop the processor.
e Examine and deposit data in registers and in memory.
e Test the hardware with the self-test microcode and macrodiagnostic
programs.

e Bootstrap the system.

¢ Single step through VAX macrocode.

-~ Run stand-alone programs without using the operating system.
The KA820 console lets you perform these functions from a terminal or an-

other KA820 processor on the VAXBI bus (logical console). You can also load

blocks of data through the console from an automatic load device. The console
terminal or automatic load device must be connected directly to serial-line
unit 0 on the primary processor installed in VAXBI slot K1J1.

For attached processors in multiprocessor systems, RXCD Registers function
like serial-line unit 0, passing commands and responses between the console
microcode and the VAXBI bus. See Section 4.6 for a discussion of logical console operation in multiprocessor systems.

4.1

Console States
The KA820 console is always in one of three states when power is on:

1. Program I/O mode (the processor is running VAX macrocode)

2. Console mode (the processor is halted with the console enabled)
3. Processor is halted with the console disabled
In the program I/O mode, the console terminal acts like a conventional VAX
system terminal. Microcode passes all characters, with the exception of
CTRL/P, from the terminal or RXCD Register through to the software. When

4-1

you type

on the console terminal (or another proceSsor in the VAXBI

backplane sends CTRL/P to the RXCD Register) and the console is enabled,
the processor halts and enters the console mode.

In the console mode, characters typed on the console terminal are interpreted
as commands or parts of commands. The console mode includes two states:
local and forwarding.

e Inthe local console mode, microcode on the KA820 module connected to the
console terminal interprets the console commands.

* In the forwarding console mode, microcode on the KA820 module sends
console commands to an attached processor in another slot on the VAXBI
bus, and the attached processor interprets the commands.
You can return control to the local console mode by typing (cTrRuP). You can
return the processor from the local console mode to the program I/O mode
with the commands to Start, Continue, or Boot. The N command returns the
processor to program I/O mode for one VAX instruction and then passes control back to the console mode.

When the processor is halted and the console is disabled, neither VAX macro-

code nor microcode takes any observable action. In a standard VAX 8200 sys-

tem you can enable the console mode by rotating the upper key switch on the
control panel to the Enable position. Bit (29) in the PCntl CSR i1s a read-only
bit that reflects the position of the upper key switch. See Table 3-1 in Chapter
3 for a list of the switches, corresponding module I/O pins, and PCntl CSR

bits. Table 4-1 lists four PCntl CSR bits related to the console. See Appendix
E for a complete description of this register.

Table 4-1:

PCntl CSR Bits Related to the Console

Module I/O Pin

PCntl CSR Bit

Function

D51
D52
D53

(31)
(30)
(29)

Restart/Halt power-up option bit
Physical/Logical console selection bit
Console secure/enable selection bit

—

(10)

RXCD logical console interrupt enable
control bit, set or cleared by software

4.2

Console Entry
The KA820 module enters the console mode in response to any of the following conditions:

1. From program I/O mode with the console enabled (PNL CNSL ENB H on
module I/O pin D53 is true)

® Youtype
or

4-2

Console Functions

on the console terminal, halting the primary processor;
|

The logical console for an attached processor sends CTRL/P to the attached processor’s RXCD Register. The logical console function on the
attached processor is enabled. PNL CNSL LOG H, module I/O pin D52,
is true; PNL CNSL ENB H, module I/O pin D53, is true; and CNSL
INTR ENBL, PCntl CSR bit (10), is set; or
A VAX error halt occurs or a VAX HALT instruction is executed in kernel mode. The lower key switch is in the Halt or Update position (PCntl
CSR bit (31) is 1). Or the switchis in the Auto Start position (PCntl
CSR bit (31) is 0) and a bootstrap attempt fails.

2. From power-up with the console enabled
Self-test fails.

Power-up initialization microcode detects a hardware error.

The lower key switch is in the Update or Halt position (PCntl CSR bit
(31) is 1).

The lower key switch is in the Auto Start position (PCntl CSR bit (31)
is 0) and a bootstrap attempt fails.
4.2.1

Halt Codes

When the processor halts and enters the console mode, the microcode displays
a halt code on the console terminal, followed by the contents of the Program
Counter (PC) and the console prompt, »)). Microcode also deposits the halt
code in the Argument Pointer (AP) for use by software, if and when the system is restarted or booted. Table 4-2 lists the halt codes and their meanings.
Table 4-2:

Halt Codes

Halt

Code

Meaning

701

Self-test completed successfully.

702

Console halt: The processor received a CTRL/P or N command from the
enabled console source. This could be serial-line unit 0 or a VAXBI node
acting as the logical console. The console is enabled.

703

Power-fail restart.

704

Interrupt stack not valid: The processor tried to save state on the interrupt stack and found the stack invalid or inaccessible.

205

?06

207

CPU double-error halt: The processor tried to report a machine-check
error to the operating system and a second machine-check occurred.

HALT instruction executed: The processor executed a VAX HALT instruc-

tion while in kernel mode.

Invalid System Control Bl(/)ck (SCB) vector: The vector has bits ¢(1:0) both
set.

(Continued on next page)

Console Functions

4-3

Table 4-2:

Halt Codes (Cont.)

Halt

Code

Meaning

708

No user-writeable control store (WCS): Software tried to use WCS by
setting the value 2 in bits (1:0) of a system control block (SCB) vector.
However, there is no user WCS on the KA820.

?20A

CHM from interrupt stack: The processor executed a change mode instruction when the interrupt stack bit, bit (26), was set in the Processor
Status Longword (PSL).

?20C

System control block (SCB) read error: A hard memory error occurred
when the processor tried to read an exception or interrupt vector.

Example 4-1 shows a sample console message following entry to the console
mode.
702

FC = 00000200
2)?

Example 4-1:

Sample Console Output Following Entry to the
Consoie Mode

This message says that a CTRL/P command stopped the processor with the
program counter pointing to address 0000 0200 (hex).

4.3

Console Commands
The following characters have special meaning for the KA820 console microcode.

e (BREAK) — Increment the console baud rate
e B — Boot

e C — Continue
e D — Deposit

e £ — Examine
e H— Halt
e | — Initialize the processor

e N — Next

e S — Start
o T — Test

o T/M — Test with menu

4-4

C(Console Functions

e X — Binary load and unload
o 7 — VAXBI forward

e | — Comment

e (ESC) — Forward the next character without interpreting it. .
e (CTRL/P) — Halt and enter console mode

e (CTRL/S) — Stop console output
e (CTRL/Q) — Restart console output

e (CTRL/U)Y — Abort the current command line and the current command

You can use these commands only when the KA820 module is in the console
mode and the console is enabled. Type
on the console terminal to enter
the console mode. The Z, (ESC), and (BREAK) commands are new with the
KA820 console. However, some console commands used on other VAX proces-

sors are not implemented on the KA820 module; they include:

o F—Find
¢

U — Unjam

L — Load
M — Microstep
R — Repeat

S — Set

°* @
(BACKSPACE)

'« (DELETE)
Although specific rules apply to each console command, the following guidelines hold for all console commands:

1. You must abbréviate all commands (except T/M) to the first character.
This character should immediately follow the console prompt, ))).

2. Console microcode ignores all invalid, -unrécognized, and unsupported
commands, echoing them with the beep (bell) character on the terminal.

3. Console microcode parses all commands as you type them, ignoring invalid characters and echoing them with beep on the terminal.

4. Console microcode takes no action on a command line until you terminate it with a carriage return. Carriage return is echoed as carriage return and line feed. (CTRL/P), (CTRL/S), (CTRL/Q), (CTRL/U),

(BREAK), and (ESC) are exceptions; microcode responds to these commands without waiting for a carriage return.

Console Functions

4-5

. You can enter commands with uppercase or lowercase characters. The
console echoes your input in the case you use, but it always responds in
uppercase.

You must use one space to separate the parts of a command. Multiple
spaces and tabs are invalid, and the console microcode echoes them with
beep.

Console microcode interprets all numbers in commands and responses as
hexadecimal values: addresses, data, and counts.

. You can type valid qualifiers immediately following any part of the command: command character, address, data, or count.

. You must abbreviate the symbolic address PSL to P.
10. Console microcode does not check the ranges for addresses or data. Values

that are too small are extended on the left with zeros. Values that are too
big are truncated.

11. You can abort any console command by typing
Table 4-3:

or (CTRLU).

Symbols Used in Console Command Descriptions

Synibol

Meaning

[

An expression enclosed in square brackets is optional.

Angle brackets enclose category names, such as (address) or

()

(qualifier).

{count)

An 8-digit hexadecimal count. You can omit leading zeros.

{address)

An address argument. You can omit leading zeros. The command
descriptions explain what address types are valid for each command.

{(data)

A numeric argument. You can omit leading zeros.

(qualifier?’

A command modifier. The command descriptions identify valid
qualifiers for each command.

Carriage return. Use
to terminate each command except
control character commands, (ESC), and (BREAK).

RET

4.3.1

Change Console Baud Rate Command ({(BREAK))

(BREHK)

With the KA820 microcodein the console mode, you can set the baud rate for
serial-line unit O by pressing the (BREAK key on the console terminal. Microcode makes eight baud rates available:
150 baud

600 baud

300 baud

4-6

Console Functions

1200 baud

2400 baud

4800 baud
9600 baud
19200 baud

Each time you press BREAK), the console microcode briefly lights the controlpanel RUN light (PNL RUN LED L, module I/O pin D49), increments the
baud rate to the next higher speed, and in the new baud rate prints on the
console terminal:
|
(CRX{LF>
>

If these characters do not appear or they are garbled on the terminal, the
KA820 module is not matched to the baud rate for your terminal. Keep typing
till you find the right speed and the console prompt symbol is ungarbled. DIGITAL ships the KA820 module with the default baud rate for
serial-line unit 0 set at 1200. The default baud rate used on power-up is set
according to data stored in byte 6 in the EEPROM customer option space (see
Table 4—-4). Four other considerations apply to use of the
key:
1. When the console microcode detects (BREAK), it aborts the current com-

mand line and stops parsing or executing any command in progress.

2. Microcode sets the transmit and receive baud rates to the same value.

3. Changing the baud rate by pressing
does not change the default
baud rate stored in the EEPROM. The console will go back to the default
‘baud rate after a power-down/power-up sequence.

4. You cannot forward (BREAK) to another processor with the Z command.

4.3.2

Boot Command (B)

Bl{qualifier)] [{ddxn}l (RET)
The B command lets you boot the system. In response to this command, microcode loads and starts the software, taking the following steps:

1. Initialize the KA820 processor. This includes loading bootstrap code from
the EEPROM into the boot RAM.

2. Load General Purpose Register R3 with the boot device specification
- {ddxn). The boot code in the boot RAM compares the device specification
with ten possible values in the EEPROM. If there is no match, microcode
prints ?44 on the console terminal.

3. Load General Purpose Register R5 with the data (specified in the command qualifier) to be passed to the bootstrap software.
|

4. Initialize the system, polling the VAXBI bus and sizing memory.
5. Search for a 64K-byte block of good memory.

Console Functions

4-7

6. Invalidate the cache.

7. Start executing the VAX bootstrap code in the boot RAM if microcode has
found a 64K-byte block of good memory.

The qualifier for the B command is optional. It takes the form:
/R5:(data)

where (data) is a 32-bit value (boot parameter) to be passed to the bootstrap
software. Appendix I lists the software boot control flags used by the VMB
primary bootstrap code and the VMS operating system. Microcode loads the
data into R5. If you do not specify a qualifier, microcode loads R5 with O.

The boot device specification is optional as well. It takes the form:
{(ddxn)

where

identifies the boot device type.

identifies the VAXBI node number to which the boot device
is attached.

identifies the unit number of the boot device.

If you specify the boot device, you must use all four characters. Microcode

loads the ASCII equivalent of these characters in R3. Note that this format
is not the same as the device specification format for the VMS operating
system.

If you do not specify the boot device, microcode loads 0 into R3 and selects the
default boot device. This is the first of ten devices identified in the EEPROM
beginning at location 2009 8180.

If microcode finds a 64K-byte block of good memory, it adds 200 (hex) to the
address of the first page of the block and loads this value in the Stack Pointer
(SP). It then transfers control to VAX bootstrap code in the boot RAM at
address 2009 0104.

If microcode cannot find a 64K-byte block of good memory, it sends the error
message ?43 to the console terminal and prompts for the next command.
Example 4-2 shows two successful B commands and one failure.
}}IB
a . .

.45

pRZaadan

...

! Boot using the default device.
! Nodes 0, 4, 5, and
F are
!
present on the VAXBI bus.

! System memory size in hex:
!

two megabytes.

with 0.

! Microcode loads R3 with 0 and R5

»)B-R5:10 DUST
a .. .45 . 000
QAZaRRAAR

4-8

Console Functions

! Boot using device DU51.
! VAXBI node configuration.
! System memory size in hex.

! Microcode loads 4455 3531 (hex),
! the ASCII equivalent of DU51,
!
into R3, and loads 10 (hex)
into R5 (specifying the VAX
!
!
Diagnostic Supervisor).

»3B

! Boot using the default device.
!

45.

...

..F

QR2008000

System memory size in hex.

Microcode loads R3 with 0 and R5
with 0.
'
Microcode fails to find a
64K-byte block of good memory.
Halted at this location. The
processor has not started
executing bootstrap code
from the EEPROM.
Console prompt.

743

I
!
!

FC = 20030817F

!
1

VAXBI node configuration.

Example 4-2: Representative Boot Commands
4.3.3

Continue Command (C)

C(RET)

The C command lets you continue executing software at the point where it

has been stopped. In response to this command, microcode passes control to

VAX macrocode. Instruction execution begins at the address specified in the
Program Counter. Continue microcode invalidates the cache but it does not
initialize the processor before starting instruction execution.

4.3.4

Deposit and Examine Commands (D and E)

Dl{qualifiers})]

{(address)[{qualifiers)]

El{qualifiers)]

[{(address)]

{(data)[{qualifiers’](RET)

[{qualifiers)l(RET)

The D and E commands let you write and read data in memory and registers

almost anywhere in the computer system (exceptions include the VAXBI node

private spaces on other nodes).

o Cvk oo

The KA820 microcode divides address space into six categories:
Physical addresses
Virtual addresses
Internal processor register addresses

General purpose register addresses
EEPROM customer options addresses
M chip internal registers

In response to the D command, microcode deposits the data in the address
specified. You must specify an address and some data with the D command,; if
you omit either, microcode displays the error message 744 on the terminal.
In response to the E command, console microcode reads the contents of the

address you specify. The console terminal displays a character describing the
address space (P, I, G, E, or M), the address, and the data. The address argument is optional in the E command.

Console Functions

4-9

The D and E commands take the same qualifiers (except that the D command
does not take the /M qualifier). You can type the qualifiers in any order and in
any of the positions shown in the command format. Each qualifier specifies a
data size or an address space.

Data size qualifiers:
—

The data size is byte.

W
—

The data size is word.

The data size is longword.

—

Address space qualifiers:
/P —

The address space is physical memory. You can use size qualifiers
/B, /W, or /L.

N
—

The address space is virtual memory. If memory mapping is not enabled, the microcode treats the address as physical. When you exam-

ine a virtual memory location (E/V) and memory mapping is enabled,
microcode displays the physical address corresponding to the virtual
address you request. You can use the size qualifiers /B, /W, or /L.
The address space is the set of internal processor registers (IPRs) accessible to software with MTPR and MFPR instructions. See Appen-

dix F. The size is longword, and the microcode ignores any size
qualifier specified.

The address space is the set of general purpose registers RO — R15.

The size is longword, and the microcode ignores any size qualifier
specified. The address you specify must be in the range 0 to F (hex).
E —

The address space is the customer option section of the EEPROM (see
~ Table 4-4). The size is byte, and the microcode ignores any size qualifier specified. If you use the /W or /L qualifier with the E/E command,

the console terminal will display 2 or 4 bytes, but only the low order
byte is valid. You can write data in 24 (decimal) EEPROM locations if
the lower key switch on the control panel is in the Update position
(PNL ENB WT EEPROM H, at module I/O pin D50, is true). The address you specify must be in the range 0 to 17 (hex). If the address is
out of range or the lower key switch is not pointing to Update (PNL
ENB WT EEPROM H, at module IO pin D50, is false), the microcode
displays the error message 7?47 on the terminal.

When you write data in the EEPROM, microcode waits for 10 milliseconds following each D command to allow the EEPROM to load the
data. Note that you can examine these EEPROM locations even when

the lower key switch is not in the Update position (when PNL ENB

WT EEPROM H, at module I/O pin D50, is false). Table 4-4 shows the
EEPROM customer option section addresses accessible with the D/E

and E/E commands.

4-10

Console Functions

Table 4-4:

EEPROM Customer Option Section Addresses

Accessible-with the D/E and E/E Commands
Address

Function

0-2

Reserved to DIGITAL

RCX50 self-test enable

Implementation

Bit (4) (0 = enable, 1 = disable)
Bit (3) must be 1
Bits (7:5;2:2) must be 0

Logical console node ID

Bits (3:0) identify the VAXBI node
number of the logical console
Bits (7:4) must be zero

Reserved to DIGITAL

Default console baud rate

Bits (7:0) =30 -

150 baud

31 —

300 baud

32 —

600 baud

33 —

1200 baud

34 -

2400 baud

35 —

4800 baud

36 —

9600 baud

37 — 19200 baud
7

F chip disable

Bit (0) (1 = disable, 0 = enable)

BTB disable

Bit (1) (1 = disable, 0 = enable,

Cache disable

Bit (2) (1 = disable, 0 = enable)

must be zero)
Bits (7:4) must be zero

8-17

Unused

16 bytes

—

The address space is the set of 64 CPU
internal registers in the M chip. The

size is longword, and the microcode ig-

nores any size qualifier specified. You
can use the E/M command following a
double-error halt to read the contents

of the stack stored in the M chip registers. Table 5-3 in Chapter 5 lists the
- contents of the M chip registers that

contain useful information on a CPU
double-error halt. You cannot examine
M chip register 1F (hex). This is the

Processor Status Longword Tempo-

rary Register. If you try, the console
will respond with the error message

?45. The /M qualifier is available only
with the E (examine) command. It is
not available in combination with the

D (deposit) command, and you cannot
write data in the M chip registers.

Console Functions

4-11

The qualifiers for the D and E commands are optional. The default address

space is physical, the data size is longword, and the default address is 0 under
three conditions:
1. After processor initialization
2. After entry into console mode
3. After execution of an N command
Otherwise the address space and data size used in the last D or E command

are the defaults, and the default address is the last address plus the last data
size used in a D or E command.
You can use the symbolic address P to deposit or examine data in the Pro-

cessor Status Longword (PSL). The size is longword, and the microcode ignores any size qualifier specified. Following a D command to the PSL, the
default address is set to the PSL for a subsequent E command. Depositing

data in the PSL may leave the processor in an unpredictable state when it
returns to program I/O mode. Example 4-3 shows D and E commands in console dialog.

NOTES
The default console baud rate is initially set to 1200.
Do not change byte 7; bits (2:0) of byte 7 should always be 0.
»))DsLsF 5050 35353535

Deposit 35353535 (hex) at
physical address 0000 5050.
! Examine the longword at address
!
0000 5050.
! Physical address 0000 5050
!
contains the data 35353535
|
|

Y)E/L/F 5050
F

20085252

35353535

!
!

YNE
P

20025054

(hex).
Examine the next location.

QRFFaRFF

YID/UAF 5054 2607

Deposit 0607 (hex) at address
0000 5054.

Y))E/B/F
P

Examine the byte at physical
address 0000 5056.
20eR5256

YME/LAV 0204
P

00030404

69696969

Examine the longword at virtual
address 0000 0204.
The physical address is
0003 0404.

YNEG 2

Examine General Purpose
Register R2.

QaReRaRaz

QaR520@5

YIE/E 6
P

Examine byte 6 in the customer
options section of the EEPROM.
2009817C

Y)/E 6 32

Set the default console
baud rate to 600. The lower
key switch must be in the
Update position.

Example 4-3:
4-12

Console Functions

Sample Console Dialog Using the D and E Commands

4.3.5

Halt Command (H)

H(BED

The H command has no effect on the processor. When the KA820 module is in
console mode, it is already halted. When the processor is running in program
I/0 mode, CTRL/P halts the processor. The console H command merely
provides compatibility with other VAX consoles. In response to the H command, console microcode prints the contents of the Program Counter on the
terminal:
YIH
FC =

(address)

)

4.3.6

Initialize Command (1)

I(RET)

The I command lets you put the processor in a known state, ready to execute

VAX instructions. In response to this command, the microcode performs the
processor initialization sequence described in Section 3.3.2 in Chapter 3. It
does not initialize the computer system, and no other VAXBI node is affected.

4.3.7

Next Command (N)

N(RET)

The N command lets you step through VAX macrocode one instruction at a

time. In response to this command, console microcode executes the VAX instruction at the address currently contained in the Program Counter. Execution then stops and the console displays:
02

(address)

)

The PC displayed is the address of the next VAX instruction.

4.3.8
5§

Start Command (S)

[(address)1(RET)

The S command lets you start program execution from the console, beginning
where you choose. The KA820 module begins executing VAX instructions at
the address you specify. The address argument is optional. If you omit it, the
Program Counter identifies the default starting address.

The S command is equivalent to a D command followed by a C command,
where the D command deposits an address in the Program Counter. Start microcode invalidates the cache, but it does not initialize the processor before
starting instruction execution.

Console Functions

4-13

4.3.9

Test Command (T)

T(RED

The T command lets you test the KA820 module from the console. In response
to this command, console microcode executes the slow self-test described in
Chapter 3, Section 3.2. The configuration of jumpers on the PCM module has

no effect on the tests executed. First, microcode sets the VAXBI RESET bit,
bit (28) in the PCntl CSR Register, to start a power-down/power-up sequence.
This forces the control-store microaddress to 0000.
Before executing the slow self-test, the processor loads primary control-store
patches from the EEPROM and sets the default baud rate on serial-line unit
0. If the KA820 module passes the slow self-test, the microcode prints # ABCDEFGHIJK.MN# on the terminal and performs power-up initialization, processor initialization, and system initialization. Self-test prints a dot instead
of a letter to indicate a missing or disabled KA820 module component. If the
KA820 module fails the slow self-test, the microcode prints only letters corresponding to the tests passed.
Example 4-4 shows the console output in response to a T command, when the
KA820 module passes the slow self test.
YT
#

HABCDEFGHIJK
. MN#
o .. .45 0
QRZ0a020
201

! Self-test passed.
FC

22222222

)

Example 4-4:

Console Output Showing a Successful Slow Self-Test

In this example VAXBI nodes 0, 4, 5, and F are installed and have passed selftest. VAXBI memory contains 200000 (hex) bytes. The program counter
points to address 22222222.

Example 4-5 shows console output when the processor fails the slow self-test.
T
#
HABC

240

FC = 22222222
)

Example 4-5:

Console Output Showing a Slow Self-Test Failure

In this example test D fails, indicating an error in the M chip (see Table 3-3 in
Chapter 3). The error code ?40 confirms the self-test failure.

4-14

Console Functions

4.3.10

Test with Menu Command (T/M)

T-M(RED)

The T/M command lets you boot software from a dévice designated in the
EEPROM. The ASCII code for this device is loaded at address 2009 C008.

Typing the T/M command is equivalent to typing B/R5:11. The microcode
does not perform a power-down/power-up sequence or self-test. Instead, the
microcode:

Loads General Purpose Register R3 with 0.

Loads General Purpose Registér R5 with 11 (hex).
Performs system initialization.

Searches for a page-al¥gned 64K-byte block of good memory.
Passes control to the VAX boot code in the boot RAM at physical address
2009 0104 Chex).

4.3.11

Binary Load and Unload Command (X)

#l{qualifier)]

{address)

{count}(RED{checksum}

The X command allows an automatic load device to communicate with the

console microcode. This command can be used in the DIGITAL manufacturing process, but it is not suitable for use by an operator using a keyboard.
In response to the X command, console microcode reads or writes the number
of bytes you spec1fy at the address you specify. The address space is always
physical.

The optional /P qualifier makes the KA820 console c,ompatible with other
'VAX consoles.

Bit (31) of the count is a load or unload signal. If bit (31) is clear, microcode

loads data from serial-line unit 0 into memory. If bit (31) is set, microcode

reads data from memory and sends it to serial-line unit 0. The remaining bits
in the count tell how many bytes to load or unload.

The checksum following the carriage return is an 8-bit command checksum
that includes the ASCII value of the carriage return. If the sum of the command characters plus the command checksum equals zero, the console issues

a prompt symbol and sends or receives data. If the command checksum is not

zero, the console issues the error message ?48 and an input prompt. The command checksum feature lets you escape from inadvertent entry into the binary load mode from the console terminal.

On a binary load command the console microcode accepts the number of bytes
specified in the count plus an additional byte containing the data checksum.
The console loads all characters, including CTRL/P, CTRL/S, and CTRL/Q,

without interpreting them. If the 8-bit sum of the data plus the data checksum is not zero, the microcode responds with the 748 error message.

Console Functions

4-15

On a binary unload command the console microcode sends the number of
bytes specified in the count plus an 8-bit data checksum that the automatic
load device can use to verify the data it receives. The console responds to
CTRL/P, CTRL/S, and CTRL/Q commands from serial-line unit 0 during the
unload function.
|

- 4.3.12

VAXBI Forward Command (Z)

Z {node-number)(RET)

The Z command lets you forward characters from the console terminal con-

nected to serial-line unit O on the primary processor (VAXBI slot K1J1) to an
attached processor on the VAXBI bus. The node-number argument is a hexadecimal character (0 — F) that identifies the attached processor.

In response to the Z command, the console microcode enters the forwarding

console mode and sends all characters typed at the console terminal (except
and Esc)) to the RXCD Register on the node you select. The selected
node echoes all console commands by writing to the RXCD Register in the
primary processor.

Console microcode on the primary processor may find that the remote node’s
RXCD Register is busy for more than one second. In this case, the primary
processor overwrites the character in the remote node’s RXCD Register by
writing first with the Busy bit off and then with the Busy bit on. The two
write functions generate a new interrupt on the remote node. This procedure
ensures that a remote processor will respond to a CTRL/P command, even if it
is hung.

In multiprocessor systems, the primary processor serves as the logical con“sole for attached processors. The physical/logical console selection signal
(CNSL LOG, PCntl CSR bit (30))is 0 by default on the primary processor,
selecting serial-line unit 0 as the physical console source. In attached processors, the CNSL LOG signal is 1 by default, enabling another processor to
serve as the logical console. The EEPROM in each attached processor contains the node number (ID) of the processor that can serve as the logical con- sole (byte 4 of the customer optlon section of the EEPROM).
You can ex1t from the forwarding console mode to the local console mode by
typing (CTRUP) on the console terminal. To send aCTRL/P command to an attached processor you must type
first. (ESC) unconditionally forwards
the next character to the attached processor, even a (CTRL/P) command or another (ESC) character. When you type
(CTRP), the
microcode forwards CTRL/P, halting the attached processor. The attached
processor then enters the console mode, ready to accept other console commands. Figure 4-1 shows the function-of the (ESC) command in combination
with the Z command. Notice that after forwarding a character, microcode
- checks for the presence of a character in its own RXCD Register.

4-16

Console Functions

Z COMMAND IN

CONSOLE MODE
ENTER

FORWARDING

CONSOLE MODE

‘l

GET A

CHARACTER

YES

(NEXT
CHARACTER

IS A
LITERAL)
|

GET ANOTHER

CHARACTER

(EVEN CTRL/P)

TERMINATE

ITA

CTRL/P

FORWARDING
ENTER LOCAL
CONSOLE MODE

FORWARD THE

CHARACTER

THERE A

CHARACTER

PRINT THE
CHARACTER

IN THE LOCAL
RXCD

MLO-400-85

Figure 4-1:

Use of (ESC) with the Z Command

Console Functions

4-17

4.3.13

Console Comment Command (!)

P {comment characters...’1l(RET)

You can enter comments in your console dialog if you use the comment command. Console microcode echoes the characters typed after the exclamation

point, but takes no action. This is handy if you plan to save the console output
displayed on a hard-copy terminal.

4.3.14

Enter Console Mode Command ((CTRL/P))

(CTRL;P}
You can halt the processor and enter the console mode by typing (CTRUP), if the
console is enabled (PCntl CSR bit (29) is 1). The processor responds by displaying the halt code 702, the contents of the program counter, and the console prompt symbol on the terminal. See Sections 4.3.15 and 4.6 for
information on sending a CTRL/P command to an attached processor.

4.3.15

Forward Next Character Command ((ESC))

(ESC)

(ESC) works in combination with the Z command. When the console is in
forwarding console mode and you type (€TeuP) on the console terminal, the
microcode normally terminates the forwarding console mode and enters the
local console mode. You can prevent this response by preceding the CTRL/P
command with the (ESC) command. (ESC) forces the console microcode to
forward the following character without interpreting it.

4.3.16

Stop Console Output Command ((CTRL/S))

(CTRL/S)

You can stop the flow of console output to the console terminal by typing
(ciews). In response to CTRL/S, console microcode also discards all input
characters except CTRL/P, CTRL/Q, and CTRL/U. It echoes each discarded
character with beep.

4.3.17

Restart Console Output Command (CTRL/Q}))

(CTRL-1}2

You can allow the stopped flow of console output to resume by typing
(CTRUQ).

4-18

Console Functions

4.3.18

Abort Command Line Command ((CTRL/U))

{(CTRL/1D

If you make a mistake in a command line, you can start again by typing
before you press the carriage return. Console microcode then ignores
the entire line and displays a fresh prompt symbol.

4.4

Console Error Codes

When the console microeode tries and fails to execute a function, it displays
an error code on the console terminal. Like the halt codes, each console

error code begins with a question mark. Table 4-5 lists these codes and their

meanings.

Table 4-5:

Console Error Codes

Console
Error

Code

Meaning

240

Self-test failure.

741

BI AC LO L timeout: BI AC LO
L not deasserted within 10 seconds
of power-up.

- 42

A warm start or bootstrap attempt has failed because the

bootstrap-in-progress flag is already set.

743

Microcode cannot find a 64K-byte block of good memory while
trying to bootstrap the system.

744
745

Unrecognized console command or boot device speCifiCatiQn.
-

Memory reference not allowed. A console D, E, or S command
required a memory reference, and a translation-not-valid fault or
access violation occurred.

746

Invalid access to an internal processor register.

247

Invalid access to the EEPROM. Either the address specified bya
D/E or E/E command is outside the valid range of 0 to 17 (hex), or
writing to the EEPROM is inhibited (PNL ENB WT EEPROM H,

I/0O module pin D50 is false). Microcode detects the second case
with an automatic read-after-write check to the location accessed.
748

Incorrect checksum of command or data in an X command.

Error while loading primary control-store patches from the
EEPROM.

?4B

?24C

Checksum error in a boot program in the EEPROM.

Hardware error. This may be an MIB or DAL parity error or a
VAXBI error. Or it may result from reference to nonexistent
memory or a nonexistent device.

Console Functions

4-19

4.5

Loading Control-Store Patches from the Console
In normal KA820 module operation microcode loads primary control-store
patches from the EEPROM before beginning self-test, and bootstrap software
loads secondary patches from a bootstrap device. Section 3.4.2.3 of Chapter 3
explains how to write software that loads control-store patches by manipulating the internal processor registers WCSL, WCSA, and WCSD. However, you
can also use the console to manipulate these registers and load control-store
patches. This process requires three steps:
1. Write the block of patches to main memory, using the console D or X command, according to the format shown in Figure 3-5. The block must include the number of patches, the beginning CAM address, and a
checksum, as shown there.
2. Load the block of patches into the control-store RAM by depositing the
main-memory starting address of the block in the WCSL Register (IPR
2E). The address must be physical.

3. Check the loaded patches by reading them back from control store. For
each microword patch:

e Deposit the address, bits (0:13) of the patched control-store ROM location, in the WCSA Register IPR 2C), bits (21:8).
e Examine the WCSD Register (IPR 2D) to retrieve microword bits (8:0,
39, 17:38), in that order.

e Examine the WCSA Register to retrieve microword bits (16:9) in the
first byte.

Figure 3-7 in Chapter 3 shows the bit configuration of the WCSA and WCSD
registers. Example 4-6 shows the console output during a control-store patch
load sequence.

Y))D/F FoRR 43214321
222D/F FOR4 87658765

! Deposit a block of control-store
! patches in main memory.

»YD/1 2E FoR@

! Transfer the entire block of
!
patches from main memory to the
!
control-store RAM, by writing
!
to the WCSL Register.

YD,

! Start the 3-command sequence to
!
examine the patch for ROM
!
address 07F3, by writing the
!
address (inverted) in bits
|
(21:8) of the WCSA Register.

2C QR33F2QA0

2
=

YNET 2
I

4-20

QoadaazDd

Console Functions

EEZ3001F

| Examine microword bits
1
(8:0, 39, 17:38), by reading
!
the WCSD Register.

INE/T 2C

! Examine microword bits (16:9), by

oooaoez2c

y))Ds1

0033F81E

QQQBFRQQ

reading the WCSA Register.

! Examine the next patch.

y))
Example 4-6:

Loading and Checking Control-Store Patches from
the Console

4.6

Logical Console Operation
In a multiprocessor system the primary processor can store and forward console commands for attached processors from the console mode and from the
program I/O mode. With the primary processor in the local console mode, you
begin the logical console session by typing the Z command.
In Example 4-7 the attached processor (node 4) is initially running in the
program I/O mode, executing software. The operator halts program execution
in the attached processor, invalidates a BTB entry in the attached processor,
restarts the attached processor, and returns to local console mode.
N

! Enter forwarding console
!
mode and send subsequent
!
commands to node 4.

¥ (ESC) (CTRUP)

! Halt the node-4 processor.

! The attached processor halts
PC =

Q@020700

»))Ds1 3A @Rl1a35@0

at physical address 0000 0700.

! Invalidate
a BTB entry in
the attached processor.
See Appendix F.

!
!

! Restart the attached processor
where it left off.

Y ¥ W(CTRLP)

! Return to local console
!

Example 4-7:

mode on the primary processor.

Logical Console Dialog Displayed on the Terminal

When software executing on the primary processor performs the same logical

console functions, the Z and (ESC) commands are unnecessary. Example 4-8
shows the sequence of commands that the software should send, one character at a time, to the attached processor’s RXCD Register, using MTPR
instructions.

Console Functions

4-21

! The CTRL/P character halts
! the attached processor.

{(CTRL/F}
|

! Invalidate a BTB entry in

DsI 3A 2@1233R{RET>

the attached processor.

! Restart the attached processor

C{(RET?

where it left off.

Example 4-8: Primary Processor Software Performs Logical
|

Console Functions

Software can access the RXCD Register on the attached processor at address

bb + 200, where bb is the base address of the node.

In response to the CTRL/P command, console mlcrocodein the attached processor echoes the command and sends
702
33)

FC = RAQRTR0

to the RXCD Register on the primary processor. In response to the D/I command, console microcode in the attached processor merely echoes the com-

mand and sends the prompt symbol. Software in the primary processor must

wait till it receives the console prompt before sending the next command.

4-22

Console Functions

Chapter 5
Handling Exceptions and Interrupts

The KA820 processor implements exceptions and interrupts according to
VAX architecture specifications (see the VAX Architecture Handbook). Some
exceptions and interrupts are specific to the KA820 processor and systems
that use the VAXBI bus, while others are standard on all VAX processors.
KA820 microcode, or another node on the VAXBI bus, or software can signal
an event that requires attention, by generating an exception vector or an interrupt vector. The vector identifies a memory location containing a pointer.
The pointer in turn locates a software service routine that can handle the

event requiring attention. The microcode deals with any exception immedi-

ately by transferring control to an appropriate exception handler, but it defers each interrupt until the priority level of the current process drops below
the priority level of the interrupt.

An exception occurs synchronously with respect to the process currently running; it often results from a condition caused by execution of a specific VAX
instruction. Exceptions are generally repeatable, so that if a program generating an exception is run again, the exception occurs again at exactly the
same point.

Traps, faults, and aborts are the three kinds of exceptions:

1. A trap exception occurs at the end of a VAX instruction, leaving the registers and memory in a consistent state. Integer-overflow is an example.

2. A fault exception occurs during execution of a VAX instruction, but it also
leaves the registers and memory in a consistent state. Translation-notvalid is an example.

3. An abort exception occurs during execution of a VAX instruction in response to a serious system failure, leaving the registers and memory in an
unpredictable state. Machine check is an example. Most exceptions leave

the interrupt priority level at IPL 0. Machine-check and kernel-stack-not-

valid exceptions, however, require the highest priority (they require immediate attention with no interruptions) and therefore raise the IPL to 1F
(hex).

An interrupt occurs asynchronously with respect to the process currently
running. Completion of an I/O function and power failure are examples of
“events that interrupt normal process execution. Microcode assigns an interrupt priority level for each interrupt vector. Software generated interrupts
use the lowest 15 interrupt priority levels (1 to F hex). Hardware and micro-

5-1

code generated interrupts take the high interrupt priority levels (10 to 1F
hex). VAXBI nodes can use four interrupt levels (BI INTR4 to BI INTR7), cor-

responding to IPL 14 to IPL 17. Table 5-1 lists the types of interrupts and
‘exceptions and the corresponding interrupt priority levels.

Table 5-1:

Interrupt Priority Levels on the KA820 Module

Interrupt

Priority

Level (hex)

Interrupt or Exception Source Type

Software
»

Machine-check exception

Kernel-stack-not-valid exception
Power-up microcode
1E

BI AC LO L becomes true

1Dto 1B

Not used

Corrected read data (CRD)

19 and 18

Not used

BI INTR7

BI INTR6

ICCS Interval Timer

BI INTR5

BI INTR4

RXCD
IPINTR

RCX50

Serial-line unit 0
Serial-line unit 1
Serial-line unit 2
Serial-line unit 3
13 to 10

Not used

Ftol

Software interrupt levels 15 to 1 (decimal)

In cases where two or more interrupts occur at the same level, priority follows

the order shown in Table 5-1. For example, BI INTR4 and serial-line unit O
both use IPL 14, but BIINTR4 takes precedence. When microcode responds to
an interrupt, it sets the IPL shown in the table to block subsequent interrupts

at or below that level until the handler for the interrupt is finished.
NOTE

Software can mask interrupts by writing a value specifying an in-

terrupt level to the Interrupt Priority Level Register IPR 12 hex)
with the MTPR instruction. Interrupts with levels at or below the

5-2

Handling Exceptions and Interrupts

value written are masked. The value 1F (hex) masks all interrupts
with the exception of interrupts for the RXCD Register and serial-

line unit 0. Microcode reschedules the RXCD Register and serialline unit 0 interrupts at IPL 14.

Operating system software includes routines that handle exceptions and interrupts. If you do not use a standard operating system, you must supply your
own exception and interrupt condition handlers.

5.1

System Control Block
KA820 microcode and system software cooperate to maintain the system con-

trol block, a structure made up of two or more pages of vectors, each begin-

ning on a page boundary. The System Control Block Base Register (IPR 11
hex) points to the first vector in the block, vector 0. The vectors in the system

control block are offsets from the base address.
Microcode on the KA820 module defines the first half page of vectors (0 to FC
hex). Software defines the vectors from 100 to 3FFC (hex). The VMS operating system software for the KA820 module assigns the vectors from 100 to
1FC (hex) to native VAXBI devices, by node number, leaving vectors 200

through 3FFC (hex) available for I/O controllers and devices. Table 5-2 lists
the vector assignments in the system control block. A dash (—) means that

Table 5-2:

System Control Block Vector Assignments on the KA820

Module

‘

microcode leaves the interrupt priority level unchanged.

Interrupt

Vector

Exception

Priority

Level

(hex)

Function

Interrupt

(hex)

UNIBUS or VAXBI passive release

Interrupt

14 to 27

Machine-check abort

Exception

Kernel-stack-not-valid abort

Exception

Power fail

Interrupt

Reserved or privileged instruction fault

Exception

—

XFC instruction fault (customer reserved

Exception

—

instruction; user microcode is not sup-

ported on the KA820)
18

Reserved operand fault or abort

Exception

—

Reserved addressing mode fault

Exception

—

Access-control-violation fault

- Exception

—

Translation-not-valid fault

Exception

—

Trace-pending fault

Exception

—

Breakpoint fault

Exception

—

(Continued on next page)

Handling Exceptions and Interrupts

5-3

Table 5-2:

System Control Block Vector Assignments on the KA820
Module (Cont.)

|
Interrupt

Function

Exception
or
Interrupt

Priority
Level
(hex)

Reserved to DIGITAL

—

Arithmetic trap or fault

Exception

—

38, 3C

Reserved to DIGITAL

—

CHMK instruction trap (change mode to
kernel)
|

Exception

—

CHME instruction trap (change mode to

Exception

—

CHMS instruction trap (change mode to

Exception

—

Exception

—

Vector
(hex)

44
48

executive)

supervisor)

CHMU instruction trap (change mode to
user)

VAXBI bus error

Interrupt

Corrected read data (CRD)

Enterrupt

RXCD

Interrupt

5C to 7C

Reserved to DIGITAL

—

Interprocessor interrupt

Interrupt 14

84 to BC

Software interrupt

Intérrupt

1to F

Interval timer

Interrupt

Reserved to DIGITAL

Interrupt

Serial-line unit 1 receive

Interrupt

CcC

Serial-line unit 1 transmit

Interrupt

Serial-line unit 2 receive

Interrupt

Serial-line unit 2 transmit

Interrupt

Serial-line unit 2 receive

Interrupt

Serial-line unit 3 transmit

Interrlipt

EOto EC

Reserved to DIGITAL

—

RCX50 interface

Interrupt

Reserved to DIGITAL

—

Console terminal receive

Interrupt

Console terminal transmit

Interrupt

14 to 17

100 to SFFC Vectors are defined and loaded by software

5-4

Handling Exceptions and Interrupts

NOTES
KAB820 microcode checks the values of interrupt vectors coming

from the VAXBI bus. It remaps to vector 50 any vector in the range
of 4 to 4C (hex) received from another VAXBI node. In this way the
processor detects invalid vectors from VAXBI nodes; VAXBI node

interrupt vectors should be 100 or above.

The KA820 module uses vector 0 for the passive release function.
When microcode responds to a VAXBI interrupt with an IDENT
transaction, the interrupting node can reply with vector 0 if the con-

dition requiring the interrupt has passed. In addition, microcode
generates vector 0 if there is a NO ACK confirmation in response to

a KA820-generated IDENT transaction. System software must.supply condition handling macrocode corresponding to vector 0, but

little action is required. The condition handler can simply add 1
to a counter and return to the interrupted process with an REI

instruction.

Machine-Check Exceptions
The KA820 module responds to nine kinds of hardware and mlcrocode related

BTB tag parity errors

BTB data parity errors

Ok~

Cache data parity errors
VAXBI node or transaction errors

MIB bus parity errors

Unforeseen microcode situations

©®

errors as machine-check conditions:

Interrupts with unexpected interrupt priority levels

5.2

Po\rt controller timeout

Cache tag parity errors

When KA820 microcode discovers a machine-check error condition, it immediately aborts the current process and raises the interrupt priority level to 1F
(hex) to mask all interrupts. Microcode then takes the following action:

1. Set the hardware-fault state flag to prevent the microcode from detecting
other errors until it has dealt with this one. The hardware-fault state flag
lights the two red LEDs on the module. Note that this flag1s inaccessible

to software.

2. Set the machine-check condition flag. If the flag is already set, this is a
double error. Microcode halts the processor and enters the console mode (if
enabled).

Handling Exceptions and Interrupts

5-5

3. Push on the stack error information from internal registersin the M chip.
The informationis then available to the software.

4. Clear the hardware-fault state flag and turn off the two red LEDs on the
module.

5. Pass control to the machine-check exception condition handler at the address specified by vector 4.

The condition handler must evaluate the information on the stack and then
either attempt to recover from the error or halt the processor. If there is any
chance of producing catastrophic results, such as corrupting the data base or
producing wrong answers, software should execute the HALT instruction. If
the condition handler does try to recover, it should take the following steps:
1. Restore the machine state as required.

2. Write (any value will do) to the MCESR Register (IPR 26 hex) to clear the

machine-check condition flag. If the condition handler performs this instruction too soon, occurrence of a second machine-check error will cause
the microcode and the condition handler to loop, unable to halt in response
to the double error.

Table 5-3:

Machine-Check Stack
Appropriate

Console
Examine

Command

Location

Corresponding M

Following CPU

in Memory
(hex)

|
Data Available

Chip Internal
Register

Double-Error
Halt

(SP)

Byte count on stack

—

none

(SP) + 8

Parameter 1

MTEMPB Register

E/M B

(SP) + C

Virtual Address

MTEMP13 Register

E/M 13
none

Virtual Address Prime

MTEMPPSL.TEMP

(SP) + 14

_Meinory Address

MTEMP9 Register

E/M 9

(SP) + 18

Status word

MTEMPC Register

E/M C

(SP) + 1C

PC at failure

MTEMPF Register

=~ EMF

(SP) + 20

Microcode PC at

MTEMP10 Register

E/M 10
E/GF

(SP) + 10

failure

5-6

(SP) + 24

Current PC

—

SP) + 28

Current PSL

Handling Exceptions and Interrupts

313029

23222120

16151413

543210

RESERVED TO
DIGITAL
VAX CAN‘T RETRY

RESERVED TO DIGITAL
VAXBI

ERROR

WRITE MEMORY

VAXBI EVENT CODE
RESERVED TO DIGITAL

BTB OR CACHE DATA PARITY ERROR

RESERVED TO DIGITAL

BTB TAG PARITY ERROR

MTB MISS
CACHE TAG PARITY ERROR

PORT CONTROLLER DETECTED ERROR

MEMORY ADDRESS REGISTER LOCK
MLO-402-85

Figure 5-1: Machine-Check Status Word Bit Layout

3. Execute an REI (Return from Exception or Interrupt) instruction to give
control back to the process that was interrupted. Note that if the machinecheck exception indicates an MIB bus parity error, the REI instruction mi-

crocode may be unable to identify the process to which control should
return.

4. Check and clear all VAXBI node Bus Error Registers.

5.2.1

Machine-Check Stack

Machine-check microcode pushes eleven longwords on the stack. Eight of
these are copies of internal registers in the M chip. This information serves as
a snapshot of the machine state at the time of error detection.

9.2.1.1

Byte Count, (SP) — This is the first entry on the machine-check stack.

It tells how many bytes are on the stack for this error (20 hex). Note, however,

that the current PC and current PSL are not included in this byte count, even
though they are pushed on the stack.

Handling Exceptions and Interrupts

o-7

5.2.1.2 Parameter 1, (SP) + 8, MTEMPB Register — On detection of a BTB tag
parity error or cache tag parity error, microcode loads the parameter 1
longword with the corresponding tag.

5.2.1.3 Virtual Address Register, (SP) + C, MTEMP13 Register — This points to
a virtual address that may be related to the machine-check error.
5.2.1.4

Virtual Address Prime Register, (SP) + 10, MTEMP.PSL.TEMP Register —

Like the Virtual Address Register, this points to a virtual address that may

be related to the machine-check error. This information is unavailable following a CPU double-error halt.

5.2.1.5 Memory Address Register, (SP) + 14, MTEMP9 Register — This points to
a physical address that may be related to the machine-check error.

5.2.1.6 Status Word, (SP) + 18, MTEMPC Register — The machine-check status
word often contains the most useful error information available to condition
handler software. The hardware copies bits (22:16, 14) from the corresponding bits in the PCntl CSR. Figure 5-1 shows the bit configuration.

e Bit ¢(30) VAX Can’t Retry (VCR) — Microcode sets or clears this flag to tell
the exception condition handler whether to restart the VAX instruction
that the saved program counter ((SP) + 1C) points to. Microcode clears the
VCR flag at the beginning of each instruction and at the resumption of
each interrupted instruction when the first-part-done (FPD) flag is set in
the processor status longword. Microcode sets the VCR flag in response to
any of three conditions:

— Reference to an address in I/O space
— A successful write transaction to memory

— A successful write transaction to a general purpose register

The VCR flag may be incorrect for cache data parity errors and BTB data
parity errors, for some VAXBI errors, and for errors that occur with the
FPD flag set. You can retry an instruction associated with a VAXBI error if
accurate address information is available on the stack. Note, however, that
when a machine-check exception occurs on a write transaction to memory,
the address information saved on the stack is invalid.

If the exception condition handler decides not to retry the failing VAX instruction, it can take one of two steps:

Log out the current process if the failing instruction belongs to a process running in the user mode or the supervisor mode.

Execute a HALT instruction if the failing instruction belongs to a process running in the executive mode or the kernel mode.

The execution of HALT may trigger a restart (warm start).

5-8

Handling Exceptions and Interrupts

Bit (22) VAXBI Error — When the port controller detects a VAXBI error, it
sets this flag, locking the write-memory flag, bit (21), and the VAXBI

event code, bits (20:16). Therefore, whenever status word bit (22) is set,
bits (21:16) are valid and pertinent. After handling the error, the exception condition handler should clear bit (22) in the PCntl CSR to unlock the

write-memory flag and VAXBI event code bits, PCntl CSR bits (21:16).
Bit (21) Write Memory — The port controller sets this flag when the
KAB820 module writes to memory. If status word bits (22) and (21) are

both set, the machine-check condition is the result of a VAXBI writememory error.

Bits (20:16) VAXBI Event Code — When status word bit (22) is set, these

~ five bits form a code that defines the VAXBI transaction that preceded de-

tection of the error. The Memory Address Register points to the physical
address that failed, unless the KA820 module was performing a write
transaction on the VAXBI bus.

When bit (22) is clear, the VAXBI event code is not useful error information, because it reflects whatever is happening on the VAXBI bus at the
moment. Table 54 lists the 32 VAXBI event codes and their meanings.
Bit (14) BTB or Cache Data Parity Error — When microcode reads the

cache or BTB, the port controller checks the parity of the data. If the port

controller detects an error,
it sets status word bit (14). No other information describing cache and BTB data parity errors is available.
Bit (12) Port Controller Timeout Error — The port controller starts a

timer when it receives a command from the CPU to perform a VAXBI
transaction. If the transaction has not been completed 12.8 milliseconds
later, the port controller sets this bit.

Bit (4) BTB Tag Parity Error — The microcode has detected a parity error
while reading a BTB tag entry.

Bit (3) MTB Miss— A miss in the MTB has caused the mlcrocode to read
the BTB. This informationis useful to self-test microcode.

Bit (2) Cache Tag Parity Error — The microcode has detected a parity error while reading a cache tag entry.

Bit (1) Port Controller Detected Error — When this flag is set, it indicates
that the port controller detected the error that produced the machine-check
condition. Status word bits ¢(22:16) and bit (14), copied from the corresponding bitsin the PCntl CSR, are valid and pertinent.

Bit <0) Memory Address Register Locked — When the Memory Address
- Register is locked, status word bits (22:1) are valid. The contents of the
Memory Address Register are not valid, however, unless bit (21) is clear,
indicating that the error did not occur during a memory write transaction.

Handling Exceptions and Interrupts

5-9

Table 5-4: VAXBI Event Codes: Status Word Bits (20:16)
Code

Event

(hex)
WO

No event (NEV)

Master Port Transaction Complete (MCP)
~ ACK received for Slave Read Data (AKRSD)

Bus Timeout (BTO); the VAXBI Error bit is set (status word bit
|

RETRY CNF Received for Master Port Command (RCR)

Internal Register Written (IRW)
Advanced RETRY CNF Received (ARCR)

(22))

Self-Test Passed (STP)

NO ACK or Illegal CNF Received for INTR command (NICI)
NO ACK or Illegal CNF Received for Force-Bit IPINTR/STOP

HEHOQW
R

Command (NICIPS)

ACK CNF Received for Error Vector (AKRE)
-

IDENT ARB Lost (IAL)

External Vector Selected — Level 4 (EVS4)
External Vector Selected — Level 5 (EVS5)
External Vector Selected — Level 6 (EVS6)
External Vector Selected — Level 7 (EVS7)
Stall Timeout on Slave Transaction (STO)
Bad Parity Received During Slave Transaction (BPS)
Illegal CNF received for slave data (ICRSD)
Bus Busy Error (BBE)

ACK CNF Received for Non-Error Vector at Level 4 (AKRNE4)
ACK CNF Received for Non-Error Vector at Level 5 (AKRNES)
ACK CNF Received for Non-Error Vector at Level 6 (AKRNEG6)
ACK CNF Received for Non-Error Vector at Level 7 (AKRNET7)
Read Data Substitute or RESERVED Status Code Received
(RDSR). The KA820 module has attempted a VAXBI memory
read transaction and failed. The responding memory node has
returned data with two or more wrong bits, because the error is
19

uncorrectable. VAXBI Error, status word bit (22), is set.
Illegal CNF Received for Master Port Command (ICRMC). The
KA820 module has received an illegal confirmation code in
response to a VAXBI command. VAXBI Error, status word bit
(22), is set.

NO ACK CNF Received for Master Port Command (NCRMC). The
KA820 module has received a NO ACK response to a command.
Reference to a nonexistent memory location or an invalid I/O
space may have caused the error. VAXBI Error, status word bit
(22), 1s set.

Bad Parity Received (BPR). This gives advance indication that a
master or slave parity error has occured.

Illegal CNF Received by Master Port for Data Cycle ICRMD). The
KA820 module has received an illegal confirmation code in
response to a VAXBI command. VAXBI Error, status word bit
(22), 1s set.

(Continued on next page)

5-10

Handling EXceptions and Interrupts

Table 5-4:

VAXBI Event Codes: Status Word Bits (20:16) (Cont.)

Code
(hex)

Event

Retry Timeout (RTO). The KA820 module has retried a transaction

4096 times consecutively without success. VAXBI Error, status
word bit (22), is set.
1E

Bad Parity Received During Master Port Transaction (BPM). While

it was the VAXBI master, the KA820 module detected bad parity

on the bus. VAXBI Error, status word bit (22), is set.
1F

Master Transmit Check Error MTCE). The KA820 module was the

only driver on the VAXBI bus when it detected data on the bus
that did not match the data sent. VAXBI Error, status word bit
(22), is set.

5.2.1.7

Program Counter at Failure, (SP) + 1C — Microcode saves the contents

of the program counter here at the moment when it detects a machine-

check error. This address may point to the middle of a partially executed
instruction.
5.2.1.8

MicroPC at Failure, (SP) + 20 (hex) — This identifies the address of the

next microinstruction at the time of error detection. This information is not

useful on a memory write transaction error.
5.2.1.9

Current Program Counter, (SP) + 24 (hex) — This longword points to

the beginning of the VAX instruction that was executing at the time of the
failure. If the software performs an REI instruction to retry the instruction

that failed, program execution resumes at this address.

5.2.1.10

Current Processor Status Longword, (SP) + 28 (hex) — The PSL is use-

ful to the condition handler because it defines the status of the process that
was executing at the time of the machine check. The first part done flag

(FPD), bit (27), may be especially relevant.
If the FPD flag is clear, repeating the instruction should produce the correct
result. If the FPD flag is set, execution can resume in the middle of the instruction, since microcode has packed up the partially executed instruction.

However, if the exception results from an MIB parity error, the microcode
state 1s incomplete, and execution of the instruction may produce another

error, regardless of the state of the FPD flag.

5.3

CPU Double-Error Halt Considerations
When microcode responds to an error condition, it sets the machine-check
condition flag. If another machine-check error occurs before a macrocode
machine-check handler resets this flag with an MTPR to MCESR instruction,

then machine-check microcode transfers control to the CPU double-error halt
handling microcode. The KA820 module then enters the console mode (if enabled), displays the CPU double-error halt code (?05), and leaves the controlpanel RUN light off.

Handling Exceptions and Interrupts

5-11

Microcode does not push error information on the stack for a CPU double error, and any information on the stack may be invalid. However, the console
Examine command gives you access to most of the same information, in case
you want to analyze the error.

Use the console command:
YWYEsM (M chip address?

to read parameter 1, the Virtual Address Register, the Memory Address Register, the status word, the Program Counter at failure, and the micro-PC at
failure in the M chip registers. Table 5-3 lists the appropriate console Examine commands.

Use the console command:
YYE/G F

to read the current Program Counter.
Use the console command:
YMHEF

to read the current Processor Status Longword.

When you no longer need to save the failing machine state, you can further
isolate a hardware error by running self-test.

5.4

Power-Up and Console Mode Errors
An error that normally causes a machine-check exception can occur while the
KA820 module is performing power-up or console functions. For example,
system initialization microcode may detect an invalid confirmation code on
the VAXBI bus as a response to a KA820 command. A memory node may respond with read data substitute (RDS) instead of the data required in a console examine command. Or the console operator can cause an error by trying
to examine a nonexistent memory location.

Since there may be no condition handling software and no system control
block set up in memory, microcode cannot deal with these errors in the nor-

mal way. Microcode sets an internal error-state flag in such situations, to prevent the machine-check exception microcode from taking control. Whenever
this flag is set, control passes to the console microcode, which attempts to
display an error message (generally ?4C) on the console terminal.

5-12

Handling Exceptions and Interrupts

Chapter 6
Dedicated I/0 and Memory Devices

The KA820 module incorporates four dedicated I/O devices and two dedicated

memory devices on the module, and it connects directly to two off-module I/O
devices. This chapter tells what you need to know about each device to write

driver software that controls it.

Four serial-line units implemented with four UARTS (UARTO, 1, 2, 3) in the
M chip make the KA820 module directly accessible to terminals and modems.
Using the serial-line units you can connect up to four terminals directly to the

KA820 module without using a VAXBI slot for a communications device.
UARTO, on serial-line unit 0, connects to the console device (normally a hard-

copy terminal).

The PCI bus connects the port controller with two on-board devices: the
~

EEPROM and boot RAM; and it runs off the module to connect with the watch

chip and the RCX50 diskette controller. Addresses for these devices lie within

the VAXBI node private space. They are accessible only to the local KA820
module, so other VAXBI nodes cannot read or write them.
The PCI bus is a 16-bit asynchronous bus that multiplexes data and ad-

dresses. Although the bus carries data on all 16 bits, only bits (14:1) are

available for addresses. Address bit {0) is unused. Data in the EEPROM,

RCX50 controller, and watch chip is accessible one byte at a time. Data in the

boot RAM is accessible with any standard VAX instruction length. Table 6-1
shows the range of addresses assigned to each PCI bus device.

Table 6-1: PCI Device Addresses and Accessibility
|

Address

- Appropriate

Data Length for

Move
Instructions

(hex)

Device

Access

2009 0000

Boot RAM

Longword oriented

MOVB, MOVW,

on longword boundaries

MOVL, MOVQ,

(read or write masked)

MOVO, MOVC

to
2009

1FFE

2009 8000

EEPROM

Byte oriented on
|

word boundaries

MOVB, MOVW
|

2009 FFFE

200B 00XX

200B 80XX

RCX50 controller

Byte oriented on

MOVB, MOVW

word boundaries

Byte oriented on

MOVB, MOVW

Watch chip

word boundaries

The byte-oriented devices (EEPROM, watch chip, and RCX50 controller) use
only even addresses. For example, the first four bytes for each device are accessible at offsets 0, 2, 4, and 6 from the base address. All read and write
transfers occur on word boundaries. Software must use either byte-length instructions, such as MOVB, or word-length instructions, such as MOVW, to
read and write the byte-oriented devices. However, for byte-length instructions, the autoincrement and autodecrement addressing modes will not work
properly, because they access each byte location twice. Word-length instructions move two bytes of data, but only the low byte is valid. When address bit
(1) is 1, valid data is in byte 2 on the DAL bus; when address bit (1) 1s O,
valid data is in byte 0 on the DAL bus. Microcode realigns the DAL data to
ensure that the valid data is in the low byte. Autoincrement and autodecrement addressing modes work properly for word-length instructions, accessing even locations on the byte-oriented devices. However, the upper byte in
each transfer is invalid.
|
-

Microcode moves data to and from the boot RAM in longwords, but it masks

the data according to the instruction. Therefore, data transfer instructions
can use any data length at any address, and microcode implementing the instructions moves only the data specified to or from the address specified.
NOTE

Serial-line units, the RCX50 controller, and the watch chip are accessible only to the KA820 module used as the primary processor.

6.1

Serial-Line Units
Each of the four serial-line units is implemented in a UART in the M chip,

and each UART makes four privileged processor registers available to software.

Receive CSR

Receive data buffer
Transmit CSR
Transmit data buffer

The serial-line units are full duplex, so they can transmit and receive data
simultaneously. When interrupts are enabled, character transfer occurs one
byte at a time, and each serial-line unit interrupts the processor at IPL 14
(hex) every time it receives or transmits a character.

To service an interrupt, interrupt handling microcode passes control to a soft-

ware device driver identified by a vector in the system control block. Software
can read and write the UART registers with MFPR and MTPR instructions.
Table 6-2 lists the IPR addresses and functions of the four registers for each
of the four serial-line units.

6-2

Dedicated I/O and Memory Devices

Table 6-2:

Serial-Line Unit Registers

IPR #
(hex)

Function

Serial-Line
Unit

SCB
Vector

RXCS

Console Receive CSR

UARTO

'F8

RXDB

Console Receive Data Buffer

UARTO

—

TXCS

Console Transmit CSR

UARTO

TXDB

Console Transmit Data Buffer

UARTO

—

RXCS1

Serial-Line Unit 1 Receive CSR

UART1

RXDB1

Serial-Line Unit 1

UART1

—

TXCS1

UART1

Serial-Line Unit 1

UART1

Serial-Line Unit 2

UART?2

Serial-Line Unit 2

UART?2

—

Serial-Line Unit 2

UART2

Serial-Line Unit 2

UART2

—

Serial-Line Unit 3

UARTS3

—

UART3

UARTS3

—

Receive Data Buffer

Serial-Line Unit 1
Transmit CSR

TSDB1

RXCS2

RXDB2

TXCS2

TXDB2

RXCS3

Transmit Data Buffer

Receive CSR

Receive Data Buffer

Transmit CSR

Transmit Data Buffer

Receive CSR

RXDB3

Serial-Line Unit 3
Receive Data Buffer

TXCS3

Serial-Line Unit 3
Transmit CSR

TXDB3

Serial-Line Unit 3
Transmit Data Buffer

6.1.1

Receive Control and Status Registers (Read/Write)

" RXCS IPR 20 Vector F8
RXCS1 IPR 50 Vector C8
RXCS2 IPR 54 Vector DO

RXCS3 IPR 58 Vector D8

Dedicated /0 and Memory Devices 6-3

by writing to the RXCS
Software can control two serial-line unit functions
Registers:

1. Enable or disable recéive interrupts from the serial-line unit.

2. Enable or disable the diagnbstié loopback function on the serial-line unit.
Software can check three serial-line unit functions by reading these reg|
|
isters:

1. Check whether a character has been received in the receive data buffer of
o

the serial-line unit.

2. Check whether receive interrupts are enabled or disabled for the serial|

line unit.

3. Check whether the loopback function is enabled or disabled for the serialline unit.
|
|

131211

87 65

RESERVED TO DIGITAL
LP

RESERVED TO DIGITAL

DON
[E

RESERVED TO DIGITAL
ML0-403-85

Figure 6-1: Receive CSR Bit Format
6.1.1.1 Bit (12) LP (Loopback Enable, Read/Write) — Diagnostic software can
- set this bit by writing 1 to it as an aid in testing the serial-line unit. The
loopback function changes the input so that it arrives at the receive data

buffer from the loopback bus instead of the external serial line.

Software must also set the loopback bit in one of the four transmit CSRs to
make use of the loopback function. All four serial-line units can have RXCS
loopback bits set at once.

Power-up initialization microcode clears the loopback bit.

6.1.1.2 Bit (7) DON (Done, Read Only) — The serial-line unit sets this bit

when it finishes receiving a character in the receive data buffer. If the interrupt enable bit is set, DON interrupts the CPU at IPL 14 (hex).

6-4 Dedicated IO and Memory Devices

When software responds to the interrupt by reading the associated Receive

Data Buffer Register with an MFPR instruction, MFPR microcode clears the
DON bit.

Power-up initialization microcode clears the DON bit.
6.1.1.3

Bit (6) Interrupt Enable (Read/Write) — Software can set (write 1) or

clear (write 0) this bit to enable or disable receive interrupts.

Power-up initialization microcode clears the interrupt enable bit. Microcode

sets the bit for serial-line unit 0 when entering console mode.

6.1.2 Receive Data Buffer Registers (Read Only)
RXDB IPR 21
RXDB1 IPR 51

RXDB2 IPR 55
RXDB3 IPR 59

Receive Data Buffer Registers provide eight data bits (enough for one character) and two status bits. Power-up initialization microcode clears the regis-

ters. After software reads an RXDB register with an MFPR instruction,
microcode clears the register automatically.

16151413

RESERVED TO DIGITAL
ERR

BRK

RESERVED TO DIGITAL
DATA
MLO-404-85

Figure 6-2:

6.1.2.1

Receive Data Buffer Register Format

Bit (15) ERR (Error on Received Character, Read Only) — Hardware

‘sets this bit when it detects an overrun or framing error in the received data.
6.1.2.2

Bit (14) BRK (Break, Read Only) — Hardware sets this bit when it de-

tects the 0 state on the serial line for longer than the transmission time for

one character at the current baud rate.

Dedicated I/O and Memory Devices

6-5

6.1.2.3 Bits (7:0) DATA (Received Data, Read Only) — The serial-line unit
|
|
stores received data in this field.

6.1.3

Transmit Control and Status Registers (Read/Write)

TXCS IPR 22 Vector FC

TXCS1 IPR 52 Vector CC
TXCS2 IPR 56 Vector D4

TXCS3 IPR 5A Vector DC

Software can write to these registers with MTPR instructions to:
1. Enable or disable the loopback function.

2. Start or end transmission of a break.

3. Change the baud rate for the serial-line unit.

4. Enable or disable transmit interrupts from the serial-line unit.

Software can check two serial-line unit functions by reading these registers
with MFPR instructions:

1. Check whether the serial-line unit has finished transmitting a character.
2. Check whether transmit interrupts are enabled.
14131211

731

9 8 7 6 5

RESERVED TO DIGITAL
LP

BRK

BAUD RATE

BAUD RATE ENABLE
RDY
|E

RESERVED TO DIGITAL
MLO-405-85

Figure 6-3: Transmit Control Status Register Format

6-6

Dedicated I/O and Memory Devices

6.1.3.1

Bit (13) LP (Loopback, Write Only) — Diagnostic software

sets this bit

by writing 1 to it as an aid in testing the serial-line unit. The loopback
tion changes the serial-line unit output from the external line

func-

to the Receive
Data Buffer. The loopback bit in one of the four serial-line unit
receive CSRs
must be set to complete the loop. Software should not set the Transmit
Loopback bit for more than one serial-line unit at one time.

Power-up initialization microcode clears the Transmit Loopbac

k bit.

6.1.3.2

Bit (12) BRK (Break, Write Only) — Software can start transmit

break by writing 1 to this bit. The serial-line unit transmits the

ting a

break signal

for at least the transmission time of one character and continue

s to transmit

break until software writes the bit with 0.

Power-up initialization microcode clears the Break bit.
6.1.3.3

Bits (11:9) Baud Rate (Write Only) — Power-up initialization
micro-

code sets the transmit and receive baud rate for serial-line units
1200. It sets the baud rate for serial-line unit 0, the console

rate specified in the EEPROM (see Table 4-4 in Chapter 4).

1,2,and 3 to

line, to the baud

Software or the console operator can set a new baud rate for sending

receiving data by writing a 3-bit value in bits (11:9) and at

and

the same time

writing 1 to bit (8), the baud rate enable bit. Table 6-3 shows
the value corresponding to each available baud rate.
6.1.3.4

Bit (8) BRE (Baud Rate Enable, Write Only) — Software
should

this bit with 1 when it sets the baud rate for a serial-line unit.

Table 6-3:

write

Setting the Baud Rate for a Serial-Line Unit

Binary Value in Transmit CSR

Bits (11:9)

Baud Rate (Decimal)

000

150

001

300

010

600

011

1200

100

101

110
111

2400
‘

4800

9600
-

19200

Dedicated I/O and Memory Devices

6-7

6.1.3.5 Bit (7) RDY (Ready, Read Only) — A serial-line unit sets this bit when |

it is ready to transmit a character. This happens when the transmit data
buffer field is empty and can accept another character for transmission. If the
interrupt enable bit is also set, the serial-line unit interrupts the processor at

{

IPL 14 (hex).

When RDY is 0, the serial-line unit is still in the process of transmitting a
character.

6.1.3.6 Bit (6) IE (Interrupt Enable, Read/Write) — Software can enable or disable transmit interrupts by writing 1 or O to this bit.

Powef—up initialization microcode clears the interrupt enable bit to disable

transmit interrupts. Microcode sets the bit for serial-line unit 0 when entéering console mode.

6.1.4

Transmit Data Buffer Registers (Write Only)

TXDB IPR 23

(

TXDB1 IPE 53

TXDB2 IPE 57

TXDBS3 IPE 5B

Software can transmit data on any of the four serial-line units, one byte at a
time, by writing data in the low order byte of the Transmit Data Buffer Regis-

ter, when the IE and RDY bits in the corresponding TXCS Register are set.

The Transmit Data Buffer Register for serial-line unit 0, the console line, differs from the other Transmit Data Buffer Registers because it includes an
extra 4-bit field to indicate whether the informationin the low byteis data or
a console command.

Figure 6—4 shows the format for the Transmit Data Buffer Registers for |
serial-line units 1, 2, and 3.

8 7

RESERVED TO DIGITAL
DATA
MLO-406-85

Figure 6-4: Serial-Line Units 1, 2, and 3 Transmit Data Buffer
(TXDB1, 2, 3) Format

6-8

Dedicated I/O and Memory Devices

Figure 6-5 shows the format for the Transmit Data Buffer Register for serial-

line unit 0.

1211

RESERVED TO DIGITAL
ID
DATA

MLO-407-85

Figure 6-5:
6.1.4.1

Serial-Line Unit 0 Transmit Data Buffer (TXDB) Format’

Bits (11:8) of TXDB (ID Field, Write Only) — Software must write F

(hex) to this field when it uses this register to send a command to the console

microcode. When software writes 0 to this field, serial-line unit 0 transmits
the data in the low byte on the serial line.
|

6.1.4.2

Bits (7:0) of TXDB, (Command or Transmit Data, Write Only) — When

the accompanying ID field is 0, hardware transmits the data that software

writes in bits (7:0) on serial-line unit 0.

When the ID field is F (hex), console microcode interprets the data in bits
(7:0) as follows:

2 = Restart the system.
3 = Clear the (warm) restart-in-progress flag in the M chip.

4 = Clear the (cold) bootstrap-in-progress flag in the M chip.

Bootstrap code and restart routines should write 0000 OF03 and then
0000 OF04 (hex) to TXDB to clear the restart
-1n-progress and bootstrap-in-

progress flagsin the M chip.

Software can restart the processor by writing 0000 0F02 (hex) to TXDB. In

response, microcode sets the BIRESET bit (PCntl CSR bit (28)), initiating a

power-down/power-up sequence. The action of the KA820 module depends on
the setting of the lower key switch on the control panel (external signal PNL

RSTRT HLT H on module I/O pin D51).
6.1.4.3

Bits (7:0) of TXDB1, 2, and 3 (Transmit Data, Write Only) — The serial-

line transmits the character that software writes in the low byte.

6.2

Using the EEPROM
The EEPROM on the KA820 moduleis a 16K-byte, electrically-erasable, pro-

grammable, read-only memory implementedin two integrated circuits. You
can change the datain the EEPROM, yet the data remains valid when the

power is off. EEPROM data defines:

Dedicated I/O and Memory Devices

6-9

1. Customer choices for KA820 module options

2. VAX bootstrap macrocode that processor initialization microcode copies
into the boot RAM (this macrocode then loads a primary bootstrap routine
into main memory from one of up to ten boot devices)

3. Primary patches that power-up microcode loads into the controlstore RAM

"Table 6-4:

EEPROM Map

Location

Data

First 8K-Byte EEPROM Chip
2009 8000 to 2009 8002

Constants used in the EEPROM test

2009 8004 to 2009 812E

Reserved to DIGITAL

2009 8130 to 2009 813E

8 bytes reserved for users

2009 8140 to 2009 8156

Miscellaneous constants and reserved

2009 8158

VAXBI self-test timeout constant

2009 8160 to 2009 816C

Reserved to DIGITAL

2009 8168 to 2009 816E

VAXBI device type data

2009 8170 to 2009 8174

Unused

12009 8176

RCX50 self-test disable

2009 8178 to 2009 817C

Console data

2009 817E

F chip, BTB, ahd Cache disable

2009 8180 to 2009 81FE

Reserved to DIGITAL

2009 8200 to 2009 87FE

Boot dispatcher

92009 8A00 to 2009 BFFE

Control-store patches and related data

locations

Second 8K-Byte EEPROM Chip
2009 C000 to 2009 COAE

Descriptors for ten boot devices

2009 COBO to 2009 FFFE

Boot code

Appendix H lists the EEPROM contents at the bit level.

You can use any of three methods to read and write data in the EEPROM, one

byte at a time:

1. Privileged software can refer to the EEPROM through node private space
addresses using instructions such as MOVB.

9. EEPROM Utility.

3. Console commands D/E and E/E.

6-10

Dedicated I/O and Memory Devices

Read access to EEPROM locations is unrestricted with methods 1 and 2. How-

ever, you cannot write data to the EEPROM unless the signal PNL ENB WT

EEPROM H on module I/O pin D50 is true (normally determined by the lower

key switch on the control panel).

On a write transfer, the EEPROM latches the address and data and then per- |
forms a 10-millisecond update cycle. If you develop software that writes data

in the EEPROM, use a software timer to ensure that the intervals between
write transfers exceed 10 milliseconds.
The EEPROM options available with the D/E and E/E console commands
occupy part of the first EEPROM chip. They include:

RCX50 controller self-test enable and disable

Console logical node ID selection

Console baud rate selecfion
See Table 4-4 in Chapter 4 for information on console access to these options.
See the VAX 8200 Owner’s Manual for an introduction to the EEPROM

Utility.

Writing data to the EEPROM of an attached processor requires special proce-

dures:

1. Load into main memory VAX code that writes the EEPROM.

2. Cause the attached processor to execute the VAX code that you have

loaded in main memory.

WARNING

Do not use the Z command or the RXCD Registers to write data to
the EEPROM of an attached processor.

6.3

Boot RAM
The boot RAM is an 8K-byte memory dedicated to bootstrap functions. At
boot time the CPU loads boot code from the EEPROM into the boot RAM and
then executes the boot code directly from the boot RAM.

6.4

Using the Watch Chip
The battery-backed-up watch chip keeps the time of year when power is re-

moved from the computer system. On power-up, software can read the time
from the watch chip and set the Time of Day Register (TODR), unless the

power outage has exceeded the limits of the battery. Notice that the TODR

stores time in a 32-bit format and increments the time every 10 milliseconds.
The watch chip, in contrast, stores time in units of seconds, minutes, hours,

days, months, and years and updates the time every second.

Dedicated I/O and Memory Devices

6-11

The watch chip stores time, status, and control information in 8-bit registers.
~ The PCI bus rotates watch chip register addresses and data in a way that is
not transparent to software, as shown in Figure 6-7.

ADDRESS AND DATA

71615141312} 1l0

AT THE WATCH CHIP

ADDRESS AND DATA

SEEN BY SOFTWARE

615]4]13}2|1{0}{7

BIT NUMBER

76543210
MLO-409-85

‘Figure 6-6: Watch Chip Bit Rotation on the PCI Bus

You can access the watch chip registers on word boundaries with MOVB or
MOVW instructions, and the data will always be offset one bit to the left.
Hardware implicitly multiplies read data by 2 and divides write data by 2.
Table 6-5: Watch Chip Registers
Address

Function

200B 8000

Seconds

- 200B 8002

Reserved to DIGITAL

200B 8004

Minutes

200B 8006

Reserved to DIGITAL

200B 8008

Hours

200B 800A

Reserved to DIGITAL

200B 800C

Reserved to DIGITAL

200B 800E

Day of the month

200B 0810

Month

200B 8012

Year

CSR A — BUSY bit

- 200B 8014
200B 8016

CSR B — OFF bit

200B 8018

CSR C — Reserved to DIGITAL

200B 801A

D — VALID bit
CSR

200B 801C to 200B 807E

50 bytes RAM reserved to DIGITAL

6-12 Dedicated I/O and Memory Dévices

Software should therefore divide read data by 2 and multiply data to be
written by 2, as shown in Tables 6-5 and 6-6. Table 6-5 lists the watch chip

registers.

Table 6-6 shows the ranges of values possible for each of the date and time
registers as stored in the watch chip and as read or written by software.

Table 6-6: -Watch Chip Data Interpretation
Hex Range

Decimal
Address

Seen by

Units

Range

~at Chip

200B 8000

Seconds

0—59

00 — 3B

00 — 76

200B 8004

Minutes

0—59

00 — 3B

00 — 76

200B8008

Hours

0— 23

00 — 17

00 — 2F

Day of the

1—31

01 — 1F

02 — 2E

1—-12

01 — 0C

02 — 18

0—99

00 — 63

00 — C6

200B 800E

Hex Range

month

200B 0810

Month

200B 8012

Year

.
.

Software

Table 6-7 shows how your software should interpret a specific date and time
read from the watch chip.

- Table 6-7: Watch Chip Date and Time Sample
-

Watch Chip Output

Data Read by Software

Time

Binary

21 seconds

0001 0101

B 15

0010 1010

58 minutes

0011 1010

0111 0100

5 hours

00000101

0000 1010

15th day

0000 1111

00011110

February

0000 0010

0000 0100

82nd year

0101 0010

1010 0100

Hex

Binary

Hex

The control and status registers on the watch chip let software:

1. Check the validity of the date and time registers
2. Set the time |

3. Stop and start the chip.

Dedicated I/0O and Memory Devices

6-13

In the control and status register descriptions that follow, the bit formats
show the register data already rotated, as the software reads and writes it.
For example, a bit shown as bit 0 is really bit 7 on the watch chip.

6.4.1

Watch Chip CSR A, Address 200B 8014
7

MUST BE ZERO
MUST BE ONE
MUST BE ZERO

BUSY

Figure 6-7:

MLO-410-85

Watch Chip CSR A Format

* Bit (0), BUSY (Read only) —

BUSY = 1: The watch chip is busy with an update cycle;
date and time registers are undefined.

BUSY = 0: The watch chip is not busy;
date and time registers are valid.

Software should check BUSY before reading the date and time registers.
The watch chip sets BUSY for 2 milliseconds every second. If software
finds BUSY set, it should try again in 2 milliseconds.

If BUSY is cleared, software has at least 244 microseconds to read the date

and time registers before the next update cycle. Reading the registers
should take less than 40 microseconds.

e Bits (7:1), Miscellaneous setup bits (Read/write) — Software must write
these bits as shown in Figure 6-8 before it sets the time in the watch chip.

6-14

Dedicated I/O and Memory Devices

Watch Chip CSR B, Address 200B 8016

6.4.2

43210

MUST BE ZERO
MUST BE ONE
MUST BE ONE

MUST BE ZERO
OFF
MLO-411-85

Figure 6-8:

Watch Chip CSR B Format

e Bit (0), OFF (Read/write) — Software must stop the watch ch1p by settmg
OFTF before it loads the date and time reglsters

Software can start the watch chip after setting the time by clearing OFF.
e Bits (7:1), Miscellaneous setup bits (Read/write) — Software must write
these bits as shown in Figure 6-9, when it sets or clears the OFF bit.
6.4.3

Watch Chip CSR C, Address 200B 8018

This register is reserved to DIGITAL.

6.4.4

Watch Chip CSR D, Address 200B 801A

READ AS ZEROS

VALID
MLO-412-856

Figure 6-9: Watch Chip CSR D Format
e Bit (0), VALID (Read only) — The VALID bit tells whether the time represented in the watch chip registers is correct. If the battery backup voltage
falls below the required level, a sensing circuit clears the VALID bit.
-

VALID = 1: Watch chip registers are valid.
VALID = 0: Watch chip registers are invalid.

The watch chip sets VALID to 1 after software reads CSR D. Therefore,

- when software reads VALID as 0, it should immediately update the date
and time registers in the watch chip. The state of the VALID bit will otherwise be misleading.

Dedicated I/0O and Memory Devices

6-15

6.4.5

Bootstrap Software Date and Time Respo nsibilities

Bootstrap software should take the following steps concerning date and time.

(

1. Determine whether the value in the TODR is correct. If the value is correct, skip the remaining five steps. If it is incorrect, go to step 2. Note that
if you set the initial value to a high number,
any lower value must be
wrong.

2. Read the VALID bitin the watch chip CSR D t0 determine Whether the
contents of the watch chip are correct.

3. If VALID is 1, read the BUSY bit in CSR A. If VALID is 0, go to step 6.
4. If BUSYis 0, read the watch Chlp date and time registers, convert the time
to the 32-bit format, and set the TODR
5. If BUSYis 1, wait until
it iis 0 and then go to step 4.
6. If VALID is 0, prompt the operator for the date and time, convert the date

and time to the 32-bit format, and load this valuein the TODR. Then convert the date and time to the Watch chlp register formats and load the

watch chip as follows:

»-

— Write OD (hex) to CSR B to stop the watch chip.
— Initialize CSR A by Writing 40 (hex). (See Figure 6-8.)
— Write the date and time in the appropriate registers.
— Start the watch chip by writing 0C (hex) to CSR B. (See Figure 6-9.)

6.4.6

Compatibility with VMS and ULTRIX

If you write your own system software, you may want your use of the watch

chip to be compatible with that of VMS and ULTRIX-32. These operating sys-

tems always set the year in the watch chip to 1982 (software saves the current
year in a location on disk). If the current year is a leap year, the Day and

Month registers in the watch chip will be ahead by one day, beginning in

(

March.

)

VMS and ULTRIX reset the date and timein the watch chip the first time the
systemis bootstrapped, following 1 January, resetting the Year Register from
1983 to 1982.

NOTE

'VMS uses local standard time; ULTRIX-32 uses Greenwich mean
time.

6.5

Controlling the RCX50 Controller
The RCX50 controller enables software to read and write diskette data one
byte at a time. The controller provides random access to the 800 512-byte

6-16

Dedicated I/O and Memory Devices

|
Q

blocks of data on one side of each diskette. The data side of a diskette contains
80 tracks, and each track contains 10 sectors. Each sector stores 512 bytes of
‘data. Software accesses the data within each sector sequentially, however,
~

beginning with the first byte.

Software communicates with the RCX50 controller by writing and reading

ten 8-bit registers. Some of the registers have several functions. For example,
when software writes to Register RX5CS0, it defines the command function.
When software reads Register RX5CS0, it checks the completmn and error
status of the last command executed.
After the RCX50 controller performs the requested function, it interrupts the

processor if interrupts are enabled. Software should ensure that bit (7>
(RXIE)in the port controller CSRis set.
Consider Register RX5CS4 as another example Followmg a data transfer
command in which a seek error occurs, Register RX5CS4 contains the num-

ber of the incorrect track. Following a maintenance command such as restore
drive, Register RX5CS4 contains system configuration data indicating what
disks are available and which ones are double sided. Unlike datain the watch

chip registers, RCX50 controller register data is not rotated durmg data
transfers. Table 6-8 lists the registers and their uses.

Table 6—8 RCX50 Controller Register Functions
Command

Status

Status |

or Data
Transfer

Following a
Data Transfer

Following a
Maintenance

Command

Address
(hex)

Function

200B 0004

RX5CS0

Wtite to load

Contains

device and
function select

command
completion and

codes

error information

200B 0006

RX5CS1

200B 0008

RX5CS2

Write
to load

Contains error

track number

Contains error

message

Write to load

Contains current

sector number

track number

200B 000A RX5CS3

—

Contains current

200B 000C

200B 000E
|

RX5CS4

RX5CS5

—

Write to load

sector number

status on unit

and volume

Contains

Contains system

incorrect track

configuration

number

data

—

extended

function code

(Continuéd “on next page)

Dedicated I/O and Memory Devices

6-17

Table 6-8: RCX50 Controlier Register Functions (Cont.)
Command

Status

Following a
Data Transfer
Command

Following a
Maintenance
Command

Address
(hex)

or Data
Transfer
Function

200B 0010

RXS5EB

Read data buffer

—

200B 0012

RX5CA

Read to clear
data buffer
address

—

200B 0014

RX6GO

Read to start

—

200B 0016

RX5FB

Write data buffer

—

6.5.1

Data Transfer Examples

Examples of command sequences that write and read data on a diskette may
help to clarify standard uses of these registers.
Write data example:
1. Read Register RX5CA to set the data buffer address to O.

2. Load Register RX5FB, one byte at a time, with the 512 bytes of data to be

stored.

Load Register RX5CS0 to select
drive O, disk 1, side O

the write sector function code (111 binary)
the normal motor timeout option (0) (see Section 6.5.2.1)
. Load Register RX5CS1 with 23 (hex), the track to be written.

Load Register RX5CS2 with 5 (hex), the sector to be written.
Read Register RX5GO to start executing the write sector command.

The controller writes the data stored in the data buffer to the disk, moving

the 512 bytes previously written to Register RX5FB to the track and sector selected.

: Whe’n the RCX50 controller interrupts the CPU (vector FO) read Register
RX5CSO0 to check command completion status. The DONE bit should be
set, and the ERROR bit should be clear.

Read data example:

1. Read Register RX5CA to set the data buffer address to 0.
2. Load Register RX5CS0 to select

drive O, disk O, side 0
the read sector function code (100 binary)

the normal motor timeout option (0)

6-18 Dedicated I/O and Memory Devices

. Load Register RX5CS1 with 1A (hex), the track to be read.
. Load Register RX5CS2 with 7 (hex), the sector to be read.

. Read Register RX5GO to start executing the read sector command. The
controller copies 512 bytes from the track and sector selected into the data

buffer.

. When the RCX50 controller interrupts the CPU, read Register RX5CS0 to
check the command completion status.

. If the DONE bit is set and the ERROR bit is clear in Register RX5CS0,
read Register RX5EB 512 times to move the requested data from the data
buffer to main memory.

. Note that the KA825 is capable of servicing an interrupt and clearing the
interrupt pending bit in the PCtrl before the RCX50 controller deasserts

INTRQA. This results in the interrupt pending bit being reset in the
PCtrl. When writing RCX50 drivers, handle this occurrence either by

clearing the interrupt pending bit in the PCtrl by macro code, or by ignor-

ing RX interrupts when the RX5CS0 DONE bit is not set.

6.5.2

RX5CSO0 is central to control of the RCX50 controller. It has two formats: command function format and status format (data transfer status and maintenance status).
6.5.2.1

RX5CS0 Command Function — When software writes to this register,

the RCX50 interprets the information as a command, according to the format
shown.

76543210

MUST BE ZERO
FUNCTION CODE BIT 2
FUNCTION CODE BIT 1
FUNCTION CODE BITO

EXTENDED MOTOR TIMEOUT
DRIVE SELECT

DISK SELECT

SIDE SELECT (MUST BE ZERO)
MLO-413-85

Figure 6-10: Register RX5CS0 Command Function Format
e Bit (0), Reserved to DIGITAL, must be zero.

e Bits (2:1), Drive, and Disk Select _ This field selects the surface to read or
write, as shown in Table 6-9.

Dedicated I/O and Memory Devices

6-19

Table 6-9: Dlskette Surface Selectlon Code Interpretatlon

Unit

Number

unit 0

Diskette
Surface

Bit2

Drive

Select

drive 0

Bitl
-

Disk

Select

Bit 0

Side

Select

(

disk O

~side 0

unit 1

drive 0

disk 1

side O

unit2

drive 1
disk O

side 0
unit 3

drive 1

disk 1

side 0

(

NOTES

Standard configurations incorporating the KA820 module provide
one disk drive that uses single-sided diskettes. Side 0 is the data

side.

The unit numbers shown in Table 6-9 refer to unit number used in

the RX5CS3 Current Status Register. These unit numbers do not
refer to VMS unit numbers,

<
:

e Bit (3), Extended Motor Timeout — Following completion of a disk access

command, the spindle normally stops rotating in 3 seconds. You can extend
the rotation for 30 seconds by writing 1 to bit (3). This function is useful
when you perform a sequence of data transfers to or from the diskette.

o Bits (6:4), Function Code

The RCX50 controller executes eight major functions (Table 6-10). | |

¢ Read Status Function (000) — The RCX50 controller responds to this main-

tenance function by showing in Registers RX5CS0 through RX5CS4 the
status of the track selected in RX5CS2 on the diskette surface selected
by

RX5CSO0 bits (2:0). RX5CS3 contains the volume changed status, generally the most useful status information. The read status functlon resets all
volume changed information.

¢ Maintenance Mode Function (001) — System start-up software and diagnostic software can use this maintenance function to test the RCX50 con-

troller. Registers RX5CS0 through RX5CS4 show the status of the
controller following completion of the test.

6-20

Dedicated I/0 and Memory Devices

{

Table 6-10: RCX50 Function Codes
Binary Function
Code in RX5CS0

Corresponding

Bits (6:4)

- 000

001

- 010

Function

Read status

Maintenance status

Mainte_nance mode

Maintenance status

Restore drive

Maintenance status

011

RCX50 initialize

Maintenance status

100

Read sector

Data transfer status

101
110

111

| Extended function

Data transfer status

Read address

Data transfer stétu‘s

Write sector

Data transfer status

RCX50 Restore Drive Function (010) — The RCX50 seeks track 0 on the
specified diskette surface in response to this maintenance function. Registers RX5CS0 through RX5CS4 show the maintenance status.

RCX50 Initialize Function (011) — The RCX50 restores the drive, checks

the drive status, and tests the controller in response to this maintenance

function. Registers RX5CS0 through RX5CS4 show the maintenance
status.

Read Sector Function (100) — The RCX50 reads the sector specified in

RX5CS2 in the track specified in RX5CS1 in response to this data transfer

function. It stores the 512 bytes read in the data buffer and shows data

transfer status in Registers RX5CS0 through RX5CS4.

Extend Function (101) — The RCX50 looks in Register RX5CS5 for the code
defining the type of data transfer function required. Six extended functions
are available.

Table 6-11:

RCX50 Extended Functions

Extended

Function

Code
(hex)

|
Function

Read with retries, up to 10 times.

Write a sector with a deleted data mark in the sector header.

Used for nonnative diskettes: report format parameters of the

unit specified by Register RX5CS0 bits (2:0) in Registers

RX5CS1, RX5CS2, RX5CS3, and RX5CS4.
3

Used for nonnative diskettes: set format parameters specified
in Registers RX5CS1, RX5CS2, RX5CS3, and RX5CS4.

(Continued on next page)
Dedicated I/O and Memory Devices

6-21

Table 6-11:

RCX50 Extended Functions (Cont.)

Extended

Function

(

Code

4
5

Function

(hex)

Report the RCX50 controller version number in RX5CS2.
Read a sector and compare it with the contents of the data

buffer. You should load the data buffer with the appropriate
values before starting this function.

o Read Address Function (110) — The RCX50 reads the first header found at
the current track location on the diskette surface selected by RX5CS0 bits
(2:0) in response to this data transfer function. The controller sequentially transfers six bytes to Register RX5EB:

)

Track address

Side address

Sector address

Sector length

Header CRC 1

Header CRC 2

(

o Write Sector Function (111) — The RCX50 writes the contents of the 512-

byte data buffer to the track and sector selected by Registers RX5CS1 and
RX5CS2 on the diskette surface selected by RX5CS0 bits (2:0) in response

to this data transfer function.

6.5.2.2 RX5CSO0 Data Transfer Status and Maintenance Status — Following completion of a data transfer function or maintenance function, the RX5CS0 Register has the following format.

76543210
ERROR

2
FUNCTION CODE BIT
FUNCTION CODE BIT 1

FUNCTION CODE BIT0
'DONE

DRIVE SELECT
DISK SELECT

'SIDE SELECT

MLO-414-85

Fig‘ure 6-11: Register RX5CS0 Status Format
6-22

Dedicated 'O and Memory Devices

(

e Bits (6:4,2:0) — The functions of bits (6:4,2:0) correspond to the functions

of these bits in the command function format listed in Section 6.5.2.1.
* Bit (3), DONE (Read only)
0 = busy
1 = done

When the DONE bit is set, the RCX50 controller is not busy; all registers
are therefore accessible to the CPU.
If the RCX50 controller is busy executing a command, software should not
try to read this register or any other RCX50 controller register. When it is

busy, the controller responds to any read request to any register with a null
byte in which bit (3) is 0.

e Bit (7), ERROR (Read only)
0 = no error
1 = error

When the ERROR bit is set, it means that an error occurred during execution of the last command. Software can read the error code in Register
RX5CS1 as an aid in defining the cause of the error.
|

6.5.3

RX5CS1 uses two formats: a command function format (Track Register) and a
status format (Error Register).

6.5.3.1 RX5CS1 Command Function, Track Register — Software should load
RX5CS1 with the target track number for disk access. Valid track numbers
range from 00 to 4F (hex).

76543210

0
TRACK BIT 6

TRACK BITH

TRACK BIT 4

TRACK BIT 3
TRACK BIT 2
TRACK BIT 1
TRACK BITO
MLO-415-85

Figure 6-12: RX5CS1 Command Function Format
Dedicated I/O and Memory Devices

6-23

6.5.3.2

RX5CS1 Data Transfer and Maintenance Status Format, Error Register —

When the ERROR bit in Register RX5CS0 is set, Register RX5CS1 contains
an error code defining the error that occurred when the RCX50 executed the
last function.

Table 6-12:

RCXSO Error Codes Availablein Reglster RX5CS1

Error

Code
(hex)

Error

No error

Drive 0 track 00 sensor failure

Drive 1 track 00 sensor failure

Both drives failed to respond; system has no drives

Tried to access a track greater than 4F (hex)

Drive fails to seek home

Data record not found; data mark (DAM) not found within 43
(decimal) bytes following 1D

ID record not found

- Command timeout

Selected side is not a match

Selected unit is not ready

58
60

Disk is not installed coi'rectl;y
ID CRC
|

Seek error

Data required (DRQ) does not appear within 32 microseconds

Soft ID read error

Data CRC

Lost data; 8051 chip did not respond to data requlred (DRQ) within

23 microseconds

Tried to access an unavailable unit

Drive not ready during write

Drive not ready during read

A8 |

No match for the specified sector

BO
B8

Unit write protected on a Wr_ité command
Tried to access a sector numbered 0 or greater than A (hex) |
(Continued on next page)

6-24 Dedicated I/O and- Memory Devices

Table 6-12:

RCXS50 Errer Codes Availablein Reglster RX5CS1 (Cont.)

Error

Code
(hex)

Error

Mamtenance status only — the low order 4 bits of the RAM falled

to pass the memory test

Maintenance status only — the hlgh order 4 bits of the RAM failed

to pass the memory test

Maintenance status only — no index pulSe was detected

Maintenance status only — drive speed is not within limits

Maintenance status only — bad format or a blank disk

Maintenance status only — stepping error

Tried to set unsupported diskette parameters

- FO

~ Maintenance status only
— phase-locked loop (PLL) frequencyis
not within the limits

Tried to read a sector with a deleted data mark

Maintenance status only — data buffer is bad

6.5.4

Tried to write a non-RCX50 diskette

formats. RX5CS2 is the Sector Register on a data transfer, and it shows the
current track following execution of a function.

6.5.4.1

RX5CS2 Data Transfer Format, Sector Register — Before transferring

data to or from a diskette, software should load RX5CS2 with the target sec-

tor number. The valid range is 01 to 0A (hex).

76543210

C
0
0
0

SECTOR BIT 3
~

SECTORBIT 2
SECTOR BIT 1
SECTOR BIT 0
MLO-416-85

Figure 6-13:

RX5CS2 Command Function Format: Sector Register
Dedicated I/O and Memory Devices

6-25

6.5.4.2 RX5CS2 Data Transfer and Maintenance Status Format, Current Track

RX5CS2 shows the track number used in the command.

76543210

TRACK BIT 6

5
TRACK BIT
TRACK BIT 4

TRACK BIT 3
TRACK BIT 2

TRACK BIT 1
TRACK BIT O
MLO-417-85

Figure 6-14: RX5CS2 Status Format: Current Track Register

6.5.5 Register RX5CS3, Address 200B 000A

Register RX5CS3 provides two status formats. It identifies the current sector
following a data transfer function, and it gives the current RCX50 controller
status following a maintenance command.

6.5.5.1 RX5CS3 Data Transfer Status Format, Current Sector Register — Following a data transfer function RX5CS3 shows the current sector number.

6.5.5.2 RX5CS3 Maintenance Statds Format, Current Status Register — The

first four bits of RX5CS3 show the status of the unit specified by Register
RX5CSO0 (see Table 6-9 and Figure 6-11).

During controller initialization, bits (3:0) show the status of drive 0, disk O.
Bits (7:4) show the volume status, updated since the last read status command. These bits are affected only by the read status command. The volume
" numbers (3-0) correspond to the unit numbers shown in Table 6--9.

" You should not normally place diskettes in the diskette drive during initiali-

zation. However, the controller tests for diskette presence and sets the corres-

ponding Volume Changed bit if it detects a diskette.

Interrupts related to the Volume Changed bits are enabled following the first
read status command after initialization.

6-26

Dedicated I/O and Memory Devices

76543210

0
0
0

SECTOR BIT 3
SECTOR BIT 2

SECTOR BIT 1
SECTOR BIT O
MLO-418-85

Figure 6-15:

RX5CS3 Data Transfer Status Format:
Current Sector Register
76543210

VOLUME 3 CHANGED
VOLUME 2 CHANGED
VOLUME 1 CHANGED

VOLUME 0 CHANGED
"UNIT n WRITE PROTECTED

UNIT n READY
- UNITn DOUBLE SIDED
UNIT n AVAILABLE
MLO-419-85

Figure 6-16:

RX5CS3 Maintenance Status Format:

Current Status Register

e Bit (0), Unit n Available (Where.n 1s specified in RX5CS0)
0 = not available

1 = available

e Bit (1), Unitn Dbuble Sided (where n is specified in RX5CS0)
0 = single sided

1 = double sided

Dedicated I/O and Memory Devices

6-27

e Bit (2), Unit n Ready (Whefe n is specified in RX5CS0)

0 = not ready
1= ready

e Bit (3), Unit n Write Protected (where n 1s specnfledin RX5CS0)
0 = not write protected
|

1 = write protected

* For all Volume Changed bits (7, 6, 5, 4)

0 = The ready signal has not changed since the last read status
|

- command

1 = The ready signal has changed since the last read status command
6.5.6 Register RX5CS4, Address 200B 000C
Register RX5CS54 prov1des two formats. The data transfer status gives the

‘incorrect track number, following‘a seek error. The maintenance status gives
the system configuration.

6.5.6.1 RX5CS4 Data Transfer Status, Incorrect Track Register — If a seek error
occurs when the RCX50 is executing a command, RX5CS4 yields the track
number to which the read/write head actually moved. If no seek error occurs,

the register contains all zeros.

76543210

INCORRECT TRACK BIT 6
INCORRECT TRACK BIT §

( |

INCORRECT TRACKBIT4

INCORRECT TRACK BIT 3
INCORRECT TRACK BIT 2

INCORRECT TRACK BIT 1
'INCORRECT TRACK BIT
0
MLO-420-85

Figure 6-17: RXSCSéCOmmand Function Format:
Incorrect Track Register

6.5.6.2

RX5CS4 Maintenance Status, System Configuration Register —

RX5CS4 summarizes the diskette drive configuration. Four bit pairs make
up the register format. Each bit pair shows the status of one diskette (vol-

ume). The initialization function updates RX5CS4 with the current system
configuration.

6-28

Dedicated I/O and Memory Devices

(

76543210

DISK 3 DOUBLE SIDED
DISK 3 AVAILABLE

DISK 2 DOUBLE SIDED
DISK2 AVAILABLE

DISK1 DOUBLE SIDED
DISK 1 AVAILABLE
DISK 0 DOUBLE SIDED

DISK0 AVAILABLE
MLO-421-85

RX5CS4 Maintenance Status Format:

Figure 6-18:

System Configuration Register

o For all Available bits (6, 4, 2, 0): 0 = the diskette is not present
1 = the diskette is present

e For all Double Sided bits (7, 5, 3, 1): 0 = single sided
1 = double sided

NOTE
are single sided.
- RX50 supported diskettes

6.5.7

Software should load Register RX5CSS with an extended function code when

it loads 101 (binary) in bits (6:4) of Register RX5CS0. Table 6-11 lists the
codes and their meanings.

543210

EXTENDED FUNCTION CODE BIT 7

EXTENDED FUNCTION CODE BIT 6
"EXTENDED FUNCTION CODEBIT b5

EXTENDED FUNCTION CODE BIT 4

EXTENDED FUNCTION CODE BIT 3
EXTENDED FUNCTION CODE BIT2

EXTENDED FUNCTION CODE BIT 1
EXTENDED FUNCTION CODE BIT 0
MLO-422-85

Figure 6-19:

RX5CS5 Format: Extended Function
Dedicated I/O and Memory Devices

6-29

6.5.8 Register RX5EB, Empty Sector Buffer Register,
Address 200B 0010

Register RX5EB gives software read access to the 512-byte data buffer on the
RCX50 controller, one byte at a time. To read data from a diskette, software
should first execute the read sector command and set the address.of the data
‘buffer to O (see the read data example in Section 6.5.1).
76543210

DATA BIT 7

DATA BIT 6
DATA BIT 5

DATA BIT 4

DATA BIT 3

DATA BIT 2
DATA BIT 1

DATA BIT 0
MLO-423-85

Figure 6-20:

RX5EB Format: Empty Sector Buffer Register

(

Each time software reads Register RX5EB, the controller increments the address of the data buffer location being examined. Software must keep track of
the location associated with each byte it reads, since the controller does not
supply address information.

6.5.9

Software sets the address in the data buffer to 0 when it accesses (reads or
writes) Register RX5CA.

6.5.10

When software reads or writes Register RX5GO, the controller executes the
function specified in Registers RX5CS0 through RX5CS5. This should be the
last step software performs in carrying out any RCX50 command. The con- troller interrupts the CPU when it finishes executing the command. Software
- should then read the RX5CS0 Register to check the command status.

6-30 Dedicated /O and Memory Devices

6.5.11

Register RX5FB gives software write access to the 512-byte data buffer on the
RCX50 controller, one byte at a time.
76543210

DATA BIT 7
DATABIT®6
DATABITS

DATA BIT 4

DATA BIT 3

DATA BIT 2
DATA BIT1
DATA BIT
O
MLO-424-85

Figure 6-21:

RX5FB Format: Fill Sector Buffer Register

Each time software writes to the register, the controller increments the address of the data buffer location being written (see the write data example in

Section 6.5.1). Software must keep track of the location accessed with each
write transfer, since tlie controller does not supply address information. Be-

fore writing data, software should read Register RX5CA to set the data buffer

address to O.

Dedicated I/0O and Memory Devices

6-31

Chapter 7
KA820 Diagnostics

The optional VAX 8200 system diagnostic package includes programs that
test all KA820 functions. Self-test is available to and appropriate for all

users. You can order the full VAX diagnostics package through your local
DIGITAL Field Service office. These programs provide more complete fault
isolation than self-test, but they require detailed knowledge of the VAX 8200
hardware. The standard VAX diagnostic programs explained in this chapter
are available if you buy a diagnostic license; they are appropriate only for
DIGITAL Field Service engineers and OEM customers who maintain their
own systems.

Table 7-1:

Diagnostic Program Categories Related to the VAX 8200

Program
Category

Intended
User

Run-time
Environment

Self-test

All customers
and DIGITAL

Area Tested

Reference

Console

KAS820
hardware

Chapter 3 of
this manual
This Chapter

Field Service

Separate

DIGITAL

VAX

VAX-generic

Cluster
Exerciser

Field Service
and Licensed

Diagnostic
Supervisor,

and KA820specific

Programs

customers

levels 4, 3,
and 2

functions

VAX

KA820

Serial-Line

DIGITAL

Unit Test

Field Service
and licensed
customers

@ Diagnostic
Supervisor
Level 2R

This Chapter

Serial-Line
Units

The macrodiagnostic programs described here require a variety of run-time
environments (diagnostic program levels), because they test a wide range of
functions, using a building-block approach.
Level 4 —

Programs that run without the VMS operating system

(stand-alone) and without the VAX Diagnostic Supervisor,
VDS

///—.\ \‘

Level 3 —

VDS-based programs that run without VMS (stand-alone)

Level 2 —

VDS-based programs that can run either with VMS (on-

line) or without VMS (stand-alone)

Level 2R —

VDS-based programs that run only with VMS (on-line)

Refer to the VAX Diagnostic System User’s Guide for a general description of

the VAX diagnostic system and an introduction to VDS. The VAX Diagnostic
System User’s Guide offers instructions for building the diagnostic directory

(SYSMAINT) and installing and updating the VAX diagnostic software.
Table 7-2 offers an overview of the programs described in this chapter.
Table 7-2:

Diagnostic Programs Described in this Chapter

Program

Run-time

Code

Program Name

Environment

Hardware Tested

EVKAA

VAX-generic cluster

Level 4 (stand-alone,

exerciser: hardcore

VAX instruction set

boot and run from

used by VDS

Instruction test

the console)

VAX-generic cluster

Level 2 (on-line or

- EVKAB

exerciser: basic

stand-alone)

instruction exerciser

EVKAC

Basic VAX instruction set, nonprivileged

VAX-generic cluster

Level 2 (on-line or

exerciser: floating-

stand-alone)

point instruction

Floating-point VAX
Instruction set,
nonprivileged

exerciser

EVKAE
«-

VAX-generic cluster

Level 3 (stand-alone)

exerciser: privileged

Privileged VAX
instruction set

architecture exerciser

EBKAX

KA820-specific

Level 3 (stand-alone)

cluster exerciser

@ KAS820 CPU, RX50

drive and RCX50
controller, serial-line
units, watch chip,

boot RAM, multiprocessor functions

EBDAN

7.1

Serial-line unit

Level 2R (on-line

diagnostic program

Serial-line units 1, 2,

only)

and 3

Load Paths
You can use two kinds of load paths for loading diagnostic programs into main
memory:

1. Load from the maintenance system disk, the operating system disk, or

other mass storage medium.

2. Load from RX50 diskettes distributed by DIGITAL.

7-2

KA820 Diagnostics

If a hardware failure prevents you from loading diagnostics from the maintenance system disk or another disk attached to a VAXBI node, you can try
loading diagnostics another way. If two or three of the load paths are faulty,

the fault is probably on the KA820 module and should be reflected in the
results of the self-test program. Use the console T command to run self-test.
The red and yellow light-emitting diodes (LEDs) on the KA820 module should

also help you to identify the problem (see Chapters 3 and 4).

7.2

Test Sequence and Repair Recommendations

The KA820 module and the VAX 8200 system are designed to make repair
easy and straightforward. If you suspect a hardware failure, you can try to

identify the failing module before calling DIGITAL Field Service.
1. Check the light-emitting diodes (LEDs) on the modules in the VAXBI back-

plane. If a yellow LED is off, the indicated module is faulty. The KA820
module also provides red LEDs, which indicate a fault when lit, unless the

CPU is in the console mode.

. If the LEDs look right, run self-test by typing

and then T on the

console terminal. See Chapter 3 for an explanation of self-test on the
'KA820 module.
|
. If self-test reveals no fault, and you suspect a fault on the KA820 module,

boot EVKAA, the VAX Hard-Core Instruction Test, from a diskette in the
RX50 drive (see Section 7.3).
. If EVKAA runs without error, boot VDS (EBSAA) stand-alone from the
maintenance system disk (see Section 7.4).

. If you cannot boot VDS from the maintenance system disk or another device connected to a VAXBI node, boot it from the RX50 diskette (secondary
load path).
When you see the VDS prompt, DS), run level 2 or 3 diagnostic programs
to test the area of the system you think is faulty. If you suspect the KA820

module, run the remaining cluster exerciser programs in the following
order:
EVKAB
EVKAC
EVKAE
EBKAX

See Sections 7.6 through 7.9.
. If the cluster exerciser programs do not reveal an error and you suspect-a

problem with the serial-line units,
Boot VMS

Run VDS on-line
Run the serial-line unit test, EBDAN (see Section 7.10).

KA820 Diagnostics

7-3

7.3

EVKAA, Hard-Core Instruction Test
The Hard-Core Instruction Test checks the set of instructions required to boot
and run VDS.

Fifteen tests, arranged in a building block sequence, make up the Hard-Core
Instruction Test. The program proceeds from a check of instructions that manipulate the PSL through tests of the INSQUE and REMQUE instructions
and console transmitter functions.

7.3.1

Booting EVKAA on the Primary Processor

Boot and run EVKAA on the primary processor by typing the console commands shown in Example 7-1.

! Halt the primary processor.

! Initialize the primary processor.

! Insert the appropriate diskette
!

»))B CSA1

in the RX50 drive.

! Boot and run EVKAA.

Example 7-1:

Booting EVKAA on the Primary Processor

Console microcode loads and starts the program in the first good 64K-byte
section of main memory at the base address plus 200 (hex). EVKAA then runs
continuously, making a complete pass every 0.2 seconds, unless it finds a
hardware error. After the first pass and subsequently after every 10 passes,
the program sounds a beep on the console terminal and prints a message:
EVKAA VUx.x PFASS nnnCX) DONE!

If EVKAA finds a hardware error, it prints a message on the console terminal
and halts, forcing the KA820 module to return to the console mode.
??? ERROR TEST #nn,

SUBTEST #nn (instruction-code) failed

(one-line description of failure)
EXFECTED DATA - xXXXXXXX
RECEIVED DATA - XXXXXXXX
206
FC

=xxXXXXXX

)

¥f EVKAA finds a hardware fault, call DIGITAL Field service to repair the
fault. If you must repair the system yourself, replace the KA820 module (see
Appendix B), since the KA820 module is the unit most likely to be at fault if
EVKAA fails. Then check the repair by running the full set of diagnostic programs that test the KA820 module.

7.3.2

EVKAA Prerequisites and Functions

The KA820 processor must meet the following conditions before EVKAA can
run:

1. The load path from the RX50 diskette drive must be functional.

2. At least 64K-bytes of main memory, aligned on a page, must be valid.

7-4

KAB820 Diagnostics

3. The following instructions must be functional:

BEQL

BICL2

BICPSW

BISPSW

BRW

CLRL

HALT

INCL

MFPR

MOVL

MOVPSL

MOVW

MOVZBL

MTPR

TSTL

BISL

XORL3

4. Three addressing modes must also be valid:

(PC)+
D (PC)

7.4

Using VDS Stand-Alone
You should be able to boot VDS (EBSAA) on any KA820 processor in the

VAX 8200 system if EVKAA runs without errors on that processor. VDS requires 512K-bytes of memory.

7.4.1

Booting VDS Stand-Alone on the Primary Processor

Boot VDS on the primary processor from the maintenance system disk by
typing the commands shown in Example 7-2 on the console terminal. VDS
identifies itself before prompting for operator input.
! Halt the primary processor.

YNNI
Y))B/R5:12

238

{(ddxn)

v om

o ow

XXXXXXXX

! Initialize the primary processor.
! Boot and run VDS from a device
!
where (ddxn) identifies the boot
!
device type, adapter node number,
!
and boot device unit number (see
!
Section 4.3.2 in Chapter 4).
! List of nodes found.
! Size of VAXBI memory.

VAR DIAGNOSTIC SOFTWARE

FROFERTY OF
DIGITAL EQUIFMENT CORFORATION
CONFIDENTIAL AND PROPRIETARY
llse Authorized Only Pursuant
COFYRIGHT,

to a Valid Right-to-lse License

DIGITAL EQUIPMENT CORPORATION,

RESERVED.
DIAGNOSTIC SUFERVISOR.

ZZ-EBSAA-2.1

DS)

1985.

ALL RIGHTS

6 MAR 1985 13:22:45

! VDS prompt symbol.

Example 7-2:

Booting VDS Stand-Alone on the Primary Processor

NOTE

The VAX diagnostic software should be permanently installed in
the SYSMAINT directory.

KAB820 Diagnostics

7-5

If the VDS bootstrap fails, boot VDS through the secondary load path, using
an RX50 diskette. Insert the appropriate diskette in the RX50 drive and type:
yyyB CSA1

on the console terminal.

7.4.2

Booting VDS Stand-Alone on an Attached Processor

If you want to test an attached KA820 processor in a VAX 8200 system, you

must first boot VDS on the primary processor using console commands, then
boot VDS on the attached processor using the VDS BOOT n command, and
then run diagnostic programs.

| Halt the primary processor.

| Initialize the primary processor.

y)) B/RS=18 (dxn)
.2 3% . . . .5 e
XXXXXXXX

o5 s s F

! Boot VDS on the primary processor.
! Nodes found.
! Size of VAXBI memory.

VAX DIAGNOSTIC SOFTWARE
PROFPERTY 0OF

DIGITAL EQUIPMENT CORFORATION

CONFIDENTIAL AND PROPRIETARY

lse Authorized Only Pursuant to a Valid Right-to-lse License

DIAGNOSTIC SUPERVISOR. ZZ-EBSAA-8.1 6 AUG 1985 14:22:45

psy BOOT n

D5y

RUN (exxxx?

! Boot VDS on the attached processor
!

at node n.

! Run diagnostic program {exxxx)

Example 7-3: Booting VDS Stand-Alone on an Attached Processor
7.4.3

Help

VDS provides a help feature that gives information on diagnostic programs
and VDS commands. Examples:
e HELP

HELP DEVICE KA820
HELP SET FLAGS
HELP EVKAB

7-6

KAB820 Diagnostics

7.4.4

Attaching and Selecting the KA820 Module

You must attach and select the KA820 module before running level 2, 2R, or 3
diagnostic programs to test it. You can attach all devices in the system by

running the autosizer in the default mode in response to the DS) prompt.
DS)

RUN

EVSEA

The autosizer identifies all native DIGITAL devices on the system and passes
this information to VDS.

Or, you can attach and select the KA820 module specifically, using the following command format in response to the DS) prompt:
DS)»

ATTACH KAB2@ HUB KAn msiz id rx@ rxi

where:
n
msiz

is the KA820 node ID (hex) (for error message print out)
is the size of memory in kilobytes (decimal)

is the CPU’s node ID (hex)

rx0

is Y or N (Is scratch diskette present in RX50 drive 0?)
is Y or N (Is scratch diskette present in RX50 drive 1?)

rxl
DS)

SELECT Kfn

If you attach an external wrap connector on the back panel of the main cabinet for serial-line unit 1, 2, or 3, attach and select each wrapped serial-line

unit as follows:
DS)

ATTACH SLU

KAn TCx@ extlp

rate

where:
TCAO is serial-line unit 1
TCBO is serial-line unit 2
TCCO is serial-line unit 3
n

DS)

is the KA820 node ID

extlp

isY or N (Is an external wrap connector provided?)

rate

is the desired baud rate (150 to 19200)

SELECT TCx@

7.4.5

Flagsin VDS

The functions of VDS command flags are consistent across all diagnostic programs, but the functions of event flags vary with each diagnostic program.

You can set command flags with the SET FLAGS command, according to the

following format:
DSy

SET

FLAGS

{(arg-list)

where (arg-list) identifies the command flags to be set (for example, SET
FLAGS OPERATOR, QUICK). The SHOW FLAGS command lets you see the
status of each VDS flag.

KAB820 Diagnostics

7-7

Some diagnostic programs use event flags. You can set event flags with the
SET EVENT command, according to the following format:
DS) SET EVENT <(arg-list)

where (arg-list) identifies the event flags to be set (for example, SET EVENT
1, 3, 4). The SHOW EVENT command lets you see the status of each event
flag.

7.4.6

Test Repetitions

Each diagnostic program that runs with VDS normally completes one pass.
You can stop it by typing ©taue). If the program finds an error, it prints an

error message, aborts the failing subtest, and continues with the next subtest

or test, unless the HALT flag is set. If the error is severe, the test or program
may be aborted, returning control to VDS.

If you want to run a specific test or set of tests, instead of running the tests in
the default section, use the /TEST qualifier with the RUN command:
DS) RUN {exxxx),TEST=(first)[:{(last)]

where (exxxx) is the program code and (first) and (last) are decimal test
numbers.

You can specify a program section to execute by using the /SECTION quali-

fier with the RUN command:

DSY RUN {(exxxx)/SECTION=(section-name?

You can specify how many times a program runs by using the /PASSES quali-

fier with the RUN command:

DS) RUN {(exxxx}/FASSES={(count)

where (count) indicates the number of passes (decimal) to run.

Use a pass count of 0 to run a program continuously. If you do this, the
or a failure occurs with the HALT flag
program will run until you type
set.

NOTE

You can replace the RUN command with the combination of LOAD
and START, where START takes the same parameters as RUN. After loading a program with LOAD, you can type SHOW TESTS, asking VDS to list the test names and numbers on the terminal.

7-8

KAB820 Diagnostics

7.5

Using VDS On-line
Before you run any level 2R diagnostic programs you must run VDS
on-line,
under the VMS operating system. Then run the program you require.
Example 7-4 shows the procedure for running VDS on-line from the SYSMAI
NT
directory and then running EVKAB. Example 7-5 shows the procedur
e for

running VDS on-line from the RX50 diskette drive (the seconda

ry load path)

and then running EVKAB. VDS identifies itself before prompting

for operator input. In either case you must begin by logging in to the field
service
account.

llsername:

FIELD

Fassward:

SERVICE

$ SHOW DEFAULT

SYS$SYSROOT: [SYSMAINTI
$ RUN EBSAA

! Load and start VDS.

VAKX DIAGNOSTIC SOFTWARE
PROFERTY OF
DIGITAL EQUIFMENT CORPORATION
CONFIDENTIAL AND FROFRIETARY
Ise Authorized 0Only Fursuant

COFYRIGHT,

DIGITAL EQUIFMENT CORFORATION,

RESERVED.

DIAGNOSTIC SUPERVISOR.

D§)

to a Valid Right-to-lUse License

ZZ-EBSAA-8.1

SHOW LOAD

DS)
DS)

ATTACH KARB2d HUBR KAZ 2048 2 ¥ N

! Attach the KA820. Insert
!
ascratch diskette in RX50
!
unit 0.
! Select the KA820 at node 2.
! Load the EVKAB diagnostic.
! List the EVKAB tests.

SELECT KA2
LOAD EVKAR

SHOW TESTS
1: BRRB
Test 2: BRW

Test 3:

Test

DS)

6 SEF 1985 12:42:45

! Identify the default load device
and directory.

DS)
.

ALL RIGHTS

DUARB: [SYSMAINT]

DS)

1985.

BRC

161:

EDITFC

START

Example 7-4:

! Run EVKAB.

Running VDS On-Line from the SYSMAINT

Directory

KA820 Diagnostics

7-9

llsername:

FIELD

Passward: SERVICE
$ MOUNT,OVERRIDE=ID CSA1:

$ SET DEFAULT CSA1:[SYSMAINTI

| Load and start VDS.

$ RUN EBSAA

VAX DIAGNOSTIC SOFTWARE
PROFPERTY OF

DIGITAL EQUIPMENT CORPORATION
CONFIDENTIAL AND PROPRIETARY

Use Authorized Only Pursuant to a Valid Right-to-lUse License
COPYRIGHT, DIGITAL EQUIPMENT CORPORATION, 1985. ALL RIGHTS
RESERVED.

DIAGNOSTIC SUPERVISOR. ZZ-EBSAA-8.1 6 OCT 1985 23:17:25
! Attach the KA820.

DS)> ATTACH KAB2@ HUB KAZ 2048 2 % N

I Select the KA820 module

DS) SELECT KA2

at node 2.

! Run the EVKAB diagnostic.

DS} RUN EVKAB

Example 7-5: Running VDS On-line from RX50 Diskette Drive
NOTE

You cannot run VDS on an attached processor on-line, and you cannot run the autosizer on-line.

7.6

EVKAB, VAX Basic Instruction Exerciser
You can run EVKAB (level 2) either stand-alone or on-line. With VDS running and the KA820 module attached and selected (see Section 7.4.4), run
EVKAB as follows. In response to the DS) prompt, type:
DS) RUN EVKAB

I Run the VAX basic instruction
|

exerciser.

Run EVKAA before running EVKAB to assure a systematic test of the
KA820 module.

EVKAB tests most of the nonprivileged VAX instruction set, except for the
floating point instructions. It consists of 161 tests, each of which checks execution of a specific VAX instruction.

Both EVKAB and EVKAC respond to the command flags; they also respond

to event flags 1 through 6, with the following functions:

Disable messages relating to the floating-point accelerator.
Disable interrupts from the interval timer.

Enable interrupts from the interval timer while page faulting is enabled.
Enable the continuation of a subtest after error detection (normally the
program aborts a subtest when it detects an error).

7-10

KAB820 Diagnostics

5. Disable execution of the DIVP instruction while the interval timer is
interrupting.

6. Prompt for tests to be executed if the OPERATOR flag is set. Begin testing

by typing (CR) twice after selecting the tests you want.

7.7

EVKAC, Floating-Point Instruction Exerciser
You can run EVKAC (level 2) either stand-alone or on-line; VDS must be run-

ning, and the KA820 module must be attached and selected (see Section
7.4.4). In response to the DS) prompt, type:

DSY RUN EVKAC

Run EVKAA and

! Run the VAX floating-point

instruction exerciser.

EVKAB before running EVKAC to assure a systematic

test of the KA820 module.

EVKAC consists of 98 tests, each of which tests a floating-point instruction.

EVKAC responds to the command flags and to event flags 1 through 6, as

explained in Section 7.6.

7.8

EVKAE, VAX Privileged Architecture Exerciser
EVKAE (level 3) runs only in the stand-alone mode; VDS must be running
without VMS, and the KA820 module must be attached and selected (see

Section 7.4.4). In response to the DS) prompt, type:
DS RUN EVKAE

! Run the VAX privileged
!

architecture exerciser.

Run EVKAA, EVKAB, and EVKAC before running EVKAE to assure a sys-

tematic test of the KA820 module.

EVKAE consists of 12 tests grouped in 8 sections:
e DEFAULT

* MEM__MGT
e EXCEPTIONS

e PROCESS
e REGISTERS

* CHANGE_MODE
e TIMER

e CONTEXT

KAB820 Diagnostics

7-11

7.9

EBKAX, VAX 8200-Specific Cluster Exerciser
EBKAX (level 3) runs only in the stand-alone mode; VDS must be running
without VMS, and the KA820 module must be attached and selected (see
Section 7.4.4)

EBKAX tests the portions of the KA820 module not specified by the VAX
architecture, including the serial-line units. You can expand the test of serialline unit 1, 2, or 3 by attaching a wrap connector to the plug for that serialline unit on the rear of the main unit. However, you cannot use a wrap

connector on serial-line unit 0 when you run EBKAX, because the console
terminal requires that line for communication with the KA820 module and
with VDS.

If you use wrap connectors, use the serial-line unit specific ATTACH and
SELECT commands for each wrapped serial-line unit as follows:
DS) ATTACH SLU KAn TCx@ extlp rate

where:

TCAO
TCBO
TCCO
n

is serial-line unit 1
is serial-line unit 2
is serial-line unit 3
is the KA820 node ID

rate

is the desired baud rate (150 to 19200)

extlp

is Y or N (Is an external wrap connector provided?)

DS) SELECT TCx@

! Run the KAB820-specific cluster

DS) RUN EBKAR

exerciser.

Example 7-6: Running EBKAX

Run EVKAA, EVKAB, EVKAC, and EVKAE before running EBKAX to assure a systematic test of the KA820 module.

EBKAX consists of 57 tests grouped in three sections:
e DEFAULT

e MANUAL INTERVENTION
e MEMORY

7.10

EBDAN, KA820 Serial-Line Unit Diagnostic
EBDAN (level 2R) runs only in the on-line mode, with the VAX Diagnostic
Supervisor running under VMS. You must attach both the KA820 module
and the serial-line units to be tested, and then select the serial line units to be
tested. First attach the KA820 module as explained in Section 7.5. Then load
EBDAN, the serial-line unit diagnostic. Then attach and select each serialline unit to be tested. And then start the test. The following example shows
the attaching, selecting, and testing of serial-line unit 1.

7-12

KAB820 Diagnostics

DS} ATTACH KARZ22 HUB 2 2048 2 Y N

Attach the KA820 module.

DS) LOAD EBRDAN

Load the serial-line unit

DS) ATTACH SLU
DEVICE LINK? knz

Attach a serial-line unit.
The serial-line unit to be

diagnostic.

DEVICE NAME? TCAQ
SERIAL-LINE UNIT EXTERNALLY WRAFFED? Y

tested is on the KA820
module at node 2.
Serial-line unit 1.

BAUD RATE? 1200
DS} SELECT TCAQ

Connect a loopback connector.
Use baud rate 1200.
Select serial-line unit 1 for

DS) START

testing.
Run EBDAN.

Example 7-7:

Running EBDAN

Run the cluster exerciser programs before running EBDAN to ensure a thorough test of the serial-line units.

]

EBDAN consists of three tests:
e Per line internal data loopback test
e Per line external data loopback test
e Multiple line external loopback test
If you do not select a specific test with the START command, EBDAN executes the tests according to the information you have provided with the
ATTACH and SELECT commands.

KA820 Diagnostics

7-13

Appendix A

- KA820 Module 1/0 Pins and Cables

A.1

Module I/O Pin Definitions
The KA820 module contains 300 module I/O pins along one edge. These pins
are arranged in five segments (A, B, C, D, E). Each segment contains 60 pins,

30 on each side of the module.
Asyou look at the card cage from the backplane side, with the cam at the top,
pins corresponding to segments A through E appear from top to bottom. Seg-

ments A and B carry the VAXBI signals. Segments C, D, and E carry modulespecific signals.
Each of the segments C, D, and E supplies signals to two 30-pin connectors.
For purposes of cable positioning, refer to the left connector for segment C as

C1 and the right connector as C2. Connectors D1, D2, E1, and E2 are identified similarly.

Segment C carries signals for-the four serial-line units. Only connector C2 is
used. Segment D carries PCI bus signals and signals that go to the control

panel and the PCM module. Segment E carries only the performance monitor
enable signal on connector E2.
Figures A-1 through A-5 show the module I/O pin segments from the backplane side of the card cage.

GND46
47

16BID31L
17 BI D30 L

GND31
32

01BID29L
02 Bl D28 L

GND 03

18 GND

GND 49

19 GND

04 Bl D27 L

GND 50
51
52
GND 53
54
GND 55

20 BI D26 L
21 Bl D22 L
22 Bl D20 L
23 BI D18 L
24 BI D17 L
25 BI D14 L

35
GND 36
37
GND 38
39
GND 40

05 Bl D25 L
06 Bl D23 L
07 BI D21 L
08 BID19 L
09 BID15 L
10 BI D24 L

Bl SPARE L 56

26 BI D12 L

11 BID13 L

GND 57
+5V 58

27 BID10 L
28 +5V

GND 42
+5V 43

12 BI D11 L
13 +5V

GND 59

29 +5V
30 BID16 L

+5V 44

14 BI DO7
L

Bl DO8 L 45

15 BI D06 L

Bl DO3 L 60

MLO-425-85

Figure A-1:

Module I/O Pins on Segment A Viewed from the
Backplane

Bl DO5 L 46

Bl ID3 H 47
GND 48

Bl ID1 H 49
+12 V 50

Bl BAD L 51

Bl D02 L 31

17 BI DO1 L

GND 32

02 BI PO L

18 Bl 12 L

Bl ID2 H 33

03 BI 11 L

19BIIOL

GND 34

20 BI CNF1 L

05 BI BSY L

21 BI D09 L

Bl STF L 36

06 BI NOARB L
07 BI I3 L

-12 'V 37

Bl RESET L 54

09 BI DCLO L

GND 55

25 Bl ECL VCC H

Bl ACLO L 40

10 GND

GND 56

26 Bl TIME H

Bl TIME L 41

GND 57

27 Bl PHASE H

Bl PHASE L 42

12 GND

GND 13

28 GND

GND 43

58 GND

29 GND

GND 44

GND

MLO-426-85

Figure A-2: Module I/O Pins on Segment B Viewed from the
Backplane

GND 31

UART3 TX L 32

UART3 RCV RTN 33

UART3 RCV L 34

05 GND
06 UART1 TX L

07 UART1 RCV RTN

GND 38

UART2 TX L 39

UART2 RCV RTN 40

UART2 RCVL 41

12 GND

13 UARTO TX L

EXT ENB APT 45

08 UART1 RCV L

14 UARTO RCV RTN
15 UARTO RCV L

MLO-427-85

Figure A-3: Module I/O Pins on Connectors C1 and C2 Viewed from
the Backplane

A-2

KA820 Module I/O Pins and Cables

(

04 BI CNF2 L

Bl IDO H 35

22 Bl CNFO L

GND 52

01 BI DOO L

16 BI D04 L

RX INTRA L 46

16 GND

BDALO L 31

01 GND

RX INTRB
L 47

17 GND

BDAL1 L 32

02 GND

18 GND

BDAL2 L 33

03 GND

19 GND

BDAL3 L 34

04 GND

PNL ENB WT EEPROM H 50

20 GND

BDAL4 L 35

05 GND

PNL RSTRT HLT H 51

21 GND

BDALS L 36

06 GND

PNL CNSL LOG H 52

22 GND

BDALG6 L 37

23 GND

BDAL7 L 38

07 GND

N O

PNL CNSL ENB H 53

——t

WATCHIP DS H 48
PNL RUN LED L 49

08 GND

BUF CPU FAULT L 54

24 GND

BAS L 39

BI STF
L 55

25 GND

BDS L 40

Bl BAD L 56

26 GND

BWRITE L 41

KA820
L 57

27 GND

BRPLY L 42

RESERVED 58

28 GND

BMDEN L 43

13 GND

SPARE 3 59

29 GND

BSDEN L 44

14 GND

SPARE 4 60

30 GND

SSX L 45

15 GND

09 GND
10 GND
11

GND

12 GND

MLO-428-85

Figure A-4: Module I/O Pins on Connectors D1 and D2 Viewed
from the Backplane

46|

| O3
| 04

48|

| 01 BUF PME OUTH

)

50|

52|

¢«

o | 22

37
38

| 09

| 10

| 12

| 13

| 14

| 15

«
o
|27

—

.
|

89|

07
|o08

.
o

E
2

| 30

MLO-429-85

Figure A-5: Module 1/0 Pins on Connectors E1 and E2 Viewed from
the Backplane

KA820 Module I/O Pins and Cables

A-3

Figure A-6 shows the backplane slots viewed from the bottom side of the
VAXBI module card cage.

A
B

miil

MLO-430A-85

Figure A-6: A Backplane Slot Shown from the Backplane Side of
the Card Cage

A.2

(

Cables Related to the KA820
Two sets of cables run from the C and D connectors on slot K1J1 of the VAXBI
card cage. See Appendix B for instructions on how to gain access to the cables.
Four cylindrical cables extend from the C2 connector at slot K1J1 to four sep-

arate serial-line unit connectors on the IOCP (I/O connector panel) as shown

in Figure A-7. The IOCP connectors convert the serial lines from EIA RS423
to EIA RS232.

Two flat 30-wire ribbon cables extend from the D connectors at slot K1J1 to

the J1P1 and J2P2 connectors on the PCM module in the KK810 control
panel assembly, as shown in Figure A-7. These cables carry the PCI bus signals from the KA820 module to the watch chip on the PCM module and then
out to the optional RCX50 controller.

A-4

KAS820 Module I/O Pins and Cables

TO SLOT IN \\
Bl CAGE

TO I/O
—v”

PANEL

TO J1 & J2
PCM MODULE
MLO-431-85

Figure A-7:

Cabling for C and D Connectors

In a multiprocessor system only the KA820 modulein slot K1J 1 uses these
cables. The other KA820 modules do not require cables.

KA820 Module I/O Pins and Cables

A-5

Appendix B
Module Installation and Access to Cables

B.1

Module Installation and Replacement
DIGITAL Field Service engineers install and repair the VAX 8200 system.
However, if you determine that a KA820 module
in the system is faulty, you
can replace it as follows:
|
1. Turn off power to the VAX 8200 system by rotating the upper key switch

counterclockwise to the vertical position.

Switch the circuit breaker on the bottom panel at the rear of the main

unit to the off position.

. Pull out the stabilizer bar at the bottom of the cabinet. See the VAX 8200
System Owner’s Manual for illustrations.

. Remove the back panel with an Allen wrench (5/32 inch).

. Release the locking mechanism on the slide and push out the 'processor
drawer from the rear of the main unit.

. Remove the 14 screws from the panel that covers the top of the drawer,

and remove the panel.

. Attach a ground strap from your wrist to the system ground to avoid
damaging the module.

. If the faulty KA820 module is the primary processor, lift the first black
handle on the right side of the module cage. This releases the module in
the first slot, K1J1.

If the faulty KA820 module is an attached processor, lift the black handle
for the corresponding VAXBI slot.

. Remove the module in the exposed slot by lifting it clear.
10. Insert the new KA820 module in the same slot, with the component side

of the module to the right.
11. Close the black handle over the new KA820 module.

12. Replace the metal panel on the drawer, and insert and tighten the 14

screws that hold it.

13. Slide the processor drawer back into the cabinet.
14. Push the stabilizer bar back inside the cabinet.

B.2

Gaining Access to the Cables
You can gain access to the cables that supply the KA820 module in slot K1J1
as follows:
1. Turn off power to the VAX 8200 system by rotating the upper key switch

counterclockwise to the vertical position.

Switch the circuit breaker on the bottom panel at the rear of the main unit
to the off position.

Pull out the stabilizer bar at the bottom of the cabinet. See the VAX 8200

System Owner’s Manual for illustrations.

Remove the back panel with an Allen wrench (5/32 inch).
. Release the locking mechanism on the slide and push out the processor
drawer from the rear of the main unit.
. Pull the latches on the drawer sides and raise the drawer to the vertical
position.

. Remove the bottom panel of the processor drawer to expose the bottom of
the VAXBI module cage and the cables that supply the KA820 module in
slot K1J1.
. When you are ready to close the main unit, replace the bottom panel,

lower the drawer to the horizontal position, and push it back inside the

main unit.

Push the stabilizer bar back inside the cabinet.

B-2

Module Installation and Access to Cables

Appendix C

‘

Drive Load Characteristics of Off-Board Signals

C.1

Serial-Line Unit Signals
The UART drivers and receivers for the KA820 serial-line units provide EIA
RS423 electrical characteristics. These signals are converted to the RS232
standard by connectors on the back panel. Table C-1 shows the electrical

characteristics of the output signals.

Table C-1:

Serial-Line Unit Output Signal Characteristics

Output

Characteristics

Voltage low

Voltage high

C.2

Minimum

Maximum

Units

—5.0

—6.0

Volts

5.0

6.0

Volts

PCI Bus Off-Board Signals
Eighteen PCl signals are buffered and run off the KA820 module to the watch

chip and the RCX50 controller. The PCI signal names change as they leave
the module, to conform to the signal names used by the RCX50 controller. The
buffer circuits are low-power Schottky devices.

Table C-2 lists the module I/O pin numbers and and names of the PCI signals.
Table C-3 lists the pin numbers and names of other signals that run off the

KA820 module. Tables C—4 through C-8 list the electrical characteristics of
these off-board signals.

Table C-2:

PCI Bus Off-board Signals
Type of Signal

On-board Signal
Name

External
Signal Name

PCIDAL 7:0H

BDAL 7:0 H

at I/0
Connection

Driver/
Receiver

Module
1/O Pin

Tristate,

8307

D38:D31

bidirectional

PCIDASL

BDS L

Driver output

LS244

D40

RX CSL

SSXL

Driver output

1.8244

D45

RX DALO L

BMDEN L

Driver output

LS244

D43

RX DALI L

BSDEN L

Driver output

LS244

D44

PCIREAD H

BWRITE L

Driver output

LS244

D41

PCI ALE H

BAS L

Driver output

LS244

D39

RTC DS H

WATCHIP DS H Driver output

L.S244

D48

BUF RXINTRAL

RXINTRAL

TTL input

LS244

D46

BUFRXINTRBL

RXINTRBL

TTL input

L8244

D47

PCI READY L

BRPLY L

TTL input with

7417

‘D42

470 ohm pull-up

C-2

Drive Load Characteristics of Off-Board Signals

Table C-3:

Other Off-board Signals
Type of Signal

On-board Signal

External

at 1/0

Name

Driver/

Signal Name

Module

Connection

Receiver

1I/O Pin

PME OUT H

BUF PEM

Driver output

LS244

Driver output

LS244

D55

EXT ENB APT Driver output ~ LS244

C45

PNL CNSL

OUTH
BUF BI STF L

BI STF L

ENB APT L

CNSL LOG H

Driver output

~ LS244

D52

Driver output

LS244

D50

Driver output

LS244

D53

Driver output

LS244

D51

PNL RUN

OC driver,

7417

D49

LED L

2000-ohm

LS38

D56

LOGH

ENB WT EEPROM
H

PNLENBWT

EEPROM H

CNSL ENB H

PNL CNSL
ENB H

RSTRT HLT H

PNL RSTRT
HLT H

RUN L

pull-up

BI BAD H

BI BAD L

OC driver,
no pull-up

Table C-4:

Driver Output Voltages

Output
Voltage

Output

Level

Minimum

Current

Typical

Maximum

Voltage

Units

Voh

Ioh=—- 3mA

3.4

—

Volts

Voh

Ioh = -15mA

2.0

—

Vol

Iol =

12mA

—

0.25

Volts

Vol

Iol =

24mA

—

0.35

0.5

Volts

Table C-5:

Volts

Driver Output Current

Output

Current

Output

Level

Minimum

Voltage

Maximum

Current

Units

Isc (short

Vec=55V

—40

—225

Ioh

=27V

—

-15

Iol

=04V

—

circuit)

Drive Load Characteristics of Off-Board Signals

C—3

Table C-6: PCI DAL (7:0) Lines Bidirectional Voltage Levels
Output

Voltage

Maximum

Minimum

Voltage

Units

Level

Output Current

Voh

Ioh = — 5mA

2.7

Volts

Voh

Toh = —10 mA

2.4

—

Volts

Vol

Iol =

20mA

—

Volts

Vol

Iol =

48 mA

—

0.5

Volts

Table C-7: PCI DAL (7:0) Lines Bidirectional Current Levels
Output Current
Level

Output
Voltage

Minimum
Current

Maximum
Current

Units

Isc (short circuit)

—

—25

—150

Iozh (tristate)

Vo=40V

—

200

Tozl

Vo=04V

—

—200

Table C-8: PCI Bus Input Signal Voltage and Current Levels

C-4

Input Signal Levels

Minimum

Maximum

Units

Vih

2.0

—

Volts

Vil

—

0.8

Volts

Iihat Vi=2.7V

—

20.0

lilat Vil = 04 V

—

-10.2

Drive Load Characteristics of Off-Board Signals

Appendix D
BlIC Registers

System software can program the BIIC registers on the KA820 module to control processor participationin transactions and to handle interrupts on the

VAXBI bus. Each BIIC register has a node space address (bb + offset, where

bbis the node base address) and a node private space address (2008 0000 +
- offset). The BIIC does not support the lock function, so it treats IRCI and
UWMCI commands like RCI and WCI commands (see Tables 2—-4 and 2-5 in

Chapter 2 for lists of VAXBI commands used by the KA820 module).

The register bit descriptions that follow use a code to define read write, and

functional characteristics:

DCLOC

Cleared following a successful self-test following the deassertion of

BIDC LO L.

DCLOL

DCLOS

Loaded on the deassertion of BI DC LO L.

Set following a successful self-test following the deassertion of BI

DC LO L.
DMW

Writeable in diagnostic mode.

Disable selection: when an enable bit of this type is cleared, the
BIIC suppresses the appropriate BCI SEL L and BCI SC 2:0 L as-

sertion and inhibits any KA820 module response to transactions
corresponding to the cleared enable bit.

D.1

Read-only.

R/W

Read/Write.

Special case: the operation is defined in the detailed description.

W1C

Write one to clear. You cannot set a W1C bit.

Device Register, DTYPE (R/W, DMW, DCLOL)
Processor initialization microcode loads this register; system software should
set bit 16 after loading secondary patches.

171615

27 26

CPU REVISION
CODE

MICROCODE PATCH
REVISION

SECONDARY PATCH REVISION
DEVICE TYPE
-

MLO-432-85

Figure D-1: Device Register (DTYPE)
Node private space address

2008 0000

Nodespace address

bb + 00

CPU Revision Code

Loaded by processor initialization microcode.

Bits (31:27)

Microcode Patch

Ioaded by processor initialization microcode.

Revision

Bits (26:17)

Secondary Patch
Revision
Bit (16)

When bit (16) is set, secondary patches are
not needed, or they are needed and have been
loaded. When bit (16) is clear, secondary

patches are needed but have not been loaded.
Processor initialization microcode writes this
bit according to data in location 2009 816C in
the EEPROM.

Code that loads secondary patches should set

bit (16) at the same time.
Device Type
Bits (15:0)

Loaded by processor initialization microcode.
The Device Type field identifies the VAXBI
node by type. The KA820 module should have
0105 (hex) in Device Type field.

D.2

VAXBI Control and Status Register, VAXBICSR

Processor initialization microcode writes this register to clear the Broke

bit following a successful self-test. System software should set the Hard and
Soft Error Interrupt Enable bits following initialization to enable error
interrupts.

D-2

BIIC Registers

16151413121110 9

2423

{0
VAXBI

INTERFACE
REVISION
BIIC TYPE
HES

SES
INIT

BROKE
STS

NRST

RESERVED TO DIGITAL,
UWP

"HEIE

SEIE
ARB
NODE ID
MLO-433-85

Figure D-2:

VAXBI Control and Status Register (VAXBICSR)

Node private space address:

2008 0004

Nodespace address:

bb + 04

VAXBI Interface
Revision (RO)

This field identifies the revision level of the BIIC.

Bits (31:24)

VAXBI Interface

Type (RO)

The type of VAXBI interface chip (BIIC) used on

this node. This field is read as 00000001 (binary) in

- Bits (23:16)

this implementation.

HES (RO)
Bit (15)

Hard Error Summary. When set, HES indicates
that one or more of the hard error bits (except TDF)
in the Bus Error Register are set.

SES (RO)
Bit (14)

Soft Error Summary. When set, SES indicates that
- one or more of the soft error bits in the Bus Error
- Register are set.

INIT (W1C, DCLOS)
Bit (13)

(INIT Bit. INIT is not used by the KA820 module.

BIIC Registers

D-3

BROKE (W1C, DCLOS)
Bit (12)

Broke bit. Broke indicates that the KA820 module
has not successfully completed its self-test. Microcode clears Broke following successful completion
of self-test.

STS (R/W; DCLOS)
|
Bit (11)

NRST (SC)
Bit (10)

UWP (W1C, DCLOC)
Bit (15)

Self-Test Status bit. STS shows the result of the
BIIC internal self-test. This bit is set to 1 if self-test
passes, and it directly enables the BIIC VAXBI
driver circuits. Since this is a normal R/W bit, it
can be altered by a write command directed at this
|
register.

Node Reset. Writing 1 to this bit forces the initiation of the BIIC self-test, as well as assertion of
BCI DC LO L, which initiates self-test on the rest
of the KA820 module. Read commands return O for
NRST. The BIIC clears STS when it sets NRST, to
allow proper recording of the self-test results.

Unlock Write Pending bit. UWP indicates that
this KA820 module has completed an IRCI transaction, but has not issued a subsequent UWMCI
transaction. If the KA820 module performs a
UWMCI transaction when the UWP bit is not set,
the ISE bit in the Bus Error Register will be set,
and the BIIC will complete the UWMCI transaction in the normal manner.

HEIE (R/W, DCLOC)

Hard Error Interrupt Enable bit. System software

Bit (6)

normally sets HEIE to enable an error interrupt
when HESis asserted

SEIE (R/W, DCLOC)
|
Bit (6)

Soft Error Interrupt Enable bit. System software
normally sets SEIE to enable an error interrupt
when SES is asserted.

ARB (R/W, DCLOC)

Arbitration Control bits. ARB determines the
mode of arbitration to be used by the KA820 mod-

- Bits (5:4)

ule, as follows:

Table D-1:

Arbitration Control Codes

Bit 5

Bit 4

Arbitration Scheme

Dual round-robin arbitration

Fixed-high priority (reserved)

Fixed-low priority (reserved)

Disable arbitration (reserved)

System software normally writes Os in these bits.

D-4

BIIC Registers

NODE ID

Node Identification field. The BIIC loads the Node

(RO, DMV, DCLOL)

ID field from the BCI I (3:0) H lines during the

Bits (3:0)

last cycle in which BCI DC LO L is asserted. Node
ID reflects the encoded node ID plug that is

plugged into the VAXBI backplane at the slot used
by this KA820 module.
Node 2 is the normal node ID assigned to the

VAX 8200 primary processor, according to DIGITAL convention.

D.3 Bus Error Register, BER (W1C, DCLOC)
313029282726252423222120191817 1615

3210

NMR

NPE

MTCE

CRD

CTE

IPE

MPE

UPEN

ISE

RESERVED TO DIGITAL

TDF

IVE

CPE
SPE
RDS

RTO

STO
BTO

NEX

ICE
MLO-434-85

Figure D-3:

Bus Error Register (BER)

When the BIIC detects an error, it sets the appropriate Bus Error Register
(BER)bit and generates an interrupt, if enabled. Software can read this regis-

ter to determine the cause of the error when it services a VAXBI error interrupt. System software should set the Hard and Soft Error Interrupt Enable
bits of each VAXBI node in the system by setting bits (6) and (7) in the VAX-

BICSR of each node.

BIIC Registers

D-5

System software must clear the error bits in the BER after reading the
register. After clearing the appropriate bit, software should reread the BER

to determine whether another bit has been set in the meantime. Alterna-

tively, it can read the Hard and Soft Error Summary bits in the appropriate

(

VAXBICSR to determine if another error bit has been set. Bits (31:16) indi-

- cate hard errors; bits (2:0) indicate soft errors.

During initialiZatiOn, system software can clear all error bits by Writing3FFF 0007 (hex) to the BER of each VAXBI node.

Node private space address: =

2008 0008

Nodespace address:

bb + 08

D.3.1 Bus Error Register Hard Error Bits
NMR (W1C, DCLOC)
Bit (30)
|

NO ACK to Multi-Responder Command Received.
NMR is set if the KA820 module receives a NO

ACK command confirmation for an INVAL, INTR,
IPINTR, STOP, BDCST, or RESERVED command.

'MTCE (W1C, DCLOC)
Bit (29)

does not perform this check on the assertion of the

encoded ID on the I lines during the embedded
|
|
ARB cycle.

Bit (28)

)

Master Transmit Check Error. During the cycles of
a transaction in which the KA820 module is the
only source of data on the VAXBI D, I and P lines,

the BIIC verifies that the transmitted data
matches the data received from the VAXBI bus. If
there is no match, the BIIC sets MTCE. The BIIC

CTE (W1C, DCLOC)

(

Control Transmit Error. The BIIC sets CTE when
there is an assertion of the NO ARB, BSY, or the

CNF (2:0) control lines, and the BIIC detects the

deasserted state. Note that the assertion of BI NO

ARB L during a burst mode transaction is not

checked.
MPE (W1C, DCLOC)
Bit (27)

Master Parity Error. The BIIC sets MPE during a

master transaction if it detects a parity error on
the bus during a data cycle of a transaction that
has an ACK confirmation on the CNF (2:0) lines.

ISE (W1C, DCLOC)
Bit (26)

Interlock Sequence Error. The BIIC sets ISE if the KA820 module successfully completes a UWMCI

transaction when the Unlock Write Pending

(UWP) bit in the VAXBICSR is not set.

TDF (W1C, DCLOC)
~
Bit (25)
A

Transmitter During Fault. The BIIC sets TDF if
the BIIC is driving the BI D and I lines (only the I
- lines during the embedded ARB cycle) during a cycle with a parity error.

D-6

BIIC Registers

(

The BIIC also sets TDF during slave transactions

if it detects a parity error on read data that it
transmits. Software that reads this register should
interpret a set TDF without a set MPE, CPE, or
IPE as an indication that the BIIC has detected a
parity error on its own transmitted read data.

TDF is not set for parity errors that occur during
-

IVE (W1C, DCLOC)
Bit (24)

loopback transactions.

IDENT Vector Error. The BIIC sets IVE if it receives anything but an ACK confirmation from a
master issuing IDENT after the KA820 module
has sent out an interrupt vector. This can occur
only when the KA820 module is used as an I/O controller and generates an interrupt.

CPE (W1C, DCLOC)

Command Parity Error. The BIIC sets CPE when

Bit (23)

it detects a parity error during a command/address

cycle. The error can occur during a VAXBI transaction or a loopback transaction.

SPE (W1C, DCLOC)

Slave Parity Error. The BIIC sets SPE when it detects a parity error during a data cycle of a write
transaction directed at the RXCD Register or any
of the BIIC registers on the KA820 module.

RDS (W1C, DCLOC)

Read Data Substitute. The BIIC sets RDS if it re-

Bit (22

Bit (215

RTO (W1C, DCLOC)

Bit(20)

ceives a Read Data Substitute or RESERVED status code during a read-type or IDENT (for vector
status) transaction. The BIIC logic also requires a
successful parity check for the data cycle that contains the RDS code, before it sets RDS. RDS gets
set even if the transaction is aborted some time after the receipt of the RDS or RESERVED code.

RETRY Timeout. The BIIC sets RTO if the KA820
module receives 4096 consecutive RETRY responses from the slave for the same transaction.

STO (W1C, DCLOC)

STALL Timeout. Not used on the KA820 module.

Bit (19)

BTO (W1C, DCLOC)
‘Bit (18)

Bus Timeout. The BIIC sets BTO if it is unable to
start any pending transaction (there may be sev-

eral that are pending) before 4096 cycles have
elapsed.

NEX (W1C, DCLOC)

Bit (17)

Nonexistent Address. The BIIC sets NEX when it
receives a NO ACK response for a read-type or
write-type command sent by the KA820 module.
Note that this bit is set only if the master transmit
check of the command/address cycle is successful.

‘BIIC Registers

D-7

The BIIC does not set NEX for NO ACK responses
to other commands.

ICE (W1C, DCLOC)
Bit (16)

D.3.2

Illegal Confirmation Error. The BIIC sets ICE
when it receives a reserved or illegal CNF (2:0)
code during a transaction. This bit can be set during either master or slave transactions. Note that
NO ACK is not considered an illegal response for
command confirmation.

Bus Error Register Parity Mode

UPEN (RO)

User Parity Enabled. UPEN indicates the parity

Bit (3)
|

D.3.3

(

mode (source of parity generation). When UPEN is
0, the BIIC is generating parity. When UPEN is 1,
the port controller is generating parity. UPEN is
normally O.

Bus Error Register Soft Error Bits

IPE (W1C, DCLOC)
Bit (2)

CRD (W1C, DCLOC)

Bit (1)

ID Parity Error. The BIIC sets IPE when it detects
a parity error on the encoded ID asserted when the
KA820 module is the VAXBI master, during an
embedded arbitration cycle. This error condition
also sets the TDF bit, except during loopback
transactions.

Corrected Read Data. The BIIC has received a cor-

rected read data status code during a read transaction. The BIIC sets CRD even if the transaction is
aborted after the BIIC receives the CRD status
code.

NPE (W1C, DCLOC)
Bit <0)

Null Bus Parity Error. The BIIC has detected odd
parity on the VAXBI bus in the second cycle of a

two-cycle sequence during which BI NO ARB L
and BI BSY L were not asserted.

D.4

Error Interrupt Control Register, EINTRCSR
When the BIIC on the KA820 module detects an error on the VAXBI bus, it
normally interrupts the processor. System software can use the Error Interrupt Control Register to control this function.
Node private space address:

2008 000C

Nodespace address:

bb + 0C

System software should load the Error Interrupt Control Register to control
interrupts from the BIIC following detection of a VAXBI error or the setting
of the INTR FORCE bit in this register. The BIIC interrupts the KA820 CPU,

D-8

BIIC Registers

if the INTR FORCE bit or any of the Bus Error Register bits is set, and the
error interrupt enable bits in the VAXBI Control and Status Register are set.

25242322212019

16151413

210

RESERVED
TO DIGITAL
INTRAB

INTRC

RESERVED TO DIGITAL
INTR SENT
INTR FORCE

LEVEL

RESERVED TO DIGITAL
VECTOR

RESERVED TO DIGITAL
MLO-435-85

Figure D-4:

Error Interrupt Control Register

INTRAB

Interrupt Abort. The BIIC sets this status bit if an

(W1C, DCLOC, SC)

INTR command sent under the control of this reg-

Bit (24)

ister is aborted (a NO ACK or illegal confirmation

code is received). System software should reset INTRAB after reading it. INTRAB has no effect on
the ability of the BIIC to send or respond to further

INTR or IDENT transactions.
INTRC

Interrupt Complete. The BIIC sets INTRC when

(W1C, DCLOC, SC)

the BIIC has successfully transmitted the vector

Bit (23)

for an error interrupt or when an INTR command

sent under the control of this register has been
aborted. Removal of the error interrupt request

automatically clears this bit. When set, INTRC inhibits the generation of new error interrupts by
the BIIC.
INTR SENT

Interrupt Sent. The BIIC sets INTR SENT when it

(W1C, DCLOC, SC)

has sent an INTR command and it expects an

Bit (21)

IDENT command to follow. The BIIC clears INTR

SENT during an IDENT command following the

detection of a level and master ID match. This allows the KA820 module to resend the interrupt re-

- BIIC Registers

D-9

quest if it loses the interrupt arbitration or if it
wins but the vector transmission fails. If the
KA820 module deasserts the error interrupt re-

quest, the BIIC clears the INTR SENT bit.
INTR FORCE

Force Interrupt. System software Can set INTR

(R/'W, DCLOC)

FORCE to force an error interrupt request when

Bit (20)

no error has been detected.

LEVEL (7:4)
(R/W, DCLOC)

Level (7:4). System software can set the Level
field to define the level at which the BIIC trans-

Bits (19:16)

mits interrupt commands.

The Level field also helps determine whether this
control register will respond to IDENT commands.
If any level bits of a received IDENT command
match the Level field in this register and there is a

match in the destination mask, the BIIC will arbitrate for the IDENT. This lets you program the
BIIC to respond to IDENT commands that match

the level exactly, or to IDENT commands that
match the level on a greater-than-or-equal-to

basis.

The BIIC does not transmit an error interrupt re-

‘quest if none of the Level bits is set.
VECTOR

Vector. The BIIC uses the vector in this field dur-

(R/W, DCLOC)

ing error interrupt sequences. It transmits the vec-

Bits (13:2)

tor when this node wins an IDENT arbitration

cycle on an IDENT transaction that matches the

conditions in the Error Interrupt Control Register.
The KA820 module uses the Vector field only when

it functions as an I/O controller.

BCI Control and Status Register, BCICSR
Processor 1n1tlallzat10n microcode loads the BCI Control and Status Register,
and software should leave it unchanged.
Node private space address:

2008 0028

Nodespace address:

bb
+ 28

BURSTEN
(R/W, DCLOC, NA)
Bit (17)

-Burst Enable. When BURSTENis set, the BIIC asserts BI NO ARB L continuously after the next
successful arbitration, until the BURSTEN bit is
reset or the BCI MAB L signal is asserted. The as-

sertion of BCI MAB L does not reset the BURSTEN bit. It merely clears the burst mode state in

the BIIC that is holding BI NO ARB L. Unless a

- subsequent transaction clears this bit, the next

D-10

BIIC Registers

successful arbitration causes the BIIC to again assert BI NO ARB L continuously. Note that loopback transactions must not use the burst mode.

1817161514131211109 8 7

6 b 4 3 2

INRNERER
-

RESERVED

TO DIGITAL
BURSTEN

STOP FORCE
IPINTR
MSEN
BDCSTEN

STOPEN|
RESEN

IDENTEN

INVALEN
WINVALEN

UCSREN
BICSREN

'INTREN

IPINTREN
PNXTEN

RTOEVEN

RESERVED
TO DIGITAL
MLO-436-85

Figure D-5:
IPINTR/STOP FORCE
(R/W, DCLOC, SC, NA)
Bit (16)

BCI Control and Status Register

IP Interrupt/Stop Force. When IPINTR/STOP
FORCE is set, it forces the BIIC to arbitrate for the
bus and transmit an IPINTR command or STOP
command, using the IPINTR Destination Register

for the destination field. The BIIC clears the
IPINTR/STOP FORCE bit when it transmits the
IPINTR command, regardless of whether the
transaction is completed successfully. Software
can monitor the EV (4:0) lines to determine
whether the transaction is completed normally.

BIIC Registers D-11

MSEN

Multicast Space Enable. When MSEN is set,

(R/'W, DCLOC, DS)

the BIIC asserts BCI SEL L and the appropriate

Bit (15)

BCI SC (2:0) code following receipt of a read-type
or write-type command directed at broadcast
space. This bit is normally left cleared, so the
KA820 module does not respond to multicast space

commands.

BDCSTEN

BDCST Enable. When BDCSTEN is set, the BIIC

(R/'W, DCLOC, DS)

asserts BCI SEL L and the appropriate BCI SC

Bit (14)

(2:0) code following receipt of a BDCST command.
This bit is normally left cleared, so the KA820
module does not respond to BDCST commands.

STOPEN

STOP Enable. The KA820 module does not re-

(R/W, DCLOC, DS)

spond to the STOP command; this bit should re-

Bit (13)

main cleared.

RESEN

'RESERVED Enable. When RESEN is set, the

(R/'W, DCLOC, SC)

BIIC asserts BCI SEL L and the appropriate BCI

Bit (12)

SC (2:0) code following receipt of a RESERVED
command code. RESEN is normally clear.

IDENTEN

IDENT Enable. When IDENTEN is set, the BIIC

(R/'W, DCLOC, SC)

asserts BCI SEL L and the appropriate BCI SC

Bit (11)

(2:0) code following receipt of an IDENT command. This bit affects only the output of SEL and
the IDENT SC code. Therefore, the BIIC always
participates in IDENT transactions that select

this node, even if IDENTEN is cleared.
INVALEN

INVAL Enable. When INVALEN is set, the BIIC

(R/W, DCLOC, DS)

asserts BCI SEL L and the appropriate BCI SC

Bit (10)

(2:0) code following receipt of an INVAL command. Processor initialization microcode sets IN-

VALEN to enable the port controller to forward
VAXBI invalidate transactions to the cache tag array on the M chip.
WINVALEN

Write Invalidate Enable. When WINVALEN is

(R/W, DCLOC, SC)

set, the BIIC asserts BCI SEL L and the appropri-

Bit (9)

ate BCI SC (2:0) code following receipt of a write-

type command for which the address is not in I/O
space. Processor initialization microcode sets
WINVALEN to enable the BIIC to forward VAXBI
write addresses to the port controller, so it, in turn,

can send invalidate requests to the cache tag array
in the M chip.

UCSREN

(R/W, DCLOC, DS)
Bit (8)

D-12

BIIC Registers

User CSR Space Enable. When set, this bit causes
the BIIC to assert BCI SEL L and the appropriate

BCI SC (2:0) code following receipt of a read-type

or write-type command directed at the RXCD Reg-

ister on the KA820 module. Processor initialization microcode sets UCSREN to enable VAXBI
access to the RXCD Register.
BICSREN

BIIC CSR Space Enable. When BICSREN is set,

(R/'W, DCLOC, SC)

the BIIC asserts BCI SEL L and the appropriate

Bit (7)

BCI SC (2:0) code following receipt of a read-type
or write-type command to its BIIC CSR space (the
first 256 bytes of this node’s node space). Processor
initialization microcode sets BICSREN to enable
VAXBI access to the BIIC CSR space on the KA820
module.

INTREN

(R/W, DCLOC, DS)
Bit (6)

INTR Enable. When INTREN is set, the BIIC asserts BCI SEL L and the appropriate BCI SC (2:0)

code following receipt of an INTR command. Processor initialization microcode sets INTREN.

IPINTREN

IPINTR Enable. When IPINTREN is set, the BIIC

(R/W, DCLOC, SC)

asserts BCI SEL L and the appropriate BCI SC

Bit (5)

(2:0) code following receipt of an IPINTR com-

mand that matches the IPINTR Mask Register.
However, IPINTREN enables only the IPINTR

SEL/SC code. The state of IPINTREN does not determine whether the KA820 module receives IPINTR commands. Software should clear the
IPINTR Mask Register to disable receipt of IP-

INTR commands. Processor initialization microcode sets IPINTREN.

PNXTEN

Pipeline NXT Enable. When PNXTEN is set, the

(R/'W, DCLOC, NA)

BIIC asserts BCI NXT L for an extra cycle (one

Bit (4)

more than the number of longwords transferred)

during write-type transactions. This extra BCI
NXT L cycle occurs after the last NXT L cycle for
write data, and is used to increment the write-silo

address counter to the address of the command/
address data for the next transaction. Processor
initialization microcode sets PNXTEN when it
sets the pipeline enable bit in the port controller
CSR, to enable the pipeline mode for memory
write transactions, increasing the efficiency of the
processor.

NOTE

If ENBL PIPE (PCntl CSR bit (13)) is set, PNXTEN must be set as well. If ENBL PIPE is clear,
PNXTEN must be clear.

BIIC Registers

D-13

RTOEVEN

When RTOEVEN is set, the BIIC asserts the RE-

(R/W, DCLOC, NA)
Bit (3)

TRY Timeout (RTO) Event code instead of the RE|

TRY CNF Received for Master Port Command

(RCR) Event code following the occurrence of a RE-

TRY timeout. If RTOEVEN is cleared, the BIIC
will not assert the RTO EV code in place of the

RCR EV code following a retry timeout. However,
the RTO bit in the BER will be set, and the BIIC
will generate an error interrupt if error interrupts
are enabled. Processor initialization microcode

sets RTOEVEN.

D.6 Receive ConSoIé Data Register, RXCD
The KA820 module receives data from other processors in the RXCD Register, one byte at a time. This register is implemented in the port controller, not

in the BIIC.

161514

1211

8 7

RESERVED
TO DIGITAL
.

BUSY

RESERVED TO DIGITAL
SENDER NODE ID
DATA
MLO-437-85

Figure D-6:

RXCD Register

Node private space
~address:

12008 0200

- Nodespace address:

bb + 200

BUSY

Busy bit. The receiving (local) KA820 module

Bit (15) |

changes BUSY from 1 to O after reading the RXCD

SENDER NODE ID
Bit (11:8)

DATA

Data received. In communications between the

Bits (7:0)

consoles of two processors, the data is an ASCII

character.

D-14

BIIC Registers

D.6.1

MFPR Instruction for the RXCD Register

Software can read the RXCD Register on the local KA820 module with an
MFPR instruction.

If the BUSY bit is cleared, no character has been received. The MFPR
instruction signals this condition by setting the V bit in the PSL.

If the BUSY bit is set, a character has been received. The MFPR instruction
reads the Data and Sender Node ID fields and clears the BUSY bit to indicate
that the RXCD Register is free to receive another character. The MFPR

instruction signals this condition by clearing the V bit in the PSL.

D.6.2 MTPR Instruction for the RXCD Register
Software can write the RXCD Register on a remote processor on the VAXBI
bus with an MTPR instruction.

- If the BUSY bitis set, no datais transferred The MTPR 1nstruct10n signals
this condition by setting the V bitin the PSL.
If the Busy bit is cleared, ‘the MTPR writes the Data and Sender Node ID

fields in the remote RXCD Register and sets the BUSY bit to indicate that
- new data is in the register. The MTPR instruction signals this condition by

clearing the V bit in the PSL.

BIIC Registers

D-15

Appendix E

Port Controller Control and Status Register

The port controller CSR performs three functions that are central to operation of the KA820 module:

1. Provides a read-only interface between the module and the control panel
that lets software and microcode examine switch positions and off-module
signals.

2. Enables software control of some module functions.
3. Stores module and VAXBI bus status information.

This register is accessible in the node private address space at addfess |
2008 8000. No other node on the VAXBI bus can read or write it.

When a VAXBI error occurs, machine-check microcode copies bits (22:16, 14)
to the MTEMPC Register in the M chip and to the status word on the stack at
SP + 18, where they are available to exception handler software (see Section

5.2 and Table 5-3 in Chapter 5).

RO)

RSTRT HLT

Auto Start/Halt Power-up Option Bit

Bit (31)

1 = Halt

0 = Auto Start

Related signal name:
Module 1I/0O pin:

PNL RSTRT HLT H
D51

RSTRT HLT shows the position of the lower key
switch on the control panel. Microcode checks the
status of this bit to determine whether to restart
(warm or cold) or go to console mode at power-up and
following an error halt condition.

RSTRT HLT is 1 on all KA820 attached processors,
since the signal from the control panel switch runs
only to the primary processor.

CNSL LOG
Bit (30)

(RO)

Physical/Logical Console Selection Bit
1 = Logical
0 = Physical

Related signal name:

PNL CNSL LOG H

Module I/O pin:

D52

313029282726252423222120191817161514131211109

RSTRTHLT _ |

CRD INTR

CNSLLOG

CLR CRD INTR

CNSLENB

CRD INT ENBL

Bl RESET

IP INTR

BISTF

CLR IP INTR

ENB APT
|
SELF-TEST PASS

RX IRQ
CLR RX IRQ

RUN

RXIE

wweE

CNSL INTR

EVENT LOCK

CLR CNSL INTR

WRITE MEM

CNSL INTR ENBL

EVNT 4

RESERVED TO DIGITAL

EVNT 3

TIMEOUT

EVNT2
EVNT 1

” |

ENB PIPE
PARITY ERR H

EVNT 0

WWPO

MLO~438-85

Figure E-1: Port Controller Control and Status Register
Microcode reads this bit to determine the console
source. The physical console is serial-line unit O,

which is normally attached to a terminal. The logical
console is another processor on the VAXBI bus.

CNSL ENB
Bit (29)

(RO)
Console Secure/Enabled Selection Bit
1 = Console Enabled
0 = Console Secure
Related signal name:
Module I/O pin:

|
PNL CNSL ENB H
D53

CNSL ENB shows the position of the upper key
switch on the control panel. Microcode checks this
bit when the console sends CTRL/P, to determine
whether console functions are enabled.

CNSL ENB is 1 on all KA820 attached Processors,

since the signal from the upper key switch on the con-

~ trol panel runs only to the primary processor.

BI RESET
Bit (28)

(R/W)

System Reset Control Bit

E-2 Port Controller Control and Status Register

Related signal name:

=~ BIRESET L

Module 1/O pin:

D54

Software can comipletely reset the VAX 8200 system,
ihéluding VAXBI memory, by setting BI RESET.
Setting this bit simulates a power-up sequence by cycling the BI AC LO L and BI DC LO L signals. Writing 0 clears the bit, but this has no useful effect,
because whenever it is set, thé resulting BI DC LO L
signal clears it.
BI STF
Bit (27)

(RO)
Self-Test Fast/Slow Selection Bit
1 = Slow Self-Test
0 = Fast Self-Test

Related signal name:
Module I/O pin:

BI STF L
D55

Microcode reads this bit to determine whether to run
the slow self-test or the fast self-test.

ENB APT
Bit (26)

(RO)
APT Connection Status Bit

1 = APT line not connected
0 = APT line connected
Related signal name:

Module 1/0O pin:

EXT ENB APT L
C45

Software can read this bit to determine whether an
APT line is connected to serial-line unit 0. APT (Au-

tomated Product Test) is a testing system used by
DIGITAL manufacturing.

SELF-TEST PASS

Bit (25)

(Read/Write by microcode)
Self-Test Status Bit

1 = Successful self-test
0 = Failed self-test
Self-test microcode writes 1 to this bit at the end of a

successful self-test, either at power-up or from the
console T (Test) command. The BI DC LO L signal
clears the Self-Test Status bit at power-up.

When the Self-Test Status bit is cleared, the KA820
module asserts the BI BAD L signal on module 1/0

~ pin D51 and it turns off the two yellow self-testpassed LEDs on the module.

When the Self-Test Status bit is set, the KA820 mod-

ule deasserts BI BAD L and turns on the two yellow
self-test-passed LEDs on the module.

Port Controller Control and Status Register

E-3

RUN
Bit (24)

(R/W)
Program Mode Run Bit

Related signal name:

PNL RUN LED L

Module I/O pin:

D49

Microcode sets this bit to indicate that it is in the program I/O mode; microcode clears the bit when changing to console mode.

The console microcode toggles this bit each time it
recognizes a (BREAK) character on serial-line unit
0. Thisis an aid in troubleshooting a dead console terminal. When RUN L toggles, the Run light on the
control panel flashes on and off to indicate that the
CPU recognizes the characters typed on the console
terminal. If the control-panel Run light flashes and
the terminal is dead, it indicates that the problem is
in the output path to the console terminal or in the
|
terminal itself.
WWPE
Bit (23)

- (R/'W)
|
Write Wrong Parity, Even Bytes.

1 = Force wrong parity generation and disable
parity checking of even data bytes on the
DAL bus

0 = Normal parity generation and parity checking
of the even bytes on the DAL bus
Self-test microcode and diagnostic software can set
WWPE to force wrong parity on the even bytes of the

DAL bus to, in turn, force wrong parity on either the
cache or BTB parity RAMs on write operations. This
~ function also prevents the port controller from detecting a cache or BTB parity error on even bytes.

Microcode and diagnostic software can clear WWPE
to resume normal parity operation and checking of
even bytes of the cache and BTB parity RAMs. Note
that bit (15) performs an equivalent function for
odd bytes.

EVENT LOCK
- Bit (22)
|

(Read/Write 1 to Clear)
Event Code Error Bit
1 = Event code is locked
0 = Event code is unlocked

The port controller sets this bit when it detects an error condition on the Event lines from the BIIC. Once
Event Lock is set, bits (21:16) are latched and no
~ longer reflect the state of the BIIC Event lines.

E-4

Port Controller Control and Status Register

Software can clear the bit and unlock the latched bits
<21:16) by writing 1 to Event Lock. Writing 0 to

Event Lock has no effect.
WRITE MEMORY

(RO)

Bit (21)

Memory Write Transaction Status Bit
1 = Error in Write Operation
0 = Error in Nonwrite Operation
The port controller sets this bit during memory write

transactions, two cycles after the BIIC asserts RAK
(Request Acknowledge). Write Memory remains set
as long as memory write transactions continue. Any
other type of VAXBI transaction clears the bit. If the
BIIC signals the occurrence of a VAXBI error condition, the port controller latches Write Memory with
the event code bits when it sets Event Lock.

Write Memory lets software determine when an error is associated with a pipelined VAXBI memory
write transaction, since errors may go undetected
until the port controller begins a subsequent
transaction.

EVENT4 — 0

(RO)

Bits (20:16)

VAXBI Transaction Event Code Bits.

The port controller checks these bits for error codes.
If it finds an error code, it latches bits (20:16) and

Write Memory, sets Event Lock, and invokes machine check microcode.
Event codes (hex) latched by the port controller:

Bus Timeout (BTO)

Read Data Substitute or RESERVED
Status Code Received (RDSR)

Illegal CNF Received fer Master Port

Command (ICRMC) Command
1A

NO ACK CNF Received for Master Port
Command (NCRMC)

Illegal CNF Received by Master Port for
Data Cycle (ICRMD)

Retry Timeout (RTO)

Bad Parity Received During Master Port
Transaction (BPM)

Master Transmit Check Error MTCE)

Port Controller Control and Status Register

E-5

After the machine-check exception handler deals
with the error, it should write 1 to PCntl CSR bit
(22) to clear Event Lock and release the latch on bits
(20:16) and Write Memory. See Table 5-4 in Chapter
5 for a full list of the event codes.

(R/W)

WWPO

Write Wrong Parity, Odd Bytes.

Bit {15)

1 = Force wrong parity generation and disable parity checking of the odd bytes on the DAL bus

0 = Normal parity generation and parity checking
of the odd bytes on the DAL bus
Self-test microcode and diagnostic software can set
WWPO to force wrong parity on the odd bytes of the
DAL bus to, in turn, force wrong parity on either the
cache or BTB parity RAMs on write operations. This
function also prevents the port controller from detecting a cache or BTB parity error on odd bytes.

PARITY ERROR

Bit (14)

Microcode and diagnostic software can clear WWPO
to resume normal parity operation and checking of
odd bytes on the cache and BTB parity RAMs. Note
that PCntl CSR bit (23) performs an equivalent
function for even bytes.
(Read/Write 1 to clear)
~ Parity Error Status Bit

1= Parity error detected by the port controller
0 = No parity error detected

Cleared by BIDCLO L
The port controller sets this bit when it detects a parity error on data read from the cache RAMs or BTB
RAMs. The port controller asserts the PCNTL ER-

ROR L signal at the same time to notify the M chip of
the error.

ENBL PIPE
Bit (13)

R/W)

Enable VAXBI Pipeline Mode Control Bit
1 = Enable pipeline mode
0 = Disable pipeline mode

Cleared by BI DC LO L

Pipeline mode lets the port controller post the next
VAXBI transaction to the BIIC without waiting until
the current transaction is completed and confirmation is received.

E-6 Port Controller Control and Status Register

However, to aid error recovery, the port controller
disables pipelining during write transactions to I/O
space, regardless of the state of this bit. This lets

microcode make sure that the transaction is completed, or an error is detected, before it starts the
next transaction.

NOTE

If ENBL PIPE is set, PNXTEN (BCI Control Register
bit (4)) must
be set as well. If ENBL PIPE is clear,
PNXTEN must be clear.
TIMEOUT

(Read/Write 1 to Clear)

Bit (12)

Port Controller Timeout Bit

1= Poi't controller timeout error
0 = No port controller timeout error

Cleared by BIDC LO L
The port controller starts a timer when it receives a
command from the CPU to perform a VAXBI transaction. If the transaction has not been completed 12.8

milliseconds later, the port controller sets this bit
and asserts the PCNTL ERROR L signal to notify the
M chip of the error.

Reserved to
DIGITAL
Bit (11)

CNSL INTR ENBL

(R/W)

Bit (10)

RXCD Logical Console Interrupt Enable Control Bit

1 - Enable interrupts from the RXCD Register
0 = Disable interrupts from the RXCD Register

Cleared by BIDC LO L
Processor initialization microcode sets this bit following self-test to enable interrupts from the RXCD
Register. With this bit set, an interrupt occurs when
- the BUSY bit in the RXCD Register is set.

Software can disable RXCD Register intefrupts by
writing 0 to this bit.

' CLEAR CNSL
INTR

(Write Only)
Clear RXCD Console Interrupt Bit

Bit (9)

Interrupt handling microcode writes 1 to this bit to
clear PCntl CSR bit (8), CNSL INTR.

Port Controller Control and Status Register E-7

CNSL INTR

(RO)

Bit (8)

RXCD Console Interrupt Bit
1 = RXCD interrupt pending

0 = No RXCD interrupt pending
The port controller sets this bit when the logical con-

~ sole is enabled and the RXCD BUSY bit changes

from O to 1, indicating that new data is in the
register.

RXIE

(R/W)

Bit (7)

RCX50 Interrupt Enable Bit
1 = RCX50 interrupt enabled

0 = RCX50 interrupt disabled
Cleared by BI DC LO L

Software can enable or disable interrupts from the
RCX50 controller by setting or clearing this bit. You
must set RXIE before performing RX50 I/O

functions.

CLR RX IRQ

(Write Only)

Bit {6)

Clear RCX50 Interrupt Request Bit
Interrupt handling microcode writes 1 to this bit to

clear the RCX50 interrupt request bit, PCntl CSR bit
(5), after reading it.

RX IRQ

(RO)

Bit (5)

RCX50 Interrupt Request Bit
1 = RCX50 interrupt request pending
0 = NO RCX50 interrupt request pending
Cleared by

BIDCLOL

Cleared by writing 1 to PCntl CSR bit (6)
The port controller sets RX IRQ whenever it receives

RX INTRA or RX INTRB pulses from the RCX50

controller. RX INTRA signals the completion of each
operation, and RX INTRB signals a change in the
RX50 drive status.

The port controller ORs RX IRQ with IP INTR and BI
INTR4 to produce BI INTR4 at IPL14. Therefore interrupt handling microcode reads RX IRQ, when it

responds to a BI INTR4 request, to determine if the
request is coming from the RCX50 controller. Micro-

code clears RX IRQ after reading it, by writing 1 to
PCntl CSR bit (6).

E-8

Port Controller Control and Status Register

(Write Only)

CLEAR IP INTR
Bit (4)

Clear Interprocessor Interrupt Request Bit

Interrupt handling microcode writes 1 to this bit to
clear the IP INTR bit, PCntl CSR bit (3).

(RO)

IP INTR

Interprocessor Interrupt Request Bit

Bit (3)

= Interprocessor interrupt request pending
0 = No interprocessor interrupt request pending
Cleared by BIDC LO L

|
Cleared by writing 1 to PCntl CSR bit (4)

The port controller sets this bit when it receives an IP
INTR request from the VAXBI bus. The port controller ORs IP INTR with RX IRQ and BI INTR4 at IPL
14. Interrupt handling microcode clears IP INTR as

it handles interrupt requests, by writing 1 to PCntl
CSR bit (4).

CRD INTR ENBL

(R/W)

Corrected Read Data Interrupt Enable Control Bit

Bit (2)

1 = CRD interrupt enabled
0 = CRD interrupt disabled

Cleared by BI DC LO L
The BIIC on the KA820 module generates a corrected read data interrupt when a single-bit error occurs in the VAXBI memory array and the memory
has corrected the data. Error logging software uses
this information to keep track of soft errors.

CLEAR CRD INTR

(Write Only)

Clear CRD Interrupt Bit

Bit (1)

Interrupt handling microcode writes 1 to this bit to
clear the CRD INTR bit, PCntl CSR bit (0).

(RO)

CRD INTR

CRD Interrupt Bit

- Bit (0)

Cleared by writing 1 to PCntl CSR bit (1).

The port controller sets CRD INTR when the BIIC indicates that it has received corrected read data and
CRD INTR ENBL (PCntl CSR bit (2)) is set. Inter-

rupt handling microcode clears the bit by writing 1 to

PCntl CSR bit (1).

Port Controller Control and Status Register

E-9

" Appendix F
Internal Processor Registers on the KA820 Module

You can use the console E/I command or macrocode MTPR and MFPR instructions to access these registers.

Thefollowing table lists the IPRs and their addresses.
IPR

Address

(hex)

Mnemonic

Name

KSP

Kernel Stack Pointer

ESP

Executive Stack Pointer

SSP

Supervisor Stack Pointer

USP

ISP

User Stack Pointer
Interrupt Stack Pointer
PO Base Register

POBR

‘POLR

PO Length Register

P1BR

P1 Base Register

P1LR

P1 Length Register

SBR

System Base Register

SLR

System Length Register

PCBB

Process Control Block Base

SCBB

System Control Block Base

12
13

IPLR
ASTLVL

Interrupt Priority Level Register
Asynchronous System Trap Level

SIRR

Software Interrupt Request Register

SISR

Software Interrupt Summary Register

IPIR

Interprocessor Interrupt Register

ICCS

Interval Clock Control Register
Next Interval Count Register

NICR

ICR

Interval Count Register

TODR

Time of Day Counter Register

RXCS

Console Transmit Buffer

RXDB

Console Receive Data Buffer

TXCS

Console Transmit CSR

TXDB

Console Transmit Data Buffer

TBDR

Translation Buffer Disable Register

CADR

Cache Disable Register

MCESR

Machine Check Error Summary Register

ACCS

Floating-Point Accelerator CSR

WCSA

Writeable Control Store Address Register

WCSD

Writeable Control Store Data Register

WCSL

Writeable Control Store Load Register
(Continued on next page)

F-1

IPR

Address

Mnemonic

Name

38
39
3A
- 3D
3E
3F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D

MAPEN
TBIA
TBIS
PMR
SID
TBCHK
RXCS1
RXDB1
TXCS1
TXDB1
RXCS2
RXDB2
TXCS2
TXDB2
RXCS3
RXDB3
TXCS3
TXDB3
RXCD
CACHEX

Memory Management Enable Register
Translation Buffer Invalidate All Register
Translation Buffer Invalidate Single Register
Performance Monitor Enable Register
System Identification Register
Translation Buffer Check Register
Serial-Line Unit 1 Receive CSR
Serial-Line Unit 1 Receive Data Buffer
Serial-Line Unit 1 Transmit CSR
Serial-Line Unit 1 Transmit Data Buffer
Serial-Line Unit 2 Receive CSR
Serial-Line Unit 2 Receive Data Buffer
Serial-Line Unit 2 Transmit CSR
Serial-Line Unit 2 Transmit Data Buffer
Serial-Line Unit 3 Receive CSR
Serial-Line Unit 3 Receive Data Buffer
Serial-Line Unit 3 Transmit CSR
Serial-Line Unit 3 Transmit Data Buffer
Receive Console Data Register
Cache Invalidate Register

S5E
5F

BINID
BISTOP

(hex)

VAXBI Node ID Register
VAXBI Stop Register

As you examine the formats of these registers, keep the following three conventions in mind:
O on read

Read as zero.

0 on write

Software must supply zeros.

Microcode does not force zeros or check for errors.
These bits are read back as written.

p:¢

Ignored on write.

Hex

Dec.

Name

Format

KSP

Kernel Stack Pointer

313029282726252423222120191817161514131211109 8 7 6 6 4 3 2 1

READ I

KSP

]

WRITE l

KSP

l
MLO-439-85

F-2

Internal Processor Registers on the KA820 Module

Hex

Dec.

Name

Format

ESP

Executive Stack Pointer

31302928272625242322212019181716151413121110 9

READ I

ESP

WRITE l

ESP

3210

|
MLO-440-85

SSP

Supervisor Stack Pointer

313029282726252423222120191817161514131211109

6 5

3210

READ [

SSP

]

WRITE l |

SSP

J
MLO-441-85

USP

User Stack Pointer

313029282726252423222120191817161514131211109

READ [

USP

WRITE I

USP

J
I

MLO-442-85

ISP

Interrupt Stack Pointer

31302928272625242322212019181716151 4131211109

READ l

ISP

WRITE I

ISP

8 7 6 5 4 3210

MLO-443-85

Internal Processor Registers on the KA820 Module

F-3

Hex

Dec.

Name

‘Format

POBR

PO Base Register

313029282726252423222120191817161514131211109 8 7 6 5 4 3 210

WRITE

lo o]

POBR

READ |1 oI

POBR

X XI

IX xl
MLO-444-85

POBR contains the virtual address of the beginning of the PO page table.

POLR

- PO Length Register

313029282726252423222120191817161514131211109 8 7

ASTLVL

WRITE lx X X X xI ) |x xI

POLR

AST'LV L

- POLR

READ IO 00O OI N IO OI

6 5 4 3210

)

J (
MLC-445-85

POLR tells the size of the PO page table in
longwords. ASTLVL stands for asynchronous system trap level.

10.

P1BR

P1 Base Register

313029282726252423222120191817161514131211109 8 7 6 56 4 3 2 1 0

WRITE |

|0 0

P1BR

READ I

P1BR

Ix xl
MLO-446-85

F-4

Internal Processor Registers on the KA820 Module

Hex

Dec.

Name

Format

P1BR contains the virtual address of the page table entry for the next unused page of P1 space. Initially this address 1s 4000 0000.

11.

Pi1LR

P1 Length Register

313029282726252423222120191817161514131211109

8 7

4 3

1 0

READ [OOOOOOOOOOI

- P1LR

WRITE Ixxxxxxxxxx

P1LR

]
MLO-447-85

P1LR tells the number of nonexistent page table
entries in P1 space.

12.

SBR

System Base Register

313029282726252423222120191817161514131211109

READ IE 0[

WRITE [x xI

8 7 6

2 1

SBR PHYSICAL ADDRESS
|

SBR PHYSICAL ADDRESS

IO O]
.

Ix x]
MLO-448-85

SBR contains the physical base address of the sys‘tem page table.

13.

SLR

System Length Register

31302928272625_24232221201918171615141‘312‘1‘1 10 9

876543 210

READ lOOOOOOOOOOI

SLR

]

WRITE lxxxxxxxxxxl

SLR

]
MLO-449-85

Internal Processor Registers on the KA820 Module

F-5

Hex

Dec. Name

Format
SLR tells the size of the system page table in
longwords.

16.

PCBB

Process Control Block Base

313029282726252423222120191817161514131211109 8 7

6 5 4 3 2

READ l

PCBB PHYSICAL ADDRESS

WRITE Io oJ

PCBB PHYSICAL ADDRESS

Io o]
MLO-450-85

PCBB contains the physical address of the process

control block.

17.

SCBB

System Control Block Base

313029282726252423222120191817161514131211109

READ L
WRITE IO 0|

SCBB PHYSICAL ADDRESS

]
0O0000O0O0O0O O]
MLO-451-85

SCBB contains the physical address of the system
control block (SCB). The SCB is a table of vectors
used to service exceptions and interrupts (see
Chapter 5).

F-6

Internal Processor Registers on the KA820 Module

Hex

Dec.

Name

Format

18.

IPLR

Interrupt Priority Level Register

313029282726252423222120191817161514131211109

7 6

READLOOOOOOOOOOOOOOOOOOOOOOOOOOOr

IPL

WRITE [xxxxxxxxxxxxxxxxxxxxxxxxxxx
MLO-452-85

Writing to IPLR with the MTPR instruction loads
- the processor priority field of the PSL. PSL bits
(20:16) are loaded from IPLR bits (4:0). Reading

IPLR with the MFPR instruction reads the processor priority field of the PSL.

19.

ASTLVL

Asynchronous System Trap Level

313029282726252423222120191817161514131211109

READ hOOOO0000OOOOOOOOOOOOOOOOOOOOI’]
ASTLVL

WRITE Ixxxxxxxxxxxxxxxxxxxxxxxxxxxxx

ASTLVL
MLO-453-85
ASTLVL tells the most privileged access mode
number for which an asynchronous system trap is

pending.

20.

SIRR

Software Interrupt Request Register
—

313029282726252423222120191817161514131211109

READ L

- ILLEGAL TO READ

WRITE |xxxxxxxxxxxxxxxxxxxxxxxxxxxx

]
SlRR]
MLO-454-85

Internal Processor Registers on the KA820 Module

F-7

Hex

Déc. Name

Format
Software can execute an MTPR instruction to

SIRR to request an interrupt at the level specified
in bits (3:0).

21.

SISR

- Software Interrupt Summary Register

313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0

READ [

SISR

WRITE[XOOXXOXOOOOOXXXX |

I
SISR

xJ
MLO-455-85

When software reads SISR, bits{(15:1) contain 1s
in bit positions corresponding to levels at which
software interrupts are pending. In addition software can post interrupts at several levels at once
by writing to SISR, setting any of the bits in the

~field (15:1). Software should not set bits (31:16).

22.

IPIR

- Interprocessor Interrupt Request Register

313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0

READ [

ILLEGAL TO READ

WRITE hooooooooooooooo

IPIR DEST. MASK

]
MLO-456-85

To send an interprocessor interrupt IPINTR), software should write this register with the destination ID mask. Bit (0) of the mask corresponds to

VAXBI node 0, and bit {(15) corresponds to VAXBI
node 15, and so on.

F-8

Internal Processor Registers on the KA820 Module

Hex

Dec.

Format

Interval Clock Control Register
|

_31773029282726252423222120191817161514131211109

876543210

READ

LJOOOOOOOOOOOOOOOOOOOOOOOIlIEIQOOOOK

WRITE

lIXXXXXXXXXXXXXXXXXXXXXXXlIIEI*EIXXX]1
INT SGL XFER
|

RUN

MLO-457-85

ERR (Read, write-1-to-clear)
Bit (31) Error

Hardware sets ERR if INT is already set and the
Interval Count Register (ICR) overflows. ERR indicates one or more missed clock ticks.
INT (Read, write-1-to-clear)
Bit (7) Interrupt

Hardware sets INT every time ICR overflows IfIE
is set, then the overflow generates an interrupt.

IE (Read, write)

Bit (6) Interrupt Enable
When set, IE enables the hardware to interrupt
the processor every time ICR overflows.

SGL (Write only)
Bit (5) Signal

Each time this bit is set, it increments ICR by 1, if
RUN is set.
XFER (Write only)
- Bit (4) Transfer

Each time this bitis set, the contents of NICR are
“transferred to ICR.

RUN (Read/write)
Bit (0) Run

ICR increments every microsecond when RUN is

“set. When RUN is clear, ICR does not increment
automatically.

Internal Processor Registers on the KA820 Module

F-9

Hex

Dec.

Name

Format

25.

NICR

Next Interval Count Register (Write only)

313029282726252423222120191817161514131211109 8 7 6 5 4 3 2

READ l

ILLEGAL TO READ

WRITE I

NICR

J
MLO-458-85

NICR is a reload re gister that holds the value to be
loaded into ICR when ICR overflows.

26.

ICR

Interval Count Register (Read/write)

313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0

READ l

ICR

WRITE l

ILLEGAL TO WRITE

J
MLO-459-85

Hardware increments this register every microsecond if ICCS bit (0) (RUN) is set.

27.

TODR

Time of Day Register

31 3029282726252423222120191817161514131211109 8 7 6 6 4 3 2 1 0

READ L

TODR

WRITE l

TODR

J
- MLO-460-85

TODR is a 32-bit binary counter driven by a precision clock source and incremented every 10 milliseconds. The counter cycles to zero after 497 days.

F-10

Internal Processor Registers on the KA820 Module

Hex

Dec.

Name

Format

32.

RXCS

Console Receive Control and Status Register

313029282726252423222120191817161514131211109

READ lOOOOOOO000000000000000OOI’IIEIOOOOOOI
DON

WRITE lxxxxxxxxxxxxxxxxxxxl’lxxxxxIIE XXXXXX]
LP

MLO-461-85

RXCS is the control and status register for receiving data from the console via serial-line unit 0. The

IE bit should be set to allow interrupts when the

RXDB Register receives a character. If the IE bit is
set and a character is received, or if a character is
received, and then the IE bit is set, an interrupt
occurs at IPL 20 and the Done bit is set.

If bit (12) (Loopback — LP) is set, then the serialline unit’s receiver is connected to the M chip’s in-

ternal loopback bus and disconnected from the
external serial line. Any number of the four receiver loopback bits may be set at once, but only
one of the four transmitter loopback bits should be
set.

33.

RXDB

Console Receive Data Buffer Register

313029282726252423222120191817161514131211109

READ[000.0000000000000I’I’IOOOOOOI

DATA

ERR BR

WRITE l

ILLEGAL TO WRITE

]
|

| 1
MLO;462-85

RXDB is the data buffer register for serial-line
unit 0. Bit (15), the Error bit, is set if the received

data has an overrun, or framing error.

Internal Processor Registers on the KA820 Module F-11

Dec.

Name

Format
"~

Hex

Bit (14), the Break bit is set, and the Error bit is
not set, if a (BREAK) character is received. When
software reads RXDB with an MFPR instruction,
microcode clears the Done bit in the RXCS
Register.

34.

TXCS

Console Transmit Control and Status Register

31 3029282726252423222120191817161514131211109 876543210

READ !000000000000OOOOOOOOOOOOl’IlEIOO0000]
L

WRITE lO 00000000O00O 000000 OILPIQiBAUDIlellEiO 00O OB]
v

BRE

BR
:

MLO-463-85

TXCS is the control and status register for trans-

mitting data to the console on serial-line unit O.

‘When the console transmitter is not busy, the
‘Ready bit is set, indicating that the TXDB Regis-

terisready toreceive a character for transmission.

is transmitted.

If the IE bit is set when the Ready bit gets set, or if
the Ready bit is set and the IE bit subsequently
gets set, an interrupt occurs at IPL 20. Software
can then write to the TXDB Register with an
MTPR instruction to transmit the next character.
The MTPR instruction automatically clears the
Ready bit. Ready stays cleared until the character
If bit (8) (Baud rate enable — BRE) is set, the contents of bits (11:9) are used to set the new baud
rate, both for the transmitter and receiver of
serial-line unit 0. If bit (12) (Send BREAK — BR)
is set, the serial line sends a continuous BREAK
signal until bit (12) is cleared. Software can generate breaks of any duration.

F-12

Internal Processor Registers on the KA820 Module

Hex

Dec.

Name

Format

If bit (13) (Loopback — LP) is set, the transmitter
for serial-line unit O is connected to the M Chip’s

internal loopback bus, and disconnected from the
external serial line (which is held idle). Only one of
the four transmitter loopback bits should be set,

but any number of the four receiver loopback bits
may be set at once.

‘The following is a table
of the baud rates that may
be selected in bits (11:9):
Bits (11:9)

35.

TXDB

Baud rate

000

150

001

300

010

600

011

1200

100

2400

101

4800

110

9600

111

19200

Console Transmit Data Buffer Register

313029282726252423222120191817161514131211109

READ L

ILLEGAL TO READ

WRITE loooooooooo'oooooooooo!

l
ml

DATA

MLO-464-85
TXDB is the data buffer register used to transmit

console data on serial-line unit 0. Bits (11:8) form
the ID field, which the CPU uses to distinguish between console commands and data. For writing
data, bits (11:8) are written with 0000. For sending a command, they are written with 1111. If the
ID field isset to 1111, the value in the data field is
interpreted as follows:
2 = Boot CPU.

3 = Clear Warm-Start flag.
4 = Clear Cold-Start flag.

Internal Processor Registers on the KA820 Module

F-13

Hex

Dec.

Name

Format

36.

TBDR

Translation Buffer Disable Register

READ hOO0000000000000000000000000000

313029282726252423222120191817161514131211109 8 7 6 5» 4 3210

WRITE lxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
!

FM
MLO-465-85

Processor initialization microcode sets or clears
bit (0) according to the BTB Enable bit in the
EEPROM (location 2009 817E). For normal opera-

tion software should ensure that bit O is clear at

power-up.

Software can write TBDR to disable the backup
translation buffer (BTB); however, this is only appropriate for diagnostics. TBDR has no effect on

the MTB (mini-translation buffer).

Disabling
the BTB does not work properly with Istream (instruction stream) addresses, because of
MTB and prefetcher interaction. Therefore soft-

ware should disable the BTB only when it is oper-

ating from physical addresses. Note that bits
(31:1) are undefined on a read.

37.

CADR

Cache Disable Register

313029282726252423222120191817161514131211109

READ EOOOO0000000000000OOOOOOOOOOOOOI $ |
FM

- WRITE Ixxxxxxxxxxxxxxxxxxxxxxxxxxx.xxxxl J
L

MLO-466-85

F-14

Internal Processor Registers on the KA820 Module

Hex

Dec.

Name

Format

Processor initialization microcode sets or clears
bit (0) according to the Cache Enable bit in the
EEPROM (location 2009 817E). For normal operation software should ensure that bit O is clear at

power-up.

Software can write CADR to disable the cache;
however, this is only appropriate for diagnostics.

Microcode interprets data written to CADR and
then writes to the cache control/status register
within the M chip. Note that bits (31:1) are undefined on a read, but bit (3) is normally read as 1.

38.

MCESR

Machine Check Error Summary Register

313029282726252423222120191817161514131211109

READ L

ILLEGAL TO READ

]

WRITE lOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOI
MLO-467-85

Software can use MCESR to clear the machine-

check condition flag within the CPU. When the
CPU begins to execute the machine-check handling software, and a machine-check condition is
detected before this flag is cleared with an MTPR
instruction, a CPU double error halt will result.
‘The data written to this register is ignored, but the
condition codes will reflect the data. Machinecheck software must write to MCESR before returning control to normal VAX code.

Internal Processor Registers on the KA820 Module

F-15

Hex

Dec.

Name

40.

ACCS

Format

Accelerator Control and Status Register (floating

point)

31 3029282726252423222120191817161514131211109

76543210

READ [OOOOOO00OOOOOOOOOOOOOOOOOOOOOOOIl
ON

WRITE lxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxl’]
ON
MLO-468-85

Software can disable the floating-point accelerator
chip (F chip) by writing 0 to ACCS. Power-up initialization microcode sets bit (0) to enable the F
chip after reading the enable bit in the EEPROM
(location 2009 817E).

44.

WCSA Writeable Control Store (Patch) Address Register

313029282726252423222120191817161514131211109

" READ lo 00000O0O0O o[

ADDRESS <0:13>

DATA <16:9> ]

WRITE ix X X X X X X X X xl

ADDRESS <0:13>

DATA <16:9> ]
MLO-469-85

This register is used with the WCSD Register for
reading the contents of the control store. The order

of the address bits is reversed from the normal
VAX order, and the data bits are permuted in an

unusual way.

Software can read a control store location, by executing a three-instruction sequence. First use an

MTPR instruction to write WCSA with a valid
control-store ROM address in bits (21:8) and
don’t-care data. Then use an MFPR instruction to

read WCSD. Then use an MFPR instruction to
read WCSA. No interrupts or context changes

F-16

should be taken within this three-instruction

Internal Processor Registers on the KA820 Module

Hex

Dec.

Name

Format

sequence, or the internal address and data state
may be lost. Addresses 0000 to 3BFF refer to

control-store ROM locations.

~ Addresses 3C00 to 3FFB refer to patch RAM locations. Addresses 3FFC to 3FFF refer to the CAM

Match Register. When software reads a ROM location that has been patched, the data returned is

the patch, not the original ROM word. See Section
3.4.2.3 in Chapter 3 for details.

45.

WCSD

Writeable Control Store (Patch) Data Register

31 302928272625242322212019181716151413121110_9 87 6543210

- READ l

DATA <8:0, 39, 17:38>

]

WRITE l

ILLEGAL TO WRITE

]
MLO-470-85

This register is used with the WCSA Register for

‘reading the patch RAM portion of the control-store

ROM/RAM chips. It contains 32 bits of the 40 bit
microword. The data bits are permuted in an unu-

‘sual way.

2FE

46.‘

WCSL

Wr-iteable Control Store Load Register

313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0

READ l
WRITE l

|
|

ILLEGAL TO READ

]

PHYSICAL ADDRESS OF A BLOCK OF PATCHES TO LOAD

]
MLO-471-85

Software can load control store patches by writing
WCBSL with the physical memory address of the
block of patches to be loaded, using the MTPR instruction. Microcode calculates a checksum for

Internal Processor Registers on the KA820 Module

F-17

Hex

Dec.

Name

Format

the block of patches and compares it with the

checksum stored with the block before loading. If
the checksum fails, the patches are not loaded, and
the V bit in the PSL is set to 1. Otherwise, micro-

code loads all the patches and clears the PSL V bit.
See Section 3.4.2.3 in Chapter 3 for details.

56.

MAPEN

Memory Management Enable Register

313029282726252423222120191817161514131211109

READ lOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO’EN]
WRITE Ixxxxxxxxxxxxxxxxxxxx.xxxxxxxxxxxIEq
MLO-472-85

Setting bit (0) enables memory management.
When bit (0) is clear, memory management is

disabled.

57.

TBIA

Translation Buffer Invalidate All Register

3130292827 26252423222120191817161514131211109 8 7 6 5 4 3 2 1 O

READ l

ILLEGAL TO READ

WRITE

0000000000000000000000000000000q
MLO-473-85

Software can invalidate the MTB, BTB, and instruction buffer by writing to TBIA. Microcode re-

sponds by clearing all of the valid bits in the
translation buffers. The data written to this register is ignored, but the condition codes will reflect

the data.

F-18

Internal Processor Registers on the KA820 Module

Hex

Dec.

Name

Format

58.

TBIS

Translation Buffer Invalidate Single Register

313029282726252423222120191817161514131211109 8 76543210

READ [

ILLEGAL TO READ

WRITE l

VIRTUAL ADDRESS <31:9>

l
X X X X X X X X J
-

MLO-474-85

Software can write TBIS to invalidate a specific
_

mapping entry in the BTB, the instruction buffer,

(

or the entire MTB.

61.

PMR

Performance Monitor Enable Register

313029282726252423222120191817161514131211109

READ hOOOOOOOOOOOOOOOOOOOOO0000OOOOOI’I
(

WRITE lxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxIJ
|]

PM
MLO-475-85

Bit (0) in PMR controls a signal visible to an external hardware performance monitor. This bit re-

<
\

fers only to the current process.

62.

SID

System Identification Register

313029282726252423222120191817161514131211109

READ ho 00010 1l CPU REV |

PATCH REV

UCODE REV

WRITE |xxxxxxxxxxxxxxxxxxxxxxxl1lxxxxxxx>j
T

MLO-476-85

Internal Procéssor Registers on the KA820 Module F-19

Hex

Dec.

Name

Format

Software uses the SID Register for system identification and revision control. Software should interpret the bits as follows:

Bits (31:24) identify the processor by a unique

type number. Type number for KA820 is 5.

| Bit (23) identifies the CPU module as a KA825
when set.

Bits (22:19) contain a binary number, which when
converted to decimal, indicates the module revision. For example, 1 = rev A; 2 = rev B.
Bits (18:9) contain the revision level of the microcode patches.
Bit (8) is the secondary patch bit (SP), which is
written by processor initialization microcode according to data in location 2009 816C in the EEPROM.
SP = 1

Either secondary patches are not
needed or they are needed and have
been loaded. |

SP = 0
|

Secondary patches are needed and
have not been loaded.

The code that loads secondary patches should set
bit (8) when it finishes loading the patches.
Bits (7:0) contain the revision level of the controlstore ROM/RAM chips.
Software can write only bit (8), and should write it
‘after loading the secondary patches.

63.

TBCHK

Translation Buffer Check Register

313029282726252423222120191817161514131211109 8 7 6 5 4

READ l
WRITE

3 2

ILLEGAL TO READ

TBCHK

Ixxxxxxxxxl
- MLO-477-85

F-20

Internal Processor RegiSters on the KA820 Module

Hex Dec. Name

Format

Software can check for the presence of a valid PTE in
the BTB by writing the corresponding virtual addressin TBCHK. The V bitin the PSLis set if the
PTEis valid.

The next 12 items describe the transmit and receive
status and data registers for serial-line units 1, 2,
and 3.

80.

RXCS1

Serial-Line Unit 1 Receive Control and Status
Register

313029282726252423222120191817161514131211109

READ IOOOOOOOOOOOOOOOOOOOOOOOOII’OOOOOO]
DON IE

WRITE lxxxxxxxxxxxxxxxxxxx *XXXXX
|

(

8 76543210

XXXXXX]

|E
MLO-478-85

RXCS1 is the control and status register for receiving data from serial-line unit 1. The IE bit should be
set to allow interrupts when the RXDB1 Register receives a character. If the IE bit is set and a character
is received, or if a character is received, and then the
IE bit is set, an interrupt occurs at IPL 20 and the
Done bit is set.

Ifbit (12) (Loopback — LP) is set, then the serial-line

unit’s receiver is connected to the M chip’s internal
loopback bus and disconnected from the external se- rial line. Any number of the four receiver loopback
bits may be set at once, but only one of the four transmitter loopback bits should be set.

Internal Processor Registers on the KA820 Module

F-21

Hex Dec. Name

Format

Serial-Line Unit 1 Receive Data Buffer Register

81.

RXDBI1

313029282726252423222120191817161514131211109

READ Eoooooooooooooool’l*loooooo
WRITE l

DATA

]

" ERR BR

ILLEGAL TO WRITE

]
MLO-479-85

RXDB1 is the data buffer register for serial-line unit
1. Bit (15), the Error bit, is set if the received data

has an overrun, or framing error.
Bit (14
), the Break bit is set, and the Error bit is not
set, if a (BREAK) character is received. When software reads RXDB1 with an MFPR instruction, mi-

crocode clears the Done bit in the RXCS1 Register.

82.

TXCS1

Serial-Line Unit 1 Transmit Control and Status
Register

31302928272625242322212019181716151413121110
9 876543210

READ IPOOO00000000000000000000|}IIE0000OO]
RD

WRITE lOOOOOOOOOOOOOOOOOOIL ’IBAUD I« IE[D 00O00O 0]
1

BRE

MLO-480-85

TXCS1 is the control and status register for transmitting data on serial-line unit 1. When the console
transmitter is not busy, the Ready bit is set, indicat-

ing that the TXDB1 Register is ready to receive a

character for transmission. If the IE bit is set when
the Ready bit gets set, or if the Ready bit is set and
the IE bit subsequently gets set, an interrupt occurs
at IPL 20. Software can then write to the TXDB1
Register with an MTPR instruction to transmit the

next character. The MTPR instruction automatically
clears the Ready bit. Ready stays cleared until the
character is transmitted.

F-22

Internal Processor Registers on the KA820 Module

Hex Dec.

Name

Format

If bit (8) (Baud rate enable — BRE) is set, the contents of bits (11:9) are used to set the new baud rate,

both for the transmitter and receiver of serial-line
unit 1. If bit {12) (Send BREAK — BR) is set, the serial line sends a continuous BREAK signal until bit
(12) is reset. Software can generate breaks of any

duration.

—

If bit (13) (Loopback — LP) is set, the transmitter for
serial-line unit 1 is connected to the M Chip’s inter-

nal loopback bus, and disconnected from the external
serial line (which is held idle). Only one of the four
‘transmitter loopback bits should be set, but any
number of the four receiver loopback bits may be set
at once.

The following is a table of the baud rates that may be
selected in bits (11:9):

Bits (11:9)

83.

TXDB1

Baud rate

000

150

001

300

010

600

011

1200

100

2400

101

4800

110

9600

111

19200

Serial-Line Unit 1 Transmit Data Buffer Register

313029282726252423222120191817161514131211109

READ L

ILLEGAL TO READ

WRITE loooooooooooooooooooooooo]

DATA

]

‘MLO-481-85
TXDBI1 is the data buffer register used to transmit
|

)

data on serial-line unit 1.

Internal Processor Registers on the KA820 Module

F-23

Hex

Dec.

Name

Format

NOTE
The operation of the registers for serial-line units 2
and 3 is exactly the same as the operation of the
registers for serial-line unit 1.

84.

RXCS2

Serial-Line Unit 2 Receive Control and Status
Register
y

| 85.

RXDB2

’56

86.

87.

TXDB2

88.

RXCS3

TXCSZ

Serial-Line Unit 2 Receive Data Buffer Register

Serial-Line Unit 2 Transmit Control and Status

Serial-Line Unit 2 Transmit Data Buffer Register

Serial-Line Unit 3 Receive Control and Status
Register

89.

RXDB3

90.

TXCS3

Serial-Line Unit 3 Receive Data Buffer Register

Serial-Line Unit 3 Transmit Control and Status
Register

91.

TXDB3

92.

RXCD

Serial-Line Unit 3 Transmit Data Buffer Register

Receive Console Data Register

31302928272625242322212019181716151413121_110_9 8 76543210

READ hooooaooooooooool’loool4
BUSY

FROM NODE

WRITE lo 0000000000000 O olxlo 0 OITONODEI

}

F-24

‘

Internal Processor Registers on the KA820 Module

‘

DATA

MLO-482-85

Hex

Dec.

Name

Format

The RXCD Register provides for interprocessor
console communications on the VAXBI bus. Read-

ing this register picks up a console character (if
any) that has been sent to this processor from a
processor on another VAXBI node. Writing the

-RXCD on another processor sends a console character to that processor.

Bit (15) is the Busy bit. When software sends a

character, this bit is sent as 1, to indicate that the
receiving register is busy. When the receiving
processor executes an MFPR instruction to read

the character, its microcode resets the receiving
- processor’s RXCD bit (15) to 0.

Bits (11:8) identify the sender’s VAXBI node

number.

When software reads a not-busy RXCD Register

(bit (15) = 0), the MFPR microcode sets the PSW
V-bit. When software reads a busy RXCD Register,
the MFPR microcode clears the PSW V-bit.
When software writes to a busy RXCD Register on
a remote node (bit {(15) = 1), no data is sent and

the sending MFPR sets the PSW V-bit.

93.

CACHEX

Cache Invalidate Register

313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0

'READ L

WRITE hx X X X X X X 0

ILLEGAL TO READ

]

CACHEX PHYSICAL ADDRESS BITS <28:8>

]

MLO-483-85
Software can invalidate a page in the cache by
writing physical address bits (28:8) in bits ¢(20:0)

of CACHEX. The CPU clears the four valid bits of
up to eight cache tags at one time. Use CACHEX
when you use the KA820 module as an I/0
processor.

Internal Processor Registers on the KA820 Module

F-25

Hex

Dec.

Name

Format

BINID

VAXBI Node Identification Register

313029282726252423222120191817161514131211109 8 76543210

READ IOOOOOOOOOOOOOOOOOOOOOOOOOOOOI NODEI
WRITE l

ILLEGAL TO WRITE

l
MLO-484-85

Software can read BINID to determine the VAXBI
node ID of the processor. Bits (3:0) contain the

VAXBI node address. Microcode obtains the address from the BIIC Control/Status Register during processor initialization.

95.

BISTOP

VAXBI STOP Register

313029282726252423222120191817161514131211109

READ l

543210

ILLEGAL TO READ

WRITE Ioooooooooooooood

]
VAXBI MASK

l
MLO-485-85

Software uses BISTOP to initiate a VAXBI STOP
transaction. BISTOP is a write-only register that
software can write with a mask of VAXBI nodes to
be stopped.

' F-26

Internal Processor Registers on the KA820 Module

Appendix G

Contents at

Console

Change to

Address

Mode Entry

Macrocode

Comments

PCntl CSR

2008 8000

Varies

—

2008 0000

xxxx 0105

xxxx refers to the

DTYPE

bb+00

CPU revision
code, microcode
patch revision,
and secondary
patch loading

VAXBI CSR

2008 0004

rrtt 0803

rrtt refers to the
BIIC revision and

bb+ 04

type

Bus Error

12008 0008

bb+ 08

Error

2008 000C

Interrupt

bb+0C

0000 0000

—

0000 0000

—

0000 0778

—

Control
Register
BCI Control

2008 0028

bb +28

RXCD

2008 0200

|
0000 0000

0000 0000

—

bb+200
RO

Random

—

Random

—

Random

—

Random

Boot device

See Chapter 4

{ddxn}
(Continued on next page)

Contents at

Console

Change to

Address

Mode Entry

Macrocode

Comments

Random

—

Random

Boot control

See Appendix I

flags

Random

—

Random

—

Random

—

Random

—

R10

Random

Halt PC

—

R11

Random

Halt PSL

—

R12

Random

Halt code

—

- R13

Random

—

R14

Random

Starting
address of

—

primary

bootstrap

- PC
TBDR

R15

-Random

'Random

—

IPR 24

0000 0000

Affected by
EEPROM
contents

CADR

IPR 25

0000 0000

0000 0000
|

Affected by
EEPROM
contents

ACCS

IPR 28

0000 0000

Affected by
EEPROM
contents

MAPEN

G-2

IPR 38

0000 0000

yenal

EEPR'OM Contents

Address

Contents

FIRST EEPROM CHIP

2009 8000

FF constant used in EEPROM test

2009 8002

~ 55 constant used in EEPROM test

2009 8004

14 bytes must be zero

2009 8020

2009 8024

10 bytes, module serial Number
2 characters = plant code
3 characters = numeric date code YWW

(Y = year, W = week)
o

5 characters = numeric module serial number

2009 8038

6 bytes, load server address (for the AIE module)

2009 8044

70 bytes unused and = 0

2009 80D0

8 bytes unused; reserved for DIGITAL CSS

2009 80EO
to

|
|

2009 812E

48 bytes reserved to DIGITAL

2009 8130

8 bytes unused; reserved for users

2009 8140

17 bytes reserved to DIGITAL

2009 8152

2009 8154

1 byte = AA, the constant that is used in the EEPROM test

2009 8156

1 byte unused

2009 8158

4 bytes for the VAXBI self-test timeout constant

2009 8160

incremental value = 0.2 microsecond increment
4 bytes unused

~ (Continued on next page)

Address

Contents

VAXBI Device Type Data

2009 8168
|

2 bytes, VAXBI device type for module = 0105 (hex) for
KA820

2009 816C

2 bytes, VAXBI revision level for module
bits (15:11)
= CPU revision
bits (10:1)
= patch revision
|
bit (0)
= secondary patches not needed, default
=1

2009 8170
2009 8176

3 bytes unused
1 byte for RCX50 self-test disable
bit (4): RCX50 self-test disable (0 = enable,
1 = disable), default = 1
bit (3) must be zero
bits (7:5,2:0) =0

Console Source Data

2009 8178

1 byte

bits (3:0) = VAXBI node number of logical console
(default = 2)

bits (7:4) must be zero

2009 817A

1 byte must be zero

2009 817C

1 byte, UARTO baud rate — default = 1200 baud
bits (7:0) = Baud rate as follows:
30 — 150 baud
34 — 2400 baud
31 —
32 —

300 baud
600 baud

33 — 1200 baud
2009 817E

35 —
36 —

4800 baud
9600 baud

37 — 19200 baud

F chip, BTB, and cache disable bits
bit (0) (1 = F chip disabled; 0 = F chip enabled),
default = 0

bit (1) (1 = BTB disabled; 0 = BTB enabled),
must be zero

bit (2} (1 = cache disabled; 0 = cache enabled),
default=0

bits (7:3) must be zero

2009 8180
to

2009 81CE
- 2009 81DO
|
2009 81E0
2009 81FC

2009 81FE

40 bytes unused

8 bytes: 40-bit checksum of control store with primary
patches installed
2 bytes reserved to DIGITAL
1 byte: constant 33 used in EEPROM test
1 byte: constant 01 used in EEPROM test

EEPROM Boot-Code Section.
2009 8200

4 bytes of checksum for 1020 bytes (decimal)
of boot code

2009 8208

Boot dispatcher

2009 87FE

(Continued on next page)

H-2

EEPROM Contents

Address

Contents

EEPROM Patch Section

2009 8A00

4 bytes of checksum for all the patches

2009 8A08

1 byte for the starting CAM address

2009 8A0A

2 bytes showing the number of patches

2009 8AOE

Start of patches,

7 bytes per patch...

2009 BFFE

up to 984 patches (decimal)

SECOND EEPROM CHIP
2009 C000

Default boot device designation of form ddnu

2009 C008

Default T/M boot device designation of form

2009 C010

Boot-code descriptor A (8 bytes)

2009 C020

Boot-code descriptor B (8 bytes)

2009 C030

Boot-code descriptor C (8 bytes)

2009 C040

Boot-code descriptor D (8 bytes)

2009 C050

Boot-code descriptor E (8 bytes)

2009 C060

Boot-code descriptor F (8 bytes)

(4 bytes)

ddnu (4 bytes)

2009 CO70

Boot-code descriptor G (8 bytes)

2009 C080

Boot-code descriptor H (8 bytes)

2009 C090

Boot-code descriptor I (8 bytes)

2009 COAO

Boot-code descriptor J (8 bytes)

2009 COBO

Boot code — including chksum
8104 bytes (decimal)

2009 FFFE

Boot code

LOCATIONS THAT CAN BE READ AND WRITTEN USING CONSOLE

COMMANDS E/E AND D/E

EEPROM

Typed

Address

Location

Configuration Use

2009 8170

to
2009 8174

00-02

Reserved for future use

2009 8176

RCX50 self-test enable

2009 8178

Bits ¢(3:0): VAXBI node number of

2009 817A

Unused

logical console
2009 817C

UARTO baud rate

2009 817E

F chip, BTB, and cache disables

2009 8180

08-23

16 bytes unused

2009 81B8

EEPROM Contents

H-3

Appendix |
ire Boot Control Fl
ag

You can control various phases of the boot procedure by setting bits in General Purpose Register R5 with the console command B/R5:{data) (see Chapters 3 and 4). These bit functions are defined by the VMB primary boot
routine and by VMS. Note that the value -1 in R5 is reserved to DIGITAL.

R5 Bit Symbol
(0>

RPB$V_CONV

Function
Conversational boot. At various points in the system
boot procedure, the bootstrap code solicits parameters
and other input from the console terminal. If bit (4)
is also set, the VAX Diagnostic Supervisor should
start, enter menu mode, and prompt you for devices
to test.

RPB$V_DEBUG

Debug. If this flag is set, VMS maps the code for the
XDELTA debugger into the system page tables of the
running VMS system.

(2)

RPB$V_INIBPT

Initial breakpoint. F RPB$V_DEBUG is set, VMS executes a breakpoint (BPT) instruction immediately
after enabling mapping.

(3)

RPB$V_BBLOCK

Secondary boot from boot block. The secondary bootstrap is a single 512-byte block whose logical block
number is specified in R4.

(4)

RPB$V_DIAG

Diagnostic boot. The secondary bootstrap is an image
called SYSMAINT DIAGBOOT.EXE.

(5)

RPB$V_BOOBPT

Bootstrap breakpoint. This stops the primary and secondary bootstraps with a breakpoint (BPT) instruction before testing memory.

(6)

RPB3V_HEADER

Image header. The transfer address of the secondary
bootstrap image comes from the image header for
that file. If RPB$VHEADER is not set, control shifts
to the first byte of the secondary boot file.

(Continued on next page)

I-1

R5 Bit

Symbol

Function

(7>

RPB$V_NOTEST

Memory test inhibit. This function sets a bit in the
PFN bit map for each page of memory present, inhibiting the memory test.

(80

RPB$V_SOLICT

(9>

RPB$V_HALT

File name. VMB prompts for the name ofa secondéi'y

bootstrap file.

Halt before transfer. VMB executes a HALT instruction before transferring control to the secondary bootstrap.

(13

RPB$V_MEMTEST

Specifies that a more extensive algorithm be used
when testing main memory for uncorrectable hardware (RDS) errors.

(155

RPB$V_AUTOTEST Used by the VAX Diagnostic Supervisor.

(165

RPB$V_CRDTEST

Specifies that memory pages with correctable (CRD)
errors not be discarded at bootstrap time. By default,
pages with CRD errors are removed from use during
the bootstrap memory test.

(31:28) RPB$V_TOPSYS

Specifies the top level directory number for system
disks in multiple systems.

I-2

Software Boot Control Flags

Appendix J

Sample Bootstrap Code

J.1

EEPROM Bootstrap Dispatcher
.TITLE KAg822 EEPROM BOOT DISPATCHER

IDENT ,V1.85/

(c)

1985 BY

THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COFIED

ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE INCLUSION
OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER COPIES THEREOF
MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY OTHER PERSON. NO
TITLE TO AND OWNERSHIF OF THE SOFTWARE IS HEREBY TRANSFERRED.

THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE,

SHOULD NOT BE CONSTRUED AS A COMWMITMENT BY DIGITAL EQUIPMENT CORPORATION.

AND

DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS
SOFTWARE ON EQUIFMENT THAT IS NOT SUPPLIED BY DIGITAL.

LY ]

L X1

i t+

.PAGE
i ++
i

FACILITY:

AUTHOR:

ABSTRACT:

R3 should contain a 4-byte ASCII device specification aof the form

LT
e

This

LX)

“u e

KAg2@ EEPROM BOOT CODE DISPATCHER

routine interprets the boot command device specification in R3.

ddxn, where dd is the mnemonic for the generic device type, x is
the VAKBI node number and n is the unit number. When R3 is set to B,
indicates that the default boot device is being selected. If the
string is valid, an attempt is made to match the 2-character
device code with one of the boot device descriptors in the EEPRON.
If
a match is found, control is passed to the appropriate boot
device. If no match is found, or if an invalid string was
detected, the message "?44" is printed on the console and the CPU
halts. All qualifiers to the boot command and the handling of the
cold and warm restart flags are handled by the CPU microcode.

INPUTS:

R3 preloaded with boot device specification of form ddxn.
RS set to 11 hex if a CRD boot is to be performed.

Qutputs:
RE - destroyed
R1 - VAKBI node number
R2 - destroyed

R3 - unit number
R8 - destroyed

e
we . e

-a

L 1]

LT3

This routine resides at offset 184 in the EEPROM.

REVISION HISTORY

PAGE

Pfiez

BOOT_DSC = “Hace
PAKET RAM = “X20090080

THDE = 35

THCS = 34
RDY = 7

. LONG

WF63F4A10

L S
i CHKSUM FOR
i

FILE HANDLING

STARTKABR:

MOVL

22(R@),R3

in R3 (dev D).

BNEQU

1000%

Br if non @-else load with

MOVL

-2(R@),R3

“z
“me
e
~o o

L 1]

#°%11,R5

9208%

dev desc.

BNEQU

#16,#16.R3,R2

BSREE
MOVL
MOVL

CONVERT
R8,R1
R3,;R8

BSBE
MOVZBL

CONVERT
R8,R3

Sample Bootstrap Code

#8,#8,R3,R8

LT3

EXTZV

EXTZV
|

J-2

Version number
|
Device designation - reversed

R3
ianas

1000%:

Size of file

TSTL
- BNEQ

CHPR

9085

Br to start éf code.

PAKET_RAM+BOOT _DSC+2,RE ; Make R& point to 1st boot
LT

HOVL

185
/AK-

WORD
ASCITI

|
STARTKAGE
ENDKAZ - STARTKAS

A 1]

STARTKAS : :
- BRB
.HORD

*%***%&**************************************&*********************%*

Is R3 = @7
Br if no.

This a CRD boot?

Br if no to use normal default
(dev A).
Fut CRD default descriptor

normal default.
Load default device designation.
Put device mnemonic in R2.
Fut VAKBI node # in RB 1o be
converted.

Go convert VHHBI node io binarg
Put it in R1.
Setup to convert unit §.
Go convert unit number.

Put binary unit number in R3.

L. X1

Match the 2-character device generic code in R2 with the same field

of the boot device descriptors.

the boot routine.

and halt.
LT

RS, 500%

SOBGTR

K2, (R4
MATCH
#6,R0

#4,R%

is found,

we dispatch to

Loop count in R8.
Device match?

Br if yes.
|

MOVZBL
CHMPW
BEQL
ADDB2

If a match

print a hexadecimal
46 on the console,

Update pointer.

Sem$:

Otherwise,

Br if more locations to check.

Nothing matches - print error message and halt.

INVALID_DEV:

o
MOVZBL
#13.RQ
BSE
10004
MOVZBL
#1@,R®
BSE
100@%

;

MOVZBL

#°X3F.
R0

BSB

MOVZBL

10008

#°%34,R0

;

BSE

MOUZBL

1000%

#°434.R0

;

BSE

1000%

HALT

Load (CR).

;
;

;
;
;

i Halt.

Go send

it.
Load a line feed.
Go send it.
Load a "?" into R@.
Go send it.
Load a "4" into RO,
Go send it.
Load a "4" into RO.
Go send it.

}

i
1022%:

2000%:

Subroutine to print the character in R@ on the console

MTFR

Ra, HTADE

HTHCS,R&

i Wait until character prints.

BRC

HRDY,R@, 2000%

i Dittao.

MFPR

Laad character into data buffer.

RSB

Print complete -

return.

i A match was found - dispatch to boot routine.
MATCH:

JMF

GO to boot

routine.

Subroutine to convert ASCII character in R8 to binary and check if valid
(@ - 15 decimal). If not, an invalid boot device message is printed on
the console and a halt is executed. Note that it is the converted value

EBS

SUBR

#"H30.R8

ERE

200%

SUBR

H"%37.R8

;

Branch if

;

Subtract out ASCII.

Character is in range A thru F.

its
A thru F.

Character is in range @ thru 9.

2004

Verify character is in the

oo &

”
:
1004

#'%6,Re, 1008

b X

ONVERT:

this will

that is checked. Therefore, if the console accepis
a ":",
convert to an AlChex) which is valid.

range A to F hex.

CHPB

#"%OF,R8

;

Is character valid

BLSSU

INVALID DEV

;

;
;

Delimit the end.
|
Kemove for file inclusion.

(2-15)7?

if no.

RSE
ENDKA®:
. END

STARTKAS

Sample Bootstrap Code

J-3

J.2

Sample RX50 Bootstrap Code
R¥5@ ROM BOOTSTRAF ROUTINE
V1 .14~

ofoe

.TITLE
.ident

THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COFIED
ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE INCLUSION
OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER COPIES THEREOF
MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY OTHER FERSON. NO
TITLE TO AND OWNERSHIF 0OF THE SOFTWARE IS HEREBY TRANSFERRED.

THE INFORMATION IN THIS.SUFTNHRE IS SUBJECT TO CHANGE WITHOUT NOTICE. AND
SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT CORPORATION.
DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS
SOFTWARE ON EQUIFMENT THAT IS NOT SUPPLIED BY DIGITAL.

LT}

L X1

LT}

i + +
i
i

FACILITY:

i
i

VARH#EZ20@ Device-Specific RXS@ ROM BOOT

i
i

AUTHOR

i
i
i

ABSTRACT:

i
i
i

i
i

This routine reads in the boot block from the RK5@ diskette and
executes it. This is LBN @ which is track 1 sector 1.
The routine assumes that the standard VAKX boot block with the
first 3 longuwords is set up as follows:

}

1st longword:
2nd longword:

}

3rd longword:

Number of blocks in primary boot
LBN of primary boot (swapped)
Load add relative to start of good 64k (208 hex)

i
i

The boot block code starts immediately after the third longword.

i
i

Drive and disk selection are mapped to the unit number as follows:

UNIT
UNIT
UNIT
UNIT

i
i
i
i
i
i
}

REVISION HISTORY:

i
i
i

J-4

Sample Bootstrap Code

##2
#1
#2
#3

Drive
Drive
Drive
Drive

@ Disk @
@ Disk 1
1 Disk
@
1 Disk 1

.page

.sbttl

Declarations

READ
DONE
RECMD
REBUF
RXGO
RETRK
RKSEC
RXCA

=
=
=
=
=
=
=
=

"0100
010
“D4
“029
024
“06
“01@
*p22

i RX50 drive specific definitions

DZ_DEV_TYPE = 64

BOOT_CODE_START = 12-"K2o0
:

in boot block

RCHS® _REGS = "X200BR20R
SIGN _BIT = “K7

i Device type code

; Offset to start of boot
i

code

i RCHSB register space
i Sign bit position (bit )

page

.sbttl
3

Boot the boot block

I
A

.long
5

I3 T 363 360022636 363022236 30336600

Hea2DE4RD

300

Patch chksum

RN
I I I
H IR RN R

Functional Description

i Brings in Logical Block @ from the RX52 drive @, diskette 2
i

Inputs

i
;
i

K3
R3
SF

Implicit

;

- Unit number of boot device
- Saftware boot cgntral flags
- Base address +
K208 of b64kb of good memory
inputs:

LEN of the boot block is @

i
i

Boot block is to be read into -208<(sp) - i.e. start of 64k block
Hfer address of boot block code is at BOOT_CODE_STARTCSP).

Outputs:

i
i
i
;
;
;
j

R@
k1
ke
K3
R3
K6
SP

(inputs to BOOTBLK and primary boot)
-

Device type code for RW52 console device (64.)
@ Cnot UNIBUS or MASSBUS)
@ ¢not UNIBUS or MASSBUS)
Unit number of boot device
Software boot control flags
Physical addresg of RR52 mini driver
Base address +
208 of 64kb of good memory - passed

;

parameter

i Boot file header

STARTCSBOOT:
RRo@_BOOT:

BRER
.WORD

STARTCS

Br to start of code

ENDCSRBOOT-STARTCSRBOOT
; Size of file in bytes

CWORD

114

i Version nunmber

ASCIT

/5Cr

Device code reversed

Start of boot code

Sample Bootstrap Code

J-5

Move stack into middle of
2nd page to enable boot

CLRL

-*¥300C(SP)

JSB
BLBS
HALT

'B*DRIVER$_R%5®

PUSHAB

LY
L X

Load R® with device type code.

LEN to read is set to Q.
Push base add of good 64k on stack
(Load address of boot block).
Go read in a block.
Br if no error.
ERROR - HALT.
Make R6 point to start of driver.

L Y]

SUBL
JMF

ar MASSBUS).

#D2_DEV_TYPE,R@

B"DRIVER$_RX5@,R6
#'%100-4,5P

BOOT_CODE_START(SP)

LX)

MOVZBL
MOVAB

into 1st page.
CLR R1+R2 (not UNIBUS

RA,100%

100%:

LT3

L 11

2000%:

CLRQ

LT}

“-e

#°%100,
5P

ADDL

L X3

STARTCS:

Restore SP to original pasition.
Fass control to the boot block.

.page

.sbttl

R¥2@ MINI DRIVER

R¥5Q mini driver.

Reads in a logical block.

It is called as a subroutine. The physical address in which the
block is to be loaded must be placed on the stack prior

to calling,

which will put it at 4(SP) upon entry.

Inputs:
RS

4(5P)

logical block number
physical load address

Outputs:
R

simple completion status - low bit set = success

LT3

L X

HE X J

DRIVERS_ RKSQ:

#fM(RErR3,ES,RB;RT,RBJR9) i Save volatile registers.

*EEA¥E (affects offset @ 3000§)¥¥kE*%
Convert unit number in R3 to drive and disk select.
Convert LBN in R8 to physical device address.

N a

PUSHR

|
Unit Number

LBN

L Xl

INPUTS:
R3

L X3

L X

QUTPUTS:
Ré
track number
RS
sector number

J-6

NOTES:

SIDE = @

TRK =

BN DIV 1@

RS drive and disk select data

BN = LBN MOD 902 (BLK # on a side)
BNA = BN MOD 12 (BLK # on a track?

Convert unit number in R3 to disk and drive select
Dec unit number so unit 1 select
DECL
k3
i
drive 0.
}

CMPRB

k3. #3

BGTRU
ADDB3
CLRL

ERROR
R3,R3,RS
R9

Sample Bootstrap Code

Is unit number valid (in range @-3)7

} Br

if no.
Shift
to left and put

Clear for EDIV.

in RS.

EDIV
ADDLZ

ADDLZ

#1@..R8,R6,R7
R6.R#
#2.R8
#53.,KR7
R7.,R%

i
i
i
i
i

R6{=TRK R7{=BNA
RB(== BN + TRK
R8{==
(BN+TRK)#*Z
R7(= BNH!S
RB{==(BNA/D + itBN+TRKJ**31

EDIV

#1@.,R8, Rfl k&

R8 {(==R8 MOD 10

INCL

Make sectors start at 1.

INCL

Make tracks start at 1.

CMFB
BNER
CLRL

#80.,R6
3004
k6

i
i
;i

Is this the last track on surface?
Br if no.

MULLZ
DIVL2

Set track to 8

(last track=@).

i Conversion of LBN to physical address is complete.
i

Read in a single block using the physical

300%:

3008%:

S0a%:

MOVL

HRCHS@_REGS,R2

Load K2 with RRS5® register add.

CLRL

Preset

RISH

HREAD, RS

Combine read code with disk

MOVEB

RS, RRCMDCR2)

and drive select.

MOVL
MOVE

4+28C(5P),K5
R6,RRTRK{R2)

i
i

Move physical address nf buffer to RS.
Select the track.

MOVEB
MOVEB

RE,RRSEC(R2)
Ba,REGOCR2)

i Select the sectar.
i Start the read sector operation.

BITR

BDONE, RECMDCR2)

BEQL
BRS

702%:

information.

return status to error.

5et func to read sector.

Done yet?

51"}
i Br back to wait for done.
HSIGN_RIT,RKCMDCR2),ERROR ; Br if errar.

TSTH

RHCHIREI

Clear silo address.

MOVE
SOBGTR

REBUFCR2), (RS)+

Load a byte

K9,700%

into the buffer.
Loop until entire block is lnaded

Indicate success.

Return.

Delimit the last location.

HOVZKL
INCL

ERROR:

FOFR

RSE

#512,R9
R@

i Load loop count.

H#°M{R2,R3,R5,R6,R7,RE,RY) ; Restore volatile registers.

ENDCSROOT :
.end

STARTCSBOOT

Remove for multifile

inclusion.

J.3 Sample
DU Series Bootstrap Code (MSCP Devices)
LTITLE

VAXH#B202 BUA MSCP Boot ROM

sV1.01,

LX)

JIDENT

DIGITAL EQUIFPMENT CORPORATION,

MASSACHUSETTS.

ONLY

LX)

THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE WSED AND COPIED

OF THE ABOVE COPYRIGHT NOTICE.

THE

TERMS

SUCH

LICENSE

AND

WITH

THE

INCLUSION

THIS SOFTWARE OR ANY OTHER COPIES THEREOF

MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY OTHER PERSON.
TITLE TO AND OWNERSHIF OF THE SOFTWARE IS HEREBY TRANSFERRED.

LX)

ACCORDANCE WITH

THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE, AND

L _X]

SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT CORPORATION.

DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS
SOFTWARE ON EQUIPMENT THAT IS NOT SUPPLIED BY DIGITAL.

Sample Bootstrap Code

J-7

FACILITY:

;

VAX#2208 DU Boot Device Type Bootstrap ROM
ABSTRACT:

;

This ROM code reads in the boot block from an MSCP speaking device
which adheres to the UQSSP port specification. It supporis the
VAXRI to UNIBUS adapter (BUAY, the VAKBI Low End Storage
Interconnect Adapter (BLA) and the VAXBI to Disk Adapter (BDA).

i
i
i
i

The code reads in the boot block and executes it. It assumes the
boot block to be the VAX standard boot block. The default addresses
for the SA and IP registers are always used. There is no mechanism
for controller selection on a given node.

AUTHOR:

;

REVISION HISTORY:

.PAGE

)

]

HMemory Map 0f Boot Frocess

Base of good
memory +

LT}

.SBTTL

1FF

SP Passed to ROM

(

LX
e

]

boot block

Available for file
brought in by

caode boot block

communications
area

{

{--- Host

FARA

{--- Available for file
brought in by

boot block

Intested nmemory

. There is no check that the BUA passed its self-test.

. There is no mechanism for using an address other than the

No check that.selected node has a BlA.

default address.

Notes

L X1

.SBTTL
e

.PAGE

J-8

- -

]

[}

]

[}

]

FFFF

Sample Bootstrap Code

—

L1}

The code for the BLA and BUA is identical. The BDA has
sighificant differences as follouws:
1. The IP address reg is in the VAXBI node space at offset F2.
2 All addresses used by the BDA are physical. Addresses used
by the BUA and BLA are relative to the start of good 64k.
This affects the address of the communications area in the
initialization table and the addresses in the buffer
descriptors.
The BDA does not initiate initialization when the IP register
is written. It is started by sett1ng the Node Reset (NRST)
bit in the VAXRBI CSR.

¥ERRESTRICTIONS®#%

LX)

The communications area starts at FARR.
If the boot block
loads a program into the first 64k of good memory, the
communications area will be overwritten if the program is
too big. The boot block can however load larae programs
starting beyond the communications area. This is the case
for VDS, which loads into the second goond 64k.

) The boot block and any program that it loads must be position
independent if it is to be guaranteed to work properly.
Otherwise problems will arise if the start of good memory is
location Q.

not at

BOOT_CODE_START

i Boot code device type for UDA BLA

W =~

BUA_BLA _DTYPE

BDA_DTYFE

inonon

.PAGE
.SBTTL Declarations

;

12 - "Heoe

Boot code device type for BDA

UDA I-0 ADDRESSES

DU_UDAIF = “0@12150
.

DU_UDASA = DU_UDAIF +

SA = DU_UDASA -

DU_UDAIP

i Address of initialize and polling
:

Address of status and address

Uffset between the registers

Bit positions for initialization

ERR

Error bit

i
i

Step 4 bit
Step 3 bit

Step 2 bit
Step 1 bit

Bit definitions for

initialization

:nmmmmm1

i G

STEF

102220

Step indicator

Host communications area definitions

Sample Bootstrap Code

J-9

COWN = “Hepooaod

Ownership of packet,
1 = UDA

@ = host,

; Communications area offsets
e

area

o»

RING = @

128 bytes needed for host comm

RMSG = RING + 12

RCMD = RMSG + 64
i

e e

COMM_END = RCHD +48

Host communications area
Buffer for response packet
from UDA

Buffer for command packet to UDA
Length of comm. area - 4 bytes

Commandsresponse packet definitions

OF_ONL = 011

On-line command op-code
Kead command op-code

P_UNIT =

Unit number offset into
packet
LBN offset into packet

"D41

P_LBN

= 28

P LEN

LX)

OP_RD

16
32
&
12

18
-4

Buffer descriptor offset into packet
Shadow unit number
Op-code offset into packet
Byte count offset into packet
End packet status offset
Length of packet offset

(1431)

s
L X
-0
LX
e
e
e
X

§5T = (181@)

VAKXRI device code for BUA

VAXBI device code for BLA

VAKBRI device code for BDA
VAKBI node address space start
Offset to VAXBI CSR register
to BDA IP reg
iffset

Offset to next VAXKRI node

|
Add of 1st adapter window
0ffset to end of adapter window
Offset to starting address
Offset to end address
0ffset to BUA map reg
Valid bit for map registers
Node reset bit in BICSK

.PAGE

BUA Initialization and Set-up

t++

FUNCTIONAL DESCRIPTION:

Loads Rlfl-with'the‘base address of the VAXBI node space:s then

performs setup based on the node type as follows:

L_J 8

LT}

SBTTL

LY
ee

VALID =

LTl

BIDEVCODE_BLA = “X1@3
RIDEVCODE_BDA = "H1QE
BRI _ADD = “H2aoooaod
BICSROFF = “Xi4
OFF = “KOF2
BDAIFADD
NEXT_NODE = "Xo@aazoa
ADAPTER_WINDOW = “K2o400000
NEXT _WINDOW = “K4pood
|
START_ADD_OFF = “H2a
END_ADD_OFF = “K24
MAP_REG_OFF = “Kaoo

BIDEVCODE_BUA = ‘K12

BUA Definitions
and offsets

=
=
=
=
=

P_BUFF
P_SHUN
P_OPCD
P_BCNT
P STS

J-10 Sample Bootstrap Code

BDA node

;

Load R11 with device type code for BDA.

i
;
i

Load R2 with address of IP reg.
Load R with R2 + 2 (BDA has separate Sfi registers for write
and read).

Make address of communications area in Init table physical C(RINGAD).

Load ADD_TYPE_FLAG with 1 to indicate BDA/Physical addressing.

;

Non BDA node

i
j
i

Load R11 with device type code for BUAZBRLA.
Load R2 with physical address of cUntrullers CSR (IF reg).
Load R@ with R2.
.

;

Sets up the VAXBRI node by loading the start and end addresses of

i
;

the adapter window into the BIIC of the BUA. Sets up the
INIBUS map registers and sets up R2 with CSR (IP) address.

INPUTS

;
;

k1
k3

OUTPUTS:

;
;

k1
k2

;

;
i

K3
ki@

- VAXRBI node number for this
BUA
= Unit number of boot device in binary
Saftware boot cnntrul flags

;

- (base_address + "X2@0) of 64kb aof good memary

- VAKRI node number for this BUA
- Physical address of the boot devicels CSK

= Unit number of boot device in binary
- Software boot control flags
- Base address of the VAKRI node

SP.

- {base_address + "®20@) of 64kb of good memory

i Work Registers:
;

k4 and RS

:**************************************************************************
LONG

"H7A1E394D

i CHKSUM - FOR FILE HANDLING

; PURPFOSES ONLY

,**************************************************************************

BOOT CODE HEADER

STARTDUROOT:
BRE

WORD
.WORD
JASCII
R

;

STARTDU
ENDDUROOT - STfiRTDHBHHT,
101
i

AUDs

Branch to start of code.
Size of file in bytes
Version number

i Device designaticn reversed
Y

R R

R E R R

R RN

Location to change if you have a second controller on the UNIBUS

"¥1468 far 1st controller “¥O@DC for second controller

Ry R

UDAIFADD:

.LONG

*H1468

RS R

R R R

; UDA IF address

AZTEC_BOOT:
RAGR_BOOT:
STARTDU:

ADDL

#°%100,5F

SUBL3

#°X30@,SP,RT

MOVZBL

#BUA_BLA_DTYFPE.R11

i Move stack off of page HB for now

to make room for boot block.

Set device code for BUA,

i Pointer to start of good 64Kk=:=)RT
BLA.

Sample Bootstrap Code

J-11

R1B{=base add of VARBRI node,

R1,#NEXT NODE,R10
#BI_ADD,R10

ADDL3

#START_ADD_OFF,R1@,R8

CMPW

A,
(K141
HBIDEVCODE_RD

BNEQU

100%

L_X1
LY

L X

L X3

MULL3

ADDLZ

LX)

Setup pointers:
field.

LX)

i
i

Node

R8{=zadd of start add

Calculate VARBI node address.
Get starting add of VARBI
node in R18.
Get add of starting add
field in RB .
Is this VARBI node a BDA?
Br if no - assume BUA or BLA.

is verified to be a BDA

Load R11 with device type code for BDA.
Load R2 with IP address.

HBDA_DTYPE,R11

MOVAL

EDAIFPADD OFF(R1@),R2

MOVZRL

Load R with K2 + 2.
Make add of communications area in the init table physical (RINGAD).
Load ADD _TYPE_FLAG with 1 to indicate physical addressingsBDA.

2,R2,R0

BRE

CONT

R7,
W RINGAD
#1,H"ADD_TYPE_FLAG

ADDLZ

Loy

MOVE

ADDL3

LX)

Load R11 with device code for BDA.
Load R2 with phys address of
IF reg.
Load R@ with IF add+2 (Far
BDA writes.
Make add in init table physical.
Indicate address type is physical.
Branch to continue.

i Node is assumed
to be BUA
or BLA
}

i
i

Setup starting and end address of adapter window in BIIC.
Load R2 with physical address of the controllers CSKR IF add.

108%:

MULL3
ADDL3
ADDL3

HNEXT_WINDOMW, R1.R2
i
HADAFTER_WINDOMW,
R2, (RB) ;

# 0760004, (RB),R2

Calculate adapter window.
Load starting add in RBRIIC.
kK2{=addres of base of UNIBUS

; 10 page.

ADDLZ

UDAIFADD,
R2

MOVL

R2,R@

;
;

i
i

HNEXT _WINDOW,
CRED+, CRE) ;

Setup the UNIBUS map registers - Map registers @ thru xxx are napped
sequentially starting at start of 64K of good memory.
Mapping is such that address B is start of good 64k.
The VALID bit is set and the non buffered data path selected.
(At this point - R8 points to the end address field)

BISLZ2

#MAP_REG_OFF-END_ADD_OFF, R8 ;i Fointer to Map
registers==)RH
Starting add of good 64k =)
R7., CRB)
1st map reg
Fosition physical add 29:9
#-9, (R8), (RE)
into 28:4.
|
Set Valid bit in 1st map

MOVZWL

H400-1,R4

ADDL3
SOBRGTR

#1,CRBY+, (RED

R4,1000%

See

L X}

L X

ADDL3

R2{==FPhysical add of
controllers CSK
RB{==CS5R add (for BDA
compatiblty)
Load end add in BIIC.

s
s

#UALID,{RE}

1022%:

.FAGE
SBTTL

J-12

ROM Control Subroutine

Sample Bootstrap Code

%es

Twme

ASHL

Nes

MOVL

fNes

ADDLZ

table entry.

Map table entry count ==) R®.
Load map table entry.
Br back if more to load.

LY
LT}
LT
b 1]

FUNCTIONAL DESCRIFTION:

The subroutine reads block @ off the boot device's volume,

INPUTS:

loads it into the first page of usable memory (the page
mapped by LUNIBUS map register H@) and transfers control to
the fourth longword (byte #12) of this boot block.

kK2 - Adiusted IF address
= RZ for BLA and BUA

- Unit number of the boot device

IMPLICIT

INPUTS:

R2+2 for BDA (accommodates different add for writes)
- VARBI node number for this BUA

=
k1

Software boot control flags

- (base_address + "X20@) of 64kb of good memary

LX)

Physical address of the boot devices CSR

L X1

LEN of boot block is @,
|
,
Boot block is to be read into (SP)-"X20@ (i.e. relative 0).
OUTFUTS:

Transfer address of boot block code is at BOOT_CODE_START(SP).

- Adjusted IF address
= R2 for BLA and BUA
|
= kK2 + 2 for BDA Caccommodates different add for writes)
k1
- VAXBI node number for this BUA

L X1

- Fhysical address of the boot device's CSR

R3
RS
k6

- Unit number of the boot device
- Software boot control flags
- Address of the device-specific read block routine

- {(base_address + "¥20@) of 64kb of good memory

routine preserves

registers K3,

K5,

R18-R11,

AP,

and SP.

L X1

This

CONT:

PUSHR

; Save register for tenp.

INITIALIZE THE CONTROLLER AND TELL IT TO GO

B2, R6

SOBGERQ

R6,RETRY

(R2)

#5ST,RICSROFF(R1®)

Start

CBUAABLAY.

init by writing IF reg

Br to continue.
Start

init by setting $5T

bit in BICSR.
Step 1 compare data ==}

MOVL

#S1,RS

MOVABR

B TABLE1.RS

Painter to

MOVH

SACR2),RY

Kead status address

BLSS
BRC
MOVH
ADBLER

IERROR
RS, k%, ILOOP
(RE8)+,SACRD)
#54,R5,IL0OP

L X
oo
LYY

ILOOP:

Sa@$:

L X1

Y"1 § 3

BISH

Br if this is a BDA.

BRE

LX)

fiDD;T?PE_FLfiG;lm@$

LYY

CLEW

10@$:

BLBS

Halt after tuo tries.

RETRY:

retries

HALT

Number of

TERROKR:

MOVL

;

# M(RS)

K3.

init data table==}RB

reg.

Br if error to retry.
Wait for proper step bit to set.
Write next command to UDASA.
Repeat until finished.

Sample Bootstrap Code ’VJ—13

‘—q-q--—---—--—u--—-a-—--——-----————---‘ -----------------------------

i Do set-up and call primitive driver to load LBN 8 - pass CUntrnl to
boot block

'----———-h-—--;-----‘---—-----—-p-----—--——--——-. ----------------------

; Set up output registers and call a device-specific subroutine that

;

reads in one block off the boot deu1ce The block is block @,

boot block.

the

i Set up registers as follows:

R? - boot device's CSR address
k3 - device unit number
RS - Relative address
k% - LBN @

;

RS
R&
R7

BSBB
BLES

BOOSUDASA_QIN
Ra,12¢

Fut relative load address in KS.
Set LBN to 28 ==) RB.
Fut physical load address on
stack.

Call driver to read in LBN 8.
Eranch on successful read..
Error, halt processor.

Set up the remaining registers needed by VMB and by the buot block.
Then transfer control to the boot block code.

L X

L_T1

L X

~»a o

CLRL
CLRL
FUSHL

10%:

ADDL2
-

#4,SF

MOVAR

B BOOSUDASR_QIO,R6

FOFR
SUBL

# M{R5)
#"%100,5P

MOVL

JMP

K11,Ra@

BOOT_CODE_STARTC(SE)

; Read was successful.
i Remove ph951ca1 load add from
i stack.

i Store address of driver.
i

Load device type.

; Restore register.
i Restore original stack position.
i Give control to boot block.

.FPAGE

.SBTTL UDA TABLES - tables used for UDA initialization

The address of the ring base as given below is relatlue If the
device does not MAP to the start of good 64k (such as the BDA),
then this address will be nuerwrztten with the physical address as

WORD

STEP

RINGAD:

.WORD

“MFAR4

L X3

.WORD

(2¥¥Q), vector
Step 2 - lo address of ring base

Step 3 - high address of

Step 1 - desc lengths = 1

ring base

.WORD

ABLE1:

part of the set-up.

Step 4 - go bit to enable DA

Bfiut code 1nterna1 storage area

;

_FLfiG field indicating type of address and BDA/non BDA

ADD_TYPE_FLAG: .BYTE @

J—14 Sample Bootstrap Code

i 1=PHYSICAL-BDA-B=RELATIVE

.PAGE
JSBTTL

BOOSUDASR_QIN - primitive device-dependent readswrite driver

FUNCTIONAL DESCRIFTION:
INFUTS:

Smes

%ee

-----------------------------------------------------------------------

%es

%ee

k3
RS
k&

unit number of boot device
starting address of transfer (relative to load address)
LBN to transfer from boot device
physical address of transfer

IMPLICIT INPUTS:

%as

4(5F)

- physical address of boot device's CSR C(IP register)

Swms

RINGAD is loaded with either physical or relative address
of

%es

VAX Diagnostic Supervisor.

OUTRUT :

Mme

(up to 399 are set up to handle direct booting of the

%ee

Swe

Mma

%ee

ring base ADD_TYPE_FLAG is set up to indicate physical or
relative addressing for BUA and BLA. The UNIBUS adapter map
registers are already set up. The 64k of good memory are
mapped to map registers @8-127. Additional map registers

- 55%_NORMAL on successful

%ws

Mes

Sms

R7-R9

read

low bit clear on error during read
scratch registers

routine preserves registers R1-R6,

R12-R11,

AP,

and SP.

m e

%es

Nes

This

O0$UDASA_QIO:

SUBL3

R5,4(5P),R7

Get phys add of communications

ADDLZ

RINGAD.,RY

; ?;fizé add - rel add + ringadd)

; Issue ONLINE command

'1mm$= éSBB
- MOVH
TSTH
HDONEB:TSTL

SETUP_ID |

i Subroutine sets up parts of
i

packet common to ONLINE

and READ commands.

NOTE:

polling.

i
i

Wait until UDA says that we
are finished C(ownership bit==)@).
Br on error to QIO_RETURN.

SETUP_IO returns R2
= @.

#OP_ONL.B ECND+F _ORCDCRTY: Set ONLINE apcode into packet.
(R2D
i Tickle UDA, cause it to initiate
(R7)

BLSS

XDONED

B RMSG+P_STS(RT)

i Check status in response packet.

ENEQ

GI0_RETURN

TSTER
i

Set up the command packet to read a single logical block.

FaaaN

Sample Bootstrap Code

J-15

BSRBEB

SETUP_IO

Subroutine sets up paris of

packet common to ONLINE

i
i

and READ commands.
NOTE: SETUP_IO returns RO =

Br if physical addressing
Duerlay physical add with

MOVH
MOVL
MOVL

#OF_RD,B RCMD+P_OFCDC(R7); Load “"READ" apcode into packet.
RS;B“RCMD+P_LBN{R7)
Load LBN in packet.
4C5F),B"RCHD+F_BUFF(R7);
Load physical address of data

BRLBS

ADD_TYPE_FLAG, 100%

NOVL

$2,B"RCMD+P_BCNT+1(R7)

; Byte count is 512 (2%¥256).

TSTH

(R2)

buffer.

MOVL

l1a@s:

R5,B*RCMD+F_BUFF(RT7)

XDONE1:TSTL
BLSS

TSTE

Access IF reg to cause
controller to initiate polling.
Wait until

INCL

UDA says that we

are finished.

B RMSG+F_STSCRT)

QIO_RETURN

Check status.
Keturn error.

i Keturn successful transfer.

QIO _RETURN:
KSR

;

relative.

(R7)
XDONE1

BNEQ

(BDA).

i
i

Return to caller.
Return.

SUBROUTINE TO PERFORM COMMON PACKET SET-UP

Set up part of command packet common to ONLINE and READ commands.
Fill in ring pointers for command response.
Implicit Inputs:
|
RINGAD nmust be adiusted with either the physical or relative

address of the communications area.
ETUP _I0:

MOVL

CLOOP:

K7.,R3

Set up to zero communications

area.

MOVL

#COMM_END-/2.R@

i Ditto.

CLRY
SOBRGTR

(R34
Ra, CLOOP

Clear packet storage area.

MOV
MOV
MOVK

#(RCMD-RMSG_;B*RMSG+P_LEN£E7}; Load length into response.
#36,B"RCMD+F_LENCR?Y
; Write length of command.
R3,B"RCHD+F _UNITCR7?
i Load unit number.

NOTE:

ADDL3

;
i
i

Load resp descriptor with add of
response packet and owned
by port.

HOWN!RCMD, RINGAD,B"4C(R7) ; Load command descriptor
;7

with add of command packet

and owned by port.

i
i

Delimit end of code.
Remove for file inclusion.

ADDL3

HOWN!RMSG,RINGAD,(R7)

this leaves R = B.

KSR

ENDDURONOT .END
STARTDU

J-16

Sample Bootstrap Code

Appendix K

Unexpected Error Conditions

K.1

ID Parity Error Interrupts Following Retry Timeout
A retry timeout error condition occurs if the KA820 module fails to access a

VAXBI node after 4096 retries, as specified by the VAXBI design. For example, if a memory node is locked, and the KA820 module tries to perform an
IRCI (interlock read with cache intent) to an address on that node, the KA820
module will retry the transaction up to 4096 times, incrementing the retry
timer with each try. If a write unlock transaction does not unlock the memory

~ before the retry timer expires, a timeout will occur. In response to this condition, KA820 microcode initiates a machine check and pushes a status word
with the event code 1D (hex) on the stack.

Software can evaluate the condition and take appropriate action.
However, as a side effect of the retry timeout, the IPE (ID Parity Error) bit
may be set in the Bus Error Register (BER) of each node on the VAXBI bus.

Each node that has the HEIE (Hard Error Interrupt Enable) bit set in the
BICSR will then interrupt the processor.

Exception condition handling software should be written with this consideration in mind.
|
|
|
|

K.2

Clearing the Bus Error Register
Error bits in the Bus Error Register (BER) on any node in a VAX 8200 computer system may be set or cleared following power-up. Software should write

3FFF 0007 (hex) to each BER in the system to clear these bits.

K.3

Interrupts Following Initialization

The BR (7:4) interrupt flags in the port controller may be set or cleared
following processor initialization. Software should deal with this situation by
setting up the system control block (SCB) before lowering the IPL below 17

(hex).

Glossary

This glossary defines terms used to descrlbe the VAXBI bus, the BIIC andthe
KA820 module
ACK data cycle

A data cycle of a read-type or write-type transactlon during which the
slave asserts the ACK CNF code to acknowledge that no error has
been detected and that the cycle is not to be stalled.
ACLOL

A signallthat indicates the condition of ac power to the computer sys-

tem. When AC LO L is false, dc power will remain steady for at least
4.2 milliseconds.
Adapter

A node that interfaces other buses, communication lines, or peripheral devices to the VAXBI bus.

Arbitration cycle

A cycle during Whlch nodes arbitrate for control of the VAXBI bus.
Assert

To cause a signal to take the “true” or asserted state.
Asserted

To be in the “true” state.
Assertion

The transition of a signal from the “false” state to the “true” state.

Atomic

Pertaining to an indivisible operation.

|
|
Attached processor
A second or third processor in a multiprOCessor system. Attached proc-

essors do not have direct access to the control panel, the console terminal, serial-line units, the RCX50 controller, or the watch chip.

Backup translation buffer (BTB)
A small memory on the KA820 module that stores translations (page
‘table entries) for 512 recently used virtual address pages. The backup
translation buffer backs up the mini-translation buffer (MTB).

Glossary-1

Bandwidth

The data transfer rate measured in information units transferred per
~unit of time (for example, megabytes per second). All bandwidth figures quoted in this manual take into account command/address and
embedded ARB cycle overhead.

BCI

BI chip interface; a Synchronous interface bus that provides for all
communication between the BIIC and the user interface.

BIIC
Bus interconnect interface chip; a chip that serves as a general purpose interface to the VAXBI bus.

BIIC CSR space

The first 256 bytes of the 8K-byte nodespace, which is allocated to the
BIIC’s internal registers. See also Nodespace.
BlIC-generated request

A transaction request generated by the BIIC rather than by the user
interface. The BIIC can request only error interrupts.

BlIC-generated transaction

A transaction performed solely by the BIIC with no assistance from
the master port interface. Only INTR and IPINTR transactions can be

independently generated by the BIIC. The user interface initiates
BIIC-generated transactions by using the IPINTR/STOP force bit, the

user interface or error interrupt force bits, or by asserting one of the
BCI INT(7:4) L lines. A BIIC-generated transaction can also result
from a BIIC-generated request, which results from a bus error that

sets a bitin the Bus Error Register.
Boot RAM

An 8K-byte memory on the KA820 module used as temporary stoi'age

for boot macrocode.
BTB

See Backup translation buffer.
Bus access latency

The delay from the time a node desires to perform a transaction on the
VAXBI bus until it becomes master.
Bus adapter

A node that interfaces the VAXBI bus to another bus.
Busy extension cycle
A bus cycle during which a VAXBI node, not necessarily the master or
the slave of a transaction, asserts the Bl BSY L line to delay the start

of the next transaction.

Glossary-2

Cache

A small, high-speed memory on the KA820 module that contains copies of recently accessed physical memory locations.
Cold start

Boot to bring a fresh copy of the operating system into memory.

Command/Address cycle
The first cycle of a VAXBI transaction. The information transmitted

in this cycle is used to determine slave selection. In some cases the

data on the BI D(31:0) L lines is not an actual address, but it serves
the same purpose: to select the desired slave node(s). For example, during an INTR command a destination mask is used.

Command confirmation

The response sent by the slave(s) to the bus master to confirm participation in the transaction.
Command confirmation cycle

The third cycle of a VAXBI transaction during which slave(s) confirm
participation in the transaction.
Conflguratlon data

Data loaded into the BIIC on power-up that includes the device type
and revision code, the parity mode, and the node ID.
Console

The manual control system integrated into the KA820 module in microcode. It lets you start and stop the processor and run diagnostics
using a terminal.
Console mode

A condition of the CPU in which the computer is halted and responds
only to machine control commands typed on the terminal connected to
serial-line unit 0.
Control store

A set of five ROM/RAM chips containing KA820 microcode.
Corrected read data (CRD)

Data sent on the VAXBI bus in response to a read transaction in which
the slave device has detected and corrected a data error. The slave device sends a corrected read data (CRD) code on the VAXBI bus when it
sends the data.
CRD

See Corrected read data.
Cycle

The basic bus cycle of 200 nanoseconds (nominal), which is the time it

takes to transfer the smallest piece of information on the VAXBI bus.
A cycle begins at the leading edge of T0/50 and contlnues until the
leading edge of the next T0/50.

GIossary—-3

Data cycle

A cycle in which the VAXBI data path is dedicated to transferring data
(such as read or write data, as opposed to command/address or arbitration information) between the master and slave(s). During read
STALL data cycles, the BID(31:0) L and I{3:0) L lines contain undefined data. See also ACK data cycle, Read data cycle, STALL data cy-

cle, Vector data cycle, and Write data cycle.

Data transfer transactions
VAXBI transactions that involve the transfer of data as well as
command/address information: read-type, ‘write-type, IDENT, and

BDCST transactions.
DCLOL

A signal that indicates the condition of dc power to the VAXBI backplane. When DC LO L is false, power to the backplane is steady:.
Deassert

To cause a signal to be in the “false” or deasserted state.
Deasserted
|
To be in the “false’ state.

Deassertion

- The transition of a signal from the “true” state to the “false” state.
Decoded ID
The node ID expressed as a single bitin a 16-bit field.
Device type

A 16-bit code that identifies the node type Thls codeis containedin

the BIIC’s Device Register.
~ Direct memory access (DMA) adapter

An adapt.er that directly performs block transfers of data to a_hd from
memory.

EEPROM

A 16K-byte electrically erasable programmable read-only memory
used on the KA820 module to store customer choices for KA820 op-

tions, VAX bootstrap macrocode, and microcode patches.

Embedded arbitration cycle

An arbitration cycle that occurs (is embedded) in a VAXBI transaction.

Encoded
ID

The node ID expressed as a 4-bit binary number. The encoded ID is
used for the master’s ID transmitted during an embedded ARB cycle.

Glossary-4

Even parity

The parity line is asserted if the number of asserted lines in the data
field is an odd number.
|
Event flag

A status posting bit maintained by an operating system or the VAX
Diagnostic Supervisor, used to pass signals between the operator and
software or between programs.
Expansion module

A VAXBI module that does not attach directly to the VAXBI bus. A
VAXBI node that requires more than one module has one module that
attaches directly to the VAXBI (that is, contains a BIIC) and one or

more expansion modules that communicate with the first module over
the user-defined I/O section.
Extension cycle

A bus cycle during which a VAXBI transactionis made longer. See
STALL data cycle, Busy extensmn cycle, and Loopback extension
cycle.
F chip

One of three chips in the KA820 processor chip set: floating point accelerator.
H

Designates a high-voltage logic level (that is, the logic level closest to
Vee). Contrast with L.
IDENT arbitration cycle
The fourth cycle of an IDENT transaction during which nodes arbitrate to determine whichis to send the vector.
I/E chip

One of three chips in the KA820 processor chip set, implementing the
instruction buffer, microsequencer, instruction execution unit, and

MTB.
lllegal confirmation code

A CNF code thatis not permlttedina partlcular VAXBI cycle (such as
a RETRY command conflrmatlon toa mu1t1 responder command).
Interlock commands

The two commands, IRCI (Interlock Read with Cache Intent) and
UWMCI (Unlock Write Mask with Cache Intent), that are used toim-

plement atomic read-modify-write operations.
Internode transfer

A VAXBI transaction in which the master and slave(s) are in different
VAXBI nodes. Contrast with Intranode transfer.
|
Interrupt port

Those BCI signals that are usedin generating INTR transactions.

Glossary-5

Interrupt port interface

That portion of user logic used to interface to the interrupt port of the

BIIC.

Infiterrupt sublevel priority
Interrupt priority information used during an IDENT transaction to

determine which node with a pending interrupt is to provide the vector. The interrupt sublevel priority corresponds to the node ID.
Interrupt vector

In VAX/VMS systems, an unsigned binary number used as an offset
into the system control block. The system control block entry pointed
to by the VAXBI interrupt vector contains the starting address of an

interrupt handling routine. (The system control block is defined in the
VAX Architecture Handbook.)

Intranode transfer

A transaction in which the master and slave are in the same node.
Loopback transactions are intranode transfers. Contrast with Internode transfer.
Invalidate

To mark an entry in the cache, MTB, or BTB to show that it no longer
contains current informatio‘n.
L

Designates a low-voltage logic level (that is, the logic level closest to
ground). Contrast with H.
Latency

Read access time; see Bus access latency.
Local memory

VAXBI memory that can be accessed without using VAXBI transac-

tions; for example, VAXBI-accessible memory on a single board computer.

Logical console

A CPU that performs console functions for another CPU.

Loopback extension cycle

A cycle of a loopback transaction during which a node asserts both Bl
BSY L and BI NO ARB L to delay the start of the next transaction.
Loopback request

A request from the master port interface asserted on the BCIRQ(1:0)
L lines which permits intranode transfers to be performed without using the VAXBI bus.

Loopback transaction
A transaction in which information is transferred within a given node
without use of the VAXBI data path. Contrast with VAXBI transaction.

Glossary—6

Macrocode

Instructions written in MACRO-32 or a higher level programming
language.
Mapped adapter

A DMA adapter that performs data transfers between a system with a
contiguous memory space and VAXBI address space (in which mem-

ory need not be contiguous). The mapping is done by using a set of map

registers located in the adapter.
Master

- The node that gains control of the VAXBI bus and initiates a VAXBI or

loopback transaction. See also Pending master.
Master port

Those BCI signals used to generate VAXBI or loopback transactions.
Master port interface

That portion of user logic that interfaces to the master port of the

BIIC.

Master port request

A request (either VAXBI or loopback) generated by the master port
interface through the use of the BCI RQ(1:0) L lines.
Master port transaction
|

Any transaction initiated as a result of a master port request.

M chip

One of three chips in the KA820 processor chip set, used for BTB and
cache tag storage, internal processor registers, interrupt handling,
memory management, clock generation, serial-line units, and inter-

face to the port controller.
Microcode

Instructions contained in control store that carry out the functions of
the VAX instruction set, console functions, and self-test.
Mini-translation buffer (MTB)

A translation buffer that stores translations (page table entries) for

five recently used virtual address pages.
Module

A single VAXBI card that attaches to a single VAXBI connector.
MTB

See Mini-translation buffer.
Multi-responder commands

VAXBI commands that allow for more than one responder. These 1n

clude the INTR, IPINTR, STOP, INVAL, and BDCST commands.

Glossary-7

Node

A VAXBI interface that occupies one of sixteen logical locations on a
VAXBI bus. A VAXBI node consists of one or more VAXBI modules.
Node ID

A number that identifies a VAXBI node. The source of the node ID is

an ID plug attached to the backplane.

Node reset

A sequence that causes an individual node to be initialized; initiated
by the setting of the Node Reset bit in the VAXBI Control and Status

An 8K-byte block of I/O addresses that is allocated to each node. Each
node has a unique nodespace based on 1ts node ID.

Nuil cycle
A cycle in which all VAXBI lines are deasserted (that is, no transaction or arbitration is taking place).

Odd parity
The parity lineis asserted if the number of asserted linesin the data
fieldis an even number.
Parity mode

Specifies whether parity is generated by the BIIC or by the user interface.
Pending master

‘A node that has won an arbltratlon but Wthh has not yet begun a
transaction.
Pending request

A r’equest of any type, whether from the master port or a BIICgenerated request, that has not yet resulted in a transaction.
Physical address

A 30-bit integer identifying a byte locatlonin physmal memory or a

Serial-line unit 0 and the related microcode funct1ons avallable on the
primary processor.

Pipeline request

A request from the master port that is asserted prior to the deassertion of BCI RAK L for the present master port transaction; that is, a
new requestis posted prior to the completion of the prev1ous transactlon

Glossary-8

Port controller
TN

An interface that connects the processor section of the KA820 module

with the VAXBI interface and the PCI bus devices (EEPROM, boot

RAM, watch chip, and RCX50 controller).

Power-down/Power-up sequence

The sequencing of the BI AC LO L and BI DC LO L lines upon the loss
and restoration of power to a VAXBI system. See also System reset.
Primary processor

The processor installedin VAXBI slot K1J1. Th1s processor 1s connected to the control panel, RCX50 controller watch chip, serial-line
units 0-3.
Private memory

Memory that cannot be accessed from the VAXBI bus

Program I/O mode
The normal condition of the CPU in which the computer executes
software. Characters typed on the console terminal are passed
through to the operating system. The console terminal acts like a

standard terminal on one of the other serial-line units.
Programmed I/O (P1O) adapter
An adapter that does not access memory on the VAXBI bus but inter-

acts only with a host processor.

RCLK (receive clock)
The clock phase during which information is received from the VAXBI
bus; equivalent to T100/150.

RDS
See Read data substitute.
Read data cycle

A data cycle in which data is transmitted»from a slave to a master.
Read data substitute (RDS)

Faulty, uncorrectable data sent on the VAXBI bus in reSponse to a
read-type transaction. The slave device sends the read data substitute
(RDS) code on the VAXBI bus when it sends the bad data.
Read-type commands
Any of the various VAXBI read commands, including READ, RCI

(Read with Cache Intent), and IRCI (Interlock Read with Cache Intent).
RESERVED code
A code reserved for use by DIGITAL.

Glossary-9

RESERVED field

A field reserved for use by DIGITAL. The node driving the bus must
ensure that all VAXBI lines in the RESERVED field are deasserted.
Nodes receiving VAXBI data must ignore RESERVED field information. This requirement provides for adding functions to future VAXBI
node designs without affecting compatibility with present designs.
Example: The BI D¢31:0) L and BI I{3:0) L lines during the third
cycle of an INTR transaction are RESERVED fields.
Reset module

In a VAXBI system, the logic that monitors the BI RESET L line and
any battery backup voltages and that initiates the system reset sequence.

Resetting node

The node that asserts the BI RESET L line.
Retry state

A state that the BIIC enters upon receipt of a RETRY confirmation
code from a slave. If the master reasserts the transaction request, the
BIIC resends the transaction without having the user interface provide the transaction information again. The command/address information and the first data longword, if a write transaction, are stored
in buffers in the BIIC.

Self-test

A microcoded test that identifies hardware faults on a VAXBI module.
Single-responder commands

VAXBI commands that allow for only one responder. These include
read-type and write-type commands and the IDENT command. Although multiple nodes can be selected by an IDENT, only one returns
a vector.

Slave

A node that responds to a transaction initiated by a node that has
gained control of the VAXBI bus (the master).
Slave port

Those BCI signals used to respond to VAXBI and loopback transactions.

Slave port interface

That portion of user logic that interfaces to the slave port of the BIIC.
STALL data cycle

A data cycle of a read-type or write-type transaction during which the
slave asserts the STALL CNF code to delay the transmission of the
next data word.

Glossary-10

| System reset
An emulation of the power-down/power-up sequence that causes all
nodes to initialize themselves; initiated by the assertion of the BI RE-

SET L line.
Target bus

The bus that a VAXBI node interfaces to the VAXBI bus.
TCLK (transmit clock)

The clock phase during which information is transmitted on the
VAXBI bus; equivalent to T0/50.
Transaction
The execution of a VAXBI command. The term ‘““transaction’ includes

both VAXBI and loopback transactions.

UNDEFINED field
A field that must be ignored by the receiving node(s). There are no
restrictions on the data pattern for the node driving the VAXBI bus.
Example: The BI D(31:0) L. and BI I{3:0) L lines during read STALL

data cycles and vector STALL data cycles are UNDEFINED fields.
User interface
All node logic exclusive of the BIIC.
User interface CSR space

That portion of each nodespace allocated for user interface registérs.
The user interface CSR space is the 8K-byte nodespace minus the low-

est 256 bytes, which comprise the BIIC CSR space.
User interface request

A transaction request from the user interface, which can take the
form of a master port request, an assertion of a BCIINT(7:4) L line, or
~

the setting of a force bit.

VAXBI primary interface

The portion of a node that provides the electrical connection to the
VAXBI signal lines and implements the VAXBI protocol; for example,
the BIIC.
-

VAXBI request

A request for a VAXBI transaction from the master port interface that
is asserted on the BCI RQ(1: O) L lines.
VAXBI system

All VAXBI cages, VAXBI modulés, reset mddules, and power supplies
that are required to operate a VAXBI bus.

A VAXBI system can be a

subsystem of a larger computer system.
VAXBI transaction

A transaction in which information is transmitted on the VAXBI sig-

nal lines. Contrast with Loopback transaction.

Glossary-11

VAX interrupt priority level (IPL)
In VAX/VMS systems, a number between 0 and 31 that indicates the
priority level of an interrupt with 31 being the highest priority. When
a processor is executing at a particular level, it accepts only interrupts
at a higher level, and on acceptance starts executing at that higher
level.

'VAX port adapter
In a VAXBI system, an adapter that conforms to the VAX port architecture, uses interlock transactions to acecess command and response
queues in VAXBI memory, and performs virtual-to-physical memory
translation by using page tables located in memory on the VAXBI bus.
Vector

An address pointing to a routine that services interrupts or excep-

tions. The system control block is a table of vectors.
Vector data cycle

A data cyclein ‘which an interrupt vector is transmitted from a slave
to a master.

Virtual address

A 32-bit integer identifying a byte location mapped by memory management.

Warm start

Restarting the software at the point where processmg stoppedin a
power failure.
Window adapter

A bus adapter that maps addresses that fall within one contlguous region (a “window”) of a bus’s address space into addresses in a window

(possibly in a different region) in another bus’s address space.
Window space

A 256-Kbyte block of I/0 addresses allocated to each node based on
- node ID and used by bus adapters to map VAXBI transactions to other
buses.

Write data cycle
A data cycle in which data is transmitted from a master to a slave.
Write-type command

Any of the various VAXBI Write commands, including WRITE, WCI
(Write with Cache Intent), WMCI (Write Mask with Cache Intent),

and UWMCI (Unlock Write Mask with Cache Intent).

Glossary-12

Index

“abort

basic instruction exerciser, 7-10 to 7-11

exception, 5-1

battery backup, 3—1

abort command line

baud rate, 2-9

console command, 4-18

console, 4-6

AC LO

BCI Control Register, D-10 to D-1

signal, 3—2

contents, G-1

timeout, 4-18

Accelerator CSR (ACCS), F-16

ACCS

(Accelerator CSR), F-16
Register

contents, G-1

BER (Bus Error Register), 2-14, D-5 to D-8

BI RESET, E-2
BI STF, E-3

BI STF L, 3-7

ACK confirmation code, 2—-17

“address space qualifiers
for console command, 4-10
address translation, 2-5
AP (Argument Pointer), 4-3
ARB (arbitration control) bits, D—4

arbitration control (ARB) bits, D—4

Argument Pointer, 4-3
ASCII console, 4-1

.
ASTLVL (Asynchronous System Trap Level),
F-7

asymmetrical multiprocessor system, 1-1

Asynchronous System Trap Level (ASTLVL),
F-7

BDCST transaction, 2—18

attached processor, 1-1, 3—4, 3-21, 4-15
starting, 3-22

attaching the KA820, 7-7
auto start, 3—1

Auto Start/Halt power-up option, E-1
automatic load device, 4-1, 4-15

BIIC

internal register address, 2—14
registers, 2-14, D-1 to D-14

test, 3—7

transaction bus timeout error, 5-10

VAXBI interface chip, 2-10
binary load and unload

console command, 4-15
BINID (VAXBI Node Identification Register),

F-26

BISTOP (VAXBI STOP Register), F—26

block diagram
CPU section, 2-2
KAS820, 1-2
port controller and PCI devices, 2—20

VAXBI interface, 2—-12

boot, 3—-1, 3-14, 3-15 to 3—16

block, 3-16
code sample, J-1
cold start, 3—1

console command, 4-7
“control flags, I-1

B console command, 4-7

backup translation buffer, 2-5
bad parity, E-5
received, 5-10

device, 3—-17
default, 3—-17

first, 4-12
second, 412

Index-1

specification, 4-8
dispatcher, J—2
failure, 4-18
parameter, 4—8

CACHEX (Cache Invalidate Register), F-25
|
CADR
(Cache Disable Register), F-14
Register

software date and time responsibilities,
6-16

software responsibilities, 3—17
boot RAM, 3-16, 6-11
test, 3—7

contents, G-1
CAL bus, 2-3, 2-6, 2-8

CAM (contents addressable memory), 2—11
change console baud rate command, 4-6
CHM

from interrupt stack

booting

halt code, 4-3

EVKAA, 7-4

to interrupt stack

VDS stand-alone, 7-5

halt code, 4-3

bootstrap

see boot

bootstrap-in-progress flag, 3-14, 3-15
clearing, 3—17

cluster exerciser, 7—2
CMISS, 2-10

CNSL ENB, E-2

BPM, 5-10

CNSL INTR, E-8

BREAK command, 4-6
broadcast transaction, 2—18
Broke bit, 3-6, 3—11, D4

cold start, 3-1, 3—-14, 3—-15 to 3—16
command/address cycle, 2—15
comment (!)

console command, 4-17

BTB, 2-5

addressing, 2—6
array test, 3—7

confirmation code, 2—17
connector

loopback, 7-12

data parity error, 5-5
data parity error flag, 5-9
fill cycle, 27

connectors C1 and C2, A-2

wrap, 7—12

miss, 2—6

connectors D1 and D2, A-3

tag addressing, 26
tag invalidate, 27

connectors E1 and E2, A-3

tag parity error, 5-5
tag parity error flag, 5-9

console

CONS LOG, E-1
baud rate, 46
default, 4-12

tags, 2—6

dialog

BTO error, 5-10
bus

timeout, E-5
Bus Error Register, 2-14, D-5 to D-8
|
contents, G—1

sample, 4-12
entry, 4-2 to 44

error code, 4-18
functions, 4-1

halt

C console command, 4-9
cables, A—4
cache, 2-7
addressing, 2—7
array test, 3—7
data parity error, 5-5
data parity error flag, 5-9

halt code, 4-3
output

sample, 44
self-test, 4-14

secure/enabled selection, E-2
terminal, 4-1
console command, 44 to 4-18

fill cycle, 2—8

,4-17

invalidate, 2-9
miss, 2—8

address space qualifier, 4-10
B, 4-7

tag, 2—7

binary load and unload, 4-15

tag addressing, 2—7
tag parity error, 5—5
tag parity error flag, 5-9
Cache Disable Register (CADR), F-14

Cache Invalidate Register (CACHEX), F-25

Index—2

boot, 4-7

C, 4-9
comment, 4-17
continue, 4-9

CTRL/P, 4-17

CTRL/Q, 4-17

console command, 4-18

CTRL/S, 4-17
D, 4-9

Current Processor Status Longword

data size qualifier, 4-10
deposit, 4-9

Current Program Counter

E, 4-9

customer options, 1-4

at failure, 5-11
at failure, 5-11

E/M, 5-12
examine, 4-9

D console command, 4-9

forward, 4-15

DAL bus, 2-3, 2-7
interface

forward next character, 4-17
guidelines, 4-5

test, 3—7

H, 4-13

data cycle, 2-15

halt, 4-13

data size qualifier
for console command, 4-10

I, 4-13

initialize, 4—13

Day-of-the-Month Register, 6—-12

N, 4-13

DC LO
signal, 3-2

next, 4-13

dedicated I/0 device, 6-1 to 6-31

S, 4-13
start, 4-13

dedicated memory device, 6-1

T, 4-14

default bootstrap device, 3—17

T/M, 4-15

deposit
console command, 4-9

test, 4-14

test with menu, 4-15

U, 4-18

device interrupt sequence, 2—18

Device Register, 2-14, D-1

device type, D-2

X, 4-15

diagnostic, 7-1 to 7-13

console mode, 4-1

flags, 7-7

error, 5—12

Console Receive CSR (RXCS), F-11
Console Receive Data Buffer Register
(RXDB), F-11
|

help, 7-6

Console Transmit CSR (TXCS), F-12
Console Transmit Data Buffer Register
(TXDB), F-13

diskette, 6-16

contents-addressable memory, 2—-11

driver output

program categories, 7—1

test repetition, 7-8

double error, 5-5
double-bit error, 3—17

continue

current

control store, 2—11
test, 3—7

voltage

console command, 4-9

PCI bus, C-3

corrected read data (CRD), D-8

DTYPE, 2-14

contents, G—1

CPU, 1-2

block diagram, 2—2

DU series bootstrap code (MSCP devices), J—4

CPU double error, 5-5
halt, 5-11 to 5-12

E console command, 4-9

halt code, 4-3

E/M console command, 5-12

CPU revision code, D-2
CPU section, 2-2 to 2—12

EBDAN, 7-12 to 7-13

CRD (corrected read data), D-8

CTRL/P, 4-2
console command, 4-17
CTRL/Q
console command, 4-17
CTRL/S

console command, 4-17
CTRL/U

EBKAX, 7-12

EEPROM, 2-21, 3-16, 6-9

bootstrap dispatcher, J—2
contents, H-1
customer options

address, 4-9
DU series bootstrap code (MSCP devices),
J-4

Index-3

RX50 bootstrap code, J-3
sample bootstrap code, J-1
test, 3-7

update, 3—4

writing data, 4-10, 6-11

abort, 5—-1

fault, 5—-1

handler, 5-1

trap, 5-1

vector, 5—1

EINTRCSR, 2-14

execution unit, 2—4

ENBL PIPE, E-6
environmental requirements, 1-7

external signals affecting power-up, 3—2

Executive Stack Pointer (ESP), F-3

error

bad parity received, 5-10

F chip, 2-10

BTO, 5-10
console mode, 5-12
CPU double, 5-5
double, 5-5

failure

BIIC transaction bus timeout, 5-10

flag

Memory Address Register, 5-9
VAXBI, 5-9
~
ICRMC, 5-10
ICRMD, 5-10
ID parity error interrupt followmg retry
timeout, K—1
illegal CNF received, 5-10
master port transaction retry timeout, 5-10

master transmit check, 5-10

MTB miss, 5-9

- MTCE, 5-10
NCRMC, 5-10

NO ACK CNF received, 5-10
parity, E—6

test, 3—7

Current Processor Status Longword, 5-11
Current Program Counter, 5-11
microPC, 5-11
Program Counter, 5-11

fault
exception, 5-1

first part done
code, 3—10

(

(FPD) flag, 5-8, 5-11
flag

diagnostic, 7-7

floating-point instruction exerciser, 7-11
forward next character

console command, 4-17
forwarding console mode, 4-2, 4-15

FPD
code, 3—-10

(

(first part done) flag, 5-8, 5-11

port controller detected, 5-9

power-up, 5-12
RDSR, 5-10
read data substitute, 5-10

reserved status code received, 5-10

general register
address, 4-9

good memory
64K-byte block, 3—16

RTO, 5-10

timeout, K-1

transaction error, 5-5

unexpected, K-1
VAXBI node, 5-5

Error Interrupt Control Register, 2-14, D-8
to D-10
contents, G—1
ESP (Executive Stack Pointer), F-3
event code, E-5
error, E—4
EVENT LOCK, E-4
EVKAA, 7-4 to 7-5
EVKAB, 7-10 to 7-11

H console command, 4-13

halt

code, 4-3
console command, 4-13
HALT instruction
halt code, 4-3

hard error interrupt enable (HEIE) bit, D—4
hard-core instruction test, 7—-4 to 7-5
hardware

error, 4-18

generated interrupt, 5—2

EVKAC, 7-11

hardware-fault state
bit (HFSB), 3—6
flag, 5-5

examine

help

console command, 4-9
exception, 5-1

HFSB, 3-6

EVKAE, 7-11

Index—4

’

(

HEIE (hard error interrupt enable) bit, D—4
diagnostic, 7-6

INTRDES Register, 2—-14

Hours Register, 6-12

INVAL transaction, 2—-18

I console command, 4-13

invalid access

I/E chip, 2-3

to an internal processor register, 4-18

and M chip interaction test 87

invalid CNF

internals test, 3—7

code, E-5

I/O address, 2-21
space, 2—13

halt code, 4-3

I/O cables, A—4
I/0 device, 6-1

‘invalidate, 2—18

ICCS (Interval Clock Control Register), F-9

IPIR (Interprocessor Interrupt Request Regis-

IPINTR transaction, 2—17, 2-18

ICR (Interval Count Register), F-10

ICRMC error, 5-10

invalid system control block

ICRMD error, 5-10

ter), F-8

IPL (interrupt priority level), F-7
IPR, 2-9

IDENT transaction, 2—-17, 2—18, 2—-19

IRCI transaction, 2—17 2-18

identify interrupting node, 2-17, 2—18

ISP (Interrupt Stack Pomter) F-3

illegal CNF
received, 5-10
imbedded arbitration cycle 2-15
initialization, 3—-1, 3-8 to 3-12
power-up, 3—9
processor, 3—9

system, 3—-11
initialize

jumper configuration, 3—4
KAB820

block diagram, 1-2

module layout, 1-5
KA820 Serial-Line Unit Diagnostic, 7-12 to
'

console command, 4-13

7-13

Kernel Stack Pointer (KSP), F—2

installation, B—1

KSP (Kernel Stack Pointer), F—2

instruction buffer, 2-3
interlock read with cache intent, 2-17, 2—-18

LED, 34

interlock transaction, 2—18

fault, 3—4

internal processor register, 2-9, F-1 to F-26

red, 3—4, 5-5

address, 4-9
interprocessor interrupt, 2—17, 2-18

Interprocessor Interrupt Request Register
(IPIR), F-8
interrupt, 2-17, 2-18, 5-1
arbitration, 2-19
hardware generated, 5—2
masking, 5-2
microcode generated, 5-2
priority level, 5-1, 5-2
service routine, 2—-20
software generated, 5-1
sublevel, 2—-19

yellow, 3—4
level 2

diagnostic, 7-2
level 2R
diagnostic, 7-2

level 3

diagnostic, 7-1
level 4

diagnostic, 7-1

level 7:4, D-10
light emitting diode (LED), 3—4

load path, 7-2 to 7-3

vector, 2—-19, 5-1

loading microcode for other nodes, 3-17
local console mode, 4-2, 4-15

with unexpected interrupt priority level,

logical console, 3—4, 4-1

5-5

node ID, 4-12

Interrupt Destination Register, 214
interrupt priority level (IPL), 2-18, F-7
interrupt stack not valid

operation, 4-20 to 4-21

loopback

mode, 2-14

halt code, 4-3

Interrupt Stack Pointer (ISP), F-3

transaction, 2-14

loopback connector, 7—12

Interval Clock Control Register (ICCS), F—9

- Interval Count Register (ICR), F-10
INTR transaction, 2-17, 2-18

M chip, 2-5
~

internal register, 4-9

- Index-5

internals test, 3—7
Machine Check Error Summary Register
(MCESR), F-15
machine-check
condition flag, 5-5
exception, 5-5 to 5-11
Memory Address Register, 5-8

module

I/O pin definition, A-1

module installation, B—1
module replacement, B-1
Month Register, 6—12

MTB, 2-5
miss, 2—6

miss error flag, 5-9

parameter 1, 5-8
recovery, 5—6

MTCE error, 5-10

stack, 5—6

MTPR, 2-9

status word, 5-8
Virtual Address Prime Register, 5-8
Virtual Address Register, 5—8

multiprocessor

macrodiagnostic program c, 7—1

MAPEN
|
|
(Memory Management Enable Reglster)

to RXCD Register, D-15
configuration start, 3—21
system, 1-1

N console command, 4-13

NCRMC error, 5-10

F-18
Register

contents, G—1

console command, 4-13

masking interrupts, 52

Next Interval Count Register (NICR), F-10

master

NICR (Next Interval Count Register), F-10

node, 2-16

NO ACK

port transaction retry timeout, 5-10
transmit check error, 5-10
"MCESR (Machine Check Error Summary
Register), F—15

Node

memory

node, 1-4

failure on boot, 4-18
node, 3—-11

confirmation code, 2-17, E-5
received, 5-10

Reset bit (NRST), D—4
ID, D-5

node ending address, 3—11

node starting address, 3—11
size, 3—11

write transaction status, E-5
Memory Address Register locked error flag,
5-9

ID plug, 2-13, D-5
private space, 2—13

nodespace, 2—-13

base addresses, 2—-14
NRST (Node Reset) bit, D—4
operating systems, 1-1

memory device, 6-1

Memory Management Enable Register
(MAPEN), F-18

PO Base Register (POBR), F—4

MFPR, 2-9

POBR (PO Base Register), F—4

to RXCD Register, D-15
MIB bus, 2-3
parity error, 5-5, 5-11

POLR (PO Length Register),
F—4

microaddress generator, 2—4

P1BR (P1 Base Register), F-5

microcode

P1LR (P1 Length Register), F-5

PO Length Register (POLR), F—4

P1 Base Register (P1BR), F-5

P1 Length Register (P1LR), F-5

generated interrupt, 5—2

page table entry, 2-5

patch, 2-21

PAL bus, 2-3, 2-7

patch revision, D-2

parity error, E—6

situation unforeseen, 5-5
microinstruction bus, 2-3
microPC
at failure, 5-11

BTB data, 5-5, 5-9

microsequencer, 2—4

MIB bus, 5-5, 5-11

BTB tag, 5-5, 5-9

cache data, 5-5, 5-9
cache tag, 5-5, 5-9

mini-translation buffer, 2—5

passive release, 5-5

Minutes Register, 6—12

patch, 2—-11

Index—6

block format, 3—17

PRIM circuit, 3-2

error, 4-18

primary bootstrap, 3—16

load sequence

primary patch, 2—-11, 3—-6

console commands, 4-19

primary processor, 1-1, 2-13, 3—4, 3-21, 4-15

loading from the console, 4-19

privileged architecture exerciser, 7-11

primary, 2-11, 3-6

process control block base (PCBB), F—6

reading, 3—20
secondary, 2—-11

processor chip set, 2—2
processor initialization, 3-9, 4-13

loading, 3—-17

Processor Status Longword (PSL), 4-12

PC (Program Counter), 4-3

Program Counter, 4-3

PCBB (Process Control Block Base), F—6
PCI bus, 6-1

at failure, 5-11
program I/O mode, 4-1

addressing, 2-21, 6-1

program mode run, E—4

bidirectional current level, C—4

PSL (Processor Status Longword), 4-12

bidirectional voltage level, C—4

PTE, 2-5

cable, A4

invalidation, 2—7

connector, A—4
device, 2-20

RAM, 2-11

device address, 6-1
driver output current, C-3

RCI transaction, 2-17, 2—18
RCX50 controller, 6-16 to 6-31

driver output voltage, C—3

Clear Address Register, 6-30

input signal current level, C—4

Current Sector Register, 6-26

input signal voltage level, C—4

Current Status Register, 626

off-board signal, C-1

Current Track Register, 626

signal, A-3

data transfer examples, 6-18

PCM module, 3-2, 3-3

data transfer status, 6-22

PCntl CSR, 2-21, E-1 to E-9

contents, G-1

disable, 4-12

Performance Monitor Enable Register (PMR),
F-19

physical address, 4-9

disk surface selection, 6-20
Empty Sector Buffer Register, 6-30
error code, 6-25

Error Register, 6-24

physical console, 3—4

extend function, 621

physical/logical console selection, E-1

Fill Sector Buffer Register, 6-31

pipeline mode control, E—6

function codes, 621

PMR (Performance Monitor Enable Reglster),

Incorrect Track Register, 6-28

F-19

polling VAXBI nodes, 3-11

port controller, 2—-10, 2—20 to 2-21

initialize, 6-21

interface, 2—-21
interrupt enable (RXIE), E-8

block diagram, 2—-20

interrupt request, E-8

timeout, E-7

maintenance mode, 6—20

Port Controller CSR, E-1 to E-9

read address, 6—22

port controller detected error flag, 5-9

read status, 6-20

power

restore drive, 6-21

outage, 221

RX5CA Register, 6-30

requirements, 1-6

RX5CS0 Register, 6-19

power-down/power-up sequence, 3—2

RX5CS1 Register, 623

power-fail restart

RX5CS2 Register, 6-25

halt code, 4-3

RX5CS3 Register, 6-26

power-up, 3—1

RX5CS4 Register, 6-26

error, 5—12

RX5CS5 Register, 6-29

initialization, 3-9

RX5FB Register, 6-31

microcode flow, 3—4

RX5GO Register, 6-30

options, 3-1

prefetch function, 2—4

Sector Register, 6-25

Start Command Register, 6-30

Index—7

System Configuration Register, 6-28
test, 3—7
write sector, 6-22

RDS (read data substitute), D—7, E—-5
RDSR error, 5-10
read data substitute, D-7, E-5
error, 5-10

read sector, 621

read with cache intent, 2-17, 2-18

F-21

- RXDB (Console Receive Data Buffer Regis-

ter), F-11

RXDB1 (Serial-Line Unit 1 Receive Data
RXIE (RCX50 interrupt enable), E-8

read-modify-write, 2—-18

S console command, 4-13.

Receive Console Data Register (RXCD), D-14

sample

to D-15, F-24

bootstrap code, J—1

recovery

console output, 4—4

from machine check, 56

SBR (System Base Register), F-5

red LED, 5-5

- SCBB (System Control Block Base), F—6

secondary bootstrap, 3-16

at boot entry, G-1

(

secondary patches, 2-11, 3-17

at power-up, G-1

loaded, D-2

registers accessible to other nodes, 2—14

loading, 3-17

repair recommendations, 7-3

Seconds Register, 6-12

replacement, B—1

segment A, A-1

reserved status code received

segment B, A-2

SEIE (soft error interrupt enable) bit, D—4

Restart

selecting the KA820, 7-7

push button, 3—2

self-test, 3—4 to 3-8, 4-14

restart, 3—14 to 3—-15

parameter block (RPB), 3—14
warm start, 3—1

restart console output command, 4-17
restart-in-progress flag, 3—14

clearing, 3-17

.console output, 3-8, 4-14

)

(

failure, 3—4, 4-14, 4-18

fast, 3—1
fast/slow selection, E-3
on attached processors, 3—8

slow, 3-1

RETRY confirmation code, 2-17
retry timeout, E-5
error, K-1
ROM, 2-11

status, E-3

status bit, D—4

SELF-TEST PASS, 3-6, E-3

serial-line unit, 2-9, 6-1

ROM/RAM chips, 2—-11

cable, A—4

RPB (restart parameter block), 3-14

connector, A—4

RS232, 2-9
RS423, 2-9
RSTRT HLT, E-1

receive data buffer register, 6-5

RTO error, 5-10

transmit control and status register, 6-6

signal, A-2, C-1
transmit data buffer register, 6-8

command, 7-8

serial-line unit 0, 4-1

light, 3—-16, 4-7

default baud rate, 4-7
|

serial-line unit 1

RX50 bootstrap code, J-3

Receive CSR (RXCS1), F-21

RXCD

Receive Data Buffer Register (RXDB1),

console interrupt, E-8
lock, 2-18
(Receive Console Data Reglster) D—14 to
D-15, F-24

Index-8

control and status register, 6—3

RUN, E—4

RX IRQ, E-8

(

RXCS1 (Serial-Line Unlt 1 Receive CSR)

Buffer Register), F—22

READ transaction, 2-18

error, 5-10

RXCS (Console Receive CSR), F-11

Track Register, 6-23

contents, G-1
Register timeout, 4-18

F-22

Transmit CSR (TXCS1), F-22
Transmit Data Buffer Register (TXDB1),

F-23

SET EVENT command, 7-8

SET FLAGS command, 7-7

system reset control, E-2

setting the time, 3-17

SHOW EVENT command, 7—-8
SHOW FLAGS command, 7-7
SID (System Indentification Register), F-19
signal
|
off-board

drive load characteristics, C—1
output characteristics, C—-1
PCI bus, A-3, C-1

serial-line unit, A-2, C-1
VAXBI, A-1
single-processor system, 1-1

SIRR (Software Interrupt Request Register),
F-7

SISR (Software Interrupt Summary Register,
F-8

T console command, 4-14
T/M console command, 4-15

TBCHK (Translation Buffer Check Register),
F-20

TBDR
(Translation Buffer Disable Register), F—-14

TBDR Register
contents, G—-1
TBIA (Translation Buffer Invalidate All Reg-

ister), F—18
TBIS (Translation Buffer Invalidate Single

console command, 4-14
diagnostic program

slave
node, 2-16

repetitions, 7-8

responses from the KA820, 2—18
SLR (System Length Register), F-5

soft error interrupt enable (SEIE) bit, D—4
software
boot control flags, 4-8, I-1
restart-in-progress flag, 3-14

clearing, 3-17
software generated interrupt, 5-1

Software Interrupt Request Register (SIRR),
F-7

Software Interrupt Summary Register (SISR),
F-8

sequence, 7—3

test with menu

console command, 4-15
time

setting, 3—17
Time of Day Register, 2-21, 6-11
(TODR), F-10
time of year, 6-11
timeout

bus, E-5
error, K-1

port controller, E-7
retry, E-5

software updates, 2—21

SSP (Supervisor Stack Pointer), F-3
STALL

TIMEOUT bit, E-7

TODR, 2-21, 6-11
(Time of Day Register), F—10

confirmation, 2—20
- code, 2-17

transaction, 2-17, 2-18

acknowledged, 2—17

start

KA820 generated, 2—-17

console command, 4—13
STF, 3-7

translation buffer, 2-5

stop console output command, 4-17
-STOP transaction, 2-17, 2-18

Translation Buffer Check Register (TBCHK)

STS bit, D—4

Translation Buffer Disable Register (TBDR),

F-20
F-14

Supervisor Stack Pointer (SSP), F-3

symmetrical multiprocessor system, 1-1
System Base Register (SBR), F-5
system control block, 5-3 to 5-5
read error

(TBIA), F-18
Translation Buffer Invalidate Single Reglster

(TBIS), F-19
transmit

halt code, 4-3

check error, E-5

System Control Block Base (SCBB), F—6
System Control Block Base Register, 5-3
System Indentification Register (SID), F-19

trap

system initialization, 3—11

TXCS (Console Transmit CSR), F-12

sequence, 3—12
SN

Translation Buffer Invalidate All Register

System Length Register (SLR), F-5

exception, 5—-1

TXCS1 (serial-line unit 1 Transmit CSR),
F-22

Index—9

TXDB (Console Transmit Data Buffer Register), F-13

TXDB1 (serial-line unit 1 Transmit Data
|

Buffer Register), F-23

using it stand-alone, 7-5 to 7-8

vector, 5-1, D-10

access control violation fault, 5-3

(

arithmetic fault, 5-3

arithmetic trap, 5-3

ULTRIX-32, 1-1

‘watch chip data format compatibility, 6-16
unexpected error conditions, K-1
unlock write mask with cache intent, 2-17,
2—-18

assignment, 5-3

breakpoint fault, 5-3
CHME instruction trap, 5-3
CHMK instruction trap, 5-3
CHMS instruction trap, 5-3

unrecognized boot device specification, 4-18
unrecognized console command, 4-18
User Stack Pointer (USP), F-3
USP (User Stack Pointer), F—3
UWMCI transaction, 2-17, 2—18

CHMU instruction trap, 5—3

VAX 8200—specific cluster exerciser, 7—12
VAX can’t retry (VCR) flag, 5-8
VAX Diagnostic Supervisor (VDS), 7-1

interrupt, 5-1

VAX interlocked instructions, 2—18
VAXBI, 1-4
address space, 2-12
addressing, 1-5
arbitration, 1-5
event code, 5-9, 5-10

console terminal receive, 5—3

console terminal transmit, 5-3
corrected read data (CRD), 5-3
exception, 5-1

interprocessor interrupt, 5—3
interval timer, 5-3

kernel stack not valid, 5-3

machine-check abort, 5—3
power fail, 5-3

privileged instruction fault, 5-3
RCX50 interface, 5-3

reserved instruction fault, 5-3
reserved operand abort, 5-3 -

forward
console command, 4-15
‘interface, 2-10, 2-12 to 220

reserved operand addressing mode fault,
5-3
|

block diagram, 2—12
memory node, 3—11
node or transaction error, 5-5

RXCD, 5-3

serial-line unit 1 transmit, 5-3

reserved operand fault, 5-3

overview, 1-4 to 1-5

serial-line unit 2 receive, 5—3

serial-line unit 2 transmit, 5-3

signal, A-1
timing, 1-5

serial-line unit 3 receive, 5—3

serial-line unit 3 transmit, 5-3

3-11

VAXBI CSR
contents, G—-1

VAXBI Node Identification Register (BINID),
F-26

VAXBI STOP Register (BISTOP), F-26

VAXBICSR, 2-14, D-2 to D-5
VAXELN, 1-1
|
VCR (VAX can’t retry) flag, 5-8
VDS
flag, 7-7

RUN command, 7-8

software interrupt, 5-3
trace pending fault, 5-3
UNIBUS, 5-3

VAXBI bus error, 5-3

VAXBI passive release, 5—3
XFC instruction fault, 5-3
virtual address, 4-9
VMS, 1-1

watch chip data format compatibility, 6-16

warm start, 3—1, 3—14 to 3—-15
failure, 4-18
watch chip, 6-11

bit rotation, 6—12

using it online, 7-9 to 7-10

CSR B, 6-15

Index—10

translation not valid fault, 5-3

SET EVENT command, 7-8
- SET FLAGS command, 7-7
SHOW EVENT command, 7-8

SHOW FLAGS command, 7-7

(

serial-line unit 1 receive, 5-3

pipeline mode control, E-6

transactions, 2-15
VAXBI Control and Status Register, 2-14,

address, 6-12
CSR, 6-12

CSR A, 6-14

(

CSR D, 6-15

write with cache intent, 2—17, 2—-18

data format, 6—-16
data interpretation, 6-13

write wrong parity

interface, 2—21

WWPE (write wrong parity), E—4

WWPE, E—4

date and time sample, 6-13

WWPO, E-6

WWPO (Write wrong parity), E-6

WCI transaction, 2-17, 2-18
WCSA Register, 3-20, 4-19, F-16
WCSD Register, 3-20, 4-19, F-17
WCSL Register, 3—19, 4-19, F-17
wrap connector, 7—12
Write Memory, E-5
write memory flag, 5-9
WRITE transaction, 2—-18

X console command, 4-15
incorrect checksum, 4-18
Year Register, 612

Z console command, 4-15

Index-11

Mnemonics and Abbreviations Associated with the KA820 Processor Module
EK-KA820-TM
ACCS

Accelerator Control and Status Register

ACLOL

ac power is unsteady when this signal is true
acknowledge transaction confirmation on the VAXBI bus
Argument Pointer Register; also attached processor
asynchronous system trap level
arbitration cycle on the VAXBI bus
VAXBI signal indicating a failing node

battery-backup unit
bus connecting the BIIC with the other circuits on a node
BCI Control and Status Register
broadcast transaction
Bus Error Register
backplane interconnect interface chip
VAXBI Node ID Register
VAXBICSR bit indicating self-test failure
backup translation buffer
11-bit address bus for cache and BTB RAMs
contents-addressable memory (part of control store)
cache miss or BTB miss
VAXBI transaction confirmation code
clock signal
central processor unit
corrected read data

a control and status register
32-bit data and address lines bus
data-in UNIBUS transaction
data-in-pause UNIBUS transaction
data-out UNIBUS transaction
data-out-byte UNIBUS transaction
dc power is unsteady when this signal is true
Device Register
VAXBI to UNIBUS adapter
KAB820-specific serial-line unit diagnostic program
KAB820-specific cluster exerciser diagnostic program
KAB820-specific VAX diagnostic supervisor
electrically erasable programmable read-only memory
EIA
EINTRCSR
ENB APT
ENB PIPE
EVKAA
EVKAB
EVKAC
EVKAE
F chip
FP
FPD
GPR
HEX
HFSB
ICCS
ICR
IDENT
I/E chip
IPL

specification of voltage levels used by serial line units
Error Interrupt Control Register

enable APT signal
enable pipeline signal
hardcore instruction test diagnostic program
basic instruction exerciser diagnostic program
floating-point instruction exerciser diagnostic program
privileged architecture exerciser diagnostic program
floating-point accelerator chip in the CPU
Frame Pointer Register
First Part Done flag
a general purpose register (R0-R15)
hexadecimal (base 16 notation)
Hardware Fault State Bit
Interval Clock Control Register
Interval Count Register
the VAXBI transaction used to solicit an interrupt vector
instruction and execution chip in the CPU
interrupt priority level
an internal processor register
interlock read with cache intent VAXBI transaction
interrupt VAXBI transaction
invalidate VAXBI transaction
interprocessor interrupt VAXBI transaction
VAXBI slot assigned to the primary processor
system control panel assembly
light emitting diode
loopback
memory interface chip in the CPU
move from processor register instruction

40-bit microinstruction bus
mini-translation buffer
move to processor register instruction
no acknowledgment VAXBI transaction confirmation
a number that identifies a VAXBI node
PO Base Register
P1 Base Register
PO Length Register
P1 Length Register
7-bit bus used to address BTB and cache tags within the M chip
Program Counter Register
Process Control Block Base Register
16-bit port controller interface bus
a VAXBI control module used in the KK810 assembly
port controller
page frame number
performance monitor enable signal
primary processor

a power control circuit used on the PCM module
Processor Status Longword
page table entry
’
random access memory
read with cache intent VAXBI transaction

controller for the RX50 diskette drive
read data substitute (containing an uncorrectable error)
return from exception or interrupt instruction

STOP
TODR
TXCS
TXDB

UART
UWMCI
VAXBI
VAXBICSR
VCR
VDS
VMB

WCI
WCSA
WCSD
WCSL
WMCI

read-only memory
restart parameter block
diskette drive
Receive Console Data Register (for VAXBI internode communication)
Serial-Line Unit 0 Receive Control and Status Register
Serial-Line Unit 0 Receive Data Buffer Register
system control block
System Control Block Base Register
System Identification Register
Software Interrupt Summary Register
serial-line unit
Stack Pointer Register
stop VAXBI transaction
Time of Day Register
Serial-Line Unit 0 Transmit Control and Status Register
Serial-Line Unit 0 Transmit Data Buffer Register
universal asynchronous receiver transmitter used in SLU
unlock write mask with cache intent VAXBI transaction
32-bit synchronous system bus
VAXBI Control and Status Register
VAX Can’t Retry flag
VAX Diagnostic Supervisor
primary bootstrap program
write with cache intent VAXBI transaction
first control-store read access register
second control-store read access register
control-store load register
write mask with cache intent VAXBI transaction