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November 1985

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Document:	IEU11-A/IEQ11-A User's Guide
Order Number:	EK-IEUQ1-UG
Revision:	003
Pages:	131
Original Filename:

OCR Text

EK-IEUQ1-UG-003

IEU11-A/IEQ11-A
User's Guide

dlilgliftlall

EK-IEUQ1-UG-003

IEU11-A/IEQ11-A
User's Guide

Prepuored by

Computer Special Systems

Digital Equipment Cormporation « Nashua, NH 03062

3rd Edition, November 1985

The information in this document is subject to change without notice and should
not be construed as a commitment by Digital Equipment Corporation. Digital
Equipment Corporation assumes no responsibility for any errors that may
appear in this document.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation:

SEROOBD TM
DEC
DECmate
DECset
DECsystem-10

DECSYSTEM-20

oecone

DIBOL
MASSBUS
PDP
P/OS

Professional
Rainbow

RSK.

UNIBUS
VAX
VMS
VT

Work Processor

CONTENTS

Page

PREFACE

CHAPTER 1

GENERAL DESCRIPTION

lol

INTRODUCTION ® © 0 000050000 C 00600000 OC OGO PCOOOPOEOIOTSOEOGEOVGTEEESS
PHYSICAL DESCRIPTION .cccccccccccccccsccccscsccssas
IEUll-A Option ComponentsS .....cceccceceveccecceeces
IEQll-A Option Components .....cceccceceeeccceces
APPLICATION EXAMPLES ® 0 0 0000006000600 0000 LeGecLLGss e
FUNCTIONAL
IEC/IEEE

Interface

Address

Command Group

l.4.1.2

Universal

1.4.1.4

Talker

l1.4.1.3

Listener Address Group

l1.4.2

Types of
IEC/IEEE

l1.4.5

GENERAL

[]

OPTION

IEUll1-A

SITE

[

2.9
2.10

2.11

1-11

.ccceccccccccccccccncscanssase

1-15

Interface Functions

UNPACKING

.....cccceceee

AND

INSPECTION ¢ccececoeoess
..cceececccccccccccccoess

M8648

INSTALLATION

Module

1-13

1-14

M8648

.vocececccocccccccccocccss
Installation ProceduUre ....cccececees

MODULE OPERATION ccecccccccccoseese
Operation Verified in a PDP-11
.....................‘...................

Module

System
M8648 Module
FIELD

Operation Verified in a VAX-11
............O...O....QCO..0...........O..

SERVICE

Field

AND

Service

Procedure

CUSTOMER

and

(PDP-1]l

Service

Procedure

2.8.1
2.8.2

ecececececccccccccecos

1-13

REQUIREMENTS

MODULE

system

2.8

1-11

M8648 MODULE CONFIGURATION .cececcocccccccsccoccsess
M8648 Module Configuration Procedure .....ccecee.

VERIFYING

2.7.2

(SCG)

1=9
1-18

ccececececccccceces

ecececececcccoccccseaes

cocceccaccsncscccconcsscccccsonaccassesse

IEUll1-A

MB648

2.
2.7.1

(LAG)

(TAG)

ececeececceccceecs

INSTALLATION

MB8648

VR NN SN N

oooouniunadWwihe

eceecececcceccccscces

(UCG)

Devices ..ceccecececcecncess
..ccecceccccccccsocccascceces

SPECIFICATIONS

INTRODUCTION

SN SE S S

Functional
BuS SYSteM

IEEE 488-1978

1.5

Address GroUp

Secondary Command Group

1.4.3
1.4.4

CHAPTER

(ACG)

Command Group

1-5

1-6
1-9

WW N

l1.4.1.1

® ® 0000000008 00000000 Oss0 e
MeSSageS ....cccececvoccccces

1.4.1

DESCRIPTION

1.3
1.4

1-3

1=3

NNNN?;JNNN

1.2.1
1.2.2

l‘l
1=1

and

(VAX-1]l

ACCEPTANCE

Customer
SYSteM)

IEC/IEEE

...ccceeeees

Acceptance
.cecececececccsccccccccce

1.2

2- 5
2~7

Acceptance
c.cceccceccacccccccccces

2-8

BUS INTERCONNECTION .vceeecesccccccccocass 2=8
IEEE/IEC Bus Interconnect ProceduUre .....c.c.ceeee. 2-9
Testing the IEC/IEEE BuS CableS ...cecececcccee 212

IEQll~-A OPTION UNPACKING AND INSTALLATION .......
IEQl]l SITE REQUIREMENTS .cceccecccoccccccnceaccccese
M8634 MODULE CONFIGURATION .ecceeccocceccococccaes

iii

2-14
2=-15
2=15

CONTENTS

(Cont)

Page

M8634 Module Configuration Procedure ....ccccec.
M8634 MODULE INSTALLATION cccccccccccccccccccccce
M8634 Module Installation Procedure ...ccccececee.
VERIFYING M8634 MODULE OPERATION .ccccccccccccccne
FIELD SERVICE AND CUSTOMER ACCEPTANCE ...ccccccece
IEEE/IEC BUS INTERCONNECTION .ccccccccccccccccces

2.11.1
2.12
2.12.1
2.13

2-20
2-22
IEEE/IEC Bus Interconnection Procedure ........ 2-22
Testing the IEC/IEEE Bus Cables ...cccccccccecee 2-25

2.14
2.15
2.15.1
2.15.2

N
[

W
o

0
*

@
o

W N -

o
0
o
0

W N -

o
e

0
6
8
8
&

wWN -

o
e

¢
8
&
8
5
6
¢
e
o
o

L VIR N

PROGRAMMING

INTRODUCTION .cccccccceccscccccccsccncscsoscsccscccocsoccoe
UNIBUS AQAreSSeS .ecececccsccccccccssccccssscsssse
Register Bit Abbreviations .....ccccc0ccccccccen
IEUl1-A DEVICE REGISTERS cccceccccccccccccsccscsse
IEEE Status Register (ISR) .ccccececceccccccccccces

ONAUNHLLELBWWWWWNNNNFE

OMBWWWWWERNNNRNNNMNMNNNNNNNODNDDNDON

[

‘

WWwWwwWwww

[] []
* [ ] | ] []
NN

CHAPTER 3

WWWWWWWWWWWWwWwwwwwuwwuww
wwwww
®

2-16
2-18
2-18
2-20

Interrupt Mask Register # and Interrupt

3-1
3—1
3-2
3—2
34

Status Register B ..cccccccecccccccccccccccccce 3
Interrupt Mask Register 1 and Interrupt

Status Register 1 c.ccccccccecccccccccccccccsce 3-8
Address Status RegisSter ...cccececcccccoccsess 3-18
Bus Status Register ...ccececcecccccscccccccccscs 3-10
IEEE Interrupt Register (IIR) ...ccccccccecccce 3-10
Address RegiSter .c.cccccccccccccccccccccccccs 3-10
Interrupt Status Register @ ...c.cccccccceces . 3-12
Interrupt Status Register 1 ....cccccccccceces 3-12
IEEE Command Register (ICR) ...ccecccesccccccsss 3-12
Auxiliary Command Register ....cceecceccccces 3-12
Auxiliary CommandS ..cccecececcccccccccccecss 3715

3-20
3-21
3-21
3—22
3=23
3—24
3-25
3—30
ss
cccccccac
Bus Address Register (BAR) cccocecec
Byte Count Register ...ccccccecccccccccccccccce 3-30

Serial Poll RegiSter .....cceecceccccccccccss
Command Pass Through Register ....ceccececses
IEEE Data Register (IDR) cccccccceccccosccccacas
Data Out RegiSter ..cceescecccscccscscscssases
Parallel Poll RegiSter ..cccececcececcccccscanecs
Data IN RegISLEr ..ccceceesceassccccccccscacsss
Control and Status Register (CSR) ecceccecccecccen

Match Character Register .cccccceccocvsccccccccs
STATE DIAGRAM IMPLEMENTATION .cccccecccccccccccce
Auxiliary Commands .c.ccccccececcccocccccccsccns
Acceptor Handshake .cccicccscccceccccccecccccce
Source Handshake ....cccccccccscesscsccsccccscs
Talker and Listener Functions ........... ceecses
SERVICE REQUEST FUNCTION .cccccccccecccccsococccccs
REMOTE/LOCAL FUNCTION ..cccecccccccccccccscsccccce
PARALLEL POLL FUNCTION .cccccccccccsacsccscccsces
iv

3-31
3-32
3-33
3-34
3=36
3—40
3-45
3-48
3—49

.
o
o
*

3-49

3-51

PaSSing ConttO]. © 0 0 0090000080600 0000000000s00s0e0e
System Controller ccccecccececccccccssccscsccsccecs
GENERAL OPERATION .c.cccccccccccccsccccscscsccscscccscscse

3"55
3=57
3-65

INTRODUCTION

REQUIRED

® ® © &0 S 00005 OO OO OO S OO SO GO OH OO S

TOOLS AND

CORRECTIVE

3"62

EQUIPMENT

MAINTENANCE

ccccccccccccccccccacs

® ©® © 0O © 0 O O 0

s OO

OO OO OO OSSO S OO S

Diagnostic Software
SystemS)

APPENDIX A

STANDARD

APPENDIX

REMOTE

APPENDIX

HANDSHAKE

APPENDIX

LSI-1l1l
OE OSSOSO S S e O

(VAX-1l Systems)

.cccccecceece

CONNECTIONS

MESSAGE

CODING

PROCESS

GENERAL

COMMENTS

LIST

EVENTS

(PDP-11 and

® ©® ©® © 0 OO0 O OO OO O OO OO OO OO OO

Diagnostic Software

EXAMPLE

MAINTENANCE

bW
-

bbb

.cccececccccecee

CONTROEBER"FUNCTTW"’J.’......................--...

PROGRAMMING

CHAPTER 4

(Cont)

Remote Configured Parallel Poll

WwN

WOIdIIN
O

WWwwwww
W

CONTENTS

MULTILINE

TIMING

SEQUENCE

® ® © &6 6 00 0 00O OV O P OO OO

FOR

HANDSHAKE

INTERFACE MESSAGES;

PROCESS

OO OO S SO O SO S e

C-l

.ccccccceeeese

C-4

156-7 BIT CODE

REPRESENTATION

FIGURES

No.
IEUll1-A

Option

Components

o
Q
o

Title
....ccceccececcccscsccss

|
R_’JAdOAUV
&N

Figure

IEQ1l-A Option Components ...c.ccccesceccccccccccecs 1
Interprocessor Link .c.cceeececcceccecscscscscccccccocnce 1
Multiple Processor Link .cc.cecececcccccccccsccscccccces 1=
Example Devices on an IEC/IEEE BUS .ccccecceccccces 1
M8648 Module Configuration (UNIBUS) .cecccccccocces 2
BC@P8S-fF1l Test Cable Installed (M8648 Module)
..... 2
IEC Cable Connections (UNIBUS)
.ccecececccccccscece 2=-1

FIGURES
Figure No.
2-4
2-5
2-6
=7
2-8
2-9

(Cont)

Page

Title

IEEE Cable Connections (UNIBUS) .cccccccecccceccses
IEC Cable Test Configuration (UNIBUS) .ccccccceees
IEEE Cable Test Configuration (UNIBUS) c.ccecesee
M8634 Module Configuration (Q-BUST ..ccccccecccces
BC@8S-f1 Test Cable Installed (M8634) .cccccceese
IEC Cable Connections, IEQll=AA .ccccccocccccccee
IBEE Cable ConnectiOnS, IEQll-AB oo o000 0ees OO0
IEC Cable Test Configuration, IEQll-AA .ccccceceee
IEEE Cable Test Configuration, IEQll1-AB .cccceecee
IEC Cable Test Configuration, IEQll-AC .cccceceece

2-11
2-12
2-13
2-17
2=21
2-23

2-24
2-26
2-26

2-27

IEEE Cable ConnectiOnS, IEQll‘AD o0 e ceo 00000600000 2“28

WO OO

WWwwww l:)uwuwu

e WN
K-

IEC Cable Connections, IEQll-AC .cccecccccccceccees 2-29

IEEE Status Register (Write Only)

.ccceccccccccceces 3-5

IEEE Status Register (Read Only) .ccccceccccccscecas 3=5
IEEE Interrupt Register (Write Only) .ccccececees 3-11

IEEE Interrupt Register

(Read Only)

.cccccecceccscs 3-12

IEEE Command Register (Write Only) ..ccccececccees 3-13
IEEE Command Register (Read Only) .ccceccceccccees 3-22

IEEE Data Register (Write Only)

IEEE Data Register (Read Only)

ccccccecceccecccss 323

ccceccecceccccccccss 3—-24

Control and Status RegisSter ..cccececcccsccecccsse 3-25

Control and Status Register

(IEQll-A Only)

......

3-25

Bus Addtess Register ............O...........O... 3-30

Byte Count RegiSter .cceeeccecccccccccccnccsccscecs 3—30
Match Character RegiSter ....cccecceccsccccccscsss 3-31
TMS 9914A Auxiliary Command State Diagram ....... 3-34

TMS 9914A Acceptor Handshake State Diagram ...... 3-35

TMS 9914A Source Handshake State Diagram ........
TMS 9914A Listener State Diagram ...c.ccceecccececee
TMS 9914A Talker State Diagram ...cccccecccscccees
Service Request State Diagram ..cecccececscccccccece
TMS 9914A Remote Local State Diagtam X EEREE XN

TMS 9914A Parallel Poll State Diagram ...ccccceee
TMS 9914A Controller State Diagram ...cccccecececee
Passing Control Between TMS 9914S ..ccccceccecces
IFC and REN PinS © 0 006 0060060060000 0000600606066 060606000000

3-39
3—42
3—43
3-46
3—48
3-50
3=-52
3-56
3-58

IEUll1-A and IEQll1-A Troubleshooting Flowchart .... 4-2
Handshake Process Timing Diagram ..c.ccecccececcecees C=2
Handshake Process Flow Diagram ....ceccccececececess C-3
TABLES

NI
(W

=
=

Table No.

Title

Data Line ® ® © © © © © 0 © O O O P O OGO P O SO O O OO O SO H OSSOSO OSSO0
Interface Management Signal Lines ...ceccccccceces
Handshaking LiNeS c.cececcccccccsccoscsccsscscscccccccs

Page

1-8
1-8
1-9

TABLES

Title

Table No.

éage

Address Command Group (ACG) eo0eceo0o0s 0000000000000
Universal Command Group (UCG) .cecccccccccccccccss

1-4
1-5

NEaWNHWOVO
IO
LE WN - —

1-6
1-7
1-8
1-9
1-1¢0
1-11
1-12
1-13

wwwwwNN?NNNNNNH
|
U

(Cont)

l-lg
1-10

.ccccccccsccccccccss 1-11

Listener Address Group (LAG)

Talker Address Group (TAG)

.cceccceccccceccsccsccscce

Functional Types of Devices

..ccccccccvccccsccces

1-13

Environment Specifications ..ccccccecccceccccececes
Electrical Specifications ..cccecceccecccccccecees

1-15
1=-15

Secondary Command GIOUP ececececcccocscsccscscccss
IEEE 488-1978 Interface Functions ...ccccccceceeces

Performance

IEC/IEEE

Parameters

1-14

..ccccececcecccscccccccceces

1-16

..cccecceccecsccsccccccssss

1-16

Bus ParametersS

IEUll-AA Option

1-11

1=12

Shipping

List

IEUl11-AB Option Shipping List

(IEC

BuS)

(IEEE BuS)

.ccccececcecs

.c.ccccee.

2-2

IEUll-A Site Requirements ..cccceccecccecccccecccecs 2=2
IEQll-AA Option Shipping List (IEC Bus) .cccecec.. 2-14
IEQl11-AB Option Shipping List (IEEE Bus) ........ 2-14

IEQll-A Option Site Requirements

LeVEI

Jumpers

...ccccccccceceee

©® © 00 0000000006 0000000000G0GCSOSIOSLLES

2-15

2"16

System-Dependent Jumper Scheme ....ccccecceececee
IEQll-A Installation Cables ...cccceccceccccceccces

UNIBUS Addresses

2-19
227
® 06 © 00 0000000000060 060000000000 OBOGOS 3-1

Bit Abbreviations

TMS 9914A Read RegisStersS

....cceccceccccccccoccs

c.cceececcccccccscocccsssece

3-2
3= 3
3= 3

TMS 9914A Write Registers .ccececececcceccccccccccecs
Interrupt Mask Register 8 and Interrupt Status
Register @ Bit Description ..cccceevcccecccececceces 3-6
Interrupt Mask Register 1 and Interrupt Status
Register 1 Bit Description ...ccccceccecccccceccecss 3-8
Address Status Register Bit Description ......... 3-10
Address Register Bit Description .ccceccecceccecces 3-11

Auxiliary CommandS

...cccecccecscccccccccccsccccscs

3—14

Control and Status Register Bit Format ....ce.c..
Match Character Register Bit Descriptions .......
Auxiliary Command State Diagram Mnemonics .......

3-28
3-32
3-34

Software

Reset ConditionNs

Acceptor

Handshake

..ccccceeccccccccccccccss

Mnemonics

...cccecccceccccccess

Acceptor Handshake Message OUutputS
Source

Handshake

Mnemonics

3=37

ccccecccscccceacse

3—40

.ccccecccoccscecsccses

3—-44

...c.cccccevcceccccceess

Talker

and

Talker

Function Message OUtPULS

..cececccosccscoacses

Service Request Message OULPULS

..ceececcocccsoes

Service

Request

MNemonNiCS

MNemonicCsS

ccccecececcccscscccsccscss

Remote/Local MNemonicCsS ..cccecccccccacccssccccccss
Parallel Poll MNemoniCS ..ccceecccceccccccccacscss
Parallel Poll Message OutputsS ..ccccececccccececcss

Controller Function Mnemonics ...cccccecececeecees
Controller Punction Message OutputsS ....cceceeee.

Multiline Interface MesSSageS

vii

3—-36

.cccceccecceces

Source Handshake Message OULPULS
Listener

3-16

...ccceceeccecccsscecss

3—-39

3—45
3—47

3—47

3—48
3—50
3—58

3-53
3—-54
3-59

PREFACE

INTENDED AUDIENCE

The IEUll1-A/IEQll-A User's Guide is for either the field service
engineer or the user who must install, program, or maintain either
the IEUII-A option or the IEQII-A option down to the Field Replaceable

Unit

(FRU)

level.

DOCUMENT DESIGN

Chapter 1 provides general information about the IEUll-A option
and the IEQll-A option.
This chapter contains a physical description, application examples, functional description, and general

specifications.

Chapter 2 contains the installation procedure for both the IEUll-A
option and the IEQll-A option.
There are two separate installa-

tion procedures:
one for the IEUll-A option, which is installed
in UNIBUS systems (VAX-l11 and PDP-11), and another for the IEQll-A
option which is installed in Q-Bus systems (LSI-11, MICRO/PDP-1l1
and

MICRO/VAX).

Chapter 3 provides programming information for both the IEUll-A
option and the IEQll-A option.
This chapter defines the register
bits for both the IEUll-A option and IEQll-A option.
Much of this
chapter is taken from the TMS 9914A General Purpose Interface Bus
(GPIB) Controller manual (published by Texas Instruments).
Chapter 4 contains guidelines in troubleshooting the IEUll-A option and the IEQll-A option.
There is a troubleshooting flowchart
and references to the required diagnostics for both options.

RELATED DOCUMENTATION
The

both

following
the

documents

IEUll-A option

Title

PDP-11 Bus

contain

and

the

that

Document Number

Handbook

Source

Shipped
option

with

the

IEUll-A

Shipped
option

with

the

IEQll-A

MP-01179

IEQll1-A

Set

MP-91180

Diagnostic

relevant

Available

Set

EB-17525-20

IEUll-A Print

PDP-11

information

IEQll-A option.

in hardcopy

AC-T@864C-MC

Distributed

EY-1864E-SG-0801

Available

by SDC

Listing

IEX11-A

IEC/IEEE Bus

Interfaces (A Service
Information Guide)

in hardcopy

Document Number

Title

Source

Published

*TMS 9914A General
Purpose Interface Bus
(GPIB) Controller

Published by DIN
Deutsches Inst.fuer

DIN IEC625 Part 1

Normung

*TEEE Standard
1975-78

Additional

this

documents listed above

may be

obtained

E.V.

Published by The
Institute
of
Electrical
and Electronic Engineers

488~

copies

by Texas

Instruments

document

and

printed

copies

the

(except those documents marked with an {*})

from:

Digital Equipment Corporation
444 Whitney Street
Northboro, Massachusetts 61532
ATTN:

Printing and Circulation Services
Customer

Services

(NR2/M15)

Section

IMPORTANT

NOTICE

Texas Instruments reserves the right to make changes at any time
to the TMS 9914A General Purpose Interface Bus (GPIB)
Controller
(IC
uct

chip)
in order
possible.

improve

design

and

supply

the

best

TI cannot assume any responsibility for any circuits
represent that they are free from patent infringement.

accordance

Instruments
for Chapter

with

Instruments

the

Copying

has granted Digital
3 of this document.

prod-

shown

1982
Incorporated

License
Equipment GmbH

Agreement,
publishing

Texas
rights

CHAPTER

GENERAL DESCRIPTION

l.1
INTRODUCTION
This manual describes

two

similar

but

distinct

options:

the

TEUll-A option, and the IEQlI-A option.
The IEUll-A option is a
DMA controller that interfaces a UNIBUS system to two independent
instrument buses (IEC/IEEE).
The IEQll-A option is a DMA controller that interfaces a Q-bus system to two independent instrument
buses (IEC/IEEE).
In both options the instrument buses conform to
both the European Standard IEC 625-1 and the U.S.
Standard IEEE
488-1978.
Each instrument bus can have up to fifteen devices in a
sequential configuration.
The total of fifteen devices includes
the option itself.
NOTE

The

designation

option
is used to refer to both the IEUll-A
option and IEQll-A option simultaneous-

ly.

This

manual

for

IEUll-A
are

IEUll-A/IEQll-A

designation

convenience

option

and

used

only,

the

since

IEQll-A

this

the

option

two distinct options.

Software drivers control and communicate with the IEUll1-A/IEQll-A
option through programmed I/0 transfers, DMA transfers, and interrupts.
DMA

Programmed

transfers

are

transfers
used

for

are

data

normally

used

for

command

bytes.

1.2
PHYSICAL DESCRIPTION
There are two kinds of options:

the

IEUll-A

option,

and

the

IEQll-A option.
The IEUll-A option is used
in UNIBUS systems,
such as the PDP-11 and VAX-1ll systems.
The IEQll-A option is used
in
the Q-BUS systems,
such
as
the
LSI-11,
MICRO/PDP-11
and
MICRO/VAX systems.
NOTE

MICRO/PDP-11
systems
(both
will,

in
the
referred to as

systems
Q22-BUS

and
MICRO/VAX
and BA23 boxes)
following
document,
be
MICRO systems.

—

SWITCH E98

]
PRIORITY

l;:]

—

SWITCHESS

_[1 prucesy]

=—]

M8648 MODULE

BC08S-01
TEST CABLE

BN11C-02
(IEC-625 BUS

17-00384-02

(OPTIONAL IEC-625
BUS CABLE)

BN11D-02
(IEEE-488 BUS

CABLE AND IEEE-488
BULKHEAD PANEL)

Cs-3270

Figure

1-1A

IEUll-A

1-2

Option

Components

1IEUll-A Option Components
- 1.2.1
The IEUll-A option consists of one

M8648

module

and

BC@8S-¢1

test cable.
The type of cable and bulkhead panel depends on
whether the option is used with an IEC bus or an IEEE bus.
1In an
IEC bus installation, the IEC-625 bulkhead will hold an IEC bus
cable (BN1llC-#2).
Although it is shipped with only one cable, a
second cable (17-00384-02) is optional.
In an IEEE bus installation, the IEEE-488 bulkhead attaches to only one IEEE bus cable
(BN11D-82).
A second IEEE-488 bulkhead panel and IEEE bus cable
combination (BNl1llD-@2) is optional.
The BC@8S-01 test cable connects J1 and J2 connectors on the M8648 module when diagnostics
are run to test the IEUll-A option.
Refer to Figure 1-1A for the
IEUll1-A option components.

1.2.2
1IEQll-A Option Components
The IEQll-A option consists of one M8634 module and a BC@8sS-#1
test cable.
The type of cable used with the bulkhead panel
depends on whether the option is used with an IEC bus or IEEE bus.
In an IEC bus installation, the C size IEC-625 bulkhead panel is
used

with

one

(17-60384-01)
IEEE-488

IEC

bus

cable

optional.

bulkhead

panel

In
is

(BNllE-@#l).

IEEE

used

The

bus

with

second

bus

installation,

one

IEEE-488

bus

cable

size

cable

(BN11lF-@l).
The
MICRO systems, a

second cable (786-20161-81) is optional.
For the
B-size IEEE-488 bulkhead panel
is used with one
IEEE-488
bus cable
(BN1l1lK-8C).
The second
cable
(BN1llL-@C)
is
optional.
For IEC Bus applications, a B-size IEC 625-1 bulkhead
panel is used with one IEC 625-1 bus cable (BN1llJ-0C).
The second
cable (BN11M-06C) is optional.
The BC@#8S-P1 test cable connects Jl
and J2 connectors on the M8634 module when diagnostics are run to
test the IEQll-A option.
Refer

Figure

components.

1-1B

and

Figure

2-13

for

the

IEQll-A

option

(

)
32

ces

)

D[]av‘ncu

—

MB8634 MODULE

BC08S-01

TEST CABLE

BN11E-01
(IEC-625 BUS
CABLE AND C-SIZE

IEC-625 BULKHEAD
PANEL)

BN11F-01
(IEEE-488 BUS

CABLE AND C-SIZE
IEEE-488 BULKHEAD
PANEL)

17-00384-01

(OPTIONAL IEC-625
BUS CABLE)

70-20161-01

(OPTIONAL IEEE-488
BUS CABLE)

cs-327M

Figure

1-1B

IEQll-A

1-4

Option

Components

1.3

The

APPLICATION EXAMPLES

IEUll-A/IEQll-A

option

can

configqured

Figure 1-2 shows an interprocessor link,
multiple processor link.

numerous

while Figure 1-3

USER

DEVICE

ways.

shows

USER

DEVICE

IEC/IEEE BUS 1
UNIBUS
CONDUCTOR

PDP-11

IEUT1-A

OR
VAX

- -]
w
o

UNIBUS

CONDUCTOR
PDP-11

VAX

IEUT1-A

c_l‘:;c/nsse BUS 3
USER
DEVICE

>
‘

USER

DEVICE
N

C8-2272

Figure

1-2

Interprocessor

Link

|
‘

USER

DEVICE

IEC/IEEE BUS 1

POP-11

IEC/IEEE BUS 2

VAX

LSi-11

IEQ11-A

<:
> OR
LSi-11 BUS

MICRO

SYSTEMS

MICRO

__::i>>

[

LSk11

IEQ11-A

SYSTEMS

IEC/IEEE BUS 3
|

USER

DEVICE

USER

DEVICE

cs-1273

Figure

1.4
The

1-3

Multiple

Processor

Link

FUNCTIONAL DESCRIPTION
IEC/IEEE bus,
a
standardized

instrumentation bus,
transfers
digital data between a group of instruments and a computer system
(see Figure 1-4).
The data is transmitted in bit-parallel/byteserial format.
The data can consist of either interface messages
or device dependent messages.

There

are

messages

data

lines,

lines.

sixteen

between

five

lines

the

that

devices.

interface

are

used

These

management

lines

control
are

lines,

All data is transferred by means
<8:1>).
Refer to Table 1-1 for data lines
face management signal
lines control
the

and

transmit

follows:

three

eight

handshaking

of the data lines
(DIO
parameters.
The interoverall
bus operations
(Table 1-2 describes these signal lines).
The three handshaking
lines
operate
in
a
three-wire
interlocked
handshake
process
to
transfer each data byte by means of the DIO data lines (Table
1-3
describes the function of these lines, while Appendix C describes
the handshaking process itself)i 6

on| K “uweus

VAX

ameto-TALK,
LUSTEN AND
CONTROL

[——-——-——-——-———-—-——-———-———————-——-———————q-d

IEUT1-A

IEC/IEEE BUS

r—======-=-"°

‘

SIGNAL

GENERATOR

.
tge]

ABLE TO

USTEN

ONLY

l
|
|
COUNTER

ABLE TO

TALK
ONLY

|
|

M8 DATA UNES

# 5

INTERFACE
MANAGEMENT

LINES

ip= 3

________ J

HANDSHAKING
LINES
CS-3274

Figure

1-4

Example

Devices on

IEC/IEEE

Bus

Data Line

Table 1-1

bata

Function

Mnemonic

Signal Name

Input/Owtput

DIO <8:YY lines are the data
the
to
lines
input/output
lines
data
These
IEC/IEEE bus.
are connected to the IEC/IEEE
bus by means of non-inverting

- DTO" <8:1>

transceivers.

Table

Signal Name

Attention

1-2

Interface Management Signal Lines
Function

Mnemonic
ATN

Sent

When

true

the

mands are
lines.

controller
(low),

being

sent over

When false
lines carry data.

Interface

Clear

IFC

Request

Sent

REN

End

Identify

EOI

com-

DIO

these

charge.

Set true (low) by a device
dicate a need for service.

Enable

the

(high),

SRQ-

Remote

charge.

Sent by the system controller to
set the interface system into a
known quiescent state.
The system
controller becomes the controller
in

Service

interface

in-

by system controller to select control either from the front
panel or from the IEC/IEEE bus.

If ATN is false (high), this indi‘cates the end of a message block.

If ATN is true (low), the controller is requesting a parallel poll.

Table 1-3

Signal Name

Mnemonic

Data Valid

DAV

Not Ready For Data

NRFD

Not Data Accepted

NDAC

‘

l1.4.1

Handshaking Lines

Punction
by

Controlled

source

data

ceptors when valid
ented to the bus.

show

ac-

pres-

Sent by acceptor to indicate. readiness

for next byte.

Acceptor

when
the

sets

has

this

latched

I/0 lines.

false

(high)

the data

from

IEC/IEEE Interface Messages

This section describes the messages that may be sent by means of
the IEC/IEEE Bus by a controller-in-charge.
A controller-incharge is an IEUl1-A/IEQll-A option that is active (CACS).
The

messages can be divided

into five groups.

1.
2.
3.

Address Command Group (ACG)
Universal Command Group (UCG)
Listener Address Group (LAG)

Talker Address

Secondary

l.4.1.1

Address

Group (TAG)
Command Group (SCG)

Command Group

(ACG)

-- These

tive only in devices which have been addressed
Talker.
Table 1-4 list the ACG commands.

commands
as

are

effec-

Listener

Table 1-4

Address Command Group (ACG)

mmmmm

Listensr

GTL

Dascription

Go To local

Causes addressed listeners to go

from Ramots mode to Local mode.
when local is trus, a device is
back
ornt
: fro
by its
controdYed
panel controls.

Listensrs

Listener

Selected

Dwvice QQear
Parallel Foll

Configuration

Causes the addressed listensrs

to be reset (initialization).

Causes the addressed listeners

to entsr the Parallel Poll Con—~
figuration mode so that the

addressed listeners are able to
participate in a parallel poll.
The next command must be PPE from
the Secondary Command Group to

allow the listener to respond to

AT or EDI becaming true.
818

Talker

Causes the addressed listeners to

Bxecute
Trigger

start basic operation of the
device of which the listener is

Take Control

Causes a device which has been

a part.

addressed as the talker to
enable its controller to become

the controller-in—charge after
the current controller—in-charge

unasserts AN,

1.4.1.2

Universal

Command

Group

(UCG)

=--

These

commands

affect

all devices which are able to respond without having to be pre-

viously addressed.

The UCG commands are listed in Table 1-5.

Table 1-5

Universal Command Group

(UCG)

Description

Mnemonic

Octal

ASCII

Command

LLO

loeal Lockout

DCL

s24

Device Clear

Causes all devices to be reset

PRU

825

Parallel Poll
Unconfigure

Causes all parallel poll configurations
¢co becanme unconfigured.

SPE

s3e

Serial Poll
Enable

Causes all devices to ignore their local

message RTL (Return To local).
(initialization).

Causes all talkers to enter the serial
poll mode to allow a talker to send a
status byte after being addressed by the
controller-inr~charge.

Serjal Poll
Disable

Causes all talkers to exit the serial
poll mode and return to the normal data

mode.

1.4.1.3
Listener Address Group (LAG) -- These commands may be
used to address one or .more listeners
or to address all listeners
at once.
Addressed listeners become active when the controllerin-charge unasserts ATN.
The LAG commands may be followed by a
secondary address (MSA) to address an extended listener.
Table
1-6

lists the LAG addresses.

Table 1-6

Listener Address Group

(LAG)

Moamonic

Octal

ASCII

MIA 08

Description

Adress
My Listen
Address §

Any listener that recognizes its own address
and is able
an addressed listener,
becomes

.to receive data bytes from a talker as soon as
the controller-in—charge unasserts AIN.

MIA 01

941

My Listen

MIA 38

My Listen

UNL

tnlisten

Causes all listeners to become unaddressed.

Mdaress 1

Mdress 30

l1.4.1.4
Talker Address Group (TAG) -- These commands are used to
address or unaddress one talker.
An addressed talker becomes active when the controller-in-charge unasserts ATN.
The commands in
the

TAG may be

extended

followed

secondary

address

talker.

(MSA)

address

Table

Mnexmonic

Octal

ASCTI

MTA 00

100

1-7

Talker

Address

Description

Address
My Talk

Address §

Group

A talker that recognizes its own address be—
canes an addressed talker, whereas all other

talkers becomes unaddressed. Only one talker
is able to send data via the IEC/IEEE Bus.

D 2

181

My Talk

MTA 30

136

My Talk

UNT

Untalk

Causes the addressed talker to become un~

Address 1

Address 3@

addressed.

l1.4.2
Secondary Command Group (SCG)
The meaning of these commands is defined

command of the Primary Command
Table 1-8 list the SCG commands.

Group

the

(PCG=

preceeding

ACG

UCG

primary

LAG

TAG).

" Table 1-8
ASCI
Octal ic
Memon
PPE A

Secondary Command Group
Command

Parallel Foll

Enable #§1

Dascription

Each PFE command mmt follow a PFC (Parallel
Poll Configure) command which forces currently

addressed listsrers fnto their Farallel Poll
Configuration stats. The PPE command inmdji-

cates to a device how to respond
to a parallel

Poll requast fram the controller-in-charge. A
device responds by sending one status bit on

one of the eight DIO lines. The second digit
of the PPE command mnamonic specifies that

1line, whereas the first digit specifies which

state of the devices status bit should activate the DIO line.
PFor example, PFE 12 instructs the device to activate the DIO line 2
when the device status bit is "1°, and PFE 82

instructs the device to activate that line if
the status
bit is °*#°. A PFarallel
Poll Request is issusd by the controller-in-charge by
actilm.vuthq the EDI line together with the ATN

l4a

Parallel Foll
Pnable 2

146

Parallel Poll
Enable #7

147

Parallel Foll
Enable 88

159

Parallel Poll
Enable 11

151

Parallel Foll
Enable 12

156

Parallel Poll
Enable 17

157

Parallel Poll
Enable 18

168

Parallel Poll
Disable

This comnand must follow its associated PPC

cammard and inhibits devices fram responding
to the Parallel Foll Request.

148

My Secondary
Mdress §

An MSA Command must follow a2 Talker or Listen—
er Address. Devices that use extended addressing will not became addressed as long

as the associated Secondary Address follows
the Primary Address.

My Secondary

175

My Secondary
Address 29

My Secondary

Address 1

Address 38

Types of PFunctional Devices
1.4.3
There are four functional types of devices that can be used on the
IEC/IEEE bus.
These functional types are the following:
Talk only devices
Listen only devices
Talk and listen devices
Talk, listen, and control devices
Table

1-9 describes

these

Table 1-9

types of devices.

Functional Types of Devices

Device Type
Talk

functional

Function

Only

When

signaled,

Example Device
this device

Counter

applies its output to the
DIO lines in a fixed con-

figuration.
The configuration may be altered by a
front panel control.
Listen

Only

Responds to
DIO lines.

Listens and

data

from

the

Printer, signal
generator

This device is configured

Talks

signals

troller,

from

the

receives

Digital

con-

the

multimeter

re-

quested reading, and returns
~the results to the IEC/IEEE
bus.

Talks,
and

Listens,

Controls

Not only

can

but also
tions on

controls all
the IEC/IEEE

l1.4.4
IEC/IEEE Bus System
Each IEC/IEEE Bus system must
to

tween

able

devices.

organize

The

and

three

Controller

°
°

Listener device
Talker device

device

talk

and

have

three

manage

the

functional

listen,

IEUll-A or

operabus.

IEQll-A

basic

functional

information

devices

are

the

elements

exchanged

following:

be-

option can be the
When acting as a controller, the IEU11-A/IEQll-A
An
m
syste controller.
controller-in-charge, as well as the devic
the
in
conta
which
es
IEC/IEEE Bus System can have multiple only one device at a time
controller interface function. However,
e is known as the controllercan be the controller, and this devic
the controller that is able
is
in-charge. The system controller Table
1-2 for the definition of
(see
ages
to send IFC and REN mess device can be assig
ned as system controlIFC and REN). Only one
ler.

controllerAn IEU11-A/IEQll-A option becomes a listener when the
EE bus, or by
in-charge sends its listen address over the IEC/IE
Listen Only
the
with
er
Regist
d
loading its own Auxiliary Comman
bytes from
data
ves
recei
ner
liste
the
,
command (LON). When active
the IEC/IEEE bus to the IEUl1-A/IEQll-A option. Multiple listeners may be configured simul taneously.

the controller-inAn IEUl11-A/IEQll-A option becomes a talker when
IEC/IEEE bus, or
the
of
means
by
s
charge applies its talk addres
the Talk Only
with
ter
Regis
nd
Comma
iary
Auxil
by loading its own
from the
bytes
data
command (TON). When active, the talker sends Only
e at a
devic
one
IEUl1-A/IEQll1-A option to the IEC/IEEE bus.
time acts as a talker.

1.4.5

TIEEE 488-1978 Interface Functions

The IEUl11-A/IEQll-A option provides the IEEE 488-1978 interface
functions listed

in Table 1-18.

Table 1-10

IEEE 488-1978 Interface Functions

Function Name

Mnemonic

Automatic Source Handshake

SH1

Automatic Acceptor Handshake

AHl

Talker and Extended Talker

TS, TES

Listener and Extended Listener

L3, LE3

Service Request

SR1

Remote Local

RL1

Parallel Poll

PPl,

Device Clear

DC1

Device Trigger

DT1

Controller

cl, 2, 3, 4, 5

(includes serial poll capability)

PP2

1.5

GENERAL SPECIFICATIONS

This section contains information on environmental specifications,
electrical specifications,
performance parameters,
and
IEC/IEEE
bus parameters.
Refer to Table 1-11 through Table 1-14 for the
information.

Table

Environmental

1-11

Environment Specifications

Parameter

Specification

Operating Temperature

59 to 58° C

Relative

10%

Humidity

Table

Electrical
Required
Current

Parameter

Voltage(s)
Requirement(s)

UNIBUS/LSI

Logic

1-12

Bus

Load

Levels

IEC/IEEE

Bus

Electrical

90%

Specifications

Specification
+5 V dc
3.5A

(+5%)

volts

(IEUll-A

3.0A @

volts

(IEQll-A

TTL
Load

noncondensing

each bus

Option)
Option)

Table 1-13

Performance Parameters

Specifications

Parameter

Operating

Mode(s)

Programmed

DMA data

I/0 transfers with interrupt.

transfer,

byte

addressing,

and

interrupt.
Transfer

Rate

Maximum
Length

Block

Up to 150K bytes per second (DMA transfer).
Transfer rates dependent on the hardware
configuration
and
operating
system
being
used.
64K bytes

Addressable
Memory

256

(4MB on

Q-22)

Range

Interrupt

Vector

(channel

Vector

(channel

depends

selectable,
on

while

Vector

Vector A is set at A+4.
Priority Level

BR6

Table

(selectable).

1-14

IEC/IEEE

Bus

Parameter

BR4

Two

independent

Devices

Cable

Two

IEC/IEEE

devices on

(includes
Maximum
Length

Q-bus

Parameters

Channel
of

used

Specification

Communication

Number

each

bus

IEUll-A/IEQll-A)

meters

number

(65.6

ft),

(6.56

£t)

devices,

whichever

NOTE

Individual

cable

1length

should

exceed

meters

between

devices.

four

buses

not

times
20

the

meters

less

CHAPTER

INSTALLATION

INTRODUCTION
2.1
The IEUll-A option can be installed in either a PDP-1ll or a VAX-ll
system, while the IEQll-A option can be installed in either a

LSI-11

a MICRO system.

The

installation

procedure

for

and MICRO systems is different from the PDP-1l1l and VAX-ll
since a different module is used.

LSI-ll

systems,

An installation consists of the folldwing six major steps.
l.

Unpacking

Module configuration

Module

Verifying module operation

Field

IEC/IEEE bus

To do
ing:

2.2
The

and

inspection

installation

service and customer

acceptance

interconnection

IEUll-A/IEQll-A option

installation,

perform

the

follow-

)

PDP-11
through

or
VAX-1ll
2.8.

system

installation

Sections

2.2

LSI-11
through

or
MICRO
2.15.

systems

installation

Sections

2.9

TIEUll-A OPTION UNPACKING AND INSPECTION
IEUll-A option is packed according to commercial

tices.

Remove

all

packing

materials

and

check

packing

the

prac-

equipment

against the shipping list.
Table 2-1 lists the items contained in
the IEUll-AA option
(IEC bus), while Table 2-2 1lists the items
contained in the IEUl1-AB option (IEEE bus).

Table 2-1

IEUll-AA Option Shipping List (IEC Bus)

Description

Part Number

Qty.

M8648

Dual IEC/IEEE bus controller (UNIBUS)

BCP8S-01

Test cable

BN11C-@2

BN@1C-62

Table 2-2

Qty.

IEC 625-1 bus system cable with PDP-1l1l

bulkhead panel assembly

Instrument bus cable,

connectors on both ends

IEUll-AB Option Shipping

Part Number

List

dual

IEEE-488

(optional)

(IEEE Bus)

Description

MB648

Dual

IEC/IEEE bus controller

BCP8S-01

Test

cable

BN11lD-@82

BNOlA-82

IEEE

488

head

bus

panel

cable

assembly

with

(UNIBUS)

PDP-11

bulk-

Instrument bus cable, dual IEEE-488
connectors on both ends (optional)

Inspect all
components,

items and carefully check the module for cracks, loose
and breaks
in
the
etched paths.
Report damages or
missing items to the shipper immediately, and inform the DIGITAL
representative.
2.3
IEUll-A SITE REQUIREMENTS
Table 2-3 lists the site requirements

Table

2-3

IEUll-A

for

the

IEUll-A option.

Site Requirements

Parameter

Requirements

Module

DD1l backplane; one
NPR jumper removed

Environment

Voltage

Regquirements

Bulkhead

Panel

Location

Size

Bulkhead

One
Panel

3.5

2-insert

Anywhere

2-2

hex

SPC-slot with

A
unit
bulkhead

frame

Table

2-3

1IEUll-A Site

Requirements

(Cont)

Parameter

Requirements

Device Address

The
factory
installed
address
is
7641686.
The IEUll-A requires an as-—
signment of eight consecutive device
addresses
in the UNIBUS
I/0 page.
The
factory
1installed
address
is
assigned to the first register (ISR 1
and 2).
.

Interrupt

Vector

Address

The

factory

installed

Interrupt

tor

address

The

274.

Vec-

Interrupt

Vector

two

the
bits
Interrupt

Priority

Level

BR6

Address requires a
block of
interrupt vectors (four words) at
beginning
of an address where

<2:8>

(bus

must

grant

equal
jumper

@.
plug).

2.4
Two

M8648 MODULE CONFIGURATION
dip switchpacks and a replaceable bus grant jumper plug determine the M8648 module configurations.
One dip switchpack (E98) is
used for the device address, while the other dip switchpack (E56)
is used for the interrupt vector address.
A bus grant jumper plug
is used to determine the BR level, normally BR6.
2.4.1

Step

M8648

Module

Configuration

Procedure

that the correct device address
(764186)
is set
switchpack E98
(refer to Figure 2-1).
If a second IEUll-A option is used in the same system, another
device address must be assigned
to
the
second
IEUll-A
option.
The device address must always be in increments
of 28
(octal) starting from 8.
Refer to Figure 2-1 for
the dip switchpack address scheme.

Verify

Verify
in dip

that the correct interrupt vector address
(278)
is set in the dip switchpack E56 (refer to Figure 2-1).
If a second IEUll-A option is used in the same system,
another interrupt vector address must be assigned to the
second

IEUll-A

switchpack

option.

address

Refer

scheme.

Figure

2-1

for

the

dip

Verify that the correct bus grant jumper plug
(E67)
is
installed and seated properly (refer to Figure 2-1).
If
the plug
(E67) does not meet the required BR level,
remove

the

plug

and

install

2-3

one

desired

level.

NOTE

Ensure that any changes. from the standard configuration are noted and are

considered during the software driver

...
installation, because the default param-

eters expect a standard hardware configuration.

2.5

M8648 MODULE INSTALLATION

The IEUll-A option can be installed in any DD1l1l system unit or CPU
backplane that accepts hex-height modules. The IEUll-A uses a SPC
slot.

2.5.1

MB648 Module Installation Procedure
Procedure

Step
1

Turn off system power.

Locate the SPC slot in the DD1ll backplane that the M8648

3
4

DO NOT insert the M8648
module is to be installed in.
time.
this
at
ne
module into the backpla

Remove the NPG jumper between pins CAl and CBl from the

designated M8648 slot on backplane.

Remove the Grant Continuity Card

M8648

from the designated

slot.

Connect the M8648 J1 connector to the M8648 J2 connector
Ensure
with a BCP8S-81 cable (refer to Figure 2-2).
conof
A
Pin
to
ed
connect
is
Jl
or
connect
of
A
Pin
that
The BC@8S-81 cable needs to be installed to
nector J2.
run the diagnostics and DEC-X/11 System Exerciser.

Insert the M8648 module into the designated SPC slot.

Turn on

Measure the +5 Vdc (Pin A2, any slot)

2.6

the

backpl ane.

system power.

The voltage

on the DDll system

should be between

VERIFYING M8648 MODULE OPERATION

4.75

and

Choosing which diagnostic to use to verify the operation of the
M8648 module depends on whether the M8648 is installed in a PDP-11
Therefore, if the M8648 module is insystem or a VAX-ll system.
If it is
stalled in a PDP-11 system, proceed to Section 2.6.1.
installed in a VAX-1ll system, proceed to Section 2.6.2.

NOTE

The diagnostics required to verify the
operation of the M8648 module are not
shipped with the IEUll-A option.
The
diagnostics are distributed
to DIGITAL
Field
Service
through
the
Software
Distribution Center (SDC).

2.6.1
M8648 Module Operation Verified in a PDP-11 System
The operation of the M8648 module (PDP-11) is verified by running
the CZIEA?? IEU/IEQ Static Diagnostic.
The loading and operating
procedures for the diagnostic are contained in the program listing.
The BC@8S-g1 cable must be installed (Figqure 2-2).
Perform
the

following:

Run

the

default

series

Run three error free passes of
'Quick Verify' flag selected.

Run one error
selected.

free

pass

tests

for

the

unit.

Tests

through

without

the

'Quick

with

Verify'

the

flag

2.6.2
M8648 Module Operation Verified in a VAX-1ll System
The operation of the M8648 module (VAX-11l) is verified by running
the IEUll-A M8648 Offline Test Diagnostic (EVCDC).
The EVCDC
diagnostic is a repair level
(Level 3)
diagnostic that exercises

M8648

module.

This

diagnostic

requires

VAX-1l1

Diagnostic

Supervisor of V6.11
Diagnostic Supervisor

or
later.
Instructions
for
running
the
can be referenced in the Diagnostic System

User's

respective

Guide

BCABC-@#l

2.7

FIELD

The

for

test

must

SERVICE AND

procedure

pends

VAX-1l1l

the

cable

used

whether

for

the

system.

type

installed

of
to

VAX-ll

run

the

processor.
EVCDC

The

diagnostic.

CUSTOMER ACCEPTANCE
field

MB8648

service

module

Therefore,

and

customer

installed

proceed

acceptance
PDP-11

system

Section

2.7.1

the

in-

M8648 module is installed in a PDP-11 system, and if
stalled in a VAX-11l system, proceed to Section 2.7.2.
NOTE

The diagnostics required for field service and customer acceptance are not
shipped with the IEUll-A option.
The
diagnostics
are distributed
to
DIGITAL
Pield
Service
through
the
Software
Distribution Center (SDC).

2-5

de-

MB8648 MODULE

'; l
I‘rEEE——"
J1(IEC/I
BUS 1)

;: . ::fl
JZIV
(\EC/IEEE BUS 2)

PRIORITY SWITCH

SWITCH

PLUG E87 ESS

€98

(BR6)

—

ON=1

SWITCHPACK ES6

|=)
5

oFF=0

o v 2 ! ; 1 2 : : 9

[oTo[x[

[

[o]1JoJofo]ofofofo]o]

VECTOR ADDRESS
(270)

ON=1

OFF=0

3 4

WanY

DEVICE ADDRESS

=
L

SWITCHPACK ES8

s INOooooonnaon

(764100)

Cs-327%

Figure 2-1

M8648 Module Configuration (UNIBUS)
2-6

2.7.1

Field

Service

and

Customer

Acceptance

Procedure

(PDP-11

System)

The following needs to be performed in order to demonstrate to the
field engineer and to the customer that the IEUll-A option performs correctly.
The BCP8S-Pl cable must be installed
(Figure
°

Ren the

Configure a DEC-X/11 System Exerciser
devices in the PDP-11 system.

Section

Run

been

the

CZIBA??

2.6.1

IBU/IEQ static

(four

exerciser

performed

&ixgnostic

error-free passes).

until

through

complete

the memory.

as outlined

include

"relocation

all

the

cycle®TM

has

BC0O8S-01

TEST CABLE

M8648 MODULE

p2) 8

——]

SWITCH E98

S—
Ji

| —

SWITCH ES6

PRIORITY

Mot

o
CS-327¢

Figure

2-2

BC@8S-f1

Test

Cable

Installed

(M8648

Module)

Pield Service and Customer Acceptance Procedure (VAX-11
System)
the EVCDB diagAfter the EVCDC diagnostic (Section 2.6.2) is run,
field service
the
both
to
trate
demons
nostic needs to be run to
ly. The
proper
ms
perfor
A
IEUllthe
engineer and the customer that
that
stic
diagno
2R)
(Level
level
onal
functi
EVCDB diagnostic is a
2.7.2

exercises an IEUll-A option.

The program runs with the Diagnostic

- The BC@8S-f1l test ca3.2 or later.
Supervisor under VMSTM Version-

ble must be installed to run this diagnostic.

The VMS software driver (IXDRIVER) must be loaded and connected,
using the SYSGEN utility. The VMS software driver (IXDRIVER) must
Refer
be installed before the EVCDB diagnostic can be executed.
to the HELP file under the Diagnostic Supervisor (DS>HELP EVCDB) .

2.8

IEC/IEEE BUS INTERCONNECTION

E bus
The IEUll-A can be a controller for either one or two IEC/IEE
:

systems.

Therefore, there are four possible configurations

IEUll-A acts as a controller for one IEC bus system.

IEUll-A acts as a controller for two IEC bus systems.

IEUll-A acts as a controller for one IEEE bus system.

IEUll-A acts as a controller for two IEEE bus systems.

2.8.1

IEEE/IEC

Bus

Interconnect

Step

1
2

Procedure

Remove

the

BC@8S-Pl

Identify the

test

2-meter

cable

shielded

from

the

cable with

tor on

one end. and. an- AmphenolTM er a

other

the

connected

end.
the

The
I/0

Amphenol

bulkhead

part number
BN11C-#2,
number BN1l1lD-g2.

M8648

while

Berg

connec-

CannonTM connector

Cannon

panel.

module.

IEEE

connector
IEC

cable

has

part

cable

Connect

the
Berg
connector of
the
identified
cable
to
connector on the M8648 module.
Refer to Figure
2-3 for an IEC cable connection,
or Figure 2-4 for an
IEEE cable connection.

the

Determine

are

present:

one
a

IEEE-488

(BN11D-82).

the

2-meter

Bus

this

following

IEC-625

cable

with

second

optional

Bus

cable

I/O

cable

components

(17-98384-82),

bulkhead

present,

panel

connect

the Berg connector to J2 on the M8648 module.
On an
IECBus installation, connect the Amphenol or Cannon connector of the cable
(17-£8384-92)
to
the
I/0
bulkhead
panel.
Refer to Figure 2-3 for an IEC bus cable connection, or Figure 2-4 for an IEEE bus connection.
Attach the
I/0O bulkhead panel(s)
to an available bulkhead frame(s)
with the four screws.
If no bulkhead
frame
is available,
the
I/0 panels can be attached to
the cabinet frame wherever it is most convenient.

BergTM
is a trademark of Berg Electronics.

Amphenofm is

Bunker-Ramo.

trademark

of Amphenol

North

America:

CannonTM
is a trademark of ITT Cannon Electric.

Division of

|
- |

SWITCH ES6.

—

PRIORITY

PLUGESZ.

*
SWITCH-ES8-

mM8648

MODULE

BN11C-02

17-00384-02

(OPTIONAL 1EC-625
BUS CABLE)

I/0 BULKHEAD
PANEL
Ccs-127?

Figure 2-3

1IEC Cable Connections
2-19

(UNIBUS)

—

v
[
SWITCH E56

PRIORMY
PLUG E67

\\\\//72//%

|
SWITCH E98

M8648

MODULE

8N11D-02

(OPTIONAL)

BULKHEAD
PANEL

BULKHEAD
PANEL
CS-2278

Figure

2-4

1IEEE

Cable

2-11

Connections

(UNIBUS)

2.8.2

Testing the IEC/IEEE Bus Cables

To test the IEC/IEEE bus cables that interconnect the M8648 module
to the 1/0 bulkhead panel(s), the following procedure is performed.

Procedure

Step

Both channels on the IEUll1-A option must be used; that
is, the following must be installed:

IEC installation -- an IEC bus cable with I/O bulkhead panel (BN11C-82) and an optional IEC bus cable
(17-96384-82).

Refer to Figure 2-3.

IEEE installation -I/0 bulkhead panels

two IEEE bus cables with two
Refer to Figure
(BN1l1lD-62).

2—40

Interconnect both channels by performing the following:
)

IEC installation -- connect the two channels by installing an instrument bus cable, dual IEC-625 con-

nector on both ends

panel

(refer

(BNS1C-82)

to Figure 2-5).

the

I/0 bulkhead

BN11C-02
IEC-625

I/0 BULKHEAD PANEL

BNO1C-02

INSTRUMENT BUS CABLE,

DUAL IEC-625 CONNECTORS

ON BOTH ENDS

CS-3279

Figure

2-5

1IEC

Cable Test

Configuration

(UNIBUS)

Procedure

Step

IEEE installation -- connect the two channels by in-

stalling an instrument bus cable, dual IEEE-488 con-

nector on both ends (BN@lA-g2)
head panels

to the two I/0 bulk-

(refer to Figure 2-6).

Perform

the module verificatiom procedure

BC@8S-01

test cable.

2.6,

ignoring

in Section

the references

2.6

Section
the

/O BULKHEAD
PANEL

BN11D-02

TO
N

M8648

/O BULKHEAD
PANEL

BN11D-02
TO
J2
M8648

BNO1A-02

INSTRUMENT BUS CABLE.

DUAL IEEE-488 CONNECTORS
ON BOTH ENDS

_—"

C3-3280

Figure 2-6

IEEE Cable Test Configuration

(UNIBUS)

2.9

IEQll-A OPTION UNPACKING AND INSTALLATION

packing pracThe IEQll-A option is packed according to commercialthe
equipment
tices. Remove all packing materials and check
ned in
contai
items
the
against the shipping list. Table 2-4 lists
the IEQll1-AA option (IEC bus) while Table 2-5 lists IEQll-AB

option

(IEEE bus).

Table 2-4

IEQl1-AA/AC Option Shipping List (IEC Bus)

Part Number

Description

M8634

Dual IEC/IEEE bus controller (Q-Bus)

BC@A8S-01

Test cable

BN1lE-81

Qty.

IEC 625-1 bus cable with LSI bulkhead
Used on IEQll-AA.

panel assembly.

IEC 625-1 bus interconnect cable with

BN11J-0C

MICRO

systems

bulkhead

Used on IEQll-AC.

Table 2-5
Qty.

nectors on both ends

assembly.

IEC-625

dual

Instrument Bus cable,

BN@1C-82

panel

(optional)

con-

IEQl1-AB/AD Option Shipping List (IEEE Bus)

Part Number

Description

MB8634

Dual IEC/IEEE bus controller

BCP8S-01

Test cable

BN1llF-01

IEEE

488

bus

panel

assembly.

IEEE

488

bus

cable

LSI

with

Used on

(Q-Bus)

bulkhead

IEQll-AB.

BN11lK-8C

bulkhead

cable with

panel

assembly.

MICRO systems
Used

IEQll1-AD.

BNOlA-02

Instrument

Bus

cable,

connectors on both ends

dual

IEEE-488

(optional)

Inspect all items and carefully check the module for cracks, loose
components, and breaks in the etched paths.
Report damages or
missing items to the shipper immediately, and inform the DIGITAL
representative.

2.16
IEQll SITE REQUIREMENTS
Table 2-6 lists the site requirements

Table 2-6

for the IEQll-A option.

IEQll-A Option Site Requirements

Parameter

Requirement

Module Environment

LSI bus backplane
1

Voltage Requirement

slot

5 Vdc @

'Required I/0 Panel

Location

quad

3.8 A

C size I/0 bulkhead panel,

I/0 Bulkhead

Panel

Device Address

I1/0 bulkhead panel
tem enclosures.

for

Available bulkhead

frame

The

factory

764100

2).

installed

(first

assignment

sys-

address
ISR

eight

secutive device addresses
page is required.

Interrupt Vector Address
:

B-size

MICRO

is
and

con1/0

The first interrupt vector has the
assigned address 2706.
Requires a
block
of
two
interrupt
vectors
(four words) at the beginning address where bits <2:0> must equal
zero.

Priority Interrupt

Level

BR4

2.11
M8634 MODULE CONFIGURATION
Two dip switchpacks and eight Jjumpers

configuration.

One

dip

switchpack

determine

(E41)

the

used

M8634

for

the

module

device

address, while the other dip switchpack (E46)
is used for the interrupt vector address.
Jumpers Wl through W3 are configured according to the type of LSI-11 backplane that the M8634 is installed in.
Jumpers W4 through W6 are used
in conjunction with
the multilevel interrupt integrated circuit which is not presently
available.
Jumpers W7 and W8 provide continuity for the interrupt
acknowledge
(BIAK)
and direct memory access grant
(BDMG)
bus

signals.

2.11.1

M8634 Module Configuration Procedure
Procedure

Step

Verify that the correct device address (764100) is set
If a secin dip switchpack E4l1 (refer to Figure 2-7).
r deanothe
system,
same
the
ond IEQll optiom is used im

vice address must be assigned to the second IEQll opRefer to Figure 2-7 for the dip switchpack
tion.
address

scheme.

Verify that the correct interrupt vector address (270)
If
is set in dip switchpack E46 (refer to Figure 2-7).
a

IEQll

second

option

used

same

the

system,

an-

other interrupt vector address must be assigned to the
Refer to Figure 2-7 for the dip
second IEQll option.
switchpack address scheme.

Verify that jumpers W6 through W4 are configured for the
Refer to both Table 2-7 for the W6
correct BR level.
and Figure 2-7 for the jumper
scheme
jumper
through W4
locations

M8634

the

module.

Jjumper

The

scheme

used only when the multi-level interrupt integrated cir-

cuit is used; otherwise, jumpers W4 through Wé must not
be

installed.

Table 2-7

BR Level Jumpers

Jumper W5

Jumper W4

BR Level

Out

BR 4

Out
In
In

Out
Out
In

In
Out
Out

BR 5
BR 6
BR 7

Jumper W6

NOTE

The

IEQll-A

option

only

supports

Therefore, the multi-level
level 4.
interrupt function is not possible, and
the jumpers W4 through W6 must be out.

2-16

M8634 MODU

SWITCHPACK E41

OFF=0

hjr
1

L
'

]

[}

(LT
L
LR
'

SWITCHPACK Eag

DEVICE ADDRESS

{764100)

X=RELATIVE ADDRESS

OFF=0 !D D 0

s e s T T T<ToTe]
LTel
VECTOR ADDRESS

(270)
X=VECTOR+4

(SECOND VECTOR)
CcS-3281

Figure

2-7

M8634

Module

2-17

Configuration

(Q-Bus)

2.12

M8634 MODULE

INSTALLATION

The M8634 module can be installed in any LSI-11 and MICRO systems
bus backplane that accepts quad-height modules.
The M8634 module
can support 18-bit addressing in backplanes that feature the tra-

ditional LSI-11 bus (Q-bus) or 22-bit addressing in backplanes
Jumpers W1l through W3 must be
that feature the extended Q22 Bus.
configured to accommodate the specific backplane.

2.12.1

M8634 Module Installation Procedure
Procedure

Step
1

Turn system power off.

module is to be installed.
DO
module into the backplane at this

Locate

quad

slot

the

NOT insert
time.

which

Determine

the

kind

backplane

label

the

kind

being

used.

M8634

Refer

backplane.

’

Connect M8634 Jl connector to M8634 J2 connector with a
BC@#8S-@F1l cable (refer to Figure 2-8).
Ensure that Pin A
of connector Jl is connected to Pin A of J2 connector.
The BC#8S-8d1 cable needs to be installed for both the
CZIEA?? IEU/IEQ Static Diagnostic and CXIEA?? DEC-X/11
System Exerciser, and if the M8634
is running
in a
MICRO/VAX for NAIEA? MDM IEQll-A Diagnostic.
Insert

the

quad

slot.

Turn

Measure

the

Verify that jumpers Wl through W3 are installed according to Table 2-8.,
Refer to Figure 2-7 for the jumper
locations.

for

backplane

and

MB8634

module

into

the

system

power,

the

(Pin

(any

Vdc

slot)

V and

A2,

are

5.25

the

any

designated

slot)

ground.

between

4.75

Verify

that

the

computer

booting

the

system

and/or

The

the

backplane

backplane.

voltage

should

hung

Vdc.

2-18

system

running

bus

normal

not

program.

Table 2-8

Backplane

System—-dependent Jumper Scheme

LSI-11 Bus Structure

Module Jumper

Bus

ouTr

Setting

Grant Jumper

Slot A/B

Slot C/4

H9276

Q22-Bus-

C/b—-Bus

W3,W2

W7,W8 *

H9273

Q-Bus

C/D-Bus

W3,W2

W7,W8

H9275

Q22-Bus

. W3,W2

H9270

Q-Bus

Q—-Bus

DDV11-B

Q-Bus

H9278-A

Q22-Bus

W7,W8

See Note

W7,W8

W3,W2

W7,W8

Q-Bus

W3,W2

W7,W8

C/D-Bus

W3,W2

Section 2.14

ouT

VERIFYING M8634 MODULE OPERATION

2.13

ied by running the CZIEA??
The operation of the M8634 is11verif
/PDP-11) and by running
IEU/IEQ Static Diagnostic (LSI- and MICRO
). The loading and
O/VAX
the NAIEA? MDM IEQll-A Diagnostic (MICR
ic are contained in the
operating procedures for the diagnostmust
be installed (Figure
program listing. The BCE8S-#1 cable
2-8).

Perform the following:

Run the default series of tests for the unit.
error,
Run three passes of tests 1 through 26 without 1ansyste
m.
if the M8634 is installed in a traditional LSI-1

Run Tests 27 and 28 to test the upper four address lines,

Run the MDM system (MICRO/VAX Diagnostic Monitor)
verify the M8634, if it is installed in a MICRO/VAX.

if a Q22-bus system is used.

NOTE

The diagnostics required to verify the
M8634 module operation are not shipped
with the

IEQll-A option.

The diagnos-

Field
tics are distributed to DIGITAL
bDistri
re
Softwa
Service through the
ution Center

(SDC).

FIELD SERVICE AND CUSTOMER ACCEPTANCE

2.14

The following needs to be performed in order to demonstrate to the
perfield engineer and to the customer that the IEQll-A option
(Figure
ed
install
be
must
cable
The BC@8S-@1
forms correctly.
2-8).

The

diagnostics

NOTE

required

for

field

service and customer acceptance are not
shipped with the IEQll-A option.

Run the CZIEA?? IEU/IEQ Static Diagnostic and perform all

)

Configure a DEC-X/11 System Exerciser to include all the
devices in the LSI-11 system including CXIEA?? IEU/IEQ

the steps listed in Section 2.13.

DEC-X module.

Run the exerciser until a complete "relocation cycle®

Run the MDM

through the memory has been performed.

system

(MICRO/VAX Diagnostic Monitor)

verify the M8634, if it is installed in a MICRO/VAX.

NOTE

If the M8634 module is installed in a
Q-BUS
backplane
(H9273
or
H9276
or
H9278-A) and the jumpers W7 and W8 are

in, pin CM2 is shorted to CN2 and pin
CR2 to CS2 on the adjacent higher numbered slot.
These connections may be
obstructive in some cases, and can be
deleted by removing the jumpers.

BCO8S-01
TEST CABLE

———

e
—

iT)

SWITCH

E46

woouie [ |
Figure

2-8

BC@8S-01

SWITCH
E41

T
Test Cable

B
Installed

(M8634)

IEEE/IEC BUS INTERCONNECTION

2.15

The IEQll-A can be a controller for either one or two IEC/IEEE bus
systems.

Therefore, there are four possible configurations:

IEQll acts as controller for one IEC bus system.

1IEQll acts as controller for two IEC bus systems.

IEQll acts as controller for one IEEE bus system.

IEQll acts as controller for two IEEE bus systems.

2.15.1

IEEE/IEC Bus Interconnection Procedure
Procedure

Step

1
2

Remove the BC@8S-81 test cable from the M8634 module.

Identify the

1.6 m or

on the other end.
BN11E-#1 and for the
IEEE

cable

systems

.3 m shielded cable with

Berg

connector on one end and an Amphenol or Cannon connector

has

part

An IEC cable has part number
MICRO systems BN11J-6C, while an

number

the

MICRO

identfied cable

to the

BN1l1F-@61

and

for

BN1l1lK-8C.

Connect the Berg connector of the

J1 connector on the M8634 module.
Refer to Figure 2-9
or Figure 2-13 for an IEC cable connection, or Figure
2-10 and Figure 2-14 for an IEEE cable connection.
Determine if one of the
a 1.6 m
are present:

following
or .3 m

optional
IEC-625

components
Bus cable

(17-86384-81 or BN1llM-@C), or an IEEE-488 Bus cable
1If this second cable is
(76-28161-81 or BN1l1lL-@6C).
present, connect the Berg connector to J2 on the M8634

module.
Connect the Amphenol or Cannon connector to I/O
bulkhead panel.
Refer to Figure 2-9 or Figure 2-13 for
an IEC bus cable connection, or Figure 2-18 and Figure
2-14

for

IEEE bus

connection.

Attach the I1/0 bulkhead panel to an available bulkhead
panel frame with the four screws.
If no bulkhead frame
is available, the I/O panel can be attached to the cabinet frame wherever it is most convenient.

Uy
SWITCH U SWITCH
E41

BN11E-O1

E46

&—

M8634
MODULE

(IEC-625 BUS CABLE

AND 1/0 BULKHEAD
PANEL)

17-00384-01

(OPTIONAL
IEC-625 BUS

CABLE)

CS-3283

Figure

2-9

1IEC

Cable Connections,
2-23

IEQll-AA

—

M8634

MODULE

\ W17/

BN11F01

(IEEE-488 BUS
CABLE AND I/0
BULKHEAD PANEL)

—

)

70-20161-01

(OPTIONAL IEEE-488
BUS CABLE)

’

)

Figure 2-10

IEEE Cable Connections,
2-24

IEQll-AB

2.15.2
Testing the IEC/IEEE Bus Cables
To test the IEC/IEEE Bus cables that interconnect the M8634 module
to the I/0 bulkhead panel, the following procedure is performed.
Procedure

Step

Both

is,

channels on the IEQll-A option
the following must be installed:

must

used;

that

IEC installation -- an IEC bus cable with I/0 bulkhead panel
(BN1llE-@#l or BN1l1lJ-8C)
and an
optional
IEC Bus cable (17-00384-061 or BN1l1M-0C).
Refer to
Figure 2-11 or Figure 2-13.
IEEE

installation

IEEE

bus

cable

bulkhead panel
(BN1l1lF-@1
or BNllK-6C),
tional IEEE bus cable (78-286161-61 or
Refer to Figure 2-12 or Figure 2-14.
Interconnect both

channels

performing

the

with

I/0

and an
opBN1llL-8C).

following:

IEC installation -- connect the two channels by installing an instrument bus cable, dual IEC-625 connectors on both ends (BN@1lC-82)
to the I/0 bulkhead
panel (refer to Figure 2-11 or Figure 2-13).
IEEE installation -- connect the two channels by installing an instrument bus cable, dual IEEE-488 connector on both ends
(BN@lA-g2)
to the I/0 bulkhead
panel (refer to Figure 2-12).
Perform
the
module
2.13,
1ignoring
the
BC@A8S-P1

test

verification
procedure
in
references
in Section
2.13

cable.
NOTE

The

BN11lK-06C/BN1l1J-0C

CRO systems.
applies,
and

change.

used

All cabling for
test
procedures

the

MI-

testing
do
not

Section
to
the

BN11E-O1

/O BULKHEAD
PANEL\

17-00384-01
(OPTIONAL IEC-625
BUS CABLE)

8NO1C-02
INSTRUMENTS BUS CABLE,

DUAL IEC-625 CONNECTOR
ON BOTH ENDS

Cs-3288

Figure

2-11

1IEC Cable Test

I/0° BULKHEAD
PA

Configuration,

IEQll-AA

BN11F-01
°

7020161 -01

BNO1A-02

(OPTIONAL IEEE-488

INSTRUMENT BUS CABLE,

BUS CABLE)

DUAL IEEE-488 CONNECTORS

ON BOTH ENDS

Cs-3286

Figure

2-12

1IEEE

Cable Test

2-26

Configuration,

IEQl1-AB

TO J1 M8634

TO J2 M8634
/0

BULKHEAD PANEL

BN11J-0C

—

BNO1C-02

INSTRUMENTS BUS CABLE,
DUAL IEC-625 CONNECTORS .

ON BOTH ENDS

CS-4850

Figure

2-13

1IEC

Cable

Test

Configurations,

IEQll-AC

NOTE

Ensure that Pin A of connector J1 or J2
(M8634)
is connected to Pin A of connector

assembly.

Table

Bulkhead

Cable

Assembly

(included

with

Cable

Second

Controller
on

IEQll-A

Installation

Cables

IEQll-AA

IEQ11-AB

IEQ11-AC

IEQl1-AD

BN1llE-01

BN11lF-@1

BN11J-06C

BN11K-8C

7620161-01

BN1l1M-@C

BN11lL-8C

option)

Optional
to

2-9

M8634

:
17-60384-01

SWITCH

E41

I E46

SWITCH

M8634
/MODULE

BN11L-0C

(OPTIONAL IEEE488 BUS CABLE)

\ BN11K-0C (IEEE488 BUS

CABLE AND I/0
BLKHD PNL)
C3-4108

Figure 2-14

1IEEE Cable Connections,

IEQll-AD

"
SWITCH D

E41

SWITCH

D E46

M8634

/MODULE

BN11M-0C

(OPTIONAL IEC-625
BUS CABLE)

BN11J-0C

(IEC-625 BUS CABLE
AND /0O BULKHEAD PANEL)
CS-4€%1

Figure

2-15

IEC

Cable Connections,

IEQll-AC

CHAPTER

PROGRAMMING

3.1
The

INTRODUCTION
following section

the

UNIBUS.

The

describes

description

for

the

IEUll-A

option

operation

the

IEQII-A

option

operation

the Q-bus is identical to the IEUll-A option, except where
noted.
All software control of the IEUll-A is performed by

it is
means
of device registers.
These device registers are assigned eight
UNIBUS addresses.
PDP-11 or VAX-1ll instructions can be used to
read and write these registers through these assigned addresses.
The
two

IEUll-A performs an interface function between
independent IEC/IEEE bus systems.
Since the

a UNIBUS
IEC/IEEE

and
bus

systems are independent of each other, the IEUll-A has two identical register sets,
To
reduce the number of UNIBUS addresses,
the

two

UNIBUS

can

controlled

MUX

status

bit,
which
registers,

distinguishes between register sets 1 and 2.
With the advantage
of MUX bit, only eight UNIBUS addresses are needed to address the

sixteen
3.1.1
The

UNIBUS

registers.

UNIBUS Addresses

UNIBUS

address assignments are changed by means of
a DIP
switchpack on the IEUll-A module.
The other seven UNIBUS addresses are relative to this base address that is set
in the
switchpack.
The switchpack has a range of 760080 to 777777.
The
factory set address (base address)
is 764106 for both the IEUll-A
option and the IEQll-A option.
Table 3-1 lists the registers and
their addresses.
Registers that are preceded with IEEE are resident in the TMS 9914A.

Table

3-1

Mnemonic

IEEE Status Register

IIR

and

764102

ICR

and

764104

IDR

and

764106

Status

CSR

and

7641180

BAR

and

764112

BCR

and

764114

MCR

and

764116

IEEE

Command

IEEE

Data

Bus

Address

Byte

Count

Match

and

(Octal)

764108 (see Note 1)

Interrupt

Character

Address

ISR 1 and 2

IEEE

Control

UNIBUS Addresses

NOTE

This address is the standard hardware
address. It is the only one that is
freely-selectable via dip switch E98.

s
Register Bit Abbreviationthat

be
describe what action can the
s
Table 3-2 lists abbrevia.tion
in
done to & register brt These abbreviations are used
3.1.2

Table 3-2

Abbreviation

Action

Read only bit; cannot be set or cleared.
Write only bit; always read as zero.

Read/Write bit; may be set or reset.

R/W

cleared
Réad/clear bit; may be read and is er.

R/C

after reading the appropriate regist

R/W8
Not Used

Read/Write

Zero

bit;

may

cleared, but cannot be set.

read

and

Not used: reading of such bits results in

receiving a zero or one - writing of such

bits will have no effect on the appropriate
register.

3.2

1IEUll-A DEVICE REGISTERS

in the IEUll-A
This section describes the device registers used
er sets. One
regist
option. The IEUll-A option has two identical
the other
while
el,
chann
register set controls one IEC/IEEE bus
both
Since
l.
channe
bus
EE
register set controls the other IEC/IE
bed.
descri
is
set
er
regist
one
register sets are identical, only
9914A),
The IEEE registers (those registers that reside in the TMS
3-4
Table
and
ers)
regist
-only
are listed in Table 3-3 (read
(write-only registers).

Table
UNIBUS Address
Offset (octal)
(Word Read Only)

3-3

TMS

9914A Read

Registers

Bit Assignment

ATN

LPAS TPAS

LADS

TADS

ulpa

Address Status REM

LLO

1‘

Bus Status

ATN

DAV NDAC NRFD EOI

SRQ

1IFC

REN

Int

Status

INTS

INT1

END

SPAS

RLC

MAC

Int

Status

GET

ERR

UNC

APT

DCAS

SRQ

1IFC

Cmd

Pass

Thru

DIO8

DIO7

DIO6

DIOS

DIO4

DIO3

DIO2

DIOlL

xXx

Data

DIO8

DIO7

DIO6

DIOS

DIO4

DIO3

DIO2

DIOl

* Reserved to DIGITALTM
Table

3~-4

TMS 9914A Write Registers

UNIBUS Address

Offset

(octal)

Bit Assignment
87

Int Mask ¢

END

SPAS RLC

MAC

Int

GET

ERR

UNC

APT

DCAS

SRQ

1IFC

Mask

xXx

Address

edpa

dal

dat

Serial

rsvl

sS4

Auxiliary

Cmd

c¢s

£4

£3

£2

Parallel

Poll

PP8

PP7

PP6

PPS

PP4

PP3

PP2

PPl

Data

DIO8

DIO?

DIO6

D10S

DIO4

DIO3

DIO2

DIO1

Poll

Out

This address is not decoded by the TMS 9914A.
A write to this
location will have no effect on the device, as if a write
had

not

occurred.

3.2.1

IEEE Status Register (ISR)

four TMS 9914A internal regThe IEEE status register consists of
9, Interrupt Mask Register 1,
isters: Interrupt Mask Register
ter. These four regAddress Status Register, and Bus Status Regis
ng or writing to this
isters use the same UNIBUS address.sameReadi
TMS 9914A internal regisUNIBUS address does not access theonly and
the other two are write
ter, since two registers are read
only (refer to Figures 3-1 and 3-2).

cycle. Since the DATI
To read the ISR requires an UNIBUS DATI
fer, two read cycles to the
cycle is a word (16 bits) dataaretrans
automatically performed by the

registers
TMS 9914A internal
execute one UNIBUS READ cycle.
IEU11-A logic to

S DATOB cycle. Since the ISR
To write to the ISR requires a UNIBU
cycle will load either the
WRITE
S
is only byte-loadable, one UNIBU
order byte) of the ISR.
(high
HOB
LOB (low order byte) or the
the LOB of the ISR is
only
med,
perfor
is
However, if a DATO cycle
'

loaded.

Interrupt Status Register @
3.2.1.1 Interrupt Mask Register # and
ters operate inde—- The Interrupt Mask and Interrupt Status regisalway
s be set when
pendently of each other. The status bits will
the appropriate events occur regardless of the state of the corresponding mask bit.

INT@ and INTI1 (which are
All interrupt bits, with the exception of set
when the appropriate
not storage bits), are edge triggered and
are cleared immediately
condition becomes true. The storage bits Regist
er is read by the
after the corresponding Interrupt Status
during this read
true
s
become
host MPU. If an interrupt condition
g bit is set
pondin
corres
The
.
operation, then the event is stored
are lost.
upts
interr
no
ore,
theref
when the read operation ends;

In addition to being cleared by a read operation, the BO interrupt
is also cleared by writing to the Data Out Register, and the BI
interrupt is cleared by reading the Data In Register.

The interrupt status bits are cleared and held in the 8 condition

while Software Reset (swrst)

is set.

set
The corresponding bit of the Interrupt Mask register mustl be
interexterna
an
cause
to
is
bit
to a 1 if an interrupt status
rupt (INT Low) when it is set.

For example:

INT=INT STATUS.INT MASK

The mask register is not cleared by 'swrst' or the Hardware Reset
It must, therepin (RESET) and will power on in a random state.

to
fore, be written to by the host MPU before 'swrst' is cleared
of
on
operati
for
avoid extraneous interrupts (see Section 3.2.3.2
‘swrst').

INTERRUPT MASK REGISTER 1

INTERRUPT MASK REGISTER 0

wiwliwlwlw]w]|w]w
ERR

GET

APT

UNC

DACS

:
|

IFC |

SRQ

NOT

USED

wliwlwlwl]w

BO
Bl

SPAS
END

00|

MAC
RLC
c3-3123

Figure

3-1

1IEEE

Status

]

00
ADDRESS STATUS REGISTER

Only)

BUS STATUS REGISTER

(Write

]

08,07

00 |

R|IR|R|R|JR|IR|R|R|R|RIR|{R]|R]R]|R]|R

DAV

ATN

NRFD

NDAC

SRQ

EO!

REN

IFC

LLO

REM

LPAS

ATN

LADS

TPAS

ULPA

TADS
CS-3124

Figure

3-2

IEEE

Status

(Read

Only)

s Register are not
The INTZ and INT1 bits of the Interrupt Statu
sked
be true if there are any unma
true status bits. INT1 will
1.
ter
Regis
s
Statu
rupt
Inter
in
1
a
interrupt status bits set to
us
Stat
8> of Interrupt
INTS will be true if any of bits <05:8If
either INT1l or INT@ is
1.
a
to
set
Register @ are unmasked and
true, then the External Interrupt pin (INT) will be pulled low,
not
provided that the Disable All Interrupts feature (dai) has
been

—
set.

ter 8.
Figure 3-1 shows the bit format for the interrupt mask regis
conThe
bits.
0
Table 3-5 defines the interrupt mask register
in
ed
defin
are
s),
thesi
ditions that set these bits (shown in paren
on
set
is
bit
Each
3.3.
n
Sectio
terms of the state diagrams in
the rising edge of the condition shown.

Table 3-5

Interrupt Mask Register # and Interrupt Status

Name

Function

Bit - (Mnemonic)

6
5

Interrupt 1
(INT1)

This will be a 1 when an unmasked status
bit in Interrupt Status Register 1 is set

Interrupt @
(INTQ)

This will be a 1 when any of bits <85:08>
of Interrupt Status Register # is unmasked

Byte In

A data byte has been received in the Data

(BI)

1l.

and set

to a

In Register.

If the mask bit is not set,

no interrupt is generated, but an RFD holdoff will still occur before the next data
If the Shadow Handshake
byte is accepted.
feature is used, this status bit will not
be set. This bit is cleared by reading the
Data In Register as well as after Interrupt
(Set On:

Status Register ¢ has been read.

ACDS1.LACS)

Byte Out
(BO)

This bit is set when the Data Out Register
is available to send a byte over the
IEC/IEEE bus.

This

byte may be

either

command (if the device is a controller), or

data
set.

(if the device

when

the

is a talker).

device

becomes

active

talker or controller, but will not occur if
the Data Out Register has been loaded with

Subsequenta byte that has not been sent.
ly, it will occur after each byte has been
sent and the TMS 9914A register

SGNS.

This bit
3-6

cleared

returns

writing

Table 3-5
'

Interrupt Mask Register

and

Bit Description

Interrupt

Status

(Cont)

Name

Bit

(Mnemonic)

Function
the Data

Out

Interrupt

Status

SGNS.CACS+SGNS.

When

well

reading

(Set

On:

TACS.SHFS)

NOTE

controller

‘

addresses

itself as a
talker and then goes to standby, there
will be a momentary transition of the
source

handshake

into

SIDS

before

TACS

becomes true and it re-enters SGNS.
Under these circumstances,
the TMS 9914A
register is guaranteed to give a BO interrupt

End

Serial

re-entering

°'SGNS'.

This bit indicates that a byte just received by a listener was the last byte in a
string
(that is,
it was received with the
EOI line true).
It is set at the same time
as
the
BI
interrupt.
(Set
Oon:
(ACDS1.LACS.EOI))

(END)

Poll/

Active

This

bit

indicates that the TMS 9914A reghas requested service by means of
rsvl or
rsv2
(in the
Serial
Poll
Register
or Poll Register or Auxiliary
Command Register)
and has
been polled
in
a
serial
pPoll.
It is set on the false transition
of
STRS
when
the
serial
poll
status
byte
is

ister

(SPAs)

sent.

(Set

On:

STRS.SPAS. (APRS1+

APRS2))

Remote/Local
Change (RLC)

This bit is set by any transition between
local and remote states in the Remot
e/Local
function.
(Set
On:
(LOCS—-REMS) + (REMS-LOCS) +
(LWLS-RWLS)+(RWLS-LWLS))

This

Address

Change

(MAC)

bit

indicates

received

that

from

resulted

IEC/IEEE

state

the

occur

not

used,

ter

has

Primary

the

command
bus

change

TMS

9914A

secondary

addressing

indicate

been

that

the

readdressed

the

TMS

been

has
addressed

the

has

which
It

will

being

99]14A

regis-

its

other

address.
(Set
On:
ACDS1.
(MTA.TADSUNT+OTA.TADS+MLA.LADS+UN.LADS))

er 1
3.2.1.2 Interrupt Mask Register 1 and Interrupt Status 1Regist
simiis
-- The operation of Interrupt Mask and Status Register except that
§
lar to that of Interrupt Mask and Status Register
are cleared only
all bits are true storage bits. The status bits
following the register being read and by '‘swrst'.

There is one distinct group of interrupts in this register: GET,

UNC, APT, DCAS, MA.

These interrupts are all set in response to

commands received over the bus and, if unmasked, a Data Accepted
(DAC) holdoff will occur when the interrupt in question 1is set.
This is
It may be released with a 'dacr’ auxiliary command.
further discussed in Section 3.3.2.

The mask bit of the APT interrupt is further used in the talker
When the interrupt is unmasked, the
and listener functions.
of the TMS 9914A register implement
ns
functio
r
talker and listene
the extended talker and extended listener functions of IEEE-488.
Otherwise, these functions implement the talker and listener

functions of

IEEE-488.

Figure 3-1 shows the bit format for the Interrupt Mask Register 1
The conditions that set these bits (shown in parenthesis)
bits.
are defined in terms of the state diagrams in Section 3.3.
Table 3-6

Interrupt Mask Register 1 and Interrupt Status

Name

Bit

(Mnemonic)

Group Execute

1 Bit Description

Trigger

(GET)

Function

This bit is set if a Group Execute Trigger

command
if

the

A DAC holdoff

is received.

interrupt

is unmasked.

occurs

This bit is set if the source handshake be-

Error

comes active and finds that the NDAC and
This indicates
NRFD lines are both high.

(ERR)

that, for whatever reason, there are no ac(Set On: SERS)
ceptors on the bus.

Unrecognized
Command

(UNC)

is set

This bit

command has

been

re-

ceived that has no meaning to the TMS 9914A

Unrecognized

will

only cause

this

only

interrupt

vice

LADS

(except

address

interrupt

for

TADS).

TCT,

commands
the

which

Secondary

de-

will

com-

mands will cause this interrupt only if the

‘pts' auxiliary command has been previously
A DAC holdoff will occur if this inset.
terrupt is unmasked, which effectively en-

ables the command pass through feature.
Unrecognized commands may be inspected in
3-8

Table 3-6

Interrupt Mask Register 1 and Interrupt Status
Register 1 Bit Description (Cont)

Name

Bit

Function

(Mnemonic)

the

Pass

Command

Through

released.

this holdoff is

before

ACDS1.

(Set On:

(uUcG.LLO.SPE.SPD.DCL+
ACG.GET.GTL.SDC.TCT.LADS+TCT.TADS+
SCG.pts))
12

Address
Through

Pass
(APT)

enables

interrupt

this

Unmasking

secondary

addressing.
It is set if a secondary command is received provided that the last
primary command received was a primary talk
or listen address of the TMS9914A register.
A DAC holdoff will occur and the secondary

address may be read from the Command Pass
Through Register.
The holdoff may be released by a
'dacr'
auxiliary command and
the
'cs'
bit
of
the
Auxiliary
Command

Device
Active
(DCAS)

Clear
State

used

indicate

(cs
has

= 1)
been

On:

ACDS1.SCG. (LPAS+TPAS))

that

valid

or an invalid (cs = @) secondary
identified by the host MPU.
(Set

This bit
(DCL) is
clear

is set when a device clear command
received or when a selected device
(SDC)
is received with the TMS 9914A

holdoff

in LADS.
This will
cause
a DAC
if unmasked.
(Set On: ACDS1l.(DCL+

SDC.LADS))

Service

Reguest

(SRQ)

This bit is
controller,

My Address

This

(MA)

recognizes
its primary talk or listen address.
A DAC holdoff will occur if this is
unmasked.
(Set On:
(MLA+MTA).SPMS.aptmk))

Interface
Clear (IFC)

provided for the benefit of the
which
should
execute
a
serial

poll in response to this interrupt.
set when the SRQ line becomes true.
On: SRQ. (CIDS+CADS))
bit

This

bit

vices

that

set

when

the

TMS

9914A

provided

for

the

are

the

System

not

It is
(Set

benefit

de-

Controller.

It is set when the
IFC line becomes true
and
indicates that the TMS 9914A register
has been returned to an idle state.
If the
device is the System Controller,
then the
IFC

interrupt

3-9

not

set.

(Set

On:

IFCIN)

3.2.1.3 Address Status Register -- Figure 3-2 shows the bit
format for the Address Status Register. Table 3-7 describes the

Address Status Register bits.

Address Status Register Bit Description

Table 3-7

Punction

Bit

Mnemonic

REM

The device is in the remote state

LLO

Local lockout is in operation

ATN

The attention line is low (true) on the bus

LPAS

TPAS

LADS (or LACS)

The device is addressed to listen

TADS (or TACS)

The device is addressed to talk

ulpa

mary addressed

addressed state

This bit shows the LSB of the last address

recognized by the TMS 9914A register

3.2.1.4 Bus Status Register -- The host MPU may examine the
status of IEC/IEEE bus management lines at the time of reading.
The IFC bit of this register does not indicate a true value if the
device is a system controller using the 'sic' auxiliary command.

Figure 3-2 shows the bit format for the bus status register.
(IIR)

1EEE Interrupt Register

3.2.2

The IEEE Interrupt Register consists of three TMS9914A internal
Interrupt Status Register 6, Interrupt Status Register
registers:

1, and Address Register.
These three registers use the same
UNIBUS address.
Reading or writing to this UNIBUS address does
not access all three registers, since two are read only and the

other

while

writing

are performed
Section 3.2.1

3.2.2.1
t?e

the

for

same

Reading

only.

DATOB cycle.

the

a description).

IEEE

Address Register -- Figure

address

bits.

is write

requires

Table

3-8

requires a DATI

The

read

3-3 shows

cycle,

write

cycles

(refer

the bit format

for

status

describes

and

the

address

a»

NOT USED

A3
EDPA

DAT

e
-—

ADDRESS REGISTER

eee

=P e enEE———.

Al
A2
Cs-3128

Figure

3-3

IEEE

Interrupt Register

(Write Only)

Address Register Bit Description

Table 3-8
Bit

Mnemonic

edpa

Enable dual primary aadressing mode

dal

Disable listener

dat

Disable talker

<12:08>

AS5-Al

Punction

function

irimary address of the TMS 9914A regiser

Bits AS5-Al1 of this register contain the primary address of the
device.
IEEE-488 1975/78 does not allow a device to be assigned
the value 11111 for bits A5-Al.
When ‘'swrst' is true at power-up,
or if set by the host MPU, the TMS 9914A register is held in an
idle state.
During this time the host MPU may load the primary
address of the device into these bits.
Often, this will be read

from an Address

Switch Register.

The 'edpa' bit is used to enable the dual addressing mode of the
TMS 9914A register.
It causes the LSB of the address to be ignored by the address comparator giving
two consecutive primary
addresses for the device.
The address from which the TMS 9914A
register was selected is indicated by the
‘'ulpa'
bit of the
Address Status Register.
The Address

not

cleared

'swrst'

hardware

reset.

the bit
3.2.2.2 Interrupt Status Register 8@ - Figure 3-4 shows
and Section
format for the Interrupt Status Register @. Table 3-5
3.2.1.1 describes the Interrupt Status Register # bits.

3.2.2.3

Interrupt Status Register 1 -- Figure 3-4 shows the bit

Table 3-6 and Section

format for the Interrupt Status Register 1.

3.2.1.2 describes the Interrupt Status Register 1 bits.

3.2.3

IEEE Command Register

(ICR)

The IEEE Command Register consists of three TMS 9914A internal
Auxiliary Command Register, Serial Poll Register, and
registers:
Command Pass Through Register. These three registers use the same
Reading or writing to this UNIBUS address does
UNIBUS address.

not access all three registers, since two are write only and the
Reading requires a DATI cycle, while
other register is read only.
The read and write cycles are
writing requires a DATOB cycle.
performed the same as the IEEE status register (refer to Section
3.2.1 for a description).

3.2.3.1 Auxiliary Command Register -- Auxiliary commands are used
to enable and disable most of the selectable features of the TMS
The
9914A register and to initiate many of the device actions.
desired feature is selected by writing a byte to this register
These values are given
with the appropriate value in bits f4-fg.
in Table 3-9.
Figure .3-5 shows the bit format of the Auxiliary

Command Register.

INTERRUPT STATUS REGISTER O

INTERRUPT STATUS REGISTER 1

1§

08,07

R/C|R/c|Rc]R/C|R/C|R/C]R/ICIR/IC]R/C|R/IC|R/IC|R/C|R/C|R/C|R/C]R/C

ERR
GET

APT
UNC

MA
DCAS

IFC
SRQ

INT?
INTO

80
8i

SPAS

MAC

END
Cs-312¢8

Figure 3-4

1IEEE Interrupt Register

(Read Only)

07
SERIAL POLL REGISTER

-—

ome

a»

AUXILIARY COMMAND REGISTER

Tw]w|w|w

BEEEE
|

c/s

FO
1

00|

WIWIWIWIWIWIWIW

NEREEE

RSV1

S2
CS-3127

Figure

3-5

IEEE

Command

(Write

Only)

The 'cs' bit is used in most cases when the feature selected by
f4-f@ is of the clear/set type.
The feature is enabled if ‘'cs' =

'1' and disabled if 'cs' = '@'.
The holdoff on all data (hdfa)
feature
is an example of such a feature.
Other auxiliary commands
initiate an action of the TMS 9914A register, such as release RFD
holdoff (rhdf).
1In most cases, the 'cs' bit is unused and ignored
by

these

commands.

All the clear/set auxiliary commands are cleared by the
RESET pin except 'swrst,' which is set true by RESET.
The force group execute trigger (fget) and
auxiliary commands have a clear/set mode of
mode of
if they
viously

hardware

return to local
(rtl)
operation and a pulsed

operation.
They behave as normal clear/set features, but
are written with 'cs' = '@' when they have not been preset, then they will pulse true.
Using the 'fget' command

in this manner will produce a pulse of approximately 1 microsecond
at the TR pin (with a 5 MHz clock).
The 'rtl' command in this way
will cause a return to one of the local
states
(assuming
local
lockout is not in force)
but the TMS 9914A register may re-enter
the remote state next time the listen address occurs.
NOTE

The TR pin signal is
the IEUll-A option.

not

available

Table 3-9

Auxiliary Commands

c/s

£3

£f2

£f1

f£f#

Mnemonic

Features

8/1

)

swrst

Software reset

dacr

Relezse DAC holdoff

)

rhdf

Release RFD holdoff

)

hd fa

Holdoff on all data

8/1

)

hdfe

Holdoff on EOI only

)

nbaf

New byte available false

8/1

)

fget

Porce group execute

rtl

Return to local

)

feol

Send

)

lon

Listen only

8/1

)

ton

Talk only

gts

tca

Take control

asynchronously

tcs

Take

synchronously

rpPp

Request parallel poll

8/1

)

sic

Send

interface

6/1

)

sre

Send

remote

[}

rqc

Request control

)

rlc

Release

control

8/1

dai

Disable

all

pts

Pass

)

stdl

Short Tl

6/1

shdw

Shadow handshake

2/1

)

vstdl

Very short Tl

8/1

rsv2

Request Service Bit 2

EOI with

trigger

next byte

standby

control

clear

enable

interrupts

through

settling

secondary

time

delay

3.2.3.2

Auxiliary Commands --

Software

Reset

Setting

this

(swrst)

command

8/1xx00000

causes

the

TMS 9914A

returned

to a known idle state during which it will not take part in any
activity on the IEC/IEEE.
This auxiliary command is set by the
power-omr RESET and- the chipshould be configured while 'swrst'
is

set.

vice

Configuration

into

the

should

Address

include writing

writing

the

mask

address

values

the de-

into

the

Interrupt Mask Registers,
and selecting
the desired
features
in
the Auxiliary Command Register and Address Register.
After this,
'swrst' may be cleared, at which point the device becomes logic-

ally existent on the IEC/IEEE.
The Serial Poll Register and
Parallel Poll Registers may also be written in this period, but
this is not necessary if there is no status to report, as both of
these are cleared by the
various states and other

power-on RESET pin.
conditions forced by

3-15

Table 3-18
'swrst'.

lists

the

Software Reset Conditions

Table 3-18

Description

Mnemonic

idle state

Source

SIDS

Acceptor

KIDS

Idle state

idle state

TIDS

Talker

TPAS

Talker primary idle state

LIDS

Listener

LPAS

Listener primary state

NPRS

Negative poll

LOCS

Local

CIDS

Controller idle state

SPIS

Serial

PPSS

Parallel

ADHS

DAC holdoff

state

ANHS

RFD holdoff

state

AEHS

RFD holdoff

SHFS

ENIS

idle state

response state

state

poll

idle state

poll

standby state

end

state

Source holdoff state
END

idle

state

NOTE

See

Section

for

definition

above.

All

not

interrupt

state,

but

affected.

status

bits are held

interrupt

mask

bits

in
are

Release DAC Holdoff

(dacr)@/lxxg0661

The Data Accepted (DAC) holdoff allows time for the host microprocessor to respond to unrecognized commands, secondary addresses, and device trigger or device clear commands.
The holdoff is
Norreleased by the MPU when the required action has been taken.
howzero;
at
bit
clear/set
the
with
loaded
is
mally the command

ever, when used with the address pass through feature, CS @s set

Release RFD Holdoff

(rhdf)naxxggglp

Any

(RFD)

Ready

For

secondary address was valid)

(if the

to one

valid).

Data

holdoff

caused

(if

in-

'hdfe'

zero

'hdfa'

released.

Holdoff on All Data (hdfa)@/l1xx@8811
A Ready For Data (RFD) holdoff is caused on every data byte until
the command is loaded with CS set to zero.
The handshake must be
completed

after

Holdoff on

End

'rhdf'

each

command.

byte

has

been

received

the

MPU

New
a

Byte Available

talker

the

(hdfe)@d/1xx80100

An RFD holdoff will occur when an end of data string
true with ATN false) is received over the interface.
must be released using 'rhdf'.
Set

using

False

interrupted

message (EOI
This holdoff

(nbaf)naxx@glgl

before

the

byte

just

out register is sent over the interface, this
be transmitted as soon as the ATN line returns

stored

the

data

byte will normally
to the false state.

If, as a result of the interrupt, this byte is no longer required,
its transmission may be suppressed using the 'nbaf' command.
Force Group
The

state

when

this

Execute

the

command

Trigger
output

(fget)@/1xx@00110
from

the

executed.

1If

TMS
the

9914A
CS

bit

the

zero,

affected
line

pulsed high for approximately 5 clock cycles
(1 microsecond at §
MHz).
1If CS is one, the TR line goes high until
'fget'
is sent
with CS equal to zero.
No interrupts or handshakes are initiated.
NOTE

The

Return

Provided

Local

the

mote/local

signal

not

available

the

(rtl)G/lxxflflll{

local

status

1lockout

bit

(LLO)

reset,

has

and

not

been

interrupt

enabled,
is

the

re-

generated

(if

enabled) to inform the host microprocessor that it should respond

If the CS bit is set to one the

to the front panel controls.

‘rtl' command must be cleared (CS = @) before the device is able
to return to remote control. If CS is set to zero, the device may
return to remote without first clearing 'rtl’'.

Force End or Identify (feoi)naxx01000

}his command causes the EOI message to be sent with the next data
Listen Only

reset.

then

The EOI line

byte.

(lon)B/1xx810061

The listener state is activated until the command is sent with CS
set to @ or until deactivated by a bus command.

Talk Only

(ton)@/1xxG1610

The talker state is activated until the command
set to @ or until deactivated by a bus command.

sent

with

NOTE

'ton'

and

'lon'

are

included

where

the

TMS

9914A

systems without a controller.
as

ly.

Care

use

However,

a controller,

used

for

being

it utilizes the

'‘lon' and 'ton' functions to set itself
up as a listener or talker, respective-

ensure

sending
Go

Standby

Issued
Take

Control

1is

asserted.

therefore

functions

UNL or

OTA.

controller

Synchronously

again
If

taken

the

charge

set

and

only

ensures

that

Request

Parallel

This
poll
the

reset

the ATN

the

controller

sends
no

controller

ATN

true

lost

data

Poll

line

false.

(tcs)naxxgllgl

not

the

true

handshake command must be used to monitor
that the TMS 9914A register is synchronous

ers

taken

are

(gts)naxx@lgll

the

Control

must

these

end

charge,

and

ATN

listener,

the

shadow

the handshake lines so
with the talker/listen-

byte

transfer.

This

corrupted.

(rpp)@/1xx@1119

is executed by the controller in charge to send the parallel
command over the interface (the TMS 9914A register must be in
Controller
Active
State
so
that
the
Attention
1line
is

asserted).

The

poll

completed

Through Register
to obtain
with the CS bit at zero.

the

status

reading

bits,

the

then

Command

Pass

sending

‘rpp'

Take Control

This

Asynchronously

command

tention

line

used

true

and

(tca)naxx8l190

the

controller

gain

control

charge

the

set

interface.

the
The

atcon-

mand is executed immediately and data corruption or loss may occur
if a talker/listener is in the process of transferring a data
byte.

Send

Interface

Clear

(sic)@/1xx@1111

The IFC line is set true when this command is sent with CS set to
one.
This must only be sent by the system controller and should
be reset (CS = @) after the IEEE minimum time for IFC has elapsed
(196 microseconds).
The system controller
is
put
into
the
controller active state.
Send

Remote

Enable

(sre)@/1xx100060

Issued

by the system controller to
remote enable message over the
sending 'sre' with CS at zero.

set

the REN line true
interface, REN is set

the

Request

When

Control

the

and

TCT command

Release

This

the

has

controller

Control

command

Pleted

Disable

been

recognized

by means

the

unidenti-

active

state

(CACS).

used
the

Interrupts

after
ATN

TCT

line

has

and

Pass

Through

This

feature may be

poll.

sent

and

handshake

control

another

com-

device.

(dai)@/lxx108611

Secondary

used

The

been

pass

The INT line is disabled, but the
holdoffs selected are not affected.

parallel

The
then

(rlc)naxxlgg@lo

release

All

(rgc)naxxl@gg@ggl

fied command pass through, this command is sent by the MPU.
TMS 9914A register waits for the ATN line to go false and
enters

send

false

interrupt

registers

and

any

(pts)naxxl1¢100

carry out

parallel

poll

passed through
command and is

remote

configuration of

configqure

command
unrecognized

(PPC)
is
addressed

the TMS 9914A register as an
identified by the MPU.
The 'pts' command is loaded, and the next byte received by the TMS 9914A register is passed
through by means of the Command Pass Through Register.
This would
be the parallel poll enable (PPE), which is read by the microprocessor.

Set

T1l

Delay

(stdl)lxxl@lgl

The Tl delay time can be set to 6 clock cycles
if this command is sent with the CS bit at one.

3-19

(1.2

MHz)

The

delay

time

5 MHz) following a poweris 11 clock cycles (2.2 microseconds at CS
set to zero.
on reset or if the command is sent with
Shadow Handshake (shdw)B8/1xx181108

carry out the
oller in charge to tran
This feature enables the contr
sfer. The’
a
dat
a
in
g
eut participatin
listener handshake with
3 clock
pulled true a maximum ofy For
Data Accepted line (DAC) is is
Data
Read
Not
and
,
ived
rece
(DAV)
cycles after Data valid false
as soon as DAV is removed.
(NRFD) is allowed to go

syns the tcs' command to be
The shadow handshake functionNotallow
can
ATN
that
so
)
(ANRS
State
chronized with the Acceptor ng Read
data
of
on
upti
corr
or
the loss
be re asserted without causi
received and causes an RFD

byte.

The END interrupt can also be

holdoff to be generated.

Very Short Tl Delay (vstdl)@/1xx10111

ing time (T1) will be
1f this feature is enabled the GPIB5 settl
on the second and subMHz)
at
reduced to 3 clock cycles (688 isns false
wise the IEC/IEEE
Oother
.
sequent data bytes when ATN

settling time is determined by the stdl feature.
Request Service Bit 2 (rsv2)0/1xx11000

as the rsvl bit (see SecThe rsv2 bit performs the same function
requesting service which is

of
tion 2.1.8) but provides a meansRegist
This allows minor uper.
Poll
Serial
the
of
ndent
indepe
without affecting the
ster
dates to be made to the Serial Poll Regi
state of the request service.

is
the serial poll status byte
In addition, rsv2 is cleared when
used
e
efor
ther
is
serial poll. It

sent to the controller duringe arequest is simply a request from an
in situations where a servic
this
er to poll its status. As soon as
instrument for the controllsince
ce
servi
sting
reque
for
n
the reaso
happens rsv2 is cleared
the
ring
clea
of
en
burd
the
es
has been satisfied. This eliminat
guarantees that rsv2 is cleared
bit from the host MPU, but also

1f this were not so, there
before another serial poll can occur
byte being sent with the
status
second
a
of
would be a possibility
sion for the controlconfu
in
t
resul
could
RQS message true, which
ler (rsv2 is cleared on. SPAS (APRS1+APRS2) .STRS) .

3.2.3.3

Serial Poll Register -- Figure 3-5 shows the bit format

for the serial poll register.

the IEC/IEEE
Bits S8, S6 S1 of this register are sent out l over
They are
poll.
seria
a
g
durin
ssed
addre
when the device is
cleared by a hardware reset but not by ‘swrst' and may therefore

chip. These bits are fully
be set up during configuration of the
is written to while the device

double buffered and if the register

is addressed during a serial poll (serial poll active state,
3-26

SPAS),

the value written

SPAS

terminated.

The

rsvl

is saved,

and these bits are updated when

input

the

bit provides an

service

request

function

the TMS 9914A register and is used to instruct this to request
that the controller service the device.
When rsvl is set true,
the SRQ line is pulled true on the IEC/IEEE bus, and the con—
troller typically responds by setting up a serial poll to obtain
the status of all instruments on the bus that may require service.

When the TMS 9914A register is addressed to send its status byte,
SRQ is set false, and the status byte is sent with the RQS message
true on DIO7.
The rsvl bit must then be cleared
again if service is to be requested a second time.
terrupt is set immediately following the status byte
The

rsvl

bit

also

'swrst'.

not double-buffered,

cleared

the

hardware
but

the

reset

and set true
The SPAS inbeing sent.

service

but

not

request

func-

tion comprehends changes in the state of rsvl while the device is
in SPAS.
The Serial Poll Register may therefore be written to any
time.

3.2.3.4
format

This

Command
for

the

provides

Pass Through Register -- Figure

Command

Pass

Through

directly

means

3-6

shows

the

bit

inspecting

the

IEC/IEEE

data

lines (DIO(8-1)).
It has no storage and should only be used when
the data lines are known to be in a steady state such as will
occur during a DAC holdoff or in CPWS during a parallel poll.
It
is used to read unrecognized commands and secondaries following a
UNC interrupt or to read secondary addresses following an APT
interrupt.
1In addition, an active controller uses this register
to read
the results of a parallel poll
at
after setting the 'rpp' auxiliary command.

least

microseconds

3.2.4
IEEE Data Register (IDR)
The IEEE Data Register consists of three TMS 9914A internal registers: Data Out Register, Parallel Poll Register, and Data In Register.
These three registers use the same UNIBUS address.
Reading or writing to this UNIBUS address does not access all three
registers, since two are write only and the other register is read
only.
Reading
requires
a
DATI
cycle,
while
writing
requires
a
DATOB

the

cycle.

IEEE

tion).

The

status

read

and

write

(refer

cycles

are

Section

performed

the

3.2.1

for

same

descrip-

COMMAND PASS THROUGH REGISTER

-e

CED

SND

oEP

GED TED

SED

AEN

NOT USED

CmB

DI0O6

Dio4

00|

DIO1

DIO3

DIOS

D07

Dio8

DIO2
Cs-3128

Figure 3-6

3.2.4.1

IEEE Command Register

(Read Only)

Data Out Register -- Figure 3-7 shows the bit format for

the Data Out Register.

The Data Out Register is used by a controller or talker for sendWhen the
ing interface messages and device dependent messages.
or the
(TACS)
State
Active
Talker
the
TMS 9914A register enters
RegOut
Data
the
of
contents
the
(CACS),
State
Active
Controller
ister are presented to the IEC/IEEE data lines (D1I0(8-1)), and the
byte is set over the bus under the control of the Source HandEach time a byte is written, the source handshake is
shake.
If the handshake is interbottom enabled, and the byte is sent.

rupted before the byte can be sent, then it will be sent the next
time the Source Bandshake becomes active unless a new byte availThis has the
able false (nbaf) auxiliary command is written.
and
Register,
Out
Data
the
from
byte
unsent
effect of clearing an
regis9914A
TMS
the
cleared,
not
is
itself
register
although the
ter behaves as

it had not been loaded.

Each time the source handshake becomes active and there is no unsent byte in the Data Out Register, a BO interrupt will occur,
informing the host MPU that the Data Out Register is available for
use.

The Data In Register and Data Out Register operate

independently.

The Data Out Register is not double buffered, and its contents are
output directly to the data lines of the IEC/IEEE.

3.2.4.2

Parallel Poll Register -- Figure 3-7 shows the bit format

for the Parallel

Poll

When a controller initiates a parallel poll, the contents of this
register are presented to the IEC/IEEE data lines.
If all bits of
the register are cleared, then none of the lines DIO(8-1l) will be
pulled low during a parallel poll which corresponds to the Par-

allel

Pol)}

Idle

State

(PPIS)

IEEE-48%.,

desired

participate in a parallel poll, then the bit corresponding
desired parallel poll response is set to a 1.

the

The

but

not

Parallel

Poll

fully double

buffered.

written to during a parallel poll, the new value is held until the
parallel poll ends, at which point the register is updated.
This
permits the host MPU to update the parallel poll response completely asynchronously to

it may
set.

cleared

loaded

IEC/IEEE.

while

the

DI08

DIOS
DI0O6

DI03
D104

RESET

being

configured

oO8

chip

PARALLEL POLL REGISTER

DI07

hardware

DATA OUT REGISTER

-t

'swrst'

this

'swrst',

the

DIO1 |
DI02

00|

WIWIWIWIWIWIWIW

PP7

PP8

PPS

PP6

PP3

PP4

PP2
CS-3129

Figure

3-7

1IEEE

Data

(Write

Only)

with

Data In Register -- Figure 3-8 shows the bit format for

3.2.4.3

the Data In Register.

This register is used to hold data received by the TMS 9914A
It is loaded during Accept Data
register when it is a listener.

State (ACDS1l) and, following this, an RFD holdoff will occur.
This will normally be released when the byte is read by the host
f AlI Data (hdfa] feature is selected,
MPU, but if the HoldofOn
this holdoff must be released by the 'rhdf' auxiliary command.

If the Holdoff On End (HDFE) feature is selected, the RFD holdoff

But if the EOI
will be released by reading the Data In Register.
line is true when the byte is received, reading the data byte will
not release the holdoff and rhdf must be used.

The
As the Data In Register is loaded, the BI interrupt is set.
by
accompanied
is
byte
the
if
sly
simultaneou
set
is
END interrupt
a

true

EOI

line.

DATA IN REGISTER

NOT USED

DI07
DI08

DIOS
DI06

DIO3
DI04

Do
Di02

‘
Cs-3130

Figure

3-8

1IEEE Data Register

(Read Only)

3.2.5

Control and Status Register (CSR)

The control and status register enables interrupt logic and also

controls data

transfers,

status

conditions,

and

error

conditions.

It can be read and written at the assigned address.

The

CSR

both byte and word loadable.

Figure 3-9 shows the CSR bit format, while Table 3-11 defines the

bits

for the CSR.

|R/

wo | wo | wo

NOT USED

NXM

comp

END

W | R

|R/WIR/W RM R/W RM R/W]R/W

INT

DMA

ENB

DIR

INT

MuUX

DMA
ENB

SYS

CONT
cs-N

Status Register

(IEUll-A only)

wowowoR’WR/WR’WR/WW

R/WIR/WIR/W|R/WI|R/W{R/W]R/W

Figure

3-9A

| R/

NXM

Control

and

COMP

END

INT

DMA

ENB

DIR

MUX

OO0

DMA

ENSB
SYS

CONT
CS-3481

Figure

3-9B

Control

and

Status

(IEQll-A Only)

Table 3-11

Control and Status Register Bit Format

Name

(Mnemonic)

Bit
15

dyte

Count

overflow
(BC OF)

Function

Cleared By

(When Set)

Indicates that the specified
number
of device dependent
data bytes have been received or transmitted by the
controller.
The

MC,

‘or loading
with "@"*

setting of this bit

causes

the

become
ates

INIT,

ENB

false,

the

DMA bit

DMA data

interrupt

which termintransfer.

is also gene-

rated, if the INT ENB bit
(CSR Bit<6>) is set.

Non-existent
Memory

(NXM)

Indicates that the controller is performing a DMA

INIT, MC,
or loading

transfer and the memory address/specified in the BAR
register is non-existent
(does

not

within

The

respond

setting

causes

MSYN

microseconds).

the

of this
ENB

bit

DMA bit

become false.
An interrupt
is also generated, if the

INT ENB bit

(CSR Bit <6>)

set.

Comparison

Indicates

that

End

number

successive

END)

(COMP

characters has

predefined

been

by the MCR register.

EOS

detected

activate this comparison
logic, the ENB Match bit

(MCR Bit<15>)

The

must be

set.

setting of this bit

causes the DMA ENB bit (CSR
Bit<@>) to become false.
An
interrupt is also generated,

<12:09>

the

INT

Bit<6>)

set.

<21:18>

used

ENB bit

IEQll1-A only.

for

(CSR

the

INIT,

MC,

with

"g*

Table 3-11

Control

and Status Register Bit Format

(Cont)

NOTE

The extended bus address bits can be
loaded only by word instructions because
the upper four extended bus address bits
18 to 21, which are resident in the high
byte of the CSR, cannot be loaded bytewise.
Extended address bits are not
used

with

the

IEUll-A.

Name

Bit
8

(Mnemonic)
Master

Clear

(MC)

Function
Loading

with

(When
"1"

Set)

Cleared

generates

reset

pulse with the same
effect for bits of the CSR
and MCR registers as the

INIT signal.
Therefore,
this bit allows selective

resetting of

the

IEUll-A

without affecting
the UNIBUS.

Interrupt
(INT)

devices

Represents the logical
condition of the INT #
1l bit (IIR Bits<7:6>).
The

setting

causes

the

this

DMA

ENB

NOR
+ INT

(ACR) or
reading the

bit
bit

(CSR

Bit<@>) to become false.
An
interrupt is also generated,
if the INT ENB bit (CSR Bit
<6>)

Interrupt

Enables

Enable

COMP

(INT

ENB)

INIT, software reset
command

IIR

set.

the

bits

END, or
interrupt

OF,

NXM,

INT to generate
request to the

CPU.

INIT,

signal

The

assertion

DONE

signal

generated
after each

quence.

of the INT
is automatically
by the hardware
interrupt

Therefore,

seit has

to be set again to allow
further interrupts.

3-27

assertion
of INT DONE

Table 3-11 Control and Status Register Bit Format (Cont)

Bit
<5:4>

(Mnemonic)

Bus Address
<17:16>

(BA <17:16>)

Cleared By

FPunction (When Set)

Name

.. Inconjunction with. BAR
bits <5:4> specify the

starting memory address of a
DMA transfer.

These bits

are incremented when BAR
overflows.

Multiplex

(MUX)

Identifies which set of reg-

isters is active.

When this

bit is clear, it indicates

that register set 1 is being

used, whereas register set

is selected when it is set.

Since this bit can be acti-

vated by both CSRs, CSR 1

must set the MUX bit to se-

lect register set 2.

Clear-

select registr set 1.

ing this bit by CSR 2 will

changing the MUX bit, the

CSR. which is presently ad-

dressed,

is activated.

Both CSRs can read the state

of the MUX bit.

DMA Direction
(DMA DIR)

Defines the data path during
DMA transfers.

It causes

INIT, MC

the IEUll A to perform a

DATI cycle
to

(data from memory

IDR).

The IEUll A performs a DATOB
cycle (data from IDR to memory) when this bit is cleared.

System Con-

Gives the IEUll A the capa-

CONT)

troller.

trol

(SYS

bilities of a system conThat is.

the

IEUl1-A is able to send the
IFC and

REN message by means

of the IEC/IEEE bus, otherwise

the

appropriate

bus

transceivers are not en-

abled.

INIT

Table 3-11

Bit
g

Control and Status Register Bit Pormat

Name

(Mnemonic)

DMA Enable
(DMA ENB)

Function (When Set)
Enables a DMA block transfer

determined by the bus adin the BAR and the
dress.
block length in the BCR.
Clearing this bit terminates

the

DMA transfer,

because this disables
further

DMA requests.

Setting this bit again is
only possible after canceling all the conditions used
to reset the DMA ENB bit
(CSR Bit<@>).

(Cont)

Cleared By
INIT, MC,

BC OF, NXM,
COMP END,
or INIT

3.2.6

Bus Address Register (BAR)

The Bus Address Register points to the current data byte that is
The BAR can be read
to be accessed during a DMA block transfer.
It is byte and word
address.
UNIBUS
assigned
the
at
and written
DMA transfer of
each
after
+1
by
d
incremente
is
loadable. The BAR
a data byte to or from memory.

the DMA BENB bit (CSR Bit<@>).
The BAR is leoaded prior te- setting
Along with BA <17:16> (CSR Bits<5:4>), the BAR contents specifies
Refer to Figure
the starting memory address of a DMA transfer.
3-19 for the bit

format of the BAR.

The BAR can only be cleared by writing "@gs"

to it.

RW |RW]RW] R W] RWIRWIRWIR/W]R/W]RWIR/W|R/W|R/W|R/W| R/W|R/W

BA
15

BA
13

BA
1"

BA
09

BA
07

BA
05

BA
o3

BA
o1
cS-3132

Figure 3-16

Bus Address Register

3.2.7
Byte Count Register
The byte count register (BCR) defines the length of the data block
that is to be transferred in the DMA mode.
Refer to Figure 3-11
for the bit format.
The BAR can be read and written at the assigned UNIBUS address.
It is both byte and word loadable.

O0O4

OO0

88—

NEEERERE

88—

R/WIR/W|IR/W|R/W|R/W|R/W|R/W|R/WIR/W|R/WIR/W|R/W|R/W|R/W}]R/W]R/W

01
133

Figure

3-11

Byte

Count Register

The BCR must be loaded initially by the 2's complement of the num-

ber of transfers to.be made before setting the DMA ENB bit

(CSR

The register's contents is incremented by +1 every time

Bit<#>).

When the register's contents equal
a DMA cycle is performed.
Howzero, the BC OF bit is set to terminate the DMA transfer.
the
resetting
ever, the DMA transfer can be terminated sooner by
rea
contains
BCR
the
case,
In this
DMA ENB bit (CSR Bit<@é>).
mainder that can be- used to calculate the real block length that
has been

transferred.

The BCR can only be cleared by writing "@sTM to it.
'
Match Character Register
3.2.8
the possibility to
provides
(MCR)
Register
The Match Character
detect EOS characters while the IEUll-A is in the Listener Active
The
State (LACS) and data is being transferred by means of a DMA.
MCR can be read and written at the assigned UNIBUS address.
It is
both byte and word

loadable.

Figure

the

defines

3-12

shows

the bits.

R/W

bit

format

for

the

MCR,

while

Table

R/W| R/W|]R/W| R/W|R/W]R/W]R/W| R/W|R/W | R/W | R/W| R/W| R/W [R/W

BEEREREREEERERE

NOT

CNT

EOS

USED

ENB
MATCH

CNT
32

CNT
8

CNT
2

EOS
8

EOS
6

EOS
4

EOS
1

EOS
2
CS-314

Figure

3-12

Match Character Register

3-12

Table 3-12

Match Character Register Bit Descriptions

Name

Enables comparison logic to

Enable Match

Cleared By

Punction (When Set)

(Mnemonic)

Bit

assert the COMP END bit (CSR

Detection

Bit<l3>) if a predefined
number of consecutive characters equal to the low
order byte of this
has been detected.

The desired number of EOS
characters may be defined by
loading the MCR bits <13:88>
with the appropriate value.

<13:88> Counter
32,

16,

INIT or MC

Can be loaded with a binary

(CNT

number

from 1 to 63 to de-

fine how many consecutive

EOS characters must be de-

tected by the Listener be-

fore the COMP END bit (CSR
Bit <13>) is asserted.
Loading with zero is not
allowed.

<P7:88> End of String
(EOS

Can be loaded with a charac-

<8:8>)

device
Talker
able.

3.3
This

that is currently the
and is freely select-

STATE DIAGRAM IMPLEMENTATION
section contains the state diagrams

Where

INIT or MC

ter equal to EOS character
used on the IEC/IEEE bus to
detect end of string.
The
EOS character depends on the

for

the

TMS

9914A.

those
ided,

equivalent, the names of TMS 9914A states are the same as
of IEEE-488.
In some cases, IEEE-488 states have been divfor example, ACDS of the IEEE-488 has been split into ACDS1

sages

and

State

diagrams

and

ACDS2.

retained.

The

upper

convention

case

with

for

lower

remote

case

messages

message

characters

and

outputs

for

are

The

outputs

shown

are

the

values

3-32

presented

mes-

states

supplemented

tables.
T is used to represent a true output and F a
put.
Parentheses denote a
passive output;
otherwise,

tive.

local

interface

with

false outit
is
ac-

the

bus

and

assume the use of the SN75160 and SN75161 or SN75162 transceivers

The symbol (NUL) associated with
or their logical equivalents.
DIO(1-8) indicates that each of these lines is sent passive false
by the

function in question.

NOTE

state

into

arrow

with

its origin represents a

state

transition from

every other state on the diagram.

Note,

however, that this does not imply that
all exit conditions from the destination

If such an entry
state are overridden.
condition is true and, simultaneously,
an exit condition is true, then this represents an illegal situation and should
Such situations will not
be avoided.
occur in normal operation of the device.

No maximum timings are discussed.
The TMS 9914A register, with
its recommended transceivers, meets all IEEE-488 maximum timing
If the TMS 9914A register is used with other transrequirements.
ceivers, then it must be ensured that these requirements are still
met.

3.3.1

Auxiliary Commands

There are two basic types of commands implemented in the auxiliary

command

immediate execute and clear/set.

The clear/set commands are used to enable and disable the various
features of the TMS 9914A register.
The particular feature is selected by the code on f#-f4 and it is set or cleared according to
the value

the

the mnemonic

state.

The

immediate

duration

bit.

execute

strobe

has been written

For

clear/set

to.

the

auxiliary

signal

This

purposes

commands

remain

command

after

simply

the

auxiliary

represented

state

represents

the

diagrams,

its

active

command

form

current

for

the

state

diagram in Figure 3-13.
Note that writes to the auxiliary command
register must be spaced by at least five clock cycles.
For the
purposes of the remaining state diagrams,
the
immediate execute
commands are represented as the mnemonic gated by the auxiliary
command

strobe

state

(AXSS).

The clear/set bit of the
several
of the
immediate
uses it to differentiate

auxiliary command
execute commands,
between valid and

addresses

when

releasing

DAC

holdoff

secondary

The
'lon'
and
‘'ton'
auxiliary
commands
are
immediate execute, as described in Section 3.3.4.

also

address.

considered

CS-3138

Figure

3-13

TMS

The

'fget'

and

'rtl'

and

clear/set.

They

9914A Auxiliary Command

auxiliary
may

commands

cleared

State

are

both

set

Diagram

immediate execute

the

normal

way,

but

if they are cleared when they are already in the false state, they
will pulse true for the duration of AXSS.
1In the following state
diagrams,
form.

however,

Table

Mnemonics
waux

3-13

are

write

simply

Auxiliary Command

Messages

command

tc(O)

these

auxiliary

included

= clock cycle time

clear/set

States
auxiliary
idle

AXWS

their

State Diagram Mnemonics

Mnemonics
AXIS

command

state

- auxiliary command write
state

AXSS

auxiliary

command

strobe

state

3.3.2
Acceptor Handshake
The TMS 9914A acceptor handshake

is shown in Figure 3-14.
The
main variation from IEEE-488 to note is that the device remains in
AIDS while the controller function is in CACS.
The TMS 9914A
register, therefore, does not monitor the commands that it sends
over the bus, and this places
are outlined in Section 3.7.

some

3-34

restrictions

the

user

which

CWAS.DAV.

(ATN+ANHS.AEHS.

vdin.rhdf.AXSS)
swrstHATN.CIDS.CADS)

(ATN.LADS.LACS)
(ANHS+AEHS+

rdin-rhdt.

dacr.AXSS

AXSS).ATN

DAV

swrst.SAHF.ACDS1

(rhdt AXSS)+shdw-Hrdin.hdfa)

swrst

‘!IE’

SWrSLATN.SCDS1.3haw

ANT+ADHS
ATN.5t.(0)+
‘l===,
ATN.t:(0)

rhdt.AXSS

swrst

‘!Ig}

—

swrst.ATN.ACDS 1.hdfe.EO!
CS-3138

Figure

The

3-14

TMS

data

9914A Acceptor

state

IEEE-488

Handshake

State

(ACDS)

divided

Diagram

into

two

states.
The first (ACDSl) is used to strobe data into the Data 1In
Register, or to sequence the decoding of commands from the bus.
All interrupts generated by the acceptor handshake (GET, MA, MAC,
DCAS, APT, UCG,
BI, and END)
are generated by this state.
The
second
(ACDS2)
is used as a holding state where the device will

remain

Certain
rupts

cerned
the

of
the

event

commands will

are

unmasked,

are

state

the

GET,

MA,

diagram

above

duration

cause

interrupts

DAC holdoff

in ACDS]1

will

the

signal

SAHF

set

unmasked.

event

stored

causing

This

which

This

con-

represented

becomes

inter-

interrupts

the

APT.

and,
The

UCG,

ACDS1.

and

occur.

DCAS,

interrupts
of

DAC holdoff.

true

when

one

persists

for

ADHS

to.

become active, which inhibits the transition from ACDS2 to AWNS.
ADHS is cleared by 'dacr'.
Table 3-27 shows the response of the
TMS 9914A register to the various bus commands.

3-35

Two additional state diagrams are included to record the type of
ANHS indicates that a
data received in ACDS1 when ATN is false.
holdoff should be
RFD
an
that
and
d
receive
been
data byte has
caused before the next data byte is accepted. The holdoff may be
released by reading the Data In Register unless the 'hdfa' feature
is enabled in which case 'rhdf' must be used. AEHS shows that the
last data byte was accepted with the EOI message true and the
‘hdfe' feature set. This will cause an RFD holdoff which can only
be released by ‘rhdf'.

Table 3-14

Mnemonics

Acceptor Handshake Mnemonics

States

Mnemonics

Messages

swrst = software reset

AIDS

= acceptor idle state

dacr

= DAC release

ANRS

= acceptor not ready state

rhdf

= release RFD holdoff

ACRS

= acceptor ready state

shdw

= shadow handshake

ACDS1 = accept data state 1

rdin

= read data in register

ACDS2 = accept data state 2

hdfe

= enable RFD holdoff after

AWNS

= acceptor wait for new

hdfa

= enable RFD holdoff on

ADHS

= accept data holdoff

ATN

= attention

ANHS

= acceptor not ready

- DAV

= data valid

AEHS

= acceptor not ready

EOI

= end or

CWAS

= controller wait for

RFD

= ready

AXSS

= auxiliary command strobe

END messages received

all data

identify state

for data

cycle state
state

holdoff

state

holdoff after

ANRS state
function)

state

'END'

(controller

(auxiliary command

DAC

= data accepted

LADS

= listener addressed state

SAHF

= set accept data
holdoff state

LACS

= listener active state
(listener function)

(listener

function)

Acceptor Handshake Mnemonics (Cont)

Table 3-14

tc(fl) - clock cycle time

Remote

RFD

CIDS

- controller idle state

CADS

- controller addressed

(controller function)

state (controller
function)

Acceptor Handshake Message Outputs

Table 3-15

State

States

Mnemonics

Messages

Mnemonics

Messages

DAC

AIDS

(T)

ANRS

ACRS

(T)

ACDS1

Sent

Other Actions

ATN False: - data entered into Data

In Register
- BI interrupt generated

ATN True:

end interrupt generated
if EOI is true

- commands decoded
- command
rupts

inter-

set

- sahf set if command
requires a DAC holdoff
- TR pin set true if GET
message is received
- pts feature cleared
after UNC interrupt set

ACDS2

- pin set
command
ACDS1

AWNS
3.3.3

true

if GET

was

received

(T)

Source Handshake

The TMS 9914A source handshake state diagram is shown in Figure
These
IEEE-488 states SIWS and SWNS have been removed.
3-15.
record the false then true transition of 'nba' (new byte available) as the old data byte is removed and a new data byte is made
ready.

Instead,

the

TMS

9914A

3-37

uses

separate

state

(SHFS) to record the availability of a data byte in the Data Out
Register. This state is exited when a byte is written to the Data
out Register which enables the transition from SGNS to SDYS and
The SHFS is re-entered
the subsequent transmission of the byte.
is interrupted
handshake
the
as the byte is sent in STRS, but if
been sent is
not
has
byte
the
before this, then the fact that
I1f,
active.
becomes
again
recorded until the source handshake
ded,
disregar
be
to
¥s
ter
Regis
Out
however, the byte in the bata
then 'nbaf' may be used to return the device to SHFS.

The status byte in the Serial Poll Register is continually avail-

The transition from SGNS to SDYS is not dependent on SHFS
able.
By separduring a serial poll; that is, while SPAS is active.
Out ReData
the
in
byte
a
of
y
ately recording the availabilit
poll
serial
a
for
interrupted
be
may
data
sending
talker
a
gister,

without risk of a byte being lost.

The additional state SERS is included to detect an error condition
This will be entered when the source handshake tries
on the bus.
to send a byte but finds both the NRFD and NDAC lines false at the
This condition will normally indicate for a controller
same time.
" that there are no devices powered up on the bus, or for a talker
that there are no devices addressed to listen on the bus.

The state VSTS will be entered after the first data byte of a
talker has been sent if the 'vstdl' feature is enabled.
This
)) for all subsequent
enables a very short bus settling time (4t

bytes until ATN next becomes true.
not

use

the

controller.

short

bus

settling

The Efig 9914A register will

time

when

active

SWIsL{TACS+SPAS+CAS)

SHFS.wdot+SPAS

SIDS

(ATN.CACSHHATN.(TACS+
SPAS))+swrst

RFD.DAC.
12t(O)+std

DAC

41.(0)

(12tc(0+

Swist.wdot

swrst

8t (O)+VSTS.

RFD.DAC.

std 1.8t(01+

—

nbafAXSS+STRS.SPAS

ATN.vstd1.STRS

cs-3137

Figure 3-15

TMS 9914A Source Handshake State Diagram

Table 3-16

Mnemonics

Source Handshake Mnemonics

Messages

Mnemonics

States

swrst

software reset

SIDS

source idle state

nbaf

new byte

available

SGNS

source generate

wdot

write to

the

SDYS

source delay state

SERS

source

false

out

data

state

stdl

enable short
setting time

vstdl

enable very short

STRS

source transfer

ATN

attention

SHFS

source holdoff state

RFD

ready for data

VSTS

very short bus settling

bus

setting

bus

time

3-39

error

state

States

Mnemonics

Messages

Mnemonics

(Cont)

Source Handshake Mnemonics

Table 3-16

DAC

data accepted

TACS

talker active state

tc(fl)

clock cycle time

CACS

controller active state

SPAS

serial poll active state

AXSS

auxiliary command strobe
state (auxiliary command

(talker function)

(controller function)

(talker function)

Table 3-17

Remote

Source Handshake Message Outputs

Messages

State

DAV

SIDS

(F)

SDYS

SGNS

Sent

Other Actions

BO interrupt and ACCRQ set true if

SERS

STRS

SHFS

ERR

false and

interrupt

SPAS

not

true

set true

3.3.4
Talker and Listener Functions
Figures 3-16 and 3-17 show the TMS 9914A listener and talker state
diagrams, which serve the purpose of the listener and talker or
extended

listener

pending

The

9914A

chip

TMS
and

the

these

and

state

extended

talker

functions

the

APT

interrupt

does

not

recognize

passed

through

cation.
Secondary addressing
interrupt.
A secondary address

mask

secondary
the

is enabled
will cause

IEEE-488,

de-

addresses

on-

bit.

host

MPU

for

verifi-

by unmasking the
this interrupt if

APT
the

last primary command received was a primary address of the device;
that is, it is in TPAS or LPAS.
A DAC holdoff will also occur.
The host MPU must respond to the interrupt by reading the secondary from the Command Pass Through Register and identifying it as
being valid or invalid.
The holdoff may then be released with a
‘dacr' auxiliary command, the sense of the 'cs' bit being used to
indicate a valid
(cs=1) or invalid
(cs=0)
secondary.
If a valid
secondary address is indicated,
then the TMS
enter TADS or LADS depending on whether it is

3-48

9914A register will
in TPAS or LPAS.

The 'lon' and 'ton' auxiliary commands together with the clear/set
bit (cs) have a direct influence on the appropriate state diagrams.
Therefore, although they appear as ordinary clear/set auxiliary commands, they can be effectively cleared by other bus
For example, if a TMS 9914A register addresses itself as
events.
a listener by means of the 'lon' command, it may be returned to
LIDS by a UNL command from the bus at a later time.

The 'lon' and ‘ton' auxiliary commands are used to implement two
First, talk only and listen only are used
features of IEEE-488.
in situations where there is no active controller on the bus.

Note that the 'lon'

and 'ton' commands are linked with these fea-

by CAS as are

and

tures to indicate to the user that these commands are not enabled
'ltn'

'lun'

of IEEE-488.

Second, the 'lon' and 'ton' auxiliary commands are used by an active controller to address itself.
IEEE-488 provides for a con-

troller
'lun'

address

message,

talker.

itself to

but

there

Therefore,

through

'ton',

similarly,

when

must

send

listen by means of

corresponding

controller

addresses

its

talk

address

itself by writing

'ton'

false.

the

'ltn'

message

itself

over

the

if it sends another talk address over the bus,

must unaddress

for

bus

and

the

talk

and,

then

When the TMS 9914A register enters SPAS, the contents of the
serial poll register are sampled and presented on DIO(8-1).
These
will remain unchanged until SPAS is exited.
The source handshake
will, however, send
ler will accept it.

this

status byte as many times

the control-

The internal IFC signal of the TMS 9914A register (IFCIN) is suppressed when the device itself is sending IFC in order to simplify

implementation

Therefore,

cluded

the

with

send

IFCIN

the

their idle
interface.

states

A separate
message of

diagram is
IEEE-488.

followed

EOI

controller

interface clear

and

return

allow

the

function
(sic)

talker

system

(see

and

into

the

command

listener

controller

included to control the
If the 'feoi' auxiliary

byte

Section

auxiliary

Data

Out

3.7.3).
is

in-

functions

clear

sending
command

of
is

its

own

the END
written

the

TMS

9914A register will enter ERAS, and the EOI line will be asserted
as 'DIO(8-1)' and will begin to change.
The function will enter
ENAS as soon as the source handshake begins to send this byte, and
If

will

'feoi'

device

released

is desired

may

ERAS.

when

send

written

the

EOI

Data

true

before

the

Out

with

Data

the

1is

next byte

Out

loaded.

well,

then

returns

the

swrst+dal+sicHFCINSG

lon.cs.AXSS

LAF

TAFHUNLACDS1

ATN

LAF = dal.iFCIN.
sic.(MLA.aptmk.

ACDS1+LPAS.aptmk.

dacr.cs. AXSS+ion.
cs.AXSS)

MLAACDST

swrst

PCG.MLAACDS1
Cs-3138

Figure 3-16

TMS 9914A Listener State Diagram

::':'d'fi;_;.fi

TAF

ATN.SPMS

(TPAS.aptmk.dacr.

ATN

cs.AXISS)+LAF+

IFCiN

OTA.ACDS1

ATN

ATN.SPMS

TAF= dat.sic.IFCIN.(MTA.APTMK.ACDS 1+
TPAS.aptmk.dacr.cs. AXSS+ton.cs.
AXSS)
MTA.ACDS1

PCG.MTA.ACDS1
IFCIN.SPE.ACDS1

IFCIN<

feoi.AXSS

nbaf AXSS
.

swest

SPD+CIDS+CADS

SDYS.SPMS
wdot

feoi. AXSS

SDYS.SPMS
CS-3139

Figure 3-17

TMS 9914A Talker State Diagram

Talker and Listener Mnemonics

Table 3-18

States

Mnemonics

Messages

Mnemonics

swrst = software reset

LIDS

= listener idle state

dal

= disable listener

LADS

= listener addressed state

dat

= disable talker

LACS

= listener active state

sic

= send interface clear

LPIS

= listener primary idle

lon

= listen only

LPAS

ton

= talk only

TIDS

= clear/set bit of the

TADS

dacr

= release 'DAC'

state

= listener primary ad-

auxiliary command
register

holdoff

aptmk = address pass through

= talker idle state
.

= talker addressed state

TACS

= talker active state

SPAS

= serial poll active

interrupt mask

nbaf

state

dressed

state

= new byte available

idle state

SPIS

= serial poll

SPMS

serial

poll mode

TPIS

talker

primary

false

feoi

wdot

= write to
Register

ATN

force

'EOI’
the

Data

Out

state

idle

state

= attention

TPAS

talker

primary addressed

state

IFCIN =

internal
message
signal,
'sic')

EOI

end

PCG

primary

interface clear

ENIS

= end

idle

state

ENRS

end

ready

ERAS

end

ready and

(a debounced
suppressed by

identify
command

group

state

active

state

MLA

= my

listen

MTA

= my

talk

address

active

state

ENAS

end

SDYS

source delay
(source

3-44

state

handshake)

Table 3-18

Mnemonics

OTA

Talker and Listener Mnemonics

Messages

other

talk

(Cont)

Mnemonics

address

CIDS

States

= controller

idle

(controller

SPE

serial

poll

enable

CADS

= controller
state

state

function)

addressed

(controller

function)

SPD

= serial

UNL

poll

disable

unlisten

ACDS1

= accept data state 1
(acceptor handshake)

AXSS

= auxiliary

command

strobe

state (auxiliary command
register)
PCG

= primary command group

Table

State

3-19

Talker

Function Message Outputs

Remote
RQS

Qualifier

Messages

Sent
EOI

Other Actions
DIO(8-1)

TIDS

(F)

(NUL)

TADS

(F)

(NUL)

TACS

ENIS,B&RS

(F)

DATA OUT REG

TACS

ENAS.ERAS

(F)

DATA

SPAS

NPRS . SRQS

SERIAL

POLL

REG

SPAS

APRS1.APRS2

SERIAL

POLL

REG

3.4

SERVICE REQUEST

Figure

3-18

shows

quest

function.

OUT

REG

FUNCTION

the

state

The

device

diagram
has

for

two

the

TMS

means

9914A

service

re-

implementing

the

request service (rsv)
local message of IEEE-488:
the
first,
‘rsvl',
is bit 7 of the Serial Poll Register; the second is the
auxiliary command 'rsv2'.
These are simply ORed together to provide an input to the service request function and,
in any particular application, only one would normally
being left in its hardware reset state.

3-45

used,

the

other

swrat.(rsv1+rsv2).5PAS

(revi+rsv2).SPAS

Cs-3140

Figure

The affirmative
into two states
son:

Request

State

Diagram

the case where a device has requested service, has
polled, and then wishes to request service again.
The
must clear the 'rsv' message and then set it true again.

serial

host

MPU

Suppose

this

occurrence

temporary

implemented
SRQ

Service

poll
response state
(APRS)
of IEEE-488
is split
on the TMS 9914A register for the following rea-

.consider

been

and

3-18

SPAS.

exactly

will

not

false

1If

the

per

condition

service

IEEE-488,

asserted

second

happens

function

not

will

time.

part

action

ponse

the

sing
is

the

service

the

requested

addressed

controller.

routine

request

for

instrument

printing
to

talk

executed

action

the

would

For

example,

which

some

data

could

had

then

send

its

'rsv'

data

over

the

been

recognized,
'rsv'

may

SPAS,

which

some

prear-

normally

controller

service.

device,

and

This

one

has

Therefore,

only be cleared when the device is known not to be
can only happen if it is cleared as a consequence

ranged

within

request

send

service

for

cleared

bus.

reswas

proces-

when

For many applications,
the fact that the device has been
serial
polled after requesting service is considered
sufficient response
from the controller.
The 'rsv'
1local message, therefore, simply
becomes a request for the controller to read
its serial
poll
status

byte.

assert

'rsv'

then

desirable

any

time

after

serial

the

able

poll

clear

and

re-

byte

has

command

status

been polled and the SPAS interrupt set.
The TMS 9914A register is
able to record a false transition of 'rsvl'
or
'rsv2'
by moving
from APRS1 to APRS2 even if the device is in SPAS.
This makes the
above approach to serial polling possib
le.

further

support

automatically
ensuring
occur.

that
If

this

cleared
'rsv2'

this

were

approach,

when
is
not

the

'rsv2'

the

auxiliary

serial pPoll status
cleared before a
second
the

case,

the

same

byte

is polled,
serial poll
can

status

byte

might

polled twice by the controller with the RQS
bit true,
which
indicate that two reasons for requiring servic
e have arisen.

3-46

may

The TMS 9914A register will only send one serial poll status byte
during each active period of SPAS.
However, it will send this
status byte as many times as the controller is prepared to accept
it.
Therefore, the controller should only read the status byte

once per serial poll; otherwise, each time a status byte
with
and

the

RQS message

'rsv2'

true,

will be cleared.

Table 3-28

Mnemonics

software

rsvl

rsv2

SPAS

interrupt

Mnemonics

reset

= negative

request service 1
(bit 7 of serial
poll register)

SRQS

request service 2
(auxiliary command
register)

APRS]1

= affirmative poll

service

Remote

3-21

Messages

State

SRQ

NPRS

(F)

SRQS

APRS1

(F)

poll

response

request

= serial

poll

state

APRS2 = affirmative poll

(talker

Table

is sent

generated

States

NPRS

SPAS

APRS?2

will

Service Request Mnemonics

Messages

swrst =

the

state

state 2

active

state

function)

Service Request Message

Outputs

Sent

Other

rsv2

Actions

cleared

- SPAS
when

STRS

as APRS1

same

3-47

SPAS and STRS

interrupt set if
is exited

SPAS

3.5

REMOTE/LOCAL FUNCTION

The TMS 9914A remote local state diagram is shown in Figure 3-19.
It differs little from that of IEEE-488.

The complete listener function (LAF) is used to effect the transiThis means that if
tion from LOCS to REMS or from LWLS to RWLS.
the APT interrupt is masked, the device will enter one of the re-

mote states
addressing

in response to its listen address, but if secondary
enabled, this will not happen until ‘dacr' is writ-

1In
ten with 'cs' true in response to a valid secondary address.
if
occur
will
states
remote
the
of
one
to
transition
the
addition,
'‘lon'

is used to address the device to listen.

RENIN.rt1.LAF

GTLLADS.ACDS1+

n1.(LLO.ACDSI)

GTLLADS.ACDS
Cs-JV41

Figure 3-19
Table

Mnemonics

TMS 9914A Remote Local State Diagram
3-22

Remote/Local

Messages

swrst

software

rtl

return

RENIN

internal remote enable
message (debounced)

GTL

= go

LLO

local

Mnemonics

States

LOCS

local

REMS

remote

state

RWLS

remote

with

local

LWLS

local

lockout

LADS

listener

reset

Mnemonics

local

state

with

(listener
ACDS]1

lockout

state

lockout

state

addressed

state

function)

accept data state 1
(acceptor handshake)

PARALLEL POLL FUNCTION
3.6
The parallel poll function of the TMS 9914A register only nominally supports logically-configured parallel poll.
With a suitable

software package, remotely-configured parallel poll may also
easily implemented.
The state diagram is shown in Figure 3-24.

When the EOI and ATN lines become true simultaneously (the Identify message), the contents of the Parallel Poll Register are
output to DIO(8-1).
1If parallel poll is to be used in a particular bus environment, then the Pull-Up Enable (PE) input of the
SN75166 must be held low so that the DIO(8-1) are driven by open
collector buffers.
Parallel Poll,
occurring when the Parallel
Poll Register is in the hardware reset condition of all zeros,
will result in none of DIO(8-1)
being pulled low.
This corresponds to the Parallel Poll Idle State (PPIS).
If it is desired to
participate in a parallel poll, then the bit corresponding to the
desired parallel poll response is set true.
This implements the
Parallel Poll Standby State (PPSS) and, when the Identify message
becomes true, the appropriate line DIO(8-1])
is pulled low.
This

is equivalent to the Parallel Poll Active State (PPAS).
Only
bit of the Parallel Poll Register should be set true at once.
3.6.1
Remote Configured Parallel Poll
The Parallel Poll Configure command
(PPC)

9914A

command.

unrecognized

addressed

treated

one

the

TMS

passed

through when the TMS 9914A register is in LADS.
If an instrument
is to be remotely configured for parallel poll, then the pass

through

before
mand

secondary

releasing

received

command.
Enable

the

(pts)

DAC

auxiliary

holdoff.

Pl, P2,
Section
against
'ist'),

will

should

cause

the

written

com-

also set a UNC interrupt
if it
is a secondary
secondary command will be either the Parallel Poll

The

command

and should
identified.

command

This

(PPE)
or
the Parallel
be read from the Command
1If it is the PPE command,

Poll
Pass

Disable command
(PPD)
Through Register and

then the attendant bits (S,
P3)
should be extracted and stored by the host MPU
(see
2.9.2 of IEEE-488 1978).
The S bit should then be matched
the individual status of the
instrument
(represented by
and
if they are the same,
the bit corresponding
to the

parallel
poll
response,
specified
by Pl,
P2,
P3,
should
be
true in the Parallel Poll Register.
If this is not the case,

Parallel
clear.

changes,
the

Poll

After

the

Parallel

'ist'
Poll

should

cleared

not

set
the

already

each time the individual status of the device
should again be matched against the S bit and

updated

received.

3-49

accordingly

until

PPD or

PPU

ATN.EOL.(CIDS+CADS)
swrst

swrst

ATN+EOI-+CIDS+CADS)
cs$-3142

Figure 3-28

TMS 9914A Parallel Poll State Diagram

the 'pts' feature has
If a PPD command is passed through aftershoul
d be cleared before
Register
been written, the Parallel Poll
precedes PPD is
that
d
comman
PPC
The
the DAC holdoff is released.
idual memindiv
g
natin
elimi
of
means
a
an address command; it is The parallel unconfigure comma
nd is
bers of a parallel poll.
sal
univer
gnized
unreco
treated by the TMS 9914A register as an
its
clear
d
shoul
MPU
host
command. When it is passed through, the
This
€.
holdof
DAC
the
ing
Parallel Poll Register before releas
command will clear all members of a parallel poll.

Parallel Poll Mnemonics

Table 3-23

States

Messages

swrst = software reset

PPSS

= parallel poll standby state

ATN

= attention

PPAS

= parallel poll active state

EOI

= end or identify

CIDS

= controller idle state (control-

CADS

= controller addressed state
(controller function)

Table 3-24
State

ler

function)

Parallei Poll Message Outputs

Remote Messages Sent

(DIO(8~-1)

Other Actions

PPSS

(NUL)

none

PPSS

PARALLEL POLL REG*

none

* Tf there is a true bit in the Parallel Poll Register, it must be
sent active; any false bit must be sent passive.

3.7

CONTROLLER FUNCTION
controller function of the TMS
9914A register is greatly simPlified compared with that
of IEEE-488.
It relies heavily on
software support but, with suit
able software, it enables all
subsets of the controller function
to be implemented.
With this approach the controller logic is
reduced
to a small
proportion of
the chip area which means that the
device may be economically used
in situatioms where =talker/}ist
ener ony is required.
The

Figure 3-21 shows
the controller function state
diagram.
With
suitable software, it will Perfo
rm the full controller function
as
described in the IEEE-488A 1988
supplement to the IEEE-488 1978.
It

therefore

for

DAV

ATN

the

additional

recognized

asserted.

immediate
added

includes

The

execute
record

false

'tcs'

auxiliary

local

command.

the

state

all

CSHS,

which

devices

message

The

allows

the

bus

implemented

state

CWAS

time

before
by

therefore

occurrence of this command
until the acceptor
ANRS and the device can ente
r CSHS.
The
'tca'
auxiliary command also causes
entry into CSHS although IEEE
-488a
1988 allows it to move directly
from CSBS to CSWS.
This is done
for convenience of implementati
on and results in the 'tca'
auxiliary command taking an extra
1.6 microseconds to assert ATN.

handshake

enters

The delay
IEEE-488A
CACS

between
1988

still

The

Controller
9914A

when

host

MPU

Parallel

ister.

must

cacs,

must

then

poll

than

set

CAWS

total

Parallel

and

the

greater

TMS

controller

CSWS

but

Poll

slightly
taken

specified

State

conduct

the

moving

wait

responses

the

time

'rpp'

(CPPS)

clear/set

CPWS
of

not

poll,

the

specified
form

included

TMS

auxiliary

which

Command

Pass

CSWS

the

9914A

based

command

true

sends EOI true.
before
reading
back

microseconds
means

than

moving

minimum.

Parallel

less

Through

The

the
Reg-

The 'rpp' auxiliary command
can then be cleared, EOI
will
false,
and the parallel Poll
is complete.
The host MPU will
receive a BO interrupt
as soon as the TMS 9914
A
register
reente

CACS

and

the

source

handshake

becomes

active.

3.7.1
Controller Self-Addressing
The acceptor handshake does
not operate
active.
This means that commands
being

and special precautions are
addressing devices and when

When

when
the
controller
is
sent are not monitored,
required as a consequence
of this when
pPassing control.

the controller is
unaddress
itself.

active,

talk

UNT

it uses 'ton'
or
'lon'
to address
IEEE-488
provides
for
the
controller
to
locally address
itself to listen,
but there is no correspondin
g
local message for the talk
er.
The TMS 9914a register
should
always accompany a ‘'ton' auxi
liary command with 'cs' true
with its
own

and

the

over

‘ton'

address,

TMS

the

9914aA

bus,

auxiliary

command

sends

ensure

sent

the

over

talk

that

address

false.

3-51

the

bus.

TIDS

Similarly,

another
by

device

writing

the

sic

SIC+

swrstHFCIN+

ficAXSS

CiDS

rqgec.AXSS

sre

gts.AXSS.STRS.SDYS

ATN

csS8S

CACS

8t.(0)

TMp

tca.AXSS

CWAS

tcs.AXSS

|ANRS

CAWS

CS-3143

Figure 3-21

TMS 9914A Controller State Diagram

3-52

Table

Mnemonics

3-25

Controller

Messages

swrst

software

sic

send

sre

send

rqc

request

rlc

release

Function Mnemonics

Mnemonics

reset

States

CIDS

= controller

idle

interface clear

CADS

= controller

addressed

remote

CACS

controller

active

state

control

CSBS

controller

standby

rate

control

CSHS

controller

standby hold

enable

state
state

state
=

standby

CSWS

'
tcs

take

control

synch-

CAWS

take

control

request

asynch-

CPWS

controller

wait

parallel

poll

ANRS

internal interface
clear message (a de~bounded signal which

parallel

poll

state

acceptor

not

(acceptor

IFCIN

active

state

ronously
r pp

synchronous

state

= controller

ronously
tca

controller

wait

ready

state

handshake)

SDYS

source delay
handshake)

STRS

source

state

(source

is suppressed if
'sic' is true)
ATN

attention

transfer

(source

tc(O) = clock cycle time

AXSS

= auxiliary command strobe
state

(auxiliary

controller
state

3-53

state

handshake)

wait

command

for

ANRS

rable 3-26

State ATN

Controller Punction Message Outputs

Remote Message Sent

EOI

DIO(8-1)

CIDS

(F)

(NUL)

CADS

(F)

(NUL)

CACS

CSBS

(F)

(NUL)

CWAS

(F)

(NUL)

CSHS

(F)

(NUL)

CSWS

(NUL)

CAWS

(NUL)

CPWS

(NUL)

State

SIIS*
SIIS
SIAS

DATA OUT

REG

Remote Messages Sent

Other Actions

Data Out Reg. may contain any
of the commands in Table 3-15

DIO(8-1) may be read via the

Command Pass Through Register

IFC

Other Actions

(F)
F

Internal interface clear
message IFCIN is held

Remote Messages Sent

false

REN

Other Actions

SRIS*

(F)

none

SRIS

none

SRAS

none

State

* Buffers not configured for a system controller; otherwise, buffers are configured for system controller.

Passing Control

3.7.2

As Figure 3-21 shows,.the controller. transfer state (CTRS) of
IEEE-488 is not present, and all transitions associated with the
Instead, two immediate execute
TCT command have been removed.
auxiliary commands are included. Request control (rqc) will cause
a transition from CIDS to CADS, and the release control command
(rlc) will return the function to CIDS. The TCT command is treated similarly to anm unrecognized addressed command but will cause a

UNC interrupt if the device is in TADS.

Figure 3-22 is a representation of the sequence of events involved
in passing control from one TMS 9914A based device to another.
The device passing control must initially ensure that it is not in
TADS; then it should send out the talk address of the device to
The receiving device will enter TADS, and after
receive control.
any DAC holdoff has been released, the host MPU of the device
passing control will set a BO interrupt indicating that it may
The TCT command will cause a UNC
then send the TCT command.
receiving device, and also a DAC
the
of
MPU
interrupt to the host
of the receiving device must
MPU
host
The
" holdoff will occur.
and upon identifying
Register,
Through
Pass
Command
its
examine
TCT, should write the auxiliary command ‘'rqc' to put its TMS 9914A
The receiving device may then release DAC
‘into CADS.
register
'dacr'

with

ATN

to go

auxiliary

command

causing

another

interrupt

This indicates that the 'rlc' auxilthe device passing control.
iary command may then be used by the host MPU of the device
passing control to return its TMS 9914A register to CIDS and allow

ATN,

false.

The

receiving

device

then

enters

CACS,

asserts

and its host MPU gets a BO interrupt as the source handshake

becomes active.

The passing of control is complete.

RECEIVES CONTROL

PASSES CONTROL

TMS9S14

CPU

b
ton.cs

wdot

—»

TMS914

CcPU

RECEIVES | —
MTA

CLEARS
TADS

SENDS

ENTERS

@1 ggns

wdot

—

TAG

RELEASE

DAC

ACDS

[®—

RECEIVES
o

—p

unc

—

rcpt

rac

-g—

dacr

CACS& |}—»

HOLD

SENDS
o

TCT

—

ENTERS

CADS

ENTERS

SGNS

RELEASE

DAC

ACDS

HOLD

TM1

ENTERS

ATN

cios

_p»|

ENTERS
SGNS

ATN
CS-3144

Figure

3-22

Passing Control

Between TMS

9914s

3.7.3
The

System Controller

TMS

9914A

whether

or not it is the system controller.
1Instead, this is determined
by the software and by the configuration of the buffers to the
IEEE-488 bus.
The REN and IFC outputs of the TMS 9914A register are controlled
by the auxiliary commands- ‘sre' and 'sic*.,
These should never be
used by the host MPU of a device unless it is the system con-

troller.
of

the

TMS

may

9914A

seen

from

registers

Figure

3-23,

open

drains

are

the REN and IFC outputs
internal pull-ups.

with

This means that the outputs are capable of driving the
inputs of
the buffers if the device
is a system controller.
If not,
the
buffers will drive into the REN and IFC pins and override
the
pull-ups.
Hence, no direction control is required.

The

false

transition of REN and the true
transition of
IFC are
debounced to prevent noise on these lines from causing permastate changes on the TMS 9914A register.
In
addition,
the

both
nent

internal

interface

TMS
for

9914A
this.

occurrence

If,

however,

IFC

and

enter

into

IFC

the

CADS.

CIDS,

and

device

CIDS,
As

clear

signal

(IFCIN)

held

false

the

is sending IFC.
Figure 3-21 shows the reason
device is not a system controller, then the
will
return
the
controller
function
to
CIDS.

the

IFCIN

there

will

'sic'

system

suppressed,

controller,

auxiliary
it

conflict.

3-57

command
will

when
will

not

asserts

cause
forced

back

Vee

REN®

—-—

—

———

—

——

—

———

-.-;/CC
.

Vss

IFC*

——

__.1

——

.S
DELAY
RENIN

|
e

—

sic

Vss

DELAY
L
IFCIN

*THE “REN~ AND “IFC” SIGNALS ARE AT THE PINS OF THE TMS9914A
AND ARE THEREFORE NEGATVIE LOGIC SIGNALS.
THE REMAINING SIGNALS ARE CONVENTIONAL

POSITIVE LOGIC SIGNALS.

Figure 3-23

1IFC and REN Pins

CS-3148

Table 3-27

Multiline

Interface Messages

DIO

Command

Symbol

ADDRESSED COMMAND GROUP°~
DEVICE CLEAR

GROUP

KACG
DCL

EXECUTE TRIGGER

GO TO LOCAL
LISTEN ADDRESS

GROUP

Interrupt

8 -1

Class

DAC

(1,2)

(3)

Holdoff

o XXXX
X8010108

ACT.
uc

DCAS

GET

Xg00019000

GET

YES

GTL
LAG

X0000001
XB1XXXXX

AC
AD

RLC
——

NO
-

Note

YES
14

LOCAL LOCKOUT
MY LISTEN ADDRESS

LLO
MLA

X00100801

uc
AD

NONE

XB81AAAAA

MA,MAC,RLC

MA ONLY

4,14

MY TALK ADDRESS

MTA

X1 BAAAAA

MA,MAC

MA ONLY

SECONDARY ADDRESS

MSA

X11SSSsSS

APT

YES

5,6

OTHER SECONDARY ADDRESS
OTHER TALK ADDRESS
PRIMARY COMMAND GROUP

OSA
OTA
PCG

SCG.MSA~
TAG.MTAACG+UCG+

SE
AD
—-—

APT
MAC
-

YES
NO

6,7

PARALLEL

POLL CONFIGURE

PPC

LAG+TAG
X0080101

UNC

YES

PARALLEL

POLL

PPE

X110SPPP

UNC

YES

9,18

PPD
PPU

X111DDDD
Xg018101

SE
uc

UNC
UNC

YES
YES

9,11
12

SCG
SDC

X11XXXXX
Xp000100

SE
AC

DCAS

YES

SPD
SPE

X901l1001
Xp811000

uc
ucC

NONE
NONE

TCT

Xg921001

UNC

YES

TAG

UNLISTEN

X108 XXXXX

—

UNL

X0111111

UNTALK
UNIVERSAL

MAC

UNT
ucG

X1011111
X080 1XXXX

AD
uc

NONE

ENABLE

PARALLEL POLL DISABLE
PARALLEL POLL UNCONFIGURE
SECONDARY COMMAND GROUP
SELECTED DEVICE CLEAR
SERIAL POLL DISABLE

SERIAL POLL

ENABLE

TAKE

CONTROL

TALK

ADDRESS

Classes:

GROUP

COMMAND

GROUP

universal

command

addressed
address

secondary

command

logical

zero

(high

level

NO
13

on GPIB)

logical
don't
Interrupts
command

one (low level on GPIB)
care (received message)
listed

Section 3.2)
and
low if unmasked.
The

are

received.

addressed

They

will

direct

are

set

cause

the

will

only

commands

ponding
interrupt
exception of TCT.

the

A DAC holdoff will only
interrupt is unmasked.

3-59

consequence
during

INT

ACDS1

the
(see

pulled

cause

their

device

LADS

caused

the

corresponding

corres-

with

the

ice.

4. AAAAA represents the primary address of a dev

5. SSSSS represents the secondary address of a device.

ess
are handled by means of addr
6. Secondary addresses inte
ld
rrupt). The host MPU shou
pass through (APT
with
respond by writing the 'dacr' auxiliary command
'‘cs'

false.

rugh by means of the APT intethe
2. If OSA is passed throshou
ing
writ
by
ld respond
rupt, the host MPU

'dacr' auxiliary command with ‘cs' false.

is
the TMS 9914A register and
8. PPC is not recognized anby unre
and.
comm
ess
cognized addr

therefore treated as
commands. These may be
9. PPE and PPD are secondaryMPU
using the 'pts' auxilipassed through to the host
is received, the
comm
PPC
ary command. when the should be and
written. PPE or PPD
'pts' auxiliary command
will then cause an APT interrupt.

bit, and the desired parallel
18. SPPP specifies the sense tely
configured parallel poll
poll response is a remo
(see Section 3.7.1).

h must be sent as
11. DDDD specifies don't care bits whic
seros but need not be decoded by the host MPU of the
receiving devices.

12. PPU is not recognized by the TMS 9914A register and
will cause a UNC interrupt.

by the TMS 9914A regis13. TCT is not recognized directly rupt
when the device is
ter. It will cause a UNC inter
in

TADS.

14. RLC is set if MLA or GTL causes an appropriate transition in the Remote/Local function.

GENERAL OPERATION
3.8
nce is used to describe
The following typical communication sequeterms
when both channels
al
the operation of the IEUll-A in gener
Channel 1 of the
.
cable
-81
are interconnected with atheBC@8S
channel 2 is the
and
Bus
EEE
IEC/I
on
e
IEUl1-A is one devic
els is done by the MUX bit in
other. The selection of these chann
rms the controller
the control status register. Channelel 2 1 isperfo
ned the function
assig
and listener functions, while chann is almost jdent
ical with the
of talker. The following sequence

programming example in Section 3.9.

ting the
The processor initializes both channels by asser
-up) or by setting
INIT signal on the UNIBUS (usually power
CSR registers.
MC (Master Clear) in each of the unit
3-60

The

processor

loads

channels with
interrupts.

the

interrupt

appropriate

mask

bits

registers

enable

both

all

required

The processor loads the address registers of both
with assigned device primary addresses.

channels

The SYS.
set

COMT

bit

select

channel

could

inthe-controland

channel

system

the

status

system

controller.

Either

controller.

The

auxiliary command register 1 is loaded
interface clear command
(SIC) bit to place

with the send
the interface

system in a known quiescent state.
The
interface clear
message is sent by means of the IEC/IEEE bus.
After 188
microseconds,
the IFC message may be cleared by loading

SIC

and

setting

command

Step

the

C/S

bit

zero

the

auxiliary

automatically

causes
channel
1
to
enter
the
active
state
(CACS)
and
therefore
is
the
controller-in-charge.
Consequently,
the ATN 1line
is
in

controller

the

true

The

primary

data
talk

state,.

talk address of channel 2 is loaded into the
out register of channel 1 which transmits the primary
address by means of the IEC/IEEE bus.

Step 7 causes the MA and MAC bits in the
register of channel
2 to become
true.

generated

ENB
an
to

bit

provided

the

control

ACDS holdoff is
respond
to
the

appropriate

status

mask

generated,

which

interrupt,

interrupt

status
interrupt
is

An
bits

and

are

set.

the

INT

Also,

allows

the

processor

recognize

the

cause

listener

reading the interrupt status registers, and therefore
perform the appropriate action (for example, check if the
Talker Addressed State (TADS) is in the true state) before
the holdoff is released.
The

controller-in-charge

sets

using the Listen Only command
into

18.

which has to be loaded
the

processor.

All
parameters that are
required to perform a DMA data
transfer have to be loaded
into
the control and status,
bus address, and byte count
registers by the processor.
In this example, channel 1 performs DATOB whereas channel
2

11,

auxiliary command

itself

(LON)

performs

DATI

cycles.

the Go to Standby command (GTS)
into the auxiliary
register 1 sets the ATN line
false
and
thus the
controller enters the controller standby state (CSBS).

command

3-61

12. Performing step 11 initiates a DMA data transfer (BOP)
from the CPU main memory back to memory by means of the
This process is automatic and needs no
IEC/IEEE bus.
further processor intervention.

13. In this example, the data transfer is terminated upon byte
ir both byte count registers 1 and 2, recount overflowspectively (for example, the selected byte count is the

The assertion of both these BC
same for both registers).
OF bits clears the DMA ENB bit in the control and status
To restart the DMA data transfer, a
registers 1 and 2.
new setup

3.9

required.

PROGRAMMING EXAMPLE

The following program sequence provides an example of how the

IEUI1-A (IEQlI-A) option operates.

This programming example pro-

vides a routine that enables every character that is typed to be
echoed to the screen, which means that two identical characters
appear

on the

screen.

To perform this program sequence, the program must establish the
following IEC/IEEE bus configuration:

Channel 1 is assigned

the

role of both controller and listener, while channel 2 is assigned

the role of talker (refer to Section 3.8 for details of this setup

and how to initiate the data transfer).

1In order for this program

sequence to function, a BCA8S-@#1 cable must connect both channels.
16$:

START

TSB

@$# RXCSR

;Console routine

MOV

@#RXBUF , 42000

;Get data from RX Data Buffer

MOVB
MOV

@#ICRx
@#ISR
@#ISRx
#1,@#IIRx
$2000,@4BAR

;Clear auxiliary command SWRST
;Load Interrupt Mask Register @
;Load Interrupt Mask Register 1
;Load device primary address "1*"
;Load Bus Address Register

MOV

#5,@4CSR

BPL
MOV

MOV
MOVB

CLRB
CLRB

CLRB
MOV

168
@$RXBUF,#TXBUF
$#10,@%CSR
$#200,@#ICRx

;Console routine
;Echo typed character

:Select channel 2
;Initialize channel 2

$177777,84BCR

; Load Byte Count Register

MOVB
CLRB

#200,8%ICRX
@#ICRx

;in CSR and select channel 1
;Initialize channel 1
;Clear auxiliary command SWRST

CLRB

@#ISRx

;Load

$3000,@$BAR
$#177777,8#BCR
$3,04CSR
#217,@#ICR#
$5008,R0

;Load Bus Address Register
;Load Byte Count Register
;Set DMA ENB and SYS CONT bit in CSR
;Set- IPC line true
;Delay for release of IFC line

CLRB

MOV
MOV
MOV
MOVB
MOV

@#ISR

@#IIRx

:Set DMA ENB and DMA DIR bit

;Load Interrupt Mask Register @
Interrupt Mask

;Load device primary address "@"

; (1860

3-62

microsec)

$1061,@4IDRx

MOVB
MOVB

#211,@4ICRx
$13,@#ICRx

;Clear auxiliary command SIC
;Select channel 2 as Talker
;Select channel 1 as Listener
;:Release ATN line and start

TST

€#CSR

;Wait for byte count overflow

BPL

308

MOVB
TSTB
BPL
MOV

#14,@#ICRx
@#TXCSR
40$
@43000,@3TXBUF

;Reassert ATN line
;Console routine

MOV

$4106,@4CSR

;Load MC and MUX bit

MOV

$#400,@#CSR

;Load MC bit

JMP
END

10$

:Go

MOVB
MOVB

388

463

208
#17,@‘ICRX

DEC
BNE

208

;DMA data

transfer

;Console routine

;Send character to TX Data Buffer

;and

: (clear
to

channel

in CSR

(clear channel

start

NOTE

The character ®x", which appears in the
above programming example in addition to
the register designation, refers to the
byte
of
the
appropriate
order
high
register.

3-63

CHAPTER

MAINTENANCE

4.1
INTRODUCTION
The corrective maintenance philosophy for both the IEUll1-A and
IEQll-A option is to replace the failing unit only.
This field
replaceable unit (FRU) maintenance is used to ensure that the system can be restored to operating status in minimum time.
Therefore, only units such as failing modules or defective cables are
replaced.
Diagnostics

are used to detect system failures and to verify the
functionality of a module.
A system exerciser is run to test the
system, while a repair diagnostic is used to test the function-

ality of a module.
diagnostics.
Once

the

tenance

The

PDP-11

IEUll-A/IEQll-A

option

procedures

periodic

and

LSI-11

systems

installed,

use

the

preventive

alignment/adjustment

same

main-

procedures

are

necessary.

4.2
The

REQUIRED TOOLS AND EQUIPMENT
DIGITAL Field Service tool kit

and the BC@8S-#1 test cable are
required.
The BCB8S-@1 test cable is used to interconnect the two
IEC/IEEE ports (J1 and J2) on either the M8648 module
(PDP-11 or

VAX-1l
test

systems)

cable

IEC/IEEE
connect

the

module
Bus

both

M8634

testing

instruments.
the

Instrument

ctors

allows

ends

with

must

the

test

(M8648

cable

module

the

without

IEC/IEEE

M8634)

either

(LSI-11/MICRO

module
to

the

dual

connected

any

bus

cables

I/0

bulkhead

IEC-625

systems).

using

the

This

external

that

inter-

panel,

IEEE-488

conne-

I/0

bulkhead

panel.

For instructions on how to do this, refer to Section 2.8.2 for a
PDP-11
or
VAX-11
installation,
or
Section
2.15.2
for
an
LSI-11/MICRO system installation.
4.3
The

CORRECTIVE MAINTENANCE
corrective maintenance procedure

vice

engineer

isolate

and

aid

repair

faults

option.

for

the

within

Field

the

Ser-

IEUll-A/

IEQll-A option.
The diagnostic programs are the basic tool used
to isolate failures, since the diagnostics test all six functional

areas

cable,

the

IEUll1-A/IEQll-A

external

IEC/IEEE

using
a
BC@#8S-f1
test
are necessary to
run the
troubleshooting
flowchart.
This

instruments

diagnostics.
Figure
4-1
is a
flowchart provides a logical approach
the IEUl1l1-A/IEQll-A option.

isolating

fault

within

IEU/IEQ11-A
FAULT

e
e

CONNECT BCO8S TEST CABLE
RUN IEU/IEU11-A DIAGNOSTICS

YES

ERROR?

y
SWAP IEU/IEQT1-A

MODULE

RUN DIAGNOSTICS

CONNECT BULKHEAD CONNECTORS

WITH IEC/IEEE CABLE

RUN IEU/IEQ11-A DIAGNOSTICS

y
e

YES

TRY ANOTHERSLOT

(NPG JUMPER)

e RUN DIAGNOSTICS

Emy
NO

I
e
e

ISOLATE AND

YES

ERROR?

REPLACE CABLE

RUN DIAGNOSTICS

<
e RUN SYSTEM
EXERCISER AND

POSSIBLE CUSTOMER FAULT
TEST INSTRUMENTS & SOFTWARE

OTHER DIAGNOSTICS

REPAIR/REPLACE CUSTOMER
o FAULT

ISOLATE SLOT
FAULT

REPAIR/REPLACE FRU

RUN DIAGNOSTICS

]
ERROR?

—p

‘

e
e

(»)

REPLACE FRU
RUN DIAGNOSTICS

FINISH )
cs-ne7

Figure 4-1

IEUll-A and

IEQll-A Troubleshooting

4-2

Flowchart

The structure of the IEUl1-A/IEQll-A diagnostic programs allows
the diagnostic to -test one channel
at a time.
Therefore, most of
the failures can be isolated to one of the channels.
This feature, along with the fact that the TMS 9914A integrated circuits
are plugged into sockets, facilitates troubleshooting.
For example, the two TMS 9914A integrated circuits can be swapped, and if
the failure moves to the other channel, one of the TMS 9914A integrated circuits most be defective.
With the aid of the error
printout,
located.

the

defective

integrated

circuit

should

easily

Because

of
the
IEUll-A/IEQll-A hardware
structure,
some
of
the
logic sections are used for both channels.
Therefore, the hardware structure limits the kinds of failures, but does help in
isolating the failure.
For
example,
in using
the PDP-11 diagnostic CZIEA??, if an error occurs in Test 23, Test 24 should also
be run, since both are DMA tests.
If Test 24 runs correctly,
it
can

are

not

assumed

that the DMA CONTROL and sections of the DMA
defective, because both sections are used by both

logic
chan-

nels.

4.4
The

IEUll-A/IEQll-A DIAGNOSTIC SOFTWARE
same diagnostic software is used for

LSI-11

systems.

Other

diagnostic

software

both
is

and MICRO/VAX systems.
Therefore, refer to the
in the following diagnostic software sections.
4.4.1
There

Diagnostic
are

two

Software

diagnostic

(PDP-11

programs

and
used

LSI-1l1
to

the

used

for

PDP-11
the

respective

and

VAX-1l1
section

Systems)

test

the IEUll-A/IEQll-A
option when installed in either a PDP-11 or LSI-1ll1 system.
The
diagnostic programs are the CXIEA?? DEC-X/11 System Exerciser, and
the CZIEA?? Static Diagnostic.
The DEC-X/11 System Exerciser aids in determining a failing option
within a PDP-11 system or LSI-1ll system, but it may not aid in the
option repair.
Option fault isolation requires using the CZIEA??
Static Diagnostic.
The

CZIEA??

Static

Diagnostic

verifies

the

IEUll-A/IEQll-A

option

operation according to specifications and within its actual environment.
The diagnostic program consists of 28 tests.
However,
Tests 27 and 28 are not used to test the
IEUll-A option.
These
two

tests

0-22

Refer

are

used

test

the

IEQll-A

option

conjunction

bus.

running

the diagnostic listing
for both details on loading
these diagnostics, and for a description of each test.

with

and

4.4.2
Diagnostic Software (VAX-1ll Systems)
There are two diagnostic programs
that are used
to
test the
IEUll-A option when it is installed in a VAX-ll system.
The two
diagnostics are the IEUll-A M8648 On-line Test
and
the
IEUll-A
M8648 Off-line Test.

B) is a functional level
The IEUll-A M8648 On-line Test (EVCD
an IEUll-A option. This
ises
exerc
(Level 2R) diagnostic that
option. option fault
ng
faili
a
g
minin
diagnostic aids in deter
-A M8648 Off-line Test
isolation is accomplished by using the IEUll
both to verify the IEUll-A
(EVCDC). The EVCDC diagnostic is used
option according to specifications, and for proper operation in an
actual environment.

InSupervisor.
Both diagnostics are run under the Diagnostic
enced
refer
be
can
visor
Super
ostic
structions for running the Diagn
tive type of
in the Diagnostic System User's Guide for the respec
operating
for
g
listin
stic
dlagno
the
to
Refer
VAX-11 processor.
and loading procedures.

4.4.3

Diagnostic Software (MICRO/VAX Systems)

test the IEQll-A
The MDM IEQll-A Diagnostic NAIEA? is used to
This diag.
system
VAX
MICRO/
a
in
option when it is installed
and verifies the
nostic aids in determining a faulty option
IEQll-A operation.

RENIN.rt1.LAF

GTLLADS.ACDS1+

n1.(LLO.ACDS1)
LAF

GTLLADS.ACDS
csS-314

APPENDIX A

STANDARD CONNECTIONS
ANDARD CONNECTOR

SHIELD

SRQ

ATN

NDAC

DAV

oo | DIOT

REN

D107 | DIOS

LOGIC

GND

ATN

NDAC

DAV

NRFD

DIO6

DIO8

ANDAR

IFC

REN

0103

EIO

DIO1

DiO4 | DIO2

RTN

1]|

32838392888

ATN

IEC-

SRQ

DIO2

IFC.. | NRED. | EOI

GND | GND | GND

SHD

DI04

D107 | DIO5S

DIO8

DIO6

APPENDIX B

REMOTE MESSAGE CODING

BUS SIGNAL LINES

§“‘

NAME

MESSAGE

c§
<

87 684 321
Do

=
>

ADDRESSED COMMAND GROUP | AcG | TM aC | x0 oox o

ATTENTION

00K

GROUP EXECUTE TRIGGER

X XXX

XXXX

oas | mDo | booooooo | ox

oac
pav
oc.
eND
e0s

x
X
1
o
o

X X X X
XXX X
X X X X
1XXX
X XXX

87 654 321

DATA ACCEPTED
DATA VALID
DEVICE CLEAR
END
END OF STRING

..z
Sgls

ATN | v uc | xxomxox | o

DATA BYTE

| uns | >x 0 X0
Y00
| U ks | xx o0 X0
10
| muc | x 010 100
00X
| UusST | xxoxox | ox
| MDD | EE EEE EEE
00X
87 654 321

GET | m Ac | x0 001 000

X X X X

GO TO LOCAL
IDENTIFY
INTERFACE CLEAR
USTEN ADDRESS GROUP
LOCAL LOCKOUT
MY USTEN ADDRESS

et | m ac | xo ooo oot
00
oy | vue | xxoxox | o
i*c
vuc | oo ox | o
WG | map | x0 1xx
00C
wo | muc | xo o010 001
00K
Ma | Mmap | 0w w
00X

1
1
x
x
1
1
1

X XXX

MY TALK ADDRESS

MTA | MmaD | ixorTr T

00K

X XXX

MY SECONDARY ADDRESS

msa | mse | xi11ss sss

X X X X

nuL | »m oo | 0o 000 ooo

00X

X X X X

UCG

Vv LAG v

54 321

NULL BYTE

OTHER SECONDARY ADORESS
OTHER TALK ADDRESS
PRIMARY COMMAND GROUP

PARALLEL POLL CONFIGURE
PARALLEL POLL ENABLE

54 329

| OSA | M
otTA | MmaD |
PCG

prc
pee

| M-

(OSA
= SCG A MSA)
(oTA=TAG A RTK)
(PCG=ACG

| mac | xo0 000 101
| mse | xi 108 per

321

X
YO

1
1

XXX X
1 XXX
XX1X
X XXX
XXX X
XXX
X

TAG)

X X X X
X X X X

PARALLEL POLL DISABLE

pe0 | Mmse | x1 11D D00 | o

X X X X

PARALLEL POLL RESPONSE 1

per1 | usT | xx 000 xx

000

1 X X X

SECONDARY COMMAND GRouP | scG | mse | x1 1xx roxx
00X
SELECTED DEVICE CLEAR
soc | mac | xo0 000 100
00K
SERIAL POLL DISABLE
spo | muc | x0 011 oot
00
SERIAL POLL ENABLE
st | muc | x0 011 000
00X
SERVICE REQUEST
sha | ust | xxoxox | ox
STATUS BYTE
sT8 | mst | sxssssss | o

'
1
1
1
X
0

4 321

TAKE CONTROL
TALK ADORESS GROUP

UNIVERSAL COMMAND GROUP

UNUSTEN

SYMBOLS:

TYPE

654 321

1
1
1
1
1
1
1
1
X
x
)

1 XXX
1X XX
1 X X X
1 XXX
1 XXX
1 XXX
1 XXX
X X X X
XX X1
X X X X
XXX
X

X X X X
X X X X
XXXX
X XXX
X1 XX
X X X X

TCY
TAG

ac |
oo oo
0
AD | X1 ox ox | 0

1
1

X XXX
X XXX

UNL

X0 111 111

X XXX

| UCG

X0 01X 20X

200X

X X X X

U= UNIUNE MESSAGE
M = MULTILINE MESSAGE

CLASS
-

AC = ADORESSED COMMAND
AD = ADORESS
(TALKX OF LISTEN)
DO = DEVICE DEPENDENT
MS = HANDSHAKE

UC = UNIVERSAL COMMAND
SE = SECONDARY
ST = STATUS
[- %

]

APPENDIX

HANDSHAKE

PROCESS

TIMING

SEQUENCE

C.l
GENERAL COMMENTS
Each data byte transferred by the interface system uses the handshake process to exchange
data between sowrce and acceptor.
Typically, the source is a Talker and the acceptor is a Listener.
Figure C-1
illustrates
the
handshake
process by
indicating
the
actual waveforms on the DAV, NRFD and NDAC signal lines.
The NRFD
and NDAC signals each represent composite waveforms resulting from
two or more
listeners
accepting
the
same data
byte
at
slightly
different times due to variations in the transmission path length
and different response
rates
(delays)
to accept and process
the
data byte.

Figure C-2 represents the same sequence of events
in
flowchart
form, to transfer a data byte between source and acceptor.
The

annotation

diagram

refer

numbers

the

same

the

flow

event on

chart

the

and

list of

the

timing

events.

NOTE
C-2 flow diagram is not intended to
represent the only method of implementing and acceptor handshake.

The

sequence

FIRST DATA BYTE

SECOND DATA BYTE

Fonros
s
e
%////
3
" Z///
/
%
/////4
H

NOT VALID

" ]

NDAC

m
3

~SGNS =

:i ,A

SOME ACCEPTED

e-SDYS »

VALID

NONE ACCEPTED

.
SOME ACCEPTED

' ALL Jjone
coone

STRS —— l —SGNS—= }sounce HANDSHAKE FUNCTION
— g —

ACTIVE STATE SEQUENCE

€s$-3290

Figure

C-1

Handshake

Process

Timing

Dlagram

SOURCE OPERATION

ACCEPTOR OPERATION

)
O

(e
)

¥
ser DAV HIGH

@lk SET NRED AND
NDAC LOW

NRFD AND NDAC

ERROR

SENSED

CONDITION

HIGH

C-)

PUT ON CHANGE

DATA ON
D10 LINES
C————

@@ y

DELAY FOR

LINES TO SETTLE

SET NRFD HIGH

NOW BEACCERTEDTM —
— — —po

LVES

SET NRFD LOW ]@&@

DATA BYTE

NDA"=
C SIG
N L LINE | STAYS Low
YES «¢ —
3IGNA
A ACEPTORS HAVE acc

Eprep ?‘rfim

SET DAV HIGH

SET NOAC "'G"]

Figure

C-2

Handshake

C-3

Process

Flow Diagram

C.2

LIST OF EVENTS FOR HANDSHAKE PROCESS
1.

Source initializes DAV to High (data not valid).

Acceptors initialize NRFD to Low (none are ready
for data), and set NDAC to low (none have accepted the data).

Source checks for error condition (both NRFD and
NDAC High), then sets data byte on DIO lines.

Source delays

DIO

settle

allow data

lines.

Acceptors have all indicated readiness to
first data byte; NRFD line goes high.
Source,

indicate

and

upon

sensing NRFD High,

that the

data

DIO

sets DAV

lines

accept
Low

settled

valid.

First acceptor sets NRFD Low to indicate that it

(NDAC
is no longer ready, then accepts the data.
NDAC
driving
remains Low due to other acceptors
Low.)

First acceptor sets NDAC High to indicate that it
(NDAC remains Low due to
has accepted the data.
other acceptors driving NDAC

Low.)

Last acceptor sets NDAC High to indicate that it
has accepted the data; all have now accepted and
the NDAC line goes High.

Source, having sensed that NDAC is High, sets DAV
This indicates to the acceptors that data
High.
on the DIO lines must now be considered not

1@.

valid.

11.

t4-t

12.

t7-t

Source changes data on the DIO lines.
Source

delays

allow

data

settle

DIO

lines.

13.

Acceptors,

upon sensing DAV high

Low in preparation for next

goes Low as the
14.

(at 18)

cycle.

set NDAC

NDAC

first acceptor sets the line

line
Low.

First acceptor indicates that it is ready for the
(NRFD
next data byte by setting NRFD High.
NRFD
driving
acceptors
remains Low due to other
Low.)

Last acceptor

15.

indicates that

ready

next data byte by setting NRFD High;

line goes High.

for

the

NRFD signal

Source, upon sensing NRFD High, sets DAV Low to
indicate that data on DIO lines is settled and

l6.

valid.

that

First acceptor sets NRFD Low to

indicate

First acceptor sets NDAC High to

indicate that it

Last acceptor sets NDAC High to

indicate

that it

20.

Source,

is High,

sets DAV

21.

Source removes data byte
after setting DAV high.

17.

18.

has accepted the data

19.

22.

23.

then accepts the data.

is not longer ready,

has

High

accepted

the

having

(as

data

sensed

(as in 8).

(as

in 9).

that NDAC

18).

from

DIO

Acceptors, upon sensing DAV High,
preparation for next cycle.
Note

that

all

initialized

three

states,

handshake
as

signal

lines

set NDAC

Low in

lines

and

are

their

(SENT AND RECEIVED WITH ATN=1)

COLUMN

ofofo]o

NUL

0jo}jo

SOH

OLE
GTL

DCh

SP
Lo

STX

DC2

ETX

0C3

EOT | SOC

DC4

ocL

ENa | PPC)| NAK

PPU

ACK

SYN
ETB

BEL

| GET

| TCT

CAN

SPE

SPD

sue

ESC

RMEEPSREASGEENS;TATIINTOENRFCAOCDEEB.MIUTLT1I5L6I-N7E

LF
vT

OONNIINNVVIIWNGG33NNII4d330QAA889930dd3w0o 0w
el P

-»

VIG3INDIS Y0L 3JIA30

AR
k)

Q3NOIS Y O1 3JIA30

b4|
b3 | b2| bt

uUs

NOTES:

UNL

ADDRESSED

UNIVERSAL

COMMAND

GROUP

(ACG)

(UCG)

LISTEN

TALK

GROUP

ADDRESS
GROUP

(LAG)

(TAG)

~—

MSG =

INTERFACE MESSAGE

b1 = DI101...

b7 =

D107

@ REQUIRES SECONDARY COMMAND

(@) DENSE SUBSET (COLUMN 2 THROUGH B6)

PRIMARY COMMAND GROUP (PCG)

ADDRESS

K4
DEL

UNT

—~—

SECONDARY
COMMAND
GROUP

(SCG)

D APPENDIX

€8-3202

Digital Equipment Corporation « Nashua, NH 03062