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EK-IBV11-UG-001
January 1977
79 pages
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IBV11-A LIS11/Instrument Bus Interface User's Manual
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EK-IBV11-UG
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001
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79
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S . Tf;/z% ,.. e 3 IBV11 A LSl 11/instrument bus - user’'s manual R - interface EK-IBV11-UG-001 IBV11-A LSI-11/instrument bus interface user’'s manual digital equipment corporation - maynard, massachusetts Preliminary Edition, January 1977 1st Edition, June 1977 Copyright © 1977 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice. Digital Equipment Corporation assumes no responsibility for any errors which may appear in this manual. Printed in U.S.A. This document was set on DIGITAL’s DECset-8000 computerized typesetting system. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC DECtape DECCOMM DECUS RSTS DECsystem-10 DIGITAL DECSYSTEM-20 TYPESET-8 MASSBUS PDP TYPESET-11 UNIBUS CONTENTS INTRODUCTION = .................................. LSI-11 Systems o GENERAL IBV11-A Interface Option W ek ek b b ot Q) DD it b b et CHAPTER 1 ............................. Instrument Bus SCOPE ........................ .............................. .................................... REFERENCES -------------------------------- CHAPTER 2 SPECIFICATIONS 2.1 GENERAL 2.2 IBV11-A MODULE SPECIFICATIONS ---------------------------------- 2.2.1 General Specifications 2.2.2 LSI-11 Bus Interface Signals 2.2.3 Instrument Bus Interface 224 Programming 2.3 2.3.1 -------------------- .......................... ....................... ------------------------- ............................... INSTRUMENT BUS CONTROLLER-IN-CHARGE COMMANDS General 2.3.2 Addressed Command Group (ACG) 2.3.3 234 Universal Command Group (UCG) Listener Address Group (LAG) 2.3.5 Talker Address Group (TAG) 2.3.6 Secondary Command Group (SCG) INSTALLATION 3.1 MINIMUM SYSTEM REQUIREMENTS 3.1.1 System Hardware 3.1.2 System Software 3.1.2.1 General ................... ------------------- ---------------------- CHAPTER 3 ................... ............................ .............................. ............................... 3.2 CONFIGURING THE IBV11-A MODULE 3.3 INSTALLING IN THE LSI-11 BACKPLANE 3.4 CONNECTING TO EXTERNAL EQUIPMENT CHAPTER 4 PROGRAMMING EXAMPLES 4.1 GENERAL 4.2 EXAMPLE 1 — IBV11-A TO LISTENER DEVICE 4.2.1 4.2.2 4.3 General ...... .................................. .................. ................. . . . . e e e e e e ---------------------------------- Program Operation . . . . . . . . . . . . . . o e e e e e e EXAMPLE 2 — IBV11-A TO TALKER DEVICE 4.3.1 General 43.2 Program Operation . . . . . . . L e ---------------------------- iii CONTENTS (CONT) Page CHAPTER 5 TECHNICAL DESCRIPTION 5.1 GENERAL 5.2 DEVICE REGISTERS 5.3 LSI-11 BUSINTERFACE 5.4 INSTRUMENT BUSCONTROL 5.5 INSTRUMENT BUS INTERFACE CHAPTER 6 MAINTENANCE 6.1 GENERAL . . . . . e e e . . . . . . . . . . . . o 5-1 e e 5-1 . ... 54 . . . . ... ... ... . . ... .... 5-5 et . . . . . . . . ... ... . . . . . . 6.2 IBV11-A DIAGNOSTIC SOFTWARE 6.3 DIGITAL SERVICES APPENDIX A IC DESCRIPTIONS Al DCOO3 INTERRUPT LOGIC e e e 6-1 . . . . . . . .. ... ... ...... 6-1 . . . . . . . . e e e e e et 6-1 . .. .... A-1 i e i e A-1 . .. . ... .. .. .. ... ....... A-1 . . . . .. .. ... . . . ... A2 DC004 PROTOCOL LOGIC A3 DCOO05 TRANSCEIVER LOGIC 5-1 o . . . . . . . . . . . . e . . . . . . . . . . . FIGURES Figure No. Title Page 1-1 IBV11-A Instrument Bus Interface Module 1-2 IBV11-A Instrument BusCable . . . . .. ... .. ... .... 1-2 . . . . ... ... ... ........... 1-4 I-3 Typical System — Functional Relationship 2-1 IBV11-A Instrument Bus Connector 2-2 Instrument Bus Signal Lines 2-3 IBV11-A Register and Bit Assignments 3-1 Configuring the IBV11-A Register Addresses 3-2 Configuring the IBV11-A Interrupt Vector Addresses 3-3 IBV11 Module Switch Locations 34 3-5 4-1 44 . . . . . .. .. ... ... ........... 2-6 . . . .. ... .. ... ....... . . . . . ... ... ...... 2-8 3-3 3-4 . . . . . ... .. ... ... ....... 3-5 BNI1A Instrument BusCable . . .. . ... ... .. ............ 3-6 Linear and Star Configurations . . . . . . . . . . . . . ... ... ..... 3-7 Example 1, Communicating with a Listener Device . . . . . . . . . . . .. ... . o 4-2 Example 1, Communicating with a Listener Device Program Listing 4-3 1-5 2-4 . . . . . .. ... ... Program Flowchart 4-2 . . . . .. ... ... ... ... . . . . . . .. .. ... ... ..... . . . . . . . . . . . . . . Memory Map forExample 1 e e 4-3 . . . . . . . .. ... ... ... . .. 4-4 Example 2, Communicating with a Talker Device Program Flowchart : . . . . . . . . . . . . . . . .. ... ... v 4-7 FIGURES (CONT) Figure No. 4-5 4-6 5-1 A-1 A-2 A-3 A4 A-5 A-6 A-7 A-8 Title Page Example 2, Communicating with a Talker Device Program Listing . . . . . . . . . ... Lo oo 4-8 Memory Map for Example 2 . . . . . . . . .. ... oo 4-9 IBV11-A Functional Block Diagram . . . . . ... ... e e e e e e 5-3 . . . . . . . ... ... ... ....... A-3 DC003 Simplified Logic Diagram DCO003 “A” Interrupt Section Timing Diagram . . . . . . . .. .. ... .. A-5 DCO003 “A” and “B” Interrupt Sections Timing Diagrams . . . . . . . . .. A-6 ... ...... A9 ... .. . . . . . . . . . DC004 Simplified Logic Diagram DC004 Timing Diagram . . . . . . . . . . . o oL A-15 DC004 Loading Configurations for Table A-2 . . . . . . . . .. ... ... A-15 DCO005 Simplified Logic Diagram . . . . . . . . . . .. . ... ...... A-18 oo A-19 o DCOO05 Timing Diagram . . . . . . . . . . .« . .« TABLES Table No. 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 3-1 A-1 A-2 A-3 A-4 Title Page IBV11-A Backplane Pin Utilization . . . . . . . . . .. ... ... ... .. BN11A IBV11 to Instrument Bus Cable — Connector Pinning . . . . . . .. o000 ..o . . . . . . . . . . Descriptions Bits Register IBS IBD Register Bit Descriptions . . . . . . . . . . e e e IBV11-A Interrupt Vectors . . . . .. e Addressed Command Group . . . . . . .« o .. . . . . . . .« o v Universal Command Group Listener Address Group Commands . . . . . . . Talker Address Group Commands . . . . . . . . Parallel Poll Enable/Disable Commands . . . . . My Secondary Address Commands . . . . . . . BN11A and BNO1A Connector Pin Assignments DCO003 Pin/Signal Descriptions . . . . . . « o . . . . DC004 Signal Timing vs Output Loading . . . . . . . . . DC004 Pin/Signal Descriptions . . . . . . . . . DCO0S5 Pin/Signal Descriptions 2-2 2-5 29 . ... 2-10 e 2-11 e e e e e e e e e e e 2-12 e oo e e 2-13 e e e it b . . . . . ... 2-14 . . . . e 2-15 .. 2-16 . . . . . . . ... . . ... ... 2-18 . . . . . . ... ... ... 3-8 v v it et e e A-7 . . ... ... ... ... A-11 . . .. .. A-16 . . ... A-20 PREFACE The rapid advancement in integrated circuit technology over the past ten years has produced a new generation of complex electronic instrumentation. This generation of instruments is less costly and more reliable and provides measurement accuracy previously available only in standards laboratory environments. ' Most of these modern instruments are based on digital logic circuit designs, especially for control and display functions. Recognizing the fact that logic circuits can be readily interconnected and remotely controlled or monitored, the IEEE Standards Board approved IEEE Standard 488-1975, Digital Interface for Programmable Instrumentation. That document defines an instrument bus that has become the industry standard. Basically, an instrument designed with an interface connector and signals that conform with the IEEE standard can communicate over a 16-line bus with other instruments and/or controllers designed to the same standard. Thus, a new family of instruments is emerging that can be interconnected to form “systems” that perform complex functions. Previously, systems were produced only by spending considerable design time and funding for each system; the instruments now conforming to the IEEE standard allow “off the shelf” purchase of instruments and system integration at minimal cost. High-speed, automatic, programmable instrumentation can now easily be implemented by interfacing a computer to the “instrument bus” that conforms to the IEEE standard. DIGITAL’s low-cost, highperformance LSI-11 microcomputer is the ideal solution for instrumentation designs. It provides minicomputer performance based on microprocessor technology. Its instruction set is compatible with most software presently available for the larger PDP-11/40 minicomputer. An instrumentation system designed in this manner is an easy to use, inexpensive, powerful tool for instrument system designers. The IBV11-A option described in this manual is the instrument bus to LSI-11 bus interface. The information contained in this manual will enable a user to determine which LSI-11 options are required for a specific instrumentation application, to install the IBV11-A in the LSI-11 system, to connect the IBV11-A to instruments, and to program the LSI-11 to communicate with the instrument bus. Vil CHAPTER 1 INTRODUCTION 1.1 GENERAL The IBV11-A (Figure 1-1)is an LSI-11 option that interfaces the LSI-11 bus with the instrument bus as described in IEEE Standard 488-1975, Digital Interface for Programmable Instrumertation. An IBV11A can be installed in any basic LSI-11 system configuration. 1.1.1 - LSI-11 Systems Three basic LSI-11 system configurations comprise the LSI-11 family: LSI-11 system components, the PDP-11/03, and the PDP-11V03. LSI-11 component systems include individual modules, backplane, etc., ordered as separate items. The user purchases only those items required for a specific application. The PDP-11/03, a boxed version of the LSI-11, is designed for users that need a packaged micro- computer system. It consists of an LSI-11 microcomputer and 4K memory, a modular power supply, and a mounting box. It is easy to use an LSI-11-based microcomputer for system development or dedicated applications. The PDP-11VO03 is the latest addition to the LSI-11 family. It is a mass storage-based system, including the PDP-11/03, the RXV 11 floppy disk system, a system cabinet and power distribution panel, either a VT52 DECscope or LA36 DECwriter terminal, RT-11 system software, and system diagnostics. Refer to DIGITAL’s Microcomputer Handbook for detailed information on theLSI-11 “family” of systems, including user-assembled component LSI-11 systems, the PDP-11/03 packaged LSI-11 microcomputer system, and the PDP-11V03 floppy disk-based LSI-11 system. 1-1 ] LSI-H1 BUS STRUCTURED BACKPLANE FINGERS 9 9 L 1 9 9 7 L | il (- | L 7 L { ] IT ] 7 L g | 1 I— I L ’5 E:D l 7 | [f — u S~ | (s2} / ADDRESS SELECT SWITCHES I | (IBS & IBD REGI%%E:-‘?SE) o ; 9 9 ] 3 l (1) E SELECTSWITGUES o N| R B | U i 20- PIN INSTRUMENT BUS ——_| CABLE CONNECTOR ,::n "n-4719 Figure 1-1 IBVI11-A Instrument Bus Interface Module 1.1.2 IBV11-A Interface Option The IBV11-A is contained on a 13.2 cm (5.2 in) by 22.8 cm (8.9 in) printed circuit board assembly; a printed circuit board of this size and shape is also referred to as a “double-height module.” Fingers on one end of the module plug directly into any LSI-11 bus-structured system backplane. A connector on the module mates directly with the instrument bus via the BN11A instrument bus cable supplied with the option. The IBV11-A is the LSI-11 bus/instrument bus interface that makes an LSI-11-based programmable instrument system possible. On the LSI-11 bus side of the interface, the IBV11-A features include: e PDP-11 software-compatible s Board-mounted user-configured switches that allow easy device (register address) and interrupt vector address selection ' e RT-11/FORTRAN IV* and RT-11/BASIC* (easy to learn and easy to use programming languages that are user-oriented; no need for users to become experts in computer programming) e System hardware-compatible with any LSI-11 component system, PDP-11/03, and PDP11V03 systems. On the instrument bus side of the interface, the IBV11-A features include: e Instrument bus-compatible with IEEE Standard 488-1975 e Supports cable length up to 20 m (65.6 ft) total e 15 devices (maximum) can connect to the bus e Instrument bus-compatible with instrument manufacturers’ devices. 1.1.3 Instrument Bus Before the potential applications for the IBV11-A can be realized, an understanding of the instrument bus functions is required. (The LSI-11 microcomputer’s I/O bus is described in the Microcomputer Handbook and is not repeated here.) The instrument bus is capable of supporting up to 15 devices, in'cluding the IBV11-A. The physical structure of the instrument bus, the functional relationships of devices connected to the bus, and the 16 signals that comprise the bus are discussed in the following paragraphs. Physical Structure Physically, the instrument bus is composed of the cables and instrument connectors that interconnect a system. The cables are terminated with a standard connector that will mate with any instrument or device conforming to the IEEE standard. Each connector contains a male plug and a female receptacle in one housing (Figure 1-2). This allows the instrument bus user to stack connectors for interconnecting instruments in a “star” or linear arrangement. Both ends of the cable are terminated with identical connectors. *Planned software options. 1-3 L ——_20-PIN y o] BN11A CONNECTOR [ INSTRUMENT BUS CABLE (CONNECTS FIRST INSTRUMENT TO IBV11-A ONLY) IBVII—-A INTERFACE MODULE RECEPTACLE FOR SECOND (AND SUBSEQUENT) 1 rl INSTRUMENT VIA INSTRUMENT I BUS CABLES A — —{_| 2 A — | USER'S INSTRUMENT 11-4715 Figure 1-2 IBVI11-A Instrument Bus Cable The instrument bus cable (type BN11A) that connects the IBV11-A to the first instrument on the bus is different, however. One end (the instrument end) has a connector as previously described. The other end (at the IBV11-A) is terminated with a molded, 20-cavity housing that mates with the 20-pin connector on the IBV11-A module. | System Device Functions System devices that connect to the instrument bus function as either “talkers,” “listeners,” or “‘controllers,” or a combination of the three functions (Figure 1-3). The function of each in the instrumentation system must be understood before the individual bus signals can be described. System Controller - The instrument bus always contains one device designated the system controller. The IBV11 usually performs this function. It can control all devices connected to the instrument bus comprising that system. NOTE When the IBV11-A is the only system controller, the ER1 switch (S1-8) must be in the OFF position. When the IBV11-A is used in a system that contains another system controller, S1-8 must be in the ON position. Controller - A controller is capable of controlling talkers and listeners connected to the bus. Only one controller may be active at a time and it is designated the “controller-in-charge.” The IBV11-A usually performs this function. All device addressing, device polling, commands, and data byte transfers are controlled by the controller-in-charge. 1-4 D DEVICE A DEVICE C ABLE TO TALK AND LISTEN " 2 ABLE TO LISTEN, ONLY |— & us = o] [+ 4 |.— DEVICE B ABLE TO TALK je— AND LISTEN DEVICE D - ABLE TO TALK, ONLY IBVII-A INSTRUMENT BUS INTERFACE CONTROLLER~ IN ~ CHARGE _____________ LSI-11 4 BUS INTERFACE ABLE TO CONTROL, MlC#ggédéUTER (KD11-F, KD11-J, ETC.) - - - - - TALK, AND LISTEN " < TM I FACE PE?QH*ERAL MoDuULES (DLV11, DRVII, ETC) - - - - [ PRINTERS,ETC. -] w n SYSTEM MEMORY (MSV11-8, MSVI1-C, MRVII-AA, MMVI1, ETC.) n - ‘kv)7 CONSOLE DEVICE INTERFACE (DLV11) SERIAL LINE INTERFACE FLOPPY DISK (RXVI1) CONSOLE TERMINAL 11-4718 Figure 1-3 Typical System - Functional Relationship Listener — A listener is a device that is capable of receiving commands and data from the instrument bus. More than one listener may be active at a time. Talker - A talker is a device that is capable of receiving commands and transmitting data via the instrument bus. Only one talker may be active at a time. Bus Signal Functions Sixteen signal lines comprise the instrument bus. Eight lines comprise an 8-bit asynchronous bidirec- tional data bus. Logical 1s are produced by asserting data lines low (ground). The remaining eight lines provide control functions. Three of these lines are “message handshaking” signals that control data byte transfers over the instrument bus. The remaining five control signal lines provide general interface management functions. A detailed description for each signal is included in Chapter 2. Controller-In-Charge Commands Controller-in-charge commands are the IBV11-A to instrument bus byte transfers that control instrument system operation. The IBV11-A becomes active as controller-in-charge by asserting TCS. If any talker is active when the controller-in-charge is to become active, the IBV11-A first inhibits additional byte transfers by asserting NRFD and waits for DAV to become not asserted, indicating that the operation has been completed; it then asserts ATN. Approximately 0.5 us later, NRFD becomes not asserted, and it can then transmit commands to all devices on the instrument bus. Commands are transmitted via the DIO<7:1> lines. Commands are coded as 7-bit ASCII characters; the DIOS line is not used for command transfers. The actual command set conforms to the instrumentation bus standard and is described in the IBV11-A specifications. The actual commands and the sequence in which they are issued are completely under the control of the LSI-11 system software being executed. 1.2 SCOPE The remaining chapters of this manual contain all of the information normally required for the LSI-11 system user to install, program, and use the IBV11-A option. The manual is organized as follows: Chapter 1 Introduction - General information and references. Chapter 2 Specifications — Hardware and software specifications for IBV11-A users. Software specifications are included for programming the LSI-11 processor to communicate with the IBV11. The procedure for programming specific instruments varies depending on the particular instrument; refer to the instrument manufacturer’s documentation for programming instructions. Chapter 3 Installation - Minimum LSI-11 system requirements to support the IBV11-A, procedures for configuring IBV11-A module switches, installation in the LSI-11 backplane, and instrument bus cabling. Chapter 4 Programming Examples - Sample instrument system application programs are discussed in this chapter. Chapter 5 Technical Description - Includes a block diagram of the IBV11-A and functional theory of operation. Chapter 6 Maintenance - Lists availabie diagnostics. 1.3 REFERENCES Digital Equipment Corporation publications: Basic Hardware Manuals Microcomputer Handbook PDP-11V03 System Manual 1-6 Hardware Option Manuals RXVI11 User's Manual { Floppy Disk System) DRVI1I-B General Purpose DMA Interface User's Manual DRV11-P Foundation Module User’s Manual H780 Power Supply User's Manual LAVI1 User's Manual (LSI-11 bus interface controller for the LA180 DECprinter I) MSVI1-C MOS Read/Write Memory User’'s Manual MRVI1I-BA LSI-11 UV PROM-RAM User's Manual IEEE Publications: Digital Interface for Programmable Instrumentation (IEEE Std. 488-1975) 1-7 CHAPTER 2 SPECIFICATIONS 2.1 GENERAL This chapter contains detailed specifications for IBV11-A users, including hardware and programming specifications for the module, and instrument bus specifications. Note that only the instrument bus specifications necessary for using the IBV11-A are included; detailed instrument bus specifications for designers are included in IEEE Standard 488-1975, Digital Interface for Programmable Instrumentation. Refer to instrument manufacturer’s documentation for the correct procedure for instrument bus addressing, commands, etc. for that particular instrument. Each IBV11-A option includes one IBV11-A (M7954) module, one BN11A-04 4 m (157.5 in) cable, and user documentation. 2.2 2.2.1 IBV11-A MODULE SPECIFICATIONS General Specifications Power Requirements +5V £ 5% 0.8 A typical (1.5 A maximum) Mechanical Height Length* Width 13.2 cm (5.2 in) 22.8 cm (8.9 in) 1.27 cm (0.5 in) Environmental Temperature Storage Operating . Relative Humidity -40° to 60° C (-40° to 140° F) 5° to 50° C (41° to 122° F) 10 to 95% (no condensation) 2.2.2 LSI-11 Bus Interface Signals The IBV11-A conforms to LSI-11 bus specifications stated in the Microcomputer Handbook, Section sne 1, Chapter 3. Refer to that document for complete LSI-11 hus bus specifications. Backplane pin utilization is shown in Table 2-1. *Length as stated is approximate and includes module handle. Actual module length is 21.6 cm (8.5 in). 21 Electrical Input Logic Levels TTL Logical Low TTL Logical High Qutput Logic Levels TTL Logical Low TTL Logical High ‘Bus Receivers Logical Low Logical High Bus Drivers Logical Low Logical High 0.8 Vdc max 2.0 Vdc min 0.4 Vdc max 2.4 Vdc min 1.3 Vdc max, -10 uA max at OV 1.7 Vdc min, 80 uA max at 2.5V 0.8 Vdc max at 70 mA 25 uA max at 3.5V Table 2-1 IBV11-A Backplane Pin Utilization Row A Pin Row B Signal Mnemonic Pin Signal Mnemonic Module Side 1 (Component Side) AAl ABI ACl ADI1 AE! AF1 AHI1 BSPAREI BSPARE 2 BADI16 L BADI17L SSPAREI] SSPARE2 SSPARE3 BA1 BBIi BCl1 BD1 BE1 BF1 BH1 BDCOK H BPOK H SSPARE SSPARES SSPARES6 SSPARE7 SSPARES AJl GND BJ1 GND ATl GND BT1 GND AVl +5B BV1 +5B AKl1 ALl AMI1 ANI1 APl ARI1 AS1 AUl MSPAREA MSPAREA GND BDMR L BHALT L BREF L PSPARE3 BK1 BL1 BM] BNI1 BP1 BR1 BS1 PSPAREI BUI1 2-2 MSPAREB MSPAREB GND BSACK L BSPARES6 BEVNT L PSPARE4 PSPARE2 Table 2-1 IBV11-A Backplane Pin Utilization (Cont) Row B Row A Pin Signal Pin Mnemonic Signal Mnemonic Module Side 2 (Solder Side) AA2 AB2 AC2 AD?2 AE2 AF2 AH?2 AlJ2 AK?2 AL2 AM2 AN2 AP2 AR2 AS2 AT2 AU2 AV2 2.2.3 BA2 BB2 BC2 BD2 BE2 BF2 BH2 BJ2 BK2 BL2 BM?2 BN2 BP2 BR2 BS2 BT2 BU2 BV2 +5 —-12 GND +12 BDOUT L BRPLY L BDIN L BSYNC L BWTBT L BIRQ L BIAKI L BIAKO L BBS7 L BDMGI L BDMGO L BINIT L BDALO L BDALI1L +5 —-12 GND +12 BDAL2 L BDAL3 L BDAL4 L BDALSL BDAL6 L BDAL7L BDALS L BDAL9 L BDALIOL BDAL 11 L BDALI12 L BDALI3 L BDALI4 L ' BDALIS L Instrument Bus Interface Nominal Logic Levels 0 = 4+2.0 V minimum 1 = +0.8 V maximum Bus Drivers and Receivers Driver low state output voltage Driver high state output voltage Receiver low state output voltage Receiver high state output voltage Receiver input hysteresis +0.4 V (maximum) at +48 mA sink current +2.6 V (minimum) +0.4 V (maximum) +2.4 V (minimum) 400 mV (minimum) (typically, 900 mV) Signal Termination Each instrument bus signal line is terminated within the device by a resistive load (3.0K pull-up to Ve, 6.2K to ground) to establish a steady-state voltage when all drivers on a line are in the high impedance state. 2-3 Electrical Length of Instrument Bus Transmission N The length of the electrical transmission path over the bus must be within the following specifications: Number of Bus Segments Bus Segments (m) 5 10 : 14 Maximum Number of Devices Transmission Path (m) 4 6 20 2 11 20 1 15 | 14 Instrument Bus Data Rate The maximum data transfer rate over the instrument bus is 250K bytes per second (4 us/byte) provided that all electrical specifications stated herein are met. Software Data Rate The maximum estimated data rate for a tight, dedicated routine to move data from the instrument bus to the LSI-11 memory is 40 kilobytes/second. The maximum estimated data rate for general-purpose and high-level language routines is 5 kilobytes/second. Instrument Bus Cable Connector Pinning Instrument bus cable connector pins are identified in Figure 2-1. Pin utilization and signal names for the IBVI1-A end and user’s instrument end of the cable are identified in Table 2-2. 11- 4886 Figure 2-1 IBV11-A Instrument Bus Connector 2-4 Table 2-2 BN11A IBV11 to Instrument Bus Cable - Connector Pinning DIO1 Cable Connector Pins (Instrument End) -ITAANWV OV e b et WL et b PE et 1IN et el DIO4 EOI DAV RFD DAC IFC SRQ ATN SHIELD DIOS5 DIO6 DIO7 DIO8 REN GND (6) GND (7) GND (8) GND (9) GND (10) GND (11) GND (logic) N [\ B O I o) DD b et BN W N = QWO DIO2 DIO3 AW — Instrument Bus Signal Name SCCPZZZU0MIRET WX <AmZTAC Instrument Bus Connector Pins on IBV11-A Module NOTE GND(n) (wheren = 6, 7, 8, 9, 10, 11) is the ground return for the signal on pin “N”’ of the instrument bus connector. For example, GND (6), pin 18, is the ground return for the signal DAYV on pin 6. These ground returns are returned to the logic ground of their respective drivers and receivers on the IBV11-A module. Signal Functions Sixteen signal lines comprise the instrument bus as shown in Figure 2-2. Each signal line is partially terminated by each device connected to the bus. Eight lines (DIO<1:8> L) comprise an 8-bit asynchronous bidirectional data bus. Logical 1s are produced by asser tino data | ines low (ground). The remaining eight lines provide control functions, as described in the following paragraphs. 2993 2-5 el vir 2 INSTRUMENT BUS SIGNAL LINES Ao HHT L DEVICE A ~ DEVICE B DEVICE C <:: DEVICE D <‘ } DIOK1: 8> } 8-LiINE DATA BUS 3210 MESSAGE HANDSHAKING NDAC tFe CONTROL ) ATN GENERAL SRQ INTERFACE REN - > SIGNAL LINES (8) MANAGEMENT EO! J t1H-4717 Figure 2-2 Instrument Bus Signal Lines 2-6 Three “message handshaking” control signals control data byte transfers over the 8-line data bus. They provide the necessary handshaking to complete interlocked, asynchronous data transfers. These control signals are described below. Data Valid (DAV) - DAV is asserted by the active talker or active controller to indicate that it has placed valid data on the DIO signal lines. DAV is asserted only after all listener devices are ready for data and valid data has been placed on the DIO lines for 2 us (minimum). Not Ready for Data (NRFD) - NRFD enables an active listener to indicate that it is “busy,” or not ready for data. All active listeners must be “ready” to not assert NRFD, enabling a talker to transmit a data byte. Not Data Accepted (NDAC) - All active listeners assert NDAC. All inactive listeners do not assert NDAC. The active listener indicates that it has accepted data during a data transfer by not asserting NDAC. When more than one active listener is on the instrument bus, the last active listener to not assert NDAC indicates that all devices have accepted the data. The remaining five control signals are for general interface management. Each signal is described below. Interface Clear (IFC) - IFC is a “master clear” for all devices that connect to the interface bus. IFC is asserted by the IBV11-A only when it is an active system controller. All devices respond to the active IFC signal by returning to the idle state within 100 us NOTE When the IBV11-A is the only system controller, the ER1 switch (S1-8) must be in the OFF position. When the IBV11-A is used in a system that contains another system controller, S1-8 must be in the ON position. Remote Enable (REN) - Typical devices (instruments) connected to the instrument bus are capable of local (device control panel) or remote control operation via the instrument bus. The IBV11-A, as system controller, asserts REN to enable remote operation, or negates REN to allow local operation of all devices. When REN is asserted, the IBV11-A may return selected devices to the local mode by addressing the devices and issuing a ““go to local’’ command. When in the local mode, devices may respond to control and data transmissions over the instrument bus that do not conflict with local control functions. Attention (ATN) - The IBV11-A, as controller-in-charge, asserts the ATN signal line when it is transmitting commands over the DIO lines. An active ATN signal causes any previously active talker to become inactive and all devices may receive commands from the IBV11-A. End or Identify (EOI) - EOI can be asserted either by the IBV11-A, as controller-in-charge, or by an active taiker. A taiker asserts EOI to indicate the last byte of a message is being transmitted. The IBV11-A can assert EOI while also asserting ATN to conduct a parallel poll. TOIMNT e Aam o am ~ ana o 4 Service Request (SRQ) - The IBV11-A monitors the SRQ line for service requests from devices connected to the instrument bus. The IBV11-A’s control/status register (CSR) can be programmed to cause IBV11-A-generated interrupts to occur whenever the SRQ line is asserted. Thus, interrupt-driven routines can be included in system software that will automatically service devices on the instrument bus. 2-7 2.2.4 Programming The IBV11-A communicates with devices connected to the instrument bus under the control of the LSI-11 program being executed. All communication between the LSI-11 and the IBV11-A is via the instrument bus status (IBS) and instrument bus data (IBD) registers. The programmer must be aware of the functional significance of each bit in both registers before any programs can be written that will control specific devices on the instrument bus. In addition, the programmer must establish instrument (device) addresses and conform to programming rules specified for each instrument connected to the instrument bus. IBS and IBD Registers The IBS register provides the means for controlling the instrument bus signals and IBV11-A functions relative to the LSI-11 bus. The low byte of the IBD register, on the other hand, is used for passing commands to devices connected to the bus and for transmitting and receiving data between the LSI-11 processor and talker and listener devices. In addition, the high byte of the IBD register allows for LSI11 processor monitoring of all instrument bus signal (data and control) lines. IBS and IBD registers are shown in Figure 2-3 and described in Tables 2-3 and 2-4. 15 08 edren (| | Jodol [ 07 [T 00 1 [ T[] «—— BIT ]T]] E TCS (R/W) EOP (R/W) REM (R/W) IBC (R/W) LON (R/W) TON (R/W) IE (R/W) ACC (R/W) LNR (R) TKR (R) CMD (R) {NOT USED) {NOT USED) ER! (R) ER2 (R) SRQ (R/W)* 15 i reisTer | " : | I | ' T | T | 08 I | I | 07 - : 00 <—— BIiT T | | T NDAC <8:1> (R/W) (DATA LINES) DAC (R) (NDAC INVERTED) DAV (R) RFD (R) (NRFD INVERTED) SRQ (R) REN (R) IFC (R} ATN (R) EOI (R} NOTE: R/W = Read/ Write Bit R - Only Bit = Read *May be written only if ER1 inhibit switch is on. Figure 2-3 11-47186 IBV11-A Register and Bit Assignments 2-8 Table 2-3 IBS Register Bits Descriptions Bit Function 00 Take Control Synchronously (TCS). Set and cleared under program control to enable or disable the IBV11-A controller-in-charge function by taking control synchronously or by negating ATN. Setting TCS will cause NRFD to be asserted for at least 500 ns before DAV is checked. ATN is then asserted when DAY is not asserted. NRFD must be unasserted and CMD is set 500 ns (minimum) after ATN is asserted. TCS is cleared by BINIT L and IFC. 01 End or Poll (EOP). Set and cleared under program control to assert or unassert the EOI line. EOP is cleared by BINIT L and IFC. 02 Remote On (REM). Set and cleared under program control to assert or unassert the REN line. REM is cleared by BINIT L and IFC. 03 Interface Bus Clear (IBC). When set, the leading edge of IBC produces IFC for 125 us (approximately). At the end of IFC, TCS is automatically asserted and IBC is automatically cleared. IBC is cleared by BINIT L. 04 Listener On (LON). Set or cleared by the program to enable or disable the IBV11-A listener function. When LON is set and the DAYV line is asserted, the IBS LNR bit (bit 08) becomes set. When LON is cleared, the IBV11-A ignores DAV LON is cleared by BINIT L and IFC. 05 Talker On (TON). Set or cleared by the program to enable or disable the IBV11-A talker function. TON is cleared by BINIT L and IFC. 06 Interrupt Enable (IE). Set and cleared by the program to enable or disable IBVI11-A interrupts. IE is cleared by BINIT L. 07 Accept Data (ACC). Set and cleared by the program. When ACC is cleared, reading a data byte from the DIO lines will automatically assert the DAC line and clear the LNR bit (bit 08). When ACC is set, the program must clear the low byte of the IBD register in order to clear the LNR status bit and assert the DAC line. ACC is cleared by BINIT L and IFC when LON, TON, and TCS are all off; ACC may be set to assert NRFD. 08 Listener Ready (LNR). When set, LNR indicates that the IBV11-A has a data or command byte that is ready for reading from the low byte of the IBD. LNR is set when LON is set and the DAV line becomes asserted. LNR is cleared by reading the IBD low byte if ACC is cleared, or by clearing the IBD low byte if ACC is set. LNR is also cleared when LON is cleared by the program and by BINIT L and IFC. 09 Talker Ready (TKR). When set, TKR indicates to the LSI-11 processor that the IBV11-A is ready for the next data byte to be transmitted to the DIO lines via the low byte of the IBD register. TKR is set when TON is set, TCS is cleared, and when listeners are ready for data. TKRis cleared by BINIT L or IFC, by writing a command or data byte into the low byte of the IBD register, or by the program clearing TON or setting TCS. 2-9 Table 2-3 IBS Register Bit Descriptions (Cont) Bit Function 10 Command Done (CMD). When set, CMD indicates to the LSI-11 processor that the IBV11A is ready for the next command byte to be transmitted to the DIO lines via the low byte of the IBD register. CMD is set by a successful TCS to indicate that the ATN line was asserted and that the next command byte may be transmitted over the instrument bus. CMD is also set when the DAC line is asserted after the command has been accepted by the addressed device on the instrument bus. CMD is cleared by BINIT L or IFC, by writing a byte (command) into the low byte of the IBD register, or by the program clearing the TCS bit. 11 Not used - read as 0. 12 Not used - read as 0. 13 Error 1 (ER1). Set whenever a conflict occurs between the instrument bus ATN, IFC, <r REN lines and their IBV11-A control hardware. When set, ATN H is cleared and cannot be set. This condition can only be cleared by clearing the cause of the error. ER1 can occur when another system controller is connected to the instrument bus. The error can then be suppressed by setting the ER1 inhibit switch (S1-8) on the IBV11-A module to the ON position. If the IBV11-A is the only system controller, set S1-8 to the OFF position. 14 Error 2 (ER2). Set when the IBV11-A tries to send a data or command byte while there is no active listener or command acceptor on the instrument bus. ER2 is cleared by clearing both the TON and TCS bits. 15 Service Request (SRQ). This bit always indicates the status of the instrument bus SRQ line. It may be written (set and cleared) if the ER1 inhibit switch is set. Table 2-4 IBD Register Bit Descriptions Bit Function <15:8> Instrument bus control line status. The program can monitor the signal status of all eight control signals by reading this byte. Note that DAC (bit 08) and RFD (bit 10) are inverted with respect to the actual instrument bus signal lines. <7.0> Instrument bus data input/output. The program can read or write via this register byte to receive or transmit command or data bytes over the instrument bus. Bits <7:0> correspond to DIO lines <8:1>. Interrupts The IBVI11-A is capable of generating four separate interrupt requests; each has separate interrupt vectors and normally would have separate service routines. Interrupts can be requested only when the IBS interrupt enable (IE) bit is set. Interrupt requests are priority structured in the IBVi1-A. A summary of the four interrupt types is provided in Table 2-5. Table 2-5 Priority Vector Highest Second highest Third highest 1IBV11-A Interrupt Vectors Associated IBS Bit Cause of Interrupt 000XNNO0O ER2, ER1 Error condition. 000XNNO04 SRQ A device connected to the instrument bus is 000XNN10 TKR, CMD The IBV11-A is an active talker and it is ready requesting service. for the LSI-11 processor to output a byte to the low byte of the IBD register. [The IBV11A will normally then transmit the byte over the instrument bus to the active listener(s).] Lowest 000XNN14 LNR The IBVI11-A is an active listener and has a data byte to be read by the LSI-11 processor. Notes 1. x = User-configured vector address octal digit. 2. N = bits. 3. User-configured vector address binary Associated IBS bits shown, when set, produce interrupt requests if the IE bit is set. 2.3 2.3.1 INSTRUMENT BUS CONTROLLER-IN-CHARGE COMMANDS General Controller-in-charge commands may only be issued by an active controller-in-charge. When the system controller asserts the IFC control line, it designates a specific controller as the controller-incharge. A controller may also become the controller-in-charge when the current controller-in-charge specifically transfers control to it with the “take control” command. The IBV11-A will detect a successful transfer of control as an ER1 condition (if S1-8 is in the OFF position) because it normally is the controller-in-charge as well as the system controller; ER1 can be avoided (when another device becomes controller-in-charge) by setting S1-8 on the IBV11-A module to the ON position. A controller-in-charge becomes active 2 us after asserting the ATN control line. First, the controller- in-charge stops further data byte transfers between the active talker and active listeners by asserting the NRFD line and then waits for the talker to unassert the DAV line. When DAYV is unasserted, the controller-in-charge asserts ATN to declare its control of the DIO message lines. The controller-in- charge waits for 0.5 us after asserting ATN before unasserting the NRFD line so that the talker and listeners will have enough time to recognize and respond to the asserted ATN line. 2-11 While active, the controller-in-charge uses the DIO lines to issue command bytes to all devices on the instrument bus. All controller-in-charge commands are coded into a 7-bit command byte on DIO<7:1>. The DIOS line remains unasserted, and is not decoded by devices when a command byte is received. The command byte MSB is on DIO7; the LSB is on DIO1. Command bytes are restricted to 7 bits so that their coding may be correlated to the ISO 7-bit code (or the equivalent code in the American National Standard Code for Information Interchange, ANSI X3.4-1968) because it is con venient to both generate and interpret this code. Command decoding in the IBV11-A, if desired, must be handled by software. 2.3.2 Addressed Command Group (ACG) Commands in this group (Table 2-6) affect only the currently addressed talker or the currently addressed list of listeners. Table 2-6 Addressed Command Group Command | ASCII ASCII Mnemonic| Character | Code Keyboard | Devices Function Affected GTL SDC PPC GET TCT CTRL A | Listeners | Go to Local CTRL D | Listeners | Selected Device Clear CTRL E | Listeners | Parallel Poll Configure CTRL H | Listeners | Group Execute Trigger CTRL1 Talker Take Control SOH EOT ENQ BS TAB 001 004 005 010 011 Command Function Go to Local (GTL) - The GTL command causes addressed listeners to go from the remote mode to the local mode. When in the local mode, a device is controlled by its front and rear panel controls. | Selected Device Clear (SDC) - The SDC command causes addressed listeners to be cleared (initialized). Parallel Poll Configure (PPC) - The PPC command causes addressed listeners to enter the parallel poll configure mode. The next command must be from the secondary command group; otherwise, the listeners will exit the parallel poll configure mode. While in parallel poll configure mode, the listeners will interpret all secondary command group commands as 1 of the 16 possible Parallel Poll Enable (PPE) commands or as the PPD (Parallel Poll Disable) command. Group Execute Trigger (GET) - The GET command causes the addressed listeners to start the basic operation of the device that the listener is a part of (only if that operation is at rest when this command is received). Take Control (TCT) - The TCT command causes the addressed talker of a controller to enable the controller to become the controller-in-charge as soon as the current controller-in-charge unasserts ATN. Controller-in-charge status can be transferred in an orderly manner from one controller to another by the current controller-in-charge addressing the talker of the next controllerin-charge, and then issuing the TCT command followed by unasserting ATN. Universal Command Group (UCG) 2.3.3 Commands in this group (Table 2-7) affect all devices able to respond without having to be previously addressed. The IEEE standard permits the first three of these commands to be issued while the system controller is asserting IFC. However, the ability to issue commands during IFC is not permitted in the IBV11-A. Local Lockout (LLO) - The LLO command causes all instruments to ignore their local *“return to local” signal. This command can be countermanded only by powering the instrument off and then on, or by the system controller unasserting the REN control line. Device Clear (DCL) - The DCL command causes all devices on the instrument bus to be cleared | (initialized). Parallel Poll Unconfigure (PPU) - The PPU command causes all parallel poll configurations to be cleared (unconfigured). Only devices that have been parallel poll configured will respond to a “parallel poll” request. After the PPU command, no device will respond to a *“parallel poll” request. Seria! Po!l Enable (SPE) - The SPE command causes all talkers to enter the serial poll mode. When in serial poll mode, an addressed talker will respond to the unassertion of the ATN control line by sending its device’s status byte to the controller-in-charge. When the controller-in-charge asserts ATN after a talker has responded with a status byte, bit 7 of the status byte will be cleared if it was set. This will in turn cause the talker to unassert its SRQ line driver if it was asserted. Serial Poll Disable (SPD) - The SPD command causes all talkers to exit the serial poll mode and return to the normal data mode where an active talker sends data bytes rather than a single status byte. Table 2-7 ASCII Command Character | Mnemonic LLO DCL PPU SPE SPD 2.3.4 DCI DC4 NAK CAN EM Universal Command Group ASCII Code Keyboard Function Command Function 021 024 025 030 031 CTRLQ CTRLT CTRL U CTRL X CTRLY Local Lockout Device Clear Parallel Poll Unconfigure Serial Poll Enable Serial Poll Disable Listener Address Group (LAG) Commands in this group (Table 2-8) are used to address one or more listeners at a time or to unaddress all listeners at once. Listener addresses specified by these commands are called primary listener addresses because they can be followed by a secondary address from the secondary command group to address an extended listener. Addressed listeners become active listeners when the controller-in-charge unasserts ATN. 2-13 Primary and secondary listener address decoding in the IBV11-A, if desired, must be handled by software. My Listen Address (MLAn) - The MLA command covers 31 primary listener addresses. Any listener that recognizes its own address becomes an addressed listener. Only addressed listeners are able to receive data bytes from a talker. Unlisten (UNL) - The UNL command causes all listeners to become unaddressed. Table 2-8 Listener Address Group Commands Command | ASCII ASCII Mnemonic | Character | Code Keyboard Function Command Function MLAOO SP 040 Space My Listen Address 0 MLAOI MLAO2 ! “ | 041 042 ! ¢ # $ % & 3 4 5 6 MLAO7 MLAOS ‘ ( 047 050 ‘ ( 7 8 MLAO09 MLAIOQ ) * 051 052 ) * MLALII MLAI2 + ’ 053 054 + ’ 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MLAO3 MLAO4 MLAOS5 MLAO6 # $ % & 043 044 045 046 MLAI13 - 055 - MLA14 MLAI1S . / 056 . MLAI6 MLA17 MLA18 MLAI19 MLA20 MLA2I MLA22 MLA23 MLA24 MLA25 MLA26 MLA27 MLA28 MLA29 MLA30 0 ] 2 3 4 5 6 7 8 9 : : < = > 060 061 062 063 064 065 066 067 070 071 072 073 074 075 076 0 1 2 3 4 5 6 7 8 9 : : < = > UNL r? 077 ? 057 1 1 2 / 2-14 25 26 27 28 29 My Listen Address 30 Unlisten 2.3.5 Talker Address Group (TAG) Commands in this group (Table 2-9) are used to address or unaddress one talker at a time. Talker addresses in this group are called primary talker addresses because they can be followed by a secondary address from the secondary command group to address an extended talker. An addressed talker becomes active when the controller-in-charge unasserts ATN. Primary and secondary talker address decoding in the IBV11-A, if desired, must be handled by software. My Talk Address (MTAn) - The MTA command covers 31 primary talker addresses. Any talker that recognizes its own address becomes addressed while all other talkers become unaddressed. Only an addressed talker is able to send data bytes. Untalk (UNT) - The UNT command causes the addressed talker to become unaddressed without addressing another talker. Table 2-9 Talker Address Group Commands Command Mnemonic ASCII Character ASCII Code Keyboard Function Command Function MTAOQO0 MTAOI MTAOQ2 MTAO3 MTAO04 MTAOS MTAO06 MTAOQ7 MTAO8 MTAOQ9 MTAI10 MTAII MTAI12 MTAI3 MTAIl4 MTAIS MTAI16 MTAI17 @ A B C D E F G H | J K L M N O P Q 100 101 102 103 104 105 106 107 110 111 112 113 114 115 116 117 120 121 @ A B C D E F G H I J K L M N O P Q My Talk Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 MTA22 \Y 126 \Y 22 MTAI8 MTAI19 MTA20 MTA2I MTA23 MTA24 MTA25 MTA26 MTA27 MTA28 MTA?29 MTA30 UNT R S T U W X Y Z [ \ Jor t A - 0T « 122 123 124 125 R S T U 127 130 131 132 133 134 135 136 137 w X Y Z [ \ Jor 1t A - Ol « 2-15 18 19 20 21 23 24 25 26 27 28 29 My Talk Address 30 Untalk 2.3.6 Secondary Command Group (SCG) The commands in this group are used to modify the parallel poll configure (PPC) command or to specify an extended talker or listener address. This group consists of 32 codes starting with the ASCII code for “grave.” However, the last code, equivalent to the ASCII code for delete, is not used. Parallel Poll Enable/Disable Commands (PPE/PPD) - Each parallel poll enable (PPE) command (Table 2-10) must follow a parallel poll configure (PPC) command, which puts currently addressed listeners into parallel poll configure mode. Usually, only one listener is addressed before a PPC command is issued so that the PPE command will affect only one device at a time. However, more than one device may be affected by a single PPE command when this is desirable. The PPE command is used to dynamically instruct (program) some devices as to how to respond to a parallel poll request. The response to a parallel poll request in some devices is determined by hardware that is field-settable during system configuration. Some devices, including the IBV11-A, are unable to respond to a parallel poll request. A device responds to a parallel poll request by returning one bit of status to the controller-incharge on one of the eight DIO lines. The second digit of the PPE command mnemonic specifies the DIO line to use. The first digit of the PPE command mnemonic specifies which logical state of the status bit should cause the DIO line to be asserted low. Thus, the PPE15 form of the PPE command instructs the device to respond to a parallel poll request by asserting DIO line 5 if the status bit is a logical 1. Table 2-10 Parallel Poll Enable/Disable Commands Command ASCII ASCII Keyboard Mnemonic Character Code Function N 140 n 156 PPEO1 PPEO2 PPEQ3 PPEQO4 PPEOQ5 PPEO6 PPEO7 PPEOS8 PPE11 PPEI12 PPEI13 PPE14 PPE15 PPE16 a b c d e f g h i ] k ] m PPE18 PPD \ 141 142 143 144 145 146 147 150 151 152 153 154 155 a b c d e f g h i j k ] m o P 157 160 o} p (Not used) q 161 q (Not used) DEL 177 DEL PPE17 n 2-16 Command Function Parallel Poll Enable 1 v 2 3 4 5 6 7 8 11 12 13 14 15 16 17 Parallel Poll Enable 18 Parallel Poll Disable The process of selecting a device by addressing a listener, commanding it to enter the parallel poll configure mode, and instructing it how to respond to a parallel poll request is called configuring a parallel poll response. Once configured, a device remembers how to respond to the parallel poll request until it is reconfigured by another PPE or unconfigured by a parallel poll disable (PPD) or a parallel poll unconfigure (PPU) command. A parallel poll request is issued by the controller-in-charge by asserting the EOI control line along with the ATN control line. The PPD command, like all secondary commands, must follow its associated primary command. The PPD command selectively disables (unconfigures) devices from responding to the parallel poll request. The particular devices affected by the PPD command are those devices that have active listeners that respond to the preceding PPC command. My Secondary Address Commands (MSAn) - An MSA command, when used, must follow an MLA or MTA primary address command. The 31 MSA commands are denoted by the mnemonics MSAOQO through MSA30 with codes equivalent to the ASCII codes from “grave” to “tilde.” A secondary address is used to specify an extended talker or listener address. Devices that use extended addressing do not become addressed until the proper secondary address follows the proper primary address. “My secondary address”” commands are listed in Table 2-11. Table 2-11 My Secondary Address Commands Mnemonic Character Code ASCII Keyboard Function Command Function MSAQ0 MSAOI MSAO02 MSAO03 MSAO04 MSAOS5 MSA06 MSAO07 MSAOS8 MSAQ9 MSAI10 MSALI MSAI12 MSAI13 MSA14 MSAILS N a b c d e f g h i ] k 1 m n o 140 141 142 143 144 145 146 147 150 151 152 153 154 155 156 157 \ a b c d e f g h i j k 1 m n 0 My Secondary Address 0 ] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Not used DEL 177 Command MSA16 MSA17 MSAI18 MSAI19 MSA20 MSA21 MSA22 MSA23 MSA24 MSA25 MSA26 MSA27 MSA 28 MSA?29 MSA30 ASCII P q r S t u Y w X y z { | } ~ 160 161 162 163 164 165 166 167 170 171 172 173 174 175 176 p q r S t u Y w X y Y4 { ! } ~ DEL 2-18 16 17 18 19 20 21 22 23 24 25 26 27 28 29 My Secondary Address 30 CHAPTER 3 INSTALLATION 3.1 3.1.1 MINIMUM SYSTEM REQUIREMENTS System Hardware System hardware can range from very simple LSI-11 execute-only systems through dual floppy disk systems running under the RT-11 operating system software. LSI-11 systems fall into three general categories: LSI-11 component systems, PDP-11/03 systems, and PDP-11V03 systems. LSI-11 component systems and PDP-11/03 (packaged LSI-11) systems are configured by the user, ranging from a basic 4K memory and LSI-11 processor upward to a more complex configuration. Expansion beyond the basic system requires the addition of various standard LSI-11 options, including system memory, serial and parallel interfaces for peripherals, floppy disk, etc. All PDP-11V03 systems, however, include 8K memory, a console terminal (VT52 or LA36), and RT-11 operating system software as part of the basic system. The basic PDP-11V03 is factory-configured and shipped as a ready-to-use system capable of developing user-software. The user can add hardware options, such as the IBV11-A, as desired. For a simple execute-only system, the minimum system hardware requirements include a console terminal, a means for loading object programs, and the IBV11-A interface. In addition, LSI-11 com- ponent systems require an LSI-11 processor and 4K memory, one or more backplanes, and +5 V and +12 V power supplies. A simple execute-only system (that is, one that will execute but not develop user application software) can consist of the basic components listed below: Option System Function KD11-F* or KDI11-J LSI-11 processor and 4K memory DLVI11 H9270* or Serial line interface for console terminal (an optional BCOSM or BCO5C cable is required for connection to the terminal) System backplane DDVI11-B VTS50, VT52, Console terminal LA36, LT33, etc. H780* (or equivalent) Power supply IBVI11-A Instrument bus interface *Included in the basic PDP-11/03 system. 3-1 Note that the KD11-F processor and 4K memory uses semiconductor memory which is volatile (programs and data are lost when system power is turned off) and programs must be loaded each time power is turned on. The KD11-J uses non-volatile 4K core memory and normally does not require reloading programs. Non-volatile storage can also be obtained by the use of the MRV11-AA 4K programmable read-only memory (PROM) option or the MRV11-BA 4K UV PROM/256 RAM option; these options are supplied without PROM integrated circuits (ICs). PROM options are available from DIGITAL. The execute-only system, as described, is not capable of developing user application software. Minimum requirements for a paper tape system capable of program development include 8K (total) read/write memory and a paper tape reader/punch. The paper tape reader must be capable of being turned on and off under program control. Either a high-speed or low-speed (110 baud) reader/punch can be used. A low-speed reader/punch function can be implemented by connecting an LT33 Teletype® (DEC-modified ASR33) to a DLV11 serial line interface; the Teletype can also function as the console device. DIGITAL can supply a modification kit for the ASR33 as option model LT33-MB. A modified ASR33 for 115V, 60 Hz operation is available from DIGITAL as option model LT33-DC. If desired, a high-speed reader/punch (user-supplied) can be interfaced to the LSI-11 system as directed in the Digital Components Group Application Note, An LSI-11 Paper Tape Reader/ Punch Interface. Floppy-disk-based systems are capable of maximum flexibility for user program development and applications. Any LSI-11 system capable of executing RT-11 operating system software is capable of supporting IBV11-A applications, including program development. Any LSI-11 system containing 8K read /write memory and a console device can be expanded for RT-11 operation by adding the RXV11 floppy disk option and appropriate software. The PDP-11V03 system includes the required hardware and software to support RT-11. 3.1.2 System Software 3.1.2.1 General - The only software required for IBV11-A operation in an LSI-11 system is the binary program for a specific application. However, in order to generate a binary program on the system, certain software options will aid the program development process. A brief list of software options is provided below. For assembly language program development: 1. Paper tape system software QJV10-CB - This software option includes ED-11 Text Editor, PAS11S Assembler, LINKI11 Linker, DUMPAB Memory Dump Utility, ODT-11 On-Line Debugging Technique, IOX Input/Output Executive, and the Absolute Loader. QJV11-CB, PROM Formatter — This software option reads binary object tapes and produces punched paper tapes (for automatic PROM programmers) and listings that are compatible with MRV11-AA and MRV11-BA applications. 2. Floppy disk software QJ003-AY or QJ003-CY, RT-11 Operating System — This software option includes: EDIT text editor, MACRO assembler (required 12K read/write memory), EXPAND macro expander, ASEMBL assembler, and various system and utility programs. EXPAND and ASEMBL allow program assembly on the basic 8K floppy disk LSI-11 system. RT-11 is a very comprehensive software option and is described in much greater detail in the Microcomputer Handbook, Section 4. ®Teletype is a registered trademark of Teletype Corporation. 3-2 For high-level language program development: 1. FORTRAN QJ925-AY or QJ925-CY - RT-11/FORTRAN 2. BASIC QJ920-AY or QJ920-CY - RT-11/BASIC NOTE The above software options run under the RT-11 operating system. Routines for IBV11-A support for FORTRAN and BASIC are planned options; however, they are not presently available. 3.2 CONFIGURING THE IBV11-A MODULE Each IBV11-A module is factory-configured for standard device register and interrupt vector addresses. Switches S1 (vector address) and S2 (device register) configure the addresses. A summary of register and vector addressing is provided in Figures 3-1 and 3-2. Observe that only the IBS register address is configured. The IBD register address is always the IBS address plus 2. Similarly, only the error interrupt vector address is configured. The remaining three vector addresses are permanently assigned sequential addresses in address increments of four, as follows: Vector Address Error “n”’ (configured address) n+4 n + 10; n + 14 Service Command and Talker Listener Switches S1 and S2 are located on the IBV11-A module as shown in Figure 3-3. S1 and S2 are switch assemblies, each containing several individual switches. The individual switches indicated in Figures 3-1 and 3-2 are clearly marked on the S1 and S2 assemblies. The ON and OFF positions are also clearly marked. IBS REGISTER ADDRESS FORMAT 5 14 13 ' ! ! 12 44 {0 O3 08 O7 06 05 04 03 02 Of 00 0 R B LBYTE POINTER BIT STANDARD ADDRESS CONFIGURATION (160150) OFF ~ OFF ~ OFF OFF ~ OFF OFF ~ ON ON OFF 0:IBS REGISTER ON 1=IBD REGISTER NORMALLY O Le(RESERVED FOR FUTURE S2 INDIVIDUAL | SWITCH NUMBERS | , 2 ] 2 . 1 5 , . . & i g USE) o , o NOTES: 1. OFF = Logical O; ON=Logical 1 2. Only the IBS REGISTER ADDRESS is configured via S2. The IBD REGISTER ADDRESS always equals the IBS REGISTER ADDRESS +2. 11- 4887 Figure 3-1 Configuring the IBV11-A Register Addresses 3-3 5 14 13 {12 0 0 0 o | 44 {0 ©09 o 0 0 STANDARD VECTOR ADDRESS CONFIGURATION (000420) O08 O OFF ©06 OFF 05 OFF 04 03 01 00 o | o ‘ + INTERRUPT VECTOR 0 0 - ERROR 0 ON 02 1 1 + = SERVICE REQUEST O = COMMAND AND TALKER { = LISTENER NOT USED S1_INDIVIDUAL | SWITCH NUMBERS » 3 s 5 6 7 ON =DISABLE ERRI INTERRUPTS 8 (NOTE 3) OFF=NORMAL (ENABLE) ERR1 INTERRUPTS NOTES: 1. OFF = Logical O; ON=Logical 1 2. Only the VECTOR ADDRESS bits (8:4) are configured via Si, Bits 3 and 2 ore IBV1i-A hardware - selected for the functions shown 3. S1-8 OFF=IBVii-A is the only system controlier connected to the instrument bus. S4-2 ON » Ancther system controiler ls connected fp the instrument bus. 11-40888 Figure 3-2 Configuring the IBV11-A Interrupt Vector Addresses 20- PIN . = = | INSTRUMENT BUS —__| o CABLE CONNECTOR U DEVICE ADDRESS SELECT {IBS & IBD REGISTERS) SWITCHES (52) T~ . mim D ale fl a'mWnim B U e U L | L —_— [ 1 7 L 7 L L I I L3 (S1) 3 SEEEe SWITCHES _ 9 1 L [ - - 9 - 9 : : 9 9 9 E 1 nn — o A f l 11-488% Figure 3-3 IBV11 Module Switch Locations 3-5 3.3 INSTALLING IN THE LSI-11 BACKPLANE the same as for IBV11-A module in the LSI-11 backplaned isperiph The general procedure for installing theinstall eral device desire the ine determ e, ing the modul any other peripheral interface. Prior to ter Handb 6, Paraer Chapt and 3, er Chapt 1, n Sectio ook, priority as described in the Microcompu is described 6.4. raph Parag 6, er Chapt I, n Sectio in graph 6.3. Module insertion and removal 3.4 CONNECTING TO EXTERNAL EQUIPMENT A cable as device on the instrument bus is via a type BN11 Connection from the IBV11-A to the first con20-pin a 20-pin connector that mates with the connector shown in Figure 3-4. One end is terminatedendwith terminated with a 24-pin “double-ended” rming nector on the IBV11-A module. The other rd;is the confo cable can be connected to any deviceconne standa that conforms with the IEEE 488-1975 ctor in e 24-pin ctor contains a male 24-pin and a femal to that standard. The double-ended connefor cted conne ments the same connector housing. This allows “linear” and “‘star’’ connections to instru to the instrument bus, as shown in Figure 3-5. | ! JPIN X PIN B —y Figure 3-4 _ BNI11A Instrument Bus Cable The linear. arrangement shown in Figure 3-5 includes five devices (or instruments), A through E. There is nO particular mgmficancg to the sequence shown or electrical position along the instrument bus. Unlike the LSI-11 bus, position along the bus does not structure device priority in the system. The star. arrangement shown in the figure allows five devices to be connected by stacking BNOIA instrument cable connectors on the BN11A’s double-ended connector. Double-ended connectors on instrument bus cables will normally include captive locking screws on each connector assembly (two each), allowing stacked connectors to be secured together in a single assembly. > IBVi1-A | | lDEVICE AI o | | rDEVICE BI | IDEVICE C| | ] EEVICE fl | lDEVlCE E| < LSI-11 BUS BNO1A CABLES LSI-11 BUS D (A) LINEAR ARRANGEMENT DEVICE IBVii-A G E BN11A CABLE o BNOtA CABLES = L DEVICE A DEVICE D — < DEVICE (B) B STAR DEVICE C ARRANGEMENT 11-4891 Figure 3-5 Linear and Star Configurations BN11A and BNOI1A cable connector pin signal assignments are listed in Table 3-1 for each connector. One 4 m (157.5 in) BN11A-04 cable is supplied with each IBV11-A option. Additional BN11A cables are available in the foliowing lengths: Model Length BN11A-01 BN11A-02 BN11A-04 1 m(39.4in) 2m (78.7 in) 4m (157.51n) BNO!A cables are available in the following lengths: Model Length BNO1A-01 BNO1A-02 BNO1A-04 1 m(39.4in) 2m (78.7 in) 4 m (157.51in) 3-7 Table 3-1 BN11A and BNO1A Connector Pin Assignments BN11A (only) BN11A and BNO1A IBV11-A Signal Instrument Bus Connector Pin Name Connector Pin U DI01 1 S P D102 DIO3 2 3 M DI04 4 R T A EOI DAV NRFD 6 X NDAC 8 B IFC 9 J F SRQ ATN 5 7 (SHIELD) 10 11 12 K DIO0S 13 H DI06 14 E DIO7 15 C D DIOS REN 16 17 N GND (DAV GND) GND (NRFD GND) 18 19 GND (NDACGND) GND (IFC GND) GND (SRQ GND) GND (ATN GND) GND (LOGIC) 20 21 22 23 24 A, L 3-8 CHAPTER 4 PROGRAMMING EXAMPLES 4.1 GENERAL ‘This chapter contains two programming examples that illustrate how the LSI-11 system can commu- nicate with instruments via the IBV11-A. No attempt is made to restrict these programming examples to specific devices. Refer to programming instructions included with the programmable instruments for specific procedures, including codes (ASCII characters) for device addressing, setting modes, ranges, etc. LSI-11 program listings, flowcharts, memory maps, and detailed descriptions are included for each exampie. Both programming examples have been executed on an LSI-11 system. The programs were entered manually via the console terminal using console ODT commands. In an actual applications environment, however, routines, similar to these programming examples, would function as parts of a larger program. Additional features, such as the ability to enter instrument parameters directly from the console keyboard and display processed results would be incorporated. No attempt is made in these examples to illustrate those features since each application, available hardware, and programmer’s skill will vary. However, the examples do illustrate how the IBV11-A can be programmed to perform useful tasks. 4.2 4.2.1 EXAMPLE 1 - IBV11-A TO LISTENER DEVICE General This programming example illustrates how the IBV11-A communicates with a listener device. Standard device and vector addresses are used, as shown in Figures 3-1 and 3-2. Once the program is started, and after pointers have been initialized and the IBV11-A has taken control synchronously, the program communicates with the IBV11-A via an interrupt-driven service routine. No “background” program is used; the program simply “waits” until another interrupt occurs. Communication with the listener device includes the transmission of 2 command bytes (read as words from a message buffer), followed by 24 message bytes that program device functions. After all message bytes have been transmitted, the program halts (displayed HALT PC address = 1066). A program flowchart for this example is shown in Figure 4-1, and a symbolic listing is shown in Figure 4-2. Figure 4-3 is a memory map for the program. Refer to those figures when reading the description of program operation in the following paragraphs. 4-1 TAKE CONTROL SYNCHRONOUSLY ¥ commk NO TO BE SENT IS TALKER SET: NO } ACTIVE IE, REM, TCS SET: IE, TON, REM ] MORE MSG TO BE NO SENT =D SEND MSG T | 11-5231 Figure 4-1 Example 1, Communicating with a Listener Device Program Flowchart 4-2 OCTAL ADTRESS ASSEMBLER CODE SYNTAX CUOMMENTS Q01020 g INTR 000200 7 FSW 001000 012706 001062 0003500 3 START: MOV #500sRé SET RO MOV #2000 RO MOV TaRE RETURN UF IS ALDRESS STACK MSG FOINTER BUFFER ADDRESS 001004 012700 301006 002000 001010 001012 000110 CONTROL SYNCHRONOUSLY 001014 1460150 CONTROLLER~IN-CHARGE 001016 QOO777 001020 Q22700 01022 001024 002004 #110:16015 WalT FOR CMF #2004 RO MORE COMMANDS 100006 BFL 20% B Q12737 IF NOGD 001024 012737 MOV 105, 160150 Q01030 Q01032 Q00105 001034 Q12037 001034 160152 001040 Q00002 160150 YESSET BITS OF IRS SEND MSG TO IR B> ACCERTED B BE CMF RO F2004, IS Q03003 BGT J0% Q01050 o010G2 012737 000144 MOV #144,1601350 001054 160150 001054 022700 CMF #2062 RU 001060 002062 Q01062 100364 BMI SEND IF OTHERWISE Q02004 001046 Q01064 083 000000 HALT GCTIVE® YES,GOD TO 19 001044 2 20% IF PAECTNNEY D22700 TALKER OTHERWISE SET IETON ANDI REM BITS 0OF IRS REG TR 001042 TO TO OR WAIT~F M5G RTI REG TO RETURN ‘ar +» 160152y SENTT ITEREMeAND ACTIVATE CONTROLLER L TR (RO RE 20% IF e MOV TO TO TCS -y S5ENDZ RECOME INTERRUFT Nr . Wy BR By WATT: TO TO ACTIVATE HaD ALl MSG NOGO 30% TALKER BEEN SENT? SEND ANOTHER STOF MSG 11-5232 Figure 4-2 Example 1, Communicating with a Listener Device Program Listing 4-3 R6 (SP) 500 — IBV11-A TKR/CMD gl [=] < 1 { INTERRUPT VECTOR PC & PS 430 PC = 1020 432 PS = 200 \/ '\__/ 1000 PROGRAM 1064 \__/ RO (MSG BFFR PTR) B 2000 }—0pn [ 2000 UNL COMMAND SET-UP DEVICE MLA COMMAND LISTEN ADDRESS SET-UP MESSAGE OPERATING BUFFER ” PARAMETERS (MODE, FREQUENCY, AMPLITUDE) - 2062 HIGHEST MEMORY LOCATION 11-5233 Figure 4-3 Memory Map for Example | 4-4 4.2.2 Program Operation Prior to starting the program, it is assumed that interrupts are enabled (PS bit 07 = 0). The program is started at address 1000. The first MOV instruction (at location 1000) initializes the stack pointer (R6) to 500. Note that this address is first decremented by two each time a new item is “pushed” onto the stack in the usual manner; the content of R6 always points to the address of the last word pushed onto the stack. Conversely, R6 is incremented after “popping” a word from the stack. In this programming example, the stack is used for servicing the IBV11-A’s interrupt requests; the interrupts will always occur while executing the *““wait” (BR.) instruction at location 1016. Thus, the PC pushed onto the stack for this example is 1016, followed by the PS. These two words are popped from the stack to restore the wait instruction by executing the RTI instruction at location 1040. The next MOV instruction (at location 1004) initializes RO to 2000 for use as a message buffer address pointer. The number of messages sent, and hence, the actual size of the message buffer, is dependent on the requirements of the instrument being programmed. In this example, 26,0 locations are reserved for the message buffer. This means that the message buffer’s last address is 2062. During program execution, the CMP instruction at location 1056 tests RO to determine if all locations of the message buffer have been transmitted to the addressed listener device. The MOY instruction at iocation 1010 sets the IBV11-A’s IBS register IE and IBC bits (bits 06 and 03). The IBV11-A responds by generating a 125 us IFC pulse, followed by ““taking control synchronously.” Once this operation is completed, the IBS CMD bit becomes set and the IBV11-A’s TKR or CMD interrupt request is enabled. The vector address for this interrupt is 430 [the configured address (420s) + 10s]. The BR. (“branch to self”’) instruction at location 1016 causes the program to “hang” (or wait) until the interrupt occurs. The processor services the interrupt by pushing the previous PC and PS onto the stack and uses the new PC (contents of location 430 = 1020) and PS (contents of location 432 = 200) for the interrupt-driven routine; interrupts are disabled by the new PS. In this example, the first two words in the message buffer are commands [UNL (unlisten) and MLA (my listen address ““n’’)]. The CMP instruction at location 1020 tests if the two commands have been sent. Initially, RO = 2000; executing the CMP and BPL instructions results in executing the MOV instruction at location 1026. The MOYV instruction sets IBS IE, REM, and TCS bits to activate the IBV1I1-A as the controller-in-charge. The MOY instruction at location 1034 is then executed, transmitting the first command byte to the instrument bus via the low byte of the IBV11-A’s IBD register (device address 160152). Note that RO is auto-incremented after it is used, causing it to point to the next command in the message buffer. The RTI instruction at location 1040 is then executed, causing the program to return to the BR. instruction at location 1016, and the program waits for the next interrupt. When the interrupt occurs, it indicates that the command transfer over the instrument bus has been completed. The second command is then transmitted in exactly the same manner. However, note that the message buffer pointer content of R0 is now 2004, and no more commands are to be sent. When the next interrupt occurs, the CMP and BPL instructions following WAIT cause the program to branch to 208 (location 1042). Since the content of RO = 2004 at this point of program execution, the branch (BGT) at location 1046 will not be executed; instead, the MOV instruction at location 1050 is executed, setting IBS register bits IE, TON, and REM, and the IBV11-A becomes an active talker. 4-5 Message bytes are now sequentially sent to the listener via the low byte of the IBV11-A’s IBD register, functioning as a talker on the instrument bus. The CMP instruction at location 1062 first checks if all message bytes have been transmitted. If more bytes are to be transmitted, the BMI instruction causes the program to branch to SEND. A word is then transmitted to the IBD register and the program exits to WAIT until another interrupt occurs; the content of R0 is now 2006. When the interrupt occurs, CMP and BPL instructions cause the program to branch to 20$. Since RO now contains a message buffer pointer greater than 2004, the CMP and BGT instructions cause the program to branch to 308S. The program then checks if the last message buffer word has been transmitted. If not, the program branches to SEND, another message byte is transmitted, etc., until all messages have been transmitted. When all messages have been transmitted, the content of R0 will be 2064. The CMP and BMI instructions (following 308) will then result in the HALT instruction at location 1064 being executed, and the program execution is completed. The instrument will then operate according to the com- mand/program data received over the instrument bus. 4.3 EXAMPLE 2 - IBV11-A TO TALKER DEVICE 4.3.1 General | This programming example illustrates how the IBV11-A communicates with a talker device. As in example 1, this programming example assumes standard IBV11-A device and interrupt vector address- es. Communication between the instrument and the LSI-11 system is via IBV11-A interrupt-driven service routines. No background program is used; the program simply “waits” until another interrupt occurs. Communication with the instrument involves first transmitting the content of the command message buffer, in a manner similar to the program operation described for example 1, followed by accepting instrument output data and storing it in a received data buffer. The content of the command message buffer typically includes first activating the device via its listen address, followed by setting up range, mode, etc. operating parameters for the instrument, an execute command, and, finally, activating the device as an active talker via its talker address. Once the device has received the command message buffer data, it performs the programmed measurements (or the function, depending on the instrument) and returns data to the LSI-11 system via the IBV11-A; note that during this portion of program operation, the IBV11-A functions as an active listener on the instrument bus. Once all measurements have been stored by the program, the program halts with a displayed PC address = 1102. A program flowchart for this example is shown in Figure 4-4 and a symbolic program listing is shown in Figure 4-5. Figure 4-6 is a memory map for the program. Refer to those figures when reading the description of program operation in the following paragraphs. 4.3.2 Program Operation The program is started at location 1000. Prior to starting the program, it is assumed that interrupts are enabled (PS bit 07 = 0) and the program and interrupt vector code has been loaded into system memory as shown in Figure 4-5. The first four MOV instructions set up the stack pointer, initialize the command message and received data buffer pointers RO and R1, respectively, and cause the IBV11-A to take control synchronously. The program portion starting at WAIT (location 1022) through the RTI instruction at location 1044 outputs the command message buffer in a manner similar to that described for example 1. 4-6 &=D TAKE CONTROL SYNCHRONOUSLY COMMAND NO TO BE SENT SET: ACC, iE, LON SEND MSG TO 1B TRANSFER MSG TO R1 ISSUE uDACu TO B ISSUE “DAC” TOIB C=D 11-5234 lowchart 11 Program COMMENTS HYNTAX COMMAND/ TALRKER RETURN FSW NS QOL024 WY ASHEMEBLER CODE ]y ADRESS YRR e AHURESSH [ E g MOV #500sRé& v SET MOY RO #2000 s ITRVLIL~& 0132701 MOV F2E00R1 v BUFF FOR Q01014 012737 MOV 110160150 RS RETURN LISTENER TAKE CONTROL 010146 QO1020 000110 |r QGGR00 INTR ADDRESS TO BECDME CONTROLLER» C~ 1+ IN-CHARGE QOI102S QOO777 Q01024 12737 QOLO24 Q0Q10% QOLO30 001032 QA2700 QOLONE QOGIO6 140150 QG1LO34 0010G3d Q1040 QL2037 A QOGO0E C 204 +» 160152 (RO MOV #3200 160150 MB0 SEND OTHERWISE RETURN TO WATT~FUR MSG TO BE ACCEFTED ITBVLL A TO CONTROLLER TO LISTENER WAIT-- RETURN FOR SAVE MGl TS fi "" {.-# IR Ay ' \%. ¥L ar.? wd 'q‘ "\} 'g‘ G0L403 HEQ 30% Halt 20 0CTaAL Misla BEEN aCCERTEDT IF YES.G0 TO 30% QOH0O3Y7 CLK 160152 RTI MOV 013721 01060 160152 GULO6L GA2701 QOLOG4 RDO2HA0 DOLO&E DGLOG70 1460152 QO1074 DOAOOZ Q01076 QQEO37 Q01100 QOOGR0 (R1D+ RTI 160152 = CLR HALT RECETVED THE IN R e RETURN -1 A0% 3 M5S0 M OTHERWISE 3 QOLOY72 160152 R LN BT BEQ MOV ey ‘;:' HAD ALL COMMANDS BEEN SENT? IF YES»G0 TO 204% FA024 5RO R i MESSAGES -+ QOOB20 1460150 COMMAND RN 201050 Q1062 3 20% SEND TC CMF RTI INTERRUFT FREFARE W QL2737 #1055 1460150 Y DOLOA4 WATT=-FOR . MSG SYNCHRONDUSLY Gk 160152 QOO002 RECEIVED S Q01042 e BR MOV Q01404 Q01044 e WATT: 160150 Q2024 Q01054 R Qo1012 T 002000 QO101Q RUFFER M5G SR QGLOGSE STACK a1l Q12700 UF - 001004 START: 3 GOOLCD § QL2706 QOLOOY b+ GG1G00 1 (-1 TGO 195UE IKFSTTM WAIT-—~FOK ANOTHER MM MED ITSSUE DAC TO IR STOF»20 MSG RECEIVED 11-5235 Figure 4-5 Example 2, Communicating with a Talker Device Program Listing 4-8 R6 (SP) L STACK 500 1———» 500 \/ 1IBV11-A TKR/CMD 430 PC = 1024 INTERRUPT VECTOR PC & PS 432 PS= 200 IBV11-A LNR 434 PC = 1056 INTERRUPT VECTOR PC & P PS 436 Po—— w RO CMD MSG BFFR PTR) L 2000 ]-—> [ 2000 UNL COMMAND SET-UP DEVICE MLA COMMAND LISTEN ADDR COMMAND SET-UP MESSAGE OPERATING BUFFER PARAMETERS, ’\/ R1 (DATA BFFR PTR) | 2500 |—— ( 2500 TALKER ADDRESS & EXECUTE COMMAND T — RECEIVED DATA < BUFFER \_—/ \/ _ 2540 v HIGHEST MEMORY EMOR LOCATION 11-5236 Figure 4-6 Memory Map for Example 2 4-9 When all command bytes have been transmitted to the addressed device, the program branches to 20$ (location 1046) and the MOV instruction at that address causes the IBV11-A to become an active listener. This is followed by an RTI instruction and the program waits for the IBV11-A’s listener (LNR) interrupt to occur. When the interrupt occurs, the IBV11-A’s IBD register, which contains the first measurement data word (byte), is read and stored in the first received data buffer location (2500); note that the received data buffer pointer (content of R1) is incremented by two (one word address) each time the IBD register is read. The CMP and BEQ instructions that follow test if all 16,, data words have been received. If not, the RTI instruction returns the program to WAIT until the next IBV11-A LNR interrupt occurs. Operation continues in this manner until all data transfers have been stored in the received data buffer. When the last buffer location has been filled, R1 contains 2540s, the last address in the received data buffer. Executing the CMP instruction (location 1062) and BEQ instruction results in the program branching to 303 (location 1076). Operation is then terminated by first clearing the IBD register; the IBD responds by asserting DAC to complete the data transfer from the instrument to the IBV11-A’s IBD register. Finally, the program executes the HALT instruction and the operation is completed. | The data contained in the received data buffer is device-dependent for its actual significance. In a typical application, the HALT could be replaced by a branch (BR) or jump (JMP) instruction to transfer control to a program that processes the received data. 4-10 CHAPTER 5 TECHNICAL DESCRIPTION 5.1 GENERAL The functional logic blocks that comprise the IBV11-A are shown in Figure 5-1. LSI-11 software controls and communicates with the IBV11-A via programmed 1/O transfers and interrupts. Refer to the Microcomputer Handbook, Section 1, Chapter 3 for a complete description of LSI-11 bus cycles, including DATO, DATOB, DATI, DATIO, DATIOB, and interrupt transactions. 5.2 DEVICE REGISTERS Programmed 1/O transfers are made possible by assigning unique device addresses (also called ““bus addresses’) to the IBS and IBD registers. The IBS register is the instrument bus status register; it is generally similar in function to other PDP-11 device control /status registers (CSRs). The IBD register is the instrument bus data register. It is a 16-bit register that contains eight read /write data bits in the low byte and eight read-only bits in the high byte. The eight read-only bits allow the program to read the logical state of the instrument bus. Functions of bits in the IBS and IBD registers are described in Paragraph 2.2.4. 5.3 LSI-11 BUS INTERFACE LSI-11 bus address selection, interrupt vector address generation, and bus data driver/receiver (transceiver) functions are provided by transceiver integrated circuits (DC005). Each integrated circuit provides the interface for four BDAL bus lines; thus, four transceivers comprise the 16-line BDAL <00:15> L LSI-11 bus interface. Refer to Appendix A for a detailed description of the DC005 transceiver integrated circuit. ' Device address switches provide a convenient means for the user to configure the IBV11-A’s register addresses. Only switches corresponding to BDAL lines <03:12> are provided. By PDP-11 convention, the upper 4K address space (bank 7) is normally reserved for peripheral devices, such as the IBV11-A. The LSI-11 processor module asserts BBS7 L whenever a bank 7 address (BDAL <13:15> L are asserted) is placed on the bus. Thus, BBS7 L must be asserted to enable an ‘““address match” output from the address selection function. Any address ranging from 16000X to 17777X can be configured, as long as it does not conflict with other device addresses within the system; the X in the address represents register and byte selection within the module. The preferred addresses (for DEC software compatibility) are: IBS = 160150 IBD = 160152 Bit 1 of the least significant octal digit selects the IBS or IBD register. The least significant bit (BDAL 0) is a byte pointer and it is significant for DATOB and DATIOB bus cycles only. Register address selection is actually performed in the LSI-11 bus protocol and register selection function; the transceiver integrated circuit simply routes the received low-order three address bits (DA <2:0>) to that function. | 5-1 A\ «~SRPLY L SYNC B L 8, o LOAD IBS W BYTE LSI-11 BUS Srore S BwrBl L BDOUT L REGISTER BDIN SELECTION & L (DCOB4) SELECT 55 DA <7:0> c ‘C"K DAIS SRQ LK CONTROL BUFFER \ T | ASSERT e 125us ONE ke ) SRQ D-FLOP | SRQ LOAD IBD, oW BYTE ——————» I8C SRQ L IFC L ENABLE z IE i—. So =N DEVICE | > SWITCH @ ADDRESS O CMD__OR| w I S CTL BUS DEVICE BBS7 L BUS LSI-11 VECTOR | pats B [ ERR| - DETECTION EOP | TAKE ) SELECTION VECTOR DATA I/0 DA <15:00> y 2 8Foof §5 - (DCOO5) T : 1514131211109 8 | IBS[ GENERATION INTERFACE REN L REM ERROR SRQ INTERRUPT | pa <7.0> BDAL <15:00> ATN DAV SWITCH CONTROL ADDRESS » _ . INTERRUPT < LSI-11 TKR LNR 54 32 1 HANDSHAKE |gATN INTERFACE = 2 2 DAV L _ J Y - DAV g CONTROL | PRLY i |BuB382382 HANDSHAKE [, DAC MULTIPLEXER | e L - NRFD L >l| 0 SYNC O 2 & CONTROL | NRFD RRRRRRRR | WWWWWW WW R 16, REGISTER 76 ATN BUS CONTROL NDAC L RFD 7 A - |._. St VECTOR o ADDRESS A SA<E: 4> o| N SELECT g0 18S SWITeh T W E 1514131211109 8 | 7654 3 2 1 0 1ep| B ELE8222 | 85883885 L RRRRRRRR|WWWWWWWW W g — -~ &0 &aa P H H H A H M M - — I ‘6 e R <« BIRA L BIAKI BIAKO L L LOAD IBD LSI-11 BUS |aZINTRCTL LOW BYTE INTERRUPT INTERFACE (DCO03) BUS I8 <16:1> RECEIVERS . BINIT L BDIN L INSTRUMENT 4—— > | INTT y oA <7:0> ' ‘ (CLK) cormgND TALKER ouTPUT BUFFER . y INSTRUMENT DAT%“EINE DIO <8:1> L DRIVERS 11 - 4897 Figure 5-1 IBV11-A Functional Block Diagram 5-3 All 1/O transfers over the LSI-11 bus are done according to a strict protocol. One bus protocol integrated circuit (DC004) performs this function and the register address selection previously discussed. When an active ADDRESS MATCH signal is present on the leading edge of the BSYNC L signal, the bus protocol integrated circuit is enabled to complete its register selection function. BWTBT L, BDOUT L, and BDIN L bus signals are decoded in the integrated circuit, as appropriate, to produce the LOAD IBS LOW BYTE, SELECT IBS, LOAD IBD LOW BYTE, and RECEIVE internal control signals for the IBV11-A logic functions. The integrated circuit also asserts BRPLY L as required during the 1/0 sequence to complete the programmed transfer. Refer to Appendix A for a detailed description of the DCO004 integrated circuit. Interrupts are generated by one interrupt integrated circuit (DC003). Four vector addresses can be generated by this LSI-11 bus interrupt interface function. A 5-bit vector address switch allows the user to select the lowest vector address for the IBV11-A module. The preferred lowest IBV11-A vector address is 420. IBV11-A vector addresses can range from 0 to 774; however, they must not conflict with other LSI-11 bus device and reserved system vectors. The error vector always has the lowest address; this is the actual address configured by the user. The remaining three vector addresses are relative to the error vector address. For example, the preferred vector address (420) selection produces the following vector addresses: Address 000420 000424 000430 000434 IBV11-A Interrupt Vector Error Service request Command and talker Listener These vector addresses allow the IBV11-A to generate interrupts that can most efficiently be serviced by four separate service routines. Each vector address points to a pair of locations in system memory containing the PC and PS words for the interrupt service routine. For example, an IBV11-A service request interrupt request, when acknowledged by the processor, will be serviced by the 000424 vector address as follows: System Memory Location Contents 000424 Service Routine PC word 000426 (starting address) Service Routine PS word Interrupt and vector control logic on the IBV11-A module generates the INTR CTL signals that initiate the interrupts. Inputs for this logic function include the interrupt enable (IE) IBS bit (stored in the control buffer), command or talker (CMD or TKR) and listener (LNR) ready flags, error (ERR) status from the error detection logic, and the device service request (instrument bus control signal). Refer to Appendix A for a detailed description of the DC003 interrupt logic integrated circuit. 5.4 INSTRUMENT BUS CONTROL The control buffer is an 8-bit register that functions as the low byte of the IBS register. Bits stored in this register control generation of interrupts, instrument bus clear, and instrument bus control and status logic. Setting the IBC bit actually triggers a one-shot producing a 125 us pulse that clears the instrument bus. Take control sync and handshake control logic function together with instrument bus control and handshake interface logic to communicate with instruments on the bus according to instrument bus protocol. LSI-11 output transactions with the low byte of the IBD register result in data being stored in the 8-bit command and talker output buffer. Instrument bus line drivers gate this byte onto the instrument bus when the IBV11-A is an active talker or when it is an active controller. 5-4 5.5 INSTRUMENT BUS INTERFACE The IBV11-A interfaces with the instrument bus via four MC3441 integrated circuits. These integrated circuits are bus transceivers, each containing four bus drivers, four bus receivers, and bus terminations that comply with instrument bus specifications. 5-5 CHAPTER 6 MAINTENANCE 6.1 GENERAL Maintenance for the IBV11-A involves executing a diagnostic program and, if required, repairing the module. As a general rule, the user should first check that the IBV11-A is properly installed as described in Chapter 3. If the module appears to be properly installed (address and interrupt vector switches are properly set, and no unoccupied device locations are located in the backplane between the IBV11-A and the LSI-11 processor module), confirm the operational status of the module by executing the IBVii-A’s diagnostic program. 6.2 IBV11-A DIAGNOSTIC SOFTWARE IBV11-A diagnostic software (MAINDEC-11-DVIBA) includes a diagnostic program tape and a program listing. Detailed operating instructions are included in the listing. In order to completely test the IBVII-A option, a second “known good” IBV11-A module and BN11A instrument bus interface cable are required. If those items are not available, the program will allow tests to be run on those IBV11-A functions that do not require the second module. Minimum hardware requirements for running diagnostics include the basic LSI-11 system, including 4K read/write memory (minimum), a console terminal, the IBV11-A to be tested, and a paper tape reader. A second IBV11-A (known functional) module and two BN11A cables will allow full use of the diagnostic program. Refer to the Microcomputer Handbook, Section 1, Paragraph 9.3 for general instructions for using paper tape diagnostics. 6.3 DIGITAL SERVICES Maintenance services can be performed by the user or by DIGITAL, as desired. DIGITAL'’s services are described in the Microcomputer Handbook, Section 5, Chapter 3. 6-1 APPENDIX A IC DESCRIPTIONS A.1 DC003 INTERRUPT LOGIC The interrupt chip is an 18-pin, 0.300-inch center, DIP device that provides the circuits to perform an interrupt transaction in a computer system that uses a ‘“pass-the-pulse” type arbitration scheme. The device is used in peripheral interfaces and provides two interrupt channels labeled “A’ and “B,” with the A section at a higher priority than the B section. Bus signals use high-impedance input circuits or high-drive open collector outputs, which allow the device to directly attach to the computer systems bus. Maximum current required from the V. supply is 140 mA. Figure A-1 is a simplified logic diagram of the DC003 IC. Figure A-2 shows the timing for the “A” interrupt section, while Figure A-3 shows the timing for both “A” and *“B”’ interrupt sections. Table A-1 describes the signals and pins of the DC003 by pin and signal name. A.2 DC004 PROTOCOL LOGIC The protocol chip is a 20-pin, 0.300-inch center, DIP device that functions as a register selector, providing the signals necessary to control data flow into and out of up to four word registers (8 bytes). Bus signals can directly attach to the device because receivers and drivers are provided on the chip. An RC delay circuit is provided to slow the response of the peripheral interface to data transfer requests. The circuit is designed such that if tight tolerance is not required, then only an external 1K £20 percent resistor is necessary. External RCs can be added to vary the delay. Maximum current required from the V¢ supply is 120 mA. Figure A-4 is a simplified logic diagram of the DC004 IC. Signal timing with respect to different loads is shown in Table A-2 and in Figure A-5. Figure A-6 shows the loading for the test conditions in Table A-2. Signal and pin definitions for the DC004 are presented in Table A-3. A.3 DCO005 TRANSCEIVER LOGIC The 4-bit transceiver is a 20-pin, 0.300-inch center, DIP, low-power Schottky device; its primary use is in peripheral device interfaces, functioning as a bidirectional buffer between a data bus and peripheral device logic. In addition to the isolation function, the device also provides a comparison circuit for address selection and a constant generator, useful for interrupt vector addresses. The bus I/O port provides high-impedance inputs and high-drive (70 mA) open collector outputs to allow direct connection to a computer’s data bus structure. On the peripheral device side, a bidirectional port is also provided, with standard TTL inputs and 20 mA 3-state drivers. Data on this port is the logical inversion of the data on the bus side. Three address jumper inputs are used to compare against three bus inputs and to generate the signal MATCH. The MATCH output is open collector, which allows the output of several transceivers to be wire-ANDded to form a composite address match signal. The address jumpers can also be put into a third logical state that disconnects that jumper from the address match, allowing for *“‘don’t care” address bits. In addition to the three address jumper inputs, a fourth high-impedance input line is used to enable/disable the MATCH output. Three vector jumper inputs are used to generate a constant that can be passed to the computer bus. The three inputs directly drive three of the bus lines, overriding the action of the control lines. Two control signals are decoded to give three operational states: receive data, transmit data, and disable. Maximum current required from the V¢ supply is 100 mA. Figure A-7 is a simplified logic diagram of the DCO005 IC. Timing for the various functions is shown in Figure A-8. Signal and pin definitions for the DCO005 are presented in Table A-4. A-2 +vec—1g| +Vvee [i6]enasT H ROSTA H [17}— s SET ENADATA H [I5}——p 1 ENACLK H [1a}———c 14 L] = B VECTOR HOJ1 SN CLRO N CLR 5 0 VECRQSTB H 2 b 1 L o ar BDIN L O3 __DF INITO L G4 18Pvce 173RQSTA H 161 ENAST H 15[ ENADATA H BINIT L ds PCO03 14 ENACLK H — BIAKO | B4 L6 BIAKI LO7 o BIAKI L [o7}— — -~ BIRQ 130 ENBCLK H 12 ENBDATA H L8 11 ENBST H GND 19 10B RQSTB H :{> BINIT L |O5] -}- :D° @BIAKO L | BOIN L @_c{> _D° 03] s1RQ L ; ENBDATA H [12}——D T — VECTOR H o) oo SET il— 1 ENBCLK H >CCLR0 {it] EnesT H <{> +VCC zg ~—\ e CLR o N o \ _D_ .> ’ 0 02| VECRQSTB H &z +vee RQSTB H [i0} bel—ano ' S CLR T 1K [oq] InITO L IC-0173 Figure A-1 DCO003 Simplified Logic Diagram A-3 BINIT L 300 [300! ‘MIN I MIN | | 1 17-35 H INITO L —=f ]:_l : | | | ENA DATA H ENA CLK H ENA ST H ~ l ] 30 MIN—»{ m I | | ] ] 7-30—’: [‘— I l RQSTA H BIRQ L l l 15-65 —» —»l 20-90 BDIN L I BIAKI L I 35 MIN—>= ‘4——1 35 MIN—F: I ! I: | ] { VECTOR H 10-45—»! > | BIAKO L 10-45 12-55 —» liF—iz—ss 1 i NOTE: Times are in nanoseconds 11- 4150 Figure A-2 DCO003 “A” Interrupt Section Timing Diagram A-5 1 ] f INITO L 7-355-1_;':!12;50 | i f ] I ENB DATA H I | l ENB CLK H ENB STH BIRQ L RQSTB H ENA DATA H [ 30 MIN —’! I 7-30—»: Io— ENA CLKH 20 MIN — I: i I | L ENA ST H RQSTA H B DIN L BIAKI L 1 1 VECTOR H | 1o-45-l ':l 10-45 1 I 10-451..|Tl-10_-1_ i | VECRQSTB H | 1 { NOTE: Times are in nanoseconds 11-4151 Figure A-3 DCO003 “A” and “B” Interrupt Sections Timing Diagrams Table A-1 Pin DCO003 Pin/Signal Descriptions Description Signal VECTOR H INTERRUPT VECTOR GATING SIGNAL. This signal should be used to gate the appropriate vector address onto the bus and to form the bus signal called BRPLY L. VEC RQSTB H VECTOR REQUEST “B” SIGNAL. When asserted indicates RQST “B” service vector address is required. When unasserted indicates RQST “‘A” service vector address is required. VECTOR H is the gating signal for the entire vector address: VEC RQST B H is normally bit 2 of the vector address. BDIN L BUS DATA IN. This signal generated by the processor BDIN always preceeds a BIAK signal. INITOL INITIALIZE OUT signal. This is the buffered BINIT L signal used in the device interface for general initialization. BINIT L BUS INITIALIZE signal. When asserted, this signal brings all driven lines to their unasserted state (except INITO L). BIAKO L BUS INTERRUPT ACKNOWLEDGE signal (OUT). This signal is the daisy-chained signal that is passed by all devices not requesting interrupt service (see BIAKI L). Once passed by a device, it must remain passed until a new BIAKI L is generated. BIAKI L BUS INTERRUPT ACKNOWLEDGE signal (IN). This signal is the processor’s response to BIRQ L true. This signal is daisy-chained such that the first requesting device blocks the signal propagation while non-requesting devices pass the signal on as BIAKO L to the next device in the chain. The leading edge of BIAKI L causes BIRQ L to be unasserted by the requesting device. BIRQL ASYNCHRONOUS BUS INTERRUPT REQUEST from a device needing interrupt service. The request is generated by a true RQST signal along with the associated true interrupt enable signal. The request is removed after the acceptance of the BDIN L signal and on the leading edge of the BIAKI L signal or the removal of the associated interrupt enable or due to the removal of the associated request signal. 10 REQSTB H 17 REQSTA H DEVICE INTERRUPT REQUEST SIGNAL. When asserted with the enable “A” flip-flop asserted will cause the assertion of BIRQ L on the bus. This signal line normally remains asserted until the request is serviced. A-7 Table A-1 Pin 11 16 Signal ENB STH ENA ST H DCO003 Pin/Signal Descriptions (Cont) Description INTERRUPT ENABLE “A” STATUS signal. This signal indicates the state of the interrupt enable ““A” internal flip-flop whichis controlled by the signal line ENA DATA H and the ENA CLK H clock line. 12 15 ENB DATA H ENA DATA H INTERRUPT ENABLE “A” DATA signal. The level on this line, in conjunction with the ENA CLK H signal, determines the state of the internal interrupt enable ““A” flip-flop. The output of this flip-flop is monitored by the ENA ST H signal. 13 ENBCLKH INTERRUPT ENABLE “A” CLOCK. When asserted (on the 14 ENA CLK H positive edge), interrupt enable “A” flip-flop assumes the state of the ENA DATA H signal line. VECTOR H 1 20pQ vce BOAL2 L 2 1903 ENB H BDALI L O3 183 RXCX H 8DALO L 4 BWTBT L OJ5 170 SEL6 L 160 SEL4 L BsYNC L Oe P€00% 1sh seL2 L BDINL Q7 140 SELO L BOOUT L o 129 ouTLB L BRPLY L 8 6ND g1o 138 OUTHB L 111 INWD L [—-\w—- +VvCC Ene H [i9} 0! vee LATCH r— BDAL2 L @L SYNC 00 1 LATCH G A O DAL 2 DECODER 0 7] SEL6 L SEL4 L 8oAL1 L [03 D o—15] LATCH G B0ALO L [04] O DAL 1 seL2L SELOL i B LATCH BWTBT L @—QD G O E { ) BoouT L @ E OUTLB L —{18] ’ Rxcx H 08} | BRPLY L @ VECTOR H INWD L IC-0174 Figure A-4 DC004 Simplified Logic Diagram A-9 Table A-2 DCO004 Signal Timing vs Qutput Loading With Signal Respect to Signal Test Cond. Output Output Max Min OUTLB L OUTHB L INWD L BSYNC L BDOUT L DBOUT L BDIN L. - Max Min (ns) (ns) SEL (0,2,4,6) L Fig. A-5 Ref. Being Asserted Being Asserted ts, tg Load B 15 35 S 25 Load C 15 40 5 30 Load B 5 25 5 25 Load C 5 30 5 30 Load B 5 25 5 25 Load C 5 30 5 30 Load A 5 25 5 25 Load B 5 30 5 30 20 60 -10 45 t13. 114 20 60 -10 45 foat 14 13> 20 60 -10 45 t13, ti4 tg, t10 tg, t1g t1]> t1o Pin 18 BRPLY L OUTLBL Connection (Load A) (Load B) BRPLY L OUTHB L (Load A) (Load B) BRPLY L INWD L (Load A) (Load B) BRPLY L VECTOR H 30 70 0 45 t13,t14 OUTLB L 300 400 -10 45 t13> t14 300 400 -10 45 t13 t14 RX = 1K 5% 35082 £5% 15 pf £5% (Load A) Pin 18 Connection BRPLY L A Load B Load RX = 4.64K 17 | (024 A) (Load B) (Load A) (Load B) BRPLY L OQUTHB L A-11 Table A-2 DCO0004 Signal Timing vs Output Loading (Cont) With Respect Signal to Output Signal Output Test Being Being Fig. A-5 Cond. Asserted Asserted Ref. Min Max Min (ns) CX=220pf+1% | BRPLY L INWD L (Load A) (Load B) BRPLY L VECTOR H Max (ns) 300 400 -10 45 t13,t14 330 430 0 45 t13, t14 (Load A) A-13 4L B8DAL (2,1,0) L %//AZS MlNIZS MINV/////////////////////I BSYNC L ] ] I SEL (0,2,4,6) L :-rs*L o[ ] OUTHB L |e— 1S MIN. e Yy T R 1 | . | OUTLB L — TSk— -—>: T‘IOI:— 8OIN L —%Tfifi— l— i IWD L . ~— 15 MIN.—> - | ] BDOUT L N R e | I —--: T12 ] ] | "": T8 A=, Ly _.:713k_ BRPLY L | | ] VECTOR H | l l i : - % ] | ] (L 1 1] | | Ry Cx H | | —iT15 ——{nsl‘— ] * TIME REQUIRED TO DISCHARGE R, Cy, FROM ANY CONDITION ASSERTED =150ns : NOTE Times are in nancseconds f1-4348 DC004 Timing Diagram s o ) o o O < < Figure A-5 %GOQ FROM OUTPUT 7 J_ T %280.0. ° 200 pF l‘ LOAD FROM CUTPUT 7 L TM < 15pF T = A FROM OUTPUT 7 i LOAD B DIODE - —l_ T rwrri 150pF J = LOAD C 11-4349 Figure A-6 DC004 Loading Configurations for Table A-2 A-15 Table A-3 DC004 Pin/Signal Descriptions Pin Signal 1 VECTOR H VECTOR. This input causes BRPLY L to be generated through the delay circuit. Independent of BSYNC L and ENB H. 2 3 BDAL2 L BDALI L BUS DATA ADDRESS LINES. These signals are latched at the assert edge of BSYNC L. Lines 2 and 1 are decoded for the 4 BDALOL 5 BWTBT L 6 Description select outputs; line O is used for byte selection. BUS WRITE/BYTE. While the BDOUT L input is asserted, ' this signal indicates a byte or word operation: Asserted = byte. unasserted = word. Decoded with B OUT L and latched BDALO L to form OUTLB L and OUTHB L. BSYNC L BUS SYNCHRONIZE. At the assert edge of this signal, address information is trapped in four latches. While unasserted, disables all outputs except the vector term of BRPLY L. 7 BDIN L BUS DATA IN. This is a strobing signal to effect a data input transaction. Generates BRPLY L through the delay circuit and INWD L. 8 BRPLY L BUS REPLY. This signal is generated through an RC delay by VECTOR H, and strobed by BDIN L or BDOUT L, and BSYNC L and latched ENB H. 9 BDOUT L BUS DATA OUT. This is a strobing signal to effect a data output transaction. Decoded with BWTBT L and BDALO to form OUTLB L and OUTHB L. Generates BRPLY L through the delay circuit. 11 INWD L IN WORD. Used to gate (read) data from a selected register on to the data bus. Enabled by BSYNC L and strobed by BDIN L. 12 OUTHB L OUT LOW BYTE, OUT HIGH BYTE. Used to load (write) 13 OUTLB L data into the lower, higher, or both bytes of a selected register. Enabled by BSYNC L and decode of BWTBT L and latched BDALO L, and strobed by BDOUT L. 14 15 SELOL SEL2 L 16 SEL4 L SELECT LINES. One of these four signals is true as a function of BDAL2 L and BDAL1 L if ENB H is asserted at the assert edge of BSYNC L. They indicate that a word register has been 17 SEL6 L selected for a data transaction. These signals never become asserted except at the assertion of BSYNC L (then only if ENB H is asserted at that time) and once asserted, are not unasserted until BSYNC L becomes unasserted. A-16 Table A-3 Pin 18 DCO004 Pin/Signal Descriptions (Cont) Signal RXCX Description EXTERNAL RESISTOR CAPACITOR NODE. This node is provided to vary the delay between the BDIN L, BDOUT L, and VECTOR H inputs and BRPLY L output. The external resistor should be tied to VCC and the capacitor to ground. As an output, it is the logical inversion of BRPLY L. 19 ENB H ENABLE. This signal is latched at the asserted edge of BSYNC L and is used to enable the select outputs and the address term of BRPLY L. A-17 JAl L O 20fg vce JA2 L 191 ]2 MATCH H O3 REC H 4 XMITHO5 DAT3 H (6 ~ DAT2 H (7 BUS3 L 8 BUS2 L ]9 GND 410 BUSO L |12} JA3 L 18[0 DATO H 170 DATI H pegos 160 JV3 H 1503 yv2 H 143 yv1 H 1300 MENB L 12[0 BUSO L 1[0 BUST L . {> w& j% 18| DATO H {14‘ JVI H sust L [11} {> JAl L |01lr % I|> fl& —l é@ DATt H es [5] BUS L I_B_;] L\/ saz L [oz} % f|> o{fi }—_] %@DAZH j 6] a& BUS3 L ‘o__e_lr % ]l> Jl> MENB L l13|r ‘é‘ flD T v [os}— ) REC H E‘r —Df— ib—bf sas L 1o} vcc L )—M é ]‘OGI DAT3 H =O3 I MATCH H D_ GND Figure A-7 l JV3 H IC-DCOGS DCO005 Simplified Logic Diagram A-18 TRANSMIT XMIT REC H BUS | H (GROUND) DATA TO l ] |<—5 TO 30ns ——I i-—s TO 30ns BUS L-OUTPUT H-~INPUT | | L RECEIVE DATA FROM BUS XMIT H (BUS INITIALLY HIGH) (GROUND) REC H N DAT [+~ 5 TO 25ns le- —»] 5 TO 25ns DAT H-OUTPUT BUS L= INPUT l+-0 10 3005 1 - _.{ - |0 TO 30ns le8 TO 30ns i [ RECEIVE DATA FROM BUS (BUS INITIALLY LOW) XMIT H (GROUND) REC I H > DAT H - OUTPUT BUS L - INPUT I |e0 710 30ns o ~ la— 8 TO 30ns I -0 T0 30ns — L VECTOR TRANSFER TO BUS JV H e 20 ns MAX > —> e~ 20ns MAX ~ @ 10 TO 40ns BUS L - OUTPUT ADDRESS DECODING X BUS L - INPUT ——| 5 TO 40ns le- —» MENB L RECEIVE XMIT H REC |4— 10 TO 40ns 3( MATCH H MODE LOGIC DELAY | H - &40 TO 90ns DAT(3:0) H (OUTPUT) ...... Figure A-8 DCO005 Timing Diagram A-19 Table A-4 DCO00S Pin/Signal Descriptions Pin Name Function 12 1 BUS<3:0> L BUSO BUSI1 9 8 BUS2 BUS3 BUS DATA. This set of four lines constitutes the bus side of the transceiver. Open collector outputs; high-impedance inputs, LOW = 1. 18 17 7 6 DAT<3:0> H DATO DATI1 DAT?2 DAT3 PERIPHERAL DEVICE DATA. These four 3-state lines carry the inverted received data from BUS <3:0> when the transceiver is in the receive mode. When in transmit data mode, the data carried on these lines is passed inverted to BUS | 3:0>. When in the disabled mode, these lines go open (hi-Z). HIGH = 1. 14 15 16 JV<3:1> H JV1 JV2 JV3 VECTOR JUMPERS. These inputs, with internal pull-down resistors, directly drive BUS <3:1>. A low or open on the jumper pin will cause an open condition on the corresponding bus pin if XMIT H is low. A high will cause a one (low) to be transmitted on the bus pin. Note that BUSO L is not controlled by any jumper input. 13 MENBL MATCH ENABLE. A low on this line will enable the MATCH output. A high will force MATCH low, overriding the match circuit. 3 MATCHH ADDRESS MATCH. When BUS <3:1> match with the state of JA <3:1> and MENB L is low, this output is open; otherwise it is low. 1 2 19 JA<3:1>L JAIL JA2L JA3L ADDRESS JUMPERS. A strap to ground on these inputs will allow a match to occur with a one (low) on the corresponding BUS line; an open will allow a match with a zero (high); a strap to V. will disconnect the corresponding address bit from the comparison. 5 XMITH CONTROL INPUTS. These lines control the operation of the transceiver as follows: 4 RECH REC 0 0 1 1 XMIT 0 1 0 1 DISABLE: XMIT DATA: RECEIVE: RECEIVE: BUS DAT open DAT BUS BUS DAT BUS DAT To avoid 3-state signal overlap conditions, an internal circuit delays the change of modes between XMIT DATA and RECEIVE mode and delays 3-state drivers on the DAT lines from enabling. This action is independent of the DISABLE mode. A-20 Reader’s Comments iBVii-A LSI-11/INSTRUMENT BUS INTERFACE USER’S MANUAL EK-IBV11-UG-001 Your comments and suggestions will help us in our continuous effort to improve the quality and usefuiness of our publications. What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well written, etc.? Is it easy to use? What features are most useful? What faults do you find with the manual? Does this manual satisfy the need you think it was intended to satisfy? Does it satisfy your needs? Why? Would you please indicate any factual errors you have found. Please describe your position. Name Organization Street Department City State Zip or Country FIRST CLASS PERMIT NO. 33 MAYNARD, MASS. BUSINESS REPLY MAIL NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES Postage will be paid by: Digital Equipment Corporation Technical Documentation Department Maynard, Massachusetts 01754
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