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EC-QN7PF-TE

December 1997

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Document:	DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller Data Sheet
Order Number:	EC-QN7PF-TE
Revision:
Pages:	55
Original Filename:	http://bitsavers.org/pdf/dec/semiconductor/ethernet/EC-QN7PF-TE_21140A_PCI_Fast_Ethernet_LAN_Controller_Data_Sheet_199712.pdf

OCR Text

DIGITAL Semiconductor 21140A
PCI Fast Ethernet LAN Controller
Data Sheet
Order Number:

EC–QN7PF–TE

Revision/Update Information:

.
Hardware Version:

This is a revised document. It supersedes the
DIGITAL Semiconductor 21140A PCI Fast
Ethernet LAN Controller Data Sheet,
EC–QN7PE–TE.
This document describes the 21140–AD,
the 21140–AE, and the 21140–AF.

Digital Equipment Corporation
Maynard, Massachusetts
http://www.digital.com/semiconductor

Important Notice
As of May 17, 1998, Digital Equipment Corporation’s StrongARM, PCI Bridge, and Networking
component businesses, along with the chip fabrication facility in Hudson, Massachusetts, were
acquired by Intel Corporation and transferred to Intel Massachusetts, Inc. As a result of this
transaction, certain references to web sites, telephone numbers, and fax numbers have changed in the
documentation. This information will be updated in the next version of this manual. Copies of
documents that have an ordering number and are referenced in this document, or other Intel literature
may be obtained by calling 1-800-332-2717 or by visiting Intel’s website for developers at:
http://developer.intel.com
The Intel Massachusetts Customer Technology Center continues to service your StrongARM Product,
Bridge Product, and Network Product technical inquiries. Please use the following information lines
for support:
For documentation and general information:
Intel Massachusetts Information Line

United States:
Outside United States:
Electronic mail address:

1–800–332–2717
1–303-675-2148
techdoc@intel.com

For technical support:
Intel Massachusetts Customer Technology Center

Phone (U.S. and international):
Fax:
Electronic mail address:

1–978–568–7474
1–978–568–6698
techsup@intel.com

December 1997
While DIGITAL believes the information included in this publication is correct as of the date of publication, it is
subject to change without notice.
This data sheet, including associated product update information, defines a particular variant of this product. Please
read the Support, Products, and Documentation section in this document to determine how to obtain current product
update and errata information.
Digital Equipment Corporation makes no representations that the use of its products in the manner described in this
publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication
imply the granting of licenses to make, use, or sell equipment or software in accordance with the description.
©Digital Equipment Corporation 1997. All rights reserved.
Printed in U.S.A.
DIGITAL, DIGITAL Semiconductor, and the DIGITAL logo are trademarks of Digital Equipment Corporation.
DIGITAL Semiconductor is a Digital Equipment Corporation business.
IEEE is a registered trademark of The Institute of Electrical and Electronic Engineers, Inc.
MicroWire is a registered trademark of BankAmerica Corporation.
All other trademarks and registered trademarks are the property of their respective owners.

Contents
1

21140A Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1
1.2
1.3

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1
2
3

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1
2.2
2.3

Signal Reference Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Grouping by Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8
18
20

Electrical and Environmental Specifications . . . . . . . . . . . . . . . . . .

3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5

22
22
23
23
23
24
25
26

3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.8
3.8.1
3.8.2
3.9
3.10
3.11
3.11.1
3.11.2

Voltage Limit Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Limit Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Current and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI I/O Voltage Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial, MII/SYM, Boot ROM, Serial ROM, and
General-Purpose Port Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Network Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial 10-Mb/s Timing—Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial 10-Mb/s Timing—Collision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial 10 Mb/s Timing—Receive, Start of Packet . . . . . . . . . . . . . . . . . . . . .
Serial 10-Mb/s Timing—Receive, Start, and End of Packet . . . . . . . . . . . . .
MII/SYM Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM 10/100-Mb/s and 10-Mb/s Timing—Transmit . . . . . . . . . . . . . . . . .
MII/SYM 10/100-Mb/s Timing—Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM 10/100-Mb/s Timing—Signal Detect . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM 10/100-Mb/s Timing—Receive Error. . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM 10/100-Mb/s Timing—Carrier Sense and Collision . . . . . . . . . . . . .
Boot ROM Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot ROM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot ROM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial ROM Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Register Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Joint Test Action Group—Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Boundary-Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27
28
28
29
30
31
32
32
34
35
36
36
37
37
38
39
40
41
41
41

iii

Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Support, Products, and Documentation . . . . . . . . . . . . . . . . . . . . . . .

Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

21140A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21140A Pinout Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Clock Specification Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagram for Other PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Network Port Timing Diagram—Transmit . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Network Port Timing Diagram—Collision . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Network Port Timing Diagram—Receive, Start of Packet. . . . . . . . . . . . . .
Serial Network Port Timing Diagram—Receive, End of Packet . . . . . . . . . . . . . .
MII/SYM Port Timing Diagram—Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing Diagram—Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing Diagram—Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing Diagram—Receive Error. . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing Diagram—Carrier Sense and Collision . . . . . . . . . . . . . . . .
Boot ROM Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot ROM Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial ROM Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Register Read Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Register Write Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Boundary-Scan Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
144-PIN PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5
7
24
25
26
28
29
30
31
32
34
35
36
36
37
38
39
40
40
42
44

Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

Index to Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description of 21140A Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Drain Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Limit Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Limit Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Current and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Voltage Specifications for 5.0-V Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Voltage Specification for 3.3-V Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial, MII/SYM, Boot ROM, Serial ROM, and General-Purpose Port . . . . . . . . .
Serial Network Port Timing—Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Network Port Timing—Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Network Port Timing—Receive, Start, and End of Packet . . . . . . . . . . . . .
MII/SYM Port Timing—Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing—Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing—Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing—Receive Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing—Carrier Sense and Collision . . . . . . . . . . . . . . . . . . . . . . .
Boot ROM Read Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot ROM Write Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial ROM Port Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Register Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Interface Signal Timing Relationships. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
144-Pin PQFP Dimensional Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6
8
9
10
19
19
19
20
20
22
22
23
23
24
24
25
27
27
29
29
31
33
34
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1 21140A Overview
The DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller (21140A)
supports the peripheral component interconnect (PCI) bus. It provides a direct
interface connection to the PCI and adapts easily to most other standard buses. The
21140A software interface and data structures are optimized to minimize the host
CPU load and to allow for maximum flexibility in the buffer descriptor management.
The 21140A contains large onchip FIFOs, so no additional onboard memory is
required. The 21140A provides an upgradable boot ROM interface.
The 21140A has several additional features that are not available on the 21140, yet it
remains pin and software compatible with the 21140.

1.1 General Description
The 21140A interfaces with the PCI bus by using onchip control and status registers
(CSRs), and a shared CPU memory area that is set up mainly during initialization.
This minimizes the processor involvement in the 21140A operation during normal
reception and transmission. Traffic on the PCI bus is also minimized by filtering out
received runt frames and by automatically retransmitting collided frames without
needing to repeat a fetch from shared memory. The 21140A is compliant with
revisions 2.0 and 2.1 of the PCI Local Bus Specification.
On the network side, the 21140A provides two ports: a serial standard 7-wire (SRL)
10-Mb/s port and a media-independent interface/symbol (MII/SYM) 10/100-Mb/s
port. The 10-Mb/s port provides a direct interface to the external 10-Mb/s front-end
decoder (ENDEC). The 10/100-Mb/s port supports two operational modes:

•

A direct interface to the external 10/100-Mb/s ENDEC. The 21140A includes
the onchip physical coding sublayer (PCS) and the scrambler for efficient
100BASE-T (CAT5 cable) implementation.

•

A full implementation of the MII standard.

The 21140A is also capable of functioning in a full-duplex environment for both the
10-Mb/s and 10/100-Mb/s ports.

21140A Overview

Features

1.2 Features
The 21140A has the following features:

•

Offers a single-chip Fast Ethernet controller for PCI local bus:
- Provides a glueless connection to the PCI bus
- Supports two network ports: 10 Mb/s and 10/100 Mb/s

•

Provides a standard 10/100-Mb/s MII supporting CAT3 unshielded twisted-pair
(UTP), CAT5 UTP, shielded twisted-pair (STP) and fiber cables

•

Contains onchip scrambler and PCS for CAT5 to significantly reduce cost of
100BASE-T solutions

•

Supports full-duplex operation on both 10-Mb/s and 10/100-Mb/s ports

•

Provides external and internal loopback capability on both ports

•

Contains a variety of flexible address filtering modes (including perfect, hash
tables, inverse perfect, and promiscuous):
- 16 perfect addresses (normal or inverse filtering)
- 512 hash-filtered addresses
- 512 hash-filtered multicast addresses and one perfect address
- Pass all multicast
- Promiscuous
- Pass all incoming packets with a status report

•

Offers a unique, patented solution to Ethernet capture-effect problem

•

Contains large independent receive and transmit FIFOs; no additional onboard
memory required

•

Includes a powerful onchip direct memory access (DMA) with programmable
burst size providing for low CPU utilization

•

Implements unique, patent-pending intelligent arbitration between DMA
channels preventing underflow or overflow

•

Supports PCI clock frequency from dc to 33 MHz; network operational with PCI
clock from 20 MHz to 33 MHz

•

Supports an unlimited PCI burst

21140A Overview

Microarchitecture

•

Supports PCI read multiple command

•

Supports early interrupts on transmit and receive for improved performance

•

Implements low-power management with two power-saving modes (sleep or
snooze)

•

Supports both PCI 5.0-V and 3.3-V signaling environments

•

Supports either big or little endian byte ordering for buffers and descriptors

•

Contains 8-bit, general-purpose, programmable register and corresponding I/O
pins

•

Provides LED support for various network activity indications

•

Provides MicroWire interface for serial ROM (1K and 4K EEPROM)

•

Provides an upgradable boot ROM interface of up to 256KB

•

Supports automatic loading of subsystem vendor ID and subsystem ID from
serial ROM to configuration register

•

Implements JTAG-compatible test-access port with boundary-scan pins

•

Supports IEEE 802.3, ANSI 8802-3, and Ethernet standards

•

Implements low-power, 3.3-V complementary metal-oxide semiconductor
(CMOS) process technology

•

Supports PCI write and invalidate, and read line commands

1.3 Microarchitecture
The following list describes the 21140A hardware components, and Figure 1 shows a
block diagram of the 21140A:

•

PCI interface—Includes all interface functions to the PCI bus; handles all
interconnect control signals; and executes PCI DMA and I/O transactions.

•

DMA—Contains dual receive and transmit controller; handles data transfers
between CPU memory and onchip memory.

•

FIFOs—Contains two FIFOs for receive and transmit; supports automatic packet
deletion on receive (runt packets or after a collision) and packet retransmission
after a collision on transmit.

•

TxM—Handles all CSMA/CD MAC1 transmit operations, and transfers data
from transmit FIFO to the ENDEC for transmission.
21140A Overview

Microarchitecture

•

RxM—Handles all CSMA/CD receive operations, and transfers the data from
the ENDEC to the receive FIFO.

•

Physical coding sublayer—Implements the encoding and decoding sublayer of
the 100BASE-TX (CAT5) specification, including the squelch.

•

Scrambler/descrambler—Implements the twisted-pair physical layer medium
dependent (TP-PMD) scrambler/descrambler scheme.

•

General-purpose register—Enables software to use for input or output functions.

•

Serial interface—Provides a 7-wire conventional interface to the Ethernet
ENDEC components.

•

MII/SYM interface—Provides a full MII signal interface and a direct interface to
the 10/100-Mb/s ENDEC for CAT5.

•

Serial ROM port—Provides a direct interface to the MicroWire ROM for storage
of the Ethernet address and system parameters.

•

Boot ROM port—Provides an interface to perform read and write operations to
the boot ROM; supports accesses to bytes or longword (32-bit). Also provides
the ability to connect an external 8-bit register to the boot ROM port.

Media access control

21140A Overview

Microarchitecture

Figure 1 21140A Block Diagram
Boot ROM/
External
Register

Serial
ROM

Board
Control
Signals

PCI
Interface

Boot
ROM
Port

Serial
ROM
Port

GeneralPurpose
Register

PCI

DMA
32

Rx
FIFO

Tx
FIFO
16

16
RxM

TxM

4
4

Physical Coding
Sublayer
4
1

4
Scrambler/
Descrambler

Serial Interface

MII/SYM Interface

10 Mb/s

10 Mb/s or 100 Mb/s

LJ-05042.AI4

21140A Overview

2 Pinout
The 21140A is packaged in a 144-pin plastic quad flat pack (PQFP). The tables in
this section provide a description of the pins and their respective signal definitions.
Table 1 lists the tables in this section. Figure 2 shows the 21140A pinout.
Table 1 Index to Pinout Tables

For this information...

Refer to...

Logic signals

Table 2

Power pins

Table 3

Functional signals description

Table 4

Input pins

Table 5

Output pins

Table 6

Input/output pins

Table 7

Open drain pins

Table 8

Signal functions

Table 9

Pinout

tdo
tdi
tms
tck
srl_txen
srl_tclk
srl_txd
srl_rclk
srl_rxen
srl_rxd
srl_clsn
mii/srl
sym_txd<4>
mii/sym_txd<3>
mii/sym_txd<2>
vdd
vss
mii/sym_txd<1>
mii/sym_txd<0>
mii/sym_txen
sym_link
mii/sym_tclk
rcv_match
vdd
vss
sym_rxd<4>
mii/sym_rxd<3>
mii/sym_rxd<2>
mii/sym_rxd<1>
mii/sym_rxd<0>
mii/sym_rclk
mii_crs
mii_clsn
mii_dv
mii_err
sd

Figure 2 21140A Pinout Diagram (Top View)

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0
4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

21140A

108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

vss
vdd
mii_mdc
mii_mdio
nc
br_a<1>
br_a<0>
br_ce_l
br_ad<7>
br_ad<6>
vdd
vss
br_ad<5>
br_ad<4>
br_ad<3>
br_ad<2>
br_ad<1>
br_ad<0>
vss
gep<7>
gep<6>
gep<5>
gep<4>
vdd
vss
gep<3>
gep<2>
gep<1>
gep<0>
sr_cs
sr_ck
sr_di
sr_do
vdd
vss
vdd_clamp

3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7
7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2
vss
c_be_l<2>
frame_l
irdy_l
trdy_l
devsel_l
stop_l
vdd
perr_l
serr_l
par
c_be_l<1>
vss
ad<15>
ad<14>
ad<13>
vss
ad<12>
ad<11>
vdd
ad<10>
ad<9>
vss
ad<8>
c_be_l<0>
ad<7>
ad<6>
vss
ad<5>
ad<4>
vdd
ad<3>
ad<2>
vss
ad<1>
ad<0>

int_l
rst_l
vdd
vss
pci_clk
vdd
gnt_l
req_l
vss
ad<31>
ad<30>
vss
ad<29>
ad<28>
vss
ad<27>
ad<26>
vdd
ad<25>
ad<24>
c_be_l<3>
idsel
vss
ad<23>
ad<22>
ad<21>
ad<20>
vdd
ad<19>
ad<18>
vdd
vss
vss
ad<17>
ad<16>
vss

LJ-04479.AI4

Pinout

Signal Reference Tables

2.1 Signal Reference Tables
Table 2 provides an alphabetical list of the 21140A logic names and their pin
numbers. Table 3 provides a list of the 21140A power pin numbers.
Table 2 Logic Signals

(Sheet 1 of 2)

Signal

Pin
Number

Signal

Pin
Number

Signal

Pin
Number

ad<0>

ad<24>

frame_l

ad<1>

ad<25>

gep<0>

ad<2>

ad<26>

gep<1>

ad<3>

ad<27>

gep<2>

ad<4>

ad<28>

gep<3>

ad<5>

ad<29>

gep<4>

ad<6>

ad<30>

gep<5>

ad<7>

ad<31>

gep<6>

ad<8>

br_a<0>

102

gep<7>

ad<9>

br_a<1>

103

gnt_l

ad<10>

br_ad<0>

idsel

ad<11>

br_ad<1>

int_l

ad<12>

br_ad<2>

irdy_l

ad<13>

br_ad<3>

mii_clsn

112

ad<14>

br_ad<4>

mii_crs

113

ad<15>

br_ad<5>

mii_dv

111

ad<16>

br_ad<6>

mii_err

110

ad<17>

br_ad<7>

100

mii_mdc

106

ad<18>

br_ce_l

101

mii_mdio

105

ad<19>

c_be_l<0>

mii/srl

133

ad<20>

c_be_l<1>

mii/sym_rclk

114

ad<21>

c_be_l<2>

mii/sym_rxd<0>

115

ad<22>

c_be_l<3>

mii/sym_rxd<1>

116

Pinout

Signal Reference Tables

Table 2 Logic Signals

(Sheet 2 of 2)

Signal

Pin
Number

Signal

Pin
Number

Signal

Pin
Number

ad<23>

devsel_l

mii/sym_rxd<2>

117

mii/sym_rxd<3>

118

req_l

srl_tclk

139

mii/sym_tclk

123

rst_l

srl_txd

138

mii/sym_txd<0>

126

109

srl_txen

140

mii/sym_txd<1>

127

serr_l

stop_l

mii/sym_txd<2>

130

sr_ck

sym_link

124

mii/sym_txd<3>

131

sr_cs

sym_rxd<4>

119

mii/sym_txen

125

sr_di

sym_txd<4>

132

104

sr_do

tck

141

par

srl_clsn

134

tdi

143

pci_clk

srl_rclk

137

tdo

144

perr_l

srl_rxd

135

tms

142

rcv_match

122

srl_rxen

136

trdy_l

Table 3 Power Pins
Signal

Pin Numbers

Signal

Pin Numbers

vdd (3.3 V)

3, 6, 18, 28,

vss (Gnd)

4, 9, 12, 15,

31, 44, 56, 67,

23, 32, 33, 36,

75, 85, 98, 107,

37, 49, 53, 59,

121, 129

64, 70, 74, 84,
90, 97, 108,
120, 128

vdd_clamp
(5.0 V or 3.3 V)

Pinout

Signal Reference Tables

Table 4 provides a functional description of each of the 21140A signals. These
signals are listed alphabetically. The functional grouping of each pin is listed in
Section 2.3.
The following terms describe the 21140A pinout:

•

Address phase
Address and appropriate bus commands are driven during this cycle.

•

Data phase
Data and the appropriate byte enable codes are driven during this cycle.

•

_l
All pin names with the _l suffix are asserted low.

The following abbreviations are used in Table 4:
I = Input
O = Output
I/O = Input/output
O/D = Open drain
P = Power
Table 4 Functional Description of 21140A Signals

(Sheet 1 of 9)

Signal

Type

Pin
Number

Description

ad<31:0>

I/O

See Table 2.

32-bit PCI address and data lines. Address and
data bits are multiplexed on the same pins.
During the first clock cycle of a transaction, the
address bits contain a physical address
(32 bits). During subsequent clock cycles,
these same lines contain 32 bits of data. A
21140A bus transaction consists of an address
phase followed by one or more data phases.
The 21140A supports both read and write
bursts (in master operation only). Little and
big endian byte ordering can be used.

br_a<0>

102

Boot ROM address line bit 0. In a 256KB
configuration, this pin also carries in two
consecutive address cycles, boot ROM address
bits 16 and 17.

Pinout

Signal Reference Tables

Table 4 Functional Description of 21140A Signals

(Sheet 2 of 9)

Signal

Type

Pin
Number

Description

br_a<1>

103

Boot ROM address line bit 1. This pin also
latches the boot ROM address and control lines
by the two external latches.

br_ad<7:0>

I/O

See Table 2.

Boot ROM address and data multiplexed lines
bits 7 through 0. In the first of two consecutive
address cycles, these lines contain the boot
ROM address bits 7 through 2, oe_l and we_l;
followed by boot ROM address bits 15 through
8 in the second cycle. During the data cycle,
bits 7 through 0 contain data.
During operation with the external register,
these lines are used to carry data bits 7 through
0 to and from the external register.

br_ce_l

101

Boot ROM or external register chip enable.
This pin has an internal 5 kΩ pull-up resistor.

c_be_l<3:0>

I/O

See Table 2.

Bits 0 through 3 of the bus command and byte
enable lines. Bus command and byte enable
are multiplexed on the same PCI pins.
During the address phase of the transaction,
these 4 bits provide the bus command.
During the data phase, these 4 bits provide the
byte enable. The byte enable determines which
byte lines carry valid data. For example, bit 0
applies to byte 0, and bit 3 applies to byte 3.

devsel_l

I/O

Device select is asserted by the target of the
current bus access. When the 21140A is the
initiator of the current bus access, it expects the
target to assert devsel_l within five bus cycles,
confirming the access. If the target does not
assert devsel_l within the required bus cycles,
the 21140A aborts the cycle. To meet the
timing requirements, the 21140A asserts this
signal in a medium speed (within two bus
cycles).

Pinout

Signal Reference Tables

Table 4 Functional Description of 21140A Signals

(Sheet 3 of 9)

Signal

Type

Pin
Number

Description

frame_l

I/O

The frame_l signal is driven by the 21140A
(bus master) to indicate the beginning and
duration of an access. The frame_l signal
asserts to indicate the beginning of a bus
transaction. While frame_l is asserted, data
transfers continue. The frame_l signal
deasserts to indicate that the next data phase is
the final data phase transaction.

gep<7:0>

I/O

See Table 2.

General-purpose pins can be used by software
as either status pins or control pins. These pins
can be configured by software to perform
either input or output functions.

gnt_l

Bus grant asserts to indicate to the 21140A that
access to the bus is granted.

idsel

Initialization device select asserts to indicate
that the host is issuing a configuration cycle to
the 21140A.

int_l

O/D

Interrupt request asserts when one of the
appropriate bits of CSR5 sets and causes an
interrupt, provided that the corresponding
mask bit in CSR7 is not asserted. Interrupt
request deasserts by writing a 1 into the
appropriate CSR5 bit.
If more than one interrupt bit is asserted in
CSR5 and the host does not clear all input bits,
the 21140A deasserts int_l for one cycle to
support edge-triggered systems.
This pin must be pulled up by an external
resistor.

Pinout

Signal Reference Tables

Table 4 Functional Description of 21140A Signals

(Sheet 4 of 9)

Signal

Type

Pin
Number

Description

irdy_l

I/O

Initiator ready indicates the bus master’s ability
to complete the current data phase of the
transaction.
A data phase is completed on any rising edge
of the clock when both irdy_l and target ready
trdy_l are asserted. Wait cycles are inserted
until both irdy_l and trdy_l are asserted
together.
When the 21140A is the bus master, irdy_l is
asserted during write operations to indicate that
valid data is present on the 32-bit ad lines.
During read operations, the 21140A asserts
irdy_l to indicate that it is ready to accept data.

mii_clsn

112

Collision detected is asserted when detected by
an external physical layer protocol (PHY)
device.

mii_crs

113

Carrier sense is asserted by the PHY when the
media is active.

mii_dv

111

Data valid is asserted by an external PHY when
receive data is present on the mii/sym_rxd
lines and is deasserted at the end of the packet.
This signal should be synchronized with the
mii/sym_rclk signal.

mii_err

110

Receive error asserts when a data decoding
error is detected by an external PHY device.
This signal is synchronized to mii/sym_rclk
and can be asserted for a minimum of one
receive clock. When asserted during a packet
reception, it sets the cyclic redundancy check
(CRC) error bit in the receive descriptor
(RDES0).

mii_mdc

106

MII management data clock is sourced by the
21140A to the PHY devices as a timing
reference for the transfer of information on the
mii_mdio signal.

Pinout

Signal Reference Tables

Table 4 Functional Description of 21140A Signals

(Sheet 5 of 9)

Signal

Type

Pin
Number

Description

mii_mdio

I/O

105

MII management data input/output transfers
control information and status between the
PHY and the 21140A.

mii/srl

133

Indicates the selected port: SRL or MII/SYM.
When asserted, the MII/SYM port is active.
When deasserted, the SRL port is active.

mii/sym_rclk

114

Supports either the 25-MHz or 2.5-MHz
receive clock. This clock is recovered by the
PHY.

mii/sym_rxd<3:0>

See Table 2.

Four parallel receive data lines when MII mode
is selected. This data is driven by an external
PHY that attached the media and should be
synchronized with the mii/sym_rclk signal.

mii/sym_tclk

123

Supports the 25-MHz or 2.5-MHz transmit
clock supplied by the external physical layer
medium dependent (PMD) device. This clock
should always be active.

mii/sym_txd<3:0>

See Table 2.

Four parallel transmit data lines. This data is
synchronized to the assertion of the
mii/sym_tclk signal and is latched by the
external PHY on the rising edge of the
mii/sym_tclk signal.

mii_txen

125

Transmit enable signals that the transmit is
active to an external PHY device. In PCS
mode (CSR6<23>), this signal reflects the
transmit activity of the MAC sublayer.

104

No connection.

par

I/O

Parity is calculated by the 21140A as an even
parity bit for the 32-bit ad and 4-bit c_be_l
lines.
During address and data phases, parity is
calculated on all the ad and c_be_l lines
whether or not any of these lines carry
meaningful information.

Pinout

Signal Reference Tables

Table 4 Functional Description of 21140A Signals

(Sheet 6 of 9)

Signal

Type

Pin
Number

Description

pci_clk

The clock provides the timing for the 21140A
related PCI bus transactions. All the bus
signals are sampled on the rising edge of
pci_clk. The clock frequency range is between
25 MHz and 33 MHz.

perr_l

I/O

Parity error asserts when a data parity error is
detected.
When the 21140A is the bus master and a
parity error is detected, the 21140A asserts
both CSR5 bit 13 (system error) and CFCS bit
24 (data parity report). Next, it completes the
current data burst transaction, then stops
operation. After the host clears the system
error, the 21140A continues its operation.
The 21140A asserts perr_l when a data parity
error is detected in either master-read or slavewrite operations.
This pin must be pulled up by an external
resistor.

rcv_match

122

Receive match indication is asserted when a
received packet has passed address
recognition.

req_l

Bus request is asserted by the 21140A to
indicate to the bus arbiter that it wants to use
the bus.

rst_l

Resets the 21140A to its initial state. This
signal must be asserted for at least 10 active
PCI clock cycles. When in the reset state, all
PCI output pins are put into tristate and all PCI
O/D signals are floated.

109

Signal detect indication supplied by an external
physical layer medium dependent (PMD)
device.

Pinout

Signal Reference Tables

Table 4 Functional Description of 21140A Signals

(Sheet 7 of 9)

Signal

Type

Pin
Number

Description

serr_l

O/D

If an address parity error is detected and CFCS
bit 8 (serr_l enable) is enabled, the 21140A
asserts both serr_l (system error) and CFCS
bit 30 (signal system error).
When an address parity error is detected,
system error asserts two clocks after the failing
address.
This pin must be pulled up by an external
resistor.

sr_ck

Serial ROM clock signal.

sr_cs

Serial ROM chip-select signal. This pin has an
internal 2 kΩ pull-down resistor.

sr_di

Serial ROM data-in signal.

sr_do

Serial ROM data-out signal. This pin has an
internal 5 kΩ pull-up resistor.

srl_clsn

134

Collision detect signals a collision occurrence
on the Ethernet cable to the 21140A. It may be
asserted and deasserted asynchronously by the
external ENDEC to the receive clock.

srl_rclk

137

Receive clock carries the recovered receive
clock supplied by an external ENDEC. During
idle periods, srl_rclk may be inactive.

srl_rxd

135

Receive data carries the input receive data from
the external ENDEC. The incoming data
should be synchronous with the srl_rclk
signal.

srl_rxen

136

Receive enable signals activity on the Ethernet
cable to the 21140A. It is asserted when
receive data is present on the Ethernet cable
and is deasserted at the end of a frame. It may
be asserted and deasserted asynchronously to
the receive clock (srl_rclk) by the external
ENDEC.

Pinout

Signal Reference Tables

Table 4 Functional Description of 21140A Signals

(Sheet 8 of 9)

Signal

Type

Pin
Number

Description

srl_tclk

139

Transmit clock carries the transmit clock
supplied by an external ENDEC. This clock
must always be active (even during reset).

srl_txd

138

Transmit data carries the serial output data
from the 21140A. This data is synchronized to
the srl_tclk signal.

srl_txen

140

Transmit enable signals an external ENDEC
that the 21140A transmit is in progress.

stop_l

I/O

Stop indicator indicates that the current target
is requesting the bus master to stop the current
transaction.
The 21140A responds to the assertion of stop_l
when it is the bus master, either to disconnect,
retry, or abort.

sym_link

124

Indicates that the descrambler is locked to the
input data signal.

sym_rxd<4>

119

Receive data, together with the four receive
lines mii/sym_rxd<3:0>, provide five parallel
lines of data in symbol form for use in PCS
mode (100BASE-T, CSR6<23>). This data is
driven by an external PMD device and should
be synchronized to the mii/sym_rclk signal.

sym_txd<4>

132

Transmit data, together with the four transmit
lines mii/sym_txd<3:0>, provide five parallel
lines of data in symbol form for use in PCS
mode (100BASE-T, CSR6<23>). This data is
synchronized on the rising edge of the
mii/sym_tclk signal.

tck

141

JTAG clock shifts state information and test
data into and out of the 21140A during JTAG
test operations. This pin should not be left
unconnected.

tdi

143

JTAG data in is used to serially shift test data
and instructions into the 21140A during JTAG
test operations. This pin has an internal
pull-up resistor and can be left unconnected.

Pinout

Pin Tables

Table 4 Functional Description of 21140A Signals

(Sheet 9 of 9)

Signal

Type

Pin
Number

Description

tdo

144

JTAG data out is used to serially shift test data
and instructions out of the 21140A during
JTAG test operations.

tms

142

JTAG test mode select controls the state
operation of JTAG testing in the 21140A. This
pin has an internal pull-up resistor and can be
left unconnected.

trdy_l

I/O

Target ready indicates the target agent’s ability
to complete the current data phase of the
transaction.
A data phase is completed on any clock when
both trdy_l and irdy_l are asserted. Wait
cycles are inserted until both irdy_l and trdy_l
are asserted together.
When the 21140A is the bus master, target
ready is asserted by the bus slave on the read
operation, indicating that valid data is present
on the ad lines. During a write cycle, it
indicates that the target is prepared to accept
data.

vdd

See Table 3.

3.3-V supply input voltage.

vdd_clamp

5.0-V reference for 5.0-V signaling
environments and 3.3 V for 3.3-V signaling
environments.

vss

See Table 3.

Ground pins.

2.2 Pin Tables
This section contains four types of pin tables:

•

Table 5 lists the input pins.

•

Table 6 lists the output pins.

•

Table 7 lists the input/output pins.

•

Table 8 lists the open drain pins.

Pinout

Pin Tables

Table 5 Input Pins
Signal

Active Level

Signal

Active Level

gnt_l
idsel
mii_clsn
mii_crs
mii_dv
mii_err
mii/sym_rclk
mii/sym_rxd<3:0>
mii/sym_tclk
pci_clk
rst_l

Low
High
High
High
High
High
—
—
—
—
Low

sd
sr_do
srl_clsn
srl_rclk
srl_rxd
srl_rxen
srl_tclk
sym_rxd<4>
tck
tdi
tms

High
—
High
—
—
High
—
—
—
—
—

Signal

Active Level

Signal

Active Level

br_a<0>
br_a<1>
br_ce_l
mii_mdc
mii/srl
mii/sym_txd<3:0>
mii_txen
nc
rcv_match

High
High
Low
—
—
—
High
—
High

req_l
sr_ck
sr_cs
sr_di
srl_txd
srl_txen
sym_link
sym_txd<4>
tdo

Low
—
High
—
—
High
High
—
High

Table 6 Output Pins

Table 7 Input/Output Pins

(Sheet 1 of 2)

Signal

Active Level

Signal

Active Level

ad<31:0>
br_ad<7:0>
c_be_l<3:0>

—
—
Low

irdy_l
mii_mdio
par

Low
—
—

Pinout

Signal Grouping by Function

Table 7 Input/Output Pins

(Sheet 2 of 2)

Signal

Active Level

Signal

Active Level

devsel_l
frame_l
gep<7:0>

Low
Low
—

perr_l
stop_l
trdy_l

Low
Low
Low

Table 8 Open Drain Pins
Signal

Active Level

Signal

Active Level

int_l

Low

serr_l

Low

2.3 Signal Grouping by Function
Table 9 lists the signals according to their interface function.
Table 9 Signal Functions

(Sheet 1 of 2)

Interface

Function

Signal

PCI

Address and data

ad<31:0>, par

Arbitration

gnt_l, req_l

Bus command and byte enable

c_be_l<3:0>

Device select

devsel_l, idsel

Error reporting

perr_l, serr_l

Interrupt

int_l

System

pci_clk, rst_l

Control signals

frame_l, stop_l, irdy_l, trdy_l

MII/symbol

Transmit data lines

mii/sym_txd<3:0>

Network port

Receive data lines

mii/sym_rxd<3:0>

Transmit, receive clocks

mii/sym_tclk, mii/sym_rclk

SYM mode

sym_rxd<4>, sym_txd<4>

Signal detection

Pinout

Signal Grouping by Function

Table 9 Signal Functions
Interface

(Sheet 2 of 2)

Function

Signal

Transmit enable

mii_txen

Collision detect

mii_clsn

Error reporting

mii_err

Data control

mii_dv, mii_crs

MII management data clock

mii_mdc

MII management data
input/output

mii_mdio

Transmit and receive data

srl_txd, srl_rxd

Transmit control

srl_txen, srl_tclk

Receive control

srl_rxen, srl_rclk

Collision detect

srl_clsn

LED indicators

rcv_match, sym_link

General-purpose pins

gep<7:0>

MII/SYM and serial port select

mii/srl

Test access port

JTAG test operations

tck, tdi, tdo, tms

Serial ROM port

Serial ROM

sr_ck, sr_cs, sr_di, sr_do

Boot ROM

ROM interface

br_a<1:0>, br_ad<7:0>, br_ce_l

Power

3.3-V and 5.0-V supply input

vdd, vdd_clamp

Ground

vss

Serial network port

Miscellaneous

Pinout

Voltage Limit Ratings

3 Electrical and Environmental Specifications
This section contains the electrical and environmental specifications for the 21140A.
Caution:

Stresses greater than the maximum or less than the minimum ratings can
cause permanent damage to the 21140A. Exposure to the maximum or
minimum ratings for extended periods of time lessen the reliability of
the 21140A.

3.1 Voltage Limit Ratings
Table 10 lists the voltage limit ratings.
Table 10 Voltage Limit Ratings
Parameter

Minimum

Maximum

Power supply voltage

+3.0 V

+3.6 V

+3.0 V

+3.6 V

vdd_clamp (5.0 V)

+4.75 V

+5.25 V

ESD protection voltage

—

2000 V

vdd_clamp (3.3 V)

In the 3.3-V signalling environment, vdd_clamp must not be more than +0.3 V above vdd.

3.2 Temperature Limit Ratings
Table 11 lists the temperature limit ratings.
Table 11 Temperature Limit Ratings
Parameter

Minimum

Maximum

Storage temperature

–55°C

+125°C

Operating temperature

0°C

70°C

Electrical and Environmental Specifications

Supply Current and Power Dissipation

3.3 Supply Current and Power Dissipation
The values in Table 12 are estimates based on a PCI clock frequency of 33 MHz and
a network data rate of 10 Mb/s for SRL and 10/100 Mb/s for MII.
Table 12 Supply Current and Power Dissipation
Typical 1

Maximum 2

Symbol

Idd (mA)

Power (mW)

Idd (mA)

Power (mW)

Normal power mode

125

413

180

648

Snooze power mode

248

150

540

Sleep power mode

198

125

450

Typical: vdd = 3.3 V, Ta = 25°C.

Maximum: vdd = 3.6 V, Ta = 0°C.

3.4 PCI Electrical Parameters
This section describes the PCI characteristics for the 21140A.

3.4.1 PCI I/O Voltage Specifications
The 21140A meets the I/O voltage specifications listed in Table 13 and Table 14.
Table 13 I/O Voltage Specifications for 5.0-V Levels
Symbol

Parameter

Condition

Minimum

Maximum

Vih

Input high voltage

—

2.0 V

vdd_clamp + 0.5 V

Vil

Input low voltage

—

–0.5 V

0.8 V

Ii1

Input leakage current 0.5 V < Vin < 2.7 V

—

±70 µA

Voh

Output high voltage

Iout = –2 mA

2.4 V

—

Output low voltage

Iout = 3 mA, 6 mA

—

0.55 V

Pin capacitance

—

5 pF

8 pF

Vol2
Cap

Input leakage currents include high-impedance output leakage for all bidirectional buffers with tristate outputs.

Signals without pull-up resistors have a low output current of 3 mA. Signals requiring pull-up resistors
(including frame_l, trdy_l, irdy_l, devsel_l, stop_l, serr_l, and perr_l) have a low output current of 6 mA.

Parameter design guarantee.

Electrical and Environmental Specifications

PCI Electrical Parameters

Table 14 I/O Voltage Specification for 3.3-V Levels
Symbol

Parameter

Condition

Minimum

Maximum

Vih

Input high
voltage

—

0.475 ∗ vdd_clamp vdd_clamp + 0.5 V

Vil

Input low voltage —

Ii1

Input leakage
current

0.0 V < Vin < vdd_clamp —

Voh

Output high
voltage

Iout = –500 µA

0.9 ∗ vdd_clamp

—

Vol

Output low
voltage

Iout = 1500 µA

—

0.1 ∗ vdd_clamp

Cap2

Pin capacitance

—

5 pF

8 pF

0.325 ∗ vdd_clamp

–0.5 V

±10 µA

Input leakage currents include high-impedance output leakage for all bidirectional buffers with tristate outputs.

Parameter design guarantee.

3.4.2 PCI Reset
PCI reset (pci_rst) is an asynchronous signal that must be active for at least 10 active
PCI clock (pci_clk) cycles. Figure 3 shows the PCI reset timing characteristics, and
Table 15 lists the PCI reset signal limits.
Figure 3 PCI Reset Timing Diagram
pci_clk

pci_rst

10 pci_clk Cycles

Internal Reset

33 pci_clk Cycles
LJ-03902.AI4

Table 15 PCI Reset Timing
Symbol

Parameter

Minimum

Maximum

Conditions

Trst

pci_rst pulse width

10 ∗ Tcycle

Not applicable

pci_clk
active

Electrical and Environmental Specifications

PCI Electrical Parameters

3.4.3 PCI Clock Specifications
The clock frequency range for the PCI is between 20 MHz and 33 MHz.1 Figure 4
shows the PCI clock specification timing characteristics and required measurement
points for both 5-V and 3.3-V signaling environments. Table 16 lists the frequencyderived clock specifications.
Figure 4 PCI Clock Specification Timing Diagram
Thigh

5.0-V Clock
2.0 V

Tlow
0.8 V

3.3-V Clock

0.475 * vdd_clamp
0.325 * vdd_clamp

Tcycle
LJ03910A.AI4

Table 16 PCI Clock Specifications
Symbol

Parameter

Minimum

Maximum

Tcycle

Cycle time

30 ns

50 ns

Thigh

pci_clk high time

11 ns

—

Tlow

pci_clk low time

11 ns

—

Tr/Tf1

pci_clk slew rate

1 V/ns

4 V/ns

Rise and fall times are specified in terms of the edge rate measured in V/ns. Parameter design guarantee.

The PCI clock frequency is from dc to 33 MHz; network operational with the PCI clock from 20 MHz
to 33 MHz.
Electrical and Environmental Specifications

PCI Electrical Parameters

3.4.4 Other PCI Signals
Figure 5 shows the timing diagram characteristics, and Table 17 lists the other PCI
signals. This timing is identical to the timing for the general-purpose register
signals.
Figure 5 Timing Diagram for Other PCI Signals
Vtest 1
Clk
Tval (max)

Tval (min)

Output

Ton

Toff

Input
Th
Tsu
1 Vtest is 1.5 V in a 5.0-V signaling environment and is 0.4 * vdd_clamp
in a 3.3-V signaling environment.

LJ04719A.AI4

Electrical and Environmental Specifications

Serial, MII/SYM, Boot ROM, Serial ROM, and General-Purpose Port Interface

Table 17 Other PCI Signals
Symbol

Parameter

Minimum

Maximum

clk-to-signal valid delay

2 ns

11 ns

Ton2

Float-to-active delay from clk

2 ns

—

Toff

Active-to-float delay from clk

—

28 ns

Tsu

Input signal valid setup time before clk

7 ns

—

Input signal hold time from clk

0 ns

—

Tval

Load for this measurement is as specified in revisions 2.0 and 2.1 of the PCI Local Bus Specification.

Parameter design guarantee.

3.5 Serial, MII/SYM, Boot ROM, Serial ROM, and
General-Purpose Port Interface Specifications
Table 18 lists the specifications for the serial, MII /SYM, boot ROM, serial ROM,
and general-purpose port interfaces.
Table 18 Serial, MII/SYM, Boot ROM, Serial ROM, and General-Purpose Port
Symbol

Definition

Condition

Minimum

Maximum

Units

Voh

Output high voltage

Ioh = –4 mA

2.4

—

Vol

Output low voltage

Iol = 4 mA

—

0.4

Vih

Input high voltage

—

2.0

—

Vil

Input low voltage

—

0.8

Iin

Input current

Vin = Vcc or Vss

–10.0

10.0

Iip

Input leakage current on pin 0.0 <Vin< vdd
with internal pull-up resistor
(sr_do)

—

+20/–1000

Ioz2

Maximum tristate output
leakage current

–10.0

10.0

Vin = Vdd or Vss

µA
1

µA

For pin sr_do, which has an internal pull-up resistor, the maximum leakage current of 1 mA can occur when
Vin = 0 V.

For br_ce_l, the maximum value is 1000.0 µA.

Electrical and Environmental Specifications

Serial Network Port Timing

3.6 Serial Network Port Timing
This section describes the serial network port timing limits.

3.6.1 Serial 10-Mb/s Timing—Transmit
Figure 6 shows the serial network port transmit timing characteristics, and
Table 19 lists the serial network port transmit timing limits.
Figure 6 Serial Network Port Timing Diagram—Transmit
Ttcf

Ttcr
Ttch

Ttcl
srl_tclk

Ttcc
Ttdp

Ttdh

srl_txd<3:0>
Ttep

Tteh

srl_txen

LJ-05016.AI4

Electrical and Environmental Specifications

Serial Network Port Timing

Table 19 Serial Network Port Timing—Transmit
Symbol

Definition

Minimum Maximum Units

Ttcl

srl_tclk low time

Ttch

srl_tclk high time

srl_tclk rise time

—

Ttcf1

srl_tclk fall time

—

Ttdp

srl_tclk fall time to srl_txd valid

—

Ttdh

srl_txd hold after srl_tclk fall time

—

Ttep

srl_tclk fall time to srl_txen valid

—

Tteh

srl_txen hold after srl_tclk fall time 5

—

Ttcr

Parameter design guarantee.

3.6.2 Serial 10-Mb/s Timing—Collision
Figure 7 shows the serial network port collision timing characteristics, and
Table 20 lists the serial network port collision timing limit.
Figure 7 Serial Network Port Timing Diagram—Collision
srl_clsn

Tclh
LJ-04721.AI4

Table 20 Serial Network Port Timing—Collision
Symbol

Tclh
1

Definition

Minimum

Maximum

Units

srl_clsn high time

—

Parameter design guarantee.

Electrical and Environmental Specifications

Serial Network Port Timing

3.6.3 Serial 10 Mb/s Timing—Receive, Start of Packet
Figure 8 shows the serial network port timing characteristics in receive mode, start of
packet; and Table 21 lists the serial network port timing limits in receive mode, start
of packet.
Figure 8 Serial Network Port Timing Diagram—Receive, Start of Packet
Trcr
Trcl

Trcf
Trch

srl_rclk

Trds

Trcc

Trdh
srl_rxd

srl_rxen
LJ-04722.AI4

Electrical and Environmental Specifications

Serial Network Port Timing

3.6.4 Serial 10-Mb/s Timing—Receive, Start, and End of Packet
Figure 9 shows the serial network port timing characteristics in receive mode, end of
packet; and Table 21 lists the serial network port timing limits in receive mode, end
of packet.
Figure 9 Serial Network Port Timing Diagram—Receive, End of Packet
srl_rclk

srl_rxd

BIT N_1

BIT N

Treh
srl_rxen
Trel
LJ-04723.AI4

Table 21 Serial Network Port Timing—Receive, Start, and End of Packet
Symbol

Definition

Minimum Maximum Units

Trcc

srl_rclk cycle time

118

Trcl

srl_rclk low time

Trch

srl_rclk high time

Trcr1

srl_rclk rise time

—

Trcf

srl_rclk fall time

—

Trds

srl_rxd setup to srl_rclk fall time

—

Trdh

srl_rxd hold after srl_rclk fall time

—

Trel

srl_rxen low time

120

—

Treh

srl_rxen hold after srl_rclk rise time 10

100

Parameter design guarantee.

Electrical and Environmental Specifications

MII/SYM Port Timing

3.7 MII/SYM Port Timing
This section describes the MII/SYM port timing limits.

3.7.1 MII/SYM 10/100-Mb/s and 10-Mb/s Timing—Transmit
Figure 10 shows the MII/SYM port transmit timing characteristics, and Table 22 lists
the MII/SYM port transmit timing limits.
Figure 10 MII/SYM Port Timing Diagram—Transmit
Tcc
Tcr
Tch

Tcf
Tcl

mii/sym_tclk
Trv
mii/sym_txd<3:0>
Trh
mii/sym_txen
LJ-05017 .AI4

Electrical and Environmental Specifications

MII/SYM Port Timing

Table 22 MII/SYM Port Timing—Transmit
Symbol

Definition

Minimum Typical

Maximum

Units

1,2

mii/sym_tclk cycle time

—

40t

—

Tch2

mii/sym_tclk high time

14t

—

26t

mii/sym_tclk low time

14t

—

26t

Tcr

mii/sym_tclk rise time

—

Tcf

mii/sym_tclk fall time

—

Trv3

mii_tclk rise to mii_txen valid time or
mii/sym_tclk rise to mii/sym_txd valid time

—

Trh

mii_txen hold after mii_tclk rise time

—

Tcc

Tcl

±50 parts per million.

t = 1 for 100-Mb/s operation and t = 10 for 10-Mb/s operation.

Outputs transmit data (mii/sym_txd) and transmit enable (mii_txen) are driven internally from the rising edge of
mii/sym_tclk.

Electrical and Environmental Specifications

MII/SYM Port Timing

3.7.2 MII/SYM 10/100-Mb/s Timing—Receive
Figure 11 shows the MII/SYM port receive timing characteristics, and Table 23 lists
the MII/SYM port receive timing limits.
Figure 11 MII/SYM Port Timing Diagram—Receive
Tcc
Tcr
Tch

Tcf
Tcl

mii/sym_rclk
Tth

Tts
mii/sym_rxd<3:0>

mii_dv
LJ-05018.AI4

Table 23 MII/SYM Port Timing—Receive

(Sheet 1 of 2)

Symbol

Definition

Minimum Typical Maximum

Units

Tcc1,2

mii/sym_rclk cycle time

—

40t

—

Tch2

mii/sym_rclk high time

14t

—

26t

Tcl2

mii/sym_rclk low time

14t

—

26t

Tcr

mii/sym_rclk rise time

—

Tcf

mii/sym_rclk fall time

—

Electrical and Environmental Specifications

MII/SYM Port Timing

Table 23 MII/SYM Port Timing—Receive
Symbol

Tts

Tth4

(Sheet 2 of 2)

Definition

Minimum Typical Maximum

Units

mii/sym_rxd setup (both rise and fall
transactions) to mii/sym_rclk rise time or
mii_dv setup (both rise and fall transactions) to
mii_rclk rise time

—

mii/sym_rxd hold (both rise and fall transactions) after mii/sym_rclk rise time or mii_dv
hold (both rise and fall transactions) after
mii_rclk rise time

—

±50 parts per million.

t = 1 for 100-Mb/s operation and t = 10 for 10-Mb/s operation.

Inputs receive data (mii/sym_rxd) and data valid (mii_dv) are latched internally on the rising edge of
mii/sym_rclk.

Parameter design guarantee.

3.7.3 MII/SYM 10/100-Mb/s Timing—Signal Detect
Figure 12 shows the MII/SYM port signal detect timing characteristics, and Table 24
lists the MII/SYM port signal detect timing limits.
Figure 12 MII/SYM Port Timing Diagram—Signal Detect
sym_rclk

Tts

Tth

sd
LJ-03905.AI4

Table 24 MII/SYM Port Timing—Signal Detect
Symbol

Definition

Minimum

Maximum Units

Tts

sd1 setup (both rise and fall transactions) to sym_rclk fall time

—

Tth2

sd1 hold (both rise and fall transactions) 12
after sym_rclk fall time

—

Input signal detect (sd) is latched internally on the falling edge of sym_rclk.

Parameter design guarantee.

Electrical and Environmental Specifications

MII/SYM Port Timing

3.7.4 MII/SYM 10/100-Mb/s Timing—Receive Error
Figure 13 shows the MII/SYM port receive error timing characteristics, and
Table 25 lists the MII/SYM port receive error timing limits.
Figure 13 MII/SYM Port Timing Diagram—Receive Error
mii_rclk

Tts

Tth

sd
LJ-03906.AI4

Table 25 MII/SYM Port Timing—Receive Error
Symbol

Definition

Minimum

Maximum

Units

Tts

mii_err1 setup (both rise and fall
transactions) to mii_rclk rise time

—

Tth2

mii_err1 hold (both rise and fall
transactions) after mii_rclk rise time

—

Input receive error (mii_err) is latched internally on the rising edge of mii_rclk.

Parameter design guarantee.

3.7.5 MII/SYM 10/100-Mb/s Timing—Carrier Sense and Collision
Figure 14 shows the MII/SYM port carrier sense and collision timing characteristics,
and Table 26 lists the MII/SYM port carrier sense and collision timing limits.
Figure 14 MII/SYM Port Timing Diagram—Carrier Sense and Collision

mii_clsn
mii_crs

Tclh
LJ-03929.AI4

Table 26 MII/SYM Port Timing—Carrier Sense and Collision
Symbol

Definition

Minimum

Maximum

Units

Tclh

mii_crs, mii_clsn high time

—

Electrical and Environmental Specifications

Boot ROM Port Timing

3.8 Boot ROM Port Timing
This section describes the boot ROM port timing.

3.8.1 Boot ROM Read Timing
Figure 15 shows the boot ROM read timing characteristics, and Table 27 lists the
boot ROM read timing limits.
Figure 15 Boot ROM Read Timing Diagram
Tads

br_ad<7:0>

Tadh

Address = <7:2>
oe = 0, we = 1

Tads

Tadh

Tavqv

Data <7:0>
Valid

Address <15:8>

br_a<1>

br_a<0>

Address <1>

Address <17>

Address <16>

Address <0>

br_ce_l
Telqx

Toh
Telqv

Tehqz
Tavav

SCALE=89% LJ-0 5037.AI4

Table 27 Boot ROM Read Timing Specifications
Symbol Parameter

Minimum

Maximum

Units

Tavav

Read cycle time

120

—

Telqv

br_ce_l to output delay

—

120

br_ce_l to output enable

—

Telqx

Tehqz1 br_ce_l rising edge to output high impedance
1

Output hold from br_ce_l change

—

Tads

Address setup to latch enable high

—

Tadh

Address hold from latch enable high

—

Toh

Parameter design guarantee.

Electrical and Environmental Specifications

Boot ROM Port Timing

3.8.2 Boot ROM Write Timing
Figure 16 shows the boot ROM write timing characteristics, and Table 28 lists the
boot ROM write timing limits.
Figure 16 Boot ROM Write Timing Diagram
Tads

br_ad<7:0>

Tadh

Address = <7:2>
oe = 1, we = 0

Tads

Tadh

Address <15:8>

br_a<1>

br_a<0>

Data <7:0>

Address <1>

Address <17>

Address <16>

Address <0>

br_ce_l
Teleh

Tehdx

Tdveh

Tehax

Taveh
Tavav
LJ-05038.AI4

Table 28 Boot ROM Write Timing Specifications
Symbol

Parameter

Minimum

Maximum

Units

Tavav

Write cycle time

120

—

br_ce_l pulse width

—

Address setup to br_ce_l rising edge

—

Data setup to br_ce_l rising edge

—

Data hold from br_ce_l rising edge

—

Tehax

Address hold from br_ce_l high

—

Tads

Address setup to latch enable high

—

Tadh

Address hold from latch enable high

—

Teleh

Taveh1
Tdveh

Tehdx1
1

Parameter design guarantee.

Electrical and Environmental Specifications

Serial ROM Port Timing

3.9 Serial ROM Port Timing
Figure 17 shows the serial ROM port timing, and Table 29 lists the characteristics.
This timing is identical to the timing for the MII management signals (mii_mdio and
mii_mdc).
Figure 17 Serial ROM Port Timing Diagram

sr_cs,
sr_ck,
sr_di,
sr_do

Tsr

Tsf

LJ-03909.AI4

Table 29 Serial ROM Port Timing Characteristics
Symbol

Definition

Minimum

Maximum

Units

Tsr1

Rise time

—

Fall time

—

Tsf
1

Parameter design guarantee.

Electrical and Environmental Specifications

External Register Timing

3.10 External Register Timing
Figure 18 shows the external register read timing characteristics, and Figure 19
shows its write timing characteristics. Table 30 lists the external register timing
specifications for both read and write operations.
Figure 18 External Register Read Timing Diagram
br_ad<7:0>

Data Valid

br_a<0>

br_ce_l
Tpd

Tehqz

LJ-05039.AI4

Figure 19 External Register Write Timing Diagram
Data <7:0>

br_ad<7:0>

br_a<0>

br_ce_l
Teleh
Ts

Th
LJ-05040.AI4

Table 30 External Register Timing Specifications

(Sheet 1 of 2)

Symbol

Parameter

Minimum

Maximum

Units

Teleh

br_ce_l pulse width

120

—

Read Timing

Tpd

br_ce_l low to br_ad<7:0> valid

Electrical and Environmental Specifications

Joint Test Action Group—Test Access Port

Table 30 External Register Timing Specifications
Symbol
1

Tehqz

(Sheet 2 of 2)

Parameter

Minimum

Maximum

Units

br_ce_l high to br_ad<7:0> high
impedance

—

Write Timing

Data setup time prior to br_ce_l

—

Data hold after br_ce_l high

—

Parameter design guarantee.

3.11 Joint Test Action Group—Test Access Port
This section provides the joint test action group (JTAG) test access port
specifications.

3.11.1 JTAG DC Specifications
Table 31 lists the dc specifications for the JTAG pins.
Table 31 JTAG DC Specifications
Symbol Definition

Conditions

Minimum Maximum

Units

Voh

Output high voltage

Ioh = –4 mA

2.4

—

Vol

Output low voltage

Iol = 4 mA

—

0.4

Vih

Input high voltage

—

2.0

—

Vil

Input low voltage

—

0.8

Iip

Input leakage current on pins
with internal pull-up resistors
(tdi, tms)

0.0 <Vin< vdd

—

±20/–1000

Ioz

Tristate output leakage current
(tdo)

0.0 <Vout< vdd

—

±20

V
1

µA

For tdi and tms pins, which have internal pull-up resistors, the maximum leakage current of 1 mA can occur
when Vin = 0 V.

3.11.2 JTAG Boundary-Scan Timing
Figure 20 shows the JTAG boundary-scan timing, and Table 32 lists the interface
signal timing relationships.
Electrical and Environmental Specifications

Joint Test Action Group—Test Access Port

Figure 20 JTAG Boundary-Scan Timing Diagram
Tck_f

Tck_cycle

tck

Tck_r

Tms_s

Tms_h

Tdi_s

Tdi_h

tms

tdi
Tdo_d

tdo
LJ-03908.AI4

Table 32 JTAG Interface Signal Timing Relationships
Symbol

Parameter

Minimum

Maximum

Units

Tms_s

tms setup time

—

Tms_h

tms hold time

—

Tdi_s

tdi setup time

—

Tdi_h

tdi hold time

—

Tdo_d

tdo delay time

—

tck rise time

—

Tck_f1

tck fall time

—

Tck_cycle

tck cycle time

—

Tck_r

Parameter design guarantee.

Electrical and Environmental Specifications

4 Mechanical Specifications
The 21140A is contained in an industry standard 144-pin PQFP. Table 33 lists
the mechanical specifications, and Figure 21 shows the mechanical layout of
the 21140A.
Table 33 144-Pin PQFP Dimensional Attributes
Symbol

Dimension

Limit

Value (mm)

Package overall height

Maximum

4.10

Package standoff height

Minimum

0.25

Package thickness

Minimum
Maximum

3.17
3.67

Lead width

Minimum
Maximum

0.22
0.38

Lead thickness

Minimum
Maximum

0.12
0.23

ccc

Coplanarity

0.1
1

Package overall width

BSC

31.20

Package width

BSC

28.00

ddd

Lead skew

Package overall length

BSC

31.20

Package length

BSC

28.00

Lead pitch

BSC

0.65

Foot length

Minimum
Maximum

0.65
1.03

Lead length

Reference2

1.60

Ankle radius

Minimum
Maximum

0.13
0.3

0.13

ANSI Y14.5M-1982 American National Standard Dimensioning and Tolerancing, Section 1.3.2,
defines basic (BSC) dimension as: A numerical value used to describe the theoretically exact size,
profile, orientation, or location of a feature or datum target. It is the basis from which
permissible variations are established by tolerances on other dimensions, in notes, or in
feature control frames.

The value for this measurement is for reference only.

Mechanical Specifications

Figure 21 144-PIN PQFP Package
-AD
D1

Pin # Direction

Pin 1

144-Pin PQFP

E1 E

-B-

See Detail "A"

// 0.13 C
- H - Datum Plane
- C - Seating Plane
ddd M C A S B S
ccc C
Detail "A"

(A) A2
R

Note: All dimensions are in millimeters.
- Basic Dimension

(

L
(LL)

Mechanical Specifications

) - Reference Dimension

0 -7 c

LJ04510B .AI4

A Support, Products, and Documentation
To view current product update and errata revision information, please visit the
DIGITAL Semiconductor World Wide Web Internet site. You may also visit this
web site for technical support, a DIGITAL Semiconductor Product Catalog, or help
deciding which documentation best meets your needs:
http://www.digital.com/semiconductor

You can also contact the DIGITAL Semiconductor Information Line or the
DIGITAL Semiconductor Customer Technology Center for support.
For documentation and general information:
DIGITAL Semiconductor Information Line

United States and Canada:

1–800–332–2717

Outside North America:

1–510–490–4753

Electronic mail address:

semiconductor@digital.com

For technical support, product updates, and errata documentation:
DIGITAL Semiconductor Customer Technology Center

Phone (U.S. and international): 1–978–568–7474
Fax:

1–978–568–6698

Electronic mail address:

ctc@hlo.mts.dec.com

Support, Products, and Documentation

DIGITAL Semiconductor Products

To order the DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller
and Evaluation Boards, contact your local distributor. The following tables list some
of the semiconductor products available from DIGITAL Semiconductor.
Note:

The following products and order numbers might have been revised. For
the latest versions, contact your local distributor.

Product

Order Number

DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller

21140–AF

DIGITAL Semiconductor 21143 PCI/CardBus 10/100-Mb/s Ethernet LAN Controller (MQFP package)

21143–PD

DIGITAL Semiconductor 21143 PCI/CardBus 10/100-Mb/s Ethernet LAN Controller (LQFP package)

21143–TD

Evaluation board kits include an evaluation board, and can include a complete design
kit, an installation kit, or an accessories kit.
Evaluation Board Kits

Order Number

DIGITAL Semiconductor 21140A 10/100BASE–TX Evaluation Board Kit

21A40–TX

DIGITAL Semiconductor 21143 PCI 10/100BASE–TX Evaluation Board Kit

21A43–04

Support, Products, and Documentation

DIGITAL Semiconductor Documentation

The following table lists some of the available DIGITAL Semiconductor
documentation.
To determine which documents apply to a particular device part number, visit the
DIGITAL Semiconductor Documentation Library on DIGITAL Semiconductor’s
World Wide Web Internet site at:
http://ftp.digital.com/pub/digital/info/semiconductor/literature/dsc-library.html
Title

Order Number)

DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller
Hardware Reference Manual

EC–QN7NF–TE

DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller
Product Brief

EC–QN7MB–TE

DIGITAL Semiconductor 21143 PCI/CardBus 10/100-Mb/s Ethernet
LAN Controller Data Sheet

EC–QWC3F–TE

DIGITAL Semiconductor 21143 PCI/CardBus 10/100-Mb/s Ethernet
LAN Controller Hardware Reference Manual

EC–QWC4F–TE

DIGITAL Semiconductor 21143 PCI/CardBus 10/100-Mb/s Ethernet
LAN Controller Product Brief

EC–QWC2B–TE

DIGITAL Semiconductor 21143 Connection to the Network Using Physical Layer Devices: An Application Note

EC–QXY7A–TE

Third–Party Documentation

You can order the following third-party documentation directly from the vendor.
Title

Vendor

PCI Local Bus Specification, Revision 2.1
PCI Multimedia Design Guide, Revision 1.0
PCI System Design Guide
PCI-to-PCI Bridge Architecture Specification,
Revision 1.0
PCI BIOS Specification, Revision 2.1

PCI Special Interest Group
U.S.
1–800–433–5177
International 1–503–797–4207
Fax
1–503–234–6762

IEEE 802.3

The Institute of Electrical and
Electronics Engineers, Inc.
U.S.
1–800–701–4333
International 1–908–981–0060
Fax
1–908–981–9667

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