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EC-QN7PE-TE

November 1996

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Document:	Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller Data Sheet
Order Number:	EC-QN7PE-TE
Revision:
Pages:	62
Original Filename:	http://bitsavers.org/pdf/dec/semiconductor/ethernet/EC-QN7PE-TE_21140A_PCI_Fast_Ethernet_LAN_Controller_Data_Sheet_199611.pdf

OCR Text

Digital Semiconductor 21140A
PCI Fast Ethernet LAN Controller
Data Sheet
Order Number: EC–QN7PE–TE
Revision/Update Information:

Digital Equipment Corporation
Maynard, Massachusetts

This preliminary document supersedes
the Digital Semiconductor 21140A PCI
Fast Ethernet LAN Controller Data Sheet
(EC–QN7PD–TE).

November 1996
While Digital believes the information included in this publication is correct as of the date of
publication, it is subject to change without notice.
Digital Equipment Corporation makes no representations that the use of its products in the
manner described in this publication will not infringe on existing or future patent rights, nor do
the descriptions contained in this publication imply the granting of licenses to make, use, or sell
equipment or software in accordance with the description.
© Digital Equipment Corporation 1996.
Printed in U.S.A.

Digital, Digital Semiconductor, and the DIGITAL logo are trademarks of Digital Equipment
Corporation.
Digital Semiconductor is a Digital Equipment Corporation business.
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
MicroWire is a registered trademark of BankAmerica Corporation.
All other trademarks and registered trademarks are the property of their respective owners.

Contents
1
1.1
1.2
1.3
1.4
2
2.1
2.2
2.3
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5

21140A Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21140A Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unique Feature of the 21140–AE . . . . . . . . . . . . . . . . . . . . . .
Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Reference Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Grouping by Function . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical and Environmental Specifications . . . . . . . . . . . . . . . .
Voltage Limit Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Limit Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Current and Power Dissipation . . . . . . . . . . . . . . . . .
PCI I/O Voltage Specifications . . . . . . . . . . . . . . . . . . . . .
PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
Other PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial, MII/SYM, Boot ROM, Serial ROM, and
General-Purpose Port Interface Specifications . . . . . . . . . . .
Serial Network Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial 10-Mb/s Timing—Transmit . . . . . . . . . . . . . . . . . .
Serial 10-Mb/s Timing—Collision . . . . . . . . . . . . . . . . . . .
Serial 10 Mb/s Timing—Receive, Start of Packet . . . . . . .
Serial 10-Mb/s Timing—Receive, End of Packet . . . . . . . .
MII/SYM Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM 10/100-Mb/s and 10-Mb/s Timing—Transmit . .
MII/SYM 10/100-Mb/s Timing—Receive . . . . . . . . . . . . . .
MII/SYM 10/100-Mb/s Timing—Signal Detect . . . . . . . . .
MII/SYM 10/100-Mb/s Timing—Receive Error . . . . . . . . .
MII/SYM 10/100-Mb/s Timing—Carrier Sense and
Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1
1
2
3
3
6
8
19
21
23
23
23
24
24
26
27
28
30
30
31
32
33
33
34
35
36
38
39
40

iii

3.7
Boot ROM Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1
Boot ROM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.2
Boot ROM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
Serial ROM Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9
External Register Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10
Joint Test Action Group—Test Access Port . . . . . . . . . . . . . .
3.10.1
JTAG dc Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.2
JTAG Boundary-Scan Timing . . . . . . . . . . . . . . . . . . . . .
4
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

41
41
43
45
46
48
48
48
50

A Support, Products, and Documentation
A.1
A.2
A.3

Ordering Digital Semiconductor Products . . . . . . . . . . . . . . . . . .
Ordering Digital Semiconductor Documentation . . . . . . . . . . . . .
Ordering Third-Party Documentation . . . . . . . . . . . . . . . . . . . . .

A–1
A–2
A–3

21140A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21140A Pinout Diagram (Top View) . . . . . . . . . . . . . . . . . . .
PCI Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Clock Specification Timing Diagram . . . . . . . . . . . . . . . .
Timing Diagram for Other PCI Signals . . . . . . . . . . . . . . . . .
Serial Network Port Timing Diagram—Transmit . . . . . . . . .
Serial Network Port Timing Diagram—Collision . . . . . . . . . .
Serial Network Port Timing Diagram—Receive, Start of
Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Network Port Timing Diagram—Receive, End of
Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing Diagram—Transmit . . . . . . . . . . . . . .
MII/SYM Port Timing Diagram—Receive . . . . . . . . . . . . . . .
MII/SYM Port Timing Diagram—Signal Detect . . . . . . . . . . .
MII/SYM Port Timing Diagram—Receive Error . . . . . . . . . . .
MII/SYM Port Timing Diagram—Carrier Sense and
Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot ROM Read Timing Diagram . . . . . . . . . . . . . . . . . . . . .
Boot ROM Write Timing Diagram . . . . . . . . . . . . . . . . . . . . .
Serial ROM Port Timing Diagram . . . . . . . . . . . . . . . . . . . . .
External Register Read Timing Diagram . . . . . . . . . . . . . . . .

5
7
26
27
28
31
32

Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

33
34
35
36
38
39
40
41
43
45
46

19
20
21

External Register Write Timing Diagram . . . . . . . . . . . . . . .
JTAG Boundary-Scan Timing Diagram . . . . . . . . . . . . . . . . .
144-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

46
49
51

Index to Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description of 21140A Signals . . . . . . . . . . . . . . .
Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Drain Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Limit Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Limit Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Current and Power Dissipation . . . . . . . . . . . . . . . . .
I/O Voltage Specifications for 5.0-V Levels . . . . . . . . . . . . . . .
I/O Voltage Specifications for 3.3-V Levels . . . . . . . . . . . . . . .
PCI Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial, MII/SYM, Boot ROM, Serial ROM, and
General-Purpose Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Network Port Timing—Transmit . . . . . . . . . . . . . . . . .
Serial Network Port Timing—Collision . . . . . . . . . . . . . . . . .
Serial Network Port Timing—Receive, Start, and End of
Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing—Transmit . . . . . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing—Receive . . . . . . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing—Signal Detect . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing—Receive Error . . . . . . . . . . . . . . . . . .
MII/SYM Port Timing—Carrier Sense and Collision . . . . . . .
Boot ROM Read Timing Specifications . . . . . . . . . . . . . . . . .
Boot ROM Write Timing Specifications . . . . . . . . . . . . . . . . .
Serial ROM Port Timing Characteristics . . . . . . . . . . . . . . . .

6
8
9
10
19
20
20
20
21
23
23
24
24
25
26
27
29

Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

30
31
32
34
35
37
38
39
40
42
44
45

30
31
32
33

External Register Timing Specifications . . . . . . . . . . . . . . . .
JTAG dc Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Interface Signal Timing Relationships . . . . . . . . . . . .
144-Pin PQFP Package Dimensions . . . . . . . . . . . . . . . . . . . .

47
48
49
50

1 21140A Overview
The Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller (21140A)
supports the peripheral component interconnect (PCI) bus. It provides a direct
interface connection to the PCI and adapts easily to most other standard buses.
The 21140A software interface and data structures are optimized to minimize
the host CPU load and to allow for maximum flexibility in the buffer descriptor
management. The 21140A contains large onchip FIFOs, so no additional
onboard memory is required. The 21140A provides an upgradable boot ROM
interface.
The 21140A has several additional features that are not available on the
21140, yet it remains pin and software compatible with the 21140.

1.1 General Description
The 21140A interfaces with the PCI bus by using onchip control and status
registers (CSRs), and a shared CPU memory area that is set up mainly
during initialization. This minimizes the processor involvement in the 21140A
operation during normal reception and transmission. Traffic on the PCI bus
is also minimized by filtering out received runt frames and by automatically
retransmitting collided frames without needing to repeat a fetch from shared
memory. The 21140A is compliant with revisions 2.0 and 2.1 of the PCI Local
Bus Specification.
On the network side, the 21140A provides two ports: a serial standard 7-wire
(SRL) 10-Mb/s port and a media-independent interface/symbol (MII/SYM)
10/100-Mb/s port. The 10-Mb/s port provides a direct interface to the external
10-Mb/s front-end decoder (ENDEC). The 10/100-Mb/s port supports two
operational modes:
•

A direct interface to the external 10/100-Mb/s ENDEC. The 21140A
includes the onchip physical coding sublayer (PCS) and the scrambler for
efficient 100BASE-T (CAT5 cable) implementation.

•

A full implementation of the MII standard.

The 21140A is also capable of functioning in a full-duplex environment for both
the 10-Mb/s and 10/100-Mb/s ports.

Preliminary—Subject to Change—November 1996

1.2 21140A Features
All 21140A devices have the following features:
•

Offers a single-chip Fast Ethernet controller for PCI local bus:
Provides a glueless connection to the PCI bus
Supports two network ports: 10 Mb/s and 10/100 Mb/s

•

Provides a standard 10/100-Mb/s MII supporting CAT3 unshielded twistedpair (UTP), CAT5 UTP, shielded twisted-pair (STP) and fiber cables

•

Contains onchip scrambler and PCS for CAT5 to significantly reduce cost of
100BASE-T solutions

•

Supports full-duplex operation on both 10-Mb/s and 10/100-Mb/s ports

•

Provides external and internal loopback capability on both ports

•

Contains a variety of flexible address filtering modes (including perfect,
hash tables, inverse perfect, and promiscuous):
16 perfect addresses (normal or inverse filtering)
512 hash-filtered addresses
512 hash-filtered multicast addresses and one perfect address
Pass all multicast
Promiscuous
Pass all incoming packets with a status report1

•

Offers a unique, patented solution to Ethernet capture-effect problem

•

Contains large independent receive and transmit FIFOs; no additional
onboard memory required

•

Includes a powerful onchip direct memory access (DMA) with
programmable burst size providing for low CPU utilization

•

Implements unique, patent-pending intelligent arbitration between DMA
channels preventing underflow or overflow

•

Supports PCI clock frequency from dc to 33 MHz; network operational with
PCI clock from 20 MHz to 33 MHz

•

Supports an unlimited PCI burst

•

Supports PCI read multiple command1

Indicates 21140A features that are not available on the 21140.

2 Preliminary—Subject to Change—November 1996

•

Supports early interrupts on transmit and receive for improved
performance1

•

Implements low-power management with two power-saving modes (sleep or
snooze)1

•

Supports both PCI 5.0-V and 3.3-V signaling environments1

•

Supports either big or little endian byte ordering for buffers and descriptors

•

Contains 8-bit, general-purpose, programmable register and corresponding
I/O pins

•

Provides LED support for various network activity indications

•

Provides MicroWire interface for serial ROM (1K and 4K EEPROM)

•

Provides an upgradable boot ROM interface of up to 256KB1

•

Supports automatic loading of subsystem vendor ID and subsystem ID
from serial ROM to configuration register1

•

Implements JTAG-compatible test-access port with boundary-scan pins

•

Supports IEEE 802.3, ANSI 8802-3, and Ethernet standards

•

Implements low-power, 3.3-V complementary metal-oxide semiconductor
(CMOS) process technology

1.3 Unique Feature of the 21140–AE
In addition to the features previously listed, the 21140–AE has the following
feature:
•

Supports PCI write and invalidate, and read line commands

1.4 Microarchitecture
The following list describes the 21140A hardware components, and Figure 1
shows a block diagram of the 21140A:
•

PCI interface—Includes all interface functions to the PCI bus; handles all
interconnect control signals; and executes PCI DMA and I/O transactions.

•

DMA—Contains dual receive and transmit controller; handles data
transfers between CPU memory and onchip memory.

•

FIFOs—Contains two FIFOs for receive and transmit; supports automatic
packet deletion on receive (runt packets or after a collision) and packet
retransmission after a collision on transmit.

Indicates 21140A features that are not available on the 21140.

Preliminary—Subject to Change—November 1996

•

TxM—Handles all CSMA/CD2 MAC3 transmit operations, and transfers
data from transmit FIFO to the ENDEC for transmission.

•

RxM—Handles all CSMA/CD receive operations, and transfers the data
from the ENDEC to the receive FIFO.

•

Physical coding sublayer—Implements the encoding and decoding sublayer
of the 100BASE-TX (CAT5) specification, including the squelch.

•

Scrambler/descrambler—Implements the twisted-pair physical layer
medium dependent (TP-PMD) scrambler/descrambler scheme.

•

General-purpose register—Enables software to use for input or output
functions.

•

Serial interface—Provides a 7-wire conventional interface to the Ethernet
ENDEC components.

•

MII/SYM interface—Provides a full MII signal interface and a direct
interface to the 10/100-Mb/s ENDEC for CAT5.

•

Serial ROM port—Provides a direct interface to the MicroWire ROM for
storage of the Ethernet address and system parameters.

•

Boot ROM port—Provides an interface to perform read and write
operations to the boot ROM; supports accesses to bytes or longword
(32-bit). Also provides the ability to connect an external 8-bit register to
the boot ROM port.

2
3

Carrier-sense multiple access with collision detection
Media access control

4 Preliminary—Subject to Change—November 1996

Figure 1 21140A Block Diagram
Boot ROM/
External
Register

Serial
ROM

Board
Control
Signals

PCI
Interface

Boot
ROM
Port

Serial
ROM
Port

GeneralPurpose
Register

PCI

DMA
32

Rx
FIFO

Tx
FIFO
16

16
RxM

TxM

4
4

Physical Coding
Sublayer
4
1

4
Scrambler/
Descrambler

Serial Interface

MII/SYM Interface

10 Mb/s

10 Mb/s or 100 Mb/s

LJ-05042.AI4

Preliminary—Subject to Change—November 1996

2 Pinout
The 21140A is packaged in a 144-pin plastic quad flat pack (PQFP). The tables
in this section provide a description of the pins and their respective signal
definitions.
Table 1 lists the tables in this section. Figure 2 shows the 21140A pinout.
Table 1 Index to Pinout Tables
For this information . . .

Refer to . . .

Logic signals

Table 2

Power pins

Table 3

Functional signals description

Table 4

Input pins

Table 5

Output pins

Table 6

Input/output pins

Table 7

Open drain pins

Table 8

Signal functions

Table 9

6 Preliminary—Subject to Change—November 1996

tdo
tdi
tms
tck
srl_txen
srl_tclk
srl_txd
srl_rclk
srl_rxen
srl_rxd
srl_clsn
mii/srl
sym_txd<4>
mii/sym_txd<3>
mii/sym_txd<2>
vdd
vss
mii/sym_txd<1>
mii/sym_txd<0>
mii/sym_txen
sym_link
mii/sym_tclk
rcv_match
vdd
vss
sym_rxd<4>
mii/sym_rxd<3>
mii/sym_rxd<2>
mii/sym_rxd<1>
mii/sym_rxd<0>
mii/sym_rclk
mii_crs
mii_clsn
mii_dv
mii_err
sd

Figure 2 21140A Pinout Diagram (Top View)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

21140A

108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

vss
vdd
mii_mdc
mii_mdio
nc
br_a<1>
br_a<0>
br_ce_l
br_ad<7>
br_ad<6>
vdd
vss
br_ad<5>
br_ad<4>
br_ad<3>
br_ad<2>
br_ad<1>
br_ad<0>
vss
gep<7>
gep<6>
gep<5>
gep<4>
vdd
vss
gep<3>
gep<2>
gep<1>
gep<0>
sr_cs
sr_ck
sr_di
sr_do
vdd
vss
vdd_clamp

3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7
7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2
vss
c_be_l<2>
frame_l
irdy_l
trdy_l
devsel_l
stop_l
vdd
perr_l
serr_l
par
c_be_l<1>
vss
ad<15>
ad<14>
ad<13>
vss
ad<12>
ad<11>
vdd
ad<10>
ad<9>
vss
ad<8>
c_be_l<0>
ad<7>
ad<6>
vss
ad<5>
ad<4>
vdd
ad<3>
ad<2>
vss
ad<1>
ad<0>

int_l
rst_l
vdd
vss
pci_clk
vdd
gnt_l
req_l
vss
ad<31>
ad<30>
vss
ad<29>
ad<28>
vss
ad<27>
ad<26>
vdd
ad<25>
ad<24>
c_be_l<3>
idsel
vss
ad<23>
ad<22>
ad<21>
ad<20>
vdd
ad<19>
ad<18>
vdd
vss
vss
ad<17>
ad<16>
vss

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0
4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9

LJ-04479.AI5

Preliminary—Subject to Change—November 1996

2.1 Signal Reference Tables
Table 2 provides an alphabetical list of the 21140A logic names and their pin
numbers. Table 3 provides a list of the 21140A power pin numbers.
Table 2 Logic Signals
Signal

Pin
Number

Signal

Pin
Number

Signal

Pin
Number

ad<0>

ad<24>

frame_l

ad<1>

ad<25>

gep<0>

ad<2>

ad<26>

gep<1>

ad<3>

ad<27>

gep<2>

ad<4>

ad<28>

gep<3>

ad<5>

ad<29>

gep<4>

ad<6>

ad<30>

gep<5>

ad<7>

ad<31>

gep<6>

ad<8>

br_a<0>

102

gep<7>

ad<9>

br_a<1>

103

gnt_l

ad<10>

br_ad<0>

idsel

ad<11>

br_ad<1>

int_l

ad<12>

br_ad<2>

irdy_l

ad<13>

br_ad<3>

mii_clsn

112

ad<14>

br_ad<4>

mii_crs

113

ad<15>

br_ad<5>

mii_dv

111

ad<16>

br_ad<6>

mii_err

110

ad<17>

br_ad<7>

100

mii_mdc

106

ad<18>

br_ce_l

101

mii_mdio

105

ad<19>

c_be_l<0 >

mii/srl

133

ad<20>

c_be_l<1 >

mii/sym_rclk

114

ad<21>

c_be_l<2 >

mii/sym_rxd<0>

115

ad<22>

c_be_l<3 >

mii/sym_rxd<1>

116

ad<23>

devsel_l

mii/sym_rxd<2>

117

(continued on next page)

8 Preliminary—Subject to Change—November 1996

Table 2 (Cont.) Logic Signals
Signal

Pin
Number

Signal

Pin
Number

Signal

Pin
Number

mii/sym_rxd<3>

118

req_l

srl_tclk

139

mii/sym_tclk

123

rst_l

srl_txd

138

mii/sym_txd<0>

126

109

srl_txen

140

mii/sym_txd<1>

127

serr_l

stop_l

mii/sym_txd<2>

130

sr_ck

sym_link

124

mii/sym_txd<3>

131

sr_cs

sym_rxd<4>

119

mii/sym_txen

125

sr_di

sym_txd<4>

132

104

sr_do

tck

141

par

srl_clsn

134

tdi

143

pci_clk

srl_rclk

137

tdo

144

perr_l

srl_rxd

135

tms

142

rcv_match

122

srl_rxen

136

trdy_l

Table 3 Power Pins
Signal
vdd (3.3 V)

Pin Numbers

Signal

3, 6, 18, 28,

vss (Gnd)

Pin Numbers
4, 9, 12, 15,

31, 44, 56, 67,

23, 32, 33, 36,

75, 85, 98, 107,

37, 49, 53, 59,

121, 129

64, 70, 74, 84,
90, 97, 108,
120, 128

vdd_clamp (5.0 V
or 3.3 V)

Preliminary—Subject to Change—November 1996

Table 4 provides a functional description of each of the 21140A signals. These
signals are listed alphabetically. The functional grouping of each pin is listed
in Section 2.3.
The following terms describe the 21140A pinout:
•

Address phase
Address and appropriate bus commands are driven during this cycle.

•

Data phase
Data and the appropriate byte enable codes are driven during this cycle.

•

_l
All pin names with the _l suffix are asserted low.

The following abbreviations are used in Table 4:
I = Input
O = Output
I/O = Input/output
O/D = Open drain
P = Power
Table 4 Functional Description of 21140A Signals
Pin
Number

Signal

Type

Description

ad<31:0>

I/O

See
Table 2.

32-bit PCI address and data lines. Address
and data bits are multiplexed on the same
pins. During the first clock cycle of a
transaction, the address bits contain a
physical address (32 bits). During subsequent
clock cycles, these same lines contain 32 bits
of data. A 21140A bus transaction consists
of an address phase followed by one or more
data phases. The 21140A supports both read
and write bursts (in master operation only).
Little and big endian byte ordering can be
used.

br_a<0>

102

Boot ROM address line bit 0. In a 256KB
configuration, this pin also carries in two
consecutive address cycles, boot ROM address
bits 16 and 17.
(continued on next page)

10 Preliminary—Subject to Change—November 1996

Table 4 (Cont.) Functional Description of 21140A Signals
Signal

Type

Pin
Number

br_a<1>

103

Boot ROM address line bit 1. This pin also
latches the boot ROM address and control
lines by the two external latches.

br_ad<7:0>

I/O

See
Table 2.

Boot ROM address and data multiplexed
lines bits 7 through 0. In the first of two
consecutive address cycles, these lines contain
the boot ROM address bits 7 through 2, oe_l
and we_l; followed by boot ROM address bits
15 through 8 in the second cycle. During the
data cycle, bits 7 through 0 contain data.

Description

During operation with the external register,
these lines are used to carry data bits 7
through 0 to and from the external register.
br_ce_l

101

Boot ROM or external register chip enable.
This pin has an internal 5 k pull-up resistor.

c_be_l<3:0>

I/O

See
Table 2.

Bits 0 through 3 of the bus command and byte
enable lines. Bus command and byte enable
are multiplexed on the same PCI pins.
During the address phase of the transaction,
these 4 bits provide the bus command.
During the data phase, these 4 bits provide
the byte enable. The byte enable determines
which byte lines carry valid data. For
example, bit 0 applies to byte 0, and bit 3
applies to byte 3.

devsel_l

I/O

Device select is asserted by the target of the
current bus access. When the 21140A is the
initiator of the current bus access, it expects
the target to assert devsel_l within five bus
cycles, confirming the access. If the target
does not assert devsel_l within the required
bus cycles, the 21140A aborts the cycle. To
meet the timing requirements, the 21140A
asserts this signal in a medium speed (within
two bus cycles).
(continued on next page)

Preliminary—Subject to Change—November 1996

Table 4 (Cont.) Functional Description of 21140A Signals
Signal

Type

Pin
Number

frame_l

I/O

The frame_l signal is driven by the 21140A
(bus master) to indicate the beginning and
duration of an access. The frame_l signal
asserts to indicate the beginning of a bus
transaction. While frame_l is asserted,
data transfers continue. The frame_l signal
deasserts to indicate that the next data phase
is the final data phase transaction.

gep<7:0>

I/O

See
Table 2.

General-purpose pins can be used by software
as either status pins or control pins. These
pins can be configured by software to perform
either input or output functions.

gnt_l

Bus grant asserts to indicate to the 21140A
that access to the bus is granted.

idsel

Initialization device select asserts to indicate
that the host is issuing a configuration cycle
to the 21140A.

int_l

O/D

Interrupt request asserts when one of the
appropriate bits of CSR5 sets and causes an
interrupt, provided that the corresponding
mask bit in CSR7 is not asserted. Interrupt
request deasserts by writing a 1 into the
appropriate CSR5 bit.

Description

If more than one interrupt bit is asserted in
CSR5 and the host does not clear all input
bits, the 21140A deasserts int_l for one cycle
to support edge-triggered systems.
This pin must be pulled up by an external
resistor.
(continued on next page)

12 Preliminary—Subject to Change—November 1996

Table 4 (Cont.) Functional Description of 21140A Signals
Signal

Type

Pin
Number

irdy_l

I/O

Description
Initiator ready indicates the bus master’s
ability to complete the current data phase of
the transaction.
A data phase is completed on any rising edge
of the clock when both irdy_l and target
ready trdy_l are asserted. Wait cycles are
inserted until both irdy_l and trdy_l are
asserted together.
When the 21140A is the bus master, irdy_l is
asserted during write operations to indicate
that valid data is present on the 32-bit ad
lines. During read operations, the 21140A
asserts irdy_l to indicate that it is ready to
accept data.

mii_clsn

112

Collision detected is asserted when detected
by an external physical layer protocol (PHY)
device.

mii_crs

113

Carrier sense is asserted by the PHY when
the media is active.

mii_dv

111

Data valid is asserted by an external
PHY when receive data is present on the
mii/sym_rxd lines and is deasserted at the
end of the packet. This signal should be
synchronized with the mii/sym_rclk signal.

mii_err

110

Receive error asserts when a data decoding
error is detected by an external PHY device.
This signal is synchronized to mii/sym_rclk
and can be asserted for a minimum of one
receive clock. When asserted during a packet
reception, it sets the cyclic redundancy check
(CRC) error bit in the receive descriptor
(RDES0).

mii_mdc

106

MII management data clock is sourced by
the 21140A to the PHY devices as a timing
reference for the transfer of information on
the mii_mdio signal.
(continued on next page)

Preliminary—Subject to Change—November 1996

Table 4 (Cont.) Functional Description of 21140A Signals
Signal

Type

Pin
Number

mii_mdio

I/O

105

MII management data input/output transfers
control information and status between the
PHY and the 21140A.

mii/srl

133

Indicates the selected port: SRL or MII/SYM.
When asserted, the MII/SYM port is active.
When deasserted, the SRL port is active.

mii/sym_rclk

114

Supports either the 25-MHz or 2.5-MHz
receive clock. This clock is recovered by the
PHY.

mii/sym_
rxd<3:0>

See
Table 2.

Four parallel receive data lines when MII
mode is selected. This data is driven by
an external PHY that attached the media
and should be synchronized with the
mii/sym_rclk signal.

mii/sym_tclk

123

Supports the 25-MHz or 2.5-MHz transmit
clock supplied by the external physical layer
medium dependent (PMD) device. This clock
should always be active.

mii/sym_
txd<3:0>

See
Table 2.

Four parallel transmit data lines. This
data is synchronized to the assertion of
the mii/sym_tclk signal and is latched by
the external PHY on the rising edge of the
mii/sym_tclk signal.

mii_txen

125

Transmit enable signals that the transmit
is active to an external PHY device. In PCS
mode (CSR6<23>), this signal reflects the
transmit activity of the MAC sublayer.

104

No connection.

par

I/O

Parity is calculated by the 21140A as an even
parity bit for the 32-bit ad and 4-bit c_be_l
lines.

Description

During address and data phases, parity is
calculated on all the ad and c_be_l lines
whether or not any of these lines carry
meaningful information.
(continued on next page)

14 Preliminary—Subject to Change—November 1996

Table 4 (Cont.) Functional Description of 21140A Signals
Signal

Type

Pin
Number

pci_clk

The clock provides the timing for the 21140A
related PCI bus transactions. All the bus
signals are sampled on the rising edge
of pci_clk. The clock frequency range is
between 25 MHz and 33 MHz.

perr_l

I/O

Parity error asserts when a data parity error
is detected.

Description

When the 21140A is the bus master and a
parity error is detected, the 21140A asserts
both CSR5 bit 13 (system error) and CFCS
bit 24 (data parity report). Next, it completes
the current data burst transaction, then stops
operation. After the host clears the system
error, the 21140A continues its operation.
The 21140A asserts perr_l when a data
parity error is detected in either master-read
or slave-write operations.
This pin must be pulled up by an external
resistor.
rcv_match

122

Receive match indication is asserted when
a received packet has passed address
recognition.

req_l

Bus request is asserted by the 21140A to
indicate to the bus arbiter that it wants to use
the bus.

rst_l

Resets the 21140A to its initial state. This
signal must be asserted for at least 10 active
PCI clock cycles. When in the reset state, all
PCI output pins are put into tristate and all
PCI O/D signals are floated.

109

Signal detect indication supplied by an
external physical layer medium dependent
(PMD) device.
(continued on next page)

Preliminary—Subject to Change—November 1996

Table 4 (Cont.) Functional Description of 21140A Signals
Signal

Type

Pin
Number

serr_l

O/D

Description
If an address parity error is detected and
CFCS bit 8 (serr_l enable) is enabled, the
21140A asserts both serr_l (system error) and
CFCS bit 30 (signal system error).
When an address parity error is detected,
system error asserts two clocks after the
failing address.
This pin must be pulled up by an external
resistor.

sr_ck

Serial ROM clock signal.

sr_cs

Serial ROM chip-select signal. This pin has
an internal 2 k pull-down resistor.

sr_di

Serial ROM data-in signal.

sr_do

Serial ROM data-out signal. This pin has an
internal 5 k pull-up resistor.1

srl_clsn

134

Collision detect signals a collision occurrence
on the Ethernet cable to the 21140A. It may
be asserted and deasserted asynchronously by
the external ENDEC to the receive clock.

srl_rclk

137

Receive clock carries the recovered receive
clock supplied by an external ENDEC. During
idle periods, srl_rclk may be inactive.

srl_rxd

135

Receive data carries the input receive data
from the external ENDEC. The incoming
data should be synchronous with the srl_rclk
signal.

srl_rxen

136

Receive enable signals activity on the
Ethernet cable to the 21140A. It is asserted
when receive data is present on the Ethernet
cable and is deasserted at the end of a
frame. It may be asserted and deasserted
asynchronously to the receive clock (srl_rclk)
by the external ENDEC.

1 The value of this resistor was 12 k

for the 21140–AC.

(continued on next page)

16 Preliminary—Subject to Change—November 1996

Table 4 (Cont.) Functional Description of 21140A Signals
Signal

Type

Pin
Number

srl_tclk

139

Transmit clock carries the transmit clock
supplied by an external ENDEC. This clock
must always be active (even during reset).

srl_txd

138

Transmit data carries the serial output data
from the 21140A. This data is synchronized to
the srl_tclk signal.

srl_txen

140

Transmit enable signals an external ENDEC
that the 21140A transmit is in progress.

stop_l

I/O

Stop indicator indicates that the current
target is requesting the bus master to stop the
current transaction.

Description

The 21140A responds to the assertion of
stop_l when it is the bus master, either to
disconnect, retry, or abort.
sym_link

124

Indicates that the descrambler is locked to the
input data signal.

sym_rxd<4>

119

Receive data, together with the four receive
lines mii/sym_rxd<3:0>, provide five parallel
lines of data in symbol form for use in PCS
mode (100BASE-T, CSR6<23>). This data is
driven by an external PMD device and should
be synchronized to the mii/sym_rclk signal.

sym_txd<4>

132

Transmit data, together with the four
transmit lines mii/sym_txd<3:0>, provide
five parallel lines of data in symbol form for
use in PCS mode (100BASE-T, CSR6<23>).
This data is synchronized on the rising edge
of the mii/sym_tclk signal.

tck

141

JTAG clock shifts state information and test
data into and out of the 21140A during JTAG
test operations. This pin has an internal
5 k pull-up resistor1 and should not be left
unconnected.

1 The value of this resistor was 12 k

for the 21140–AC.

(continued on next page)

Preliminary—Subject to Change—November 1996

Table 4 (Cont.) Functional Description of 21140A Signals
Signal

Type

Pin
Number

tdi

143

JTAG data in is used to serially shift test data
and instructions into the 21140A during JTAG
test operations. This pin has an internal
5 k pull-up resistor1 and should not be left
unconnected.

tdo

144

JTAG data out is used to serially shift test
data and instructions out of the 21140A
during JTAG test operations.

tms

142

JTAG test mode select controls the state
operation of JTAG testing in the 21140A. This
pin has an internal 5 k pull-up resistor1 and
should not be left unconnected.

trdy_l

I/O

Target ready indicates the target agent’s
ability to complete the current data phase of
the transaction.

Description

A data phase is completed on any clock when
both trdy_l and irdy_l are asserted. Wait
cycles are inserted until both irdy_l and
trdy_l are asserted together.
When the 21140A is the bus master, target
ready is asserted by the bus slave on the
read operation, indicating that valid data is
present on the ad lines. During a write cycle,
it indicates that the target is prepared to
accept data.
vdd

See
Table 3.

3.3-V supply input voltage.

vdd_clamp

5.0-V reference for 5.0-V signaling environments and 3.3 V for 3.3-V signaling
environments.

vss

See
Table 3.

Ground pins.

1 The value of this resistor was 12 k

for the 21140–AC.

18 Preliminary—Subject to Change—November 1996

2.2 Pin Tables
This section contains four types of pin tables:
•

Table 5 lists the input pins.

•

Table 6 lists the output pins.

•

Table 7 lists the input/output pins.

•

Table 8 lists the open drain pins.

Table 5 Input Pins
Active

Active

Signal

Level

Signal

Level

gnt_l

Low

High

idsel

High

sr_do

High

mii_clsn

High

srl_clsn

High

mii_crs

High

srl_rclk

—

mii_dv

High

srl_rxd

—

mii_err

High

srl_rxen

High

mii/sym_rclk

—

srl_tclk

—

mii/sym_rxd<3:0>

—

sym_rxd<4>

—

mii/sym_tclk

—

tck

—

pci_clk

—

tdi

—

rst_l

Low

tms

High

Preliminary—Subject to Change—November 1996

Table 6 Output Pins
Active

Active

Signal

Level

Signal

Level

br_a<0>

High

req_l

Low

br_a<1>

High

sr_ck

—

br_ce_l

Low

sr_cs

High

mii_mdc

—

sr_di

High

mii/srl

—

srl_txd

—

mii/sym_txd<3:0>

—

srl_txen

High

mii_txen

High

sym_link

High

—

sym_txd<4>

—

rcv_match

High

tdo

High

Table 7 Input/Output Pins
Active

Active

Signal

Level

Signal

Level

ad<31:0>

—

irdy_l

Low

br_ad<7:0>

—

mii_mdio

—

c_be_l<3:0>

Low

par

—

devsel_l

Low

perr_l

Low

frame_l

Low

stop_l

Low

gep<7:0>

—

trdy_l

Low

Table 8 Open Drain Pins
Active

Active

Signal

Level

Signal

Level

int_l

Low

serr_l

Low

20 Preliminary—Subject to Change—November 1996

2.3 Signal Grouping by Function
Table 9 lists the signals according to their interface function.
Table 9 Signal Functions
Interface

Function

Signal

PCI

Address and data

ad<31:0>, par

Arbitration

gnt_l, req_l

Bus command and byte
enable

c_be_l<3:0>

Device select

devsel_l, idsel

Error reporting

perr_l, serr_l

Interrupt

int_l

System

pci_clk, rst_l

Control signals

frame_l, stop_l, irdy_l, trdy_l

MII/symbol

Transmit data lines

mii/sym_txd<3:0>

Network port

Receive data lines

mii/sym_rxd<3:0>

Transmit, receive clocks

mii/sym_tclk, mii/sym_rclk

SYM mode

sym_rxd<4>, sym_txd<4>

Signal detection

Transmit enable

mii_txen

Collision detect

mii_clsn

Error reporting

mii_err

Data control

mii_dv, mii_crs

Serial network port

MII management data clock

mii_mdc

MII management data
input/output

mii_mdio

Transmit and receive data

srl_txd, srl_rxd

Transmit control

srl_txen, srl_tclk

Receive control

srl_rxen, srl_rclk

Collision detect

srl_clsn
(continued on next page)

Preliminary—Subject to Change—November 1996

Table 9 (Cont.) Signal Functions
Interface

Function

Signal

Miscellaneous

LED indicators

rcv_match, sym_link

General-purpose pins

gep<7:0>

MII/SYM and serial port
select

mii/srl

Test access port

JTAG test operations

tck, tdi, tdo, tms

Serial ROM port

Serial ROM

sr_ck, sr_cs, sr_di, sr_do

Boot ROM

ROM interface

br_a<1:0>, br_ad<7:0>, br_ce_l

Power

3.3-V and 5.0-V supply
input

vdd, vdd_clamp

Ground

vss

22 Preliminary—Subject to Change—November 1996

3 Electrical and Environmental Specifications
This section contains the electrical and environmental specifications for the
21140A.
Caution
Stresses greater than the maximum or less than the minimum ratings
can cause permanent damage to the 21140A. Exposure to the maximum
or minimum ratings for extended periods of time lessen the reliability
of the 21140A.

3.1 Voltage Limit Ratings
Table 10 lists the voltage limit ratings.
Table 10 Voltage Limit Ratings
Parameter

Minimum

Maximum

Power supply voltage

+3.0 V

+3.6 V

vdd_clamp (3.3 V)1

+3.0 V

+3.6 V

vdd_clamp (5.0 V)

+4.75 V

+5.25 V

ESD protection voltage

—

2000 V

1 In the 3.3-V signaling environment, vdd_clamp must not be more than +0.3 V above vdd.

3.2 Temperature Limit Ratings
Table 11 lists the temperature limit ratings.
Table 11 Temperature Limit Ratings
Parameter

Minimum

Maximum

Storage temperature

–55°C

+125°C

Operating temperature

0°C

70°C

Preliminary—Subject to Change—November 1996

3.3 Supply Current and Power Dissipation
The values in Table 12 are estimates based on a PCI clock frequency of 33 MHz
and a network data rate of 10 Mb/s for SRL and 10/100 Mb/s for MII.
Table 12 Supply Current and Power Dissipation
Typical1
Symbol

Idd (mA)

Power (mW)

Maximum2
Idd (mA)

Power (mW)

Normal power mode

125

413

180

648

Snooze power mode

248

150

540

Sleep power mode

198

125

450

1 Typical: Vdd = 3.3 V, Ta = 25°C
2 Maximum: Vdd = 3.6 V, Ta = 0°C

3.3.1 PCI I/O Voltage Specifications
The 21140A meets the I/O voltage specifications listed in Table 13 and
Table 14.
Table 13 I/O Voltage Specifications for 5.0-V Levels
Symbol

Parameter

Condition

Minimum

Maximum

Vih

Input high voltage

—

2.0 V

vdd_clamp + 0.5 V

Vil

0.8 V

Input low voltage

—

–0.5 V

Input leakage current

0.5 V < Vin < 2.7 V

—

670 µA

Voh

Output high voltage

Iout = –2 mA

2.4 V

—

Output low voltage

Iout = 3 mA, 6 mA

—

0.55 V

Pin capacitance

—

5 pF

8 pF

Vol 2
3

Cap

1 Input leakage currents include high-impedance output leakage for all bidirectional buffers with tristate

outputs.
2 Signals without pull-up resistors have a low output current of 3 mA. Signals requiring pull-up resistors

(including frame_l, trdy_l, irdy_l, devsel_l, stop_l, serr_l, and perr_l) have a low output current of 6 mA.
3 Parameter design guarantee.

24 Preliminary—Subject to Change—November 1996

Table 14 I/O Voltage Specifications for 3.3-V Levels
Symbol

Parameter

Condition

Minimum

Maximum

Vih

Input high
voltage

—

0.475 3 vdd_clamp

vdd_clamp + 0.5 V

Vil

Input low
voltage

—

–0.5 V

0.325 3 vdd_clamp

Ii 1

Input
leakage
current

0.0 V < Vin < vdd_clamp

—

610 µA

Voh

Output
high
voltage

Iout = –500 µA

0.9 3 vdd_clamp

—

Vol

Output low
voltage

Iout = 1500 µA

—

0.1 3 vdd_clamp

Cap2

Pin
capacitance

—

5 pF

8 pF

1 Input leakage currents include high-impedance output leakage for all bidirectional buffers with tristate

outputs.
2 Parameter design guarantee.

Preliminary—Subject to Change—November 1996

3.3.2 PCI Reset
PCI reset (pci_rst) is an asynchronous signal that must be active for at least
10 active PCI clock (pci_clk) cycles. Figure 3 shows the PCI reset timing
characteristics, and Table 15 lists the PCI reset signal limits.
Figure 3 PCI Reset Timing Diagram
pci_clk

pci_rst

10 pci_clk Cycles

Internal Reset

33 pci_clk Cycles
LJ-03902.AI

Table 15 PCI Reset Timing
Symbol

Parameter

Minimum

Maximum

Conditions

Trst

pci_rst pulse width

10 3 Tcycle

Not applicable

pci_clk
active

26 Preliminary—Subject to Change—November 1996

3.3.3 PCI Clock Specifications
The clock frequency range for the PCI is between 20 MHz and 33 MHz.4
Figure 4 shows the PCI clock specification timing characteristics and required
measurement points for both 5-V and 3.3-V signaling environments. Table 16
lists the frequency-derived clock specifications.
Figure 4 PCI Clock Specification Timing Diagram

Thigh

5.0-V Clock
2.0 V

Tlow
0.8 V

3.3-V Clock

0.5 * vdd_clamp
0.3 * vdd_clamp

Tcycle
LJ03910A.AI5

Table 16 PCI Clock Specifications
Symbol

Parameter

Minimum

Maximum

Tcycle

Cycle time

30 ns

50 ns

Thigh

pci_clk high time

11 ns

—

Tlow

pci_clk low time

11 ns

—

Tr/Tf1

pci_clk slew rate

1 V/ns

4 V/ns

1 Rise and fall times are specified in terms of the edge rate measured in V/ns. Parameter design guarantee.

The PCI clock frequency is from dc to 33 MHz; network operational with the PCI
clock from 20 MHz to 33 MHz.

Preliminary—Subject to Change—November 1996

3.3.4 Other PCI Signals
Figure 5 shows the timing diagram characteristics, and Table 17 lists the other
PCI signals. This timing is identical to the timing for the general-purpose
register signals.
Figure 5 Timing Diagram for Other PCI Signals

Vtest 1
Clk
Tval (max)

Tval (min)

Output

Ton

Toff

Input
Th
Tsu
1 Vtest is 1.5 V in 5.0-V signaling environment and is 0.4 * vdd_clamp
in 3.3-V signaling environment.

LJ04719A.AI5

Note
The value for Vtest in Figure 17 in a 5-V signaling environment is
1.5 V, and in a 3.3-V signaling environment is 0.4 3 vdd_clamp.

28 Preliminary—Subject to Change—November 1996

Table 17 Other PCI Signals
Symbol

Parameter

Minimum

Maximum

Tval

clk-to-signal valid
delay

2 ns

11 ns

Ton1

Float-to-active delay
from clk

2 ns

—

Toff1

Active-to-float delay
from clk

—

28 ns

Tsu

Input signal valid
setup time before clk

7 ns

—

Input signal hold time
from clk

0 ns

—

1 Parameter design guarantee.
2 Load for this measurement is as specified in revisions 2.0 and 2.1 of the PCI Local Bus
Specification.

Preliminary—Subject to Change—November 1996

3.4 Serial, MII/SYM, Boot ROM, Serial ROM, and General-Purpose Port
Interface Specifications
Table 18 lists the specifications for the serial, MII/SYM, boot ROM, serial
ROM, and general-purpose port interfaces.
Table 18 Serial, MII/SYM, Boot ROM, Serial ROM, and General-Purpose Port
Symbol

Definition

Condition

Minimum

Maximum

Units

Voh

Output high voltage

Ioh = –4 mA

2.4

—

Vol

Output low voltage

Iol = 4 mA

—

0.4

Vih

Input high voltage

—

2.0

—

Vil

Input low voltage

—

0.8

Iin

Input current

Vin = Vcc or Vss

–10.0

10.0

µA

Iip

Input leakage current on pin
with internal pull-up resistor
(sr_do )

0.0 <Vin<vdd

—

+20/–10001

Ioz 2

Maximum tristate output
leakage current

Vin = Vdd or Vss

–10.0

10.0

µA

1 For pin sr_do, which has an internal pull-up resistor, the maximum leakage current of 1 mA can occur when
Vin = 0 V.
2 For br_ce_l, the maximum value is 1000.0 µA.

3.5 Serial Network Port Timing
This section describes the serial network port timing limits.

30 Preliminary—Subject to Change—November 1996

3.5.1 Serial 10-Mb/s Timing—Transmit
Figure 6 shows the serial network port transmit timing characteristics, and
Table 19 lists the serial network port transmit timing limits.
Figure 6 Serial Network Port Timing Diagram—Transmit
Ttcf

Ttcr
Ttch

Ttcl
srl_tclk

Ttcc
Ttdp

Ttdh

srl_txd<3:0>
Tteh

Ttep

srl_txen

LJ-05016.AI4

Table 19 Serial Network Port Timing—Transmit
Symbol

Definition

Minimum

Maximum

Units

Ttcl

srl_tclk low time

Ttch

srl_tclk high time

Ttcr1

srl_tclk rise time

—

Ttcf1

srl_tclk fall time

—

Ttdp

srl_tclk fall time to srl_txd valid

—

Ttdh

srl_txd hold after srl_tclk fall time

—

Ttep

srl_tclk fall time to srl_txen valid

—

Tteh

srl_txen hold after srl_tclk fall time

—

1 Parameter design guarantee.

Preliminary—Subject to Change—November 1996

3.5.2 Serial 10-Mb/s Timing—Collision
Figure 7 shows the serial network port collision timing characteristics, and
Table 20 lists the serial network port collision timing limit.
Figure 7 Serial Network Port Timing Diagram—Collision

srl_clsn

Tclh
LJ-04721.AI5

Table 20 Serial Network Port Timing—Collision
Symbol
Tclh

Definition

Minimum

Maximum

Units

srl_clsn high time

—

1 Parameter design guarantee.

32 Preliminary—Subject to Change—November 1996

3.5.3 Serial 10 Mb/s Timing—Receive, Start of Packet
Figure 8 shows the serial network port timing characteristics in receive mode,
start of packet; and Table 21 lists the serial network port timing limits in
receive mode, start of packet.
Figure 8 Serial Network Port Timing Diagram—Receive, Start of Packet
Trcr
Trcl

Trcf
Trch

srl_rclk

Trds

Trcc

Trdh
srl_rxd

srl_rxen
LJ-04722.AI5

3.5.4 Serial 10-Mb/s Timing—Receive, End of Packet
Figure 9 shows the serial network port timing characteristics in receive mode,
end of packet; and Table 21 lists the serial network port timing limits in
receive mode, end of packet.

Preliminary—Subject to Change—November 1996

Figure 9 Serial Network Port Timing Diagram—Receive, End of Packet
srl_rclk

srl_rxd

BIT N_1

BIT N

Treh
srl_rxen
Trel
LJ-04723.AI5

Table 21 Serial Network Port Timing—Receive, Start, and End of Packet
Symbol

Definition

Minimum

Maximum

Units

Trcc

srl_rclk cycle time

118

Trcl

srl_rclk low time

Trch

srl_rclk high time

Trcr1

srl_rclk rise time

—

Trcf1

srl_rclk fall time

—

Trds

srl_rxd setup to srl_rclk fall time

—

Trdh

srl_rxd hold after srl_rclk fall time

—

Trel

srl_rxen low time

120

—

Treh

srl_rxen hold after srl_rclk rise time

100

1 Parameter design guarantee.

3.6 MII/SYM Port Timing
This section describes the MII/SYM port timing limits.

34 Preliminary—Subject to Change—November 1996

3.6.1 MII/SYM 10/100-Mb/s and 10-Mb/s Timing—Transmit
Figure 10 shows the MII/SYM port transmit timing characteristics, and
Table 22 lists the MII/SYM port transmit timing limits.
Figure 10 MII/SYM Port Timing Diagram—Transmit
Tcc
Tcr
Tch

Tcf
Tcl

mii/sym_tclk
Trv
mii/sym_txd<3:0>
Trh
mii/sym_txen
LJ-05017 .AI4

Table 22 MII/SYM Port Timing—Transmit
Symbol

Definition

Minimum

Typical

Maximum

Units

Tcc1 ; 2

mii/sym_tclk cycle time

—

40t

—

Tch2

mii/sym_tclk high time

14t

—

26t

Tcl2

mii/sym_tclk low time

14t

—

26t

Tcr

mii/sym_tclk rise time

—

Tcf

mii/sym_tclk fall time

—

Trv3

mii_tclk rise to
—
mii_txen valid time or
mii/sym_tclk rise to mii/sym_txd
valid time

—

Trh

mii_txen hold after mii_tclk
rise time

—

650 parts per million.

2 t = 1 for 100-Mb/s operation and t = 10 for 10-Mb/s operation.
3 Outputs transmit data (mii/sym_txd) and transmit enable (mii_txen) are driven internally from
the rising edge of mii/sym_tclk.

Preliminary—Subject to Change—November 1996

3.6.2 MII/SYM 10/100-Mb/s Timing—Receive
Figure 11 shows the MII/SYM port receive timing characteristics, and Table 23
lists the MII/SYM port receive timing limits.
Figure 11 MII/SYM Port Timing Diagram—Receive
Tcc
Tcr
Tch

Tcf
Tcl

mii/sym_rclk
Tts

Tth

mii/sym_rxd<3:0>

mii_dv
LJ-05018.AI4

36 Preliminary—Subject to Change—November 1996

Table 23 MII/SYM Port Timing—Receive
Symbol

Definition

Minimum

Typical

Maximum

Units

Tcc1 ; 2

mii/sym_rclk cycle time

—

40t

—

Tch2

mii/sym_rclk high time

14t

—

26t

Tcl2

mii/sym_rclk low time

14t

—

26t

Tcr

mii/sym_rclk rise time

—

Tcf

mii/sym_rclk fall time

—

Tts3

mii/sym_rxd setup (both
rise and fall transactions) to
mii/sym_rclk rise time or
mii_dv setup (both rise and fall
transactions) to mii_rclk rise
time

—

Tth4

mii/sym_rxd hold (both rise
and fall transactions) after
mii/sym_rclk rise time or
mii_dv hold (both rise and fall
transactions) after mii_rclk rise
time

—

650 parts per million.

2 t = 1 for 100-Mb/s operation and t = 10 for 10-Mb/s operation.
3 Inputs receive data (mii/sym_rxd) and data valid (mii_dv) are latched internally on the rising
edge of mii/sym_rclk.
4 Parameter design guarantee.

Preliminary—Subject to Change—November 1996

3.6.3 MII/SYM 10/100-Mb/s Timing—Signal Detect
Figure 12 shows the MII/SYM port signal detect timing characteristics, and
Table 24 lists the MII/SYM port signal detect timing limits.
Figure 12 MII/SYM Port Timing Diagram—Signal Detect
sym_rclk

Tts

Tth

sd
LJ-03905.AI

Table 24 MII/SYM Port Timing—Signal Detect
Symbol

Definition

Minimum

Maximum

Units

Tts

sd1 setup (both rise and fall transactions) to sym_rclk fall time

—

Tth2

sd1 hold (both rise and fall transactions)
after sym_rclk fall time

—

1 Input signal detect (sd) is latched internally on the falling edge of sym_rclk.
2 Parameter design guarantee.

38 Preliminary—Subject to Change—November 1996

3.6.4 MII/SYM 10/100-Mb/s Timing—Receive Error
Figure 13 shows the MII/SYM port receive error timing characteristics, and
Table 25 lists the MII/SYM port receive error timing limits.
Figure 13 MII/SYM Port Timing Diagram—Receive Error
mii_rclk

Tts

Tth

mii_err
LJ-03906.AI

Table 25 MII/SYM Port Timing—Receive Error
Symbol

Definition

Minimum

Maximum

Units

Tts

mii_err1 setup (both rise and fall
transactions) to mii_rclk rise time

—

Tth2

mii_err1 hold (both rise and fall
transactions) after mii_rclk rise time

—

1 Input receive error (mii_err) is latched internally on the rising edge of mii_rclk.
2 Parameter design guarantee.

Preliminary—Subject to Change—November 1996

3.6.5 MII/SYM 10/100-Mb/s Timing—Carrier Sense and Collision
Figure 14 shows the MII/SYM port carrier sense and collision timing
characteristics, and Table 26 lists the MII/SYM port carrier sense and collision
timing limits.
Figure 14 MII/SYM Port Timing Diagram—Carrier Sense and Collision

mii_clsn
mii_crs

Tclh
LJ-03929.AI

Table 26 MII/SYM Port Timing—Carrier Sense and Collision
Symbol

Definition

Minimum

Maximum

Units

Tclh

mii_crs, mii_clsn high time

—

40 Preliminary—Subject to Change—November 1996

3.7 Boot ROM Port Timing
This section describes the boot ROM port timing.
3.7.1 Boot ROM Read Timing
Figure 15 shows the boot ROM read timing characteristics, and Table 27 lists
the boot ROM read timing limits.
Figure 15 Boot ROM Read Timing Diagram

Tads

br_ad<7:0>

Tadh

Address = <7:2>
oe = 0, we = 1

Tads

Tadh

Tavqv

Data <7:0>
Valid

Address <15:8>

br_a<1>

br_a<0>

Address <1>

Address <17>

Address <16>

Address <0>

br_ce_l
Telqx

Toh
Telqv

Tehqz
Tavav

SCALE=89% LJ-0 5037.AI4

Preliminary—Subject to Change—November 1996

Table 27 Boot ROM Read Timing Specifications
Symbol

Parameter

Minimum

Maximum

Units

Tavav

Read cycle time

120

—

Telqv

br_ce_l to output delay

—

120

br_ce_l to output enable

—

Tehqz

br_ce_l rising edge to
output high impedance

—

Toh1

Output hold from
br_ce_l change

—

Tads

Address setup to latch
enable high

—

Tadh

Address hold from latch
enable high

—

Telqx

1 Parameter design guarantee.

42 Preliminary—Subject to Change—November 1996

3.7.2 Boot ROM Write Timing
Figure 16 shows the boot ROM write timing characteristics, and Table 28 lists
the boot ROM write timing limits.
Figure 16 Boot ROM Write Timing Diagram

Tads

br_ad<7:0>

Tadh

Address = <7:2>
oe = 1, we = 0

Tads

Tadh

Address <15:8>

br_a<1>

br_a<0>

Data <7:0>

Address <1>

Address <17>

Address <16>

Address <0>

br_ce_l
Teleh
Tdveh

Tehdx
Tehax

Taveh
Tavav
LJ-05038.AI4

Preliminary—Subject to Change—November 1996

Table 28 Boot ROM Write Timing Specifications
Symbol

Parameter

Minimum

Maximum

Units

Tavav

Write cycle time

120

—

br_ce_l pulse width

—

Taveh

Address setup to
br_ce_l rising edge

—

Tdveh1

Data setup to br_ce_l
rising edge

—

Tehdx1

Data hold from br_ce_l
rising edge

—

Tehax1

Address hold from
br_ce_l high

—

Tads

Address setup to latch
enable high

—

Tadh

Address hold from latch
enable high

—

Teleh

1 Parameter design guarantee.

44 Preliminary—Subject to Change—November 1996

3.8 Serial ROM Port Timing
Figure 17 shows the serial ROM port timing, and Table 29 lists the
characteristics. This timing is identical to the timing for the MII management
signals (mii_mdio and mii_mdc).
Figure 17 Serial ROM Port Timing Diagram

sr_cs, sr_ck
sr_di, sr_do
Tsr

Tsf

LJ-03909.AI

Table 29 Serial ROM Port Timing Characteristics
Symbol

Definition

Minimum

Maximum

Units

Tsr

Rise time

—

Fall time

—

Tsf

1 Parameter design guarantee.

Preliminary—Subject to Change—November 1996

3.9 External Register Timing
Figure 18 shows the external register read timing characteristics, and
Figure 19 shows its write timing characteristics. Table 30 lists the external
register timing specifications for both read and write operations.
Figure 18 External Register Read Timing Diagram

br_ad<7:0>

Data Valid

br_a<0>

br_ce_l
Tpd

Tehqz

LJ-05039.AI4

Figure 19 External Register Write Timing Diagram
Data <7:0>

br_ad<7:0>

br_a<0>

br_ce_l
Teleh
Ts

Th
LJ-05040.AI4

46 Preliminary—Subject to Change—November 1996

Table 30 External Register Timing Specifications
Symbol

Parameter

Minimum

Maximum

Units

Teleh

br_ce_l pulse width

120

—

br_ce_l low to br_ad<7:0> valid

—

br_ce_l high to br_ad<7:0> high
impedance

—

Read Timing
Tpd
1

Tehqz

Write Timing
Ts

Data setup time prior to br_ce_l

—

Data hold after br_ce_l high

—

1 Parameter design guarantee.

Preliminary—Subject to Change—November 1996

3.10 Joint Test Action Group—Test Access Port
This section provides the joint test action group (JTAG) test access port
specifications.
3.10.1 JTAG dc Specifications
Table 31 lists the dc specifications for the JTAG pins.
Table 31 JTAG dc Specifications
Symbol

Definition

Conditions

Minimum

Maximum

Units

Voh

Output high voltage

Ioh = –4 mA

2.4

—

Vol

Output low voltage

Iol = 4 mA

—

0.4

Vih

Input high voltage

—

2.0

—

Vil

Input low voltage

—

0.8

Iip

Input leakage current on pins
with internal pull-up resistors
(tdi, tms, and tck)

0.0 <Vin<vdd

—

+20/–10001

Ioz

Tristate output leakage current
(tdo)

0.0 <Vout<vdd

—

620

1 For tdi, tms, and tck pins that have internal pull-up resistors, the maximum leakage current of 1 mA can

occur when Vin = 0 V.

3.10.2 JTAG Boundary-Scan Timing
Figure 20 shows the JTAG boundary-scan timing, and Table 32 lists the
interface signal timing relationships.

48 Preliminary—Subject to Change—November 1996

Figure 20 JTAG Boundary-Scan Timing Diagram

Tck_f

Tck_cycle

tck

Tck_r

Tms_s

Tms_h

Tdi_s

Tdi_h

tms

tdi
Tdo_d

tdo
LJ-03908.AI

Table 32 JTAG Interface Signal Timing Relationships
Symbol

Parameter

Minimum

Maximum

Units

Tms_s

tms setup time

—

Tms_h

tms hold time

—

Tdi_s

tdi setup time

—

Tdi_h

tdi hold time

—

Tdo_d

tdo delay time

—

Tck_r1

tck rise time

—

tck fall time

—

Tck_cycle

tck cycle time

—

Tck_f

1 Parameter design guarantee.

Preliminary—Subject to Change—November 1996

4 Mechanical Specifications
The 21140A is contained in an industry-standard 144-pin PQFP. Table 33 lists
the mechanical specifications, and Figure 21 shows the mechanical layout of
the 21140A.
Table 33 144-Pin PQFP Package Dimensions
Symbol

Dimension

Limit

Value (mm)

Package overall height

Maximum

4.10

Package standoff height

Minimum

0.25

Package thickness

Minimum
Maximum

3.17
3.67

Lead width

Minimum
Maximum

0.22
0.38

Lead thickness

Minimum
Maximum

0.12
0.23

ccc

Coplanarity

0.1
1

31.20

Package overall width

BSC

Package width

BSC

ddd

Lead skew

Package overall length

BSC

31.20

Package length

BSC

28.00

Lead pitch

BSC

0.65

Foot length

Minimum
Maximum

0.65
1.03

Lead length

Reference2

1.60

Ankle radius

Minimum
Maximum

0.13
0.3

28.00
0.13

1 ANSI Y14.5M-1982 American National Standard Dimensioning and Tolerancing, Section 1.3.2,
defines basic (BSC) dimension as: A numerical value use to describe the theoretically exact size,
profile, orientation, or location of a feature or datum target. It is the basis from which permissible
variations are established by tolerances on other dimensions, in notes, or in feature control frames.
2 The value for this measurement is for reference only.

50 Preliminary—Subject to Change—November 1996

Figure 21 144-Pin PQFP Package
-AD
D1

Pin # Direction

Pin 1

144-Pin PQFP

E1 E

-B-

See Detail "A"

// 0.13 C
- H - Datum Plane
- C - Seating Plane
ddd M C A S B S
ccc C
Detail "A"

(A) A2
R

Note: All dimensions are in millimeters.
- Basic Dimension

(

L
(LL)

) - Reference Dimension

0 -7 c

LJ04510B .AI4

Preliminary—Subject to Change—November 1996

A
Support, Products, and Documentation
If you need technical support, a Digital Semiconductor Product Catalog, or
help deciding which documentation best meets your needs, visit the Digital
Semiconductor’s World Wide Web Internet site:
http://www.digital.com/info/semiconductor
or call the Digital Semiconductor Information Line:
United States and Canada
Outside North America

1–800–332–2717
+1–510–490–4753

A.1 Ordering Digital Semiconductor Products
To order the Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller
and Evaluation Boards, contact your local distributor. To obtain a Digital
Semiconductor Product Catalog, contact the Digital Semiconductor Information
Line.
The following tables lists some of the semiconductor products available from
Digital:
Product

Order Number

Digital Semiconductor 21041 Evaluation Board Kit

21A41–01

Digital Semiconductor 21041 PCI Ethernet
LAN Controller (PQFP package)

21041–PA

Digital Semiconductor 21041 PCI Ethernet
LAN Controller (TQFP package)

21041–TA

Digital Semiconductor 21140A 10/100BASE–TX
Evaluation Board Kit

21A40–TX

Digital Semiconductor 21140A PCI Fast Ethernet
LAN Controller

21140–AE

Preliminary—Subject to Change—November 1996

A–1

Product

Order Number

Digital Semiconductor 21143 PCI 10/100BASE–TX
Evaluation Board Kit

21A43–01

Digital Semiconductor 21143 PCI/CardBus Ethernet
LAN Controller (PQFP package)

21143–PA

Digital Semiconductor 21143 PCI/CardBus Ethernet
LAN Controller (TQFP package)

21143–TA

A.2 Ordering Digital Semiconductor Documentation
The following table lists some of the available Digital Semiconductor
documentation. For a complete list, contact the Digital Semiconductor
Information Line or visit Digital Semiconductor’s World Wide Web Internet
site.
To determine which documents apply to a particular device part number, visit
the Digital Semiconductor Documentation Library on Digital Semiconductor’s
World Wide Web Internet site at:
http://ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
Title

Order Number

Digital Semiconductor 21041 PCI Ethernet LAN
Controller Data Sheet

EC–QAWWB–TE

Digital Semiconductor 21041 PCI Ethernet LAN
Controller Hardware Reference Manual

EC–QAWXB–TE

Digital Semiconductor 21041 PCI Ethernet LAN
Controller Product Brief

EC–QAWVB–TE

Digital Semiconductor 21140A PCI Fast Ethernet LAN
Controller Hardware Reference Manual

EC–QN7NE–TE

Digital Semiconductor 21140A PCI Fast Ethernet LAN
Controller Product Brief

EC–QN7MB–TE

Digital Semiconductor 21143 PCI/CardBus 10/100-Mb/s
Ethernet LAN Controller Data Sheet

EC–QWC3A–TE

Digital Semiconductor 21143 PCI/CardBus 10/100-Mb/s
Ethernet LAN Controller Hardware Reference Manual

EC–QWC4A–TE

Digital Semiconductor 21143 PCI/CardBus 10/100-Mb/s
Ethernet LAN Controller Product Brief

EC–QW2CA–TE

Digital Semiconductor 21143 Connection to the Network
Using Physical Layer Devices: An Application Note

EC–QXY7A–TE

A–2 Preliminary—Subject to Change—November 1996

A.3 Ordering Third-Party Documentation
You can order the following third-party documentation directly from the
vendor:
Title

Vendor

PCI Local Bus Specification Revision 2.1
PCI BIOS Specification Revision 2.1

PCI Special Interest Group
1–800–433–5177 (U.S.)
1–503–797–4207 (International)
1–503–234–6762 (FAX)

Preliminary—Subject to Change—November 1996

A–3