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EC-QC0CA-U1

2000

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Document:	21140 Hardware Reference Manual Update
Order Number:	EC-QC0CA-U1
Revision:
Pages:	12
Original Filename:	http://bitsavers.org/pdf/dec/semiconductor/ethernet/EC-QC0CA-U1_21140_Hardware_Reference_Manual_Update.pdf

OCR Text

D ig ita l S e m ic o n d u c to r

E C–QC0CA–U1

D ECc h ip 21140 P CI F a s t Eth e rn e t LAN
Co n tro lle r Ha rd w a re Re fe re n c e Ma n u a l U p d a te

Th is docu m en t pr ovides u pda t ed in for m a t ion for t h e DE Cch ip 21140 PCI Fast
E th ern et L AN Con troller H ard w are R eferen ce M an u al, E C–QC0CA–TE .

Section 3.2.2.5 Status Register (CSR5)
On pa ge 3-26, in Ta ble 3-35, CS R5 Ac c e s s Ru le s , t h e va lu e a ft er r eset sh ou ld
be ch a n ged a s follows:
Category

Description

Va lu e a ft er r eset

F C000000H

3.2.2.6 Operation Mode Register (CSR6)
On pa ge 3-27, F igu r e 3-15, CS R6 Op e ra tin g Mo d e Re g is te r, sh ou ld sh ow
t h a t bit 25 m u st be on e. See t h e followin g ﬁgu r e for t h e cor r ect in for m a t ion :

3
1

2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

0 0 0 1

MBZ - Must Be Zero
MB1 - Must Be One
SCR - Scrambler Mode
PCS - PCS Function
TTM - Transmit Threshold Mode
SF - Store and Forward
MBZ - Must Be Zero
HBD - Heartbeat Disable
PS - Port Select
CA - Capture Effect Enable
MBZ - Must Be Zero
TR - Threshold Control Bits
ST - Start/Stop Transmission Command
FC - Force Collision Mode
OM - Operating Mode
FD - Full-Duplex Mode
MBZ - Must Be Zero
PM - Pass All Multicast
PR - Promiscuous Mode
SB - Start/Stop Backoff Counter
IF - Inverse Filtering
PB - Pass Bad Frames
HO - Hash-Only Filtering Mode
SR - Start/Stop Receive
HP - Hash/Perfect Receive Filtering Mode
LJ-04294.AI

On pa ge 3-28, in Ta ble 3-36, CS R6 Op e ra tin g Mo d e Re g is te r D e s c rip tio n ,
u pda t e bit s 28 t h r ou gh 25 a s follows:
Field

Description

28:26

MB Z — Mu s t B e Ze ro
Th ese bit s a r e n ot u sed by t h e 21140 a n d sh ou ld a lwa ys be pr ogr a m m ed
t o zer o.

MB O — Mu s t B e On e
Th is bit s h o u ld a lw a y s be p ro g ra m m e d to o n e .

On pa ge 3-31, in Ta ble 3-36, CS R6 Op e ra tin g Mo d e Re g is te r D e s c rip tio n ,
a dd t h e followin g n ot e t o t h e descr ipt ion for bit 0:
Field

Description

HP — Ha s h /P e rfe c t Re c e iv e F ilte rin g Mo d e (Re a d On ly )
Wh en r eset , t h e 21140 does a per fect a ddr ess ﬁlt er of in com in g fr a m es
a ccor din g t o t h e a ddr esses speciﬁed in t h e set u p fr a m e (Ta ble 4-8).
Wh en set , t h e 21140 does im per fect a ddr ess ﬁlt er in g of m u lt ica st
in com in g fr a m es a ccor din g t o t h e h a sh t a ble speciﬁed in t h e set u p
fr a m e. If CSR6<2> is set , t h en ph ysica l a ddr esses a r e im per fect a ddr ess
ﬁlt er ed t oo. If CSR6<2> is r eset , ph ysica l a ddr esses a r e per fect a ddr ess
ﬁlt er ed, a ccor din g t o a sin gle ph ysica l a ddr ess, a s speciﬁed in t h e set u p
fr a m e.

Note
A u n iqu e c o n d itio n o c c u rs in h a s h /p e rfe c t re c e iv e ﬁ lte rin g m o d e
w h e n a p h y s ic a l a d d re s s is p e rfe c t ﬁ lte re d by c o m p a rin g it to
a s in g le a d d re s s . In th is c a s e , w h ile in p e rfe c t ﬁ lte rin g m o d e ,
th e d riv e r s e n d s a s e tu p fra m e c o n ta in in g th e s in g le p h y s ic a l
a d d re s s . Th e d riv e r th e n s e ts th e p a s s a ll m u ltic a s t m o d e .

On pa ge 3-32, followin g Ta ble 3-37, Tra n s m it Th re s h o ld , a dd t h e followin g
n ot e:
Threshold (Bytes)
CSR6<21>

CSR6<15:14>

CSR6<22> = 0

CSR6<22> = 1

128

256

512

128

1024

160

St or e a n d for wa r d

Note
Th e CS R6<22> bit is m e a n in g fu l o n ly if th e CS R6<18> bit is s e t.
Oth e rw is e , th e th re s h o ld v a lu e re m a in s a s lis te d in th e c o lu m n
w ith h e a d in g CS R6<22> = 1.

On pa ge 3-33, in Ta ble 3-39, Lo o p ba c k Op e ra tio n Mo d e , u pda t e foot n ot e 1
a s follows:
CSR6<11:10>
01

Operation Mode
In t er n a l loopba ck

1 In t er n a l loopba ck is per for m ed on t h e ser ia l a n d MII/SYM por t s. If en a bled by CSR6, it a ls o
t est s t h e P CS fu n ct ion s (CSR6<23>) a n d t h e scr a m bler fu n ct ion (CSR6<24>). N o te th a t w h e n
in te rn a l lo o p ba c k is p e rfo rm e d o n th e S YM p o rt, s y m bo ls a p p e a r o n th e n e tw o rk . Wh e n
in te rn a l lo o p ba c k is p e rfo rm e d o n th e MII p o rt, th e m ii_tx e n s ig n a l is d is a ble d .

Section 3.2.2.7 Interrupt Enable Register (CSR7)
On pa ge 3-38, in Ta ble 3-43, CS R7 Ac c e s s Ru le s , t h e va lu e a ft er r eset sh ou ld
be ch a n ged a s follows:
Category

Description

Va lu e a ft er r eset

F F F E0000H

Section 3.2.2.9 Serial Address ROM and MII Management Register
(CSR9)
On pa ge 3-42, in Ta ble 3-47, CS R9 Ac c e s s Ru le s , t h e va lu e a ft er r eset sh ou ld
be ch a n ged a s follows:
Category

Description

Va lu e a ft er r eset

F F F 097F F H

Section 4.2.2.2 Transmit Descriptor 1 (TDES1)
On pa ge 4-16, in Ta ble 4-7, TD ES 1 Tra n s m it D e s c rip to r 1 D e s c rip tio n , a dd
t h e followin g in for m a t ion t o t h e descr ipt ion for bit 31:
Field

Description

IC — In te rru p t o n Co m p le tio n
Wh en set , t h e 21140 set s t r a n sm it in t er r u pt (CSR5<0>) a ft er t h e
pr esen t fr a m e h a s been t r a n sm it t ed. It is va lid on ly wh en la st segm en t
(TDE S1<30>) is set o r w h e n it is a s e tu p p a c k e t.

Section 5.2 Bus Commands
On pa ge 5-2, in Ta ble 5-1, B u s Co m m a n d s , t h e la st fou r com m a n ds sh ou ld be
ch a n ged a s follows:
c_be_l<3:0>

Command

Type of Support

1100

Me m o ry re a d m u ltip le

S u p p o rte d a s ta rg e t

1101

D u a l a d d re s s c y c le

Not su ppor t ed

1110

Me m o ry re a d lin e

S u p p o rte d a s ta rg e t

1111

Me m o ry w rite a n d
in v a lid a te

S u p p o rte d a s ta rg e t

Section 6.4 Loopback Operations
On pa ge 6-19, in Sect ion 6.4, Lo o p ba c k Op e ra tio n s , ch a n ge t h e la st sen t en ce,
wh ich r ea ds ‘‘Th e loopba ck da t a r a t e is 10 Mb/s.’’, t o t h e followin g: Th e
d e fa u lt v a lu e o f th e lo o p ba c k d a ta ra te is 10 Mb/s . Wh e n th e MII/S YM
p o rt is e n a ble d , th e lo o p ba c k d a ta ra te is 100 Mb/s .

Section 6.4.2 External Loopback Mode
On pa ge 6-19, in Sect ion 6.4.2, Ex te rn a l Lo o p ba c k Mo d e , delet e t h e la st
sen t en ce wh ich r ea ds a s follows: ‘‘Th e 21140 sh ou ld be in fu ll-du plex m ode
(CSR6<9>).’’

Section 7.2.1 Read Operation
On pa ge 7-3, in Sect ion 7.2.1, Re a d Op e ra tio n , r epla ce t h e ﬁgu r e sh own in
F igu r e 7-2 Rea d Cycle (P a ge 1 of 2) wit h t h e followin g ﬁgu r e:

Write CSR9<2:0> = 000#2

30 ns

Write CSR9<2:0> = 001#2

50 ns

Write CSR9<2:0> = 011#2

250 ns

Write CSR9<2:0> = 001#2

100 ns

Write CSR9<2:0> = 101#2

150 ns

Write CSR9<2:0> = 111#2

250 ns

Write CSR9<2:0> = 101#2

250 ns

Write CSR9<2:0> = 111#2

250 ns

Write CSR9<2:0> = 101#2

100 ns

10.

Write CSR9<2:0> = 001#2

150 ns

11.

Write CSR9<2:0> = 011#2

250 ns

12.

Write CSR9<2:0> = 001#2

100 ns

13.

Write CSR9<2:0> = X01#2

150 ns

14.

Write CSR9<2:0> = X11#2

250 ns

15.

Write CSR9<2:0> = X01#2

100 ns

Command

X = Current Address Bit
Address

No
X = A0?
Yes
Wait 150 ns

A
LJ-04049.AI

On pa ge 7-4, in Sect ion 7.2.1, Re a d Op e ra tio n , r epla ce t h e ﬁgu r e sh own in
F igu r e 7-3 Rea d Cycle (P a ge 2 of 2) wit h t h e followin g ﬁgu r e:
A

16.

Write CSR9<2:0> = 011#2

100 ns

17.

Read CSR9<3> = DX

150 ns

18.

Write CSR9<2:0> = 001#2

250 ns

DX = Current Data Bit
Data

No
DX = D0 ?
Yes
19.

Write CSR9<2:0> = 000#2

Wait 100 ns Until Ready

End
LJ-04050.AI

Section 7.2.2 Write Operation
On pa ge 7-6, in Sect ion 7.2.2, Write Op e ra tio n , r epla ce t h e ﬁgu r e sh own in
F igu r e 7-5 Wr it e Cycle (P a ge 1 of 2) wit h t h e followin g ﬁgu r e:

Write CSR9<2:0> = 000#2

30 ns

Write CSR9<2:0> = 001#2

50 ns

Write CSR9<2:0> = 011#2

250 ns

Write CSR9<2:0> = 001#2

100 ns

Write CSR9<2:0> = 101#2

150 ns

Write CSR9<2:0> = 111#2

250 ns

Write CSR9<2:0> = 101#2

100 ns

Write CSR9<2:0> = 001#2

150 ns

Write CSR9<2:0> = 011#2

250 ns

10.

Write CSR9<2:0> = 001#2

100 ns

11.

Write CSR9<2:0> = 101#2

150 ns

12.

Write CSR9<2:0> = 111#2

250 ns

13.

Write CSR9<2:0> = 101#2

100 ns

14.

Write CSR9<2:0> = X01#2

150 ns

15.

Write CSR9<2:0> = X11#2

250 ns

16.

Write CSR9<2:0> = X01#2

100 ns

Command

X = Current Address Bit
Address

No
X = A0?
Yes
A
LJ-04052.AI

On pa ge 7-7, in Sect ion 7.2.2, Write Op e ra tio n , r epla ce t h e ﬁgu r e sh own in
F igu r e 7-6 Wr it e Cycle (P a ge 2 of 2) wit h t h e followin g ﬁgu r e:
A

17.

Write CSR9<2:0> = DX01#2 150 ns

18.

Write CSR9<2:0> = DX11#2 250 ns

19.

Write CSR9<2:0> = DX01#2 100 ns

DX = Current Data Bit
Data

No
DX = D0?
Yes
20.

Write CSR9<2:0> = 000#2

250 ns

21.

Write CSR9<2:0> = 001#2

250 ns

22.

Read CSR9<3>

Wait 1 ms
CSR9<3>
= 1?

Busy

Yes
23.

Write CSR9<2:0> = 000#2

End
LJ-04053.AI

Appendix A.2.3 Boundary-Scan Register
On pa ge A-3, in Appen dix A.2.3, B o u n d a ry -S c a n Re g is te r, ch a n ge t h e
bou n da r y-sca n r egist er list in g t o r ea d a s follows (ch a n ge clk t o pci_clk, do$pd
t o sr _do, di$br t o sr _di, sk_br t o sr _ck, a n d cs_$br t o sr _cs):
-> tdi
-> req_l
-> idsel
-> irdy_oe
-> devsel_l
-> serr_l
-> c_be_l<0>
-> sr_cs

-> int_l
-> ad_oe
-> ad<23:16>
-> irdy_l
-> stop_oe
-> par_oe
-> ad<7:0>
-> tdo

-> rst_l
-> ad<31:24>
-> c_be_l<2>
-> trdy_oe
-> stop_l
-> par
-> sr_do

-> pci_clk
-> cbe_oe
-> frame_oe
-> trdy_l
-> perr_oe
-> c_be_l<1>
-> sr_di

-> gnt_l
-> c_be_l<3>
-> frame_l
-> devsel_oe
-> perr_l
-> ad<15:8>
-> sr_ck

© Digit a l E qu ipm en t Cor por a t ion 1995. All r igh t s r eser ved. P r in t ed in U.S.A.
DE Cch ip, Digit a l, a n d t h e DIGITAL logo a r e t r a dem a r ks of Digit a l E qu ipm en t
Cor por a t ion .
Digit a l Sem icon du ct or is a Digit a l E qu ipm en t Cor por a t ion bu sin ess.