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XX-0D36F-E0

June 1988

136 pages

Original

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Document:	DC-541 SGEC 198806
Order Number:	XX-0D36F-E0
Revision:
Pages:	136
Original Filename:	http://bitsavers.org/pdf/dec/semiconductor/ethernet/DC-541_SGEC_198806.pdf

OCR Text

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SGEC specification V3.0
Part Number DC-541
For Internal Use Only
This document contains the specification for the Second Generation
Ethernet Chip pass1 part. It has been reviewed by the development team
and is now submitted for internal customers review.

Written by:
Name

Enet addrau

Joel Chocron

JEREMY::JOEL

Elliot Gerberg

NAC::GERBERG

Philippe Klein

JEREMY::PHILIPPE

Ady Litshes

JEREMY::AOY

John Redford

AD::REOFORO

David Shemla

JEREMY::DAVID

Revision/Update Information:

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This document supersedes the SGEC
specification V2.0

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Change history:
Revision

Date

Description

3.0

June 6, 1988

Pass1 SGEC version, including:

•

SIA dropped .

•

CP-BUS parity support added .

•

Incorporated various inputs received
at reviews.

2.0

July 7, 1987

•
•
•
•

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,.,

1.0

Oct 17, 1986

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Major update including:

O.x

Jan 30, 1986

DEQNA mode dropped .
SGEC host port interface redefined .
FIFOs size increased to 120 bytes .
Serial parameters programmability
dropped.

•

Direct µVAX bus support dropped .

•

Incorporated various inputs received
at reviews.

Major update including:

•

DEQNA mode added .

•

SGEC "native" mode defined .

•
•

Removed references to LANCE .
Incorporated various inputs received
at first review.

Initial version

June 1988

This document and the specifications contained herein are confidential and
proprietary. They are the property of Digital Equipment Corporation and shall
not be reproduced or copied or used in whole or In part as the basis for the
manufacture or sale of items without written permission. This is an unpublished
work protected under the federal copyright laws.

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Copyright ©1986,1987,1988 by Digital Equipment Corporation
All Rights Reserved.
Printed In U.S.A.

. This document was prepared using VAX DOCUMENT, Version 1.0

-' ~--------------------------------------------------------------------~

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Contents
PREFACE

CHAPTER 1 ETHERNET AND IEEE 802.3 OVERVIEW

xiii

1-1

1.1

LOCAL AREA NETWORKS

1-1

1.2

ETHERNET IN DIGITAL

1-1

1.3

THE IEEE 802 FAMILY OF LAN STANDARDS

1-2

1.4

ETHERNET AND IEEE 802.3 ELEMENTS

1-3

1.5

ETHERNET AND IEEE 802 DIFFERENCES AND COEXISTENCE

1-5

ASSUMPTIONS AND GOALS

2-1

2.1

SGEC BASIC ASSUMPTIONS

2-1

2.2

SGEC PROJECT GOALS

2-1

2.3

BASIC DEFINITION GUIDELINES
2.3.1
System Interface
Serial Controller Features
2.3.2

2-2
2-2
2-2

PINOUT

3-1

3.1

PINOUT TABLES

3-2

3.2

PINOUT SIGNAL DESCRIPTIONS

3-3

CHAPTER2

CHAPTER 3

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iii

Contents

HOST BUS PROTOCOLS

4-1

4.1

BUS OPERATING MODES
4.1.1
Synchronous mode
4.1.2
Asynchronous mode

4-1
4-1
4-1

4.2

BUS SLAVE (CSRS ACCESSES) OPERATtON
4.2.1
SGEC addressing
4.2.2
Bus holding policy
4.2.3
Host read cycle
4.2.4
Host write cycle
4.2.5
Interrupt acknowledge cycle

4-2
4-2
4-2
4-3
4-3
4-4

4.3

BUS MASTER (OMA) OPERATION
4.3.1
Bus arbitration and holding policy
4.3.2
Single read cycle
Single write cycle
4.3.3
4.3.4
Octaword read cycle
Octaword write cycle
4.3.5

4-4
4-4

PROGRAMMING

5-1

5.1

PROGRAMMING OVERVIEW

5-1

5.2

COMMAND AND STATUS REGISTERS
5.2.1
Host access to CSRs
5.2.1.1
Physical CSRs • 5-2
5.2.1.2
Virtual CSRs • 5-2
5.2.1.2.1 CSR write • 5-2
5.2.1.2.2 CSR read • 5-3
Vector Address, IPL, Sync/Asynch (CSRO)
5.2.2
5.2.3
Polling Demand (CSR1)
5.2.4
Reserved register (CSR2)
5.2.5
Descriptor List addresses (CSR3, CSR4)
5.2.6
Status Register (CSR5)
5.2.7
Command and Mode Register (CSRG)
5.2.8
System Base Register (CSR7)
5.2.9
CSR8
5.2.10 Watchdog Timers (CSR9)
5.2.11 CSR10
5.2.12 Revision Number and Missed Frame Count (CSR11)

5-1
5-2

CHAPTER 4

CHAPTERS

4-5
4-6
4-6
4-7

5-3
5-4
5-4
5-5
5-5
5-9

5-13
5-13

5-13
5-14
5-14

Contents

5.2.13
5.3

5.4

CHAPTER 6
6.1
~

6.2

Diagnostic Registers (CSR12, 13, 14, 15)

5-15

DESCRIPTORS AND BUFFERS FORMAT
Receive descriptors
5.3.1
5.3.1.1
RDESO word • 5-16
5.3.1.2
RDES1 word • 5-17
5.3.1.3
RDES2 word • 5-18
5.3.1.4
RDES3 word • 5-18
5.3.2
Transmit descriptors
5.3.2.1
TDESO word • 5-19
5.3.2.2
TDES1 word • 5-20
5.3.2.3
TDES2 word • 5-21
5.3.2.4
TDES3 word • 5-22
5.3.3
Setup frame
5.3.3.1
First setup frame • 5-23
5.3.3.2
Subsequent setup frame • 5-23
5.3.3.3
Changing filtering mode • 5-23
5.3.3.4
Setup frame descriptor • 5-23
5.3.3.5
Perfect Filtering setup frame buffer • 5-24
5.3.3.6
Imperfect Filtering setup frame buffer • 5-26

5-15
5-16

SGEC OPERATION
5.4.1
Hardware and Software Reset
5.4.2
Interrupts
5.4.3
Startup procedure
5.4.4
Reception process
5.4.5
Transmission process
5.4.6
Loopback operations
5.4.7
DNA CSMA/CD counters and events support

5-29
5-29
5-30
5-31
5-31
5-33
5-35
5-36

SERIAL INTERFACE

6-1

BASIC SERIAL OPERATION
6.1.1
Frame Format
6.1.1.1
Ethernet Format Types • 6-1
6.1.1.2
Detailed frame format • 6-2
6.1.2
Ethernet Reception Addressing
6.1.3
Collision Detection and Implementation
6.1.4
Clock Generator
6.1.5
Watchdog timers
6.1.6
Transmit Mode
6.1.7
Receive Mode

6-1
6-1

DETAILED TRANSMISSION OPERATION

6-5

5-18

5-22

6-3
6-4
6-4
6-4
6-4
6-4

Contents

6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.3

CHAPTER 7
7.1

7.2

Transmission Initiation
Frame Encapsulation
Initial Deferral
Collision
Watchdog Timer
Terminating Transmission
Transmit parameters values

6-5
6-5
6-5
6-6
6-6

6-6
6-7

DETAILED RECEIVING OPERATION
Initiating Reception
6.3.1
6.3.2
Preamble Processing
6.3.3
Address Matching
6.3.4
Frame decapsulation
6.3.5
Terminating Reception
6.3.6
Frame Reception Conditions
6.3.7
Frame reception programmable quantities

6-10

DIAGNOSTICS ANO TESTING

7-1

SGEC OPERATIONAL MOOE DIAGNOSTICS FEATURES.
7. 1. 1
SGEC internal Self test
7.1.2
Time Domain Reflectometer
7 .1.3
SGEC Loopback modes

7-1
7-1
7-1

6-7
6-7
6-8

6-8
6-8
6-8

6-9

7-1

SGEC DIAGNOSTIC MODE FEATURES.
7-2
7.2.1
Diagnostic CSR's.
7-2
7.2.1.1
Reserved register (CSR12) • 7-2
7.2.1.2
Breakpoint Address Register (CSR13) • 7-2
7.2.1.3
Reserved Register (CSR14) • 7-3
7.2.1.4
Diagnostic mode and status Register (CSR15) • 7-3
7.2.2
Serial access to the SGEC via test pins.
7-3
7.2.2.1
Serial Address Register • 7-5
7.2.2.2
Serial Control Register • 7-5
7.2.2.3
Serial Data Register • 7-5
7.2.3
Performing code Patches
7-6
7.2.4
Monitoring of the internal Busses
7-6
7 .2.4. 1
Monitoring of the internal Processor address bus • 7-6
7.2.4.2
Monitoring of the internal Processor Data bus • 7-7
7.2.5
Diagnostics frame
7-7
7.2.5.1
Address Dump Diagnostics frame • 7-9
7.2.5.2
Address load Diagnostics frame • 7-9

Contents

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SYSTEM CONFIGURATIONS

8-1

8.1

CVAX HOST BUS SYSTEM
CVAX host bus with SGEC in synchronous mode
8.1.1
CVAX host bus with SGEC In asynchronous mode
8.1.2

8-1
8-1
8-2

8.2

GHIDRA BUS WITH SGEC IN SYNCHRONOUS MODE

8-3

8.3

OTHER HOST BUS CONFIGURATION

8-4

8.4

SGEC SERIAL LINE CONFIGURATIONS
SGEC configuration on 10BASE5 (fatwira} Ethernet
8.4.1
line.
SGEC configuration on 10BASE2 DTE line.
8.4.2
SGEC configuration on twisted pair Ethernet line.
8.4.3

8-5
8-5
8-6
8-6

AC/DC CHARACTERISTICS

9-1

9.1

ABSOLUTE MAXIMUM RATINGS

9-1

9.2

ELECTRICAL CHARACTERISTICS

9-1

9.3

SGEC SYSTEM BASIC TIMING
9.3.1
CVAX Clock In CLKA,CLKB
9.3.2
SGEC RESET pin timing

9-5
9-5
9-6

9.4

SGEC SLAVE MODE TIMING
9.4.1
CPU Raad Cycle Timing
Interrupt acknowledge cycle Timing
9.4.2
9.4.3
CPU Write Cycle
9.4.4
NSGEC timing

9-7
9-7
9-9
9-11
9-13

9.5

SGEC MASTER MODE TIMING
9.5.1
DMA Grant Cycle
9.5.2
Single Transfer SGEC Read Cycle
Octaword Transfer SGEC Read Cycle
9.5.3
9.5.4
Single Transfer SGEC Write Cycle
9.5.5
Octaword Transfer SGEC Write Cycle

9-14
9-14
9-17
9-19
9-22
9-24

CHAPTERS

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CHAPTER9

vii

Contents

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9.6

APPENDIX A

SGEC SERIAL.INTERFACE TIMING
Receive clock and Transmit clock timing
9.6.1
9.6.2
SGEC RESET pin timing
9.6.3
Serial link timing
SGEC timing for 100ns and 60ns clock cycles
9.6.4

9-27
9-27
9-28
9-29
9-31

REFERENCES

A-1

APPENDIX B SGEC INTERNAL BLOCK DIAGRAM

B-1

APPENDIX C OPEN ISSUES

C-1

EXAMPLES
5-1
5-2
5-3

Perfect filtering buffer
Imperfect filtering buffer
Imperfect filtering Setup frame buffer creation C program

5-25
5-27
5-28

Several of the Digital developed transport mechanisms
802 family of standards
Ethernet Network Elements
DNA CSMA/CD frame formats
SGEC plnout
CSRO format
CSR1 format
Descriptor list addresses format
CSR5 bits
CSR& format
CSR7format
CSR9 format
Revision Number and Missed Frame Count (CSR11) format
Receive descriptor format
Transmit descriptor format
Setup frame descriptor format
Perfect Fiitering setup frame buffer format
Imperfect Filtering setup frame format
DEC STD 134B Frame Format

1-2
1-2
1-3
1-5
3-1
5-3
5-4
5-5
5-6
5-9
5-13
5-14
5-15
5-16
5-19
5-23
5-24
5-26
6-2

FIGURES
1-1
1-2
1-3
1-4
3-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
6-1

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Contents

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7-1

7-2
7-3

7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11

8-1
8-2
8-3

8-4
8-5
8-6
8-7
9-1

9-2
9-3
9-4
9-5

9-6
9-7

9-8
9-9
9-10
9-11

9-12
9-13
9-14

9-15
9-16
B-1

TABLES
2-1
2-2
3-1

3-2
4-1

4-2

CSR13 format
CSR15 format
SGEC test loop hardware.
Serial Address register
Serial control register
Serial Data Register
SGEC address monitor hardware.
SGEC data bus monitor hardware.
Diagnostic frame descriptor format
Address Dump Diagnostics frame format
Address Load Diagnostics frame format
Typical SGEC CVAX Host synchronous system configuration
Typical SGEC CVAX Host asynchronous system configuration
GHIDRA local bus configuration
Block Diagram for 80386 System
SGEC configuration on fatwlre Ethernet llne.
SGEC configuration on DTE line.
SGEC configuration on twisted pair Ethernet line.
SGEC CLKA/CLKB timing
SGEC RESET Timing
SGEC slave read cycle Timing
SGEC Interrupt acknowledge Timing
CPU write cycle for SGEC In slave mode timing
NSGEC timing
External OMA cycle timing • Acquiring the CP • bus
External OMA cycle timing • Releasing the CP-BUS
Single Transfer SGEC read Cycle
Octaword Transfer SGEC Read Cycle
Single Transfer SGEC write Cycle
Octaword Transfer SGEC Write Cycle
Receive clock timing
Receive clock and Transmit clock timing
SERIAL RESET Timing
Serial link timing
SGEC Block Diagram

Minimum interframe gaps physical
Minimum interframe gaps virtual
SGEC pinout table
Plnout summary
Maximum bus holding time
Single read cycle

7-2
7-3

7-4
7-5

7-5
7-6
7-6
7-7

7-8
7-9
7-9

8-2
8-3
8-4
8-5
8-6
8-6
8-7
9-5
9-6
9-7

9-9
9-11
9-13
9-14
9-15
9-17
9-19

9-22
9-24
9-27
9-27

9-28
9-29
B-2

2-3
2-3
3-2
3-3
4-5
4-5
Ix

Contents

4-3
4-4
4-5
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19

5-20
5-21
7-1
7-2
7-3
7-4
7-5
7-6
9-1
9-2
9-3

!"""

9-4
9-5
9-6
9-7
9-8

9-9
9-10
9-11
9-12
9-13

9-14
x

Single write cycle
Octaword read cycle
Octaword write cycle
Bit access modes
CSRO bits
CSR1 bits
Descriptor lists addresses bits
CSR5 bits
CSR6 bits
CSR7 bits
CSR9 bits
CSR11 bits
RDESO bits
RDES1 bits
ROES2 bits
RDES3 bits
TDESO bits
TDES1 bits
TDES2 bits
TDES3 bits
Setup frame descriptor bits
Reception process state transitions
Transmission process state transitions
CSMA/CD counters
CSR13 bits
CSR15 bits
Serial Address Register
Serial control register
Serial Data register bits
Diagnostic descriptor
SGEC absolute maximum ratings
SGEC Electrical characteristics table
SGEC Electrical characteristic table
SGEC Electrical Signal Summary
SGEC CLKA CLKB Timing
SGEC RESET Timing
SGEC slave read cycle Timing table
SGEC slave read cycle,interrupt acknowledge cycle Timing
table
CPU write cycle Timing
NSGEC timing
External OMA cycle timing table • acquiring the CP • bus
External OMA cycle timing table - releasing the CP·BUS
Single Transfer SGEC read Cycle timing table
Octaword Transfer SGEC Read Cycle timing table

4-6
4-7

4-8
5-2
5-3
5-4
5-5
5-6
5-9
5-13
5-14
5-15
5-16
5-18
5-18
5-18
5-19
5-20
5-21
5-22
5-24
5-32
5-34
5-36
7-2
7-3
7-5
7-5
7-6

7-8
9-1
9-1
9-1
9-2
9-5
9-6
9-8
9-10
9-11
9-13
9-15
9-15
9-18

9-21

Contents

9-15
9-16
9-17
9-18
9-19
9-20
9-21
C-1

Single Transfer SGEC write Cycle timing table
Octaword Transfer SGEC Wrjte Cycle timing table
Transmit and Receive clock Timing
SGEC RESET Timing
Serial link Timing
SGEC timing· 100ns
SGEC timing - 60ns
Open issues

9-23
9-26
9-27
9-28

9-30
9-31
9-33
C-1

Preface
Executive summary
The SGEC is one of a two (three) chips Ethernet controller for low-end
systems connecting to lOBASES (10BASE2) cables. Another required chip
is an SIA (and a 10BASE2 transceiver).
The SGEC device is a second generation VLSI Ethernet controller. It is
part of the 32 bit CVAX VLSI device family, and directly compatible to the
pinout and bus timing of the CVAX.

The SGEC is superior to comparable devices in the market due to a
higher host bus transfer rate, better host bus utilization, provides higher
integration, as well as other features.
The SGEC connects directly to the 32 bit CP-BUS (CVAX Pin Bus),
communicating with the host through CSR's - Command and Status Registers
and a "host communication area" set up in main memory. For data
transfer it uses an on-chip DMA controller supporting both VAX virtual and
physical memory addresses.
The SGEC features a dual, internal FIFO for decoupled and separate
reception and transmission buffering facilitating efficient CP-BUS
utilization. The FIFO holds the data until, at least, the collision window is
passed.
The SGEC conforms to the DIGITAL CSMA/CD (ETHERNET) LOCAL
AREA NETWORK SPEOFICATION (DEC STD 134B).
The device is fabricated in Digital's CMOS-II dual-metal process and is
packaged in an 84 pin cerquad package.

xiii

Preface

Feature list

•
•
•
•

xiv

Direct interface to the 32-bit CP-BUS .
Host port interface sup:porting list structured descriptors with
ownership flags, VAX Virtual and physical memory addressing, and
errors and statuses reporting.
Up to 14 perfectly filtered addresses or a 512 bits imperfect hash filter .
Two on-chip 120 byte FIFOs for reception and transmission .

•

DIGITAL CSMAJCD (ETHERNET) LOCAL AREA NETWORK
SPECIFICATION (DEC STD 134B) compliant.

•

25 MHz system dock rate and independent serial dock variable from 1
to 10 MHz.

•
•
•
•

CP-BUS DMA octaword transfers at rates up to 20 MByte/sec .
CP-BUS parity generation and checking.
Meeting 9.6µS IPG - Inter Packet Gap· in most cases .
Full frame encapsulation including preamble generation and removal,
automatic 32-Bit FCS (CRC) generation and checking, and IEEE 802.3
pad bytes addition and stripping.

•

Programmable watchdog timers to prevent babbling transmission and
reception.

•
•
•

Loopback capability.
Single 5V power supply .
84 pin cerquad package .

Ethernet and IEEE 802.3 overview

1.1

Local Area Networks
Local Area Networks are communication networks extending from several
hundred to several thousand feet within a building or other facility. LANs
are a means of connecting various types of equipment for the purposes
of sharing resources and communicating in a distributed processing
environment. Although LANs using a range of speeds (from 2400 bits/sec
up to 10 Mbits/sec) exist today, the trend is clearly towards networks
between 1 and 10 million bits per second. Both Ethernet and the IEEE 802.3
specifications use 10 Mbits/sec speeds.

1.2

Ethernet in Digital
Ethernet has been Digital's LAN flagship in recent years. In 1982 Ethernet
was introduced into the DNA- Digital Network Architecture, at the data link
level, thus providing DECnet support over the Ethernet media for almost all
the CPU offerings ranging from VAXes to Personal Computers. Recently,
with the approval of the IEEE 802 family of LAN standards, Digital has
added IEEE 802.3 and parts of IEEE 802.2 support to its architecture.
Digital has publicly adopted the IEEE 802.3 standard and committed to
both Ethernet and IEEE 802.3 support, collectively known as CSMA/CD
LANs.
In addition to DECnet, Digital introduced several other products making
use of the Ethernet at the data link layer, but deviating from DNA at

higher layers and employing Digital developed proprietary protocols and
Transport mechanisms. All these protocols, as well as DECnet, coexist and
concurrently operate on the same wire, as illustrated by the figure.

1-1

nL!
Ethernet and IEEE 802.3 overview

Figure 1-1

Several of the Digital developed transport mechanisms
DECnet

LAVcluster

LAT

+-------------+
USER
+-------------+
+-------------+
I APPLICATION I
!PORT-TO-PORT I
+-------------+
+-------------+
I TRANSPORT I
I SESSION I
+-------------+
+-------------+
+-------------+
IPRBSBNTATION I
I CHAN. CONT. I
I BNO-TO-BNO I
+-------------+
+-------------+
+-------------+
ROUTING
ox
I TRANSPORT I
+--+-------------+----+-------------+----+-------------+--+
I
CSMA/CO DATA LINK
I

n
t i

+---------------------------------------------------------+

Distributed Systems in general, and Ethernet in particular, constitute
the cornerstone of Digital' s long range strate&Y. Products like DECnet,
Terminal Servers and other products such as various Local Area Servers
and Ethernet based Local Area VAXclusters are expected to significantly
enhance Digital' s offering in the Distributed Systems market by providing
fully distributed solutions to customers' business problems.

1.3

The IEEE 802 family of LAN standards
This family of standards is the effort undertaken by the IEEE to standardize

existing popular LAN implementations, such as the Ethernet and the Token
Passing based LANs, improving, enhancing and cleaning up various issues.
This family of standards constitutes the low level building blocks for other
standards organizations such as the ISO, which has adopted the IEEE
802 standards as the LAN Data Link level standards of its OSI - Open
System Interconnection model. Currently the IEEE 802 family consists of
the following:
Figure 1-2 802 family of standards

+----------------------------------+
002.1
I

+-----------------------------+
I+----------------------------+
11
802.2 LLC
I ---------------II

sublayer

I+----------------------------+
DATA LINK
I 802.3
802.4
802.S
LAYER
!+--------++--------++--------+
11 MAC
11 MAC
II MAC I
llsublayerllsublayerllsublayerl

II - - - -II- - - - II- - - - I----------------

11PHYSICAL11PHYSICAL11 PHYSICAL I PHYSICAL
11 layer 11 layer 11 layer I LAYER

+----++--------++--------++--------+ ----------------

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1-2

802.1- Describes the relationships among the IEEE 802 family of
standards and their relationship to the ISO/OSI model.

Ethernet and IEEE 802.3 overview

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1.4

802.2 - Describes the functions, features and protocols of the LLC
(Logical Link Control) sublayer of the Data Link layer. The LLC
Sublayer together with the MAC (Media Access Control) sublayer
form the complete Data Link layer. While the LLC sublayer is common
to all the access methods, the MAC sublayer is unique to and defined
within the access method standard.

802.3 - The standard for LANs employing CSMA/CD (Carrier Sense
Multiple Access with Collision Detection). The CSMA/CD media
access method is the means by which two or more stations share a
common bus transmission medium. This is the standard that emerged
from the Ethernet.

802.4 - Describes the elements of the Token Passing Bus access method
and its associated physical signaling and media technologies.

802.S - Describes the format and protocols used by the Token Passing
Ring MAC sublayer, the physical layer, and the means of attachment to
the token passing ring physical medium.

Ethernet and IEEE 802.3 elements
The Ethernet, which has gained wide acceptance by both large and small
corporations, is a~ speed (10 Mbps) LAN. The figure shows the main
components of the Ethernet network:
Figure 1-3 Ethernet Network Elements

+-------------------+
I
COMPUTER
I

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+----+
I

I
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+---------+---------+

I Ethernet interface
I
I
!Transceiver drop cable
COAX cable
I
++_ _ _ _ _ _ _ _ _ _ _ +---+_ _ _ _ _ _ _ _ _ _ _ ++

terminator

+---+

Transceiver

terminator

The cable is a low noise, shielded 50 ohm coaxial cable. Over this cable,
information is transmitted at the rate of 10 million bits per second.
Segments of the cable can be up to 500 meters (546.8 yards) in length
and can be extended into longer network lengths by using repeaters. A
repeater provides the signal regeneration that is required to strengthen the
data transmission signal along the extended length of the cable.
The transceiver, a small electronic device, transmits and receives signals
on the coaxial cable, and generally protects against failure and detects
electrical interference (referred to as collisions) on the cable. It is
connected to the cable using a simple tap and to the interface by means of
a transceiver cable which consists of four individual twisted pairs and may
be up to 50 meters (54.68 yards) in length.
The terminator is a passive device which fits on both ends of each cable
segment, providing proper electrical termination.
1-3

Ethernet and IEEE 802.3 overview

Finally, the interface provides the connection to the user or the server
station and performs such functions as:
•

Data encapsulation/decapsulation (frame assembly/disassembly)
handling of source and destination addressing
detection of physical channel transmission errors
frame delimiting

•

Network link management
collision avoidance

collision handling
•

Encoding and decoding of the signal to and from the transceiver

The key element of the Ethernet and IEEE 802.3 specifications is the media
access method (rules for using the shared coaxial cable). Commonly
referred to as Carrier Sense Multiple Access with Collision Detection
(CSMA/CD), it is a simple and efficient means of determining how a
station transmits information over a medium that is shared with other
stations. In order to transmit information, a station takes the following
steps:

CARRIER SENSE - Any station wishing to transmit "listens• first. If the
cable is busy (i.e. some other station is transmitting) the station waits
until the line is clear before transmitting.

MULTIPLE ACCESS - Any station wishing to transmit can do so. No
central controller is needed to decide who is able to transmit and in
what order. This is commonly referred to as distributed control, where
all stations on the network are peers with equal access.

COLLISION DETECTION - When the cable is free (no other station
is transmitting), a station can start transmitting. The transmitting
station (or stations) always listens while transmitting in order to detect
any other station transmitting on top of its own signal, causing a
"collision". In the event of such a collision, where two or more stations
are transmitting at the same time, the transmitting stations will continue
transmitting for a fixed time to insure that all transmitting stations
detect the collision. This is known as the "jam". After the jam, the
stations stop transmitting and wait a random period of time before
retrying. The range of random wait times increases (by the power of
2) with the number of successive collisions so that collisions can be
resolved even if a large number of stations are colliding (this is referred
to as the exponential back.off algorithm).

The three most significant characteristics of CSMA/CD based networks are
the passive nature of the network, its reliability and expandability. The
CSMA/CD media access method enables the network to operate without
central control or switching logic. If a station on the network malfunctions,
it does not affect the ability of other stations to communicate with each
other, nor affect the operation of the network.
A direct result of such a passive network is increased reliability. Total
network failure cannot be caused by a single station malfunctioning. A
system-wide failure can be caused by a cable malfunction such as an open
or short circuit or a continuously transmitting station, and system hardware
has built-in checks to detect and correct such situations.
1-4

Ethernet and IEEE 802.3 overview

The passive, distributed nature of a CSMA/CD based network also permits
easy expansion. Stations can be added to (or deleted from) an existing
network without reinitialization or reconfiguration of all other stations.
Such a capability supports future growth requirements through simple
expansion of the network.

1.5

Ethernet and IEEE 802 differences and coexistence
There are many minor differences in the hardware specifications. Some of
the 802.3 differences have special exceptions that allow for Ethernet, others
are incompatible. Fortunately, the signal put on the Ethernet cable remains
the same.
In terms of software, IEEE 802.3 and Ethernet are not compatible. 802.3

has a length field where Ethernet has a type field. The Ethernet type field
is a 16 bit field used to differentiate among different Ethernet users such
as DECnet, LAT (the terminal servers protocol) etc. Under the IEEE 802
standards, differentiation among multiple users
of the 802.2 LLC
specification. To that end, an 8 bit field is define - DSAP (Destination
Service Access Point).

is/art

The DNA CSMA/CD Data Link Functional Specification (Version 1.0.1,
12 February 1986) allows for the coexistence of Ethernet and IEEE 802.3
frames on the same wire and in the same node. The prerequisite is that
Ethernet protocol type field values be ALWAYS greater than the maximum
data length (1500).
Figure 1-4 ONA CSMA/CD frame formats
Octets:
Ethernet
format

46-1500

802.3

format

1-2

+-----+---+---+------+----+----+---+----------//---+---+
IPreamlD_AIS_A!LengthlDSAPjSSAP!Ctll Data
// PADjFCSI
+-----+---+---+------+----+----+---+--------//-----+---+

Field

Description

Pream

Preamble including the Start Frame Delimiter

D_A

Destination Data Link Address

S_A

Source Data Link Address

P_type

Protocol type field for Ethernet frames

Length

The data length field tor IEEE 802.3 frames

DSAP

Destination LLC Service Access Point address for IEEE 802.3 frames

SSAP
Ctl

Source LLC Service Access Point address for IEEE 802.3 frames
LLC Control field for IEEE 802.3 frames

Data

User data

PAD

Padding octets

FCS

Frame Check Sequence

+-----+---+---+------+------------------------//---+---+
IPreamjD_AjS_AIP_type!
Data
// PADIFCSI
+-----+---+---+------+----------------------//-----+---+

1-5

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Assumptions and goals

2.1

SGEC Basic Assumptions
This paragraph will list the assumptions which led to the design of the SGEC as an internal product.
Those assumptions also served as the baseline for the SGEC definition goals.

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•

Ethernet networks will continue to be used by DEC customers and by
DEC engineering community in the future for at least one more decade.

•

Current Ethernet VLSI devices do not provide an adequate integration
level for Digital products.

•

Present Ethernet devices have 60K - SOK transistors, but existing CMOS

n technology allows for more than 200K transistors per device.

•

Im.proved device performance in both the Serial Channel interface and
the system interface would significantly benefit Digital products.

•

VMS software compatibility and support is highly desirable within
Digital.

•

Ethernet VLSI devices are used in high volumes inside Digital, the
estimated numbers are around lSOK - 200K devices per year.

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2.2

SGEC Project Goals
The following paragraph will list the SGEC design goals. Those goals were derived from the above
list of assumptions. They were used to generate the specific list of functionality which was selected
for the SGEC.

Des~gri an Ethernet communication controller as part of the CVAX chip
family. Based on:

•

Ethernet networks will continue to be used by DEC customers and
by DEC engineering community in the future for at least one more
decade.

•

Current Ethernet VLSI devices do not provide an adequate
integration level for Digital products.

•

Ethernet VLSI devices are used in high volumes inside Digital, the
estimated numbers are around lSOK - 200K devices per year.

b. Design a VLSI Ethernet LAN controller superior in its serial channel
features to similar devices already available in the market, or planed in
the near future, based on:
•

Current Ethernet VLSI devices do not provide an adequate
integration level for Digital products.

•

Present Ethernet devices have 60K - SOK transistors, but existing
CMOS n technology allows for more than 200K transistors per
device.
2-1

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•~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Assumptions and goals

•

Improved device performance in both the serial channel interface
and the system interface would significantly benefit Digital
products.

c. Design a port architecture which will get VMS commitment. Based
on:
•

VMS software compatibility and support is highly desirable within

Digital.

2.3

Basic Definition guidelines
This paragraph will list the definition Guidelines for the SGEC Design.
The set of the SGEC device features was selected out of the envelope
of performance which can be designed into an Ethernet device. This set
selection was derived from the above two paragraphs stating the SGEC
device goals.

2.3.1

System Interface
This section will list the SGEC system interface definition guidelines:

2.3.2

•

The SGEC will provide the system designer a two chip solution for
10BASE% Ethernet network connection.

•

The device will fit into the CVAX system architecture including 32 bit
data and address bus interface and CVAX pin bus timing.

•

The SGEC bus transfer rate will match the CVAX pin bus rate and will
be up to 20 Mbyte/sec.

•

The SGEC will include two 120 byte FIFOs, which will allow a system
bus latency of approximately 2 microseconds for data transfers.

•

The SGEC will support VAX physical and virtual memory addressing.

•

The SGEC will interface to the CPU via a "host communication area
in host memory and via CSR's.

Serial Controller Features
This section will list the SGEC serial channel interface definition guidelines:
•

The SGEC will avoid shortcomings in the devices now on the market,
such as exponential backoff implementations and coupled serial and
system clocks.

•

It will perfectly filter 14 addresses or for more than 14 addresses will

contain a 512 bit hash mask and one physical address for imperfect
addresses filtering.

2-2

•

The SGEC will automatically discard incoming runt (colliding and too
short) frames.

•

The SGEC will automatically retransmite outgoing colliding frames.

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Assumptions and goals

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•

The SGEC will support a continuous packet rate of up to 14,000 frames
per second.

•

The following interframe gaps between successive, minimum length backto-back frames will be allowed in host physical memory interface mode.,
i.e., will not cause frame loss:

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Table 2-1

Minimum interframe gaps physical

Scenario

Minimum gap

Receive following receive

9.6 µSEC
4.8 µSEC
4.8 µSEC
9.6µSEC
9.6µSEC
9.6 µSEC

Receive following transmit
Receive following a collision
Transmit following transmit
Transmit following receive
Transmit following a collision

•

The following interframe gaps between successive, minimum length backto-back frames will be allowed in host virtual memory interface mode.,
i.e., will not cause frame loss:

Table 2-2 Minimum lnterframe gaps virtual
Scenario

Minimum gap

Receive following receive

19.2 µSEC

Receive following transmit

4.8µSEC
4.8µSEC
19.2 µSEC
9.6 µSEC
9.6 µSEC

Receive following a collision
Transmit following transmit
Transmit following receive
Transmit following a collision

,,
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•

The Transmite following a collision numbers, are valid for a backoff_
time • 0, for cases when this time is non zero it will define the
transmite following a collision timing.

•

The above numbers hold for the following system parameters:

~ .:

Maximum DMA latency • 2 µSEC.
Burst limit • 4 longwords.
System clock cycle • 80 NanoSEC.
Serial line clock cycle - 100 NanoSEC.

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PT
fl
\),;

2-3

PIN OUT

Figure 3-1

SGEC ptnout

'
_,

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M

a~aaa~•a•nn~•HUnu•u
31

VDD

CSIDP_L

CSIDP_L<2>

CSIDP_L<1>

CSIDP_L<O>

IM...L/1'EST <2>

IM...L/1'EST ct>

IM...L/1'EST Cl>

41
42
41

..
44

DC541

CCTL..L

SGEC

CSL_L

IM...LITEST CO>

vss
VDD
IRO..L

IAICEl_L

•

IAKEOJ.

NSGECJ.

TSM_H

DPE_L

TXEN_H

VDD
MU•~---~-UMRRWU•nnnn

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Note: The figure is the final pass 1 pinout. It is subject to change in future
revisions.

3-1

----------------------------------------------

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PIN OUT

3.1

Pinout tables
The chip will be packaged in an 84-pin fine lead (25 mil) surface mount
package.

Table 3-1

Usage

Width

Description

CVAX interface pins

DPE_L

10
10
10
10
10
10
10
10

CCTL_L

Cache Invalidate Signal (open drain)

ERR_L

Bus Error

NSGEC_L

Not SGEC Reference

CSL_L

Chip select

DMR_L

COAL
BM_LfTEST
CS/DP_L

AS_L

WR_L

DS_L
RDY_L

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CVAX Data and Address Lines

Byte Mask or Test

Cycle Status/Parity/Sync/Async

Address strobe
Data Strobe
Write
Ready (open drain)
Data Parity Enable Signal (open
drain)

OMA Request (open drain)

DMGl_L

OMA Grant Input

IRQ_L

Interrupt Request (open drain)

IAKEl_L

Interrupt Acknowledge Enable Input

IAKEO_L

Interrupt Acknowledge Enable Output

CLKA,B

CVAX Clock inputs

Sub total

56
Serial interface pins

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SGEC pinout table

Receive data

RCLK

Receive clock

RXEN_H

Receive enable

CLSN_H

Collision Detect

Transmit data

TCLK

TXEN_H

Sub total

3-2

Transmit clock

Transmit enable

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PIN OUT

Table 3-1 (Cont.) SGEC pinout table

Usage

Width

Deacription

Miscellaneous

RESET_L

8
9
1
1

Sub total

VDD

vss

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TSM_H

+5V Power
Ground
Test Mode
Reset

The following table summarizes the usage of the SGEC's pins.
Table 3-2 Pinout summary

Section

No. of pins

Comments

CP-BUS bus

Host bus connection

Serial bus

To/from SIA

Power and reset

Not used

Total

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3.2

Pinout Signal Descriptions
For all the pins names, suffix _L means that the pin is asserted when low,
and an _H means it is asserted when high. No suffix implies pin can be
driven both low and high.
•

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Reserved for future use

CDAL<31:0> - CVAX Data And Address Lines - (1/0 Pins)
The CVAX Data and Address bus (COAL) is a 32-bit time multiplexed
bus used to carry all data and address information between the SGEC,
host CPU and host memory. The strobe control signals AS_L and
DS_L determine whether the bus is currently carrying address or data
information.

•

BM_L/TBST<3:0> - Byte Mask/Test pins. - (1/0 Pins)
These pins have dual functions. in normal operation mode they carry
byte mask information; in test mode they are used as test pins. Mode
selection is done by the TSM_H pin.
The Byte Mask signals specify which data bytes of the current transfer
contain valid information during the data phase of the bus cycle. H
BM_LITEST<3>,BM_LITEST<2> are asserted, then CDAL<31:16>
contain valid data; if BM_LITEST < 1>,BM_LITEST<0 > then
CDAL<15:0>; if they are all asserted, then CDAL<31:0>.

3-3

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PINOUT

During read cycles, the byte masks indicate which bytes of data, and
which bits of parity, must be placed on the CDAL and Data Parity
lines; if this amounts to less than 32 bits, the other bytes of the CDAL
and bits of Data Parity are ignored. During write cycles, the byte
masks specify which bytes of the CDAL bus, and which Data Parity
bits, contain valid data. The BM_LrrEST < 3:0 > signals are initially
evaluated at the time AS_L is asserted, then each time DS_L is asserted
for multiple words transfer cycles.

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Note: When the SGBC is accessed as slave, these signal must be 110" as only
longword acceBBes are permitted to SGEC CSR's.
When the TSM_H pin is high, these pins are used as test pins. They
may be used to read and write test information from/to the SGEC.
Detailed test mode operation is provided in the Chapter 7.

•

CS/DP_L<3:0> are time-multiplexed signals. During the first part
of bus cycles, CS/DP_L< 2:0 >, in conjunction with the WR_L signal,
provide status about the current bus cycle. When the SGEC is bus
master, it initiates only D-stream read (no lock or modify intent) or
write no unlock bus cycles; when it is the bus slave, it responds to
only D-stream read (no lock or modify intent), write no unlock, or
interrupt acknowledge. Specifically, WR_L and CS/DP_L< 2:0 > mean
the following when AS_L is asserted:

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•

I
;

CS/DP_L<2:0>

Cycle type

H
H

LHH
HHH

Interrupt Acknowledge

HHH

Write no unlock

Demand D-stream read (no lock or modify
intent)

During the second part of bus cycles, CS/DP_L<3:0> provide byte
parity for the CDAL bus data. Even parity is checked/generated on
even bytes; odd parity on odd bytes. Even parity will drive a Low
when there are an even number of "l"'s in the byte's data; odd parity
will drive a Low for an odd number of "l'"s. CS/DP_L<3> is the
parity signal for CDAL<31:24>, CSIDP_L<2> for C0AL<23:16>,
CS/DP_L<l> for COAL<15:8>, CS/DP_L<O> for CDAL<7:0>. On
an SGEC read, the SGEC reads and checks data parity for the bytes
specified by BM_L<3:0> if Data Parity Enable (DPE_l) is asserted.
On an SGEC write , the SGEC generates data parity for all bytes,
irrespective of BM_L< 3:0 >.

.,....

WR_L

When the SGEC is bus master, it uses CS/DP_L<3> to tell the memory
controller whether this is a synchronous or an asynchronous bus
operation. The SGEC will drive it low for synchronous transfers.

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CS/DP_L<S:O> - Cycle Status/Data Parity- (I.JO Pins)

AS_L - Address Strobe - (I.10 Pin)
When the SGEC is the bus slave, the host CPU asserts AS_L to indicate
it has placed an address on the COAL lines. The SGEC latches the
CDAL information at that time, and interprets it as a physical address.
When the SGEC chip is bus master (i.e., when it is performing OMA
cycles to host memory), AS_L is used to indicate that it has placed a
physical address on the COAL lines.

3-4

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PINO UT

•

DS_L provides the timing control for the data transfer portion of the
cycle.

When the SGEC is the bus slave, in a read cycle the falling edge of
DS_L indicates the COAL lines are free to receive data from the SGEC
internal registers; the rising edge indicates that it has been latched by
the host CPU and can be removed. In a write cycle, the falling edge
indicates the host should place data on the COAL lines; the rising edge
indicates the data may be removed.

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When the SGECchip is bus master, during a read cycle DS_L is used
to indicate the memory controller should place data on the COAL lines;
the rising edge indicates it has been latched by the SGEC and can be
removed. In a write cycle, the falling edge indicates the SGEC has
placed data on the COAL lines, and the rising edge indicates the data
will be removed.
•

When the SGEC is the slave, if WR_L is asserted, the bus master
(CVAX.) will drive the CDAL lines at data time; if WR_L is not asserted
the SGEC is expected to supply data.

When the SGEC is bus master, it will use the Write signal to specify
the direction of the current bus transfer. If WR_L is asserted, the SGEC
will drive the CDAL lines at data time; if WR_L is not asserted, the
SGEC expects to get the data from the bus slave (memory controller).

In slave mode the SGEC sample the WR_L line at the time AS_L is
asserted. In master mode the SGEC drive this line during all the bus
cycle time.

•

RDY_L - Ready - (I/O Pin) - (Open Drain)
RDY_L is used to synchronize data transfers between the SGEC and
host CPU or memory controller. During the data phase of the bus
cycle, the bus master must wait for RDY_L to be asserted by the
addressed device before terminating the current cycle and latching (or
removing) data from the bus.

When the SGEC is in slave mode, RDY_L assertion signals a CSR
access or interrupt cycle completed.

WR_L - Write - (I.JO Pin)
The Write signal is used to specify the direction of the current bus
transfer.

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DS_L - Data Strobe - (J.10 Pin)

When the SGEC is the bus master, it waits for the slave (memory
controller) to assert RDY_L to indicate transfer completed.
•

DPB_L - Data Parity Enable - (1/0 Pin) - (Open Drain)
This pin is used to control CP-BUS parity checking.

During an SGEC master read or slave write DPE_L is asserted by
external logic in conjunction with the COAL data in order to enable
parity checking on the incoming CDAL data. When deasserted, the
CS/DP_L lines parity information part is ignored.

I. I

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3-5

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PIN OUT

During an SGEC master write, or slave read or interrupt acknowledge
cycles. the DPE_L pin will always be asserted by the SGEC in
conjunction with the CDAL data in order to indicate that valid parity
information is present.

•

CCTL_L - Cache invalidate control - (Output Pin) - (Open Drain)
This pin is used to signal to the host CPU that a memory location is

being written to and should initiate a conditional cache invalidate cycle.
•

ERR._L - Bus Error - (Input Pin)
This signal is used by external logic to indicate abnormal termination of
the current bus cycle. This is typically due to an uncorrectable memory

error.
The SGEC monitors this pin, never asserts it.
•

NSGEC_L - Not SGEC Reference. - (Output Pin)
The pin will be asserted when a bus cycle did not address the SGEC.
This pin is active only when the CSL_L pin was Low during reset.

•

CSL_L - Chip Select pin. - (Input Pin)
This pin is used for addressing the SGEC when the user has elected
not to use the internal predefined SGEC addresses or when multiple

SGEC's are present on the same CP-BUS.
•

DMR_L - DMA Request - {Output Pin) - (Open Drain)
Used to request bus mastership on the CP-BUS bus. Following the
assertion of the signal, the host asserts DMGI_L, allowing the SGEC to
take over the bus. The SGEC then performs one or more bus cycles
and deasserts DMR_L to relinquish the bus.

•

DMGl_L - DMA Grant Input - (Input Pin)
This pin is used for bus grant arbitration. If the SGEC has asserted

DMR_L, DMGI_L assertion tells the SGEC it acquired bus mastership.

•

IRQ_L - Interrupt Request - (Output Pin) - {Open Drain)
This line is used to signal interrupts from the SGEC to the host CPU.

•

IAKEI_L - Interrupt Acknowledge Enable Input - (Input Pin)
This pin is used to control interrupt arbitration. Interrupting devices
are usually daisy chained with IAI<EI_L coming from IAI<EO_L of the
preceding device in the chain.

•

IAI<EO_L is used to daisy-chain interrupting devices. It is usually
connected to IAI<El_L of the next device in the chain. IAI<EO_
L is asserted whenever the SGEC is not the target of an interrupt
acknowledge cycle. It permits the next device(s) in the chain to
acknowledge the interrupt.

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IAKBO_L - Interrupt Acknowledge Enable Output - (Output Pin)

•

CLKA, CLKB - Oock Inputs - (Input Pin)
Those two pins are the system clock input pins, they are
complementary clock phases, with CMOS level inputs.

3-6

~INOUT

Synchronous mode operation requires these clocks come from the
same source used to clock all other synchronous devices on the CPBUS. When working asynchronously they can be supplied from a
different source.

l. )

•

RX - Receive Data - (Input Pin)
This pin carries the input receive data from the SIA. The incoming data

should be synchronous with the RCLI< signal.
•

RCLK - Receive Oock - (Input Pin)
This pin carries the recovered receive clock supplied by an external

SIA. During idle periods the RCLK pin may be inactive.

•

RXEN_H - Receive Enable - (Input Pin)
This pin signals activity on the Ethernet cable to the SGEC. It is
asserted when receive data is present on the Ethernet cable and
deasserted at the end of a frame. It should be asserted and deasserted
synchronously with RCLI<.

•

CLSN_H - Collision Detect - (Input Pin)
This pin signals collision occurrence on the Ethernet cable to the SGEC.
It is asserted or deasserted by the SIA.

•

TX - Transmit Data - (Output Pin)
This pin carries the serial output data from the SGEC. The data is

synchronized to the TCLK signal.
•

TCLK - Transmit Oock - (Input Pin)
This pin carries the transmit clock supplied by an external SIA. This

clock should always be active.

•

TXEN_H - Transmit Enable - (Output Pin)
This pin signals SGEC transmit in progress to an external SIA.

•

+SV, supplied through eight pins.

•

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VDD-Power

VSS - Ground
Ground, supplied through nine pins.

•

TSM_H - Test Mode. - (Input Pin)

This pin is used for selecting the operating mode of the SGEC. When
tied to VDD, the SGEC is in test mode and pins BM_LITEST<3:0>
function as test pins. When connected to VSS, BM_LITEST<3:0>
carry the byte mask information.

•

RESET_L - Reset - (Input Pin)
Resets the SGEC to its initial state. This signal needs to be at least six
clock cycles high. During reset all output pins are tristated and all open
drain signals are floated. This signal is also used to synchronize the
internal clock phases.

Note: The NSGEC_L and IAKEO_L are exceptions to this rule at reset they
are deuserted and not floated.

3-7

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r 4

Host bus protocols

The SGEC uses the host bus to communicate with the host cpu and
memory controller (such as the CVAX and CMCTL chips). The SGEC
is directly compatible with the CP-BUS (CVAX pin bus) and uses a subset
of the CVAX chip inputs and outputs. It supports a subset of the CP-BUS
cycles (transactions) in either synchronous or asynchronous operating
modes. It operates as the bus slave when communicating with the CVAX
and as the bus master when communicating with the CMCTL. For detailed
timing information see Chapter 9, AC/DC Characteristics.

Note: The SGBC, being CP-BUS coct.~le, does not require nor checks for
the presence of CVAX or CM
chips. Although both the CVAX and
the CMCI'L are mentioned throughout this chapter, they merely represent
currently available CP-BUS compatible host cpu and memory controller
devices.

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Note: The term clock cycle used throughout this chapter, refers to the 80ns period
specified for the CMOS II CVAX family.

4.1

The SGEC operates in either synchronous or asynchronous mode when it
is the bus master. A CSR bit is used to select the mode.

When it is the bus slave, it only supports asynchronous mode.

t •.

Bus operating modes

4.1.1

Synchronous mode
When the SGEC is bus master in synchronous mode, CSIDP_L< 3 > is
driven low during the first part of the bus cycle.
Note: Synchronous mode operation gives the best attainable host bus
performance.

4.1.2

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!

Asynchronous mode
When the SGEC is in asynchronous mode, all inputs are routed through
synchronizers, thus it can take input signals with arbitrary timings.
However, the SGEC output signals are always driven as if it were
synchronous mode, with the exception that an additional delay cycle is
added between successive master OMA transfers.

4-1

r,.

Host bus protocols

t ;

4.2

Bus slave (CSRs accesses) operation
All host accesses to CSRs in the SGEC are canied out with the SGEC being
the slave. A detailed description of the CSRs is contained in Chapter 5,
Programming.
The supported CP-BUS cycles (transactions) are:

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•

Demand D stream read (no lock or modify intent), for host reading a
CSR.

•

Write no unlock, for host writing a CSR.

•

Interrupt acknowledge.

Only single transfers are supported in slave mode.

4.2.1

SGEC addressing

The CSRs addresses are allocated in the CVAX 1/0 address space. Every
SGEC is allocated 16 addresses, one for each CSR. CSRs are longwords
and only longword accessible.

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l

The SGEC contains the address decoding logic for a single set of CSRs at
20008000 through 2000803C (hex). - hereafter referred to as the internal
address. When multiple SGECs are to be used in a system, external logic
has to perform the address decoding and drive a chip select input (pin CSL_
L) to the SGEC.

The decision on whether to respond to the internal address or monitor
the CSL_L pin, is done at reset time. If pin CSL_L is pulled low at reset
time, the SGEC will respond to the internal address, else it will monitor
the CSL_L input.

When the SGEC is instructed to respond to the internal address, and for
CP-BUS cycles other than interrupt acknowledge, it also drives an output
pin - NSGEC_L. This pin will be asserted whenever the SGEC was not
addressed. NSGEC_L will be valid within one and a half clock cycles (six
phases) of the assertion of AS_L. If NSGEC_L was asserted, it will deassert
after AS_L deasserts.

t'.

4.2.2

Bus holding policy

The 16 CSRs of the SGEC are subdivided into two blocks:
1

Physical CSRs
CSRs 0-7,15 are physically present in the chip. Access to any of these
CSRs will take four to five clock cycles - until RDY_L is asserted.

Virtual CSRs
CSRs 8-14 are not physically present and are handled by the on-chip
processor. Host access to these CSRs is a two or three stage process.

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4-2

Host bus protocols

First, upon a host access the SGEC will assert RDY_L within four to
five clock cycles, then, the host must poll the CSR5<DN> bit, which
signals that the action, implied by the first CSR access, has completed.
If the first CSR access was a read, the host must reissue the read, and
only then will it receive valid data.

4.2.3

Host read cycle
A host read cycle takes the following steps:

The host initiates a read cycle by asserting AS_L with WR_L deasserted,
writing "111" to CS/DP_L<2:0> (demand D stream read) and driving the
address of the device register to be read onto the CDAL pins.

The SGEC latches the address, CS/DP_L<2:0>, BM_L<3:0> and
WR_L on the leading edge of AS_L.

The SGEC deasserts the NSGEC_L pin, and places data onto
CDAL<31:0>. Driving of CDAL pins begins as soon as the address is
decoded, so as to not leave them floating. However, the data driven is
arbitrary and should not be considered valid. Parity data is placed on
the CS/DP_L pins and DPE_L is asserted.

The SGEC then asserts RDY_L to inform the host that data on the
CDAL pins is valid.

Finally, after the host deasserts DS_L and AS_L, the SGEC deasserts
DPE_L and RDY_L.

A host read cycle takes from four to five clock cycles.

4.2.4

Host write cycle
A host write cycle takes the following steps:

The host initiates a write cycle by asserting AS_L, asserting WR_L,
writing "111" to CS/DP_L<2:0> (write no unlock) and driving CDAL
pins with the address of the device register to be written.

The SGEC latches the address, CS/DP_L<2:0>, BM_L<3:0> and
WR_L on the leading edge of AS_L.

The SGEC deasserts the NSGEC_L pin.

After DS_L has been asserted, the SGEC latches the data on
CDAL<31:0>, CS/DP_L<3:0> and DPE_L.

Note: The BM_L pins must be all "0", otherwise, the SGBC will ignore the
written data without any error indication.
5

The SGEC then asserts RDY_L to inform the host that the data has
been sampled.

Finally, after the host deasserts DS_L and AS_L, the SGEC deasserts
RDY_L.

If DPE_L was asserted, the SGEC checks the parity data. If a parity
error is detected, an interrupt is generated to the host cpu.

A host write cycle takes four to five clock cycles.

4-3

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Host bus protocols

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4.2.5

Interrupt acknowledge cycle

An interrupt acknowledge cycle follows the same general pattern as a host
read cycle.

The host initiates an interrupt acknowledge cycle by asserting IAKEI_L,
driving the IPL on COAL< 6:2 > with WR_L deasserted and writing
"011" to the CS/DP_L<2:0> pins.

The SGEC responds to an interrupt acknowledge cycle under the
following conditions:

M
L

•

The SGEC had requested an interrupt

•

IAI<El_L is asserted

•

The IPL driven on CDAL<6:2> matches the SGEC programmed
IPL

The SGEC then drives COAL< 15:2 > with the appropriate interrupt
vector (COAL<31:16,1:0> - "O"), places parity data onto CS/DP_L,
asserts DPE_L and asserts RDY_L to indicate to the host that a valid
vector address is present on COAL pins.

The host reads the interrupt vector, and resumes the cycle as for a host
read cycle. The SGEC releases IRQ_L, RDY_L, DPE_L and COAL pins.

H IAI<El_L asserts, but one of the other conditions is not met, the SGEC
asserts IAKEO_L to pass the interrupt acknowledge to the next device in
the interrupt acknowledge daisy chain.

4.3

Bus master (DMA) operation
The following CP-BUS cycles are supported:

•

Demand D-stream read (no lock or modify intent)

•

Write no unlock

The SGEC supports either single transfers or octaword transfers in either of
the above cycles.

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4.3.1

Bus arbitration and holding policy
The SGEC requests host bus mastership by asserting DMR_L, after
checking that DMGI_L is not asserted. The first bus cycle starts one to
two clock cycles following DMGI_L assertion. The bus is released by
deasserting DMR_L.

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The amount of time the SGEC will hold the bus is controlled by a
programmable parameter - burst limit. The burst limit parameter sets an
upper limit to the number of longwords which may be transferred before
releasing the bus. The SGEC supports burst limits of 1,2,4,8 longwords
or burst limit disable, in which case the SGEC holds the bus for as long
as it needs it, typically until the whole FIFO (120 bytes) completely fills
or empties. Table 4-1 specifies the maximum bus holding time versus
burst limit size (assuming no CMCTL delays and burst start address in not
octaword aligned):

M
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4-4

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-----

--------

---~-----------------------------

Host bus protocols

Table 4-1

Maximum bus holding time

Burst limit (longwords)

Holding time (clock cycles)

2
4

8
16

Disabled

150 approx.

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4.3.2

Single read cycle
In a single read cycle, the SGEC reads one longword from host memory.

A single read cycle takes upward of three clock cycles.
The steps in the single read cycle are described ,in Table 4-2.
Table 4-2 Single read cycle

Clock
cycle
1

Typical

phase
3

t '

The SGEC asserts AS_L, indicating that the address is
valid.

2
3

The SGEC tristates CDAL<31:0>.

The SGEC tests for cycle complete (ROY_L or ERR_L
asserted) once every clock cycle. In a normal, error-free
transfer, data is valid on CDAL<31:0>. When RDY_L is
asserted, with ERR_L deasserted, the SGEC latches the
data from CDAL<31:0>, CSIDP_L<3:0> and DPE_L.
Should an error occur (e.g., time out), extemal logic will
respond by asserting ERR_L with RDY_L deasserted.
The SGEC will Ignore the data on CDAL<31:0>.

SGEC deasserts DS_L.

SGEC deasserts AS_L.

t j

The SGEC drives the address onto CDAL<29:02>.
CDAL<31:30> are set "01" to indicate single transfer.
WR_L is deasserted. BM_L/TEST<3:0> are all asserted.
CS/DP_L<2:0> are set to "111" (demand D stream

react,.

Pins actions

3 ...

The SGEC asserts DS_L, indicating that the COAL bus is
free to receive incoming data.

If DPE_L was asserted, the SGEC does a parity check by computing the

CDAL<31:0> parity and comparing it to the CSIDP_L<3:0> pins. Should
a parity error be detected, the SGEC generates an interrupt to the host cpu.

4-5

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Host bus protocols

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n 4.3.3 Single write cycle

i !

In a single write cycle, the SGEC writes a single longword to host memory.

A single write cycle takes upward of three clock cycles.

The steps in the single write cycle are described in Table 4-3.
Tabla 4-3 Single write cycle
Clock
cycle

Typical
phase

The SGEC drives the address onto CDAL<29:02>.
CDAL<31:30> are set to "01" to indicate single
longword transfer. CCTL_L and WR_L are asserted.
BM_L/TEST <3:0> are asserted as required. CS/DP_
L<2:0> are set to 111 (write no unlock).

The SGEC asserts AS_L, indicating that the address is
valid.

The SGEC drives CDAL<31 :0> with valid data, drives
parity data onto CS/OP_L<3:0>, and asserts DS_L and
DPE_L. CCTL_L is deasserted.

The SGEC tests for cycle complete (RDY_L or ERR_L
asserted) once every clock cycle. RDY_L is asserted with
ERR_L deasserted. Should an error occur (e.g., time
·out), external logic will respond by asserting ERR_L with
RDY_L deasserted.

SGEC deasserts DS_L.

SGEC deasserts AS_L.

l '

3 ...

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4.3.4

Pina actions

Octaword read cycle
In an octaword read cycle, the SGEC reads four consecutive longwords,
supplying only the start address. This mode will be used when the burst
limit is set to 4 or greater, the SGEC needs four longwords and the start

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address is octaword aligned.

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An octaword read cycle takes upward of ten clock cycles.
The steps in the octaword OMA read cycle, no error, are described in
Table 4-4.

In case of an error (ERR_L asserted with RDY_L deasserted) in either of the

four longwords transfers, the SGEC aborts the read cycle after completing
the current longword transfer, by releasing the bus without completing the
transfer of any remaining longwords.

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4-6

Host bus protocols

Table 4-4 Octaword read cycle
Clock
cycle

Typical
phase

The SGEC releases CDAL<31:0>.

DS_L is asserted, indicating that the COAL pins are free
to receive incoming data.

The SGEC tests tor transfer complete (ROY_L or ERR_L
asserted) once every clock cycle. In a normal, error-free
transfer, data is asserted on CDAL<31:0>. RDY_L is
asserted with ERR_L deasserted and the SGEC latches
the data from the CDAL<31:0>, CS/DP_L<3:0> and
DPE_L pins.
First longword transfer is finished by deasserting DS_L.

3
4 ...

The SGEC reasserts DS_L.

The SGEC tests again for next transfer complete (RDY_L
or ERR_L asserted) once every clock cycle and reads the
next three longwords from the COAL pins as it did for the
first, finishing each transfer by dea.sserting DS_L.

SGEC deasserts DS_L tor the last time.

The octaword read cycle is finished by the SGEC
deasserting AS_L.

9 ...

The SGEC drives the address of the first longword
onto CDAL<29:02>. This address will always be
octaword aligned. COAL< 31 :30 > are set to "11" to
indicate octaword transfer. WR_L is deasserted. BM_
UTEST <3:0> are all asserted. CS/DP_L<2:0> are set
to "111" (demand D stream read).
The SGEC asserts AS_L, indicating that the address is
valid.

1l1fi"li

Pins actions

t The SGEC Is capable of initiating a longword transfer once every two clock cycles
in octaword transfer cycles, even though RDY_L is sampled every cycle.

If DPE_L was asserted, the SGEC does a parity check by computing the
CDAL<31:0> parity and comparing it to the CS/DP_L<3:0> pins. Should

a parity error be detected, the SGEC generates an interrupt to the host cpu.

4.3.5

Octaword write cycle
In an octaword write cycle, the SGEC writes four consecutive longwords,
supplying the start address only. This mode is used if the burst limit is set

to 4 or greater, the SGEC needs to write four longwords and the starting
address is octaword aligned.
An octaword write cycle takes upward of nine clock cycles.

The steps in the octaword DMA write cycle, no error, are described in
Table 4-5. In case of error (ERR_L asserted with RDY_L deasserted) in
either of the four longwords transfers, the SGEC will complete the whole
octaword write cycle driving the BM_L/TEST<3:0> to all "1", and only
then release the bus.

4-7

Host bus protocols

Table 4-5 Octaword write cycle
Clock
cycle

Typical
phase

The SGEC asserts AS_L, indicating that the address is
valid.

The SGEC drives CDAL<31 :0> with valid data, places
parity data onto CS/DP_L<3:0> and asserts DS_L and
DPE_L CCTL_L is deasserted.

The SGEC tests for transfer complete (RDY_L or EAR_L
asserted) once every clock cycle. In a normal, error-free
transfer, ROY_L ls asserted with ERR_L deasserted and
CMCTL reads the data from the COAL bus.

The SGEC reasserts DS_L CCTL_L is reasserted when
DS_L asserts for the third longword, and deasserted one
clock cycle later.

The SGEC tests again tor next transfer complete (ROY _L
or ERFl_L asserted) once every clock cycle and writes the
next three longwords to the COAL pins as It did for the
first, finishing each transfer by deasserting DS_L.

SGEC deasserts DS_L for the last time.

The octaword write cycle is finished by the SGEC
deasserting AS_L

First longword transfer is finished by deasserting DS_L

3
4 ...

9 ...

Pins actions
The SGEC drives the address of the first longword onto
CDAL<29:02>. This address will always be octaword
aligned. CDAL<31:30> are set to "11" to indicate
octaword transfer. CCTL_L and WR_L are asserted. BM_
L/TEST <3:0> are asserted as required. CS/DP_L<2:0>
are set to "111" (write no unlock).

t The SGEC is capable of initiating a longword transfer once every two clock cycles
in octaword transfer cycles, even though RDY_L is sampled every cycle.

4-8

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"'t ·:

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The operation of the SGEC is controlled by a program in host memory
called the port driver. The SGEC and the port driver communicate through
two data structures: Command and Status Registers (CSRs) located in the
SGEC and mapped in the host I/O address space, and through descriptors
lists and data buffers, collectively called Host Communication Area, in host
memory. The CSRs are used for initialization, global pointers, commands
and global errors reporting, while the host memory resident structures
handle the actions and statuses related to buffer management.

Programming

5.1

Programming Overview
The SGEC can be viewed as two independent, concurrently executing
rocesses: Reception and Transmission. After the SGEC completes its
nitialization sequence, those two processes alternate between three states:
STOPPED, RUNNING or SUSPENDED. State transitions occur as a result
of port driver commands (writing to a CSR) or various external events
occurrences. Some of the port driver commands require the referenced
process to be in a specific state.

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A simple programming sequence of the chip may be summarized as:
1

After power on (or reset), verifying the self test completed successfully.

Writing CSRs to set major parameters such as System Base Register,
Interrupt Vector, Address Filtering mode and so on.

Creating the transmit and receive lists in memory and writing the CSRs
to identify them to the SGEC.

Placing a setup frame in the transmit list, to load the internal reception
address filtering table.

Starting the Reception and Transmission processes placing them in the
RUNNING state.

Waiting for SGEC interrupts. CSRS contains all the global interrupt
status bits.

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Issuing a Poll Demand command, if either of the Reception or
Transmission processes enter the SUSPENDED state, after having
remedied the suspension cause.

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c#?<

-4'

,.,

The following sections contain detailed programming and state transitions
information.

5.2

Command and Status Registers
The SGEC contains 16 registers, most of which may be accessed by the
host while the rest are reserved.

5-1

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Programming

,..,

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[ :

5.2.1

Host_access to CSRs

The SGEC' s CSRs are located in VAX I/O address space.
The CSRs must be longword aligned and can only be accessed using
longword instructions. The address of CSRx is the base address plus 4x
bytes. For example, if the base address is 2000 8000, then the address of
CSR2 is 2000 8008. In the following paragraphs, CSRs bits are specified
with several access modes. The different access modes for bits are as
follows:

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Table S-1
Bit marked

Meaning

Reserved for future expansion - Ignored on Write, Read as "O"

Reserved for future expansion - Ignored on Write, Read as "1"

Read only, ignored on Write

PJW

Read or Write

Write only, unpredictable on Read

PJW1

Read, or Clear by writing a "1 ". Writing with a "O" has no effect.

In order to save chip real estate, yet not tie up the host bus for extended
periods of time, the 16 CSRs are subdivided into two groups:

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Physical CSRs - 0 through 7, 15.

Virtual CSRs - 8 through 14.

S.2.1.1

Physical CSRs
These registers are physically present in the chip. Host access to these
CSRs is by a single instruction (e.g., MOVL). There is no host perceivable
delay and the instruction completes immediately. Most commonly used
SGEC features are contained in the physical CSRs.

5.2.1.2

Virtual CSRs
These registers are not physically present in the SGEC and are incarnated
by the on-chip processor. Accesses to SGEC functions implied by these
registers may take up to 20 µseconds. So as not to tie up the host bus,
virtual CSR access requires several steps by the host.

CSRS<DN> is used to synchronize access to the virtual CSRs. Before
accessing a virtual CSR, CSRS<DN> must be checked to be set. After the
first virtual CSR access, the SGEC will zero CSR5<DN>. After the SGEC
completes the action, it will set CSRS<DN>.

The group the CSR is part of, determines the way the host will access it.

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Bit access modes

S.2.1.2.1

CSR write
To write to a virtual CSR the host takes the following actions:
1

Issue a write CSR instruction. Instruction completes immediately, but
the data is not yet copied by the SGEC.

Poll on CSR5 < DN >. No SGEC virtual CSR may be accessed before
CSRS < DN> asserts.

S-2

---------------

-----------------------

Programming

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s.2.1.2.2

CSR read

To read a virtual CSR the host takes the following actions:

5.2.2

Issue a read CSR instruction. Instruction completes immediately, but
no valid data is sent to the host.

Poll on CSRS<DN>. No SGEC virtual CSR may be accessed before
CSRS<DN> asserts.
.

Reissue a read CSR instruction, to the same CSR as in step 1. The host
receives valid data.

Vector Address, IPL, Sync/Asynch (CSRO)
Since the SGEC may generate an interrupt, on parity errors, during host
writes to CSR's, this register mu.st be the first one written by the host.
Figure 5-1

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CSRO format

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 s 4 3 2 1 0 9 8 7 6 s 4 3 2 1 0

.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·
II ISll 1 1 1 l 1 1 1 1 1 1 1 ll I - Interrupt Vector lllll CSRO
IP IAI
I v
I I I
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

Crucial: A parity error during CSRO host write may cause a host system crash due
to an erroneous Interrupt Vector. To protect against such an eventuality,

CSRO mu.st be written as follows:

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rl

Write CSRO.

Read CSRO.

Compare value read to value written. In values mismatch, repeat from
step 2.
4 Read CSRS and examine CSRS< ME> for pending parity interrupt.
Should an interrupt be pending, write CSRS to clear it.

Table 5-2 CSRO bits
Bit

Name

Acceu

Dncription

15:00

R/W

Interrupt Vector - During an Interrupt Acknowledge cycle
for an SGEC interrupt, this Is the value that the SGEC
will drive on the host bus CDAL<31 :0> pins (COAL pins
<1:0> and <31:16> are set to "0"). Bits <1:0> are
ignored when CSRO Is written, and set to "1" when read.

RMI

Sync/Asynch - This bit determines the SGEC operating
mode when It Is the bus master. When set, the SGEC
will operate as a synchronous device and when clear, the
SGEC wlll operate as a asynchronous device.

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5-3

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Programming

Table 5-2 (Cont.) CSRO bits

Bit

Nilme

Acceu

Description

31:30

R/W

Interrupt Priority - is the VAX interrupt priority level that the
SGEC will respond to.

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5.2.3

Polling Demand (CSR1)

3 3 2 2 2 2 2 2 2 2 2 2 l l l l l l l l 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 l 0

.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.
11 1 1 1 l 1 1 1 1 l l l l 1 1 l 1 1 1 1 1 1 1 l l l 1 l 1 1 llPI CSRl
I
IDI
,_,_,_,_,_,_,_._,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

l •

Tabla 5-3 CSR1 bits

5.2.4

Bit

Name

Access

Description

R/W

Polling Demand - Polls the receive list only If it has not
previously acquired a free descriptor. Checks the transmit
list for frames to be transmitted.

Reserved register (CSR2)
This entire register is reserved.

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Figura 5-2 CSR1 format

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IPL (hex)

Although the SGEC only has one interrupt request pin, that
pin might be wired to any of the four IRQ pins on the host.
The vaJue In IP should correspond to the IPL level that the
pin is wired to.

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5-4

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Programming

5.2.5

Descriptor List addresses (CSR3, CSR4)
The two descriptors lists heads address registers are identical in function,
one being used for the transmit buffer descriptors and one being used for
the receive buffer descriptors. In both cases, the registers are used to point
the SGEC to the start of the appropriate buffer descriptor list.

The descriptors lists reside in VAX physical memory space and must be
longword aligned.

[)

Note: For best performance, it is recommended that the descriptors lists be
octaword aligned.

Initially, these registers must be written before the respective Start
command is given (see Section 5.2.7), else the respective process will
remain in the STOPPED state. New list head addresses are only acceptable
while the respective process is in the STOPPlID or SUSPENDED states.
Addresses written while the respective process is in the RUNNING state,
are ignored and discarded.

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H the host attempts to read any of these registers before ever writing to
them, the SGEC responds with unpredictable values.

l .

Figure 5-3 Descriptor list addresses format
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 B 7 6 5 4 3 2 l 0 9 B 7 6 5 4 3 2 l 0 9 B 7 6 5 4 3 2 l 0

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.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.
IOIOI Start of Receive List - RBA

.-.-.-.-.-.-.-.-.-.-.-.-.-.-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·
IOIOI Start of Transmit List - TBA
IOIOI CSR4
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

Table 5-4 Descriptor lists addresses bits

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IOIOI CSR3

,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

5.2.6

Bit

Name

Ace ea

Description

29:00

RBA

R/W

Address of the start of the receive list. This is a 30-bit VPJ<
physical address.

29:00

TBA

R/W

Address of the start of the transmit list. This is a 30-bit
VPJ< physical address.

Status Register (CSR5)
This register contains all the status bits the SGEC reports to the host.

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.

5-5

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Programming

Figure 5-4 CSRS bits

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3 3 2 2 2 2 2 2 2 2 2 2 l l l l l l l l l l
l 0 9 8 7 6 5 4 3 2 l 0 9 8 7 6 5 4 3 2 l 0 9 8 7 6 5 4 3 2 l 0

.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.
IIISI SS ITS IRS lllllllOM 101111111111111111111TIRIMIRIRITIII CSRS
IDIFI
I I I I I I INI I I I I I I I I IWIWIEIUIIIIISI
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
Table 5-5 CSR5 bits
Bit

Name

Acc...

Description

R/W1

Interrupt Summary - The logical "OR" of CSR5 bits 1
through 6.

Passt restriction: This bit does not function properly in passl parts. It
may be fixed for pass2.
1

R/W1

r
r
r

r
n
n
n
n

•

Either all the frames In the transmit list have been
transmitted (next descriptor owned by the host), or
a frame transmission was aborted due to a locally
induced error. The port driver must scan down the
list of descriptors to determine the exact cause. The
Transmission process is placed in the SUSPENDED
state. Section 5.4.5 explains the Transmission
process state transitions. To resume processing
transmit descriptors, the port driver must issue the Poll
Demand command.

•

A frame transmission completed, and TDES1 <IC>
was set. The Transmission process remains in the
RUNNING state, unless the next descriptor is owned
by the host or the frame transmission aborted due to
an error. In the latter cases, the Transmission process
is placed in the SUSPENDED state.

R/W1

Receive Interrupt - When set, Indicates that a frame has
been placed on the receive list. Frame specific status
information was posted In the descriptor. The Reception
process remains in the RUNNING state.

R/W1

Receive buffer Unavailable - When set, indicates that the
next descriptor on the receive list is owned by the host
and could not be acquired by the SGEC. The Reception
process is placed in the SUSPENDED state. Section 5.4.4
explains the Reception process state transitions. Once
set by the SGEC, this bit will not be set again until a
Poll Demand is issued and the SGEC encounters a
descriptor it can not acquire. To resume processing
receive descriptors, the host must issue the Poll Demand
command.

Transmit Interrupt - When set, indicates one of the
following:

5-6

r
r

Programming

Table 5-5 (Cont.) CSRS bits
Bit

Name

Acceaa

Description

RJW1

Memory Error • Is set when any of the followings occur:

,..

•

SGEC is the CP-BUS Master and the ERR_L pin is
asserted by external logic (generally indicative of a
memory problem).

•

Parity error detected on an host to SGEC CSR write or
SGEC react from memory.

When a Memory Error is set, the Reception and
Transmission processes are aborted and placed In
the STOPPED state.

t ;

Note: At this point, it is mandatory that the port driver
issue a Reset command and rewrite all CSRs.
5

RJW1

Receive Watchdog Timer interrupt • When set, indicates
the Receive Watchdog Timer has timed out, indicating that
some other node is babbling on the network. Current frame
reception is aborted and RDESO<LE> and RDESO<LS>
will be set. Bit CSR5<RI> will also set. The Reception
process remains in the RUNNING state.

RJW1

Transmit Watchdog Timer interrupt • When set, indicates
the transmit watchdog timer has timed out, indicating the
SGEC transmitter was babbling. The Transmission process
is aborted and placed In the STOPPED state.

Done • When set, indicates the SGEC has completed a
requested virtual CSR access. After a reset, this bit is set.

18:17

Operating Mode • These bits indicate the current SGEC
operating mode as in the following table:

l ;

Value

Meaning

Normal operating mode.

Internal Loopback • Indicates the SGEC Is
disengaged from the Ethernet wire. Frames
from the transmit list are looped back to
the receive list, subject to address filtering.
Section 5.4.6 explains this mode of operation.

External Loopback • Indicates the SGEC is
working in full duplex mode. Frames from the
transmit list are transmitted on the Ethernet
wire and also looped back to the receive list,
subject to address filtering. Section 5.4.6
explains this mode of operation.

Diagnostic Mode· Explained in Chapter 7.

r
,

n
i

5-7

n
'

Programming

Table 5-5 (Cont.) CSRS bits

Bit

Name

Ac ens

Description

23:22

Reception process State - Indicates the current state of
the Reception process, as follows:

Value

Meaning

00
01
10

STOPPED
RUNNING
SUSPENDED

Section 5.4.4 explains the Reception process operation
and state transitions.
25:24

Value

Meaning

00
01
10

STOPPED
RUNNING
SUSPENDED

Section 5.4.5 explains the Transmission process operation
and state transitions.
29:26

Self test Status - The self test completion code according
to the following table. Only valid If SF is set.

Value

Meaning

0001
0010
0011
0100
0101
0100

ROM error
RAM error
Address filter RAM error
Transmit FIFO error
Receive FIFO error
Special loopback error

Pust info: Self test takes 30 milliseconds to complete.
30

Self test Failed - When set, indicates the SGEC self test
has failed. The self test completion code bits indicate the
failure type.

Initialization Done - When set, indicates the SGEC has
completed the Initialization (reset and self test) sequences,
and is ready for further commands. When clear, indicates
the SGEC is performing the Initialization sequence and
ignore all commands. After the Initialization sequence
completes, the Transmission and Reception processes are
in the STOPPED state.

n
n
I

5-8

Transmission process State - Indicates the current state of
the Transmission process, as follows:

r
r

n
r

Programming

5.2.7

Command and Mode Register (CSR&)
This register is used to establish operating modes and for port driver
commands.

Figure 5-5 CSR6 format
3 3 2 2 2 2 2 2 2 2 2 2 l l l l l l l l l l
10 9 8 7 6 s 4 3 2 l 0 9 8 7 6 s 4 3 2 l 0 9 8 7 6 5 4 3 2 l 0

.-.-.-.-.-.-.-.-.-.-.-.-.-.-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·
IRIIIBI BL 11111111111111111111111111tslsfOM IDIFISISIPIAF IHI csa6
l:&:IEIDI
I I I I I I I I I I I I I ITIRI
ICICIPICIBI
IPI
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

rt :

Table 5-6 CSR& bits
Bit

Name

Access

Description

A/W

Hash/Perfect filtering mode - When set, the SGEC will
interpret the setup frame as a hash table, and do an
imperfect address filtering. The imperfect mode is useful
when there are more than 14 multicast addresses to listen
to.

When clear, the SGEC will do a perfect address filter of
incoming frames according to the addresses specified in
the setup frame.

t '

Refer to the AF bits and Section 5.3.3 for related
information.

Note: Toggling this bit invalidates the internal address
filtering table. The table is not disturbed but the
receive logic will interpret its contents according
to the value of the HP bit. The port driver must
reload it with an appropriate setup frame. See
Section 5.3.3.3 for more details.
2:1

A/W

Address Filtering mode - These bits define the way
incoming frames will be address filtered:
Value

Meaning

r
r

Normal - Incoming frames will be filtered
according to the value of the HP bit.

Promiscuous - All incoming frames will be
passed to the host, regardless of the HP bit
value.

All Multicast - All incoming frames with
multicast address destinations will be passed
to the host. Incoming frames with physical
address destinations will be filtered according
to the value of the HP bit.

Unused - Reserved.

r
l I

n
i'
l

n
r

5-9

Programming

Table 5-6 (Cont.)

CSR6 bits

Bit

Name

Access

Description

R/W

Pass Bad Frames mode - When this bit is set, the SGEC
will pass frames that have been damaged by collisions or
are too short due to premature reception termination. Both
events should have occurred within the collision window (64
bytes), else other errors will be reported. bits SC,SP must
be set as no stripping will be performed.

When clear, these frames will be discarded and never show
up in the host receive buffers.

Passl restriction: This mode should not be used as it does not work
for frames shorter than 14 bytes. Consequently, the
SGEC may dead lock.
4

R/W

Strip CRC Disabfe mode - When set, the SGEC will transfer
CRC bytes, of a received frame, to host receive buffers.
When clear, the CAC bytes will not be transferred to the
host receive buffers. This bit does not affect the CRC
checking and reporting.

Note: For IEEE type frames, the CRC bytes will not be
moved to host memory. However, for Ethernet
type frames, the CRC bytes will be moved to host
memory but not reflected in the received frame
length RDESO<FL>. Consequently, as any frame
type might be arriving, host buffers should be large
enouri to accommodate the CRC bytes, else the
SGE might use the next buffer.
5
l!'fl!>

R/W

Strip Padding Disable mode - When this bit is set, the
SGEC will transfer padding bytes, of a received frame, to
host receive buffers.
When clear, the padding bytes and CRC bytes will not
be transferred to host receive buffers. This bit does not
affect the CRC checking and reporting.

Note: In order to strip the padding, the SGEC looks at
the frame length field in the receive frame. This
field is present in IEEE 802.3 frames, but not in
Ethernet frames. The SGEC makes its decision by
examining this field and if it is less than 1500, it
assumes it is dealing with an IEEE type frame and
perform the stripping, if enabled. Should Ethernet
type frames with protocol types less than 1500 be
expected, stripping of both padding and CRC should
be disabled, else frames might be corrupted.
Stripping of padding bytes means less CP-BUS
bandwidth is consumed for frames less than 64 bytes
long.

5-10

n
Programming

r
Table 5-6 (Cont.) CSR& bits

n
.

Bit

Name

Acceu
RIW

R/W

""t

Description
Force Collision mode - This bit allows the collision logic
to be tested. The chip must be in intemal loopback mode
for FC to be valid. If FC is set, a collision will be forced
during the next transmission attempt. This will result in 16
transmission attempts with Excessive Collision reported in
the transmit descriptor.
Disable data Chaining mode - When set, no data chaining
will occur in reception; frames, longer than the current
receive buffer, will be truncated and RDESO<FS> and
RDESO<LS> will always be set. The frame length
returned in RDESO<FL> will be the true length of the
non-truncated frame. It is up to the port driver to compare
the frame length with the buffer size, thus determine
whether a frame was actually truncated.
When clear, frames too long for the current receive buffer,
will be transferred to the next buffer(s) In the receive list.

n
....

9:8

R/W

Operating Mode - These bits determine the SGEC main
operating mode. Changing mode Is permitted only when
both the Reception and Transmission processes are in the
STOPPED state, and ignored otherwise. The port driver
must examine CSR5< OM> to verify the new setting took
effect.
Value

Meaning

Normal operating mode.

lntemal Loopback - The SGEC will loopback
buffers from the transmit list. The data will
be passed from the transmit logic back to the
receive logic. The receive logic will treat the
looped frame as it would any other frame, and
subject it to the address filtering and validity
check process.

External Loopback - The SGEC transmits
normally and in addition, will enable Its receive
logic to its own transmissions. The receive
logic will treat the looped frame as it would
any other frame, and subject It to the address
filtering and validity check process.

Diagnostic mode - Explained in the Chapter 7.

r
n
n
n
L I

5-11

r
n

r
r
r
.

Programming

Table 5-6 (Cont.) CSR6 bits
Bit

Ne me

Accns

Deacrlption

R/W

Start/Stop Reception command - When set, the Reception
process is placed in the RUNNING state, the SGEC
attempts to acquire a descriptor from the receive list
and process incoming frames. Descriptor acquisition
is attempted from the current position in the list. If no
descriptor can be acquired, the Reception process enters
the SUSPENDED state. The Start Reception command
is honored only when the Reception process is in the
STOPPED state. The first time this command is issued,
an additional requirement is that CSR3 must already have
been written to, else the Reception process will remain in the
STOPPED state.

r";

r
r
L •

When cleared, the Reception process is placed in the
STOPPED state, after completing reception of the current
frame. The next descriptor position in the receive list is
saved, and becomes the current position after reception
is restarted. The Stop Reception command is honored
only when the Reception process Is in the RUNNING or
SUSPENDED states.

r'
r
'

,..

Refer to Section 5.4.4 for more information.
11

Start/Stop Transmission command - When set, the
Transmission process is placed the RUNNING state, the
SGEC checks the transmit list at the current position for a
frame to transmit. If it does not find a frame to transmit,
the Transmission process enters the SUSPENDED state.
The Start Transmission command is honored only when
the Transmission process is In the STOPPED state. The
first time this command is issued, an additional requirement
is that CSR4 must already have been written to, else the
Transmission process will remain in the STOPPED state.

r
t

When cleared the Transmission process is placed in
the STOPPED state after completing transmission of
the current frame. The next descriptor position in the
transmit list is saved, and becomes the current position
after transmission is restarted. The Stop Transmission
command is honored only when the Transmission process
Is in the RUNNING or SUSPENDED states.

r
n

Refer to Section 5.4.5 for more information.
28:25

R/W

Burst Limit mode - Specifies the maximum number of
longwords to be transferred in a single OMA burst on
the host bus. Permissible values are 1,2,4,8. After
Initialization, the burst limit will be set to 1. Only
meaningful when BO is clear. Chapter 4 describes host
bus operation.

R/W

Burst Limit Disable mode - When set, the SGEC may
hold the bus for as long as it needs it. When cleared, BL
defines the maximum length of a OMA burst. Chapter 4
describes host bus operation.

n
i

n
n
....
I

5-12

n
.

Programming

M
l:

Table 5-6 (Cont.) CSR& bits

r
n
~.

5.2.8

Bit

Name

Accesa

Deacription

R/W

Interrupt Enable mode - When set, setting of CSR5 bits 1
through 6 will cause an interrupt to be generated.

R/W

Reset command - Upon being set, the SGEC will abort all
processes and start the reset sequence. After completing
the reset and self test sequence, the SGEC will set bit
CSR5<1D>. Clearing this bit has no effect.

System Base Register (CSR7)
This CSR contains the physical starting address of the VAX System Page
Table. This register must be loaded by host software before any address
translation occurs so that memory will not be corrupted.

;

Figure 5-6 CSR7 format

3 3 2 2 2 2 2 2 2 2 2 2 l l l l l l l l l l
l 0 9 8 7 6 5 4 3 2 l 0 9 8 7 6 5 4 3 2 l 0 9 8 7 6 5 4 3 2 l 0

.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.
System Base address
IOIOI

,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

r
r

Table 5-7 CSR7 bits
Bit

Name

ACCHS

Deacription

29:02

R/W

System Base address - The physical starting address
of the VAX System Page Table. Not used if VA (Virtual
Addressing) Is cleared in all descriptors.

r
r

CSR7

This rettiat•r should be loaded only once after a
resat. Subsequent modifications of this register at
any other time may cause unpredictable results.

5.2.9

CSR8
This register is reserved.

5.2.1 o Watchdog Timers (CSR9)

The SGEC has two timers that restrict the length of time in which the chip
can receive or transmit.

n
n
n
r

5-13

r
M
f;

Programming

Figure 5-7 CSR9 format
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 l l 1 l l l
l 0 9 8 7 6 5 4 3 2 1 o. 9 8 7 6 5 4 3 2 l 0 9 8 7 6 5 4 3 2 l 0

.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.

I ·CSR9
I TRANSMIT TIME-OUT - TT
I RECEIVE TIME-OUT - Rf
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
Table 5-8 CSR9 bits

Bit

Name

Accen

Description

15:00

R/W

TRANSMIT WATCHDOG TIME-OUT - The Transmit
Watchdog Timer protects the network against babbling
SGEC transmissions, on top of any such circuitry present
in transcievers. If the transmitter stays on for TT• 16 cycles
of the serial clock, the SGEC will cut off the transmitter
and set the CSR5<TW> bit. If the timer is set to zero, It
will never time-out. The value of TT is an unsigned integer.
With a 1O MHz serial clock, this prOVides a range of 1.6µs
to 1ooms. The default value is 12500 corresponding to
20ms.

31:16

R/W

RECEIVE WATCHDOG TIME-OUT - The Receive Watchdog
Timer protects the host cpu against babbling transmitters
on the network. If the receiver stays on for RT* 16 cycles
of the serial clock, the SGEC will cut off reception and set
the CSR5<RW> bit. If the timer is set to zero, It will never
time-out. The value of RT is an unsigned integer. With
a 1O MHz serial clock, this prOVides a range of 1.6µs to
100ms. The default value is 12500 corresponding to 20ms.

r
.

Pust restriction: A value less than 45 must not be programmed as the
SGBC will lock.
These watchdog timers are enabled by default. These timers will assume
the default values after hardware or software resets.

n
.I

5.2.11 CSR10

This register is reserved.

5.2.12 Revision Number and Missed Frame Count (CSR11)
This register contains a missed frame counter and SGEC identification
information.

n
ri
Ii

n
n
'

5-14

n
..

n
n
n
n
.

ffe'

Programming

Figure 5-8

Revision Number and Missed Frame Count (CSR11) format

3 3 2 2 2 2 2 2 2 2 2 2 l l l l l l l l l 1
i o 9 e 1 6 s 4 3 2 i o 9 e 7 6 s 4 3 2 i o 9 e 7 6 s 4 3 2 i

.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.

I CSRll
101010101010101010101010101 RN I
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_._,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

Table 5-9 CSR11 bits

Bit
15:00

Name
MFC

Access
R

18:16

Description
Missed Frame Count - Counter for the number of frames
that were discarded and lost because host receive buffers
were unavailable. The counter pins at all "1" and is
cleared when read by the host.
Chip Revision Number - This stores the revision number for
this particular SGEC.

Passl info: RN is set to 1.

5.2.13 Diagnostic Registers (CSR12, 13, 14, 15)
These registers are described in Chapter 7, Diagnostics and Testing.

r
,..

n
'

u
M
f. !

n
n
n
!!!<

5.3

Descriptors and buffers format
The SGEC transfers frame data to and from receive and transmit buffers in
host memory. These buffers are pointed to by descriptors which are also
resident in host memory.
There are two descriptor lists: one for receive and one for transmit. The
starting address of each list is written into CSRs 3 and 4 respectively.
A descriptor list is a forward-linked (either implicitly or explicitly) list
of descriptors, the last of which may point back to the first entry, thus
creating a ring structure. Explicit chaining of descriptors, through setting
xDESl<CA> is called Descriptor Chaining. The descriptor lists reside in
VAX physical memory address space.
Note: The SGBC first reads the descriptors, ignoring all unused bits regardless
of their state. The only word the SGBC writes back, is the first word
(xDBSO) of each descriptor. Unused bits in xDBSO will be written as "0".
Unused bits in xDBSl - xDES3 may be used by the port driver and th-e
SGEC will never disturb them.
A data buffer can contain an entire frame or part of a frame, but it cannot
contain more than a single frame. Buffers contain only data; buffer status
is contained in the descriptor. The term Data Chaining is used to refer to
frames spanning multiple data buffers. Data Chaining can be enabled or
disabled, in reception, through CSR6<DC>. Data buffers reside in VAX
memory space, either physical or virtual.

jj'

5-15

n
n
'

Programming

5.3.1

r
r
r

r
r.
'

r
r
r

Receive descriptors
The receive descriptor format is shown in Figure 5-9, and described in the
following paragraphs.
Figure 5-9 Receive descriptor format
3 3 2 22222 22 22 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 321 0

.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.

101
IEILID'l' IRIOIPILITILIPIOITIDICIOI RDESO
fwl
Frame Length
ISl!I IPI fSISILICITI INIBIEIFI
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_._,
ICIVlufulululululululuf ulululululululululululululululululululuful RDESl
IAIAI I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
I I
I I I I I I I I
I I RDES2
lul
Buffer Size
lululululululul Page Offset lul
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
I
ful RDES3
I
SVAPTE/Physical Address
I I
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
O - SGIC writes as "0"
u - Ignored by the SGIC on read, never written
RDESO word
RDESO word contains received frame status, length and descriptor
ownership information.

5.3.1.1

Note: With the exception of RDESO<OW> and RDESO<FS>, all RDESO bits
are valid only if the current descriptor buffer contains the last segment of
a received &ame - RDESO<LS> set.

Table 5-10 RDESO bits
Bit

Name

Description

Overflow - When set, indicates received data in this descriptor's buffer was
corrupted due to internal FIFO overflow. This will generally occur if SGEC
OMA requests are not granted before the internal receive FIFO fills up.

CRC Error - When set, indicates that a CRC error has occurred on the
received frame. All incoming frames are CRC checked, regardless of the
strip CRC or padding functions.

Dribbling Bits - When set, Indicates the frame contained a non-integer
multiple of eight bits. This error will be reported only If the number of
dribbling bits in the last byte is greater than two. The CRC check is
performed independent of this error, however, only whole bytes are run
through the CRC logic. Consequently, received frames with up to
seven dribbling bits will have this bit nt, but If CE (or other error
indicators) are not nt, they should be considered valid.

Translation Not Valid • When set, indicates that a translation error occurred
when the SGEC was translating a V~ virtual buffer address. It will only set
if RDES1 <VA> was set. The Reception process remains in the RUNNING
state and attempts to acquire the next descriptor.

Frame Type - When set, indicates the frame is an Ethernet type frame.
When clear, indicates the frame is an IEEE 802.3 type frame.

n
n
n

n
n
r

5-16

n
Programming

n
n
.
'

.n
'

r
r

r
r
r,.,
l:

n
n

Table 5-10 (Cont.) RDESO bits
Bit

Name

Description

Late Collision - When set, indicates the frame was damaged by a collision
that occurred after the collision window has passed.

Frame Too Long - When set, indicates the frame length exceeds the
maximum Ethemet specified size of 1518 bytes .

Last Segment - When set, indicates this buffer contains the last segment of
a frame and status Information Is valid.

Note: The last buffer of a frame may be devoid of any data.

First Segment - When set, indicates this buffer contains the first segment of
a frame.

Runt Frame - When set, indicates this frame was damaged by a collision or
premature termination before the collision window had passed. Runt frames
will only be passed on to the host If (CSR6<PB>) Is set.

13:12

Data Type • Indicates the type of data the buffer contains, according to the
following table:

Value

Meaning

Normal received frame

Internally looped back frame

Externally looped back frame

Length Error - When set, indicates one of the following:
•

The frame segment does not fit within the current buffer and the SGEC
does not own the next descriptor. The frame is truncated.

•

The Receive Watchdog timer expired. CSR5<RW> is also set.

Error Summary - The logical "OR" of RDESO bits OF,CE,TN,LC,TL,LE,RF.

30:16

Frame Length - The length in bytes of the received frame.

Own bit - When set, indicates the descriptor is owned by the SGEC. When
cleared, indicates the descriptor is owned by the host. The SGEC clears
this bit upon completing processing of the descriptor and its associated
buffer.

5.3.1.2

RDES1 word

.... '

n
5-17

r
i

Programming

Table 5-11

r
r

RDES1 bits
Name

Descriptor

Virtual Addressing - When set, RDES3 is interpreted as a SVAPTE
(System Virtual Address of Page Table Entry). The SGEC uses RDES3
and RDES2< Page Offset> to perform a VAX virtual address translation
process to obtain the physical address of the buffer. When clear, RDES3 is
interpreted as the actual physical address of the buffer.

Chain Address - When set, RDES3 is interpreted as another descriptor's
VAX physical address. This allows the SGEC to process multiple, noncontiguous descriptor lists and explicitly "chain" the lists. Note that
contiguous descriptors are implicitly chained.

Bit

5.3.1.3

RDES2 word

Table 5-12 RDES2 bits

r,...

Bit

Name

Descriptor

08:00

Page Offset - The byte offset of the buffer within the page. Only meaningful
if RDES1 <VA> is set.

Note: Receive buffers must be word aligned.
30:16

Buffer Size - The size, in bytes, of the data buffer.

Passl restriction: When Data Chaining is enabled (CSR6<DC> clear), buffer size
must be 256 bytes or greater. While permitted, smaller buffers may
cause overflow errors.

5.3.1.4

RDES3 word

Table 5-13 RDES3 bits
Bit

Name

31:00

SVIPA

Descriptor
SVAPTE/Physical Address - When RDES1 <VA> is set, RDES3 is
interpreted as the System Virtual Address of Page Table Entry and used in
the virtual address translation process. When RDES1 <VA> is clear, RDES3
is interpreted as the physlcal address of the buffer. When RDES1 <CA> is
set, RDES3 is interpreted as the VAX physical address of another descriptor.

Note: Receive buffers must be word aligned.

5.3.2

n
n
n
n
-

I ~-

Transmit descriptors
The transmit descriptor format is shown in Figure 5-10, and described in
the following paragraphs.

5-18

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Programming

r
~

I\
~

Figure 5-10 Transmit descriptor format
3 3 2 2 2 2 2 2 2 2 2 2 l l l l l l 1 l l l
1 0 9 8 7 6 5 4 3 2 l 0 9 8 7 6 5 4 3 2 l 0 9 8 7 6 5 4 3 2 l 0

.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.

IOIOI
IBIOIOILILINILIEIHI Coll. ITIUIDI TDESO
IWI
I
TOR
ISi I IEIOICICICIFI Count INIFIEI
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
ICIVIDT IAIFILIIlulululululululululululululululululululululululul TDESl
IAIAI
1c1s1s1c1 I I I I I I I I I I I I I I I I I I I I I I I I
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
I I
I I I I I I I I
I TDES2
lul
Buffer Size
lululululululul Page Offset
I
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

SVAPTE/Physical Address

I TDES3
I

,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

O - SG!C writes as "0"
u - Ignored by the SGEC on read, never written

5.3.2.1

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Table 5-14 TDESO bits
Bit

Name

Description

Deferred - When set, indicates that the SGEC had to defer while trying to
transmit a frame. This condition occurs If the channel Is busy when the
SGEC is ready to transmit.

Underflow Error - When set, indicates that the transmitter has truncated
a message due to data late from memory. UF Indicates that the SGEC
encountered an empty transmit FIFO while In the midst of transmitting a
frame. The Transmission process enters the SUSPENDED state and sets
CSR5<TI>.

Translation Not Valid • When set, indicates that a translation error occurred
when the SGEC was translating a VAX virtual buffer address. It may
only set If TDES1 <VA> was set. The Transmission process enters the
SUSPENDED state and sets CSR5<TI >.

06:03

Collision Count - A four bit counter indicating the number of collisions
that occurred before the transmission attempt succeeded or failed. A
count of zero Indicates that there were no collisions or that the frame was
aborted after 16 collisions (the cases can be distinguished by examining
TDESO<EC>. )

Heartbeat Fall - When set, indicates Heartbeat Collision Check failure
(the transceiver failed to return a collision pulse as a check after the
transmission. Some transceivers do not generate heartbeat, and so will
always have this bit set. If the transceiver does support It, it indicates
transceiver failure.)

Excessive Collisions - When set, indicates that the transmission was aborted
because 16 successive collisions occurred while attempting to transmit the
current frame.

Late Collision - When set, indicates frame transmission was aborted due to
a late collision.

n
n

TDESO word

TDESO word contains transmitted frame status and descriptor ownership
information.

5-19

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Programming

. Table 5-14 (Cont.) TDESO bits
Bit

Name

Description

No Carrier - When set, indicates the carrier signal from the transceiver was
not present during transmission (possible problem in the transceiver or
transceiver cable).

Meaningless in internal loopback mode (CSR5<0M>-1).
Loss of Carrier - When set, indicates loss of carrier during transmission
(possible short circuit in the Ethernet cable).
Meaningless in internal loopback mode (CSR5<0M>•1).

Length Error - When set, indicates one of the following:

•

The SGEC encountered a descriptor it did not own, or a chain descriptor
(TDES1 <CA> • 1), In the middle of data chained descriptors (a frame
spanning multiple buffers).

•

Zero length buffer in the middle of data chained descriptors.

•

Wrong data type (TOES1 <DT> not equal 0) in the middle of data
chained descriptors.

•

Incorrect pairing of TDES1 < FS > and TDES1 <LS>.

The Transmission process enters the SUSPENDED state and sets
CSR5<TI>.
15

Error Summary • The logical "OR" of UF, TN, EC, LC, NC, LO and LE.

29:16

TOR

Time Domain Reflectometer • This is a count of bit times (1 bit time • 100
ns on 10BASE5 networks), and is useful for locating a fault on the cable
using the velocity of propagation (about 5 ns I meter) on the cable. Only
valid If TOESO<EC> is also set. Two such aborts (Excessive Collisions) in
a row and with the same or similar (within 20) TOR values indicate a possible
cable short (when also TDESO<LO> is set) or open (TDESO<LO> clear).

Own bit • When set, indicates the descriptor is owned by the SGEC. When

r
~

cleared, Indicates the descriptor Is owned by the host. The SGEC clears
this bit upon completing processing of the descriptor and Its associated
buffer.

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l

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5.3.2.2

TDES1 word

Table 5-15 TDES1 bits
Bit

Name

Descriptor

Interrupt on Completion· When set, the SGEC will set CSR5<TI> after
this frame has been transmitted. To take effect, this bit must be set in the
descriptor where LS Is set.

Last Segment • When set, indicates the buffer contains the last segment of
a frame.

First Segment - When set, Indicates the buffer contains the first segment of
a frame.

5-20

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Programming

Table 5-15 (Cont.) TDES1 bits
Bit

Name

Descriptor

Add CRC disable - When set, the SGEC will not append the CRC to the
end of the transmitted frame. To take effect, this bit must be set In the
descriptor where FS ls set.

29:28

Data Type - Indicates the type of data the buffer contains, according to the
following table:
Meaning

00
10

Setup frame - Explained in Section 5.3.3.

Diagnostic frame - Explained in Chapter 7.

Normal transmit frame data

Virtual Addressing - When set, TDES3 is interpreted as a SVAPTE
(System Virtual Address of Page Table Entry). The SGEC uses TDES3
and TDES2<Page Offset> to perform a VAX virtual address translation
process to obtain the physical address of the buffer. When clear, TDES3 is
interpreted as the actual physical address of the buffer.

Chain Address - When set, TDES3 ls interpreted as another descriptor's
VAX physical address. This allows the SGEC to process multiple, noncontiguous descriptor lists and explicitly "chain" the lists. Note that
contiguous descriptors are implicitly chained.

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Value

5.3.2.3

TDES2 word

Table 5-16 TDES2 bits
Bit

Name

Descriptor

08:00

Page Offset • The byte offset of the buffer within the page. Only meaningful
If TDES1 <VA> is set.

Note: Transmit buffers may start on arbitrary byte boundaries.

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5-21

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Programming

Table 5-16 (Cont.) TOES2 bits

Bit

Name

Dncriptor

30:16

Buffer Size - The size, in bytes, of the data buffer. If this field is 0, the
SGEC will skip over this buffer and ignore it. The frame size is the sum of
all BS fields of the frame segments (between and including the descriptors
having TDES1 <FS> and TOES1 <LS> set).

Passl restriction: Buffer sizes must be set according to the following table:
Range of
buffer sizes
(bytes)

Position (within data
chalned dncrlptors)

TDES1<FS>
state

TDES1<LS>
state

First

1 to 64

Intermediary

256 at least

Last

1 at least

Any

First and only

Deviation from these rules, while permitted, may result in
underflow errors.

Note: If the port driver wishes to suppress transmission of a frame, this
field must be set to 0 in all descriptors comprising the frame and
prior to the SGBC acquiring them. If this rule is not adhered to,
corrupted frames might be transmitted.

l '

5.3.2.4

TDES3 word

Table 5-17 TDES3 bits

Bit

Name

Descriptor

31:01

SVIPA

SVAPTE/Physical Address - When TDES1 <VA> is set, TDES3 is interpreted
as the System Virtual Address of Page Table Entry and used in the virtual
address translation process. When TDES1 <VA> is clear, TOES3 is
interpreted as the physical address of the buffer. When TDES1 <CA> is
set, TOES3 is interpreted as the VAX physical address of another descriptor.

Note: '.fransmit buffers may start on arbitrary byte boundaries.

5.3.3

Setup frame
A setup frame defines SGEC Ethernet destination addresses. These
addresses will be used to filter all incoming frames. The setup frame
is never transmitted over the Ethernet, nor looped back to the receive
list. While ~e setup frame is being processed, the receiver logic will
temporarily disengage from the Ethernet wire - around SOµseconds. The
setup frame size is always 128 bytes and must be wholly contained in a
single transmit bUffer. There are two types of setup frames:

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5-22

Perfect Filtering addresses (14) list

Imperfect Filtering hash bucket (512) heads + one physical address

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Programming

5.3.3.1

First setup frame
A setup frame must be queued (placed in the transmit list with SGBC
ownership) to the SGEC before the Reception process is started, except for
when the SGEC operates in promiscuous reception mode.

5.3.3.2

Subsequent setup frame
Subsequent setup frames may be queued to the SGEC while the Reception
process is in the RUNNING, SUSPENDED or STOPPED (except when
changing filtering mode, see Section 5.3.3.3) state, nor does it affect the
state of the Reception process. The only requirement for the setup frame to
be processed, is that the Transmission process be in the RUNNING state.
The setup frame will be processed after all preceding frames have been
transmitted and after the current frame reception, if any, is completed.

5.3.3.3

Changing filtering mode
When switching filtering mode from prefect to imperfect (or vice versa), the
following steps must be taken:

'
'

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'

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n
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n,...
.
.

5.3.3.4

Figure 5-11

A Stop Reception (CSR6< SR>) command must be issued (unless the
Reception process is already in the STOPPED state).

The driver must verify the Reception process is STOPPED by repeatedly
examining CSR5< RS>.

Toggle CSR6<HP>.

Queue a setup frame and wait for indication that it has been processed.

Start the Reception process with a Start Reception (CSR6<SR>
command.

Setup frame descriptor
The setup frame descriptor format is shown in Figure 5-11, and described
in the following paragraphs.

Setup frame descriptor format

3322222222 2 2 l l l l l 1 1 1 1 1
1 09 8 7 6 5 4 3 2 1 09 8 7 6 5 4 3 21 09 8 7 6 5 4 321 0
.-.-.-.-.-.-.-.-·-·-·-·-·-·-·-·---.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.
101010101010101010101010101010101BIOISIOIOIOIOIOIOIOIOIOIOIOIOIOI SDBSO
1w1
I I I I I I I I I I I I I I Isl IBI I I I I I I I I I I I I I
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
lulul DTI I I IIlulululululululululululululululululululululululul SDBSl
I I I I I I 1c1 I I I I I I I I I I I I I I I I I I I I I I I I
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_I
I I
lulululululululululululululululul SDBS2
Il_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_I
uI
suffer size
I I III I IIII II II III
juju!
lul SDBS3
II I
Setup buffer Physical Address
I I
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
O- SGBC writes as "0"
u - Ignored by the SGBC on read, never written

5-23

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.

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1

Programming

Table 5-18 Setup frame descriptor bits

Word

Bit

Name

Description

SDESO

Setup Error - When set, indicates the setup frame buffer
size in not 128 bytes .

Error Summary - Set when SE is set.

Own bit - When set, indicates the descriptor is owned by
the SGEC. When cleared, indicates the descriptor is owned
by the host. The SGEC clears this bit upon completing
processing of the descriptor and Its associated buffer.

Interrupt on Completion - When set, the SGEC will set
CSR5<TI> after this setup frame has been processed.

29:28

Data Type - Must be 2 to indicate setup frame.

.'.

SDES1

SDES2

30:16

Buffer Size - Must be 128.

SDES3

29:1

Physical Address - Physical address of setup buffer.

Note: Setup buffer must be word aligned.

5.3.3.5

Perfect Filtering setup frame buffer
This section describes how the SGEC interprets a setup frame buffer when
CSR6<HP> is clear.

The SGEC can store 14 - full 48 bits Ethernet - destination addresses. It will
compare the addresses of any incoming frame to these, and reject those
which do not match.
The setup frame must always supply all 14 addresses. Any mix of physical
and multicast addresses can be used. Unused addresses should be
duplicates of one of the valid addresses. The addresses are formatted
as shown in the figure below.

M
l:

Figure 5-12 Perfect Fiitering setup frame buffer format

M
L

Figure 5-12 Cont'd. on next page

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,...

5-24

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Programming

Figure 5-12 (Cont.) Perfect Filtering setup frame buffer format
31

bit

+-------+------+------+-------+
Bits<3110> I
ADDRESS_OO
<-- Physical/Multicast bit
Bits<47:32>lxxxxxxxxxxxxxxl

11----------------------------ADDRESS_Ol
lxxxxxxxxxxxxxxl

1----------------------------1
ADDRESS_02
lxxxxxxxxxxxxxxl

!----------------------------'
ADDRESS_03

lxxxxxxxxxxxxxxl

!-----------------------------

r!
Il

1-----------------------------1
I
ADDRESS_12
I

lxxxxxxxxxxxxxxl
I
1-----------------------------1
I
ADDRESS_13
I
lxxxxxxxxxxxxxx I

1-----------------------------1
lxxxxxxxxxxxxxxxxxx:xxxxxxxxxxxl
lxxxxxxxxxxxxxxxxxxxrmxxxxxl
lxxxxxxxxxxxxxxxxxxxxxxxxxxxxxl
lxxxxxxxxxxxxxxxxxxxxxxxxxxxl

+-------+------+------+-------+

xxxxxx • don't care

The low-order bit of the low-order bytes is the address's multicast bit.
Example 5-1 illustrates a Perfect Filtering Setup buffer (fragment).

Example 5-1
0

Perfect filtering buffer

Ethernet addresses to be filtered1
AS-09-65-12-34-76
09-:SC-87-DB-03-15

Setup frame buffer fragment:
126509A8
00007634
DB87:SC09
00001503

D Two Ethernet addresses written according to the DEC STD 134
specification for address display.
S

Those two addresses as they would appear in the buffer.

n
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,..
I

5-25

Programming

u
5.3.3.6

The SGEC can store 512 bits, serving as hash bucket heads, and one
physical 48 bit Ethernet address. Incoming frames with multicast destination
addresses will be subjected to the imperfect filtering. Frames with physical
destination addresses will be checked against the single physical address.

For any incoming frame with a multicast destination address, the SGEC
applies the standard Ethernet CRC. function (see (6-1) to the first six bytes
containing the destination address, then uses the least significant nine bits
of the result, as a bit index into the table. If the indexed bit is set, the
frame is accepted. If it is cleared, the frame is rejected.

.....

Imperfect Fiitering setup frame buffer
This section describes how the SGEC interprets a setup frame buffer when
CSR6<HP> is set.

This filtering mode is called imperfect, because multicast frames not
addressed to this station may slip through, but it will still cut down on the
number of frames the host will be presented with.
The format for the hash table and the physical address is shown below:

Figure 5-13 Imperfect Filtering setup frame format
31

.....'
I.
-

bit

+--------+-------+-------+-------+
I
HASH_FILTER_OO
I
I

HASH_FILTER_Ol

I
I

HASH_FILTER_14
HASH_FILTER_ls

I
I

1--------------------------------1
I
PHYSICAL ADDRESS
I<-- Physical/Multicast bit
Ixxxxxxxxxxxxxxxx I
I
l:xxxxxxxxxxxxxxxxxxxxxxxxxxxxl
lxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxl
lxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxl
lxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxl
lxxxxxxxxxxxxxxxxxxxxxxxxrmxxxl

lxxxxxxxxxxxxxxxxxxxxxxxxxxxxxl
lxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxl

lxxxx
I
lxxxxxxxxmxxxxxxxrmrml
I
I

txxxxxxxxxxxxxxxxxxxxxxxxxxl
IXXXXXXXXXXXXXXXXXXXXXX:U:XlCXXXXXX I
lxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxl

+--------+-------+-------+-------+
xxxxxx • don't care

Bits are sequentially numbered from right to left and down the table. For
example, ifCRC(destination address)<8:0> - 33, the SGEC will examine
bit 11 in the second longword.

Example 5-2 illustrates an Imperfect Filtering Setup frame buffer and
Example 5-3 shows a C program to compute the hash bucket heads and
create the resultant Setup frame buffer.

n
.

5-26

Programming

Example 5-2

Imperfect fUtering buffer

Ethernet addresses to be filtered:

2s-oo-2s-oo-21-oo

A3-C5-62-3F-25-87
D9-C2-C0-99-0B-82

7D-48-4D-FD-CC-OA
E7-Cl-96-36-89-DD
61-CC-28-55-D3-C7
6B-46-0A-55-2D-7E
~

AS-12-34-35-76-08

Setup frame buffer:
00000000
10000000
00000000
00000000
00000000
40000000
00000080
00100000
00000000
10000000
00000000
00000000
00000000
00010000
00000000
00400000

353412AB
00000876

D Ethernet multicast addresses written according to the DEC STD 134
specification for address display.
~

An Ethernet physical address.

The first part of an Imperfect filter Setup frame buffer with set bits for
the Omulticast addresses.

m The second part of the buffer with the f.l physical address.

5-27

Programming

Example 5-3 Imperfect filtering Setup frame buffer creation C
program
tinclude <:stdio>
unsigned int imperfect_setup_frame[128/4],
/* bytes
"'/
address [ 2],
crc[33];
/* CRC residue vector
*/

/* The setup buffer - 128

main()
{

int i, hash;
I*

*/
/* This program accepts 48 bits Ethernet addresses and builds a Setup frame
/* buffer for imperfect filtering.
*/
/*
*/
/* Addresses must be entered in hexadecimal. The multicast bit is the least
/* significant bit of the least significant digit of the first 32 bits.
/* Non-multicast addresses are ignored.
*/
/*
*/
/* Input is terminated by keying CTRL/Z after which the program prints out
/* the buffer.
*/
I*
*/

main_ loop:
/* Prompt user for the Ethernet address

printf("\n\n Enter the first 32 bits (HEX) - ");
if (scanf("%x", &address[O]) == EOF)
{

printf("\n\n Imperfect Setup buffer printout\n")l
for (i=O; i <: 128/4; i++)
printf("%0SX\n•, imperfect_setup_frame[i]);
exit(l);
}

printf("\n Enter the remaining 16 bits (HEX) - ");
scanf("%x",&address[l]);
/* Ignore non multicast addresses

if {(address[O] & 1)
goto main_loop;

/* Compute the hash function

hash• address_crc(address[O],address[l]);
/* Set the appropriate bit in the Setup buffer

imperfect_setup_freJne[hash/32] =
imperfect_setup_frame[hash/32) I 1 <:<: hash%32;

goto main_loop;
int address_crc( unsigned int lsb32 , unsigned int msbl6)
{

int j,hash "' O;
/* Set CRC to all l's

for (j=O;
crc[j] = 1;

j < 33;

j++)

/* Compute the address CRC by running the CRC 48 steps

for (j=O; j <: 32; j++)
nextstate ( lsb32 & l<:<:j ? 1 : O);
for (j=O; j <: 16; j++)
nextstate(msbl6 & l<<j ? 1 : 0);
/* Extract 9 least significant bits from the CRC residue

Example 5-3 Cont'd. on next page

5-28

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Programming

n
n
[.

Example 5-3 (Cont.) Imperfect filtering Setup frame buffer creation
C program

;

for (j•247 j < 337 j++)
hash• hash<<l I crc[j);
return hash:
}

nextstate ( dat)
int dat;
{

int i,mean;
mean • crc[32] A dat;
for(i•32;i>•2;i--) crc[i]-crc[i-1];
crc[27] • crc[27] A mean;
crc[24] • crc[24] A mean;
crc[23] • crc[23] A mean;
crc[17] • crc[l7] A mean;
crc[13] • crc[13] A mean;
crc[l2] • crc[12] A mean;
crc[ll] • crc[ll] A mean;
crc[9] • crc[9] A mean;
crc[8] • crc[8] A mean;
crc[6] • crc[6] A mean;
crc[S] • crc[SJ A mean;
crc[3] • crc[3] A mean;
crc[2] • crc[2] A mean;
crc[l] •mean;

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!"':
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}

5.4

SGEC operation

5.4.1

Hardware and Software Reset
The SGEC responds to two types of reset commands: a hardware reset
through the RESET_L pin, and a software reset command triggered by
setting CSR6<RE>. In both cases, the SGEC aborts all ongoing processing
and starts the Reset sequence. The SGEC restarts and reinitializes all
internal states and registers. No internal states are retained, no descriptors are
owned and all the host visible registers are set to "O ", except where otherwise

noted.
Note: The SGBC does not explicitly disown any owned descriptors; so
descriptors Own bits might be left in a state indicating SGBC ownership .
The following table indicates the CSR fields which are not set to "O" after
reset:

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5-29

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Programming

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'

CSR4

Unpredictable

CSR5<DN>

CSR6<BL>

CSR7

Unpredictable

CSR9

RT • TT • 12500

If the self test completes successfully, the SGEC is ready to accept further
host commands. Both the Reception and Transmission processes are
placed in the STOPPED state.

[]

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r

Successive reset commands (either hardware or software) may be issued.
The only restriction is that SGEC CSRs should not be accessed during a
lµsecond period following the reset. Access during this period will result
in a CP-BUS timeout error. Access to SGEC CSRs during the self test are
permitted; however, only CSR5 reads should be performed.

5.4.2

Interrupts
Interrupts are generated as a result of various events. CSR5 contains all
the status bits which may cause an interrupt, ;>rovided CSR6< IE> is set.
The port driver must clear the interrupt bits (by writing a "l" to the bit
position), to enable further interrupts from the same source.

n
n

Interrupts are not queued, and if the interrupting event reoccurs before the
port driver has responded to it, no additional interrupts will be generated.
For example, CSR5<RI> indicates one or more frames were delivered to
host memory. The port driver should scan all descriptors, from its last
recorded position up to the first SGEC owned one.

j, I

An interrupt will only be generated once for simultaneous, multiple
interrupting events. It is the port driver responsibility to scan CSR5 for
the interrupt cause(s). The interrupt will not be regenerated, unless a new
interrupting event occurs after the host acknowledged the previous one, and
provided the port driver cleared the appropriate CSRS bit(s). For example,
CSR5<TI> and CSRS<RI> may both set, the host acknowledges the
interrupt and the port driver begins executing by reading CSR5. Now
CSRS<RU> sets. The port driver writes back its copy of CSR5, clearing
CSRS<TI> and CSR5<RI>. After the host IPL is lowered below the
SGEC level, another interrupt will be delivered with the CSRS<RU> bit
set.

Unpredictable

Passl info: Self test takes 30 milliseconds to complete.

Value

After the reset sequence completes, the SGEC executes the self test
procedure to do basic sanity checking. After the self test completes,
the SGEC sets the Initialization Done flag CSR5< ID>. The self test
completion status bits CSR5<SF> and CSR5<SS> indicate whether the
self test failed and the failure reason.

n
n
n

Field
CSR3

Should the port driver clear all CSRS set interrupt bits before the interrupt
has been acknowledged, the interrupt will be suppressed.

5-30

Programming

5.4.3

Startup procedure
A sequence of checks and commands must be performed by the port
driver to prepare the SGEC for operation.
1

Wait for the SGEC to complete its Initialization sequence by polling on
CSR5<ID> and CSR5<SF> (refer to Section 5.2.6 for details).

Examine CSRS<SF> to find out whether the SGEC passed its self test.
If it did not, it should be replaced (refer to Section 5.2.6 for details).

Write CSRO to establish system configuration dependent parameters
(refer to Section 5.2.2 for details).

If the port driver intends to use VAX virtual addresses, CSR7 must
be written to identify the System Page Table to the SGEC (refer to
Section 5.2.8 for details).

If the port driver wishes to change the default settings of the watchdog
timers, it must write to CSR9 (refer to Section 5.2.10 for details).

Port driver must create the transmit and receive descriptors lists, then
write to CSR3 and CSR4 to provide the SGEC with the starting address
of each list. The first descriptor on the transmit list will usually contain
a setup frame (refer to Section 5.2.5 for details).

Write CSR6 to set global operating parameters and start the
Transmission and Reception processes. The Reception and
Transmission processes enter the RUNNING state and attempt to
acquire descriptors from the respective descriptors lists and begin
processing incoming and outgoing frames (refer to Section 5.2.7 for
details). The Reception and Transmission processes are independent
of each other and can be started and stopped separately.

Caution: If address filtering (either perfect or imperfect) is desired, the
Reception process should only be started after the Setup frame has

been processed.
8

5.4.4

The port driver now waits for any SGEC interrupts. If either the
Reception or Transmission processes were SUSPENDED, the port
driver must issue the Poll Demand command after it has rectified the
suspension cause.

Reception process
'While in the RUNNING state, the Reception process polls the receive
descriptor list, attempting to acquire free descriptors. Incoming frames are
processed and placed in acquired descriptors' data buffers, while status
information is written to the descriptor RDESO words. The SGEC always
tries to acquire an extra descriptor in anticipation of incoming frames.
Descriptor acquisition is attempted under the follov.ri.ng conditions:
•

Im.mediately after being placed in the RUNNING state through setting
of CSR6<SR>.

•

In response to a Poll Demand command if the SGEC was in the
SUSPENDED state.

•

The SGEC begins writing frame data to a data buffer pointed to by the
current descriptor.

5-31

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Programming

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.

The last acquired descriptor chained (RDESl <CA> set) to another
descriptor.

•

A virtual translation error was encountered RDESO< TN> while the
SGEC was doing the address translation .

As incoming frames anive, the SGEC strips the preamble bits and stores
the frame data in the receive FIFO. Concurrently, it performs address
filtering according to CSR6 fields AF, HP and its internal filtering table.
If the frame fails the address filtering, it is ignored and purged from
the FIFO. Frames which are shorter than 64 bytes, due to collision or
premature termination are also ignored and purged from the FIFO, unless
CSR6<PB> is set.

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After 64 bytes have been received, the SGEC begins transferring the
frame data to the buffer pointed to by the current descriptor. If Data
Chaining is enabled (CSR6<DC> clear), the SGEC will write frame data
overflowing the current data buffer into successive buffer(s). The SGEC
sets the RDESO<FS> and RDESO<LS> in the first and last descriptors,
respectively, to delimit the frame. Descriptors are released (RDESO<OW>
bit cleared) as their data buffers fill up or the last segment of a frame has
been transferred to a buffer.

The SGEC sets RDESO<LS> and the RDESO status bits in the last
descriptor it releases for a frame. After the last descriptor of a frame is
released, the SGEC sets CSRS< RI>.

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This process is repeated until the SGEC encounters a descriptor flagged

a5 owned by the host. After filling up all previously acquired buffers,

the Reception sets CSRS<RU> and enters the SUSPENDED state. The
position in the receive list is retained. Any incoming frames while in
this state will cause the SGEC to increment the Missed Frames Counter
(CSRll<MFC>). To reinitiate processing the port driver must issue the
Poll Demand command.

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.

Note: The SGEC does not automatically poll the descriptors lists and the port
driver must explicitly issue a Poll Demand command after rectifying the
suspension cause.

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•

The following table summarizes the Reception process state transitions and
resulting actions:
Table 5-19 Reception process state transitions
From state

Event

To state

Action

STOPPED

Start Reception command

RUNNING

Receive polling begins from last list position
or from the the list head if this is the first
Start command issued, or if the receive
descriptor list address (CSR3) was modified
by the port driver.

RUNNING

SGEC attempts acquisition
of a descriptor owned by the
host

SUSPENDED

CSR5< RU> is set when the last acquired
descriptor buffer is consumed. Position in
list retained.

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5-32

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Programming

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Table 5-19 (Cont.) Reception process state transitions
From state

Event

To state

Action

RUNNING

Stop Reception command

STOPPED

M
lj

Reception process is STOPPED after
the current frame, if any, is completely
transferred to data buffer(s). Position in list
retained.

RUNNING

Memory or host bus parity
error encountered

STOPPED

Reception is cut off and CSR5<ME> is set.

RUNNING

Reset command

STOPPED

Reception is cut off.

SUSPENDED

Poll Demand command

RUNNING

Receive polling resumes from last list
position or from the list head if CSR3 was
modified by the port driver.

SUSPENDED

Stop Reception command

STOPPED

None.

SUSPENDED

Reset command

STOPPED

None.

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5.4.5

Transmission process
While in the RUNNING state, the Transmission process polls the transmit
descriptor list for any frames to transmit. Frames are built and transmitted
on the Ethernet wire. Upon completing frame transmission (or giving
up), status information is written to the TDESO words. Once polling
starts, it continues (m sequential or descriptor chained order) until the
SGEC encounters a descriptor flagged as owned by the host, or an
error condition. At this point, the Transmission process is placed in
the SUSPENDED state and CSR5<TI> is set.
CSR5<TI> will also be set after completing transmission of a frame which
has TDESl<IC> set in its last descriptor. In this case, the Transmission
process remains in the RUNNING state.
Frames may be data chained and span several buffers. Frames must
be delimited by TDES1 < FS > and TDESl <LS> in the first and last
descriptors, respectively, containing the frame. While in the RUNNING
state, as the Transmission process starts, it first expects a descriptor with
TDES1<FS> set. Frame data transfer from the host buffer to the internal
FIFO is initiated. Concurrently, if the current frame had TDES1 <LS>
clear, the Transmission process attempts to acquire the next descriptor,
expecting TDES1<FS> and TDESl<LS> to be clear indicating an
intermediary buffer, or TDESl<LS> to be set, indicating the end of the
frame. After the last buffer of the frame has been transmitted, the SGEC
writes back final status information to the TDESO word of the descriptor
having TDESl<LS> set, optionally sets CSR5<TI> if TDESl<IC> was
set, and repeats the process with the next descriptor(s). Actual frame
transmission begins after at least 72 bytes have been transferred to the
internal FIFO, or a full frame is contained in the FIFO. Descriptors are
released (TDESO<OW> bit cleared) as soon as the SGEC is through
processing a descriptor.
Transmit polling suspends under the following conditions:
•

the SGEC reaches a descriptor with TDESO<OW> clear. To resume,
the port driver must give descriptor ownership to the SGEC and issue
a Poll Demand command.

5-33

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Programming

•

The TDESl <PS> and TDES1 <LS> are incorrectly paired or out of
order. TDESO<LE> will be set.

•

A frame transmission is given up due to a locally induced error. The
appropriate TDESO bit is set.

The Transmission process enters the SUSPENDED state and sets
CSRS<TI>. Status information is written to the TDESO word of the
descriptor causing the suspension. The position in the transmit list, in all
of the above cases, is retained. The retained position is that of the descriptor

following the last descriptor closed (set to host ownership) by the SGEC.

Note: The SGEC does not automatically poll the descriptors lists and the port
driver must explicitly issue a Poll Demand command after rectifying the
suspension cause.

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The following table summarizes the Transmission process state transitions:

Table 5-20 Transmission process state transitions

From atete

Event

To state

Action

STOPPED

Start Transmission
command

RUNNING

Transmit polling begins from the last list
position or from the head of the list if this
is the first Start command issued, or if the
transmit descriptor list address (CSR4) was
modified by the port driver.

RUNNING

SGEC attempts acquisition
of a descriptor owned by the
host

SUSPENDED

CSR5<TI> is set. Position in list retained.

RUNNING

Out of order delimiting
flag (TDESO<FS> or
TDESO<LS>) encountered.

SUSPENDED

TDESO<LE> and CSR5<TI> are set.
Position in list retained.

RUNNING

Frame transmission aborts
due to a locally induced
error (refer to Table 5-14 for
details).

SUSPENDED

Appropriate TDESO and CSR5<TI> bits are
set. Position in list retained.

RUNNING

Stop Transmission
command

STOPPED

Transmission process is STOPPED after the
current frame, if any, is transmitted. Position
in list retained.

RUNNING

Transmit watchdog expires

STOPPED

Transmission is cut off and CSR5<TW> is
set. Position in list retained.

RUNNING

Memory or host bus parity
error encountered

STOPPED

Transmission is cut off and CSR5<ME> is
set.

RUNNING

Reset command

STOPPED

Transmission is cut off.

SUSPENDED

Poll Demand command

RUNNING

Transmit polling resumes from last list
position or from the list head if CSR4 was
modified by the port driver.

SUSPENDED

Stop Transmission
command

STOPPED

None.

SUSPENDED

Reset command

STOPPED

None.

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5-34

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Programming

5.4.6

Loopback operations
The SGEC supports two loopback modes:
•

This mode is generally used to verify correct operations of the SGEC
internal logic. While in this mode, the SGEC will take frames from the
transmit list and loop them back, internally, to the receive list. The
SGEC is disengaged from the Ethernet wire while in this mode.

•

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Externalloopback
This mode is generally used to verify correct operations up to the
Ethernet cable. While in this mode, the SGEC will take frames from
the transmit list and transmit them on the Ethernet wire. Concurrently,
the SGEC listens to its own transmissions and places incoming frames
in the receive list.

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r

Internal loopback

Note: Caution should be exercised in this mode as transmitted frames
are placed on the Ethernet wire. Furthermore, the SGBC does not
check the origin of any incoming frames, consequently , frames not
necessarily originating from the SGBC might make it to the receive
buffers.
In either of these modes, all the address filtering and validity checking
rules apply. The port driver needs to take the following actions:
1

Place the Reception and Transmission processes in the STOPPED state.
The port driver must wait for any previously scheduled frame activity
to cease. This is done by polling the TS and RS fields in CSRS.

Write to CSR6< OM> according to the desired loopback mode.

Prepare appropriate transmit and receive descriptors lists in host
memory. These may follow the existing lists at the point of suspension,
or may be new lists which will have to be identified to the SGEC by
appropriately writing CSR3 and CSR4.

Place the Transmission and Reception processes in the RUNNING
state through Start commands.

Respond and process any SGEC interrupts, as in normal processing.

To restore normal operations, the port driver must execute above step 11,
then write the OM field in CSR6 with "00".
Passl restriction: Loopback frames are limited to 64 bytes.

5-35

Programming

n 5.4.7

DNA CSMA/CD counters and events support

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Table 5-21

This section describes the SGEC features that support the port driver in
implementing and reporting the specified counters and events.

CSMA/CD counters

Counter

SOEC feeture

Seconds since last zeroed

No support.

Octets received

Port driver must add up the RDESO<FL> fields of all successfully received
frames.

Octets sent

Port driver must add up the TDES2<BS> fields of all successfully transmitted
buffers.

Frames received

Port driver must count the successfully received frames in the receive
descriptors list.

Frames sent

Port driver must count the successfully transmitted frames in the transmit
descriptors list.

Multicast octets received

Port driver must add up the RDESO< FL> fields of all successfully received
frames with multicast address destinations.

Multicast frames received

Port driver must count the successfully received frames with multicast address
destinations.

Frames sent, initially
deferred

Port driver must count the successfully transmitted frames with TDESO<DE>

Frames sent, single collision

Port driver must count the successfully transmitted frames with TDESO<CC>
equal to 1.

Frames sent, multiple
collisions

Port driver must count the successfully transmitted frames with TDESO<CC>
greater than 1.

Send failures

Port driver must count the transmit descriptors having TDESO<ES> set. Other
TDESO bits indicate the specific error with the following exceptions:

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set.

•

Remote Failure to Defer error is flagged as a late collision - TDESO<LC>.

•

Frame Too Long is not reported by the SGEC.

Collision detect check failed

Port driver must count the transmit descriptors having TDESO< HF> set.

Receive failures

Port driver must count the receive descriptors having RDESO< ES> set. Other
RDESO bits indicate the specific error.

Unrecognized frame
destination

No support.

Data overrun

Port driver must count the receive descriptors having RDESO< OF> set.

System buffer unavailable

CSR11 <MFC> (refer to Table 5-9).

User buffer unavailable

Not applicable.

CSMA/CD specified events can be reported by the port driver based
on the above table. The Initialization Failed event is reported through
CSRS<SF>.

5-36

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n 6
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6.1

Serial Interface

Basic Serial Operation
The SGEC support the full DEC STD 134B frame encapsulation and MAC.
It will function in a send and receive half duplex mode system. The SGEC
will function in either transmit or receive mode at any instant in time,
except for when it is in the loopback modes which operate in full duplex.
Before transmission the SGEC checks that there is no contention for the
network bus. In addition to listening for a clear line before transmitting,
the SGEC handles collisions in a predetermined way. Should two
nodes attempt to transmit at the same time, the signals will collide
and the data on the line will be garbled. When transmitting the SGEC
listens while transmitting and detect the collision. H present, the SGEC
continues to transmit for a predetermined length of time to •Jam" the
network, insuring that all nodes have recognized the collision. The
SGEC then delay transmission a random amount of time according to
the "truncated binary backoff"' algorithm implemented in the SGEC, before
attempting to transmit again. This minimizes the possibility of collision on
retransmission.

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Note: All frequency and timing information in this chapter, are is for lOMbit/sec
serial operation, the bit time equivalent will be given in parenthesis.

6.1.1

Frame Format
The SGEC transmits or receive information in frames. The SGEC
recognizes and transmit DEC STD 134B frames .

.
.
.

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6.1.1.1

Ethernet Format Types
Ethernet standards now have three main standard documents, which
slightly differ from each other. In this chapter Ethernet will be used as
a generic name for the type of network. The specific standard which
will be referred is the DEC STD 134B Document. This document is
the DEC merge of the three old Ethernet standards. The old Three
company Ethernet STD, the DEC STD 134A and the IEEE/802.3 will not be
referenced at all.

A DEC STD 134B frame consists of a preamble, an SFD, two address
fields, a type/length field, a data field, and a frame check sequence (PCS).
Each field has a specific format which is described below. A DEC STD
134B frame has a minimum length of 64 bytes and a maximum length of
1518 bytes exclusive of the preamble.
The IEEE/802.3 frame is generally the same as the DEC STD 134B frame.
They are different in the type/length field:
1

The IEEE/802.3 has a frame length field with valid data length of 1 to
1500 bytes, the DEC STD 134B recognize values which are greater than
1500 and interpret them as type fields. No type fields smaller than
1500 are allowed in the DEC STD 134B
6-1

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Serial Interface

The DEC STD 134B frame format is shown below:
Figure 6-1

DEC STD 1348 Frame Format

+-----------+-----+---------+---------+-------+-----------+---------+
I
I
I
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I
I
I
I
+-----------+-----+---------+---------+-------+-----------+---------+
I
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I

Preamble

rI.:,

I
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I
I
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I

I
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I

Source
Address

Destination
Address

SFD

<6>

I
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I

Data
(46-1500)

FCS/CRC
(4)

Type/Length
( 2)

(6)

(1)

Note: The field length in bytes is shown in parentheses.
6.1.1.2

Detailed frame format
Preamble: The preamble is a 7 byte field consisting of 56 alternating "l"
and "0" beginning with a "1 ".

SFD - Start Frame Delimiter: The SFD is a 1 byte field consisting of 6
alternating "1" and "O" beginning with a "1 ". and terminated by a "11"
This field is identical for the DEC STD 134B and IEEE/802.3 frame format.

Destination Address: The Destination Address is a 6-byte field containing
either a specific station address, the broadcast address, or a multicast
(logical) address to which this frame is directed.

This field is identical for the DEC STD 134B and IEEE/802.3 frame format.

Source Address: The Source Address is a 6-byte field containing the
specific station address from which this frame originated.

This field is identical for the DEC STD 134B and IEEE/802.3 frame format.

Length!Type field: This field consists of two bytes. For DEC STD 134B
frames this field is interpreted as length field if smaller than 1500. As a
length field this quantity is the number of data bytes in the frame.
H this field is greater than 1500 it is interpreted as a type field. As a type
field this field define the type of Protocof of the frame.

n
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'

For IEEE/802.3 frames this field is the length field defining the data length
in bytes with values from 1 to 1500.
Data Field: The Data field consists of 46 to 1500 bytes of information which
are fully transparent in the sense that any arbitrary sequence of bytes may
occur.
The DEC STD 134B format allows a shorter data field which is specified by
the length field. Padding has to be added, upon transmit, to fill the data
field up to 46 bytes.
Frame Check Sequence: The Frame Check Sequence (PCS) field is a
32-bit cyclic redundancy check (CRQ value computed as a function of
the Destination Address Field, Source Address Field, Type Field, and
Data Field. The FCS is appended to each transmitted frame, and used at
reception to determine if the received frame is valid.
6-2

Serial Interface

The CRC polynomial, as specified in the DEC STD 134B specification, is:
FOS(X) = x32 + x26 + x23 + x22 + x16 + x12 + xn+

(6-1)

x 10 +x8 + x 7 +x5 +x4 +x2 +x+1
This field is identical for the DEC STD 134B and IEEE/802.3 frame format.

6.1.2

Ethernet Reception Addressing
The SGEC may be setup to recognize any one of the Ethernet receive
address groups described below. Each group is separate and distinct from
the other groups.
1

Fourteen Address Perfect Filtering
The SGEC provides support for the perfect filtering of up to 14 Ethernet
physical or multicast addresses. Any mix of addresses may be used
for this perfect filter function of the SGEC. The fourteen addresses are
issued in setup frames to the SGEC.

One Physical Address, Unlimited Multicast Addresses Imperfect
Filtering.
The SGEC provides support for one single physical address to be
perfectly filtered with an unlimited number of multicast addresses to
be imperfectly filtered. This case supports the needs of applications
which wish one single physical address to be filtered as the station
address, but also need to enable reception of more than 14 multicast
addresses, yet not suffer the overhead of using pass-all-multicast mode.
The single Physical address, for perfect filtering, and a 512 bit mask, for
imperfect filtering using a hash algorithm are issued in a setup frame to
the SGEC. Upon hash hits, the SGEC delivers the received frame.

Promiscuous Ethernet Reception
The SGEC provides support for reception of all frames on the network
regardless of their destination. This function is controlled by a CSR bit.
Use of this group is typically for network monitoring.

Group 1 (above) and Reception of All Multicast Ethernet Addresses
This group augments receive address group 1 above with the addition
of receiving all frames on the Ethernet with a Multicast Address.

6-3

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Serial Interface

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t:

6.1.3

Collision Detection and Implementation
The Ethernet CSMA/CD network access algorithm is completely
implemented within the SGEC. In addition to listening for a clear line
before transmitting, the SGEC will handle collisions in a predetermined
way as defined by the standard. Should two transmitters attempt to seize
the line at the same time, they will collide and the data on the fine will be
garbled. When transmitting the SGEC will listen while it transmits, detect
the collision, and then continue to transmit for a predetermined length of
time to "jam" the network and ensure that all nodes have recognized the
collision. The transmitting SGEC will then delay a random amount of time
according to the Ethernet "truncated binary backoff" algorithm in order
that the colliding nodes do not try to repeatedly access the network at the
same time. Up to 16 attempts to access the network are made by the SGEC
before reporting back an error due to excessive collisions.

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6.1.4

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Clock Generator
The SGEC serial clocking is derived from an external clock source. Use of
an external clock enables varying the serial clock frequency independetly
of the system clock and thereby vary the serial line speeds. The supported
range of line speeds is from 1 Mhz to 10 Mhz.

6.1.5

Watchdog timers
The SGEC contains two separately programmable watchdog timers for
receive and transmit. These are 16 bits counters capable of counting for up
to 100ms on lOMbps networks.

6.1.6

Transmit Mode
In the transmit mode, the SGEC initiates a DMA cycle to access data from
a transmit buffer. It prefaces the data with a preamble and SFD pattern,
and calculates and appends a 32-bit CRC, if enabled.

After a frame is assembled the SGEC waits for the internal Transmite
machine to allow transmission on the network, then it serializes the data
and output it to the external SIA.

6.1.7

Receive Mode
In the Receive mode the decoded data and clock are fed to the SGEC
from an external SIA. The data is deserialized by the receive machine and
fed into the internal FIFO. As the data is received the address is checked
by the SGEC and a CRC is calculated and then compared to the CRC
checksum at the end of the frame. If the calculated CRC does not agree
with the Frame CRC, an error bit is set in the receive descriptor. The
host processor is notified of all received frames, including those with CRC
errors or exccesive dribbling errors. Runt frames are not delivered to the
host unless the SGEC is programmed to do so.

•1 J

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6-4

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Serial Interface

,.,

r1
6.2

Detailed Transmission Operation
This section will describe the detailed transmission operation as supported
by the SGEC. The specific control regi.Ster definitions, setup frame
definitions, and mechanics for host processor software to manipulate
the transmit list (i.e. descriptors and buffers) can be found in Chapter 5,
Programming.
·
·

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6.2.1

Transmission Initiation
The host CPU initiates a transmission by storing the entire information
content of the frame to be transmitted in one or more buffers in memory.
The host processor software prepares a companion transmit descriptor,
also in host memory, for the transmit buffer and then signals the SGEC to
take it. Once the SGEC has been notified of this transmit list, the SGEC
starts to move the data bytes from the host memory to the internal transmit
FIFO.

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When the Transmit FIFO has adequately filled or when there is a full frame
buffered in the transmit FIFO, the SGEC begins to encapsulate the frame.
This transmit encapsulation is performed by the Transmit state machine
which delays the actual transmission of the data onto the network until the
network has been idle for the minimum IPG time (9.6µs).

6.2.2

Frame Encapsulation
The transmit data stream consists of the Preamble, four information fields,
and the CRC which is computed in real time by the SGEC chip and
automatically appended to the frame at the end of the serial data, if
enabled.

The preamble and CRC encapsulation supports DEC STD 134B frame
format.
For an outgoing frame the Destination Address, Source Address,
Type/Length Field and Data Field are prepared, by the host processor,
in the bulfer memory prior to initiating transmission by the host CPU. The
SGEC chip encapsulates these fields into an Ethernet frame by inserting
a preamble before these information fields and appends padding and
optionally a CRC after the information fields .

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6.2.3

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Initial Deferral
The SGEC device constantly monitors the line and is rrepared to initiate a
transmission any time the host CPU request it. Actua transmission of the
data onto the network will only occur if the network has been idle for 9.6µs
IPG time and any backoff time requirements have been satisfied.
The IPG time is divided into two parts, IPSl and IPS2. They are equal
respectively to 6.()µs and 3.6µs. In the first part of the IPG, the IPSl time,
the SGEC will monitor the network for idle condition. If carrier will be
sensed on the serial line, during this time, the SGEC will deffer and wait
until the line will be idle again to restart the IPSl time count. In the second
part of the IPG, the IPS2 time, the SGEC will continue to count the time
even though a carrier will be sensed on the network, and will thus force

6-5

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Serial Interface

"'J

n
n 6.2.4

collision on the network. This is done to assure fairness in the access to
the serial line between all the network stations.

Collision
When concurrent transmissions from two or more Ethernet nodes occur
(collision), the SGEC chip halts the transmission of the data bytes in the
Transmit FIFO and transmits a Jam pattern consisting of AAAAAAAA hex .
At the end of the Jam transmission, the SGEC chip begins the Backoff wait
period.

r
.

Scheduling of retransmission is determined by a controlled randomization
process called Truncated Binary Exponential Backoff. The delay is an
integer multiple of slot times. The number of slot times to delay before
the nth retransmission attempt is chosen as a uniformly distributed random
integer r in the range:
OSr < 2k

r
r

where k - min (n, N) and N - 10
When 16 attempts have been made at transmission and all have been
terminated due to collision, the SGEC sets an error status bit and issues an
interrupt to the host, if enabled.
NOTE: The jam pattern is a fixed pattern which is not compared with the
actual frame CRC. This may cause at a very low probability, a jam pattern
which is equal to the CRC.

6.2.5

Watchdog Timer
This watchdog timer will cut out transmission after a programmable delay.
This provides a checking mechanism to prevent babbling.

The value used for the time delay for the watchdog timer is programmable,
thus providing a mechanism for the host processor to disable or set the
timer. The timer starts counting at the beginning of each transmission. If
the last bit of the frame is transmitted before the timer expires or there is
a collision, the timer is reset and ready for the next transmission. If the
timer expires before the transmission ends, transmission is aborted. The
watchdog timer can be programmed to count intervals between 1.(¥ts and
100 milliseconds in increments of 1.6 microseconds. A default value of
20ms is used for Ethernet/IEEE 802.3 networks.

"''

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n 6.2.6
n

Terminating Transmission
Transmission terminates under the following conditions:

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6-6

,...
l

Normal: The frame has been transmitted successfully. When the last
byte is serialized, the pad and CRC are optionally appended and
transmitted, thus concluding frame transmission.

Underflow: Transmit data is not ready when needed for transmission.
Underflow status bit is set.

Excessive Collisions: If a collision occurs for the 15th consecutive time,
the Excessive Collisions status bit is set.

Serial Interface

Watchdog timer Expired: If the timer expire while transmission is still
ongoing than the programmed interval, transmission will be cut off,
and a CSR bit will be set.

Memory error: This is a generic error indicating either a host bus
timeout or a host memory error. A CSR bit is set.

Descriptor error: This is a generic error indicating any problem with
the host descriptors list. It may be a translation error, a length error or
non proper descriptor control bits.

Late collision: If a collision occurs past the collision window,
transmission is cut off and a Late Collision bit will be set.

At the completion of every frame transmission, status information about
the frame, is written into the Transmit descriptor. In an event of an error
concerning the operation of the transmite machine itself, status information
will also be written in CSR5.

6.2.7
~

6.3

Transmit parameters values
1

Defer time - IPSl + IPS2 - 96 Bit Time, 9.6µs for 10Mhz serial rate.

IPS1 - 60 Bit Time, 6.0µs for 10Mhz serial rate.

IPS2 - 36 Bit Time, 3.6µs for 10Mhz serial rate.

Slot time interval - 512 Bit Time, 51.2.µs for 10Mhz serial rate.

Attempts limit - 16.

Backoff limit - 10.

Watch dog timer, programmable, units: multiples of 1.28µs, default
16ms, range 1.2.µs - 80,000µs.

Append CRC on frame transmission, programmable, (yes or no).

Detailed Receiving Operation
This section will describe the detailed reception operation as supported by
the SGEC. The specific control register definitions, setup frame definitions,
and mechanics for host processor software to manipulate the receive list
(i.e. descriptors and buffers) can be found in a chapter on programming.

6.3.1

Initiating Reception
The SGEC continuously monitors the network when reception is enabled
(See CSR definitions). When activity is recognized by a preamble being
detected on the Receive data lines, the SGEC synchronizes itself to the
incoming data stream during the preamble, waits for the SFD, and then
examines the destination address field of the frame. Depending on the
address match mode specified, the SGEC will either recognize the frame
as being addressed to itself, or abort the frame reception.

6-7

Serial Interface

6.3.2

Preamble Processing
The preamble as defined by the DEC STD 134B is up to 64 bits (8 bytes)
long. The SGEC allow any arbitrary preamble length, it expects at least 6
preamble bits before looking for the "11" end of preamble indicator. H
the SGEC chip receives a "00" before receiving the "11" in the preamble,
reception is aborted. The frame is not received, and the SGEC waits until
the carrier drops and rises again, then begins monitoring the network for a
new preamble sequence.

6.3.3

Address Matching
Ethernet addresses consist of two 6-byte fields, one field for the source
address and one for the destination address. The first bit of the destination
address signifies whether it is a physical address or a multicast/broadcast
address.
I First Eli t I

Address

---------------------------------------------------0
I Station Address (Physical)
I
1

I Multicast/Broadcast Address (logical)J

, the SGEC will filter the frame based on the group of Ethernet Receive
Address filtering that has been enabled.
If the frame address passes the filter, then the SGEC will remove the

Preamble and deliver the frame to host processor memory.
If, however, the address does not pass the filter, then as soon as the
mismatch is recognized the SGEC will terminate reception. In this case, no

data is sent to the host memory nor is any receive buffer consumed.
In addition to the four groups of Ethernet Receive Address filtering, an

SGEC CSR permits the reception to be explicitly disabled or enabled.

6.3.4

Frame decapsulation
The SGEC checks the CRC bytes of all received frames before releasing
the frame to the host processor. CRC (optional) removal is performed for
both Ethernet and IEEE 802.3 frames.
Optionally, the SGEC will strip padding off IEEE 802.3 formatted frames.

6.3.5

Terminating Reception
Reception of a specific frame is terminated when any of the following
conditions occur:

6-8

Normal Termination: The carrier sense line goes inactive, this indicates
that traffic is no longer present on the Ethernet cable.

Overflow: The receive DMA for some reason is not able to empty the
Receive FIFO into host processor memory as rapidly as it is filled, and
an error occurs as frame data is lost. Overflow status bit will be set.

Serial lnterf ace

6.3.6

Watchdog timer Expired: If the timer expire reception will be cut off
and a CSR bit will be set.

Collision: Either a normal or a late collision occurred. In the latter
case, Late Collision status bit will be set.

Memory error: An error has occurred on either the host bus or in the
host memory. A CSR bit will be set.

Descriptor error: An error has occurred on the definition of the
descriptor for reception.

Frame Reception Conditions
Upon terminating reception, the SGEC will determine the status of the
received frame and load it into the Receive Status word in the buffer
descriptor. An interrupt will be issued if enabled. The SGEC may report
the following conditions at the end of frame reception:
1

Overflow: The SGEC receive FIFO overflowed.

CRC Error: The 32-bit CRC transmitted with the frame did not match
that calculated upon reception. The CRC check is always done and is
independent of any other errors.

Dribbling bits Error: This indicates the frame did not end on a byte
boundary. The SGEC signals dribbling bits error only if it detects more
than two dribbling bits. Only whole bytes are run through the CRC
check. This means that although up to seven dribbling bits may have
occurred, framing error signaled, the frame might nevertheless have
been correctly received.

Frame Too Short (Runt frame): A frame containing less than 64 bytes
of information was received (including CRQ. Reception of such runt
frames is optionally selectable. The SGEC defaults to inhibit reception
of runts.

Frame Too Long : A frame containing more than 1500 bytes of
information was received Reception of such long frames is completed
with an error indication.

Late collision Error: A frame collision occurred after 64 bytes of
information were received. Reception of such frames is completed , an
error bit will be set on the descriptor.

Descriptor error: An error was found in one of the receive descriptors,
which disabled the proper reception of an incoming frame.

6-9

Serial Interface

6.3.7

Frame reception programmable quantities

6-10

•

Enable/Disable reception of runt frames.

•

Receive Address Filtering :

Fourteen Addresses Perfect Filtering.

One Physical Address Perfectly Filtered with 512 bits Mask for
Imperfect Hash Filter for Multicast Addresses.

Promiscuous mode.

Fourteen Addresses Perfect and All Multicast Addresses.

•

Watchdog timer count.

•

Enable/disable CRC stripping on reception.

•

Enable/disable pad stripping off IEEE 802.3 formatted frames.

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The SGEC supports two levels of testing features.
The first level induds diagnostics features which may be activated without
taking the SGEC out of the system. They will need some different software
set up but will give more information on the chip without changing the
hardware set up.
The second level allows more thorough testing by switching the SGEC
to work in diagnostic mode. All those features will be described in this
chapter.

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Diagnostics and Testing

7.1

SGEC Operational mode diagnostics features.
Extensive on chip diagnostics is provided by the SGEC. Error in the self
test are recorded as flags in the CSRs and should be examined by the CPU
before starting operations.
This paragraph lists the summary of diagnostics features that the SGEC will

support in operation mode.

7 .1.1

SGEC internal Self test
The SGEC includes a self test which is performed after Reset, this test
checks some internal parts of the SGEC and after the test completion a
report is given in the Status register.
The following hardware blocks of the SGEC are tested in the self test and
their functionality is reported in CSRS.

r,..

The Internal ROM, RAM, Transmit FIFO, Receive FIFO and the Address
Recognition RAM. After testing those blocks the SGEC perform an internal
local Loopback test, to check the serial channel functionality.

7 .1.2

A Time Domain Reflectometer is incorporated into the SGEC to aid
locating faults in the Ethernet cable. Short and opens manifest themselves
in reflections which are sensed by the TOR.

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I

Time Domain Reflectometer

7 .1.3

SGEC Loopback modes
There are two SGEC Loopback modes, internal and external Loopback. In
all types of device Loopback supported by the SGEC it is the responsibility
of the host software to build the frame to transmit and to provide a receive
buffer for the looped data to be returned to the host processor.
The SGEC Loopback modes are described in Chapter 5.

7-1

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Diagnostics and Testing

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SGEC Diagnostic mode features.

7.2

This paragraph will list the functions that the SGEC will support in

diagnostic mode. Those functions will only be accessible after the TSM
pin was set to test mode, thus they mostly will be used for debugging and
production testing and less in on board diagnostics:

The following diagnostics features are available on the SGEC:

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7.2.1

Diagnostic CSR' s.

Serial access to all the SGEC internal registers via test pins.

The ability to load code patches to the internal quip via test pins.

Monitor mode.

Dump and load internal SGEC address space.

Diagnostic CSR's.
Four CSR' s are used for diagnostics purposes, their operation is as follow:
7 .2.1.1

Reserved register (CSR12)
This register is reserved for future diagnostics

7.2.1.2

Breakpoint Address Register (CSR13)
This register is virtual CSR. It contains the breakpoint address that will
cause the internal CPU to jump to a patch address.

Figure 7-1

CSR13 format

3 3 2 2 2 2 2 2 2 2 2 2 1 1 l 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 l 0

.-.-.-.-.-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·
CODE RESTART ADDRESS
I BRBAI<POINT ADDRESS
I CSR13
I
I
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
Table 7-1

CSR13 bits

Bit

Name

Access

Description

15:0

BPA

R/W

Breakpoint Address - Define the internal processor address
at which the program will halt and jump to the RAM loaded
code.

30:16

CAA

R/W

Code restart address - Define the first address in the
internal ROM that the Internal processor is supposed to
jump to after a breakpoint occurred.

R/W

Breakpoint enable.

Note: This register in conjunction with the Write address space diagnostics descriptors allow the testing
of software patches.

7-2

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Diagnostics and Testing

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7.2.1.3

Reserved Register (CSR14)
This register is reserved for future diagnostic purposes.

7.2.1.4

Diagnostic mode and status Register (CSR15)
This register is a phisical CSR. It contains the bits which will select the
internal test block operation mode.

Figure 7-2 CSR15 format

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r

3 3 2 2 2 2 2 2 2 2 2 2 l l l l l l l l l l
l 0 9 8 7 6 S 4 3 2 l 0 9 B7 6 S 4 3 2 l 0 9 8 7 6 S 4 3 2 l 0

.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-·-·-·
CSRlS
RESERVED BITS
!RESERVED BIT ILIDIOSLIAIMISISIII
I
IPISI
JDIOITITINI
I
10101
IDIOlllOITI
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

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1

Table 7-2 CSR15 bits
Bit

Neme

Access

Description

15:0

RES

R/W

Reserved bits - for future use, will erad as 1

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INT

R/W

Interrupt bit - This bit will set the internal level 14 interrupt.

STO

R/W

Status o bit - This bit is a general popose status bit which
may be set or reset by a external control. It may be used
for diagnostics programs control.

ST1

RIW

Status 1 bit - This bit is a general popose status bit which
may be set or reset by a external control. It may be used
for diagnostics programs control.

MON

R/W

Monitor bit - This bit will select the tests block mode of
operation. When set to one it will be in monitor mode and
when set to zero it will be in serial test mode.

ADB

R/W

Address data space - This bits will define the whether
the monitor function will apply to the address or data
space which will be avallable on the external test pins
BM_LJTEST <3:0>

22:21

QSL

R/W

Quad select bits - This bits will define the specific four bits
of the address or data space which will be available on the
external test pins BM_LJTEST <3:0>

DSQ

RIW

Disable Quip bit - This bit is used to disable the Quip
operation, for control purposes.

LPQ

R/W

Loopback Quip bit - This bit is used to put the Quip in
a loop on instruction status, in this mode the Quip will
indefinitly execute a specific instruction.

31:25

RES

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,...
I
I

7.2.2

Reserved - will read as 1

Serial access to the SGEC via test pins.
The four test pins may be used to load and read serial information from
the internal SGEC ADDRESS SPACE. The pins BM_LITEST<3:0> will be
allocated to test pins when TSM pin is set to 1. In this mode those pins
will work as a serial mechanism to load and read data from the SGEC
internal bus by bypassing the SGEC internal controller.
7-3

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Diagnostics and Testing

The following assignment IS valid :
BM_LITEST < 0 > - Serial test data in.
BM_LITEST< 1 > - Serial operation strobe signal.
BM_LITEST < 2 > - Serial load clock envelope signal.

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BM_LITEST < 3 > - Serial test data out.

This hardware block allows reading and writing to any internal register in
the following way:
Reading internal registers:

To perform this operation the required internal address is loaded serialy
into the serial address register and then the strobe pin is set to high for
one clock cycle. As a result the data on the specific address will be loaded
internally to the data register. Shifting the data 16 more bits will send this
data to the outside world.

Writing internal registers:

To perform this operation the required internal address and data is loaded
s~y into the serial address register and data register by a 31 cycle load
signal. then the strobe pin is set to high for one clock cycle. As a result
the data on data register will be loaded to the specific address listed on
the address register. The following figure will show the specific internal
organization.

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Figure 7-3 SGEC test loop hardware.
+-----+

+------------------+
+------------------+
!Serial Control Reql
!Serial Address Reql
!Test+->>----+
(l bit)
+-----+
(14 bits)
+--->>-----+
I o I
+------------------+
+-------+ •--------+
+-----+
I I

I I
v

Address Bus Drivers.
+-----+
+------------------+
I Test!
I
I
+--->>--+
I

+-----+

+-----+
+------------------+
!Test +---<<--+ Serial Data Reg +-----------------------------------+
I
I
I <16 bi ts>
I
I 3 I
+-------+ +--------+
+-----+
I I

rti

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'

I
I
I
+-------------------> To Device
I
Control Logic
I

+-----+
!Test I
I
+--->>--+
I 2 I
+------------------+
+-----+

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Control Block.

I I
v

Internal Data Bus I/O Lines.

Figure 7-3 Cont'd. on next page

7-4

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Diagnostics and Testing

Figure 7-3 (Cont.) SGEC test loop hardware.

7 .2.2.1

Serial Address Register
This register will store the serial loaded address. It will be a 14 bit shift

4 3 2 l 0 9 8 7 6 S 4 3 2 l'O

.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.
Address

Bits

,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

Table 7-3 Serial Address Register

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Bit

Name

Acc...

Description

14:0

Serial

lntemal address bits

7.2.2.2

Serial Control Register
This register will include the control bits. It will be a one bit control
register.

Figure 7-5 Serial control register
0

.-.-.-.

I CB I
I
I
,_,_,_,

CB • Control Bit.

Table 7-4 Serial control register

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Bit

Name

AcceN

Description

RWB

Serial

Read write bit , when 1 set to read when O set to write.

7.2.2.3

Serial Data Register
This register will be an internal data register latch. It will be a 16 bit input

output serial register.

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7-5

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Diagnostics and Testing

Figure 7-6 Serial Data Register

1 1 1 1 1 l
5 4 3 2 l 0 9 8 7 6 5 4 3 2 1 0

.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.
Data Bits

,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

Table 7-5 Serial Data register bits

7.2.3

Bit

Name

Access

Description

15:0

Serial

DATA bits - the internal SGEC data bits

Performing code Patches
Code patches can be done in the SGEC via two mechanism. The first is the
load address space, and the second is the serial test block load mechanism.

7.2.4

Monitoring of the internal Busses
7 .2.4.1
Monitoring of the Internal Processor address bus
The four test pins may be used to monitor the SGEC code sequence by getting on them the SGEC
address lines. This will be controlled by CSR15.
Figure 7-7 SGEC address monitor hardware.
+-----+

+------------+

I
AddreBB bus ( O, 4, 8, 12 )
+---------------------!

!Test+---<<--+

I o I

I
I

I
I
I
I
I

output

I
I
I

Address bus(l,5,9,13)
+---------------------!
BOX

Addresa

I
I
I
I

Address bus(2,6,10,IOPW_L)
+---------------------!

+-----+
MOX
I
Address bus(3,7,ll,[O])
+-----+
+---------------------!
!Test I
I
I
+---<<--+
I
I 3 I
+------------+
+-----+

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'

+-----+
+-----+
I Test!
I
+---<<--+

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.

+-----+
I
+-----+
I
!Test +---<<--+

7-6

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Diagnostics and Testing

7.2.4.2

Monitoring of the internal Processor Data bus

The four test pins may be used to monitor the SGEC internal data bus by getting on them the SGEC
internal data lines. This will be controlled by CSR15.
Figure 7-8 SGEC data bus monitor hardware.

+-----+
I
I

+------------+
I
I

Data bus(0,4,8,12)
+---------------------!

!Test+---<<--+

!""!
f ,,.·

I o I

+-----+
+-----+

I
I
I

Output

!Test +---<<--+

I
I

+-----+
+-----+

I
I
I
I
I

I Testl
I
+---<<--+
I 2 I

+-----+

BOX

Data

+-----+

7.2.5

Data bus(l,S,9,13)
+---------------------!

I
I
I
I
I

Data bus(2,7,10,14)
+---------------------!
MUX

+-----+
!Test I
I
+---<<--+

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I
I
I

I
Data bus(3,8,ll,1S)
+---------------------!

I
I

+------------+

Diagnostics frame
A diagnostics frame may be used in the SGEC to load and dump internal
address spaces. The Diagnostics frame is never transmitted over the
Ethernet, nor looped back to the receive list. The diagnostics frame must
be wholly contained in a single transmit buffer. There are two types of
Diagnostics frames:

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Diagnostics Dump Address space.

Diagnostics Read Address space.

A Diagnostics frame may be given to the SGEC while the Reception
process is in the RUNNING, SUSPENDED or STOPPED state, nor does
it affect the state of the Reception process. The only requirement for the
diagnostics frame to be processed, is that the Transmission process be
in the running state. The setup frame will be processed after the current
frame reception, if any, is completed. While the diagnostics frame is being
processed, the receiver logic will temporarily disengage from the Ethernet
wire. The diagnostics frame will be controlled by the following descriptor:
The diagnostic frames are only proceed when the SGEC Operation mode
is placed in Diagnostic mode CSR6< OM>•< 11 >.
A dump frame must never be placed inside a multi_buffer frame. H
its occurs, the Tx process stops the frame transmission and enters the
SUSPENDED state as for a descriptor error.

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7-7

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Diagnostics and Testing

Figure 7-9 Diagnostic frame descriptor format

3 3 2 2 2 2 2 2 2 2 2 2 l l l l l 1 l 1 l l
l 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 l 0 9 8 7 6 5 4 3 2 l

.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.

1w1 I
I
I
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,

1010 I

I DD!SO

ju ID Tl u
!WIST I
u
I
u
I DDESl
I,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
I I
101
I
I
I

I I
I I I
I DDES2
IUI
Dump size
IUIUI
Dump start address
I
,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
I u I
I u I DDES3
I,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,
I
Buffer Physical Address
I I
0 - SGEC writes aa "0"
u - Ignored by the SG!C on read, never written

Table 7-6 Diagnostic descriptor

Word

Bit

Name

DDESO

Description
Own bit - When set, indicates the descriptor is owned by
the SGEC. When cleared, indicates the descriptor is owned
by the host. The SGEC clears this bit upon completing
processing of the descriptor and its associated buffer.

DDES1

22:21

SGEC dump Type - Select the SGEC dump type:

Value

Meaning

ROM/RAM/Registers dump

Rx Flfo data dump

Tx Flfo data dump

DDES1

DDES2

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Read/Write Dump - When set (WAITE), the host data will be
download into the SGEC. When reset (READ), the SGEC
data will be dumped into the host diagnostic buffer.

29:28

Data type - For Diagnostic frames those bits should be 11

13:00

Dump start Address - The start address of the transfer
into/from the SGEC Internal memory.

30:16

Dump Size - The size, in word of the memory data transfer.

Note: The associated buffer must be equal or greater
than the dump size.If this is not the case, the
dump destination memory (host or SGEC) will
be corrupted.
DDES3

29:02

Diagnostic buffer Physical Address -

Note: Diagnostic buffer may be word aligned.

7-8

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Diagn~stics and Testing

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7.2.5.1

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Figure 7-10 Address Dump Diagnostics frame format

Words 03-02

+-------+------+------+-------+,

bit

Bits<3l:O> I _____________________________
Words 01-00
I

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1-----------------------------1
I
Words 05-04
I
1-----------------------------1

1-----------------------------1
I
Words 29-28
I
1-----------------------------1
I
words 31-30
I
!-----------------------------!

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Address Dump Diagnostics frame
This section describes how the SGEC will interpret a diagnostics frame
when a dump set up packet will be sent. The Dump buffer must be word
aligned. It will contain after the operation the data dumped from the
internal Address space. This can be used to dump the internal ROM, RAM
or any other internal register.

7.2.5.2

Address load Diagnostics frame
This section describes how the SGEC will interpret a diagnostics load
frame when it is sent to the chip.
The format for the load address space table is shown below:

Figure 7-11

Address Load Diagnostics frame format

bit

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Bits<31:0> +-------+------+------+-------+
I
Words 01-00
I
I1-----------------------------1
Words.03-02
I
1-----------------------------1
I
Words 05-04
I
1-----------------------------1

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Bits are sequentially numbered from right to left and down the table.

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'

~·

;

1-----------------------------1
I
Words 29-28
I
1-----------------------------1
I
words 31-30
I
1-----------------------------1

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8.1

System Configurations

The SGEC device can be integrated into a system in three main different
system configurations:
1

CVAX host bus system.

GffiDRA local bus system.

Other host bus system configuration.

CVAX host bus system
This configuration is the generic configuration for system based on the 32
bit Digital Miaoprocessor family. In this configuration the SGEC device
will reside directly on the CVAX CP-BUS.
This mode of operation can be divided into two sub modes which differ
slightly in their application space:

8.1.1

CVAX host bus with SGEC in synchronous mode.

CVAX host bus with SGEC in asynchronous mode.

CVAX host bus with SGEC in synchronous mode
This is the highest performance configuration. In this configuration the
SGEC will use the same Cl.KA and CLI<B signals as the CVAX, and will
work synchronously with the CVAX bus.

It will have a 32 bit multiplexed address and data bus and will be able to
do the VAX virtual memory address translation.
The command and status registers will be transferred between the SGEC
and the CVAX via a simple slave interface, while the data blocks will be
DMAed directly by the SGEC to main memory buffers.
No glue will be needed to connect the device to the CVAX CP-BUS.
To complete A network connection the system will need in addition to the
SGEC an SIA to drive the Transceiver cable and an External Tranceiver.

The following figure is a typical system connection scheme for this mode:

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8-1

System Configurations

Figure 8-1

Typical SGEC CVAX Host synchronous system configuration

+-------+
+------+I +------+
+-------+I
I
I I
I
I I
I CFPA I ICMCTL +---+ Main I I
I
I
I I
+---+
I I s sc I
I
I I
IMemoryl
I
I
+------+
+--+
+--+
+--+
+-+
+------+
+--+
+--+
jCVAXI
II
11 CDALBus
II
I
+--------+ +--------+ +-------------------+ +------+
I CPU +-----------+ +------------+ +---------------------+
I
I
I I
I I
+--+---+
+---+
+---+
+---+
+---+
I s

+-------+
I
I G
I
I
I CLKA,CLKB I B
I
+-----+-----------+ c
I CCLK I
+----+----+

+-------+

I
I

+----+----+
I
I
I

+---+-----+
I

+-------->>>TO DSSA Bus

+----+----+
I

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SIA

I
I SHAC
I
I

+-------------->>> TO LAN TRANSCEIVER.

8.1.2

CVAX host bus with SGEC in asynchronous mode
This mode main design goal is to allow for the SGEC to be connected to
CVAX at different frequencies either because of faster CVAX CPU chips or
the need to use bus buffers for the CVAX bus.

In this mode the SGEC will reside on the CVAX bus asynchronously using
a different clock.
In this mode the SGEC will be driven by a separate clock chip. As different
clock are used the SGEC will work asynchronously with the processor.

It will have a 32 bit multiplexed address and data bus and will be able to
do the VAX virtual memory address translation.

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The control and status registers will be transferred between the SGEC
and the CVAX via a simple slave interface, while the data blocks will be
DMAed directly by the SGEC to main memory buffers.
No glue will be needed to connect the device to the CVAX buffered pin
bus. An SSC device will be needed on the CP-Bus to syncronize the Rdy,
Err and Reset Signals.
To Complete a full network connection the system will need in addition to
the SGEC an SIA chip to drive the Tranceiver cable and a Transceiver.

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The following figure is a typical system connection scheme in this mode:

8-2

System Configurations

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Figure 8-2 Typical SGEC CVAX Host asynchronous system configuration

+-----+ +--------+
ICMCTL+--+ Memory I
I
+--+
I
I
I I
I +---+
+------+ +-+ +-+ +--------+ I D I
I
I
I I CDAL Pin Bus I A I
CDAL Buffered Bus.
I
+-----+ +----------------+ L +----------------------+
+------+ I CVAX +-----+ +-------+ +------+ +-----+ +------------+ +
I
+---+
I
I I
I I
I B I
I I
I I
ICCLK I
I
II
I I
I u I
II
I I
I
I +------+ +--+ +---+ +-+ +--+ I P I +---+ +---+ +---+ +---+
+------+
I
I I
I +---+ I s
I I
ICPPA 11ssc I
I G
I I sHAc
I
I I
I
I B
I
I
+--------+ +------+ +----+ c
I +-+
I
+---+-----+ I +--+------+
+--------!--------+
I
+--------+
I
I
I
I
I
I
I
+-»TO DSSI.
I CCLK +--------------+ +----+----+
I
I
I
I
+--------+
I SIA
I
+----+----+

r
n

+--->>> TO ~ TRANSCEIVER.

8.2

GHIDRA bus with SGEC In synchronous mode
This mode main design goal is to be used in high performance systems
like the RIGEL where buffering is needed between the system bus and the
peripherals.
In this configuration the SGEC will reside on the GHIDRA local bus.

Note: It is as811Dled that the GHIDRA is identical to the CMCTL, when viewed
from the 32 bits (CP-Bus) bus side.

t -,

In this mode the SGEC will use the same dock as the GHIDRA chip and
will work synchronously with the GHIDRA. It will be connected VIA the 32
bit multiplexed address and data bus.

The command and status registers will be transferred between the SGEC
and the RIGEL via the window capability of the GHIDRA chip while the
data blocks will be transferred by the SGEC via the GHIDRA chip to the
main memory buffers.
-

No glue will be needed to connect the device to the local GHIDRA CP-Bus.

n
n

To Complete a full network connection the system will need in addition to
the SGEC an SIA to drive the Tranceiver cable and a Transceiver.
The following figure shows the connection scheme:

n
rI

8-3

r
r

System Configurations

r
r

Figure 8-3 GHIDRA local bus configuration

+--------------+
RIGEL
I
I

+---------+ +------+
+------+
+----+
+-------+
I
I I
I
!RIGEL I
I !RIGEL Main Bus I Ri9el
I I Main I
I
+--------+ +---------------+
+---+
I
I CPU +-------------+ +----------+
+---+IMemory II
I
I
I I
I GHIDRA
+------+
+-----+
+----+I
I
I
I
I Ri9e1
+---+
+---+ +------+
FPA

r
r

I Secondary I
I Cache
I

+------------+

I I
I I
I +------------------+
+------+I +---------+
I
I
I I

+--+ +--+ +--+ +---+
I
I I

I SGl!!C I
I
+------+
I
I
I
+---+---+
I CCLK I
I
+------+
I
+------+

r
r

I SHAC
I

+--+-----+

+----+----+
I
I
I

SIA

+---->>>TO DSSI Bus

+----+----+
I
I

+---->>> TO LAN TRANSCl!!IVl!!R.

8.3

Other host bus configuration
The device may also be used for the 32 bit non Digital processor, such as
the Intel 80386, and the Motorola 68020, or with other Digital processors
not pin compatible to the CP-Bus, such as the µVAX chip.

In this configuration the SGEC will not reside directly on the Processor bus.
It will need external glue logic such as TrL multiplexei: and transceivers.
The control for these multiplexors and transceivers can be derived from the
SGEC's bus control signals.

In this mode the SGEC will need a clock chip to drive its timing and it will
work asynchronously with the processor.
It will have a 32 bit multiplexed address and data bus and will be used in
physical memory mode.
The control and status registers will be transferred between the SGEC and
the processor via slave memory transfers. Data blocks will be transferred
by the SGEC to main memory by the DMA channel.
The serial LAN connection will need an SIA and a Transceiver to complete
a fatwire Ethernet capability.
The following figure is a system connection scheme:

r
n
r
l

8-4

System Configurations

r
n

. Figure 8-4

.
.

Block Diagram. for 80386 System

+-------+
I FPA I

+-------+
I
I
I MBMORYI
I
I

I
I
I 80387 I

+------+
+-+I +---+
+--+I +--+
I 803861
I
I 32 Bit bus
I
+----------+ +-------------+ +-------+
I CPU +-----------------+ +----------------+
I
I
I I
+---+
+----+I
+------+
I TTL

Glue.

+----+ +---+
I I
+----+ +---+

M
fl

+-----+
I s
I
I
I
I G
I
ICCLK +-------------+
E
I
I
I
I c
I
+-----+
+----+-----+
I
+----+----+
I
I

SIA

+----+----+
I

+---->>> TO LAN TRANSCEIVER.

r
r
n
n

8.4

SGEC serial line configurations
This paragraph will show the various way in which the SGEC can be
connected to an Ethernet serial line. For all the three configurations the
SGEC will need an external SIA to drive the transceiver lines.
The serial line mode of operation can be divided into three sub modes
which differ slightly in their application space:
1

SGEC on lOBASES (fatwire) Ethernet line.

SGEC on 10BASE2 (DTE) line.

SGEC on twisted pair Ethernet line.

8.4.1

SGEC configuration on 10BASE5 (fatwlre) Ethernet line.
In this configuration the SGEC will be used on a full fatwire 2.SI<m Ethernet
network.

The SGEC will do part the data link Layer protocol for the serial LAN
connection and will need an external SIA to drive the full SOm Transceiver
cable. It will also need and a Transceiver to connect to the coax cable.
The following figure is a typical system connection scheme:

n
n
l

8-5

r
r
r

System Configurations

Figure 8-5 SGEC configuration on fatwlre Ethernet line.

LAN Cable

CVAX Bus

I I
+---------+
+---------+
+-+ +--+
I I
I S
I
I
I
TXCV Cable
I
I
I I
I G
+--------+ SIA
+-----------------+ TXCV I
I +--------+ E
+--------+
+-----------------+
I
I +--------+ c
I
I
I
I I
+---------+
+---------+
+--+ +-+
I I
I I
I I

r
r
r

I I
I I
I I

8.4.2

SGEC configuration on 10BASE2 DTE line.
In this configuration the SGEC will be used with an External SIA to drive
only a DTE Transceiver on the same board. This will allow working only
with up to 185m DTE cables.

The SGEC will do part of the Data link layer protocol and for the serial
LAN connection will need an external SIA and a DTE driver to drive the
DTE cable.

I ,

The following figure is a typical system connection scheme:
Figure 8-6 SGEC configuration on DTE line.

LAN CATV Cable

CVAX Bus

I I
I I

I I
+---------+
+-------+
+-------+
+-+ +--+
I I
I
s
I
I
I I DTE
I I
I
G
+-----+
s +---+LINE +--------+ T
I
I +--------+
E
+-----+
I
+---+DRIV. +--------+ BNC I
I +--------+
c
I
I A I I
I
I
I
I I
+---------+
+-------+
+-------+
+--+ +-+
I I
I I
I I

n
M
l;

n
n
n
n
.

8.4.3

SGEC configuration on twisted pair Ethernet line.
This is the lowest cost configuration in term of the serial line . In this
configuration the SGEC will need an external SIA and a twisted pairs line
driver to connect to the Network. This will allow working with DEC 10
MHZ twisted pairs or Starlan configuration.

The SGEC will do part of the data link layer protocol for the serial LAN
connection and will need an external SIA and line driver to drive the
twisted pair cable.

8-6

r
System Configurations

The following figure is a typical system connection scheme:
Figure 8-7 SGEC configuration on twisted pair Ethernet line.

CVAX Bus

I I
+---------+
+-------+
+-------+
I I
I
S
I
I
I I TWIST.I Twisted Pairs Cable
I I
I
G
+-----+ s +---+ PAIR +--------------------+
I +--------+
E
+-----+ I +---+ DRIV. +--------------------+
I +--------+
c
I
I A I I
I
I I
+---------+
+-------+
+-------+
I I

r
r
r

r
r
r
r
"

r
r
'

8-7

r
9

AC/DC Characteristics

9.1

Absolute Maximum Ratings
This table defines the maximum rating for the SGEC storage and
operation.

Table 9-1

r
l

No.

r
r

9.2

Parameter

Value

Storage Temperature Range

-55 C to +125 C

Operating Temperature Range

DC Supply Voltage Range

Input/Output voltage applied

O C to +125 C
-0.5 v to +7.0 v
-0.5 V to +7.0 V

Electrical Characteristics
This table shows the specified electrical characteristics for the SGEC.

Table 9-2

r•

r
rL

r
r
.

SGEC absolute maximum ratings

SGEC Electrical characteristics table

No.

Parameter

Value

Specified Temperature Range

0Cto+70C

Specified Supply Voltage Range

+4.50 V to +5.50 V

This table shows the specified electrical characteristics for the SGEC.

Table 9-3 SGEC Electrical characteristic table
Symbol

Paramter

Min

Vih

High level input voltage

2.0

Max

Units

0.8

v
v
loh - -400 uA

0.4

v
v
v

loh • -100 uA, CL= 100pF

10% VDD

lol • 1.0 mA, Cl • 100 pF

Tut condition

Vil

Low level input voltage

Voh

High level output voltage

Vol

Low level output voltage

Vihm

High level input voltage
(MOS)

Vilm

Low level input voltage
(MOS)

Iii

Input leakage current

-10

O<Vin<VDD

IOI

Output leakage current

-10

0< Vin<VDD

Ice

Active supply current

500

lout -

2.4
90%VDD

lol - 2.0 mA, CL • 1OOPf

o, Ta - Oc

9-1

r
I.

r
r
r
r
r
r
r

r
r
r

r
r
'

r
r
I;'

r
r
r
r
-

AC/DC Characteristics

Table 9-3 (Cont.) SGEC Electrical characteristic table
Symbol

Paramter

Min

Max

Units

Cin

Input capacitance

Cout

Output capacitance

Cio

Input/Output capacitance

Test condition

This table shows the specified electrical characteristics for the SGEC.

Table 9-4 SGEC Electrical Signal Summary

Signal Name
CDAL<31>
CDAL<30>
CDAL<29>
CDAL<28>
CDAL<27>
COAL<26>
CDAL<25>
CDAL<24>
COAL<23>
CDAL<22>
CDAL<21>
CDAL<20>
CDAL<19>
CDAL<18>
CDAL<17>
CDAL<16>
CDAL<15>
CDAL<14>
CDAL<13>
CDAL<12>
CDAL<11 >
CDAL<10>
CDAL<09>
CDAL<08>
CDAL<07>
CDAL<06>
CDAL<05>
CDAL<04>

9-2

Signal
Type

10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10

Pin
Num·
ber
Vlh

Vil

Voh

x
x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x
x
x

x
x

63
62
61
60
59
58
57
56
55

48
47
46
45
42

x
x
x
x
x

x
x
x
x
x
x

39
38
37
36
35
34

x
x

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

x
x
x
x

Applicable Teats
Vol
Iii
lol

x
x
x
x
x
x
x

x
x
x
x

x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x

x
x

x
x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x
x
x
x
x
x

x
x

x
x
x
x

x
x
x

x
x

x
x
x
x
x
x
x
x
x
x
x
x
x
x

AC/DC Characteristics

r
r
r
r
r
r
r
r
r

Table 9-4 (Cont.) SGEC Electrical Signal Summary

Signal Name

Signal
Type

Pin
Number

Vih

VII

Voh

Applicable Tests
Vol
Iii
IOI

29
28

x
x

RESET_L

CLKA *

x
x
x

x
x
x
x
x

x
x

CDAL<03>
CDAL<02>
CDAL<01>
CDAL<OO>

10
10
10
10

CLKB *

AS_L

10
10
10
10

DS_L
WA_L

RDY_L

ERR_L

DMR_L

DMGl_L

CS/DP_L<3>

CCTL_L

10
10
10
10
10
10
10
10
0

CS/DP_L<2>
CS/DP_L<1>
CS/DP_L<O>
BM_UTEST <3 >
BM_UTEST < 2 >
BM_UTEST < 1 >

x
x
x
x
x

x
x

09
08

x
x

x
x
x
x

06
05
04
03

BM_UTEST < 0 >
CSL_L

n
r
n
r
r
r

IRQ_L

IAKEl_L

IAKEO_L

NSGEC_L

TSM_H

80
79
78

DPE_L

x
x

TXEN_H

x
x

x
x
x

x
x

x
x
x

x
x

RX
RCLK

70
69

x
x

x
x
x

x
x
x
x

x
x
x

x
x

TCLK

RXEN_H

x
x

x
x
x
x
x

x
x

I~.~~~~~~~-

9-3

r
n
'

r
r
r
r

AC/DC Characteristics

Table 9-4 (Cont.) SGEC Electrical Signal Summary

Signal Name

CLSN_H

,.,

r
!"'!
l;

Pin
Number

Vih

Vil

Voh

Applicable Teats
Vol
Iii
IOI

* CLI<A and CLKB should be tested with Vihm and Vilm.

r
r
r
r

Signal
Type

9-4

AC/DC Characteristics

9.3

SGEC SYSTEM BASIC TIMING
**************************************************************

QUALIFICATION: These are all PRELIMINARY timing parameters.
**************************************************************

9.3.1

CVAX Clock In CLKA,CLKB
Those two inputs supply bask clock timing to the chip, when working with
a CVAX host. These are nominally a 25 Mhz square wave.
This table show the specified docks waveforms for the SGEC.
Figure 9-1

SGEC CLKA/CLKB timing

1
CLKA

90%
10% I

11--,

1r1'

\ _ _! I

I I

-->I !<--Tclke

I \_/

1--,

11-1,
I

I \_/

I I

-1->I l<--Tclke

\_I

-->I

1--, \

1--,
I

-,-,

l<--Tclkh

I
-->I

l<--Tclkl

!<--Tcycle->I

--->I
CLKA

l<---Tclkdly

\
1-I-I\
/-\
//-I-I\
I
\ __ 1 I I , __ ;
\ __ / I l \ _ /
\_I
I I I
I I
I I
I I I
I I
I I
-->I l<--Tclke
I >I l<--Tclke
-->I l<--Tclkh -->I l<--Tclkl
I
I

90% \
10% , _ _ 1

ti--\

I
I I
I I

l<--Tcycle->I

This table show the specified timing characteristics for the SGEC clock
inputs.
Table 9-5

SGEC CLKA CLKB Timing

Symbol

Definition

Min

Max

Units

Tc Ike

External clock edge rate

8.0

Tcycle

External clock cycle

40.0

TBS

Tclkh

External clock high

12.0

20.0

Tel kl

External clock low

12.0

20.0

Tclkdly

Clock A to clock B delay

18.0

22.0

ns
ns
ns
ns
ns

9-5

r
r

AC/DC Characteristics

r
r
r

9.3.2

SGEC RESET pin timing
This input supplies the Reset timing signal to the chip. CLI<A and CLI<B

must be supplied while assertion of RlfsET_L.
Figure 9-2 SGEC RESET Timing
RESET

pl
CI.KA

90%/--\

,--\
\ _ _1

10%/

r
r

TIMING

'--'

-->I

RESET_L

I<--- Treaeta

l<-----Treaetw--------->I

I
I
\ I

/-I- \
,--,
,--\
I
\_/
'-'
\_
I
I I

/-\

I I
I
I I

I
I

---->I

l<----Tresetsd

I _ _ _I _
NSGEC_L_ _ _ _ _
I

IAKEO_L

l<---Tresetz

---->I

AS_L
DS_L
WR L

I
- - - - - - -\ _
I _ _ _ _ __
_______/

CDiLc:31:0>
BM L<3:0>
cs7oP_L<3: O>
DPE_L

RDY_L

r
r
r
r
r

This table list the SGEC Reset timing.

Table 9-6 SGEC RESET Timing
Symbol

DetiniUon

Min

Tresetw

Reset assertion width

e•Tcycle

Tresetd

Strobe inactive delay from reset

120

Tresetz

Bus tristate time from reset

120

Tresets

Reset Input setup prior to p1

Tcycle - 10

9-6

J --------------------------------------------------------

Max

Units
ns

AC/DC Characteristics

9.4

SGEC slave mode timing
**************************************************************

QUALIFICATION: These are all PRELIMINARY timing parameters.
**************************************************************

The SGEC operates in slave mode while the host CPU accesses CSRs or
acknowledges interrupts.

9.4.1

CPU Read Cycle Timing
This paragraph shows the SGEC timing diagrams and tables for slave Read
cycle to the SGEC by the host CPU.
Figure 9-3

SGEC slave read cycle Timing

--->I

l<---Tas_hw

/---,,

11--

_____________ ! I

! '---

AS_L _ _ /

I I
I
I !<----------------- Tas_lw ------------------>!
--1 >I I<-Tasi_h
I I l
---->I I I
I<--- Tas_ds_l
!<-- Tds_hw I I I -->I
Tds_as_l -->I
DS_L _/

1-----rI

Tasi_s-->I

I
---1

I
I
I
I
I
I
I
I
I I I
!<-- I
I I
I I
I

I
I
I

I
I
!<---

11
, ________________ / I
I
I I
I<---- Tds_lw --------------->! I

I
I

I
I
I

Tds_d_h-->I

I<-- Tds_rdy_d--->I

l<-I______ I___ I
I

CDAL<31:0>_/ address
\_______/
\/
data
\
\ ______ /
\ ___ /\ _ _ _ _ _ _ _ _ I - I

CS/DP L<3: O>F-statu;--, _________ /----, >---pa_r_i_t'y

DPE_L

, _____!

I
I

_ _____
1

I
I
1
--->I
WR_L ----/-I--I
_ _ _I I
l
I
I
--->I
I

- _____ /\

BM L<3:0>-\/

\
/---

, ___ _/\ _ _ _ _ _ ___,,,

I
I
- - - !______ !___

________ /
\I
\ _ _ !\_
l<--Tasi_h
\\

parity valid

I
I

T---

I
I

\ ___ _
I

__________________________

I<--Tasi_h

------'-------'-----

______ _____________________
_________ >--Valid

- - - - - - - - - - ' - - - - - - - - ' - - - - ,_ _
/

jTds_r_d----->I

l<-

R!>Y_L - - - - - - - - - - - - - - - - - - - - - - - - - - \

Figure 9-3 Cont'd. on next page

9-7

AC/DC Characteristics

Figure 9-3 (Cont.)

r
r
.
j

r
.

r
r
r
r

Table 9-7 SGEC slave read cycle Timing table
Symbol

Definition

Min

Tas_hw

AS high

Tas_lw

AS low

Tasi_h

Address,WR,BM,CS to AS hold time

Tasi_s

Address,WR,BM,CS to AS setup time

Tas_ds_I

AS to OS delay

Tds_hw

OS high

Tds_lw

OS low

Tds_as_I

OS to AS delay

Tds_d_h

OS to DATA.Parity

Tds_rdy_d

OS to ROY delay

Tds_r_d

OS to ROY deassertion delay

50
240
10
18
40
100
140
0
0
100
0

r
n
a:

9-8

r
i

SGEC slave read cycle Timing

Max

Units
ns

320

ns
ns
ns
ns
ns

220

ns
ns
ns

180
22

r
M
L

AC/DC Characteristics

M
L

r
r
r

r
r

9.4.2

Interrupt acknowledge cycle Timing
This paragraph shows the SGEC timing diagrams and tables for interrupt
acknowledge cycle.

Figure 9-4 SGEC Interrupt acknowledge Timing

--->I

l<---Tas_hw

I\
I \

I
AS_L _ _ /

I I
I
I !<----------------- Tas_lw ------------------>!
--1 >I I<-Tasi_h

I I

---->I I
I<-- Tds_hw I I

I
I<--- Tas_ds_l
1--->I

Tds_as_l -->I

,,
I
I
I
I

I
I<---

\
II
I
I
\
I I
I
I
I I
I
I
I<---- Tds_lw --------------->! I
I
I
I
I I I
Tasi_s-->I
I<-- I
I
Tds_d_h-->I
I
I I
I
I
I I
I_ _ _ _ _ _ _ !
\I
data
COAL<31:0>_/ address
\
os_L _!

-- --------'I

\__ If

I
CS/OP_L<3:0>/

--\I'-------parity
\__

status

\- - - - - - - '
I

'--'i

I>PE_L

/
I
1.---~-_,.'------.---------'
\__
I
\ __ \I
/\ parity valid
I
I
I
I
I

--->I

WR_L

l<-1
\__

1<--Tasi_h

I \
---------------------'-----------,,

___ 1 1
I

BM L<3:'0>\/

--->I
Valid

'------------~---------------

l<--Tasi_h
\I

\__

- --"·------"-----------------'
I
I
ITds_r_d----->I

l<----Tiakei_rdy_d --------------->! \._ _ _ _ _ _ !

l<-

I' - - - -

I
IAREI_L - - -

'--------------'

---->I

IAREO_L - - - - - - - - - - -

l<---Tiake_d

I
\ I

'----------

Figure 9-4 Cont'd. on next page

9-9

r
,.,

AC/DC Characteristics

Figure 9-4 (Cont.)

Table 9-8

r
r'

Definition

Min

Tas_hw

AS high

Tas_lw

AS low

240

Tasi_h

Address,WR,BM,CS to AS hold time

Tasi_s

Address,WR,BM,CS to AS setup time

10
18

Tas_ds_I

AS to OS delay

Tds_hw

OS high

Tds_lw

DSlow

Tds_as_I

OS to AS delay

Tds_d_h

OS to DATA.Parity

Tiakei_rdy_d

IAKEI to ROY delay (when the SGEC
responses to the Interrupt acknowledge
cycle).

100
140
0
0
100

Tds_r_d

OS to ROY deassertion delay

Tiake_d

IAKEI to IAKEO assertion delay (when the
SGEC propogates the IAKEI signal)

140

340

r-t;

r
n
.

n
n
..

n
n
.

SGEC slave read cycle,interrupt acknowledge cycle Timing table

Symbol

SGEC Interrupt acknowledge Timing

9-10

Max

Units

ns
ns
ns

180

AC/DC Characteristics

9.4.3

CPU Write Cycle
In a host CPU write cycle, it outputs information to The SGEC.
Figure 9-5

CPU write cycle for SGEC in slave mode timing

--->!

l<---Tas_hw

/----,,

11--

I \
I I

AS_L _ _ /

I !<----------------------- Tas_lw --------------->!
--1>
I<---- Tasi_h

I
I

---->I
I<-- Tds_hw I

Tds_as_l--->I

---,--,,....._,
I
I

Tasi_s-->I

I
I

I'----------I
I

I
I

I
II

I
I
I
I

I
\I_ __

!<----- Tds_lw ------------>! I

I
I

!<--- Tds_rdy_d--->I
I

I< - I ->I
I

l<--Tds_ct_ct
I

I
I

I
I
I Tds_d_h->I

I
data

!\ _ _ _ /\

WR_L

I
I

I
I
I
I
I

I
I

I
/----,/

___

'--

--.----_,.-..........,./

parity valid

_ _ 1I_ _ __

____
--,-------,----________-----,-1/ I

\/
/\

l<--Tasi_h

\/
/\

'jTds_r_d-->II
I
I
I

RDY_L

Table 9-9

\
/--

I --

___ 1I_--->I
_

I
l<--

parity

l<--Tasi_h

--->!

----'---!
I

BM L<3:0>

\ _ _ _ _ !\ _ _ _ /\.,.__ _ _.

---,--,

CS/DP L<3:0>/""'Stat-;:;---\/

DPE_L

I
-

---,---

I ----~---'
address
\/ --~- \I

CDAL<3l:O>

l<--

/-,

!
l

I<---- Tas_ds_l
l-->I

1
I
I
I

I
I
l

l<----1

,______ '-/

CPU write cycle Timing

Symbol

Definition

Min

Tas_hw

AS high

Max

Units
ns

9-11

n
n
n
n
n
n
n
n
n
'

AC/DC Characteristics

Table 9-9 (Cont.)
Symbol

Definition

Min

Max

Units

Tas_lw

AS low

Address,WR,BM,CS to AS hold time

Tasi_s

Address,WR,BM,CS to AS setup time

Tas_ds_I

AS to OS delay

240
10
18
40
100
140
0
100
0

320

Tasi_h

Tds_hw

OS high

· Tds_ lw

DSlow

Tds_as_I

OS to AS delay

Tds_rdy_d

OS to ROY delay

Tds_r_d

OS to ROY deassertion delay

Tds_d_d

OS to DATA delay

Tds_d_h

OS to DATA hold time

u
M

l :.

n
.

r
r:
r:t.:
M

CPU write cycle Timing

9-12

ns
ns
ns
ns

220

ns
ns

180
22
20

ns
ns
ns

r
r!

AC/DC Characteristics

n
9.4.4

NSGEC timing
This diagram shows the timing for the NSGEC_L output. The NSGEC_L
signal is asserted when the following occurs:

- A bus cycle doesn't address the SGEC.

- Not during interrupt acknowledge cycle. ·

n
n
n

- The SGEC selected to work in its internal address.
Figure 9-6 NSGEC timing

_____

\
ti
\.
'I - - - - - - - - - ' II
I
CDAL<31:0>
I
address
\_/data
\ _ _/
addreaa
\__
'---.---' \_
I I
\.______ /
I
I
1<--'l'aa_nsgec_d
I
--->I
--->I
l<--'l'as_nagec_a
I
I
NSGEC_L - - - - - - - - - I_ _ _ _ _ __

AS_L

'-····-----'

~ .,l
~

Table 9-10

NSGEC timing

Symbol

Definition

Min

Max

Units

Tas_nsgec_a

AS to NSGEC assertion delay

100

180

Tas_nsgec_d

AS to NSGEC deassertion delay

n
n
n
n
'
'

r
''

,.
l i

"
r
I

9-13

n
n
n
n 9.5
"'j

AC/DC Characteristics

SGEC MASTER MODE TIMING
**************************************************************

QUALIFICATION: These are all PRELIMINARY timing parameters.
**************************************************************

9.5.1

OMA Grant Cycle
The SGEC can request mastership of the CP-BUS and related control
signals to transfer incoming and outcoming data by OMA
Figure 9-7 External OMA cycle timing - Acquiring the CP - bus

n
,,

pl
CL:KA

r
r

CLRB

\_/
I \_/
I
I
\
\
I
I
' \ I_ I
\_/
I

DMR_L

I
--->I

-,,
p3

\_I

I
I II \

'-'I

- \

I \_/

I<-- Tdmrd
I
\ I

t-1 \

I
I
I
\ I
I

\_/

I-\

\_/

'-'

\_/

I
I

- I

I
I

- \

\
\

I
I

I<--- Tdmg_out_h-->I
->I l<---Tsyncs
I
DMGI_L - - - - - - - - -

M
t~

_________ _____ I____ I ___________
I

I I

I
I
....,...

\ \..,.....
I

______________________
/I
1

r
r

AS_L

n
n

CDAL<3l: 0>

9-14

....,...

l<--

________
I

' \, I

_________ I

-->I l<--Trdalhlz

------------'
DAL CVAX

\ ___________ /

-------------------'

Tasd---->I

\. I

OPE L
CS/DP_L<3:0>
BM_L<3:0>
WR_L

_..,.

-->I l<--Trshlz

DS_L

n
ri
L

t-1 \

DAL SGBC

'·------------------~

n
L
n

n
n
n

n
n

AC/DC Characteristics

Table 9-11

External OMA cycle timing table - acquiring the CP - bus

Symbol

Definition

Min

Max

Units

Tdmrd

DMR delay

Tsyncs
)

Asynchronousr input setup

Tasd

AS strobe assertion delay

Tdmg_out_h

DMGI to SGEC outputs High delay

0
100

Trshlz
Trdalhlz

13.5

140

Required tri-state

Required COAL tri-state

Figure 9-8 External OMA cycle timing • Releasing the CP-BUS

n
d
M

CLKA

/-\

,_,

\_/

pl
I

\
'-'

/-\
'-'

,-,
\_!

'-'

\_!

,-,
\

I l<--

I I

i,,--------------------------I

----------------------------.-------'
I
I
I

Tasid-->I

DS_L
OPE L
CS/DP_L<3:0>
BM_L<3:0>
WR_L

I
--->I

I<--

I
I

CDAL<31:0>

I
I
--->I
I

I
I
----->I
DAL SGBC

\
I

l<--Tasz
I

I<-- Treldlz
I

Table 9-12 External O,.A cycle timing table - releasing the CP-BUS
Definition

Min

Max

Units

Tdmrd

DMR delay

Tasld

AS strobe deassertlon delay

Symbol

--------------------------~'I

r
r

' I- ' II

DMR_L

AS_L

n
r

/-I-,

I Tdmrd-->I

M
L
[I

CLKB
,-,
,-,
,-,- ,
,-1-,
I
_ _!
\_!
\_I I
\_! I
'-'

/-\

9-15

r!
ll
r!
L

r
n

AC/DC Characteristics

Table 9-12 (Cont.) External OMA cycle timing table - releasing the CP-BUS
Symbol

Definition

Tasz
Treldlz

r
n

n
n
.
'

r
n
~

L'.
r!
f:

n
r

9-16

Min

Max

Units

Tri-state delay

COAL tri-state

AC/DC Characteristics

9.5.2

Single Transfer SGEC Read Cycle
In a single transfer SGEC read cycle, the SGEC reads one longword from the main memory. A
single transfer read cycle requires a minimum of four clock phases (nominally 160 ns) and may last
longer, in increments of tv.ro clock phases (nominally 80 ns).
Figure 9-9

Single Transfer SGEC read Cycle
p2

/-I-,
/-I-,
11-,
/--,
/--,
1-I-,
I
\
\
I \ _ I I \_/ I \ __ ;
\_!
\_! I
' -I
I
I
I
I
_l_I
I
____ I
I
CLKB 90% I
\ I
I
\ I
11 \ I I
\
I
\
I
\ I
/I \
10%/
\
I
\ __ ; I
\_/
\_I
\_I
\_I I
\
I
-I
I
I
I
I
I
I
I
I
I
I
I
I
--->I
l<-Tasdl
Tasidl--->I
I<-AS_L
I I
I
I
I
CLKA 90%-\

\_!

10%_

----,----,I I
I
I

DS_L - - -

->I

l<-Tdsd

_1--j-\I address
I

CDAL<31:0>\

I
I
Tsd-->I

-->I
-->I

______ II II

--,-,________
I status

CS/DP L<3:0>

'----·

I
I
Tdps->j
l<---I ->I
l<-Tdh

!_ _ _

--------,___ / ______
\

Tdps--> I

I<--

I ->I

-->I

1<--Tsd

I
I

I<--Tsd
\/____

--,-----

-->I

j<--Tdh

1---,;p-ar-i-ty-z
- - - ,_ _ /\ enable /--------

---1----

BM_L<3:0>

data

/parity

I
!
1
l

_ _ _ _ _ _!

___ I l

\ ____ /

I l<-Tdalhlz
l<---Tdalh

I<-

I
I
Tdz---> I
I<-Tdh--> I
l<-Tds->j
I<-----·---~/

I<--

'I I - · - - - -

lI
I
1
Tdald---> I
I

DPE_L

Tdsid->I

-- \ II
I
'------·
Tdalh--> I I!
I l<--Tdalhlz
______ I I

WR_L

I
I

'-------------------.,...-·
I
I
I

BM valid

\/ __ _

---- -----------------------,------- /\ __ _
Tsws --->I
1

I
RDY_L - - - - - - - - - - - - - - - - - - - - - - - - - I
ERR_L
\ I

l<--

->I

l<--Tswh

I I<-- Tswlmax
I -----l/ I

,______

Figure 9-9 Cont'd. on next page
9-17

AC/DC Characteristics

Figure 9-9 (Cont.) · Single Transfer SGEC read Cycle

Whenever ERR_L is asserted, DS_L and AS_L remain asserted one
additional cycle before the deassertion.
In asynchronus mode, the SGEC waits one additional cycle before starting
the next transfer.
Table 9-13

Single Transfer SGEC read Cycle timing table

Symbol

Definmon

Min

Max

Units

Tasd

AS strobe assertion delay

13.5

Tasid

AS strobe deassertion delay

Tdsd

DS strobe assertion delay

Tdsid

DS strobe deassertion delay

Tdalh

COAL hold

4.5

Tdald

COAL drive

Tdalhlz

COAL tri-state

Tdz

Required COAL tri-state

Tdh

Required COAL hold

Tds

Required COAL setup

Tdps

Required Parity setup

Tsd

General strobe assertion delay

Tsws

ROY/ERR sample window setup

13.5

Tswh

ROY/ERR sample window hold

4.5

Tswlmax

ADY/ERR maximum assertion

9-18

r
AC/DC Characteristics

r
r

r
rL

9.5.3

Octaword Transfer SGEC Read Cycle
In an octaword transfer SGEC read cycle, the SGEC reads four longwords (quadword) from main
memory. An octaword transfer SGEC read cycle requires a minimum of eighteen clock phases
(nominally 240 ns) and may last longer. Each longword transfer may be independently stretched in

increments of two clock phases (nominally 80 ns).
Figure 9-10
p2
CLKA 90111-\

10111_
10'1

,-,\

'-'I
I
I
\ I

CLKB 90111

Octaword Transfer SGEC Read Cycle

'-,-

I
I
\ I

',-

,,,

I
I
l<-Tasdj
I I
I
\ I I
I

\_!I

p2
\

,_,

p4
\

\
\_/

->I

I
Tdalh--->II

I
I
-->I

I<-

I
\

- \

I
\ I

\_/

..........
'...........
,-

l<-Tdsd

I
I
I

l<--Tdalhlz

Tdz---> I
I<-Tdh-->I
l<-Tds->I
l<-----data

I
\

I
l<---I ->I
l<-Tdh

Tdps->I

'---

\. _ _ _ _ _ _ _ _ _ _ /parity

\ _ ••••••••••

l<--

1 ->I

\!I__ ......... .

Tdps-->I
DPB_L

.............

I
Tdsid->I l<-I , _ ............ .

.-----'
status

I
I
I

1 I .--...,.---'
CDAL<3l:o>\
addrea
\_II
_I
I\
I
I
I
-->I I <-- Tdalhlz
I
-->I l<---Tdalh
I
Tsd-->I
I<1
I
CS/DP_L<3:0>

I
\ I
II
'
'
I<I

DS_L _ _ _ _ _ _ _ _ _ _ _

I
II

\_/ I

\_/

Tdald--->I

I
--->I

'-'
-

,-, \

'-'I
I
\ I

AS_L

l<--Tdh

--....---------------'
\/parity \ _ ••••••••••
\_/\_enable_/
I
I
I
l<--Tsd
-->I
I
I
I

-->I
BM_L<3:0>

l<--Tsd

--------.,.-------------·
....... .
BM valid

\/
I\

·----------------.....----·
....... .
I
Tsws -->I

I
RDY_L - - - - - - - - - - - - - - - - - - -

BRR_L

l<-->I
->I

l<--Tswh
I I<-- Tswlmax

II I

'-----'

Figure 9-10 Cont'd. on next page

r
.

9-19

AC/DC Characteristics

Figure 9-10 (Cont.)
p2

11-- \

CLKA 90%-\
10%_

Octaword Transfer SGEC Read Cycle

I
I
I
\ I

\ _ _!

CLKB 90% I
10%/

I
\

'--

---

- I

- \

11- \

I
I
!
!

I
->I

-1
1<-Tctsct

I
I\ I

DS_L

Tdsid->I

___
Tds--->I

--!I \

-- \

I
\

-- \

I
\

- I

I
I

l<--

l<--I<--- Tdh

I ->I
I II<--- Tdz
____

----,____
/---,
I
--I

1 ---

1 ->I

CDAL<31: 0> • · - , . . - - - · - - -

-- I \ -- I
l<--Tasid
-->I
/-----, \ ______
,_ _ _ !

I
I
I

AS_L

I- \
__ / I -- \
\

data

address

_____

1
Tdps-->I

l<---

1 ->I

CS/DP_L<3:0>.

-,----

I <---

,_____

_ _ _ _ _ _ _ _ _ /- parity

Tds--->I
I

Tdh

, ___;
/
\

l<---

->I

I<--- Tdh

DPE_L

I parity \. _ _ __
-,-----------\_enable_/

WR_L

I
-----,-------I

-->I

BM_L<3:0>

I
I
I
I

1<--Tsd

___/\___________ _ _____ ____
\/I___

ElM v a l i d - - - - - - - - , ; - - - - - - - - - - ,

Tsws-->I
1

RDY_L
ERR_L

'-----/

status

I
I
'\I

_...,..

I
I
I
l<--

->I

1<--Tswh
I<-- Tswlmax

_________II - - - - - - - - - - - /I

Whenever ERR_L is asserted, DS_L and AS_L remain asserted one
additional cycle before the deassertion.
In asynchronus mode, the SGEC waits one additional cycle before starting
the next transfer.

9-20

r
n
u

AC/DC Characteristics

M
Il

Table 9-14 Octaword Transfer SGEC Read Cycle timing table
Symbol

Definition

Min

Max

Units

Tasd

AS strobe assertiOn delay

13.5

Tasid

AS strobe deassertion delay

Tdsd

OS strobe assertion delay

Tdsid

OS strobe deassertion delay

Tdalh

COAL hold

0
4.5

18
18
18

Tdald

COAL drive

Tdalhlz

COAL active drive delay

Tdz

Required COAL tri-state

Tdh

Required COAL hold

Tds

Required COAL setup

Tdps

Required Parity setup

Tsd

General strobe assertion delay

Tsws

ROY/ERR sample window setup

n
n

Tswh

ROY/ERR sample window hold

13.5
4.5

Tswlmax

ROY/ERR maximum assertion

"
I '.

"
n
u

ns
ns
ns

18
18

ns
ns

ns
ns
ns

n
n
n
n

n
n
~ l

n
~.

M
t '.

9-21

n
n
n
n
n

n
n
n

AC/DC Characteristics

9.5.4

Single Transfer SGEC Write Cycle
In a single transfer SGEC write cycle, the SGEC writes one longword to the main memocy. A

single transfer write cycle requires a minimum of four clock phases (nominally 160 ns) and may last
longer, in increments of two clock phases (nominally 80 ns).
Figure 9-11

Single Transfer SGEC write Cycle

CLKA 90%-\
ti\
/I
10%_ \_I I
\_I I

n
n
'

n
n
n
'

n
n
n

1-I-,
/-\
I-\
/-I-,
I-\
\_/ I \_I
\_I
\_I I \_/
\_
_
1_1_1_
_1_
CLKB 90% I
\ I I \ I /I \ I I \
I \
I \ I /I \
I
10%/
\_I
\_I I ' - '
'-'
\_I
\_I I \_/
I
I

I
--->I

AS_L - - - - - , . - - - -

I
I
l<-Tasdl

I I

I
I
Tasidl--->I

\ I I
\

->I

l<-Tdsd

DS_L - - - -I - - - - -I- -I\

I
I
Tdald---> I
I

Tdalh--->I
I<-

I \

II

_____ I

1<--

I I
I

Tdsid->I l<--

I,,,-.,.----

I
----------1
I
Tdalh----> I
l<--Tdald
I
I

I<--

COAL<3l:O>\_.....,.._/ address
\_/
data
\_
_!
I \, _ _ __...,. _! I \ , - - - - - - - - - - - . . . - - '

I
Tdalh--->I II
I<--->I
l<--Tparityd
I
_____ I I
CS/DP_L<3: 0>_-..._/ status
\_/
parity

I
I
Tparityh-->I
I
I

1<-I
I
\__

' - - - - - - ' II '--------------------'
I
I
--->I

l<--Tparityd

I
I

-->I
WR_L

Tparityh-->I

l<--

I
I

,--

1
\I

DPE_L

'--------------....----'

1<--Tsd

-----'-I
\ I

--------'.,.--------....,...--------------------- - >I

l<--Tsd

____ _________________________
\I
/\,

BM_L<3:0>

n
n
u

BM valid

Tsws-->I

1
I

RDY_L - - - - . . . , . - - - - - - - - - , . . - - - - - - - - - -

ERR_L

I
II

I
--->II

-->I
CCTL_L - - - -

I
\ I
\

Figure 9-11 Cont'd. on next page

9-22

l<--Tcctl_d
I

l<--Tcctl_d
I
I

\
/ \/_

l<-->I
->I

l<--Tswh

I I<-- Tswlmax
II I

\ II
'-------'

n
n
n
n
n
l
'

AC/DC Characteristics

Figure 9-11 (Cont.)

Single Transfer SGEC write Cycle

Whenever ERR_L is asserted, DS_L and AS_L remain asserted one
additional cycle before the deassertion.

In asynchronus mode, the SGEC waits one additional cycle before starting

Table 9-15 Single Transfer SGEC write Cycle timing table

Symbol

Definition

Min

Max

Units

Tasd

AS strobe assertion delay

Tasid

AS strobe deassertion delay

Tdsd

OS strobe assertion delay

13.5
18
18
18

the next transfer.

n
M
f I
&'

n
'

Tdsid

OS strobe deassertion delay

Tdalh

COAL hold

4.5

Tdald

COAL drive

Tdalhlz

COAL active drive delay

Tparity_d

Parity delay

Tparity_h

Parity hold

4.5

Tsd

General strobe assertion delay

Tcctt_d

CCTL_L delay

Tsws

ROY/ERR sample window setup

Tswh

ROY/ERR sample window hold

0
13.5
4.5

Tswlmax

ROY/ERR maximum assertion

ns
ns
ns
ns
ns

18
18

ns
ns

18
18

ns
ns
ns
ns

n
n
d

n
'

n.
n
n
n
f:;

f,, !

n
r

9-23

n
J

AC/DC Characteristics

9.5.5

Octaword Transfer SGEC Write Cycle
In an octaword transfer SGEC DMA write cycle, the SGEC writes four longwords (quadword) to
main memory. An octaword transfer SGEC write cycle requires a minimum of eighteen clock
phases (nominally 240 ns) and may last longer. Each longword transfer may be independently
stretched in increments of two clock phases (nominally 80 ns).
Figure 9-12
p2

n
~:

n
n..
n
'

cLRA 90,-,

,r,

,-1-,

II
I
Tdald--->I

n
'

r
I

,-.......
\

I
Tdalh---> I

I
I
Tds--->I
I_ _ _ 1 status
\

I
I

-->I

I
l<-I

data

\
,-

I I
1<---->I
l<--Tparityd
I
I
I
I I
_1 _ _ _ _ _ _ _ _ _ _ _ 1
\_/
parity
\_
I I \
I

l<--Tparityd

Tparityh-->I

1
\ I

l<--

I
I

1_....

'-------------'
I
I

l<--Tsd

I
\ I

WR_L

Tdalh---->I
I
I

l<--Tdald

- - - - - 1\ _ /_I

CI>AL<31:0>\._ _ _ / addreBB
_I
I\

------'·-----------------.---· ......... .
-->I

l<--Tsd

--------------------··
...... .
BM_L<3:0>
\/
BM valid
----''·--------------------··
...... .
I
Tsws-->I
1
RDY_L - - - - - - - - - - - - - - - - - - ERR_L

I
-->I
CCTL_L - - - -

n
n

\_/

I ' · - - - - - - - - - 'I

Tdalh---> I II

;

,-,\

Tdaid->I l<-I-·············
It

,- II ,-

->I
l<-Tdad
DS_L - - - - - - - - - . , . - - - I
I
I
I\ I

- .......
'I
I
'--..--..,..-----------.....-·
............ .
I
I

DPE_L

[!,

I- \

,-,

\_/
\_/
'-' I
\_/ I
'-' I
'-'
_I
_I
I
I
CLKB 90% I
\ I
I
\ I
/I \ I
I
\
\
\
10 I
\_I
\_I I
\_/
\_I
\_/
I
--->I l<-Tasdl
AS_L
I I
I
\ I I
I

--->I

10%_

n
n

Octaword Transfer SGEC Write Cycle

,_______

I
\ I

Figure 9-12 Cont'd. on next page
9-24

l<--Tcctl_d

--->I
l<--Tcctl_d

I
II

I
l<--

->I
->I

l<--Tswh
I I<-- Tswlmax

_____

II I
/

I
- - - - - - - - - - - - · ....•......

AC/DC Characteristics

r
Figure 9-12 (Cont.)
p2

l. :

Octaword Transfer SGEC Write Cycle

1-1- \
CLKA 90% \
10%_ \ _ I I
\
I
I
CI.RB 90% I
I
' \_
I I
10%/
I
AS_L
I
I

I
->I

I-\
I

\_/ I

- \

\ _I

t-1- \

\_/

I
I

p4
I

l<--Tasid

\ _I

- \
\

I
I
Tdsid->I l<-1

l<-Tdsd

CDAL<3l:O~· · - , / - - - d - a t - a - - - - - - - - - - t _ /

I
I-,----------I\ I
11
II ' - - - - - - - - - - /I -->II
l<--Tdalh
--->I
1<---Tdald
I
I
I

..•

-,
I

/\-------------/

--->I

...

\ _ _ _ __
I

l<--Tparityh

-->I
I

1<---Tparityd

address

CS/DP_L<3:0> - - \ /---~----------'
parity
\_/
...
I\
I \

- \

n
n
n

I
I

n
!.-. l

DS_L

\_/

- \

\_/

I -->I
I
I
I
I

\_/

- \

- \ I

\_/

II
/
-....,----------------:-----/
->I

statys

\ _ _ _ __
I

l<--Tparityh

n
n

I
I

-->I

BM_L<3: 0>

1<--Tsd

'-----------------BM valid
\/
...- -\/
/\
/\

__
I
I
I

n
u

I
1
I

Tsws-->I
I

RDY_L - - - - - - - - - - - - -

n
M

n
.

ERR_L

I
I

I
-->I
CCTL_L

--->I
l<--Tcctl_d

I
\ II

_______

I
\ \. I

I
I
I

I
->I
->I

__________

l<-l<--Tswh
I I<-- Tswlmax

II I

'......,...--...,._~/
l<--Tcctl_d
I
/

Whenever ERR_L is asserted, DS_L and AS_L remain asserted one
additional cycle before the deassertion. CCTL_L is reasserted when DS_L
asserts for the third longword .

n
n
f

-1

~~~----------~--~--------~--------------------~----~--~~----~·

9-25

r
~.

;

AC/DC Characteristics

In asynchronus mode, the SGEC waits one additional cycle before starting
the next transfer.

n
n
n
n
n.
'

Table 9-16 Octaword Transfer SGEC Write Cycle timing table
Symbol

Definition

Min

Max

Units

Tasd

AS strobe assertion delay
AS strobe deassertion delay

Tdsd

OS strobe assertion delay

Tdsid

OS strobe deassertion delay

13.5
18
18
18

Tasid

Tdalh

COAL hold

Tdald

COAL drive

0
0
0
0
4.5
0
0
0
4.5
0
0
13.5
4.5

Tdalhlz

COAL active drive delay

Tparlty_d

Parity delay

Tparity_h

Parity hold

Tsd

General strobe assertion delay

Tcctl_d

CCTL delay

Tsws

ROY/ERR sample window setup

Tswh

ROY/ERR sample window hold

Tswlmax

ROY/ERR maximum assertion

M
t!

n
,

n
n
.n
,

n
n
n
n
,
,

& :i

9-26

ns
ns
ns
ns

18
18
30

ns
ns
ns
ns

18
18

ns
ns
ns
ns

r
·r

AC/DC Characteristics

r
r
r
r

9.6

ri " 9.6.1

SGEC serial interface timing
**************************************************************

QUALIFICATION: These are all PRELIMINARY timing parameters.
**************************************************************

This paragraph specifies the serial interface timing. The serial clock is
nominally a lOMhz square wave.

Receive clock and Transmit clock timing

"'' -J

Figure 9-13 Receive clock timing

I<--- Trot ------>I
I
Trch--->I
I<-I
'l'rcr--->I I<- ->I
l<--Trcl
I

I
I I

I
I\
I \
I I

_ _ _I

RCLK

I
II I

\. _ _ _ ,

-->I I<--Trcf

ri
~

Figure 9-14 Receive clock and Transmit clock timing

4~ .J

n
n
"

n
n
n

TCLK

l<--Ttcl
-->I
I
I
Ttch-->I
I<-I
I
I
\
I\
I I
I II
\
I
I I
I\
I I
I I
I I -->I l<--Ttcf
Ttcr--->I I<--

\
\

This table show the specified timing characteristics for the Transmit and
receive clocks.

n
n
n.

Table 9-17 Transmit and Receive clock Timing
Symbol

Definition

Min

Typ

Max

Units

Trct

RCLK cycle time

Trcl

RLCK low time

Trcr

RCLK rise time

Trcf

RCLK fall time

Ttct

TCLK cycle time

Ttcl

TCLK low time

99
45

100
50
50
2.5
2.5
100
50

RCLK high time

82
38
38
0

118

Trch

ns
ns

101
55

ns
ns

__,l

9-27

AC/DC Characteristics

Table 9-17 (Cont.)

9.6.2

Transmit and Receive clock Timing

Symbol

Definition

Min

Typ

Max

Units

Ttch

TCLK high time

Ttcr

TCLK rise time

Ttcf

TCLK fall time

2.5
2.5

SGEC RESET pin timing
This input supplies the Reset timing signal to the chip. CLKA and CLKB
must be supplied while assertion of RESET_L.
Figure 9-15

SERIAL RESET Timing

!<------ Ttcl --->I
!
I
TCLK

/----,

/---,

/----,

\ ___!

/---,

\ _ _ _ _!

\ _ __

!<-----Tresetw--------->I
RESET_L - - -

I
\ I

I
I ----I I

\__

This table list the SERIAL reset timing
Table 9-18

SGEC RESET Timing

Symbol

Definition

Min

Trasetw

Reset assertion width

4Ttcl • 400

Ttcl

TCLK cycle time

9-28

Max

Units
ns

101

AC/DC Characteristics

9.6.3

Serial link timing
Figure 9-16

Serial link timing

RCLK _ _ _ _ /

1-I- - ,
1-I---,
I
, ___ / I
\ ______ /
1

I
I

I
I<----Trds---> I
I
I
->I 1<--Trdh
I
I
-->I I<--Trctf I
\/____
I\

--------,

l<--Trens

-->I

I
I
RX 7111/I/III11I111

!--, ' - - -

\I l ___,_ _ _ _ _ \//;77/77711777
I\
/\ _ _ _ _ _ _ _

Trdr->I

I<--

I
I

l<--Trenh-->l<--Tdpl-->I
,---~~,-- I
I

,______I

/------

\ I

RXEN_H_ _/

CLSN_H_ __/

II
I
I

-->I

11--,
TCLK _ _ _ /

I
'--1
l<---Tcph

11--,

, ___ / I

I
I
I<--Ttctp-> I
I
I
TX

\ ____ _/

I
I
I
--->I

l<--Ttcth

'-----'

\I
/\

1-1----,

, ___ _/ I

\ __

I
I
I
I

- -

\/
\I
\/
/\ _ _ _ _ _ _ _ _ !\. _ _....,..._ _ _ /\ _ _

-----,--I<--Ttep---> I
I
TXEN_H_ _ _ _ _ _ _ I

1---,

l
I
Tteh---->I
,______ !<-!
\

'--

9-29

AC/DC Characteristics

n
n
n
n

This table show the specified timing characteristics for the SGEC clock
inputs.

*· j

M
I!

n
n
n

Table 9-19 Serial link Timing
Symbol

Definition

Ttep

TXEN propagation delay

Tteh

TXEN hold time

Ttdp

TX propogation delay

TX hold time

RX data rise time

Trdf

RX data fall time

0
5

Trdh

RX data hold time

Trds

RX data setup time

Tdpl

RXEN low time

Tcph

CLSN high time

ns
ns

RXEN setup time

Trenh

RXEN hold time

n
I

n
'

M
ll ~

n
'

9-30

ns
ns

Trens

60
120
80
40

,.,

Units

Ttdh

Max

Trdr

Min

ns
ns

AC/DC Characteristics

9.6.4

SGEC timing for 100ns and 60ns clock cycles
Table 9-20 SGEC timing - 1OOns
Symbol

Definition

Min

Max

Units

Tc Ike

External clock edge rate

10.0

Tcycle

External clock cycle

50.0

TBS

Tclkh

External clock high

15.0

25.0

Tclkl

Extemal clock low

15.0

25.0

Tclkdly

Clock A to clock B delay

23.0

27.0

Tresetw

Reset assertion width

s•Tcycle

Tresetd

Strobe inactive delay from reset

150

Tresetz

Bus tristate time from reset

150

Tresets

Reset input setup prior to p1

Tcycle - 12

Tas_hw

AS high

Tas_lw

AS low

300

Tasi_h

Address.WR,BM,CS to AS hold time

12.5

Tasi_s

Address,WR,BM,CS to AS setup time

Tas_ds_I

AS to DS delay

Tds_hw

OS high

120

Tds_tw

OS low

175

Tds_as_l

OS to AS delay

Tds_d_h

OS to DATA.Parity

Tds_rdy_d

OS to ADY delay

125

225

Tds_r_d

DS to ROY deassertion delay

27.5

Tiake_d

IAKE! to IAKEO assertion delay

175

425

Tds_d_d

OS to DATA delay

Tds_d_h

DS to DATA hold time

Tas_nsgec_a

AS to NSGEC assertion delay

125

225

Tas_nsgec_d

AS to NSGEC deassertion delay

Tnsgec_lw

NSGEC assertion width

125

325

Tdmrd

DMR delay

22.5

Tsyns

Asynchronousr input setup

Tsynh

Asynchronous input hold

Tsynf

Asynchronous input fall time

Tasd

AS strobe assertion delay

Trshlz
Trdalhlz
Tasid

AS strobe deassertion delay

Tasz

Tri-state delay

Treldlz

COAL tri-state

400

275

ns
ns
ns
ns

ns
ns

Required tri-state

Required COAL tri-state

20
50
20

9-31

AC/DC Characteristics

Table 9-20 (Cont.)

SGEC timing· 100ns

Symbol

Definition

Min

Max

Units

Tdsd

DS strobe assertion delay
DS strobe deassertion delay

0
0

20
20

Tdsid
Tdalh

COAL hold

Tdald

COAL drive

Tdalhlz

COAL tri-state

Tdz

Required COAL tri-state

Tdh

Required COAL hold

Tds

Required COAL setup

Tdps

Required Parity setup

0
50
5
25
20

Tsd

General strobe assertion delay

Tsws

ROY/ERR sample window setup

Tswds

ROY/ERR deassertion setup

Tswh

ROY/ERR sample window hold

Tswtmax

ADY/ERR maximum assertion

Tparity_d

Parity delay

Tparity_h

Parity hold

Tcctl_d

CCTL delay

9-32

ns
ns

20
20

ns
ns
ns
ns
ns
ns

37.5

22.5

AC/DC Characteristics

Table 9-21

SGEC timing • 60ns

Symbol

Definition

Min

Max

Units

Tclke

External clock edge rate

Tcycle

External clock cycle

30.0

6.0
TBS

Tclkh

External clock high

9.0

15.0

Tclkl

External clock low

9.0

15.0

Tclkdly

Clock A to clock B delay

13.5

16.5

Tresetw

Reset assertion width

8*Tcycle

Tresetd

Strobe inactive delay from reset

Tresetz

Bus tristate time from reset

Tresets

Reset input setup prior to p1

Tcycle - 8

Tas_hw

AS high

37.5

Tas_lw

AS low

180

Tasi_h

Address,WR,BM,CS to AS hold time

Tasi_s

Address,WR,BM,CS to AS setup time

13.5

Tas_ds_I

AS to OS delay

Tds_hw

OS high

Tds_lw

OS low

105

Tds_as_I

OS to AS delay

Tds_d_h

OS to DATA,Parity

Tds_rdy_d

OS to ROY delay

135

Tds_r_d

OS to ADY deassertion delay

16.5

Tiake_d

IAKEI to IAKEO assertion delay

103

257

Tds_d_d

DS to DATA delay

Tds_d_h

OS to DATA hold time

Tas_nsgec_a

AS to NSGEC assertion delay

Tas_nsgec_d

AS to NSGEC deassertion delay

Tnsgec_lw

NSGEC assertion width

Tdmrd

OMR delay

Tsyns

Asynchronousr input setup

Tsynh

Asynchronous input hold

Tsynf

Asynchronous input fall time

Tasd

AS strobe assertion delay

Trshlz
Trdalhlz
Tasid

AS strobe deassertion delay

Tasz
Treldlz
Tdsd

DS strobe assertion delay

13.5

Tdsid

DS strobe deassertion delay

13.5

ns
240

165

135

195

13.5

Required tri-state

Required CDAL tri-state

13.5

Tri-state delay

COAL tri-state

13.5

9-33

AC/DC Characteristics

Table 9-21 (Cont.)

SGEC timing • 60ns

Symbol

Definition

Min

Tdath

COAL hold

Tdald

COAL drive

13.5

Tdalhlz

COAL tri-state

13.5

Tdz

Required COAL tri-state

Tdh

Required COAL hold

Tds

Required COAL setup

Tdps

Required Parity setup

Tsd

Genera! strobe assertion delay

Tsws

ADY/ERR sample window setup

Tswds

ADY/ERR deassertion setup

Tswh

ADY/ERR sample window hold

Tswlmax

ROY/ERR maximum assertion

Tparity_d

Parity delay

Tparity_h

Parity hold

Tcctl_d

CCTL delay

9-34

Max

Units

13.5

22.5

ns
ns

13.5

References

William Stallings. Local Networks. Macmillan Publishing Company May 1984

Computer Networks. Prentice Hall Inc - April 1981

Introduction to local area networks. Digital Press - Edited 1982

Network - a description of Digital LAN support. Digital Press - Edited
1982

G. R Davis. The Local Network Handbook. McGraw Hill - May 1982

DEC Standard 134 B - 1988

The Ethernet Blue Book. Intel, Xerox and Digital - May 1982

The IEEE 802.3 Standard. IEEE 802. * Committee - 1985

AMD 7900 Data Sheet. AMD - Edited 1984

10 AMD 7902 Data Sheet. AMD - Edited 1984
11 The CVAX data sheet

12 The CMCTL data sheet
13 The CCLK data sheet
14 80386 CPU data sheet. Intel - 1986

A-1

SGEC internal block diagram

The following is a list of the main blocks in the SGEC:
Short
name

Name

Description

HPI

Host Pin Interface

A bus interface unit which takes care of all internal signals for
interfacing to the host system bus.

BOP

Bus Data Path Unit

Data path interface unit which passes the data between the internal
and external buses.

OMA

Direct Memory Access Unit

3 OMA channels which control the transfer of data between the
SGEC and main memory. One RX channel, one TX channel and

one control channel. The channels can operate with either physical
or virtual addresses.

RAM

Code RAM

A 256 word RAM for control and status bits, and special purpose
logic for supporting and testing the internal CPU.

IOP

Processor

An internal 16 bit processor which controls the internal operation of
the device, the OMA initialization and the buffer management.

ROM

Code ROM

A 3K word ROM storing the internal code.

FIFO

Two 120 byte deep, word-organized, first-in-first-out (FIFO)
memories. One stores data to be transmitted and the other stores
data that has been received.

RXM

Receive Machine

An interface between the serial line and the Receive data FIFO.
The RXM is in charge of the data link layer functions such as
Address recognition and filtering, CRC check framing and packet
decapsulation.

TXM

Transmit machine

An interface between the serial line and Transmit Data FIFO. The
TXM is in charge of the frame generation and CAC generation.

B-1

SGEC internal block diagram

Figure B-1

SGEC Block Diagram

+---------+I

CDAL<31:00> <---->I
_
I
AS <---->I
-I
DS <---->I
I
BM/TEST<3: 0> <---->I
I
WR <---->I
_

I
I
I
I
I

RDY <---->!BUS
__
JINTERFACEI
ERR ----->!UNIT

CS/DP<3:0> <---->I
-

DPE

DMGI ----->I

<-----1

I
I

+-------------+
!OP

+-------------+
I

HPI
BDP
OMA

I
I
I
I

I
I
I

IA.KEO <-----1

---

CSL ----->I

NSGEC

<-----1

TSM

----->I

1
I

IMACHINE I<-- RCLK
I
I

l<--+-->I

I
I
I
I
I I
1--------1
I
I
I
I
I
I 161

I<-- RXEN

+----+---+

+------- CLSN
v

+----+---+

JTRANSMITl<-/--->I

I
I

FIFO

I
I
I

I
I

I
I
I
I

1--> TX

jTRANSMITI

IMACHINE I<-- TCLK
l
I

l<--+-->I

1--> TXEN

+--------+

+--------+
16
!<-----+-----+-----+---------/---------+
I
I
I
Internal IOP
I
I
I
I

I
I

--I
IAKEI ----->!
__
I

IRQ

I
I
v
I +---------+ +---------+
II
II
I I ROM
I I RAM
I I
I I

I I
I I
I
I +---------+ +---------+

+---------+

B-2

1-----/------1----------->I
I
I
I

<---->!
I
DMR <-----1

I
I 16
+--------+
I 16
!RECEIVE l<-/--->I
I<-- RX
l<----/-------------------1 FIFO I
!RECEIVE I

CCTL <-----1

-----

+--------+

bus

" To all

blocks

+------------+

I<----- CLKA

CLOCKS

I
I<----- CLKB
I
I
-I

!<----- RESET

+------------+

n
n c

r
r

Open issues

Table C-1 summarizes the open issues for the pass2 part:
Table C-1

Open issues

Issue

Explanation

Received IEEE frames

Currently, the SGEC ignores the IEEE Data Length field, except when
programmed to strip pad/CRC. An incoming frame whose actual length
does not match the Data Length field is not truncated nor error flagged.
Is. this acceptable?

MOP BOOT message

Should the SGEC detect ttie MOP BOOT message and optionally
trigger a reboot?

Separate Receive and Transmit
interrupts

LANBridge request to expedite processing.

Global VPiX memory addressing

Currently not supported, should it be?

r
r
[j

n
n
n
Iii I

n
n
n
n

C-1