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October 1996

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Document:	SA110 Technical Reference 199610
Order Number:	EC-QPWLC-TE
Revision:
Pages:	78
Original Filename:	http://bitsavers.org/pdf/dec/semiconductor/arm/EC-QPWLC-TE_SA110_Technical_Reference_199610.pdf

OCR Text

Digital Semiconductor

Digital Semiconductor
SA-110 Microprocessor
Technical Reference Manual
L

mamDDID
Digital Semiconductor
SA-11 O Microprocessor
Technical Reference Manual
Order Number: EC-QPWLC-TE

Revision/Update Information:

Digital Equipment Corporation
Maynard, Massachusetts

This is revision C of a preliminary
document. It supersedes the
Digital Semiconductor SA-110
Microprocessor Technical Reference
Manual (EC-QPWLB-TE). This
manual is to be used in conjunction
with ARM Architectural Reference
(EC-QV44A-TE).

October 1996
While Digital believes the information included in this publication is correct as of the date of publication, it is subject to
change without notice.
Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply
the granting of licenses to make, use, or sell equipment or software in accordance with the description.
© Digital Equipment Corporation 1996. All rights reserved.
Printed in U.S.A.
Digital, Digital Semiconductor, and the DIGITAL logo are trademarks of Digital Equipment Corporation.
Digital Semiconductor is a Digital Equipment Corporation business.
ARM and ARM Powered are trademarks of Advanced RISC Machines Ltd.
All other trademarks and registered trademarks are the property of their respective owners.

SA-110 Microprocessor
The Digital Semiconductor SA-110 Microprocessor (SA-110) is the first member of the StrongARM family of highperformance, low-power microprocessors. The SA-110 is an implementation of Advanced RISC Machines Ltd.
(ARM) Version 4 architecture and offers significant advances in microprocessor design. The SA-110 has been
designed to further extend the ARM family as the world's leading source of low-power, high-performance RISC
processors for embedded consumer markets such as portable products and interactive digital video.
The SA-110 is a general-purpose, 32-bit RISC microprocessor with a 16KB instruction cache (Icache); a 16KB
write-back data cache (Dcache); a write buffer; and a memory-management unit (MMU) combined in a single chip.
The five-stage pipeline distributes tasks evenly over time to remove bottlenecks, ensuring high throughput for the core
logic. The SA-110 offers high-level RISC performance, yet it provides minimal power consumption, making it ideal
for portable, low-cost systems.
The SA-110 onchip MMU supports a conventional two-level page-table structure, with a number of extensions, which
makes it ideal for embedded control systems and object-oriented systems. These features result in a high instruction
throughput and impressive real-time response for a small and cost-effective chip.

Features
• High performance
- 115 Dhrystone 2.1 MIPS @100 MHz
- 185 Dhrystone 2.1 MIPS @160 MHz
- 192 Dhrystone 2.1 MIPS @166 MHz
- 230 Dhrystone 2.1 MIPS @200 MHz
- 268 Dhrystone 2.1 MIPS @233 MHz
•Low power (normal mode)
- 130 mW @1.65 V/100 MHz core/27 MHz bus
- 170 mW @ 1.65 V/160 MHz core/33 MHz bus
- 230 mW @ 2.0 V/166 MHz core/33 MHz bus
- 330 mW @ 2.0 V/200 MHz core/50 MHz bus
- 420 mW@ 2.0 V/233 MHz core/66 MHz bus
• Internal phase-locked loop (PLL)
- 3.68 or 3.56 MHz external reference oscillator
• Idle and sleep power-down modes
• Big and little endian operating modes
• 3.3-V 1/0 interface

• 144-pin thin quad flat pack (TQFP)
• 32-way set-associative caches
- 16KB instruction cache
- 16KB write-back data cache
• 32-entry memory-management units
- Maps 4KB, 64KB, or lMB
•Write buffer
- 8 entry 16-bytes each
•Early termination 32-bit multiplier
- 32-bit accumulation - (2-4 cycles)
- 64-bit accumulation - (3-5 cycles)
•Memory bus
- Asynchronous or synchronous
- 0-33 MHz@ 100 MHz
- 0-53 MHz@ 160 MHz
- 0-53 MHz@ 166 MHz
- 0-66 MHz @ 200 MHz
- 0-66 MHz @ 23 3 MHz

Applications
• Portable products
- Personal Digital Assistants (PDAs)
- Smart phones
- Digital cameras
- Organizers
- Bar-code scanners
• Interactive digital media
- Digital set-top devices
- Interactive TV
- Video game players

Preliminary

• Embedded control
- Intemetworking: routers, bridges, LAN switches
- Office automation: printers, scanners, copiers
- Telecommunication: PBX, Cellular Base Station
- Storage peripherals: drive and RAID controllers
- PC add-ins: intelligent I/O cards, LAN/WAN
•Network computers
- Tablet intranet products
- Internet appliances

Digital Equipment Corporation

iii

Table of Contents

Table of Contents
1.0 Introduction .................................................................................................................... 1
1.1 ARM Architecture .................................................................................................... 2
1.1.1 26-BitMode .................................................................................................... 2
1.1.2 Coprocessors ................................................................................................... 2
1.1.3 Memory Management ..................................................................................... 2
1.1.4 Instruction Cache ............................................................................................ 2
1.1.5 Data Cache ...................................................................................................... 2
1.1.6 Write Buffer .................................................................................................... 2
1.2 Block Diagram .......................................................................................................... 3
1.3 Functional Diagram .................................................................................................. 4
2.0 Signal Description .......................................................................................................... 5
3.0 ARM Implementation Options ....................................................................................... 8
3.1 Big and Little Endian ................................................................................................ 8
3.2 Exceptions ................................................................................................................ 8
3.2.1 Reset ................................................................................................................ 9
3.2.2 Abort ............................................................................................................... 9
3.2.3 Vector Summary ........................................................................................... 10
3.2.4 Exception Priorities ....................................................................................... 10
3.2.5 Interrupt Latencies ........................................................................................ 11
3.3 Coprocessors ........................................................................................................... 11
4.0 Instruction Set .............................................................................................................. 12
4.1 Instruction Set ......................................................................................................... 12
4.2 Instruction Timings ................................................................................................ 12
5.0 Configuration ............................................................................................................... 13
5.1 Internal Coprocessor Instructions ........................................................................... 13
5 .2 Registers ................................................................................................................. 14
5.2.1 Register 0 - ID ............................................................................................. 14
5.2.2 Register 1 - Control ...................................................................................... 15
5.2.3 Register 2 - Translation Table Base ............................................................. 16
5.2.4 Register 3 - Domain Access Control.. .......................................................... 16
5.2.5 Register 4 - Reserved ................................................................................... 16
5.2.6 Register 5 - Fault Status ............................................................................... 16
5.2.7 Register 6 - Fault Address ............................................................................ 16
5.2.8 Register 7 - Cache Control Operations ......................................................... 17
5.2.9 Register 8 - TLB Operations ........................................................................ 17
5.2.10 Registers 9 -14 Reserved ........................................................................... 17
5 .2.11 Registers 15 - Test, Clock and Idle Control.. ............................................. 18
5.2.11.1 !cache LFSR Controls ....................................................................... 18
5 .2.11.2 Clock Controls ................................................................................... 18
6.0 Caches and Write Buffer .............................................................................................. 19
6.1 Instruction Cache (!cache) ...................................................................................... 19
6.1.1 !cache Operation ........................................................................................... 19
6.1.2 !cache Validity .............................................................................................. 19
Preliminary

Digital Equipment Corporation

Table of Contents
6.1.2.1 Software Icache Flush .......................................................................... 19
6.1.3 le ache Enable/Disable and Reset .................................................................. 19
6.1.3.1 Enabling the Icache .............................................................................. 19
6.1.3.2 Disabling the !cache ............................................................................ 20
6.2 Data Cache (Dcache) ............................................................................................. 20
6.2.1 Cacheable Bit - C .......................................................................................... 20
6.2.2 Bufferable Bit - B .......................................................................................... 20
6.2.3 Dcache Operation .......................................................................................... 20
6.2.3.1 Cacheable Reads C = 1 ....................................................................... 20
6.2.3.2 Noncacheable Reads C = 0 .............................................................. 20
6.2.4 Dcache Validity ............................................................................................. 21
6.2.4.1 Software Dcache Flush ........................................................................ 21
6.2.4.2 Doubly Mapped Space ......................................................................... 21
6.2.5 Dcache Enable/Disable and Reset.. ............................................................... 21
6.2.5 .1 Enabling the Dcache ............................................................................ 22
6.2.5.2 Disabling the Dcache ........................................................................... 22
6.3 Write Buffer (WB) ................................................................................................. 22
6.3.1 Bufferable Bit. ............................................................................................... 22
6.3.2 Write Buffer Operation ................................................................................. 22
6.3.2.1 Writes to a Bufferable and Cacheable Location (B=l,C=l) ................ 22
6.3.2.2 Writes to Bufferable and Noncacheable Location (B=l,C=O) ............ 22
6.3.2.3 Unbufferable Writes (B=0) .................................................................. 23
6.3.3 Enabling the Write Buffer ............................................................................. 23
6.3.4 Disabling the Write Buffer. ........................................................................... 23
7 .0 Memory Management Unit (MMU) ............................................................................ 24
7 .1 Overview ................................................................................................................ 24
7 .1.1 MMU Registers ............................................................................................. 24
7.2 MMU Faults and CPU Aborts ................................................................................ 24
7 .3 External Aborts ....................................................................................................... 24
7.3.1 Cacheable Reads (Cache Line Fills) ............................................................. 25
7.3.2 Buffered Writes ............................................................................................. 25
7.4 Interaction of the MMU, !cache, Dcache and Write Buffer. .................................. 25
8.0 SA-110 Clocking .......................................................................................................... 27
8.1 SA-110 Operating Modes ....................................................................................... 27
8.2 SA-110 Clocking .................................................................................................... 27
8.2.1 Switching to Idle Mode ................................................................................. 27
8.2.2 Switching to Sleep Mode .............................................................................. 28
8.2.3 Core Clock Configuration - CCCFG ............................................................. 28
8.2.4 Memory Clock Configuration - MCCFG ...................................................... 29
8.2.5 Tester and Debug Clocks .............................................................................. 29
9.0 Bus Interface ................................................................................................................ 30
9.1 Bus Modes .............................................................................................................. 30
9.1.1 Standard and Enhanced Mode ....................................................................... 30
9.2 SA-110 Bus Stalls .................................................................................................. 31
9.3 Cycle <Types ............................................................................................................ 32
9.4 Memory Access ............<.......................................................................................... 32
vi

Digital Equipment Corporation

Preliminary

Table of Contents
9.5 Read/Write .............................................................................................................. 32
9.6 Address Pipeline Enable (APE) .............................................................................. 32
9.7 Memory Access Types ........................................................................................... 33
9.8 External Accesses .............................................................................................. ;.... 34
9.8.1 Unbuffered Writes I Noncacheable Reads .................................................... 34
9.9 Buffered Write ........................................................................................................ 35
9.10 Cache Line Fill ..................................................................................................... 35
9.11 Read-Lock-Write .................................................................................................. 35
9.12 Stalling the Bus ..................................................................................................... 36
9.13 Summary of Transactions ..................................................................................... 37
9.13.1 Read Bursts ................................................................................................. 37
9.13.2 Write Bursts ............................................................................................... 37
9.13.3 Transaction Summary ................................................................................ 37
10.0 Boundary Scan Test Interface .................................................................................... 39
10.1 Overview .............................................................................................................. 39
10.2 Reset ..................................................................................................................... 40
10.3 Pullup Resistors .................................................................................................... 41
10.4 nPWRSLP ............................................................................................................. 41
10.5 Instruction Register .............................................................................................. 41
10.6 Public Instructions ................................................................................................ 41
10.6.1 EXTEST (00000) ........................................................................................ 41
10.6.2 SAMPLE/PRELOAD (00001) .................................................................... 42
10.6.3 CLAMP (00100) ......................................................................................... 42
10.6.4 HIGHZ (00101) ........................................................................................... 42
10.6.5 IDCODE (00110) ........................................................................................ 43
10.6.6 BYPASS (11111) ........................................................................................ 43
10.7 Test Data Registers ............................................................................................... 44
10.7.1 Bypass Register ........................................................................................... 44
10.7.2 SA-110 Device Identification (ID) Code Register ..................................... .45
10.7.3 SA-110 Boundary Scan (BS) Register ....................................................... .45
10.8 Boundary Scan Interface Signals ......................................................................... .46
11.0 de Parameters ............................................................................................................. 51
11.1 Absolute Maximum Ratings ................................................................................. 51
11.2 de Operating Conditions ....................................................................................... 51
11.3 de Characteristics .................................................................................................. 52
11.4 Power Supply Voltages and Currents ................................................................... 52
12.0 ac Parameters ............................................................................................................. 53
12.1 Test Conditions ..................................................................................................... 53
12.2 Module Considerations ......................................................................................... 53
12.3 Main Bus Signals .................................................................................................. 54
12.4 SA-110 ac Parameters .......................................................................................... 56
13.0 Physical Details .......................................................................................................... 62
13 .1 Pin out. ................................................................................................................... 63
Support, Products and Documentation

Preliminary

Digital Equipment Corporation

vii

Figures

Figures
1 SA-110 Block Diagram .................................................................................................... 3
2 Functional Diagram .......................................................................................................... 4
3 Read or Write (One Word) ............................................................................................. 33
4 Sequential Read or Write (Two Word) .......................................................................... 33
5 Two I-Word Nonsequential Reads or Writes Back-to-Back ........................................ 34
6 Cache Line Fill ............................................................................................................... 35
7 Read-Lock-Write ............................................................................................................ 36
8 Using nWAIT to Stop the SA-110 for One MCLK Cycle ............................................. 36
9 Test Access Port (TAP) Controller State Transitions .................................................... 40
10 Boundary Scan Block Diagram .................................................................................... 44
11 Boundary Scan General Timing ................................................................................... 46
12 Boundary Scan Tri-state Timing .................................................................................. 47
13 Boundary Scan Reset Timing ....................................................................................... 47
14 SA-llOMainBusTiming ............................................................................................ 54
15 SA-110 Address Timing with APE=Low .................................................................... 55
16 SA-110 Address Timing with APE=HIGH ................................................................. 55
17 SA-110 144-Pin TQFP Mechanical Dimensions in mm .............................................. 62

viii

Digital Equipment Corporation

Preliminary

Tables

Tables
1 Signal Pin Description ..................................................................................................... 5
2 Vector Summary ........ .. .. .. .. .... ........................ .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . 10
3 Instruction Timings ........................................................................................................ 12
4 Cache & MMU Control Registers ................................................................................. 14
5 Cache Control Operations .............................................................................................. 17
6 TLB Control Operations ................................................................................................ 17
7 Test, Clock, and Idle Controls ...................................................................................... 18
8 Valid MMU, Dcache & Write Buffer Combinations ..................................................... 25
9 CCLK Configurations .................................................................................................... 28
10 MCLK Configurations ................................................................................................. 29
11 Enhanced Mode Wrapping Order ................................................................................ 30
12 Byte Mask .................................................................................................................... 31
13 Cycle Type Encodings ................................................................................................. 32
14 SA-110 Transactions .................................................................................................... 37
15 SA-110 Boundary Scan Interface Timing .................................................................... 48
16 Boundary Scan Signals & Pins .................................................................................... 49
17 SA-110 de Maximum Ratings ...................................................................................... 51
18 SA-110 de Operating Conditions ................................................................................. 51
19 SA-110 de Characteristics ............................................................................................ 52
20 SA-110 Power Supply Voltages and Currents ............................................................. 52
21 SA-110 Output Derating .............................................................................................. 53
22 SA-110 ac for -AA Parts ............................................................................................ 57
23 SA-110 ac for -BA Parts ............................................................................................. 58
24 SA-110 ac for -CA Parts ............................................................................................ 59
25 SA-110 ac for -DA Parts ............................................................................................. 60
26 SA-110 ac for -EA Parts ............................................................................................. 61
27 SA-110 Pin out - 144 pin Thin Quad Flat Pack ........................................................... 63

Preliminary

Digital Equipment Corporation

Introduction
1.0 Introduction
The SA-110 microprocessor (SA-110) is a general purpose 32-bit microprocessor with a 16KB instruction cache, a
16KB writeback data cache, an 8-entry write buffer with 16 bytes per entry, and a memory management unit (MMU)
combined in a single chip. The SA-110 is software compatible with the ARM V4 architecture processor family and
can be used with ARM support chips such as I/O, memory and video.
The onchip caches together with the write buffer substantially raise the average execution speed and reduce the average
amount of memory bandwidth required by the processor. This allows the external memory to support additional
processors or direct memory access (DMA) channels with minimal performance loss.
The instruction set comprises eight basic instruction types:
Two of these make use of the onchip arithmetic logic unit, barrel shifter and multiplier to perform
high-speed operations on the data in a bank of 16 logical (31 physical) registers, each 32 bits wide.
Three classes of instructions control data transfer between memory and the registers, one optimized
for flexibility of addressing, another for rapid context switching and the third for swapping data.
Two instructions control the flow and privilege level of execution.
One class is used to access the privileged state of the machine.
The ARM instruction set is a good target for compilers of many different high-level languages. Assembly code
programming, where required for critical code segments, is also straightforward unlike some RISC processors which
depend on sophisticated compiler technology to manage complicated instruction interdependencies.
The memory interface has been designed to allow the performance potential to be realized without incurring high costs
in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented
in standard low-power logic, and these control signals permit the exploitation of page mode access offered by industry
standard DRAMs.
The SA-110 is a static part and has been designed to run at a reduced voltage to minimize its power requirements. This
makes it ideal for portable applications where both these features are essential.
Document Conventions:

Ox
BOLD
binary

Preliminary

- marks a Hexadecimal quantity
- external signals are shown in bold capital letters
- where it is not clear that a quantity is binary it is followed by the word binary.

Digital Equipment Corporation

Introduction
1.1 ARM Architecture
The SA-110 implements the ARM V4 architecture as defined in the ARM Architecture Reference, Version A,
7 Feb. 1996, with the following options.

1.1.1 26-Bit Mode
The SA-110 supports 26-bit mode but all exceptions are initiated in 32-bit mode. The P and D bits do not affect the
operation of SA-11 O; they always read as a one and writes to them are ignored.

1.1.2 Coprocessors
The SA-110 only supports MCR and MRC access to coprocessor number 15. These instructions are used to access the
memory management, configuration, and cache control registers. All other coprocessor instructions cause an
undefined instruction exception. No support for external coprocessors is provided.

1.1.3 Memory Management
Memory management exceptions preserve the base address registers so no fixup code is required. Separate translation
look aside buffers (TLBs) are implemented for the instruction and data streams. The TLBs each have 32 entries that
can each map a segment, a large page, or a small page. The TLB replacement algorithm is round robin. The data
TLBs support both the flush-all and flush-single-entry operation, while the instruction TLBs only support the flush-all
operation.

1.1.4 Instruction Cache
The SA-110 has a 16KB instruction cache (Icache) with 32-byte blocks and 32-way associativity. The Icacne supports
the flush-all-entry function. Replacement is round robin within a set. The Icache can be enabled while memory
management is disabled. When memory management is disabled all of memory is considered cacheable by the lcache.

1.1.5 Data Cache
SA-110 has a 16KB data cache (Dcache) with 32-byte blocks and 32-way associativity. The Dcache supports the flushall, flush-entry, and copyback-entry functions. The copyback-all function is not supported in hardware. This function
can be provided by software. The cache is read allocate with round-robin replacement.

1.1.6 Write Buffer
The SA-110 has a 8-entry write buffer with each entry able to contain 1 to 16 bytes. The drain-writebuffer operation
is supported.

Digital Equipment Corporation

Preliminary

Introduction
1.2 Block Diagram

ABE A[31:0] CLF MAS nRW LOCK APE

TCK TDI TMS nTRST TDO

Address Buffer

JTAG Test

IMMU

le ache

MSE

PC
nMREQ

StrongARM
Core
DMMU

Dcache

SEQ

Addr
CONFIG
nPWRSLP
ABORT

Write
Buffer

nIRQ

Load/Store Data

nFIQ

nRESET
DBE

D[31:0]

Figure 1: SA-110 Block Diagram

Preliminary

Digital Equipment Corporation

Introduction
-1.3 Functional Diagram

TCK BYP

-,.
TESTCLK __..

SnA
CLK

Clocks.

MCLK
11111

....~

.
....
.

nWAIT
11111

MAS[1:0]
__..

-,.

nRW

..._ nRESET_OUT
.....CCCFG_l_3:QL.

LOCK
CLF

........

MCCFG_[2:0_L.
-,.
SPDF
nlRQ
Interrupts

Power

nFIQ

VDDX

vss
TCK
TOI

JTAG
Test

-....-

_...
...

SA-110

....

-,.

_.._

-,.

..,.....

..._ CON FIG
....-

nPWRSLP

11111

........

_...

nMREQ

..,.....

SEQ

....
........

Bus
Control

ABORT

........
11111

VDD

(

Address
Bus

__..

nMCLK
nRESET

A[31:0]

-,.

TOO
TMS
nTRST

.
..

ABE, DBE
11111

APE
11111

MSE
11111

.
.

1<0(31:0]

Figure 2: Functional Diagram

Digital Equipment Corporation

Preliminary

Signal Description
2.0 Signal Description
Table 1: Signal Pin Description
Name

Type

Description

A[31:0]

ocz

Address Bus. This bus signals the address requested for memory accesses. If APE is high the
address changes while MCLK is high, if APE is low the address changes during the following low period of MCLK. In enhanced bus mode A[l:O] contain byte mask bits two and
three. The byte mask bits are asserted low on reads to indicate the required data. The byte
mask bits are asserted low on writes to signal which bytes of the 32-bit data bus contain data
to be accessed. In standard mode A[l:O] contain the low order two bits of the address. In
both modes A[31:2] contain the upper 30 bits of the byte address.

ABE

Address bus enable. When this input is low, the address bus A[31:0], nRW, MAS[l:O],
CLF, and LOCK are put into a high impedance state (Note 1).

ABORT

External abort. Allows the memory system to tell the processor that a requested access has
failed. Only monitored when the SA-110 is accessing external memory.

APE

Address pipeline enable. This input is used to control the timing of the latches on the address
bus A[31:0], MAS[l:O], nRW, CLF, and LOCK. Normally these signals change during
MCLK high, but they may be held to the next MCLK low by driving APE low. APE is a
static configuration pin and must remain stable at all times.

CCCFG[3:0]

Core Clock Configuration pins. These four pins configure the core clock speed. They must
remain stable at all times.

CLF

ocz

Cache Line Fill. An output signal used by the processor to indicate a cache line fill burst read
or write. The CLF pin is asserted for full 8-word reads and writes. Burst reads are only done
for cache line fills. Burst writes are done for castouts of dirty data and data stores that have
merged in the write buffer. If CONFIG is high, then cache line fetches are wrapped in the
four word subblock and then switched to the other subblock. The CLF signal follows
address bus timing. Note it is NOT asserted for writes in pass one parts.

CLK

The 3.57/3.68 MHZ crystal oscillator input clock for the core PLL. This is the base clock in
from which the high speed core clock and the MCLK in synchronous mode are generated.

CONFIG

The CONFIG input sets the bus mode to standard (low) or enhanced (high). In standard
mode all cache line fetches start at word 0 of the cache block and stores are not allowed to
merge. If CONFIG is high then cache line fetches are wrapped in the four word subblock
then switch to the other subblock starting at the critical word. The write buffer is allowed to
merge stores to the same cache block and will use the A[l:O] and MAS[l:O] pins to present
a byte mask of the bytes being read or written.The CONFIG signal must remain stable at all
times.

D[31:0]

ICOCZ

Data bus. These are bi-directional pins used for data transfers between the processor and
external memory. For read operations (when nRW is low), the input data must be valid
before the falling edge of MCLK. For write operations (when nRW is high), the output data
will become valid while MCLK is low.

DBE

Data bus enable. When this input is low, the data bus, D[31:0] is put into a high impedance
state (Note 1). The drivers will always be high impedance except during write operations,
and DBE must be driven high in systems which do not require the data bus for DMA or similar activities.

Preliminary

Digital Equipment Corporation

Signal Description
Table 1: Signal Pin Description
Name

II Type ,I

_ _ _______ Description ___ _ __ _

LOCK

ocz

Locked operation. LOCK is driven .high, to signal a "locked" memory access sequence, and
the memory manager should wait until LOCK goes low before allowing another device to
access the memory. LOCK changes while MCLK is high artd remains high during the
locked memory sequence. The LOCK signal follows address bus timing.

MAS[l:O]

ocz

Memory access size. An output signal used by the processor in standard bus mode to indicate to the external memory system the number of bytes being transferred. MAS[l:O] is 2 for
word transfers, 1 for halfword transfers, and 0 for byte transfers, and is valid for both read
and write operations. In enhanced mode the MAS pins contain bits zero and one of the byte
mask. The byte mask bits are asserted low on reads to indicate the required data. The byte
masks bits are asserted low on writes to signal which bytes of the 32-bit data bus contain
data to be accessed. The MAS signals follow address bus timing.

MCCFG[2:0]

Memory Clock Configuration pins. These pins configure the system clock speed when SnA
is asserted.They must remain stable at all times and may not be dynamically changed. When
SnA is asserted MCLK is generated by dividing the core clock by the value of MCCFG
plus two (2 .. 9) for MCCFG in the range 0 .. 7.

MCLK

ICOCZ

Memory clock input or output. When SnA is deasserted MCLK is an input clock, when SnA
is asserted MCLK is an output. This clock times all SA-110 memory accesses. The low or
high period of MCLK may be stretched for slow peripherals; alternatively, the nWAIT
input may be used with a free-running MCLK to achieve similar effects.

MSE

Memory request/sequential enable. When this input is low, the nMREQ and SEQ outputs
are put into a high impedance state (Note 1).

nFIQ

Not fast interrupt request. If FIQs are enabled, the processor will respond to a low level on
this input by taking the FIQ interrupt exception. This is an asynchronous, level-sensitive
input, and must be held low until a suitable response is received from the processor.

nIRQ

Not interrupt request. As nFIQ, but with lower priority. This is an asynchronous, level-sensitive input, and must be held low until a suitable response is received from the processor.

nMCLK

ocz

Not memory clock output. When SnA is high, nMCLK is the inverse of MCLK. If SnA is
low then nMCLK is held low. This output can also be disabled by an MCR instruction to
save power if nMCLK is not used.

nMREQ

ocz

Not memory request. A pipelined signal that changes while MCLK is low to indicate
whether or not, in the following cycle, the processor will be accessing external memory.
When nMREQ is low, the processor will be accessing external memory.

nPWRSLP

Power Sleep. When low this puts the SA-110 110 pins into sleep mode. In sleep mode all
outputs are driven low except nMREQ which is driven.high.

nRESET

Not reset. This is a level sensitive input which is used to start the processor from a known
address. A low level will cause the current instruction to terminate abnormally, and the onchip caches, MMU, and write buffer to be disabled. When nRESET is driven high, the processor will re-start from address 0. nRESET must remain low for at least 2 full MCLK
cycles. While nRESET is low the processor will perform idle cycles.

nRESET_OUT

ocz

Not reset out. This signal is asserted when nRESET is asserted and deasserts when the processor has completed resetting. This signal remains asserted until the PLL is stable.

Digital Equipment Corporation

Preliminary

Signal Description
Table 1: Signal Pin Description
Nanw

I T~ I
pe

Description

nRW

ocz

Not read/write. When high this signal indicates a processor write operation; when low, a
read. The nRW signal follows address bus timing.

nTRST

Test interface reset. Note this pin does NOT have an internal pullup resistor. This pin must
be pulsed or driven low to achieve normal device operation, in addition to the normal device
reset (nRESET).

nWAIT

Not wait. When low this allows extra MCLK cycles to be inserted in memory accesses. It
must be asserted low before the rising edge of MCLK to extend the MCLK cycle and is
latched with the rising edge of MCLK. Note this is different than previous ARM processors
that required nWAIT to be asserted for the entire MCLK high time and did not latch
nWAIT.

SEQ

ocz

Sequential address. This signal is the inverse of nMREQ, and is provided for compatibility
with existing ARM memory systems. The signal changes while MCLK is high.

SnA

Synchronous/Not Asynchronous. When SnA is low, MCLK is an input and nMCLK is
driven low. When SnA is high, nMCLK and MCLK are output clocks with the frequency
selected by the MCCFG and CCCFG pins. SnA must remain stable at all times and may
not be dynamically changed.

SPDF

SPDF. The SPDF pin should be tied low. It is for DIGITAL use only.

TCK

Test interface reference Clock. This times all the transfers on the ITAG test interface.

TCK_BYP

Test clock PLL bypass. When TCK_BYP is high, the TESTCLK is used as the core clock
in place of the PLL clock, when low the internal PLL output is used.

TDI

Test interface data input. Note this pin does NOT have an internal pullup resistor.

TDO

ocz

Test interface data output. Note this pin does NOT have an internal pullup resistor.

TESTCLK

Test Clock. TESTCLK is used to provide the core clock when TCK_BYP is high. It should
be tied low if TCK_BYP is low. This clock should never be driven higher than VDD.

TMS

Test interface mode select. Note this pin does NOT have an internal pullup resistor.

VDD

Positive supply for the core. Eight pins are allocated to VDD.

VDDX

Positive supply for the I/O pins. Nine pins are allocated to VDDX.

vss

Ground supply. Eighteen pins are allocated to VSS. The ground plane on the board should be
the same for these pins.

Notes:
1. .When output pads are placed in the high impedance state for long periods, care must be taken to ensure
that they do not float to an undefined logic level, as this can dissipate power, especially in the pads.
2. It must be noted that unless all inputs are driven to the VSS or VDDX, the input circuits will consume
power.
Key to Signal Types:
IC - Input, CMOS threshold
ICOCZ - Input, CMOS threshold, output CMOS levels, tri-stateable
OCZ - Output, CMOS levels, tri-stateable

7
Preliminary

Digital Equipment Corporation

ARM Implementation Options
3.0 ARM Implementation Options
The following sections describe ARM architecture options that are implemented by the SA-110.

3.1 Big and Little Endian
The big endian bit, in the control register, sets whether the SA-110 treats words in memory as being stored in big endian
or little endian format. Memory is viewed as a linear collection of bytes numbered upwards from 0. Bytes 0 to 3 hold
the first stored word, bytes 4 to 7 the second and so on.
In the little endian scheme the lowest numbered byte in a word is considered to be the least significant byte of the word
and the highest numbered byte is the most significant. Byte 0 of the memory system should be connected to data lines
7 through 0 (D[7:0]) in this scheme.
In the big endian scheme the most significant byte of a word is stored at the lowest numbered byte and the least

significant byte is stored at the highest numbered byte. Byte 0 of the memory system should therefore be connected to
data lines 31 through 24 (D[31:24]).
The state of the big endian bit only changes the location of the bytes within a 32-bit word. The accessed bytes are
changed for the load byte, store byte, load halfword, and store halfword instructions only. Instruction fetches and word
load and stores are not changed by the state of the bigend bit.

3.2 Exceptions
Exceptions arise whenever there is a need for the normal flow of program execution to be broken, so that (for example)
the processor can be diverted to handle an interrupt from a peripheral. The processor state just prior to handling the
exception must be preserved so that the original program can be resumed when the exception routine has completed.
Many exceptions may arise at the same time.
The SA-110 handles exceptions by making use of the banked registers to save state. The old PC and CPSR contents
are copied into the appropriate R14 and SPSR and the PC and mode bits in the CPSR bits are forced to a value which
depends on the exception. Interrupt disable flags are set where required to prevent otherwise unmanageable nestings
of exceptions. In the case of a re-entrant interrupt handler, R14 and the SPSR should be saved onto a stack in main
memory before re-enabling the interrupt; when transferring the SPSR register to and from a stack, it is important to
transfer the whole 32 bit value, and not just the flag or control fields.
When multiple exceptions arise simultaneously, a fixed priority determines the order in which they are handled. The
priorities are listed later in this chapter. Most exceptions are fully defined in the ARM Architecture Reference. The
following sections specify the exceptions where the SA-110 implementation differs from the ARM Architecture
Reference.
The SA-110 initiates all exceptions in 32-bit mode. When an exception occurs while the SA-110 is running in 26-bit
mode the SA-110 saves only the PC and CPSR. The PC is saved in R14 and the CPSR is saved in the SPSR of the
exception mode. The 32-bit handler will have to merge the condition codes, the interrupt enables, and the mode from
the SPSR into R14 if a handler wants to run in 26-bit mode.

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Preliminary

ARM Implementation Options
3.2.1 Reset
When the nRESET signal goes low, the SA-110 stops executing instructions, asserts the nRESET_OUT pin, and then
performs idle cycles on the bus.
When nRESET goes high again, the SA-110 does the following:
(1)

Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The values
of the saved PC and CPSR are not defined.

(2)

Forces M[4:0]=10011 (32-bit Supervisor mode) and sets the I and F bits in the CPSR.

(3)

Forces the PC to fetch the next instruction from address OxO

At the end of the reset sequence, the MMU, Icache, Dcache, and write buffer are disabled. Alignment faults are also
disabled, and little endian mode is enabled.

3.2.2 Abort
An abort can be signalled by either the internal memory management unit or from the· external ABORT input pin.
ABORT indicates that the current memory access cannot be completed. For instance, in a virtual memory system the
data corresponding to the current address may have been moved out of memory onto a disk, and considerable processor
activity may be required to recover the data before the access can be performed successfully The SA-110 checks for
ABORT during memory access cycles. When aborted the SA-110 will respond in one of two ways:
( 1)

If the abort occurred during an instruction prefetch (a prefetch abort), the prefetched instruction is marked as
invalid but the abort exception does not occur immediately. If the instruction is not executed, for example as
a result of a branch being taken while it is in the pipeline, no abort will occur. An abort will take place if the
instruction reaches the head of the pipeline and is about to be executed.

(2)

If the abort occurred during a data access (a data abort), the action depends on the instruction type.

(a)

Single data transfer instructions (LDR, STR) will abort with no registers modified.

(b) The swap instruction (SWP) is aborted as though it had not executed, though externally the read access may
take place.
(c) Block data transfer instructions (LDM, STM) abort on the first access that cannot complete. If writeback is
set, the base is NOT updated. If the instruction would normally have overwritten the base with data (for
example, a LDM instruction with the base in the transfer list), the original value in the base register is restored.
When either a prefetch or data abort occurs, the SA-110 performs the following operations:
(1)

Saves the address of the aborted instruction plus 4 (for prefetch aborts) or 8 (for data aborts) in R14_abt; saves
CPSR in SPSR_abt.

(2)

Forces M[4:0]=10111 (Abort mode) and sets the I bit in the CPSR.

(3)

Forces the PC to fetch the next instruction from either address OxOC (prefetch abort) or address OxlO (data
abort).

To return after fixing the reason for the abort, use SUBS PC, Rl 4_abt,#4 (for a prefetch abort) or SUBS PC,R14_abt,#8
(for a data abort). This will restore both the PC and the CPSR and retry the aborted instruction.

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Digital Equipment Corporation

ARM Implementation Options
The abort mechanism allows a demand paged virtual memory system to be implemented when suitable memory
management software is available. The processor is allowed to generate arbitrary addresses, and when the data at an
address is unavailable the MMU signals an abort. The processor traps into system software which must work out the
cause of the abort, make the requested data available, and retry the aborted instruction. The application program needs
no knowledge of the amount of memory available to it, nor is its state in any way affected by the abort.

3.2.3 Vector Summary
Table 2: Vector Summary
Address

Exceptio~

I __ Mode on entry

OxOOOOOOOO

Reset

Supervisor

Ox00000004

Undefined instruction

Undefined

Ox00000008

Software interrupt

Supervisor

OxOOOOOOOC

Abort (prefetch)

Abort

OxOOOOOOlO

Abort (data)

Abort

Ox00000014

not used

Ox00000018

IRQ

OxOOOOOOlC

FIQ

These are byte addresses, and will normally contain a branch instruction pointing to the relevant routine.

3.2.4 Exception Priorities
When multiple exceptions arise at the same time, a fixed priority system determines the order in which they will be
handled:
(1)

Reset (highest priority)

(2)

Data abort

(3)

FIQ

(4)

IRQ

(5)

Prefetch abort

(6)

Undefined Instruction, software interrupt (lowest priority)

Note that not all exceptions can occur at once. Undefined instruction and software interrupt are mutually exclusive
since they each correspond to particular (non-overlapping) decodings of the current instruction.
If a data abort occurs at the same time as a FIQ, and FIQs are enabled (that is, the F flag in the CPSR is clear), the
SA-110 will enter the data abort handler and then immediately proceed to the FIQ vector. A normal return from FIQ
will cause the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to
ensure that the transfer error does not escape detection; the time for this exception entry should be added to worst case
FIQ latency calculations.

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Preliminary

ARM Implementation Options
3.2.5 Interrupt Latencies
Calculating the worst-case interrupt latency for the SA-110 is quite complex (due to the cache, MMU, and write buffer)
and is dependent on the configuration of the whole system.

3.3 Coprocessors
The SA-110 has no external coprocessor bus, so it is not possible to add external coprocessors to this device.
SA-110 uses the internal coprocessor designated #15 for control of the on chip MMU, Caches, and clocks. If a
coprocessor other than #15 is accessed, then the CPU will take the undefined instruction trap. The coprocessor load,
store, and data operation instructions also take the undefined instruction trap.

Preliminary

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Instruction Set
4.0 Instruction Set
4.1 Instruction Set
The SA-110 implements the ARM V4 architecture as defined in the ARM Architecture Reference, Version A,
dated 7 Feb 1996, with previously noted options.

4.2 Instruction Timings
The following table lists the instruction timing for the SA-110. The result delay is the number of cycles the next
sequential instruction would stall if it used the result as an input. The issue cycles is the number of cycles this
instruction takes to issue. For most instructions the result delay is zero and the issue cycles is one. For load and stores
the timing is for cache hits.

Table 3: Instruction Timings
__

~tr~~ g~~~ __

_J__R~~ d~I ___

Data processing shift amount literal

Data processing shift amount from register

Mul or Mul/Add giving 32-bit result

1..3

Mul or MullAdd giving 64-bit result

1..3

Load Single - writeback of base

_Issue c::c1es

Load Single - load data zero extended
Load Single -load data sign extended

Store Single - writeback of base

0
MAX(2, number of registers loaded)

Load Multiple (delay for last register)
Store Multiple - write back of base

Branch or Branch and Link

MCR

MAX(2, number of registers loaded)

MRC

MSR to control

MRS

Swap

Digital Equipment Corporation

Preliminary

Configuration
5.0 Configuration
The operation and configuration of the SA-110 is controlled with coprocessor instructions, configuration pins, and
with the memory management page tables. The coprocessor instructions manipulate on-chip registers which control
the configuration of the cache, write buffer, MMU and a number of other configuration options.
Note:

The gray areas in the register and translation diagrams are reserved and should be programmed 0 for future
compatibility.

5.1 Internal Coprocessor Instructions
The on-chip registers may be read using MRC instructions and written using MCR instructions. These operations are
only allowed in non-user modes and the undefined instruction trap will be taken if accesses are attempted in user mode.
31

I nj
Cond
CRn
CRm
OPC_2

Rd
n

CRn

- ARM condition codes
- SA-110 Register
- Function bits for some MRC/MCR instructions
- Function bits for some MRC/MCR instructions
- ARM Register
- 1 MRC register read
0 MCR register write

Format of Internal Coprocessor Instructions MRC and MCR

Preliminary

Digital Equipment Corporation

Configuration
5.2 Registers
The SA-110 contains registers which control the cache and MMU operation. These registers are accessed using CPRT
instructions to coprocessor #15 with the processor in any privileged mode. Only some of registers 0-15 are valid: the
result of an access to an invalid register is unpredictable.

Table 4: Cache & MMU Control Registers
Register

ID Register

~e~erved

Control

Translation Table Base

Domain Access Control

Reserved

Fault Status

Fault Address

Fault Adress

Reserved

Cache Operations

Reserved

TLB Operations

9..14

Reserved

Test, clock, and Idle

5.2.1 Register 0 - ID
Register 0 is a read-only register that returns the code for this chip: Ox4401Al Ox. The low order four bits of the register
are the chip revision number.
24 23

AlO

Digital Equipment Corporation

I Revision

Preliminary

Configuration
5.2.2 Register 1 - Control
Register 1 is a read/write register containing control bits. All writeable bits in this register are forced low by reset.
31

I ol ol ol ol ol ol ol ol ol ol ol ol ol ol ol ol ol ol ol 1 I ol ol RI sl Bl 111 Ii lwlclAIMI
MBitO
ABit 1
CBit2
WBit3

Enable/disable
0 - on-chip memory management unit disabled
1 - on-chip memory management unit enabled
Address Fault Enable/Disable
0 - alignment fault disabled
1 - alignment fault enabled
Data Cache Enable/Disable
0 - Data cache disabled
I - Data cache enabled
Write buffer Enable/Disable
0 - Write buffer disabled
1 - Write buffer enabled

B Bit 7

Big/Little Endian
0 - Little endian operation
1 - Big endian operation

SBit8

System
This selects the access checks performed by the memory management unit.
See the ARM Architecture Reference for more information.

RBit9

ROM
This selects the access checks performed by the memory management unit.
See the ARM Architecture Reference for more information.

I Bit 12

Instruction Cache Enable/Disable
0 - Instruction cache disabled
1 - Instruction cache enabled

Bit 13..31

Preliminary

Unused
Undefined on Read. Writes ignored.

Digital Equipment Corporation

Configuration
5.2.3 Register 2 - Translation Table Base
Register 2 is a read/write register that holds the base of the currently active level one page table. Bits [13:0] are
undefined on read, ignored on write.
14

Translation Table Base

5.2.4 Register 3 - Domain Access Control
Register 3 is a read/write register that holds the current access control for d.omains 0 to 15.
31

24 23

11
1

5.2.5 Register 4 - Reserved
Register 4 is reserved. Accessing this register has no effect.

5.2.6 Register 5 - Fault Status
Register 5 is a read/write register. Reading this register returns the current contents of the Fault Status Register (FSR).
The FSR is written when a data memory fault occurs or can be written by a MCR to the FSR. It is not updated for a
prefetch fault. See Chapter 7 .0 Memory Management Unit (MMU) for more details. Bits [31 :9) are undefined on read,
ignored on write. Bit 8 is ignored on write and is always returned as zero.
9

j 0 I Domain

Status

5.2.7 Register 6 - Fault Address
Read/Write: Fault Address
Register 6 is a read/write register. Reading this register returns the current contents of the Fault Address Register
(FAR). The FAR is written when a data memory fault occurs with the address of the data fault, or can be written by a
MCR to the FAR.
0

Fault Virtual Address

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Preliminary

Configuration
5.2.8 Register 7 - Cache Control Operations
Register 7 is a write-only register. The CRm and OPC_2 fields are used to encode the cache control operations. All
other values for OPC_2 and CRm are unpredictable.

Table 5: Cache Control Operations
Function

OPC_2

CRm

Data

Flush I+D

ObOOO

ObOl 11

Ignored

Flush I

ObOOO

Ob0101

Ignored

Flush D

ObOOO

ObOl 10

Ignored

Flush D single entry

ObOOl

Ob0110

Virtual Address

Clean D cache entry

ObOOl

Ob1010

Virtual Address

Drain Write Buffer

OblOO

Ob1010

Ignored

5.2.9 Register 8 - TLB Operations
Register 8 is a write-only register. The CRm and OPC_2 fields are used to encode the following TLB flush operations.
All other values for OPC_2 and CRm are unpredictable.

Table 6: TLB Control Operations
_

Function

OPC_2

CRm

Data

Flush I+D

ObOOO

ObOl 11

Ignored

Flush I

ObOOO

Ob0101

Ignored

Flush D

ObOOO

ObOl 10

Ignored

Flush D single entry

ObOOl

Ob0110

Virtual Address

5.2.10 Registers 9 -14 Reserved
The results of accessing any of these registers is unpredictable.

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Configuration
5.2.11 Registers 15 - Test, Clock and Idle Control
Register 15 is a write-only register. The CRm and OPC_2 fields are used to encode the following control operations.
All other values for OPC_2 and CRm are unpredictable.

Table 7: Test, Clock, and Idle Controls
Funl'lion

OPC_ 2

CRm

Enable odd word loading
of !cache LFSR

ObOOl

ObOOOl

Enable even word loading
of !cache LFSR

ObOOl

ObOOlO

Clear !cache LFSR

ObOOl

Ob0100

Move LFSR to R14.Abort

ObOOl

OblOOO

Enable clock switching

Ob010

ObOOOl

Disable clock switching

Ob010

Ob0010

Disable nMCLK output

Ob010

ObOlOO

Wait for interrupt

Ob010

OblOOO

5.2.11.1 Icache LFSR Controls
The OPC_2=1 functions are used to control the Icache linear feedback shift register (LFSR) which is used for
manufacturing tests.

5.2.11.2 Clock Controls
The four OPC_2=2 functions are used to enable and disable DCLK switching, disabling the nMCLK output and
disabling MCLK output and waiting for an interrupt. See Chapter 8.0 SA-110 Clocking for information on their use.

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Preliminary

Caches and Write Buffer
6.0 Caches and Write Buffer
To reduce effective memory access time the SA-110 has an instruction cache, a data cache, and a write buffer. In
general these are transparent to program execution. The following sections describe each of these and give all
necessary programming information,

6.1 Instruction Cache (lcache)
The SA-110 contains a 16KB instruction cache (!cache). The !cache has 512 lines of 32 bytes (8 words), arranged as
a 32-way set-associative cache, and uses the virtual addresses generated by the processor core. The !cache is always
reloaded a line at a time (8 words). It may be enabled or disabled via the SA-110 control register and is disabled by the
nRESET pin. The operation of the cache, when memory management is enabled, is further controlled the Cacheable
or C bit stored in the memory management page table (see Chapter 7.0 Memory Management Unit (MMU).). If
memory management is disabled all addresses are marked as cacheable (C=l). When memory management is enabled
the C bit in each page table entry can disable caching for an area of virtual memory.

6.1.1 Icache Operation
In the SA-110 the !cache will be searched regardless of the state of the C bit, only reads that miss the !cache will be
affected. If, on an !cache miss, the C bit is a one or the MMU is disabled, a cache line fill of 8 words will be performed
and it will be placed in an !cache bank with a round-robin replacement algorithm. If, on a miss, the MMU is enabled
and the C bit is a zero for the given virtual address, an external memory access for a single word will be performed and
the !cache will not be written.The !cache should be enabled as soon as possible after reset for best performance.

6.1.2 lcache Validity
The !cache operates with virtual addresses, so care must be taken to ensure that its contents remain consistent with the
virtual to physical mappings performed by the memory management unit. If the memory mappings are changed, the
!cache validity must be ensured. The !cache is not coherent with stores to memory so programs that write cacheable
instruction locations must ensure the !cache validity. Instruction fetches do not check the write buffer so data must not
only be pushed out of the !cache but the write buffer must also be drained.

6.1.2.1 Software Icache Flush
The entire !cache can be invalidated by writing to the SA-110 cache operations register (Register 7). The cache will
be flushed immediately when the register is written, but note that the following four instruction fetches may come from
the cache before the register is written.

6.1.3 Icache Enable/Disable and Reset
The !cache is automatically disabled and flushed on nRESET. Once enabled, cacheable read accesses will cause lines
to be placed in the !cache. If the !cache is subsequently disabled, no new lines will be placed in the !cache, but the
!cache will still be searched and if the data is found it will be used by the processor. If the data in the !cache must not
be used, then the !cache must be flushed.

6.1.3.1 Enabling the Icache
To enable the !cache set bit 12 in control register. The MMU and !cache may be enabled simultaneously with a single
control register write.

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Caches and Write Buffer
6.1.3.2 Disabling the Icache
To disable the !cache clear bit 12 in control register.

6.2 Data Cache (Dcache)
The SA-110containsa16KB writebackdata cache (Dcache). The Dcachehas 512 lines of32 bytes (8 words), arranged
as a 32-way set-associative cache, and uses the virtual addresses generated by the processor. A line also contains the
physical address the block was fetched from and two dirty bits. There is a dirty bit associated with both the first and
second half of the block. When a store hits in the Dcache the dirty bit associated with it is set. When a block is evicted
from the Dcache the dirty bits are used to decide if all, half, or none of the block will be written back to memory using
the physical address stored with the block. The Dcache is always reloaded a line at a time (8 words). It may be enabled
or disabled via the SA-llO control register and is disabled on nRESET. The operation of the Dcache is further
controlled by the Cacheable or C bit and the Bufferable or B bit stored in the memory management page table (see
Chapter 7.0 Memory Management Unit (MMU).). For this reason, in order to use the Dcache, the MMU must be
enabled. The two functions may however be enabled simultaneously, with a single write to the control register.

6.2.1 Cacheable Bit- C
The cacheable bit determines whether data being read may be placed in the Dcache and used for subsequent read
operations. Typically main memory will be marked as cacheable to improve system performance, and 1/0 space as
noncacheableto stop the data being stored in SA-llO's Dcache. [For example ifthe processor is polling a hardware
flag in 1/0 space, it is important that the processor is forced to read data from the external peripheral, and not a copy
of initial data held in the cache].

6.2.2 Bufferable Bit - B
The bufferable bit does not affect writes that hit in the Dcache. If a store hits in the Dcache the store is assumed to be
bufferable. Writebacks of dirty lines are treated as bufferable writes. See section 6.3 on page 22 for more information
on the B bit.

6.2.3 Dcache Operation
In the SA-110 the Dcache will be searched regardless of the state of the C bit, only reads that miss the Dcache will
check the C bit. The C bit controls loading the Dcache on a miss not checking the Dcache on an access.

6.2.3.1 Cacheable Reads C = 1
A cache line fill of 8 words will be performed and it will be placed in a Dcache bank with a round-robin replacement
algorithm.

6.2.3.2 Noncacheable Reads

C =0

An external memory access will be performed and the Dcache will not be written.
Note: Load Multiples to C=O space do NOT perform a burst read.

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Preliminary

Caches and Write Buffer
6.2.4 Dcache Validity
The Dcache operates with virtual addresses, so care must be taken to ensure that its contents remain consistent with
the virtual to physical mappings performed by the memory management unit. If the memory mappings are changed,
the Dcache validity must be ensured.

6.2.4.1 Software Dcache Flush
SA-110 supports the flush and clean operations on single entries of the Dcache by writes to the cache operations
regsiters. The flush whole cache is also supported. Note that since this is a writeback cache, in order to not lose data,
a flush whole must be preceeded by a sequence of loads to cause the cache to write back any dirty entries. The
following code will cause the Dcache to flush all dirty entries.
;+

;Call:
RO points to the start of a 16384-byte region of readable data used
only for this cache flushing routine. If this area is used for
by other code then 32K must be loaded and the flush MCR is not
not needed.
bl writeBackDcache
;Return:
RO, R 1, R2 trashed
Data cache is clean
writeBackDcache
add
l1
ldr
teq
bne
mer
mov

rl, rO, #16384
r2, [rO], #32
rl, rO
l1
pl5,0,r0,c7,c6,0
pc, rl4

6.2.4.2 Doubly Mapped Space
Since the cache works with virtual addresses, it is assumed that every virtual address maps to a different physical
address. If the same physical location is accessed by more than one virtual address, the cache cannot maintain
consistency, since each virtual address will have a separate entry in the cache, and only one entry will be updated on
a processor write operation. To avoid any cache inconsistencies, doubly-mapped virtual addresses should be marked
as noncacheable.

6.2.5 Dcache Enable/Disable and Reset
The Dcache is automatically disabled and flushed on nRESET. Once enabled, cacheable read accesses will cause lines
to be placed in the cache. If subsequently disabled, no new lines will be placed in the cache, but it will still be searched
and if the data is found it will be used by the processor. Write operations will continue to update the cache, thus
maintaining consistency with the external memory. If the data in the cache must not be used, then the cache must be
flushed.

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Caches and Write Buffer
6.2.5.1 Enabling the Dcache
To enable the Dcache, make sure that the MMU is enabled first by setting bit 0 in Control Register, then enable the
Dcache by setting bit 2 in Control Register. The MMU and Dcache may be enabled simultaneously with a single
control register write.

6.2.5.2 Disabling the Dcache
To disable the Dcache clear bit 2 in Control Register.

6.3 Write Buffer (WB)
The SA-110 write buffer is provided to improve system performance. It can buffer up to eight blocks of data of 1 to
16 bytes, at independent addresses. It may be enabled or disabled via the W bit (bit 3) in the SA-110 control register
and the buffer is disabled and and all entries are marked empty on reset. The operation of the write buffer is further
controlled by the Cacheable or C bit and the Bufferable or B bit, which are stored in the memory management page
tables. For this reason, in order to use the write buffer, the MMU must be enabled. The two functions may however be
enabled simultaneously, with a single write to the control register. For a write to use the write buffer, both the W bit
in the control register, and the B bit in the corresponding page table must be set. It is not possible to abort buffered
writes externally; the abort pin will be ignored.

6.3.1 Bufferable Bit
This bit controls whether a write operation may use the write buffer. Typically main memory will be bufferable and
1/0 space unbufferable.

6.3.2 Write Buffer Qperation
When the CPU performs a store, the Dcache is first checked. If the Dcache hits on the store and the protection for the
location and mode of the store allows the write then the write completes in the cache and the writebuffer is not used.
If the location misses in the Dcache then the translation entry for that address is inspected and the state of the B and C
bits determines which of the three following actions are performed. If the write buffer is disabled via the SA-110
Control Register, writes are treated as if the B bit is a zero.

6.3.2.1 Writes to a Bufferable and Cacheable Location (B=l,C=l)
If the write buffer is enabled and the CONFIG pin is asserted and the processor performs a write to a bufferable and
cacheable location, and the data is in the Dcache, then the data is Written to the Dcache, and the Dcache line is marked
dirty. If a write to a bufferable area misses in the data cache, the data is placed in the write buffer and the CPU
continues execution. When placing the write data into the write buffer if the data is being written to the same 16 byte
aligned area of the previous write then the current write is merged into the same entry in the write buffer. The write
buffer performs the external write some time later. If a write is done and the write buffer is full then the processor is
stalled until there is sufficient space in the buffer. If the CONFIG pin is not asserted then no merging is allowed.

6.3.2.2 Writes to Bufferable and Noncacheable Location (B=l,C=O)
If the write buffer is enabled and the processor performs a write to a bufferable but noncacheable location, and misses
in the data cache, the data is placed in the write buffer and the CPU continues execution. When placing the write data
into the write buffer no merging is allowed and each write takes it own write buffer entry. The write buffer performs
the external write some time later.

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Caches and Write Buffer

Note: the case of a data cache hit for a bufferable but noncacheable location is a system programming bug. In this
case the data is written to the Dcache, and the Dcache line is marked dirty.

6.3.2.3 Unbufferable Writes (B=O)
If the write buffer is disabled or the CPU performs a write to an unbufferable area, the processor is stalled until the
write buffer empties and the write completes externally. This will require several external clock cycles.

6.3.3 Enabling the Write Buffer
To enable the write buffer, ensure the MMU is enabled by setting bit 0 in control register, then enable the write buffer
by setting bit 3 in control register. The MMU and write buffer may be enabled simultaneously with a single write to
the control register.

6.3.4 Disabling the Write Buffer
To disable the write buffer, clear bit 3 in control register. Note that any writes already in the write buffer will complete
normally, but a drain write buffer needs to be done to force all writes out to memory.
Note the write buffer will be used for copybacks from the Dcache even when it is disabled.

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Memory Management Unit (MMU)
7.0 Memory Management Unit (MMU)
7.1 Overview
The SA-110 implements the standard ARM memory management functions using two, 32-entry fully associative
TLBs. One is used for instruction accesses and the other for data accesses. On a TLB miss the translation table
hardware is invoked to retrieve the translation and access permission information. Once retrieved, if the entry maps to
a valid page or section then the information is placed into the TLB. The replacement algorithm in the TLB is round
robin. For an invalid page or section an abort is generated and the entry is not placed in the TLB.

7.1.1 MMU Registers
See section 5.2 on page 14 for a description of the MMU CP15 registers supported by the SA-110.

7.2 MMU Faults and CPU Aborts
The MMU generates four faults:
Alignment Fault
Translation Fault
Domain Fault
Permission Fault
Alignment faults are generated by word loads or stores with the low order two address bits not zero, and by load or
store halfwords with the low order address bit a one. Translation faults are generated by access to pages marked invalid
by the memory management page tables. Domain faults and permission faults are generated by accesses to memory
disallowed by the current mode, domain, and page protection. See ARM Architecture Reference for more information.
In addition, an external abort may be raised on external data accesses.

7 .3 External Aborts
In addition to the MMD-generated aborts, SA-110 has an external abort pin which may be used to flag an error on an
external memory access. However, some accesses aborted in this way are not restartablenot all accesses can be aborted
in this way, so this pin must be used with great care. Writes to memory areas marked as bufferable ignore the external
abort pin.
The following accesses may be aborted and restarted safely. If any of the following are aborted the external access will
cease on the next cycle. In the case of a read-lock-write sequence in which the read aborts, the write will not happen.
Reads
Unbuffered writes
Level One descriptor fetch
Level Two descriptor fetch
Read-lock-write sequence

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Preliminary

Memory Management Unit (MMU)
7.3.1 Cacheable Reads (Cache Line Fills)
A cache line fill may be safely aborted on any word in the transfer. If an abort occurs during the cache line fill then the
cache will be purged, so it will not contain invalid data. It the abort happens before the word that was requested by
the access is returned, the load will be aborted. It the abort happens after the word that was requested by the access is
returned, the load will complete, and the fill will be aborted (but no exception will be generated).

7.3.2 Buffered Writes
Buffered writes cannot be externally aborted. Therefore, the system should be configured such that it does not do
buffered writes to areas of memory which are capable of flagging an external abort.

7.4 Interaction of the MMU, Icache, Dcache and Write Buffer
The MMU, Icache, Dcache, and WB may be enabled/disabled independently. The Icache can be enabled with the
MMU enabled or disabled. However, the Dcache and WB can only be enabled when the MMU is enabled. Because
the write buffer is used to hold dirty copyback cached lines from the Dcache, it must be enabled along with the Dcache.
Therefore only four of the eight combinations of the MMU, Dcache, and WB enables are valid. There are no hardware
interlocks on these restrictions, so invalid combinations will cause undefined results.
Table 8: Valid MMU, Dcache & Write Buffer Combinations

\l~Il

Dcache

I \\

Off

The following procedures must be observed.
To enable the MMU:
(1)
(2)
(3)

Program the translation table base and domain access control registers
Program level 1 and level 2 page tables as required
Enable the MMU by setting bit 0 in the control register.

Note:
Care must be taken if the translated address differs from the untranslated address as the three instructions following
the enabling of the MMU may have been fetched using "flat translation" and enabling the MMU may be considered
as a branch with delayed execution. A similar situation occurs when the MMU is disabled. Consider the following code
sequence:

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Memory Management Unit (MMU)
MOY
MCR
Fetch Flat
Fetch Flat
Fetch Flat
Fetch Translated

Rl, #Oxl
15,0,Rl,O,O

;Enable MMD

To disable the MMU
(1)
(2)
(3)
(4)

Disable the WB by clearing bit 3 in the control register.
Disable the Dcache by clearing bit 2 in the control register.
Disable the !cache by clearing bit 12 in the control register.
Disable the MMU by clearing bit 0 in the control register.

Note:

If the MMU is enabled, then disabled and subsequently re-enabled the contents of the TLB will have been preserved.
If these are now invalid, the TLB should be flushed before re-enabling the MMU.
Disabling of all three functions may be done simultaneously.

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Preliminary

SA-110 Clocking
8.0 SA-110 Clocking
8.1 SA-110 Operating Modes
The SA-110 supports three operating modes, normal, idle, and sleep. The SA-110 can be switched between the three
operating modes to minimize power consumption. In normal mode the chip executes instructions. In idle mode no
instructions are executed but the internal phase-locked loop (PLL) continues to run. In sleep mode the core power
(VDD) is switched off; the chip does not execute instructions, and the PLL does not run. The 1/0 power, VDDX, is
used to hold the all output pins that are enabled at a low state except nMREQ which is held at a high state.

8.2 SA-110 Clocking
The SA-110 receives a 3.57/3.68-MHz clock (CLK) from a crystal-based clock generator on the CLK pin and uses
an internal PLL to lock to the input clock and multiply the frequency by a variable multiplier to produce a high-speed
core clock (CCLK). The 3.57/3.68-MHz oscillator and PLL run constantly in normal and idle modes. There are two
clocking domains in SA-110; the core logic domain clocked by DCLK and the bus interface domain clocked by
MCLK. The core clock, DCLK, switches between being driven by the high-speed core clock, CCLK and the bus
clock, MCLK. CCLK is used except when SA-110 is waiting for fills to complete after a cache miss.
At RESET, clock switching is disabled and the DCLK is driven from MCLK. The time from the deassertion of the
nRESET (and the nPWRSLP) pin until the chip comes out of reset (and nRESET_OUT deasserts) is about 150 µsecs
and is asynchronous (to MCLK). The clock switching can also be disabled by writing to the CP15 register 15 with
OPC_2=2 and CRm=2. Clock switching is enabled by writing to the CP15 register 15 with OPC_2=2 and CRm=l.
Disabling switching only disables switching for DCLK, it does not force the DCLK to MCLK. To force DCLK to
be driven by MCLK after disabling switching, force an instruction or data cache miss.
The SA-110 can be configured to either source or sink the MCLK pin. If SnA is deasserted, MCLK is an input to the
SA-110. If SnA is asserted the SA-110 drives the MCLK pin with clock generated by dividing CCLK by 2 to 9 as
specified by the MCCFG pins. The SA-110 synchronizes signals which cross between the CCLK and MCLK
domains. The SnA pin should be programmed by connecting it to VDDX or VSS and should not change. With SnA
asserted nMCLK, an inverted copy of MCLK is also provided. It is enabled at reset and can be disabled by writing
to the CP15 register 15 with OPC_2=2 and CRm=4 to save power if it is not used. If SnA is a 1 then MCLK and
nMCLK start clocking about 10 µsecs before the nRESET_OUT deasserts. If SnA is deasserted the nMCLK pin is
held high. The only difference between running with SnA asserted or deasserted is that MCLK is driven into or out of
the SA-110. The SnA mode is intended to provide a low-cost system clock. For the highest performance systems an
external clock generator may be a better choice.

8.2.1 Switching to Idle Mode
With SnA deasserted, idle mode is entered by disabling clock switching and then doing a load from a noncacheable
location (C=O ). The external driver of MCLK should then stop MCLK to stop the SA-110 from executing
instructions. To resume normal operation MCLK is restarted and clock switching is enabled.
With SnA asserted, idle mode is entered by disabling clock switching, then doing a load from a noncacheable location
(C=O), and then doing a wait for interrupt instruction. The SA-110 stops driving MCLK when it is low and holds
MCLK low. Asserting either nFIQ or nIRQ will cause MCLK to start clocking again. To resume normal operation,
reenable clock switching.

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SA-110 Clocking
8.2.2 Switching to Sleep Mode
To enter sleep mode first assert nRESET for at least 20 ns and then assert nPWRSLP, then switch off the VDD power
(drive VDD to 0 volts). To exit sleep mode restore the VDD supply and deassert nRESET and nPWRSLP. The order
of deassertion of nRESET and nPWRSLP does not matter. Note there is no difference between initial reset and
leaving sleep mode.

8.2.3 Core Clock Configuration - CCCFG
The high speed core clock frequency is configured at reset by the four core clock configuration pins (CCCFG[3:0]).
These pins should be programmed by connecting them to VDDX or VSS and should not change .
Table 9: CCLK Configurations

CCCFC
'
-

CCLK FrequenQ in MHz
(3.57 l\lHz Input)

CCLK Frequenc~ in l\lHz
(3.68 MHz Input)

I
I

85.7

88.3

92.7

95.6

96.4

99.4

103.5

106.7

139.2

143.5

146.4

150.9

157.1

161.9

164.2

169.3

185.6

191.3

196.3

202.4

207.0

213.4

221.3

228.1

235.5

242.8

249.9

257.6

267.8

276.0

278.4

287.0

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Preliminary

SA-110 Clocking
8.2.4 Memory Clock Configuration - MCCFG
If SnA is asserted then the MCLK frequency is selected by the three memory clock configuration pins

(MCCFG[2:0]). These pins should be programmed by connecting them to VDDX or VSS and should not change. The
following table gives the MCLK divisors as a function of the MCCFG pins. With SnA asserted , MCLK is a 50%
duty cycle clock . The nominal frequency is the CCLK frequency divided by the selected divisor. With SnA asserted,
the low and high period of MCLK is generated at ±5% of the nominal frequency short term and at the error of the
crystal oscillator long term.
Note: Some combinations of MCCFG and CCCFG settings will produce an MCLK output that exceeds the
maximum supported MCLK frequency.
Note: For pass one parts, an odd divisor n with a CCLK cycle time of Tcycle will produce an MCLK with a high time
ofTcycle*(n-1)/2 and a low time ofTcycle*(n+2)/2.

Table 10: MCLK Configurations
l\JlTFG

l~C.LK

cln 1sor

,
I

8.2.5 Tester and Debug Clocks
If TCK_BYP is high then the PLL ouput is not used and the high speed core clock is supplied externally on the

TESTCLK pin. This mode is for testing use only and not supported for standard operation. There are important
restrictions on use of TESTCLK which must be observed to avoid permanent damage to the chip. Casual use of
TESTCLK is strongly discouraged.

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Bus Interface
9.0 Bus Interface
The following chapter describes the external bus interface for SA-110.

9.1 Bus Modes
The SA-110 bus has two modes, standard and enhanced. When in enhanced mode data cache line fills are wrapped to
provide the critical word first, and the write buffer allows more generalized merging. The CONFIG signal is asserted
(=1) for enhanced mode and deasserted (=0) for standard mode. The CONFIG signal can only change while nRESET
is asserted.

9.1.1 Standard and Enhanced Mode
In enhanced mode line fills are performed with the critical word first. The burst read is wrapped at the end of the
4-word cache subblock, then the other subblock is accessed in the same order. In standard mode, line fills are started
on cache block word 0 so no wrap is needed. The byte mask is presented on the A[l:O] and MAS[l:O] pins and the
byte mask bits are asserted low on reads to indicate the required data.
Note: This matches current SSRAMs, burst mode EDO DRAMs, and SDRAMs.

Table 11: Enhanced Mode Wrapping Order

Miss Address
Bits f4:2]
'

v·11 () d .
rl
r e1
-

0, 1,2,3,4,5,6, 7

1,2,3,0,5,6,7,4

2,3,0,1,6,7,4,5

3,0,l,2,7,4,5,6

4,5,6,7,0,1,2,3

5,6,7,4,1,2,3,0

6,7,4,5,2,3,0,l

7,4,5,6,3,0,1,2

In enhanced mode, the write buffer is allowed to merge random byte, halfword, and word stores. On each bus cycle
the word address is specified on the A[31:2] pins and the bytes to be read/written are specified by a byte mask. The
byte mask bits [3:0] specify that bytes [3:0] of the data bus are being transferred. The byte mask is presented on the
A[l:O] and MAS[l:O] pins and is asserted low.

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Bus Interface

Table 12: Byte Mask
Byte Mask
Pins

Dbus
Bytes

11
I

A[l]

D[31:24]

A[O]

D[23:16

MAS[l]

D[15:8]

MAS[O]

D[7:0]

In standard mode the write buffer will only merge stores from store multiple instructions and castouts. In standard
mode a MAS[l:O] of 2 is for word, 1 is for halfword, 0 is for byte. The full byte address of the transfer is given by
A[31:0]
Read data must always be returned on the correct byte of the data bus D[31:0]. The chip provides write data on the
data bus bytes specified by the byte mask in Enhanced mode or by the low order two address bits and the memory
access size in Standard more.
Note: Unlike previous ARM chips the SA-110 does not replicate byte stores to all four bytes of the data bus.

9.2 SA-110 Bus Stalls
The bus interface is controlled by MCLK, and all timing parameters are referenced with respect to this clock. The way
the bus is stalled depends on the mode of the bus. If the system is providing MCLK (SnA=O), the bus is stalled in one
of two ways.
1)

The low or high phases of the clock may be stretched

nWAIT can be used to insert entire MCLK cycles into the access. When low, this signal maintains the low
phase of the cycle by gating out MCLK internally. The signal nWAIT is asserted before the rising edge of
MCLK and latch by the SA-110.

If the SA-110 is providing MCLK (SnA= 1), only then WAIT signal can be used to stall the bus with the same timing
as with SnA=O.

The ABORT input is not sampled during clock cycles where nWAIT is stalling the bus.

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Bus Interface
9.3 Cycle Types
There are two cycle types performed by the SA-110. These are idle cycles and sequential cycles. Idle and sequential
cycles are combined to perform memory accesses. The two cycle types are differentiated by nMREQ. The SEQ signal
is the inverse of nMREQ and is provided for compatibility with earlier memory controllers. nMREQ and SEQ are
pipelined, and so their value determines what type the following cycle will be nMREQ and SEQ become valid during
the low phase of the cycle before the one to which they refer. The following table shows the encoding used to generate
the idle and sequential cycles.
Table 13: Cycle Type Encodings

Sequential

Idle

The address from the SA-110 becomes valid during the high phase of MCLK, but can be delayed by using APE. It is
also pipelined, and its value refers to the following memory access.

9.4 Memory Access
There are two types of memory access. These are non-sequential and sequential. The non-sequential cycles occur
when a new memory access takes place. Sequential cycles occur when the cycle is of the same type as, and the address
is 1 word (4 bytes) greater than, the previous access or during cache line fills. Cache line fill cycles occur in response
to a cache miss and the address sequence is given above. Burst reads are only done for cache line fills. Burst writes are
done for castouts of dirty data and data stores that have merged in the write buffer. Cache line fills have the CLF high
and use the defined wrapping order but otherwise are the same as sequential cycles. CLF has the same timing as the
address.
Non-sequential accesses consist of an idle cycle followed by a sequential cycle, sequential accesses consist simply of
a sequential cycle.

9.5 Read/Write
Memory accesses may be read or write, differentiated by the signal nRW. This signal has the same timing as the
address. In the case of a write, the SA-110 outputs data on the data bus during the memory cycle. They become valid
during MCLK low, and are held until the end of the cycle. In the case of a read, the data is sampled at the end of the
memory cycle. nRW may not change during a sequential or cache line fill access, so if a read from address A is
followed immediately by a write to address (A+4), then the write to address (A+4) would be a non-sequential access.

9.6 Address Pipeline Enable (APE)
APE is used to control the timing of the address signals including A[31:0], MAS[l:O], nRW, CLF, and LOCK.
Normally these signals change during MCLK high, but they may be held to the next MCLK low if APE is low. APE
is a static configuration pin and must remain stable at all times. The rest of this chapter assumes APE is high. If APE
is low the address will be held a MCLK phase longer and be driven an MCLK phase later.

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Bus Interface
9.7 Memory Access Types
The following timing diagrams assume APE is high and are only included to demonstrate timing relationships.
Figure 3 shows a 1-word read or write memory access. Figure 4 shows a 2-word sequential access. Figure 5 shows two
1-word accesses back-to-back. Notice that an idle cycle followed by a sequential cycle distinguishes a nonsequential
access.
Cycle Type

Idle

Seq

Idle

MCLK

A[31:0]
MAS,CLF
nRW
nMREQ
SEQ
D[31 :O]
WRITE
D[31 :O]
READ

Figure 3: Read or Write (One Word)

Cycle

Idle

Seq

Idle

MCLK
A[31 :O]
MAS,CLF
nMREQ
SEQ

_ _ __J

nRW

0[31 :O]
WRITE

-----~

D[31:0]
READ

--------c

=><~-

Figure 4: Sequential Read or Write (Two Word)

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Bus Interface

Cycle

Idle

Seq

Idle

Seq

MCLK
A[31 :O]
MAS,CLF

nMREQ
SEQ
nRW
0[31 :O]
WRITE
0[31 :O]
READ

Figure 5: Two 1-Word Nonsequential Reads or Writes Back-to-Back
Note that the data bus is piped one cycle after the address bus. This means that for a read following a write, the data
bus is not tristated by the processor until the falling edge of MCLK in the SEQ cycle of the READ. Notice that the
asserting n WAIT will extend the time the processor is driving the data bus.

9.8 External Accesses
The SA-110 performs bus access for many different operations. All are constructed by combinations of non-sequential
or sequential accesses. There may be any number of idle cycles between two other memory accesses. If a memory
access is followed by an idle period on the bus (as opposed to another non-sequential access), then the address A[31:0],
and the signals nRW and DL[l:O] will remain at their previous value in order to avoid unnecessary bus transitions.
The accesses performed by a SA-110 are:
Unbuffered Write

Level 1 translation fetch

Uncached Read

Level 2 translation fetch

Buffered Write

Cache Line Copyback

Cache line fill

Read-Lock-Write sequence

9.8.1 Unbuffered Writes I Noncacheable Reads
Unbuffered writes and noncacheable reads are the most basic access types. Each may consist of a single access. The
cycles always reflect the type (read or write) of the instruction requesting the cycle. Level 1 and 2 translation fetches
also generate noncacheable reads.

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Bus Interface
9.9 Buffered Write
Buffered writes can consist of sequential or nonsequential accesses. Note, if in enhanced mode, that if several write
accesses are stored concurrently within the write buffer, then each access on the bus will start with a nonsequential
access. If several write accesses occur to the same cache subblock, the SA-110 will merge these in the write buffer
and write to memory using several sequential accesses with the byte masks indicating the valid byte lanes. Burst writes
are done for castouts of dirty data and data stores that have merged in the write buffer. Cache line copybacks are also
buffered writes.

9.10 Cache Line Fill
This access appears on the bus as a nonsequential access followed by sequential accesses. Cache line fills are not
required to start on an 8-word boundary and will be 8 words long. The first access will fetch the critical word if the
bus is in enhanced mode or word 0 if in standard mode. CLF will be high for line fetches. The following diagram is
a cache line fill in enhanced mode. If it was in standard mode the fill would have started at location OxOO rather than
location Ox 18.

Cycle

Idle

Seq

X a=Ox1 o X <ii=Ox14

~=Oxoa

Seq

MCLK
A[31 :O]
MAS,CLF

_ _ _ __,X'-_a_=O_x_1a
_ _ _~X a=Ox1 c

nMREQ
SEQ
nRW
CLF
0[31 :O]

READ

Figure 6: Cache Line Fill

9.11 Read-Lock-Write
The read-lock-write sequence is generated by an SWP instruction to a noncacheable/nonbufferable location. On the
bus it consists of a single word read access followed by a single word write access to the same address, and both are
treated as non-sequential accesses. The cycle is differentiated by the LOCK signal. LOCK has the timing of address,
ie it goes high in the high phase of MCLK at the start of the read access. However, it always goes low at the end of
the write access, even if the following cycle is an idle cycle (unless of course the following access was a read-lockwrite sequence). There may be several idle cycles between the read and the write. Note that for a cacheable/bufferable
access the two access are done in the data cache, preceeded by a cache line fill if needed.

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Bus Interface

MCLK
A[31 :O]
MAS,CLF
nMREQ
SEQ
LOCK
nRW
0[31 :O]

Figure 7: Read-Lock-Write

9.12 Stalling the Bus
The SA-110 can be stalled by nWAIT, as shown for a load in Figure 8. The following diagram shows part of a load
request that has been stalled for one cycle waiting for return data on the third word.

MCLK
A[31 :O]
MAS,CLF

x~----~X , a+4 X~,___a_+_s----~X__,i__
a

nMREQ
SEQ
nWAIT
0[31 :O]
READ

Figure 8: Using nWAIT to Stop the SA-110 for One MCLK Cycle
The SA-110 samples the n WAIT signal pin at time A. The signal n WAIT must meet setup and hold requirements
with respect to the rising edge of MCLK at A. Without the stall cycle, the data would have been sampled at time B.
Inserting a single stall cycle causes the data to be sampled at time C.

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Bus Interface
9.13 Summary of Transactions
The SA-110 will only generate a subset of all possible transactions on the bus. The SA-110 will generate only single
nonsequential transactions and bursts described in the following sections.

9.13.1 Read Bursts
The only actions that cause read bursts are cache line fills. All other reads will be single nonsequential accesses. All
cache line fills are 8 words long.

9.13.2 Write Bursts
In standard mode write bursts are caused by STM to B=l locations and castouts of the data cache. Because the data
cache keeps a dirty bit for each 16-byte subblock in standard mode, write bursts are either 4 or 8 words long. In
enhanced mode, the write buffer will merge random writes. The write burst sizes in enhanced mode are 2, 3, 4, or 8
words. The CLF bit is set on stores. The CLF signal is asserted on stores for all 32-byte write bursts. Note that pass
one parts never assert CLF on writes. When CLF is asserted, the external memory system does not need to wait until
the byte mask information is valid during write bursts. Optimization is aided because all byte lanes will be valid.

9.13.3 Transaction Summary
The following table lists all the transactions that the SA-110 can generate. No burst will cross an aligned 32-byte
boundary.
Table 14: SA-110 Transactions

Bus Operation

I CONFIG

I I
Burst
Size

Starting
Address
Bits l4:21

Note

Read single

0or1

Any

Read burst

Generated by cache line
fills. CLF is asserted.

Read burst

Any

Generated by cache line
fills. CLF is asserted.

Write single

Any

Write single

Any

1. .4 bytes are written as

specified by the byte mask.
Write burst

0, 1, 2
4,5,6

All 8 bytes are written.

Write burst

0, 1
4,5

All 12 bytes are written.

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Bus Interface
Table 14: SA-110 Transactions

Write burst

0
4

All 16 bytes are written

Write burst

0, 1, 2
4,5,6

Each word can have one to
four bytes written

Write burst

0, 1
4,5

The first and last word can
have one to four bytes written. The middle word can
have zero to four bytes
written

Write burst

0
4

The first and last word can
have one to four bytes written. The middle words can
have zero to four bytes
written

Write burst

Oor 1

CLF is asserted and all 32
bytes are written

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Boundary Scan Test Interface
10.0 Boundary Scan Test Interface
The boundary-scan interface conforms to the IEEE Std. 1149.1 - 1990, Standard Test Access Port and Boundary-Scan
Architecture (please refer to this standard for an explanation of the terms used in this section and for a description of
the TAP controller states.) The SA-110 only supports JTAG continuity testing.

10.1 Overview
The boundary-scan interface provides a means of driving and sampling all the external pins of the device irrespective
of the core state. This function permits testing of both the device's electrical connections to the circuit board, and (in
conjunction with other devices on the circuit board having a similar interface) testing the integrity of the circuit board
connections between devices. The interface intercepts all external connections within the device, and each such cell is
then connected together to form a serial register (the boundary scan register). The whole interface is controlled via
five dedicated pins: TDI, TMS, TCK, nTRST and TDO. Figure 9: Test Access Port (TAP) Controller State
Transitions shows the state transitions that occur in the TAP controller.

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Boundary Scan Test Interface

Test-Logic Reset
tms=1
tms=1
Select-DR-Scan

Select-IA-Scan

tms=O

Capture-DR

Capture-IA

tms=1

tms=O

tms=O
Exit2-DR

Exit2-IR

tms=1

Update-DR
tms=1

Update-IA
tms=O

tms=1

tms=O

Figure 9: Test Access Port (TAP) Controller State Transitions

10.2 Reset
The boundary-scan interface includes a state-machine controller (the TAP controller). In order to force the TAP
controller into the correct state after power-up of the device, a reset pulse must be applied to the nTRST pin. If the
boundary scan interface is to be used, then nTRST must be driven low, and then high again. If the boundary scan
interface is not to be used, then the nTRST pin may be tied permanently low. Note that a clock on TCK is not
necessary to reset the device.
The action of reset (either a pulse or a DC level) is as follows:
System mode is selected (the boundary scan chain does NOT intercept any of the signals passing between the
pads and the core).
IDcode mode is selected. If TCK is pulsed, the contents of the ID register will be clocked out of TDO.

Digital Equipment Corporation

Preliminary

Boundary Scan Test Interface
10.3 Pullup Resistors
The IEEE 1149.1 standard effectively requires that TDI, nTRST and TMS should have internal pullup resistors. In
order to minimise static current draw, nTRST has an internal pulldown resistor. These four pins can be left
unconnected for normal operation and overdriven to use the JT AG features.

10.4 nPWRSLP
The nPWRSLP input pin is not sampled by the JT AG interface and must be deasserted to use the JTAG interface. The
TDO pin is tristated when nPWRSLP is asserted.

10.5 Instruction Register
The instruction register is 5 bits in length.
There is no parity bit. The fixed value loaded into the instruction register during the CAPTURE-IR controller state is:
00001.

10.6 Public Instructions
The following public instructions are supported:

Instruction

Binary Code

EXTEST
SAMPLE/PRELOAD
CLAMP
HIGHZ
IDCODE
BYPASS

00000
00001
00100
00101
00110
11111

Private

00010, 00011, 00111, 01000-01111, 10000-11110

In the descriptions that follow, TDI and TMS are sampled on the rising edge of TCK and all output transitions on
TDO occur as a result of the falling edge of TCK.

10.6.1 EXTEST (00000)
The boundary scan (BS) register is placed in test mode by the EXTEST instruction.
The EXTEST instruction connects the BS register between TDI and TDO.
When the instruction register is loaded with the EXTEST instruction, all the boundary-scan cells are placed in their
test mode of operation.

Preliminary

Digital Equipment Corporation

Boundary Scan Test Interface
In the CAPTURE-DR state, inputs from the system pins and outputs from the boundary-scan output cells to the system
pins are captured by the boundary-scan cells. In the SHIFT-DR state, the previously captured test data is shifted out of
the BS register via the TDO pin, while new test data is shifted in via the TDI pin to the BS register parallel input latch.
In the UPDATE-DR state, the new test data is transferred into the BS register parallel output latch. Note that this data
is applied immediately to the system logic and system pins.

10.6.2 SAMPLE/PRELOAD (00001)
The BS register is placed in normal (system) mode by the SAMPLE/PRELOAD instruction.
The SAMPLE/PRELOAD instruction connects the BS register between TDI and TDO.
When the instruction register is loaded with the SAMPLE/PRELOAD instruction, all the boundary-scan cells are
placed in their normal system mode of operation.
In the CAPTURE-DR state, a snapshot of the signals at the boundary-scan cells is taken on the rising edge of TCK.
Normal system operation is unaffected. In the SHIFT-DR state, the sampled test data is shifted out of the BS register
via the TDO pin, while new data is shifted in via the TDI pin to preload the BS register parallel input latch. In the
UPDATE-DR state, the preloaded data is transferred into the BS register parallel output latch. Note that this data is not
applied to the system logic or system pins while the SAMPLE/PRELOAD instruction is active. This instruction should
be used to preload the boundary-scan register with known data prior to selecting EXTEST instructions (see the table
below for appropriate guard values to be used for each boundary-scan cell).

10.6.3 CLAMP (00100)
The CLAMP instruction connects a 1 bit shift register (the BYPASS register) between TDI and TDO.
When the CLAMP instruction is loaded into the instruction register, the state of all output signals is defined by the
values previously loaded into the boundary-scan register. A guarding pattern (specified for this device at the end of
this section) should be pre-loaded into the boundary-scan register using the SAMPLE/PRELOAD instruction prior to
selecting the CLAMP instruction.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test data is shifted into
the bypass register via TDI and out via TDO after a delay of one TCK cycle. Note that the first bit shifted out will be
a zero. The bypass register is not affected in the UPDATE-DR state.

10.6.4 HIGHZ (00101)
The HIGHZ instruction connects a 1 bit shift register (the BYPASS register) between TDI and TDO.
When the HIGHZ instruction is loaded into the instruction register, all outputs are placed in an inactive drive state.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test data is shifted into
the bypass register via TDI and out via TDO after a delay of one TCK cycle. Note that the first bit shifted out will be
a zero. The bypass register is not affected in the UPDATE-DR state.

Digital Equipment Corporation

Preliminary

Boundary Scan Test Interface
10.6.5 IDCODE (00110)
The IDCODE instruction connects the device identification register (or ID register) between TDI and TDO. The ID
register is a 32-bit register that allows the manufacturer, part number and version of a component to be determined
through the TAP.
When the instruction register is loaded with the IDCODE instruction, all the boundary-scan cells are placed in their
normal (system) mode of operation.
In the CAPTURE-DR state, the device identification code (specified at the end of this section) is captured by the ID
register. In the SHIFT-DR state, the previously captured device identification code is shifted out of the ID register via
the TDO pin, while data is shifted in via the TDI pin into the ID register. In the UPDATE-DR state, the ID register is
unaffected.

10.6.6 BYPASS (11111)
The BYPASS instruction connects a 1 bit shift register (the BYPASS register) between TDI and TDO.
When the BYPASS instruction is loaded into the instruction register, all the boundary-scan cells are placed in their
normal (system) mode of operation. This instruction has no effect on the system pins.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test data is shifted into
the bypass register via TDI and out via TDO after a delay of one TCK cycle. Note that the first bit shifted out will be
a zero. The bypass register is not affected in the UPDATE-DR state.

Preliminary

Digital Equipment Corporation

Boundary Scan Test Interface
10.7 Test Data Registers
Figure 10 illustrates the structure of the boundary scan logic.

BSINENCELL
BS IN CELL

BSINCELL

SA-110
Core Logic

)

1---1>-- BSOUTCELL

I/O
Cell

BSOUTNENCELL

Device ID Register

Bypass Register

TDO
Instruction Decoder

TDI

Instruction Register

TMS
TCK

TAP
Controller

nTDOEN

Figure 10: Boundary Scan Block Diagram

10.7.1 Bypass Register
Purpose: This is a single bit register which can be selected as the path between TDI and TDO to allow the device to
be bypassed during boundary-scan testing.
Length: 1 bit
Operating Mode: When the BYPASS instruction is the current instruction in the instruction register, serial data is
transferred from TDI to TDO in the SHIFT-DR state with a delay of one TCK cycle.

Digital Equipment Corporation

Preliminary

Boundary Scan Test Interface

There is no parallel output from the bypass register.
A logic 0 is loaded from the parallel input of the bypass register in the CAPTURE-DR state.

10.7.2 SA-110 Device Identification (ID) Code Register
Purpose: This register is used to read the 32-bit device identification code. No programmable supplementary
identification code is provided.
Length: 32 bits
The format of the ID register is as follows:
31

Version

Part Number

JEDECCode

The high order four bits of the ID register are the version and bits 27 .. 0 are Ox102C06B.
Operating Mode: When the IDCODE instruction is current, the ID register is selected as the serial path between TDI
andTDO.
There is no parallel output from the ID register.
The 32-bit device identification code is loaded into the ID register from its parallel inputs during the CAPTURE-DR
state.

10.7.3 SA-110 Boundary Scan (BS) Register
Purpose: The BS register consists of a serially connected set of cells around the periphery of the device, at the interface
between the core logic and the system input/output pads. This register can be used to isolate the pins from the core
logic and then drive or monitor the system pins.
Operating modes: The BS register is selected as the register to be connected between TDI and TDO only during the
SAMPLE/PRELOAD, and EXTEST instructions. Values in the BS register are used, but are not changed, during the
CLAMP instruction.
In the normal (system) mode of operation, straight-through connections between the core logic and pins are maintained
and normal system operation is unaffected.
In TEST mode (when EXTEST is the currently selected instruction), values can be applied to the output pins
independently of the actual values on the input pins and core logic outputs. On the SA-110 all of the boundary scan
cells include an update register and thus all of the pins can be controlled in the above manner. An additional boundaryscan cell is interposed in the scan chain in order to control the enabling of the data bus.

Preliminary

Digital Equipment Corporation

Boundary Scan Test Interface
The correspondence between boundary-scan cells and system pins, system direction controls and system output
enables is as shown in the Boundary Scan Signals & Pins table . The cells are listed in the order in which they are
connected in the boundary-scan register, starting with the cell closest to TDI.
The EXTEST guard values specified in the Boundary Scan Signals & Pins table should be .clocked into the boundaryscan register (using the SAMPLE/PRELOAD instruction) before the EXTEST instruction is selected, to ensure that
known data is applied to the core logic during the test. This guard ¥alue should also be used when new EXTEST
vectors are clocked into the boundary-scan register.
·
The values stored in the BS register after power-up are not defined. Similarly, the values previously clocked into the
BS register are not guaranteed to be maintained across a Boundary Scan reset (from forcing nTRST low or entering
the test logic reset state).

10.8 Boundary Scan Interface Signals
Tbscl

Tb sch

tck

tms, tdi

tdo

Data In

Data Out

LJ-04681.Al4

Figure 11: Boundary Scan General Timing

Digital Equipment Corporation

Preliminary

Boundary Scan Test Interface

tck

tdo

Tbs oz

I
II

Data Out

Tbsdz

I
LJ-04682.Al4

Figure 12: Boundary Scan Tri-state Timing

ntrst

tms

LJ-04683.Al4

Figure 13: Boundary Scan Reset Timing

Preliminary

Digital Equipment Corporation

Boundary Scan Test Interface

Table 15: SA-110 Boundary Scan Interface Timing
S)mhol

Parameter

\Jin

!\lax

llnits

Notes

Tbs cl

TCK low period

Tbsch

TCK high period

Tbs is

TDI,TMS setup to [TCr]

Tbsih

TDl,TMS hold from [TCr]

Tbs oh

TDO hold time

Tbsod

TCf to TDO valid

Tbsss

110 signal setup to [TCr]

Tbs sh

1/0 signal hold from [TCr]

Tbsdh

data output hold time

Tbsdd

TCf to data output valid

Tbsoe

TDO enable time

Tbs oz

TDO disable time

Tbs de

data output enable time

Tbs dz

data output disable time

Tbsr

Reset period

Tbsrs

tms setup to [TRr]

Tbsrh

tms hold from [TRr]

ns
40

5
40

ns
ns

1,2

1,3

5,6

5,7

Notes:
1.

Assumes a 25pF load on TDO. Output timing derates at 0.072ns/pF of extra load applied.

TDO enable time applies when the TAP controller enters the Shift-DR or Shift-IR states.

TDO disable time applies when the TAP controller leaves the Shift-DR or Shift-IR states.

For correct data latching, the 1/0 signals (from the core and the pads) must be setup and held with respect to
the rising edge of TCK in the CAPTURE-DR state of the SAMPLE/PRELOAD and EXTEST instructions.

Assumes that the data outputs are loaded with the ac test loads (see ac parameter specification).

Data output enable time applies when the boundary scan logic is used to enable the output drivers.

Data output disable time applies when the boundary scan is used to disable the output drivers.

TMS must be held high as nTRST is taken high at the end of the boundary-scan reset sequence.

TCK may be stopped indefinitely in either the low or high phase.

Digital Equipment Corporation

Preliminary

Boundary Scan Test Interface

Table 16: Boundary Scan Signals & Pins

(;uarrl

Output l'nahle

Cell N.mw

Output' nahk
I 1 pe
BS l'dl

a29

A[29]

OUT

abe

a30

A[30]

OUT

abe

a3l

A[3l]

OUT

abe

ape

APE

abort

ABORT

melkin

MCLK

IN
IN
IN

MCLK

OUT

sna

NMCLK

OUT

sna

\ .ilu(•

( di l\anw

I 1 pe

mse

MSE

config

CONFIG

IN
IN

nmreq

nMREQ

OUT

mse

seq

SEQ

OUT

mse

elf

CLF

OUT

abe

lock

LOCK

OUT

abe

melkout

nrw

nRW

OUT

abe

nmelk

spdf

SPDF

nwait

nWAIT

mccfgO

MCCFG[O]

mccfgl

MCCFG[l]

mccfg2

MCCFG[2]

IN
IN
IN
IN

testclk

TESTCLK

cccfg2

CCCFG[2]

cccfgl

CCCFG[l]

l\o.

BS ("ell

from tdi

'lo.

cccfg3

CCCFG[3]

cccfgO

CCCFG[O]

nresetout

nRESET_OUT

OUT

nreset

nRESET

abe

ABE

abe

sna

SnA

masO

MAS[O]

OUT

abe

fiq

FIQ

mas I

MAS[I]

OUT

abe

irq

IRQ

A[O]

OUT

abe

dinO

D[O]

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

A[I]

OUT

abe

doutO

D[O]

OUT

A[2]

OUT

abe

dint

D[l]

A[3]

OUT

abe

doutl

D[l]

OUT

A[4]

OUT

abe

din2

D[2]

A[5]

OUT

abe

dout2

D[2]

OUT

A[6]

OUT

abe

din3

D[3]

A[7]

OUT

abe

dout3

D[3]

OUT

A[8]

OUT

abe

din4

D[4]

elk

CLK

test_byp

TEST_BYP

A[9]

OUT

abe

dout4

D[4]

OUT

alO

A[!O]

OUT

abe

din5

D[5]

all

A[ll]

OUT

abe

dout5

D[5]

OUT

al2

A[12]

OUT

abe

din6

D[6]

al3

A[13]

OUT

abe

dout6

D[6]

OUT

al4

A[l4]

OUT

abe

din7

D[7]

al5

A[l5]

OUT

abe

dout7

D[7]

OUT

al6

A[l6]

OUT

abe

din8

D[8]

al?

A[l7]

OUT

abe

dout8

D[8]

OUT

al8

A[l8]

OUT

abe

din9

D[9]

al9

A[l9]

OUT

abe

dout9

D[9]

OUT

a20

A[20]

OUT

abe

din JO

D[LO]

a2l

A[21]

OUT

abe

doutlO

D[LO]

OUT

a22

A[22]

OUT

abe

dinll

D[ll]

a23

A[23]

OUT

abe

doutll

D[ll]

OUT

a24

A[24]

OUT

abe

dinl2

D[l2]

a25

A[25]

OUT

abe

doutl2

D[l2]

OUT

a26

A[26]

OUT

abe

dinl3

D[l3]

a27

A[27]

OUT

abe

dout13

D[l3]

OUT

a28

A[28]

OUT

abe

dinl4

D[14]

Preliminary

Digital Equipment Corporation

(,u.nd
\ .ilue
I X

dbe
dbe
dbe
dbe
dbe
dbe
dbe
dbe
dbe
dbe
dbe
dbe
dbe
dbe

Boundary Scan Test Interface
Table 16: Boundary Scan Signals & Pins

l\o.

Output

~11.ihk

( ell '\,nm

I\ pe

BS ( "c II

dbe

dout14

D[14]

OUT

din15

D[15]

dout15

D[15]

OUT

din16

D[16]

dout16

D[16]

OUT

din17

D[17]

100

doutl7

D[17]

OUT

101

din18

D[18]

102

dout18.

D[18]

OUT

103

din19

D[19]

104

dout19

D[19]

OUT

105

din20

D[20]

106

dout20

D[20]

OUT

107

din21

D[21]

108

dout21

D[21]

OUT

109

din22

D[22]

110

dout22

D[22]

OUT

111

dbe

DBE

IN
IN

112

dbein

DBE

113

din23

D[23]

114

dout23

D[23]

OUT

115

din24

D[24]

.ii.u cl

\ 'lhH.'

dbe
dbe
dbe
dbe
clbe
dbe
dbe

'
J<.X

'\o.

Output

t11.1hkl

(ell N.nne

I \ill

BS (di

116

dout24

D[24]

OUT

dbe

117

din25

D[25]

118

dout25

D[25]

OUT

119

din26

D[26]

120

dout26

D[26]

OUT

121

din27

D[27]

122

dout27

D[27]

OUT

123

din28

D[28]

124

dout28

D[28]

OUT

125

din29

D[29]

126

dout29

D[29]

OUT

127

din30

D[30]

128

dout30

D[30]

OUT

129

din31

D[31]

130

dout31

D[31]

OUT

(,u,nd

\.due

dbe
dbe
dbe
dbe
dbe
dbe
dbe

dbe

dbe
toTDO

Key:

IN
OUT
INENl
OUTENl

Input pad
Output pad
Input enable active high
Output enable active high

Digital Equipment Corporation

Preliminary

de Parameters
11.0 de Parameters
11.1 Absolute Maximum Ratings

Table 17: SA-110 de Maximum Ratings
S) mhol

Parameter

l\lininrnm

l\laximum

VDD

Core supply voltage

VSS-0.5

VSS+2.2

VDDX

I/O voltage

MIN(VSS - 0.5,
VDD-0.3)

VSS+3.6

Vip

Voltage applied to any pin

VSS-0.3

MIN(VDDX +0.3,
vss +3.6)

Short-term storage temperature

-20

125

llnits 11\ote

v
v

Note: (1) These are stress SA-110 ratings only. Exceeding the absolute maximum ratings may permanently damage
the device.

11.2 de Operating Conditions
Table 18: SA-110 de Operating Conditions
S)mhol

Parameter

l\linimum

\laximum

I nits

Notes

1,2

0.2*VDDX

v
v
v
v

High-level output current

-2mA

Iolc

Low-level output current

2mA

Ambient operating temperature

Vihc

IC input high voltage

0.8 *VDDX

VDDX

Vile

IC input low voltage

0.0

0.2*VDDX

Vohc

OCZ output high voltage at -2 mA

0.8 *VDDX

VDDX

Vole

OCZ output low voltage at 2 mA

0.0

Iohc

1,2
1,2,3
1,2,3

Notes: (1) Voltages measured with respect to VSS.
(2) IC - CMOS-level inputs (includes IC and ICOCZ pin types).
(3) In sleep mode, the levels on the output and I/O pins are maintained by weak leakers only. Systems
that require the SA-110 to sink or source de current may not use sleep mode.

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de Parameters
11.3 de Characteristics

Table 19: SA-110 de Characteristics

S~mbol

Parameter

Nominal

Iin

IC input leakage current

100

µA

Its

Tristate leakage current

100

µA

Cin

Input pin capacitance

Cio

Input /output pin capacitance

ESD

HBM human body model

(!nits

11.4 Power Supply Voltages and Currents
Table 20: SA-110 Power Supply Voltages and Currents

,\A

B,\

21281
C\

Maximum normal mode power

450

300

Maximum idle power

Maximum sleep mode current

Parameter

E c\

900

700

n/a

I I
l 'nits

.\Jotl's

1000

n/a

µA

VDD

Minimum internal power supply voltage

1.5

1.8

1.9

Nominal internal power supply voltage

1.65

2.0

Maximum internal power supply voltage

1.8

2.2

2.1

VDDX

Minimum external power supply voltage

3.0

Nominal external power supply voltage

3.3

Maximum external power supply voltage

3.6

Notes: (1) Running Dhrytone 2.1 at 25°C, nominal power supply voltages, and 20 pF load on output and 1/0 pins.
Power for AA, BA, and DA parts assumes 33-MHz external bus. Power for CA and EA parts assumes
66-MHz external bus.
(2) Measured at 25°C junction temperature. Since the power levels for these modes are low, the junction
temperature and ambient temperature are nearly equal during sleep and idle.

Digital Equipment Corporation

Preliminary

ac Parameters
12.0 ac Parameters
12.1 Test Conditions
The ac timing diagrams presented in this section assume that the outputs of the SA-110 have been loaded with a 50pF
capacitive load on outut signals and 15pF load on clock outputs. The output pads of the SA-110 are CMOS drivers
which exhibit a propagation delay that increases with the increase in load capacitance. An 'output derating' figure is
given for each output pad, showing the approximate rate of increase of delay with increasing or decreasing load
capacitance for typical process at room temperature.

Table 21: SA-110 Output Derating

Load for
!\iominal
Value

Output
Derating
( ns/pF)
VDD=l.65
Rising Edge

Output
Ile rating
(ns/pF)
VDI>= 1.65
Falling Edge

Output
De rating
(ns/pF)
VDI>=2.0
Rising Edge

Output
Derating
(ns/pFJ
VDI>=2.0
Falling Edge

A[31:0], nR/W, LOCK,
nMREQ, SEQ, D[31:0]

50pf

.07

.09

.07

nMCLK,MCLK

15pf

.03

.04

.03

Output Signal

12.2 Module Considerations
The edge rates for the SA-110 are such that the lumped load model presented above can only be used for etch lengths
up to 1 inch. Over one inch of etch the signal is a transmission line and needs to be modeled as such.

Preliminary

Digital Equipment Corporation

ac Parameters
12.3 Main Bus Signals
The MCLK signal is the reference for all SA-110 timing. The nMCLK signal is an inverted copy of the MCLK signal
when SnA is high. The nMCLK signal is low when SnA is low. The SA-110 will stall its internal clock for one cycle
if nWAIT is low when MCLK goes high.

MCLK
Tmckft

nMCLK
nWAIT

____..

DBE

Tdz __.j

0[31:0]

OUT

0[31:0]
I

ABORT

I..-

Tabth

MSE
Tm sh

+Tmse

nMREQ
SEQ

Figure 14: SA-110 Main Bus Timing

Digital Equipment Corporation

Preliminary

ac Parameters

MCLK

ABE
A[31 :O]
MAS[1:0]

Tabz..,._

Tabe

LOCK
nRW

CLF

Figure 15: SA-110 Address Timing with APE=Low

MCLK

ABE
A[31 :O]
MAS[1:0]

Tab __.

Tabz•~

LOCK
nRW

CLF

Figure 16: SA-110 Address Timing with APE=HIGH

Preliminary

Digital Equipment Corporation

ac Parameters
12.4 SA-110 ac Parameters
The ac parameters specified in the following tables are valid for the full range of voltage, temperature, and process
defined for each SA-110 part in Table 20.
The following notes are used in Tables 22-26.
1)

MCLK and nMCLK timings measured between clock edges at 50% of VDDX driving 15 pF load.

(2)

The timings of these signals are measured to 80%/20% for outputs and 90%/10% for inputs.

(3)

The Taddrx times are for the first address of a sequential cycle. The Taddrxseq times are for the subsequent
addresses of a sequential cycle.

(4)

The MCCFG setting with SnA asserted should be selected so the nominal MCLK speed does not exceed
1/(2*Tmckh).

(5)

Tdoh is guaranteed to be greater than a minimum Tdz.

Digital Equipment Corporation

Preliminary

ac Parameters

Table 22: SA-110 ac for -AA Parts

s~ mhol

Parnmeter

:\I in

I i\lax I llnit 11 Note I

Tmckl

MCLK LOW time

Tmckh

MCLK HIGH time

Tmckrt

MCLK, nMCLK rise time SnA=l

.75

Tmckft

MCLK, nMCLK fall time SnA=l

CCCFG

CCCFG setting

Tmckr

value

MCLK rise to nMCLK fall SnA=l

--0.5

1.5

Tmckf

MCLK fall to nMCLK rise SnA=l

-1.5

0.5

Tws

nWAITsetup to MCLK

Twh

n WAIT hold from MCLK

Tabe

address bus enable

Tabz

address bus disable

Taddrl

MCLK to address delay APE high

2,3

Taddr2

MCLK to address delay APE low

2,3

Taddrlseq

MCLK to address delay APE high

2,3

Taddr2seq

MCLK to address delay APE low

2,3

Tah

address hold time

Tdbe

DBE to data enable

Tde

MCLK to data enable

Tdbz

DBE to data disable

Tdz

MCLK to data disable

2,5

Tdout

data out delay

Tdoh

data out hold

Tdis

data in setup

Tdih

data in hold

Tabts

ABORT setup time

Tabth

ABORT hold time

Tmse

nMREQ & SEQ enable

Tmsz

nMREQ & SEQ disable

Tmsd

nMREQ & SEQ delay

Tmsh

nMREQ & SEQ hold

Preliminary

Digital Equipment Corporation

2
10
3

ac Parameters

Table 23: SA-110 ac for -BA Parts
S.\ mhol

Parameter

l\lin

l\la:x

l nit

Tmckl

MCLK low time

Tmckh

MCLK HIGH time

Tmckrt

MCLK, nMCLK rise time SnA=l

.75

Tmckft

MCLK, nMCLK fall time SnA=l

CCCFG

CCCFG setting

Tmckr

Note

3.5

value

MCLK rise to nMCLK fall SnA=l

-1

Tmckf

MCLK fall to nMCLK rise SnA=l

-2

Tws

nWAIT setup to MCLK

Twh

nWAIT hold from MCLK

Tabe

address bus enable

Tabz

address bus disable

Taddrl

MCLK to address delay APE high

2,3

Taddr2

MCLK to address delay APE low

2,3

Taddrlseq

MCLK to address delay APE high

2,3

Taddr2seq

MCLK to address delay APE low

2,3

Tah

address hold time

Tdbe

DBE to data enable

Tde

MCLK to data enable

Tdbz

DBE to data disable

Tdz

MCLK to data disable

2,5

Tdout

data out delay

Tdoh

data out hold

Tdis

data in setup

Tdih

data in hold

Tabts

ABORT setup time

Tabth

ABORT hold time

Tmse

nMREQ & SEQ enable

Tmsz

nMREQ & SEQ disable

Tmsd

nMREQ & SEQ delay

Tm sh

nMREQ & SEQ hold

2
14
3

Digital Equipment Corporation

Preliminary

ac Parameters

Table 24: SA-110 ac for-CA Parts
Symbol

Preliminary

Parameter

I Min I Max I lJnit I Note I

Tmckl

MCLK LOW time

7.5

Tmckh

MCLK HIGH time

7.5

Tmckrt

MCLK, nMCLK rise time SnA=l

.75

Tmckft

MCLK, nMCLK fall time SnA=l

.75

2.5

CCCFG

CCCFG setting

value

Tmckr

MCLK rise to nMCLK fall SnA=l

-1

Tmckf

MCLK fall to nMCLK rise SnA=l

-1

Tws

nWAIT setup to MCLK

Twh

n WAIT hold from MCLK

Tabe

address bus enable

Tabz

address bus disable

Taddrl

MCLK to address delay APE high

2,3

Taddr2

MCLK to address delay APE low

2,3

Taddrlseq

MCLK to address delay APE high

2,3

Taddr2seq

MCLK to address delay APE low

2,3

Tah

address hold time

Tdbe

DBE to data enable

Tde

MCLK to data enable

Tdbz

DBE to data disable

Tdz

MCLK to data disable

2,5

Tdout

data out delay

Tdoh

data out hold

Tdis

data in setup

Tdih

data in hold

Tabts

ABORT setup time

Tabth

ABORT hold time

Tmse

nMREQ & SEQ enable

Tmsz

nMREQ & SEQ disable

Tmsd

nMREQ & SEQ delay

Tmsh

nMREQ & SEQ hold

Digital Equipment Corporation

2
9
3

ac Parameters

Table 25: SA-110 ac for -DA Parts

Symb~I ~- 11

Par~meter

](1 Min

Max ( Unit
1

Note

Tmckl

MCLK low time

Tmckh

MCLK HIGH time

Tmckrt

MCLK, nMCLK rise time SnA=l

.75

Tmckft

MCLK, nMCLK fall time SnA=l

.75

2.5

CCCFG

CCCFG setting

value

Tmckr

MCLK rise to nMCLK fall SnA=l

-l.5

Tmckf

MCLK fall to nMCLK rise SnA=l

-1

Tws

nWAIT setup to MCLK

Twh

nWAIT hold from MCLK

Tabe

address bus enable

Tabz

address bus disable

Taddrl

MCLK to address delay APE high

2,3

Taddr2

MCLK to address delay APE low

2,3

Taddrlseq

MCLK to address delay APE high

2,3

Taddr2seq

MCLK to address delay APE low

2,3

Tah

address hold time

Tdbe

DBE to data enable

Tde

MCLK to data enable

Tdbz

DBE to data disable

Tdz

MCLK to data disable

2,5

Tdout

data out delay

Tdoh

data out hold

Tdis

data in setup

Tdih

data in hold

Tabts

ABORT setup time

Tabth

ABORThold time

Tmse

nMREQ & SEQ enable

Tmsz

nMREQ & SEQ disable

Tmsd

nMREQ & SEQ delay

Tmsh

nMREQ & SEQ hold

ns
1.5

2
13
3

Digital Equipment Corporation

Preliminary

ac Parameters

Table 26: SA-110 ac for -EA Parts
S) mhol

Preliminary

Parameter

I Min I Max II Unit I Note I

Tmckl

MCLK LOW time

7.5

Tmckh

MCLK HIGH time

7.5

Tmckrt

MCLK, nMCLK rise time SnA=l

.75

Tmckft

MCLK, nMCLK fall time SnA=l

.75

2.5

CCCFG

CCCFG setting

value

Tmckr

MCLK rise to nMCLK fall SnA=l

-1

Tmckf

MCLK fall to nMCLK rise SnA=l

-1

Tws

n WAIT setup to MCLK

Twh

nWAIT hold fromMCLK

Tabe

address bus enable

Tabz

address bus disable

Taddrl

MCLK to address delay APE high

2,3

Taddr2

MCLK to address delay APE low

2,3

Taddrlseq

MCLK to address delay APE high

2,3

Taddr2seq

MCLK to address delay APE low

2,3

Tah

address hold time

Tdbe

DBE to data enable

Tde

MCLK to data enable

Tdbz

DBE to data disable

Tdz

MCLK to data disable

2,5

Tdout

data out delay

Tdoh

data out hold

Tdis

data in setup

Tdih

data in hold

Tabts

ABORT setup time

Tabth

ABORT hold time

Tmse

nMREQ & SEQ enable

Tmsz

nMREQ & SEQ disable

Tmsd

nMREQ & SEQ delay

Tmsh

nMREQ & SEQ hold

Digital Equipment Corporation

2
9
3

Physical Details
13.0 Physical Details
22.00

View from above

20.00

Pin 1

Pin 108

20.00

SA-110

22.00

Pin 73

Pin 36
Pin 37

Pin 72

0.5 Typical

1.60
Maximum

1.40

~k
0.22
Figure 17: SA-110144-Pin TQFP Mechanical Dimensions in mm

Digital Equipment Corporation

Preliminary

Physical Details
13.1 Pinout
Table 27: SA-110 Pinout -144 pin Thin Quad Flat Pack
Pin

I Signal I T) JJe

2
3
4
5
6
7

I T~ pe

D[23]

I/O

MAS[O]

Signal

I T) pe

109

A[22]

0
0
0
0

I/O

D[l]

1/0
1/0
1/0

D[24]

I/O

MAS[l]

D[25]

I/O

A[ O]

110
111

A[23]
A[24]

D[26]

I/O

A[ 1]

112

A[25]

41
42

D[27]

I/O

A[2]

113

vss

VDDX2

VDDXl

114
115

VDDX2
A[26]

D[28]

I/O

vss
vss

116

A[27]

D[29]

I/O

D[30]

VDD
A[ 3]

117
118

A[28]
A[29]

0
0

D[31]

I/O
I/O

81
82
83

A[ 4]

TDO

A[ 5]

0
0

D[2]
D[3]
VDD

vss
vss
VDDXl

9
10
11
12
13
14
15
16
17

D[4]
D[5]

D[ll]
VDDXl.

18
19

vss
vss

44
45
46
47
48
49
50
51
52
53
54
55

20
21

VDD
D[12]

56
57

D[13]

D[14]

58
59

nMREQ
SEQ

D[15]

CLP

D[16]

1/0
I/O
1/0
1/0

LOCK

I/O
I/O

62
63

nRW

D[17]
D[18]

D[l9]

1/0

VDDXl

30
31

vss
vss

VDD
D[20]

I/O

D[21]

I/O

D[22]

I/O

66
67
68
69
70
71
72

SPDF
MCCFG[O]

Note:

Pin 1

D[O]

33
34
35
36

I Signal I T~ pe

Signal

D[6]
D[7]
D[8]
D[9]
D[lO]

DBE

1/0
1/0
1/0
I/O
1/0
I/O
I/O
1/0

I/O

0
0

119

A[30]

0
0

120

A[31]

121

APE

122

ABORT

TDI

A[ 6]

nTRST

A[ 7]

TMS

A[ 8]

123

MCLK

I/O

TCK

A[ 9]

124

nMCLK

n/c

A[lO]

0
0

125

vss

VDD

126

VDDX2

VDD

90
91

nWAIT

vss
vss

127

MSE

128

CLK

CONFIG

93
94

VDDX2
A[ll]

129
130

VDD
TCK_BYP

131

TESTCLK

0
0
0
0
0

A[12]

A[13]

A[14]

A[15]

99
100

A[16]
A[l 7]

101

A[18]

102

MCCFG[l]

103

MCCFG[2]
CCCFG[2]

vss

CCCFG[3]
nRESET_OUT
ABE

0
I

0
0
0
0
0

132

vss

133

VDD

134

n/c

135

n/c

0
0

136
137

n/c
n/c

VDDX2

138

CCCFG[l]

vss
vss

139

CCCFG[O]

104

140

nPWRSLP

105
106

VDD
A[l9]

107
108

A[20]
A[21]

0
0
0

141

nRESET

142
143

SnA
nFIQ

144

nIRQ

VDDXl and VDDX2 should be tied to the VDDX power plane of the system, but are not internally connected.

Preliminary

Digital Equipment Corporation

Support, Products and Documentation
If you need technical support or help deciding which literature best meets your needs,
call the Digital Semiconductor Information Line:

United States and Canada 1-800-332-2717
Outside North America
+1-510-490-4753
or visit the Digital Semiconductor World-Wide Web Internet site:

http://www.digital.com/info/semiconductor
Ordering Digital Semiconductor Products

To order the Digital Semiconductor SA-110 microprocessor and for more information
about an evaluation board kit, contact your local distributor.
The following table lists some of the semiconductor products available from Digital. To
obtain a Digital Semiconductor Product Catalog, call the Digital Semiconductor Information Line.
Product

Order Number

Digital Semiconductor SA-110 Microprocessor (100 MHz)
Digital Semiconductor SA-110 Microprocessor (160 MHz)
Digital Semiconductor SA-110 Microprocessor (200 MHz)
Digital Semiconductor SA-110 Microprocessor (166 MHz)
Digital Semiconductor SA-110 Microprocessor (233 MHz)
Digital Semiconductor SA-110 Hardware Developer's Kit
ARM Software Developer's Kit- End User License
ARM Software Developer's Kit- Site License

21281-BA
21281-AA
21281-CA
21281-DA
21281-EA
21A81-11
21B81-01
21B81-02

Ordering Associated Digital Semiconductor Literature

The following table lists some of the available Digital Semiconductor literature. For a
complete list, call the Digital Semiconductor Information Line.
Title

Order Number

Digital Semiconductor SA-110 Microprocessor Product Brief
Digital Semiconductor SA-110 Microprocessor Tools Brochure
Digital Semiconductor SA-110 Evaluation Board Reference Manual
ARM Architecture Reference

EC-QPWKC-TE
EC-QPWJB-TE
EC-QU5KA-TE
EC-QV44A-TE

Ordering Third-Party Literature

You can order the following third-party literature directly from the vendor:
Title

Vendor

IEEE Standard 1149.1 - 1990, Standard Test Access Port and
Boundary-Scan Architecture

The Institute of Electrical and Electronics
Engineers, Inc.
U.S.
1-800--701-4333
International 1-908-981-0060
FAX
1-908-981-9667

Preliminary

Digital Equipment Corporation

•

EC-QPWLC-TE

Printed in U.S.A.