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March 1983

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Document:	Rainbow 100 PC100 System Module Specification
Order Number:	AA-V523A-TV
Revision:
Pages:	34
Original Filename:	http://bitsavers.org/pdf/dec/rainbow/AA-V523A-TV_Rainbow_100_PC100_System_Module_Specification_Mar83.pdf

OCR Text

AA-V523A-TV

RainbowTM

100
PC100 System Module Specification

digital equipment corporation

First Printing, March 1983
© Digital Equipment Corporation 1983. All Rights Reserved.

The information in this document is subject to change without notice and should
not be construed as a commitment by Digital Equipment Corporation. Digital
Equipment Corporation assumes no responsibility for any errors that may
appear in this document.
The software described in this document is furnished under a license and may
only be used or copied in accordance with the terms of such license.
No responsibility is assumed for the use or reliability of software on equipment
that is not supplied by DIGITAL or its affiliated companies.
CP/M®, CP/M@-80 and CP/M@-86 are registered trademarks of Digital
Research Inc.
Z80@ is a registered trademark of Zilog, Inc.
8088® is a registered trademark of Intel Corporation.
The following are trademarks of Digital Equipment Corporation:

momoomo

DEC
DECmate
DECsystem-10
DECSYSTEM-20
DECUS
DECwriter
DIBOL

MASSBUS
PDP

P/OS
Professional
Rainbow
RSTS
RSX

UNIBUS
VAX
VMS
VT
Work Processor

The postage-prepaid READER'S COMMENTS form on the last page of this
document requests the user's critical evaluation to assist us in preparing future
documentation.

Printed in U.S.A.

TABLE OF CONTENTS/REVISION STATUS

1.0
1.1

SYSTEM MODULE OVERVIEW • • •
BLOCK DIAGRAM • • • • •

2.0

SYSTEM MODULE FUNCTIONAL
SPECIFICATION • • • •
• • • • • 5
8088 SYSTEM
• • 5
8088 CPU • • •
• • • • • 5
Memory • • • • •
• • 5
Shared Memory
6
ROM • • • • • •
• • 6
4KB Screen Memory And 4KB
Attribute Memory • • • • • •
• • 6
256 x 4 NVM With Shadow RAM • • • • • • • • • 6
Unshared Dynamic Memory (optional)
• 7
8088 I/O Map • • • • • •
• • • •
· 7
8088 Memory Map • • • • • • • • • • • •
• 8
8088 Interrupts • . . •
9
Video System: 8088 • .
• • 9
General Video Features •
• • • • 9
Composite Video Output •
10
Video Memory • • • • . • • • • • • • • •
10
Video Processor
(DCOll And DC012)
• • •
10
DCOll programming Information
• • • • 12
DC012 Programming Information • • • • •
12
Character Generator ROM
• • • •
14
Diagnostic Registers • • • • • •
15
Diagnostic Write Register: 8088
15
COMM LOOPBACK Maintenance Bit • • • •
15
DIAGNOSTIC LOOPBACK Maintenance
Bi t
. . . . . . • . . . . . . .
16
Diagnostic Read Register: 8088 •
16
General/Diagnostic Control/Status
Register: Z80A • • • • • • • • • •
17
General/Diagnostic Control-Z80A
Port Address 21 (and 20) Hex • • •
17
General/Diagnostic Status Register
Z80A Port Address 21 Hex • • • • • • • •
17
Pr inter Port Interface • • • •
17
Printer Bit Rate/Communication
Clock Source Register • • • • • • • • • • • 18
Communications Port
19
Communications Status
Register: 8088 • • • • •
20

2.1
2.1.1
2.1. 2
2.1.2.1
2.1.2.2
2.1.2.3
2.1.2.4
2.1.2.5
2.1. 3
2.1.4
2.1. 5
2.1. 6
2.1.6.1
2.1.6.2
2.1.6.3
2.1.6.4
2.1.6.5
2.1.6.6
2.1.6.7
2.1. 7
2.1.7.1
2.1.7.2
2.1.7.3
2.1.7.4
2.1.7.5
2.1.7.5.1
2.1.7.5.2
2.1.7.6
2.1.7.6.1
2.1.7.7
2.1.7.7.1

iii

3
3

CONTENTS (Cont.)

2.1.7.7.2
2.1.S
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.S
2.3

Communications Control
Register: SOSS • • • • • • • • • • •
Massive Hardware Foul-Up
Detection
ZSOA SYSTEM
ZSOA CPU • • • •
ZSOA Shared Memory • •
ZSOA Private RAM •
ZSOA I/O Map • • •
ZSOA Memory Map
• • • •
ZSOA Cycle Time
• • • •
ZSOA Interrupts • • ••
•••••
Floppy Controller Module • • • • •
ZSOA/SOSS INTERRUPT FLAGS • • • •

•

21
21
21
21
21
22
22
23
23
23
23

CONNECTOR PINOUTS AND DESCRIPTION
POWER INTERFACE CONNECTOR
VIDEO INTERFACE CONNECTOR
EXTENDED COMMUNICATIONS OPTION
CONNECTOR • • • • • • •
MEMORY OPTION CONNECTOR
COMMUNICATIONS INTERFACE
CONNECTOR • • • •

25
25
25

4.0

POWER REQUIREMENTS • • •

5.0

PHYSICAL DIMENSIONS - MODULE •

6.0

RELIABILITY GOALS

7.0

SYSTEM MODULE ENVIRONMENTAL
SPECIFICATIONS • • •

S.O

APPLICABLE STANDARDS •

9.0

DOCUMENTS SOURCE •

3.0

3.1
3.2
3.3

3.4
3.5

26
27
2S

FIGURES
FIGURE

1
2
3
4

System Module Block Diagram
SOSS Memory Map • • • • • •
ZSOA Memory Map • • • • • •
Floppy Controller Block Diagram

• • 4

• • • 8

22
24

TABLES
TABLE

1
2

Extended Communications Option Connectors
Memory Option Connector
• • • • • •

26
27

PCloa SYSTEM MODULE SPECIFICATION
1.0

SYSTEM MODULE OVERVIEW

PC100 System Module is the basic intelligence of the system and provicies
the means for interconnect'ion of all options.
This module includes the
following features:
1.

8088 CPU

UOA CPU

64KB Shared Dynamic Hemory

2KB Z80A Pr ivate RAN

24KB RON

256 x 4 Non-Volatile Memory (NVM)

1:C011. DC012 Video Electronics

Asynchronous/Bisynchronous Communications Port

Printer Port

10. Keyboard Interface
11. Floppy Controller
12. Option expansion capability

1.1

•

Extended communications

•

Color graphics

•

Ex tended memor y (64/192 KB)

BLOCK DIAGRAM

The following figure represents the block diagram for the system module.

Page 3

PC100 SYSTEM MODULE SPECIFICATION

+----------------------INTERRUPT-----------------------------------+
+--------+
I

+------+

----+

+- - - - +

ZeOA

:-----I
I
I

+--------+

B
I

+--------+
: 2 KB :

IUNSHAREDI-----: RAN
I

D
T

+--------+
RX50 :

I1F

+--------+

+---------+
-----, 8088 1--+
I

+----------+
: 2~ KB
:----:

+--------+

tISK :-----DRIVE

+----------+
+
1 SHARED
I------DMA--------I EXTENDED 1
COMt-',S
I
I ----- I 62 KB
I
+------+
:
RAM
; ---OPTION I
+----------+
I
2 KB
I
I UNSHARED :---8
1
RAM
:
,
,
B
+----------+

ROM

+----------+

U
S

I
T

,
I

+---------+

D
A
T
A

+---------+
,
I

+----------+
I OPTIONAL
I

I
I

,
I

+------+

RAM
:----;
1(64 KB OR :
I
192 KB) I

B
U
S

-----IKEYBOARD
:

+---------+
-----1 BISYNC
I COt'lhS

: DC 11/12 I
: VIDEO
1---ICONTROLLERI

+---------+

+----------+
,
+------+
: I 4 KB :

+---------+
,
,

PORT

+---------+

+---+------+
: 4 KB
I
IATTRIBUTE 1---RM;

+ -

-----,
I

+------+

System Module Block Diagram

Page 11

,
I

+----------+
Figure 1.

-----1 PRINTER I

I ISCREEN I ----

+---------+
I ASYNC/

+ - --"- - - - -- - +

: RAM

+----------+

IfF

COLOR I
GRAPHICSI

+ -

PC100 SYSTEM MODULE SPECIFICATION
2.0

SYSTEM MODULE FUNCTIONAL SPECIFICATION

The PC10a includes a two-processor architecture based on the simultaneous
operation of an 808B and a ZeOA CPU. These CPUs operate from and transfer
data through a shared block of 62Kb of RAt-i.
In addition to this block .of
shared memory, each processor has its own memory and peripheral circuitry.
In addition to running application/user software, each processor supports a
portion of the needed functions of the computer. The Z80A processor
performs the functions required to read/write the floppy disks.
The 8088
handles the video output, keyboard I/O, printer port and the communications
as well as any other options.

2.1

8088 SYSTEM

2.1.1

8088 CPU

The 80BP microprocessor on the module controls nearly everything except the
floppy disk.
The 8088 microprocessor runs from a clock of .4.815 MHz (208
nS cycle) and control s the following:

•
•
•

•
•
•
•

Video
Keyboard
Pr inter
Commun ic at ion line
Optional graphics board
Optional extended communications board
hemory

1. 64KB dynamic memory (62KB shared)

2. 24KB ROM

3. 4KB video screen memory (static)
4. 4KB video attribute memory (static)

5. 256 X 4 non-volatile memory (NVM) with shadow RAM
6. 64KB or 192KB optional unshared dynamic memory

2.1.2

Memory

The various memory
non-volatile RAK.

available

the

8088

Page 5

consists

ROH,

RAM,

and

PC100 SYSTEM MODULE SPECIFICATION
2.1.2.1 Shared Memory - The standard 64KB bank of memory is shared with
the ZeOA processor.
However, the Z80A is unable to address (and ther~fore
can't modify) the first 2KB portion of this bank.
Ttlerefore, the 8088
keeps its interrupt vectors and some other information safe from being
affected by a Z80A application.
No parity generation/detection .is
implemented with the 64KB shared RAM.
If there is no contention for the shared RAM at the time of an 8088 access,
no wai t states are required fol" the cycle. If the RAM is busy due ·to a
refresh cycle or a Z80A memory cycle, which was initiated prior to the
8088' s request, wait states will occur until the request can be filled.
Refresh has the highest priority for memory cycles.
The 8088 has
approximately equal priority with the Z80A except that the Z80A wins all
ties.

2.1.2.2 ROM - There is 24KB of ROM (three sockets) on the module which is
re-addressable by the 8088. The 24KB contains both ZeOA code and 8088 code
for diagnostics, bootstrap, and VT102 emulation.
The code for the ZEOA
must be moved into shared memory by the 8088 in order to be executed by the

ZEOA.

No wait states are required when the 8088 accesses this memory; however,
because the circuitry assumes that all memory is dynamic RAM, wait states
will be excecuted whenever refresh cycles are in progress.
Supported
450 ns.

ROMs are of the 2732/276l.J pinout variety,

with access times

2.1.2.3 4KB Screen Memory And 4KB Attribute Memory - There is screen and
attribute memory available to the 8088 that allows it to control what is on
the CRT display.
This memory is available to the 8088 90% of the time. In
the remaining lOr"
the DCOll and DC012 have access to this memory and
prohibit the 8088 from access.
~ait states to the 8088 will occur during
refresh cycles and while the DCOll and DC012 are using the memory. The
worst case time in which the 8088 can be held in a wait state due to
contention with the DCOll and DC012 is 65 microseconds.
2.1.2.4 256 x 4 NVM With Shadow RAM - The PC100 mother board contains 1024
bits of non-volatile memory that is organized 256 x 4.
The NVM, as it is
called, is located on the 8088 CPU bus at address OEDOOOH through OEDOFFH
and the data path to the dev ice is through data bits C, 1, 2, and 3·
Phantom images of the NVM exist from address OED100H through OEDFFFH.
The device contains a 256 x 4 bit static RAM that performs as any other
static memory. The device also contains a 256 x 4 bit non-volatile memory
that is overlaid with the 256 x 4 bit static memory.
On initialization,
the 8088 does a RECALL of the NVM which places that data into the static
memory. At this time, any read or write to the memory occurs to the static
memory. The RECALL is done viaa bit in the Diagnostic Write register. On
power-up, this bit is a 0, and is set to a 1 by the firmware.
Page 6

PC100 SYSTEM MODULE SPECIFICATION
To perform a RECALL, the bit is set to a 0 and then set back to 1.
The
minimum width for this pulse is 450 ns.
The data is available immediately
after the RECALL bit is reset. On power-up, the RECALL bit is a 0 to
prevent spurious data from being stored into the device.
Therefore, the
RECALL bit must be set to a 1 by software after power-up.
The data that is in the static memory portion can be stored in the NVM by
the 8088 CPU v ia the PROGRAM NVM bit also located in the Diagnostic wr ite
register. This bit is also set to a 0 on power-up. To perform a PROGRAt<i NVN
operation, the bit is set to a 1 and then back to a O.
This pulse has a
minimum width of 100 ns. Once the PROGRAM NVM bit has met the minimum pulse
width it can be removed, however, the device cannot be accessed by the CPU
for 10 ms. At this time, the device is in the process of storing the data
into the NVM.
There is no in<;l ication to the CPU that the dev ice is done
other than 10 ms has passed. If another operation is done on the dev ice
during those 10 ms, it will be ignored. Once the operation is started, it
cannot be terminated unless the power is turned off. In this case, data in
the device is not Valid.

2.1.2.5 Unshared Dynamic Memory (Optional) - The module can be optionally
expanded with 64KB or 192KB of memory for use by the 8088.
If installed,
this memory is always available and never requires wait states (except when
the memory cycle contends with a refresh cycle).

2.1.3

8088 I/O Map

The 8088 I/O map follows:
PORT H

OOH
OOH
02H
02H
04H
06H
OAH
OAIl
OCH
OEH
10H
11 H
20H-2FH
40H
41H
42H
43H
50H-5FH
60H-6FH

FUNCTION
Interrupts Z80A Flop
Clears 8088 Interrupt Flop
Communications and LED Register
General Communications Status Register
DCOll Write Register
Communications Bit Rate Register
Maintenance Port
Maintenance Port
DC012 Write Register
Printer Bit Rate Register
Keyboard Data Register(8251A)
Keyboard Control/Status Register(8251A)
Ex t. Comm. Option/Opt ion Select 1
Comm Data Reg. (7201)
Pr i n t erDa taRe g. (7 20 1 )
Comm Control/Status Reg. (7201)
Pr inter Control/ Status Reg. (7201)
Graphics Option Select
Ext. Comm. Option/Option Select 2
Page 1

(wr He)
(Read)
WO
RO
'vi 0

WO
WO
RO

\iO
\0;0

RO/ roO
RO/WO
RO/WO
RO/WO

RO/WO
RO/WO
R/W

pelOO SYSTEM MODULE SPECIFICATION
2.1.4

8088 Memory Map

Figure 2 shows the 8088's memory map.
FFFFF

ROM 2 (BOOT)
FEOOO
ROM 1
FCOOO
ROM 0
FAOOO

FOOOO
ATTRIBUTE RAM
EFOOO
SCREEN RAh
EEOOO
NVM SHADO".
ED040

NVM

EDOOO
NVM SHADOw
ECOOO
40000
OPTION RAM
10000
SHARED RA~l
0

Figure 2. 8088 Memory Map

Page 8

PC100 SYSTEM MODULE SPECIFICATION
2.1.5

8088 Interrupts

The following table lists the 8088 interrupts.
Interrupt vector
Interrupt Source

Type (Hex)

Address ( Hex)

Highest Vertical Frequency Interrupt
...
DMA Controller In terrupt
(from Optional Extended Comm.
Board)
Graphics Interrupt
Comm. / Pr inter (7201) Interrupt
Extended Comms Interrupt
(optional)
Ke yboard (8251A) Interrupt
Lowest Interrupt from Z80A

20
23

80
8C

22
24
25

90
94

26
27

98
9C

Priority

2.1.6

Video Subsystem: 8088

The video subsystem resides on the mother board and is controlled by the
8088. The subsystem provides fully VT100-compatible video features.
2.1.6.1 General Video
following features:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.

Features -

The

v ideo

subsystem

supports

the

2lJ line x e3 column display
2 4 lin e x 1 37 col urn n dis pIa y
Smooth scroll ing (full screen and spl it screen)
Double height lines
Double width lines
Reverse video
Bold
Bl inking
Un d e r lin e
Composite video output
ROM-resident character patterns

The double height and double width attributes may be selected on a line by
line basis. The other attributes (reverse, bold, blink, and underline) may
be selected on a character-by-character basis.

Page 9

pelOO SYSTEM MODULE SPECIFICATION
2.1.6.2 Composite Video Output - The composite video output provides RS170
like output generated by combining the video signal with a composite sync
signal.
Note
The use of dc coupling is not in strict agreement
with RS 170.
To agree with RS 170, th~ output load
would require a 10 uf capacitor in series with the
output. Failing this, the 2 rna dc short circuit
current requirement .is violated.
This presents no
problem with most monitors which are in fact ac
coupled.
The composite video output has the following nominal characteristics:
1.
2.
3.
4.
5.

Output impedance = 75 ohms, dc-coupled
Sync level = a v
Black level = approximately 0.3 V when loaded with 75 ohms
~hite level = approximately 1.0 V with a 75 ohm load
The composite sync waveform conforms to EIA RS170 st.andards.
The
vertical interval is composed of six equalizing pulses, six
vertical sync pulses, and six more equalizing pulses.
Tile timing
is as follows:
Equalizing pulse width = 2.33 microseconds + 50 ns
Vertical pulse width = 27.28 us + 200 ns
Horizontal pulse width = 4.71 us + 50 ns
Horizontal blank width = 11.84 us + 50 ns/80 column mode
= 12.34 us + 50 ns/132 column ~ode
Front Forch
= 1.54 us + 50 ns

2.1.6.3 Video Memory - The video subsystem tlas 4KB of ·screen RAl'l and 4KB
of attribute RAM.
Only the four LSbs of the attribute RAI': are actually
looked at by the video subsystem.
2.1.6.4 Video Processor (DCOll And DC012) - When accessing the screen
(DC011 and DCC12) RAM, the video processor generates the 12-bit address for
a particular byte in the lower 4KB bank (character RAM). The corresponding
byte in the upper 4KB bank (attribute RAM) is selected also. The two bytes
are passed to the video processor in parallel. The video processor uses the
character code to index into a character generator and uses the attribute
information to modify the video data.
The contents of the screen RAM directly control the display of the lines
and characters. This region of memory contains the displayable characters,
their attributes the line attributes, and the addresses that link one line
to the next. The microprocessor modifies and updates this information in
the intervals between the video processor's D~As.

Page 10

PC100 SYSTEM MODULE SPECIFICATION
The video processor begins reading the screen RAM at the start of RAM
(location OEEOOOH) following each vertical reset.
Three bytes of control
data are located at the end of each line of characters.
The first byte,
called the terminator, is FF hex and is a unique character that the video
processor recognizes as the end of the line. The next two bytes form .an
address (low byte followed by high byte) which points to the first
character of the nex t line to be displayed.
The byte of attr ibutes which
corresponds to the low byte of the address contains three bits of line
attributes which are applied to the line being pointed to.
Attribute ,I
\
RAM
IAttribute Datal
I
I

RAM

\
\

I Character Data I
\

\
I
\

I
I
I

Character

No Attrib.

ILine Attribute

I
I

I
I
I

Address of Next Line

, Terminator
I

The bits are assigned in the following manner:

£:1

,
, Rev. ,
I

Unused

Char.
Attrib.

Not
Under
Line

Al t.
Char Set

D~ta

, Unused
Line
Attrib.1

Not I
I
Bold I Videol

,
I

Char.

Not
Blink

Code for Character

,
,
I
I

Unused

Un used

Unused

DoublelDoublelScrolll
Width IHeightlHegionl
I
I

(Smooth) scroll region - if set, this line scrolls: if not set, it doesn't
Double
Height

Double
Width

o
1
o

o
1
1

Result
bottom half double height
top half double height
double width
normal height, normal width

Page 11

PC100 SYSTEM MODULE SPECIFICATION
2.1.6.5 DCOll Programming Information - The DCOll video-timing chip can be
accessed by the 8088 (WRITE-ONLY) at I/O address Li.
The DC011 must be
programmed with the desired refresh rate and col umn mode on power-up and
after any mode changes. To program the DC011, write two of the following
four codes:
Code

Configuration
80 column mode sets
132 column mode interlaced mode
6C Hz mode resets
50 Hz mode interlaced mode

00
10
20
30

Interlaced/non-interlaced mode is determined by the order in which 80/132
column and 50/60 Hz are set. Every time the DCOll is programmed, its
internal timing chain is reset.
Because this will cause the screen to
jump, the DCO 11 should be programmed onl y if absol utel y necessar y.
For
example, the following two instructions will set the DCOll to BO-column, 60
Hz, no interlace:
MOV AX,200CH
OUT LCOll,AX
Note
when eO-column mode is selected, the video
processor is actually capable of displaying 83
columns in single width mode or Li 1 columns in
double .width/height mode.
When 132-column mode is
selected, 137 columns can be displayed in single
width mode or 68 columns in double width/height
mode.
2.1.6.6 DC012 Programming Information - The DC012 videa control chip can
be accessed by the 8088 (~·RITE-ONLY) at I/O address OCH.
The following
codes are defined for the DC012:
Code

Result

00
C1
02
03

set scroll latch LSBs to 00
set scroll latch LSEs to 01
set scroll latch LSBs to 10
set scroll latch LSBs to 11
set scroll latch MSBs to 00
set scroll latch ~lSBs to 01
set scroll latch MSBs to 10
set scroll latch MSBs to 11
toggle blink flip flop
clear vertical frequency interrupt
set reverse field on
set reverse field off
not supported
set basic attribute to reverse video w/ 2Li lines and set
blink flip-flop off.
not supported
set basic attribute to reverse video w/48 1 ines and set
blink flip-flop off.

all

05
06
07
08
09
OA
OB
OC
00
OE
OF

Page 12

PC100 SYSTEM MODULE SPECIFICATION
On power-up, the DCC12 can be programmed to bring it to a known state.
Typically, codes 00, 04, 09, DB, and CD will be programmed at power-up
time.
The value to which the scroll latch is set determines what scan row the
first 1 ine of a scrolling region starts on. Likewise, it determines the
last scan row displayed for the last line in a scrolling region.
For example, when the latch is set to zero (the degenerate case), the first
line of the scroll region starts at scan row zero (so the line is
completely visible).
The last line of the scrolling region terminates at scan row 9 (so this
line is also completely visible).
When the scroll latch is non-zero, for
example 5, the first line of the scrolling region starts with scan row 5
(so only the bottom half of the line is visible).
The last line of the
scrolling region terminates at scan row 4 (so only the top half of the line
is visible).
If on each successive frame, the scroll latch is incremented from 0 through
9 and back to 0 again, the screen appears to smooth scroll from bottom to
top (assuming that line linkages and line attributes are properly handled).
On the other hand, if the scroll latch is decremented from 0 to 9 then down
through C, the screen appears to smooth scroll from top to bottom (again
assuming that all line linkages and line attributes are properly handled).
A scrolling region is defined as a group or lines with their scrolling
attributes set, surrounded by lines whose scrolling attribute is not set.
Note that the scrolling attribute ·.for a line resides in the line pointer
information at the end of the previous line.
Also, the first line on the
screen (the one at RAt-:. location 0), has its scrolling attribute reset by
defini tion. Also note that the definition of a scrolling region does not
preclude the definition of more than one scrolling region per screen,
although that is of dubious value.
Whenever the scroll latch is non-zero, each scrolling region on the screen
requires an extra (scrolling) line to be linked in.
For example, if the
scrolling region is 10 lines long, when the scroll latch is set non-zero
there will have to be an 11th line linked in.
If scrolling up
(incrementing the scroll latch), the line must be linked in at the bottom.
When the scroll latch is incremented back to 0 again, the top line of the
scrolling region must be unlinked.
When scrolling down (decrementing the
scroll latch), new lines must be linked in at the top of the scroll region
and unlinked down at the bottom.
All line linking/unlinking should be done during the vertical blanking
interval (after the vertical frequency interrupt is rung). In 60Hz mode,
there are two blanked lines at the beginning of the screen (the line at RAM
location 0, and the line that it points to).
The first line (at location 0) is guaranteed to have been read by the time
that the interrupt service routine is entered; any changes to this line
will not affect the screen until the next frame time.
Page 13

PC100 SYSTEM MODULE SPECIFICATION
However, the second line will not be read for over 500 microseconds after
asserting the interrupt.
If it is to be changed, it must be changed very soon after entering the
interrupt serv ice routine in order to guarantee that the change will .be
visible in the current frame.
Therefore, if the first visible line on the screen is involved in the
scroll region and is being either linked in or unlinked, then the vertical
interrupt routine must guarantee that its pointer (which resides in the
second invisible line) is changed within approximately 500 usec after the
ringing of the interrupt.
The modification of the scroll latch is much less time critical than this.
Since the scroll latch is loaded by the DC012 by the vertical reset at the
beginning of each frame, the only requirement is that the scroll latch be
modified before the next frame begins.
Note
The scroll latch value is the value that will be
used during the next frame rather than the current
frame.
2.1.6.7 Character Generator ROM - The character generator is a ~K x 8 ROM
with access time < 300 nS. The standard ROM is a 2732A UVPROM.
The ROM
holds 255 characteFs corresponding to character codes C-FE (hex) (character
code FF is reserved for use as a terminator by the video subsystem). The
character codes O-FE correspond to addresses O-FEO in the character
generator ReN (the final hex digit of the address indicates which scan row
of the character is being addressed).
The following table relates the scan number to the scan address:
Scan Address

Character Scan. Number

1 (Normall y blan k)
2 (Top of normal upper case character)

6
7

7
8

9-E

8 (Bottom of normal uppercase character)
9 Normal descenders (Underline scan)
10 Normal descenders
Unused (never displayed)

Each byte of information in the ROM at a valid scan address represents 8
bits of horizontal scan information. The low. order bit is a fill bit; it is
used not only as the rightmost bit in the character bit but also fills in
the right hand space between characters (this inter-character space is two
dots wide in 80 column mode and one dot wide in 132 column mode).

Page

PC100 SYSTEM MODULE SPECIFICATION
Character Generator
Bit Positions
Scan Number

Scan Address
76543210007654321000

1
2

3
4
5
6
7
8
9
10

2.1.7

---#-----------------#-#---------------#---U----#-##,#----

1
2

#-----#---#D----'--HD#'HI#---##----#---

4
5

#-----#---#-####---#-----#---#---------

----------#------------------#---------

7
8

Diagnostic Registers

The following registers are for the purpose of controlling diagnostics for
the PC100.
2.1.7.1 Diagnostic Write Register: 8088 - This write only register (Port
Address OA hex) is used for diagnostic control purposes. Also contained in
this register is a bit for the loopback of all communications transmit
signals to the receive signals.
1.

Bit 0 - This bit is used to reset the Z80A CPU from the 8088 sioe.
This signal is active at power-up.

Bit 1 -

Ei t 2 - lAhen low. mother board
graphics board video is selected.

Bit 3 - When high, this bit enables testing of the parity circuitry
on the optional memory board.

Bit 4
Diagnostic loopback
subhead 2.1.7.4

Bit 5 - Comm. Loopback maintenance bit. See subhead 2.1.7.2.

Bi t 6

- PRCGRAM (write) NVM.

Bit 7

- RECALL (read) NVM.

~hen

reset, the display will be blanked.

v ideo

selected.

when

- see Diagnostic Read Register.

high,

See

2.1.7.2 COMM LOOPBACK Maintenance Bit
The COMM LOOPBACK bit is a
maintenance bit that is cleared on power-up. This bit sets up loopback for
the three serial ports to allow testing.
The port loopbacks are done in
such a way that bit rate errors of one port can be detected by another.

Page 15

PC100 SYSTEM MODULE SPECIFICATION
The following table shows how the signals are routed.
PORT LOOPBACK = 0

PORT LOOPBACK = 1

SIGNAL SOURCE
FROM

SIGNAL SOURCE
FROt-i

SIGNAL INPUT
TO

COIJJM RCV DATA
PRT RCV DATA
KBD ReV DATA

COMl-i TXD
KBD TXD
PRT TXD

COMM RXD
PRT RDATA
KBD RXD

2.1.7.3 DIAGNOSTIC LOOPBACK Maintenance Bit - The DIAGNOSTIC LOOPEACK bit
is a maintenance bit that is cleared on power-up. This bit, when set to 1,
allows the floppy data separator and the serial video output to be tested
through the use of the printer port. The following table shows how the
signals are routed.
DIAGNOSTIC LOOPBACK = 0

DIAGNOSTIC LOOPBACK = 1

SIGNAL SOURCE
FRO/o'j

SIGNAL SOURCE
FROM

PRT RDATA (J2)
PRT RXTXC
MASTER CLK
FLOPPY RAW DATA

VIDEO OUT
500 KHZ
250 KHZ
PRT TXD (7201)

SIGNAL INPUT
TO
PRT RXD (7201)
PRT liXTXC (7201)
VIDEO CLK (DCOll)
FLOPPY DATA SEPARATOR

During Diagnostic Loopback, the -TEST input of the 8088 is connected to the
interrupt output of the MPSC. Thus, using the 8088's WAIT instruction in a
polled 1/0 loop, the diagnostic firmware will be able to keep up with the
500 Kb data rate on the MPSC.
2.1.7.4 Diagnostic Read Registe.r: 8088 - This register (Port address OA
Hex) is used to read a select number of signals for diagnostics.
1.

Bit 0 - This bit represents the state of bit 0 of the Diagnostic
Write Register (Z RESETL).

Bits 1-3 - Manufacturing test straps.

Bit 4 - Represents the state of bit 4 of the
Register. (Diagnostic loopback H)

Bi t 5 - This bit represents the state of bit 5 of the Diagnostic
Write Register (port loopback H).

Bit 6
This bit represents the state
Diagnostic write Register (PROGRAM NVM).

the

bit

6 of

the

Bi t 7
This bit represents the state of
Diagnostic Write Register (RECALL NVM).

the

bi t

7 of

the

Page 16

Diagnostic

~r i te

PC100 SYSTEM MODULE SPECIFICATION
2.1.7.5 General/Diagnostic Control/Status Register: Z80A
This
register/buffer holds a variety of information bits for the Z80A.
2.1.7.5.1

8-bit

General/Diagnostic Control - Z80A Port Address 21 (and 20)Hex -

ZFLIP L - ~hen this signal is low, address line 15 of the Z80A is
inverted.
In this case, the 2K unshared RAt'. appears at address
8000 rather than at O.
The signal is low whenever the Z8CA is
reset. It can be set high by writing to the general/diagnostic
control register at 21 hex. It can be reset by writing to address
20 hex.

Bits 0 - 3 - These bits are connected to the dig i tal
converter. (Future option).

Bits 4 - 6 - These bits are connected to the LEDs.

2.1.7.5.2

to analog

General/Diagnostic Status Register - ZeOA Port Address 21 Hex -

Bit C - ZFLIP L - This bit is the read back for
General Diagnostic Control Register.

ZFLIP L in the

Bit 1 - INTZ80L - This bit reads the INTZaO bit that is sent by the
80P8 to interrupt the Z80A.

3·

Bit 2 - INT88L
This bit reads the INTS8 bit that is sent by the
ZeOA to interrupt the 8088.

Bit 3 - Status of the READY L coming from the floppy.

Bit 4 - This bit reflects the status of the DIRECTION signal from
the 1793 going to the floppy. Used to control step direction.

Bit 5 - This bit reflec~s the status of the TRACK 0 signal coming
from the floppy. Indicates the head is on the track 0 position.

Bit 6 - This bit reflects the status of the WRITE GATE signal from
the 1793. Used to gate write pulses to the floppy drive.

Bi t 7 - This bit reflects the status of the STEP signal from the
1793 which is used to step the floppy read/write head in or out on
the drive.

2.1.7.6 Printer Port Interface - This is a general purpose printer port
provides an RS423 interface compatible with DEC printers.
EIA
signals supported are:
~Jhich

•
•
•
•
•

Transmit Data
Receive Data
Data Terminal Ready
Clear to Send always asserted
Data Set Ready al ways asserted
Page 17

PC100 SYSTEM MODULE SPECIFICATION
Software programmable bit rates supported are:
•
•
•
•
•
•

75
150
300
600
1200
2400

•

9600

•

lIeoo

Software-programmable character formats supported are 5-8 bits/character
with 1, 1-1/2, or 2 stop bits/character. Parity may be selected as odd,
even or none . Software should support XON/XOFF restraint protocol for this
port. The D-type 25-pin female EIA printer connector physically resides on
the mother board in the normal printer port location and att~ches directly
to a printer. No null modem is necessary. DSR and CTS are always asserted.
Printer Port Interface Connector
Pin No.

Signal Description

Mnemonic

Direction

1
2
3
5

Protective Ground
Transmi t Data
Receive Data
Clear to Send
Data Set Ready
Signal Ground
Data Terminal Ready

PROT GND
TXD
RXD
CTS
DSR
GND
DTR

------

7
20

Input
Output
Output *
Output *

-----Input

Note
*This output is

~lways

asserted high.

2.1.7.6.1 Printer Bit Rate/Communication Clock Source Register - Bits 0,1,
and 2 of this write-only register specify the printer bit rate (16X clock)
according to the following table:
Bit Rate Of 16X Clock
75
150
300
600
1200

C
0

0
0

0
1
0
1
0
1
0

Li800

1
1

9600

21100

Page 18

1
0
0

PC100 SYSTEM MODULE SPECIFICATION
Bit D3 specifies the communication clock source as follows:
Source

Internal
External

0
1

2.1.7.7 Communications Port - This port is used to communicate to another
computer.
It has full modem support and supports the same signals as the
VT1C2. U.S. and European full- and half .. duplex modems can be supported by
this port.
The port has ASYNC as well as BISYNC modes with a RS423
(V.21.1/V.28) physical interface conforming to CCITT V.21. V.22 and V.23.
Break detection by this port is supported.
The bit rates are set by writing iii byte to port 6. The low nibble of the
byte (DO - 03) controls receive btt rate and the high nibble (04 - D7>
controls the transmit bit rate aCQQrd~ng to the following table:
Nibble
Value

Bit
Rate

Nibble
Value

Bit
Rate

0
1

50
75
110

8
9
A

1200
1800
2000
2400
3600
4800
9600
19200

131j.~

1.1

150
200
30Q
600

C
0
E
F

All bit rate~ are software sel~Qt~bl@.
Transmit and receive bit rates may
be selected independently from the ~v~ilable bit rates.
Signals supported
are:
1.
2.
3.

Receive Data
Transrni t Data
Secondary Transmit Data
11.
Request to Send
5. Secondary Request to Send
6.
CI ear to Send
7.
SeQondary Clear to Send
8.
Receive Line Signal Detegt;.
9. SecOndiilry Receive Line ~ign~l Detect/Speed Indicator (Bell 212A)
10. Ring 11"10 i e a t o r "
11. Datp Set Ready
12. Speed Sehct,

ppge 19

PC100 SYSTEM MODULE SPECIFICATION
2.1.7.7.1 Communications Status Register: 8088 - The following read-only
register (Port Address 02 hex) holds the status of the modem control lines
on the COMM's port and two interrupt lines, one from each CPU.
1.

Bit a - This bit reflects the status of the Ring Indicator line Df
the communications port.

Bit 1 - This bit reflects the status of the Speed Indicator line or
the Secondary Receive Line Signal Detect of the communications
port.

Bit 2 - This bit reflects the status of the Data Set Ready line of
the communications port.

lJ.

Bit 3 - This bit reflects the status of the Clear To Send line of
the communications port.

Bit lJ - This bit reflects the status of the Receive Line Signal
Detect of the communications port.

Bit 5 - This bit reflects the status of MHFU Enable L.

Bit 6 - This bit reflects the status of the INT 88 L bit which is
generated by the Z80A to interrupt the 8088 CPU.

Bit 7 - This bit reflects the status of the INT Z80A L bit which is
generated from the 8088 to interrupt the Z80A CPU.

2.1.7.7.2 Communications Control Register: 8088 - The following write-only
register (Port Address 02 hex) controls the modem lines on the COMM port as
well as four LEOs.
1•

Bit 0
This bit
communications port.

con t r 0 I s

the

S pee d

Bit 1 - This bit controls the Secondary Request To Send line of the
communications port.

3·

Bit 2 - This bit controls the
communications port.

lJ.

Bit 3
This bit controls
communications port.

Bit lJ

Bit 5 - When written with a 0, lights a LED.

Bit 6 - When written with a 0, lights a LED.

Bit 7 - When written with a 0, lights a LED.

Data

the

Terminal

Request

When written with a 0, lights a LED.

Page 20

Se Ie c t

lin e

0 f

the

Ready line of the
Send

line

the

PC100 SYSTEM MODULE SPECIFICATION
2.1.8 Massive Hardware Foul-up Detection
There is a watchdog timer on the mother board which is intended to detect
situations in which the 8088 has lost most of its sanity. If the 8088 does
not acknowledge the vertical frequency interrupt within approximately 1.08
milliseconds, a reset signal is applied to the 8088 for lOa milliseconds.
This causes the 80e8 to begin executing code at FFFF:O.
MHFU detection is disabled by writing to the DC012 at port address 10C- hex.
It is enabled by writing the DC012 at port address OC hex. The
enable/disable status may be read from bit 5 of the communications status
register (port address 02). When the firmware begins executing at location
FFFF:O, it should assume a power up reset if NHFU is disabled, and a hHFU
reset if MIIFU is enabled.

2.2

ZaOA SYSTEM

The following describes the section of the system controlled by the ZeOA.
2.2.1 ZaOA CPU
The module includes one ZaOA microprocessor, which runs from a clock of
4.012 MHz. The ZaOA alone has access to the floppy disk interface and thus
is responsible for controlling the floppy (via programmed lIO) for all
applications.

2.2.2 Z80A Shared Memory
The
and
the
the

ZeOA has available to it 64 KB RAN which is divided into 62 KB shared
2KB unshared memory. Accesses to the shared portion of memory select
corresponding address in the, standard bank of 64K DRAHS. Accesses to
un shared memory select a private 2Kx8 byte-wide static RAM.

2.2.3 Z80A Private RAM
The unshared RAM may be accessed by the ZeOA at any time without any wait
states. If the shared RAM is "busy" at the time of a Z80A access, the Z80A
will execute wait states until the RAt'. is free. The RAM is considered
"busy" when an 8088 cycle or a refresh cycle is in progress or is pending.
In addition to wait cycles due to contention, all M1 cycles from the shared
RAtt. have one extra wait cycle due to the timing for this sort of machine
cycle. In any case, the ZaOA is held in a wait state for no longer than 2.5
microseconds, unless the bundle board causes contention. If both processors
are executing out of the shared memory, the Z80A cannot reliably access the
floppy disk (i.e., lost data errors will often result).

Page 21

PC100 SYSTEM MODULE SPECIFICATION
2.2.4 Z80A I/O Map
Port

00£1
OOH
21H
21£1
40B
40H
60H
60H

Function
Clear Interrupt to ZeOA (Read)
Interrupts 8088 (Write)
Lisk Diagnostic Read Register
Disk Diagnostic Write Register
Disk Control Read Register
Disk Control ~rite Register
FDC Status Register
FDC Control Register
FDC Track Register
FDC Sector Register
FCC Da ta Register

6HI

62£1
63H

RO
WO
RO
WO
HO

WO
R/W
H/W

R/W

Note
The above Z80A I/O ports are re-mapped within their
own pages and are also re-mapped starting at BOH.
~riting
Diagnostic Write Register at address 21H
will reset ZFLIP.
Writing the Diagnostic ~rite
Register at address 20£1 will set ZFLIP.

2.2.5

Z80A Memory Map

Figure 3 shows the ZeOA memory map:
Z FLIPPED

Z NOT FLIPPED

FFFF:

FFFF

7FFF FFFF

SHARED RAl-'l

SHARED HAl-';

8000:

FFFF

,,
800:

----------~-------------

: PRIVATE

0: -------8088

8800

800

8000

PRIVATE

Z80

800
PRIVATE

PRIVATE

8088

Z80

Figure 3. Z80A Memory Map
Page 22

PC100 SYSTEM MODULE SPECIFICATION
2.2.6

ZaOA Cycle Time

The clock time on the Z80A is 249.2375 nS.
Unshared memory accesses have
no wait states. Shared memory accesses have wait states on M1 cycles and
for cycles in which there is contention between devices accessing t·he
shared RAM. Contention exists because of refresh cycles and 8088 cycles.

2.2.7

ZaOA Interrupts

The only interrupts are interprocessor interrupts from the 8088 CPU. The
vector placed on the bus is F7 (hex) which causes a RST 30 instruction to
be executed in interrupt mode O.

2.2.a

Floppy Controller Module

The floppy controller module is not optional.
connects to the mother board via J7.

It is a

separat~

module that

The interface is designed to control up to four 5-1/4 inch (Jlatters with
one or two surfaces. The controller supports soft-sectored double-density
diskettes using a PLL circuit. Single- or double-sided drives are
supported. The interface adheres to drive capability and signal definition
of the ANSI standard interface for mini-floppy drives.
The floppy controller block diagram is shown in Figure 4.

2.3

Z80A/8088 INTERRUPT FLAGS

Each CPU has a D-type flop that is used to interrupt the other CPU.
1.

INT ZeOA flag is set when the 8088 writes to I/O port C. The flag
can be cleared by the Z80A only via a read of I/O port C. The data
is irrelevant. The firmware should clear this flag on power-up.

The flag
INT 88 flag is set when the Z80A writes to I/O port O.
can be cleared by the 8088 only via a read of I/O port O. The data
in either case is irrelevant. The firmware should clear this flag
on power-up.

Page 23

pelOO SYSTEM MODULE SPECIFICATION

+-----+
+--STATUS
: F
CPU CONTROL ----------------->: L
o -------<----------------FLOPPY---->+-----------+
: DATA
:------>:
DATA->:MTIX:: SEPARATOR:
-...-

:+-----------+
'---------------------.
+--------+
DIAGNOSTIC --->: PULSE : :

LOOPBACK
DATA
ZPO

+---------+
+---+
->: WRITE
:--->:
F
: PRECOMP :
L
+---------+
,

P
P
Y

CONTROL SIGNALS : 0
----->-+------- >' P

R
L
E

DATA BUS ---<--->---+------

: SHAPER :--+
+--------+

R
X

D
I
S
K

+-----+

: +-------------+ :
+-<-: DIAGNOSTICS :<-+
BUFFER
+-------------+

: +-------------+
CONTROL
:

D
R
I

V
E
R
S

I
V
E

:
LATCH
:----------->:
AND DRIVE
:
:
,
SELECT
+---+
+-------------+

+->- :
I

: +-------------+
:
STATUS
:<-------------------:

+-<-:

BUFFER

+-------------+
Figure~.

Floppy Controller Block Diagram

Page

+---

PC100 SYSTEM MODULE SPECIFICATION
3.0

CONNECTOR PINOUTS AND DESCRIPTIONS

3.1

POWER INTERFACE CONNECTOR

The power connector on the mother board is a 13-pin in-line connector with
the following pinout:

ACOK

This signal ind icates the presence or absence of val id ac
power enter ing the power suppl y.
when valid ac power is
present, this signal will be high (open circuit) and when the
ac power is lower than the required minimum input voltage,
this signal will be low (short circuit to logic ground).

UNUSED

Key

This pin must be missing from the mother board.

-12V OUT

5,6

+12.1V OUT

7,8,9

+5.1V OUT

10, 11 ,
12, 13

DC Power Return Signal Ground

3.2

VIDEO INTERFACE CONNECTOR

This connector is a 15-pin D-type female connector supplying interface
signal s and power to the PC 100 mon i tor and ke yboard wi til the following
pinout:
Pin
1

2
3
4

5,6
7,8
9
10

11
12
13, 14
15

Name
Blue Shield
Green Shield
Red Shield
~;ono Shield
GND
+12V
Blue
Green
output
Red
Mono video
KBD TX data
KBD RCV data

Description
Ground connector for b'~e gun shield
Ground connector for green gun shield
Ground connector for red gun shield
Ground connector for B/W video gun shield
+12V returns
+12V DC to monitor and keyboard
Composite blue gun output
Composite green gun output; also monochrome text
Composite red gun output
Composite B/W video output
RS423 serial data to keyboard
RS423 serial data from keyboard

Page 25

PC100 SYSTEM MODULE SPECIFICATION

3.3

EXTENDED COMMUNICATIONS OPTION CONNECTOR

The extended communications option uses two LjO-pin connectors.
Table 1 for pin numbers and signals:

Refer to

Table 1 • Extended Communications Option Connectors
JLj
Pin No.
2
3
Lj
5
6

9
10
11
12
13
111
15
16
17
H'

19
20
21
22
23
211
25

J5
Signal

Pin No.

INIT L
-12 V
EXCOMKS PRES L
+12 V
DMAC INTR L
GND
EXCOMMS SEL 1L
+12 V
EXCOMNS REO L
Not used
Not used
+5 V
Not used
+5 V
Not used
+5 V
Not used
GND
Not used
GND
Not used
GND
Excmms INTRL L
GND
EXCOt-iIvlS ACK L

1
2
3
Lj
5
7
8
9
10
11
12
13
111
15
16
17
18
19
20
21
22
23
211
25

BADO
SHDO
BAD1
SHD1
BAD2
SHD2
BAD3
SHD3
BADll
SHDll
I:!AD5
SHD5
bA))6
SHD6
BAD7
SHD7
AO
SHNAO
A1
SHMA1
A2
SHt-'iA2
A3
SHNA3
EXCONES

GND
2.5 MHZ
GND
05A H
tlot used
05C L
Not used
BWR 88 H
Not used
BRD Be H
Not used
05C H
Not used

26
27
28
29
30
31
32
33
311
35
36
37
38

SHHAlJ
+5 V
SHNA5
+5 V
SHMA6
+5 V
SHMA7
GND
SHRAM RAS L
GND
SHRAM CAS L
GND
EXCOI'IMS SH wR

Not used
e H

39
llO

Not used
Not used

26
27
28
29
30

31
32
33
311
35
36
37
38
L
39
llO

Signal

Page 26

SEL

PC100 SYSTEM MODULE SPECIFICATION
3.~

MEMORY OPTION CONNECTOR

The memory option connects to the mother board via a 52-pin connector (J6).
Table 2 lists the pin numbers, signals and dc loading.
Table 2. Memory Option Connector
J6
Pin No.
1
2

5
6

9
10
11
12
13
1L1

15
16
17

18
19

Signal

DC Signal Load
(mA/uA)

GN])
GND
GND
RAS68H
RESERVED
A6
A15
A1
A13
M!.
A3
A10
AD
A14
A7
A2
A5
A9
A12

~1UXeBH

21
22
23
211
25
26
27
28
29
30
31
32
«
34
35
36
37
38
39
40
41
42

A11
All
RFSH RAS H
PARITY TEST H
+5 V
PARITY ERROR L
+5 V
+5 V
MEt'.ORY PRESENT L
ADDRESS EN L
DO RFSH L
S64K2 L
RFSH DONE H
naT L
+5 V
BAD7
CAS88H
BAD6

_oJ

R/-DT

BAD5
BRD88H
BAD4

-12/300
-2140

-2/40
-2/40
-2/40
-2/40
-2/40

-2/40
-2/40

-2/110
-2/110

-2/40
-2/40
-8/200
-2/110
-2/40
-6/150
-.4/20
+8/-400
(GROUND)
-2/50
-.4/40
-2/50
-1.6/40

-2/50

*-1012 50
*-.6/40
*-4.4/120
*
Page 21

PC100 SYSTEM MODULE SPECIFICATION
Table 2. Memory Option Connector (Continued)
J6
Pin No.

4-::-,
4 I.!
lJ• ..
J

46
47
48
49
50
51
52

Signal

DC Signal Load
(mA/uA)

S64K3 L
BAD3
BWR8€ H
BAD2
S64K1 L
BAD1
GND
BADO
GND
GND

-2/50

*-10/250
*
-2/50
*
*

Note

.OFF STATE = -200 uA/.10 uA; ON STATE = .24 mA/-15 mA
3.5

COMMUNICATIONS INTERFACE CONNECTOR

Pin Number
1
2
3
4
5

6
7
8

10
11
12
13
14
15
16
17

18
19
20
21
22
23
24
25

Mnemonic

Signal Description
Protect ive Ground
Tr ansrn i t Data
Receive Cata
Request To Send
Clear To Send
Data Set Ready
Signal Ground
Receive Line Signal Det.
Not Used
Not Used
Not Used
Speed Indicator/Secondary
Receive Line Signal Det.
Second ar y Cl ear To Send
Secondary Transmit Data
Send Clock
Not Used
Receive Clock
Not Used
Secondary Request To Send
Data Terminal Ready
Not Used
Ring Indicator
Speed Select
Not Used
Not Used
Page 28

PROT GND
XHIT DATA
REC DATA
RTS
CTS
DSR
GND
RLSD
N/U
N/U
N/U
SI/SRLSD
SCTS
SXMIT DATA
SEND CLK
N/U
REC CLK
N/U
SRTS
DTR
N/U
RI
SPDSEL
N/U
N/U

PC100 SYSTEM MODULE SPECIFICATION
4.0

POWER REQUIREMENTS
1.
2.

5.0

+5 Vdc +1- 5% @ 4.0 A max.
+12 Vdc +1- 10% @.3 A max.
-12 Vdc +1- 101 @ .3 A max.

PHYSICAL DIMENSIONS - MODULE

The mother
connectors:
J1
J2
J3
J4
J5
J6
J7
J8
J9

board

modified

module

Communications Connector 25-pin
Printer Connector
25-pin
Videc/Keyboard Connector 15-pin
Extended Comms Connector 40-pin
Extended Comms Connector 40-pin
Memory Option Connector 52-pin
Graphics Option Connector 40-pin
Power Connector
13-pin
Floppy Controller Pin
40-pin

The dimensions are: 10.4 inch high;

6.0

hex

with

the

following

nine

D-male
D-female

14.0 inch long; 1.0 inch high

RELIABILITY GOALS

The module will meet a 12,00C hour MTBF.

1.0

SYSTEM MODULE ENVIRONMENTAL SPECIFICATIONS

8.0

APPLICABLE STANDARDS
DEC STD 102

Environmental Standard, Class B

UL 478

Electronic Data Processing Units and Systems

CSA C22.2,

Canadian Electronic COde, Part II, Safety
Standards for ElectrIcal EquIpment

lEC 485

Safety of Data Processing Equipment

EIA RS170

Electrical Performance Standards Monochrome Television Studio Facilities

Page 29

PC100 SYSTEM MODULE SPECIFICATION

9.0

CCITT Recommendation V.24

List of Definitions for Interchange Circuit
Between Data Terminal Equipment and Data
Circuit Terminating Equipment

CCITT Recommendation V.28

Electrical Characteristic for Unbalanced
Double-Current Interchange Circuits

DEC STD 119

Product Safety Standard

DOCUMENTS SOURCE
1.
2.
3.
4.
5.
6.
7.
8.
9.

Zilog's Z80A CPU Specifications
Zilog's Z80A Technical Manual
Zilog's Z80A Programming Manual
Zilog's Z80A CPU Programmer's Reference Guide
In tel's 8251 A Programmable USART Specifications
Intel's iAPX 86, Be User's Manual
Intel's iAPX 88 Book
CEC VT100 Technical t-ianual (information) (DCOll and DC012 Technical
Description)
Intel's Peripheral Design Handbook (8251 and 8274 programming
information)

Page 30

RainbowTM 100
PC100 System
Module Specification
AA-V523A-TV

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