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AA-P308A-TV

March 1983

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Document:	Rainbow 100 PC100 System Specification
Order Number:	AA-P308A-TV
Revision:
Pages:	108
Original Filename:	http://bitsavers.org/pdf/dec/rainbow/AA-P308A-TV_Rainbow_100_PC100_System_Specification_Mar83.pdf

OCR Text

AA-P308A-TV

RainbowTM

100
PC100 System Specification

digital equipment corporation

First Printing, March 1983
© Digital Equipment Corporation 1983. All Rights Reserved.

The information in this document is subject to change without notice and should
not be construed as a commitment by Digital Equipment Corporation. Qigital
Equipment Corporation assumes no responsibility for any errors that may
appear in this document.
The software described in this document is furnished under a license and may
only be used or copied in accordance with the terms of such license.
No responsibility is assumed for the use or reliability of software on equipment
that is not supplied by DIGITAL or its affiliated companies.
CP/M®, CP/M®-80 and CP/M®-86 are registered trademarks of Digital
Research Inc.
Z80® is a registered trademark of Zilog, Inc.
8088® is a registered trademark of Intel Corporation.
The following are trademarks of Digital Equipment Corporation:

~D~DD~DT.
DEC
DECmate
DECsystem-10
DECSYSTEM-20
DECUS
DECwriter
DIBOL

MASSBUS
PDP

P/OS
Professional
Rainbow
RSTS
RSX

UNIBUS
VAX
VMS
VT
Work Processor

The postage-prepaid READER'S COMMENTS form on the last page of this
document requests the user's critical evaluation to assist us in preparing future
documentation.

Printed in U.S.A.

11/88-15

TABLE OF CONTENTS/REVISION STATUS

··········4

1.0

SYSTEM OVERVIEW

2.0
2.1
2.2
2.3

BASE SYSTEM
BA25
VR201-A MONITOR
LK201-AA KEYBOARD

3.0
3.1
3.1.1
3.1. 2
3.1. 3
3.1.3.1
3.1.3.2
3.1.3.3

SYSTEM MODULES
• • •
MOTHER BOARD •
Mother Board Block Diagram
8088 System • • ••
8088 Memory
• • • •
Shared Memory
• • • •

3.1.3.4
3.1.3.5
3.1.3.6
3.1.3.7
3.1.3.8
3.1.3.9
3.1.3.9.1
3.1.3.9.2
3.1.3.9.3
3.1.3.9.4
3.1.3.9.5
3.:\..3.10
3.1.3.11
3.1. 4
3.1.4.1
3.1.4.2
3.1.4.3
3.1.4.4
3.1. 5
3.1.5.1
3.1.5.2
3.1.5.3
3.1.5.4
3.1.5.5
3.1.5.6
3.1.5.7
3.1.5.8

4
..··
·
·
4
. . · · · · · · · ·· ·· 45
··········

......

ROM

•

• .•

•

• •
• • • • •
•
•
•

•
•
•
• • • • • •

•
•
•
•

5
5
5
7

• • 7
• • • • . • 7
8

4KB Screen Memory And 4KB
Attribute Memory • • • • •
• • • • • • 8
• • 8
256 x 4 NVM With Shadow RAM •• • •
Unshared Dynamic Memory (optional)
•• 9
8088 I/O Map • •
• • • • • • 9
8088 Memory Map
• • • • • • • 9
8088 Interrupts • • • • • • • •
11
Video Subsystem: 8088 • • • • • • • • • • 11
General Video Features • • • • •
11
Video Memory
•••••••••
11
Video Processor (DCOll And DC012) • • • • 11
DC011 Programming Information • • • • •• 13
DC012 Programming Information • • • • •• 14
Keyboard Interface • • • • • • • • • • •• 15
Printer Port Interface •
• • • • •• 17
MPSC Overview • • • • •
• • • •• 18
Asynchronous Operations • • • • • • • •• 18
Communications Port
• • •• 20
Synchronous Operation • • • • • • •
22
Synchronous Operation -- SDLC -23
General • • • • • • • • • •
24
Z80A System • • • •
••• •
24
Z80A CPU • • • • • •
••• •
24
Z80A Shared Memory •
24
Z80A Private RAM
•••••
Z80A I/O Map • •
• • • • • • • • 25
25
Z80A Memory Map
• • • • •
Z80A Cycle Time
• • • • • • • • • • 26
26
Z80A Interrupts
• • • • • • • •
Floppy Controller Module • • • • • • • • • 26

iii

CONTENTS (Cont.)

3.1.5.8.1

3.2.3.1

Floppy Disk Controller
Registers: Z80A
General Control and Status Register
Bit Discription: Z80A
General Floppy Control
Register: Z80A • • • • • • •
Drive Select Light Operation.
General Floppy Status
Register: Z80A • • • • • • •
Floppy Disk Controller
Required Delays • • • • • •
Floppy Disk Motor Speedup
Detection • • • • . •
Floppy Controller Head Load
Timer Activation • . • •
Mother Board Physical
Dimensions • • • . . • •
OPTION MODULES • • • • • •
Memory Option • • . . • • • • • • • •
Extended Communications Option
Description/Features • • • • •
Reset Sequence For Extended
Communications • • •
Graphics Option Description/Features
Features • • • • • •

4.0
4.1
4.2
4.3
4.4

RX50 DRIVE • • • • • • •
GENERAL DESCRIPTION
DRIVE CHARACTERISTICS
TRACK FORMAT •
HEADER FORMAT

41
41
41
42
43

5.0

PCIOO FIRMWARE •

6.0
6.1
6.1.1
6.2
6.3
6.4
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.6

43
43
44
48
48
48
50
50
58
58
59
59
59

6.7

PRODUCT GOALS
GOALS
Functional Anomalies • •
PERFORMANCE
NON-GOALS
GENERAL
Text Strings •
Character Sets • • • • •
START-UP/SHUT-DOWN/RESET •
Power-Up Initialization
Power-Off • • • • • • •
Hardware Resetting • . .
RAM Parity Error • • . .
MEMORY-MAPPED VIDEO ACCESS
SERVICE • • • • • . •
KEY ACCESS SERVICE • • •

7.0
7.1
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.2
7.2.2.1

FUNCTIONAL DEFINITION
OPERATIONAL DESCRIPTION
TRANSMITTED CHARACTERS • •
Un-Seen Fixed Function Keys
Hold Screen • • • •
Set-Up • • • •
Fixed Function Keys
ESCAPE •
••••

61
61
62
62
62
63
63
63

3.1.5.8.2
3.1.5.9
3.1.5.9.1
3.1.5.10
3.1.5.10.1
3.1.5.10.2
3.1.5.10.3
3.1. 6
3.2
3.2.1
3.2.2
3.2.2.1
3.2.3

28
35
35
36
36
37
37
37
38
38
38
38
40
40
41

59
61

CONTENTS (Cont.)

7.2.2.2
7.2.2.3
7.2.2.4
7.2.2.5
7.2.2.6
7.2.2.7
7.2.2.8
7.2.2.9
7.2.3
7.2.4
7.2.5
7.2.6
7.2.6.1
7.2.6.2
7.2.7
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.4.1
7.4.2

LINE FEED
BACKSPACE
SHIFT
••••
CONTROL • • • •
LOCK • • •
TAB
RETURN •
DELETE •
Alpha and Symbol Keys
Keypad Keys
Cursor Arrow Keys
Special Function Keys • • • •
Print Screen • •
Break Key
Function Keys • • . •
RECEIVED CHARACTER PROCESSING
Received Character Processing
ANSII Mode Control Functions
Operational Variations • . . .
Terminal Reports • • . • • • • •
Terminal Reset • • . • • • • .
VTl02 CONTROL OF ATTACHED DEVICES
Modem Control
• • . • • • • • •
Printer Control

63
63
63
63
63
64
64
64
64
64
64
65
65
65
65
68
68
68
69
69
69
69
70
70

8.0
8.1
8.2
8.3

EXTERNAL INTERACTIONS AND IMPACT •
OPERATING SYSTEM • • . • • •
STACK OVERHEAD • • • • • • •
STACK USE BY APPLICATIONS

74
74
74
75

9.0
9.1
9.1.1
9.1.1.1
9.1.1.2
9.1.1.3
9.1.1.4
9.1.1.5
9.1.1.6
9.1.1.7
9.1.1.8
9.1.1.9
9.1.1.10
9.1.1.11
9.2

VTl02
SET-UP • • •
Set-Up Display and Operation
Help Field • •
Answerback Field .
Tab Setting Field
Parameter Major Field
Modem Field . . • •
Printer Field
Miscellaneous Field
Memory Size Field
Storing the Set-Ups
Using Default Set-Ups
Recalling Stored Parameters
RESET TECHNIQUE

76
76
77
78
79
79
79
80
80
80
80
81
81
81
81

10.0
10.1

INTERFACE LAYER
SOFTWARE INTERRUPT TYPE 40
(DECIMAL)
••••
•••••
Console Out
• . • •
Level 2 Console In • • • •
Level 2 Console In Status • .
Level 1 Console In •
Disable Cursor • • •
•
Enable Cursor
• • • • • •
Initialize Interrupt Vectors •
Return Clock Rate • • • • • •
Set Keyboard LEDs
• • • •
Clear Keyboard LEDs
Send Data To Screen

10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
10.1.6
10.1. 7
10.1.8
10.1.9
10.1.10
10.1.11

• •
• • •
• • •
• •

81
82
82
83
83
85
85
85
86
86
87
87

CONTENTS (Cont.)

10.1.12
10.1.13
11.0

INIT 7201 TO NVM PARAMETERS • • • • •
Raw Keyboard Data • • • • • •

IMAGE OF Z80 RAM SPACE TO BE
LOADED • • • • • • • • • • •

12.1

BOOT LOADER TO READ TRACK 0,
SECTOR 1 OF FLOPPY • • •
BOOT PROCESS • • • • •

89
90

13.0

MENU SELECTION PROCESS

14.0

SYSTEM PARAMETER INFORMATION •

15.0
15.1

POWER SUPPLY • •
POWER CONNECTOR

93
93

16.0
16.1
16.2

95
95

16.3
16.4
16.4.1

CONNECTOR OUTPUTS • • • • •
VIDEO INTERFACE CONNECTOR
COMMUNICATIONS INTERFACE
CONNECTOR • • . • • • • • •
Communications Signal
Descriptions • • • • • •
• • • •
PRINTER PORT INTERFACE CONNECTOR •
FLOPPY INTERFACE CONNECTOR •
Floppy Signal Descriptions •

17.0

OPTIONS

18.0

CABLES • •

19.0

ENVIRONMENTAL SPECIFICATIONS •

20.0

RELIABILITY

21.0

PHYSICAL PACKAGING •

• • • • 101

22.0

VIDEO CHARACTER SET

• • 101

23.0

APPLICABLE STANDARDS AND
REGULATIONS

12.0

16.2.1

96
98
98
99
• 100

• • • • lOO
• • • lOl

• 101

101

FIGURES
FIGURE

1
2
3
4
5
6
7

6
···
·
10
· · 20
·········
··
·
· · · · · · · · · . · · · . 23
. . . · · · · · · · · . · · · 2425
· · · · · · · · · · · · · 27
···

Mother Board Block Diagram
8088 Memory Map
Asynchronous Mode Register Setup
Synchronous Mode Register Setup -Monosync, Bisync
Synchronous Mode Register Setup -SDLC/HDLC
Z80A Memory Map
Floppy Controller Block Diagram

FIGURES (Cont.)

2
3
4
5
6

7
8

. · · · · · · · · 71
72

"Terminal" Mode "Off-Line"
"Terminal" Or "Console" Mode "Set-Up" •
"Terminal" Mode "On Line"
No Printer Functions
"Terminal" Mode "On Line In
"Printer Controller
Terminal Mode On Line
Printing From Screen
Console Mode
·
Set-Up Mode Header Display
Modem Major Field Display

·.

·····
· 72
.···
· 73
·· ·· ·· ·· ·· · · ·· 73
74
...··.
· 78
· 80

TABLES
TABLE

2
3

Command Summary
Displayable Characters and
Corresponding Code
Function Codes

. . ·· ·

vii

· · · · · · · · 28
51
· · · · · · 82
····
·

PC100 SYSTEM SPECIFICATION
1.0

SYSTEM OVERVIEW

The PC100 system is a low-cost user installable personal business computer
used to run applications in the Fortune 1000 marketplace. The PC.l00
prov ides hard ware and so ftware support for both stand-alone processing and
as a terminal emUlation for DEC and other computer manufacturer's systems.
The PC100 is designed to be used by users with no prior computer
experience. Applications software include packages designed by third party
software houses.

2.0 BASE SYSTEM
The base system consists of the following components:
2.1

BA25

The BA25 is the system nucleus.
The multi-box is the primary housing for
the system, and encloses the following components:
a.

PC100 System Module - The basic intelligence of the system and
provides the means for interconnection of all options. This module
includes the following features:
o
o

o
o
o

o
o
o
o
o
o
o
o
o

2.2

8088 CPU
Z80A CPU
64KB shared dynamic memory
24KB ROM
256 x 4 NVM
VT100 ~ompatible DC011, DCC12 video electronics
Async/Bisync communications port
LA50, LA100, LA12 Pr.inter Port
LK201 Keyboard interface
RX50 Floppy controller
Option expansion capability
Extended communications
Color graphics
Extended memory (64/192KB)

RX50 Mini-Floppy Drive - A dual platter mini-floppy drive system
which is the main storage area for the system.

H7842A Power Supply - A 140 W switching regulator power supply with
a switch selectable 115/230 V primary circuit.

VR201-A MONITOR

A 12-inch diagonal composite monitor that supplies video information to the
user, as well as an interconnect means for the keyboard.

Page 4

PC100 SYSTEM SPECIFICATION
2.3

LK201-AA KEYBOARD

An ergonomic keyboard supporting 105 keys.
This is interconnected v ia a
coiled cord terminated in a four-conductor telephone plug.

3.0 SYSTEM MODULES

3.1

MOTHER BOARD

The PC 100 includes a two-processor architecture based on the simultaneous
operation of an 8088 and a Z80A CPU. These CPUs operate from and transfer
data through a shared block of 62KB of RAM. In addition to this block of
shared memory, each processor has its own memory and peripheral circuitry.
Note
Because the floppy controller module is an integral
part of the system, it is incl uded in the mother
board section.
In addition to running application/user software, each processor supports a
portion of the needed functions of the computer. The Z80A processor
performs the functions required to read/wr ite the floppy disks. The 8088
handles the video output, keyboard I/O, printer port and the communications
as well as any other options.

3.1.1 Mother Board Block Diagram
The Mother Board Block Diagram is shown in Figure 1.

Page 5

PC100 SYSTEM SPECIFICATION

+----------------------INTERRUPT-----------------------------------+
+--------+
Z80A

I
I

1------1
I

+--------+

B
I
T

+--------+
: 2 KB :
:UNSHARED:-----RAM
:
+--------+

D
A
T
A

+--------+
RX50
DISK :------1
DRIVE I
IfF

+--------+

+-----.----+
+---------+
SHARED I------DMA--------I EXTENDED:
I ----- I 62 KB
:
+------+
: COMMS
:
RAM
: ---: OPTION :
:
I
+----------+
+---------+
I
2 KB
:
: UNSHARED 1---8
RAM
I
+---------+
I
I
B
+----------+
I
I

+------+

U
S

+----------+
24 KB
:---ROM
:

1
I

+------+

+---------+

+----------+
: OPTIONAL

'-----:KEYBOARD :
:

I/F

+---------+
+---------+
: ASYNC/
-----: BISYNC
: COMMS
I
I

+---------+
+---------+

: +------+
: I 4 KB :
I I SCREEN: ---: I RAM :
+---+------+
I 4 KB
:
:ATTRIBUTE 1---:
RAM
I
+----------+

-----1 PRINTER:

PORT

+---------+

+---------+
-----: COLOR :
: GRAPHICS:
I

+------+
Mother Board Block Diagram

Page 6

: VIDEO
: ---: CONTROLLER:
+----------+

Figure 1.

+----------+
: DC 11/12 :

D
A

B
U
S

:--+
I

+----------+

8088

:
RAM
:----:
: (64 KB OR I
: 192 KB)
:

I
I

-----1

I
T

+---------+

PC100 SYSTEM SPECIFICATION
3.1.2

8088 System

The 8088 microprocessor on the module controls nearly everything except the
floppy disk. The 8088 runs from a clock of !i.815 MHz and controls the
following:
o Video
o Keyboard
o Pr inter
o Communication line
o Optional graphics board
o Optional extended communications board
The 8088 also controls the Z80A's RESET line, as it can start/stop the Z80A
at will.
The cloc.k time on the 8088 is approximately 208 nanoseconds.
Contention from either the Z80A or refresh can cause wait states.

3.1.3 8088 Memory
The 8088 has several different types of memory available for its use:
a.
b.
c.
d.
e.
f.

64KB dynamic memory (62KB shared)
24KB ROM
4KB video screen memory (static)
4KB video attribute memory (static)
256X4 NVM with shadow RAM
64KB or 192KB optional un shared dynamic memory

3.1.3.1 Shared Memory - The standard 6!iKB bank of memory is shared Shared
Memory with the Z80A processor. However, the ZaOA is unable to address (and
therefore can't modify) the first 2KB portion of this bank. Therefore, the
8088 keeps its interrupt vectors and some other information safe from being
mole sted by a laOA a ppl ic at ion. No par i ty gener at ion/ detec t ion is
implemented with the 64KB shared RAM.
If there is no contention for the shared RAM at the time of an 8088 access,
no waji t states are required for the cycle. If the RAM is busy due to a
refr~sh cycle or a l80A memory cycle, which was initiated prior to the
8088 1 s request, wait states will occur until the request can be filled.
Refresh has the highest priority for memory cycles.
The 8088 has
approximately equal priority with the l80A.
Page 7

PC100 SYSTEM SPECIFICATION
3.1.3.2 ROM - There is 2~KB of ROM (three sockets) on the module which is
addressable by the 8088. The 24KB of ROM contains Z80A code and 8088 code
for diagnostics, bootstrap, and VT 102 emulation.
The code for the Z80A
must be moved into shared memory by the 8088 in order to be executed by the
Z80A.
No wait states are required when the 8088 accesses this memory;
however, because the circuitry assumes that all memory is dynamic RAM, wait
states will be excecuted whenever refresh cycles are in progress.
Supported ROMs are of the 2732/2764 pinout variety, with access times <=
~50 nsec.

3.1.3.3 4KS Screen Memory And !lKS Attribute Memory - There is screen and
attribute memory available to the 8088 which allows it to control what is
on the CRT display. This memory is available to the 8088 90 percent of the
time. In the remaining ten percent, the DCOll and DC012 have access to this
memor y and prohibit the 8088 from access.
Wait states to the 8088 occurs
during refresh cycles and while the DCOll and DC012 are using the memory.
The worst case time in which the 8088 can be held in a wait state due to
contention with the DCOll and DC012 is approximately 120 microseconds.

3.1.3.4 256 X 4 NVM With Shadow RAM - The PC100 mother board contains 1024
bits of non-volatile storage that is organized 256 x 4. The NVM, as it is
called, is located on the 8088 CPU bus at address OEDOOOH through OEDOFFH
and the data path to the device. is through data bits 0, 1, 2, and 3.
Phantom images of the NVM exist from address OED100H through OEDFFFH.
The device contains a 256 x 4 bit static RA~I that performs as any other
static memory.
The device also contains a 256 x 4 bit non-volatile memory
that is overlaid with the 256 x 4 bit static memory.
On initialization,
the 8088 does a RECALL of the NVM which places that data into the static
memory. At this time, any read or write to the memory occurs to the static
memory. The RECALL is done via a bit in the Diagnostic Write register. On
power-up, this bit is set to a 0, and must be set to a 1 by firmware before
data from the NVM RAM is available.
To perform a RECALL, the bit is set to a 0 and then set back to 1. The
minimum width for this pulse is 450 ns. The data is available immediately
after the RECALL bit is reset. The data that is in the static memory
portion can be stored in the NVM by the 8088 CPU via the PROGRAM NVM bit
also located in the Diagnostic Write register. This bit is also set to a 0
on power-up. To perform a PROGRAM NVM operation, the bit is set to a 1 and
then back to a O. This pul se has a minimum wid th of 100 ns. Once the
PROGRAM NVM bit has met the minimum pulse width it can be removed, however,
the device cannot be accessed by the CPU for 10 ms. At this time the device
is in the process of storing the data into the NVM. There is no indication
to the CPU that the device is done other than 10 ms has passed. If another
operation is done on the device during those 10 ms, it will be ignored.
Once the operation is started, it cannot be terminated unless the power is
turned off. In this case, data in the device is not valid.

Page 8

PC100 SYSTEM SPECIFICATION
3.1.3.5 Unshared Dynamic Memory (Optional) - The module can optionally be
expanded with 6LiKB or 192KB of memory for use by the 8088.
If installed,
this memory is always available and never requires wait states (except when
the memory cycle contends with a refresh cycle).

3.1.3.6 8088 1/0 Map - The 8088 I/O map follows:

PORT H
OOH
OOH
02H
02H
04H
06H

OAH
OAH
OCH
OEH
10H

11H
20H-2FH
LiOH
LilH
Li 2H
Li3H
50H-5FH
60H-6FH

FUNCTION
Interrupts Z80A Flop (write)
Clears 8088 Interrupt Flop (Read)
Communications and LED Register
General Communications Status
DCOll Write Register
Communications Bit Rate Register
Maintenance Port
Maintenance Port
DC012 Write Register
Printer Bit Rate Register
Keyboard Data Register(8251A)
Keyboard Control/Status Register(8251A)
Ext. Comm. Option/Option Select 1
Comm Data Reg. (7201)
Printer Data Reg. (7201)
Comm Control/Status Reg. (7201)
Printer Control/Status Reg. (7201)
Graphics Option Select
Ext. Comm. Option/Option Select 2

\\0

RO
WO
WO
WO
HO
WO
wO
HO/WO
HO/WO
RO/WO
HO/WO
RO/WO
HO/WO
H/W

3.1.3.7 8088 Memory Map - The 8088 memory map is shown in Figure 2.

Page 9

PC100 SYSTEM SPECIFICATION

FFFFF
ROM 2 (BOOT)
FEOOO
ROM 1
FCOOO
ROM 0
FAOOO

FOOOO
ATTRIBUTE RAN
EFOOO

(

SCREEN RAM

EEOOO
NVM SHADOW
ED.OllO

NVM

EDOOO
NVM SHADOW
ECOOO
110000

OPTION RAM
10000

SHARED RAM
0

Figure 2. 8088 Memory Map

(

\
Page 10

PC100 SYSTEM SPECIFICATION
3.1.3.8 8088 Interrupts - The following table lists the 80S8 interrupts.
Priority

Interrupt Source

Highest

Vertical Frequency Interrupt
Graphics
DMA Controller Interrupt
(from Optional Extended
Comm. Board)
Comm. / Pr inter ( 7201) Interrupt
Extended Comms Interrupt
(optional)
Keyboard (8251A) Interrupt
Interrupt from ZSOA

Lowest

Interrupt
Type (Hex)

Vector
Address ( Hex)

20
22
23

80
88
SC

25
26
27

94
9S
9C

3.1.3.9 Video Subsystem: 8088 - The video subsystem resides on the mother
board and is controlled by the S08S.
The subsystem provides fully
VT100-compatible video features.

3.1.3.9.1 General Video
following features:
a.
b.
c.
d.
e.
f
g.

h.
i.
j.

Features

The

video

subsystem

supports

the

24 line x 83 column display
24 line x 137 column display
Smooth scrolling (full screen and split screen)
Double height lines
Double wid th lines
Reverse video
Bold
Bl inking
Under 1 ine
RS170 "like" composite video output
256-character set

The software on the 8088 is able to vary the speed of the smooth scrolling,
(e.g., 3, 6, 12, or 18 lines/sec). The double height and double width
attributes may be selected on a line by line basis. The other attributes
(reverse, bold, blink, and underline) may be selected on a character by
character basis.
3.1.3.9.2 Video Memory - The video subsystem has 4KB of screen RAM and 4KB
of attribute RAM. Only the four LSBs of the attribute RAt-: are actually
looked at by the video subsystem.

3.1.3.9.3 Video Processor (DCOll And DC012) - when accessing the screen
RAM, the video processor generates the 12-bit address for a particular byte
in the lower 4KB bank (character RAM). The corresponding byte in the upper
Page 11

PC100 SYSTEM SPECIFICATION
4KB bank (attribute RAM) is selected also. The two bytes are passed to the
video processor in parallel.
The v ideo processor uses the character code to index into a charac.ter
generator and uses the attribute information to modify the video data.
The contents of the screen RAM directly control the display of the lines
and characters. This region of memory contains the displayable characters,
their attributes the line attributes, and the addresses that link one line
to the next. The microprocessor modifies and updates this information in
the intervals between the video processor's DMAs.
The video processor begins reading the screen RAM at the start of RAM
(location OEEOOOH) following each vertical reset. Three bytes of control
data are located at the end of each line of characters. The first byte,
called the terminator I is FF hex and is a unique character that the video
processor recognizes as the end of the line. The next two bytes form an
address (low byte followed by high byte) which points to the first
character of the next line to be displayed. The byte of attributes that
correspond s to the low byte of the address contains three bits of line
attrib~tes which are applied to the line being pointed to.

,--------------------,---------------,-------------------------------,

Attribute:
At tr ibute Data
RAM
:

No Attrib.

Character:
Character Data
RA"I
:

Terminator

Line Attribute No Attrib.

:-------------------- --------------Address of Next Line

,-------------------- --------------- -------------------------------

The bits are assigned in the following manner:

Char.
Attrib.
Char.
Data

,
I

D4
Unused : Unused : Unused

D7
Unused

Alt.
Char

D2
Not
Blink

D3
Not
Under
Line

D1
Not
Bold

DO
Rev.
Video

Code for Character

Set
i
I

Line
Attrib.

Unused :Unused

i
I

1
I

Unused: Unused: Unused: Double: Double: Scroll
Width
Height: Region

Page 12

PC100 SYSTEM SPECIFICATION
(Smooth) scroll region - if set, this line scrolls: if not set, it
doesn't
Double
Height

Double
Width

o
o

o
1
o

1
1

Result
bottom half double height
top half double height
double width
normal height, normal width

3.1.3.9.4 DCOll Programming Information - The DC011 video-timing chip can
be accessed by the 8088 (WRITE-ONLY) at I/O address 4. The DCOll must be
programmed with the desired refresh rate and column mode on power-up and
after any mode changes. To program the DCCll, write two of the following
four codes:
Code

Configuration

80 column mode sets

132 column mode interlaced mode
60 Hz mode resets
50 Hz mode interlaced mode

Interlaced/non-interlaced mode is determined by the order in which BO/132
column and 50/60 Hz are set.
Every time the DCOll is programmed, its
internal timing chain is reset. Since this causes the screen to jump, the
DCOll should be programmed only if absolutely necessary.
For example I the
following two instructions set the DCOll to BO-column, 60 Hz, no interlace:
MOV AX,2000H

OUT

DCOll,AX
Note
When 80 column mode is selected, the video
processor is actually capable of displaying B3
columns in single width mode or 41 columns in
double width/height mode. When 132-column mode
is selected, 137 columns can be displayed in single
width mode or 68 columns in double width/height
mode.

Page 13

PC100 SYSTEM SPECIFICATION
3.1.3.9.5 DC012 Programming Information - The DC012 video control chip can
be accessed by the 8088 (WRITE-ONLY) at I/O address OCH.
The following
codes are defined for the DC012:
Code

Result

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
CD

Set scroll latch LSB's to 00
Set scroll latch LSB's to 01
Set scroll latch LSB's to 10
Set scroll latch LSB's to 1 1
Set scroll latch MSB's to 00
Set scroll latch MSB's to 01
Set scroll latch MSB's to 10
Set scroll latch MSB's to 11
Toggle blink flip flop
Clear vertical frequency interrupt
Set reverse field on
Set reverse field off
Not supported
Set basic attribute to reverse video with 24 lines and set
blink flip flop off
Not supported
Set basic attribute to reverse video w/48 lines and set blink
fl ip flop off

OE
OF

On power-up, the DC012 can be programmed to bring it to a known state.
Typically, codes 00, 04, 09. OB, and OD will be programmed at power-up
time.
The value to which the scroll latch is set determines which scan row the
first line of a scrolling region starts on.
Likewise, it determines the
last scan row displayed for the last line in a scrolling region.
For example, when the latch is set to zero (the degenerate case), the first
line of the scroll region starts at scan row zero (so the line is
completely visible).
The last line of the scrolling region terminates at
scan row 9 (so this line is also completely visible).
When the scroll latch is non-zero, for example 5, the first line of the
scrolling region starts with scan row 5 (so only the bottom half of the
line is visible). The last line of the scrolling region terminates at scan
row 4 (so only the top half of the line is visible).
If the scroll latch is incremented from a through 9 and back to a again
once each frame. the screen appears to smooth scroll from bottom to top
(assuming that line linkages and line attributes are properly handled). On
the other hand, if the scroll latch is decremented from 0 to 9 then down
through 0, the screen appears to smooth scroll from top to bottom (again
assuming that all line linkages and line attributes are properly handled).

Page 14

PC100 SYSTEM SPECIFICATION
A scrolling region is defined as a group of lines with their scrolling
attributes set, surrounded by lines whose scrolling attribute is not set.
Note that the scrolling attribute for a line resides in the line pointer
information at the end of the previous line. Also, the first line on the
screen (the one at "RAM location 0). has its scrolling attribute reset by
definition. Also note that the definition of a scrolling region does not
preclude the definition of more than one scrolling region per screen,
although that is of dubious value.
Whenever the scroll latch is non-zero, each scrolling region on the screen
requires an extra (scrolling) line to be linked in.
For example. if the
scrolling region is 10 lines long, when the scroll latch is set non-zero
there will have to be an eleventh line linked in. If scrolling up
(incrementing the scroll latch). the line must be linked in at the bottom.
When the scroll latch is incremented back to a again, the top line of the
scrolling region must be unlinked. When scrolling down (decrementing the
scroll latch), new lines must be linked in at the top of the scroll region
and unlinked down at the bottom. All line linking/unlinking should be done
during the vertical blanking interval (after the vertical frequency
interrupt is rung). In 60-Hz mode, there are two blanked lines at the
beginning of the screen (the line at RAM location 0, and the line that it
points to).
The first line (at location 0) is guaranteed to have been read by the time
that the interrupt service routine is entered; any changes to this line
will not affect the screen until the next frame time.
However, the second line
asserting the interrupt.

will

not

read

for

over

500

usec.

after

If it is to be changed, it must be changed very soon after entering the
interrupt service routine in order to guarantee that the change will be
visible in the current frame.
Therefore, if the first v isible line on the screen is involved in the
scroll region and is being either linked in or unlinked, then the vertical
interrupt routine must guarantee that its pointer (which resides in the
second invisible line) is changed within approximately 500 usec after the
ringing of the interrupt.
The modification of the scroll latch is much less time critical than this.
Because the scroll latch is loaded by the DC012 by the vertical reset at
the begirining of each frame, the only requirement is that the scroll latch
be modified before the next frame begins. Note that the scroll latch value
is the value that will be used dur ing the l')ext frame rather than the
current frame.

3.1.3.10 Keyboard Interface - The interface to the keyboard is a RS423
full-duplex connection. The interface runs at 4800 bits per second
asynChronous, with an 8-bit no parity character format. The UART used on
the mother board is an 8251A. It must be set up in asynchronous mode with a
16 times clock and 8-bits no parity. The recommended setup procedure is to
Page 15

PC100 SYSTEM SPECIFICATION
output the following sequence to port 11 (hex):
(all values in hex)
0,0,0,40,4E,15
DURING THE INITIALIZATION, CONSECUTIVE WRITES MUST NOT BE SPACED
ANY CLOSER THAN 3 MICROSECONDS.
The Status Read Format of the 8251A (input from Port 11 Hex) follows:

D6
I
I

DSR

l SYNDETI l
lBRKDET

,
,
,
i

lTxEMPTYl RxRDY

TxRDY

Note 1
SAME DEFINITIONS AS 1/0 PINS
PARITY ERROR - The PE flag is set when a par i ty error is detected. It is
reset by the ER bi t of the Command Instruction. PE does not inhibi t
operation of the 8251A.
OVERRUN ERROR - The OE flag is set when the CPU does not read a character
before the next one becomes available. It is reset by the ER bit of the
Command Instruction. OE does not inhibit operation of the 8251A, however,
the previously overrun character is lost.
FRAMING ERROR (Async only) - The FE flag is set when a valid Stop bit is
not detected at the end of every character. It is reset by the ER bi t of
the Command Instruction. FE does not inhibit the operation of the 8251A.
DATA SET READY - Indicates that the DSR is at a zero level.
Used to read a
manufactur ing jumper.
Tx RDY status bit has different meanings from the
TxRDY output pin. The former is not conditioned by -CTS and TxEN; the
latter is conditioned by both -CTS and TxEN. i.e., TxRDY status b i t : DB
Buffer Empty TxRDY pin out: DB Buffer Empty (-CTS:O) (TxEN:1)
Note 2
TxE (Transmitter Empty) - When the 8251A has no characters to send, the
TxEMPTY output will go "high".
It resets upon recelvlng a character from
the CPU if the transmitter is enabled. TxEMPTY remains low when the
transmitter is disabled if it is actually empty.
RxRDY (Receiver Ready) - This output indicates that the 8251A contains a
character that is read y to be input to the CPU. Rx RDY is connected to the
interrupt structure of the CPU. For polled operation, the CPU can check the
condition of RxRDY using a Status Read operation.
Page 16

PC100 SYSTEM SPECIFICATION
RxEnable, when off, holds RxRDY in the Reset Condition.
For Asynchronous
mode, to set RxRDY, the Receiver must be enabled to sense a Start Bit and a
complete character must be assembled and transferred to the Data Output
Register.
Failure to read the received character from the Rx Data Output Register
prior to the assembly of the next Rx Data character will set overrun
condition error and the previous character will be written over and lost.
If the Rx Data is being read by the CPU when the internal transfer is
occurring, overrun error will be set and the old character will be lost.
TxRDY (Transmitter Ready)
This output signals the CPU that the
transmitter is ready to accept a data character.
The TxRDY output pin is
used as an interrupt to the system, since it is masked by Tx Enable. For
Polled operation, the CPU can check Tx ROY using a Status Read operation.
TxRDY is automatically reset by the leading edge of -WR when a data
character is loaded from the CPU.
Note that when using the Polled operation, the TxRDY status bit is not
masked by TxEnable, but will only indicate the Bnpty/Full Status of
the Tx Data Input Register.
Parity errors should not occur. A hardware or software problem exists
if parity errors do occur. The keyboard generates an interrupt to the 8088
when either the TxRDY pin or the RxRDY pin is asserted. The interrupt is a
type 26 Hex.
3.1.3.11 Printer Port Interface - This is a general purpose printer
which provides an RS423 interface compatible with DEC printers.
signals supported are:
o Tr an sm i t

Da t a
o Receive Data
o Data Terminal Ready
o Data Set Read y asserted
Software programmable bit rates supported are:
o 15
o 150
o 300
o 600

o
o
o
o

1200
2400
4800
9600

Page 17

port
EIA

PC100 SYSTEM SPECIFICATION
Printer bit rates are selected by writing the following to 8088 port OEH:
Data Bit 0-2

Bit Rate

°21

150

75
300
600
1200

3
4
5

2"00

"800

9600

Note
Bit 3 controls the communications port clock.
Software-programmable character formats supported are 5-8 bits/character
with 1, 1-1/2, or 2 stop bits/character. Parity may be selected as odd,
even or none. Software should support XON/XOFF restraint protocol for this
port. The O-type 25-pin female EIA printer connector physically resides on
the mother board in the normal printer port location and attaches directly
to a printer. OSR and CTS are always asserted.

3.1.4 MPSC Overview
The 7201 Multi-Protocol Serial Controller is a microcomputer peripheral
device that supports Asynchronous (Start/Stop), Byte Synchronous (Monosync,
IBt-'i Bisync), and Bit Synchronous (ISO's HDLC, IBM's SDLC) protocols. This
controller's flexible architecture allows implementation of many variations
of these three protocols with low software and hardware overhead.
The Multi-Protocol Serial Controller (MPSC) implements two independent
serial receiver/transmitter channels.
The printer port uses one channel
and the communications port uses the other channel.
As implemented on the mother board, the MPSC supports two microprocessor
interface options: Polled and Interrupt.

3.1.4.1 Asynchronous Operations
General
For operation in the
asynchronous mode, the MPSC must be initialized with the following
information:
o character length (WR3; 07, D6 and WR5; D6, D5)
o clock rate (WR4; D1, 06)
o number of stop bits (WR4; D3, D2)
o odd, even or no parity (WR4; D1, DO)
o interrupt mode (WR1, WR2)
o receiver (WR3; DO) or transmitter (WR5; 03) enable
Page 18

PC100 SYSTEM SPECIFICATION
When loading these parameters into the MPSC, WR4 information must be
written before the WR1, WR3, WR5 parameters/commands.
For transmission via a modem or RS423 interface, the Request To Send (RTS)
(WR5; D1) and Data Terminal Ready (DTR) (WR5; D7) bits must be set along
with the Transmit Enable bit (WR5; D3). Setting the Auto Enables (WR3; D5)
bi t allows the programmer to send the first character of the message
without waiting for a clear to send (CTS).
Both the Framing Error and Receive Overrun Error flags are latched and
cause an interrupt.
If the

External/Status Interrupt bit (\-oRl;
DO) is enabled, Break Detect
D3) will cause an interrupt.
Reset
(RRO;
D7) and Carrier Detect (RRO;
External/ Status Interrupts (WRO; D5, D4, D3) will clear Break Detect and
Carrier Detect bits if they are set.
A status read after a data read will include error status for the next word
in the buffer. If the Interrupt on First Character (WR1; D4, D3) is
selected, then data and error status are held until an Error Reset command
(WRO; D5, D4, D3) is given.
If the Interrupt on Every Character Mode bit (WR 1;
D4, D3) is selected,
the interrupt vector is different if there is an error status in RR1. When
the character is read, the error status bit is set and the Special Receive
Condition vector is returned if Status Affects vector (WR1B; D2) is
selected.
In a polled environment, the Receive Character Available bit (RRO; DO) must
be monitored so that the CPU can determine when data is available. The bit
is reset automatically when the data is read.
If the Xl clock mode is
selected, the bit synchronization must be accomplished externally.
Refer to Figure 3.

Page 19

PC100 SYSTEM SPECIFICATION

+-------+-------+-------+-------+-------+-------+-------+-------+
I D7
I D6
I D5
I D4
I D3
I D2
I D1
DO
I
--------+-------+-------+-------+-------+-------+------+-------+-------w
10C RX 5 B/CHAR I
101 RX 7 B/CHAR I AUTO
I
0
:
110 RX 6 bl CHAR I ENABLESI :

\oJR3

:11 RX 8 b/CHAR :

;

0
I

0:
RX
:
I ENABLE I
•

;

--------+---------------+-------+-------+-------+-------+-------+-------+
100 Xl CLOCK
100 ENABLE SYNC I
:
I
WR4

101 X16 CLOCK
110 X32 CLOCK
III X64 CLOCK

0
I

MODES
EVENI I
:
101 1 STOP BIT
I
ODD
I PARITY I
: 10 1.5 STOP BIT: PARITY: ENABLE:
: 11 2 SlOP BITS :
:
:

0
:
I

--------+-------+-------+-------+-------+-------+-------+-------+-------+
100 TX 5 bl CHAR I
I
WR5

DTR
;

101 TX 7 b/CHAR I SEND I
TX
I
110 TX 6 b/CHAR I BREAK I ENABLEI
;
:
: 11 TX 8 bl CHAR :

I
I
:

RTS

0
•

--------+-------+---------------+-------+-------+-------+-------+-------+
Figure 3.

Asynchronous Mode Register Setup

3.1.4.2 Communications Port - This port is used to communicate to another
computer.
It has full modem support and supports the same Signals as the
VT102. U.S. and European full- and half-duplex modems can be supported by
this port. The port has ASYNC as well as BISYNC modes with a RS423
(V.24/V.28) physical interface conforming to CCITT V.21, V.22 and V.23.
Break detection by this port is supported. Bit rates supported are:
0

1200

1800

110

2000

134.5

2400

150

3600

200

4800

300

9600

600

o 19200

Page 20

PC100 SYSTEM SPECIFICATION
Communications bit rates are selected by writing the following to 8088 port
06H:
Nibble Data
0 H
1 H
2 H
3 .H
4 H
5 H
6 H
7 H
eH
9 H
A H

B H
C H
D H
E H
F H

Bit Rate
50
75
110
134.5
150
200
300
600
1200
1800
2000
2400
3600
4800
9600
19200

Percent Error

o
o
o
o
o
o
o
o
+. 14
o
o

-. 17
+.46
+.46
+.46
-2.04

The low nibble of the data written to port 06H sets the transmit clock
while the high nibble sets the receive clock.
For example: Data OAH written to 8088 port 06H would set the receive bit
rate to 50 and the transmit bit rate to 2000.
Bit 3 on port OEH selects the comm port clocks (RxC, TxC).
set; internal when reset.

External when

Note
Bi t 0-2 on port OEH controls the printer port bi t
rates.
All bit rates are software selectable. Transmit and receive bit rates may
be selected independently from the available bit rates.
The ROM code
supports VT102 emulation on this port.

Page 21

PC100 SYSTEM SPECIFICATION
Signals supported are:
1. Receive Data
2. Transmit Data
3. Secondary Transmit Data
~. Request to Send
5. Secondary Request to Send
6. Clear to Send
7. Secondary Clear to Send
8. Receive Line Signal Detect
9. Secondary Receive Line Signal Oetect/ Speed Indicator (Bell 212A)
10. Ring Indicator
11. Data Set Ready
12. Speed Select
3. 1. ~. 3 Synchronous Operation -- Mono Sync, B1 Sync -- General - The MPSC
must be initialized with the following parameters:
o odd or even parity (WR~; 01, DO)
o X1 clock mode (WR4; D7, 06)
o 8- or 16-bit sync character (WR4; 05, O~)
o CRC polynomial (WR5~ D2)
o Transmitter Enable (WR5; D3)
o Interrupt modes (WR1, WR2)
o Transmit character length (WR5; 06, D5)
o Receive character length (WR3; D7, D6
WR4 parameters must be written before WR1,WR3, WR5, WR6and WR7. The data
is transmitted on the falling edge of the Transmit Clock (TxC) and is
received on the rising edge of Receive Clock (RxC). The X1 clock is used
for both transmit and receive operations· for all three sync modes: Mono, Bi
and External.

Page 22

PC100 SYSTEM SPECIFICATION

+-------+-------+-------+-------+-------+-------+-------+-------+
D7
D6: D5
D4
D3
D2
D1
DO
--------+-------+-------+-------+-------+-------+-------+-------+-------~

WR3

:00 RX 5 B/CHAR
:01 RX 7 B/CHAR
:10 RX 6 b/CHAR
: 11 RX 8 b/CHAR

:
ENTER
: AUTO I HUNT: RX CRC:
:ENABLES: MODE: ENABLE:
:
:
:
:

: SYNC
: CHAR
RX
: LOAD : ENABLE:
: INHIBIT:

--------+-------+-------+-------+-------+-------+-------+-------+-------+
: 00 8 BIT SYNC :
: EVEN/ :
:
WR4

0 : 01 16 BIT SYNC:
:
11 EXT SYNC:

:
:

: ODD : PARITY:
: PARITY: ENABLE:

--------+-------+-------+-------+-------+-------+-------+-------+-------+
: 00 TX 5 b/CHAR
:
1
:
:
WR5

DTR

:01 TX 7 b/CHAR I SEND I
TX : (SELECT: RTS I TX CRG:
:10 TX 6 b/CHAR : BREAK: ENABLE:CRC-16):
: ENABLE:
: 11 TX 8 b/ CHAR :
: : : :

--------+-------+---------------+-------+-------+-------+-------+-------+
Figure 4.

Synchronous Mode Register Setup -- Monosync, Bisync

3.1.4.4 Synchronous Operation -- SDLC -- General - Like the other
synchronous operations the SOLC mode must be initialized with the following
parameters:
o SOLC mode (WR4; 05, D4)
o SOLC polynomial (WR5; D2)
o Request to Send, Oata Terminal Ready, transmit character length
( WR5; 06, 05 )
o Interrupt modes (WR1; WR2)
o Transmit enable (WR5; D3)
o Receive enable (WR3; DO)
o Auto enable (WR3; D5)
o External/status interrupt (WR1; DO)
WR4 parameters must be written before WR1, WR3, WR5, WR6 and WR7.

Page 23

PC100 SYSTEM SPECIFICATION

+-------+-------+-------+-------+-------+-------+-------+-------+
I 01
: 06
: 05
I 04
I 03
: 02
: 01
: DO
:
--------+-------+-------~-------+-------+-------+-------+-------+-------*

WR3

100 RX 5 B/CHAR
101 RX 1 BICHAR
:10 RX 6 b/CHAR
:11 RX a b/CHAR

I
ENTER I
IADDRESSI
I AUTO : HUNT I RX CRCI SEARCH:
:ENABLES: MODE: ENABLE: MODE
:
I
I
I
:

I RX
I
I ENABLE:
:
:

--------+-------+-------+-------+-------+-------+-------+-------+-------+
:
0
1:
:
WRlI

0 : (SELECTS SDLC/:
I
HDLe MODE):

:
I

;

--------+-------+-------+-------+-------+-------+-------+-------+-------+
: 00 TX< 6b/ CHAR
:
a
:
WR5

OTR

:01 TX 1 b/CHAR I
:10 TX 6 b/CHAR I
:11 TX a b/CHAR :

:
TX : (SELECT:
: ENABLE: SOLC:
CRC) I

RTS

I
TX CRC:
: ENABLE:

-----.--+-------+---------------+-------+-------+-------+-------+-------+
F1,ure 5.

3.1.5

Synchronous Mode Register Setup -- SOLC/HOLC

ZaOA System

The following describes the section of the system controlled directly by
the Z80A
3.1.5.1 ZSOA CPU - The module includes one ZeOA microprocessor, which runs
from a clock of 1I.012 MHz. The Z80A alone has access to the floppy disk
inter face and thus is responsible for controlling the floppy (v ia
programmed 110) for all applicat.ions.

3.1.5.2 ZBOA Shared Memory - The ZSOA has available to it 64KB RAM, which
is divided into 62KB shared and 2KB unshared memory. Accesses to the shared
portion of memory select the corresponding address in the standard bank of
64KB RAMS. Accesses to the un shared memory select a private 2Kx8 byte-wide
static RAM.

3.1.5.3 ZSOA Private RAM - The un shared RAM may be accessed by the ZSOA at
any time without any wait states. If the shared RAM is "busy" at the time
of a Z80A access, the ZBOA will execute wait states until the RAM is free.
The RAM is considered "busy" when an 8088 cycle or a refresh cycle is in
progress or is pending. In addition to wait cycles due to contention, all
M1 cycles from the shared RAM have one extra wait cycle due to the timing
for this sort of machine cycle. In any case, the Z80A is held in a wait
state for no longer than approximately two microseconds.
If both
Page 24

PC100 SYSTEM SPECIFICATION
processors are executing out of the shared memory, the Z80A cannot reliably
access the floppy disk (i.e., lost data errors will often result).
3.1.5.4 Z80A 1/0 Map - The following is the ZBOA I/O map.
PORT

FUNCTION

OOH
OOH
21H
21H
40H
40H
60H
60H
61H
62H
63H

Clear Interrupt to Z80A (Read)
Interrupts 8088 (Write)
Disk Diagnostic Read Register
Disk Diagnostic Write Register
Disk Control Read Register
Disk Control Write Register
FDC Status Register
FOC Control Register
FOC Track Register
FOC Sector Register
FOC Data Register

RO
WO
RO
WO
RO
WO
R/W
R/W
R/W

Note
The above ZBOA I/O port~ are remapped within their
own pages and are also remapped starting at BOH.
Writing Diagnostic Write Register at address 21H
will reset ZFLIP. Writing the Diagnostic Write
Register at address 20H will set ZFLIP.
3.1.5.5 Z80A Memory Map - The ZBOA memory map follows:
Z FLIPPED

Z NOT FLIPPED

FFFFI

FFFF

1FFF FFFF

SHARED RAM

8000

800

8800

800

8000

FFFF

PRIVATE

0
8088

Z80

800
PRIVATE

PRIVATE

8088

ZSO

Figure 6. Z80A Memory Map
Page 25

PC100 SYSTEM SPECIFICATION
3.1.5.6 Z80A Cycle Time - The clock time on the Z80A is approximately 250
ns. Unshared memory accesses have no wait states. Shared memory accesses
have wait states on Ml cycles and for cycles in which there is contention
between devices accessing the shared RAM. Contention exists because of
refresh cycles and 8088 cycles.

3.1.5.7 Z80A Interrupts - The only interrupts are interprocessor interrupts
from the 8088 cpu. The vector placed on the bus is F7 (hex) which causes a
RST 30 instruction to be executed in interrupt mode O.

3.1.5.8 Floppy Controller Module - The floppy controller module is not
optional. It is a separate module that connects to the mother board via
J7. The interface is designed to control up to four 5-1/~ inch platters
with one or two surfaces.
The controller supports soft-sectored double-density diskettes using a PLL
circuit. Single- or double-sided drives are supported. The interface
adheres to drive capability and signal definition of the ANSI standard
interface for mini-floppy drives.
The floppy controller block diagram is shown in Figure 7.

Page 26

PC100 SYSTEM SPECIFICATION

+-----+,

,
STATUS
o ,,:-------<-------------------P
+---+
+---------+
I

F
L

CPU CONTROL-------------------------->

+-----------+
FLOPPY ------------>:
DATA
:---->
DATA
: SEPARATOR:
+-----------+
+--------+ A
DIAGNOSTIC -->: PULSE : :
LOOPBACK
: SHAPER : --+
DATA
+--------+

P
Y
C
T
R
L

'-->: WRITE :---->:
F
: PRECOMP :
: L
+---------+
CONTROL SIGNALS
: 0
-------->-+------->: P

P
Y

Z80 DATA BUS

----<------>---+-------

+-----+

,
,,
I

o
R
I
V
E

R
X

D
I
S
K
D

R
+-------------+
:
I
+-<--: DIAGNOSTICS :<----+
BUFFER
R
V
,
E
S
I
+-------------+
:
+-------------+
:
+->--:
CONTROL
:
:
:
:
LATCH
:------------->:
AND DRIVE
:
:
:
SELECT
:
+---+
,
I
+-------------+
:
+-------------+
:
+-<--:
STATUS
:<----------------------:
:
BUFFER
+--+-------------+
I

Figure 7.

Floppy Controller Block Diagram

Page 27

PC100 SYSTEM SPECIFICATION
3.1.5.8.1 Floppy Disk Controller Registers: Z80A 1.

Command Register (Write Only) (Port Address 60 Hex)
This 8-bit write-only r.egister is loaded by the program with the
command that is to be execut.ed by the drive. A command summary
follows.
Table 1. Command Summary
Bits
Type Command

0
0

0
0
0

0
0
1
0
1
0
1
0
0

0
1

h
h
h
h
h

v
v

Restore
Seek
Step
Step In
Step Out
Read Sector
Write Sector
Read Address
Force
Interrupt

I
I

I
I
II
II

III

0
0
0
1
1
1

0
0
1

1
1

u
u
u
m 0
m 0

v
v
e
e
e

1(3)

1(2)

d1) do)

r (1)
r( 1)
r (1)
r( 1)
0
0
0

reO)
reO)
reO)
reO)
0
a(O)
0

1(0 1(0)

Note
Read Track and Write Track are not supported.
Flag Summary
Type I Commands
h = Head Load Flag (Bit 3)
v = Verify Flag (Bit 2)
r1,rO = Stepping Motor Rate ( Bits 1-0)
u = Update Flag (Bit 4)
Type II and III Commands
m = Multiple Record Flag (Bit 4)
aO = Data Address Mark (Bit 0)
e = 30 msec delay
Type IV Commands
Ii = Interrupt Condition Flags
For more detailed information on the meaning and purpose of these bits,
refer to the System Module Functional Specification.

Page 28

PC100 SYSTEM SPECIFICATION
Floppy Command Summary
This module accepts 9 commands for floppy disk control. (See Table 1
for a command summary.) Commands should only be loaded into the commpnd
register when the Busy status bit is off.
The one exception is the
Force Interrupt command. The Busy status bi t i s set when a command is
executed.
Type I Commands
Type I commands are for head positioning. The stepping rate of these
commands are dictated by the drive. R1 = 0 and RO = 0 (6 ms) is the
recommended stepping rate for the RX50 drive.
The head load flag determines if the head is loaded at the beginning of the
command. Otherwise, the head is loaded at the end of a command.
The verification flag allows a verification operation to take place on the
de st ina t ion trac k. The ver i fic a t ion cons i sts 0 f read ing the fir s t
encountered ID field off of the disk.
The track address of the ID field is compared to the Track Register.
If
there is a match and a valid ID CRC, the verification is complete. If not
valid, the Seek error status bit in the FDC is set.
The Step, Stepin, and Stepout commands contain ari update flag for updating
the track register when this bit is set after the step has been completed.
Type II Commands
The Type II commands are to read and write sectors to the disk.
Prior to
loading the Type II command into the Command register, the Sector register
must be loaded with the desired sector number.
Upon receipt of the command, the Busy status bit is set. If the e flag is
set (normal case), the head is loaded and the HLT signal is sampled after
30 ms; otherwise, no delay is incurred after a command.
The HLT does not become active until 500 ms after the head is loaded to
allow the spindle motor to have time to accelerate. The FDC then attempts
to find the ID field with the specified track and sector.
If the desired field is not found within five revolutions of the disk, the
Record Not Found status bit is set. Otherwise, the command is executed by
the FDC generating Data Requests (DRQS) for servicing the data register.
Each of the Type II commands contain an m flag which determines if multiple
sectors are to be read or written, depending on the command. When set,
mul tiple sectors are read or written with the sector register internally
updated for address verification on the next track.
The FDC continues to do the transfers until the sector register exceeds the
number of sectors on the track or until a force interrupt command is loaded
into the command register.
Page 29

PC100 SYSTEM SPECIFICATION
Note
If the command is not terminated by software, the
1793 continues looking for five index pulses after
the last sector on the disk has been read or
wr i tten •
If the Sector register exceeds the number of sectors on the track, the
Record Not Found Status bit is set. When the head is loaded, the Busy
status bit is set, and when an ID field is encountered that has the correct
track, sector, side numbers and correct CRC, the data field is presented to
the computer (read) or presented by the computer (write).
At the end of the Read operation, the type of Data Address Mark encountered
is recorded in the Status register (Bit 5).
On a Write operation, the aO
flag (Bit 0) determines the type of Data Address Mark to be written onto
the disk. If set, a deleted data tnark is written else a data mark is
written.
Type III Commands
The Read Address command is to read in the six bytes of the ID field (track
number, side number, sector address, sector length, and two bytes of CRC).
Type IV Command
This command is to terminate an operation upon the specified condition in
Bits 3-0. See Table 1, Command Summary, for descriptions of the termination
conditions.
Type I Command Bit Description
1.

Bit 0,1 - Stepping Rate Bits - These bits control the rate at which
the stepping pulses are sent to the drive. Check the specifications
for the drive in use to determine the drive's proper step rate. See
the table above for stepping rate breakdown.

Bit 2 - Track Verify Bit - This bit determines if there is a
verification operation to take place on the destination track.
During verification, the head is loaded and after a 30-ms delay,
the HLT input is sampled. After a 500-ms motor start up time, the
HLT input becomes active. When HLT is true, the first ID field is
read off the disk. The track address of the ID field is compared to
the track register. If there is a match and a valid ID CRC, the
verification is complete and an interrupt is generated.
If not
valid, the seek error status is set.

Bit 3 - Head Load Flag - This bit determines i f the head is to be
loaded at the beg inning of a command.
If the head is loaded then
the head remains loaded until either the FDC receives a command
that specifically disengages the head or 15 revolutions of the disk
have passed with the busy bit = O.
Page 30

PC100 SYSTEM SPECIFICATION
4.

Bit 4 - Update Bit (Step Commands) - When set, the track register
is updated by one for each step, otherwise the track register is
not affected.

Bits 5-7 - Determine the command to be executed.

Type II Commands Bit Description
1.

Bit 0 - Data Address Mark Bit - When set upon a wr ite sector
command, this bit defines a Data Mark (OFBH) to be written on the
disk. If the bit is not set then a Deleted Data ~jark (OF8H) is
written onto the disk.
When writing valid data on the disk this
bit should be set.

Bit 1 - Always

Bit 2 - 30 Millisecond Delay Bit - When set during a command, there
is a 30-ms delay before reading begins.
For maximum controller
through-put, this bit should be o.
It should be set if the last
command was a seek or new drive select.

Bit 3 - Always

Bit 4 - Multiple Sector Bit - When set, this bit allows mul tiple
sectors to be transferred.

Bits 5-1 - Determine the command to be executed.

Type III Command Bit Description
1.

Bits 0,1 - Always set to O.

Bit 2 - Same as Bit 2 for Type II commands.

3. Bits 3-7 - Determine the command to be executed.
Type IV Command Bit Description
This command can be loaded into the register at any time.
If there is a
current command under execution, the command is terminated. See Table 1 for
a description of conditions upon which the command is terminated.
2.

Status Register (Read Only) (Port Address 60 Hex)

This read only register also resides at the same address as the command
register.
It contains the 8-bit status resulting from the completion of a
command. A description of the status bits follows.

Page 31

PC100 SYSTEM SPECIFICATION
Type I Status Bit Description
7

Busy
Index
Track 0
10 Field eRG Error
Seek Error
Head Loaded
Write Protect
Not Ready
Bit 0 - Busy Bit - When this bit is true (1), the FOe is currently
executing a command. Only a Type IV command can be issued when this
condition exists.

Bit 1 - Index Bit - When this bit is true (1), the index pulse is
currently occurring.

Bit 2 - Track 0 Bit - When this bit is true (1), the read/write
head is currently positioned at track O.

Bit 3 - 10 Field CRC Error Bit - When true, this means that there
was a eRe error of the 10 field.

Bit 4 - Seek Error Bit - When true, a seek error was encountered
meaning that the destination track address was not found.

Bit 5 - Head Loaded Bit - This bit reflects the current status of
the head. When set, the head is loaded and the HLT input is
asserted.

Bit 6 - Write Protect Bit - When set, the bit means that the
current disk is write protected. An attemp'C to write a sector
generates an interrupt if the device interrupt enable bit is set.

Bit 7 - Not Ready Bit - When set, the bit indicates that the drive
is not ready. This could mean that the drive is not up to speed,
the disk is in upside down, or the door is open. This bit must be
clear before any commands are issued to the FOe.

Page 32

PC100 SYSTEM SPECIFICATION
Type II Read Sector Status Bit Description
7

o
Busy
Data Request
Lost Data
ID/Data Field CRC Error
Record Not Found Error
Record Type

Not Ready

Bit 0 - Busy Bit - Same as Type I status.

Bit 1 - Data Request Bit - This bit means that the data register is
full and it is waiting for the CPU to read the register.

Bit 2 - Lost Data Bit - When set, it means that the data register
had not been serviced within 27.0 microseconds and the data in the
data register is not valid.

Bit 3 - ID/Data Field eRC Error Bit - When set, an error is found
in one or more ID fields or the data field. This bit is reset when
updated.

Bit 4 - Record Not Found Error Bit - When equal to one, this bit
means that a Data Address Mark was not found within 43 bytes of the
last ID field CRC byte or it can indicate that the desired track,
sector or side was not found.

Bit 5 - Record Type Bit - This bit reflects the type of Data Mark
that was encountered during the read. When set a Deleted Data Mark
was found. If clear, a Data Mark was encountered.

Bit 6 - Always set to o.

Bit 7 - Not Ready Bit - Same as Type I Not Ready Status Bit.

Page 33

PC100 SYSTEM SPECIFICATION
Type II Write Sector Status Bit Description
7

Busy
Data Request
Lost Data
CRe Error
Record Not Found Error
Wr ite Fault
Write Protect
Not Ready
Bit 0 - Busy Bit - Same as Type I status Busy Bit.

Bit 1 - Data Request Bit - This bit means that the data register is
empty and it is waiting for the CPU to write the register.

Bit 2 - Lost Data Bit - When set, it means that the data register
had not been written within 23.0 microseconds and the data on the
disk is not valid (zero bytes are substituted for data lost).

Bit 3 - CRC Error Bit - When set, this bit indicates an error in
one or more ID fields. This bit is reset when updated.

Bit 4 - Record Not Found Error Bit - When equal to one, this bit
indicates that the desired track, sector or side was not found.

Bit 5 - Write Fault Bit - Not implemented; should
always be O.

Bit 6 - Write Protect Bit - When this bit is set after a write
command, then an attempt was made to write on a write protected
disk.

Bit 7 - Not Ready Bit - Same as Type I Not Ready Status Bit

3. Track Register (Port Address 61 Hex)
This R/W 8-bit register holds the updated address of the current read/write
head. It is incremented by one every time the head is stepped toward the
spindle and decremented by one every time the head is stepped away from the
spindle. The contents of the register are compared with the recorded track
number in the 10 field during disk read, write and verify operations.
4. Sector Register (Port Address 62 Hex)
This read/write8-bit register holds the address of the desired sector
position. The contents of the register are compared with the recorded
sector number in the 10 field during disk read and write operations.

Page 34

PC100 SYSTEM SPECIFICATION
5. Data Register (Port Address 63 Hex)
For a seek operation, this 8-bit read/wr ite register holds the desired
track position.
During data transfers, this register is the data buffer
for the disk.

3.1.5.8.2 General Control and Status Register Bit Description: Z80A This 8-bit register holds various control information for the drive as well
as the module. The lowest four bits are read/write while the upper four
bits are read only.

3.1.5.9 General Floppy Control Register: Z80A - The following write-only
register (Port Address 40 Hex) holds control lines used to select drives
and write delay pre-comp values for the floppies.
1.

Bits 0-1 - These bits control the selection of floppy drives. The
binary values written to them (0 - 3) selects drive 0 through 3.
Only 1 drive can be selected at a given time.

Bit 2
Diagnostic READY override bit. When set, this bit asserts
DRIVE READY to the 1193.

Bit 3 - This bit controls the MOTOR o ON bit. Turns on the motor on
in the first drive unit.
4.

Bit 4 - This bit controls the MOTOR 1 ON bit. Turns on the motor on
in the second drive unit •

Bit 5- This bit selects the SIDE of the disk to be accessed.
single-sided drives, this bit is always set to a 0 for side O.

Bits 6-7 - These binary bits are used to control the write delay
pre-comp values. The following table lists the values for all
tracks:
( TG43)

PCl

PCO

TRACK

a
a
a

a
a
a
a

a
a
a

0-9
10 - 19
20 - 29
30 - 39
40 - 49
50 - 60
61 - 69
70 - 79

0
1

0
0
0

0
0
1

Page 35

For

PC100 SYSTEM SPECIFICATION
3.1.5.9.1 Drive Select L1ght Operation - The drive select logic is set up
so that none of the drives are enabled on power-up. When a disk is
installed, the door is closed, the drive is selected and either HEAD LOAD
or MOTOR ON is asserted. Then the drive active indicator light illuminates,
the head loads and the motor turns on. Only one drive can be selected at a
time.
The drive motors, on the other hand, are not gated with any signals. Each
motor on signal can be activated independent of any other condition. The
software never turns on both motors simultaneously.
It is necessary to
d~lay the start of the second selected motor for 500 ms after the start of
the first motor.
CAUTION
When both drive motors are off, a MOTOR ON override
must not be generated for the unselected drive. Due
to a hardware idiosyncrasy, this causes both drive
motors to turn on simultaneously.

3.1.5.10 General Floppy Status Register: ZBOA - The following read-only
register (Port Address LlO Hex) holds the status of the RX50 drive lines
coming from the 1793 FDC and going to the floppy drive.
1.
2.

Bits 0-1 - These bits read back the status of Bit 0 and 1 from the
general floppy control register. They indicate which drives have
been selected.
Bit 2 - This bit reflects the status of the TRACK GREATER THAN 43
signal from the 1793 going to the floppy.
Bit 3 - This bit reflects the status of MOTOR ON 0 line at the
floppy connector. The signal, when read as 0, indicates that t.he
MOTOR ON
bit is set.

Bit 11 - This bit reflects the status of MOTOR ON 1 line at the
floppy connector. The signal, when read as 0, indicates that the
MOTOR ON 1 bit is set.

Bit 5 - This bit reflects the status of the side select signal at
the floppy connector.

Bit 6 - This bit reflects the status of the INTERRUPT REQUEST
signal coming from the 1793. This is used to indicate that a status
bit has changed.

B1 t 7 - This bit reflects the status of the DATA REQUEST Signal
from the 1793. Used to indicate that the 1793 has read data to be
transferred or requires new write data.

Page 36

PC100 SYSTEM SPECIFICATION
3.1.5.10.1 Floppy Disk Controller Required Delays - The following
describes required delays from one operation to the next operation:
Operation

Next Operation

list

Delays Required
(microseconds)

Write to Command Register Read Busy Bit
(status bit 0)

Write to Command Register Read Status
Bits 1-1

write to Any Register

Read from Different
Register

Write to Track, Sector
or Same Register

Read from Data Register

Write to Any Register

Write to Another Register

Interrupt Request

Read Status Register

3.1.5.10.2 Floppy Disk Motor Speedup Detection - While writing to a sector
on a disk, the opening or closing of the OTHER DRIVE'S door will cause a
transient in the floppy spindle motor speed. This transient can make any
sector being written at the time of the opening or closing to be not
readable in all situations. The following procedure is recommended and is
implemented in the BIOS of CP/M-86/80:
Just prior to writing a sector upon the disk, the drive being written to
is de-selected. The other drive IN THE SAME RX50 disk assembly is then
selected and the condition of the Ready bit is sampled. The disk being
written to is then selected again, and the write operation is performed.
After the sector has been completed, the same operation is performed; the
disk drive being written to is de-selected and the sister drive is
selected.
Ready is again sampled. If the condition of this bit had
changed from the prev ious sample taken, then the sector must be
re-written.

3.1.5.10.3 Floppy Controller Head Load Timer Activation - The Head Load
Timer can be fired only in the following circumstance: The Head Load Timer
must not be already timing. This means that neither MOTOR ON bits (MO, M1)
are active, nor is the HEAD LOAD bit (HLD). Upon the next occurance of any
of these three bits, and the state of the drive is READY, then the Head
Load Timer will be actuated. This timer puts a 500-ms delay prior to HLT
going true.

Page 37

PC100SYSTEM SPECIFICATION
3.1.6 Mother Board Physical Dimensions
The mother board is a modified quad module with the following connectors:
Jl
J2

J3
J4
J5
J6
J7

J9
Jl0
J 11

3.2

Communications Connector
Printer Connector
Video/Keyboard Connector
Extended Comms Connector
Extended Comms Connector
Memory Option Connector
Graphics Option Connector
Power Connector
Floppy Controller Pin
A/ B Floppy Board
C/O Floppy Board

25-pin
25-pin
15-pin
40-pin
4D-pin
52-pin
40-pin
13-pin
40-pin
34-pin
34-pin

D-male
D-female
D-male
HEADER
HEADER
HEADER
HEADER

OPTION MODULES

The following option modules will be supported by the Rainbow system:
3.2.1 Memory Option
Description/Features • The memory option for the PC1DO allows the user to
upgrade the system with an additional 64K or 192K bytes of memory.
Additionally, two 64K byte stacks can be added to the option for a total of
192K bytes on the option. Along with the 64K bytes already on the system
mod ule, a total of 256K bytes of available memory for the PC1Da is
possible.
The 64KB and 192KB variants use the same 50 class etch.
not user upgradable.

The 64KB board is

If installed, this memory is always available and never requires
states (except when the memory cycle contends with a refresh cycle).

wait

The option is equipped with parity generation and a parity error
detect circuit to notify the 8088 CPU in the event of a memory error.
If such an error occurs, the memory option interrupts the 8088 CPU
through a non-maskable interrupt •. At this point the firmware takes
the proper action to notify the user.
3.2.2 Extended Communications Option - Description/Features
The extended communications option card is a major component of the PC1Da
system and is. connected to the PC1DD main module via standoffs.
The
pur pose of t.he option is to add a second communications port to the PC 100
with bit and byte synchronous capability.
It also gives the PC10a a
separate high-speed serial communications port to support clustering and
the addition of a high-speed file server. It has two 40-pin connectors
through which it plugs into the system.
Pagt 38

PC100 SYSTEM SPECIFICATION
The extended communications option functions in the following ways within
the PC100:
1.

By means of the 8237 DMA Controller, block transfers data
bidirectionally between memory and the high-speed communications
link (7201 shared MPSC) while maintaining full interrupt support.
The transfer to memory is into the PC100's shared RAM only and not
into optional memory.

Distinguishes bit protocols at a clock rate of 880 kHz by means of
the 7201 MPSC.

Provides an optional bisync port (7201 MPSC) that is a subset of
the PC100's communication port.

Provides two complete serial communications controllers in a single
7201 MPSC package to:

Convert parallel data (from the processor) to ser ial data, as
required by various protocols.

Convert serial data streams of the protocols back to parallel
data for the processor.

Buffer incoming and outgoing data, allowing the processor time
to respond.

Insert and delete framing bits and characters.

Calculate/check parity and check CRC error.

Inform CPU what actions need to be taken and when.

Interface with outside world over discrete modem control lines.

Uses a 7201-Bus Interface Controller to provide:
a.

Bus Control Logic (BCL), which determines the internal source
or destination of data and control transfers between the MPSC
and the processor bus.

Interrupt Control Logic (ICL), which prioritizes internal input
requests and places information on the data bus during an
Interrupt Acknowledge cycle (prov ided the MPSC vectored
interrupt feature has been enabled)

DMA Control Log ic (DMACL), which enables the MPSC to make a
data transfer wi thout interrupting the processor.
DMACL
accepts service requests (if they are prioritized) and, like
ICL (in b above), places information on the data bus at
appropriate times. DMACL also accepts information from the data
bus. When enabling the MPSC, DMACL activates an external
controller to move data directly from the MPSC to memory or
vice versa.
Page 39

PC100 SYSTEM SPECIFICATION
d.

Ciock and Reset Logic (C&RL), which controls timing states in
the MPSC and is (usually) connected to the processor clock.
The extended communications option consists of the following main
components mounted on a printed circuit board:
1.
2.

A 5 MHz 8237 Direct Memory Access Controller (DMAC).
A 7201 Multi-Protocol Serial Controller (MPSC) with the following
features:
a.

A high-speed synchronous serial communications port
external clocks and RS~22 differential drive capability.

with

A general-purpose synchronous serial communications port, with
RS~23 drive capability, capable of supporting bisync modes.

Refer to the Extended Communications Option Functional Specification for
further information.

3.2.2.1 Reset Sequence For Extended Communications. - The firmware will
perform the following RESET function on the Extended Communications option
upon power up ,and any time that it has to handle an interrupt from the
Extended Communications option: A write to 8088 port 27H will reset the
option.

3.2.3 Graphics Option - Description/Features
The Graphics option is a bit mapped color graphics option which resides on
a daughter board inside the Rainbow system box, and attaches to the Rainbow
system board via a ~O-pin connector, J7. The Graphics option will emulate
VT2~O functionality in both graphics and text handling. This includes but
is not limited to the funcionality of the VT100, VT102, and VT125.
The Rainbow system with the color graphics option can operate in one of two
modes, text only or graphics/text. In text only (VT100 text mode), the
graphics option video will be deselected.
During this time, the DC 11 and
DC12 on the system board will be responsible for providing signals to the
monitor. During Graphics/text mode, the option will be selected.

Page 40

PC100 SYSTEM SPECIFICATION
3.2.3.1 Features
following features:
a.
b.
c.
d.
e.

The

Graphics

option

for

Rainbow

will

support

Low resolution mode - 240 X 400 pixels X 4 planes.
High resolution mode - 240 X 800 pixels X 2 planes.
16 simultaneous colors from a pallet of 4096.
9600 baud character throughput (HARDWARE ONLY)
Smooth and jump split screen scrolling

4.0 RISO DRIVE
4.1 GENERAL DESCRIPTION
The RX50 subsystem is a 5-1/4-inch flexible diskette drive and a
single board controller which enables the PC100 to store or retrieve
information on one side of each front-loaded diskette. Each diskette
can contain up to 409,600 8-bit bytes (formatted), allowing a total of
819,200 bytes of storage per device.
4.2

DRIVE CHARACTERISTICS
No. of recorded surfaces
No. of diskettes/drive
No. of tracks/surface
No. of sectors/track
No. of bytes/sector
No. of bits/byte

Capacity (formatted)
per drive
per surface
per track

2
2

80
10
512
8

819,200 bytes
409,600 bytes
5,120 bytes

Access Time, track to track
head load time,
including settle time
rotational latency
random access
drive motor start

6 ms, one track
30 ms. max
100 ms typical, 200 ms max.
290 ms average
500 ms max.

Transfer rate

250K bytes/sec (average)

Disk rotation

300 RPM + lJ , -

Size

5.75 in. wide x 3.25 in. high x
8.5 in. deep

Weight

3.8 pounds

Page "1

the

PC100 SYSTEM SPECIFICATION
4.3

TRACK FORMAT

Each of the tracks is formatted as described below. Each data field
is made up of 512 8-bit bytes, with a total of 10 data fields or
sectors numbered 01 through OA (hex) on each track. The following is a
description of the track fields.
Description

No. of Bytes

Pte 10 gap
10 Fields

!l7

!IE

8
3

00
A1**
FE
Track no. COC-4F>
00
Sector n. C01-OA)
02
Calculated header CRC code
4E

Sync
"'ark
Header lOAM
Track Address
Side Number
Sector Address
Bytes/sector code
CRC
Pose 10 gap
Data Fields
Sync
Mark
Data DM·;
Data
CRC
Post amble
Pre-index gap

1
1
1
1

1
1

22
12
3
1

512
2
1

*70

Contents (HEX)

00
A1**
FB
20H
Calculated data CRC code
00
!IE

This field is written once per track until
encountered.
** The clock bit is missing between bits 4 and 5.

index

field

Fields modified by a WRITE operation are:
1.
2.

!I.
5.

The
The
The
The
The

DATA SYNC field
DATA MARK field
DATA field
DATA CRC field
POST AMBLE field

4.4 HEADER FORMAT
The diskettes are pre-formatted with header data. The header data fields
cannot be modified or re-written by the system. The header field is made up
of seven 8-bit bytes as follows:
Byte 1:

10 Address Mark (IDAM) , FE (hex). This byte coupled with the
10 SYNC FIELD and MARK field is decoded by the controller to

identify the start of a header.
Page 42

PC100 SYSTEM SPECIFICATION
Byte 2:

Track Address. This is the absolute binary track address (00
to 4F hex). Each sector contains track address information to
identify its radial position on 1 of 80 separate tracks.

Byte 3:

Zeros.

Byte 4:

Sector Address. This is the absolute binary sector address (01
to OA hex).
Each sector contains address information to
identify its circumferential position on a track. There is no
sector 00.

Byte 5:

Sector Length 02 hex. This byte specifies the number of bytes
contained in one sector. The RX50 drive is formatted with 512
bytes per sector.

Byte

6,7:
These two bytes represent the cyclical redundancy check
characters that are calculated from the first five header
byte s .

5.0

PC100 FIRMWARE

6.0

PRODUCT GOALS

The PC10a firmware includes two variations of VT102 emulation: "terminal"
mode and "console" mode. "Terminal" mode enables PC100 to act like a VT102
connected to a host computer via the communications port.
The "console"
mode enables PC100 to act like a VT102 (without printer port and using fDX
data leads only as a protocol) when running programs on the PC100.
The firmware provides services to a "user" for console-out, console-in,
console-in-status, enable/disable cursor, line-at-a-time screen data
transfers, initialize interrupt vectors, return clock rate, l6-bit "key
data", and keyboard LED control.
Communications and printer port drivers
are supplied the operating system in console mode.
The firmware
loader.

also provides self-test diagnostics and a minimal bootstrap

6.1 GOALS
The PC100 VT102 emulation runs a firmware program using the 8088 processor
and
looks to the user like a VT102.
It provides subfunctions in modules
usable to other programs.
These other programs need to be able to execute
similar functions.
The VT102 emulation processes incoming character
strings in the same manner as a VT102.
The VT102 emulation also returns
characters to the host in a manner similar to that of VT102 given the same
SET -UP env ironment.
Di fferences between VT 102 and PC 100 emul ation are
listed below.

Page 43

PC100 SYSTEM SPECIFICATION
VT52 emulation wi thin the VT 102 emulator performs as a VT 102 (i.e. VT 102
emulation of VT52 incl udes most VT102 functions such as 132 col umns,
auto-wrap, split screen, double high, double wide, etc.).
The basis for
VT102 functionality is the VT102 engineering specification REV A (SP
VT102-0-02 A) dated l-Aug-81.
6.1.1

Functional Anomalies

The following is a list of deviations from VT102 functionality, variances
with TIA (terminals interface architecture), and other features of the
firmware.
1.
When printing from the screen in terminal mode and encountering a
"blob" character, the VT102 sends ASCII "SUB" to the printer.
The PC100
sends the VT100 line-drawing graphics character "blob", bracketed by the
appropriate character set selection escape sequences, if required.
Also,
PC10a assumes the printer is capable of properly receiving 8-bit DEC STD
169 characters.
2.
If keyboard is locked, break key does not function.
This has been
fixed in the
1/18 Rml set.
All "Break Key" functions work with keyboard
locked, but they also cause the keyboard to unlock.
3.
Break Key and its associated
auto-repeat, as in a VT102.

control

and

shift

4.
A backspace received when beyond column 127
return. This has been fixed in the 1/18 ROM set.

acts

functions
like

not

carriage

5.
At the completion of a "print cursor line" operation, pel0a sends the
escape string to restore the printer'S GO character set in between the
terminating carriage return and line feed.
VT102 sends it after the line
feed.
6.
If a key is auto-repeating and the control key is then pressed, any
resulting control character also auto-repeats. This has been fixed in the
1/18 ROM set.
7.
Locking and unlocking the keyboard while a key is auto-repeating. or
attempting to, has no effect.
This has been partially fixed in the 1/18
ROM set.
Locking the keyboard does stop an auto-repeat, but unlocking the
keyboard does not re-start auto-repeat unless the original key is still the
one held down. Any new key must be pressed after the keyboard is unlocked,
in order to have it auto-repeat.
8.
Escape sequences that move the cursor down and right cause incorrect
cursor locations (it disappears) if the parameter plus the current location
add up to 0 in an 8-bit value. The terminator and pointer of a screen line
can be modified as a result of subsequent actions. This has been fixed in
the 1/18 ROM set.

Page iIiI

PC100 SYSTEM SPECIFICATION
9.
When the SET-UP key is pressed to enter SET-UP mode in the PC100, the
key-holding buffer is cleared, which causes any unserviced keys to be lost,
and SET-UP is immediately honored.
10. When the keyboard buffer fills up, the PC100 ignores further entries
and sounds the bell. It does not light the keyboard-locked LED as does the
VT102. This has been fixed in the 1118 ROM set.
11. The printer port baud rate selection and the communications port
external clock selection both reside in the same wr i te-onl y 8088 port.
Selecting communications port external clocks can make the printer port
baud rate incorrect and selecting printer port baud rates in SET-UP will
de-select external clocks for communication.
Also, the break control bit
for the 7201 is in the same write-only register as the number-of-data-bits.
The firmware can read the NVM and set this properly for use with terminal
mode. An application cannot do this.
12. PC100 keeps two separate "graphics mode" flags; one for VT52 mode and
one for ANSI mode. VT102 keeps only one flag, which applies to both.
In
the 1118 ROM set, selecting ANSI or VT52 mode also initializes character
sets and selection to non-graphics.
13. PC100 maintains wrap-pending flag unconditionally, and tests it
conditionally.
VT102 maintains the flag conditionally and tests it
unconditionally.
This affects where the next character goes when the
auto-wrap mode is changed while the cursor is in the "line-filled"
posi tion.
14. In PC100, the escape sequences to select alternate ROM and alternate
ROM special graphics are parsed but ignored.
15.

NVM defaults are not the same as VT102 for the printer port.

16. PC10a executes C1 control codes for index, next line, horizontal tab
set, reverse index, single shif.t 2, single shift 3, and control sequence
introducer. Reception of any Cl control code (or 8-bit graphics character)
will abort an escape sequence in process (CSI restarts an escape sequence).
In the 1/18 ROM set, 8-bit graphic characters will be displayed if received
during an escape sequence and will not abort the parsing.
17. PC 100 always
say ing into NVM.

sets

insertionlreplacement mode

replacement before

18. PC100 requires use of the shift key for some of the keyboard-entered
control codes.
This is due to the uncertainty of character location on
various foreign-language keyboards.
19. The PG100 accepts and acts on 8-bit character codes; the VT102 always
strips the 8th bit. If 8-bit codes are received in VT52 mode, they will be
handled the same as in ANSI mode.
20. Shift out (GTRL/N) and shift in (GTRL/O) in VT52 mode will abort VT52
"graphics" operation if the character set selected is not the "graphics"
set.
Page 45

PC100 SYSTEM SPECIFICATION
21.
In console mode, with default character set for UK, G2 and G3 are
initialized to UK, but GO and Gl are initialized to U.S. The operator must
enter SET-UP and toggle the US/UK default selection to get GO and Gl into
UK. This has been fixed in the 1/18 ROM set to use the correct default
character set.
22.
Terminal mode print functions are implemented via the "print screen"
key on the PC100. VT102 uses the keypad "enter" key.
PC100 "print screen"
is equivalent to VT 102 <shift/enter> and PC100 <control/print screen> is
equivalent to VT102 <control/enter>.
23. When hold-screen is in effect, all attempts to "receive" a character
will hang until hold-screen is removed.
This includes selections from the
opening menu, console out requests, data moves to screen display, and
terminal mode character reception.
In terminal mode, the receive buffer
will continue to fill, but will not be emptied.
When "full", it will
automatically send XOFF if enabled in SET-UP; otherwise, data will be lost
if the host does not stop sending.
In the 1/18 ROM set, the diagnostic
routines in ROM have been given a separate entry to the display process
that bypasses the "Hold Screen" test.
2~.
The PC100 will parse but ignore the escape sequences to set GO and Gl
to the alternate ROM and alternate ROM special graphics ( ESC ( 1 , ESC ( 2
, ESC) 1 , ESC) 2).
It will also parse but ignore the escape sequences
to run self-tests ( ESC [ 2 ; Pn y ) and the LED control ( ESC [ Pn q).
Also, the device status report request ( ESC [ 5 n ) will always cause the
ready, no malfunctions reply ( ESC [ 0 n ).

25.
Serial line SET-UP selections of 7-bit mark and space actually use the
7201 in 8-bit no-parity mode.
The mark/space aspect is handled by the
firmware drivers in terminal mode.
In console mode~ the operating system
drivers do not make this distinction, and set-ups 7M and 7S are the same as
8N in console mode.
26.
The HOLD-SCREEN key on the PC10a does not work the same as the NO
SCROLL key on the VT102.
On a VT102, it sends an XOFF/XON as it toggles
back and forth, and CTRL/ Sand CTRL/Q typed from the keyboard can be used
to get the same effect.
In PC100, setting HOLD SCREEN does not necessarily
cause an XOFF to be sent.
It sets an internal flag that causes the
"receive character" process to loop until the flag is cleared.
This
effectively "hangs" any console output (normal or direct) .in console mode.
In terminal mode, this "hang" causes the communication receive buffer to
fill up until it reaches the high-water mark, at which point it will send
an XOFF if enabled by SET-UP. After the HOLD SCREEN is removed, characters
are removed from the receive buffer until the low-water mark is reached,
which causes XON to be sent if enabled.
As a resul t of this method of
implementation, PC100 honors HOLD SCREEN even in "local"; VT102 does not.
27.
PC100 resets CAPS LOCK to "lower case" any time the
selection is made from the opening menu.

"s"

(self test)

28.
The following keys generate escape sequences that end in characters
that cause valid selections at opening menu time: cursor arrow keys will
select drives to boot from and PF~ in the keypad will select self-test.
Page 116

PC100 SYSTEM SPECIFICATION
29. The PC100 in VT52 mode honors the origin mode setting; the VT102 in
VT52 mode does not.
30. In PC100 escape sequences for erase in line and erase in display, only
the first selective parameter is processed if more than one is sent.
31. In PClOO, ESC c (reset to initial state) does not reset keypad and
cursor keys to their normal modes.
32. In PC100, print screen while screen is "held" is deferred until after
"hold" is removed and the character being "held" is processed.
33. In PC 100 terminal mode, after using "hold-screen" on incoming data,
the last character for display is being "held". Entering SET-UP, switching
to local, and exiting from SET-UP does not clear the "hold" state or t.he
character.
When "hold" is finally removed, the character originally being
"held" is displayed before any locally-generated characters.
34. In PC100, any noise on the printer port DTR line can cause
interrupt that will set a flag indicating a printer was once available.

35. In PC100, cursor key mode and keypad mode are independent.
This
agrees with the TIA specification, but not the VT102.
In the VT102, the
cursor keys only send application codes if both cursor and keypad modes are
set to "application".
36. In PC100, the TAB character always clears the wrap-pending flag. This
agrees with the TIA specification, but not the VT102.
As a result,
auto-wrap will not be the same if TAB is the 81st character in an
80-character line. Character 82 will not wrap, but character 83 will. In
VT102, character 82 will wrap.
37. In PC 100 terminal mode, the second XOFF is sent at "buffer-full". In
VT102, the second XOFF is sent 12 characters before "buffer-full".
Also,
the PC100 buffer is 255 characters in size; the VT102 is 128.
38.

PC100 allows a tab stop in the first column; VT102 does not.

39. Function keys are not ignored when entering the answerback message,
and they produce unpredictable results.
40. PClOO aborts escape sequence parsing when it finds an intermediate
character, causing all following characters to be displayed.
VT102 aborts
the sequence, but continues parsing until it finds a final character, so
the intervening part of the escape sequence does not display.
41. Because of differences in implementation and timing, the PC100 and
VT102 can have different transient appearances where the cursor is
concerned.
For example, the cursor may appear momentarily and/or in
different locations when the same data is sent to both for display.
42. In terminal mode, local, printer
keyboard characters to the printer.
Page 47

controller

mode

does

not

send

PC100 SYSTEM SPECIFICATION
A single-shift 2 or 3 is not preserved across escape sequences. If an
intervening escape sequence occurs, the following graphic character set is
not affected.
This is also true for intervening control sequences and
8-bit control codes.
~3.

~~.
Any printer-related escape sequence (ANSI or VT52) or keyboard entry
isignored if the printer DTR signal is not asserted at toe time.
After
printing begins, the state of the DTR from the printer is ignored.

Switching auto-xon/xoff after establishing contact can cause the
"Terminal" to hang under the right conditions.
Typing an xon (CTRL/Q) in
these cases should clear the hung state.
~5.

6.2 PERFORMANCE
The per formance of the VT 102 emulation is at least equal to that of the
actual VTl02. Using pure text for data in jump scroll mode, the VT102
emulation operates at 9600 baud unrestrained as a terminal. It is a goal
for it to operate at 38.~K baud as a console.

6.3 NON-GOALS
The non-goals for this program are:
1.
2.
3.

6.~

Emulation of bugs in the VT102 software.
SET-UP mode identical to that of the VT102.
The VT102 firmware excludes all VT131 hooks.
for editing, block mode transmit, protected
linkage, etc.
All printer baud rates of VT102 supported.

There is no support
fields, option ROM

GENERAL

The firmware of the PC-lOa provides the following services:
1.
2.
3.
~.

Power-up initialization of hardware
Self-test diagnostics
VT102 emulation - available in "terminal" and "console" modes
Image of Z80 RAM space to be loaded
Boot loader to read track 0, sector 1 of floppy

Page 118

PC100 SYSTEM SPECIFICATION
6.
7.

Opening menu selection process
Automatic shut-off of screen display after 30 minutes of non-use,
and restoration of display on first activi~y (any keyboard key or
received character).

The firmware is organized such that the VT102 emulation primitives form the
"console" functionality for use by "applications" through the interface
layer. When in "terminal" mode, a background loop is entered which calls on
the "console" primitives and adds the necessary functionality to provide
full "terminal" mode.
An interface layer is placed over the "console" primitives to provide an
"application" with means of accessing those primitives.
Note
In "console" mode there is no support provided for
the printer or the communication ports. This
hardware (7201) must be controlled directly by the
operating system.
For "applications" that need more immediate control of the hardware,
services are provided to obtain "raw" key information, enable/disable
cursor, and transfer data directly to screen RA~l.
The interface between
the "application" and
the
firmware
is implemented using a software
interrupt,with arguments passed and returned in CPU registers.
This leads to a layered structure as diagramed below.
From the firmware
view pOint, the operating system in this example is an "application".
It
can actually be anything, including another firmware routine.
All entries to firmware routines from external processes are via a software
interrupt.
This makes the interface release-independent because ROM code
loads the proper vectors during initialization.
8088 side

--------,---------,-------------1 NORMAL 1
I

USER

:,----------------,
OPERATING
:
1
SYSTEM
1
••••••••••••• •••••••••••••••••••••••
,

•
VT102
•
• 'TERMINAL' •

INTERFACE
LAYER

•

X •

•••••••••••••••••••••••••••••••••••••
•
VT102 'CONSOLE' PRIMITIVES
•
····················*····*··*········---1-----1 VIDEO 1 KBD 1 PRINTER 1
COMM
1 OPT
1 HDWR
PORT
PORT
: HDWR
,
,---------------------------------------------SU indicates sophisticated user; ••••• indicates located in ROM
Page Jl9

PC100 SYSTEM SPECIFICATION
6.4.1

Text Strings

All text strings are located in a single section of the code space so they
may be changed with no effect on ROM code (foreign languages). The t~xt
strings are accessed by a table of pointers that remains in a fixed
location so routines do not need to know the exact text locations. This
table and its associated text strings are in one ROM to minimize changes
required for other language versions.
The keyboard key-to-code mapping
tables are also in this same ROM.
The total amount of ROM space allocated to text strings cannot be
increased.
There is no restriction on individual string size, only total
bytes used and order of messages.
6.4.2 Character Sets
As with the VT 102, the VT 102 emulation supports the following character
sets: UK, USASCII, Special graphics.
The character generator ROM also contains the displayable right half of the
DEC multinational character set (shown as the DEC supplemental graphic set
in DEC STD 169). These characters are accessed by direct writing of data
into the screen via interrupt 40 or by reception of the corresponding 8-bit
code.
The character generator ROM also contains space for 31 additional
displayable characters to be determined.
The "console" VT102 accepts 8-bit character codes to display the alternate
characters.
The "terminal" VT102 accepts 7- or 8-bit codes (depending on
communication port parameters) and displays characters based on character
set mapping through escape sequences. The "console" also works with escape
sequence character set mapping and 7-bit characters.
The PC100 also accepts 8-bit C1 control codes for index, next line,
horizontal tab set, reverse index, single shift 2, single shift 3, and
control sequence introducer.
Any C1 control code will abort an escape
sequence in process, and CSI will re-start it.
Table 2 lists the characters and corresponding codes available in the PC100
for display. The codes are actually a part of the address for the bit map
of that character in the character generator ROM. They are the upper eight
bits of the address; the lower four bits select the proper scan line within
the character. There are six unused "scan lines" at the end of each
character (uses 10 out of 16).
Note
All undefined and reserved characters are indicated
by an upside-down question mark.

Page 50

PC1DO SYSTEM SPECIFICATION
Table 2. Displayable Characters and Corresponding Codes

CHAR
CODE
IN RAM

CHAR
CODE
RCVD

8 BITS

7 BITS

(HEX)

00
01

02
03

60
61
62

05
06
07

64
65
66
67
68

08
09
OA
OB
OC
OD
OE
OF

69
6A
6B

6C
6D
6E

10
11

12
13

15
16

77
78

1A
1B
1C
1D
1E

79
7A
7B
7C
7D

CHAR SET(DEFINES
RULES FOR RCVD TO
RAM TRANSLATE)

ALL
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
SPECL GRAPHICS
UK
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS

NAME OF CHARACTER

NULL,IGNORED ON RCV, DISPLAYS A BLANK
BLANK
DIAMOND
CHECKERBOARD (BLOB)
HT (HORIZONTAL TAB)
FF (FORM FEED)
CR (CARRIAGE RETURN)
LF (LINE FEED)
DEGREE SYMBOL
PLUS/MINUS SIGN
NL (NEW LINE)
VT (VERTICAL TAB)
LOWER RIGHT CORNER
UPPER RIGHT CORNER
UPPER LEFT CORNER
LOWER LEFT CORNER
CROSSING LINES
HORIZONTAL LINE, SCAN 1
HORIZONTAL LINE, SCAN 3
HORIZONTAL LINE, SCAN 5
HORIZONTAL LINE, SCAN 7
HORIZONTAL LINE, SCAN 9
LEFT 'T'
RIGHT 'T'
BOTTOM 'T'
TOP 'T'
VERTICAL BAR
LESS-THAN OR EQUAL
GREATER-THAN OR EQUAL
PI SYMBOL
NOT EQUAL SIGN
U.K. POUND STERLING SIGN
CENTERED DOT
SPACE
EXCLAMATION POINT
DOUBLE QUOTES
NUMBER SIGN (POUND SIGN)
DOLLAR SIGN

Page 51

PC100 SYSTEM SPECIFICATION
Table 2. Displayable Characters and Correspond in, Codes
CHAR
CODE
IN RAM
8 BITS
(HEX)

CHAR
CODE
RCVD
7 BITS

CHAR SET(DEFINES
RULES FOR RCVD TO
RAM TRANSLATE)

UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS

NAME OF CHARACTER

PER-CENT SIGN
AMPERSAND SIGN
SINGLE QUOTE
LEFT PARENTHESES
RIGHT PARENTHESES
ASTERISK SIGN
PLUS SIGN
COMMA
DASH (MINUS SIGN)
PERIOD
SLASH (FRACTION BAR)
NUMERAL 0
NUMERAL
NUMERAL 2
NUMERAL 3
NUMERAL 4
NUMERAL 5
NUMERAL 6
NUMERAL 1
NUMERAL 8
NUMERAL 9
COLON

Pal. 52

PC100 SYSTEM SPECIFICATION
Table 2. Displayable Characters and Corresponding Codes
CHAR
CODE
IN RAM
8 BITS
(HEX)

CHAR
CODE
RCVD
7 BITS

CHAR SET(DEFINES
RULES FOR RCVD TO
RAM TRANSLATE)

NAME OF CHARACTER

SEMI-COLON
LEFT ANGLE BRACKET
EQUALS SIGN
RIGHT ANGLE BRACKET
QUESTION MARK
AT SIGN
CAPITAL A
CAPITAL B
CAPITAL C
CAPITAL D
CAPITAL E
CAPITAL F
CAPITAL G
CAPITAL H
CAPITAL I
CAPITAL J
CAPITAL K
CAPITAL L
CAPITAL M
CAPITAL N
CAPITAL a
CAPITAL P

Page 53

PC100 SYSTEM SPECIFICATION
Table 2. Displayable Characters and Corresponding Codes
CHAR
CODE
IN RAM
8 BITS
(HEX)

CHAR
CODE
RCVD
7 BITS

CHAR SET(DEFINES
RULES FOR RCVD TO
RAM TRANSLATE)

60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D

UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UKI USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
SPECL GRAPHICS
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII

NAME OF CHARACTER

CAPITAL Q
CAPITAL R
CAPITAL S
CAPITAL T
CAPITAL U
CAPITAL V
CAPITAL W
CAPITAL X
CAPITAL Y
CAPITAL Z
LEFT SQUARE BRACKETS
BACK-SLASH
RIGHT SQUARE BRACKETS
CIRCUMFLEX
UNDERLINE
ACCENT GRAVE
LOWER CASE A
LOWER CASE B
LOWER CASE C
LOWER CASE D
LOWER CASE E
LOWER CASE F
LOWER CASE G
LOWER CASE H
LOWER CASE I
LOWER CASE J
LOWER CASE K
LOWER CASE L
LOWER CASE M

Page 54

PC100 SYSTEM SPECIFICATION
Table 2. Displayable Characters and Corresponding Codes
CHAR
CODE
IN RAM
8 BITS
(HEX)

CHAR
CODE
RCVD
7 BITS

CHAR SET(DEFINES
RULES FOR RCVD TO
RAM TRANSLATE)

6E
6F
10
11
12

13
14
15
16
71
18
19
1A
1B
1C
1D
1E
1F

111
15
16
11
18
19
1A
1B
1C
1D
1E
1F

UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
UK/USASCII
ALL

80
81
82
83

84
85
86
81
88
89
8A
8B

8D
8E
8F
90
91
92
93
911
95
96

NAME OF CHARACTER

LOWER CASE N
LOWER CASE 0
LOWER CASE P
LOWER CASE Q
LOWER CASE R
LOWER CASE S
LOWER CASE T
LOWER CASE U
LOWER CASE V
LOWER CASE W
LOWER CASE X
LOWER CASE Y
LOWER CASE Z
LEFT BRACES
VERTICAL LINE (BROKEN)
RIGHT BRACES
TILDE
RESERVED FOR CHARACTER GENERATOR ROM
CHECKSUM
DISPLAYS JUNK, SHOULD NOT BE USED
UNFILLED RECTANGLE FOR 'AUTO-BLANKED
CURSOR'
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERP.lINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
Page 55

PC100 SYSTEM SPECIFICATION

Table 2. Displayable Characters and Corresponding Codes
CHAR
CODE
IN RAM
8 BITS
(HEX)
97

99
9A
9B
9C
9D
9E
9F
AD
A1
A2

A3
All

A5
A6

A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2

B3
B4

B5
B6

B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2

CHAR
CODE
RCVD
1 BITS

CHAR SET(DEFINES
RULES FOR RCVD TO
RAM TRANSLATE}

NAME OF CHARACTER

TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
TO BE DETERMINED
NOT USEr
INVERTED EXCLAMATION POINT
CENT SIGN
U.K. POUND STERLING SIGN
RESERVED (DEC STD 169)
YEN SIGN
RESERVED (DEC STD 169)
SECTION SIGN
GENERAL CURRENCY SIGN
COPYRIGHT SIGN
FEMININE ORDINAL INDICATOR
LEFT ANGLE QUOTATION MARKS
RESERVED (DEC STD 169)
RESERVED (DEC STD 169)
RESERVED (DEC STD 169)
RESERVED (DEC STD 169)
DEGREE SIGN
PLUS/MINUS SIGN
SUPERSCRIPT 2
SUPERSCRIPT 3
RESERVED (DEC STD 169)
MICRO SIGN
PARAGRAPH SIGN, PILCROW
MIDDLE DOT
RESERVED (DEC STD 169)
SUPERSCRIPT 1
MASCULINE ORDINAL INDICATOR
RIGHT ANGLE QUOTATION MARK
FRACTION 1/4
FRACTION 1/2
RESERVED (DEC STD 169)
INVERTED QUESTION MARK
CAPITAL A WITH GRAVE ACCENT
CAPITAL A WITH ACUTE ACCENT
CAPITAL A WITH CIRCUMFLEX ACCENT

Page 56

PC100 SYSTEM SPECIFICATION
Table 2. Displayable Characters and Corresponding Codes

CHAR
CODE
IN RAM
8 BITS
(HEX)

C4
C5
C6
C7
C8
C9

CA
CB

CC
CD
CE
CF
00
01
D2

03
04
05
06
07
08

09
OA
DB
OC
DD
DE
DF
EO
E1
E2

E3
E4

E5
E6

E7
E8
E9

EA
EB
EC
ED
EE

CHAR
CODE
RCVD
7 BITS

CHAR SET(DEFINES
RULES FOR RCVD TO
RAM TRANSLATE)

NAME OF CHARACTER

CAPITAL A WITH TILDE
CAPITAL A WITH UMLAUT
CAPITAL A WITH RING
CAPITAL AE DIPTHONG
CAPITAL C WITH CEDILLA
CAPITAL E WITH GRAVE ACCENT
CAPITAL E WITH ACUTE ACCENT
CAPITAL E WITH CIRCUMFLEX ACCENT
CAPITAL E WITH UMLAUT
CAPITAL I WITH GRAVE ACCENT
CAPITAL I WITH ACUTE ACCENT
CAPITAL I WITH CIRCUMFLEX ACCENT
CAPITAL I WITH UMLAUT
RESERVED (DEC STD 169)
CAPITAL N WITH TILDE
CAPITAL 0 WITH GRAVE ACCENT
CAPITAL 0 WITH ACUTE ACCENT
CAPITAL 0 ~ITH CIRCUMFLEX ACCENT
CAPITAL 0 WITH TILDE
CAPITAL 0 WITH UMLAUT
CAPITAL OE DIPTHONG
CAPITAL 0 WITH SLASH
CAPITAL U WITH GRAVE ACCENT
CAPITAL U WITH ACUTE ACCENT
CAPITAL U WITH CIRCUMFLEX ACCENT
CAPITAL U WITH UMLAUT
CAPITAL Y WITH UMLAUT
RESERVED (DEC STD 169)
GERMAN SMALL SHARP S
LOWER CASE A ~ITH GRAVE ACCENT
LOWER CASE A WITH ACUTE ACCENT
LOWER CASE A WITH CIRCUMFLEX ACCENT
LOWER CASE A WITH TILDE
LOWER CASE A WITH UMLAUT
LOWER CASE A WITH RING
LOWER CASE AE DIPTHONG
LOWER CASE C WITH CEDILLA
LOWER CASE E WITH GRAVE ACCENT
LOWER CASE E WITH ACUTE ACCENT
LOWER CASE E WITH CIRCUMFLEX ACCENT
LOWER CASE E WITH UMLAUT
LOWER CASE I WITH GRAVE ACCENT
LOWER CASE I WITH ACUTE ACCENT
LOWER CASE I WITH CIRCUMFLEX ACCENT
Page 57

PC100 SYSTEM SPECIFICATION
Table 2. Displayable Characters and Corresponding Codes
CHAR
CODE
IN RAM
8 BITS
( HEX)

CHAR
CODE
RCVD
7 BITS

CHAR SET(DEFINES
RULES FOR RCVD TO
RAM TRANSLATE)

LOWER CASE I WITH UMLAUT
RESERVED (DEC STD 169)
LOWER CASE N WITH TILDE
LOWER CASE 0 WITH GRAVE ACCENT
LOWER CASE 0 WITH ACUTE ACCENT
LOWER CASE 0 WITH CIRCUMFLEX ACCENT
LOWER CASE 0 WITH TILDE
LOWER CASE 0 WITH UMLAUT
LOWER CASE OE DIPTHONG
LOWER CASE 0 WITH SLASH
LOWER CASE U WITH GRAVE ACCENT
LOWER CASE U WITH ACUTE ACCENT
LOWER CASE U WITH CIRCUMFLEX ACCENT
LOWER CASE U WITH UMLAUT
LOWER CASE Y WITH UMLAUT
RESERVED (DEC STD 169)
NOT ALLOWED, THIS IS 'TERMINATION' CODE

EF
Fa
Fl
F2

F3
F4

F5
F6
F7

F8
F9
FA
FB
FC
FD
FE
FF

6.5

NAME OF CHARACTER

START-UP/SHUT DOWN/RESET

6.5.1 Power-Up Initialization
This process initializes all the hardware, including any indicated
EXPANSION RAM options and all the flags, pointers, etc. Power-up must also
read in the contents of the NVM and configure itself accordingly. The NVM
contains information on memory configuration for use by self-test
diagnostics. It shows which 64K memory blocks are installed.
The option
installer must enter this information at the time of installation. There is
a choice in the Set-Up that provides this "RAM Option Configuration" Set-Up
service.
The NVM consists of two elements, the non-volatile storage part and a
volatile shadow RAM part. A recall operation transfers the contents of the
non-volatile storage part to the shadow RAM part.
A store operation
transfers the contents of the shadow RAM part into the non-volatile storage
part, destroying any previous contents. Data can only be transferred
to or from the CPU from the shadow RAM part, and only when the NVM is not
either in the recall or store modes of operation.

Page 58

PC1DD SYSTEM SPECIFICATION
A CRC is calculated and stored along with the shadow RAM data. This CRC is
verified after any recall operation.
If the CRC does not verify, thE:
recovery procedure is:
1.
2.

A second recall is done.
If second recall is OK, continue as normal.
3. If second recall is also bad, it could be due to two reasons:
a. first time ever used, contains random data
b. bad NVM
4. Put defaults into shadow RAM, store into NVM, and display
ERROR, INITIALIZED TO DEFAULTS message and continue as normal.
6.5.2 Power-Off

NVM

No attempt to do anything special is made on power-off.
6.5.3 Hardware Resetting
The system resets similar to a VT102. Enter Set-up mode and press the Ctrl
key and the Set-Up key simultaneously.
The resetting is accomplished by
jumping to a separate location at the start of the self-test diagnostics.
Entry at this point distinguishes it from a power-up start.
This assumes the system is still capable of entering Set-Up. If not, the
only recovery is to cycle the power off and on.
CAUTION
Leaving interrupts disabled for 100 ms or more in
the 8088 CPU causes the hardware failure detect
circuitry to be activated.
6.5.4 RAM Parity Error
When the expansion RAM is installed, a parity error activates the NMI
input. The NMI causes the message FAILURE, RAM OPTION, CONSULT YOUR USER'S
GUIDE to be displayed on the screen and causes the bell to beep. tlo more
options are allowed except to enter Set-Up and reset the system.
If an operating system needs to handle parity errors itself, it takes over
the NMI interrupt vector.
6.6 MEMORY-MAPPED VIDEO ACCESS SERVICE
A "sophisticated user" accesses the s6reen/attribute RA~ directly for fast
data transfers.
Note
The character stored in the screen RAM by this process
is actually a code (not necessarily ASCII).
This code
is bits 4
11 of the
address in the character
generator ROM for the first scan line of the bit
pattern of that character. See subhead 6.4.2.
Page 59

PC100 SYSTEM SPECIFICATION
The screen display is a linked list and there are several related tables,
flags, and pointers that must be retained. It is imperative, then, that the
"sophisticated user" follow certain restrictions when directly accessing
the screen/attribute RAM.
1.

In order to guarantee a known starting condition and remove all
effects of scrolling, double height, double width line, top and
bottom margins, origin mode, and so on, the user must send the
escape sequence to set the desired screen width. These also place
the cursor at the top, left screen position and clear the screen.
for 80 columns escape [ ? 3 1
for 132 columns escape [ ? 3 h
Note
A lower case L is used here.

The standard escape sequences to position the cursor and set double
height and wid th 1 ines can be used. The user is responsible for
keeping track of what lines have been modified so no attempt is
made to put more characters on a line than it can hold.

CAUTION
Each line ends with a termination code and pointer
to the next line. Video display hardware uses these
in its operation. Destroying these values in either
s c r e e n d i s pIa y
aT
a t t rib ute
spa c e
c a use s
unpredictable results on the display.

Each character (data) screen position has a related attribute. ~hen
the screen width escape sequence initializes the screen, these
attributes are all set to the "off" condition.
Bit assignments for character attributes are:

= Reverse Video
o = normal
1 = reverse video
Bit 1 = Bold
o = bold
1 = not bold
Bit 2 = Blink
o = blink
1 = not blink
Bit 3 = Underscore
o = underscore
1 = not underscore
Bit 0

Contents of character locations can be changed at any time.
However due to the way the cursor is implemented, attributes at the
cursor position cannot be changed at will. When the user wishes to
change the attributes of the character at the cursor position, he
must use the DISABLE CURSOR function.
This removes all cursorrelated attribute affects. After the attributes have been changed
Page 60

PC100 SYSTEM SPECIFICATION
as desired, the user must use the
ENABLE
CURSOR function to
restore the cursor to operation.
See sections 10.1.5 and 10.1.6
for these functions.
6.7 KEY ACCESS SERVICES
This allows a "sophisticated user" to obtain "raw" key data (e.g. a code
for left arrow instead of an escape sequence) to simplify the process of
detecting special keys. If no key is waiting for detection a "no data"
status is returned.
Two different layers of access are prov ided. The lowest level (Level 1)
gives a unique 16-bit code for any key in combination with any or all of
the Shift, Caps Lock, or Ctrl keys. It also identifies the function keys
with a unique code (reference table X). The highest level (Level 2) is the
same as the VT102 generates, plus additional 8-bit codes for certain keys
and foreign keyboards. Certain keys are trapped out for special processing
and are never seen in the buffer. The following keys cannot be remapped:
Key

Position

Hold Screen
Set-Up
Control
Caps Lock
Shift Keys

G99
GOl
e99

COO
B99,B11

Any other keys may be re-mapped by a "console" mode user.
7.0 FUNCTIONAL DEFINITION
7.1

OPERATIONAL DESCRIPTION

The VT102 emulation is always resident in the PC100's ROM, and can be
used even without working floppy disks.
The VT102 "console" emulator must be completely interrupt driven. The
"terminal" VT102 uses a "background" routine to add the additional
functions of printer port and modem protocols. The VT102 HDX modem
protocols are not supported by the firmware.
The VT102 emulator must operate in two distinct modes. Terminal mode
provides VT102 capabilities. Console mode also has VT102 capabilities with
these exceptions: no printer port, no local echo, and modem protocol
equivalent to full duplex data leads only.

Page 61

PC100 SYSTEM SPECIFICATION
1.2 TRANSMITTED CHARACTERS
The LK201 Keyboard transmits a code for each key that identifies the
physical location of that key on the keyboard. These position codes .are
converted to character codes by means of ROM-resident language tables. The
ROM must be mapped by language to the keyboard (different keycap legends).
Two different types of codes are passed to routines requesting keyboard
data. These types are designated as Levelland Level 2. Level 2 is the
standard 7-bit codes transmitted by a VT102 with the addition of the DEC
STD 169 multi-national character codes being sent in the context of the
current language option.
At Level 2 (terminal mode) all keys not defined
in a normal VT102 send no code and cause the bell to beep.
In console
mode, level 2, the function keys not defined in normal VT102 send escape
sequences (see section 1.2.7).
Level 2 supports all the VT102
key-generated escape sequences (cursor and keypad keys) in the current key
mode context (keypad numeric/application, cursor key normal/application).
In addition, foreign keyboard support includes a correspondence/data
processing mode that allows up to four different character codes per key.
This mode is a Set-up parameter and allows a foreign keyboard user to
access key codes he normally loses because of his special character
requirements.
Level 1 is only available to a sophisticated user in console mode.
This
provides a unique 16-bit ~ode for any key in combination with the CAPS
LOCK, SHIFT, and CONTROL keys with the following exceptions:
Hold Screen - not available
SET-UP
- not available
The keyboard may be broken into several functional key groups. Each has its
own general characteristics.
Note
The following refers to the keyboard layout shown
in the figure at the end of this section.
This
layout differs from a VT102 keyboard.

1.2.1 Un-Seen Fixed Function Keys - HOLD SCREEN, SET-UP
These keys always provide the same function regardless of console
terminal mode and are never provided to any level of output request.

1.2.1.1 Hold Screen
Position G99
Freezes the screen display or
unfreezes it (toggle mode). Any attempt to output any character is blocked
until Hold Screen is "off". May cause an XOFF to be sent in terminal mode
if receive buffer reaches high water mark and auto XON/XOFF is enabled.
This is equal to the NO SCROLL key on a VT102.

Page 62

PC10a SYSTEM SPECIFICATION
Note
If the user does not want blocking, he should test
the state (available in SYSPAR) and put off
"consol-e out" until the user unblocks the display
process by turning the Hold Screen off.
7.2.1.2 Set-up - Position GOl - This causes entry to and exit from Set-Up
mode. A system reset occurs in Set-Up mode when the CONTROL key is pressed
in combination with the Set-Up key.

7.2.2 Fixed Function Keys - Escape, Line Feed, Backspace, Shift, Control,
Tab, Return, Delete
These keys always provide the same function regardless of
terminal mode and are provided to any level of output request.

console

7.2.2.1 ESCAPE - POSTlON Gl1 - Escape at all times generates the ASCII
backspace character code, 1B (hex). It is not affected by SHIFT, CONTROL,
or CAPS LOCK keys.
7.2.2.2 LINE FEED - POSITION G13 - Line feed at all times generates the
ASCII line feed character code, OA (hex). It is not affected by SHIFT,
CONTROL, or CAPS LOCK keys.
7.2.2.3 BACKSPACE - POSITION G12 - Backspace at all times generates the
ASCII backspace character code, 08 (hex). It is not affected by SHIFT,
CONTROL, or CAPS LOCK keys.
7.2.2.4 SHIFT (2 Keys) -POSITION B99, Bl1 - Shift at all levels causes a
modification of the codes being generated by the alpha, numeric, and symbol
keys. For alpha keys it sends the upper case code. The numeric and symbol
keys send the code for the upper character shown on the keycap. If there
are multiple upper and/or lower characters shown on the keycap, then the
upper character/case is sent according to the correspondence/data
processing mode in effect at the time.
7.2.2.5 CONTROL
POSITION C99
Control at all level s causes a
modification of the codes being generated by the alpha keys and some of the
symbol keys and the space bar. Some or the symbol keys are only accessible
with some foreign keyboards by using the data processing mode. The control
codes remain associated with the keycap legend.
If, for example, the alpha
key for C is moved, a <Ctrl/C) stili generates t~e tTX code.
7.2.2.6 LOCK - POSITION COO - Lock at all levels causes selection of upper
case for all alpha keys when "on." "On" state is indicated when the LED
marked "Lock" is lit.
Page 63

PC100 SYSTEM SPECIFICATION
7.2.2.7 TAB
POSITION DOO
Tab at all times generates the ASCII
hori zontal tab code, 09 (hex). It is not affected by SHIFT, CONTROL, or
CAPS LOCK keys (except in SET-UP mode).
7.2.2.8 RETURN - POSITION C13 - Return at all times generates the ASCII
carriage return code,' OD (hex). It is not affected by SHIFT, CONTROL, or
CAPS LOCK keys.
Note
If New-Line mode is selected,
generate a CR LF combination.

this

key

will

7.2.2.9 DELETE - POSITION E13 - Delete at all times generates the ASCII
delete character code, 7F (hex). It is not affected by SHIFT, CONTROL, or
CAPS LOCK keys.

7.2.3 Alpha and Symbol Keys - POSITIONS EOO-E12, D01-D12, C01-C12, BOO-B10
These are the Standard Keys affected by the SHIFT, CONTROL, and CAPS LOCK
keys, as well as the correspondence/data processing mode.
They are mapped
to match the keycap legends according to the language being used.
Note
This requires use of the shift key in add i tion to
the control key for those 'symbols' that generate
control codes. Some foreign language keyboards may
also require use of the 'data processing' keyboard
mode (see SETUP) in order to select the desired
'symbol' •
7.2.4 Keypad Keys - POSITION E20-E23, D20-D23, C20-C23, B20-B22, A21-123
These keys act the same at Level 2 as in a VT102 except for the Enter key
which is not used for print functions.
Either character codes or escape
sequences are generated depending on keypad numeric/application mode and
ANSI/VT52 mode. At Level 1 these keys are considered as function keys, and
control/shift/caps lock flags are included in the 1~-bit code.
7.2.5 Cursor Arrow Keys - POSITION C17, B16-B18
These keys act the same at Level 2 as in a VT102. Escape sequences are
generated depending on cursor key normal/application mode and ANSIIVT52
mode. At Level 1 these keys are considered as function keys and the
control/shift/caps lock flags are included in the 16-bit code.

Page 64

PC100 SYSTEM SPECIFICATION
7.2.6 Special Function Keys - Print Screen. Break
These keys have a defined function in terminal mode and are available in
console mode only at Levell.
7.2.6.1 Print Screen - POSITION GOO - In terminal mode Print Screen causes
the contents of the screen to be sent to the attached printer.
Pressing
<Ctrl/Print Screen) causes the terminal to toggle back and forth between
auto print "on" and "off." This key is used in place of the ENTER key on a
VT 102 for pr inter functions.
In console mode, this key is considered a
function key and is only available at Level 1. The control/shift/caps lock
flags are included in the 16-bit code.
7.2.6.2 Break Key - POSITION G03 - In terminal mode, the Break key acts
just like in a VT102 including Shift-Break for a long break disconnect and
Control-Break for a transmitted answerback message. In console mode, this
key is considered a function key and is only available at Levell. The
control/shift/caps lock flags are included in the 16-bit code.
7.2.7 Function Keys - POSITION G02. G05-G09, G1~-G16. G20-G23. E16-E18. D16-D18, A99 - These keys are only available in console mode at either
Level 1 or Level 2 (as escape sequences).
The control/shift/caps lock
flags are included in the 16-bit level 1 code.
Note
Some of these keys have functions
mode:
Help
- position G15
Next Screen
- position D18
Previous Screen - position D17

Page 65

wi thin Set-Up

PC100 SYSTEM SPECIFICATION

ESCAPE SEQUENCES
'tilde').
Name
FLI
F6
F7
F8
F9
F10
F14
HELP
DO
F17
F18
F19
F2C
FIND
INSERT
REMOVE
SELECT
PREV SCREEN
NEXT SCREEN
COMPOSE

GENRATED

Position
G02
G05
G06
G07
G08
G09
G14.
G15
G16
G20
G21
G22
G23
E16
E17
E18
D16
D17
D18
A99

BY FUNCTION

KEYS

ESC Sequence
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [
ESC [

1 LI 1 7 1 8 1 9 2 o 2 1 2 6 2 8 2 9 3 1 323 3 3 L! 1 2 3 LI 5 -

6 10 -

The keyboard layout of the PC100 is shown below.

Page 66

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characters

are

PC100 SYSTEM SPECIFICATION

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Page 67

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I
:

j---i
I
I
!---!
I
I F19

F18

021

G22

1---1
I
I

1: _023
_ _ 1I

'_I

1 F17'

020

WAIT

F20

PC100 SYSTEM SPECIFICATION
7.3

RECEIVED CHARACTER PROCESSING

7.3.1

Received Character

Processing

VT102 emulation responds to different characters and control sequences so
as to duplicate the response of the VT102. The full description is found in
section 8 (Terminal Control Functions) of the VT102 Engineering
Specification. A summary follows.
Reception of '8-bit control codes cause the same effect
character 7-bit escape-FE equivalent had been received.

the

Note
Reception of the 'RESET TO INITIAL STATE' escape
sequence (ESC c) will also reset the 7201 serial
line controller effectively disabling its interrupt
structure. This escape sequence should not be used
from within an application without restoring the
interrupt structure.
Normally, the operating
system is in control of the interrupts of the 7201
and an application will not know how to restructure
the interrupts.
Note
Some operational capabil i ties are common to both
terminal and console modes; others are not. These
are noted below in the following format:
1.

Those common to both are marked BOTH.

Differences are marked as either TERMINAL or CONSOLE.

7.3.2 ANSII Mode Control Functions
BOTH

These functions give the terminal its intelligence.
this group include:

Examples in

Cursor functions (Movement, positioning, position reporting,
etc.)

Mode setting and resetting

Line and character
character, etc.)

Terminal
etc.)

editing

modes

(Insert

Page 68

(Blink

and

delete

character,
line

and

underline
character,

PC100 SYSTEM SPECIFICATION
5.

Terminal identify, test, and status

Terminal characteristics
mode, etc.)

(Key autorepeat,

linefeed/newline

CONSOLE MODE No local echo, modem, or printer functions in "console" mode.

7.3.3 Operational Variations
Some of the sequences listed in the previous section affect the terminal's
operational mode. Examples include VT52 or ANSI mode, smooth or jump scroll
and the like.
The escape sequence which normally causes a VT102 to execute self-tests are
ignored and the status report always returns a "no problem" status.

7.3.4 Terminal Reports
BOTH

The host computer tells the VT102 emulator to report its
current cursor position, status, and device attributes.

TERMINAL MODE Printer status reports occur only in Terminal Mode.

7.3.5 Terminal Reset
BOTH

7.4

The terminal also responds to a command from the computer
which causes it to reset to its saved state. This is not
the same as a keyboard entered system reset which returns
to the opening menu.
This recalls the NVM set-ups,
clears the screen, and homes the cursor only.

VT102 CONTROL OF ATTACHED DEVICES
TERMINAL MODE VT 102 emulation firmware has the same control over the
printer and EIA modem as the VT102.
CONSOLE MODE

VT 102 emulation firmware does not have control over the
printer and comm ports or EIA modem lines.

Page 69

PC100 SYSTEM SPECIFICATION
7.4.1 Modem Control
TERMINAL MODE Terminal Mode has full duplex capabilites:
1. Data leads only
2. Full modem
3. Asymmetrical (require special cable)
Terminal Mode does not have half duplex capabilites:
CONSOLE MODE

In console mode the "appl ication" must control the comm
port hardware directly.

7.4.2 Printer Control
BOTH

The baud rates available for the printer port are more
limited than VT102 baud rates. The available baud rates
are: 75, 150, 300, 600, 1200, 2400, 4800, 9600.

TERMINAL MODE VT102 firmware contains code to control a seriallyconnected printer in this mode only. The emulation
supports the print screen and print cursor line commands,
auto print mode, and printer control mode.
CONSOLE MODE

In Console Mode tbe printer is only accessible to an
"application" through direct control of the hardware.

7.5 OTHER DIFFERENCES - TERMINAL VS CONSOLE MODES
TERMINAL MODE This mode emulates a VT102, where keyboard characters g 0
to the communication line, and communication line
characters go to the display, plus all the printer
support and Set-Up and modem control, etc.
Differences from a real VT102 are due to differences in
the keyboard (keys in different places), different
numbers of and different labels for LEOs and more
ext ens i v e Se t - Up in for mat ion r e qui red ( 0 p t ion I D's,
volumes of bell and click, etc.). Also, no support of HDX
modem protocols is provided.
CONSOLE MODE

This mode acts like a VT102 console (without modem
control, local echo, or printer port) to an application,
wbere keyboard characters go to the a p p 1 i c a t ion ,
application characters go to the display, and the printer
is under control of the application;
the communication
port is under control of the application. However, the
VT 102 can still be put into Set-Up mode anCi have its
characteristics changed like a real console.
Page 70

PC100 SYSTEM SPECIFICATION
Because there is no XON/XOFF between the "console VT102"
and an application, both are running on the same CPU
and/or in a single threaded environment. As a result the
service routine hangs waiting for buffer space to. become
available (emptied by interrupt process) before returning
to the calling routine.
There are two access methods:
1.

The "aplJlication" accesses the VT102 "console" through the
interface as though it were a serial line controller communicating
over a high speed communications line.

A "sophisticated application" may access the video display RAM
through indirect write of the display/attribute memory.
This
bypasses normal VT102 rcvd char processing. A "sophisticated user"
also obtains "raw" key data to bypass escape sequence encoding and
decoding needs.
Note
Level 1 and Level 2 character-available
status are not interchangeable; a Level 2
character-available does not imply a
Level 1 character-available.

Within the VT102 emulation there are routines to pass status and data
from/ to the inter face layer. Wi thin the VT 102 emulation, interrupts must
not be disabled any longer than 450 microseconds.
This requires cautions
on re-entrancy of routines that are shared and potential problems of not
completing an interrupt handler that re-enables interrupts and then does
not complete before it is called again.
DATA FLOW DIAGRAMS FOR THE DIFFERENT MODES OF OPERATION

PRINTER

1 'TERMINAL' mode
1<--------------all print
1
functions

bell

KEYBOARD

APPLICATION

1<--------------------------------------1 DISPLAY
1-------------------------------------->1----------------I

SET-UP PROCESS

Figure 1. "Terminal" Mode "Off-Line"
Page 71

COMM

PC100 SYSTEM SPECIFICATION

PRINTER

bell

KEYBOARD

l<--------------------------------------l
l---------------l
l-------------->l

---------~-------

DISPLAY

APPLICATION

CONM

SET-UP PROCESS

Figure 2. "Terminal" Or "Console" Mode "Set-up"

PRINTER

bell

KEYBOARD

l<--------------------------------------l
local
l
l---------------------->:

-----------------

l echo

DISPLAY

----------------A

APPLICATION

SET-UP PROCESS

COMM

Figure 3. "Terminal" Mode "On Line" No Printer Functions

Page 72

PC100 SYSTEM SPECIFICATION

:<-----------------------------if operator selects print

PRINTER

screen, it takes precedence:

:<---------------bell
KEYBOARD

::<--------------------------------:
local:

DISPLAY
------>;
: echo -----------------

;--------------------------------

V
I

APPLICATION

COMM

: SET-UP PROCESS

Figure 4. "Terminal" Mode "On Line In "Printer Controller

PRINTER

:<--------------I

bell

:<--------------------------------------:
:------------X blocked

KEYBOARD

DISPLAY

blocked

APPLICATION

SET-UP PROCESS

CONM

Figure 5. Terminal Mode On Line Printing From Screen

Page 73

PC100 SYSTEM SPECIFICATION

PRINTER
A
I

bell

:<---------:----------------------------1

KEYBOARD

DISPLAY

------->1

APPLICATION

SET-UP PROCESS

COMM

Figure 6. Console Mode

8.0

EXTERNAL INTERACTIONS AND IMPACT

8.1

OPERATING SYSTEM

"T 102 emUlation allows access to its subroutines by the operating system.
It does not require operating system services and runs without the use of
disks.

8.2 STACK OVERHEAD
Hardware interrupts and the attendant interrupt handlers impose a stack
overhead on any program running at the time of the interrupt.
The
interrupt handlers swap to their own stack as soon as possible to minimize
this overhead. However, it still requires three words due to the interrupt
process itself (CS, IP, FLAGS) and the firmware pushes three more words
before it swaps to its own stack.
So f twa r e i n t err up t s don 0 t s wa pst a c k s • and the use r mu s t pro v ide
sufficient stack space (plus hardware interrupt overhead). The amount of
stack required is 25 words (plus hardware, total = 31).
Page 74

PC100 SYSTEM SPECIFICATION
8.3 STACK USE BY APPLICATIONS
The firmware hardware interrupt handlers swap stacks, if required, so they
always run on their own stack.
Some of the handlers re-enable interrupts
after this swap, but while still wi thin the interrupt handler, so other
high priority interrupts are not held up.
At the conclusion of the
original firmware interrupt handler, the stacks are swapped back to the
original.
There is a caution for "application" interrupt handlers that
expect to use the stack or registers to pass data between their interrupt
handler and the main-line program.
If the application interrupt occurs
while still within the firmware interrupt handler, then current stack and
registers will not be preserved for main-line use.
Application interrupt
handlers must never use registers to pass data and must guarantee their own
private stack if they are going to pass data on a stack.

Page 75

PC100 SYSTEM SPECIFICATION
9.0 VT102

9.1

SET-UP

The non-volatile Set-Up parameters are different from those in the VT102
due to hardware differences and system requirements.
The non-volatile Set-Up parameters that are the same as the VT102 are:
Minor Field

Major Field

Default

on line/local mode
80/132 column mode
tab stop bit map
scroll - SMOOTH/JUMP
auto repeat - ON/OFF
screen background - LIGHT/DARK
cursor - UNDERLINE/BLOCK
margin bell - ON/OFF
keyclick - ON/OFF
ANSI/VT52
* auto xon/xoff - ON/OFF
US/UK char set
auto wrap - ON/OFF
line feed/new line
* local echo - ON/OFF
* print termination
char - none/FF
* print extent - ALL
SCREEN/SCROLLING REGION
comm stop bits - 1/2
* rcv parity check - ON/OFF
* break enabled - ON/OFF
* disconnect char enable-ON/OFF
* disconnect delay- 60 MS/2 SEC
* auto answerback enabled
- ON/OFF
50/60 hz
comm data/parity bits
comm xmit rate
comm rcv rate
* comm modem line discipline
* disconnect char
answerback message - UP TO 20
CHAR (PLUS 2 DELIMITERS)
printer data/parity bits
printer xmit/rcv rate

header
parameter
TABs
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter

on line
80
every e positions
smooth
on
dark
block
off
on
ANSI
on
US
off
LF
off

parameter

parameter
parameter
parameter
parameter
parameter
parameter

all
1

on
on
off
2 sec

parameter
parameter
modem
modem
modem
modem
modem

off
60
7S

answerback
printer
printer

none
8N

9600
9600

FDXA
none

4800

Insertion/replacement mode is always saved as replacement mode.

Page 76

PC100 SYSTEM SPECIFICATION
VT102 non-volatile parameters not included in the emulator are:
NO SOFTWARE CONTROL
NO KEYBOARD VARIATION .FOR
THIS

screen brightness WPS keyboard HDX protocol related parameters

New non-volatile parameters to be added in emulator are:
bell volume
misc
keycl ick vol ume
misc
options memory installed
option RAM
- AUTOMATIC SCREEN BLANKING
parameter
AFTER ELAPSED TIME - on/off
scroll rate for smooth scroll
- 3,6,12 LINES/SEC AT 60HZ
(slower at 50HZ)
misc
- KEYBOARD KEY ASSIGNMENTS (for
foreign language keyboard
support)
parameter
correspondence/data processing
LEGEND:

7(max)
7(max)
none
on
6

correspondence

* only apply in terminal mode

9.1.1 Set-Up DIsplay and Operation
The Set-Up displays consist of two major screen areas.
One is fixed and
the other variable is a function of what part of Set-Up is used. The fixed
part of the display, called the header, consists of the words shown in
Figure 7.
Beneath the header is the variable area which is one of eight different
displays called "major fields."
On entering the Set-Up mode, the tab
settings major field is automatically displayed.
There are two types of
major fields.
One type is accessed by stepping through them sequentiall y
by means of the Next Screen and Previous Screen keys.
The other type is
entered directly at any time (almost) by means of the Help key (help field)
and shifted A (answerback field).
wi thin some of the major fields are
variable numbers of minor fields, one for each parameter selectable within
that major field. Minor fields are stepped through by means of the left and
right arrow keys.

Page 17

PC100 SYSTEM SPECIFICATION

SSS

EEE

TTTTT

S
S

EEE

SSS

XXX

u u PPP
u U P P
u U PPP
u U P
u u P

TO EXIT PRESS "SET-UP"
PRESS "HELP"
TO RESET TYPE <CTRL/SET-UP>
VERSION 01.01.01 A
: ON LINE (or LOCAL) :
A

reverse video
Figure 7. Set-up Mode Header Display
Except for 'HELP' and
the same effect:
SET-UP
CTRL-SET-UP
HELP
NEXT SCREEN
PREV SCREEN
UPPER/LOWER CASE L
UP-ARROW
DOWN-ARROw
SHIFT-S
SHIFT-D
SHIFT-R
SHIFT-A

'ANSWERBACK' fields, the following keys always have
exit set-up mode
reset system
enter/exit help field
select next major field
select preceeding major field
toggle line/local state
select next higher value
select next lower value
save current set-ups in NVM
set current set-ups to defaults
(does not save)
recall saved set-ups from NVM
enter answerback field

9.1.1.1 Help Field - The Help field is displayed by pressing the Help key.
It is entered at any time except when already in the answerback field. It
presents a short list of how to access the major sequential fields, minor
fields, and how to change values. The only key honored while in "Help" is
the Help key which causes an exit to the field displayed before entry to
"Hel p."
Page 78

PC100 SYSTEM SPECIFICATION
9.1.1.2 Answerback Field - The answerback field is displayed at any time by
pressing the SHIFT and A keys simultaneously. The major field heading
ANSWERBACK is displayed and beneath it "A :". The first character typed
(and displayed) is a delimiter. Up to 20 characters can be entered
following the delimiter. The string automatically terminates after the 20
characters or before that when a second delimiter entry is made. Any
character can be entered in the answerback string, including NULL, DELETE,
or CTRL characters. Normally non-printing control characters show as their
related ASCII characters in reverse video. For example, ETX (control C)
shows up as a reverse video C. Answerback is exited by typing the delimiter
character a second time or by reaching the 20 character entry limit.
String entry errors can only be fixed by exiting answerback and re-entering
to make a new string. The string is eliminated by making the first two
characters the same (two delimiters with nothing between).
9.1.1.3 Tab Settings Field - The tab setting field is displayed on entry
to Set-Up. It consists of a row of numbers running repetitively from 1
through 0 with alternate groups of 10 shown in reverse video.
The line
above this row of numbers contains a variable number of the letter "T." The
location of the T symbol signifies that a tab stop is set at that point.
There are 80 or 132 possible tab stops depending on the screen width
setting in effect. A cursor shows the current active position. This cursor
moves by means of the left and right arrow keys, Return, Tab (to next "Ti'
location), and the space bar(acts the same as right arrow). The "T" key (or
Up or Down arrow keys) reverses the tab setting at the active position. In
addition, Ctrl Tab clears all tab stops and SHIFT TAb sets the default tab
stops at every 8th position.
Beginning with the 9th position, a Tis
displayed.
9.1.1.4 Parameter Major Field - The parameter major field displays all the
Set-Up parameters that have only two possible values (usually on/off). The
parameters are shown as a row of l's and D's with alternate groups of four
shown in reverse video. The current active parameter is shown by a cursor.
This cursor moves left and right by means of the left and right arrow keys,
Return (to start of line), Tab, and space bar (acts the same as right
arrow). As the cursor moves to a new position, a field is displayed below
the line that details the name of the parameter and what the 1 and 0 values
mean.
The 1 and a values are changed by means of the up and down arrow
keys. Some of these parameters have an immediate affect if changed. Others
do not take affect until exiting from Set-Up mode.
Changing to either 80
or 132 columns destroys the user's text display (normally it is preserved
during Set-Up and restored on exit).

Page 79

PC100 SYSTEM SPECIFICATION
9.1.1.5 Modem Field - The modem field displays the parameters for the modem
port (communications port). Some of these are only applicable in "terminal"
mode. Each parameter has a range of possible values, and the field is shown
as a list on the display (Figure 8).
The active parameter is shown by a
reverse video field.
.

MODEM

DATA/PARITY

' __ >: 9600:

XMIT BAUD

9600

Rev BAUD

FDXA

PROTOCOL

--------------- reverse video

Figure 8. Modem Major Field Display
The value of the active parameter changes by means of the up and down arrow
keys which cause the parameter to step through its allowable values.
The
active parameter selection changes by means of the left and right arrow
keys.
9.1.1.6 Printer Field - The printer field displays the parameters for the
printer port. The active parameter selection and value changes are the same
as for the modem.
9.1.1.1 Miscellaneous Field - The miscellaneous field is used to select the
bell and key click volumes and the smooth scroll rate. The active parameter
selection and value changes are the same as for the modem.
9.1.1.8 Memory Size Field - The memory size field identifies the presence
and size of the memory extension option so it is included in the selftesting procedure.
It only contains a single parameter and the value is
stepped through by means of the up and down arrow keys.

Page 80

PC100 SYSTEM SPECIFICATION
Storing the Set-Ups - The current contents of all the
Set-Up
9.1.1.9
fields, including any answerback message, are transferred to non-volatile
storage by pressing the SHIFT and "S" keys simultaneously (not while in
HELP or ANSWERBACK).
Note
Insertion/replacement mode is always
replacement mode before saving is done.

set

9.1.1.10
Using Default Set-Ups - All the Set-Up fields are set to their
respective default conditions by pressing the SHIFT and "D" keys
simultaneously (not while in HELP or ANSWERBACK).
Defaults are listed in
section 9.1.
Note
This does not enter the defaults into non-volatile
storage (must use "store"), but it causes the
user's text to be erased from the screen and causes
a line disconnect in "terminal" mode.
9.1.1.11 Recalling Stored Parameters
The parameters stored in nonvolatile storage are recalled for use by pressing the SHIFT and "H" keys
simultaneously. This also causes the user's text to be erased from the
screen and causes a line disconnect in "terminal" mode.
Stored parameters
are also automatically recalled at power-up, system reset, and reception of
the RIS escape sequence (ESC c).
RIS will also do a channel reset of the
7201 printer and communications ports, destroying the mode and interrupt
structures in use at the time.
9.2 RESET TECHNIQUE
Wi thin Set-Up mode, a "reset" key combination (CONTROL SET-UP) causes a
jump to the start of the sel f -test at a point which allows it to be
distinguished from a power-up.

10.0 INTERFACE LAYER
Functions provided by the
sophisticated applications.

firmware

for

use

operating

systems

and

10.1 SOFTWARE INTERRUPT TYPE 40 (DECIMAL)
Function code is passed in DI. It is organized as 16 even number values for
ease in using as table offsets to dispatch to serv ice routines. Refer to
Table 3.

Page 81

PC100 SYSTEM SPECIFICATION
Table 3. Function Codes
Hex

Function

CONSOLE OUT
CONSOLE IN
CONSOLE IN STATUS
LEVEL 1 (16-BIT) CONSOLE IN
DISABLE CURSOR
ENABLE CURSOR
INITIALIZE INTERRUPT VECTORS
RETURN CLOCK RATE
SET LEDs ON KEYBOARD
CLEAR LEOs ON KEYBOARD
SEND DATA TO SCREEN
INIT 7201 TO NVM pARAMETERS
RAw KEYBOARD DATA
RESERVED
RESERVED
RESERVED

2
4
6
8
A
C
E
10

12
14
16
18
1A
1C
1£

Note
Only registers CS: , SS: , and DS: are preserved.

10.1.1

Console Out

ENTRY

01 = 0
AL = character in ASCII (includes 8-bit multinational characters)

10.1.2

Level 2 Console In

ENTRY

DI = 2

EXIT

AL = Level 2 keyboard character if available
CL = returned status
o = no character available
FF = character is in AL

Page 82

PC100 SYSTEM SPECIFICATION
10.1.3

Level 2 Console In Status

ENTRY

EXIT

=4
CL = returned status
o = no character available
FF = character is available
Cannot be used to
character available.

Note
detect

10.1.4

Levell Console In

ENTRY

=6
AX = Level 1 character
CL = returned status
o = no character available
1 = no character available

EXIT

status

Level

due to Level 2 sequence not
com p let e d ( pre v i 0 u s key c a use d a s t r in g 0 f Le vel 2
characters to be generated.
Level 2 buffer has not been
emptied of this string yet.)
FF = character is in AX

RULES FOR LEVEL 1 CHARACTERS
AH

AL
9

11 10
I

8
I

______ I~I~I~I~I---------------I

I
I

FUNCTION KEY FLAG 1 = This is a function key.

= Shift key in effect.
CONTROL FLAG
= Control key in effect.
CAPS LOCK FLAG
= Caps Lock key in effect.

SHIFT FLAG

For non-function keys, the AL = character (incl uding 8-bi t multinational
characters).
The effect of shift/control/caps lock is already taken into
account.

Page 83

PC100 SYSTEM SPECIFICATION
For function keys, the AH = flag data and AL = function key code (ASCII) as
follows:
KEY CODE HEX
0
1
2
3
5
7
9
B
D

F
11
13
15
17
19
18
1D
1F
21
23
25
27
29
28
2D
2F
32
35
38
3B
3E
41
44
47
4A
4D
50
53
56
59
5C
5F
62
65

KEY
HELP
DO
COMPOSE
PRINT SCREEN
F4
F6
F7
F8
F9
F10
F14
F17
F18
F19
F20
FIND
INSERT
REMOVE
SELECT
PREV SCREEN
NEXT SCREEN
UP-ARROW
DOWN-ARROW
RIGHT-ARROW
LEFT-ARROW
KEYPAD 0
KEYPAD 1
KEYPAD 2
KEYPAD 3
KEYPAD 4
KEYPAD 5
KEYPAD 6
KEYPAD 7
KEYPAD 8
KEYPAD 9
KEYPAD DASH
KEYPAD COMMA
KEYPAD PERIOD
KEYPAD ENTER
KEYPAD PF1
KEYPAD PF2
KEYPAD PF3
KEYPAD PF4
BREAK

Page 84

PC100 SYSTEM SPECIFICATION
10.1.5

Disable Cursor

ENTRY

EXIT

There is no cursor affect on attributes at cursor position.
cursor does not show on the screen.

=8
The

Note
The disable and enable cursor functions are only to
be used immediately preceeding and following a
function 14 that may attempt to set the attributes
at the current cursor position.
They cannot be
used to make the cursor "invisble" while it is
moved around by other escape sequences or control
characters. These functions must be used in pairs;
first disable, then enable.

10.1.6

Enable Cursor

ENTRY

EXIT

Cursor does affect attributes at cursor position.
on the display.

10.1.7

Initialize Interrupt Vectors

ENTRY

EXIT

The following interrupt types are modified for use by the firmware:

=A
The cursor shows

NMI for RAM option parity error
vertical frequency refresh
graphics controller option
DMA controller of extended comms option
7201 of extended comms option
keyboard 8251
44.
time tick
In add i tion, the extended comms option and graphics option are reset to the
disabled state.
Type 2

32.
34.
35.
37.
38.

The extended comms option is reset by writing anything to 8088 port 27 hex.
The graphics option is reset by toggling bit 0 of 8088 port 50 hex from
high to low to high.

Page 85

PC100 SYSTEM SPECIFICATION
10.1.8

Return Clock Rate

ENTRY

=E
AL = clock rate
bit 0

EXIT

10.1.9

60 Hz
50 Hz

= 01
=

Set Keyboard LEOs

Set and clear LEOs are onl y for the ind icators.
They do not cause any
action that may be implied by the label of the LED being affected.
Firmware normally maintains all but the "compose" LED in the proper state.
ENTRY

= 10

AL = bit pattern of LEDs to turn on
bit set to 1 = LED on

65432

I
I

~---~-:'"li"-"-"

I
1

1
1 _ _ __

WAIT
CO~lPOSE

CAPS LOCK
HOLD
MUST BE 1
EXIT

LEDs as requested

Page 86

PC100 SYSTEM SPECIFICATION
10.1.10

Clear Keyboard LEDs

ENTRY

DI = 12
AL = bit pattern of LEDs to turn off
bit set to 1 = LED off
6

2
I

-------I

I
t1

1
1I _ __

WAIT

COMPOSE
CAPS LOCK
HOLD
MUST BE 1
EXIT

LEOS as requested.

10.1.11

Send Data To Screen

ENTRY

DI = 14
AX = TRANSFER TYPE
o = CHARACTERS AND ATTRIBUTES
1 = ATTRIBUTES ONLY
2 = CHARACTERS ONLY
3 - FFFF = UNDEFINED
BX = START LOCATION IN DISPLAY
BL = LINE NUMBER (1-24)
BH = COLUMN NUMBER (1-132)
Note
max column number is a function of screen width

(80,132) and line width (single,double)

CX = NUMBER OF CHARACTERS/ATTRIB TO TRANSFER, IN BYTES
Note
User is responsible for limiting size of transfer
so end-of-line is not exceeded.
OX = OFF EST TO START OF ATTRIBUTES RELATIVE TO USERS OS:
Page 87

PC100 SYSTEM SPECIFICATION

= OFFSET TO START OF CHARACTERS RELATIVE TO USERS DS:
BP = CHARACTER/ATTR1B SEGMENT COpy OF USERS DS: USED FOR OFFSETS

PASSED

IN DX AND SI.

Note
Characters and
value of DS.

10.1.12

a~tributes

must be relative to same

INIT 7201 TO NVM PARAMETERS

NVM refers to current contents of the shadow RAM which are displayed in
SET-UP.
These are not necessarily the same as the currently saved SET-UP
parameters.
ENTRY

= 16

FUNCTION
1.

2.
3.
4.

5.
6.

Does a channel reset on both channels A and B
Sets baud rates for modem and printer ports according to NVM
Loads 10 (hex) into write register 2A, and 0 into write register 2B
Loads write registers 4A,B with X16 clock, parity/stop bits
according to NVM for the port
Loads write registers 3A,B with number of receive data bits
according to NVM for the port and enables receive
Loads write registers 5A,B with number of transmit data bits
according to NVM for the port and enable transmit
Note
When data/parity is 7M or 7S, the 7201 is actually
set for eight data bits, no parity.

Page 88

PC100 SYSTEM SPECIFICATION
10.1.13 Raw Keyboard Data
ENTRY

DI = 18

This function is provided for diagnostics to test the keyboard and is only
intended for that purpose. It is documented here for completeness.
Note
The SHIFT, CAPS LOCK, and CONTROL keys can only be
read in conjunction with another key by looking at
the flag bits in AH. The SET-UP will not be
detectable by a program, but an operator will see
entry into set-up mode on the display. The HOLD
SCREEN key will not be detectable by a program, but
an operator will see the "HOLD SCREEN" LED on the
keyboard light up.
EXIT

CL = 0 no key available
= 1 key available
AL = key location matrix code as defined in LK201 Keyboard
specification
AH = flag bits as for function 6, level 1 console in.

11.0

IMAGE OF Z80 RAM SPACE TO BE LOADED

Any routines that must be loaded into the Z80 s~ace for it to run
initially must be put there by the 8088. The ROM must contain this
code because it cannot be obtained from the floppy disk until after
the floppy handler is loaded into the Z80 and the interface to access
the loader is also in place. This initial code must know how to take
care of the "flipped" Z80 RAM addresses and relocate routines in the
proper locations in RAM.

12.0 BOOT LOADER TO READ TRACK 0, SECTOR 1 OF FLOPPY
The purpose of the boot loader is to get into memory a minimal routine
which initiates the loading of the overall operating system. The boot
loader accesses any available drive as selected by the operator. If
an error occurs, an error message is displayed and the opening menu is
re-displayed.
The boot loader loads 512 bytes from the specified drive, track 0,
sector 1 into the shared RAM beginning at address 1000 (hex) and jumps to
it. If the loaded routine returns an error, the opening menu is
re-displayed. The selected drive is available by examining the register
which did the selectio~. The loaded data must be Z80 instructions.

Page 89

PC100 SYSTEM SPECIFICATION
12.1 BOOT PROCESS
The boot process consists of the following steps:
1.
2.

Operator selects the drive to boot from by means of the menu.
The 8088 passes control to the zao routine. The routine attempts
to read track 0, sector 1 of the selected drive into address 1000
(hex) •

While the Z80 is attempting to read, the 80a8 counts time
monitors a semaphore location at O:FFF (initially set to 0).

If the semaphore does not change from a within approximately 10
seconds, there is some sort of major problem.
The Zao is stopped
and the message FAILURE, Zao RESPONSE, CONSULT YOUR USER'S GUIDE is
displayed along with the opening menu. The operator may then make a
selection from the menu.

If the Z80 routine detects a "drive not ready" condition, it
returns a value of 6 in the semaphore location. The a088 displays
the message 'Failure, drive not ready, consult yo~r user guide' and
redisplays the opening menu. A 'drive not ready' is caused when
either a drive door is opened, no disk is in the drive, or when
there is no drive in the system.

If the Z80 detects an error read ing track 0, sector 1 of the
selected drive due to a seek or CRC error, it retries up to two
more times. If all three attempts fail, the Zao returns the value 2
in the semaphore location. The 8088 displays the message "Failure,
boot loader, consul t your user guide" and re-displays the opening
menu.

If the Z80 successfully reads track C, sector 1 of the selected
drive, it checks the contents of address 1000 (hex).
If this is
not the Z80 code for disable interrupts (F3), the Z80 returns the
value 4 in the semaphore location. The 8088 displays the message
'Failure, non-system disk, consult your user guide' and redisplays
the opening menu.

and

Note
This requires the Z80 code resident in
sector 1 to begin with a 01 instruction.
1.

track

If the Z80 successfully reads track 0, sector 1 of the selected
drive into address 1000 (hex), and the first byte is the 01
instruction, control transfers to this secondary boot by
jumping to address 1000 (hex).
Note
The secondary boot is Zao code.

Page 90

PC100 SYSTEM SPECIFICATION
2.

The secondary boot is responsible for loading the remainder of
the system.

If the loading process fails, control returns to the 8088 by
placing the value 8 in the semaphore location. The 8088
displays the message "Failure, system loader, consult your user
guide', halts the Z80, reloads the boot reading routine, and
re-displays the opening menu.

When the loading process completes successfully, control passes
to the 8088 by placing the value A (hex) in the semaphore
location. The 8088 passes control to the loaded system by doing
an indirect, intersegment, far jump via O:FFB.
Note
The contents of four bytes, starting at O:FFB, must
be pre-loaded with the code segment and an offset
of the 8088 (system) start address:

FFB, FFC contain IP
FFD, FFE contain CS
Note
The selected drive is determined by reading the Z80
port ~O (hex), mask to read bits 0 and 1, and the
drive selected is:
Drive
A

B
C

Bit

Bit 0

o
o

When the menu choice is made, the screen is blanked by means of
a hardware gate.
This leaves the menu image still in display
RAM, it just does not show. The loaded program should send
escape str ings to erase the screen and home the cursor, then
unblank the display by writing an 83 (hex)to 8088 port OA
(hex). This port should not be written to at any other time as
it contains other bits which could cause major problems if they
do not agree with an internally maintained copy of the port.
The firmware properly maintains this port at all other times
for NVM and ZeD control.

Page 91

PC100 SYSTEM SPECIFICATION
13.0 MENU SELECTION PROCESS
After initialization and self-test (or reset), the operator is presented
with a choice of things to do.
1.

VT102 terminal mode - system looks like a VT102 to a host connected
to the communications port

Boot operating system - read in and start the operating system,
drive is selectable

Run more extensive self-tests

14.0 SYSTEM PARAMETER INFORMATION
This is a word of data which maintains bit flags which define the system
state. It is used mainly by the firmware, but is defined here for use by
special routines (e.g. 3277 emulator) that need to know about these
parameters in order to avoid problems.
Location Mnemonic - Syspar
Address - EFOO:FFE
Bit Assignments
Bit 0 - emulator mode flag
0 = console mode
1 = terminal mode
Bit 1
0

Line flag
-= OnOn/Off
Line

1 = Off Line, Local

Bit 2 - Set-up mode flag
0 = normal
1 = in Set-Up
Bit 3

- Hold Screen mode flag

Bit 11

Scroll in process flag
-= normal

a = normal
1 = Hold Screen in effect
0

1 = smooth scroll in process
Bits 5-1 reserved
Bit 8 - bundle card option present flag
o = option present
1 = option not present

Page 92

PC100 SYSTEM SPECIFICATION
Bit 9 - floppy controller board present flag
o = floppy present
1 = floppy not present
Bit 10 - graphics option present flag
o = graphics option present
1 = graphics option not present
Bit 11 - memory option present flag
o = memory option present
1 = memory option not present
Bits 12 - 15 reserved

15.0

POWER SUPPLY

15.1

POWER CONNECTOR

The power connector on the mother board is a 13-pin in-line connector
with the following pinout:
1

ACOK

This signal indicates the presence or absence of valid ac
power entering the power supply. When valid ac power is
present, this signal will be high (open circuit) and when the
ac power is lower than the required minimum input voltage,
this signal will be low (short circuit to logic ground).
Low State (ac power invalid): The voltage level of this
signal is 0.45 volts maximum when sinking 2.0 milliamperes.
High State (ac po,wer valid): The voltage on this signal is
pulled-up by external circuitry. When pulled up to 10.0
volts, the leakage current to logic ground shall be 25
microamperes maximum at the maximum external pull-up voltage
of 10.0 volts.
Transi tion Times: The rise time (1 O~ to 90~) and fall time
(90% to 10%) shall be 1.0 microsecond maximum.

VBIAS

When the ac input power is within its valid range, this
source has an open circuit voltage of 12.0 volts + 10i and a
source impedance of 410 ohms + 10%. This signal is used for
manufacturing to automate test monitoring via connecting the
LED write signal through a jumper to this pin.
Power-Up: During power-up of the power supply, this source
has an open circuit voltage of 8.0 volts minimum at the time
when the dc output voltages start to increase from zero
volts.
Page 93

PC100 SYSTEM SPECIFICATION
Power Down: During power-down of the power supply, the
vol tage on this source decreases toward zero. Due to output
loading variations, there is no definable relationship
between the decay of this output and the decay of the dc
output voltages.

Key

This pin must be missing from the mother board.

-12V OUT

Maximum Current -12 VDC 0.0 amperes minimum to 0.35 amperes
maximum
Output Voltage Variations:
Total Tolerance
+ 7%
Initial Tolerance
+ 3%
Line Regulation
+ 1.5%
Load Regulation
+ !!. 0%
5.1 Volt Load Interaction + 3.0%
Temperature Stability
+ 0.05$/C degrees
Long Term Stability
+ 1$/1000 hrs
Ripple and Noise
120 millivolts, peak to peak
Overcurrent Trip Point
Minimum
O.!! ampere
Maximum
1.5 ampere
Short Circuit Current
0.5 ampere, maximum
Overvoltage Protection
Range,Minimum Trip Point -13.0 Volts
Absolute Maximum Output
-15.0 Volts

5,6 +12.1V OUT

Maximum Current
+12 VDC 0.6 ampere minimum to 6.7 amperes maximum
Output Voltage Variations
Total Tolerance
+ 5~
Initial Tolerance
+ 2$
Line Regulation
+ 3%
Load Regulation
+ 3%
5.1 Volt Load Interaction + 3%
Temperature Stability
+ 0.05%/C degrees
Long Term Stability
+ 1%/1000 hrs
Ripple and Noise
75 millivolts, peak to peak
Overcurrent Tr ip Point
Minimum: 6.8 amperes
Maximum: 8.0 amperes
Short Circuit Current
5.2 amperes (Maximum)
Overvoltage Protection Range: not applicable

7,8,9 +5 .. 1 V OUT

Maximum Current: +5 Vdc amperes minimum to 10.5 amperes
maximum
Output Voltage Variations:
Total Tolerance
+ 5%
Initial Tolerance
+ 2%
Line Regulation
+ 1%
Load Regulation
+ 3%
12.1 Volt Load Interaction + 3%
+ 0.05%/C degrees
Temperature Stability
Long Term Stability
+ a/1000 h
Ripple and Noise
50 millivolts, peak to peak
Page 94

PC100 SYSTEM SPECIFICATION
7,8,9 +5.1 V OUT
(continued)

Overcurrent. Trip Point, minimum: 10.7 amperes
maximum: 12.6 amperes
Short Circuit Current:
8.2 amperes, maximum
Overvoltage Protection Range,
Minimum trip point: 5.80 volts
Absolute maximum output: Volt.age 7.0 volts

10,11,
12,13

DC Power Return

16.0

CONNECTOR OUTPUTS

16.1

VIDEO INTERFACE CONNECTOR

Signal Ground

This connector is a 15-pin D-type female connector supplying interface
signals and power to the PC100 monitor and keyboard with the following
pinout:
Pin

Name

1
2
3
4
5,6
7,8
10
11
12

Red Shield
Green Shield
Blue Shield
Mono Shield
GND
+12V
Blue
Green
Red
Mono video

13
14
15

Not used
KBD r:v data
KBD TX data

Description
Ground connector for red gun shield
Ground connector for green gun shield
Ground connector for blue gun shield
Ground connector for B/w video gun shield
+12V returns
+12V DC to monitor and keyboard
RS170 "like" composite red gun output
RS170 "like" composite green gun output
RS170 "like" composite blue gun output
RS170 "like" composite B/W video output/green
drive signal for applications color monitor
RS423 serial data from keyboard
RS423 serial data to keyboard

16.2 COMMUNICATIONS INTERFACE CONNECTOR
Pin Number
1
2
3
4
5
6
7
8
9

Signal Description

Mnemonic Direction

Protective Ground
Tran smi t Data
Receive Data
Request To Send
Clear To Send
Data Set Ready
Signal Ground
Receive Line Signal Det.
Not Used
Not. Used

PROT GND
XMIT DATA
REC DATA
RTS
CTS
DSR
GND
RLSD
N/U
N/U

Page 95

PC100 SYSTEM SPECIFICATION
16.2 COMMUNICATIONS INTERFACE CONNECTOR (Continued)
Pin Number
11
12
13
14
15
16
17
18
19
20
21
22
23
211
25

Signal Description

Mnemonic Direction

Not Used
N/U
Speed Indicator/Secondary
Receive Line Signal Det. SI/SRLSD
Not used
Not used
Send Clock
SEND CLK
Not Used
N/U
Receive Clock
REe eLK
Not Used
N/U
Secondary Request To Send SRTS
Data Terminal Ready
DTR
Not Used
N/U
Ring Indicator
RI
Speed Select
SPDSEL
Not Used
N/U
Not Used
N/U

16.2.1 Communications Signal Descriptions
Note
The following terminology is used interchangeable
to describe the communications signals:
Negative Voltage = 1 = Mark = OFF
Positive Voltage = 0 = Space = ON
1.

Protective Ground - This connector is connected to the chassis via
wire jumper TBD.

Signal Ground - This circuit establishes the common ground reference
potential for all interface circuits except protective ground.

Transmitted Data (output) - Signals on the line represent the serially
encoded characters that are transmitted from the communications port.
This circuit is held in the marking state dur ing intervals between
characters and at all times when no data is being transmitted.

Receive Data (input) - Signals on this circuit represent the serially
encoded characters to be received.

Request to Send (output) - Assertion of this signal indicates that the
channel is ready for transmission.

Clear to Send (input) - When this signal is asserted, it indicates
that the modem is ready for transmission.

Data Set Ready (input) - The on condition of DSR indicates that the
modem is in data mode, and that the control signals asserted by the
modem are valid.
Page 96

PC100 SYSTEM SPECIFICATION
8.

Receive Line Signal Detector (input) - Also called Carrier Detect. The
modem asserts this signal ON when the received signal is of sufficient
quality and magnitude.

Data Terminal Ready (output) - This signal is turned
channel is ready for transmission.

10.

Ring Indicator (input) - The ON condition indicates that a ringing
signal is being received from the comm line.

11.

Speed Indicator (input) - This signal allows some modems to control
channel bit rates.

12.

Secondary Receive Line Signal Detect (input) - This circuit is used in
half duplex coded control with reverse channel.

whenever the

Note
Speed Indicator and Secondary Receive Line Signal
Detect are two different uses of the same physical
line.
13.

Speed Select (output) - This signal allows the 8088 to control the
modulation method of the modem to coincide with its selected bit rate.

14.

Secondary Request to Send (output) - This signal is used
restraint mode and Asymetric FOX Secondary Request to Send.

15.

Secondary Clear to Send (input) - In FDX, this signal is the same as
Clear to Send. In Asymetric FOX, it provides the functionality for the
secondary channel.

16.

Secondary Transmitted Data (output) - In FOX, this signal is the same
as Transmitted Data, but when operating in Asymetric FOX, it provides
functionality for the secondary channel.

17.

Send Clock (input) - This is the external transmit clock that is
supplied by the modem substituted for the communication transmit clock
when the synchronous select bit is set.

18.

Receive Clock (input) - This is the external receive clock that is
supplied by the modem substituted for the communication receive clock
when the synchronous select bit is set.

Page 97

for

HDX

PC100 SYSTEM SPECIFICATION
16.3 PRINTER PORT INTERFACE CONNECTOR
Pin No.

Signal Description

1
2
3
5
6
1
20

Protective Ground
Receive Data
Transmit Data
Clear to Send
Data Set Ready
Signal Ground
Data Terminal Ready

Mnemonic

Direction

PROT GND
-----Output
RXD
Input
TXD
CTS
Output *
DSR
Output *
GND
-----Input
DTR
Note

-This output is always asserted high.
16.4 FLOPPY INTERFACE CONNECTOR
Pin Number
1

2
3
4
5
6
1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
21
28
29
30
31
32

Signal Description

Mnemonic

Ground
Track greater than 43
Ground
Not Used
Ground
Select 3
Ground
Index
Ground
Select 0
Ground
Select
Ground
Select 2
Ground
Motor On
Ground
Direction
Ground
Step
Ground
Write Data
Ground
Wri te Gate
Ground
Track 00
Ground
Wr i te Protec t
Ground
Read Data
Ground
Side Select

GND
TG43
GND
N/U
GND
SEL3 L
GND
INDEX L
GND
SELO L
GND
SELl L
GND
SEL2 L
GND
MOTOR ON L
GND
DIR L
GND
STEP L
GND
WRT DATA L
GND
WG L
GND
TKOO L
GND
WRT PRT L
GND
RD DATA L
GND
Side OH

Page 98

PC100 SYSTEM SPECIFICATION
16.4 FLOPPY INTERFACE CONNECTOR (Continued)
Pin Number

33
34

Signal Description

Mnemonic

Ground
Drive Ready

GND
READY L

16.4.1 Floppy Signal Descriptions
1.

Select Unit 3 (output, Pin 6) - When asserted, this signal indicates
that the current disk in position 3 is selected.

Index Pulse (input, Pin 8) - This input informs the controller when
the index hole is encountered on the diskette.
Minimum pulse width
is 20 microseconds.

Select Unit 2 (output, Pin 14) - When asserted, this signal indicates
that the current disk in position 2 is selected.

Select Unit 1 (output, Pin 12) - When asserted, this signal indicates
that the current disk in position 1 is selected.

Select Unit 0 (output, Pin 10) - When asserted, this signal indicates
that the current disk in position 0 is selected.

Motor On (output, Pin 16) - When asserted, this signal turns on the
drive's spindle motor.

Stepping Direction Control (output, Pin 18) - This direction signal
is an active low when stepping the head toward the spindle and active
high when stepping the head away from the spindle.

Step Pulse (output, Pin 20) - This is a 2-microsecond pulse to move
the head one track.
The direction of the step is determined by the
direction output.

Write Data (output, Pin 22) - This is a 500 ns pulse generated for
each flux transition.

10.

Write Gate (output, Pin 24)
This output
writing is to be performed to the diskette.

11.

Track 00 (input, Pin 26) - When asserted, this signal informs the
controller that the R/W head is positioned over track O.

12.

Write Protect (input, Pin 28) - This input is sampled whenever a
write command is received. When asserted, the command terminates and
sets the write protect status bit in the FDC status register.

13.

Read Data (input, Pin 30) - This is the raw data signal from the
drive. This signal should be a negative pulse from a minimum of 750
ns to a maximum of 1250 ns for each flux transition.
Page 99

is made

valid

before

PCtOO SYSTEM SPECIFICATION
1~.

Side Select (output, Pin 32) - When high, the outer sur face is
selec·ted. At present, only single surface drives are available, so
this pin would always be high.

15.

Ready (input, Pin 3~) - This bit indicates drive readiness and is
sampled for a logic high before a read or write operation.
This
signal means that a disk is in place and the door is closed and drive
selected. The motor does not have to be on.

17.0 OPTIONS
The following assemblies shall be also be offered as options to the base
system:
1.

Expansion RX50 consisting of:
a.
b.

RX50 disk drive
Data cable for second disk drive unit.
longer than the standard drive cable.
Color graphics

This cable

will

Extended communications, giving Bit/Byte/Async communications, as
well as a high speed networking capability.

18.0 CABLES
The following cables are included with the system:
1.

Monitor cable - transports monochromatic RS-170 "like" video
signals to the monitor and supplies the keyboard interface.
This
cable carries all power and ground to the monitor and keyboard. The
cable runs external to the system.

RX50 cable - is be a 3~-pin ribbon cable to supply interface and
ground from the system board to a single RX50 disk drive.

Power harness - carries all DC power to the system board and up
two disk drive units.

The following cables
non-standard cables.

are optionally offered

with

the

system.

They are

RX50 add-on cable - allows an upgrade to a second RX50 disk drive.

Video color cable - allows connection to a color monitor.
cable supplies a keyboard connection to the system.

Page 100

This

PC100 SYSTEM SPECIFICATION
19.0 ENVIRONMENTAL
The PC10e meets the requirements of the DEC STD 102, Class A. The PC100 and
all peripherals as a part of the system meet the requirements for FCC Class
B emitted radiation and conducted.

20.0 RELIABILITY
The PC100 demonstrates mean time between failures of no less than 2800
hours. This correlates to roughly one year of operation.

21.0 PHYSICAL PACKAGING
The outer measurements of the BA25 are 17.5 inches in width, 13.625 inches
in depth, and 6.0 inches height. On the front of the unit is the main power
switch, and a bezel with pop-out plugs for the RX50 disk drive(s). The back
of the unit supplies access for ac power and primary circuit selection
swi tch and circuit breaker, and access to standard and option connectors.
The packaging includes a fan.
The system board is housed in the lower portion of the BA25 and is encased
in sheet metal to minimize RFI problems. Enough space is available to
support another plane of circuit at in the very least 7/8-inch above the
system module.

22.0 VIDEO CHARACTER SET
See Appendix A.

23.0 APPLICABLE STANDARDS AND REGULATIONS
The PC100 complies with the following standards:
DEC STD 119
DEC STD 102

Digital Product Safety
Environmental Standard for Computers and
be a class A
product.

Per"lpnerarS-;--fh-e-PC100 wiIl

DEC STD 122

AC Power Line Standard

DEC STD 103

Electromagnetic Compatibility (EMC) Hardware
Design Requirements (draft): The Pe10a will
meet FCC class B level.

Page 101

pel00 SYSTEM SPECIFICATION

DEC STD 052, Section 1

Operational Requirements for Asynchronous,
Full Du p iex Serlal~mina!~ a~~_~~~te~
Interfaces peratin~ as J5'1"'E"i s Connecte<r~o
EtA RS-232 or celt V.28 Point-to-Poipt

Modems~--------------------------------

DEC STD 110

Escape Sequence Standard

DEC STD 111

Terminal Synchronization Standard

DEC STD 107

Digital Standard for Terminal Keyboards

DEC STD 138

Registry of Control Functions (proposed)

In addition, the following non-DEC standards have been used in the design
of the PC 100:
ANSI X3.16
ANSI X3.4-1977

Character Structure and Character Parity Sense
USA Standard Code for Information Interchange

TAStII)

ANSI X3.41-1974

Code Extension Techniques for Use With ASCII

ANSI X3·64-1977

Additional Controls for Use With ASCII

UL-478

Electronic Data-Processing Units and Systems

CSA C22.2, No. 54

Canadian Electronic Code, Part II, Safety
Standards-fOr-Electrical Equipment

VDE 0871

Limits of Radio Interference from Radi~
trequencyApp~atus-~d-lnstillat~ns-------

VDE 0875

Regulations for Radio Frequency Suppression

lEC 485

Safety of Data Processing Equipment

FCC Part 15

Rules and Regulations - Radio

EIA RS170

Electrical Performance Standards - Monochrome
Television studio Facilities

CCITT Recommendation
V.24

List of Definitions for Interchange Circuit
Between Data Terminal Equipment and Data

CCITT Recommendation
V.28

~rcult-~~mInarrngEqurpmemt---------------

Electrical characteristic for Unbalanced
Double-Current Interchange Circuits

Page 102

RainbowTM 100
PC100 System Specification
AA-P30BA-TV

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