Digital PDFs

XX-DACC0-12

June 1985

143 pages

Original

17MB

Document:	Dragon Video System Hardware Specification Rev 4.2 19850625
Order Number:	XX-DACC0-12
Revision:
Pages:	143
Original Filename:	http://bitsavers.org/pdf/dec/qbus/vcb02/Dragon_Video_System_Hardware_Specification_Rev_4.2_19850625.pdf

OCR Text

DRAGON
HARDWARE
June

VIDEO
SYSTEM
SPECIFICATION

25,

Revision

1985
4.2

This

page

intentionally

left

blank.

DRAGON

VIDEO

SYSTEM

HARDWARE

June

25,

Revision

COMPANY
RESTRICTED

The

change
additional

Bob
Ned

notice.

copies

Rose
Forrester

1985
4.2

CONFIDENTIAL

DISTRIBUTION

specifications
without

SPECIFICATION

contained
For
further

NOT

REPRODUCE

this
document
information

are
or

subject
obtain

contact:

HLO2-1/J12
PKO3-1/K90

225-6136
223-7015

SEAMOS:

: ROSE

REGINA:

: FORRESTER

DRAGON

VIDEO

SYSTEM

HARDWARE

CONFIDENTIAL

COMPANY

page

CONTENTS
1

INTRODUCTION

1.1
1.2

Definitions

2
2.1

2,2
2.2.1
2.2.2
2.2.3
3

3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.4.1
3.4
3.4.1
3.4.2
3.5
3.5.1
3.5.1.1
3.5.1.1.1
3.5.1.1.2

3.5.2.1
3.5.2.2
3.5.2.3
3.5.3
3.5.4
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.7
3.7.1
3.7.2
3.7.3

3.7.3.1
3.7.3.2
3.7.4
3.7.5

Documents

SYSTEM

Features

weew

2. 2.

«©

.:-.

OVERVIEW

Principal

«©

«©
©

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SF
6

«©

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Hardware

Buses

.°

«©

tlw

«©

«6

Bitmap
Timing

Memory
.

Memory
Dragon

...

2...

OPERATIONAL

«©

DESCRIPTION

Organization

....

Control
System
Viewport
Support

«©

«6

Scrolling
Dragging
A Region
Clearing
In
The
Drawing
Scrolling
Indexing
2.
Support
Multiplane
.

Destination
And
Holes
Bresenham
First
Source
Mode
Fast
Second
Source

Chip

Viper

6»

«©

«©©

«©

«6

«©

........

....

...

«©

.......-..

.......-.

Mask

Function
«

Registers

.....

....

Text

«©

«@

2...

«©

2...

«©

7
L7
LT
LG
LY
28
29
23
4
26
26
27
29
30
SL
33
35
36
38
38
40
40
41
43
44
49

«©

Tile
+

Patterns

«©

«©
«©

«©«©

8
8
CO
10
12
LS

46
47
48
49
OL

Graphics

And
2.

Mode

Additional

And

Linear

Polygons
Complement

.....

er
©

Registers

....

vectors
Of Vectors

And

AccesS

Graphics

.
And
.

...

And

Mode

«6

Source
RAM And

Text

Fill
With
Fill
Baseline
Flood
Polygon

Objects

Pitch
Text
And
Scaled
Attributes

Shading

Hardware

......

Transfers

Text

Points

Path

Data

Manipulation
Bit
Alignment

And

Storage

Support
Fill

And

Tiles

Data

Application

Character

Performance

Normal
Variable
Rotated

Processor/Bitmap
Font

Store

Application

.......

Control

Duplications
Computation
Scaling...

Unit,

Logic

.......6.

Error

Shifter

Barrel

Rotation

Addressing

«©

Chip

Region

Resolution
Mode
Z Axis
Addressing
Address
Calculation
Basic
Adder

3.5.1.2
3.5.1.3
3.5.1.4

3.5.2

ele

BS
8S
$4
OF
e680
62
G2
63

ene

DRAGON

VIDEO

SYSTEM

HARDWARE

CHIP

REGISTERS

DRAGON

AND

...

4.1.1.3
4.1.1.5
4.1.2
4.1.2.1

4.1.2.2

Rasterop

Command

4.1.2.3.1

PBT
Mode
PBT
zZ Mode
Command...
Cancel
X

4.1.2.3.2
4.1.2.4
4,2
4.2.1
4.2.2
4.2.2.1
4.2.2.2

PHYSICAL

5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.3
5.3.1

A.l.1.1

.«

«©

Chip
Viper
Memory
Bitmap
Video
Clocks

«6

Power

High

Timing

System

Sync

Memory
Data
Memory

eee

Adder

Bugs

«6

«©

Interface

....

oo.

.....

he)

whe)

2...

The

Pass

Circuits
«©

74
76
78
85
86
88
89
89
91
92
93
93
101
101
102

L105
105
105
106
107
108
108
108
109
109
110
C10
6D
CUD
hULDD
lil
112
113
hUdLDG
114
CSS
117

6118
61D
6120
121

......

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we)

ew)

he)

ew)

Adder...

et)

65
65
65
66
72

Scrolling Boundaries 122

And
©

we)

cee

CHANGES

eee

AND

Assignments
And
Configuration

...

BUGS

Chips...
Chip

Bit

Bus

BuS

Circuits
Enable
Pixel
Clipping
Single
And
Video
Video
Bus
Output

CHIP

Write

Pass

1/D BusDevices

Selection

DRAGON

External
“Chip Selects
Address
Memory
Address
-Memory
Refresh
Memory

Processor

«©

wtwe

Generation

Bus.

6...

see

«©

.......

«1

.....-+

Speed

«©

eee

....

«@

Clock

I/D
-

Output
.

.......

Chip

«5.

....

«©

«@

«©

VIPER

«©

«@

«©

«6

...

«©

BUS

.....+s+..

2...

Pins

I/D

«©«©

Power

...

Timing

Clocks

Instructions
Instructions
I/D
Instructions

I/D

Pins

BUS
I/D
Monitor

Interface
And
Address

Processor

5.4

A.l
A.l.1

Bus

Chip

Memory

5.3.2

«©

Commands»...

Processor

Chip

2...

CONFIGURATION

Adder

«©

Instruction/Data

5.1

5.9

Bus)
Viper
Chip (I/D
Viper
Chip Registers
Local
Adder

Transfers

Processor/Bitmap

5.8

.....

......

4.1.2.3

5.6
5.6.1
$.6.2
5.6.3
5.7
5.7.1
5.7.1.1

.........

«©

page

......

4.1.1.4

5.4.1
5.5

COMMANDS

Adder
And
Commands
Chip Registers
Adder
Chip Registers
2.
Interface
Control
Registers
Scroll
Registers
1.
Control
Registers
Update
Control
Registers
Rasterop
Screen
Format
Control
Registers
Adder
Chip Commands

4.1
4.1.1
4.1.1.1
4.1.1.2

CONFIDENTIAL

COMPANY

123
6124

61258
615
125
125

DRAGON

VIDEO

aaa
@

Chip

Pass

Bugs

Features
1 Chips

Adder

aaaNR
s

The
2
2
The

In
Pass
The
Pass
Not
In
-

Adder
OAD

Pass
*

CONFIDENTIAL

Viper

AeViper

Pass

page

#®

125
125
125
126
126
126
126

NNNNNN
e

COMPANY

Not

Viper

«¢

HARDWARE

Features

Ne
EH
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e

SYSTEM

Chip
In

Bugs

Features

Viper

aa NN

INDEX

Chip
In

Bugs

Features

Pass
The
Pass
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Pass
The
Pass
In
Not
-

Adder

The

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1
The

Viper
Pass

pteAddePr
8

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127
128

128
128

131

DRAGON

VIDEO

SYSTEM

HARDWARE

COMPANY

CONFIDENTIAL

page

INTRODUCTION

This
document
will
that
System
These
of

systems.
the
them

control
DEC's

series.
variable

describes

the
in many
terminals

be
video
several

hardware
future

used

the

may
processes

different

by
for

generation
replacement
New
features
include
display
may
screen
fonts,
pitch
rectangular
next

one

the

Video

Dragon

terminals
virtual
support

and

display
terminals

making

user,

VT100

larger
regions,

for

and

vT200

sizes,

screen

and

bitmap

graphics.
this

In
most

form

formats
will
be
reserved

initial

have

some

only
products.

1.1

circumstances
Terminals

by
the

enclosed
for

Due

enclosed
uncontrolled
authors.

may

the

of
are

this

circulation.

not

Extra

Viper

first
the
listed
first

pass
second

copy

the

Dragon

chip
chips.
pass
the

chips.”

pass

document

construed

refer

this
to

by multiple
dimension.
spatial

variations

the
in

bitmap

planes

document,

"X"

and

variable
this

copies

may

terms

intensity,
and
"Y"

terminal
produce
any
This
should
specification
based
designing
Dragon

and
and

personnel
confidential
do

the

use

Engineering
specification.
please

the

features

should

and

nature

document
be
obtained

the
allow
from
the

Definitions

provided
third

the

information,

"color"

its

features

description
in

not

only

training
to

Throughout
or

in
screen

implemented

(DC323B)

chip

and
differences
bugs
should
product
design

Some

not

complete

features,

new

describes

used

described

features

products.

any
and

pass

commitment
be

is
the
Adder

pass

specification

used

extensions

system

which

offering.
second

Under
a

future

The

first
chips;
appendix.

Dragon

regard

specification

system.
(DC322B)
The

without

actually
for

product
This

the

specification,

general

axis",

color

does
not
do
refer

refer
the

dimension"
blink
as
to
the
horizontal

DRAGON
VIDEO
INTRODUCTION

SYSTEM

vertical

spatial

and

The
controls
tasks

term

"local

the

Dragon

such

chips"

refers

refers
its

dimensions

respectively.

processor"

refers
to
This
processor
communications

system.

providing

the

outside

world,

"Dragon"
system

COMPANY

to
product
application.

(with

HARDWARE

CONFIDENTIAL

"Dragon

only
all

system"

without

local
Adder

the

Dragon

the

even

running

refers

interface

the

user's

entire

video

or
"Chips"
"Dragon
"Hardware"
chips.

the

EXCEPT

system

non-video-.

the

processor).
and
Viper

that

processor
have
may
the

page

—

local

and

processor

firmware.

"viewport" is

from

mapped
refers

the

"<"

place

the

users

this

between

information

implementation

Differences

highlighted

the

"window"

change

the

symbol

that

readers

start

may

left

of
wish

image

The
term
"region",
in
the
hardware.

viewports
the

which

screen

data.

and

specification
in

bars

the

revision

3.4

are

margin.
indicates
paragraph
their
skip during

detailed
first

reading.

1.2

This
and
software
documents

Documents

specification

provides
of

concepts

the

additional

provide

general

coverage
The
interest

Dragon

system.

detail

the

hardware

following
to
product

implementers:
1.

Video

Dragon
page

Firmware

programming.
potentially
3.

DC323

Seriously

The

specification.
Guide
of
date,

out

parametric

Chip Specification
of
specification

Functional

Description

Viper

following

tutorial
still

Dragon

but

useful.

Adder

DC322B
and
AC

Specification

Summary

Programmers

specification
§.

this

summary

Dragon

Hardware

System

Video

the

Processor

parametric
documents

the

Functional
Adder
chip.

DC322

and

Functional

chip.

(Viper)
specifications

Chip

provide

implementation

Specification
the
Viper

chip.

examples:

DRAGON
VIDEO
INTRODUCTION

SYSTEM

HARDWARE

COMPANY

SERRA

A library
DRAGONLIB.C
the
C language.
Along
the
a
library
provides

fmimanle

Dragon

drawing

with
of

set

CONFIDENTIAL

routines

associated
examples

page

written

calling
for

programs,

using

most

functions.

eet

cineet
siE
oD
eN

Viper
implementation
programmable

and
of

Pegasus

resolution

Adder
a
four
run

any

Board

plane

These

schematics

Dragon
bus

memory

system

width

mode

show

that
and

any

mode.

SHNE

SN
SemtiOE

etch

Pegasus
Dragon

board

schematics

Simplified

half

page

system.

ANNIE
ORE

QDSS

Secrest

8
page,
commands

nee

Base

Subsystem
plane
system
from

Qbus.

and
A
Modules
Memory Upgrade
with
to
DMA
capability
Dragon
-

full

DRAGON
SYSTEM

VIDEO
SYSTEM
OVERVIEW

SYSTEM

The
tube
and

HARDWARE

COMPANY

CONFIDENTIAL

page

OVERVIEW

Video

Dragon
driven

displays

System

scanned

raster

cathode

facilitate

flexible
of
by
bitmap
formatting
text
to
in
all
video
terminals.
provide
graphics
capability
allows
a
of
and
sizes
Appropriate
modularity
range
display
memory
to
be produced,
full
or
traditional
including
page
partial
page
and
with
one
or
more
of
displays
planes
display
memory.
Monochrome
and
color
are
available.
are
displays
Display
regions
to
facilitate
the
use
of
different
of
the
implemented
portions
screen
The
allows
text
by different
processes.
system
high speed
of
the
(or
the
local
to
graphics)
update
bitmap
by
processor
support
editing.
ray

2.1

Features

bitmap
a

over

Principal
l.

cell

variable

character

graphics

capability.

Arbitrary

display
format
width
and
height,

the

known

advantages
include:
Examples
inherent

positioning

and

display

provides

the

pixels

(Paster

page

avoiding
The

size

version
of
refreshed
the
flicker
and
also
systems
may

full
thousand

The

well
many
the
VT100.

display
provides
like
display

the

smear

possible.)

about
60

screen

850

Hertz,

interlaced

display.

is
to
allow
programmable
refresh
rate
combinations.

different

regions
support
multiple
viewports
can
be
smooth
scrolled
both
region
and
at
various
horizontally
speeds.
Incoming
to
the
boundaries.
New
data
can
clipped
region
a
to
even
in
is
region
though
scrolling
rectangular

Each

screen.

vertically
is
data
added
be

progress.
5.

Return

results

clipping
assist

processor

can

editing,

used

windowing

and

the

local

picking

algorithms.
6.

The

with

interface

direct

passing

local
of

the

local

either
processor
supports
to
the
video
or
system,
a
DMA controller.

access

processor
commands

through

planes
Multiple
bitmap
(up to 24) support
applications
color
or
control
All
scale,
gray
requiring
planes.
be
can
manipulated
planes
simultaneously.

Any of
resolution

the

allows

planes
or

depth

can

four

quarter

(color)

subdivided
resolution
be

traded

into

two

half

This
resolution.

planes.
for

“eee

DRAGON
SYSTEM

VIDEO
SYSTEM
OVERVIEW

axis

that

sub-plane)
adjacent
to
easily

ll.

The
basic
character
if
fully
200
msec

CONFIDENTIAL

bit

fill

hardware
fast
provides
20 thousand
characters/second,
local
(about
processor

page).

average
be

extended
the
beyond
character
size,
arbitrary
and
variable
sub/superscript

may

like:

italics,

angle,

manipulation
rate
of
writing
the
supported
by

additions

Rasterops

are

source

orientation.
combined

with

mode

linear
orient

patterns

Another

of
mode
of
vector

pattern

The

use

good

transform

arbitrary
pitch

tiles
destination.

source)
rasterops

operate
operate

another

Scaled
at

to
pairs
an
image

of
64Kx1l
or
will
lower

size

any

be
may
rotated
about
0.5
million
at
about
8 million

image

two-dimensional
Linear
patterns

allows
the
be
filled
at
about
8

rasterop

rectangular

destination

allows
creation
of
of
cell
size.
any
the
drawing
path.

circuits

2.2

normal

<Arasterop

series
tile
15.

any

(single

rasterops

14.

that

Halftone

pixels/sec;
pixels/sec.
13.

provided
parallelogram

with

VT100

fonts.
12.

page

allows
an
alternate
form
of
memory
the
transfers
bits
from
each
(or
plane
that
to
one
instead
of
correspond
pixel,
X bits
from
one
This
can
also
be
used
plane.
all
for
a
color
to
be
written.
program
planes

attributes

Text

COMPANY

addressing

access

10.

HARDWARE

64Kx4
RAMS
and
the
cost
of
the

between
a
solid

area

with
million

color,

pixels/sec.

custom

VLSI

control

achieve

system

ratio.

cost/performance

Hardware

A brief
functions
information

overview

the
hardware
will
aid
of
understanding
in
sections
3
and
4.
Basic
presented
timing
is
also
to
enable
calculation
of
provided
Additional
hardware
is
in
introduced
section
3 as
performance.
it
is
Additional
information
about
the
Adder
and
required.
Viper
and
other
hardware
is
in
contained
chips
Dragon
components
section
internal
of
these
is
5; the
complete
specification
chips
covered
see
section
1.2.
documents,
by separate

the

Figure
two,
the

custom,

speed

components:

the

shows
VLSI

chips

the
the

system.
local

Dragon
to

system

reduce
the
The
system

processor

hardware.
cost

The
and

comprises

(optionally,

design

size,
six
with

and

logical
a

DMA

uses

increase

DRAGON
SYSTEM

VIDEO
SYSTEM
OVERVIEW

controller),

the

HARDWARE

COMPANY

CONFIDENTIAL

page

(address

Adder

(3 micron,
processor)
chip
ZMOS),
(video
(4
Viper
processor)
chips
and
shift
and
the
map
register
circuits,
The
Adder
(DC323,
chip
formerly
upper
functions
that
are
common
to
all
planes,
such
as:
local
all
processor
interaction,
rasterop
computations,
address
screen
bitmap
scroll
generation,
clipping,
refresh,
control
and
monitor
The
sync
generation.
(DC322,
Viper
chip
lower
the
data
and
control
formerly
elements
chip)
provides
path
that
are
to
each
such
data
as:
FIFOs
for
refresh
unique
plane,
and
a
barrel
shifter
for
bit
a
unit
scrolling,
alignment,
logic
with
data
and
mask
for
Z axis
registers
modification,
memory
address
and
a
control
store
RAM to
define
logic,
Viper
chip
operations
during
rasterops.
the

bitmap
memory
planes,
color
micron,
HMOS), the
high speed
timing
logic.
is
for
chip)
responsible

multiple
generator;
except
may

limitations

exceeded,

2.2.1

possible

the

the
screen
of
displays
that
are
from
the
same
clock
Dragon
systems
running
no
buses
be
shared
may
by separate
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local
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to
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processor
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up
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however,
chip;
loading
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section
5.4
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32 Viper
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DRAGON
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VIDEO
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nsec.

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DRAGON
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SYSTEM
OVERVIEW

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screen
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parameters)
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is
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less

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1.5

2 shows
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16 major
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the

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which

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scroll

refresh
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are

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reads.

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of
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words
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if
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and
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any
scroll
are
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minor
for
cycles,
cycles
updates
or
NOPs.
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address
bus
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row
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column
provides
eight
addresses
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and
one
row
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column
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major
cycle,
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data
bus
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cycle.
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number
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the
data
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the
screen
screen).
refresh
Enough
reads
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executed
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each
scan
to
512
memory
display
pixels
of
the
bus
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width,
regardless
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guarantee
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of
refresh
all
these
need
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to
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but
memory
pixels
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must
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No
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than
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can
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unless
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to
each
pixels
displayed
memory
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minimum
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and
width
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to
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1024,
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major
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DRAGON
SYSTEM

SYSTEM
OVERVIEW

VIDEO

HARDWARE

COMPANY

CONFIDENTIAL

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DRAGON
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VIDEO
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OVERVIEW

HARDWARE

COMPANY

CONFIDENTIAL

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DRAGON
VIDEO
OPERATIONAL

SYSTEM
HARDWARE
DESCRIPTION

OPERATIONAL

This
and

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overall
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video
hardware
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CONFIDENTIAL

DESCRIPTION

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The

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4.1.1.5
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power

3.2

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through
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Adder
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chips
and
rasterops.

—

DRAGON
VIDEO
OPERATIONAL

SYSTEM
HARDWARE
DESCRIPTION

CONFIDENTIAL

COMPANY

page

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directly.
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word
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data
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registers,
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3.3

Viewport
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of
on
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and
or
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chips
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Dragon
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left
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Figure
examples
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either
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currently
clipping
cannot
and
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be
modified
scrolling
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DRAGON
VIDEO
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SYSTEM
HARDWARE
DESCRIPTION

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CONFIDENTIAL

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CONFIDENTIAL

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number

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size
the
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region,
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to
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but
are
there
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screen,
time;
side
in motion
effects.
one
can
be
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unpleasant
only
region
a
frame
because
two
want
to
write
time,
during
regions
might
of
the
same
word
to
more
than
one
location.
portions
memory
down
cannot
in
be
the
obvious
Second,
scrolling
accomplished
way
because
this
would
data
into
locations
not
require
writing
memory
read
yet
by the
refresh/scrolling
process,
thereby
destroying
screen
data.

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its

data
normal

from

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down

region

refresh
illusion
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is
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This
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the

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Some

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displayed)
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being
of

the
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memory

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consumption

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frame

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for

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time
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all

"disabled".

not

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and

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motion

sideways

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processor.

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be

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data

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up
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of
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bottom
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number
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top.
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the
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in
distance,
in
one
frame
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of
4.

reading
region

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planes
3.

of
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outside
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address
at
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does
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pixels,
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and

starts

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up,

the

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work

for

the

local

VIDEO
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COMPANY

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page

commands
with
screen
most
refresh,
scrolling
related
in
both
the
Adder
and
registers
Viper
chips
buffered.
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required
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note
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(see
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requests
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synchronize

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of
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chip
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ID
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registers
scrolling
update,
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data
select
control
for
the
is
path
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chips)
for
this
allows
a
scroll
service
routine
to
provided
scrolling;
act
without
the
to
state
of
service.
The
scroll
regard
update
and
services
must
avoid
each
other's
The
update
using
registers.
use
and
control
of
the
index
is
somewhat
more
registers
and
is
described
in section
3.3.4.1.
complicated
To

prevent
for

and

NOTE
conserve

die

registers

are

scroll

required
Single
registers
regions

sustain

Extra

region.

in
the
buffered

area

only
scrolling
buffering

Adder

chip,
the

extent

dragging

index
different
function

the

would
be
needed
to
scroll
in
This
successive
frames.
is
not
considered
because
its
use
important
only
be
in
would
to
simulate
simultaneous
trying
two
of
separate
regions;:
scrolling
however, a
smooth
effect
cannot
be
achieved
by this
so
it
should
not
matter
if
technique,
anyway,
the
of
of
the
two
abruptness
jump scrolling
is
[If the
local
increased.
regions
processor
to
can
service
an
load
four
interrupt
request
in
on
screen
200-500
usec
(depending
registers
then
it
will
be
to
scroll
format),
possible
in
frames
different
successive
without
regions
of
the
extra
the
index
buffering
registers.
local
take
an
the
processor
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entire
frame
time
to
load
buffered
any

3.3.2

Dragging
scroll

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different
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with
distance

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used

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to

For

screen.

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size

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smoothly
each
for

drag

increment
the

current

in
increased
this
allows

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the

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direction
whole

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DRAGON
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CONFIDENTIAL

COMPANY

must
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it
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HARDWARE
SYSTEM
DESCRIPTION

stop
to

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four
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the
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the
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sixth
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can
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with
a
screen)
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for
the
next
frame
use
of
the
time,
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waiting
erase
mechanism
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a
clean
because
it
provide
very
appearance
is
to
occur
between
two
synchronized
display
frames.

cleared

3.3.4

Drawing
The

The

filled
continues

blank
space
with
new
data.
so
that
the

disturbed.

The

drawn

draws

the

keep

filling
“The
from
the
control

clipping
being
clipping

the

scroll

region

the
the
location

selected

Typically,
portions

region
stands
outside

still

during
region.

scrolling

prevent

this
means
However,
as
a
cannot
used
function"
region
"drawing
to
the
or
extent
of
drawn
into
a
objects
being
shape
does
not
move
because
the
with
the
moving
region,
clipping
region
as
are
cannot
be
used
drawn.
to
Also,
objects
they
clipping
of
when
the
writes
data
same
list
prevent
multiple
display
are
this
would
the
segments
repeated
during
scrolling;
require
follow
of
blank
to
a
set
as
clipping
region
particular
pixels
move
on
screen.
writes
will
create
the
they
problems
Multiple
for
in
lists
that
contain
drawn
mode
display
segments
complement
or
drawn
with
the
which
successive
(in
painter's
algorithm
elements
elements).
replace
previous
data
that

written

(or

screen
screen.

needs
to
be
draw
while
scrolling
scroll
is
not
Adder
data
chip allows
without
to
how
regard
the
update
process
of
to
it)
repeatedly
blank
is
created.
space

scrolling

desirable

effect
mechanism

correct

the
moving
list
display

Region
created

It
is
smooth

scrolling

that

indexing
the

Scrolling

the
be

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enable

commands,

(to

pause
set
a

to
DMA

the
synchronizing
the
areas
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interrupt
the
when

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continue
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the
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this
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displayed;
bottom
edge of a region
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become
space

into

CONFIDENTIAL

update
or

enable

request
or

processor

or
a

bottom
of
full
frame
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scroll

scrolling),

by
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with

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created

on
the
specific
point
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Normally,
pause
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allow
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update

refresh.
routine

screen

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3.3.4.1

COMPANY

fill
and

controller

passed
the

SYSTEM
HARDWARE
DESCRIPTION

the

bits
further

can

data
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has
be

screen

would

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from

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process

the
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visible.

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To

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requiring
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is

the

local

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scrolling

processor

scrolled)

has

controller

DMA

without

to
the
coordinate
values
in
processor
change
there
are
index
in
the
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registers
chip
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are
added
to
the
first
source
and
destination
coordinates
to
match
the
new
of
data
that
has
been
position
moved in the
memory
There
six
index
old
X and
are
X
by scrolling.
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registers:
and
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The
Y.
old
values
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the
indexes
that
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pending
to
data
that
has
not
moved
the
current
apply
yet
frame;
during
the
new
values
are
the
indexes
that
to
data
that
has
apply
been
the
values
will
become
the
new
values
moved;
already
pending
at
the
start
of
the
next
frame.
Between
the
Adder
frames,
chip
transfers
the
in
value
stored
the
new
to
the
old
register
and
from
the
to
new
the
thus
register,
pending
register
register,
the
new
frame
with
the
correct
indexes.
The
index
starting
values
to
the
that
if
apply
region
is being
updated.
Ordinarily
the
is
also
the
new
and
old
indexes
scrolled,
update
region
being
will
differ
scroll
constant
the
(X or
Y¥) for
current
frame
by the
in
(loaded
the
and
if
the
is
not
frame);
previous
update
region
scrolled
and
the
new
old
values
are
the
same.
being

The
between

being

values
scroll
time.
index
values

values

must

updates

different
the
scroll

scrolled,
between
movement

Because

registers
provided

must

This

general,
update
scrolling
processor
controller
Adder

index

maintained

frames
when
both
and

they

changed
regions.

process

must

that
extend

Also,

update

process

update

the

update

will
updates
the
beyond

maintained

the

is
driven
not
the
process
may
change
update
because
a
frame
end
between
may
index
in
values
the
data
places
and
the
time
that
these
values
Thus
it
best
to
is
not
send
chip.
the

the

stay
end

update

process

local

region

index

the
locked
of
one

the
and
scroll
update
processes
the
must
use
the
update
process
the
scroll
a
process,
tight
very
between
these
two
processes.

interlock
if

the

frame
the

modify
most

recent

interlock

the

time

list

for
loaded

are

region

that
the

changes

thus,

processor

by a DMA controller,
to
one
that
region

the

is
local

the
DMA

into

the

through

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DMA
<

SYSTEM
HARDWARE
DESCRIPTION

COMPANY

CONFIDENTIAL

page

controller.
When

local
interlock

the

following
l.

changes

processor

with

The
and

local
the

processor
of
part

(no

DMA

controller).

The

update

the

scroll

the

always
update

the

update

region,

process

recommended:

executes

the
that

scroll

process

regions

changes

scroll
interruptable
by the
is
process
update
process
regions
changing
unless
the
caused
(note
below),
exception
by
latency
is
index
disabling
interrupts
during
loading
acceptable
when

the

system.

During

memory

location
is
now

region

must

process
the

region

the

change,
tells

that

being

update
the

scroll

process
process

loads

what

updated.

correct
index
values
for
process
copies the
from
a
table
maintained
scroll
by the
to
the
Adder
The
index
process
chip
registers.
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in
must
loaded
the
order:
new
and
registers
pending,
then
If
old.
the
that
is
to
used
move
instruction(s)
each
index
value
to
Adder
the
is
it
chip
interruptable,
is
to
disable
least
for
(at
the
necessary
interrupts
of
the
scroll
service
while
each
priority
interrupt)
index
value
is
copied.

The
that

update
region

is
the
scroll
will
be
started,
process
the
scroll
service
from
the
Adder
interrupt
by
The
scroll
must
run
to
before
process
chip.
completion
to
the
The
scroll
returning
update
process.
process
table
the
index
entries
for
the
updates
region
being
SCROLLED
so
that
new
values
will
be
available
to
the
If
a
new
awakened

update

frame

process.

The
scroll
process
in
the
Adder
chip

load
should
with
the
new
If
the
update

all
six
values

index

registers

the
region
is
NOT
UPDATED.
the
as
being
region
same
the
scroll
the
need
not
be
If
loaded.
region,
registers
is
that
in
the
scroll
certain
the
index
values
process
the
to
the
scrolled
Adder
chip
corresponded
region
being
of
the
frame
that
caused
BEFORE
the
end
the
scroll
there
is
one
on
the
only
region
interrupt
(perhaps
has
screen
or
the
scroll
been
since
region
only
updated
the
then
the
last
index
scroll),
only
pending
registers
need
to
be
loaded.

Update

processing

may

now

continue.

for

DRAGON
VIDEO
OPERATIONAL

3.4

SYSTEM
HARDWARE
DESCRIPTION

Multiplane
The

multiple
manipulation

use

chips

described
functions
each
Viper

CONFIDENTIAL

page

Support

simultaneous

Viper

COMPANY
,

Viper
of

controlled
The

are

above.
to
be

chip

(data

many

exchange
for

registers
performed
may
in

chips

data
by and

data

allows

chips)

path
planes

data
transfers

independently

memory.
the
I/D
and
the

the
The
bus

logic
for

programmed

system.

The
number
of
is
fanout
of
the
I/D
planes
limited,
by the
address
to
24 Viper
of
the
address
buses,
chips
(buffering
is
the
400
load
on
the
bus
I/D
required;
pf maximum
may
32 Vipers
if
a
close
is
Z axis
maintained).
permit
layout
are
limited
to
words
of
Z data
operations
4, 16 bit
addressing
which
a
allows
of
maximum
64 planes
or
this
subplanes;
to
half
the
maximum
number
of
that
would
corresponds
subplanes
otherwise
be
from
32 Viper
possible
chips.

and
bus

Resolution

3.4.1

Mode

The

resolution

bits/pixel.

the
each

video
of

two

pairs

bus
four
of

of
bit
mode,
for
four
divisions

pairs

The

of
bit

one

four
to

adjacent

may
four

set

the
two

possible

states

two

bit

each
each

bits

for

the

screen;

and,

possible

pixels.
is
plane

16
the

referred

One

two

defines

appearing

mode,

states

bus

video

the

resolution

low

planes

possible
pixels

adjacent

output
a

defines

screen;

defines

horizontally
of

chip

the

horizontally
each

all
each

Viper

pixels
bits

mode,

any

four

states
or

the
two

four

subplane.

actual

of
the
video
bus
data
as
interpretation
multiple
must
be
in
the
color
adjacent
pixels
provided
map;
the
modifications
to
the
use
of
data
and
but,
Viper
chip
provides
the
of
barrel
shift
and
the
masks,
effects
values,
interpretation
Z axis
of
that
aid
the
of
low
resolution
addressing
manipulation
section
4.2.1
for
an
(see
of
the
planes
complete
description
effects
of
resolution
Resolution
in
mode).
mode
the
Viper
chips
affects
the
of
new
data
so
that
different
only
writing
regions
can
have
different
resolution
additional
however,
settings;
external
hardware
would
be
to
different
required
actually
provide
color
to
different
map
interpretations
regions.
for

States

Resolution

mode

tradeoff
between
it
is
not
intended
there
are
Viper
each
of
other
as
Some
of
chips.

the

control

restrictions

share
store

limited
application
resolution
in

the
and

depth
to
provide
Note
chips.
are
planes

Subplanes
and

has

of
one

a
allowing
planes;

than
general
purpose
planes
are
NOT
subplanes
independent
with
implemented
separate
Viper
on
are:
subplanes
more

that

update
ram

settings
in

the

for

viper

the

chip.

logic

function

DRAGON

comin

mode
bits

Complement
the

each
of
addressed

LmtneA

during

SRNR

with

mask

complement
register

MERE

only

one

mmm

COMPANY

HARDWARE
SYSTEM
DESCRIPTION

VIDEO

OPERATIONAL

will

writing
in

separately,
access.

each

bit

will
all

not

avoided

Viper

chip

low

resolution

can

because
will
be
be
written
the
problems

general

pixel

writing
in
the
within

but

page

work

not

resolution
both
bits

low
but
Some

CONFIDENTIAL

by programming
to
permit
writing
pixel.

Sm
3.

Inainuim

Writing
speed
proportionately

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addresses

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accessing

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each
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snnane

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lowest

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data.

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time)

are

pixels

shows

enabled
of
increase

examples
two
planes

Viper

data

the

are

used,

use.

When

subplanes,
of

the
of

phase

low

speed
in

reduced

larger.

are

low

the

chip,

enabling
through

rate

of
both

use

scroll

duration;

longer

the

have
to
intended

may
the

proportionately
the
pixels

because

are

not

two

example,

upper

horizontal

maximum
would
be

planes

does
subplanes
chip.
Viper

the

screen

cannot

subplanes

off

depending

horizontally,

resolution

loaded

patterns

resolution

Figure

still
chip
resolution,
Of
pixel.
on
the
pixels

were

low
resolution
a
low
resolution
fraction
a
given
to draw
for
full
resolution.
as

same

(pixels/frame

Adder
full

within
fewer

time

the

resolution

will

pixel
The

because
if
it

be
scrolled
independently.
that
contains
a
scrolling
region
should
be moved
by multiples
only
to
the
resolution
subplane
preserve

Subplanes
horizontally
the
region

low

resolution

low
reduced

resolution
in

mode.

bit

mode,

to
shift
are
serialized
buses
registers
from
a
color
four
values
one
of
accesses
bit
code
that
a
two
In
lower
the
of
each
color
the
to
determine
example,
pixel.
map
one
of
sixteen
choose
in
4 bit
mode
to
is
used
one
plane
1 bit
while
the
mode
for
four
colors
adjacent
pixels
foreground
color
or
a
of
this
choice
an
makes
independent
plane
foreground
in
the
of
four.
color
for
each
screen-wide
group
pixel
background

whose
form

video

3.4.2

Z
Z

Adder
data

output

Axis

axis

and
word

operations
chips
Viper
to

subplanes.
between

the
of

Addressing
allow
the
bit
one
be
used
on

transfer
can
This
local
processor

appropriate

the

for
memory

Viper

of
exchange
using
by

bus
I/D
to/from

chip

both
and
data

each
the
the

data
the
of
16

planes

exchange
bitmap,

of
and

data
the

registers.

between
16 bits

the
of

DRAGON
VIDEO
OPERATIONAL

SYSTEM
HARDWARE
DESCRIPTION

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COLOR

HARDWARE
SYSTEM
DESCRIPTION

DRAGON
VIDEO
OPERATIONAL

CONFIDENTIAL

COMPANY

page

a
bit
with
six
plane
programmed
an
bus
the
bit
within
I/D
specify
a Z axis
a Viper
data
word
to
which
during
chip will
respond
Z block
two
bits
the
and
the
(separate
specify
upper
operation;
need
if
16 planes
or
more
than
bus
transaction)
I/D
subplanes
used
to
selects
be
be
transferred.
may
Alternatively,
chips
Z blocks.
to
form
of
enable
groups
viper
chips

Each

and

the
next
address
nibble
whole
two

have
four
ensured

normal
controller

and

nibble

lowest
have
the

bit

equal

I/D

command,

axis

fill

scroll

I/D
data

one

the
command

bus
load

output

bit

must

plane
transfers

and
the

plane
other

addresses
the
resolution
plane

bit
have
the
address.

addressed

the

and

address;

resolution

plane
of

any

(this

the

may
two

must

processor).
data
data
exchanges,
transferred
to/from
If
Z mode
transfers
of
will
be
the
color
and
4.1.2.3.2.
3.5.3

the

can

DMA

are
one

pixel.

with
an
be
commanded
directly,
the
source,
foreground,
background
The
source
in
the
Viper
chips.
in
the
the
units
the
Viper
chip,
logic

cycle
either

registers
to
input
background

and

bus;

boundary,
to
corresponds

processor/bitmap

plane

and

address,

any

transfers
resolution

bit

same

low

I/D
and

address,

bit;

have

may
the

the
from
bitmap
local
or
the
processor.
word
transferred
each
sections
information
see

new

whose

local
During
rectangle

requested,

the

bit
even

starts

may
address
a
bits
accessed
local
by the

plane

higher

planes
plane

For

basis
axis
which

that

bits

resolution
addressed

the
have

must

can

four

lower

bit

transfers

plane

chip

Viper

the

address;

can

are
selected
registers
and
unit
loading
logic
for
the
the
Viper
chips

program
will
elements
subsequent
the
color
define
Viper
chips
of
scrolled
areas
regions.

The
be

drawn.
will
that

them
colors

fill
written

bit-for-bit
with
with

registers
into

the
ad

3.5

Basic
The

Calculation

Address
and

Adder

Viper

And

chips

Data

contain

Hardware

Path

bitmap

manipulation

local
hardware
by the
processor.
provided
which
can
select
are
All
pixels
rasterops,
manipulations
with
and
combine
them
screen
of
the
(a source)
from
an
area
The
Adder
area
from
another
(a destination).
selected
pixels
and
control.
bit
word
and
all
handles
addressing,
clipping,
chip
data
and
bit
The
exchange
logical
alignment,
Viper
chip provides
modes:
linear
three
are
There
combinations.
normal,
rasterop
the
normal
will
describe
This
section
and
fill.
mode;
pattern,
in
will
be
described
section
fill
modes
and
linear
the
pattern
to

execute

the

commands
based
on

3.7.
The

registers

contents
are

NOT

of
the
modified

Adder
or

and
Viper
destroyed

chip
by

any

rasterop

operation

parameter
of

the

DRAGON
VIDEO
OPERATIONAL

loaded

registers

3.5.1

CONFIDENTIAL

those
whose
values
registers
between
Of course,
operations.
be
may
changed
by rasterops.

Adder

Every
sources;

two

COMPANY

Only

system.
to

SYSTEM
HARDWARE
DESCRIPTION

Chip

are

the

page

need

changed
of

content

data

Addressing

has

rasterop

destination

and

have

may

zero

one

implies
to
be modified
pixels
source
combined
with
being
destination.
No curve
are
algorithms
implemented
because all of
the
useful
ones
and
there
is
no
"best"
require
multiplications
for
all
curves
be
handled
applications;
may
by passing
algorithm
a
series
of
vectors
to
the
Adder
straight
chip.
destination

size

scaled

source

zero

destination
orientation
or
rotated

used
characters
However,

The
and
the
the

source.

for

The
destination

and

patterns
can

than
used
from

be
copy

(as

fallout
is
useful

but
vectors,
independent
and
performing
discussed
rotation
below,
mode
complement
drawing

operations

rectangle

screens

and

different
with
the
and

data

scaling

pictures..
of
image to an area
off
screen.
area,
possibly
form
of
the
simple
rectangle)
of
its
as
two
implementation
for
italic
characters
forming
with
non-square
pixels.

"zoom"
another
to

opposed

largely

may

Rotation
elements
such
picture
for
whole
transforming

transforming

scaling
is

first
source
destination.

the
the

fit

and

parallelogram

than

by a scaled
parallelogram

The

constant

selects
generator
select
generators
pixels

are

screen

scaling

may

not

suitable

the

during

operations.

of
is
source/destination
controlled
operations
command
three
bits
select
one
of
the
register;
combinations
of
sources
and
a
destination
possible
and
second
(sources:
destination:
none,
first,
both,
on,
off;
of
not
all
these
combinations
are
the
source
and
useful);
destination
addresses
are
but
these
three
bits
always
computed,
whether
are
used.
The
determine
effect
of
the
source
data
they
of
is
determined
the
by the
programming
Viper
chips.

by the
eight

sequence
Adder
chip

The
for
first
the
source
and
the
destination
areas
origins
an
X
be
offset
the
addition
of
and
Y
a
index.
Index
mode
by
may
invoked
for
the
be
either
first
source
or
the
destination
may
X and
Y index
but
the
values
are
the
same
for
both.
independently
data
This
mode
allows
the
command
to
remain
unmodified
when
a
been
or
is
has
scrolled
scrolled
the
index
being
region
(only
need
to
be
the
of
a
values
and/or
be
updated),
origin
region
may
to
the
of
its
actual
location
in
0,0
regardless
update
process
the
bitmap.
<

All

complement
calculations
The

usable

address
numbers
will
range

computations
for

wrap
of
values

each
from

plus
for

the
and
to

any

Adder
Y.

chip
Beyond

minus
the

the

14
the
14
normal

use

bit,

two's

bit
limit,
fashion.
is
registers

DRAGON
VIDEO
OPERATIONAL

SYSTEM

HARDWARE

COMPANY

CONFIDENTIAL

page

DESCRIPTION

+/~
in

bits
(+/internal

because
4095)
calculations;

these
values
are
multiplied
by two
however
are
still
they
specified
as
14 bit,
two's
numbers.
13
bits
of
the
X address
complement
of
the
within
a
and
13 bits
(including
word)
specification
pixel
of
the
Y address
are
available
at
the
of
the
16
(in
output
chip
bus
bit
width
mode).
The
address
of
the
Adder
large
output
chip
is
to
allow
for
a
laser
which
provided
bitmap
writing
printer,
will
about
four
times
the
resolution
in both
X and
Y as
require
will
a
video
display.
some

<
A six
is
to
store
the
addresses
deep FIFO
provided
computed
before
are
used
in
this
allows
better
use
of
they
memory
cycles;
available
If
one
memory
cycles
during
scrolling.
only
destination
or
is
source
six
can
be
stored
required,
operations
two
more
can
(and
be
while
these
are
usually
computed
used,
being
so
that
at
least
8 operations
can
be
each
scan
performed
during
of
if
the
screen
format
if
scrolling
allows);
and,
source/destination
are
then
three
two
(or
operations
required,
for
double
source)
can
be
stored.
operations

the

functions,
computation

may
address

to
helpful
path
diagram,

Destination

3.5.1.1
The

and

discussion

following
it

signed

chip
the

computation
chip
5.
Figure
Adder

Rotation

destination

origin
integers

of
Adder
refer
to
shown

(see

parallelogram
6).

Figure
representing

Each
a

vector

horizontal

defined
is
delta

two

defined

vectors

(DX)

two

and

delta
both
vectors
(DY) and
start
at
the
same
origin.
is
scanned
the
of
one
by addressing
pixels
along
path
vector
fast
(the
from
the
destination
vector),
starting
origin
if
(after
until
it
is
and
selected),
indexing,
exhausted;
then,
the
next
on
the
of
the
other
vector
slow
(the
using
pixel
path
as
a
new
for
vector)
another
fast
vector
with
its
DX
same
origin
and
fast
vectors
are
scanned
until
all
of
the
on
DY;
the
pixels
slow
vector
have
been
addressed.
Thus
of
size
parallelograms
any
or
rotation
can
be
scanned.
can
be
used
to
scan
Parallelograms

vertical
The
area

rectangles
The
Bresenham's

screens

on
the
pixels
Algorithm.

having
path
Of

non-square
of
the

the
two

pixels.
are
vectors
components
is
generally

computed
(DX

and

by
DY)

of
a
slow
one
than
the
vector,
component
longer
and
is
called
the
the
shorter
is
axis";
"major
component
the
"minor
axis".
to
Bresenham's
the
According
Algorithm,
number
of
selected
the
of
a
vector
is
to
pixels
along
path
equal
the
of
the
axis.
The
and
all
to
length
major
origin
points
up
but
not
the
last
on
vector
(the
at
including
point
any
point
are
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DRAGON
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DESCRIPTION

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CONFIDENTIAL

page

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DRAGON
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DESCRIPTION

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the

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bus
these
of
this
as
an
modes,
output.
Both
words
of
the
can
be
the
are.
reduced
input
proportionately.
can
the
word
and
or
one
word
be
current
current
word
read,
being
of
in
one
two
the
a
word
held
other
delay
registers;
previous
to
avoid
the
latter
excess
fast
mode
ability
require
operations
is
associated
reads
One
to
the
source.
register
always
delay
and
the
other
with
the
second
with
the
first
source
always
shifter
can
be
directed
to
the
The
of
the
barrel
source.
output
to
bus
on
the
the
source
or
mask
I/D
Viper
chip and/or
registers
or
the
Adder
for
other
broadcast
to
the
chips
chip.
Only
Viper
bus
source
one
can
drive
the
I/D
during
any
operation.
Viper
chip

During

accepts

bitmap
memory
and
input

bit

read

cycle,

provides

For
the
first
the
shift
constants.
Adder
chip provides
difference
between
the
source
constant
is
the
the
shift
source,
X
2 bits
of
the
addresses
and
destination
(low
4, 3 or
pixel
if
for
the
second
after
addresses)
selected;
source,
indexing,
the
low
bits
the
difference
between
the
is
shift
constant
simply
X index,
if
selected
for
the
of
2 X Origin
and
the
the
Source
two
or
bit
is
set
to
bit
four
If
a
destination.
chip
Viper
one
or
two
bits
of
the
the
least
resolution
mode,
significant
are
truncated
in
that
barrel
shift
constant,
Viper
respectively,
a
from
the
bits
of
low
a
this
shifting
chip;
rasterop
prevents
or
than
a
bit
nibble.
resolution
less
pair
plane
by
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The

DRAGON
VIDEO
OPERATIONAL

SYSTEM
HARDWARE
DESCRIPTION

COMPANY

CONFIDENTIAL

page

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HARDWARE
SYSTEM
DESCRIPTION

VIDEO
DRAGON
OPERATIONAL

3.5.2.2

During
unit

bitmap

Mask

read-modify-write

memory

Registers
the

cycle,

logic

(loaded

location.
destination
memory
Any of
be
combinations
may
requested.
logical
for
on
a
unit
basis,
selects,
pixel
pixel
logic
form
new
destination
data.
color
to
background

the
The

constant

during

present

contents

content
a

preceding

the

source

with

the

bit-wise

possible
of

the

foreground
loaded
and
are
usually
registers
foreground
background
Z
or
a
axis
the
local
load,
using
ordinary
by
processor
Z mode
a
loaded
are
also
during
processor
implicitly
they
transfer.
bitmap
or

page

the

output

And

Source

CONFIDENTIAL

with

combines

And

Unit,

Logic

COMPANY

The

explicitly
load;
to

a
text
as
a
full
resolution
(such
When
pattern
using
binary
low
resolution
or
to
write
into
a
character
vector
plane,
path)
so
that
all
the
bits
it
is
to
spread
adjacent
pattern
necessary
is
either
on
or
off.
This
are
bits
of
a
low
resolution
"pixel"
source
mode
between
the
register
logic
by resolution
accomplished
or
bits
the
two
four
this
ORs
and
the
unit;
logic
adjacent
logic
if
that
of
the
so
and
four
bit
two
(in
modes,
any
respectively)
of
the
all
or
four
bits
a
"1"
then
two
bits
in
the
is
group
group
In
order
that
either
of
the
unit.
will
at
the
be
one
logic
input
there
is
a
can
be
so
in
the
source
the
ones
or
the
zeros
spread,
and
the
the
source
between
register
complementer
programmable
data
that
If
an
mode
resolution
moving
requires
logic.
operation
the
low
resolution
to
has
been
colors,
expanded
already
can
be
disabled.
mode
resolution
logic
<

which
bits
ina
to
control
are
provided
registers
loaded.
are
modified.
These
word
to
be
are
registers
1
the
mask
source
fashion
to
the
Loading
register.
data
same
so
2
with
the
loads
mask
also
the
register
register
loaded
2 may
be
mask
one
mask
is
that
effective;
only
a
value
mask
Hither
when
masks
are
two
required.
independently
the
A
mask
be
used.
(called
or
its
edge
special
complement
may
bus
via
the
Adder
I/D
is
mask)
during
chip,
provided
by the
of
a
word
bit
or
to
define
the
segment
cycles,
read-modify-write
words
All
of
mask
these
in
the
current
involved
cycle.
rasterop
three
masks
selected
bits
so
that
ANDed
are
by all
only
together
as
Adder
not
addressed
bits
will
be modified;
being
chip
by the
When
no
mask
is
be
modified.
cannot
a
the
of
in
rasterop
range
ones
and
both
loaded
with
all
1
be
mask
should
used,
being
bits.
of
destination
off
to
turned
masking
prevent
complementers
mask
1 and
for
both
1
mask
is
If
the
used,
complementers
only
the
will
all
bits
be
or
else
same
to
the
mask
2 should
be
set
state,
masked.
mask

Two

destination
in
a
similar

similar
bits
all

combined

The

that

according
of

together.
disabled.

the

bits
The

mode
are
masks
logic,
by resolution
processed
mask
which
ORs
the
for
the
used
source,
adjacent
This
forces
resolution
mode.
of
to
the
setting
to
be
modified
resolution
of
a
low
pixel
be
CANNOT
for
the
masks
mode
resolution
logic

wee

DRAGON

VIDEO
OPERATIONAL

3.5.2.3

HARDWARE
SYSTEM
DESCRIPTION

Control
To

provide

flexibility
Viper
chip

each
rasterops,
The
functions.
which
define
the
of
memory
cycle
1.

where

control
data
a

where

whether

the

has

two
RAM

store

send

the

send

incoming

I/D

the

read
the

capture
that

registers

each.
on

of
each

are:

from

I/D

its

6 locations,
be
performed

operations
define

that

provides

data

read

and

sequencing
memories

masks,

page

Registers

function
The
functions

transfer

rasterop.

(source,

CONFIDENTIAL

Function

And

RAM

Store

COMPANY

shifter

barrel

the

bus),

precedes

data

one

the

delay

shifter.

with
three
controls
data
a
1 read
of
source
the
control
(and
during
specifies
for
the
first
the
controls
second
source),
register
a
2 read
the
control
of
source
(and
during
specifies
and
third
for
the
second
the
source),
delay
register
the
destination
The
two
banks
allow
read-modify-write.
two
without
the
between
functions
switching
reprogramming
easy
must
with
when
a
function
that
be
(such
as,
Viper
chips
performed
is
executed
The
Adder
two
rasterop
chip
steps
repeatedly).
which
local
selects
bank
to
use
(as
specified
by the
processor)
also
defines
of
source
and
destination
accesses
and
the
sequence
2
if
source
source
and
is:
(the
1,
destination,
sequence
store
RAM
is
because
the
enabled).
The
control
required
Viper
for
often
do
different
at
the
same
time;
example:
things
chips
one
be
the
font
text
chip will
reading
during
operations
Viper
others
will
be
and
it
on
the
bus
while
the
I/D
transmitting
from
bus.
the
font
the
I/D
receiving
There
locations
transfers
the
delay
transfers
the
other
controls

two

are

each.

The

banks
first

control
location

data
barrel

and

masks),

(source,

store

RAM,

each

bank

of
earlier
It
is
not

the

control

NOTE
<

RAM

vestiges
required.

ever

the
used;
probably
Furthermore,

logic
bits.
bits
the

zero

delay
always

time

when

CSR

probably
contain

ever

store

and
that

design
clear

no
may
there
is
NOT

delay

control
in
the

enabled
there
is

destination
than

functions
of
an

the

longer
will

Some
are

bits
two
no

are

for

use
a

CSRs.

source

value

other

(NOP).

other
The
memory
and
mask
registers.
Four
bits
select
normal
or
select
last
two
bits
select

the

controls
This
a
logic
complement

normal

logic

unit,

source

four
for
function
for
each
of

locations
the
logic

complement

the

RAM

has

the
for

two

resolution
of
eight

unit;
masks,
source

two

and

DRAGON
VIDEO
OPERATIONAL

COMPANY

CONFIDENTIAL

page

and
enable
the
source
RAM
resolution
mode
This
logic.
addressed
the
Adder
as
by
chip during
rasterops,
local
These
processor.
registers
by the
permit
between
tasks
different
transitions
requiring
logic
as
normal
and
text.
Four
such
reverse
writing
allows
two
functions
to
be
programmed.
orthogonal

SYSTEM
HARDWARE
DESCRIPTION

also

specified
convenient
selections

registers

3.5.3

Transfers

Processor/Bitmap

(PBTs)

are
similar
to
rasterops,
is
the
local
destination
Processor
to
transfers
are
referred
to
as
bus.
processor
bitmap
and
to
are
referred
to
as
transfers
PTBs;
BTPs;
processor
Bitmap
to
PBTs.
All
data
for
of
either
are
referred
as
transfers
type
data
PBT
is
the
six
FIFO.
There
are
transferred
I/D
through
deep
X
Z
The
source
is
not
two
modes
for
mode
and
mode.
second
PBTs,
or
rotation
are
available.
no
available;
scaling

transfers

Processor/bitmap

the

local

word
and

(in

{there

data
from
16
bus
with
width
mode)
scans.

bits,

all
PBT,
(or
subplanes)
followed
word,

mode

planes

is
one
transferred
to/from
plane
in
X
one
bits
adjacent
occupying
X
additional
words
followed
by
In
4 bit
width
8 and
bus
modes,

significant

respectively,
Adder
by the

are

bits

pixel

location

to/from

performed

chip

build

words

nibbles).

and

bytes
In

packing

source

PBT,

processor
16 bit
bus
additional
by
low
low
8 or

from

the

mode

then
the

only

either

that

except

bus
processor
fast
vector
and
16 planes,
than
with
transferred

then

the

additional
16

additional
additional

from

one

transferred

are

additional

blocks
commands.

plane

PBT

data

along

system
blocks)

has

pixel

scans.

local

can

the

more
be

words
data
to/from
local
the
processor
data
words
are
a
DMA controller;
the
or
itself
through
the
of
the
hardware
written/read
along
path
by the
and
then
until
fast
destination/source
exhausted,
vector,
along
the
of
the
at
vectors
additional
fast
path
starting
points
along
on
the
in
usual
fashion.
the
slow
vector,
Depending
words
can
be
all
these
of
the
device,
transferring
sophistication
vector's
or
each
fast
in
the
local
processor
sequential
memory,
in
the
indexed
to
different
data
could
be
processor
points
of
to
a
action
could
be
used
access
latter
The
rectangle
memory.
in
local
formatted
data
a
within
already
rectangle
larger
an
is
such
externally
supplied
indexing
memory;
processor
of
the
Adder
not
a
function,
chip.
part
A

the

mode

PBT

local

transfers

continuous
either

executing

general,

horizontally
on
depends

are

PBTs

restricted

scrolling
the
alignment

because
of

through

while
from
the

the

stream

memory,

processor

scrolling
use

number

rectangle

possible.

is
that
region
of
words
transferred
transferred
being
a

DRAGON
VIDEO
OPERATIONAL

the
mode
<

words,

memory
transfers

SERENE
some

HARDWARE
SYSTEM
DESCRIPTION

which

changes

restrictions

have

PBTs

scrolling

part

the

screen

SREY
continuously,

requirement

DMA

scrolling
the

can

only

controller.

section

see

location

screen

operate
words
address
and
data

will
this

Generally

uninterruptable
for
problem

such

information,

location.

screen

wrong
be
met

There

For

SRI memory.

transfer

page

horizontal
during
scrolling.
scrolling.
during

in
on
(or
any
down
must
scrolling)
a
maximum
time
between
becomes
delayed,
will
become
invalid

the

to/from

CONFIDENTIAL

region
is

adhering
If
for

transferred.
Men
ND calculations
NE transfer

COMPANY

processor
in
off

PBTs

screen

4.1.2.3.

SiO
LEE

It
is
recommended
that
local
the
processor
compute
exactly
number
of
will
words
that
be
transferred
with
a
PBT
command
the
Z mode
hardware.
For
a
will
this
be
the
transfer,
simply
width
times
the
(in
of
the
area
transferred;
height
pixels)
being
for
X mode
a
the
width
will
be
calculation
on
transfer,
dependent
the
width
the
(in
bus
width
and
the
xX
mode
indexed
pixels),
If
address.
exact
not
calculations
are
too
much
origin
possible,
local
data
is
accommodated
additional
reads
processor
by harmless
or
writes
to
the
if
too
little
data
is
FIFO;
however,
Adder
the
not
be
a
transferred,
satisfied,
chip will
requiring
cancel
command
more
to
continue
(or
data)
The
operation.
ability
a
to
cancel
BTP
is
if
useful
the
local
operation
particularly
wishes
to
scan
the
data
for
a
set
of
processor
bitmap
particular
when
such
is
this
is
useful
for
a
values,
found;
stopping
polygon
flood
operation.
<

ENE the
by
Le

ee
es

3.5.4

Performance
When

Single
they

operate

Rasterops

operate
format).

width.
initialize

bus

approximately

500K

with

whether

they
Four

each

are

two

400K

compute
rasterop.

cycles

(compute

are

cycle

memory

for

8
are

Adder

the

cycles/sec

cycles/sec
single

either
the
conditions
either
4,
on

bound

sources

and

destination-only

progress,

compute

approximately
Cycles
operate
on

in
are

rasterops
at

rate).

depending
are
possible,

scrolling

source

(depending
or
pixels
fast

bits,
required

screen

words

depending

the

and

bound,

exist;

mode

chip;
cycle

Adder

words
the

chip

the
whole
screen
is
or
or
area
scrolling
up
sideways,
any
all
are
bound.
scrolling,
rasterops
memory
cycle
at
300K-400K
Destination-only
rasterops
operate
cycles/sec,
source
at
200K
rasterops
operate
single
approximately
cycles/sec,
and
two
source
at
150K
rasterops
operate
approximately
all
on
the
screen
format.
cycles/sec;
depending
Partially
screens
down
will
have
scrolling
(except
scrolling)
update
speeds
the
intermediate
between
and
full
non-scrolling
scrolling
speeds.

If
down

There

one

additional

performance

limitation

that

applies

DRAGON
VIDEO
OPERATIONAL

SYSTEM

HARDWARE

COMPANY

CONFIDENTIAL

page

DESCRIPTION

that
in motion
is
or
region
(scrolling)
any
in
is
when
the
scrolling
progress.
Normally,
screen
and
an
area
on
the
screen
process
passes
scrolling
where
are
source
data
is
(or
updates
read),
taking
place
being
the
is
halted
while
the
refresh
update
process
temporarily
to
ensure
that
old
indexes
are
used
below
the
process
passes
only
and
new
indexes
are
used
this
above;
process
only
refresh
is
the
because
address
cannot
computer
predict
necessary
a
when
address
will
be
to
the
precisely
computed
memory.
output
this
in update
causes
unnoticeable
decrease
an
Normally
speed;
if
the
is
down
the
screen
however,
update
process
proceeding
faster
than
the
refresh
can
if
fewer
than
(this
process
happen
about
8 memory
on
screen
are
format,
cycles,
depending
required
to

updates

when
refresh

region

down

delay

write

read

vectors),

all

data

the

update
process
thereby
limiting

process,
process.

eliminate

skinny
portion

rasterops,
of
than

rather

the
screen
from
top

(or

bottom.
disabled

if
equal
they are
and
Y offset
the
is
this
limitation
does

unchanged
not
apply.

3.6

Text

Application

not
to

effect,

regions
height,
to

each

progress

this
in

will

vertical
address,
eg.
be
able
to
the
refresh
pass
that
of
the
refresh
it
is
recommended
that
tall,
Y

is
whose
a
height
significant
be
written
from
to
bottom
top,
When
the
new
and
old
indexes
for
both
source
and
destination)
from
of
that
the
frame,
previous

are

Normal
are
used
to
write
The
characters.
Adder
rasterops
no
in
contains
additional
hardware
to
assist
the
of
chip
display
but
much
of the
standard
hardware
described
was
text,
already
This
will
section
describe
common
inspired
by text
requirements.
text

procedures.

3.6.1

Font

Storage

And

Access

in
an
stored
of
the
undisplayed
portion
bitmap.
in
font
be
stored
one
and
is
need
only
plane
to
itself
and
a
from
that
others
when
character
transmitted
plane
in writing
in
will
result
characters
the
is written.
This
bitmap
of
one
color
and
one
that
are
monochromatic
(all
foreground
as
If
multi-colored
or
is
desired.
color),
normally
background
characters
are
then
the
(for
desired,
anti-aliasing)
gray~scale
RAM
across
Some
extra
will
fonts
can
be
stored
many
planes.
in
for
the
off
screen
of
the
be
available
portion
bitmap
normally
RAM
if
ROM or
additional
is
can
soft
this
fonts;
but,
required,
X and
Y address
bits
be
because
there
are
more
added
to
a
plane
are
for
a
full
ROM storage
than
mene available
needed
page
display.
if
a
is
of
is
forward
fonts
in
the
neem
bitmap
straight
only
product
in
or
if
ROMs
to
one
bus
width
mode
ete restricted
separate
operation
ee
are
for
each
this
is
due
to
the
different
mode;
mapping
provided
of
bits
in
bus
width
modes.
address
the
various
data
and
cen
Fonts

Ordinarily,

are

DRAGON
VIDEO
OPERATIONAL

HARDWARE
SYSTEM
DESCRIPTION

COMPANY

CONFIDENTIAL

page

in
Characters
be
stored
the
(though
may
anywhere
bitmap
in
off
take
screen
a
character
does
however,
normally
memory);
up
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dimensional
in
a
the
described
height,
space
memory,
by
width
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an
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Y origin.
in
font
the
Thus,
memory
storage
must
be
in
the
allocated
a
two
dimensional
fashion.
Normally
in
font
local
will
a
for
the
each
table
characters
processor
keep
where
it
can
look
and
While
character
their
widths.
up
origins
will
be on
faster
may
origins
any
pixel,
operation (20-30%)
if
word
result
characters
left
in
are
justified
bitmap
memory
will
be
cells
8 or
4 bit
because
(16,
words),
only
shifting
in
fewer
source
reads.
required,
resulting
<

left

Normal

3.6.2

use

only
be

Text

The
display
the
following
those
settings

The

The
data

resolution

source

The

Viper
chip
(possibly)

Adder

functions,

logic

and
character

desired

the
of

attributes,

chip

mode

index
1

source

on,

origin

first

to
character
bits
rest
(the
sign
direction
of
source

destination
origin
location
for
the
DX is
destination
fast
of
the
character
direction
to
The
destination
0.

The
fast
factors

set

character
all
other

proper

data

planes.

background
for
further

set

are

(see

initialized

off,

as:

index

source

set

and

the
the

significant)

start
DX and
set

are

and
one.

the

for

the

height

slow

scale

the

set

slow
and

is
set
to
the
desired
The
character.
the
width
to
and
fast
set
and
DY
is
the
fast
cells,
DX is
the
slow
set
to
0, and
slow
direction
of
the

and

first

cells.

off,

down.

pen

not

scanning.

screen

is
character

fill
and

Y)
(X and
transferred,

The

the

attributes

the
the

Normally

foreground,
registers

mask

for

set

below).

hole

normal,

destination
The

Limits,

clipping

are

The
and

rasterop

RAMs

store

the
during
rasterop.
of
enable
broadcast
the
font
containing

discussion

with

transfers
would
settings
from
the
plane

chips;
need

mode.

control

chip

Viper

initialized

region
and

some

text

Viper

initialization:

update

indexes

could

fixed-pitch
the
Adder
and
between
characters

unscaled,

unrotated,

in
example
settings
actually
changing

following

updated
1.

registers

are

set

for

scale

DRAGON
VIDEO
OPERATIONAL

each

SYSTEM
HARDWARE
DESCRIPTION

The
following
in
character

The
the

with
bank
2.

Adder
fast
using

could

operations
string:

local
processor
Adder
to
chip
desired
the
selected.

The

COMPANY

chip

would

now

mode

start

logic

unit

copies

(because

CONFIDENTIAL

now

load

the

performed

rasterop

source

command: register

function

the
there

write

l/destination

source

the

rotation

page

and

CSR

destination
or

scaling).
3.

After
for
the
Adder
to
finish
the
waiting
chip
initialization
of
the
but
while
the
phase
rasterop,
is
character
still
the
local
written,
being
processor
can
reload
source
and
destination
and
the
the
origins
command
the
same
as
the
so
that
(if
command),
previous
the
next
character
will
start
immediately
upon
of
the
first.
completion

This
an

process
attribute

is
repeated
is
change

until

the

text

exhausted

required.

of
in
varies
with
The
text
this
mode
the
speed
writing
on
a
for
9 wide
cells
16 bit
character
but,
size;
bus,
by 15 high
can
be
if
20K
about
chars/sec
written,
fully
supported
by the
15K
The
will
from
to
25K
local
chars/sec
speed
range
processor.
a
full
screen
for
other
useful
character
sizes.
Because
page
fill
6000
300
msec
will
be
to
contains
about
characters,
required
100
to
screen
with
about
msec
clear
the
the
characters.
Adding
an
text
but
that
screen,
average
page
really
only
considering
will
be
about
3000
about
250
msec
contains
characters,
required
of
if
the
local
for
a
"new
text.
Obviously,
page”
average
as
is
not
able
to
characters
as
fast
the
processor
process
will
determine
the
hardware
can
take
then
the
them,
processor
overall
performance.

Variable

3.6.3

Pitch

Text

wishes
use
it
to
local
may
any
technique
processor
fixed
is
character
the
Obviously,
spacing
spacing.
compute
can
be
used
to
useful
in many
Variable
spacing
applications.
extra
over
the
of
text
a
line
pixels
by spreading
any
justify
find
number"
is
to
the
"real
one
such
line;
(integer
computation
for
each
character
and then,
and
of
(or
fraction)
space),
pixels
for
number
each
character,
of pixels,
integer
by the
plus
spacing
have
accumulated
to
more
than
one
if
the
fractions
more
pixel
allows
but
otherwise
one.
also
This
any
non-integer,
algorithm
be
useful
for
simulated
to
be
(as
fixed,
may
compatibility
pitch
with
when
the
dot-matrix
dumping
bitmap).
printers
The

DRAGON
VIDEO
OPERATIONAL

SYSTEM
HARDWARE
DESCRIPTION

variable

for

font

pitch
each

COMPANY

would

with

displayed

(read

character

CONFIDENTIAL

page

different
from

its
by
processor
width
This
be
table).
the
may
accomplished
by changing
destination
and
fast
DX or just
the
destination
origin
origin
alone.
The
former
mode
allows
the
font
to
be
stored
compactly,
with
the
characters
their
width
in
the
only occupying
memory;
the
will
be
somewhat
reduced
because
the
local
but,
speed
must
wait
for
the
to
be
processor
previous
rasterop
completed
before
DX register
the
and
a
new
reloading
starting
rasterop.
The
latter
mode
allows
the
same
of
as
fixed
speed
operation
pitch
but
the
characters
would
in
need
to
be
stored
text,
probably
cells
the
size
of
the
character
so
that
of
largest
portions
unwanted
characters
would
not
be
to
the
of
course
screen;
copied
some
loss
of
will
result
from
If
areas.
speed
copying
larger
of
variable
is
characters
care
overstriking
pitch
performed,
should
be
taken
to
center
smaller
on
characters
of
the
top
and
to
to
the
next
character
the
one,
largest
space
by
largest
space.

spacing

destination
between
could

writing

the

local

character
of
character
pitch
any
DX setting,
fast
care
must
be
that
is
characters
not
covered
by
be
done
the
area
of
the
by clearing
the
character
string.
.

The

of
fixed

variable

for

And

Scaled

Text

performance

described

above

3.6.4

the

Rotated

pitch

rasterops.

text

line

text

than
the

larger

taken
the

clear

that

degree
and

axes

before

similar

rotated

want

text

shown

that

text.

of
the
the

may

area

This

rotated
or
scaled
text
is
similar
normal
to
destination
and
fast
slow
vectors
need
not
X and
Y axes,
to
and
the
scale
parallel
respectively,
need
not
be
one.
The
execution
of
a
defaults
to
rasterop
a
For
a
at
time.
rotated
text
the
cell,
pixel
rectangular
DY are
DX and
to
be
the
chosen
closest
to
the
integer
pair
and
desired
size
of
(the
angle
magnification
images
along

Display

except

the

accounted
in
Figure

for).

example

text

be
factors
one

fast
45
the
scaled

ll.

<
To
of
insure
an
base
real
line,
proper
tracking
arbitrary
destination
could
be
made
in
the
manner
discussed
origin
updates
for
variable
but
with
an
and
fractional
text,
pitch
integer
part
X and
both
Y that
to
the
for
correct
base
line
correspond
angle.
will
Use
of
real
allow
of
position
updates
accurate simulation
or
scale
of
a
fixed
orientation
text
the
any
pitch
string;
characters
will
be
within
one
of
their
intended
pixel
position.

The

performance

characters/second

Using

pixels/character.
3.5.4,

these

of
text
because

characters

scaling
of

figures
will

be
expressed
number
of

cannot

the

varying
provided

written

sections

500K

pixels/sec

2.2.3

terms
or

and

DRAGON
VIDEO
OPERATIONAL

SYSTEM
HARDWARE
DESCRIPTION

This
JAis

This

COMPANY

CONFIDENTIAL

NORMAL text.
L7ALIC text,

is
is

1.3

SCALED

Text

Scaling

SCALING.

italic

2,4

and

Rotation

Figure

Examples

page

DRAGON
VIDEO
OPERATIONAL

will

take

3.6.5

1.7

840K

character

registers

attributes

COMPANY.

pixel

CONFIDENTIAL

page

screen.

Attributes
the

set

fill

sec

Character

chip

SYSTEM
HARDWARE
DESCRIPTION

attributes,
all

loaded;

are

Adder
and
appropriate
retain
the
current

characters

Viper

until

registers
strings
is

being
periodically
following

the
are
the
However,
settings
changed.
only
those
attributes
that
between
actually
change
to
be
if
a
list
loaded;
although,
permanent
display
it
be
desirable
to
reset
all
attributes
maintained,
may
of
each
The
line).
(maybe at the
beginning
list
describes
the
intended
of
implementation

for
need

attributes:
1.

Reverse

a
case
of
a
more
specific
general
that
modifies
the
function
logic
on
the
destination
Two
data.
bits
are
being
performed
in
the
Adder
word
to
address
one
provided
chip command
of
the
four
unit
function/mask
logic
complement
in
the
These
function
registers
Viper
chips.
registers
could
be
set
to
the
current
definition
of
reverse
and
some
other
function
as
(such
mode
from
switching
replace
to
overstrike
mode).
-

class

Reverse

attributes

—

Underline
desired

Underlines
thickness
and
-

can

drawn

linear

pattern

vector
can

desired.

dashed
or
other
underline
patterned
Another
would
be
to
overstrike
technique
with
another
character
an
containing
a

Overstrike

must

care

Invisible

The
be

may

processor

can

invisible.
this
5.

Intensity,
and

are

writing
subplanes,

each

the
used

up
to

and

character

underscore.

Adder

chip

writing,
strings

are

area

desired,

explicitly.
Blink

load

These
the

color
in
the

are

map.

axis

parameters
To

enable

or
bitmap
planes
chip
foreground
with
accomplished

the
Viper
and/or
would
be
background
registers
Z axis
bus
this
will
set
all
I/D
of
the
F/B
command;
in
bits
each
or
to
either
ls
or
0s.
plane
subplane
Source
would
then
be
loaded
the
(via
patterns
Viper
a
into
mask
CSRs)
to
Viper
chip
register
accomplish
overstrike
or
into
the
source
to
writing,
register
a

mode
the
local

that

invisible

the

implemented
through
the
color
appropriate
axis

the

text

any
of

performed

Color

bit
in
disable

skip

erasure

may
NOT

(or

pen
used

just
If

must

accomplished
by
destination
loading)
of the
of
the
use
"OR"
modes.
writing
from
variable
fonts
are
overstruck,
pitch
in
be
taken
positioning.
-

appropriate
loading
and
origin
register
characters

mode

DRAGON
VIDEO
OPERATIONAL

SYSTEM
HARDWARE
DESCRIPTION

mode
replace
by periodic

accomplish
performed

Italics
is

Size,

COMPANY

writing.
writing

Rotation

and

3.7

patterns

3.7.1

Points

functions

Additional

use

the
add

fill

polygon

(monochrome)

color

with

loaded
fast
both

equal

drawn

single
to

can

to
one

processor

command;
avoid

required

are

may

Support

introduced
additional

above.
features.

the

desired

rasterop

pixel

addressed

permitted
always

read
to

while

even

accommodate

are

destination

origin

bitmap
by using
This
pixel.

mode

one

because
words

scrolling
one

chips

color
(usually
location
the
is
the
destination
of
one
(DX, DY
is
loaded.
The

the

The

operations.
the
Viper

command
by the

from
address

plotted

are

point,
registers,
with a length
For

the

be
may
transfer

vectors

source

six

the

without

deep
being

local
While
a
PTBZ
could
be
used
to
processor
delays.
this
is
not
while
because
the
possible
pixel,
scrolling
not
the
data
after
the
PTBZ
might
supply
quickly
enough
the
described
is
above
recommended
single
pixel
rasterop
Because
of
the
this
overhead
problem.
computational

initialize

write
many
a
discussion

pixels
of

Figure
described

the

pixel

subject

and

processor

FIFO

write

one),

and

any

axis
bus
I/D
command).
into
the
destination
origin
and
slow
vectors
are
loaded
to

features

registers

is
point
registers.

data

factors,
update,

Graphics

some

points

parallelograms,
foreground/background
with
constants
according

fast

Vectors

bitmap
operation

origin

And

without

loaded

and

destination

slope

Graphics

and

And

Solid

graphics

Most

Linear

source

italic

These
character
offsets
Superscript
obtained
of
the
destination
by appropriate
loading
In
this
sub
and
origin
registers.
way,
superscripts
be
nested
and
baselines
be
accounted
for.
angled
may

Application

specific

may

bitmap.

the
destination
slow
scale

fast

page

blink
Alternately,
the

size,

setting

and

Subscript

Any

rotation
available
by
and
slow
vectors
and
the
and
providing
appropriate
discussed
above.
7.

CONFIDENTIAL

rasterop
if
time,

applicable

PBT,

12
shows
for
the
examples
the
following
paragraphs.

is
See

possible.
techniques.
various

best
section

vector

types

for

DRAGON
VIDEO
OPERATIONAL

SYSTEM
HARDWARE
DESCRIPTION

Single

COMPANY CONFIDENTIAL

Width

Broad

Vectors

Figure

page

DRAGON
VIDEO
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For

point

width
the
into

single

HARDWARE
SYSTEM
DESCRIPTION

loaded

COMPANY

fill

hole

vector,
destination

CONFIDENTIAL

origin

the
the

disabled,

registers,

fast
vector
is
set
length
DY of
the
desired
the
command
rasterop
The
loaded.
destination
point
by the
initially
are
is
as
but
drawn,
({X0,YO])
to,
points
up
DX
the
the
and
[XO+DX,YO+DY].
including,
point
Loading
the
fast
rather
than
the
slow
is
vector,
vector,
preferred
that
horizontal
vectors
can
take
of
fast
mode
advantage
written
rather
than
single
pixels).
vector
DX and

set

the
one,
and
vector,
addressed
all
of
the

page

start

slow
the

origin
not

into

(words

is
the
set
would
be
the
same
desired,
up
fill
on
and
load
a
slow
with
a
vector
except
length
to
the
thickness
and
a
direction
to
equal
perpendicular
the
fast
vector.
Care
must
be
taken
at
corners
to
prevent
gaps
in
the
between
vectors.
with
(seen
figure)
Gaps may be filled
to
the
and
of
the
vectors;
appropriate
adjustments
origin
length
a
be
to
each
vertex
to
the
“vertex
cover
or,
shape"
may
copied
of
Simulation
the
area
traced
brush
gaps.
by a rectangular
may
be
each
vector
into
two
accomplished
segment
by decomposing
of
with
with
one
to
the
side
the
parallelograms
edge parallel
brush
and
to
the
the
other
edge parallel
path.
If

broad

Curves

vector

hole
desired

turn

formed

must

from

string

straight

vectors

points.

3.7.2

Shading
Vectors

stripes)

or
a

provide
of
path
Linear

tile

two

(Figure

ways

set
for
linear
first
source
linear
dashed
(like
patterns
with
the
that
themselves
align

mode
bullets
of

lines,
direction

are

linear

second

set

source

that

are

for
tile
"uncovered"

mode
under

pattern

registers
(the

will
the

vector.

initialization

(slow)
pattern

created

mode;
from

define

by
this
each
the

of
size

the
setting
uncouples
The

other.

size

and

Adder
the

magnitudes
the
mode);

(fast)

source

scanning

mode
and

chip
source

direction

DX and
DY registers
the
of
the
source
in
this
pattern
significant
or
The
fast
slow
directions.
in
either
the
any
integer
destination
slow
vector
defined
vector
is
patterned
by the
the
destination
fast
vector.
width
of
the
vector
by the
normal
or
in
the
slow
be
used
manner.
scale
factor
may
in
fast
mode.
never
patterns
operate

the

shows

pattern

patterns

the

patterns
to

destination
and
for

one

Patterns

vector.

Inclusion

Tile

And

types):

Inclusion
of
will
provide

Linear

shaded

may
both

examples

Vectors

ARE

can

path
and

Any
Linear

fast

VIDEO
DRAGON
OPERATIONAL

SYSTEM

HARDWARE

COMPANY CONFIDENTIAL

page

DESCRIPTION

Joorneeintigg..
a

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DRAGON
VIDEO SYSTEM
HARDWARE
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DESCRIPTION

COMPANY

CONFIDENTIAL

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DRAGON
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COMPANY

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DRAGON
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SYSTEM
HARDWARE
DESCRIPTION

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HARDWARE
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VIDEO
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the
see
the
but
memory
chips
Viper
chip,
only

flood

Flood

can

scan

processor/bitmap
of
the
bitmap

bitmap

each

returned

set

when

scan

with

the

flood

scan

normal

command

commanded
color
or

plane

transfer
Adder

the
the

write

pattern

continue

then

for

the

BTP
to

would

algorithm
or

one

used
of

the

with

the

terminated

chip,

desired
normal
to

step

seed

match

maintained

count

the

found,

cancel

vector

facility
or

checked

and

colors,

match

mode

value

pixel

commands:

following

transfer

page

mode,

boundary
received,

pixels

the

using

implemented

local

the
read

CONFIDENTIAL

COMPANY

HARDWARE
SYSTEM
DESCRIPTION

DRAGON
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OPERATIONAL

pixels

the

fashion.

point
point,

the
the

manner.

determined

BTP
by the
local
processor
2 usec
for
each
than
takes
more
it
(which
The
time
if
flooded
area
is
narrow).
or
the
drawing
comparison
and
to
decision
not
is
scanning
compared
significant
generally
of
if
the
outline
is
If
a
one
used,
Dragon
system
plane
making.
or
if
the
in
a
is
described
area
flood
the
boundary
single
plane,
with
an
be
scanned
can
the
described
is
color,
bitmap
by a single
16
bits
(or
to
X mode
transfer,
checking
thereby
processor
bitmap
an
this
on
each
the
width
of
bus)
the
transfer;
technique,
using
in
less
than
been
flooded
x
has
screen
864)
full
(1024
page
empty
2 seconds.

The

speed

scanning

time
could

3.7.5

Objects
Ordinary

the

can

rasterops
In

screen.

is
time

of
this
operation
the
overhead
plus
if
be
significant

used

the

move

environment,

multiplane

objects
rectangles
in parallel,

in
all
the
planes,
pixels
referred
This
is
in
the
same
locations
planes.
is
of
a
all
move
because
raster
copied.
rectangle
on
from
either
so
be
and
and
offset
indexed
is
may
from
off
screen.
it
must
be
2 is
used
If
a
source

copied
[X,Y]

moving

just
pixels

move

destination
necessary

for

background.
in
object
rectangle

one

rasterop

background

is
for

the

to
hardware
can
be
done
area
The
plane.
then
transmitted
mask
that
as
a
use

the
This

pixels.

This

The
or

can

new
a

source

off

screen.

the
only
it
is
object,
boundary
and
between
object
distinguish
the
of
the
foreground
by defining
within
the
of
this
rasterop
plane
the
other
to
the
during
planes

that

object,
within

windows

operation

prevents
is

alter
the

the
referred

alteration
to

object

DRAGON
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SYSTEM
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DESCRIPTION

move.

Alternatively,

object

from

off

the
screen,

second

with

CONFIDENTIAL

COMPANY

source

can

"clipping"

be
the

used
to
destination

page

copy

shape.

two
the
movement
of
color
The
described
previous
paragraphs
in more
It
is
defined
than
one
objects
(objects
plane).
also.
a
to
move
monochromatic
(ones
possible
objects
specified
by just
a
and
color
to
background
foreground
shape),
assigning
foreground
has
them
at
the
time
that
are
moved.
This
of
type
operation
they
been
for
of
described
the
text.
already
writing

DRAGON
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COMPANY
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AND
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page

COMMANDS

AND

REGISTERS

CONFIDENTIAL

local
interface
from
the
processor
and
in. detail.
General
concepts
are
in
There
introduced
section
3.
were
basically
terminology
to
the
commands
hardware:
direct
two
of
commands
to
the
types
the
that
are
and
bus
commands
Adder
I/D
passed
chip,
through
devices.
bus
to
and
other
Adder
the
I/D
Viper
chips
chip,
to

the

This
section
Adder
and

Adder

4.1

defines

Chip

All

chips

chip commands
local
by the

presenting
to
define

appropriate

Adder

4.1.1

Chip

the

are

Adder
external

result
or

processor

commands

Adder
chip
Adder
the

the

Before

Commands

And

Registers

Adder
loads

the

Viper

chip

and

chip
DMA

interface,

device.
it
is

registers.

Registers

hold
that
Adder
loadable
registers
many
chip contains
and
control
the
set
for
timing,
system
rasterops,
are.
otherwise
Unless
of
the
specified,
chip.
bits
14
contain
and
numerical
write
significant
registers
only
for
word
are
MSBs
of
a
two
the
except
ignored,
(including
sign,
The
in
two's
test
loading
representation.
complement
purposes)
to
be
taken
actions
additional
causes
some
of
specific
registers
described
with
the
will
be
actions
Adder
these
chip;
by the

The

parameters
operation

registers

corresponding
There

different

are

various
position
of
the
coordinate
system
index
values
before
(if
coordinates"
to
"device
on
the
screen;
position

registers.

increasing
coordinates"

by
part
read

major
and

allow
allows

The
of

memory

for

the

screen

the

processor
the

image
physical

left
corner
with
downward.
"Memory
increasing
to
account
for
down
internally
to
the
on
all
addresses
offset
to
location
accessed
by a
(any memory
X limit
the
delineated
refresh),
by
is

the

upper

and

registers

combinations

common

loads

be
the

loaded

may

address
the

registers,

all

"[0,0]

coordinates
implied
refers
coordinates"
local
the
viewed
by
to
translate
are
added
describe
coordinates

registers.

Because

through
sequential

the

cycle

limit

Device

right

adding
of

image

enabled)

obtained

are

scrolling
screen

the

of
"World

types

counter,

device's

data

addresses
in

HEX

minimum
list.
of

address

(or

the

and

enclosed

to
a

assigned
adjacent;

are

registers

accomplished

controller
several
loading

DMA

addresses

with

DMA

by
thereby

[],

the

this

address

first

precede

of
the

—

DRAGON VIDEO
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CHIP

descriptions
register
(or
assignments

the

page

COMMANDS

AND

bit

CONFIDENTIAL

COMPANY

HARDWARE

SYSTEM
REGISTERS

list.

following
of

LSB

Where

bits)

group

specified,
in

enclosed

are

<>,

C0]

4.1.1.1

Interface

ADDRESS

COUNTER

Control

(ADCT)

provides
for
registers

This

indirect

that

Registers
controls
Adder
controller.

address
to
the

access

counter

chip

If
DMA
the
standard
is
a
0
when
this
is
data
word
the
MSB of
register
to
in
the
is
the
data
pointed
written,
register
placed
and
the
counter
is
then
of
the
contents
counter,
by the
1 when
this
data
is
MSB of
the
If
the
incremented.
bits
of
the
data
low
six
the
is
written,
register
the
address
counter.
of
contents
the
original
replaces
if
the
address
counter
is
is
The
that,
only
exception
or
the
Data
the
(IDD)
either
to
I/D
register
pointing
of
the
data
is
MSB
the
Data
Scroll
I/D
(IDS),
register
all
16
bits
are
and
address
the
decoding
by
ignored
When
a
read
I/D
into
the
loaded
register.
appropriate
the
address
to
the
directed
is
counter,
register
pointed
and
the
counter
is
is
accessed
counter
address
to
by the
a
that
few
incremented
(note
only
subsequently
always
is
The
counter
readable).
are
actually
registers
is
asserted.
-INIT
the
when
cleared
pin

REQUEST

(2]

INTERRUPT

ENABLE

The

unencoded
the
of

ENABLE

(INT)
bits

enables
a

registers,
will
register
cleared
by assertion

and

bit

the
or

these
in
the

bit

status

registers
Adder

the

enable

Both
-INIT

one

corresponding

asserted.
of
the

any

status

request

enabled

output

either

bit;

that

and
the

one

status

a
one

bits
the

assert
A

allow

registers

two

these

pins.

output
is

corresponding
enabled

(REQ)

C1]

selection

use

chip.
The

data

control

present
DMA

request

requests
the

controller

local
would

request

conditions

for
word.

specific

event

The

control

interrupt
interrupt

DMA

processor's
probably
at

one

pin
requests

time

[In

set

one

only

the

are

local

be
the

may

general,
of

will

passing

that

because

before

and

provided

are

controller
bus.

these
be

provided
processor.

waiting
data

canti

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will
interrupt,
processor
the local
determine
the
register
to
if
more
than
is
one
condition(s),
interrupting
interrupt
enabled.
the
and
Actually
request
interrupt
functions
are
if
a
DMA controller
is
so,
implemented
identically
both
be
not
used
as
used,
outputs
may
separate
interrupt

After
need

of
the

receipt
read

status

requests.
(3]

STATUS

(STAT)

indications
The
conditions
identified
readable
<0>

The
status
various
register
provides
of
the
internal
the
Adder
progress
chip.
that
set
and
clear
bit
are
each
the
list.
This
is
following
register
as
noted
below).
(except

of
in

only

Pause

the

began.

Cleared

with

unaffected
values
two

when

(in

by
of

other

events;

pause

the
screen
refresh
process
device
that
coordinates)
was
when
set
to
the
current
frame
a
word
to
the
status
by writing
zero
at
this
bit
position;
this
one
at
bit
or
position
by
This
status
bit
will
bits.
queue
in one
if
frame
the
thus,
pause
Set

address

Complete

reaches
the
pause

set

was

the

near

bottom

the

and.

screen

frame
the
was
set
near
pause
register
both
events
will
the
be
screen,
pause
detected
local
even
“separately
by the
processor
if
before
the
first
the
second
event
occurs
event
is
if
this
means
the
detected.
that,
However,
pause
the
active
and
is
set
within
screen
the
register
bit
has
not
been
cleared
within
the
status
pause
will
be
two
two
clears
to
frames,
previous
required
make
this
status
bit
low.
The
status
bit
stay
pause
from
set
can
be
the
being
by programming
prevented
a
value
than
that
of
the
to
register
greater
pause
in
the
YCTvertical
event
end
(see
period
registers
-INIT
The
clear
section
4.1.1.5.
pin will
any
but
one
clear
event,
explicit
queued
pause
by
is
the
status
still
to
to
writing
register
required
bit
low.
set
the
status
pause
<1>

top

(Frame

Scroll

Service

frame,

when

new

Cleared
with

writing

this

This

bit
latter

the
be
may

Set

parameters
a

word

bit

this

bit
position
differs
from
the
set
at
is
the

the

initialization
transfer
safe
to

Initialization

unaffected
values
of
Vertical
Blank
of
the
beginning

(PBT)
load
or

Complete

complete,

the

source

load

rasterop
1
a

new

Set

by
other
bit

bits.

in
vertical

that

when

processor/bitmap
it
that
indicating
and
destination
origin
or

(but

not

loaded.

status

position;
or
by

start

interval.

Rasterop

registers,

Sync)

scroll

zero

one

the
blank
<2>

the

different)

DRAGON
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(but

rasterop

<3>

indicating
parameters
2 parameters,

rasterop
source

rasterop

(but

<4>

such
scale

as:

any

Address
Complete
Output
calculated
by all
pending
that
been
used,
indicating

update

parameters

indexes,
addition,

I/D

safe

DX/DY

all

addresses

safe

(bitmap

ANY

boundaries,
In

commands,

processor)

have

load

commands.

BTP

4.1.2.2.
loaded.

PBTs

clipping

different

mode

section

pairs,

the

different)

rasterops

including:

during

address
command
is
load
any
PBT

and

when

4.1.2.2.
loaded.

PBT
command
-INIT
the
pin.

Set

data

origins,

command

cancel

further

factors,
not
new
(but
command
(see

PBT)
rasterop

not

section

rasterop
no

page

command
PBT
-INIT
the
pin.

when
and

that

load

when

Cleared

complete

are

pending,

Set

(see

command

Complete

Rasterop
calculations

Set

any

cancel

PBT)
rasterop

not

when

Cleared
Set

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IDD
FIFO
the
will
not
bit
status
this
high until
go
data
transferred
all
that
is
also
indicating
empty,
local
has
been
BTP
processor
up
by the
picked
by the
PBT
or
when
Cleared
DMA controller.
or
rasterop
any
the
or
a
cancel
loaded.
Set
is
command
command
by

~INIT

<5>

pin.

if
set
the
bit
is
I/D
This
it
for
available
word
reading;
When
a
becomes
FIFO
if
the
empty.
the
loaded
to
is
command
PBT
or
cancel
rasterop,
the
initialization
bus
or
occurs,
command
register,
will
be
cleared.
bit
and
this
initialized
FIFO
is
is
data
time
that
set
will
be
bit
this
Note
that
any
command
PTB
or
I/D
as
such
in
the
FIFO,
during
not
when
used.
masked
be
and
should
sequences,

I/D

Data
FIFO

Receive

Data

Transmit

has

data
cleared
is

<6>

I/D

Ready

When

the

rasterop
will
this

command,

PBT

the

bit

This
Ready
on
depending
Adder
chip:

command

this

data

interpretations,
executed

set.

bit

command
is
FIFO

During

can
words
accept
long)
FIFO
if
the
is
cleared
it
bit
this
during
responds
in
these
not
used
is
data
in
the
remain
will
loaded

)}

During

been

loaded

I/D

command
and until

rasterop

commands,

I/D

the

and

commands
FIFO

during
an

other

the
and

becomes

(after
some

is
loaded
initialized

additional

command.

being

data
data
full.

set

four

has

commands

the

word;
(While

any
the

command
is
command

I/D

PTB

FIFO

[/D.
data

has

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data
word
this
bit
is
set
if
a
new
loaded),
may
and
it
is
be
to
the
data
I/D
loaded
register,
to
the
when
an
is
loaded
cleared
command
I/D
also
be
This
command
bit
should
register.
before
another
command
checked
loading
following
if
least
three
at
an
I/D
command;
however,
major
a
about
(one
cycle,
major
cycle
plus
sync
cycles
is
the
new
command
before
3 usec)
loaded,
passes
bit
need
not
be
checked.
this
status
When

cancel

momentarily

command

low;

when

set

execution
this

is
complete,
IDD
indicate
that
the
be
loaded.
a
new
command
may
to
indicate
checked
completion
this
is
not
command;
required
command

cancel

high

ed
ee

cycles

are

command

rasterop

<7>

Scroll
word

I/D
data
loaded

may
and
the

loaded

when

(see

IDD

progress

this

bit

and

scroll

the

asserted,
will

set.

new

This

loaded
to
is
cleared

it
I/D

pass

bit
is
set
the
scroll
I/D
when
an
I/D
command
register.

data
command

of
portion
boundary.
top

least

one

rasterop

clipped

the

least

one

rasterop

clipped

the

least

one

rasterop

clipped

the

at
of
portion
boundary.
right

least

one

rasterop

clipped

the

one

rasterop

was

<8>

<9>

portion

bottom
<A>

-INIT

Ready
be

not

initialized

Data

is
the

FIFO

PBT

is
bit

loaded.

data

I/D

the

will
be
set
clear
and
should
be
cancel
least
four
before
the

bit

This
a
of
if
at

guaranteed

bit
of

FIFO

major
d.

this

loaded,

<C>

portion

left
<B>

boundary.
boundary.

portion
(did

drawn

The

clip

preceding
activity

clipping

destination

-each

bit

last

The

indicating

inside

Clipping

the

may
that

clipping
information

successfully

boundary).

any

bits
accumulate
clipping
results
having
clipping
their
ORed
with
write
cycle
five

These
used

contents.

previous
by

least

at
not

be
a

bits
to

rasterop

rectangle.
during

are

asserted

picking

aid

was

The
a

rasterop

for

high.
algorithm
partly

least
accumulation
will

of
be

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will
be
the
information
for
a
Clipping
after
address
the
complete
status
the
reading
clipping
undefined
results.
can
yield

different
end
the

Sesnemiey
caine
mamas

isis
seein
ee

CONFIDENTIAL

HARDWARE
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CHIP

for
result

five

These

write

the

bits

width

cases.

will

rasterop
bit

bits

during

complete

asserted;
a
rasterop

cleared

selectively

are

although

all

status

with

status

modes,
in

same

page

zero

in
each
be
cleared

bit
to
position
clipping
be
to
zeros
or
unaltered;
positions
will
in
bit
have
no
on
ones
effect
positions
of
bits.
the
status
these
status
Clearing
clipping
will
a
bits
rasterop
give unpredictable
during
bits
should
be
cleared
these
after
the
results;
only
bit
is
status
asserted.
address
complete

corresponding
and

Blank
interval.

Vertical

<D>

in
other

one

blank

with

unaffected
by
values
of
other
Scroll
Service
of
the
the
end

[4]

RESERVED

C5]

SPARE

C6]

RESERVED

bits.
in
bit
vertical

this
This

bit
bit

that

DATA

(IDD)

loaded

into

this

zero

the

the
vertical
word
to

bit

the

position;
or
by

position
differs

from

the

set

near

latter

interval.

blank

address
This
register
the
it
because
precedes
IDD
if
load
the
this
to
counter.
the
address

through
C7]

one

by writing
a

used

IDD

only
register

address

were

function
force

start

function.

Test

the

Cleared

status

Set

for
a
test
and
would
accessed

PBT
When
a
or
cancel
command
rasterop,
or
the
-INIT
command
pin is
register,
at
this
address
is
the
six
asserted,
register
deep FIFO
the
FIFO
is
either
read
PBT
cleared.
commands,
During
of
on
the
direction
the
transfer
written
or
(depending
data
between
the
and
the
to
transfer
command)
processor
FIFO
bus
data
is
16 bits
wide.
When
The
I/D
bitmap.
data
FIFO
X
the
data
is
I/D
(in
screen
through
passed
in
to
the
left
most
the
LSB
the
mode),
corresponds
pixel

I/D
is

the

word.
Whenever
address

rasterop
cleared
loaded
loaded

load

output

the

complete

command
is
as
the
data
word
remains
to

subsequent

the

same

this
I/D
conditions

NOT

data

I/D
in

word
in
the
is
register

progress),
is

loaded
FIFO

(only

available

command).
does

status

Reading
not

clear

AND

occurs

set

the

FIFO

that
the
for

PBT

the

the
only
word
last
transmission

this
register
Note
the
FIFO.

under
that

DRAGON
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VIDEO
CHIP

HARDWARE
COMPANY.
AND
COMMANDS

SYSTEM
REGISTERS

the
address
output
complete
indicate
that
a
BTP
operation
data
has
been
removed
from

C8]

COMMAND

(CMD)

described
address

address

This

is
the

address

because

written
frequently
registers.

not

page

will

bit

status

continue
until

complete

all

FIFO.

the

accesses

the

following
is
provided

counter

CONFIDENTIAL

mode

ease

the

command

following

writes

command
the

same

I/D

the

through

access

data

mode

[9]

(MDE)

MODE

described
<0>

Sets

various

the

following

destination
from
the
01=Reserved
10=Linear

scaled
Pattern

Mode

from

destination
the
is
determined

size

pattern

uncoupled

modes

The
first
source
is
to
coupled
that
the
source
size
is
determined
destination
size.

Mode

00=Normal

execution

rasterop
bits:

first

The

the

source

that

the

source

and

slow
generator
the
first
source
and
edge vector,

the

source

registers.
The
destination
"A"
edge vector,
"B”"
the
computes
between
is
filled.

ll=Fill

Mode
the

computes
generator
space

mode
<2>

<3>

The

selected

O=The

fill

("X

£111").

l=The

fill

("y

O=Normal,
form

ignored
preceding

are

scanned

parallel

the

axis

area

scanned

parallel

the

axis

baseline
selected

for

the

"B"

edge

generator

horizontal
scan
direction

disabled.

up,

down,

This

wide

pixel
enabled.

destinations.
This
is

destinations.

source

O=Pen
1=Pen

the

source

<7]>

locked
fill
with
the

bit).

fill
Q=Hole
for
single
fill
l=Hole
all
other

0=Destination
l=Destination

fill.

edge

fill,

<6>

fill

bits.

vertical

O0=First
l=First

when

except
two

area

two

(depending
preceding

<§>

bits
in
the

two

£111").

l=Baseline

<4>

indexing
indexing
indexing
indexing

writing
writing

disabled.
enabled.

the
the

normal
normal

setting

for

DRAGON
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VIDEO
CHIP

[A]

HARDWARE
COMPANY
AND COMMANDS

SYSTEM
REGISTERS

(CMD)

COMMAND

Adder

CONFIDENTIAL

command

chip

page

See

of
a
the
commands
4.1.2
for
section
detailed
description
this
The
effects
of
and
various
loading
register.
for
all
commands
is
used
command
by the
update
register
of
will
in
bits
result
Some
combinations
process.
of
a
series
When
undefined
performing
operation.
an
identical
or
vector
text
strings),
(eg.
operations
after
the
be
reloaded
command
rasterop
may
bit
is
set
if
the
status
initialization
only
complete
have
been
or
1 and
destination
source
origins
changed,
if
bit
is
set
other
the
after
rasterop
rasterop
complete
have

Parameters
the

been

address

output

load
bit

changed.
complete

status

command,

new

must

set.

Command.

<Q>

Bits.

I/D

<8>

bits.

Function

all

select.
and

active

commands

pending

(except

Ics).

command.
command.
10=Rasterop

01=I/D
*

Destination

<B>

First

<C>

Second

<D>

Test

Function,

normally

<E>

Test

Function,

normally

<F>

Reserved,

loaded
vertical
of

Registers

active
During
scroll
by the

during
activity

function
a

This

process
Adder

vertical

DATA
to

chip
blank,
for

pending

IDS

registers
the

this

of
the

type

frame.

must

START

various
performs
on
depending
the

address
register
the
it
precedes

because
load
to
the
address
the

SCROLL
I/D
transmitted

scroll
before

scrolling,
The

blank.

normally

Scroll

RESERVED

through

Enable.

Source

scroll

force

Enable.

Source

functions

CC]

Enable.

<A>

4.1.1.2

(B]

command.

transfer

ll=Processor/bitmap

used

IDS

only
register

address

were

a
for
test
and
would
accessed

counter.

(IDS)
the
I/D

This
bus

contains

during

data
scroll

process

I/D

DRAGON
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VIDEO
CHIP

HARDWARE.

SYSTEM
REGISTERS

transmitted

I/D

SCROLL

scroll
will

last
the.

bits

the

commands;

COMPANY

word

loaded
to
scroll
I/D

page

this

will

for

the

This

command.

wide.

(ICS)

COMMAND

Commands

process.

transmitted

CONFIDENTIAL

COMMANDS

AND

I/D

command

directed

through

without
interference
with
that
be
in
any
update
activity
may
progress,
that
in the
related
assuming
only scroll
registers
Viper
are
and
that
selects
are
addressed,
chips
separate
chip
An
used.
from
the
Adder
can
enable
an
output
pin
chip
bus
that
is
reserved
for
I/D
these
chip select
register
scroll
commands.
I/D

(E]
(F]

SCROLL
The
left

SCROLL

MIN

(PXMN)

most

pixel

MAX

(PXMX)

first

The

the

Left
the

outside

pixel

boundary
scroll

scroll

region.

of
scroll
boundary
side
of
the
right

Right

bus

I/D

the

region.
scroll

region.
The
boundaries

LSBs

two

only

may

X boundaries
the
be
to
specified

the
four

are
ignored,
of
multiple

pixels.
[10]

SCROLL

The

{11]

(PYMN)

MIN

upper

Y MAX
SCROLL
(PYMX)
The
first
outside
pixel

the

scroll

Bottom

boundary

Top

pixel

most

scroll

of
the

boundary

the

region.

bottom

scroll
scroll

region.
region.

start

boundaries
are
in device
coordinates
so
that
unaffected
the
index
that
values;
is,
by
they
on
the
still
screen.
These
are
double
registers
so
that
the
values
loaded
become
active
at
the
of
the
frame.
following

PAUSE

(PSE)

Scroll

they

are

stand
buffered

[12]

that,
bit

when
to
be

new

following
Only the
(13]

coordinate
will
displayed,
a

the

memory
processor
of
height

(PYOF)

second

pause
double

loaded
value
and
frame
ll
bits
low

OFFSET

get

device

being
set,

description
This
register
the

the

event

pause

complete

status

buffered

begins

continues
of
this

the

specifying
cause

the

that

status

pause
be

queued

bit

above).

comparison
of
that

start

throughout
register

scan

are

(the

same

one,

see

below).

should
frame

with

the
frame.

significant.

Offset
added
to
device
coordinates
coordinates.
Decremented
local
by the
down
0 and
between
scroll;
during
ranges
the
value

(see

displayed

portion

in
stored
the
The
offset
be
that
which
is
complete,

the

bitmap
register,

memory
minus
this
when

Y limit
value
loaded
to
will
be
in
effect
due
to
the
multiple

the

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(14]

Viper
loaded
next

<0>

the
vertical
Specifies
of
in one
frame
time.
scrolled
Loading
selected
the
will
cause
by the
region
register
vertical
be
scrolled
to
boundaries
(by the
OR the
horizontal
to
this
loaded
register
in
the
constant
to
the
scroll
loaded
registers
If
value
is
no
the
frame.
following
during
chips)
in
will
occur
the
no
a
frame,
scrolling
during
frame.

<D>

the

(unsigned

magnitude
non-zero

Viper

chips,

the

scroll
Y

distance)
is

constant

scroll

constant

zero.

left

scroll
be
set

scrolling.

right

scrolling.

l=Down

the
also

scroll.

specified
O=Up,

vertical

The

Bits.
the

12
of

(PYSC)

must

<C>

page

CONSTANT

SCROLL

distance
this
scroll
distance
distance

this

buffering

CONFIDENTIAL

direction
to

down

is
down
scrolling
in
the
bits
Viper
and
left.

specified,
should
chips

in
bits
scroll
direction
The
OQ=Normal
scrolling.
the
to
be
set
should
the
according
chips
Viper
direction.
scroll
desired
will
be
scroll
The
entire
mode.
l=Erase
region
of
the
fill
color
the
to
cleared
settings
regardless
must
be
constants.
scroll
the
of
Up scrolling
Adder
and
the
in
both
chips.
Viper
specified

4.1.1.3

Update

Control

[15]

PENDING

INDEX

(PXI)

[16]

PENDING

INDEX

(PYI)

[17]

NEW

INDEX

(NXI)

[18]

NEW

INDEX

(NYI)

[19]

OLD

INDEX

(OXI)

(1A]

OLD

Y¥ INDEX

(OYT)

Registers

to
addresses
the
to
are
added
values
rasterop
on
of
and
the
location
for
regions
scrolling
adjust
which
will
be
are
values
those
The
the
pending
display.
at
the
start
new
the
into
loaded
registers
automatically
is
not
of
these
content
the
next
of
the
frame;
registers
will
if
no
so
load
this
that,
scrolling
by
destroyed

Index
them

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VIDEO
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HARDWARE
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©

SYSTEM
REGISTERS

CONFIDENTIAL

page

in
next
need
take
the
these
not
frame,
place
registers
new
reloaded.
The
values
are
the
indexes
that
be
apply
has
the
to
data
that
been
moved
current
already
during
of
these
will
be
loaded
the
contents
frame;
registers
at
old
the
start
of
the
next
into
the
frame,
registers
new
are
loaded
into
the
before
the
values
pending
are
that
The
old
values
the
indexes
registers.
apply to
values
has
not
moved.
The
index
to
data
that
apply
yet
is
because
that
the
they
only
region
being
updated,
the
addresses.
affect
update
loaded
also

These

are
normally
registers
is
the
scrolling
region
and
are
also
loaded
region,
the
region
changes.
update

process

update
whenever

interlock
section

for
3.3.4.1.

(CXMN)

MIN

CLIP

most

pixel

CLIP

(CXMX)

MAX

The

boundaries

(15)

pixel

CLIP

pixel

(CYMN)

MIN

most

the

MAX

(CYMX)
the

clipping
region.

Top

loaded

update

one

the

The

left

first

The

region.
the
four

ignored,
of
multiple
are

boundaries
and

are

they
clipping
thus

are

contain

merely

scroll

window.

destination

clipping

not

data
status

performed.

usable
the

are

the

by
coordinates,
on
as

The

boundary.

boundary.
clipping
the

Bottom

bottom

boundaries
unaffected
in
is
device
stand
still

SPARE

may
from
loaded

boundary.

X boundaries
the
to
be
specified

Clipping

[1F]

described

old.

clipping
region.

update

outside

that

still

process

CLIP

update
appropriate

clipping
boundary.
Right
of
side
the
update
right

only

may

scroll

current

LSBs

pixels.

registers
changing
be
always

then

update

the

two

must

Left

the

outside

pixel

{ip]

processes
these
when

order:

{ic]

two

All

required
to
another;
they
new
and
pending,

directly,
region
{1B]

these

the

by
the

The

update

region.

device
index

coordinates
values.

the

screen

drawing

upper

first

Because

clipping
during
scrolling
but
of

function,

the
borders
image within
or
affect
whether
They only
and
the
is
written
setting
all
calculations
bits;
rasterop

not

the
are

the

—

DRAGON

VIDEO
DRAGON CHIP

SYSTEM
REGISTERS

4.1.1.4

[20]

FAST

SOURCE

This

(FSDX)

can

only

component.

SLOW

SOURCE

(SSDY)

can

only

This

signs
whole
modes.
-2*12
because

page

Registers
Fast

for

extent

delta

the

Slow
extent
+
in
the

first

the
X

direction,

for

first

the

component.

bit
the
1
source
13) of
(MSB, bit
Only the
sign
in
normal
is
mode
the
(even
registers
significant
are
if
the
source
is
not
the
enabled);
ignored
1
in
value
is
linear
and
fill
significant
pattern
in
In
values
the
fill
2*12-1
to
range
mode, only
in
allowed
values
these

are

the

source

are

multiplied

internal

calculations

(23]

there

[22]

Control

there

source,

CONFIDENTIAL

COMPANY

COMMANDS

AND

Rasterop

source.

(21]

HARDWARE

SOURCE

source

origin.

SOURCE

source

origin.

(SXO)

ORIGIN

(SYO)

ORIGIN

delta

by 2
chip.

registers
in
some

the

Adder

coordinate

the

first

Y¥ coordinate

the

first

can
in
first
source
be
either
The
origin
components
on
the
of
world
or
device
coordinates,
depending
setting
The
mode
for
the
first
source.
of
either
index
loading
in
linear
mode
will
of
these
reset
the
pattern
registers
slow
scale
scan
and
the
calculations.
source
pattern
;

[24]

[25]

DESTINATION

destination

origin.

DESTINATION

destination

origin.
or

for

mode

(DXO)

(DYO)

origin
fill

initialized;
to
relative

coordinate

the

coordinate

the

mode
end

all

the

vector

source
nor
destination
the
first
mode
after
used
any
during
reqisters
these
is
initialization
registers
complete;
after
the
values
with
new
loaded
rasterop
is
set.
bit
status
complete

Neither

DESTINATION
fast
destination
FAST

DX
vector.

(FDX)

component

vector.

rasterop

be
may
initialization

the

origin
the

are

[26]

either

setting

either
new
fill

causes

otherwise,
the

be
the

can

on
depending
Loading

to
are

components

coordinates,
the
destination.

during

registers

position
extents

ORIGIN

destination
device

The

world
index
these

ORIGIN

DRAGON
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[27]

VIDEO

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HARDWARE
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AND
COMMANDS

SYSTEM
REGISTERS

destination

(28]

SLOW

fast

[29]

allowed
values
to

(2a)

[2B]

SCALE

vectors

(FSC)

vectors

{2c]
[2D]

origin.

SOURCE

source

origin.
The

2°12-1

-2*12

are

because

registers

relating

the

fast
in
normal

relating

the

slow
in
normal

destination

in
bit

the
12.
factor.

origins

HEIGHT

The

scale
both

unless

determine

3 Bits.
tile
the
bus
bit
for
less
a

narrower

the

scale

the

second

added
bits

than

the

tile

(S2HW)

the
bus

unindexed
if
tiling

the
them

components.

tile

width;

repeating

the

(W) from
4
(from

Tile
width
is
2°(W+2)
width
modes,

the

section
factors.

See

coordinate of
origin

size

with
adds

second

low

WIDTH

one.

the

source

AND

chip

0
to

The

contents

source

512).

the
In

are

2 cannot
the
source
coordinates;
memory
for
is
not
the
effects
and
it
indexed
adjusted
must
be
off
If
screen.
and
therefore
offset,
2
must
be
on
a
word
the
source
enabled,
origin
in
the
bus
on
width)
memory.
{dependent
SOURCE

13)
if
bits

are

(or

Adder

The

XK coordinate

(bit

MSB

scaling
13
remaining

the

(S2Y0)

ORIGIN

the
down

factors,
zero

be
of

always

(25]

these

internal

calculations

some

and

(S2X0O)

ORIGIN

addresses
second
The

enabled).

the

scale
Adder
chip
are
enabled.
of
description

each

complete

source

destination

factor

destination

source

component

destination

scale

the

source

ignored

SOURCE

the

and

if
a
scaling
is
specified
magnitude
point
binary
preceding

factor

0.0000000000001B
are
factors
1 and
source
for
3.5.1.2

component

modes.

each

Scale

pattern

For

the

delta

source

first

the

indicates

modes.

(SSC)

linear

component

range

Scale

pattern

SCALE

first

the

linear

SLOW

The
the

multiplied
chip.

Adder

the

FAST

and

the

are

and

in
the
destination

Only values

DY (SDY)
vector.

slow

vector.

DESTINATION

SLOW

(SDX)

slow

destination

page.

vector.

DESTINATION

destination

(FDY)

DESTINATION

FAST

CONFIDENTIAL

Y¥

is
tiling
boundary

this

and

of
16

tile.
width
8

width
must
not
be
of
one
course,
may
within
it
the
larger

set

have

DRAGON
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VIDEO
CHIP

cell.

<3>

Reserved.

Should

<4>

3 Bits.
tile
the

Tile
height
is
2*(H+2)

O=Tile

bits

during

destination

the

height

high

bits

enabled;

before

adding

source

See

section

width

disabled;

all

destination

origin.

added

Error

adjustment

source

side
-

and
in

normal

side)

for

added

initialization
linear
pattern
fill
mode.

for

adjustment

Error

the
the

error

the
the

error

slow

mode).

fill

rasterop
(B

added

initialization

rasterop

(ERR2)

during

the

from
0 to
7;
4 to
512).

truncated

component

(ERR1)

ERROR

(H)
(from
width

origin.
and
height

l=Tile
address

[30]

source

ERROR

and

height

destination

(2F]

page

AND COMMANDS

pattern

<7>

CONFIDENTIAL

COMPANY

HARDWARE

SYSTEM
REGISTERS

for

3.5.1.1.2

mode,

fast
and

for

these

information

registers.

4.1.1.5

Control

Format

Screen

the

program
example
registers
following

can

that
from

found

DRAGONLIB.C,

in
the
referenced

Registers

SCAN

COUNT

(¥CTO)

[32]

SCAN

COUNT

(YCT1)

[33]

SCAN

COUNT

(Y¥CT2)

[34]

SCAN

COUNT

(YCT3)

the

general

timing

VDIsetscan()

routine

(31]

calculates

section

contents

requirements
in

the

file

1.2.

all
program
Each
register
timing
such
as
vertical
one
of
the
event,
is
the
event
vertical
blank;
by the
specified
asserting
the
low
11
bits
determine
The
12
and
13).
two
MSBs
(bit
and
for
vertical
(scans
event
the
events,
of
time
sync
from .
for
other
one
minus
events),
scans
starting
in
the
are
stored
events
The
unblank.
vertical
11
time
(low
of
in order
increasing
bits),
registers
is
time
value
the
in
programmed
YCTO;
highest
starting
If
the
horizontal
event.
vertical
for
the
period
period
These

vertical
determines

four

parameter

for
time

the

registers

Dragon

system.

DRAGON
DRAGON

VIDEO
CHIP

SYSTEM
REGISTERS

HARDWARE
COMPANY
AND COMMANDS

CONFIDENTIAL

page

is
set
for
an
odd
number.of
(N odd,
where
major
cycles
"N"
is
defined
for
the
horizontal
event,
period
below),
there
must
be
an
even
number
of
in
scans
a
so
frame,
that
there
will
still
be
an
even
number
of
major
cycles
in
a
frame
vertical
(the
event
must
be
set
to
an
period
odd
Vertical
blank
number).
is deasserted
(set
low)
when
the
vertical
is
reached.
The
bits
of
the
y
period

seem

me
cote
NLA

registers

count

scan

<Q>

Bits.

blank,
minus

one

event

minus

one.

<B>

Reserved,

<C>

2 Bits.
00=End

scans

for
other
to
the

for

from

event

should

vertical
events.

number

as:

deassertion
of
vertical
and
scans
events,
sync
The
end
vertical
period
of
scans
in
the
frame,

zero.

Event.

vertical

period.

vertical

Set

blank

low

scan.

vertical
vertical
vertical

Ol=Set
10=Set
ll=Set

Time

set

following

vertical
in

The
for

assigned

are

blank

high.
is

signal

sync

use

high.
low.

sync
syne

that

systems

available
separate

want

output

vertical
and
between
two
the
variable

horizontal

this
also
chooses
sync;
signal
in
X scan
the
counter
that
provide
width
horizontal
needed
in
a
sync
pulse
composite
sync
When
are
the
vertical
system.
separate
syncs
required,
is
and
the
"010"
or
"011"
x
sync
polarity
programmable
event
should
be
removed
from
the
X scan
count
sequence,
so
that
the
horizontal
width
is
When
sync
unchanged.
the
vertical
interval
must
be
using
composite
sync,
sync
delineated
of
the
vertical
by the
high state
sync
the
horizontal
time
to
be
signal,
allowing
longer
syne
determined
"100"
or
"101"
event
in
the
X scan
by the
events

(see

counter

below).

example
application

sync
YCT1

will

sync

low,

set

is:
vertical

sync

request

scan

prior

(scan

prior

timing

X
SCAN

scan

sync

high,

set

vertical

will
to

first

the

CONFIGURATION

generated

deasserting
displayed

within

request

count

for
a
vertical
YCT2
will
blank

composite
blank
set

low

high,

vertical
and

counter.

System
the

of
events
will
set

will

YCT3
vertical

chip
the

C35]

and
the

restart

YCTO

assignment

registers,
(XCON)

that
below.

vertical

scan):
scan

the
Adder
blank

the
exact
determined

DRAGON
DRAGON

VIDEO
CHIP

<Q>

COMPANY
HARDWARE
AND COMMANDS

SYSTEM
REGISTERS

page

used
for
each
read
of
cycles
major
set
the
smallest
to
integer
normally
to
number
of
to:
the
pixels
equal
greater
64
or
32
divided
on
each
be
scan,
by 128,
displayed
To
bus
4 bit
8 or
in
width
mode,
respectively.
16,
the
of
refresh
bitmap
memory,
dynamic
guarantee
to
must
be
read
programmed
cycles
major
enough
4
will
allow
this
each
on
512
scan;
pixels
display
in
16
bit
scan
on
each
be
addresses
row
refreshed
to
in
8 bit
and
addresses
8 row
width
bus
mode,
mode,

Bits.

Number
This
is
or
than

scan.

typical
accomplished
occurring
gap
of

discussion

relationships
2

Bits.

in
is

the

bit

in
4
rates,

addresses
scan

<§>

CONFIDENTIAL

bit

(see

memory

refresh

approximately
vertical
during

every

and

XCTto

this

width

Bus

mode

0.5

registers
register.
must

plus

msec,

See

retrace.

mode
before

below).

<8>,
will

for

any

the

required
here

programmed
bitmap
memory
is
initialized,

and

access

chips
Viper
most
Once
bus
attempted.
the
bus
are
width;
independent
operations
X mode
are
transfers,
processor/bitmap
exceptions
boundaries.
scroll
and
2 tile
source
Viper
origins
the
Adder
bits
to
X and
Y address
of
The
assignment
the
width
and
on
bus
is
dependent
pins
output
chip
are
The
bit
below.
assignments
configuration
memory
section

covered
bit
00=4
bit
01=8

bus
bus

any
width
of

5.6.1.

width.
width.

10=Undefined.
bit

11=16
<8>

Memory

bus

width.

configuration

controls
on
each
32 row
4
8 or

the

number

row

than
refreshed
addresses
"greater
are
refreshed
addresses
1024"
mode,
8, 16 or
bit
in
scan
modes,
on each
16,
respectively.
addresses
16
row
512"
than
In
4, 8 or
mode,
"greater
4
bit
in
8
or
scan
on
each
modes,
refreshed
16,
are
in
each
read
of
The
number
pixels
respectively.
in
reads
of
refresh
the
is
(number
scan
programmed
*
*
width
8).
bus
the
XCON
<=
from
read
of
(number
0=1024
memory/scan)
pixels
2048
<=
from
read
of
512
(number
l=
memory/scan)
pixels
scan.

[In

1024

NOTE

If
on

of
1 Mbit
the
Dragon

maximum

memory

system

addressable

1024
pixels
of
memory

(actually
are

reserved

is
used
64Kxl
memories)
the
16 bit
mode),
Y is
in
X and
both
range
32 scans
992
in Y if
only
To
for
down
scrolling).

(16
(in

DRAGON
DRAGON

SYSTEM
REGISTERS

VIDEO

CHIP

HARDWARE
COMPANY
AND COMMANDS
-

extend
these
it
would
ranges,
add
another
1 Mbit,
allowing
x
1024H
2032V
memory
range.
more
be
if
added,
memory
may
x 8192V
8192H
the
limits
(or
desired
the
system
speed).

[36]

LIMIT

(XL)

{37]

LIMIT

(YL)

CONFIDENTIAL

be
necessary
2048H
x
Of
course,

1008V
still

desired,
of

bus

page

for

Width
of
that
of
the
READ
portion
memory
the
screen
refresh
be
(could
more
by
process
than_that
which
is
This
tells
the
address
displayed).
register
calculation
what
hardware
extent
of
the
in X,
memory,
Y offset
the
for
down
should
be
(used
scrolling)
applied
number
loaded
to
to.
The
this
must
be
the
register
of
read
in
number
set
the
X scan
cycles
configuration
64 or
32
in
4 bit
times
bus
128,
16, 8 or
register,
width
modes,
respectively.

the

refresh

screen

scans

hardware

(used

for

process,
down

when

required
suggested).

Height

This

what
down

the

of
portion
memory
the
of
number
plus
16
(between
scrolling

tells

extent

scrolling)

the

memory,
should
be

address
in Y,

and

calculation
Y offset

the

applied

read
extra

to.

is
to
all
of
the
applied
rectangular
defined
corners:
and
[0,0]
memory
by the
inclusive.
The
in
the
(XL-1,¥L-1],
memory
rectangle
of
from
address
screen
to
(scans)]
[0, height
displayed
the
not
address
Y limit]
is
(but
[X limit,
including)
not
for
while
the
usable
between
the
any
purpose;
memory
of
screen
and
X
the
limit
be
(if
right
edge
any) can
is
for
Y addresses
this
from
0 to
used,
only possible
the
of
the
screen.
The
addresses
height
displayed
to
in
this
are
in device
referred
coordinates.
paragraph
The

the

area

offset

[38]

SCAN

COUNT

(XCTO)

(39]

SCAN

COUNT

(XCT1)

(3A]

SCAN

COUNT

(XCT2)

(3B)

x SCAN

COUNT

(XCT3)

[3c]

SCAN

COUNT

(XCT4)

[3p]

SCAN

COUNT

(XCTS5)

(38)

SCAN

COUNT

(XCT6)

the

The

registers
system.

scan

count
count

most
program
Each
register

registers
registers.
horizontal
determines

are

These

similar

function

seven

parameter

timing
the

time

for

the

one

Dragon

DRAGON
DRAGON

VIDEO
CHIP

COMPANY
HARDWARE
AND COMMANDS

SYSTEM
REGISTERS

horizontal
the
low

such

event,
is

event

determine

bits

specified

allowed
event,

asserting
three

high

time

(in

but

nsec,

programmed
from

reference

starting

blank;
bits.

order
l6ths

The

major

are not

events

some

this

page

horizontal

by
the

nominally

cycle,

CONFIDENTIAL

of
precision)
time
preceding

the
the

that
reads
the
first
data
the
of
cycle
memory
time
the
a
scan
refreshed
on
(or
be
to
corresponding
stored
in
The
events
are
the’
vertical
retrace).
during
in
in
order
of
time,
XCTO;
starting
increasing
registers
as
horizontal
the
value
is
time
the
programmed
highest
in
all
be
seven
<E>
must
Bit
event.
programmed
period
event
if
"end
horizontal
the
even
is
period"
registers,
of
X
scan
count
The
bits
the
an
earlier
in
register.

beginning

registers

assigned

are

as:

<Q>

a
from
reference
time
3-1/4
of
the
first
the
start
memory
preceding
major
cycles
the
in
of
a
l6ths
on
a
scan,
major
cycle;
cycle
defined
as
the
is
a
of
start
rising
memory
cycle
that
the
RAS precharge
2 during
begins
edge of PHI
in
occur
the
same
No
two-events
1/4
the
may
cycle.
events
have
no
two
that
a
of
is,
may
major
cycle;
in
all
but
the
low
two
bits.
are
that
times
equal

<B>

3 Bits.
000=Set
001=Set
010=Set

Time

Bits.

Event.

event.
sync
horizontal
100=Set
horizontal
101=Set
horizontal
110=End

lll=Set
one

multiple
cycles
major
retrace

the

syne

high

sync
sync

high.

least

vertical

during

except

low.-

period.
event.

bit

zero

this

XCT6,

the

XCT-

contains

that

registers

the
must

bit.

normally

The
to
Nxl6-4.
set
must
be
integer
of
read
the
number
to
twice
be
"N"
must
equal
of
number
two
least
at
(an
in XCON plus
integer
horizontal
"N"
will
the
a
lengthen
larger
cycles);
N must
be
of
one
interval
cycle.
major
by units

period

10.

Horizontal
of

start

vertical

during

except

must

function

Test

The

low

for
this
programmed
the
register
following
register
All
other
event.
request”
"sync

contain
<F>

high.

sync

request

sync

low.

blank
blank

horizontal
horizontal
horizontal

event.
sync
horizontal
Oll=Set

<E>

event

the

blank
first

set
normally
of
cycle

memory

low
the

shortly
scan

after
allow

DRAGON
DRAGON

VIDEO
CHIP

SYSTEM
REGISTERS

for

eee

the

HARDWARE
COMPANY
AND
COMMANDS

pipeline
in

and
chips
produces

the

delay
video

the

data

the

Adder

circuitry;

output

°..

CONFIDENTIAL

3-1/4

the
mentioned

page

and
Viper
Adder
chip

major
cycle
delay
above,
and
the
an
additional
10 Alpha
Viper
clock
chip produces
(5/8
Horizontal
blank
would
be
delay
major
set
cycle).
the
desired
number
of
have
been
high after
pixels
on
a
scan.
displayed
The

(or

low
low

set

when

starts

sync
the
the

by
by

horizontal

polarity

Horizontal

event).

"100"
"010"

vertical
horizontal
"101"
by the

syne

programmable.

high

the

"101"
ends
sync

Horizontal

(or

event

when
when

except

set

high

from
is

the

event

when

"011"),

is
"100"
event
(or
event).
The
or
"101"
high
events
will
horizontal
one
of
these
events
always
change
sync;
should
be
set
to
occur
after
the
"010"
or
"011"
event
when
is
and
should
be
used
composite
sync
generated,
alone
(without
the
"010"
or
"011"
when
events)
separate
are
syncs
generated.

high,

request

event

the

Adder

following
this

event

inclusive;

the

0 to
where

implied),
above.
when
the

vertical

must

other

following

for
for

set

counter

scan

interval
in
the

sync
are

The

low

two

significant

events

(two
range

bits

(only

sync

during

occurs

blank.
"Shortly"
of
the
timing
logic
the
interval
syne
an

(integer

defined

also

logic
the

major
cycle
implementation,
in
the
Mx32+4
range
"M"
must
multiple

such

programmed
the
integer
inclusive
(N/2)-2,
"N"

This

times
affected
inclusive.
time
are
not

must

Mx32+16,
range

with

request;

sync

generated
after
“shortly”
request
always

implementation
chip.
Usually
of
next
beginning

the

counter

scan

the

the
Adder

the

sync
end

the

preceding
on
dependent
scan

external
will
start

chip

occurs;

low
by
"100"

set

synchronization

System
external
the

sync
sync

the
a

time
will

major
Mx32+21
the
sync
240
nsec

truncation

period
during

event

the

scan

during
event
cycles);
to
(M+1)x32+23,
occur

request
intervals

event

allowed).
An
of
events
for
a
example
assignment
composite
is:
XCTO sets
horizontal
blank
sync
application
low,
XCT1
sets
XCT2
sets
horizontal
low
sync
request,
sync
for
vertical
interval
("100"
XCT3
sets
event),
horizontal
blank
XCT4
sets
horizontal
high,
sync
high,
XCT5
sets
horizontal
low
vertical
sync
except
during
interval
and
("010"
XCT6
ends
the
horizontal
event),

period.
(3F]

SYNC

PHASE

horizontal
per

defined

frame).
for

(SYNP)

11 Bits.
The
value
loaded
in
the
counter
at
each
time
(once
sync
system
syne
This
must
be
set
for
where
M is
(M+l)x32,
the
above
(this
assumes
sync
event,
request
-

DRAGON
DRAGON

VIDEO
CHIP

the
low

SYSTEM
REGISTERS

required
five

bits

programmable).

CONFIDENTIAL

HARDWARE
COMPANY
AND
COMMANDS

sync
of

of
interval
this
register

two
are

major
cycles).
(not
ignored

page

The

DRAGON
DRAGON

VIDEO
CHIP

SYSTEM
REGISTERS

4.1.2

Adder

Chip

HARDWARE

COMPANY

CONFIDENTIAL

page

COMMANDS

AND

Commands

commands
to
the
hardware
are
two
to
the
command
passed
in
the
Adder
which
is
initiated
chip
(except
scrolling,
the
scroll
constant
as
register,
previously
The
command
all
for
screen
described).
(CMD) is used
register
and
scroll
functions
the
command
is
I/D
(ICS)
update
register
for
bus
loads
used
scroll
The
I/D
only
register
process.
by the
has
13 significant
MSBs
command
bits
three
are
(the
register
for
reserved
test
shown
below:
as
functions),
All

registers
by loading

COMMAND

FORMAT
pa

pan

TFITEBIDICIBIAITS9I8I7IE6151413121110
|

heen

pee

pot

|
|
|
|
|

annem

I/D

BUS

COMMAND

nme

|
+

mine

COMMAND

CHIP

ADDER

pan

0
a

|S2E/S1E|DTE]

{| O

low

The

settings

section
described

are

processor/bitmap
3 bits
enable
The
ICS
register

specify

byte

the

thus,

only

I/D

not

the

nibble

but

in
bits

this
select

CODE

ADDRESS

se ow wt feme af me

I/D

bus

and

nibble
instructions

required
section

portion

I/D

address;
4.2.2,
2

combinations
commands
commands

Not

all

the

specific
Illegal

allowed.

oeoe oeoehe

command,

any

that

usually
fully
and
bit
optional
to
they
apply
specific
are

four
functions
(I/D
bus,
or
transfer
and
the
next
cancel)
(PBT),
rasterop
of
a
combination
the
destination
and
two
sources.
is
that
it
uses
the
low
identical,
except
only
and
the
an
command
is
I/D
I/D
assumed;
operation
will
not
be
scroll
command
further
described.

The

commands.

contains

opcode

FUNCT

fae se ee ee

described

byte
of

consisting
specifies

one

command
bits
described
undefined
yield

the

that
will

are

meaningful;
this

section

results;

are

they

are

NOPs.

commands

All

those
Viper
will
respond
writes
allow
in
scrolling
in
bit
each

enabled.

Viper

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and/or
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of
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operation

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common

only
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and
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described
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description
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status
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reviewed
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execution
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status

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bus

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Prololjototliilotialiaultilaioitutridso
Pew
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pw
pee
pee
pee
mam
em

The

plane

address,

select
are
used
register
Z word.
The
destination
the
size
of
the
rectangle
DX should
both
be
zero.
the
of
the
data.
origin
determine
the
direction

the
to

COMMAND
ce

He oecneo

fame

bee

oe
ne

oeeo

|
pom

BLOCK

select

rasterop

pee

address
the
Viper

registers

to
be
transferred;
The
source
registers
The
bits
of
the
sign
of
scanning.

pee

IZ BLOCK]

pee

and/or

peep

the

chip

which

chips

programmed

are

the
are

source

fast

mah

form
the
for
and
slow

programmed
DX

and

for
DY

VIDEO

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CHIP

4.1.2.4

Cancel

CANCEL

COMMAND

POLO
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craea memmr
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ee

CONFIDENTIAL

page

Command

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HARDWARE
COMPANY
AND COMMANDS

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The

of
the
cancel
command
all
stops
operations,
regardless
in progress,
EXCEPT
for
commands
entered
the
through
The
bits
are
to
status
set
their
I/D port.
rasterop
and
the
FIFO
is
The
states
Address
cleared.
"completed"
output
IDD
ID
FIFO
is
also
cleared
and
the
status
bits
set
accordingly.
The
scroll
and
vertical
scroll
I/D
data,
service,
pause,
clipping
blank
status
bits
are
not.
affected.

command
scroll

transmit

execution
During
status
ready”

the

bit

will

cancel
be

the
cancel
is
command
complete
be
be
loaded.
This
bit
should
unless
the
software
is
loaded
guarantees
will
be
the
case).
(this
normally

high,
may

data
the
"I/D
When
this
bit
goes
new
data
or
command
any
before
command
the
next
4 major
of
delay
cycles

command,
held
and
tested

low.

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4.2

VIDEO
CHIP

Viper
The
and

SYSTEM
REGISTERS

HARDWARE
COMPANY
AND
COMMANDS

(I/D

Chip

Bus)

CONFIDENTIAL

933

page

Commands

instruction/data

bus
is
used
to
of
control
all
the
Viper
external
devices
connected
The
to
it.
chips
any
I/D bus
also
for
the
of
data
between
or
from
provides
exchange
Viper
chips
to
the
local
the
Adder
(via
Viper
Control
chips
processor
chip).
of
external
bus
I/D
devices
is
covered
in section
of
5.4.1
this
because
these
devices
can
be product
specification
specific.
External
devices
include
the
for
the
might
chip selects
Viper
control
(which
the
in
bus
I/D
chips
Viper
chip's
participation
transfers
and
or
the
video
color
Two
rasterops),
map.
chip
select
are
selected
Adder
one
for
the
registers
by the
chip,
scroll
to
access
the
and
for
one
the
process
Viper
chips
update
process.

4.2.1

Viper
The

Chip

basic

Registers

width

of
a
is
16 bits,
Viper
chip
register
fewer
than
this.
All
of
the
although
many
registers
require
are
writable
and
none
are
readable.
The
Viper
chip registers
address
the
(or
address
of
the
first
of
a
of
register
group
in HEX and
enclosed
in
the
registers),
[J], precedes
register
in
the
list.
Where
bit
descriptions
following
specified,
the
LSB
(or
of
a
of
bits)
are
in
enclosed
<>.
assignments
group

(0]

MODE

RESOLUTION
bits

(the

mask

mask),

edge
shift
behave
mode

2 Bits.
combination

the

and
2

the

planes.

The
that

resolution
different

but,

the

mode

regions

external

color

its

configuration
to
make
displayed
different

resolution
the
scroll
of
the

regions,
axis

load

<0>

Q0=1

Plane.
others.

significant.
for

one

bit

axis

Ol=2

(after

Planes.
the

registers)

be
may
have
may
must
map

dynamically

of
the
and
the
barrel

used

are

will

process

not

Viper

time

any

resolutions;
be

able

region

useful.
in different
be
able

change

use

may
Even

receiving

the

its

programmed

and

complementers
and

chip

resolution

also
each

changes

modes

fill

changed
different

resolution

operations,
corresponding

address

plane

Each
mask/source
bit
controls
its
mask
unit
bit
mux/logic
independently
All
barrel
shifter
constant
bits
The
as
a
Viper
chip acts
single

respective
the

mask

the
rasterop
commands
to
make
The
effect
of
can
be
disabled.

axis

source

actions

the

source

constant,
on

Controls
of
mask

result

odd

plane
to

of
are

plane
the

transmitting
address:
any

the

value.

mask/source
bits
controlled
by the
is
used
to
control

are

ORed

LUF

both

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HARDWARE
“COMPANY
AND
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SYSTEM
REGISTERS

CONFIDENTIAL

page

bits
of
the
mask
unit.
the
corresponding
mux/logic
the
barrel
shift
is
The
LSB
of
constant
rasterop
in
will
so
that
data
this
move
truncated
plane
only
a
of
two
The
acts
as
bits.
Viper
chip
by
multiple
Z
axis
or
for
two
receiving
planes
operations,
to
the
two
bits
its
corresponding
transmitting
plane
and
next
more
the
address
the
bit;
significant
plane
an
even
must
be
to
value.
address
programmed

10=This

will

setting

give

undefined

results.

from
each
The
four
bits
11=4
Planes.
mask/source
the
controlled
nibble
are
ORed
(after
complementers
result
is
used
to
LUF
and
the
registers)
by the
bits
of
the
all
four
of
the
control
corresponding
of
The
two
LSBs
the
mask
unit.
mux/logic
rasterop
in
truncated
so
that
data
shift
constant
are
barrel
of
four
will
move
this
only
by a multiple
plane
for
Z axis
as
four
The
bits.
planes
Viper
chip acts
the
four
bits
or
transmitting
operations,
receiving
and
the
to
its
address
next
plane
corresponding
the
address
must
more
three
bits;
plane
significant
to
a
of
four.
be
multiple
programmed

NOTE

The
barrel
rasterop
in
low
truncated
in
bits
their
the
Adder
chip cannot

shift
resolution

constant

must

to
Viper
chips
keep
because
the
subplanes
a
each
with
Viper
chip
be
(each
chip may
Viper

proper

supply

constant
shift
On
the
for
a
different
resolution).
programmed
be
for
cannot
this
effect
other
hand,
provided
the
error
caused
because
by truncation
scrolling
the
and
because
not
be
accumulated
must
for
which
not
be
the
region
scrolling
region
may
Horizontal
mode
has
been
set.
the
resolution
of
the
be
in
increments
should
only
scrolling
involved.
resolution
lowest
plane

different

C1]

Allows
either
<2>).
on
the
be
used
depending
All
number
of
Viper
by the
display.
required
pixels
same
bus
be
set
to
the
Adder
and
the
chip must
chips
so
is
of
the
barrel
shifter
control
width.
The
adjusted
control
of
the
with
Adder
combined
actions,
that,
chip
of
the
bus
is
and
all
scrolling
independent
rasterops
2
source
are:
width
(almost,
exceptions
xXmode PBTs,
scroll
and
tile
also,
boundary
registers;
Viper
origins,
of
and
the
of
amount
the
speed
memory
present
bitmap
The
will
of
in
fast
mode
course).
change,
operations
for
to
the
video
bus
is
compensate
adjusted
speed
BUS

WIDTH

bits

Bits

with

(starting

memory

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SYSTEM
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HARDWARE
COMPANY:
AND
COMMANDS

number

reduced

pixels

time.
<2>

Bit

00=4

bus

240

Bit

width.

The

video

bus

outputs

four

bits

bus

width.

The

video

bus

outputs

four

bits

nsec.

10=This
setting
11=16
Bit
bus
bits
60
every

SCROLL

CONSTANT
becomes

loaded
frame.

<4>

frame

one

nsec.

120

every

<0>

displayed

page

every
01=8

{2]

CONFIDENTIAL

Bits.
nibble
4

will

give

width.

The

undefined
video
bus

results.
four

outputs

nsec.

This

active

the

beginning

double

data

buffered;
of

the

following

scroll
For
constant.
left
this
scroll,
the
of
the
0 to
15
scroll,
magnitude
frame
time.
For
the
this
pixels
per
scroll,
right
nibble
is
the
of
the
scroll
minus
the
magnitude
one;
values
0 to
15
result
in
scrolls
of
1 to
16 pixels
frame
If
the
scroll
disable
time,
per
respectively.
bit
is
in
set
this
or
if
a
non-zero
Y
register
scroll
constant
is
in
the
Adder
programmed
chip,
this
nibble
must
be
zero.
If
the
region
being
scrolled
contains
some
set
for
low
Viper
chips
the
low
order
one
or
two
bits
of
this
resolution,
nibble
should
be
zero
for
left
scrolls
or
all
ones
for
scrolls.
right
X

Horizontal
O=Left.

scrolling.
programmed

scroll
Also
use
If
a
in
the

direction.
"0"

for

up,
Y

non-zero

Adder

chip,

down
scroll
this

disabled

and

is
be

constant

bit

must

zero.

1=Right.
<5>

O=Disable
scrolling
data
accessed
by
for
memory
plane).
must
be
register

(horizontal
this

Viper
Also,

set

chip
the

vertical)
(disables
bits

other
left

down,

and

all

writing
in

zero

this
X

scroll

constant.
l=Enable

<6>

Vertical
some

O=Down

l=Up,

scrolling.
scroll
asymmetries
scroll.
left

direction.
between
Also
used
scroll.
right

This

bit

and
up
with

down

scrolling.

disable

scroll.

for

accounts

[3]
PLANE

operations.
(or

ADDRESS
No
two

overlapping)

Bits.

Plane
address
for
should
be
Viper
chips
given
If
fill
address(es).
the
plane
-

the

axis
same

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AND
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is
register
addresses
plane
if

scroll

the

individually,
different
for
additional
<0>

must

(4]

restrictions.
Bit
the

Bits.

Viper

chip)

transfers.
in
a
low

This
resolution

the

UNIT

four

FUNCTION

registers
PTB

commands,

bitmap
modification

within

low

order

must

Viper

can

the

llll=

F=ONEs

AND

F=
F=

NOT(S)
NOT(S)

XOR
AND

AND

XOR

Ss
S

F=
F=
F=

D
D
D

OR
OR

two

15).

chip

will

low

four

This

Ss)

NOT(S)
S

separate

8
for
mode
"10"

bits.

The

Viper

Any

during

use

for

chip

logic
(D)

destination

the

through
and
or

uses

one

processor
is
used

(read-modify-write
register
source
previous

passed
logic,
foreground

F=NOT(D)

mode

with

from

has

OR
AND

source

F=NOT(D
F=NOT(D)
F=NOT(D)

F=NOT(D

3).

During
register

loaded
during
after
the
latter
and
resolution
complementer
to
select
the
result
(F)
color.

selected

(normally
cycle),

F=NOT(D

have
3.4.2

registers
be

the

F=ZEROs

block
in

Viper

multiple
chip.

addressed

with

0000=
0001=
0010=
O01l1l=
0100=
Q101=
0110=
Qlll=
1000=
1001=
1010=
101l1l=
1100=
1101=
1110=

could
section

are
to
sub-planes
These
are
system.
essentially
a
of
6 bit
but
address,
plane

command.
function
the
bitmap.

contents

bit
the

planes

during

Bits.

axis

See

regions

address
16

unit
function.
Logic
combines
the
word
read
destination
a
cycle

unit

registers

which
bus
during

I/D

2 Bits.
Z axis
block
needed
if
more
than
be
in
addressed
the
the
bits
high order
blocks
must
separate
commands.

rasterop

<0>

(or

the
however

process,

permanently;
fill

page

scroll

arrangements.

bit

data

the

update

address

exchange

LOGIC

the

Z mode
by
be
established
loads
the

process
then
different
address
plane

Addresses
resolution

<4>

loaded

CONFIDENTIAL

cycle)
(S)
memory
a

the

background

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AND
COMMANDS

O=Use
l=Use

<4>

<5>

<6>

mask
the

complement

OQO=Use mask
l=Use
the

O=Use
l=Use

<7>

CONFIDENTIAL

l.
of

mask

complement

mask

complement

source.

the
source.

OQ=Enable

resolution
mode
for
source
the
logic
resolution
(see
mode
register
description,
for
discussion
of
effect).
resolution
mode
for
the
source
logic
bits
to
the
unit
(pass
through
logic

The

combining

adjacent
register

mode

bits,

regardless

setting).

four

have
16 bits.
The
registers
in
a
as
viewed
on
the
word,
pixel
screen
the
MSB
is
the
most
All
four
right
pixel.
the
can
be
loaded
bus
I/D
load
registers
by
register
commands.
The
mask
and
source
can
also
be
registers
loaded
transfers
The
by data
during
rasterop
cycles.
source
and
fill
can
be
loaded
with
constant
registers
data
Z
(solid
a
color)
axis
load.
by
register

[8]

the

MASK

following

left
and

which

[9]

bits

MASK

are

mask
mask

which

bits

independent

unit

function

outputs

rasterop)

ANDed

bit).

If
be

must

control

cycle.
are

the

by
of

that

followed

logic

the

with

each
other
and
with
the
those
bits
in
involved
a
those
bits
are
modified
that
are
masks
from
AND
(a one
the
enables
Resolution
mode
follows
logic
1 is
both
used,
only mask
enabled
or
disabled
to
together

word

(normally

logic

select

unit
the

for

each

pixel.
The

cycle.

bits.

all

and

control

data

registers

(controlled
The
outputs

Source
the

complementer
unit.
logic

the
"00".

mask

two

for

destination
colors

only
three

function.

complementers
masking

cycle)

the

defines

that
all
of

prevent

SOURCE

Used

2.
Used
register
a
read-modify-write

complementers
registers).

are
complementers
(which
edge mask

selected
modification
AND
the

mask

modified

are

The

[A]

mask

modified
by a read-modify-write
1 loads
mask
2 with
the
same
is
effective.

Programmable

LSB

most

Programmable

Loading
one
only

page

loaded
combine

by
with

foreground
The

resolution
Z axis

source

data

mode
address

logic
for

source

memory

the

background
is
processed
by
before
entering
this
is
register

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CONFIDENTIAL

page

Data
that
will
be
inserted
into
words
to
memory
fill
the
blank
created
a
by
scrolling.
Normally
space
solid
color
fill
is desired
and
will
be
with
a
provided
Z axis
if
loaded
care
should
be
taken
to
load;
directly,
set
all
of
the
bits
to
one
to
the
subplane
same
value.
This
is
double
data
buffered;
loaded
becomes
active
on
the
frame.
The
Z
following
axis
address
for
this
is
"10".
register
FILL

corresponding
register

the

Because

within
of
the

left

scroll
word
scroll.

most

actually

the
to

programmed

boundaries

region
Viper
chips

the

word,

place
possible

(for
position
cannot
chip
specify

and

the

‘region.
the

must

right

most

The

be
which

word

are

Viper

chip

boundaries

extension),

but

region

future

can

told

set

bits
be

can

bit

any
the

Adder
closer
than a multiple
of
those
boundaries
should
be
four;
therefore,
only
selected
that
select
of
four
bits.
When
groups
loading
these
the
low
4 bits
8 or
of
these
registers,
only
are
in
8 or
4 bit
bus
width
registers
significant
modes,
These
are
double
respectively.
buffered;
registers
loaded
becomes
active
on
the
frame.
following
the

boundary

data

[Cc]

LEFT

SCROLL

bits

All
to

are

clearing
the

contained

(E]

through
RIGHT

SCROLL

one

clear
in

to
the
that
pixels
word
that
contains
the
left
other
bits
(all
set).
this
Normally,
all
bits
from
the
on
the
pixel
edge
of
the
but
if
both
are
word,
edges
then
bits
from
the
left
word,
only
are
clear.

corresponding

the

BOUNDARY

from
the
that

boundary
are
edges
bits

set.

are

BACKGROUND

logic

FOREGROUND

the
"ol".

bits.

(all

COLOR

unit.

The

COLOR

logic

unit.

The

foreground
The

LSB

the

(LSB

and
the

scrolled)

not

for

one

address

most

which

the
this

for

background
left

zero

address

case

all

output

registers

pixel

both

word,

same

Selected
axis

edge)
through
that
is
to
pixel
the
of
right
edge
the
right

most

contains
unless
set),

(left

LSB

right

Selected
Z axis

The

Bits.

clear

are

edge

corresponding

region

Bits.

edge

right

bits

All
bit
scrolled

the
word
other
bits
is
between
words
in
contained
the

the
"11".

(F]

MSB

in
the

the
be
the

are

be
scrolled
of
the
region

edge
requires
through

(D]

BOUNDARY

word,

16
as

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viewed

pixel.
register
The

the
Both
load

outputs
bit-by-bit

mux

(the

the

old

store

of the
basis.

to/from

controlled

[10]

CSR

CSR
bank

Adder

(14]

CSR

selected
command

(15]

CSR

CSR
bank

I/D

its

contents

Adder

Viper

bus

during
and

chip

control

chip

within

the

during

Viper

rasterops.
is

rasterops
occurs

for

once

each

cycle.
1

first
is

second
source
is
enabled

the
source

source

enabled

read
in
the

bank
Adder

chip

the
source

read
the

if
bank
1
Adder
chip

Controls
is
selected

the
and

command

Controls
and

destination
read-modify-write
the
destination
is
enabled

if
in

the

first

the
1

source

enabled

read
the

bank

Adder

chip

Controls
and

second

the
2

source

enabled

read
the

if
bank
2
Adder
chip

Adder

(17]

transfer

selected
command

{16]

The
data
devices

registers.

the

Controls
and

chip

Reserved

can

[13]

selected
command

C12]

6
the
other
-

by
Controls
and

page

MSB

registers

memory

selected
command

C11]

mux

destination
is
used

chip and
Addressing

the

CONFIDENTIAL

is
the
most
right
be
loaded
by I/D bus
and
load.
by a Z axis
register
unit
select
these
on
logic
registers
as
the
to
of
one
side
the
mask
inputs
then
selects
between
this
new
data
and
Either
of
these
two
data).
to
Z mode
data
PTB
pass
during

the
commands

RAM
STORE
RAM controls

update

and

screen

mask

registers
operations.
CONTROL

HARDWARE
COMPANY
AND
COMMANDS.

Controls
is
selected

chip

command

destination

the
and

the

read-modify-write
destination

enabled

Reserved
NOTE

These

the

assume

and

CSR

CSR
of
functions
are
defined
assignments
Adder
The
not
Viper
chip.
chip does
of
that
CSR
0
CSRs,
any
assignment
except
are
first
linked
to
the
and
delay
register
and
5 are
the
linked
to
second
delay

the

DRAGON
DRAGON

VIDEO
CHIP

Each

CONFIDENTIAL

HARDWARE
COMPANY
AND
COMMANDS

SYSTEM
REGISTERS

the

has

words

CSR

bit

following
the

load.
Selects
2 Bits.
External
from
the
which
data
I/D
incoming
read.
a
be
loaded
memory
following
00=None.
0l=Source.
mask
2.
1 and
10=Mask
ll=Mask
2.

<Q>

incoming

(from
memory
00=None.
01=Source.
10=Mask
ll=Mask

1 and
2.

other

Barrel
‘

excessive
can

remainder
controls
4

any

one

the

address).

CSR

(for

control.

delay

word

output

one

pegister
2
0=Do
l=Do

plane

a
fast
When
executing
formed
is
usually
To
avoid
source
words.
of
two
of
each
the
to
the
source
reads
raster,
previous
so
that
its
in
a
held
be
register
delay
This
bit
next
word.
with
the
be
used
can
CSR
is
when
the
active
one
register
delay
other
and
controls
the
source
1)
delay
1 or
source
is
5 (for
active
CSR
when
the

shifter

rasterop,
a
part

word

during
one

any

be
should
bus
I/D
read
memory

one

data

output.
output.

l=Enable

mode
from

Only
shifted

planes
for

O=Disable

<5>

control.
its
output

mask

output
(ie.

cycle

shifter)

barrel
the
read.

bus
I/D
enabled
all
for

<4>

data

into
will

into
the
Selects
register
local
the
memory
plane
will
be
loaded
following

load.
from

Internal

2 Bits.
which

<2>

assignments:

bus

100

page

load

not

load

delay

With
the

two

CSR

longer

delay
registers,
enable
delay

separate
address,

the

necessary.

should

selected
is

bit

programmed

NOTE

There

may

destination
two

registers

reason

CSR

may

ever

than
other
be
unnecessary.

program

"000000";

either
these

mee

DRAGON
DRAGON

VIDEO
CHIP

4.2.2

Instruction/Data
This

section
is

devices

and

Dragon

video
4.1.2.

section

I/D

rasterop

SYSTEM
REGISTERS

included
to
with
the
help
for
required
understanding
Programming
requirements

instructions

bus
and

further
Most
bus
I/D
bit
data
transfer.

Processor

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byte.
by

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the

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the
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instructions

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accompanied

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CONFIDENTIAL

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Bus

system.

subinstruction

4.2.2.1

HARDWARE
COMPANY
AND
COMMANDS

chip

Adder

16
the

chip

is
always
transmits

never

bit
word

data

initiated
it
without

LOAD

caaf onemf ae wee
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all
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in
each
of
the
16
register,
of
the
addressed
Z block
(in
the
sub-planes
Viper
chips
that
are
also
with
the
contents
of
the
bit
selected),
chip
selected
low
four
bits
of
the
address
by the
plane
(programmed
into
each
of
the
If
a
is
set
for
a
low
Viper
chips).
Viper
chip
resolution
a
of
bits
or
a
nibble
is
into
mode,
pair
duplicated
each
of
the
8 pairs
or
four
nibbles
of
the
selected
register.
2Z
axis
addresses
are
defined
as:
register

planes

00=Source.

01=Foreground.
10=Fill.

ll=Background.

DRAGON
DRAGON

VIDEO

SYSTEM
REGISTERS

CHIP

EXTERNAL

HARDWARE
COMPANY
AND
COMMANDS

tem

INST:

ape

Adder

pee

penn

Chip

I/D

pen

penn

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devices

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this

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external

using

I/D

specification.
<7>=0
by bit

distinguished

00H
is
reserved
to
7FH
used
be
may

for
for

NOP.

Any

external

the

instructions

bus
and

that
a
will
programmer
device
loads.
The
register
used
Adder
by the
chip to
for
the
of
sake
completeness.

external

instructions
and

pent

pon

Instructions

I/D

rasterops

are

listed

are

OPERATION

INST:

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SUBINST:

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INST:

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INSTRUCTION]

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Information
section
5.4.1

the

Viper

penn

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direct

only
the

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Instruction

byte.

pee

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instructions

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The

specific.
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provided

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SUBINST:

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External
instruction
instruction
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102

page

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The

CONFIDENTIAL

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onof

RIGHT

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identical

essentially

the
is

Viper
chip
except
generated
register
as
of
a
an
read-modify-write
cycle
accompanying
part
is
set
to
to
transfer.
"0"
select
the
to
F/B
bitmap
processor
and
to
"1"
to
select
the
background
foreground
register,
cannot
be
used
for
PTBZ
the
source
register
operations
register;
in
the
are
too
for
because
the
Viper
chip
propagation
delays
long
The
of
the
source
use
unit
the
through
register.
logic
path
in
the
PTBZ
An
"10"
assumed
command.
is
function
register
edge
in
one
bit
the
is
select
the
mask
to
memory
provided
being
axis
with
Z

load,

that

the

instruction

DRAGON
DRAGON

VIDEO
CHIP

written.

SYSTEM

the

However,

the

are

address
of
the

description
Z

AXIS

data

is
that
which
was
cycle
not
the
concurrent
cycle,
loads
interleaved
register
The
and
mask
left
right
and

CONFIDENTIAL

HARDWARE
COMPANY
AND COMMANDS

REGISTERS

written

being

transmitted
these

with

destination

specifiers

edge

equal
for

bit;
Active

current

for

this

complete

instruction

below.

Cycles

READ

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instruction

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used
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by the
chip during
transfer
with
an
processor
along
accompanying
memory
The
bit
address
the
in
bit
the
cycle.
specifies
memory
which
the
color
is
(The
being read.
Viper
chip generates
barrel
shift
constant
from
the
bit
address
and
the
low
of
the
Each
of
address.)
the
addressed
plane
Viper
chips
block
transmits
its
bit
if
(or
a
low
resolution
bits,
the
bus
I/D
appropriate
pin.
to

ACTIVE

memory

I/D bus
previous
Z axis
really
ordinary
only
rasterop
cycles.

are

the
selected
mask
see

the

by
the

during

cycle;

103

page
-

CYCLE

FOR

MEMORY
ee

INST:

fitlaid

This

instruction

NOP

afce
DIR

for

four

by
chip)

bits
the
on

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SUBINST:

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Adder
with
an
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chip
control
the
of
the
handling
read
data.
selects
the
CSR
location
controlling
(and
therefore
a
and
will
be
either
0, 1, 4 or
delay
register),
5.
The
subinstruction
controls
the
use
of
the
barrel
shifter
to
the
source
data
with
the
destination
location.
The
barrel
align
shifter
has
a
32 bit
and
selects
a
16 bit
as
an
input
segment
If
the
shift
constant
is
left
most
16 bits
are
0, the
output.
if
the
shift
constant
is
the
most
bit
of
the
selected;
15,
right
left
word
and
the
left
15 bits
of
the
word
are
selected.
right
The
to
or
the
left
word
of
the
barrel
shifter
can
inputs
right
come
either
from
the
data
read
on
the
current
or
from
the
cycle
data
in
stored
the
that
to
previously
delay
register
corresponds
the
addressed
CSR.
LD bit=0,
the
current
word
is
used
for
If the
the
left
if
LD
the
the
is
used
for
bit=1,
input;
delay
register
the
The
is
selected
left
input.
right
input
similarly.

accompanying

memory
The
CSR

generated
to
cycle

DRAGON
DRAGON

VIDEO
CHIP

ACTIVE

CYCLE

SYSTEM

REGISTERS

fame pa
pn
fm man
SUBINST:
This

[FNC

pan

pen

LEFT

fee

instruction

written
left
address
one

the

pee

page

104

pen

RIGHT

pan
em

pew

generated
cycle

penn

pent

tenn

tenant

MASK
poe

CSR
be
control
mask

pent

Adder
chip
control
the
selects
address
2 or
6.
either
the

The
will
mask

pet

ADDRESS |

SELINOPICSR

MASK
pe

anpan
pan

accompanying
read-modify-write
and
the
register
edge masks.
and
CSR
location,
controlling
and
four
unit
function
logic
The

CONFIDENTIAL

READ-MODIFY-WRITE

FOR

INST:

HARDWARE
COMPANY
AND
COMMANDS

registers

with

logic

unit

the
of
selected.

One

the

bits
to
be
to
select
the
sends
the
edge
of
is
the
bit
address
the
The
left
word.
mask
mask
is
the
bit
The
most
to
be
modified.
right
pixel
if
of
the
to
be modified.
most
Therefore,
right
pixel
0 is
values
are
the
same.
to
both
mask
is
be
modified,
pixel
most
15
is
the
MSB or
LSB
or
left
most
right
pixel.
pixel;
subinstruction
within

the

DRAGON
PHYSICAL

VIDEO

SYSTEM
HARDWARE
CONFIGURATION

PHYSICAL

COMPANY
CONFIDENTIAL

105

page

CONFIGURATION

For
to

complete

Adder

Chip

the
Adder
and
specifications
Viper
chips
their
referenced
in
section
respective
specifications,
This
section
describes
wide
system
interconnection,
timing
and
issues
in general
terms.
functional
Specific
implementation
are
also
referenced
in section
1.2.
The
examples
implementation
in
this
section
the
recommended
suggestions
or
intended
represent
but
are
of
system
course.
configuration
flexible,

refer
1.2.

5.1

The

surface

Pins

Adder

chip

mount

grouped
pins,
the
high order

package.
the
pin
pin.

5.1.1

Processor

DAT<15:0>

66,

70,

71,

72,

Processor

pin,

leaded,

indicated
in order,

[57,
73,

Data

data

square,
for

[];
starting

with

Interface

(Input/Output)

69,

Local

contained
in
an
Pin
numbers
are
numbers
are
listed

74,

59,

60,

63,

64,

65,

76]

Tri-stated

Bus.

unless

58,
75,

high,

and

-AS

81,

82]

receive
and
-DS

are

low.
-

AD<5:0>

Latched

connecting
-

local
select

chip
-

and

the

Read/-Write.
by

facilitate
bus.

multiplexed

should

latches
address
is
provides
be
asserted

AD<5:0>
Adder
for
only
on

the

During
rising

write,
read,
edge

falling

edge

the

level
DAT<15:0>

low

disables

Request.
for

Indicates

read

write

-DS.

[11]

(Output)

[1]
Bus

Data

<-AS

processor

data.

Latched

REQ
DMA

During

(Input)

cycle.

chip

-AS

[83]

processor
DAT<15:0>
buffers.

Processor

Adder

cycles.

Strobe.

output

80,

edge

bus.
and

function
bus

(Input)

latches
enables

Falling

processor

chip

-DS
Data

79,

[84]

Strobe.

Adder

78,

Address.
an
Selects
the
of
falling
edge
the
AD and
DAT
pins

(Input)

-AS

Address
from

[77,

(Input)

Processor

DMA

Enabled
controller

Adder
service

chip
request

request
or

enable
local

SYSTEM
VIDEO
CONFIGURATION

DRAGON
PHYSICAL

[10]
Interrupt.

enable

And

VIPER

(Output)

[52,

51,

Address

addresses

for

bitmap.

one

sequence
column

and

times

ADDCLK

(Input)

[25]

Bitmap

Memory

Address

memory

cycle;

two

(Output)

128/-16

Bitmap
for
selects
write

Memory

read
128
of
a
pair
16
bit
(also

R/-W

(Output)

Bitmap
major
minor

Memory
or

addresses

47,

48,

Nine
minor

Clock.

cycles

per

minor

cycles

16
for

by
major
cycle.

the

row

major

cycles

per

memory

cycle.

major

mode).

bit
a

column

5.6.1.

selects

High
(in

write

45,

46,

presented

in’section

described

bit

cycle

Low

read

mode).

[36]
If

cycles.
external

read
or
indicated
the
implements

Selects

Read/-Write.

minor

cycle,

49,

50,

[37]
Select.
Cycle

bit

Interface

Chip

row
and
Bits.
Multiplexed
are
clocked
out
Addresses
for
a
addresses
column
eight
for
a
minor
of
row
and
column

and
each

row

and

cycle,

Address

Bitmap

The
and

the
-INIT.

40]
Memory

43,

ADDCLK;

clears

FIFOs.

Memory

MEMAD<10:0>

44,

interrupt

Adder
processor,
chip command
and
IDD
and
counter
address
bus
drivers
on
the
Disables
I/D
of
SYNC
first
occurrence
following

Resets

and

halts
commands,
address
output
Adder
chip until
of
deassertion

chip
interrupt.

[2]

(Input)
Initialize.

5.1.2

Adder

Enabled
by
local
processor

for

INIT
Bus

106

page

(Output)

-INT
Processor

CONFIDENTIAL

COMPANY

interrupt.

processor
~

HARDWARE

write

timing

write
for

for
a

required

RMW

sequence.
-

-WE<3:0>

(Output)

[35,

34,

33,

32]

enables
to
write
are
in memory
words
that
to
writes
-WE<0>
or
the
scroll
of
outside
clipping
regions.
most
on
the
screen).
nibble
low
order
the
(left
controls
address
for
each
column
values
is
A set
of
provided
for
are
used
Adder
Only -WE<1:0>
chip.
output
by the
4 bit
for
-WE<0>
is
used
width
and
bit
bus
mode,
only
Low
enables
width
mode.
bus
writing.

Bitmap
disable

Memory

Write

Enables.
nibbles

Four

DRAGON
PHYSICAL

VIDEO SYSTEM
CONFIGURATION

FORCE

frame

major
writing

that

participating
SCROLL

Scroll
are

most
right
for
provided
chip during

Address

reads,
device

sensing
address,
be
may
removal

scrolling
planes

not

scrolling.

each
a

all

region,
A

state

except
output

column
address
output
refresh
major
cycle.

screen

bus

bitmap

for

the

words
the

that

is
Adder

[28]

suspended

lowered.
asserted

When

from

the

updates
is
addresses

Scrolling
to

high,

memory

addresses
that

because
have

may
used

are

down
in
all

forced

allows
the
Adder
to
chip
and
then
all
cycles
suspend
(minor)
The
address
bus
memory
cycle
activity.
minor
become
tri-stated,
cycles
dummy 16 bit
and
continue
An
unaltered.
external
major
cycles
can
take
over
of
the
that
it
wishes
any
cycles
by
the
and
128/-16
R/-W
and
its
own
pins,
supplying
data
and
control.
Refresh
and
scroll
cycles
lost
(if
the
external
but
ignored
by
device),

NOT

FIFO

107

page

[39]

Disable.
its
current

complete
update
is

during
be

can

High indicates
in
a
scrolling
word
in
the
region.

(Input)

ADS

cycles

down

(Output)

Enable.
contained

CONFIDENTIAL

[38]

(Output)
indicates

High

‘COMPANY

HARDWARE

not

indexes

stale

access

address
continue

can

when
when

recommended
held
in
the
or
offsets

FIFO
ADS
is

output

this

address

pin
output
time

the

laser

the
the

operations
bitmap
printer.

they

memory.
NOTE

This

function

printer
so

that

I/D

ID<7:0>
ID

IDCTL

Chip
select

indicated

chip

memory

can

dump

speed

for

appropriate

used

allow

external

bitmap

processor
function

refresh/scroll

directly.

memory

bit
Eight
cycles;

unless

PTB

[22,

21,

bus

always

20,

tri-stated
command
I/D

19,

18,

transmits

16,

14]

15,

during

the
two
during
is
being
executed.

the
data

[12]

(Output)
Select

for

screen

(Input/Output)

Bit.
instruction

cycles

Adder
hardware

Bus

two

intended

external

at
memory
It
also
may
an
alternate
access
the

5.1.3

suspend

Control.

registers.
by a

Selects
Scroll

high

during

update
select
execution

chip

scroll

chip

registers

are

commands

the

HARDWARE

VIDEO
SYSTEM
CONFIGURATION

DRAGON
PHYSICAL

ICS

5.1.4

Monitor

BLANK

(Output)
Composite

[7]

(Output)

[6]

CMPSYN

Timing

Blank

Signal.

Video
Composite/Horizontal
if
horizontal
separate
sync

(Output) [5]

VRTSYN

Video

Vertical

5.1.5

PHI1,

Phase

blank.

Composite

Sync.

sync

(or

used).

are

syncs

Vertical

Sync.

sync;

used

for

separate

polarity.

Programmable

syncs.

indicates

High

polarity.

Programmable
-

108

page

Video
-

COMPANYCONFIDENTIAL

Clocks

PHI2

Period

PHI3,

PHI4

Phase

1/4

Period

major

Clock

1/8

cycle.
27]

[26,

clocks.

Non-overlapping

Inputs.

major

clocks.

Non-overlapping

Inputs.

(Input)
4

55]

[53,

(Input)
Clock

cycle.

[8]
-SYN/REQ
(Output)
that
a
Low
indicates
Request.
Synchronization
System
initiated
external
should
be
timing
by the
system
sync
in
the
following
major
cycle).
(normally
generator

Reset

SYNC

high

state

the

assertion

SYNC.

[9]
(Input)
Synchronization.
the
during

Issued
external
by the
timing
of
a
interval
to
first
part
sync
a
the
Adder
of
reset
Also,
chip timing
logic.
phase
will
be
buffered
double
of
number
registers
updated.
All
not
a
reset
clock
is
this
Note
that
chip
pin.
the
entire
held
frozen
be
must
during
sync
signals
two
interval
major
cycles).
(normally

System
generator

5.1.6

Power

VDDL3,
VDDL2,
VDDL1,
67]
41,
54,
17,

VDDI,

VDDM,

VDDC,

VDDD

(3,

23,

62,

DRAGON
PHYSICAL

VIDEO
SYSTEM
CONFIGURATION

Power.

Plus

address

bus,

and

clocks,

data

for
bus.

Return.

bus,

clocks,

VBB

[31]
bypass.

and

memory

GNDM,

GNDC,

logic,

I/D

[4,

GNDD

bus,

6l,

24,

address

memory

is
contained
in
a
68 pin,
leaded,
chip
square,
Pin
numbers
are
indicated
in
for
[];
package.
the
are
in order,
listed
pin numbers
starting
pin.

Viper
mount

grouped
pins,
the
high order

5.2.1

Bitmap

DIO<15:0>

Bitmap

Data

drivers

are

(Input)

[10]

Enable.

High
in

word

most

Enable.

bitmap

R/-W

all

scrolling
region.

Minor

internal
logic
bit
process).
is
that
logic

this
be
written
This
output

high,
to

cycle.
high.

16,

15,

13,

14,
output

DIO<15:0>

bus

region,

except

words
for

signal

allows

rasterop

the

tri-state

during
driver

tri-stated

[65]

(Input)
or

the

When

memory

write

128/-16

17,

[25]

(Output)

Major

indicates
in

contained

18,

Bus.
The
DIO<15:0>
when
is
R/-W
high.

Input/Output
tri-stated

Scroll
that

right

[19,
3,

SCROLL
are

with

Memory

(Input/Output)
8,

11,

Plane
the
scroll
when

bus,

bus.

Pins

Chip

I/D

logic,

109

page

30]

(29,

12,

for

supply

Ground
data

Power

Viper
The

volts

COMPANY.CONFIDENTIAL

GNDI,

Spare

surface

GNDL1, GNDL2, GNDL3,
13,
42,
56, 68]

VBB

5.2

HARDWARE

When
this
activates
high,
signal
that
is
associated
with
major
cycles
When
this
activates
internal
low,
signal
associated
with
minor
(16 bit
cycles

Cycle.

(128

process).
R/-W

(Input)

Bitmap
DIO<15:0>

Memory
and

[64]
Read/Bitmap
PE

output

Memory
drivers

Write.
will
be

When

tri-stated,

high,

all
and

DRAGON
PHYSICAL

HARDWARE

VIDEO
SYSTEM
CONFIGURATION

the

VIPER

chip

low,

all

DIO<15:0>

COMPANY

receive

may

and

CONFIDENTIAL

bitmap
PE

data.
will

memory

drivers

output

110

page

When
be

enabled.
When
latch
-

(Input)

[66]

Clock.

When

R/-W
will

LTCLK
on
the
LTCLK

the

is.

low

cause

and
valid

DIO<15:0>

lines.

major

per

5.2.2

R/-W

of
LTCLK
DIO<15:0>

edge

I/D

ID<7:0>

of
R/-W
DIO<15:0>

falling
data

memory

Latch

data

the

low,

bitmap

LTCLK

falling

128/-16

and

128/-16

is
used
lines.

are

latch

128/-16

is
used
lines.

edge
the

data

memory

rising

edge

the

shifted

must

high,
the
bitmap

high,

scrolled
There

eight

[31,
32,
33,
35,
(Input/Output)
36,
bus.
input/output
Normally
or
the
ID<7:0>
data,
instructions

38,

and

Video

VID<3:0>
Video
these

rising
-

PHI1,

axis

executed.
will
be

ignored.

instruction,

instruction

ID<7>

the

Otherwise,

will

arriving

Output

(56,

Screen

lines

57,

59]

58,

refresh
data
the
rising

edge

shifted
out
of
ALPHA.

Clocks

ALPHA
Data

receiving
arriving

(Outputs)
Output.
output

5.2.4

execution

during

the

high,

are

instruction

5.2.3

enabled

instructions.

While

Select.

and
CS
latched

46]

39,

tri-stated
output

[40]

(Input)

Chip

cycles

Bus

to
receive
drivers
can
active
I/D

out

cycle.

Instruction/Data

(Input)

[55]

the

VID<3:0>
of
ALPHA.

edge
PHI2

Non-overlapping

(Inputs)
clocks

lines
will
Period

[50,

shifted
of
1/16

out
a

the

major

cycle.

49]
that

determine

overall

timing

and

DRAGON
PHYSICAL

HARDWARE

VIDEO
SYSTEM
CONFIGURATION

control

the

VIPER

COMPANY

CONFIDENTIAL

Period

chip.

lll

page

1/4

major

cycle,
System

Viper

Dragon

5.2.5

VDD

Plus

Volts

30
535°"

5.3.1,

Power

Return.

VBB,

CAVITY

system
in

memory
control

write
in

5.3.1

Clock
The

which

and

5.2.1,

[61,

67,

27,

28,

44,

ground,

logic

ground.

connected

must

CAVITY.

clocks
are
discussed
in
in
section
address
5.3.2,
data
in
section
memory
timing
in section
and
video
5.7.1,

section
enable

section

5.6,

logic

section

5.7,
data

and

5.8.

Generation
and

Viper

described

completely
in

briefly

PHI1,

PHI3,

chipsin

in
the
1.2:

Basic
Determines

PHI2

PHI4

Serial

require

sections

Adder

and

bus

following

5.1.5,

Viper

clocks

system
I/D

the

5.2.4,

ALPHA

Video

output

and

for

both

the

Adder

clocks

for

the

Adder

Viper

chip.

timing.

arithmetic

clock

clocks,
5.1.2,

chipspecifications

chip.
©

Logic:

45;

Viper
chip
synchronization

Viper.
Oo

68,

60]
VBB

and

section

referenced

chip

Timing

Adder

are

Driver

bias.

Speed

generation

54]
(53,
Supply

(Drivers:

Adder

The

29,

VSS

High

phase

remainder
of
the
double
buffered
that
this
is
not

Power

Substrate

5.3

the
of

a
number
Also,
Note
updated.

will

the

synchronizes

states

pin.

reset

asserted,

chip

system.

registers

When

Sync.

internal

[63]

(Input)

SYNC

for

the

VIDEO
SYSTEM
CONFIGURATION

DRAGON
PHYSICAL

Som

ADDCLK

HARDWARE

Address

COMPANY

clock

output

CONFIDENTIAL

for

the

Adder

page

112

cycles)

for

chip.

ENN

ORE

for

Data
LTCLK
clock
the
Viper
chip.
-

bit

128

cycles

(major

ety
cl
SiS
is
GONG

convenience
the
clock
throughout
specifications,
in
discussed
increments
of
30
nsec;
however,
generally
Phi
4 is
114
actual
minimum
for
3 and
rather
Ghar
nsec,
period
120
The
maximum
is
at
the
nominal
nsec.
least
twice
SION
period
All
minimum.
other
clocks
scale
SAAR
accordingly.
For

timing
the
than
the

ith
Ne
RAL
RR

eee

skew
between
two
of
the
above
The
clocks
cannot
exceed
any
5 nsec.
This
can
be
achieved
generally
only
by deskewing
a
common
of
these
clocks
clocked
at
30 nsec,
latch,
through
in wire
and
will
because
differences
consume
a
delays
loading
the
allowed
of
skew.
significant
part

+/-

all

Settee
waveforms
of
all
clocks
ADDCLK
and
The
LTCLK
are
except
in
Adder
and
can
be
found
the
and
Viper
specifications.
and
waveforms
for
ADDCLK
LTCLK
are
The
<anetG
dependent on the selection
Considerable
of
for
the
is
in
i
bitmap.
range
memory
permitted
and
the
earliest
latest
is
these
cinid
possible
signals;
timing
shown_
th
and
and
in
Adder
of
the
specifications,
Viper
any placement
nt
earliest
and
between
the
latest
is
transitions
permissible.
ny
nine
or
two
must
have
minor
ADDCLK
cycles
per
major
cycle
per
have
for
LTCLK
must
or
cycles
Sinn cycle.
eight
every
major
cycle
meme
minor
even
LTCLK
does
not
clock
of
data
at
cycles;
though
pair
it
is
still
minor
used
used
the
ene
during
cycles,
internally.
pins
for
sete
Sater
seme

fixed

Seminit
Ger

meme
5.3.2
SumLU

Sync

System

aut
init

Once

mea

tit

synchronization

ane

seth

writing,

Semenrobust

synchronized
once

periodic
static

utnewer
Synchronization
unenaieuser

(vertical

frame

per

are
timers
be
required

perceivable

synchronization
and
discharge
activity

time
in
is

the

other.

startup,
system
all
could
corrupt

occurs

scan

each

because

but
future
makes

other
when

screen),
Ideally,
screen

the
system
environmental
no

screen

all

this
loss

system
should

only

display
much

effects.
refresh

and
more

other

progress.

eetronss
is
ALL
and
clocks
accomplished
by freezing
Synchronization
for
two
in
(one
major
cycles
timing
signals
compute
cycle
mete memory
the
and
the
SYNC
called
Adder
the
interval,
sync
asserting
chip),
all
the
first
of
Adder
and
the
Vipers
during
part
sync
pin on the
The
for
the
first
clocks
must
be
interval
major
cycle).
(usually
of
of
the
start
at
any
major
cycle
(rising
edge
every
stopped
of
the
X SCAN
that
is
other
PHI2)
by the
programming
permitted
in
as
described
section
4.1.1.5.
the
COUNT
registers
During
sync
in
the
must
remain
the
clocks
states:
interval,
following

snes

DRAGON
PHYSICAL

VIDEO
SYSTEM
CONFIGURATION

PHIL
PHI2
PHI3
PHI4

Senn

SRNL
S

MeD

stuLInAD
ANNA
GARI!
“COMA
NONE:

After

Low

The

sync

SOE

SYN/REQ

TS programmed

timing

memory

interval,
of
cycles
clocks
only
sync

the
to

RENNES

time

the

is
The
SCAN

respond
major
cycle

signals

the

required.

all clocksinterval
sync
don't

that

proceed

must

freeze

had

never

are

the

exactly

occurred.
ones
that

interval.

sync

interval

signal..

should

SE logic
the

the

needed

High
High
High

major

two

GRRBasically,

ENED

Other

the

113

page

High
High

ADDCLK
LTCLK

Sei

CONFIDENTIAL

Low

ALPHA

are

COMPANY

00000000

Sat

Stim if

HARDWARE

when
of

initiated

exact

Adder

the
this

timing
registers,
SYN/REQ by
COUNT

signal
The

starting

clock

syne

issues

chip

generating
interval

boundary.

SOL

SERINIS
each
SenLARh

multiple

other,

stint systems.
sucht systems,

Dragon

display

systems

should

clock

there
The
clock
and
then
all

the

will

systems,

are

clocks

synchronized
for

generator

responds

generator
stops
This

to
all
aemethin
systems.
of
activities
sinimin
euimeem
are
programmed

one

SYN/REQ

all
systems
the
memory
that
their

synchronize
assuming

all
from

the
of

one

issues

and
and

the
SYNC

display
formats

screen

identically.

semen
bus

autnunm
Processor
eet interval.

activity

proceed

can

normal

during

the

sync

enw

Seana
einai

5.4
<nnettts

I/D

Bus

site
The
bus
Instruction/Data
tester
and
and
the
Adder
comminien
Viper
chips
to
it.
Because
site be connected
“are
no
direction
it
controls,
<Eianmib
bus
to
its
drive
this
increase
eniiniis

is
to

the
is

intended

directly

any
bus

that
and
buffers

to
be
tied
external
devices
is
bi-directional

possible
capability.
not

put

might
there
on

evn

itis
for
siimetin
retin 24

The

devices,
ewhitih
other
‘mene

maximum

operation
to
32 Viper
DC

the

loads)

load

capacitive
at

full

chips
wire
are

clock
per

rate.

Adder

routing
connected

allowed
This

plus
is

compact.
to

the

bus
is
400
I/D
pf
be
sufficient
for
number
of
TTL
TTL
devices
(or
it
be
bus,
may
necessary
this
could
be
I/D
bus;
on

the

should
limited
If

I/D

a
minimum
on
the
to
capacitance
suniulve
guarantee
if
needed.
sarnante
capacitors,
by discrete
provided
winaauh
two
The
bus
transmits
of
command
from
the
I/D
Adder
wiitsnse
bytes
of
data
two
from
the
Adder
or
chip and transfers
bytes
samen
Viper
minor
Transmissions
are
to
anvvess
cycle.
chips
every
synchronized
A byte
erase memory
as
is
transmitted
each
cycles,
required.
during

DRAGON
PHYSICAL

sive the
PHI1
ARAN

SYSTEM
CONFIGURATION

VIDEO

PHI1

four
and

Node

PHI2B
Stern PHI2A

and
PHI2

two

starts

and

HARDWARE

PHI2

minor

pulses

pulses
cycle
The

PHII1A.

are

COMPANY

in
a
labeled
and
the

command/data

CONFIDENTIAL

minor
A

Each

cycle.
and

The

is
is:

sequence
sequence

114

page

the

rising

PHI2B,

two

edge

PHI1B,

MeeRt

1.
2.
3.
4.

PHI2A
PHIIA
PHI2B
PHIIB

ScLEEN

5.
6.

sietnittt

Siti

PHI2A
PHIIA
PHI2B
PHI1B

9.
10.
11.
12.

PHI2A
PHILA
PHI2B
PHI1B

13.

ete.

RINNE
SANK

Instruction
Subinstruction

l
1

data
byte
data
High byte

Low

mtAhINE
Sinn

Instruction
Subinstruction

2
2

data
data

Low

byte
High byte

1
l

owtueGt
ERG

SieNENR
GemINUR

stsnaneY

Instruction
Subinstruction

Low

High

3
3
2

byte
byte

data
data

for

instruction

follows

instruction

pipelining

requirements

ae
iin

sn
mucinNotice
ote

certain

for

provides

tint rasterop

data

the

that

this

2;
source

cycles.

memory

chet
entre

ith
ceten5.4.1
samt
ent

addition

wunees
<eomate

order

External

I[/D

Bus

Devices

the
the

Adder

and

devices
immercan
attached
to
bus.
These
be
devices
must
be
write
I/D
only
Adder
the
transmit
data
because
an
I/D
sovemmn
always
chip will
during
External
commands
are
command.
from
bus
I/D
Suuunty
distinguished
Viper
<7>
in bit
of
commands
the
instruction
The
by a zero
chip
byte.
Musennn
is
undefined
external
subinstruction
instructions
and
I/D
cinema
during
of
to
an
is
not
use
external
device.
See
section
so
4.2.2.1
for
snanaite
discussion
of
external
I/D
instructions.
conve a further
to

for

at
it
must
decode
ceoweus
PHI2A
newurne
during
only
amines the
A/B
PHI1/PHI2

erent during

5.5

Chip

PHI2B

device
instruction

external

least

cycles.
cycles
(see
cycle

Viper

the

external

using

section

SYNC,
5.3.2).

to
respond
which
byte

device
which

the
is

I/D

bus,

present

synchronize
occurs
always

can

Selects

has
a
Each
chip select
chip
Viper
it
bus
instructions
to
I/D
responds
whether
it
and
write
enable
logic,

memory
is
to

rasterops.
during
an
unencoded
provide

that

and,

not

associated
selects
chip

external

chips,

allows
The
usual

controls

whether
PE
the

through
in
its
writing
implementation
from
a
chip select

DRAGON
PHYSICAL

VIDEO
SYSTEM
CONFIGURATION

COMPANY

HARDWARE

CONFIDENTIAL

115

page

this
allows
combination
Viper
chip;
any
register for to everybe enabled.
selects
are
sensed
SERIE
Viper
chips
by
Chip
the
instruction
SRAM chip
(PHI2A).
only during
cycle

SOREN

the

Viper

YEN
AAR

the

Because

UMMMwithout

disturbing

of
SERN

selects.

chip

the
SOLIS

scroll

chip
The

SMEAR
progress.

LORIE
register;
SR cycles,
and
UNION

SREY
register.
SN

all

axis

the

needs

process,

Adder
when

load

the

process

the

access

the

IDCTL

normally

are

separate

pinis

instruction

I/D

chips

Viper

requires

provides
scroll

set

select

provided

be
enabled
scroll
I/D
during
be
scrolled
or
erased
together,
used
to
load
the
scroll
fill
cannot
be
used
for
the
fill
scroll
the
addresses
might
change
plane

are

Viper

chip
selects

loads

process

update

chip
all
they may simply
will
planes
always

but,
if

scroll
the
The
selects
scroll

feiiath
The

SiN

KN local
Siem bus.
data
aaneiN
mixed
AiemenE

select
can
be
connected
to
either
the
register
bus
or
as
an
external
device
to
the
I/D
processor
directly,
The
latter
connection
is
if
a
DMA controller
feeds
required
the
Adder
to
because
are
chip,
chip select
changes
generally
other
with
Adder
commands.
chip

chip

mem

GeREn

EN
REN

5.6

Memory

Address

Bus

SmI
SINR

The

ity

Buffering
WiReINEN
planes.

Site control

address
bus
is
common
to
all
bitmap
planes.
be
to
fanout
the
in
bus
with
may
required
systems
many
There
are
two
of
from
the
Adder
that
groups
pins
chip
the
address
memory:
bus to the bitmap

bitmap

GINA
eum
tinh

htmtit:
femittiin

cumemee

“Ome

supe
MORIN
GeNe

The

-WE
and
SCROLL
are
clocked
ADDCLK
pins
by the
The
MEMAD
one
row
address
and
one
pin.
pins
provide
column
address
for
each
16 bit
and
one
(minor)
cycle,
row
and
column
addresses
for
each
128
bit
eight
(major)
A valid
set
of
write
enables
and
a
scroll
are
cycle.
for
each
column
the
-WE
are
address;
provided
only
write
the
SCROLL
is
meaningful
during
cycles;
only
for
128
bit
read
meaningful

MEMAD,

pins

cycles.

coms

ADDCLK

‘aN

includes

SAmLnOE

5.4)

that

required
first

the
starts

the

cycles);

CRE
inne

interval
address

for

innit
setenih
saree
seveemne

previous
following

pulse
pulses

cererese
mee

cycle.

column
in
a

writes.

rising
a

minor
fetches

There
and

cycle

ADDCLK

the

(for

addresses.

major

cycle)

two

normally

row

major

interval

(see

of
pair
that
pulse

address
the
Adder

address;

that
section
minor
includes

only
chip.

and

nine

the

additional

cycles

ADDCLK

the

same

for

this
column
The

(or

fetch

cycle)
be

must

high
PHI2B

(or

cycle
of.
the
column
from

first

the

brings

nsec

major
edge

seni

have
a
of
the

in
reads

of
a

ADDCLK

minor
as
for

DRAGON
PHYSICAL

ual

SNR
SANE
SARIN
INR

VIDEO
SYSTEM
CONFIGURATION

HARDWARE

series

The

CONFIDENTIAL

116

page

in
addresses
a
major
cycle
If
the
controller
sequential
up
memory
to
its
own
column
addresses
(for
generate
example,
is
used
in
nibble
mode
it
RAMs),
implicit
addressing
may
use
the
first
column
address
and
assume
the
rest
are

form
needs

COMPANY

column

count.

sequential.
ht

nim

The
Adder

MEMADs

chip

“nT

chip

EEN

clocked

GUNERG

cee
ENR

address

SOON

while
There
that

the
is

the

latches.

MEIER
ORI

IRN

IY
SIN

latched

externally
delay

the

propagation
timing.
memory

first

fetched

time
available
enough
setup
banks
of
can
multiple
memory
while
a
buffer
fans
latches,
chip

The

AER

Adder
should

of
latch

the

the
Adder
is
also
of
the

This
tight
so
that
the
last
column
address
by ADDCLK
is
to
the
while
the
row
cycle
going
memory
of
the
next
is
from
the
Adder
cycle
coming
the
row
address
is
to
the
applied
memory

similarly,

contained

ARR

need
deskew

obtain

EN
ARR

column

SCROLL

the

accepted

from
the
it
matches

memory,
the

from
the
chip.
the
so
latch
fed
from
separate
from
the
Adder
to

be
out

indicates
words
that
are
memory
scroll
It
comes
of
out
the
region.
the
address
of
the
associated
word
and
with
the
it
is
MEMADs;
but,
along
if
as
it
were
data
Viper
chip
coming
so
it
must
be
further
so
that
delayed
data
timing.

in
the
with
latched

chip

address

chip;

eis
NOTE

<tr

scroll

Gene

The

sewn

connect

MuuRNAAA

chip.

the
the

from

pin
directly

Adder
scroll

chip
pin

does
NOT
of
the
Viper

section

5.7.1.

ctu
ti

enemy

The

WE pins

semen
seein

128/-16,

Ss
ean

major

“nen

the

nuns

next.
generated
bit
read-modify-write

seman
cine

R/-W
PHI2A

the

cycle
clock

(or
generator

and

read

both

and
that

discussed

are

FORCE
are
provided
PHI2B
the
precedes
of
minor
cycles).
pair
A

of
the
16 bit

write

type

write
is
cycle

the

by
that

Adder

chip
each

starts

These

pins

that
cycle
means
cycle

should

which

next,

that
will

warn

16
contain
a

portions.

mete
NOTE

The
NOT

which

The
is

R/-W

128/-16,
the

Viper
force
down

from
the

pins

directly

connect

the

Adder

128/-16,

chip
R/-W

pins

chip.

pin indicates
scrolling.

major
It

cycles

further

in
a
discussed

frame

DRAGON
PHYSICAL

VIDEO

SYSTEM

section

5.6.1
The

address

COMPANY

CONFIDENTIAL

117

page

5.7.1.

Bit

Address

Memory

sequence
of
the

function
Scan

HARDWARE

CONFIGURATION

address
outputs
width
and
memory

bus

Configuration
bits
are
in such

Assignments

the

address

configuration
Adder
chip.

pins
bits
The

the
¥

and

row
and
column
times
for
the
refresh
is
(for
guaranteed
either
256
refresh
addresses)
requiring
by
the
Y addresses
in
the
low
keeping
8 row
fastest
moving
addresses.
The
Address
bits
are
numbered
to
their
according
in
address
calculations.
The
lowest
significance
4X
2, 3 or
address
bits
shown
in
(not
the
tables
below)
within
access
pixels
a
word
in 4,
8 and
16 bit
bus
width
memory
modes,
respectively.

memory
memories

"Greater

than

Address

Row

Bit

time

y12

Y11
Y10

X10
X11

Y10
Y9

X10
X11

Bit

Bus
Y4

Width

YS
x9

8
Row

time

Column

| Y12
Time|

Y1ll

Column

Time!

Y10

"Greater

than

1024"

mode:

time

Address

Row

Bit

time

|
Time!

Column

|__10
X12
Y12

Yl1
Y10

time

| Yl12
Time]

Column

Yll

Column

| ¥Yll

time

Time!

Y10

Width

v3
YS

x8
Y¥8

Y¥2
Y7

Yl
Y6

YO
X6

x8
X5

x7
x4

Y2
Y7

Yl
Y6

YO
X5

x7
x4

X6
xX3

~=9

Bus

Width
X7
Y4

X8
Y7

X6
X3

x5
x2

Bit

Bus
Y4

Width
Y2
Y7

Yl
Y6

YO
X6

x8
xX5

Yl
Y6

YO
xX5S

X7
x4

x6x3

X8
Y7

Yl
Y6

x6
X3

X10
X11

X10
Y12

Bus

¥2
YS

xX9
Y¥5

Y10
K10
Y¥9 X11

¥9
Y8

Bit
Y4

Bit

Bit
x9
Y¥4

4
Row

Y3
Y8

Y3
X9

8
Row

x9
4

| ¥Yll

¥9
X10
Y¥8 ¥12

Row

memory
128
or
X and

mode:

|_ 10
| X12

out

that

way

512"

Time!

Column

Y¥9
Bus

yY3
YS

¥Y¥3
Y8

Width
xX8
¥2
Y8

Bit

Bus

Width

xX9
Y3

Y¥2
YS

X7
Y4

= x2

DRAGON
PHYSICAL

VIDEO
SYSTEM
CONFIGURATION

HARDWARE

COMPANY

CONFIDENTIAL

118

page

‘

are
suitable
for
standard
Dragon
systems.
in memory
that
are
of
in both
two
spaces
powers
If
width.
the
address
bits
can
St
be
height
necessary,
and
recombined
to
form
a
new
of
row
and
LIAR demultiplexed
arrangement
column
there
is
even
sufficient
time
in most
SuNCtID
addresses;
memory
to
the
column
address
bits
out
of
the
Adder
and
LARUE
get
arrangements
ERRAND
include
some
of
them
in
row
the
address
to
the
going
memory.
hI
Such
can
allow
the
to
be
used
when
remultiplexing
Dragon
system
of
the
other
CORRE
have
determined
the
requirements
processors
already
row/column
combinations.
can
SIRI necessary
also
be
Remultiplexing
used
to
alter
the
of
two
restriction
on
the
of
the
power
shape
I
for
a
1024
x
could
be
altered
to
memory;
example,
1024 memory
See 960 x 1088.

onmee

eREEERE
They

These
result
and

assignments

NNSA
Mh

§.6.2

Refresh

Memory

enti
standard
address
in
section
memory
sequence
given
refresh
is
the
screen
refresh
memory
Ste 5.6.1,
accomplished
by
IRN process
if
are
MEMAD<7:0>
connected
to
the
memories
is
(it
assumed
that
memories
at
least
64K deep
are
used).
The
Gun
following.
table
the
number
of
row
addresses
mR
gives
unique
generated
per
scan
and
the
number
of
scans
to
a
iin horizontal
required
get
of
128
or
256
row
for
each
eweihiy
addresses,
complete
sequence
combination
the
bit
and
the
bus
sueniuim
memory
configuration
width.
of

SRL

For

the

commen
supe
"Greater

Sane

than

512"

mode:

caine
eens

Width

Bus

Bit

nies
Addresses
for
Scans
Scans
for

shining
‘niin

emerinan
seceaeme
enremy
cemnien
smvnse

1024"

Scans

rows

scan

times,

0.6
msec;
However,

completed
normally

required.

vertical
the
screen

may

not

scans).

displayed
is

the

and

retrace

last

complete

Therefore,
refresh

Bit

|
|
|

rows

typical
0.5

32
64

Bit

scan

per
128
256

for
for

Scans

8
16
32

16
8:
16

mode:

Addresses
’

refresh

rows

Width

Bus

For

rows

than

"Greater

|
|
|

scan

per
128
256

period

8
16.
32

128

complete
this

is
refresh

sequence

(according
the

worst

computed

far

less

is
of

Bit
16
8
16

address
than

sequence
2
the

accomplished

32
4

is
msec

during

refresh
addresses
to
the
number
of
case
time
to
complete
from
the
above
table,

plus

DRAGON

VIDEO

SYSTEM
CONFIGURATION

PHYSICAL
the
vertical
<inwe,
SONNE
incomplete
Gin displayed

HARDWARE

and
time,
that
cycle

retrace

refresh

COMPANY

the

plus

duration
the
bottom

occurs

CONFIDENTIAL

screen.

119

page

any
of

the

amAASIND
Sino
Only

the
128
bit
read
refresh.
Therefore,
memory
it
is
GARNER
used,
only necessary
read
the
MRA bit,
cycles;
only
other
GORINELID cycles.
Restricting
in
SHLD considerable
power
large

cycles

the

perform
than

required

and

screen

bank
of
is
memory
to
RAS
all
banks
of
memories
for
128
selected
bank
need
be
RASed
for
all
the
RAS
on
memories
can
save
cycles
more

one

systems.

memory

SLD
SE

LID
SILA 5.6.3

Selection

Memory

And

Configuration

Seuhitaty
the

Although

“AON

and
64Kx4
static
“ALOHA
SENOEN
cycle),
Dragon
Sm Unfortunately,
The
commer
planned.
semeapproximately
minor
te
cycles

Dragon

column
can
be

static
data

system
with

used
column

stress

become

not

64Kxl
mode

available

major
cycles
requires
cycles.
Speed
requirements
RAMs.
ordinary

mode

page

to
work
with
designed
a
fast
having
very
page
of
other
variety
RAMs.

have

RAMs

during

rate

90 nsec
do
not

was

(RAMs

RAMs

even

for

SNL

direct

tpl

RAMS.

AANA

This

alternative
allow
fast

These

two
requires
be
possible.

seniitshould

static

enn nibble

mode
RAMS
are
256Kx1,
be
used
of
per
plane;
of
off
screen
Sahinamounts
memory
of
nibble
mode
sittinconfigurations

column
RAMs
are
four
column
bits

cycling
RAS
for
cycles
Unfortunately,

each

which

meING

memory

major
the

cycle,
readily

most

dictates
this

course,

that

required,

are

mode

time.

but

this
available

four

ideal

screens

anyway.
be
available.

should

RAMs

nibble

large

Other

Siren

If
“itt
acceptable,
ANAS
AN

two

and

even

screens

ordinary

inn

alternate
RANGper
plane

odd
banks
banks.
if
16Kx4

memory

speed
with
The

per
64Kxl

plane

successive
same

major

arrangement

RAMs

required

are

64Kx4

RAMS

cycle
be

can

words
used

arranged
accessing

for

one

screen

used.

are

Amine
Video

cee

row

NNR

refresh
scrolled
KRY

(having

RAMs

data)
reads
and

are

built

useful

not

are

still

perform

for

shift

Dragon

required

memory

refresh.

pick

used

that
but

for

output

because

normal
that
is

screen

being

When

site

screen

eam

additional

are

and

memory

requirements

cycle

Seas cycle

configuration
for

the

visible

screen

meets

the

still

memory
required,
ordinary
memory
In
this
case
the
RAS
memory.
only
part
read
is
to
the
additional
RAM
(for
applied
memory
the
fast
CAS
will
never
be
cycles
applied.
can

used
of

major
off
for
a

the

major
refresh)

5.7

Memory

CONFIDENTIAL

COMPANY

HARDWARE
SYSTEM
CONFIGURATION

VIDEO

DRAGON
PHYSICAL

120

page

Bus

Data

connected
the
are
to
each
plane
to
the.
latch
with
appropriate
usually
Viper
latch
is
held
The
generally
required.
timing
memory
particular
minor
from
the
to
or
(16
data
to
memory
during
directly
open
pass
is
The
latch
controlled
direction
R/-W.
with
the
bit)
by
cycles,
hold
of
the
time
extend
to
used
bit)
(128
cycles
during
major
a
latch
of
the
to
the
data
Viper;
transparent
requirements
memory
4 bit
When
or
LTCLK.
8
clocked
which
can
be
is
used,
by
normally
of
reduced
number
a
is
mode
bus
width
used,
proportionately
bits
of
the
low
order
to
the
attached
memories
are
Viper
only
data
bus
that
the
on
the
load
maximum
data
The
bus.
capacitive
full
at
clock
for
40
drive
is
can
rate;
operation
pf,
Viper
chip
tha
of
the
number
on
limitation
this
is
the
memory
chips
primary
connected.
can
be directly

The

128/-16
of
time

type
and
the

R/-W

minor

is
Viper
normally

memory

cycle

pins.

These

pins

(see

section

minor

cycle

16
the
data

PHI2B

cycle.
the
from
(signaled
indicates
initially
to
changes
cycle,

for

lines

data

The
memory
data
lines,

clock
the
Adder

chip

read
write

and,

the
are

5.4)

latch

controlled

changed

that

each

starts

the
the

major

read-modify-write
the
bit
R/-W
write),
in
time
appropriate
a

and

the

bus.

the

reverse

NOTE

The

Viper

Adder

the

controlled

The
128

clocking

falling

edge

do
of

chip
pins

R/-W

128/-16,

bus

data

memory

the

from

pins

directly
chip.

connect

The

R/-W

128/-16,

differently

for

controlled
latched

NOT

the

and

major

minor cycles.
1.

Major

cycles
During

LTCLK.

Viper

writes,
edge of

the
data

The
each

with
reads.

128

LTCLK

must

reads,
of
from

by
in

the

bit
128
LTCLK.
During
on
the
the
rising
Viper
LTCLK
is
of
normally
writes.

and

reads

data
data

continue

run;

During
the

read

bit

timing

used.
to
the
is applied
Viper
signal
128
word
during
memory
corresponding
described
is
further
The
scroll
signal

scroll

5.6.

Minor

cycles
chip
Viper

of
middle
latched
is

falling;

timing

The

for

section

the

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DRAGON
PHYSICAL

VIDEO

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COMPANY

HARDWARE

CONFIDENTIAL

121

page

CONFIGURATION
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its

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enable

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DRAGON
PHYSICAL

VIDEO
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CONFIDENTIAL

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DRAGON
PHYSICAL

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VIDEO
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CONFIGURATION

contains

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COMPANY

CONFIDENTIAL

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DRAGON
DRAGON

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COMPANY

CONFIDENTIAL

127

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registers.
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events

status

just

value

boundary

only

the

explicitly,
pause

the

may

cleared.

stay

neue
sete

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seruaeen

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vent
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like

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bit
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scroll

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bit.

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edge
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is
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blank.

just

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have

DRAGON
DRAGON

VIDEO

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SYSTEM
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COMPANY

when

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128

page

disabled

source

ignored

are

CONFIDENTIAL

The

the

source

rasterop.

mum
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first
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fast

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vector.

LAER
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Error

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GREET

the

RENNER

Registers

indexes

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changing

SARIN
Sinn

loaded

during
[2F]

and

Pass

Two

new

error

the

Bresenham
Used

added

initialization.
term.

error

prevent

problems

when

registers

can

scrolling.

rasterop

initial

while

Initialization
with
numbers

Term

terms

improved

regions

update

Normally

error

adjust

programmed

zero.

[30].

SRN
SiO

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NR A.2.2

Chip

Viper

Min

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There
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no
foreground/background
unit
directly
logic
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PTBZ
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register

source

the

registers;

are

the

mask

mux.

output
The

operations.

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second

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with

pass

all

zeros.

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for

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is
any

part

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foreground
to
register

only
CSR.

source

but
to

the
allow
one

delay

all

first

ones

operation.

correct

Because

pass
part:
program
and
the
background
To
a
use
second
a
as
pass
part
set
bits
PTBZs:
<2:3>
to
"00";
will
be
addressed
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PTBZ
register
from
this
not
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register
may
path
to

source

available

operations

require

use
a

DRAGON
DRAGON

smi

VIDEO
CHIP

delay

Seen

with
first
in
enabled
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pass

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and

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a
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should
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set

resolution

CSRs

second

logic
bits

part:

pass

be
2

can

in
the

mode

first

possible

not

are

129

page

disabled
with

and

compatibility

part

pass

CONFIDENTIAL

operations
the
delay

and
complementer
source
register.

following
To

“COMPANY

SYSTEM
HARDWARE
BUGS
AND
CHANGES

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itt

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first

the

address,

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should

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pass

bits

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second

Bit

pass.

fill

second

pass

part

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the

Adder

during

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scrolling.

bits
three
for
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set

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all

planes

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part:

bit

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scroll
for
down

direction

the
down

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for

and

scrolling.
as

part

pass

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input
scroll. pin

forced

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down

chip,

permanently.

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centemn

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enue

boundaries

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scrolling:

there
must

vertical
modified

bit,

scrolling.

win
net

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Mente

LEFT
All
bits
of
the
of
the
values
specified
when
NOT down
scrolling.

boundary
for

set

are

the

RIGHT

the

complement
boundary

scroll

ctint
tiny,

Cinete
seve

All
bits
of
the
RIGHT
values
of
the
specified
when
NOT down
scrolling.

boundary
for

set

are

the

LEFT

scroll

the

complement
boundary

SmI

iment
mined
i

scp

use

scroll
boundaries

second

direction

pass
bit

described

part

for

up
above

first

pass
and

scrolling
for

first

part:

set

program
pass.

the

the
-

DRAGON
DRAGON

VIDEO
CHIP

SYSTEM
HARDWARE
AND
BUGS
CHANGES

This

page

CONFIDENTIAL

COMPANY

intentionally

left

blank.

page

130

INDEX

-~A-

Adder
See

also
and

(Cont.)

clipping

status,

data
126

125,

85
to
92
30
to
44
40,
54 to
64
105
to
109
pins,
65 to
84
registers,
Address
bus
See
Hardware
ADDRESS
66
COUNTER,
Address
counter
DMA controller
See
Address
disable
107
pin,
Address
FIFO

38,

45,

scroll
video

80,

format,
17,
boundaries,
123
14,
bus,

screen

98
95

restrictions

fonts,

region

boundaries,
77
39,

tiles,

122

WIDTH
BUS
(Viper),
Buses
See
Hardware

Rasterop.

BACKGROUND

Cancel

data

path

See

Rasterop,

Bitmap,
planes

data

path

See
See

Brush,

See
CLIP
CLIP
CLIP
CLIP

transfers

PST

Bresenham's
See

Clear,

Memory

Bitmap/processor

algorithm

See

69,

PBT

Buffered

registers,
Scrolling

72,

75
75
75
75

MAX,
MIN,
¥ MAX,
Y MIN,
X

8,
also

57,

Status

18,
23,
region,
75
registers,
with
scrolling,

BTP

See
BTPZ
See

63,

region
Scrolling

Clipping,

arithmetic

Rasterop,

bit,

Status

shifter

Barrel

45,

Characters
See
Text
select
Chip
See
Hardware

Rasterop,

command,
89,

PBTs,

Background
See

97
42,
96,
101
29,
87,

of,
of,

loading
with

~C-

COLOR,

effect

See

16,

~B-

Bus

63,

performance,

commands,
functions,
46,

120

bus,
45,

PBTs,

128

See

width
effect

10,
29,
Rasterop
changes,

chip,

bugs

Bus

64
bits
122

121,
23

Clocks
PBT

width
effect
address

See

double

Color
See

Column

of,

output,

See

117,

118,

Hardware
map
Hardware
address

Memory
30,
60
of,

COMMAND,

121

use

index-1

71,

72,

Command

descriptions

Command

descriptions

Dragon

See

Dragon
mode
Complement
See
Rasterop
Control
See

store

definition,
ram

data

Drawing

modes

See

Rasterop,

path

Coordinates
65
65
65
99
to

memory,

world,
CSR,
43,
also

See

Curves
See

data

path

-~B-

mask

Edge
101

See
See

data

Rasterop,

path
selecting,

6
78

DRAGONLIB.C,

Rasterop,

device,

(Cont.)

system

Viper

chip,
cycle

active
90

88,

path
commands,

region
Scrolling

Erase,
See
ERROR
ERROR

Graphics

data

Rasterop,

1,
2,

78
78

36,
36,

-~D—
-P-

bus
Hardware

Data
See

a FAST

Definitions,
Delay
registers
See
Rasterop,

data

DESTINATION

ORIGIN,

31,

ORIGIN,

DMA

Fast

mode
Rasterop

58,

See
FAST
FAST

controller

FILL,
7

10,

18,

86,

89,

Double

registers

Scrolling

See

See
Graphics
FOREGROUND
COLOR,

with

Dragon
chips

Rasterop
.

of,
of,
PBTs,

Foreground

42,
96,
29,
87,

Rasterop,
8,

rate,

registers
to

and
104

data
13

-G~-

commands,
52

Graphics,
See

system
index-2

also

97
101

Viper

definition,
65

See
Frame

Adder

also
also

101

88,

Scrolling

loading
Scrolling

See
See

of,

mode

effect

Dragging

87,

See

related,
buffered

See

Flood

Documents,

38,

color

Fill

115

of,
37,
62
60,

56,
76

Rasterop

See

25
24,
44,
45,

38,
DX,

29,

Fill

65,

29,

of,

loading
8,

restriction,
use
of,

vector

See

37,

SOURCE

effect
Fast

SCALE,

use

Screen

example,
interface,

38,

58,

Display
See

31,

DESTINATION
DY, 31,
38,

coordinates
Coordinates

See

DX,

FAST

60,
Device

path
31,

60,

DESTINATION

Rasterop

path

Local

(Cont.)
54
30,
62 to
45,

Graphics
curves,

flood,

63
52

objects,
points,
polygons,
shaded,

bus

I/D

57
57

Hardware

also
also
also
also

See
See
See
See

57
to
52 to
54 to

vectors,

~T-

processor

Scrolling
bits

Status
Z axis

command,

73,

72,

85,

88
data

105
to
Adder

also
also

See
See

68
status,
address
with
counter,
66
data
90,
source,
40,
100
external
85,
device,
114
101
to
102,

124

chip
chip

Viper

10
buses,
address,

115

data,
I/D,

26,

107,

120
to
12,
14,
12,
16,
26,
93,

121
113

14,

29,

color

87,

88,

9 to
13 to

timing,
clocks,

111

cycle,

14,

synchronization,

73,

22,

ENABLE,
-L-~

Laser
LEFT

Linear

83,

See

84,

120

115,
10,

79,

printer,
SCROLL

112

video
bus,
14,
83,
enable
write
logic,
123
Horizontal
signals

95
121

107
31,
39,
98
BOUNDARY,
88,

pattern
Rasterop
101
17

processor,

bitmap

access,

See

also

See

Hardware

PBT

bus

113

See

18,

Local

bus

115
16

112,

120

85,

bus

INTERRUPT

bus,
82,
14,

cycle,

73,

66,

DATA,

I/D

pin,

114

16,

major

82,

processor

87,

14,
to

71,

Scrolling

See
See

cycle,

local

minor

commands
102

101

Interrupt,

computation

93,

Indexing

90,

bus,

115,

SCROLL

87,

123

93,

16,

address

bus,
bus,

102,

Instruction/Data

26,

87,

definition,
system,

I/D

85
115

I/D

101

map,

data

124

I/D

select
chip
22,
73,
12,
logic,
114
to
93,
86,

of,
91,

chip,
87,

70
to
DATA,
66,
101
92,
SCROLL
COMMAND,

I/D.

86,
89,
123
12,
26,

video,

use

See
Viper
NOP
cycle,

14,
10,
124
93,

processor,

44,

99,

instructions

119

114

local

18,

10,

89,

86,

44,

71,

73,

FIFO,
~H-

Hardware,

registers,
72

definition,
index

interface,
66

Screen

use

index-3

management,

of,

29,

44,

18,

65,

Logic

function

unit

Logic

function

See
LOGIC

unit
data

Rasterop,
UNIT
FUNCTION,

~O-

path
43,

Objects

See

selecting,

88,

90,

Off

Graphics
screen

definition,

17,

shared

use

-M=~

Major

complement
fonts,
27,

cycle
96

of,

42,

of,

of,
loading
Mask
register

42,

control
See

Rasterop,

Memory,

also
also
also

See
See
See

100

definition,

data

See

down

12,

17,

26 to
123

29,

80,

46,

Rasterop

119

command,
72,
63
flood,

63,

with

scrolling,

118

MODE,

119
117

of,

use

54,

44,

See
Pen

45,

Screen

INDEX,
INDEX,

24,
24,

74,
74,

44,
45,

45,

91,

91
99
102

96,
42,

103

Rasterop
X
Y

24,
24,

INDEX,
INDEX,

88
88

non-square,
PLANE

index-4

74,
74,

88
88

9, 16
45
9, 16,
49
9, 16,
48,
47
storage,
19,
scrolling,

font
while
46
with
resolution
Pixels
See
also
Graphics
low
resolution
See
Resolution

-N-

NEW
NEW

up/down

text,

Monitor
See

PBT

See
PENDING
PENDING

57,

PBTZ

Performance,
rasterop,
to

instructions,
to

cycle
Hardware
71
51,

44,
44,

80,

Coordinates

See

mode,
mode,
I/D

row/column

Minor

45,

86,

addresses,
115
to
117
116,
115
14,
82,
timing,
word
boundaries,
39,
98
90,
47,
coordinates
Memory

PAUSE,
24,
67,
73,
44
to
PBT,
27,
29,

119

118,

maximum,
8, 10,
119
RAM, 9,
13,
80,
14,
refresh,
80,
117,

See

Parallelogram

88
88

74,
74,

-p-

screen

Scrolling,

17,

path

screen

configuration,
121

63,

57,

38,

30
zoom,
OLD X INDEX,
24,
OLD Y INDEX,
24,
On screen,
65
63,

Off

planes,

117,

mode,
35,
47
46,

two,

source

45,

PBTs,

Hardware
1, 97
control
of,

See
MASK

MASK

use,

ADDRESS,

mode,

mode

30,

31,

35
96

Rasterop
Plane

address
Z axis

See
Planes
See

Rasterop
(Cont.)
path
delay
registers

data

See

Memory

Points
See

CSRs

unit,
logic
selecting,

Graphics

Polygon
See

Local

processor

transfers

Processor/bitmap
See
See
PTB
See

of,

use

PBT

spacing

Text

RAM

Rasterop,

Memory
17,

64
address
FIFO,
arithmetic
Bresenham's

44,

31,

46,

107
31

algorithm,

effect

error

computation,

major
minor

axis,
axis,

range,

36,

use

31
3l

slow

shift

constants,

command,

30,
of,

fast
fill

88
to
72,
89
86,

27,

mode,

and

30,

also
mode

fill

Rasterop,

crossing

93,

103

100,
42,

40,

90,

3937, 98

96,

origin,
polygon
or

62,

vectors,

58,

57,

36
60

subdivision,
¥
fill
axis,
71
58,
62,

38,

57,

indexing

loading
of,
35,

CSRs,

71
62,
mode,

registers,

error

use

60
54,
56,
54
38,
40,
45,
57
to
71
9,
62,
58
to
sides,
60,

38,
path,
shifter,
barrel
colors,

baseline,
complement

33,

35,

of,
complement
use

mode,
mode,
A

36,

38
of,
52
of,
30,
49,
78
vector,
77,

definition,
use
of,

31,

scaling,

data

33,

See

loading,

~R-

See

93,

definition,
9, 29
31 to
destination,
30,
72
42,
88
enable,
fast
vector,
38,
76,
31
definition,
use
56
of,
54,
holes
and
duplications,
34
to
71
35,
54,
76
58,
origin,
77
76
to
registers,
44
rotation,

PBT

See

42,

96,
PBT

mode

source

PTBZ

88,

logic
Resolution

See

44,

97
42,
96
93,
63
51,

27,

resolution

Proportional

use
51.
mask
register,
control
of,

Processor
See

90,
of,

Graphics

42,

of,

29,

See

40,

mode,
43,

29,
30,
up/down,
54
use
of,
performance

pen

101

selecting,

88,

Scrolling

index-5

71
to
72
57,
71
51,
57,

Rasterop
Resolution

Rasterop
(Cont.)

performance

Performance

See

values,

source

30,

one,

78
36
to

36,

vector,

38,

linear

54,

56
of,
pattern,

use

ROM
See

of,
57
40,
51,
54,
56,
57,
58,
62,

Rotation

57,

effect

of,

use

origin,

37,
of,

36,

54,

40,

9,
of,

of,

40,

See

23,

8,
boundaries,
definition,

Region,

SCROLL

bits
46
to

18,

SCROLL
SCROLL
SCROLL
SCROLL

25
19

documents,

signals,
81

(Viper),

CONSTANT
121
XK MAX,

MIN,
Y MAX,
Y MIN,

73,
73,
73,
73,

87
87
87
87

19,

14,
123

83,

88,

24,
22,
98
73,
74,
95,
95
74,
l2l
enable,
85,
95,
plane
21
95
to
down,
74,
22,
73,
effect
of,
33,
38,
45,
46,

buffered

registers,

121
reserved
81

Interrupt
to
67
66
94
to
93
MODE,

fill

index-6

19,
98

21,

23
74

23,

region,

color,
97

14,

memory,
22

dragging,
erasing

REQUEST ENABLE,
RESOLUTION

81,

25,
command,

Request
See

80
14,
21,
22,
46,

79,

buffered

See

17,

Scrolling,

erase

Scrolling
descriptions
Register
See
Dragon
double
Registers,
See
Scrolling

13,

synchronization
95,

Status

of,

screen

63,

57,

screen

107

54,
38,

Off

refresh,
78

bits

status

also
also

registers,
requirements,

72,

Rasterop

format,
38

use

Region

See
Screen
See
See

54,

52,

registers,

use

44,

60
of,
30,
two,

tiles,

memory

Scaling

49,

30,

of,

40,
enable,

35,

vector,

use

38,

of,
56,

use

94,

~S~

registers,

source

Scrolling

Text

See

89
effect

use

Performance

registers,
scaling,

slow

See
Rasterop
Row
address

use

26,

93 to
40,
42,
42,
101
96,
97,
98
29,
94,
subplane,
26
definition,
with
95
94,
scrolling,
RIGHT
SCROLL
88,
BOUNDARY,

72,

fast

logic,

40,
enable,

also
also

See
See

29,

mode,

23,

29,

93,

Variable

Scrolling
I/D

(Cont.)
commands,
22,
69,
115
73,
85,
93,
24

indexing,
effect

45,
enable,

38,

39,

23,

69,

33,

initialization

30,

38,

18,
boundaries,
to.

SLOW
SLOW

scroll
27

resolution
87

23 to
to
88

25,

31,

60,

DESTINATION
77

DY,

SCALE,

37,

SOURCE

of,

Slow

of,
60,

mode,

22,

DX,

effect

SOURCE,

control
effect

of,
of,
of,

56,

Sync,

31,

with

58,
SOURCE

33,
SOURCE
SOURCE
Source
See

Hardware,
sync

See

Hardware,

57,

Test

attributes,
46
fonts,

47
normal,
performance

56,

rotated

57,

ORIGIN,

62,

36,

56,

variable

57,

pitch,

Tiles

AND
HEIGHT
WIDTH,
77
to
78
77
2 X ORIGIN,
38,
77
2 Y ORIGIN,
38,

38,

See

Rasterop
-U-

data

Rasterop,

path

Update

process

See

Rasterop

Splines
See

Graphics
67

§1

62,

STATUS,

72,

Performance
and
scaled,

See

36,

70,

51
52
to
9, 44,
49
47,
RAM
and
46
addition,
resolution
27
mode,

with

100,

65,
52

ROM

ORIGIN,

timing

87,

timing

functions,
85
82,

42,
29,

mode

-T=

DY, 76
54
37,
62

PBTs,
1

See

System
60,

101
SOURCE

25,
88

PHASE,
system

Text,

Rasterop

22,
86,

blank,
Resolution

See
SYNC

vector

See

68,

Subplanes

update,
39,
75,

use

60,

vertical

DESTINATION
77

SLOW
SLOW

86,
67,
complete,

service,
66, 72,

of,
89,

use

21,

89
73

PBTs
PBT

See

with
with

rasterop

98
8

19,

speed,
with

complete,
68,
24,

pause,

122
121,
97
75,
95,

98,
72

registers,
smooth,

22,

70
68

ready,
87
69,
ready,
68
to
ready,

87,

region,

68,
69

19,

receive
scroll
transmit

I/D
74

92
70,
70,

71,
I/D
I/D

18,

complete,

clipping,

31,
of,
37,
77
75,
46,

of,

bits,

address

registers,
use

Status

pitch

-V-

Variable
See

index-?7

pitch
Text

Vectors

-~X-

Vectors
See

Graphics
signals
also
Scrolling,
registers

Vertical
See

also

See
See

Video
See

Screen

XOR mode
See
Rasterop

18
6

10,

chip,

26,

29,

Rasterop
changes,

126,
commands,

128
to
101
to

129
104

cycle,

86,

active

125

effect

loading
88,
101,

access,

46,

103
102

of,

use

65,

17,
73

33,
of,
38,
87
of,
21,
81
21,
65,

SCAN
78
to
COUNT,
SCROLL
CONSTANT,

74,

103
40

functions,
See

LIMIT,
of,
Y OFFSET,
use

104

65,
Y

also
and

-Y-

bugs

65
of,
17,
SCAN
CONFIGURATION,
117
81,
81,
82,
81
to
SCAN
COUNT,

bus
Hardware

definition,

See

LIMIT,
use

bits

Status

Viewport,
Viper

also

path
109
Pins,
registers,
loading,
88,

-Z~

data

Rasterop,

lll

101

87,

27
to
axis,
9, 26,
29,
definition,
5, 27
86
I/D
29,
command,
PBT

97,

PBT

See

address,
plane
register,
restrictions,

94,

101

91,

29,
95

29,

load,

42,

51,

97,

87,

101
-W-

of,

use

98,

block,
87,
91,
29
definition,
Z axis
I/D
command,
Z

Window

definition,
World
See

Write
See

Writing
See

coordinates
Coordinates
enable
Hardware
modes

Rasterop,

data

path

axis

block

plane
restrictions,

See

zoom,

96,

101

115

address
115

axis

eee:
stent

DRAGON

VIDEO

SYSTEM

HARDWARE

COMPANY

NOTES

CONFIDENTIAL

DRAGON

VIDEO

SYSTEM

HARDWARE

COMPANY

NOTES

CONFIDENTIAL