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TK-DESQA-TM-001

August 1988

259 pages

Original

12MB

Document:	DESQA TECHNICAL MANUAL
Order Number:	TK-DESQA-TM
Revision:	001
Pages:	259
Original Filename:	http://bitsavers.org/pdf/dec/qbus/TK-DESQA-TM-001_DESQA_Tenchnical_Manual_198808.pdf

OCR Text

DESQA TECHNICAL MANUAL
Order Number: EK-DESQA-TM-001

Prepared by Educational Services
of

Digital Equipment Corporation

August 1988

The infonnatior. in this document is subject to change without notice and should not be construed as a
commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility
for any error~ that may apµcar ir this dQcument.
The software described in this document is furnished under a license and may be used or copied only in
accordance with the terms of such licen!>e.
No responsibility is assumed for the use or reliability of software on equipment that is not supplied by Digital
Equipment Corporation or its affiliated companies.
Copyright © 1988 by Digital Equipment Corporation
All Rights Reserved.

The postpaid READER ·s COMMENTS fonn on the last page of this document requests the user's critical

evaluation to assist in preparing future documen!ati0n.
The following are trademarks of Digital Equipment Corporation:
DEC
DIBOL
UNIBUS
DEC/CMS
EduSystem
VAX
DEC/I'v1MS
IAS
VAXcluster
DECnet
MAS SR US
VMS
DECsystem- J0
PD?
VT
DECSYSTEM-20
PDT
RSTS
DECUS
RSX
DECwriter
This document \\>as prepared using \'AX DOCUMEKT, Version 1.0

CONTENTS
Preface . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
CHAPTER 1 Introduction
1.1

SCOPE· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5

ETHER~ET OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1- -I
Safety Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
Thickwire Ethernet-General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4
Thinwire Ethernet-General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-7
Ethernet Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I-JO

1.3
FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.3. I
i\ormal Mode and DEQNA-Lock Mode . . . . . . . . . . . . . . . . . . . . . . .
1--11
1.3.2
Module Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.3 ..3
l\fodule Op:rdtinns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.3.4
Protocol Function, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.3.4.1
Physical Channel Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.3.4.2
Data Link Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . 1-14
1.3.5
Q-Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
TECHNICAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .
1.4
1.4.l
Module Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4. l.1
Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1.2
On-board Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1.3
DC-to-DC Convener . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2
ivlodule Pwcess;ng Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.3
Network. Integrity Functions . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . .
1.4.3.1
Self-test Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.3.2
Sanity Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.3.3
Controller Locphack Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.3.4
Remote Console Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
l.4.3.5
Ethernet Channel Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-15
1-15
1-19
1-19
1-19
1-'.!0
l-20
1-21
1-21

1.5

1-22

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

111

1--21

1-21
1-21

CONTENTS

CHAPTER 2 Functional Description
2.1

SCOPE

............................................... .

2-1

MODULE OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Q-Bus Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-block-mode DMA
Data and Status Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backport Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Ethernet Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3. l
2.2.4
Ethernet Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4.1
Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4.2
\faster Moduk Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5

2-1
2-1
2-2

2.2

2.2.1
2.2.1.1
2.2.l.2
2.2.1.3
2.2.1.4

.., <
.....

2-2
2-2
2-2

2-2
2-7
2-7
2-7
2-7
2-7
2-7

2.3.2

SYSTEM PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Module Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-8
2-8

2.4

CONFIGURING THE DESQA MOPULE

2-8

2.3.1

2-7

CHAPTER 3 Programming
SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit-Ho~t to Ethernet Data Transmission . . . . . . . . . . . . . . . . . . . . . . . .
Receive-Data Reception from Ethernet to Host . . . . . . . . . . . . . . . . . ; . . . . .

3-1

REGISTER DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Status Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : ... .
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2.1
Control and Status Register (CSR) Definitions . . . . . . . . . . . . . . . . . . . . . . .
3.3.3
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3.1
Vector Address Regi~ter (VAR) Definitions . . . . . . . . . . . . . . . . . . . . . . . . .
3 ..•.·1
BDl Start Addres~ Registers (BDL SARsJ . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.5
Stath:>11 Address Registers (SA ROM) . . . . . . . . . . . . . . . . . . . . . . . . . ... .

3-4
3-4
3-4
3-4
3-13

3.2
3.2.1

3.2.2
3.3

3.3.I
3.3.2

3-2
3-2

3-13
3-i7
3-17

3.4

HOST \1E\1ORY DATA STRUCTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
f'cc.-,\e and Transmit Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i-lh
[kffc;- Descriptor Lists (RDL~) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -~-19
3.4.2
Buffer Descriptor Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.4.3
3.4.3.1
Reserved Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.4.3.2
Address Descriptor Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
"",.-1. .."', ...,
Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-""'
Buffer Length (Word Count) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - .,..,
-' .j .: ...\
3.-U.5
StdtU~ Woru~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.5
3.5.1
3.5.2
3.5.3
3.5.4

3.5.5
3.5.6

DATA TRANSFER PROCEDURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Pad.et . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Emirs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-27
3-27
3-27
3-28
3-29
3-29
3-30

CONTENTS

CONFIGURATION AND CONTROL PROCEDURES . . . . . . . . . . . . . . . . . . . . .
3.6
Boot/Diagnostic Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.l
Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2
Setup Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . .
3.6.2.l
3.6.2.2
Setup Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setup Packet Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2.3
Setup Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2.4
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3
Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.4
Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.5
Sanity Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.6

3-3 I
3-31
3-32
3-32
3-32
3-33
3-34
3-37
3-38
3-38
3-39

MAINTENANCE OPERATIONS PROTOCOL (MOP): MODULE SUPPORT . . . . . . .
Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOP Element Blocks (MEBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOP Element Type 0: MOP Termination . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOP EJernenl Type t. R~ad Et!len?et .~ddress . . . . . . . . . . . . . . . . . .
MOP Element Type 2: Reset System ID . . . . . . . . . . . . . . . . . . . . .
MOP Element Type 3: Read Last MOP Boot . . . . . . . . . . . . . . . . . . . . . . . . .
MOP Element Types 4, 5: Read, Write Boot Password . . . . . . . . . . . . . . . . ; . .
MOP Element Type 6, 7: Read/Write System ID. . . . . . . . . . . . . . . . . . . . . . .
MOP Element Types 8, 9: Read, Read/Clear Counters . . . . . . . . . . . . . . . . . . .

3-39
3-40
3-40
3-41
3-1 i
,--4-l

3.7
3.7.l
3.7.2

3.7.3
3.7.4
3. 7 .5
3.7.6
3.7.7
3.7.8

3.7.9

3---44

3-44
3-44
3-48

CHAPTER 4 Technical Description
"""-

4.1

SCOPE

............................... .

4.2
4.2.1
4.2.2

ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4--1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selection Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. . . . . .

4-1
4-1
4-3

CHECKING LED TEST PATTERNS . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . .
4.3
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1
POWER LOADING . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .
4.3.2
Fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2.1

4-3
4-5
4-7
4-7

Q-BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8
4.4
4.4.1
O\·erview . . . . . . . . . . . . . . . . . . . . . .
4.4.?
:11i1iali ,::i.tior ..
4-13
DMA Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.4.3
Data DMA . . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
..:-1_--.
-1.4.3.l
4.--..J.::
Cont10l Dl'\L.;. . . . . . . . . . . . . . . . . . . . . . .

4.5
ETHERNET INTERFACE ................... .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1
initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2
DestinatiL>n Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2.1
LA1':CE Memory Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2 ..::
Tram.mission . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .
4.5.3
Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.4
Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.5
Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.6
Thinwire Ethernet Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.7
DP8392 ReceiYe Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.7.1
4.5.7.2
DP8392 Transmit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8392 Collision Detect Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.7.3
DP8392 Jabber Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.7.4
V

+-1-+
4-14
4-15
4-16
4-16
4-17
4-17
4-1 R
4-18
4-20
4--20
4-20
4-21

CONTENTS

4.5.7.5

Thinwire DC-to-DC Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21

4.6
4.6.l
4.6.2

BACKPORT BUS & QNA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Backport Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23

4.7
4.7.1
4.7.2
4.7.3
4.7.4

MODULE CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sanity Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-24
4-25
4-25
4-27
4-27

CHAPTER 5 Maintenance
5.1

SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1

MAINTENANCE PHILOSOPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.'2
Preventive Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1
Correctiw Maint1.:nance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2
DESQA Thinwire Troubleshooting (Thinwire Mode) . . . . . . . . . . . . . . . . . . . .
5.2.2.l
DESQA Thickwire Troubleshooting (Thickwire mode) . . . . . . . . . . . . . . . . . . .
5.2.2.2
Field Replaceable Units (FRUs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3
Diagnostic Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.4

5-4
5-4
5-4
5-6
5-8
5-9

SELF-TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Extended Primary BcC'tstrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.l
Citizenship Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2
Citizenship Te,;t Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2. l
Citizenship Test Re~ults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2.2

5-9
5-10
5-11
5-11
5-14

5.4
5.4.1
5.4.2

5.5
5.5.l
5.5.2

5--4

IEEE 802.3 NETWORK SUPPORT: NULL LINK-LAYER SERVICE ACCESS
POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
TEST Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
XID (Transmit ID) Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
NETWORK DIAGNOSTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
DECnet Network Control Program (NCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Network Interconnect Exerciser (NIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
MODL'LE DIAGNOSTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MicroVAX Diagnostic Monitor (MDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PDP-11 Field Functional Diagnoqic (ZQNA??). . . . . . . . . . . . . . . . . . . . . . . .
PDP DEC/.\'.11 Exerciser...................................

:'i- J8
5-18
5-18
5-19

OPERATING EJ\VIRO.\JMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
PDP-11 Diagnostic Runtime Services (DRS) . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1
DRS Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •.
5.7.1.1
DRS Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.l.2
DRS Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.l.3
!\1icroVAX Diagnostic Monitor (MDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.2

5-19
5-19
5- 20
5-20

5.6
5.6.1
5.6.2
~.6.3

5.8

i-2 l

5-22

NETWORK INTERCONNECT EXERCISER (NIE) . . . . . . . . . . . . . . . . . . . . . . 5-23

OPERATING MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
Unattended Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.l
Build Node Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.1.1
Direct Loop Message Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.l.2
Pattern Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.1.3
Muliiple Message Activity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.1.4

5-23
5-23
5-24
5-24
5-24
5-24

CONTENTS

5.9.2

Operator Directed Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

5.10

SYSTEM REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

COMMAND DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11
5.11.l
DRS Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11.1.1
Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11.1.2
NIE Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11.2

5-25
5-25
5-26
5-27
5-29

5.12
ERRORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12.1
5.12.1.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12.1.2
Basic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12.1.3
Other Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12.2

5-38
5-38
5-38
5-38
5-38
5-39

5.13 PDP-1 I Flfl\;CTIO~,AL DIAGNOSTIC (ZQNA) . . . . . . . . . . . . . . . . . . . . . . . .
ZQNA ?? Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5. 13.1
ZQNA?? Test Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.13.2
ZQNA ?? Error Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.13.3

5-:\9

5.14 MicroVAX DIAGNOSTIC MONITOR (MDM) . . . . . . . . . . . . . . . . . . . . . . . . .
MOM Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14.1
MOM Service Test Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14.2
5.14.2.1
Verify Mode T.,.sts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Field Service Funciional Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14.2.2
Field Sen ice Exerciser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .
5.14.2.3
5.14.3
MDM Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5--19

5-39
5-40
5-41
5-41
5-41
5-ti
~2
.'.i--42

5-B

5.15 DEC/X 11 EXERCISER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 5-44
Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
5.15. l
Command Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5.15.2

Appendix A IC Descriptions
A.I

SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A-1

A.2
A.~'.I
A.2.2
A.2.3

68000 MICROPROCESS( 1R . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signals and Pinout . . . . . . . . . . . . . . . . . . . . .
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A-2
A-2
A-4
A-8

A.3
A.1.i
A.:.2

Q-BUS l\'TERFACE CONTROLLER (QIC) . . . . . . . . . . . . . . . . .
Ov<>rview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signals and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A-9
A-9
A-I I

A.4
A.4.1
A.4.2
A.4.2.1
A.4.2.2
A.4.2.3

QNA2 Q-BUS 1'ETWORK ARBITRATOR . . . . . . . . . . . . . . . . .
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIGNALS AND PINOUT . . . . . . . . . . . . . . . . . . . . . . . . . .
QNA2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . •.
P1nout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A-18
A-18
A--19
A-19
A-24
A-24

A.5

AM7990 LOCAL AREA NETWORK CONTROLLER FOR ETHERNET
(LANCE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signals and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LANCE Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LANCE Registers . . . . . . . . . . . . . . . . . . . . . . . . . .

A-25
A-25
A-25
A-30
A-30

A.5.1
A.5.2
A.5.3
A.5.4

Vil

CONTENTS

A.5.5
A.5.6

LANCE Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logical Address Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A-30
A-34

A.6
A.6.1
A.6.2
A.6.3

AM7991 SERIAL INTERFACE ADAPTER (SIA) . . . . . . . -. . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Margins . . . . . . . . . •. . . . . . . . . . . . . . . . . . . . . . . .

A-36
A-36
A-36
A-39

A.7
A.7.1

THINWIRE ETHERNET TRANSCEIVER . . . . . . . . . . . . . . . . . .
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A-40
A-40

Appendix B Network Management
B.1

SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B-1

B.2
B.2.1

NETWORK CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Contention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .

B-1
B-1
B-1
B-2
B-2

B.2.2
B.2.3
B.2.4

Appendix C

Vector Assignments

C.J

THE FLOATING VECTOR -ASSIGNMENTS

C-1

C.2

FLOATING VECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C-1

Appendix D Programming Examples for PDP-11 Systems
D.I

DATA DEFl'.\ITIO~S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D-1

D.2

RESETTING THE DESQA . . . . . . . . . . . . . . . . . . . . . . . . . . .

D-5

D.3

CO~FIGURING THE DESQA . . . . . . . . . . . . . . . . . . . . . . . . .

D-6

D.4

A SIMPLE INTERRUPT HANDLER . . . . . . . . . . . . . . . . . . . . .

D-12

D.5

DATA TRANSMISSION . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D-13

D.6

DATA RECEPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D-17

D.7

EXECUTING ON-BOARD DIAGNOSTICS . . . . . . . . . . . . . . . . .

D-21

D.il

Bl'FFER DESCR!PTOR MA!'?,\GEMENT ALGORITHM . . . . . . . . .

D-21

Appendix E Glossary

INDEX
FIGURES
1-i

\\aming-;

. .....

1-2

,, ";.in1inr, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Typical Ethernet Configuration . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Connecti\'ity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Thinwire Ethernet DESQA/DESTA!DTE Dai!>y Ch2in. . . . . . .
Typical Ethernet Backport ro DEMPR to DESQA/DESTA/DTE Daisy
Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ethernet Packet (Frame) Format . . . . . . . . . . . . . . . . . . . . . . . .
DESQA Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . .

1 -1

1-3
1-4
1-5
1-6
1-7
1-8

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

1-5
1-7

1-8
1-9
1-11
1-13

CONTENTS

1-9
1-10
I-II

1-12
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
3-5
3-6
3-7

3-8
3-9

3-10
4-1
4-2

4-3
4-4

4-5
4-6
4-7
4-8
4-9
5-1
5-2
5-3
5-4
5-5
5-6
5-7

5-8
5-9
A-1
A-2
A-3
A-4
A-5
A-6

A-7
A-8
A-9
A-10
A-11
A-12
C-1

Host 1/0 Page Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESQA Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESQA Hardware Block Diagram . . . . . . . . . . . . . . . . . . . . . . .
DESQA Handle . . . . . . . . ~ . . . . . . . . . . . . . . . . . . . . . . . . .
Q-Bus Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESQA Backport Bus Structure . . . . . . . . . . . . . . . . . . . . . . . .
Backport Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESQA Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESQA-SA Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Sequence (No Chaining) . . . . . . . . . . . . . . . . . . . . . . .
Host 1/0 Page Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Status Register (CSR) . . . . •. . . . . . . . . . . . . . . . . . .
Vector Address Register (VAR) . . . . . . . . . . . . . . . . . . . . . . . . .
BDL Start Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setup Packet Forn1at (Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . .
MOP Element Block Buffers in the Setup Packet . . . . . . . . . . . . . .
MOP Element Block Types I to 9 . . . . . . . . . . . . . . . . . . . . . . .
QNA2 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESQA Clocks And the Main Selection Switches . . . . . . . . . . ... .
Q-Bus Interface (hardware) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Interface (hardware) . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram of Thinwire Ethernet Transceiver . . . . . . . .
DP8392 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC-to-DC Converter Block Diagram . . . . . . . . . . . . . . . . . . . . .
DMA Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESQA Interrupt and Reset Signals . . . . . . . . . . . . . . . . . . . . . .
Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Warnings . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . .
DESQA Troubleshooting (Thinwire Mode) . . . . . . . . . . . . . . . . . .
DESQA Troubleshooting (Thickwire Mode) . . . . . . . . . . . . . . . . .
Field Replaceable Units (FRUs) . . . . . . . . . . . . . . . . . . .
Lo1Jp Direct !\11 cssages Test Path . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Assist Loopback Message Test Path . . . . . . . . . . . . . . . .
Full A~sisr Loopback Message Te,t Path . . . . . . . . . . . . . . . . . .
Receive Assist Loopback Message Test Path . . . . . . . . . . . . . . . . .
68000 Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68000 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QIC Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QNA2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QNA2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM7990 LANCE Block Diagram . . . . . . . . . . . . . . . . . . . . . . .
AM7990 LANCE Pinouts . . . . . . . . . . . . . . . . . . . . . . . . .
AM7991 SIA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
AM7991 SIA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram of Thinwire Ethernet Transceiver . . . . . . . .
DP8392 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Q-bus Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-15
1-16
1-17
1-18
2-3
2-4
2-5
2-6
2-9
3-3

3-5
3-5
3-13
3-18
'.1--20
3-2R

3-36
3-42
3-43

4-2
4-6
4-9
4-15
-1-18

4-19
+-22

4-24
4-26
5-2

5-3
5-5
5-7

5-S
5-36
5-36

5-37
A-3

A-4
A-10

A-12
A -1~

.-..-:~4
A-26
A-27
A-36
A-37
A-Hl

A-41
C-5

CONTENTS

TABLES
1-1
1-2
1-3
2-1
2-2
3-1
3-2
3-3
3-4

3-5
3-6
3-7
3-8

3-9
3-10
3-11

3-12
3-13
3-14
4-1
4-2
4-3
4-4

4-5
4-6

5-1
5-2
5-3
5-4
5-5
5-6

5-7
5-8
5-9
5-10
5-11

5-12
5-13
A-1
A-2

A-3
A-4
A-5
A-6
A-7

A-8

Field Sizes in an Ethernet Packet . . . . . . . . . . . . . . . . . . . . . . .
DESQA Bulkhead Thickwire D-Type Connections . . . . . . . . . . . . .
DESQA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESQA Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESQA Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESQA Unit 1/0 Base Addresses . . . . . . . . . . . . . . . . . . . . . . .
Control and Status Register (CSR) Normal Mode Usage . . . . . . . . . .
Vector Address Register (VAR) . . . . . . . . . . . . . . . . . . . . . . . . .
Reseived Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setup Packet: Iniormatio,1 Group Comt-i,1ations . . . . . . . . . . . . . . .
Setup Packet Buffer Descriptor: Address Mode Bits . . . . . . . . . . . .
Effects of Reset on Setup Packet Data . . . . . . . . . . . . . . . . . . . .
MOP Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOP Element Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOP Element Types 4, 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOP Element Types 6, 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information Value Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .
MOP Elements Type 8, 9 MEBB Format . . . . . . . . . . . . . . . . . . .
Default Switch Settings (All Closed) . . . . . . . . . . . . . . . . . . . . .
Power-Up LED Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Remote Buot LED Patterns (Normal or DEQNA Mode) . . . . . . . . . .
DESQA and transceiver power requirements . . . . . . . . . . . . . . . . .
Q-Bus Connector Pins and Signals . . . . . . . . . . . . . . . . . . . . . . .
Backpon Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Module LED Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Irrecoverable Failure Indications . . . . . . . . . . . . . . . . . . . . . . .
Citizenship Test: Error Bit Definitions . . . . . . . . . . . . . . . . . . . .
Diagnosti:- Runtime Services (DRS) CClmmands . . . . . . . . . . . . . . .
Command Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flags Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRS Co:nmands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRS Command Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRS Command Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NIE CommanJs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESQA DEC/All Exen.iser Software Regi,;ter Bi1,, . . . .

68000 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QIC Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QNA2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .
QNA2 Registers . . . . . . . . . . . . . . . . _. . . . . . . . . . . . . . . . .
AM7990 LANCE Signal Definitions . . . . . . . . . . . . . . . . . . . . . .
LANCE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LANCE Initialisation Block . . . . . . . . . . . . . . . . . . . . . . . . . . .
LANCE Descriptor Ring Pointers . . . . . . . . . . . . . . . . . . . . . . .

·x

1-10

1-22
1-23
2-10
2-ll
3-4
3-6

3-14
3-21
3-23
3-32
3-34
3-37
3-40
3-41
3-44
3-45
3-46
3-48
4-3
4-4
4-4

4-7
4-10
4-23
5-10
5-10
5-15
5-20
5-21
5-21
5-22
5-25
5-26
5-27
5-28
5-29
5-4:-i
A-5
A-13
A-19
A-24
A-28
A-30
A-31
A-31

-"-,

CONTENTS

A-9
A-10
A-11

C-1
D-1

LANCE Four-Word Descriptor Ring Formats . . . . . . . . . . . . . . . .
LANCE Logical Address Filter Mask . . . . . . . . . . . . . . . . . . . . .
AM799 l SIA Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . .
Aoating Vector Address Assignments . . . . . . . . . . . . . . . .
Data Definitions for Sample Programs . . . . . . . . . . . . . . . . . . . . .

A-32
A-34
A-38

C-2
D-2

PREFACE
The DESQA is a quad height module, designed to fit the BA200 series of enclosures. The module will provide
.an interface from the Q-Bus to one of two implementations of local area networks. The two are Thickwire (IEEE
802.3 IOBASE5) and Thinwire (IEEE 802.3 I0BASE2). Selection of the implementation supported is by a single
jumper block on the module.
This.manual describes how the DESQA communications module functions internally. It provides information for
detailed system programming, field service support and for customer engineers
The chapters are as follows:

CHAPTER 1 introduces the DESQA module and its interfaces.

CHAPTER 2 is a functional description of the DESQA module.

CHAPTER 3 describes how to program the DESQA module.

CHAPTER 4 details the architecture and operatims of the module.

CH APTER 5 maintenance

APPENDIX A s11mmarise!> the details of the principal Integrated Circuits in the DESQA module.

APPENDIX B describes the Ethernet Network Management protocol.

APPENDIX C details the DESQA vector address and assignments.

APPENDIX D gives examples of host software programming of the ~ESQA.

10. APPENDIX E is a glossary.

Notes and Warnings

Notes and warning!> are detined as follows:

•

A NOTE contains l?eneral information

A WAR~I~G i~ de!>ignC'd 10 prevent per,;onal injury.

xiii

Preface

Related Publications

Communications Options Mini-Reference Manual: Volume W (Ethernet) (EK-CMINI-RM)
DECnet Maintenance Operations Protocol (MOP) Functional Specification V3.0.0 (AA-X:436A-TK))
DECnet-RSX System Manager's Guide (AA-H224C-TC))
DECnet-VAX System Manager's Guide (AA-H803C-TE))
DECconnect System Installation and Verification Guide (EK-DECSY-VG)
DECconnect Planning and Configuration Guide (EK-DECSY-CG)
DESQA Installation Guide (EK-DESQA-IN)

FCC NOTICE: The equipment described in this manual generates, uses, and may emit radio frequency energy.
The equipment has been type tested and found to comply with the limits for a Class A computing device pursuant
to Subpart J Part 15 of FCC Rules, which are designed to provide reasonable protection against such radio
frequency intcr1ace .vhen opt:rated in a commercial environment. Operation of this equipmerit in a r~sider.tial
area may cause int~rference. in which case the user at his own expense may he required to take measures to
correct the int~rference.

xiv

CHAPTER 1
INTRODUCTION
1.1 SCOPE
This chapter introduces the M3127 module, which is a DIGITAL Ethernet Local-Area-Network switchable Q-Bus
Adapter (DESQA). The sections are as follows:

Section 1.2 ETHERNET OVERVIEW
Section 1.3 DESQA FUNCTIONAL OVERVIEW
Section 1.4 DESQA TECHNICAL OVERVIEW
Section 1.5 SPECIFICATION

1.2 ETHERNET OVERVIEW
The DESQA can support either of two possible Ethernet cabling systems. These arc the standard Ethernet which
will be referred to as Thickwirc Ethernet, and Thinwire Ethernet. The principal characteristics of the Ethernet
are:

Topology:

Branching bus

Medium:

Shielded coaxial cable

Transmission:

Manchester-encoded digital baseband signalling

Dati> Rate:

IO Megabits/second.

Access Control:

Carrier Sense, Multiple Access with ColJision Dete..:t l CS MA/CD 1.

Allocation:

64- lo 1518-byte packet length (indudes variable-length data field bet\l.een 46 and
1500 bytes).

1.2.1 Safety Warnings
See Figures 1-1 and 1-2.

1-1

INTRODUCTION

WARNING
Ethernet installations may extend to thousands or meters and couple hundreds or separate items of equipment. To prevent hazardous
voltages appearing on the installation, it is important that all the equipment be part of a common equipotential bonding system as
defined in IEC publication 364-4-41 clauses 413.l.2 and 413.1.6. Where it is required o couple equipment outside ofthe main equipotential
bonded area via ethernet, then optical repeaters or other such galvanically isolated measures must be employed. If in doubt please
refer to Digital for advice.

VAROITUS
Ethernet-verkot voivat olla tuhansia metrejii pitkiii ja niihin voidaan liittiiii satoja erilaisia laitteita. Jott11 verkkoon ei paasm
ayntymiiiin vaarallisia jiinnitteitii, kaikkien laitteiden on ehdottomasti kuuluttava samaan potentiaalintasausjirjestelmiiin, jonka
ominaisuudet on miiiritetty IEC:n julkaisussa 364-4-41, kohdissa 413.1.2 ja 413.1.6. Mikili Ethernetiin halutaan liittaiilaite, joka ei
kuulu potentiaalintasausjiirjestelmiiiin, on kiytettiiviioptisia toistimia tai vastaavia galvaaniseati eristettyji menetelmii. Jos et ole
varma kiiytettiiviistii menetelmiistii, ota yhteys Digitaliin.

DANGER
Une installation Ethernet peut s'etendre sur des kilometres et relier des ccntaines d'elements. Afin d',.viter tout probleme electrique,
veritiez la pri·scncc d'un~ n:i,e a la terre commune ainsi qu'elle est definie par l'IEC (364.4.41, clauses U3.1.2 et 413.1.6). S'il s'a,·ere
necessaire de relier par Ethernet des equipements non rattaches ii une meme terre, utilisez des repeteurs opuques ou autres materiels
oft'rant la meme qualite d'isolation. En cas de doute, prenez contact avec les Services techniques Digital.

VORSICHT
Ethernet-Netzwerke kcinnen sich iiber mehrere tausend Meter erstrecken und mehrere hundert einzelne Geriite miteinander
verbinden. Zur Vermridung \'On ~cfiihrlichen Spannungen im Jl;etzwerk ist es nnbedingt erforderlich, daO alle Geriite Teil einer
gemeinsamen Erdungsschleife s1.1J, wie in den IEC-Richtlinien 364-4-~l. Abschnitte 413.1.2 und ,03.1.6 angegeben. Wenn Geriite
auOerhalb der Erdungsschleife iiber Ethernet miteinander verbunden werden miissen, miissen optische Repeater oder andere
galvanisch getr«nnte Mittel verwrndet wnrien. Falls Sie Frageu haben. wenden Sie sich an Digital Equipment.

WAARSCHUWING
Ethernet-configuraties kunnen een afstand van verschillende kilometers overbruggen en honderden afzonderlijke apparaten met
elkaar verbinden. Om te vermijden dat er zich gevaarlijke spanningen zouden voordoen op de configuratie, is het belangrijk dat alle
apparatuur gebruik maakt van dezelfde voeding en dezelfde aarde, zoals gedefinieerd in de IEC-publikatie 364-4-41, bepalingen 413.1.2.
en 413.1.6. Wanneer apparatuur die nitt op eenzelfde equipotentianl spanningsnet is aangesloten via Ethernet gekoppeld moet worden,
moet men gebruik maken van optische repeaters of van andere galvanisch isolerende technieken. Bij twijfel gelieve u contact op te
nemen met Digital.

ATTE1,ZION1i:
Le mstallazioni l:.thernet possono estendersi per mi1,;liaia di metri e collegare diverse centinaia di elementi separati di
apparecchiature. Per evitare ii rischio di scarichc elettriche al momento dell'installazione, e importante che tuttP le apparecchiature
siano collegate ad un cmnune •istemR di massa come definito nella pubblicazione IE(' 3G~-1-11, c!aus:>le 413.1.Z e 413.1.6. Ladclove ~i
richieda di collegare l'epparecchiatura fuori dalla principale area .!i mas~a via Etl.ernt-t, si devono utiliu.:..rc rip, titori su fihra ottica o
quolsiasi altro strumento isolato gshanicamente. Per qualsiasi informazione rivolgersi nils sede Digital piu vicina.

ADVARSEL
Ethcrnrtinstallasjoner kan strekke seg over flere tu~en meter og ha tilkoblet flere hundre forskjellige ut~tyrsenheter. For A forhindre
at det ska] ..ippst.A f:1rhJ,!t! spennin,ier pA insta!la$jnnt.n. <•r det ,·iktig at alt utstyret tilhorer et felles ekvipotensialt fnrbjndelse-h:ystern.

slik deter defin,-rt i IEC-publikasjon 364-4-41. parai:rafone 413.l.2 og 413.1.6. Der hvor dct er pilkrC'''"t :\ koble utstyr vie f_theruet
utenfor det ekvipot.,nsiale hovedomr&dPt, er dl't :,ahurit a benytte opti~ke hnjcfo1sterkPre (rrpe ... ,re) rllrr til:;varende ralvunisk
isolert materiale. Kontakt Digital hvis du er i tvil.
RE7124

Figure 1-1

1-2

Warnings

INTRODUCTION

ATENCION
Las instalaciones basadas en Ethernet pueden cubrir areas de varios centenares de metros e interconectar distintos modulos de un
equipo. Para evitar que se den tensiones peligrosas en la instalaci6n es necesario que todos los compo~entes se conecten a una mass
unica, de acuerdo con normas IEC 364-4-41 (§413.1.2 y §413.1.6). Cuando sea preciso utilizar Ethernet con componentes que no vayan
conectados a dicha masa comun se utilizaran repetidores 6pticos u otros dispositivos de medida con aislamiento galvanico. En caso de
duda consulte con Digital.

VARNING
Ethemet-installationer kan omfatta tusentals meter kabel som kopplar samman hundratals separata delar av en utrustning. For att
skadliga spiinningar ska undvikas iir det viktigt att all utrustning bar gemensam jord enligt vad som anges i IEC:s skrift 364-4-41,
avsnitten 413.1.2 och 413.1.6. Dir det iir nodviindigt att ansluta utrustning med annan jordning via Ethernet, miste optiska kopplare
anviindas eller andra itgiirder vidtas for att astadkomma galvanisk isolering. Kontakta giima Digital f"or ytterligare information.

AVISO
A instaliu;ii<, da lsthe,.nPt pnde estender-se por inilhares dt> n,etros e acrrupar centenas de itens de PffUipamcnto.
Para l!vitar que voltagens perigosas surjam na im,talacih. e importante que todo o cquiµamento fac" p>trte de um sistem:. ele,·trico
equipotencial comum, tal como definido na publicacio 364-4-41 do IEC, clausulas 413.1.2 e 413.1.6.
Onde for necessario ligar equipamento fora da area principal de ligacio electrica equipotencial, atraves da Ethernet, deverio ser
empregues repetidores 6pticos ou outras solucoes galvanicamente isoladas.
Em caso de duvida, contacte a Digital.

ADVARSEL
Ethernet-installationer kan str1Pkke ~ii< ovl'r lusindvis .,~meter cg forbin.Je hundredevis af sep.. rat<· d~le af udstyr. For at undj!a farlig
spa,nding i installationerne er det vigtigt. at alt udstyret er del af et faelles jonlingspunkt som defineret i IEC publikation 364-4-41.
klausulcrne 413.1.2 og 413.1.6. Hvor deter nodvPndigt at forbinde udstyr udenfor det &terre Caellesjordingspunkt via Ethernet, ska) dcr
anver..:l"s optisk kobling eller anden form for gnlvanisk isolering afudstyret. For yderligere oplysninger hPnvises tll den lokale Dilitital
afdeling.

Fn , o•,on '!J':JN •\'!) 'Ju O'Ol/!J':J n,11,nl'ln ETHERNET-n n1\'pnn
o•nnn 111tn, •,J .o•,,!Jt 11•~ •o•,!J n1Nn nnJ ':J1':JJ':J n1':J1':J11
,,,~n '.JJl'.I 1•gpn':J J11'/n ,Nn ,1pnnJ ntJo n,,n, o•':Ji,uv o••,nvn
1 'J n,1rnJ71 n\':m 1mz.o m.r~nt:i mm1vm ?nl'ln n:n1Jnn p'.Jn .,, i:-1·
, '.)i-,•~tOl!)Jl
n:n J'i J\'.l;l , ,l']'J71J
Ol!J7 ,:i, ,~EC -:i 77ll,l\'.I '!)J
.413.1.6 -1 413.1.2 O'!J'lJO 364-4-41
nN ':J'.J1J;i n\'Jn':J -i_,nn ,, •~ •o•,!J 1 'J ,Jn'.J ,,,,\' onJl'I nin1pnJ
l'.lrJnvn, O'J"n •1i-, ,ETHERNET n111:snz..::i ,n!lmvn:i n''!l1-<7;-; 'Jn~•n· n:r,:.;:J
o•,nz.< D'l/~JJNJ lN \0PTICAL REFEATERS, BP.:[.';ES) 'V!)lN 7;':i:,
.•nJnn ~~, o·,,,Jnn
.J1,p;, " " ' l ' • ,,l'ln'.l m\'!J':J 1-1\' ,mP!.-'J n,,ur,'1 n,•nJ

.;',til((.:~.'i.-t"f.,lc:f.+i 7>··~ft.7>ft:4z:-i•J1 ~ t.:"'1(:,i.

IE<. ~fli 1 t, .1 •• -I - -I l :•,
~Ii"l I l 1. I.~. ;t,,t[.•.1 1 3. 1. t,(.:iic.n:,iL-:~,;,:,,t ;d:. ~-;:".7>1f'i~f,,
:ft)l!!f~tl!!;., 7.,. 7' .[, {:f~f:'~ ::- J l-: I. 1 7-, _:. t IJi •f •~~: -J-

c!t,l!itttt!!.;, 7.-r.!.(.:tiit:.'.·: 3- ,:.-.-tll,P/i c ltl!.71 t.1, " f ) (.: -( --tt ,r••, I· -i' >t '- ·: ~
~ ~ J2:'{ri""T 7-, ,12:•~;~·•_i-) ~. t~ ~ - -;,t? "7- 'h IL 1 J t - $' _ £ t.:.C:J:~-li:~8/;Jl: Jr;ff ~ i;.,t:_
.:rnz-tJ\ ~ ;:. .:. :::1,•.e-~·:-r
RE7125

Figure 1-2
1-3

Warnings

INTRODUCTION

1.2.2 Thickwire Ethernet-General Description
Ethernet employs a branching-bus topology, with all nodes granted equal access rights. Using repeaters, the main
bus can be extended up to 2.8 kilometres (1.74 miles) between the two furthest nodes of the network. Along this
length, up to 1024 nodes can be tapped into the network.
•
Each node is a single addressable entity, comprising a controller and a transceiver. 1be transceiver is connected
to the Ethernet cable by a cable tap. The cable that connects the transceiver to the controller can be up to 50
meters Jong. The transceiver itself is not always necessary: for example, the connection to the Ethernet may be
made using a DELNI multiplexer. Figure 1-3 shows an example of a large-scale Ethernet configuration.

1-4

INTRODUCTION

SEGMENT1

LOCAL
REPEATER
PDP

PDP

VAX

SEGMENT2

VAX

DELNI

REMOTE
REPEATERS

Micro
POP

PRO

SEGMENT3

PRO

PDP

~
SEGM::.NT TERMINATION
I

KEY

H4XXX TRANSCEIVER/CABLE TAP
TRANSCEIVER CABLE
HOST NODE
(COMMUNICATIONS CONTROLLER
ANO HOST SYSTEM)

.....,

Figure 1-3

Typical Ethernet Configuration
1-5

INTRODUCTION

The maximum Ethernet configuration for a coaxial cable bus is as follows.
•

Each segment of coaxial cable can be up to 500 meters long (1640.5 feet). Each segment must be terminated
at both ends.

•

Up to 100 nodes can be tapped into a cable segment. Each node must be between 2.5 meters (8.2 feet) and
1500 meters (4921.5 feet) from its nearest neighbours. Standard transceiver positions are usually marked at
every 2.5 meters.

•

A transceiver cable (from transceiver to node controller) can be up to 50 meters (164 feet) long.

•

Repeaters are used to retransmit signals from one segment to another. A repeater uses a node position,
and also contributes to the total node count, on both the segments that it connects. There can be up to two
repeaters in the path between any two nodes.

•

Repeaters can be placed at any position along a cable segment to extend the network bus up to a maximum
of 2.R kilometres (1.74 miles). This would comprise three segments of 500 meters. plus six tran<:ceiver cables
of 50 meters, plus a I km fibre cable between remote repeaters.

The Ethernet configuration rules ensure the best network performance within physical channel limitation<,.
Figure 1-4 shows the limits of Ethernet connectivity.

1-6

----..,,,

INTRODUCTION

MAXIMUM SEGMENT 500m, WITH UP TO 100 NODES

SEGMENT 1
LOCAL REPEATER
TAKES ONE NODE
POSITION ON BOTH
SEGMENTS

SEGMENT2

MAXiMUM TRAN;,CEIVER
CABLE LENGTH (TRANSCEIVER TO
CONTROLLER) 50m

1
B

DELNi

D
D

Micro
P:)P

MAXIMUM BUS LENGTH (ALL SEGME:.NTS) 2.8Km
WITH UP TO 1024 NODES
STANDARD NODE SEPARATION MINIMUM 2.Sm MAXIMUM 1500m

Figure 1-4

Ethernet Cormee:\ ity

1.2.3 Thinwirc Ethernet-General Description
Thinwire 'Ethernet offers an alternative ba~eband cabling system that provides full Ethernet capat>ility for per,0na!
:::omputcrs. 'l'tOrkstations. and low-end systems in offices and other local work areas. Thinwire Elhem.::t is ;1
low-cost. flexible companion system to Thickwire Ethernet that utilises an industry standard cable to connect up
to 30 stations in one 185 meter segment.
The DESQA is part of a cabling and hardware set that connects Q-Bus systems in BA200 series enclosures. to a
standard Thin"'ire Ethernet cilble segment. The maximum length of a Thinwi1e E:I.cmt>I ,cgn1ent is l ~5 meters.
30 ,k\11.·es may be connecied to a singk segment. A Thi11\\:rc Ethernet d2isy ciia:1. -.l'gm..:n; con,i,1~ ur s,ct;ors
linked togtther by BNC T-cc,nnector'-. The bottum of the "1" is insertcJ into a DE~QA. wi,i.:-h is ir.;l·rh.:d :nto
the system enclosure. "T" connectors may be a minimum of 0.5 meters apart.
It is possible to have up to eight of these daisy chains by using a DEMPR to form a network of up to 232
stations. A local network interconnect (DELNI) may be used to concentrate up to eight DEM PR ·s.

For more i11format:on on Thim,.,ire configuration using DEMPR. see the Digital Thinwire Ethernet \1ultip 1 >rt
Repeater (DEMPR Installation and User's Guide (EK-DEMPR-UG).

1-7

INTRODUCTION

50-OHM
TERMrATOR
DECserver 200
TEE-CONNECTOR ~
AND DESTA

ESTA

UP TO 29 STATIONS
ON ONE SEGMENT

]

BA200 ENCLOSURE

a::J CJ

50-OHM

~CJ

TERMINATOR

LAST

~ NODE

11(7204

Figure 1-5

Typical Thinwire Ethernet DESQA/DESTA/DTE Daisy Chain.
}-8

INTRODCCTION

H4000

STANDARD ETHERNET BACKBONE SEGMENT

:,--o

◄◄---- TRANSCEIVER CABLE (OPTIONAL)

DEMPR

8 SEGMENTS

•••••••••

THINWIRE
ETHERNET
CABLE

~~ DECserver 200
TEE-CONNECTOR __ _..
AND DESTA

DESTA

UP TO 29 STATIONS
ON ONE SEGMENT

BA200 ENCLOSURE

UP TO 29 STATIONS
ON ONE SEGMENT

,-4.,.,,

BA200 ENCLOSURE

DESQA

LAST

50-OHM
TERMINATOR

LAST DTE

Figure 1-6

Typical Ethernet Backport to DEMPR to DESQA/DESTA/DTE Daisy Chain
1-9

DTE

INTRODUCTION

1.2.4 Ethernet Layers
The Ethernet architecture is structured in two layers which correspond to the lowest layers in the International
Standards Organisation (ISO) model for Open Systems Interconnection (OSI).
The two layers have the following functions.
•

The physical layer specifies the maximum number of nodes, their maximum separation. the data rate on the
Ethernet bus, as well as the electrical and mechanical connections.

•

The data link layer specifies the mechanism for access control (CSMA/CD), the procedure for muhiaccess
network control, and the format of transmission packets.

The physical layer and the data link layer together provide a datagram service for transmitting message packets
between nodes. A datagram service cannot guarantee that a packet is received, because transmission and reception
are the responsibility of higher levels in the network architecture; but it does guarantee that those packets that are
received are correct.
The DESQA module handles all of the physical layer, and part of the data link layer functions. Host
software handles the higher levels of protocol, as well as network management. error recovery. inter-network
communication, and the user interface.
1.2.5 Data Encapsulation
Data is transmitted over an Ethernet in packets (or frames) that have a specific format.
Figure 1-7 shows the format of an Ethernet packet. Table 1-1 gives the size of each field in an Ethernet packet.
Table 1-1

Field Sizes in an Fthern~t Packet

Field

Bytes

Destination

Source

Type

Data

46 to 1500

CRC

Total pad.t't

64 to 1518

A packet is preceded by a 64-bit preamble which is a pattern of alternating ls and Os for receiving node
synchronisation. The pattern ends with ...0101 I rather than ... 01010.
The fields in the packet are as follows.
I.

The destination field con:ains the 48-bit addre~s of the rcc,~1ving node(s). The addres!> i, tither physical or
logical. and it may be any one ot the following.
•

An individual node address (first address bit = 0)

•

A multi-cast address for a group of nodes (fir,;t address bit = 1).
A broaJcast address for all nodes (all address bits = 1).

The source field contains the 48-bit Ethernet physical address of the sending node.

The 16-bit type field determines how higher-level software interprets the data field.
1-10

INTRODUCTION

The protocol data field itself must contain between 46 and 1500 bytes. If the data to be sent consists of less
than 46 bytes, software must insert null bytes to fill the field.

The frame check sequence (FCS) contains a 32-bit Cyclic Redundancy Check (CRC) value. The DESQA
module calculates this value, inserts it when a packet is transmitted, and checks it when a packet is received.
The CRC is removed from a packet prior to delivery to the host.

The interframe spacing (or interpacket gap) allows the physical channel to recover between packets. The
minimum spacing is 9.6 microseconds.
Figure 1-7 shows the standard Ethernet packet format.

NOTE
In an IEEE 802.3 packet, the type field is replaced
• with a 2 byte length field to indicate the number of
data bytes contained in the data field.

PREAMBLE

DESTINATION

SOURCE

8 BYTES

6 BYTES

DATA
2 BYTES

CRC
1:l\7EP.FRAr:1E1
----'-----~.G~~----J
4 BYTES

BETWEEN 46 ANO
1500 BYTES

9.6 MICROSECONDS
(MINIMUM)

- - - - T O T A L SIZE OF PACKET IS BETWEEN 64 AND 1518 BYTES - - - -

Figure 1-7

Ethernet Pa.:kct (Frame) Format

1.3 FVNCTIONAL OVERVIEW
The DESQA {DIGITAL Ethernet Switchable Q- Bus Adapter) is a quad height module having a recessed bulkhead
which physically supports the interface connectors. This type of handle is required hy the nature of the BA200
series enclosures, which eliminate the need for cabkits. The DESQA module is functionally equivalent to :i
DELQA with a cabkit for Thickwire networks combined with DESTA Thinwire transceiver for interfacing to
Thinwire networks.
The DESQA provides an interface from the Q-Bus to either a Thinwire or Thickwire Ethernet (IEEE 802.3
Network). It is fully supported by both PDP-I I and MicroVAX families available in the BA200 enclosures. The
choice of Thickwire or Thinwire is switch selectable.

1.3.1 Normal ,1ode and DEQNA-Lock Mode
The DESQA module operates in one of two switchable modes: Normal mode or DEQNA-lock rnodt:.
In Normal mode. DESQA supports the following functions:
Maintenance Operations Protocol (MOP) messages for Remote BOOT. Request ID. Transmit Sy-;tem JD and
Loopback
IEEE 802.3 Maintenance Me~sages for XID {Transmit IDi and TEST on NL-LL LSAP (Link-lays.:r Sen ice
Acee,~ Point) access points
Self-test on powerup and via host command
Single Ethernet physical addres-, (the first of any specified in a setup packet to replace the default held in
Station Address ROM)
Multiple Ethernet Multi-cast addresse~

1-11

INTRODUCTION

•

All standard DEQNA functions, except multiple Ethernet physical addresses and the automatic enabling of
the on-board sanity timer at powerup.

In DEQNA-lock mode, DESQA provides functional compatibility with DEQNA modules, but at the expense of

losing some Normal mode functions. The functions supported are:
•

Multiple Ethernet physical addresses

•

Multiple Ethernet Multi-cast addresses

•

Sanity timer (Switch enabled on powerup).

The operating mode is selected at powerup by the setting of the mode switch (S3) on-board the DESQA module.
If mode switch S3 is closed, the module operates in Normal mode; subsequently, host software can use the Vector
Address Register (VAR15) to set the operating mode to either Normal mode or DEQNA-lock mode. If mode
switch S3 is open, the operating mode is fixed as DEQNA-lock, and this cannot be altered by software. Use of
DEQNA-lock mode is not recommended.
Host software can detennine whether the module is a DESQA or a Dl:.QNA by using bit O in the Vector Address
Register.

.._,,

1.3.2 Module Interfaces
The DESQA is a microprocessor-based device which provides all the logic necessary to connect to the Ethernet.
It acts as a data communications controller, executing the physical layer protocol and part of the data link layer
protocol (as defined by the seven-layer OSI model). The protocol functions include synchronisation, format
conversions, encoding and decoding, formatting data packets and data link management.
The DESQA enables programs that execute higher levels of protocol, such as DECnet, to communicate with their
peers over the Ethernet link.

The DESQA module performs all the channel access functions ;,ecessary to achieve maximum throughput with
minimum intervention from the host processor, including:
•

Block-mode Direct Memory Access (DMA) to host memory

•

Control OMA, which uses Buffer Descriptor Lists (BDLs) in host memory to sequence transfers between
data buffers in the host and in the DESQA.

The DESQA implements some of the Maintenance Operation Protocol (MOP) functions on request from a
remote station without host intervention. These functions include host reboot, loopback operations, and system
identification.

1.3.3 Module Operations
The DESQA module transfers data between buffers in host memory and the Ethernet transceiver. The main data
flow operations are as follows:
1.

Transfer of data between host memory buffers and shared RAM in the DESQA.

Conversion of data and status information between the host format and that used in the DFSQA module.

Transfer of forn1aued data packets between shared RAM and the Ethernet connector.

The data is fonnattf'd in packet~ of between 60 and 1514 data bytei. at a higher levd ot protocol. The DESQA
module calculates and appends a four byte CRC (Cyclic Redundancy Check) to transmit packets, and strips the
CRC from receive packets. Therefore, the full length of a packet on the Ethernet is between 64 and 1518 bytes.
Figure 1-8 shows how transmit and receive data is passed between the main functional componenti. of the
DESQA module.

1-12

--,,

INTRODUCTION

,___ _ _ _ _ _ _ THICKWIRE
THICKWIRE ETHERNET TRANSCEIVER
(H4XXX)
1---------...,

THINWIRE ETHERNET

... \

----v'

THINWIRE
SELECTOR
TRANSCEIVER - - - ~ BLOCK
DP8392

_ SERIAL INTERFACE
ADAPTER (SIA)

LOCAL AREA NETWORK CONTROLLER
FOR ETHERNET (LANCE)

f
I

FORMAT
COi\lVERS!ON

TRANSMIT
FIFO
BUFFER

68000
MICROPROCESSOR

SHARED
RAM
RECEIVE
FIFO
BUFFER

DATA

•

I 0-BUS

OMA

INTERFACE
CONTROLLER
(QIC)

DATA AND
CONTROL OMA

t ----...---

Figure 1-8

HOSTO-BUS

DESQA Functional Block Oiagram
1-13

INTRODUCTION

1.3.4 Protocol Functions
The Physical Channel Functions and the Data Link Functions are described in this section.
1.3.4.1 Physical Channel Functions
The DESQA module transmits and receives at 10 Mbit/s. It provides physical channel functions that are specific
to Ethernet and necessary for the interface to the DIGITAL H4.xu Ethernet transceiver. DESQA executes the
following functions:
During transmission
•

Encodes serial data in Manchester format

•

Recognises heartbeat and self-test collision detect signals from the DIGITAL H4.ux transceiver, verifying
that the transceiver is monitoring collision detect sign~s.

During reception
•

Senses transmission carrier from any Ethernet station

•

Decodes the incoming serial bit-stream from its Manchester format.

1.3.4.2 Data Link Functions
The DESQA module provides the following Ethernet-specific functions at the data link layer:
During transmission
•

Generates the 64-bit preamble for synchronisation

•

Provides parallel-to-serial conversion of the frame
Calculates the 32-bit CRC value and places it in the packet sequence field for transmission

•

Attempts automatic, multiple re-transmissions upon receiving a collision detect signal.

During reception
•

Checks the 32-bit CRC value in each incoming packet

•

Perfo1ms address filtration. either to match an incoming message to the physical address of the module, or to
accept messages broadcas, to a group of stations

•

Synchronises to the preamble, and removes it prior to processing

•

Provides serial-to-parallel conversion of the frame.

The Ethernet provides a datagram service; that is, sending a packet does not guarantee that it will reach its
destination. The software for the protocol layers above data link is respon,;ible for checking that a packe! has
been received. and for recovering from conditions where it has not been received.

1.3.S Q-Bus Interface
As bus master of the Q-Bus, the host can program the DESQA module by mear.s of eight \\ord-length registers
in the 1/0 page of the Q-Bus memory map. The DESQA acts as bus slave to suppon access trom the Q-Bus to
these on-b<"'lard locations.
Four of the 1/0 page addresse~'. are write-only registers. used to pass the start add;·es,cs of the BDLs for tram,mit
and receive bufferi,. Two are read/write registers: the Control and Status Regisk:r (CSR) and the Vector Addres~
Register (VAR).
The lower bytes of each of the first six addresses are read-only registers, used to access the Station Address (SA)
ROM. The SA ROM contains the 48-bit physical address of the DESQA module in the Ethernet LAN.

1-14

I!liiTRODUCTION

OCTAL

READ REGISTERS

WRITE REGISTERS

CONTROL AND STATUS REGISTER

VECTOR ADDRESS REGISTER

ADDRESS
BASE+ 16
BASE+ 14

STATION
ADDRESS

TRANSMIT BDL
START ADDRESS REGISTER

BASE+ 12
STATION
ADDRESS
BASE +.10
STATION
ADDRESS

RECEIVE BDL
START ADDRESS REGiSTER

BASE+ 06
STATION
ADDRESS
BASE+ 04
STATION
ADDRESS
BAs·E + 02
STATION
ADDRESS
GASE+ 00

At.166f

Figure 1-9

Host 1/0 Page Map

1.4
TECHMCAL OVERVIEW
The DESQA mmlule comprises of one quad-height Q-Bus module. The DESQA module plugs imo the Q-Bus
hackplane inside the BA'.!00 enclosure.

1.4.1

Module Components

On the DESQA board there are six t.1ain integrated circuits to perform the mair. module operations (refer w
Section 1.3'.3 ). These operations are cor:trolled by the on-board microprocessor. Data storage is provided by
shared RAM.

1-15

BNC CONNECTOR

LED 5
(THICKV'JIRE)

....----.-.I
I I

D-TYPE CONNECTOR

I I

0
z

FUSE ( 1.5A SB)

ODO
I

E46 (8392)

E41 (SIA)

LED 1
LED 3
LED 2

1 2 3 4 5

:?l

E13 (LANCE)

!1Q

=
~

i,.o

E39 (68000)

I
°'

ODD

§J

I
I

E29 (68000 ROM)
E28 (68000 ROM)

~L~~ED

~ ~~ ~ ~

SWITCHPACK

I
I

E5 (SHARED RAM)

D I

I:""

E36 (QIC)

I»

E4 (SHARED RAM)!
E24 (QNA2)

=
....

E3 (SHARED RAM)

E2 (SHARED RAM)!
E1
(SA ROM)

MULTl JUMPER
BLOCK

)

NOTE : HANDLE NOT SHOWN

PICOrUSE (5A)

AUMl99

)

INTRODUCTION

Figure 1-11 shows the major components of the DESQA module and their interconnections.
TO THINWIRE E/N

TO THICKWIRE TRANSCEIVER

SIA

LANCE

LS646
DATA
LATCH

FIRMWARE
ROM

I
I

F244
ADf"lRESS
L.A.TCH

F373
ADDRESS
LATCH

ADDRESS BUS

I
I

---J_Ji
68000

SHARED
RAM

LS245
DATA
LATCH

CONTROL

~ SAROM

DAT A,'ADDRESS BUS
~

QIC

F373
ADDRESS
LATCH

1 2 '.J ,' 5

CLL.SEiJ - ■ ■ I •
I!.!'! ' 1 ! I
OPEN
L: LJ J l.JL.!

QNA2

LED 1

SW 1CHPACK
Q-BUS TRANSCEM:RS

Figure 1-11

DESQA Hardware Block Diagram

1-i 7

CONTROL

---!

INTRODUCTION

SELF TEST
LEDS.___
ETHERNET
ADDRESS
LABEL

3
2,
«:, 1 ,

THICKWIRF
CONNECTluN

RP:W3

Figure 1-12

DESQA Handle

1-18

INTRODUCTION

1.4.1.1 Integrated Circuits
The principal integrated circuits in the OESQA module are:
I.

Q-Bus Interface Controller (QIC)

This gate array provides a OMA path between the host system memory and the shared memory on the
OESQA board, and between SA ROM and host memory. The QIC also allows the host system access to the
internal registers of the OESQA.

2. 68000 Microprocessor
This is the 16-bit microprocessor which controls the OESQA and performs the necessary conversions of the
frame data between host buffer format and Ethernet packet format.
3.

Q-Bus Network Arbitrator (QNA2)

This gate array provides access to the backport bus, arbitrating between the QIC, the 68000 microprocessor.
and the LANCE.
4.

Local Area l'ietwork t.:ontroUer for Ethemet (LANCE)
This is a \'LSI circuit which performs bidirectional OMA between shared RAM and the Serial Interface
Adapter (SIA).

Serial Interface Adapter (SIA)

This is a VLSI circuit which links the LANCE to the transceiver. (H4xxx for Thickwire onboard OP8392 for
Thinwire). Tht: SIA provides Manchester encoding of data transmitted, and decoding of data recfr:,•ci.
6.

Thinwire Transceh-e1· (DP 8392)
This is a VLSI circuit which links the serial interface Adapt.:r (SIA) to the Thinwire Ethernet BNC connector.

1.4.J .2 On-board Memory
The DESQA module contains both preprogrammed ROM and static RAM. as follows:
I.

Firmware ROM contains 12K words of master control program for the module (executed by the 68000
microprocessor). In addition.the firmware ROM contains 4Kbytes of self test diagnostic code and 4 Kb)1es
of PDP-I I boot/diagnostic code for execution by a POP-11 host. (MicroVAX systems provide equivalent
bool/diagnosti..: code in their own host system ROM.)

Station Address (SA) ROM. (32 bytes) contains. in the first six bytes, the default physical address of the
DESQA module. The SA ROM alsc, contains a 2 byie checksum which is accel,sibk to host i,oftware.

Shared RAM (16Kwords) provides the memory for data packet buffers, Buffer Descriptor Listi. 1BDbf the
\'<:ctor Add,~<.s Rcgi,ter. tht' LANCE initialisation hlock (wh;ch inclmles the phy.,iu1 1 .icl-ir..-,, ..... the module,
and tim1\\ "' c Jata structurci,.

J.4.t.:-; DC-to-DC Converter
This convens the +12Vdc from the backplane to the -9V required for the DP8~92 transceiver.

1-19

INTRODUCTION

1.4.2 Module Processing Operations
The operation of the DESQA can be broken down into processing modules. as follows:

The QIC transfers data between Q-Bus HOST memory and shared RAM. as follows:
•

Block-mode (or non-block-mode) data DMA (block size up to 16 words) to transfer data buffers directly
to and from shared RAM

•

Control DMA (block size up to four words) to transfer control information and Buffer Descriptor List
(BDL) entries. Control DMA does not use block-mode.

The 68000 microprocessor translates data and status information between the format recognised by the host
system and that recognised by the LANCE.

The QNA2 provides access to the backport bus. arbitrating between (in order of priority): the QIC, the
68000 microprocessor, and the LANCE. It also provides all the gating and strobing signals necessary for
these devices to access shared RAM.

The LA]\jCE and the SIA operate together to transfer the tra11slr.;eC.: packets between :,hared RAM and the
Ethernet transceiver.
If Thickwire mode is selected. the packt:t~ pass through the 15 way D-type connector on the handle and
onto the transceiver cable. Alternatively, if Thinwire mode is selected, the packets pass through the Thinwire
transceiver chip and BNC connector which connects via a "T" piece to the Thinwire cable.

The SIA w,c, Man.·he,ter coding. to encode transmitted data anJ decode received data. The SIA Jetect~
and synchronis;:~ with incoming data. and passes it on to the LANCE. The LANCE checks the destination
address. and, if it matches any of the module addresses. transfer, the data direct hy DMA into shared RAM.

The 68000 microprocessor controls the operation of the DESQA module, including initialisation of I/0 and
module self-test (implemented on powerup or initiated by host software).

1.4.3 Network Integrit:y Functions
The DESQA module provides the following features for network integrity:
•

Self-test diagnostic execution on powerup or after host software initialisation

•

Sanity timer to monitor host software
Controller looph;.ick
Maintenance Operaiion:, Protocol (MOP1 message~ for Remote Monitor Con~ok (!~MC: 0lJerations: Remote
BOOT. Request ID. Transmit System ID

•

Mai11h.:nance Opcraiions I'rotocol l~10PJ: datalink counters, maintained and stmed by DE.S(.)A

•

IEEE 802.2 f\1aintenance Messages for XID (Transmit ID) aml TEST on NULL L;Pk-layer Service Access
Points (LSAPsJ.

To as~i~t in fault diagno~i,- and network mana~ement, the DESQA cz.n abo operate in pro111i,cuous addressing
mode. Effectively. this di~rcgard~ the internai addr~ss filter logic. This allows the DESQ.\ :o .:ccept all pac\e!~
received from the network, and to verify the integrity of the received data by performing a 32-bit CRC check on
each received packet. All transmissions (normal,loopback. and Setup) reset the sanity timer without affecting its
status (e11abled or disabled).

l-20

INTRODUCTION

1.4.3.l Self-test Diagnostics
In Nonna) mode. the DESQA executes a comprehensive self-test on powerup. This takes approximately five
seconds to complete.

The finnware ROM on the DESQA contains 4 Kbytes of PDP- I I boot/diagnostic code. If the module is
controlled by a PDP host, the host can execute this code in order to increase fault coverage. This enables the
DESQA to determine that it is operating correctly. before it attempts to access the Ethernet.
1.4.3.2 Sanity Timer
The sanity timer acts as a check that the host software is operating effectively. If the host communications driver
fails to reset the timer periodically, the timer initiates a system reboot at the host.
All transmissions (normal. Joopback and setup). reset the sanity timer, without affecting it's status (enabled or
disenabled).
1.4.3.3 Controller Loopback Modes
In intemal loopback, the DESQA loops all ml.!~sages thru11gh the module. and tl1e host can neither ,end nor
receive Ethernet messa_.?es.

Internal loopback may be entered either by the host command (set CSR08) or at device powerup. The beha,·iour
of the device differs according to ib mode.
•

•

In Normal mode. the characteristics of internal loopback depend upon how loopback was initiated.

From Host command. no Ethernet access is possible .

From device powerup. certain types of MOP messages may ht> processl·d by the DESQA (that i'.-. MOP
boot if enabled by S4. Ethernet loop channel. and Request System ID).

In DEQNA-lock mode. no Ethernet ac:cess is possible.

1.4.3.4 Remot<: Console Commands
When operating in Nonna! mode. the DESQA responds to the following MOP remote console commands:

•

System Identification Request from another Ethernet station. The DESQA sends the current System ID
parameters from shared RAM

•

System ID Transmission is sent periodically to a Multi-cast Ethernet address

•

Remote trigger command from another Ethernet station. The DESQA verifies the request. and then causes
thc host system to reboot by negating BDCOK on the Q-Bus interface in order to sirnulatc a pm,wup 1v,1art.

1.4.3.5 Ethernet Channel I.oopback
DEC:r)A rcr1-.gm~e' Ethernc'! l:wpb,1, k te'.,I rn:.-,cage~. The mululf' .. h.::cJ... t > dctcrmi,,e ,,. ltc-:hc IP fr,r\\ ai,' ,,;
return the incoming mes!->agc:. Mr~s.,ge~ are received. dccod.:ci. and rl'-tra1N11iued by DESQA indi:pcndenliy ol
host s.:>ftware. t,onnal mes:,ages are passed through as usual.

1-21

INTRODUCTION

Table 1-2

DESQA Bulkhead Thickwire D-Type Connections

Signal Name

Voltage common(+l2V return)

Voltage supply (+I 2V)

Voltage shield

Receive+

Receive -

Receive shield

Transmit shie!d

Transmit+
Transmit Control-In shield

Collision Presence +

Collision Presence -

Control-Out A

Control-Out B

Shell

Protective Ground (Conductive Shell)

1.5 SPECIFICATIONS
The DESQA module meets the Ethernet specification (Version 2.0) and is compatible with IEEE 802.3
Spedfication for Carrier Sense with Multiple Arcess ~·ith Collision Detection.
Table 1-3 gives the specifications of the DESQA module.

1-22

INTRODUCTION

Table 1-3

DESQA Specifications

Physical

Electrical

Q-Bus loads

lemperature

Dimension

Imperial

Metric

Height

12. 13 inches

30.8 cm

. Width

0.95 inches

2.4cm

Length

9.45 inches

24cm

Weight

20.3 ounces

0.58 kg

Voltage

Tolerance

Typical

Maximum

current

+5.0 V

±5%

2.15 A

'2.7 A

+12.0 V

±5'k

0.21 A

1.5 A

3.3

0.5

Environment

Specification

Storage

-40C(-40F)

Operation

5C(41F) to 50C(l22F)

to 66C(l 5 IF)\l

NOTE
BEFORE OPERATING with the DESQA module
you must give it a reasonable time to stabilise in an
environment within the operating range.
Airflow

Specification

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --···------ --··Airflow across the board must limit the outlet temperature to a maximum of
.5tlC(l22F). and the kmp::-ratwe rise a.:,o.-, th, b,ia,d IL' :,:ic:SL•:::
Under typical power dissipation. this can be achieved using a linear airflow of 1.2
meters/second.

NOTE

Do not subject any area of the board to a local
ambient temperature above 70CU:-8F) tinder any
environmental conditions.
Relatin HumiditJ

Environment

Specification

Storage

l07r to 95%. non-condensing

1-23

CHAPTER2
FUNCTIONAL DESCRIPTION

2.1 SCOPE
This chapter describes the main operations of the DESQA module, and its system pon interface with the Q-Bus.
The se::tions an· ;:i, 1·c11m, s:
Sec1ion 2.2 MODULE OPERATIONS
Section 2.3 SYSTEM PORT 11\TERFACE
Section 2.4 SWITCHES AND LEDs

2.:

MODliLE OPERATIONS
Th~· DESQA moduk transf..:n, d:1t,1 hetween buffers in ho~, memory and either the Thickwire Ethernet tran,,eiver
or the Thinv. ire Eth::met. The main operations are as follow,:

Transfer of data between host memory buffers and shared RAM in the DESQA.

Conversion of data and status information between host format and that used in the DESQA module.

Arbitration of access requests on the backpon bus.

Transfer of en.::apsulated d,11a packeb between shared RAM anC: the Ethernet connector.

DESQA module control.

Tht· daw is hrou~h: tc,i;ether at a higher level of protocol to fonn packeb of between 60 and l .'i 14 data byte,. The
DESQA 11i..Jdt1k· c ..dculates and appends a four byte CRC to transmit packets, and strips the Cl{C from receive
packets. Th..:refore, the full length of a packet on the Ethernet is between 64 and 1518 bytes.

2.2.1 Q-Bus Transfers
Tht: QiC is a du:u-poned device: one set 0f data and address lines is connected to tne Q-Bus: the othl.'r interface,
with the backport bus in the DESQA module. In the data DMA path. each port is double buffered, and each po:1
is controlled by sequencer logic in the QIC. Figure 2-1 shows the Q-Bus interface functions.
The QIC supports DMA hetween the Q-Bu~ and shared RAM:
1.

Block-mode or {non-block-mode) data DMA.

Non-block-mode control D\1A.

2-1

INTRODUCTIOJ\

Table 1-3 (Cont.)

DESQA Specifications

Relative Humidity

EnYironment

Specification

Operation

I 0% to 95%, non-condensing

Environment

Specification

Storage

Maximum: 12.l km (40,000 ft)

Operation

Maximum: 2.4 km (8,000 ft)

Altitude

NOTE
Derate the maximum operating temperature by
1C(l.8F) for each 1000 meters (3281 feet) of
altitude, unles~ constant cooling is 1>rovided.

l-24

FUNCTIONAL DESCRIPTION

These two types are described in the next sections.
2.2.1.1 Data DMA
The QIC can execute up to 16 words of block-mode OMA between Q-Bus system memory and shared RAM
each time it acquires control of the Q-Bus. The transfer must use either read only instructions, or write only
instructions.

When executing OMA transfers to block-mode memory, the QIC relinquishes the Q-Bus whenever:
1.

The transfer reaches a 16 word boundary.

Another device is requesting the Q-Bus when the transfer reaches a 7 word boundary. This causes the QIC
to relinquish the bus at the 8 word boundary.

2.2.1.2 Control DMA
The QIC can also handle up to four words of control OMA, using mixed reJd and write operations on the Q-Bu~
to access BOLs. This is known as control OMA; it is used to transfer status information as well as to access
descriptors, as follows:

Buffer Descriptor Fetch. This operation acquires the Q-Bus, executes one non-block-mode write and three
non-block-mode read instructions, then relinquishes the Q-Bus.

Store status. This operation acquires the backport bus, executes two non-block-mode write instructions, then
relinquishes the Q-Bus.

2.2.1.3 lit-on-block-mode DMA
When t!xecuting transfers to non-block-mode memory. the QIC relinquishes the Q-Bus whenever it reaches a
four-word boundary.
2.2. 1.4 Data and Status Conversion
The 68000 microprocessor handles:

Formatting of buffers for transmission.

Reformatting of packets received from the Ethernet.

Conversion of starns information for both translT'it and receive messages.

Figure 2-4 shows the data transfers involved in formatting the message data.
2.2.2 Backport Rus Arbitration
The Q-Bus Network Arbitration (QNA2) controls access to the backport bus on the DESQA module. arhitr&ting
between access requests from the QIC, the 68000 microprocessor, and the LANCE. The QNA2 provides all the
gating and the strobing signals necessary fN these devices to access th• .. shared RAM.

Figure 2-3 shows the control and gating signals that the QNA2 generates to control the backport bus.

2-2

--..,.

FUNCTIONAL DESCRIPTION

HOST MEMORY

RECEIVE PACKET
BUFFERS

OBUSINTERFACE
CONTROLLER
(QIC)

I-

- ...

DATA

DMA

I
I
I
I

TRANSMIT PACKET
BUFFERS

TRANSMIT
BUFFER DESCRIPTOR
LIST (BDL)

RECEIVE PACKET
DATA BUFFERS (FIFO)

I
I

I
I
I -CONTROL

DELQA MEMORY

J_ OMA
L -

TRANSMIT PACKET
DATA BUFFERS (FIFO)

CONTROL AND STATUS
REGISTER

VECTOR ADDRESS REGISTER

TRANSMIT BDL
START ADDRESS REGISTER

I - RECEIVEBDL

START ADDRESS REGISTER

STATION
ADDRESS
ROM
RECEIVE
BUFFER DESCRIPTOR
LIST (BDLl

Figure 2-1

Q-Bus Data Structures

2-3

~~:-,,~/W

FUNCTIONAL DESCRIPTIO!\'

DESQA
SERIAL INTERFACE
ADAPTER (SIA)

LOCAL AREA NETWORK CONTROLLER
FOR ETHERNET (LANCE)

TXCVR
(TRANSCEIVER)

ONA2
ROM

Cl)

:::,

Cl)

:::,
CX)

0
0

CX)

a::

>
u

a::
0
a..

I-

::.,:
L'

(.0

68000

CX)

RAM

C·BUS
INTERFACE
CONTROLLER
(QIC)

Q-BUS TRANSCEI ✓ ERS

/1_ _ _ _ _ __J~
~

HOST O-BUS

Figure 2-2

DESQA Backport Bus Structure

2-4

✓

FUNCTIOJl<iAL DESCRIPTIOS

---

HOLD
HLDA

LEN

LALE

LDIR

LAOE

LS646
(DATA)

LALE

LANCE

LREADY
LALE
LDAS

F373
(ADDRESS)

[

FiRMWARE ROM
ROMSEL

A16

•I

t---~

A15

SHARED RAM

l
I

I
68000

i - - - - - ; AS

r-----; MREQ

F244
(ADDRESS;

DTACK

~-~ IPL2

CPAOE

cs --

LS245
(DATA)

SA ROM

CPDOE CPDIR

SELSAR

-QIC

; - - - - . ~-1ACK

Figure 2-3

Backport Control Functions

2-5

..
,4----;

FUNCTIONAL DESCRIPTION

LOCAL AREA NETWORK
CONTROLLER FOR ETHERNET
(LANCE)
I

68000 MICROPROCESSOR

SHARED RAM

RECEIVE
DESCRIPTOR
RING
TRANSMIT

D::SCRIPTOR
RING

►

TRANSMIT PACKET
DATA BUFFERS

FORMATTING
MICROPROGRAM

STATUS
CONVERSION
MICROPROGRAM

RECEIVE PACKET
DATA BUFFERS

TRANSMIT BDL
START ADDRESS
REGISTER

RECEIVE BDL
START ADDRESS
REGISTER

L·----1

Q-BUS INTERFACE CONTROLLER
(QIC)

Figure 2-4

DESQA Data Path

2--6

I
I

FUNCTIONAL DESCRIPTION

2.2.3 Ethernet Transfers
Ethernet transfers are handled by the LANCE (Local Area Network Controller for Ethernet) in conjunction with
the SIA (Serial Interface Adapter).

2.2.3.1 Transmission
When the 68000 has translated a data frame into a packet suitable for transmission, the LANCE transfers it by
DMA from the shared RAM to the SIA. The SIA Manchester encodes the data, and sends the packet using either
the internal Thinwire Ethernet transceiver, or the external Thickwire Ethernet Transceiver.
2.2.4 Ethernet Transfers
Ethernet transfers are handled by the LANCE (Local Area Network Controller for Ethernet) in conjunction with
the SIA (Serial Interface Adapter).

2.2.4.l Transmission
When the 68000 has translated a Jata frame into a packet suitable for transmission, the LANCE transfers it by
DMA from the shared RAM to the SIA. The SIA Manchester encodes the data. and ~nds the packet using either
the internal Thinwire Ethernet transceiver, or the external Thickwire Ethernet Transceiver.

2.2.4.2 Rereption
When the SIA detects activity on the Ethernet, it synchronises with the preamble of the incoming message. The
SIA then decodes the data and transfors the packt:t to the LANCE. The LANCE filters the destination addrec;s. If
the aadress on the incoming packet matches one of the addresses in module memory, the LANCE transfers the
data by OMA to the shared RAM.

2.2.S Master Module Control
The 68000 microprocessor executes the master control program for the DESQA module. The master control
program is held as firmware in the ROM associated with the microprocessor on the 68000 bus, and executes the
following functions:

Conversion of control and status information.

Initialisation of QIC and LANCE on powerup.

DESQA self-rest on powerup or on initiation by host.

Interrupt control.

The QNA2 contains the CSR (Control and Status Register), and the DESQA IR (lntellllpt Register) for the
DESQA module.
2.3 SYSTEM PORT INTCRFACF.
The DESQA is accessed through twelve registers which are mapped into the Input/Output page of Q-Bus address
space in the host system. When it receives the vaiid address of one of the registers from the bus master. the
DESQA responds as a bus slave.

2-7

FUNCTIONAL DESCRIPTION

2.3.l Port Registers
The address mapping implemented by the QIC enables the host system to access the following internal registers
in the DESQA:

Control and Status Register (CSR).
This is a one-word. read/write register held in the QNA2.

Vector Address Register (VAR).
This is a one-word, read/write register held in the shared RAM.

Receive BDL Start Address Register.
Transmit BDL Start Address Register (BDL SARs).
These are two-word. write-only registers that are maintained by the host in shared RAM.

Station Address ROM.
This is a set of six read only memor) bytes (the lower bytes of the first six words in the DESQA space J.

All the registers are word addressable only. The 68000 microprocessor can access these registers directly from
the backport bus.
2.3.2 Master Module Control
The 68000 microprocessor executes the ma~ter control progr:im for the DESQA module. The master control
program is held as firmware in the ROM associated with the microprocessor on the 68000 bus, and executes the
following functions:

Conversion of control and statw, information.

Initialisation of QIC and LANCE on powerup.

DESQA self-test on powerup or initiated by host.

Interrupt control.

The QNA2 contains the CSR (Control and Status Register), and the DESQA IR (Interrupt Register) for the
DESQA module.

2.4 CONFlf;t_;RJ1\G THE DESQA !'\10DllLE
The DESQA can support either of two possib!e baseband Ethernet cabling systems, standard or Thinwm: Ft!il:m1:,
You set a jumf1er hlod.. 011 the module to mat.:h the cablmg system. The DESQA is shipped from the factory m
Thinwire cable mode.
The jumper block has three rows of pins (Figure 2-5).
To select Thinwire. :-ou cover the middle row of pins and the pins labelled Thinwire.
•

To select Thickwire. )OU ~-,l\·er ,he middle pins and the pins labelied fhid,wire.

You use a switchpack (Figure 2-5) to select the CSR address and other operating features of the DESQA. The
switchpack has five switches. SI through S5. Table 2-1 lists their functions. The DESQA is shipped from the
factory with all five switche~ closed.

2-8

FUNCTIONAL DESCRIPTIOS

JUMPER BLOCK
0

0
0
0
0
0
0
0

0 0
0. 0
0 0
0 0
0 0
0 0
0 0

0 0

FACTORY SETTING

....................
THINWIRE _J LTHICKWIRE

OPEN

□□□

r:::--,
□

0□

CJ
CJ

□
Al712l

Figure 2-5

DESQA-SA Module Layout

2-9

FUNCTIONAL DESCRIPTION

Table 2-1

DESQA Switches

Switch

Setting

Function

closed

Selects CSR address 17774440. (factory)

open

Selects CSR address 17774460. (for second DESQA)
Reserved.

S2
S3

closed

Selects normal mode. (factory)

open

Selects DEQNA lock mode.

closed. and S3 closed

Remote boot disabled. (factory)

open, and S3 closed

Remott' boot enabled.

open, and S3 open

Sanity timer automatically enabled at power-up.

closed, and S3 open

Sanity timer not. enabled at power-up.
Reserved.

The DESQA can operate in DEQNA lock mode or normal mode, which you select by using S3. Table 2-2 lists
the differences between DEQ~A lock mode and normal mode.
Note that S4 is an option switch. whose function depends on the position of S3. S4 enables a sanity tin,er that
monitors the host for inactivity. All transmissions (normal, loopback. or setup) reset the sanity timer without
affecting its status (enabled or disabled). If a hardware or software problem occurs. the timer reaches its limit.
causing the host to reboot itself. You should enable the sanity timer only for specific applications.

NOTE
If you enable the sanity timer in DEQNA mode and
download software or diagnostics, the sanity timer
ma~ time out before the !oar! is compk!e. This
time-out causes the system to reboot.

The DESQA imerrupt vector of 120 is written int,) a read/write rcgi~ter by software>. ll )O..; in'itali •. secf'nj
DESQA, its interrupt vector floats. with a rank of 47.

2-10

FUNCTIONAL DESCRIPJ'ION

Table 2-2

DESQA Mode Differences

Support

DEQNA
Lock
Mode

Normal
Mode

All DEQNA functions

yes

Maintenance operation protocol (MOP) functions
(including remote boot)

yes

Self-test suppon

yes

Boot/diagnostic code suppon

yes

Sanity timer

yes

2-11

CHAPTER3
PROGRAMMING
3.1 SCOPE
This chapter contains information about programming the DESQA module. The sections are as follows.

Section 3.2
Secuon 3.3
Secti-.>n 3.4
Section 3.5
Section 3.6
Section 3.7

OVERVIEW
REGIS1 ER DEFil'ilTIONS
HllFFER DESCRIPTOR DEFINITIONS
DATA TRANSFER
COSFJGURATION AND CONTROL
MAINTENANCE OPERATION PROTOCOL(MOP):

MODULE SUPPORT

3.2 OVERVIEW
The host software must provide routines to handle three hasic types of operation on the module.

•

Modl!le initialisation

•

Configuration and control operations (addressing capabilities loopback modes, and so on.)

•

Data transfer (transmit/receive) operations

This section provides the definitions and procedures which the host software uses to implement these three basic
types of operations with the DESQA.
As an introduction to these operations the following section provides an overview of the data transfer mech.mism
between the host and the DESQA.
Communication between the host anJ the DESQA is acc;:,mpli.,hed th,ou~I; buffrr ,je~.criptcr,; orga11i~,.d as li!,!
structure!- in host memory.
Thi::re is one de!,cr:ptor a!'-sC:;uteJ wi;h each data buffrr, and there ar..: separ,1Le de,cripto:- lists for tr-111;.mit and
receive. T_,._ BDL and Rx BDL.
The information in each descriptor includes:
•

The address of the data buffer

•

The length of the data buffer

•

Status information associated with the buffer.

The location of the descriptor lists is specified by the host writing the list address to the Tx BDL or Rx BDL 1/0
page register.
The transmit/receive protocol is described below.

3-1

PROGRAMMING

3.2.1 Transmit-Host to Ethernet Data Transmission
The host builds a list of one or more transmit descriptors, and then writes the address of the start of the list to the
OESQA Tx BOL register. Note that the host must always terminate the list with an invalid entry.
In response to the Tx BOL address register write, the OESQA talces the following action.

Bit 15 of the second descriptor word (the Valid bit) is examined to check that the descriptor is a valid one.
If it is invalid, the OESQA sets XL in the Control and Status Register (CSR), and talces no further action.

If the descriptor is valid, and the OESQA has a transmit data buffer available, then a data-OMA transaction
is performed to copy host data into the OESQA RAM, using the host buffer address and byte count supplied
in the descriptor.

The next host descriptor is read, and steps 2 and 3 are repeated. If the descriptor is invalid, then the OESQA
assumes it has reached the end of the list, sets XL in the CSR, and talces no further action.

When the packet has been transmitted on to the Ethernet, the OESQA writes the transmit status back to the
host using a control-OMA WW (write-write) operation.

The OESQA sets the XI-bit in the CSR and then interrupts the host to indicate completion of transmission.

The host should respond to this interrupt by reading the CSR to determine the reason for the interrupt. The host
should then clear the reason bit, by writing a l to it. See Figure 3-1.

3.2.2 Receive-Data Reception from Ethernet to Host
In order to receive any data from the Ethernet, the host must build a list of one or more receive descriptors. and
then write the address of the start of the list to the OESQA Rx BOL register. The host must alway~ terminate the
list with an invalid entry.
If the host wishes to receive packets for an address other than that in the SA ROM, then the host must specify
this address using a setup packet (see Section 3.6).
In response to an Rx BDL address register write, the OESQA does the following.
1.

Starting at the address provided by the host, the OESQA reads the descriptor into RAM (by performing a
Write Read Read Read (WRRR) control-OMA, where the Write operation is to set all the bits of word 1 to
I). All the bits of word I are reserved for the OESQA.

Bit 15 of the second descriptor word (the Valid bit) is examined to check that the descriptor is a valid one.
If it is invalid, the OESQA sets RL (Receive List Invalid) in the CSR, and takes no further action.

If the d°.scriptor is Yalid. and the DESQA has received an) packets from the network. then a rlata-DMA
transaction is performed to copy the packet from th.: DESQA RAM to tht: host. Data is c.:opied using the host
addrt>~s and byte count supplied in the descriptor.

The next host descriptm is reacl. and step,, :'. and 3 are r~peatcd. If the de~cript0r is in-.. .11id. tiler, die DESQ1\
assume~ it has reached the end of th.:: list, sets RL in CSR, and take~ no forthe1 actior,.

When the data-DM/. 0pcration to the host ha< completed. the DESQA writes the status associated with the
received packet back to the host using a control-OMA Writc-Wnte (WW) operation.

The DESQA sets the RI-bit in the CSR. and interrupt~ the host to indicate that J Tt'ceiH" ort:rnti0n ha~
completed.

3-2

PROGRAMMING

l
TIME

HOST_ _ _ _ _ _ _ _ _ _DELQA
TX BDL ADDRESS

FLAGWORD
DESCR.BITS.BUFF.ADDR.HI
BUFF.ADDR.LO

WRRR CONTROL - OMA
(TRANSMIT DESCRIPTOR)

BUFF. LENGTH
DATA

}0
0

STATUS WORD 1
STATUS WORD 2

DATA,DMA
DELQA TRANSMITS PACKET

WW CONTROL-OMA

HOST WRITES TX BDL ADDRESS TO DELOA

DELQA FETCHES HOST DESCRIPTOR (WRITE-READ-READ-READ CONTROL-OMA)

DELOA DMAs DATA BUFFER FROM HOST

DELOA TRANSMITS PACKET

DEL.QA WRITES TRANSMIT STATUS TO HOST (WRITE-WRITE CONTROL-OMA)

THE DELOA WILL CONTINUE TO FETCH AND PROCESS HOST DESCRIPTORS UNTIL
IT FINDS A DESCRIPTOR WITH THE VALID BIT CLEAR

Figure ~1

Transmit Sequence (No Chaining)

3-3

PROGRAMMING

3.3 REGISTER DEFINITIONS
3.3.1 Control and Status Transfers
This section describes how the host uses the DESQA's hardware registers.
3.3.2 Control and Status Registers
Each DESQA is assigned a block of eight word-locations in the Q-Bus 1/0 page. These locations are wordaddressable only, and the DESQA acts as a bus slave to support access by the host software to the DESQA
registers.
The accessible registers are:
•

Control and Status Register (CSR)
This is a one-word read/write control register.

•

Vector Address Register (VAR)
This is a one-word read/write control register.
Receive Ruffer Descriptor List (RDL) Start Address Register
Transmit Buffer Descriptor List (BDL) Start Address Register
These are two-word write-only registers that are maintained by the host software, and point to the Buffer
Descriptor Lists (BDLs) in host memory.

•

Station Address ROM
This is a set of six read-only memory hytes (the lower bytes of the first six words in the DESQA space).
The Station Address (SA) ROM contains the 48-bit physical address of the DESQA mcxlule in the Ethernet
LA~.

Four of the 1/0 pu;e addresses arc write-only data registers, used to pass the start addresses of the BDLs for
transmit and receive buffers. Two are read/write control registers.
The DESQA can act as bus master to the Q-Bus, in order to implement DMA transfers (either block-mode or
non-block-mode) between RAM on-board the DESQA and BDLs in host memory.
The registers are assigned to fixed blocks, so that more than one DESQA module can be mixed with other
DESQA or DEQNA modules in the same host configuration, as shown in Figure 3-2 (Host 1/0 Page ~vlap) and
listed in Table 3-1.
Table 3-1
St

DESQA Voit 110 Base i\ddre~ses
Base Address

l;nit

Module
---------

CLOSED

17774440

DESQA I

DESQA. DEQNA or OELQA

OPEN

17774460

DESQA 2

DESQA, DEQNA or DELQA

3.3.2.1 Control and Status Register (CSR) Definitions
The Control and Status Register tCSR) is a read/write register that contains control and si.atus information for the
DESQA.
Figure 3-3 shows the CSR bits, and Table 3-2 summarises the bit definitions in Normal mode. More complete bit
definitions follow this table.

PROGRAMMING

OCTAL
ADDRESS

READ REGISTERS

WRITE REGISTERS

CONTROL AND STATUS REGISTER

VECTOR ADDRESS REGISTER

BASE+ 16
BASE+ 14
STATION
ADDRESS

TRANSMIT BDL
START ADDRESS REGISTER

BASE+ 12
STATION
ADDRESS
BASE+ 10
STATION
ADDRESS

RECEIVE BDL
START ADDRESS REGISTER

BASE+ 06
STATION
ADDRESS
··;.,._

BASE+ 04
STATION
ADDRESS
BASE+ 02
STATION
ADDRESS
BASE+ 00
RE1HE

Figure 3-2

Host 1/0 Pa~e Map

II II II I II II II II II

f;E~D/WRITE)
RE168?

Figure 3-3

Control and Statu<; Register (CSR)

3-5

PROGRAMMING

Table 3-2

Control and Status Register (CSR) Normal Mode Usage

Bit

CSROO

Description

State after
Software Reset
or Self-Test

State after Power-Up Reset

R/W

Receiver Enable

0 (Clear)

0 (Clear) RE

CSR0l

R/W

Software Reset

0 (Clear)

0 (Clear) SR

CSR02

Nonexistent-Memory
Timeout Interrupt

0 (Clear)

0 (Clear) NXM

CSR03

R/W

Boot/Diagnostic
ROM Load

0 (Clear)

0 (Clear) BD

CSR04

Transmit List
Invalid/Empty

I (Set)

I (Set) XL

CSR05

Receive List
Invalid/Empty

I (Set)

I (Set) RL

CSR%

R/W

Interrupt Enable

0 (Clear)

0 (Clear) IE

CSR07

R/Wl

Transmit Interrupt
Request

0 (Clear)

0 (Clear) XI

CSR08

R/W **

Internal Loopb.;.ck

0 (Clear)

0 (Clear) IL

CSR09

R/W

External Loopback

0 (Clear)

0 (Clear) EL

CSRIO

R/W

Sanity Timer Enable

0 (Clear)

0 (Clear) SE

CSRll

Reserved: set to zero

0 (Clear)

CSR12

Ethernet Transceiver
Power OK

No change

CSR13

Carrier from Receiver
Enabled

0 (Clear)

0 (Clear) CA
. -- -

--------

~ey:

R-Read-only
W-Write-only
R/W-Read or Write
R/\':i--Read or Wnte-one-to-dear (writing zero ha, tll> effecti
**- ·.'""cti,c lo>'
rr-Reserved bit with no access defined

3--6

----~ ----------·-· - - - · - -

PROGRAMMING

Table 3-2 (Cont.) Control and Status Register (CSR) Normal Mode Usage

Bit

Description

State after
Software Reset
or Self-Test

State after Power-Up Reset

NOTE
If Thickwire mode is selected then a short circuit
on the Thickwire Ethernet cable can be detected by
CSR bit 13. If, however, Thinwire mode is selected,
it will not be possible to detect a short circuit on the
Thinwire Ethernet.
CSR14

Parity Error in
Memory

0 (Clear)

0 (Clear) PE

CSRI5

R/Wl

Receive Interrup!
Request

0 (Clear)

0 (Clear) RI

Key:

R-Read-only
W-Write-only
R/W--Read or Write
Rf\\'J-Read or Write-one-to-clear (writing zero has no effect)
**-Active low
rr-Reserved l;it with no access defined

The CSR bits are used as follows.
(CSROO)

Receiver Enable (RE)

Read/Write

When set: Enables the host to receive datagrams from the DESQA.
When cleared: Disables recl!ption of datagrams from the DESQA.
Reset: Both software reset (CSRQI) and power-up n::,d clear CSRG0 and disable datagram rt:ceptinn.
Thie bit is sel or cleared by the host only.

3-7

PROGRAMMING

NOTE.I
The DESQA may still be active for up to lOOps
after the clearing of the software reset bit.

NOTE.2
Setting this bit does not reset the device. It must be
first set then immediately cleared. See Section 3.6.3

PROGRAMMING

(CSROI)

Software Reset (SR)

Read/Write

When first set, and tht:n cleared: The DESQA initiates a software reset.
This bit is set or cleared by the host only.

(CSR02)

Nonexistent-MemOQ' Timeout (NXM)

Read-only

When set: CSR02 is set if the DESQA times out while trying to access host memory.
When reset: Software reset and power-up reset clear CSR02.
This bit is set by the DESQA only, and cleared by the host. Note that the host must write a l to
CSR07 in order to clear this bit.

(CSR031

Boot/Diagnostic 1<01\1 Load (BD) (PDP-11 only)

Read/Write

When set and then cleared: The DESQA copies the boot/diagnostic code from its on-board BID
ROM across to 4K words of receive packet buffers in the host. The host should wait 150 milliseconds
before clearing CSR03. and a funher 150 milliseconds after that before executing the BID code.
The host must h:n .:- a PDP- I I CPL and the appropriate boot ROM. and the host software must foliow
the co1Tect st>quence of commands both before and after BD load; this includes clearing CSROO
(disable ri:cepttonJ. See ~ection 3.6. Configuration and Control Procedures, for more details.
Reset: Both software r~~et (CSR0I) and power-up reset clear CSR03.
This bit is set or cleared by the host only.

(CSR04)

Transmit List lnrnlid/Empt~· (XL)

Read-only

When set: The DESQA sets this bit to indicate to the host that it has encountered an invalid transmit
descriptor (a transmit descriptor with the Valid bit clear). <The DESQA alw2ys interpret, an invalid
Jt,-,cni:,tv:· a:, marking tlie eud ot a ii!>i.)

When ciear: Thi, bit i, cleared bv the action of th<' host writing the high-order word of tht' trausmit
buffer dc,-criptor list address to the Tx BDL 1/0 page register. This event indicates to the DESQA
that the !Joq ha~ a list of tr:msmit descriptors that it wishes tu be processed.

Reset: D::ith software reset and power-up reset cause the DESQA to set mi-- hit (that i~. !h•· b,t i-.
con,,ide1cd 111vaiiJ on res.:-tJ.
This bit is always set by the host (by writing the Rx BDL address), and cleared by the DESQA.

3-9

PROGRAMMING

(CSROS)

Receive List Invalid/Empty (BL)

Read-only

When set: The DESQA sets this bit to indicate to the host that it has encountered an invalid receive
descriptor (a receive descriptor with the Valid bit clear). (The DESQA always interprets an invalid
descriptor as marking the end of a list.)
The DESQA also sets this bit if it detects an NXM timeout, see CSR02.
When clear: This bit is cleared by the action of the host writing the high-order word of the receive
buffer descriptor list address to the Rx BDL 1/0 page register. This event indicates to the DESQA
that the host has a list of receive buffers into which the DESQA may deliver packets.
Reset: Both software reset and power-up reset cause the DESQA to set this bit (that is, the list is
considered invalid on reset).
This bit is always set by the host (by writing the Tx BDL address), and cleared by the DESQA.

(CSR06)

Interrupt Enable (IE)

Read/Write

When set: This bit is set by the host _to enable the DESQA to generate interrupts. Interrupts are
generated under the following conditions.
1.

The DESQA has completed a transmit operation

The DESQA has completed a receive operation.

The DESQA has detected an NXM timeout.

The host should read the CSR to determine the reason 1ur the interrupt (XI. RI. NI):
When clear: Interrupts to the host are disabled. (Interrupt bits XI. RI NI may still get set, but no
interrupts will be generated).
When reset: This bit is set or cleared by the host only.

(CSR07)

Read/W r!te-Onl'.-Tu •C It ·u-

Transmit lnte1 cupt !"~e-1uest (Xil

\\'hH, S<'t: 1:-:di~.-i;(:' tlnt t! 1 e DESQA h:i~ tr,lll~miHec at lea,;t on." pad,.et. and 11:1, writtcr; tlie tr·,n<m;:
s11tw, to tht: statu~ woni-- of the cunespondmg buffer descriptor(s) in host memor). It C~R.06 i" also

set. the DESQA will issue ;m interrupt to the host.
When reset: This hit is set by the DESQA and cleared by the host. Not,:, that the host mu~t write a
l to CSR07 in order to clear it.

3-10

PROGRAMMING

(CSR08)

Internal Loopback (IL)

Read/Write

(CSR09)

External Loopback (EL)

Read/Write

These bits are used to select the various DESQA loopback modes, but also have cenain other
functions.
Loopback modes:
CSR08

CSR09

Loopback Mode

Internal

Internal Extended

External

Note that CSROO must be cleared for all loopback modes
Other functions:
CSR03

CSR08

0
0

CSR09

Function

Non-loopback operation

Read SA ROM checksum

BID ROM Load

Where X = don't care

When reset: the host may set or clear both CSR08 and CSR09.

(CSRIO)

Rea:1/Write

Sanity Timer Enable

When set: The DESQA will enable the sanity timer after the host has transmitted the next setup
packet. (Note that the setup packet is used to define the timeout period - see Section '.\.6.<, for
details). Once the sanity timer is enabled. any transmit a..::tivity by the ho,-,t. sLch a~ datarrain
transmission. setup packet transmission, or loopback packets will reset the timeout coun:er.

3-11

PROGRAMMING

When cleared: The DESQA will disable the sanity timer after the host has transmitted the next setup
packet.

NOTE
Setting or clearing this bit by itself has _
no effect on the operation of the sanity
timer. The host must remember to use
the combination of CSRlO and setup
packets to manage the sanity timer. The
sanity timer will only be enabled or
disabled based on the state of CSRIO
after a setup packet is transmitted by the
host.

When Reset: Both software reset and power-up reset clear CSR IO and disable the sanity timer. Note,
however that power-up in DEQNA-lock mode, with switch S4 open on the DESQA module, will, by
itself, cause the sanity timer to be enabled with the default (four-minute) timeout period (no setup
packet is required).

(CSRU)

Reserved: set to zero

(CSR12)

Ethernet Transceiver Power (OK)

Read-only

When set: Power is reaching the bulkhead connector.

When cleared: Either the fuse on the bulkhead assembly has blown. or there is no power to the
bulkhead.
Reset: CSR] 2 is not affected by either software reset (CSROI) or power-up reset.

(CSR13)

Carrier from Receiver Enabled (CA)

Read-only

When set: In normal transmission or external loopback mode (CSR08 clear), CSRU mdicate!> that
the DESQA is receiving a carrier signal from the Ethernet.
When cirnred: There is no activity currently on the Ethernet. or internal or extended loopba~k mode
is selected tCSR08 set).
CSR 13 can be sampled to poll activity on the Ethernet.
Reset: Both ~oftware reset <CSROI) and power-up reset clear CSR13. because they set internal
loopba..:-k mode (CSR08).

(CSR14)

Read-only

Parity Error in Host Memory (PE)

When set: Q-bus parity error during access to the host memory. Tiris error is fatal, and the DESQA
halts operation.

3-12

PROGRAMMING

When cleared: Parity in the last host memory access was normal.
Reset: Both software reset (CSROl) and power-up reset clear CSRI4.
In DEQNA-lock mode, CSR 14 is reserved

(CSRlS)

Receive Interrupt Request (RI)

Read/Write-one-to-clear

When set: Indicates that the DESQA has delivered at least one packet to host memory, and has
written receive status to the status words of the corresponding buffer descriptor(s). If CSR06 is also
set, the DESQA will issue an interrupt to the host.
When reset: Both software reset and power-up reset clear CSRI4.

This°bit is set by the DESQA and cleared by the host. Note that the host must write a I to CSR15 in
order to clear it.
3.~ 3 Vector Addresses
3.3.3.1 Vector Address Register (VAR) Definitions
The Vector Address Register (VAR) is a read/write register. The host system initialises VAR<09:02> with the
address of the vector to the DESQA interrupt service routine. In Normal mode, VAR<l5:10> are used for extra
control and status information. In DEQNA-lock mode, only VAROO is used for extra status information.

NOTE
The host software ,;hould disithle interrupts (by
clearing CSR06 or issuing a software reset) before
writing to the Vector Address Register (\'Ak). Use a
read/modify/write sequence to amend the VAR, and
only attempt one operation (change vector; change
mode; request self-test) at a time.

Figure 3-4 shows the VAR bits, and Table 3-3 summarises the bit definitions for Normal mode operations. More
complete bit definition!-> follow the table.
15

l____

j MS o~ 1-_R_s__._l_s_3_.l_s_2_T....._s_1....

,N_T_E_R_Ru_P_T_v_E_c_T_o_R_ _ _ _
f _R__R_l_1o]_

VAR
(READ/WRITE)
A[16BS

Figure 3-4

Vector Address Register (VAR)

3-13

PROGRAMMING

Table ~3

Vector Address Register (VAR)

Description

After
Power-Up
Reset

Software
Reset

Self test

R/W

Identity Test Bit

0 (Clear)

No change

Reserved

VAR<09:02>

R/W

Interrupt Vector

Undefined

No change

VAR<l2:10>

Self-Test Status

I (Set)

No change

Result

VAR13

R/W

Request Self-Test

I (Set)

Clear

VAR14

Option Switch (S4)
Setting

Reflect S4

No change

VARl5

R/W

Mode Select

Reflect S3

No change

Normal
Bit

Mode
Access

VAROO
VAR0I

Key:
R-Rcad-only
W-Write-only
R/W-Read or Writ~
rr-Re~ervcd bit with no access defined

• 3-14

PROGRAMMING

(VAR
<12:10>}

Self-Test Status (Normal mode only)

Read-only

VAR<12:IO> always indicate the latest status of the module self-test.
VARI2

VARI I

VARIO

Meaning
ROM CRC test

68000 test

0
0

RAM test

QIC test
QNA2 test

0
0

SA ROM test
LANCE test

·o

Self-test completed without error

The self-test can be initiated in Nonna! mode, by power-up reset, or by a host write to VAR bit 13
at1e1 the ~clf-te.,t completes.

In DI-.Q'.\A-lock mode V<\R<l2:10> always reads as zero.

(VAR13)

Request Self-Test (Normal mode only)

Read/Write

When set: The module is executing self-test.

Self-test takes approximately five secor.ds, and the contents of all the DESQA Q-bus registers should
be treated as invalid during the test, and for another five seconds afterwards. The registers should not

be written during this period.
When cleared: Tl1e sdf-test has ,.:unipkted, and VAR<l2:lC> irnli-:ah. wh..:'.lier th.: self-test
completed successfully or failed during a functional test. External loopback failures may be due
to an lll!ll•nnected transceivt:>r.All 0th..:r self-t~st failure~ shnuld be treated a·, fatal.
Reset: In '.\onnal mode. pnwer-up reset sets VAR13 to initiate the module self-test.
In DEQNA-lock mode. VARI3 always read~ as zeru. and cannot be set.

(\'AR14)

Option Switch Settiilg (Normal mode only)

Read-only

Immediately after power-up this bit may be used to determine the state of option switch S4.
When set: Option switch S4 is closed.
When cleared: Option switch S4 is open.

3-16

PROGRAMMING

The VAR bits record the DESQA status, as follows.

(VAROO)

Identity Test Bit

Read/Write

When set: VAROO provides an identity test to distinguish a DESQA module operating in DEQNAlock mode from a native-mode DEQNA module. To implement the test, the host software should:

Write VAROO=l

2. Immediately read VAROO
If VAROO=l, the module is a DESQA
If VAROO=O, the module is a DEQNA
3.

Write VAROO=O

When cleared: VAROO is ready for the identity test.
Reset: Power-up reset clears VAROO, but software reset (CSROl) has no effect on its value.

(VAROl)

Reserved

(VAR
<09:02>)

Interrupt Vector

Read/Write

In calculating the host interrupt vector address, the DESQA firmware read5 only VAR<09:02> and
assumes that VAR<Ol :00>=0.
Reset: Software reset (CSROl) has no effect on the interrupt vector, which is written directly by the
host software using the 1/0 port.
The interrupt vector is undefined after power-up reset, until a new value is written by the ho~t.

3-15

PROGRAMMING

Reset: Software reset (CSROl) has no effect on VAR14, but power-up resets VAR14 to reflect the
setting of option switch S4.
In DEQNA-lock mode. VAR14 is always zero.

(VAR15)

Mode Select (Normal mode only)

Read/Write

When set: If mode switch S3 is closed (for Normal mode}, VARI5=1 selects Normal mode.
When cleared: If mode switch S3 is closed (for Normal mode), VAR15=0 selects DEQNA-lock
mode and the DESQA clears VAR<l4:10> for DEQNA compatibility. Use of this setting is not
recommended.
Reset: Software reset (CSROl) has no effect on VAR15, but power-up reset resets VAR15 to reflect
the setting of mode switch S3.
In DEQNA-lock mode. (mode switch 3 open), VAR15 is always zero.

NOTE
Host software must delay for a minimum of 5
seconds after power-up before accessing device
registers. in order to allow self-test to complete.
3.3.4 BDL Start ,\ddress Registers (BDL SARs)
There are two sets of Start Address Registers for the Buffer Descriptor Lists (BDLs):
Tr:msmit BDL Start Addtess Register
•

Receive BDL Start Address Register.

Both registers are written by the host, and must be initialised with a word-~rite instruction. Reserved bits should
be written as zero. The low-order word address must be written first, followed by the high-order word address.
This is because the DESQA stans transfers as soon as it receives the high-order address.
To set up the transmit list for the first DESQA. write register 17774450 before register 17774452.
'fhc DESQA ,larh D\1A transfers of Ethernet packets :is soon as they me tiansferred to on-beard ~hared RAM
from the receiver. When the Transmit BDL Start Address Register is initialised, the module starts DMA transfer!>
of outgoing mes,:ige,- t0 shared RAM
3.3.5 Station Aodn.·!'s Registers 1.SA ROM 1
The lower bytes of each of the fin,t six register locations contain the default Ethernet physical address of the
DESQ/. modu?::.-. Th.: Lo:;1 ac.:es~,·,-; the 48-bit address by reading the registe, location.; in ascending or.:ier. The
host software is responsible for inserting the correct address in the source address field of each packet transmitted.
Two byte locations of the SA ROM inc.:lude the checksum of the Ethernet physical address. The checksum is
accessed by reading the first t\\ o bytes in reverse order, as follows.
Clear CSROO (Receiver Enable) to disable Ethernet reception.
Clear CSR08 (Internal LoopbackJ and ~et CSR09 (External Loopback) to put the DESQA into external
loopback mode.
3.

Read the lower byte of word I in the DESQA I/0 block.

3-17

PROGRAMMING

RESERVED

HIGH BITS

ADDRESS (LOW BITS)

I RR I
21

RESERVED

HIGH BITS

ADDRESS (LOW BITS)

II
RR

RE1689

Figure 3-5

BDL Start Address Regis1ers

Read th(.: lower byte of word O in the DESQA 1/0 block.

To clear external loopback mode:
Either set and then clear CSROI (Software Reset)
or write zero to EL (External Loopback).

3.4 HOST MEMORY DATA STRUCTURES
T,1is ;;ection describes how Buffer Des.:riptor Lists (BDLs) are used to organise transmit and receivt: L,uffcr£.
When initialised. the DESQA has direct access to the host memory. The host memory should be set up with
huffer !-pdLC allocated for rt:cci,e and transmit pad.els. ar..:l al,u for BDLs.
3.4.l Receive and Transmit Buffers
The DESQA transfers packet data to and from receive and transmit buffers in the host meml)r:r. A buffer can
contain an entire packet or part of a packet, but it cannot contain more than one packet.
The buffers that make up a TT'essage packet are referenced using a Huffer Descriptor List (BDU. Buffer~ co11tain
only data; the status of each buffer is maintained in its buffer descriptor. and the sequence of butt"e:-s in the
message is determined by the sequence of descriptors in the BDL. Only buffers that have the Valid bit set in their
buffer descriptor can be used by the DESQA. The last entry in the BDL should have its Valid bit (bit 15) cleared to indicate termination of the BDL.
T,ansinit buffers may start and end on byte boundaries, but this is not recommended. Receive buffers must start
and end on word boundaries. Word boundaries are recommended in both ca,;es for faster processing .

• 3-18

PROGRAMMING

3.4.2 Buffer Descriptor Lists (BDLs)
In the host database of BDLs there are two sections: the Transmit BDLs, and the Receive BDLs.
Each BDL is a forward-linked list of buffer descriptors. Contiguous descriptors are linked implicitly. Other
descriptors can be linked explicitly by writing a chain address in the BDL.
Each descriptor identifies a single buffer by its starting address and length. The descriptor also contains space for
the DESQA to supply status information associated with completed transmissions and receptions.
The host memory may contain as many BDLs as seems necessary, each referring to a set of buffers in memory.
To initiate transfers, the host software writes the start address of the next Transmit or Receive BDL to the
Transmit BDL or Receive BDL Start Register in the DESQA 1/0 page.

3-19

PROGRAMMING

Figure 3-6 shows the format of a buffer descriptor.

RESERVED
2

DESCRIPTOR BITS

HIGH ADDRESS BITS

LOW ORDER ADDRESS BITS
BUFFER SIZE

STATUS WORD 1

STATUS WORD 2

REll90

Figure 3-6

Buffer Descriptor Format

Each buffer descriptor in a BDL contains:
•

A reserved word: reserved for DESQA use on)_}'.

•

Descriptor bits that define the attributes of the buffer address: byte alignment; setup (optional); chaining
(optional).

•

Buffer address in the host memory.

•

Buffer size in words. given as the two's-complement. (The word count does not include the two CRC
words.)
The word count is alway~ given as the number of aligned words for DMA transfer. So a one- or two-byte
buffer has a word count of one, but a two-byte buffer that crosses a word boundary (that is starts on an odd
address). has a word count of two. Therefore, a buffer that starts and ends on an odd-byte boundary must
increase its word count by one.
The word count is taken from the byte count and the buffer alignment information in the H and L bits of the
buffer address de~criptor:
WORD C'Ol.iNT = (BYTE COUN r + H + L)/2

•

Two status words. The status words may be omitted only when a buffer descriptor is forward-linked
explicitly hy a chai11 address to another buffer.
When a complete packet has been transforred inlo or from the BDL. the DESQA +irmw:•re update!> the );.;st
pair of status word~ with a record of any errors in reception or tram,mission.

To allow for multiple lists of descriptors. and to allow the DESQA to chain lx:rween them. the buffer address
may be replaced by the start adJ,·c,s of another BDL. The chain bit in the descript'>r bits ;s s~1 to indicate this.
3.4.3 Buffer Descriptor Bit Definitions
The buffer descriptor format is shown in Figure 3-6 and described in the following paragraphs.

3-20

PROGRAMMING

3.4.3.1 Reserved Word

Table 3-4

Reserved Word

Bit

Definition

F<IS:00>

Reserved
Note: The DEQNA module sets all of the bits in the flag word to I "during" the processing of
a buffer descriptor. However, with DESQA ihe host software should not use these bits and their
transition as an indication of the state of the descriptor. The host software should use the buffer
descriptor status word I SI<IS:14> bits to determine the buffer descriptor completion status.

3.4.3.2 Address Descriptor Bits
The host uses these bits to define the attributes of the associated buffer.
Bit

Definition

V-\'alid
When set: This bit indicates that this descriptor contains valid information (see the table below).

C-Chain Address
When set: This bit indicates that the acdress contained in this descriptor is the add~ess of another
descriptor. This allows the DESQA to process multiple non-contiguous descriptor lists and
explicitly "chain" the lists. Note that contiguous descriptors are implicitly chained (see the table
below).

Valid and Chain bit combinations:
Valid

D15

Chain
D14

Descriptor Use

This is a valid descriptor.

This descriptor contains the address of another des<..iptor.

This is an invalid descriptor (end of BDL).
Rt:served

E-End of l\lessage (Transmit Ruffer Descriptor Only)
This bit provides a mechanism for the host to chain together a number of buffers into a single
packet.
When cleared: This bit indicates that the associated buffer does not contain a complete packet.

3-21

PROGRAMMING

Bit

Definition
When set: This bit indicates that this buffer contains the last segment of the packet. (The DESQA
will attempt to transmit the entire frame after this segment has been DMAd from the host).

S-Setup (Transmit Buffer Descriptor Only)
When set: This bit indicates that the buffer contains a list of DESQA Ethernet destination
addresses and control information.

11:08

Reserved

L-Low Byte Termination (Transmit Buffer Descriptor Only)
When set: This bit indicates that this buffer ends on a byte boundary instead of a word boundary.

H-High Byte Start (Transmit Buffer Only)
When set: This bit indicates that this buffer starts on a byte boundary instead of a word boundary.

NOTE
When the transmit word count is
1, and the buffer starts on a byte
boundary, the H bit must be set.
3.4.3.3 Buffer Address
The high- and low-order address bits are either the 22-bit address of the buffer associated with this descriptor. or
the address of another descriptor (see address descriptor bit 14. above).
3.4.3.4 Buffer Length (Word Count)
Buffer length is the two's complement value of the number of words in the buffer. The worcl count is always
measured in aligned words, transmit buffer misaligned is not reflected in the word count, instc::ad the H and l.
descriptor bits are used to denote this.

NOTE
It is not recommended that unaligned buffers be
chained together, as this can degrade performanc~.

·3-22

PROGRAMMING

3.4.3.5 Status Words
Upon completion of a transmit or receive operation, the DESQA will update the two status words at the end of
the buffer descriptor.
Status Word 1 bits 14 and 15 are used as a handshake between the DESQA and host. These bits are initialised
by the host, and are updated by the DESQA to indicate that it has completed processing this descriptor and
associated buffer. These bits should be initialised by the host as indicated below.

Table 3-5 Status Words
Bit

Definition

Transmit Status Word l

Lastnot See the table below.

Error or Used See the table below.
Lastnot

Chain

Re:.erved

Loss

Summary Status

Value initialised by the host.

This buffer has been used, b!.lt it is not the last segment of the pacl-..t>t· that
ii,, a chained buffer.

This buffer contains the last s·::gmeni of a packet, and has.been transmi!Led
with no errors.
This buffer contains the last segment of a packet, and has been transmitted
with errors.

When ~t: Indicates loss of carrier during transmission.

Reserved

NOTE
In the DEQNA. Bits 11 and 12 have different
functions for carrier status.

3-23

PROGRAMMING

Table 3-5 (Cont.)
Bit

Status Words

Definition
STE (Sanity Timer Enabled)
The state of this bit is only valid in DEQNA-lock mode.
When set: Indicates that the sanity timer was enabled via switch S4 at powerup.

Abort
When set: Indicates that the transmission was aborted due to excessive collisions.

Reserved

07:04

Count
The value in this field is an indication of the number of collisions that occurred before the
transmission att~1npt associated with this status word. The only possible values are:
012-

No collisions. or packet aborted after 16 collisions (see Abort)
One collision
Between two and fifteen collisions

Averaged over time, Count indicate!. the network loading.

03:00

Reserved

frirnsmit Status Word 2
15:10

Reserved

09:00

TDR

TDR count for Time Domain Reflectometry.

3-24

PROGRAMMING

Table 3-5 (Cont.) Status Words
Bit

Definition

Receive Status Word 1
15

Lastnot See the table below.

Error or Used See the table below.
15

Summary Status

Value initialised by the host.This buffer has been used, but it is not the last segment of the packet; that
is, a chained buffer.

0
0

This buffer contains the last segment of a packet, and has been transmitted
with no errors.
This buffer contains the last segment of a packet, and has been transmitted
with error)..

ESETUP

When set: lnJicates a setup packet. external loopback packet, or internal-extended ioopback
packet.

Reserved

Runt ,Internal Loopuack Failurcj

When set: Indicates that the internal ioopback operation was unsuccc~sful.

10:08

RBL

Received Byte Length bits 10 to 08. These bits are all set for a setup packet.

07:03

Reserved

3-25

PROGRAMMING

Table 3-5 (Cont.) Status Words
Bit

Definition

Frame
When set: Indicates a framing alignment error; that is, other than an integral number of bytes
were received. This bit is only set if there was also a CRC error. See bit 01.

CRCERR
When set: Indicates that a CRC error has been detected in the current packet. The DESQA
delivers all packets received with CRC errors.

OVF (Overflow)
When set: Indicates that at least one packet has been discarded between the current and previous
packet.

Receive Status Word 2
15:08

RBL<07:00>
Receive Byte Length bits 07 to 00, duplicated from the lower byte.

07:00

RBL<07:00>
Receive Byti:- Lengtn bit~ 07 to 00. These hits ano Receive Statm, Word l bits I O:OE (see abm el
form RBL<I0:00>, the number of bytes transferred by the DESQA into the host receive buffer,
less 60. Host software must add 60 to this value to get the length in bytes of the recci\'ed packet.
excluding the CRC (not transferred).
Packet Length (bytes)= RBL<I0:00> + 60
In the case of setup packets, and all types of loopback pa.:kcts. the host need not add 60 to get the
correct packet length.

• 3-26

PROGRAMMING

3.5 DATA TRANSFER PROCEDURES
This section describes how the host software controls transmission and reception.
Data transfers are handled automatically by the DESQA, using data OMA. The host· software controls
transmissions by initialising and clearing buffer areas and associated control registers.

3.5.1 Transmit Packet
The host initiates transmission by first setting up a Transmit BDL, and then writing its address to the Transmit
BDL Start Address register in the DESQA module.
The transmit buffers should be set up before attempting to set up the Transmit BDL. A transmit buffer can be up
to 1514 bytes in length; this is the maximum number of bytes allowed in an Ethernet packet, excluding the fqur
CRC bytes.
To complete the transmission, the DESQA executes the following steps.
I.

Read the descriptor bits. and act on the buffer descriptor information as follows.

If the Valid bit is set, the DESQA accesses the start address and buffer length fields, reads the relevant
buffer, transfers the contents to its on-board shared RAM, updates the status words and continues to the next
descriptor.

If the Valid bit is clear, the DESQA marks the end of the current BDL. The DESQA ceases to access the
BDL and its associated buffers.

If th~ chain bit is set, the DESQA links to the BDL, via the start address indicated in the buffer address field.
and continues to the next descriptor.

If the End-of-Message bit 0<13> is set. the DESQA generates the preamble and CRC for the message.
and transmits the compiete message packet over the Ethernet. Then it updates the status words in tht: latest
buffer descriptor with the outcome of the transmission. (If CSR06 Interrupt Enable is set. thi> l)ESQA also
generates a transmit interrupt request to indicate that a message has been tran.;mined.)

To achieve acceptable transmission rates, the DESQA executes control DMA (to set up the next data DMA
transfer), data DMA, and data transmissions in parallel. The host software reads the status or contents of buffers
only after the DESQA has returned the transmission status to the status word bits.

3.5.2 Transmit Programming
The host software for packet transmission is responsible for the following actions.
I.

Establish .the location and contents of the transmit :nessafe buffers.

Initialise the start address and descriptor bits for each buffer descriptor in the Transmit BDL

Write all the data fields within the transmit packet, including destination address (6 bytes). ~ourct:: aJdre,, (6
bytes), type field (2 bytes). and data (between 46 and 1500 bytes).
The DESQA hardware supplies the CRC automatically.

Clear the Valid bit in the last descriptor of the BDL.

Set the Valid bit in all the previous descriptors of the BDL.

Write the start address of the BDL to the BDL Start Address register on-board the DESQ.<\, to initiate
transmissions.

The host software should also provide an interrupt service routine to:
•

Check the status and availability of transmit buffers

•

Check CSR04 (Transmit List Invalid) to ensure that previous list processing has completed

3-27

PROGRAMMING

DESTINATION ADDRESS (6 BYTES)

SOURCE ADDRESS (6 BYTES)

TYPE FIELD (2 BYTES)

DATA FIELD (BElWEEN 46 AND 1500 BYTES)

I
I

---------------------------------------~
Af16!1

1-·igure '3-7

Ethernet Packet Format

•

Check CSR02 (NXM) in case the interrupt was caused by a memory access error.

•

Write 1 to clear CSR07 (Transmit Interrupt Request), if the bit is set.

3.5.3 Transmission Errors
In status word l of the last BDL entry for the transmitted message, the following status bits in the transmit buffer
descriptor record tra,,<:mission errors.

3-28

PROGRAMMING

Sl<09>

Abort

Excess collisions: there have been more than 15 attempts to transmit this packet.
Check Sl<l2> in Transmit Status Word I in case the Ethernet circuit is faulty (see
below).
•

S1<12>

Loss

Loss of carrier during transmission, usually due to a short circuit on the Ethernet.
HQwever, Loss does not abort transmission, because it may be set during a normal
collision recovery.

The Time Domain Reflectometry (TOR) counter (S2<09:00>) is a IO MHz counter which is enabled by the
OESQA when a carrier signal is detected, and disabled when the carrier stops or a collision is detected. The
contents of the TOR counter are valid only when Abort (Sl<09>) is set, and may be used as a relative measure
of the distance through the network between the module and the supposed fault or collision.
3.5.4 Receive Packet
The host initiates· reception by first setting up a Receive BOL, and then writing its start address to the OESQA
module.
To complete the receive process in response to activity on the Ethernet, the OESQA executes the following steps.
1.

Read the descriptor bits, and act on the buffer status as follows.
•

If the Valid bit is cleared. it marks the end of the current BOL. The OESQA ceases to access the BOL
and its associated buffers.

•

If the Chain bit is 5,et. the DESQA links to the BOL whose start address is indicated in tht: buffer address
field, and continues from step 2.

•

If the Valid bit is set. the OESQA accesses the start address and buffer length fields, reads the next part
of the incoming message into the indicated buffer from its on-board shared RAM, and continues from
step 2.

If the message ends. the DESQA terminates reception. and updates the status words in the last buffer
descriptor used. (If CSR06 is set, the OESQA also generates a receive interrupt request to indii;:ate that a
message has been received.)

3.5.5 Receive Programming
Th" host software for packet reception is responsible for the- following rctions.
I.

b,tablish the- location and con:ents of the receive message buffers.
Sufficient receive. buffers shoulri be allocated for at least one p:•cket of the maximum expected length. in
t'nkr to em,ure that a receive interrupt request is generated before the next incomin~ message arriv.:s.

NOTE
No interrupt is generated if there are not
enough \'Slid receive butlers in the Receive BDL
to an.ommodate a complete packet.
2.

lnit1:1l:se the start address and descriptor bits for each buffer desciiptor in the Receive BOL.

Initialise Status Word 2 of all the descriptors in the Receive BOL with unequal high and low bytes. (1be
OESQA makes the high and low bytes both equal to the received byte length, to indicate when the receive
data is valid.)

Clear the Valid bit of the last BO in the BOL.Sct the Valid bit in all BOs in the BOL except the last BO.

Set the CSROO(Receiver Enabk) to enable Ethernet packet reception.

3-29

PROGRAMMING

Write the start address of the BDL to the BDL Start Address register on-board the DESQA, to initiate
reception.

The host software should provide an interrupt service routine to:
•

Check the status and availability of receive buffers

•

Check CSR05 (Receive List invalid) to ensure that previous list processing has completed.

•

Write 1 to clear CSR15 (Receive Interrupt Request) if this bit is set.

•

Check CSR02 (NXM) in case the interrupt was caused by a memory access error.

3.5.6 Receive Errors
In Status Word I of the last BDL entry for the received message, the following status bits in the receive buffer
descriptor record reception errors.
_
S 1<00>
OVF
Overflow: indicates that message data from the Ethernet has been lost between the
current and the previous message.

Sl<Ol>

CRCERR

CRC error: with the message truncated as a result. Affected packets are delivered, but
the datalink error counters are updated.

Sl<02>

Frame

Frame Alignment Error (some bytes incomplete): Frame is set only if CRCERR is set
also.

S1<12>

Discard

Discard packet.

Sl<13>

ESETUP

Looped Back Setup Mode packet or EL packet.

Receive Buffer Length, RBL<I0:00> is the number of bytes in the current received packet, excluding the CRC.
The value in RBL should be interpreted as follows.
•

For normal datagram reception, RBL is 60 bytes smaller than the actual number of bytes received.

•

For other loopback modes, RBL gives the correct value.

•

For all looped setup packets the RBL bits <10:08> equal 1. The lower byte of the RBL gives the correct
value.

• 3-30

PROGRAMMING

3.6 CONFIGURATION AND CONTROL PROCEDURES
This section describes the host programming procedures for bootstrap loading (PDP-11 only), for DESQA setup,
reset, and interrupt handling, and the sanity timer.
3.6.1 Boot/Diagnostic Load
NOTE
The on-board boot/diagnostic microcode is for use
with modules connected to PDP•ll systems only.

The boot/diagnostic (BD) ROM on-board the DESQA contains PDP-11 code that can be loaded into the host
memory and executed. This code is used for extended primary and DECnet bootstrap, and for the DESQA
citizenship test.
The PDP-11 boot/diagnostic code can be loaded across the Q-bus in either Nonnal or DEQNA-lock mode, but
the DESQA must be software reset before the boot/diagnostic c~e is loaded into the host memory.
All requests for this code from the DESQA must follow the correct sequence of commands. The operations listed
below are the exact sequence implemented in existing DEQNA suppon code for use with PDP- I I CPU/system
boot ROMs for CPU number KDJ-11/B. Timing values are indicated to be 150 milliseconds, but values as low
100 milliseconds should be acceptable.

The BD loading sequence is as follows.
1.

To reset the DESQA, set and then clear CSR0l. This software reset:
•

Disables Receiver Enable by clearing CSROO

•

Enables internal loopback mode by clearing CSR08 (IL).

Build two Receive descriptor buffers, each of 2K bytes.

Load the pointer into the Receive BDL Stan Address h!gister.

Write the octal pattern 1010 to the CSR to:
•

Disable the receiver (CSROO = 0)

•

Disable software reset (CSR0I =0)

•

Request boot/diagnostic ROM code (CSR03 = 1)

•

Disable interrupts (CSR06 =0)

•

Select internal extended loopback mode, by clearing IL (CSR08 ~ 0) and ~::.,tting EL (CSR(}l1 = l 1

•

Disable the sanity timer (CSRlO =0).

Wait 150 milliseconds

Clear CSR03 (Boot/Diagnostic ROM Load)

Wait 150 milliseconds

Execute the boot/diagnostic code from the Receive descriptor buffers.

When the DESQA boot/diagnostic code begins executing, it requests the on-board self-test. and waits for it to
complete before <:ontinuing. The DESQA aborts the self-test when the boot/diag11ostic sequence commences.
This is for compatibility with the DEQNA/PDP-11 system boot Roms which do not wait for the DESQA ROM
self-test to complete after power-up. In all cases, this sequence begins with a re9uired software reset.

3-31

PROGRAMMING

3.6.2 Setup
The setup packet is the only mechanism, other than the DESQA control registers (CSR and VAR), by which the
host software can send commands, status, and control functions to the DESQA module.

The setup packet can be used to initialise the following functions within the DESQA module.
•

Multi-cast address or promiscuous filtering for address recognition
Timeout value for the sanity timer

•

Up to 14 six-byte Ethernet addresses that the DESQA module is to recognise

•

MOP configuration and control

3.6.2.l Setup Packets
The setup packet is a special type of transmit packet. In setup mode, the transmit packet is not sent out on the
Ethernet. Instead. it is stored as control information within the DESQA module.
Setup mode is entered by setting bit 12 of the address descriptor in a transit BD.
The setup packet is looped around internally. and placed in a receive buffer for verification and synchronisation.
Reception of messages from the Ethernet is blocked until the loopback of the setup packet is complete.

NOTE
Ethernet reception is disabled during processing of
setup packets;their excessive use may significantly
affect performance.
3.6.2.2 Setup Information
The setup packet contains three main groups of info1111ation which the host software can issue to the DESQA.

Target address information contain~ the Ethernet physical and multi-cast addresses for which the DESQA
is to receive messages.

Control parameters specify special reception modes (such as promiscuous or all multi-cast) and sanity timer
timeout values.

MOP information is used to read and change MOP parameters.

Setup packets may contain either one or tv. o of the,e groups of infom1ation. A combination of the specified
length of the setup packet and tlie value of the tirst byte of the setup p.;cket buffer indicates v.hich groups of
iufom1ation are present.
Table 3-6 explain, all the possible combinaiions of information groups.
Table 3-6

Setup Packet: Information Group Combinations

Information Groups (Maximum 2)

Packet Length in Bytes
(Octal)

Target addresses only

177 or less

Target addresses and control parameters

200 to 377

Zero

Target addresses and MOP Element Blocks
(MEBs)

400 exactly

Non-zero

Value of Byte l

More than one setup packet may be issued. Each setup packet overwrites completely the setup area up to the 200
byte offset, but the MOP area between the 200 byte and 256 byte offset is overwritten only if the MOP flag is set

3-32

PROGRAMMING

at the start of the packet. Therefore. the only useful setup packet lengths are 177. between 200 and 377. or 400
(octal) bytes.
The host should maintain a copy of the current setup data, in order to recreate the correct 14 addresses (which
cannot be read back from the DESQA) whenever the setup information is modified, Since the DESQA can
only have two types of setup packet information per setup packet, the DESQA will accumulate all setup packet
information. unless respecified in a subsequent setup packet. Although setup packets may be repeatedly issued
to the DESQA to modify parameters or to read internal values (that is, counters, system id parameters), only one
setup packet should be outstanding to the DESQA at a time.
3.6.2.3 Setup Packet Buffer Descriptor
The DESQA recognises setup packets of between 200 (octal) and 377 (octal) bytes as indicating that control
information is present, as well as target addresses. The contents of the extra bytes between 200 (octal) offset and
377 (octal) offset can be arbitrary, because the control information itself is held in the buffer descriptor for the
setup packet.
In the buffer descriptor. the lower bits of the buffer word count are used to specify special address filter modes
(promiscuous or all multi-cast) for reception, and to reset the timeout value for the sanity timer.
Please refer to the equation in Section 3.4.2 in order to understand how the host specifies the descriptor's buffer
BYTE size from a combination of the Descriptor's Word Count Field (Transmit Descriptor Word 4) and the
Descriptor's Address Descriptor bits (Transmit Descriptor Word 2) 0<07> "L" bit and D<06> "H" bit.
•

Buffer size in bytes (byte count) =200 (octal)
Thi~ se1s D<06:()()> = 000000 (binary) which does not specify any control parameters in the size field of the
buffer.
Buffer size in bytes (byte count) = 201 (octal)
This seb D<OG:00> = 000001 (binary) which specifies that the DESQA should set All Multi-e:ast Enabled of
the setup packet control parameters.

3-33

PROGRAMMING

Table '3-7 Setup Packet Buffer Descriptor: Address Mode Bits
Bit

Meaning

Word 4: Buffer Word Count
C<OO>

All Multi-cast address filter
Enables DESQA recognition of any multi-cast address

C<Ol>

Promiscuous address filter
Enables recognition of any destination address

C<03:02>
C<06:04>

Sanity timer timeout value
Increases the timeout period of the sanity timer in factors of four.

Code

Timeout

000
001
010
01 I
100
IOI
110
111

0.25 seconds
1 second
4 seconds
16 seconds
I minute
4 minutes (default)
16 minute!>
64 minutes

C<l5:07>

Word count of the buffer (which contains the entire setup packet), given as the two's
complement.

C<I0:8>

All 1s for all setup packets

C<7:00>

Size of setup packet buffer if less than 200

C<7:0U>

= 0 if MOP specified in serup packet

3.6.2.4 St>tup Packet Format

Th-: fir~, p,,rt LI a :setup pad.et defines the E:.themtl addresses to which th: DESQA should r,~spt•nd.
Figure 3-8 shows the setup packet fo1mat in byte!. (octal). The columns are used to !'ho"" how the DCS(JA ,·:m
be programmed to recognise up to 14 six-byte Ethernet addresses. The low-order byte of the addres:s is at the top
of each column. The low-order bit of the low-ord<'r byte is the Multi-l:ast bit.
Each group of seven addres:s.!s is interleaved through 56 bytes of the setup packet. One of the addresse~ must
be the physical address of the DESQA module. Any other specified addresses are multi-ca!>l addresses. The
broadcast Ethernet addres~ (all ls) may be optionally enabled.
Any columns not used should be set to the physical address (for better protection against mischievous Ethernet
traffic). More than one physical address may be specified, but in Normal mode, only the first is used for receiving
datagrams, and as the source address for system ID messages generated by the DESQA. In DEQNA-lock mode
the specifications of multiple physical Ethernet addresses will cause the DESQA to filter all such physical
Ethernet addresses for packet reception.

3-34

PROGRAMMING

NOTE

Enabling more than one physical address is not
recommended under normal circumstances as this
may have a substantial impact on performance.
The MOP flag is located in the first byte of the setup packet (location 0). If the MOP flag is set to a non-zero
value by the host software. the DESQA expects to find MOP information at the end of the setup packet. between •
offset 200 (octal) and 400 (octal). The setup packet itself must be exactly 400 (octal) bytes long.
Refer to Section 3.7 for information about MOP programming.
Table 3-8 lists the effects of power-up reset, software reset, and self-test on the parameters of the setup packet.

3-35

PROGRAMMING

OCTAL
ADDRESS

BYTE OFFSET

400

-,- -,-1-T-,-,- -,-

+10 (OCTAL)

-1- J_ .J. _ J. _ L-L -1I
I
I
I
I
I
I
220
210

-,-7--,- - T - r - r 7 -

200

170

160
150

-~--

140
130

CX)

r.l)
(/)

(/)
(J)
LU

0::

0
0

110
100
070
060

I
I
I
0
I
I
0::
I 0::0
0
0
0
<! I <!
I
I
I

'<t

(J)
(J)
LU

(J)
(J)
u..,

(J)

(fJ

C/'J

(/':
(J)
LU

0::

0
<!

GROUP B
ETHERNET
TARGET
ADDRESSES

~
I
I

050

I
I N
I w
0
I 00
0
<!
I <

040

(J)
(/)

(/)

030

0::

020
010
FLAG

000

MOP ELEMENT
BLOCKS
(IF PRESENT)

'<t

(/)
(/)
LU

(J)
(/)

(/)
(J)

0::

"
<.

0
0

I
I
I
I "

(J)
(/)

I a:w
0
I 00
0
<!
I <
w

GROUP A
ETHERNET
TARGET
ADDRESSES

I
I
I

RESERVED BYTES SHOULD BE SE:T TO ZERO
RE1692

Figure 3-8

Setup Packet Format (Bytes)

3-36

PROGRAMMING

Table ~ Effects of Reset on Setup Packet Data
Setup Packet Data

Value After Power-Up
Reset or Self-Test

Value After Software Reset

Physical address

SA ROM address

NIA

Multi-cast addresses

Multi-cast disabled

NIA

Mode bit: All Multi-cast

Disabled

Mode bit: Promiscuous

Disabled

Mode bit: LED Value

LEDs set

NIA

Mode bit: Sanity timer

Reset to four minutes

NIA

MOP: Boot Password

Reset to zero default

NIA

MOP: Sys ID Data

Reset to defaults

NIA

MOP: Datalink counters

Counters cleared

NIA

3.6.3 Reset
The DESQA is reset during power-up, or by the host software using CSR0l (Software Reset). The module is
affected differently by ,hese two methods of reset.
Setting CSR0I (Software Reset) does not reset the DESQA hardware; imtead it causes the DESQA to enter tht:
DESQA reset state. The hLISL software may vc1ify that the DESQA is in the reset state by checking for a 10062
(octal) pattern in the CSR; this indicates that CSR<02,05,06,13> are set. The DESQA remains in the reset state
until the host software clears CSR0l (Software Reset).
In reset state, the DESQA supports:
•

Clear CSR0l (Software Reset) to exit the DESQA reset state

•

Load Vector Adriress Register (VAR)
If enabltd by option switch S4:

Either MOP remote boot
Or Sanit) timer timeouts.
Other attempt-, to write commands to the DESQA registers (such as setting interrupt enable, or loading
transmit/receive lists) are not supported. The host software must clear the software reset bit separately, before
writing other commands to the DESQA register~.
After CSR0I has been cleared. it take~ up to 10 milliseconds for the DESQA to complete the initialisatio;•
sequence.
Tables 3-2 and 3-3 summarise the effects of power-up reset, CSR0l (Software Reset), ano VARI3 (Self-Test) on
the Control and Status Register (CSR) and the Vector Address Register (VAR) respectively. Table 3-8 summarises
the effects on setup packet data.

3-37

PROGRAMMING

NOTE
The DESQA can remain active for up to lOOps after
the Software Reset bit is cleared.

3.6.4 Interrupt Handling
There are three interrupt conditions.
•

Receive Interrupt Request (CSR15), when a complete packet has been received.

•

Transmit Interrupt Request (CSR07), when a transmission is completed.

•

Nonexistent Memory (CSR02), when a Q-bus or memory 1lCcess error occurs. Setting CSR02 also sets
CSR07 (Transmit Interrupt Request).

These conditions generate an interrupt only if CSR06 (Interrupt Enable) is set.
Interrupts are not queued. If multiple messages are handled by the DESQA before the Interrupt Request bit is
cleared, there are no additional interrupts. The interrupt service should therefore scan the remaining descriptors
in the current BDL to determine whether any other messages have been received.
3.6.5 Loopback
All luopback modes loop a data packet back through the on-board Ethernet controller (LANCE) to be read back
into a Receive buffer.
There are four loopback modes, as follows.
•

Setup: The setup packet does not reach the Etht.>rnet, but it does pass through the LANCE before the
contents are uc.ed to set up arlcJress and control data in the DESQA module. CSROO (Rt..ceiver Enable) does
not affec1 this mode of loopback.
Setup mode is enabled by setting address descriptor bit D12 of the buffer descriptor for the setup data packet.

•

Internal: Internal loopback only supports packet lengths of six bytes. The data packet does not reach the
Ethernet, but it does pass through the LANCE on its way back to the host. The DESQA is initialised in this
mode as a failsafe feature.
Internal lo0pba..:k i!. selected by setti:1g CSR08 (IL) whc..n CSRCI (EL) and CSROO (Receiver Fr.ab!e) ..ire
clear.
Internal extended: Internal extended loopback mode can loopback all legal si1es of Ethernet packet. from
60 to 1514 bytes, excluding CRC. The data packet doe!> not reach the Eth..:rnct. IJut it doe~ :xi<;, tlm•t1gh tnl."
LANCE on it!, way back to the host.
Internal loopback is selected by setting CSR08 (IL) and CSR9 (EL) when CSROO (Receiver Enable) is clear.
External: Extended loopback exercises the Ethernet serial interface (SIA) as well a:-. the LANCE, and can
loophack all legal size~ of Ethernet packet. from 60 to 1514 bytes. excluding CRC.
A suitable external loopback connector must be connected either (as supplied) to thC' hulkhead assembly. or
to the end of the transceiver cable, for the loopback test to be executed. The test should be run using first
the minimum and then the maximum available Ethernet segment length.
External loopback is selected by setting CSR09 (EL) when CSR08 (IL) and CSROO (Receiver Enable) are
clear. As with CSR03 (Boot/Diagnostic ROM Load), the DESQA must be disabled and the on-boaro transmit
and receive buffers emptied before this function is inYoked.

• 3-38

PROGRAMMING

3.6.6 Sanity Timer
When DEQNA-lock mode is enabled by mode switch S3 set to open, the sanity timer is cleared and enabled
automatically on power-up if option switch S4 is open.
In either Normal or DEQNA-lock mode, the sanity timer is enabled when CSRlO is set and a setup packet is
issued. When cleared and a setup packet is issued, CSRlO both disables and resets the sanity timer.
All transmissions (normal, loopback, and setup) reset the sanity timer without affecting its status (enabled or
disabled). CSRlO is cleared at power-up reset and by CSROI (Software Reset). The default timeout period is
four minutes. Other limits between 0.25 seconds and 64 minutes can be programmed using a setup packet.
If the timer reaches its limit, BDCOK is negated on the Q-bus for approximately 3.6 microseconds, causing the
host to reboot itself.
3.7 MAINTENANCE OPERATIONS PROTOCOL (MOP): MODULE SUPPORT
This section describes how the host software can change the parameters that the DESQA uses when implementing
the Maintenance Operations Protocol (MOP) functions as part of DECnet network management functions.

In Normal mode the DESQA implements the following MOP functions in response to remote console messages
from other nodes on the Ethernet.
•

Respond to request system ID
Loopback reply to remote node

•

The J:?ESQA can initiate a host system reboot in response to a Trigger instruction message from a remote
console. This remote boot option must be selected explicitly by opening option switch S4 on the DESQA
board.

The DESQA also implements the following functions automatically and independently.
•

Transmit system ID every 8 to IO minutes.

•

Maintain and store datalink counters as a record of transfers and errors.

The host software can read and amend the MOP implementation parameters by including special MOP Element
Blocks (MEBs) in a setup packet.
The implementation of each of the MOP remote console functions and the format of the Ethernet messages are
described in Chapter 4. The rest of this section describes how to use the MOP elements in a setup packet.
For fu,ther information. refer to the DErnet Mainte!'. C'nce Operation ,nmrocol (MOP) Fu 1ctional Specification.
1

3-39

PROGRAMMING

----..,,

Table 3-9

MOP Functions

Element Type

Function

MOP Termination

Read Ethernet Address

Reset System ID

Read Last MOP Boot

Read Boot Password

Write Boot Password

Read System ID

Write System ID

Read Counters

Read/Clear Counters

3.7.1 Internal Loopback
In internal loopback, the DESQA loops all messages through the module, and the host can ndther send nor
receive Ethernet messages.
Internal loopback may be entered either by the host command (set CSR08) or at device power-up. The behaviour
of the device differs according to its mode.
•
•

•

In Normal mode, the characteristics of internal loopback depend on how loopback was initiated.
a.

From host command, no Ethernet access is possible.

From device power-up, certain types of MOP message may be processed by the DESQA (that is, MOP
boot if enabled by S4, Ethernet loop channel, and Request System ID).

In DEQNA-lock mode, ro Ethernet access is possible.

3.7.2 MOP Element Blocks (MEBs)
A MOP element is programmed by inserting a MOP Element Block (MEB) in a setup packet. Each MEB
specifies a single MOP function for the DESQA to perform, and refers in tum to a MEB buffer which details the
parameters for implementing the function.

NOTE
Although a given setup packet may contain from 0
to IO MEB elements, each MEB may appear only
once in a given setup packet. The terminating MEB
type field of zero must always be ~he last MEB

type. Omission of the terminating MEB type field
of zero will cause the setup packet to fail to be
properly processed. Although the DESQA loops
backs all setup packets and sets the ESETUP bit ir.
the receive descriptor of the looped setup packet, ff
no terminating MEB type field of zero is found the
DESQA will also set the Error or Used bit of the

PROGRAMMING

receive descriptor status word 1. The Error or Used
bit, in the receive descriptor status word 1 will also
be set if the buffer size specified for any MEB read
operation is too small. See Figure 3-10 for required
buffer sizes.
A MEB is fixed at six bytes in length and has the following fields.

Byte 1 - MEB Buffer Type field (indicates MOP function)
Bytes 2, 3, 4 - MEB Buffer Base (MEBB) Address
Bytes S, 6 - MEB Buffer Size
Although the format of each MEB buffer is specific to its type field, the following is true for all MEB buffers.
•

Word orientation is used in all MEB definitions.

•

Offsets from the MEB Base Address (MEBB) are defined in octal.

Figure 3-9 shows the relationship between the MEB in the setup packet and the corresponding MEB buffers.
Figure 3-JO shows the format of the MEBs for MOP element types 1 to 9; the start addresses refer back to the
MEB Base (MEBB) address shown in Figure 3-9.

3.7.3 MOP Element Type 0: MOP Termination
MOP element type O tenninates a list of MOP elements in the setup packet.

3.7.4 MOP Element Type 1: Read Ethernet Address
MOP element type l provides a mechanism for the host software to verify the current Ethernet physical .:1ddr<"S.:i.
This function pennits the host software to verify that the DESQA has correctly loaded the physical address
infonnation from the setup packet. (The default Station Address (SA) in the DESQA ROM is usually read
directly from the 1/0 port.)

Table 3-10 MOP Element Type I
Offset

Bits

Description

MEBB+0

PA<l5:00>

The low-order address bits <15:00> of the physical address. Written by the
DESQA for a read function.

MEBB+2

PA<31:16>

The rnid<l:e-orcier 16 ?.ddress bits of ~he physical address. W,·;tte!l by the
DESQA for a read fonction.

MEBB+4

PA<47:32>

The high-order 16 address bits of the physical address. Written by the DESQA
for a read function.

3-41

PROGRAMMING

GROUP A ETHERNET
TARGET ADDRESSES

GROUP B ETHEKNET
TARGET ADDRESSES

MOP ELEMENT BLOCK (MEB)
---------,MEBB+O
TYPE
BASE ADDRESS <07:00>

------MOP ELEMENT
__,

BASE ADDRESS <15:08>

______

MEB BUl=f=ER

BLOCKS /!\1 ~Bs)

BASE ADDRESS <21 : 1 6>
SIZE (IN BYTES) <07:00>

SIZE (IN BYTES) <15:08>
.__ _ _ _ _ ____, I\/IEBB+NN
◄
-----1

Figure 3-9

BYTE ------1►►

MOP Element Block Buffers in the Setup Packet

R£1893

PROGRAMMl~G

I REQUIRED MEBB SIZES (BYTES) (DECIMAL)
~

MEB8 OFFSETS (OCTAL)
07

PHYSICAL ADDRESS< 15:00>

MEBB + 0

PHYSICAL ADORESS<31: 16>

MEBB + 2

PHYSICAL AOORESS<47:32>

MEBB + 4

BOOTCODE<15:00>

MEBB +O

BOOT CODE <31:16>

MEBB + 2

BOOT CODE<47:32>

MEBB + 4

BOOT CODE <63:48>

MEBB + 6

MEBB + 2
MEBB + 4

INFO TYPE/LENGTH

MEBB + 6

INFO VALUE

MEBB + 10

INFO VALUE

MEBB+14-,.n

------------------------------------13

MEB
TYPES4.5.7
READ/WRITE/
RESTORE SYSTEM

MEBB-,. 12

INFO TYPE/LENGTH

READ/WRITE BOOT

MEBB +O

SYSTEM ID RECEIPT NUMBER

MEB
TYPES 2.3

SYSTEM ID CODE

256

MEB
TYPE 1
READ ETHERNET

MEBB + 0
MEBB + 2

DESTINATION ADDRESS (6 BYTES)

MCBB + 4
MEBB-,. 6
MEBB + 10

SOURCE ADDRF.SS r BYrES)

MEBB + 12
MEBB + 14

T{PE

CHARACTER COUNT

MEBB + 16

MEBB + 20

VERIFICATION 18 BYTES)

MEBB + 24

CODE

MEB
TYPE 7
READ LAS1 MOP
BOOT MESSAGE

MEBB + 22

100

MEBB + 26

C0,,7R0L CG'.):C

PROCESSOR

- MEBB • 30

SCFTvVARE ID

M[il6 - 32

MEBB • 34
MEBB., '.?6

PAD DATA (32 8YrES 1

MEBB-,. 74
CRC (4 BYTES)
MEBB + 76
15

O!'

ZERO

l.1EBB.,. 0

OPCODE (READ/CLEAR)

BASE AC''.:>'1ESS OF HOST BUFFER FOR COUNTERS< 15:01 >

ZERO

1<17:16>

MEBB + 4

MEBB + 6

LENGTH OF COUNTERS LIST

Figure 3-10

M€BB + 2

MOP Element Block Types 1 to 9
3-4~

MEB
TYPES 8.9
READ/CLEAR COUNT

• PROGRAMMING

3.7.5 MOP Element Type 2: Reset System ID
MOP element type 2 resets the system ID to the default parameters stored on-board the DESQA. This default is
then broadcast from the DESQA to the network automatically at power-up reset, and repeatedly at intervals until
a modification occurs from a MOP element 5 (Write System ID).
MEB Type 2 has only a type field, and no associated MEBB specification.

3.7.6 MOP Element Type 3: Read Last MOP Boot
MOP element type 3 obtains a copy of the MOP remote boot message which caused the last local host reset. The
only occasion when this function value returns a valid, non-zero MOP remote boot message is just following the
execution of a SYSTEM PROCESSOR remote boot. In the case of a COMMUNICATION PROCESSOR remote
boot, or a local power-up reset, this function returns a zero value.
3.7.7 MOP Element Types 4, 5: Read, Write Boot Pasn'ord
The MOP element types 4 and 5 enable the host software to reachmd write the MOP boot verification password.
This password is used only in Normal mode (mode switch S3-closed) with remote boot enabled (option switch
S4-open).
The boot password enables the DESQA to filter MOP remote boot messages. The default password is all Os,
which permits the DESQA to act on any MOP remote boot message.
The length of the password must be eight bytes.

Table 3-11

MOP Element Types 4, 5

Offset

Bits

Description

MEBB+0
MEBB+2
MEBB+4
MEBB•6

PW<l5:00>
PW<13:16>
PW<47:32>
PW<63:48>

Eight sequential bytes of the MOP remote boot password (least-significant
hex-digit first)

3.7.8 MOP Element Type 6, 7: Read/Write System ID
MOP Element types 6 and 7 enable the host software to read and write the MOP system ID message.
The buffer specified for READ must be at least 256 (decimal) bytes.
The other fields may be broken down into individual Info units:

OTHER I!\FO TYPE

OTHER INFO LENGTH

OTHER INFO VALUE

The order in whid1 Info units are arranged is not impo11ant. but Lhc variable sizing of th~ unit~ must he ob<.e-rved.
The overall size of the MEB in the setup packet dctcm1ines the numbt:r of Info elementl> spel·ificd.
Table 3-12 lists the Info types and Table 3-13 lists the Info value descriptions. For funher details. refer to the
Maintenance Operarions Protocol (MOP) Functional Specification.

3-44

---.,,.

PROGRAMMING

Table 3-12

MOP Element Types 6, 7

Offset

Bits

Description

MEBB+O

IT<l5:00>

Info type (binary value)
Type

Information

Termination of other information type list

Maintenance Version

Functions

Console User_

Reservation Timer

Console Command Size

Console Response Size

Hardware Address

System Time

100

Communication Device

101 to 199

Communication device related

200

Software ID

201 to 299

Software ID related

300

System Processor

301 to 399

System processor related

400

Data Link

401

Data Link Buffer Size

402 to 499

Data liuk related

Types I, 2, 8, and 100 are required fields; types 3, 4, 5, and 6 are required for
console messages.
MEBB+2

IL<07:00>

Info Length in bytes of Info Value field (binary value)

PROGRAMMING

Table 3-12 (Cont.)

MOP Element Types 6, 7

Offset

Bits

Description

MEBB+4
MEBB+6
MEBB+IO
MEBB+l2
MEBB+l4
MEBB+l6
MEBB+20
MEBB+22
MEBB+24

IV<lS:08>
IV<31:00>
IV<31:00>
IV<31:00>
IV<3l:00>
IV<3l:00>
IV<31:00>
IV<3l:00>
IV<07:00>

Info Value of
up to 16 bytes

Table 3-13 Information Value Descriptions
Type

Bytes

Description

001

Maintenance Version Number (binary)
Byte I Version number (lowest byte)
Byte 2 ECO
Byte 3 User ECO

002

Functinns
The bits indicate functions as follows.
0
I
2
3
4
5
6
7

003

Loop
Dump
Not supported by the DESQA
Multi-block loader (tertiary loader or system)
Boot
Console carrier
Data link counters
Console carrier reservation

Console User
The system address of the system that has the console reserved. The mandatory
field when tht' console carrier is av:.1ilahle (Functi,.m bit .5). Invalid if th~ console
camer i!> not reserved (Function bit 7).

004

Reservation Timer
The maximum value (in seconds) of the timer used to clear unused console
reservations. The mandatory field when the console carrier is available (Function bit
5).

005

Console Command Size
The maximum size of the conso)P. command buffer. The mandatory field when the
console carrier is available (Function bit 5) .

• 3-46

PROGRAMMING

Table 3-13 (ConL) Information Value Descriptions
Type

Bytes

Description

006

Console Response Size
The maximum size of the console response buffer. The mandatory field when the
console carrier is available (Function bit 5).

007

Hardware Address
An address in the SA ROM on the DESQA (read-only)

008

System Time
A segmented binary system time stamp.

Communication Device

100

The hardware device type of the host channel in use (decimal for the DESQA1. For
DESQA Info Type=37 (for DEQNA Info Type=5). (Read-only)
IOI to
199

16 (max)

Communication device related
Information specific to the particular communication device.

200

17 (max)

Software ID
The identificat10n of the software the sys1em i, ,npposed to be running.

201 to
299

16 (max)

Software ID related
Information specific to the particular software ID. Interpretation i!> specific to the
receiving system; for example, a file specification may vary depending on the type
of file server.
System Processor = t_ype

300

The type of system proces._or.
301 to
399

lo (max)

System processor related
Information !>pecific to the particular system processor.

400

Data Link
The data link JJrotocol; in this case. Ethernet.

401

Data Link Buffer Size
The size of the data link buffer.

3-l7

PROGRAMMING

Table ~13 (Cont.)

Information Value Descriptions

Type

Bytes

Description

402 to

16 (max)

Data link related

499
Information specific to the particular data link.
3.7.9 MOP Element Types 8, 9: Read, Read/Clear Counters
MOP element types 8 and 9 read the datalink counters which the DESQA maintains on-board in its shared RAM.
A MOP element type 8 does not affect the state of the DESQA counters; a MOP element type 9 clears the
counters after copying them to the MEB.
The buffer must be at least 100 (decimal) bytes long.
Counter values are unsigned integers. Counters latch at their maximum values to indicate overflow. For 16-bit
counters. the order of bytes is:
Lower 8 bits of counter
Higher 8 bits of counter

Byte 1 Byte 2 -

For 32-bit counters. the order of words is:

Word 1 Word 2 -

Lower 16 bits of counter
Higher 16 bits of counter

The DESQA counters are in the contigu01.:s format described in Table 3-14.

Table ~14
Count

MOP Elements Type 8, 9 MEBB Format
Specification
Seconds Since Last
Zeroed

16 bits in datalink counter

The number of seconds since the counters were last zeroed.
(Data) Bytes
RcceiveJ

32 bits in datalink counter

The total number of data bytes received error free, excluding the data link protocol overhead.
3

(Data) Bytes (Sent)
Tran-;mitted

32 bits in datalink coum-:r

The total numbe1 of data bytes ~uccessfully transmitted, excluding tl,e a,ta link protocol ovt:rhead,
and not counting data-link-generated retransmissions, but including transmissions in which the
collision test signal failed to set.
4

Packets (Frames)
Received

32 bits in datalink counter

The total number of datagrams received error free.
5

Packets (Frames
Sent) Transmitted

32 bits in datalink counter

3-48

--.....,

PROGRAMMING

Table 3-14 (Cont.)
Count

MOP Elements Type 8, 9 MEBB Format

Specification
The total number of datagrams successfully transmitted, including transmissions in which the collision
test signal failed to set.

Multi-cast Bytes
Received

32 bits in datalink counter

The total number of multi-cast data bytes received error free, excluding the data link protocol
overhead.

Multi-cast Packets
(Frames) Received

32 bits in datalink counter

The total number of multi-cast datagrams received error free.

Packets Transmitted:
(Initially) Deferred

32 bits in datalink counter

The total number of datagrams successfully transmitted on the first attempt after deferring. including
transmissions in which the collision test signal failed to set.

Packets Transmitted
(single collision):
2 Attempts

32 bits in datalink counter

The total number of datagrams successfully transmitted on tv,o attempts, including transmis:.ions in
v.hicJ, the collision test signal failed to set.
IO

Packets Transmitted
(multiple collisions):
3+ Attempts

32 bits in datalink counter

The total number of datagrams successfully transmitted on three or more attempts, including
transmissions in which the collision test signal faikd to set.
Transmit Packets
Aborted

16 bit, in <latalink counter

The total number of datagram.: aborted during tran!.mission for one or more of the bitmapped error:-..
12

Transmit Packets Aborted (Send Failure) Bitmap
Bit <00> RTRY

Excessive Collisions: Retry error after 16 un5uccessful transmission attempt~.

Bit <01> LCAR

Loss of Carrier (Carrier check failed): Retry error (after 16 unsuccessful
transmission attempt'i), loss of carrier flag, and non-zero TOR value on last
attempt.

Bit <02> = 0

Short Circuit (not supported on the DESQA).

Bit <03> = 0

Open Circuit (not supported on the DESQA).

Bit <04> MLEN

Data B!ock Too Long. The DESQA aborted the transmission because the
datagram exceeded the maximum packet size.

3-49

PROGRAMMING

Table 3-14 (Cont.) MOP Elements Type 8, 9 MEBI Fenaat
Count

Specification

Bit <05> LCOL

Remote Failure to defer: late collision on the last transmission attempt.

Bits <15:06> = 0

Undefined

Packets Received
with Error (Receive
Failure)

16 bits

The total number of datagrams received with one or more errors logged in the bitmap, including only
those datagrams that passed destination addre11 comparison.
14

Packets Received with Error (Receive Fahn Bitmap)
Bit <00> CRC

Block Check Error: a datagram failed the CRC check.

Bit <01> FRAM

Framing Error: a datagram failed the CRC check and did not contain an
integral multiple of eight bits.

Bit <02> MLEN

Message Length Error (Frame too long): a datagram was larger than 1518
bytes.

Bits <15:03> = 0

Undefined

Reserved for Host
Counter Word

16 bits

The host software for the DNA Network Management layer should maintain the DECnet MOP
counter for Unrecognised frame destination error. This indicates that a packet was received by the
DESQA, passed Ethernet destination address filtering. but failed Ethernet protocol type filtering. The
host software is responsible for Ethernet protocol type filtering.
16

Receive Packet Lost:
Internal Buffer Error
(Data Overrun)

16 bits

The tutal number of times that an incoming packet was discarded due to lack of ir,:emal buffer spa1.t..
Incoming packets must be error-free to be counted.
17

Receive Packet
Lost: Local Buffer
Error (System Buffer
Unavailable)

16 bits

The total number of times that there was a problem with a receive list data buffer. This counter is
incremented on one of more of the following occurrences.
Buffer Unavailable

A datagram was lost because there was no available buffer on the receive
list.

Buffer Too Small

A datagram was truncated because it was larger than the available buffer
space on the receive list.

3-50

CHAPTER4
TECHNICAL DESCRIPTION
4.1 SCOPE
This chapter describes how the components of the DESQA module work together on the backport bus. The
sections are as follows:

Section 4.2 ARCHITECTURE
Section 4.4 Q-BUS INTERFACE
Section 4.5 ETHERNET INTERFACE
Section 4.6 BACKPORT BUS
Section 4. 7 MODULE CONTROL

4.2

ARCHITECTURE

4.2.l Ovirview
The DESQA module is huilt around a backport bus which passes data between the QIC, shared RAM. and the
LANCE. A 68000 microprocessor handles formatting, module control, and initialisation.

The QIC handles the interface with the Q-Bus protocols, and the LANCE handles the interface with the Ethernet
protocols. Shared RAM is used as an intermediate buffer store.
•
The QNA2 arbitrates between the 68000, the lance and the QIC, for access to the backport bus. The QNA2
provides all the control signals for successful data transfer. The QNA2 contains the DESQA control and status
register (CSR) and internal i,•tenupt registe.-.
Firmware ROM contains both the master control program for the DESQA module and 4Kbytes of PDPI I boot/diagnostic code for the Q-Bus system. The firmware ROM can be addressed only by the 6i:iooo
:rncropnxessor.
The Station Address (SAJ ROM is preprogrammed with the 48-bit default physical address of the DESQA module
in the Ethe"met LAN.
Figure 4-1 shows the principal control signal paths through the DESQA module.

4-1

TECHNICAL DESCRIPTION

H4XXX

8392 POWER

SIA

I
FUSE

•

!RENA

LHOLD
LDAS
LREAD
READY
LHLDA

LANCE

-LEN
LADE

LDIR

LS646
(DATA)

i
FIRMWARE ROM

F373
(ADDRESS)

CPAOE
F244
(ADDRESS)

ROMSEL

14--14--i-i-I--+

t\DS
R/W
ADR22
68000
ADR23
IPL2
i - - A21TES

cs i . . SHARED
ROM

LS245
(DATA)

WE i - -

CPDOE CPDIR
♦

SA ROM
SELSARI--

AS
MREQ
~-1!\CK
, _ qD1tVR

F373
(ADDRESS)
QIC

I
QNA2

Figure 4-1

QNA2 Control Signals
4-2

,,.LEI•

PROGRAMMING

Table 3-14 (Cont.) MOP Elements Type 8, 9 MEBB Format
Count

Specification

Reserved for Host
Counter Word

16 bits

The host software should maintain the DECnet MOP counter for User Buffer unavailable. This
indicates that a packet was received by the DESQA, delivered to the device buffer pool in the host
memory, but discarded due to insufficient user-level receive buffers. The host software manages
user-level buffers.
19

Multi-cast Bytes
Transmitted

32 bits

The total number of multi-cast data bytes successfully transmitted, excluding data link protocol
overhead, and not counting the DESQA generated retransmissions, but including transmissions in
which the collision test signal failed to set.
20

Reserved

16 bits

Reserved

16 bits

Babble Counter

16 bits

Counter for the total number of times the DESQA LANCE reported the babble condition on the
ch:mnel.

3-51

TECHNICAL DESCRIPTION

4.2.2 Selection Switches
The DESQA has five manual selection switches: SI to S5. These are part of a switchpack on the DESQA board.

The mode switch defines two possible modes of operation for the DESQA. The preferred mode is the "Normal
mode" which indicates that the DESQA is operating as a DESQA. All current DIGITAL software for the
DEQNA may be used with confidence for the DESQA when the DESQA is switched to operate in Nonna! mode.
"DEQNA-lock mode" should only be required for use with some non-DIGITAL software drivers to achieve
compatibility with DEQNA programming features. The sanity timer enabling, on power-up. is controlled by the
option switch when the DESQA is operated in DEQNA-lock mode. The following table defines the functions
which may be selected through various combinations of S3 (mode switch) and S4 (option switch).

Table 4-1

Default Switch Settings (All Closed)

Switch

Position

Definition

Switch 1:

Closed

17774440 (Base Address)

Switch 2:

Closed

Reserved

Switch 3:

Closed

Normal mode

Switch 4:

Closed

MOP Remot<: Boot Disabled

Switch 5:

Closed

Reserved

4.3 CHECKING LED TEST PATTERNS
The DESQA module has a power-up self-test that includes an external loopback test. In order for _the extern; I
loopback test to pass, you must set up the DESQA as follows:

•

In Thinwire Ethernet mode: Connect a tee connector to the BNC connector on the DESQA handle.
Connect either two terminators or a valid Thinwire network to the tee connector.
In standard Ethf'rnet mode: Connect a D-type bophack connector. a H408() loophac~ -:nnnector. or a \·alid
Ethernet flelw'.)rk to the !5-pin D subminiaturc conn-.c:or on the D!:::~QA t-.anole.

The self-test is only available when the DESQA is in normal mode. The host operating system ~oftwan. .:an
reque,t the self-tec;t through the DESQA Q-Bc1s rf'gi,ter.

4-3

TECHNICAL DESCRIPTION

Table ~2

Power-Up LED Patterns

LED

Meaning

Normal Mode

•

•
•

Running the internal logic self-test.

The self-test is running an external loopback test.

•

Ready to run citizenship tests and/or normal functions, or run the module self-test.

DEQNA Mode

•

LEDs tum on and stay on .

• = on. o = off.

REMOTE BOOTS:
If a remote boot is initiated, make sure the LED
sequences in Table ~3 also appear.

Table 4-3

Remote Boot LED Patterns (Normal or DEQNA Mode)

--·---------------------------------------LED
1

Meaning

•

Running citizenship tests.

•

Internal loopback citizenship tests completed successfully.

External loopback citizenship tests completed successfully.

• = on.

-= off.

Confirm th.it all three LEDs are off, indicating that all citizenship tests completed ~uccessfully.

NOTE
If any LEDs remain flashing, an error has occurred.
Whether the DESQA is in normal mode or DEQNA mode. make sure all three LEDs turn on within 10 seconds.
indicating a successful power-up.

4-4

TECHNICAL DESCRIPTION

4.3.1 Clocks
The clock signals in the DESQA module run from a 40MHz oscillator located at the Ethernet end of the board.
The main clock signaJ is divided by two to produce two antiphase 20MHz clock signals. One of these is fed into
the XI input of the SIA, where it is used to generate the 10MHz Transmit Clock signal to the LANCE. The other
clock is fed to the QIC and the QNA2, so that these two chips can operate synchronously at 20MHz.
The QNA2, as bus controller, generates the 10MHz clock that drives the 68000 microprocessor.
Figure 4-2 shows the main clock signals, and the switchpack.

4-5

TECHNICAL DESCRIPTION

SERIAL INTERFACE
ADAPTER (SIA}

10MHz
LOCAL AREA

NETWORK
CONTROLLER FOR
ETHERNET (LANCE)
68000 MICROPROCESSOR

~-------~140 MHz

◄

DIVIDE
BY2
_

CPCLK

10MHz 20 MHz

-- CLK

CLK

0-BUS NETWORK
CONTROLLER (QNA2)

0-BUS INTERFACE
CONTROLLER (QIC)

UNITSEL 1

JMPR1

f
I

1 2 3 4 5

~~~ED ~~~Li~
SWITCHPACK

Figure 4-2

DESQA Clocks And the Main Selection Switches

·4-6

_CLOCK_

JMPR2
ja•

TECHNICAL DESCRIPTIOl'i

4.3.2 POWER LOADING

Table 4-4

DESQA and transceiver power requirements

Function

Typical
Voltage

Typical
Current

Maximum
Current

Backplane
Pins

TTL level

+ 5V +/-0.25V

2.15A +/-10%

2.7A

BVI, AA2, BA2

TTL ground
Transceiver
power

AJI, AMI, ATI BJI,
BMI, AC2, BC2

+12V +/-0.60V

0.21A

1.5A (Note )

BD2
BTI, CTI, CC2.

Transceiver
ground

DTI,DC2.

NOTE
At powerup, the surge current of the transceiver
can cause certain power supplies to current limit
or even to fail. These failures can also be caused
during powered-up connect. There is no surge
protection circuitry on the DESQA module.
However the +12V supply to the 15-pin O-Type
connector is limited by a SA pico fuse on the
module, and a handle mounted 1.5A/2.50V slo-blo
fuse. A fuse of the correct type must always be
fitted to the bulkhead module.

4.3.2.1 Fuses
A l.5A/250 slc-bJorn 1.25 inch ~y o.:5 iflch glass fm:e (orde, min;be,· 90-07211) pr:·•.:ct-; th..: tran;c:i\._1 and
its assl,ciat 1·d external wi: ing. The Fu,.,. may be rep!aced b) another fuse 0f the -;,1mc type. a Li11;cfo,c 1 ' 1 type
31301.5, a BEL FUSETM type 3SB 1.5. or an equivalent. The 1.25 inch (3.8cm) fuse holder (order number
I :-22?55-03 l is located in the DESQA bulkhead.

A 5.0 A/125 V :!,ia; kad pi..:o fuse (order number 12-05747-00) protect!> the DSSQA nwrltale and mtema1
wiring. The pico fuse i~ fitted on the DESQA board. It looks like a resistor and is ,,oldered in the same v.a).
It should be replaced only by trained personnel.

slo-blo is a Trademark of S.B. ruses
Littlefuse is a Trademark of Littlefuse Inc .. Illinois. USA
TM BEL FUSE is a Trademark of Belfuse Inc .. New Jersey, USA
TM

4-7

TECHNICAL DESCRIPTION

4.4

Q-BUS INTERFACE

4.4. l Overview
The QIC (Q-Bus Interface Controller) handles the Q-Bus interface protocols. To provide a complete Q-Bus
interface, four octal bus transceivers and two quad transceivers are connected between the Q-Bus and the QIC.
The QIC shares a 20MHz clock input with the QNA2.
The QIC provides complete Q-Bus slave control logic for host access to the OESQA 1/0 page registers.
On the Q-Bus side, the QIC supports control OMA and data OMA, using block-mode to achieve the highest
possible speeds. The QIC generates two control signals to change the direction of the DC021 transceivers:

DC012IN controls the direction of transfer of the three OC021 transceivers connected to the Q-Bus
data/address lines, BOAL<21 :0>.

TSACK (Transmit DMA Selection Acknowledge) controls the direction of transfer for the fourth DC02l
transceiver, which carries the bus control signals that enable the QIC to act as Q-Bus master for OMA.

On the backport side, the QIC supports OMA transfers to and from shared RAM along 16 data/address lines. The
QIC is controlled through a series of registers that are accessed by the 68000 microprocessor.
Figure 4-3 shows the Q-Eus interface. Table 4-5 summarises the signals and pinouts.

4-8

TECHNICAL DESCRIPTION

Q•BUS INTERFACE
CONTROLLER (QIC)

TRANSCEIVERS

Q-BUS

3X
DC021

BOAL.I\,

DAL
21:00

DATA

21:ooV

DAL
21:00

BIROS
BDMG'
DIR

.._

t
BIR06

DC021IN
TSACK

!
DIR

BDOUT
BOIN
BSYNC
BWTBT

1X
DC021

BIAK!

1/1 "--.7
~

ses7
-

BSACr-

co~

BUS
CONTROL
LINES

BDCOK
BINIT

BDMGO
BREF
BIAKu

14--·

2X
8641

-r-.."-1

·-

BDMR
BIR04
BRPLY

l
Rf.17~

Figure 4-3

Q-B,~s Interface (hardware)

4-9

TECHNICAL DESCRIPflON

----.,,,
Table 4-S

Q-Bus Connector Pins and Signals

Signal

Description

Signal

AAI

BIRQ5

Interrupt lines

AA2

+5V

ABI

BIRQ6

ACI

BDAL16 L

Data/Control

AC2

ADI

BDAL17 L

lines

AD2

AB2

AEI
AFI

AF2

BRPLY L

AHI

AH2

BOIN L

AJ2

BSYNC L

AKI

AK2

BWTBT L

ALI

AL2

BIRQ4 L

AM2

BIAI\.I L

AN2

BIAKO L

AP2

BBS7 L

AR2

BDMGI L

AS2

BDMGOL

AT2

BINIT L

.\lJ2

3DAT r L

GND

AMI

GND

ANI

BDMRL

API

BHALT L

ARI

BREFL

OMA Control

Q-Bus control

ASl
ATl

GND

FUSE H sink

AUi
AVI

AE2

GND

BDOUTL

AJI

Description

AV2

BDALIL
+5\"

BAI

BDCOK H

DC Power OK

BA:?

BBi

BPOK

Power OK

BB2

BCI

BDAL18 L

Data/Address line~

BC2

GND

BDI

BDAL19 L

BD2

+12V
(XCVR)

BEI

BDAL20 L

BE2

BDAL2 L

BFI

BDAL2l L

BF2

BDAL3 L

BH2

BDAL4 L

BHl

4-10

Bus Control lines

}

Interrupt !in-:,

-Bus Coutrol

OMA Control

Bus Control

Dat<• 'Addn.:ss l,ne~

Tram.c-eiver

Data/Add,ess lines

TECHNICAL DESCRIPTION

Table 4-S (Cont.)

Q-Bus Connector Pins and Signals

Signal

BJ2

BOALS L

BKI

BK2

BDAL6 L

BLI

BL2

BDAL7 L

BM2

BDAL8 L

BN2

BDAL9 L

BP2

BDALI0 L

BRI

BR2

BDALll L

BSI

BS2

BDAL12 L

BT2

BDAL13 L

BU2

BDAL14 L

BV2

BDAl.15 L

Signal

BJI

GND

Description

BMI

GND

BNI

BSACK L

OMA Control

BPI

BIRQ7 L

Interrupt

BTI

GND

......

(XCVR) Transceiver

BUI
BVI

+5V

CAI

CA2

CBI

CB2

CCI

CC2

GNDCXCVR1

CDI

CO2

+12V(XCVR)

CEI

CE2

CFI

CF2

CHI

CH2

CJI

GND(XCVR)

CJ2

CK!

CK2

CLI

CL2

CM!

GND(XCVR)

CM2

Ct-: I

CN2

CPI

CP2

CRI

CR2

CSI

CS2

CTI

GND(XCVR)

CT2

4-11

Description

Data/Address lines

TECHNICAL DESCRIPTION

Table 4-5 (Cont.) Q-Bus Connector Pins and Signals
Pin

Signal

Description

CUI

CU2

CVI

CV2

4-12

Signal

Description

TECHNICAL DESCRIPTION

Notes:
I.

(XCVR) indicates isolated power connections through the OESQA to the Ethernet transceiver cable
connector.

BC2 is tied to the ground plane of the module and serves as a pull-down sink through approximately 14K
Ohms for the Transceiver Connector signal FUSE H.

4.4.2 Initialisation
The QIC is reset from the Q-Bus when BDCOK is regated and BINITL is asserted. The assertion of BINITL
also causes a reset sequence to the remainder of the OESQA module. On the falling edge of RINITH a 200ns
pulse resets the QNA2 and a 150ms pulse resets the 68000 and the LANCE.

4.4.3 DMA Functions
The QIC can request, accept, and relinquish ownership of the Q-Bus, for both data OMA and control OMA
accesses to the host database.
There are separate addressing and buffering mechanisms for data OMA and control OMA. This allows control
DMA requests to take priority over data transfers in progress; when the control OMA is complete, the data
transfer is restarted from where it left off.

4.4.3.1 Data DMA
During data DMA transfers, the 21-bit Q-Bus address counter is connected to DAL<21:0l>, with DAL<OO> held
at 1ero. During a transfer. data transferred bdween the Q-Bus and the backport bus is double-buffcreci within :he
QIC. The 16-bit backpon address counter is connected to BPDAL<00,15:01> to support tran'ifcrs of up to 128
Kbytes.
Double buffering inside the QIC allows for the signal setup, hold and access times of Q-Bus and backport bus,
and for high speed, pipelined transfers through the chip.
If control DMA is attempted during data DMA, the QIC:

Relinquishes control of the Q-Bus

Requests control for a control DMA transfer (non-block-mode).

Completes the control DMA transfer. and relinquishes control of the bus.

Requests control of the bus in order to resume data DMA transfers.

The QIC recognises 16-word boundaries because there is no RREF (Refresh) from the bus slave. To change to
non-block mode, th<" QIC negates and re-asserts TSYNC (Synchronise).

4-13

TECHNICAL DESCRIPTION

4.4.3.2 Control DMA
During Control OMA transfers, the 21-bit Q-BUS address counter is connected to DAL<21:0l>, with DAL<OO>
held at zero.Control information is passed along a latched path through the QIC using single byte or single word
transfers.
This is the same path that is used when the host accesses the QIC as bus slave. If the host requests an 1/0 page
access at the same time as the 68000 requests a control OMA transfer, the host request takes priority.

ETHERNETINTERFACE

4~.l Overview

The LANCE (Local Area Network Controller for Ethernet) and the SIA (Serial Interface Adapter) operate
together to provide a complete interface from the backport bus to the Ethernet. To provide electrical isolation
between the DESQA and the Ethernet transceiver, a transformer passes the signals between the SIA and the
transceiver differential pairs. Between the SIA and the Ethernet is a selector for choosing Thinwire or Thickwire
transmission. In the Thickwire mode the signals are routed to the D-Type connector and for the Thinwire mode,
they are routed to the DP8392 transceiver chip and from there to the BNC Thinwire connector.
On the backport side of the LANCE, two bus transceivers isolate the LANCE from the backport data bus, and
two latches isolate the LANCE from the backport address bus (arbitrated by the QNA2). The SIA takes a 20MHz
clock input from the DESQA clock, and uses it to generate a 10MHz clock, which it also passes to the LANCE
for synchronisation.
The SIA pmvides Manchester encoding of data for transmission, and decodes received data. The LANCE
supplies and checks the 32-bit CRC that is appendi::d to all Ethernet packets.
During transmission the LANCE polls the transmit buffer descriptor list for buffer descriptors that it owns.
When it finds an entry that it owns it DMA's the data from shared RAM into internal FIFO. It prefixes the
64 bit preamble to the packet and sends the data to the SIA as a serial bit stream. When the packet has been
transmitted, or if an error occurs, the LANCE will update the relevant buffer descriptor.
A DC-to-DC converter provides the -9V supply required for the operation of the DP8392 Thinwire transceiver
chip. This -9V supply is DC isolated from the + 12V input power supply.
The Thinwire lntt:rface Circuit which includes the DP8392 transceiver chip is used to isolate DC voltage!> from
the Ethernet to the DESQA. Thi:, function is carried out by the H4xxx when Thickwire Ethernet moJc: ;s i-elected.
During reception, the SIA detects and synchronises to the incoming bit stream from the Ethernet. The LA "-:CE
checks the destination address contained in the package against its list of addresses. If it tiuds a matd1, the
LANCE will DMA the data from its internal FIFO in to buffer memory. When the reception is completcJ. or if
an error occurs, the LANCE will update the relevant entry in the receiver buffer descriptor list.
The SIA communicates only with the LANCE and the Thinwire Transceiver or Thickwire inti:rfan:. The LA'.\ICE
acts as backrorl bus master for all data transfers, and as bus slave for the 6ROOO microproce!->sor to program its
internal registers. It communicates with the QNA2 in order to access the backport bus and transfer data to anc!
from shared RAM.
Figure 4-4 shows the Ethernet interface.

- 4-14

TECHNICAL DESCRIPTION

68000

MICROPROCESSOR

RENA

LANCE
IPL 1 ...__--1 INTR

+12V

DC
646

ADDRESS
LATCH

LANCE
INTERFACE
ADAPTER

A16

DAL

RENA
CLSN
RXDATA
RXCLK

15:00

373
DATA

LATCH

SIA

DC
THINWIRE
LED

-9V

CLSN
RXDATA
RXCLK

THINWIRE
:TRANSCEIVER

HOLD
HLDA

LREAD
LALE

RCV+
RCV-

LDAS

TX+I

a:
w
~

READY
CS
TENA
TX

~1 Ie:
a:

CLSN+ _ . .
CLSNt--4-~-----•
►·• TENA

c::

WO
a: 1-

- o
3:w

~-'
:r
w

I- Ch

1--1---------►ITX

L.,;T:_:X::::C:,:::LK~J-1-"-------.... TXCLK
RENA . ._ _ _ _ _ _
_J

FUSE 1 ◄◄-------------------------

G
QNA2

FH1

SA PICOFUSE

1.5!, 250V

THICKWIRE
CONNECTOR

-----------t>~-----v(l---------------------------

Q-BUS
CONNECTOR

Figurt 4-4

Ethern~t Interfa.:e (hardware)

4.5.2 Initialisation
The LANCE initialises itself on request from the 68000. The 68000 writes an Initialisation block frcim 68000
ROM to shared RAM. and programs the LANCE. CSR to locate the block. The LANCE reads the block to
determine mode of operation, addre~s recognition parameters. and buffer descriptor ring pointers.

4-15

TECHNICAL DESCRIPTION

4.5.2.1 Destination Addresses
The LANCE can be programmed to match three different types of address from an incoming packet, as follows:
1.

48-bit destination address
This is programmed as the unique address of the DESQA. Usually, the initialisation block is programmed
to include the physical address from the SA (Station Address) PROM, but DECnet software reprograms the
address in order to reflect the current DECnet node number. (SA ROM still stores a permanent record of the
default physical address.)

Multi-cast address filter
This is programmed using a logical address mask in the initialisation block.

Promiscuous mode

In this mode the LANCE is programmed to accept all incoming packets. This mode is set using the mode
register in the initialisation block.

4.5.2.2 LANCE Memory Structures
There are three memory structures accessed by the LANCE:
I.

Initialisation Block (12 words) contains the operating parameters for the device: mode of operation; physical
addre~s; logical address mask; location of receive and transmit descriptor rings; number of entries in receive
and transmit descriptor rings.

Receive Message Descriptor Rings (rMDR) and Transmit Buffer Descriptor Rings (tMDR). Two ring
structures, one each for incoming and outgoing packets. Each entry is four words long, comprising: data
buffer address, length, and status.

Data buffers for packet buffering.

These memory structures are set up in shared RAM by the 68000 microprocessor. The 68000 then writes the
Initialisation 'Block Start Address (IADRl to CSR 1 and CSR2 in the LANCE, and the LANCE loads itself with
the informatioil contained in the Initi.!lisatiun Block.
Refer to Appendix A for details.

4.5.3 Transmission
The LANCE polls the transmit Message Descriptor Ring (MOR) automatically every 1.6 milliseconds whenever
it is not searching out receive buffers tor incoming packets.

The polling consists of searching the status words of the transmit Message Descriptor Ring ·(MOR) for a buffer
descriptor marked a5' OWNed by the LANCE. Then the LANCE executes two more rc;.;d operations to collect the
transmit buffer addres,; md .ill> buffer byte count.
Where the buffers are chained, the LANCE looks ahead once during the current transfer in order to find the next
buffer. If it does not OWN the next MOR entry, it sets the UFLO and BUFF error bits in CSR0. When it empties
a buffer, the LANCE clears the OWN status bit for that buffer.
The interpacket gap time on the Ethernet is a minimum of 9.6 microseconds, sturting on the falling edge of the
SIA signal RENA.

4-16

TECHNICAL DESCRIPTION

In transmit mode, the host supplies the destination address, source address, and length field. The LANCE appends
preamble, sync, and CRC to the frame.

If an error occurs, the current buffer transmission is abandoned, causing an interrupt to the 68000 microprocessor.

4.5.4 Reception
When an incoming packet arrives,the LANCE checks to see if it own a receive buffer. If not it will poll the
receive ring once for a buffer. If it does not own the buffer it will set the MIBB bit in CSRO,and will not poll
the receive ring until the packet ends.
The polling consists of searching the status words of the receive Message Descriptor Ring (MOR) for a buffer
descriptor marked as OWNed by the LANCE. Then the LANCE Q.ecutes two more read operations to collect the
receive buffer address and its buffer byte count.

If the LANCE OWNs a receive packet when an incoming packet arrives, it looks ahead once between transfers
to find the next OWN buffer. This involves three separate one-word read operations. If the buffers for incoming
packet need to be chained, and the LANCE has not found the next buffer, it sets the BUFF and/or the.OFLO bits
in CSR0.
The interpacket gap time on the Ethernet is a minimum of 9.6 microseconds, starting on the falling edge of the
SIA signal RENA. If a new packet arrives within 4.1 microseconds of this edge, it can only be received correctly
if at least eight bits of the preamble are left.
in receive mode, the LANCE strips the preamble and sync bits, and transfers data and CRC to shared RAM. The
LANCE discards runt packets of less than 64 bytes (which are usually due to a collision).
The LANCE can handle up to seven dribbling bits when a received packet terminates, so long as the CRC
accounts for them. If there are both dribbling bits and a CRC error, then a Framing Error is flagged in the
Receive Message Descriptor.
If an error occurs, the current buffer reception is abandoned, causing an interrupt to the 68000 microprocessor.

4.5.5 Collision Detection
A collision on either the Thickwire or the Thinwire Ethernets is rep0rted by assertim: oi the collisior. detect
differential pair. The SIA reports a collision to the LANCE by assertirag CLSN. 1t !.:-aves TE:,t;,\ asser:cd for
beiw.:en 32 a11d 40 additional bit times in order to transruil the collision jaiil signal pattern. The jam pauem i,
any pattern other than the CRC bytes. The LANCE completes the preamble or the current byte transmission
before starting to transmit the Jam pattern.
The LANCE makes up to 16 retransmission attempts before reporting a collision.
If CLSN is, asserted during reception, the reception is terminated at once, either because of an address mismatch
with an internal pointer. or as a runt packet. A late collision (occurring after 64 byte times. or 51.2 milliseconds)
is not recognised in receive mode.

4--17

TECHNICAL DESCRIPTION

4.5.6 Buffering
The LANCE operates two types of DMA transfer to shared RAM: single word DMA, and burst mode DMA.
Single word DMA is used to access the Transmit and Receive Message Descriptor Rings MD, and to read the
initialisation block. Burst mode is used to transfer Transmit or Receive messages in eight consecutive reads or
writes.
Bus cycles are a minimum of 600 nanoseconds. Burst mode transfers are separated by a gap of at least 700
nanoseconds.
Separate MD describe transmit and receive operations. Up to 128 tasks may be queued upon each MDR.
Each message descriptor entry is four words long. Each descriptor in a ring is marked as OWNed by either
the LANCE or the host (the 68000 microprocessor). The status of a descriptor can only be changed while the
descriptor is OWNed, and ownership can only be relinquished, never taken.
The location of the descriptor rings is programmed in the initialisaiion block.
~

4.5.7 Thinwire Ethernet Transceiver
The Thinwire Ethernet Transceiver is made up of a DP8392 transceiver chip, an isolation transformer and a DCDC converter. The transformer isolates the Thinwire Ethernet Transceiver from the rest of the DESQA circuitry.
The -9 Vdc needed for the DP8392 chip, is converted by the DC-DC converter from +12 Vdc which is supplied
by the host. A functional block diagram of this transceiver component set is shown in Figure 4-5

OCTODC
CONVERTER

12VDC

499OHMEACH

-9V ISOLATED

COAX

COLLISION
PAIR

4
RECEIVE
FAIR

7
TRANSMIT
PAIR

78
OHM 8

CO+ 1

CO- 2

15 TXO

RX+ 3

14 RXI

VEE 4

VEE 5

cos

13 VEE

8392

RX- 6

TX· 7

1() GND

iX-

0664

I-''"'

L , T I C N TRANSFORMER

Figure 4-5

Functional Block Diagram of Thinwire Ethernet Transceiver

"4-18

--.,

iK
R<l, ~1~,

TECHNICAL DESCRIPTION

The DP8392 chip block diagram is shown in Figure 4-6 and is discussed in the following sections.
Section 4.5.7.l Receive Functions
Section 4.5.7.2 Transmit Functions
Section 4.5.7.3 Collision Detect Functions
Section 4.5.7.4 Jabber Functions

COAX
CABLE

.---------------------------------,

RECEIVE
PAIR

RECEIVER
EOUit.LIZER

TRANSMITTER

SENSE
TRANSMiTTER
SOUELCH

COLLISION
COMPARATOR
AND
t-C.ARTBEAT FNABLc
E • RTBEAT
~ ~ - - - - - - - - - - - - - - - - - - - - i ~E~ERATOR

0
Figure 4--6

SIA
INTERFACE

DP8392 Block Diagram

4-!9

TECHNICAL DESCRIPTION

4.5.7.1 DP8392 Receive Functions
The receiver circuitry of the DP8392 transceiver chip is made up of the following components.

NOTE
Refer to the National Semiconductor Corporation
DP8392 Data Sheet for detailed information.

The Input Buffer
This buffer provides high input impedance and low input capacitance to minimise loading and reflections on
the coaxial.

The Cable Equaliser
This equaliser is a high pass filter that compensates for the low pass effect of the cable. The composite result
of the maximum length cable and equaliser is a flatband respo""nse at the signal frequencies to minimise jitter.

The 4-Pole Bessel Low Pass Filter
This extracts the average de level on the coaxial cable, which is used by both the receiver squelch and the
collision detection circuits.

The Squelch Circuit
The receiver squelch circuit prevents any noise on the coaxial cable from falsely triggering the receiver in
the absence of a signal. The squelch turns off at the beginning of the packet when the de level from the low
pass tilter is lower than the dl' threshold. At the end of the pi1cket, a quick squelch tum on rejects dribble
bits.

The Differential Line Driver
This driver provides ECL-like signals to the rest of the DESQA circuitry that have rise and fall times of 5
ns. In the idle state. differential line driver outputs go to differential zero to prevent de standing currents in
the isolation transformer.

4.5.7.2 DP8392 Transmit Functions
The transmitter of the DP8392 transceiver chip receives differential signals from the rest of the DESQA circuitry
through the isolation transformer of the Thinwire interface. It uses a squelch circuit that provides noise immunity,
and an open collector current output driver to drive the coaxial cable when transmitting.

The open collector current output Jriver meets Ethernet speci/icati0m fo, sigr.al levels. It controls rise ar.ct fa)l
times to minimise higher harmonic components.
4.:-. ,.3 DP839:? Colli~ion Detect Fm,ctions
The rnllision detect .:ircumy of the DP839~ transceiver chip, consists of the followin,; components.
l.

The Low Pas<; Filter
This filter extracts average de level on the coaxial.

The Comparator
The comparator munitor~ the de level from the low-pas<; lilrer. If the le\cl is more negative than the collisiun
threshold, the collision output is enabled.

The Heartbeat Generator
The heartbeat generator enable is tied to ground.

The IO-MHz Oscillator
This oscillator generates the signal for the collision/heartbeat functions. and is m,ed as the timebase for all
jabber functions.
4-20

TECHNICAL DESCRIPTION

The Collision Differential Line Driver
This driver transfers the IO-MHz signal to the collision detector (CD) +/- input if collision, jabber, or
heartbeat conditions are present. It also features zero differential idle state.

4.5.7.4 DP8392 Jabber Functions
The jabber timer monitors the transmitter for faults and inhibits transmission when faults exist. A fault exists
if the transmitter is active for longer than 32 ms. The jabber timer enables collision outputs for the duration of
faults. After faults are removed, the jabber timer waits 500 ms before re-enabling the transmitter. The transmit
input must stay inactive during unjab time which is 500 ms.
4.5.7.5 Thinwire DC-to-DC Converter
The onboard DC-to-DC converter takes the +12V from the backplane and converts it into the -9V required for
their operation of the DP8392 transceiver.

The type of converter used for this purpose is a pulse width modulated ftyback type switching power supply.
Regulation is achieved via a simple single stage zener referenced amplifier, opto-coupled to the pulse width
modulator circuit.
The result is a steady -9V output that is isolated from the +12V input.
Figure 4-7 shows the block diagram of the DC-to-DC Converter.

4-21

TECHNICAL DESCRIPTION

I
OPTO
COUPLER

1- -1

I
I
I
I

_l/ I

FET
SWITCH

+12V

ASTABLE
MULTIVIBRATOR

12V RETURN

I_ _J

REGULATOR'

I LINE OF
! ISOLATION

Figure 4-7

DC-to-DC Converter Block Diagram
• 4-22

-9V

SHIELD
GROUND

TECHNICAL DESCRIPTION

4.6

BACKPORT BUS & QNA2

4.6.1 Overview
The DESQA module is built around a backport bus which passes data between the QIC, shared RAM. and the
Lance.
The QNA2 (Q-Bus Network Arbitrator) arbitrates requests for access to the backport bus. It then implements
the control function appropriate to the access request that it has granted. Priority of access is in the order QIC,
68000. LANCE.
The QNA2 input, FUSE, monitors the power indicator from the H4x.u Ethernet transceiver. The QNA2 also
drives the on-board LEDs that indicate: powerup, loopback testing, citizenship (CQ) tests, and normal operation.
Table 4-6 shows how the memory space on the backport bus is used.

-Table 4-6

Backport Address Map

Word address
Octal

Binary

QIC Base

40 377 440

100 000 Oll ll l 111 100 100 000

QNA2 CSR

20 177 416

010 000 001 111 1ll 100 001 110

QNA2 IR

20 177 436

010 000 001 111 11 l 100 011 110

4.6.2 Backport Interface Timing
The 20 MHz CLOCK input to the QNA2 is shared with the QIC. This ensures the synchronous operation between
the QNA2 and the QlC. The QNA2 further divides this 20MHz clock to produce a 10MHz clock (or the 68000
microprocessor.
The antiphase version of the QNA2 clock is passed to the SIA which uses it to generate a 10MHz clock. This
clock is passed to he LANCE as TXCLK.

4-23

TECHNICAL DESCRIPTION

4.7

MODULE CONTROL

LANCE

cs
VPA --

68000

FC0
FC1
FC2
AS

I
-

HLDA
RD
HOLD LREADY

VPA

ASM
---- COMB!LOGIC

INTACK '-- ' - -

DTACK
A23
A22 ~
RW

I II
I

VPA LCS

ASM

HOLD LREADY
HLDA
RD

DTACK
--- A23

-- A22

- FM/

QNA2

OIC

MREQ
MACK
BPAS 4 - - - - - - - - RDWR --

.___.

I
IIEll95

Figure 4-8

OMA Control Signals

4-24

TECHNICAL DESCRIPTION

4.7.1 Interrupts
In the DESQA module there are three interrupt lines to the 68000 microprocessor, as foIJows:

1. From the QIC
2.

From the QNA2

From the LANCE

The A'ITN (Attention) signal from the QIC to the 68000 is the result of a logical OR operation on several status
condition bits within the QIC. It alerts the microprocessor, which can then interrogate the QIC backport attention
register. Bits in this register are cleared when written to one, or when the QIC is reset by the QBUS.
Figure 4-9 shows the main interrupt control logic.

4.7.2 Error Recovery
Errors in accesses to host memory. and in Ethernet transmit and receive operations, are flagged in the Control and
Status Register.
The error conditions are recorded originally in the QIC Attention Register or the LANCE CSR0. The 68000
responds to a backport interrupt from these devices by examining the relevant register, transferring the information
to the DESQA CSR, and g.:-nerating a Q-Bus interrupt to the host system.
The LANCE Hags network errors in CSR0, to be examiP.cd by the 68000 following a backport interrupt. System
errors include:

Babbling transmitter attempts to transmit more than 1518 bytes

2. Collision detection circuitry not functioning
3.

Packet missed due to insufficient buffers

Memory acknowledge timeout.

PackPt errors are recorded in the relevant buffer descriptor entries. Packet errors include:

Invalid CRC

Framing e-rror

3. Overflow or underflow
4.

l.lsufficient buffors.

The LANCE contains a I 0MHz time domain reflectometry counter to aid the location of faults in an Ethernet
cable.
Figun.: 4-6 shov..s the main DMA control signals.

4-25

TECHNICAL DESCRIPTION

LOCAL AREA NETWORK
CONTROLLER FOR ETHERNET (LANCE)

FIRMWARE ROM

RESET
h

A<3:1>

VPAt4---------------+-----+---,
As--::"
68000M
MICROPROCESSOR

Fc2-1--.._ COMBI
VPAt---------1---+----..i
FC1
_ LOGIC
FCOt--~~----.J

IPL2 ~-1--~
IPL1--..---1
IPLo....,.-1----1

HALT

RESET

INTERRUPT
PRIORITY
ENCODER

'----'---------.--------+---,------~
a

,,
VPA

ATTNt---+-------~

'-----t

0-BUS NETWORK
CONTROLLER (QNA2)

RESET

----1INIT

O-BUS INTERFACE
CONTROLLER (QIC}

150ms
ONESHOT

2.2us
ONESHOT

OINIT

.....

BINIT L

200ns
ONESHOT
__J

RINIT H

IIE689f

Figure ~9

DESQA Jnterrupt and Reset Signals
·4-26

TECHNICAL DESCRIPTION

4.7.3 Sanity Timer
The sanity timer is enabled and reset by the host software. After the timer is enabled, the software must reset it
periodically; otherwise it counts to its preset limit and times out.
When the sanity timer times out, the Q-Bus line DCOK is negated for approximately 3.6 microseconds. This
resets the host system, and invokes the primary bootstrap (depending how the jumpers are set up in the host
processor).
On reset the timeout defaults to four minutes, but it can be changed during setup mode to any factor of four
within the range 1/4 second to 64 minutes. The timer can also be disabled by host software command.

4.7.4 Initialisation
There are two initialisation mechanisms:
I.

Q-Bus powerup/reset

Software reset

Powerup initialises the LANCE and 68000 for 150 milliseconds. The Q-Bus signal RINIT is used to trigger this
reset.

NOTE

The QIC is initiali.,cd by the combination of the
RINIT asserted and RDCOK negated.
Software Reset initialises the LANCE and 68000 for 2.2 microseconds. The signal OINIT rs m,ed to trigger thi~
reset. OINIT i~ the inversion of CSR0J.
The assertion of both these resets causes the QNA2 to be reset for 200ns.

4-27

CHAPTERS
MAINTENANCE
S.1 SCOPE
This chapter describes the maintenance activities for the DESQA. The sections are as follows.

Section 5.2

Maintenance philosophy

Section 5.3

Built-in diagnostics

Section 5.5

IEEE 802.3 Network Support: Null link-layer Service Access Points

Section 5.6

Network diagnostics

Section 5.7

Module diagnostics

5-1

MAINTENANCE

WARNING
The procedures described in this chapter involve the
removal of the system covers, and should be
performed only by trained personnel.
ATTENTION
Les procedures decrites dans ce cbapitre necessitent
l'enlevement des capots du systeme. Elles ne pourront
etre effectuees que par du personnel qualifie.
VORSICHT!
Bei der Ausfuhrung der in diesem Kapitel
beschriebenen Anweisungen mussen die
Systemabdeckungen entfemt werden. Dies soUte our
von geschultem Personal ausgefuhrt werden.
, ATENCION!
Los procedimientos descritos en este capitulo
incluyen el desmontaje de las cubiertas del sistema y
debe ser realizado solamente por personal entrenado.
ADVARSEL!
lfolge de procedurer, som er beskrevet i dette kapitel,
skal systemets heskyttelsesplader fjernes; dette bor
kun udfores af personer der ved bvordan dette skal
gores.
WAARSCHVWING
Bij de procedures die in dit hoofdstuk worden
besl'hreven dienen bt-paaldc delen van de
s~·steemomhulling te worden verwijderd; dit mag
uitsluitcnd ,mrden gedaan door opgeleid personeel.
VAROITUS!
Tassa lurnssa kuntut toimenpiteet liittyviit
jiirjestelman suojakansien irrottamiseen. Ainoastaan
koulutettu hcnkilokunta saa suorittaa nama
toimenpiteet.

Figure 5-1

5-2

\\'arnings

MAINTENANCE

i£ ..
• ~ B: 1: (;t , ~ f* 'h , ' - o, JUl l'J ~ L 'if i: -::> \ , '"C
~ " -c 6, " t -t o fl: • ,1 . i!:·
wr, 0) ru ~ ~
,~ J;. -, "C ~ ~ t. -, "'( "f ~ I,' ..

-r

o•oJn~ n,o~J n1J1,J .~t w,~J n,,,,nnn~ n,~,u~~
.10010 o,N .,. ,u ~,, ,~ lU~lT'l nJ,un~ ?~

ATIENZIONE
La procedura descritta in questo capitolo comporta la
rimozione delle coperture e deve essere eseguita solo
da personale specializzato.
ADVARSEL
I dette kapitlet beskrin•s bl. a. h\'Ordan man f,Jerner
dekslene rundt systemet. Dette arbeidet ma bare
utfores av fagfolk.
AVISO
Os procedimentos descritos neste capitulo respeitam

a forma como se retiram as protec~oes do sistema.

Dada a sua es~cificidade, recomenda:!los que seja
executado por pcssoal especializado.
VARNING
I detta kapitel beskrivs hur systemkaapan tas bort.
Detta faar endast utfocras u utbildad personal.

Figure 5-2

5-3

Warnings

MAINTENANCE

5.2 MAINTENANCE PHILOSOPHY
5.2.l Preventive Maintenance
There are no preventive maintenance procedures for the DESQA module. However, when the host system is
serviced it is good practice to check the DESQA installation for loose connectors, damaged cables, and similar
faults.
5.2.2 Corrective Maintenance
The DESQA module has been designed to enable diagnostics to determine a faulty Field Replaceable Unit (FRU)
rapidly. Corrective maintenance in the field therefore consists of changing FRUs. Component replacement in the
field is not intended and is not recommended.
The diagnostic tests are processor-specific.
•

For PDP- I I host processors
Network testing
DECnet Network Control Program (NCP)
Network Interconnect Exerciser (NIE) running under Diagnostic Runtime Services (DRS)
Module testing
Field functional diagnostic (ZQNA??) running under diagnostic runtime services (DRS)
DEC/X 11 Exerciser.

•

For MicroVAX processors
Network testing
DECnet Network Control Program (NCP)
Network Interconnect Exerciser (NIE) running under the MicroVAX Diagnostic Monitor (MDM)
Module testing
MicroVAX Diagnostic Monitor (MDM)

5.2.2.l DESQA Thinwire Troubleshooting (Thinwire Mode)
The following figure shows a flowchart for troubleshooting the DESQA when configured in the Thinwire mode.

5-4

MAINTENANCE

ENTER

RUN NIE (NETWORK
INTERCONNECT
EXERCISER)
TO IDENTIFY
FAILING NODE

GO TO FAILING NODE

POWER DOWN HOST

POWER DOWN HOST AND
CHECK DESOA FUSE (IN
HANDLE) AND PICO FUSE
(ON PCB): IF BOTH O.K.
CHECK HOST POWER: IF
O.K. REPLACE DESOA

POWER DOWN HOST
AND CHECK JUMPER
BLOCK SELECTION. IF
CORRECT REPLACE
DESOA.

REPLACE DESQA

________J

NETWORK PROBLEM

POSSIBLE NETWORK
/HOST/ DESOA
PROBLEM
CALL SUPPORT

Figure 5-3

DESQA Troubleshooting (Thinwire Mode)

5-5

MAINTENANCE

S.2.2.2 DESQA Thickwire Troubleshooting (Thickwire mode)
The following figure shows a flowchart for troubleshooting the DESQA when configured in the Thickwire mode

ENTER

AUN NIE (NETWORK
INTERCONNECT
EXERCISER)
TO IDENTIFY
FAILING NODE

GO TO FAILING MODE ~ - - - - - - _ _ , J

POWER DOWN HOST AND
CHECK DESQA FUSE (IN
NO
HANDLE) AND PICO FUSE
~--t-.i (ON PCB): IF BOTH O.K.
CHECK HOST POWER: IF
O.K. REPLACE DESOA

POWER DOWN HOST

POWER DOWN HOST
AND CHECK JUMPER
BLOCK SELECTION. IF
CORRECT REPLACE
DESQA.

ANSCEI
E WITH LOO
CTOR (12-2

T. CHECK C
M PCB TO 1
i::lE TRANS
ET FOR PR
NNECTI

UP HOST AN

EOUEt~C:: A
TABLE 5-

-1

YES
RECONNECT CABi..E
CORRECTLY

REPLACE DESOA

• 5-6

MAINTENANCE

REPLACE OESOA IF
FAULT PERSISTS.
OBTAIN H4080 AND
_,__ _ _ _~ TRANSCEIVER CABLE
FOR FURTHER TESTING

REPLACE TRANSCEIVER
>----11-.CABLE

REPLACE. DESQA

NETWORK PROBLEM

POSS:BLE NETWORK/
HOST, DESQA

PROBLEM: CALL
SUPPORT

Figure 5-4

DESQA Troubleshooting (Thickwire Mode)

5-7

MAINTENANCE

NOTE
Early versions of the DEQNA diagnostics are not
compatible with the DESQA. For PDP-11 processors
use ZQNAI or later. For MicroVAX processors use
Diagnostic release 124 or later.
5.2.3 Field Replaceable Units (FRUs)
The Field Replaceable Units (FRUs) are:

•

The DESQA module

•

Bulkhead assembly fuse
Transceiver and transceiver cable (or bulkhead loopback connecto.,2
Module picofuse.

NOTE
This picofuse should only be replaced by trained
personnel.
Figure 5-5 shows the field replaceable units in the DESQA installation.

TEE-PIECE AND
TERMINATORS

THICKWIRE
ETHERNET

THINWIRE
ETHERNET

Cl)

HOST
SYSTEM

TRANSCFIVER

::,
CD

BULKHEAD
LOOPBACK
CONNECTOR

FUSE SA PICO FUSE (1 SA l
FOR FURTHER t•JFORt,MTiO'II ON :'.:ORRECT FUSE SEE SECTION 4.32.1.
R£70S4

Figure 5-5

Field Replaceable Units (FRUs)

5-8

MAINTENANCE

5.2.4 Diagnostic Procedure
The general strategy for identifying a fault is as follows:
l.

Check the DESQA configuration to ensure that the system can identify the module correctly.

Run the module test(s) to test for faulty FRUs.

Run the network test(s) to test for faults in network configuration and/or operation.

5.3 SELF-TEST
The DESQA has a comprehensive self-test which is executed at powerup in Normal mode only. In addition in
Normal mode the self-test can be requested by the host operating system software through the DESQA Q-busregisters. The test takes about five seconds to run and consists of the following sections.
1.

The ROM-32 checksum test checks for corrupted ROM content.

The RAM test checks memory addressing and operation.

The 68000 microprocessor test checks for correct execution of 68000 instructions and handling of CPU
exceptions.

The QIC function tests check QIC programming functions.

The QNA2 function tests check:
•

Access to the DESQA CSR

•

Sanity timer operation

•

Acces~ to the SA ROM
QNA2 interrupts to the 68000 when the host accesses BDLs.

The SA ROM test verifies the checksum on the SA ROM.

The LANCE/SIA subsystem tests check:
•

The LANCE internal Control and Status Register

•

The LANCE subsystem address and data paths

•

The CRC generation circuitry (using correct and incorrect CRCs)
The nntification of RETRY error following collisions on 16 succes~ive attempts Ln transmit a packet

•

Thi:'. broadcast. multi-cast. .ind physical address filtering
The int~mal loophack
The exterrd loophack.

~OTE
A successful pass of the self-test requires that the
DESQA be connected to a valid Ethernet network,
or an external loopback connector. For Thickwire
use the Bulkhead loopback connector (12-2219602) or alternatively an 84080 Ethernet tester. For
Thinwire, the "T" piece with two terminations (1226318-01) attached should be connected to the BNC
connector.

5-9

MAINTENANCE

Table 5-1

Module LED Sequences

LEDi

LED2

LED3

Normal Mode - Power-Up Sequence
Definition

Executing internal logic self-test

ON
ON

Self-test executing external Joopback test
ON

Ready (to execute citizenship tests and/or normal functions) or module self-test

DEQNA-lock Mode ON

Power-Up Sequence

All LEDs come on and stay on

If an Ethernet boot is initiated in either Normal or DEQNA-Jock mode, or if software initiates a citizenship test,
the following additional LED states are used.

LEDi

LED2

LED3

Definition

Ready (to execute citizenship tests and/or normal functions) or module self-test

Executing citizenship tests
Internal loopback citizenship tests completed successfully
External loopback citizenship tests completed succe!>sfully

These sequences of LEDs should take less than 10 seconds. If the LEDs flash after this time, and irrecoverable
failure has occurred. See Table 5-2.

Table >-2

l,i e,:onrai>I~ Failure Indications

Failure lndilation

LEDi

LED2

LED3

(.>-bu, tailtm:

OFF

LAJ",;CE failure

OFF

68000 exception

OFF

Firmware Fault

--·-

--...,

5.3.l Extended Primary Bootstrap
A PDP-11 host can boot from a DESQA using a method similar to that for a mass-storage device. Part of the BD
ROM on board the DESQA contains PDP-11 code for bootstrapping a PDP-11 from the network. This pan of the
boot/diagnostic BD ROM is made up of three sections.
•

The Extended Primary bootstrap (EPB) code

•

The DESQA citizenship (CQ) test code

--..,,.

• 5-10

MAINTENANCE

•

The DECnet secondary loader code

The host primary boot code passes control to the EPB code (loaded from the BD ROM), which then loads and
verifies the complete contents of the BD ROM into host memory. The EPB code then initiates the CQ test before
allowing the DESQA to access the Ethernet.
5.3.2 Citizenship Test
The DESQA citizenship test (CQ) is a series of diagnostic test routines that determine whether the DESQA
is operating correctly and can access the Ethernet, or is faulty and requires further diagnosis. Test results are
indicated in part by the LEDs on the DESQA, and complete test reports are returned to host register RO.

The CQ test uses internal loopback, internal extended loopback, and external loopback modes, and requires the
DESQA and an H4xxx transceiver (or equivalent); connection to the Ethernet is required. The sanity timer is
enabled for testing but is not expected to time out. If the timer does time out it is an error. When all testing is
complete, the sanity timer is turned off, unless switch S3 is open, in which case it is left on.
The CQ test is a free-standing subroutine and can be called by other software. For example, during network boot,
CQ can determine if the node should be allowed to proceed from the initialised state to either a functional or a
nonfunctional state.
5.3.2.1 Citizenship Test Descriptions
The citizenship tests are described in the list that follows. The corresponding error bit values that appear in host
register RO are also given.
Tl:
Station
Address
Verification

The default physical address is verified ru:d copied from the Station Address (SA) ROM into a test pack~t for
later use. If this test fails, testing continues until the final external loopback test or another test failure occurs.
Possible errors are:

T')·

ROcBit

Error Description

Station address is all zeros, or all ones, or is not a valid DESQA address

Device
Interrcpt
Test

A transmit des\.'.rip:0r is given to ,he UUT attcr imerrupts are enabled. 1 ne UllT shoul,I gem:ratt: a trammi1
inte-rrupt. Possible erro1~ are:

T3:

RO Bit

Error Description

No interrupt occurred, or interrupt occurred prematurely, or wrong interrupt occurred

Setup Mode
and Receh·e
Processing
Test

A series of setup packets with a repeating test pattern for checking stu~k-at faults is transmitted to tile l TT. 1 he
patterns are varied so that each byte in the station address memory is tested with all pattern:;. Possible errors are:

5-11

MAINTENANCE

T4:

RO Bit

Error Description

12,01

Setup packet echoed data check

09,12,01

Setup packet operation timeout

14,12,01

Setup operation status check

Internal
Loopback
and Address

Filter
A setup packet is generated with all target addresses identical and based on a pattern of one walking bit. This
packet is set up in the Unit Under Test (UUT). Then, two internal loopback packets are generated and transmitted
for each address in the pattern. The first packet is addressed to the complemented target address, which is not in
the pattern, and must be correctly transmitted and received as a runt. The second packet is addressed to a target
address in the pattern, and must be correctly transmitted and received.
The test is repeated 48 times with a walking bit of one (other bits zero) advanced by one bit each time, and then
with a walking bit of zero (other bits one). Possible errors are:

T5:

RO Bit

Error Description

Transmit/receive data compare check.

Unexpected receive interrupt

09.02

True packet transmission and receive error

12,02

Setup packet echoed data check

14,02

False packet receive error

Internal
Extended
Loopback
and Protocol

The Unit Under Test (UUT) j._ put in internal extended loopback mode and packets of varying (increasing)
length are circulated through the tram,miller am! receiwr. The packet,, are made up uf bit pattt'rns de~igr.ecl ,n
show stuck-at conditions and iaults in the buffers. The received packets are , erified to be sur,;: that the data w:b
properly transferred. The packet length starts at the minimum Ethernet packet size and continue~ until beyond the
maximum size. Possible errors are:

RO Bit

Error Description

General packet transmit/receive data compare check

Long packet not detected

09,03

Test packet transmit or receive timeout

14,03

General operation status check

5-12

MAINTENANCE

14.03
T6:

Long packet not detected via operation status

DMA to Q-

bus Interface
Processing
An internal extended loopback packet with the station address is transmitted using a chained descriptor, with
buffers, elements and high/low bytes. This packet is received and verified. Possible errors are:

T7:

RO Bit

Error Description

Transmit (scatter/gather) data check

09,04

Transmit (special) and receive timeout

14.04

Receive or transmit operation status check

Transceiver
Operational
and Status

A setup packet with the physical address of the Unit Under Test (UUT) is generated and looped back through the
DESQA. T.he packet also turns off LED 2 and sets the sanity timer value reset to 1/4 second. CSR13 (Carrier
from Receiver) is monitored to be sure it is cleared; or, if it is set, that it is cleared within approximately 100
microseconds. Possible errors are:

RO Bit

Error Description

Setup packet echo data check

09,12

Setup packet operation timeout

14,12

Setup packet operation status check

CSR carrier bit on for too long

5-13

MAINTENANCE

T8:

External
Loopback
and Ethernet
Protocol

This test is executed only if no other errors have been detected.
The physical address of the Unit Under Test (UUT) is assumed to be set up by TI. The next minimum-size
Ethernet packet, addressed to the UUT with a data pattern of descending-integers, is transmitted and received
using external loopback. Finally, the maximum-size Ethernet packet is generated and sent to the UUT. The
maximum packet is addressed to the UUT and has a data pattern of descending integers. Both packets will test
Ethernet protocol processing, and the maximum packet will test the transmit FIFO memory. Possible errors are:

RO Bit

Error Description

External loopback not operational

External loopback transmitted/received packet data compare check

09.05

External loopback operation timeout

14.05

External loopback operation status check

5.3.2 .2 Citizenship Test Results
The CQ test either executes successfully or fails, as follows.
a.

CQ te~t succe~sful: the value of host register RO is zero and the DESQA is set up as follows.
•

All tbe·_· DESQA module LEDs are off. (See steps 2, 3, 15. and 16 from Sections 2.4.3 and 2.4.4, to
gain al'cess to these LEDs.)
All 14 target addresses are set to the physical address from the station address ROM.

•

The sanity timer is set to its default interval (four minutes) and disabled or enabled, according to the
setting of option switch S3.
Modes for promiscuous and all multi-cast address filtering are off.
The DESQA ha'. hee'1 reset.
Recei\'e is dis~hled
Transmit 1~ disabled.

5-14

MAINTENANCE

CQ test fails: the LED indicators display the following error codes.

LEDi

LED2

LED3

Definition

OFF

(Step 4) CQ test passed

OFF

(Step 3) External loopback test failed

OFF

(Step 2) DESQA internal error

(Step I) Cannot upload the BD ROM contents, or the first setup
packet prefill failed

The bits in register RO indicate the test that failed. If bit 15 is the only bit set, the DESQA passed all the CQ
tests except those which require a connected transceiver.

Table 5-3 Citizenship Test: Error Bit Definitions
Bit

Error Definition and Source(s)

External loopback not operational (Tests 7 and 8)
Ethernet not operational
H4000 not operational (blown fuse, disconnected)

Operation completion status check (all tests)
CSR status after final r.:sct not no.ninal
CSR status after transmit and/or receive not nominal
Receive descriptor flags and status word 1 not nominal
Received byte length check
Transmit descriptor flags and status word I not nominal
TDR value= 0

Sanity timer interrupt (general error)
Pov. er failed during test
lJnefiJt:C'led ;,nity timer intem1pt

Set::p racket or target address echo check (all tests)
Set·•p packet transmit timeout
Transmit status not nominal
Setup packet receive timeout
Receive status not nominal
Echoed data not identical to transmitted data
Extra word at end of setup packet not nominal

Spurious or missing device interrupt (general error)
Expected device interrupt not dett>cted
Device did not detect nonex;,tent memory (NXM) bus state
18-bit or 22-bit addressing failure
Unexpected DESQA devic2 interrupt

5-15

MAINTENANCE

-..,,
Table 5-3 (Cont.) Citizenship Test: Error Bit Definitions

Bit

Error Definition and Source(s)
Bus timeout or NXM interrupt (general error)
1/0 page not accessible for read or write
Cannot read station address ROM
Test code attempted to access nonexistent memory

Device operation timeout (all tests)
Unit under test failed to complete a transmit and/or receive in time

Undefined

Self-test error

Final operation failed to clear device

Ethernet external loopback test check (Test 8)
Ethernet protocol processing check
Ethernet minimum valid length processing check
Ethernet maximum valid length processing check

DMA-to-Q-bus interface processing check (Test 6)
DMA odd/even length and address processing check.
Multi-element transmit descriptor processing check
Chained transmit descriptor processing check

Internal extended loopback transmit buffer data check (Test 5)
Ethernet protocol processing check
Transmit buffer memory malfunction
Packet size processing error (protocol error)

Station ad,lre,s co~npare test check (Te~t 4)
Address filter logic passing all addresses
Addi."~.~ filtt>r logic not passini e"<pected addresses

Station address/receive processm.;; check (Test 3)
Target address RAM malfunction
Packets not properly stored in receive buffer.
Receive memory malfunction

Invalid Ethernet station address (Test I)
1/0 page register read failure (see also bit 10)
Unit under test is not a DEQNA (M7504)
Station address ROM malfunction
Invalid DESQA address

5-16

MAINTENANCE

5.4

IEEE 802.3 NETWORK SUPPORT: NULL LINK-LAYER SERVICE ACCESS POINTS

In NORMAL mode the DESQA implements IEEE 802.2 logical link control messages when they are received on
a NULL Link-layer Service Access Point (LSAP) within an IEEE 802.3 standard local area network.
These messages can be used to interrogate and test many link layer service points per node. Therefore, IEEE
802.2 logical link control messages which are received on a non-NULL LSAP are passed on to the host system
as normal datagrams.
For details of this message format and protocol, refer to the ANSI/IEEE Draft International Standard 802.2
Logical Link Control.
S.4.1 TEST Message
The IEEE 802.2 TEST message is similar in function to the loopback message on Ethernet networks.

5.4.2 XID (Tr~nsmit ID) Message
The IEEE 802.2 XID (Transmit ID) message is similar in function tcn:he MOP remote console request system ID
messages on an Ethernet network.
The DESQA does not broadcast IEEE 802.2 XID messages automatically as it does with MOP system IDs. since
it is not required by the IEEE 802.2 protocols.

5.5 NETWORK DIAGNOSTICS
5.5.1 DECnet Network Control Program (NCP)
The DECnet Network Control program (NCP) provides a command-driven interface for executing loopback tests
oa the Ethernet, and for examining network and datalink counters.
Som<'. of the relevant commands are:
•

LOOP

•

SHOW

•

TELL

•

TRIGGER.

The TRIGGER command may 1-e used to initiate boot loading from the UESQA for PDP-ll host system': ,hat
have the apprnpriat,· h,1c·t RO;\i s:ipport.
The commands may be is!>ued either from the local host system or, by using the TELL command, from a remote
node. The functiom are performed concurrently witb other DECnet operations, and do not intcrfore with othc~
Ethernet traffic (althou_'.!h there may be some degradiltio:1 of tl:roughput).
Refer to the DECnet System Manager's Guide for further information.
S.5.2 Network Interconnect Exerciser (NIE)
The Network lnterconnecL Exerciser (NIE) diagnostic program is used to determine the connectivity of node; on
the Ethernet; to determinr the ahility of nodes lC' communicate with each other; and to support nodi.: installaii,m
verification and problem isolation.
The NIE does not test the DESQA. but the communications link to which it is connected; therefore, the NIE
assumes that the DESQA has successfully completed the citizenship test.
The NIE is used with XXDP+ and MicroVAX Diagnostic Monitor.

5-17

MAINTENANCE

Refer to Appendix B for further information.

5.6 MODULE DIAGNOSTICS
The Field Replaceable Units (FRUs} that will be indicated by these diagnostics for the DESQA are:
•

The DESQA, DELQA or DEQNA modules

•

The fuse.

5.6.1 MicroVAX Diagnostic Monitor (MDM)
The MicroVAX Diagnostic Monitor (MOM) offers a selection of menu-driven tests and utilities that may be run
in verify or service modes. These are:
•

Utilities for external loopback tests and NIE

•

Service tests for external loopback

•

Verify tests for:
Internal and internal extended loopback
Setup packet handling
Buffer Descriptor Li\t (BDL) handling
DMA and interrupt handling
Transmit and receive circuitry and firmware
Addres~ filtering
De\'lce exerciser for testing the DESQA simultaneously with other system devices

MDM prompts the operator when it needs to use an external loopback connector.
S.6.2 PJlP-11 Field Functional Diagnostic (ZQNA??)
The field functional diagnostic program (ZQNA??) tests the DESQA in Q-bus systems. It attempts to isolate
fault, to the Field Replaceable Units (FRUs):
Tc!-.t~ iin: ~xecuk~l unde• ihf" ~upen-i~ion of the Diagnostic Runtime Services (XXD?+). and ..:ontrolled by an
operator from a (omole (h:ird copy or video).
ZQ\:x:·: i, nnt an [1h.:met net\\'.1:-k exerc;,rr. The ZQNA?? ~erifies that the DESQA ca1, ext>cnte Ethe-met
protocol. and that valid net\\ork traffic can be transmitted and received. The Netv.ork lnterco1111~c1 Exerciser
(NIE) provides a higher level of testing.
ZQNA?? tests the DESQA in all loopback modes: internal loopback and internal extended loopback mode!., with
or without an external loopback connector or transceiver connected.
External loophack mode is used with a connected transceiver or external loopback connector. Alternatively.
external loophad; mt,dc can he u~cd with a terminated transceiver that is not attached to a netwurk cab;e.
Executing ZQNA"?·! using c:-.1emal loopba.:k mode in a system connected to a live Ethernet does not disrupt the
Ethernet.

• 5-18

MAINTENANCE

5.6.3 PDP DEC/Xll Exerciser
The DESQA DEC/XI I Exerciser exercises one DESQA at maximum activity rates. It transmits and receives
random-length packets (using either 18- or 22-bit physical address space). The DESQA transmits and receives
the same packet.

NOTE
Early versions of the DEQNA diagnostics are not
compatible with the DESQA. For PDP-11 processors
use ZQNAI or later. For MicroVAX processors use
the Diagnostic release 124 or later.
5.7 OPERATING ENVIRONMENTS
5.7.1 PDP-11 Diagnostic Runtime Services (DRS)
The Diagnostic Runtime Services (DRS) run under the XXDP+ monitor. To start the DRS, use the following
procedure.

Boot XXDP+

To the "." prompt, type :R <NAME>
where <NAME>is either:
VNIA?? for the PDP NIE or
ZQNA ?? for the functional diagnostic

To the "DR>" prompt type START[/SWITCHES][/FLAGSJ.
For details of switches i>nd flags. sections B.2.1 ..'. and B.2.1.3
respectively.
DRS prompts CHANGE HW (L)?
Respond with y(es) (unless the hardware information has been preloaded using the setup utility) and answer
all the hardware questions that follow:

# OF UNITS (D) ?
Respond with the numb.:r of uni1:, to be tc..:sted (there is no default). At lP-ast one dt:vice must be srP.cified for
th.: program to run. To abort testing the devii.:e, type 0.
DRS requests the following information for each device:
BASE ADDRESS OF DESQA/DEQNA?

Respon"d with the address of the 1/0 page register assigned for one of the DESQA devices; refer to Chapter
3 for details.
INTERRLTPT VECTOR ADDRESS?

Respond with the DESQA interrupt vector address; refer to Appendix A.
WHAT IS THE PRIORITY LEVEL?

Respond with the DESQA interrupt priority level.
4.

DRS prompts: CHANGE SW (L) ?
Respond with N(o).

For a complete description of DRS, refer to the XXDP+ User's Manual.

5-19

MAINTENANCE

5.7.1.1 DRS Commands
There are 11 DRS commands. The system can recognise a command by its first three characters; for example.
you can type STA instead of START.
Table 5-4 lists the DRS commands.
Table 5-4

Diagnostic Runtime Services (DRS) Commands

Command

Description

ADD

Activate a unit for testing (all units are considered active at START time).

CONTINUE

Continue at the test that was interrupted (after CTRL/C).

DISPLAY

Print a list of all device information.

DROP

Deactivate a unit.

EXIT

Return to the XXDP+ monitor (XXDP+ operation only).

FLAGS

Print the state of all flags.

Print statistical information (if implemented by the diagnostic).

PROCEED

Continue from an error halt.

RESTART

Start the diagnostic without initialising.

START

Start the diagnostic from an initial state.

ZFLAGS

Clear all flags.

5.7.1.2 DRS Switches
To modify supervisor operation. several switches can be appended to each DRS command. The system will
recognise a switch by its first three characters. For example, you can type /TES:1-5 instead of /TESTS:1-5.
The switches can be used in combination, for example:
;.-'.xample 5-1 DRS Switch Combination<;
STARTffESTS: 1-5/PASS: 1000/EOP: 100

executes tests I to 5, tests all units 1000 times, and prints the end-of-pass messages only after every 100 passes.
Table 5-5 lists the DRS switches that can be used with each command, with a brief description of each. Table
B-3 indicates the commands to which each switch applies.

5-20

MAINTENANCE

Table 5-5 Command Switches
Switch

Description

/EOP:ddddd

Report End-of-Pass message, and pass count and total errors, only after every ddddd
passes.

/FLAGS:flag

Set the specified flag(s).

/PASS:ddddd

Execute ddddd passes, where ddddd = 1 to 65535 decimal.

/TESTS:list

Execute only the tests specified by list (a string of test numbers).
For example: STARTITESTS:/:5:7-10 runs tests 1, 5, 7, 8, 9, and 10, and no others.

/UNITS:list

Test/ADD/DROP only those units (0 to 63) specified by list.
For example: START!UNITS:0:5:10-/2 tests-ttnits 0, 5, 10, 11, and 12.

Table 5-6

Switch Application

Commands

Switches
Tests

Pass

Flags

EOP

ADD

Units
X

CONTINUE

DISPLAY

ORO~

EXIT

(none)

FLAGS

(none)

PROCECD

RES1ART

START

ZFLAGS

(none)

5.7.1.3 DRS Flags
Commands are used with the /FLAGS switch to set up certain operational parameters. such as "loop on error".
The flag..; rt>main ai, specified by the last !FLAGS switch. All flags are cleared:

At startup, and remain cleared until explicitly set with the /FLAGS switch

After a START command, unless set with the /FLAGS switch with the ZFLAGS command

With the ZFLAGS command.

5-21

MAINTENANCE

Rags can be specified in combinations. For example:

Example B-2 DRS Flag Combinations
/FLAGS:LOE:IER:BOE
causes the program to loop on error, inhibit error repons, and sound the bell on error..
The flags are listed and described in Table 5-7.

Table 5-7 Flags Application
Flag

Effect

ADR

Execute the autodrop code.

BOE

Sound the bell on error.

EVL

Execute evaluation (on diagnostics supporting evaluation).

HOE

Halt on error-return control to DRS command mode.

IBE

Inhibit all error repons except first level (first level contains error type, number, PC, test and unit).

IDR

Inhibit the program from dropping umts.

IER

Inhibit all error reports.

ISR

Inhibit stati~tical reports (applies only to diagnostics which support statistical reporting).

IXE

Inhibit extended error repom, called by PRINTX macros.

LOE

Loop on error. One error occurrence will cause the test to loop until the operator takes the program
out of the loop.

LOT

Loop on test.

P!\T

Print the test numher as the test executes.

PR!

Di1 ~ct me,sages to the line printer.

UA\f

Unattended mode (no manual intervention).

5.7.2 MicroVAX Diagnostic Monitor (MDM)
The Micro\"AX Diagnostic Monitor (MOM) is a bootable, menu-driven, maintena.'lce and diagnostics system
which runs the MicroVAX Diagnostic Monitor (MOM) as part of its optional Service -.ersion. For ObSQA
te!>ling. MOM include~:
I.

Exterr,al loorhilc.'k utilities tests. including NIE utilities

Functional tests

Exerciser tests.

·S-22

MAINTENANCE

The installation version of MDM is supplied as standard with MicroVAX systems. It provides two levels of
testing.
I.

Verification test for the configuration. A console display lists the devices found. If an installed device is
missing from the list, its configuration details (address and vector assignments) and physical connections
should be checked.

2. System-level functional and exerciser tests for all devices that are currently configured. Displays on the
console, and LED indicators on the device itself, show the current test status of each device.
All tests are accessed from the main MDM menu display, using subsidiary menus to initiate Installation and
Service tests.
Section 5.11 describes the DESQA MDM tests in more detail.
Refer to the MicroVAX Diagnostic Monitor User's Guide for further information about MDM.

5.8

NETWORK INTERCONNECT EXERCISER (NIE)

The NIE diagnostic program is used to determine the connectivity of nodes on the Ethernet. It determines
the ability of nodes to communicate with each other, and supports node installation, verification and problem
isolation.
The NIE does not test the device (DESQA), but the communications link to which it is connected; therefore, the
NIE assumes that the DESQA has passed device-specific diagnostics. If any hardware errors occur during
execution, the NIE reports the error by message to the operator. Unless command to halt on error (see
Section 5.11.1.2), the NIE re-;umes testing where it left off after reporting the error. However, note that the
NIE does not test the DESQA to its performance limits, diagnose problems, provide comprehensive hardware
testing. nor identify a failed FRU.
The ME runs under control of either the PDP-I I Diagnostic Runtime Services (DRS) software or MDM;
the,cfore, it c.mnot ru11 l•ml·.irrently with any op.-rating sy<;tem, nN can anyone else use the sysrem whik the
NIE is running. In addition, 0verall performance of the Ethernc~ can bt: degraded by runnmg the 'NIE.

5.9

OPERATING MODES

The NIE is command-driven: that is. it executes commands given by the uc;er. Command.; are descrihed in
Paragraph Section 5.1 I In addition to entering commands, the user can select one of two operating modes:
unitttendcd or opcr;,tor directru.
5.9.1 lln,., iended ,tode
This mode allows Ethernt:t testing without operator interaction. The tests share a table comprising the physical
addn."sse, r,f the node~ to 1,e lestcd ll',;0de T;1ble), and use default test parameter!> th:i• cannut be: mudified by the
operator. The unattended mode:
I.

Runs internal loop test

Runs external loop test

Build!. node table

Runs direct lnop mes~.ige test

Runs pattern test

Runs multiple message activity test

5-23

MAINTENANCE

5.9.1.1 Build Node Table
The build subroutine is called to collect the physical addresses of the Ethernet nodes. It begins by transmitting a
Request ID message on the Ethernet, to find a node to test. As the other nodes respond with their IDs, the NIE
collects the IDs and adds the nodes to the node table, to include them in the tests.
5.9.1.2 Direct Loop Message Test
This test checks the ability of a node to respond to a loopback request. (See Paragraph Section 5.11.2, RUN
TEST command, DIRECT test.) A node has a maximum of 8 seconds to respond; three attempts are made to
contact each node.
5.9.1.3 Pattern Test
This test sends six different loop direct messages to each node in the node table. (See Paragraph Section 5.11.2,
RUN TEST command, PATTERN test.)
5.9.1.4 Multiple Message Activity Test
This test uses the direct loop maintenance feature to create a large volume of Ethernet traffic. Loopback requests
are sent to a subset (for example, I 0) of the available nodes. AIJ nodes in the subset are expected to respond, but
data integrity is checked for only one of the responses (to save overhead). Upon successful completion, testing
continues, checking the response from a different node each time. After all the nodes in the subset have been
tested, testing continues with a different subset. This test is expected to cause multiple collisions and can affect
overall Ethernet performance.
S.9.2 Operator Directed Mode
The commands available in this mode are listed below and described in Paragraph Section 5.1 l.2.
HELP
BUILD
CLEAR MESSAGE
CLEAR NODE
CLEAR SUMMARY
IDENTIFY
MESSAGE
NODE
RUN DIRECT
RUN LOOPPAIR
RUl\1 PATTERN
RUN ALL
RUN RESP

SAVE
U!'i!SAVE

SHOW COUNTERS
SHOW MESSAGES

SHOW NODES
SUMMARY
EXIT

5-24

MAINTENANCE

5.10
SYSTEM REQUIREMENTS
The following hardware is the minimum required to run the CVNIA NIE program.

•

LSI- II processor

•

28 Kwords memory

•

Event line enabled or real-time clock

•

Console tenninal

•

Any XXDP+ supported load media

•

DESQA Ethernet to Q-Bus Adapter (minimum of 1, maximum of 2; tested individually)

The NIE uses XXDP+ as the program loading system and the PDP-11 Diagnostic Runtime Services (DRS) for
the program environment.
5.11

COMMAND DESCRIPTION

5.11.1 DRS Commands
The 11 DRS commands are listed in Table 5-8, with a brief description of each. The system will recognise a
command by its first three characters; for example, you can type STA instead of START.
Table 5-8 . DRS Commands
Command

Description

START

Start the diagnostic from an initial state.

RESTART

Start the diagnostic without initialising.

CONTINUE

Continue at test that was interrupted (after <CfRL>C).

PROCEED

Continut: from an error halt.

EXIT

Return to XXDP+ monitor (XXDP+ operation only).

ADD

Activate a unit for testing (all units are considered active at START time).

DROP

Deactivate a unit.

PRll\T

Print :.t..1tistical intom1ation (if implemented b) the diagnostic;.

DISPLAY

Type a list of all device information.

FLAGS

Type the state of all flags (see Section 5.11.1.2)

ZFLAGS

Clear all flag~ ( see Section 5.11.1.2)

5-25

MAINTENANCE

5.11.1.l Switches
Several switches can be appended to DRS commands, to modify supervisor operation. The switches are defined
in Table C-2, with a brief description of each. (Note: ddddd = I to 65535 decimal.) The switches can be used in
combination. For example:
START/TESTS:1-5/PASS:IOOO/EOP:IOO
will cause tests I through 5 to execute; all units will be tested I 000 times; and the end of pass messages will
be printed only after every I 00 passes. The system will recognise a switch by its first three characters. For
example, you can type /TES:1-5 instead of /TESTS:1-5. Table 5-9 lists the switches that can be used with each
command.

Table 5-9

DRS Command Switches

Switch

Description

/EOP:ddddd

Report End of Pass message only after every ddddd passes.

/FLAGS:flag

Set specified flag(s) (see Section 5.11.1.2)

/PASS:ddddd

Execute ddddd passes.

/TESTS:list

Execute only the tests specified by list (a string of test numbers). For example:
START/TESTS: I :5:7-10
will run tests l, 5, 7, 8, 9, and IO. No other tests will be run.

/l'.i',ITS:lis:

START/ADD/DROP only those units (0-63) specified by list. For example:
START/UNITS:0:5: 10-12
will test units 0, 5, IO, 11. and 12

5-26

MAINTENANCE

Table 5-10 Switch Application

Commands

Tests

Switches
Pass

START

RESTART

CONTINUE

EOP

Units

PROCEED
EXIT

Flags

(none)

ADD

DROP

(none)

DISPLAY
FLAGS

(none)

ZFLAGS

(none)

---5.11.1.2 Fiags

Flags are used to set-up certain operational parameters, such as looping on error. All flags are clear~d:
1.

at startup and remain cleared until explicitly set with the /FLAGS switch

after a STAPT command unless set with the /FLAGS switch

with the ZFLAGS cnmmand.

No o!her cClmmar.ds. wit!,cut a /FLAGS sw;tch, atfe·::t the ~rate <'f the ilags: they reTJ1:•in as specified liy the Lst
/FLAGS switch. The flags are listed and described m Table 5-11.

Fla'.?~ c:>n be spccifie:! in ~-,~•11hinations. For example:
tH.AliS:LOE:IER:BOE
causes the program to loop on error. inhibit error reports. and sound the bell on error.

5-27

MAINTENANCE

Table 5-11

DRS Command Flags

Flag

Effect

ADR

Execute autodrop code.

BOE

Sound bell on error.

EVL

Execute evaluation (on diagnostics which have evaluation support).

HOE

Halt on error -

IBEt

Inhibit all error reports except first level (first level contains error type, number, PC, test and
unit).

IDR

Inhibit program dropping of units.

IERt

Inhibit all error reports.

JSR

Inhibit statistical reports (applies only to diagnostics which support statistical reporting).

IXEt

Inhibit extended error reports (those called by PRINTX macros).

LOE

Loop on error.

LOT

Loop on test.

PNT

Prin! test number as test executes.

PRI

Direct messages to line printer.

UAM

Unattended mode (no manual intervention).

control is returned to DRS command mode.

tError messages are described in Paragraph Section 5.12.1.

5-28

·j

MAINTENANCE

5.11.2 NIE Commands
NIE commands are typed in response to the prompt:
NIE> (A)?
The commands are interpreted from left to right; and you need type only enough characters to uniquely specify a
command. Command descriptions and examples follow.
Table 5-12

NIE Commands

Command

Description

HELP or?

Types a brief description of NIE commands.
Example:
NIE> (A)? H
or
NIE> (A)??

BUILD

This command is used to build the node table. It causes the exerciser to listen
for system ID mes~ges (broadcast by all nodes every 10 minutes). All such
identifying nodes
added to the node table. The· command stops if no new
nodes have been added for 10 minutes or 40 minutes have elapsed. The average
time for this command should be 15 to 25 minuteis.

are

It is possiblt! to miss a transmission within tlle 10 minute period. Therefore. if no
nodes appear in the table after a BUILD. wait 4 or 5 minutes and retry the BlHLD.
Example:
NIE> (A)? BU

CLEAR MESSAGE

This command resets message parameters to the default values.

CLEAR NODE/ADR

This command clears the specified node from the node table. The node can be
specified by either it~ 12-dit,it (hex) physical .-.duress or its logical name (from
the nodr. table). To fiud the lot1icai n ..me associ:ued with an a<ldre~,;. l:X•:~ut.; the
SHOW NODE command.
Example:
Clear a node using its Ethernet address:
NIE> (A) ? CL N/AA-00-04-f'F-FF·F·o
Clear a node using its logical name:
NIE> (A) ? CL N/N3

CLEAR NODE/ALL

This command clears the node table.
Example:
Clear all nodes:

5-29

MAINTENANCE

Table 5-12 (Cont.)

NIE Commands

Command

Description
NIE> (A)? CL NIALL
A cleared node can be restored to the node table with the UNSAVE command.

CLEAR SUMMARY

This command clears the summary table.

IDENTIFY ADR

Sends a Request ID message to the node specified by ADR. The returned system
ID parameters are typed.
Example:
NIE> (A) ? ID AA-00-04-FF-FF-FO _

MESSAGE/TYPE=
/SIZE=n/COPIES=m

This command allows the operator to select the current message parameters. Any
or all parameters can be changed. The default parameters are:
/rYPE=ALPHA/SIZE=5 l 2/COPIES= I.

The size of the message buffer is between 46 and 512 bytes. The number of copies
of each message sent to each node can be between 1 and 255 copies. The message
types are listed in Table C-5.
Examples:
Change type:
NIE> (A) ? M/T:ZERO
Change size:
NIE> (A) ? M/S:256
Change both size and type:
NIE> (A)? M/S:512.'T=ALPHA

MAINTENANCE

Table 5-12 (Cont.)
Command

NIE Commands
Description

NIE Test Message Types
·Content

Type

NODE ADRffYPE

ALPHA

!"#$%'( )*+,-./0123456789;:=?ABCDEFG etc.

ONES

All ones (11111111 ).

ZEROS

All zeros (00000000 ).

IALT

Alternating ones and zeros (10101010 ).

0ALT

Alternating zeros and ones (01010101 ).

CCITI

International Telegraph and Telephone Consultation
Committee pseudo-random test pattern.

OPERATOR
SELECTED

Operator selected pattern of less than 72. character~
using 0-9, A-Z, and spaces (not used in PATTERN)

Thi~ command allows the operator to ent.:r nodes into the node tahle. Nodes
are specified by t:1eir 12-digit(hex, Ethemc::1 physical addre~.,: anu can be funher
specified (hy ffYPE) to be eithi.:r target or assist (default = target).Before changing
a node's type, the node:: must tirs1 be cleared from the node table· (see CLEAR
command).
Examples:
Enter target node:

NIE> (A)? N AA-00-04-FF-FF-F0
or

NIE> (A)? N AA-00-04-FF-FF-F0ff
Enter as,;;ist node

NIE> (A)? N AA-00-04-FF-FF-F0/A
Change a target node to an assist node:

NIE> (A)? CL N/AA-00-04-FF-FF-F0
NIE> (A)? N AA-00-04-FF-FF-F0/A

5-31

MAINTENANCE

Table 5-12 (Cont.) NIE Commands
Command

Description

RUN <TEST>/PASS=nn

Causes the specified test to execute for nn passes (default PASS I). If nn 0,
the test will run indefinitely. Prior to running the test(s), the NODE command
should be used to enter the node addresses (taken from the node table) to be tested.
The LOOPPAIR test requires node pairs, specified as target and assist nodes. Each
test uses the currently selected values for message type, size, and copies. The tests
are as follows.

DIRECT-This test sends a loop direct message to all of the nodes in the node
table, waits for a response, checks returned data integrity, and reports any errors
to the operator. The message to the target node comprises encapsulated forward
and reply messages. The response from the target node comprises the same reply
message.
LOOPPAIR -This test sends transmit, receive, and full assisted loopback
messages, comprising encapsulated forward and reply messages, to the node
pairs in the node table. (See Figures 5-9, 5-JO. and 5-11.) In each case, the test
waits for a response and checks the data.
PATTERN - This te_st sends six different loop direct messages to each node in
the node table. Each of six message types (ALPHA, ONES, ZEROS. IALT. 0ALT.
CCITI-see Table 5-1 I) is sent to each node. Returned data is checked for errors.
ALL - This two-part test performs the most extensive check of the network. It
sends a loop direct message to each node in the node table. If this is successful,
the exerciser build~ an array of node pairs and send,; a full assisted loopback
message to each pair in the array.

Node Pair Array

1-2

2-3

3-4

4-5

5-6

1-3

2-4

3-5

4-6

5-7

!-4

2-5

3-6

4-,

1-5

2-6

3-7

1-6

2-7

6-7

1-7
RESP-The RESPONDER test is a section of code that provides loop-server
functions, such as: forwarding messages. answering console ID requests, and
transmitting a system ID every 8 to 9 minutes. This must be run to use the
DESQA as a loop assist or target node on the Ethernet. The other tests ignore
forwarding requests, and will not transmit console IDs.

5-32

MAINTENANCE

Table 5-12 (Cont.)
Command

NIE Commands
Description
Examples:

Run the DIRECT test for one pass:
NIE> (A)? RD
Run the DIRECT test for 5 passes:
NIE> (A)? R D/P:S
Run the DIRECT test for infinite passes:
NIE> (A) ? R D/P:0
Run the LOOPPAIR test:
NIE> (A)? R L
Run the RESPONDER test:
NIE> (A)? RR

NOTE
The onl~· way to end a large or infinite number of
passes is to type <CTRL>C. However, bt> careful:
type RESTART in response to DSR> (after the
<CTRL>C), to return to the NIE> prompt and
preserve the counters. If you type START in
response to DSR> after the <CTRL>C, you will
destroy al: summary statistics and counters.

5-33

MAINTENANCE

Table 5-12 (Cont.)

NIE Commands

Command

Description

SAVE

This command saves the contents of the node table. Both the PDP NIE and the
VAX NIE save the contents internally, not to a disk file.
Example:
NIE> (A)? SAV

UNSAVE

This command restores the contents of the node table from the internally saved
table.
Example:
NIE> (A) ? UNS

SHOW COUNTERS

Types the contents of the host node DEUNA internal counters. The counters are
described elsewhere in this manual.
Example:
ME> (A)? SH C

SHOW MESSAGE

Types the current message parameters for size, type. and copies.
Example:
NIE> (A) ? SH M

SHOW l'iODES

Types the contents of the node table.
Example:

NlE> (A} ? SH N
SU!\1\1ARY

This command types the summary table. The NIE maintains the following
infonnation about nodes to which it has sent messages:
RECEIVES SOT COMPLETE

RECEIVES COMPLETE

LENGTH ERRORS

DATA COMPARE ERRORS

BYTES COMPARED

BYTES TRANSFERRED

BYTES COMPARED represents data minus the loop-server protocol overhead;
therefore. it will be less than BYTES TRANSFERRED which represents data plus
loop-server protocol overhead.
Example:
NIE> (A) ? SUMM

5-34

MAINTENANCE

Table 5-12 (Cont.)

NIE Commands

Command

Description

EXIT

Returns control to the diagnostic supervisor (either VDS or DRS). The DRS
RESTART and CONTINUE commands cannot be used if the EXIT command was
used.
Used to leave the NIE.
Example:
NIE> (A) ? EXIT

5-35

MAINTENANCE

FORWARD

NI/ETHERNET

01 -

NI
EXERCISER
NODE

TARGET
NODE

NOTE: NUMBERS INDICATE SEQUENCE IN WHICH MESSAGES ARE SENT
MR-12465

Figure 5--6

Loop Direct Messages Test Path

r";'\

v,--.

NI/ETHERNET

!
......

•

., .• '[,
FOP.WARD I FOR c.1,,"\ f

NI
[XERCISER
r,OD::

FORWr i:irl
I
f:>

NODE A
LOOP ASSl~T

NOE ,,uMBERS INDICATE SEQUENCE I~ WHICH MESSAGES ARE SE~.T

Figure 5-7

Transmit Assist Loopback Message Test Path

5-36

L~EPL)

I
J\;QDE 8
TARGET

MAINTENANCE

----.....---I I0
REPLY

FORWARD

NI/ETHERNET

NI
EXERCISER
NODE

FORWARD

NODE A
LOOP ASSIST

NODE B
TARGET

NOTE: NUMBERS INDICATE SEQUENCE IN WHICH MESSAGES ARE SENT
MA 12467

Figure 5-8

Full Assist Loopback Message Test Path

----·0

------0
REPLY

~oRwARD

j FORWARD I FORWARD j

FORWARD

FORWARD_

I
I

NI
EXERCISER
NODE

FORWARD

I
REPLY

NODE A
LOOP ASSIST

NOTE: NUMBERS INDICATE SEQUENCE IN WHICH MESSAGES ARE SENT

Figure S-9

Receive Assist Loopback Message Test Path

5-37

I
NOC'~ !3
TAR(j[T

MAINTENANCE

5.12

ERRORS

5.12.1

Error Messages

The three levels of error messages that a diagnostic can issue are: general, basic, and extended.
5.12.1.1 General
General error messages are always typed unless the IER flag (XXPD+) is set. The format is as follows.

NAME TYPE NUMBER ON UNIT NUMBER TST NUMBER PC:xxxxxx
ERROR MESSAGE
where:

NAME
TYPE
NUMBER
UNIT NUMBER
TST 1\l 'MBER
PC:xxxxn

= diagnostic name
= error type (system fatal, device fatal, hard or soft)
= error number
= 0 through n (n is last unit in PTABLE; that is, device information table)
= test and subtest where error occurred
= address of error message call

5.12.1.2 Basic
Basic error messages contain some additional information about the error. These are always typed unless the IER
or IBR flag (XXPDTJ is set. These messages are typed after the associated general error message.
5.12.1.3 Extended
Extended eiTor messares contain supplementary error information, such as register contems or good/bad data.
These arc always typed unless the IER. IBR, or IXR flag is set. These messages are typed after the associated
general error message and any associated basic error messages.
Examples:
Lost packet error during LOOPPAIR testing:
CVNJA HRD ERR 00028 ON UNIT 00 TST 001 SUB 000 PC:064442

TIMEOL'.T OCCLRRED - LOOP MESSAGE TYPE - RECE1 1/E .\SS!ST
FAILING TARGET NODE ADDRESS: AA-00-03-00-00-00
FAlLil\G ASSIST NODE ADDRESS: AA-00-03-00-00-02
Lost packet error during PATTERN testing:
CVNIA HRD ERR 00028 O!'J U~IT 00 TST 001 SUB 000 PC:63730
TIMEOUT OCCURRED BEFORE LOOPBACK REPLY
FAILING NODE ADDRESS: AA-00-03-00-00-00
DATA PATTERN: ONES

5-38

MAINTENANCE

5.12.2 Other Error Messages

Error Message

Description

?ILL CMD-BAD SYNTAX

A command with an illegal character was typed; retype the command.

?INCOMPLETE

A required part of a command was omitted.

?NUMBER TOO BIG

The numeric string value in the command line was larger than 65535 (177777
octal).

?BAD RADIX

An 8 or 9 was typed when an octal string was expected.

5.13

PDP-11 FUNCTIONAL DIAGNOSTIC (ZQNA)

The Field Functional Diagnostic Program (ZQNA ??) tests the DESQA in Q-bus systems. It attempts to isolate
faults to the following Field Replaceable Units (FRUs).
•

DESQA. DEQNA or DELQA

•

Fuse

Refer to the XXnP+ User Manual for further information.

NOTE
Early versions of ZQNA ?? only work with
the DEQNA. ZQNAI is the tirst ,·ersion lo be
compatible with both DEQ!';A and DESQA.

NOTE
A successful pass of the self-test requires that the
DESQA be connected to a valid Fthernet network,
or an external loopback connector. For Thickwire
use th'! Bulkhead loopback connector (12-22196021 or alternatively an 84080 Ethernet tester. For
Thinwire, the "T" piece with two terminators (1226318-01) attached should be connected to the BNC
connector.

5.13.1 ZQNA?? Environment
Tests are executed under the supervision of the Diagnostic Runtime Services (XXDP+ ), and controlled by an
operator from a cor.solc i_hard copy or video).
5.13.2 ZQ~A ?'? Test Descriptions
The setup tests are describcu below.
•

•

Basic operation tests:
I.

Device self-test

Station address verification

BD code verification

Internal Extended Loopback Test
4.

Rx/fx descriptor mechanism verification
5-39

MAINTENANCE

•

Q-bus NXM test

Q-bus OMA interface (transmit) test

Q-bus OMA interface (receive) test

Internal extended loopback path stuck-at test

Extended memory test

Setup mode loopback tests

10. Setup mode loopback test
•

Internal loopback tests

11. Ethernet Address recognition test
12. Ethernet Address recognition mode test
13. Overflow status check
•

External loopback tests

14. External loopback path verification test
15. Carrier bit test
16. Sanity timer test
5.13.3 ZQNA'!? Error Reports
A diagno<;tic can issue general and specific types of error messages.

General error mc:,;-,ages arc always printed .mless the IBE and/or IER flag is set. The information shown is:
1

NAME =Diagnostic name
ER_TYPE =Error type (all errors are hard errors)
ER_NO = Error number
UNIT_NO =0
TEST_NO =Te:.l and su'btest where error occurred
:>C_ADDR cc ;. rograrn counter contents.
General error messages may include two sublevels:
Basic error me.uagc.\ an: printeJ after the associated general error message, and contain some :-!dd1tiomtl
information about the error. They are always printed unless one or more DRS error flag; (IBE. !XE. IER 1
are set.

•

Extended error messages are printed after the associated general error message and any associated basic
error messages. [:;tended error messages contain additional error information, such as register content', or
good/bad data. They are always printed unless either the IXE or IER flag (or both) is set. The format of a
typical extended error message is shown in Figure 5-2.

Specific error messages are defined as needed. The following are possible error messages.
Device fatal error messages:
CSR REGISTER FAILED TO RESPOND
NO INTERRUPT FROM DESQA

Return status messages:
TRANSMIT STATUS ERROR

5--40

MAINTENANCE

RECEIVE STATUS ERROR
CSR STATUS ERROR
5.14 MICROVAX DIAGNOSTIC MONITOR (MDM)
MOM diagnostics are based on a functional testing approach where the objective is to gain the maximum
coverage and to isolate OESQA faults down to the Field Replaceable Unit (FRU).

The recommended test strategy for identifying Field Replaceable Units (FRUs) that are causing a fault is as
follows.
1.

Check the. MOM configuration listing for the correct DESQA details.

Run the Verify tests (FUNCTIONAL and EXERCISER) to check DESQA functions.

Run the Field Service Functional tests and the utility tests if yet more advanc~ and detailed fault-finding is
essential to identify a faulty FRU.

5.14.1 MDM Environment
MOM test commands require loopback connectors in the following cases.

•

Tests in functional mode and exerciser mode, including TEST CABLES (Utility l) require one of~
In Thickwire Mode- Bulkhead loopback connector (order number 12-22196-02)
Cable and Ethernet transceiver to provide external loopback.
In Thinwire Morle- "T" piece anJ two tenninators (order number 12-26318-0l)

•

TESTLOOP (l.'tility 2) and ECHOSERVER (Utility 3) enable two MicroVAX systems to send packets to
each other.

The Verify tests (FUNCTIO!\AL .:1nd EXERCISER) J.J not require any loopbad.. connections.
The operator is prompted whenever a loopback cable/connector is required.
5.14.2 MDM Service Test Descriptions
5.14.2.1 Verify Mode Tests
MDM Verify mode is dt!s:gned for use by untrained personnel. It prohibits o~rator intervention during testing.

The sequence of tests is as follows.

MAINTENANCE

TESTl

Initialise controller Test bulkhead assembly fuse
(If Normal mode) Invoke self-test
Possible failure: nonexistent memory interrupt (NXM)

TEST2

Send several setup packets
Test BDL handling
Test interrupt ability
Test DMA

TEST3

Loop packets in internal loopback mode
Test address decoding logic

TEST4

Loop packets back in internal extended loopback mede with different data types (zeros, ones,
alternating. CCITT. and so on)
Test internal RAM Tests long packet logic

TESTS

Loop packets in internal extended loopback mode
Use chained descriptors and multiple buffers

TEST6

The device is placed in different station address filtering modes and packets are looped through
using imernal loopback. Depending upon the mode and the station address, the packet may or
may not be re<.:eived.
Test promiscuous filtering
Test multi-<.:ast filtering
Te~t normal tilt.:~ing

TEST7

(Normal mode only) Verify the operation of Extended setup packet by looping several back
through the DESQA.
Verify correct processing of the MOP element blocks

5.14.2.2 Field Service Functional Tests
Field service tests are clesigned for operators experienced in the testing and debugging of DIGITAL equipment.
The l>Jlc'ra:, •: na, '1t asked tc ,nak.: mir,or physical alttratif)ns. including mounting an external loopback
co111w~·1u;.

Thi~ diagnostic has one field service test. FIELD_TEST, which uses external loophack to te!'.t the bulkhead
loopback conne.::tor or the DESQA-cable-transceiver loop. (Internal loopback i~ test.::d m the MODi: routim.:s. l

TESTI

Send packet!-. using external loopback mode

5.14.2.3 Field Sen-ice Exerciser
The exerci,er i~ designed to stre,s the MicroVAX syst-~,n. creating a simulation of nonnal system operation. By
executmg sewral exercisers together. on the same MicroVAX S)stcm. it is expected that any marginality in the
system design and operation can be isolated and corrected. The EXERCISER does not require the operator to
modify the system.

TESTl

Performs the setup test

Internal loopback test
Internal extended loopback test

5-42

MAI1''TENANCE

Allocate and deallocate buffers
5.14.3 MDM Utilities
The utilities are designed for the sophisticated troubleshooter, who needs to configure the system for specific tests.
These utilities, using already verified circuits, produce test scaffolds to track down failures in the cables anached
to the DESQA.

Utility 1

TESTCABLES
Repeatedly prompts the user to connect a loopback connector/cable at any point in the
communications path in order to isolate an error to a particular segment.

Utility 2

TESTLOOP

Sends packets to an echo server and expects to receive those packets, error free, back over
the Ethernet.
Utility 3

ECHOSERVER
Acts as an echo server for the TESTLOOP utility.

Utility 4

NIE

5-43

MAINTENANCE

5.15 DEC/XU EXERCISER
The DEC/X 11 Exerciser exercises one DESQA at maximum activity rates. It transmits and receives randomlength packets (using either 18- or 22-bit physical address space). The DESQA transmits and receives the same
packet.
One pass of the exerciser consists of 1000 iterations of transmitting a packet, receiving a packet, and comparing
the contents of the transmit packet to the receive packet. Packet length is random for each iteration. The transmit
and receive status words and CSR status are all checked for correct contents.
The DESQA is dropped from further testing if any of the following occurs.
•

The DESQA does not reset properly.

•

The CSR and/or the receive and/or transmit status word(s) are in error.

•

A hard error occurs.

•

A transmit and/or receive interrupt is not generated.

•

The transceiver is disconnected while in external loopback mode.

Internal extended loopback mode is the default mode of operation.
You must set the sanity timer switches S4 to enable the timer before executing the sanity timer test. When sanity
timer testing is complete, restore the switches to the positions they occupied before the test.

5.15.1 Environment
It is assumed that, prior to nmning this exerci~er, both the DESQA citizenship (CQ) test and field functional test
have been successfully run. The default parameters are:
Device address: 17774440
Interrupt Vector. 700

BR level: 4
Number of devices:
The hardware switch settings are:
Mode switch S3: OPEN to enable DEQNA-lock mode
•

Opti0n switch S4: OPEN to enable the sanity timer at power up.

To run th.: e\er:.:iser in external loopback in 1l1ichvire tvfode, lhe DESQA nnde, test must Lr. cunnected to the
transceiver, or the external loopback connector must be connected.
In the 1l1inwir.:- Mode.the taminator~ must be c,mnected.
The options for Software Kegister 1 (SR I) bit~ 0 and I are described in Table 5- l 3.

5-44

MAINTENANCE

Table 5-13

DESQA DEC/Xll Exerciser Software Register Bits

BIT 1

BIT0

Description

Clear

Exerciser runs in internal extended loopback mode (default). The network is not
needed.

Set

Exerciser runs in external loopback mode. A valid network or external loopback
connector is required.

Clear

Print error messages.

Set

Do not print error messages.

5.15.2 Command Descriptions
To set external loopback mode. type the following commands.
MOD QNAA0 16 <RETURN>
1 <RETURN>
To test a DESQA in the second slot (address 17774460), type the following commands after the exerciser has
been loaded:

MOD QNAA0 6 <RETURN>
174460 <LINE FEED>
70J <RETURN>
For additional infonnation. refer to the DEC/XI 1 User Manual.

5-45

APPENDIX A
IC DESCRIPTIONS

A.I SCOPE
This appendix contains some basic data on the main Integrated Circuits in the DESQA. The sections are as
follows:

Section A.'2
Section A.3
Section A.4
Section A.5
Section A.6
S.::cti()n A.7

68000 Microprocessor
Q-Bus Interface Controller(QIC)
QNA2 Q-Bus Network Arbitrator
AM7990 Local Area Controller for Ethernet (Lance)
Al\17991 Serial Interface Adapter(SIA)
DP8392 Thinwire Ethernet Transceiver

Eat·h section include~ the following (where relevant):

Overview.

'2.

Signals and pinout.

Addressing, memory structures, and registers.

For more detailed information, refer to the manufacturer's data sh~ets. Other components on the DESQA board
are well described in the standard references. and are not included here.

NOTE
J'iot all feature~ described in these sections arc used
by the DESQA.

A-1

IC DESCRIPTIONS

A.2

68000 MICROPROCESSOR

A.2.1 Overview
The 68000 is a 16-bit microprocessor which has a 32-bit internal architecture. The 68000 is located on the top
side of the DESQA board. Its main features are:

•

16-bit asynchronous data bus

•

23-bit asynchronous address bus, capable of addressing 16 Mbytes in conjunction with the data strobe signals
UDS and LOS

•

Eight 32-bit data registers
Seven 32-bit address registers

•

Memory-mapped 1/0

•

Compatibility with 6800-series peripheral ICs
Single +5V power supply

•

Mounted in a PLCC package.

The internal registers of the 68000 are shown in simplified fonn in Figure A-1.

A-2

IC DESCRIPTIONS

\4-.,...,-

DO
D1
D2
D3

EIGHT
DATA
REGISTERS

D4
05

D6
D7
31

00
AO
A1
A2
SEVEN
ADDRESS
REGISTERS

A3
A4
A5,
A6
00

[
31

TWO
SYSTEM
STACK
POINTERS

]Al
A7

i
I I I I
15

STATUS

TnACE MODE j
SUPERVISORY MODE
INTERRUPT MASK

PRCGRAI\~
cou~J:-Er
11

l l l I II I I II I I
I I I

EXTEND-~~
NEGATIV~
ZERO
OVERFLOW
CARRY
R[17.a1

Figure A-1

68000 Internal Registers
A-3

IC DESCRIPTIONS

Table A-1

68000 Signal Descriptions

Address and Data Bus

Pio

Name

Seoset

Des:riptioo

01:05
54:64

0<04:00>
0<15:05>

1/0 Hi

Data Bus Lines DO:D15. 16-bit bus to transfer words or bytes.
Lines DO:D7 are also used to receive a vector number during an
interrupt-acknowledge cycle.

29:32
33:48
50:52

A<Ol:04>
A<05:20>
A<21:23>

0 Hi

Address Bus Lines Al:A23. 23-bit bus to address 16 MBytes in
conjunction with Data Strobes UDS and LDS. Lines A3:Al> are also
used to signal the interrupt level while an interrupt is being serviced.
In the DESQA, A20 selects the firmware ROM.

Asynchronous Bus Control
Pin

Name

senset

Description

OLo

Address Strobe to indicate that a valid memory address is on the
address bus.

07
08

UDS
LDS

OLo

Data Strobes to indicate whether data for transfer is on the upper, the
lower, or both bytes of the data bus. (No Connection)

R/W

OHi

Read to indicate direction of data.

Write transfer to the data bus latches.

I Lo

Data Transfer Acknowledge to complete a data transfer. The data bus
cycle is extended until DTACK so that slow devices or memories can
synchronise with the cycle.

DTACK

t The Sense column is used to show if a signal is an input I or output O from
the chip. Logic High (Hi) or Low (Lo) states are shown for signal assertion.

A-5

IC DESCRIPTIONS

A.2.2 Signals and Pinout
The signals to and from the 68000 microprocessor fall into logical groups. The functions, signals and pinouts of
these groups are described in Table A-1, and shown in Figure A-2.

TOP VIEW

BUS
CONTROL
LINES
BUS
ARBITRATION---LINES

10MHz
HALT
RESET

M6800
PERIPHERAL
INTERFACE
BUS ERROR--------►
INTERRUPT
PRIORl1Y
LINES
FUNCTION---------CODE
BITS

----------

D4
D3
D2
D1
DO

1
2
3
4
5

AS
UDS
LDS

R/W

7
8
9

DTACK

BG
BGACK

12
BR 13
vcc 14
CLK 15
GND 16
HALT 17
RES 18
VMA 19
E 20

VPA
BERR
IPL2
IPL1
IPLO
FC2
FC1
FCO
A1
:\2
A3
A4

Figure A-2

22
23
24
25
26
27
28
29
30
31
32

64 D5
63 D6
62 D7
61 D8
60 D9
59 D10
58 D11
-57 D12
56 D13
55 D14
54 015
53. vss
52 A23
51 A22
50 A21
49 vcc
48 A20
47 A19
46 A18
45 A17
44 A16
43 A15
42 A14
41 A13
40 A12
39 A11
38 A10
37 A9
36 A8
35 A7
34 AG
33 A5

68000 Pinouts

A-4

~
A01 :23 .

IC DESCRIPTIONS

Bus Arbitration (Not used)
Pin

Name

senset

Description

I Lo

Bus Request from a device for bus control.

OLo

Bus Grant gives control of the bus.

BGACK

I Lo

Bus Grant Acknowledge from a device confirms that it has taken
control of the bus.

I Lo

Interrupt Priority Lines WL<2:0> encode the priority of an
interrupting device or process in the range O (no interrupt) to 7
(highest priority). IPL2 is the MSB.

OHi

Function Code Lines FC<2:0> indicate the state (user or supervisor)
and type of cycle (data, program, interrupt) executed:

Interrupt Priority

23
24
25

IPL2
IPLI
IPL0

Function Code

28
27
26

FC0
FCl
FC2

FC2

FCI

FCO

State

Cycle

User

Reserved

User

Data

User

Program

User

Reserved

Supervisor

Reserved

Supervisor

Data

Supervisor

Program

Super,i-,or

Interrupt

0
0

-----

t The Sense column is used to show if a signal is an ,input I or output O from
the chip. Logic High (Hi) or Low (Lo) states are shown for sip:nal assertion.

A-6

IC DESCRIPTIONS

M68000 Peripheral Interface
Pin

Name

senset

Description

VPA

I Lo

Valid Peripheral Address indicates that the device or memory
addressed is type M68000 and that data transfer should be
synchronised to Enable (E).

VMA

0Lo

Valid Memory Address indicates, in response to VPA, that a valid
address is on the address bus and that the 68000 is synchronised to
the Enable Signal. (Not used.)

0Hi

Enable is the standard enable clock signal for M68000 systems. (Not
used.)

System Control· and Timing
17

HLT

1/0 Lo

Halt is a bidirectional line that either receives an external halt from.
or sends a halt signal to, external devices. When generated internally
the instruction halts the processor. When HLT is assened by an
external device, the 68000 halts at the end of the current bus cycle.
A halted 68000 can be restarted only by an external Reset.
HLT also interacts with RES and BERR.

RESET

1/0 Lo

Reset is a bidirectional line that either receives an extemal re-.et from.
or sends a reset signal to. external devices. When generated internally
the instruction resets all external devices without affecting the 68000.
When RES and HLT are asserted by an external device. all devices
are reset and the 68000 executes its reset veci.or at interrupt level 7
(non-ma~kable: highest priority).

BERR

I Lo

Bus Error terminates the current bus cycle due to an error. If HLT
is asserted, the 68000 prepares to rerun the cycle, and does so when
HLT is negated. If HLT is negated, the 68000 executes its bus error
vector. (Pullup resistor.)

CLK

I Hi

Clock input from the QNA2. frequency 10MHz.

Power Supply
-------------- - - - - - - ---·--·-- -

Name

14,49

Vee

+5\' Power rail.

16,53

Vss

God Earth rail.

sem,et

---· - - - - - - - - - - - - - - - -

Description

t The Sense colum:, is used to show if a signal ;s an input I or output 0 from
the chip. Logic High (Hi) or Low (Lo) -;tates are shown for signal a,sertion.

---------------------------

A-7

IC DESCRIPTIONS

A.2.3 Addressing
The 68000 uses an asynchronous bus structure with separate address and data buses. The processor executes read
and write cycles to transfer bytes and words from and to shared buffer RAM, using the function code and bus
control signals to control the transfer.
The Test and Set (TAS) instruction operates on bytes only to provide interprocessor communication. The
instruction is executed by an indivisible read-modify-write cycle; during this cycle AS (Address Strobe) is
asserted throughout.
Bus arbitration is controlled using the Bus Arbitration signals to determine whether the 68000 or an external
device is acting as bus master.

IC DESCRIPTIONS

A.3

Q-BUS INTERFACE CONTROLLER (QIC)

A.3.1 Overview
This section describes the DIGITAL Q-Bus Interface Controller (QIC). It is intended only to describe the
functions of the QIC that are used in the OESQA module. It is not a complete QIC specification; nor does it
include details of Q-Bus operations.
The QIC is a general-purpose Q-Bus Interface Controller, which provides complete Q-Bus slave control logic.
The QIC is packaged in an 84-pin plastic leaded chip-carrier (plcc). Together with 2 8641-2 and 4 DC021
transceivers, the QIC forms a complete Q-Bus interface design.
The OESQA supports both block-mode and non-block mode OMA on the Q-Bus.
On the Qbus side. the QlC supports control OMA (based on Buffer Descriptor Lists) and data OMA, using
block-mode to achieve the highest possible speeds.
On the backport side. the QIC uses OMA to transfer data to and from sh~ed buffer RAM and on-board registers
(if supported by the module). The backport has 16 data/address lines and up to four control lines. The main
controller can program the QIC registers and initiate OMA transfers to and from the Q-Bus.
Internally the QIC provides:
•

Complete Q-Bus slave control logic

•

1/0 page addressing. with: slave address matching and programmable base-address register.

•

DMA arbitration and control, both block-mode and non-block-mode
22-bit Q-Bus OMA address register/counter
15-bit DMA word-count register
16-bit backport DMA address register/countt:r a,1d control
Interrupt control

•

Non-existent-memory (NXM) timeout

•

Holdoff timer to separate DMA requests so that mher units can access the Q-Bus
Ability to initiate host reboot.

The architecture of the QlC is shown in the block diagram Figure A-3.

A-9

IC DESCRIPTIONS

BACKPORT BUS

Q-BUS

Q-BUS MUX

BUFFER 1

SLAVE DATA
LATCH
BUFFER 2

ADDRESSING CONTROL
CONTROL ADDRESS (LO)
CONTROL ADDRESS (HI)

DATA

BACKPORT ADDRESS

MUX

BYTE COUNTER
DATA ADDRESS (LO)
DATA ADDRESS (HI)
ATTENTION REGISTER
MODE REGISTER 2

...___ _ _ _ _ _ _ _ _ _._ADDRESS
MUX

1/0 BASE ADDRESS
MODE REGISTER 1

RE174J

Figure A-3

QIC Block Diagram
A-10

IC DESCRIPTIONS

A.3.2 Signals and Pinouts
The signals for each pin of the QIC are shown in Figure A-4, and the signals are described in Table A-2. Some
of the QIC signals share pins on the IC, and the circuit designer will have chosen one function or the other.
DESQA does not use all the functions provided by the QIC. Unused outputs are not connected; unused inputs are
tied high or low as appropriate.

A-11

IC DESCRIPTIONS

TOP VIEW

0-BUS INTERFACE
(PINS 1-42)

GND
DAL21

Q-BUS DATA/

DAL20
DAL19
DAL18
ADDRESS LINES
DAL 17
DAL16
OMA CONTROL RDMGI
INTERRUPTS----► RIRQ5
Q-BUS
RREF
ARBITRATION RREPLY
OMA CONTROL----• RDMR
OMA CONTROL---- TDMR
0-BUS ABITN TREPL Y
INTERRUPTS------ TIAKO
0-BUS CONTL DC21 IN
0-BUS DATA/
DAL 15
DAL 14
DAL13
ADDRESS LINES
DAL 1 2
GND

vcc

Q-BUS DATA/

ADDRESS LINES

BUS RESE-:- BUS RESET Q-BUS DATAI

ADDRESS LINES
BUS RESET OMA CONTROL
INTERRUPTS

DAL 11
DAL10
DAL01
DALOO
DAL09
DAL08
DAL07
DAL06
RINIT
TEST
RDCOK
DAL05
DAL04
DAL03
DAL02
TDCOK
TDMGO
TIRQ4
NC
GND

84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

Q-BUS INTERFACE
(PINS 74-84)
BACKPORTINTERFACE
(PINS 42-73)
GND
RIAKI

WTBT
BS7
DOUT

-----► 0-BUS

INTERRUPTS

vcc

----ARBITRATION
-a-BUS
DIN
-coNTROL
SYNC
LINES
TSACK
- - - - OMA CONTROL
UNITSEL UNIT
UNITSEL2 SELECT
TRANS
BPDAL
BPDAL
BPDAL
BACKPORT DATA/
BPDAL
BPDAL
ADDRESS LINES
BPDAL
BPDAL
BPDAL

BPDAL
BPDAL
BPDAL
BACKPORT DATA/>
BPDAL
BPDAL
ADDRESS LINES
BPDAL
BPDAL
BPDAL
BPRDWR if PORT CO NTL
UQSTHAP ◄---···· f\mDE:
BURST
SETTING
RESET
ATTN
INTER Rt IPTS
SPAS
- - - B'PORT COrffL
BRPLY
MREQ
MEMORY
MAG~
.__._ ACCESS
CLOCK
- - - - - 201\1h,:
RIRQ7
-

vcc

R(1744

Figure A-4

QIC Pinouts

·A-12

IC DESCRIPTIONS

Table A-2 QIC Signal Descriptions
QIC to Q-Bus Interface: Address and Data Bus Control
02:05
06:07
17:20
23:24
25:26
27:30
34:37

DAL<21:18>
DAL<l7:16>
DAL<l5:l2>
DAL<ll:10>
DAL<0 I :00>
DAL<09:06>
DAL<05:02>

1/0 Hi

Data/Address Lines, connected as follows to the DC02l transceivers:
DAL<l5:08> to DC02l number 3;
DAL<2l:20,07:02> to DC02l number 2;
DAL<l9:16,0l:OO> to DC021 number l;
DAL<OO> is held low for data DMA, high for control DMA transfers.
DAL<2 l: 18> are Address lines.
DAL<l7:16> are Memory parity/Address lines.
DAL<l5:00> are Data/Address lines.

QIC to Q-Bus Interface: DMA Control
Pin

Name

sensef

Description

RDMGI

I Hi

Receive DMA Grant In (with pulldown resistor), from the Q-Bus
signal BDGMl (receive), using DC021 number I.

RDMR

I Hi

Receive DMA Request, which connects to the Q-Bus signal BDMR
(receive), using 8641 transceiver number 2.

TDMR

0 Hi

Transmit DMA Request, which is sent to the Q-Bus signal BDMR
(transmit). using 8641 transceiver number 2.

TDMGO

OHi

Transmit DMA Gr.int Out. which is sent to the Q-Bus signal BDMGO
(transmit), using 8641 mmsceiver number l (with a pulldown
resistor).

TSACK

OLo

Transmit DMA Selection Acknowledge, which controls the direction
of transfer of DC02 l number 4.

t The Sense column is used to show if a signal is an input I or output O from
the chip. Logic High (Hi) or Low (Lo) states are shown for signal assertion.

A-13

IC DESCRIPTIONS

QIC to Q-Bus Interface: Interrupts control
Pin

Name

senset

RIRQ5

I Hi

Description

Receive Interrupt Request Level 5 (with pulldown resistor), from the
Q-Bus signal BIRQ5 (receive). using DC021 transceiver number I.

TIAKO

OHi

Transmit IntemJpt Acknowledge Out, which is sent to the Q-Bus
signal BIAKO, using DC021 number 4 (with a pulldowrr resistor).

TIRQ4

0 Hi

Transmit IntemJpt Request Level 4, which is sent to the Q-Bus signal
BIRQ4 (transmit), using 8641 transceiver number 2.

TIRQ6

0 Hi

No connection.

RIRQ7

I Hi

Tied inactive low.

RIAKI

I Hi

Receive IntemJpt Acknowledge In (with pulldown resistor), from the
Q-Bus signal BIAKI, using DC021 number 4.

RIRQ6

I Hi

Receive IntemJpt Request Level 6 (with pulldown resistor). from the
Q-Bus signal BIRQ6 (receive), using DC021 number l.

QIC to Q-Bus Interface: Address and Data Bus Control
Pin

Name

senset

Description

RREPLY

I Hi

Receiw Reply. from the Q-Bus signal BRPLY (receive). using 8641
transceiver number 2.

TREPLY'

0 Hi

Transmit Reply, which is sent to the Q-Bus signal BRPLY (transmit),
using 8641 transceiver number 2.

BS7

1/0 Hi

Bank Select 7 (tristate signal), which connects to the Q-Bus signal
BBS7, using DC02 l number 4.

WTBT

1/0 Hi

Write Byte (tristate signal). which connects to the Q-Bus signal
BWTBT. using DC021 number 4.

DC021l!\

0 Hi

DC021 Input c::mtrols the direction of transler of IY'0'.11 nun,her~ I
to 3.

QIC to Q-Gus lnterl'are: Ac!drcss and Data Rus Control
Pin

l'liame

senset

Description

SY:\C

I/0 Hi

Synchronise (tristate signal). which connects to the Q-Bus <;ign1l
BSYNC. using DC021 number 4.

1/0 Hi

Data Input (tristate signal), which connects to the Q-Bus signal BDIN,
using DC021 number 4.

1/0 Hi

Data Output (tristate signal). which connects to the Q-Bus signal
BDOUT. using DC021 number 4.

DOUT

t The Sense column is used to show if a signal is an input I or output O from
the chip. Logic High (Hi) or Low (Lo) states are shown for signal assertion.

A-14

IC DESCRIPTIONS

QIC to Q-Bus Interface: Bus Control
Pin

Name

senset

Description

RREF

I Hi

Refresh, from the Q-Bus signal BREF, using 8641 transceiver number
1.

RINIT

I Hi

Receive. Initialise, from the Q-Bus signal BINIT, using 8641
transceiver number 1. This signal is asserted each time the Q-Bus
host executes a Reset instruction.

RDCOK

I Lo

Receive DCOK, from the Q-Bus signal BDCOK (receive), using 8641
transceiver number 1. When RINIT is active at the same time. the
QIC asserts ATTN to alert the 86000 microprocessor.

TDCOK

OLo

Transmit DCOK, which is sent to the Q-Bus signal BDCOK
(transmit), using 8641 transceiver number 1.

QIC to Q-Bus Interface: Unit Select

74
75

UNITSEL<2>
UNITSEL<l>

I Hi

Unit Select pins at powerup is reflected in mode register 2; bits
<15:14> UNITSEL<l> is connected to a test point to provide an
external select facility.

.EXTSEL

I Hi

External Select. This pin is used to request QIC access to the
ba.:kp,in memory

QIC to Q-Bus Interface: Power
*""-"

Name

1, 21,
42, 64,
84

Gnd

Signal ground.

22,43,
63

Vee

+5V Power rail.

senset

De~cription

QIC to Backnort Interface: Add, css aad Data Bus

-----Pin

l'iame

senset

Description

72:(,5

BPDAL<l5:08>

I/0 Hi

BackpoI1 Data/Address Line~ 1_trista1e;

62:55

BPDAL<07:00>

t The Sense column is used to show if a signal is an input I or outpt:, 0 from
the chip. Logic High (Hi) or Low (Lo) states are shown for signal assertion.

A-15

IC DESCRIPTIONS

QIC to Backport Interface: System Control and Timing
Pin

Name

senset

Description

TEST

I Lo

Test mode. Tied inactive high.

CLOCK

UQSTRAP

20MHz TTL clock, shared with QNA2.
I Hi

Tied inactive low.

QIC to Backport Interface: Memory Access
47

MREQ

0 Hi

Memory Request, sent to QNA2 during backport OMA to request
access to shared buffer RAM, and negated one clock ·pulse after
MACK is received in response.

MACK

I Hi

Memory Acknowledge received in response to MREQ during
backport OMA. This enables both the OMA address onto the backport
bus, BPOAL<l5:00>, and also BPAS. BPROWR, and BPRPLY. This
signal must be synchronous to the 20MHz clock.

QIC to Backport Interface: Backport Bus Control
Pin

Name

senset

Description

BPAS

1/0 Lo

Backport Address Strobe (tristate, with pullup resistor) indicates that
a valid address on BPOAL<15:00> can be latched on the as~erting
edge.

BP1<.D\VR

1/0 Hi
LO

Backport Read/Write (r, istate signal) Lo indicates the direction of
transfer. BPROWR is asserted through most of the ttansft:r cyde. In
Read operations, BPROWR is negated after the QIC latches the data,
so that the backport master can start reading.

t The Sense column is used to show if a signal is an input I or output O from
the chip. Logic High (Hi) or Low (Lo) states are shown for signal assertion.

A-16

IC DESCRIFl'IONS

QIC to Backport Interface: DMA Control
Pin

Name

senset

Description

BPRPLY

1/0 Hi

Tied high.

DMARDY

I Lo

This pin is used to indicate to the QIC that backport transfers for
DATA OMA should not be attempted, when negated (high). Host l/0
page accesses, vector fetches and control OMA are unaffected by the
state of this pin.

TRANS

1/0 Hi

Not used. Tied low.

QIC to Backport Interface: Interrupt Control

Name

senset

Description

ATTN

OLo

Attention asserts an interrupt to the 68000, in order to indicate an
error or a completion.

RESET

OLo

Not used.

t The Sense column is used to show if a signal is an input I or output O from
the chip. Logic High (Hi) or Low (Lo) states are shown for signal assertion.

A-17

IC DESCRIPTIONS

A.4 QNA2 Q-BUS NETWORK ARBITRATOR
A.4.1 OVERVIEW
The QNA2 is packaged in a 68-pin, surface-mounted plastic leaded chip-carrier (plcc). The device is created with
an LSI logic 2220-cell gate array.
The QNA2 controls access to the multiport memory system on the a backport bus. It arbitrates between requests
from the QIC, the LANCE, and the 68000 microprocessor, granting access rights to these three devices on a
shared time basis.
Access is granted according to the following order of priority:
l.

QIC

68000 microprocessor

LANCE.

The QNA2 implements the following control functions:
•

Arbitration of access rights for QIC, 68000 microprocessor and LANCE

•

Read/Write control logic for RAM and ROM accesses

•

Read/Write control logic for QIC registers and LANCE registers
Read/Write control logic for QNA2 register:.

•

LANCE and QIC OMA control

•

68000 control.

The architecture of the QNA2 is shown in the block diagram.

68000
PROGRAMCONTROL

SEQUENCE
CONTROL

CHIP
SELECT

20MHz · CLOCK
ADDRESS
DECODE

10MHz ...,_

!
DIAGNOSTIC
LEDS

X
::::>
~

MODULE
CONTROL -

68000
B/D ROM
BUFFER RAM
BACKPORT
LATCHES
QIC
LAi-JCF
ETHERNET
INTERFACE

BPDAL<0.15:1 >

CSR

Rl1745

Figure A-5

Q".-A2 Block Diagram

A-18

IC DESCRIPTIONS

A.4.2 SIGNALS AND PINOUT
The QNA2 controls all the gating on the DESQA board. It employs combinational logic to examine the access
requests asserted on the backport bus, and then executes the appropriate control function for the request with the
highest priority.
The three control sequences implemented by the QNA2 are:
I.

QIC OMA transfers:
a.

Read/Write access to the QNA2 CSR.

Read/Write access to shared RAM.

Read only access to Station Address ROM.

68000 microprocessor:
a.

Read/Write access to shared RAM.

Read/Write access to QIC and QNA2 registers.

Read/Write access to the LANCE.

Read access to finnware ROM.

Read access to Station address ROM.

LANCE OMA transfers:
a.

Read/Write access to shared RAM.

A.4.2.1 QNA2 Signal Descriptions •
Table A-3 QNA2 Signal Dei.criptlons

Backport Interface: Address and Data Bus

Name

02:04

BPDAL<l3:15>

47:50

BPDAL<00:03>

BPDAL<l5:00> <lata word transfers;

53:56

BPD\L<08:li>

BPDAL<07:00> contro; byte transfers;

63:67

BPDAL<04 :07 .12>

BPDAL<00.15:0!::-> Backport DMA.

Seoset
1/0 Hi

W:scciptioo
Backport Data/Address lines, used as follows:

t The Sense column is used to shC'w it a signal is an input I or output O from
the chip. Logic High (Hi} or Low lLo} states are shown for signal assenion.

A-19

IC DESCRIPTIONS

Backport Interface: QIC
Description

Name

MREQ

QIC request for access to RAM or to QNA2 registers. No
synchronisation needed since QIC and QNA2 share a 20MHz
clock.

MACK

Acknowledge MREQ.

BPRDWR

1/0

Hi/Lo

Baclcport Read/Write indicates direction of data transfer. Hito-Lo transition terminates a slave read access by enabling the
tristate gates.

BPAS

Backport Strobe latches a QIC register address for a slave read
or write.

Senset

-...,,

Module Control and Timing
Pin

Name

CLOCK

INIT

JMPR3

Senset

Description

20 MHz clock (shared with QIC).

Initialise pulse clears all register bits and output functions. and
sets the contFol sequencer to idle.

Select access time for 68000 ROM:
Hi= 150ns.; Lo= 250ns. Preset to Lo. If Hi. DTACK is
generated 100 ns. earlier.

JMPR2

Select Option, connected to option switch S4 of the 5-way
switchpack, and reflected in IR bit 10. For DEQNA-Lock mode
(mode switch S3=0): select sanity timer. For Normal mode
(mode switch S3=1): select MOP Remote Boot.

JMPRI

Select Mode, connected to switch S3 of the 5-way switchpack.
and reflected in IR bit 5. S3=1=Normal mode: S3=0=DEQNALock mode.

OINIT

The state of this pin is the inversion of CSRbit I (SR;

t TI1e Sc-n~e column is u:-eJ to show if a signal is an input I or output O fron,
rhe chip. Logic High (Hi) or Low (Lo) states are shown for sirnal a-;,-:rti,>i1.

A-20

,~\

IC DESCRIPTIONS

Diagnostic Signals
Pin

Name

LED3

Diagnostic output to LED2 driver.

LED2

Diagnostic output to LEDI driver.

LEDi

Diagnostic output to LEDO driver.

ELOOP

Ethernet Loopback, reflects CSR bit 9 and selects the MSB of
Station Address ROM.

Senset

Description

Ethernet Interface
Pin

Name

Senset

Description

RENA

Receive Enable signal from the SIA.

FUSE

Power indicator from the BULKHEAD FUSE. lbis signal is
fed directly to CSR bit 12.

Backport Interface: LANCE

."'-'

.Name

LADR

LANCE Address Select, (re)set each time ADS (Addreso;
Strobe) is asserted with ADR21 (un)set.

LREAD

1/0

Hi/Lo

LANCE Read indicates the direction of tranc;fe~ (Hi=read:
Lo=write) for both slave and DMA accesses.

LDAS

1/0

Lo/Hi

LANCE Data Strobe to/from the LANCE,asserted by:.
a. 68000-to-LANCE read/write control sequence.
b. LANCE DMA read/write cycle.(Pullup resistor).

LHLDA

LANCE Hold Acknowledge, asserted in response to LHOLD
only whe'.1 thue is no valid slnve acce:;s hy the 68fl()(J_

LHOLD

LANCE DMA Request. (Pullup resistor).

Senset

Description

t The Sense column is used to show if a signal is an input I or output O from
the chip. Logic High (Hi) or Low (Lo) states are shown for signal assertion.

A-21

IC DESCRIPTIONS

Name

LREADY

Senset
1/0

Lo/Hi

Description
LANCE DMA Ready, used as follows:
Lo - the QNA2 control sequence responds to a LANCE DMA
cycle;
Hi - the LANCE indicates completion of 68000 slave accesses.

LCS

LANCE Chip Select, asserted for each complete 68000
read/write cycle.

LEN

LANCE Data Latch Enable (backport bus).

LCAB

LANCE Data Latch from backport bus, allowing the LANCE
control sequencer to terminate in its own time when:
a. 68000 writes to the LANCE;
b. LANCE DMA reads RAM.

LDIR

LANCE Data Latch Direction, presented before LENL to avoid
tristate overlaps.

LAOE

L~NCE Address Output enables the address latches on DMA
cycles. (The address is latched by LALE from the LANCE).

--.,

Backport Interface: 68000
Pin

Name

Senset

Description
~

lnt<'rrupt Level '2, ass~ncd to 68000 .. ~ the rc~ult of a host write
to the CSR. VAR, TXBDL, RXBDL or after the QNA2 tuner
has expired.

Hi/Lo

Read/Write from 68000.

Address Strobe from

I 0MHz clock for the 68000 microprocessor.

Valid P.:riph-.!ral Acces~. the result of a NA 1'/D operation on
FC0+FCI+FC2 and the inverse of ASM, indicatiug an active
interrupt acknowledge cycle. This inhibits 68000 access cycles.

Data Transfer Acknowledge to 68000.

1/0

Hi/Lo

Address Bit 21/Test, used with ADS to clock in BPDAL21 and
assen LADR.

'27

IPL:!

R/W

ADS

CPCLK

VPA

:, ~

DTACK

A21TES

t The Sense column is used to show if a signal is an input I or output O from
the chip. Logic High (Hi) or Low (Lo) states are shown for ~ignal assenion.

A-22

IC DESCRIPTIONS

Name

39:40

ADR<22:23>

Address Bits <23:22> indicate to the control sequencer the
device addressed:
00 68000 to ROM access
01 68000 to RAM access
10 68000 to QIC access
11 68000 to LANCE access

CPDIR

Control Pon Direction for the 68000 data transceivers.

CPOOE

Control Pon Data Output Enable for the 68000 data
transceivers.

CPAOE

Control Pon Address Output Enable for the 68000 address
latch .

Sensef

•

Description

Backport Interface: Memory

Name

SELROM

Select 68000 Firmware ROM.

SELSAR

Select Station Address ROM.

MWE

Memory Write Enable.

MCSL

Memory Chip Select.

Senset

Description

Backport Interface: Backport Bus Control
Pin

Name

MALE

Senset

Description
Memory Address Latch selects the two F373 latches on the
backport bus. The associated OMA cycle may be initiated by
68000 or QIC.

Power lines
Pin

Name

Description

0l,18,35,52Vss

Signal ground.

l 7,34,51,68Vcc

+5V Power rail.

t The Sense column is used to show if a signal is an input I or output O from
the chip. Logic High (Hi) or Low (Lo) states are shown for signal assertion.

A-23

IC DESCRIPTIONS

TOP VIEW

BACKPORT BUS
QIC
INTERFACE

------------

DIAGNOSTIC
LED
OUTPUTS
MODULE CONTROL
ETHERNET
INTERFACE MODULE CONTROL

LANCE I/F SA ROM I/F
MODULE CONTROL MODULE CONTROL
LANCE
INTERFACE

G8000
,N1ERFACE
BUS RESET
68000 !'FACE

GND 1
BPDAL13 2
BPDAL 14 3
BPDAL15 4
MREQ 5
MACK 6
BPRDWR 7
BPAS 8
20MHz 9
LED2 10
LED1 11
LEDO 12
INIT 13
RENA 14
FUSE 15
JMPR3 16
vcc 17
GND 18
LADR 19
ELOOP 20
JMPR2 21
JMPR1 22
LREAD 23
LDAS 24
LHLDA 25
LHOLD 26
IPL2 27
R/W 28
ADS 29
CPCLK 30
VPA 31
OINIT 32
DTACK 33
GND 34

68 GND
67 BPDAL12
66 BPADL7
65 BPDAL6
64 BPDAL5
63 BPDAL4
62 MCS
61 MWE
60 MALE
59 CPAOE
58 CPDOE
57 LAOE
56 BPDAL 11
55 BPDAL10
54 BPDAL9
53 BPDAL8
52 vss
51 GND
50 BPDAL3
49 BPDAL2
48 BPDAL1
47 BPDALO
46 CPDIR
45 LDIR
44 LCAB
43 LEN
42 SELSAR
41 ROMSEL
40 ADR23
39 ADR22
38 A21TES
37 LCS
36 LREADY
35 vss

BACKPORT BUS

-RAM
-

ACCESS
BACKPORT BUS

68000
INTERFACE
-----LANCE l'FACE
BACKPORT BUS

BACKPORT BUS
-

68000 l'FACE

_ _ _ _ _ LANCE

----► INTE.RFACE
-sAROM
68000 l'F-ACE
SEQUENCE
CONTROL
----► 68000 l'FACE
LANCE
INTERFACE .

R£17'6

Figure A-6

QNA2 Pinout

A.4.2.3 Addressing
Table A-4 lists the QNA2 registers together with their backport memory map adilre<;s..::...
Table A-4

QNA2 Registers

Backport Address

40FFOE

Control and status Register (CSR)

40FFIE

lnterrrupt Register (IR)

·A-24

IC DESCRIPTIONS

A.5 AM7990 LOCAL AREA NETWORK CONTROLLER FOR ETHERNET (LANCE)
A.5.1 Oven·iew
The LANCE operates with the SIA (from the same family of LSI devices) to provide a complete interface
between the backport bus and the Ethernet cable. The LANCE is a I 0Mbit/sec MOS device in a 48-pin package.
It implements the following facilities for the link level of the Ethernet protocol:
•

CSMA/CD network access

•

Memory management using on-board DMA

•

Error reporting

•

Packet handling

•

Microprocessor interface.

In transmit mode, the LANCE initiates a DMA cycle to transfer data from shared RAM. It prefaces the data with
the standard preamble and synchronisation pattern, and it calculates and appends a 32-bit CRC.
In receive mode. the SIA asserts Carrier Present to the LANCE, in order to indicate that two signals are available:
Receive Data and Receive Clock. The LANCE uses Receive Clock to clock in the Receive Data signals. Then it
calculate~ and compares the CRC to the CRC checksum at the end of the packet. If the two values do not match.
the LANCE sets an error bit and flags an interrupt to the 68000 microprocessor.
There are three addressing modes:
•

Physical addressing. in which a 48-bit destination address at the front of an incoming packet is compared
with the node addres~ wrinen to the LANCE at initialisation
Multi-cast addressing. in whilh the LANCE accepts all incoming packets for a certain class of node

•

Promiscuous operation, m which thr LANCE accepts all incoming packets.

In its buffers. the LANC[ sets up circular task queues known as descriptor rings. The l:!sh are l!Sed for transmit
and receive operations; up to 128 tasks may be queued for execution.
The architecture of the QlC is shown in Figure A-7.

A.5.2 Signals and Pinout
The signals to and from each QIC port fall into logical groups. The functions. signals and pinouts of these group,
are shown in Figure A-8 and described in Table A-5.

A-25

IC DESCRIPTIONS

DAL<15:0>
A<23: 16>

INTR
HOLD
HLDA
ALE/AS
CS
ADR
DAS
DALO
DAL1
READ
BMO
BM1
READY
RESET

PARALLEL
BUS
INTERFACE

OMA/DATA
PATH
CONTROL

BACKPORT
BUS
AND
CONTROL
INTERFACE

MICROPROGRAM
STORE

STATION
ADDRESS
DETECTION

RETRY
LOGIC

SERIAL
INPUT/
OUTPUT

RCLK
RX
TCLK
CLSN
TENA
RENA
RE17'1

Figure A-7

AM7990 LANCE Block Diagram

A-26

IC DESCRIPTIONS

BACKPORT BUS
INTERFACE

TOP VIEW

GND
DAL07
DAL06
DAL05
DAL04
DAL03
DAL02
DAL01
DALOO
BUS CONTROL - - - READ
INTR
68000 l'FACE
DALI
NCDALO
NC - DAS
BUS CONTROL
BMO
NC
BM1
NC
HOLD
QNA2
ALE/'AS
BACKPORTHLDA
BUS 1
cs
CONTROL
ADA
READY
RESET
68000 l'FACE
GND
DATA/
ADDRESS
LI-NES

¼............,

BACKPORTINTERFACE
(PINS 40-47)
ETHERNET INTERFACE
(PINS 25-31)

---

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

vcc

47 DAL08
46 DAL09
45 DAL10
44 DAL 11
43 DAL12
42 DAL13
41 DAL14
40 DAL15
39 A16
NC
38 A17
37 A18
NC
NC
36 A19
NC
35 A20
34 A21
NC
33 A22
NC
32 A23
NC
31 RX
30 RENA
29 TX
28 CLSN
27 RCLK
26 TENA
25 TCLK

DATA/
ADDRESS
LINES

HIGH-ORDER
ADDRESS BUS

SERIAL
INPUT/
OUTPUT
VIA
SIA

AE1748

Figure A~

AM7990 LANCE Pinouts

A-27

IC DESCRIPTIONS

Table A-5

AM7990 LANCE Signal Definitions

Backport Interface: Address and Data Bus

Pio

Name

Seoset

Description

02:09

DAL<07:00>

1/0 Hi

Data/Address lines (tristate). During

40:47

DAL<15:08>

32:39

A<23:16>

address select, A<23:16> contains the

0 Hi

upper 16 address bits.

Backport Interface: Backport Bus Control
Pin

Name

Senset

Description

READ

1/0 Hi

Read indicates the direction of data transfer. Reading when the
LANCE is bus master; writing when LANCE is bus slave.

DALI

0 Lo

Data/Address Line In (tristate).

DALO

0 Hi

Data/Address Line Out (tristate). (Not used).

1/0 Lo

Data Strobe (tristate).

14
15

BM0/BYTF

0 Lo/Hi

Byte Mask/Byte.

BMl/BllSAKO

0 Lo/Lo

Byte Mask/Bus Request Daisy Chain Output.
These tristate :signals are programmable through bit Oof CSR3. (Nu
Connection.)

HOLD/BUSRQ

O Lo/Lo

Bus Hold Request (open drain). This signal is programmable through
bit 0 of CSR3 (Pul!up resistor).

ALE/AS

O Lo/Hi

Address Latch Enable. This tristate signal is programmable through
bit I of CSR3 (Pullup resistor).

HLDA

I i..o

81,.,; Hold Ad.11,1wledge . .i.ssert..:d in re~pon~e 111 HOLD 1<1 make tht"
LANCE bus master.

I Lo

Chip Select puts the LA!\iCE imo bus -,la,.e mode fl,r a data 11-ai,,L·r
to or from the LANC::E rcgi:.ter-;. This signal mu~t not re a"scrr-. d
with HLDA.

ADR

I Hi

READY

1/0 Lo

Data Transfer ReaJy (open drain).

t The Sense column is used to show if a signal is an input I or output O from
the chip. Logic High (Hi I or Low (Lo) states are shown for signal assertion.

IC DESCRIPTIONS

SIA Interface: Ethernet 1/0
Pin

Name

senset

Description

READ

1/0 Hi

Read indicates the direction of data.

TCLK

I Hi

Transmit Clock (10MHz).

TENA

OHi

Transmit Enable.

RCLK

I Hi

Receive Clock (10MHz square wave).

CLSN

I Hi

Collision (logical input).

OHi

Transmit output bit stream.

RENA

I Hi

Receive Enable (logical input) indicates that a carrier is present on
the Ethernet channel.

I Hi

Receive input bit stream (input).

SIA Interface: 68000 Interrupts Control
Pin

Name

senset

Description

INlR

0 Lo

Interrupt (open drain; pullup resistor).

:'.3

Rf:SET

I Lo

Bus Reset Request cause~ LANCE to stop. clear its internal logii.:. and
idle.

""~

Power lines
Pin

Name

De~cription

Vss

Signal ground.

V..-c

+5V Power rail.

t 1 ,1e Sense column is used to show if a signal is an input I or output O from
the chip. Ln,·i, ilish (H1) or Low (L0! .,late:; are sho,rn for ,igf!al ::!'.-.ertion.

A-29

IC DESCRIPTIONS

A.5.3 LANCE Addressing
The LANCE has four Control and Status Registers, which are programmed from the 68000 microprocessor
through two pons on the backpon bus: the Register Data Pon (RDP), and the Register Address Pon (RAP).
To access the registers, the QNA2 first assens CS to put the LANCE into bus slave mode. The 68000 then writes .
a CSR select code to the LANCE, which stores the code in its Register Address Pon. Subsequent read/write
accesses affect only the CSR selected.

A.S.4 LANCE Registers
Table A-6 lists the LANCE registers.
Table A-6 LANCE Registers
Register

Description

RAP

Read/Write.

RDP

Read/Write.

CSRO

Control and Status Register 0

Transmit/Receive error flags.

CSRI

Control and Status Register I

Initialisation Block address.

CSR2

Control and <itatus Register 2

lnitialisati.>n Block address.

CSR~

Control and Statu~ Register 3

Defines bus master interface.

A.5.5 LANCE Buffers
Table A-7 lists the contents of the Initialisation Block. Table A-8 lists the contents of the Descriptor Rings.

A-30

IC DESCRIPTIONS

Table A-7

\_,

LANCE Initialisation Block

Bit/Name

Description

IADR + 0

Mode Register.

15 PROM

Promiscuous addressing mode.

14:07

Reserved.

06 INTL

Internal Loopback.

05 DRTY

Disable Retry on transmission.

04 COLL

Force Collision (diagnostic).

03 DTCR

Disable Transmit CRC (enables Multi-cast addressing in external loopback).

02 LOOP

Enable Loopback.

0IDTX

Disable Transmitter.

OODRX

Disable Receiver.

IADR.,. 02

Physical Address (P,\) .

47:00 PADR

Physical Address of LANCE .

IADR + 08

Logical Add1t:ss Filtt:r (J ,AF) .

63:00 LADRF

64-bit logical address mask.

Table A-8 LANCE Descriptor Ring Pointers
Bit/Name

Description

IADR + 18

Receive Descriptor Ring Pointer.

15:13 RLEN

Receive Ring Length, exprt:ssed as power of two.

1~:0!l

Rcl-erved.

07:00 RORA

Receive Descriptor Ring (base) Address.

IADR + 20

Transmit Descriptor Ring Pointer.

15:13 TLEN

Transmit Ring Length, expressed as power of two.

12:08

Reserved.

07:00TDRA

Transmit Descriptor Ring (base) Address.

A-31

IC DESCRIPTIONS

Table A-9 LANCE Four-Word Descriptor Ring Formats
Receive Message Descriptor O (RMDO)

Bit/Name

Descciptiou

15:00 LADR

Low order 16 address bits of buffer described. Written by the host and unchanged.

Receive Message Descriptor 1 (RMDI)
Bit/Name

Description

15OWN

Descriptor owned by LANCE (not host).

14 ERR

Error = OR operation on FRAM, OFLO, CRC, BUFF.

13 FRAM

Framing Error (not just CRC error).

12 OFLO

Overflow (internal silo).

11 CRC

CRC Error.

10 BUFF

Buffer Error (OWN bit zero, or silo overflow).

09 STP

Start of Packet.

08 ENP

End of Packet.

07:0U HADR

High order 8 address bits of buffer described.

Recehe Message Descriptor 2 tRMD2)
15:12

Must be ones

11:00 BCNT

Buffer Byte Count (2's complement), written by host and unchanged.

Receive Message Descriptor 3 (RMD3)
Bit/~ame

Description

15: 12

Reserved.

11:00 MC:--.:T

l\ks!-age By1e Count (in BCD), when l::.RR is clear and ENP i:. sc:. Written hy hu!-.I
and unchanged.

--------

Transmit Mec;sage Descriptor O (TMDO)
Bit/Name

Description

15:00 LADR

Low order 16 address bits of buffer described. Written by the host and unchanged.

A-32

IC DESCRIPTIONS

Table A-9 (Cont.) LANCE Four-Word Descriptor Ring Formats
Bit/Name

Description

Transmit Message Descriptor 1 (TMDl)

;,;;....._,_,,

Bit/Name

Description

15OWN

Descriptor owned by LANCE (not host).

14 ERR

Error = OR operation on LCOL, LCAR, UFLO, RTRY.

Reserved.

12 MORE

More than one retry needed.

II ONE

Exactly one retry needed.

JO DEF

Transmit Deferred, due to busy channel.

09 STP

Start of Pach.et.

08 ENP

End of Packet.

07:00 HADR

High order ~ address bits of buffer desl:ribed.

Transmit '\les,;age Descriptor 2 (TMD2)
mt/Name

Description

15: 12

Must be ones.

II:00 BCNT

Buffer Byte Count (2's complement), wrinen by host and unchanged.

Transmit Message Descriptor 3 (TMD3)

15 BUFF

Buffer Error (OWN bit zerc,, or ,;ilo underflow).

14 UFLO

Underflow error. Mess,1ge truncated due to late data from inemor).

Reserved.

12 LCOL

La:e Collision (channel slot time elapsed).

11 LCAR.

Loss of Carrier (RENA negated during transmission).

IO RTRY

Retry Error. after either one or 16 attempts.

09:00 TDR

Time Domain Reflectometry (valid for RTRY).

A-33

IC DESCRIPTIONS

A.5.6 Logical Address Filter
The LANCE maps each incoming 48-bit logical address from the Ethernet to the 64-bit logical address mask
(stored at IADR+08 in the Initialisation Block).

If the first bit of the incoming physical address is set (PADR<O>=l), the address is passed to the logical address
filter, which contains four 16-bit registers. All 48-bits of the incoming address are passed through the CRC
circuit. The six high-order bits of the resultant 32-bit CRC are strobed into a register, where they are decoded to
select a single bit position in the LAF. If that bit in the LAF is set, the incoming address is accepted.
This provisional assessment is then checked by comparing the full incoming logical address with the list of valid
logical addresses that is stored in shared RAM.
The broadcast address does not go through this decoding process.
Table A-10 shows how LAF bit positions correspond to logical addresses.
Table A-10

LANCE Logical Address Filter Mask

Logical

LAF

Filter

bit

Destination
Address

Logical

LAF

Destination

Filter

bit

Address

(hex)

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

'.!B

LAF2

LAFO

LAF2

LAH)

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LArD

LAF2

LAFO

LAF2

A-34

--.

IC DESCRIPTIONS

Table A-10 (Cont.)

LANCE Logical Address Filter Mask

Logical

LAF

Destination

Logical

LAF

Destination

Filter
Register

bit

Address
(hex)

Filter
Register

bit

Address

LAFO

A7 •

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

LAF2

LAFO

8()

LAF2

LAFO

LAF2

LAFO

LAF2

\._

(hex)

A-35

IC DESCRIPTIONS

A.6 AM7991 SERIAL INTERFACE ADAPTER (SIA)
A.6.1 Overview
The SIA is a Manchester encoder/decoder which interfaces between the LANCE TIL logic and the Ethernet
transceiver. It is a 24-pin package, and is located close to the Ethernet connector.
The SIA acquires clock and data within six bit-times, and decodes Manchester data with less than +/-20ns phase
jitter at 10MHz. In order to minimise false start conditions, the SIA provides both guaranteed signal threshold
limits and transient noise suppression circuitry in both data and collision paths.
The architecture of the SIA is shown in the block diagram Figure A-9.

RX -

MANCHESTER
DECODER

RCLK

RECEIVE+

DATA
RECEIVER

RECEIVE-

l
RENA

CARRIER
DETECT

CLSN

COLLISIOI\!
DEHCT

TX
TENA
TCLK

NOISE
REJECT
FILTER

MANCHESTER
ENCODER

COLLISl:JI\! 1~-"""'-

COLLISIOi\1--

TRANSMIT+
TRANSMIT-

Figure A-9

AM7991 SIA Block Diagram

A.C..2 Signal Description
The signals lo and from the SIA fall into two logical groups. The functions, signals and pinoub uf these group~
are shown in Figure A- IO and described in Table A-11.

·A-36

IC DESCRIPl'IONS

BACKPORTINTERFACE

TOP VIEW
CLSN

23
22
21
20
19
18
17
16
15

RENA 3
RCLK 4
TSEL 5
GND1 6
GND2 7
X1 8
X2 9
TX 10
TCLK 11
TENA 12

ETHERNET INTERFACE
COLLISION+
COLLISIONRECEIVE+
RECEIVETEST
VCC1
VCC2
PF
RF

GND2
14 TRANSMIT+
13 TRANSMIT1111710

Figure A-10

AM7991 SIA Pinouts

A-37

IC DESCRIPTIONS

Table A-11

AM7991 SIA Signal Definitions

Backport Interface
Pin

Name

senset

Description

CLSN

0 Hi

Collision

0 Hi

Receive Data (TTL output)

RENA

0 Hi

Receive Enable (TTL output)

RCLK

0 Hi

Receive Clock (TTL output)

TSEL

1/0 Hi

Transmit Mode Select (open collector output/sense amplifier input). When
the transmitter is idle: TSEL low selects Transmit + positive with respect
to Transmit - , TSEL high selects Transmit + equal to Transmit -

Gndl

High current ground

Gnd2

Logic ground

I Hi

Transmit (TTL compatible)

TCLK

OHi

Transmit Clock (TTL; symmetrical). This is also input to tbe LANCE

TENA

I Hi

Transmit Enable (TTL compatible)

Gnd3

Phase Filter control voltage for phase lock loop damping (receive path)

\'cc2

+5V Power rail for vL,Jtage controlled oscillator in phase lock loop

Vee!

High current and logic supply

TEST

I Hi

Biased crystal 0scillator. used to generate TCLK
Biased crystal oscillator, used to generate TCLK

Ground for voltage controlled oscillator
0

I Lo

Receive Frequency. A reference voltage for the receive path phase
detector ard and timing noise immur.ity circuits

Te~t control

t The sense column is used to show if a signal in an input I or output O from
the chip. Logic High (Hi) or Low (Lo) states are shown for signai asse11ion.

A-38

IC DESCRIPTIONS

Table A-11 (Cont.)
Pin

Name

AM7991 SIA Signal Definitions

senset

Description

Ethernet Interface

Transmit -

Transmit. Differential line outputs into terminated transmission lines

Transmit+

Transmit. Differential line outputs into terminated transmission lines

Receive -

Differential line inputs

Receive+

Differential line inputs

Collisian +

Differential collision inputs, which do not affect data path functions.

Collision -

Differential collision inputs, which do not affect data path functions.

t The sense column is used to show if a signal is an input I or output O from
the chip. Logic High (Hi) or Low (Lo) states are shown for signal assenion.
A.6.3 Noise Margins
On input the static noise margin for received carrier detection is -175mV to -275mV. Transient noise of !es<; than
IOnsec. in the collision path. and 16nsec. in the data path. are a1so rejected. The SIA will decode jittered data of
up to +/-20nsec.

A-39

IC DESCRIPTIONS

A.7

THINWIRE ETHERNET TRANSCEIVER

A.7.1 Functionality
The Thinwire Ethernet Transceiver is made up of a DP8392 transceiver chip, an isolation transformer and a DCDC convener. The transformer isolates the Thinwire Ethernet Transceiver from the rest of the DESQA circuitry.
The·-9 Vdc needed for the DP8392 chip, is convened by the DC-DC convener from +12 Vdc which is supplied
by the host. A functional block diagram of this transceiver component set is shown in Figure A-11.
COAX

SIA

CABLE

, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , INTERFACE

RECEIVE
PAIR

RECEIVER
EQUALIZER

•·POLE BESSEL
LOW PASS FILTER

SENSE

tiEARTBEP ENABLt:
~

i t Mi,~

OSCILLATOR

RE7096

Figure A-11

Functional Block Diagram of Thinwire Ethernet Transceiver

A-40

IC DESCitlPJ'IONS

The DP8392 chip block diagramis shown in Figure A-12

DCTODC
CONVERTER

12VDC

4990HMEACH

.fNISCX.ATED
COAX

16
COLLISION
PAIR

RECEIVE

PAIR

CDS

1312

"'
TX+ 7
TX- 8

TRANSMIT
PAIR

ISOLATION TRANSFORMER
1117100

Figure A-12

DP8392 Block Diagram

A-41

IC DESCRIPTIONS

Name

senset

Description

CD+

Balanced differential line driver outputs from Collision Detect Circuitry.

CD-

The I 0MHz signal from the internal oscillator is gated to these outputs in
the event of collision, excessive transmission (jabber), or during SQE test.
These outputs are open emitter; pulldown resistors to VEE are required. When
drawing a 78 ohm transmission line, these resistors should be 500 ohm.

RX+

Balanced differencial line driver outputs from the receiver.

RX-

These outputs also require 500 ohm pulldown resistors.

TX+

TX-

VEE

GND

Ground connection.

HBE

Thi~ input enahles CD Heartbeat when at VIH, disabk:s it when at VIL.

RX!

Receiver input from the coaxial cable. Signals meeting receiver squelch
requirements are equalized for intersymbol distortion, amplified, and outputted
at RX+.

TXO

CDS

Balanced differencial line receiver inputs to the transmitter.

Supply connection. VEE is negative with respect to ground.

Transmit output; connects to coaxial cable.
Ground sense connection for collision detect circuitry. This pin should be
connected seperately to the shield to avoid voltage drops through the coax
shield from altering the receive mode collis.ion threshold.

tThe sense column is used to show if a signal is an input I or output O from
the chip. Logic High (Hi) or Low (Lo) states are shown for signal assertion.

A-42

APPENDIX B
NETWORK MANAGEMENT

B.1 SCOPE
This appendix outlines the Ethernet Network Management protocol.

B.2 NETWORK CONTROL
To control access, Ethernet uses Carrier Sense Multiple Access with Collision Detection (CSMA/CD). This is a
distributed channel allocation procedure under which every station receives all the trarn,missions from every other
station. Each station can detect overlapping transmissions by other stations, and must wait for the bus to become
idle before transmitting its message. There is no central or hierarchical control for this distributed process.

B.2.1 Ethernet TraPsmisdon
The data link layer checks that the network bus is clear of any baseband signal before it start<, to trausmir.
When the channel is clear, the data link layer passes the data packet to the physical layer a~ :, :,tr.cam ot bih.
The physical layer prl'.cedes the data with an encoded preamble that allows the other nodes on the charmel to
synchronise their clocks. Then the physical layer starts to translate the binary encoded data into Manche<;terphase-encoded signals.
Throughout the transmission. the physical layer monitors the correct energ5' level for transmission without
contention in the channel. If the energy level exceeds this, then the physical layer sen&, a colli:,ion detect signal
to the data link layer.
The collision detect sifnal Lan 011ly be detecteJ by a node that is tr~nsinitting.

B.2.2 Ethernet Rt'ception
In the absence of other traffic on the channel, the physical layers of all other nodes in the network sem,e the
carrier signal from a transmitting node. They alert their respective data link layers with a carrier sense signal. in
order to delay any conflicting attempts to transmit.
The physical layer of each receiving node synchronises to the incoming preamble. receives the encoded bits from
the cable. and translates the phase-encoded signal to binary encoded data, discarding the preamble.

At each of the receiving nodes. the binary bits are passed to the data link layer. which has been alerted to its
arrival by the carrier sense signal. As the bit stream arrives. the data link layer checks the destination address. If
the data is intended for that node. the packet is inspected for damage and alignment. before being passed on to
higher levels of protocol with an indication of its condition. If the packet is not intended for that node. the bit
stream is halted.
The physical layer continues to receive encoded bits from the channel until the carrier goes off.

B-1

NETWORK MANAGEMENT

B.2.3 Ethernet Contention
When two nodes simultaneously determine that the channel is free, and start to transmit, a collision occurs.
Ethernet is designed to cater for such collisions by re-transmission following on a collision detect signal.

The Ethernet packet is specified to have a minimum length of 64 bytes because the time it takes to transmit such
a packet over the maximum Ethernet configuration is slightly less than the time it talces for a collision detect
signal to travel from one end of the network to the other and back again. (The elapse time for a round-trip signal
is known as the network slot time).
This means that the collision detect signal from a node at the other end of the network has time to reach any
originating node before that node has completed transmission of the packet that caused the collision. The
originating node can then re-transmit the correct packet.
On receipt of a collision detect signal the data link layer at the transmitting node:

Continues to transmit the packet, in order to cause a jam that will be noticed by all other nodes.

Backs off and schedules a re-transmission attempt. The delay before re-transmission is an integral multiple
of the slot time. The multiple is selected at random by each node for each collision.

The bits from a collision are known as a runt packet because the physical layers at all the receiving nodes accept
the bits as though they were from a valid packet. However, the data link layers reject runt packets because they
are always shorter than the shortest Ethernet packet.

B.2.4 Ethernet Fault Detection
Data integrity is maintained by the 32-bit CRC for each packet. This is handled by the data link layer protocol.
Several network maintenance features are also built into the system:

Time Domain Reflectometry. Whenever a packet is transmitted, the transmitting node starts a timer and
notes the times of all collisions. If the collision times are not random, but predictable and due to some
physical fault. then the location of the fault be determined by time/speed/distance calculations.

Time-limited operations. Both controller and transceiver are designed to time out any transmission that i~
significantly longer than the Ethernet specification.

Power supply monitor. The controller monitors the power line direct from the transceiver; and trie
transceiver provides a positive test signal to the controller after every transmission to verify its opuauon.

Loopback diagnostics. both local and remote, are provided.

ll-2

APPENDIX C
VECTOR ASSIGNMENTS
This appendix lists the rank of vector assignments for Q-Bus systems.
The DESQA has a fixed 1/0 page address, as selected by the on-board switch SI, and uses a fixed vector of
120(octal) for the first DESQA and a floating vector assignment for the second DESQA. The floating vector
assignments start at 300(octal), and are assigned by rank to the units on the host system. The rankings are shown
in Table A-1; the highest ranks have the lowest numbers.

C.l THE FLOATING VECTOR ASSIGNMENTS
If a host node has a KXVll and an RXV21 and a DESQA, the DESQA is allocated the third floating vector
because it is third in rank.
A device may use both fixed and floating vectors and addresses, and the assigned rank may be different for a
floating address and a floating vector.
The DESQA module is configured as a OMA dev.cc, in the same way as a DEQNA module. The first
DEQNA/DESQA vector is fixed by host system software at 120(octal). Subsequent DEQNA/DESQA modules
are assigned a floating vector with a rank of 47(octal), and should be configured at system start-up using the
auto-cnnfigmation routines for floating vectors.
C.2 FLOATING VECTORS
The DESQA uses one 16-bit word for a vector adchss.

The vector assignment rules are as follows.
Each device occupies vector address space eqtial to Size in words.
For example. the DLVI 1-J occupies 16 words of vector space. If its vector was 300(octal), the next available
vector wou;d be a, J40(octal).
•

Ther are no gaps, except those needed to align an octal modulus.

C-1

VECTOR ASSIGNMENTS

.-....,,

Table C-1 Floating Vector Address Assignments

Device

Size
(Decimal)

(Octal)

Dell

TU58

KLil

I0t

DLII-A

lot

DLII-B

lot

DLVll-J

DLVll, DLVll-F

DPII

DMll-A

DNII

DMll-BB/BA

UH 11 modem control

DRil-A, DRVll-B

DRll-C, DRVll

PA611 (reader + punch)

LPDll

D107

DXII

DLII-C to DLVll-E

DJl I

DHll

VT40

VSVll

LPSll

DQll

Rank

Modulus

.--..

,,,.~

tKLJ I or DLI I as console has a fixed vector.

C-2

VECTOR ASSIGNMENTS

Table C-1 (Cont.) Floating Vector Address Assignments
Rank

Device

Size
(Decimal)

(Octal)

KWll-W, KWVll

DUll, DUVll

DUPII

DVll + modem control

LKII-A

DWUN

DMCI 1/DMRI I

DZll/DZSll/DZVll, DZ32

KMCII

LPPll

VMV21

VMV31

VTVOJ

DWR70

RLll/RLVII

4§

TSII, TU80

4§

LPAll-K

IP! l/1P300

4§

KWll-C

RX11/RX21 I RXVI l/RXV21

4§

DRII-W

DRII-B

4§

DMPll

DPVll

MLII

4:j:

Modulus

§The first device of this type has n fixed vector. Any extra devices have a floating vector.
;ML! I is a MASSBUS device whii:h can connect to UNIBUS using a bus adapter.

C-3

VECTOR ASSIGNMENTS

Table C-1 (Cont.)

Floating Vector Address Assignments

Rank

Device

Size
(Decimal)

Modulus
(Octal)

ISBI I

DMVII

DEUNA DEQNA/DESQA/DELQA

4§

KDA50/RQDX3

4§

DMF32

KMSII

PCLI 1-B

VSIO0

TU81

KMVll

KCT32

JEX

DHVl 1/DHUl 1/DHQI l

DMZ32/CPI32 (async)

CPI32 (sync)

QNA

QVSS

VS31

LNVII

QPSS

QTA

DSVll

§The first device of this type has a fixed vector. Any extra devices have a floating vector.

C-4

VECTOR ASSIGNMENTS

- - - - - - - - - - - - - - - 777 777

FIXED ADDRESSES (2K WORDS)

- - - - - - - - - - - - - - - 770000

USER ADDRESSES ( 1K WORDS)

- - - - - - - - - - - - - - - 764000
FLOATING ADDRESSES (1 K WORDS)
i------------------4

760010

DIAGNOSTICS

' - - - - - - - - - - - - - - - - 760 000

000477
80 FLOATING VECTORS

000 450
0-BUS RESERVED

000 400
FLOATING VECTORS

000 300
FIXED VECTORS
TRAPS

Figure C-1

Q-bus Address Map

C-5

000030

(

APPENDIX D
PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS
This appendix contains programming examples written in MACRO- I I for the DESQA. They are presented only
as a general guide for the prospective user, and not as the best or only method of driving the DESQA. These
programs are not guaranteed or supported by Digital Equipment Corporation.
Programming examples are provided for the following.

Data definitions

Resetting the DESQA

Configuring the DESQA

A simp!e interrupt handler

Data transmission

Data reception

Executing on-board diagnostics

D.1

DATA DEFINITIONS

)

The following data definitions are used throughout the sample programs. N~te that all numbers are octal unless
otherwise specified.

D-1

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

Table D-1

Data Definitions for Sample Programs

bitl5

100000

bitl4

040000

bitl3

020000

bitl2

010000

bitl I

004000

bitlO

=
=

bit09

001000

bit08

000400

bit07

000200

bit06

000100

bit05

000040

bit04

000020

hi!0~

000010

000004

bit0I

000002

bitOO

000001

002000

The following sample programs refer to a DESQA installed at 1/0 page base address 17774440, and the following
detinitiom, of 1/0 port registers apply throughout.
. ·,.,,... ::.:..
qar:..r.: .wo:-ci
a G- -- "'l l : . ;..;:: r ci
q=-::-~.: . \o:Oc::

q~"'~- :
~

.J.

risvs:::

. "-A·~.:j

: 7 4 ;4
17444
I7445
J. ~ 4 ½:
17445

?'-: ">DL 1_ow-·order address bi Ls

Rx BDL high-order address bits
Tx BuL low-ordec address bits
'I:-: BDL high-order address bits
Vecc.or Address Register

D--2

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

VAR bit definitions
ms
OS

rs
s3
s2
sl

bitl5
bit14
bitl3
bit12
bitll
bitlO
174456

lqacsr: .word
;

Mode Select
Option Switch
Request to execute self-test
Self-test status
; Control and Status Register

CSR bit definitions
ri
el
il
xi
ie
sr =
re

bitl5
bit09
bitOB
bit07
bit06
bitOl
bitOO

; Receive Interrupt
External Loopback
Internal Loopback
Transmit Interrupt
Interrupt Enable
Software Reset
Receiver Enable

The following define the octal offsets and bit values of individual fields of a buffer descriptor.
; Flag word.
bflw

Note : This field is reserved]
0

; AdJ=ess descriptor bits.
bd.-s

h
l

bitOG
b:..t07
bitl2

:.,

e
C
V

invalid

bitl3
bitl4
bitl5
0

High byLe only beginning
Low byte only te1::r.i!1ation
.:.:tdica:.es th,;t this is a ...
... Setup paci<et
Endo: message
Chain address
Valid bit
descriptor is not Valid

; 6 High Order buffer address bits.
bp;ih

; 16 Low O=der b~ffer address bits.
bpad

; Twos complement of buffer size in words.
bsiz

; Status word ¥1.
bswl
unused
lastok

1 ~100000
0

unused status word
this descriptor contains the last ...
... or only segnent of a packet ...
... with no errors.

Bits defined for Receive status word #1
esetup
rblh

bitl3

; indicates a looped back Setup or ...
; ... External Loopback packet
b:tC8!bitO~!b:t10 ; high order 3 bits of ...

D--3

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

... receive byte length of packet
;

; Status word #2.

bsw2

; Bits defined for Receive status word t2
;

rbll

377

low order 8 bits of receive ...
... byte length of packet

D-4

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

D.2 RESETTING THE DESQA
The DESQA undergoes a software reset when CSR bit I is cleared from I io 0.

;

*--------------------------------------------------------------*
*

; *
; *

A routine to Software Reset the DESQA.

*
*

*--------------------------------------------------------------*

lqares: bis
bic
rts

#sr,@lqacsr
#sr,@lqacsr
pc

; set SR in CSR
; clear SR to generate sw reset
; return to caller

D-5

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

D.3 CONFIGURING THE DESQA
The DESQA may be configured using SETUP packets for various modes of reception of Ethernet packets. The
following routines demonstrate a method of assembling, transmitting and receiving a SETUP packet.

*--------------------------------------------------------------*
;

*
*

; *
; *

; *
;

Routine to enable the DESQA to accept any legal packet
from the Ethernet whose destination address is in the
following list.
All address digits are octal.

• *

;
;

*
*

• *

;

100-001-002-003-004-005
100-002-002-003-004-005
101-001-002-003-004-005
101-002-002-003-004-005
377-377-377-377-377-377

physical
physical
multicast
multicast
broadcast

address
address
address
address
address

fl
f2
fl
f2

; *

*
*
*

*
*

*--------------------------------------------------------------*

setupa:

JS:r

ilstpa:ls,rl
#ns::pad,r2
r3
pc,lqastp

rts

r.-1.:>V

mov
clr

:able
stp.::.:i~·:

Ethernet addresses.

.b· ~c

.b::te
.l:Y::e

.by::"'
ns:paci

rl := addr of SETUP addr list
r2 := number of addrs in list
r3 := SETUP control byte
assemble, transmit, receive ...
... the SETUP packet
return to caller

::.oo,C~l,OG2,0S3,004,005
lOO,G:2,002,003,004,005
101, :::::., 3:,2, oc::., 004, 005
ic::.,oc:,0c2,003,Jo4,00S
377,377,377,377,377,377
<.-stpads>/6

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

,.
,.

*--------------------------------------------------------------*
.
*

.*Subprogram: LQASTP

* This subprogram generates and transmits a SETUP packet to
* the DESQA using a list of addresses (physical, multicast,
* broadcast) supplied by the caller. The caller may also
* specify control information concerning device filtering
* modes (e.g. all multicast, promiscuous) and Sanity Timer
* timeout values.
;

;

* Note that if the caller specifies less than 14 Ethernet
* addresses, this code pads the Setup packet with duplicate
* addresses until there are 14 addresses in the packet.

*
*

*
*
*

; *

* Parameters :

;

;
;
;
;

*
*

;

*
*

;
;
;
;

*
*

Rl <-- table of 6 byte filter addresses.
R2 <-- number of addresses in table.
R3 <-- control byte value defined as follows

*
*

bit #0
- Enable[l)/Disable[0J All Multicast Mode. *
bit #1
- Enable[l]/Disable[0J Promiscuous Mode.
bits #2-3 - Specify which cf the three DESQA LEDs to"
switch off.
*
bits #4-6 - Specify factor of 4 times 1/4 second for*
Sanity :imer timeout value.
*

*,..

*
*

*------------------------------•--------------------------------Y

save !:"egisters

F,ov
mov

rl,-(sp)
r2,-($p1
r'.>,-(sp)
r 4 , - ( s ,., \
rS,-(sp)

mov
mov
mov
mov
mov

rl,stplst
r3,ctlbyt
r2,numsad
lstpkt,r3
#2,r0

save addr of callers addr table
save control byte
save number of addrs in table
?.3 .- start of setup pr.1cket
FOR 2 addr blocks in setup pkt -DO

10$:

!TIO\'

#6,r:

20$:

mov
clrb

rl,adrbyt
(r3) +

mov

#7,r4

Jqa3t.p:

'.'.lOV

mcv

FOR 6 bytes in each addre:s
BEGi, 1
save a~dr byte pointer
zero £~rs~ byte ira colum~

FOR 7 addrs in each blor.k

BEGIN

30$:

moyb
dee
ble
add

(rl), (r3) +
r2
4CS
16,rl
r4,30$

get next addr byte from tbl
decrerr:ent address cou:.t
IF NOT end of table THEN
skip to next addr in table
SND [for]

mov
inc
mov
sob

adrbyt,rl
rl
numsad,r2
rS,20$

restore addr table poinLer
skip to next addr byte in tbl
restore addr table entry count
EN:) [ for J

40$:

Zero the unused bytes from
<l> offset 160 to 177 octal
<2> offset h0 to 77 octal.

D--7

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

70$:

mov
mov

#stpkt+60,r4
#10,r3

mov
clr
sob

#0,lOO(r.4)
(r4) +
r3,70$

r4 := addr of 1st unused area
FOR x = 1 to 10 (octal) words DO
BEGIN
word[l60+x] ·= 0
·= 0
word[60+x)
END [ for l

Insert the next 7 addresses at offset 100 (octal) into packet.

90$:

mov
mov
sub
ble
add
mov
sob

#stpkt+l00,r3
stplst,rl
#7,r2
90$
#7*6,rl
r2,numsad
r0,10$

mov

ctlbyt,rO

r3 := addr of second addr block
goto start of callers addr tbl
IF> 7 addrs in table THEN DO
jump to the 8th addr in table
remember number of addrs left
END [for]
restore control byte

The byte length seen by the DESQA must be 200 (octal)
plus the 7-bit control information.
add
mov
ash

#200,::C
r0,r4
#-1,r4

rO := e=fective SETUP pkt ler.gth
save byte count
divide_by 2 for word count

Two cases arise here
<1> Eve~ ty:e length SETJP packet.
Use address descriptor flags V(valid), E(end of message)
and S (setup).
<2> Odd byte length SETUP packet.
Use V,E and S anG also L(low byte only termination).
NOTE

In the case cf Setup packets, the Address Descriptor
bits Hand Lare not used to determine the transmit
buffer alignment as they are with other packets. Instead
the Hand L bits are used solely to calculate the
lo~~cal lenq•h of the Setu~ packet for the purpose cf
determining the control information from the packet
length mcdu:a 200 oct~l.
n,.......

¥·.r!e!2, :-tt:,:rll •L.Je:-

bit
be~

11,rO
95S

.inc

I :,

C, stt:-:dl+bdes

;

a:::sume on even len:.1~ ~ '')acket

I~ odci length setup p~: ~~E~ DO
BECIN
1ncrmt worJ count for odd by~e
set addr descriptor L bit
Et;::i

95.;'.:

neg

mov

r.;, :,tt:-:dl+bsiz

get 2r r0~pleme~t word cou~t
save it in TxBDL field
disable interruptr via CSR IE

ClC

Validate the Reseive ~nd Transmit buffer descriptor lists.
mcv
clr
mov
clr

# st. r:-: j l,@ l qa r 11
~lqa.rln
#sttzdl,~lqa::...i
@lqatlh

w,ite R·, P:'L
a:-.d valid;c;:e
wr:.te Tx iiDL
validate it,

jsr

pc,wtri:-:i

wait for x: and RI to be
. . . asser:.ed ~- CSR

D--8

addr to the DESQA
it
addr tc the DESCA
sta!"t transmi3sinn

...

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

RI and XI must be reset to '0' by writing '1' to them.
bis

#ri!xi,@lqacsr

reset XI and RI to '0' in CSR

Verify that there were no transmit errors.
mov
bic
cmp
beq

sttxdl+bswl,rl ; rl := transmit status word 1
#AC<bit15!bit14>; zero all except LASTNOT ...
... and ERROR/USED
#lastok,rl
IF NOT transmit error THEN DO
100$
check for receive error

Transmit .error handling code should be placed here.
br

endstp

quit

Verify that there were no receive errors.
100$:

mov
bic
crr.p
teq

strxdl+bswl,rl ; rl := receive status word 1
#AC<bit15!bit14>; zero all except LASTNOT ...
;
... and ERROR/USED
#iastok,r~
IF NCT receive error THEN DO
er.dstp

Receive ~rror ha~dlir.g code should be placed here.
endstp: mov
mov

restore caller~ registers

ft)(Y\•

(sp) +, r5
(sp) +, r4
(sp)+,r3
(sp)+,r2
(sp)+,r~

rts

return to caller

me\

mov

Define Buffer Descriptor Lists.
Transmit Buffer Descriptor List.
sttxdl:

.word
.word
. wora
.word
.w~rd
.wo~d

unused
s.::pki:.
ur:us~·-::
t::.::se::i

flag word
reserved for addr descrptr bits
addr of assembled SETUP packet
reserved for packet lenqth
status word #1
sta~us word #2

Follo¼ with an inval~d descriptor.
.word
.word
.word

unused
ir.val:.d
0,0

flag word
INVALID descriptor
dummy buffer addr and word count

Rec"'ive Buffer Descriptor List.
strxdl:

.wo:d
.word
.word
.word
.word
.worci

u1,us,2d
V

recbuf
-rcbfln/2
unused
unused

flag word
this descriptor is VAL!D
addr cf SETUP packet Rx buffer
2s comp of Rx buffer word length
status word #1
status word #2

Follow with an invalid descriptor.
.word
.word

unused
inva:id

flag word
this 0escriptor is INVALID

D--9

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

.word

0,0

; dummy buffer addr and word count

Reserve storage for the assembled SETUP packet.
stpkt:

.blkb

377

.even
Reserve storage for the Receive buffer.
recbuf: .blkb
rcbfln

377
.-recbuf

.even
; Temporary work storage.
ctlbyt: . word
numsad: . word
adrbyt: . word
stplst: . word

SETUP control byte
# entries in callers addr table
addr of ·current addr byte in ...
... callers address table
address of callers address table

D-10

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

;

: *--------------------------------------------------------------*

,• *

* Subprogram WTRIXI

; *
* This subprogram waits for RI and XI to be asserted in
; * the CSR.

,• *

*
*
*
*

*
*

; *--------------------------------------------------------------*
wtrixi: mov

rl,-(sp)

; save rl

Wait for RI and XI to be set. Note that a real application
; program would need a timeout check.

10$:

mov
bic
cmp
bne
mov
rts

@lqacsr,rl
#AC<ri!xi>,rl
#ri!xi,rl
10$
(sp)+,rl
pc

REPEAT
rl := (CSR)
zero all bits except RI and XI
UNTIL RI and XI are set to , 1,
restore rl
return to caller

D-11

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

D.4
;
;
;
;

A SIMPLE INTERRUPT HANDLER

*--------------------------------------------------------------*
*
*
*
*

,• *
,• *

Subprogram LQAINT

This subprogram handles DESQA Transmit and Receive
interrupts .

; *--------------------------------------------------------------*
lqaint: mov
bit
beq
movb

rl,-(sp)
#xi,@lqacsr
ck.rxi
#1,txdone

save work register
IF XI is not set to '1' THEN DO
go check for Rx Interrupt
ELSE DO
set TXDONE flag

; Reset XI to '0' by writing a '1' to it.
Must be careful to avoid accidentally resetting RI also.
mov
bic

@lqacsr,rl
#ri,rl

mov

rl,@lqacsr

ck.rxi: bit
beq

#ri,@lqacsr
endint

rl := (CSR)
RI := 0 to avoid writing ...
, 1' to it
reset XI to , 0' ty w~iti1,g ...
, l' to it

...

IF RI is not set to , l' THEN DO
return
i:l..::E

movb

#1, rxdor.e

set RXDC'NE ila;

Rese~ R: tc '0' by w~~t~ng? ' 1 ' to ~t.
Must be careful to ~~cid accidentally re~etting XI also.
mov
bic

@lqacs::::, :::::
#xi,rl

mov

rl,@lqacsr

endint: mov
rti
txar,ne:
rxdone:

.byte
.byte

(sp)+,rl

r: := (CSR)
XI := 0 to avoid writing ...
. . . ' l ' to it
reset RI to '0' by writing ...
... ' l ' to it
restore rl
ret~::::n to caller

stcrace for in:err~2t flag byte
~turage for interrupt fl~g by~e

D-12

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

D.5 DATA TRANSMISSION
The steps required to initiate a transmission are:
•

Write the 16 LOW-order bits of the Transmit BDL address to the 1/0 page low-order Tx BDL register.

•

Write the 6 HIGH-order bits of the Transmit BDL address to the 1/0 page high-order Tx BDL register.

The completion of the transmission may be detected in one of two ways.
•

Polling the XI bit in the CSR with DESQA interrupts disabled.

•

Enabling the DESQA to interrupt the host when transmission is complete.

*--------------------------------------------------------------*
*
• *
Routine to transmit a packet and poll the CSR to

; *

*
*

; *
; *

detect transmission completion.

*--------------------------------------------------------------*

txpkti: bic

#ie!el,@lqacsr

bis

#il, @lqacsr
#t:-: .bell, @lqatll
@lqatlh

me~~
clr

;

disable DESQA interrupts ...
... and loopback modes
disable Internal Loopback
write addr of Tx BDL to DESQA
start the transmission

Wait for XI to be set. Note that a real application program
would. need a timecut check.

10$:

1: ~ T"

#xi,@Jqacsr

REPEAT
te~t XI bit in CSR

heq
FP£~-

.·.. :c:.

'2' ~y wri~~ng a '1' to it .

c·:: ccc:-,-C:·;2. to avoid acci:ientally res.,,::ting RI al::;o.
mov
bic

@lqacsr,rl
#ri,rl

m'.:l".'

r~,@lqacsr

rl := (CSR)
RI := OI to avoid writing ...
a , 1' to it
reset XI to , 0, by writing ...
a '1' to it
f

...

C~e~k ~hf 7~a~s~i: sta:~s to v£rify t~---~ ~o tran~n,it erro~s have
oc--:;.;rred.
rnov

Die.

tx.bdl+bswl,rl
¥~C<bitl5!bit14>
¥.::.astok, rl
2nc-

20$;

rl := transmit status word 1
zero all except LASTNOT ...
... and ERROR/USED
IF NOT transmit error THEN DO
continue
; ELSE DO

return Lo caller

; 7ransm~t Buffer Desc~iptor List.
tx.bdl:

.word
.word
.word
.word
.word
.word

unused
,: ! e

tx.buf
-t.x . .::.eP./.;:
unused
unused

flag word
Valid desc and End 0£ Msg
address of transmi~ b~ffer
2s comp buffer word length
status word #l
status word #2

D- ·13

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

Follow with an invalid descriptor.
.word
.word
.word

unused
invalid
0,0

flag word
this descriptor is INVALID
dummy buffer address, length

Reserve storage for maximum length transmit buffer.
tx.buf:
tx.len

.blkb

1514.
.-tx.buf

1514 (Decimal) bytes

D-14

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

*-----------------------------------------------------------~--*

,• *
; * Routine to transmit a packet and wait for the DESQA to
; * interrupt the host to signify that the transmission is
; * complete.
,• *

*
*

*--------------------------------------------------------------*

txpkt2:
lqavec
pri07

400
340
bic

#ie!el,@lqacsr

bis

#il,@lqacsr

;
;
;
;
;
;
;

DESQA host interrupt vector
Processor Status of
... interrupt handler
IPL= 7
disable DESQA interrupts ...
... and External Loopback
disable Internal and
... Internal Extended Loopback

...
-

; We must write the address of the DESQA interrupt vector to the
VAR without altering the Mode Select bit (bit15) in that
; register.
mov
bic
bis
mov

@lqavar,rl
#AC<~s>,rl
tlqavec,rl
rl,@lqavar

mov

#lqaint,lqavec

mo"J

trri07,lqavec+2

rl := (VAR)
zero all except MS (bit 15)
OR in addr of interrupt vector
and write it back to the VAR
; load interrupt vector with ...
... address of interrupt handler
; establish IPL of hnndler ~ 7
init TX::JONE iT'lterrui:,t flag
enable DESQA interrupcs
write addr of Tx BDL to DESQA
start the transmission

t:-:d-:ne

ilie,@lqacsr
#t:-:.Dd2.,@lqatll
@lqatlh

bis
mcv
clr

Wait for the interrupt flag 7XDONE to be set to '1' to signify
completion of transmission. Note that a real application program
would need a timeout check.
10$:

tstb
be'-!

ChE'•..;k tht.

txdone
10$
t3..ns:-.~---

1 ..

;

REPEAT
test TXDONE flag
UNTIL TXDONE i.; set to 'l'

.=,~~r 1.1E tc ver~.:~-~

t.hat

--._

t. ..-.:..."1smit ert.u!"'"s !"€.:·.,.:.-

occurred.
mov
bic

t:-:. bdl +bswl, rl
#AC<bitl5!bitl4>

cmp
beq

20$

#lastok,rl

rl := transmit status word 1
zero all except LASTNOT ...
... ar,d ERP.OR/USED
; IF NOT transmit error THEN DO
continue
; E!..~E DO

Error handling code should be pla~ed here.
20$:

rts

return to caller

; Transmit Buffer Descriptor List.
tx.bdl: .word
.word
.word
.word
.W{:.rd

unused
v!e
tx.buf
-tx.len/2
·:nuscd

flag word
Valid desc and End of Msg
address of transmit buffer
2s comp buffer word length
status wo~~ 411

D--15

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

.word

unused

; status word #2

Follow with an invalid descriptor.
.word
.word
.word

unused
invalid
0,0

; flag word
this descriptor is INVALID
dummy buffer address, length

Reserve storage for maximum length transmit buffer.
tx.buf:
tx. len

.blkb

1514.
.-tx.buf

; 1514 (Decimal) bytes

D-16

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

D.6

DATA RECEPTION

The steps required to initiate a reception are:
•

Set RE to l in CSR. This is not necessary if the DESQA is receiving a packet which was looped by Internal.
External, Internal Extended, or Setup loopback modes.

•

Write the 16 LOW-order bits of the Receive BDL address to the l/0 page low-order Rx BDL register.

•

Write the 6 HIGH-order bits of the Receive BDL address to the l/0 page high-order Rx BDL register.

The completion of the reception may be detected in one of two ways.
•

Polling the RI bit in the CSR with DESQA intelTUpts disabled.

•

Enabling the DESQA to intelTUpt the host when reception is complete.

*----------------------------------------------------------~---*

; *

* Routine to wait for a packet from the Ethernet.

* Polling is used to determine when a packet has been
* received.
; *

*
*
*
*

*--------------------------------------------------------------*

n:pktl: 1:-ic

4fie:!el,@J.1acsr

bis

#il!re,@lq3.csr

:no-....~

#n:.bdl, :alqa:::11
@lc;:arlh

clr

disable DESQA interrupts ...
... and loopback modes
disable Internal Loopback ...
... and enable receiver
writ.e add::: of Rx BDL tc DES~A
i::.it.,.ate a packet reception

""'-~ :'.:-;;::: R: t::, be :;e:;:.. '.k-;..Ec ~ha: a real aprlication program
~c;:~ r.eed a tirr.P~Ut c~ec~.
10S:

bit.
beq

4fr::.,@lqa.csr
10S

REPEAT
test RI bit in CSR
UNTIL RI= 'l'

~eset RI to '0' by writi~g a 'l' to it.
Must be careful to avoid accidentally resetting XI also.
rl := (CSR)

mov

@l.qacsr,rl

:Oic

h:i,;..l

xr := '8' ~o avoid w~ititig ...

mov

rl,@lqacsr

... a '1' to it
reset RI to '0' by writing ...
. . . a ' l' t.:> it

Check the receiv~ status to verify that no receive errors have
occ,.;rred.
i:,:.. _;

r)-:.bd:-bs;,;l, ::::1
#AC<b~t1S!bitl4>

beq

l<l;;stck,rl
2C$

r,.cv

rl := rec?ive: status w0rJ l
zero all except iASTNOT ...
... a~d ERROR/USED
IF N'.)T receive error THEN DO
;
continue
; ELSE DO

Error handl~~g code sh~uld be placed tere.
20$:

Calculate leng~h ir. ty~es of received packet.
NOTE : This assumes that the packet received is NOT a loopback
packet. Therefore, the receive length as determined from

D--17

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

the receive status words is 60 decimal less than the
actual packet length.
Additional code is required to handle the loopback cases.
mov
bic
mov
bic
add
add

rx.bdl+bswl,rl
#AC<rblh>,rl
rx.bdl+bsw2,r2
#AC<rbll>,r2
rl,r2
#60.,r2

rl := receive status word 1
zero all bits except RBLH
r2 := receive status word 2
zero all bits except RBLL
r2 := pkt length - 60 decimal
r2 := correct packet length

rts

return to caller

Receive Buffer Descriptor List.
rx.bdl: .word
.word
.word
.word
.word
.word

unused
V

rx.buf
-rx.len/2
unused
unused

flag word
Valid descriptor
address of receive buffer
2s comp word length of buffer
status word #1
status word #2

Follow with an invalid descriptor.
.word
.word
.word

unused
invalid
0,0

flag word
this descriptor is INVALID
dummy buffer address, length

Reserve sto:.age for maximum length receiv,:, buffer.
rx.buf:
rx.len

.blkb

1514.

1514 (Decimal) bytes

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

*--------------------------------------------------------------*

• *

* Routine to wait for a packet from the Ethernet.
*
* This routine waits for a Receive interrupt from the DESQA to*
; * to determine that a packet has been received.
*
; *
*

*--------------------------------------------------------------*

lqavec
pri07

400
340

rxpkt2: bic

he! el, @lqacsr

bis

#il!re,@lqacsr

DESQA host interrupt vector
Processor Status· of ...
; ... interrupt handler - IPL= 7
disable DESQA interrupts ...
... and loopback modes
disable Internal Loopback ...
... and enable receiver

We must write the address of the DESQA interrupt vector to the
VAR without altering the Mode Select bit (bitlS) in that
register.
mov
bic
bis
mov

@lqavar,rl
#~C<ms>,rl
#lqavec,rl
rl,@lqavE..:-

rl := (VAR)
zero all except MS (bit 15)
OR in addr of interrup~ vector
and write it back to the VAR

mov

#lqaint,lqavec

mnv

¥;::ri07,lqavec+2

load interrupt vector with ...
... address of interrupt handler
establi~h If~ of handlPr = 7

clrl:
bis
mov
clr

#ie,@2.qa::=-:hx.bJl,@l-::arll
~lqarlh

init RXG)NE interrupt flag
e:,abl<> r_ E.SQA i , 1 :er!"upt ~
wr i ;:.e add:· of R~: Ei:JL to DES QA
initiate the reception

Wa:_t for the interrupt flag RXDONE to be set to '1' to signify
completion of reception. NJte :hat a re3l application progr~~
would need a timeout check.

10$:

tst..b
beq

rxd::>•:,o
10$

REPEAT
test RADONE flag
UNTIL RXDONE is set to '1'

Chee~ the receive status to verify that no receive errors have
occu.:.red.
!'\OV

r;..:. bdl •!:'~w~ , ~:

b.:.c:

# '· C <bl t l :: ! i::. :_: l 4 >

#lastok,!"1
20$

r1 ·= receive statu~ word l
ZE:er::> all except LASTNG: ...
... a~d ERROR/USED
IF il0T receive sc:!"ror TEEN
-::ontinue
ELSE DO

Error hand2ing cede should be placed here.
20$:
Calculate length in bytes of received packet.
NOTE : This assur.es that the packet received is NOT a loopback
packet. Therefore, the receive length as determined from
the receive status words is 60 deci~al less than the
actual packet length.
Add'.r~o~al code is requ1.red to handl~ the loo~ba~k cases.
n:.bdl+bswl, ::::1

; rl := receive sta~us word 2

D--19

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

bic
mov
bic
add
add

#AC<rblh>,rl
rx.bdl+bsw2,r2
#AC<rbll>,r2
rl,r2
#60.,r2

zero all bits except RBLH
r2 ·= receive status word 2
zero all bits except RBLL
r2 ·= pkt length - 60 decimal
r2 ·= correct packet length

rts

return to caller

Receive Buffer Descriptor List.
rx.bdl:

.word
.word
.word
.word
.word
.word

unused
V

rx.buf
-rx.len/2
unused
unused

flag word
Valid descriptor
address of receive buffer
2s comp word length of buffer
status word #1
status word #2

Follow with an invalid descriptor.
.word
.word
.word

unused
invalid
0,0

flag word
this descriptor is INVALID
dummy buffer addres~, length

Reserve stcrage for max~mum length receive buffer.
rx.buf:
rx.len

.blkl::

1514.
.-rx.buf

1514 (Decimal) bytes

D-2~

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

D.7 EXECUTING ON-BOARD DIAGNOSTICS
The DESQA firmware contains self-test code which may be executed by setting the RS (Request to execute
Self-test) bit to I in the VAR. RS is cleared to Oby the firmware when the self-test has completed execution and
the self-test status bits are updated in the VAR.

*--------------------------------------------------------------*

,• *
,• *
,• *
,• *

Routine to start Self Test running and wait for the
results.

stast:

bis

*
*
*

; *--------------------------------------------------------------*
#rs,@lqavar

; request Self Test execution

; Wait for RS to be set to '0' again in the VAR. Note that a real
application program would need a timeout check.

lOS:

b~t
br.e

#rs,@lqavar

:cs

;

REPEAT
test RS bit
UNTI:;., RS
'0'

The Self Test s~atu~ is stored in VAR<l2:10>.
mov
b.:c

@lqavar,rl
i!~C<s3!s2!sl>,rl
2G$

"e!.i:

rl := (VAR)
clear all but Self Test ...
... .stati.;s bits
Self Test f0und no fault

Test has d1scc'!er.:d c. fot:lt in the DESQA.

E.r .ror lianc.:.c.r.•:; 1 -::-epc:-r!:ing :::ode sht:.uld be pla.::ed here.

?0$:

rts

; return to caller

D.8 BUFFER DESCRIPTOR MANAGEMENT ALGORITHM
(BDLs). The algorithm is described using pseudo code for the Transmit BDL, however this algorithm must be
used for hoth Transmit and Receive BDLs.
•

•

The host devict> driver manages each transmit and receive BDL as a "ring" or contiguous list of descriptors.
Each BDL must have at all times at least one invalid buffer des~riptor to terminate the BDL.
The ho,;t loads new BDs onto this BDL while the processing other BDs on the sarnl.' BDL.

•

The host ""locks"" it's own access to the BDLs hy perfom1ing all host RD loading and unloading at the same
Devi :e lnkrrupt Priority Level (IPL}. 1ht.s host unloading never intenupts hoi.t loading.
1

•

The host only specifies buffers in the receive BDL greater to or equal to 1518 bytes.

•

The host alway!. sets the Buffer Descriptor·s VALID bit 0<15> after the remaining descriptors fields are all
setup.

•

The host always clears th1.: Buff..:r Descriptor's VALID bit 0<15> after processing a completed descriptor
within the interrupt service routine.

D-21

PROGRAMMING EXAMPLES FOR PDP-11 SYSTEMS

•

BD RECOVERY ALGORITHM PART I: LOAD RECOVERY After the host sets the VALID bit in a Buffer
Descriptor (BD) with new data for the DESQA to transmit, it is recommended that the host use the following
algorithm with the BD just issued to the DESQA:
(DESQA CSR bit XL = 1)
if
then begin
(BO bit LASTNOT S<lS>
(BD bit ERROR
S<l4>
then begin

1) and
0)

Load address pointer of BD into DESQA
Transmit BDL Start Address Register.
end
end (* END OF LOAD BD ALGORITHM*)

•

BD RECOVERY ALGORITHM PART 2: UNLOAD RECOVERY In the host device driver's interrupt
service routine the following algorithm is highly recommended:
WRITE ONE TO CLEAR DESQA CSR BIT XI
start bd unload:
BD = NEXT BD TO BE RETURNED BY DESQA ON TRANSMIT BDL
if (BD VALID BIT D<lS>)
then begin

= 1)

(BD bit L~STNOT 5<15>
(BD c:t £RROR
S<14>
then begin

1) and
0)

\D~SQh CSR bit X~ = 1)
then begi!1
if

(BD bit LASTNOT S<lS>
and
(BD bit ERROR
S<l4>
then begin

1)
0)

Load address pointer of
BD into DESQA Transmit
BDL
Start
Address
Register.
end
end
else beg:.r.
process completed BD and then loop back
to "start bd unload:" to get next BD
which will be returned from the DESQA
on the transm~t BDL.
end
e:1d ( * E::::- CF :JN:...~.Z..D B'.:, h:.G'.)RITHI-'.

D-22

E
GLOSSARY

APPENDIX

This appendix defines some of the terminology of DESQA and Ethernet.
baseband system

In a baseband system, information is encoded and transmitted in a single frequency band. This means that only
one information signal at a time can use the transmission channel without disruption (see collision).
binary exponential backoff

The algorithm used to schedule retransmissions after a collision. So named because the interval between
retransmissions is increased exponentially with repeated collisions.
bit cell

The length of time occupied by one encoded data bit (see Manchester encoding). Equivalent to bit time.
bit time

Equivalent to bit cell. At IO MHz the bit time is 100 ns.

b.oadcast
In general, the mode of communications where all nodes are capable of receiving a signal transmitted by any
other node. Also, a specific Ethernet addressing mode where the destination ii, all nodes.
bulkhead
That part of the host system cabinet that provides for external connections to system modules; also known as the
'-Y~tem 1/0 panel. the distribJtirn1 panel.or the patch and filter assembly.
bulkhead assembl~·

An assembly ,:omprising the transcci, er cable. socket. transceiver fuse, and bulkhead p:mel insert.
carrier sense

The means by which the physical layer determines that one or more node~ are currentiy transmitting on tht:
Ethernet.
citizenship (CQ) test

This is a go/no go diagnostic test for the DESQA. The PDP- I I code that runs the test is held in the DESQA
boot/diagnostic ROM. It can be loaded into host memory and executed by the host.
coaxial C'able interface

The electrical, mechanical. and logical connection to the coaxial cable. In other words, the transceiver.
coaxial cable section

An unbroken piece of coaxial cable, fitted with coaxial connections at its ends, which is used to make up coaxial
cable segments.

E-1

.GLOSSARY

collision

The result of simultaneous transmissions by two or more nodes. Simultaneous transmissions diston each other's
signals, and the data must be retransmitted separately. Collision detect be asserted only during transmission
collision enforcement

Each node continues to transmit encoded frame bits after a collision has been detected. This makes the collision
last long enough for all transmitting stations to detect it. See also jam bits.
contention

Interference between colliding transmissions (see collision.) Ethernet link management resolves contentions (see

CSMA/CD.)
controller

A unit, such as a DESQA, which connects a node to the Ethernet.
CRC (cyclic redundancy check)

An error detection scheme. in which a check character is generated by taking the remainder after dividing all the
serialized bits in a block of data by a predetermined binary number. The check character is compared with the
transmitter-generated check character as a safeguard against errors in transmission.
CSMA/CD

Carrier Sense Multiple Access with Collision Detection. This is the generic term for the class of link management
procedure used by the Ethernet. So called becam,e it:
•

Allows multiple nodes to access the broadcast channel at will

•

Uses carrier sense and deference to avoid contention

•

Resolves c:1ntention through collision detection and retransmission.

data-link layer

The layer in which the modules create a communications path between two adjacent nodes. Data-iink module~
ensure the integrity of data transferred across the path. Data-link modules execute simultaneously and
independently in this layer. This is the higher of the two layers in the Ethernet local area network. See also
physical layer
DECnet boot

This is the PDP-I I code that the host calb to stan DECnet. The code is stored in the DESQA 8001/Diag.1~,1,tic.:
ROM.

deftrence
A rrocess by which the DESQA delays transmi.;sion when the channel is busy. in order to avoid contentior. with
on-going transmissions.

DESQA primary boot

That pan of th·.: primary bootstrap code in the: host that is specific to DESQA. See also extended primar.,·
bootstrap.
destination address

In the message packet. this is the 48-bit field that contains the address of the receiving node.
drop cable

See transceiver cable.

E-2

GLOSSARY

extended primary bootstrap

This is the PDP- I I code that the host calls from the DESQA Boot/Diagnostic ROM. The sequence is as follows:
I.

The DESQA primary boot loads the extended primary bootstrap from the DESQA Boot/Diagnostic ROM
into host memory.

The DESQA primary boot transfers control to the extended primary bootstrap.

The extended primary bootstrap uploads the entire contents of the Boot/Diagnostic ROM into host memory,
calls the citizenship (CQ) test, and does one of the following:
•

The bootstrap calls the DECnet boot.

•

The bootstrap transfers control to a user-supplied address.

If an error occurs, the bootstrap halts.