Digital PDFs

XX-2EC59-B2

2000

354 pages

Original

13MB

Document:	micronoteReprints
Order Number:	XX-2EC59-B2
Revision:
Pages:	354
Original Filename:	http://bitsavers.org/pdf/dec/qbus/micronoteReprints.pdf

OCR Text

u note Reprints
It took the minicomputer company to make micros this easy.

TABLE OF"CONTENTS
PAGE NO.
001
005
009
OIOA
011
012
013
014
015
017
018
019
020
021
023
024A
025
026
027A
028
029
030
032
033

BATTERY BACKUP
IEEE Bus SUB-SPECS
HEX AND QUAD HOLD-DoWN BRACKET FOR LSI-II
SYSTEMS
POWER SUPPLY FOR H909C
LSI-II HALTING DURING INTERRUPT CYCLE
LSI-II Bus THEORY OF OPERATION
INSTALLING APL-l1 ON 11V03 AND 11T03
CORRECT INPUT PARAMETERS FOR THE QJV1l PROM
FORMATTING PROGRAM
POWER SEQUCENCING FOR THE KD1l-HA MODULE
LSI-11/2 PROCESSOR CLOCK
DRl1-C vs. DRVII
EIA RS-422 AND RS-423
9 X 6 SLOT BACKPLANE DOCUMENTATION ERROR
COMPARISON OF DATA TRANSMISSION TECHNIQUES
USING THE MSVll-D 30K OPTION
ASYNC.~ SERIAL LINE UNIT COMPARISONS
CONFIGURING MEMORY SYSTEMS WITH MSVll-D
RAM & PROM
MICRO BACKPLANE MECHANICAL MOUNTING
GUIDELINES
PROM CHIPS AVAILABLE UNDER PART # MRVll-AC
EXTENDED MEMORY FOR THE LSI-II
USING THE MRVII-AA FOR A BOOTSTRAP ROM
SRUN SIGNAL
EXTENDED Bus TIME-OUT LOGIC
CABLES FOR DLVll~ DLVll-E~ DLVll-F

1
4
5
6
8
10
19
20
22
25
26
30
34
35
40
41
46

48
56

57
69
71
73
76

PAGE NO.
034
035
036
037
038
039
040
041
042
043
044
046A
047
048
049
050
051
052
053
054
055
056
057
058
059
060

CONFIGURING A 3-Box 11/03 SYSTEM
PROM PROGRAMMING
CORE MEMORY IN 11/03-L BACKPLANE
C-D INTERCONNECT SCHEME
DIAGNOSTICS FOR 30K MEMORIES ON LSI-II's
DMA REQUEST/GRANT TIMING
PATCHES FOR BASIC/PTS ON LSI-II
NEW FUNCTIONALITY FOR BDVll-AA BOOT
REMOVING f10DULES FROM "LIVE" BACKPLANES
BACKPLANES FOR THE RLVl1 (RL01)
CONSOLE ODT "L" COMMAND ON 30K SYSTEMS
DLVII-F REPLACEMENT FOR THE DLVII
INCOMPATIBILITY BETWEEN THE REVII AND
THE LS I-11/23
LSI-ll/23 INSTRUCTION TIMING (PRELIMINARY)
SYSTEM DIFFERENCES - LSI-II VS. LSI-ll/23
MICRO ODT DIFFERENCES - LSI-II VS. LSI-ll/23
DIGITAL SUPPORTED PROM's
PARITY MEMORY IN LSI-ll/23 SYSTEMS
PDP-II FAMILY DIFFERENCES
MXVII CONFIGURATION
LSI-II VS. LSI-ll/23 Bus TIMING
DLVII-J CABLI NG
LOCATION OF W13 ON THE BDVII
CONFIGURING MEMORY FOR LSI-II SYSTEMS
WITH MORE THAN 64K BYTES
l~J--ll/2? FOUR-LEVEL INTERRUPTS
MAXIMUM CONFIGURATION OF DLV11-J MODULES

78
80
81
82
85
86
88
90
91
93
95
96

99
101
111
113
116
117
125
136
141
143
147
149
155
162

PAGE NO.
061
062
063
064
065
066
067A
068
069
070
071
072
073
074
075
077
078
079
080A
081
082
083
084
085

PROGRAMMING THE MRV11-C
BOOTSTRAPS FOR TU58 1 RL01 1 RK05 1 RX02 1 RX01
RLOI TYPE-IN BOOTSTRAP
DLV11-J 1/0 PAGE ADDRESS PROBLEM REPORT
BOOTSTRAP FOR RX02
11/23 FLOATING POINT CO~IPATIBILITY
DLV11-J RECEIVER CHIP PROBLEM
MICROCOMPUTER MODULE ENVIRONMENTAL
CONSIDERATIONS
18-BIT DMA WITH CHIPKITS
LSI-II vs. LSI-11/23 TRANSACTION DIFFERENCES
EXPANDING BA11-MA AND BA11-NC BASED SYSTEMS
PERIPHERAL COMPATIBILITY WITH 11/23 SYSTEMS
TU58 CABLING
MXV11-AAI -AC CABLING
MXV11-A2 BOOTSTRAP ERROR HALTS
SUMMARY OF BOOTSTRAP SOURCES
LSI-11/23 PROCESSOR DIFFERENCES
THE LSI-11/23 AND THE LSI-11/2 BUSES ARE
THE SAME
LSI-11/23 1/0 PAGE ADDRESSING
USE OF RECOMMENDED DISKETTES
HANDLERS FOR SERIAL LINE PRINTERS
ALTERNATE CLOCK FREQUENCIES FOR THE MXV11
IMPROVED DLV11-F
WAKE-UP CIRCUIT IMPLEMENTATIONS

164
173
204
205
207
210
211
213
214
216
218
221
223
225
227
230
231
233
234
236
237
248
250
252

NUMBER

).Inote

TITLE

001
DATE

BATTERY BACKUP

DISTRIBUTION
ORIGINATOR

/ 1

/77

PRODUCT
MSV11-C (M79SS)

UNRESTRICTED
JOE AUSTIN

PAGE 1 OF3

SCOPE
The function of this note is to furnish the information necessary
to provide battery backup for the MSVII-C 16K MaS RAM module.
Specific recommendations for the battery, charger, and DC-DC
converters will not be covered at this time.
Additional information on the MSV11-C is contained in the
"MSVIl-C Users Manual", document number EIC-NSV11-0P.
SYSTEM DESCRIPTION
A block diagram showing two MSVI1-C aodules providing 28I words
of memory is shown in Figure 2. Bach 16K module is plugged into
a standard backplane with the battery power connected to pins
AVI (+SV) and ASl (+12V) as shown. These two voltages are
sourced by DC-DC converters/regulators which are connected
directly to the battery. A charger is provided which is
connected to the battery and converters by control logic. The
function of the control logic is to disconnect the charger
when AC power is lost, to disconnect the battery from the
converters when it discharges too low, and to switch to a
trickle-charge once the battery has been fully charged.
FUNCTIONAL REQUIREMENTS
To properly implement this system, the following conditions must
be met:
l~

The battery power required to back up the two modules is:
+SV +3'
+12V +3'

1.6 A type (2.8A aax)
0.32 A type (O.4A max)

These voltages must remain within +3' of the voltages for
the LSI-II at all times, and aust not change by aore than
+3\ during the transition~DD~erom the battery.

COMPONENTS
GROUP
1

)Jnote
2.

NUMBER 001
PAGE 2 OF3

All MSVll-C modules using battery backup aust be at etch Rev. D.
Those modules at etch Rev. C must have ECa No. I for aodule M79SS
installed. This ECa adds the circuit shown in Figure 1 in the
following manner:
•

cut the etch to free pins E31-S and E31-10

•

add wires from E18-12 to E20-9
E19-12 to E20-10
E20-14 to E31-S &10

The following jumpers should be configured as shown:
WI. WS - Remove to separate the battery power from the bussed system
power.
W2. W3 - Insert to connect the battery power to the refresh logic.
W6 • • 7 - Insert to enable internal refresh and to prevent the aodule
from asserting BRPLY during refresh.

The heat generated by the refresh logic on each MSVII-C is 8 watts.
Alternate cooling .ust be providfed to dissipate this heat if the
AC fans are off for aore than tWiO minutes.

Certain precautions should be tajken in the design of the power
sequencing logic and other specilll modules. Signal BSYNC m,st be
driven by a source tbat has a hiJ~h impedance when power is removed
from the rest of the system. Signals BDCOK and BPOK must be driven
by a low impedance source (less than 8 ohms) under the same condition
and should have no bounce (no relay). A J-FET is recommended since
it also provides the necessary rise and fall times. These precautions have been taken in those systems using the H780-H or J power
supply as provided by PDP-ll/03 ()r PDP-IIV03 systems.

All master (DNA) modules aust fiIlish gracefully when BPOK indicates
an AC power failure. Any cycles in process .ust be allowed to
finish. should be off the bus within two microseconds. and must not
hang up signal BSYNC.

The software .ust finish its powE~r-down procedure and issue a HALT
instruction within two milliseconds from the time signal BPOK
indicates an AC power failure.
(EI8-12) DCOK L
(EI9-12) Lockout H

:01

8:::~ Lockout AL(E31-S 10)
&

FIGURE I~Dm_LOGIC

COMPONENTS
eiReMlP
2

NUMBER 001
PAGE 3 OF 3

FIGURE 2.

TYPICAL BATTERY BACKUP SYSTEM

MSV11-C
16K

MSV11-C
12K

BACKPLANE
AV1*
AS1*
GND

+5V

+12V

+5 DC-DC
CONVERTER

GND

+12 DC-DC
CONVERTER
DC

CONTROL LOGIC

BATTERY
CHARGER

BATTERY

AC INPUT

~D~DDmD
COMPONENTS

GROUP
3

NUMBER
DATE

TITLE, __~I~E~B~E~B~U~S~S~U~B~-S~P~B~C~S____._____________
DISTRIBUTION....-_l~B~V~I~l_C~U~'S~T~O~ME_RS~.____------____

ORIGINATOR

PRODUCT

JOB AUSTIN
PAGE

The IBVII-A, when connected to the LSI-!l, will meet the following
subsets of IBEE Standard 488-1975:
SHI
AHI
TS

TBS
L3
LB3

SRl

RLI
PP2
DCI
DTl

CI
C2
C3
C4
CS

This module is designed to be th4! only controlle1" on the IEEB bus.
Therefore, it will not respond to another controller on the bus
that issues either a parallel' poll configure command or a parallel
poll control signal (subset PP2)~

~IJ~DDmD
COMPONENTS
CiROUP
4

NUMBER

),Inote

009

DATE

·'ITLE

HEX AND ~UAD HOLD-DOWN BRACKET FOR
LSI-II S STEMS
HSTRIBUTION
UNRESTRICTED

DRIGINATOR

/ 77

PRODUCT LSIo.ll
M ~UNTING

JOHN HUGHES
PAGEl

HARDWARE
Oli

Here is a product that will help in applications that require a
mechanically rigid system with double-sized modules in a 4x4 backplane or any time the 9x6 backplane is used. The hold-down bar
that is described in the following clipping from the 1977-78 Logic
Handbook (page 369) describes the same hold-down bracket that is
u.sed on quad-sized modules, like the LSI-II processor and the MSVII-CD
memory board.
To use this bracket, customers can drill out the existing handles on
double or quad-sized board and attach the bracket by means of either
rivets or screws.
In addition to offering increased rigidity and resistance to vibration,
this bracket makes insertion and removal of modules far easier.
Hold-Down Bracket 12-10711'()2
The 12~10711-02 module hold-down bracket serves as a mechanical combination handle arid hold-down bracket for Hex-size modules when used with
the appropriate cards guides such as an' H0341. .This bracket can also be
used as a hold-down bracket for LSI-ll compatible modules (quad-size) but
must be modified as shown in the accompanying drawing.

LSI-ll HOLDOWN 12-10711'()2
1_ CUT BRACKET AT POINTS DESIGNATED ON DRAWING BELOW.
2. DISCARD CENTER SECTION "B".
3. MOUNT SECTIONS "A" AND "C" ON BOARD AS DESIRED.

'CtIT ~f THI!SE

IOINrs

~D~DD~D
COMPONENTS

GROUP
5

NUMBER

).Inote

010A
DATE

TITLE

Power Supply For H909C

DISTRIBUTION
ORIGINATOR

PRODUCT

H909C Customers

H909C

David Schanin

PAG~

of2

THIS MICRO NOTE REPLACES 1010. 1010 SHOULD BE DISCARDED AND
REPLACED WITH THIS ONE AS IT WAS IN ERROR.

----------------------------~-------~~------------------~----

The H909C Expander Box is a convE~nient" way to package the DDVI1-B
9x6 ba~kplane with the H0341 card guide. However, the H780 power
supply may not be used with the H909C because air flow from the
power supply fans will be restricted. Customers must provide
their own power supplies and provide for cooling of both the
LSI-II cards and the power supplies.
There are two configurations of I"ambda power supplies that have
the potential of powering the H909C module systems enclosure.
One is a 148-watt configuration that sells for $400 and the other
is a 321-watt configuration that sells for $760.
The 321-watt configuration requires two +12 volt supplies to be
connected in parallel. This is accomplished by connecting a
diode in series with each positi,re output and connecting the sense
input on the load side of the diode. One supply will current
limit and the other will regulatE~. The diode is to protect the
over-voltage protection circuit.
CONFIGURATION ONE
QTY

MODEL

VOLTAGE

CURRENT

PRICE

POWER

LJS-11-5-0V
LJS-10-12-0V

5V
12V

20A
4A

$220
$180
$400

100 Watts
48 Watts
148 Watts

CONFIGURATION TWO
QTY

MODEL

VOLTAGE

CURRENT

PRICE

POWER

1
2

LGS-5-5-0V;"R
LJS-10-12-0V

5V
12V

45A
8A

$400
$360
$760

225 Watts
96 Watts
321 Watts

~D~DD~D
COMPC)NEMTS
G~OUP

).Inote

NUMBER 010 A
PAGE 2 OF 2

The KPVll-A can be used to generate the power fail/restore signal
sequence and line time clock normally provided by the H780 plower
supply. An H780 control panel may also be interfaced to the
LSI-II via the KPVII-A.

NOTE:

DUE TO PHYSICAL AND COOLING LIMITATIONS I THE H780 POWER
SUPPLY CANNOT I UNDER ANY CONDITIONS I BE USED IN THE HgOge
BOX.

~D~DD~D
COMPONENTS

GROUP
7

NUMBER

).Inote
TITLE

011
DATE

LSI-II Halting During InterruEt Cr cle

DISTRIBUTION
ORIGINATOR

/77

PRODUCT

LSI-II Customers

General

Ted SemEle
PAGEl

OF2

An unusual sequence of events may cause the LSI-II processor to
HALT during an interrupt cycle. The problem occurs when an I/O
device requests interrupt service simultaneously with an instruction being executed to reset the interrupt enable bit for the
particular interrupt request.
An internal flip flop in the CPU chip set is set by the leading
edge of an interrupt request. The processor responds by first
completing execution of the current instruction and then asserting
BIAK to grant the interrupt. The interrupt grant is then passed
in daisy chain fashion down the bus to the board that made the
request. However, if the instruction being executed resets the
interrupt enable bit, the boarel will not realize that it was the
one that generated the request and will, in turn, continue the
daisy chain of the grant down the bus. If no other board has
an interrupt request pending, the interrupt grant will pass all
the way to the end of the bus and 12 us. later, the processor
will time out and enter the HALT mode. This scenario, although
unlikely, may be the cause of some previously unexplained CPU
HALTs.
These false interrupts can be t~liminated by modifying software.
Before clearing an interrupt enable bit, all interrupts should
be disabled by setting bit 07 of the PSW. To avoid needless
interrupt latency, bit 07 of the PSW should be cleared as soon
as possible after the interrupt enable bit is cleared.
The same scenario occurs in noisy environments when the BIRQ
signal line is glitched by noise. In this case, a BIAK will be
issued by the processor when no board has made an interrupt
request.
There is a solution for this problem for those customers who are
not using system software packages such as RT-ll. This solution
may be implemented by adding a single strap to the backplane and
by a simple software modification.

~D~DDmD
COIIlPONENTS
C~ROUP

NUMBER 011
PAGE 2 OF 2

On the last slot used on the backplane pin AN2, BIAKO, should. be
connected to pin AF2, BRPLY. During program loading, address
location 000000 should be loaded with 000002 and location 000002
should be loaded with 000002.
These modifications will cause the following sequence to occur.
When an interrupt acknowledge is not captured by a module, the
interrupt acknowledge itself becomes the reply to that interrupt
acknowledge. The processor, seeing a reply, will assume that a
vector is on the bus. The bus, being in a floating condition, is
equivalent to having a 0 vector. The processor then fetches
the contents of location 000000 and stores this in the program
counter, register 7 of the processor. Next, the processor fetches
the contents of memory location 000002 and loads that into the
processor status word. As with any interrupt cycle, the processor
then begins to execute the program whose starting address is now
in register 7. In this case, the processor will begin executing
a program starting at memory location 000002. The instruction
in this location is an RTI, Return from Interrupt. The RTI instruction causes the processor to return to the original program that
was falsely interrupted, and the operation will continue as if
the interrupt never occurred.
CAUTION:

This solution should only be used with operating systems
that do not use memory location 000000. RT-11 and other
operating systems use location 000000.

~D~DDmD
COMPONENTS
CiROUP

1ITLE

)./note

NUMBER

LSI-II Bus Theorl of 0Eelati~

7
/11
PRODUCT

012
DATE

LSI-ll Customers

I ISTRIBUTION

fl9270j DDVII-B

Ted SemEle

( RIGINATOR

PAGE 1

1.0

/77

OF 9

PROPAGATION DELAY &REFLECTIONS

If a voltage is supplied between any two conductors, they Ilay be considered as a transmission line. The ideal transmission line input
impedence looks like pure resistance but, in fact, is mainly a combination of capacitance and inductance (see Figure 1).
When the voltage at one end of the transmission line is changed, that
change does not instantaneously appear at the other end. There is some
delay, which is called propagation d.elay (see Figure 2). The propagation delay of LSI-II bus cable is approximately 1.4 to 1.9 ns. per
foot (or .0348 a).

Figure 1.

Transmission Line Circuit Example

L
------------~.I
r~~--------~Transmission
Line

~I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

•

I
I

I
I
I

I
I
Pel

....I

U'" I

fI'ItOfI•••
"LAY

Figure 2.

•

Cable :Delay Example

mD~mlDmD
COMPONENTS
GRe...P
1C)

)Jnote

NUMBER 012
PAGE 2 OFg

A lossless transmission line of infinite length looks like a pure
resistance of value Z • L/C. If such a line is broken and terminated
with a resistor of this value (R • Z), the line will behave like an
infinitely long line; i.e., appear resistive (see Figure 3). The
impedence (Z) of LSI-II bus cable is approximately 120 ohms.

Z • 120U

.. cn .....MAT....'

Figure 3.

Cable Impedence Exaaple

When a voltage is applied to the line, the instantaneous power consumed
will be:
P • E2/Z
P • E2 /120
Suppose now that the terminating resistor (R) is not equal to the
characteristic impedence of the line. The power which is traveling
down the line before it reaches the termination (during propagation
delay) is equal to E2IZ, but the power dissip!ted in the resistor after
propagation delay is approximately equal to E IR.
If resistance (R) is greater than the impedence (Z), there will be
extra energy available at the termination and since energy cannot simply
disappear, it will be reflected back int'o the line. After one more
propagation delay (for the return journey), this reflection will be
seen back at the source (see Figure 4A).
CAl

ClOURCEI

ell

I
I
I

I
CTERMINATIONI

I
I
I

I
' I

I
I

, I

. . - N, ~ ..... .....1.- .....

Fi,ure 4.

-+ ...

~ HI-.I
I

Iapedence Mismatch Example

~DmDDmD
COMPONENTS
GROUP
11

j../note

NUMBER 012
PAGE 3 OF9

Some of this reflection will be dissipated by the source impedence
and some will be re-reflected back into the line. When this rereflection is seen at the termination (Figure 4B), (after still another
propagation delay), the energy difference will be reflected back to
the source. Eventually both source and termination will arrive at the
same level. The important point to note here is that what was intended
to be a level change with a clean, transition did not turn out that way
on the line due to a termination mismatch between Rand z.
Essentially the same situation oc,curs when the termination resistor is
smaller than the characteristic impedence of the line. If resistance
(R) is less than impedence (Z), there will be a mismatch and this will
also be reflected back to the source (see Figure 5).

ISOU.CEI-r
I
I
I
fTE.MINATION)

_ _.....Ii..-_._ _....

ltd

Figure S.

Iapedence (Low Resistance) Misaatch Example

Note that: (a) transmission line which is not terminated in its
characteristic.impedence w~ll have refle~tions and (b) the voltage
seen at any p01nt on the 11ne or at any 1nstant in time will be a
combination of the incident and reflected voltage.
The amount of reflection depends on the mismatch, and approaches
100 percent for either a shorted or an open line (see Figure 6).

~II~DD~D
COMPONENTS
CiROUP
12

.,....
alfLECTION

).Inote

NUMBER 012
PAGE 4 OF9

1------:...--+--=:;;;;;;;.....-----

Figure 6.

Misaatch Reflection Curve Exaaple

Essentially the same thing happens on the negative going edge of a
level change so that what seemed to be a clean transition as in
Figure 7A may look aore like Figure 7B.

..
Figure 7.

Cable Mismatch (Waveform Example)

To further compound the problem, each device on the bus contributes
its own unique impedence and mismatch in complex time relationships
(Figure 8).

~D~DDmD
COMPONENTS
GROUP
13

NUMBER 012
PAGE 5 OF 9

-...

r------"'\I ----'-r-------t
LIOUtleE

.1-.

WCI

-1-IOUtleE

C:"

loutlet

Figure 8.

System Devicn Iapedence Example

All of this impedence and resistance Ilismatch is normal and to be
expected in LSI-II bus systems. The objective here is to point out
the possible impedence mismatch and how to use the appropriate tools
to minimize the effects of reflections and "noise".

1.1

LINE TERMINATION TECHNIQUE

The question may be asked, how can a 178 and 383 ohm resistor properly
termina te aline which has an impedenc:e of 120 ohms?

~D~DD!~D
COMPONENTS
CiROUI)
14

NUMBER 012

)Jnote

PAGE 6

OF9

A perfect power supply has an AC resistance (impedence) of zey'o ohms,
so for AC considerations the termination diagram changes somewhat to
that shown in Figure 9B and siap1ified in Figure ge.
z • 110 U

'N"

IAI

Jan

Z - 120 n

.,u

1" 1/

'oF
+IV
fI'OWER

IUPPLY

-=J:
1-12011

ICI

Figure 9.

'm~,:

•

1,:'11"

Line TeI11lination Technique Example

The choise of these two values satisfies both the quiescent condition
and the required termination·impedence.

2.0

AC LOAD

An AC load is defined as a number related to the impedence that a bus
element presents to an LSI-I1 bus signal line (due to backpla.ne wiring,
PC etch runs, receiver input loading, and driver output loading).
This impedence load on a transmission line causes a "reflection" to
occur when a step is sent down the line. This reflection shows up
on an oscilloscope as a spike occurring shortly after an asserting or
unasserting edge. An AC load is nominally 9.35 pf. of capacitance~
Nine lump~d AC loads reflect 20 percent and 20 lumped AC loads reflect
40 per.cent of a 2S ns. risetime step. AC loads must be distributed

~D~DDmD
COMPONENTS
GROUP
15

NUMBER 012
PAGE 7 OF9

on the bus in the aanner described in the LSI-II Configuration
Guidelines in order to provide bus operation with reflections
guaranteed to be at or less than a tolerable level. The AC load
rating of LSI-II bus elements is usually based on the greatest of
the capacitances that the element :presents to the BDOUT, BDIN,
BRPLY, BSYNC, BREF and BSACK signal lines. If the element is
customer-designed, its AC loadin~ lnust be determined from a reasonable
estimate of the equivalent capac1tance presented to the LSI-II bus.

3.0

DC LOAD

A DC load is defined asa number related to the amount of DC leakage
current that a bus element presents to an LSI-II bus signal line which
is high (undriven). A DC load is nominally 105 uA (80 uA - receiver
plus 25 uA - driver). However, the DC load rating of a bus element
is not strictly based on the element's signal line that has the greatest
leakage, (e.g., DC leakage is less important on BDAL lines than it
is on BSYNC). The DC loading of an element should always be obtained
from the specification for that element. It should not be obtained
from a calculation of the receiver and driver leakage current, unless
the element is custom-d.esigned and is not listed in the applicable
documentation.

4.0

LOADING RULES
4.1

In multiple backplane systems, each backplane can have
up to 20 AC loads. If a load is too large, it may
generate a reflection on the LSI-II bus large enough
to create a false logic signal and cause a failure.
Figure 10 illustrates such a failure. The reflection
may cause the threshold of the 8640 receiver to be
crossed a second time.

(DRIVER WAVEFORM)

(REFLECTION
flllK)Wl LYMPeO

(NET WAVI'ORM

AT . .CIIVI..

Figure 10.

AC Loading Violation

~DI~DD~D
COMPONENTS
C;~tOUP

NUMBER 012
PAGE 8 OF 9

).Inote

To avoid this problem, some of the modules should be
moved to another backplane. Best results will be
obtained when the AC loading of all backplanes is equal.
4.2

In single backplane systems, the number of AC loads.is
limited by the bus termination impedence. The RC t1me
constant of the loaded backplane determines the rise
time of a signal line when a driver unasserts that line.
If the maximum RC time constant is exceeded, the signal
may not rise within 2S ns. (see Figure 11). 2S ns. is
the maximum delay permissible and still meet bus timing
requirements.
(" Max. RC Time Constant
'Q!
/

Typical Backplane
Signal

, ",'"
(71"

,'~

Unacceptable RC Time
Constant

/ /r:="'------- Receiver Threshold
/

/, "
/,,,,,

---".....-Max.

Delay
~ Time

Figure 11.

Single Backplane Signal Waveform

To slow a rise time may also cause the output of some
bus receivers to oscillate as the input signal rises
through the receivers threshold.
5.0

DC LOADING RULE

The maximum number of DC loads in either a single or multiple backplane
system is 20. If too many DC loads are put on the bus, the quiescent
undriven voltage may be lowered to a level where bus receivers become
susceptible to reflections from lumped loads and the overall noise
margin on the high end (bus undriven) may become too small.

~DmDD~D
COMPONENTS

GROUP
17

)lnote
6.0

NUMBER 012
PAGE 9 OF p

CABLING RULES

In multiple backplane systems, the c:ables must be at least 2 feet long.
If a cable is less than 2 feet long, the system will behave like a
single backplane system.
In multiple backplane systems, the c:ables must be at least 4 feet
different in length. When this rulE~ is violated and a driver in the
middle backplane unasserts the bus, reflections from the other backplanes will arrive back at the middle backplane simultaneously and
superimpose. The net reflection may cross the 8640 threshold and cause
a failure (see Figure 12). When thE~ cables are different lengths,
the reflections will arrive at slightly different times (see Figure 13).

----v- -ff-t

-----y-- +

+
\.

---IINGT. . . . . . .

I
I

O"'VE"
WAVI ..O ....

"IFLICTION
PM".NO

'-~

. , IU'IN

NIT WAVI"O" ..
A'A"ICTIO
UIMHOLOAO

"IU,OUT

Mau

Figure 12.

"IFlECTION
NOM.NO

caeu

Violation Of Ca.ble Length Rule Waveform

--v- + ----yI

I
I

1'2

\.
DAIVE"
WAVEfO...

"EFlECTION
.. "OMINO
0' .U"N
CAeli

Figure 13.

["UlECTION
IJtHt".NO
flW ev'OUT

)

NET WAVffO" ..

ATU"fCTlO

~L"

•

Proper Cable Length Rule Waveform

~D~DDmD
COMPONENTS
GROUP
18

'f/

NUMBER

).Inote

013
DATE

Installing APL-11 on 11V03 & 11T03

TITLE

All APL-11 Customers

DISTRIBUTION
ORIGINATOR

PRODUCT

APL-11

Rich Bi1liS
PAGl

oF!

When installing RT-11 APL on an 11V03 or 11T03 system, you must
consider two options:
•

Choice of:

•

SINGLE PRECISION variables

(7 decimal d.igits
of precision), OR

DOUBLE PRECISION variables

(17 decimal digits
of precision), AND

KEV1l optional hardware

Unless the application requires high preclslon, we recommend
choosing SINGLE PRECISION for speed reasons.
To choose the correct APL interpreter file for your configuration,
refer to the following table:

KEVIl
PRESENT?

SINGLE PRECISION

DOUBLE PRB eI S I ON

YES

APL04.SAV

APL03 . SAV

APLOO.SAV

APL01.SAV

~DmDD~D
COMPONENTS

GROUP
19

NUMBER

).Inote
Correct Input Parameters for the

TITLE

DATE

QJV11 PROM Formatting Pr()gram

DISTRIBUTION
ORIGINATOR

014

All QJV11 Users

/28

PROijffili

Dave Schanin

PAGE 1 OF 2

The document that is shipped with the QJV11 PROM Formatting
Program has a serious error in it. The document is in the
process of being corrected, but until such time, Chapter 7
of the Microcomputer Handbook should be used as a guide to
using the QJVl1.
The error is in the description of the answers the user is
supposed to give to questions printed by QJV11. A sample
typeout is listed below:

PROM V01·OO
ENTER AN OCTAL VALUE IN RESPONSE TO QUESTIONS
WHICH REQUIRE A NUMERIC RESPONSE. TYPE 'Y' FOR
YES AND 'N' OR NOTHING FOR NO. TERMINATE ALL
RESPONSES WITH A <CR> (CARRIAGE RETURN).
RUBOUT MAY BE USED TO DELETE ONE CHARACTER AT
A TIME BEFORE <CR> IS TYPED. CTRL/U MAY BE
USED TO DELETE THE ENTIRE RESPONSE. CTRl/O
MAY BE TYPED TO TURN OFF OUTPUT TO THE
TERMINAL.

Initial
Message

HOW MANY WORDS ARE IN A PROM!' --.,;..::.
HOW MANY BITS ARE IN A PROM WORO?_
HOW MANY PROMS ARE USED IN PI'RALLEL? _
ARE THE DATA BITS INVERTED? _
ARE THE ADDRESS LINES INVERTE[)? _
HOW MANY BYTES ARE IN THE AREP, TO BE
OUTPUT? _
WHAT IS THE STARTING ADDRESS C)F THE AREA TO
BE OUTPUT? _
IS YOUR INPUT/OUTPUT DEVICE ON THE HIGH SPEED
READER/PUNCH? ....
READY INPUT, TYPE <CR> WHEN FtEADY. <~>

Input
Parameters

oo"yotJ WISH TO PUNCH TAPES?

,):
DO YOU WANT TO VERIFY A TJ.PE? Y.
READY INPUT, .TYPE <CR> WHEN READY. <CB>
DO YOU WANT A LIST OF THE PROM CONTENTS? Y
DO YOU WANT iT ON A UNE PAINTER? ,!j

~D~mIDmD
COMPONENTS
CiRC....P

2Ct

QJVll
)

Operation

j../note

NUMBER 014
PAGE 2 OF 2

The proper responses, based on the type of PROMs used, are listed
below. Note that all of this information is copied from the
Microcomputer Handbook.

T... 7·5

QNl1 Input hrameters

MRVll-AA ~ons

MRVU-BA Applbtions

h ...rneter

512 X 4 PROMs

No. words ~n a PROM (N.)

1000

400

2000

N
Y

N
N

20000

10000

20000

0. 20000. 40000.
60000. 100000,

0. 10000. 20000.
30000, 40000,

0. 20000, 40000,
60000, 100000,

etc.

No. bits in 8 PROM
word (N s)
No. PROMs used in Pllrallel

Ale data bits inverted
Ale addr. lines inverted
How many bytes in the area
to be output (N.)
Starting Address

1/0 device on the H.i.
Nader I punch

256 X 4 PROM.

YorN

~D~DDmD
COMPONENTS
GROUP
21

YorN

lK X 8 PROMs

YorN

NUMBER

).Inote

015
DATE

Power Sequencing for the KD11-HA Module

TITLE

DISTRIBUTION
ORIGINATOR

11 /

/77

PRODUCT

Unrestricted

KD11-HA

Dave Schanin
PAGE 1

OF 3

The KD11-HA power-up and power-down sequencing functions are exactly the
same as on the KD11-F. The user may select anyone of four power-up
modes:
Mode

Start-up Function

PC at 24, PS at 26
OOT microcode
PC at 173000
Reserved microcode

1
2
3

Power-Up
On all KOl1 s, there are two methods (not modes) to start the LSI-II and
cause it to power-up through the selected mode:
1

Method 1:

Use an H780 power supply or KPV11 power sequence module.
They function as follows::
a)

DC power is applied to the backplane, while BPOK
and BOCOK are asserted.

3-10 ms. following DC power application, BOCOK is
released. At this time, the CPU comes up, does a
fast DIN on location 4 (a DIN which ignores the actual
contents of location 4), and in doing so reads the
power-up jumpers and the state of BPOK. The CPU
senses BPOK is asserted and continues looping.

70 ms. (min.) followi'ng the release of BDCOK, BPOK
is released. The CPU, which had been looping on
reading the BPOK linE!, now senses that BPOK has
been released and jumps to the location specified
by the power-up jumpe!rs.

~D~DD~D
COMPONIENTS
GROUP

)lnote
Method 2:

NUMBER015
PAGE2
O!

Use a pushbutton. Connect a pushbutton, preferably
debounced, to the BOCOK line. This pushbutton should
allow BOCOK to float when the button is released, and
should assert (ground) BOCOK when the button is
depressed. This method functions as follows:
a)

DC power is applied. BOCOK and BPOK are released.
The CPU is in an undefined state and will not run.

The pushbutton is depressed following DC power
application and, therefore, BOCOK is asserted. As
long as BOCOK is asserted, the CPU is in a reset
condition and non-functional.

The button is released so BOCOK is released. The
CPU comes up, does a fast DIN on location 4, reads
the power-up jumpers, and the state of BPOK.

Since BPOK is not asserted, the CPU jumps to the
location specified by the power-up jumpers.

Power-Down
On all K011's, two power-down methods exist:
Method 1:

Method 2:

Power-fail detection. This requires a KPV11 or an
This method allows for detection
of AC loss by causing a trap through location 24. The
CPU then has 4 ms. to complete its transaction and
halt. This method works as follows:

H780 power supply.

Upon AC loss, BPOK is asserted. This causes a trap
through location 24. The power supply ride-through
will maintain DC power for 4.05 ms. (min.) beyond
AC power loss. The user software must complete a'll
housekeeping functions in less than 4 ms. and halt.

4 ms. following BPOK assertion, BDCOK is asserted
suspending CPU operations, locking out core memory
access, and initializing peripherals.

5 us. following BOCOK assertion, DC power is lost.

Non power-fail detection. Loss of DC power, while BOCOK
and BPOK are released. Under this method, DC power is
simply shut off to the backplane. The CPU may lose power
anywhere in a bus or execution cycle and may cause any
random event to occur on the bus or at a peripheral due
to the unknown state of all devices on the bus as they

~D~DD~D
COMPONENTS

GROUP
23

j../note

NUMBER015
PAGE3 AS:

randomly lose power. This is unacceptable in a core-based
system since the core contents may get "scrambled".
However, in a MOS RAM system where the peripherals
cannot cause damage Olr harm to anythi ng shoul d they
execute a random operation, this power-down method is
perfectly acceptable.
How do these power-up and power-down ml~thods affect the new KDII-HA? For
most applications, the only requirement is automatic power-up and -down,
as outlined in Method 2. Full sequencl~d power-up and -down, Method 1, is
usually only required for core based systems. Therefore, the KDII-HA
incorporates a "wake-up" circuit which automatically powers up and down
the CPU according to Method 2 (i.e., no power-fail detection) with no
external hardware requirements. Essentially, the "wake-up" circuit consists of a single shot tied to the BDCOK line which is asserted following
the application of +5 volts backplane !power. Since this single shot only
is tied to +5, +5 and +12 must come up within 50 ms. of each other to
insure reliable power-up. See Micro Note #016 for recommended power
supplies.

CAUTION:

MSVII-B memories should not be used as bank 0 memory on the
KDII-HA unless it is ECO REV E or higher. Failure to use
at least a REV E board will result in inability of the
KDII-HA to power-up (note that external refresh is required
from the REVll). The reason for this is that on REV D or
lower MSVII-B ' s, the negative voltage charge pump will not
attain operating voltage before the KDII-HA does a fast
DIN on location 4 to read the power-up jumpers. If
location 4 does not reply, the CPU will hang, and never
power-up.

~D~IJD~D
COMPC..ENTS
CRC)UP
2i~

NUMBER

).Inote

017
DATE
11 /28
PRODUCT

LSI-11/2 Processor Clock

TITLE

DISTRIBUTION
ORIGINATOR

Unrestricted

/77

KD11-HA

Ron Young

PAGE 1 OF1

The CPU clock is a crystal controlled (non-adjustable) clock that will set
the machine cycle time to 380 ns. + .01%. This should, at last, lay to
rest any competitor's claim that we have to "tune" the clock to make the
CPU work.
The tight tolerance on the clock will serve to tighten system performance
between systems.
In addition, the 380 ns. figure was selected to optimize CPU--memory
performance for our new memory offering without impairing performance
with our older memories. This marriage of CPU and memory will serve to
further enhance system performance.
NOTE:

It has been brought to my attention that customers have been
using "instruction loops" for timing purposes. This is not a
good method for marking time. One must consider that the memory
has "refresh cycles" to perform which can add time to the
instruction execution time. This makes exact execution time
impossible to calculate.

~D~DD~D
COMPONENTS

GROUP
25

NUMBER

).Inote

018
DATE

TITLE

DR11-C vs. DRV11

DISTRIBUTION
ORIGINATOR

11 / 28

/ 77

PRODUCT

Unrestricted

DRV11

Ron Young
I

PAGE 1 OF 4

The following tables and figures 1ist thle differences between the DR11-C
and the DRV11.
Some concern has been expresses on the mlnipulation of the REQUEST A
and REQUEST B lines. Let me remind you of the IIhandshakingll necessary
between the interface and the user's device. The user's manuals (DR11-C
General Device Interface Manual--chapter 6, and ADVI1-A, KWV11-A,
AAVII-A, DRVII User's Manual--chapter 5) state the need for the user to
hold the REQUEST lines until the NEW DATj~ READY or the DATA TRANSMITTED
signals are generated. The recol11l1ended method is illustrated in Figure 1
below.
ruSE~sD~;c;-

LOGIC
SET REO A L

REOUEST
A

CONN
No. ,
OR-3 HEW DATA READY H

ivvr----------------~
:

OR-3 REOUEST A H

~~~~----------------~--------~
SET REO 8 L

DR It - C
INTERFACE

(M11601

R~OUEST

CONN
No.2

r--

: c

DR-3 DATA TRANSMITTED H

----------+-1

!L __S
I

OR·3 "fQUfST 8 H

L _______ J

~D~Dlm~D
COMPOI~EMTS

GROUP
2E.

NUMBER 018
PAGE2 OF 4

).Inote
TABLE I
OUTPUT SIGNAL LOADING
SIGNAL

DRVll

DRII-C
--

New Data Ready

10 Loads **

30 Loads

Data Transmitted

30 Loads

10 Loads Per Connector

30 Loads Over Both Connectors

New Data Ready LO* (byte)

N/A

30 Loads

New Data Ready HI* (byte)

N/A

30 Loads

5 Loads

7 Loads

Init.

All Other Outputs

* Byte-oriented control signals available on DR11-C only.
ETCH REV E or later.

** One load is defined as (-1.6 rnA) one TTL load

~D~DDmD
COMPONENTS

GROUP
27

NUMBER 018
PAGE 3 OF l1

TABLE II
VARIABLE LENGTHS OF OUTPUT CONTROL SIGNALS
EXTERNAL CAPACITOR

NEW DATA READY

DATA TRANSMITTED

OR11-C
-

DR11-C

None

350 ns.

450 ns.

470 pF.

500 ns.

600 ns.

820 pF.

600 ns.

750 ns.

DR.Vll

DRV11

None

350 ns.

00047 uF.

750 ns.

750 ns .

• 01 uFo

15501 ns.

1550 ns .

• 02 uFo

23301 ns.

2330 ns .

• 03 uF.

31501 ns.

3150 ns.

~D~DDmD
COMJtONENTS
GROUP
28

)Jnote

NUMBER 018
PAGE 4 OF 4

TABLE III
BERG CONNECTOR PIN DIFFERENCES
SIGNAL

DRV11

DR11-C

In 02

J2 H,E

J2 H

Out 02

J1 RR,NN

J2 NN

New Data Ready HI (Byte)

N/A

J1 E

New Data Ready LO (Byte)

N/A

J1 H

~D~DDmD
COMPONENTS

GROUP
29

NUMBER

).Inote
TITLE

DATE

EIA RS-422 and RS-423

DISTRIBUTION
ORIGINATOR

019
11

/29

/77

PRODUCT

Unrestricted

DLV11-J

Ted SemQle
PAGEl

OF4

Electronic Industries Association (EIA) standards RS-422 and RS-423 have
been accepted as new international standards for transmission lines
between electronic equipment. These new standards offer a considerable
performance improvement over traditional EIA RS-232C and current loops.
Unlike RS-422 and RS-423 which were developed so that newly designed
equipment could have higher performance, RS-232C and current loops
grew out of existing applications and were accepted after the fact as
standards. RS-232C was originally developed by the Bell System as a
standard for interconnecting terminal equipment to communications
equipment (modems). Current loops were the method employed to interconnect teletypewriter devices.
Figure I graphically shows the performance differences between RS-232C,
RS-422 and RS-423. With RS-232C, the maximum reliable cable length is
50 feet and the maximum frequency is 20K baud. Comparing that with
RS-422, you will see that RS-422 has the capability of going all the way
up to 4000 feet and a maximum baud rate of 10 megabaud (although not
simultaneously). Table I is a more detailed comparison of the
specifications.
The new RS-422 and RS-423 specifications define the characteristics of
the transmitters and receivers used to drive the transmission line as
well as the characteristics of the transmission line itself. The
receivers and cables used for both standards are identical, but the
transmitters are different. RS-422 is a differential (balanced) line
system which is capable of transmitting data at high baud rates over
long distances with the high noise immunity associated with balanced
line systems. RS-423 is a single-ended line system which inherently
does not have the capability of a differential line.
EIA RS-423 is actually a stepping stone between EIA standards RS-232C and
RS-422. RS-423 transmitters and receivers are actually backward compatible
with RS-232C transmitters and receivers. This means that an RS-232C
transmitter can send data to an RS-423 receiver and vice versa. Since
the receivers used for RS-423 are identical to the receivers used for
RS-422, it is possible to design systems which will work with existing
RS-232C equipment and can then be upgradted (usually via a strapping
change) to RS-422. This provides for a smooth transition between current
equipment utilizing RS-232C and newly designed equipment utilizing

~D~DDmD
COMPOMENTS

GROUP
301

).Inote

NU~t1BER 019
PAGE 2 OF4

RS-422 without instantaneously obsoleting existing equipment. Remember
that when RS-232C and RS-423 transmitters and receivers are interconnected,
the system performance is that of RS-232C rather than the improved
performance of complete RS-423 systems.
The DlVI1-J 4-line serial line unit has been designed with the new
hardware for RS-422 and RS-423. Straps have been provided which permit
use of the RS-423 transmitters initially and then by restrapping, the board
can be upgraded to RS-422 transmitters. The DLVI1-J can, therefore, be
used with RS-232C peripheral devices. In the future, new peripheral
devices designed by Digital and other manufacturers will most likely
utilize the new RS-422 specifications. The maximum baud rate with
the DLVI1-J is 38.4K baud, not the limit of either RS-422 or RS-423.
The product line has additional technical details on RS-422 and RS-423
for those who need it.

~D~DD~D
COMPONENTS

GROUP
31

NUMBER 019
PAGE 30F 4

j../note
10K
ILLI
LLI

u...

:I:

le.!'
Z

LLI
.....J

c::c
u

100

~8
10

RS-2 2C
100

10K 20K

lOOK

DATA RATE - BAUDS

FIGURE 1 - DATA RATE vs. CABLE LENGTH

~D~DD!~D
COMPONENTS
GROIII»
32

10M

).Inote

NUMBER 019
PAGE 4 OF 4

Table 1. Comparison of the old and new interface standards

Parameter

RS232

RS422

RS423

Line length (recommended max-may be
exceeded with proper
design).

50 ft

1200 m (4000ft)
See Fig. 3

1200m (4000 ft)
See Fig. 5

Input Z

3 to 7 kQ
2500 pF

> 4 kQ

Max frequency (baud)

20kbaud

10 Mbaud

100 kbaud

Transition time>l<
(time in undefined area
between "1" and "0")
tr = 10 to 90%

4% of T
or
1 ms

tr ~ 0.1 T:
T ~ 200 ns
tr ~ 20 ns:
T < 200 ns

tr ~ .3 T:
T < 1 ms
tr ~ 300 p.s:
T > 1 ms

dV/dt (wave shaping)

30 V/p.s

See transition
time

See Fig. 4

Mark (Data "I")
Space (Data "0")

-3 V
+3 V

A < 8
A > 8

A = Negative
8 = Positive

Common mode voltage
(for balanced receiver)

-7 V < VCM < +7 V

< 100 n Balanced

< 50 12

IVo I~ 6Vu

4V~ IVol~6V

----

Output Z

Open-circuit
output voltage (V 0>

3 V < I Vo I

Vt = loaded V0

5<IV o l<15V
3 to 7kU load

Short circuit current

500 mA

150 mA

Power-off lea kage
(V0 applied to unpowered
device)

> 300 Q

2 V < I V I < 25 V
Vo applie

< 100 ,.,.A
o V <eVo < 6 V
Vo applied

< 100 p.A
I Vol < 6 V
Vo applied

> ±3 V

200 mV differential

f---

Min receiver input
for proper Vo

< 25 V

2Vor.5V o < IV t

r I~ bit perrod
.. across output. or output to ground
t whichever IS greater

EI H'TRONI( DI SHiN

100 n balanced load

IK. Scplcmhcr I. 1977

~D~DD~D
COMPONENTS

GROUP
33

IV t I ~ .9 IVI)!
450 U load

NUMBER

),Inote
TITLE

DATE
11 /30

9x6 Slot Backplane Documentation Error

ORIGINATOR

PRODUCT
DDV11-B

DDV11-B Users

DISTRIBUTION

020

Joe Austin
PAGE 1 OF1

There is an error in the two documents which define the backplane pin
assignments for the DDV11-B 9x6 slot backplane. Pins ET1 and FT1 in
all slots are actually bussed to ground as shown in the table below.
These pins are not blank as indicated in the Components Group, Logic
Products Option Bulletin (ED 06703 76, dated September, 1976) entitled
tlDDV11-B 9x6 Slot LSI-II Backplane tl,

(Correcte:d)
DDV11-B Backpllane Pin AssIgnments
SIDE

ROW

A&C

B&D

A
B
C
D
E
F
H
J
K
L
M
N
P
R

+5V
-12V
GND
+12V
BDOUTL
BRPLY L
BDINL
BSYNCL
BWTBTL
BIRQL
BIAKIL
BIAKO L
BBS7L
BDMG I L
BDMGOL
BINITL
BDALOL
BDAL 1 L

BSPARE 1
BSPARE 2
BAD16
BAD17
SSPARE 1
SSPARE 2
SSPARE 3
GND
MSPAREA
MSPAREA
GND
BDMRL
BHALT L
BREFL
PSPARE 3
GND
PSPARE 1

+5V
-12V
GND
+12V
BDAL2L
BDAL 3 L
BDAL 4 L
BDAL 5 L
BDAL6L
BDAL 7L
BDAL8L
BDAL9L
BDAL 10 L
BDAL 11 L
BDAL 12 L
BDAL 13 L
BDAL 14 L
BDAL 1-5 L

BDCOKH
BPOKH
SSPARE4
SSPARE5
SSPARE6
SSPARE 7
SSPARE 8
GND
MSPARE B
MSPARE B
GND
BSACK L
BSPARE6
BEVNT L
PSPARE 4
GND
PSPARE 2
+5B

+5V
-12V
GND
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLAN
BLAN
BLANK

BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK

+5V
-12V
GND
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK

BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK

BLANK

LANK~
LANK
BLA
LANK
gnd
BLANK
BLANK
BLANK

S
T
U
V

+58

~D~DD~D
COMPC)NENTS
Ci~:xIP

3:4

NUMBER

).Inote
TITLE

Comparison of Data Transmission Techniques

DISTRIBUTION
ORIGINATOR

Unrestricted

021

DATE

12 / OS

PRODUCT

-----

Ted Semple
PAGEl

OFS

Frequently, the application artses where a data transmission path has to
be established between two devices. Usually the distance between the
devices is known, and also the rate of data transmission is known. The
problem comes with deciding which is the best communication technique to
use to interconnect the devices. Figure I should help you with this
decision.
Figure I is a graph of data rate vs. distance for the various standard
transmission techniques. Parallel data transmission techniques (PLU's
and DMA) give the highest data rate; however, they are only good for
relatively short distances. The serial techniques (RS-232C, RS-422 and
current loops) are good for longer distances but at limited data rates.
While analyzing Figure I, remember that the axes are logrithmic and that
the data rate is in words per second rather than baud rate. The limits
established for both distance and data rate are a function of both the
inherent limitations of the transmission technique and of the Digital
Equipment Corporation device used to do the interconnection. As an
example, look at the 422 section of the graph. Maximum distance is
4000 feet as established by the EIA standard RS-422, but the maximum
data rate of 1920 words per second is based on the maximum baud rate of
the DLV1I-J which is 38.4K baud.
Table I is a summary of the LSI-II devices which can be used with each
communication technique. The Unibus equivalent for each device is also
shown. Currently, there is no Unibus device for EIA RS-422.
The material for this Micro Note was extracted from the "CPU Interconnection Techniques" session given at the DCG International Sales
Meeting. The entire presentation is available in 3S mm. slides,
together with backup material, from the LSI-II Presentation Library.
Contact the product line if you would like further information.

~D~DD~D
COMPONENTS

GROUP
35

NUMBER 021
PAGE 2 OF ~

).Inote
FI~iURE

lOOK

DATA RATE vs. DISTANCE
With Digital Devices

10K

EIA
RS-232C

w/Modem

1.5K EIA
RS-422

u.
I
I

L&J
U
Z

EIA
RS-423

V')

.......
CI

100

Current
Loop

1920

EIA RS-232C

DMA (3 - STATE)

ALL
TECHNIQUES

PLU

100

DMA
(TTL)

480

----

10K
DATA RATE
Words/Sec.

~DI~DDmD
COMJaoMENTS
GROUP
36

46K
lOOK

)./note

NUMBER 021
PAGE 3 OF f

NOTES AND ASSUMPTIONS FOR FIGURE 1

Data Rate Definition
a.

One word equals 16 bits

For serial techniques, one word equals two characters formatted
with one start bit, eight data bits and one stop bit. Asynchronous serial transmission is assumed.

Serial Line Maximum Data Rate
a.

Modems were limited to 120 words/sec. (2400 baud) because
modems with higher rates cost more than LSI~11 systems
usually warrant. Higher data rate modems are generally
synchronous rather than asynchronous.

480 words/sec. is equal to 9600 baud, the limit of the
DLVll SLUe

1920 words/sec. is equal to 38.4K baud, the limit of the
DLVII-J SLUe

PLU (Parallel Line Unit) Limits
a.

The TTL inputs/outputs of the DRVll limit the distance to
15 feet.

46K words/sec. assumes non-interrupt driven program servicing
with bit testing (TSTB, BMI, MOV and SOB). 97K words/sec.
is maximum rate with program servicing without bit testing
(MOV and BR). With interrupt driven servicing, the maximum
limit is 20K words/sec. assuming 50 us. for interrupt
latency and software servicing of interrupt. (380 ns. CPU
microcycle time)

DMA (Direct Memory Access) Limits
a.

The DRVII-B can be used up to 50 feet because it has tri-state
drivers and receivers. The distance is limited to 15 feet
with TTL devices like the DRII-B.

~D~DD~D
COMPONENTS

GROUP
37

j../note
b.

NUMBER 021
PAGE 4 OF5

OMA transfers with the ORVII-B and the ORII-8 are limited
to SOOK words/sec. in burst mode operation. 250K words/sec.
is the limit for single cycle mode operation with either
devi ce. These 1imi ts are dev1i ce dependent; they are not
LSI-II bus limits (which is 8:~3K words/sec.). Remember
that burst mode can disrupt mE~mory refreshing if bus
refreshing (OMA or microcode) is used. Self-refreshing
memories, MSVII-CO or MSVII-0" eliminate this problem.

~DmD[I~D
COMPC»IENTS
. GROiJP
38

)./note

NUMBEH 021
PAqE 5 OF 5

TABLE I
DEVICES
LSI-II

PDP-II

Loop

DLVII

DLII-C

EIA (RS-232C)

DLVII

DLII-0

EIA W/Modem

DLVII-E

DLII-E

RS-422

DLVII-J

PLU

DRVII

DRII-C

DMA

DRVII-B

ORII-B

mD~DDmD
COMPONENTS

GROUP
39

NUMBER

)lnote
TITLE

023
DATE
12 /16
PRODUCT
MSVII-0

Using the MSVII-0 30K OEtion

OISTRIBUTION
ORIGINATOR

Unrestricted
Rich Billig

/77

PAGE 1 OFI

The MSVI1-D memory, when configured with the full complement of 16K
RAM chips, provides 32K words of storagE~. In the LSI-II memory map,
however, the top 4K words (addresses 160000 to 177777) are normally
reserved for I/O device registers (the so-called "I/O Page").
The 32K MSVII-0, as delivered, operates as a 28K word memory for the
LSI-II. In this configuration, it is totally compatible with all
DEC-supplied software. The 4K word reg~ion which is located at
address 160000 is present but inaccessible to the program.
To allow more of the memory to be used (for large applications), a
jumper-selectable option on the MSVII-0 makes 30K words (rather than
28K) addressable by the program. This "is done by "removing" the low
2K word area of the I/O page (addresses 160000 to 167777). When the
30K option is enabled, the memory map is:
000000 to 167777

RAM '~emory

170000 to 177777

I/O Page

Because current system software expects a 4K word I/O page, RT-11 and
RSX-11S cannot make use of the extra 2K words of RAM. (A userwritten program operating under either system may, however, access
locations 160000 to 167777 directly if desired.)
Engineering is presently evaluating the feasibility of supporting
the full 30K RAM in the next release of RT-ll (V3B). Similar modifications to RSX-I1S would be more extensive and are not currently
planned.
When the 30K option is used, all I/O devices must be Configured to
place their I/O page addresses in the range 170000 to 177777. (This
would not be the default assignment for such devices as the DUV11 and
DZVll.) Also, it is not possible to use the REV11 bootstrap with
this option, as a portion of the bootstrap PROM code resides at
addresses 165000 to 165777. The new quad bootstrap module (BDV11) may
be used in the 30K environment.

~D~DD~D
COMPOIt-tENTS

GROUP
4()

NUMBER

)lnote
TITLE

DATE

Async., Serial Line Unit Comparisons

DISTRIBUTION
ORIGINATOR

024A
SUPERSEDES pNOTE #024
10 /

PRODUCT

LSI-II Users

Async. SLU's

Joe Austin
PAGE 1 OF

Attached are charts comparing the different members of the families of
asynchronous serial line products. All modules of the DLV11 series are
dual height modules. The DLV11-E, -F, and -J modules detect overrun
conditions which are reported in the receiver CSR. These modules will
not generate phantom interrupts on overrun.
DLV11-J
Each of the 4 serial ports on this module are separate and independent
from the others. This is not a multiplexed module. Each port has its
own CSR's, data buffers, interrupt vectors, baud rates, UARTs, etc. The
net effect of this module is to achieve a 4:1 compression ratio over the
DLV11-F and the DLV11. The main functional difference between the ports
of the DLV11-J and the DLV11 is that the DLV11-J provides the higher
performance EIA RS-422 and RS-423 interfaces (RS-423 on the DLV11-J also
meets the EIA RS-232C specification) and requires the DLV11-KA option
(one per port) to add the 20 mA current loop interface, to add 110 baud,
and to add reader run functions.
DLV11-E
This module is functionally equivalent to the DL11-E except that it has
programmable transmit baud rates. This module provides one serial port
that has full modem control.
DLV11-F
This module is functionally equivalent to the DLV11 and will eventually
replace it. In addition, it can be configured to provide programmable
transmit baud rates.
DLV11-KA
Thfs option allows an EIA port to be connected to a terminal with a 20 mA
interface, such as an ASR33. It consists of a small PC card containing
the interface conversion logic within a box that is externally mounted.
Mating cables are included. This module is not restricted to 110 baud.

~D~DD~D
COMPONENTS
GROUP
41

NUMBER 024A

).Inote

PAGE 2 OF 5

TABLE
- -1
COMPARISON OF HARDWARE FEATURES

ur IBI S

LS -1 l B)S

c:C
I

....... .......

.......
N

-I

Number of Ports Per Module
EIA RS-232C
Full Modem Control
Limited Modem Interface
EIA RS-422, RS-423
Data Leads Only
20 mA Current Loop
RCVR Active or Passive
XMIT Active or Passive
XMIT Active Only
CCITT
HALT on Framing Error (4)
BOOT on Framing Error (4)
Baud Rates (see Table 3)
Programmable
Split Speed Clocks Included
Reader Run Control
Error Flags
Transmit Break Generation Bit
Receiver Active Bit
Maintenance Bit
Internal Real Time Clock
UART Cleared by INIT
UART Cleared by DCOK
No Trap on Write to Input
Buffer
Easy Configuration Using
Wire-Wrap Jumpers
Stop Bits
1
1.5

.......
Q

.......

-I

....... ....... ....... ....... .......
-I

-I
Q

LLJ

Q
I

-I
Q

.;
.;

.......
.......
:::-

.; .;
.;
.; .;
.; .;
.; .;
.; .;

LL.

r-:>

....... .......
....... .......
:::- :::-

.......
.......

-I

-I
Q

:::-I

.; .;

c:C

.......
.......
:::-

-I

.; .;

.;
.;
.;
.; 2) .;
.; 2) .;

.; .; .;

.; .; .;
.; .; .;
.; .; .;

.; .; .; .; .; .;

4 1 4

.; .;
.;

.;
.;
.; .;
.; .;
.;
.; .;

LLJ

.; .; .; .; .; .;

.; 6)
.; .; 6)

.; .;
.; .;
.;
.;
.; .;
.; .; .;
.; .;
~3) .; .;
.;

.;
2) .;
.;
.;
.;
.;
3)

.; .; .;

.; .; .;
.; .; .;
.; .; .;
.; .; .; .; .; .;

.;
.;

~DmIODmD
COMPCNNTS
CiRC)Up
4:2

.; .; .; .;
.; 5) 5) .;

.;
.;
.;

NUMBER 024A

).Inote

PAGE 3 OF 5

TABLE 2
COMPARISON OF SOFTWARE FEATURES
UNIBUS
ex:I coI

REG ISTER

BIT

NAME

RCS R:

15
14
13
12
11
10
9,8,4

data set status/interrupt
ring
CTS
CD
receiver active
2d receive
unused
receive done
receive into enbl.
data set into enbl.
2d XMT
RTS
DTR
rdr. enable

7
6

5
3
2
1
0

RBU F:

15
14
13
12
8-11
0-7

XCS R:

8-15
7
6

1,3,4,5
2
0

XBU F:

8-15
0-7

LSI-II BUS

......t
......t

...J
0

I..LJ
I

I' I' I' I'
I' I' I' I'
I' I' I' I'
I' I' I' I'

:3
I

I..LJ
......t
......t

>
...J

LL.
I

P"':)

......t
......t

...J
0

I'
I'
I'
I'
I' I'
I'
I'
I' I'
I' I'
I'
I'
I'
I'
I'

~1) I'
I'
I'
I'
I'
I'
I' I'
I' I'
I' I'
I'
I'
I'
I'
I'

I'
I' I'
I' I'
I' I'

I' ~2 )

error
OE
FE
PE
unused
receive data

I'
I'
I'
I'
I' I' I'
I' I' I'

I'
I'
I'
I'
I'
I'

I'
I'
I'
I'
I' I'
I' I'

I'
I'
I'
I'
I'
I'

unused
XMT ready
XMT into enbl.
unused
maintenance
XMT break

I'
I'
I'
I'
I'

I'
I'
I'
I'
I'
I'

I'
I'
I'
I'

I'
I'
I'
I'
3) I'
I' I'

I' I'
I' I'
I' I'
I' I'
I' ~3)
I' ~I'

unused
XMT BUF

I' I' I' I' I' I'
I' I' I' I' I' I'

~D~DDmD
COMPONENTS
GROUP
43

I'
I'
I'
I'
I'

I'
I'
I'
I'
I'
I'

I' I' I' I'
I' I' I' I'

NUMBER 024A
PAGE 4 OF 5

).Inote·
TABLE 3
BAUD RATES
UNIBUS
c::cI

c::cI

BAUD
RATE
EXT
50
75
110
134.5
150
200
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

N
0

.....t
.....t
-I
0

I
I
I

I
I
I
I
I

.....t
.....t

>
-I

l
I
l
../
../
../
I
I
I
I

I
I

~D~DD!~D
COMPOMIENTS
CiROUP
44

.....t
.....t

I
I
I
I
I

I
I
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I

...
c::cI

.....t
.....t

>
-I

"':)

.....t
.....t

I
I
I
I

>
-I

I
I
I
I
I
I
I
I
I
I
I

I
I
I
I

.....t
.....t

.....t
.....t
-I

.....t
.....t
-I
0

I
I
I
I
I
I
I
I
I
I

I
I
I

.....t
.....t
-I
0

I
I
I
I
I
I
I
I
I
I

I
I
I

LLJ

I
I
I
I
I
I
I
I
I
I

vi
vi
I
I
I

LL...

LLJ

co
I

.....t
.....t
-I
0

.....t

LSI-I" BUS

>
-I

.....t

N
0

(2 )

I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

).Inote

NUMBER 024A
PAGE 5 OF 5

Read only bit wf11 not generate an interrupt.

The external 20 rnA option (DLVll-KA) is required to implement this
function.

The loop-back cable is required to implement this function.

Optional feature.

110 baud only.

Applies only to the part assigned to the console device.

~D~DDmD
COMPONENTS
GROUP
45

NUMBER

).Inote

025

TITLE

Configuring Memorl Slstems With MSVII-D
RAM and PROM
DISTRIBUTION Unrestricted

ORIGINATOR

DATE
12 121

PRODUCT
MSVII-D

Ted Sem~le
PAGE 1 OF2

Configuring LSI-II memory systems which consist of only Random Access
Memory was made easy by the introduction of the MSVII-D module.
Availability of 4K, BK, 16K, and 32K versions of the MSVII-D RAM
board means that any memory configuration usable with an LSI-II can
be configured with a single, double height printed circuit board.
Memory systems utilizing both RAM and ROM can be configured with
the MSVI1-D using the guidelines listed below:
1.

All memory addresses on an MSVII-D module must be contiguous.
It is not possible to split the address range of RAM on a single
MSVII-D board. If the address range of RAM must be split, then
more than one MSVI1-D board will be required.

ROM should generally be configured in the lower address range
before RAM. With the 32K version of the MSVII-D, the ROM must
come before RAM.
--

The 2BK-30K feature of the 32K version of the MSVI1-D (see Micro
Note #23) cannot be used in systems with ROM.

The starting address of an MSVI1-D board is selected by switches on the
The starting address of the module can be any multiple of 4K
words. The MSVI1-D module will then respond to either 4K, BK, 16K, or
32K (depending on the version used) continuous locations above the
selected starting address. In LSI-II systems, the MSVI1-D will not
respond to any address above 2BK except as explained in Micro Note #23
and note #3 above. Any unused portion of an MSVII-D board that extends
above the normal 32K word addressing limit of LSI-II systems will not
be usable. To establish an upper address limit, no strap is required
when configuring boards that will exceed the normal 28K limit.
module~.

If a customer's application requires an addressing scheme which does not
meet the guidelines above, he may be forced to use more than one RAM
board because the MSVI1-D address range must be contiguous and because
it cannot be truncated. For example, if a customer's application

~D~DD~D
COMPC)NENTS
Ci~OUP

NUMBER 025
PAGE 2 OF ~

requires RAM from 0 to 24K and then PROM from 24K to 28K, he would have
to configure the system using one 16K module, one 8K module, and one 4K
PROM module.
Figure 1 shows the standard LSI-11 memory map and a sample system with
24K of RAM and 4K of ROM configured with a single MSV11-D (32K version)
and a 4K PROM board.

24K RAM, 4K ROM
CONFIGURATION

LSI-II
MEMORY MAP
0
4K
BK
12K
16K
20K
24K
2BK
32K

vectors

~-------------------

GENERAL
PURPOSE
MEMORY
&

STACK
I/O

ROM
4K
)
8K
12K
(
RAM
16K
20K
24K
J
..)
28K
32K l ___________________
I/O
36K

FIGURE 1

~D~DDmD
COMPONENTS

GROUP
47

If
~

USED
PORTION
OF
MSVII-D
UNUSED
PORTION
OF MSVII-D

NUMBER

)lnote
TITLE

026
DATE

Micro Back~lane Mechanical Mounting Guidelines

DISTRIBUTION
ORIGINATOR

LSI-II/2 Back~lane Users
Chi Lau

/ 4 As

PRODUCT

H9281
PAGEl

OF8

MICRO BACKPLANES
FEATURES
The micro backplanes are a series of backplanes with available card frame
assemblies which have the following primary characteristics:
•

LSI-11 bus signal connections

•

Accommodates double height DEC standard modules

•

Variations for four, eight, or twtelve modules

•

Seven terminals for DC input powe r (H780 compatible) including
battery backup

•

9-pin header connects power supply signals to LSI-II bus (H780
compatible)

DIMENSIONS AND MOUNTING
Mechanical dimensions and mounting can be divided into two categories.
One is the backplane series; the other is the card frame assembly series.

~DmDD~D
COMPONENTS
CiROUP .
4E~

NU~~BER

026
PAGE 2 OF C

Backplane series (H9281-AA, H9281-AB, H9281-AC) mechanical information
for mounting is shown in Figure 1 and Table 1.

4P/...CS

POwc.e
INPl..lr
7£~M.(7)

:1
I
I

NOTES : I. t:lLL DIMENSIONS liRE
IN I)JCH£S

2. 70L€~,qAJCe =:t .0/0
..3.I=INISJI€D "'WJJHOLE
SIZE = ./40 l)1I1.

---FIGURE 1
TABLE 1
DIMENSION
Option

# HOLES

H9281-AA
_.

.220

5.31

5.75

N/A

.lS0

1.74

.lS0

.440

.220

1.94

H92S1-AB

.220

5.31

5.75

1.90

.2S0

3.80

.280

.S20

.820

1.94

H92S1-AC

.220

5.31

5.75

2.90

.280

5.80

.2S0

.S20

1.94

~DmDDmD
COMPONENTS

GROUP
49

NUMBER

026

PAGE 3 OF 8

1.1

Stand-Off Mounting
These backplanes may be mounted onto any plane by using the mounting
holes ("W" holes) in the printed curcuit board. Figure 2a examplifies
this mounting scheme.

SPACER

HOL£' SIZE: #~

LENGTH :t.OO'~

POJ~ER
SU;:~LY

(e.g. LAMBDA

FRONT VIEW

LIVD-X-MPU)

SJ.I£E7 METJ1L
'i'd " 7YP.

BOTTOM VIEW

(9)

AIR ,cLOW

FIG, £'C2

ILLUSTR'A7,VE BI1C~PLlllv£ /vJOUNTING
TO HOKIZO/l/TAL PLANE.

~DmDDmD
COMPOIMENTS
GROUP
5()

NUMBER 026
PAGE 4 OF 8

1.2

Flush Mounting
Figure 2b examplifies this mounting scheme.
for dimensional information.

See Figure 1 and Table 1

#6 pan head screw 5/8" 19

- - - k n ¥ l o n washer for #6 screw

11"0

1
1
----

lock nut for #6 screw

- Surface with Gut-out area shaded.
See Table 1 for dimensions.

Figure 2b - Flush Mounting

~DmDDmD
COMPONENTS
GROUP
51

)lncne
a,
----;;;

.....- - - - 5 . t S (

J-

4.5'

- - - - - - _ •. _ ... , - -

-<'~.'

"-- .250 DIA
TIIRLI
16 "Y 1J HOLES
....

-.-~

.. - .... ,

..... ...

;II

11-1

.12

PLCS

1.75'

J
':".50

_1
~
I

yr-

.....

~.--

~. - _----_
.

...

1-..
~

5.25

. ............

-- - --

r;- --=:1hI'W~

?:r f-'--X

yt··

~- -~
'---

I-I

- -I
.5.4.3
FRONr

5>.21
p

[ 1--

.715
II
"

.5.31

lhIITI

-J
II

-I I

........ D

- 8 f---.
R-SIDE

1 0 0 0 0 0 0 0 1 --,-.
i

Option
Number
-.----H9281-BA

~-.--,. ..,.-

-----

.•.

H9281-BB
~-------~'2 -----------~

Dimension. In Inch
A

3.10
~.----

.30
.. _-----_.-.-

H92A1-BC

1...--... __. _ _

.1L-

2.70

0.0

----.-~

5.10

.65

4.70
-

.65

7.10

.65

6.70

.65

:-..---.

BOTTOM VIEW

Figure 3 - Card-Frame-Assembly Mechanical Drawings (Not To Scale)

~D~!DDmD
COMP4ONENTS
GROUP

026

PAGE 5 OF 8

10.80

NUMBER

NUMBER 026
PAGE

6 OF 8

Card frame assembly series (H9281-BA, H9281-BB, H9281-BC) mechanical
information is shown in Figure 3. These assemblies may be mounted
onto any surface or support by utilizing either the threaded
extensions or the "V" holes of the card frame.
2.1

Rear-Mounting (Figure 4a)
This mounting scheme makes use of the threaded extensions of
card frame.

DC input terminals

Lock nut
ID:

#10

Spacer hole
size: #10
length: 1"

Direction of airflow
must be across cards

Sheet metal 1/8" typo

Figure 4a - Illustrative Card Frame Rear-Mounting

~DmDDmD
COMPONENTS
GROUP
53

NUMBER 026

).Inote

PAGE 7

Side-Mounting

2.2

This mounting scheme utilizes the lIyll holes (see Figure 3) to
mount the card frame onto a surface or side wall of an enclosure.
Direction of air flow must be parallel to and through the spaces
among modules.
SPACER

1.0. = .25 11

0.0. = 3/8
LG = 3/4 11
8 PLCS

r-.

"......

C
SCREW/
LOCK NUT
\
COMBINATION
DIA = .216
LENGTH = 1.25

POWER
SUPPLY
(e.g. LAMBDA
LND-X-MPU)

c
SHEET METAL
OR SIDE WALL
OF ENCLOSURE
(see Figure 5
for more
details)

\
:$

InII

1--- ---I ~ DC Input

Terminal

Circuit Board
Figure 4b - Illustrative Card Frame Side-Mounting

~ID~DDmD
COIfIPOMENTS
C3lOUP
54

OF 8

NUMBER 026
PAGE: 8 OF 8

The hole pattern for side-mounting is shown in Figure 5. Sidemounting may be accomplished in two ways. One requires spaces (see
Figure 4b) to offset circuit board overlap. The other is flush
mounting which requires cut-out in the mounting surface (see shaded
area) .

Mounting Surface

+---+
+- -+
+- -+
I

_++"I"\+--_ _ _ _ _ _ _

.J../. 7'1

2.3.))

Figure 5 - Hole Pattern For Side-Mounting
(See Figure 3 For Dimensional Information)

~DmDDmD
COMPONENTS
GROUP
55

NUMBER

)lnote
TITLE

027A
DATE

PROM Chi~s Available Under Part #MRVll-AC

DISTRIBUTION

Onl~ As

ORIGINATOR

Dave Schanin

Needed

/25
/78
PRODUCT
MRVll-AC
1

PAGEl

°Fi

Until recently, there was some concern because a customer ordering
MRV11-AC PROMs could get PROMs from one of three different vendors -MMI, Intersil, or Signetics. The problem was caused by the fact that
these PROMs had different personality traits; i.e., some blasted a
location to a logic "oneil and some bla:sted a location to a logic "zero".
This caused customer problems.
The problem has now been resolved so that anyone ordering MRV1l-AC
PROMs will only receive Signetics 82S131 parts.

~D~lDD~D
~ONENTS

GROUP
56

NUMBER

)lnote
TITLE

028
DATE

Extended Memory for the LSI-I!

DISTRIBUTION
ORIGINATOR

Unrestricted
Ted Sem~le

/2
1'8
PRODUCT
MSVII-C &MSVII-D
2

PAGEl

OFl2

SCOPE
This Micro Note describes how an LSI-11 user can expand the memory in an
LSI-II system from the normal maximum of 28K words to lOOK words. To do
this, a customer must manufacture his own control module. The custom
module will allow a user to put multiple MSVII-C and/or MSVII-D memories
on one LSI-II bus.
CAUTION:

This Micro Note outlines an approach to extend
the LSI-II memory beyond 28K. The approach
taken is not compatible with any of the memory
management units available for larger PDP-II's.
Therefore, it is unlikely that programs written
to take advantage of this extended memory
approach will migrate without major revision
to the next generation processors for the
LSI-II bus.

THEORY OF OPERATION
The extended memory approach explained in this Micro Note is the
approach that has been recommended by the LSI-II Tech Support Group to
customers who desire to expand the memory on their LSI-II system beyond
28K. Thi s approach a'llows a customer to expand hi s memory from 28K to
a maximum of lOOK words by utilizing BDAL 16 and BDAL 17 signal lines
on the LSI-II bus. Both the MSVII-C and the MSVII-D memories have the
capability of decoding address lines 16 and 17. The LSI-II processor
does not have the capability of controlling these address lines. The
sche~e proposed here outlines a way address lines 16 and 17 can be
controlled by the program.
The extended memory approach proposed is a paging scheme. A portion of
the standard 16-bit LSI-II address range is mapped to four different pages
which fall within a range addressable with 18 address lines. The address
translation used is shown graphically by Figure 1 (on page 2). The
left-hand side of the figure is the virtual address map. Virtual

~D~DD~D
COMPONENTS

GROUP
57

..I eRa 'fOTE

o
4K
8K
12K
16K
20K
24K
28K
32K

NUMBER:
028
PAGE 2 OF 12

VIRTUAL ADDRESS

PHYSICAL ADDRESS

COMMON MEMORY

.------------------------------1-------.. - ----------------------------------------------------------l
-----------------------------PAGE 0
------------------------------.
----------------------------

~----------------------------- \•
----------------------------------------------------------I/O

\----_.-

.~ \

ItO

_l!/ll[llrj}l[!I!IIll~

\\
\\ \.
.\
\.
\ \.

PAGE 1

----------------------------

\\
\ \ ----------------------------\ . ----------------------------PAGE 2

\• \. ----------------------------\.'

•

\•

II11 Unused/
1111- Unusable

PAGE 3
----------------------------\
. -----------------------------

FIGURE #1 - EXTENDED MEMORY ADDRESSING

BANK
0
4K
8K
12K
16K
20K
24K
28K
32K
36K
40K
44K
48K
52K
56K
60K
64K
68K
72K
76K
80K
84K
88K
92K
96K
lOOK
104K
108K
112K
116K
120K
124K
128K

0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37

j../note

NUMBER 028
PAGE 3 OF12

addresses are 16-bits long and are the actual addresses referred to by
LSI-lIar any PDP-II programs. The right-hand side of the figure shows
the physical address map. Virtual addresses 4K to 28K map to physical
addresses 4K to 28K for Page 0, 36K to 60K for Page 1, 68K to 92K for
Page 2, and lOOK to 120K for Page 3.
Two 4K portions of the virtual address range do not map to each of the
pages in the physical address page. Both of these 4K ranges are reserved
for functions which must be available for programs operating out of any
one of the four pages. Virtual addresses 0 to 4K map directly to physical
addresses 0 to 4K. This first 4K bank is referred to as Common Memory.
The I/O address range 28K to 32K maps directly to physical address range
28K to 32K. Virtual addresses 28K to 32K are not mapped up to 124K to
128K as with memory management units of larger PDP-II's.
Common memory contains all of those system functions which must be
accessible independent of which page the program is being executed from.
These functions include interrupt vectors, the stack, and all interrupt
subroutines. For longer interrupt subroutines, it is possible to have
the beginning and the end of the subroutine in common memory with the
bulk of the routine actually on one of the pages. Common memory must
also be used for routines that handle the switching of the pages. The
generation of the physical address, described below, requires that
there be a common memory space so that the LSI-II interrupt mechanism
will work properly, regardless of which page a program is being executed
from. Any memory reference in the a to 4K region will always be in
common memory, independent of which page is being used at the time.
Additional considerations on the use of common memory are given below.
Figure 2 (on page 4) shows how the physical address is generated.

Bits

a to 15 of the physical address are equivalent to the virtual address.

Bits 16 and 17 of the physical address come from the relocation register.
The relocation register is a hardware register on a custom module made
by the user. The recommended address for the relocation register is
164000.

Figure 3 (on page 4) is the recommended format for the relocation
reglster. Read/write bits 00 and 01 control BDAL 16 and BDAL 17
respectively. Read/write bit 07 is used to enable the bus data address
line drivers. Additional circuitry is required on the custom module for
the timing of BDAL 16 and BDAL 17 signals. This circuitry is described
under the Implementation section below.
Shaded portions of the physical address map (Figure 1) between-each one
of the pages and the end of memory are defined as unusable. An analysis
will reveal that these gaps actually correspond to the virtual address

~D~DD~D
COMPONENTS
CiROUP
59

NUMBER 028

).Inote

PAGE 4

OF 1'.'

FIGURE #2 - PHYSICAL. ADDRESS FORMAT

VIRTUAL ADDRESS

RELOCATION REG.

PHYSICAL ADDRESS

FIGURE #3 - RELOCATION REGISTER

w
... '-_.J

-- -.,.

l.LJ

V')

=>
z:
=>

z=>
=>

~D~IJDmD
COMPC~ENTS

CiRC)lJP

XIw
~

........

I.D

-'
<C
o
co

-'
<C
<C
co

......

164000

NUMBER 028
PAGE 5 OF12

common memory areas and I/O address areas. To make this extended memory
addressing scheme work, no memory board can respond to any address within
those shaded address ranges of the physical address map. If a board does
respond in those ranges, it will mean there are two boards in the memory
responding to common memory addresses or I/O addresses. The BBS7 signal
on the LSI-11 backplane is generated by the bus master whenever an access
to an I/O device is made. This signal inhibits both the MSVI1-C and the
MSV11-0 from responding to any address in the I/O range and from responding
to any physical addresses which are memory banks 7, 17, 27, and 37 of
the physical address page. Unfortunately, there is no signal similar
to BBS7 to prevent the memory boards from responding to addresses in
physical address banks 10, 20 and 30 which are translations of the common
memory area. Therefore, care must be taken to insure that no memory
board responds to addresses in those ranges (a bank 0 detection circuit
is described below).
IMPLEMENTATION
This section describes the physical implementation of how a user can
get lOOK words of memory on an LSI-11. Configuration of standard LSI-11
memory modules for the extended memory is discussed, and a block diagram
for the user's custom module is reviewed.
NOTE:

The following approach has been thoroughly
reviewed by LSI-11 technical personnel. However,
the approach has not actually been breadboarded.

Table 1 (on page 6) shows how standard LSI-11 memory modules are
configured for the expanded memory. Either MSV11-D or MSV11-C modules
may be used. Switches on either modules are used to select the starting
address shown for that particular module. This table shows how to
configure the entire lOOK words of extra memory. If an application
requires less than the full amount of memory, only those memory modules
necessary are used.
Figure 4 (on page 8) is the block diagram of the extended memory control
module. There are five distinct portions of this block diagram,. each
with their own functions. These sections are:
1.
2.
3.
4.
5.

Bus interface logic
Relocation register
BDAL drivers
Bank 0 detector
Synch low stretcher

~D~DDmD
COMPONENTS

GROUP
61

NUMBER028

).Inote

PAGE 6

TABLE #1 - MEMORY MODULE ADDRESS RANGES
PHYSICAL
ADDRESS
- -BANK
---

0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
20
21
22
23
24

2S--

26
2"-30
31
32
33
34
35
36
37

STARTING
ADDRESS

A,PPROACH
#1

000000

MSV~-CD
..,

100000

MSV~-CD

220000

~Isvli- CD

320000

~_CD

420000

f
MSVlf CD

520000

620000

~JSVI

.,- CD

~JSV11- CD

APPROACH
#2

MSV11-DD

1
T
1

MSV11-DD

i
1

MSV11-DD

MSV11-DD
720000

MSVl! CD
~

~DmDD~D
COMPONEim
GROUP'
62

OF 1'"'

),Inote

NUMBER 028

PAGE 7

The following paragraphs discuss the function and operation of each one of
these sections.
The bus interface logic performs all of the functions necessary to connect
the circuitry of the extended memory control module to the LSI-II bus.
Bus interfacing is accomplished using Digital's own DC004 and DC005 ch:fps.
These chips are available from Chipkit DCKll-AA. Four DC005 transceiver
chips are used to detect when the extended memory control module is being
addressed as well as to buffer the data lines. The OC004 chip handles
the LSI-II bus protocol (the last chip in the kit, the OC003 interrupt
protocol chip, is not used). The 8641 bus receiver chip, also available
from Digital, buffers the BYSNC, BSACK, and BINIT signals. Detailed
circuit information on how to interface to the bus is available in the
DCK11-AA Chipkit User's Guide.
The relocation register is a 3-bit latch (3/4 of a quad latch) with
Tri-State buffers to feed the output of the latches back to the data
bus. The Tri-State buffers are required to make each bit of the register
readable under program control. Control signals from the OC004 bus
protocol chip clock data into the latches and enable the Tri-State
buffers.
Two 8881 NAND gates, available from Digital, are used for BDAL drivers.
One gate drives address data line 16 and the other gate drives address
data line 17. Address bits 16 and 17 actually control which page is
being used at the time. Data inputs for the drivers come from the
relocation register bits 00 and 01. The 8881 gates are enabled by the
output of a Schottky negated input AND (NOR) gate. When all inputs to
this gate are low, the BDAL drivers are enabled. There are four input
signals to this gate. The ENABLE signal from the relocation register
permits the programmer to control the bus drivers. The SYNC* signal
comes from the Sync Low Stretcher. This signal enables the extended
address bits only during the address portion of a bus transaction. The
SACK signal disables the drivers whenever a DMA operation is taking
place on the bus. The final input to this gate is BBSO, which comes from
the bank 0 detector, disables the 16th and 17th address bits whenever an
access is being made to RAM bank O. A Schottky gate is used to minimize
the propagation delay through this circuitry.
The bank 0 detector is a single DC005 transceiver chip. Only the bus
receiver and address comparison features of this chip are being utilized.
When the address select inputs to the De005 are allowed to float (vs.
being connected either to ground or to Vcc), the chip will detect when
BDAL 13, 14, and 15 signal lines are high, bank 0 is being addressed,
;ld the MATCH output of the chip will go high. The MATCH output of the
DC005 is the BBSO signal on the block diagram. When BBSO is high, the

~D~DDmD
COMPONENTS

GROUP
63

OF12

MICRO NOTE
BANK 0 DETECTOR

BDAL 15 L
BDAL14 L
BDAL13 L
NC
NC
NC

BBSO

..
DC005

-L

o-~
~

74S260

BDAL17 L

8881

BDAL DRIVERS

V1-

SACK

::(

5J--

DAL17

BADL16 L

LLJ
....J

ott
U

a:l

8881

BDALOO-15

ex:
:z

DAl16

:z
>V)

LLJ

RELOCATI ON
REGIST ER

STRAP
FOR
164000

NUMBER: 028
PAGE 8 OF 12

DC005
(4)

DATA BUS

......

CONTROL SIGNALS

BRPLY L
BWTBT L
BDIN L
BDOUT L

i('

DC004

BUS INTERFACE
LOGIC

SYNC LOW
STRETCHER

<X.~ SYNC

BSYNC L
BSACK L
BINIT L

......

.....

8641

~J
•

....

SACK
INIT

FIGURE #4 - EXTENDED MEMORY CONTROL MODULE BLOCK DIAGRAM

f>4

NUMBER 028
PAGE 9 OF 1~

BDAl 16 and 17 drivers will be disabled. The BBSO signal will not be stable
during the data portion of a bus cycle, but that is of no consequence in
this design approach.

sJ
SYNC*

--l ~

100 ns.

FIGURE #5 - SYNC lOW TIMING DIAGRAM
The final section of the block diagram is the Sync low Stretcher. As
explained above, the function of this circuit is to enable the BDAl
drivers only during the address portion of a bus cycle. The lSI-II bus
timing specifications require that the address lines remain stable for
100 ns. after the rising edge of SYNC. The Sync low Stretcher delays
the rising edge of the SYNC signal for 100 ns. so that the timing specification will be met. This circuit may be fabricated from a single
flip flop and a one-shot. The one-shot timing should be set for 100 ns.
and should be triggered by the rising edge of the SYNC signal. The
falling edge of the SYNC signal cannot be used to trigger the one-shot
because the time the SYNC signal is low is unpredictable. Figure 5
shows the timing requirements of the Sync low Stretcher. This circuit
makes it possible for the MSVll-D memory module to put parity information
onto the bus during the data portion of the bus transaction.
There is an element of risk associated with using the bank a detector
described above. An analysis of the bus timing circuit diagrams from
Chapter 3 of the Microcomputer Handbook will reveal that there is not
sufficient amount of time to detect bank a and disable the drivers for
BDAl 16 and BDAl 17 and still meet the specified address to SYNC set-up
time. The bus specification requires that all addresses be stable for
at least 75 ns. at the bus receiver before the SYNC signal comes along.

~D~DD~D
COMPONENTS

GROUP
65

NUMBER 028
PAGEIO OF I'"'

)Jnote

-------1

R SYNC

~-47 ns. ~

R DALI6,17---------'¥
_

R DAL16,17

134 ns.

'!\'

.. I

WORST CASE

TYPICAL

75 ns. min.~

DAL16,17~===1====-J--'__,______ PER SPECIFICATION

8 ns. /-- RISK FACTOR

59 ns.

SAFETY MARGIN

FIGURE #6 - ADDRESS TO SYNC TIMING
Figure #6 shows the timing relationship between the received data
address lines 16 and 17 to the received SYNC pulse. The diagram shows
worst case timing, typical timing, and the timing required by the bus
specification. The worst case occurs when there is the maximum skew
between the SYNC signal and the DAL lines on the bus, and there is the
maximum propagation delay differential betwl~en the drivers and receivers
used for the DAL lines and those used for the SYNC lines. Typical bus
timing is when there is a minimum amount of bus skewing, and when all
of the drivers and receivers used are operating at typical propagation
delay times. Normally, the address lines will be stable 59 ns. before
the bus specification requires them to be stable. However, when the
unlikely worst case condition occurs, the address lines will not be
stable until 28 ns. after the bus specification requires them to be
stable. The worst case condition is extremely unlikely in systems with
short bus lengths as is the case with the nt~W 2x4, 2x8, and 2x12 backplanes.
The risk is higher when multiple backplane systems are used and when
large, single backplane systems such as the 9x6 backplanes are used.
Even in the worst case situation, modules on the bus would have to
require stable data for more than 47 ns. before the SYNC signal came
along. This, again, is an unlikely situation.

mD~DDmD
COMPONENTS

GROUP
66

NUMBER 028
PAGE 11 OF12

The approach described above is also in violation of the LSI-II bus
loading rules. Using an additional DCOOS chip to detect bank 0 results
in more than one load on several bus signals. This is not desirable;
however, it is required to minimize the bank 0 detection time. The
excess loading occurs on non-critical (non edge triggered) bus signals.
USING COMMON MEMORY
There are several things that a programmer should be aware of when using
the paging scheme described above. It was stated that the common memory
is required for interrupt vectors, the stack, the beginning and end of
all interrupt subroutines, and for the routines where page switching
occurs. It is also mandatory that data used by routines on different
pages be in common memory. The following paragraphs will elaborate on
page switching and interrupt handling.
Page switching operations are required when a routine on one page wants
to call or jump to a routine on another page. All page switching must
be done from common memory. Coding will be most efficient when a single
routine is used for page switching of jumps and another routine for
calls.
Figure #7 is an example of a routine that may be used for page
switching with calls. Briefly, this routine must store the current
page number and program counter so that it is possible to return to
the current routine. It must then set the new page number and JSR to thE~
new routine. Upon return from the new routine, the page switching
routine must restore the old page number and return to the routine that
initially called it. The original routine must specify the new page
and virtual address of the new routine. A similar approach may be
used for jumping to a new page.
Using this MACRO definition:
. MACRO
JSR
.WORD
.WORD
.ENDM

CALL X PAGE, ADDRESS
RO, PAGTRN
ADDRESS
PAGE
CALL X

The routine would be:
MOV
MOV
MOV
JSR
MOV
RTS

@#164000, -(SP)
(RO)+, - (SP)
(RO)+, @#164000
PC, @(SP)+
(SP)+, @#164000
RO

~D~DDmD
COMPONENTS

GROUP
67

FIGURE #7 -PAGE SWITCHING
ROUTINES FOR CALLS

NUMBER 028
PAGE 12 OF12

For the LSI-II interrupt mechanism to work properly, the interrupt vectors
the stack and portions of the interrupt subroutines must be located in
the common memory area. For very long iinterrupt subroutines, it may be
desirable to have only the beginning and the end of the routine in the
common memory space and the bulk of the routine on one of the extended
memory pages. The RTI instruction cann()t be executed from one of the
pages. Before exiting from the interrupt subroutine, the program must
return to conrnon memory.
A techniquE~ similar to the call page
swi tchi ng routi ne descri bed above may bE~ used for page swi tchi ng.

~D~DDlmD
COMPC»iIENTS

GROUP
68

NUMBER

).Inote

TITLE

Using the MRV11-AA for a Bootstrap ROM

DISTRIBUTION
ORIGINATOR

Unrestricted
Ted SemQle

029

DATE
1 / 12 /78
PRODUCT
MRV11-AA
PAGEl

OF2

The MRV11-AA can be a cost effective alternative to using the REV11-A
bootstrap module in LSI-11/2 systems for customers who use a custom
bootstrap ROM. Two features of the REV11-A module are not required
with the LSI-11/2 systems. Since the H9281 backplanes have built-in
termination networks, the termination networks on the REV11-A are not
required. The DMA refresh circuitry on the REV11-A is not required
either because the MSV11-D memory module is self-refreshing. Also,
the REV11 bootstrap ROMs are now soldered directly to the printed
circuit board rather than being mounted in sockets. Customers have
discovered that they void their warranty when they remove the ROM
and solder in their own custom bootstrap ROM. Using the MRVl1-AA
is a good alternative to using the REV11 because it is less expensive,
has no unneeded features, and the warranty will not be voided.
To maintain standard I/O page address assignments, only 256 x 4
ROMs may be used with the MRV11-AA. Using 512 x 4 ROMs will exceed
the 256-word window left at address 173000 in the standard I/O
page address assignments. This mayor may not be detrimental in ~
particular application.
One advantage to using the MRV11-AA in place of a modified REV11-A
that may not at first be apparent is the MSV11-D feature which allows
the memory module to expand its address range from 28K to 30K may now
be enabled. The second half of the REV11-A bootstrap ROM has a
starting address of 165000 which is in the middle of the 28K to 30K
range. This prohibited using the REV11-A in systems that had a
MSVI1-D module with the expansion feature enabled.
To configure the MRV11-AA as a bootstrap ROM module with starting
address 173000, four 256 x 4 ROMs should be inserted in rom CE6, and
the straps should be configured as follows:

~DmDD~D
COMPONENTS

GROUP
69

NUMBER 029
PAGE 2 OF ?

STRAP NAME
WO
WI
W2
W3
W4
W5
W6
W7
W8

R = REMOVED
I = INSTALLED

STRAP NAME

R
R
R

W9
WI0
Wll
.W12
W13
W14
W15
W16
W17

R
R
I
R
R

I • REMOVED
I • II![ST&-bED
It

•
I
I
R
I
R
R
R

The QJV1I PROM formatter program may be used to produce the binary
patterns for individual PROM chips.

mamOllmo

~
70

NUMBER 030
PAGE 2 OF 2

)Jnote

The following table summarizes the SRUN connections made to the 10-pin
connector:
BACKPLANE

BACKPLANE PIN CONNECTED
TO 10-PIN CONNECTOR

H9270

CHl*

DDVll-B

None--Wire Wrap Pin
Available For Customer Use

H928l

AFI

H9273
(ll/03-L Backplane)

AFI

*NOTE: Although this backplane
used to have a wire wrap
connection from CHI to
the 10-pin connector, that
wire has been deleted and
the connection put in etch.
Therefore, a customer using
an 11/03, BAll-ME, or an
H9270 with a KDIl-HA must
insert a jumper between pin
AFI and CHI to obtain the
SRUN signal at the 10-pin
connector.

~DmDDlmD
COMPONIENTS
CiROlJIP

NUMBER

).Jnote
TITLE

Extended Bus Time-Out Logic

DISTRIBUTION
ORIGINATOR

032

DATE
2 / 13

fiB

PRODUCT
KD11-HA (M7270)

KD11-HA Users
Joe Austin

PAGEl

OF3

SCOPE
This Micro Note discusses the procedures whereby a user can extend the
bus time-out delay of the KD11-HA (M7270) LSI-11/2 central processor
module using external logic. The normal time-out delay of 12.16 us.
is quite adequate for almost all applications. Occasionally, however,
a special need arises where the customer wishes to extend this delay.
Typical reasons for this could occur as a result of waiting for the
response from an exceptionally slow peripheral or allowing time for a
complete handshake with another microprocessor system.
Although a modification to the backplane is necessary, no modifications
are required to be made to the KD11-HA module.
THEORY OF OPERATION
Two connections to the bus time-out counter on the KD11-HA module have
been routed to the backplane to allow a user direct access to the
time-out logic (see Figure 1). The EN/OUT function on E23 pin 7 has
been named STOP L (time-out pulse) and is routed to backplane pin AE1.
The STB function on E23 pin 10, normally connected to ground to enable
the outputs on pins 5 (TERR L) and 6 of E23, has been named MTOE L
(time-out enable) and is routed to backplane pin AK1 where it can be
connected to pin ALl, which is grounded on the M7270 module. Pins AKI
and ALI are normally connected together by etch in order to allow for
special factory level testing of modules. Thus, when this module is
inserted into the backplane, the STB function on E23 is connected to
ground and the logic functions normally.
To extend the bus time-out delay beyond the normal 12.16 us., this
jumper between pins AK1 and ALI must be broken so that signal MTOE L
can be controlled externally. As long as this signal is kept high,
the output signal TERR L (which is used to inform the CPU control chip
of the time-out) is blocked. The 6-stage counter contained within the
(7497) chip (E23) will continue to run, however, and will count the
phase 3 clock (PH 3 H).

~D~DD~D
COMPONENTS
GRCXIP

NUMBER 032
PAGE 2

Signal STOP L can be used as a clock for driving an external counter as
shown in the figure. Based upon a microcycle clock of 380 ns., this
signal will be a 380 ns. pulse that will occur after every 64 counts, or
24.32 us. (the normal time-out delay is :32 counts for 12.16 us.).
The figure shows the procedure for interconnecting an additional counter
stage to the 7497 chip using a 7474 flip flop. Signal BSYNC insures that
the flip flop is reset prior' to the start of the bus cycle and that it
will be reset again at the end of the cycle. Signal MTOE L will be high
at the start of each bus cycle, thus blocking the TERR L line internally
to the 7497 via the STB input on pin 10. After the 7497 has counted
24.32 us., it issues the pulse STOP L which sets the flip flop. The
STB line to the 7497 then changes to ground, enabling the outputs on
E23 pins 5 and 6. The 7497 will then proceed with a normal count-down
of 12.16 us. and will generate TERR L to inform the C.P. control chip
of the bus time-out. This circuit thus produces a total bus time-out
delay of 36.48 us.
By replacing the flip flop with a multiple stage counter, additional
bus time-out times can be achieved as shown in the table.
TABL.E 1.

BUS TIME-OUTS

NUMBER OF
COUNTS OF
STOP L

NORMAL
TIME-OUT
(us. )

ADDITIONAL
TIME-OUT
(us. )

TOTAL
TIME-OUT
(us. )

0
1
2
3
4

12.16
12.16
12.16
12.16
12.16

0
24.32
48.64
72.96
97.28

12.16
36.48
60.80
85.12
109.44

TOTAL = normal + additional,
= 12.16 us. + 24 us. (no. of counts)
NOTE:

Although laboratory tests have verified this design concept, it
is provided here for information purposes only. DEC makes no
claim and shall not be liable for its accuracy or for the operation of the user's irnplementation of the design shown.

~D~DD~D
COMPONENTS
GROUP
74

OF3

vee..

' "7

71£Z'l

,.~
I

REMove

EiCtl

I3AC.KPLANE~1

- - - - - - --

_ _I

FIGURE 1.
BUS TIME-OUT LOGIC

________ ~2

W~EPLY

~z
G)C

mS:
OJ
m

W::D

Ilw

j../note

NUMBER

033
DATE

TITLE

Cables for DLV11 z DLV11-E, [)LV11-F

DISTRIBUTION
ORIGINATOR

/ 24

/78

PRODUCT

Unrestricted
Llo~d

DLV11, DLVI1-E, -F

Fugate

PAGEl

Of2

The introduction of the DLV11-EB has raised a question on which cables
can be used with "DLV" type
asynchronous interfaces. The DLV11-EB
is the basic DLV11-E plus BC01V-25 cable. For other DLV interfaces, the
BC05C-25 cable has been recommended.
The BC05C-25 is a 40-pin Berg to EIA connector cable that can plug
directly into a modem for remote use or to a null modem for local use.
This cable contains all 25 specified EIA signals, including those used
only for synchronous communication controllers. Since the DLV11 family
is asynchronous, almost half of these conductors are not used.
The BC01V-25 is identical to the BC05C-25 but contains only the 15
conductors used for asynchronous co~nunications.
Because of the pri ce di fference betw.~en these two cables - the BC01 V-25
is $88 and the BC05C-25 is $112 - future customers will probably use
the lower priced cable for their applications. This cable is available
in limited quantity now and in volume starting in June.
For those customers who require a cable with null modem capabilities,
the BC03M-XX cable is re~corrmended. This cable includes the functionality
of the H312 null modem and can be attached to the EIA connector on the
BC01V-XX, BC05C-XX, and BC21B-05 (DLV11-J cable).

~DI~DD~D
COMFONENTS
CillOUP
'76

KlMBER:

MICRO NJTE

033

PAGE 2 of 2
OATA SET CONTROL

40 PIN
CONN
DLVII-E

DB-2S

~r-

________________~B~C~0~5~c~'O~r~B~C~O~1~V~______~[:]

CURRENT
40PIN
CONN

DATASET
BELL 103
BE LL 202

LOOP MODE

MATE-NLOK

[:]---------B-C-0-5-M------~[:]

DL. V II
(REeE IVER
PASS'VE,
TRANSM I TTER
AC T IJE )

OLV11
(RECE:VER
PASSIVE,
TR.\NSp."ll TTER
PASS IVE)

40 PIN
CONN.

BC05M

DLVI1

BC05F

BC05M

[:]

DLV11
(RECEIVER
PASSIVE
TRA~SMIT1 ER
At TIVE)

40 PIN
CONN

8C05M

OLlI-,.:

DATA LEADS ONLY" MODE

08-25

OB-25

BC05rD~ BeolB

ElA/CCITT

BC03M

TERMINAL'
NULL MODEM CABLE

40 PIN

CONN

DLVI1

40 PIN
CONN

MATE-NLOK

EJ G

ErA
40 PIN
CONN

BC05F

MATE-NLOK

4C PIN
CONN.

MATE-NL0K

MATE-NLOK
BC05M

LA",6
VT52
TTY

OR - ;>~)

[:] __________-----------B-C-O-5-C--o-r--B-C--Q~1-V----------~tJ

MODEL \()3
DATASE.T

(AUTC f..AODE)

NUMBER

).Inote
TITLE

034

Configuring a 3-Box 11/03 System

DISTRIBUTION
ORIGINATOR

DATE
3 / 2

PRODUCT
11/03 Systems

Unrestricted
Dave Schanin

PAGEl

oF2

The 11/03 system box and the BAll-ME E!xpander box are both used either
stand-alone or in a multiple backplane configuration. When interconnecting
boxes in a multiple backplane system, the standard BCVlB or BCVlA cable
set interconnects the backplanes. Ho~'ever, the slave power supply in the
BAll-ME must be slaved to the master power supply in the 11/03. The front
panels on the two boxes have sockets for this purpose (see Figure 1). A
cable with a DIP plug on either end is supplied with each BAll-ME to
connect J2 on the master to J2 on the slave. The obvious problem is how
to connect a second BAll-ME into the system since J2 is now occupied.
The solution, until mid-summer, is to order a BC03Y-16 cable. This cable
has three DIP plugs on it, one at either end and one in the center of
the cable. One plug goes in J2 of each box. About mid-summer, an ECO
will have been phased in, adding J3 to all BAll-ME slave consoles. This
plug parallels J2. Therefore, a user could connect J2 on the master
11/03 to J2 on the slave BAll-ME with the cable supplied with the first
BAll-ME. J3 on the first BAll-ME can be connected to J2 on the second
BAll-ME with the cable supplied with the second BAll-ME. The BC03Y-16
will then no longer be required.

~D~~IDmD
COMPONENTS
GRCKJP
7~3

NUMBER 034
PAGE 2 OF2

"' ....... yt~TO.ON
fiIIMIR IWPL,Y
illMftR

,,c........

.. 'REMOTtI CONJIIFCTl'D TO 11. 'REMOT£!
. . R.AW 5UII'P\. Y INOICATOII
~

,,c.

H780·H and .J (Master)
."11·2

... _'fI~CTlDTOII(lll
_ " SUP"'\.'f ~.c:.lOAfIOOI'Sl.."'''f

....

H780·K and ·L (5&8ve)

FIGURE 1

momoomD
COMPONENTS

GROUP
79

NUMBER

),Inote
TITLE

DATE
4 /4
/78
PRODUCT
MRVll-AA, -BA

PROM Programning

DISTRIBUTION
ORIGINATOR

035

Unrestricted
Dave Schanin

PAGEl

of!

INTRO
Customers in a dedicated 'environment ~,ill very often store their program
in PROM. Some RAM is always necessary in a PROM-based system for a stack,
for a scratchpad, etc. Very often, the RAM on a KDlI-F is used, though
sometimes a separate memory board is used.
PROBLEM
On power-up, a program must initializE! itself to a known state. This
includes initializing any scratchpad F~M in the system. However, some
PROM customers have assumed a power-up state for the RAMs. On the early
4K RAM parts, this was generally true;~ they usually powered up to a zero
state. However, later version RAMs, ~Ihich have differential sense
amplifiers rather than single ended amps, come up in a random 1 or 0
state. A user who does not initialize the RAM will find that his PROM
program will not run unless a certain memory vendor's chips are used in
his system because of the power-up state of the RAMs. We cannot, of
course, guarantee a particular module will have a particular vendor's
chips. It is an obligation of the programmer to clear all RAM on program
power-up.
SOLUTION
The software engineer must assure that all RAM in a PROM based system is
cleared on program initialization.

~D~IDD~D
COMPONENTS

GROUP
~30

NUMBER

J.lnote
TITLE

036
DATE

Core Memory in 11/03-L Backplane

DISTRIBUTION
ORIGINATOR

5 /

16 /

PRODUCT

Unrestricted

H9273; MMVII-AA

Ted Semple

PAGE 1 OF

THE MMVII-AA CORE MEMORY MODULE MAY NOT BE USED WITH THE 11/03-L
BOX, THE BAII-NE EXPANDER BOX, OR THE H9273 BACKPLANE.
The MMVII-AA Core memory module is a quad size printed circuit board.
Unlike other quad modules which make all connections to the LSI-II
bus via the A and B card edge connectors, the Core memory module also
uses the C and D connectors to interconnect to the LSI-II bus. The new
11/03-L backplanes do not have the LSI-II bus distributed on the C and
D fingers. Therefore, modules used with the 11/03-L backplane must make
all bus connections via the A and B card edge connectors.
To use the MMVII-AA Core memory module in the 11/03-L backplane would
require the addition of 10 wires to the backplane to make interconnections
to the LSI-II bus from the C and D connectors and to provide daisy-chain
grant continuity on the LSI-II bus. To do this would be impractical
because the backplane used in the 11/03-L box does not have wire-wrappable
connector pins. To solder wires onto the backplane would, at best, be a
risky operation.

~D~DDmD
COMPONENTS

GROUP
81

NUMBER

).Inote
TITLE

DATE

C-D Interconnect Scheme

DISTRIBUTION
ORIGINATOR

037
30
5
PRODUCT

Unrestricted

/ 78

H9273;
BA11-N; 11/03-L

Joe Austin

PAGE 1 OF 3

H9273 BACKPLANE
The BA11-N backplane is a 9x4 backplane that accepts both double height and
quad height modules. The backplane structure is unique, providing two
distinct buses - the LSI-II bus and the C-D bus as shown in Figure 1. Modules
are inserted in rows 1 and 9 of the backplane. The LSI-II bus signals appear
on slots A and B; the C-D bus signals appear on slots C and D.
LSI-II BUS SIGNALS
The LSI-II bus in the H9273 backplane is supplied by slots A and B. These
signals are bused to the same pin in all nine rows of the backplane. Interrupt
acknowledge and bus grant signals (BIAKO L, BIAKI L, BDGMO L, and BDGMI L)
are not bused, being corrected, instead in a way that allows the grant lines
to be passed on in a priot~ity chain in order from slot 1 to slot 9, with
slot 1 having the highest priority and slot 9 the lowest.
C-D BUS SIGNALS
The C-D bus is supplied by slots C and D as shown in Figure 2. The +5V supply
voltage is bused to all rows on pin A2 of slots C and D (i.e., pins CA2 and
DA2). Likewise, ground connections on pins CC2, CT1, DC2, and DT1 are bused
to all rows. All other pins connect only to an adjacent row. For example,
pin CF2 of any row connects .9.!llY. to pin CF1 of the adjacent higher numbered
row. Pins on side 2 of the slot (B2, C2, etc.) connect to the adjacent higher
numbered row (except DT2, which connects to CT2 of the adjacent lower
numbered row), while pins on side 1 of the slot (B1, C1, etc.) connect to
the adjacent lower numbered row (except pin AI, which connects to C1 of the
adjacent higher numbered row). Thus, each row, except 1 and 9, has 33
signal connections (i.e., connections other than +5V and ground) to both
the adjacent higher numbered row and the adjacent lower numbered row.

mD~IID~D
COMPC~ENTS

(iRC)uP

812

NUMBER 037
PAGE 2 OF3

LSI-II BUS

C-D BUS

r-----------~-----------~ r~----------~-----------,
SLOTA
ROW 1

ROW2

ROW3

SLOT I

SLOT C'

LSI-II 9PTION 1

LSI-II ~PTION 2

LSI-II ~PTION 3

I
I

ROW4

ROW 5

LSI-II qPTION 4

I
I

LSI-II o'PTION 5

ROWS

LSI-II OfTION 6

ROW1

ROWS

LSI-II OfTION 7

I
I

LSI-II OIPTION 8

I
ROW9

SLOT 0

LSI-II O~TION 9

VIEW IS FROM MODUl.E SIDE OF CONNECTORS

FIGURE 1 -- H9273 BACKPLANE

mD~DDmD
COMPONENTS

GROUP
83

NUMBER 037
PAGE 3 OF 3
COl

+5V

~ Ai

~~ ~
Bl-

B2
~

-..zl

E'I

F'I

-<I'

r-- --0

. . . . . 1"0

HI
0

1~1'

)

--0

Mil

RI
0

RI
I

Tl-

)

v..t

)

001

002

Ad...,

~L.

Bl)

.... k;

Cl
0

Oil

....El

Kl
W3 --0

L.1

r-I

IL __

--0

Ml
0

)

0
0

111

0
0

Sl
0

T2
U2

VI
0

r-~2
X

VI
0

0
0
0

DOB

009

0.....,)

,..~

L(
.}

(

(I
}
o
o
o
o

}

Ul
0

)

0
0

0
0
0

0
0

)

-CI

I
I __
L

C09

Cl
0

COB

Bl
0

GND

C02

VIEW FHOM PIN SIDE
FEATURES:
• ALL PINS Al CONNECT TO PINS Cl IN
THE NEXT LOWEST SLOT.
• ALL PINS A2 CONNECT TO +5 VOLTS.
• ALL PINS T2 OF SLOT C ARE CON·
NECTED TO PIN T2 OF SLOT 0 IN THE
NEXT LOWER SLOT.
• ALL PINS C2 AND PINS Tl ARE GROUND.
• JUMPER W2 IS CONNECTED ACROSS
PINS Kl AND Ll IN SLOT CONLY.
• JUMPER W3 IS CONNECTED ACROSS
PINS Kl AND L1 IN SLOT 0 ONLY,

FIGURE 2 -- C-D BUS WIRING
MR-1564

~DmDIDmD
COMPONENTS

GROUP
8L~

)./note

NUMBER

038
DATE

TITLE

Diagnostics for 30K Memories on LSI-Ills

DISTRIBUTION
ORIGINATOR

13 /

PRODUCT

Unrestricted
Llo~d

MSV11-D

Fugate
PAGE 1

OF 1

The recent introduction Of the MSV11-D memory system allows for the jumper
selection of 2K of memory in the space historically reserved for the I/O
page. When this jumper is installed, the LSI-II is capable of addressing
30K words of memory; however, the installation of this jumper causes some
of the LSI-II diagnostics to exhibit problems.
These problems center around the fact that the first four locations in
the I/O page have been used by diagnostic software. The principal use of
these locations was in the design of autosizing algorithms and as a means
of validating the correct operation of the hardware to conditions of
non-existent memory references.
For the MSV11-DD, the memory diagnostic is being upgraded to isolate
problems in the 28-30K range; however, there are no plans to modify other
diagnostics to support this memory space. Customers should be aware that
when a complete system diagnostic is required, they will have to restrap
their MSV11-DD memory for 28K if they expect all standard DEC diagnostics
to operate.
An effort will be made in the future to document where diagnostics fail
as a result of the 30K strap.

~D~DDmD
COMPONENTS
GROUP
85

NUMBER

).Inote
TITLE

DATE

DMA Request/Gran.t Timing

DISTRIBUTION

039

/ 27 /

PRODUCT

All DMA Users

All
ORIGINATOR

Ted SemEle

PAGE 1

OF 2

Some LSI-II users have discovered that: their Direct Memory Access modules
are not compatible with the KDll-HA processor module, even though they had
been successfully used with KDll-F processor modules. There are no compatibility problems with DIGITAL's DRVll-B Direct Memory Access controller
or with DIGITAL's DCOIO DMA controller chip. Compatibility problems did
occur, however, with REVll modules and with users' custom-designed DMA
interfaces. Revision J REVll's have had an ECO incorporated that makes
the REVll's DMA refresh compatible with all LSI-II processors. (Users
that desire DMA refresh in systems with a KDll-HA processor must use a
Revision J or later version of the REVll module.)
Both the KDll-F processor and the KDlJ.-HA processor meet the timing
requirements for DMA on the LSI-II bus:. There is a difference between
processors -- this is the amount of time taken to respond to bus signals.
The KDll-F takes longer to issue a Direct Memory Access Grant (DMG) in
response to a Direct Memory Access Request (DMR). The KDll-F also takes
longer to de-assert DMG after receiving a Select Acknowledge (SACK).
The compatibility problem is caused by the manner in which a Direct Memory
Access controller responds to a Direct: Memory Access Grant issued by the
processor. The LSI-II bus specification requires that a Direct Memory
Access controller meet three criteria before issuing a SACK signal. DMG
must be asserted and SYNC and RPLY must be de-asserted before issuing a
SACK signal. This requirement is sho~rn by arrows on the timing diagram
on Page 2.
Some DMA controllers have interpreted the above timing requirements to mean
that a SACK signal can be issued immediately upon the receipt of DMG from
the processor and then waiting until SYNC and RPLY are de-asserted before
actually starting a bus transaction. The processor module de-asserts DMG
upon receipt of a SACK signal from the: DMA controller. The apparent failure
mode for most DMA controllers is that they require DMG be asserted as well
as SYNC and RPLY de-asserted when they start a bus transaction. If DMG is
no longer present, then the DMA controller may "hang-up" the bus with SACK
asserted. This can happen with either the KDll-F processor or the KDll-HA
processor. However, this is more like:ly to happen wi th the KDll-HA processor
because the KDll-F processor has a longer internal time delay from the
receipt of SACK to the de'-assertion of DMG.

~D~I~DmD
COMPONENTS
GRC)uP

NUMBER 039
PAGE 2 OF 2

)lnote

There are two ways to fix this problem. The first is for the DMA controller
to meet the actual bus timing requirements before issuing the SACK signal.
The second approach which is not as acceptable but still works with the
current LSI-II processors is to latch the DMG signal on the DMA controller
module so that the board does not forget that it received a grant. By
latching the DMG signal, the board can then issue SACK immediately upon
receipt of the DMG.

T DUIII

III DUO

T UCI(

_ _ _ _ _- . J

-----------+--~p

~/T SYNC

~IT IIIPL Y

T DAL

(:~:~.::!i

--IIIO-T-[-' _ _ _ _---J

ADDR

~_ _..J

DATA

' -_ _ _ _ _ _---:It.-_ __

rI"u""",, .....ICI bWI ."vI' ,,,,uti 0'" INa rec.'v" .11., ....
cIo" ••• b.lo.
T. IVI Drive, I"""
III· h. Ro•• ,.., 0..,,,,,'

, T "wi", 11\0." .t
2. 511.0' ._. ",.11 ••• • ,,

) lvo

Ot,.., 0..,.... OM I •• 1II••• i ... I .......... _

I •••••••••• , .. iii

DMA Request/Grant Timing

mDmDomo
COMPONENTS
GROUP
87

PRINTED IN U

.3/77 040 03 030

NUMBER

).Inote

040

DATE
TITLE

Patches forBASIC/PTS on LSI-II

DISTRIBUTION
ORIGINATOR

PAGE 1

OF 2

6
27
PRODUCT
BASIC/PTS

Unrestricted
Rich Billi~

The PDP-II Paper Tape BASIC software package (BASIC/PTS, QJ900) is not
designed to operate on the LSI-II processor. The patches required for
LSI-II operation are 'supplied in this Micro Note. Although these patches
have been used successfully in a number of installations, they are not
"official", and BASIC/PTS is not an officially-supported product on the
LSI-II.
The procedure for patching BASIC/PTS is as follows:
1.

Load BASIC with the Absolute Loader.

The system responds:

BASIC VOOlA
OPT FNS: A-ALL, N-NONE, I-IND
2.

Press the BREAK key to enter OD'!'.

The system responds:

Determine whether you have BASIC/PTS with or without strings.
(System responses are underlined for clarity. The character 1
indicates a carriage return.)
For BASIC/PTS with :strings, enter the following patches:
@xxxxx
@15l60/l06746 ~
@15l62/ 106427 ).
~152l4/ 106426 ).
@15222/ 106426;1
@20620/l06 746 ~
@20622/ 106427 ~
@206 72/106426 iJ.
~20700/l06426~

~D~~DD~D
COMPONENTS
CiROUP
~38

j./note
For BASIC/PTS without strings, enter the following patches:
@xxxxx
@13400/1067461
@13402/106427 )
.113434/106426 _
!13442/106426 ~
~16610/106746;2
~16612/106427 ')
~16662/ 106426 ~
~166 70/106426 ,.

Respond to the question:
OPT FNS:

DISCLAIMER:

A-ALL, N-NONE, I-IND

Although the patches are known to work, this procedure
has not been officially tested.

mD~DDmD
COMPONENTS
GROUP
89

PRINTED IN U.:

;3177 040 03 030

NUMBER 040
PAGE 2 OF 2

NUMBER

).Inote

041

DATE
7

New Functionality for BDV ll--AA Boo t

TITLE

DISTRIBUTION
ORIGINATOR

PRODUCT
BDVll-AA

Unrestricted
Llo~d

Fugate

PAGE 1

OF 1

Engineering is currently going through a ROM revision to provide new
functionality for the BDVll-AA boot. Specifically, this revision adds
the following features to the BDVll-;~:
1.

Add boot for the RXV2l floppy disk.

Code to auto load the full l6KW PROM (2716 type) or 2K PROM
(2708 type) resident on the board in a manner which is transparent to the user.

Maintain unattended boot but provide option to boot by device
name mnemonic.

Add DLVll-F DECnet boot.

Modify the memory t~est to support the 30K word MSVll-DD.

Add a mechanism so that new boot devices can be added by additional
ROMs wi thout change to the opera,tor interface or the basic DECg,upplied ROMs.

These additions do not a:ffect the current functionality of the BDVll.
The revision number for the BDVll-AA may be identified by ROM part
numbers as follows:
SOCKET

REV. A PART 4ft

REV. B PART 4ft

E48

23-0l0E2

23-045E2

E53

23-0llE2

23-046E2

It is our plan to phase this revision in during July.

~D~DDmD
COMPONENTS
CiRC)UP
9f)

NUMBER

)lnote
TITLE

042

DATE

Removins Modules from "Live" BackE lanes

DISTRIBUTION

PRODUCT

LSI-11 Customers

All
I

ORIGINATOR

Joe Austin

PAGE 1 OF

PROBLEM
Occasionally the situation arises where users would like to remove a
module from a backplane while the DC bus power is on. The primary reason
for doing this is to prevent the loss of programs stored in the MOS
memory.
SOLUTION
Our single answer to this is:
! ! DON'T

DC operating power on the bus should always be turned off whenever a
module is being removed or inserted into a backplane. Failure to do so
will risk d~maging not only the module being changed but also the other
modules in the backplane. The inconvenience of a damaged module is far
greater than the inconvenience of the loss of contents of MOS memories
suffered by turning the backplane power 'off.
REASONS
1)

When power is turned off in a system, the DC voltages decay exponentially in a controlled known tested manner. When a module is removed
from a live backplane, this controlled decay is bypassed and all power
stored on the module must decay as best as it can without the benefit
of a ground return line.

Removing or inserting modules changes the loading on the backplane
which causes spikes on data, control, and power lines. Voltages and
grounds are not usually removed simultaneously; any combination is
possible, including the removal of a ground while +5 and +12 are
active. This process, along with spikes that occur as an active
line is connected or disconnected, causes random effects, some of
which can overload IC's, especially MOS circuits. The probabi1i Y
of a MOS circuit being damaged is high, but the probability of T L
circuits failing under such circumstances is also high.

~D~DD~D
COMPONENTS
GROUP
91

)Jnote

NUMBER 042
PAGE 2 OF 2

If a program is running at the time, it is almost certain that it
will malfunction when the module is (;hanged.

It is almost a certainty that a module will be damaged after fewer
than 10 removals or insertions into u "live" backplane.

ALTERNATIVE PROCEDURE
One method of turning off bus DC power while retaining the memory contents
requires the use of techniques similar to providing battery backup for the
MSV11-C, D, and E series memory modules. The procedure is to provide a
separate power supply similar to a batte:ry backed up supply for the
refresh logic of these modules that is s.~parate from the bus power.
Detailed procedures for providing battery backup for these memory modules
is described in the Application Note entitled "Battery Backup for LSI-11
Microcomputer Systems", document #ED-0937l. With the memory modules
backed up in this manner, the remainder of the bus is "dead", and the
probability of damage being caused to modules removed from the backplane
is considerably reduced. The following restrictions still exist, however:
1)

Memory modules using thE~ alternate power source cannot be removed;

When removing/inserting modules immediately adjacent to the memory
modules, ensure that the module being moved does not make physical
contact with the module containing the alternate power. Such
contact could conceivably cause a short that would either damage one
or more modules or caUSE~ loss of memory contents.

Even though the main bus power is off, some bus signals might be active
due to the presence of the refresh power on the memory modules. These
signals might be active due to the fact that refresh power is sometimes
routed to bus circuits involved in external refresh. Even in a selfrefresh configuration, the routing of refresh power throughout the etch
of the memory module might leave some bus drivers or receivers active.
This has the potential for causing problems as a result of removing
or inserting other modules in the ba.ckplane, but because of the low
power levels, the probability of damage is low.

DISCLAIMER
The information in this document is furnished for information purposes
only. Further development is necessary by the user in order to ensure
safe operation. The batte>ry backup proc:edures defined in the Application
Note referenced above have been tested. The removal/insertion of modules
under these conditions has not been tested. Consequently, DEC makes no
claims and shall not be liable for the cLccuracy or for the operation of
this board removal/insertion procedure.

~DmDDmD
COMPONENTS

GROUP

PRINTED IN

u.s.

1/77 040 03 030

NUMBER

),Inote
TITLE

Backplanes for the RLVII (RLOl)

DISTRIBUTION
ORIGINATOR

RLVII Customers and Users

DATE
7

043

19 /

PRODUCT
RLVll, RLOI

Joe Austin

PAGE 1 OF 2

PROBLEM
The control logic for the RLVII option is contained on two quad modules
that need to be interconnected. Signals are brought off these modules
on connector fingers in slots C and D to allow for this interconnection
via the special etch of the C-D side of the H9273 backplane (Micro Note #037).
QUESTION NO. 1
Can different backplanes be used for the RLVII disk modules for the
LSI-II and PDP-ll/03 systems?
ANSWER NO.1
No. The only backplane that will support the RLVII disk modules is
the H9273. The H9273 backplane can be purchased by itself; it is also
included in the PDP-ll/03-L series products and is included in the
expansion box, BAll-N.
QUESTION NO.2
Can any other DEC backplanes containing the LSI-II bus be modified to
accept the RLVII modules?
ANSWER NO.2
No. There are no other bused backplanes that will accept these modules
and there are no bused backplanes that can be modified to accept them.
The DDVll-B 9x6 backplane, with its uncommitted slots E and F, provides
+5V and ground to slots E and F according to standard DEC pin assignments.
A conflict exists between one of these standard assignments and a signal
on the C-D interconnections between the two RLVll modules. Because of
this conflict, the two RLVII modules cannot be interconnected by wirewrapping appropriate pins of the E-F slots of the DDVll-B. The DDVll-B
cannot be modified because it is a multi-layer board with +5V and ground
in the middle layers.

~D~DD~D
COMPONENTS

GROUP
93

NUMBER 043
PAGE 2 OF2

QUESTION NO.3
Can the unbused backplane, the H927l, be wire-wrapped to accommodate
the RLVll?

ANSWER NO.3
We recommend against doing this. Wire-wrapping the H927l backplane
represents an extremely high-risk situation to the user which is
neither cost-effective nor supported by DEC. The high risk exists
because wire-wrapping i~creases the bus capacitance and crosstalk.
This violates the bus specification and decreases significantly the
system reliability.

PHINTED IN u.s.~

3/77 040 03 030

)lnote
TITLE

Console ODT "L" Conunand on 30K S~stems

DISTRIBUTION

All MSVll-D Users

NUMBER
044
DATE
7

26 /

PRODUCT
MSVll-D, -E

ORIGINATOR

Rich BilliS
PAGE 1 OF 1

The Console ODT "L" conunand, which is normally used to load the paper
tape absolute loader, will load into the low 28K words of memory only.
Therefore, on 30K word systems, the "L" command will still load the
absolute loader just below the 28K word boundary.
The algorithm used by the console micro-program in executing this
conunand is:
1.

Starting downwards from address 160000 (8), try to write each
word of memory until the highest address location installed
responds.

Write the CSR address given in the "L" conunand into this
highest RAM location for later use by the absolute loader.

Start the loading process.

This memory sizing technique will fail to correctly calculate the
highest read/write address if MRVll-BA EPROM board(s) with the replyto-DATO ECO are installed above the read/write memory in the LSI-II's
memory map.
If your application makes non-standard use of the "L" connnand,
please note how the memory sizing algorithm operates in 30K systems.

~D~DD~D
COMPONENTS
GROUP
95

).Inote
DLV11-F Replacement for the DLV11

TITLE

DISlRIBUTION

PDP-11/03 ruld LSI-II Users

ORIGINATOR

Joe Austin

NUMBER

046A
SUPERSEDES uIDTE #046

DATE

12 /

/78

PRODUCT

DLV11; DLV11-F
PAGE 1

OF 3

The DLV11-F is almost a direct rep1acemen.t for the DLV11 and is now being shipped
in lieu of the DLV11. The factory configuration of the jumpers on both modules
makes them functionally equivalent, even though the jumpers themselves are
different.
Foreward compatibility (the DLV11-F repla.cing a. DLV11) is maintained in all but
three areas:
(1)

The DLV11 uses bit 15 of the recei.ve CSR to indicate dataset status
when in the EIA mode; no such bit or function exists on the DLV11-F.
(This bit is sometimes used by customers as an operational status bit
for terminals as well as modems.)

(2)

When the 20 rnA transmitter on the DLV11 is changed from active to
passive, the flow of current is also reversed. However, the current flow is
not normally reversed when the DL\r11-F transmitter is changed to passive.
This means that plug compatibilit)r is not maintained with the normal
configura tion jumpers. Fortuna tely, this problem can be easily overcome
by crossing the configuration jumpers between the transmitter and the
COlmector on the DLVl1-F, as shown in Figure 1. Since the configuration
jumpers use wire wrap pins, this change is easy to make. (The ntunber
of users that will be affected by this is extremely small.)

(3)

The DLV1l-F does not accorrnnodate ZOO baud.

DLV1l-F ._- The most significant additional features of the DLV11-F are the
separate, prograrmnable baud rates for both the transmit and receive
lines; the baud rate increase to 19200 baud; and the additional
error status bits.
(4)

TIle DLVl1-F is cleared by INIT, wllereas the DLV11 is cleared by DCOK.
This difference has a significance only in that the two modules respond
differently whenever the system is initialized. This difference usually
shows up when the LSI -11 is being down line loaded from a hos t computer.
If the host initializes the bus with a RESET corrnnand, then the DLV1l-F
will generate a different response to the host than will the DLVl1.

~DmDDmD
COMFOMENTS
GROUP
96

j../note
(5)

NUMBER 046A
PAGE 2

The DLV11-F automatically configures 110 baud lines for 2 stop bits and
all other baud rates for 1 stop bit. The DLV11 configured the stop bits
separately from the baud rate, allowing any combination of the two. It
is believed that it is possible to connect the jumpers on the DLV11-F in
such a way as to get around this difficulty. If so, it will be discussed
in a later M[cro Note.

~D~DDmD
COMPONENTS
GROUP
97

OF 3

NUMBER 046A
PAGE 3 OF 3

____________________________DLV1'·F
-JA~____________________________~,

+5V

~12V

"ART OF
J\CTIVE
TRANSMITTER

'--.:~-----~O

XBUF

BC05MCABLE

C4AI

o---.-~ AA)

SERIAL
OUT 1+1

TRANSMIT
DATA

PASSIVE TRAI'\ISMITTER

c.J---+-f KK

SERIAL

OUT I-I

'PART OF
A.CTIVE
TRANSMITTER

FIGURE 1 -- DLVII-F TRANEMITTER CONFIGURED FOR PASSIVE
20 rnA OPERATION AND DLVII-COMPATIBLE REVERSED
CURRENT FLOW

~DmDD!~D
COMPOMEKfS

CiROUIt
98

).Inote

NUMBER

047
DATE

TI1LE Incompatibility Between the REVII and the L8I-11/23

12/ 19 /78
PRODUCT

DIS1RIBUTION
ORIGINATOR

Unrestricted

KDF11 , REV11

Joe Austin

PAGE 1

OF 2

PROBLEM
The ROM bootstrap on the REV11-A and -C will not work with the LSI-11/23 processor
eKDF11). Any attempts by the LSI-11/23 processor to run this bootstrap will cause
the system to fail.
SOLUTION
In all cases where the REV11 is installed in a backplane containing the LSI-11/23
processor, the bootstrap on the REV11 must be disabled. This is accomplished by
removing W4 from the REV!l module (M94ntr-YA, -YC).
RFASONS FOR FAILURE
TWo programming bugs exist in the REV11 ROM that are incompatible with the KDF11.
The first occurs in the memory address test at location 173712 where the following
illegal addressing mode combination is used: MOV R2, (R2)+, This instruction is
executed differently in the LSI-11/23 than it is in the LSI-II.
The second bug occurs at location 165326 in the RX01 bootstrap. In this case, a
write byte instruction is used where a write word instruction should be used. The
write byte instruction assumes that bit 14, which is used by the RX01 as an
initialize command, is a zero. With the LSI-II processor, bit 14 is zero; with
the LSI-11/23, it is not.
REMAINING USEFUL FUNCTIONS
With the ROM disabled, the REV11 can be used as a terminator in LSI-11/23 systems,
and it can be used as a refresh source for memory modules that do not have internal
refresh.

~D~DDmD
COMPONENTS
GROUP
99

NUMBER 047
PAGE 2 OF 2

ALTERNATE BOOTSTRAPS
Bootstraps are provided for several peripllera1s on the following modules that
are compatible with the LS!-11/23:
MXVll (with the MXVII-A2 ROM set)
RLVll (RLOl)
RXVll (RXOl)
RXV21 (RX02)
RKVll (RK05) (See NOte 1)
'IU58

BDVII-M (with the -045 and -046 RCM?l
RKVll (RK05) (See NOte 1)
RLVll (RLOl)
RXVll (RXOl)
RXV21 (RX02)

DECnet
NOTE 1:

The RKVll cannot be used in LS!-11/23 systems using 18-bit
addressing; i.e., with greater ~rran 64KB of memory.

~D~DDmD
COMPC)MENTS
~OUP
1~)O

PRELIMINARY .
NUMBER

)lnote

048
DATE

LSI-ll/23 Instruction Timing

TITLE
DISTRIBUTION
ORIGINATOR

12 /

/ 78

PRODUCT

Unrestricted

KDFII-A

Ted SemEle z Doug Swartz &Burt Hashizume

PAGE 1

OF 10

This Micro Note consists of four sections:
1.0
2.0
3.0
4.0

Instruction Execution Time--Standard PDP-II &EIS
Floating Point Instruction Timing
DMA Latency
Interrupt Latency

1.0 -- LSI-l1/23 INSTRUCTION EXECUTION TIME--STANDARD PDP-II &EIS
The execution time for an instruction depends on the instruction itself, the modes
of addressing used, and the type of memory referenced. In most cases, the instruction execution time is the sum of a Basic Time, a Source Address (SRC) Time, and
a Destination Address (DST) Time.
INSTR TIME = Basic Time + SRC Time + DST Time
(BASIC TIME = Fetch Time + Decode Time + Execute Time)
Some of the instructions require only some of these times.
The tables that follow are typical (typ. gate delays, max. MSV11 access time,
refresh overhead, and 40 ns. bus propagation delays) instruction execution times
for standard memories. A 300 ns. microcycle time is assumed. Times can vary
,:!:.20%. All timing is in microseconds unless otherwise noted.
If memory management is enabled, add .16 us. for each memory reference. To
arrive at incremental value to add to the instruction times given in the tables,
use the following (select numbers from the memory cycle column):
Increment = .16 (reads and writes) + .32 (read/modify/write)

~D~DD~D
COMPONENTS
GROUP
101

NUMBER 048
PAGE 2 OF 10

j../note
TABLE #1 -- BASIC TIMES
Memory Cycles
MicroCycles

MOV, CMP, BIT,
ADD, SUB, BIC, BIS,
XOR, SXT, CLR, TST,
SWAB, CCM, INC, DEC,
NEG, ADC, SBC, ROR,
ROL, ASR, ASL, MFPS

MTPS

Instructions

MSV11-C

MSV11-D

MSV11-E

1.85 us.

1.72 us.

1.76 us.

4.85 us.

4.72 us.

4.76 us.

MFPI (D)

4.25 us.

4.12 us.

4.16 us.

MTPI (D)

3.10 us.

2.85 us.

2.93 us.

MUL

78-80

24.65 us.

24.52 us.

24.56 us.

DIV

132-167

50.75 us.

50.62 us.

50.66 us.

ASH

14-101

30.95 us.

30.83 us.

30.86 us.

ASHC

21-155

47.15 us.

47.02 us.

47.06 us.

All Branch Instructions

1.85 us.

1.72 us.

1.76 us.

SOB (Branch)
(No Branch)

7
6

1
1

2.75 us.
2.45 us.

2.62 us.
2.32 us.

2.66 us.
2.36 us.

RTS

3.40 us.

3.15 us.

3.23 us.

MARK

4.90 us.

4.65 us.

4.73 us.

RTI, RTT

5.55 us.

5.17 us.

5.29 us.

Set or Clear C,V,N,Z

2.75 us.

2.62 us.

2.66 us.

HALT

21-25

WAIT

3.05 us.

2.92 us.

2.96 us.

RESET

8-430

W RMW

124.70 us. 124.57 us. 124.61 us.

~D~~DD~D
COMP4:::tNENTS
CiROUP
1102

NUMBER 048
PAGE 3 OF 10

).Inote
TABLE #1 -- BASIC TIMES (CONTINUED)
Memoty Cycles
MicroCycles

IMT, TRAP

lOT, BPT

JMP (mode 1)

(mode 2)
(mode 3)
(mode 4)
(mode 5)
(mode 6)
(mode 7)

5
6
6
6
7
7
9

1
1
2
1
2
2
3

JSR (mode 1)
(mode 2)
(mode 3)
(mode 4)
(mode 5)
(mode 6)
(mode 7)

9
10
10
10
11
11
13

1
1
2
1
2
2
3

Instructions

TABLE #2
Source
Addressing (mode 0)
(mode 1)
(mode 2)
(mode 3)
(mode 4)
(mode 5)
(mode 6)
(mode 7)

0
2
2
4
3
5
5
7

MSV11-C

MSV11-D

MSV11-E

9.11 us.

7.95 us.

8.07 us.

10.01 us.

8.85 us.

8.97 us.

2.15 us.
2.45 us.
3.10 us.
2.45 us.
3.40 us.
3.40 us.
4.65 us.

2.02 us.
2.32 us.
2.85 us.
2.32 us.
3.15 us.
3.15 us.
4.27 us.

2.06 us.
2.36 us.
2.93 us.
2.36 us.
3.23 us.
3.23 us.
4.39 us.

4.38 us.
4.68 us.
5.33 us.
4.68 us.
5.63 us.
5.63 us.
6.88 us.

3.86 us.
4.16 us.
4.69 us.
4.16 us.
4.99 us.
4.99 us.
6.11 us.

3.90 us.
4.20 us.
4.77 us.
4.20 us.
5.07 us.
5.07 us.
6.23 us.

0
1.12 us.
1.12 us.
2.25 us.
1.42 us.
2.55 us.
2.55 us.
3.67 us.

0
1.16 us.
1.16 us.
2.33 us.
1.46 us.
2.63 us.
2.63 us.
3.79 us.

RMW

1
1
1
1
1
1
1

SOURCE TIMES
0
1.25 us.
1.25 us.
2.50 us.
1.55 us.
2.80 us.
2.80 us.
4.05 us.

1
1
2
1
2
2
3

~DmDDmD
COMPONENTS
GROUP
103

)lnote

NUMBER 048
PAGE 4 OF 10

TABLE # 3 - - DESTINATION ADDRESSING
Memory Cycles
Instructions
MOV, CLR, (mode 0)
SXT, MFPS, (mode 1)
(mode 2)
MTPI (D)
(mode 3)
(mode 4)
(mode 5)
(mode 6)
(mode 7)
CMP, BIT,

TST

(mode 0)
(mode 1)
(mode 2)
(mode 3)
(mode 4)
(mode 5)
(mode 6)
(mode 7)

MTPS, MFPI (D), (mode 0)
MUL, DIV, ASH, (mode 1)
ASHC
(mode 2)
(mode 3)
(mode 4)
(mode 5)
(mode 6)
(mode 7)
BIC, BIS,
ADD, SUB,
SWAB, COM,
INC, DEC,
NEG, ADC,

SBC, ROR,
ROL, ASR,
ASL, XOR

(mode 0)
(mode 1)
(mode 2)
(mode 3)
(mode 4)
(mode 5)
(mode 6)
(mode 7)

MicroC:lcles
0
4
4
5
4
6
6
8

MSV11-C

MSVII-D

MSV11-E

0
2.23 us.
2.23 us.
3.18 us.
2.23 us.
3.48 us.
3.48 us.
4.73 us.

0
1.84 us.
1.84 us.
2.66 us.
1.84 us.
2.96 us.
2.96 us.
4.09 us.

0
1.84 us.
1.84 us.
2.70 us.
1.84 us.
3.00 us.
3.00 us.
4.17 us.

1
1
2
1
2
2
3

0
1.55 us.
1.55 us.
2.50 us.
1.55 us.
2.80 us.
2.80 us.
4.05 us.

0
1.42 us.
1.42 us.
2.25 us.
1.42 us.
2.55 us.
2.55 us.
3.67 us.

0
1.46 us.
1.46 us.
2.33 us.
1.46 us.
2.63 us.
2.63 us.
3.79 us.

1
1
2
1
2
2
3

0
0.35 us.
0.35 us.
1.30 us.
0.35 us.
1.60 us.
1.60 us.
2.85 us.

0
0.22 us.
0.22 us.
1.05 us.
0.22 us.
1.35 us.
1.35 us.
2.47 us.

0
0.26 us.
0.26 us.
1.13 us.
0.26 us.
1.43 us.
1.43 us.
2.59 us.

0
3.18 us.
3.18 us.
4.13 us.
3.18 us.
4.43 us.
4.43 us.
5.68 us.

0
2.66 us.
2.66 us.
3.49 us.
2.66 us.
3.79 us.
3.79 us.
4.91 us.

0
2.70 us.
2.70 us.
3.57 us.
2.70 us.
3.87 us.
3.87 us.
5.03 us.

1
1
1
2

RMW

1
1
1
1
1
1
1

3
3
4
3
5
5
7
0

-1
-1

0
-1
:1
:1
3

5
5
6
5
7
7
9

1
1
1
1
1
1
1

1
1
1
2

~D~DDmD
COMPC:»IENTS
Ci~OUP

104

NUMBER 048
PAGE 5 OF 10

2.0 - - FLOATING POINT INSTRUCTION TIMING
The execution time of a KEF11-A floating point instruction is dependent on the
following:
1.

type of ins truc tion

type of addressing mode specified

type of memory

In addition to the above, the execution time of many instructions, such as ADDF,
are dependent on the data.
Table 1 provides the basic instruction times for addressing mode 0 with a microcyc1e
time of 300 ns. Tables 2 through 5 show the additional time required, using the
MSVl1-E, for instructions with other than mode O. Refer to the notes for the
execution time variations for the data dependent instructions.
TABLE 1
Instruction

Microcycles

Mode 0
Time (us.)

Notes

LDF
LDD
LDCFD
LDCDF
CMPF
CMPD
DIVF
DIVD
ADDF
ADDD
SUBF
SUBD
MULF
MULD
MODF
MODD
TSTF
TSTD

28
36
40
55
65
71
301
795
121
139
124
142
264
641
682
693
28
32

9.15
11.55
12.75
17.25
20.25
22.05
91.05
239.25
37.05
42.45
37.95
43.35
79.95
193.05
205.35
208.65
9.15
10.35

1,2,19
Use Table 2
1,2,23
1,4
1,5
14,15
14,15
1,29,41,43,44
1,30,42,43,44
1,16,17,18,20,25,27,28,41,43,44
1,16,21,22,24,26,27,28,42,43,44
1,16,17,18,20,25,27,28,41,43,44
1,16,21,22,24,26,27,28,42,43,44
1,29,31,41,43,44
1,30,32,42,43,44
1,26,30,32,33,34,35,41,43,44
1,26,30,32,33,34,36,42,43,44
1,2,37
1,2,37

mD~DDmD
COMPONENTS
GROUP
105

Modes 1 thru 7

)./note

NUMBER 048
PAGE 6 OF 10

TABLE 1 (CONTINUED)
Microclcles

Mode 0
Time (us.)

STF
SID
STCDF
STCFD
CLRF
CLRD

18
26
65
48
36
40

6.15
8.55
20.25
15.15
11.55
12.75

1,38
1,4

ABSF
ABSD
NEGF
NEGD

43
51
42
50

13.65
16.05
13.35
15.75

37
37
1,37
1,37

LDFPS
LDEXP
LDCIF
LDCID
LDCLF
LDCLD

11
38
60
55
60
55

4.05
12.75
18.75
17.25
18.75
17.25

1,2,3,37
6,8
6,8
6,7,8,9
6,7,8,9

STFPS
STST
STEXP
STCFI
STCDI
STCFL
STCDL

16
17
34
58
59
55
56

5.55
5.85
10.95
18.15
18.45
17.25
17.55

CFCC

12
14
14
14
14

4.35
4.95
4.95
4.95
4.95

Instruction

SEW
SEID
SETI
SETL

Notes

Modes 1 thru 7
Use Table 3

Use Both Tables
2 and 3

Use Table 4

Use Table 5
1,2
11,12,39
11,12,39
10,11,13,40
10,11,13,40
No Operands

~DmDDmD
COMPONENTS

GROUP
10E3

)lnote

NUMBER 048
PAGE 7 OF 10

TABLE 2

Addressing
Mode

Microclc1es*
Single
Double
Presision Precision

1
2
2 Innnediate
3
4
5
6
7

6,8,11
7,9,11
6,8,11
7,9,11
7,9,11
8,10,13
8,10,13
10,12,15

*Note:

8,10,13
9,11,14
2,4,7
9,11,14
9,11,14
10,12,15
10,12,15
12,14,17

Read/Write
Memory ~cles
Single -uEle
2/0
2/0
1/0
3/0
2/0
3/0
3/0
4/0

4/0
4/0
1/0
5/0
4/0
5/0
5/0
6/0

Time (us. )
Double
Single
Precision Precision
4.81
5.11
4.05
5.86
5.11
6.16
6.16
7.52

6.92
7.22
2.85
7.97
7.22
8.27
8.27
9.63

The three numbers (of microcycles) in each set represent three different
conditions:
1.
2.
3.

if the floating point number is positive
if the floating point number is negative and non-zero
if the floating point number is a negative zero with FIUV flag clear

TABLE 3

Addressing
Mode
1
2
2 Innnediate
3

4
5
6
'7

Microcyc1es
Slngle
DouEle
Precision Precision
3
6
-2
4
6
5
5
7

5
8
-6
6
8
7
7
9

Read/Write
Memory ~cles
Single -uble
0/2
0/2
0/1
1/2
0/2
1/2
1/2
2/2

~D~DDmD
COMPONENTS
GROUP
107

0/4
0/4
0/1
1/4
0/4
1/4
1/4
2/4

Time (us.)
Single
Double
Precision Precision
2.56
3.46
0.23
3.61
3.46
3.91
3.91
5.27

4.82
5.72
-0.97
5.87
5.72
6.17
6.17
7.53

NUMBER 048
PAGE 8 OF 10

)Jnote
TAB.LE 4
-Addressing
Mode
1
2
2 Irranediate
3
4
5
6
7

Microcycles
Short
Long
Integer Integer
2
3
1
3
3
4
4
6

4
5
1
5
5
6
6
8

Read/Write
Memory Cycles
Short
Long

Time (us. )
Short
Long
Integer Integer

1/0
1/0
1/0
2/0
1/0
2/0
2/0
3/0

1.35
1.65
1.05
2.41
1.65
2.71
2.71
4.06

2/0
2/0
1/0
3/0
2/0
3/0
3/0
4/0

2.71
3.01
1.05
3.76
3.01
4.06
4.06
5.42

TABLE 5
-Addressing
Mode
1
2
2 Irranediate
3
4
5
6
7

Microcycles
Short
Long
Integer Integer
2
3
1
3
3
4
4
6

4
5
1
5
5
6
6
8

Read/Write
Memory Cycles
Short
Long

Time (us. )
Long
Short
Integer Integer

0/1
0/1
0/1
1/1
. 0/1
1/1
1/1
2/1

1.43
1.73
1.13
2.48
1.73
2.78
2.78
4.13

0/2
0/2
0/1
1/2
0/2
1/2
1/2
2/2

m'TES

Add 300 ns. if result is positive.
Add 300 ns. if result is non-zero.
Add 900 ns. if SRC> 177 or SRC.c.: -177.
Add 900 ns. if floating point number := O.
5. Add 3.3 us. if overflow on rounding.
6. Add 300 ns. if integer is negative.
7 . Add 1.5 us. if absolute value of integer' 65,536.

1.
2.
3.
4.

~DI~DDmD
COMPONENTS
Ci~tOUP

11D8

2.86
3.16
1.13
3.91
3.16
4.21
4.21
5.57

)Jnote
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.

NUMBER 048
PAGE 9 OF 10

Add 1.2 us. n times where n = 220 - expn.
Add 1.2 us. n times where n = 240 - expn and if absolute value of integer
"'7 = 65,536.
Add 600 ns. if expn4 20.
Add 2.1 us. n times where n is the smaller of the two absolute values:
(210 - expn) or (230 - expn).
Add 600 ns. if integer is negative.
Add 900 ns. if integer is negative.
Add 1.2 us. if floating point numbers are equal.
Add 2.1 us. if ntmlbers are lll1equal but the signs are the same.
Add 600 ns. if FPACC > FPSRC.
Add 2.4 us. if FPSRC ~ FPACC.
Add 600 ns. if adding opposite signs or subtracting like signs.
Add 2.4 us. if trapped on lll1defined variable.
Add 900 ns. and 1.2 us. n'times where n = expn difference.
Add 3.6 us. if FPSRC> FPACC.
Add 1.2 us. if adding opposite signs or subtracting like signs.
Add 1.2 us. if trapped on undefined variable.
Add 900 ns. and 1.8 us. n times where n = expn difference.
Add 1.2 us. n times ehere n = shifts to normalize.
Add 1.8 us. n times where n = shifts to normalize.
Add 3.3 us. if lll1derflow.
Add 600 ns. if overflow.
Sff 600 ns. if need to normalize after multiply or divide.
Add 1.2 us. if need to normalize after multiply or divide.
Add 600 ns. for every "1" bit in multiplier (FPSRC).
Add 1.2 us. for every "1" bit in multiplier (FPSRC).
Add 900 ns. times n where n = expn mod 16 (calc integer and fraction).
Add 300, 600, or 900 ns. if expn = 21-40, 41-60 or ~ 100, or 61-100 respectively.
Add 1.8 us. if the fractional part = O.
Add 1.2 us. if the fractional part = O.
Add 4.5 us. if trapped on any of the FP11 interrupts.
Add 5.4 us. if trapped on overflow.
Add 24.3 us. if trapped on conversion error.
Add 24.9 us. if trapped on conversion error.
Add 1.2 us. if rOlll1ding.
Add 1.8 us. if rOlll1ding.
Add 8.1 us. if trapped on overflow.
Add 9.0 us. if trapped on underflow.

~DmDDmD
COMPOMENTS
GROUP
109

NUMBER 048
PAGE 10 OF 10

)Jnote
3.0 - - IMA lATENCY

IMA (Direct Memory Access) latency, which is the time from request (BIJ.1RL) to bus
mastership for the first DMA device, is:

lMA lATENCY

MSV11-C
MSV11-D
MSV11-E

4.15 us., worst case
~;. 49 us., worst case
~;. 53 us., worst case

Worst Case Time =-Longest DATIO C~cle + Refresh Time
A 300 ns. microcycle time is assumed.
4.0 -- INTERRUPT lATENCY
Interrupt latency is the sum of the time from request (BIRQL) to aclmowledgement
(BIAKL) and the time from aclmowledge to fetch of the first service routine
instruction.
BIRQL
10 BIAKL

BIAKL
10 FETCH

lOTAL
WORST CASE

Standard PDP-II
Instruction Set

MSV11-C
MSV11-D
MSV11-E

12.11 us.
10.79 us.
11.07 us.

9.41 us.
8.18 us.
8.26 us.

21.52 us.
18.97 us.
19.33 us.

EIS

MSV11-C
MSV11-D
MSV11-E

56.28 us.
55.65 us.
55.81 us.

9.41 us.
8.18 us.
8.26 us.

65.69 us.
63.83 us.
64.07 us.

FPl1
(KEF Option)

MSV11-C
MSV11-D
MSV11-E

N/A
N/A

47.72 us.

8.26 us.

55.98 us.

For all floating point instructions except ADD, SUB, MUL, DIV and MOD, the interrupt
latency is the length of the instruction. Unlike the KD11 processors, the EIS
instructions are not interruptable. In the floating point arithmetic instructions,
interrupts may be serviced while in the midst of their execution. If an interrupt
is to be serviced before execution is complete, the instruction is aborted and all
the PDP-II general registers and floating I)oint registers are restored to their
original values. After the interrupt is serviced, the floating point instruction
is restarted from scratch. This interrupt restore routine takes 6.9 us. and the
time must be added to the interrupt latency times where execution of an instruction
is aborted.

~DmlmDmD
COMPC»IENTS
GRC)uP
110

NUMBER

)lnote
TITLE

049
DATE

Srstem Differences - LSI-II vs. LSI-11/23

DIS'IRIBUTION
ORIGINATOR

12/ 22

PRODUCT

KDF11-A,
KD11-F, KD11-HA

Unrestricted
Ted SemEle &Doug Swartz

PAGE 1 OF 2

Here is a list of system differences between a KDF11-A and KD11-F. It is intended
to point out all possible problems that may arise if a KD11-F is literally removed
fram a backplane and a KDF11-A substituted.
1.

KDF11-A HAS NO BOOT LOADER IN MICROCODE -- KD11-F has "L" conunand. Those
users who are down l~ne load~ng to KDFI1-A's will have to change their host
software to enter the bootstrap loader via micro ODT, which is 14 memory
words. KDF11-A users whose memory size varies will have to self-size the
system via micro ODT or enter a quick PDP-II program to do the same thing.
The LSI-II's boot loader automatically sizes memory.
Those users still using paper tape and thus invoking the LSI-II boot from
a terminal will have to enter the 14-word PDP-II boot by hand from the
terminal.

KDF11-A WILL NOT PERFORM MEMORY REFRESH KD11-F OOES -- The dual LSI-II
board CKDll-HA) does not perform refresh either, but nevertheless, there
will be some users who pullout a KD11-F, insert a KDF11-A, and then must
do something else to keep memory refreshed such as change
over to the newer memories (e.g., MSV11-C, MSV11-D) that perform refresh
locally.

EVENT LINE IS ON LEVEL 6 IN KDF11-A , ON LEVEL 4 IN KD11- F - - With the
KDFII-A having the optional capabil~ty to support 4 interrupt levels, the
real time clock on normal PDP-II systems is attached to Level 6. In the
KD11-F, it is attached to Level 4. Users who have written software and
have locked out the event line by setting the priority level to 4 will
still see the event line interrupt with the KDF11-A. Users will have to
set the priority level to 6 or above to lock out the event line.
DEC software is unaffected since it takes advantage of the fact in the
KD11-F that the other 2 bits of the priority level are mechanized (read/write)
but do not do anything. In many cases, users do not lock out the clock at
all because they do not want to miss a tick, and if they have, the change is
trivial and should be only in a small number of places in their code.

~D~DD~D
COMPONENTS

GROUP
111

).Inote

NUMBER 049
PAGE 2 OF 2

KDFII-A OOES NOT BRING FOUR EXTRA MICROCODE BITS 'ID MOOOLE CONNEC'IDR AS
KDII-F DOES -- The KDFII-A does not have 4 microcode bits like the KDII-F
has. Users who are sensing these 4 bits for one reason or another
(e.g., bus initialize, bus error, etc.) will have to make a change in
their system.

The KDFII-A pulses SRUN (API, AHl) eluring ODT each time a character is
transmitted. The KDII-F and KDII-HPl modules do not pulse SRUN during
ODT. All three modules do pulse the SRUN line each time an instruction
is fetched. Those users who use SRl~ for other than driving the RUN
lamp should be aware that they will get additional pulses.

The KDFII-A supports I8-bit addressing, whereas the KDII-F and KDll-HA.
modules only support I6-bit addressjng. When the KDFII-A has the MMU
enabled, all modules on the bus must be capable of responding to 18-bit
addressing. Memory modules must decode all 18 bits. Modules with IMA.
capability must address 18 bits instead of only 16 bits. I/O interfaces
that use BBS7 instead of decoding address bits 13 and above will work
with either 16- or 18-bit addressing.

There are some differences in instru.ction execution between the KDll' s
and the KDFII-A. See Micro Note #OS3 for details.

~D~I~DmD
COMPC»NENTS
CiRC)UP
112

NUMBER

J.lnote
TITLE

050

DATE

Micro ODT Differences - LSI-II vs. LSI-11/23

DIS1RIBUTION
ORIGINATOR

12 /

/ 78

PRODUCT

ImF11-A,
Im11-F, Im11-HA

Unrestricted
Ted Semple

PAGE 1

OF 3

The attached micro ODT difference list shows that there are some changes in
ODT between the KD11 CPU's and the ImF11-A CPU. Most notably, the ImF11-A
does not support the "L" connnand.
In most cases, those using ODT from a console terminal will not be affected.
HOwever, the slight differences in response to some connnands may impact users
that have programmed a host computer to emulate a console terminal for the
purpose of down line loading (DLL) programs to the LSI-II.

~D~DD~D
COMPONENTS

GROUP
113

MICRO ODT DIFFERENCES:

LSI-II vs. LSI-11/23

KDII-F &KDll-HA

KDFII-A

1. All characters that are input are echoed except
when in the APT corrnnand mode where no characters
are echoed. An echoed line feed (LF) will be
followed by a carriage return eCR) only (no second
"LF" or padding nulls). This method creates a
potential timing problem with a TTY ASR33 which
types the next character before the print head has
completely returned.

All characters that are input in any corrnnand mode except
the APT mode are echoed except the octal codes 0, 2, 10,
12, 200, 202, 210 and 212. This suppresses echoing LF's
(and nulls (0), STX's (2), BS's (10)) because an automa tic (CR) mld (LF) follow. In the APT corrnnand mode, no
input characters are echoed.

An address location must be explicitly closed by a (CR)
or (LF) corrnnand before another is opened or else an
error (?) will occur and any open location will automatically be closed without altering its contents .

When an address location is open, another location
can be opened without explicitly closing the first
location; e.g., 1000/123456 2000/054321.

....L

~ 3.

~ !! 'vlill open the previous location.

..!..,., ___ "1
"r,t."
.. I .. is .1..ll.~gGll.

___ ..l

.. .. I""T'VT'

GL.lIU UVIJl

____ .! __ A-_
f)l.l.lll.~

· · r ..
"n"
, l U\.) ,
r~"\

rT ,-,"\

lLJ:' ) ,

"~,,

I::

"@" will open a location using indirect addressing.

"@" is illegal and uODT prints "?" , (CR) , (LF) , "@"

"~,, will

"?" is illegal and uODT prints "?" , (CR) , (LF) , "@"

"M" will print the contents of an internal CPU register.

"M" is illegal and uODT prints "?" , (CR) , (LF) , "@"

Rubout (ASCII 177) will delete the last character
typed in.

Rubout is illegal and uODT prints "?", (CR), (LF),

"L" is the boot loader corrnnand which will load the
absolute loader.

"L" is illegal and uODT prints "?", (CR), (LF), "@"

Control-Shift-S corrnnand mode (ASCII 23) accepts 2
bytes forming a 16-bit address and dumps 10 bytes in
binary format. The 2 input bytes are not echoed.

Control-Shift-S command mode (ASCII 23) accepts 2 bytes
forming an 18-bit address with bits (17:16) always
zeroes and dumps 10 bytes in binary format. The 2
input bytes are not echoed.

open a location using relative addressing.

"@"

KD11-F &KD11-HA (cont.)
10.

KDF11-A (cont.)

Up to a 16-bit address and 16-bit data may be entered.

Up to an 18-bit address and 18-bit data may be entered.

Leading zeroes are assigned.

Leading zeroes are assumed.

11.

Incrementing (LF), the address 177776 results in
the address 000000.

Incrementing (LF), the addresses 177776, 377776, 577776
and 777776 result in the addresses 000000, 200000, 400000
and 600000 respectively; i.e., the upper 2 bits of the
18-bit address are not affected. They must be explicitly
set.

12.

Incrementing a PDP-II register from R7 prints out
''R8'' and the contents of RO.

Incrementing a PDP-II register from R7 prints out "RO"
and the contents of RO.

13.

The lie page is in the address group 17XXXX.

The I/O page is in the address group 77XXXX where
address bits (17:12) must be explicit ones.

14.

The micro ODT mode can be entered from the following
sources:

a) A PDP-II HALT instruction.
b)
c)
d)
e)

a) A PDP-II HALT instruction when in kernel mode; the
POKL line is low and the HALT jtnnper option strap
is present.
b) An asserted HALT line.
c) A power up option.
d) An asserted HALT line caused by a DLV11 framing error.
e) A micro ODT bus error.

15.

A carriage return (CR) is echoed and followed by just
a line feed (LF).

A carriage (CR) return is echoed and followed by another
(CR) and line feed (LF).

16.

1'b' 'If' command.

The F-11 chip set has a feature which is not implemented
on the KDF11-A. "H" causes the chip set to output a
signal that can be used to toggle the HALT F/F to allow
single-step program execution. "H" causes the KDF11-A
to execute a microcode routine that, in effect, does
nothing.

.....
.....

C1I

A double bus error.
An asserted HALT line.
A power up option.
An asserted HALT line caused by a DLV11 framing
error.
f) A micro ODT bus error.
g) A memory refresh bus error.
h) An interrupt vector time out.
i) A non-existent micro PC address.

NUMBER

)lnote

051
DATE

TITLE Digital Supported PROMs
DIS1RIBUTION
ORIGINATOR

22 / 78
PRODUCT MRV11-M
MRVl1-B, MRV1l-C
MXV11-A PBII
12/

Unrestricted
Ted SemEle

PAGE I

OF 1

The following PROMs are supported by Digital to the extent shown below:
W PRCMs

Size

Intel 2758
Intel 2708
Intel 2716
Intel 2732
Mostek MK2716
T.I. 1MS 2516
T.1. 1MS 2532

8K
8K
16K
32K
16K
16K
32K

BiEloar PROMs

Size

Intel 3628
Signetics 82S 129
Signetics 82S 131
Signetics 82S 2708
Signetics 82S 181
Signetics 82S 191

8K
1K
2K
8K
8K
16K

MRVII-B

MRV11-C

MXV11-A

X
X
X
X
X

MRV11-C

MXV11-A

MRV11-M
X
X

PB11
X
X

X
X
X

PB11
X

X
X

X
X
X

X
X

This is not an exhausting list of possible ReM chips. It does represent the
chips that have been tested by Digital except for the 32K parts which will be
supported when available from the vendors.
The 1758 UV PROM is supported but is not recommended for new designs because
continued availability is not guaranteed .

~D~~DD~D
COMPONENTS
G~lOUP

1"16

NUMBER

)./note

052
DATE

TITLE

12/ 27

Parity Memory in LSI-ll/23 Systems

DIS1RIBUTION
ORIGINATOR

/ 78

PRODUCT

Unrestricted

lG)FII-A

Ted SemEle

MSVII-E

PAGE 1 OF 8

r------------- -l
1

lG)FII-A
CPU

MSVII-E
PARITY
RAM

CUS'I'CM
PARITY
CONTROLLER

LSI-II BUS
FIGURE 1 -- A CUSTOM PARITY CONTROLLER ALLOWS 1HE MSVII-E
PARITY FFAWRE TO BE USED WIlli 1HE lG)Fll-A
Both the lG)FII-A CPU module and the MSVII-E parity memory module have provision
to support parity of memory data. However, the parity feature cannot be used
unless a parity controller is available. Currently, DIGITAL does not have a
parity ,control module. A customer desiring parity in a LSI-ll/23 system must
fabricate his own custom parity control module.
This Micro Note explains the parity features of the lG)FII-A and MSVII-E modules.
implementing a parity controller is described.

An approach for

~D~DDmD
COMPONENTS

GROUP
117

NUMBER 052
PAGE 2 OF 8

KDF11-A PARITY MECHANISM
A simple parity trap mechanism is implemented on the module. During every
processor-initiated DATI or the DATI portion of a DATIO(B) cycle, the processor
will sample the state of bus signals BDAL16L and BDAL17L after the 200 ns.
REPLY deskew time. BDAL16L and BDAL17L (which are address bits 16 and 17,
respectively, during the beginning of a bus cycle) are treated the same way
as BDAL (15:0) at REPLY time. BDAL16L at REPLY time is interpreted as a
parity error signal from memory while B~~17L at REPLY time is interpreted as
a parity error enable signal from an exte~rnal parity controller module. If
BDAL17L is not asserted at REPLY time, no abort will occur and program execution
will continue. If BDAL17L and BDAL16L are both asserted at REPLY time, a trap
to location 1148 will occur.
The above capability allows the processor to recognize memory parity errors and
trap to the same PDP-II compatible location. Unlike PDP-II parity controllers
which have a Control and Status register that captures the high order seven
address bits of the offending location, the KDF11-A will have no information
available to the progrannner. This information can be captured by extenlal bus
logic described below.
MSV11-E PARITY LOGIC
MSV11-E parity logic functions are shown in Figure 2. The basic functions
include a parity generator for memory write data, a 2-bit memory array, a parity
detector, and a latch circuit. The pari~{ generator produces two parity bits,
one for each main memory byte. Address and control signal (not shown) lines are
identical to those applied to the main manory array. When any main memory
location is read, the corresponding pari~{ memory location is read. Parity bits
are checked by the parity detector and the result is stored in the output latch.
If a parity error is detected (PAR ERROR IND H is active), PAR ERR H is gated
onto the BDAL16L bus line. The processor reads the error during the memory read
(DATI) cycle and responds accordingly.
Parity logic functions are tested when rU1ning memory diagnostics by writing
incorrect parity bits. The custom parity control module forces this condition
during a DA1D(B) cycle by asserting BDAL16L during the output data transfer
portion of the bus cycle. BDAL16L is received, inverted to produce ''write wrong
parity" (WWPA16H), and applied to the parity generator, forcing it to store
incorrect parity bits. The error is then detected by subsequent memory read
cycles.

~D~DlomD
COMPOI~ENTS

GROUP
11E~

).Inote

r-.,

I
I
I

r---,

WRITE DATA

NUMBER 052
PAGE 3 OF 8

I READ DATA..
MEMORY ARRAY I

L _ _ ...J

DATA
LATCH

I LAT<DOO:15> H

L_...I
PARITY
I-DETECTOR

r;ioSUS'
1
1
1'"/ 1
XCVR

BDAL16 L

I\. DAL<OO:07> H

WWPA16H

PDO 16H

PDI16 H

PARITY
GENERATOR

DAL<08:15> H

PDI 17 H

L_...J

2·BIT
MEMORY
ARRAY
(4K,8K,
16K, OR
32KI

PDO 17H

MUX <A1:A7> H

PARITY ERROR IND H

,..--.

r;/~~----'
LATCH

PAR ERR H

SYNC L

RPLY L

DATA LAT L

DIN L

L.. _ _

FIGURE 2 -- MSVII-E PARITY LOGIC

mD~DDmD
COMPONENTS
CiROUP
119

BDAl16 L

).Inote

NUMBER 052
PAGE 4 OF 8

CUSTrn PARITI CON1ROL MODULE
To achieve PDP-II software system compatibility and to properly interface with
the KDF11-A and the MSV11-E modules, the parity controller must:
1)

Have a compatible CSR (Control and Status Register). In addition to parity
control functions, the CSR contains the partial address of the memory
location with a parity error.

Have provision to control BDAL17 , the parity enable signal.

Have provision to control BDAL16.
parity for diagnostic purposes.

BDAL16 forces the MSV11-E to write wrong

CON1ROL AND STAnIS REGISTER (CSR)
The CSR can be thought of as one 16-bit register which has its own location
address. The contents of the CSR can be~ either read (DATI) or changed (DATO)
by the processor. The CSR contents are also changed when a
parity error has occurred. The CSR bit assignments are illustrated in Figure 3
and are described as follows:
1)

Bits 1, 3, 4, 12, 13 and 14 are not used.
are always read as a DATA O.

Bit 0 (Parity Error) -- If this bit is set (DATAl), the parity
controller will assert BDAL17L during the data portion of a DATI or DATIO
bus cycle. If this bit is not set (DATAO), the CPU will not trap to 114
on parity errors. The state of bit 0 can be changed by the processor by a
DATO data transfer to the CSR. LSI-II signal BINIT clears this bit.

Bit 2 (Write-Wrong Parity) -- If this bit is set (DATAl), the parity
controller will assert BDAL16L to force the MS\T11-E to generate even
(incorrect) parity based on data transferred into memory (DATO/DATOB). A
parity error is then caused on a rea.d (DATI) cycle of this data. The
state of bit 2 can be changed by the processor by DATO data transfer to
the CSR. LSI-II bus signal BINIT clears this bit.

Bits 5-11 (Error Address) -- Once a parity error has occurred, these bits
contain the seven highest order address bits (A17-A11) of the faulty data
which caused the parity error. The stored address bits describe the location
of faulty data to wi thin 1K of memory. Therefore, the memory module
involved in the parity' error can be located by using the partial address
contained in bits 5-11. The software operating system has the ability to
lock out (prevent the access of) a lK block of memory that is specified
by a programmer.

They contain no data.

~D~~DDmD
~ONENTS

GROUP
1120

These bits

NUMBER 052
PAGE 5 OF 8

Bit 15 (Parity Error Bit) -- This bit is set (DATAl) by the parity
controller when a parity error occurs. Bit 15 is a flag, but it does not
cause a parity error trap in the processor. LSI-II bus signal BINIT
clears this bit.

STATUS REGISTER BITS

~-------,,---------ERROR
ADDRESS

NOT
USED

WRITE
WRONG
PARITY

ERROR
IND.
ENABLE

FIGURE 3 - - CONTROL AND STATIJS REGISTER BIT ALLOCATION
The address of the CSR is determined in the parity controller circuitry;
the address bits are shown in Figure 4. The address of the CSR is strapped
within the range 772100 - 772136.
Address bit AOO is not decoded by the address select logic.
(A04-AOl) are determined by wired jumpers.

A17 A16 A16 A14 A13

A12

A11 Al0 A09 A08

'11111111,1,10
I

I
I

I
7

1 0

A07
1

A06 A05
1

A04

FIGURE 4 - - CSR ADDRESS BITS

~D~DDmD
COMPONENTS

GROUP
121

A03 A02 A01

AOO

1x I x I xl x 1

Address bits

NUMBER 052

).Inote
WWP H

PAGE 6 OF

<t--~-

OUTLB L

OOUT H
DAL16 H

PAR ERR

EN H
D

....:I

DAL17 H

DC005

! DO

(4)

D (0:15)

Q3,14
~

Dl,3,4,12,

D (11:15)

D (5:11)

""'-----L-..l

XMIT

INWD L

INWD L
ADDRESS
lATCH

SELO L

::c:

DC004

OUTLB L

ffi

~
t-----------....--- OOUT H
I - - - - t - - - - - - - - - -...~- DIN H

t---+--+--------,--~
..... SYNC
I------.l~.....

8640
(5)

BSYNC L
BDIN L
BOOUT L
BRPLY L
BINIT L

FIGURE 5 --

CUSTOM PARITY CONTROL LOGIC

RPLY H

-----[::»--- INIT L
l'-K)TE:

~D~DDmD
COMPONENTS
GROUP
122

This approach has been reviewed
by LSI-II technical personnel.
However, the approach has not
been tested.

).Inote

NUMBER 052
PAGE 7 OF 8

CUSTOM PARITI CONIROL LOGIC
Figure 5 is a diagram of the logic required for the custom parity control module.
This diagram is not intended to be the actual schematic for the parity controller
but does show an approach that may be used. This approach has been thoroughly
reviewed by LSI-II technical personnel; however, the approach has not been tested.
The diagram breaks down into three distinct portions: the LSI-II bus interface
on the left, the parity error latch in the upper right-hand quadrant, and the
address latch in the middle of the right-hand side. There is no block on the
diagram that is called the Control and Status Register. In effect, the CSR is
all of the logic on the diagram except for the bus interface logic.
The bus interface is fabricated out of integrated circuits available from
DIGITAL. Except for some miscellaneous drivers and receivers (8881's ruld 8460's,
respectively), all of the interface chips are available as part of the DCK11
Chipkit.
Only five of the six chips in the Chipkit are used. The DC003 interrupt protocol
chip is not necessary for this application. Details on the bus interface can be
found in Chipkit documentation. Outputs from the Chipkit interface include
control signals and the Tri-State data bus D(0:15).
The parity error latch consists of a flip-flop and a pair of gates used to
control the clock to the flip-flop. The flip-flop is set whenever the memory
detects a parity error during a DATI bus cycle. If BDAL16 is asserted when the
reply signal is asserted, the latch is set. The latch is cleared the first time
the Control ruld Status Register is read by the processor. This flip-flop is
bit 15 of the CSR.
The address latch is shown as a single block on this diagram. In reality, it is
7 flip-flops with Tri-State buffers on their outputs leading back to the data
bus (this function may be perfonned by MSI chips similar to 74173's). On the
leading edge of each BSYNC, the latch is clocked to save address bits 11-17.
The clock is inhibited when a parity error occurs so that the upper address bits
of the memory location where the parity error occurred are saved. The outputs
of the address latch are CSR bits 5-11. These 7 bits may be used by the parity
error service routine to detennine which 1K block of memory the error occurred in.
The 2 flip-flops shown in the upper center of the diagram are used to implement
CSR bits 0 and 2 (parity error enable and write-wrong parity, respectively). The
lower flip-flop of the two is the parity error enable flip-flop and is set whenever
the processor writes a 1 into bit 0 of the CSR. When parity error enable is set,
BDAL17 is asserted whenever BDIN is asserted. This enables the processor to
respond to parity errors. The write-wrong parity flip-flop (the upper flip-flop
of the two) is set by writing a 1 into bit 2 of the CSR. When the write-wrong
parity flip-flop is set, BDAL16 is asserted during the DOUT portion of the bus
cycle. This forces the parity memory to store the wrong parity for diagnostic
purposes.

~DmDD~D
COMPONENTS

GROUP
123

)./note

NUMBER 052
PAGE 8 OF 8

Only one custom parity control module is necessary for all of the memory addressable by the KDF11-A processor.
SOF1WARE SUPPORT
When BDAL16 and BDAL17 are asserted during the data portion of a DATI cycle, the
processor will recognize this as a parity error and trap to address location 114.
The progrannner must have provisions for responding to this trap. The service
routine mlst read the Control and Status Register to find the address of that
portion of memory where the parity error occurred and also to re-enable the
parity error circuitry. The progrannner must decide what course of action is to
be followed when a parity error occurs.
RT-l1 and RSX-11M have provision to support parity error traps.

~D~mID~D
COMPONENTS

GROUP
124

NUMBER

)lnote

053

DATE

TITLE

PDP-11 Family Differences

DIS1RIBUTION
ORIGINATOR

12/ 27 /78
PRODUCT

Unrestricted

KD11, KDF11-A

Ted Sem2le

PAGE 1 OF 11

The attached PDP-11 Family Differences table will help users migrate
their software between different members of the PDP-11 Family. Each
member of the Family has some slight differences in the manner
instructions are executed. Any program developed using PDP-11 operating
systems with higher level languages will migrate with very little
difficulty. HOwever, some applications written in assembly language
may have to be modified slightly. This table will help users determine
where potential problems may occur.

~D~DD~D
COMPONENTS
c:~p

125

ACTIVITI

11
1.

PDP-II

LSI-

11/23

05/10 15/20

OPR%R, (R)+ or OPR%R, -(R) using the same register as
both source and destination: contents of R are incremented (decremented) by 2 before being used as the
source operand.

------------------------------------------------------------- ------- ----- -------

OPR%R, (R)+ or OPR%R, -(R) using the same register as
both register and destination: initial contents of R
are used as the source operand.
2.

OPR%R, @(R)+ or OPR%R, @-(R) using the same register as
both source and destination: contents of R are incremented (decremented) by 2 before being used as the
source operand.

35/40

I 45

---------------------~-----

---------------------------------------------------------------------------------------------------------t------

OPR%R, @(R)+ or OPR%R, @-(R) using the same register as
both source and destination: initial contents-of Rare
used as the source operand.
3.

OPR PC, X(R); OPR PC, @X(R); OPR PC, @A; OPR PC, A:
location A will contain the PC of OPR +4.

----------------------------------------------------------------------------------- ---------------------r-----

OPR PC, X(R); OPR PC, @X(R), OPR PC, A; OPR PC, @A:
location A will contain the PC of OPR +2.
4.

~W (R)+ or JSR reg, (R)+:
contents of R are incremented by 2, then used as the new PC address.

--------------------------------------------------------------------------- -----------------------------------

(R)+ or JSR reg, (R)+:
used as the new PC.

initial contents of Rare

%R or JSR reg, %R traps to 4 (illegal instruction).

--------------------------------------------------------------------------- -----------------------------------

%R or JSR reg, %R traps to 10 (illegal instruction).

11
6.

SWAB does not change v.
SWAB clears V.

PDP-I1

LSI-

ACTIVI'IY

11/23

05/10 15/20

35/40

---- ------- ----- ------- ------ f------ f-------- ----X

---- ------- --- -- ------- ------ ----- ------- -- ---

Register addresses (177700 - 177717) time out when used
as a program address by the CPU. Can be addressed under
console operation. NOte addresses cannot be addressed
under console for LSI-II or LSI-l1/23.
8.

Basic instructions noted in PDP-II Processor Handbook.

---- ------- ----- ------- ------ ----- ------- -----

SOB, MARK, RTf, SXT ins truc tions •
ASH, ASHC, DIV, MUL.
XOR ins truction.

X
X
X
X
X
X
---- ------- -- --- ------- ------ ----- ------- ----X
X
X
X
X
---- ------- ----- ------- ------ ----- ------- ----X
X
X
X
X

The external option KE11-A provides MUL, DIV and SHIFT
opera tion in the same data fonna t.

--------------------------------------------------------- ---- -------

The KEII-E (Expansion Instruction Set) provides the
instructions MUL, DIV, ASH, and ASHC. These new
instructions are 11/45 compatible.

The KEII-F adds unique stack ordered floating point
instructions: FADD, FSUB, FMUL, FDIV.

-----~-------

------ ----- ------- ----X

--------------------------------------------------------- ---- ------- ----- ------- ------ ----- ------_. -----

The KEVl1 adds EIS/FIS instructions.
SPL instruction.

ACTIVI1Y

LSI-

11
9.

11/23

PDP-II
04

05/10

15/20

Power fail during RESET instruction is not recognized
until after the instruction is finished (70 milliseconds). RESET instruction consists of 70 millisecond pause with INIT occurring during first 20
milliseconds.

35/40

-------------------------------------------------------- ---- ------- ----_._------ ---------------------------

Power fail immediately ends the RESET instruction and
traps if an INIT is in progress. A minimum INIT of 1
microsecond occurs if ins truction aborted.

--------------------------------------------------------------------_._---- ------_._--------------------------

Power fail acts the same as 11/45 (22 milliseconds with
about 300 nanoseconds minimum). Power fail during RESET
fetch is fatal with no power down sequence.

--------------------------------------------------------------------- ----- -----------------------------------

RESET instruction consists of 10 microseconds of INIT
follOTn'ed by a 90 Iuicrosecond pause. Power fail not
recognized until the instruction is complete.
10.

No RTT instruction.

------------------------------------------------------------- ------- ----_.------- ------ --------------------

If RTT sets the T bit, the T bit trap occurs after the
instruction following RTT.
11.

If RTI sets "1'" bit, "T" bit trap is aclmowledged after
instruction following RTI.

------------------------------------------------------------_._------------ -------------_._-------------------

12.

If RTI sets "T" bit, "T" bit trap is aclmowledged
immediately following RTI.

If an interrupt occurs during an instruction that has
the "T" bit set, the "T" bit trap is aclmowledged before
the interrupt.

-------------------------------------------------------- ---- ------- ----- ------- ------ ----- -------------If an interrupt occurs during an instruction and the
"T" bit is set, the interrupt is aclmowledged before
"T" bit trap.

ACTIV11Y
11
13.

PDP-II

LS1-

"T" bit trap will sequence out of WAIT instruction.

11/23

05/10 15/20

35/40

----------------------------------------------------------------------~----------------------------------

"T" bit trap will not sequence out of WAIT instruction.
Waits until an interrupt.
14.

Explicit reference (direct access) to PS can load "T"
bit. Console can also load "T" bit.

----X

----------------------------------------------------------------------~--------------------------~-------r-----

15.

Only implicit references (RTI, RTT, traps and interrupts)
can load "T" bit. Console cannot load "T" bit.

Odd address/non-esixtent references using the SP cause
a HALT. This is a case of double bus error with the
second error occurring in the trap servicing the first
error. Odd address trap not in LSI-II or LSI-11/23.

---------------------------------------------------------~----~-------~--------------------~-----~-------~-----

Odd address/non-existent references using the stack
pointer cause a fatal trap. On bus error in trap
service, new stack created at 0/2.
16.

The first instruction in an interrupt routine will not
be executed if another interrupt occurs at a higher
priority level than assumed by the first interrupt.

---------------------------------------------------------~-----------------

The first instruction in an interrupt service is
guaranteed to be executed.
17.

8 general purpose registers.

---------------~-----~-------~-----

-------------------------------------------------------------------------------------------------~-------------

16 general purpose registers
18.

PSW address, 177776, not implemented must use new
instructions, ~ITPS (move to PS) and ~WPS (move from PS).

--------------------------------------------------------------~-------~--------------------

----- ------- -----

ACTIVI1Y

LSI11

11/23

PDP-11
04

PSW address implemented, MTPS and MFPS not implemented.

05/10 15/20

35/40

--------------------------------------------------------------r---------------------~------~-----r-------

PSW address and MTPS and MFPS implemented.
19.

Only one interrupt level (BR4) exists.

Stack overflow not implemented.

-----

---------------------------------------------------------r---- -------~-------------~------------

Four interrupt levels exist.
20.

--------------------------------------------------------- ---- ----------- ------- ----Stack overflow below 400 implemented.
X
X
X
X
X
---------------------------------------------------------r---- ------- ------------- ----------~--------------

Red and yellow zone stack overflow implemented.
21.

Odd address trap not implemented.

---------------------------------------------------------r----r------------------------------------------ -----

Odd address trap implemented.
22.

FMUL and FDIV instructions implicitly use R6 (one push
and pop); hence, R6 must be set up correctly.

--------------------------------------------------------------~-------r-----r-------

Due to their execution time, EIS instructions can abort
because of a device interrupt.

------r----- -------

---------------------------------------------------------~------------r-------------r------------

Due to their execution time, FIS instructions can abort
because of a device interrupt.

EIS instructions do not abort because of a device
interrupt.
24.

FMUL and FDIV instructions do not implicitly use R6.
23.

------- ----X

ACTIV1TI

11
25.

EIS instructions do a DATIP and DATO bus sequence when
fetching source operand.

PDP-II

181-

11/23

05/10 15/20

35/40

------------------------------------------------------------- ------- ----- -----------------------------~-----

EIS instructions do a DATI bus sequence when fetching
source operand.
26.

MJV instruction does just a DAm bus sequence for the

last memory cycle.

------------------------------------------------------------- ------------- ------- ---------------------------

instruction does a DATIP and DATO bus sequence for
the last memory cycle.

27.

If PC contains non-existent memory address and a bus
error occurs, PC will have been incremented.

------------------------------------------------------------- -------------------------------------------1------

If PC contains non-existent memory address and bus error
occurs, PC will be unchanged.
28.

If register contains non-existent memory address in
mode 2 and a bus error occurs, register will be
incremented.

------------------------------------------------------------- ------- ----- ------- ---------------------------

Same as above but register is unchanged.
29.

If register contains an odd value in mode 2 and a bus
error occurs, register will be incremented.

-------------------------------------------------------- ------------ ----------------------------------------If register contains an odd value in mode 2 and a bus
x
X
x
X

error occurs, register will be unChanged.
30.

Condition codes restored to original values after FIS
interrupt abort eElS doesn't abort on 35/40).

--------------------------------------------------------------------- ----- -----------------------------------

Condition codes that are restored after EIS/FIS interrupt abort are indetennina te.

11
31.

PDP-II

LSI-

ACTIVITI

Op codes 075040 thru 075377 unconditionally trap to 10
as reserved op codes.

11/23

05/10 15/20

35/40

----------------------------------------------------------------------r---------------------------------- -----

If KEVIl option is present, op codes 075040 thru 075377
perform a memory read using the register specified by
the law order 3 bits as a pointer. If the register
contents are a non-existent address, a trap to 4 occurs.
If the register contents are an existent address, a
trap to 10 occurs if user microcode is not present. If
no KEVIl option is present, a trap to 10 occurs.
32.

Op codes 210 thru 217 trap to 10 as reserved op codes.

----------------------------------------------------------------------~----------------------------------

Op codes 210 thru 217 are used as a maintenance

instruction.
33.

Op codes 075040 thru 075777 trap to 10 as reserved op
codes.

---------------------------------------------------------~---------------------------------------

Only if KEVIl option is present, op codes 075040 thru
075377 can be used as escapes to user microcode. Op
codes 075400 thru 075777 can also be used.
As escapes to user microcode and KEVIl option need not
be present. If no user microcode exis ts, a trap to
10 occurs.
34.

Op codes 170000 thru 177777 trap to 10 as reserved

-------

instructions.
---------------------------------------------------------~-----------------~---------------------

Op codes 170000 thru 177777 are implemented as floating

point instructions.
---------------------------------------------------------r----~-------~--------------------------r-------

Op codes 170000 thru 177777 can be used as escapes to

user microcode.
10 OCClITS.

If no user microcode exis ts, a trap to

-----

11
35.

PDP-II

151-

ACI'IV1'IY

CLR, SXT, MFPS, MIP1 and MTPD do just a DATO sequence
for the last bus cycle.

11/23

05/10 15/20

35/40

----------------------------------------------------------------------------------- ---------------------

CLR and SXT do DAT1P- DA'ID sequence for the last bus
cycle.

36. MIM.MGT maintenance mode SRO bit 8 is implemented.

---------------------------------------------------------------------------

37.

I 45

MEM.MGT maintenance mode SRO bit 8 is not implemented.

PS (15:12), user mode, user stack pointer, and MTPX
and MFPX instructions exist even when MEM.MGT is not
configured.

-----------------------------~-----

---------------------------------------------------------------------------------------------------------------

PS (15: 12), user mode, user stack pointer and MTPX
and MFPX instructions exist only when MEM.MGT is
configured.
38.

Current mode PS bits (15:14) set of 01 or 10 will cause
a MEM.?vK;T trap upon any memory reference.

---------------------------------------------------------------------------------------------------------------

Current mode PS bits (15:14) set to 01 or 10 will be
treated as user mode (11) and not cause a MEM.MGT trap.
39.

MTPS in user mode will cause MEM.MGT trap is PS
address 177776 not mapped. If mapped PS (7:5) and
(3:0) affected.

---------------------------------------------------------------------------------------------------------------

MIPS in user mode will only affect PS (3:0) regardless
of whether PS address 177776 is mapped.
40.

MFPS in user mode will cause MEM.MGT trap is PS address
177776 not mapped. If mapped, PS (7:0) are accessed.

-------------------------------------------------------------1-------------

x
--------------------

11
MFPS in user mode will access PS (7: 0) regardless of
whether PS address 177776 is mapped.

PDP-11

LSI-

ACTIVI1Y

11/23

05/10 15/20

35/40

41.

X
A HALT instruction in user mode traps to 4.
--------------------------------------------------------- --- -- -------- ----- -------- ------- ------ -------- ----X
X
X
A HALT instruction in user mode traps to 10.

42.

X
X
X
If an RTT sets the T bit and the next instruction is
an RTI, which clears the T bit, the T bit trap will not
be taken.
--------------------------------------------------------- ----- -------- ------ -------- ------- ------ -------- ~----X
X
X
Same as above, but the T bit trap will be taken.

PRIORITI OF TRAPS AND INI'ERRUPTS
LSI-II

LSI-ll/23

PDP-ll/04

PDP-II/OS, 10

PDP-II/IS, 20

BUSERR Trap
Memory Refresh
Trap Inst.
Trace Trap
PFAIL Trap
Bus Halt Signal
Event Line
Device Interrupts
Wait Loop

C1LERR Trap
mJ Trap
BUSERR Trap
PARERR Trap
Trap Inst.
Trace Trap
STOVF Trap
PFAIL Trap
Device Interrupts
Bus Halt Signal
Wait Loop

BUSERR Trap
Trap Inst.
Trace Trap
STOVF Trap
PFAIL Trap
Device Interrupts
Console Hal t
Wait Loop

BUSERR Trap
Trap Inst.
Trace Trap
STOVF Trap
PFAIL Trap
Device Interrupts
Console Ha.lt
Wait Loop

BUSERR Trap
Trap Inst.
Trace Trap
STOVF Trap
PFAIL Trap
Console Ha.lt
Device Interrupts
Wait Loop

PDP-ll/34

PDP-l1/35,40

PDP-ll/45

aDDAD Trap
Trap
BUSERR Trap
PARERR Trap
Trap Inst.
Trace Trap
STOVF Trap
PFAIL Trap
Device Interrupts
Console Halt
Wait Loop

PARERR Trap
rvMJ Trap

BUSERR Trap
STOVF Trap
(Red Zone)
Trap Inst.
Trace Trap
STOVF Trap
(Yellow Zone)
PFAIL Trap
Console Ha.lt
Device Interrupts
Wait Loop

Console Ha.lt
aDDAD Trap
SIDVF Trap
(Red Zone)
~ Trap
BUSERR Trap
PARERR Trap
STOVF Trap
(Yellow Zone)
PFAIL Trap
PIRQ
Device Interrupts
Wait Loop
Trace Trap

BUSERR = Timeout Error
= Memory Management Trap
PARERR = Parity Error
ODDAD = Odd Address Error
SIDVF = Stack Overflow
PFAIL = Power Fail
Ins t. = Ins truc tions

NUMBER

).Inote

054

DATE

TITLE

MXV11 Configuration

DISTRIBUTION
ORIGlNAIDR

12/ 27

/ 78

PRODUCT

Unrestricted

MXV11

Joe Austin

PAGE 1

OF 5

The MXV11 multi-function module contains the following functional elements:
a)
b)
c)
d)
1.

RAM - 8KB or 32KB with internal refresh
ROM - sockets for: 2KB, 4KB or 8KB program memory
512B bootstrap memory
2 DLV11-J type serial line interface ports
60 Hz crystal clock

This module will initially be available with two configurations of memory
as follows:
MXV11-M -- 8KB of RAM (ROM not included)
MXV11-AC -- 32KB of RAM (RCM not included)
The RAM can be configured to start on any 8KB boundary below 64KB. Because
of this restriction, the MXV11-M 8~~ version is not usable for memory above
56KB. It can be used in 18-bit memory address systems, but it is restricted
to being assigned to the lower memoIY area below 56KB.
The MXV11-AC, on the other hand, can operate above 56KB, but its starting
address must be at 56KB (160000 8 ) or below. This then allows it to cover
the 56KB-88KB range (160000 8 to 257777 8 ) as shown in Figure 1.
Beyond these restrictions, the MXV1l-M or MXV11-AC can be used with any
other valid combination of memories.

The ROM area of the MOCV11-AA or -AC can be configured to operate in
bank 0 (0-8KB), 1 (8KB-16KB), or the I/O page (see Figure 2). If bank 0
or 1 is selected, then the customer can use his own 1Kx8, 2Kx8 or 4Kx8
RCMs, and the ROMs can be either fusible link PRCMs, ultra-violet
erasible EPROMs, or masked RCMs (see Micro Note #51).

~D~IJD~D
COMPC~ENTS

CiRC)UP
13f3

)./note

NUMBER 054
PAGE 2 OF 5

If the boot area in the I/O page is selected, then the customer can use
two 255x8 ROMS starting at the power up address of 173000 8 • This ROM area
covers the 512 byte address range of 173000 to 173777. In addition, a
configuration jumper is provided which allows a user to install two 512x8
ROMs. 512 bytes of the 1KB can be used at a time. A jumper is provided
on the board to select the upper or lower half of the larger ROM.
The user may provide his own ROM in this area, or he may use the following
DEC-supplied bootstrap ROM:
MXV11-A2 - ROM bootstraps for:

disk -- RLV11 (RL01)
RKV11 (RK05)
RXV21 (RX02)
RXV11 (RX01)
tape -- ru58

This ROM is a 512 word ROM that uses the above-mentioned jumper to select
either the disk boots or the TU58 boot. It is not possible for both sets
of boots to-oe-accessible in ~same system simultaneously, even if two
MXV11 Inodules are used since both ROMs would occupy the same address space.
3.

The two serial line ports have the same functionality as the DLV11-J
except that RS-422 is not supported. The output connectors are the same,
allowing the use of the same cables. The DLV11-KA option is also
required to support a 20 rnA interface.
a)

Address Selection -- Serial port 0 may be assigned to one of four
startlng addresses: 176500, 176510, 176520 and 176530.
Serial port 1 may be assigned addresses in two ranges. The first
range starts at 176500 and covers the eight starting addresses from
176500 to 176570. The second range starts at 177500 and also
contains eight possible starting addresses, including the standard
console address, 177560. Due to the fact that several other standard
DEC devices use addresses in this second range, it is recommended
that only the console address be used.

Interrupt Vector Selection -- Vectors can be configured for either of
two ranges - - 000 to 074 or 300 to 374. Both ports must be configured
in the same range, but within the range any combination can be configured.

System Clock -- The 60 Hz crystal controlled clock can be jumpered to the
BEVNT line to provide the equivalent of line time clock which does not
otherwise have one. The factory configuration is to have this signal
disconnected. It should not be connected if there is any other source in
,the system. This includes the case where there is more than one MXV11
module in a system.

mD~DDmD
COMPONENTS

GROUP
137

).Inote

NUMBER 054
PAGE 3 OF 5

This clock can be used in conjunction with the BDVII clock status/control
regis ter feature. The BDVll can s till be used to turn the clock off under
program control since it accomplishes this by pulling the BEVNT L line to
ground on the bus. If this control feature is to be used, the MXVll should
be installed in the same expansion box as the BDVll.
5.

System Concepts:
a)

The RCM and RAM memories should not be configured to cover the same
area of memory. There is no ove~rlay protection logic to prevent
conflicts in this case.

The RAM memory will not respond to addresses in the I/O page area
(bank 7 in 16-bit address systems). This prevents conflicts when
peripherals (including the on-board SLUs) are addressed.

It is not practical to install more than 2 MXVl1 modules into a single
system due to cost considerations. Even though the hardware limitation
imposed by the SLU addressing is 4 modules, it is not reconnnended that
customers consider using more than 2 in one system.

~DmDI~mD
COMPOI-tENTS

GROUP
13f~

054
PAGE 4 OF 5

NUMBER

SvlALL SYSTEM

LARGE SYSTFM

SINGLE MXVII-AC
EXAMPLE 1 0

DUAL MXVll- AC
EXAMPLE 3
OlliER
MEMORY
VALID
START
ADDRESSES
8KB
INCRIMENTS

MXVII-AC
RAM

FIRST
MXVII-AC

16KB
32KB

RAM

I 0 PAGE

SECOND
MXVII-AC

48KB
64KB

RAM

80KB
96KB
112KB
128KB

SMALL SYSTI:M

144KB

DUAL MXVll- AC
EXAMPLE 2
0

160KB

FIRST
MXVII-AC
RAM
I

-1'

c;::

SECOND
MXVII-AC
IV\M
I
I/O PAGE

.1/0 Page Overlay

Is Invisible

176KB
16KB
192KB
32KB
208KB
48KB
224KB
64KB
240KB
248KB

I 0 PAGE

SAMPLE MXVI1-AC
EXAMPLE RAM CONFIGURATIONS

139

256KB

NUMBER 054
PAGE 5 OF 5

).Inote

IS-BIT MEMORY SYSTEMS

OKB

16-BIT MEMORY SYSTEMS

BANK 0 RCM --:--

SKB
---- BANK 0 ROM
-------BANK I Ra.1 ___ _ _ _ I~KB_ __ _
::::= BANK I RQ\1

56KB

16-BITI/0 F~GE
64KB

256 Word ______
ROM Boot

256 Word

------- ROM Boot

_ _24SKB
_ _ __ _
IS-BIT I/O F~GE
256KB

FIGURE 2 -- MXVII-M, -AC ROM ADDRESSING RANGES

~D~D[lmD
COMPC»IENTS
GROIIP
140

NUMBER

)lnote

DATE

LSI-II vs. LSI-ll/23 Bus Timing

TITLE

DISlRIBUTION
ORIGINATOR

055

12/ 28 /78
PRODUCT

Unrestricted

KDll; KDFll- A

Ted SemEle &Doug Swartz

PAGE 1

Even though the LSI-II bus is asynchronous, many users did not take advantage of
this feature by optimizing their custom interfaces. Undoubtedly, some custom
interfaces that work with LSI-II and LSI-11/2 processors will not work with the
LSI-11/23 because the KDFII-A module performs bus transactions faster than the
KDll modules. This Micro Note will help users isolate problems that might arise
when they migrate their applications to the new processor.
NOTE:

Any custom interface that meets the LSI-II bus specification
published in the LSI-11 Processor Handbook will work with
either the KD11 or KDF11-A processor modules. Only modules
that do not abide by the specification have a potential
compatibility problem.

Note the following while studying Table 1 - LSI-11 vs. LSI-ll/23 Timing Differences:
1)

The KDFI1-A performs bus transactions faster than the KDII-F.

Neither the KDF11-A nor the KDI1-F run at the maximum bus speed.

Users should review their custom interface designs to make sure that changing
things like address set-up time from 285 ns. to 196 ns. will affect their module
operation.
All DIGITAL modules meet the bus timing specification and will work with all
processor modules. (Some modules such as the REVII and RKVll are not compatible
with the KDFII-A processor, but this is not because of bus timing.) Likewise,
modules designed with the DCK11 Chipkits will work properly with all processors.

~D~DD~D
COMPONENTS

GROUP
141

NUMBER 055
PAGE 2 OF 2

).Inote
TABLE 1
LSI-II vs. LSI-11/23 BUS TTIMING DIFFERENCES

BUS SPEC 1
--

KD11-F 2

KDF11-A 3

BSYNC L - BDIN L

100 ns. min.

190 ns.

130 ns.

BSYNC L - BOOUT L

200 ns. min.

285 ns.

260 ns.

ADDRESS SET-UP TTIME

150 ns. min.

285 ns.

196 ns.

ADDRESS lDLD TIME

100 ns. min.

100 ns.

REPLY TO DIN/OOUT INACTIVE TTIME

150 ns. min.

720 ns. min.
1120 ns. max.

220 ns. min.
285 ns. max.

mTES:

Bus specification times are at the bt~ master inside the bus drivers.

KDl1- F with 380 ns. microcycle time.

KDFI1-A with 300 ns. microcycle time.

~D~~DD~D
COMPONENTS
GROUP
1L~2

NUMBER

).Inote

056
DATE

TITLE

DLVll-J Cabling

DIS'IRIBUTION
ORIGINATOR

12 /

/ 78

PRODUCT

Unrestricted

DLVll-J

Barbara Beck
PAGE 1 OF 4

This Micro Note presents all the cables currently available that will mate with
the 2x5 pin Amp connector on the DLVll-J, as well as some pointers and part
numbers for constructing a cable.
DEC cables for the DLVll-J:
BC20N-05

5' EIA RS-232C null modem cable to directly interface
with an EIA RS-232C terminal (2x5 pin Amp female to
RS-232C female; see Figure 3).

BC2lB-05

5' EIA RS-232C modem cable to interface with modems
and acoustic couplers (2x5 pin Amp female to RS-232C
male; see Figure 2).

BC20M-50

50' EIA RS-422 or RS-423 cable for high-speed transmission ( 19.2K baud) between two DLVll-J's (2x5 pin
Amp female to 2x5 pin Amp female).

DLVll-KA

20 rnA current loop converter option for the DLVll-J.
Comes with an EIA cable (BC2IA-03) which connects the
DLVll-KB converter box to the DLVll-J. The option
mates with standard DEC 20 rnA cabling using the 8-pin
mate-'n'-lock connector.

When designing a cable for the DLVll-J, here are several points to consider:
1.

The receivers on the DLVll-J have differential inputs. Therefore, when
designing an RS-232C or RS-423 cable, RECEIVE DATA (pin 7 on the 2x5 pin
.Amp connector) must be tied to signal ground (pins 2, 5, or 9) in order to
maintain proper EIA levels. RS-422 is balanced and uses both RECEIVE DATA+
and RECEIVE DATA- •

To directly connect to a local EIA RS-232C terminal, it is necessary to
use a null modem. To design the null modem into the cable, one must
switch RECEIVED DATA (pin 2) with TRANEMITTED DATA (pin 3) on the RS-232C
male connector as shown in Figure 3.

~D~DD~D
COMPONENTS

GROUP
143

NUMBER 056
PAGE 2 OF 4

)./note
3.

To mate to the 2x5 pin connector block, the following parts are needed:
Cable Receptable

AMP PN 87133-5
DEC PN 12-14268-02

Locking Clip Contacts

AMP PN 87124-1
DEC'PN 12-14267-00

Key Pin (pin 6)

AMP PN 87179-1
DEC PN 12-15418-00

The pin out on the 2x5 pin connector block on the DLV11-J is as follows:
Pin #

Signal
UART clock in or out (16 x baud rate; CMOS)
Signal ground
TRANSMIT DATA+
TRANSMIT DATANOte: For EIA RS-423, this line is grounded.
For DLV11-KA 20 rnA. option, this line
is the reader enable pulse.
Signal ground
Index in key - no pin
RECEIVE DATARECEIVE DATA+
Signal ground
When FI is installed for the DLV11-KA, +12V is supplied
through a lA fuse to this pin

1
2

3
4

5
6

7
8
9

10
9

o
r...,

2x5 PIN CONNECTOR
BLOCK (Viewed from
Edge of Card)

."')

mD~IDDmD
COMPClMENTS

GROUP
1~~4

-.......;

PRINTED
CIRaJIT
CARD

NUMBER 056
PAGE 3 OF 4

FIGURE 1
DLVII-J CABLING SUMMARY

DLV11·J TO MODEM OR ACOUSTIC COUPLER

~DLVll~I-·-----B:~O:~50------·1 DLVl -J ~

14=-9FT-ft
(NOTE 2)

~D~DDmD
COMPONENTS
GROUP
145

NUMBER 056
PAGE 4 OF 4

)Jnote
BC21B-OS MODEM CABLE
FIGURE 2

EIA RS-232C

DLVII-J
~

~-.

rr-

GRD

RCV DATA) 1)+12 VDC

7S0n
1/2 W

<s( - -1

Clear to Send (CB)

I
I

r-(4( - -I

Request to Send (CA)

'- ~ 6~- 1

Data Set Ready (CC)

... r-'~ __ ,I

Data Terminal Ready (CD)

FIlA fuse /
RCV DATA +) 8"'I

<3 (

Received Data (BB)

XMIT DATA +) 3)

<2(
7<

Transmitted Data (BA)

(l(

protective Ground (AA)
Modem

>2 I

GRD

GP-

Connector

DLVII-J Module

Cable

EI.A

RS 232C
Connector

Signal Ground (AB)

BC20N-OS 'Null Modem' Cable
FIGURE: 3

EIA RS-232C

DLVII-J
XMT DATA +

~_4~--------,----------------------~~~-3-(.
"I ____________________
3

RCV DATA

RCV DATA +

) 8

2 -<

XMT DATA

RCV DATA -

GRD

):-J

GRD

\......-2

--------~~---(

----1J1.--- (

Shield

Important:
Attach to chassis
at entry point.

~D~DD!~D
COMPONIHrS
QlOUI~

146

GRD

NUMBER

j.lnote

057
DATE

TITLE

Location of W13 on the BDV11

DIS1RIBUTION

Unrestricted

ORIGINATOR

Joe Austin

12 /

PRODUCT

BDV11-AA
PAGE 1

OF 2

W13 on the BDV11-AA module is referenced in several places in the Memories
and Peripherals Handbook, but its location is not shown in any figures. The
purpose of this Micro Note is to show where W13 is located.
W13 on the BDV11-AA module is located as follows (see Figure):
1.

Remove capacitor C30 whiCh is located between PROM sockets E37 and E38.

Insert one end of W13 in the pad that was used for the right-hand side of
C30 as shown in the Figure.

Insert the other end of W13 in the feed-through hold located approximately
7/16 inch to the right of the pad of item 2 above.

The function of W13 is to COlUlect either +5V or GND to pin 21 of same ROM
sockets to allow for use by different types of ROMs.

~D~DD~D
COMPONENTS

GROUP
147

NUMBER 057
PAGE 2 OF 2

'" +
+

. + ~

<nIIJIt- + +

-~.
+

+ ,..

!fl

~D~~DDmD
COMPONENTS
QOUP
148

NUMBER

),Inote
TITLE

Configuring Memory for LSI-II Systems With MOre
Than 64K Bytes

DIS1RIBUTION
ORIGINAIDR

058

DATE

/ 02 /

PRODUCT

Unrestricted

LSI-11/23

John llighes

PAGE 1 OF 6

The LSI-ll/23 makes it possible to implement LSI-II Family systems with up to
248KB of memory (the last 8KB of address space is reserved for peripheral device
addresses). The LSI-II and LSI-ll/2 processors are capable of addressing up to
56KB of memory, with a total of 64KB of address space including I/O addresses.
There are a number of characteristics of the memory modules in the LSI-II Family
which will affect their usefulness in large memory (more than 64KB) configurations.
This Micro NOte focuses on the consideratlons involved in configuring large
memory LSI-II systems.
MEMORY CHARACTERISTIC DESCRIPTION
Attached to this Micro Note is a table describing four different characteristics
for each of the memory modules in the LSI-II Family. The following points
summarize the memory characteristics and their impact on large memory configurations.
Address Lines Decoded
16 address lines are required to decode addresses up to 64KB. Some of the
earlier LSI-II Family modules decoded only 16 lines because this was the
maximum address capability of the LSI-II and LSI-ll/2. These modules are
not useful in large memory configurations. Only which modules which decode
18 address lines can be used for larger than 64KB configurations.
Start Address Increments
The start addresses for memory modules are selected by straps or switches
on the memory board. The start address increments entry in the attached
table indicate the granularity of start addresses that can be selected. .An
8KB entry in this column indicates that start addresses 0, 8K, 16K, 24K, etc.
are possible.
Although this memory characteristic does not impact the usefulness of
memory modules in large memory configurations, it does impact the way in
which memories are positioned in address space.

~D~DDmD
COMPONENTS

GROUP
149

).Inote

NUMBER 058
PAGE 2 OF 6

Start Address Positioning
Start address ranges for memory modules fall into three categories:

i) Start addresses that are in the first 64K bytes of address space.
2)

Start addresses that can be anywhere within the 256KB address space
of the LSI-11/23.
Start addresses that are at the standard bootstrap location (173000
for a small memory system and 773000 for a large memory system).

All memory modules which have 16-bit address capability are confined to
start in the first 64KB of address space. Most, but not all, memories
which have 18-bit addresses can start anJrwhere within the 256KB address
space of the LSI -11/ 23. The exception to this rule is the MXV11. This
module, although it has 18-bit addressing, has a RAM memory section which
is confined to start addresses in the fi:rst 64KB.
Capacity
The colunm headed capacity shows the amolmt of storage provided by each
memory module in K bytes. Some memory modules have varying capacity.
Capaci ty variations are acc.omplished by using memory chips of varying
densities and also by partially or completely populating memory boards
wi th memory chips.
NiUscellaneous Memory Characteristics
1)

RAM!PROM Implementation -- RAM memory· boards are provided with the
memory chl.ps permanently installed (soldered) on the board. PROM
memory boards, on the other hand, are provided with PROM sockets only.
Customers are advised to purchase one of the chip types which are
reconnnended for each of the PROM boards.

2) MSV11-B Refresh -- The MSV11-B memory is the only memory which requires
bus refresh. This refresh has to be provided either by one of the
quad size LSI-II processors using microcode refresh or alternately, by IMA
using an REV11. All other RAM memory modules are self-refreshed; that
is, they have the circuitry on the memory board to refresh the dynamic
RAM chips independent of any bus activity. The MSV11-B is a relatively
low density memory board. It is not recorrnnended for new designs.

~DmDDmDI
COMPOMENrTS

GROUP
150

),Inote

NUMBER 058
PAGE 3 OF 6

3) MXVII Configurations
The MXVII multi-function board warrants separate consideration because it
is a very popular board with some special configuration characteristics.
The following points summarize those characteristics:
1) RAM memory capacity for the MXVII can either be 8KB or 32KB.
2)

RAM memory start addresses must be in the range of 0 to 56KB in
increments of 8KB. The memory address space that is covered by the
MXV11 can begin in the first 64KB addresses and extend into the next
64KB addresses. The start address cannot, however, be outside the
range of the first 64KB.

There are three alternatives for the start address for PROM memory
on the MXVll:
a)
b)
c)

address 0
address 20,000 8
address 1730008 (bootstrap)

When the 32KB RAM version of the MXVII is purchased, a maxtffium of two of
these modules can be used in an LSI-l1/23 system.
4)

Peripheral Address Decoding
8KB of addresses is reserved in all LSI-II Family systems for addressing
peripheral devices. In small memory systems with a maximum of 64KB addresses,
the peripheral device address space is in the address range of 56KB to
64KB. In a large memory sys tern with a total of 256KB addresses, the
peripheral device address space is in the range of 248KB to 256KB.
Peripheral devices decode the low order 13 bits of an address and a
separate line called BBS7 to determine when they are being addressed. They
do not decode the high order address bits. BBS7 is generated by the
processor any time that it wishes to communicate with a peripheral device
in the upper 8KB of address space. This type of arrangement means that it
it unnecessary to change peripheral devices to operate in small (64KB)
or large memory (256KB) configurations.
When configuring a large memory system, it is possible to position memory
in the range of 56KB to 64KB. This space would normally be reserved for
peripheral device addresses in a small memory configuration.

~D~DDmD
COMPONENTS
GROUP
151

NUMBER 058
PAGE 4 OF 6

5) MRVII-C Window Mapped
The MRVlI-C has two modes of operating. It can either be mapped directly
into the address space of the LSI-l1 bus or it can appear as two separate
lK address windows. The window conc.ept makes it possible for small memory
configura tions to have access to a large amOlmt of PROM storage without
taking up a large amount of address space. A separate Micro Note in the
future will describe the window mapping concept in more detail.
6) MSVII-D I/O Page Overlap
The MSVll- D has the ability to provi.de 60KB of memory in a small memory
system with a maximum address space of 64KB. This is accomplished by
mapping RAM memory into the address space between 56KB and 60KB which
would normally be reserved for peripheral device addresses. This feature
of the MSVII-D is available only on the MSVI1-DD model where the start
address is configured to be location O.
This capability is also available for the MSVII-DD in large memory
configurations provided that the start address is 192KB. With the I/O
page overlap feature enabled in this large memory configuration, the
MSVI1-DD configuration will provide memory all the way up to 252KB overlapping half of the I/O address space (i.e., 4KB).
Ma1JRY MAPS

Included in this Micro NOte is a pair of memory maps for small and large systems.
These maps are intended to be used as a tool in configuring memory for LSI-II
systems.

~DmDDmD
COMPCtlENTS
GRC)uP
1E.2

058
NUMBER
PAGE 5 OF 6
LSI-II MEMORY CHARACTERISTICS
ADDRESS
LINES
DECODED

START
ADDRESS
INCREMENTS

START
ADDRESS
POSITIONING

CAPACITI

MMVII-A

8KB

0-56KB

8KB

MSVII-B

8KB

0-56KB

8KB

MSVII-CD

8KB

0- 248KB

32KB

18
18
18
18

8KB
8KB
8KB
8KB

0-248KB
0- 248KB
0-248KB
0-248KB

8KB
16KB
32KB
64KB

MRVll-AA (512x4 PROMS) 16
(256x4 PROMS) .16

8KB
4KB

0-56KB
0-56KB

lKB-8KB
512 Bytes-4KB

18
18

8KB
512 Bytes

0- 248KB
0- 248KB

2KB-8KB
512 Bytes

8KB

0-248KB

8KB-64KB

18
18

8KB
8KB

0- 56KB
0-8KB
(or boot)

8KB or 32KB
2KB-8KB

RAM

MSVII-D

A
B
C
D

PR~

MRVll-BA

PR~

RAM

MRV11-C
MULTI-FUNCTION
MXVl1

RAM

PRrn

153

NUMBER 058
PAGE 6 OF 6
SMALL SYS'I'rM

IARGE SYSTIM

MIM>RY MAP

MrMORY MAP

16KB

32KB

·H8KB

48KB

56KB -+--------1

llO PAGE

64KB

64KB
80KB

248KB -I-,-r""'!"'lO----PA~G-E---I
256KB

NUMBER

)lnote
TIlLE

059

DATE

LSI-11/23 Four-Level Interrupts

DIS1RIBUTION
ORIGINATOR

1 /

PRODUCT

Unrestricted

LSI-11/23

Dave Schanin

PAGE 1 OF 7

I NIRODUCTI ON
The LSI-11/23 implements a four-level priority interrupt scheme which is backward
compatible to the single level system used on the LSI-II and LSI-11/2. This
allows a prioritizing of the interrupts so that a high priority interrupt request
can interrupt a lower priority service routine. Figure 1 illustrates the LSI-II
priority scheme. Figure 2 illustrates the LSI-11/23 priority scheme. NOte that
the LSI-11/23 has both a vertical system priority (that is software controllable)
as well as the LSI-II type of horizontal priority within each system priority
level.
FOUR-LEVEL INTERRUPT IMPLfMENTATION
Hardware - Signal Line Definition
On the LSI-II,

the BIRQ line was treated as a level four interrupt; i.e.,
BIRQ 4. The LSI-11/23 preserves this definition and redefines three
additional lines to gain the additional three levels of interrupt:
BSPARE 6
BSPARE 2
BSPARE 1

BIRQ 7
BIRQ 6
BIRQ 5

Hardware - Interrupt Acknowledge Scheme
The LSI-II interrupt acknowledge scheme consisted of a daisy-chained grant
signal issued from the processor whenever the BIRQ line was asserted. It
was the responsibility of the I/O modules to accept the IAKI pulse and pass
it on as an IAKO pulse if the module was not requesting an interrupt. !AKO
would not be passed on if the module was awaiting an interrupt acknowledge.
The LSI-11/23 preserves this IAK scheme for backward compatibility with
the LSI-II but adds an additional responsibility to the I/O modules to pass
IAK if a device is requesting an interrupt but there is a higher priority
interrupt request pending.

~D~DD~D
COMPONENTS

GROUP
155

).Inote

NUMBER 059
PAGE 2 OF 7

Hardware - Interrupt Protocol
There are two methods for handling interrupt protocol. The first method uses
position-dependent I/O modules and the second method uses position-independent
modules within interrupt levels.
The primary motivation for the two different methods of implementing fourlevel interrupts has to do with whe~ier the module under discussion already
exists or is in design. The PositioJrr-Dependent approach allows simple and
straightforward upgrade of an existing module interfaced to the LSI-II bus
to operate in a multi-level environment on any interrupt level other than
four. The Position-Independent approach is reconnnended for new module
implementations; it is the approach that will be used by DIGITAL on all
future modules.
As.a general description,

position-dependent I/O modules must not only be
in priority order within their respective levels but must also be in system
priority order (see Figure 3). Pos~tion-independent modules, however, can
be placed anywhere in the backplane-and still maintain their assigned
interrupt priority level. These mO&lles need only be placed in priority
order within their respective priority levels. The most significant drawback
to the module position-dependent approach is non-backward compatibility with
the LSI-II. This will be explored in the following two sections.

ME'lliOD ONE - .POSITION-DEPENDENT MOOOLES
Method One is simply an extension of the present LSI-II interrupt scheme. A
module 'tvhich is requesting an interrupt simply asserts the BIRQ line for t~t
particular inter!1Jpt level. The IAK ac]mowledge signal is also handled
identically with the LSI-II. When an L\KI signal is received, the module passes
the signal to the IAKO only if the module is not requesting an interrupt. The
limitation of this simple scheme is thqt the modules in the system must be
placed in interrupt priority order not only wi thin an interrupt level but also
must be placed within the system inter~lpt levels; i.e., all level 7 modules
must be closer to the processor than level 6 modul~sL etc._ An important
observation should be made concerning tilis approach to four-level inter~pts.
If a mod~f ~d~~~ed to f:~e;t ~ interrupt leyel above BIRO 4 and i t

C O~ - I "a

only ass; 5TR
6, o r a d f' will not be transferrable to an ,LSI-II ~/~~AJ'(.oe
based . SYS tern since the only BIRQ line q.xail aQleIn the LSI -11 is RI,BQ 4.
lilA-if.
ME1HOD 1W0 - POSITION- INDEPENDENT IDDULES
Method 1Wo allows the modules to be placed in any sequence within the system;
however, the modules must still be placed in order within an interrupt level.
The basic approach here is that a module asserts the BIRQ line corresponding to
the interrupt level that it is on and, in addition, asserts the BIRQ lines of
lower priority according to Chart 1. TIle scheme outlined in Chart 1 requires

~D~DDmD
COMPC)NEMTS
QIC)lJP
156

NUMBER 059
PAGE 3 OF 7

).Inote

a module to monitor a maximum of two other BIRQ lines and assert a maximum of
three BIRQ lines. This is done to allow design of a DC103 Integrated Circuit
that has just two additional pins over the standard DC003 chip. The DC103 will
be incorporated in new I/O module designs from DIGITAL. Therefore, it is
important to adhere to the scheme outlined in Chart 1 to maintain the approach
tha t DIGITAL will be following in the future.
In addition, there are two side benefits from this assertion/monitoring scheme.
One is that a module so designed will be backward compatible with the LSI-II
since regardless of the interrupt level of the module, it will always assert
BIRQ 4. The second is that it gains position independence for modules on
separate interrupt levels. This is accomplished by modifying the interrupt
acknowledge sequence as follows: A modUle monitors the BIRQ line that is at
a higher priority level than the one on which it is currently requesting an
interrupt. When such a module requests an interrupt and receives an IAKI, it
will pass on the IAKO despite requesting an interrupt if the higher level BIRQ
line is asserted. The module will retain the IAKI only if it is both requesting
an interrupt and the higher level BIRQ line is asserted. The penalty here is
the increased functionality required on the module. However, as was previously
mentioned, this method retains backware compatibility with the LSI-II. Note
that arlY module in this position-independent system needs to only monitor
BIRQ 5, 6 because of the BIRQ assertion scheme in Chart 1. This is done to
reduce the number of line receivers required on an I/O module and also allows
the module to be compatible with the DC103 integrated circuit that will be
used by DIGITAL to create four-level interrupt capability on the standard I/O
modUles. Therefore, an important feature of this second approach to fourlevel implementation is that it will be compatible with future modUles from
DIGITAL.
MODULE INTERRUPT LEVEL
Level 4
Level 5
Level 6
Level 7

CHART 1
ASSERTS
BIRQ 4
BIRQ 4
BIRQ 5
BIRQ 4
BIRQ 6
BIRQ 4
BIRQ 6
BIRQ 7

~D~DDmD
COMPONENTS

GROUP
157

MONITORS
BIRQ 5
BIRQ 6
BIRQ 6
BIRQ 7
(None)

NUMBER 059
PAGE 4 OF 7

HARDWARE - SlM1ARY OF FFAWRES
APPROACH

POSITIVE FFAWRES

NEGATIVE FFAWRES

Position
Dependent
Modules

1. Easy to implement
2. Can use DC003

1. Not compatible with

Position
Independent
Modules

1. Compatible with LSI-II
2. Identical with the DIGITAL
approach
3. Module placement not critical
to correct system operation

1. Requires added logic
on the I/O board or
DC103 chip

LSI-II
2. Not functionally the
same as the approach
to be used by DIGITAL
3. Module placement in
the backplane is
critical

SOFTWARE IMPLICATIONS
The software has the capability of establishing the minimum priority level that
is to be allowed to interrupt. This is done by manipulating the Processor
Status Word (PSW). Bits 5-7 establish the minimum interrupt priority in an
LSI-11/23 system. In the LSI-II system, bit 7 (corresponding to 100 2 or 4 for
BIRQ 4) was the only priority bit. Here is a comparison of the two PSW's:
15

NOT USED

NOT
USED

T
BIT

CONDITION
CODES

INTERRUPT
PRIORITI
15

CURRENI'

MODE

PREVIOUS
MODE

NJT USED

INTERRUPT
PRIORITI

T
BIT

CONDITION
CODES

It should be noted that all DEC software correctly handles either the single
level or the mUltiple levels of interrupt priority.

~DmDDmD
COMPC»IENTS
GROUP
158

IRQ 4

P
R

o
..... c
CJ1 E
CO S
S

OPTION #1

o
R

IAKI

OPTION #2

OPTION #3

/, f'

IAKO

IAKI

!AKa

FIGURE 1 -- LSI-II INTERRUPT SCHEME

IAKI

IAKO

FIGURE 2 -- LSI-11/23 POSI
~

______________________

.'I- INDEPENDENT MJIlJLES

_________________________________________

I~~Q~7

OPTION
#1

/,-

IAKI

IAKO

IRQ 6
~

OPTION

#3
-!.

,1\

CI)

fi.)

s<
E

IAKI

IAKO

IRQ 5

OPTION
#4

R
1
-I

IAKll' -----------lIAKO

~----------'

OPTION
#2

IAKI

l' ~----------'
lIAKO

----~~

INTERRUPT LEVEL PRIORI'IY

IRQ 4

FIGURE 3 -- LSI-11/23 PO~

IN-DEPENDENT MODULES

IRQ 7

~----------~I----~----~~~~~----~----~~----~------------------~---+l
i

OPTION
#1

II'

a
c
~

IRQ 6

IAKO

OPTION

.-\

IAKI

'1'-

IAKI

IAKO

IRQ 5
- -

---

-----,--

-.-.

OPTION
#3

IAKI

IAKO

IRQ 4

_.-

OPTION
#4

1'1

NUMBER

).Inote
TITLE

060

Maximum Configuration of DLVI1-J Modules

DISTRIBUTION
ORIGINATOR

DATE
3

01 / 79

PRODUCT

DLV11-J Users

DLV11-J
Joe Austin
PAGE 1 OF 2

The purpose of this Micro Note is to define the maximum number of
DLV11-J 4-line serial line unit modules that can be configured into a
single system.
The maximum number of DLV11'-J modules that can be installed into a
single system is limited by the range of interrupt vectors that can be
configured on the module. Starting with the base vector, the DLV11-J
uses eight consecutive interrupt vectors. However, the DLV11-J module
provides only three sets of configuration jumpers with which to configure the base vector.
The usable base vectors are shown below. Note that only the first two
conform to DIGITAL standards and are free from conflicts with other
options. Up to three more base vectors can be used if the conflicting
options are not present in the system. In the case of modules #3 and
#4, the vectors of the conflicting options can be reconfigured to
another value. This would require ch;mging both the hardware and the
support software for the conflicting option. In the case of the 5th
DLV11-J module, the conflicts with the FIX and MMU options cannot be
resolved if either is present.
SUMMARY

- 2 DLV11-J modules (8 serial lines) can be easily configured in a
single system.
- 5 DLV11-J modules (20 serial lines) can be configured if conflicts
can be resolved with other options.

~DmDD~D
COMPC)NOOS
GRC)uP

1612

NUMBER 060
PAGE 2 OF 2

DLVII-J

BASE
VECIDR*

STANDARD
ADDRESS

#1
#2
#3
#4
#5

300
340
140
200
240

176500
176540

CONFLIC1S WITH

RLVll
LPVll, RKVll
FIS, RXVll, MMU

Std. DIGITAL Configuration
Std. DIGITAL Configuration
Non-Standard
Non-Standard
Non-Standard

ADDITIONAL SERIAL LINES
The DLV11, DLV11-E, DLVII-F and DZVll can be used to add additional
lines, if necessary, that do confonn to DIGITAL standards. The assignment of addresses and vectors to confonn to DIGITAL standards is
defined in Appendix A of the Memories and Peripherals Handbook.

*The base vector cannot be configured above 400.

mDmDD~D
COMPONENTS
GROUP
163

NUMBER

)./note

061
DATE

TITLE

Programming the MRV11-C

DISTRIBUTION

2/ 02

/ 79

PRODUCT

Unres tric ted

MRV11-C
ORIGlNAIDR

Rich Billig
PAGE 1

OF 9

IN1RODUCTION
The MRV11- C is a high -densi ty ROM memory module for the LSI -11 bus. The
16 24-pin sockets on this module will accept 1024x8, 2048x8, or 4096x8
RCM, PROM or EPRCM memory chips. This gives the module a maximum storage
capacity of 64K bytes. All chips used on a single board must be of the
same density. However, the board may be partially populated in pairs of
chips. Table 1 gives the maximum storage for each chip density and total
number of chips installed. A jumper option on the MRV11-C allows this
board to respond to both DATI and DATIO bus cycles to allow use with
programs using the KEVIl extended instructions on the LSI-11/2 processor.
When used in an LSI-11/2 or LSI-11/23 system, this board may operate in
either direct addressing mode or window mapped mode. In addition, the
board may optionally provide a system bootstrap window.
DIRECT MODE OPERATION
When functioning in direct mode, the 1~V11-C serves as a high-density
replacement for the MRV11-AA or MRV11-BA ROM memory modules. The base
address of the direct mode RCM area is assignable on any 8KB boundary
from 0 to 248KB (000000 8 to 760000 8 ). When operated in this mode, the
application program is executed directly from the MRV11-C storage.
WINDOW MAPPED (PAGED) MODE OPERATION
When window mapped operation is selected, the entire contents of the RCM
board are not visible to the LSI-II address space at any particular point
in time. Instead, any two 2KB segments of the ROM can be addressed through
two independent windows defined in the LSI-II system's address space.
The association of segments of the Ra~ board with windows is controlled
by a control and status register. Refer to Figure 1 for an example of
this operation.
CSR Definition
Each MRV11-C board uses one 16-bit control and status register
located in the system I/O page to determine mapping of ROM

~DmDD~D
COMPC)NENTS
Ci~)UP

1E34

NUMBER 061
PAGE 2 OF9

segments into windows in the window mapped mode. The default
address for this CSR is 177000 8 (777000 8 in 11/23 systems). The
valid address range for CSR's is 177000 8 to 177036 8 (777000 8 to
777036 8 on 11/23 systems). Figure 2 shows the bit assignments
for the MRV11-C control and status register.

15 14 13 12 11 10
D 0
S

WINDOW 1
PAGE #

WINDOW 0
PAGE #

FIGURE 2
MRV11-C CONTROL AND STATUS REGISTER FORMAT

The CSR contains a 5-bit read/write field for each window. The
number stored in this field (0 to 31 10 ) selects the desired 2KB
region from the MRVI1-C board to be associated with the window
in question. CSR bits 0 through 4 control the mapping of the
low address window, window o. The low 5 bits of the upper byte,
bits 8 through 12, control the mapping of window 1.
The MRVI1-C optionally provides a window enable/disable capability.
When this option is selected, bit 15 of the CSR is used to enable
or disable window response under program control. When bit 15 is
a 0, the board will respond to references to the CSR or DATI or
DATIO references to either of the windows. When bit 15 is a 1,
only the CSR will respond. If the enable/disable option is not
selected, bit 15 of the CSR will be read only and always O. The
enable/disable bit has no effect on direct mode addressing or
the bootstrap window capability.
The remaining bits in the CSR (bits 5-7 and bits 13-14) are
reserved and mus t always be zero.
Window Definition
Each MRVll- C board provides a pair of 2KB windows. These windows
are always contiguous with each other, and the base address of the
window pair may be set to any 4KB boundary in the LSI-II address

~D~DDmD
COMPONENTS
GROUP
165

NUMBER 061
PAGE 3 OF 9

space fronl 0000008 to 770000 8 • To maximize the amount of space
left for system RAM memory, a default window base of 160000 8
(760000 8 for 11/23 systems) is suggested. Figure 1 shows such a
window configuration.
Using MUltiple Boards
Up to 16 MRVII-C boards may be configured in a single system. When
multiple boards are present, each board has a unique control and
status register address assigned in increasing order from 177000 8
(777000 8 in 11/23 systelllS). Each board can have a unique 4KB area
of the physical address space set aside for its windows, but it is
also possible to share one 4KB area of the address space among all
MRVl1-C boards installed in the system. This is done by using the
enable/disable capability discussed earlier. When enable/disable
is implemented, the disable bit in the CSR will be set automatically
by BINIT on the bus or by execution of the RESET instruction.
Therefore, the initial state of the system will have all boards
disabled. To access a particular segment of ROM in this multi-board
configuration, the programmer first enables the desired board and
maps the segment. When access to that segment is completed, the
board is again disabled to allow another board to be selected at
a future time.

Sizing Window Mapped Boards
When a board is totally populated (i.e., all 16 PROM sockets are
occupied), the mapping values in the CSR will be interpreted modulo
the size of the board. Thus, if the board is populated with 2048x8
chips and the programmer selects the 16th 2KB section, the Oth 2KB
section will be mapped by the window. If, however, a board is
partially populated, an attempt to access the unpopulated area of
the board will result in a bus time-out trap.
BOOTSTRAP WINOOW

An additional optional feature of the MRVI1-C board is the capability to

respond to the standard PDP-II bootstrap addresses. When this feature is
enabled, an attempt to reference addresses 173000 8 to 173777 8 (773000 8 to
773777 8 in 11/23 systelllS) will be automatically rerouted to a user-selected
512-byte section of the MRVII-C board. In this way, 512 bytes of the
board will be visible in two places in the LSI-II address space. The
highest addressed 512 bytes of any 2KB segment of the board may be
selected to correspond to the bootstrap window. This allows custom
bootstraps to be added to an LSI-II system, without requiring an additional
board to store the bootstrap.

~DmDD~[1

COMPONDm
GROUP
166

NUMBER 061
PAGE 4 OF 9

WINDOW MAPPED MODE APPLICATION EXAMPLES
The window mapped mode may be used in two different ways in LSI-II
application programs. The application can be coded in such a way as to
execute directly from the windows, or the window mapped board may be
used as a program load device to transfer a stand-alone application
program from ROM into RAM memory at system start-up.
Executing Windowed Programs
Executing directly from MRV11-C windows allows very large program
sizes with up to 56KB of RAM on LSI-11/2 systems. HOwever, software to be executed in this mode must be custom designed and must
be written in assembly language.
An application designed for windowed execution must have a mechanism

for calling a subroutine or transferring control to another routine
which is physically located in a presently unmapped section of the
windowed ROM board. To accomplish this, we mus t use a technique
different from the standard JSR or JMP instructions. A method
for doing this is illustrated in Figure 3. The routine which
processes subroutine calls and jumps to other pages must, of course,
be located in a section of memory which is not window mapped. To
call a subroutine using these capabilities, one would write CALLWO
label rather than JSR PC, label. This would cause the subroutine
desired to be mapped into window 0 and the call to be executed.
Upon subroutine return which is done with a normal RTS PC instruction,
the original mapping would be restored and control would be
returned to the calling program unit. Likewise, to invoke a
subroutine but have it mapped in window 1, the programmer codes
CALLW1 label. Note that the mechanism shown in the figure preserves
condition codes from the called routine back to the caller (i.e.,
routines can return status in the condition codes). Instead of
the unconditional jump instruction, the programmer codes JMPWO label
to jump to a routine, mapping it into window O. Similarly, one can
code JMPW1 label to transfer control to a routine which should be
mapped into window 1.
To make use of this functionality, the program should be assembled
with .ENABL AMA to force absolute addressing in the assembly and at
start-up time, a boot routine must be executed (from the MRV11-C
boot window or elsewhere) which copies the trap handler routine to
RAM memory, if necessary, and initializes the trap vector to contain
the address of the trap handling routine and a new status word of
all O's.

~D~DDmD
COMPONENTS

GROUP
167

).Inote

NUMBER 061
PAGE 5 OF 9

The progrannner of this type of application must take care not to
cross page boundaries without remapping to the next page. If a
page boundary is encountered, the JMPWO or JMPWI pseudo instructions should be used to get to the begirming of the next· page.
Using Window Mapping As A Program Loader
The MRV11-C in window mapped mode can also be used as a low-cost
program load device for stand-alone applications. This allows
application programs which carmot be easily segmented into ROM
and RAM sections to be loaded from a ROM envirorunent into RAM
for execution. To use the MRV11-C in this mode, a bootstrap
loader program must be written to copy the contents of the ROM
board into the RAM area at power-up. Figure 4 demonstrates such
a program designed to load stand-alone images which have been
created by the RT-11 LINK utility. (Figure 4 is attached)
It is also possible to load an RSX-11S system image from one or
more MRV11-C boards into RAM for execution. The loader required
for this process will be the subject of another Micro Note.

~DmDDmD
COMPONENTS

GROUP
168

NUMBER 061
PAGE 6 OF 9

# OF
CHIPS
INSTALLED

1024x8

2048x8

4096x8

2
4
6
8
10
12
14
16

2KB
4KB
6KB
8KB
10KB
12KB
14KB
16KB

4KB
8KB
12KB
16KB
20KB
24KB
28KB
32KB

8KB
16KB
24KB
32KB
40KB
48KB
56KB
64KB

CHIP SIZE

TABLE 1
TOTAL STORAGE CAPACITY PER BOARD
AS A FUNCTION OF SIZE AND NUMBER OF CHIPS

169

NUMBER 061

PAGE 7 OF 9

PAGE
#
15
14

BIT 15=0 INDICATES
WINDOWS ARE ENABLED

1000 1

1770008

13
12
11
10

CONTROL & STATUS REG

1700008
1640008
1600008

I/O PAGE

7
6

WINDOW 1
-------WINDOW 0

5
4
3
2
1
0
MRVII-C
USING 16
2048X8
PROM CHIPS

LSI-II
ADDRESS
SPACE

FIGURE 1
EXAMPLE OF WINDOW-MAPPED OPERATION

170

NUMBER 061
PAGE 8 OF 9

WOBASE=16 0000
WlBASE=164000
JMPW =1
JSRW =0
Wl
=2
WO
=0
.MACRO
TRAP

•WORD
.ENIM

.MACRO
TRAP

. WORD
.ENIN

.MACRO
TRAP

•WORD
.ENIM

.MACRO
TRAP

.WORD
•. ENIM
1RPHAN:

MOV
TST
MOV
MOV
ADD
MOV
illV

BIC
ASR
ROR
MOV
ADC
illVB

ROL
MOV
BCS
JSR
MFPS
MOV

@#MRVCSR,- (SP)
- (SP)
RO, - (SP)
6 (SP) ,RO
#2,6(SP)
@RO,2(SP)
- (RO) ,RO
#177600,RO
RO
RO
#MRVCSR,-(SP)
@SP
RO,@(SP)+
RO
(SP)+ ,RO

PC,@(SP)+
4 (SP)
(SP)+, @#MRVCSR

RTI
illV

MOV
RTI

(SP)+,@SP
(SP)+,@SP

CALLWO ADRS
JSRW+WO+«ADRS/I000> &174>
WOBASE+<ADRS&3777>
CALLWO
JMPWO ADRS
JMPW+WO+«ADRS/I000> &174>
WOBASE+<ADRS&3777>
JMPWO
CALLWl ADRS
JSRW+Wl+«ADRS/1000> &174>
WlBASE+<ADRS&3777>
CALLWI
JMPWI ADRS
JMPW+W1+«ADRS/I000> &174>
WlBASE+<ADRS&3777>
JMPWI
;Save previous mapping
;Reserve space for adrs
;Save caller's register
;And set RO to address of TRAP+2
;Update return PC beyond adrs
;Mbve adrs (follows TRAP instruction)
;RO=TRAP instruction itself
;Extract page #, window #, JMP/JSR
;Mbve JMP/JSR to C bit
;Place window # in C, JMP/JSR in bit 15
;Set address of window 0 map bits
;And update based on window #
;Map new page in selected window
;JMP/JSR back to C bit
;Restore caller's re~ister
; If JMP, branch to 1~
;Else JSR to desired routine
;Store returned condition codes in old PS
;Restore original mapping
;And return after TRAP and adrs
;If JMP, move adrs
;Up over old (caller's) PC
;And go to new location
FIGURE 3

JSR AND JMP WINDOW MAPPED CON1ROL ROUTINES

171

NUMBER 061
PAGE 9 OF 9

MRVCSR=

177000

MRVWIN=

1601000

ONEKW=

003'777

LOADBR:

CLR

BHIS
BIT
BNE
INC
BR

@#MRVCSR
' ; Eriable & Map Low 1K Words
@#MRVWIN+SO,RS;RS = RT-11 SAV File High Limit
R4
;Start Copying Into Location 0
#MRVWIN,R3
; Reset to Base of Firs t Window.
CR3) +, CR4)+ ;Copy One Word Into RAM
R4,RS
;Moved Highest Word in Program?
;If HIS, Yes
3$
#ONEKW,R3
; Have Reached Next 1KW Botmdary?
2$
;If NE, No
@#MRVCSR
; Else Map Next 1K in Window 0
;And Continue Copying
1$

MaV

@#40,PC

IDV

1~:

CLR
MaV

2$:

MJV
Q.1P

34:

;Start at User's Transfer Address

FIGURB 4
BOOTS1RAP LOADER FOR STAND-ALONE PRoGRAMS IN RT-11 . SAV FORMAT

NUMBER

).Inote.

062A
DATE

TITLE BootstraEs for TUSS, RL01, RKOS, RX02, RX01
DI S1RI BUTI ON
ORIGINATOR

6 / 14
PRODUCT

Unrestricted

/ 79

russ, RL01,

RKOS, RX02, RX01

Rich Billig
PAGE 1 OF 31

-THIS MICRO NOTE SUPERSEDES MICRO !\UTE #062 ON TIIE SAME SUBJECT DATED 2/2/79

The attached listings contain the programs stored in the MXV11-A2 bootstrap chips. These programs reElace the preliminary versions originally
published in Micro NOte #062.
Either of these programs can be used in a 2S6-word bootstrap PROM
enviromnent in MRV11-M, MRV11-C or other RCM modules.
For more details on the operation, please consult the comments in the
program listings.

~DmDDmD
COMPONENTS

GROUP
173

MXV11 TU58 BOOTSTRAP
TABLE OF CONTENTS
2-

55666-

6666-

77-

778-

888999~

999910lOlOlO1113-

1
1
1
25
25
25

1
20
20
20
35

35
35
1
11
11
11
1
31
31
31
1

23
23
40
40
40
1
II
II
II

1
1

MACRO V03.02B13-JUN-79

Definitions and Protocol EGuates
Test
Subroutine to Write, Read, and Verifw Memorw
Memor~

*****
***** HALT AT PC=173076 INDICATES -MEMORY ADDRESS ERROR·
***** Data Storase Test
*****
***** HALT AT PC=173122 INDICATES ·BAD MEMORY DATA*****
*****
***** HALT AT PC=173140 INDICATES "MEMORY BACKGROUND DATA ERROR·
*****
MACRO, FORTRAN-Callable Loader Entry
Memor~

*
*----)
TULOAD ENTRY POINT IS AT ADDRESS 173154

Bootstrap TU58

*****
***** HALT AT PC=173274 INDICATES ·CONTROLLER ERROR - SUCCESS CODE IN RO LOW BYTE·
*****
Stand-Alone File Loader
*****
***** HALT AT PC=173374 INDICATES -DESIRED FILE WAS NOT FOUND*****
*****
***** HALT AT PC=173440 INDICATES ·PROTOCOL ERROR IN READ OPERATION*****
Load Stand-Alone Prosram File
*****
***** HALT AT PC=173474 INDICATES ·START ADDRESS INVALID"
*****
Start READ Operation on TU58
TU58 Interface I/O Routines

MXV11 rUS8 BOOTSTRAP

MACRO V03.02B13-JUN-79 PAGE 1
.TITLE
.ENABL

2
3
4
5
6
7

Edit level 11, made 09-Mar-79 by RRB
November 1978 by RRB
Copyright (C) 1978
by Digital Eauipment Corporation, Maynard, Massachusetts 01754

9
10
11
1~

13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
~~

56
57

MXV11 TU58 BOOTSTRAP
LC

000000

.REPT

This is a 256-word diagnostic and bootstrap program for LSI-l1 systems
using the TU58 DECtape II tape cartridge drives.
It performs the following
functions:
1.
2.

3.
4.
5.

On power up, size memory (up to 30K words).
Test addressing of memory by writing each location with its
address and verifYing the contents.
Check data retention, writing l's into a O's background, and
vice-versa.
Attempt to bootstrap the TU58 cartridge on unit O.
If unit 0 fails
to function, cycle to unit 1 and try it. Continue cycling between
units 0 and 1 until one correctly reads block 0 of the tape.
Check the first word read to see if it is 240(8).
If so, start
program execution at location 0 with interrupts disabled (PR7).
(This is the standard PDP-11 bootstrap convention.)
If the first word is not 240(8), check to see if it is 260(8).
If so, this signals a special ·stand-alone· program load reouest
to this bootstrap progr~a.
If not 260(8), return to step +4 and
cycle to the next unit.
If a stand-alone program load reouest was made (i.e., location 0
contains 260(8», scan the RT-11 directory of the unit to find
the file whose name is given in locations 2-6 in block 0 of the
cartridge. The name is represented as three words of RADIX50 data
denoting the desired filename and extension.
If the file is found in the directorY, load it as an RT-11 .SAV
image file, and start its execution.

The bootstrap ROM also provides a MACRO or FORTRAN-callable entry point
which can be used to ·chain· from one stand-alone prograa to another.
The format of the FORTRAN CALL is:
CALL TULOAD( ifile )
where ·ifile a is a four-element INTEGER array containing:
ifile(l)
ifile(2)
ifile(3)
ifile(4)

the
the
the
the

unit + of the TU58 drive to use (binarY 0 or 1)
RADIX50 code for the first 3 characters of the filename
RADIX50 code for the last 3 characters of the filename
RADIX50 code for the file extension

Calling the entry point TULOAD with the appropriate FORTRAN-format argument
list will cause the bootstrap to search the directorY of the indicated tape
unit for the file specified, and if found, load it into memory and start its
execution.
.ENDR

MXV11 TU58 BOOTSTRAP
MACRO V03.02B13-JUN-79 PAGE 2
DEFINITIONS AND PROTOCOL EQUATES
.SBTTL

Definitions and Protocol EQuates

Absolute address definitions

3
4

5
6
7

000002

FILNAM

000002

001000

DIRBUF

001000

8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

~Address of RAD50 filename for stand-alone
; prosram loading
;Start of 512. word buffer used for RT-l1
; director~ operations in stand-alone loadins

; TU58 Address definitions
176500
176502
176504
176506

TI$CSR
TI$BFR
TO$CSR
TD$BFR

176500
176502
176504
176506

iDL
;DL
iDL
;DL

receiver control and status
receiver data buffer
transmitter control and status
transmitter data buffer

TU58 Radial Serial Protocol codes
Flag B~te Definitions:
000001
000002
000004
000020
000023

R$$DAT
R$$CTL
R$$INT
R$$CON
R$$XOF

.... B<OOOOl>
.... B<00010>
~'B<00100>

.... B<10000>
.... B<10011>

iData message flag
;Control messase flaS
;Initialize flas
; ContinlJe flas
iXOFF

; Control packet operation codes:

27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
53
54

000000
000001
000002
000003
000004
5)00005
000006
000007
000010
000011
000012
000013
000100

R$NOP
R$INIT
R$READ
R$WRIT
R$COMP
R$POSI
R$ABRT
R$DIAG
R$GETS
R$SETS
R$GETC
R$SETC
f<$ENIt

O.
1.
2.

3.
4.
5.
6.
7.
S.
9.
10.
11.
.... B<01000000>

iNo-operation
;Initialize
;Read operation
;Write operation
;Compare (NOP on TU5S>
;Position operation
;Abort (NOP on TUSS)
;Diasnose
;Get status
iSet status (NOP on TUSS)
;Get characteristics
;Set characteristics (NOP on TUSS>
;*END messaSe

; END packet success codes:
000000
000001
177776
177770
177767
177765
177757
177740
177737
177720
177711

S$NORM
S$RETR
S$PART
S$UNIT
S$CART
S$WPRT
S$DCHK
S$SEEK
S$MOTR
S$OPCD
S$RECN

O.
1.
--2.

···8.
-9.
-11.
-17.
··-32.
-33.
-48.
-55.

, No rma I SIJccess
;Success but with retries
iPartial operation (end of medium)
;Invalid unit number
iNo cartridSe
iCartridSe write protected
;Data check error
;Seek error (block not found>
;Motor stopped
;Invalid operation code
;Invalid record number

MXV11 TUS8 BOOTSTRAP

MACRO V03.02B13-JUN-79 PAGE 3

DEFINITIONS AND PROTOCOL EQUATES
; RT-ll

Director~

St rlJctlJre Definltlons

3
4
c'
.J

6
7

001000
001002
001004
001006
001010

SEGALO
NXTSEG
HGHSEG
XTRBY'T
STRBLK

IHRBUF
DIRBUF+2
DIRBUF+6
DIRBUF+I0

; NIJITlber of seSITlerlts allocated
; NUITlbe r of ne:<t loSical sesment
;Hishest seSITlent in use
; NIJITIber of e:dra b~tes per entr~
;Startins blockt for files in this sesnlent

000016
000010
000400
001000
002000
004000

ENTSIZ
D.FLEN
TENTAS
EMPTY'$
PERMF$
ENDSG$

7*2
10
000400
001000
002000
004000

;Size of a director~ entr~
;Offset to file lensth irl entr~
;Flas for tentative file entr~
;Flas "for elTlpt~ area entr~
;Flas for permanent file
;Flas for end of sesment

DH~BUF+4

....L

""-I
""-I

9
10
11
...
1"
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

; RT-11

000040
000042
000044
000046
000050
000052
000053
000054
000056
000057

RT$STA
RT$ISP
RT$JSW
RT$USR
RT$HGH
RT$EMT
RTSUER
RT$RMN
RT$FCH
RT$FCT

S~stem

Communications Area Defirti tions
;Start address for program
;Initial stack pointer
;Job status word
;USR load address
;Job hish ITleITlor~ liITlit
;(B~te) EMT error code
;(B~te) User error code
jBase address of residerlt ITloni tor
;(B~te)
Console fill character
;(B~te) Console fill cOIJnt

000040
000042
000044
000046
000050
000052
000053
000054
000056
000057

; Error macro definition

.MACRO

ERROR
HALT

• IRP
.SBTTL
.SBTTL
.SBTTL
.ENDR
.ENDM

peS,\ •

TEXT

*****
***** HALT at
*****
ERROR

F'C=~F'C$

indicates

·~TEXT·

MXV11 TUS8 BOOTSTRAP

MACRO V03.02B13-JUN-79 PAGE 4

MEMORY TEST
.SBTTl

1
2
3 000000

.ASECT
.IIF NDF ORIGIN, ORIGIN=173000
.=ORIGIN

173000

5
6
7

Memory Test
;Set default origin to beginning of boot
;Origin to beginning of bootstrap ROM

Start of Memory Diagnostics

9
10 173000
11 173002
12 173004
13 173006
14
15
16
17
18
19 173010
20 173014
21 1·73016
22 173020
23 173024

...L

'""-I
00

Mnll
IIUV

BR
ClR
BR

PC,Rl
MEMSIZ
R3
MEMDO

size "leniOr'''''
;SubrolJtine call
;Set test data = 0
;Go do melTlory test
><",-

,t.JU

Memory sizing subroutine (called with R1 convention)
Sets R4 to highest writable memory address, R2=2

'">A
.:.;..,

1""77"",1

25
26
27
28
29
30
31
32
33

173032
173034
173040
173042
173044

012700
106400
000005
012702
106712
"'v ..... .::."..::.
""\-,"' .....
005004
012706
011414
005724
000775

173046
173050
173052

034442
010406
000161

.L.''';'v~Q

MEM:

010701
000402
005003
000423

000340
000006
173046
001000

000002

ClR
MOV
MOV
TST
BR

;Assure no interrupt enable on restart
; by setting priority 7
;Reset external bus
t6,R2
;R2 -) PS word in timeout vector
@R2
;Set new PS priority to 7
i2$-ORIGINt173000,-(R2) i and new PC to escape label
R4
;Set initial start address
t1000,SP
;And initial stack pointer
@R4,@R4
;Try to read and write each memory location
(R4>t
;If no trap on DATI or DATO, skip to next
1$
;And loop until timeout occurs

BIT
MOV
JMP

-(R4),-(R2)
R4,SP
2(R1)

MEMSIZ: MOV
MTPS
RESET
MOV
MFPS
MOV

;Set R4 -) highest writable adrs, R2=2
;And set stack at top of memory
;Return to caller

MXV11 TU58 BOOTSTRAP
MACRO V03.02B13-JUN-79 PAGE 5
SUBROUTINE TO WRITE, READ, AND VERIFY MEMORY
1
2
3
4

.SBTTL

Subroutine onl~ returns if no errors are detected.
The contents of R2 are destro~ed.
The test consists of a memor~ address and data storase test.
First we write all of memor~ with its address and then read
and verif~ memor~.

Memor~

CallinS Seouence:
MOV
pe,Rl
BR
MEMDO

13
14
15
16
17

Verif~

Subroutine to Write, Read, and Verif~ Memor~
Enter with:
R3
0
R4 = Hish address for verification

6
7
8
9
10
11

18 173056
19 173060
20 173062
21 173064
22 173066
23 173070
24 173072
25 173074
26
27
28
29 173076
30 173100

Subroutine to Write, Read, and

005002
010212
005722
020204
101774
024202
001401

CLR
R2
;Cop~ startinS address
MOV
R2,@R2
iStore address at address
TST
(R2)+
iAnd skip to next
CMP
R2,R4
iFinished with all addresses?
BLOS
ADDRT
i I f LOS no
CHECK: CMP
-(R2),R2
;Yes, check data
BEO
ADCONT
i I f EO, no comparison error
MEMERA: ERROR
<Hemor~ address error>
; Expected data is in R2; bad data is pointed to b~ adrs in R2.
i T~pe .p. to continue test.

005702
001373

ADCONT: TST
BNE

MEMDO:
ADDRT:

R2
CHECK

;Have we finished the check?
;If NE, no

f'iXi)1:1.

ru~)n

l-.i(J(nSn~{IF'

Mf~LfW

\,)03. 02B 13--JUN- /9 r'AGE 6

MEMORY DATA STORAGE TEST
.SBTTL

1
2
3

Memors Data Storase fest

, Memors data storase test.

4
c.;:
d

6
7
8
9
10
11
12
13
14
15
16
1"7
18
19
20
21

The steps of this test are:
1. Fill memory with zeroes.
2. Walk an all l's word throush memors & verify each location.
3. Fill memory wIth ones.
4. Walk an all O's word throush memory & verify each location.
By performlnS these steps all bit positions are checked for OIl
storaSe and the sense amps are stressed in the semiconductor memories.
173102
173104
173106
173110
17:U 12
173114
173116
173120

010322
020204
101/75
005103
074342
005112
001401

fn, (R2) t
,Move background data to melTlory
MOV
R2, F~4
,Done with desired area?
eMf'
;If LOS, no
MEMT
BLOS
WALK:
R3
; eOlTlP I ement test dat3
COM
f.:3,····(R2)
rUse background & test data to set all l's
XOf<
,Check for all l's (tests previol..Js bcks)
@R2
COM
DCONT
PIf EO, data is good
BEU
MEMERD: ERROR
<Bad melTlory data>
Expected data is in R3, bad data is pointed to by adrs In R2.
j
Type -p. to contlnue test.

005103
074312
005702
001367

DCONT:

:22

...

00
0

23
24 173122
25 173124
26 173126
2J 173130
28
29
30
31

MEMT:

COM
XOR
TST
BNE

R3
R3,@R2
R2
WALK

;Get previous background data
;Restore background data for current location
,Done with one pass?
,If NE, no

At this point, the pattern has been walked through all of memory.
Go back through examining background data to make sure it was not
effected by modification of other locations.

~~2

,53 173132
34 173134
35 173136
36
Tl 173140
38 1"73142
39 173144
40 173146
41 1 J31::'iO
42 173152

020322
001401

BACK:

CMF'
BEC~

MEMERB: ERROR
020204
1017/3
005002
OO::'j103
001354
000411

BGCON,.: CMF'

BLOS
CLR
COM
BNE
BR

R3, (fU)t
,Is backsrol..Jnd still valid?
,If £(~ , yes
BGCONT
<Memory background data error>
R2,R4
BACK
R2
R3
MEMT
BOOT

, f.kanned all of background yet?
no ... continue with ne!·~t word
;Else restore F'"
to low memory Ii/TIlt
\"""
,FIlP t.·o other pattern
d f NE, test not cOlTlPlete yet
;Go I~.ick the boot

; I f LOSt

MXV11 TUSS BOOTSTRAP
MACRO V03.02B13-JUN-19 PAGE 7
MACRO, FORTRAN-CALLABLE LOADER ENTRY
.SBTTl

MACRO, FORTRAN-Callable loader Entrw

The followins entr~ point, callable froffi MACRO or FORTRAN prOSrams,
will autoload and start an executable file whose naffie is specified
bw the FORTRAN-stwle arSuffient list pointed to bw R5.

4
1,;;"

6
7
8

.IRP PC$,\.
.SBrTl
.SBrTl *----) TUlOAD entrw point is at address 'PC$
.SBrTl
.ENDR

10
11
12
13
14
15
16
17
18

173154
173154
173156
173160
173164
173166
19 173170
20 173172
21 173174

TULOAD::
010701
000714
016505
012514
012522
012522
011512
000446

000002

MOV
DR
MOV
MOV
MOV
MOV
MOV

PC,R1
MEMSIZ
2(R5),R5
(R5)t,@R4
(R5)t,(R2>t
(R5)t,(R2)t
@R5,@R2
STANDS

; SIJbrolJtine call
; to size II'JelTlorw
;R5 -) four element arraw
;Set unit. on top of new stack
;Copw filename.ext
; in RAD50 to locations
; 2,4, and 6 of memorw
;And so load file

MXVll TUS8 BOOTSTRAP
BOOTSTRAP TUSS

MACRO V03.02B13-JUN-79 PAGE 8

1
2

3
4 173176
5 173202
6 173204
7 173206
8 173212
9 173214
10 173216
11 173220
12 173222
13 173224
14 173226
15 173230
16 173234
17 173236
18 173242
19
20
21
22 173244
23 173246
24 173250
25 173250

26 173252
27 173256
28 173262
29 173264
30 173270
31 173272
32 173274
33
34 173276
35 173276
36 173302
37 173304
38 173310
39
40 173312

012701
005303
005211
004767
105711
100376
005011
012703
004
004715
005741
105737
100375
121127
001075

176504

BOOT:

000514

004
176500
000020

.SBTTL

Bootstrap rU58

.ENABL
MOV
DEC
INC
CALL
TSTB
BF'L
CLR

LSB
tTO$CSR,R1
R3
@R1
CB80UT
@R1
1$
@Rl

MOV

(PC>t,R3

;Rl -) output CSR for TUSS serial line
;Set R3 - 177777 (Two RUBOUT characters)
;Start transmittin~ BREAK to TU58
iSend eight RUBOUTs
;Is transmitter read~ again ~et?
;If f'L no -. wait
;Else stop sending BREAK now
~Get two INIT commands for TU58

.BYTE
CALL
TST
TSTB
BF'L
CMPB
BNE

R$$INT,R$$INT
@R5
-(R1)
@tTI$CSR
2$
@R1,tR$$CON
LOIJERR

;And transmit them
;Dump an~ ~arbage char in TI$BUF
;Is a character available from the TU58?
;If PL, no - wait in loop
;If so, was it a CONTINUE flag?
;If NE, no - ERROR

TU58 is now initialized.
005416
000316

005000
012701
004767
100005
120027
001766

001000
000230
177767

000641
021527
001475
022527
001356

NEG
3$:
SWAB
REBOOT:
eLk
MOV
CALL
BF'L
CMf'B
BEO
ERROR
BR
CLR
CMF'
BEO
CMf'
BNE
.DSABL

000240
000260
STANDB:

Prepare to read block to.

@Sf'
@SF'

;Set unit=l in low b~te, unit=O in high
; Swi tch I.lrli ts
;Reference label for retries
RO
;Block number = 0
t512. ,R1
;B~te count = one block
;Attempt to read the block
REAIJZU
5$
;If F'L, read was succes~ful
RO,tS$CART
;IJid it fail because no ca~tridge present?
3$
;If EO ~es - ~o tr~ other drive
<Controller error - success code in RO low b~te>
MEM
;F'roceed will restart memor~ test
R5
@R5,t240
START
(R5)t,t260
3$
LSB

;f'oint to address 0 (after REAIJ, R5=0)
;Did we read a valid bootstrap block?
;Go start exebution (Note: R5 = 0 here!!!)
;Is this a stand-alone load tape?
;If NE no - tr~ to boot other unit

MXV11 rUSB BOOTSTRAP
MACRO V03.02B13-JUN-79 PAGE 9
STAND-ALONE FILE LOADER
.SBTTL

1
;.5

;

Stand-Alone File Loader

fhis routine loads stand-alone prosrams (assumed to be In RT-11 .SAV
file format) from an RT-11 file structured TU58 cartridse.
It is
invoked if the first word in block 0 of the cartridSe is a 260.

7 173312

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41

173316
173320
1'73322
173326
173332
173336
173340
173344
173346
173350
173354
173356
173362
173364
173370
173372
173374

012700
006300
022020
012701
012704
004767
100437
012704
012400
010403
022724
001410
022744
001015
013700
001352

000001
002000
001000
000156
001010
002000
004000
001002

000776

173376
173402
173404
173406
173410
173412
173414
173416
173420
173424
173426
173430
173434

012705
022425
001004
022425
001002
022425
001413
010304
062704
062400
022424
063704
000744

173436
173440

000167

000002

STANDB: MOV
1$:
ASL
CMF'
MOV
MOV
CALL
BMI
MOV
MOV
2$:
MOV
eMf='
BEQ
eMF'
BNE
MOV
BNE
3$:
ERROR
BR

tl,RO
;5et director~ seSment tl
RO
iTwo blocks per sesment
(RO)t,(RO>t
;Add 4 to RO, as director~ starts in blockt6
tl024.,Rl
;F'repare to read two blocks
tDIRBUF,R4
;Into the director~ buffer
READU
;Read the seSment
LODERR
;If MI, read was unsuccessful
tSTRBLK,R4
;Else prepare to pick UP startins block
(R4)t,RO
iRO = startins block for files
R4,R3
;Save pointer to current entr~
tPERMF$,(R4>t
;Is this a permanent file?
4$
iIf EQ, ~es - So check if it matches
tENDSG$,-(R4)
;Else 1S this the end-of-sesment marker?
5$
iIf NE, no - so skip this entr~
@tNXTSEG,RO
;Else set number of next sesment
1$
iIf NE, there is one - So read it
<Desired file was not found>
3$
;Cannot continue!

4$:

MOV
CMF'
BNE
CMF'
BNE
eMP

5$!

MOV
ADD
ADD
CMF'
ADD
BR

tFILNAM,R5
(R4)"t, (R5)t
5$
(R4)t,(R5)t
5$
(R4>t,(R5>t
LOAD
R3,R4
tD.FLEN,R4
(R4)t,RO
(R4)t,(R4>t
@:l:XTRBYT,R4
2$

B[(~

000010
001006

177334

LODERR! ERROR
JMF'

;Point to RAD50 name of desired file
;Check file name, first word
ilf NE not desired file
; ••• Check second word of filename
iIf NE not desired one
i ••• Finall~, check extension
;If EQ, sot it - ~o load this one into
;Get entr~ pointer back
iAdvance to file size of entr~
;Update current file base
;And skip to next file entr~
iPlus an~ extra b~tes in each entr~
iContinue file search

<Protocol error in READ operation>
MEM
iIf PROCEED, tr~ asain

memor~

MXV11 TUS8 BOOTSTRAF'
MACRO V03.02B13-JUN-79 PAGE 10
L.OAD STAND-ALONE PROGRAM FILE
1
2
3 173444
4 173446
0::173450
.J
6 173452
7 173456
8 173460
9 173464
10 173470
11 173472
12 173474
13
14 173476
15 173500
16 173504
17 173510

011401
000301
006301
004767
100767
013705
032705
001402

LOAD:
000034
000040
000001
1$:

000776
112600
012701
013706
000115

START:
176500
000042

.SBTTL

Load Stand-Alone ProSram File

MOV
SWAB
ASL
CALL
BMI
MOV
BIT
BEQ
ERROR
BR

@R4,Rl
;Rl = size of file in blocks
;
Rl
256. = word cOI.mt
;
Rl
2 = bl::lte cOI.mt
;Read the prosram file into memorl::l
READZU
jlf MI, error in read
LODERR
;Get proSrall1 start adrs
@tRT$STA,R5
;Is adrs ever,,?
t1,R5
START
nf EQ \:Ies - oka\:l
<Start address invalid>
1$
;Cannot continlJe from here

MOVB
MOV
MOV
JMP

(SP)t,RO
tTI$CSR,Rl
@tRT$ISP,SF'
@R5

iGet unit n'Jmber booted
;Pass the CSR address
;Load proSram1s stack pointer
;Go start proSram e~<ecution

MXV11 TUS8 BOOTSTRAP
MACRO V03.02B13-JUN-79 PAGE 11
START READ OPERATION ON TU58

00
01

1
2
3
4
5
6
7
8
9
10
11
1'")
...
13
14
15 173512
16 173514
17 173520
18 173522
19 173524
20 173530
21 173534
22 173540
23 173542
24 173544
25 173546
26 173550
27 173552
28 173554
29 173556
30 173560
31 173562
32 173564

.SBTTL

Start READ Operation on TU58

Starts a read operation on the rU58

transmittin~

a command packet

InplJts:
RO
startin~ block t for transfer
b~te count for transfer
R1
unit nlJlflber
R2
R4
address of buffer to receive data
OutPIJtS:
RO, R1, R2 unchansed
Destro~s:

R3, R4, R5
005004
116602
010446
005004
012703
004767
012703
004715
010203
004715
005003
004715
010103
004715
010003
004715
010403
004715

000002
005002
000176
000002

READZU: CLR
READU: MOVB
READ:
MOV
CLR
MOV
CALL
MOV
CALL
MOV
CALL
CLR
CALL
MOV
CALL
MOV
CALL
MOV
CALL

R4
;Set buffer address = 000000
2(SP),R2
;And set unit number from stack
R4,-(SP)
;Save buffer address
R4
;Init checksum
t10.*400+R$$CTL,R3 ;Set command flaS and lensth
CH20UT
;Output two chars and set R5
tR$READ,R3
;Send read command and modifier=O
@R5
R2,R3
;Then unit number and switches=O
@R5
R3
;Plus a zero seouence number
@R5
Rl,R3
;Followed b~ the b~te count
@R5
RO,R3
;And the block number
@R5
R4,R3
;Finall~, transmit the checksum
@R5

MACRO V03. 02B 13-..)UN--79 PAGE 12
i"1XV11 TU58 BOOTSTRAP
START r;:EAD OPERATION ON TU58
1
2
3
4
5
6
7
8
9

.....

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
4""43
44

Now ready to accept data messages frolT, the TU58
173566

012600

173570
173572
173576
173602
173604
173606
173610
173612
173614
173616
173622
173624
173626
173632
173634
173636
173642
173646
173652
173654
173656
173662
173666
173670

006001
004767
122703
001017
105003
000303
106003
160301
010305
004767
010320
077504
004767
005701
001356
004767
004767
122703
001271
010300
004767
004767
000300
000207

173672
173676
173700
173702

004767
020403
001256
000207

173704
173706
173710
173712
173714
173720
173722
173724

000106
000001

1$:

MOV
CLC
ROR
CALL
CMF'B
BNE

000072

2$:

000040
000042
000046

3$:

CLRB
SWAB
RORB
SUB
MOV
CALL
MOV
SOB
CALL
TST
BNE
CALL
CALL

vvv.£.vv

CMPB

000026
000004

BNE
MOV
CALL
CALL
SWAB
RETURN

~~~"I'\~

(SP)t,RO
Rl
5$
tR$$DAT,R3
3$
R3
R3
R3
R3, f~l
R3,R5
7$
R3,(RO)t
R5,2$
4$
Rl
1$
5$
7$
iR$ENIt,R3
LODERR
R3,RO
6$
4$
RO

jRO ..- ~> data ()lJffe r
, (CH20U'f leaves C clear)
;Rl = word count for transfer
jGet first word of packet
;Is this indeed a data messaste?
jlf NE no - /TIay be END lTIessaste
jElse clear flags
,Move pacil..et byte co'-,nt to low b!:lte
;And convert to word co'-,nt
;Remove from transfer co'-,nt
,And COpy for loop co'-,nter
;Get ne~·~t two words
,Store in buffer
jLoop for entire data messaste
;Get checv-.sum and compare
,Have all data records been transferred?
,If NE no
,And stet prospective END packet start
;Get opcode/s'-,ccess b!:ltes of END packet
;Is this an END packet?
,If NE no -. abort transfer
,Save s'-,ccess code in RO
;Read relT.ainder of ENIt packet
;And check its checksum
,Set CC's on sl-,ccess code of transfer
;Return to caller

4$:

CALL
CMF'
BNE
RETURN

CH2IN
R4,R3
LODERR

;Get two checks'-'ITI b!:ltes
,Does it match calcl-'1 ated value?
;If NE no - ERROR
,Else return with success

005004
000402

5$:

CLR
DR

R4
7$

;Init checv-.slJm
,And set the first word

004717
004717
004767
060304
005504
000207

6$:

CALL
CALL
CALL
ADD
ADC
RETURN

@PC
@F'C
CH2IN
R3,R4
R4

,Read 4 words

000060

000036

7$:

;Read ne~·~t two b!:ltes
,Add into checksl-'ITI
; with end-aro'-,nd carr!:l
;And back to caller

MXV11 rUS8 BOOTSTRAP
MACRO V03.02B13-JUN-79 PAGE 13
TU58 INTERFACE JIO ROUTINES
1

.SBTTL

TU58 Interface 110 ROl-ltines

2
3

CH20UT --- Write two bytes to the TUS8

4
"'6

Writes two bytes to interface and updates checkslJlll.

InPI-lts!
R3
two bytes to be OI-ltPIJt; low byte first
R4
current checkslJm word
OIJtputS:
R3 unchansed
R4 updated to new checksum
R5 pointins to CH20UT routine for easier futlJre CALLs

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

173726
173730
173732
173734
173736
173740
173742
173746
173750
173754

004717
004717
010705
060304
005504
004717
105737
100375
110337
000407

176504
176506

CH80UT: CALL
CALL
CH20UT: MOV
ADD
ADC
CALL
1$:
TSTB
Bf'L
MOVB
BR

@F'C
@F'C
f'C,R5
R3,R4
R4
@f'C
@tTO$CSR
1$
R3,@tTO$BFR
CHRET

;Entry point to OIJtP/Jt 8 characters
;Set R5 to followins rOIJtine adrs
;Update checksum word
; with end--a round carry
;Repeat for both characters
Hs interface ready for OIJtput?
;If f'L no - wait
;Else transmit character to TU58
;Merse with other rOIJtine to retl-lrn

'")c"
.:..~

.....
(X)
~

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

CH2IN
CHIN

Read two bytes from the TU58
Read a sinsle byte from the TU58

Inputs:
none.
OIJtPUtS!
R3 = character(s) read
173756
173760
173762
173766
173770
173774
173776

004717
105003
105737
100375
153703
000303
000207

176500

CH2IN:
CHIN:
1$:

176502
CHRET:

CALL
CLRB
TSTB
BF'L
BISB
SWAB
RETURN

@F'C
R3
@tTI$CSR
1$
@tTI$BFR,R3
R3

;Read two, not one
;And zero OIJt space for new one
;Is a character available?
Hf PL no
;Else set into resister
;Move clJrrent character over
;And retlJrn to caller

MXVll TU58 BOOTSTRAP
MACRO V03.02B13-JUN-79 PAGE 14
TU58 INTERFACE I/O ROUTINES
26

000001

.END

i"1XV11 TU58 BOOTSTRAP
SYMBOL TABLE

MACRO V03.02B13-JUN-79 PAGE 14-1

ADCONT
ADDRT
BACK
BGCONT
BOOT
CHECK
CHIN
CHRET
CH2IN
CH20UT
CHaOUT
DCONT
DIRBUF=
D.FLEN=
EMPTY$=
ENDSG$=
ENTSIZ=
FILNAM=

HGI-ISEG=
L.OAD
LODERR
MEM
MEMDO
MEMERA
MEMERB
MEMERII
MEMSIZ
MEMT
NXTSEG=
ORIGIN=
PERMF$=
READ
READU
READZU
REBOOT

173076
173060
173132
173140
173176
173070
173760
173774
173756
173732
173726
173122
001000
000010
001000
004000
000016
000002

ABS •

174000
000000
ERRORS DETECTED:

001004
173444
173436
173000
173056
173074
173136
173120
173010
173102
001002
173000
002000
173520
173514
173512
173250

000
001
0

( 7 PAGES)
1639 WORDS
VIRTUAL MEMORY USED:
DYNAMIC MEMORY AVAILABLE FOR 47 PAGES
,LP:TU5aBT=DK:TU5aBT/C

...L

(X)

RT$EMT= 000052
RT$FCH= 000056
RT$FCT= 000057
RT$HGH= 000050
RT$ISF'= 000042
RT$JSW= 000044
RT$RMN= 000054
RT$STA= 000040
RT$UER= 000053
RT$USR= 000046
R$ABRT= 000006
R$COMF'= 000004
R$ItIAG= 000007
R$END = 000100
R$GETC= 000012
R$GETS= 000010
R$INIT= 000001

R$NOF' ==
f':$POSI==
R$REAIt=
f<$SETC=
R$SETS=
R$WRIT=
R$$CON=
R$$CTL.=
R$$DAT=
R$$INT=
R$$XOF=
SEGALO=
STANDI{
START
STRBLK=
S$CART=
S$DCHK=

000000
000005
000002
00001.3
000011
000003
000020
000002
000001
000004
000023
001000
173312
173476
001010
177767
177757

S$MOTR=
S$NORM=
S$OPCD=
S$PART=
S$RECN=
S$RETR=
S$SEEK=
S$UNIT=
S$WF'RT=
TENTAS=
TI$BFR=
TI$CSR=
TO$BFR=
TOSCSR=
TULOAD
WALK
XTRBYT=

177737
000000
177720
177776
177711
000001
177740
177770
177765
000400
176502
176500
176506
176504
173154 G
173110
001006

UNIVERSAL DISK BOOTSTRAP
TABLE OF CONTENTS
:~-

44-

a::-

5667-

20
1
47
1

1
1

10-

-L

..;-

MACRO V03.02B13-JUN-79

Controller Definitions
Test
>. HALl AT PC:: J. 73056 INDICATES "MEMORY ADDRESS ERROR"
Melflor~ Data Storage Test
_.. _---). HALT AT f'C=173102 INDICATES -BAD MEMORY DATA·
RLOl Bootstrap
------ ~> HALT AT f'C=173270 INDICATES "RL BOOT FAILURE·
RK05 Bootstrap
MRV11--C Bootstrap
RX01/RX02 Bootstrap
Miscellaneous Subroutines
MelTlor~
_ _ 0. _ _ _ . _ . -

UNIVERSAL DISK BOOTSTRAP

MACRO V03.02B13-JUN-79 PAGE
• TITLE
.ENABL

2
3

UNIVERSAL DISK BOOTSTRAP
LC

Edit level 08 made 01-Mar-79

RRB

6
7

October 1978 b~ RRB
(C) 1978
b~ Disital Eaui~ment
Co~~risht

Cor~oration,

Ma~nard,

Massachusetts 01754

9
10
11

12
13
14
15
16
17
18
19
20
21
22

CO
~

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37

000000

.REF'T

This is a 256 word bootstra~ ~rOSram desiSned to handle all disks which are
available for the LSI-ll bus.
It will automaticall~ search for controllers
for the various disks (in a ~redefined order) and bootstra~ the first such
device which is found and is o~erable.
The

bootstra~

Size read/write memor~, to a maximum of 30K words.

Perform a memor~ addressinS test, writins each location with its address
and verif~ins the contents.

Exercise memor~ data storaSe ca~abilities, movins a l's ~attern throush a
backS round of O's and a O's ~attern throush a backS round of l's, to test
all read/write memor~ locations for inde~endence and retention.

Check for

Attem~t to bootstra~ RLOl unit to.
If there is no such drive,
or if no cartridSe is present, the cover is o~en, or the drive is spinnins
down, proceed to Ste~ t6.

Check for

Attem~t

Check for presence of RXVll or RXV21 controller in the
exists, ~roceed to Step tl0.

Wait for min. 2 seconds to allow drive spin-uP, then attempt to
bootstra~ unit 0 of the flopp~ disk, at the densit~ of the media
present in the drive at the time. If the drive is not read~ or does not
contain a bootable medium, so to the other unit and tr~ it. Continue
loo~inS between units 0 and 1 until one is found to bootstra~.

40
41
42
43
44
45
46
47
48
49
50
51
52
53

54
55
56
5'

seauence is as follows:

~resence

of RLV11 controller. If not found,

~roceed

to Step t6.

of RKV11 controller. If not found, proceed to Step tS.

to bootstra~ each RK05 unit in seQuence (0,1, ••• ,7) until a unit
is found ~hich is read~ and readable. If no such unit exists, ~roceed to
Ste~ t8.
(This ste~ is ~receeded b~ a min. 8 second wait loo~ to allow
sufficient s~in-u~ time.)
s~stem.

10. Check for the ~resence of an MRV11-C board with ~asinS enabled.
found, ~roceed to step t4.

If none

If not

11. Load the first 256 words from the MRVll-C into memor~ and execute them,
if the first word is NOP (000240). Else proceed to ste~ t4.

UNIVERSAL DISK BOOTSTRAP
CONTROLLER DEFINITIONS

MACRO V03.02B13-JUN-79 PAGE 2
.SBTTL

2
3
4
5
6
7
8

; RLOI (RLVll)
174400
174402
174404
174406

RLCS=
RLBA=
RLDA=
RLMF'=

Controller Definitions
Re~ister

174400
RLCS+2
RLBA+2
RLDA+2

Definitions
;Control and Status
;Bus Address
;IIisk Address
;Multipurpose Re~ister

....L

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3i
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

; RLOl Function IIefinitions
000000
000002
000004
000006
000010
000012
000014
000016

RL$NOF'=
RL$WCK=
RL$GST=
RL$SEK=
RL$RHII=
RL$WII=
RL$RD=
RL$RDN=

0*2
1*2
2*2
3*2
4*2
5*2
6*2
7*2

;No-Operation <Maintenance on RLVll)
;Write Check
;Get StatlJs (and Reset)
;Seek C~linder and Select Head
;Read Header
;Write Data
;Read Data
;Read Data With No Header Check

; RL01 Miscellaneous IIefinitions
000001
000013
177730
000006
000177

RL$$IIR=
RLG$RS=
RL$$ER=
RLE$UH=
RL$$CA=

000001
000013
~C<000047>

6
"'C<177600>

j IDrive Read~1 bit ir. RLCS
;Reset and Get status for RLDA in RL$GST
jMask for Cover Open and State in error bits
jlUnload Heads l in State info
jMasl'-. for c~linder address in header data

j RK05 (RKV11) Controller
177400
177402
177404
177406
177410
177412
177416

RKIIS=
RKER=
RKCS=
RKWC=
RKBA=
RKDA=
RKIIB=

177400
1.77402
177404
177406
177410
177412
177416

Re~isters

;IIrive Status
;Error
;Control and Status
;Word Count
;Bus Address
Hlisk Address
;IIata BIJffer

; RK05 (RKV11) FIJoction Codes (plus GO bit)

000001
000003
000005
000007
000011
000013
000015
000017

RK$CRS=
RK$WRT=
RK$REII=
RK$WCK=
RK$SEK=
RK$RCK=
RK$DRS=
RK$WLK=

0*2+1
1*2+1
2*2+1
3*2+1
4*2+1
5*2+1
6*2+1
7*2+1

;Control Reset
;Write
;Read
;Write Check
;Seek
;Read Cheer..
;Drive Reset
;Write Lock

UNIVERSAL DIS"': BOOTSTF.:AP

MAC~O

V03.02B13-JUN-79 PAGE 3

CONTROLLER DEFINITIONS
; RXOI/RX02 (RXVll,RXV21) Register Definitions
2
3

4
5

177170
177172

10
11

12
13
14
15
16
17
18

19
20
21

177170
RXCSt2

~Control and Status
• Data BIJffe r

• RX Control and Status Bits

7
8
9

RXCS=
RXDB=

100000
040000
030000
004000
003000
000400
000200
000100
000040
000020
000016
000001

RX$$ER= 100000
RX$$IN= 040000
RX$$XA= 030000
RX$$02= 004000
RX$$XX= 003000
RX$$DE= 000400
RX$$TR= 000200
RXSSIE= 000100
RX$$[iN= 000040
RX$SUN= 000020
RXS$FN= 000016
RX$SGO= 000001

; Error
;Initialize controller
,Extended address bits
;1 if RX02 or RX03; 0 if RX01
;Unused bits
;Densit~ (l=double,O=sinSle)
;Transfer function
,Interrupt enable
;Done
,Unit select
;Function select
;GO

; RX Function Codes (in RX$$FN) with GO bit preset

23
24
25
26
27
28
29
30
31
32

000001
000003
000005
000007
000011
000013
000015
000017

RXSFIL= 0*2+RX$SGO
RX$EMP= 1*2+RXS$GO
RX$WRT= 2*2+RX$$GO
RX$RED= 3*2+RX$$GO
RX$STD= 4*2+RX$$GO
RX$RST= 5*2tRX$$GO
RX$WDD= 6*2+RXs,s,GO
RX$REC= 7*2+RX$$GO

,Fill blJffer
; Enlpt~ buffer
;Write sector
,Read sector
;Set media densit~
;Read status
;Write sector with deleted data
;Read error code

; RX Error Codes

34
35
36
37
38

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55

000400
000200
000100
000040
000020
000004
000001

RXESUN=
RXESDR=
RXESDD=
RXESDN==
RXE$DE=
RXESID=
RXESCR=

000400
000200
000100
000040
000020
000004
000001

;Unit selected
;Drive read~
;Deleted data
;Drive densit~
;Densit~ error
;Initialize done
,CRC error

; MRVI1-C Paged ROM Board Definitions
177000
160000

MRSCSR= 177000
MRSWIN= 160000

;Default paging control CSR address
'Default page· window base address

; Miscellaneous Definitions
000010
004000

RETRY=
STACK::::

8.
4000

.MACRO

ERROR
TEXT
HALT
PCS,\ •
-----) HALl AT PC='PCS INDICATES ·'TEXT"

.IRF'

• SBTTL
.[NDR

r:"'r",r".r'lr:.

L..f\f\lJI"'

iNumber of retries
;Default stack pointer for bootstraps

UNIVERSAL DISK BOOTSTRAP
MEMORY TEST

...L

<0
~

.1
2
3 000000
4
5
6
7
8
9
10 173000
11 173004
12 173006
13 173010
14 173012
15 173014
16 173020
17 173022
18 173024
19 173026
20 173030
21
22 173032
23 173034
24
25
26
27
28
29
30
31
32
33
34
35 173036
36 173040
37 173042
38 173044
39 173046
40 173050
41 173052
42 173054
43
44
45
46 173056
47 173060

MACRO V03.02B13-JUN-J9 PAGE 4
.SPTTl

Memcr~

Test

.ASECT
.IIF NDF ORIGIN, ORIGIN=173000
.=ORIGIN

173000

;Default assembly base is boot ROM area
;Origin to beginning of bootstrap ROM

Start of Memory Diagnostics
012700
106400
000005
111701
005004
012721
010011
011706
011414
005724
000775

000340

ME:M:

173032

005744
005003

MOV
MTPS
RESET
MOVB
CLR
MOV
MOV
MOV
MOV
TST
BR

;Assure that interrupts are disabled
; by setting priority to PR7
;Reset ~ll devices (assert BINIT)
@PC,Rl
;Set Rl=4
Depends on CLR R4 following!
R4
;Set initial address for sizing
t2$tI73000-MEM,(Rl)t ;Set timeout trap to go to 2$
RO,@Rl
; at priority 7
@PC,SP
;And set stack to 011414
Depends on
@R4,@R4
;Size writable memory
this seauence!
(R4>t
;If no trap on DATI or DATO, skip to next adrs
1$
;Loop until timeout occurs

TST
CLR

-(R4)
R3

*340,RO

****

*****
*****

;R4 -) highest writable memory address
;Clear initial memory test data

Subroutine to Write, Read, and Verify Memory
Enter with:
R3
0
R4 = High address for verification
The contents of R2 are destroYed.
The test consists of a memory address and data storage test.
First we write all of memory with its address and then read
and verify memory.
005002
010212
005722
020204
101774
024202
001401

;COPy starting address
CLR
R2
R2,@R2
;Store address at address
MOV
(R2)t
;Update to ne~{t word address
TST
R2,R4
CMP
;Finished with all addresses?
;If LOS no
BLOS
ADDRT
-(R2),R2
;Yes, check data
CHECK: eMP
BEQ
;If EQ, no cOlTlParison error
ADCONT
<MelTlory address error>
MEMERA: ERROR
; E~·~pected data is in R'I· bad data is pointed to by adrs in R2.
; T~pe apa to continue test.
MEMDO:
ADDRT:

005·702
001373

ADCONT: TST
BNE

p")
\..:..

CHECK

jHave we finished the check?
;If NE, no

UNIVERSAL DISK BOOTSTRAP
MEMORY DATA STORAGE TEST
1
2
3
4

.SBTTL
Memor~

...I.

(J'1

Memor~

Data Storase Test

data storase test.

The
1.
2.
3.
4.

steps of this test are:
Fill memor~ with zeroes.
Walk an all l's word throush memor~ & verif~ each location.
Fill memor~ with ones.
Walk an all O's word throush memor~ & verif~ each location.
B~ performins these steps all bit positions are checked for 011
storaSe and the sense amps are stressed in the semiconductor .emories.

6
7
8
9
10
11
12
13 173062
14 173064
15 173066
16 173070
17 173072
18 173074
19 173076
20 173100
21
22
23
24 173102
25 173104
26 173106
27 173110
28 173112
29 173114
30 173116
31
32 173120

MACRO V03.02B13-JUN-J9 PAGE 5

R3,(R2)t
;Move backS rOIJnd data to memor~
R2,R4
;Done with desired area1
;If LOS, no
MEMT
WALK:
; COIIIP I ement test data
R3
R3,-(R2)
;Load test data in .. emor~ location @(R2-2)
@R2
;Checl'-. for correct data
BE(~
,IfElh data is sood
ItCONT
MEMER[I: ERROR
<Bad merrlor~ data>
Expected data is in R3; bad data is pointed to b~ adrs in R2.
; T~pe • F' • to continl..Je test.

010322
020204
101775
005103
074342
005112
001401

MEMT:

MOV
CMF'
BLOS
COM
XOR
COM

005103
074312
005702
001367
005103
001362
010406

[lCONT:

COM
XOFi:
TST
BNE
COM
BNE
MOV
BR

;
RLBOOT:

R3
Fi:3,@R2
R2
WALK
R3
MEMT
R4,Sf'
RLBOOT

;Get previous backsrol..Jnd data
;Restore backS round data for current location
; [lone with one pass1
;If NE, no
;Flip to other pattern
jlf NE, test not complete ~et
;Set stack to top of writable memor~

UNIVERSAL DISK BOOTSTRAP

MACRO V03.02B13-JUN-79 PAGE 6

RLOl BOOTSTRAP
.SBTTL

RL01 Bootstrap

2
The following routine will bootstrap unit to of the RLOl disk
sYstem, if a cartridge is present.

3
4

6 173120
7 173124
8 173126
9 173130
10 173134
11 173140
12 173144
13 173150
14 173152
15 173156
16 173160
17 173164
18 173170
19 173172
20 173176
21 173200
22
23 173202
24 173204

004567
173300
174400
012702
012700
012720
004567
000004
032711
001011
016103
042703
001443
022703
101440
000755

000574

""
.... "r.....,
VJ.J.vv.;)

26 173210
27 173214
28 173216
29 173220
30 173222
31 173224
32 173230
33 173232
34 173236
35 173240
36 173242
37
38 173244
39 173246
40 173250
41 173254
42 173256
43 173260
44
45 173262
46 173264
47 173266
48 173270
49
50 173272
51 173274
52
53 173300

042703
005203
010340
004514
000006
005037
005020
012710
004514
000014
000413
010704
012511
032711
001775
100401
000205

000010
174404
000013
000074

1$:

R5,@R4
RL$RHD

.WORD
MOV
MOV
MOV
JSR
.WOFW

000001
000006
177730
000006

2$:

BIC
INC
MOV
JSR
.WORD
CLR
CLR
MOV
JSR
.WORD
BR

tRL$$CA,R3
R3
R3,-(RO)
R5,@R4
RL$SEK
@tRLBA
(RO)t
t-256.,@RO
R5,@R4
RL$RD
6$

;Start read header operation
; to get current head position
;Get disk address info from RLMP
;Clear all but cylinder address
;Set for seek function
;Place cylinder offset in RLDA
;60 do seek operation
; to cylinder 0, head 0
;Prepare to read into location 0
i from Cyl 0 head 0 sector 0
; for 256. words
;Start read operation
; for first block of data
;And gO check for valid boot

MOV
MOV
BIT
BEG
BMI
RTS

PC, f<4
(R5)t,@Rl
t100200,@Rl
4$
5$
R5

;Make subseauent calls easier
;Start operation on RL
;Wait for done or error
i I f EO, neither set yet
;If MI, an error occurred
;Else return

TST
GOB
ERROR
BR

(SP)t
;Dump return address
R2,1$
;And retrY operation
(RL Boot Failure)
RLBOOT
;Proceed will restart RL bootstrap

CLR
JSR

RO
R5,CHK240

11..","'11

nuv

000177

174402
177400

100200

005726
077255
000713
005000
004567

JSR
.WORD

.WOFW

004514
000010

25 173206

BIT
BNE
MOV
BIC
BEG
CMf'
BLOS
BR

R5,SETT4
;Set timeout trap to start
RKBOOT-MEMt173000 ; RK05 boot if RL is not present,
RLCS
; And load RLCS adrs into Rl
tRETRY,R2
;R2 = total retrY count for all errors
tRLDA,RO
;RO -) RLDA register
tRL6$RS,(RO>t
;Set reset and get status code in RLDA
R5,3$
;And gO start
RL$GST
; a get status operation
tRL$$DR,@Rl
;Is drive readY?
2$
;If NE, yes
6(Rl),R3
;Else get error status
tRL$$ER,R3
;Clear all but state and cover open info
RKBOOT
iIf EO, no cartridge is present
tRLE$UH,R3
;Unload heads, spin down, or cover open?
RKBOOT
;If LOS yes - gO try RK05
1$
;Else wait for drive ready

RLBOOT: JSR

6$:
000406
RKB001:

;Set unit 0
;Check for valid secondary boot,

UNIVERSAL DISK BOOTSTRAP
RKOS BOOTSTRAP
1
2
3
4
S
6 173300
7 173304
8 173306
9 173310
10 173314
11 173316
1"> 173322
13 173324
14 173326
15 173332
16 173336
17 173342
18 173344
19 173346
20 173352
21 173354
22 173356
23 173362
24 173364
25
26 173366
27 173370
28 173372
29 173374
30 173376
31 173400
32 173404
~

CO
-...J

MACRO V03.02B13- ..JUN-79 PAGE 7
.58TTL

RKOS Bootstrap

The following rOIJtine will bootstrap the lowes t--nIJRlbe r RI\0S unit which is
read~ and operational.
If none are found, it will proceed to the RX boot.
004567
173442
177412
004567
005003
012701
010311
005041
012741
012741
032711
001775
100010
012711
105711
100376
062703
103355
000426
010300
006300
006100
006100
006100
004567
000764

000414
000430
177412
177400
000005
100200

BPL
MOV
TSTB
BF'L
ADD
BCC
BR

R5,SETT4
;Set UP timeolJt trap to start
RXBOOT-MEMt173000 ; if RK05 is not present, and
preload RKDA into Rl
RKDA
;If RKVll present, dela\:J 8 seconds for sp inlJp
R5,l)ELAY4
;Initialize unit nUllIber word
R3
,Prepare to load registers
tRKDA,Rl
R3,@Rl
;Set IJnit t and disk address
-(RU
; BIJS address = 000000
t-256.,-(R1)
;Word COlJnt = 256.
tRK$REIt,-(Rl)
;Start read operation
tl00200,@R1
;Wait for error or done
;If EQ, neither set ~et
2$
5$
;If PL, operation successflJl
jElse reset controller
tRK$CRS,@R1
;Wait for done
@R1
;If PL, not done \:Jet
3$
; BIJmp IJnit selected
t020000,R3
1$
;And gO tr\:J ne~{t IJnit
;Else tr\:J floppies
RXBOOT

MOV
ASL
ROL
ROL
ROL
JSR
BR

R3,RO
RO
RO
RO
RO
R5,CHK240
4$

RKBOOT: JSR
.WORD
.WORD
JSR
eL.R
1$:
MOV
MOV
CLR
MOV
MOV
2$:
BIT
BE(~

000001
3$:
020000

4$:

5$:

000302

;COP\:J CIJrrent unit t
;Shift unit t down
; for secondar\:J bootstrap
;Check for valid secondar\:J boot
;If failure, tr\:J next unit

UNIVERSAL DISK BOOTSTRAP
MRV11-C BOOTSTRAP

MACRO v03.b2B13-JUN-/9 PAGE 8

1
2

.SBTTL

MRV11-C Bootstrap

The following routine loads the first 256 words stored on an MRVI1-C

ROM ooard into low memors and executes them, if the first word

NOP (i.e., follows PDP-i1 bootstrap conventions).
The MRV11-C must
be strapped for pagirlg mode enable and the correct window address.
It is the responsibilit~ of the code loaded from the MRV11-C board to
lOcld an~ additional program area from the board into RAM.

6
7
8
9
10
11
12
13
14
15
16
17
18
19

173406
173412
173414
173416
173420
173424
173430
173432
173434
173440

004567
173120
177000
005011
012700
016040
005700
001374
004567
000627

000306

001000
157776
000246

MRBoor: JSR

15:

.WORD
.WORD
CLR
MOV
MOV
TST
BNE

JSR
BR

R5,SETT4
;Setup timeout trap to start
RLBOOT-MEMt173000 i RL01 boot if MRV11-C is not present,
MRSCSR
and preload CSR address into Rl
@R1
;Set paging CSR to map page 0
t512.,RO
;Load high b~te offset
MRSWIN-2(RO),-(RO) ;Cop~ word from ROM to RAM
RO
,Have we loaded all 256 words ~et?
1$
;If NE, no
R5,CHK240
;Check for valid secondar~ boot
RLBOOT
;And if not valid, pass on to RL01 boot

DISK BOOTSTRAP
RXOllRX02 BOOTSTRAP

UNIVH:~;AL

MACRO V03.02D13-JUN-79 PAGE 9
.SBTTL

RX01/RX02 Bootstrap

3
4
5
6
7

This routine will bootstrap either floppw drive, at the
media mounted in that drive.

10
11

...

CO
CO

of the

Resister IJsase:
RO
densitw bit ! unit select bit (proto for commands)
R1
RXDB address
R2
bus address for next read operation
R3
word count/sector
R4
RXGO TR/DONE test routine pointer
R5
current sector address (1,3,5,7)

8
9

12
13
14
15 173442
16 173446
17 173450
18 173452
19 173456
20 173460
21
22 173462
23 173466
24 173470
25 173472
26 173474
27 173500
28 173502
29 173504
30 173506
31 173512
32 173516
33 173520
34 173524
35 173526
36 173530
37 173534
38 173540
39 173542
40 173544
41 173546
42 173552
43 173554
44 173556
45 173562
46 173564
47 173572
48 173574
49 173576
50 173600
51 173602
52 173604
53 173606
54 173610
1:.,-'::::
,J,J
173612
56 173616
57 173620

densit~

004567
173406
177172
004567
005046
000404

000252

012700
074016
001746
111600
004567
000013
111102
100366
012703
032702
001403
052700
006303
005002
012705
004567
000007
010511
004514
012711
004514
100714
004567
000003
032737
001413
010311
004514
010211
004514
1 .:..:.
'"Vi<:",")C"
...J.:.. ,J
060302
060302
022702
001346
000404

000020

000272

000154

000100
000040
000400
000001
000114

000001
000072
004000

001000

177170

.ENABL
RXBOOT: JSR
.WORD
.WORD
JSR
CLR
DR

LSB
R5,SETT4
;Set timeout trap to restart MR boot
MRBOOT-MEMtI73000 i if RX is not present, and
RXDB
preload RXDB into Rl
R5,DELAYI
;Wait for 2 seconds if RXU is present
-(SP)
~Set unit=O
RXTRY
;And start boot

RXOUER: MOU
XOR
BEQ
RXTRV: MOUB
JSR
.WORD
MOUB
BPL
MOU
BIT
BEQ
BIS
ASL
CLR
MOU
JSR
.WORD'
MOU
JSR
MOV
JSR
BMI
JSR
.WORD
BIT
BEQ
MOV
JSR
MOV
JSR
CMF'B
ADD
ADD
CMF'
BNE
BR

tRX$$UN,RO
RO,@SP
MRBOOT
@SP,RO
R5,RXGO
RX$RST
@Rl,R2
RXOUER
t64.,R3
tRXE$DN,R2
IS
tRXSSIIE,RO
R3
R2
t1,R5
R5,RXGO
RXSRED
R5,@R1
R5,@R4
t1,@Rl
R5,@R4
MRBOOT
R5,RXGO
RXSEMP
tRXSS02,@tRXCS
3$
R3,@Rl
R5,@R4
R2,@R1
R5,@R4
(R5)t, (R5)t
R3,R2
R3,R2
t512.,R2
2$
5$

iGet unit number mask
iAnd switch units
iIf both have been tried, So on to next boot
iInitialize current unit/densit~ word
iStart a read status operation
; to determine status and densit~
iPick UP low bwte of status
iIf PL, drive not readw
;Assume sinsle densit~, set word count
;Check media density
ilf EU, sinsle density
;Else set double density in default word
iAnd double word count/sector
;Current bus address = 000000
;Current sect~r address = 1
iStart read sector operation
i and wait for TR
iSet sector t
iWait for TR aSain
;Set track tl
iWait for DONE
;If error, skip this boot
iStart empty buffer function
i and wait for TR
iIs DMA available?
iIf EQ no - handle as RXOI
iElse load word count
iWait for TR
iAnd load current bus address
iWait for DONE
iUpdate sector adrs
iAnd also the
; current bus address
iHave we read all of first block yet?
iIf NE, no - continue with next sector
;Else So check for valid secondary boot

DISK BOOTSTRAP
RX01/RX02 BOOTSTRAP

MACRO V03.02B13-JUN-79 PAGE 9-1

UNIVEF~SAl

58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81

I\)

173622
173624
17362'6
173630
173632
173634
173636
173640
173642
173644
173650
173652

006303
111122
004514
077303
005000
105716
001401
005200
005741
004567
005721
000703

173654
173656
173660
173664
173666
173670
173674
173676
173700

012504
050004
010437
010704
005741
032711
001775
005721
000205

3$:
4$:
5$:

6$:
000036

RXGO:
177170
000240

1$:

;Turn word count into byte count
;Move one byte frolT! blJffer to lTIenlory
;Wait for TR or DONE
;loop for all b':ltes in first sector
; AsslJnle unit 10
;Was it unit 101
nf EO, yes
jElse indicate unit 11
;Reset to point to CSR
;Check for valid secondary boot
jlf not valid, reset to RXIIB
;And so switch units

ASL
MOVB
JSR
SOB
ClR
TSTB
BEO
INC
TST
JSR
TST
BR
.DSABL

R3
@R1,(R2>t
R5,@R4
R3,4$
RO
@SP
6$
RO
-(R1)
R5,CHK240
(R1)t
RXOVER
lSB

MOV
BIS
MOV
MOV
TST
BIT

(R5)t,R4
;COP':l cOlTIlTland word to IJse
;Set unit I and densit':l
RO,R4
R4,@IRXCS
;Start operation
;COpy adrs for later calls
F'C,R4
jR1 -:> RXCS
-(RU
IRX$$TR!RX$$DN,@R1 ;Wait for TR or DONE
;If ED.~ neither are true ~et
1$
(RUt
;Reset R1 -:::. RXDB and checl'-. for errors
; RetlJrn to caller
R5

BED.

TST
RTS

UNIVERSAL DISK BOOTSTRAP

MACRO V03.02B13-JUN-79 PAGE 10

MISCEllANEOUS SUBROUTINES
.SBTTl

1
2
3 173702

005737

CRUNCH: TST

170000

Miscellaneous Subroutines
@t170000

;This better trap to 4,

gu~S

4
The CHK240 routine will return onl~ if location 0 does not contain a
valid secondar~ bootstrap (i.e., does not have a NOP instruction in it).
Otherwise it starts execution of the booted program.

6
7
8

0
.....L

9 173706
10 173714
11 173716
1'")
.:..
13
14
15
16
17 173720
18 173724
19 173732
20 173734
21 173740
22 173742
23
24
25
26
27
28 173744
29 173746
30 173750
31 173754
32 173756
33 173760
34 173762
35 173764
36 173766

022737
001024
005007

000240

000000

CHK240: CMP
BNE
ClR

t240,@tO
RETR5
PC

;Did we read a valid bootstrap?
;If NE, no
;Else gO to it

The SETT4 routine is used to set UP the bus timeout trap vector to
activate another bootstrap if the current device is not
present on the s~stem.
autDmaticall~

012537
012737
012501
012706
005711
000115

000004
000340
004000

5ETT4:
000006

MOV
MOV
MOV
MOV
TST
JMP

(R5)t,@t4
t340,@t6
(R5>t,R1
tSTACK,SP
@R1
@R5

;Set trap adrs into location 4
;And PS = Priorit~ 7
;Preload R1
;Reset stack pointer
;Trap to next boot if controller not present
;And return to caller

The DELAY routines are used b~ the RK05 and RX bootstraps to wait for
Bus timeout traps (min, 10us) are used to minimize
the device to spin UP.
processor speed dependence,
004517
004517
012700
010604
005003
010710
,010406
077332
000205

000004

DElAY4: JSR
JSR
DElAY1: MOV
MOV
CLR
MOV
MOV
SOB
RETR5: RTS

R5,@PC
R5,@PC
t4,RO
SP,R4
f.:3
F'C,@RO
R4,SF'
R3,CRUNCH
R5

;Wait for min. 7 seconds
;Wait for min 1. 79 seconds
;Save clJrrent stac~. pointer
;Set ma~<imum count for loop
jSet timeolJt PC (Assl../mes @t6 = 340! )
;Restore original SF'
;If R3 NE 0, gO force timeolJt trap
; Hand'=l RTS R5 instruction

UNIVERSAL DISK BOOTSTRAP
MISCELLANEOUS SUBROUTINES
21
26

000001

MACRO V03.02B13-JUN-79 PAGE 11
YOU HAVE 4 FREE WORDS UNUSED OUT OF 256.
.END

LJ ~~ 1 VEf~SAL I) I St<

MACRO V03. 02B13-~JUN-79 F'AGE 11--1

SYMBOL TABLE
ADCONT
ADDfn
CHECK
CHK240
CRUNCH
DCONT
DELAY1
DELAY4
i'1EM
MEMDO
MEMERA
MEMERD
MEMT

173056
173040
173050
173706
173702
173102
173750
173744
173000
173036
173054
173100
173062
MRBOOT 173406
MR$CSR= 177000
MR$WIN= 160000
ORIGIN= 173000
RETRY = 000010
173770
000000
ERRORS DETECTED:

RETR5

17376t.l
17'7410
RKBOOT 173300
177404
RKCS
RKIiA
177412
177416
RKDB
177400
RKDS
177402
RKER
RKWC = 177406
RK$CRS= 000001
RK$DRS= 000015
RK$RCK= 000013
RK$RED= 000005
RK$SEK= 000011
RK$WCK= 000007
RK$WLK= 000017
RK$WRT= 000003
174402
RLBA
RKI~A

• ABS.

000
001
0

VIRTUAL MEMORY USED:
1624 WORDS
(7 PAGES)
DYNAMIC MEMORY AVAILABLE FOR 48 PAGES
,LP:DISKBT=DK:DISKBT

f..:LBOOT 173120
RLCS
174400
RLDA
174404
RLE$UH= 000006
RLG$RS= 000013
RLMP
174406
RL$GST= 000004
RL$NOP= 000000
RL$RD = 000014
RL$RDN= 000016
RL$RHD= 000010
RL$SEK= 000006
RL$WCK= 000002
RL$WD = 000012
RL$$CA= 000177
RL$$DR= 000001
RL$$ER= 177730
RXBOOT 173442

RXCS
RXDB
f~XE$CF~=
f~XE$[lD:::

RXE$DE:::
RXE$DN=
RXE$[lR=
RXE$I[I=
f~XE$UN=

f.:XGO
RXOVER
RXTRY
RX$EMP=
RX$FIL=
RX$REC=
RX$RED=
RX$RST=
RX$ST[I=

177170
1771/2
000001
000100
000020
000040
000200
000004
000400
173654
173462
173472
000003
000001
000017
000007
000013
000011

RX$WDD= 000015
RX$WRT= 000005
RX$$DE= 000400
RX$$DN= 000040
RX$$ER= 100000
RX$$FN= 000016
RX$$GO= 000001
RX$$IE= 000100
RX$$IN= 040000
RX$$TR= 000200
RX$$UN= 000020
RX$$XA= 030000
RX$$XX= 003000
RX$$02= 004000
SETT4
173720
STACK
004000
WALK
173070

NUMBER

)lnote
TInE

063
DATE

RL01 Type-In BootstraE

DIS1RIBUTION
ORIGINATOR

3 /

19 / 79'

PRODUCT

Unrestricted

RL01

Barbara Beck
PAGE 1 OF 1

The following bootstrap may be typed in, under ODT control, to boot an
RL01 disk, drive O. To boot other than drive 0, locations 1020, 1036 and
1062 should contain the drive number in the upper byte.
RL01 TIPE-IN BOOT
1000
1002
1004
1006
1010
1012
1014
1016
1020
1022
1024
1026
1030
1032
1034
1036
1040
1042
1044
1046
1050
1052
1054
1056
1060
1062
1064
1066
1.070
1072
1074
1076

012710
174400
105710
100376
012760
13
4
012710
4
105710
100376
012760
077601
4
012710
6
105710
100376
012760
177400
6
012760
0
4
012710
14
10571.0
100376
00571.0
100001
000000
005007

MOV

#174400,RO

;Put CSR in RO

TSTB
BPL
MOV

(RO)
.-2
#13,4(RO)

;Check for Ready
;Wait for Controller
;Set Up for Drive
;Reset and Clear Error

MOV

#4, (RO)

;Get Status

TSTB
BPL
MOV

(RO)
.-2
#77601,4(RO)

;Wait for Ready
;Loop on Wait
;Seek - Cy1

MOV

#6, (RO)

;Seek Connnand

TSTB
BPL
MaV

(RO)
.-2
#177400,6 (RO)

;Check for Ready
; Loop on Wait
;Word Count-400
; (2 Sectors)

MaV

#0,4(RO)

;C1ear Disk Address
; Register

MOV

#14, (RO)

; Read

TSTB
BPL
TST
BPL
HALT
CLR

(RO)
.-2
(RO)
. +2

;Check for Ready
;Loop on Wait
;Check for Error
;Branch if OK
;Ha1t on Error
; Execute Boot

~D~~DDmD
COMP4ONEMTS

GROUP
204

NUMBER

)lnote
TITLE

064
DATE

DLV11-J I/O Pase Address Problem ReEort

DIS1RIBUTION
ORIGINAIDR

/ 03

/ 79

PRODUCT

DLV11-J Users

DLV11-J

Joe Austin
PAGE 1 OF 2

PROBLEM
Under certain conditions, the DLV11-J will falsely respond to bus cycles
intended for other bus interface modules. When this happens, the
DLV11-J address selection logic will be enabled, in addition to the
address selection logic of the correct module. This results in the
DLV11-J placing information onto the bus which will be OR'ed with the
data from the correct module.
KOTE:

DLV11-J modules at Circuit Schematic (CS) Revision E or above do
not have this problem.

CONDITIONS
1)

This problem will occur only when the program is performing a bus
cycle that accesses the I/O page and will not occur for accesses
in the 0-28Kword address space for the LSI-II.

This problem will occur only on DLV11-J modules that are configured
to have a console port.

This problem is more noticeable with the 11/23 and with DMA transfers
on the LSI-II and LSI-11/2.

PROBLEMS OBSERVED
1)

This problem has been noted to occur when using the bootstrap in the
REV11 module to load paper tape. In this case, the REV11 RCM command
"AL177560" will cause an abort to ODT. However, the conunand ''AL CR"
will work properly.

Program failures and data errors may be noted when using the 28K to
30K area in the I/O page for program memory.

~DmDDmD
COMPONENTS

GROUP
205

NUMBER 064
PAGE 2 OF 2

Errors may also be noted while usinlg other I/O interfaces which
have certain address bits (notably bits 5 and 8-12) that are
similar to those used by the DLVll-.J.

SOLUTION
Install ECO M8043-002 on the DLV11-J.
Revision E.

'£his BCO brings the CS up to

All modules processed by the Customer Repair Area (CRA) will be updated
to this ECD. This update will be perfol:med at no charge to the customer.
This customer should obtain a no-charge SBA from his Sales Specialist in
order to have the module updated.
.
QUICK CHECK
The presence of green wires or of CS Revision E or higher indicates that
this ECO has been installed.

OOTE
'mIS ECO IS REQUIRED FOR ALL DLVI1-J
MODULES USED WITH THtl LS1-11/23.

mDmDD:mD
COMPONENTS
GROUP
206

NUMBER

J.lnot.e

065
DATE

BootstraE for RX02

TITLE

Unrestricted

DISTRIBUTION
ORIGINATOR

6 / 04 / 79
PRODUCT
RX02

Barry Maskas

PAGE 1 OF 3

These boots are to be used in systems with RX02 floppy disk drives
controlled by a Q-bus QM8029) interface. The diskette for boot #1
must be DIGITAL double density and must reside in Drive O. The
diskette for boot #2 must be single density format and must reside
in Drive O.
The LTC must be off and other interrupts inhibited; i.e., under
ODT enter $S/
340 CCR) . Ini tialize the stack pointer:
$6/ ______ 1000lCRJ:- Initialize the program counter: $7~ ______ 1000(CR).
Type in the appropriate boot, return to address 1000 and~type P;
i.e., 1000P
RXOI TYPE-IN BOOT #1 -- DOUBLE DENSITI DISKETTE FORMAT
001000
001002
001004
001006
001010
001012
001014
001016
001020
001022
001024
001026
001030
001032
001034
001036
001040
001042
001044
001046
001050
001052
001054
001056
001060

012700
100240
012701
177170
005002
012705
000200
012704

MOV

#100240,RO

; INIT TEST WORD

MOV

#177170,R1

; INIT RX2CS ADDR

CLR
MOV

R2
#200,R5

; INIT BUS ADDR
; INIT WDCNT

MOV

#401,R4

;INIT TRACK &SECTOR ADDR

START:

MOV

#177172,R3

;INIT RX2DB ADDR

WAIT:

BIT
BEQ
EMI

RO, CR1)
WAIT
HALT
#407, (R1)

;WAIT FOR RFADY,
;DONE AND ERROR FlAGS
;HALT ON ERROR
;RFAD SECTOR

RO, (Rl)
WAIT1
HALT
R4, (R3)
R4
RO, (Rl)
WAIT2
R4, (R3)
R4

;WAIT FOR RFADY

BEGIN:

000401

012703
177172
030011
001776
100437
012711
000407
030011
001776
100432
110413
000304
030011
001776
110413
000304

MOV

WAIT1:

BIT
BEQ
BMI

- MJVB
SWAB

WAIT2:

BIT
BEQ
MOVB

SWAB

~D~DDmD
COMPONENTS

GROUP
207

;HALT ON ERROR
; LOAD SECTOR ADDR
; INIT TRACK ADDR
; WAIT FOR READY
; LOAD TRACK ADDR
; REINIT SECTOR ADDR

NUMBER 065
PAGE 2 OF 3

).Inote
001062
001064
001066
001070
001072
001074
001076
0011100
0011102
0011104
0011106
001110
0011:12
0011:14
0011:16
001120
001122
001124
001126
001130
001132

030011
001776
100421
012711
000403
030011
001776
100414
010513
030011
001776
100410
010213
060502
060502
122424
120427
000003
003735
005007
000000

WAIT3:

BIT
BEQ
BMI
MOV

lWAIT4:

lWAIT5:

,HALT:

RO, CRl)
WAIT3
HALT
#403,CRl)

BIT
BEQ
BMI
MaV
BIT
BEQ
BMI

; WAIT FOR OONE
;HALT ON ERROR
; IMPTY BUFFER

RO, CRl)
WAIT4
HALT
RS,CR3)
RO,CR1)
WAITS
HALT
MOV
R2, CR3)
ADD R5,R2
ADD R5,R2
CMPB CR4)+, CR4)+
CMPB R4,#3

; WAIT FOR READY

BLE START
CLR PC
HALT

; IF NO, AGAIN

; HALTON ERROR
; LOAD WORD CNT
; WAIT FOR READY
;HALT ON ERROR
; LOAD BUS ADDR
; UPDATE BUS ADDR
;UPDATE SEC10R ADDR
; READ ONE BLOCK?
; IF YES, LOAD

RX02 TYPE-IN BOOT #2 -- SINGLE DENSITY DISKETTE FORMAT
0010130
0010132
0010134
0010136
001010
001012
0010:14
001016
0010:20
0010:22
0010:24
0010:26
001030
0010:32
0010:34
0010:36
001040
001042
001044
001046
001050
001052
001054
001056
001060

012700
100240
012701
177170
005002
012705
000100
012704
000401
012703
177172
030011
001776
100437
012711
000007
030011
001776
100432
110413
000304
030011
001776
110413
000304

MOV

#100240,RO

; INIT TEST WORD

M)V

#177170,R1

; INIT RX2CS ADDR

CLR
M)V

R2
#100,R5

; INIT BUS ADDR
;INIT WDCNT

MOV

#401,R4

;INIT TRACK AND SEC10R

START:

MOV

#177172,R3

; INIT RX2DB ADDR

lWAIT:

BIT
BEQ
BMI
MJV

RO, CR1)
WAIT
HALT
#007, CR1)

; WAIT FOR READY,
; OONE AND ERROR
; HALTON ERROR
; READ SEC10R

lWAIT1 :

BIT
BEQ
13MI
MJVB

:BEGIN:

WAIT2:

RO,CR1)
WAIT1
HALT
R4, CR3)
SWAB R4
BIT RO, CRl)
BEQ WAIT2
MOVB R4, CR3)
SWAB R4

; WAIT FOR READY
;HALT ON ERROR
;LOAD SEC10R ADDR
; INIT TRACK ADDR
;WAIT FOR READY
; LOAD TRACK ADDR
; REINIT SEC10R ADDR

~DmDDI~D
COMPOMIEMTS
CiROUIP
208

NUMBER 065
PAGE 3 OF 3

).Inote
001062
001064
001066
001070
001072
001074
001076
001100
001102
001104
001106
001110
001112
001114
001116
001120
001122
001124
001126
001130
001132

030011
001776
100421
012711
000003
030011
001776
100414
010513
030011
001776
100410
010213
060502
060502
122424
120427
000007
003735
005007
000000

WAIT3:

WAIT4:

WAITS:

HALT:

BIT
BEQ
BMI
MOV

RO, (Rl)
WAIT3
HALT
#003, (R1)

; WAIT FOR OONE
; HALTON ERROR
; EMP1Y BUFFER

RO, (Rl)
WAIT4
HALT
MOV
R5,(R3)
BIT RO, (Rl)
BEQ WAITS
PMI HALT
MOV
R2,(R3)
ADD R5,R2
ADD R5,R2
CMPB (R4)+, (R4)+
CMPB R4,#7

;WAIT FOR RFADY

BLE START
CLR PC
HALT

; IF ID, AGAIN
; IF YES, LOAD

BIT
BEQ
EMI

; HALTON ERROR
; LOAD WORD CNT
; WAIT FOR RFADY
; HALTON ERROR
; LOAD BUS ADDR
; UPDATE BUS ADDR
; UPDATE SECIDR
; RFAD ONE BLOCK?

mDmDD~D
COMPONENTS
CiAnUP

209

NUMBER

)lnote
TITLE

066
DATE

11/23 Floating Point Compatibilitr

DI8'lRIBUTION
ORIGlNAIDR

Restricted to KEF11-AA Users

6 /

/ 79

PRODUCT

KEF11-M

Barry Maskas
PAGE 1 OF 1

Early KDF11 (M8186) modules will not support floating point functionality
because the FP11 Hybrid I.C. is not compatible with initial versions of
the CTL- DAT Hybrid chip and MMU chip. These modules can be identified
by the following or earlier revision codes or part m..nnbers printed on
the chips:
CClvllilNATION

mDEL #

CHIP PN

HYBRID PN

DEC 303-C
DEC 302-E
DEC 304-C

23-001C7-M)
21-15541-AA)
21-15542-00

57-00000-00

DEC 303-D
DEC 302-E
DEC 304-C

23-001C7-M)
21-15541-M)
21-15542-00

57-00000-00

DEC 303-D
DEC 302-F
DEC 304-C

23-001C7-AA)
21-15541-AB)
21-15542-00

57-00000-01

CTL:
DA.T:
M\1U:

eTL:
DA.T:

M\1U:

eTL:
DAT:
M\1lJ:

All later revision codes are compatible with the option.
If a user (DCG customers only) desires to upgrade his L81-11/23 module
to include floating point, he should contact his microcomputer sales
representative.
NJTE:

With the exception of floating point, the modules with the above
chip sets have identical functionality to the upgraded modules.

~DmDDmD
COMPONENTS

GROUP
210

NUMBER

).Inote
TITLE

067A

DLVII-J Receiver Chip Problem

DIS1RIBUTION
ORIGINATOR

DATE
8 /

PRODUCT

DLVII-J Users

DLVII-J

Joe Austin

PAGE 1 OF 2

THIS MICRO NOTE SUPERSEDES MICRO NOTE #067
This Micro Note describes the fix to a potential problem that has been
reported by some DLVI1-J users.
SYMPTCMS

The system can transmit data to a tenninal cOImected to the DLVII-J
but cannot receive data from it.

The output on pins 6 and 7 of the 9637 ATC receiver chip (E34 or
E37) is cons tantly low while data is observed on the inputs
(pins 2 or 3) of the receiver chip.

PROBLEM
Receiver chips (2 per module) with part number 9637 ATC do not meet the
original DEC specifications. If the REC+ signals on pin 8 of the cable
connector (see Figure 1) becomes more negative than -10 volts, then no
signal will pass through the receiver. In this case, the receiver output
usually remains low.
CHIP IDENTIFICATION
All 9637 parts with a date code "79xx" or higher are correct and will
work properly.
SOLUTION
A "quick fix" is described on page 2. The long-tenn fix consists of
having the receiver chips replaced at no cost to the customer.

~D~DDmD
COMPONENTS
GROUP
211

NUMBER 067A
PAGE 2 OF 2

---'---1

CR1

~--...a..-~

RECEIVER INTEFIFACE
FICV
L--!;IATA

RX REC -

IBRE~<
I
II

IN914 (or equivalent)
•

7. 5KIl ::5%, ~W

XMIT

DATA

...J

!
a:

READE R RUN_PU_L_S_E_ _ _

FIGURE 1

w
~ _ _ _ _ _ _ _ _ _ _ _ _ _ _---f_CL_K__ Q.

1+12 VDC

DLVII-J QUICK FIX (One Per Line)

1+12 F

----~----------------~---~
10
&...-. _ _ _ _ _ _ -...1

qUICK FIX
If your system experiences this problem, then the addition of the series
resistor and diode as shown in Figure 1 will adequately solve it. The
purpose of the resistor (Rl) is to offset the input signal from the
terminal such that the signal into thEl receiver does not exceed the
operating limits of the chip. The purpose of the diode (CRl) is to
prevent the positive portion of the input signal from being offset by
the resistor.
NOTE:

It is reconnnended that this fix not be used unless necessary.

momooma
COMPC)MENTS
(aOUP
2~12

NUMBER

).Inote

DATE

TITLE MicrocamEuter Module Environmental Considerations
DIS1RIBUTION
ORIGINATOR

068

7 /

PRODUCT
All
LSI-II Bus Modules

Unrestricted
Rick Plunnner

PAGE 1 OF 1

The following information defines the environment in which LSI-II bus modules
are designed to operate:
OPERATING
Temperature:

5°C to 60°C -- Derate the maximum temperature by one degree
Celcius for each 1000 feet of altitude above
8000 feet.

Relative HUmidity:

10% to 90%, non-condensing

Altitude:

Up to 50,000 feet (Note temperature derating above 8000 feet.)

Airflow:

Sufficient air flow must be provided to limit the temperature rise
across the module to 5°C for an inlet temperature of 60°C. For
inlet air temperature below 55°C, air flow must be provided to
limit temperature rise across the module to 10°C.
The actual air flow and fan requirements will vary greatly with
mechanical design and the choice of modules, but in any event,
the above requirements must be met for all modules in the system.

In addition to the operating considerations, the modules may be stored over a
wider range of temperatures. When stored outside the operating range, modules
should be allowed to stabilize in the operating range for a minimum of 5 minutes
before operating. The storage limits are listed below for reference:
STORAGE
Temperature: -40°C to 66°C
Relative HUmidity:
Altitute:

10% to 90%, non-condensing

Up to 50,000 feet

The above information applies only to LSI-II bus modules except the MMV11-A
whose operating temperature is SoC to 50°C. For external peripheral devices
such as mass storage devices and terminals, the individual User's Guides should
be consulted for environmental considerations.
IDTE:

These are the design limi ts ~D~DDmD
for the modules. Lower
temperature limits will COMPONENTS
serve to increase the
CiROUD
life of the product.

213

NUMBER

j../note

069

DATE

TITLE

6/ 21 /

18-Bit ~~ With Chipkits

DISTRIBUTION
ORIGINATOR

PRODUCT

Unrestricted

DCK11-AB, -AD

Rick Plummer
PAGE 1 OF 2

The following information will serve to assist those DMA Chifkit users who are
designing interfac.es for use with 18-bit addressing in LSI-l /23 systems. It
is intended as an addendum to the specification and application information for
the chip sets as published in the following:
Microcomputer Memories and Peripherals Handbook
Computer Interfacing Accessories and Logic Handbook
Chipkit Users Manual
To extend the DMA addressing to 18 bits, the following functions must be
accomplished:
1.

Provide an extension of 2 bits to the bus address counter which will
advance on overflow from the 16 bits provided in the DC006 chips.

Provide for read/write of these 2 bits as bits 4 and 5 of the interface
control and status register (CSR).

Provide for placing these 2 bits on address lines 16 and 17 during the
address portion of the IMA. transfer cycle.

Clear the additional bits upon initialization of the bus.

The following figure outlines the required additional hardware. Signal
mnemonics are from the DMA application section contained in the abovementioned documents. Because bits 4 and 5 are used for software compatibili ty with other 1MA. interfaces, it will be necessary to use a bit other
than 5 for data in/data out selection as was the case in the application
info:nna tion.

~D~~ID~D
COMPONENTS
C;RO~P

214

NUMBER 069
PAGE 2 OF 2

74LS367's

CSRRD ---+---+--~....,
ADDITIONAL
COUNTER

DATA 5 ----I----4I~ PB

QB t--+---+--~---I

BDAL17

~--

DATA 4 _ _~_---I DA

BDALI

CSR WLB

INIT L
ADREN H

Max A

From High Byte DC006

INA CHIPKIT ADDRESS EX11!NSION

~D~DD~D
COMPONENTS
GROUP
215

NUMBER

).Inote
TITLE

LSI -11 vs.. LSI -11/23 Bus Transaction Differences

ORIGINATOR

22 / 79

PRODUCT
KDFI1-A

Unrestricted

DIS1RIBUTION

DATE
6 /

070

Rick Plummer
PAGE 1 OF 2

There a.re a number of bus transactions that are performed differently on the
LSI-ll/23 than on the LSI-II and some which are unique to the LSI-ll/23. While
these do not affect the operation of DIGITAL or other properly-designed custom
interfaces, they are presented here for the purpose of helping users more
thoroughly understand the bus operations~
1.

~ Address

Relocation -- When the :~ is enabled, the virtual address
occurs on the bus at 'the beginning of each bus cycle. This is then
followed by the relocated address. Once the relocated address has met
the bus address set-up time requirements, then sync is issued. Note
tha t i t is the relocated address tha t is part of the bus timing and
protocol.

MMU Re~ister Transfers -- When the various MMU registers are addressed
from t e program, the transaction will appear on the bus as any normal
CPU to I/O connnunication (i.e., address, data, sync, DIN/DOUT and reply
will occur). It is not possible, however, to connnunicate with these
registers from another bus master on the bus.

PSW Transfers -- When the PSW is explicitly addressed (Mov #340, @#177776),
the transfer -will appear on the bus in a similar fashion to the M'4tJ
registers except that there will be no reply. Likewise, there can be no
connnunication from a bus master to the PSW.

DATOB Cycles -- On previous LSI-II processors the byte data has been
ptesent on both bytes during a DATOB cycle or the output portion of a
DATIOB cycle~ The LSI-ll/23 presen.ts valid data only on the byte
actually being transferred during these cycles. The data on the opposite byte is not meaningful during these transactions.

DATIO
erand Fetches - - On previous LSI -11 processors, the source
operan or MTPS and EIS instructions was fetched using the DATIO bus
cycle. The ]~SI-ll/23 fetches these· using DATI bus cycles.

MOVB Output Cycle -- Previous LSI-II processors performed a DATIOB bus
cycle as the last cycle of instruction execution. The LSI-ll/23 performs
a DATOB as the last bus cycle of in.struction execution.

~D~~DD~D
COMPONENTS
Ci~OUP
2~16

NUMBER 070
PAGE 2 OF 2

'7.

CLR and CLRB Cycles -- Previous LSI-II processors perfonned a DATIO

(or DATIOB) cycle for hardware minimization.

The LSI-II/23 uses a

DATO (or DAIDB) bus cycle to perfonn the instruction.

SXT ~cles -- Previous LSI-II processors perfonned a DATIO cycle for
the ast bus cycle for hardware minimization. The LSI-II/23 uses a
DATO cycle as the last bus cycle in execution.

also to Micro Note 055 for bus timing differences between the LSI-II
and LSI-II/23.

]~efer

~D~DDmD
COMPONENTS
GROUP
217

)lnote
TITLE

Expanding BA11-MA and BAl1-NC Based Srstems

DIS1RIBUTION
ORIGINAWR

NUMBER

071

DATE

7 /

05 /

PRODUCT

Unrestricted

BAl1-M
and BAl1-N Boxes

Barry Maskas

PAGE 1 OF 3

This is intended to provide a reconnnended procedure for expanding BAl1-MA
based systems to a two or three box system which includes the BAl1-NE
expansion box or for expanding BAl1-NC based systems to a two or three
box system which includes the BAll-ME expansion box.
When expanding system configurations, pay strict attention to the single
backplane configuration rules and mUltiple backplane configuration rules
located. on page 4-39 of the 1978-79 Memories and Peripherals Handbook.
The PDP-11V03 systems motmted in a H984 series cabinet (described on
page 4-41 of the 1978-79 Memories and Peripherals Handbook) have only
enough expansion space to house one BAll-ME expansion box.
E!J)ansion Parts List:
Expansion Boxes:
Model

Primary Power/Front Panel

Bused Slots

BAll-ME

115v/blank panel

A,B,C, and D

BA11-NE

115v/blank panel

A and B only

Power Controller:
861-C

90-13Ov AC single phase 24A per pole primary
(available from Accessories and Supplies Group
at 800-258-1710) to output 90-13Ov AC at 12A
for each outlet

Bus Expansion Cards and Cables:
BCV1B-XX

Used with two 'backplane systems

BCVlA-XX

Used with the third backplane expansion

}~ can be

2,4,6, or 12 foot lengths

~D~DDmD
COMPC)NENTS
GROUP
218

NUMBER 071
PAGE 2 OF 3

BAl1-MA base box expanded to a BAl1-NE box:
Power is controlled by the power
controller ON/OFF switch.
...--

10 115v AC
SIMiLE PHASE

CUTLET

NOTE: Leave DC switch
in ON or UP position.

861-C
SWITCHED
...__ OUTPUTS
1

-t

J2 AC IN
J3 AC OUT

BAl1-NE backplane jumpers:
W1 R
W2 R
W3 R
The LTC is sourcing the BEVNI' L in the BAl1-MA box.
2.

BA11-NC base box expanded to a BAll-ME box:
,..Ft:olll. AVX ON/OFF switch of a bezel panel
Power is controlled by the
I
power controller ON/OFF
:
.lffA
B ~~
swi tch or by the AUX ON/OFF
:!
~3 ~,: .. J2 AC IN
switch on the bezel front
panel or the AUX ON/OFF
J3 AC OUT
switch of an 11/03-L
"

J
JZ
--_i
1,

cabi~. 115v AC

SIMiLE PHASE
OUTLET

•

~BCVl;~XX
----]

861-C
~
li~
SWITCHED ~ ~ c:::t~::~- J
OUTPUTS f
G~~L.~---+
..-. -.... - ..... - -----_--1

BA11- NC backplane jtD11pers:
W1 I
W2 I) If M7264 or M7264-YA CPU
W3 I) is used, otherwise R.
BA11-NC bezel jumpers:
W1 R) When bezel AUX ON/OFF switch is used to turn
W2 R) system power controller on and off, otherwise I.
W3 R
W4 I
The LTC is sourcing the BEVNI' L in the BAII-NC box via backplane
jumper W1 I.

~D~DDmD
COMPONENTS
GROUP
219

NUMBER 071
PAGE 3 OF 3

BAll-NC base box expanded to a BAll-NE box:
Power is controlled by the
AC input box ON/OFF switch.
TO 115v AC

J2 AC IN

SINGLE PHASE

OUTLET
001- NC backplane jumpers:
W1 I
W2
I) If M7264 or M7264-YA
W3 I) CPU is used, otherwise R.
OO1-NC bezel jumpers:
W1 I
W2 I
W3 R
W4 I

J3 AC OUT

Total input current from the AC source
must be less than l2A.

BAll-NE backplane jumpers:
Wl R
W2 R
W3 R
NOTE:

Do not attempt to source AC power for the BA11.-M box from

the BAll-N box AC outlet sin.ce the current rating of the
BA11-N box will be exceeded and severe damage may occur.
Also, do not attempt to chain AC power to three BAll-N boxes.
Further expansion guidelines are contained in the OOl-N Mounting Box
User's Guide CEK-BAllN-UG-001) or the BAll-N Momting Box Teclmical
Manual CEK-BAllN-'JM-OOl).
The LTC is sourcing the BEVNT L in the BA1l- NC box via backplane
jumper W1 I.

~D~DD!~D
COMPOMIKrS
GROll)
220

NUMBER

)Jnote

072
DATE

TITLE

PeriEheral ComEatibility with 11/23 Systems

DIS1RIBUTION
ORIGINATOR

7 /

/ 79

PRODUCT

Unrestricted

LSI-II
Memories &Peripherals

Barry Maskas

PAGE 1 OF 2

When configuring 11/23 systems or upgrading existing LSI-II systems, consider
the following option compatibilities:
I.

The following list of options will function in system configurations
with the KDF11-AA CPU:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.

II.

AAV11 (A6001) 4-channel 12-bit D/A converter
ADV11 (A012) 16-channel 12-bit A/D converter
BDV11 (M8012) bootstrap, diagnostic and tenninator
DLV11 (M7940) asynchronous serial line interface
DLV11-E (M8017) asynchronous serial line interface (with modem controls)
DLV11-F (M8028) asynchronous serial line interface
DRV11 (M7941) parallel line unit
DRV11-B (M7950) IMA interface
DUV11 (M7951) buffered line interface
DZV11 (M7957) asynchronous multiplexer
IBV11-A (M7954) IEEE instrument bus interface
KPV11-A,-B,-C (M8016,M8016-YB,-YC) power fail, LTC and terminator
KWV11-A (M7952) programmable real-time clock
LAV11 (M7949) LAl80printer interface
LPV11 (M8027) LAl80/LP05 printer interface
MRV11-BA (M8021) IN PROM-RAM module
MRV11-C (M8048) EPRCM, PRCM and RCM module
MSV11-C (M795S-Y) MOS memory (self-refresh)
MSVII-D (M8044) MOS memory (self-refresh)
MXV11-AA, -AC (M8047-.M, -CA.) memory and serial I/O
RLVII (M8013,M8014) RL01 disk drive controller
RXVII (M7946) RXOI floppy disk controller
RXV21 (M8029) RX02 floppy disk controller
TB111 (M9400-YB) 120 ohm tenninator

The following options can be utilized in 11/23 systems under the
following conditions:
1.

DLVII-J (M8043) asynchronous 4-line serial interface
CS Revision E or higher must be used or
ECO #M8043-MR002 must be installed.

~D~DD~D
COMPONENTS

GROUP
221

),Inote
2.

NUMBER 072
PAGE 2 OF 2

MSV11-E O~8045) MOS memory with parity (self-refresh)
Requires externa.l parity controller if parity
is to be used -- see Micro Note 052.

III. The following options are incompatible in some or all 11/23 system
configurations:
1.

M'-W11-A (H223,G653) 8KB core memory

Must be used, in backplanes which supply Q-bus
signals on both AlB and C/D connectors
(H9270 and r IDV11-B) -- it can only be configured in 64KB or less systems since it can
only decode 16 bits of address.
2.

MRV11-M (M7942) PRCM/RCM
Can only be configured in 64KB or less systems
because it only decodes 16 bits of address.

MSV11- B (M7944) MaS memory (requires refresh)
Can only be configured in 64KB or less systems
because it only decodes 16 bits of address and
it requires external refresh.

REV11-A,-C (M9400-YA,-YC) bootstrap, terminator and IMA. refresh
The bootstrap and diagnostics in ROM
are LSI-II unique and, therefore, use
on LSI-11/23 systems is incompatible -termination (120 ohms) and IMA. refresh
are features that still may be utilized.

RKV11-D RK05 disk interface
(~n only be configured

in 64KB or less systems because
it only does IMA. transfers into 16 bits of address.

KEVIl EIS/PIS chip
Designed for LSI-II and LSI-11/2 processors and is not
electrically compatible with 11/23 processors.

KlN11 Wri table Control Store
Designed for LSI-II and LSI-11/2 processors and is not
electrically compatible with 11/23 processors.

~D~DI]mD
COMPOt4ENTS
GROI~p

22:2

NUMBER

).Inote

073
DATE

WS8 Cabling

TITLE

DIS'IRIBUTION
ORIGlNAIDR

/ 05 /

PRODUCT

Unrestricted

WS8

Barbara Beck
PAGE 1 OF 2

The WS8 is a serial asynchronous peripheral. It is designed to be easily
interfaced not only to LSI-11 based systems but also to other computers as
well. It may be configured to operate in RS-232C, RS-422 or RS-423 protocol
(jumper selectable). Only the DLV11-J currently supports RS-422 on the
LSI-11 bus.
FRCM

CABLES

DLV11
DLV11-E
{ DLV11-F
DL11

WS8

Use BCOSC-XX (H8S6 to DB2SP) and a
BC20N-OS (DB2SS to AMP 2xS pin
female)

~DZV11

WS8

Use BC20N-OS (AMP 2xS pin female
to DB2SS). RS-232C connection
(cable or distribution panel) is
supplied with the modules

WS8

Use BC20N-OS (AMP 2xS pin female
to DB2SS) and a BC21B-OS (DB2SP to
AMP 2xS pin female)
OR
Use BC20M-SO (AMP 2xS pin female
to AMP 2xS pin female). This is
available in 50' lengths only

lDZll

<;"MXVl1
lDLVII-J

The pin-out of the serial I/O connector on the WS8 is as follows*:
PIN #
1
2
3
4
5
6

7
8
9

SIGNAL
Auxiliary A
Signal Ground
TRANEMIT DATA+
TRANSMIT DATASignal Ground
Index in Key - NO Pin
RECEIVE DATARECEIVE DATA+
Signal Ground

~D~DDmD
COMPONENTS
GROUP

223

NUMBER 073
PAGE 2 OF 2

2xS PIN CONNECIDR
BLOCK (Viewed
from Edge of Card)

* n~ DECtape II User's Guide incorrectly labels these pins.

~DmD[lmD
COMP<»IENTS
GROIIP

224

PRINTED
CIRCUIT
CARD

NUMBER

)lnote
TITLE

074
DATE

MXVll-AA,-AC Cabling

DIS'IRIBUTION
ORIGlNA1OR

/ OS / 79

PRODUCT

Unrestricted

MXVII-M, -AC

Barbara Beck

PAGE 1 OF

The following DEC cables are recommended for interfacing the MXVII to a
serial device:
BC20N-05

5' EIA RS-232C null modem cable to directly interface with an EIA RS-232C tenninal (2x5 pin .AMP
female to RS-232C female)

BC21B-05

5' ErA RS-232C modem cable to interface with modems
and acoustic couplers (2x5 pin .AMP female to RS-232C
male)

BC20M-50

SO' EIA RS-423 or RS-232C cable (2x5 pin AMP female
to 2x5 pin AMP female) to COlUlect to another MXVll,
DLVII-J, TU58 or any other peripheral with a
compatible COlUlector

The pin-out for the two serial I/O COlUlectors is:
PIN #
1
2
3
4
5
6
7

8
9

SIGNAL
UART Clock In or Out (16 x baud rate; CMOS)
Signal GroWld
TRAN3'-1IT DATA+
Signal GroWld
Signal Grotmd
Index in Key - No Pin
RECEIVE DATARECEIVE DATA+
Signal GroWld
When Fl is installed for the DLVll-KA, +IZV is
supplied through a lA fuse to this pin

~D~DD~D
COMPONENTS

GROUP
225

NUMBER 074
PAGE 2 OF 2

)Jnote
9

2x5 PIN CONNECTOR
BLOCK (Viewed from
Edge of Card)

PRINTED
CIRCUIT
CARD

The DLV11-KA may be used with the MXV11 for EIA to 20rnA current
loop conversion.
For more information on constructing cables, refer to Micro Note 056.

~D~DI]mD

COMPOttENTS
GROI.JP
226

NUMBER

).Inote
TITLE

075
DATE

MXV11-A2 Bootstrap Error Halts

DIS'IRIBUI'ION
ORIGINATOR

/ 18 / 79

PRODUCT

Unrestricted

MXV11-A2

Rich Billig
PAGE 1 OF 3

The MXV11-A2 bootstrap reports errors in operation by HALT instructions. The
attached list of HALT addresses (the number displayed by console ODT) details
the error indicated by each HALT and the effect of P (PROCEED) in response to
the HALT.

ru58 (TAPE) BOOT ERRORS
HALT @ PC

INDICATED ERROR

173076

Memory Diagnostic Failure
R2 = Address of Failing Word;
Expected Data is Contents of R2
P = Continue Test

173122

Memory Diagnostic Failure
R2 = Address of Failing Word;
R3 = Expected Memory Data
P = Continue Test

173140

Memory Diagnostic Failure
Bad Background Data
R2-2 = Address of Failing Word
R3 = Expected Memory Data
P = Continue Test

~DmDDmD
COMPONENTS
GROUP

227

NUMBER 075
PAGE 2 OF 3

173274

TU58 Controller Error
RO = Success Code in Low Byte
XXX357 = Data Check Error on Medium
XXX340 = Seek Error (Bad Tape Fonnat)
XXX337 = Motor Stopped (Drive Malfunction)
P == Restart the Memory Diagnostic

173374

Stand-Alone Program Not Found
The file name irdicated for stand-alone program
loading (by recording it in block #0) or by
calling the stand-alone load entry point was
not found in the RTII file directory of the
specified unit.
P == HALT Again (Cannot Continue)

173440

Protocol Error Between TU58 Controller &LSI-II
(Serial Line Unit/Cabling Problem)
P == Restart Memory Diagnostic

173474

Start Address Irlvalid
Location 40 in Stand-Alone Program File
Does Not Contain a Valid Program Start
Address
P := HALT Again (Cannot Continue)

DISK BOOT ERRORS
173056

Memory Diagnostic Failure
R2 = Address of Failing Word
R3 = Expected ThL ta
P == CONTINUE Diagnostic

173102

Memory 1)iagnostic Failure
R2 = Address of Failing Word
R3 = Expected Data
P == CONTINUE Diagnostic

~D~DD!ID
COMPONENTS
CiROUfJ228

J.lnote
173270

RL01 Bootstrap Failure
Unit 0 Contains a Bootable Medium but
Failed to Boot
P = Restart (Retry) RL01 Bootstrap

~D~DDmD
COMPONENTS
GROUP
229

NUMBER 075
PAGE 3 OF 3

NUMBER

).Inote

077
DATE

TITLE

Summary of BootstraE Sources

DIS1RIBUTION

Unrestricted

ORIGINA1OR

Charles Giorgetti

/ 10 / 79

PRODUCT

Bootstraps
PAGE 1 OF 1

The purpose of this Micro Note is to provide a brief stumnary of the sources tha t
will provide a bootstrap :for a given device. Included is a reference to a particular bootstrap that can be entered tmder the console monitor ODT for a given
device.
1.

REV11-A,-C bootstrap code is incompatible with the LSI-11/23.

2.
3.

The MXV11-A2 chips can only be used with the MXV11-M, -AC.
Revision A chips must be installed on the BDV11 to boot the RX02.

The "L" connmmd under the console monitor ODT is not available with the
LS1-11/23.

I:~

CONSOLE MONITOR
ODT

REV1l-A, -C

BDV11

MXV11-A2

RX01

See Microcomputer
Handbook Series

Yes

RX02

See Micro Note
#065

Yes

WSS

See Micro Note
#062A

Yes

RL01

See Micro Note
#063

Yes

DEVICE

MRV11-C
RK05
Paper Tape

~e Microcomputer

Hmdbook Series
See PDP-II
i>rogrammer's Card
"L" Connnand

~D~DD~D
COMPC)NENTS
Ci~)lJP

2:30

NUMBER

j./note

078
DATE

TITLE

L8I-11/23 Processor Differences

DI81RIBUTION
ORIGINA'IOR

8 /

02 / 79

PRODUCT

Unrestricted

KDF11-A

Barry Maskas

PAGE 1 OF 2

The following facts concerning the L8I-11/23 processor should be carefully
considered by all KDF11 users.
1.

Sunset Loops: The L8I-11/23 processor has the potential for several
microcode loops which cannot be broken out of by using the HALT switch;
i •e., it is an infinite loop. Only by negating the BDCOK H for a
minimum of 1 microsecond or cycling power off and on can you break the
loop. These loops revolve around the general problem that if anything
is wrong with memory page zero, any double abort (bus errors, memory
management aborts, parity errors, stack overflow) could cause a sunset
loop. Because these service inputs have a higher priority than the HALT
switch, the HALT switch is never recognized. The three most likely
causes of sunset loops which a user may encounter are:
a)

If the memory management is enabled and page zero of the kernel space
is set up as no access; i.e., Status Register Zero (SRO) bits 3-1
contain zeros and Page Description Register (PDR) bits 2 and 1 are
zeros, then any trap, interrupt or an abort will cause a read
reference to kernel page zero which will cause a memory management
abort. The 11/23 will get caught in the loop of trying to service
the memory management abort by reading the vector at 250 (octal)
which causes another memory management abort.

If there is no memory in locations 0-377 (octal) or the memory there
is faulty, then on traps, interrupts or memory management aborts a
read reference to kernel page zero will occur and will cause repeated
bus time- outs.

If memory in locations 0-377 (octal) is ROM, then any kind of double
bus error; i.e., the SP (R6) points to non-existent memory during a
bus time-out trap, which forces the kernel stack pointer to 4, will
cause an infinite loop because of the bus time-outs on the PC push
during the trap sequence. The memory will time-out because it does
not respond to writes.

~D~DDmD
COMPONENTS

GROUP
231

)Jnc)fe

NUMBER 078
PAGE 2 OF2

Stack: The LSI-11/23 has a hardware stack limit check to make sure that
"t.11eKernel stack does not go below 400 (octal). Since this check does not
exist on the LSI-11, the LSI-11/23 will trap to 4 on a stack push below
400 (octal).

Maskinf Inter~: The line time clock is hardwired to interrupt level 6
:md al current I/O devices reside on priority level 4; hence, to mask out
all interrupts, a M1PS #340 should bE~ used instead of a M1PS #200.

Ins tructions: Some fundamental diffE~rences exist between the way the
tSI-l1/23 treats some double operand instructions and the treatment by
the LSI-11 and the PDP-l1/34 when b01n operands use the same register
;md the first addressing mode is register (mode 0) and the second
addressing mode is auto-increment or auto-decrement (modes 2,3,4 or 5).
Since the destination address is calculated before the register operand
fetch on the LSI-11/23 and after the register operand fetch on the
LSI-II and PDP-11/34, the effective address may differ between the two
machines. This will result in different values being moved for
instructions like:

MOV RO, (RO)+
MOV RO,-(RO)
MOV RI,@-(Rl)
MOV Rl,@(Rl)+
MOV PC,@X(R)
See Micro Note #05:3 for PDP-II Family differences.

~D~DDmD
COMPOI~EMTS

CROUP

23:2

NUMBER

).Inote

079
DATE

8 /

TITLE The LSI-11/23 and the LSI-11/2 Buses Are the Same!

/ 79

PRODUCT

11/23 Upgraders

DIS1RIBUTION

LSI-11/23
ORIGINAIDR

Joe Austin
PAGE 1 OF 1

The LSI-11/23 uses the same Q-bus as the LSI-11/2 and the older quad LSI-II.
Ever since it was first developed, the DIGITAL backplanes for the Q-bus were
built with room-to-grow; the LSI-11/23 uses this room in order to implement
extended memory and priority interrupts. Bus signals that were listed as
"spares reserved for DIGITAL use" in earlier documentation have been renamed
to reflect their use with the 11/23, as shown in Table 1.
TABLE 1 - - BACKPLANE PIN ASSIGNMENT CCMPARISON
LINE
M1
AB1
BPI
AC1
AD1
AE1
API
AH1
AK1
ALI
AM2
AR1
AR2

BC1
BD1
BEl
BF1
BH1
BK1
BL1

BACKPlANE
NAME

KDF11-M

KD11-F

KD11-HA.

BSPARE1
BSPARE2
BSPARE6
BAD16
BAD17
SSPARE1
SSPARE2
SSPARE3
MSPARFA
MSPARFA
BIAKIL
BREFL
BIMGIL
SSPARE4
SSPARE 5
SSPARE6
SSPARE7
SSPARE8
MSPAREB
MSPAREB

BIRQSL
BIRQ6L
BIRQ7L
BDAL16L
BDAL17L
Single Step
SRUNL
SRUNL
Not Used
Not Used
~ SlRH
Not Used+
UBMMPL
M4U DAL18H
M\ID DAL19H
MMU DAL20H
M.1U DAL21H
CLK DISL
Not Used
Not Used

Reserved*
Reserved*
Reserved*
Reserved*
Reserved*
Not Used
SRUNL
Not Used
Not Used
Not Used
Not Used
BREFL
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
4K RAM BIAS
4K RAM BIAS

Reserved*
Reserved*
Reserved*
Reserved*
Reserved*
SIDP L
SRUNL
SRUNL
MTOEL
GND
Not Used
Not Used+
Not Used
SCLK3H
SWMIB18H
SWMIB19H
SWMIB20H
SWMIB21H
Not Used
Not Used

* Even though these lines are not used on the KD11-F and KD11-HA., they are
bused on the backplane and terminated for future bus expansion.

~D~DDmD
COMPONENTS

GROUP
233

NUMBER
BOA

)Jnota
LSI-1l/23 I/O PAGE ADDRESSING

TITLE

DISTRIBUTION

UNRESTRICTED

ORIGINATOR

RICK PLUMMER

DATE
10 / 29

/79

PRODUCT
KDFll-A
PAGE 1

OF 2

THIS MICRO NOTE SUPERSEDES #Bo
THE FACTS
In order to maintain a high degree of system compatibility between LSI-l1/23
systems and their LSI-11/2 counterparts, the I/O page addressing scheme has
been modified. The modification has to do with the physical address which is
present on BDAL lines during an I/O page reference.
On revision A3 and earlier KDF11-A modules, BDAL 16 and 17 were forced-active
whenever the processor made reference to the I/O page (i.e. whenever BBS7 was
asserted). (The r€:vision of the module is stamped into the plastic module
handle.) This made it impossible to reference the area between 56KB and 60KB
when using the MSVll-D series of memory mod~les in an unmapped system.
On revision A4 and above, as well as CO and above, this has been changed. In
unmapped mod~ the processor will reference the I/O page by asserting a physical
address between 56KB and 64KB on the lB-bit address bus, as well as asserting
BBS7. In mapped mode, the processor will behave as it has in the past and the
I/O page will have a physical address corresponding to 24BKB to 256KB present
on the bus during BBS7 references.
When using ODT to reference the I/O page with either module, you must still use
l8-bit addresses (i.e. 760000 to 777777).
THE IMPLICATIONS
The above has a number of implications with respect to the use of the LSI-ll bus
as follows:
1.

Devices which should respond as 1/0 page, whether they are I/O
register devices or others such as bootstrap ROM, should respond
based on BBS7 and not use BDAL 13-17.

~D~IDD~D
COMPC)NEMTS
CiRC)lJP
2~34.

NUMBER 80A
PAGE 2

Memory devices designed to respond in the 56KB to 64KB memory
area should not reply to addresses in this area if BBS7 is
asserted. This is especially critical in mapped systems because they power up in unmapped mode and RAM memory will overlay the I/O register. The disabling on BBS7 may optionally
be conditioned with BDAL 12 if one half of the I/O page is to
be used for memory. This is the case in 60KB systems using
the MSV1l-D series memories.

Other bus masters, such as DMA devices should assert BBS7 if
DMA access to the I/O page is desired.

SPECIFIC DEVICE CONSIDERATIONS
M5Vll-CD MEMORIES
These memories do not have provIsions for deselecting on BBS7 and must not be
configured to respond to addresses between 56KB and 64KB, or between 248KB and
256KB. They do, however, decode the l8-bit addresses and may be used elsewhere
in the system.
MRVll-C
a.

Bootstrap Addressing
The bootstrap mode responds only to BBS7 and low order address
bits and may be used as a normal bootstrap in the I/O page.

Direct addressing
The direct address decodes l8-bits but does not deselect on
BBS7, therefore, do not configure it for 56KB to 64KB in
systems which will be used in mapped mode. In unmapped systems
it may be configured for part of the I/O page.

Window Mapped Mode
The address of the window is decoded using l8-bits but does
not deselect on BBS7, therefore, do not configure it for
56KB to 64KB in systems which will be used in mapped mode.
It may, however, and quite often is, configured for the bottom
4KB of the I/O page in unmapped systems.

~D~DDmD
COMPONENTS

GROUP
235

OF 2

).Inote

NUMBER

081
DATE

TITLE

Use of Recommended Diskettes

DIS1RIBUTION

RXO 2, RXO 1 eus tomers

8 /

/ 79

PRODUCT

RXV21,
RX02, rue01

ORIGINATOR Mark Snrder
PAGE 1 OF 1

PROBLEM
Users llave experienced block errors on RX02's when using diskettes that
have normally been used on RX01' s. ends problem is not tmique to the
RX02 and has also been noted when using RX01's.)
EVALUATION
Media reliability is uncertain when usjng diskettes other than those
recommended by DIGITAL. Customers buying cheap, low quality diskettes
will frequently encotmter unreliable media.
SOLUTION
DIGITAL recommends the use of only DIGITAL or IBM diskettes with the
RXD1 or RX02. This is especially true where the diskette is used
frequently, such as a system device. 1be following note is repeated
from Section 2.3.5 of the RX02 User's Guide.

mTE:

Removable media involve use, handling, and
maintenance which are beyond DIGITAL's direct
control. DIGITAL disclaims responsibility
for performance of the equipment when
operated with media not meeting DIGITAL
specifications or with media not maintained
in accordance with procedures approved by
DIGITAL. DIGITAL shall not be liable for
damages to the equipment or to media resulting from such operation.

~D~I~D~D
COMPONENTS
GR()UP
2316

NUMBER

)lnote
TITLE

082
DATE

Handlers for Serial Line Printers

DIS1RIBUTION
ORIGINATOR

8/ 27 /

PRODUCT

Unrestricted

Serial Printers

Barry Maskas
PAGE 1 OF 11

THE FOLLOWING IS A SUMMARY OF METHODS FOR PERMANENTLY
MODIFYING THE RT-11 V03.00B LP HANDLER TO SUPPORT
SERIAL LINE PRINTERS VIA A DLV11 FAMILY INTERFACE.
METHOD ONE
TO SUPPORT LA34 OR LA36 ASCII TERMINALS:
1.DETERMINE THE XBUF CSR ADDRESS AND VECTOR
2.PERFORM THE FOLLOWING MONITOR SET COMMANDS:
.8ET LP CR
.8ET LP LC
3.RUN THE PATCH UTILITY:
.R PATCH
FILE NAME-"*LP.SYS
NOTI: Enter new
xcsr~ VECT()r~
*10001 200
XCSI vector and
XCSR ADDRESS
*10541 177514
acldl'ess and XBUF
XBUF ADDRESS
*12041 177516
acciress.
*E
THE MODIFIED HANDLER CAN BE COPIED TO OTHER SYSTEM
DISKS WITH THE COMMAND:
COPY/PRE/SYS LP.SYS DEV:
·NOTES: EVEN WITH THE DLV11 CONFIGURED AT THE LINE
PRINTER ADDRESS THE ABOVE PATCH IS NECESSARY. WHEN
INTERFACED IN THIS MANNER, THE LP HANDLER CANNOT
DETECT POWER DOWNt OFF LINE, OR PAPER OUT CONDITION;
OUTPUT SENT TO THE PRINTER UNDER THESE CONDITIONS
WILL BE LOST WITHOUT WARNING.
THE STANDARD LP HANDLER DOES NOT PROVIDE XON/XOF
HANDSHAKING OR FORM FEED EMULATION. THE FORMER
MUST BE USED IN CONJUNCTION WITH LA120,LS120 AND
SERIAL LA180 IF IT IS TO BE RUN AT ITS MAXIMUM
SPEED()2400 BAUD; 9600 BAUD RECOMMENDED FOR LA120
AND LA180, 4800 BAUD FOR LS120). THE LATER MAY BE
USED WITH AN LA34,LA35 OR LA36 IF THE LP HANDLER
IS TO EMULATE THE FORM FEED FUNCTION NOT PRESENT
ON THESE TERMINALS. BOTH OF THESE OPTIONS CAN BE
REALIZED WITH THE FOLLOWING LP HANDLER.

~DmDDmD
COMPONENTS
CiROII»

237

NUMBER 082
PAGE 2 OFll

METHOD TWO
TO ASSEMBLE AND INSTALL THE LINE PRINTER DRIVER ON YOUR
SYSTEM THE FOLLOWING IS NECESSARY:
1.REMOVE THE OLD LP HANDLER I.E.,'REM LP:'
2.DELETE THE OLD LP HANDLER I.E.,'DEL/NOQ/SYS LP.SYS'
3.EDIT THE FILE: SYCND.MAC, TO REFLECT YOUR
SINGLE PRINTER SUPPORT INFORMATION I.E.,EITHER
LA180 OR LA35, AND THEIR ADDRESS/VECTOR.
4.RE-ASSEMBLE AND LINK THE DRIVER. REFER TO THE
ENCLOSED INDIRECT COMMAND FILE: LPDRV.COM
5.INSTALL LP.SYS VIA:'INS LP:'

LPDRV.COM

*********
MAC/LISTlSY:LP/OBJ:LP SYCND+LP
LINK/EXE:LP.SYS LP
DEL/NOQ LP.OBJ
SYCND.MAC
.SBTTL.. SYSTEM CONDITIONAL FILE
SYSG$N =
1
TIME$R =
1
RDF~fi.L

CLOCK
STAI~$T
PWF~J;L
ESC~t)P

$DYSYS
DY$CSR
DY$VEC
L$$:L80
LP$CS~~

LP.B
LP$VEC
LP.VEC

=
=
=
=
=
=
=
=
=
=
=
=

60.
1
1
0
1
17'7170
264
1
177514
177514
204
204

This SYNCD.MAC file is provided as an example. Your system device will
contain a file with this title if you SiSGEN'd and you should reference
it in the above procedures.
'

~DmDDmID
COMPONEIm
GROUP
238

)./note

NUMBER 082
PAGE 3 OF 11

THE ABOVE SYCND FILE IS FOR LA180 OR LS120 SUPPORT
IT CAN BE EDITED TO REFLECT LA3X SUPPORT USING THE
FOLLOWING SYMBOL DEFINITIONS:
L$S180
DEFINE THIS SYMBOL IF YOU
WISH LA180 OR LS120 SUPPORT
L$$35
DEFINE THIS SYMBOL IF YOU WISH
LA35,LA36 OR LA30 SUPPORT
MS$RGN
USED IN CONJUNCTION ONLY WITH
L$$35 SYMBOL TO DEFINE THE
MARGIN TO BE USED BETWEEN PAGE8.
IF NOT SPECIFIED;DEFAULT TO SIX
LPSCSR
XBUF CSR ADDRESS, THE DEFAULT IS
STANDARD LP CSR ADDRESS=177514
LP$VEC
XBUF VECTOR ADDRESS, THE DEFAULT
IS STANDARD LP VECTOR=200
LP.CSZ
THE COLUMN WIDTH OF THE OUTPUT DEVICE
IF NOT SPECIFIED, DEFAULT IS 132. COLUMNS.
FOR LA30 SUPPORT SET THIS SYMBOL TO 80. OR
USE THE '8ET LP: WIDTH=80' COMMAND
THE FOLLOWING KMON 'SET' COMMAND IS AVAILABLE WHEN THE LINE
PRINTER IS ASSEMBLED FOR LA35 SUPPORT:
SET LP: PAGE=NN ;8ET PAGE SIZE NOT INCLUDING MARGIN
THE DRIVER DEFAULT VALUE IS 61. THE TARGET IS THAT THE VALUE
OF M$.RGN (DEFAULT 6) PLUS THE PAGE SIZE (DEFAULT 61) MINUS ONE IS
THE SIZE OF A PAGE IN LINES (DEFAULT RESULTING VALUE IS 66.) •
• TITLE LP
V03.03
.IDENT IV03.031
; FZ033--ADDED LA180S (AND LS120) SUPPORT
;
ADDED LA35 (AND LA30,LA36) SUPPORT
; ADDITIONAL AMENDMENTS FOR XON AND XOF INCLUDED
;RT-l1 LINE PRINTER (LP/LS11) HANDLER
,

; DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS 01754

; THIS SOFTWARE IS FURNISHED UNDER A LICENSE FOR USE ONLY
; ON A SINGLE COMPUTER SYSTEM AND MAY BE COPIED ONLY WITH
; THE INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE,
; OR ANY OTHER COPIES THEREOF, MAY NOT BE PROVIDED OR OTHERWISE MADE
; AVAILABLE TO ANY OTHER PERSON EXCEPT FOR USE ON SUCH SYSTEM AND TO
; ONE WHO AGREES TO THESE LICENSE TERMS. TITLE TO AND OWNERSHIP OF THE
; SOFTWARE SHALL AT ALL TIMES REMAIN IN DEC.

; THE INFORMATION IN THIS SOFTWAF\E IS SUB.JEer TO CHANGE
; WITHOUT NOTICE AND SHOULD NOT BE CONSTRUED AS A

mDmDomo
COMPOMENTS
GROUP
239

NUMBER 082
PAGE 4 OF 11

;COMMITMENT BY DIGITAL EQUIPMENT CORPORATION.

;DEC ASSUMES NO RESPONSIBILITY FOR THE USE OR
;RELIABILITY OF ITS SOFTWARE ON EQUIPMENT
;WHICH IS NOT SUPPLIED BY DEC.

;SYSTEM GENERATION OPTIONS:
.IIF
NDF
MMGST, MMGST=O
.IIF
NDF
ERLSG,ERLSG=O
.IIF
NDF
TIMSIT, TIM$IT=O
.QELDF
;DEFAULT CONTROL REGISTER DEFINITIONS
.IIF NDF LPSCSR, LPSCSR==177514 ~STANDARD LP CONTROL REGISTER
.,1 IF NDF LF'~~VEC, LF'SVEC==200
; STANDARD LP VECTOr~
LPDSIZ
.IIF

=0
NDF

~DEVICE BLOCK SIZE (0 IF NONFILE-STRUCTURED)
LPSTS,LPSTS=20003 ~DEVICE STATUS (WRITE ONLY)

;CONSTANTS FOR MONITOR COMMUNICATION
HDERR
=1
;HARD ERROR BIT
V.MAX
=500
;MAXIMUM VECTOR
;ASCII

CONSTANTS

CF~

=3.5

=1:~~

FF
HT

=14
=1Jl.

IF DF

L$~;:L80

CNTF~LC:~
CNTF~L.S

=2:l
=23

;XON CHARACTER
; XDFF CHAr~ACTER

.ENDC
;DEFAULT COL.UMN SIZE DEFINITION
.IIF NDF LP.CSZ,LF'.CSZ=132. ~DEFAULT IS 132 COLUMNS
COLSIZ ::::=LF'.CSZ
.IF
DF
L$$35
;DEFAULT MARGIN SIZE IF NOT SPECIFIED
.IIF NDF M$$RGN, M$$RGN = 6 •
• ENDC

~~lmDDmD
COMI~

GROUP
240

)lnots

NUMBER 082
PAGE 5 OF 11

;THE FOLLOWING ARE THE PARAMETERS FOR INTERFACE TO THE MONITOR ·SET a
;COMMAND
.ASECT
.=400
.IF DF L$$35
.WORD
M$$RGN ;MINIMUM PAGE HEIGHT
• r~AD50 IF'AGE I
.WORD
(0.PAGE-400)/2+40000 ;NO 'NO' OPTION, NUMBER REQUIRED
.ENDC
.WORD
• f~AD50
.WORD
NOP
• RAD50
.WORD
NOP
• RAD50

30.

;MINIMUM WIDTH

IW I DTH I

(O.WIDTH-400)/2+40000

;NO 'NO' OPTION, NOMBER REQUIRED

;NO CR =) NOP CROPT
ICF~

I
(O.CR-400)/2+100000

;ALLOW 'NO'

~WORD

;NO FORMO =)NOP FFOPT
IFDr-\:MO I
(Q.FORMO-400)/2+100000 ;ALLOW 'NO'

8MI
• RAD~;O
.WORD

LF'ERR-ERROPT+. ;NO HANG BY GOING TO ERROR
IHANG I
(O.HANG-400)/2+100000 ;ALLOW 'NO'

.WORD
• F~AD50

~WORD

(O.LC-400)/2+100000

ILC

;FOR NO LC, CONVERT LC TO UC
I

8NE

IGNORE-CTROF'T+.

+ F~AD50

ICTF~L

;IGNORE CTRL CHAR IF NOCTRL

.WORD

(O.CTRL-400)/2+100000

SEQ
• F~AD50
.WORD

TABSET-TABOPT+.
ITAB
I

(0.TAB-400)/2+100000

.WORD

;SIMULATE TAB IF NOTAB

;END OF LIST

~DmDDmD

~
241

NUMBER 082
PAGE 6 OF 11

,THE FOLLOWING 'SUBROUTINES' SERVICE THE 'SET' COMMANDS
,TYPED TO KMON TO ALTER'SEVERAL OPTIONS IN THE DRIVER (
;SUCH AS PAGE HEIGHT, COLUMN WIDTH, 'WRITE-ALL' MODE, ETC.)

O.WIDTH:MOV
RO,COLCNT
MOV
RO,RSTC+2
• IF DF L!t>$35
MOV
RO,VTLOOP+2
.ENDC
1;:0, R3
eMP
I~TS
PC
.IF
O.PAGE: MOV
MOV
eMP

F~ETur~N

,NEW WIDTH TO 2 CONSTANTS
;NEED IT IN 3 PLACES HERE
,ERF~OR

L~~$35

JClF

I:~O, $PAG~
I~O,

IF <30.

,SET PAGE SIZE
,INTO TWO PLACES
,BUT DON'T ALLOW NUMBERS LESS M$$RGN

$HOLD

I~O"r-i:3

.ENDC
c). CFn

MDV

(PC)t,R3

BE(~

IRSTc-cr~OPTt

MOV

R3,CROPT
PC

I~TS

,SET TO DO FORMFEEDS ON BLOCK 0

,SET TO HANG

F~TS

(PC)t,R3
RET-'ERROPT+ •
R3"ERROPT
PC

cl...r~

F~3

,FOR 'LC', LEAVE LOWER CASE STUFF ALONE

BE(~

MOV
r-i:TS

O.LC:

MOV
BMI
MOV

NOP
MOV
r~TS

O.CTRL: MOV
BNE
MOV
I~TS

O.TAB:

;SET CR OPTION

(PC) +, r~3,
BLKO-FFOPTt.
F~~~, FFOPT
PC

O.FDRMO:MOV

1]. H,elNG:

,NO 'NO', SO SET TO DO CR
•

MOV
BEt~

MOV
r~TS

R3,LCOPT
PC
(PC)t,R3
PC1-CTROPTt.
r~3, CTROPT
PC

,SET TO PASS ALL NON-PRINTING CHAR

(PC)t,R3
;PASS TAB DIRECTLY TO LP
HDWTAB-·TABOPTt.
R3,TABOPT
PC

multlmmo
COMPOIerrs

CiIlOII»
24~~

).Inote

NUMBER 082
PAGE 7 OF 11

;LOAD POINT
.IF NDF L$$180
~NO TABLE IF NOT DEFINED
.DRBEG LP,LPSVEC,LPDSIZ,LPSTS
.IFF
~OTHERWISE INCLUDE TABLE FOR 2 VECTORS
.DRBEG LP,LP$VEC,LPDSIZ,LPSTS,LPTAB
.ENDC
;ENTRY POINT
MOV
LPCQE,R4
ASL
6(R4)
.IF NDF L$$180
BCC
LF'ERR
BEQ
LPDONE
.IFF
98$
BCS
JMP
LPEF~F~
99$
BNE:
.JMP
LF'DONE

jR4 POINTS TO CURRENT Q ENTRY
;WORD COUNT TO BYTE COUNT
;A READ REQUEST IS ILLEGAL
;SEEKS COMPLETE IMMEDIATLY

<,.9$ :

.ENDC
i=<ET:

1$:

.IF DF L$$180
MTPS
:1:340
TST
XOF
BNE
1$
.IFTF
BIS
;CAUSE AN INTERRUPT,STARTING TRANSFER
.IFT
MTPS
to
BIS
tl00,@tLP$CSR-4 ;INTERRUPT ENABLE INPUT SIDE
.ENDC
RTS

.IF DF L$$180
;XON/XOFF REQUIRE TWO VECTORS AND ISR'S, INCLUDE THE TABLE
I...F'TAB:

tWORD
• WORD
.WORD
.WORD
• WORD
.WORD
.WORD

LF'~~VEC-'4

LRINT-' •
340
LP$VEC
LPINT- •
340

~OTHER IS INPUT SIDE
;OFFSET TO INPUT ISR

; pr~7

;FIRST IS OUTPUT VECTOR
,OFFSET TO IT'S ISR
jPR7
;E-O-T

~DmDDmD

COMPONENTs
GROUP
243

NUMBER 082
PAGE 8 OF 11

,.+
,
; **-'LRINT
;INPUT SIDE INTERRUPT SERVICE ROUTINE. IF WE RECEIVE AN XON
;WE SET THE INTERRUPT ENABLE ON THE OUTPUT SIDE. IF WE RECEIVE
;AN XDFF, WE rURN OUTPUT I.E. OFF. IF A JUNK CHARACTER IS SEEN
;WE THROW rT A~AY AND ASSUME THE 'USER IS TRYING TO TYPE WHILE
;WE ARE.
; ..
;;;AST ENTRY POINT
.DRAST UR,4,LRDONE
@:I:LP$CSR-2, R4
;;;PICK UP CHARACTER TYPED
MOVB
;;;INSURE WE GET ONLY 7-BITS
:JI:177600,R4
BIC
:fI:CNTRLQ,R4
;;;WAS THIS AN XON?
CMP
;;;IF EQ YES, ENABLE OUTPUT SIDE
BNE
CL.R
XDF
BR
REiT
:JI:CNTRLS,R4
;;;WAS THIS AN XOF1
2$:
eMF'
1.$
;;;IF NE NO, IGNORE CHARACTER AND GO
BNE
:U::l,XOF
MOV
@*LPSCSR
;;;IF EQ YES,TURN OUTPUT SIDE OFF
CLf~
:fI:l00,@tLP$CSR-4 ;;;AL.WAYS RE-ENABLE SELF
1.$:
BIS
I:~TS
PC
;;;AND RETURN TO MONITOR
@1L.P$CSR-4
;;;INTERRUPT DISABLE ONLY
RDONE: CLR
~

RTS

;;;

.ENDC

;+
y **"-L.PINT
~THIS IS THE OUTPUT INTERRUPT SERVICE ROUTINE.
PICK UP CURRENT
;PACKET, GET-BYTE, AND SEE IF CHARACTER REQUIRES SPECIAL PROCESS
;SUCH AS THE FF AND TAB •

• ENABL
• IF

Et~

LSB
MMG~~T

~IFTF

• nR{~ST
MOV

.IF
TST
tIFF
CLN
BF~

.ENDC
I...PS:

• wor~D

LP,4,LPDONE
LPCQE,R4
NDF
L ~;'$180
@.(PC)t

;R4 -)CURRENT QUEUE ELEMENT
;ERROR CONDITION?

ER:ROPT
LF"$CSR

;L.INE PRINTER STATUS REGISTER

mDmDomo
COMPCHNTS
CiRC)UP

244

NUMBER 082
PAGE 9 OF 11

ERROF'T: BMI
TSTB
BF'L
CLR
.FORK
TST
FFOPT: BEQ
LPNEXT: TSTB
BF'L
ASLB
TABFLG: • WOr~D
BNE

RET
@LPS
RET
@LF'S
LPFBLK
(R4)
BLKO
@LPS
RET
(PC)+

iYES-HAN6 TILL CORRECTED
iIS IT READY
;NO,RETURN
;YES, DISABLE INTERRUPTS
i REQUEST A SYSTEM PROC,ESS
;IS THIS BLOCK O?
;YES-OUTPUT INITIAL FORM FEED
iREADY FOR ANOTHER CHAR YET?
;NOPE-RETURN FROM INTERRUPT
;TAB IN F'RIGRESS?

TAB

;BRANCH IF DOING TAB

+IF [IF L$$35
DEC
$SKIP
BGT
VTLOOP
+ENDC

iAN I IN MIDDLE OF LF STREAM?
;IF 6T YES, CONTINUE TILL DONE

6(R4)
LPDONE

iANOTHER CHARACTER TO TRANSFER?
;BR IF NOT, XFER DONE

@4(R4) ,r~5
4(R4)

iGET NEXT CHAR (IF ANY)
;BUMP BUFFER POINTER

F'C,@$GTBYT
(SP)t,R5

;6ET A BYTE FROM USER BUFFER
;PUT IN r~5

6(R4)
t177600,R5
t40,R5
CHRTST
(PC)+,R5

;BUMP CHARACTER COUNT
;7-BIT
;PRINTING CHAR?
iNO-GO TEST FOR SPECIAL CHAR.
;LOWER CASE?
;NO
;YES,CONVERT IF DESIRED

(F'C)+
COLSIZ
IGNORE
(PC)+

;ANY ROOM LEFT ON LINE?
;t OF PRINTER COLUMNS LEFT
;NO MORE ROOM ON LINE,DON'T F'RINT CHAR
;UPDATE TAB COUNT

I GNOI:;:E: TST
BEQ
.IFT
MOVB
INC
+IFF
JSR
MOV
.IFTF
INC
BIC
eMF'B
BHI
CMF'B
BHIS
SUB
LCOPT: 40
PCHAR: DEC
COLeNT: .WORD
BLT
ASLB
TABCNT: .WORD
BEQ
PC1:
MOVB
LF'B:
.WORD
BR
CHRT'ST: CMPB

t140,r~5

F'CHAr~

RSTTAB
R5,@(PC)+
LF'$CSR+2
LPNEXT
tHT,R5

;RESET TAB
;PRINT THE CHAR
iLINE PRINTER BUFFER REGISTER
;TRY FOR NEXT CHAR
;IS CHAR A TAB?

~DmDDmD

COMPONENTS
GROUP
245

NUMBER 082
PAGE 10 OF 11

TABOF'T: BEO
TABSET
tLF,R5
CMPB
.IF [IF L.$$35
BEO
PGCNT
.IFF
BEQ
RSTC
.ENDC
tCR,R5
eMF'B
.IF DF L$$180
CROPT: BE(~
r';:STC
.IFF
CHOPT: NOP
.ENDC
CMPB
R5,iFF

jYES-RESET TAB
JIS IT LF1
jIF EO YES,COUNT NUMBEr~ OF LINES
j YES-r~ESTORE COLUMN COUNT
L$$35

jREASONABLE DEFAULT FOR LA35/LA180S
jIGNORE UNLESS MODIFUED
JIS IT A FF1

.IF [IF L$$35
FFFLT
.ENDC

jIF E(~ YES, SPACE UP PAPER RIGHT

BEC~

CTIi:OPT: BNE
IGNORE
.IF DF L$$35
F'GCNT: [lEC
$PAGE
BEO
PGFLT
+ENDC
F~BTC :
MOV
tCOLSIZ,COLCNT
I:~STTAB : MOV
il,TABCNT
BF~
PCl
TABBET:MOV
TAB:
MOV
BF~

1··II:tWTAi:{: ASLB

TABCNT,TABFLG
:ft:40,R5

jNO-CHAR IS NON-PRINTING
;KEEP TRACK OF NUMBER OF LINES
jIr EO THEN PAGE FAULT, DO SKIPS
jRE-INITIALIZE COLUMN COUNTER
jRESET TAB COUNTER
; Pf;: I NT THE CHAR
JSET UP TAB
;PHINT SPACES

PCHAF~

TABCNT

BEt~

r~STTAB

DEC
BR

COLeNT
HDWTAB

jADJUST TAB COUNT
;IF EO, RESET TAB COUNT
jELSE ADJUST COLUMN COUNT
jCONTINUE UNTIL NEXT TAB POSITIO

+ IF DF L$~)35
MOV
$PAGE,$SKIP
ADD
tM$$RGN-l,$SKIP
MOV
SHOLD,$PAGE
BR
VTLOOP
PGFLT: MOV
$HOLD,$PAGE
MOV
tM$$RGN,$SKIP
VTLOOP: MOV
tCOLSIZ,COLCNT
MOV
tl,TABCNT
MOV
tLF,R5

FFFLT:

;IS IT CR1

'NUMBER OF LINES LEFT IN PAGE
jPLUS SKIPPING OVER THE BOUNDARY
;RESET NUMBER LINES/PAGE
;GENERATE CORRECT NUMBER OF LF'S
jRESET LINES/PAGE COUNTER
;DO M$$RGN LINES BETWEEN PAGES
jRESET FORM WIDTH
jRESET TAB COUNTER
;PRINT LINE FEEDS

~D~DDmD
COMPONENTS
GROUP
246

NUMBER 082
PAGE 11 OF 11

BR
.ENDC
BI...KO:

I... PEf~r< :

PCl

;UNTIL NO MORE SKIPS TO DO

@R4
INC
tFF,R5
MOV
.IF DF L.$$35
Bf<
FFFLT
.IFF
BR
RSTC
.ENItC
tHDERf<, @.- (r~4 )
BIS
.ENDC
.DSABL LSB

;MAKE SURE WE ONLY COME HERE ONCE
;PRINT INITIAL FF
;SKIP REQUIRED NUMBER OF LF'S

;S£T HARD ERROR BIT

,OPERATION COMPLETE
I...PDONE:
.IF DF L$$180

:
~I~HOLD :
~I;SKIP :
~I~F'AGE

CLR

t~tLP$CSR-4

;TURN INPUT INTERRUPTS OFF ALSO

.ENDC
CLR
.Df<FIN

@LPS
LF'

;TURN OFF INTERRUPT

.IF DF L$$35
.WORD
61 •
• WOr~D
61.
.WORD
0•
• ENDC

LPFBLK: • WOF~D
.IF
XOF:
.WORD
.ENDC
.DREND

;LINES/PAGE DEFAULT TO THIS
;LINES/PAGE HOLDER
;iOF LINES BETWEEN PAGES COUNTER
;FORK BLOCK

0,0,0,0

L$$:l.80

LF'

tEND

~DmDDmD
COMPONENTS
CROUP
247

NUMBER

).Inote

083
DATE

TITLE Alternate Clock Freguencies for the MXV11
DIS1RIBUTION

MXV11 Users

ORIGINATOR

Charlie Giorgetti

9/ 05

/79

PRODUCT

MXV11-M, -AC
PAGE 1 OF 2

The purpose of this Micro Note is to define frequencies, other than the standard
60Hz., that can be obtained from the MXV11 to be used as the BEVNT clock. The
frequencies defined are 50Hz., 300Hz. and 2.4KHz.
The 50Hz. clock is obtained from the MXV11 by replacing one chip. The chip that
must be changed is in an IC socket, making replacement simple. In location XE70
(see attached figure) of the board layout is a 74LS90; it is replaced pin for pin
with a 74LS92 to obtain the 50Hz. clock.
To obtain the 300Hz. clock from the ~~1 involves the removal of one chip and
connecting two pins left by the removed chip. The chip that is removed is the
74LS90 at location XE70. The removed chip is replaced with a 14-pin component
carrier. The component carrier allows pin 1 and pin 8 of the IC socket (see
attached figure) to be connected, without damage or pennanent alternations being
done to the actual board itself.
The 2.4KHz. signal can be obtained from the MXV11 by removing one chip and
co:rmecting a wire wrap jumper to a pin location left by the removed chip. The
74LS90 is removed from the IC socket at XE70 and is replaced with the component
carrier. Pin location 8 of the carrier is connected to wire wrap pin J41.
NOTI3S
1.

The operating systems RT-ll and RSX-11 run at either 50Hz. or 60Hz.

Since these are non-standard configuration changes, it is recorrnnended that
the MXV11 be returned to its original configuration prior to returning it
for repair in order to prevent it from being rejected by the DIGITAL
repair center.

~DI~DD~D
COMFONENTS
GllOUP

248

NUMBER 083
PAGE 2 OF 2

SOCKET XE70

WIRE WRAP PIN J41
--l-

5 ~
10
-...]
6

PIN ASSIGNMFNfS

LOCATION AND PIN ASSIGNMENTS OF XE70 ON THE MXV11

~D~DDmD
COMPONENTS
CiROUP
249

).Inote

NUMBER

084
DATE

TITLE

Improved DLVII-F

DISTRIBUfION

Unrestricted

ORIGINATOR

Barry Maskas

/ 79

PRODUCT

DLVII-F
PAGE 1 OF 2

The DLV11-F OM8028) has been re-etched due to some improvements in the optical
isolation 20ma receive circuit and the ·-12V charge pump circuit. The logical
jumper functions are unchanged and are explained in the 1978-79 Memories and
Peripherals Handbook, however, the physical location of these jtunpers on a
board is shown in the diagram.
To use this board. for a 20ma interface lNith a TTY, ensure that capacitor C29
(O.OOSUF) is installed as shown in the diagram.

mD~IDDmD
COMPC)NEMTS
GRC)UP
2S0

NUMBER 084

PAGE 2 OF 2

- - - nI
\Jl

L-____~-------- ~ '-----==----.

Ln
N

o
o
w

,....

....

-f

(1"

U- .,

-{:

I...
B

251

J)-

NUMBER
085

)lnote
TITLE

DATE
10 /29

WAKE-UP CIRCUIT IMPLEMENTATIONS

DISTRIBUTION

UNRESTRICTED

ORIGINATOR

RICK PLUMMER

/79

PRODUCT
LSI-l1/2, LSI-ll/23
PAGE 1

OF 2

PURPOSE OF THE WAKE-UP CIRCUIT
The wake~up circuit is included on the LSI-l1/2 and LSI-l1/23 processors in order
to allow users to implement small systems without the need for more complex power
sensing circuitry. Small systems are those which do not contain disk mass storage
devices. Systems containing disks as well as those containing non-volatile read/
write memory (i.e. core or battery backed-up RAM) or other devices depending on
both DCOK. and POK or power failure detection for proper system operation should
utilize the full power sequencing implemented with a Digital Power supply, KPV11
module or other means. When using the full power sequencing the processor, onboard wake-up circuit should be disabled. This will be discribed later in this
note.
For reference purposes, the wake-up circuit description from the Microcomputer
Processor Handbook is reprinted below.
Wake-Up Circuit - The wake-up circuit
causes
the LSI-11 processor to self-initialize during pOWtlf-Up. An R-C circuit
recoives + 5 V operating power when power is turned on. When power
is first applied, the low capacitor vCI~reirtiilJ.ses the Schmitt trigger's
output to go high and the bus driver'"
A
·t1le BOCOK H signal (low).
Aftor power has been applied for approximately 1 second, the capacitoris voltage rises above the Schmitt trigger's threshold voltage, and its
output goes low. The low voltage turns off the bus driver, enabling
BOCOK H to become asserted. The processor then starts its initialization
sequence if no other device is asserting BOCOK H. Proper: i~itialization
requires that + 12 V operating power be applied within 50 ms of + 5 V
I
operating power.

.........~

L,!:1T-IVzJ

'~Ir- -,-l~.I
I

+5v--&f--ItN'

D,II

SCHMITT

T'''GGEII

l' -.---

BOCOKH

Normal operation of the wake-up circuit depends on the rise time of the
+ 5 V power supply being faster tt1an 50 ms. The + 12 V power supply
also must attain its specified operating voltage in the same 50 ms. The
wake-up circuit does not provide power failure detection nor powerdown sequencing. These functions. if required. must be generated externlilly.

~D~DD~D
COMPC:»IEMTS

GROUP
252

)Jnote

NUMBER
PAGE 2 OF 2

The circuit is the same for both processors, although physical implementation is
di fferent as described below.

LSI-ll/2
The wake-up circuit,as shown in the figure, is fully implemented and the module is
shipped with the wake-up option fully functional.
To disable the wake-up function, remove capacitor C81 by cutting its leads at the
board.

LSI-ll/23
The wake-up circuit on the LSI-l1/z3 is the same as shown in the figure.
It is shipped with a red wire accross diode 01, thus disabling the circuit.
To enable the wake-up circuit, remove the red wire accross diode 01 by cutting at
the board. Be careful not to damage the diode.
Some early revIsion modules were shipped without the wire. A later revision will
change this wire to a jumper strap at some time in the future.

~DmDD~D
COMPONENTS
GROUP

253

)./note
TITLE

INTERFACING TO THE TU58 WITHOUT BREAK

DISTRIBUTION
ORIGINATOR

NUMBER
086

DATE
1

UNRESTRICTED

/ 80

PRODUCT
TU58

JON TAYLOR

PAGE 1

OF 2
,e:Jp

The controller of a TU58 intelligent tape cartridge system can be connected to any
serial interface that conforms to RS-422, RS-423 or RS-232C interface standards.
This allows aTU58 drive to be connected to any non-DEC host computer that provides
these interfaces. The TU58 can be connected to such a host even though its
'interface is incapable of transmitting a break ("space" condition) to the controller.
This article explains the hazards involved with using such an interface.
The TU58 DECtape II User's Guide (EK-OTU58-UG) describes the radial serial protocol
that ~s used by a processor to communicate with a TU58 controller. The protocol
uses a break signal to initialize the controller in much the same way as the LSI
bus BINIT signal is used to initialize devices on the bus. Regardless of the state
of the line protocol (and the controller), the controller will always detect the
break signal as it is routed to the controller's "non-maskable interrupt".
Break is normally used in two situations:
1.

On power-up, the TU58 continuously sends INIT bytes to the ho~t. The
host sends break and two INIT bytes. The TU58 responds with a CONTINUE
byte and is ready for use.

If communications break down due to a protocol, line, or TU58 error, the
host can restore order by sending a break and two INIT bytes. As above,
the TU58 will respond with a CONTINUE and wait for further instructions.

In situation one, a host without break capabilities would send just one INIT byte
and the TU58 will respond in the usual way with a CONTINUE. The host should be
prepared to ignore one or two INIT bytes that may be seen before the CONTINUE byte
(due to UART buffering).
The absence of break in the second situation is the cause of less reliable operation.
In most cases, the standard checksumming of messages and protocol handshaking will
detect a protocol or line error and the state of the protocol will be known.

mDmDomo

MICROCOMPUTER
PRODUCTS
GROUP
270

)lnote

NUMBER 086
PAGE 2 OF 2

To reset the TU58, the breakless host would send one INIT'byte and wait for a
CONTINUE byte response. However, in the case that an error occurs while the host
is sending a packet to the TU58, more than one INIT must be sent, as the TU58
can not distinguish the INIT from the packet it is expecting. There is a very
slim chance in a write operation (one in 65536) that when the TU58 interprets
two of the INIT's as a checksum word, the checksum will actually be correct and
an erroneous write will occur.
Very infrequently, communications may break down due to a TU58 controller malfunction (caused by power glitches or noisy environments). Without break, the
only way to reset the controller is to power it off and on.
To avoid a possible malfunction because the controller can not be initialized,
Digital recommends that all serial interfaces to the TU58 be capable of generating
a space condition.

~D~DDmD
MICROC4)MPUTER
PROII)UCTS
CiR4)UP
271

NUMBER
0087

)lnote
TYPE-IN BOOTSTRAP FOR TUS8

TITLE

DATE
12 / 18

/79

PRODUCT
TUS8

DISTRIBUTION

UNRESTR I CTED

ORIGINATOR

CHARLIE GIORGETTI
PAGE 1 OF

1
~

The following is a short type-in bootstrap for the TUS8. This code, using the
TUS8 bootstrap command reads block 0 from the TUS8 drive o. It then executes
from location 0 in memory. This code will boot an RT-l1 TUS8 system, an RSX-l1S
System, or suitable user-written software.
To implement the boot, all interrupts must be inhibited. This can be done under
ODT, enter $S/ ______ 340 (CR). The stack pointer and program counter must be
initialized. Under ODT enter R6/ ______ 1000 (LF), R7/ ______ 1000 (CR). Type
in the bootstrap starting at 1000 and type P.

001000
001004
001.01.0
001.012
001014
001016
001020
001.022
001.024

012701
012702
010100
105712
100376
006300
001.00:.;
00:.;01.2
() 1. 270·)

';)0103:2
':)01.036
001.042
001046

00::j)'61
042700
01.0062
00:l.3t.,:::
00:.;003
105?1:1.

0010~;0

00:1.0:;1.:-

00J.062
00106&,
001070

START:

00~;212

')0 1 ()2,!~,

001052
0010::;4

176500
176504

WAIT1:

00000'.

ooooo:?
000020
000002

WAIT2:

10037 t)

11.6123
022703
101371
005007

XBYT:

000002
001000

MOV t176500,R1
MOV t176504,R2
MOV R1, f,O
INC ( FC )
TSTB (R2)
BF'L WAIT1
ASL RO
BNE XBYT
elF.: ( F.::.' )
MOV t4 ~ F:O
TST .2(R1)
BIC t20,RO
MOV RO,2(R2)
BNE WAIT1
elR R3
TSTB (Rl)
BF'l WAIT2
MOVB 2(Rl), (F.'3d
eMF' tl000,R3
BHI WAIT2
ClR PC

momoomo
MICROCOMPUTER
PRODUCTS
CiROUP
27'2.

;INIT RCSR ADDR
;INIT X,CSR ADDF.:
;INIT BREAK COUNTEF.:
;SET BREAK
;TEST FOR READY
;WAIT FOR READY
;SHIFT COUNTER
;NOT ZERO, XMIT
;ZERO~ CLEAR f<RE r~l-<
; ~;ET-"UF' INIT,f:ocn CClUNTEF:
; DUMF' F,[CIEVEF, BUFFEF:
;ClEAF: AFTER BOOT CODE
;XMIT CHAR
;IF ZERO NOT XMITTED
;ZEFW, INIT MEM POINTER
nTST FOF: READY
;WAIT FOR READY
;PUSH BYTE INTO MEM
;512 BYTES RECEIVED
;IF NOT lOOF'
;IF YES EXECUTE AT 0

).Inote
TITILE

RT-11 V3B FB MONITOR AND TUSS's

DISTRIBUTION

UNRESTRICTED

ORIGINATOR

JON TAYLOR

NUMBER
nB&

DATE
1

/80

PRODUCT
TUS8

PAGE 1 OF 1
~Rt-"

Users of RT-11 V3B and TUS8's should be aware that I/O errors on TUS8 access
or total system failure may occur under the following conditions.
1.
2.
3.

11 /03 p ro ce s so r
Serial line interface to TUS8 controller runs at 38.4K baud
RT-11 V3B foreground/background moni tor

This is due to a timing problem internal' to the RT-11 FB monitor.
The May 1979 RT-11 Software Dispatch (AD-C740B-13) contains two binary patches
(sequence numbers 20M or 22M) which, when applied, will remedy the problem.
In the same issue, note that optional performance improvement patches 210 and
230 apply only to PDT, 11/03, 11/23 and 11/34 processors. Once patched, the
software can not be run on other than the above processors.

~D~IIDmD
MICROCC)MPUTER
PROI)UCTS
GRC)UP
273

NUMBER

).Inote
TITLE

089

DATE

STANDALONE PROGRAM LOADER

DISTRIBUTION

UNRESTRICTED

ORIGINATOR

JON TAYLOR

3 / 04

/ 80

PRODUCT
DEVELOPMENT SYSTEMS

PAGE 1 OFS
E"BP

This micro note includes a 1 isting of a program l~ader ("LOADER IJ ) that runs as a
background job under RT-11. LOADER is useful to customers who are developing and
debugging standalone FORTRAN IV and/or MACRO-l1 programs (that is, programs which
run without operating system support). LOADER will read any memory image file
(.SAV file) from any RT-11 supported device into memory (overwriting RT-11), and
Ibegin its execution. No hardware bootstraps are required to debug the program.
The .SAV file needs no special processing before loading. The RT~ll assembler and
linker cooperate to produce the standalone file with no special commands. For example,
consider the following standalone FORTRAN program, called IITEST.FOR'I:
10

IF «IPEEK(1I177560).AND."200) .EQ. 0) GOTO 10
ICHAR = IPEEK(1I177562) .AND. 255

IF «IPEEK(1I177564).AND. 1J 200) .EQ. 0) GOTO 20
CALL IPOKE(1I177566, ICHAR)
GOTO 10
END

The following commands will produce a standalone image:
. FOR TEST
.LINK/EXE:TEST UNI,TEST

compile FORTRAN program
UNI contains $SIMRT

The following command will load TEST.SAV and begin its execution:
.R LOADER
~'cTEST

LOADER uses locations 40,42, and 50 in the .SAV file to determine initial PC (start
address), initial SP (stack address), and program high limit, respectively.
NOTE: The LOADER algorithm requires that the background partition be large enough
to contain both LOADER and ~he standalone program. Therefore, the total amount of
memory required to run LOADER should be at least the sum of the following:

~D~DDmD
MICROCOMPUTER
PRODUCTS
GROUP

274

).Inote

NUMBER
PAGE

089

2 OF 5

•
•
•
•

256 words (vector and stack area)
size of loader program (about 128 words)
size of standalone program (from its link map)
size of any Foreground Job, or System Tasks,
USR (if SET NOSWAP), and any loaded handlers
• size of RMON
To ma)(imize the memory available for the standalone program, no Foreground Job
or System Tasks should be loaded, the USR should be SET SWAP, and all resident
drivers should be UNLOADED.
An undocumented feature of the MXV11-A2 TU58 bootstrap can be used to load standalone
programs after they have been debugged using LOADER. As described in the listing
contained in Micro Note 62A, the bootstrap can load a program from an RT-ll filestructured TU58 cartridge into memory and begin its execution. The cartridge is
prepared in the following manner:
• I NIT /NOQ

DD:

.COPY TEST.SAV DO:
.R PATCH
Fi le Name? DO:
,"0/ xxxxxxx 260 LF
2/ xxxxxxx 76733 LF
4/ xxxxxxx 76400 LF
6/ xxxxxxx 73376 CR
'~E CR

initialize the TU5S, if required
run the standalone program on the TU58
run RT-11 patch program
and "patch" the TU58
put a 260 as first word of first TU58 block
RAD50 for "TES II
HAD50 for IITII
RAD50 for "SAV"

Now when the TU58 is booted by the MXV11-A2, TEST.SAV will begin execution.

~DmIDmD
MICROCO~MPUTER

PROD'UCTS
C;RO~UP
27~)

LOADER

~AL~O

V03.02B13-MAY-80 16:59:32 PAGE 1

1
2

.TITLE
.IDENT

LOADER
IMAY. 80/

.ENABL

.MCALL

.WAIT

-......,J

4
5
6
7
8
9
10
11
12
13
14
15
16
17 000000
18 000000
19
20
21
22
23 000004
24 000012
25 000014
26
27
28
29 000016
30 000020
31 000034
32 000036
33 000040
34 000046
35
36
37
38 000050
39 000054
40 000056
41
42
43
44 000060
45 000062
46 000064
47 000066
48 000070
49 000072
50 000074
51 000100
52 000106
53 000110
54 000112
55 000116
56
57

.CSIGEN .READW

.SETTOP .PRINT

.EXIT

LOADER - Load .SAV file into memor~ startins at location O.
Start proS ram execution with interrupts disabled.
To build LOADER, enter this proSram with
and t~pe the followinS commands:

~our

favorite editor

.MACRO LOADER
• LINK LOA[IER
;

START:
012703

MOV

000316'

IAREAt4, R3

; a

hand~

pointer

Claim memor~ UP until RHON (or USR if LOCKed) for buffer.
Find first address after our partition.
.SETTOP 1-2
TST
(RO>t
MOV
RO, R2

005720
010002

= last address

-> first loc after partition

; Next, set command line and open input file on channel 3.
5$:

010601
010106
010013
103763

SP, Rl
MOV
.CSIGEN IHILIM, IDEFEXT, 10
Rl, SP
MOV
RO, (R3)
save hish used address as buffer address
MOV
see if file specified
.WAIT
13
5$
and retr~ if not
BCS

Move • Dlove' routine to top of
012701
014142
001376

000302'
10$:

MOV
MOV
BNE

lIIe'lor~.

R1 = first address after Dlove routine
Klove a word
until done

ILAST, R1
-(R1), -(R2)
10$

fill in rest of .READW ars block
005722
010201
162302
000241
006002
010213
012700
103405
014304
026401
103005

000312'

000050

TST
MOV
SUB
CLC
ROR
MOV
MOV
.READW
BCS
MOV
CHP
BHIS

(R2)t
R2, R1
(R3>t, R2
R2
R2·, (R3)
IAREA, RO
12$
- (R3) , R4
50(R4), Rl
14$

to the move routine!

address of routine
R2
save routine address
R2 = number of b~tes left in partition
.;

R2
number of words left
save in EMT arS block
RO -> EMT block
read in the imaSe
R4 -> imase
see if program HILIM is too high
if so, we probabl~ didn't set whole imase

o
t-rj

LOADER

:0 V03.02BI3-MAY-80 16:59:32 PAGE 1-1

58
59 000120
60
61 000122
62 000130
63 000132
64 000140
65
66
67 000142
68 000176
69
70
71
72
73
74
75
76 000242
77 000244
78 000250
79 000252
80 000256
81 000260
82 000262
83 000264
84 000266
85 000270
86
87
88
89
90
91
92
93
94
95
96 000272
97 000276
98
99
100
101
102 000302
103 000302
104 000304
105 000312
000320
106 000324
107
108
109

000111

.NLIST BIN
.ASCIZ
MESS:
OOPS:
.ASCIZ
.EVEN

JMP

(Rl)

to the routine

.PRINT
.EXIT
.PRINT
.EXIT

tMESS

come here on .READW failure

tOOPS

come here if imaSe too biS

'1LOADER-F-Imase read failed'
too bis for memor~'

'1LOADER-F-I~ase

.LIST BIN
The move routine (MUST BE PIC!)
In: R1
first address of this routine
R4
first address of imaSe

=
=

000000
012746.
010746
062716
000002
000005
005000
012420
020401
103775

o
000340

MOV
MOV
AD!I

000006

RTI
RESET
CL'R

t340, -(SP)
PC, -(SP)
t20$-., (SP)
soto 20$ with interrupts off
stop the world
RO

MOV
CMP
BLO

mcy~

im~s~

dc~n

to location 0

R4, Rl
30$

The next instruction seQuence starts the imase Just read in •
• SAV files produced b~ RT-ll (for example FORTRAN prosrams with SIHRT)
are started b~ loadinS SF' and PC from locations 42 and 40, respectivel~.
Alternatel~, an imase that expects to start at location 0 ma~ be startid
b~ clearinS the PC.
Alternatel~, an imase that expects to be started
throush the power UP vectors ma~ be started b~ simulatins a power-up.

013706
013707

CLR

MOV

@t40, PC

***
or ***
@t42, SF'
MOV

000042
000040

***
or ***
t24, SP
MOV
RTI

073376
000000
004003
000000

LAST:
DEFEXT:
000000
000000
000000

000000
000000

.RAD50
• WOf<[I

AREA:

.WORD

the imase is a .SAV file
the imase comes
vector

/SAV/
0, 0, 0
10*400+3, 0, 0, 0, 0

throush the power-up

o
t"Ij
U1

HILIM:
000000'

the imase expects to start at location 0

.END

START

LOADER
':0 V03.02B13-MAY-80 16:59:32 PAGE 1-2
SYMBOL 1 ;' .•. _£
AREA
DEFEXT

0OO312R
000302R

000000
000324
ERRORS DETECTED:

HILIM
LAST

000324R
000302R

MESS
OOF'S

000142R
000176R

START

OOOOOOR

••• Vi

000003

••• V2 = 000001

000
001

ABS.

VIRTUAL MEMORY USED: 1756 WORDS (7 PAGES)
DYNAMIC MEMORY AVAILABLE FOR 49 PAGES
LOADER,LOADER=LOADER

o
t'lj
V1

NUMBER

).Inote
TITLE

090
DATE

USING THE BAll-VA IN SMALL SYSTEMS

DISTRIBUTION

4/ 17 /80
PRODUCT BA 11-VA
MXVll-A, HXV11-A2

UNRESTRICTED
RICK PLUMMER

ORIGINATOR

PAGE 1

2
7ZAP

There are a number of possible ways to configure small LSI-ll based systems. The
purpose of this note is to point out some of the configurations and stimulate the
imaginative solution of others. The confi9urations below will all be housed in a
BAll-VA mounting chassis. This is ideally suited for ROM based, RAM based or TU58
mass storage based applications. Since the chassis contains no power sequencing,
the CPU wake-up circuit will be used to initial ize the system. Refer to Micro Note
#85 for a further discussion of the wake-up circuitry. Remote restart may be
accomplished with the connector provided. This note will also refer heavily to the
MXVll-A multifunction module. Refer to the Microcomputer Processor Handbook and
Micro Note #54 for more details on the MXVll-A.
1.

Small ROM Based Systems
Option

Modules

Functionality

KD ll-GC

KDll-HA

LSI-ll/2 CPU

MXVll-AC

8KB ROM
32KB RAM
2 Serial Ports

Customer program would be in PROM chips residing on the MXVll.
Two option slots remain for other I/O devices.
2.

Large ROM Based Systems
Option

Modules

Funct iona 1 i ty

KDll-GC

KD l1-HA

LSI-l1/2

MXV11-AC

32KB RAM
2 Serial Ports

MRV11-C

64KB ROM

MRV11-C

The MRV11-C may be addressed either directly or through a window. If window
mapping is used, the MXVll-A2 bootstrap chip set may be used to load a program
stored in PROM into the RAM memory for execution. One option slot remains for
I/O modules.

mamaomD

MICROCOI~PUTER

PRODLICTS
GROIJP
279

)Jnote
3.

NUMBER
PAGE 2

OF 2

RAM Based Systems
Option

Module

Funct i ona 1 i ty

KD11-GC

KD11-HA

LSI-l1/2 CPU

MXV11-AC

32KB RAM
2 Serial Ports
Custom Boot

A typical RAM based system may be down-line loaded from a host processor. The
customer down-line load boot may reside on the MXV11-A module. This system
leaves two option slots for I/O. If memory expansion is desired, either an
MXVll-AC or MSV11-DC may be added depending on the usefulness of two extra
s e ria 1 po r t s .

TU58 Based Systems
Option

Module

Functional ity

KDll-GC

KD l1-HA

LSI-l1/2 CPU

MXV11-AC

32KB RAM
2 Serial Ports
60 HZ Clock

MXVll-A2

Boot PROM

MXV11-AC

32KB RAM
2 Serial Ports

The TU58 based system is typical of the large amount of computer power that
will fit in small spaces. Full system memory, bootstrap and four serial I/O
ports occupy only three modules, leaving the forth for additional I/O capability.

~DmDDmD
MICROCOMPUTER
PRODUCTS
CiROUP

280

NUMBER

j../note

091

DATE

--- .

TITLE USING'rHE MXVIl-A2 BOOTSTRAP ON THE MRVll-C

DISTRIBUTION

UNRESTRICTED

PRODUCT

ORtIGINATOR

RICK PLUMMER

MRVll-C

/ 80

MXVll-A2
I

PAGE 1 OF

2
~p

The purpose of this note is to provide users with the information to allow
them to use the MRVll-C to bootstrap their system using standard MXV,11-A2 bootstrap chips. While this is not usually optimum for new designs, due to the
highe](' functional density of the MXVll-A Multifunction Module, it will be useful
in upgrade and evaluation situations.
The MX~\tll-A2
1fuere are two distinctly separate boot programs residing in a pair of
512 x 8 ROM chips. Address bit 8, the highest order bit, of the chip is used
to select the appropriate one. One program boots from the TU58 while the other
boots froml RL02, RLOl, RK05, RX02, RXOI or MRVll-C. The second will check
system resources in the order listed; looking for a bootable device. See Micronote
62A for more detailed information concerning the bootstrap programs.
BOOTING FROM TU58
To use the TU58 boot simply:
1. insert PROM 040Dl in socket XE44
2. insert PROM 039Dl in socket XE43
3. jumper Jl17 to Jl12 to Jl07
4. jumper Jl16 to JIll
5. jumper J 86 to J 87
6. jumper J 6 to J 7
7. jumper J 18 to J 19 to J20 to J2l to J22 to J24
The module will now have the TU58 boot starting at 173000.
BOOTING FROM DISK
To use the Disk boot it is necessary to:
1.

jumper the module as outlined in steps 3 thru 7 above.

Before inserting the ROM chips in the sockets, bend pin 23 of each of the
chips upward 90 degrees. (This will void the chip warranty.) Now wire
wrap a connection from .pin 23 of 040Dl to pin 23 of 039Dl. Wrap a second
piece of wire to pin 23 of 039Dl and leave the other end free.

~D~DDmD
MICROCC)MPUTER
PRO~.UCTS

CiRC)UP
281

NUMBER

091

PAGE 2

OF 2

Now insert the ROM into the sockets as in steps 1 and 2 above. The free end
of the second wire should now be wrapped to JIll for Disk boot or to Jl17 for
TU58 boot.
If this is done carefully, no damage should be done to the chips.

MlZuJl-C

8048

tv)

,J]

&--------_.

~!- - - - - - - -

~D~DDmD
MICROCOMPUTER
PRODUCTS
GROUP
282

NUMBER

)lnote

092

TWO POTE~TIAL PROBLEMS WITH THE RXV21 INTERFACE
(M8029)
UNRESTRICTED
DISTRIBUTION

TITLE

ORIGINATOR

BARBARA BECK

DATE
5 /

PRODUCT
RXV21

PAGE 1 OF 1

fZ./IP

The RXV21 interface module may exhibit signs of irrational behavior due to two
problems recently discovered with that board.
First, there exists a semiconductor-related problem which may cause undetected
errors during data transfer. This problE~ will be detected by the RXV21 performance
exercisor (CZRXDA). Modules that are currently being shipped have been corrected
for this. To identify modules that have already had the correction applied, it is
necessary to check the revision level of the module. The revision level is stamped
into the side of the handle and is identified by a letter. The old revision was
"D" and this correction has updated the revision to "E". Another visual check to
verify that the correction has been installed is to see if green wires have been
added to chip E42.
Second, the Bus Address Register incorrectly increments over 32K word boundaries
during DMA transfers. The implication here is that it will not work correctly
in systems that have 11/23 processors that are running with memory management enabled.
11/23 development systems with RXV21 disks that are currently being shipped have been
modified to correct this problem. They can be identified by the revision level _"F".
For those customers that have upgraded their LSI-II's to II/23's and need to have
their RX02 floppy modified, please contact your sales person.
Please contact the LSI-II Hot Line (800-225-9220) if you have any questions regarding these issues.

~D~DDmD
MICROCC-MPUTER
PRO~~UCTS

GRC-UP
28:3

).Inote
TITLE

USER WRITTEN SYSTEM TASKS UNDER RT-11 V4

DISTRIBUTION

UNRESTRICTED

ORIGINATOR

JON TAYLOR

NUMBER
093

DATE
5

/12

/80

PRODUCT
RT-11 V4

PAGE

OF 1
e~

A SYSGEN option called "system tasking" is available in the RT-11 Version 4 foreground/
background monitor. System tasking allows RT-11 to run up to six programs (called
system tasks) in addition to the standard background and/or foreground programs.
Although only Digital supplied system tasks are supported, it is not difficult to
write programs which can be run as system tasks. This capability gives RT-11 true
multi-tasking capabilities and allows it to be used when a small, fast, multitasking operating system is required.
Note that although RT-l1 V4 has multi-tasking features, it remains a single
user operating system - only one tenninal at a time is the "console", with the
power to run program development software. User written application tasks, however,
may be assigned a tenninal other than the console.
Be warned that any suspected system errors must be reproduced on a supported software
configuration before submitting an SPR. This may be as simple as re-running the userwritten system task as a foreground job to see if the problem persists. Details
;-regarding the implementation of user written system tasks can be found in the RT-l1
Software Support Manual Chapter 3, :beginning on page 35.

momoomo

MICROCOMPUTER
PRODUCTS
GROUP
284

NUMBER

),Inote
TITLE

09AA

RL02 SUPPORT BY DIGITAL SOFTWARE

DISTRIBUTION
ORIGINATOR

UNRESTRICTED

DATE
5 / 13

/80

PRODUCT
RL02

JON TAYLOR

PAGE

OF 1

'?bP
This article describes the level of RL02 support offered by DIGITAL operating
systems RT-11 Version 3B, RT-l1 Version 4, and RSX-11M Version 3.2. Any applicable
mandatory patches will be described. Patches are found in the "SOFTWARE DISPATCH"
for the particular operating system.
RT-11 Version 3B
Although RT-11 V3B's "DL" handler was designed to interface to RL01 drives, RL02's
are officially UNSUPPORTED under RT-11 V3B. In practice, they are reported to work
on media with no bad blocks. If you must Ulse RL02's (and/or RL01's) with V3B, review the following patches:
MONITOR
SOURCES
SOURCES
SOURCES
SOURCES
SYSTEM HANDLERS
SYSTEM HANDLERS
UTILITIES

08M
05M
07M
10M
14M
01M
07M
25M

Aug. 78
Apr. 79
Aug. 79
Jan. 80
Apr. 80
Sep. 78
Jan. 79
Apr. 80

RT-11 Version 4
The "DV' handler has been completely rewritten for V4. RL01 and RL02 drives are
fully SUPPORTED. Version 4 distribution is available on RL01 and RL02 media. No
special SYSGEN is required to use RL02 drives; RT-1l utilities will determine drive
type "on the fly" using a .SPFUN call to the DL handler.
RSX-11M Ver~ion 3.2 and RSX-11S Version 2.2
RL02 support is available in 3.2 through SYSGEN. The system installer must explicitly
tell the software how many RL01/RL02 drives are on an RLV11 controller and specify
drive type (RL01 or RL02). After the virgin. boot, an RL01 drive may be replaced with
an RL02 (and vice versa). It is not necessary to re-SYSGEN in this case, just to re-boot.
RL02 distribution kits for 3.2: were announced in Feb. 1980. The following mandatory
patches are out:
Oct. 79
2.1.6.1 M
3.1.1.3 M
Apr. 80

~D~DamD
MICROCO~~PUTER

PRODIJCTS
GROIlJP
28~

).Inote
TITLE

VT103 APPLICATIONS FOR UNUSUAL BAUD RATES

DISTRIBUTION
ORIGINATOR

UNRESTRICTED

NUMBER
095

DATE
5

/19

/SO

PRODUCT
VT103

CHARLIE GIORGETTI

PAGE

OF 1
~"$P

Systems that require serial lines in addition to the console have configuration
advantages in a VT103 system. The first additional serial line can be cabled
internally and make use of the EIA connector on the rear of the VT103. Also, the
serial lines that are added can be baud rate selectable from the SET-UP mode of
the VT103. This feature allows easily changed baud rates and a wide range of
speeds for the additional serial lines.
The VT103 in SET-UP mode B can select certain baud rate values.' The baud rates
that can be selected are 50, 75, 110, 134, 150, 200, 300, 600, 1200, lS00, 2000,
2400, 3600, 4S00, 9600 and 19200. This wide range of values can be utilized with
most DLV11 type interfaces and the MXV11. The baud rate of the VT103 console is
fixed and is not affected by the given baud rate selected in SET-UP mode B for the
additional serial lines.
The baud rate is selected using the TRANSMIT SPEED feature in SET-UP mode B on the
VT103. The RECEIVE SPEED feature has no effect on serial line baud rates. If the
serial line is a DLV11-J or a MXV11-AA, -AC configured for external baud rate and
cabled into connector J2 on the Standard Terminal Port (STP) with DEC cable #1911411-00, as described in the VT103 User's Manual Chapter 5, it would be able to
be programmed from the keyboard in SET-UP mode B. If the line is a DLV11-E or a
DLV11-F, set for external baud rate and common speed, cable the serial line into
connector J3 on the STP with DEC cable BCOSR-01. The baud rate is now selectable
from the TRANSMIT feature.

mD~DDmD
MICROCOMPUTER
PRODUCTS
GROUP
286

NUMBER

).Inote
TITLE

096

DATE

TUS8 TIPS

DISTRIBUTION

UNRESTRICTED

PRODUCT

ORIGINATOR

ERNIE STRANGE

TUS8

PAGE

OF 2

KD11-F MEMORY REFRESH AND TIlE ruS8
When the KDll-F goes through a memory refresh cycle, it takes approximately 130
usec. During the refresh cycle, no I/O device can be serviced. Operating the
ruS8 at 38.4K baud requires service every 260 usec. When reading or writing
just to the TOS8, no problems arise. If other devices are also serviced, depending
on their number and type, the chances increase of not being able to service the
TUS8. Operating at a lower baud rate will lessen this potential problem.
ruS8 EM!
The drive units should be mounted in an area that is free from electro magnetic
interference. Such noise could be caus(~d by a switching power supply or a CRT. While
wires coming from the read/write heads are shielded, these are low level signals and
errors may occur if noise is introduced.
ruS8 HEAD CARE
The TUS8 read/write.head should be cleaned after the first 20 hours of use. Thereafter,
cleaning should be done at 100 hour int(~rvals. Use a cotton applicator moistened
with DEC cleaning fluid (from cleaning kit TUC-01) or isopropyl alcohol, fluorocarbon
TF or equivalent.
ruS8 CABLES
The IBC20Z-2S cable should be used to connect the MXV11 or DLVll-J to the ruS8. If
the cable is being manufactured by the c:ustomer, pin 1 of the amp connector should
not be used. The 38.4K baud clock on the MXV11 and DLVII-J will become loaded
Capacitive load) and cause the serial ports to malfunction. This problem usually
occurs when 10 conductor mass terminated. cable is used.
ruS8 POWER SUPPLY SELECTION
When considering a power supply for the TUS8, insure peak and maximum current ratings
are met.

~D~DDmD
MICROC:OMPUTER
PRC-DUCTS
Ci~~OUP

287

).Inote

NUMBER

096

PAGE 2

OF 2

POWER CONSUMPTION
Logic Control Module
and 1 or 2 Drives

l1W, typical drive running
+5V +5% at .75A, maximum
+12V-+I0% -5% at 1.2A peak
.6A average running
.1A idle

If the power supply selected is rated at I amp for +12V, there may be a problem.
The power supply could shut down when a peak current of 1.2A is drawn by the drive
unit.
RUN INDICATOR (TAPE MOVEMENT)
When the LED (Light Emitting Diode) is put in series with the tachometer, check for
correct polarity. If correct polarity is not established. the tape could run off
the reel because the logic card cannot read pulses from the tachometer, therefore,
positioning is lost.

TO PIN'

J3, Jo4

PIN 7

"ODED
LED

,......--,
I

+12\1

I
PIN. _ _ _ _ _---1

PIN ,-------~

Installation of Run Indicator

mD~DDmD
MICROCOMPUTER
PRODUCTS
GROUP
288

NUMBER

).Inote
TITLE

097

DATE

TU58 TAPE FORMAT AND ADDRESSING MODES

DISTRIBUTION

UNRESTRICTED

ORIGINATOR

ERNIE STRANGE

5 /

/80

PRODUCT
TU58

PAGE 1 OF 5

TIlere has been some confusion on just how data was organized on the TU58 tape
cartridge. The following information details actual tape formatting.
78. 7b/c~
200b/in\ <:

315 b/cm
800 b/in ------------------~
I

Inter
Record
Murk
16-Bits

Header
Sync.

Record
Number

Data Sync
Field

Data Field
128 Bytes

Check
Sum

16-Bits

Compl.
of Red.
Number
16 .. Bits·

16-Bits

56-Bits

1024-Bits

16-Bi t 5

TRACK 1 10 0 .. C 000 .. 01

N + 1024

00 00 00 00 .. 01

End
I
Space
I
All Zerod
136-Bits

000 .. 01

ONE RECORD
~eader Description

TIle header and data fields are shown in the above figure.
following components.
A..

The header contains the

Interrecord Marks - Sixteen bits recorded at 200 BPI and having a data pattern
of 1010101010101010. During search, the controller finds records by starting
from a known position and counting the interrecord marks as they go by at 60
IPS. When it reaches the record before the record being searched for, it slows
the tape down to 30 IPS and reads the next header. If the record number read
agrees with the record number expected, and it error checks O.K., the controller
continues with the read or write operation. Otherwise, it corrects the current
position and initiates a new search.
Any combination of incorrect record numbers or tape reversals totaling eight
events causes the controller to abort the operation and declare a seek error.

~nmDDmD
MICR4)COMPUTER
PlIlODUCTS
~CROUP

289

j./note

NUMBER
PAGE 2

097
OF 5

Header Sync - (All of the following bits are recorded at 800 BPI.) It
consists of 15 zeros followed by a one. The controller looks for the one
and then begins to accept the record number.

Record Number - 16-Bits (0 to 2047)

Record Number Complement - The controller tests this number to insure that
the header was read with no errors.

Data Sync Field - 55 zeros and a one. During a write operation, the controller
turns on write current after the first 8 zeros and writes the remaining zeros
and one. The glitches caused by switching on the write current are then confined to a narrow space which the controller blanks out during read operations.
After a fixed duration blank (controller ignores tape output) the controller
begins to search for the one at the end of the data sync field. When it
finds the one, it begins reading the data fleld.

Data Field Description
A.

Data Field - The next 1024-bits of data are stored in the data buffer in the
controller.

Checksum - The checksum contains 16-bits and is used to find errors in t~e
real data. During read, each pair of bytes is summed in a 16-bit add. If
a carry results, it is added to the LSB (l's complement addition). If the
sum of 128 bytes does not equal the checksum on tape, the record is re-read
up to eight tries. If the correct data cannot be read after eight tries, a
hard error is indicated to the host processor.

Post Record Zeros - When the tape is formatted, an additional 136 zeros are
written t~ allow for 10% tolerance in motor speed. The first 8 zeros are
written after data is written. The remaining 128 zeros are never rewritten
or read in normal operation. Their purpose is only to provide flux reversals
in the space between the end of data and the beginning of the next record.

momoomD

MICROCOMPUTER
PRODUCTS

GROUP
290

Record
1024

BOT

H
H

DATA
DATA

H I
H

DATAl

DATA

Record 1

lO
I---'

DATA

No Mark for Records 0, 1024

OF 5

DATA /1M

DATA

Eor

TRACK I

DATA ) M

DATA

Eor

TRACK 0

Record

1022

Record

1023

DATA

Record

3 II

TAPE FORMAT

M = Interrecord Mark
H = Header

PAGE 3

A
Record

097

Record 2047

)BOT

Record 2046

Record 1026

Record 1025

NUMBt."R

BOT, EOT, and Interrecord Marks
Special marks are recorded during tape formatting to
indicate beginning and end of tape a5 well as beginning
of record. These marks are recorded at one fourth the
bit density of data or at 200 BPI. The lower frequency
is detected by the controller. The encoding method used
is not sensitive to tape speed, so that ones and zeros
may be recovered at the lower frequency with no change in
hardware. The BOT, EOT, and IRM (Interrecord Marks) are
distinguished from one another as follows:
A.
B.
C.

BOT is recorded as all zeros.
EaT is recorded as all ones.
IRM's are recorded as alternate ones and
zeros.

NUMt.
097
PAGE 4
OF 5

BLOCKS ARE INTERLEAVED TO IMPROVE ACCESS TIME
A

BLK (384

TRACK
#1

I 2~'28 3~ 3~ 3~ J7
I I( I . I I I ( I I,

RECORDS~1024

25 26

)9 30
f

RECORDS.. 0

rIbs!

..-J

BLK #130

BLK #257

BLK #258

,I ] I I

BLK #1

l I 3~~

I I I

BLK # 383

BLK (259

10 11 12 13 14 15 16 17 18 J9 20 21 22 23 24 25 2j 2

I I I I I I
BLI #0

38 3140 4'1 42 43 4( 45 46 4

BLK #129

BLK #256
TRACK
#0

34 J5

~--r--[~

BLK #128

t'..)
LO
N

BLK #386

BLK(385

BLK #2

11016 1018

28 29 3f
f

BLK #3

11017 11019 [ 1021 11023

BLK #127

11J58 RECORD A.~D BLOCK DIAGRAM
Logical Format
Data is recorded on two tracks. Each track contains 1024 retords
of 128 bytes. To accommodate the orientation of the record and
erase head gaps, beth tracks are recorded in the same direction.
To accommodate standard mass storage blocks of 512 bytes, the
controller groups four 128 byte records together. Addressing
from the host i~ done by 512 byte block numbers. (0-511)
A special mode permits access of 128 byte data blocks.
in special mode is by 128 byte block numbers (0-2047).

Addressing

1024 Data Bits Per Record
128 Bytes Per Record
4 Records Per Block
256 Blocks Per Track
2 Tracks Per Cartridge
One Cartridge Equals 256K Bytes
(262, 144 Bytes)

).Inote

NUMBER 097
PAGE

ADDRESSING MODES
Special Addressing Mode
Setting the most significant bit of the modifier byte (byte 3 of conunand packet) to 1
selects special address mode. In this mode all tape positioning operations are
addrlessed by 128-byte blocks (0-2047) instead of 512~byte blocks (0-511). Zerofill in a write operation only fills out. to a 128-byte boundary in this mode.
Applications that have less than 128-bytes of data per block could use the special
addressing mode to put more data on a cartridge.
Normal Addressing Mode
Tape motion stops at the end of a block in a write operation and at the end of
a record in a read operation. Writing or reading data to the TUS8 is done by
specifying the block and number of bytes to be written or read. If only one record
(128 bytes) is to be written, the remaining three records (384 bytes) of the block
will be zero-filled.

~D~DDmD
MICR04:0MPUTER
PRC)DUCTS
GIIOUP
293

NUMBER

)lnote

098

TITLE 11/23 & 11/03 RLOI BASED PACKAGED SYSTEM EXPANSION
DISTRIBUTION

UNRESTRICTED

ORIGINATOR

MIKE SHUSTER

DATE
5 / 19

/80

PRODUCT

RLOI Based Packaged
Development Systems

PAGE 1 OF 2

All 11/03 and 11/23 Packaged Systems have been described as expandable to a second
BAII-NE or -NF type box within a system cabinet. The above statement is true but
must be qualified to reflect power controller ratings in 11/03 and 11/23 systems
with RLOI disk.
11/03 SYSTEMS
120V 11/03 PACKAGED SYSTEMS
These systems will cont~nue to be produced with the 871-A 12 amp power controller
and a standard 15 amp plug (Fig. 1).

Receptil~lp.s

Plug
(NEMA 15-15P)

(NF.MA ',-15R or ',-?OR)

FIGURE 1
120V 11/03 systems have the physical space for a BAI1-NE e~pander box. It must be
noted, however, that the current capacity to power an additional box plus mass
storage does not comply with UL ratings.
IMPACT ON 11/03 USERS
11/03 users will be affected when adding a second BAI1-NE or -NF box.
Should a user wish to expand an existing system, he or she must replace the 871-A
12 amp power controller with an 871-C 16 amp power controller, as well as provide a
20 amp receptacle, in order to comply with UL ratings.
All 240V 11/03 Packaged Systems are expandable.

~D~DDmD
MICROCOMPUTER
PRODUCTS
GROUP
294

).Inote

NUMBER 098
PAGE 2 OF 2

11/23 SYSTEMS
120V 11/23 PACKAGED SYSTEMS

These systems are being produced with an 871-C 16 amp power controller which allows
expansion to a second BAI1-NE box. The 871-C has a plug requiring a 20 amp outlet
(Fig. 2).

Plug

Receptacle

(NEMA 15-20P)

(NEM!\ 15-20R)

FIGURE 2
A few early production 11/23 packaged systems used the 871-A 12 amp power controller
with a standard 15 amp plug. The procedure for expanding these systems is similar
to that of the 120V 11/03 Packaged Systems.
IMPACT ON 11/23 SYSTEMS
11/23 Packaged System users must understand that 120V systems require a 20 amp outlet
which is standard in most commercial buildings. If a 20 amp outlet is unavailable,
a licensed electrician should be consulted for the best possible solution.
All 240V 11/23 Packaged Systems are expandable.

*NOTE: This analysis does not include terminals (a VT100 is rated for 3 amps at 120V).
It is~ recommended the wall outlets be used for such a purpose so that the system will
remain within its UL rating.

~D~DDmD
MICROCC)MPUTER
PROI)UCTS
CiRC)UP
295

)lnote
TITLE

RL02 BOOTSTRAP FAILURES USING BDVII

DISTRIBUTION
ORIGINATOR

UNRESTRICTED

NUMBER
099
DATE
8 /

/ 80

PRODUCT
BDVII

RICK PLUMMER

PAGE 1 OF 1

A problem has been discovered when using the BDVl1 to bootstrap RL02 disks.
symptom would be seemingly intermittent boot problems.

The

The problem is due to the fact that the BDVII boot code was written :tror the RLOl,
which uses only eight cylinder address bits (versus nine for the RL02). When
calculating the difference count for a seek to cylinder 0, bit 15 is cleared (it
is defined as "must be 0" for RLOl's). This means that if the heads are already
positioned at cylinder 400, or beyond, an incorrect difference will be calculated.
A seek will then be made to the incorrect cylinder, resulting in bootstrap failure.
Since the position of the heads determines the failure mode, the problem will appear
to be intermittent. In fact, many users may never see the problem, particularly
those who only bootstrap after power-up.
The problem will be corrected with new ROM~s. Until these ROM's are available,
it may be necessary to avoid the erro.r by eycl ing the desired RL02 down, then up
again before bootstrapping.
Contact the LSI-l1 hot line for further information.

~D~DDmD
MICROCOMPUTER
PRODUCTS
GROUP
296

NUMBER

).Inote
TITLE

100

DATE

UPGRADES FOR PBll

DISTRIBUTION

UNRESTRICTED

OHIGINATOR

CHARLIE GIORGETTI

11 / 13

.... . -

PRODUCT
PBll
PAGE

1 OF

User applications that require Intel 2732, 2732-6 or 2716 type EPROMs
should consider the following upgrades to the PBII hardware and the
PROM/RT-ll PROM programming utility.
The first upgrade is required when 2732s or 2732-6s are used with
PROM/RT-Il VI.05A under distributed RT-II V03B or RT-I1 V04 monitors.
The upgrade is also required when 2716s are used with PROM/RT-11 Vl.05A
under a distributed V04 monitor. 11he reason for the upgrade is to
increase a time out counter that is activated when data is being
transferred to the PBll hardware. The following patch to PROM.SAV or
PROM.REL changes the counter and upgrades the Version number:
.RUN PATCH
FILENAME*PROM ... SAV/f
*1-_~52310R

*10226ilR
*~~070'-....

101

102

*.!-L 392 0 /

264

*E
Checksum?

1377

(underlined characters typed by the user)
The second upgrade is required when the 2732s are used.
In the option,
PBllK-AD, for 2732s, the socket adapter is 715-1531. The change
requires the replacement of two resistors on the reverse of the
socket adapter itself. The resistors are marked Rl and R2, both have
a resistance of 1 KOhms.
Resistor Rl should be changed to 10 KOhms
and resistor R2 should be changed to 3.3 KOhrns.
Figure 1 shows the
resistor locations.

mDmDD~D
MICROCC)MPUTE~

PROI)UCTS
CiRC)UP
2~l7

NUMBER 100
PAGE 2

OF 2

The resistor changes can be implemented by the user, by a local DATA I/O
service office, or by Digital's Customer Returns Area. The Customer
Heturns Area could reject the adapter tor future repairs when this
resistor change is implemented by non-authorized personnel.

QA R3

b Q2

D-

-C-J-

-g-

--------,--'--------- -- ------------ ------ -'Figure 1 reverse of socket
adapter 715-1531

~D~DDmD
MICROCOMPUTER
PRODUCTS
GROUP

298

)lnote
TITLE

NUMBER
101

DATE

TUS8 SYSTEM PeMER PROBLEM

[)ISTRIBUTION

UNRESTRICTED

ORIGINATOR

ERNIE STRANGE

1
c::w

au:

/ 81

PRO~U~T

rLJS8
I._~

t ' ..

' . " , .. "",', _ ' . , ........... ~~ ".~""J •. ""'''''''\':.'

PI\§§ 1
UtliP!

.........

.'1:; ...... "..

. . . . . ~.

....

-.. , ..,....... ...
~

SYSTEMS
When DLV11-J's were used in a system to communicate with TU58's, an extra continue
response from the ruS8 was obtained. The DLV11-J's -12V charge pump was coming up
late. Initially, the TUS8 logic card would start its self-test diagnostics. Then
the TUS8 received what it thought was a break (-12V coming up on the DLV11-J),
creating a continue response from the TUS8. The TU58 logic card, ECO #2 (CS Rev. C
to Cl) corrected this problem.
TUS8 POWER SUPPLY SELECTION
When considering a power supply for the TUS8, insure peak and maximum current ratings
are met.
POWER CONSUMPTION
Module and 1 or 2 drives

l1W, typical, drive running
+SV +5% at .7SA, maximum
+12V--+I0% -5% at 1.2A, peak
.6A average running
.1A idle

If the power supply selected is rated at 1 amp for +12V, there is a problem. The
power supply could shut down when a peak current of 1.2A is drawn by the drive unit.

~D~DDmD
MICROC:OMPUTER
PRC-DUCTS
GAtOUP
299

NUMBER

j../note
TITLE

102

DATE

MMU CONFIGURATION JUMPERS

DISTRIBUTION

LSI -11/23 USERS

ORIGINATOR

LINDA MENTZER

/ 14
1
PRODUCT

/ 81

Kl) P11 ( M818 6)
"~

PAGE

1 OF

The purpose of this Micronote is to provide the proper configuration for the KDF11-A
module to be used when an MMU chip is present.
FLOATING POINT COMPATIBLE MMU.

DIP PART #21-15542-01 (CHIP PART #304E)

Etch Revision C modules should have jumper W2 removed and W3 installed when the
above MMU chip is present.
Etch Revision A modules must have ECO M8186-ML009 installed if the above MMU chip
is used. This ECO is to remove W2 and install a wire from E2 pin 5 to E2 pin 15.
If the proper configuration is not followed, a timing problem could occur which
would cause the MMU chip to place the wrong physical address on the bus. The
frequency of occurrence of the problem would increase with increasing temperature
of the chip or with installation of the Floating Point option.
NON-FLOATING POINT COMPATIBLE MMU.

DIP PART #21-15542-00 (CHIP PART #304C)

Etch Revision C modules should have W2 inserted and W3 removed.
Etch Revision A modules should have W2 installed.
NEED MORE INFORMATION?
Please contact the LSI-II Hot Line (800-225-9220) if you have any questions regarding
this.

momoamo

MICROCOMPUTER
PRODUCTS
GROUP
300

NUMBER

).Inote

103

TITLE CREATING A DIAGNOSTI C DECTAPE II UNDER XXDP+
DISTR~BUTION

UNRESTRI eTrn

ORIGINATOR

BOB DUCEY

'"-

DATE
9

/ 80

PRODUCT
TUl38
.-.-....-

PAGE 1

•

~ . .Y(11iJ2P7

OF 1

The following procedure will create an XXDP+ diagnostic monitor on a TU58 tape.
Original XXDP+ diagnostic release media is used as the source and various commands
from UPD2 do the transfer to the destination device. The resulting copy will be a
DDDP+ diagnostic tape.
1/

Boot XXDP+ from the distribution media.

Answer the date, 50 HZ and LSI questions.

Run UPD2.
ego
R UPD2

Take a scratch DECTAPE II and load into the TUS8 drive O.

Use the zero command, this will i.nitialize the tape.
eg.
Zero DDO: (CR)

Use the load command to load the TUS8 monitor (HMDDAX.SYS)
into a buffer within the utility program.
ego
Load DEV:HMDDAX.SYS (where X is the current version
of the monitor 0,1 etc.)

Use the dump command to write the contents of buffer area in
the utility to the TUS8.
eg.
Dump DOG: HMDDAX. SYS

1
/

Use the SAVM command to create the boot blocks on the tape.
SAVM DOG: IIMDDAX . SYS

eg •

Use the PIP command to copy a~l desired file'S from the
system device to tape.
eg.
PIP DDO: FI LNAM. 'I'YP.:::DEV: FI LNAM. TYP.
(Where DEV: is the source device.)

10/

You now have a boatable TUS8 diagnostic tape. If you wish to
exercise the TU58, the TUS8 performance exerciser is diagnostic
ZTUUBX.BIN. (Where X is the current version level 0,1 etc.)

~D~DDmD
MICROCOMPUTEC
PROIDUCTS
GROUP
3;01

..-

NUMBER

),Inote

104

TITLE

11/23 ECO Status

DISTRIBUTION

Unrestricted

ORIGINATOR

DATE
12
'.~

3 /

PRODUCT

Jon Taylor
,~~

PAGE

1 OF

This uNote documents the ECO and etch revision history of the KDFlI-A
module. A quick verify has been included so that the status of a modulE~
may be determined by a visual check.
In using the attached table, it is important to be aware of the new
hardware revision system employed on the M8186 (KDFIl-A). Whereas other
modules have the etch revision level coded into the etch and the circuit:
schematic (Gs) revision level on the module handle, the M8l86 has both
stamped on the module handle.
The revision identifier is a two-field alphanumeric designation. The
·first field indicates the etch revision.
The second field indicates the
modifications (lies revision") to this etch.
Hardware revision notation:

A
Identifies etch level

T_____

Identifies modifications

~rhe M8l86 began as hardware reVl.Sl.on "A¢", as shown above.
That is,
etch revision "A" with no modifica:i.ons or rework. As ECO's were released calling for rework (but not a new etch), the hardware revision
level was updated to "AI", then "A2", etc. When new etch revisions
were released, the etch revision field wa.s incremented from "A" to liB"
to "C".
(For the M8186, no etch revision "B" modules were built, so
the revision level appeared to change from "A" to "C" via ECO #4. Etch
Revision "c" boards had ECO #5 incorporated in them before release,
therefore, their hardware revision status did not change with ECO #5).

~DmDDmD
MICROCOMPUTER
PRODUCTS
GROUP
302

NUMBER 104
PAGE

2 OF 7

The hardware revision history of the M8l86 is shown below:
Release

"AflS"

Rework
ECO #1

"AI"

Rework
ECO #2

"A2"

1
1

NOTE:
All
. _ - Rework
modules shipped
ECO #3
are at revision
A3 or greater
New etch
- - Relayout
Revision "c"
ECO #4
created.
No
Revision "B"
modules were built

j
"C¢" --- NOTE: The relayout
incorporated the
changes for ECO #5

Rework
ECO #5

"A4"

Rework
ECO #6

"A5"

"Cl"

Rework
ECO #7

"A6"

"C2"

Rework
ECO #8

1
1

"A6"

"C2" -- NOTE: This was a
documentation
change only

1
I

-l.
Rework
ECO #9

"A7"

1
1

"C3"

~D~DDmD
MICROCOIMPUTER

PRODUCTS
GROIUP
30:3

)Jnote

NUMBER 104
PAGE

3 OF 7

JUMPER FUNCTIONS ON ETCH REVISION "A" AND "c" MODULES
SHIPPINC;
srrATUS

Out

Enabled

----------+--~---.~------..-~------+-----_t
I

A
N

Mode Name
o PC@24, PS@26
1 Canso Ie l{ ODT
2 Bootstrap
3 Extended l ....Code

W5 W6
Out Out
In Out
Out In
In In

W5=In
W6=Out

----+-------------------~--------------------------------~---------

Halt/Trap Option

In=Trap to 10 on "Halt"
Out=Enter console MODT on
"Halt"

Out

In=773000 is bootstrap
address
Out=Bootstrap address is
specified by Jumpers
W9-W15

j
r---------+-------------------~--------------------------------+_-----W8

Bootstrap Address

T
C

I,
i
I

I
I

~--------~---------------------.-4---------------------------------_r--------~

W9-W15

User Selectable
Bootstrap Address

W9-W15 Correspond to
In
j
Address Bits 9-15
I
H
respectively.
In=Logic "I"
Out=Logic "0"
I--------I------------t------------------------+-------"
"c" W16, W17
Factory Installed, Do
In
Reserved for DEC
Not Remove
--------~--------------------------------~-------

Etch

"c"

W18

t "A"

W18

Etch

W19

Wake-Up Circuit
Out = Enabled
In
-------1--------. . "" -.----------------11----Reserved for DEC
Factory Installed, Do
In
Not Remove
Wake-Up Circuit
Out = Enabled
In

*W3 on Etch Revision "A"
Modules consists of a jumper
from E2 Pin 5 to E2 Pin 15.

MICROCOMPUTER
PRODUCTS
GROUP
304

PAGE

~~~.---;?-.-.....,~-= ~~~=.'
,

\\If

~W'~

o--c.W15
Wl"c.--<>

'1\1" <>--<>

~W1J

C>--o WI)

'1\110--->

V.I~<>--c
<>--0 WII

"" 100--0

~W9

"'ile>---<>

O--<>W7

V16~

0---<, W!>

. W3

~'I\l

~W~

____~J
REVIS!Ot~

w8<>--<>
W"~-<l

M8186 eTCH

0 - - < ) Wl1
Wl0~
<,"""-> >lV9

__rL.-----.J
~818G

"A"

ETCH REVISION "C

LOCATION OF JUMPERS ON ETCH REVISION "T~" AND REVISION

3U~)

nc" MODULES

),Inote

NUMBER 104'
PAGE 5 OF 7

The following table details the ECa's issued since the M8186 began to shi~.
to the field.
These ECO' s are coded "M8186'- MLOOX", where "X" is thp ECO '
sho\'1n below:
ECO #

PROBLEM

QUICK VERJfY! _______,

Too many wires and etch cuts, new
etch needed. Note that the jumper
locations change for etch Revision

Module hqnJl~ will be
stamped nGn" (Where
"nit refers to the ~S
revision. )

"Cit.

I/O page addressing scheme differs
from LSI-ll/2 processor.
Note: I.rcplerrentation of this EXX) inpacts
configurations. This EX)) is discussed in
detail in uNote 8DA.
The internal wake-up circuit defeats
the sequencing provided by standard
DEC power supplies. This ECO should
be installed when the M8186 is used
with same.

Check for etch cut to
E7 Pins 16 and 18
Red jumper wire is
installed in parallel
with 01.

CTL/DAT hybrid (57-00000-00) and
MMU IC (21-15542-00) were not
compatible with KEFll-AA floating
point option. The FP registers
in the MMU were inaccessable, and
the CTL/DAT data path caused intermittent errors in floating point
instructions.

CTL/DAT should be
57-00000-01 and MMU
should be 21-15542-01 for
floating point
compatibility.
Coordinate with ECO
M8l86-ML009.

MMU (21-15542-01) was included as
part of the M8l86 module.
It should
have been specified as an option
that could be added to the module.
This ECO removes the MMU from the
M8186. ECO KDFIIA-MLOOI adds it
back in at the option level (KDFII-AB,
KDFll-AA). This is a documentation
change only.

Modules in systems mayor
may not have MMU,
depending upon which
option they represent.
Spares, however, are
ordered as modules and
will not have MMU's.
MMU'sImlst be ordered
separately.

1. No jumper table in printset
(documentation change only)

1. Prints contain a
jumper table

2. Crxstal oscillator may short to
adJacent components.

2. Oscillator has nylon
spacer. Manufacturing
change only.

momoomo

MICROCOMPUTER
PRODUCTS
GROUP
306

)lnote

NUMBER l04
PAGE 6

ECO # PROBLEM
QUICK VERIFY
------------_._----------_...:..:-_--------,---"'--

3. Module will h~ve W2
removed ~n~
~n.
On etch Rev A" modules,
W3 is in~tAlled by
solderin~ a jumper wire
from E2 Pin 5 to E2
When ECD M8l86-ML007 is put in
Pin 15.
When a ucode option (i.e. KEFll)
is installed.
When a 40 Pin IC (CTL/DAT, t-"lMU
or KEFIl) is replaced.
Whenever unexplained system
crashes are occuring.

Possibility of worst case MMU
timing violations. Change configuration of W2 and W3 to adj ust timing.. This ECD must be
installed:
A)
B)
C)
D)

mamaomD

MICROCO~'PUTER

PRODUCTS
GROIl'P
307

W,
IF

)lnote

NUMBER 104
PAGE 7

OF 7

ECO's in Other Options, but Related to the ~1/23
RXV2l

(M8029) -

Modules at CS Revision "E" and lower aannQt OQ:t:rtu,::t:ly
DMA across a 64Kb boundary.
This will pgy§e
DECX to fail in an 11/23 and could ~ftegt QM§tom or
modified device drivers.
It doe~ not atf@pt ~gdules
installed in 11/03-based Bystems. Modu~@§ in§talled
in 11/23's must be at CS "Revision "F,r O:J= higher.

BDVll

(M8012) -

Prior to ECO #2, the BDVll did not provide proper
termination for BIRQ6. Modules installed on 11/23~s
should be at CS Revision liD" or higher.
(Only a few
early units are affected.)

DLVII-J (M8043)-

The DLVII-J will respond to incorrect bus addresses when
used on 11/23 CPU's unless ECO #2 is installed. Modules
used on 11/23 systems must be at CS Revision "E" or
higher.
'

~DmDDmD
MICROCOMPUTER
PRODUCTS

GROUP
308

NUMBER

).Inote
TITLE

105

MXVII BOQTSTRAP PROBLtMS

DISTRIBUTION

Yt:lB~~:l:RI~:l:~1:2

ORIGINATOR

BE~EBLY

DATE
2

/ 3 / 81

PRODUCT
MXVll

PAGE

1 OF

Two problems have been noted at bootstrap time in systems
containing an L51 11/23 processor and an MXVlI.
The first ~roblem occurs when using the MXVll-A2 ROMs to boot
fronl a TUS. The bootstrap p~ogram halts when executed immediately after power-up, in processor power-up mode 1 or 2. However,
when the boot is tried again from ODT (773000G) it is successful.
The cause of this behavior lies in the TUS8 bootstrap code on
the MXVII ROMs (refer to unote 62~~). The MFPS instruction at
locClltion 173024 moves only the lO'rl byte of the processor status
word into location 6. Memory is sized by writing successively
to each location until a non-existent location causes a trap
to 4·. The new PSW is picked up from the word at location 6,
but only the low byte has been initialized. The high byte
cont.ains random data.
Bits 14 and 15 of the PSW determine the mode of the processor,
kernel or user. If location 6 has l's in these bits, the
processor will go into user mode causing some differences and
restrictions in operation. For e~{ample, a HALT instruction
causes a trap to 10, a RESET is e~{ecuted as a NOP, and different
stack pointers are used in each mode.
The ROM bootstrap completes execution and the secondary bootstrap read from the TUS8 begins. The secondary boot executes
until it encounters an illegal instruction - i.e., a HALT.
The failure mode will differ depending on the secondary boot
read from the tape. The system will boot successfully the
second time it is attempted because a subsequent routine in the
ROM code, MEMT, wri tes ~'s into mE~mory. When the boot is tried
again, the upper byte has been cleared, and the status is picked
up as intended - in kernel mode.

~DmDDmD
MICROC0141PUTER
PRODUCTS
GROUIP
309

j./note

NUMBER 105
PAGE

2 OF 2

Note that this problem will occur only in ll/23/MXVII/TU58
systems, and the boot will succeed if location 6 is cleared
before starting execution. This error has been corrected in
a new version of the MXVIl-A2 ROM's.
The second problem is evidenced by the processor hanging on
power-up. By halting the processor (break key, halt switch)
and going into ODT, then typing 773~~~G, or pushing the restart
switch, the system will boot. For this second problem, the
bootstrap device is not limited to the TU5S, and the ROM code
is not necessarily the MXVll-A2 code.
This problem is caused by a failure to initialize a latch on
the MXVll at power-up. This latch enables the gating of
DIN, and subsequently generates BRPLY. The result is a BRPLY
may be sent by the MXVll even though it has not been addressed.
ECO M8~47-MR~~2 corrects this problem. Installation of this
ECO brings the MXVll to circuit schematic revision C.
If you have any further 'questions, please contact the LSI-li
Hotline.

~D~DDmD
MICROCOMPUTER
PRODUCTS
GROUP
310

).Inote
TITLE

MXVll FUNCTIONALITY

DISTRIBUTION

UNRESTRI~TED

ORIIGINATOR

Bruce Gollob

NUMBER
106

DATE
.1-

/~Q

PRODUCT
MXVII

PAGE I

OF 3

The purpbse of this u-note is to describe the functionality
of thE~ MXVll-A series modules, and describe a system configuration
wi th itwo MXVll-AC multifunction modules.
MXVll·-A FUNCTIONALITY
The multifunction module (MXVll-A series) contains two
asychronous line interfaces, space for two user configured ROMs
or thE~ system device bootstrap ROMS, memory with on board refresh,
and a crystal clock which can be used to generate the system line
time c:lock. There is no provision for battery backup, or to allow
addressing of the top 2K words of memory in a 30K word system. The
board has 18 bit address decoding, however, the RAM memory decodes
only 16 bits, therefore in a system with more than 3~K words of
memory, the MXVll-A on board memory must be placed in the range of
0-32K words (000000-177776) .. Removal of the zero ohm resistor W4
on thE~ MXVll-AA or WS on the MXVll-.l\C will totally disable the RAM
memory on the multifunction module.

).Inote

NUMBER 106
PAGE 2

OF 3

SYSTEM CONFIGURATION WITH TWO MXVll-AC MODULES
When a sys.tem configuration requires mu1 tiple MXV1l-AC modules,
special care must be taken to insure that no two options on the boards
have the same address.
In the system configuration shown below there
is no memory overlap and each slu address and vector is unique.
It is
only necessary to have one bootstrap and line time clock per system.
Therefore, the bootstrap and the line time clock on the other board
must be disabled. Channel 1 on any MXVll-A series module, whether it
is the console or not, can be configured to ignore break, to halt on
break or reboot on break. To disable an option on the multifunction
module,all of the jumpers associated with the option must be removed.
This must be done, otherwise the board is left in an unknown state
which could cause unpredictable results.
The chart shown below shows one way to configure two MXVll-AC
modules in a system. The system configured contains 32K words of RAM,
the MXVIl-A2 disk bootstrap, and four asynchronous serial line interfaces, one of which is the console interface.

RAM

#1 BANK 0-3 (000000-077776)
#2 BANK 4-7 (100000-160000)
SLU ,ADDRESSES
CH. 0
CH. I

#1
176500.
177560

#2
176510
176520

#1
300
60

#2
310
320

SLU VECTORS
CH. a
CH. 1

ROM BOOT (DISK)
ROM ON #2 DISABLED

MXV1l-AC #1
from
to

MXVII-AC #2
from
to

J30*
J32*
J31*

J31
J33
J32

J30*
J31
J32

J31
J33
J34

J23*
J24*

J18
J19

J23*
J24

J18
J12

CH. 0

-----------------------------------~-

J26
J25
J27*
J28*

J16
J17
J13
J19

J51
J52
J54
J57

J56
J55
J54*
J53

J58
J57
J52
J51

J38
J22
J37
J39
J16

J21

J26*
J25*
J27*
J28*

J15
J14
J13
J19

J56*
J54*
J53*
J53*
;]37*
J21*
J34*
J33*
J29

~DmDDmD
MICROCOMPUTER
PRODUCTS
GROUP
312

CH. 1

NUMBER 106
PAGE 3

~[XVII-AC

MXVII-AC #2

from

OF 3

-----------------------~-----------------------------------------------SLU
8 DATA BITS'
J'S9*
J61
J59*
J61
J'61*
J62
J62
PARAMETERS
EVEN PARITY
J61*
J'60*
J63
J63
J60*
1 STOP BIT

8 DATA BITS
EVEN PARITY
1 STOP BIT

J62*
J64*
J63*

J64
J66
J65

CH.O

9.6K

J45

J48

CH.O

J62*
J64*
J63*

J64
J66
J65

J45

J48

J68*

J67

-----------------------------------------------------------------------J46*
J48 CH.l
J46*
J48
BAUD RATE
9.6K
------------------------------------------------------------------------

BREAK GENERATOR (NOT USED, REMOVE FACTORY JUMPERS)
CRYST}~L

CLOCK

J68*

J67

------.-~--~-~~--~~~~~--~~~-~~-~-------------~--~------------~----------J4
J3*
LINE 'J~IME CLOCK

----~-.--------------------~---~--~-----~--~-------------~----~--------~-

*FACTORY INSTALLED JUMPERS.

~DmnDmD
MICROCC)MPUTER
PROI.UCTS
GRC)UP
313

NUMBER

}~note
TITLE

107

DATE

22-BIT ADDRESSING FOR DBA CHIFKIT USERS

/ ,r;

DISTRIBUTION

Unrestricted

PRODUCT

ORIGINATOR

. Chris DeHers

CHIPKIT

PAGE

/Rl

.OF 2

This uNote is intended to assist chipki t users who are designing DI-1A interfaces for
use with 22-bit (Q-22) addressing in LSI-ll/23 based systems.
To extend the D~~ addressing to 22 bits, t:he following must be acco~plished in addition
to using the chips provided in the chipkit:
1.

Provide a 6 bit addre'ss counter which will advance on overflow from the DCOD6.
These six bits, along with the 16 bits; from the DC006 will form ·the 22 bit address.

Provide for'read/write of these 6 bits as bits 0-5 of a user-defined bus address
extension register.

Provide for placing these 6 bits on address lines
of the· DV.L.A transfer cycle.

Clear the additional bits upon initialization of the bus.

l6-2.~

during the address portion

The following figure ~utlines the additional hardware. No extra chipkit hardware is
needed. Signal mnemonics are consistent with those found in the Chipkit Users Manual.
This design does not consider an 18 bit or combination 18/22 bit-addressing configuration.
Informa1:ion on designing an 18 bit interface can be found in uNote #69 •

....

~~~~~~~
MtCROCOF4PUTl!R
PRODUCTS
GRC~UP

NUMBER·
PAGE 2 OF

.~~

---~I

~,::

BUS .

J:,

\:.r

~-<'
i
~~l i!

i !

------7--;1-·:--:--'--'1-1---

. l, ~ ~·:i -,' :

_._. __.__

~,-t:j8881~PA!'19

n!::; .
____-==
-===LB

~'QFl
.... ='=:2~
--'-r I· i,' ;. ~ ~ DE
QE I -',• . ::=:L.il~____
0-.:

QQQl " \ ..-JmAI!20

, ;l'~-'

QD~ '.- e I

h -

OB
0
----- - lI iI . • •_-- .bB
DC QC :l'
'-. 1'"I
-------1 -.. ' - - - - b A QA --'~---+e.____

---

. - - - - - - ....

)bC'~

BtJSI~~R 7 4 L S 2 9 9 :
REG

R ..

CSR ...J

LOGIC T

ADDRESS

)

8881 .. .:BDALl _>

, •
I I

WLB
Y INTERFACE ~
STROBEDOBLOAD INITIAL

~19
~!

RESS EXTENSION

! .......,

DATA 5
DATA 4
DATA 3
DATA 2
DATA J.
DA'TA ~

-~LJU

_:'-

I,;

CSRRD

:----<. ,

~DAL2L>

---I

I' / '/";- - - - - ;

I·
i

'
0 f
! . 8881

I~~~
~.

I~
BY IN':t~ERFACE LOGIC TO
~.:ED
a::l'<'TD~
R2J.,o 'O"="",,'T~"'"
~.;;lU_"""

DRIVER

FROM

, :

Ie'" BINIT

, ,

INIT L

MAX A
F HIGH BYTE

FROM OVERFLOW 0
IN DC006

;

~I
I
~BD:ar'6)
l.-;'L~~
!

. .

ADREN H
FROM DC010

~~m~~6~

k:[CROCOI~PUTER

PRODUCTS
GROUP

NUMBER

).Inote
AAVll-A, KWVII-A vs.
AAVll-C Differences
Unrestricted
DISTRIBUTION
TITLE

ADVll-A~

ORIGINATOR

108

DATE
~~DVI1-C,

KWVII-C,

01 /

/82

PRODUCT

Ernie Strange

PAGE i

OF 12

The following information compares the cu.rrent analog products (AnVll-A, AAVll-A)
with their replacement ADVll-C, AAVll-C. The real time clock KW'Vll-C and KW'Vll-A
are functional equivalents. The terminology, as well as the specifications on both
are identical.
Diagnostics used on the AAVll-A and KWVll will run also on the AAVll-C and KWVll-C.

~B~fi[J~D
MICROCO'MPUTER
PRODUCTS
GROUP

ADV11-A vs ADV11-C
NOTE:

-NIl

Represents significant differences
Represents slight differences
Means inforcation not published
ADV l1-A

ADVll-C

Resolution (A/D)

12 Bits

Linearity

: 1 LSB (end point)

: 1/2 LSB

29~ of State Widths
- 1/2 LSB; No Skipped
States; None> 2 LSB

Sane

Gain - 6 PPM/oC
Linerarity - 2 PPM/oC
Offset - 7.5 PPM/oC

25 PPM/oC Total

1/3 LSB Rt·1S;
Peak (module)

0.2mV. RHS

(A/D)·

Differential Linearity
(AID)

S tability

Noise

(A/D)

LSB
_.

1/2 LSB RMS; 1.5 LSB
Peak (in a system)
5 mins. max.

N/A

24, 390 ChannE~l
Samples/Sec.

25,000' Channel
Samples/Sec.
-30 Volts

Input Protection

Fuseable Resistors
(! 85V.)

Coding

Offset Binary

Offset Binary or 2's
Complement

Warm Up
Thru-Put

(A/D)

••

Input Range

••

5.J2V

10V, 0 to +10V

Software Programmable
Ranges

None

Xl, X2, X4, X8

Number of Channels

16 Single-Ended
(8 quasi-differential)

16 S.E
8 True Differential

Input Ir.lpedance

100M

ADV11-A vs ADV11-C
Input Impedance (power off)

N/A

-Input Bias Current

50nA max.

•

CMR

1 Kohm min.

N/A

>80 db at 60 HZ

S & H Aperture Uncertainty

H/A

<10nS

+5V/2A

5V 11. SA

Power Required

+12V/.45A

External Trigger

Hi-Lo Edge

•

Load Desired Channel
Into Bits 8 - 11 of
CSR (16 channels)

Bits 8 - 13 of CSR
(up to 64 channels)

AID Start

Bit 0, CSR

AID Done

Bit 7, CSR

Bit 7~ CSR

Error(s)

Bit 15, 14, CSR

Interr'upt Enable

Bit 6, CSR

Clock Enable

Bit 5, CSR

External Trigger Enable

Bit 4. CSR

Bit 4, CSR

••

I.D. Enable
Maintenance

ProgrammableXl,X2,X4,X8
Gain. Amplifier

CSR Base Address

VIA Dip Swi tl~h
Range; 170000-177774

Wire Wrap
170000-177774

. Data:

Vector' Address

Via Dip Swi tl~h
000-770

Wire Wrap
000-770

Operating Temperature

10 0 _ 60 0 C

00 - 70 0 C

Input Connector (Jl)

40 Pin Berg

26 Pin 3t-1

•

ChannE~l

Select

Bi ts (~, 3, CSR

Bi~s 0··11; I.D. =
Bit 12
Data: Bi ts 0-' 1
Doubled Buffered
Bits 12 - 15 = MSB
(signed extended)

ADV11-A

vs ,ADVll-C

REGISTERS

VERNIER D/A (WRITE)

~
. I I . ! I . I I J i I I ! I

IS 114 13 12111 10 09 °8 07 06 °5 04 03,02 01 00

~~~~~M~S~B

_________

__________

~L~S~E~

CONVERTED DATA (READ)

ADV1'-A DATA BUFFER REGISTER (DBR)
A/D DATA BUFFER REGISTER (READ ONLY)

15 14 13 12 11 10 09 08 07 06 OS 04 03 02 01 00

170402
(BASE ADDRESS +2)

lI2 I I
SIGN
(USED FOR
TWO'S
COMPLEMENT
NOTATION
ONLY)

ADV11-C DATA BUFFER REGISTER (DSR)

Bits 12 - 13 have a different function.

LSB

ADV"-A

·ADV"-C

REGISTERS

12 11 10 09. 08 07 06. 05 04 03 02 01

I I

NOT

W\INTj. AD

USED

STAR
ENA

START

ERR
INT ENA

DONE

CLK
START
ENA

ID
ENA

NOT
USED

ADV"-A ~ONTROL/STATUS REGISTER (CSR)

A/D CONTROL/STATUS REGISTER (READ/WRITE)

14 13 12 11 10 09 08 07 06 05 0.4 03 02· 01 00

I I l-r-:-i

170400

(BAS:E ADDFESS)

-....."

ERROR

NOT
USED

ERROR
INT ENA

MULTIPLEXER
ADDRESS
A/D

RTC
ENABLE

DONE
INT ENA

GAIN
SELECT

E T
TRIGGER
ENABLE

ADV1'-C CONTROL/STATUS REGISTER (CSR)

Bits 2, 3 have a different function between ADV1'-A and ADV"-C.

START

NOT
USED

AAV11-A vs AXV11-C

The following specifications describe the two DI A channels on the AXV 11-C.
The DEC ADV11-A does not have D/A capability, therefore, the 2 D/A channels
will be compared with the D/A specification of the AAV11-A four, channel D/A.
AAV11-A
Resolution

AXV11-C

12 Bits

Output Voltage

+
+
10.24
-2.56, -5 .. 12,
o To +5.12, 0 T() 10.24

!10V, o To +10V

Differential Linearity

!1/2 LSB Monotonic

='/2 LSB Monotonic

Linearity

:112 LSB

=1/2 LSB

5V/us

.33V/us

Slew Rate

D.C. Output Impedance

.05

.*
Rise Time

Bus. to .1S of F.S.

35us. to .01S F.S.
(for 10 volt change)

AAV11-A vs AAV11-C
Comparison of .the AAVll-A and AAV11-C 4 channel D/A (the AAVll-A diagnostic
also runs on the AAVll-C).
AAV11-A
Resolution

AAV11-C

12 Bits

Differential L~nearity

=112 LSB (monotonic)

=1/2 LSB

Linealri ty

=1/2 LSB

..
••

30 PPM/oC Max

liain Drift

•

15 PPM/oC Max

Offset Drift

••

Output Impedance

••

Ranges

•

Output Current

0.05
+
+
-2.65V. -5.12V,
+

-10.24, 0 to 5.12V,
o to 10.24V
5mA

lOrnA

5V/uSec.

20V/uSec.

4us to 0.'1 ~

For 20Volt Change,
6uSec Max. To within
!.1~ of Final Value

+.5V/l.5A, 12V/ .4A

+5V/2.0A

Size

. Quad

Dual

Digital Output
Base Address Selection

4LSB's of DAC "3"
Same Range for Bc)th

4LSB's of DAC "0"

•

Slew Hate

•

Settlj.ng Time

••

Power

Bus Loading

••

The rl:!al time clock, KWV11-A and the KWV11-C are functional equivalents.
The te:rminology (as well as specification.s) on both are identi.cal. In fact,
the KWV11-A diagnostic will run on the KWV11-C.

ANALOG DEFINITION
RESOLUTION - The resolution of an AID converter is defined as the smallest
analog change that can be identified. Resolution is the analog
value of the Least Significant Bit (LSB).
EX: A chemical processes can deliver
control flow~to w1thing .2 of an oz.
Resolution

gal/min.

desired

LSB = Full Scale Range
212 Code Combinations

1 Gal = 128 oz.

LINEARITY -

EX:

128 oz
4095

= .03125 oz.

Is defined as the maximum deviation from a straight l-1ne drawn
between the end points of the converter transfer function.
How close to a straight line are ac"tual readings.

Gi ven as a percentage of full scale or as a fraction of LSB.
Usually at either extremes of range a non-linear (or deviation)
value occurs.

ANALOG DEFINITIONS
DIFFERENTIAL LINEARITY The maximum deviation of an actual stated width from its
theoretical value for any code over the full range of the
converter. A differential linearity of 1/2 LSB-means that the
width' of each code over the range off the converter is 1 LSB
+
-1/2
LSB.
Missing codes in an A/D converter occur .-when the
output code skips a digit. This happens when the differential
linearity is worse than -:, LSB.

EX:
DIGITAL
LSB

VALUE

/
/

STABILITY -

EX:

, . . - - - - - - - Theoretical "/
~l~
1/2 LSB.

How.will the value change as temperature varies?
Gain = 6PPM/ o CThe gain will not change more than 6 parts per million for a 1
degree centergrade.

NOISE

In an ideal system no noise is generated (zero noise). In the
real world some noise will be introduced into the system thru
the cable, module (A/D converter). power supply.

THROUGHPUT - Is the number of samples per second that may be taken.

EX:

System throughput = N (n) X (S.W) samples/sec
Channel 1 = 150 HZ
Channel 2 = 800 HZ
Channel 3 = 400 HZ
System throughput = N(n) X (Highest Band Width)

N = 10

sample~/se?

(Sampling Factor)
Normal from 5 - 10 samples per cycle are needed to give a
resonable reproduction of sampled signal

= 3

(Number of Channels)

BW = 800
Throughput = (10) (3) (800)
= 24K Samples/Second

ANALOG DEFINITIONS

CODIUG
--BINARY

Full Scale Input Voltag!

Output Code (Octal)

+9.9976V
0.00000

007777
000000

The 'binary numbers f9 r• cS',m9760V(.8)
input voltages OV to
BINARY
OFFSET

Full Scale Input Yoltag~
+9.9951V
O.OOOOV
-10.0000V

to 007777 (8)

represent the

Output Code (Octal)
007777
004000
000000

Using the binary offset technique, a zero voltage point is
established at 004000 (8) •
This technique is usually used
when both positive and negative voltages ~re present.
nJO'S

COMPLEMENT

Full Scale Input Voltage
+9.9951V
O.OOOOV
-10.0000V

Output Code (Octal)
003777
000000
174000

Using Two's Complement, OV in is represented by 000000 fR')
in the output code. -10V in is represented by 174000. THe
output code range is still 007777(8) it's just formated
differently.

ANALOG DEFINITIONS
INPUT RANGE

SOFTI/ARE
PROGRAMMABLE
RANGES

The range of voltages that can be applied to the input of an
AID converter. If this range is exceeded damage may result
to AID converter.

Allows the resolution to be increased by changing the full
scale voltage range.

E"x: If the gain is set' at one and the input vol tage is from 0 10 volts;
Resolution

Voltage Range
= Full Scale
1. . '
2 c:"

Resolution

l0V
4095

= 2.442 mv

-Changing the programmable gain to 8 allows the input voltage
range of 0 - 1.25V.
Resolution

= 1.25V = 305.2 mv
4095

NUMBEB OF
CHANNELS

INPUT
IMPEDANCE

Channels are a communication path thru which analog voltages
are translated' to Digj~ tal information.
The number of
channels specify how many analog voltages may be monitored.
The amount of internal impedance of the input channel. The
higher the impedance the less loading on the external
circuit occurs.
Ideally the input impedance would be
infini te so no current would be drawn from the external
source.

ANALOG DEFINITIONS
INPUT BIAS
CURRENT

The amount of current that
channel from the source.

CMR
S

flows

into the, selected

AID

Common Mode Rejection is the ability of a differential
amplifier to reject noise common to both inputs.

APERTURE
UNCERTAINTY

Sample and Hold Aperture Uncertainty is the change in
aperture delay times between specific sample and hold
commands.

CHANNEL
SELECT

The control status register has bits (8 - 11) dedicated to
selecting one of 16 possible channels.

SLEW RATE

The capability of the output of an analog circuit to change
its voltage in_a given period of 'time. EX: If the slew rate is 5V/uSec, the analog circuit output will
change five volts in o~e uSe~ond.

GAIN DRIFT

Is the amount of change in gain due to the temperature
co-efficient of the components.

OFFSET DRIFT -

Is a function
components.

the

temperature

co-efficients

the

NUMBER.

).Inote

109

DATE

UsinS the FALCON SBC-ll~2l in a Standalone
Environment
Unrestricted
DISTRIBUTION

PRODUCT

Charlie Giorgetti

FALCON

TITLE

OHIGINATOR

04/ 13

PAGE 1

The FALCON SBC-ll/2l can be used in standalone applications. The user must
interface to the module with power via a connector block and then mount the
FALCON SBC-ll/2l. Environmental requirements should be adhered to when the board
is mounted (see the Microcomputer Handboc,k Series for environmental specifications).
The mounting holes for the FALCON SBC-ll/2l are shown in Figure 1. The FALCON
SBC-ll/2l should be mounted using the holes provided. When the actual mounting is
done, insulated washers should be used to isolate the screws from the module
surface. Insulated standoffs should be used to raise the FALCON SBC-ll/2l off
the surface to which it is being secured. The standoffs should have the following
chara1cteristics-: 0.15 inch diameter, .1 inch hole size,o and a height of at
least 0.75 inches. The connector block that is recommeded for use with the FALCON
SBC-ll/2l is DEC part number HB030. This is a 72 pin block that fits over the
modul.e edge. connector and allows a user to access a finger via wirewrap pins that
are on the connector block.
Since the FALCON SBC-ll/21 supports on-board wake-up circuitry, the +5 and +12 volts
can b~e obtained from any supply which is capable of. meeting the modu+e' s power
requirements. A power supply, such as the DEC H7BO, can be used in those applications
that require power fail detection. The needed voltages can be applied to the
connector block on the following wirewrap pins:
GND

AMI, AC2, ATl, AJl, BC2, BTl, BMl, or BJI

+ .)1"

AA2, BA2, or BVI

+JL2

BD2

Refer to the Microcomputer Handbook Serie:s for the locations of each wirewrap pin.
It is of interest that in FALCON SBC-ll/21 applications that are not using the
serial line units only +5 volts is requirl3d.
For applications that are using battery back-up for the on-board static RAM, in the
event of a power failure, +5BB is applied to pin AVI on the connector block.

~U~Dfj~D
MICROCC)MPUTER
PROCIUCTS
GRC)UP

).Jnote

NUMBER
PAGE

o
o

o
Figure 1.:

COHPONENT SIDE VIEW OF FALCON SBC-l1/21

~D~an~D
MICROCC>MPUTER
PRO[)IUCTS
GRC)UP

109

OF 2

NUMBER

).Inote

110

DATE

MUL, DIV, and.ASH Instruction.1or the FALCON
SBC-ll/2l
unrestricted
DISTRIBUTION

PRODUCT

Charlie Giorgetti

. FALCON

TITLE

ORIGINATOR

/ 13 /82

PAGE 1 OF

The FALCON SBC-ll/2l 'supports the standard PDP-ll instruction set. There is
no hardware support for the EIS, FIS or FPP instruction sets. For FALCON
SBC-ll/2l applications that need the ability to perform the EIS instructions
MUL, DIV, and ASH, equivalent software routines can be substituted. These
callable routines do not do any form of error checking. A user should be aware
that extensive use of these software routines for hardware instructions will have
impact on system performance.
These routines can be incorporated into an application and called as a subroutine.
The calling sequence for the subroutines: can be set-up in a macro. The following
is a list of each of the subroutines and the macros that are used to set-up and
call the software MUL, DIV, and ASH rout~ines.

~fI~Dn~1l
MICROCOMPUTER
PRO,DUCTS
GROUP

).Jnote

The

MUL

tollo~inY

instr~ctlon

OF 4

ruacro ana sUDroutine can De used to perform tne

in sottware:

.MACRO

SMUL

til 0 V
MOV
JSf<
"'·0 V

A,-(SP)
B,-(SP)
PC, $ ,'lUL
(SPJ+,HI
lSP)+,LO

MOY

NUMBER, 110
PAGE 2

A,8,HI,LG
han, u 1 tip 11 e ron tot nest a c l<
.; Pus
PUSh the other multiplier as well
Call tne
sUbroutine
,. Get ttJe most Significant part of the result

~UL

(jet trJe leest significant part of the result

• E' "I LJ r.~
Sj·~UL: :

t-iOV

Ru,-(S?)

MaY

Rl,-(~fJ)

HOV
MOV

1;21,-(SP)

eLk

lOs:

HOR

HO
RO

HOk

ADD

20s
lO(Sf'),kO

Bee
20$:

lO(SP),Rl

CLC
DEC
bl~£

(SP)
lOS

T.S1

(SP)+

MUV

fd,lO(SP)

~'IOV

RU,b(::>P)

~:(J V

(SP)+,Rl
(S?)+,kO
PC

"'10'1,
~1':)

~dve

SOffie

~orK

registers

ub t ,0 1 n t I! eVe 1 u e

0 t A t r 0 fI, t n est a c l<
Initialize tne Shltt counter
Initi~lize the high 16-bit accumulator
; t: e r ,f c r rn n! u 1 t 1 p 1 i cat ion

Bump the snift counter
'; Not done?
; Re~ov~ the counter from the stac~
Save the low 16-oit value on the stack
; Save the hi~~ 16-cit value on the stack
Kestore tne ,ork registers
Return

mD~DD~D
MICROC(jMPUTER
PROIOUCTS

GRC:> UP

J-It"lote
'1 tIe

NUMBER
PAGE

t 0 J. 1 0 jI,. i n g IT· a c r 0 a nos ~J Dr 0 uti n e c 6 n

Instruction 1n

use a top e r tor ill

110

OF 4

t tJ e LJ I 'J

soft~are:
DIVSOR,DIVHl,DlVLL,~E~,GUO

• J-;ACkO

~Dl V

~iOV

,.·.uv

ulVSCJE,-CSP)
DIVnl,-(SP)

,.;0'1

uIVLO,-(SP)

JSf\

PC,SDIV
(SP) ... ,Rt:M
(SP)+,QuO

MOV
t-.C V

0 e

ttle divisor onto the stack
fiush tne ~p~er 16-~its of tt'le dividena
PUSh the I O"'~ e r ib-nits ot tne dividend
Call tne uIV subroutine
Get the r en'Q inde r
; Get the quotient
PUS fJ

;
;
;

.ENl.H'1

SDlv::

tJ.OV
"IG'v
1>1 0 'v
,.,. CJ 'v

MOv

CLR

MOil

if32.,-(SP)
R5

ASL
HOL
kOL
C~P

bLO
SUo

INC
2S:

~ 0 If,

e w0 r k reg i s t e r s

;

the a 1 v 1 5 0 r fro 01 the 5 t a C K
t r. e tj 19 rl 1 6 - bit sot the d 1 v ide n d
c:;) ~ell as lOtti'16-bits'
Clear an accun:ulator
Snift counter
Per tor fjl the d 1 vis ion

(; e t
G f' t

HO
f<O,k3
2S
t':3,PO
R5

DEC

(SP)

cNt::
'lST

1$
(SP) ...

MOV
t'lO V

RO,12.(SP)

kS,l't.lSP)

MuV

(SP)+,~:O

MOV
Po'. 0 V

(SP)+,k3
(SP)+,R4
(SP);.,H5

~'.OV

; (, e t

l-<O,-CSF)

14.(SP),R3
12.(SP),R4
lO.(SP),k5

MGV
!JOV

ts:

R5,-CSP)
P4,-(SP)
R3,-CSr')

; Not done ?
Kemove tne counter from the stac~
S tor e t n ere In a 1 n de r o,n the s t a c k
Store the quotient as ~ell
kestore tile .,,'ork registers

r'lOv

(SP)+,(Sf')

~~date

kTS

Return

the return PC

~11~~BD~D
MICROICOMPUTER
PRC:>DUCTS
GIROUP

").Jnote

The tOllo'vwing rt.dcro and sut'routine can

NUMBER
PAGE 4

boe

110

OF 4

used to pertorlo tne ASh

instruction in sottitfare:
SASH

COuNT,-{SP)
VAL,-C.sP)
PC,SASrl
(SP)+,VAL

Push the snltt ~ount
Push ~hat is to be sh1fted
; Call the ASh subrout1ne
Get ttl ere s u 1 t s 0 f the S h if t

f-HJ V

kO,-(Sf-'J

;

ro'lOV

MaV

i\l,-CSP)
b(SP),kO

i,'IUY

8.(SP),Rl

~IC

R A C,<77>,kl

be:: 'l
eMP
bGT

20$

Get

Rl,rt31.

~hat

MOY

JSR
t·\OV

S A .s rl : :

5$:

CULif\iT,VkL

.1-'.ACkU

ASL

lOS
°

bNE

t:)R

20S

lOS:

t\"E.G

l1S:

hlC
ASk
DEC

kCl

20s:

eNS
MOV
MOV

RO,8.(S~)

tlDV
RTS

cou~le

of worK registers

= value to be shittea

= oirect10n ana shift count

it no shifting
airection 1s the 5hi1t
Go to toe corect10n direction shift
o~t

DI=:.C

Mav

~et

C< 7 > , H 1

Hi
I1S

(Sf')+,kl

; Store the shifted result on tne stacK
: Restore tne .0rK registers

(SP)'t,RO

CSP)+,(SP)
PC

Upoate the return PC
kf~turn

~1J~1)[1~D
MICROC()MPUTER
PROI)UCTS
GR()UP

NUMBER

).Inote

,,,

DATE

TITLE DIFFERENCES BETWEEN MSVll-L and MSV1I-P MEMORIES
DISTRIBUTION

Unrestricted

ORIGINATOR

Mike Collins

os!

PRODUCT

PAGE

There are now two ser~es of memory boards for the LSI-Il bus which have full parity
functionality on-board and also utilize the 22 bit addressing capability. They are the
MSVI1-L an.d the MSVIl-P.
This uNOTE will discuss differences existing !~tween the MSVll-L and P memories
which should be considered when choosing and configuring these boards for a system.
DIFFERENCE:

MSVll-L is a dual height module.
MSVll-p is a quad height module.

The MSVll-p memory is physically twice the siz:e of the L memory and requires a quad
size backplane (e.g. the H927S-A, which is a 9 x 4 backplane).
DIFFERENCE:

MSVll-L has 8 CSRs (Control Statu.s Register).·
MSVll-p has 16 CSRs.

The CSR allows the user to enable parity er~or reporting and will also report the
error to within a 2 Kbyte segment of memory.
Wi th MSVll--L memories, full pari t.y functionality can be utilized on up to a maximum
of 2 Megabytes. The MSVll-P memories have 8 additional CSRs which allows the complete
4 Megabyte!3 of address space to use the full parity feature-.
DIFFERENCE:

MSVll-L memories are configurable on 8 Kbyte boundaries.
MSVII-P memories are configurable on 16 Kbyte boundaries.

This infon~tion must be kept in mind when configuring the boards in a system.
Previous tC) the MSVIl-P, all other memory opti.:)ns were configureabie on 8Kb boundaries.
This includes the MSVll-'C, D and E memories.
No problems would arise if only L and P memori,es are used in a system and they are
configured contiguously from a starting address of zero. However, a problem could
occur if al.l of the following conditions exist.:
Both Land P memories are to be used in a sY:3tem. The memories are to be
contiguotls and an L memory is configured first with a starting address on
an ODD 8 Kb boundary.

~D~Dll~~D
MICROCOMF·UTER
PRODUC·rS
GROUP

)Jnote
For example:

NUMBER
PAGE 2

111

A system uses 1 MSVll-LK memory (256 Kb) and
1 MSVll-PL memory (512 Kb).

If for some reason the MSVll-LK memory is' configured for a starting address of
8 Kb, its last address is 264 Kb (256 Kb + 8 Kb). But the MSVll-PL cannot have
a starting address of 264 Kb·because ·it is only configurable on 16 Kb boundaries.

If the P memory is configured for the next possible starting address, a "hole"
would e~:ist in the memory space, and the t'flO memories would not be contiguous.
MEMORY

784 Kb

lJ,[SVll-PL
272 Kb Next configurable address for MSVll-PL

"hole"
264 Kb MSVll-PL cannot: be configured to have this starting

address
MSVll-LK
8 Kb MSVll-LK starting address.

DIFFERENCE:

It is possible to disable half: of the MSVll-L RAM array.
no provisions for disabling ~~ on the P memory module.

There are

If bad mc~mory exists in one of the two 128 Kb sections of the MSVll-LK, the bad
section can be disabled. The board will then look like a half populated module and
the addr(~ss will be from 0 Kbyte to 128 Kbytes. As stated above, there are no
jumpers ()n the MSVll-P memory which allow selective disabling of the RAM array.

~D~DD~D
MICROCOJMPUTER
PRODUCTS
GROIUP

).Inote
TI'TLE

IS-BIT RXV21 in 22-BIT LSI-II RSX-1L.'1 V4.(I

DISTRIBUTION
OFUGINATOR

Un-restricted

NUMBER
112

DATE
2 /

PRODUCT

Bernie A1imonti

PAGE 1 OF

Incorporating an 18-BIT RXV21 Controller
Into a 22-Bit LSI-II RSX-IIM V4.~ System
The LSI-II Bus specification has always provided for 22-bit
·addressing. However, only since spring of 1982, has DIGITAL
acknowledged and supported 22-bi t addressing on the LSI-II
Bus4t
The RLEJI/RLiJ2 mass storage! controller for th4;L L.SI-Il
Bus was redesigned in 1982 as the RLVI2J and includes
Sjl2Port for 16-« 18- as well as 22-B1 t addressinq. "'Hie--n92
mass storage controller for the LSI-II Bus, the RXV21,
~tver, does not support 22-bit addressing.
RSX--IIM V4. 9 supports 22-bi t addressing on LSI-II systems,
and supports the RLV12 in a 22-bit LSI-II. However, it does
not support the RXV2I in a 22-bi t LSI-II
The reason for
this is that without 22-bit addressing the RXV21 cannot
perform DMA into the total range of addresses.
Below is a
dis(:ussion of how you can, in fact, incorporate an RXV21
into your LSI-II running a 22-bit RSX-IIM V4.9 system.
The RSX-IIM RX92 driver, DYDRV.MAC, assumes that if 22-bit
addressing is performed, it is performed only on a UNIBUS
syst:em. With this assumption, 22-bit DMA is performed using
UNIBUS mapping registers (UMR). If the code for the UMRs is
used in a 22-bit LSI-II system, RSX-IIM will not operate
properly. Therefore, the approach taken here to incorporate
an RXV21 into a LSI-II 22-bit running RSX-IIM is to modify
DYDFtV.MAC not to use UMRs. Together wi th the driver change,
tasks that do I/O to the RX92 are restricted to reside only
in the first 256KB of memory.
The modified RX~2 driver
should not be used in 18-bit LSI-II or UNIBUS system, nor a
22-bit UNIBUS system.

~DmUDmD
MICROCC)MPUTER
PROI)UCTS
GRC)UP

j../note

NUMBER
PAGE

112

The correction file below for DYDRV.MAC is for. the
distribution (V4.9 master) version of the file. It does not
include any other driver corrections.
You can easily
integrate this correction with any another correction(s) for
DYD1RV. MAC.
Although this information is prol~ided by DIGITAL, it is not
authored by the RSX-llM developm1ent group, and therefore is
not officially supported by DIGITAL.
Steps to Include an IS-bit RXV21 Controller
Into a 22-bit LSI-II RSX-llM V4.e system
1.

Create the following SLP correction file for DYDRV.MAC
arid modify the driver source using the procedure
outlined in the first paragraph (and example) of Section
5.2.1 (page 46) of the RSX-llM V4.S Release Notes.

DYDRV.MAC;2/AU:72./-BF=[11,le]DYDRV.MAC;1/CS:62S64
\

-2,.

.IDENT
-IS,.
; V:ERSION 92.l6X
-76

/S2.l6X/

;

;
;

B. ALIMONTI
l4-SEP-S2
BAl6S--MODIFY FOR IS BIT DY CONTROLLER ON 22 BIT SYSTEM

-3S8,3l5,/;BA16S/
.IF DF M$$EIS
MOV
ASH
BIC
MOV

U.BUF(R5) ,Re
'4,RS
''''C(3SSSS>,Re
RS,U.BUF(RS)

;
;
;
;

MOV ADR EXTENSION BITS TO RS
MOV ADR BITS 16 AND 17 INTO POS
ISOLATE ADR BITS.16 AND 17
REPLACE BACK IN U.BUF

.IFF
.REPT 4
ASL
U.BUF(R5)
.,ENDR

; MOV ADR BITS 16 AND 17 INTO POS

~DmDDmD
MICROC~OMPUTER

PROIDUaS
C;R~OUP

),Inote
SIC

,AC<38888>,U.BUF(RS)

NUMBER
PAGE

; ISOLATE ADR BITS 16 AND 17

.ENDC ;M$$EIS
-343,353,/;BA168/
;

/
2.

If you have already perfornned a SYSGEN and your RX82
driver is loadable, follow the procedure outlined in
section 5.1.2 of the Release Notes for loadable drivers
(page 47) to reassemble and rebuild the driver.
Do not
yet VMR the system as indi4cated in the Release Notes
(but instead go to step 4 below).

Perform a SYSGEN if: 1) you have not yet done so, or 2)
you have performed a SYSGEN but the RX82 driver is
resident.
Use the modified driver source to do the
SYSGEN.

Create a new system image as follows:
a)

Set the UIC to [1,54] wi t~h the command
SET /UIC=[1,54]

Edit SYSVMR.CMD to establish a partition, l8BIT, in
the first 256KB of memory for those tasks that
perform I/O to the RX92.
You do this by first
locating the line
SET /MAIN=FCPPAR:*:fcplen:SYS
and the adding the line
SET /MAIN=18BIT:*:18bitlen:SYS
following it , where fcplen is the length of
partition FCPPAR, and 18bitlen is the length of
partition lSBIT (as long as partition l~BIT is
contained totally within the first 256KB).

112
3 OF 4

NUMBER
PAGE

Create a new system image file with the command
PIP RSXIIM. SYS/NV/CO/~L: ~'98 .=RSXIIM. TSK

VMR the system as follow!1
VMR @SYSVMR.CMD

Install those tasks that pe'rform I/O to the RX92 into
partition 18BIT.
This is done either with VMR or MCR.
For example
INS PIP/PAR-18BIT

~DmnDmD
MICROCC)MPUTER
PROI)UaS
GRC)UP

112

).Inote
TITl.E

BLOCK MODE Dl-1A

NUMBER
113

DATE
6

DISrRIBUTION

Unrestricted

ORIGINATOR

Mike Collins, Scott: Tincher

PRODUCT
PAGE

BLOCK MODE DMA
What i.s Block Mode DMA?
Block mode DMA is a method of data transfer which increases throughput
due to the reduced handshaking necess~ry over the Q-bus. In order to
implement Block mode DMA both the master and slave devices must
unders.tand the block mode protocol.
If ei ther device does not have
Block mode capability the transfers proceed via standard DATI or DATa
cycles; •
Conventional Direct Memory Access on the Q-bus.
Under conventional DMA operations, after a DMA device has become bus
master, it begins the data transfers. This is accomplished by gating
an address onto the bus followed by the data being transferred to or
from the memory device. If more than one transfer is performed by the
temporary bus master, the address portion of the cycle must be
repeated for each data transfer.
Block Mode Direct Memory Access on the Q-bus.
Under block mode DMA operations an address cycle is followed by
multiple word transfers to sequential addresses.
Therefore data
throughput is increased due to the elimination of the address portion
of each transfer after the initial transfer.
There are two types of block mode transfer, DATBI (input) and DATBO
(output) • An overview of what occurs during each type of block mode
transfer is outl ined in figures 1 (DATSI, block mode input) and 2
(DATSO, block mode output).
A detailed description of each type of transfer accompanies figures 1
and 2 as well as detailed timing diagrams.
In the foll6wing ~iscussion the signal prefix T(Trans~it) indicates a
bus driver input and the signal prefix R(Receive) indicates a bus
receiver output.

).Inote

NUMBER
113
PAGE 2 OF 15

DATBl Bus cycles
Before a block mode transfer can occur the DMA bus master device must
requt!st control of the bus.
This occurs under conventional Q-bus
prot()col.
o

BUS
'The bus master device requesits control of the bus by asserting
TI)MR.

Gl~NT

ACKNOWLEDGE BUS MASTERSHIP
The DMA bus master device asserts TSACK S nsec minimum after
receiving RDHGI, 9 nsec minimum after the negation of RSYNC and 0
nsec minimum after the negation of RRPLY.
The DMA bus master
device negates TDMR 0 nsec minimum after the assertion of TSACK.

TERMINATE GRANT SEQUENCE
'flhe bus arbitration logic in the CPU negates TDMGO 0 nsec minimum
after receiving RSACK. The bus arbitration logic will also negate
TDMGO if RDMR negates or if RSACK fails to assert within Ie usee
('no SACK timeout').

EXECUTE A BLOCK MODE DATSI TRANSFER

RI~OUEST

BUS CONTROL
The bus arbitration logic in the CPU asserts the DMA grant signal
TDMGO ~ nsec minimum after TDMR is received and ~ nsec minimum
after RSACK negates (if a DMA device was pr~vious bus master) •

ADDRESS DEVICE MEMORY
a) The address is asserted by the bus master on
TADDR<21:00> along with the negation of TWTBT.
b) The bus master asserts TSYNC 1Se nsec minimum after gating
the address onto the bus.

DECODE ADDRESS
The appropriate memory device recognizes that it must respond to
the address on the bus.

REQUEST DATA
a) The address is removed by the bus master from
lee nsec minimum after the assertion of TSYNC.

TADDR<21:~H'>

b) The bus master asserts the first TDIN 1ge nsec minimum after
asserting TSYNC.

).Inote
c)

NU.MBER 113
PAGE 3 OF 15

The bus master asserts 'raS7 50 nsec maximum after asserting
TDIN for the first time. TBS7 remains asserted until 50 nsec
maximum after the assertion of TDIN for the last time.
In
each case, TBS7 can be asserted or negated as soon as the
conditions for asserting TDIN are met.
The assertion of TBS7 indicates the bus master is requesting
another read cycle after the current read cycle.

DATA
a) The bus slave asserts TRl?LY 0 nsec minimum (8000 nsec maximum
to avoid a bus timeout) after receiving RDIN.

Sl~ND

b) The bus slave asserts TREF concurrent with TRPLY if, and only
if, it is a block mode device which can support another RDIN
after the current RDIN •.
NOTE
Block mode

must not cross 16
word b()undaries

transfer~

c) The bus-slave gates TDATA<15:00> onto the bus 0 nsec mlnlmum
after receiving RDIN and 125 nsec maximum after the assertion
of TRPLY.
o

TERMINATE INPUT TRANSFER
a) The bus master receives stable RDATA<15:00> from 20" nsec
maximum after receiving I~RPLY until 20 nsec minimum afte~ the
negation of RDIN.
(The 20 nsec minimum represents total
minimum
rece i ver, delays
for
RDIN
at
the slave
and
RDATA<15:00> at the master.)
b) The bus master negates TIDIN 200 nsec minimum after rece-IYing

RRPLY.
0

OPERATION COMPLETED
a) The bus slave negates
the negation of RDIN.
b)

,]~RPLY

0 nsec minimum after receiYing

If' RBS7 and TREF are both asserted when TRPLY negates, the
bus slave prepares for another DIN cycle.
RBS7 is stable
from 125 nsec after RD:tN is recei yed unti 1 ISS nsee after
TRPLY negates.

).Inote
c)

NUM'8ER

PAGE

113

If· TBS7 and RREF were b()th asserted when TDIN negated, the
bus master asserts TDIN lS~ nsec minimum after receiving the
negation of RRPLY and continues with timing relationship
'SEND DATA' above.
RREF is stable from 7S nsec after RRPLY
asserts until 2" nsec minlmum after TDIN negates. (The ~ nsec
minimum represents total minimum receiver delays for RDIN at
the slave and RREF at the master.)
NClte
The bus master must limit itself to not
more than eight transfers unless it
monitors RDMR.
If :It monitors RDMR, it
may perform up to 16 transfers as long as
RDMR is not asserted at the end of the
seventh transfer.

TERMINATE BUS CYCLE
a) If RBS7 and TREF were not: both asserted when TRPLY negated,
the bus slave removes TDATA(lS:""> from the bus" nsec
minimum and 1~9 nsec maximum after negating TRPLY.
b) If TBS7 and RREF were not both asserted when TDIN negated the
bus master negates TSYNC 2:59. nsec minimum after receiving the
last assertion of RRPLY an.d ~ nsec minimum after the neqa.tion
of that RRPLY.
.

RELEASE THE BUS
a) The DMA bus master negates TSACK
last RRPLY.
b)

The DMA bus master negatl!s TSYNC
negates TSACK.
.

nsec after negation of the
39~

nsec maximum af:teu it

c) The DMA bus master must remove RDATA(lS:~~>, TBS7, and TWTBT
from the bus l~0 nsec maximum after clearing TSYNC.
o

RESUME PROCESSOR OPERATION
The
bus
arbitration
logic
processqr-generated ,TSYNC or will
(TDMGO) if RDMR is asserted.

in
the
CPU
ef'lta.b:les
issue another bus ~rant

NUMBER 113
PAGE 5 OF 15

OAT B I

PROCESSOR

C '{ C t. E

I/O OEVIC!
Re~uest Bus
/ . s s e r t "fI5MR

Grant Bus Control
• Near end of the
current bus cycle
(RRPt.Y is negated)
assert TOMGO and
inhibit new
processor generated
TSYNC for the
duration of the OMA
operation
Acknowledge Bus
Mastershlf
• Receive ROMGO
• Wait for negation
of RSYNC and
RRPt.Y
• Assert TSACK
· Negate TOMR

Terminate Grant
Sequence
. Negate ROMGO and
wait for OMA operation
to be completed.

Execute a Block
Moae OM); ("O'Al'II)
bata Transfer

Address Device
Ae:or y
• ssert TAOOR(2l:00>
with address
• Assert TSYNC
• Negate TWTBT

~ Decode
Address
. Store -bevlce
Selected- operation

).Inote

OAT B I

C Y C t. E

NUMBER 113
PAGE 6 OF 15

CON T ' 0

I/O DEVICE

PROCESSOR

Dati
.emove the address
from TAooR<21:99>
· Assert ToIN
• Assert T857 (request for
an additional DIN cycle
after the current one)

Re~uest

(
I
I
i
i

~ Send Data
Piace data on
ToATA<15:99>
• Assert TRPt.y
• Assert TRtF
( indicates
block mode
capabi 11 ty)

I
I

Terminate Input
fransfer
• Accept data and
respond by negating
TOIN

Operation com~leted
• Negate tRPt:

i
yes
"'-----------<

Terminate Bus Cycle and
Release the Bus
• Negate fs)~
• Negate TSYNC
· Remove ToAt., T8S7, and,
TWTBT f ronl the Bus

Resume Processor
Operatlon
• Enable processorgenerated TSYNC
or issue another
grant if RoMR is
asserted

).Inote

NUMBER 113
PAGE 7 OF 15

T OI1R

R OI1C

T SACK

rlDt'l

:MX

T OIN

It RPL'i

R REF

'---------1r----, ~ n. ...
'_______

T BS7

~ ~ns~_ax

_ _ _ _ _ _ _ _ _ _ _ __ _

\\\\\\\\\\\\\\\\\\~

T W'I'BT

1'illlinq at lII&ster device.
l' • Bus driver input
R • bus receiver output

DATBI

).Inote

R/T OAL

II. ADOR

X\\\\~
12~ns

-----1\__

T DATA

)\\\\S\X

NUMBER 113
PAGE 8 OF 15

T DATA

lD~~'

)

max
II. SYNC

II.

OIN

T RPt.y

---'-----L

T REF

II. BS7

--------'

\ ' - -_ _ _ _ _ __

R\ofI'BT~~_A\\\\\\\\\\\\\\\\\\\\\\\\\\\~
Timinq
atdriver
slave input
device.
T
. Bus
Bus receiver output
II. •

DATB!

).Inote

NUMBER

113

PAGE 9 OF 15

DATBO Bus cycles
Before a block mode transfer can occur the DMA bus master device must
request control of the bus.
This occurs under conventional Q-bus
protocol.
o

REQUEST BUS
The bus master device requests control of the bus by asserting
TDMR.
GRANT BUS CONTROL
bus arbitration logic in the CPU asserts the DMA grant signal
TD~IGO ~ nsec minimum after RD~'R is received and. ~ nsec minimum
after TSACK negates (if a DMA device was previous bus master) •

'TFiE~

ACKNOWLEDGE BUS MASTERSHIP
'fhe DMA bus master device asserts TSACK ~ nsec minimum after
receiving RDMGI, ~ nsec minimum after the negation of RSYNC and ~
nsec minimum after the negation of RRPLY.
The DMA bus master
device negates TDMR ~ nsec minimum after the assertion of TSACK.
TERMINATE GRANT SEQUENCE

T'FiEt bus arbitration logic in the CPU negates TDMGO ~ nsec minimum
after receiving RSACK. The bus arbitration logic will also negate
TDMGO if RDMR negates or if RS}\CK fails to assert within 13 usec
('no SACK timeout').

EXECUTE A BLOCK MODE DATBO TRANSFER
o

ADDRESS DEVICE MEMORY
. a) The address is asserted by the bus master on
along with the assertion of TWTBT.
b)

The bus master asserts TSYNC
the address onto the bus.

DECODE ADDRESS
The
appropriate memory device
respond to the address on the bus.

15~

TADDR<21:~~>

nsec minimum after gating

recognizes

that

must

SEND DATA
"a) The bus master gates TDATA<15:a~> alon.g with TWTBT 1"" nsec
minimum after the assertion of TSYNC. TWTBT is negated.

).Jnote

NUMBER
PAGE

113
10 OF
15

b) The bus master asserts th,e first TDOUT l~~ nsec minimum after
gating TDATA<15:~e>.
NOTE
During DATBO cycles TBS7 is undefined
o

RE:CEIVE DATA
a) The bus slave receives Htable data on RDATA<15: ~g> from 25
nsec minimum before recedving RDOUT until 25 nsec minimum
after receiving the negation of RDOUT.
b)

The bus slave asserts TnPLY 9 nsec minimum after receiving
RDOUT.

c) The bus slave asserts TREF concurrent with TRPLY if, and only
if, it is a block mode device which ca~ support another RDOUT
after the current RDOUT.
NOTE
Blockmode transfers must not cross 16
word boundaries

TERMINATE OUTPUT TRANSFER
The bus master negates TDOUT 15f2J nsec minimum after receiving
RRPLY.

OPERATION COMPLETED
a) The bus slave negates TFtPLY 9 nsec minimum after receiving
the negation of RDOUT.
b) If RREF was asserted when TDOUT negated and 1-f the bus master
wants to transfer another word, the bus master gates the new
data on TDATA<15:9rtJ> lf2J9 nsec minimum after negating TDOUT.
RREF is stable from 75 nSt!C maximum after RRPLY asserts until
29 nsec minimum after RDIOUT negates.
(The 2rtJ nsec minimum
represents minimum receiver delays for RDOUT at the slave and
RREF at the master) •

NUMBER

113

PAGE 11 OF

The bus master asserts TD'OUT 100 nsec minimum after gating
new data on TDATA<15:a3> and 153 nsec minimum after receiving
the negation of RRPLY.
The cycle continues with the timing
relationship in 'RECEIVE DATA' above.
Note
The bus master must limit itself to not
more than eight transfers unless it
moni tors RDMR.
If i 11: moni tors RDMR, it
may perform up to 16 transfers as long as
RDMR is not asserted at the end of the
seventh transfer.

TERMINATE BUS CYCLE
a) If RREF was' not asserted when RRPLY negated or if the bus
master has no addi tional data to transfer, the bus master
removes data on TDATA<15::00> from the bus 100 nsec minimum
after negating TDOUT.
b)

If RREF was not asserted when TDOUT negated the bus master
negates TSYNC 275 nsec minimum after receiving the last
RRPLY and 0 nsec minimum after the the negation of the last
RRPLY.

RELEASE THE BUS
a) The DMA bus master negat:es TSACK 0 nsec after negation of
the last RRPLY.
b)

The DMA bus master negates TSYNC 300 nsec maximum after it
negates TSACK.
~

The DMA bus master must remove TDATA, TBS7, and TWTBT from
the bus 100 nsee maximum after clearing TSYNC.

RESUME PROCESSOR OPERATION
bus arbitration logic in the CPU enables processor- generated
TSYNC or will issue another bus grant (TDMGO) if RDMR is asserted.

).Inote

DATBC)

PROCESSOR

NUMBER

PAGE 12 OF

C Y C L E

MEMORY

I/O DEVICE:

Grant Bus Control
• Near the end of the
current bus cycle
(RRPLY is negated)
assert TDMGO and
inhibit new processor
generated TSYNC for
the duration of the
OMA operation.

Terminate Grant

Acknowledg'e Bus
Mastershlf!
• Rece! ve 'RDMG
• Wait for negation of
RSYNC and RRPLY
• Assert 'I'SACI(
• Negate ,!'DMR

se~uence

.egate TDMGO and
wait for DMA operation
to be completed.
Execute A Block Mode

OMA (OATBe) Data

Transfer

Address Membb~
• Assert fA
<21:00>
with Address
• Assert TWTBT
• Assert TSYNC

113

Decode Address
• Address ma Ech
selects device

).Inote

OAT B 0

PROCESSOR

C Y C [. E

NUMBER 113
PAGE 13 OF 15

CON T'D

MEMORY

I/O DEVICE
Send Data
o
Assert TDATA <15:00>
Negate TWTBT
Assert TOOUT
o
o

-----

Receive Oata
o
Accept data and
RWTBT
o
Assert TRP['Y
o
Assert TREF
(Indicates block
mode capability)

Terminate Output
Transfer
o
Negate TOOUT
operation Completed
Negate TRPt'x'
o

Terminate Bus Cycle and
Release the Bus
o
Negate 'f~
o
Negate 'T'SYNC
Remove 'T'O"[', TBS7, and TWTBT
from the Bus
o

Resume Processor
operation
o
Enable processorgenerated TSYNC
(Processor is bus
master) or issue
another grant if
ROMR is as.erted

).Inote

NUMBER

T OMR

R CHG

TOAL

T OOUT

R RPLY

------------~--~\~

R REF

T BS7

======~----~-----------t------~mm:::Er:l::N:ED:---------------------------------~~

T tl'l'BT

T1m.1n9 at lUster devic:e.
T • Bus driver input
R • Bus rec:eiver output

113

PAGE 14 OF

DATBO

).Jnote

It OAL

R SYNC:

X,-__ _---J;~'-__~ _.-A'-____

R ADOR

RDA_TA

--.II

_OAT_A

~- ~.

T REI'

R as'

R"WTBT

/
~

NUMBER 113
PAGE' IS OF
IS

\\.-\'--------\'----\'-----

UNDEP'INED

\~_ _ _ _ _ _ _ _ _ _ __

TimLn9 At slAve device.
T • au. driver input
R • au. receiver output

,. DATBO

NUMBER

).Inote
TITLE

114

Compatible Bootstrap for the LSI-1l/73

DISTRIBUTION

unrestricted

ORIGINATOR

Mike Collins

DATE
11

PRODUCT
LSI-11/73

PAGE 1 OF

The 11/73 (KDJ11-AA) is a high perfor.ance CPU for the QBus. It
is a CPU only, which .eans that thE~re is no boot capability on
the module itself. Therefore a boot Module .ust be selected to
work with the 11/73.
This uNOTE will discuss the bootstrap Modules which can be used
with 1the 11/73.
There are 4 possible .odules which can be used for bootstrap.
They are: MXV11-BF w/MXV11-B2 boot ROMs
MRV11-D w/MXV11-B2 boot ROMs
MXV11-AA or -AC w/MXV11-A2 boot ROMs
BDV11
For an 11/73 (KDJ11-AA) based system to be Field Serviceable the
bootstrap code Must execute a cache memory diagnostic on
power-up. The only boot code which satisfies this requirement is
found in the MXV11-B2 boot ROMs. Threfore an 11/73 based, Field
Serviceable system must use either the MXV11-BF w/MXV11-B2 ROMs
or the MRV11-D w/MXV11-B2 ROMs.
NOTE:

The MXV11-B2 ROMs will not work on the MXV11-A
module.

MXV11-BF or MRV11-D w/MXV11-B2 ROMs
The MXV11-BF w/MXV11-B2 ROMs is the preferred choice since
this .odule has 2 asynchronous serial lines as well as 128Kb
of dynamic RAM in addition to the boot capability. However,
if your application does not need the extra serial lines and
I~AM, an alternate choice would be ,the MRV11-D w/MXV11-B2
f~ OM s •

~D~DD~D
MICROCOMlPUTER
PRODU~CTS

GROUP

),Inote

NUMBER
PAGE

J.14

The MXV11-B2 ROMs will boot the following devices:
RL01/RL02 (DL)
RX01/RX02 (DX,DY)
TU58 (DD) .
TSV05 (MS)
MSCP type devices e.g. RD51, RX50 (DU)
DECnet via DPV11, DLY11-E, DLV11-F, DUV11
The remaining 2 boot .odules do NOT have the necessary cache
.emory diagnostic code to .ake an 11/73 based syste. Field
Serviceable.
.
is a list of all of the TESTED bootstraps for the 2
remaining boot .odules.

Belo~

MXV11-A w/MXV11-A2 ROMs.
Working Bootstraps:
RL01/RL02
RX01/RX02
TU58 conventional boot
TU58 standalone boot
WARNING:

If the MXV11-A is used in a 22 bit system the
on-board RAM .ust be disabled. Refer to uNOTE
#106

BDV11
Working Boostraps:
RL01/RL02
RX02
RKOS
WARNING:

Disable the processor and memory tests since an
odd address trap does occur in each of them. (See
NOTE below). To disable the CPU test, set switch
E15-1 to OFF. To disable the memory test set
switch E1S-2 to OFF. Refer to the Microcomputer
and Interfaces Handbook for complete configuration
information.

mDmDomD

MICROCO'''PUTER
PRODIJJCTS
CROIIP

NUMBER
PAGE

114
3 OF 3

The 11/73 has an on-board Line Ti.e Clock
Register, therefore the BDY11 BEYNT switch E21-S
should be set to the OFF postion. This disables
the BDY11 LTC reg. and allows the BEYNT signal to
be under S/W control of the 11/73 LTC Reg.
If the BDY11 is used in a 22 bit system, it Must
be CS REV E or later or ECO M8012-MLOOOS .ust be
installed.
NOTE:

ODD ADDRESS TRAPS. The 11/23 ignores an odd
address reference whereas the KDJ11-A will trap to
4.

~D~DDmD
MICROCO'''PUTER
PROD~JCTS

CiROIJP

)Jnote
LSI-11/73 Upgrade Paths

TITLE
DISTIRIBUTION

Unrestricted

ORIGINATOR

Mike Collins

NUMBER
115

DATE
11

28 /

PRODUCT
LSI-ll/73

PAGE 1

LSI-11/73 UPGRADE PATHS

With the announcement of the 11/73 (KDJ11-AA) CPU .odule, there
will be nUMerous questions regarding configuring the Module into
a current system. The purpose of this uNOTE is to address all
possible configuration upgrade paths (within reason).
Generally an 11/73 will be installed as an upgrade to a system
built from components or a DEC packaged system.
In the case of a compon~nt upgrade it is assumed that the
processor is a KDF11-A and the boot mechanism is an MXV11-A with
the MXV11-A2 boot ROMs.
System upgrades fall into two categories:
1. KDF11-A Based Systems and
2. KDF11-B Based Systems (11/23+ and uPDP-11)
There are three issues which Must be addressed when considering a
KDJ11-A upgrade. They are:
1.
The Boot Mechanism
2. 18 or 22 Bit System
3. Single or Multiple Box System
NOTE:
1.

In the following upgrade scenarios, the systems have been
Labeled as being Field Serviceable or not. A system which
is Field Serviceable has a bootstrap which meets Field
Service requirements. The requirement is th.t the bootstrap
must execute an 11/73 cache .emory diagnostic on power-up.
~tef~rence uNOTE entitled "Compatible Bootstraps for the
l.SI-11/73". There is no guarantee that the overall system
will be Field Serviceable or that it will be FCC compliant.

mD~DD~D
MICROCO,.'PUTER
PRODUCTS
GROUP

j./note

NUMBER
PAGE 2

SysteMs using CPUs other than the KDF11-A or KDF11-B (i.e.
systeMs) are not considered for upgrade.

11/03

CAUTION:
It is recolI.ended that the AC and DC loading for the final
configuration be checked for confor.ance with the Q-bus loading
rules. It is also reco.mended to check for overloading on the +5
Volt and +12 Volt Power Supplies.
For each s y stell upg rade-t«he d-fo II ow; ng"pa ra'lIete rs are listed for
both the "Current" system and the "Upgraded" system:
CPU
1•
2. Boot Mechanism
3. System Size
4. Number of Boxes
5. Field Serviceable or Not
6. Special Conditions
COMPONENT UPGRADE PATHS:
1•

Current System
KDF11-A
MXV11-A
18 Bit System
1 Box

Upgrade 1
KDJ11-A
MXV11-B/MRV11-D with MXV11-B2
Boot ROMs
18 Bit System
1 Box
Field Serviceable
Upgrade 2
KDJ11-A
MXV11-A
18 Bit System
1 Box
,
NOT Field Serviceable

~D~DDmD
MICROCOMPUTER
PRODIUCTS
CROUP

115
7

°).lnote

NUMBER
PAGE

3 OF

Current SysteM
KDF11-A
MXV11-A
18 Bit SysteM
More than 1 Box

Upgrade
See Upgrades for '1

Current System
KDF11-A
MXV11-A (MeMory Disabled)
22 Bit System
1 Box

Upgrade
See Upgrades for .1

Current System
Upgrade
KDF11-A
Not currently configurable with
MXV11-A (Memory Disabled)
DEC equipment
22 Bit System
More than 1 Box
This system is not currently configurable with DEC equipMent

PDP 11/23A SYSTEM UPGRADE PATHS:
5.

Current System
KDF11-A
BDV11
18 Bit System
1 Box

115

Upgrade 1
KDJ11-A
MXV11-B/MRV11-D with MXV11-B2
Boot ROMs
18 Bit System
1 Box
Field Serviceable
Upgrade 2
KDJ11-A
BDV11
18 Bit System
1 Box
NOT Field Serviceable
Disable the Processor and
Memory tests and also the eEVNT
register on the BDV11.

J.,Inc)te

NUMBER
PAGE 4

Upgrade 3
KDJ11-A
MXV11-A (with MXV11-A2 boot
ROMs)
18 Bit System
1 Box System
NOT Field Serviceable
Check AC loading since
terMination was re.oved when
the BDV11 was re.oved fro. the
systeM.
6.

Current System
KDF11-A
BDV11
18 Bit System
More than 1 Box

Upgrade 1
KDJ11-A
MXV11-B/MRV11-D with MXV11-B2
Boot ROMs
18 Bit System
More than 1 Box
, Field Serviceable
Use BCV1A and BCV1B expansion
cables.
Upgrade 2
KDJ11-A
BDV11
18 Bit System
More than 1 Box
NOT Field Serviceable
Disable the Processor and
Memory tests and also the BEVNT
register on the BDV11.
Use BCV1B cable set between
1st and 2nd box and the BCV1A
cable set between the 2nd and
3rd box.
NOTE: If in a 3 ~ox system the
expansion cable set lengths
must differ by 4 ft.

~DmDI~mD
MICROCOJMPUTER

PRODIJCTS
CROIUP

115
7

).Inote

NUMBER
PAGE

Upgrade 3
KDJ11-A
NXV11-A (with MXV11-A2 boot
ROMs)
18 Bit System
More than 1 Box
NOT Field Serviceable
Use BCV1A and BCV1B expansion
cables.
7.

Current System
KDF11-A
BDV11
22 Bit System
1 Box
Systems with this configuration were never shipped by DEC.

PDP 11/23 PLUS SYSTEM UPGRADE PATHS:
8.

Current System
KDF11-B
Boot is on CPU
22 Bit System
1 Box System

Upgrade 1
KDJ11-A
MXV11-B/MRV11-D with MXV11-B2
boot ROMs
22 Bit System
1 Box
Field Serviceable
,Ups rade 2
KDJ11-A
MXV11-A (with MXV11-A2 boot
ROMs)
22 Bit System
1 Box
NOT Field Serviceable
Must Disable RAM on MXV11-A

mD~DDmD
MICROCOJMPUTER
PRODllJCTS
CiROIUP

115
5 OF 7

),Inote

NUMBER
PAGE 6

Upgrade 3
KDJ11-A
BDY11
22 Bit System
1 Box SysteM
NOT Field Serviceable
Must have BDV11 Eca M8012-ML005
installed.
Disable the Processor and
Me.ory tests and also the BEYNT
reg~s~er on the BDY11.
9.

Current System
KDF11-B
Boot is on CPU
22 Bit System
More than 1 Box

Upgrade 1
Not currently configurable with
DEC equipMent.

NICRO PDP-11 SYSTEM UPGRADE

PATHS~

10.

Current SysteM
Micro PDP-11
KDF11-BE
Boot is on CPU
22 Bit System
1 Box System

Upgrade
.
Same as 11/23+ rules, see
upgrades for 118

11.

Current System
Micro PDP-11
KDF11-BE
Boot is on CPU
22 Bit System
More than 1 Box

Upgrade
Same as 11/23+ rules, see
upgrades for 119

NOTE:

It is not currently possible to expand out of the uPDP-11
while Maintaining FCC co.pliance.
11/23 PLUS and uPDP-11 systeM upgrades will require an
EXTRA backplane slot to accomodate the additional boot
module (i.e. MXV11-X or BDV11).

~D~Dlm~D
MICROCO~r.tPUTER

PRODIJCTS
CiROllJP

115

).Inote

NUMBER
PAGE 7

The KDF11-BA and KDF11-BE (CPUs for 11/23+ and uPDP-11)
have two asynchronous serial lines in addition to the CPU
and Boot ROMs. When the 11113 is substituted for these
CPUs the two serial lines .ust be replaced. Since the
MXV11-BF has two serial lines it is the preferred choice.

11/23-S SYSTEM UPGRADE SOLUTIONS:

12.

Current System
KDF11-BA
Boot is on CPU
18 Bit System
1 Box system

Upgrade
See upgrades for '5

13.

Current System
KDF11-BA
Boot is on CPU
18 Bit System
More than 1 Box

Upgrade
See upgrades for '6

NOTE:

It is not currently possible to expand out of the 11/23-S
while maintaining FCC compliance.

~D~DDmD
MICROCOj~PUTER

PRODIJCTS
CiROI~P

115

,..............-............

--~.--

----.---.-. --'---..

..--'''"'''''.-" ..........

.....

.., --.~~~

NUMBER

)Jnote

Expanding into a

TITLE

B~~-SA

DISTRIBUTION

Restricted

ORIGINATOR

Peter Kent

R12

DATE
Box :al

/ 10 /

PRODUCT
BAll-SA

PAGE
I

_
~

Because of the availability of one type of box - specifically the BAll-SA it might
be desirable to be able to expand from one BAll-SA box to another BAll-SA box.
This
particular arrangement was tested with one configuration to determine the workabilit~
of both boxes.
~ ~
- . :.-

, ...

\..

The mas1~er box contained the following:
module cmd cable).

KDFll-B, MSVll-P, DZVll, and M940l (expansion

The expclnsi on BAll-SA cOTltained M9400-YE
(REVll tE:l-minator board), and RLV12.

(t~Xf,ansion

module and cable),

M~400-YB

Both expansion modules were convertec to 22 bit by using the 4 ground lines Fffi,
KK, MM., and PP on Jl.
This was accomp] ishE~d t ! desoldering JI and cutting the etch
foil (rE!fer to drawing) under Jl for t~ose foi..::: pins.
Four wires were then added
to those pins and connected tc~ the unused fin~=-!:'s Bel, BDl, BD1, BEl, BFI. Fffi was
con.fleeted t,o BCI, KK to BDl, MM to BEl, and po: SFI. There are 2 potential problems
wi th this a,rrangement:
1)

,By using 4 of the ground leads, somE of the noise suppression may

compromised because normally every c-__~er wire on the cables are alternated
with ground wires - here 4 B:>AL lines are interspersed with other signal
lines;
Some of the newer modules do not ha'\P<'" any spare gold fingers.

The four BDAL lines

(18-21) were not termir . at.:d on the REV 11 board.

spare re~istors on the :REV11
have to be wired to the four
be done by wiring pins 2 and
AAI and ABl and wiring these

There are
resistor DIP fo:: ":.errnir.ation.
These tenninations would
spare gold fingE::'!"s BCI, BDI, BEl, and BFl. This could
3 on E6 to BCl
BDl and cutting the etches going to
to BEl and BF1.

a-=

If a KDF11-A processor board is used, the fi1:,,~ backplane must have an additional
240 ohm termination so that the total lumpe·d lackplane impedance is 120 ohm.
An
M940C-YE expansion module has the necessary t:~:nnination on i t and could be used
in this case.
The jumper WI on the H9276-B backplane (line time clock) was removed as well as the
cable to JI on the Bezel control card (to cli~..able front f-a..'F).el switch functions) for
expanslon BAll-SA box.

~D~DDmD
MICROCOMPUTER
PROD!UCTS
CROUP

).Inote

NUMBER
PAGE

2 OF 2

The system was successfully booted wi th R~r-ll version 4.0 and some fW1ctions
were eJcercised, such as the clock, the editor, directory, and typed without
difficulty.
This te!st of the above mentioned arrangement was by no means all inclusive and
could not possibly attempt to cover all posslble configurations in both backplanes.

~!D~DD"D
~ ~
~
..

MICROCOMPUTER
PRODllJCTS
GROUP

o,- -

0"-

You are looking at side 2
(solder side).

t 3012

®qIH:> qlJ,

make cut here

\
·

• tl.

- - -".

I
FIGURE 1

....-------...