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XX-EF0CA-F9

May 1986

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Original

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Document:	KXJ11-CA prelimUG 1986
Order Number:	XX-EF0CA-F9
Revision:
Pages:	236
Original Filename:	http://bitsavers.org/pdf/dec/qbus/KXJ11-CA_prelimUG_1986.pdf

OCR Text

KXJ11-CA User's Guide
preliminary version 1.3

Copyright (C) 1986 by Digital Equipment Corporation
The information in this document is subject to change without notice
and should not be construed as a commitment by Digital Equipment
Corporation. Digital Equipment Corporation assumes no responsibility
for any errors that may occur in this document.

CONTENTS

CHAPTER 1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.2.1
1.5
1.6
1.7
1.8
CHAPTER 2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2.2.10
2.2.11
2.2.12
2.2.13
2.2.14
2.2.15
2.3
2.4
2.4.1
2.5
2.5.1
2.5.2
2.5.3
2.6
2.7
CHAPTER 3
3.1
3.2
3.2.1
3.2.2

OVERVIEW
INTRODUCTION
••••.•••
KXJ11-CA HARDWARE FEATURES . .
. . . ..
OPERATIONAL OV~RVIEW ( ••••• ) •
· . .
KXJ11-CA OPERA~ING MODES
Standalone Mode
. . . .
lOP Mode
••••.•
. . . . . . . . .
KXJ11-CA Fro~ Point Of View Of Arbiter..
SOFTWARE ENVIRdNMENT . • · . . .
. . ..
KXJII-CA SPECIFICATIONS · . . .
. . .
TERMINOLOGY US~D IN THIS DOCUMENT • • • • • .
RELATED DOCUMENTS
· . . . .

• 1-1

. 1-1

.
•
. .
. .
.
.

1- 3
1-3
1-3
1- 4
1-4

1 ... 4
. 1-4
1-5
1-6

INSTALLATION
INTRODUCTION • '. • • • • • • •
• • • •
SELECTING OPERATING FEATURES
...•
. .
Boot/Self test-Switch
••••
• • • • •
Q-Bus Size
• • • . •
.
Q-Bus Base Address Selection
. . . . . .
DMA Requests
•••••.
BREAK Enable • • • • • . • • . • . • • • •
HALT Option Selection
Power-Up Option Selection
PROM Addressing • • • • •
SLU1 Baud Rate . . . . . .
SLU1 Transmitter . . . . .
SLU1 Receiver
. . . . . . .
. • . •
SLU2 Channel A Receiver . • • • . . • • • • .
SLU2 Channel e Transmitter
.••••••••
SLU2 Channel e Receiver
. • • .
Real-Time Cloqk Interrupt
POWER SUPPLY CONSIDERATIONS . . . . . • · • . •
INSTALLING THE ~XJ11-CA INTO A BACKPLANE
Edge Connecto~ Pin Assignments
• • • .
. • • • ••
CONNECTORS AND EXTERNAL CABLING
Parallel I/O Interface (J4)
· . . • .
Serial I/O Lines (J1, J2, J3)
Loopback Connectors . • . . . . . . • .
ERROR DETECTION ;AND REPORTING WITH THE LEDS
DIAGNOSTIC TES~tNG WITH XXDP+

• 2-1
• 2-1
• 2-- 4

• 2-8
. 2-9
2-11
2-12
2-13
2-14
2-15
2-16
2-17'
2-18
2-19
2-20
2-23
-2-24
2-25
2-26
2-27
2-30
2-30
2-31
2-37
2-38
2-39

ARCHITECTURE
INTRODUCTION
.••....••••. ·
KXJ11-CA BLOCK DIAGRAM
J-11 Microprocessor . • . . • • • • ·
·
RAM
• • • • • • '. •

.
•
.
.

. . 3-1
. . 3-1
. . 3-2
. . 3- 2

Page 2
3.2.3
Two Port Register (TPR) File
••••••
3 •2 •3•1
TPRO
• ~ • • • • • • • • • • ••
••
3.2.3.1.1 TPRO As A Control Register
•••••••••
3.2.3.1.2 TPRO As A Test Register • • • • • • • • • • •
3.2.3.1.3 TPRO As A Q-Sus OOT Register
••••••••
3•2•3•2
TPRl
••••••••••••••••
• •
3•2•3•3
TPR2
••••••••••••
• • • • • •
3•2•3• 4
TPR3
••••••••••••••
co.
•
•
3.2.3.5
TPR4 Through TPR15
•••••••••
0"
3.2.4
CPU 10 Switch • • • • • • • • • • • • • • • •
3.2.5
DNA Controller
•••••••••••••••
3.2.6
Wake-up Circuit • • • • • • • • • • • • • • •
3.2.7
PROM And Firmware Control • • • • • • • • • •
3.2.7.1
Native F~rmware Vs. User-Designed Firmware
3.2.8
KXJll-CA Control And Status Registers • • • •
3.2.8.1
KXJll Control/Status Register A (KXJCSRA) ••
3.2.8.2
KXJ11 Control/Status Register B (KXJCSRB) ••
3.2.8.3
KXJll Contr~l/Status_ Register C (KXJCSRC) ••
3.2.8.4
KXJ11 Control/Status Register D (KXJCSRD) ••
3.2.8.5
KXJ11 Control/Status Register E (KXJCSRE) ••
3.2.8.6
KXJl1 Control/Status Register F (KXJCSRF) ••
3.2.8.7
KXJ11 Control/Status Register H (KXJCSRH) ••
3.2.8.8
KXJ11 Control/Status Register J. (KXJCSRJ) ••
3.2.9
Q-Sus Interrupt Register (QIR) • • • • • • • •
3.2.10
Maintenance Register
••••••••••••
3.2.11
Program Interrupt Request (PIRQ) Register ••
3.2.12
CPU Error Register
•••••••••••••
3.2.13
Processor Status Word (PSW) • • • • • • • • •
3.2.14
Console Asynchronous Serial I/O • • •
• •
3.2.15
Synchronous/Asynchronous Serial I/O
•••
3.2.16
Parallel I/O
••••••••••••••••
3.2.17
-12V Charge Pump
••••••••••
• •
3.3
Q-BUS INTERFACE • • • • • • • • • • • • • • • •
3.4
TWO-PORT REGISTERS AND COMMUNICATION WITH THE
ARB ITER • . • • • • • • ., • . • • • • • • • • •
KXJ11-CA INTERRUPTS • • • • • • • • • • • • • •
3.5
3.5.1 ~ Interrupts From The Q-Bus To The KXJl1-CA • •
Interrupts From The KXJl1-CA To The Q-Bus • •
3.5.2
Local Interrupts From On-Board Devices
•••
3.5.3
SPECIAL INTERRUPT HANDLING
....,......
3.6
KXJ11-CA RESETS • • • • • • ••
• • • • • •
3.1
Software Reset • • • • • . • • • • • • • • • • •
3.7.1
Hardware Reset • • • • • • • • • • • • • • • •
3.7.2
MEMORY MANAGEMENT ARCH I TECTURE • • • • • • • • •
3.8
Page Address Registers (PARs) ••
• • • •
3.8.1
Page Descriptor Registers (PDRs)
••••••
3.8.2
Memory Management Register 0 (MMRO)
••••
3.8.3
Memory Management Register 1 (MMR1)
co
•
.,.
3.8 .. 4
Memory Management Register 2 (MMR2)
., •
3.8.5
Memory Management Register 3 (MMR3)
••••
3.8.6
SHARED MEMORY
• • • • • • • • • • ••
•••
3.9
Shared Memory Organization
•••• •••••
3.9.1
Defining One Block Of Shared Memory
• • •
3.9.2
Defining Two Blocks Of Shared Memory
• •
3.9.3
Defining 64 Blocks Of Shared Memory • • • • •
3.9.4

• 3-3
• 3-3
• 3-4
• 3-6
3-10
3-11
3-13
3-13
3-14
3-14
3-14
3-15
3-15
3-17
3-17
3-18
3-19
3-21
3-21
3-24
3-24
3-25
3-26
3-28
3-28
3-29
3-30
3-31
3-32
3-33
3-33
3-33
3-33
3-34
3-34
3-35
3-35
3-36
3-37
3-38
3-38
3-39
3-41
3-41
3-42
3-43
3-44
3-45
3-45
3-46
3-47
3-47
3-48
3-50

Page 3
3.9.5
3.9.6

CHAPTER 4

Enabling And D'isabling Shared Memory
Shared Memory Considerations
••••

. . .. .. 3-50
3-52

DNA TRANSFER CONTROLLER (DTC)

4.1
OVERVI EW • • • • • • • • • • • • • • • • • • • • • 4- i
4.2
DTC CONSIDERATIONS • • • • • • • • • • • • • • • • 4-2
4.3
DATA TRANSFER CONTROLLER (DTC) REGISTERS
• • • • 4-2
4.3.1
DTC Global Registers
• • • • • • • • • • • • • 4-4
4.3.1.1
Command Register
• • • • • • • • • • • • • • • 4-4
4.3.1.2
Master Mode Register
••••••
• • • • • 4-6
4.3.2
DTC Channel ~e9isters • • • • . • •
• • • 4-7
4.3.2.1
Current Address Registers A And B • • • • • •• 4-7
4.3.2.2
Base Address Registers A And B
• • • • • • • • 4-9
4.3.2.3
Chain Address Register • • • • • • • • • • • • • 4-9
4.3.2.4
Interrupt Vector And Interrupt Save Register
4-10
4.3.2.5
Status Register • • • • • • • • • • • • • • • 4-12
4.3.2.6
Current And Base Operation Count Registers
4-14
4.3.2.7
Pattern And Mask Registers
• • • • • 4-14
4.3.2.8
Channel Mode Register • • • • • • • •
4-15
4.4
PROGRAMMING THE DTC • • • • • • • • • • • • • • 4-18
4.4.1
Chip Initialization • • • • • • • • • • • • • 4-18
4.4.2
Data Transfer • • • • • • • • • • • • • • •• 4-21
4.4.3
Termination Options • • • • • • • • •
4-22
4.4.4
Examples • • • • • • • • • • • • • • • • • •• 4-22

\..riAPTER 5

PARALLEL I/O CONTROLLER (PIO)

5.1
OVERVIEW
• • • • • • • • • • • • • • • • • • • • 5-1
5.2
PARALLEL I/O PORT (PIa) REGISTERS • • • • • • • • 5-2
5.2.1
Master Control Registers
• • • • • • • • • • • 5-4
Master Interrupt Control Register • • • • • • • 5-4
5.2.1.1
Master Configutation Control Register • • • • • 5-5
5.2.1.2
Port Specification Registers
• • • • • • • • • 5-7
5.2.2
Port Mode Specification Registers (Ports A And
!5.2.2.1
B) • • • • • • • • • • • • • • • • • • • • • • • 5-7
Port Handshake Specification Registers (Ports A
!5.2.2.2
And B) • • • • • • • • • • • • • • • • • • • • • 5-9
Port Command And Status Registers (Ports A And
5.2.2.3
B) • • • • • • • • • • • • • • • • •
5-11
Bit Path" Definition Registers • • •
5-12
5.i:3
Data Path Polarity Registers
••
•• 5-13
~).2.3.1
Data Direction Registers
•••••
5-13
5.2.3.2
Special I/O.Control Registers • • • •
5-14
5.2.3.3
Pattern Definition Registers
••••
5-15
5.2.4
Pattern Polarity Registers (PPR)
• • •• 5-15
5.2.4.1
Pattern Transition Registers (PTR)
•••
5-16
5.2.4.2
Pattern Mask Registers (PMR)
••••••
5-16
5.2.4.3
Port Data Registers • ...-. • • • • • •
5-16
~;.2.5
PIO Counter/Timer Control Registers . • • • • • 5-17
~;.2.6
PIa Counter/Timer Mode Specification
5-17
5.2.6.1
"'PIa Counter/Timer Command And Status
• • • • 5-19
5.2.6".2
PIa Counter/Timer Time Constant • • •
5-21
5.2.6.3

Page 4
5.2.6.4
PIO Counter/Timer Current Count • • • •
5.2.7
Interrupt Related Registers • • • • • •
5.2.7.1
Interrupt Vector Register •• • • • • •
5.2.7.2
Current Vector Register • • • • • • • •
5.2.8
I/O Buffer Control Register • • • • • •
5.3
PROGRAMMING THE I/O PORTS • • • • • • • •
5.3.1
Programming The I/O Ports As Bit Ports •
5.3.2
Programming The I/O Ports As Ports With
Handshake • • • • • • •
5.3.2.1
Example •• • • • • • • • • • • • • • •
5.3.2.2
Example • • • • ••
• • • • • • • •
5.3.2.3
Example
• ••
• • • • • • • • •
5.3.2.4
Example •• • • •
• • • • • • • •
5.3.2.5
Example • • • •
• • • • • •
5.3.2.6
Example • • • • • • • • • • • • • • • •
5.3.3
PROGRAMMING THE PIO COUNTER/TIMERS • • •
0

CHAPTER 6

•

•
•
•
•
•
•
•

••••

•
•
•
•

•
•
•
•
•
•
•
•

•
•
•
•

•

• • •

5-21
5-22
5-22
5-23
5-23
5-24
5-25

5-27
5-33
5-36
5-38
5-40
5-41
5-43
5-44

SERIAL LINE UNITS (SLUS)

6.1
OVERVIEW • • • • • • . • • • • • • • • • • • • • • 6-1
6.2
CONSOLE SERIAL PORT (SLUl)
• • • • • • • • • • • 6-1
6.2.1
SLU1 (Console) Reg isters
...........~ 6-2
Receiver Control/Status Register (ReSR) • • • • 6-2
6.2.1.1
6.2.1.2
Receiver Buffer Register (RBUP) • • • • • • • • 6-3
Transmitter Control/Status Register (XCSR) • • • 6-4
6.2.1.3
6.2.1.4
Transmitter Buffer Register (XBUP)
• • • • • • 6-5
6.2.2
Examples • • • • • • • • • • • • • • • • • • • • 6-6
MULTIPROTOCOL SERIAL CONTROLLER (SLU2) • • • • •• 6-6
6.3
Synchronous/Asynchronous Serial Line (SLU2)
6.3.1
Registers • • • • • • • • • • • • • • • • • • • 6-7
KXJ11 Control/Status Register A (KXJCSRA) • • • 6-8
6.3.1.1
6.3.1.2
Time r Reg is t e r s • • • • • • • • • • • • • • .• • 6 - 9
6.3.1.2.1 SLU2 Timer Control Registers
• •
6-10
6.3.1.2.2 SLU2 Timer Data Registers ••
• • • • • • 6-12
. 6.3.1.3
SLU2 Control Registers
•••
• • • • e . 6-14
6.3.1.3.1 Control Register 0
• • • • • • • • • • • • • 6-14
6.3.1.3.2 Control Register 1
•••••
• •
6-17
6.3.1.3.3 Control Register 2 - Channel A
• • • • • • • 6-19
6.3.1.3.4 Control Register 2 - Channel B
•••••
6-20
6.3.1.3.5 Control Register 3 • • • • • • • • • • • • • • 6-21
6.3.1.3.6 Control Register 4 • • • • • • • • • • • • • • 6-23·
6-25
6.3.1.3.7 Control Register 5 • • • • • • • • • •
6-26
6.3.1.3.8 Control Register 6 • • • • • • • • • • • •
••
6-26
6.3.1.3.9 Control Register 7 • • • • • • • •
SLU2 Status Registers • • • •
• • • • 6-27
6.3.i.4
• •
• • • • 6-27
6.3.1.4.1 Status Register 0
6.3.1.4.2 Status Register 1 • • • • • • • • • • • • • • 6-29
••
6-31
6.3.1.4.3 Status Register 2 (Channel B Only)
SLU2 Transmitter Registers
• • • • • • • • • 6-31
6.3.1.5
SLU2 Receiver Registers • • •
• • • • • • 6-32
6.3.1.6
Examples • • • • • • • • • ••
• • • • • • 6-32
6.3.2

Page 5
APPENDIX A
A.l
APPENDI:X B
B.l

MEMORY MAP SUMMARY
REGISTER SUMMARY

. . . . . . • • • • • • • • • • A-l

KXJll-CA/KXTll-CA DIFFERENCES
DIFFERENCES BETWEEN THE KXJll-CA AND THE KXT11-CA

B-1

CHAPTER 1
OVERVIEW

1 • 1.

I NTRODUCT I ON

The KXJll-CA (M7616) is an I/O processor based on
the
J-ll
microprocessor
chip.
It
is
a quad-height, extended length,
single-width module that executes the extended PDP-ll instruction set
(all
140
instructions
including
floating-point)
with memory.
management. The KXJ11-CA can operate as a Q-Bus slave device under
the direction of a Q-Bus arbiter processor or can act as a st.andalone
processor.

The KXJll-CA meets the spec~fication for a Q-Bus slave and Q-Bus DNA
master and can interface w~th most of Digital's large family of Q-Bus
modules described in the Mic;rocomputer Interfaces Handbook and the
Microcomputers and Memories Handbook.

1.2

KXJ11-CA HARDWARE FEATURES

The KXJ11-CA has the following features:
0-.

J-l1 (DCJ1l-AC) l6-bi t microprocessor
Executes extended PDP-ll instruction
including floating-point).

set

(140

Contains memory management unit for
protection and 4 MBaddressing.

three

levels

instructions
of

memory

Operates at 14 MHz.
o

Memory
512 KB of dynamic RAM
Can be accessed by local (on-board) devices and Q-Bus devices

1-1

KXJll-CA User's Guide
OVERVIEW

PRELIMINARY

4/3/86

Up to 64 KB of PROM; 16 KS of whichris for firmware
o

Q-Bus interface
16 word, two-ported RAM
commands and parameters.

(TPR)

file

for

passing

Performs transfers between local 22-bit addresses and
18-bit, or 22-bit Q-Bus addresses.

I6-bit,

Mechanism for posting interrupts to the Q-Bus.
o

Two channel pt:ogrammable DMA transfer controller (DTC)

Eight control/status registers

Console asynchronous serial line
DL-compatible
-

'EIA RS-422/RS-423/RS-232C compatible
Programmable baud rates of 300 to 38400

Primary synchronous/asynchronous serial line unit
Full modem support
EIA RS-449 (CCITT V.24) and RS-422/RS-423/RS-232C compatible
Programmable baud rates of 110 to 76800
Bit-oriented
support

character-oriented

synchronous

protocol

Secondary synchronous/asynchronous serial line unit
RS-449 <CCITT V.24) data and timing only
RS-422/RS-423/RS-232C compatible
Programmable baud rates of 110 to 76800
Bit-oriented
support

character-oriented

Party line operation

1-2

synchronous

protocol

KXJll-CA User's Guide

PRELIMINARY

4/3/86
OVERVIEW

Two programmable timers for the synchronous/asynchronous
line units and one watchdog timer

Parallel I/O Interface

serial

Two 8-bit bidirectional double-buffered I/O ports
One 4-bit special purpose I/O port
Pattern recognition logic
Three independent l6-bit counter/timers
IEEE 488 electrically compatible

1.3

OPERATIONAL OVERVIEW ( ••••• )

This section explains how the KXJll-CA fits into an overall Q-sus
system.
Describes the operational modes of the KXJII-CA. Defines . . .
arbiter/KXJlI-CA relationship for lOP mode. Describes multi-KXJll-CA
con:f igurat ions.

1.4

KXJ11-CA OPERATING MODES

The KXJ1l-CA can operate in either standalone mode or in lOP mode.
The AC and DC
The sections that follow explain these modes.
characteristics of the KXJll-CA are identical in both modes.

1.481

Standalone Mode

The KXJ11-CA can be configured to operate as a standalone processor.
In standalone mode, communication with other Q-Bus devices (including
the system arbiter> is disabled.
The backplane into which the
KXJll-CA is plugged acts as a source of power and ground. The
KXJll-CA preserves the con~inuity of the daisy-chained interrupt
acknowledge and OMA grant lines on the backplane.
Standalone mode is selected when the on-board 10 s~itch is in position
o or 1. In the operational descriptions that appear in this and other
chapters, ignore any referen~es to Q-Bus activity if the KXJ11-CA is
to operate in standalone mode •

.1-3

KXJll-CA User's Guide
OVERVIEW
1.4.2

PRELIMINARY

4/3/86

lOP Mode

The KXJll-CA is designed primarily as an I/O processor. In a typical
system, a KXJll-CA is connected to one or more I/O devices that would
otherwise be interfaced directly with the Q-Bus.
In lOP mode, the
KXJll-CA handles interrupts and data processing associated with the
I/O devices, freeing the Q-Bus from traffic that would ordinarily
degrade system performanceG lOP mode is selected when the on-board ID
syitch is in positions 2 through 15.

1.4.2.1

KXJll-CA From Point Of View Of Arbiter -

1.5

SOFTWARE ENVIRONMENT

1.6

KXJ11-CA SPECIFICATIONS

Physical
Height (quad)
Length (extended)
Width (single)
Weight
Power Requirements
Operational Power
Bus loads

26.6 em (10.5 in)

22.8 cm (8.9 in)
(includes module handle)
1.27 em (0.5 in)
665 g (22 oz) maximum

<----

+/- 5% 6.0 A maximum
+12V +/- 5% 2.0 A maximum
+5V

AC loads • 2 units
DC loads • 1 unit

<---<----

Environmental
Temperature
Storage
Operating

-40 to 66 degrees C (-40 to 150 degrees F)
5 to 60 degrees C (41 to 140 degrees F)

Relative Humidity
Storage
Operating

10% to 90%
10% to 90%

Altitude
Storage
Operating

Up to 15 km (50,000 ft)
Up to 15 kIn (50,000 ft)

Air Quality
Air must be non-caustic.

1-4

(non-condensing)
(non-condensing)

KXJ11-CA User's Guide

1. '7

PRELIMINARY

4/3/86
OVERVIEW

TERMINOLOGY USED IN THIS DOCUMENT

Some terms used throughout this document are defined below.
Local device/memory - R~fers to an I/O device or
located on the KXJ11-CA board.
Global or Q~Bus - Refers to any Q-Bus address
Q-Bus addresses.

memory

that

including

KXJl1-CA

Shared memory - Refers to the area of memory in local
space that is also assigned to a Q-Bus address range.

address

Arbiter - The Q-Bus default master, interrupt acknowledger, DMA
grantor, and power up/down and reset control device (usually
resides in the first slot of the Q-Bus).
BOAL bus - The Q-Bus
lines.

(backplane)

multiplexed

data

and

address

Q-BuS transceivers - The interface between the Q-Sus and the
bus.
ZDAL bus - The 22-bit address and 16-bit data
BOAL transceivers and the KDAL transceivers.

path

between

QDAL
the~~

KOAL bus - 1he KXJll-CA internal module multiplexed data
address bus which is common to all local memory and I/O.

and

JDAL bus - The 22-bit address and l6-bit data
KDAL transceivers and the J-ll microprocessor.

the

path

between

Instruction cycle - The sequence of bus transactions involved in
the execution of an entire instruction by the J-1l microprocessor.
Transaction
- Either a KXJll-CA address and data exchange or a
DMA master address and data exchange with the necessary handshake
signal assertions.
Refers
controller.

DTC

the

Z80l6

direct

memory

access

transfer

PIO - Refers to the Z8036 parallel I/O unit and counter/timer.
uPD720l - Refers to the NEC 7201 multiprotocol serial
Also referred to as SLU2.

controller.

Native firmware - ROM based programs which direct and coordinate
the operation of the KXall-AA and allow the KXJ11-AA to interpret
and respond to commands from arbiter processor.
Refers
receiver/transmitter
as SLUl.

DLART

to
used
1-5

the
DL-compatible
asynchronous
as the console port. Also referred to

KXJ11-CA User's Guide
OVERVIEW
1•8

PRELIMINARY

4/3/86

RELA'l'BD DOCUMENTS

This User's Guide is the
package that accompanies
package include:

primary reference in the documentation
the KXJll-CA. The other documents in the

OCJll Microprocessor User's Guide
Z8036 Parallel I/O Chip Technical Manual
uP0720l Multiprotocol Serial Controller Data Sheet
AmZ80l6 DMA Transfer Controller Data Sheet
8254 Programmable Interval Timer Data Sheet
OLART Data Sheet
KXJll-CA Schematics
KXJll-CA Fir.mware Listings
Other documents the reader may find useful include:
Title
Microcomputers and Memories Handbook
Microcomputer Interfaces Handbook
POP-ll Architecture Handbook
TU58 Technical Manual
These documents are available from:
Digital Equipment Corporation
Accessories and Supplies Group
P.O. Box CS2008
Nashua, NH 03061
Attention: Documentation Products

1-6

Order Number
EB-20912-20
EB-23144-18
EB-23657-18
EK-0TU58-TM

CHAPTER 2
INSTALLATION

2.1

INTRODUCTION

This chapter describes'how to install the KXJll-CA module.
NOTE
Before
changing
the
factory
shipped
jumper
configuration, the user should make sure the jumpers
match those of Figure x-x and should verify that the
module is operating properly as described in Section

x.x.

Installation includes the following activities:
1.

Selecting operating
jumpers

characteristics

Determining power supply requirements

Installing the board into a backplane

Selecting and connecting cables
interfaces to external devices

Verifying proper operation

2.2

SELECTING OPERATING FEATURES

from

and

installing

serial

and

appropriate

parallel

I/O

Sev1eral characteristics of the KXJ1l-CA are defined by
jumper
settings.
This section summarizes which characteristics are part of
the factory shipped configuration. It also shows how to change these
characteristics by changing the appropriate jumpers.
Figure x-x illustrates the factory shipped jumper settings. Table x-x
swmnarizes the meaning of each of the jumper settings. The sections
that follow describe the various
jumper
setting
alternatives
available.
2-1

KXJll-CA User's Guide
INSTALLATIOH

PRELIMINARY

4/3/86.

.. ...•,..
.. ta,
...1I:!l..... ..... ..,
.. ..'..,ta..
Il10..

'''''

•• 1

Woe •

• lolli' (i1 ••u

-~I III

......

••

•

• .."
MK

"'G:!]wnI.!J-'
"UI

'"
c.......
, ..

tOMIOll

-0 1--_----,10
IDOl/In"",

lin ... ,

'."C"

B. ta

----....
~

.
=-

P~Y .z~.

D
Figure x-x

KXJll-CA Jumper Layout

2-2

I~.

~bJ!UJ
.".,-- I ......

-!Hi'
II:D

III. . . . .

KXJ11-CA User's Guide

PRELIMINARY
4/3/86
INSTALLATION

Table x-x Factory Shipped Jumper Configuration
Function

Setting

Jumpers Installed

Q-BuS Size

22 bits

M3 to M4
M5 to M6

Q'-Bus Base Address
10 Switch Position

17760240

Ml to M2

DMA Requests
SLU2 Channel.A
8036 counter/timer
SLU2 Channel B

Enabled
Disabled
Enabled

M7 to MS

BREAK Enable

Enabled

Ml2 to Ml3

HALT Option Selection

MicrOODT

Ml4 to MlS

Power-Up Option Selection*

MicroODT

M16 to M17

PROM Addressing*·

16-bit

MIS to M19

SLU1 Baud Rate

9600

MS6 to M55
M60 to M59

SLUl Transmitter

RS423

M62 to M61

SLU1 Receiver

RS423

no jumper

SLU2 Channel A Receiver

RS422

M34 to M33
M32 to M31
M30 to M29
M28 to M27
M26 to M25
M24 to M23

SLU2 Channel B Transmitter

RS422

M38 to M36
M51 to M50

SLU2 Channel B Receiver

RS422

M42 to M4l
M40 to M39
M20 to M2l

Real-Time Clock Interrupt

60 Hz

M52 to M53

Boot/Self test Switch Position

MIO to MIl

this jumper installed, firmware is not executed upon power-up.
this jumper installed, firmware can not perform user ROM checksum
or sizing calculations.

*~1ith
**~1ith

2-3

KXJll-CA User's Guide
INSTALLATION
2.2.1

PRELIMINARY

4/3/86

Boot/Self test Switch

The boot/selftest switch is a 16 position switch that is used if the
board is configured to execute firmware (rather than MicroODT) upon
power-up. It has three functions:
1.

It determines what the KXJ11-CA will do when a special interrupt
condition exists (see Section x.x) including whether or not
self tests will run.

It determines whether special interrupt handling is
user code or by fi~ware.

It determines where in memory the on-beard 'PROM is mapped.
There
are two alternatives
low memory or high memory. The memory
maps associated with low and high PROM mapping are sho~n in
Figures x-x, and x-x, respectively.

The location of the boot/selftest switch is shown in
Table x-x summarizes the functions associated with
position.

OCr----10

o
Figure x-x Boot/Self test Switch

2-4

performed

pigure x-x.
each switch"

KXJll-CA User's Guide

Switch
position

PRELIMINARY
4/3/86
INSTALLATION

Table x-x Boot/Self test Switch Functions
Special
KXJll-CA
Interrupt
Special Interrupt Response
Handling

PROM
Mapping

User PROM appl~cation code is
executed. No self tests are
performed.

Firmware

Low

User PROM application code is
executed. All self tests are
performed.

Firmware

Low

User PROM applfcation code is
executed. All self tests are
performed. The user (P)ROM
checksum test is also performed.

Firmware

Low

Application cGde is booted from
a TUS8 via SLUt. All self tests
are performed, then the TUS8
primary bootstrap is executed.

Firmware

High

MicroODT is entered. No self tests
are performed

Firmware

High

All self tests are performed.
The KXJ!l-CA awaits command from
the arbiter via TPRO.

Firmware

High

No self tests are performed.
The KXJ!l-CA aw'aits a boot
command from the arbiter via
TPRO.

Firmware

High

All self tests a~e performed
continuously. No application
code is booted or executed.
Loopback connec~ors (see
Section x.x.x) are installed
for these tests. ,_

None

High

User PROM application code is
executed. No self tests are
performed.

User Code

Low

User PROM appli~ation code is
executed. All self tests are
performed.

User Code

Low

User PROM application code is
executed. All sel~tests are
performed. The user '(P)ROM
checksum test is also performed.

User Code

Low

2-5

KXJll-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

Application code is booted from
a TOSS via SLU1. All self tests
are perfo~ed, then the TU58
primary bootstrap is executed.

User Code

High

MicroODT is entered. No self tests
are performed

User Code

High

13 .

All self tests are performed.
The KXJ11-CA awaits a command
from the arbiter via TPRO.

User Code

High

No self tests are performed.
The KXJ11-CA awaits a command
from the arbiter via TPRO.

User Code

High

All self tests are performed
continuously. No application
code is booted or executed.
Loopback connectors (see
Section x.x.x) are installed
for these tests.

None

High

Notes:
1.

Switch position 5 is the factory shipped configuration.

The encoded value of the boot/self test switch position
is
available in the KXJCSRB register, bits <7:4>. For example switch
position 1 would be encoded as 0001 in KXJCSRB <7:4>.

The user· (P)ROM checksum· test looks for a checksum at the highest
word address of user (P)ROM. Similarly, the firmware checksum
test looks for a checksum at the highest word address of the
firmware
PROM.
Either checksum is calculated and checked
according to the DECPROM algorithm which is as follows:
CHECKSUM =- 0
FOR I =- number of PROM addresses to be checksumed DO
CHECKSUM • CHECKSUM + contents of address
(high order carry from addition is discarded)
CHECKSUM • ROTATE LEFT ONE BIT
(bitO -> bitl, bitl ->-bit~, •••• ,n-l -> bitO
NEXT I

Special interrupt handling can be performed by user code in switch
positions 8-15. This function is useful in applications that need
to continue running after the Q-Bus signals BHALT or BINIT has
been
asserted.
For switch positions 0 through 7, special
interrupt handling is done by firmware.

2-6

KXJll-CA User's Guide

PRELIMINARY
4/3/86
INSTALLATION

If the KXJ11-CA is in standalone mode, switch positions 5, 6, 13,
and 14 should not be used. These post ions cause the KXJll-CA to
idle and wait for a command. In standalone mode, the KXJll-CA
will idle indefinitely, waiting for an arbiter command that will
never come.

,""'"
'''''''''"'

IIQWtttl/ll

,"""'

"",..

,.,.",...

=::,.."

''''''''
""17'"",

....

,.,...1/11

' '1'

1
1

Itt. . . . . .

",..
".'''''
, "

."- 01""""

MOM~MO

\.1111,..

....

....,.UII.IoCI
•

Figure x-x Memory Mapping - PROM in Low Memory

2-7

KXJll-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

,""",

~II""

1
... .

""-

"",,"

"""'OllMIO
OIAfHOIT1C1

,""'"

••

..• It

.I"""

J"_
,,"'"

a'"..

1'717''I

I 10 ......

...."" ,I.......
1

lIIIOI,fQIIMIO
OIA4N01'flCl
~.NOII

I"""

.....

•

Figure x-x Memory Mapping - PROM in High Memory

2.2.2

Q-Bus Size

The KXJll-CA may be configured to handle 16-, 18-, or 22-bit Q-bus
addressing.
This is accomplished with the Q-bus size jumpers (see
Figure x-x). 22-bit addressing is selected as part of the factory
shipped configuration.

2-8

KXJll-CA User's Guide

PRELIMINARY
4/3/86
INSTALLATION

...••••.•

0_1___
iill

, .. tb

Figure x-x

Q-Bus Size Selection

Jumper Connection

Description

* M3

0
0

o M5
o M6

22-bit addressing selected

M3
M4

0
0

o M5
o M6

l8-bit addressing selected

M3
M4

0
0

o M5
o M6

i6-bit addressing selected

Factory shipped configuration

2.2.3

Q-Bus Base Address Selection

In systems with multiple I/O processor boards, it is necessary to
distinguish one from another by making sure that each one has a unique
Q-bus base address. This is accomplished on the KXJll-CA by setting
the 10 switch and installing or removing a jumper which connects Ml
and M2.
Table x-x list~the base addresses that can be selected.
Table x-x
lists 22-bit addresses.
If the KXJll-CA is configured for 16- or
18-bit addressing, simply use the lower 16 or 18 bits of the addresses
2-9

KXJll-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

specified in Table x-x.
Figure x-x shows the locations of Ml, M2,
factory shipped base address is 17760240 •

and

the

-0

10 01
II I

¢Jj(-::- ....

......

-Figure x-x
o

Q-Bus Base Address Selection

Factory shipped configuration Base address • 17760240

2-10

switch.

The

KXJll-CA User's Guide

PRELIMINARY
4/3/86
INSTALLATION

Table x-x Q-Bus Base Address Selection
ID Switch Position
0
1
2
3
4
5*
6
7
8
9

10
11
12
13
14
15

Base Address
(Jumper IN)

Base Address
(Jumper OUT)

+
+

17760100
17760140
17760200
17760240*
17760300
17760340
17775400
17775440
17775500
17775540
17775600
17775640
17775700
17775740

11762100
17762140
11762200
17762240
17762300
17762340
17777400
17777440
17777500
17777540
17777600
17777640
17777700
17777740

* Factory shipped configuration
+

The Q-Bus interface is disabled (i.e., the KXJ11-CA is
running in standalone mode) for these switch positions
Caution - Base address selections may cause conflicts
with addresses of existing Q-Bus devices •.

2.2 .. 4

DMA Requests

DMA requests to the on-board DMA transfer controller (DTC) may come
front several sources. The KXJ11-CA has a set of jumpers which enable
or disable DMA requests from: (1) SLU2 channel A, (2) SLU2 channel B,
or (3) the on-board 8036 PIO counter/timer. The location of these
jumpers is shown in Figure x-x. Note that only two of the three
sour'ces may be specified (jumpered) at a time. The two sources that
are jumpered as part of the factory configuration are SLU2 channel A
and SLU2 channel B.

2-1]:

KXJll-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

....

...• • • • ""•
'..."

10 01
u!

..Ul'I

lUI

Jumper Connection
M10

Mll

MlO

DNA Requests

Description

* Mll

• .. d,

D
Figure x-x

* Mll M10

I
I

Allows DMA channel o requests from SLU2
channel A
Allows DMA channel 1 requests from PIO
counter/timer port A
Allows DMA channel 1 requests from SLU2
channel B

* Factory shipped configuration
Note: Do not connect a jumper between M10 and K9: this configuration
is not supported.

2.2.5

BREAK Enable

There is a jumper on the board that enables or disables console BREAK
requests from SLUl (the on-board DLART) to the J-ll. A BREAK is
generated by SLUl when a console terminal is attached to the system
and the BREAK key on the console keyboard is pressed. When BREAK is
2-12

KXJll-CA User's Guide

PRELIMINARY

4/3/86

INSTALLATION

rece'"ived, the J-11 executes MicroODT. The location of this jumper is
shown in Figure x-x.
BREAK requests are enabled as part of the
factory shipped configuration.

. . .0''-___10 iin01,-~'D

! ...

II I

..,: "',J

I
a -ais

Figure x-x

BREAK Enable

Junlpe r Connect ion

Description

* ~t13 0

o M12

Console BREAK requests enabled

1-113 0

o M12

Console BREAK requests disabled

* Factory shipped configuration

2.2.6

HALT Option Selection

A jumper on the KXJll-CA dete~ines what action will be taken if a
HALT instruction is executed in kernel mode. The location of this
jumper is shown in Figure x-x. The jumper affects the state of bit 3
of the Maintenance Register (see Section x.x). If the jumper is
installed
(the
factory
shipped
configuration),
MicroODT
is
unconditionally entered upon the execution of a HALT instruction in
kernel mode. If the jumper is not installed, the KXJll-CA traps
through location 4 in kernel instruction space and sets bit 7 of the
CPU error register when a kernel mode HALT instruction is executed.

2-13

KXJll-CA User's Guide
INSTALLATION

PRELIMINARY

-0

4/3/86

10 01
uU
!! I

1 .-

II.

I
I

_....,.......

"fit

--Figure x-x

HALT Option Selection

Jumper Connection

Description

* M1S 0

o M14

MicroOOT is entered when a HALT
instruction is executed in kernel mode.

M1S 0

o M14

KXJll-CA traps through location 4 in
kernel instruction space and sets bit 3
of the CPU error register if a HALT
instruction is executed in kernel mode.

* Factory shipped configuration

2.2.7

Power-Up Option Selection

The power-up jumper (see Figure x-x) determines what action the
KXJll-CA will take when the board is powered up or reset. The jumper
affects the state of bit 2 of the Maintenance Register (see Section
x.x). If the jumper is installed (the factory shipped configuration),
MicroODT is entered with the PS cleared upon power-up. This is also
known as power-up option 1.
If the jumper is not installed, the
KXJll-CA executes the firmware power-up code at location 173000 upon
power-up (PC • 173000, PS • 340). This is also known as power-up
option 3.
2-14

KXJ11-CA User's Guide

-.0

10 01

If I

PRELIMINARY
4/3/86
INSTALLATION

iill

I ...

I
I

__ II1II" .....' •

I
I

I .. tlt

-Figure x-x

Power-Up Option Selection

Jwnper Connection

Description

* M17 0

o M16

MicroODT is entered upon power-up.

M17 0

o M16

The KXJ11-CA bootstraps via location
173000 upon power-up.

* Factory shipped configuration

2.2418

PROM Addressing

The KXJ11-CA can be jumpered to accommodate various PROM types.
The
location of the PROM addressing jumper is shown in Figure x-x. If the
jumper is not installed, the on-board PROMs use 1S-bit addresses.
PROMS such as the Intel ~764 (8K x 8) and 27128 (16K x 8) use 1S-bit
addresses.
If the jumper is installed, the PROMs use
16-bit
addx"esses.
This accommodates PROMs such as the Intel 27256 (32K x 8)
which use 16-bit addresses. 16-bit PROM addressing is specified as
part of the factory shipped configuration.

2-15

KXJ1l-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

1
1
0
------ 0
lill

Figure x-x
Jumper Connection

PROM Addressing

Description

o Ml9
o MlS

15-bit addressing selected

o M19

16-bit addressing selected

o MlS

* Factory shipped.configuration

2.2.9

SLUl Baud Rate

The jumpers shown in Figure x-x select the default baud rate for the
SLU1 transmitter and receiver. The default baud rate for SLUl is set
when the KXJll-CA is powered up or reinitialized. It can be changed
under software control if KXJCSRJ<3> is set. Table x-x shows the
various baud rates that can be selected. A default baud rate of 9600
is specified as part of the factory shipped configuration.

2-16

KXJll-CA User's Guide

........
........
.........,,

PRELIMINARY
4/3/86
INSTALLATION

0,--1-----,I
iiU
!en

o
D
Figure x-x

M60 0
M58 0
M56 0

0
0
0

M59
M57
M55

• ".h

SLUl Baud Rate

Factory shipped configuration 9600 baud
Table x-x SLUl Baud Rate Jumpering

Baud Rate

M56 to M55

M58 to M57

M60 to M59

38400
19200
* 9600
4800
2400
1200
600
300

In
In
In
In
Out
Out
Out
Out

In
In
Out
Out
In
In
Out
OUt

In
Out
In
Out
In
Out
In
Out

2.2.10

SLUl Transmitter

The SLUl transmitter can be jumpered to send either single-ended
(RS423) or differential (RS422) asynchronous serial data via connector
J3. The location of the jumpers is shown in Figure x-x.
RS423
2-17

KXJll-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

transmission is selected as part of the factory shipped configuration.

-0

IQyf_.......

10 01
!f I

ull

i .

I
I

I ...h

-Figure x-x
Jumper Connection

* M63 M62 M61
0

SLUl Trans.itter

Description
ItS423 transmission selected

M62 M61
RS422 transmission .elected
0
oJ
* Factory shipped confi9uration~
M63

2.2.11

SLUl Receiver

The SLUl receiver can be ·jumpered to receive either single-ended
(RS423) or differential (RS422) asynchronous serial data via connector
J3. The location of the jumper is shown in Figure x-xc
RS423
reception is selected as part of the factory shipped configuration~

2-18

KXJll-CA User's Guide

PRELIMINARY
4/3/86
INSTALLATION

.....•• ,

-0 Ir...-__IO~unOl~---10
II I

i ...

III

o
o
riCJure x-x
Jumper Connection
[ 0

M47
oj

* 1'148

1'147

M48

SLUl Receiver

Description
RS422 reception selected
RS423 reception selected

* Factory shipped configuration

2.2.12

SLU2 Channel A Receiver

The SLU2 channel A receiver can be jumpered to receive either
single-ended (RS423) or differential (RS422) serial data via connector
Jl. The location of the jumpers is shown in Figure x-x.
RS422
reception is selected as part of the factory shipped configuration.

2-19

KXJll-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

...... MU

........wa,,
IIIn • • IIIGt
IIUO • •

;pr-"flGl • • filii'

-0''-------,10
If I

.11

I ..

D
Figure x-x

Jumper Connection

K28 0
K26 0
K24 0

0]
01
0
0
0
0

M33
JIl31
M29

M34 0
JIll2 0
1'130 0
M28 0
JIl26 0
M24 0

o
o
o
a
o
o

M33
JIl31
1'129
1'127
JIl25
JIl23

• H34 0
K32 0
1130 0

SLU2 Channel A .eceiver

Description
RS422 reception selected

1'127

M2S
M23

RS423 reception selected

• Factory shipped confi9u~ation

2.2.13

SLU2 Channel B Transmitter

The SLU2 channel B transmitter can be jumpered to send single-ended
(RS423), differential (RS422), or party line (CCITT R1360) serial data
via connector J2. The location of the jumpers is shown in Figure x-x.
RS422 transmission is selected as part of the factory shipped
2-20

KXJ11-CA User's Guide

configuration.

2-21

PRELIMINARY
4/3/86
INSTALLATION

PRELIMINARY

KXJll-CA User's Guide
INSTALLATION

-0

4/3/86

JO 01

II I

iill

I
I

....•
........
• • ...• , .......
• •
.."

.....

• • •

-Oil

x-x

r19ur~

SLU2 Channel I Transmitter

Jumper Connections

Description

1'138

•

M46

M45

M37

l136

K3S
0

RS422 transmi.sion selected

~ 1 M~ K49
a

1'138
0

l146

1'145

l137

[0
0

1'151

Mfl
0
MSO

M3S
a

IS423 transmission selected

M49

1'138
0

1'146

I 0

K~j

1'137
0
0

M51

(2
M36
0

MSO

l13S

M49

Party line transmission seiected

KXJll-CA User's Guide

PRELIMINARY
4/3/86
INSTALLATION

* Factory shipped configuration

2.2.14

SLU2 Channel B Receiver

ThE! SLU2 channel B receiver can be jumpered to receive single-ended
(RS423), differential (RS422), or party line (CCITT Rl360) serial data
via connector J2. There are two groups of jumpers involved, as shown
in Figure x-x.
RS422 reception is selected as part of the factory
shipped configuration.

2-23

KXJll-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

.........
,,
.....
...,
"lid'
-Ol-··-W-OI__·\~
-J:;-;-~I

-~
In

, ·,11

Figure x-x

SLU2 Channel B Receiver
Description

Jumper Connections

M428
M40
0

1'143
1'141
M39

M44 0
M42 a
1440 0

0
0
0

M43
1'141
1439

1444(0
1'142 0
1'140 0

01
0
0

1'143
M41
1'139

1'144 0

J]M20
o M21
o 1'122
I]M20
o 1421

RS422 reception selected
RS423 reception .elected

o 1422
o M20

I]M21
o M21

party line reception selected

* Factory shipped configuration

2e2.15

Real-Time Clock Interrupt

SLUl (the on-board OLART) can generate real-time clock interrupts at
frequencies of 50 and 60 Hz. Jumpers M52, M53, and M54 select either
the SO Hz or the 60 Hz real-time clock as, an input to the interrupt
control logic.
If interrupts are enabled, each clock "tick" results
in a maskable priority level 6 interrupt request to the on-board J-ll.
The location of the real-time clock interrupt jumpers is shown in
2-24

KXJll-CA User's Guide

PRELIMINARY
4/3/86
INSTALLATION

Figure x-x. A real-time clock rate of 60 Hz is specified as
the factory shipped configu,ration •

part

......
-Ol'-~ iill01,--------,I 0
~:

III

o
D
Figure x-x

I
I

Mlh

aeal-Time Clock Interrupt

':Jumper Connection

De.cript~on

••

M54
M53
M52

60 Hz real-time clock .elected

M54
M53
M52

50 Hz real-time clock selected

ill
rn
0

* ractory shipped configuration
--~..,..........~---

2.3

.-...

POWER SUPPLY' CONSIDERATIONS

When installing the KXJll~CA, the user must make sure the power supply
can handle the extra load presented by the board. The KXJll-CA draws
a maximum of 4A at +5V and 2A at +12V. The board adds 2.7 AC loads
and 1.0 DC loads to the bus.
In standalone mode, at least
four
power
fingers
(backplane
connections) and fou~ ground.fingers for +5VOC must be connected to
the power supply. And at least two power fingers and two ground

2-25

KXJll-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

fingers for +12VOC must be connected to the power supply.

2.4

INSTALLING THE KXJll-CA INTO A BACKPLANE

The KXJll-CA plugs into any DEC standard quad height backplane (see
Pigure x-x). No special backplane wiring or jumpering is required to
accommodate the KXJll-CA. Keep in mind that the grant structure must
be preserved if there are blank slots between the ~ll-CA and the top
of the backplane. This can be accomplished by inserting grant cards
where appropriate.
Figure x-x shows an example of the use of grant
cards. The dual height grant card (M8659) pres.rves grant continuity
for slots A and B and grant card G7272 preserves the DNA and interrupt
grant continuity for slot C. Also keep in mind that the KXJll-CA
board must be configured for the proper Q-Bus adqress size.

Figure x-x Backplane Installation

,
•

2-26

KXJll-CA User's Guide

lC;omponent Side

Solder Side

KXJll-CA

:~in

Signal

CAl
CBl
CCl

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
NC

CA2
CB2
ce2
CO2
CE2
CF2
CH2
CJ2
CK2
CL2
012
CN2
CP2
CR2
eS2
CT2
CU2
CV2

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
NC

OA2
DB2
De2
002
DE2
DF2
DH2
DJ2
OK2
DL2
DM2
DN2
DP2
DR2
DS2
DT2
DU2
DV2

-~----

(:01

C:El
Cptl
CHl
CJl
C:Xl
C:Ll
Ofl
CNl
CPl
CRl
CSl
CTl
(:Ul
CVl
DAl
DBl
DCl
001

DEl
D'Fl
OHl
OJl
OKl
DLl
O:Ml
D.Nl
OPl
O:Rl
DSl
D'rl
001

DVl

PRELIMINARY
4/3/86
INSTALLATION

KXJll-CA
Signal
----~-

+5V

NC
GND
NC
NC
NC
NC.
NC
Nt
NC
IAR. L (Note 2)
IAR L (Note 2)
NC
OMG L (Note 3)
OMG L (Note 3)
NC
NC
NC
+5V

NC
GND

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

Notes:
1.

NC = Not connected

Pin CM2 is jumpered to pin CN2 for the interrupt acknowledge daisy
chain.

Pin CR2 is jumpered to pin CS2 for the DMA grant daisy chain.

2-29

KXJll-CA User's Guide
INSTALLATION
2.5

PRELIMINARY

4/3/86

CONNECTORS AND EXTERNAL CABLING

The KXJll-CA communicates with external devices via a parallel I/O
connector (J4) and three serial I/O connectors (Jl, J2, and J3). This
section specifies the pin assignments of these connectors and ·lists
the types of cables that can be used with each.

2.5.1

Parallel I/O Interface (J4)

The parallel I/O (PIO) interface signals appear at connector J4.
These signals are buffered.
They can be driven over a 50 ft.
distance via a ribbon cable or round cable with a 40-pin AMP contact
housing at each end. A PIO cable is not provided wi th the KXJll·-CA.
We recommend the use of the following cables, available from Digital
Equipment Corporation:
BC06 R shielded ribbon cable
BCOS L "mirror image" cable

x-x shows the pin assignments for J4,

Figure
connector.

the

parallel

-Figure x-x Parallel I/O Interface Pin Assignments

2-30

I/O

KXJll-CA User's Guide

2.5.2

PRELIMINARY
4/3/86
INSTALLATION

Serial I/O Lines (Jl, J2, J3)

The KXJll-CA has three serial I/O lines:
o

SLU2 channel A (Jl), a synchronous/asynchronous serial
modem control

SLU2 channel B (J2),
without modem ~ontrol

SLUl (J3), the console asynchronous serial line (no modem control)

synchronous/asynchronous

line

with

serial

line

Each serial line is compatible with the EIA RS232-C and RS422/RS423
protocols.
In addition, SLU2 channel B (J2) is compatible with the
CCITT R1360 party line protocol. Interfacing the KXJll-CA with 4-20
rnA current loop devices via the serial lines can be done by using the
DLVII-KA option.
The user must supply his own serial line cables.
We recommend the
following cables (available from Digital Equipment Corporation) for J2
and J3:
BC20N-05

AS-foot EIA RS232-C null modem cable for a direct connectiOA
between the KXJ11-CA and an EIA terminal. This cable has a
la-pin (2 x 5) AMP female connector on one end and a 25-pin
RS232-C female connector on the other.

BC21N-05

A 5-foot EIA RS232-C modem cable for a connection between
the KXJll-CA and a modem or acoustic coupler. This cable has
a lO-pin (2 x 5) AMP female connector on one end and a 2S-pin
RS232-C male connector on the other.

BC2()M-50

A 50-foot EIA RS422 or RS423 cable for a direct connection
between the KXJll-CA and a remote processor. Used in
applications requiring. high data transmission speeds (up to
19.2 K baud). This cable has a 10-pin (2 x 5) AMP. female
connector on each end.

The pin designations for J2 and J3 are shown in Figure x-x.
All three serial lines are factory configured to handle differential
inputs and outputs.
If you change the configuration of any of the
serial lines to handle single ended inputs or outputs make sure the
return (-) signal(s) on the cable are tied to signal ground.

2-31

KXJll-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

Figure x-x J2 and J3 Pin A•• ignments (lO-pin)

There is no standard cable available
from
Digital
Equipment
Corporation for SLU2 channel A; the user needs to construct his own.
Figure x-x illustrates the pin assignments for SLU2 channel A (Jl).
Tables x-x through x-x show the correspondence between the pins of the
standard connectors for the RS422/RS423, RS232, and CCITT protocols
and the pins of Jl.
These tables make it easy to construct an
appropriate cable. The KXJll-CA register address associated with each
signal is specified in the last column of each table for ease of
programmer reference. The register descriptions in Chapter x provide
further details.

2-32

KXJll-CA User's Guide

....

PRELIMINARY
4/3/86
INSTALLATION

••• •"' •w

riqure x-x Jl Pin Assignments (40-pin)

2-33

KXJll-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

Table x-x RS422/RS423 Interface to J1
Pin

Circuit

Direction

1
2
3
4

SHIELD
SI
SPARE
SO

From Modem
To Modem

Function

RS-232

CCITT

Location

112

S,E

17777522

Send Data (+)

103

From Modem

Send Timing (+)

114

23,AA 17775706
6,F
12,N 11777520

Protective Ground

R5.

From Modem
To Modem

Receive Data (+)
BS
Request to Send (+) CA

104
105

From Modem
From Modem
To MQdem

Receive Timing (+)
Clear to Send (+)
Local Loop

DD
CS

RT
CS
LL

115
106
141

11
12

DM
TR

From Modem
To Modem

Data Mode (+)
Terminal Ready

CC
CD

107
108/2

(+)

8,J
17775702
13,P 17775704
18,V
l4,R 17775720
16,T 17775700
25,CC Dummy Gen~
22,Z 17775710
33,M 17777520
26,DO
24,'B8 17775700
."
9,K
Dummy Gene
20,X 17775710

13
14
15

RL
IC

From Modem
To Modem
From Modem

Receiver Ready (+)
Remote Loop
Incoming Call

109
140
125

SF/SR

To Modem

Select Frequency
Signal Rate Select CH
Terminal Timing (+) DA

126
111
113

18
19

From Modem
To Modem
From Modem

Test Mode
Signal Ground
Receive Common

142
102
102b

RSR

To Modem
From Modem
From Modem
To Modem

Send Data (-)
Send Timing (-)
Receive Data (-)
Request to Send (-)

31,KK
38,TT
15,5
32,LL

26
27
28
29
30

RTR
CSR
IS
DMR
TRR

From Modem
From Modem
To Modem
From Modem
To Modem

Receive Timing ( -)
Clear to Send (-)
Terminal in Service
Data Mode (-)
Terminal Ready (-)

37,SS
35,PP
17777520
3,C
l7,V
19,W

31
32
33
34
35

RRR

55
5Q
N5
TTR

From Modem
To Modem
From Modem
To Modem
To Modem

Receiver Ready (- )
Select Standby
CG
Signal Quality
New Signal
Terminal Timing (-)

116
110

36
37

From Modem
To Modem

Standby Indication
Send Common

117
102a

20
21
22
23
24
25

SG
RC
SPARE
SDR

STR
RDR

2-34

3,C
1777752f
3,C
30,JJ 17777530
lO,L
17777522
5,E
40,~

2,S

7,H
28,FF Dummy Gen.
27,EE
1,A

KXJll-CA User's Guide

PRELIMINARY
4/3/86
INSTALLATION

No1:es on Figure x-x and Table x-x:
1.

Pins K 9, 25 ce, and 28 FF are driven by dummy generators which
disable RL (CCITT 140), LL (CCITT 141), and SS (CCITT 116)
respectively.

The label.·NC indicates no connection.

The suffix R in a three-letter pin label (such as RDR) signifies
that the pin is associated with the return side of a differential
driver or receiver.

Circuit IS can be redefined to mean SF. Or IS can be redefined to
SR. In the second case, TM is also redefined to SI.
Table x-x RS232-C Interface to Jl

2-35

KXJ11-CA User's Guide
INSTALLATION

Circuit

1
2
3

BA
BS
CA

PRELIMINARY

4/3/86

Direction

Function

CCITT

To Modem
From Modem
To Modem
From Modem

Protective Ground
Transmitted Data
Received Data
Request to Send
Clear to Send

101
103
104
105
106

39,00
6,F
17775706
8,J
17775702
18,V 17775704
16,T 17775700

107
102
109

22,Z 17775710
40,W
24,BB 17775700

6
7
8
9
10

CC
AS
CF

From Modem

11
12

SCF

From Modem

SCB

From Modem

SBA

To Modem

From Modem

SBB

From Modem

17
18
19

DO
SCA

From Modem
To Modem
To Modem

To Modem

From Modem

22
23

CE
CHICI

From Modem
To Modem

To Modem

Data Set Ready
Signal Ground
From Modem
Receiver Ready
(From Modem) (+ DC Test Voltage)
(To Modem)
(- DC Test Voltage)
Unassigned
Secondary Carrier
Detector
Secondary Clear to
Send
Secondary Trans- .
mitted Data
Transmitter Clock

122
121
118
114

Secondary Received
119
Data
Receiver Clock
115
Receiver Dibit Clock
Secondary Request to 120
Send
Data Terminal Ready 108/2
Signal Quality
Detector
Ring Indicator
Data Rate Selector

... "

12,H

17777520

14,R

17777520

26,DD 17777520

110

125
111
112
External Transmitter 113
Clock
Force Busy

Table x-x CCITT/V.35 Interface to Jl

2-36

Location

20,X
5,!
3,C
10,L

17775710
17777522
17777520
17777530

KXJll-CA User's Guide

Circuit

A
B

C
0
E

F
H
J
R
T

V
X

Y
AA

P
S
U

Direction

Function

101
102
105
106
107

To Modem
From" Modem
From Modem

Protective Ground
Signal Ground
Request to Send
Ready for Sending
Data Set Ready

109
10S/1
10S/2
125.
104
104

From Modem
To Modem
To Modem
From Modem
From Modem
From Modem

115
115
114
114
103
103
113
113

2.5.3

PRELIMINARY
4/3/86
INSTALLATION

RS232

RS449

CA
CB
CC

SG
RS
CS
OM

39,00
40,W.
lS,V 17775704
16,T 17775700
22,Z 17775710

RCV Line Signal Oet
Con:nect Data Set
Data Terminal Ready
Calling Indicator
Received Data A
Received Data B

24,8B 17775700

CO
CE
BB

TR
IC

26,00 17777520
20,x 17775710
8,J
17775702

From Modem
From Modem
From Modem
From Modem
To Modem

Receive Timing A
Receive Timing B
Transmit Timing A
Transmit riming B
Transmit Data A

To Modem
To Modem
To Modem

Transmit Data B
Terminal Timing A
Terminal Timing B

DB
BA
DA

RD
RD

Location

RT
RT
ST
ST
SO

14,R

17777520

12,N

17777520

6,F

1 ~775706

SD
TT
TT

10,L

17777530

Loopback Connectors

Loc)pback connectors (not provided) are attached to the ser"ial or
parallel communication potts to determine whether or not they are
operating correctly (see Figure x-x).
They are typically used in
conjunction with the running of diagnostic programs and in some
firmware self tests (see Sections x.x.x and x.x.x).
These connectors
may be ordered from Digital Equipment Corporation or may be built by
the user. If the user wants to make his own loopback connectors, see
Appendix x.
There are three different types of loopback connectors.
A lO-pin
loopback connector (DEC part number H3270) is plugged into J2 to test
SLU2 channel B or into J3 to test SLU1. A 40-pin loopback connector
(DEC part number H3022) is. plugged into Jl to test SLU2 channel A. As
shown in Figure x-x, this loopback connector can be configured to test
RS422 or RS423 operation.
The third type of loopback connector is
als,o 40 pins (DEC part number H3021) and is plugged into J4 to test
the parallel I/O port.

2-37

KXJ11-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

l~oooOQeQQol ;; sa :r =- ....... .,
Figure x-x Loopback Connectors

2.6

ERROR DETECTION AND REPORTING WITH THE LEOS

There are four LEOs on the edge of the KXJ11-CA board which the native
firmware uses to indicate the state of the board.
These are
especially useful for diagnostic purposes
during
power-up
or
reinitialization.
Using the LEDs, the user can quickly verify that
the board is operating properly or, if there is a problem with the
board, can help locate the difficulty.
Table x~x summarizes the
conditions the LEOs can indicate.
Upon power-up or reinitialization, all four LEOs are illuminated for
approximately 1/2 second if they are working properly'. The LEDs are
labeled L~ through Ll from left to right as vi~wed from the back of
the box when the KXJ11-CA is installed 1n a backplane. If the
KXJll-CA runs its self tests (this is determined by the setting of the
boot/self test switch), L4 is off and Ll - Ll are on as the self tests
run. If one of the self tests fails, L4 is illuminated and L3
Ll
indicate the test that failed. ,Self tests are run in the order listed
in Table x-x. Thus, if a test fails, the user can also determine
which tests (if any) passed.
If all the self tests run without error, the KXJll-CA performs a boot
operation.
The boot/self test switch setting determines what func~ion
is performed. L4 remains off and L3 - Ll indicate the status of the
executing code.
Note that the boot/self test switch may be set such
2-38

KXJll-CA User's Guide

PRELIMINARY
4/3/86
INSTALLATION

that self tests are not run. If that is the case then L4 is off and L3
- Ll indicate the state of the board as it executes code.
Table x-x

LED Display Definitions

LEDs
L3 L2

Meaning

All LEDs on for 1/2 sec. at the start of a power-up
or reinitialization operation
Can't access Control/Status Registers in I/O page
DMA or RTC test failed
RAM test failed
ROM checksum test failed
Serial line test of SLUl failed
Serial line test of SLU2 channel A failed
Serial line test of SLU2 channel B failed
Parallel port test failed

x
x
x
x

0
0
0
0

0
0

x
x
x

x
x

x
x
0
0

0
0
0
0
0
0
0
0

x
x
x

x
x

x
0
0
0
0

x
x

Auto self tests running
Loopback tests running
Q-Bus OOT mode
Fatal runtime error
Waiting for command
Performing DTC load
TUSS primary bootstrap executing
Executing non-native code

Quick LED Reference
L4

LEDs
L3 L2

Meaning

x
x

Self test error detected
Fatal self test error detected

0
0

No self test errors detected
Application running without error

Note: x
o

:I
:I
:I

2.7

ON
OFF
Don't care <either ON or OFF)

DIAGNOSTIC TESTING WITH XXDP+

TheKXJll-CA can be tested by running XXDP+, a diagnostic operating
system that is booted from the user's system disk. This section
explains how to run the XXDP+ diagnostics to te~ the KXJll-CA.
More
infc)rmat ion on XXDP+ is found ,in the XXDP+ System User's Manual
2-39

KXJ11-CA User's Guide
INSTALLATION

PRELIMINARY

4/3/86

(AC-F348F-MC).
When the user has successfully booted XXDP+ from his system disk, a
message such as the one shown below appears on the console terminal.
The items that are blank (underscore) indicate values that are system
dependent.
BOOTING UP XXDP-SM SMALL MONITOR
XXDP-SM SMALL MONITOR VERSION
BOOTED FROM
KW OF MEMORY
NON=UNIBUS SYSTEM
RESTART ADDR: 152010
THIS IS XXDP- SM TYPE "H" or "H/t" FOR HELP
When the "period" prompt appears, the user types in:
R KXJ008<CR>
This initiates the running of the tests. The message KXJ008.BIN then~;
appears
on
the
console followed by several lines of system
information. Then the following should appear:
USE <ESC> TO HALT
KXJ FUNCTIONAL TEST
SWR

OCTAL

15
14
13
12
10
09
08
07

100000
040000
020000
010000
002000
001000
000400
000200

SWR

FUNCTION

.----,.-,-

:II

140000

-...,~----

HALT ON ERROR
INHIBIT ERROR SUMMARY
INHIBIT ERROR REPORTS
UNUSED
UNUSED
LOOP ON ERROR
LOOP ON TEST IN SWR<6:0>
INHIBIT TEST NUMBER/TITLE
NEW :II

At this point, the user should type in 100000<CR> which runs the tests
until an error is detected.
As the tests run, their results are
displayed on the console. If an error is detected, a self-explanatory
error message is displayed and the tests halt. To rerun the tests
after an error occurs, the user should halt the system and type in:
@152010G<CR>
When the "period- prompt appears, the user
typing in:
2-40

can

rerun

the

tests

KXJll-CA User's Guide

PRELIMINARY
4/3/86
INSTALLATION

R KXJ008<CR>
To repeat the procedure· described previously.
If no errors are
detected, testing can be terminated by pressing the ESCAPE key.or by
halting the system.

2·-41

CHAPTER 3
ARCHITECTURE

3.1

INTRODUCTION

This chapter describes the architecture of the KXJll-CA and explains
operation of the various user-accessible portions of the KXJll-CA.

the

In the case of the on-board I/O devices (chips), more detailed information
is found in the data sheets that accompany this documentation package. The'
chapter describes how the I/O devices operate on the KXJll-CA.
This
information may differ somewhat from that in the data sheets, since t'he
data sheets describe the operations on a chip level, indepe~dent of~
application. The differences where they exist are noted.

J.2

KXJll-CA BLOCK DIAGRAM

Figure x'-x illustrates the major operational elements and data paths of the
The sections that follow describe the important characteristics
of these components.

KXJ1I-CA,.,

3-1

KXJll-CA User's Guide
ARCHITECTURE

PRELIMINARY

4/3/86

lOCAL
IN

fl''''''''''

.DOMlll"IST SWITCH

O t - - - - - -..

Mt'\.ICAflON

DIM
CON'MOUI"

5I"ACI

Figure x-x

3.2.1

KXJll-CA Block Diagram

J-l1 Microprocessor

The J-11 microprocessor operates at 14.0 Mhz. It contains a full PDP-ll
memory management unit (MMU) and executes the PDP-ll Extended Instruction
Set (EIS). The processor also contains microdiagnostics as well as console
ODT.
Cache memory and the FPA (Floating Point Accelerator) are not
included as part of the KXJll-CA architecture. The start address is fixed
at 173000 with the restart address at 173004. Status bits are used to
determine the reason for a restart. J-ll power-up options land 3 are
selectable via jumper M17-M16.

3.2.2

RAM

Employing 256K x 1 dynamic RAM chips, a 512 KB x 18 bit array is provided
for memory and parity storage.
RAM may be accessed locally or may ~e
configured as shared memory (accessible locally and from the Q-Bus) 1n
quantities of 0 KB to 512 KB. Shared memory is assignable in 8 KB blocks
on 8 KB address boundaries and if more than one block is configured 'they
3-2

KXJ11-CA User's Guide

PRELIMINARY
4/3/86
ARCHITECTURE

'9
contigious.
The memory is configured with the KXJCSRF and KXJCSRH
..... gister,s and is enabled by a bit in the KXJCSRJ register.
KXJCSRF
contains the starting Q-Bus address as well as the number of 8 KB blocks
assigned to the shared memory. KXJCSRH contains the ending Q-Bus address
assigned to the shared memory. S'ection x.x provides more details on shared
memory and how to set it up.

3.2.3

Two Port Register (TPR) File

The Two Port Register (TPR) File is a 16 word set of registers that can be
accessed either by the on-board J-ll microprecessor or by the Q-Bus. The
TPR file is the primary means by which the Q-Bus arbiter controls and
commUniCi!ltes with the KXJ11-CA.
There are four groups of TPRs. TPRO
through TPR3 is a communication channel between the KXJ11-CA native
firmware and the arbiter. The other three groups, TPR4 through TPR7, TPR8
through TPRll, and TPR12 through TPR15 typically act as communication
channels between the user's application and the arbiter. All TPRs reside
in the GAP on-board gate array (DC7036B). The TPRs are enabled by a, bit in
the KXJCSRD register.
If TPRs are disabled, all TPRs except TPRO are
read-only from the arbiter side and always read as zeros.
Writes to any
register except TPRO will time out if the TPRs are disabled. writes to
TPRO with the TPRs disabled succeed but read a zero. This allows a write~"
to TPR<l~.> to cause a hardware reset. Figure x-x illustrates the TPR file.

----------------• t-----=---I.-tt.,.._
- .••• I---...-;.;;-:--_f , , - •

.n..... _

I---~~-_f

- , - - - - _ . _ ...

I---~--_f
1 - - -......~_--_f

::=..-::--

:::::r

1'------1------"_'.
I - - -.....-~----I ......I-----~---I ...-.I---~~-_f

::=..-:--

1----=:-----1-,-... --.-....- ...
I----=~--I.,,--

_ .•.• t----=~-..L.I. ~:=.""'~-------~~-~~

Two Port Register (TPR) File

3.2.3.1

TPRONOTE'

'r'he description of TPRO that follows assumes that bit 6

KXJCSRJ (NMI enabled) is set.

From the Q-Bus, TPRO can be inter~reted or used in three different ways:
as a KXJll-CA control register, as a test register, or as a Q-Bus OOT
lister.

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If bit 15 is cleared when TPRO is written from the Q-Bus, TPRO is
interpreted as a control register. If bit 15 is set when TPRO is first
accessed from the Q-Bus, TPRO is interpreted as a test register.
After a
·Start Q-Bus OCT- command is issued (i.e., when bit 3 is set while TPRO is
used as a control register) TPRO is interpreted as a Q-Bus ODT command
register until an~Exit Q-Bus OOT" or ·Proceed" or "Start Program" command
is issued (i.e., until bit 15, bit 4, or bit 3 is set). The sections that
follow provide bit descriptions for all three interpretations of TPRO.
Bit 14 of TPRO is always used as a "hard reset" which when set from the
Q-Bus causes a KXJll-CA exception condition which is handled by the
KXJ11-CA native firmware. A hardware or software reset or a Q-Bus OOT "Go"
command disables non-maskable interrup~,.
To avoid unpredictable results, the user should not alter the TPRs used to
pass parameters while a command or test is executing. The bit descriptions
in the sections that follow specify which TPRs are used to pass parameters
for the various commands and tests.
After any command, test, or Q-Bus
without error), TPRO is cleared.

ODT

operation

executed

(with

3.2.3.1.1 TPRO As A Control Register - If TPRO is used as a control
register (Figure x-x), a set bit in TPRO<9:0> specifies a command. Only
one command at a time can be specified.
If any parameters accompany a
command, they are passed via TPR2 and TPR3.

SHOW
SHM

PRG

TC I

COM

D'S
SHM

EN
SHM

OMA

OOT

NOP

LOAD

SHO

CON

INIT

TRAP
MA·17200

Figure x-x

TPRO as a Control Register

Bits

Name

Description

TC I

Test/Control indicator - When set,
TPRO is used as a test register.
When cleared, TPRO~is used as a control
register.

HR" .

Hard reset - When set, a local power-up
sequence occurs during the write portion
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of the current Q-Bus cycle. The setting
of this bit cancels any previously
invoked operations. Setting this bit
causes a hardware reset and is equivalent
to powering up the board regardless of.
whether or not the native firmware is
installed or whether the TPRs or nonmaskab1e interrupts are enabled.
13:11
10

Not used (read/write)
WRU

What are you .- When set, causes the
firmware to write a value of 1 in
TPR2, indicating that the board is a
KXJll-CA.
Not used (read/write)

DIS SHM

Disable shared memory - When set,
disables shared memory. When set and
when shared memory is already disabled,
sets bit 15 of TPRl to indicate a
command error.

SHOW SliM

Show shared memory - When set, bits
<22:13> of the starting address of
shared memory is loaded into TPR2 bits
<9:0>. The number of pages to be shared
minus one is loaded into TPR3. When set
and when shared memory is disabled, sets
bit 15 of TPR1.

EN SliM

Enable shared memory - When set, enables
shared memory. Loads bits <22:13> of the
starting address of shared memory from
TPR3 bi ts <9 :.0>. Bi ts <12: 0> of the
starting address are zeros. Loads the
number of 8 KB blocks to be shared minus
one from TPR2.

NOP

No operation - This bit is reserved for
use by Digital Equipment Corporation. It
currently has no effect on KXJll-CA
operation.

SHO CON

Show configuration - When set, loads
the boot/self test switch setting into
TPR3<7:4>. Also writes TPR3<2:1> with
the type of ROMs used on the board as
summarized below:
TPR<2:1>
00
01
3-5

ROMs

8 K x 8
16 K x 8

KXJll-CA User's Guide

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x 8

32 K

Not used

ODT

Start Q-Bus OOT - When set, forces the
KXJll-CA into Q-Bus ODT mode. TPRO is
redefined (see Section x.x) until bit .
15 (EXIT), bit 3 (GO), or bit 4 (PROCEED)
is set.

RE INIT

Restart/Initialize - When set, forces
the native firmware to perform its
power-up sequence. If TPR3 contains
an 8 (decimal), the boot/self test
switch setting is used to determine what
operations to perform. If TPR3 contains
o through 1 (decimal), that value is used
instead of the boot/se1ftest switch
setting. TPR3 values greater than 8
(decimal) are not valid.

DMA LOAD

DMA load - When set, starts a chain
load of the DTC. TPR3 is used to pa~s
a "segment tag" parameter and TPR2 is
used to pass an "offset tag" parameter of
a chain control table (see Section x.x).
After the operation is complete, bit 14
of TPRl is set and the contents of the
orc Status Register are written into TPR2.

TRAP

Trap - When set, causes a trap
emulation. The trap vector is in TPR2
(which contains the PC) and TPR3 (which
contains the PSW). The trap vector is
assumed to be in kernel I space.

3.2.3.1.2 TPRO As A Test Register - If TPRO is used as a test register
(Figure x-x), a set bit in TPRO<10:0> specifies a test. Only one test at a
time can be specified. Test results are passed ,via TPR2 and TPR3 as
described below.
After a test is complete, TPRO is cleared. The user
application should be reloaded after any of these tests are performed.

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QIR

TC I
TPR

SLUl

PIO

aaus

SLU2

CPU

BEVENT

RAM
ROM

CSR

DMA
M"'.17201

Figure x-x· TPRO as a Test Register

Name

Description

TC I

Test/Control indicator - When set,
TPRO is used as a test register.
When cleared, TPRO is used as a control
register.
~

14:11

Not used (read as zeros)
TPR

TPR test - When set, performs read and
write tests on the local side of the TPR
file. TPR4 through TPR15 are zeroed upon
completion of this test.

QIR

QIR test - When set, tests the Q-Bus
interrupt mechanism. The address of
the interrupt vector must be in TPR3
before this test is run.

DNA

DNA controller test - When set, tests the
on-board DNA controller by performing DNA
transfers between memory locations.

PIO

PIO .test - When set, tests the parallel
I/O port and its associated timers. A
loopback connector must be installed on
J4 before this test is run.

SLU2

SLU2 test - When set, tests the
multiprotocol serial controller.
LOQpback connectors for Jl and J2
must be installed before this test is
run. A one in TPR3 indicates SLU2
channel A is to be tested. A two in
TPR3 indicates SLU2 channel B is to
be tested. A zero in TPR3 indicates
SLU2 channels A and B are to be tested.
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SLUl

BEVENT
,.

SLUl test - When set, tests the console
serial line. A loopback connector must
be installed on J3 before this test is
run.
BEVENT test - When set, verifies that

the line clock interrupt (BEVENT) can be
enabled, asserted, and disabled. The
interrupt associated with BEVENT is at
priority level 6 with a vector of 100.

CPU

CPU test - When set, tests the on-board
J-ll microprocessor.

ROM

ROM test - When set, performs a checksum
test of the on-board ROM. TPR3 must be set
to 1 if the user (P)ROM and the native
firmware are to be tested or to zero if
only the native firmware is to be tested.
RAM test - When set, performs a nondestructive test of all on-board RAM.

CSR

CSR test - When set, performs read
tests on KXJCSRA throu9h KXJCSRJ and
the control/status reglsters for all
the other on-board I/O devices.

TPR2<lO:O> indicate which test(s) if any have failed (see Figure x-x).
A
set
bit indicates a failed test.
Note the correspondence between
TPR2<lO:0> and the tests specified by TPRO<lO:O> respectively. TPR2<15:11>
are unused.

f17

--,a

• ~a.cr:'V
TOT COOl 0" LAST~UT

OISCRITI liT ENCODED ERROR OF \..AST TlST

Figure x-x TPR2 as a Test Result Register
TPR3 provides detailed information about certain failed tests as summarized
in Table x-x.

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Table x-x TPR3 as a Test Result Register
Failed
Test

TPR2 Bit
Set

CSR

TPR3 Bit
Set
0
,-

1
2
3
4
5

6
7

8-15

BEVENT

o
1
2
3

4-15

SLUI

o
1

2
3
4

5
6

7-15

SLU2

o
1

2
3
4

5 ---6-15

PIO

o
1
2
3
4

5
6
7

8-15
DMA

o
1

2
3
4

Definition
Bus error at CSR address
Bus error at OIR address
Bus error at TPR address
Bus error at SLUl address
Bus error at SLU2 address
Bus error at SLU2 counter/timer address
Bus error at PIO address
Bus error at DMA controller address
Unde'fined
ROM in vector space, can't run
Clock interrupt not masked at level 6
Clock doesn't interrupt
Can't shut it off
Undefined

ROM in vector space, interrupts not tested
XMTR interrupt not masked at level 4
XMTR interrupt not received
RCVR interrupt not masked at level 4
RCVR interrupt not received
Recieved data incorrect
No RCVR done, loopback open
Undefined
ROM in vector space, can't run
SLU2 counter/timer 2 doesn't interrupt
Asych mode, data transfer incomplete
Synch mode, EOF-SDLC not received
Synch mode, data transfer incomplete
Synch/asynch mode, received data incorrect
Undefined
ROM in vector space, can't run
Reset state incorrect
Timer didn't start
Timer never stops
Interrupt not masked at level 4
Interrupt not received
'LOOp timeout, data transfer incomplete
Received data incorrect
Unused
ROM in vector space, interrupts not tested
address undefined, access not tested
Channel interrupt not received
DNA channel hung (TC/EOP both cleared)
DNA aborted (BOP • 1 • NXM)
DNA data error
O~Bus

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6-15

4/3/86

Unused

3.2.3.1.3 TPRO As A Q-Bus ODT Register - TPRO is interpreted as shown in
Figure x-x when the KXJl1-CA is in Q-Bus ODT mode. This interpretation of
TPRO continues until-bit 15 is set.

OP EX
REG

eXIT

PRO

Figure x-x

DEP

OP EX
MJ:M

TPRO as a Q-Bus ODT Register

Bits

Name

Description

EXIT

Exit ODT ~ When set, Q-Bus ODT mode is
exited. The KXJ11-CA then awaits a
command from the arbiter.
Not used (read/write)

14:5
4

PRO

Proceed - When set, the context of an
interrupted program is restored and
the execution of the program resumes
at the address specified by the restored

pc.

Start program - When set, a restart
operation is performed and the execution
of the program begins at the PC address
passed via TPR3. The system bus is
initialized. A RESET instruction is
executed to initialize the local I/O
devices. The MMRO<lS:13,0> and MMR3
registers are zeroed by Micro/ODT and
are zeroed on this system when RESET
is executed. The following registers are
cleared PS, PIRQ, CPUERR, Memory System
Error, and Floating Point Status. The
system Memory Error Register (177744) is
cleared by Micro/ODT but does not exist
on the KXJl1-CA.
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DEP

Deposit - When set, the contents of TPR2
are loaded into the current open memory
location or register.

OP EX REG

Open and examine register - When set,
the register specified by TPR3 is
opened and its contents are loaded
into TPR2. The registers are encoded
in TPR3 as follows:
Code
000000
000001
000002
000003
000004
000005
000006
000007
000010

Any other code will set bit 15 of TPR1,
indicating a command error.

Open and examine memory - When set,
opens a memory location and deposits
its contents in TPR2. The address of
th~ memory location has 22 bits. The six
mo.t significant bits are obtained from
the six least significant bits of TPR2.
The lower 16 bits are obtained from
TPR3.

OP EX MEN

3.2.3.2 TPRl - TPRl is used to record KXJll-CA errors. This register is
read-only from the O-Sus but can be read or written by the on-board J-ll.

CMO
ERR

FATAL
ERR
DMA
ERR

STK

ERR
MA.11203

Figure x-x
3-11

TPRl

KXJll-CA User's Guide
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Bits

Name

Description

om ERR

Command error - Set when an error is
detected during the execution of a
command.

DMA·"ERR

DMA error - Set when the DTC aborts
after a DNA LOAD command from TPRO
(bit 1) has been issued.
Not used (read/write)

13:6
5

FATAL ERR

Fatal error - Set when a fatal error
is detected during auto self test,
Q-Bus controlled self test, or the
execution of a user program. The
KXJI1-CA becomes unavailable and
does not respond to any commands
from the arbiter except the setting
of TPRO bit 14 which causes a hardware
reset.
Not used (read/write)

STK ERR

Stack error - Set when a red or yellow
stack violation (see Chapter 1 of the
J-ll User's Guide) occurs. In kernel
mode, this is a fatal error.

2:0

STATE

State - Reflects the state of the
KXJ11-CA:
000

Zero State - KXJII-CA not
available. No commands should
be sent from the Q-Bus.

001

Power-up Auto Self test - The
KXJll-CA is performing its
auto self tests.

010 . Dedicated Test State - The
boot/self test switch is set
to either 7 or 15. No commands
should be sent from the Q-Bus.
011

Q-Bus aDT Mode - The KXJll-CA
is participating in a Q~Bus ODT
operation. Only Q-Bus OOT commands
should be sent from the Q-Bus.

100

Waiting For Command - The KXJ11-CA
is idle and waiting for a command
from the arbiter.
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101

Loading Application From TOSS The KXJll-CA is loading (or
attempting to load) a boot block
from the TUSS connected to the
console' serial line.

110

Reserved - This state is reserved
fo~ future use by Digital Equipment
Corporation.

111

Executing User Application Code The KXJll-CA is executing a user
application program.

Note that STATE is indeterminate when
J-ll console ODT is active.

3.2.3.3 TPR2 - TPR2 is used to pass parameters required to execute
commands.
See the description of TPRO (Section x.x) for the commands and
parameters that involve TPR2. This register can be read or written,.by both
the Q-Bus and the on-board J-ll.

3.2.3.4 TPR3 - TPR3 is used to pass parameters required to execute
commands or perform tests.
Refer to Sections x.x.x and x.x.x for the
commands, tests, and parameters that involve TPR3.
Upon hardware reset,
TPR3 has the following format:

Figure x-x
Bits

Name

I I

TPR3 Format During Hardware Reset
Description
Not used (read as zeros)

15:8
- '4

BOOT

Boot/self test switch - Reflect the
encoded switc.h position of the
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boot/self test switch.
Not used (read as zeros)

3:0

This register can be read or written by both the
J-ll.

Q-Bus

and

the

on~board

3.2.3.5 TPR4 Through TPR1S - If the TPRs are enabled and the appropriate
enable bit in KXJCSRD is set, registers TPR4 through TPR1S are used by the
user's application to pass status and control information between the Q-Bus
arbiter agd the KXJll-CA.
All the TPRs may be read or written by the
on-board J-11. From the Q-Bus, however, TPR1, TPRS, and TPR9 are read-only
and the other TPRs are read/write.
Writes to TPR4, TPR8, and TPR12 from the Q-bus cause maskable level 5
interrupts. The vectors associated with these interrupts are 120, 124, and
134, respectively. The status of the enables and the interrupt requests'
are contained in the KXJCSRD register.

3.2.4

CPU ID Switch

A hex encoded ID switch is used to select the standalone or the lOP mode of
operation.
ID numbers range from 0 through 15, with 0 and 1 signifying
standalone operation and 2 through 15 signifying system usage of the Q-Bus.
The ID switch code can be read via KXJCSRC. 'There are two jumpers (M3-M4
and M5-M6) that correspond with the address width (16-, 18-, or 22-bit) of
the Q-Bus backplane being used. These jumpers determine the size of the
memory decode required for shared memory.

3.2.5

DMA Controller

A 16-bit DMA controller is addressable by the local processor as an I/O
device.
The DNA controller has two independent channels and can perform
transfers between any local 22-bit address and any 16-, 18-, or 22-bit
Q-Bus bus address. Transfers can also be performed between any two local
22-bit addresses or any two Q-Bus addresses. Word, high byte, and low byte
operations are supported locally.
Only word operations are supported
across the Q-Bus interface. Either the source or the destination may have
incrementing, decrementing, or fixed addresses. Words may be compared with
a mask register as they flow through or as they are read.
DMA operations
can be interleaved with the local processor and the other channel, or may
occur in various burst sizes. Channel 0 or channel 1 can service hardware
requests from SLU2 or the PIO, or can be invoked by software commands after
certain mask control bits are cleared.

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wake-up Circuit

The wake-u~ circuit provides autQmatie generation of the INIT signal on the
J-ll to lnitialize the LOCAL system (i.e., the KXJll-CA board only). The
wake-up circuit does not support power down sequencing and assumes that +5V
and +l2V rise together.
Q-Bus signals BoeOK and BPOK are used to
synchroni~e the Q-Bus with the
LOCAL system bus.
With Vec rising in
approxim,stely 30 '''',40 ms, power-up occurs in approximately 400 ms for
standalo:ne mode and 550 rns for non-standalone mode.

3.2.7

PROM And Firmware Control

The operation of the KXJll-CA is controlled by firmware that resides in two
8K x 8 PROMs (Intel 2764 or equivalent). The firmware occupies 8 KB of
PROM space. The other 8 KB of PROM space is available for the user's
applicat:ion program (see Figure x-x). Note that PROM data at addresses
2140000 through 2177777 also appears at other addresses. As shown in the
figure, the address space from 2140000 - 2177777 is duplicated three times
for the 13K x 8 PROMs.

If the user wants to put his application in PROM, he will need, a PROM
programmer and a program called DECPROM or its equivalent. Using these ~~
items, the user blasts new PROMs which contain: (1) a copy of the firmware
and (2) the application.
The procedure for doing this is explained in
c:
t"
. ~c lon x.x.
8K X 8 PROMS
2177777

FIRMWARE

2160000
USER CODE

.....
~

2000000
Figure x-x PROM Space Allocation - 8K x 8 PROMs
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The KXJll-CA can also accommodate two 16K x 8 (Intel 27128 or equivalent)
or two 32K x 8 (Intel 27256 or equivalent) PROMs if the user needs more
than 8 KB of PROM for his application. Pigure x-x shows how address space
is allocated for the 16K x 8 PROMs. The data at addresses 2100000 through
2177777 is duplicated once. Figure x-x shows the address space allocation
for the 32K x 8 PROMs. There is no duplication of address space when.using
th~ 32K ~ 8 PROMs. '.' The firmware always occupies 8 KB of space.
2177777
FIRMWARE
2160000

2100000
USER CODE

.2000000

Figure x-x

PROM Space Allocation - 16K x 8 PROMs

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32K X 8 PROMS

2177777 , . . - - -.....- - - - - - -......
FIRMWARE
2160000 ...._ _ _ _ _ _ _ _......

USER eOOE

2000000 _ _ _ _ _ _ _ _ _ _ _.....

Figure x-x

PROM Space Allocation - 32K x 8 PROMS

3.2.7.1 ,Native Firmware Vs.
User-Designed Firmware - The KXJll-CA is
shipped 'with firmware that is referred to as "native firmware". Native
firmware provides the KXJl1-CA with the functions described in the sections
that follow. The handling of Q-Bus exceptions, interrupts, and resets are
all functions which involve the native firmware.
The user, however, may wish to design his own firmware.
User-designed
firmware should have an entry point at physical location 173004. An entry
point in firmware for location 173000 should also be provided for power-up
handling.

3.2.8

KXJll-CA Control And Status Registers

rhe KXJll-'CA has eight registers which are used to monitor and control the
overall operation of the board. These are the KXJl1 Control and Status
Registers and are described in the sections that follow.
All the KXJll
Control/Status Registers are contained in the on-board gate arrays.

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3.2.8.1 KXJ11
Control/Status
Register
A (KXJCSRA) - Control/Status
Register A (Figure x-x) is used to monitor and control SLU2 and the real
time clock (RTC). This register is cleared upon hardware reset.

Figure x-x KXJll Control/Status Register A

ADDRESS: 17777520

eNT Ie

TEAM

RTCIE

SER
TT 108/2

3-18

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KXJ11-CA User's Guide

dits

Name

Description

15:8
7

Not used (read as ones)
CNT IE
,~

PRELIMINARY
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ARCHITECTURE

RTC IE

Programmable counter interrupt enable When set, interrupts from programmable
timer/counter 2 are enabled. When cleared,
these interrupts are inhibited.
Real time clock interrupt enable When set, interrupts from the on-board
line-time clock (LTC) are enabled. When
cleared, these interrupts are disabled.
Not used (read/write)

IN SER

Terminal in service - For use with
modems. When set, Terminal In Service
(IS) is asserted and incoming calls
can be connected. When cleared, IS
is not asserted.

TERM

TTI08/2

Modem connected - For use with modems.
When set, Terminal Ready (TR) is
asserted. When cleared, TR is not
asserted.

SYNCM A

Clock select channel A - When set, SLU2
channel A receives its clock from the
on-board baud rate generator. When
cleared, channel A receives its clock
from an external source.

SLU2BR EN

Party line enable - Used when the
KXJ11-CA is configured for party line
operation. When set, SLU2 channel Bean
not receive party line data. When cleared,
party line data reception for channel B is
enabled.

SYNCM B

Clock select channel S - When set, SLU2
channel S receives its clock from the
on-board baud rate generator. When
'cleared, channel S receives its clock
fr,om an· external source.

3.2.8.2 KXJ11
Control/Status
Register
S
(KXJCsas) - Control/Status
Register S· (Figure x-x) is used to monitor the state of the boot/self test
switch, the base address jumper, the bus size jumpers, and the SLU2 modem
t~st
function. The register is read-only with the exception of bits <7:4>
~ch are read/write.
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ADDRESS: 17777522
15

BAse
TT142

Figure x-x KXJll Contr~l/Status Register B
Bits

Name

Description
Not used (read as zeros)

15:8
7:4

SST

Boot/self test switch - Contains the
encoded value of the boot/self test
switch position (see Section x.x for
a description of the boot/self test
switch). 0000 corresponds to switch
position 0, 0001 corresponds to switc.h
position 1, and so on. These bits are
read/write. BST is loaded with the
encoded value of the boot/se1ftest
switch on hardware reset and can be
changed by the user's software. The user
should exercise caution when writing
SST since it changes the configuration
of the board.

BASE

Base address jumper - When set,
indicates that the Q-Bus base address
jumper is installed (see Section x.2.3).
This bit is loaded upon hardware reset
and cannot be chang~ by software.

2:1

BUS

SIZE

Bus size jumpers - Indicates the Q-Bus
size jumper settings (see section x.2.2).
This bit is loaded upon hardware reset
and cannot be changed by software.
BUS SIZE
00

01
10
11
Q

TT142

Address Bits Used
22

16
18
Reserved

Modem test - When set, indicates that the
modem connected to SLU2 channel A is in
test mode. When cleared, indicates that
the modem is not in test mode. Cleared
upon hardware reset.
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~ 1.8.3 KXJ11 Control/Status Register C (KXJCSRC) - KXJll Control/Status
, Jister C (Figure x-x) contains infor-mation on the state of the CPU 10
switch and the state of the on-board LEOs.

ADDRESS: 17777524

I I I I I I I I I : If ; I : +: I
15

Figure x-x KXJ11 Control/St~tus Register C
Bits

Name

Description

15:8
7:4

Not used (read as zeros)
ID

CPU 10 switch - Contains the encoded
of the CPU 10 switch position.
0000 corre~ponds to switch position 0,
0001 corresponds to switch position 1,
and so on. These bits are read-only.~
These bits are loaded upon hardware
reset and cannot be changed by software.

va~ue

LED

LED state - Each bit determines the
state of one of the four on-board LEOs.
LEOs 4 through 1 correspond to bits
<3:0>, respectively. If a bit is set,
the LED is ON. If a bit is cleared,
the LED is OFF. These bits are read to
determine the state of the LEOs or are
written to set the LEDs. These bits are
set to ones upon hardware reset.

3.2.8.4 KXJ11 Control/Status Register 0 (KXJCSRD) - KXJll Control/Status
Register 0 monitors and controls the Q~ the TPRs, and the Q-Bus
reset/interrupt mechanism. This reQister is cleared UDon reset. Access is
read/write.
ADDRESS: 17777530

PWRFL

IQIR

IE
QIR REO

TPR
QS
SHALT
RQST
RESET
SQIR
QS
SHALT..... TPR
IE
. EN
EN
RESET
IE

3-21

IE<124>

RQ<120>
RQ<134>

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Figure x-x KXJll Control/Status Register D
sits

Nue

Description

PWRPL

Power fail - When set, the Q-Bus
has deasserted BPOK, indicating a
power failure. When clear, indicates
that BPOK is asserted.

OIR REO

OIR request - When set, indicates
that the OIR has been written and
that a Q-Bus interrupt is pending
Clearing OIR REQ after it has been
set clears the pending request to
the Q-Bus. The deassertion of the
O-Bus signal BIAKI clears OIR REO.
This bit cannot be set by the user.
OIR REO has no meaning if the KXJI1-CA
is operating in standalone mode.

IOIR IE

OIR interrupt enable for J-l1 - When
set, the on-board'J-ll receives a level
5 interrupt request for vector 130 when
any of the following occur:
1. When BIAKI is asserted as part of
the Q-Sus interrupt handling
sequence.

2. When 'bit 14 (OIR REQ) is set and
then cleared before the Q-Bus
interrupt has been serviced.
3. When BINIT is asserted before the
Q-Bus interrupt has been serviced.

If IOIR IE is set, the arbiter causes
a local level 5 interrupt when it
acknowledges a OIR interrupt.
12

BQIR EN

OIR interrupt enable for Q-Bus master When set, enables the Q-Bus master to
participate in O-Bus interrupt handling.
When SOIR EN is set, the Q-Bus master
receives a level 4 interrupt request for
the vector in the OIR register when the
J-ll writes the vector. When cleared,
O-Bus interrupt requests are blocked
from reaching the Q-Bus master.

os RESET

O-Bus reset - Set when bit 10 <OS RESET
IE) is set and bit 6 KXJCSRJ (NMI EN) is
set and SINIT is asserted. When this bit
is set, an exception condition exists
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which is handled by the KXJ11-CA native
firmware.
10

OS RESET IE

Q-Bus reset interrupt enable - When set,
~nables the KXJl1-CA to detect the
assertion of the Q-Bus signal BINIT.
When set and when BINIT is asserted,
bit 11 <OS RESET) is set. When cleared,
the KXJI1-CA is prevented from responding
to the assertion of BINIT.

BHALT

Bus halt - Set when bit 8 (BHALT IE) is
s:et and bi t 6 KXJCSRJ (NMI EN) is set
a:nd BHALT is asserted. When thls bit is
set, an exception condition exists which
is handled by the KXJ11-CA native
firmware.

BHALT IE

Bus halt interrupt enable - When set,
enables the KXJll-CA to detect the
assertion of the Q-Bus signal BHALT.
When set and when SHALT is asserted,
bit 9 (SHALT) is set. When cleared,
the KXJll-CA is prevented from
responding to the assertion of BHALT.

TPR RQST

TPR restart request - Set by a Q-Bus
write to TPRO when KXJCSRJ bit 6 (NMI
EN) is set. This indicates an exception
which is handled by the KXJll-CA native
firmware. The user can not set this bit
directly. Once TPR RQST is set,
sybsequent writes to TPRO do not cause
more exceptions. Cleared by the
KXJIl-CA native firmware when the
command has completed execution.

TPR EN

TPR enable - When set, allows the
contents of the TPR file to be
accessed from the Q-Bus. When
cleared, forces the Q-Bus to read
zeros from the TPR file (writes will
time out). All the TPRs except TPRO
are enabled and disabled by this bit.
TPRO is always accessible from the O-Bus.

5:3

IE<134>
IE<124>
IE<120>

TPR interrupt enables - Each bit
when set enables a level 5 interrupt
request to occur when a particular TPR
is written. IE<l34> controls interrupt
requests from TPR12 for vector 134.
IE<124> controls interrupt requests
from TPR8 for vector 124. IE<120>
controls interrupt requests from TPR4
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for vector 120. When a bit is cleared,
the corresponding interrupt request
is blocked.
2:0

RQ<134>
RQ<124t>
RQ<120>

request flags - Each bit when set
indicates that a particular TPR has
been written. RQ<134>, RQ<124>, and
RQ<120> corresponds to TPR12, TPR8,
and TPR4 respectively. If the
corresponding IE<134>, IE<124>, or
IE<120> bit is also set, a level 5
interrupt occurs when the TPR is
written.

TPR

3.2.8.5 KXJll
Control/Status
Register
E
(KXJCSRE) - Control/status
register E is a dummy register provided for software compatibility with th~
corresponding reserved register on the KXTlI-CA. This register can· be read
and written, but writes to it do not affect KXJll-CA operation and reads
always produce zeros. The address of KXJCSRE is 17777526.

3.2.8.6 KXJll Control/Status Register F (KXJCSRF) - KXJll Control/Status
Register F defines the lower limit of the shared memory space accessible to
the Q-Sus. The upper limit is defined by KXJll Control/Status Register H
(see Section x.x). This register is initialized to a value of 177600 upon
power-up.
ADDRESS: 17777534
t5

Figure x-x KXJll Control/Status Register F

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Sits

Name

Description

15:7

STA ADD

Starting address - Contains the most
sjgnificant nine bits of a Q-Bus starting
aadress. The starting address defines the
beginning of the shared memory space on
this board that is accessible to the
Q~Bus. STA ADD corresponds to BDAL<21:13>
at address time. These bits are read/write
and are unaffected by a hardware reset.
Not used (read as zeros)

6:0

3.2.8.7 KXJ11 Control/Status Register H (KlJCSRH) - KXJll Control/Status
Register" H defines the upper limit of the shared memory space accessible to .
the Q-Bus. The register also contains the number of blocks in this memory
space.
The lower limit is defined by KXJll Control/Status Register F (see
Section x.x). This register is initialized to a value of 177777 upon
power-up.
ADDRESS: 17777536
15

I : :

Figure x-x KXJll Control/Status Register H

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Bits

Name

Description

15:7

END ADD

Ending address - Contains the nine most
significant bits of a Q-Bus ending
address for this board's shared memory.
The ending address is defined as the
first address of the last SK block of
Q-Bus accessible shared memory (see
Section x.x for an example of the
use of END ADD). The KXJ11-CA compares
END ADD with addresses on the Q-Bus to
determine which Q-Bus addresses refer to
this board's shared memory. END ADD
corresponds to BDAL<21:l3> at address
time. These bits are read/write and are
unaffected by a hardware reset.
Not used (read/write)

5:0

NlJM SLIt

Number of blocks - Contains a value that
represents the number of S KB blocks
in the shared m~mory space accessible
to the Q-Bus. This value is derived from
the starting address of the Q-Bus shared
memory and the number of blocks to be
shared (see Section x.x). Since the
shared memory is 512 IUS, up to 64 S KB
blocks can be specified. These bits are
read/write and are unaffected by a
hardware reset.

3.2.S.8 KXJll Control/Status Register J (KXJCSRJ) - KXJl1 Control/Status
Register J (KXJCSRJ) enables and disables the non-maskable interrupts
(power fail, SINIT, SHALT, and TPRO writes).
KXJCSRJ also indicates
whether timeouts for DNA or bus-locked operations have occurred. KXJCSRJ
determines whether the baud rate for SLUl is under software control and
determines whether shared memory can be accessed from the Q-Bus. KXJCSRJ
also specifies parity characteristics for the on-board RAM. This register
is read/write and is cleared upon hardware or software reset.
ADDRESS: 17777540

Figure x-x KXJll Control/Status Register J
3-26

SACK
BAUD
Wh
TOUT
RATE
PAR
NMI
LOCK
as
EN
TOUT
ENS

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Name

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Description

15:8

Not used (read as zeros)

Not used (read/write)

NMI EN

Non-maskab1e interrupt enable - '
When written with a 1, enables
recognition of interrupts from the
following sources: power failures,
the assertion of BINIT.or BHALT,
and interrupts which result from
writing TPRO. When written with a
0, disables recognition of the
interrupts from the sources listed
previously.

SACK TOUT

SACK timeout - Set if a DNA request to
the Q-Bus is not granted in the
alotted time (approximately 140 us).
Writing a 1 has no effect on this bit.
This bit must be explicitly cleared by
writing a zero.

LOCK TOUT

Lock timeout - Set when a bus locked·
instruction (WRTLCK, TSTSET, or ASRB)
is executing locally and access to the
Q-Bus cannot be obtained in the alotted
time (approximately 140 us). Writing
a 1 has no effect on this bit. This bit
must be explicitly cleared by writing a
zero.

BAUD RATE

Baud rate - When set, the baud rate for
SLU1 is under software control according
to the value written to PB in the Console
Transmitter Status Register (XCSR). When
cleared, the baud rate is determined by
the SLUl baud rate jumpers.

QS ENS

Q-~us enable - When set, enables the
Q-Bus to access the KXJll-CA shared memory
that has been allocated to it. When
cleared, prevents Q-Bus access to the
shared memory.

WR PAR

Write parity - When set, generates wrong
parity on writes to the on-board RAM.

PAR ENS

Parity enable - When set, enables parity
errors to be detected. If a parity error
is detected, a non-maskable parity
interrupt occurs wi th an assoc iated vee-tor
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of 114. When cleared,
ignored.

3.2.9

pa~ity

errors are

Q-Bus Interrupt Register (QIR)

The Q-Bus Interrupt Register (QIR) is used by the KXJ11-CA to interrupt the
arbiter.
When the KXJl1-CA initiateS a Q-Bus interrupt, it loads an
interrupt vector into the Q-Bus Interrupt Register. This causes bit 14 in
KXJII-CA Control/Status Register 0 (.see Section x.x.x) to be set. It then
asserts BIRQ4 on the Q-Bus if bit 12 (BQIR EN) of Control/Status Register 0
is set. The KXJll-CA drives the contents of the orR register on the Q-Bus
if it receives BIARI and bit 12 of Control/Status Register D is set.
The
receipt of BIAKI clears bit 14 in KXJCSRD. This register is write-only and
is initialized to a value of 177777 upon power-up.

ADDRESS: 17777532
'5

I I I I I I I : : : :vec: : : I I
Figure x-x
Bits

Name

VEe

1:0

3.2.10

Description
Must be zero

15:10
9:2

Q-Bus Interrupt Register (QIR)

Vector - Contains the interrupt vector
used to service the KXJII-CA's interrupt
to the Q-Bus. These bits are not
affected by a hardware reset.
Must be zero

Maintenance Register

The Maintenance Register (Figure x-x) indicates which halt and power-up
options were selected by the user. It also indicates the status of the
O-Bus signal SPOKe This register is read-only and is unaffected by a
hardware reset.
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ADDRESS: 17777750

HLT

BPOK
PUP
MOOe

Figure x-x
Bits

Name

Maintenance Register
Description

15:8

Is 11110110

7:4

Is 0011, indicating the CPU code for
the KXJl1-CA.

HLT

Halt - When set, indicates that MlS
and Ml6 are not jumpered' together. When
cleared, indicates that M15 and Ml6 are
jumpered together. The M15 - M16 jumper
determines what action the KXJl1-CA will
take if a HALT instruction is, executed
in kernel mode (see Section x.x.x).

PUP MODE

Power-up mode - When set, indicates that
MI6 and M17 are not jumpered together.
When cleared, indicates that M16 and M17
ate jumpered together. The M16 - M17
jumper determines what action the
KXJ11-CA will take when the board is
powered up or reset (see Section x.x.x).
Must be 1

3.2.11

BPOK

BPOK status - Set when the Q-Bus
signal BPOK is asserted.

:Program Interrupt Request (PIRQ) Register

The Program Interrupt Request (PIRQ) Register provides seven levels of
software interrupt capability for the on board J-11 microprocessor. An
lterrup't is queued by sett ing one of bi ts <15: 9>, which correspond 'to
J.nterrupt priority levels 7 through 1 (respectively). Bits <7:5> and <3:1>
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are set by the on board J-ll to the encoded value of the highest pending
request.
When the interrupt request is granted, the J-11 traps th,rough
location 240 in kernel I space. The user's interrupt service routine must
clear the appropriate PIRQ bit before exiting. The format of the PIRQ is
shown in Figure x-x:

I..ul ..•-I". sI..•-I "·,1,,· 21 ..•,I oI
I
=oJ
[

.IQUIST LIVIU

'AtO'UTY INeOOEO VALUI 0' "TS <15:0>

Figure x-x
Bits <15:9> can be read or written.
The other bits are read as zeros.

3.2.12

PIRQ Register
Bits <7:5> and

<3:1>

are

read-only.

CPU Error Register

The CPU Error Register (Figure x-x) identifies the source of a trap through
location 4. Refer to the J-ll User's Guide for details on the handling of
the traps. This register is read/write.

ADDRESS: 17777766
02

ILL
HLT

Figure x-x
Bits

Name

YEL

NXM

STA
ADO

I/O

ERR

TOT

RED
STA

CPU Error Register

Description
Not used (read as zeros)

15:8
7

ILL HLT

Illegal halt - Set when execution of a
HALT instruction is attempted in user
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or supervisor mode, or in kernel mode
when M1S and M16 are jumpered together.
6

ADD ERR

Address error - Set when a word access
is made to an odd byte address, or when
an instruction fetch from a J-l1
internal register is attempted.

NXM

Non-existent memory - Set when reference
is made to a non-existent memory address.

I/O TOT

I/O bus' timeout - Set when reference is
made to a non-existent I/O page address.

YEL STA

Yellow stack violation - Set when a yellow
zone stack overflow occurs.

RED STA

Red stack trap - Set when a red stack trap
occurs.

1:0

3.2.13

Unused (read as zeros)

Processor Status Word (PSW)

be Processor Status Word (Figure x-x) contains:
the current and previous
operational modes, the J-11 general-purpose register set being used, t·he
current priority level, condition codes, and the trace trap bit. All bits
in this register are read/write except bits <10:9> which are read-only (and
not used).

ADDRESS: 17777776
15

Figure x-x

Processor Status Word (PSW)

Bits

Name

Description

15:14

Current mode - Displays the current
operational mode:
CM

3-31

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00
01
10
11
13:12

PM··

10:8
7:5

Kernel
Supervisor
Illegal
User

Previous mode - Displays the previous
operational mode using the same encoding
as for Of.
Register set - When set, RO' through R5'
(set 1) of the J-l1 general-purpose
registers is used. When cleared, RO
through RS (set 0) is used.
Not used (read as zeros)

PRI

Priority - Determines the hardware
interrupt priority level:
PRI
III
110
101
100
011
010
001
000

Priority Level
7
6
5
4
3
2
1
0

Trace trap - When set, causes a trap to
location 14 at the end of the current
instruction. When cleared, disables
the trace trap function.

N bit - Set if the result of the
previous instruction was negative.

Z bit - Set if the result of the
previous instruction was zero.

V bit - Set if the previous instructionresulted in an arithmetic overflow.

t bit - Set if the previous instruction

3.2.14

resulted in a carry of its most
significant bit.

Console Asynchronous Serial I/O

The console asynchronous serial line interface (based on the DLART chip)
provides program or jumper selectable baud rates (300 to 38.4K baud),
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eal-ti:me clock outputs (800 HZ, 60 Hz, and 50 Hz), 8 data bits, no parity,
one st'op bit, break detection which causes the J-l1 to enter ODT if the
BREAK enable jumper (M12-M13) is installed. A break detect bit appears in
the RBUF of a UART during the time a BREAK condition exists on the line.
Also fe,atured are RS422/RS423/RS232-C EIA interfaces, la-pin interface
connector, optional EIA to 20ma conversion utilizing the OLVll-KA. There
is no reader run pulse generation, or 110 baud rate input.

3.2.15

Synchronous/Asynchronous Serial I/O

A two-channel multiprotocol serial communications controller (uPD7201)
supports asynchronous, character-oriented synchronous, and bit-oriented
synchronous protocols, programma~le character size, parity, CRC generation
and chE!cking, BREAK detect, framing error detection, automatic detection
and genE!ration of SYNC characters, auto hunt, and external or internal
programmable baud rates from 110 to 76.8K baud. The primary channel (SLU2
channel A) is provided with type SR (send-receive) RS449(CCITT) electrical.
interface and modem control lines. The secondary channel (SLU2 channel B)
is a synchronous/asynchronous secondary channel with type DT (data ~d
timing only) RS449 (CCITT) electrical interface. In addition this second
channel can be operated in a 16 node party-line configuration.
~~

.2.16

Parallel I/O

Twenty programmable parallel I/O lines are provided, with programmable
direction control of IEEE-488 electrical standard compliant input buffers
and either passive pull-up drivers or TTL compatible drivers.
There are
three parallel I/O ports: two 8~bit data ports and one 4-bit control port.
Features include three interrupt requests and handshake control for either
polled,
interrupt
conditional control, three-wire, or bidirectional
operation. Three programmable l6-bit timers are provided with either
internal control and interrupt or external buffered control lines.

3.2.17

-12V Charge Pump

Local serial I/O drivers and receivers require a negative 12V bias.
This
is provided by an on board charge pump operating at 614.4 KHz. The charge
pump is :zener diode regulated.
>

3.3

Q-BtJS INTERFACE

The Q-Bu:~ interface can be considered from two perspectives: from the
perspective of the Q-Bus and from. the perspective of the local KXJll-CA
bus. Th~!re are two distinct portions to the KXJll-CA that may be
-~rtitioned
in any way the user sees fit. The I/O page addressable TPR
.le's address is determined by the base address and the CPU IO switch
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setting while the addresses in shared memory can be defined as the user
wishes. From the Q-Bus, the KXJll-CA looks like a 16 word I/O page
addressable register file that may be logically partitioned into a transmit
status and command section and a receive command and status section.
The
file is intended to provide a control communication path. The Q-Bus master
can read and writ&· f.rom/to· any of three defined command registers and read
status from any of three associated read only status registers. All other
file words may be written or read. TPR4, TPR8, and TPR12 when written from
the Q-Bus, can either flag the J-ll through KXJCSRD or interrupt the J-ll
with unique level five interrupts. In addition, when the first file word
is written a nonmaskable J-ll restart trap is generated. This is intended
to be a priority command channel.
The Q-Bus sends messages or asks for status thru the TPR file.
The J-ll
can respond either by directly reading or writing the file or by invoking
the data path controller (DTC) to move data across the bus interface and
signal the arbiter when done. The local processor can signal the Q-Bus
arbiter at will by writing into its Q-Bus interrupt register (QIR) to
generate a level 4 interrupt to the Q-Bus arbiter, or for polled operat.ions
by writing into the two port register.
The KXJ11-CA DMA controller can address any portion of the Q-Bus 22-bit~~
address space. Shared memory is visible from the local bus as a contigious
physical memory with an address range of 00000000 - 01777777 (512 KB). All
512 KB can be shared. The addressing from the Q-Bus is determined by the
host and stored in two internal registers, KXJCSRF and KXJCSRH.
These
registers contain the starting address (KXJCSRF) and a value for the number
of blocks and the ending address (KXJCSRH). Shared ~emory is enabled and
disabled by KXJCSRJ. The locally mapped Q-Bus memory may be allocated in 8
KB contigious increments in any non I/O address range.
The range sele'cted
must also be on 8 KB boundaries which allows a user a total of sixty-four 8
KB pages. The shared memory area is located at the top of local RAM.

3.4

TWO-PORT REGISTERS AND COMMUNICATION WITH THE ARBITER

3.5

KXJl1-CA INTERRUPTS

There are three general categories of interrupts which involve the
KXJll-CA:
interrupts from the Q-Bus·to the KXJll-CA, interrupts from the
KXJl1-CA to the Q-Bus, and local interrupts by on-board KXJII-CA I/O
devices.
This section describes the KXJll-CA's role in each type of
interrupt. Special interrupt handling by the firmware is discussed in
Sect ion Jt-. x.

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:Interrupts From The Q-Bus To The KXJ11-CA

AQ-Bus device can interrupt the KXJll-CA by writing TPR4, TRPS, or TPR12.
If the TPRs and the TPR interrupts are enabled (as determined by bits 6:3
of KXJCSRD), a write to any of these three registers from the Q-Bus causes
a level 5 interrupt.
The vectors associated with the i~terrupts are
located at logical,· addresses 120, 124, and 134 respectively ln kernel I
space.
The sequence of events during a Q-Bus interrupt is illustrated in
Figure It-X.
Q-EJus Device
or Arbiter

KXJ11-CA

~--.--~--------~-----~------------~--~-------------------~-----~--

Wri.tes TPR4, TPR8,
or TPR12

If TPRs and TPR interrupts are enabled,
handles a levelS interrupt with the
following vector:
TPR
TPR4
TPR8
TPR12

Vector
120
124
134

Figure x-x Interrupts from the Q-Bus to the KXJlI-CA

3.5.2

Interrupts From The KXJ11-CA To The Q-Bus

The KXJll-CA can interrupt device:s on the Q-Bus (including the arbi ter) vi a
a register in the on-board GAP gate array (DC7037B) called the OIR or Q-Bus
Interrupt Register. The format of the OIR is described in Section x.x.
In order for the KXJ11-CA to interrupt the Q-Bus via the OIR, bit 12 of
(BQIREN) must 'first be set. If this bit is cleared, interrupts
from the KXJll-CA cannot be posted.

KXJCSRD

If KXJCS1u) bit 12 is set, a write to the OIR sets KXJCSRD bit 14 (QIRRQ)
and causes the Q-Bus signal BIRQ4 to be asserted, generating a le~l 4
interrupt on the Q-Bus. At some later time, a Q-Bus device (or arbiter>
asserts the signal BIAKI to acknowledge the interrupt and reads the
contents of the QIR for the appropriate vector.
The assertion of BIAItI (acknowledgement of interrupt) clears KXJCSRD bit 14
and if bit 13 is set posts a levelS local interrupt request with a vector
of 130. The user must ensure that there is a vector at 130 that points to
a routine that handles the interrupt. The routine handles the interrupt
and the operation is complete.
Figure x-x summarizes the sequence of
events.
Q-Bus Device
or Arbiter

KXJ11-CA
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-------~~~----------~-~----~-~-~-----~----~-------------------~---

Wri tes OIR wi th vector when KXJCSRD<12>'
is set
Sets KXJCSRD<14>
Asserts BIRQ4

Asserts BIAKI"
Reads QIR
Handles a local level 3 interrupt with
a vector of 130
Figure x-x

Interrupts from the KXJll-CA to the Q-Bus

3.5.3 . Local Interrupts From On-Board Devices

The KXJII-CA on-board devices that can post local interrupts to the.
on-board J-l1 include:
the data transfer controller (OTC), the parallel
I/O port (PIO), the console serial line (SLUl), the multiprotocol seri~l
controller (SLU2), the SLU2 counter/timer, the real-time clock (RTe), TPR4,
TPR8, TPR12, and the QIR.
...
Interrupts from local devices are all handled in the same general way:
1.

The local device posts an interrupt to the on-board J-ll
J-ll's IRQ lines,

via

the

The J-l1 performs an interrupt acknowledge cycle and
vector which points to an interrupt service routine,

reads

The routine handles the interrupt, and

Operation resumes.

The DTC and the PIa share a common interrupt request line. The OTC has the
higher priority of the two devices (these two devices are daisy-chained)
and allows the PIa to acknowledge an interrupt only if there are no DTC
interrupts pending.
Table x-x is a summary of all the interrupts handled locally by the
KXJl1-CA, their relative priorities, and the vectors associated with each.
Within a priority level, the interrupt with highest priority is listed
first.
Table x-x
Priority

Summary of KXJl1-CA Local Interrupts
Interrupt Type

Vector(s)

---~--------~-------~-----------~------------~~---------~-------

Programmable
6
6
5

PIRQ
Real-Time Clock
SLU2 Counter/Timer
Interrupt from Q-Bus

240
100

104
120

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5
5
5
4

4
4
4
4

124
130
134
224,230*
200,204,210*

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Interrupt from Q-Bus
Interrupt to Q-Bus (via QIR)
Interrupt from Q-Bus
DTC Interrupt
PIO/PIO Timer Interrupt
Console (SLU1) Receiver
Console (SLU1) Transmitter
MPSC (SLU2) Communication

60
64

*Default values. May be changed by the user.
The vectors for DTC interrupts and PIO interrupts shown in Table x-x are
·thedefaults set by the native firmware. These vectors are programmable.

3.6

SPECIAL INTERRUPT HANDLING

The KXJJ.1-CA native fir.mware is designed to handle four types of special
interrupts.
A special interrupt occurs when the exception enable bit
(KXJCSRJ bit 6) is set and:
1.

A command is issued (TPRO is written), or

A power fail occurs (BPOK is deasserted), or

A Q-BU5 halt occurs (BHALT is asserted)
enable bit (KXJCSRD bit 8) is set, or

A Q-Bus initialization is performed (BINIT is asserted)
corresponding enable bit (KXJCSRD bit 10) is set.

and

the

corresponding
and

the

During an special interrupt, the KXJl1-CA forces the PC to 173004, the PSW
to 340, clears bit 6 of KXJCSRJ (NMI EN), and begins to execute code.
Typically, the KXJII-CA firmware handles the special interrupt.
If the
user ha:s his own code for special interrupt handling, he should make sure
that the entry point for this code is at physica~ location 173004.
The
firmware handles a special interrupt as follows:
1.

TPRl bit I selects either user code or firmware to handle the
exception.
If TPRl bit 1 a 1, control is passed to user code via
locations 24 and 26 and user code handles the exception. If TPRl
bi t I a 0, ,control is retained by the KXJll-CA firmware which
handles the exception. The steps that follow assume the KXJll-CA
firmware handles the exception.

The cause of the exception is determined according to the contents
of KXJCSRD.

It the exception is caused by a power failure, the fi~are
through locations 24 and 26 and handles it.

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If the exception is caused by the assertion of BHALT,

If the exception is caused by the assertion of BINIT, a RESET
instruction is executed.
The firmware then jumps to location
173000 which is the power-up ("cold") restart location.

If the exception is caused by the issuance of a command, the
firmware determines which command it is by looking at TPRO and
then executes the command. The arbiter may need to load command
parameters into TPR2 and TPR3 before it issues the command.

After the exception is handled, the firmware sets the restart
enable bit (bit 6 of KXJCSRJ) to allow other exceptions to be
handled if need be.

KXJll-CA RESETS

There are two ways in which the ~ll-CA can be reset or reinitialized:
1.

By executing a RESET
reset.

instruction.

By the assertion of the local power-up signal PUP.
a hardware reset.

This

called

software

This is called

The sections that follow explain the causes and effects of the two types of
resets.

3.7.1

Software Reset

When a RESET instruction is executed by the on-board J-ll, the various
components of the KXJ11-CA are affected as summarized in Table x-x.
Table x-x
Component
SLUl (DLART)

PIO

KXJll-CA Software Reset
Effect
, The DLART input INIT is asserted, which
clears interrupt enables and clears bits
2 and 0 of the SLUts XCSR. Refer to the
DLART Data Sheet for details of DLART
behavior when INIT is as·serted.
The PIO inputs ZDS and ZAS are asserted
which resets the PIO. Refer to the PIa
Data Sheet for details of PIO behavior
when-ZDS and ZAS are asserted.
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DTC

The DTC inputs ZDS and ZAS are asserted
which resets the DTC. Refer to the DTC
Data Sheet for details of orc behavior
when ZDS and ZAS are asserted.

J-ll

Memory management is disabled and the
J-ll executes a RESET instruction.
Refer to the J-ll Data Sheet for details
of J-ll behavior when RESET is executed.

SLU2 (MPSC)

Unaffected.

SLU2 Timers

Unaffected.

RTC

Interrupts disabled (KXJCSRA<6> cleared)

KXJCSRD

Unaffected.

KXJCSRJ

Cleared. This disables shared memory and
special interrupts. It has other effects
as described in Section x.x.

Other CSRs

Unaffected.

Boot/Self test
Switch

No effect on software resets.

LEDs

Unaffected.

ID Switch

No effect on software resets.

Pending Interrupts

Cleared.

Hardware Reset

3.7.2

Hardware resets are caused by the assertion of the local power-up
PUP. A hardware reset occurs when any of the following occurs:

signal

If the KXJll-~ is in standalone mode (as determined by the
setting of the IO switch), a hardware reset occurs when an
on-board wake-up circu~t detects the presence of +5V DC power.

If the KXJII-CA is not in standalone mode (as determined by the
setting of the IO switch), a hardware reset occurs when the
on-board wake-up circuit detects the assertion of the Q-Bus signal
SDeOK.
A hardware reset is also caused by writing TPRO bit 14
from the Q-Bus.

During a hardware reset, the various
-efected as summarized in Table x~x.
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Table x-x

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KXJll-CA Hardware Reset

Component

Effect

SLUl (DLART)

The DLART input TEST is asserted
which resets the DLART. Refer to the
DLART Data Sheet for details of DLART
behavior when TEST is asserted.

PIO

The PIO inputs ZOS and ZAS are asserted
which resets the PIO. Refer to the PIO
Data Sheet for details of PIO behavior
when ZOS and ZAS are asserted.

The DTC inputs ZDS and ZAS are asserted
which resets the DTC. Refer to the DTC
Data Sheet for details of DTC behavior
when ZDS and ZAS are asserted.

J-ll

The J-ll input INIT is asserted. Refer
to the J-ll Data Sheet for details of
J-ll behavior when INIT is asserted.
Jumper M17-M16 determines whether control
is passed to the firmware (location
173000) or to ODT after power-up is
complete.

SLU2 (MPSC)

The MPSC input RESET is asserted. Refer
to the MPSC Data Sheet for details of
MPSC behavior when RESET is asserted.

SLU2 Timers

Initialize themselves upon power-up.

RTC

Interrupts disabled (KXJCSRA<6> cleared)

KXJCSRA
KXJCSRB
KXJCSRC
KXJCSRD
KXJCSRE
KXJCSRJ

Initialized to power-up values. See
specific register descriptions for
details. All writeable bits are cleared.

KXJCSRF
KXJCSRH

Contents are unpredicable.

Boot/Self test
Switch
.

If firmware is executed upon power-up,
this switch specifies the function
performed.

LEOs

All on.

10 Switch

Value is loaded into KXJCSRC.

Pending Interrupts

Cleared.
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MEMORY MANAGEMENT ARCH I TEC'l'URE

NOTE
It is assumed the reader is familiar with PDP-ll memory
management
concepts.
For further details on memory
management, refer to Chapter 4 of the DCJll Microprocessor
User's Guide (EK-DCJII-UG-PRE).
The KXJll-CA implements the fullPDP-ll memory management and protection
architecture with its extensions for extended direct addressing. The
KXJ1I-CA memory management regi$ters include Page Address Registers (PARs),
page Descriptor Registers (PDRS);, and Memory Management Registers 0 through
3 (MMRO - MMR3). MMRO through MMR3 are contained in the on-board J-ll
microprocessor.
The PARs and PDRs are located in physical memory. These
registers are described in the sections that follow.
I

3.8.1

:Page Address Registers (PARs')

There are 48 PARs, eight for each of the following:
kernel I space,
supervi.sor I space, user I space, kernel D space, supervisor 0 space, and
user D .space. Each PAR contains a page address field (PAF) which specifies
:he starting address of a page as a block number in physical memory.
NOTE

Kernel I space and D sp~ce PAR7 is mapped to the I/O
by the firmware. This mapping must not be altered.

page

The format of a PAR is shown in Figure x-x.

MA·17127

Figure x-x

Page Address Register (PAR)

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Page Descriptor Registers (PDRs)

There are 48 PDRs, eight for each of the following:
kernel I space,
supervisor I space, user I space, kernel D space, supervisor D space, and
user D space. Each PDR contains information on expansi.on direction,' page
length, and access'· control. The format of a PDR is shown in Figure x-x.

...........:

r""~
~tmt

Name

PLF

07
0

~pwl 0

I I I AfF I
0

00
0

Page Descriptor Register (PDR)
Description

Page length field - Specifies the block
number, which defines the page boundary
(see bit 3). The block number of the
virtual address is compared with PLF to
detect length errors. An error occurs
when expanding upwards if the block
number is greater than PLF and when
expanding downwards if the block number
is less than PLF.
Not used (read as zero)

Not used (read/write)

14:8

: : :PLF: : :
Figure x-x

Bits

Page written - When set, this page has
been modified since it was loaded into
memory. Cleared when the PAR or PDR of
,this page is written.
Not used (read as zeros)

5:4
3

Expansion direction - When set, this
page expands downwards from block number
127 to include blocks with lower
addresses. When cleared, this page
expands upwards from block number 0 to
include blocks with higher addresses.

2:1

ACF

Access control field - Contains the
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access code for this page.
ACr
00
01
10
11

Not used (read as zero)

·0

3.8.3

Access
Non-resident - abort all accesses
Read only - abort on write attempt
Not used - abort all accesses
Read/write access

Memory Management Register

0 (MMRO)

MMRO contains status and control

unit.

MMRO.

This

information for the memory management
is read-only. Figure x-x illustrates the format of

ADDRass: 17777572
15

ABO NRE

ABO ACV

ABO PLE

1/0 SPC

ENS REL

Figure x-x

Memory Management Register

Bits

Name

Description

ABO NO

Abort non-resident - Set when an access
is made to a page with an access control
field key of 0 or 2. Also set by
attempting to use memory relocation with
a current processor mode (PS<15:14» of
2 (illegal). ABO NRE is set when
. PAG MOD equals 2.

ABO PLE .

Abort page length - Set when an access
is made to a page with a block number
o'uts ide the range spec i f i ed by the
page's PDR. Also set by attempting to
use memory relocation with a current
processor mode (PS<lS: 14»' of 2
(illegal).

ABO ACV

Abort access violation - Set when
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attempting to write a read-only page,
i.e., the access control field equals
1.
Not used (read as zeros)

12:7
6:5

PAG MOD

Page mode - Indicates the CPU mode
associated with the page causing an

abort.

PAG MOD
00
01
10

Mode
Kernel.
Supervisor
Illegal Mode
User

If an illegal mode is specified, ABO
is set.

NRE
4

I/O SPC

Page address space - When set, a 0 space"
mapping operation was attempted when an
abort occurred. When cleared, an I space
mapping-operation was attempted when an
abort occurred.

3:1

PAG NOM

Page number - Contains the page number
of a reference causing a memory
management abort.

ENB REL

Enable relocation - When set, memory
management is enabled and address
relocation occurs. When cleared, memory
management is disabled and addresses are
neither relocated nor protected. Cleared
by RESET instruction.

3.8.4

Memory Management Register

1 (MMR1)

MMRl records the autoincrementing or autodecrementing of any general
purpose register (GPR) during an instruction, including references through
the program counter (PC). This. register is cleared at the beginning of an
instruction.
Whenever a GPR is autoincremented or autodecremented, the
register number and amount (in 2's complement notation) by which the
register was modified is written into MMR1.
The low byte of MMRl is
written first. The format of MMRl is shown in Figure x-x.

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()t

?f
,..

AMOU~TCHANQiO

/2'S COM'I.IMINTJ

Figure x-x

3.8.5

REGISTIR
HUMSI"

Memory M:anagement Register

Memory Management Register

...

AMOUNT CHANG!O
/2"$ COMPLIMENT)

fIIlOISTIR
NUMS.R

"-.M

1 (MMRl)

2 (MMR2)

a
This ~~

MMR2 is also called the virtual program counter (VPC) and is loadea with

16-bit virtual address
register is read-only.

3.8.6

at the beginning of each instruction fetch.

Memory Management Register

3 (MMR3)

MMR3 enables and disables data space mapping for kernel, user, and
supervisor modes. It also controls I/O mapping, 18-bit/22-bit mapping, and
whether requests for Call to Supervisor Mode instruction are enabled. This
register is read/write and is cleared upon a hardware reset.

ADDRESS: 17772516

ENSI/O

ENS CSM

ENS 22S

Bits

Figure x-x

Memory Management Register

Name

Description

3 (MMR3)

Not used (read as zeros)
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Not used (read/write)

ENS 22B

Enable 22-bit mapping - When set and
when memory management is enabled <i.e.,
bit 0 of MMRO is set), 22-bit mapping
is used. When cleared and when memory
management is enabled, lS-bit mapping
is used. This bit has no effect when
memory management is disabled.

ENB CSM

Enable Call to Supervisor Mode - When
set, allows a Call to Supervisor (CSM)
instruction to execute. When cleared,
the execution of a CSM instruction
causes a trap through location 10 in
kernel I space.

2:0

MODE

Mode bits - enable and disable
kernel, supervisor, and user 0 space
as shown:
Bit
MODE<2>
0
MODE<2>
1
MODE<l> :II 0
MODE<l>
1
MODE<O> • 0
MODE<O> • 1
:I
:I

3.9

Meaning
Disable kernel D space
Enable kernel 0 space
Disable supervisor 0 space
Enable supervisor 0 space
Disable user 0 space
Enable user D space

SHARED MEMORY

The KXJll-CA contains 512 KB of on-board RAM. The RAM can be configured as
wshared memory" which can be accessed by devices on the Q-Bus as well as
the on-board J-ll microprocessor. Shared memory could be used for example
in an application where the arbiter needs to access RAM that is read or
written locally.
Shared memory can be configured under software control by loading KXJll-CA
Control/Status Registers KXJCSRF and KXJCSRH (Sections x.x and x.x) and
enabled by setting KXJCSRJ<2>. ,KXJCSRF and KXJCSRH contain values which
specify the starting address, ending address, and number of blocks for the
shared memory area. This section explains how the user can derive the
values he needs to load into KXJCSRF and KXJCSRH once he has determined
which Q-Bus addresses are to be associated with shared memory. The section
that follows explains the mechanics of how the registers are loaded by the
arbiter or by the on-board J-ll.
When configuring shared memory, the user must ensure that there are
overlapping Q-Bus addresses. That is, Q-Bus addresses must be unique.

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Shared Memory Organization

Shared memory consists of one or more 8 KB blocks of RAM. Since there is
512 K8 of RAM on the KXJll-CA" the maximum number of shared memory blocks
is 64. Each block must start on an 8 KB boundary. On the KXJ11-CA, the
last block is the highest 8 KB Of RAM (1777777 - 176000~), the next to last
block is the next highest 8 KB (1757777 - 1740000), and so on. All blocks
of shared memory are contiguous. The shared memory space is located at the
top of local RAM. The local stareing address is (2000000 - N*20000) octal
where N is the number of blocks.
The algorithms for determining the contents of KXJCSRF and KXJCSRH
follows:
CSRF:

are

determined

and

(Q-Bus starting address/laO) octal

CSRH:

The sections that follow illustrate how these
used.

3.9.2

values

are

Defining One Block Of Shared Memory

Suppose the user wants to define one 8 KB block of addresses as
The following example illustrates how this would be done.

~emory.

shared

In this example, the user wants to define one 8 KB block of shared memory
starting at Q-Bus address 100000. In this case (Figure x-x), addresses
100000 through 117777 on the Q-Bus correspond to KXJ11-CA shared memory
addresses 1760000 through 1777777.
What values do we need to load into
KXJCSRF and KXJSCRH?

a·sus

KXJ11·AA
1777776 .

17777776

8K
1 - - - - - - 1 1760000

117776
8K
100000

0"'-_ _ __

Figure x-x

"-_ _ _.... 0

Defining One Block of Shared Memory
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The value for the ·starting address" that we need to load into KXJCSRF is
obtained by shifting the starting Q-Bus address right six bits. Figure x-x
shows the relationship between KXJCSRP and the 22-bit Q-Sus address.
Plugging in our Q-Bus address of 100000 (octal), we see that 1000 (octal)
should be loadedin·to KXJCSRF • Bits 6: a of KXJCSRF· are not used and read
as zeros •

6.1 0

~~ 121 1 20 1'9 1"8 117 1'6 1'5 1'4 1'3

. sr1rt'TINC.

Figure x-x

Control Register Bits/Q-Bus Address Relationship

The value for the "ending address" that we need to load into KXJCSRH bits
15:7 (END ADD) is obtained by taking the first CQ-Bus) address in the last
block and shifting it right six bits. In this case, we are working with
only one block so the first block is the last block. The first address in
the block shifted right thirteen bits yields 000000100 for bits 15:7.
The value for the "number of blocks" that we need to load into KXJCSRH bits
5:0 is obtained by extracting bits 18:13 of the Q-Bus starting address,
adding the number of blocks, and two's complementing the result:
Q-Bus address 100000 bits 18:13
Add number of blocks

000100
1
000101

Negate

111011

The value 111011 is loaded into bits 5:0
interprets this value as meaning one block.

3~9.3

KXJCSRH.

The

KXJll-CA

Defining Two Blocks Of Shared Memory

Suppose the user wants to define two blocks of shared memory. Assume tha~
the range of Q-Bus addresses asaigned to shared memory in this case is
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100000 through 137777. On the KXJ11-CA, the corresponding two blocks are
contiguous in RAM and reside at addresses 1740000 through 1777776. The
relationship between the Q-Bus addresses and the KXJll-CA addresses is
i llustr'ated in Figure x-x.
~ 7777776

Q·BUS

KXJ11·AA

8K
8K
~37776

8K
120000 '

177776

100000

....._ _ _... 0

0 ...._ _ _...

Figure x-x

Defining Two Blocks of Shared Memory

rind the correct values to load into KXJCSRF and KXJCSRH.
The value for the "starting address" that we need to load into KXJCSRF is
obtained by shifting the starting Q-Bus address right six bits. This
yields 1000 (octal) for KXJCSRF. Bits 6:0 of KXJCSRF are not used and read
as zero.s.
The value fqr the "ending address" that we need to load into KXJCSRH bits
15:7 tEND ADD) is obtained by taking the first (Q-Bus) address in the last
block and shifting it right six bits. In this case, the first address of
the last block is 120000.
Shifting the address right six bits yields
000000101 for bits 15:7.
The value for the "number of blocks" that we need to load into KXJCSRH bits
5:0 is obtained by extracting bits 18:13 of the Q-Bus starting address,
adding ,the number of b.locks, and negat ing the resul t:
Q-Bus address 100000 bits 18:13
Add number of blocks

000100
10
000110

Negate

111010

The value 111010 is loaded in:to bi ts 5: a of
interpr1ets this value as meaning two blocks.

3-49

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3.9.4

Defining 64 Blocks Of Shared Memory

Suppose the user wants to define all 64 blocks of RAM as shared memory.
Assume that the range of Q-Bus addresses assigned to shared memory in this
case is 1000000 through 2777776. On the KXJll-CA, the corresponding 'blocks
are contiguous in, RAM and reside at addresses 0 through 1777776. The
relationship between the Q-Bus addresses and the KXJll-CA addresses is
illustrated in Figure x-x:

1..

~.,

KXJl1·AA

1777778

2777776

512K

S12K

1000000

Figure x-x

o
.. 100

Defining 64 Blocks of Shared Memory

The correct values to load i'nto lOCJCSRF and KXJCSRH are:
KXJCSRF • 10000 (octal)
Since the first (Q-Bus) address of the last block is 2760000,
KXJCSRH bits 15:7 • 001011111 '
KXJCSRH bits 5:0 are determined as follows:
Q-Bus address 1000000 bits 18:13
Add number of blocks

100000
100000
000000
000000

Negate
Carries are ignored.

3.9.5

E:nabling And Disabling Shared Memory

Qhared m1emory can be enabled and disabled by ei ther the on-board J-11 or by
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an arbiter command.
When shared memory is enabled, the relationship
between Q-Bus addresses and KXJll-CA RAM addresses is defined by the values
in KXJCSRF and KXJCSRH (see Section x.x). This section describes how the
on-board J-ll and arbiter can enable and disable shared memory_
Once KXJCSRH and KXJCSRF are set up, the on-board J-ll enables and disables
shared memory simply by writing bit 2 of KXJCSRJ. When this bit is set,
shared memory is enabled. When the bit is cleared, shared memory is
disabled. The shared memory ~onfiguration values might be known at startup
time or they can be passed from the arbiter to the KXJ1l-CA via one of the
TPR user communication channels.
When the arbiter wants to enable or disable shared memory via the firmware,
the process is somewhat more involved.
To enable shared memory, the
following events occur:
1.

The arbiter determines that the KXJll-CA is ready to receive a
This occurs when TPR1<2:0> ~ 100, and TPRO<15:0> ~ O.
command.
This is sometimes called the "waiting for command" state.

The arbiter writes bits 21:13 of the Q-Bus starting
TPR2<8:0> and writes zeros into TPR2<15:9>.

The arbi ter wri tes the number of blocks of. shared memory minus, one
into TPR3<5:0>. For example, TPR3<5:0> • 000000 for one block of
shared memory, TPR3<5:0> • 000001 for two blocks of shared memory,
and so on. The arbiter writes zeros into TPR<l5:~>.

The arbiter sets TPRO bit 6. Only bit 6 should be set.
If the
arbiter were to set more than one bit at a time in TPRO, an error
would result (and would be recorded in TPR1).
Setting bit 6
causes the KXJ11-CA firmware to configure and enable shared
memory_ The data in TPR2 and TPR3 are translated into values
which are loaded into KXJCSRF and KXJCSRH and bit 2 of KXJCSRJ is
set.

After shared memory is configured and enabled, the KXJ1l-CA clears
TPRO and sets TPR1<2:0> • 100. This puts the KXJ11-CA back into
the "waiting for command" state.

address

into

NOTE
A local reset or a Q-Bus OOT GO command will disable shared
memory because it clears KXJCSRJ bit 2 but will leave the
contents of KXJCSRF and KXJCSRH unaffected.
To disable shared memory, the following events occur:
1.

The arbiter determines that the KXJll-CA is ready to receive a
This occurs when the KXJll-CA is in the "waiting for
command.
command" state.

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PRELIMINARY

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The arbiter sets TPRO bit 8. Only bit 8 should be set.
If the
arbiter were to set more than one bit at a time in TPRO, an error
would result (and would be recorded in TPR1).

The KXJll-CA clears bit 2 of KXJCSRJ, disabling shared memory.

The KXJll~CA clears TPRO and sets TPR1<2:0> • 100. This puts
KXJll-CA back into the "waiting for command" state.

the

Shared Memory Considerations

When designing an application, the user should note the
following
circumstances
under
which
the
use of shared memory could yield
unpredictable results.
The KXJll-CA is designed for use in memory architectures which are
non-cached. Arbiters with cache memory (such as the KDJll) must disable orbypass the cache when accessing shared memory.
The KXJIl-CA has no
mechanism for updating the arbiter's cache when cached shar~d memory
locations are altered by the on-board J-ll or DMA controller.
Warning~;

for locked instructions (synchronization) go here.

3-52

CHAPTER 4
DMA TRANSFER CONTROLLER (DTC)

4.1

OVERVIEW

The DTC is designed around the AmZa016 chip.
For details on the
operation of the AmZ80l6, refer to the AmZ8016 DMA Transfer Controller
Data Sheet included as part of this documentation package.
The
information that follows is of a summary nature and describes the DTCfunctions implemented on the KXJII-CA.
The DTC can
addresses:

perform

DMA

transfers

between

any

the

following .. "

local address to a local address

A local address to a Q-Bus address

A Q-Bus address to a local address

A Q-Bus address to a Q-Bus address

To/From channel A of the multiprotocol SLU via DMA channel I

To/From channel B of the multiprotocol SLU via DMA channel 0

To/Prom the PIO chip port A via DMA channel I

Word and byte transfers are supported locally.
Only word transfers
are supported across the Q-bus. Note that in byte mode the addressing
is the inverse of of the PDP-II addressing scheme. For example, DTC
address 1000 corresponds to PDP-II address 1001 and DTC address 1001
corresponds to PDP-ll address lOOO.
The operations of the OTC are controlled by several
internal
registers.
The OTC can load these registers directly from memory
thereby minimizing the amount of processor intervention necessary to
perform a DMA transaction. The area of memory where the parameters
for the DTC are stored is referred to as the chain table.
The local
J-ll microprocessor need only load the address of the chain table into
the DTC and give a "start" command to initiate a DMA transfer.
DMA transactions may be initiated
4-1

locally

the

J-ll

the

KXJll-CA User's Guide
PRELIMINARY
DMA TRANSFER CONTROLLER ( DTC )

4/3/86

arbiter CPU. If the transfer is initiated by the arbiter the command
words and transfer paramete:rs are placed in the command registers of
th1e two-port RAM (TPR) file. The local J-ll will then initiate the
DMA transaction using the parameters supplied by the arbiter.
The OTC consists of two identical channels.
DNA transfers may be
interleaved between these two channels or interleaved between the OTC
and the J-ll." 'It is also possible to select a "hog mode" that allows
the DMA transfer to run to. completion without interruption.
The OTC supports three types of operations:
Transfer, Search, and
Trclnsfer-and-Search.
As the name implies, Transfer operations move
data from a source to a destination. Search operations read data from
a source and compare the data to the pattern register. A mask
re~1ister
allows the user to declare "don't care"
bits.
The
Trclnsfer-and-Search operation combines the features of the Transfer
and Search functions. In t~is type of operation data is transferred
between a source and destination until the data transferred meets the
match condition specified in the Channel ~ode register.
OTC is capable of performing multiple DMA transactions without
processor intervention.
This can be accomplished in two way'S:
base-to-current reloading or chaining.
Base-to-current reloading
allows the DTC to reload a portion of its registers before initiating~"
a DMA transfer.
The reload operation occurs between
internal
registers so there are no memory access related delays. This type of
operation is only practical in applications where data' is continuously
transferred between the same addresses. Chaining allows some or all
of the applicable registers of the DTC to be reloaded from a new chain
table.
ThE~

Upon completion of a DMA transfer the DTC may perform any combination
of the following options:
Interrupt the local processor, perform
base-to-current reloading, or perform a chain reload.
It may also
choose to take no action.

4.2

DTC CONSIDERATIONS

Get from Henry.

4.3

DATA TRANSFER CONTROLLER (DTC) REGISTERS
NOTE
Refer to Section x.x for descriptions of how
registers are used during DNA operations.

the

DTC

The Data Transfer Controller contains two types of registers:
global
registers and channel registers. Global registers control the overall
4-2

KXJll-CA User's Guide
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OMA TRANSFER CONTROLLER (OTC)
operation and configuration of the OTe.
There are two global
registers: the command register and the master mode register (see
Table x-x). Channel registers define the state of a particular
channel.
There are two identical sets of channel registers, one for
each channel. These registers are always accessed as words and are
aligned on J!ven (word) address boundaries. Table x-x lists the DTC
channel registers and their·addresses.
The KXJll-CA DTC is based on the AmZ8016 chip (as described in the
AmZ8016 Data Sheet).
Several registers of the AmZ80l6 chip are not
implemented in the KXJII-CA. These are shown as ftreservedft in the
tables.
The tables specify the access code for each register.
abbreviations used is as follows:

The key to

R • The register can be read by the on-board J-11 processor.
W • The register can be written by the on-board J-l1 processor.
C • The register can be loaded by the OTC as part of a chaining
operation.
X • The register is not implemented or is reserved for future
use by Digital Equipment Corp.
Table x-x

DTC Global Registers

Address

Access

Description

17774454 *
17774470

Command Register
Master Mode Register

4-3

the

KXJ11-CA User's Guide
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DMA TRANSFER CONTROLLER (DTC>
Table x-x

4/3/86

DTC Channel Registers

Channel 1
Address

Channel 0
Address

Access

Description

17774400
17774404
17774410
17774414
1'7774420

17774402
17774406
17774412
17774416
17774422

RWe
RWe
RWe
RWe
Rwe

Current B Address Offset
Base B Address Offset
Current A Address Offset
Base A Address Offset
Current B Address Segment/Tag

17774424
17774430
17774434
17774440
17774444

17774426
17774432
17774436
17774442
17774446

Rwe
Rwe
Rwe
Rwe
RWC

Base B Address Segment/Tag
Current A ~ddress Segment/Tag
Base A Address Segment/Tag
Chain Address Offset
Chain Address Segment/Tag

17774450
17774454 *
17774460
17774464

17774452
17774456
17774462
17774466
17774472

R
R
Rwe
RWe

Interrupt Save Register
Status Register
Current Operation Count
Base Operation Count
Reserved

17774474
17774500
17774504
17774510
17774514

17774476
17774502
17774506
17774512
17774516

17774520
17774524
17774530
17774534

17774522
17774526
17774532
17774536

X
X
X
X

RWC
RWC
Rwe
RWC
RWC
X

Reserved
Reserved
Reserved
Pattern Register
Mask Register
Channel Mode Low
Channel Mode High
Interrupt Vector
Reserved

* Location 17774454·can be read or written. When read, it yields

status information only. It is written with command information
that cannot be read back.

4.3.1

DTC Global Registers

4.3.1.1 Command Register - The Command Register is the write-only
register that the on-bo'ard J-11 uses to issue commands to the DTC.
The:se commands include Reset, Start Chain, and others (see Figure
x-x) •

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DMA TRANSFER CONTROLLER ( DTC )

ADDRESS: 17774454

Figure x-x
Bits

DTC Command Register

Name

Description

15:8
7:5

Not used
FF

Function field - specifies the type
of function to be performed by the DTC.
FF
000
001
010
011
100
101
110
111

Function
Reset
Interrupt
Software Request
Flip Bit
Hardware Mask
Start Chain
Reserved
Reserved

CIE

Channel interrupt enable - When set,
indicates that interrupt requests are
enabled.

IUS

Interrupt under service - When set,
indicates that an interrupt is being
-serviced.

Interrupt pending - When set, indicates
that an interrup~ request is currently
pending.

SET

Set/Clear - When set, specifies a set
or 1 condition. When cleared, specifies
a clear or 0 condition.

Channel O/Channel 1 - When set, specifies
channell. When cleared, specifies channel
O.

Table x-x summarizes the functions that can be
the various bits of the DTC Command Register:

4-5

performed

writing

KXJll-CA User's Guide

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DNA TRANSFER CONTROLLER (MC)

4/3/86

Table x-x DTC Command Summary
Ccnnmand

DTC Command Register Bits
76 543 210

Reset
Start Chain Channel 0
Start Chain Channel 1
Set Software Request Channel 0
Set Software Request Channel 1

10
10
01
01

OXX
lXX
lXX
OXX
OXX

XXO
XXl
XlO
Xll

Clear Software Request Channel 0
Clear Software Request Channel 1
Set Hardware Mask Channel 0
Set Hardware Mask Channel 1
Clear Hardware Mask Channel 0

01
01
10
10
10

OXX
OXX
OXX
OXX
OXX

XOO
X01
X10
Xll
XOO

Clear Hardware Mask Channel 1
Set CIE, IUS, IP Channel 0
Set CIS, IUS, ID Channel 1
Clear CIE, IUS, IP Channel 0
Clear CIE, IUS, IP Channel 1

10
00

OXX

X01
P10
P11

lES
lES
lES
lES

Set Flip Bit Channel 0
Set Flip Bit Channel 1
Clear Flip Bit Channel 0
Clear Flip Bit Channel 1

01
01
01
01

lXX
lXX
lXX
lXX

00
00

XXX

POO
POl
X10
Xl1

xoo

XOl

Notes:
E

:II

AS:II

P
X

:II
:II

Set to perform set/clear on ClE, clear for no effect on ClE.
Set to perform set/clear on IUS, clear for no effect on IUS.
Set to perform set/clear on IP, clear for no effect on IP.
"Don't care" bit. This bit is not decoded and may be 0 or 1.

4.:1.1.2

val~ious

Master Mode Register - The Master Mode Register
aspects of overall DTC operation (see Figure x-x).

controls

ADDRESS: 17774470
15

Figure x-x Master Mode Register
Bits

Description

Name
4-6

ENS WAI
DC CTR

HOG

DMA ENS

KXJII-CA User's Guide
PRELIMINARY
4/3/86
DMA TRANSFER CONTROLLER (DTC)
15:8

Not used (read as ones)

Must be zero

Must be one

Must be zero
DC CTR

Daisy chain control - When set, inhibits
interrupt requests from the on-board
PIa counter/timer. The PIa counter/timer
is on an interrupt daisy chain at a higher
level than the DTC.
;

Must be one.

HOG

Hog mode - When set, the DTC inter'leaves
control of the local I/O bus with the
on-board J-ll. When cleared, the DTC
retains control of the bus until a
terminal condition (as indicated by ~he
contents of the Current Operation Count
Register described in Section x.x.x) ~~
exists. This is also called "hog mode
ft

•

Must be zero

DMA enable - When s~t, allows the DTC to
request control of the local I/O bus.
When cleared, prevents chaining or DMA
operations.

DMA ENB

4.3.2

DTC Channel Registers

4.3.2.1 Current Address Registers A And B - Each channel has two
Current Address Registers, one which specifies the current source
address of a DTC transfer and one which specifies the current
destination address. The "flip bit n in the Channel Mode Register (see
Section x.x) specifies which registers (A or B) are the source and
which are the destination.
A complete Current Address Register
consists of two words, a segment/tag and an offset.
The segment/tag
specifies:

Whether the source (or destination) address resides on the Q-Bus
Whether the source (or destination) address
page

resides

the

Address bits <21:16> of the source (or destination> address

4-7

I/O

KXJll-CA User's Guide
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DMA TRANSFER CONTROLLER ( DTC )

4/3/86

Whether the source (or destination) address should be incremented,
decremented, or held constant as the transfer proceeds
The segment/tag has the following format:

ADDRESS: 1-7774420,17774422,17774430,17774432
1S

Figure x-x Current A or B Address Segment/Tag

Q/L

Bi1:s

Description

I/O

OIL

Bus Choice - When set, indicates that
the current source (or destination>
address resides on the O-Bus. When
cleared, indicates that the current
address is a local (KXJ11-CA) one.

I/O

I/O bit - When set, causes the Q-Bus
signal BBS7 to be asserted which forces
a reference to the I/O page. The
referenced I/O page can reside locally
(if bit 15 is cleared) or on the Q-Bus
(if bit 15 is set).

13:8

ADDR

Bits <21:16> of the current address.
Must be zero

7:5

4:3

ACF

Count method - determines how addresses
will be affected as the DTC transfer
proceeds.
ACF
00
01

Function
Increment address
Decrement address
Hold address
Hold address

11
Must be zero

2:0

The offset consists of bits <15:00> of
address

4-8

the

source

(or

destination)

KXJll-CA User's Guide

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DMA TRANSFER CONTROLLER (eTC)

ADDRESS: 17774400,17774402,17774410,17774412
15

: :' :

'02

: ::

Figure x-x Current A or B Address Offset

4.3.2.2 Base Address Registers A And B - The formats of Base Address
Registers A and B are identical to those of Current Address Registers
A and B. At the beginning of a transfer, the Base Address Registers
and Current Address Registers are loaded with the same information. A
transfer can be restarted by reloading the Current Address Registers
with the contents of the Base Address Registers. Refer to Figures x-x
and x-x for the register bit descriptions.

4.3.2.3 Chain Address Register - The Chain Address Register is used
to point to a -reload word-, the first word in a chain table (see
Section x.x). The reload word specifies which registers are to be
loaded in order to set up a chaining operation. The other chain table
entries contain the data with which the registers are loaded.
The Chain Address Register consists of two words,
offset. The segment/tag specifies:

segment/tag and an

Whether the reload word address resides on the Q-Bus
Whether the reload word address resides in the I/O page
Address bits <21:16> of the reload word address
The segment/tag has the following format:

ADDRESS: 17774444, 17774446
12

Figure x-x Chain Address Segment/Tag

OIL
Bits

I/O

Description

Name
4-9

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4/3/86

Q/L

Bus Choice - When set, indicates that
the reload word address resides on the
Q-Bus. When cleared, indicates that the
address is a local (KXJll-CA) one.

14 .

I/O

I/O bit ~ When set, causes the Q-Bus
signal BSS? to be asserted which forces
a reference to the I/O page. The
referenced I/O page can reside locally
(if bit 15 is cleared) or on the Q-Sus
(if bit 15 is set).
.

13:8

ADDR

Bits <21:16> of the reload word address.
Must be zeros

7:0

The offset consists of bits <15:0> of the reload word address:

ADDRESS: 17774440, 17774442
15

1009

•••. 1'" .,,,

Figure x-x Chain Address Offset

4.3.2.4 Interrupt Vector And Interrupt Save Register - Each channel
has an Interrupt Vector Register and an Interrupt Save Register. The
Interrupt Vector Register contains the vector that is output during an
interrupt acknowledge cycle. When an interrupt occurs, the contents
of the Interrupt Vector Register and part of the... Status Register are
loaded automatically into the Interrupt Save Register. This allows a
new vector to be loaded during chaining and a new DNA operation can be
performed before an interrupt acknowledge cycle occurs. The Interrupt
Save Register can be read but can not be directly written by the user.
The Interrupt Vector Register has the following format:
.

ADDRESS: 17774530, 17774632
15

(¥: :
Figure x-x Interrupt Vector Register
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4/3/86

DMA TRANSFER CONTROLLER (DTC)

Description

Name

Bits

Not used (read/write)

15:8

VEe

7:2

Interrupt vector
Not used (read/write)

1:0

The Interrupt Save Register has the following

fo~at:

ADDRESS: 17774450. 17774452

MCl
MCH

MC
CA

TC
EOP

Figu e x-x Interrupt Save Register

Bi ts

Nant

HRQ

Hardware request - A copy of Status
Register bit 5.

MCH

Match count high - A copy of Status
Register bit 4.

MCL

Match count low - A copy of Status
Register bit 3.

Chain abort - A copy of Status
Register bit 12.

Match count - A copy of Status
Register bit 2.

EOP

End of process - A copy of Status
Register bit 1.

Terminal count - A copy of Status
Register bit O.

CH NUM

Channel number - When set, refers to
channel 1. When cleared, refers to
channel O.

7:2

VEC

Interrupt vector - A copy of Interrupt
Vector Register bits <7:2>.

1:0

CH NUM

Description

Not used

4-11

KXJ11-(:A User's Guide
PRELIMINARY
DNA TRANSFER CONTROLLER (DTC)

4/3/86

4.3.2.5 Status Register - Each channel has a
read-only
Status
Register.
Each Status Register contains: an interrupt status field
(bits <15:13», a DTC status field (bits <12:9», a hardware interface
field (bits <6:5», and a completion status field (bits <4:0». The
bits which comprise these fields are described below.
Parts of the
Status Register are copied to the Interrupt Save Register when an
interrupt occurs (see Section x.x.x). Note that bits <12:9> a 0000
indicates that the channel is initialized and ~aiting for a request.
The Status Register has the following format:

ADDRESS: 17774454, 17774456
15

WFB

HRQ

SIP

IUS

EOP

MCH

Bits

Name

. Description

CIE

Channel interrupt enable - When set,
indicates that interrupt requests are
enabled. Set the same as 4 of the
Command Register.

IUS

Interrupt under service - When set,
indicates that an' in.terrupt is being.
serviced. Set the same as bit 3 of the
Command Register.

Interrupt pending - When set, indicates
that an interrupt request is currently
pending. Set the same as bit 2 of the
Command Register.

Chain abort - When set, indicates that
a chaining operation has been terminated.
This bit is also set when the DTC is
initialized. Cleared when a new chain
address segment/tag or offset word is
loaded.

NAC

No auto reload on chaining - When set,
indicates that the channel has completed
a DMA transfer and that neither base-tocurrent reloading nor auto-chaining were
enabled. This bit is also set when the
DTC is initialized. Cleared when a Start
Chain Command is issued.

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DMA TRANSFER CONTROLLER (DTC)

WFB

Waiting for bus - When set, indicates
that the channel wants control of a bus
to perfo~ a DMA transfer.

SIP

Second interrupt pending - When set,
indicates that a second interrupt is
pending on the channel and that channel
activity should be suspended until an
interrupt acknowledge occurs.
Must be zero

8:7
6

Hardware mask - When set, indicates that
this channel is inhibited from responding
to the assertion of the channel's hardware
request line.

HRQ

Hardware request - When set, indicates
that the channel's hardware request line
is asserted.

MCH

Match count high - When set, lndicates~
a match between the upper byte of data
being transferred-and-searched or
searched and the pattern deter.mined by
the Pattern and Mask Registers.

MCL

Match count low - When set, indicates
a match between the lower byte of data
being transferred-and-searched or
searched and the pattern determined by
the Pattern and Mask Registers.

Match count - When set, indicates that
a DMA operation was terminated due to
a match between data being·transferredand-searched or searched and the
condition specified by bits <1:0> of
the Channel ~ode High Register.

EOP

End of process - When set, indicates
that a DMA operation was terminated
due to the assertion of the DTC's
end of process (EOP) line.

Terminal count - When set, indicates
that a DMA operation was terminated
because the operation count reached
zero.

4-13

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DMA TRANSFER CONTROLLER (DTC)

4.3.2.6 Current And Base Operation Count Registers - Each channel has
a Current Operation count Register which specifies the number of words
(or bytes) remaining to be transferred for a DMA operation.
The
contents of the register are decremented by one each time a datum is
transferred. A DNA operation can be resumed where it left off by
u!sing the count contained in this register. When a DMA transfer is
c()mplete, the register contains zero. The maximum count (64 K) is
specified by loading this register with zero.
Each channel also has a Base Operation Count Register.
The contents
of the Base Operation Count Register are initially identical to those
of the Current Operation Count Register. As the transfer progresses,
hc)wever, the contents of the Base Operation Count Register are not
dEtcremented. I fa DMA transfer needs to be restarted from scratch,
the original byte (or word) count can be restored by loading the
contents of the Base Operation Count Register into the Current
Operation Count Register.
Refer to Figures x-x and x-x for the register formats.

ADDRESS: 17774460,17774462
15

: : : :

Figure x-x

Current Operation count Register

ADDRESS: 17774464, 17774466
15

I :

: :
Figure x-x

Base Operation Count Register

4.3.2.7 Pattern And Mask Registers - Each channel has a Pattern
Register
and
a
Mask Register which are used in search and
transfer-and-search operations.
The Pattern Register contains a
pattern that read data is compared with to determine whether or not a
"match" condition exists. The user can program the DTC to stop a
search when there is a match or when there is no match. The Mask
Register is used to exclude selected bits from the' comparison.
Setting a Mask Register bit to "1" excludes that bit from the
comparison. The formats of the Pattern and Ma~k Registers are shown
in Figures x-x and x-x.
4-14

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DMA TRANSFER CONTROLLER (DTe)

ADDRESS: 17774510. 17774512
15

I :

::
12

00·

: : : :

Figure x-x

Pattern Register

ADDRESS: 17774514. 17774516
15

: : : :
Figure x-x

Mask Register

4.3.2.8 Channel Mode Register - Each channel has a Mode Register.
The Mode Register specifies what type of DNA operation a channel is to
perform, how the operation is to be executed, and what action if any
is to be taken when the operation is completed. The Mode Register
consists of two words, a Channel Mode High and a Channel Mode Low.
Channel Mode High is used to:
Initiate a DMA operation
Specify what is to occur if a match condition exists
Determines how software and hardware requests are h'andled.
Channel Mode High has the following format:

I I I I I I I I I I I I t\\\\\\\\\\\1 I +1
0

Figure x-x Channel Mode High
Bits
15:5

Name

Description
Not used (read as zeros)
4-15

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DNA TRANSFER CONTROLLER (DTC)
4

Software request - When set, initiates
a DNA operation. The channel requests
the bus and performs transfers as
specified by XFER in Channel Mode Low.

,liM

Hardware mask - When set, inhibits the
channel from responding to the assertion
of the channel's hardware request line.
Not used (read as zero)

1:0

Match condition - Specifies what is to
occur for match conditions.
MC

Action
Stop on no match
Stop on no match
Stop on word match
Stop on byte match

00
01
10
11

Channel Mode Low specifies:
The type of operation and transfer performed
Which of the Current Address Registers (A or B) is the source
which is the destination.

and

What will occur when a DNA operation is complete.
Channel Mode Low has the following format:
ADDRESS: 17774520, 17774522
01

TCCE

EOPCE

MCCE

MCSC

Tesc

EOPIE

TelE

eopsc

MCIE

FLIP

Bits

Name

Description

TCCE

Terminal count chain enable - When set,
causes a chain reload for the next DMA
operation if the Current Operation count
Register is decremented to zero.

MCCE

Match count chain enable - When set,
causes a chain reload for the next DMA
operation if a match condition exists.

EOPcE

End of process chain enable - When set,
4-16

KXJll-CA User's Guide
PRELIMINARY
4/3/86
DMA TRANSFER CONTROLLER (DTC)
causes a chain reload for the next DMA
operation if an end-of-process (EOP)
termination occurs.
12

TCBC

Terminal count base-current - When set,
causes a base-to-current reload if the
Current Operation count Register is
decremented to zero.

MCBC

Match count base-current - When set,
causes a base-to-current reload if a
match condition exists.

EOPBC

End of process base-current - When set,
causes a base-to-current reload if an
end-of-process (EOP) termination occurs.

TCIE

Terminal count interrupt enable - When_
set, the channel issues an interrupt
if the Current Operation count Register
is decremented to zero.

MCIE

Match count interrupt enable - When
set, the channel issues an interrupt
if a match condition exists.

EOPIE

End of process interrupt enable - When set,
the channel issues an interrupt if an
end-of-process (EOP) termination occurs.

6:5

XFER

Transfer type - Specifies the type of
transfer the channel is to perform. Refer
to the DTC Data Sheet for descriptions of
these transfers.
XFER
00
01
10
11

Transfer Type
Single transfer
Demand dedicated with bus hold
Demand dedicated with bus release
Channel to channel demand interleav~

FLIP

Flip bit - When set, Current Address
Register B contains the source and
Current Address Register A contains the
destination of a transfer. When cleared,
Current Register A contains the source
and Current Address Register B contains
the destination.

3:0

Operat ion type - Speci f ies t.he type of
operation the channel is to perform. See
the DTC Data Sheet for descriptions of
t,;lese operations.
4-17

KXJ11-(~ User's Guide
PRELIMINARY
DMA TRANSFER CONTROLLER (DTC>

4/3/86

Operation

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Transfer
Word Word Flowthrough
Transfer
Byte Byte Flowthrough
Reserved
Reserved
Trnsf-Search Word Word Flowthrough
Trnsf-Search Byte Byte Flowthrough
Reserved
Reserved"
Transfer
Byte Word' Flowthrough
Reserved
Reserved
Reserved
Trnsf-Search Byte Word . Flowthrough
Reserved
Search
Word Word Read
Search
Byte Byte Read

Operand
Size
A

Transaction
Type

Note that "flyby" operations are nGt
supported on the KXJll-CA.

4. ~~

PROGRAMMING THE DTC

Chip Initialization,
Prc)gramming the DTC consists of three phases:
Data Transfer (or Search), and Termination. This section will provide
a general description of these phases.

4.4.1

Chip Initialization

The RESET instruction is used to place the DTC in a known state.
A
reset will clear the CIE, IP, SIP and WFB bits and set the CA and NAC
bits in the Channel Status registers. The Master Mode register will
also be cleared.
Before a DMA operation is initiated the local CPU
loads the Master Mode register and the Chain Address register of the
appropriate channel of the DTC. The DTC fetchs any other parameters
that are necessary from a table located in system memory - referred to
as the chain table.
This minimizes the amount of CPU intervention
necessary to perform a DNA operation. The relationship of the Chain
Address Register tO,the chain table is shown in Figure x-x.

+---------------+

I
I

System
Memory

\
I

+---------->11-------------------\
Reload Word
I

DTC
Channel Oil

4-18

1-------------------1
I
I

KXJll-CA User's Guide
PRELIMINARY
4/3/86
DMA TRANSFER CONTROLLER (OTC)

I
I

DTC

+---------+ I
I Chain I I
I
I Address 1--1----------+
I Reg. I 1
+---------+ I
+--~~-----~-----+

+---- New Chain Address
I

-------------------

1
1

I
I

-------------------

+--->

Reload Word
DTC

I
I

I
I
I

1-------------------1
1

Figure. x-x Chain Address Register

The first word in the chain table is the reload word. The reload word
is used to specify which registers are to be loaded for the pending
DMA operation. Bits <9:0> of the reload word correspond to the
registers of the DTC as s~own in Figure x-x. Bits <15:10> are not
used.

+---------------------------------------------------------------+
I x 1 x I x I x I x I x 1 9 I 8 1 7 I 6 I 5 1 4 1 3 I 2 I 1·1 a I
+----~---~-------~~------------~--------~-~--------~-- ----------+

I
Current ARA
1
Current ARB ---------------------+
1
Current Op-Count
1
Base ARA
I
Base ARB
Base Op-Count
Pattern and Mask
Interrupt Vector
Channel Mode
Chain Address
Figure x-x Reload Word

-----------------+
I
I·
--------------------+
I
--------------------------------+
I
------------------------------------+ I
I
-----------------------------------+ I I
------------------------------------+ I
----------------------------------------+ 1
------------------------------------------------+
---------------------------------------------------+

Therefore if a bit in the reload word is set then the corresponding
register(s) are to be reloaded from the chain table. Since all of the
registers are not applicable to each DMA operation the chain table may
be of variable length. (i.e. The pattern and mask registers would
not be used in DMA operations that do not search the data.) It is NOT
correct to select a register in the reload word and subsequently load
that register with a dummy argument such as zero. Figures x-x and x-x
4-19

KXJII-C~ User's Guide
PRELIMINARY
DNA TRANSFER CONTROLLER (DTC>

illustrate examples
the chain table.

4/3/86

the relationship between the reload word and

9
7
8
4
5
6
2
3
1
o I
----~-------~--------~--~---~-~--~-~-------~~--~---~~--~---~---I

x
x x 1
1
1
0
0
0
0
0
1
.. --.x. - x --------.....
------_......
----------..
--------..;-..---------_
.....0 - I
I

I
I
~~-!.---

Current ARA

Segment/Tag

I
~----------~------------~--~--~~---~---------~------~~-~-------,

Current ARA Offset
I
---------~-----------------------------------------------------1
Current ARB Segment/Tag
_1

---------------------------------------------------------------1
Current ARB Offset
I
---------------------------------------------------------------1
Current Op-Count
I
---------------------------------------------------------------1
Channel Mode High
I
--~----------~-------------------~--------~-----------~---~----I

Channel Mode Low

-------------------------------~--~~--------~--------- ---------1

765

0 /

---------------------------------------------------------------/
x
x
x x
x x 1
0
1
0
0 101 1
1
1
I

101

~------------------------~----------------------------------~--I

Current ARA Segment/Tag
1
---------------------------~-----------------------------------1
Current ARA Offset
1

---------------------------------------------------------------1
Current Op-Count
---------------------------------------------------------------1
Pattern Register

1
1

-----------~-----------------------~---------------------------1
Mask Register
I

---------------------------------------------------------------1
Channel Mode High

--~~~--------~------~-----~--------~--------~---~--------~-----I

Channel Mode Low

-------------~----~----~~-~-~------~----------~------- ---------1
Chain Address Segment/Tag
I

--~--------~-------------------------~---------------~---~----~I
. Chain Address Offset
I

---------------------------------------------------------------1I

The DTC has been properly initialized once the chain table(s) have
been created and the Master Mode register and Chain Address. Register
for the selected channel have been loaded.

4-20

KXJll-CA User's Guide
PRELIMINARY
4/3/86
DNA TRANSFER CONTROLLER (DTC)
4.4.2

Data Transfer

The DTC may perform a DMA operation once it has been properly
initialized.
A DNA operation may be initiated in one of four ways:
by software request, by hardware request, by loading a set software
request bit'·· in the Channel Mode register during chaining, or as the
result of a command from the arbiter.
Software Request: The local CPU may initiate a DNA operation by
writing a "start chain" command to the Command Register. If the
"software request" bit is not set as part of the start chain command
then the "software request" command can be issued to initiate the DMA
-operation. The "software request" command sets the software request
bit in the chan:nel's Mode register.
If either the SIP (second
interrupt pending) bit or the NAC (no auto-reload or chain> bit is set
in the channel's status register the DNA operation will not begin.
The SIP bit will be cleared when the channel receives an interrupt
acknowledge.
The NAC bit will be cleared when the channel receives a,
'start chain' command. The 'start chain' command initiates the DMA
operation after the registers of the selected channel are loaded fr~m
the chain table. The 'start chain' command is ignored if the~SIP bit
or the CA (Chain Abort) bit are set in the channel's status register.~~
The SIP bit was described above. The CA bit is cleared when the
channel's chain address register is reloaded.
Hardware Request: DNA operations may· be started by asserting a
channel's DREQ input from SLU2 or the PIO. The mask bit in the
Channel Mode Register controls whether this request is detected or
not.
Details about this type of request are beyond the scope of this
document.
Starting After Chaining: If the software request bit of the channel's
Master Mode register is set during chaining the channel will perform
the DMA operation at the end of chaining.
Arbiter Request: The arbiter may interrupt the local CPU to request a
DMA operation. This is accomplished by passing parameters to load the
chain address register of channel 0 via the two-port RAM. The arbiter
loads register 2 of the TPR with the offset of the chain address
register and register 3 of the TPR with the segment/tag of the chain
address register." The DMA operation is then initiated by setting the
DMA Load bit (bit 1) in the TPR command register (register 0).
Error
conditions will be returned in TPR register 1.
Information in the channel's Mode "register determines what type of DMA
operation will be performed. The Channel Mode register consists of
two words, Channel Mode High and Channel Mode Low.
Bits <3:0> of the Channel Mode Low~register select the type of DMA
operation.
These
bits
determine whether the data should be
transferred, searched, or transferred-and-searched. Bit 4 is the flip
bi~.
It is used to determine which set of current address registers
(CARA, CARS) points to the source.
4-21

User's Guide
PRELIMINARY
DMA TRANSFER CONTROLLER (DTC)

KXJ11-(~

4/3/86

Bits <6:5> determine the transfer type. The types of DTC transfers
ar'e:
single transfer, demand dedicated with bus hold, demand
dedicated with bus release, and channel-to-channel demand interleave.
Single transfer is used with devices which transfer data at irregular
intervals. A single DNA transaction will occur each time a 'software
request' command is issued or the DREQ input is asserted. Demand
dedicated with 'bus hold is a software hog mode. This mode allows the
DMA transaction to' run to completion for local addresses as long as
there is a valid op count and the OREQ input is asserted. If the DREQ
input is not asserted no DMA operations will occur but the channel
will retain bus control. In Q-Bus hog mode, the KXJlI-CA releases the
bus and requests the bus again after each word transfer. Demand
dedicated with bus release is similar to demand dedicated with bus
hold in that a DMA transaction is allowed to run to completion if DREQ
is asserted. If DREQ is no't asserted the DTC must release the bus
thus allowing other devices to obtain the bus.
The operation
performed by a channel-to-channel demand interleave request depends on
the state of bit 2 in the Master Mode register. If MM bit 2 is clear
then control may be passed between each channel of the DTC without theneed to release the bus. If MM bit 2 is set then the DTC must share
the bus with the local processor. The DTC will release the bus and
then re-request it after every DMA iteration.
Bits <1:0> of the Channel Mode High register are used to determine the
t~?e
of match control in Search and Transfer-and-Search operations.
The DTC is capable of generating a termination condition based on 'No
Match', 'Word Match', and 'Byte Match'.
Bit <4> of the Channel Mode High register causes the channel to
request the bus and perform transfers when it is set by a 'Software
Request Command' or a chain reload.

4.4.3

Termination Options

Bits <15:7> of the Channel Mode Low register control the termination
options.
A DTC operation may be terminated in a number of ways. If
the Current Operation Count Register goes to zero then a Terminal
Count (TC> termination is generated. External logic may assert the
End Of Process (EOP) input of the DTC to generate an EOP termination
at any time.
In addition, during a Search or Transfer-and-Search
operation a match condition may occur which
generates
a
MC
termination.
Bits <15:7> allow the DTC to perform a chain reload, a
base-to-current reload, or to int~rrupt the local processor if a TC,
EOP, or Me termination condition is encountered. If bits <15:7> are
cleared then no special action is initiated when a TC, EOP, or MC
condition is encountered.

4.4.4

Examples

The following example programs were developed on a
4-22

PDP-ll/23+

system

KXJIl-CA User's Guide
PRELIMINARY
4/3/86
OMA TRANSFER CONTROLLER (OTC)
with 256KB of memory using the RT-I1 (version 5.1) operating system
with the KXJ1l-CA Peripheral Processor Software Toolkit.
These
examples assume the programmer is familiar with MACRO-l1 and the
KXJll-CA Peripheral Processor Toolkit •
• TITLE EXAMl.MAC
; This program transfers data from local KXJll-CA addresses to other
; local KXJll-CA addresses. This program should be compiled and linked
; on the development system and then downloaded into the KXJIl-CA using
the KXJ11-CA Software Toolkit. Once the program has been compiled
; and linked use the following KUI commands to execute it and verify.
its successfullness •

, •KUI
,· KUI>SET n
, KUI>LOAD EXAMl
,·· KUI>ODT
,
,··
.
,· ODT>CTRL/C

!Where n is the appropriate KXJll-CA
Use RUI ODT to verify that the destination
addresses are cleared

KUI>EXECUTE
KUI>ODT

·
·
,

Execute EXAMl
Use KUI OOT to verify that the transfer was
successful

; ODT>CTRL/C
; KUI>EXIT
,
; SET UP REGISTER ASSIGNMENTS
CMDREG
CASTFO
CAOFO

=
=
=
=

START:

MOVB #lJO,MMREG

LOAD MASTER MODE REG TO DISABLE DTC

CLRB CMDREG

RESET THE DTC

MMREG

MOV
MOV

174470
174454
174446
174442

MASTER MODE REGISTER
COMMAND REGISTER
; CHANNEL 0 CHAIN ADDRESS SEGMENT/TAG FIELD
; CHANNEL 0 CHAIN ADDRESS OFFSET FIELD

, LOAD THE CHAIN ADDRESS REGISTER SEG/TAG
#Q,CASTFO
#RELOAD,CAOFO, ; LOAD THE CHAIN ADDRESS REGISTER OFFSET

MOVB #131,MMREG

LOAD "MASTER MODE REG TO ENABLE OTC

MOVB #102,CMDREG

SET SOFTWARE REQUEST CHANNEL 0

MOVB #240,CMDREG

START CHAIN CHANNEL 0

STAY HERE WHILE THE USER VERIFIES
THAT THE PROGRAM WAS SUCCESSFUL

, CHAIN LOAD REGION
4-23

User's Guide
PRELIMINARY
DMA TRANSFER CONTROLLER (DTC)

KXJ11-C~

, RELOAD WORD <Select CARA,CARB,COPC,CM>

RELOAD: •WORD 001602
•WORD
• WORD

000000
SOURCE

.WORD-• WORD

000000
DESTNT

CURRENT ADDRESS REGISTER A SEG/TAG
CURRENT ADDRESS REGISTER A OFFSET
<This local address is the source>

,· CURRENT ADDRESS REGISTER B SEG/TAG
;

. WORD

000013 •

. WORD
•WORD

000000
000040

4/3/86

CURRENT ADDRESS REGISTER B OFFSET
<This local address is the destination>
CURRENT OPERATION COUNT <Transfer 13 words>

· CHANNEL MODE REGISTER LOW

, CHANNEL MODE REGISTER HIGH
<No match conditions, do nothing upon
completion,
transfer type =- Demand Dedicated w/Bus
Hold,
, CARA source, word transfers>

:II

SOURCE: •WORD

1,2,3,4,5,6,7,6,5,4,3,2,1

DESTNT: • BLKW

13 •

.END START

4-24

KXJll-CA User's Guide
PRELIMINARY
4/3/86
DNA TRANSFER CONTROLLER (DTC)

•TITLE EXAM2. MAC
This program transfers data from local KXJll-CA addresses to
global Q-bus addresses. This program should be compiled and linked
on the development system and then downloaded into the KXJII-CA using
the KXJll-CA Software Toolkit. Once the program has been compiled
; and linked use the following commands to execute it and verify its
successfullness.
;

<HALT the development machine so that locations may be examined
with Q-bus ODT>
@600000/xxxxxx
Examine the destination locations and clear
them if necessary

,· @P

, @600030/xxxxxx

···

Use the 'PI command to return to the system prompt

,
, .KUI

KUI>SET n
KUI>LOAD EXAM2
KUI>EXECUTE
KUI>EXIT

Where n is the appropriate KXJII-CA

· <HALT the development machine so that locations may be examined
,· with Q-bus ODT>
; @600000/xxxxxx ! Examine the destination locations to verify the
success of the transfer
;
.
@600030/xxxxxx
,

SET UP REGISTER ASSIGNMENTS

MASTER MODE REGISTER
COMMAND REGISTER
CHANNEL 0 CHAIN ADDRESS SEGMENT/TAG FIELD
; CHANNEL 0 CHAIN ADDRESS OFFSET FIELD

MMREG
CMDREG
CASTFO
CAOFO

=
=
=

START:

MOVB

#l30,MMREG

LOAD MASTER MODE REG TO DISABLE DTC

CLRB

CMDREG

RESET THE DTC

MOV
MOV

LOAD THE CHAIN ADDRESS REGISTER SEG/TAG
#O,CASTFO
#RELOAD,CAOFO , LOAD THE CHAIN ADDRESS REGISTER OFFSET

174470
174454
174446
174442

MOVB #131,MMREG

LOAD MASTER MODE REG TO ENABLE DTC

MOVB #102,CMDREG

SET SOFTWARE REQUEST CHANNEL 0

MOVB #240,CMDREG

,· START CHAIN CHANNEL a

, STAY HERE WHILE THE USER VERIFIES THAT

4-25

KXJll-CA User's Guide
PRELIMINARY
OMA TRANSFER CONTROLLER (OTC>

4/3/86

; THE PROGRAM WAS SUCCESSFUL
; CHAIN LOAD REGION
RELOAD: .WORD 001602 ; RELOAD WORD <Select CARA,CARB,COPC,CM>
.WORD·OOOOOO ; CURRENT ADDRESS REGISTER A SEG/TAG
• WORD SOURCE ; CURRENT ADDRESS REGISTER A OFFSET
; <This local address is the source>
.WORD 101400
.WORD 00000

CURRENT ADDRESS REGISTER B SEG/TAG
CURRENT ADDRESS REGISTER B OFFSET
.; <This global Q-bus address is the destination>
<This corresponds to address 600000 on the Q-bus>
; <The DTC uses physical addresses only>

.WORD 000013. ;. CURRENT OPERATION COUNT <Transfer 13 words>
•WORD 000,000
.WORD 000040

; CHANNEL MODE REGISTER HIGH

MODE REGISTER LOW
<No match conditions, do nothing upon compl~tion,
transfer type = Demand Dedicated w/Bus Hold,
, CARA = source, word transfers>
;

CHANNEL

SOURCE: .WORD

1,2,3,4,5,6,7,6,5,4,3,2,1

.END START

. 4-26

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
DMA TRANSFER CONTROLLER (DTe)

•TITLE EXAM3. MAC
This program transfers data from global Q-bus addresses to local
KXJ11-CA addr~sses. This program should be compiled and linked on
the development system and then downloaded into the KXJl1-CA using
the KXJ11-CA Software Toolkit. Once the program has been compiled
; and linked use the following commands to execute it and verify its
; successfullness.
; <Use Q-bus ODT to deposit values in locations 600000(8)-->600030(8) ..
, These values will be the source for this ope~ation>

··,
: @600000/000001 ! Deposit source values
,
.
,·· @600030/000001
, @P
Use the 'P' command to return to the system prompt
,·
,·· .KUI
,· KUI>SET n
Where n is the appropriate KXJ11-CA
,· KUI>LOAD EXAM3
KUI>EXECUTE
KUI>ODT

,·

ODT> .

! Use KUI ODT to examine the destination locations
to verify the transfer was successful

ODT>CTRL/C
; KUI>EXIT
SET UP REGISTER ASSIGNMENTS
MMREG
CMDREG
CASTFO
CAOFO
START:

:=I
:=I

=
=

MASTER MODE REGISTER
; COMMAND REGISTER
; CHANNEL a CHAIN ADDRESS SEGMENT/TAG FIELD
CHANNEL a CHAIN ADDRESS OFFSET FIELD

174470
174454
174446
174442

LOAD MASTER MODE REG TO DISABLE OTC

MOVB #130,MMREG
CLRB omREG
MOV
MOV

., RESET THE OTC

LOAD· THE CHAIN ADDRESS REGISTER SEG/TAG
LOAD THE CHAIN ADDRESS REGISTER OFFSET

#O,CASTFO
#RELOAD,CAOFO

MOVB #131,MMREG
MOVB #102,CMDREG
MOVB #240,CMDREG
BR

LOAD MASTER MODE REG TO ENABLE DTC

, SET SOFTWARE REQUEST CHANNEL a
START CHAIN CHANNEL 0

,.- STAY HERE WHILE THE USER VERIFIES THAT
4-27

KXJll-CA User's Guide
PRELIMINARY
DMA TRANSFER CONTROLLER (DTC)

4/3/86

; THE PROGRAM WAS SUCCESSFUL

; CHAI N LOAD REG ION
RELOAD: .WORD 001602

RELOAD WORD <Select CARA,CARB,COPC,CM>

• WORD··' 000000
• WORD DESTNT

CURRENT ADDRESS REGISTER A SEG/TAG
CURRENT ADDRESS REGISTER A OFFSET
; <This local address is the destination>

.WORD 101400
.WORD 000000

CURRENT ADDRESS REGISTER B SEG/TAG
CURRENT ADDRESS REGISTER B OFFSET
i <This global Q-bus address is the source>
: <This corresponds to address 600000 on
the Q-bus>
<The DTC uses physical addresses only>
i

.WORD 000013 • : CURRENT OPERATION COUNT <Transfer 13 words>
• WORD 000000
.WORD 000060

DEs'rNT: • BLKW

; CHANNEL MODE REGISTER HIGH
; CHANNEL MODE REGISTER LOW
; <No match conditions, do nothing upon
;completion,
transfer type a Demand Dedicated w/Bus Hold,
CARS a source, word transfers>
<Notice how similar this reload table is to
the one in EXAM2. By utilizing the flip bit
; in the CM Reg Low no further changes were
; necessary to use this table in this example>

13 •

. END START

4-28

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
DMA TRANSFER CONTROLLER (DTe)

.TITLE EXAM4.MAC
This program transfers data from global Q-bus addresses to other
global Q-bus ,addresses. This program should be compiled and linked
on the development system and then downloaded into the KXJll-CA using
the KXJll-CA Software Toolkit. Once the program has been compiled
; and linked use the following commands to execute it and verify its
successfullness.
<Use Q-bus OOT to deposit values in locations 600000(8)-->600030(8).
These values will be the source for this operation>
@600000/000001

! Deposit source values

; @600030/000001
; @P

Use the 'P' command to return to the system prompt'

;

; .KUI
KUI>SET n
KUI>LOAD EXAM4
KUI>!XECUTE
KUI>EXIT

Where n is the appropriate KXJll-CA

Q-bus ODT to examine the destination locations to verify that
.; <Use
the operation was sucessful>

; @610000/xxxxxx

@610030/xxxxxx
@P

Return to system prompt

SET UP REGISTER ASSIGNMENTS
MMREG

:II

CMDREG
CASTFO
CAOFO

:II

174470
174454
174446
174.42

START: MOVB #130,MMREG
CLRB CMDREG
MOV
MOV

, MASTER MODE REGISTER

COMMAND REGISTER
CHANNEL 0 CHAIN ADDRESS SEGMENT/TAG FIELD
CHANNEL 0 CHAIN ADDRESS OFFSET FIELD

, LOAD MASTER MODE REG TO DISABLE DTC
RESET- THE DTC

#O,CASTFO
; LOAD THE CHAIN ADDRESS REGISTER SEG/TAG
#RELOAD,CAOFO
LOAD THE CHAIN ADDRESS REGISTER OFFSET

MOVB #131,MMREG

LOAD MASTER MODE REG TO ENABLE DTC

MOVB #102,CMDREG

SET SOFTWARE REQUEST CHANNEL 0

MOVB #240,CMDREG

START CHAIN CHANNEL 0
4-29

KXJ11-CA User's Guide
PRELIMINARY
DMA TRANSFER CONTROLLER (DTC)
BR

4/3/86

: STAY HERE WHILE THE USER VERIFIES THAT
: THE PROGRAM WAS SUCCESSFUL

; CHAIN LOAD REGION
REI.OAD: • WORD 001602
• WORD 101400
• WORD 000000

RELOAD WORD <Select CARA,CARB,COPC,CM>

··

, ~URRENT ADDRESS REGISTER A SEG/TAG
, CURRENT ADDRESS REGISTER A OFFSET
,· <This global Q-bus address is the source>

<This corresponds to Q-bus address 600000(8»

• WORD 101400
• WORD 010000

CURRENT ADDRESS REGISTER B SEG/TAG

· <This global Q-bus address is the destination>

, CURRENT ADDRESS REGISTER B OFFSET

<This corresponds to Q-bus address 610000(8»

·
• WORD 000000 ,· CHANNEL MODE REGISTER HIGH
•WORD 000040 ,· CHANNEL MODE REGISTER LOW
<No match conditions, do nothing upon
completion,
transfer type = Demand Dedicated w/Bus
·,, CARA
= source, word transfers>

• WORD 000013. , CURRENT OPERATION COUNT <Transfer 13 words>

.END

START

4-30

ttO.LQ,

KXJll-CA User's Guide
PRELIMINARY
4/3/86
DNA TRANSFER CONTROLLER (DTC)

.TITLE EXAMS.MAC
;
;
;
;

This program demonstrates how chaining is implemented using the
DTC. A local to local transfer will be initiated under program
control. Then, using the chaining feature of the DTC, a local to
global transfer will be performed followed by a global to global
0; transfer and finally a global to local transfer. The following
; diagram illustrates these transfers.

,··
,

·;Transfer #1

KXJ11-CA Memory
--------------

;

+---1

;
;

I
1--·----------1
+-->1
I

;

Q-bus Memory

Transfer #2

1
1
I
I
1----------1

Transfer-#3

---------------> 1I ----------11---+I
1------------1

;
;
;

1------------1

;,;

I--~---------I

Transfer #4

I
I
I
1----------1
1
I
1<--+

<--------------- \----------1

· This program should be compiled and linked on the development system
and then downloaded into the KXJ11-CA using the KXJ11-CA Software
Toolkit. Once the program has been compiled and linked use the
following commands to execute it and verify its successfullness.
<Use Q-bus ODT to clear the memory locations 600000(8) --> 600030{S)
and 6100000(S) --> 610030(8) before executing the program>

· .KUI

KUI>SET n
; KUI>LOAD EXAMS
KUI>EXECUTE
KUI>ODT
ODT> .
ODT> .
; ODT>CTRL/C
KUI>EXIT

Where n is the appropriate KXJ11-CA
Use KUI ODT to verify that the destination
contents are accurate

; <Use Q-bus ODT to examine the contents of the intermediate
destinations to verify their accuracy>
SET UP REGISTER ASSIGNMENTS
MMREG
CMDREG
CASTFO
CAOFO
START:

::I
:::II

174470
174454
174446
174442

MOVB #130,MMREG

MASTER MODE REGISTER
COMMAND REGISTER
, CHANNEL 0 CHAIN ADDRESS SEGMENT/TAG FIELD
, CHANNEL 0 CHAIN ADDRESS OFFSET FIELD

LOAD MASTER MODE REG TO DISABLE DTC
4-31

User's Guide
PRELIMINARY
DMA TRANSFER CONTROLLER (DTC)

KXJ11-~~

4/3/86

RESET THE DTC
,O,CASTFO
; LOAD THE CHAIN ADDRESS REGISTER SEG/TAG
'LOAD1,CAOFO ; LOAD THE CHAIN ADDRESS REGISTER OFFSET

eLRB OfDREG

MOV
MOV

MOVB 1131,MMREG

; LOAD MASTER MODE REG TO ENABLE DTC

MOVB ,102,CMDREG

SET SOFTWARE REQUEST CHANNEL 0

MOVB 1240,CMDREG

START CHAIN CHANNEL

; STAY HERE WHILE THE USER VERIFIES THAT
THE PROGRAM WAS SUCCESSFUL

; CXAIN LOAD REGION
LOAD1: .WORD 001603
.WORD 000000
.WORD AREAl

CURRENT ADDRESS REGISTER A SEG/TAG
; CURRENT ADDRESS REGISTER A OFFSET
; <This local address is the source of
; transfer 11>

• WORD 000000
.WORD AREA2

; CURRENT ADDRESS REGISTER B SEG/TAG
CURRENT ADDRESS REGISTER B OFFSET
<This local address is the destination of
transfer #1>

.WORD 000013.

CURRENT OPERATION COUNT <Transfer 13 words>

.WORD 000000
.WORD 100040

; CHANNEL MODE REGISTER HIGH
CHANNEL MODE REGISTER LOW
<No match conditions, chain reload upon
completion, transfer type ~ Demand Dedicated
; w/Bus Hold, CARA = source, word transfers>
CHAIN ADDRESS REGISTER SEG/TAG
CHAIN ADDRESS REGISTER OFFSET
; <This address points to the new chain table>

.WORD 000000
.WORD LOAD2
LOA]) 2

RELOAD WORD <Select CARA,CARB,COPC,CM,CA>

.WORD 001603

RELOAD WORD <Select CARA,CARB,COPC,CM,CA>

.WORD 000000
.WORD AREA2

CURRENT ADDRESS REGISTER A SEG/TAG
CURRENT ADDRESS REGISTER A OFFSET
<This local address is the source of
transfer #2>

.WORD 101400
.WORD 000000

CURRENT ADDRESS REGISTER B SEG/TAG
CURRENT ADDRESS REGISTER B OFFSET
<This global address is the destination of
; transfer #2 - 600000(8»

.WORD 000013.

CURRENT OPERATION COUNT <Transfer 13 words>

.WORD 000000

CHANNEL MODE REGISTER HIGH
4-32

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
DMA TRANSFER CONTROLLER (DTC>

LOAD3

.WORD 100040

; CHANNEL MODE REGISTER LOW
; <No match conditions, chain reload upon
; completion, transfer type = Demand Dedicated
w/Bus Hold, CARA • source, word transfers>

•WORD '-000000
.WORD LOAD3

; CHAIN ADDRESS REGISTER SEG/TAG
; CHAIN ADDRESS REGISTER OFFSET
; <This address points to the new chain table>

.WORD 001603

; RELOAD WORD <Select CARA,CARB,COPC,CM,CA>

.WORD 101400
.WORD 000000

CURRENT ADDRESS REGISTER A SEG/TAG
; CURRENT ADDRESS REGISTER A OFFSET
; <This global address is the source of
; transfer #3>
<600000(8»

.WORD 101400
.WORD 010000

; CURRENT ADDRESS REGISTER B SEG/TAG
; CURRENT ADDRESS REGISTER B OFFSET
; <This global address is the destination of
; transfer #3 - 610000(8»

.WORD 000013 •

; CURRENT OPERATION COUNT <Transfer 13 words>

•WORD·OOOOOO
.WORD 100040

CHANNEL MODE REGISTER HIGH
CHANNEL MODE REGISTER LOW
; <No match conditions, chain reload upon
; completion, transfer type • Demand Dedicated
; w/Bus Hold,
, CARA • source, word transfers>

LOAD4

.WORD 000000
.WORD LOAD4

; CHAIN ADDRESS REGISTER SEG/TAG
; CHAIN ADDRESS REGISTER OFFSET
; <This address points to the new chain table>

.WORD 001602

; RELOAD WORD <Se.lect CARA,CARB,COPC,CM>

.WORD 101400
.WORD 010000

;
;
;
;

.WORD 000000
.WORD AREA3

CURRENT ADDRESS REGISTER B SEG/TAG
; CURRENT ADDRESS REGISTER B OFFSET
; <This local address is the destination of
, transfer #4>

CURRENT ADDRESS REGISTER A SEG/TAG
CURRENT ADDRESS REGISTER A OFFSET
<This global address is the source of
transfer #4>
<610000(8»

.WORD 000013.

CURRENT OPERATION COUNT <Transfer 13 words>

.WORD 000000
.WORD 000040

CHANNEL MODE REGISTER HIGH
REGISTER LOW
; <No match conditions, do nothing upon
completion, transfer type • Demand Dedicated
CHANNEL MODE

4-33

KXJll-w\ User's Guide
PRELIMINARY
DMA TRANSFER CONTROLLER (OTC>

4/3/86

; w/Bus Hold,
ARl~Al
ARl~A2

• WORD

AREA 3

.BLKW

CARA 2 source, word transfers>

1,2,3,4,5,6,7,6,5,4,3,2,1
13.
13.

.END START

4-34

KXJll-CA User's Guide
PRELIMINARY
4/3/86
DMA TRANSFER CONTROLLER (DTC)

.TITLE

EXAM6.MAC

; This program demonstrates how to initiate a DTC operation from. the
; arbi ter CPU-. ,This program wi 11 tranfer a block of data from Q-bus
i memory to KXJll-CA memory.
All of the information necessary for the
i transfer will reside in Q-bus memory (chain table, source data)
; This program should be compiled, linked, and run on the arbiter
i development system.
After the program executes use the following
; KUI commands to verify the transfer

; .KUI
; KUI>SET n
KUI>ODT
; ODT>5000/xxxxxx

Where n is the appropriate KXJl1-CA

Examine locations 5000 --> 5030 to verify that
the data was transfered correctly

ODT>5030/xxxxxx
; ODT>CTRL/C
; KUI>EXIT
i

Two-port RAM register definitions
TPRO:.160l00
TPR2:.160104
TPR3:.160l06
.MCALL

.EXIT

START: MOV #lOOOOO,TPR3 ; Place Chain Address Reg Seg/Tag in TPR3
; Place Chain Address Reg Offset in TPR2
MOV #LOAD,TPR2
BIS

#2,TPRO ; Issue DMA Load command to the conunand reg.ister

.EXIT
LOAD

•WORD

001602

; RELOAD WORD <Select CARA,CARB,COPC,CM>

• WORD

100000

• WORD

SOURCE

; CARA SEG/TAG <Select Q-bus address as
source>
CARA OFFSET

• WORD

000000

. WORD

005000

. WORD

000013 •

•WORD
•WORD

000000
000040

SOURCE: .WORD

icARs SEG/TAG <Select KXT address 5000 as
; destination>
;CARB OFFSET
cope <Op-count = 13 words>
eM High
; CM Low <select no termination options, software
,
hog-mode, CARA = source, word transfer~>
,

1,2,3,4,5,6,7,6,5,4,3,2,1
4-35

KXJll-CA User's Guide
PRELIMINARY
DMA TRANSFER CONTROLLER (DTC)
.END

START

4-36

4/3/86

CHAPTER 5
PARALLEL I/O CONTROLLER (PIO)

5.1

OVERVIEW

The PIO is designed around the AmZ8036 chip.
For details on the
operation of the AmZ8036, refer to the Z8036 Counter/Timer and
Parallel I/O Unit Technical Manual included as part
of
this
documentation package.
The information that follows is of a summary'
nature and describes the PIO functions implemented on the KXJI1-CA.
The KXJIl-CA PIa has the following features:
a

Two a-bit, double buffered, bidirectional I/O ports

A 4-bit special purpose I/O port

Four handshake modes

REQUEST signal for utilizing the DNA controller

Pattern recognition logic

Three independent 16-bit counter/timers
.~.

The two_a-bit ports (A and B) are identical excep~ that Port B can
provide external access to Counter/Timers 1 and 2. Each port may be
configured under program control as a single or double buffered port
with handshake logic or as a bit port for control applications.
Pattern recognition logic is also included in each port.
This logic
allows interrupt generation whenever a specific pattern is recognized.
Ports A and B may be linked to fo~ a 16-bit port with handshake.
When Port A or B is used as a port with handshake the control lines
are supplied by a special 4-bit port (Port C). If no handshake lines
are required then Port C may be used as a bit port.
Port C also
provides external access to Counter/Timer 3 and a REQUEST line that
allows the PIO to utilize the DMA controller when transfering data.
The PIO supplies three identical 16-bit counter/timers.
These
counter/timers operate at a frequency of 2 MHz which provides a
resolution of 500 ns. Each counter/timer may operate with one of
three output duty cycles:
pulse, one-shot, or square-wave. In
5-1

KXJll-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

4/3/86

addition, each unit may operate as retriggerable or non-retriggerable.

5.:2

PARALLEL I/O PORT (PIO) REGISTERS

Tht! PIO is designed around the AmZa036 chip and consists of two a-bi t
ports, one 4-bit port and a counter/timer. Table x-x summarizes the
registers associated with the PIO. All the registers in Table x-x
re~Jide
in the AmZa036 chip with the exception of the I/O Buffer
Control Register which· resides in the GAS on-board gate array
(OC:7037B).
The sections ·that follow give brief descriptions of the
PIe> registers.
Table x-x PIO Registers

5-2

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)

MASTER CONTROL REGISTERS
Master Interrupt Control Register
Master Config~ration Control Register

17777000
17777002

PORT SPECIFICATION REGISTERS
Port Mode Specification Register
Port Handshake Specification Register
Port Command and Status Register

17777100
17777102
17777020

17777120
17777122
17777022

BIT PATH DEFINITION REGISTERS
Data Path Polarity Registers
Data Direction Registers
Special I/O Control Registers

17777104
17777106
17777110

17777124
17777126
17777130

17777012
17777014
17777016

PATTERN DEFINITION REGISTERS
Pattern Polarity Registers (PPR)
Pattern Transition Registers (PTR)
Pattern Mask Register (PMR)

17777112
17777114
17777116

17777132
17777134
17777136

PORT DATA REGISTERS
A

17777032

17777034

17777036

CIT 1
17777070
17777024
17777054
17777056
17777040
17777042

CIT 2
17777072
17777026
17777060
17777062
17777044
17777046

CIT 3
17777074
17777030
17777064
17777066
17777050
17777052

17777004
17777076

17777006

CIT
17777010

PIO COUNTER/TIMER CONTROL REGISTERS
PIO Counter/Timer Mode Specification
PIO Counter/Timer Command and Status
PIO Counter/Timer Time Constant (MSB)
PIO Counter/Timer Time Constant (LSB)
PIO Counter/Timer Current Count (MSB)
PIO Counter/Timer Current Count (LSB)
INTERRUPT RELATED REGISTER.S
Interrupt Vector Register
Current Vector Register
I/O BUFFER CONTROL REGISTER

17777140

5-3

4/3/86

User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

lOCJ11-CJ~

5.:2.1

Master Control Registers

The Master Control Registers affect the overall operation of the PIO.
ThEtre are two Master Control Registers: the Master Interrupt Control
Register and the Master Configuration Control Register. All bits of
thEtSe two registers are cleared upon hardware reset except hi t 0 of
thE! Master'Interrupt Control Register, which is set.
Both registers
arE! read/wr i te.

5.2.1.1

Master Interrupt Control Register ADDRESS: 1 7777000
15

MIE

Figure x-x Master Interrupt Control Regls~er
CHRESET

5-4

KXJll-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)

Name

Bits

Not used (read as one·s)

15:8
··-MIS

Master interrupt enable - When cleared,
prevents the PIO~rom requesting interrupt
service or responding to an interrupt
acknowledge cycle. When set, enables
interrupts.
Must be zero

6:1

5.2.1.2

Description

CHRESET

Reset - Set upon hardware reset. Must
be explicitly cleared. When set, reads
of other PIO registers will yield zero
and writes will be ignored.

Master Configuration Control Register -

Figure x-x Master Configuration Control Register

ADDRESS: 17777002
15

. PIE

CT2E
CTl E

5-5

PLC

PCElCT3E

PAE

KXJll-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

Bits

N~e

15:8

4/3/86

Description
Not used (read as ones)

PBE

Port B enable - When cleared, inhibits
port B from issuing an interrupt request
and forces the port B I/O lines into a
high impedance state.

CTIE

Counter/timer 1 enable - When cleared,
inhibits counter/timer 1 from issuing an
interrupt request and clears bit 0 of
the Counter/Timer 1 Command and Status
Register.

CT2E

Counter/timer 2 enable - When cleared,
inhibits counter/timer 2 from issuing an
interrupt request and clears bit 0 of
the Counter/Timer 2 Command and Status
Register.

PCE/CTJE

Port C and counter/timer 3 enable - When~
cleared, inhibits port C and counter/timer
3 from issuing an interrupt request. Also
clears bit a of the Counter/Timer 3 Command
and Status Register arid forces the port C
I/O lines into a high impedance state.

PLC

Port link control - When cleared, allows
port A and port B to operate independently.
When set, links ports A and B to form a
l6-bit port. When the ports are linked,
only port A's Handshake and Command and
Status Registers are used. Port B is
specified as a bit port and its pattern
matching capability is disabled. When
linked, port B must be read or written
before port A. If the ports are to be
linked, this bit must be set before the
ports are enabled.
Port A enable - When cleared, inhibits
port A from issuing an interrupt request
and forces the port A I/O lines into a
high impedance state.

1:0

Counter/timer link control - Specifies
if and how counter/timers land 2 are
linked. The counter/timers must be
linked before they are enabled.
LC
00
5-6

Configuration
Counter/timers are independent

KXJl1-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL IIO CONTROLLER (PIO)
01
10
11

5.2.2

CIT l's output (inverted) enables;
CIT 2
CIT l's output (inverted) tri9ger~
CIT 2
CIT l's output (inverted) is
CIT 2's count input

Port Specification Registers

The Port Specification Registers define the operating characteristics
of ports A and B.
There are three types of Port Specification
Registers: Mode, Handshake, and Command and Status. Each port (A and
B) has one set of these three registers.
5.2.2.1 Port Mode Specification Registers (Ports A And B) - Th~se
registers are read/write. They are cleared upon hardware re~t.

Figure x-x Port Mode Specification Registers (Ports A and B)

ADDRESS: 17777100, 17777120

ITS

IMO

5-7

LPM/OTE

KXJ11-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

Bi 1:s

Name

Description
Not used (read as ones)

15~8

7: Ei

4/3/86

PTS

Port type select - Specifies the port
type.
PTS

00
01
10
11

Port Type
.
Bit port (no handshake)
Input port with handshake
Output port with handshake
Bidirectional port with handshake

ITB

Interrupt on two bytes - When cleared,
the Interrupt Pending (IP) bit for this
port (bit 5 of the Port Command and Status
Register) is set when one byte of data is
available for transfer. When set, IP is set
when two bytes of data are available for
transfer. For an input port, IP is set when
the Input Data Register is full. For an
output port, IP is set when the Output rrata
Register is empty. This bit must be cleared
for ports specified as bit ports, singlebuffered ports, or bidfrectional ports.

Single buffered mode - When cleared,
specifies that this port is doublebuffered. When set, specifies that this
port is single-buffered. This bit is always
cleared for bit ports.

IMO

Interrupt on match only - When set, an
interrupt is generated when the data moved
into the Input Data Register or out of the
Output Data Register matches the pattern
specification.

2:1

PMS

Pattern mode specification - Defines the
operation of the pattern match logic.
PMS
00
01
10
11

LPM/DTE

Pattern Mode
Disable pattern matching
AND mode
OR mode
OR-priority encoded vector mode

Latch on pattern match (LPM) or deskew
timer enable (DTE) - This is a dual
function bit. The LPM function is active
when the port is used as a bit port. The
DTE function is active when the port is
specified as an output port with
5-8

KXJll-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)
handshake. If LPM is set, the port
latches input data when a pattern match
is detected. If LPN is cleared, pattern
matches are detected, but the data read
from the port is the current (unlatched)
value. If DTE is set, the deskew timer is
active and can perform delay functions
(see the description of the Port Handshake
Specification Register). When DTE is
cleared, the deskew timer is not active.

5.2.2.2 Port Handshake Specification Registers (Ports A And B) - The
Port Handshake Specification Registers determine the parameters of a
handshake operation.
A Port Handshake Specification Register is
ignored if a port is configured as a bit port. These registers are
cleared upon reset. Access is read/write.

ADDRESS: 17777102, 17777122
15

Figure x-x Port Handshake Specification Registers
(Ports A and B)

5-9

tKJII-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

Bits

Name

15:8

7:6

4/3/86

Description
Not used (read as ones)

HST

Handshake type - Specify the type of
handshake operation performed.
HST
00
01
10
11

Handshake Type
Interlocked
Strobed
Pulsed
3-Wire

The pulsed and 3-wire handshake must not
be specified for bidirectional ports.
Only one port at a time can use the
pulsed handshake. If one port uses the
3-wire handshake, the other port must be
must be a bit port.
5:3

RWS

Request/Wait - Defines how this'port
impl~ments the request function. The
wait function is not implemented on
the KXJll-CA.
RWS
000
001
010
all
100
101
110
III

Request Function
Request disabled
Reserved
Reserved
Reserved
Special request
Output request
Reserved
Input request

Only port A can participate in a request.
Port B must be programmed as a bit port.
2:0

DTSB

Deskew time speci~ication - Defines the
minimum number of PIO clock cycles of
delay between the time a new byte of
data is output and the time the handshake
mechanism indicates that new data is
available. The PIO clock has a period of
250 ns. A deskew time of zero is defined
by setting DTE to zero in the Port Mode
Specification Register.
DTSB
000
001
010
011
5-10

Deskew Clock Cycles
2
4
6
8

KXJll-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL 1/0 CONTROLLER (PIO>
100
101
110

10
12
14
16

111

5.2.2.3

Port Command And Status Registers (Ports A And B)

ADDRESS: 17777020, 17777022
02

Ie
Bits

Name

00.

ORE

IUS

ERR

IRF

Description
Not used (read as ones)

15:8
7

IUS

Interrupt under service - When set,
indicates that this port is engaged
in an interrupt acknowledge sequence.
Interrupt requests at the same level or
lower are disabled. This bit is readlwrite
and is cleared upon reset.

Interrupt enable - When cleared, this port
is prevented from requesting an interrupt
or engaging in an interrupt acknowl~dge
sequence. When set, these interrupts are
enabled. The bit is read/write and is
cleared upon reset.

Interrupt pending - When set, indicates
that this port requires service because
of a pattern match, a handshake operation,
or an error. When cleared, indicates that
the. port does not require service. This
bit is read/write and is cleared upon
reset.
IUS, IE, and IP are written according to
the following command codes:
Bits <7:5>
000
001
010
5-11

Command
Null (no effect)
Clear IP and IUS
Set IUS

KXJll-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

4/3/86

011

100
101
110
III

Clear IUS
Set IP
Clear IP
Set IE
Clear IE

Interrupt ~rror - This bit is meaningful
only if this port has been configured as
a bit port and pattern matching has been
enabled. When set, indicates that a
pattern match occurred before a previous
match could be acknowledged. This bit is
read-only (writes to it are ignored) and
is cleared upon reset.

ORE

Output register empty - When set,
indicates that this output port's Output
Data Register is empty. Can be cleared
only by writing to the Output Data
.Register. This bit is read-only (writes
to it are ignored) and is set ~pon reset.

IRF

Input register full - When set,
indicates that this input port's Input
Data Register is full. Can be cleared
only by reading the Input Data Register.
This bit is read-only (writes to it are
ignored) and is cleared upon reset.

PMF

Pattern match flag - If pattern matching
is enabled for this port, this bit when
set indicates the occurrence of a pattern
match. This bit is read-only (writes to
it are ignored) and is cleared upon reset.

IOE

Interrupt on error - This bit is meaningful
only for bit ports with pattern matching
enabled. When cleared, prevents an interrupt
from being issued by this port if an error
occurs in pattern matching. When set, allows
these interrupts. The bit is ignored by
ports with handshake and should be cleared
for these ports. The bit is read/write.

5.2.3

Bit Path Definition Registers

Each port (A, B, and C) has one set of Bit Path Definition Registers.
They include the Data Path Polarity, Data Direction, and Special I/O
Control Registers. Only the four least significant bits of the
registers are valid for the port C registers.
5-12

KXJll-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)
5.2.3.1 Data Path Polarity Registers - The Data
Path
Polarity
Registers (Pigure x-x) define whether the bits in a port are inverting
or non-inverting_ These registers are cleared upon reset. Access is
read/write.

ADDRESS: 17777104, 17777124, 17777012
15

Figure x-x Data Path Polarity Registers (Ports A,
Name

Bits

a, and C)

Description

15:8

Not used (read as ones)
DPP

7:0

Data path polarity -, If a bit ~is set, the
corresponding bit path for this port i~
inverting (asserted LOW). If a bit is
cleared, the corresponding bit path for
this port is non-inverting (asserted HIGH)

5.2.3.2 Data Direction Registers - The Data Direction
Registers
(Figure x-x) define the data direction of each bit in a port. These
registers are ignored by'ports with handshake and are cleared upon
reset. Access is read/write.
ADDRESS~ 17777196. 17777126, 17777014

Figure x-x Data Direction Registers (Ports A,

5-13

a, and C)

4/3/86

KXJll-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

Name

Bits

Description
Not used (read as ones)

l!;: 8

,- 'DD

7:0

Data direction - If a bit is set, the
corresponding bit of this port is
specified as an input. If a bit is
cleared, the corresponding bit of this
port is defined as an output.

5.2.3.3 Special I/O Control Registers - The Special I/O Registers
(Figure x-x) allow special characteristics to be defined for a port's
data path.
These registers are cleareo upon reset.
Access is
read/write.

AtiORESS:1777713Q, 17777110, 17777016
15

'12

Figure x-x Special I/O Registers (Ports A, B, and C)

5-14

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)

Name

Bits

Description

15:8

Not used (read as ones)

7:0

Special input/output - If a bit is ~et,
the corresponding bit of this port 1S
specified as a l's catcher for input.
A l's catcher functions by automatically
latching a 1 if the input goes to 1.
The l's catcher is cleared only by
writing a zero to the Input Data Register.

5.2.4

Pattern Definition Registers

The Pattern Definition Registers (Figures x-x through x-x) are usea
collectively to specify a match pattern for each bit in port A or pqrt
B. The pattern specification for any bit (x) is summarized.in Table
x-x. These registers are cleared upon reset. Access is read/write.
Table x-x Pattern Specifications
PPRx

PTRx

PMRx

0
0
0

0
0
1

0
1

1
1
1
1

0
1
1

1
0
1

5.2.4.1

Bit x Match Condition
Bit masked off
Bit masked off
Any transition
Any transition
Zero
One
One to zero transition
Zero to one transition

Pattern Polarity Registers (PPR) -

ADDRESS: 17777112, 1 7777132
,5

I
Figure x-x Pattern Polarity Registers (Ports A and B)

5-J.5

KXJll-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)
5.2.4.2

4/3/86

Pattern Transition Registers (PTR) -

ADDRESS: 17777114, 17777134
15

Figure x-x Pattern Transition Registers (Ports A and B)

5.2.4.3

Pattern Mask Registers (PMR) -

ADDRESS: 17777116, 17777136
15

)
Figure x-x Pattern Mask Registers (Ports A and B)

5.2.5

Port Data Registers

Port Data registers are used to hold data that is read from or written
to the PIO. The Port Data Register format for ports A and B is shown
in Figure x-x. The" format for the Port C Data Register is shown in
Figure x-x.
These registers are read/write and are unaffected by a
reset.

ADDRESS: 17777032, 17777034
15

Figure x-x Port Data Registers (Ports A and B)

5-16

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)

ADDRESS: 17777036
15

I I I I

0'1

I I : P{EN I : ¥

1
MA·17215

Figure x-x Port C Data Register
Bits

Name

15:8

Description
Not used (read as ones)

1:4

PCEN

Port C bit enable - used as a write-protect
bit mask for bits <3:0>. A set bit in PCEN
inhibits the writing of the corresponding
bit in bits <3:0>. A cleared bit in PeEN
enables the writing of the corresponding
bit in bits < 3 : 0> •
~~

3:0

Port C data - contains the four bits of
data to be read by or written to port C.
Subject to masking according to the
value of PCEN.

5.2.6

PIO Counter/Timer Control Registers

There are three PIO counter/timers numbered 1, 2, and 3.
Each PIO
counter/timer has a set of six control registers which specify the
operation that the counter/timer performs.
The
registers
are
described in the paragraphs that follow.

5.2.6.1 PIO Counter/Timer Mode Specification - Each counter/timer has
a Mode Specification Register (Figure x-x). These registers define an
operational mode for a counter/timer and specify which external
control and status lines' are used.
They are cleared upon reset.
Access is read/write.

5-17

KXJ11-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

4/3/86

ADDRESS: 17777070, 17777072. 17777074

else

ECE

EGE

EOE
ETE
Figure x-x Counter/Timer Mode Specltlcatlon
(Counter/Timers 1, 2, and 3)

Bit.s

Name

15:8

REB

Description
Not used (read as ones)

C/SC

Continuous/single cycle - When set, the
time constant value used initially is
reloaded and the countdown sequence is
repeated when the counter reaches zero.
When cleared, the countdown sequence is
terminated when the counter reaches zera~

EOE

External output enable - When set, the
output of the counterltimer is provided
on the I/O line associated with that
particular. counter/timer (see Table
x-x). This bit must be programmed as an
output in the Data Direction Register of
its port. When cleared, external access
to the counter/timer is disabled.

ECE

External count enable - When set, the IIO
line of the port associated with_J'.he
counter/timer is used as an external
counter input (see Table x-x). The
corresponding bit must be programmed as
an input. When cleared, external access
is disabled.

ETB

External trigger enable - When set, the
I/O line of the port associated with the
counter/timer is used as a trigger input
to toe counter/timer (see Table x-x). The
corresponding bit must be programmed as
an input. When cleared, external access
is disabled.

EGB

External gate enable - When set, the I/O
line associated with the counter/timer
is used as an external gate to the
counter/timer (see Table x-x). This
allows the external line to suspend or
5-18

KXJll-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)
continue the countdown in progress by
toggling the line. When cleared, external
access is disabled.
2

REB

Retrigger enable bit - When set, triggers
that occur during a countdown sequence
cause a new countdown to begin. When
cleared, triggers that occur during a
countdown sequence are ignored.

1:0

DSC

Output duty cycle select DSC
00
01
10
11

Output Duty Cycle
Pulse output
One-shot output
Square wave output
Reserved

External access to the counter/timers is provided via the following
I/O lines:
Table x-x Counter/Timer External Access
CIT 1
Function
CIT 2
CIT 3
Port B 4
Port B 0
Port C 0
Counter/Timer Output
Port B 5
Port B I
Port C 1
Counter Input
Port C 2
Port B 6
Port B 2
Trigger Input
P,ort C 3
Port B 7
Port B 3
Gate Output

5.2.6.2 PIO Counter/Timer Command And Status - Each counter/timer has
a Command and Status Register which is used to control and monitor
timer operation. These registers are cleared upon reset.

Figure x-x Counter/Timer Command and Status
(Counter/Timers 1, 2, and 3)

ADDRESS: 17777024,17777026,17777030
'5

IUS

5-19

ERR

TeB

Rce

GeB

CIP

KXJ11-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

Bits

Name

15:8

4/3/86

Description
Not used (read as ones)

IUS

Interrupt under service - When set,
indicates that this counter/timer is
engaged in an interrupt acknowledge
sequence. Interrupt requests at the same
level or lower are disabled. This bit is
read/write.

Interrupt enable - When cleared, this
counter/timer is prevented from requesting
an interrupt or engaging in an interrupt
acknowledge sequence. When set, the
interrupts are enabled. The bit is
read/write.

Interrupt pending - When set, indicates
that this counter/timer requires ser~ice.
The bit is automatically set each time
the counter/timer reaches its terminal ~~
count. When cleared, indicates that the
counter/timer does not require service.
This bit is read/write.
IUS, IE, and IP are written according to
the following command codes:
Bits <7:5>
000"
001
010
all
100
101
110
111

Command
Null (no"effect)
Clear IP and IUS
Set IUS
Clear IUS
Set IP
Clear IP
Set IE
Clear IE

ERR

Interrupt error - When set, indicates
that the counter/timer has reached a
terminal count before the previous
terminal count has been serviced.
This bit is read-only.

RCC

Read counter control - When set, causes
the contents of the Counter/Timer Current
Count Register (which normally follows
the down counter) to be frozen until the
least significant byte of the register is
read. This cit cannot be set unless the
counter/timer is enabled in the Master
Configuration Control Register.
5-20

KXJl1-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)
2

GCB

Gate command bit - When set, starts or
resumes the countdown sequence. When
cleared, halts the countdown sequence.
This bit is read/write.

rTCB

Trigger command bi t - When set, t'he
down-counter is loaded with the time
constant value and a countdown sequence
is init"iated. This bit is write-only and
always read as zero.

CIP

Count in progress - When set, indicates
that a countdown sequence is in progress.
It is automatically set when when the
down-counter is loaded with the time
constant value. It is automatically
cleared when the down-counter reaches
zero. This bit is read-only.

5.2.6.3 PIa Counter/Timer Time Constant - Each counter/timer has a
register which contains a time constant value. This valu6 is loaded
into the down-counter of a counter/timer when a trigger is detected.
Each register is 16 bits wide and is accessed as two consecutive bytes
(bit 7 of the Msa is bit 15 of the PIO Counter/Timer Time Constant
Register).
Refer to Figure x-x for the register format. These
registers are read/write and are unaffected by a reset.
ADDRESS: 17777054, 1 7777060, 17777064 - MOST SIGNIFICANT BYTE
ADDRESS: 1 7777056, 1 7777062, , 7777066 - LEAST SIGNIFICANT BYTE
15

10,' 09

Figure x-x Count'er/Timer Time Constant
(~ounter/Timers 1, 2, and 3)

5.2.6.4 PIO Counter/Timer Current Count - Each counter/timer has a
Current ·Count Register (Figure x-x).
This register follows the
contents of the appropriate down-counter until a 1 is written into the
RCC bit of the Status/Control Register.
When this happens, the
contents of the Current. Count Register are frozen until the least
significant byte of the register is read. Then the register follows
the contents of the down-counter again. Th~ countdown sequence is not
affected.
Each register is 16 bits wide and is accessed as two
consecutive bytes (bit 7 of the Msa is bit 15 of the Current Count
Register).
A reset forces the Current Count Register to follow the

5-21

KXJll-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)
down-counter.

4/3/86

Writes to the Current Count Register are ignored.

ADDRESS: 17777040, 1 7777044, 1 7777050 - MOST SIGNIFICANT BYTE
ADDRESS: 1 7777042. 1 7777046, 1 7777052 - LEAST SIGNIFICANT Byre
15

Figure x-x Counter/Timer Current Count
(Counter/Timers 1, 2, and 3)

5.2.7

Interrupt Related Registers

Interrupt related registers are registers used in the handling of PIOinterrupts.
Three of these are three vector registers: one for port
A, one for port B, and one shared by the three counte~/timers.
Another register is provided to indicate which devices need service in~~
a plolled environment.

5.2.7.1 Interrupt Vector Register - The Interrupt Vector Register
holds the vector used during an interrupt acknowledge operation. The
native firmware initializes the vector for port A at 200 (octal), the
vector for port B at 204, and the vector for the counter/timers at
210. If the MIE bit. of the Master Interrupt Control Register is set,
bits 1, 2, and 3 of the vector are affected as shown:
Ports A and B
OR-Priority Encoded Vector Mode:
Bit 3
x

Bit 2

Bit 1

Encodes the number of the highest
priority bit with a match.

All other modes (see Port Command and Status Register description):
Bit 3
ORE

Bit 2
IRF

Bit 1
PMF

Bit 2

Bit 1

No error
Error

Counter/Timers

o
o

1
1

o
1
o

5-22

Counter/timer 3
Counter/timer 2
Counter/timer 1
Error

KXJll-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)
This register is read/write and is unaffected by a reset.
of the Interrupt Vector Register is shown in Figure x-x.

The

format

ADDRESS: 17777004. 17777006. 17777010
15

VEP .:

Figure x-x Interrupt Vector RegJster

5.2.7.2 Current Vector Register - The Current Vector Register is a
read-only register. When read, it returns the vector that would have
been returned during an interrupt acknowledge cycle if the device had
had the highest priority interrupt pending. The order of priority
(highest to lowest) is counter/timer 3, port A, counter/timer 2, port
S, counter/timer 1.
If no enabled interrupts are pending~or if the
PIO is reset, the register will contain a pattern of all l's. This i~
useful in a polled environment.
The format of the Current Vector Register is shown in Figure x-x.
ADDRESS: 17777076
15

: :

Figure x-x Current Vector Register

5.2.8

I/O Suffer Control Register

The PIO is protected from the connector· by a set of IEEE 488
compatible buffers.
The buffers are controlled by the I/O Buffer
Control Register (Figure x-x).
The register allows the user to
configure ports as inputs or outputs. Also, port driver buffers can
be configured to operate in open collector or active pull-up mode.
This register is cleared upon reset.

5-23

KXJII-C~ User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (pro)

4/3/86

ADDRESS: 17777140
15

" PCTT

PAHN
OIR

PABTT

'PAlN
OIR

Figure x-x I/O Buffer Control Register
Bits

Name

Description

PCTT

Port C buffer control - When set,
configures the port C drivers as
active pull-up drivers.·When cleared,
the port C drivers are open collector.

PABTT

Ports A and B buffer control - When •
set, configures the port A and.B drivers
as active pull-up drivers. When clearedr~
the port A and B drivers are open
collector.

13:10

PC DIR

Port C direction - If a bit is set,
the corresponding port C bit is a driver.
If a bit is cleared, the corresponding
port C bit is a receiver.

PAHN DIR

Port A high nibble direction - When set,
the port A high nibble bits <7:4> are
receivers. When cleared, the port A
high nibble bits are drivers.

PALN DIR

Port A low nibble direction - When set,
the port A low nibble bits <3:0> are
receivers. When cleared, the port A
low' nibble bits are drivers.

7:0

PB DIR

Port B direction - If a bit is set, the
corresponding port B bit is a driver.
If a bit is cleared, the corresponding
port B bit is a receiver.

5.3

PROGRAMMING THE I/O PORTS

This section describes how to program the 'I/O ports and provide
example programs. In particular this section describes how to use the
I/O ports in the following modes:
as bit ports, as ports with
handshake,' in 16-bit linked mode, and with the DNA controller. The
5-24

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)
use of the pattern recognition logic will also be discussed.

5.3.1

Programming The I/O Ports As Bit Ports
~

•

Using the I/O ports as bit ports provides ~p to 20 lines for control
and status. Each bit in ports Band C may be independently configured
to be an input or a~ output. Port A must be configured on a nibble
(4-bit) basis.
Programming the PIO as a bit port is straightforward. First, the Port
Mode Specification Register is used to select the port as a bit port
with or without pattern matching.
Then the Bit Path Definition
Registers are used to determine the polarity, direction, and special
characteristics of the bits of the port. If pattern recognition is
enabled the Pattern Definition Registers must also be initialized. It
is then a simple matter to write to the output data buffer to providethe correct control signals and to read the input data buffer to
monitor status.
•
The following program provides an example for using the PIO in the bit~~
mode:

;+
;
;

·
·

,
,

.TITLE

PI01.MAC

This program provides an example of how to program the PIO's
I/O ports as bit ports. This program utilizes the PIO
loopback connector (Part #H3021 or 54-16227) which makes the
following connections:

,·
;

;

C3
C2

,·

BO
B1

After this program has been assembled and linked on the
development machine use the RUI utility of the KXJ11-CA Software
Toolkit to load the program into the KXJ11-CA to execute as
shown in this example: .
SET 2
LOAD PI01.SAV
EXECUTE
!OOT

;
;

;

! 001152
!R2/000000
! 1154/041101
1001156/042103
1001160/043105

5-25

KXJ11-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

,·

,
,•
,•
·,

4/3/86

00·1162/177507
001164/041101
001166/042103
001170/043105
001172/000107
001174/000000
"'C
EXIT

,•
,• A non-zero result in R2 indicates that an error has occurred.
,•

(Try
running the test without the loopbqck connector). Location 1154 is
the beginning of the output buffer. Location 1164 is the beginning
of the input buffer •

., -Register Assignments
MIC
MCC
PAMOOE
PAPOL
PADOIR
PASIO
PADATA

==s_
==
=s=
==
s_
==

177000
177002
177100
177104
177106
177110
177032

PBMODE
PBPOL
PBOOIR
PBSIO
PBDATA

:sa

s=
s_

177120
177124
177126
177130
177034

IOCNTL

177140

START: :
MTPS

#340

. Initialize PIO

MOVB

#l,MIC

CLRB

MIC

recognition of
.,. Inhibit
interrupts
Reset device and inhibit interrupt

,. requests

Enable device (interrupts still
inhibited)

., Set-up Port A
CLRB
CLRB
CLRB
CLRB

Port A: bit port, no pattern match
Port A bits are non-inverting
Port A bits are output bits
Normal output

PAMODE
PAPOL
PADDIR
PASIO

; Set-up Port B
CLRB
PBMODE
CLRB
PBPOL
NOVB
#377,PBDDIR
CLRB
PBSIO

; Port B: bit port, no pattern match
; Port B bits are non-inverting
Port B bits are input bits
Normal input
5-26

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)

NOV

Set-up the PIO buffers
#1400, IOCNTL
configure the PIO buffers for
; A-output and B-input

; Initialize GPRs
MOV
#OUTBUF,RO
MOV
'#INBUF,Rl
CLR
R2

; Point to data to be output
; Point to input data buffer
R2 will indicate error status

Flush input buffer
TSTB
PBDATA
Enable Ports A and B and send the data
MOVB
#204,MCC
; Enable ports A and B
1$:

MOVB
NOP

(RO)+,PADATA

MOVB

PBDATA,(Rl)+

; Move data out of Port A

and into Port B

Test to see if done
TSTB
(RO)
BPL
lS

; IF (RO) is positive
; THEN transfer another byte
; ELSE check if data is valid

; Compare original data with received data
MOV
#OUTBUF,RO
Point to output data buffer
MOV
#INBUF,Rl
Point to input data buffer
2$:

3$:

; Test to see if done
TSTB
(RO)
BMI
3$
(RO)+,(Rl)+

CMPB
BEQ

INC

OUTBUF: • BYTE

negative
. IFTHEN(RO)doneis comparing

ELSE do another compare
; Compare bytes
; IF bytes are equal
THEN test another pair
ELSE indicate error
; A non-zero value of R2 indicates
an error
Branch here upon completion

101,102,103,104,105,106,107,-1

• EVEN

INBUF:

.BLKB

. END

START

5.3.2

Programming The I/O Ports As Ports With Handshake

Ports A and B may be configured as ports with handshake to facilitate
transferring data on a byte-by-byte basis. Port C is used to provide
the handshake lines. In addition, Port C may use the REQUEST line to
5-27

KXJll-C~

User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

4/3/86

utilize a DNA controller to transfer the data. See table 1 for a
description of the Port C handshake lines. Figure 1 shows how two
PIOs can be connected directly together to transfer data and the
handshake lines that are utilized.
OUTPUT

INPUT

"+--------+
!
I

~--------+
I
PIO

1-----------------\ 1
1
!

DATA

\1
/1

PIa

1-----------------/ 1
1
1

DAVI ----------------->/ACKIN
ACKIN!<----------------- IRFD
!
I

+--------+

I
1

1
1

I
!
I

+--------+

Figure x-x PIO Handshake Lines
Th4! handshakes that are available are: Interlocked, Strobed, Puls~d,
and 3-Wire. A short description of each handshake type follows:
WhE!n using the Int:erlocked Handshake any action by the PIO must be
acknowledged by the external device before the next action can take
place. In other words, an output port does not indicate that it has
ne~,
data available until the external device indicates that it is
ready for data. Likewise, and input port does not indicate that it is
ready for new data until the external device indicates that the
previous byte of data is no longer available, thereby acknowledging
thE~ input port's acceptance of the last byte.
The Strobed Handshake uses external logic to "strobe" data into or out
of a port.
In contrast to the Interlocked handshake, the signal
indicating that the port is ready for another data transfer operates
independently of the ACKIN input. External logic must ensure the data
transfers at the appropriate speed.
The Pulsed Handshake is used to interface to mechanical devices which
require data to be held for relatively long periods of time in order
to be gated in or out of the device. The logic is the same as the
Interlocked Handshake except that Counter/Timer 3 is linked to the
handshake logic to add the appropr~ate delays to the handshake lines.
The 3-Wire Handshake may be used so that one output port can
communicate
to
several
input
ports simultaneously.
This is
essentially the same as the Interlocked Handshake except that two
individual lines are used to indicate when an input port is ready for
data (RFD) and when it has accepted data (DAC).
Because this
handshake requires three lines only one por~ can use the 3-Wire
Handshake at a time.
Table x-x Port C Handshake Lines
Port C Bits
5-28

KXJll-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)
Port A/B Configuration

Pin C3

Pin C2

Pin Cl

Pin CO

+---------------------------+-----------+---------+-----------+--------+
'Ports A , B • Bit Ports
IBit I/O
IBit I/O IBit I/O
IBit I/O I
+-----------------------~---+~-~-~------+---~---~-+------~-~--+-~-~-~--+

IPort A • Input or Output
I (Interlocked,. Strobed,
I or Pulsed Handshake)*

IRFO or DAV IACKIN
I
. I
I
I

IREQUEST
ISit I/O I
lor Bit I/O I
I
I

I (Interlocked, Strobed,
I or Pulsed Handshake)*

lor Bi t I/O I
\
I

I
I

I (3-Wire Handshake)

I (Output)

I (Input)

lor Bit I/O I (Output) I

I (Output)

I (Input)

lor Bit I/O I (Input) I

+---------------------------+-----------+---------+-----------+--------+
IPort B • Input or Output
I REQUEST
ISit I/O IRFO or DAV IACKIN
I
I

+--------.------------------+-----------+---------+-----------+--------+
\Port A or'B = Input Port
IRFD
\DAV
I REQUEST
IDAC
I
+---------------------------+-----------+---------+-----------+--------+
~ Port A or B
Output Port 'DAV
I DAC
I REQUEST
'RFD
,
==

I (3-Wire Handshake)

+---------------------------+-----------+---------+----------~+--------+

IPort A or B • BidirectionallRFD or DAV IACKIN
I (Interlocked or Strobed
I
I
I
I
I Handshake)

I REQUEST
lIN/OUT"
lor Bi t I/O I
•
I
I

I
I
I

+---------------------------+-----------+---------+-----------+------~+

* Both Ports A , B may be specified as input or output ports with
the Interlocked, Strobed, or Pulsed Handshakes at the same time
if neither uses REQUEST. Only one port can use the Pulsed
Handshake at a time.

When Ports A and B are configured as ports with handshake they must
also be configured as single- or double-buffered. Double-buffering a
port allows more time for the interrupt service routine to respond to
a data transfer. A second byte of data is input to or output from the
port before the interrupt for the first byte is serviced.
A
single-buffered
port
is
used where it is important to have
byte-by-byte control over the transfer or where it is important to
enter the interrupt service routine in a fixed amount of time after
the data has been accepted/output.
The REQUEST line may also be used by ports with handshake.
This
control line enables the PIO to signal the DMA controller of the
KXJll-CA that the port wishes to transfer
data
without
CPU
intervention.
The operation of the REQUEST line is dependent on the
Interrupt on Two Bytes (ITB) bit in the Port Mode Specification
Register. If ITS • 0 then the REQUEST line goes active anytime a byte
is available to transfer. ' If ITB • 1 then the REQUEST line does not
assert until two bytes are available to transfer. The implementation
of the PIO on the KXJll-CA requires that only Port A be used for DMA
transfers.
Since the REQUEST line utilizes one of the Port C bits
Port B must be programmed as a bit port when Port A uses the REQUEST
facility.
The following example programs display the
used as a port with handshake:
.TITLE

PI02.MAC
5-29

capabilities

the

PIO

User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

KXJ11-C~

,·
,•
,
,·
,·

4/3/86

This program demonstrates the ability of the PIa to transfer data
on a byte-by-byte basis. The program uses the Interlocked
Handshake to transfer data from Port A to Port B. Both ports are
configured as single-buffered. The PIO loopback connector (part
'&3022 or 54-16227) or a functional equivalent is required to·
successfully run this program.

;
;

After this program has been assembled and linked on the
development machine use the KUI utility of the KXJ11-CA Software
Toolkit to load the program into the KXJII-CA to execute as
shown in this example:

;

SET 2
LOAD PI02.SAV

EXECUTE
tOOT

;

;
;
;

;

!001214
t1262/06S151
!001264/066153
!001266/067155
!001270/070157
1001272/000377
1001274/065151
1001276/066153
!001300/067155
!001302/070157
!001304/000000

;

! "'C

;

EXIT
This verifies that the contents of the output buffer (location 1262
were successfully transferred to the input buffer (location 1274).
: Register Assignments

=-=- 177000
177002
PAVEC
=. 177004
PASTAT =. 177020

MIC
MCC

PADATA
PAMOOE
PAHDSH
PAPOL
PASIO

PBVEC
PBSTAT
PBDATA
PBMODE
PBHOSH
PBPOL

=======
==

.••
.=••
••

177032
177100
177102
177104
177110
177006
177022
177034
177120
177122
177124
5-30

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)
PSSIO

••

177130

PCPOL
PCDDIR

••
••

177012
177014

IOCNTL, ==

177140

START: :
MTPS

1340

; Inhibit recognition of interrupts

MOVS

#1,MlC

CLRB

MlC

; Reset device and inhibit interrupt
requests from the PIO
Enable device (interrupts still
inhibited)

MOVB
MOV
MOV

1200,PAVEC
lOUT., @#200
#340,@#202

MOVS
MOV
MOV

#204,PSVEC
IIN,@#204
#J40,@#206

. .,

Port A interrupt vector
.; Set up
and PSW
; Set up Port B interrupt vector
and PSW

; Set-up Port A
MOVS
#220,PAMODE
CLRB
PAHDSH
CLRB
PAPOL
CLRB
PASlO
MOVS
#300,PASTAT

; Port A: Output Port, single-buffered
; Use interlock handshake
; Port A bits are non-inverting
; Normal output
Enable Port A interrupts

; Set-up Port B
MOVS
#120,PSMODE
CLRB
PBHDSH
CLRB
PBPOL
CLRB
PBSlO
MOVS
#300,PSSTAT

Port B: Input Port, single-buff~red
Use interlock handshake
Port B bits are non-inverting
; Normal input
; Enable Port B interrupts

; Set-up the Port C handshake lines.
; All handshake lines are configured as inputs - even
; if they aren't!
MOVS
#377,PCDDlR
Port C bits are inputs
; Set-up the PIO b~ffers
MOV
#165400, IOCNTL

;

; Set-up data areas
MOV
#OUTBUF,RO
MOV
#INBUF,R1
; Enable Interrupts
MOVB
#224,MCC
MOVB
#200,MIC
MTPS
10

configure the PIO buffers for A=out
B-input, CO,C2=input, C1,C3=output
Point to Output Buffer
Point to Input Buffer

Enable ports A, B, and C
Enable MIC
; Enable recognition of interrupts
5-31

KXJII-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

4/3/86

; Start the first transfer
MOYS
#200,PASTAT
Set IP to initiate a transfer

,· Wait here for the interrupts

BR
OUT: :

TSTB
BMI

.....

'(RO)
1$

MOVB

(RO)+,PADATA

,· IF (RO) are negative

THEN transfers are complete
ELSE transfer another byte
Move byte to the Port A output data
, register

,· Clear IP when done

MOVB
MOVB
RTI

#240,PASTAT
#l40,PASTAT

MOVB

PBDATA, (R1) +

MOVB
RTI

#140,PBSTAT

OUT:8UF:

• BYTE
• EVEN

151,152,153,154,155,156,157,160,-1

INBUF:

.BLKB

• END

START

1$:
2$:

IN: :

Clear IUS on each pass

;

5-32

Move byte from Port B input data
register
Clear IUS on each pass

KXJII-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL 1/0 CONTROLLER (PIO)
5.3.2.1

Example.TITLE

;

PI03.MAC

This program is basically the same as PI02.MAC with the
with the exception that the ports are double-buffered.
The PIa loopback connector (part #H3022 or 54-16227) or a
functional equivalent is required to successfully run this program.

· After this program has been assembled and linked on the

,·
;

development machine use the KUI utility of the KXJll-CA Software
Toolkit to load the program into the KXJ1l-CA to execute as
shown in this example:
SET 2
LOAD PI03.SAV

EXECUTE

,
;
;

ODT

001214
1272/065151
001274/066153
001276/067155
001300/070157
001302/000377
!001304/065151
!001306/066153
!001310/067155
!001312/070157
1001314/000000
!AC

EXIT
;

This verifies that the contents of the output buffer (location 1272
were successfully transferred to the input buffer (location 1304).
; Register Assignments
NIC
NeC

••
••

177000
177002

PAVEC
PASTAT
PADATA
PAMODE
PAHDSH
PAPOL
PASIO

••

177004
177020 '
177032
177100
177102
177104
177110

PBVEC
PBSTAT
PBDATA
PBMODE

:::II=:::II=:::II=-

==
=====:11
=:::II===-

177006
177022
177034
177120
5-33

KXJ11-CA User's Guide
PRELIMINARY
PARALL1~L I/O CONTROLLER (PIO)
PBHDSH
PBPOL
PBSIO

••
••

••

177122
177124
177130

PCPOL
PCDOIR

•• ·177014

••

177012

IOCNTL

••

177140

START: :
MTPS

4/3/86

#340

Inhibit recognition of interrupts
device and inhibit interrupt
. Reset
requests from the PIO

MOVS

#l,MIC

CLRB

MIC

MOVS
MOV
MOV

#200,PAVEC
#OUT,@#200
#340,@#202

; Set up Port A interrupt vector
; ••• and PSW

MOVB
MOV
MOV

#204,PBVEC
#IN,@#204
#340,@#206

; Set up Port B interrupt vector
; ••• and PSW

; Enable device (interrupts still
inhibited)

; Set-up Port A
MOVS
#240,'PANODE
CLRB
PAHDSH
CLaRB
. PAPOL
CLRB
PASIO
MOVS
#300,PASTAT

; Port A: Output Port, double-buffered
; Use interlock handshake
Port A bits are non-inverting
Normal output
Enable Port A interrupts

: Set-up Port B
MOVB
#140,PBMODE
CLRB
PBHDSH
CLRB
PBPOL
CLRB
PBSIO
Mova
#300,PBSTAT

; Port B: Input Port, double-buffered
; Use interlock handshake
; Port B bits are non-inverting
; Normal input
; Enable Port B interrupts

; Set-up the Port C handshake lines.
All handshake lines are configured as inputs - even
; if they aren't!
MOVB
#377,PCDDIR
; Port C bits are inputs
; Set-up the PIO buffers
MOV
#165400,IOCNTL; configure the PIO buffers for A·out
a-input, CO,C2·input, el,e3-output
; Set-up data areas
MOV
#OUTBUF,RO
MOV
#INBUF,Rl

; Point to Output Buffer
; Point to Input Suffer

; Enable Interrupts
MOVB
#224,MCC

; Enable ports A, S, and C
5-34

KXJll-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)
MOVB
M'1'PS

#200,MIC
#0

Enable MIC
; Enable recognition of interrupts

: Start the first transfer
MOVB
#200,PASTAT
Set IP to initiate a transfer
Wait here for the interrupts

. OUT::
BMI

(RO)
1$

MOVB

(RO)+,PADATA

MOVB

(RO)+,PADATA

2$
·#240,PASTAT
#-140,PASTAT

TSTB

1$:
2$:

MOVB
MOVB
RTI

; IF (RO) are negative
THEN transfers are complete
ELSE transfer another byte
Move 1st byte to the Port A output
, data register
; Move 2nd byte to the Port A buffer
register

; Clear IP when done
Clear IUS on each pass

IN: :

MOVB

PBDATA, (Rl) +

MOVB

PBDATA, (Rl) +

MOVB
RTI

#140,PBSTAT

OUTBUF: • BYTE

Move 1st byte from Port B input data
register
Move 2nd byte from Port B buffer
, register
Cle·ar IUS on each pass

151,152,153,l54,lS~,156,157,160,-1

• EVEN

INBUF:

.BLKB

• END

START

5-35

KXJll-C~

User's Guide

. PRELIMINARY

4/3/86

P ARALLE1C, I/O CONTROLLER ( PI 0)

5.:3.2.2

,·

,•
,•
,•
;
;
:

:
;
;
;

;
;
;

Example-

This example shows something a little more practical - one
KXJll-CA transferring data to another. Two programs follow:
one accepts data through Port B using the double-buffered
mode (PI04I.MAC): the second one sends data out of Port A
using the double buffered mode (PI040.MAC). In order to
successfully run these programs the'KXJ1I-CAs must be connected
by a "straight-thru" ribbon cable which is given a half twist.
In other words, it should make the same connections that the
PIO loopback connector does. (A1-B1,A2-B2, ••. A7-B7,CO-C3,C1-C2).
Each program should be assembled and linked separately on the
development machine. Then use the KUI utility of the KXJll-CA
Software Toolkit to load the programs into the KXJ11-CAs to execute
as shown in this example:
SET 3
LOAD PI04I.SAV
EXECUTE
SET 2
LOAD PI040.SAV
',EXECUTE
SET 3
lOOT
1001130
!1152/065151
:1001154/066153
1001156/067155
!!001160/070157
n001162/000000
!~C

lOCIT

This verifies that the data was successfully transferred to
the input buffer of KXJll-CA #3 •

.;-------------------------------------------------------------------

, _-----------------------------------------------------------------.
.TITLE

PI04I.MAC

: Register Assignments
MIC
MCC

==-

177000
177002

PBVEC
PBSTAT
PBDATA
PBMODE
PBHDSH
PBPOL
PBDOIR

==-

177006
177022
177034
177120
177122
177124
177126

:11::11

=::11
=::11
==
==
:11=
=::11

5-36

KXJll-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)
PBSIO

177130

PCDDIR

177014

IOCNTL

177140

START: :

IN: :

MTPS
MOVa

#340
..II,MIC

CLRB

NIC

Mova
MOV
MOV

'204,PBVEC
'IN,@#204
'340,@#206

; Set up Port B interrupt vector
; ••• and PSW

MOVB
CLRB
CLR
CLR
MOVB

'140,PBMODE
PBHDSH
PBPOL
PBSIO
'30o,PBSTAT

;
;
;
;
;

MOVB

#377,PCDDIR

; Port C bits are inputs

MOV

'165400, IOCNTL

MOV

#INBUF,Rl

; Point to input data buffer

MOVB
MOVB

#22o,MCC
#20o,MIC

; Enable ports Band C
; Enable MIC

MTPS
BR

; Enable recognition of interrupts
; Wait here for the interrupts

MOVB

PBDATA, (R1) +

Mova

PBDATA, (R1) +

Mova

'140,PBSTAT

; Inhibit recognition of interrupts
; Reset device and inhibit interrupt
,• requests from the PIO
; Enable device (interrupts still
inhibited)

; configure the PIO buffers for A=out
a-input, CO,C2=input, Cl,C3-output

,•

; Move 1st byte from Port B input data

, register
; Move 2nd byte from Port B buffer
,· register
; Clear IUS on each pass

RTI

INBUF:

.BLKB

.END

START

Port B: Input Port, double-bufferedUse interlock handshake
Port B bits are non-inverting
Normal input
Enable Port B interrupts

5-37

KXJ11-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)
5.3.2.3

4/3/86

Example.TITLE

PI040.MAC

: Register Assignments
MIC
MCC
PAVEC
PASTAT
PADATA
PAMOOE
PAHDSH
PAPOL
PADOIR
PASIO

..-.==

177000
177002

===
===
==-

177004
177020
177032
177100
177102
177104
177106
177110

PCPOL
PCDOIR

==.
=-

177012
177014

IOCNTL

177140

START: :
MTPS
MOVB

#340
#1,MIC

Inhibit recognition of interrupts
; Reset device and inhibit interrupt
, requests from the PIO
; Enable device (interrupts still
inhibited)

CLRB

MIC

MOVB
MOV
MOV

#200,PAVEC
#OUT,@#200
#340,@#202

MOVB
CLRB
CLR
CLR
MOVB

#240,PAMOOE
PAHDSH
PAPOL
PASIO
#300,PASTAT

MOVB

#377,PCDDIR

MOV

#165400,IO~L

MOV

#OUTBUF,RO

; Point to output data buffer

MOVB
MOVB
MTPS
. MOVB
BR

#24,MCC
#200,MIC
#0
#200,PASTAT

Enable ports A and C
; Enable MIC
Enable recognition of interrupts
Set IP to initiate a transfer
Wait here for the interrupts

Set up Port A interrupt vector
and PSW
; Port A: Output Port, double-buffered
; Use interlock handshake
Port A bits are non-inverting
; Normal output
Enable Port A interrupts
Port C bits are inputs
the PIO buffers for A=out
. configure
a-input, CO,C2=input, CI,C3-output

OTJT: :
5-38

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)

TSTB

2$
#240,PASTAT
#140,PASTAT

, Clear IUS on each pass

(RO)
1$

MOVB

(RO)+,PADATA

MOVB
1$:
2$:

(RO)+,PADATA

·
· Move 1st byte to the Port A output
,· data register
Move 2nd byte to the Port A buffer

BMI

BR
MOVB
MOVB
RTI

, IF (RO) are negative
, THEN all data has been transferred
,· ELSE do another transfer

· register

;

Clear IP when done

OUTBUF: :

• BYTE

151,152,153,154,155,156,157,160,-1

• END

START

5-39

KXJ11-CA User's Guide

PRELIMINARY

4/3/86

P ARALLE:t. IIO CONTROLLER (p I 0)

5.3.2.4
;
;
;
;
;
;
;

,·

Example-

The following two programs demonstrate how the DTC may be used
to transfer data from the PIO to KXJ11-CA local memory. OTC
transfers may only be accomplished using Port A of the PIO.
It is not possible to properly connect two PIOs with a ribbon
cable because the handshake lines will not align correctly when
connecting Port A to Port A. Therefore it is necessary to build
a cable that ~kes the following connections:

. ,•

Input Port A
Output Port A
AO
AO
A1
Al
<~------->

<-------->

,
,·
,
,
,

··
··

C2
C3

<-------->
<-------->
<-------->

C3
C2

It is also necessary to place a jumper between posts M48 and M49
so that the REQUEST line from the PIO may signal the OTC. For more~~
information about programming the OTC please refer to Section x.x.
i

;
;
i

After each program has been assembled and linked on the
development machine use the KUI utility of the KXJ11-CA Software
'roolki t to load the programs into a KXJll-CA to execute as
~shown in this example:

·,, SET 3

PIOSI.SAV

]~OAD
I~XECUTE

SET 2
LOAD PI050.SAV

·· EXECUTE
SET 3
,· lOOT
,· !

,
,

1001140
!1140/000777
t001142/065l5l
1001144/066153
1001146/067155
!001150/070157
!001152/001602

··
,· ! "'C
,·
,· Examining the contents of the input buffer (location 1142)
,
,

verifies that the data was successfully transferred.

5-40

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)
5.3.2.5

Example-

.TITLE

PIOSI.MAC

; This program transfers data from Port A of the PIO
to local memo~y by utilizing the DTC
: Register Assignments

START::

MMREG
CMDREG
CASTF1
CAOFl

••
••

=-.
=-.

174470
174454
174444
174440

NIC
NCC

••
••

177000
177002

PAVEC
PASTAT
PADATA
PAMODE
PAHDSH
PAPaL
PADOIR
PASIO

••

177004

••
••
••
••
••
••

177100
177102
177104
177106
177110

PCPOL
PCDOIR

••
••

177012
177014

IOCNTL

=-. 177140

MTPS

#340

=-. 177020
177032

; Inhibit recognition of interrupts

; Initialize the DTC - for more information on the DTC
; refer to Section x.x.
MOVB
#154,MMREG
; Load Master Mode Reg to Disable DTC
Reset the DTC
CLRB
CMDREG
MOV
#O,CASTFl
Load the CH1 Register SEG/TAG
MOV
#RELOAD,CAOFl
Load the CH1 Register Offset
Load Mas"ter Mode Reg to "Enable DTC
MOVB
#155,MMREG
Start Chain Channel 1
MOVB
#241,CMDREG
; Initialize the PIO
MOVB
#1,MIC
CLRB

MIC

; Set-up Port A
MOVB
#120,PAMODE
MOVB
#70,PAHDSH
CLR

PAPaL
5-41

Reset device and inhibit interrupt
requests from the PIO
Enable device (interrupts still
inhibited)
Port A: Input Port, single-buffered
Use interlock handshake, input
REQUEST
Port A bits are non-inverting

KXJ11-u\ User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)
CLR
MOVB

PASIO .
#2,PCPOL

MOVB

#377,PCDDIR

Normal input
Invert pin Cl - this is the line
that is used for the REQUEST signal
, Port C bits are inputs

·
#164377, IOCNTL ,· configure the PIO buffers for A-in
,• B-output, CO,C2-input, C1,C3-output
,· Point to input data buffer
#INBUF,Rl

MOV
MOV
MOVB

Enable ports A and C

#24,MCC

BR
INBUF:

4/3/86

.BLKB

Wait here while the DMA transfers
take place

; Chain Load Region
RELOAD: • WORD
•WORD
• WORD

001602

: Reload Word <Select CARA,CARB,COPC,CM>

000020 ; Current Address Register A Seg/Tag
padata+l; Current Address Register A Offset
; <This local address. is the source,
,• its address is held constant, since
, the DTC is doing byte transfers specify
,• the source address high byte>

•WORD
• WORD

000000
inbuf

J Current Address Register B Seg/Tag
: Current Address Register B Offset
: <This local address is the destination>

• WORD

000010

; Current Operation Count <Transfer 8 words>

. WORD
•WORD

000000
000001

: Channel Mode Register High
: Channel Mode Register Low
<No match conditions, do nothing upon
, completion, transfer type • Single Transfer
, CARA • source, byte transfers>

··
.END

START

5-42

KXJ11-CA User's Guide

PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)

5.3.2.6

Example.TITLE

PI050.MAC

,. This program transfers data out of Port A of the PIO
, utilizing the DTC

; Uegister Assignments
MMREG

CMDREG
CASTF1
CAOF1
MIC
MCC

.••
::11:11

••
::II.

••

174470
174454
174444
174440
177000
177002

PAVEC
PASTAT
PADATA
PAMODE
PAHDSH
PAPOL
PADDIR
PASIO

••
••
••
••
••
••

177004
177020
177032
177100
177102
177104
177106
177110

PCPOL
PCDDIR

••
••

177012
177014

IOCNTL

••

177140

MTPS

#340

:II.

S'r'ART: :

; Inhibit recognition of interrupts

; Initialize the DTC
MOVB
CLRB
MOV
MOV
MOVB
MOVB

#1~4,MMREG

CMDREG
#O,CASTFl
#RELOAD,CAOFl
#155,MMREG
#241,CMDREG

; Initialize the PIa
Move

#1,MIC

CLRB

MIC

#220,PAMODE
#050,PAHDSH

CLR
CLR

PAPOL
PASIO

, Start Chain Channel 1

; Reset device and inhibit interrupt
;. requests from PIO
; Enable device (interrupts still
, inhibited)

: Set-up Port A
MOVe
MOVB

·
,· Load the CHl Register Offset
·, Load Master Mode Reg to Enable DTC

, Load Master Mode Reg to Disable DTC
,· Reset the DTC
,· Load the CHl Register SEG/TAG

Port A: Output Port, single-buffered
; Use interlock handshake, output
, REQUEST
; Port A bits are non-inverting
; Normal output

5-43

KXJll-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

,• Pin Cl must be inverted - this is

MOVB

'2,PCPOL

MOVB

'377,PCDDIR

MOV

1165400,IOCNTL

MOV

' #OUTBUF,RO

MOVB

#24,MCC

the line used to signal the DTC
Port C bits are inputs

;

·
·

configure the PIO buffers for-A-out

, B-input, CO,C2-input, Cl,C3=output
, Point to output data buffer
Enable ports A and C

BR
OUTBUF: :
• BYTE
• EVEN

4/3/86

Wait here while the DMA transfers
complete
151,152,153,154,155,156,157,160,-1

; CHAIN LOAD REGION
RELOAD:

. WORD

001602

; Reload Word <Select CARA,CARB,COPC 4 CM>

• WORD

000000
outbuf

Current Address Register A Seg/Tag
Current Address Register A Offset
; <This local address is th~ source>

• WORD

• WORD
• WORD

5.3.3

000020 ; Current Address Register B Seg/Tag
padata+l; Current Address Register B Offset
; <This local address is the destination,
Hold the address, must specify high byte
for byte transfer>

. WORD

000010

; Current Operation Count <Transfer 8 words>

• WORD

000000
000001

; Channel Mode Register High
Channel Mode Register Low
; <No match conditions, do nothing upon
; completion, transfer type = Single Transfer
CARA = source, byte transfers>

.END

START

PROGRAMMING THE PIa COUNTER/TIMERS

This section describes how to program the PIa Counter/Timers
provides example programs demonstrating their capabilities.

and

Each of the three PIO Counter/Timers provides up to four lines for
external access.
If these external lines are used the corresponding
port pins must be available and programmed in the proper direction.
The following table displays which port pins correspond to the
5-44

KXJll-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIO)
Counter/Timer external access lines:
Table x-x PIO Counter/Timer External Access Lines
+--~----------~---~--~-~-~-------~----~-~--------~------~---~---+

Function

CIT 2

CIT 1

CIT. 3

+-------~-------~~----------------~---~-~----------~---~~-~-----+

I Counter/TImer Output
I Counter Input
I Trigger Input
I Gate Input

Port B4
Port BS
Port B6
Port B7

Port co
Port Cl
Port C2
Port C3

Port BO
Port Bl
Port B2
Port 83

I
I
I
I

+---------------------------------------------------------------+
The first step in programming a PIO Counter/Timer is to specify which
(i:f any) external lines are to be used, the output duty cycle, and
whether the cycle is continuous or single-cycle.
The following
figures display the available output duty cycles:
Output Duty Cycles
If Time Constant Value = 5
Pulse Output Mode
-> 500

nS <-

+-----+
I
I

---~-----~----~-----~---~~----------+

I
4

+-----I

I
4

One-Shot Mode

+-----+-----------------------------+
I
I
I
+-----+
------+
I
5

I
T

I
4

I
3

I
2

I
1

I
5

I
4

If Time Constant Value = 8
Square Wave Mode

+-----------------------+I
+------------------------------------+

I
T

I
8

I
6

I
5

I
2

Next, the Time Constant Registers must be loaded. Each Ceunter/Timer
contains two of these registers which are used to form the 16-bit
5-45

I
8

KXJII-CA User's Guide
PRELIMINARY
PARALLEL I/O CONTROLLER (PIO)

4/3/86

value that is loaded into the down-counter when the
triggered.

Counter/Timer

If external lines are to be used then the corresponding port pins
should be programmed as bit ports with the correct data direction.
Finally, theCo~nter/Timer enable bit for that port must be enabled in
the Master Configuration Control Register.
The down-counter is loaded and the countdown sequence is initiated
when the Counter/Timer is triggered. This trigger may occur because
the Trigger Command Bit (TCB) in the Command and Status Register js
set or because an external trigger input was asserted. Once the
countdown is initiated it will continue towards the terminal count as
long as the Gate Command Bit (GCB) in the Command and Status Register
is set and the Gate Input is held asserted (if it is enabled).
If a
trigger occurs during a countdown sequence the action taken is
determined by the Retrigger Enable Bit (REB). If REB ~ a then the
trigger is ignored, but if REB ~ 1 then the down-counter is·reloaded.
and a new countdown is initiated.
•

When the terminal count is reached the state of the Continuous/Single
Cycle bit (C/SC) in the Mode Specification Register is examined. If~A
clse ~ a then the countdown sequence stops. If C/SC ~ 1 then the time
constant is reloaded and a new countdown is initiated. If the
Interrupt Enable Bit (IE) is set an interrupt request is generated
when the down-counter reaches its terminal count. If a terminal count
occurs while the Interrupt Pending Bit (IP) then an error is indicated
by the Interrupt Error (ERR) bit.
The following program provides an example of how to
Counter/Timers:
.TITLE
;

program

the

PIO

CT1.MAC

This program demonstrates how to utilize one of the Counter/Timers
on the RXJII-CA. Counter/Timer 1 will be used in this program.
This counter/timer is clocked at a 500 ns rate. The time constant
used for the counter is 50,000. Therefore the countdown sequence
will take 25 ms. (500 ns x 50,000 = 25,000,000 ns = 25 ms). The
interrupt service routine waits until the countdown sequence has
completed 40 times and then outputs an 'A' out of the console
port. This should happen approximately one time a second. (25 ms
x 40 ~ 1 s).
After this program has been assembled and linked on the
development machine use the RUI utility of the KXJII-CA Software
Toolkit to load the program into the"KXJII-CA to execute as
shown in this example:
SET 2
LOAD CTl.SAV

EXECUTE
EXIT

5-46

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
PARALLEL I/O CONTROLLER (PIa)
Notice that the 'A's keep on coming after you exit KUI!

., Register Assignments

MIC
MCC
CTVEC
CTICON
CTIHI
CTILO
CTIMOD
START: :
MTPS

.-.=
~.

=.
~-

177000
177002
177010
177024
177054
177056
177070

#340

MOVB
CLRB

#l,MIC
NIC

; Reset PIO
Enable PIO (Interrupts disabled)

MOVB
MOV
MOV

#210,CTVEC
#ISR,@#210
#340,@#212

CLR

; Used as a counter

MOVB

#200,CTIMOD

MOVB
MOVB

#203,CTIHI
#120,CTILO

; Select continuous mode, no external
access, pulse output
; CT1HI and CT1LO combine to form
, 141520(8) =- 50000(10)

MOVB
MOVB
MTPS

#lOO,MCC
#200,MIC
#0

Enable Counter/Timer 1
Enable PIO interrupts
Enable recognition of interrupts

BISB

#306,CT1CON

Set IE,GCB,TCB - this starts the
countdown
; Wait here for the interrupts

Rl
Rl,#40.
2$
,
Rl
#101, @#177S,66

Increment the counter
IF this is not the 40th time
THEN count again
ELSE clear the counter and •••
;
send an 'A' to the console

BR
ISR:

INC
CMP
SHE

CLR

., -

2$;

Disable recognition of interrupts

MOVB

.
;

Initialize Counter/Timer vector
and ISR address

The console in this case is the"KXJl1-CA console - NOT the
development system console,. Therefore you'll have to hook a
terminal up to SLUI to se"e the 'A's pop out •
MOVB

Clear IUS and IP but don't bother
GCB

#44,CTICON

RTI
.END

START
5-47

CHAPTER 6
SERIAL LINE UNITS (SLUS)

6.1

OVERVIEW

The KXJll-CA has two serial line units (SLUs), SLUl and SLU2.
SLUl is also called the cons:ole port and is designed around the DLART_
(DC3l9) chip. SLUl is dedicated for a console device. For details on
the operation and programmin'g of the DLART, refer to the DLART Data
She1et included as part of this documentation package.
SLU:2 is also called the multiprotocol serial controller (MPSC) and has
two independent channels, A and B.
SLU2 is designed around the
uPD'7201 chip. For details on the operation of the MPSC, refer to the
MPSC: Data Sheet included as part of this documentation package. There
are three timers associated with SLU2 designed around the 8254 chip.
Inf()rmation on the.se timers is included here for completeness. Refer
to the 8254 Data Sheet included as part of this documentation package
for operational details.
The material that follows is of a summary nature and
DuutT and MPSC functions implemented on the KXJIl-CA.

6.2

describes

the

CONSOLE SERIAL PORT (SLUl)

SLUl provides the following features and capabilities for the
seri.al line:
o

Asynchronous operation,

Error detection overrun, framing, and BREAK detection

Internal baud rate generation from 300 to 38.4 K baud

Common baud rate for both transmitter and receiver

50- and 60-Hz real-time clock interrupt outputs

6-1

console

KXJll-CA User's Guide
SERIAL LINE UNITS (SLUs)

PRELIMINARY

4/3/86

o One stop bit only

6.2.1

SLU1 (Console) Registers

The console serial port (SLU1) is based on the DLART (DC3l9) chip.
All SLUl registers are contained in this chip. SLUl has a receiver
and a transmitter each of which has a control/status register and a
buffer register.
These registers are described in the sections that
follow. Note that these registers are the ones used for console aOT
operations.

6.2.1.1 Receiver Control/Status
Register
(RCSR) - The
Receiver
Control/Status Register (RCSR) is used to monitor and control the
operation of the SLUl receiver. This register is read-only.

ADDRESS: 17777560
15

Rev

ACT

Rev
IE

Figure x-x
Bits

Receiver Control/Status Register (RCSR)

Name

Not used (read as zeros)

15:12
11

RCV ACT

Receiver active - When set, the receiver
is active. Set when the start bit of
the input serial data is received. When
cleared, the receiver is inactive. Cleared
at 'the expected time of reception of the
stop bit (after RCV DN is set).
Not used (read as zeros)

10:8
7

Description

Rev ON

Set after a character has been received
a'nd is in the, receiver buffer register
(RBUF). Cleared when the character is read
from RBUF.
6-2

KXJl1-CA User's Guide

When set, allows an interrupt request to
be made when bit 7 (RCV DN) is set. When
cleared, disables interrupts from RCV DN.

RCV IE

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

Not used (read as zeros)

5:0

6.2.1.2 Receiver Buffer Register
(RBUF) - The
Receiver
Buffer
Register (RBUF) holds the most recent byte received and contains break
and error information for this byte. .RBUF is read-only.

ADDRESS: 17777562
00

ERR

ERR
OR

ReV
BRK

ERR

Figure x-x

Receiver Buffer Register (RBUF)

Bits

Name

Description

ERR

Error - Set when bit 14 (OR ERR) or
bit 13 (FR ERR) is set. Cleared
when the condition causing the
error is cleared.

OR ERR

Overrun error - Set when a received
byte is loaded into bits 7:0 (RCV
DATA) before bit 7 of the RCSR (RCV
ON) is cleared. This occurs when
a new byte is received before the
reception of the previous byte is
complete. This bit is updated each
time a byte is received.

FR ERR

Framing error - Set when a received
byte is loaded into bits 7:0 (RCV
DATA) without a valid stop bit. FR ERR
is updated each time a byte is received.
Not used (read as zero)

RCV BRK

Receive break - Set when the receiver's
serial input line goes from a mark to a
6-3

KXJ11-CA User's Guide
SERIAL LINE UNITS (SLUs)

PRELIMINARY

4/3/86

space condition and stays in the space
condition for 11 bit times after
reception starts. Cleared when serial
input returns to the mark condition.
Not used (read as zeros)

10:8
7:0

RCV DATA

Receive data - Contains the most recent
byte received. Each time a byte is
received, the RCV ON bit in the RCSR
is set.

6.2.1.3 Transmitter Control/Status Register (XCSR) - The Trans~itter
Control/Status Register (XCSR) is used to monitor and control. the
operation of the SLUl transmitter. Bits <15:7> of this register ar~
read-only. Bits <6:0> are read/write.

ADDRESS: 17777564
07

P8E.
M

XIE

X BRK

Figure x-x Transmitter Control/Status Register (XCSR)
Bits

Name

Description
Not used (read as zeros)

15 :8·
7

X ROY

Transmit ready - When set, the Transmitter
Buffer Register (XBUF) is ready to accept
a byte. Cleared when XBUF is written.

X IE

Transmit interrupt enable - When set,
allows an interrupt request to be made
when bit 7 (X ROY) is set. When cleared,
disables interrupts from/x RDY.

5:3

Programmable baud rate - These bits
determine the transmitter and receiver
baud rate as shown:
PB
6-4

Baud Rate

1XJ11-CA User's Guide

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLOs)

000
001
010
all
100
101
110
111

300
600
1200
2400
4800
9600
19200
38400

Maintenance - When set, external serial
data input to SLUl is disabled and the
transmitter serial output is connected
to the receiver serial input. This allows
self testing of SLUl.

PBE

Programmable baud rate - When set, the
baud rate is determined by PB. When
cleared, the baud rate is determined by
a source external to SLU1.

XBRK

Transmit break - When set, the seria!
output line is torced to a space condition.

6.2..1.4 Transmitter Buffer Register (XBUF) - The Transmitter Buffer
Register (XBUP) holds the most recent byte transmitted. Bits <15:8>
of this register are read-only. Bits <7:0> are read/write.

ADDRESS: 17777566
15

o I 0

Figure x-x
Bits

Transmitter Buffer Register (XBUF)

Name

Description
Not used (read as zeros)

15:81

7:0

XMIT DATA

Transmit data - Contains the next byte
to be transmitted. When the X ROY bit in
the XCSR is clear, XMIT DATA is copied
into a shift register (the serial data
6-5

KXJll-CA User's Guide
SERIAL LINE UNITS (SLUs)

PRELIMINARY

4/3/86

output register) for transmission. XMIT
DATA is loaded with the next byte to
be transmitted, which sets X ROY. When
X ROY is cleared, the operation is repeated

6.2.2
6.3

Examples
MULTIPROTOCOL SERIAL CONTROLLER (SLU2)

SLU2 provides
capabilities:
o

the

KXJll-CA

with

th~

following

features

Two full duplex channels
Channel A provides full modem control
Channel B provides data and timing leads only

Each channel may be operated in one of three modes:
Asynchronous
o

5, 6, 7, or 8 Data bits

1, 1-1/2, or 2 Stop bits

Odd, Even, or No Parity

Break generation and detection

Interrupt on parity, Overun, or Framing Errors
~

Character-oriented synchronous
o

Monosync, Bisync, and External Sync Operations

Software Selectable Sync Characters

Automatic Sync 'Insertion

CRe Generation and Checking

Bit-oriented synchronous
o

HDLe and SDLC Operations

6-6

and

KXJll-CA User's Guide

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

Abort Sequence Generation and Detection

Automatic Zero Insertion and Detection

Address Field Recognition

eRe Generation and Checking

I-Field Residue Handling

Programmable Baud Rates

Double Buffered Transmitted Data

Quadruply Buffered Received Data

Programmable CRe Algorithm

Channel A may utilize the DMA controller to transfer data . .

6.3.1

Synchronous/Asynchronous Serial Line (SLU2) Registers

SLU2 is a synchronous/asynchronous serial device with two independent
channels, A and B. SLU2 is based on the uPD7201 chip. The registers
ass()ciated wi th SLU2 are summarized in Table x-x.
Table x-x SLU2 Registers
Address

Access

Description

17777520

KXJ1l Control/Status Register A

17775736
17775734
17775732
17775730
17775724
17775722
17775720

W
W
W
W

R
R
R

SLU2 Timer Control Register
SLU2 Timer 2 Data Register
SLU2 Timer 1 Data Register
SLU2 Timer 0 Data Register
SLU2 Timer·2 Data Register
SLU2 Timer 1 Data Register
SLU2 Timer 0 Data Register

Channel A
Address

Channel B
Address

Access

Description

17775706
17775704
17775702
17775700

17775716
17775714
17775712
17775710 "

Transmitter
Control Register
Receiver
Status Register

Vi
R
R

KXJ11 Control/Status Register A is contained in the GAS on-board
6-7

gate

KXJll-CA User's Guide
SERIAL LINE UNITS (SLUs)

PRELIMINARY

4/3/86

array.
The timer data and control registers are contained in an
on-board Intel 8254-2 timing controller chip. The other registers are
contained in SLU2 itself, i.e., the uPD7201 chip.

6.3.1.1 KXJll Control/Status Register A (KXJCSRA) - This register
contains control information which affects the overall operation of
SLU2. The register is cleared whenever the KXJll-CA is powered up or
reinitialized.
KXJll Control/Status Register A has the following format:

Figure x-x KXJll Control/Status Register A

ADDRESS: 17777520

CNTIE
RTC ~e

fI\
TERM
SYNC~ B
IN
,...
B
SER .'TT
1oS/i.
.....
, SLU2$
........

6-8

,.,-,'

KXJll-CA User's Guide

Bit.s

Name

Description

15:8
7

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

Not used (read as ones)
,. CN'l'

Programmable counter interrupt enable When set, interrupts from programmable
timer/counter 2 are enabled. When cleared,
these interrupts are inhibited.

RTC IE

Real time clock interrupt enable When set, interrupts from the on-board
real-time clock (RTC) are enabled. When
cleared, these interrupts are disabled.
Not used (read/write)

TERM IN SER

Terminal in service - For use with
modems. When set, Terminal In Service
(IS) is asserted and incoming calls.
can be connected. When cleared, IS
is not asserted.

..~

TTI08/2

Modem connected - For use with modems.
When set, Terminal Ready (TR) is
asserted. When cleared, TR is not
asserted.

SYNCM A

Clock select channel A - When set, SLU2
channel A receives its clock from the
on-board baud rate generator. When
cleared, channel A receives its clock
from an external source.

SLU2BR EN

SYNCM B

~arty

line enable - Used when the
KXJII-CA is configured for party line
operation. When set, SLU2 channel B can
not receive party line data. When cleared,
party line data reception for channel B is
enabled.
Clock select channel B - When set, SLU2
channel B receives its clock from the
on-board baud rate generator. When
cleared, channel B receives its clock
from an external source.

6.3.1.2 Timer Registers - There
are
three
independent
timers
associated with SLU2. These timers, labeled 0, 1, and 2 are contained
in an on-board 8254-2 timing controller chip. Timer 0 and timer 1 run
at 9.8304 MHz and are us:ed to determine the baud rates for SLU2
channels A and a, respectively. Timer 2 is a general purpose SOD-Hz
6-9

KXJll-CA User's Guide
SERIAL LINE UNITS (SLUs)

PRELIMINARY

4/3/86

clock
capable
of
generating interrupts at priority level 6.
Interrupts from the SOO-Hz timer are enabled and disabled via bit 7 of
KXJ11-CA Control Register A (see Section x.x).
Each timer has a Control Registe~ and a Data Register.
To use a
timer, its Control Register 1S loaded first with configuration
information. Then, its Data Register is loaded with the number of
clock "ticks" the timer is to count.
'
The baud rates for channels 0 and 1 can be set by loading a
ratio" into a Data Register. For synchronous transmission,
Divider ratio

"divider

9830.4 K / synchronous baud rate

For asynchronous transmission,
Divider ratio

::11

614.4 K /

asynchronous baud rate

6.3.1.2.1 SLU2 Timer Control Registers - There are three
Timer-Control Registers, one for each timer. They all have the same format
as shown in Figure x-x.

ADDRESS: 17775736
15

I I

I I Sf

: M:

Figure x-x Timer Control Register Format
(Timers 0, 1, and 2)

6-10

01·

I I
BCD

KXJll-CA User's Guide

Bits

Name

15:8

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

Description
Not used (read as ones)

Select counter - Determines which
counter is selected or whether a read
back command is issued.
SC
00
01
10

Selection
Select counter 0
Select counter,l
Select counter 2
Issue read back command

If a read back command is issued, bits

<5:0> of the Timer Control Register are

defined as follows:

5:4

Bit
5

Definition
count - When set, latche~
the contents of the Timer
Counter Data Register(s)
~"
specified by bits <3:1>.
The contents of the
register(s) are interpreted
as a count of clock "ticks".

Status - When set, latches
the contents of the Timer
Counter Data Register(s)
specified by bits <3:1>.
The contents of the
register(s) are interpreted
as status information.

When set, specifies counter 2

When set, specifies counter 1

When set, specifies counter 0

Must be zero

Read/write - Determines which byte of
information is read/written to/from a
Timer Data Register or whether a counter
latch command is issued.
RW
00
01
10
6-11

Selection
Issue counter latch command
Read/write least significant
byte only
Read/write most significant

KXJ11-CA User's Guide
SERIAL LINE UNITS (SLUs)

PRELIMINARY

4/3/86

byte only
Read/write least significant
byte first, then most
significant byte.

If a counter latch command is issued, bits

<3:0> of the Timer Control Register are

"don't care" bits and are not interpreted.

3:1

Mode select - selects the operational
mode of the timer. See the uPD7201 Data
Sheet for descriptions of these modes.

Mode
Interrupt on terminal count
Reserved
Baud rate generator
Square wave
Software triggered strobe
Reserved
•
Reserved
Reserved

000
001
010
011
100
101
110
111

BCD

BCD enable
When set, indicates that the
information in the Timer Data Register is
to be interpreted in binary coded decimal
(BCD) format (four decades). When cleared,
the data is interpreted in l6-bit binary
format.

6.3.1.2.2 SLU2 Timer Data Registers - There are six Timer Data
Registers, two for each timer. Each timer has one register for read
data and another register for write data. They all have the format
shown in Figure x-x except when status data is read. In that case,
the format is as shown in Figure x-x.
ADDRESS: 17775720, 17775722, 17775724, (READ-ONLY)
17775730, 17775732, 17775734, (WRITE-ONLy)
15

I I I I I I , I I' I : : ? : : :
1

Figure x-x Timer Data Register Format
(Read and Write Registers 0, 1, and 2)

6-12

)

KXJ1i-CA User's Guide

Name

Description

15::8
7: ()

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

Not used (read as ones)
o

Counter data - specifies a number of
timer clock ~ticks".

ADDRESS: 17775720,17775722,17775724,
15

OUTPUT
•

.NIII I

Figure x-x Tlmer Data Reglster Format When Used as a
Timer Status Register
Bits

Name

15:8

Description
Not used (read as ones)

OUTPUT

Output - When set, the corresponding
timer output signal is asserted. The
state of this bit is the same as the
state of the timer's pin on the 8254-2
chip.

NULL

Null - When cleared, a new count has
been written and is ready to be read.
When set, the counter contains a "null
count" value which should not be read
unless the user desires the previous
(not updated) count.

5:4

Read/write - Determines which byte of
information is read/written to/from a
Timer Data Register or whether a counter
latch command is issued.
RW
00
01
10
11

Selection
Issue counter latch command
Read/write least significant
byte only
Read/write most significant
byte only
Read/write least significant
byte first, then most
significant byte.

If a counter latch command is issued, bits
6-13

KXJll-CA User's Guide
SERIAL LINE UNITS (SLUs)

PRELIMINARY

4/3/86

<3:0> of the Timer Control Register are
ftdon't careft bits and are not interpretedo
3:1

Mode select - selects the operational
mode of the timer.

Mode

000
001
010
all
100
101
110
111

Interrupt on terminal count
Reserved
Baud rate generator
Square wave
Software triggered strobe
Reserved
Reserved
Reserved

BCD enable - When set, indicates that the
information in the Timer Data Register i~
to be interpreted in binary coded decimal
(BCD) format (four decades). When cl~red,
the data is interpreted in 16-bit binary
format.
~"

BCD

6.3.1.3 SLU2 Control Rf!9isters - Each channel has a set of eight
write-only Control Registers numbered 0 through 7. Control Register 0
can be written directly. Control Registers 1 through 7 are accessed
by first writing Control Register 0 bits <2:0> and then writing the
desired Control Register. This section describes each of the Control
Registers.

6.3.1.3.1

Control Register 0 -

ADDRESS: 17775704, 17775714
'5

Figure x-x Control Register 0

6-14

KXJll-CA User's Guide

Bits

Name

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

Description

15:8

Not used (read as ones)

7:6

CRe control - The following commands
control the operation of the cyclic
redundancy check (CRC) circuitry:

5:3

CMD

CRC
00

Mode
Null - No effect. Used when
setting other fields in Control
Register a such as the register
pointer field.

Reset receiver CRC checker In synchronous mode, resets the
CRe checker to zeros. In SDLC
mode, resets the eRC checker to
ones.

Reset transmitter CRe generator
- In synchronous mode, resets
the CRC generator to zeros. In
SDLe mode, resets the eRC
generator to ones.

Reset idle/CRC latch - Clears
the idle/CRe latch. When a
transmitter underrun occurs,
the transmitter enters the eRC
phase of operation and begins to
send the CRC character calculated
up to that point. Then the latch
is set. If the underrun condition
persists, idle characters are sent
after the eRC character. This
latch is set when the channel is
initialized.

Commands - The following SLU2 commands are
specified by this field:

6-15

CMD
000

Command
Null - No effect. Used when
setting other fields in Control
Register 0 such as the register
pointer and the CRe command
field.

001

Send abort - Used in SDLC mode.
Causes an SDLC abort code to be
transmitted.

KXJll-CA user's Guide
SERIAL LINE UNITS (SLUs)

2:0

PRELIMINARY

4/3/86

010

Reset external/status interrup~~
- Clears any pending external
interrupts and allows new
interrupts to be detected.

all

Channel reset - Disables the
channel's receivers and
transmitters (transmitter
outputs are set high) and sets
modem control outputs high.
Disables interrupts and clears
all DMA and interrupt requests.
All Control Registers must be
rewritten after a channel reset
command. One NOP instruction
must be executed before a new
command can be written.

100

,Enable interrupt on next
character - Used when operating
in Interrupt on First Character
mode. Reenables the interrup~~
logic for the next received
.
character.

101

Reset pending transmitter
interrupt/DNA request - Clears
a pending Transmitter Buffer
Becoming Empty interrupt or DMA
request without sending another
character.

110

Error reset - Clears a Special
Receive Condition interrupt.
Clears parity and overrun errors.

III

End of interrupt (Channel A
only) - Typically included as
part of an interrupt service
routine. Reenables lower priority
devices in the interrupt daisy
chain for servicing of any pendin
interrupts.

Register pointer - Specifies which Control
Register will be written or which Status
Register will be read next. When the
KXJll-CA is reset or initialized, this
field is set to 000 which allows the
writing of Control Register a or the Reading
of Status Register O. Following a read or
write to a Control Register other than 0,
this field is set to 000.
6-16

KXJll-CA User's Guide

6.3.1.3.2

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

Control Register 1 -

ADDRESS: 17775704,17775714, RP = 001, WRITE ONLY
11

Figure x-x Control Register 1

03· 02

SAV

EXT IE

XMITIE

6-17

KXJll-CA User's Guide
SERIAL LINE UNITS (SLUs)
Bits

PRELIMINARY

Name

4/3/86

Description

15:8

Not used (read as ones)

7:5

Must be zero

4:3

RIM

Receiver interrupt mode - Determines how
a channel handles received characters.
RIM
00

Interrupt Mode
Receiver interrupts/DMA request
disabled - Disables interru~ or
DMA requests from this channe1 if,
a character is received (polled
mode) •

Interrupt on first character
only - Causes an interrupt to_be
issued for the first character
received after an enable
•
interrupt on first character
command has been given (see . ."
description of Control Register
0). If the channel is in DMA
mode, a DMA request is issued
for each character received
including the first.

Interrupt on all received
characters - Causes an interrupt
to be issued whenever a character
is present in the channel's
receive buffer. A DMA request is
issued if the channel is in DMA
mode. A parity error is
considered a Special Receive
Condition.

Interrupt on all received
characters - This is similar to
10, described previously. The
difference is that is parity
error is not considered to be a
Special Receive Condition.

SAV

Status affects vector - Must be 1 for
channel S, must be a for channel A. This
setting insures that the vector loaded into
Status Register 2, channel B is modified to
indicate the cause of the interrupt.

XMIT IE

Transmit interrupt enable - When set, this
channel will issue an "interrupt when the
transmitter buffer becomes empty or when
6-18

KXJll-CA User's Guide

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

the transmitter enters an Idle phase and
begins transmitting sync or flag characters.

External status interrupt enable - When set,
this channel will issue an interrupt when
any of the following occur: transition of
a Carrier Detect (CO) input, transition of
a Clear to Send (CTS) input, transition of
sync input, entering or leaving synchronous
Hunt Phase break detection or termination,
SDLC abort detection or termination,
Idle/CRe latch becoming set.

EXT IE

6.3.1.3.3

Control Register 2 - Channel A -

ADDRESS: 17775704, RP = 010, WRITE-ONLY
15

I I I

06
0

I 0 I ' I 0 IPRII 0

Figure x-x Control Register 2 - Channel A

6-19

I
I

DMA·
MODE

KXJll-CA user's Guide
SERIAL LINE UNITS (SLUs)

PRELIMINARY

Name

Bits

4/3/86

Description

15:8

Not used (read as ones)

7:3

Must be 00010

,. PRI

Priority - If both channels A and B are in
interrupt mode the interrupt priority is:
RxA > TxA > RxB > TxS > extA > extB
if PRI is cleared and
RxA > RxB > TxA > TxS > extA > extB_
if PRI is set.
If channel A is in DMA mode and channel

B is in interrupt mode, the interrupt

priority is:

RxA > RxB > TxB > extA > extB

•

Must be zero

DMA MODE

DMA mode - If set, channel A operates in
DMA mode and channel B does not. If

cleared, neither channel A nor B operates
in DMA mode.

6.3.1.3.4 Control Register 2 - Channel B - Control Register 2 for
channel B holds the SLU2 interrupt vector. Although the register is
programmed via channel a, the same vector is used for interrupts on
both channel A and B. Initially, the KXJIl-CA firmware loads this
vector wi th an octal value of 70. If bi t 2 in Control Rig ister 1 is
set, the contents of this register will be modified according to thetype of interrupt that occurs. The modified vector is obtained from
StatUS Register 2 (see section x.x).
ADDRESS: 17775714, RP = 010, WRITE.ONLY
15

I I

Figure x-x Control Register 2 - Channel S

6-20

KXJ11-CA User's Guide

6.3.1.3.5

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

Control Register 3 ADDRESS: 17775704,17775714, RP = 01 1, WRITE-ONLY

Figure x-x Control Register 3

AUTO

Rev

SYNC

ENB

CRC

HUNT

LOAD •

ADOA
SRCH

6-21

RCVIE

KXJ11-CA User's Guide
SERIAL LINE UNITS (SLUs)
Bits

PRELIMINARY

Name

15:8
7:6

4/3/86

Description
Not used (read as ones)

BPe

Bi t·s per character - Spec i f i es the number
of data bits per received character.
BPe

00·
01
10
11

Bits Per Character
5
6
7

AUTO ENB

Auto enable - When set, causes Carrier
Detect (CD) to act as an enable for the
receiver and Clear to Send (CTS) to act
as the enable for the transmitter.

HUNT

Hunt - When set, causes the receiver to
enter a hunt phase. This is typically, done
to restore synchronlzatlon. Wh,n the
receiver is enabled, a hunt begins and a~
transfer can occur only when character
synchronization has been achieved. The hunt
phase is also automatically entered wheneve
a channel is reset.

RCV eRe

Receiver CRC enable - When set, enables
CRC calculation. When cleared, disables (bu
does not reset) the receiver CRC generator.

ADDR SRCH

Address search mode - This bit must be zero
in non-SDLC modes. If this bit is set in
SDLC mode, character assembly does not begin
until the a-bit ~haracter (secondary addres:
field) following the starting flag of a
message matches either the address
programmed into Control Register 6 or the
global address 11111111 (binary).

SYNC LOAD

Sync character load inhibit - When set,
prevents the loading of sync characters
into the receive buffer. Meaningful only
in synchronous mode. When using CRC,
this bit should be used to strip only the
leading sync characters preceding a message
and not the embedded sync characters.
Protocols using other types of block
checking, however, may use this bit to stri~
the embedded sync characters.

RCV IE

Receiver enable - When set, enables this
channel's receiver. When cleared, disables
the receiver.

6-22

KXJl1-CA User's Guide

603.1.3.6

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

Control Register 4 -

ADDRESS: 1 7775704, 1 7775714, RP = , 00, WRITE-ONLY
08

Figure x-x Control Register 4

PAR
PAR
ENS

6-23

KXJ11-CA user's Guide
SERIAL LINE UNITS (SLUs)
Bits

PRELIMINARY

Name

Description
Not used (read as ones)

15:8

7:6

4/3/86

CLK

Clock rate - Specify the relationship
between the transmitter and receiver
clock inputs and the actual data rate~
When operating in synchronous mode,
eLK must be 00.
CLK
00
01
10
11

5:4

Sync Mode - Selects which synchronous
protocol to use if this channel has been
programmed in a synchronous mode.
M
00
01
10
11

3:2

Clock Rate
1 x data rate
16 x data rate
32 x data rate
64 x data rate

Protocol
Monosynch
Bisynch
SDLC
External Synch

Stop bits/synchronous mode - Specifies
whether the channel is to be used in
synchronous or asynchronous mode. In
asynchronous mode, this field also
specifies the number of stop bits used
by the transmitter. The receiver always
uses one stop bit.

sa
00
01
10
11

Mode
Synchronous mode
Asynchronous mode, 1 stop bit
Asynchronous mode, 1.5 stop bits
Asynchronous mode, 2 stop bits

PAR

Parity sense - When set, causes even
parity generation and checking. When
cleared, causes odd parity generation
and checking.

PAR END

Parity enable - When set, causes an extra
bit containing parity information to be
concatenated with each transmitted
character. Also causes parity checking
to be perfor.med for each received
character.

6-24

KXJll-CA User's Guide
6.3.1.3.7

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

Control Register 5 ADDRESS: 17775704, 17775714, RP := 101, WRITE-ONLY

Bits

XMIT

RTS

SRK

Not used (read as ones)

Must be zero

BPe

ENS

Figure x-x Control Register 5
Name
Description

15:8

6:5

CRC
SEL

XMIT
CRe

Transmitted bits per character - Specifies
the number of data bits per transmitted
character.

BPe
00
01
10
11

Bits/Character
5 or less

6
8

Note that for five or less bits/character,
the data must be formatted as follows:
Bits/Character
1

2
3
4
5

-Format
1111000d
111000dd
11000ddd
lOOOdddd
OOOddddd

Where d represents a data bit. The most
significant data bit is always in the
leftmost position.
4

BRK

Send break - When set, forces this channel's
transmitter data output low (spacing).

XMIT ENB

Transmitter enable - When this channel is
reset, this bit is cleared. The transmitter
data output is forced high (marking) and the
transmitter is disabled until this bit is se

eRe SEL

eRe polynomial select - When set, th-e
is selected (X**16 + X**lS
+ X**2 + 1). When cleared, the CRC-CCITT
polynomial is selected (X**16 + X**12 + X**5
CRe-l~ polynomial

6-25

KXJll-CA User's Guide
SERIAL LINE UNITS (SLUs)

PRELIMINARY

4/3/86

+ 1). The CRC-CCITT polynomial must be
selected when in SDLC mode.

RTS

Request to Send - When set, asserts RTS.
When cleared, deasserts RTS. In synchronous
and SDLC modes, RTS is asserted immediatel~
In asynchronous mode, RTS is asserted only
when the transmitter data buffer is
completely empty.

XMIT CRC

Transmitter CRe enable - When set, enables
this channel's transmitter CRC generator.
When cleared, the CRe calculation is not
performed. Setting and clearing this
bit includes or excludes individual
characters from a eRC calculation. If this
bit is cleared when a transmitter underrun
occurs, the CRC will not be sent.
.

6.3.1.3.8 Control Register 6 - Control Register 6 holds sync
which has different meanings in different modes:
~

byte

Monosync - The 8-bit sync character transmitted
phase.

Bisync - The least significant 8 bits of the l6-bit
receive sync character.

SDLC - A secondary address value which is matched to the Secondary
Address field of the SDLC frame when in Address Search mode.

External Sync - The sync character
phase.

transmitted

during 'the

Idle

transmit

during

and

the

Idle

ADDRESS: 1 7775704" 17775714, RP = 110. WRITE-ONLY
15

Figure x-x Control Register 6

6.3.1.3.9 Control Register' - Control Register' holds sync
which has different meanings in different modes:
6-26

byte

KXJll-CA User's Guide

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

Monosync - The a-bit sync character matched by the receiver.

Bisync - The most significant a bits of the
receive sync character.

SDLe - Mus~ contain the flag character (01111110) matched
receiver.
.

External Sync - Control Register 7 is not used
mode.

1S-bit

transmit

and

the

external

sync

ADDRESS: 17775704,17775714, RP = 11 1, WRITE .. ONLY
15

Figure x-x Control Register 7

6.3.1.4 SLU2 Status Registers - Channel A has two read-only Status
Registers numbered 0 and 1.
Channel B has three read-only Status
Registers numbered 0 through 2. A Status Register is read by first
writing Control Register 0 with an appropriate register pointer.
Then, a read to address 17775700 (for channel A) or 17775710 (for
channel B) produces the status data. This section describes each of
the Status Registers.

6.3.1.4.1

Status Register 0 ADDRESS: 17775700,17775710

Figure x-x Status Register
IDLE

6-27

xeE

RCA

KXJll-CA User's Guide
SERIAL LINE UNITS (SLUs)

Bits

Name

PRELIMINARY

4/3/86

Description
Not used (read as ones)

15:8
7

SR/AB

Break/Abort - When set in asynchronous
receive mode, indicates that a break
sequence has been detected. A break
occurs when the data input is held low
(spacing) for more than one character
~ time. Cleared when the input returns high
(marking). An External/Status interrupt
if enabled occurs when the state of this
bit changes. When set in SOLe mode,
indicates that an abort sequence (seven
or more l's) has been detected.

IDLE

Idle - Indicates the state of the Idle/CRe
latch used in synchronous and SOLe modes.
This bit is set during a reset operat~on.
Cleared by a Reset Transmit Underrun/EOM
Latch command.

Clear to send - This bit reflects the
state of the CTS input for this channel.
When set, eTS is asserted. Any transition
of this bit causes an External/Status
interrupt request.

Sync status - Meaning depends upon the
operating mode of this channel.
Asynchronous: Reflects the state of the
SYNC input. When set, SYNC is asserted.
Any transition of this bit causes an
External/Status interrupt request.
External sync mode: Similar to
asynchronous mode. A low-to-high
transition of this bit indicates that
synchronization has been achieved and
character assembly has begun.
Monosync, Bisync, SDLC modes: When set,
indicates that the receiver is in the
Sync Hunt phase of operation. When
cleared, indicates that the receiver is
in the Receive Data phase.

DCD

Data carrier detect - Reflects the state
of the DCD input. When set, DCD is
asserted. Any transition of this bit
causes an External/Status interrupt
request.
6-28

KXJll-CA User's Guide

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

XBB

Transmitter buffer empty - When set,
indicates that the transmitter buffer is
empty, except during transmission of CRC
characters in synchronous mode. When
cleared, indicates the transmitter buffer
is loaded. This bit is set during a reset
operation.

Interrupt pending (Channel A only) Used in conjunction with the interrupt
vector register (Status Register 2,
channel B) to determine the status of
an SLU2 interrupt. In Non-vectored
Interrupt mode, this bit is set when
Status Register 2, channel S is read.
The low three bits of this Status
Register indicate the cause of the
interrupt. In Vectored Interrupt mode,
the Interrupt pending bit is set when
SLU2 is the highest priority device
requesting interrupt service. In either
mode, the bit is cleared when an End of~~
Interrupt command is issued and there
are no other pending interrupt requests.
This bit is zero for channel S.

RCA

Received character enable - When set,
indicates that one or more characters are
available in the receiver buffer. Once
all the available characters have been
read, this bit is cleared until a new
character has been received.

6.3~l.4.2

Status Register 1 AODRESS: 17775700,17775710, RP - 001, REAO-oNLY
00

Figure x-x Status Register 1

EOF
FE

6-29

KXJ11-CA User's Guide
SERIAL LINE UNITS (SLUs)

Bits

Name

15:8

PRELIMINARY

4/3/86

Description
Not used (read as ones)
End of frame - This bit is valid only
in SOLC mode. When set, indicates that
a valid ending flag has been received
and that the CRC error flag and residue
code is valid. Cleared by an Error Reset
command or upon reception of the first
character of the next frame.

" e:OP

Framing error - When set in asynchronous
mode, indicates that no stop bit has been
detected at the end of a received
character. When set in synchronous modes,
indicates that the calculated CRC value.
does not match the last two bytes received.
This bit is cleared by issuing an Err.r
Reset command.

Overrun error - When set, indicates that
the receiver buffer has been overloaded.
The receiver buffer (FIFO) can contain
three characters. If a fourth character
is received, the last character in the
buffer is overwritten. This error bit
remains latched until an Error Reset
command is issued.

Parity error - When set, indicates that
parity checking has been enabled and that
the parity of a received character does
match the programmed sense (even/odd).
This bit remains set until an Error Reset
command is issued.

3:1

SOLe residue code - These bits are valid
only in SDLC mode. The data portion of
an SDLe message may consist of a
non-integral number of characters. Since
transfers are character oriented, the
residue code provides the capability to
receive any leftover bits. See the uPD7201
Data Sheet for a table of residue codes
corresponding to characters of various
lengths.

All sent - When set in asynchronous mode,
indicates that the transmitter buffer is
empty. When cleared in asynchronous mode.,
indicates that a character is present in
the transmitter buffer or shift register.
6-30

KXJll-CA User's Guide

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

In synchronous modes, this bit is always
set.

6~3.1.4.3

Status Register 2 (Channel B Only) -

ADDRESS: 17775710, RP - 010, REAO-oNlY

Figure x-x Status Register 2 (Channel B Only)
Bits

Name

Description
Not used (read as ones)

15::8
7: 21

VEe

Interrupt vector - Contains bits <7:3>
of the vector contained in Control Register
2, channel B (see Section x.x).

2:0

Status modifiers - These three bits
indicate the following:
S
III

000
001
010

all
100
101
110
111

Description
No Interrupt Pending
Channel S Transmitter Suffer Empty
Channel S External/Status Change
Channel B Received Character Availabl
Channel B Special Receive Condition
Channel A Transmitter Buffer Empty
Channel A External/Status Change
Channel A Received Character Availabl
Channel A Special Receive Condition

111 has two meanings. They may be
distinguished by examining bit 1 of Status
Register -0, channel A (Interrupt Pending).

6.3.1.5 SLU2 Transmitter Registers - There are two Transmitter Data
Registers, one for each channel. The format of these registers is
shown in Figure x-x.

6-31

KXJll-CA User's Guide
SERIAL LINE UNITS (SLUs)

PRELIMINARY

4/3/86

ADDRESS: 17775706. 17175116
15

,00

Figure x-x Transmitter Registers A and B

SLU2 Receiver Registers - There are two Receiver Regtsters
(data registers), one for each channel. The format of these reglsters
is shown in Figure x-x.

6.3.1.6

ADDRESS: 17775102. 17175112
,5

11 : 1 ~ 1 : 1 : -,: 1 : -,; -1

which

I : : R~CEIVf DA1A: : I

Figure x-x Receiver Registers A and B

6.3.2

Examples

The following programs provide
application programs •
• TITLE

Iskeletons'

base

user

SLU1.MAC

; This program utilizes the uPD720l to transfer serial data. The
; data will be transfered out of Channel A and received by Channel
& so a loopback connector is required (Part #H3022 or 54-16229-01).
1bis example transfers the data in asynchronous mode using
,• iDterrupts.

·,; jfter this program has been assembled and linked on the
:
;

evelopment machine use the KUI utility of the KXJ11-CA Software
~lkit to load the program into the KXJll-CA to execute as
,• .own in this example:

·,,• SB'l' 2
;

UlAD SLU1.SAV

: JlECUTE

·,,· !!ODT

6-32

KXJll-CA User's Guide

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

1001206
· 1001302/041101
1001304/042103
· 1001306/043105
!001310/044107

,
,•
,•
,

1001312/041101
t 001314/04(2103
, !001316/043105
,• !001320/044107
,• _! 001322/000000
!R4/000000
!CTRL/C
EXIT

··

· This verifies that the data was successfully transfered. 1302 is

,·

the address of the transmit buffer and 1312 is the address of the
receive buffer. R4 a O verifies that no external or special
condition interrupts were received.

,· Register Definitions
175700
175702
RBUPA ••
CNTRLA ::I=- 175704
TBUPA ==- 175706
STA'l'A

STA,-s
CN'fttLB

::a=-

a.
a_

175710
175714

TIMREG ==- 175736
TI~O a=- 175730

, Channel A status register
·, Channel A receiver

Channel A Control register
Channel A transmitter

,• Channel B status register

, Channel B control register

,· Timer control register
,• Timer 0 data register

START: :
This section initializes the KXJII-CA system environment
MTPS

#340

MOV
MOV

#ISR,@#70
#340,@#72

CLa

MOY
MOV

#TBUF,R2
#RBUF,R3

CLK

·
SLU2 interrupts at location 70
,· Let the ISR run at priority 7
,· This is the transmit char counter
, R2 points to the transmit buffer
,·· R3 points to the receive buffer
,· This counter keeps track of external
changes and special receive
··,, status
receive
, Disable recognition of interrupts

co~ditions

~~his

sect ion in i t i a1 izes the bi t rate generator
MOV.

#26,TIMREG

: Select timer 0, low byte only,
6-33

KXJll-CA User's Guide
SERIAL LINE UNITS (SLUs)

PRELIMINARY

4/3/86

mode 3, binary
·; This
divider selects 9600 bps

,
MOVB

#64.,TIMERO

This section initializes the 7201 for asynch operation
MOVB
NOP

'. #,30, CNTRLA

; Reset Channel A
Wait for reset to complete

MOVB
NOP

#30,CNTRLB

; Reset Channel B
; Wait for reset to complete

. "MOVB
MOVB

#2,CNTRLA
#24,CNTRLA

Point to CR2A
Setup bus interface options:
; No DMA, RxA>RxB>TxA ••• , Non-Vectored

MOVB
MOVB

#4,CNTRLA
#104,CNTRLA

; Point to CR4
; Set operation mode:
; No parity, asynch mode, 1 stop bit,
, clock rate a 16x data rate

MAIN: :

ISR: :

MOVB
MOVB

#3,CNTRLA
#301,CNTRLA

Point to CR3
Enable receiver, char length a 8

MOVB
MOVB

#S,CNTRLA
#lS2,CNTRLA

; Point to CRS
; Enable transmitter, Char length a 8

CLRS
MOVB

CNTRLA
#20,CNTRLA

Point to CRO
Reset External/Status Interrupts

MOVB
MOVB

#l,CNTRLA
#36,CNTRLA

Point to CRl
Transmit IE, Interrupt on all
received chars, enable condition
; affects vector

MTPS
MOVB
BR

#0
(R2)+,TBUFA

, Enable recognition of interrupts
,· Send first character --

MOVB
MOVB

#2,CNTRLB
STATS,-{SP)

,· Store the condition affects vector

;

·
,· Stay here while the interrupts occur
Point to SR2B

on the stack

This section inspects the condition affects vector to
determine the cause of the interrupt

ROR
BCS

(SP)
EXT

ROR
BCS

(Sp)
RCV

Rotate bit 0 into the carry bit
If this bit was set then the
interrupt was caused by a special
receive condition or an external/
, status change
; Rotate bit 1, into the carry bit
; If this bit was set then the

6-34

KXJll-CA User's Guide

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

,• interrupt was caused by a received
,· character

,• If neither of the above conditions was
,· satisfied then the interrupt must have
, been caused by the transmitter buffer
goihg'empty
·,.,
XMIT: :
, Increment the xmit char counter
INC
RO
,·· IF this is the eight char
CMP
RO,IS.

1$:
RCV: :

EXT:: :

SEQ
MOVB
SR
MOVB
SR

MOVB
SR

RBUFA, (R3) +

(R2)+,TBUFA

tOONE

#50 ,CNTRLA
I DONE
tOONE

branch to IS
· THEN
ELSE send another char

,
;

, and return
,• reset pending xmit interrupt
,· request - then return
Store this character

,· and return

,. External/Status interrupt or Special Receive Condition

;

This program does not take any special action if an

;

occurs. Just note that it occurred (there shouldn't be
any) and continue.

;

INC

;

Increment the counter
and return

IDONE:: TST
MOVS
RTI

(SP)+
#70,CNTRLA

TBUF::
RBUF::

. BYTE
.SLKB

101,102,103,104,105,106,107,110
8.

.END

START

Fix the stack
; Issue end of interrupt command
,• and return to main program

6-35

KXJ11-CA User's Guide
SERIAL LINE UNITS (SLUs)

.TITLE
:
:
;
;

PRELIMINARY

4/3/86

SLU2.MAC

This example program for the uPD7201 transfers serial dat~ via
a loopback connector (part #H3022 or 54-16229) between Channel
A's transm·i t, and receive using the DMA controller. No ISR is
included in this example as it is meant to show how the uPD7201
and the DTC may work together. A 'real-life' program should
include an ISR which monitors any External or Special Receive
condition interrupts. For more information regarding the
programming of the DTC please refer to Section x.x.

;. After this program has been assembled and linked on the
development machine use the KUI utility of the KXJ11-CA Software
Toolkit to load the program into the KXJ11-CA to execute as
shown in this example:
SET 2
LOAD SLU2.SAV
EXECUTE

lOOT

;

1001234
!1276/041101
!001300/042103
1001302/043105
!001304/044107
!001306/041101
1001310/042103
!001312/043105
!001314/044107
1001316/000000
!CTRL/C
EXIT
This verifies that the data was tranfered successfully. The
transmit buffer begins at address 1276 and the receive buffer
begins at address 1306.
Register Assignments

:a.:a. 174470
174454
CASTFO =:a 174446
:a. 174444
174442
CAOFO
CASTF1

MMREG
CMDREG

CAOFl

=-=
==

174440

STATA =-= 175700
RBUFA == 175702
CNTRLA :sa 175704
TBUFA =-= 175706
STATB •• 175710
CNTRLB •• 175714

Master Mode Register
Command Register
Chan 0 Chain Address Seg/Tag Field
, Chan 0 Chain Address Offset Field
Chan 1 Chain Address Seg/Tag Field
, Chan 1 Chain Address Offset Field

·
·

Channel A status register
Channel A receiver
Channel A Control register
Channel A transmitter
Channel B status register
, Channel B control register

6-36

KXJll-CA User's Guide

TIMREG •• 175736
TlMERO •• 175730

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

: Timer Control register
: Timer 0 Data register

START: :

This section initializes the KXJl1-CA system environment
M'l'PS

#340

MOV
MOV

#TBUF,R2
#RBUF,R3

: Disable recognition of interrupts
R2 points to the transmit buffer
R3 points to the receive buffer

This' section initializes the bit rate generator
MOVB

#26', TIMREG

Mova

#64. ,TlMERO

; Select timer 0, low byte only,
, mode 3, binary
; This divider selects 9600 bps

This section initializes the 7201 for asynch operation

Mova

#30,CNTRLA

: Reset Channel A
; Wait for reset to complete

Mova

#30,CNTRLB

; Reset Channel B
; Wait for reset to complete

Mova
Mova

#2,CNTRLA
#25,CNTRLA

; Point to CR2A
; Setup bus interface options:'
; Chan A DMA, RxA>RxB>TxA •.• ,
; Non-Vectored

MOVB

#4,CNTRLA
#104,CNTRLA

; Point to CR4
; Set operation mode:
; No parity, asynch mode, 1 stop bit,
, clock rate = 16x data rate

NOP
Nap

Mova

Mova
Mova
Mova
Mova

#3,CNTRLA
#301,CNTRLA

CLRB

CNTRLA

Mova
Mova
MOVB

#5,CNTRLA

#152,CNTRLA
#20,CNTRLA .

Point to CR3
; Enable receiver, char length = 8

,·

; Point to CRS
; Enable transmitter, Char length = 8

·; Point to eRO

,•

#1,CNTRLA

#16,CNTRLA

Reset External/Status Interrupts

Point to CRl
Transmit IE, Interrupt on 1st
received char and issue DMA request
enable· condition affects vector

This section initializes the DMA controller
CLRB

Reset the DTe

CMDREG

6-37

KXJ11-CA User's Guide
SERIAL LINE UNITS (SLUs)

PRELIMINARY

MOV
MOV
MOV
MOV

'O,CASTFO
,LOADO ,CAOFO
#O,CAST!'l
,LOAD1 ,CAO!'l

MOVB

' #11S,MMREG

MOVB
MOVB

#240,CMDREG
#241,CMDREG

4/3/86

, Load Chain Address Register Seg/Tag
,·· Load Chain Address Register Offset
Load Chain Address Register Seg/Tag
,• Load Chain Address Register Offset
·, Load Master Mode Reg to Enable DTC
;

MAIN: :

Start Chain Channel a
Start Chain Channel 1

,· Stay here while the DMA transfers
, occur

; Chain Load Region
LOAD1:

• WORD

001602

•WORD
•WORD

000000
TBUF

Current Address Register A Seg/Tag
Current Address Register A Offset
; <This local address is the source>

•WORD
•WORD

000020
TBUFA+1

Current Address Register B Seg/Tag
Current Address Register B Offset
<This local address is the destination>

•WORD

000010

Current Operation Count <Transfer 8 bytes>

• WORD
• WORD

000020
000001

; Channel Mode Register High
; Channel Mode Register Low
<No match conc;iitions, do nothing upon
, completion, transfer type = single transfer
, CARA = source, byte transfers>

Reload Word <Select CARA,CARB,COPC,CM>

··

LOADO:

Reload Word <Select CARA,CARB,COPC,CM>

.WORD

001602

. WORD
. WORD

000020 ; Current Address Register A Seg/Tag
RBUFA+1 ; Current Address Register A Offset
<This local address is the source>

•WORD
•WORD

000000
RBUF

Current Address Register B Seg/Tag
Current Address Register B Offset
~This local address is the destination>

•WORD

000010

· Current Operation Count <Transfer 8 bytes>

• WORD

000000
000001

, Channel Mode Register Low

•WORD

·
I

TBUF: :

• BYTE

Channel Mode Register High
<No match conditions, do nothing upon
completion, transfer type • single transfer
CARA = source, byt~_ .transfers>

101,102,103,104,105,106,107,110
6-38

KXJll-CA User's Guide

RBUF ': :

• BLKB

.END

START

6-39

PRELIMINARY
4/3/86
SERIAL LINE UNITS (SLUs)

APPENDIX A
MEMORY MAP SUMMARY

A.1

Table x-x lists all the registers in the
addresses associated with these registers.

KXJI1-CA

and

specifies

Table x-x KXJ11-CA Registers
KXJ11-CA Address

17772200 17772220 17772240 ;772260 -

Supervisor I Space PORe - POR7
Supervisor 0 Space PORe - POR7
Supervisor I Space PARe - PAR7
Supervisor 0 Space PARe - PAR7
Kernel I Space PORe - POR7
Kernel D Space PDRe - POR7
Kernel I Space PARO - PAR7
Kernel D Space PARe - PAR7

_/772300 -

17772320 17772340 17772360 -

17772216
17772236
17772256
17772276
17772316
17772336
17772356
17772376

17772516

Memory Management Register a (MMR3)

17774400
17774402
17774404
17774406
17774410
17774412
17774414
17774416
17774420
17774422
17774424
17774426
17774430
17774432
17774434
17774436
17774440
17774442
17774444
774446

DTC CHI Current B Address Offset
DTC CHa Current B Address Offset
DTC CHI Sase B Address Offset
DTC CHa Sase B Address Offset
DTC CHI Current A Address Offset
DTC CHa Current A Address Offset
DTC CHI Base A Address Offset
DTC CHD Sase A Address Offset
DTC CHI Current B Address Segment/Tag
DTC CHD Current B Address Segment/Tag
DTC CHr Base a Address Segment/Tag
DTC CHD Base a'Address Segment/Tag
DTC CHl Current A Address Segment/Tag
DTC CHD Current A Address Segment/Tag
DTC CHI Biase A Address Segment/Tag
DTC CHa B:ase A Address Segment/Tag
DTC CHI Chain Address Offset
DTC CHO Chain Address Offset
DTC CHI Cnain Address Segment/Tag
DTC CHO Chain Address Segment/Tag
A-1

the

KXJ11-CA User's Guide
Memory Map Summary

PRELIMINARY

4/3/86

17774450
1.7774452
1.7774454
17774456
177'74460
17774462
17774464
17774466
17774472 - 1774506
17774510
17774512
1.7774514
17774516
17774520
17774522
17774524
17774526
17774530
17774532
17774534 - 17774536

DTC CHI Interrupt Save Register
DTC CHO Interrupt Save Register
orc CHI Status Register
DTC CHO Status Register
DTC CHI Current Operation Count
DTC CHO Current Operation Count
DTC CH1 Base Operation Count
DTC CHa Base Operation Count
DTC Reserved
DTC CHI Pattern Register
DTC CHa Pattern Register
DTC CHI Mask Register
DTC CHa Mask Register
DTC CHI Channel Mode Low
DTC CHa Channel Mode Low
DTC CHI Channel Mode High
DTC CHa Channel Mode High
DTC CHI Interrupt Vector
DTC CHa Interrupt Vector
DTC Reserved

17775000
17775002
17775004
17775006
17775010
17775012
17775014
17775016
17775020
17775022
1.7775024
17775026
17775030
17775032
17775034
17775036

TPRO
TPRI
TPR2
TPR3
TPR4
TPRS
TPR6
TPR7
TPR8
TPR9
TPRIO
TPR11
TPR12
TPR13
TPR14
TPR15

17775700
17775702
17775704
17775706
17775710
17775712
17775714
17775716
17775720
17775722
17775724
17775730
17775732
17775734
17775736

SLU2 Channel A Status Register
SLU2 Channel A Receiver
SLU2 Channel A Control Register
SLU2 Channel A Transmitter
SLU2 Channel B Status Register
SLU2 Channel B Receiver
SLU2 Channel B'Control Register
SLU2 Channel B Transmitter
SLU2 Timer 0 Data Register
SLU2 Timer 1 Data Register
SLU2 Timer 2 Data Register
SLU2 Timer 0 Data Register
SLU2 Timer 1 Data Register
SLU2 Timer 2 Data Register
SLU2 Timer Control Register
A-2

KXJ11-CA User's Guide

1777701E; . .
17777020
17777022
17777024
17777026
17777030
17777032
17777034
17777036
17777040
17777042
17777044
17777046
17777050
17777052
17777054
17777056
17777060
'7777062
'777064
.17777066
17777070
17777072
17777074
17777076
17777100
17777102
17777104
17777106
17777110
17777112
17777114
17777116
17777120
17777122
17777124
.17777126
1777 7130
17777132
17777134
17777136
17777140

PIO Master Interrupt Control Register
PIO Master Configuration Control Register
PIO Port A Interrupt Vector Register
PIO Port B Interrupt Vector Register
PIO Counter/Timer Interrupt Vector Register
PIO Port C Data Path Polarity Register
PIO Port C Data Direction Register
PIO Port C Special I/O Control Register
PIa Port A Command and Status Register
PIO Port 8 Command and Status Register
PIO Counter/Timer 1 Command and Status Register
PIa Counter/Timer 2 Command and Status Register
PIa Counter/Timer 3 Command and Status Register
PIO Port A Data Register
PIO Port 8 Data Register
PIa Port C Data Register
PIa Counter/Timer 1 Current Count (MSa)
PIa Counter/Timer 1 Current Count (LSa)
PIa Counter/Timer 2 Current Count (MSa)
PIO Counter/Timer 2 Current Count (LSa)
PIO Counter/Timer 3 Current Count (MSa)
PIO Counter/Timer 3 Current Count (LSB)
PIO Counter/Timer 1 Time Constant (MSa)
PIa Counter/Timer 1 Time Constant (LSa)
PIO Counter/Timer 2 Time Constant (MSa)
PIO Counter/Timer 2 Time Constant (LSB)
PIO Counter/Timer 3 Time Constant (MSS)
PIO Counter/Timer 3 Time Constant (LSS)
PIO Counter/Timer 1 Mode Specification
PIO Counter/Timer 2 Mode Specification
PIO Counter/Timer 3 Mode Specification
PIO Current Vector Register
PIO Port A Mode Specification Register
PIO Port A Handshake Specification Register
PIO Port A Data Path Polarity Register
PIO Port A Data Direction Regist~~
PIa Port A Special I/O Control Register
PIa Port A Pattern Polarity Register (PPR)
PIO Port A Pattern Transition Regi~ter (PTR)
PIO Port A Pattern Mask Register (PMR)
PIO Port B Mode Specification Register
PIa Port B Handshake Specification Register
PIO Port B Data Path Polarity Registers
PIO Port B Data Direction Registers
PIO Port,B Special I/O Control Registers
PIa Port B ~attern Polarity Registers (PPR)
PIa Port B Pattern Transition Registers (PTR)
PIa Port B Pattern Mask.Register (PMR)
PIO I/O Buffer Control Register

17777520
17777522
''7777524
777526

KXJ11 Control/Status Register A (KXJCSRA)
KXJll Control/Status Register B (KXJCSRB)
KXJll Control/Status Register C (KXJCSRC)
KXJll Control/Status Register E (KXJCSRE)

7777000
17777002
1777700~'

17777006
17777010
17777012
1777701~~

PRELIMINARY
4/3/86
Memory Map Summary

'.'

A-3

KXJ11-CA User's Guide
Memory Map Summary

PRELIMINARY

17777530
17777532
17777534
17777536
17777540

KXJll Control/Status Register D (KXJCSRD)
Q-Bus Interrupt Register (QIR)
KXJ11 Control/Status Register F (KXJCSRF)
KXJll Control/Status Register H (KXJCSRH)
OJll Control/Status Register J (KXJCSRJ)

17777560
17777562
17777564
17777566

SLU1 Receiver Control/Status Register (RCSR)
SLUl Receiver Buffer Register (RBUF)
SLUl Transmitter Control/Status Register (XCSR)
SLUl Transmitter Buffer Register (XBUF)

17777572
17777574
17777576

Memory Management Register 0 (MMRO)
Memory Management Register 1 (MMR1)
Memory Management Register 2 (MMR2)

17777600 17777620 17777640 17777660 -

17777616
17777636
17777656
17777676

4/3/86

User I Space PORO User D Space PORO User I Space PARO User 0 Space PARO -

PDR7
PDR7
PAR7
PAR7

17777750

Maintenance Register

17777766

CPU Error Register

17777772

PIR

17777776

Processor Status Word (PSW)

A-4

APPENDIX B
KXJll-CA/KXTll-CA DIFFERENCES

B.l

DIFFERENCES BETWEEN THE KXJll-CA AND THE KXTll-CA

Table x··x summarizes the differences between the KXJll-CA and the KXTll-CA.
Table x-x

KXJll-CA/KXT11-CA Differences
KXJll-CA

KXTI1-CA

Memory management

Yes

PRa4

64 KB

8-32 KB

512 KB

32-48 KB

RAM parity

Yes

Shared memory

Yes

Wan. floating-point

Yes

Maintenance Register

Yes

DTC vectc)rs

214 and 220

110 and 114

TPRO (control mode)
TPRO<14>
TPRO<9>
TPRO<8>
TPRO<:7>
TPRO<6>

Hard reset
Execute program
Disable shared memory
Show shared memory
Enable shared memory

Unused
Unused
Unused
Unused
Unused

TPR1<13>

Unused

Trap to 4 disable

TPR1<11>

Address error flag

SP NXM

TPR1<10>

Unused

Power-up with
battery backup

TPR1<9>

Unused

Power-up without

TPRI

8-1

test flag

KXJll-CA User's Guide
PRELIMINARY
KXJII-CA/KXTll-cA Differences

4/3/86

battery backup
TPR1<7>

Unused

Q-Sus ODT flag

TPR1<6>

Unused

Serial OOT flag

TPR1<4>

Firmware handling interrupts

COT on HALT

instruction

TPR1<3>

Unused

Stack error flag

CSRD<15>

PWR

CSRE
CSRF
CSRH

No operation
Yes
Yes

Controls PIa
No
No

HALT instruction

If in kernel mode,
enters serial OOT

Restart

Stack violations and
NXM references in
kernel mode

Fatal runtime error

Not applicable

Exceptions

Caused by the assertion
of SHALT or BINIT, the
deassertion of BPOK, or
the writing of TPRO by
the arbiter

HALT instruction

Battery backup

Yes

Firmware stack

128 KB at top of
kernel stack for
native firmware scratch
area

Separate RAM
in I/O page transparent to
user

Hardware reset

Caused by power-up or
by setting TPRO<14>

Caused by power-up

Arbiter NOP command

Ignored

Reserved

Boot/self test switch

Switch positions 0-6 in KXJ11-CA are identical
to sWltch positions 0-6 in KXTll-CA. Switch
positions 7-15 are unique.

Console ODT

Microcode

Firmware

All alpha characters
must be upper case

Rand 5 may be
upper or lower
case

(close last memory
location or register and

Supported

NXM

B-2

KXJ11-CA User's Guide
PRELIMINARY
4/3/86
KXJll-CA/KXT11-CA Differences
open preceding) not
supported

Software control
of SLU1 baud rate

Examining a range of
locations not supported

Supported

Not supported

Autobaud not supported

Supported

All addresses are 22 bits

All addresses are
16 bits

Two register sets and
three stack pointers.

Not applicable

LEDs Indeterminate

LEOs in fixed state
while in OOT"
-

Selectable by a bit
in KXJCSRJ

Jumper selectable

B-3

Q-bus
KXJ11-C
PERIPHERAL
PROCESSOR/SINGLE
BOARD COMPUTER

September 1986

Product Brief

Features
• J11 (DCJ11-AC) 16-bit microprocessor executes the extended PDP-11 instruction set
including all 46 floating point instructions and memory management.
• 512K bytes of dynamic RAM with dual-ported access. 64K bytes of PROM; 48K for
user code, 16K for native firmware.
• Two synchronous/asynchronous serial line units with baud rates to 76.8K baud
(RS232-C, RS422, and RS423); byte (I BM Bisync) and bit (CCID X.25) modes.
• Console port asynchronous line, DL-compatible.
• 20 programmable buffered parallel lines with pattern recognition.
• 2-channel DMA controller; three counter/timers; four diagnostic LED's; watch dog
timer; real time clock.
• Multiprocessor configuration ability; up to 14 KXJ11-C's in one O-bus backplane.
• Software Support: MicroPower Pascal, with host tool kits supported under MicroVMS,
RSX, and RT-11. Additional software support planned.
• i-year return-to-factory warranty.

Description
The KXJ11-C is a subsystem including a powerful processor, the J11, as the central
compute engine. There is plenty of memory for most applications; 512K bytes of RAM
and 64K bytes of PROM. Several types of I/O structures are provided to support most
forms of peripheral processing and many protocols. DMA capabilities were designed
in to link each of the sections together.

KXJ11-C Single Board Peripheral Processor, Real-Time Processing. Coprocessing,
I/O Processing

Peripheral Processor
The KXJ11-C is a powerful peripheral
processor which can supercharge your
Q-bus system (Figure 1) acting as either
a real-time processor, co-processor, or
I/O processor. As a real-time processor, it
provides predictable real-time response
to interrupts for data collection, CPU
power for local data reduction, sufficiont
memory for temporary storage, and data
transfer mechanisms (DMA, shared
memory) for easy host access to data. In
co-processing applications, the KXJ11-C
offers J11 power with floating point and
512K bytes of memory for working
space. I/O processing applications can
take advantage of the several highspeed SLU's or the parallel interface;
capable of DMA operation and specific
protocol support.
The Microprocessor Unit
The J11 is a high-performance
microprocessor that delivers the
architecture and functions of Digital's
popular minicomputer, the PDP11, in a
60-pin package. A CMOS microprocossor, the J11 has 16-bit I/O and 32-bit
internal data pat.h, and addresses
memory with on-chip pipelined memory
management offering three levels of
memory protection. The chip operates in
the KXJ11-C at a maximum clock rate of
14 Mhz.

Q-BUS

KXJ11-C
PERIPHERAL
PROCESSOR
• CPU
• MEMORY
• ASYNC COMM
• SYNC COMM
• PARALLEL COMM
• DMA

CONCENTRATOR
PROCESS CONTROL DEVICE
COMPUTER SYSTEM

Figure 1. KXJ11-C Sample Configuration
The J11 implements the full PDP-11
instruction set, including hardware
multiply, divide (EIS) and Floating
Point-11 (FP-11) extensions. This means
you can run powerful software and
operating systems for realtime, as
co-processing, and I/O processing
applications. Its comprehensive capabilities include microdiagnostics and console 22-bit ODT on chip for ease of use.

Memory Configurations
The KXJ11-C includes 512K bytes of
dynamic RAM which can be shared with
the Q-bus. This is the only I/O device
which also has the ability to place a
significant amount of memory into Q-bus
memory space. This memory can be
operated on directly both by the local
J11 and devices, and the Q-bus. This is
useful in passing large amounts of data

to or from the KXJ11-G The full 512K
bytes may be shared in contiguous 8K
byte blocks. As a general rule, the local
J11 has priority when it and the Q-bus
are trying to address the sharable
memory simultaneously.
Up to 64K bytes of PROM space is
provided for with two 28 pin sockets.
The native firmware resides in 16K bytes
of the PROM space and the remaining
space is for application code. The
module is shipped with two 8Kx8
PROM's which include the native firmware and self-test. The user can use
16Kx8 or 32Kx8 PROM's to include
application code.

1/0 Capabilities
The KXJ11-C includes three forms of
I/O functionality; asynchronous serial I/o'
synchronous/asynchronous serial I/O;
and parallel I/O.
One asynchronous serial line provides
DL-compatibility, baud rate generation,
program or shunt selectable baud rates

(300 to 38.4K baud), 8-data bits, no
parity, one stop bit and break detection
that causes the J11 microprocessor
to RESTART trap. Also featured are
RS232-C, RS422, and RS423 EIA interfaces, with a 10-pin interface connector.
A dual-channel, multiprotocol serial communications controller is provided with a
send-receive, RS422 and RS423 electrical interface, and modem control lines.
It supports asynchronous, characteroriented synchronous, and bit-oriented
synchronous protocols. Some of the
features of this line are programmable
character size, parity, framing error
detection, auto hunt, and external or
internal programmable baud rates from
150 to 76.8K baud. A synchronousl
asynchronous secondary channel is
provided with type OT (data and timing
only) RS422 and RS423 electrical
interface.
In addition, twenty programmable
parallel 1/0 lines are provided on the
KXJ11-C. Features here include three
interrupt requests and handshake control for either polled, interrupt conditional
control, three wire, or bi-directional operation. Three programmable 16-bit timers
are provided with either internal control
and interrupt, or with external buffered
control lines.

Peripher,al Processor Control
The Q-bus interface includes a 16 word
Two Port I~egister file (TPR). The register
file is the primary means by which the
Q-bus arbiter controls and communicates with the KXJ11-C. The registers can
be processed by both the local J11 and
Q-bus.
DMA Communications
The KXJ11-C 16-bit OMA controller facilitates data tranfers to or from the local 1/0
devices, memory, and Q-bus addresses.
This capability helps to support real-time
data 1/0, high-speed communication,
and the management of data.
The KXJ11-C is addressable by the
arbiter CF)U as an 1/0 device. It supports

two channels of OMA and can perform
transfers between any local 22-bit
address and any 16-, 18-, or 22-bit Q-bus
address. OMA operations can be interleaved with the local processor and the
other OMA channel, or may occur in
various burst sizes.

Multiprocessing or Standalone
Capability
The KXJ11-C provides extensive 1/0
expansion capabilities through the
Q-bus interface. Up t9 14 modules can
reside in one Q-bus backplane with an
arbiter Q-bus CPU. This facilitates the
physical configuration of modules and
cabling. KXJ11-C's can be added modularly, with each dedicated to specific
tasks, thereby greatly increasing the
application's overall performance and
efficiency.
A simple hex-encoded switch configures
the KXJ11-C for standalone operation or
for multiple operation on the Q-bus.
When in standalone mode, even if the
module is physically connected to the
Q-bus, the KXJ11-C does not respond to
any signals on the Q-bus. It will, however,
use the power supply and ground
signals.

Software Environment
The KXJ11-C is supported by six operating systems for the arbiter (or host)
processor. Tool kits are available for
MicroVMS, RSX11-M, RSX11-M PLUS,
MicroRSX, and RT-11. Each tool kit contains two utilities, a device handler and a
load utility. The device handler manipulates the TPR so that an application running in the host environment can
communicate with the MicroPower/Pascal
application running on the KXJ11-C.
The load utility allows MP/P programs

and .SAV images to be loaded into a
peripheral processor from the arbiter,
performs debugging opera1tions, starts
execution of KXJ11-C prdgrams, and
initiates the KXJ11-C self tests.
MicroPower/Pascal (MP/P) is both an
operating system and a highly structured
programming language for applications
executed on any POP-11 processor. As
such, MP/P can be used on the arbiter
or on the KXJ11-C peripheral processor.
On the arbiter side of the Q-bus, M PIP
has, built in, the utilities included in the
tool kits. On the KXJ11-C, MP/P is the
preferred operating environment. It
provides drivers for KXJ11-C onboard
devices such as: serial asynchronous
1/0. serial synchronous I/O. parallel I/O.
three counter/timers, and OMA transfer.
Also included is a utility which permits
the application to pass variable length
messages to the arbiter system by
emulating the traditional O-bus slave.
As an alternative, MACRO-11 can be
used to program the KXJ11-C, if the
user wishes to program in assembly
language.

Physical Specifications
Height
Length
Size
Power Specifications
Operational Power
Bus Loads
Operating Specifications
Temperature
Relative Humidity
Altitude

Storage Specifications
Temperature
Relative Humidity
I/O Specifications
Serial Asynchronous

Serial Async/Sync

Async Operation

Sync Operation

Parallel I/O
Programmable Timers

Parallel 1/0 Lines

10.457 in
8.430 in
Quad-height
+5V ±5%; 6.0A maximum
+ 12V ±5%; 2.oA maximum
AC 3 unit loads; DC 0.5 unit load
5° C to 60° C
10% to 90% noncondensing
1524 km (50,000 ft)
Note: Derate the maximum operating temperature
by 1.0° C for each 1000 meters of altitude above
sea level
-10° C to 65° C
10 0/0 to 90% noncondensing
• Programmable or jumper selectable baud
rates from 300 to 38.4K baud
• nS422, RS232-C, and RS423 compatible
• IJL-compatible, 8-bits only
• 2 channel serial communication controller,
programmable baud rates from 150 to 76.8K
baud
• Data bits: 5, 6, 7, or 8
• Stop bits: 1, 11/2, or 2
• fJarity: odd, even, or no parity
• Character oriented protocol (I BM Bisync)
• f3it oriented protocol (CCITT X.25)

OJ
ill

OJ
OJ
OJ
C'\J

IT:
(j)

1:'
OJ
rI

• :3 timer, 16-bit
• Operating frequency of 2 Mhz
• fJulse output, one-shot, or square-wave modes
• 1 control lines
·16 data lines with programmable parity, programmable direction, pulse catchers, patternrecognition logic

«c
Q

o
o
U
0.

Electrical Parameters

Vih
Vmin
2.0

Vii
V max
0.8

Voh
Vmin

Vol
V max
0.5

~~.5

Input
lih
p.,a min
-200
Output
loh
mamin
-5.2

Iii
p.,a max
40

101
mamin
48

The following are trademarks of Digital Equipment
Corporation'
Digital Logo
PDP-11
KXJ11-C
RSX11-M
MACRO 11
RSX11 MPLUS
MicroRSX
RT11
MicroVMS
MlcroPower/Pascal

Digital believes the information in this publication is
accurate as of its publication date; such information
is subject to change without notice. Digital is not
responsible for any inadvertent mrors.

~
OJ
cS
ill
OJ

D
Q)

~
Q::