Digital PDFs

EK-TSV05-UG-001

September 1982

155 pages

Original

9.5MB

Document:	TSV05 Users Guide
Order Number:	EK-TSV05-UG
Revision:	001
Pages:	155
Original Filename:	http://bitsavers.org/pdf/dec/qbus/EK-TSV05-UG-001_TSV05_Users_Guide_Sep82.pdf

OCR Text

EK-TSV05-UG-001

I
TSV05
Tape Transport Subsystem
User's Guide

momooma

EK-TSV05-UG-001

TSV05
Tape Transport Subsystem
User's Guide

Prepared by Computer Special Systems
of
Digital Equipment Corporation

1st Edition, September 1982

@ 1982 by Digital Equipment Corporation

The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.
Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
Idlilgliltlalll
DEC

PDP
DECUS
UNIBUS

DECsystem-19
DECSYSTEM-29
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
05/8
RSTS
RSX
lAS

CONTENTS

Page
CHAPTER 1

INTRODUCTION

1.1
1.2
1. 2.1
1. 2. 2
1. 2. 3
1.3
1. 3.1
1. 3. 2
1. 3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.4

PURPOSE AND SCOPE ••••••••••••••••••••••••••••••••• 1-1
GENERAL DESCRIPTION ••••••••••••••••••••••••••••••• 1-1
Features and Capabilities •••••••••••••••••••••• 1-3
FunctionalOverview •••••••••••••••••••••••••••• 1-5
Controls and Indicators •••••••••••••••••••••••• 1-6
PHYSICAL DESCRIPTION........................
..1-9
Mechanical Characteristics...............
..1-9
Electrical Requirements •••••••••••••••••••••••• 1-9
Environmental Considerations ••••••••••••••••••• 1-10
Operating Conditions •••••••••••••••••••••••• 1-10
Nonoperating Conditions ••••••••••••••••••••• l-ll
Emissions....
• •••••••••••••••••••••••••• 1-11
RELATED DOCUMENTS ••••••••••••••••••••••••••••••••• 1-12

CHAPTER 2

INSTALLATION

2.1
2.1.1
2.1.2
2.1. 3
2.1.4
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.4.1
2.3.4.2
2.3.5
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.5
2.6
2.6.1

SITE PREPARATION •••••••••••••••••••••••••••••••••• 2-1

2.6.2
2.7
2.7.1

Accessibility ••••••••••••••••••••.••••••••••••• 2-2
Power Receptacles •••••••••••••••••••••••••••••• 2-2
Coo1ing •••••••••••••••••••••••••••••••••••••••• 2-2
Aii Purity ••••••••••••••••••••••••••••••••••••• 2-4
UNPACKING AND INSPECTION •••••••••••••••••••••••••• 2-4
Tools and Working Space •••••••••••••••••••••••• 2-4
Unpacking the Cabinet •••••••••••••••••••••••••• 2-4
Deskidding the Cabinet ••••••••••••••••••••••••• 2-6
Unpacking the Smaller Cartons •••••••••••••••••• 2-8
TAPE TRANSPORT CABINET INSTALLATION ••••••••••••••• 2-8
Tools Required ••••••••••••.•••••••••••••••••••• 2-10
Moving the Side Panel •••••••••••••••••••••••••• 2-l0
Connecting the Cabinets •••••••••••••••••••••••• 2-15
Removing Shipping Foam ••••••••••••••••••••••••• 2-18
Removing the Top Foam Piece ••••••••••••••••• 2-l8
Removing the Bottom Foam Pieces ••••••••••••• 2-l8
Connecting Line Power •••••••••••••••••••••••••• 2-23
TAPE TRANSPORT CHECKOUT ••••••••••••••••••••••••••• 2-24
Power Up Test...........
• •••••••••••••••• 2-24
Tape Loading Test •••••••••••••••••••••••••••••• 2-25
Tape Movement Test ••••••••••••••••••••••••••••• 2-27
Tape Unloading Test •••••••••••••••••••••••••••• 2-28
BUS INTERFACE/CONTROLLER MODULE INSTALLATION •••••• 2-28
CABLE INSTALLATION •••••••••••••••••••••••••••••••• 2-29
M7196 Module and Tape Transport
Interconne6tion •••••••••••••••••••••••••••••••• 2-29
Power Controller Interconnection ••••••••••••••• 2-3l
TSV05 SUBSYSTEM CHECKOUT •••••••••••••••••••••••••• 2-32
Power Up Checks •••••••••••••••••••••••••••••••• 2-32
iii

CONTENTS (CONT)

Page
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.S

TSV05 SUBSTYSTEM CHECKOUT ••••••••••••••••••••••••• 2-32
Power Up Checks •••••••••••••••••••••••••••••••• 2-32
System Setup ••••••• ~ ••••••••••••••••••••••••••• 2-33
TSV05 Logic Test ••••••••••••••••••••••••••••••• 2-33
Advanced Logic Test •••••••••••••••••••••••••••• 2-35
Tape Transport Test •••••••••••••••••••••••••••• 2-35
Advanced Tape Transport Test ••••••••••••••••••• 2-36
Data Reliability Test •••••••••••••••••••••••••• 2-36
Additional Testing ••••••••••••••••••••••••••••• 2-37

CHAPTER 3

OPERATION

3.1
3.1.1
3.1. 2
3.1. 3
3.1.4
3.1.5
3.1.5.1
3.1.5.2
3.1.6
3.1.7
3.1. S
3.1.S.1
3.1.S.2
3.2
3.3
3.3.1
3.3.2
3.3.2.1
3.3.2.2
3.3.2.3
3.3.2.4
3.3.2.5
3.3.2.6
3.3.2.7
3.3.2.S
3.3.2.9
3.3.2.10
3.3.3
3.3.3.1
3.3.3.2
3.3.3.3
3.3.3.4

ROUTINE OPERATING PROCEDURES •••••••••••••••••••••• 3-1
Power Up .••.•.•..••••••.••.••...•.......••••..• 3-!
Loading Tape ••••••••••••••••••••••••••••••••••• 3-1
Rewinding Tape ••.•.••.•••...••.•••.•••...•.•..• 3-2
Unloading Tape ••••••••••••••••••••••••••••••••• 3-4
Restarting the Tape Subsystem •••••••••••••••••• 3-4

Power Failure ••••••••••••••••••••••••••••••• 3-4
Hard Errors ••••••••••••••••••••••••••••••••• 3-4
Operator Troubleshooting ••••••••••••••••••••••• 3-5
Confidence Checks •••••••••••••••••••••••••••••• 3-5
Customer Case •••••••••••••••••••••••••••••••••• 3-6
Case of Magnetic Tape ••••••••••••••••••••••• 3-6
Preventive Maintenance •••••••••••••••••••••• 3-7
TSV050PERATIONS •••••••••••••••••••••••••••••••••• 3-12
PROGRAMM ING ••••••••••••••••••••••••••••••••••••••• 3-12

Overview . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . • . . . 3-13
Registers •••••••••••••••••••••••••••••••••••••• 3-1S
Bus Address Register (TSBA) ••••••••••••••••• 3-1S
Data Buffer Register (TSDB) ••••••••••••••••• 3-20
Status Register (TSSR) •••••••••••••••••••••• 3-22
Extended Data Buffer Register (TSDBX) ••••••• 3-26
Extended Status Register 0 (XST0) ••••••••••• 3-27
Extended Status Register 1 (XST1) ••••••••••• 3-30
Extended Status Register 2 (XST2) ••••••••••• 3-32
Ex tended Sta tus Reg i ste r 3 (XST3) ••••••••••• 3-34
Extended Status Register 4 (XST4) ••••••••••• 3-35
Summary of Registers •••••••••••••••••••••••• 3-37
Packet processing •••••••••••••••••••••••••••••• 3-39
Buffer Ownership and Control •••••••••••••••• 3-40
Buffer Control on Attentions •••••••••••••••• 3-42
Message Packet Format ••••••••••••••••••••••• 3-44
General Status Handling Information ••••••••• 3-47

CONTENTS (CONT)

Page
3.3.4
3.3.4.1
3.3.4.2
3.3.4.3
3.3.4.4
3.3.4.5
3.3.4.6
3.3.4.7
3.3.4.8
3.3.4.9
3.3.4.10
3.3.5
3.3.5.1
3.3.5.2

Command Packet Definitions ••••••••••••••••••••• 3-54
Get Status Command ••••••••••••••••••••••••••••• 3-60
Read Command ••••••••••••••••••••••••••••••••••• 3-60
Write Characteristics Command •••••••••••••••••• 3-63
Write Command ......••...••..•••.•.•....•.•.•..• 3-69
position Command...
• ••••••••••••••••••••••• 3-70
Format Command ••••••••••••••••••••••••••••••••• 3-72
Control Command •••••••••••••••.•.••.••••.•••••• 3-73
Inititalize Command •••••••••••••••••••••••••••• 3-74
Write Subsystem Memory Command ••••••••••••••••• 3-74
Record Buffering •••••••••..•••••••••.••••.••.•••.• 3-75
Read Buffering •••.••.••••••••••••••••••••••.••• 3-75
Write Buffering •••••••••••••••••••••••••••••••• 3-78

APPENDIX A

CONFIGURATION DATA •••••

APPENDIX B

MANUAL LOADING •••••••••••••••••••••••••••••••••••• B-1

APPENDIX C

SUMMARY OF KNOWN DIFFERENCES •••••••••••••••••••••• C-l

COMMANDS •••••••••••••••••••••••••••••••••••••••••• 3- 53

•..•••••••...•••..•••.•. • A-I

FIGURES
Figure No.
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18

Title

Page

TSV05 Subsystem Components •••••••••••••••••••••••• 1-2
Operator Front Panel •••••••••••••••••••••••••••••• 1-7
Cabinet Access Requirements ••••••••••••••••••••••• 2-3
Cabinet Carton Removal •••••••••••••••••••••••••••• 2-5
Removing Shipping Bolts ••••••••••••••••••••••••••• 2-6
Deskidding the Cabinet •••••••••••••••••••••••••••• 2-7
Tape Transport Cabinet Connection ••••••••••••••••• 2-9
Installing Leveling Feet •••••••••••••••••••••••••• 2-11
Computer Cabinet Ground Connection •••••••••••••••• 2-12
Removing Side Panel ••••••••••••••••••••••••••••••• 2-13
Mounting the Side Panel ••••••••••••••••••••••••••• 2-14
Cabinet Alignment ••••••••••••••••••••••••••••••••• 2-16
Cabinet Interconnection Hardware •••••••••••••••••• 2-17
Cabinet Top Cover ••••••••••••••••••••••••••••••••• 2-19
Tape Transport Top Cover •••••••••••••••••••••••••• 2-20
Tachometer and Takeup Hub ••••••••••••••••••••••••• 2-21
Service Access Position ••••••••••••••••••••••••••• 2-22
Front Panel Controls and Indicators ••••••••••••••• 2-24
Inserting Tape •••••••••••••••••••••••••••••••••••• 2-26
Cabling the M7196 Module •••••••••••••••••••••••••• 2-30
v

CONTENTS (CONT)

Page
2-19
2-20
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19(a)
3-19 (b)
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
A-I
A-2
A-3

8-1
8-2

Cabling the Tape Transport •••••••••••••••••••••••• 2-30
Remote Power Control Connections •••••••••••••••••• 2-31
Opening the Front Door Panel •••••••••••••••••••••• 3-3
Accessing the Tape Path Area •••••••••••••••••••••• 3-10
Tape Path and Related Parts ••••••••••••••••••••••• 3-11
Command Packet Types •••••••••••••••••••••••••••••• 3-17
TSBA Register Format ••••••••••••••••••••••••••••• 3-19
TSDB Register Format ••••••••••••••••••••••••••••• 3-21
TSSR Register Format ••••••••••••••••••••••••••••• 3-22
TSDBX Register Format ••••••••••••••••••••••••••••• 3-26
XST0 Register Format ••••••••••••••••••••••••••••• 3-27
XSTI Register Format ••••••••••••••••••••••••••••• 3-30
XST2 Register Format ••••••••••••••••••••••••••••• 3-32
XST3 Register Format ••••••••••••••••••••••••••••• 3-34
XST4 Register Format ••••••••••••••••••••••••••••• 3-35
TSV05 Hardware Device Registers ••••••••••••••••••• 3-37
TSV05 Extended Status Registers ••••••••••••••••••• 3-38
TSV05 Command Register Format ••••••••••••••••••••• 3-39
Message Packet Format ••••••••••••••••••••••••••••• 3-44
Command Packet Header Word •••••••••••••••••••••••• 3-54
Memory/Tape Data Byte Positioning (Forward Tape
Direction, Read or Write; Reverse Read with Even
Byte Count) ••••••••••••••••••••••••••••••••••••••• 3-58
Memory/Tape Data Byte Positioning (Forward or
Reverse Read, Odd Byte Count) ••••••••••••••••••••• 3-59
Get Status Command Packet ••••••••••••••••••••••••• 3-60
Read Command Packet ••••••••••••••••••••••••••••••• 3-61
Write Characteristics Command Format •••••••••••••• 3-65
Write Command Packet •••••••••••••••••••••••••••••• 3-69
Position Command Packet ••••••••••••••••••••••••••• 3-71
Format Command Packet ••••••••••••••••••••••••••••• 3-72
Control Command Packet •••••••••••••••••••••••••••• 3-73
Initialize Command Packet ••••••••••••••••••••••••• 3-74
M7196 Switch and Jumper Identification •••••••••••• A-l
M7196 Vector and Address Switches ••••••••••••••••• A-2
Transport Switch and Terminator Identification •••• A-3
Accessing the Tape Path Area •••••••••••••••••••••• B-2
Tape Threading Path ••••••••••••••••••••••••••••••• B-3

TABLES
Table No.
1-1
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18

Title

Page

Controls and Indicators ••••••••••••••••••••••••••• 1-7
Power Line Connections •••••••••••••••••••••••••••• 2-2
TSV05 Subsystem Diagnostics ••••••••••••••••••••••• 2-32
Suggested Preventive Maintenance Schedule ••••••••• 3-8
TSV05 Assigned Command Modes •••••••••••••••••••••• 3-l4
TSBA Register Bit Definitions •••••••••••••••••••• 3-l9
TSDB Register Bit Definitions •••••••••••••••••••• 3-2l
TSSR Register Bit Definitions •••••••••••••••••••• 3-22
TSDBX Register Bit Definitions •••••••••••••••••••• 3-27
XST0 Register Bit Definitions •••••••••••••••••••• 3.-28
XSTl Register Bit Definitions •••••••••••••••••••• 3-31
XST2 Register Bit Definitions •••••••••••••••••••• 3-33
XST3 Register Bit Definitions •••••••••••••••••••• 3-34
XST4 Register Bit Definitions •••••••••••••••••••• 3-36
Buffer Ownership Transfers •••••••••••••••••••••••• 3-40
Message Packet Field Definitions •••••••••••••••••• 3-45
Termination Class/Message Type Relationship ••••••• 3-48
Command Packet Header Word Bit Definitions •••••••• 3-55
Command Code and Mode Field Definitions ••••••••••• 3-57
Characteristic Mode Data Word Bit Definitions ••••• 3-66
Extended Characteristics Data Word Bit
Definition •••••••••••••••••••••••••••••••••••••••• 3-67

vii

CHAPTER 1
INTRODUCTION

1.1 PURPOSE AND SCOPE
This manual describes how to unpack, install, and check out the
TSV135 Tape Transport Subsystem.
It also describes the capabilities and basic functions of the subsystem.
An overview of the
functional characteristics and the physical specifications appears
in Chapter 1, while Chapter 2 is devoted to the installation.
Chapter 3 discusses various aspects of system operation, including
routine operating procedures and programming requirements.
For
further information, refer to the documents listed in Section 1.4.
1.2 GENERAL DESCRIPTION
The TSV135 Tape Transport Subsystem provides magnetic tape storage
capabilities to computer systems using quad-sized LSI-II bus backplanes.
The subsystem reads or wr i tes up to 1613,131313 bytes per
second in ANSI standard format.
Data is recorded by phase encoding 161313 bits per inch on nine-track tape.
Reading and writing
are performed at either 25 or 11313 inches per second.*
The TSV135
subsystem is hardware compatible wi th 18- and 22-bi t addressing
versions of the LSI-II bus quad backplane.
It is software compatible with system and application programs written for the TSII
tape transport subsystem (as long as such programs use the DECsupplied device handler).
Tape formatting, error detection and
correction, and self-test diagnostics are included as integral
components of the TSV135 subsystem.
The TSV135 hardware consists of four items:
1.

TS135 tape transport

M7l96 LSI-II bus interface/controller module

H9642-series cabinet, including 874 power controller and
remote power control cable

Pair of 71316855 bus cables for connecting tape transport
input and output to the bus interface/controller module.

The bus interface/controller module plugs into the LSI-II bus (see
Figure 1-1).
The two cables connect the module with the tape
transport.
*11313 IPS operating speed requires
the appropriate software.

1-1

enabling

special

features

and

LSI-ll BUS

M7196

INTERFACE/CONTROLLER
MODULE

TRANSPORT
BUS

TS05
TAPE TRANSPORT

C5-2428

.... 99-

.<&.

CS-2448

Figure 1-1 TSV05 Subsystem Components
1-2

1.2.1 Features and Capabilities
The TSV05 Tape Transport Subsystem offers the following:
o

Bidirectional reading capability

3.5K bytes of RAM in controller for buffering tape data

Streaming, or reel-to-reel, technology (meaning that the
tape is not required to stop in the interrecord gap)

Automatic tape loading (threading)

Microprocessor control in both the controller and the tape
transport

Microcoded diagnostic and maintenance features

Tape formatting and
3.39-1973 Standard

Both ANSI and IBM tape mark detection

Industry standard bus between controller and tape transport

On-line diagnostics that verify data path integrity during
idle periods

Uses media conforming to ANSI X 3.40-1976 Standard

Automatic read after write verification

Small form factor with low power consumptions.

error

detection

following

ANSI

The tape handling characteristics and parameters are as follows:
Tape Characteristics
Type:

Mylar base, iron-oxide coated

Lenqth:

731 m (2400 ft) maximum

Width:

1 • 3 cm (0. 5 in)

Thickness:

1.5 mil (industry compatible)

Reel Diameter:

26.7 cm (10.5 in) 2400 ft
21.6 cm ( 8.5 in) 1200 ft
17.8 cm ( 7.0 in)
600 ft

Capacity/Tape Reel:

46 million bytes
matted)

1-3

(10.5

in reel,

unfor-

Tape Motion
Handling:

Bidirectional reel-to-reel, with compliance arm

Tape Tension:

212.6 g (7.5 oz) nominal

Read/Write Speed:

64 cm/sec
software)

(25

64 or 254 cm/sec (25
(program
selectable
software)
Rewind Speed:

(using

in/sec)

TSll

or 100 in/sec)
using
spec i al

330 to 457 cm/sec (130 to 180 in/sec)
(nominal), depending on reel size
445 cm/sec (175 in/sec)
26.7 cm (10.5 in) reel

(average), using

Rewind Time:
Reel Size, cm (in)

Minutes, maximum

17.8 (7.0)
21.6 (8.5)
26.7 (10.5)

0.9
1.6
2.8

Auto Loading
Reliability:

An average of 96% of attempted loads will be
successful, with automatic retries, assuming a
properly maintained transport and tape library.

Retries:

Three automatically provided.

Times:

30 sec typical with no retry
30 sec maximum for each additional retry

Unloading
Time:

15 sec maximum with tape located at BOT

Tape Speed Variation:
Long Term:
In stantaneou s:

+ 1% of nominal
+ 4% of long term

Data Acce ss Time s:

Tape at Re st:
Worst Case:

64 cm/sec (25 in/sec)

254 cm/sec (100 in/sec)

40 ms
140 ms

260 ms
1040 ms

1-4

Data Transfer Rate:

40K bytes/sec
i n/ sec)

cm/sec

(25

160K byte s/ sec
in/sec)

254

cm/ sec

(100

Data Organization
Number of Tracks:

Nine (eight data; one parity)

Recording Density:

160 0 bit s/ i n (n 0 n se 1 e c tab 1 e)

Interrecord Gap:

1.3 cm (0.5 in) minimum, 1.65 cm
(0.65 in) typical at 64 cm/sec (25
i n/ sec)

Recording Method:

Phase encoded (PE)

Er ror Rate s:

Recoverable Write:

1 error in 10 8
bits transferred

Recoverable Read:

1 error in 10 9
bits transferred

Unrecoverable Read: 1 error in 10 10
bits transferred
The LSI-II bus interface characteristics are as follows:
Address Space Required:

772520/772522
772524/772526
772530/772532
772534/772536

1st
2nd
3rd
4th

unit
unit
unit
unit

224

1st
2nd
3rd
4th

unit
unit
unit
unit

Vectors Required:

*
*
*

1.2.2 Functional Overview
Tape loading is automatic. There are no vacuum columns, retaining
clips, or multiple tension arms.
When the tape transport is powered up, sets of internal diagnostics are run by the microprocessors in the tape transport electronics package and the bus interface/controller module. The subsystem is then ready for loading.
Once the tape has been inserted and the door closed, the
TS05 tape transport automatically seats and locks the tape reel on
the spindle, and thread s the tape through the correct path to the
takeup reel. The threading operation is accomplished by precisely
directed air flows that blow the tape along the path to the takeup
reel.
When this power up and load sequence is complete, control
of the tape transport switches to the controller module.

* Rank of 37 in the floating vector area starting at 300.
1-5

The TSV05 subsystem operates under the control of a microprocessor
on the M7l96 bus interface/controller module.
The module is a
direct memory access (DMA) device in that it transfers data directly into or out of the LSI-II memory without requiring the control of the LSI-II CPU.
To perform a data transaction wi th the
TSV05 subsystem, the LSI-II first builds a "packet" of command
words in main memory. Next, it passes the starting address of the
command packet to the M7l96 module. Using this address, the M7l96
module performs a DMA transfer to bring the command packet out to
the controller memory.
The command packet tells the controller
what type of operation is to be performed and where the data is to
come from or go to. The module then controls the movement of data
from LSI-II memory to the tape, or from tape to memory.
It buffers this data so that DMA transfers can be handled independently
of the mechanical movements of the tape.
Addi tionally, it generates interrupts when necessary to provide the LSI-II with status
information.
The TS05 tape transport has an internal formatter that controls
tape motion, formatting and wri ting of data on tape, reading of
data from tape, and tape transport status moni toring.
Commands
from the M7l96 module are latched into registers and then processed by a microprocessor in the formatter electronics. The formatter creates the identification (10) burst, preamble, post
amble, and file mark during a write operation, and it interprets
these during a read operation.
The formatter also oversees the
handling of error conditions.
1.2.3 Controls and Indicators
The M7l96 bus interface/controller module has jumpers, DIP switchpacks, and LED indicators. The jumpers and switchpacks are preset
to the normal configuration and do not need to be changed unless
there is an address conflict with an existing device. The LED indicators are provided as maintainability features, and are not exposed to view during normal operation.
The TS05 tape transport has an ON/OFF (1/0) power switch and five
tactile swi tches, each wi th an LED indicato r.
(Refer to Figure
1-2.)
The functions of these controls and indicators are described in Table 1-1.
The TS05 tape transport also has internal
swi tches for selecting tape units and enabl ing certain features,
but these are preset and normally not changed. It also has an LED
faul t indicator.
This LED is not exposed to view during normal
operation.
.

1-6

~D~DDmD TS05

000

o[JJ

00000

LOAD UNLOAD ON LINE WRITE
REWIND
TEST

ENTER

POWER
C8-2429

Figure 1-2
Table 1-1
Control/
Indicator

Operator Front Panel
Controls and Indicators
Function

Type

POWER

On/off rocker switch
and indicator

Switches
off.

line

power

and

LOAD
REWIND

Tactile switch and
indicator

1. Blinks when the tape drive
is executing a load or rewind sequence.
2. Lit continuously when the
beginning of tape (BOT)
marker is sensed.
3. pressing the switch:
a. Initiates load sequence
and advance s tape to
load point.
b. Rewinds the
load point.

UNLOAD

tape

1. Pre ssi ng the swi tch cau se s
the tape to be unloaded
regardle ss of tape po sition.

Tactile switch and
indicator

2. Blinks when the tape drive
is executing an unload sequence.

1-7

Table 1-1
Control/
Indicator

Controls and Indicators (Cont)
Function

Type
3.

Lit continuously when the
tape drive has completed
its unload sequenc e and
the front acce ss door is
unlocked. At thi s time,
the tape may be removed
and another tape inserted
into the drive.

4. Lit

continuously after a
successful power up, indicating
a tape may be
loaded.

ON-LINE

Tactile switch and
Indicator

Lit when drive
and on-line.

ready

2. Pressing the switch:

a. Takes the tape drive
off-line
and
extingui she s the indicator.
b. Put s the tape dr i ve
on-line and lights the
indicators.
NOTE
Pressing the switch during a load sequence puts the tape drive on-line when
the BOT marker is sensed.
TEST

Tactile swi tch

Operational only in the test
mode. Selects alternative operational mode for other
swi tche s.

WRITE

Indicator

1. Lit when the write ring is

installed and data may be
written on tape.
in die a tor i s off,
inwr i t e ring i s no t
stalled and tape is file
protected.

2. Wh e n

ENTER

Thi s control is used for manual loading, and controlling
the test mode.

Tactile swi tch

1-8

1.3

PHYSICAL DESCRIPTION

1.3.1

Mechanical Characteristics

Tape Transport Cabinet
He ight:

111.13 cm (43. 75 in)

Width:

59.69 cm (23.50 in)

Depth:

83. 82 cm (33.00 in)

Weight:

121 kg (265 lb)

M7l96 Bus Interface/Controller Module
Length:

(From contact finger s to handles) : 228.6 mm (9.0
in)

Width:

266.7 mm (10.5 in)

Thickness:

12.7 mm (0.5 in)

Weight:

0.51 kg (1.13 lb)

Formatter Bus Cables

1.3.2

Connector s:

50-pin, right-angle, flat cable header connectors at controller end; industry standard
formatter connectors at tape transport end.

Length:

2.4 m (8.0 ft)

Electrical Requirements

Tape Transport Cabinet
Power Consumption:

220 W average
270 W maximum

Vol tage (+7% or -15%) :
Nominal, Vdc

Low Limit, Vdc

Hi9h Limit, Vdc

120
240
220

102
204
187

128
256
235

TSV05-BA
TSV05-BB
TSV05-BD
Frequency: + 1 Hz

Nominal, Hz

Low Limit, Hz

High Limit, Hz

50 or 60

1-9

Frequency Rate of Change: 1.5 Hz/sec maximum
M7196 Controller

1.3.3

Power Consumption:

5 Vdc + 5% at 6.5 A (maximum)

LSI-II Bus Loading:

DC:
AC:

One load
Three loads (maximum)

Environmental Considerations

1.3.3.1 Operating Conditions -- The TSV05
to operate under the following conditions:

subsystem is designed

Temperature
IS o C to ~2oC
Temperature Shock: 20 0 C change/hr maximum
Relative Humidity
20% to 80% noncondensing
Altitude
Sea level to 3 km (10,000 ft)
Vibration
Frequency Range:

5 to 500 Hz

Peak Acceleration:

0.25 g, 22 to 500 Hz, 0.01 in DA5-22 Hz

Application:

Each of three orthogonal axes

Shock
+10 g peak, Halfsine, 10 ms
Pollutants
Atmospheric Particulates:

60 mg/1000 cu ft air by weight of
particle (5 micron diameter)

Electrostatic Discharge
10 kV through

l~~

ohms from 350 pF

1-10

1.3.3.2 Nonoperating Conditions -- The TSV135 subsystem is designed to withstand the following conditions during nonoperating
periods (e.g., shipping):
Temperature
-413 0 C to 66 0 C
Relative Humidity
95% maximum, noncondensing
Altitude
Sea level to 15 km (49,131313 ft)
NOTE
Magtape media typically has more restricting nonoperating environmental
considerations.
Vibration (in shipping container)
Frequency Range:

113 to 31313 Hz

Peak Acceleration:

1.4 g rms vertical axi s
13.68 g rms longitudinal and lateral axis
21313 Hz maximum

Shock (in shipping container)
Peak Acceleration:

213 g

Duration:

313 + 113 ms

Wave shape:

1/2 sine

1.3.3.3 Emissions
During normal operation, the TSV135 subsystem
is designed to emit no more than the following levels:
Heat
1100 Btu/hr maximum
Acoustic Noi se
Standby (blower on):

57 dB A scale

Operating Conditions:

613 dB A scale

1-11

Electromagnetic Interference (EMI)
Complies with FCC Part 15, Subpart J, Class A.
Designed to comply with VDE 0871 B requirements.
NOTE
The TSV05 subsystem has been designed
and tested to meet Digital standards including FCC requirements.
The specifications in this chapter are based on
this testing.
Digital cannot guarantee
the TSV05 subsystem will meet these
specifications if nontested equipment is
installed into the TSV05 cabinet or the
TSV05 cabinet is installed in nontested
configurations.
1.4

RELATED DOCUMENTS
Title

Order Number

TSV05 Tape Transport Pocket Service Guide

EK-TSV05-PS

Operation and Maintenance Instructions for
Model F880 Tape Transport

799816-000*

TSV05 Tape Transport Subsystem Installation Guide

EK-TSV05-IN

XXDP User Guide

AC-9093l-MC

DEC/XII User Document

AC-8240Z-MC

TS05 Tape Transport Operation and Acceptance
Preventive Maintanance Remove/Replace

EY-D3l42-PS

TSV05 Field Print Set

MP-0l157

TSV05 Subsystem Technical Manual

EK-TSV05-TM

Microcomputers and Memories

EB-1845l-20

Microcomputer Interfaces Handbook

EB-17723-20

CAUTION
Reference the appropriate TSV05 Manual
for installation, operation, and maintenance information.
*Available from Cipher Data Products, 10225 Willow Creek Road, San
Diego, California 92131.
This document contains detailed
drawings of the TS05 formatter and power supply.

1-12

CHAPTER 2
INSTALLATION

This chapter explains the TSV05 Tape Transport Subsystem installation. A section is devoted to each of the following:
1.

Site preparation

Unpacking and inspection

Installing the tape transport cabinet

Checking out the tape transport

Installing the bus interface/controller module

Installing the interconnecting cables

Checking out the TSV05 subsystem.
NOTE
BEFORE YOU UNPACK the cartons, inspect
for signs of shipping damage.
If the
shipment has been damaged, call the
dealer from whom the equipment was purchased.
If the equipment is covered
under "Digital Transit Insurance", the
Digital representative will estimate the
damage and put in a claim.
If the
equipment is not insured by "Digital
Transit Insurance" contact the carrier
who handled the equipment and your own
insurance company.
Digital Field Service is available on a per-call basis to
make estimates of damage for any resulting insurance claims.

2.1 SITE PREPARATION
The TSV05 Tape Transport Subsystem mounts to the left side of the
existing computer cabinet. It requires a 59.7 centimeter (23.5
inch) wide by 83.8 centimeter (33.0 inch) deep area of floor space
that is capable of supporting, a s a minimum, 121 kilograms (265
pounds). The cabinet is capable of supporting up to 205 kilograms
(450 pound s) •
Beyond this mounting space, the TSV05 subsystem also requires room
for access to the cabinet, the correct power receptable, and an
adequate flow of cooling air.

2-1

2.1.1 Accessibility
The cabinet requires sufficient space behind it for opening the
rear door.
If any expansion is anticipated, room in front of the
cabinet wi 11 be requi red to allow f ut ure equi pment to be pulled
out of the cabinet for maintenance.
Refer to Figure 2-1 for the
required dimensions.

2.1.2 Power Receptacles
Ensure that the correct power receptacle is available (refer to
Table 2-1).
It should be capab1 e of handl i ng a t lea st the 270
watts required by the tape transport.
Table 2-1
MODEL

Power Line Connections
RECEPTACLE

PLUG
w

SILVER~
TSV05-BA

BRASS

TSV05-BB
-BD

NEMA # L5-30P
DEC # 1 2-111 93

==
~

NEMA #6-15P
DEC #90-08853

L5-30R
12-11194

BRASS2~
BRASS 1

CIRCUIT RATING

120 V
24A

220/240 V
12A

6-15R
12-11204
CS-2431

Power Cord Color Code
Pin Connection
Function

L5-30P

6-15P

Brown

Hot

Brass

Brass 1

Blue

Neutral

Silver

Brass 2

Green/yellow

Ground

Color

2.1.3 Cooling
The TSV05 subsystem requires 1100 Btu per hour of cooling
provided by the movement of room air through the cabinet.

2-2

to be

TOP VIEW

1534 mm
: (21 in)
I

I
I

838 mm
(33 in)

TSV05-B MUST BE
BOLTED TO ADJACENT
CABINET

FRONT VIEW

1111 mm
(43 %"in)

FILLER
PANELS

I
H9642
CABINET

......______
L597mm
.

(23 Yz in)

I
I
~----------..J--

----+J

CS·2430

Figure 2-1

Cabinet Access Requirements

2-3

2.1.4 Air Purity
The tape transport is equipped wi th internal fi 1 ters to prevent
dust from accumulating on the tape and tape heads.
Nevertheless,
it is good practice to avoid placing the cabinet in the path of a
dust-laden current of air (such as beside a door).
2.2 UNPACKING AND INSPECTION
The TSVI2J5 is shipped as one skid-mounted carton and one or more
smaller cartons.
The carton on the skid contains the TSI2J5 tape
transport cabinet.
The smaller carton(s)
contain the M7196
controller,
the
documentation
and
accessories,
and
two
individually packaged cables.
These smaller items may be shipped
in one carton or two, depending on shipping requirements.
Check
the shipping documents to ensure that the correct model has been
shipped.
If anything is missing, damaged, or incorrect, contact
the dealer from whom the equipment was ordered.
2.2.1 Tools and Working Space
The following tools are required
tem:
1.

Scissors

9/16 inch wrench

3/4 inch wrench

Hammer

5/32 inch hex key

for

unpacking

the TSVI2J5 subsys-

Also, an area of approximately 3 meters (HI feet) square
quired for moving the cabinet off the shipping skid.
2.2.2

re-

Unpacking the Cabinet

Cut the nylon straps and remove the cardboard pieces of
the cabinet carton as shown in Figure 2-2.
Remove the
plastic bag.

Using a 9/16 inch wrench, remove the four bolts that hold
the cabinet to the skid.

Slide the wooden blocks out
Figure 2-3).

from

under

the cabinet

(see

CAUTION
Once the blocks have been removed, the
cabinet is free to roll on its casters.
The cabinet is top-heavy and must be
handled with care.
The bloc ks may requi re a few taps wi th a hammer to move
them out from under the cabinet.
It may be helpful to
tilt the cabinet slightly while removing the blocks.
2-4

REMOVE

LIFT AND

REMOVE

Cardboard
Tube

Cover

Plastic
Bag

CS-2432

Figure 2-2

Cabinet Carton Removal

2-5

REMOVE SHIPPING
BOLTS (

RED METAL
SHIPPING BRACKETS (4)
SLIDE SHIPPING _ _----~,--"i~
BLOCKS OUT (4)

CS·2433

Figure 2-3
2.2.3

Removing Shipping Bolts

Deskidding the Cabinet
WARNING
Two people are required for moving the
cabinet off the skid.

The recommended procedure for removing the tape transport cabinet
from the- skid i s as follows:
1.

One person stands in front of the cabinet while the other
per son stand s behind it.

Grasp the cabinet by right top and by the left center, as
shown in Figure 2-4.

Roll the cabinet off the side of the skid, taking care to
prevent it from toppling over.

When the ca ster s on the lef t side of the cabinet are on
the floor, push the skid out from under the right side of
the cabinet.
Take care to prevent the cabinet f rom hi tting the floor hard or toppling.

2-6

CS-2435

Figure 2-4

Deskidding the Cabinet

2-7

\1Jith the cabinet standing on the floor, use a 3/4 inch
wrench to remove the red metal shipping brackets from the
bottom.
Af ter they are 100 sened, the bracket s sl ide
outward.

Open the rear door using a 5/32 inch hex key (see Figure
2-6) and verify that the envelope taped to the bottom of
the cabinet contains:
a.

7008288-8F remote cable

H9544-HB leveler feet and hardware

7422224/7422225 intercabinet hardware

2.2.4 Unpacking the Smaller Cartons
Open the smaller cartons and check that they contain the following:
1.

M7l96 bus interface/controller module

Two interconnection cables (part number 7016855-08)

TSV05 Tape Transport
(thi s manual)

TSV05 Tape Transport User's Guide (EK-TSV05-UG)

TSV05 Pocket Service Guide (EK-TSV05-PS)

26.7 centimeter (10.5 inch) magtape number 30-18709-08

Tape cleaning kit part number TUC02

MP0ll57 field print set.

Installation

Manual

(EK-TSV05-IN)

Vi sually in spect each i tern.
If any item is damaged, mi ssi ng, or
incorrect, contact the dealer from whom the system was purchased.
2.3 TAPE TRANSPORT CABINET INSTALLATION
The TSV05 subsystem is designed to be connected to the left side
of an H9642 cabinet that contains a PDP-ll/23 computer.
Older
LSI-II computer systems that use H9612 cabinetry require
alternative installation procedures. These procedures are defined
in the MP0ll57 print set.
The tape transport cabinet is shipped
with no side panels, but with an expansion ring on the right side
of the cabinet.
(Refer to Figure 2-5.)
The left side panel of
the computer cabinet is moved to the left side of the tape
transport cabinet.
Then the right side of the tape transport
cabinet is bolted to the left side of the computer cabinet.

2-8

--,.

illIIID RL02

)c::::rIi..... DODOO

~ ..

11IDiiIiTi!l= I
I

«= ggg»)

ITIIIID RlO2

~.~~-

SIDE PANEL
EXPANSION RING
TAPE TRANSPORT
CABINET

EXISTING LSI-11
COMPUTER CABINET

/
ITIIIIlJ RlO2

~ c::::rIi..... 0"0000 QI

:!@j

~
I~-

aIIJl] RL02

«= ggg»)

:wj
Ij

EXPANDED SYSTEM
CS·2436

Figure

2-5

Tape Transport Cabinet Connection

2-9

This configuration has been tested for compliance with FCC requirements.
Installing the TSV05 subsystem in other configurations may result in higher levels of EMI radiation.
2.3.1 Tools Required
Cabinet installation requires the following tools:

9/16 and 11/16 inch wrench (for leveling feet)

5/32 inch hex key (for door)

7/16 inch wrench (for bolting cabinet together)

Screwdriver or nut driver,
ground cable.

as applicable,

for connecting

2.3.2 Moving the Side Panel
Install the TS05 cabinet levelers and move the side panel as follows:
1.

Install the four leveling feet on the bottom of the TS05
cabinet (Refer to Figure 2-6.)
The leveling feet are
screwed
into the holes previously used by the red
shipping brackets. The cabinet must be tilted to the left
to provide clearance for installing the feet on the right
side, and tilted to the right while installing the feet on
the lef t side.
CAUTION
Do not tilt cabinet more than necessary.
Approximately 5 centimeter s (2 inche s)
of clearance is necessary to insert the
leveling feet.

Open the rear door of the TS~5 cabinet and the CPU cabinet.
Typically, thi s requires inserting the hex key into
the latch and turning it 1/4 turn counterclockwise.
(See
Figure 2-7.)

Remove the locking bracket located at the rear bottom,
right-hand side of both cabinets.
Each bracket is held by
two bolts. Loosen but DO NOT remove the bolts.

Lift the side panel straight up and remove it from the CPU
cabinet left side (see Figure 2-8).
Di sconnect the side
panel ground wire from the cabinet frame.

Place the side panel removed in step 4 next to the TS05
cabinet left side. Connect the side panel ground strap to
the TS05 cabinet using the hardware supplied on the left
rear cabinet rail.

2-10

WARNING
CABINET MUST BE
HANDLED WITH CARE
TO AVOID INJURY.

REMOVE LEVELING FEET
FROM SHIPPING BAG.

ENSURE THAT NUT, LOCK
WASHER AND FLAT WASHER
ARE ON EACH FOOT.

TURN NUT DOWN TO BOTTOM.

SCREW FOOT INTO THREADED
HOLE IN BOTTOM OF CABINET
FAR ENOUGH TO PERMIT THE
CABINET TO BE ROLLED ON
ITS CASTERS.
CS-2443

Figure 2-6

Installing Leveling Feet

2-11

UNLOCK

~~//
\~~
,,/

V4 TURN

REAR DOOR

11111111111 111I1I111I11r 1111111
11111111111 1111111111111 1111111
11I111t111l HIIIIIIIIIII

11111111111 1111111111111
"""11111
11111111111 1111111111111
11111111111
11111111111 1111111111111
11111111111
11111111111 1IlIlltlljjil 11111111111

GROUND WIRE
(G REEN/YELLOW)

11111111111 1111111111111 11111111111
11111/11111:1 11111111111
1111:111111

SWING OPEN
LOOSEN BEFORE
REMOVING SIDE
PANEL. TIGHTEN
AFTER SIDE PANEL
IS INSTALLED.
CS·2439

Figure 2-7

computer Cabinet Ground Connection

2-12

1111111111 1111111111111 llilllllill
1111111111 1111111111111 IllillllIlI
1111111111 1111111111111 11111111111
1111111111 1111111111111 11111111111
11111111111 III1IHII,d, 11111111111
1111111111 1111111111111 11111111111

-.) II 11111111111:1 11111111111
1111111111 1111111111111 1111:111111
1111111111 1111111111111 11111111111
1111111111 1111111111111 111111111111111111 1111111111111 111111111,
11111111111 1111111111111

CS-2441

Figure 2-8

Removing Side Panel

position the side panel against the TS05 cabinet such that
the slots align with the pins. (Refer to Figure 2-9.)
Hold the side panel a few inche s above its mounted
position until it is even with the front and rear of the
cabinet. Slide the panel straight down such that the four
pins engage the four slots.

Reinstall and tighten the bracket located on the TS05
cabinet at the rear bottom right side.
This was one of
the brackets removed in step 3.

2-13

~=-~.-

- :, , ,

CS-2442

Figure 2-9

Mounting the Side Panel
2-14

2.3.3 Connecting the Cabinets
The two cabinets must be connected together both mechanically and
electrically. The mechanical connection is made as follows:
1.

Roll the TS05 cabinet, with side panel attached, next to
the CPU cabinet left side~ Place the TS05 cabinet 1 inch
forward of the CPU cabinet such that the pins in the CPU
cabinet align with the cutouts in the trim panel.
To obtain this alignment, adjust the TS05 leveling feet until
the top of the TS05 cabinet is level with the top of the
CPU cabinet.

Push the TS05 cabinet sideways so that it is against the
computer cabinet.
Push the TS05 cabinet backwards until
it is even with the CPU cabinet. Check that all the pins
are engaged properly into the tr im panel.
(Ref er to
Figure 2-10.)

Reinstall the second locking bracket that was removed in
Section 2.3.2, step 3.
Do not tighten it.
This bracket
is located on the CPU cabinet bottom rear, right-hand
side.
(Ref er to Figure 2-11.)

Loosen, but DO NOT REMOVE, the TS05 locking bracket that
holds the rear door bottom pivot pin.
This is easier if
you partially remove the TS05 rear door by pushing down on
the top pivot pin and rai sing the rear door out of the
bottom pivot hole.

Install the rear intercab bracket as shown in Figure 2-11.
Tighten the four screws, ensuring all brackets are fully
down.
Reinstall the TS05 rear door if it was removed in
step 4.

Remove the bottom trim panels located on the CPU and TS~5
cabinets.
Typically, thi s panel is held in place by two
phillips head screws.

Remove the four center-most bolts and two center-most trim
panel brackets from the cabinetry.

Refer to Figure 2-11 and install the front intercab bracket. Reinstall the two trim panel brackets and tighten the
four bolts, and then reinstall both bottom trim panels.

Recheck the cabinetry leveling.
Adjust the leveling feet
of both cabinets, if necessary, to ensure that the system
is properly leveled and all leveling feet are properly
supporting the system.

2-15

BACK
TOP
VIEW

COMPUTER
CABINET

TAPE
TRANSPORT
CABINET

FRONT

... ---==

TRIM PANEL
SCREW

TRIM PANEL
SCREW
CS·2437

Figure 2-10

Cabinet Alignment
2-16

LOCKING
BRACKET

//~L

""-1

1....::;:
TRIM PANEL
BRACKET

FRONT INTERCAB
BRACKET
(PART NUMBER

7422224)
LOCKING
BRACKET

CS-2440

Figure 2-11

Cabinet Interconnection Hardware
2-17

2.3.4 Removing Shipping Foam
The tape transport is shipped with foam cushions protecting the
takeup hub and blower motor.
These cushions must be removed bef ore the uni t i s powered up.
Thi s requi re s opening the tape
transport to the operator maintenance acce ss po si tion to remove
the foam from around the takeup hub, and opening it to the service
access position to remove two other pieces of foam.
2.3.4.1

Removing the Top Foam Pieces

Raise the top of the cabinet by grasping the handle on the
top cover and lifting.
When the top cover is raised far
enough, the support arm latches to keep the cover up.
(Refer to Figure 2-12.)

Raise the top cover of the tape transport unit by reaching
in through the front door and pushing upward on the front
of the top cover.
Prop the cover up using the nylon support that hangs from the left side of the cover.
(Refer
to Figure 2-13.)

Refer to Figure 2-14. Gently move the tachometer assembly
away from the takeup hub. Remove the foam cushion. Carefully place the tachometer assembly back on the takeup
hub.

Inspect and ensure that the tape path area is free of any
foreign matter.
With the cover still in the operator
maintenance access position, proceed to Section 2.3.4.2.

2.3.4.2

Removing the Bottom Foam Pieces

Loo sen the two spr ing-loaded captive screws, located on
each side (as viewed from the top of the TS05 tape transport unit), that secure the TS05 unit to the top rail assembly.
(See Figure 2-15.)

Lower the top cover of the tape transport unit.

With both hands, grasp the lower front of the TS05 unit
and lift the entire assembly to its maximum upright position.
(Thi s engage s the locking mechani sm automatically.)
WARNING
Keep hands clear of the corners of the
tape unit while lifting. This is important to avoid brushing the mounting
rails with your hands while lifting the
unit.

2-18

==~
...

""""------

c:2

CS-2438

Figure 2-12

Cabinet Top Cover

2-19

TAPE TRANSPORT
TOP COVER SUPPORT
CABINET TOP
COVER SUPPORT

-'-

- =1:-

CS-2444

Figure 2-13

Tape Transport Top Cover

2-20

TAKEUP HUB
TACHOMETER
TAPE CLEANER
TAPE ROLLER GUIDE
COMPLIANCE ARM
ROLLER GUIDE

TAPE-INPATH
SENSOR
TAPE ROLLER GUIDE

REEL HUB PAD

SUPPLY REEL
CS-2466

Figure 2-14

Tachometer and Takeup Hub

2-21

CAPTIVE
SCREW (2)

CONTROL
MODULE
UP

FORMATTER
CONTROL
MODULEr-----~~~~~~~----~--~~~~~
DOWN

FOAM BLOCK

INSERT SAFETY
PIN HERE
FOAM
SHEET

Figure 2-15

Service Access position
2-22

CS-2445

Carefully lower the TS05 unit approximately 2.5 centimeters (1.0 inch).
(This will activate the locking mechanism automatically.)
WARNING
To eliminate the possibility of the tape
uni t dropping due to a failure in the
locking mechani sm, insert the supplied
safety pin into the hole provided [2.5
centimeters
(1.0
inch)]
above the
locking mechani sm on the top plate
supporting sl ide.
Route the safety pin
behind the supporting sl ide and acro ss
in front, and install it from left to
right.

Release the drive/formatter module by pulling down on the
two Ny-Lok fasteners that secure it to the bottom of the
top plate assembly.
When the Ny-Lok fasteners are released, carefully lower the drive/formatter module as far
as it will go.

Remove the sheet and block of foam from the unit.

Place the TS05 unit back to the operating position by rever sing steps 1 through 5.

Close the top cover of the tape unit and the top cover of
the cabinet.
NOTE
To release the cabinet top cover support
arm, it is necessary to raise the top
cover slightly and move the top of the
arm forward.

2.3.5 Connecting Line Power
Before connecting the line power, perform the following checks:
1.

Power swi tch on the front panel of the tape transport is
in the 0 (OFF) position.

Power controller
system.

Power controller circuit breaker switches are in the OFF
position.

Power controller
position.

voltage

rating

LOCAL/REMOTE

is correct

switch

for

the

your

LOCAL

With the switches in these positions, unwind the power cable and
plug it into the receptacle.

2-23

2.4 TAPE TRANSPORT CHECKOUT
The tape transport is tested by itself before being cabled to the
bus interface/controller module.
Thi s standalone testing is performed with the line power controlled locally at the cabinet power
controller.
After standalone operation has been verified, operation with the computer system is tested.
At that point, the tape
transport cabinet power is placed under the control of computer
cabinet power controller by connecting the remote control cable.
For the tests in this section, however, the remote control cable
remains unconnected.
2.4.1

Power Up Test

Switch the circuit breaker switches on the cabinet power
to the ON position.
Observe that the power controller
pilot lamp lights. Close the cabinet rear door.

On the tape transport front panel (Figure 2-16), press the
power switch to the 1 (ON) position. Observe that all indicators light for approximately 2 seconds.

Observe that after 2 seconds all the indicators extinguish, and then the UNLOAD indicator lights.

If these indications have occurred, the tape transport unit has
successfully completed the internal verification checks that it
performs automatically at power up.
If. the indications were different, there is a problem.
Refer to the TSV05 Pocket Service
Guide or call your local Digital representative.

mamaamo TS05

000

00000

LOAD UNLOAD ON LINE WRITE
REWIND
TEST

ENTER

o[[J}
POWER
CS·2429

Figure 2-16

Front Panel Controls and Indicators

2-24

2.4.2 Tape Loading Test
This test verifies the ability of the TSV~5 subsystem to automatically load a tape.
It requires a tape that is blank except for
the beginning-of-tape (BOT) and end-of-tape (EOT) markers.
Refer
to Figure 2-17 and proceed as follows:
1.

Ensure that the tape is wound completely onto the reel and
that the end has been properly crimped.

Open the front panel door by gently pressing down on the
top center area of the door.

Hold the tape with the file-protect ring side down, and
insert it into the transport unit, centering it on the
hub.

Close the door.
CAUTION
Both the tape transport top cover and
the front panel door are locked when a
tape is loaded.
Any attempt to force
open either the cover or the door before
the tape is unloaded will result in
mechanical damage to the locking mechan-

ism.
5.

Press the LOAD switch. This locks the cover and the door
and begins the loading sequence.

Observe the LOAD indicator.
It blinks while the tape is
being loaded.
After a maximum of 135 seconds, it stops
blinking and remains lit.
This indicates that the tape
loading sequence is complete.
If the LOAD indicator does not stop blinking, or if the
other indicators begin to blink, there is a problem.
Unload the tape, check for a proper crimp, and retry the
test.
If the tape does not load, refer to the TSV~5
Pocket Service Guide or to the manual loading instructions
in Appendix B.

2-25

Figure 2-17

.
Tape
Insertlng

2-26

2.4.3 Tape Movement Test
Thi s test exerci ses the tape drive in both forward
directions and at both high and low speeds.

and

rever se

panel

control

NOTE
If you make an error and enter an illegal test sequence, or if you stop during
the sequence and permit more than 2 seconds to pass before pressing the next
swi tch in the sequence, the sy stem
aborts the test instruction and you must
start the sequence from the beginning.
An erroneous or aborted test instruction
results in an expanding pattern of
blinking.
1.

Start the test by pressing the
switches in the following sequence:
a.

TEST

ENTER

UNLOAD

ENTER

front

The tape should begin to move after step e.

Observe the indicators.
If, over a period of 2 minutes,
they change their blinking value substantially, there is a
problem.
If the blinking remains about the same, the test
is progressing successfully.

After 2 minutes, terminate the test by pressing the TEST
key. This causes the tape to rewind (which may take several minutes) and the LOAD indicator to light.

If problem s
Guide.

are

encountered,

ref er

2-27

the

TSV05 Pocket Service

2.4.4 Tape Unloading Test
This test verifies the ability of the tape unit to unload the tape
automatically.
1.

Press the UNLOAD switch.

Observe the UNLOAD indicator.
It blinks to indicate that
the tape is being unloaded. When the unloading process is
complete, the UNLOAD indicator lights continuously, and
the front panel door and top cover are unlocked.
Thi s
should take a maximum of 15 seconds.

Open the front panel door and lift the tape reel out of
the tape transport.

Close the door.

Press the tape transport power switch to the 0 (OFF) position.

Switch the circuit breaker switches on the cabinet power
controller to the OFF position.

2.5 BUS INTERFACE/CONTROLLER MODULE INSTALLATION
The M7196 bus interface/controller module plug s into a quad slot
in the LSI-II backplane.
It connects to the LSI-II bus on the A
and B sets of edge connectors (module fingers).
It is shipped
with the DIP switches set for an interrupt vector of 224 and for
addresses of 772520 and 772522.
If your system already uses any
of these addresses, the M7196 module must be switched to other
addresses.
Refer to Appendix A for information on switching the
DIP switchpacks on the M7l96 module.
Refer to the Microcomputers
and Memories Handbook or your system configurator for guidance in
selecting new addresses.
For guidance in choo sing the be st backplane slot in which to
install the M7l96 module, refer to your system documentation or to
the Microcomputers and Memories Handbook.
Install the M7196 module as follows:
1.

Test the computer system to verify that it is functioning
properly.

Power down the computer system.

Remove the cover to gain access to the backplane.
(Which
panel must be removed depends on which system you have.
Earlier systems accept modules in the front, while in more
recent models the modules are inserted in the back.
Refer to your system documentation.)

Insert the module into the LSI-II backplane. Do not fully
seat the module until the cables have been installed.
2-28

2.6 CABLE INSTALLATION
Cable installation involves connecting the M7l96 module to the
tape transport uni t and connecting the tape transport cabinet
power controller to the computer cabinet power controller.
2.6.1 M7196 Module and Tape Transport Interconnection
Each of the two flat interconnection cables has a large connector
on one end and a small connector on the other end.
The large
connectors go to the tape transport unit and the small connectors
to the M7l96 module. Refer to Figure 2-18 and proceed as follows:
1.

Take a cable and position it so that pin 1 of the smaller,
"low profile" connector lines up with pin I of connector
Jl on the M7l96 module.
Pin I on the cable connector is
indicated by a red stripe on the cable.

Gently push the cable connector into the JI module connector until it is seated.

Route the cable to the rear of the cabinet. Cable routing
depend s on the model and conf iguration of the computer
system, however, try to avoid blocking ventilation or running the cable where it may get caught on other equipment
when a chassis is pulled out. Refer to drawing UA-TSV05-B
for typical cable routing.

Pass the cable through the open side of the computer cabinet and into the tape transport cabinet.
Do not route
the cables outside the cabinetry.

Refer to Figure 2-19.
Line up pin 1 of the cable connector with pin I of connector PIon the tape transport unit.
There are two sets of connectors on the back of the tape
transport unit.
The TSV05 subsystem uses the left-hand
set of connectors.

Gently pre ss the cable connector onto the PI edge connector in the back of the tape transport cabinet.

Repeat this procedure to cable J2 of the M7196 module to
P2 of the tape transport unit.
Ensure that pin 1 of J2
connects to pin 1 of P2.

After both interconnection
fully seat the module.

2-29

cables have

been

installed,

M7196 MODULE

PIN 1

....-C~~J_1-:....... 0

PIN 1

LOW PROFILE
CONNECTOR
RED STRIPE

CS-2447

Figure 2-18

Cabling the M7196 Module

TAPE TRANSPORT UNIT

..>
'"

1 50
I

1
I

PIN 1

~ RED STRIPE

Figure 2-19

Cabling the Tape Transport
2-30

2.6.2 Power Controller Interconnection
The power controllers in the two cabinets are to be interconnected
by a remote control cable.
Thi s enable s the computer cabinet
power to switch on the tape transport cabinet power automatically
whenever the computer is powered up.
The remote control cable, part number 7008288-8F, has a three-pin
connector on each end. The cable connectors are the same, and they
are keyed to plug in only one way.
Refer to Figure 2-20 and install the remote control cable as follows:
1.

In the computer cabinet, pI ug one end of the cable into
the power controller connector labeled DEC POWER CONTROL
BUS.

Route the remote control cable through the open side of
the computer cabinet and into the tape transport cabinet.
Do not route the cable outside the cabinetry.

In the tape transport cabinet, plug the cable into the
power controller connector labeled DEC POWER CONTROL BUS.

Place the LOCAL/REMOTE switch in the REMOTE position.

Switch the circuit breaker switches to the ON position.

The tape transport cabinet power is now fully interconnected with
the computer cabinet.

COMPUTER CABINET

•

•
•
•
. •
•
•

TAPE TRANSPORT
CABINET

•

•
•
•
•
•

Figure 2-20

Remote Power Control Connections

2-31

CS·2434

2.7 TSV05 SUBSYSTEM CHECKOUT
The TSV05 subsystem is tested by checking the M7196 LED indicators
and voltage supply, and by running the diagnostic programs listed
in Table 2-2.
These programs are available on the XXDP+ diagnostic software package that is shipped with the computer system.
If
your system is an earlier model and has the XXDP package instead
of the XXDP+, contact your local Digital representative for ordering information.
2.7.1

Power Up Checks

Set the power switch on the tape transport unit to the ON
position.

Swi tch on the computer system power and observe that the
tape unit powers up with the system.

After a few seconds, all the tape unit indicators should
be extinguished except for the the UNLOAD indicator.

Verify that the +5 V power to the M7196 module is within
specification.
Typically, the additional load of the
M7196 module lower s the power supply vol tage sl ightly.
Adjust if nece ssary.

On the M7196 module, verify that the center LED (D2) is
blinking.
This indicates that the M7196 module self-test
diagno stic s are running.
If other indications occur,
there is a problem.
Refer to the TSV05 Pocket Service
Guide or contact your local Digital representative.

Replace the access panel on the computer and close the
rear doors of the cabinets.
Table 2-2

TSV05 Subsystem Diagnostics

Program Title

File Name

Logic Test

CVTSAA

Advanced Logic Test

CVTSBA

Transport Te st

CVTSCA

Advanced Transport Te st

CVTSDA

Data Reliability Test

CVTSEA

DEC-XII

XTSAA0

2-32

2.7.2

System Setup

To prevent erroneous error indications, ensure the tape
transport is clean and the blank tape is of known good
quality.

Load the blank tape into the tape transport by:
a.

Opening the front panel access door.

In serting the tape reel, wi th the file-protect
side down, and centering it on the hub.

Closing the door.

pressing the LOAD switch.

Waiting for the LOAD indicator
stay on continuously.

Pressing the ON-LINE switch.

ring

stop blinking and

Load the computer system diagnostic diskpack or floppy.

Before running the tape subsystem diagnostics, run the
system exerciser or diagnostics to verify that the computer is operating properly.
For instructions on running
the computer system tests, refer to the documentation for
the system.
NOTE
The logic test and the advanced logic
test (CVTSAA and CVTSBA) do not require
a tape to be loaded in order to run.
The other diagnostics, however, require
the tape to be loaded and the tape subsystem to be ON-LINE.

2.7.3 TSV85 Logic Test
This program tests the logic on the M7196 bus interface/controller
module. It checks the microprocessor, RAM,and various registers.
It verifies that the computer can move data out to the module and
receive status in from the module.
After you have booted the
XXDP+ disk (DL, DX, or DY) and answered the questions. about the
date, the processor, and the power line frequency, start the logic
test as follows (operator responses are underlined):
.R VTSA?? <CR>

2-33

The system responds with a display similar to the following:
DIAG. RUN-TIME SERVICES
CVTSA-A-~

····TSV~5 LOGIC
TSV~5

DIAGNOSTIC····

UNIT IS
DR>

At this point, type in the following commands:
DR> START/FLAG:PNT:HOE <CR>
This instructs the program to start the test, display the test
number as each of its 11 tests are executed, and halt it if an
error is detected. The computer now asks:
CHANGE HW (L) ?
Type in a

nyu

for yes:

CHANGE HW (L)? Y <CR>
The computer then asks:

t UNITS (D) ?
Type in a n1 n to indicate that there is one tape unit:

t UNITS (D) ? 1 <CR>
The computer than displays the device address, the interrupt vector, and the interrupt priority.
If you have left the M7l96
module in the configuration in which it was shipped, respond to
these queries by typing a carriage return:
UNIT ~
DEVICE ADDRESS (TSBA/TSDB) (0)
INTERRUPT VECTOR (0) 224? <CR>

l7252~?

<CR>

If, on the other hand, you have changed the DIP swi tchpack setting s on the M7l96 module, then you must type in the parameter s
you selected.
The computer then ask s if you wi sh to change the
meter s:

sof tware para-

CHANGE SW (L) ?
For the subsystem checkout, the answer to thi s question is no:
CHANGE SW eL) ? N <CR>

2-34

After you have responded to these questions, the program starts
te sting the sub system. The program run s continuously, repeating
itself until it detects an error or until you halt it. If the
program hal ts because of an error, refer to the CVTSAA TSVf35
MAGTAPE Diagnostic User's Document for a detailed description of
the tests. For assistance, contact your local Digital Field
Service office.
After the program has made one pass through all the tests, _halt it
by pre ssing CONTROL C. Thi s pa sse s control of the sy stem back to
the diagnostic supervisor program. Then type "EXIT" to get back to
the system monitor:

"c
DR> EXIT <CR>
2.7.4 Advanced Logic Test
This program verifies that the M7196 module can get status and
write characteristics from the computer memory, and that it can
deposit message packets in the computer memory.
It tests error
detection circuits and verifies that the computer can ititialize
and write into the controller RAM memory.
It checks the internal
timers, buffers, and status and control logic.
Also, it verifies
that the controller can move signals to and from the cables that
connect it to the tape transport unit.
Load thi s program as follows:
.R VTSB?? <CR>
After the program title is displayed and the diagnostic supervisor
returns the DR prompt, enter the command line:
DR> START/FLAG:PNT:HOE:UAM <CR>
The program responds by asking the same questions about hardware
and software parameters as were asked by the logic test.
Type in
the same answers.
After the last question is answered, the program starts running its tests (this one has 12 tests, with the
la st 3 not executed).
It run s continuou sly unti I there is an
error or until you halt it.
After one pass, halt the program by
typing CONTROL C, and type "EXIT" to return to the system moni tor:

"'c
DR> EXIT <CR>
2.7.5 Tape Transport Test
Thi s program ver if ie s correct tape motion command decoding.
It
checks the basic operation of the rewind positioning command, the
wr i te data command, and the read forward and read rever se commands.
It verifies that the system can space over records forward
and in reverse direction, and that it can reread records.
The

2-35

ability of the subsystem to respond to error conditions is also
te sted.
The program check s the command s f or retrying to wr i te
data and tape marks.
It also tests the skipping of tape marks in
forward and reverse directions.
Load the program as follows:
.R VTSC?? <CR)
After the system displays the program title, enter the same command line and answers to the parameter questions as for the previous program (described in Section 2.7.4).
After one successful
pass of the eight tests in this program, halt the program and exit
to the system monitor.
2.7.6 Advanced Tape Transport Test
This program verifies the funtioning of the No-Op, Initialize, and
Erase commands.
It checks that errors are indicated when no data
is found on the tape and it tests the data parity checking circuitry in both the controller and the tape transport electronics.
It checks for the proper handling of the EOT status and tests the
record buffering functions.
It also checks that records and gaps
written on the tape are the correct length.
Load the program as follows:
.R VTSD?? <CR)
After the title is displayed, enter the commands:
DR) START/FLAG:PNT:HOE <CR)
The program starts and runs its nine tests.
After one successful
pass, halt the program and exit to the system monitor.
2.7.7 Data Reliability Test
This program exercises and verifies the correct completion of all
tape transport functions.
It executes read and write commands a
random number of times, with records of random length and data,
for the entire tape.
Load the program by typing:
.R VTSE?? <CR)
and then, after the title is displayed, enter:
DR) START/FLAG:PNT:HOE <CR)

2-36

NOTE
Magtape media typically will have several flaws per reel that will cause this
diagnostic to indicate write errors or
write retries due to bad tape spots.
These types of errors do not indicate a
problem with the subsystem.
The program then asks:
SELECT DRIVE 0-1 (0)?
Answer by typing 0 and a carriage return:
• 0<CR)
2.7.8 Additional Testing
The tests described in the preceding sections provide a high confidence level that the TSV05 subsystem is functioning correctly.
More exhaustive checks are available by allowing the diagno stic
programs to run for more than one pass.
The second pass of the
program is more comprehensive than the first pass. All iterations
after the first pass are the same, however, they are substantially
longer than the first one.
Running tests that cause tape motion
for extended per iod s wi 11 requi re transport cleaning to prevent
erronous error reports.
The logic type tape motion tests, when
run continuously, can cause high tape wear to occur in the first
few feet of tape.
In these cases, errors due to faulty or worn
tape do not indicate a failure.
Another te st that may be run is the DEC/XII runtime system exerciser. This test exercises the entire system to verify that there
are no spurious interactions between various subsystems and components. There is an exerciser program module for each major system component, and the se are 1 inked together to create a system
exerciser that is tailored to your system. The DEC/XII module for
the TSV05 subsystem is XTSAA0. Although this exerciser can be run
by itself, its full value is not realized unless it is linked to
and run with the system exerciser. For information about building
a system exerci ser to include the TSV05 subsystem, refer to
DEC/XII User's Manual, AC-8240Z-MC.

2-37

CHAPTER 3
OPERATION
System operations can be divided into various levels or categories
of activities. At the most basic level are activities such as
powering up and maintaining the system, loading the tape, and
performing verification (confidence) checks on system operation. A
second category of operating
activities
involves system
generation.
When the TSV05 is added to the computer system, the
software operating system must be modified to include the handler
for the tape subsystem. System generation requires building a new
copy of the operating system. A third category of operating
procedures covers the use of the software utility programs for
operations such as copying data from one drive to another,
updating files and comparing one file to another. The most complex
level of user activity involves designing programs that manipulate
the internal workings of the tape subsystem. This chapter devotes
sections to these categories of activities.
3.1

ROUTINE OPERATING PROCEDURES

3.1.1 Power Up
On the tape transport front panel, press the power swi tch to its
ON ("1") posi tion. The ind icators all 1 ight for approx imately two
seconds and then go out. Then the UNLOAD indicator lights and
stays on. At this point, the tape unit is ready to be loaded.
3.1.2 Loading Tape
The TSV05 loads tape automatically unless the tape is in very bad
condition. If you must recover data from a tape that is crumpled
or creased on the end, it may be necesssary to load the tape
manually. Refer to Appendix B for instructions on manual loading.
For best load reliability the beginning of tape leader should be
crimped using DEC part number 47-00038 or equivalent. However, do
not repeatedly crimp or remove excessive tape leader as this would
cause the BOT marker to be too close to the beginning of tape.
Tape crimper
part number 47-00038 can be ordered from the
Accessories and Supplies Group, as outlined in Section 3.1.8.2.1.
For normal tape loading, proceed as follows:
1.

Ensure that the tape is wound completely onto the reel,
and the file protect ring is fully seated, if present on
the reel.
NOTE
Most tapes have some form of stick on TAB or
rubber block
to
prevent
the
tape
from
unwinding during shipment or storage.
These
items must be removed so that the tape leader
is free to unwind during the auto loading
sequence. High levels of static electrici ty
should also be avoided since this could
prevent the tape leader from unwinding.
3-1

Open the front door panel by gentl y pressing down on the
top center of the door. (See Figure 3-1).

Ho ld the tape reel wi th the file-protect ring s ide down.
Insert the reel into the transport uni t, center ing it on
the hub.

Close the door.
CAUTION
Both the tape transport top cover and front
panel door are locked when a tape is loaded.
Any attempt to force open either the cover or
the door before the tape is unloaded will
result in mechanical damage to the locking
mechanism.

Press the LOAD/REWIND switch. This locks the cover and the
door, and begins the loading sequence.

The LOAD indicator blinks while the tape is being loaded.
Typically after 30 seconds, the LOAD indicator stops
blinking and remains lighted. This indicates that the tape
is loaded and the TSV05 subsystem is ready to use.

Press the ON-LINE switch to place the tape subsystem under
the control of the host computer. The ON-LINE indicator
lights when the TSV05 system is on-line.
The ON-LINE
switch can be pressed immediately after the load switch.

3.1.3 Rewinding Tape
It is not necessary to rewind the tape during normal operation, as
all tape movement is under program control. Under unusual
circumstances, however, such as a host system failure or a loss of
communications wi th an upl ine host, you may wish to rewind the
tape under local control. This is done as follows:
1.

If the tape subsystem is on-line (indicated by the ON-LINE
indicator being on), press the ON-LINE switch once to
switch the subsystem off-line.

Press the REWIND switch. The LOAD/REWIND indicator blinks
while the tape is being rewound, and then remains on
continuousl y when the Beg inning-of-Tape (BOT) marker is
reached.

3-2

Figure 3-1

Opening the Front Door Panel
3-3

3.1.4 Unloading Tape
To unload a tape from the transport, proceed as follows:
1.

If a tape subsystem is on-line (indicated by the ON-LINE
indicator being on), press the ON-LINE swi tch once to
switch the subsystem off-line.

Press the UNLOAD switch. The UNLOAD indicator blinks while
the tape is being unloaded. When the unloading process is
complete, the UNLOAD indicator 1 ights continuously, and
the front panel and top cover are unlocked. A typical
unload sequence from BOT takes 15 seconds.

Open the front panel door (Figure 3-1) and lift the tape
reel out of the tape transport.

Close the front panel door.

3.1.5 Restarting the Tape Subsystem
The TSV~S ceases operation in the event of a power failure or if
it detects a hard operational error.
3.1.5.1 Power Failure -- When line power is interrupted, the
transport automatically shuts down and tape motion stops without
any physical damage to the tape. When line power is restored, the
TSV~S powers up in the unload mode. You must press either the LOAD
or the UNLOAD swi tch. I f you press the LOAD swi tch, the
LOAD/REWIND indicator blinks while the tape is being reloaded to
the BOT marker. When the BOT marker is reached, the LOAD/REWIND
indicator remains on continuously, and the ON-LINE switch can be
pressed to return the tape subsystem to computer control.
If you press the UNLOAD switch, the UNLOAD indicator blinks while
unloading is in progress. When the UNLOAD indicator remains lit
continuously, you can open the door and remove the tape.
3.1.5.2
Hard Errors
When the TSV~S encounters an error
condi tion from which it cannot automatically recover, it stops
tape movement and displays a series of blinks on the indicators.
If this happens, switch the TSV~S power off, switch it back on
again, and then press the UNLOAD switch. After the UNLOAD
indicator stops blinking, remove the tape. At this point, it may
be necessary to ei ther call DEC Field Service or refer to the
TSV~S Magtape Subsystem Pocket Service Guide.

3-4

3.1.6 Operator Troubleshooting
It may be possible to avoid a service call by making a few checks
before reporting a condition as a problem. If the TSV05 is located
in an area where several people may be using the tapes and
equipment for different purposes, check the following:
1.

If the transport does not power up, ensure that the power
controller in the TSV05 has:
a.
b.
c.
d.

Circuit breaker switches ON.
REMOTE ON/OFF/LOCAL ON switch switched to REMOTE ON.
Remote control cable connected to DEC POWER connector.
Power controller pilot lamp lit.

If a tape does not load properly, ensure that:
a.
b.
c.
d.

The tape is in reasonably good condition (if not,
refer to manual loading procedure in Appendix B).
Tape has a BOT marker, located per ANSI STDX3.40-l973,
16+ or -2 feet.
Front panel door is completely closed.
The instructions on the loading label are followed.

If the subsystem is unable to write a file, ensure that
the write enable ring is installed in the tape reel.

If interm i ttent problems occur involv ing the read/wr i te
functions, clean the tape path (see Section 3.1.8 Customer
Care) •

If it is determined that the equipment is malfunctioning, record
the symptoms of the malfunction to aid maintenance personnel in
troubleshooting the system.
3.1.7 Confidence Checks
There are three "confidence levels" that can be established by
testing. The basic level of confidence is established simply by
powering up the system. Both the tape transport and the
controller/interface module perform internal self-test programs
each time power is applied. Therefore, the ability of the
subsystem to power up and load tape establishes that it is
probably in good working order.
A second, higher level of conf idence can be establ ished by using
the console terminal of the host computer sytem to check the
status of the TSV05 subsystem. This is performed by using the
appropriate operating system command to check device status (e.g.,
on-line or off-line) or to call for a directory listing from a
tape mounted in the TSV05 system. If the TSV05 powers up and loads
tape properly, and if the operating system gets directory or
status information from the TSV05, then the probability that the
system is working correctly is very high.

3-5

The highest level of confidence in the TSV"5 is established by
running the Data Reliability Diagnostic Program (CVTSEA in the
XXDP diagnostic package) and the DEC/XII exerciser).
3.1.8 Customer Care
The person in charge of the TSV"5
responsible for the following tasks:

subsystem

normally

Obtaining operating supplies, including magnetic tape and
cleaning supplies.

Maintaining
the
required
consistently and accurately.

Making the documentation available
in a
convenient to the system users and maintainers.

location

Ensuring that the exterior of
surrounding area are kept clean.

and

Ensuring that ac plugs are securely plugged in each time
the equipment is used.

Ensuring that preventive maintainance activities are
performed at the suggested periods, or more often· if usage
and environment warrant.

logs

and

the

report

system

files

the

3.1.8.1 Care of Magnetic Tape -- The person responsible for the
TSV"5 should ensure that system users exercise due care in the
handling of magnetic tape. Basic rules of tape care are as
follows:
1.

Do not expose magnetic tape to excessive heat or dust.
Most tape read errors are caused by dust or dirt on the
read head. Keeping the tape clean is imperative.

Always store tape reels inside containers when the tape is
not in use. Keep empty containers tightly closed to guard
against dust and dirt.

Never
touch
the
portion
of
tape
b.etween
the
Beginning-of-Tape (BOT) and End-of-Tape (EOT) markers; oil
from fingers attracts dust and dirt.

Never use a contaminated reel of tape; this spreads dirt
to the clean tape reels and could adversely affect tape
transport reliability.

Always handle tape reels by the hub hole; squeezing the
reel flanges leads to tape edge damage when winding or
unwinding tapes.

3-6

not smoke near the tape transport or storage area;
tobacco smoke and ash are especially damaging to tapes.

Do not place magnetic tape near
devices that produce paper dust.

Do not place magnetic tape on top of the tape transport or
in any other location where it may be affected by hot air.

Do not store magnetic tape near electric motors.

line

printers or other

3.1.8.2 Preventive Maintenance -- The tape transport is a highly
reliable precision instrument that provides years of trouble-free
performance when properly maintained. For optimum performance and
reliability, a planned and scheduled program of routine inspection
and maintenance is essential. preventive maintenance consists of
cleaning only a few items, but the cleanliness of these items is
essential to proper tape transport operation. The frequency of
maintenance operations will vary with the environment and the
degree to which the transport is used. Therefore, a rigid schedule
for all machines is difficul t to define. Cleaning after every
eight hours of operation is recommended for uni ts in constant
operation in ord inary env ironments. Th i s
sched ul e
sho u1d
be
modified if experience shows other periods are more sui table.
Typically, new tapes or tapes near the end of their life will
prod uce the most oxide bui ldup wi thin the transport and require
more frequent cleaning. Table 3-1 shows the recommended frequency
of maintenance activities. The replacement of filters, reel motors
and head wear check is to be performed by DEC Field Service
personnel. The other activities are to be performed by the
customer.
Before performing any cleaning operation, remove the supply reel
and store it properly. When cleaning, be gentle but thorough.

3-7

Table 3-1

Suggested Preventive Maintenance

Maintenance Operation

Frequency

I
Quantity to Maintainl

I
I
I
I
I
I
I

Clean Head, Guides,
Roller Guides, Tape
Path

Once per shift

Clean Tape Cleaner

Once per shift

Clean Reel-Hub Pads

Once per shift

Clean Tachometer
Roller

I
I

Once per week

Check Head Wea r

2,500 Hours

Replace Reel Motors

10,000 Hours

Check Air Filter

Every 3 Months

I
I
I

I
I
I
I
I
I

3.1.8.2.1 Magnetic Tape Transport Cleaning Kit -- A magnetic tape
transport cleaning kit (TUC02, Part Number 2200012) has been
carefully assembled to provide materials that will not harm tape
equipment or leave any residue to interfere with data reliability.
The hints contained in the following paragraphs will help you
obtain the very best results from the kit.
WARNING
When using DECmagtape cleaning fluid, avoid
excessive skin contact and contact wi th the eyes.
Do not swallow it. Use the cleaning fluid only in a
well ventilated area.
When cleaning tape equipment, never dip a dirty cleaning swab or
wipe into the can.
Always keep the can of fluid tightly closed when not in use; the
fluid evaporates rapidly when exposed to air.
CAUTION
Do not use acetone, lacquer thinner or rubbing
alcohol to clean the tape path and related parts.

3-8

Should you encounter any unusually stubborn dirt deposi t that
resists the cleaner, try a mild soap and water solution to
dislodge it. After using soap, be sure to wash down the affected
area thoroughly with cleaning fluid to remove soapy residue.
If you need more cleaning materials, tape crimper Part Number
47-00038, or other items, forward orders for supplies, accessories
or documentation to:
Digital Equipment Corporation
Accessories and Supplies Group
Cotton Road
Nashua, New Hampshire 03060
Contact your local sales office or call DIGITAL Direct Catalog
Sales toll-free 800-258-1710 from 8:30 a.m. to 5:00 p.m. Eastern
Standard Time
(U.S. customers only). New Hampshire customers
should dial (603) 884-6660. Terms and conditions include net 30
days and F.O.B. DIGITAL plant. Freight charges will be prepaid by
DIGITAL and added to the invoice. Minimum order is $35.00. Minimum
does not apply when full payment is submi tted wi th an order.
Checks and money orders should be made out to Dig i tal Equipment
Corporation.
3.1.8.2.2
Accessing the Tape Path Area -- Refer to Figure 3-2.
Raise the cabinet top cover by grasping the handle on the top
cover and lifting. When the top cover is raised far enough, the
support arm latches to keep the cover up.
Ra ise the top cover of the tape transport uni t by reaching in
through the front panel door and pressing upward at the front area
of the top cover.
3.1.8.2.3
Cleaning the Tape Path and Related Parts -- Refer to
Figure 3-3. Using foam-tipped swabs soaked in cleaning fluid,
gently wipe the following parts:
1.

Read/Write head

Tachometer roller

3-9

CABINET TOP
COVER SUPPORT

anml

IE
:;;;;;-----

CS"2444

Figure 3-2

Accessing the Tape Path Area
3-10

TAKEUP HUB
TACHOMETER
TAPE CLEANER
TAPE ROLLER GUIDE
COMPLIANCE ARM
ROLLER GUIDE

TAPE-INPATH
SENSOR
TAPE ROLLER GUIDE

REEL HUB PAD

SUPPLY REEL
CS-2466

Figure 3-3

Tape Path and Related Parts
3-11

Tape Cleaner.
CAUTION
Exercise care to avoid damage to the sharp
edges of the blades on the tape cleaner.

Roller guides (quantity of five).
NOTE
When cleaning the roller guides, ~he cleaning
fluid should contact only the tape-bearing
surfaces. This prevents degreasing the roller
guide bearing.

Supply hub pawls (quantity of three).

Tape path. (use the supplied texwipes).

3.1.8.2.4 Cleaning the Housing -- Clean the front panel door and
the control panel with Miller Stephenson Chemical Company MS-260,
Windex, or an equivalent commerc ial grade plastic cleaner and a
clean, lint-free wipe material.
3.2 TSV95 OPERATIONS
The TSV05 is compatible with TSll/TS04 software in all operating
system level functions. Generally, any utili ty that supports a
magtape subsystem (device code MS) supports the TSV05. For
detailed procedures and examples, refer to the utili ties manual
for your operating system.
Operation of the TSV05 may differ slightly from that of the
TSll/TS04 at the level of user-written application programs. Refer
to Section 3.3. for detailed descriptions of program-accessible
TSV05 functions.
3.3 PROGRAMMING
The TSV05 follows the same programming protocol as the TSll/TS04
subsystem.
The nature of the TS05 transport dictates that some
status bits will be redefined. In addition, the TSV05 has special
features not available in the TSll/TS04 subsystem.

3-12

3.3.1. Overview
The functions listed in Table 3-2 make up the TSV05 Subsystem
Command Set.
These commands uti Ii ze "command packets" stored in
the computer system memory to operate the transport and transfer
data.
Some commands have various sub-commands, termed "modes".
The interface device registers are used to initiate command packet
processing and retrieve basic status.
This section describes
register manipulation and provides an overview of
packet
protocol (the format used to transfer commands and data).
A
detailed description of the commands is provided in Section 3.3.4.
The TSV05 has four device registers which occupy only two LSI-II
Bus word locations:
a Data Buffer (TSDB), a Bus Address Register
(TSBA), a Status Register (TSSR) and an Extended Data Buffer
(TSDBX). The
TSDB
is
an
l8-bit register
that is parallel
loaded from the LSI-II Bus or from the TSV05 controller
(M7l96)
itself. A l6-bit portion of this register is used as a word buffer
register;
it is written into by the CPU to initiate and operate,
and it is written
into
by the
controller
logic
itself to
store data to be transmi tted to LSI-II Bus memory during a DMA
cycle.
The
TSDB
can
be
loaded from
the
LSI-II
Bus
by
three different transfers from the CPU.
Two transfers are for
maintenance purposes (byte transfer, and DATOB at high byte or
low byte), and the third is for the normal (word) operation (DATO)
to initiate an operation. This
register is write-only and is not
cleared at power on, subsystem initialize or bus initialize. This
register can be loaded without the tape transport connected, since
all controller functions reside wi thin the
M7196
interface
module.

3-13

Table 3-2

Command Name

TSV05 Assigned Command Modes

Mode Name/Description

GET STATUS

Get Status (update the Extended Status
registers in the message buffer in memory)

READ

Read Next (Forward)
Read Previous (Reverse)
Reread Previous (Space Reverse,
Read Forward)
Reread Next (Space Forward,
Read Reverse)

WRITE
CHARACTERISTICS

Load Message Buffer Address and Set Device
Characteristics

WRITE

Wri te Data
Write Data Retry (Space Reverse,
Erase, Write Data)

POSITION

Space Records Forward
Space Records Reverse
Skip Tape Marks Forward
Skip Tape Marks Reverse
Rewind

FORMAT

Write Tape Mark
Erase
Write Tape Mark Retry (Space
Reverse, Erase, Write Tape Mark)

CONTROL

Message Buffer Release
Rewind and Unload
Clean Tape (handled as a NO-OP)
Rewind with Immediate Interrupt

INITIALIZE

Controller/Drive Initialize

WRITE SUBSYSTEM
MEMORY

Diagnostic function. Allows test sequences
and data patterns to be entered into the
controller.

Extended function, not part of the TS11/TS04 repertoire.

3-14

Commands are not written to the TSV05 LSI-II Bus registers.
Instead, command pointers, which point to a command packet
somewhere in CPU memory space, are wri tten to the TSDB reg ister.
The command pointer is used in the TSV05 subsystem to retrieve
words in memory called the Command Packet.
The words in the
Command Packet instruct the system as to the function to be
performed.
These words contain any function parameters such as
bus address, byte count, record count, and modifier flags.
The TSBA is an l8-bit register (22-bits when the high byte of the
TSSR
is wr i tten to) that is parallel loaded from the TSDB every
time the TSDB is loaded. TSDB bits 15-2 load into TSBA bits 15-2,
TSDB bi ts 1 and 0 load into TSBA bi ts 17 and 16, and zeros are
loaded
into
TSBA bits
1 and
0
(thereby specifying
a
modulo-4 address). TSBA bits 17 and 16 are displayed in TSSR bits
9 and 8, respectively.
(TSDB can be extended to 22 bits by
firstloading TSDB bits 18-22 into the high byte of TSSR.
The
Extended Features Switch must be ON or else bits 18-22 are
ignored) •
The TSBA reg ister is incremented or decremented by two
for DMA word transfers, or by one for DMA byte transfers. The two
major purposes of the TSBA register are as follows:
1.

The TSBA can be used as a command pointer, pointing to the
"functional device registers" (command and message
buffers). These are located somewhere in LSI-II Bus
address space. The contents loaded into the TSDB when the
TSV05 is the bus slave is considered the command pointer.
In this mode, the TSV05 receives data (command buffer
words) and stores them internally on the M7l96 module for
storage and/or execution.

The TSBA can be used as a data pointer (bus address for
DMA), pointing to data buffer areas located somewhere in
the
LSI-II Bus address space.
In this mode, the
controller loads TSBA wi th data pointer information from
internal storage. The contents are then used to point to
data buffer areas while transferring Tape data between CPU
memory and the tape transport. The
data pointer is
extended to 22 bi ts (18-21 are zero s) if the TSSR high
byte is not first loaded, or if the Extended Features
Switch is OFF.

The TSSR is a J16-bit register that can be updated only from the
M7l96 internal logic.
It cannot be modified from the LSI-II Bus.
In this register, major system status can be observed.
The tape transport, when on-line, is under control of the
microprocessor
and
related
microcode
within
the
M7l96
interface/controller module.
When the transport is off-line, the
transport is under control of its own internal logic, which can in
turn be controlled by the operator using swi tches on the front
panel.

3-15

Before the TSV05 begins a function, the LSI-II must assemble a
command packet in main memory. The command packet is always four
words long, although not all commands use all four of the words in
the packet. The words in the command packet may be thought of as
the contents of several registers:
1.

Command Register (CMDR)

Data Pointer Register (DPR)

Positive Byte Count Register (BPeR)

The Command Register (CMDR) contains the machine language
representation of one of the commands listed in Table 3-2. The
Data Pointer Register (DPR) contains the address of the data to be
manipulated. The DPR consists of two words: a low-order address
word containing bits 15-00, and a high-order address word
containing either bits 17-16 (for IS-bit addressing) or bits 21-16
(for 22-bit addressing). In the IS-bit addressing mode, bits 01-00
of the DPR high-order address word are used to specify bits 17-16
of the address. If the extended features switch is on, the 22-bit
addressing mode can be used.
In this case, bi ts 05-00 of the DPR high-order address word are
used to specify address bits 21-16.
When the command being used does not involve a data operation, the
two DPR words are not used in the command packet (see Figure 3-4).

3-16

One-word type
00

15
COMMAND WORD (CMDR)

CMDR

NOT USED

NOT aSED
NOT USED
B.

Two-word Type
15

I
I
I
CMDR+21
I
I
I
I
I

COMMAND WORD (CMDR)

CMDR

BYTE COUNT(BPCR)
NOT USED
NOT USED

Four-word Type
15

CMDR

I
I
I

COMMAND WORD (CMDR)

CMDR+21--~A71~5------------~A~D~D~R~E~S~S~P~O~I~N~T~E~R~(~L~OW~O~R~D~E~R~--~------~A~0~01

I
CMDR+41
I
CMDR+61
I

ADDRESS POINTER (HIGH ORDER DPR WORD)
BYTE COUNT

Figure 3-4

I
IA21-A18 IAI7,AI6 I
I
I
I

Command Packet Types

3-17

The positive Byte Count Register (BPCR) contains the number of
items to be manipulated during the operation specified by the
command. In a packet that includes DPR words, the BPCR word
follows the DPR word. If a packet does not involve a data
operation, the BPCR word, if present, follows the command words.
Message packets are issued by the M7l96 controller and buil t in
the host CPU memory space. Subsystem operation requires a message
buffer address to be supplied on a Write Characteristics command.
This command must be the first command issued to the subsystem
a fte r an ini ti al i ze. Otherwi se, all othe r commands wi 11 be
rejected.
The command pointer must be an address on a
(i.e., beginning at octal 0, 4, 10, 14, etc.).

modulo-4

boundary

The DPR is eventually loaded into TSBA to be used as
the
LSI-II
Bus address for DMA transfers.
The BPCR is used to indicate the
number of bytes (8 bi ts of data per byte) to be moved to or from
the transport during a data transfer.
It is also used to specify
the number of records in a Space Record command or the number of
files in a Skip Tape Marks command. The CMDR specifies the
function to be executed by the subsystem.

3.3.2 Registers
The TSV05 contains four hardware device reg isters on the M7l96
controller mod ule, and also five .. remote" device reg isters tha t
the controller maintains in a Message Buffer area of the LSI-II
memory. The hardware registers are:
1.

LSI-II Bus Address Register (TSBA).

LSI-II Data Buffer (TSDB).

Status Register (TSSR).

Extended Data Buffer Register (TSDBX).

The remote reg isters set up in LSI-II memory are Extended Status
Registers 0-4 (XST0-4). Register formats and bit definitions are
presented in the sections that follow.

3.3.2.1 Bus Address Register (TSBA) -- The Bus Address Register
(TSBA) is a Read-Only hardware register located at the first I/O
register address. In normal operating mode, it displays the
low-order 16 bi ts of the memory address to be used. or being used
by the controller to access system main memory (e.g., for command
buffer fetch, message buffer store,
or data
transfer). In
Maintenance Mode, it displays data from the Wraparound tests
invoked by writing into TSDB.
Figure
3-5 illustrates the TSBA,
and Table 3-3 defines the bits.

3-18

LSI-II Bus Address + 0 -- Read-Only
15 14 13 12 11 10
4
2
8
7
6
5
3
1
9
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
\A1S\A14\A13\A12\A11~A10\A09\A08\A07\A06\A0S\A04\A13\A02\A0l\A00\

\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\ S \ S \ S \ S \ S \ S \ S \ S \ S \ S \ S \ S \ S \ S \ S \ S \
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
\

Figure 3-5 TSBA Register Format
Table 3-3

Bit

Name

15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00

AlS
A14
A13
A12
All
A10
A09
A08
A07
A06
A0S
A04
A03
A02
A01
A00

TSBA Register Bit Definitions

Definition
Bus address
Bus address
Bus address
Bus address
Bus address
Bus address
Bus address
Bus address
Bus address
Bus address
Bus address
Bus address
Bus address
Bus address
Bus address
Bus address

bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 09
bi t· 08
bit 07
bit 06
bit 05
bit 04
bit 03
bit 02
bit 01
bit 00

Address Bits 15 through 00 normally reflect the low-order 16 bits
of the 22-bit address used by the controller to access LSI-II Bus
memory. They can be loaded by:
1.

The CPU when writing a word into TSDB, to define the
address of the Command Buffer for the next operation.
TSDB<lS:02> are copied into TSBA<lS:02>, and TSBA<0l:00>
are set to 0.

The CPU writing into the high byte (DATOB) of TSDB (for a
maintenance function).
TSDB bi ts 15-08 are copied into
both bytes of TSBA. Data for bits 07-00 is TSDB<lS:08>.
TSDB bi ts 08 and 09 are copied into TSSR bi ts 08 & 09
(A16, A17).

3-19

The CPU wr i ting into the low byte (DATOB)
maintenance function). TSDB bits 07-00
TSBA<07:00). TSBA <15:08) is then loaded
07-00.

The CPU wri ting a word (DATO) into TSDB in Maintenance
Mode.
(Maintenance mode is achieved as a result of b or

of TSDB (for a
are copied to
from TSDB bi ts

c) •

The controller, for specifying bits 15-00
address. TSBA is not modified by Initialize.

DMA

3.3.2.2 Data Buffer Register (TSDB) -- The TSDB is, externally, a
16-bi t
Wri te-Only
register
that
is parallel loaded from the
LSI-II Bus. Internally, it is a 22-bit register. It can be loaded
from the CPU by four different types of transfers. Two transfers
are for maintenance purposes (DATOB to high byte and DATOB to low
byte); these place the controller into Maintenance
Mode, which
can be cleared onl y by an Ini tial i ze, and causes the internal
"Data
wraparound" functions. The
third
is
for
maintenance
purposes
(DATO word when
in Maintanance Mode).
The fourth is
for normal operation (DATO word when not in Maintenance Mode) to
specify a Command Pointer. The 4-bit extension to TSDB is written
at the high byte of the TSSR location. These address bi ts are
ignored if the Extended Features Swi tch is OFF. The extension is
cleared after it issued once and so must be reloaded if extended
addressing is to be used on subsequent command pointers. (It must
be loaded before
the TSDB is loaded.) It is also cleared by
Initialize.
The controller will respond whenever the TSDB location is written
to, but will be loaded only ·when the SSR bi t in the TSSR register
is set (if SSR is clear, the RMR bit in TSSR will be set). writing
into TSDB clears SSR.
After a DATO or DATOB to TSDB (for
maintenance data "wraparound"), SSR momentarily clears then
sets
when the data "wraparound" has been performed.
An Initialize
should be performed (Le., write into TSSR) in order to
use
the
controller again for
normal operation.
Note that entering
Maintenance Mode (by performing a DATOB to either byte of the
TSDB)
causes the NBA (Need Buffer Address) bit in TSSR to be set
and automatic running of the idle-time On-Line Microdiagnostics
to be inhibited.
The TSDB register is illustrated in Figure 3-6 and the
listed and defined in Table 3-4.

3-20

bits

are

LSI-11 Bus Address + 0 -- Write-Only
15 14 13 12 11 10 9
8
7
4
6
5
3
2
1
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
IP151p141p131p121plllp101p091p081p071p061p051p041p031P021p171p161
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
IM151M141M131M121M111M101M091M081M071M061M051M041M031M021M011M001
+---+---+----+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-6
Table 3-4

TSDB Register Format

TSDB Register Bit Definitions

Bit

Name

Definition

15-02
01-00

P<15:02>
P<17:16>

Command Pointer bits 17-02. When the TSDB
is written as a word, and SSR=l, and the
controller is not in Maintenance Mode, the
data is loaded into bits 17-02 of both the
TSBA Output File register (for reading onto
the LSI-11 Bus) and into an internal TSBA
register and command processing commences.
TSBA bits 01-00 are cleared to 0 (modulo-4
address).
In addition, the Extended TSDB
Register
(TSDBX)
is loaded into TSBA bits
21-18; TSDBX must be loaded before TSDB.

(DATO
Word,
Normal
Mode)
1
1
1
15-081 M<15:08>
1
1 (DATOB
1 to High
1 Byte)
1
07-001 M<07:00>
(DATOB
to Low
Byte)
15-00

M<15:00>
(DATO)
Word in
Maint.
Mode)

Maintenance Data bits 15-08 for wraparound
to TSBA. If the wraparound is correct,
M<15:08> appears in both bytes of TSBA.
A DATOB to TSDB places the controller into
maintenance mode.
Maintenance Data bits 07-00 for wraparound
to TSBA. If the wraparound is correct,
M<07:00> appears in both TSBA<07:00> and
in TSBA<l5:08> .A DATOB to TSDB
places the controller into maintenance mode.
Maintenance Data bits 15-00. This function
can be in used for specifying the address
used in the Low-Byte Data Wrap test. Bits
15-12 are reserved for future maintenance
functions and should be written to 0.

3-21

3.3.2.3 Status Register (TSSR) -- TSSR is a 16-bit register.
Although defined as a Read/Write register, its contents cannot be
directly modified by the LSI-II Bus.
It can be read to examine
status, but writing into it causes a hardware initialize of the
controller.
(A DATOB) to the high byte only of the TSSR, however,
loads the extended TSDBX).
The contents of the register is
modified by the M7196 controller.
The register format is
illustrated in Figure 3-7. Table 3-5 gives the register bit
definitions.
If the initialize diagnostic fails, this register
has alternate bit definitions.
15 14 13 12 11 10
9
8
7
6
5
4
2
1
3
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
ISC 1 * ISCEIRMRINXMINBAIA171A161SSRIOFLIFCI1FC01TC21TCI1TC01
1
1
1
1FC21
1
1
1
1
liS 1
1
1
1
1
1
1
1 S 1
1 7 1 S 14,51 SIS 1 SIS 11,31 7 1 7 1 SIS 1 S 1
1
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-7
Table 3-5

Bit

Name

14
13

SCE

TSSR Register

TSSR Register Bit Definitions

Code

Definition

Special Condition
When set, indicates that the last command was
not
completed
without incident:
either an error was detected or an
exception condition (i.e., Tape Mark
on read,
reverse motion at BOT,
etc.)
occurred.
Also set by the
error bits in TSSR: RMR, and NXM.
Indicates that the Termination
Class bits are nonzero (unless RMR
is
the only error
see RMR).
Cleared by Initialize unless a selftest error is detected, in which
case SC is set.
Not used in TSV0S, UPE in TSII.
Sanity Check Error. Set when the
controller detects an internal
failure. This is considered
serious enough that a Message
Buffer is not sent out. SPE in TSll.

FC2
7

3-22

Bit

Table 3-5

TSSR Register Bit Definitions (Cont)

Name

Code

Definition

RMR

Register Modification Refused - Set
when the TSDB is written from the
LSI-II Bus and SubSystem Ready (SSR)
is not set. Causes the Special Condition (SC)
bit to be set but no
Termination Class
(the TSV05 never
sees the data written) because on a
system with no bugs, RMR can be set
if TSDB is written while an ATTN
message is being output. If ATTN's
are not enabled, RMR setting indicates a fatal controller problem or
a software bug.

NXM

4,5

Nonexistent
Memory
Set
when
trying to do a DMA transfer to/from
a memory location which does not
exist
(does not respond within 12
usee). May occur when fetching a
Command Packet, fetching or storing
data, or storing the Message Packet.

NBA

Need Buffer Address
When set,
indicates that the TSV05 needs a
Message
Buffer
address.
Set by
Initialize and performing a DATOB to
the TSDB (i.e., to enter Maintenance Mode). Cleared during the Write
Characteristics command (if a valid
address was given).
If NBA=1 and
any
command
other
than
Write
Characteristics is given, the operation is terminated with Function
Reject.

09-08

A<17:l6>

Address Bits 17-16. A17 and A16
display
bits 17 and 16 of the
internal TSBA register, which holds
a Command Pointer or DMA address.
Loaded from TSDB bits 01-00 when
TSDB is written.

3-23

Bit

Table 3-5

TSSR Register Bit Definitions (Cont)

Name

Code

Definition

Ready
When
set,
indicates that the TSV05 is not busy
and is ready to accept a new command
pointer.
Cleared by writing the
TSDB. Also cleared by Initialize,
then set by the controller if the
basic
microdiagnostics
are
successfully passed.

Off
Line
When set, indicates
that the TS05 transport is off-line
and unavailable for any tape motion
commands.
This bit can cause a
Termination Class of 1 (on an ATTN
interrupt)
or
3
(resul ts
in
Non-Executable
Function,
NEF,
status). This bit does not indicate
the
current status of the Tape
Transport
(updated
on
command
completions) •

SSR

OFL

Sub-Syst~m

1,3

05-04

FC<1:0>

Fatal Termination Class Code - Used
to indicate the type of fatal error
which has occurred on the TSV05. The
code is valid only when the SC bit
is set and the Termination Class
Code
(TC) bits are all set (Ill) i
they are clear otherwise. The
FC codes are:

Code Meaning

Internal diagnostic failure.
See the Error Code byte
(XST3) for the failed
function.
Initialize must be
issued for the controller to
accept furthe r commands.

1
1

2
3

Reserved.
Not used.
Reserved for detection of
power down on transport (not
currently implemented).

1
1

__________________----_1----------------------------------------3-24

Table 3-5

TSSR Register Bit Definitions (Cont)

Name

Code

I
Bit

Definition

______ 1__________________________________________________________
1

03-011 TC<2:0>
1
1

Termination Class Code - This 3bit field acts as a word
offset value whenever an error or
exception condition occurs on a
command. Each of the 8 possible
values of this field represents a
particular class of errors or
exceptions. The conditions in
each class have similiar significance and recovery procedures (as
applicable). The codes are:
Code Meaning

o
1
2
3
4
5
6
7

Normal Termination
Attention Condition
Tape Status Alert
Function Reject
Recoverable Error - tape
position is one record down
tape from start of function.
Recoverable Error - tape not
moved
Unrecoverable Error - tape
position lost
Fatal Controller Error - (See
Fatal Class Codes)
Not Used

3-25

3.3.2.4 Extended Data Buffer Register (TSDBX) -- The Extended
Data Buffer Register (TSDBX) is a Write-Only hardware byte
register located at the fourth byte address of the TSV05 I/O
reg ister block.
This address corresponds to the high-order byte
of the TSSR register.
The TSDBX is used to specify the most
significant four bits of a 22-bit command pointer address, and
also to allow an automatic tape boot sequence to be performed.
TSDBX can be written only by a byte-access (DATOB) cycle addressed
to the high byte of TSSR.
If the Extended Features switch is Off
when TSDBX is written, only the boot bit is examined; the other
bits are ignored.
Figure 3-8 illustrates
describes each bit.

the

format

TSDBX,

and

Table

3-6

Assume the Extended Features switch is on.
Once written, the
contents of the least-significant four bits of TSDBX are
transferred to bits 18 through 21 of the internal TSBA (Bus
Address) register for use as a command pointer.
The low order 18
bits of the command pointer are specified by writing into the TSDB
register, which starts operation and then clears TSDBX.
Therefore, a subsequent load of only the TSDB will specify a
22-bit command pointer address with the high-order four bits equal
to zero.
For the TSDBX register to be properly written, the SSR
(Subsystem Ready) bit in TSSR must be set; if it is not, the RMR
(Register Modification Refused)
bit will be set and no
modification to TSDBX will occur. When the TSDBX is written, the
SSR bi t is not cleared.
Therefore, RMR should be checked for,
before TSDB is written. Writing the TSDB will begin processing on
TSDBX.
If the Boot bit is not set, the command pointed to by the
22-bit TSDB will be retreived, and command processing will begin.
If the Boot bit is set, SSR will remain clear until the boot
sequence is complete or until an error occurs.
LSI-II Bus Bits:
Byte Data Bits:

15
7

14
6

13
5

12
4

11
3

10
2

9
1

+---+---+---+---+---+---+---+---+
BT I

Ip211p201p191p181

--- --- ---+---+---+---+---+---+

Figure 3-8

TSDBX Register Format

3-26

Table 3-6

Bit

Name

14-12
11-08

T5DBX Register Bit Definitions

Definition
Boot Command Bit. When written to 1, with
55R=1, causes the tape to be rewound to
BOT, the first tape record to be skipped,
and the second record (only the first 512
bytes of it) to be loaded into CPU memory
space starting at location o.
Reserved. 5hould always be written to O.

P<2l:l8>

Command Pointer bits 21-18. When the T5DBX
is written, and 55R=1, the data is loaded
into
bits 21-18 of the internal T5BA
register. T5DBX is cleared after T5DB is
written and is also cleared by Initialize.

3.3.2.5 Extended Status Register 0 (XSTO) -- Extended 5tatus
Register 0 (X5TO) appears as the fourth word in the Message Buffer
stored by the T5V05 upon completion of a command or on an
Attention (ATTN).
Figure 3-9 illustrates the register format and
Table 3-7 describes each bit.
15 14 13 12 11 10
4
2
1
8
7
6
3
9
5
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
ITMKIRL51LETIRLLIWLEINEFIILCIILAIMOTIONLIIE IVCKIPEDIWLKIBOTIEOTI
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I 5 I
15,21 2 I 2 I 2 13,61 3 I 3 I 3 I 5 11,31 5 15,31 5 15,315,315,21
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-9

X5TO Register Format

3-27

Table 3-7
Bit

Namel Codel

TMK

I
I

XST0 Register Bit Definitions
Description

S,2

I
I
I

Tape Mark Detected.
Set whenever a Tape
Mark
is
detected
during
a Read, Space, or
I
Skip
command,
and
also
as a result of the
I
Write
Tape
Mark
or
Write
Tape Mark Retry
I
commands.
I
I
I Record Length Short. This bit indicates
that either the record length was shorter
I
I than the byte count on Read operations, a
Space Record operation encountered a tape
mark or BOT before the position count was
exhausted, or a Skip Tape Marks command was
terminated by encountering BOT or a double
tape mark
(if that operational mode is
enabled, see LET) prior to exhausting the
position counter.
I

RLS

LET

Logical End of Tape. Set only on the Skip
Tape
Marks
command
when
either two
contiguous tape marks are detected, or when
moving off of BOT and the first record
encountered is a tape mark. The setting of
this bit does not occur unless this mode of
termination is enabled through use of the
Write Characteristics command.

RLL

Record Length Long. When set, indicates
that the record read on a Read was longer
than the byte count specified.

WLE

3,6

Write Lock Error. When set, indicates that
a
write operation was issued but the
mounted tape did not contain a write enable
ring.

NEF

Function.
Non-Executable
indicates that a
command
executed
due to one of
conditions:

When
set,
could not be
the following

I
- The command specified reverse tape direc- I
tion but the tape was already at BOT.
I
The issuing of any motion command when I
the Volume Check bit is set.
I
- Any command, except Get Status or Drive I
Initialize, when the transport is off-linel
- Any write command when the tape does not I
contain a write enable ring
(also causes I
Write Lock Status - WLE)
I

3-28

Table 3-7
Bit

Namel Codel

Description

I
I

-=I~L=C-I--=3--I~I~1~1-e-g-a~1~-C=-o-m-m-a-n~d~.--~S~e-t~-w~h-e-n---a---c-o-m-m-a--n~d~i-s-I

I issued

I
I
I
ILA I
I

and either its Command field or its I

I Command Mode field contains codes which are
I not supported by the TSV05.
I
I Illeqal
Address.
Set
when a command
I speclfies an address more than 18 bits
I (when the Extended Fea tures swi tch is of f)
I or more than 22 bits (when the Extended
I Features switch is on), or an odd address
when an even one is required.

I
I

XST0 Register Bit Definitions (Cant)

L
I

I
I
I

I
I
I
I

MOT

Motion. Tape is moving. Indicates that the I
transport is asserting Formatter Busy or I
Rewinding status.
I

ONL

On Line. When set, indicates that the TS05
transport is on-line and operable. A change
in this bit can cause a Termination Class
of 1
(ATTN interrupt,
if ATTENTIONS are
enabled).
If ONL is clear and a motion
command is issued, causes NEF (Termination
Class 3).

Interrupt Enable. Reflects the state of the
Interrupt Enable bit supplied on the last
command.

VCK

Volume Check. When set, indicates that the
transport has been either powered down or
turned
off-line. Cleared by the Clear
Volume Check
(CVC)
bit in the Command
Header
word.
This
bit
can cause a
Termination Class of 3.

I
I
I
I
I
I

PED

Phase-Encoded Drive. Always Set. Indicates I
that the TSV05 is capable of reading and 1
writing only phase encoded data.
1

WLK

S,3

BOT

S,3

Write Locked. When set, indicates that the 1
mounted reel of tape does not have a write 1
enable
ring
installed.
The tape is, 1
therefore, write protected.
1
I
Beginning of Tape. When set, indicates that 1
the tape is positioned at the load point as I
denoted by the BOT reflective strip on the I
tape.
1

_____ -----------------------------------------------1
3-29

Table 3-7

Bit

XST0 Register Bit Definitions (Cont)

I
I
Name I Codel

Description

______----1----_1----------------------------------------------I
I
EOT I 8,2
I
I
I
I
I
I
I
I
I
I

______----I

I End of Tape. This bit is set whenever the
I tape is positioned at or beyond the End of
I Tape reflective strip. Does not reset until
I the tape passes over the strip in the
I reverse direction under program control. If
I the
controller
is
read
buffering
I (pre-reading
records
from
tape
I automatically) and the EOT strip is seen,
I this bit will not be set until the program
I actually requests the record associated
I with the EOT.

1_______________________________________________

3.3.2.6 Extended Status Register 1 (XST1)
Extended Status
Register 1 (X8Tl) appears as the fifth word in the Message Buffer
stored by the TSV05 upon completion of a command or on an
Attention (ATTN). Figure 3-10 illustrates the register format and
Table 3-8 describes each bit.
15 14 13 12 11 10
8
7
4
2
1
9
6
3
5
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
IDLTI
I
I
I 4 I

ICORI * I * I * I * IRBPI * I * I * I * I * I * IUNCI * I
I
I
I
I
I
I + I
I
I
I
I
I
I
I
I
IS,41
I
I
I
I 4 I
I
I
I
I
I
I 4 I
I

+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

Figure 3-10

XSTI Register Format

3-30

Table 3-8

Bit

Name 1 Codel

1
1
1
1

DLT

XSTI Register Bit Definitions

1
1
1

Description
Data Late. Set when the M7196 internal
FIFO buffer is full on a Read and the
transport attempts to enter another byte, or
when it is empty on a Write and the transport requests another byte. These conditions
occur whenever the LSI-II Bus latency exceeds the required data transfer rate of the
TS05.
Not Used.

COR

S,4

Correctable Data. When set, indicates that
a
correctable
data
error
has
been
encountered while reading or writing. On a
Write, this bit causes a termination class
of 4. On a Read, the termination class is 0
(no corrective action required).

12-91
7-2,1

Not used by the TSV05i always set to 0. In
the TSll, these bits indicate Crease Detected (CRS), Trash in Gap (TIG), Deskew Buffer Fail
(DBF), Speed Check (SCK), Invalid
er Fail (DBF), Speed Check (SCK), Invalid
Preamble or Postamble
(IPR, IPO), Sync
Failure
(SYN),
Invalid End Data
(lED),
Postamble Short or Long
(POS, POL), and
Multi-Track Error (MTE). The TS05 transport
reports any of these errors as Hard Error,
causing the UNC bit (bit 1) to be set.

1
1
1
1
1
1

1
1

1
1
1 RBP
1
1
1

Read Bus Parity Error.
Set when the controller detects a parity error on the Read
Data lines of the transport bus (during a
Read or Write).
If this parity error was
also detected by the transport, the UNC bit
will also be set. The problem is most
likely in the bus drivers in the transport,
the bus receivers in the controller, or in
the transport bus cable.

1
1
1
1
_____ 1__________________________________________________________-

3-31

Table 3-8

Bit

Name

Code

UNC

XST1 Register Bit Definitions (Cont)

Definitions
Uncorrectab1e Data or Hard Error. Set, in
response to the transport asserting Hard
Error, during a read or write to indicate
that one of the following has occurred:
-

False preamble detection
False postamb1e detection
Multichannel dropout
Parity error without associated channel
dropouts (could result from bad Write
Data interface cir<cuit in the controller)
- Loss of data envelope pri9r to postamble
detection
- Excessive skew
"\

3.3.2.7 Extended Status Register 2 (XST2)
Extended Status
Register 2 (XST2) appears as the sixth word in the Message Buffer
stored by the TSV05 upon completion of a command or on an
Attention (ATTN). Figure 3-11 illustrates the register format and
Table 3-9 describes each bit.
Note that the low-order 8 bits of
this register have special meaning for the Write Characteristics
command; unlike the TS1l, there is no display of dead tracks, or
residual capstan tick count.
15 14 13 12 11 10
7
4
3
2
1
9
8
6
5
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
IOPMIRCEI * I * I
IWCFI
I * IRL71RL61RL51RL41RL31RL21RL11RL01
I
I@I
I
I
I
I
I
I@I@I@I@I@I@I@I@I
I S 17F21
I
I
I 7 I
I
I SIS I SIS I SIS I SIS I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-11

XST2 Register Format

3-32

Table 3-9

XST2 Register Bit Definitions

Description

Bit

Name \ Code

OPM

\
\
\
\

Operation in Progress.

RCE I

RAM Checksum Error. Set on a Read or Write
when the checksum of a data block extracted
from the M7l96 internal RAM does not match
the checksum computed when the data was
entered. Causes Fatal termination.
This Bit is (SIP) Silo parity in the TSll.
Not used by the TSV~5; always set to ~. In
the TSll, bit 13 is Serial Bus parity at
Drive, bit 12 is Capstan Acceleration Fail,
and bit 8 is parity Dead Track.

13,
12,
8

11,9

(Tape Moving)

Not used.

WCF

Write Clock Failure. Set during a write to
indicate that the M7l96 internal FIFO buffer
is not being emptied by the transport.

7-~

Revision Level. On a Write Characteristics
command this field displays the settings of
the Extended Features Enable switch (bit 7)
and the Buffering Enable switch (bit 6) and
the microcode revision level (bits 5-~). On
all other commands, bits 2-~ show the unit
number of the currently selected transport.

7-~

3-33

3.3.2.8
Extended Status Register 3 (XST3) -- Extended Status
Reg ister 3 (XST3) appears as the seventh word in the
Message
Buffer stored by the TSV05 upon completion of a command or on an
Attention (ATTN). Figure 3-12 illustrates the register format and
Table 3-10 describes each bit.
15 14 13 12 11 10
8
7
9
5
4
3
2
1
6
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I MICRO DIAGNOSTIC ERROR CODE
I * IOPIIREVI * IDCKI * I * IRIBI
I @
@ @ @ @ @ @ @ I
I
I
I
I
I
I
I
I
7
7
7
7
7
7
7 I
I 6 I S I
IS,61
1
1 2 1
I 7
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-12 XST3 Register Format
Table 3-10

XST3 Register Bit Definitions

Bit 1 Namel Code

Description

_____ 1_____ 1____________________________________________________

15-81 MDE I

Micro-Diagnostic Error Code. This field is
encoded
by the controller to indicate
various
failures
detected
by
the
microprogram.
Detections can occur during
the
running of internal on-line tests
during Idle periods
(e.g.,
RAM or FIFO
failures) •
Once
an
error occurs, an
Initialize
must be issued to use the
controller again.

Not used by the TSV05. In the TSl1, this
bit is LMX - Tension Arm Limit Exceeded.

Operation Incomplete. Set when Read, Space,
or Skip operation has moved about 25 feet
of tape without detecting any data on the
tape.

Reverse. Set when the current operation
caused reverse tape motion (includes the
Retry commands as well as simply reverse
Read,
space, etc); clear when operation is
forward or rewind.

Not used by the TSV0S, in the TSll, this BIT
is CRF (Capstan Response Failure).

1
1

I
1
1

I
1

I
I
I
I
I
I OPI

I
I
I

I
05

I REV
I
I
I
I
I
I
I

----_1----- _____________________________________________________

3-34

Table 3-10

XST3 Register Bit Definitions (Cont)

I
I
Description
Name I Codel
I
I
DCK
S,6 I Density Check. Set when a PE Identification
(IDB)
is not detected while moving
I Burst
A Read, Space or Skip will,
I off of BOT.
complete
(if no other errors
I however,
occur) to allow tapes with the IDB wrong to
be read.

Bit
03

2,1

RIB

Not used by the TSV05i always set to 0. Bit
2 is used by the TSll to indicate that a
noise bit was detected during an erase. Bit
1 is used by the TSll to indicate that a
limit switch was activated.

Reverse Into BOT. When set, indicates that
a
Read, Space, Skip or Retry command
already in progress has encountered the BOT
marker when moving tape in the reverse
direction. Tape motion will be halted at
BOT.

3.3.2.9 Extended Status Register 4 (XS.T4) -- Extended Status
Register 4 (XST4) appears as the eighth word in the Message
Buffer stored by the TSV05 upon completion of a or on an
Attention (ATTN). Figure 3-13 illustrates the register format and
Table 3-11 describes each bit.
Note that for this word to be
stored, the Extended Features option must be enabled and the
Message Buffer extent parameter specified in the Write
Characteristics command must be increased by 2 over the normal
TSll specification.
r 15

+---+---+---+---+---+---+---+---+---+---+~--+---+---+---+---+---+

IHSPIRCXI
I
WRITE RETRY COUNT
I
I
+
I
I + I + I
I
S
I
I S I 6 I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-13

XST4 Register Format

3-35

Table 3-11

Bit 1 Name
_____ I

Codel

1
HSP

1
I

1 RCX

1
I

1
1

1
I

I
1

I
I
I
I
I
I
I
1

I
I
1

I
I

High

I Reserved. Always set to 0.

13-81

7-0

Speed. When set, indicates that the
is operating in high speed mode
1 (100
IPS). When clear,
the transport is
1 operating in low speed mode (25 IPS).
1
1 Retry
Count Exceeded. When set, indicates
1 that
the controller was buffering Write
1 data
and could not successfully output the
1 buffered record within the specified number
1 of
retries.
Causes Tape Position Lost
1 termination.
1

1 transport

1
1
14

Description

_____ 1_______________________________________________

1
15

XST4 Register Bit Definitions

WRC

Write

Retry

Count

Statistic. When the

I controller is buffering write data records,
this field indicates the total number of
controller-initiated retries performed in
order
to
write the previous buffered
record.
This count is cleared after it is
displayed. For example, consider the situaation in which 1) buffering is in operation
and record N is in RAM (the controller has
given successful termination for record N) ,
and 2) the Write command for record N+l has
been issued to the controller but the controller has not yet accepted the command,
I
and 3) the controller must perform M retriesl
to finally write record N successfully. In
I
this situation, M will appear in the WRC
I
field when termination of record N+l is
I
finally given.
I

----_1----- _____________________________________________________ 1

3-36

3.3.2.1e Summary of Registers -- The formats of the hardware and
remote (software determined) registers discussed in the preceding
sections are summarized in Figures 3-14 and 3-15. Figure 3-16
shows the forma t of the command reg isters implemented by the
LSI-II CPU when it builds a command packet.

15 14 13 12 11 Ie
9
s 7 6 s 4 3 2 1
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
IAlSlA141A131A121AlliAlelAe91AeslAe71Ae61AesIAe41Ae31Ae21AellAeei
TSBA I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
(R/O) I SIS I SIS I SIS I SIS I SIS I SIS I SIS I SIS I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

TSDB IPlSIP141P131P121PlI1Plelpe91peslpe71pe61peslpe41pe31Pe21pellpeel
(W/O) I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

TSSR I SCI * ISCEIRMRINXMINBAIA171A161SSRIOFLIFClIFCOITC21TCliTCei
(R/W) I
I
I @ I
I
I
I
I
I
I S I
I
I
I
I
I
I S I
I & I S 14,51 SIS I SIS 11,31 7 I 7 I SIS I S I

I
I
I

+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+---+---+---+---+---+---+---+---+

IBT I
TSDBXI
I
(W/O) I
I

I
I
I

IP211p2elP191plSI
I
I
I
I
I
I
I
I
I
I

(TSDBX exists only on the TSVeS)

+---+---+---+---+---+---+---+---+

Legend:

*@ = Bit defined for TSll but normally set to e by TSVeS
= Bit defined for TSll but has similiar but slightly

different meaning for Tsves.
S = Status bit, not necessarily associated with a particular
termination class.
Termination
class code associated with this bit.
1-7 =
Figure 3-14

TSVeS Hardware Device Registers

3-37

15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
ITMKIRLSILETIRLLIWLEINEFIILCIILAIMOTIONLIIE IVCKIPEDIWLKIBOTIEOTI
XSTO I
I
I
I
I
I
I
I
I
I S I
I
I
I
I
I
I
IS,21 2 I 2 I 2 13.61 3 I 3 I 3 I S 11,3\ S IS,31 S IS,3IS,3IS,21
+---+---+-~-+---+---+---+---+---+---+---+---+---+---+---+---+---+

I DLT I
XST1 I
I
I 4 I

I COR I * I * I * I * I RBP I * I * I * I * I * I * I UNC I * I
I
I
I
I
I
I + I
I
I
I
I
I
I
I
I
IS,41
I
I
I
I 4 I
I
I
I
I
I
I 4 I
I

+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

IOPMIRCEI * I * I
XST2 I
I @ I
I
I
ISI71
I
I

IWCFI
I
I
171

I * IRL71RL61RL51RL41RL31RL21RL11RL01
I
I @ I @ I @ I @ I @ I @ I @ I @ I
I
ISISISISISISISISI

+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

I MICRO DIAGNOSTIC ERROR CODE I * IOPIIREVI * IDCKI * I * IRIBI
XST3 I @
@ @ @
@ @ @
@ I
I
I
I
I
I
I
I
I
I 7
7
7
7
7
7
7
7 I
I 6 I S I
IS,61
I
I 2 I

+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

IHSplRCxl
XST4 I + I + I
I S I 6 I

I
I
I

WRITE RETRY COUNT
+

I
I
I

+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

Legend:
defined for TS11 but normally set to 0 by TSV05.
*@ = Bit
Bit
defined
for TSll but has similiar but slightly
=
different meaning for TSV05.
+ = Bit not defined (unused) in TSl1.
S = Status bit, not necessarily associated with a particular
termination class.
1-7 = Termination class code associated with this bit.
XST4 = Extended Status Register 4 not defined for TS11;
Available in TSV05 when Message Buffer extent
is increased.
Figure 3-15

TSV05 Extended Status Registers

3-38

+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
IACKI DEVICE
I
MODE
I
FORMAT I
COMMAND
I
CMDR I

I DEPENDENT

CODE

+---+-----------+---------------+-----------+-------------------+
LOW ORDER DATA POINTER ADDRESS
I

DPRL I
I

A<15:00>

DPRH I
I

A<2l:l6>

BXCR I

COUNT PARAMETER

+---+-----------+---------------+-----------+-------------------+
HIGH ORDER DATA POINTER ADDRESS
I

+---+-----------+---------------+-----------+-------------------+
I
I
+---+-----------+---------------+-----------+-------------------+

NOTE: Not all words are required for all commands
Figure 3-16

TSV05 Command Register Format

3.3.3 Packet Processing
The CPU passes control information to the controller by means of a
command packet in the Command Buffer area (e.g., a sequential
series of control words) in CPU memory space.
Similarly, the
controller passes status information to the CPU by means of a
message packet in the Message Buffer area in CPU Memory space.
A
command is ini tiated by the CPU by specifying to the controller
the location of the Command Buffer (by writing TSDBX/TSDB).
The
controller then becomes "busy", fetches the command and associated
parameters from the Command Buffer, executes the command, deposits
status into the Message Buffer, and finishes by becoming idle.
The CPU can then examine the TSSR hardware register and the
Message Buffer to determine the success or failure of the command.
Every command is handled in this basic manner.
The following
paragraphs discuss buffer control, Message Buffer format, and
Attention handling.
The basic "packet protocol" scheme implemented by the TSV05 is
identical to that implemented by the TSll/TS04 Magtape System.
There are, however, differences in some of the information passed
between controller and CPU. These differences are in the form of
extra command modes and extra or differing status fields
implemented by the TSV05 when the Extended Features switch is set.
There is also a difference in operation of the Write Subsystem
Memory diagnostic command, whether or not Extended Features are
enabled.
These differences are discussed within the descriptions
of the individual commands. The basic protocol, however does not
change.

3-39

3.3.3.1 Buffer Ownership and Control -- To prevent the controller
from updating the Message Buffer while the CPU is reading it, or
the CPU from updating the Command Buffer while the controller is
reading it, the concept of "ownership" is defined.
Each
buffer
may be owned by the controller or the CPU, but not by both.
Ownership of a buffer can be transferred only by the current
owner.
There are four different combinations
buffers in the two directions:

transferring

the

Command Buffer:

CPU to Controller, by the CPU.

Command Buffer:

Controller to CPU, by the Controller.

Message Buffer:

CPU to Controller, by the CPU.

Message Buffer:

Controller to CPU, by the Controller.

two

Table 3-12 describes the buffer transfer operations.
An Initialize aborts any current operation and gives ownership of
both the Command Buffer and the Message Buffer to the CPU.
Table 3-12

I
I Buffer

1--------I Command
I Buffer
I

Buffer Ownership Transfers

Direction

Transfer Method

CPU to
Controller

The CPU transfers ownership of the
Command Buffer to the Controller by
writing the address of the Command
Buffer into the TsnB register. This
clears the SSR bit in TSSR.

I
I

=-__
~~~~~__~__~~________~__~_
The Controller transfers ownership of

I~----~- _=-~__~____

I Command
I Buffer
I
I
I
I
I

I
I
I

I
I
I
I

Controller
to CPU

the Command Buffer back to the CPU by
depositing a Message Packet (in the
Message Buffer)
that has the Acknowledge
(ACK)
bit set in the message
header word. After the message is deposited by the controller, it sets the
SSR bit in TSSR to indicate that the
message is in the Message Buffer. If
the message does not contain the ACK
bit set, the CPU will know that the
controller did not see the last Command Buffer and that the CPU still
owns the Command Buffer. The command
may be reissued by the CPU.

1--------- ______________________________________________________

3-40

Table 3-12

Buffer Ownership Transfer

I
I

Buffer

Direction

Message
Buffer

CPU to
Controller

Message
Buffer

Controller
to CPU

Transfer Method

1--------- ------------1----------------------------------------1
The CPU transfers ownership of the
Message Buffer to the controller by
setting the ACK bit in the Command
Buffer and then initiating the command
by writing into TSDB.
If the Command
Buffer does not contain~the ACK bit,
the controller will know that the CPU
did not see the last message buffer
and the controller still owns it. The
controller,
in response to the CPU
writing into TSDB, will set SSR and
perform an interrupt (if the IE bit is
set)
without sending out a message,
since it does not own the buffer.
The Controller transfers ownership of
the Message Buffer to the CPU by writing the Message Buffer and setting the
SSR bit. This can happen at one of two
times:
1. At the end of a command, or
2. By outputting an Attention (ATTN)
message. In this case, SSR will already be 1 because an ATTN only
happens when the controller is inactive. So the controller clears
SSR, outputs the message, the sets
SSR again
(and interrupts if the
IE bit was set on the Message Buffer Release Command that gave control of the Message Buffer to the
Controller). Note that for an ATTN
to occur, the EAI bit must have
been set in the previous Write
Characteristics command.

During normal command processing, the ownership of both buffers
passes simultaneously, first from CPU to Controller (at the start
of command processing, when the CPU writes a Command Pointer into
the
TSDB
register),
and
then
from
Controller
to
CPU
(upon completion of the command).

3-41

3.3.3.2
Buffer Control On Attentions -- An Attention (ATTN) is
enabled by the CPU by setting up the appropriate Characteristics
Mode word on the Write Characteristics command.
It allows the
controller to flag exceptional condi tions (change in transport
on-line/off-line status and microdiagnostic self-test errors) when
the controller is in the Idle state (not executing a command).
If
an ATTN condi tion occurs and the controller does not own the
Message Buffer, the controller will queue the ATTN internally.
Then, when the CPU releases the Message Buffer on the next command
(with the ACK bit
set), the controller will output the ATTN
message with the ACK bit 0 in the message header word to indicate
tha t the command wa s los t (except for the transfe renc e of
ownership of the Message Buffer to the controller). In this case,
the controller refuses to accept ownership of the Command Buffer.
The CPU will then still own the Command Buffer (because the
controller did not accept the command) and will also
own
the
Message Buffer now filled with an ATTN message.
If the CPU still
wants to do the ignored command, the CPU must reissue the command
(wi th the ACK bi t set).
Exceptions to this procedure are the
Write Characteristics command and Write Subsystem Memory command,
which are executed regardless of a pending Attention.
These
exceptions are necessary to allow the software to specify a
Message Buffer address, control enabling of Attentions, and
perform diagnostics.
Now consider the case in which the CPU wants to be notified of a
change in status or a microdiagnostic error while the controller
is inactive for a long period of time.
To accomplish this, the
controller must own the Message Buffer for that entire period of
time.
Normally, the controller gives up ownership of the Message
Buffer at the end of a command.
However, for enabling Attention
messages, ownership of the Message Buffer is transferred to the
controller via the Message Buffer Release command.
This is a
special command that tells the controller not to give ownership of
the Message Buffer back to the CPU at the end of the command. The
controller does not output a message at the end of this command,
but just updates the TSSR register (with the SSR bit set) and
interrupts (if the IE bi t was set in the command and such an
interrupt was enabled by the ERI bit in the previous Write
Characteristics command.
The controller then maintains ownership
of the Message Buffer until an ATTN condition is seen and then
immediately clears SSR, outputs the ATTN message (with the ACK bit
not set since the controller is not responding to a command), and
then sets SSR and interrupts the CPU (if the IE bit was set on the
Message Buffer Release command).
In this condition, the CPU owns
the Command Buffer and the Controller owns the Message Buffer. If
the controller outputs an Attention message, ownership of the
Message Buffer is passed to the CPU. At that time the system is
back to the state of the CPU owning both buffers.
Another ATTN
will not be done until the CPU does a command with the ACK bit set
to release ownership of the Message Buffer containing the ATTN
message.

3-42

If the CPU has done a Message Buffer Release command, and wants to
do another command but has not received an ATTN from the
controller (so that the controller still owns the Message Buffer
from the Message Buffer Release command), the CPU can do a command
wi thout the ACK bi t set in the command buffer.
At the time the
command is issued, the CPU does not own the Message Buffer so the
CPU cannot release the Message Buffer.
If the CPU does set the
ACK bit, nothing will happen except the CPU might miss an ATTN if
the controller was sending out an ATTN message at the same time
that the CPU was issuing the command.
It is possible that the CPU may attempt to initiate a new command
at or
near the same time that the controller attempts to output
an Attention message.
[The command must not have the ACK bit set
since the CPU does not own the Message Buffer.]
If the CPU writes
the TSDB register while SSR is clear during an ATTN, the Register
Modification Refused (RMR) error bit will be set and that command
will be ignored.
The ATTN message will not have the ACK bit set
since the controller does not own the command buffer.
Note that
RMR may set in this way on a bug-free system.
All other settings
ofRMR indicate a software bug (the CPU tried to do a command
before the previous command was finished).
If the CPU command was
lost because the controller was outputting an ATTN message, Volume
Check (VOL CHK) and Interrupt Enable (IE) are not updated.
If the
CPU command was rejected (illegal command, etc.) and not ignored,
VOL CHK and IE are updated to the start of the rejected command.

3-43

3.3.3.3
Message Packet Format -- Figure 3-17 illustrates the
format of the message packet in the Message Buffer.
This format
is used for all messages, whether at an end of a command or for an
Attention.
The message consists of a Header word, a
Data Field
Length word, a Residual Byte/Record/Tape-Mark Count word, and
either four or five Extended Status registers.
Normally, only
four Extended Status registers are provided. The fifth one (XST4)
is available only when the Extended Features function of the
controller is enabled. Table 3-13 describes the message packet.
15

+---+-----------+---------------+-----------+-------------------+
ICtll Reserved
I
Class Code
I Format 1 I
Message Type
I
I •••I •••••••••••I•••••••••••••••I •••••••••••I •••••••••••••••••••I
IACKI 0
C
C I 0
o I m m m m m I
+---+-----------+---------------+--------~--+-------------------+

Reserved

Data Field Length

I •••••••••••••••••••••••••••••••I •••••••••••••••••••••••••••••••I
o 0 0 0 0 0 0 0 0 0 0 0 1 x x 0 I

+---------------------------------+---------------------------------+
RBPCR
XST0
XST1
XST2
XST3

XST4
+

-------------------------------------------------------------------+

NOTE:

XST4 is not part of a TSl1-compatible Message Buffer.
is available only when the Extended Features mode
enabled.
Figure 3-17

Message Packet Format

3-44

It
is

Table 3-13
Word
1

Message Packet Field Definitions

Bit

Description

ACK -- Acknowledge.
This bit is set by
the TSV05 to inform the CPU that the Command Buffer is now available for any pending or subsequent command packets. On an
ATTN message, this bit will not be set
since the controller does not own the
Command Buffer.

14-12

Reserved.
These
future expansion.
as zero.

11-8

Class Code Field. These bits define the
class of failure determined for the rest
of the message buffer when the Message
Type field is not indicating a normal END
message. The codes are:

(Header)

7-5

bits are reserved for
They will always appear

Message
Type

Class
Code

Definition

ATTN

0000

On or off line

ATTN

0001

Microdiagnostic failure

FAIL

0000

Not used. (On the TS11,
this code indicates a Bad
Packet due to a serial bus
parity error.)

FAIL

0001

Illegal Command (ILC) , Illegal Address (ILA), or
Need Buffer Address (NBA)
on a tape motion command.

FAIL

0010

Write-Lock error on Nonexecutable function.

FAIL

0011

Microdiagnostic Error.

Packet Format il Field. The single value
supported by the TSV05 is 000, which specifies a one-word message header.

3-45

Table 3-13

Message Packet Field Definitions (Cont)

Word

Bit

Description

4-0

Message Type Code. This field, together
with the Format field indicates the format
and length of message packets. For the
TSV05 (and TSll), the Message Type is of
the form 10xxx, which indicates that the
message contains a Header word, a DataCont'dl Length
word and then xxx
Data/Status words. This field indicates
the general type of message contained in
the buffer and is related to the
Termination Class Code appearing in the
TSSR register as follows:

Termination
Class Code

Message
Type

Definition

0,2
3
4,5,6,7
1,7

10000
10001
10010
10011

End
Fail
Error
Attention

15-8

Reserved.
This field is reserved for future expansion.
It always appears as 0.

7-0

Data Field Length. This field specifies
how many bytes of information follow this
word in the message packet. Normally,
with the Extended Features option of the
TSV05 disabled, this field contains a value of 10
(binary 00001010), indicating
that the packet contains the RBPCR plus
four Extended Status registers. With the
Extended Features option enabled, this
field contains a value of 12, to indicate
that an additional Extended Status register (XST4) is supplied.

(Data
Length)

3-46

Table 3-13

Message Packet Field Definitions (Cont)

Description

Word

Bit

15-00

Residual Byte/Record/File Count Register.
After a Read command, this word contains
the difference between the number of bytes
specified in the command and the number of
bytes actually transferred from tape. In
other words, this register indicates by
how much the tape record fell short of the
expected length. After a Space Records or
Skip Tape Marks command, this register
contains the difference between the number
of records or tape marks specified in the
Count word of the command and the number
of records or files actually skipped. Note
that spacing and skipping operations can
terminate before the count is exhausted
for a variety of reasons (tape mark, BOT,
etc.) •

15-00

Extended Status Register 0. See Paragraph
3.4.2.5 for a desc~iption of this register.

5
(XST1)

15-00

Extended Status Register 1. See paragraph
3.4.2.6 for a description of this register.

15-00

Extended Status Register 2. See Paragraph
3.4.2.7 for a description of this register.

7
(XST3)

15-00

Extended Status Register 3. See paragraph
3.4.2.8 for a description of this register.

8
(XST4)

15-00

Extended Status Register 4. See Paragraph
3.4.2.9 for a description of this register.
Note that this register is not supplied in
TSll Compatibility mode
(Extended Features disabled).

(RBPCR)

4
(XST0)

(XST2)

3.3.3.4
General Status Handling Information
Table 3-14
summarizes the relationship between the termination class
code
appearing in the TSSR register and Message Type code appearing in
the Header Word of the Message Buffer after a message packet has
been deposited by the controller.

3-47

Table 3-14

TC2-~

Value

Offset

Termination Class/Message Type Relationship

Message
Type
END
(2~)

Normal Termination. The operation
was completed without incident.

ATTN
(23)

Attention condition.
This code
indicates that the drive has undergone a status change, such as
going Off-Line or coming On-Line.

END

Tape Status Alert. A status condition has been encountered that
may have significance to the program. Bits of interest in the Extended Status registers include
TMK (Tape Mark), EaT (End of Tape)
and RLL (Record Length Long).

(2~)

Meaning

FAIL
(21)

Function Reject.
The specified
function was not initiated. Bits
of interest include OFL, VCK, BOT,
WLE, ILC, and ILA.

ERROR
(22)

Recoverable Error. Tape position
is a record beyond what its position was when the function was initiated. Suggested recovery procedure is to log the error and issue
the appropriate retry command.

ERROR
(22)

Recoverable Error. Tape position
has not changed. Suggested recovery procedure is to log the error
and reissue the original command.

3-48

Table 3-14

Termination Class/Message Type Relationship (Cont)

Message
Type

TC2-fiJ
Value

Offset

ERROR
(22)

Unrecoverable Error.
Tape posiion has been lost. No valid recovery procedures exist unless the
tape has labels or sequence numbers.
Recovery would be handled
by the specific application program.

ATTN
(23) or
ERROR
(22)

Fatal Subsystem Error. The subsystem is incapable of properly
performing commands, or at least
its integrity is seriously questionable. Refer to the Fatal Class
code field in the TSSR register
for additional information on the
type of fatal error.

Meaning

3-49

The following points should be noted in reference to
error handling:

status

and

Er ror bi ts in the TSSR reg ister (SC and RMR) are cleared
by successfully loading a command pointer into the TSDB
register and by successfully depositing an END message.

All commands (even the Get Status command) clear the
internal copy of each error bi t in the Extended Status
registers except bits 15-8 of XST3 (Microdiagnostic Error
Code). Therefore, a Get Status command will not return
the error bits as set up by a previous tape operation.

A Read operation which encounters a Tape Mark will not
transfer any data and will give a Tape Status Alert
termination. The Tape Mark and Record Length Short status
bits will be set, and the RBPCR word in the message buffer
will contain the orig inal byte count as specified in the
command.

A Space Records operation will automatically terminate
when a Tape Mark is traversed, and the TMK status bit will
be set. Also, Record Length Short (RLS) will be set if the
record count was not decremented to zero.

A Skip Tape Marks operation will automatically terminate
when two consecutive tape marks are encountered and the
.. Enable Skip Stop" (ESS) mode is enabled v ia the Wr i te
Character istics command.
Record Length Short (RLS) will
be set if the count was not decremented to zero. The same
is also true if a tape mark is the first record off BOT
and both the ESS and ENB bi ts were set in the prev ious
Write Characteristics data word.

Every Write, Write Retry, Write Tape Mark, Write Tape Mark
Retry, and Erase command which is executed at or beyond
the EOT marker will result in a Tape Status Alert
termination. The internal EOT status bit will remain set
until logically passed over in the reverse direction
(Rewind, reverse Read, reverse Space, etc.).
The EOT
status bit is not specifically identified with a
particular record.

A Read Reverse, Space Reverse, Reverse or Skip Tape Marks
Reverse command which encounters BOT after the operation
is underway will result in a Tape Status Alert termination
(the RIB status bit will be set).

If a Read Reverse, Space Records Reverse, or Skip Tape
Marks Reverse command is issued while the tape is already
at BOT, a Function Rej ect (NEF-Non-Executable Function)
status will be returned.

3-50

When a normal Rewind command is issued, the term ination
message and interrupt will not occur until the tape
reaches BOT and has stopped. If the tape space is already
at BOT when the command is issued, the transport will
still be commanded to rewind to make sure the tape is
properly positioned.

10.

When a Rewind with Immediate Interrupt is issued, the
controller commands the transport to rewind, checks for
proper status, and then issues an interrupt and END
message for normal termination. If a new tape motion
command is issued to a rewinding unit, the controller will
wait until the tape has been rewound to BOT before
preceding with the new command.
During execution of a
Rewind wi th Immediate Interrupt, the Motion (MOT) bi t in
XSTO will be set if a Get Status command is performed.

11.

Any Write Function issued at BOT (including Erase which
results in the Density Check bit (DCK) being set will
cause a termination of that command with a TSSR
Termination Class code of 6 set
to
indicate
an
unrecoverable error.
Normally, a Wr i te function causes
the PE Identi fication (ID) burst to be wr i tten off BOT,
and the controller checks for the appropriate status
signal from the transport. Therefore, if DCK is set on a
wri te off BOT, a serious transport or controller problem
exists.

12.

If a Densi ty Check condi tion is detected during a Read,
Space or Skip Function, the DCK bi t wi 11 be set but the
operation will not be aborted. If DCK is the only error
status bi t set during the operation, normal termination
will be reported.
This allows tapes wi thgood data but
bad denisty check (ID) areas to be read.
If, in fact, a
tape of the wrong densi ty has been mounted, other errors
will be reported and will stop the operation.

13.

Note that if you begin reading a tape, get a Density Check
wi th no other errors, and then append data to the tape,
the Write will get a Termination Class code of 6
indicating that tape position is lost because Density
Check will remain set. The whole tape should be copied
over so that dr ives that depend on the ID burst will be
able to read the tape.

14.

Certain failures can result in no interrupt even though
the specified command had Interrupt Enable set. These
fail ures inc1 ude NXM (Non-Ex istent Memory Er ror), since
the failure could have occurred before the Interrupt
Enable bit was fetched from the command packet.

3-51

15.

The following are notes concerning interrupts:
a.

If interrupts are enabled (the Interrupt Enable bi t
was set on the previous command accepted by the
controller), interrupts may occur at any time. This is
due to the possiblity of diagnostic interupts
occurring immediately after normal terminations (even
if Attention interrupts are not enabled). The software
must therefore defend against unexpected interrupts.
The subsystem may not be useable, but the software
should still not crash.

Similarly, the controller could be broken in such a
way that interrupts may be issued even with IE clear.

With Attention interrupts enabled (EAI bit set on the
Writ~ Characteristics command), a non-fatal diagnostic
failure will not be reported until control of the
Message Buffer is returned to the controller. A fatal
failure may interrupt at any time as lone as Interrupt
Enable is set.

With Attention interrupts disable, a diagnostic
failure will not be noticable until the next command
is issued. At this time, the command will be rejected.

When record buffering for Writes is in operation, the
controller issues Normal Termination messages and
interrupts immediately after the data to be wri tten
has been stored in the controller's RAM and before the
data is actually written on tape. The possiblity
exists that the record cannot successfully be written
on tape with the first attempt, in which case a retry
algorithm is executed to attempt to successfully write
the data. If the data is eventually successfuly
written, the CPU will not know that any problem
occurred unless the Extended Features option is
enabled, in which case the Write Retry Count field in
XST4 can be examined in the message termination the
NEXT command. If retries are therefore to be logged,
the software should examine the Write Retry Count
field in each message packet.

If record buffering for Writes is in operation and the
controller cannot write a stored record successfully
from its RAM (retry count exhausted), the next Tape
Motion command following the Write command associated
with the failed record will be terminated with
Termination Class 6 (Tape position Lost) and the Retry
Count Exceeded (RCX) bit in XST4 will be set. In
addi tion, the Uncorrectable Error (UNC) bi t in XSTI
will be set. The tape will be positioned one record
beyond the last successfully written record.

3-52

3.3.4 Commands
The TSV05 is capable of running on programs that are, in most
cases, identical to those written for the TSll/Ts04 Magtape
Subsystem. When the Extended Features option of the TSV05 is
disabled, the following commands and their associated command
modes operate identically to those of the TSll, except for some of
the extended error status bits provided for by the TSll but not by
the
TSV05.
READ
WRITE
POSITION
FORMAT
GET STATUS
With Extended Features enabled, the above commands have the
capability to perform 22~bit memory addressing, and, in addition,
some command modes (subcommands) are added that are not in the
TSll repertoire: basic operation of the basic TSll commands,
however, remains the same.
The following commands differ in their meanings to TSV05 and TSll
hardware:
WRITE CHARACTERISTICS

(Same as TSll except for the ability, when
the Extended Features switch is set, of the
TSV05 to specify an extra Characteristics
Data word to control special features, and
also to specify a longer than normal
Message Buffer length to accommodate an
extra Extended Status register).

WRITE SUBSYSTEM MEMORY (The data format and function is entirely
different from that of the TSll).
CONTROL

(Function is same as TSll except for the
Clean Tape command mode, which the TSV05
treats as a NO-OP -- tape is not moved. In
addition,
when
Extended
Features
is
enabled, two new com~and modes are added).

INITIALIZE

(Similar to TSll in that control logic is
initialized but the transport itself is not
initialized in certain non-error states.)

The following paragrpahs first describe the general command
format, then each command is described in detail.

3-53

3.3.4.1 Command Packet Definitions -- The CPU issues a command to
the TSV05 subsystem by first building a Command Packet in CPU
memory space (on a modulo-4 address boundary) then writing the
address of the packet into the TSV05 TSDB hardware register. The
address written is termed the Command Pointer.
Assuming that the
TSV05 is ready to accept a command, writing of the Command Pointer
initiates command processing, in which the controller fetches the
Command Packet and executes the command encoded within the packet.
Logically, a Command Packet can be composed of one, two, three or
four
l6-bi t words, depending upon the type of command and the
amount of information it needs to proceed wi th execution.
All
Command Packets begin with a Command Packet Header Word, shown in
Figure 3-18.
The format of this word is the same for all
commands; the encoding of the various fields wi thin the word
distinguishes one command from another.
Table 3-15 defines the
fields within the Header Word.
Table 3-16 summarizes the Command
Code and Command Mode field definitions. The following paragraphs
describe each command in detail, along with its specific Command
Packet format.
Figure 3-18 illustrates the posi tioning of tape
data bytes in CPU memory under various conditions (Forward,
Reverse, Swap Bytes, etc.) for Read and Write commands.
Certa in bi ts of the
Header Word and othe r words wi thi n the
Command
Packet are not defined for all commands.
When building
the Command Packet, the software should set these undefined bits
to zero.
If any bi t is undefined or reserved wi th respect to a
particular command and the bit is not zero, the command will not
be executed and will be terminated with a Function Reject
(Termination Class 3).
4
2
1
15 14 13 12 11 10
3
8
7
6
5
9
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
ICtllDevice Dep.1
Mode
I Format 1 I
Command
I

I•••I •••••••••••I•••••••••••••••I•••••••••••I•••••••••••••••••• •I

IACKICVC opp SWBI 0
m
m
m lIE
0
0 I 0
c
c
c
c I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-18

Command Packet Header Word

3-54

Table 3-15

Command Packet Header Word Bit Definitions

Bit

Name

Function

Acknowledge
(ACK)

This bit should be set when issuing a
command when the CPU owns the Message
Buffer. Its function is to inform the
TSV05 that the Message Buffer is now
available for any pending or subsequent message packets.
This passes
ownership of the Message Buffer to the
TSV05 controller.
If the CPU has released ownership of the Message Buffer
to the TSV05 for Attentions and has
not received an ATTN message yet, the
ACK bit should be coded as a 0.

14-12

Device
Dependent
Bits

These three bits perform functions
applicable to particular commands. The
bit definitions are as follows:

Bit

Name

Definition

CVC

Clear Volume Check - When set,
causes the Volume Check condition, set when the transport
goes from Off-Line to On-Line,
to be cleared, thereby allowing
tape operations to be executed
on the transport.

OPP

Opposite - When set, reverses
the execution sequence of reread
commands (i.e, Reread Next,
Previous, etc)

SWB

Swap Bytes - When set, instructs
the TSV05 to alter the sequence
of storing and retrieving tape
data bytes from the CPU memory.
When SWB=0, the "first" byte in
a word is the least significant
byte (bits 7-0); this is the
standard DEC method. When SWB=l,
an industry-standard method is
specified, in which the first
byte of a word is considered to
be bits 15 through 8. Figure
3-19 illustrates the positions
of bytes as written or read from
memory.

3-55

Table 3-15

Command Packet Header Word Bit Definitions (Cont)

Bit

Name

Function

11-8

Command Mode
Field

This field acts as an extension to the
Command Code field and allows further
specification of device commands, as
detailed in Table 3-16.

7-5

Packet
Format :In
Field

This field defines the header type
(only one type is used in the TSV05
and TS11) and the Interrupt ~nable.
The only two valid configurations are:
Bit Values

Definition
One-word Header;
Interrupt Disable

100
4-0

Command Code

One-word Header;
Interrupt Enable

This field defines that major command
category.
It is used together with
the Command Mode field to specify the
command, as defined in Table 3-16.

Table 3-16

Command Code and Mode Field Definitions

00001 I READ
,
,

Command I
Mode Name
Mode
I
--~~_I------~------~----~~-------0000
, - Read Next (Forward)
0001
- Read Previous (Reverse)
0010
- Reread Previous (Space
Reverse, Read Forward)
0011
- Reread Next (Space Forward,
Read Reverse)

00100

WRITE CHARACTERISTICS

0000

- Load Message Buffer address
and Set Device Characteristics

00101

WRITE

0000
0010

- Write Data (Next)
- Write Data Retry (Space Reverse, Erase, Write Data)

00110

WRITE
SUBSYSTEM
MEMORY

0000

- Enter Maintenance Mode and
Load Test Functions
(diagnostic use only)

01000

POSITION

0000
0001
0010
0011
0100

01001

FORMAT

0000
0001
0010

- Write Tape Mark
- Erase
- Write Tape Mark Retry
(Space Reverse, Erase,
Write Tape Mark)

01010

CONTROL

0000
0001
0010

- Message Buffer Release
- Rewind and Unload
- NO-OP (Performs Clean Tape
function in TS11)
- Rewind with Immediate
Interrupt

Command,
Code'

Command
Name

________ ,______________

0100*

Space Records Forward
Space Records Reverse
Skip Tape Marks Forward
Skip Tape Marks Reverse
Rewind

01011

INITIALIZE

0000

- Controller/Drive Initialize

01111

GET STATUS

0000

- Get Status (output END
status message)

Extended Features function, not part of the TSll repertoire.

3-57

Swap Bytes = 0
Buffer Address = 1000
Byte Count = 10(8)
Block Size = 10(8) bytes

Swap Bytes = 1
Buffer Address = 1000
Byte Count = 10(8)
Block Size = 10(8) bytes

+-----+-----+
1000

+-----+-----+
1002

1002

1006

+-----+-----+
I
7 I 6 I
+-----+-----+

Swap Bytes = 0
Buffer Address = 1001
Byte Count = 10(8)
Block Size = 10(8) bytes

Swap Bytes = 1
Buffer Address = 1001
Byte Count = 10(8)
Block Size = 10(8) bytes

1000
1002
1004

1006

1010

+-----+-----+
I
I 7 I
+-----+-----+

1010

1006

+-----+-----+
6

+-----+-----+
1004

+-----+-----+
I
6 I 7 I
+-----+-----+

+-----+-----+
1002

1004

+-----+-----+
1000

+-----+-----+

+---~-+-----+

1004

+-----+-----+

+-----+-----+
I
I 0 I
+-----+-----+
I 1 I 2 I
+-----+-----+
I

+-----+-----+
I 5 I 6 I
+-----+-----+
I 7 I
I
+-----+-----+

NOTE
Byte 0 indicates the byte neare~t to BOT.
Figure 3-19 (a) Memory/Tape Data Byte Positioning (Forward
Tape Direction, Read or Write; Reverse Read with Even Byte Count)

3-58

Swap Bytes = 0
Buffer Address = 1000
Byte Count = 7
Block Size = 7 bytes

1000
1002
1004
1006

+-----+-----+
I
1 I 0 I
+-----+-----+
I
3 I 2 I
+-----+-----+
I
5 I 4 I
+-----+-----+
I
I
6 I
+-----+-----+

Swap Bytes = 0
Buffer Address = 1001
Byte Count = 7
Block Size = 7 bytes

1000
1002
1004
1006

+-----+-----+
I 0 I
I
+-----+-----+
I
2 I 1 I
+-----+-----+
I 4 I 3 I
+-----+-----+
I
6 I 5 I
+-----+-----+

Byte 0 indicates the

Swap Bytes = 1
Buffer Address = 1000
Byte Count = 7
Block Size = 7 bytes

1000
1002
1004
1006

+-----+-----+
I
0 I 1 I
+-----+-----+
I 2 I 3 I
+-----+-----+
I 4 I 5 I
+-----+-----+
I 6 I
I
+-----+-----+

Swap Bytes = 1
Buffer Address = 1001
Byte Count = 7
Block Size = 7 bytes

1000
1002
1004
1006

NOTE
byte

+-----+-----+
I
I
0 I
+-----+-----+
I 1 I 2 I
+-----+-----+
I
3 I 4 I
+-----+-----+
I
5 I 6 I
+-----+-----+

nearest to BOT.

Figure 3-19 (b)
Memory/Tape Data Byte Positioning
(Forward or Reverse Read, Odd Byte Count)

3-59

3.3.4.2
Get Status Command -- Figure 3-20 illustrates the Get
Status command packet. This command causes a message packet to be
deposited in the Message Buffer area in order to update the
Extended Status registers.
However, after the end of any command
except Message Buffer Release., the TSV05 hardware automatically
updates the Extended Status registers, so this command need be
used only when the TSV05 has been left idle for some time, or when
a status register update is desired without performing a tape
motion command, or when the user desires to read the unit number
of
the currently selected tape transport (deposited in bits 2-0
of Extended Status Register 2).
15 14 13 12 11 10
2
9
8
7
6
5
4
3
1
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
ICtllDevice Dep.1
Mode
I Format 1 I
Command
I

I •• • I ••••• ••••• • I •••••••••••••• •I • •• ••••••• •I •• ••••••••••••• ••• • I
IACKICVC 0
0 I 0
0
0
0 lIE
0
0 I 0
1
1
1
1 I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

I
Not Used
I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-20

Get Status Command Packet

3.3.4.3 Read Command -- Figure 3-21 illustrates the command packet
for a Read. There are four normal modes of operation: Read
Forward, Read Reverse, Reread Previous, and Reread Next. Two of
these modes (the Rereads) are further controlled by the state of
the Opposite (OPP) bit in the packet header word.
Mode

Function

0000

Read Next (Forward)

0001

Read Previous (Reverse)

0010

Reread Previous

= 0:
OPP = 1:

OPP

Space Reverse, Read Forward
Read Reverse, Space Forward
Reread Next

0011
OPP

= 0:

Space Forward, Read Reverse

OPP

= 1:

Read Forward, Space Reverse

3-60

15 14 13 12 11 10
1
7
4
2
9
S
6
5
3
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
ICtllDevice Dep.1
Mode
I Format 1 I
Command
I

I •••I •••••••••••I•••••••••••••. • I•••••••••••I•••••••••••••••••••I

IACKICvC OPP SWBI 0
m
m
m lIE
0
0 I 0
0
0
0
1 I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
LOW ORDER
I
IA15
BUFFER ADDRESS
A001
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
HIGH ORDER
I
I
I
I 0
BUFFER ADDRESS
0 IA21
A1SIA17 A161
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
BUFFER EXTENT (Byte Count)
I
I
(16-Bit positive Integer)
I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-21

Read Command Packet

The command packet for a Read contains four words: a Header word,
two words specifying the address of the data buffer in CPU memory
space where the data read from tape is to be deposited, and a
Buffer Extent (Byte Count) word specifying the number of bytes
available in the data buffer and the number of bytes expected in
the tape record to be read.
A byte count of 0 specifies that
65,536 (64K) bytes are expected.
The third word in the packet specifies the high-order address bits
of the starting address of the data buffer.
When the Extended
Features option is disabled (i .e., the TSV05 is running in TS11
compatibility mode), only the two low-order bits (A17 and A16) may
be nonzero; these bits, together with the 16 bits in the second
word of the packet allow an IS-bit memory address to be specified
for the start of the data buffer. In this case, if any of bits
2-15 are nonzero, the function will not be performed but will
terminate with a Function Reject with Illegal Address (ILA) error
status. When the Extended Features mode is enabled, the low-order
6 bi ts of the thi rd word are used to specify bi ts A21-A16 of a
22-bit memory address.
In this mode, if any of bits 6-15 in the
third word are nonzero, the command is aborted with Function
Reject termination with Illegal Address (ILA) error status.

3-61

The read operation is assumed to be for a record of known length.
Therefore, the correct record byte count (fourth word of the
packet) must be known.
If the byte count exactly equals the
record length, Normal termination occurs. If the record is shorter
than the specified byte count, the Record Length Short (RLS) error
bi t will be set in XSTflI and a Tape Status Alert termination
occurs.
If the record on tape is larger than the byte count, the
Record Length Long (RLL) error bi t will be set in XSTflI and Tape
Status Alert termination given; in this case, on1 y the number of
bytes specified in the byte count will be transferred to the data
buffer. Also, any Read operation that encounters a Tape Mark will
not transfer any data.
In this case, the Tape Mark (TMK) and
Record Length Short (RLS) bits will be set and a Tape Status Alert
termination given.
Reverse Read operations which pass BOT cause the Reverse Into BOT
(RIB) bi t in XST3 to be set and Tape Status Alert termination
given.
If the tape is already at BOT when a reverse read (i.e.,
Read previous or Reread Previous with the OPP bit set) is issued,
there will be no tape motion and Function Reject termination will
occur, wi th the Non-Executable Function (NEF) error bi t set in
XSTflI.
The OPP bi t in the header word (bi t 13) alters
sequence of the Reread command modes, as follows:

the

exec ution

Reread Previous (Space Reverse, Read Forward) becomes Read
Reverse, Space Forward.

Reread Next (Space Forward,
Forward, Space Reverse.

Read

Reverse)

becomes

Read

Reading data in the reverse direction with a correct byte count
will place data in memory correctly (as if the record were read in
the forward direction), not in reverse order. This feature allows
data to be placed correctly in memory on one retry (read reverse).
On a reverse read, data is placed in the data buffer in the
reverse order (highest address first); the starting address is
calculated by adding the byte count to the address specified in
the command packet and then subtracting 1. if the byte count is
greater than the actual record length, the beg inning of the data
buffer (lowest addresses) will not contain the data from tape.
Similarly, if the actual record is larger than the byte count, the
first part of the record (that nearest to BOT) will not be placed
in the data buffer.
For any of the data transfers, the Swap Bytes (SWB) bi t in the
command header word controls the storing of bytes in CPU memory,
as shown in Fig ure 3-19.

3-62

3.3.4.4 Write Characteristics Command -- Figure 3-22 illustrates
the Write Characteristics command packet and data format. The
objective of this packet is to inform the TSV05 subsystem of the
location and size of the Message Buffer in the CPU memory space.
The Message Buffer must be at least seven contiguous words long
(eight when the Extended Features option is enabled) and located
on a word boundary.
The Write Characteristics command also transfers a Characteristics
Mode word to the controller and, if Extended Features is enabled,
an additional control word. The Characteristics Mode word causes
specific actions for certain operational modes. The bits for this
word are defined in Table 3-17.
Table 3-18 defines the bi ts in
the addi tional control word ava ilable when Extended Features is
enabled.
The four command packet words are identical to those used for the
TSII except for the third word (High Order Characteristic Data
Address). In this word, bits 2 through 5 are used to specify bits
18 through 21, respectively, of the address specifying the
location of the associated Characteristics Data buffer.
The data
buffer must reside on an even address in CPU memory space.
If bit
o of the second packet word (Low Order Characteristic Data
Address) or bi ts 2-15 (Extended Features disabled) or bi ts 6-15
(Extended Features enabled) of the third packet word (High Order
Characteristic Data Address) are nonzero, the function is not
executed but is terminated with a Function Reject.
In this case,
no message packet is stored but an interrupt is generated if the
IE bit is set.
When the Extended Features switch on the M7196
module is off, the Write Characteristics command functions
identically to that of the TS11.
When the Extended Features
sWltch is on, a fifth Characteristics Data word can be specified
to invoke special functions.
In addition, a Message Buffer
Extent of
16 bytes (8 words) can be specified so that Extended
Status Register 4 (unique to the TSV05) can be outputed.

3-63

Similarly, the first four words of the five-word Characteristic
Data buffer are identical to those used for the TSll except for
the third word (High Order Message Buffer Address). In this word,
bits 2 through 5 are used to specify bits 18 through 21,
respectively, of the address specifying the location of the
Message Buffer to be used for subsequent status and attention
messages.
The fifth Characteristic Data word is used to specify parameters
for the multi-record buffering mode of operation and also is used
to select a tape unit in a multi-drive system. Table 3-18
The Write Characteristics command will clear the Need Buffer
Address (NBA) bit in the TSSR reg ister, ind icating that a val id
Message Buffer has been specified, if all of the following
conditions are met:
1.

The command was not rej ected because of nonzero bi ts in
reserved or unused fields wi thin the first three command
packet words,

The fourth packet word (Byte Count) contains at least a
count of 6, to allow first three Characteristic Data words
to be fetched,

The first two Data words
(word boundary), and

The third Data word contains a value of 14
(specifying the length of the Message Buffer).

specify

valid

even
or

address
greater

If any of the above conditions are not met, then the NBA bit will
be set (even if it was already clear from a previous valid Write
Characteristics command) and no further message packets will be
deposi ted.
Note that if the Byte Count word in the command packet is less
than 7, the Characteristic Mode data word will not be fetched,
causing the current values of the Characteristic Mode bits stored
in the controller to be retained. Similarly, if the Byte Count is
less than 1121, the addi tional Extended Features control word will
not be fetched and the current values retained.

3-64

(Command Packet)
4
2
1
15 14 13 12 11 10
7
6
3
9
8
5
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
ICt11Device Dep.1
Mode
I Format 1 I
Command
I

I ••. I •••••. •••••I ••. ••••••••••••I •. •••••••••I ••••. •••••••••••. ••I
1
o lIE
o I
IACKICvC 0
010
01"
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
LOW ORDER
I
I
IA15
CHARACTERISTIC DATA ADDRESS
A"ll " I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
HIGH ORDER
I
I
I
CHARACTERISTIC DATA ADDRESS
"IA21
A181A17 A161
I 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
BUFFER EXTENT (Byte Count)
I
(16-Bit Positive Integer)
I
I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
(Characteristics Data)
2
1
4
3
8
7
6
5
15 14 13 12 11 10
9
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
LOW ORDER
I
I
IA15
MESSAGE BUFFER ADDRESS
A011 " I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
HIGH ORDER
I
I
MESSAGE BUFFER ADDRESS
"IA21
A161
I 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
LENGTH OF MESSAGE BUFFER (At Least 14 bytes long)
I
(16-Bit Positive Integer)
I
I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
I ESS I ENB I EAI I ERI I
I
I "
0 I
I
I
I
I 0
"
0
"I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I XIRG RETRY
I NO-XIRG RETRY IRTYI
IHSPI BUFFERI
UNIT
I
LIMIT
I
LIMIT
I
I
I
I CONTROL I SELECT
I
I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

Figure 3-22

Write Characteristics Command Format

3-65

Table 3-17

Bit

Name

15-08
3-0

Characteristic Mode Data Word Bit Definitions
Definition
Not used. These bits are not checked by the
TSV0s controller. Their state will not affect
operation but they should be written to 0.

ESS

Enable Skip Tape Marks Stop - When set, this
bit instructs the controller to stop and set
the Logical End of Tape (LET) status bit during a Skip Tape Mark command when a double
tape mark
(two contiguous tape marks) have
been detected. Setting this bit also enables
operation of the ENB bit.
In the default setting of 0, the Skip Tape Marks command will
terminate only on tape mark count exhausted,
if it runs into BOT, or if it runs 15 feet
past the EOT marker.

ENB

Enable Tape Mark Stop Off BOT - This bit is
meaningful only if the ESS bit is set. When
this bit is set (and ESS=l), the tape is at
BOT, a Skip Tape Marks Forward command is issued, and the first record seen is a tape mark,
then the controller will stop the operation
and set the Logical End of Tape (LET) status
bit in XST0.
If this bit is clear under these
conditions, the controller will merely count
the tape mark and continue.

EAI

Enable Attention Interrupts - When this bit is
0, attention conditions such as transitions
from On-Line to Off-Line and Off-Line to OnLine, and microdiagnostic failures will not
result in interrupts to the cpu. Rather, a
tion will not be noticeable until the next command is issued; at this time the command will
be rejected.
With this bit set to 1, attention conditions will cause an Attention message to be generated (and an interrupt, if the
IE bit was set on the last command) as soon as
the controller owns the Message Buffer.

ERI

Enable Message Buffer Release Interrupts If
this bit is 0, interrupts will not be generated upon completion of a Message Buffer Release
command.
Upon recognition of the command,
only Subsystem Ready (SSR) will be reasserted.
If ERI is 1, and interrupt will be generated
(without an accompanying message packet).

3-66

Table 3-18 Extended Characteristics
Data Word Bit Definitions

Bit

Name

Description

______________ ------------------------------------------------------1I
15-12

XGRL

Extended Interrecord Gap
(XIRG) Retry Limit.1
The value in this field,
taken as a 4-bitl
positive integer, specifies the number of timesl
the controller will attempt to write a bufferedl
record
before
aborting
buffered
Writel
operation. A retry with XIRG consists of al
backspace over the faulty record, an erase ofl
3.5 inches of tape,
then a write of thel
buffered record
(from RAM). An XIRG retry isl
attempted once after the Non-XIRG retry limitl
has been reached; then, if still not successfull
another
series
of
non-XIRG
retries
isl
attempted. The total number of retries allowedl
on any record is therefore the Non-XIRG Limitl
times the XIRG Limit. This field has meaning I
only if write buffering is enabled and bit 7, I
RTY, is set.
I

11-8

NXGRL

Non-Extended Interrecord Gap Retry Limit. The
value in this field, taken as a 4-bit positive
integer, specifies the number of times the
controller will attempt to write a buffered
record without generating an
extended IRG
before attempting a
retry with an extended
IRG. A retry without an XIRG consists of a
backspace over the faulty record, then a write
of the buffered record (from RAM); no special
erase is performed. This field has meaning only
if write buffering is enabled and bit 7, RTY,
is set.

3-67

Table 3-18 Extended Characteristics
Data Word Bit Definitions (Cont)

Bit

Name

Description

RTY

Retry Algorithm Control. When this bit is 0 and
the controller is Write buffering, the default
Retry algorithm
(1 backspace then write with
extended IRG, up to 10 times) is used when a
record cannot be successfully written onto
tape. When this bit is 1, the retry limits in
bits 8-15 are used.

HSP

High-Speed Select. When this bit is 0, the
transport operates at a tape speed of 25 inches
per second. When 1, the transport operates at
100 inches per second.

4,3

BUF
CTL

Buffering
Mode
Control. This 2-bit field
controls
the
read
and
write
buffering
capabilities of the controller. The codes are
defined as follows:
Bit Bit
4
3

Function
Buffering is enabled or disable via
the switch setting on the module.
This is the default condition.

1
1

2-0

USEL

No buffering is performed; the switch
is ignored.
Enable Read buffering only; the switch
is ignored.

Enable both Read and Write buffering;
the switch is ignored.

Unit Select. This field selects a transport for
subsequent tape operations. Initialize always
sets the unit selection to 0.

3-68

3.3.4.5 Write Command -- Figure 3-23 illustrates the command
packet for a Write. There are two normal modes of operation:
Write Data and Write Data Retry.
The allowable Mode field codes and their functions are:
Mode

Function

0000

Write Data

0010

Write Data Retry
Erase, Write Data)

(Space

Reverse,

15 14 13 12 11 10
4
2
1
7
6
0
3
9
S
5
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
ICtllDevice Dep.1
Mode
I Format 1 I
Command
I

I•••I•••••••••••I ••••. . •••••. •••I•••. •••••••I••••••••••••••. ••••I
IACKICvC 0 SWBI 0
m
m
m lIE
0
0 I 0
0
1
0
1 I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
LOW-ORDER
I
A001
IA15
BUFFER ADDRESS
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
HIGH ORDER
I
I
I
0 IA2l
AlSIAl7 A161
I 0
BUFFER ADDRESS
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
BUFFER EXTENT (Byte Count)
I
I
(16-Bit positive Integer)
I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-23

Write Command Packet

The command packet for a Write contains four words: a header word,
two words specifying the address of the data buffer in CPU memory
space where the data to be written onto tape is stored, and a
Buffer Extent (Byte Count) word specifying the number of bytes
available in the data buffer and the number of bytes to be written
onto tape.
A byte count of 0 specifies that 65,536 (64K) bytes
are to be written.
The third word in the packet specifies the high-order address bits
of the starting address of the data buffer.
When the Extended
Features option is disabled (i.e., the TSV05 is running in TSII
compatibility mode), only the two low-order bits (A17 and A16) may
be nonzero; these bits, together with the 16 bits in the second
word of the packet allow an IS-bit memory address to be specified
for the start of the data buffer.
In this case, if any of bi ts
2-15 are nonzero, the function will not be performed but will
terminate with a Function Reject with Illegal Address (ILA) error
status. When the Extended Features mode is enabled, the low-order
6 bi ts of the third word are used to specify bi ts A21-A16 of a
22-bit memory address.
In this mode, if any of bits 6-15 in the
third word are nonzero, the command is aborted with Function
Reject termination with Illegal Address (ILA) error status.
3-69

Fo r any of the Wr i te modes, the Swap Bytes (SWB) bit in
command header word controls the fetching of bytes from
memory, as shown in Figure 3-19.

the
CPU

If a Write command is executed at or beyond the EaT marker, the
data will be written but a Tape Status Alert (TSA) termination
will occur.
EaT will remain set until passed in the reverse
direction.
If a Write Data command is issued while the tape is positioned at
BOT, the PE identification burst (IDB) will be written onto the
tape.
This should clear the Density Check (DCK) status bit if it
was set.
If DCK did not clear, the transport is faul ty.
If any
Wri te command is issued wi th the DCK bi t set and the tape not
positioned at BOT, no data will be written and Tape position Lost
termination will occur. If a Write Retry command is issued while
the tape is positioned at BOT, a Function Reject termination will
occur, wi th the Nonexecutable Function (NEF) error bi t set in
XSTr3.
During Writes, the controller generates a parity bit for each data
byte sent to the transport; the transport then wr i tes this bi t
along with the data byte onto tape.
During the write, the
transport also reads the written bytes from tape and checks the
parity; the data is also sent to the controller, which also checks
the parity.
Therefore, two types of data errors can arise during
a write: a correctable error or an uncorrectable error. In either
case, the CPU should immediately issue a Wri te Retry command to
rewrite the data correctly.
3.3.4.6 Position Command -- Figure 3-24 illustrates the Position
command packet. This command causes tape to space records forward
or reverse, skip tape marks forward or reverse, or to rewind to
BOT. The tape-mark/record count is the second word of the command
packet. This word is ignored for a Rewind command.
The allowable Mode field codes and their functions are:
Mode

Function

13131313

Space Records Forward

1313131

Space Records Reverse

1313113

Skip Tape Marks Forward

131311

Skip Tape Marks Reverse

1311313

Rewind (Record Count Ignored)

3-713

15 14 13 12 11 10
9
8
7
6
4
3
2
1
5
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
ICtllDevice Dep.1
Mode
I Format 1 I
Command
I

I•••I•••••••••••I ••••••••••••••• I•••••••••••I••••••••••••••••••• I
IACKICVC 0
0 10m
m
milE
0
0 I 0
1
0
0
0 I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
I
TAPE MARK/RECORD COUNT
I
I
(16-Bit positive Integer)
I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-24

Position Command Packet

The Space Records operation skips over the number of records
specified in the Record Count word of the command packet.
However, the operation automatically terminates, with a Tape
Status Alert termination code, when a tape mark is traversed. (The
Tape Mark is included in the record count.) Also, the Record
Length Short (RLS) status bit in XST0 will be set if the record
count is not decremented to zero.
A Skip Tape Marks command will skip over the number of tape marks
specified in the Tape Mark Count word of the command packet.
However, the operation will be automatically terminated if a
double tape mark (two contiguous tape marks wi thout intervening
data) are encountered and the Enable Skip Stop (ESS) bit was set
in the Characteristic Mode word on the last Write Characteristics
command.
Termination will also occur if a tape mark is the first
record off of BOT and ESS and ENB bits are set in the
Characteristic Mode word. Record Length Short (RLS) is set if the
Tape Mark count is not decremented to zero.
A Space Records Reverse or Skip Tape Marks Reverse which runs into
BOT sets the Reverse Into BOT (RIB) status bit and causes a Tape
Status Alert Termination.
If one of these reverse commands is
issued while the tape is already positioned at BOT, the
Nonexecutable Function (NEF) error bi t will be set and Function
Reject termination given; in this case, the tape will not move.
If the Density Check (DCK) error is present when a position
command is issued, the DCK bit is set, but the operation is not
stopped. It will terminate with Tape Status Alert. This
allows
tapes with a bad lOB area to be read.
When a Rewind command is issued, the interrupt (if enabled) will
not occur until the tape reaches BOT and has stopped.

3-71

3.3.4.7 Format Command
Figure 3-25 illustrates the Format
command packet. Note that the second word is present (fetched by
the controller) but is not used in the command.
This command can
write a tape mark, rewrite a tape mark, or erase tape.
The allowable Mode field codes and their functions are:
Mode

Function

0000

Write Tape Mark

0001

Erase

0010

Write Tape Mark Retry (Space Reverse,
Erase, Write Tape Mark)

15 14 13 12 11 10
4
3
2
1
8
7
6
9
5
0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
ICtllDevice Dep.1
Mode
I Format 1 I
Command
I

I •••I •••••••••••I•••••••••••••••I •••••••••••I••••••••••••••••••• I
IACKICVC 0
0 10m
m
milE
0
0 I 0
1
0
0
I I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

I
(Not Used)
I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-25

Format Command Packet

In all cases, executing a Format command at or beyond EOT will
cause a Tape Status Alert termination.
The EOT bit will remain
set until the EOT marker is passed in the reverse direction.
A Write Tape Mark or Erase command issued at BOT will
automatically cause the PE Identification Burst (IDB)
to be
written on the tape.
If, during this operation, the IDB is not
received from the transport (i.e., there is a transport or cable
problem), the Densi ty Check (DCK) error will be set and Tape
Position Lost termination will occur.
If the Density Check bit is already set and the tape is not at
BOT, a
Format command will be aborted with Tape Position Lost
termination; the tape will not move.
The Wri te Tape Mark command causes approximately 3.75 inches of
The Erase
tape to be erased and a file mark to be written.
erased.
command merely causes 3.75 inches of tape to be
Successive Erase commands can be used to erase more than 3.75
inches (3.75-inch increments).

3-72

The Write Tape Mark Retry command causes a space reverse (over the
previous record), followed by an erase of 3.75 inches of tape,
followed by a Write Tape Mark (which erases 3.75 more inches of
tape before writing the file mark).
If the tape is positioned at
BOT when the Write Tape Mark Retry command is issued, the
operation will be aborted with Function Reject termination and the
Nonexecutable Function (NEF) error bit will be set.
3.3.4.8 Control Command -- Figure 3-26 illustrates the Control
command packet. The are three normal modes (Message Buffer
Release, Rewind and Unload, and NO-OP) and one addi tional mode,
(Rewind with Immediate Interrupt).
The Control command is
characterized by the fact that termination (and an interrupt if
the IE bit is set) occurs immediately at the start of the command.
The allowable Mode field codes and their functions are:
Mode

Function

frHHH~

Message Buffer Release

'HHH

Rewind and Unload

00Hl

NO-OP (Performs Clean Tape
function in TSll)

0100

Rewind with Immediate Interrupt

1
15 14 13 12 11 10
6
4
3
2
0
9
8
7
5
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
ICtllDevice Dep.1
Mode
I Format 1 I
Command
I

I••• I•••••••••••I•••••••••••••••I•••••••••••I••••••••••••••••••• I
IACKICVC 0
0 10m
m
m lIE
0
0 I 0
1
0
1
0 I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

I
(Not Used)
I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-26

Control Command Packet

The Message Buffer Release command, when executed with the ACK bit
set, allows the controller to own the Message Buffer so it can
update the status in the message buffer area on an
Attention
(ATTN). This would be used when the CPU is not operating the TSV05
for a period of time but desires to be notified of a change in
status or a microdiagnostic error.

3-73

The Rewind and Unload command rewinds the tape completely onto the
supply reel and places the transport in the Off-Line state. When
this command 5s executed, termi~ation (and an interrupt if IE is
set) will occ'u immediately.
When the NO-OP command is issued, normal termination will occur
immediately and no tape motion will result.
The Rewind with Immediate Interrupt command causes the tape to be
rewound to BOT.
This command differs from the normal Rewind
command in that termination response to the CPU occurs at the
start of the rewind rather than when the tape reaches BOT.
This
command would therefore be used in a multi-transport system when
it is desired to select another unit after issuing a rewind.
If a
transport is rewinding and another tape motion command is issued
to it, the new controller will wait until the tape has been
rewound to BOT before proceeding with the new command. During
execution of a Rewind with Immediate Interrupt, the Motion (MOT)
bit in XST0 will be set if a Get Status command is performed.
3.3.4.9 Initialize Command
Figure 3-27 illustrates the
Initialize command packet.
If there are no microdiagnostic
errors, this command is treated as a NO-OP.
If there are errors
present, however, the command performs the same as a wr i te into
the TSSR register.
In either case, IFEN to the Tape Transport is
pulsed to stop runaway commands.
15 14 13 12 11 10
6
2
1
9
8
7
4
3
5
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
ICtllDevice Dep.1
Mode
I Format 1 I
Command
I

I •• • t••••• •••••• I ••••••••••••• • •I ••• ••••• •• •I ••• •• ••••• ••• ••••• • I
IACKICVC 0
(i} lIE
(i} I 0
1
1
010
1 I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

I
(Not Used)
I
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Figure 3-27

Initialize Command Packet

3.3.4.10 Write Subsystem Memory Command -- This command is used
for the diagnostic programs, and is not applicable to programming
for normal operations.

3-74

3.3.5 Record Buffering
The Record Buffering mode of operation can be invoked to optimize
system performance when performing Read and Write operations on a
"streaming" tape transport.
The technique causes tape records to
be "cached" (buffered) in the controller in order to avoid many of
the long repositioning delays frequently encountered when dealing
with a streaming tape transport.
Repositioning occurs if the
transport does not receive its next command before the reinstruct
period expi res.
On a typical system, the chances are high that,
in a non-buffering mode, the software will miss the reinstruct
period (e.g., data to be written must be transferred from a disk,
or data read must be transferred to a disk, etc.) since the
software cannot always keep the transport busy.
Buffering is a
mean~ to decrease the number of repositionings while transferring
a file of sequential records.
The effect of buffering serves to
lengthen the apparent reinstruct period (as seen from the CPU)
since tape data transfers can be overlapped with the CPU
operations required to prepare for issuing the next command to the
tape subsystem.
Read buffering causes an additional record to be read from tape in
response to a program requesting just one.
Typically, a program
requests several records in succession, so a record stored in the
controller will be available for immediate transfer to the CPU and
can be transferred while another record is being read or the tape
is repositioning.
Only the Read Next command (e.g., a forward
read) causes the buffering algorithm to be invoked.
Wri te buffering allows one record to be accumulated wi thin the
controller and subsequently written to tape, allowing transfer of
data from CPU memory to controller to be overlapped wi th tape
repositioning.
This also allows the CPU to prepare and issue the
next Wri te command while the previous (stored) record is being
wri tten to tape.
Therefore, there can be two records ready for
transfer. One in the controller and one in CPU memory.
Record Buffering is enabled either by software or hardware. If the
Extended Features switch is set, it can be enabled or disabled via
the "extra" (5th) Characteristics Data word. If Extended Features
is off, it is enabled or disabled only by the Buffering Enable
switch. The following paragraphs describe the operations performed
for Read and Write buffering.
3.3.5.1 Read Buffering -- Assuming that the transport is ready
for an operation (On-Line, etc.), the following occurs when a Read
Next (Forward) command is issued to the controller and buffering
is enabled:

3-75

When a Read Next command is issued, the tape is started
and data is transferred from tape to CPU memory in the
normal fashion.

When the final byte of data from the tape has been
transferred to CPU memory and the transport has negated
the DATA BUSY signal, the controller tests the Status
inputs from the Transport Bus and determines if any errors
or special incidents occurred.

If an error occurred, or if a Tape Mark was read, or if
the tape is beyond the EDT marker, the controller will
terminate the operation by issuing the appropriate status
message and will not automatically issue another command
to the transport. The controller wi 11 return to its Idle
state (before Step 1) and the transport will be allowed to
complete its sequence.

If the transfer completed without incident, the controller
will issue its normal Successful termination message. The
program in the CPU can then act on this message (i.e.,
begin transfer of the data to disk, etc.).

If the transfer completed without incident, and if the
record just read was 3. 5K bytes or less in length (e.g.,
could fit entirely
within the controller's RAM), the
controller will issue another Read Forward command to the
transport and read the next record from tape and store the
data in its internal RAM (up to 3.5K bytes of data). This
operation can be termed "pre-reading".

When the next record has been read, or if an "incident"
occurs (Tape Mark, EDT, or error), whichever occurs first,
the tape drive will be allowed to stop. In addition, if,
during a pre-read, data on tape is not encountered within
1 second, the pre-read will be aborted and the tape
allowed to stop, since there may be no more data on the
tape; if this is the case and a Read Next is eventually
issued for this nonexistent record, the operation will
terminate wi th an DPI error after 25 feet of tape have
been passed without encountering data.

While the controller is pre-reading the next record, it is
moni toring the LSI-II Bus Interface for the next comma,nd
from the CPU.

If the next command is Read Next, the controller
immediately begins transferring the pre-read data record
from RAM to CPU memory (this transfer can be performed
during the pre-read of data from tape).

3-76

When the pre-read record has been transferred entirely to
CPU memory, the controller issues another Read command to
the transport and the cycle repeats.

1".

If additional sequential Read Next commands are issued,
data is supplied from the RAM until its contents are
exhausted.
The cycle then repeats from Step 1 if another
Read Next is issued.

11.

If an End of File mark is encountered on tape, or if any
errors occur, pre-reading of records ceases. If errors
occur, the controller spaces one record reverse (only if
the 25-foot timer did not abort on the pre-read.) The tape
will be log icall y posi tioned just before the record of
incident. If and when a Read command is received from the
CPU'to read a record, normal read operation will occur. If
the 25-foot timer expired from the previous pre-read, Tape
Posi tion Lost will be reported in response to this read
command.
If an End of Fi Ie mark is encountered on tape,
the controller records this, and does not move the tape.
The next command handles the File Mark appropriately.

12.

If any command other than a Read Next is issued by the
CPU, and if the controller RAM still contains a pre-read
record, the new command is stored internally (so that
action may eventually be taken) and the controller
performs a recovery action as follows:

If a record is currently being
controller allows the operation
transport to negate Data Busy.

If the new command is a Space Records (either forward
or reverse), the current tape posi tion is compared
wi th the tape posi tion assumed by the CPU program
(based upon the last record transferred to CPU
memory). The controller recomputes the recordcount
required to reach the final target position and enters
the normal Space Forward or Space Reverse sequence,
using the new record count.

If the new command is a Rewind or Rewind/Unload, the
rewind sequence is immediately performed; no further
adj ustment in tape posi tion is required.

If the new command is a Skip Tape Marks, the
controller determines if it contains an outstanding
pre-read file mark and recomputes the skip count.
If
there is no pre-read file mark, no adjustment is
necessary. If one exists, the count as supplied by the
CPU is adj usted by one (plus or minus). The normal
skip sequence is then entered.

3-77

read from tape,
to complete and

the
the

13.

If th~ new command is other than those listed above,
the controller reposi tions the tape by skipping one
record in reverse (to space back over the pre-read
record outstanding) before executing the new command.

If, during pre-reading, data from the current tape record
will not fit into the space currently available in RAM,
the tape operation is aborted and the controller directs
the transport to space reverse in order to recover proper
tape position.
The controller does not attempt to
pre-read the record that was aborted.

3.3.5.2 Write Buffering -- Record Write Buffering allows the CPU
to issue successive Wri te Data commands to the controller, wi th
the controller storing one record up to 3. 5K bytes in length in
its RAM.
When a Write Data command is first received, a "fetch
from memory" process is started to transfer data from CPU memory
to the controller RAM.
Then, when at least one byte of data is
available in RAM, the tape transport is directed to write and an
"output to tape" process is started to transfer data from the RAM
to the FIFO.
These processes are rela ti vely independent, wi th a
supervisory loop overlayed to keep track of RAM buffer management
and abnormal conditions.
Ini tially, the tape is probably at rest or in a reposi tioning
cycle. Therefore, the "access time" (the time elapsed since the
controller commanded the transport to write, and the time when the
fi rst character was strobed out of the FIFO and wri tten onto
tape), is relatively long.
During this time, another Write Data
command can be accepted from the CPU (but not given a termination
response), wi th the associated data held in CPU memory. When in
buffering mode, a Successful termination status is given to the
CPU as soon as a record has been transferred completely from CPU
memory to RAM, thereby allowing the CPU to issue another Write
Next command.
It is therefore possible that the "output to tape"
process is one record behind the "accept new command" process.
The overall effect is to allow the 'CPU to overlap the preparation
of one record wi th the wri ting to tape of the previous record,
allowing the controller to command the transport to write within
its reinstruct time.
If a record is specified to be greater than 3.5K bytes (the amount
of RAM allocated for buffering), the record is handled in the
non-buffered mode: termination status is not given to the CPU
until the record has been written entirely onto the tape or an
error occurs.

3-78

When writing a record that is not associated with the current
command (last issued by the CPU), the controller performs an
automatic error recovery (retry) procedure (space reverse, erase,
then write forward) up to 10 times.
Hence the necessity for a
record to reside completely within the RAM when buffering. If the
Extended Features swi tch on the M7196 is set, the extra (5th)
Characteristics Data word can specify the number of retries (from
o up to 15) and can specify that a long gap should not be
generated on an automatic retry (the Erase function is eliminated
from the recovery sequence).
During the Write Buffering mode of operation, the controller reads
a block of data into its RAM from CPU memory then responds to the
CPU with a normal successful completion status. As far as the CPU
software is concerned, then, the record was written on tape
successfully.
The controller must therefore take all the steps
possible to eventually write that record onto the tape. Hence the
need automatic retries.
Write buffering is a more complex
operation than Read buffering because of these retries.
Furthermore, should the worst occur and the controller cannot
wri te a buffered record, the CPU program will not know exactly
which record failed to be written (the program could conceivably
bel ieve that a record was wri tten properly when in fact it was
not).
For this reason, a Tape Position Lost error termination is
given for the next Tape Motion command issued by the CPU if a
buffered record cannot be successfully written.
In addition, if a
buffered record is successfully wri tte"n after retries, the CPU
will have no way of logging the fact that some trouble was
encountered.
Because of the potential difficulties described above, the
controller implements an adaptive buffering algorithm.
In this
algor i thm, the first Wr i te Data command following any type of
command other than a Write Next or Write File Mark is handled in a
non-buffered mode: termination status is not returned to the CPU
until the actual wri te-to-tape operation is complete.
If the
record was written without
error, then subsequent Write Data
commands will cause buffering of the data.
If an error occurred
on this first record, the CPU can take its normal error logging
and recovery procedures. Buffering will not be enabled again until
a successful record is written without retries.
Assuming that the transport is wri te-enab1ed and ready for an
operation, the following occurs when a 'Write Data command is
issued by the CPU and buffering is enabled (but not currently
activated by having just completed a successful Write Data or
Write Tape Mark):
1.

When the Write is received by the TSV05, the controller
issues a Wri te Command to the Tape Transport, and beg ins
transferring the associated data from CPU memory to RAM.

3-79

As soon as the first
transferred to the FIFO.

word

The previously issued Write command to the transport will
eventually beg in emptying the FIFO and wr i ting the data
onto tape.

Meanwhile, the transfer from CPU memory to RAM continues
as long as there is room in the RAM; the transfer from RAM
to FIFO continues as long as there is room in the FIFO.

Since this is the first Wri te, it is being handled in a
non-buffered mode so the "memory to RAM" process is
allowed to overwri te a RAM byte that has already been
transferred to the FIFO. The RAM management algorithm has
the capability of suspending transfers either into or out
of the
RAM so that bytes not already transferred to the
FIFO do not get overwritten, and so that the FIFO receives
only valid bytes. (The RAM is handled as a circular
buffer.)

When the final byte of data associated wi th this command
has been written onto the tape and the transport has
negated DATA BUSY, the controller tests the Status inputs
from the transport bus and also its internal status (i.e.,
FIFO overrun) for errors or exceptional conditions.

If an error occurred or EOT was seen, the controller will
terminate the operation by issuing the appropriate status
message and will not enable itself for write buffering.
The controller reverts to its Idle state (before Step 1)
with buffering deactivated.

If the transfer completed without incident, a normal
successful termination message will be issued and the
controller will enable itself for buffering of future
Write commands.

If the next command is indeed a Write Data, operation
proceeds as in Steps 1 through 4 above. However, when all
the required data has been transferred from CPU memory to
RAM, and if the record will fit entirely in RAM, and if no
exceptional condition has yet occurred, the controller
will issue normal successful termination status to the
CPU. As far as the CPU is concerned, the record has been
wri tten onto the tape, although this is not really the
case.

3-8(3

appears

RAM,

10.

The controller continues transferring data from RAM to
FIFO until the record it is currently transferring has
been completel y wri tten onto tape. If the transfer is
successful, the record is purged from the RAM, freeing its
space for another record from the CPU. In addi tion, if no
incident has occurred wi th the transfer, the controller
will accept another Write Data command from the CPU and
begin transferring data into the RAM.

11.

As long as no errors are encountered, another
co mm and will con tin u e to be accepted and the
previous steps repeated.

12.

If an error occurs, the controller enters its retry
algorithm to attempt to successfully write the current
record (space reverse, possibly erase forward, and rewrite
the record using data stored in RAM). Statistics are kept
as to the number of retries completed. If, after the
specified number of retries (10 is the default), the
record cannot be successfully written, operation is
aborted and an error message (Tape position Lost) is
issued to the CPU
(if possible) as follows:
a.

13.

14.

Write
three

Tape Posi tion Lost status will be issued on the next
motion type command received by the controller.

Assume an error occurs and the record can be successfully
written within the retry constraints. If a Write command
was currently pending (termination status not yet issued
to the CPU) when the recoverable error occurred, it is
then allowed to complete in the normal unbuffered fashion
(so the CPU can log any errors). If this record is
successfully written, buffering will again be enabled and
will wait for the next command at Step 9. If the record
required retries by the CPU, the controller will then
return to its Idle mode (before Step 1), causing the next
Write command to be handled in the unbuffered mode.
If, during the normal sequence of processing sequential
Write commands, buffering the records, and writing them to
tape, a Tape Motion command other than Write Data is
encountered, the RAM is purged (a stored record written to
tape) befo re the new command is
processed. Wr i te
Buffering is disabled until a successful Wr i te Command.
Therefore, after this new command is processed and its
termination status issued, the tape is positioned as
expected by the user and all outstanding conditions
reconciled.

3-81

15.

Similarly, if a Write Next command specifying a record
larger than 3.5K bytes is processed, this command will be
handled in the unbuffered fashion, but will allow
buffering to be attempted if the very next command is
Write Next.
NOTE
Ini tialization (Bus INIT or a wri te into TSSR)
should be avoided, since it purges the RAM and
current status. When this is done, it is possible
to lose a record that the user might asume was
properly written.

3-82

APPENDIX A
CONFIGURATION DATA

(
E122
______ THESE 14 ROMS ARE FACTORY
INSTALLED AND SHOULD NOT
BE REMOVED.

VECTOR SWITCH PACK

rr(WS
ADDRESS

SWITCH~

El0S

VECTOR SWITCHPACK
1

O~: vsl V71 v61 Vsl v41 v31 v21 Sl

A121 ESS

I I

ADDRESS SWITCH PACK
1

o~:1 All1Al01 Asl Asl A71 A61 Asl A41 A31 A21 ES7
V = VECTOR BIT
A = ADDRESS BIT

Sl = BUFFERING
SO
EXTENDED FEATURES

JUMPERS
Wl
W2
W3
W4
WS
W6

AS SHIPPED
BIRQS
BIRQ7
BIRQ6
BUS GRANT CONTINUITY
BUS GRANT CONTINUITY
SCLOCK ENABLE (USED DURING FACTORY REPAIR ONLY)

OUT
OUT
OUT
IN
IN
IN
CS-2450

Figure A-I

M7I96 Switch and Jumper Identification

A-I

M7196 VECTOR AND ADDRESS SWITCHES

1 0 1 0 1 0 11 1 0 1 0 11 1 0 11 1

o 1 0 I BDAL BIT

POSITION

IIIIIIII

STANDARD VECTOR
CONFIGURATION
(224)

OFF

VECTOR

~~ITCH

OFF OFF

OFF

OFF OFF

II I I I I I I I I I I I I I I I
2 13

: ~6

( 10

ON
STANDARD ADDRESS
CONFIGURATION
(172520)
1 1 1 2 1 3 1 4

1 6 1 7 I 8 1 9 1 10 1~::g~s

1 5

I I I I I I I I I I

SO
S1

L-~

OFF

ON OFF

~~~~

OFF

~~~~

OFF OFF

L-~

E57

BDAL BIT
POSITION

= EXTENDED FEATURES
= BUFFERING
CS-;l468

Figure A-2

M7196 vector and Address Switches

A-2

TAPE TRANSPORT
UNIT SELECT
SWITCH

TERMINATOR *
SOCKET

*NOTE: THE LAST (OR ONLY) TRANSPORT ON THE
BUS MUST HAVE THESE TWO DIP RESISTOR
PACKS INSTALLED. OTHER JUMPERS WITHIN
THE TRANSPORT ARE FACTORY-CONFIGURED
AND $HOULD NOT BE CHANGED. JUMPER
CONFIGURATION VARIES FROM BOARD TO
BOARD, DEPENDING ON THE EPROM TYPES IN
USE. HOWEVER, THIS DOES NOT AFFECT THE
INTERCHANGEABILITY OF THE BOARD.

CS-2451

TAPE TRANSPORT UNIT SELECT SWITCH
OFF

UNIT SEL 0

220/

/33011

Ul0W

UNIT SEL 1

SPECIAL IRG

UNIT SEL 2

EXT PARITY SEL

INT PARITY GEN

RESERVED

o
220/

/33011

U3W

U8W

Figure A-3

Transport Switch and Terminator Identification

A-3

APPENDIX 8
MANUAL LOADING

If the autoloading routine does not successfully load the tape,
the manual loading procedure may be used. Refer to Figure 8-1 and
proceed as follows:
1.

Switch off the tape transport power.

Raise the cabinet top cover by grasping the handle on the
top cover and lifting.
When the top cover is raised far
enough, the support arm latches to keep the cover up.

Raise the top cover of the tape transport unit by reaching
in through the front panel door and pushing upward on the
front of the top cover.

Ensure that there are no foreign objects in the tape path.

Place the reel of tape on the supply hub.
Ensure that it
is evenly seated on the hub, and then clo se the front
door.

Thread the tape along the tape path as shown in Figure
8-2. Carefully move the tachometer assembly away from the
takeup hub and wrap the tape clockwi se around the hub.
Wrap the tape just short of one complete turn.
Note that
the tape should not overwind at thi s point (i.e., there
should be a short section of the takeup hub that ha s no
tape on it yet) •

Gently move the tachometer assembly back against the hub.
(The tape should pass between the tachometer and the
takeup hub.)

Check that the tape is seated correctly on the guides and
threaded properly over the head assembly.
Remove any excess slack by gently turning the supply reel counterclockwi see

Turn the takeup hub clockwise to wrap two additional turns
of tape on the hub.
Ensure that the tape does not ride up
and extend over the top surface of the hub.

l~.

Close the top covers of the tape transport and the cabinet.

11. Switch on the tape transport power.
,12. Press ENTER, with ENTER depressed, press LOAD.
When the
LOAD i nd icator stops bl inking, the tape is loaded and
ready to be switched on-line.

8-1

CABINET TOP
COVER SUPPORT

CS-2444

Figure 8-1

Accessing the Tape Path Area

8-2

CS-2467

Figure 8-2

Tape Threading path

8-3

APPENDIX C
SUMMARY OF KNOWN DIFFERENCES

The following list describes the known programming differences
between the TSll/TS04 Magtape Subsystem and the TSV05 Magtape
Subsystem, with the TSV05 in "TSll Compatibility" mode (Extended
Features switch off and record buffering disabled).
1.

In the TSV05, control logic resides in the M7l96
Controller/Interface module (allowing non-tape-motion
commands to be executed wi th the transport power of f) ,
whereas in the TSll, control log ic resides in the tape
dr ive (preventing any commands from being executed wi th
tape drive power off).

TSDB/TSBA Data Wraparound Maintenance Functions:
The
TSV05 uses (wraps around into the TSBA) only the byte that
was wri tten into TSBD, whereas the RSll wraps around both
bytes from the bus (the contents of the byte not
specifically written is not always known, since it varies
with CPU type).
In addition, a word-write maintenance
function is defined for TSBD that is not available in the
TSll.

TSSR Register:
Bit 14 and 13 have differing meanings
between the two subsystems.
On the TS-ll, bit 14
indicates a Unibus parity Error (UPE) , while in the TSV05
it is not used.
On the TSll, bit 13 indicates Serial Bus
parity Error (SPE) , while on the TSV05 it indicates a
Sanity Check Error (SCE), an error detected by the
controller in its RAM while performing Micro Diagnostics.

TSSR Register:
In the TSV05, this register is also used
to indicate self-test errors detected upon initialization.

Extended Status Register 1 (XST1):
Bits 12-9, 7-2 and 0
are not used by the TSV05 and always appear as 0, while in
the TSll these bits detail the cause certain errors on a
tape motion command.
This detail is not presently
available from the TS05 tape transport used in the TSV05
subsytem.

Extended Status Register 1 (XST1):
Bit 8 is not used on
the TSll, while on the TSV05 it indicates a parity error
detected on the Read Data lines from the transport.

Extended Status Register 2 (XST2):
Bit 14 on the TSll
indicates I/O Silo Parity error (SIP), while on the TSV05
it indicates a RAM Checksum Error (RCE).

C-l

Extended Status Register 2 (XST2):
Bits 13, 12, and 8 are
not used on the TSV05, while on the TSll these bits
indicate Serial Bus parity Error at Drive (BPE), Capstan
Acceleration Fail (CAF), and Dead Track parity (DTP).

Ex tended Status Reg ister 2 (XST2):
Bi ts 7-0, on a tape
motion command, on the TS11 indicate tracks which when
dead, while on the TSV05 this information is not available
from the TS05 transport.

10.

Extended Status Register 2 (XST2):
Bits 7-0, on a write
Characteristics command, indicate the microcode revision
level on both machines.
In addition, the TSV05 indicates
the settings of the extended features enable swi tch (bi t
7) and the buffering enable switch (bit 6).
On commands
other than wr i te character istics the TSV05 displays the
uni t number of the currentl y selected transport in bi ts
2-0.

11.

Extended Status Reg ister 2 (XST2):
Bi ts 7-0, on a Get
Status command, on the TS11 indicate the "residual capstan
tick count, while on the TSV05 this information is not
available from the TS05 transport.

12.

Extended Status Register 3 (XST3):
the TSV05, while on the TS11 it
Limit Exceeded (LMX).

13.

Bit 4 on the TS11 is
Ex tended Status Reg ister 3 (XST3):
to report Capstan Response Failure (CRF), while on the
TSV05 it is not used.

14.

Ex tended Status Reg ister 3 (XST3):
Bi ts 2 and 1 are not
used on the TSV05, while on the TS11 these are used to
indicate a Noise Record
(NOI)
and Limit Exceeded
Statically (LXS), respectively.

15.

The Clean Tape
does not move.

16.

The Write Subsystem Memory Command
between two machines.

17.

Tape speeds, and therefo re data transfer rates,
45 ips for the TS1l, and 25 ips for the TSV05.

18.

Data access characteristics
Stop/Start tape drive and
(Streaming) tape drive.

Bi t 7 is not used on
indicates Tension Arm

is handled as a NO-OP in the

C-2

TSV05i

tape

is entirely different
di ffer :

differ, since TS11 uses a
TSV05 uses a Reel-to-Reel

TSV05 TAPE TRANSPORT SUBSYSTEM USER'S GUIDE
EK-TSV05-UG-001

Reader's Comments

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our publications.
What is your general reaction to this manual? In your judgement is it complete. accurate. well organized.
well written. etc? Is it easy to use? _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

What features are most useful? _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

What faults or errors have you found in the manual? _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Does this manual satisfy the need you think it was intended to satisfy?_ _ _ _ _ _ _ _ _ _ _ _ __
Does it satisfy your needs? _ _ _ _ _ _ _ _ __

Why? ______________________

Please send me the current copy of the Technical Documentation Catalog. which contains information
on the remainder of DIGITAL's technical documentation.

Name ____________________ Street _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
Title _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Company _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___ State/Country _ _ _ _ _ _ _ _ _ _ _ _ ___
Zip _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Department _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

Additional copies of this document are available from:

Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01532
Attention: Printing and Circulation Services (NR2/M15)
Customer Services Section

Order No,

EK-TSV05-UG-001

---------------------.~~~~------------------

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Do Not Tear - Fold Here and Staple - - - - - - - - - - - - - -

111111
BUSINESS REPLY MAIL
FIRST CLASS

PERMIT NO. 33

MERRIMACK. NH

POSTAGE WILL BE PAID BY ADDRESSEE

Digital Equipment Corporation
Educational Services/Quality Assurance
12 Crosby Drive. BU/E08
Bedford. MA 01730

No Postage
Necessary
if Mailed in th
United Statel

Digital EqUipme~tCorporation • Bedford, MA 01730