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EK-RQDX1-UG-001

January 1984

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Document:	RQDX1 Controller Module User's Guide
Order Number:	EK-RQDX1-UG
Revision:	001
Pages:	62
Original Filename:	http://bitsavers.org/pdf/dec/qbus/EK-RQDX1-UG-001.pdf

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EK-RQDX l-UG-OO 1

RQDXl
Controller Module
User's Guide

EK-RQDX l-UG-OO 1

RQOXl
Contr()lIer Module
IUser's Guide

Prepared by Educational Services
of
Digital EquipmE~nt Corporation

First Edition" January 1984

Copyright © 1984 by Digital Equipment Corporation
All Rights Reserved
Printed in U.S.A.
The material in this document is for informational purposes and is subject to change without notice; it should not be
construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document.

Notice: This equipment generates, uses, and may emit radio frequency energy. The equipment has been type tested
and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules,
which are designed to provide reasonable protection against such radio frequency interference when operated in a
commercial environment. Operation ofthis equipment in a residential area may cause interference in which case the
user at his own expense may be required to take measures to correct the interference.
The manuscript for this book was created using aD I G ITAL Word Processing System and, via a translation program,
was automatically typeset on DIGITAL's DECset Integrated Publishing System. Book production was done by
Educational Services Development and Publishing in Marlboro and Bedford, MA.
The following are trademarks of Digital Equipment Corporation.

mamaala

DEC
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DECUS
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DECSYSTEM-20
DECwriter
DIBOL
DIGITAL
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lAS
LA
LETTERPRINTER 100
LETTERWRITER 100
LSI-II
MASSBUS
MICRO/PDP-II
MINC-II
OMNIBUS
OS/8

PDP
PDT
RSTS
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TOPS-IO
TOPS-20
UNIBUS
VAX
VMS
VT

CON1'ENTS
Page

PREFACE
CHAPTER 1

INTRODUCTION

1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4

DESCRIPTION .............. " ..........................................
FEATURES ................. " .........................................
SPECIFICATIONS ............, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RQDXl Disk Controller Module. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RD51 Disk Drive ......... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RX50 Diskette Drive ...... " . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RQDXI-E Extender Module Option....... . ........... ...... ..........

CHAPTER 2

FUNCTIONAL DESCRIPTION

2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19

INTRODUCTION ............ " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
BLOCK DIAGRAM DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
SHUFFLE STEP OSCILLATOR......................................... 2-3
PHASE LOCKED LOOP ...... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-4
DATA RECOVERY .......... " ......................................... 2-5
SYNC MARK DETECTOR ... ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
SERIALIZER/DESERIALIZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-6
MFM ENCODER/PRECOMP GrENERATOR ............................. 2-6
INTERRUPT VECTOR REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-8
SA READ REGISTER, SA WRITE REGISTER, IP REGISTER. . . . . . . . . . .. 2-8
QBUS TRANSCEIVERS AND HANDSHAKE CONTROLLERS. . . . . . . . . .. 2-8
RQDXl CONTROL LOGIC ............................................. 2-10
MEMORY ADDRESS COUNTER/REGISTER ........................... 2-12
2 K X 16 RAM ......................................................... 2-12
DISK DRIVE CONTROL REGISTER AND STATUS BUFFER ............ 2-12
T-l1 RAM ADDRESS POINTER AND ALU ............................. 2-14
BIDIRECTIONAL BYTE MULTIPLEXER ............................... 2-14
8 K X 16 PROM ........................................................ 2-14
QBUS DMA POINTER AND ALU ...................................... 2-14

CHAPTER 3

CONFIGURATION AND INSTALLATION

3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.7.1
3.7.2

INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DEVICE ADDRESS SELECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LOGICAL UNIT NUMBER SELECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
INTERRUPT VECTOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
INTERRUPT REQUEST LEVEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RQDXl CONTROLLER MODULE INSTALLATION ....................
RQDXI-E EXTENDER MODULE OPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RQDXI-E Extender Module Jumper Configuration. . . . . . . . .. . . . . . . . . . . ..
RQDXI-E Extender Module Installation. . . . . . ... .. . . . . . . . . . . . . .. . . . . ..

iii

1-1
1-2
1-2
1-2
1-3
1-4
1-6

3-1
3-2
3-3
3-4
3-4
3-4
3-4
3-5
3-6

CONTENTS (Cont)
Page
CHAPTER 4

REGISTERS AND COMMANDS

4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.4
4.4.1
4.4.2

INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
REGISTERS ...........................................................
Initialize and Poll Register (IP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Status and Address Register (SA) ..............................' . . . . . ..
MASS STORAGE CONTROL PROTOCOL (MSCP) ............... " . . . . . ..
MSCP Commands .......................................... " . . . . . ..
MSCP Status Codes ......................................... " .. '. . . ..
DIAGNOSTICS AND UTILITIES PROTOCOL (DUP) ............ " . . . . . ..
DUP Commands ........................................... " .......
DUP Responses ............................................ " .......

CHAPTERS

ERROR DETECTION

5.1
5.2
5.3

INTRODUCTION ........................................ " ..... '. . . . . . .. 5-1
DIAGNOSTIC LED ERROR DISPLAYS ......................... '. . . . . . .. 5-1
DIAGNOSTIC SOFTWARE .................................... '. . . . . . .. 5-3

CHAPTER 6

DISK DRIVES

6.1
6.2
6.2.1
6.2.2
6.3

INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RD51 DISK DRIVE ....................................................
RD51 Disk Drive Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Formatting the RD51 Disk Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RX50 DISKETTE DRIVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

APPENDIX A

RQDXl CONTROLLER MODULE BACKPLANE PIN ASSIGNM:ENTS

APPENDIX B

RQDXl CONTROLLER MODULE CABLE SIGNALS

APPENDIX C

DISK DRIVE CABLE CONNECTOR PIN ASSIGNMENTS

C.1
C.2

RD51 DISK DRIVE CONNECTOR PIN ASSIGNMENTS. . . . . . . . . . . . . . . .. C-l
RX50 DISKETTE DRIVE CONNECTOR PIN ASSIGNMENTS ....' . . . . . .. C-3

4-1
4-1
4-1
4-1
4-2
4-3
4-4
4-5
4-5
4-6

6-1
6-1
6-2
6-3
6-4

FIG1JRES
Figure No.
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3
3-4
3-5
3-6
4-1
5-1
6-1
6-2
6-3
6-4
6-5
A-I

Title

Page

RQDXl Controller Module Functional Block Diagram ....................... 2-2
Shuffle Step Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
Phase Locked Loop Logic ................................................ 2-4
Data Recovery and Sync Mark D(:tector Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
Serializer/Deserializer and MFM Encoder/Precomp Generator Logic . . . . . . . . . .. 2-7
Interrupt Vector Register, SA Regiisters and QBus Interface Logic. . . . . . . . . . . . . .. 2-9
T-ll, RAM and ROM Logic .............................................. 2-10
Main High-Speed Controller Architecture ................................... 2-11
Disk Drive Control Register and Status Buffer ............................... 2-13
RQDXl Controller Module Jumpier and LED Locations ...................... 3-1
RQDXl Address Selection Jump(~r Format .. . . . . . . . . . . . . . ... . . .. . . . . . . . . . .. 3-2
RQDXl Logical Unit Number Jumper Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
RQDXl MICRO/PDP-II Signal Distribution Connections. . . . . . . . . . . . . . . . . . .. 3-4
RQDXI-E Extender Module Jumper Locations .............................. 3-5
RQDXI-E Extender Module Connections .................................. 3-6
Memory "Communications Area" Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-2
Diagnostic LED Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
RD51 Disk Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-1
RD51 Disk Drive Read/Write Printed Circuit Board. . . . . . . . . . . . . . . . . . . . . . . . .. 6-2
RD51 Disk Drive Head Positioner Flag ..................................... 6-3
RD51 Serial "Number Label Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-4
RX50 Diskette Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-5
Quad Module Contact Finger Identification ................................. A-I

TAB:LES
Table No.
1-1
3-1
3-2
3-3
4-1
4-2
4-3
5-1
5-2
6-1
A-I
B-1
C-l
C-2
C-3
C-4
C-5

Title

Page

RQDXl Controller Module Configurations.. . . . ... . . . . . . . . . .. . . . . . . . . . . . . . .. 1-1
RQDXl Standard Address Jumper Configuration... .... . . . . . . . . . . . . . . . . .. . .. 3-2
RQDXl Standard Logical Unit Number Jumper Configuration. . . . . . . . . . . . .. . .. 3-3
RQDXI-E Extender Module Jumper Configuration .......................... 3-5
MSCP Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
MSCP Status Code Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
DUP Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
Diagnostic LED Error Displays ........................................... 5-2
XXDP+ Diagnostic Programs ............................................ 5-3
DIP Shunt Jumper Configuration .......................................... 6-2
RQDXl Controller Module Backplane Pin Assignments ...................... A-2
Jl Connector Signals ..................................................... B-1
. RD51 Disk Drive J 1 Signal Conm:ctor Pin Assignments .. . . . . . . . . . . . . . . . . . . .. C-l
RD51 Disk Drive J2 Signal Conm:ctor Pin Assignments . . . . . . . . . . . . . . . . . . . . .. C-2
RD51 Disk Drive J3 Power Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . .. C-2
RX50 Diskette Drive J 1 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . .. C-3
RX50 Diskette Drive J3 Power Connector Pin Assignments . . . . . . . . . . . . . . . . . .. C-3

PREFACE

This user's guide provides information on the configuration, installation, and operation of the RQDX I disk
drive controller module, the associated disks (the RD51 Winchester fixed disk drive and the RX50
diskette drive), and the RQDXI-E extender module option.
Chapter I provides environmental and functional specifications for the RQDXI controller module, the
RD51 fixed disk drive, the RX50 diskette drive, and the RQDX I-E extender module option.
Chapter 2 gives a functional description of the RQDX I controller module.
Chapter 3 presents configuration and installation information for the RQDX I controller module and the
RQDX I-E extender module option.
Chapter 4 describes the programmable registers that are LSI-II bus addressable on the RQDX I controller
module. Mass storage control protocol (MSCP) and diagnostics and utilities protocol (DUP) are also
briefly described.
Chapter 5 provides testing and error detection information.
Chapter 6 presents installation and operation information for the RD51 fixed disk drive and the RX50
diskette drive.
RELATED DOCUMENTATION
The following documents provide additional information and may be of interest to RQDXI controller
module users.
Document Title

Document Number

RQDX I Field Maintenance Print Set
UDA50 Programmer's Documentation Kit

MP-OI731-01
QP-905-GZ

In addition, users may refer to documentation for the specific system in which the RQDXI controller
module is installed.

vii

CHAPTER 1
INTRODUCTION

1.1 DESCRIPTION
The RQDX 1 disk drive controller module interfaces, the RD5I disk and/or RX50 diskette drives to any
quad- or hex-size backplane that uses a 16-, 18-, or 22-bit LSI-II bus. The backplane must be in a
mounting box (such as a BA23) that provides a control panel and a signal distribution panel. A single
RQDX 1 module controls anyone of the configurations listed in Table 1-1.
Table 1-1
Configuration

RQDXl Controller Module Configurations
Logical Disk
Drive Numbers

Physical Disk Drives
One RD51, one RX50

Unit 0 = RD51
Unit 1, 2 = RX50

Two RX50s

Unit 0, 1 = RX50
Unit 2, 3 = RX50

Two RD51s
One RX50

Unit 0 = RD51
Unit 1 = RD51
Unit 2, 3 = RX50

Two RD51s

Unit 0 = RD51
Unit 1 = RD51

One RX50

Unit 0, 1 = RX50

One RD51

Unit 0 = RD51

These configurations require the use of the optional RQDX J-E extender module. Refer to Paragraph 3.7 for additional
RQDX J-E information.

The RD51 disk drive is a random access storage device, which uses two non removable 133.4 mm (5.25
inch) disks as storage media. The RD51 disk drive has a total formatted storage capacity of II megabytes.
The RX50 diskette drive is a random access storage device, which uses two single-sided 133.4 mm (5.25
inch) RX50K diskettes. The total storage capacity of the RX50 diskette drive is 800 kilobytes of
formatted data.
The RQDX l-E extender module option provides cable connection to a single disk or diskette that is
mounted externally from the MICRO/PDP-II (BA23) mounting box.

1-1

1.2 FEATURES
The RQDX I controller module has the following features.
•

Single quad-size module.

•

Supports DMA data transfers in 16-, 18-, or 22-bit addressing modes.

•

Supports block mode transfers with MSVII-P memories.

•

Supports 22-bit addressing on an LSI-II bus.

•

Memory parity error abort feature for use with memories that have a parity option.

•

Requires no jumper/switch reconfiguration when adding or removing RDSI or RXSO drives.

1.3 SPECIFICATIONS
1.3.1

RQDXl Disk Controller Module

Module

I quad-size module, M8639

Size

Height: 26.S6 cm (10.46 in)
Width: 1.27 cm (O.S in)
Length: 22.70 cm (8.94 in)

Power Requirements

+S Vdc ±S% at 6.4 A (typical)
8.0 A (maximum)
+12 Vdc ±S% at 7.3 rnA (typical)
10 rnA (maximum)

Bus Loads
AC Bus Loads
DC Bus Loads

2.S
I

Addressing Modes

16-, 18-, and 22-bit
(determined by user)

Limitations

The RQDX I will not fit in the
dual-height LSI-II mini-series
H9281 backplane.

Drives Per Controller

Up to four logical units, no more
than two RDSI disk drives

LSI-II Bus-Addressable
Registers

Base Device Address
(Standard)

Addressing Mode

Address (Octal)

16-bit
18-bit
22-bit

1721S0
7721S0
177721S0

1-2

Vector

Software selectable
(I\rormally set at 154)

Data Transfer Rate

800 ns/word (peak) controller to host

Environmental Specifications
Temperature
Storage
Operating

-40°C to 66°C (-40°F to 150°F)
5°C to 50°C (41°F to 122°F)

Relative Humidity
Storage
Operating

10% to 95%, noncondensing
10% to 95%, non condensing

Altitude
Storage
Operating

9.1 km (30,000 ft) maximum
2.4 km (8,000 ft) maximum

Airflow
Operating up to 50°C

t .3.2

Maximum temperature rise across
module must not exceed 20°C (68°F)
input to output.

RD5 t Disk Drive

Storage Type
Medium

Winchester fixed disk

Recording Surfaces

4 data surfaces

Magnetic Heads

4 read/write heads

Recording Method

Modified frequency modulation (MFM)

Performance Specifications
Recording Capacity
(Formatted)
Bytes Per Sector

512 bytes

Sectors Per Track

18 sectors (track size)
Each sector has a logical block
number (LBN)

Tracks Per Group

4 tracks (group size)

Groups Per Cylinder

3 groups (cylinder size)

Cylinders Per Unit

100 cylinders

Total Cylinders
Per Unit

102 cylinders *

Total Bytes Per U ni t

11.059 M bytes
5,000,000 bits/s
(625 K bytes/s)

Transfer Rate
Access Time (Buffered Seek, Including Settling)
Average

85 ms

Maximum

205 ms

A verage Latency

8.33 ms

Functional Specifications
Rotational Speed

3,600 r/min (±1 %)

Recording Density

9,074 bits/in (maximum)

Track Density

345 tracks/in

Environmental Specifications
Ambient Temperature
Relative Humidity

20% to 80% noncondensing

Maximum Wet Bulb
1.3.3

RXSO Diskette Drive

Storage Type
Medium

Diskette

Recording Surfaces

2 data surfaces

Magnetic Heads

2 read/write heads

Recording Method

Modified frequency modulation (MFM)

* Cylinders 100 and 101 are assigned as follows.
Cylinder 100, Group 0:
Cylinder 100, Groups I, 2:
Cylinder 101, Groups 0, I:
Cylinder 101, Group 2:

Replacement and caching table (RCT)
Format control table (FCT)
Replacement block numbers (RBNs)
Diagnostic block numbers (DBNs)
Reserved

1-4

Performance Specifications
Recording Capacity
(Formatted)
Bytes Per Sector

512 bytes

Sectors Per Track

10 sectors (track size)
Each sector has a logical block
number (LBN).

Tracks Per Group

5 tracks (group size)

Groups Per Cylinder

16 groups (cylinder size)

Cylinders Per Surface

1 cylinder

Bytes Per Surface

404,480 bytes

Surfaces Per Unit

2 surfaces (2 diskettes)

Bytes Per Unit

808,960 bytes

Transfer Rate

250,000 bits/s
(31.25 K bytes/s)

Access Time
Track to Track

Minimum

Typical

Maximum

6 ms

Head Settling Time

30 ms

Head Load Time

30 ms

Rotational Latency

100 ms

Random Access

264 ms
250 ms

Drive Motor Start
Functional Specifications
Rotational Speed

300 r/min (±1.5%)

Recording Density

5,576 bits/in (maximum)

Track Density

96 tracks/in

Environmental Specifications
Ambient Temperature
Relative Humidity

200 ms

20% to 80% non condensing

Maximum Wet Bulb
1-5

1.3.4

RQDXI-E Extender Module Option

Module

1 dual-size module, M7 S12

Size

Height: 13.2 cm (S.2 in)
Width: 1.27 cm (O.S in)
Length: 22.8 cm (8.9 in)

Power Requirements

+S Vdc at O.S A (typical)
0.6 A (maximum)

Bus Loads
AC Bus Loads
DC Bus Loads

o
o

Provides signal distribution to a
single disk or diskette drive

Limitations

Cannot be used on the PDP-II /23 Plus
Environmental Specifications
Temperature
Storage
Operating

-40°C to 66°C (-40°F to IS0°F)
SoC to 60°C (41°F to 140°F)

Relative Humidity
Storage
Operating

10% to 9S%, noncondensing
10% to 9S%, noncondensing

Altitude
Storage
Operating

9.1 km (30,000 ft) maximum
2.4 km (8,000 ft) maximum

Airflow
Operating up to SO°C

Maximum temperature rise across
module must not exceed 20°C
(68°F) input to output.

1-6

CHAPTER 2
FUNCTIONAL DESCRIPTION

2.1 INTRODUCTION
The RQDX I controller module interfaces the RD51 disk drive and/or RX50 diskette drives to a 16-, 18-,
or 22-bit LSI-II bus. One RQDXI controller module can support up to four logical units in any
combination of RD51 and RX50 drives (up to two RD51 drives per RQDX I controller module). The
RQDX I controller module (M8639) has the LSI-II bus transceivers and decoders, programmable registers, controller timing and sequence logic, and the data formatting circuits necessary to read and write on
lthe RD51 disk media and/or the RX50 diskette media.
:!.2 BLOCK DIAGRAM DESCRIPTION
The main functional subsections of the RQDX I module are shown on the block diagram in Figure 2-1.
The block diagram illustrates the basic architecture and the data path relationships of the major subsections. The RQDX I controller module is a bus-oriented system controlled by a system control function
shared by the T-II chip and the main high-speed controller.
The major subsections of the RQDX I are as follows.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Shuffle step oscillator
Phase locked loop
Data recovery
Sync mark detector
Serializer/ deserializer
MFM encoder/precomp generator
Interrupt vector register
SA read/write registers, IP register
QBus transceivers and handshake controlle:r
RQDX 1 control logic: T-II chip and main high-speed controller
Memory address counter/register
2 K X 16 RAM
Disk drive control register and status buffer
T -I I RAM address pointer and arithmetic logic unit (ALU)
Bidirectional byte multiplexer
8 K X 16 PROM
QBus DMA pointer and ALU

2-1

Cl-BUS

Q-BUS
CONTROL
SIGNALS

Q-BUS TRANSCEIVER
AND SATELLITE
HANDSHAKE CONTROLLERS

GO
T11
REQTlIDMA
Tll DMAACK
MICROPROCESSOR
(7_5 MHZ, 16 BIT)
1------.1
TAKE BUS

MAIN
HIGH SPEED
CONTROLLER
(100 nslSTATE)

.. CONTROL ..

tv
I
tv

SE RIALIZE R/DESER IALIZER

NRZWRITE DATA

2K x 16
STATIC RAM

MFM ENCODER AND
PRECOMPENSATION
CONTROLLER

8K x 16
EPROM

DEVICE CTl BLOCK

--------SECTOR BUFFER
WRITE DATA

DISK DRIVE

Figure 2-1

RQDX 1 Controller Module Functional Block Diagram

INIT
TIMEUP

PROGRAMMABLE
TIMER

2.3 SHUFFLE STEP OSCILLATOR
The shuffle step oscillator (Figure 2-2) is a system of two matched 10 MHz oscillators, a small asynchronous oscillator controller, and a read data delay equalizer. When one of the oscillators is generating a raw
read clock signal for the phase locked loop (PLL), the other oscillator is in stand-by. At each raw read data
pulse, the active oscillator is commanded to turn off and the stand-by oscillator is commanded to become
active. This causes the oscillators to "shuffle" to keep in step with the RAW read data. The read data
delay equalizer section delays the RAW read data to compensate for the short amount of time that it takes
to shuffle the oscillators.

'
£

SELFLOPY(H)
SELWINCH1(H)

B
A

8 TO 1 MUX
(74LS151)
RSTRDF/F(L)

RD F/F

INITDVDR(L)

DLQRDDATA(H)

10MRAWOSC(H)

Figure 2-2

Shufflle Step Oscillator

2-3

2.4

PHASE LOCKED LOOP

The phase locked loop (PLL) logic is shown in Figure 2-3. The PLL is a dual-channel, single··mode system.
Dual channel provides one channel for the RX50 diskette drive(s} and one channel for the RD51 disk
drive(s}. The function of the PLL logic is to provide the "flywheel" effect for the shuffle step oscillator
output, thus integrating the effects of the "pulse drift" in the RAW read data. The output of the PLL is
fed into a counter which generates two data recovery window signals. These "windows" are generated in a
way to center the read data pulses. (At any given time the data will be framed by one of these windows.)
The proper data framing window is selected automatically by the sync mark detector.

REFCLK(H)

PHASE DETECTOR
(74574
74564)
~

PMPUP(L)

PMPDWN(L)

ACTIVE FILTER
AND CHARGE PUMP

~~arjE;r
:

>=
CI..

(LF347)

o..J
U.

..J
W

I
I

DUAL VCO
:
WINNY

FLOPPY

DLQRDDATA(H)

(74L5626)

()

10MRAW05C(H)

20MHZVCO(L)

>
N

500KHZ05C(H)

!
1

~
0

()

2TO 1 MUX
(745157)

5ELFLOPY(H)

BITCELL

2XVCO(L)

2XVCO(H)
()

VCOOUTPUT(~~
REFCLK(H)

AWINDOW('L-J

RDDATA(H)

VCOOUTPUT(H)
MR-'1290

Figure 2-3

Phase Locked Loop Logic

2-4

2.5 DATA RECOVERY
The data recovery logic (Figure 2-4) consists of two single-bit, edge-triggered, double-buffered registers.
The registers are cross-coupled in order to capture the read data occurring anywhere within either data
framing window. Together with the phase locked loop output, an NRZ read data stream is produced.
2.6 SYNC MARK DETECTOR
The sync mark detector logic (Figure 2-4) provides two functions. One, it detects the sync mark, and, two,
it selects the proper stream from the data recovery logic. Both data recovery bit streams are analyzed to
find the sync mark. Upon detection of the sync mark in either stream, the serializer/deserializer logic
receives the desired data stream.
VCOOUTPUT(H)

»z

:0
N

--,

c~~~ !
SERLSRCLK(H)

STATE REGISTEF]

Z
:0
N

»--I

I
I

.J.A~~S~
ADRMRKFND(H)

SERLSRCLK
"vca OUTPUT"
AWINDOW
MFM _ _+-' '--~"-T--+~ 'T~-~ '--__.I.1If:_---'n

BNRZDAT
MFM

........--"--~-----L-'f-"--------'

nl.....-+-_ _ }

o ~O
0

AN RZDAT _ _ _-'

;- ~.,

n ___JI
n

_:-+--....J

BNRZDAT

~~1-'

ADF:MRKFND(H)

IS LOCKED TO
CELL BOUNDRYS
"CLOCKS"

Al
OA

in'---+---

ANRZDAT~_~~~

WHEN WINDOW

}

WHEN WINDOW
IS LOCKED TO
CELL CENTERS
"ONES"

MR-11288

Figure 2-4

Data Recovery and Sync Mark Detector Logic

2-5

2.7 SERIALIZER/DESERIALIZER
The serializer /deserializer is shown in Figure 2-5 and consists of the following four parts.
•
•
•
•

A double-buffered serial in/parallel out register
A double-buffered parallel in/serial out register
A eRe generator/checker
A high-speed finite state machine controller

The serial in/parallel out (SIPO) logic shifts the serial read data through the eRe generator and forms an
8-bit parallel byte. The byte is buffered for data transfer.
The parallel in/serial out (PISO) logic receives the parallel write data, buffers it, and shifts this data
serially through the eRe generator to the MFM encoder and precomp generator. This serial data becomes
the write data to be sent to the disk.
Both the SIPO and the PISO logic are controlled by the high-speed machine controller.
2.8 MFM ENCODER/PRECOMP GENERATOR
The MFM encoder/precomp generator logic (Figure 2-5) receives the serial data to be written to the disk
and performs the following operations.
1.

It generates a modified frequency modulation (MFM) data bit stream.

It precompensates the MFM bit stream (for both the RD51 disk drive and the RX50 diskette
drive).

It generates the sync mark bit sequence on command.

2-6

HIGH SPEED CONTROLLER

A
~

(

...J

W/R BUF FLG
(74LS74)
R

~ ;:oc
~ ~ 8a:

r
NRZRDATA (H)

-:2J: J:
~ -0'" a: t~ ~H~ ~

W/RBUFFLG (H)l

2 ~ ~w

...J

&lt-

DAL(7:Q) (H)

J SER

L
'-

-=t::.

ADRMRKFND (H)

LASTWORD (H)

LJ,eUAL RANK BYTEJ
CTRL HOLD REG
r-----------I~r>
(2 x 74LS175)

c","'o",":

LDPISOBUF (H)

L..-_ _ _ _ _- ,

a: '" U

~ «o J:Ud da:U
g O
a: a: a:

<'r-.
'I1B

SIPO

SCLK

J L

HOLDING REGISTER
(74LS374)

(74LSl64)

~ OE B BIT REGISTERI
~ LD

(74LS374)

ERR

I IL..------'

ERROR FLG
(74LS74)

NRZDOUT (H)

LOADREGS (H)

r---~t-t--I

:1rJ

SLOADPISO (L)
SHIFTREGS (H)

: I "XT"""OG" I:
~

I
N
I
-J

CRCDOUT (H)

L -________________________

m~+-;;t--:I~AL TIME I

o 0 d 0
r-------~r_

V- ~

OUTPUT DECODER

r
I
I
I

REQADRMRK (H)

(PALl6R4).

L---------,-. -

~------~S~E~L~CH~K~W~R~D~(~L~)----------------------~-tsc~C~UXJ
UPSTRMNRZ (H)

r=~'~'"'j- +~ATf::'" I!
L

PRESETCRC (L)

I BIT
COUNTER
j-t-t----------t--~V
I
(74LS161)
BITCNTR=8 (H)

MISSING BIT
DECODER

?
SHIFTREGS (H)

MFM LOGIC I

J L
V

ENBLBNDRY (L)
ENBLCENTR (L)

I II

L _

PRECOMP LOGIC

MFMwRTTH)-

WRTADRMRK (L)

1j~-I------~~==~~I

.-----~------------+--'~~~A~~~--~~

(PALl6L8)I

SELPRECOMP1 (H)

r-------------------~~~~~~-r-____+-._ _ _ _ _ _ _ _ _ _~S~E~LP~R~E~C~OM~P~O~(~H)~_

SELFLOPPY (H)

III

(PALl6R4.!.J

I- -

LAT~7:S175)

I
J
J

PRECOMP TIMING
CONTROLLER

PRECOMP MUX
(74S151)

I
I

WRTDATA (H)

Figure 2-5

SerializerjDeserializer and MFM EncoderjPrecomp
Generator Logic

}

T11

2.9 INTERRUPT VECTOR REGISTER
During an interrupt sequence, the contents of the interrupt vector register (Figure 2-6) are: gated to the
QBus to be used as the vector. The MSCP initialization function supplies the T-ll chip on the RQDXI
controller module with the vector number. The T-Il chip loads this number into the interrupt vector
register.
2.10 SA READ REGISTER, SA WRITE REGISTER, IP REGISTER
The status and address registers (SA) shown in Figure 2-6 are used by the T-ll chip and the QBus
processor for the MSCP port initialization sequence. Both SA registers occupy the same QBus I/O page
address.
The SA read register is written into by the T-II chip and read from by the host QBus processor. This
register is used to pass initialization status to the QBus processor.
The SA write register is written into by the QBus processor and read from by the T-ll chip. This register
is used during the initial sequence to pass the MSCP command buffer address and interrupt vector to the
T-ll chip.
The IP register is used to begin the initialization sequence when this register is written into by the QBus
processor. When the host QBus processor reads from the IP register, the RQDXl controller module
initiates a polling routine.
2.11 QBUS TRANSCEIVERS AND HANDSHAKE CONTROLLERS
The RQDXI controller module interfaces to the QBus through QBus drivers, QBus receivers, and control
circuits. The control circuits, shown in Figure 2-6, provide the handshake signals necessary to interrupt the
QBus, obtain control of the QBus for DMA, and interface the programmed SA and IP n~gisters to the
QBus.

2-8

QBUS
TO Q BUS TRANCEIVER
I

••
::::;

::::;

XQDAL<l5:00>(H)

;;:

'ty'
~

LUN BUFFER
(l4LS240)

SA READ REG
(2 x 74LS374) / \

ff-

a
x

~I!:i

VECTOR REG
(2 x 74LS374)

"-'\

~
<{

::::;

I I

;;:

ADDRESS
HOLD

~
f~

ENBLLUN(L)

::::;

~
0

I I
(PALl6LS)

A
~ :;:~ ~ ~

;;; ~ 0 ~
0 0
0
;;: ;;:
;;: ;;:

~~~'b~T.

II I I I I
r::::i:L Z 1="(3):
::> z -'
~ ~ 0 o >- Q.
'" a:
~ a: f- o
f- f- a:

()

,'NTERRUPT
,
CONTROLLER
(DCOO3 1/2 74S74)

REQVECTOR(H)

q c

§ :J
~+ ~a
~ ~

~
Tll

TO T11
INTERRUPT
HIGH SPEED CONTROLLER

Figure 2-6

QBUS DMA REQUEST'
CONTROLLER
(PAL 16LS)

i I

PIOCONTROL

Tll MEMORY MAP

g~ ~~ g~ ~~ ~~ ! ~

I
~a:~

I
I="

" 7

::::; ::::; ::::; ::::;

()

;;:

::::;

(3 x xDS8641)

z z §" ~
~ ~ ~ ~ ~

(1/2 74LS74)

(1/274LS74)

QBUS TRANSCEIVER

D~'----II--+--r-D~---+------i~
~

::::;

() () f) ) () () ( () () ) (

LJ'---r--T--r-r~~......-r-Tl~~~----r--r-'

~---,i'r,----,--~-----"'--{I---,...;--'
I

~'" i ,

:::;

:;:

}~16

SA WRITE REG
(2 x 74LS374)

;;:

:;:

::::;

Interrupt Vector Register, SA Registers
and QBus Interface Logic

2.12 RQDXI CONTROL LOGIC
The supervisory control of the complete RQDXl controller module is a shared function between the T-ll
chip and the main high-speed controller. These two devices share the internal data address blllS (DAL bus).
(Refer to Figure 2-1)
The T -11 chip has control over all housekeeping functions that are considered to be slow or those that
require data processing. The T-ll chip is configured into the 16-bit static mode driven by a 7.5 MHz
clock. The T -11 logic, along with the RAM and ROM memories, is shown in Figure 2-7.

HIGH SPEED
CONTROLLER
T·ll MEMORY MAP
200000

256 CSR'.

117400

REQTIIDMA(H)
. - -_
_ _ _ _---1
TIIDMAACK(L)

NOT USED
NOT USED

INTERRUPT REGISTER
PWR UP AND DMA LDGIC

~~
2K X

(74LS15S)

____

[ \ 21

___

1~ RAM

.....,""""r-~~""--I~_(2_X~4~01...
6)....J

(74LSJO, PAL lSLS 2 x 74LS13S)

-=M::EM:::A:"::;DR<...
15_:00_>H
_ _ _ _ _---'

I rl

__-.,. _____

MEMORY DECODE

S lMUX

V :;
;3

1~...--

l.
...--_~ll_.w..---. al

1.U)

""- 16

-..;

a:i

f'
"l'

:::;;

DEVICE
SELECT

Figure 2-7

T -11, RAM and ROM Logic

2-10

I,......---.:Io£....~------.
~~RXO::
I

___

(2 X 27M)

(1/2 74LS240)

L..-_"'--~"'--_~/

MODE BUFFER

RAS(H)l ADDRESS LATCH
(4 X 74LS163)

CONT~OLLER

HIGH SPEED
\

ASYNHOLD
(74LS373)

7.5 MHZ
XTAL OSC

(2 X PAL 16LS)

The main high-speed controller controls the high-speed read, write, and DMA functions to or from host
memory. This controller is configured as a microprogrammed multibranch controller operating at 10
MHz. The main high-speed controller architecture is shown in Figure 2-8.

LDCOFLAG(H)

CONTROL
INPUTS

~
21

(1/274LS74)
GO(HI

CLR

CONTRCLK(H)

WATCH DOG
TIMER

7.5 MHZ

(74LS292)
MUX1<C:A>(H)
~

~
Cl
«
UJ

E
a::
.....J

EN4WAY(L)
FLAGO(H)
NXTSTATE<9:2>(H)

r
I
I

RESETCTL(L)

CONTROL
OUTPUTS

Figure 2-8

T11 BUS
OUTPUTS

Main High-Speed Controller Architecture

2-11

MR-11293

The 1'-11 chip sets up all disk drive control signals, initializes the timer, clears the parity error flag, and
resets the shuffle step oscillator. The 1'-11 chip then sets up the device control block (DCB) with
parameters for the high-speed controller, initializes the response word with Is, and then sets the GO flag in
the I/O map. The high-speed controller, upon receipt of the GO signal, requests direct me:mory access to
the DAL bus from the T-ll chip. Upon receipt of the TI1DMAACK signal, the controll(~r takes control
of the DAL bus and begins the operation specified in the function code. Upon completion, various
parameters are placed in T-l1 RAM, the controller response word is filled in (in the DCB), the GO bit is
cleared, and control is returned to the T -11 chip. All high-speed controller operations must be completed
within 1 second or the timer logic will terminate controller operation.
2.13 MEMORY ADDRESS COUNTER/REGISTER
The memory address counter/register (shown in Figure 2-7) is used to latch the T-ll luemoryaddress
during the address phase of the bus cycle. The counter function of the address register is used by the highspeed controller to form a RAM pointer which can be incremented.
2.14 2 K X 16 RAM
As shown in Figure 2-7, the 2 K X 16 RAM is divided into the following three major sections.
•
•
•

1'-11 work space
Device control block
Sector buffer

This RAM can be accessed by both the 1'-11 chip and the high-speed controller.
2.15 DISK DRIVE CONTROL REGISTER AND STATUS BUFFER
The disk drive control register and status buffer are shown in Figure 2-9. Under T -11 control, the disk
drive control register provides drive selection and head control, including cylinder seeks on the selected
drive. This register also contains static control information for the PLL and serializer. The drive status
buffer is designed to interface the selected drive status to the DAL bus so that it can be interrogated by
either the 1'-11 chip or the high-speed controller.

2-12

£l-Z

- }~

INDEX(L)

Lr-

TRACKOO(L)

""'
..r

WRTFAULT(L)

READY(L)

..r

TIMEUP(HI

ENDRVSTAT(L)

"'"

I'"

SEEKCPLT(L)

....,

DRVSL1ACK(L)

~ r----"1

,---

~ Vim
...aC.

DRVSLOACK(L) , ;

:IJ

---.c "r- 0
""
~

.."

fiQ'

c::

@
N
I
\0

r;;'

<:
(p

(j
0

""1

:e
~
~

0.9.
tI:l

(p
""1

=
0.

rJ).
....

....c::
~

c::

LDDRVSEL(L)

....
....
....
....
....

(")

SELWINCHl (H)
RXMOTORON(L)

;::;

-i

""
~

:IJ
m

;;:

SELPRECMO(H)

~
o

P-~

BCLR(L)
LDDRVCTRL(L)

(")

DI RECTION(L)

~
~
r- :IJ
[J)

!::l

STEP(L)

HEADSEL2(L)
-

0
r-

:IJ

~." u;
~

-~ ~
-

.....

RXWRTDATAlL)

0<::]-

(")

o
WRTGAfE(H)

~
:IJ

""1

MFMWRTDT1(L)
MFMWRTDTl (H)

.....

MFMWRTDTO(L)
MFMWRTDTO(H)

WRTDATA(H)

MFMRDDATO(L)
MFMRDDATO(H)

READDATA(L)

WINY1RDAT(H)

MFMRDDATl(L)
MFMRDDATl (H)

(")

SELPRECM1(H)

~
(p

LDSYSD ISP( L)

DRVSEL 1(L)

WRTGATE(L)

~
~

DRVSEL2(L)

....

"""

m
Gl

i'\.r-

DRVSEL3(L)

HEADSELO(L)

.a>

DRVSEL4(L)

HEADSEL1(L)

~\:..:/

BCLR(L)

:IJ

m
rm

SELFLOPY(H)

REDUCWRTI(L)

(")

(/)

RXOWPTLED(L) -1"

.:'.:::.,1

,.~

~III

-i

(")

(/)

,..JS:::J..

RX1WPTLED(L)

:IJ

RX2WPTLED(L)

tI:l

t:::C

BCLR(L)

'----

P--

,..

....

......
...
-...

K=--

.-..'.:::.,1

RX3WPTLED(L) ;.

~»

~
0

,.~

..("1

RDOWRTPRO(L)

<-i

:J.

....=

RDORDY(L)
RD1WRTPRO(L)

~o;

.-.'-J

f'l

0»

r---

RDl RDY(L)

r--

r..c' -~- - -

..
..
....
....

DIAGMODE(H)

.{>

- f~
-

.,""'0,"'",

(")

~-<

FLPYRDDA1(H)

2.16 T-ll RAM ADDRESS POINTER AND ALU
The T -II RAM pointer logic consists of an address counter and an ALU. The high-speed controller logic
loads the beginning and ending T-ll RAM addresses into the registers within the address counter. The
controller then uses these pointers to specify the locations in the T -11 RAM where data is to be transferred
during QBus DMA and disk data transfers. The high-speed controller increments the pointers and
monitors the ALU to determine when the ending address has been reached.
2.17 BIDIRECTIONAL BYTE MULTIPLEXER
The bidirectional byte multiplexer is used to interface the 8-bit input/output of the serializer/deserializer
to the 16-bit RAM via the DAL bus.
During t~ read operation, the byte multiplexer causes the 8-bit byte from the serializer/deserializer to
appear on both high and low bytes of the 16-bit DAL bus. The high-speed controller can then selectively
write the byte into either the high or low byte section of the 2 K X 16 RAM.
During a write operation, the bidirectional byte multiplexer, again under control of the high-speed
controller, can be used to place the high byte into the low byte position of the DAL bus. The low byte
output of the RAM is disabled at this time.
2.18 8 K X 16 PROM
The 8 K X 16 PROM is used solely to store the T -11 instructions.
2.19 QBUS DMA POINTER AND ALU
The QBus DMA pointer logic consists of an address counter and an ALU. This logic is controlled by the
high-speed controller and is used to hold the QBus address during a DMA process.
This logic is also used as a byte comparator. The high-speed controller utilizes this compare function to
perform sector seek functions during read/write operations.

2-14

CHAPTER 3
C01'lFIGURATION AND INSTALLATION

3.1 INTRODUCTION
The RQDX 1 controller module must be mounted in the last occupied slot of the backplane due to the
DMA and interrupt structure of the LSI-II bus. The module's device address and logical unit number may
be changed by reconfiguring jumpers on the module. Figure 3-1 shows the RQDX 1 controller module
jumper and diagnostic LED locations.

07 08 D9 010

LUN7 :::::::: 0

A12

NOTES:
1. ADDRESS SELECTION (A12 THROUGH A2) AND
LOGICAL UNIT NUMBER SELECTION (LUN7 THROUGH
LUNO) IS MADE BY ATT.A.CHING TWO POSITION
JUMPER CLIPS (PART NO. 12-18783-00). THIS
ELIMINATES THE NEED TO WI RE WRAP JUMPERS
ONTO THE ADDRESS OR LOGICAL UNIT NUMBER
STAKES.
2. JUMPERS W1 AND W2 ARE IN FOR % AND 022/022
MACHINES AND ARE OUT FOR O/CD AND 022/CD
MACHINES. THEY PROVIDE GRANT CONTINUITY.
MR-9915

Figure 3-1

RQDX 1 Controller l\lodule Jumper and LED Locations

3-1

3.2

DEVICE ADDRESS SELECTION

The location of the RQDX 1 controller module address jumpers is shown in Figure 3-1. Table: 3-1 lists the
jumper configuration for the standard module address (772150). To configure the module for an address
other than 772150, use the format shown in Figure 3-2 to determine the appropriate jumper configuration.

Table 3-1

RQDXl Standard Address Jumper Configuration

Jumper

State

A2
A3
A4
A5
A6
A7
A8
A9
AID
All
AI2

Out

In
In
Out
Out
Out

In
Out

CI I I [ I I I
1

BANK SELECT 7
FOR 18-BIT
ADDRESSING

Address selection (772150)

BANK SELECT 7 FOR
22-BIT ADDRESSING

I
l 1 1 1 1 1 1 1 1

All

A10

l
! ! ! ! ! ! ! ! ! ! !
1

A12

----.J

BUS ADDRESS JUMPERS
CONNECT TWO POSITION JUMPER CLIPS (PART NO. 12-18783-00)
TO DECODE A 1.
NO CONNECTION DECODES A O.
"FACTORY
CONFIGURATION
MR-11287

Figure 3-2

RQDX 1 Address Selection Jumper Format

3-2

3.3 LOGICAL UNIT NUMBER SELECTION
The location of the RQDX 1 controller module logical unit number jumpers is shown in Figure 3-1. These
jumpers are set to the lowest logical unit number assigned to any disk/diskette drive controlled by the
module. The controller module automatically sizes the logical unit configuration during initialization to
determine how many (of the four possible units) are actually present. This automatic sizing eliminates the
need for reconfiguration of jumpers when units (RD51 or RX50 drives) are added to or removed from the
controller module. The standard configuration for the logical unit number jumpers (selecting logical unit
number 0) is listed in Table 3-2. To configure the rnodule for logical unit numbers beginning with other
than unit number 0, use the format shown in Figure 3-3 to determine the appropriate jumper
configuration.
Table 3-2

RQDXl Standard Logical Unit Number Jumper Configuration

Jumper

State

LUNI
LUN2
LUN3
LUN4
LUN5
LUN6
LUN7
LUN8

Out
Out
Out
Out
Out
Out
Out
Out

•

Logical unit number (0)*

This indicates that logical unit numbers 0--3 are assigned to this controller module.
The controller will automatically determine if less than four logical units are present.

LOGICAL
LUN
UNITS
JUMPER SPECIFIED
7
32-35
6

28-31

24-27

20-23

16-19

12-15
8-11

4-7

ONLY ONE JUMPER IS
INSTALLED AT ANY
TIME
ALL JUMPERS REMOVED
SPECIFIES LOGICAL
UNITS 0- 3
MR·11286

Figure 3-3

RQDX 1 Logical Unit Number Jumper Format

3-3

3.4 INTERRUPT VECTOR
The interrupt vector has a range of 0 to 774 and is software selectable. (A vector selected by software
must be greater than 0.) The normal interrupt vector used by the RQDXl controller module is 154.
3.5 INTERRUPT REQUEST LEVEL
The RQDX 1 controller module interrupts at priority level 4 determined by E3, a DC003 c:hip.
3.6 RQDXl CONTROLLER MODULE INSTALLATION
The RQDX 1 module (M8639) is typically installed in the last occupied slot of the backplane. If empty
slots are left between the other modules and the M8639 module, install grant cards (part number G7272)
in those empty slots to accommodate the interrupt and direct memory access structure of the backplane.
Before installing the module, make sure that the address and logical unit number jumpers are properly
configured.
Install the 50-conductor signal cable (part number BC02D-ID) to the Jl connector on the M8639 module.
This cable must be connected to a signal distribution panel that will connect the appropriate signals to the
RD51 and/or RX50 drives. An example of the MICRO/PDP-II signal distribution panel connecting the
M8639 module to an RD51 disk drive and an RX50 diskette drive is shown in Figure 3-4. The RD51 disk
drive requires two signal cable connections. One is a 20-conductor cable (part number 17-010282-00), the
other is a 34-conductor cable (part number 17-00286-00). The RX50 diskette drive requires a single 34conductor signal cable (part number 17-00285-02).

RQOX1

M8639

MR-11285

Figure 3-4

RQDX 1 MICRO/PDP-II Signal Distribution Connections

3.7 RQDXI-E EXTENDER MODULE OPTION
Typically (in the MICRO/PDP-II), the RQDXI controller module is located in the same mounting box as
the disk and/or diskette drives that it controls. However, if the system mounting box cannot accommodate
all of these drives, the optional RQDX l-E extender module may be used to connect the RQDX 1 controller
module signals to any drive that is external from the system mounting box.

3-4

3.7.1 RQDXI-E Extender Module Jumper Config:uration
As shown in Figure 3-5, the RQDXI-E extender rnodule is a dual-height module that provides signal
connectors and requires appropriate jumper configurations. The J2 connector receives signals from the
RQOX 1 controller module. The other connectors (J land J3) distribute these signals to the disk and
diskette drives. Jumper functions for the RQDXI-E extender module, as well as the jumpers installed in
the factory configuration, are listed in Table 3-3.

J J J

BAC
• •• 1
• •• 2
• •• 3
• •• 4

• •• 5
•

•• 6

• •• 7
• •• 8

DDX

-c::r Wl
-c::r W2

-c:::r W3
-c:J- W4

J
J
RJ R

• •• 1
• •• 2
• •• 3

MR-' '577

Figure 3-5
Table 3-3

RQDXI-E Extender Module Jumper Locations
RQDXI-E Extender Module Jumper Configuration
Factory
Configuration *

Jumpers

Functions

WI through W 4

Must be installed
(Manufacturing uSle only)

WI through W 4

JRO 1 through JR03
JOI through J03
JRX 1 through JRX3

Select the external drive
to be connected to the J 3
connector

JDI to JROI
JD2 to JRD2
JD3 to JRD3

J81 through J88
JA 1 through JA8
JC 1 through JC8

Determine which connector
(J2 or J3) the RD
read/write will connect to

JAI to JCI
JA2 to JC2
JA3 to JB3
JA4 to JB4
JA5 to JB5
JA6 to JB6
JA7toJC7
JA8 to JC8

Factory configuration is set to connect an external RD51 disk drive to connector J3. To configure the module for an external
RX50 (connected to J3), jumpers JDI through JD3 are connected to JRX I through JRX3, jumpers JA I through JA8 are
connected to J B I through J B8.

3··5

NOTE
Jumper selection (for configurations listed in Table
3-3) is made by attaching two-position jumper clips
(part number 12-18783-00).
3.7.2

RQDXI-E Extender Module Installation

Figure 3-6 shows the installation of the RQDXI-E extender module option in the MICRO/PDP-II system
(BA23 mounting box). The M7512 dual-height module is installed in the backplane slot dire:ctly below the
M8639 (RQDX 1) module, in connectors A and B. A cable (part number BC02D-OK) connects the
RQDX I controller module to the RQDXI-E extender module through the J2 connector. Another cable
(part number 70-18652-01) attached to the J3 connector connects the RQDX I-E extende:r module to a
mounting plate (part number 74-2866-01) that is mounted to the system's patch and filter panel assembly.
(The entire cable and mounting plate assembly may be ordered as part number 70-20691-0 I.) This
external plate provides the signals to be sent to the external drive. A third cable (part number BC02D-I 0
- attached to the J I connector on the RQDX I-E extender module) is connected to the signal distribution
panel in the mounting box, providing signals to the disk or diskette drives that are installed in the system
mounting box.

RQDX1
M8639

RQDX1-E
M7512

*MOUNTING PLATE INSTALLED IN SYSTEM
PATCH AND FILTER PANEL ASSEMBLY
MR-11295

Figure 3-6

RQDX I-E Extender Module Connections

3-6

CHAPTER 4
REGISTERS AND COMMANDS

4.1 INTRODUCTION
The RQDX I controller module contains two registers that can be accessed by a QBus address. A number
of other registers reside on the module, but these are accessible only to the T-II logic within the module.
The module uses mass storage control protocol (MSCP) to communicate with the host QBus processor.
Detailed information regarding MSCP is available in the UDA50 Programmer's Documentation Kit
(document number QP-905-GZ).
4.2 REGISTERS
The programmable registers contained on the RQDX 1 controller module are the initialize and poll register
(I P) and the status and address register (SA).
These registers can be addressed like any memory location.
4.2.1 Initialize and Poll Register (IP)
The initialize and poll register (lP) has a standard LSI-II bus address of 772150. This address is
determined by the address selection jumpers on the RQDX I module. (Refer to Paragraph 3.2 for jumper
selection information.)
The host begins the initialization sequence by either issuing a bus initialize or by using the IP initialize
operation. The I P register is not an actual register, but is simply a circuit that checks for a write operation
at the I P address. Any write to that address will cause an initialize operation to take place.
4.2.2 Status and Address Register (SA)
The status and address register (SA) has a standard LSI-II bus address of 772152. This address is
determined by the address selection jumpers on the RQDX I module.
The SA register consists of a set of two registers, the SA read register and the SA write register. These are
named according to their function in relation to the QBus host processor.
The SA read register is written into by the RQDXI module's T-Il and read from by the QBus. This
register is used to pass initialization status to the QBus processor.
The SA write register is written into by the QBus processor and read from by the T-Il. This register is
used during the initialization process to pass the mass storage control protocol (MSCP) command buffer
address and interrupt vector to the T-II chip.

4-1

4.3

MASS STORAGE CONTROL PROTOCOL (MSCP)

Mass storage control protocol (MSCP) is the message-oriented set of rules by which the RQDX 1 controller
module communicates with the host system. MSCP provides the protocol that allows the host to send a
command message and the controller module to send a response message. The host designates an area of
memory to be used as a communications area, and provides the location of this area to the controller
module. The size of the communications area is variable and is determined by the host software. Its
organization is shown in Figure 4-1. For additional information regarding MSCP, refer to the UDA50
Programmer's Documentation Kit (document number QP-905-GZ).

..
LOWER
ADDRESS

16-BIT WORD--+
COMMAND INTERRUPT WORD
RESPONSE INTERRUPT WORD
TWO WORD
BUFFER DESCRIPTOR
RESPONSE
RING

TWO
MSBs = Os

o0
COMMAND
RING

HIGHEST
ADDRESS
MR-l0588

Figure 4-1

Memory "Communications Area" Organization

4-2

4.3.1 MSCP Commands
Table 4-1 lists MSCP commands and their functions that are supported by the RQDX 1 controller module.

Table 4-1

MSCP Commands

Command

Function

Access

R(~ads data from the specified unit.

Abort

Guarantees that referenced MSCP command will complt~te within the controller timeout period.

Available

If specified unit is on-line, returns it to the unit-availabl(~ state. If specified unit is currently in the unit-available state, this command is essentially a no-operation.
(The RQDXl cannot spin down a unit.)

Compare Host Data

Reads data from the disk and compares it with the data
in the host buffer.

Erase

W rites zeros to the specified logical blocks on the unit.
(No data is accessed from the host.)

Get Command Status

Re:ports on the status of a specified command by
returning a number that reflects the command's
progress.

Get Unit Status

Re:ports on the status of a specified unit.

On Line

Places the specified unit on line, if possible.

Read

Reads data starting from the specified logical block on
the disk into host memory.

Set Controller Characteristics

Sets host-settable controller characteristics.

Set Unit Characteristics

Sets host-settable unit characteristics.

'Write

Writes data starting at the specified logical block on
the: disk from the host memory.

4-3

4.3.2

MSCP Status Codes

The RQDX 1 controller module provides MSCP status code response messages listed in Table 4-2.

Table 4-2

MSCP Status Code Messages

Message

Meaning

Command Aborted

The current command was aborted before it could be
completed normally.

Compare Error

While performing a Compare command, a discrepancy
was found while comparing the disk data to the host
data.

Controller Error

The RQDX 1 controller module detected an internal
error, but is able to continue processing its outstanding
commands.

Data Error

Data could not be read or written due to CRC errors,
"header not found", or due to a sector being read
whose forced error bit was set.

Drive Error

A drive-related error was detected (such as a seek
failure).

Media Format Error

lndicates the the media mounted on the unit was incorrectly formatted.

Host Buffer Access Error

Reports bus timeouts and parity errors during data
transfers. (Applies only to the data portion of an MSCP
command.)

Invalid Command

The RQDXI controller module found some field in the
command to be in error.

Success

The command was successfully completed.

Unit Available

The RQDX] controller module is not on line, but it can
accept an On Line command from the host.

Unit Offline

The RQDX] controller module is not on line, and it
cannot be brought on line.

W rite Protected

A write or erase command was attempted to a unit that
is either physically or logically write-protected.

4-4

4.4

DIAGNOSTICS AND UTILITIES PROTO(~OL (DUP)

The diagnostics and utilities protocol (DUP) provides a diagnostic mode of communication between the
host QBus processor program and the diagnostic and utilities server task (DUST). This protocol allows the
host program to request that the DUST load a diagnostic or utility program and execute it. Some
diagnostic programs access the diagnostic blocks on the RD51 disk. This allows the diagnostic to test
reading/writing on the disk without accessing or affecting customer software.
During execution of the diagnostic or utility program, the host program can make inquiries to the DUST
about the progress of the program being executed, or abort the program if there are unexpected results.
The diagnostic and utility programs executed by DUP commands (see Table 4-3) may require the host
program to specify certain parameters (such as starting host buffer addresses, byte count, block count,
etc.).
For additional information regarding DUP, refer to the UDA50 Programmer's Documentation Kit
(document number QP-905-GZ).
Table 4-3

[)UP Programs

Program

I('unction

Write DBN (RD51 only)

'~rites

and transfers a diagnostic block with a data.

pattern.
Read DBN (RD51 only)

Reads a diagnostic block.

Format (RD51 only)

Formats the entire disk, verifies the disk, and implennents bad block revectoring.

Read Sector (RD51 or RX50)

Reads a physical sector. The data is not transferred to
the host, but drive problems will be detected.

Restore (RD51 or RX50)

~({oves the read/write head of the drive to the home

position.
Self Test

Verifies that certain RQDXl controller module logic is
functioning properly. Self Test results are reported in
the diagnostic LEDs (refer to Paragraph 5.2). Self Test
is always executed on power up or Bus INIT.

4.4.1 DUP Commands
The following commands are available to OUP and are supported by the RQOX 1 controller module.
•
•
•
•
•
•

Get DUST Status
Execute Supplied Program
Execute Local Program (Diagnostic or Utility)
Send Data
Receive Data
A bort Program

4-5

4.4.2 DUP Responses
The following responses are available to DUP and are supported by the RQDXl controller module.
•
•

Success
Illegal Command

In the case of an Execute Supplied Program command, the following responses are also available.
•
•

No Region Available
No Region Suitable

In the case of an Execute Local Program command, the following responses are also available.
•
•
•
•
•

No Region Available
No Region Suitable
Program Not Known
Load Failure
Standalone

4-6

CHAPTER 5
ERROR DETECTION

5.1 INTRODUCTION
Each time that the RQDX 1 controller module is powered up, the module executes a selftest that verifies
the operation of the T-Il chip and the ROM and RAM memory chips. Successful completion of the
seIftest takes approximately five seconds. The RQDX 1 controller module provides a set of four diagnostic
LEOs that display a code corresponding to the functional block of the selftest currently being executed or
the type of failure that occurred. The diagnostic LEDs and error codes are described in Paragraph 5.2.
Diagnostic programs determine whether or not the RQDX 1 controller module, the RD51 disk drive,
and/or the RX50 diskette drive are working properly. If they are not, they isolate the failing component.
Diagnostic programs are used exclusively for maintenance purposes and play no part in normal system
operation. The programs are provided on the XXDP+ diagnostic software system available from Digital
Equipment Corporation. The diagnostic programs that test the RQDX 1 controller module, the RD51 disk
drive, and the RX50 diskette drive are described in Paragraph 5.3.
5.2 DIAGNOSTIC LED ERROR DISPLAYS
The diagnostic LEDs provided on the RQDXI controller module indicate faults during the selftest. On
power up, all of the LEDs are lit and then immediately cleared as the RQDX 1 module enters the seIftest.
The LEOs indicate (in a binary sequence) the functional block of the seIftest or the type of failure that has
occurred. All four LEDs are off after successful completion of the selftest. Figure 5-1 shows the diagnostic
LED locations on the RQDX 1 module. Table 5-1 lists the diagnostic LED codes and the corresponding
failure description.

010

c[]1----_O_O_C_1_0
__

MR·11284

Figure 5-1

Diagnostic LED Locations

5··1

Table 5-1

Diagnostic LED Error Displays

Display
LED
Octal

MSD
DI0
Bit 3

LSD
D9
Bit 2

D8
Bit 1

D7
Bit 0

Off

No error
Exit from selftest

Off

T-II failure

Off

T -II 2942 failure

Off

QBus 2942 failure

Off

Serializer deserializer failure

Off

CRC failure

Off

Microcode version

Off

Diagnostic interrupt failure

Off

Shuffle oscillator failure

Off

RQDXI ROM checksum
failure

Off

RQDX I RAM failure

Off

Undefined

Off

Undefined

Off

Undefined

Off

Undefined

Power up of the: RQDXI or
reception of Bus INIT

5-2

Type of Error

5.3

DIAGNOSTIC SOFTWARE

The XXDP+ diagnostic software system provides the diagnostic programs necessary to test the RQDX 1
controller module, as well as any RD51 disk drives and/or RX50 diskette drives that are connected to the
RQDX I. Table 5-2 lists the appropriate XXDP+ diagnostic programs and the testing function performed
by each program. The individual program listings may be used to further isolate component failures.

Table 5-2

XXDP+ Diagnostic Programs

XXDP+ Program Name

Title

ZRQA??BIN*
ZRQB??BIN

RDRX Performance Exerciser
RDRX Formattert

* '?'? indicates any revision of the program.
t This program formats the RD51 disk. The procedure is described in Paragraph 6.2.2.

5-3

CHAPTER 6
DISK DRIVES

6.1 INTRODUCTION
The RQDX I controller module is used to interface an RDSI disk drive(s) and/or an RXSO diskette
drive(s) to the extended LSI-II bus.
The RDSI disk drive is a random access storage device which uses two nonremovable 133.4 mm (S.2S
inch) disks as storage media. The total formatted capacity of the RDSI disk drive is II megabytes.
The RXSO diskette drive is a random access dual diskette storage device which uses two single-sided 133.4
mm (S.2S inch) RXSOK diskettes. The total drive capacity is 800 K bytes of formatted data.
6.2 RD51 DISK DRIVE
The RDSI disk drive, shown in Figure 6-1, is a field replaceable unit (FRU) that is installed in a system
mounting box. The RDSI drive is connected to the controller module (via the distribution panel) by two
signal cables (J I and J2). A third cable (J3) provides power supply connections to the RDSI drive. The
connector pin assignments for each of the three cables is provided in Appendix C.

MR·940B

Figure 6-1

RDSI Disk Drive

The RDSI disk drive capacity is 11 megabytes on two nonremovable 133.4 mm (S.2S inch) disks. Each
disk surface uses one movable head to service 306 data tracks. The head and disk technology used allows
the heads, which normally fly over the disk surface, to land when the drive is powered off. This
technology, termed Winchester, utilizes lubricated media and lightly loaded read/write heads.
High bit densities on the media are achieved by flying the heads at a height of 20 microinches. This flying
height requires a clean air environment which is achieved by manufacturing and sealing the head and disk
assembly (HDA) in a clean room environment.

6-1

6.2.1

RD51 Disk Drive Installation

Installation of the RD51 disk drive requires proper configuration of the dual in-line package (DIP) shunt
jumper pack located on the RD51 read/write printed circuit board. Location of the shunt is shown in
Figure 6-2. The proper jumper configuration (required for the RD51 drive to be used with the RQDX 1
controller module) is listed in Table 6-1.

MR 9539

Figure 6-2

RD51 Disk Drive Read/Write Printed Circuit Board

Table 6-1
Pin
Numbers

Pin
Connection

1 to 16
2 to 15
3 to 14
4 to 13
5 to 12
6 to 11
7 to 10
8 to 9

Not used*
In
In
In

DIP Shunt Jumper Configuration

Out
In

Out
Out

The 14*pin DIP jumper pack is offset into a 16-pin socket toward the contact pins on the read/write printed circuit board. If
the DIP shunt Uumpers) need to be replaced, a new DIP shunt can be ordered (part number 29-24115).

NOTE
Any replacement RD51 disk drive must be formatted
using the ZRQB??BIN program to be compatible
with the RQDXl controller module. (Refer to Paragraph 6.2.2 for the formatting procedure.)
WARNING
When sliding the RD51 disk drive in or out of a
system chassis, do not hold the drive by its front
right side. Doing so will cause the head positioner
flag to rotate, resulting in damage to the drive. Figure 6-3 shows the head positioner flag location on
the disk drive.
6-2

HEAD POSITIONER FLAG

Figure 6-3

RD51 Disk Drive Head Positioner Flag

16.2.2 Formatting the RD51 Disk Drive
The ZRQB?? (any revision) program, provided by the XXDP+ diagnostic software system, is used to
format the RD51 disk drive. The procedure for formatting is as follows.
lin response t.o the XXDP+ . (period) prompt, type R ZRQB??
.R ZRQB?? <CR>
(The question marks will allow any revision of the program to be used.) A response similar to the following
appears on the console terminal.
DRS DO
RDRX -X-X (where -X-X is the current revision information)
RD51 DISK FORMATTER
UNIT IS RQDXI DISK DRIVE SUBSYSTEM
RSTRT ADR AAAAAA (where AAAAAA specifies a restart address)
DR>
You must respond to this prompt with a command to run the program. For example:
DR>START

(default will cause the program to run one pass)

You are then asked the following.
CHANGE HW (L) ? N
CHANGE SW (L) ? N
ENTER UNIT TO BE FORMATTED (D) ? X

(where X is the unit number assigned to the drive
to be formatted)

USE EXISTING BAD BLOCK INFORMA T]ON (L) N ? N
USE DOWN LINE LOAD (L) N ? N
CONTINUE IF BAD BLOCK INFORMATION IS INACCURATE (L) N ? Y
ENTER 8 CHARACTER SERIAL NUMBER (A) ?

6-3

The 8-character serial number is a unique serial number assigned to each RD51 disk drive. It is labeled on
the left side of the disk drive (refer to Figure 6-4).

MR-11296

Figure 6-4

RD51 Serial Number Label Location

ENTER DATE IN MM-DD-YY FORMAT (A)?
As shown above, the current date should be entered.
The format routine takes approximately II minutes to complete, and its successful completion results in a
message similar to the following.
FORMAT COMPLETED, X REVECTORED LBNS
RDRX EOP 1
o TOTAL ERRS
The RQDX 1 controller module automatically revectors any bad sectors and prints the total number of
revectored sectors in the format completed message. The maximum number of sectors that will be
revectored is 144.
If the formatting process is not successful, an error message appears on the terminal. Refer to the
individual program listing to use this message (if necessary) to isolate the failure or to determine which
FRU to replace.
6.3 RX50 DISKETTE DRIVE
The RX50 diskette drive is shown in Figure 6-5. The RX50 diskette drive is a field replaceable unit (FRU)
that is installed in a system mounting box. One cable connects the RX50 to the RQDX 1 controller module
(via the distribution panel), another cable connects the drive to the power supply. There are no field
alignment procedures for the RX50 diskette drive, since it is adjusted and aligned at the time of
manufacture.

6-4

MR-9532

Figure 6-5

RX50 Diskette Drive

The RX50 diskette drive is a random access, dual-diskette storage device. It has two access doors and slots
for diskette insertion and removal. An active drive light for each diskette slot informs you when that drive
is busy. The RX50 diskette drive capacity is 800 K bytes of formatted data on two single-sided diskettes.
This is accomplished by utilizing a 133.4 mm (5.25 inch) RX50K diskette that contains 80 tracks, 10
sectors per track, and 512 bytes per sector of modific;:d frequency modulation (MFM) data. The average
access time, including latency, is 264 ms.

6-5

APPENDIX A
RQDXl CONTROLLER MODULE BACKPLANE PIN ASSIGNMENTS

Diigital Equipment Corporation's plug-in modules, including the RQDXI controller module, all use the
same contact (pin) identification system. Figure A-I shows the contact finger identification for a typical
quad-height module. Each connector contains 36 lines (18 lines on each side of the printed circuit board).
Table A-I lists the backplane pin assignments for the RQDX I controller module.

ROW A

BAl

ROW B

ROWC

DAl

SIDE 1
COMPONENT SIDE

SIDE 2
SOLDER SIDE
ROW 0

Figure A-I

Quad Module Contact Finger Identification
A-I

Table A-I

RQDXI Controller Module Backplane Pin Assignments

Signal Name

AAI
ABI
ACI
ADI
AEI
AFI
AHI
AJI
AKI
ALI
AMI
ANI
API
ARI
ASI
AT1
AUI
AVI

(BIRQS L)
(BIRQ6 L)
BDALl6 L
BDAL17 L
(SSPAREI or +SB)
(SSPARE2)
(SSPARE3)
GND
(MSPAREA)
(MSPAREB)
GND
BDMR L
(BHALT L)
BREF L
(+12Bor+SB)
GND
(PSPAREI)
(+SB)

AA2
AB2
AC2
AD2
AE2
AF2
AH2
AJ2
AK2
AL2
AM2
AN2
AP2
AR2
AS2
AT2
AU2
AV2

+SV
(-12V)
GND
(+12V)
BDOUT L
BRPLY L
BDIN L
BSYNC L
BWTBT L
BIRQ4 L
BIAKI L
BIAKO L
BBS7 L
BDMGI L
BDMGO L
BINIT L
BDALO L
BDALI L

BAI
BBI
BCI
BDI
BEl
BFI
BHI
BJI
BKI
BLI
BMI
BNI
BPI
BRI
BSI
BTl
BUI
BYI

(BDCOK H)
BPOK H
BDALI8 L
BDALI9 L
BDAL20 L
BDAL21 L
(SSPARE8)
GND
(MSPAREB)
(MSPAREB)
GND
BSACK L
(BIRQ7 L)
(BEVNT L)
(+12B)
GND
(PSPARE2)
+SY

BA2
BB2
BC2
BD2
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

+SV
(-12V)
GND
+12V
BDAL2 L
BDAL3 L
BDAL4 L
BDALS L
BDAL6 L
BDAL7 L
BDAL8 L
BDAL9 L
BDALIO L
BDALll L
BDALl2 L
BDAL13 L
BDALl4 L
BDALIS L

A-2

Table A-I

RQDXI Controller ModulE~ Backplane Pin Assignments (Cont)

Signal Name

CAl
CBI
CCI
COl
CEI
CFI
CHI
CJI
CKI
CLI
CMI
CNI
CPI
CRI
CSI
CTI
CUI
CVI

(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
GND
(Unused)
(Unused)
GND
(Unused)
(Unused)
(Unused)
(Unused)
GND
(Unused)
(Unused)

CA2
CB2
CC2
CD2
CE2
CF2
CH2
CJ2
CK2
CL2
CM2
CN2
CP2
CR2
CS2
CT2
CU2
CV2

+5V
(Unused)
GND
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
CIAKI L
CIAKO L
(Unused)
CDMGI L
CDMGOL
(Unused)
(Unused)
(Unused)

DAI
OBI
DCI
DOl
DEI
DFI
DHI
DJI
DKI
DLI
DMI
DNI
DPI
DRI
DSI
DTI
DUI
DVI

(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
GND
(Unused)
(Unused)
GND
(Unused)
(Unused)
(Unused)
(Unused)
GND
(Unused)
(Unused)

DA2
DB2
DC2
DD2
DE2
DF2
DH2
DJ2
DK2
DL2
DM2
DN2
DP2
DR2
DS2
DT2
DU2
DV2

+5V
(Unused)
GND
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)

A-3

APPENDIX B
RQDXl CONTRC)LLER MODULE CABLE SIGNALS

Table 8-1 lists the RQDX I controller module signals on the J 1 connector.

Table B-1

Jl Coolnector Signals

Jl Pin

Signal Name

MFMWR TDT 1 (H) (RD51 only signal)
MFMWRTDTI (L) (RD51 only signal)
GROUND
HEAD SEL 2 (L) (RDXX only signal)*
GROUND
SEEKCPLT (L) (RD51 only signal)
RD 1 RDY (H) (RD51 only signal)
WRT FAULT (L)
DRV8USOE (L)

2
3
4
5

6
7
8

9
10
1I
12
13
14
15
16
17
18
19

20
21

22
23
24

25
26
27
28
29

HEAD SEL ] (L) (RD51 only signal)
RXOWPTLED (L) (RX50 only signal)
RDO RDY (H) (RD51 only signal)
RX 1WPTLED (L) (RX50 only signal)
DRVSLOACK (L) (RD51 only signal)
MFMRDDATO (H) (RD51 only signal)
MFMRDDA TO (L) (RD51 only signal)
MFMWRTDTO (H) (RD51 only signal)
MFMWRTDTO (L) (RD51 only signal)
MFMRDDATI (H) (RD51 only signal)
MFMRDDA Tl (L) (RD51 only signal)
GROUND
REDUCWRTI (L)
RDOWRTPRO (L) (RD51 only signal)
DRV SEL 4 (L)
GROUND
INDEX (L)
RDI WRTPRO (L) (RD51 only signal)
DRV SEL 1 (L)
DRV SEL 2 (L)

* Reserved for future use.

B-1

Table B-1

J 1 Connector Signals (Cont)

Jl Pin

Signal Name

30
31
32
33
34
35
36
37
38
39

DRV SEL 3 (L)
RX2WPTLED (L) (RX50 only signal)
RXMOTORON (L) (RX50 only signal)
GROUND
DIRECTION (L)
GROUND
STEP (L)
GROUND
RXWRTDAT A (L) (RX50 only signal)
GROUND

WRT GATE (L)
GROUND
TRACK 00 (L)
RX3WPTLED (L) (RX50 only signal)
DRVSLIACK (L) (RD51 only signal)
GROUND
READ DATA (L) (RX50 only signal)
GROUND
HEAD SEL 0 (L)
GROUND
READY (L)

42
43
44
45
46
47
48
49

* Reserved for future usc.

B-2

APPENDIX C
DISK DRIVE CABLE: CONNECTOR PIN ASSIGNMENTS

C.l RD51 DISK DRIVE CONNECTOR PIN ASSIGNMENTS
The connector pin assignments for the RD51 disk drive signal and power cables are listed in Tables C-I
through C-3.

Table C-l

RD51 Disk Drive Jl Siignal Connector Pin Assignments

GND Return
Pin
I
3
5
7
9

I1
13
15
17
19
21
23
25
27
29
31
33

Signal
Pin

Signal
Name

Reserved
Head Select 2
Write Gate
Seek Complete
Track 0
Write Fault
Head Select 0
Reserved (to J2 pin 7)
Head Select 1
Index
Ready
Step
Drive Select 1
Drive Select 2
Drive Select 3
Drive Select 4
Direction In

4
6
8
10
12
14
16
18
20

22
24
26

28
30
32
34

C-l

Table C-2

RD51 Disk Drive J2 Signal Connector Pin Assignments

GND Return
Pin

Signal
Pin

Signal
Name

2
4
6
8

1
3

Drive Selected
Reserved
Reserved
Reserved (to J 1 pin 16)
Reserved
GND
+MFM Write Data
-MFM Write Data
GND
+MFM Read Data
-MFM Read Data
GND

5
7
9, 10
11
13
14
15
17
18
19

12
16

Table C-3

RD51 Disk Drive J3 Power Connector Pin Assignments
GND Return
Pin

Signal
Pin

Signal
Name

2
3

+12 V

+5 V

C-2

C.2 RX50 DISKETTE DRIVE CONNECTOR PIN ASSIGNMENTS
The connector pin assignments for the RXSO diskette drive signal and power cables are listed in Tables C4 and C-S.

Table C-4
GND Return
Pin
I
3
S
7
9
II
13
IS
17
19
21
23

RX50 Diskette Drive J 1 Connector Pin Assignments
Signal
Pin

Signal
Name

TK43L (controls write current level)
Reserved
Drive Select 3 L
Index L
Drive Select 0 L
Drive Select 1 L
Drive Select 2 L
Motor On L
Direction (head movement direction)
Step L (head movement distance)
Write Data L
Write Gate L
Track 0 L
Write Protect L
Read Data L
Reserved
Ready L

4
6
8
10
12
14
16
18
20

22
24
26

2S
27

30
32
34

31
33

Table C-5

RX50 Diskette Drive J3 Power Connector Pin Assignments
GND Return
Pin

Silgnal
Pin

Signal
Name

1
4

+S V

C-3

+12 V

Digital Equipment C-orporation • Bedford, MA 01730