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EK-RLV12-UG-001

July 1981

53 pages

Original

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Document:	RLV12 Disk Controller User's Guide
Order Number:	EK-RLV12-UG
Revision:	001
Pages:	53
Original Filename:	http://bitsavers.org/pdf/dec/qbus/EK-RLV12-UG-001_Jul81.pdf

OCR Text

EK -RLV12- UG·OOl

RlV12
Disk Controller
User's Guide

~DmDDmD

RLV12
Disk Controller
LJser's Guide

Prepared by Educational Services
of
Digital Equipment Corporation

1st Edition, July 1981

The material in this manual is for informational purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL's DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment
Corporation:
DIGITAL
DEC

PDP
DECUS
UNIBUS
DECLAB

DECsystem-IO
DECSYSTEM-20
DIBOL
EduSystem
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX

lAS
MINC-II

CONT'ENTS
CHAPTER 1!

INTRODUCTIO~

1.1
1.2
1.3
1.3.1
1.3.2

DESCRIPTION .......................... "...........................................................................
FEATURES ...........................................................................................................
SPECIFICATIONS .................... "............................................................................
RL V 12 Disk Controller ......................................................................................
RLO 1/RL02 Disk Drives ................. ,...............................................................

CHAPTER 2

FUNCTIONAL DESCRIPTION

2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.5
2.6

2.9

INTRODUCTION ....................................... ""........................................................... 2-1
BUS PROTOCOL................................................................................................... 2-3BUS TRANSCEIVERS......................................................................................... 2-4
PROGRAM\;fABLE REGISTERS ...................................................................... 2-4
Bus Address Register (BAR) ........................................................................... 2-5
Bus Address Extension Register (BAE) ......................................................... 2-5
Disk Address Register (DAR) ........................................................................ 2-5
Control/Status Register (CSR)...................................................................... 2-7
Multipurpose Register (MPR) ....................................................................... 2-8
FIFO Memory, FIFO Serializer and Word Difference Counter.................... 2-9
DATA SOURCE MULTIPLEXER AND CRC GENERATOR ........................ 2-10
MICROSEQUENCER, CONTROL STORE PROMS,
AND BUFFER REGiSTER ... " ................................................................................. 2'-10
Buffer Register Fields ...................................................................................... 2-11
Fatal Error Clearing Logic ..................................................................... "....... 2-] 1
CONTROL REGISTERS AND PULSE GENERATORS ................................. 2-12
WRITE ENCODER AND PRECO~fPENSATION LOGIC ............................. 2-12
DATA SEPARATOR READ CiRCUiT .............................................................. 2-15

CHAPTER 3

CONFIGURATION AND INSTALLATION

3.1
3. 2
3.3
3.4

3. 6
3. 7
3. 8
3. 9

INTRODUCTION..................................................................................................... 3-1
DEVICE ADDRESS SELECTION ...................................................................... 3-1
BUS SELECTION.................................................................................................. 3-1
INTERRUPT VECTOR........................................................................................ 3-1
INTERRUPT REQUEST LEVEL ....................................................................... ·3-1
MEMORY PARITY ERROR ABORT FEATURE............................................. 3-4
JUMPERS THAT REMAIN INSTALLED ........................................................ 3-4
INSTALLATION ................................................................................................... 3-5
ACCEPTANCE TESTING ..................................................................................... 3-5

CHAPTER 4

REGISTERS

4. 1
4. 2
4,,3
4.4
4 . 4.1
4..4.2
4..4.3

INTRODUCTION ....................... "...........................................................................
CONTROL/STATUS REGISTER (CSR)...........................................................
BUS ADDRESS REGISTER (BAR).....................................................................
DISK ADDRESS REGISTER (DAR) .................................................................
DAR During a Seek Command ......................................................................
DAR During a Read, \Vrite, or \Vrite Check Command ...............................
DAR During a Get Status Command.............................................................

2.6.1
2.6.2
2.7
2.8

3. 5

IIJ

1-1
1-1
I-I
I-I
l-3

4-1
4-1
4-1
4-4
4-4
4-4
4-4

CONTENTS (Cont)
4.5
4.5.1

~vfULTIPLRPOSE REGISTER (:\lPR) ...............................................................

4-4

4.6

\Vriting the MPR to Set the \Vord Count.......................................................
Reading the MPR After a Read l-leader Command ........................... ".........
Reading the l\1PR After a Get Status Command............................................
BUS ADDRESS EXTENSION REG ISTER (BAE) ...........................................

CHAPTER 5

CO;\I1\:I:\ NDS

4 ..5.2

4.5.3

4-7
4-7
4-7

5.1

INTRODUCTION.................................................................................................

5-1

5.2

\\' R IT E C H E C K ( 1) ......................................................................................... ~. ...

5.3

5-1
5-1
5-·2
5-2

5.11

GET STATUS (2) ..................................................................................................
SEE K (3) ................................................................................................................
READ I-lEADER (4)..............................................................................................
\V R I T E ·D /\ T r\ (5) .................................................................................................
READ Df\ T A (6) ...................................................................................................
READ \VITHOUT HEADER CHECK (7) ..........................................................
MAINTENANCE FU~CTION (0)......................................................................
EXAMPLES OF USING COMMANDS .............................................................
Seek Operation ...............................................................................................
Data Transfer Operation ............................................................................. "..
ERROR RECOVERY ...........................................................................................

CHAPTER 6

DISK DRIVE

6.1
6.2
6.3

I NTI{ODUCTION ..................................................................................................
USER S\VITCHES AND INDiCATORS............................................................
110/220 VOLTAGE AND NORl\1AL/LOW VOLTAGE
RANGE SETTING ................................................................................................

5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.10.1
5.10.2

5-2

5-2
5-2
5-3
5-3
5-4
5-4

5-5

6-1

6-2
6-2

TABLES
Table No.
2-1

3-1
4-1
4-2

4-3
4-4

4-5
4-6

5-1
5-2
6-1

Title

Page

Control/Status Register Bits .................................................................................. 2-8
Address Selection.................................................................................................... 3-2
CSR \Vord Format.................................................................................................. 4-2
DAR Seek Command \Vord FormaL .................................................................. "... 4-5
DAR Read/\Vrite Data Command Word Format.................................................. 4-5
DAR Get Status Command \Vord Format ............................................................. 4-6
M PR \Vord Count Forn1at ....................................................................................... 4-6
MPR Status \Vord Format........................................................................................ 4-8
Controller Status Errors........................................................................................... 5-5
Disk Drive Status Errors.......................................................................................... 5-6
Voltage and Range Selector Setting ....................................................................... 6-3

FIG·URES
Figure 1\0.
2-1
2-2

2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-]0
2-11
2-12

2-13
3-1
3-2
3-3
3-4
4-1

4-2
4-3

4-4
4-5
4-6
4-7
4-8
4-9
6-1
6-2

Title

Page

R LV 12 Block Diagram ........ ...................... .............. .............................. ..................... 2-2
Bus Protocol Logic ................................................................................................... 2-3
Bus Transceivers ........... ...... ...... ................................. ............................... ............... 2-4
Bus Address Register (BAR) Circuit....................................................................... 2-5
Bus Address Extension Register (BAE) Circuit ..................................................... 2-6
Disk Address Register (DAR) Circuit.................................................................... 2-6
Control/Status Register (CSR) Circuit.................................................................. 2-7
FIFO RAM. Buffers. and Serializer....................................................................... 2-9
Microsequencer. Control Store PROiVls. and Buffer Register. ... :.......................... 2-10
;\1Fl\1 Encoding .............................................................................................. ~ ........ 2-12
Peak Shift \Vaveforrn .............................................................................................. 2-13
Write Encoder and Precompens:ltion Circuit ......................................................... 2-14
Data Separator Read Circuit .................................................................................. 2-15
RLV 12 Jumper Locations....................................................................................... 3-3
RLV 12 Device Address Format.............................................................................. 3-4
RLV 12 Interrupt Vector Format ............................................................................ 3-4
RL V] 2 Installation ................................................................................................... 3-6
Control/Status Register (CSR) .............................................................................. 4-3
Bus Address Register (BAR) .................................................................................. 4-3
DAR During a Seek Command ............................................................................. ~.. 4-5
DAR During a Read. \Vrite. or \Vrite Data Command.......................................... 4-5
DAR During a Get Status Command ..................................................................... 4-6
Writing the MPR to Set the Word Count................................................................ 4-6
Reading the MPR After a Read Header Command
. (Three l-leader \\' ords) .............................................................................................. 4-7
Reading the \fPR After a Get Status Command ................................................... 4-7
BAE Register \\lord Format ................................................................................... 4-8
RLOI/RL02 Disk Drive (Front View)..................................................................... 6-1
RLOI/RL02 Disk Drive (Rear View) ............................................ ~......................... 6-3

CHAPTER 1

INTRODUCTION
1.1 DESCRIPTION
The RL V 12 Disk Controller interfaces RLOI and RL02 disk drives to any quad- or hex-size backplane
that uses a 16-, 18-, or 22-bit LSI-II bus. One RL V 12 controls up to four disk drives. The RL V 12
consists of one quad-size module (M8061), a BC80M cable, a drive terminator, and drive identification
hardware.

The RLOI and RL02 disk drives are random-access, mass-storage. subsystems that store data in fixedlength blocks on a preformatted disk cartridge. Each RLO 1 can store 5.24 million bytes, and each RL02
can store 10.48 million bytes. The drives are 26.67 cm (10.5 in) high, self-cooled, rack-mountable units
and come complete with a power supply. Option RL V 12-AK includes one RLO 1 drive, and option
RL V22-AKincludes one RL02 drive.
The RL V 12 transfers data to and from the LSI-:[ I bus using direct lnenlory access COMA) transactions. This allows data transfers to occur without first going to the processor.

1.2 FEATURES
TheRL V 12 controller has the following features.
•
•
•
•
•
•

Single quad-size module; needs no C-D connections.
Supports DMA data transfers in 16-, 18-, or 22-bit addressing modes.
Software compatible with RL V 11 controller (l6- or I8-bit 1110de only).
Supports 22-bit addressing on an LSI-II bus.
Controls from one to four RLOI jRL02 drives.
l\1emory parity error abort feature for llse with memories that have a parity option.

1.3 SPECIFICATIONS
1.3.1

RLV12 Disk Controller

Module

1 quad-size module, M8061

Size

Height: 26.56 em (10.457 in)
Width: 1.27 crn (0.5 in)
Length: 22.70 cm:" (8.94 in)

Power Requirements

+5 Vdc ± 5% at 5.0 A
+12 Vdc ± 5% at 0.1 A

Bus Loads
ac bus loads
dc bus load
Addressing Modes

3
I

16-, 18-, and 22-bit (determined by user)

1-1

Minimum Configuration
. for 22-Bit Address Mode

H9275-A or similar backplane that supports 22-bit addressing, and
memory capable of 22-bit addresses, such as the MSV Il-L lOr the
MSVII-P.

Limitations

The RL V 12 will not fit in the dual-height LSI-II mini-series H9281
backplane.

Drives per Controller

Up to four RLOI and RL02 drives in any combination

LSI-I) Bus-Addressable
Registers

8 (5 are used; 3 are not used)

Base Device Address

Selected by jumpers as follows.
Addressing IVf ode

Base Device Address

16-bit
I8-bit
22-bit

1744008
7744008
177744008

Devi ce In tcrru pt Vector

0001608, jumper selectable

Data Transfcr Rates

4.9 Jls/word (avg) drive to controller. controller to memory
3.9 Jls/word (peak) drive to controller
2.0 Jls/word (peak) controller to memory

Error Detection Capability

Cyclic redundancy check (CRe) on data and headers
Memory parity error abort for use with memories that have parity
checking

Maximum Cable Length
Controller to Last Drive

30 m (100 ft)

Environment Specifications
Temperature
Storage
Operating*

-40 0 C to 66 0 C (-40 0 F to 150 0 F)
50 C to 60 0 C (41 0 F to 11 0 0 F)

Relative Humidity
Storage
Operating

10% to 90%, noncondensing
10% to 90%, noncondensing

Altitude
Not operating
Operating*

9 km (5.6 mi) max
2.4 km (1.5 mi) max

Airflow
Operating

Max temperature rise across module must not exceed 10 0 C
(18° F) input to output.

* Reduce the maximum operating temperature by I.S0 C for each 1000 m altitude above sea level or J
above sea level.

1-2

F for each 1000 ft

1.3.2

RLOI/RL02 Disk Drhes

Storage Type
Medium

Magnetic disk cartridge

Recording Surfaces

2 data surfaces

Magnetic heads

2 read/write heads

Recording Capacity (formatted)
Cylinders per cartridge
Tracks pier cylinder
Tracks pier cartridge
Sectors per track
Bytes per sector
Bytes per track
Bytes per cylinder
Bytes per cartridge
Rt:cording Method

RLOt

R1L02

256
2
512
40
256
10,240
20,480
5.24 M

5112
2
1024
40
256
10,240
20,480
10.48 M

Modified frequency modulation (MFM)

Performance
Transfer Rate

40-sector (l6-bit data words):
4.9 ,us/word (avg) drive to controller, controller to memory
3.9 ,us/word (peak) drive to controller

Head Positioning Time

55 ms (avg)
17 ms (one track)
100 ms (max)

Revolution Latency

12.5 ms (avg)

Operating Environment
Temperature Range
Relative Humidity
Wet Bulb Temperature
Altitude
Heat Dissipation

10° C to 40° C (50 0 F to 104° F) at sea level
10% to 90%, noncondensing
28° C (82° F) max
Up to 2400 m (8000 ft) at max temperature of 36° C (96 0 F)
150 W (546 Btu/hr)

Operation
Start Time
Stop Time
Revolutions per Minute

50 s
30 s
2400

1-3

Power
Drive

Single-phase

Starting Current

5 A (rms) max, 120 Y, 47/63 Hz
2.5 A (rms) max, 240 Y, 47/63 Hz

Mechanical Drive
Size

48 em wide X 63.4 em deep X 27 em high (19 in wide X 25 in
deep X 10.5 in high)

Weight

33.75 kg (75 Ib)

Mounting

The drive mounts on slides in a standard 48.26 em (19 in) cabinet
(provided). Recommended max height from floor is 18.9 em (48
in).

Cartridge

Em bedded servo
Top loading cartridge with 2 data surfaces.

Standard Cable Lengths
Power cord

2.74 m (9 [t)

Controller to First Drive

1.83 m (6 ft)

Drive to Drive

3.05 m (lOft)

Optional Drive Cables

Cable

Part No.

Length

BC20J-20
BC20J-40
BC20J-60

7012122-20
7012122-40
7012122-60

6 m (20 ft)
12 m (40 [t)
18 m (60 ft)

NOTE
Total length of cable(s) from controller to the last
drive must not exceed 30 m (t 00 ft).

1-4

CIIAPTER 2
FUNCTIONAL DES,C'RIPTION
2.1 INTRODUCTION
The RL V 12: controller interfaces the RLOI and RL02 disk drives to a 16-, 18-, or 22-bit LSI-II bus.
One RL V 12 can support up to four RLOI and RL02 disk drives in any combination. The RLV 12 mod~
ule, M806I, has the LSI-II bus transceivers and decoders. programmable registers. the controller timing and sequence logic, and the data formatting circuits necessary to read and write on the disk.
The main sections of the RLV12 are shown in Figure 2-1. The RLVI2 has the following five programmable registers.
Control/status register (CSR)
Bus address register (BAR)
Disk address register (DAR)
Multipurpose register (MPR)
Bus address extension register (BAE) (22-bit addressing only)
These registers can be addressed like any memory location. The CSR is always written last of these five
registers because it starts the microsequencer operation.
An RL V 12 program can select 16-, 18-, or 22-bit LSI-II bus addressing. When not enabled for 22-bit
addressing, the module is software compatible with and can replace the RL V 11 or RL V2 L
To issue a command to the RL V 12, the processor first places the address of the register on the LSI-II
bus. Then it places the data on the bus. The RL V12 controller decodes the address and channels the
data to the correct register. The processor loads the bus address register (BAR) with bits 0 through 15.
If 18- or 22-bit addressing is used, the processor also loads the bus address extension register (BA E)
with bits 16 through 2 I. Bits 16 and 17 may also be written to or read from the control/status register
(CSR). The CSR is loaded in the same way.
Once the command is written into the control/status register, the RL V 12 starts a microsequencer routine. The microsequencer decodes the command and branches to an address in the control store
PROMs. There the microsequencer finds a routine for the command issued. The microsequencer then
generates the control signals needed to channel the data through the controller.
Included on the controller are error detection features, such as the memory parity error abort feature
for use with memories that have parity error checking. When reading system memory, data bits] 6 and
17 from tht:: bus are checked for a parity error. If an error is detected, the current command to the
controller is aborted.
Cyclic redundancy checking (CRC) is used to check the serial data integrity from the disk drive. A
CRC check word is created from the data being sent to the disk and this check word is written immediately foHowing the data. When a header or data field is read from the disk, the incoming bit stream and
eRC check word are checked for errors. If an error is detected, a header CRC or a data eRC error
flag is set in the CSR.

2-1

16-,18-, OR 22-BIT

I--BDAL
16, 17

..-L

MEMORY
PARITY ERROR
ABORT LOGIC

r----

DRIVE ERROR

NXM

NXM
~~----~I~P-A-R-E-R-R~ ERROR

,.-L.

SET OPI- OPI
ERROR
FfF

I......-

L-_ _ _ _ _-I

OPI

PHOTOCOl

kiO

i.--

1-...1-_-",\ ~

~/ ~
In

!::

CONTHOlW
INTERRUPT
CaNTHal

iii

...J

I' -

'\..r--,/

BUS
TRANSCEIVERS
AND
.-II
......
AODRESS
'/ '\
UECODER
~

I
..

POWER
OK
BUFFER

~YSo II

em: Clll (;K E Ii II+--r---+------I~

Ill!
CMU

MS elK

CRC

SEND DHIVE COMMAND
DATA
SOURCE
Mux6ATAH WHITEENCODEH+-'
MUl TlPLEXEIl 1-o,.J....;.;.-=,--"';:';;'
r-':";":"'~" PfH:COM
....-l-PENSATION

MUXSEl_.

SY~;CI K

1·11 Mil!. I

ClK SE l

CLOCK
MUX

DH eMU

I,/-

SERDA
SERDATAOUT
DS DATA

SER
~
DATA IN/
I{

CLOCK
II.:? Mill

--T--'

AN!) MUX SELlCr)

tiEN[IIATOIl

MSClK
STATUS elK

~_tSMSCLKIMAINTI

DATA SEPARATOR
OS DATA READ CIRCUIT
I(PHASE lOCK lOOP)

WR DATA PlS
.
RD DATA

~~S~T..:...A:..;.T~U~S~IN~__________________-r____~~~~~~~~~~~~~~~~~~:~~~

SERIAlFIFO
IZER

~~----1

RD DATA
STATUS

MA~NT

READ STATUS

IWORD
DIFFERENCE
COUNTER

1
BPOK

CRC ERR

ZERO BIT-'

,.....-..x./_
. .....,
'
FIFO RAM'
256 X 16

(itNt:IIATOIIS,
tfll'OCUNrHOI.,
CI K SEt
IJATA PATH CON1 HOt

,....--

\vR GA I £

,.....-S-y-~j-r-E~-,--' 8, 2- MH Z

CUNT HUl HEGISn HS
A,U,C, AND 0 PLJLSr.
MLJX~

WRITE MARKER BIT---l

FIFO
INPUT
BUFFER

TSFI,.F_O_l_5_:0_0_ _ _

I I

SlC PLS

SECTOR PULSE

BUF FE R RE G ISTE RS I-_ _ _~W..:..:R..:...IT:....:E:...G;:;.A:..;.T..:...E=___ _ _~

WBITE_(j

....,,~

MICROSEOUENCE R
STATUS FLAGS
CONTROL STORE

CHECK

SHIFT
REGISTER

L---~V' L __--'===~'\
~_ ~
_

tU(,,!;

DA 15:00l\....V
OAR

~V
I /I

01'1 IC()MI'AHL

" - - - IWRITE ONLY)
DISK
ADDRESS

I-

r---~
FIFO
OUTPUT
BUFFER

BUS
ADDRESS
EXTENSION

BAE

HNF

~ I ....,
v
~.-II
.... f - - eus
Ii( V""----''\. BAR ADPRESS/
ttl ~ lweI WOIIO COUNT

WH·NPH

I\.

~
ISCEOAM:C~ISlT
: i:

DR SE L 1
ZERO l

HDR

.---

~ I( .----.)

1\ [) NP R -....,i-r------1

FUNCTION CMDS

DATA lATE

....

~ _J\.~OMA
"

OR SEl 0

!il Lf C I ION

~_____

DR ROY

DRIVE SElECTO

eSR

INT EN (lEI

<=) Iir Gi s1i: I!

OR ERR

DRIVE READY

DRIVE SELECT 1

LOGIC

BUS

,..... DRiVe'l 0
BUS

FATAL ERR H

~ lSI-ll BUS

CNT UP
(ON TRANSFER TO RAM)

. FSMS ClK
WD FOUR (RD NPRI

-f
CNT ON
rON TRANSFER FROM RAM)
PWR FAIL

POK
DISK DRIVE 8US .....
TRANSCEIVERS

Figu rc 2·1

R LV 12 Block Diagra m

The RL V 12 has a 256 X 16-bit RAM to store data for or from direct 111emory access (DMA) transactions. The RAIYl is a first-in, first-out (FIFO) memory that can store up to 256 words of data.
During a write command, a FIFO serializer is used with the FIFO RAM to convert parallel data into
serial format to be written on the disk. During a read command, the FI FO serializer converts the serial
dat.a into parallel data to be loaded into the FIFO RAM.

2.2

BUS PROTOCOL

The bus protocol logic (Figure 2-2) generates the control signals to read from or write to the controller.
This logic uses a DC004 as a bus protocol chip. Two negative logic decoders and one positive logic
decoder provide the read and write signals to the fiv(;: RL V 12 registers: CSR .. BAR. DAR, MPR. and
BAE. The following events occur.
1.

At addressing time, R SYNC H clocks in the address bits (TSDAL 1, 2 and 3). These address bits arc decoded to read or write to the five registers.

The DC004 generates a slave reply signal, SRPL Y H, that becomes BRPL Y L to the processor and completes the LSI-II bus protocol.

=>-

r------'L.A

READ TO
REGISTERS

DECODER
FROM
THREESTATE
BUS

[)-TYPE
FLIP·
F:lOPS
REG SEL C

TS DAL 3

XMIT H

DECODER

TOBUS
TRANSCEIVERS
WRITE
TO
REGISTERS
WR CSR L

lATCH

WR CSR PLS H

WR BAR L

--- WR BAR PLS H
-WR DAR PLS H

Jj-----'--+--if-- RD DAR L

WR DAR L

ler---""--II-RDMPRL

WR MPR L

[ :r-------iL- R 0 BAE L

WR BAE L

WR MPR PLS H
-

WR BAE PLS H.

TS DAL2SEL
TS DAL 1
DATA
R SYNC H

elK

DEV SEl l

R DOUT l

WR PLS H
SEl
BRPL Y [>-----+-&.....(.~
OUT LB

BRPlY L
TO LSI-ll BUS

OUT LB l

IN wDn-~~~---r
DC004
CRDY H-

MRPLY L-

CLK
SINGLE RANK
_ _ _~SYNCHRONIZER
MR 5738

Figure 2-2

Bus Protocol Logic

2-3

A single rank synchronizer monitors controller ready (CRDY) to enable the slave device (the
addressed register). MRPL Y L clocks in CRDY and generates S DEV EN H.

When CRDY is asserted, the RL V 12 is ready to accept another command.

The signals XMIT Hand REC H go to the DC005 transceivers that interface the LSI-II bus
and the 16-bit three-state DAL bus.

2.3 BUS TRANSCEIVERS
The bus transceivers on the RLV12 are DC005s. as shown in Figure 2-3., These transceivers transmit
and receive both data and address information. They interface the LSI-ll BDAL 0-15 H signals and
the RLVI2 TS DAL 0--15 H bus/address signals. BBS7 L must be asserted during address time to
enable the transceivers. The transceivers are controlled by the signal's XMIT Hand REC H from the
bus protocol logic.
The jumper pins connected to the transceivers select the device address and the interrupt vector of the
RLV12.

DCDD5

IN/OUT

DCDD5

} TO/FROM
,THREE-STATE
BUS
, TS DAL 11-14

MATCH H

TO/FROM
l.SI-l1 BUS

BDAL

11_,.{

IN/OUT

}

TS DAL 8, 9, 10,15

MATCH H

{

BDAL 8--10

BBS7 L

TO WIRE
WRAP PINS

ADDR.ESS

ADDRESS

TOWIRE
WRAP PINS

-RD BAE H

VECTQR

XMITH

REC H

TO OTHER DCDD5
BUS TRANSCEIVERS
MA5739

Figure 2-3

Bus Transceivers

2.4 PROGRAMMABLE REGISTERS
The five programmable registers of the RL V 12 interface to a three-state bus (TS DAL BUS). These
registers receive address, data. and control information, via the bus, and they return data and status
information on the same bus.

2-4

2A.1 Bus Address Register (BAR)
The BAR (Figure 2-4) has t\'v'o DC006 binary counters. The BAR is loaded with the 16··bit bus address
to which the first word of a DMA transfer is to be made. The signal \VR BAR L enables the register to
load this address.

SEL BAR
RD BAR L

BUS ADDRESS REGISTER
Dca06

TSDAlS-'V

Dca06
DUAL!
BIN
COUNTER

DUAL!
BIN
COUNTER
MAX·C H
SA

MAX ACRY H

MAX C CRY H

CLK·A

CLK-C

CLK·C

S·C

SoC

WC OFLW

+5 WC
OVER
FLOW

WC BAR LD

we BAR elK l--c:{:)

MJ1 5741)

figure 2-4

Bus Address Register (BAR) Circuit

2.4.2 Bus Address Extension Register (RAE)
The BAE (Figure 2-5) is a 6-bit register for the extended address bits, 16 through 21. For 22-bit addressing, the BAE is loaded from TS DAL 0-5 using a write BAE command.
For I8-bit addressing, the extended address bits 16 and 17 can be loaded either into BAE bits 0 and J or
into CSR bits 4 and 5.

NOTE
Writing CSR bits 4 and 5 modifies BAE bits 0 and 1
and vice versa.
2.4 . 3 Disk Address Register (DAR)
The DAR (Figure 2-6) holds the next sector address to read or write data on the disk. After each sector
is read or written, the contents of the DAR is incremented by 1. The output of the DAR goes to the
DA R serializer.
During a Seek command, the DAR is used for the head selected, the direction to travel, and the cylinder address diff·~rence. During a Read, Write, or \Vrite Check command, the DAR is used for the head
selected, the next sector address to read or write, and the cylinder address. During a Get Status command, the DAR is used to get the drive status and to clear the drive error register of soft errors.
The: DAR serializer has two 8-bit shift registers that load parallel data in and shift serial data aut. The
DAR serializer sends the data to the header compare circuit.

2-5

BI~"

CNTR

T5 DAL 5

BAE21XH

TS DAL 4

BAE 20X H

TS .DAL 3

BAE 19X H

T5 DAL 2

BAE18XH

RD BAE L

WR BAE L

LOAD

INR BAE PLS H

CLK

r---+--------------f D

MUX

8AE
RSLT H

BIN
CNTR

1---'--1- BAE 17X H

r-~_+------------------_;O

TS DAL 4

8AE 16X H

TS OAL
OH

0
\vR CSR L
RD 8AE l

TS OAL 0
T5 DAL 5

lOAD

ClK

TS DAL 1
--WR CSR H

WR 8AE l
1 SEL

INR BAE PlS H
INR CSR PlS H

Figure 2-5

Bus Address Extension Register (BAE) Circuit

BINARY
COUNTER
(1 OF 4)

FROM
THREE-STATE
BUS

T5 DAl 0-15 H
RD DAR L
WR DAR L

DAR

DAR
SERIAL·
IZER

OAO-15 H

-DASHIFTl

lOAD

:.:.:M~S-::C~L:..:.K:..H:..:...__

INC DAR H
WR DAR PlS H

SHIFT
REGISTER
(1 OF 2)
SER OA H

SHFTlO
_I ClK

MARKER H
-SER DA INH l

CLK

INHIBIT

MA 5742

Figure 2-6

Disk Address Register (DAR) Circuit

2-6

2:.4.4 Control/Status Register (CSR)
The CSR (Figure 2-7) is a holding register for the command to the microsequcncer. The register also
holds the int1errupt enable bit, the control1er ready signal, the drive select bits~ and error flags. /\ command to read the CSR gets status information as shown in Table 2-1.

TS DALO

GSR

FO H

TS DAL 1 H
TS DAL 2 H
FROM
THREESTATE
BUS

TS DAL 1

Fl H
F2 H

TS DAL 3 H

IE H

TS DAL 6 H

TS DAl 2

DR SEL 0 H

TSDAL8H

DRSEllH

TSDAL9H
GlK

TS DAL 7 H

TS DAL 3
TO
THREESTATE
BUS

GRDY H

PAR ERR L
F/F

WR GSR PlS H

-GRDY H

OPI H

TS DAL 10

OPI
F/F
K

D/H GRG H

550MS

R DAL 16X H.----

~NF H =-:I;>TS DAL12

R DAL 17X H
DATA FROM
LSI-l1 BUS

PAR ERR l
EN ADD l

NXM
ONE
SHOT

NXM H

TS DAL 13
-~--

NXM
F/F
t-------iC

ERR H

TS DAl15

RD CSR l
MR5743

Figure 2-7

Control/Status Register (CSR) Circuit

When set by the hardware, the controller ready flip-flop indicates that the RL V] 2 is ready to accept a
command. The CRDY bit in the CSR is cleared by software. After this bit is clear, the firmware-generated signal lPLS OP} H starts the OP} watchdog timer.
The watchdog timer allows 550 ms for the controller to complete an instruction. The timer prevents the
controller from taking too much time to perform an instruction and keeping out other instructions. If
the instruction is not complete within 550 ms, the timer clocks the OPI flip-flop, enabling OPI H, which
turns off the controller.

2--7

Some of the CSR status error signals have two meanings depending on the state of the OPI flip-flop.
,When the D/H eRe flag is set without OPI H set. a data eRe error occurred; with OPI H set. a
header eRe error occurred.
When the DLT /HN F flag is set without OPI H set. a data late error occurred; with OPI H set, a
header not found error occurred.
During a DMA transfer, the 1\:X;Vt one-shot allows Io.,us for-the addressed memory location to send and
return BRPL Y L. This one-shot prevents the RL V 12 from indefinitely holding the LSI-II bus. If the
one-shot times out, it clocks the NXM flip-flop, setting NXM H. and releases the LSI-II bus.

If NXM H is set without OPI H set, a nonexistent memory error occurred. If NXM H is set with OPI
H set, a memory parity error occurred. (A memory parity error forces both the NXM flip-flop and the
OPI flip-flop set.)
Any error that occurs also sets status bit ) 5.
Table 2-1

CSR Bit(s)

Status Information

Drive ready (DRDY)
Command function code (FO, Fl, F2)
Extended address bits 16 and 17 (DAL 16-17)
Interrupt enable (IE)
Controller ready (CRDY)
Drive selected (DS)
Operation incomplete (OPI)
Data eRC error (DCRC)
Header CRC error (HCRe)
Data late (DLT)
Header not found (HNF)
Nonexistent memory (NXM)
Parity error abort (PAR ERR)
Drive error (DE)
Error flag' (ERR)

1-3

4.5
6
7

8, 9
10
11
10.11
12
10. 12
13
10, 13
14
15

2.4.5

Control/Status Register Bits

Multipurpose Register C\lPR)

The MPR has three functions and uses different circuits depending on the command being performed.
l.

Word Count Register - During a Read Data or Write Data command, the MPR functions as
a word count (WC) register and uses the same circuit as the bus address register, shown iii
Figure 2-4. Before either command is issued, the number of words to be transferred (the word
count) is written into the MPR. The words transferred go through one of the FI FO buffers to
the FI FO memory (see Paragraph 2.4.6). At the end of each sector read or written, the word
count is incremented. \Vhen the count is complete, the word count overflow (MAX-C H in
Figure 2-4) clocks the word count flip-flop and ends the data transfer.

Status Register - Following a Get Status command, the MPR functions as a status register.
The controller places the disk status information in the FI FO output buffer, shown in Figure
2-8. The disk status word from the selected drive is placed in this buffer and can be read by
reading the MPR. (See Paragraph 4.5.3.)

2-8

lV[emory Buffer Register -- Fol1owing a Read Header command. t.he MPR functions. as a
memory buffer register. The controller places the three header words in the Fl FO memory.
Reading the MPR places the header words, one at a time~in the: FIFO out.put buffer. To read
the three header words requires three successive read MPR instructions. (Sec Paragraph
4.5.2.)

:Z.4.6 FIFO Memory, FIFO Ser.ializer, and \Vord Differenc.e CountC"f
The FI FO memory is a first-in, first-out 256 X 16-bit RAM that can store up to 256 data words. A
FI FO serializer takes serial data from the disk. makes it paralIel~ and places it in the VI FO memory.
The FI FO serializer also takes parallel data out of the FI FO memory makes it serial. and sends it to
the disk. Se1e Figure 2-8.
y

A word diff,crence counter keeps track of the number of words coming from the disk to the FI FO buffer. After four words are read from the disk, the word difference counter signals the microsequcnccr to
start a DMA transaction.

RD FIFO EN L

ADDRESS
GENERATOR

PROM
ADDR
DECODER

RAM ADD 0-7 H

]

TS FIFO 0-15 H

FROM
D PULSE
INC APT H GENERATORS

FIFO OUTPUT
BUFFER

FIFO INPUT
BUFFER
D·TYPE.
F/F
TS FIFO 0-15H

D·TYPE
F/F

RD MPR H
EN OAT H

_T_D_IN_H-----fCLK

DISK STATUS IN H
RD STATUS H
FROM CONTROL
REGISTER C
-RD STATUS H

SER DATA IN H

FROM DATA DS DATA H
SEPARATOR

~OO-15H

Figure 2-8

FIFO
SERIAL-IlER
ODD/EVEN DATA
(SER DATA OUT)

FIFO RAM. Buffers. and Seriatizer

2-9

TO DATA SOURCE
MULTIPLEXER

2.5

DATA SOURCE lVIULTIPLEXER ANDeRe GE7\ERATOR
Data that is to be written on the disk goes to a data source multiplexer (see Figure 2-1). i\1UX SE L 0,
1•. and 2 determine which of the following inputs reaches the multiplexer output.
Serial Input

Source

SER DA (disk address)
SER DATA OUT
OS DATA
eRe

DAR (disk address register)
FI Fa serializer
Data separator
CRe checker/generator

The multiplexer's serial output. rvtUX DATA H. goes to the write encoder precompensation circuit to
be written on the disk. At the same time. a eRe check word is being created by the eRe checker /generator. This check word is then added to the end of the data field of the sector.
When the header or sector is read from the disk. the data is again sent through the eRe checker/generator. Any errors in the data or in the eRe word are detected, and a data eRe (DCRC) or a
header eRC (HCRC) error bit is set.in the control/status register.

2.6 MICROSEQUENCER. CONTROL STORE PRO:\·IS, AND BUFFER REGISTER
The microsequencer decodes the function commands of the CSR and points to an address in the control
store PROMs. where the routine resides, to execute the command. The microscquencer sends an address (PR ADD 0-9 H) to the control store PROMs. (See Figure 2-9.)

PR ADD 0-9

-~LDCTRLC

PR OUT 0-23

LD CTRL B
CONTROL
STORE
PROMS

BUFFER
REGISTER

-T FLAG X H

CRDY H

T MUX SEL 0-2

DEV SEL H

INSTR 0-4

LD CTRL A
TO CONTROL
REGISTER A,B,C
AND PULSE D
GENERATORS

T MUX SEL
RE l
CONDI·
TIONAl
BRANCH
LOGIC

FE: l
SO H
Sl H

SEL

STATUS
FLAGS

STATUS
FLAG
MUX

DUAL
RANK
SYNC

MFIS745

Figure 2-9

Microsequencer. Control Store PROMs. and Buffer Register

2-10

The control store PROiVls receive the address from the microsequencer and. generate a 24-bit microinstruction at the outputs (PR OUT 0-23 H). The PROM output~ go to a buffer register. which is
divided into five fields as follows.
1.
2.
3.
4.
5.

I nstruction field
T MUX SEL field
T FLAG X L (test f1a,g don't care)
Constant field
LD CTRL register field

2.6.1 Buffc~r Register Fields
The instruct.ion field signals (INSTR 0, 1, 2 and 4) go to the conditional branch multiplexer to provide
the microsequencer with the next address to access. These instruction signals generate t.he select inputs
(SO Hand S 1 H) and the enable inputs (FE Land RE L) to the microsequenccr. INSTR 3 goes
directly to the push/pop input of the microsequencer.
The T MUX SEL field signals select one of the status flags to enable the instruction from the conditional branch multiplexer. One of the status flags that go to the status flag multiplexer is enabled to
pass to the dual-rank synchronizer. The status flag becomes T FLAG L and goes to the select input of
the conditional branch multiplexer selecting the instruction field signals from the buffer register.
The T FLAG X L signal from the control store buffer register allows the microcode to branch on a
specific flag as follows.
1.

~v'hen T FLAG X L is low, the instruction in the instruction field is executed unconditionally_
(The state of T FLAG L is a don't care condition.)

Vv'hen a status flag appears on the dual-rank synchronizer" it asserts T FLAG L. If at the
same time T FLAG X L is high (unasserted), the microscquencer conditionally executes the
instruction in the instruction field.

If both T FLAG X Land T FLAG L are high, the microsequencer skips to the next inst.ruction in the control store PROMs.

The constant field has two purposes. It provides a direct input to the microsequencer, and it provides
inputs to load one of three control registers (A, B, and C) and the two D-pulse generators. (See Paragraph 2.7.)
When loadiing a control register or pulse generator. the signals LD CTRL A, B, or C are decoded to
determine which register or pulse generator to load.

2.6.2 Fatal Error Clearing Logic
If a fatal pulse occurs it halts the clock on the RLY 12 and sets CRDY H. CRDY H generat.es ZERO
L, which resets the microsequencer to location zero, where it stays until the controller is restarted
(CRDY is cleared). When the controller is accessed, DEY SEL H clocks and initializes the microsequencer

2-11

2.7

CONTROL REGISTERS AND PULSE GENERATORS

The control signals for the R LV 12 logic. such as clock selection, FI FO control, and data path control.
come from three control registers (r\. B, and C) and two D-pulsc generators. These registers and D~
pulse generators arc loaded from the constant field of the microscquencer's control store buffer. They
provide the following functions.

2.8

Two D-pulse generators. one positive and one negative, provide pulses for clearing, 10crementing, and decrementing the logic.

WRITE ENCODER Al'D PRECO~lPENSAtION LOGIC

The write encoder converts binary data into modified frequency modulated (MFM) data, which is recorded on a disk.
MFM is a magnetic recording method for disk drives, in which a clock signal is encoded in the flux
transitions recorded on the disk. \Vhen reading data from the disk, one can synchronize on the data
transitions, and with a phase-locked loop and MFM decoder, recover the clock and data.
Each bit cell (Figure 2-10) can have a transition at its beginning or at its center or may have no transition at all. Each 1 produces a transition at the center of the bit cell time; a 0 preceded by a I produces
no transition; and a 0 preceded by a 0 produces a transition at the beginning of the bit cell time. Therefore, with MFM encoding, flux transitions are always present even with an all Os or all Is data pattern.

8.2 MHz

SYS (0) H

I
I
I

NRZ WRT DATA

1
MFMDATA

--=-_-'

L-~--'

\.......;.-._ _---'

I
I

WRITE CURRENT

I
0

t+- BIT --tool
I

I
1

.Jl

rL
I

CELL
IIIIR·590B

Figure 2-10

MFM Encoding

A problem with this recording method is that adjacent flux transitions appear to be moved from where
they were written. This is called peak shifting. The direction of the peak shift is linked to the position of
the M FM pulses. Two pulses close together shift the peaks of the read voltage away from each other.
(See Figure 2-11.)

2-12

To offset this peak shifting, the write encoder uses a delay line to shift the data in the opposite direction
to that expected by the peak shift. This shifting of the data is called precompensation.
The delay line has nine taps off it. Each tap delays the data input 5 ns more from its entry point. (See
Figure 2- 12.) All nine taps go to a multiplexer. ~The center tap is a reference line.)
The select lines to the multiplexer come from a PRO\f and binary counter, which keeps a history of the
previous data. The select lines determine whethe:r to advance or delay the new data from the previous
data, creating precompensated .rv1FM data.

BIT CELLS

MFM DATA

DISK TRACK FLUX
REVERSALS

IDEALIZED READ SIGNAL
VOLTAGE PULSE

INDIVIDUAL PULSE
CONHIIBUTION TO VOLTAGE
WAVEFORM

COMPOSITE READ VOLTAGE
WAVEFORM

L--_ _ _---'(4)'--_ _

~~_ _ __

- -1------[-----1 -. . . --~---I·-----I------

I
I

1-1,_____

PEAK SHIFT

~H
MR 59~l

Figure 2-11

Peak Shift \Vaveform

2-13

...---0

8.2 MHZ·

D·TYPE
FF

CRYSTAL
OSC

'-__..,......,f-,,-----If--t C

Pt-- r-t- SYS 0 H

8.2 MHZ
SYS 1 H
SYSO H

DELAY LINE 5 NSiTAP

)

WRT DATA PLS H
TO BUS INTERFACE
TRANSCEIVERS

L . . - - - - - - - t SE LECT·
L-_ _ _ _ _
ABLE
_____________
MUX
~

,.
SEL
..... 1-------1

LD CK

()

r - - - - - t BINARY r-~

~ COUNT.

- - -.... 80

PROM

r- ER

'-I:-~-i--~-+-I"-i

~+R--O--......

SYSOHD

8.2 MHZ

84
PREVI·
MUX DATA /-1- OUS
~
FROM
DATA
DATA SOURCE FLIP.
MULTIPLEXER FLOPS
(1 OF 6)

ADDR

MA 514(,

Figure 2-12

Write Encoder and Precompensation Circuit

2-14

2.9 DATA SEPARATOR READ CIRCUIT
The data separator read circuit (Figure 2-13) take:~ the MF\;1 data from the disk drive and produces
binary data and a clock. This circuit uses a phase-locked loop to generate a clock signal to synchronize:
to the M FM data. (A variable capacitor sets the free-running frequency of the voltage-controlled oscillator (YCO). This frequency is set at the factory and should not .be changed.) Then. the read circuit
decodes the .MFM data. The serial binary data then goes to the FI FO serializer. as DS DATA H. and is
clocked in by OS ClK.
PHASE DETECTOR
UP H

DOWN
F/F
(ASSERTED
DUFtING READ)
E!:!j_OOP lOCK H J
INPUT DATA L
FROM DRIVE
BUS TRANSCEIVERS

INPUT
DATA
F/F
K
o

DELAY LINE 10 N~. T~P)

-0 DET EN l

[.-+-+---1-------"

MARKER
-VCO ClK L

F/F
K

RCE
F/F

UP l
VCO ClK H

74S74
F/F

OS DATA
F/F

ON L

DS DATA H
OS DATA L
TO FIFO
SERIALIZER
AND MARKER
FLlP·FLOP

CRDY L

C66
MA·5747

Figure 2-13

Data Separator Read Circuit

2-15

CHAPTER 3
C()NFIGURA1'ION AND INSTAl.. LATION
3.1

INTI~ODUCTION

This chapter provides the user or installer with information to configure and install the RL V 12 in a 16-.
18-, or 22-bit LSI-] I bus. The user can change the device address. interrupt vector, and memory parity
error abort feature.

3.2

DEVICE ADDRESS SELECTION

Software control of the RLV 12 is by means of four or five device registers - CSR, BAR. DAR. !\'lPR.
and BAE .. Four registers are used for 16- or ] 8-bit addressing: five registers are used for 22-bit addressing. The bus address extension register (BAE) is added for upper address bit. selection for 22-bit addressing. The usual device starting address is as rollov,,'s.

Addressing I\lode

Starting Address (Octal)

16-bilt
18-bit
22-bit

174400
774400*
]7774400

The first register. the CSR, is assigned the starting address. and the other registers arc assigned the
next sequential addresses, as shown in Table 3-1.
The device: starting address is selected by jumpers for bits 3 through 12. These jumpcTs are shown in
Figure 3-1. A jumper from the selected bit to ground (\rI22) decodes a 1; no jumper decodes a 0; and a
jumper to + 5 V (M I 1) decodes an X (don't care) condition. Figure 3-2 shows the R LV 12 device Slarting address format.

NOTE
For 22-bit addressing, bit ..\3 is not decoded in the
starting address.
3.3

BUS SELECTION

The RL V 12 module can be used on ] 6-, 18-, or 22-bit LSI-II buses. \Vhen sent from the factor'y~ the
module operates on 16- or I8-bit buses. To enable the module to operate on a 22-bit bus. install jmnper
M I to M2, shown in Figure 3-1. \Vhen installed. the jumper enables bank select 7 (BBS7) to be deter·
mined by the upper address bits (13-21). \Vhen the jumper is removed, the RL V 12 has an 18-bit mode
bank select: 7 and can replace an existing RL V lIar RL V21 as the disk controller for RLO} and RL02
disk drives.
.

3.4

INTERRUPT VECTOR

The interrupt vector has a range of 0 to 774. The interrupt vector is preset at the factory to 160. The
user may select another vector by changing the jumpers for bits V2-V8, as shown in Figure 3-3. A
connection to VEC TO BUS H (M3. shown in Figure 3-1) generates a 1 for that bit; no connection
genera tes a O.

3.5

INTERRUPT REQUEST LEVEL

The RL V 12 interrupts at priority level 4 determined by the interrupt chip E23, a DCOD3.

3-1

Table 3-1

Address Selection

Device
Address

16-Bit
Addressing

IS-Bit
Addressing*

Addressing

Starting
Address Range

160000-177770

760000-777770

17760000-17777760

Starting
Address

I 74-WO

774400

17774400

No. of
Registers

8 (5 are used: 3 arc not)

Registers
Used

CSR (t 74400)
BAR (174402)
DAR (174404)
MPR (174406)

CSR (774400)
BAR (774402)
DAR (774404)
MPR (774406)

CSR (17774400)
BAR (17774402)
DAR (17774404)
MPR (17774406)
BAE (17774410)

Jumpers Used

Tie \122 (HI")
to l\'f 17. M20.
and M21

Tie M22 ("1")
to M17. M20.
and M21

Vector Range

(}-774

0-774

Standard
Vector

160

Jumpers Used

Tie \-13 ("I")
to \16. M7.
and \-18

TieM3( .. t")
to M6. M7.
and M8

Tie M3 r~I")
to M6. M7.
and M8

22-Bit

Tic M22 ("I")
10 M17. M20,

and M21;
Tie Mil ("X")
to MI2

Interrupt
Vector

*Factory Configuration

3-2

c'---- =J
_Jl

ENABLE CRYSTAL
~M29

IZ.-M28
ENABLE
VCO ClK
M27 M26

V
\

MEMORY PARITY ERROR
ABORT SELECTION
M23

•

TEST POINT
M30
W3

-c=:r

Mll . +~iV
M12·A3
M13· A4
M14·A'j
M15-At3
DEVICE
M16-Al
ADDRESS
M17-A8
PINS

\!3

{ M24
M25

SEE NOTE

Ml0 M9 M8 M7 M6 M5 M4 M3
V8 V7 V6 V5 V4 V3 V2 VEe
TO BUS H
I

~~~ ~~'~O

M20·Al1
M21 . A12

E23

,-------,11 Tl M2~~ --111--------W2

PASS CD PRIORITIES
(CDMG, CIAK)

JUMPER
ASSEMBLY

M2
Ml
ENABLE
22·81T ADDRESSING

NOTE:
THE MEMORY PARITY ERROR A80RT
FEATURE IS AVAILABLE FOR USE
WITH MEMORIES THAT HAVE PARITY
ERROR CHECKING.
THIS FEATURE DOES NOT HAVE TO
BE DISABLED FOR MEMORIES THAT
DO NOT HAVE PARITY ERROR
CHECKING. THE PINS ARE CONNECT·
ED AS FOLLOWS:
CONNECTION

FUNCTION

M23· M24
M24· M25

NO PARITY
PARITY ERROR ABORT

Figure 3-1

RL V12 Jumper Locations

-----

3-3

~~----~r-------~

BANK SELECT 7
FOR 18-BIT
ADDRESSI."ljG

BANK SELECT 7 FOR
22·BIT ADDRESSING
(CONNECT Ml TO M2)

FACTORY
CONFIGURATION
eSR
BAR
DAR
MPA
BAE

M15

M14

! ! ! ! ! ! ! 1 1 !

M21

M20

Ml9

M18

M17

M1S

M13

M12
,

BUS ADDRESS PINS
CONNECT TO GROUND (PIN M22)
TO DECODE A 1_ CONNECT TO +5 V 1PIN M 11)
FOR A DON'T CARE (X) CONDITION.
NO CONNECTION DECODES AO.

774400
774402
774404
774406
774410

figure 3-2

I I

FACTORY
CONFIGURATION

I~~ I

RLVl2 Device Address Format

I I I I I I I I I
V8

1I I I 1I I

160

.1 1 1 1 1 1 1
Ml0

M4 ,

.INTERRUPT VECTOR PINS
CONNECT TO PIN M3
TO DECODt: A 1.
NO CONNECTION DECODES A 0,
MR-5750

figure 3-3

3.6

RLVI2 Interrupt Vector Format

MEMORY PARITY ERROR ABORT FEATURE

When reading the system's optional memory with parity error detection, a parity error will set OP) and
NXM of the CSR. This is a unique error condition that aborts the current command to the RL V 12.
This error abort feature is possible only with memories that have parity data bits.
The RL V 12 is sent from the factory with the memory parity error abort feature enabled. To disable
parity error abort, remove the jumper between pins M24 and M25 and install a jumper between pins
M23 and M24. (See Figure 3-1.) This feature does not have to·be disabled for non-parity memories, as
parity errors are not generated. Parity error abort uses data bits 16 and 17.

3.7

JUMPERS THAT REMAIN INSTALLED

The modulc has two jumpers. \V I and W2. that enable priority signals to pass through the module. The
module has these jumpers installed, and they should be left in.
Jumper

Signal

WI
W2

CIAKI to CIAKO
CDMGI to CDMGO

One jumper, W3. enables the word count rcgister to automatically increment during a DMA operation.
This jumper is used for factory testing and should be left in.

3-4

Two jumpers on the module disable the crystal oscillator and the voltage-controlled oscillator (VeO)
during factory testing. These jumpers should be left in.
Jumper

Oscillator

M26-M27
M28-M29

VCO
Crystal

3. 8 INSTALLATION
The RL V 12 (;an be installed in any quad LSI-II bus slot. The controHer's priority level is based on its
electrical distance from the processor module. Use the following procedure to install the lnodule.
1.

Examine the module to make sure that the base address jumpers and vector address jumpers,
are set correctly. (See Paragraphs 3.2 and 3.4.)

Chcckjumpers M l' and M2 for enabling the correct bank select 7 (BBS7) for the 18- or 22bit LSI-II bus.

I f desired, disable the memory parity error abort feature. This feature can only be used with
system memories that have parity options.. but this feature does not have to be disabled for
non-parity memories. (See Paragraph 3.6.)

I nsert the BC80M controller cable (or equivalent) into J I on the M8061 as shown in Figure
3-4.

I nsert the M 8061 in the selected slot in the LS I-II bus.

Attach the ground strap on the cable to the metal cabinet chassis.

Connect the other end of the BCSOM cable to the back of the first disk drive.

Continue with the disk installation. Refer to the RLOI / RL02 Disk Subsystel1'1 User's Guide
(EK-RL012-UG).

3.9 ACCEPTANCE TESTING
The RL V 12 controller is tested by running the R LV 12 diskless diagnostic test and~ if a drive is attached, by running the diagnostics that exercise the RLOI and RL02 disk drive. The diskless diagnostic
should be run first. The RLV12 diagnostics are available on different media. Contact your local Digital,
sales office for the types of media available and their part numbers.
Run the XXDP+ diagnostics in the following order.
1.

CVRLB RL V 12 Diskless Diagnostic (16-, 18-, or 22-bit mode)

NOTE
\Vhen the RLV12 is confi~:ured for 16- or I8 ... bit addressing, the RLVl1 diskless diagnostic (CVRLA)
is compatible with the RL \'12 diskless diagnostic
and checks the same logic.
2.

CZRLG Controller Test Part 1

CZRLH Controller Test Part 2

3-5

CZRLI Drive Test Part I

CZRLJ Drive Test Part 2

CZRLN Drive Test Part 3

CZRLK Performance Exerciser

CZRLL Compatibility Test

CZRLM Bad Sector File Utility

NOTE
The Bad Sector File lJ tiJity is not a diagnostic test.
I t is used by. field service to examine the bad sector
·file on the disk and to \vrite entries into that file.

M8061

MR 5898

Figure 3-4

RLVI2 Installation

3-6

CHAPTER 4
REGISTERS
4.1 INTRODUCTION
This chapter describes the functions of the bits in each of the five programmable registers.
NOTE
To prevent accidental writing on a disk, the RLV12
synchroniz~_ on controller ready. (C1;l.DY). If tIle
CRDY bit in the CSR changes from clear to set
while the processor is in ODT mode, the next read
access of any RLV12 register produces all Os.
4.2; CONTROL/STATUS REGISTER (CSR)
The control/status register (Figure 4-1) is a I 6-bit, \vord-addressable register with a standard address of
774400 for 18··bit addressing. Bits 1 through 9 can be read or written; the other bits can only be read.
The bit functions are described in Table 4-1.

When the LSI-) I bus is initialized with BINIT L, bits 1-6 and 8-13 are cleared. and bit 7 (CRDY) is
seC Bit 0 (DRDY) is set when the selected drive is ready to accept a command; otherwise, this bit is
cleared. Bit 14 (DE) is clear as long as there is no drive error. Otherwise~ this bit is set and stays set
until the drive error is corrected; or if bit 3 (drive reset) is set in the DAR and the controller is sent a
Get Status command, the DE bit is cleared.
Bit 15 (ERR) is set when there is a drive or controller error in bits 10--14.
At the beginning of each controller command, error bits 10-13 are automatically cleared. At the completion of each controller command, bit 7 is automatically set. (Bit 7 is also set if an error is detected
during command execution.)

4.3 BUS ADDRESS REGISTER (BAR)
The bus address register (Figure 4-2) is a 16-bit, word-addressable register with a standard address of
774402 for I8··bit addressing. Bits 0 through 15 can be rea.d or written; bit 0 is usually written as O. The
bus address register indicates the memory location for the DMA data transfer during a read or write
operation. The: register's contents are automatically incremented by 2 as each word is transferred between the system memory and the controller.
The bus address can be expanded for an 18-bit LSI-II bus by using bits 4 and 5 (BA 16 and 17) of the
CSR or by using bits 0 and 1 of the BAE register.
The bus address can be expanded for a 22-bit LSI-II bus by using the BAE register(BAE 16-21).
NOTE
When using 22-bit mode, writing CSR bits 4 and 5
modifies BAE bits 0 and t :and vice versa.
The BAR is clIeared by initializing the bus (BINIT L).

4-1

Table 4.. 1 CSR \\ford Format

Bit(s)

Name

Description

DRDY

Drive R~ady - \Vhcn set. this bit indicates that the selected drive is ready to receive a command or supply
valid read data. The bit is cleared \yhen a Seck or head selcct operation is startcd and set when tlH: Seek
operation is completed.

1--3

FO- F2

Function Code - These bits are the function code set by soft\vare to indicate the command to be executed.
Function
F2
Fl

0
0
~'O '

I I

I
1

0
0
tt __ '~

0
0
I
I

Octal
Code

Command

Maintenance mode
\Vrite Check
O
• GetStatus ,
,·1 -, ' Seek_' __ -·7·0·
.Read Header
I
\Vrite Data
0
Read Data
1
Read Data Without
Header Check
I

0
I
2

>3
4
·~5

6
7

Command execution starts when CRDY(bit 7) of the CSR is cleared by soflware~ Thc commands are
described in more detail in Chapter 5. The function code is cleared by initializing the bus (BI N rr L).
4.5

BAI6,
BAI7

Extended Address Bits ~ These two bits are the upper-order bus address bits for 18~bit buses. These bits
are read and written as bits 4 and 5 of the CSR. They function as address bits 16 and 17 of the BAR.
Writing bits 4 and 5 of the CSR also writes bits 0 and I of the BAE.

Interrupt Enable -, \Vhen CRDY is asserted, bit 6 allows the controller to interrupt the processor. This
interrupt occurs at the termination of a command. Once an interrupt request is placed on the LSI-II bus.
it is not removed until acknowledged by the LSI-II processor even if IE (bit 6) is cleared. This bit is
cleared by initializing the bus.

CRDY

Controller Ready - \Vhen cleared by software. this bit indicates that the command in bits 1--3 is to be
executed. This bit is set by the controller at the completion of a command. at the detection of an error, or
by initializing the bus. Software cannot set this bit because no registers are accessible while CRDY is o.

8,9

DSO,
DSI

Drive Select - These bits determine which drive will communicate with the controller via the drive bus.
These bits are cleared by initializing the bus.

10-13

EO-E3

Controller Status Errors - These bits are the error code set by the controller to indicate one of the follow~
ing errors.
Error Code
E3
E2

0
0
0
0
0
I
I

Error

0
0
0

0
0
0
0

I
0
I
0

Operation incomplete (OPI)
Data CRC (DCRC)
Header CRC (HCRC)
Data late (DL T)
Header not found (HNF)
Nonexistent memory (NXM)
Parity error abort (PAR ERR)

I
0
0

1
I

0
I

Octal
Code
2

3
4

5
10
11

Operation incomplete indicates that the current command was not completed within the OPt timeout period of 550 ms.
A data CRC error indicates that while reading the data field from the disk, an error was found.
A header CRC error indicates that while reading the header from the disk, an error was found. The CRC
check is performed on the first and second header words. although the second header word is always o.

4-2

Table 4-1

CSR Word Format (Cont)

Bit(s)

)\;ume

Description

10-13

EO-E3

Data late indicates that the FI FO RAM was more than half full and the controller wa~ not able to read the
next sequential sector. This error may occur during a Read \Vithout Header Check command.
Header not found indicates that an OPI timeout occurred vvhitc the controller \"'o1s searching for the COfrect sector to read or write. A header compare did not occur.

A nonexistent memory error indicates that during a D\rfA transfer the memory location address~d did nol
respond with RPL Y within 10 IlS.

A memory parity error abort indicates that a parity error \Vas detected while reading the system's optional
memory that has parity error checking. If ;',n error was detected, the current command to the RLV 12 is
aborted.
14

Drive Error- This bit is buffered from the drive error interface linc. When set. it indicates that the selected drive has flagged an error, the source of which can be determined by executing a Get Status command. DE will not set ERR (bit 15) or CRDY (bit 7) until the usual occurrence of CRDY.

ERR

Composite Error - When set, this bit indicates that one or more of the error bits (bits 10-14) arc set.
When an error occurs, the current operation terminates. and an interrupt routine is started if the interrupt
enable bit (bit 6 of the CSR) is set.
All error bits are cleared by initializiriglhe bus by starting anew command. \vilh the exception of DE and
ERR if they were caused by a drive error.

I l})
15

OPI
0
ERR DE NXM DLT CRC
0
OPI
H
PAR
HNF
CRC 1
ERR
\..

....,.~----------A--J
READ
ONLY

READIWRITE

READ ONLY

MR 57!;t

Figure 4-1

Control/Status Register (CSR)

__________________________

~~~~

Bus Address Register (BAR)

4-3

____________________________J

READI\NRITE

Figure 4-2

MR 5752

4.4 DISK ADDRESS REGISTER (DAR)
The disk address register is a 16-bit. read/write. word-addressable register with a standard address of
774404 for IS-bit addressing. Its contents has one of three meanings. depending on the command being
performed.
Command

DAR Function

Seek

Head selected. number of cylinders to move. direction

Read Data
or \Vrite Data

Head selected, cylinder address, sector address

Get Status

Send drive status to MPR; reset error registers

Th.e DAR is ch~aied by initializing .thebus (BI~ IT L).
4.4.1 DAR During a Seek Command
To perform a Seek command. the program must provide the head selected (HS). direction to move
(DIR), and the cylinder address difference (OF), as indicated in Figure 4-3. The bits arc described in
Table 4-2.
.
.
4.4.2 DAR During a Read, \Vrite, or \Vrite Check Command
For a Read, \Vrite. or Write Check command. the DAR provides the head selected (HS) and the address of the first sector to be transferred (SA). as indicated in Figure 4-4. The bits are described in
Table 4~3. As each sector is transferred, the DAR sector address increments by 1.
4.4.3 DAR During a Get Status Command
Both the CSR and the DAR must be programmed to perform a Get Status command. The DAR must
be programmed as shown in Figure 4-5. Then a Get Status command is placed in the CSR. The DAR
bits are described in Table 4-4.
4.5 MULTIPURPOSE REGISTER (l\lPR)
The multipurpose register is a 16-bit. read/write, word-addressable register. It is accessed using the
standard address of 774406 for IS-bit addressing. Following a Read Header command or a Get Status
command, reading the MPR obtains sector header or drive status information.
Writing to the MPR is used to set the word count. The word count is cleared by initializing the bus
(BINIT L).
4.5.1 Writing the MPR to Set the \Vord Count
Before starting a DMA transfer. the MPR is loaded with the word count. The program must load the
MPR with the 2's complement of the number of words to be transferred. The MPR is written in the
format shown in Figure 4-6. The bits are described in Table 4-5. As each word is transferred, the MPR
is automatically incremented by 1. The reading or writing operation continues until a word count. overflow occurs, indicating that all words have been transferred .
. The word count can range from 1 to 5120 data words. The maximum word count is limited by the
maximum number of sectors available (40) and the maximum words per sector (12S).
NOTE
Once \"f'ritten the word count cannot be read back.
Reading the l\IlPR does not change the word count.

4-4

~~ JOFOI 01 a IHS I a I~~~~]

(RL02 ONLY)
MR 5753

Figure 4-3

Table 4-2

Bit(s)

Name

DAR Dming a Seek·Command

DAR Seek Command Word Format

Description
____I,e"

MRKR

Marker - Must be a 1.

none

Must be a O. indicating to the drive that a Seek command is being issued and that the other bits in the
register hold the Seek specifications.

DIR

Direction - This bit indicates the direction in which the Seck is to take place. \Vhcn the bit is sct. the
heads movetov,,·ard the spindle (to a higher cylinder address). When the bit is cleared. the heads move
away from the spindle (to a lower cylinder address). The actual distance moved depends on the cylinder
address difference (bits 7-15).

none

Must be a O.

Head Select - Indicates which head (disk surface) is to be selec.ted:

5. 6

none

Reserved

7-15

Cylinder Address Difference - Indicates the number of cylinders the heads are t.o move on a Seek.

lower. 0 = upper.

ICA8ICA7ICA6ICA5ICA4ICA3ICA2ICAB~s ISASISA4ISA3ISA2\ SA', SA?}
MR-5754

Figure 4-4

DAR During a Read, \\"rite. or Write Check Command

Table 4-3

DAR Read/\Vrih~ Data Command \Vord Format

Bit(s)

Name

Description

0-5

Sector Address - Address of one of the .:~O sectors on a track. (Octal range is 0 to 47.)

Head Select - Indicates which head (disk ~urfacc) is to be selected: I = lower: 0 = upper.

C;\

Cylinder Address - Address of one of the 256 cylinders for RLOI or 512 cylinders for RL02. (Octal range
is 0 to 777.)

7--15

4-5

Ix x

000
MR 5755

Figure 4-5

Table 4-4

DAR During a Gct Status Command

DAR Get Status Command Word Format

Bit(s)

Name

Description

o·

MRKR

Marker - Must be a I.

Get Status - Must be a I. indicating to the drive to send its status \I/ord. At the completion of the Get
Status command. the drive status word is read into the controller multipurpose register (iVIPR). \Vith this
bit set. bits 8-\5 are ignored by the drive.

none

Must be a O.

RST

Reset - When this bit is set. the disk drive clears its error registcr orsoft errors·before sending a status
word to the controller.

none

Must be a o.

none

Not used.

8-\5

well
Figure 4-6

MR·5756

Writing the MPR to Set the Word Count

Table 4·5

MPR \Vord Count Format

Bits

Name

Description

0-12

Word Count - This is the 2's complement of the total number of words to be transferred.

13-\5

none

Must be all \ s for word count in correct range.

4-6

4.5.2 Reading: the i\lPR After a Read Header Command
When a Read Header command is executed. three words can be sequentially read from the iVtPR. as
shown in Figure 4-7. The first word includes the sector address. the head selected. and the cylinder
address. The s(!cond word is all Os. The third word has the header eRe information.
4.5.3 Reading the lVIPR After a Get Status Command
After a Get Status command is eXGcuted. a status word is stored in the MPR, as sho\\"n in Figure 4-8.
The status word from the selected disk drive includ\!~, information on the functional state of the drive
and ~lny drive lerrors. The bits arc described in Table -+-6.

4.6, BllS ADDRESS EXTENSION REGISTER (BAE)
The bus address extension register is a 6-bit read/write register used to drive address bits 16-21 for a
22··bit LSI-II bus. The BAE has a standard address of 17774410 for 22~bit addressing. A write to the
BAE loads TS DAL 0-5 into BAE 0-5, shown in Figure 4--9. Reading the BAE enables bank select 7
(BBS7 L) to the LSI-II bus .. (A jumper must be connected between Ml and M2 on the controller to
. enable 12-bit ,tddressing; see Chapter 3.) \Vhen address bits 13-21 are all Is, the RL V 12 drives BBS7
L
direct dat.a to the I/O page.

The two least significant bits of the RAE (bus addre~.s lines 16 and 17) are mirrored in bits 4 and 5 of
the CSR. The same bits can be read or written as CSR bits 4 and 5 or BAE bits 0 and I.

NOTE
Writing CSR bits 4 and 5 modifies RAE bits 0 and 1
and vice versa.
The BAE register is cleared by initializing the bus (BINIT L).

~vs6RDlcA8IcA7IcA6IcAs[cA4IcA3ICA2[C; ICAol HS lSA5fATA3IsA2IsAllsA~1
15

~~~D I a I 0 I 0 I 0 ] 0= I 0 I 0 I 0 I 0 I a I 0 I 0 10 Ii. 0 I a I
3RD
WORD

~~~~~~~~~~~~-~~~~~~~-bT-~~~

CRC14

Figure 4~7

CRe8

CRC12

CRCS

. CAC4

CACO

CRC2

Reading the MPR After a Read Header Command
(Three Header Words)

ISPErGE\ vc IOSE\ OT

EOEIHCEI WL I

BH ISTC\STS\STAI

I I I I

'---y----'

SKTO

STATE
MR 5758

Figure 4-8

Reading the MPR After a Get Status Command

4-7

Table 4-6

:\IPR Status Word Format

Bit(s)

Name

Description

0-2

STA.
STB.
STC

These bits (A. B. and C) define the state of the drive as follo\\-s.

c
o
o
o
o

.-\

State of nrhe

0
0
I
I
0
0

0
Load state
I
Spin up
0
Brush cycle
1
Load h~ads
I
0
Seek track counting
1
I _ Seek linear mode (lock on)
. -1 ____ l :'-0· . Uri-load h-ea-ds
-~r--=-< __ ~ ____ ~ i_~::-::'~Sp-i~~do~~n~_"~: 3

__ Bl-L

Heads Out - Asserted when the heads are over the disk

Cover Open -- Asserted \I.,·hen the cover is open or the dust cover is not in place.

.HS

Head Select - I ndicatcs the head selected: I = lower. 0 = upper .

Drive Type - Indicates the type of disk drive: 0 = RLO I, I = RL02.

DSE

Drive Select Error - Indicates multiple drive selection is detected.

Volume Check - VC is set every lime the drive goes into load heads state. This asserts a drive error at the
controller, but not on the front panel. VC is an indication that the program docs not know which disk is
present until it has read the serial number and bad sector file. (The disk might have been changcd while
the heads were unloaded.)

\VGE

\Vritc Gatc Error - Indicates that the write gate \Vas asserted when the drive was not ready, the sector
pulse was asserted, or the drive was write-locked.

SPE

Spin Error - Indicates that the spindle did not reach full speed within a specific time, or it is turning too
fast.

SKTO

Seek Time Out - Indicates the heads did not come onto track within a specific time during a Seck command.

\VL

\Vrite Lock - Indicates write lock status of selected drive: 0 = unlocked; I = protected.

HCE

Head Current Error - Indicates write current was detected in the heads when write gate was not asserted.

WDE

\Vrite Data Error _. Indicates write gate was asserted. but no pulses were detected on the write data line.

Brush- Home - Asserted. \I.-hen the brushes arc not over the disk.

MR 5899

Figure 4-9

BAE Register \Vord Format

4-8

CHAprrER 5
COMMANDS
5. t INTRODUCTION
This chapter describes the commands that are sent to the control/status register. FO, F 1, F2. to perform
a specific disk function. The number in parentheses afteT each command is the octal code for the conl~
mand.
Aprercquisiteto issuinganycommand"isthat~CRDY (controller ready) is set in the CSR (bit 7). Software cannot set thIS bhandcannot accessanY'-fegister if this bit isO.
At the start of each new command, the error bits in the 'CSR"(bits 10-13) are automatically cleared. At
the completion of each command. the CRDY bit is automatically set. (CRDY is also set if an error is
detected during command execution.)
•

5~2

......

0>-

WRITE ('HECK
Prerequisite: The disk heads must be placed at the correct track by issuing a Seek command if neces-"
sary. The BAR must be loaded with the address of the first location of the data block in system memo~
ry. The word count of the data block length must be loaded in the MPR. The DAR must be loaded with
the starting disk address location.
The Write Check command is used to verify that data was written on the disk correctly. It is used: after
writing a block of data on the disk by the Write Data command.
The Write Check command reads this same block of data and compares it with the data in the computer's system memory. Because this comparison is performed in the controller, this source data must
be transferred out of memory into the controller~s FI FO buffer. A bit-by~bit comparison of the header
on the disk and the contents of the disk address register checks for a header match,"
Once a header match is found and the header CRe validates the match. the 128 words of data are read
from the disk. This data is then compared with the serial data coming out of the FIFO serializer (SER
DATA OUT). A compare error or a data eRC error sets bit 11 in the CSR.

NOTE
When writing only a partial sector (less than 128
words), words with all Os are used to fill the remaining portion of the sector.
5.3 GET STATUS (2)
Prerequisite: The software should first verify that the controller ready bit is set. (The drive does not
have to be ready.) Then a status request word must be loaded into the DAR. Bits 0 and 1 must be set;
bit 3 (reset) can be either 0 or 1; and all other bits must be Os. (See Paragraph 4.4.3.)
A Get Status command in the CSR asks the selected disk drive to return information about its current
operation and error status. I f the reset bit (bit 3) is set in the DAR, the disk drive first clears its error
register of all slOft errors before sending back the drive status. When the drive sends back its status
word, it is stored in the FI FO buffer and can be acces.sed by reading the MPR.

5-1

OROY (drive ready) does not have to be set to issue a Get Status command. For example, a Get St.atus
command can be issued during a seek operation or when the drive is in its load state.
5.4 SEEK (3)
Prerequisite: The present location of the disk head must be known. This can be determined with a Read
Header command. Then the software must compute the cylinder address difference (OF) needed by the
drive to move the heads to the new location. Then the DAR must be loaded with the head positioning
information. The OAR must include the number of cylinders to move (bits 7-15), the head select bit
(bit 4), and the direction to move (bit 2). Bits 6, 5, and 1 must be set to 0; bit 0 must be set to 1.

The Seek command shifts the contents of the DAR to the disk drive. The DAR contains the head selected for the next data transaction, the cylinder difference address, and the direction of movement.
Once the drive receives this head positioning information, it moves the head to the new track location.
5.5· READ HEADER (4)
Pr~requisile: A Get Status command must be issued and DRDY must be seti'n theCSR,.

The Read I-leader command· reads the first header found on the selected drive and stores the three .
header words in the FI FO RAM. The first word, \VD I, includes the cylinder address, the head selected, and the sector address. The second word, WD2, is all zeros. The thirdword, WD3, has the head- .
er eRe information. These words can be read from the FIFO RAl\1 buffer by consecutive re.ad MPR
instructions: Three readMPR instructions are needed to read three FIFO words. Reading the first
header word provides enough head positioning information to permit software computation of the cylinder difference for another Seek command to a new track address.
5.6 WRITE DATA (5)
Prerequisite: The head must be loaded at the correct track. by issuing a Seek command if necessary.
The 2's complement of the words to be written (word count) must be loaded into the MPR.

The Write Data command enables the controller OMA circuitry_ The RLV12 becomes LSI-II bus
master, and data words are loaded into the FIFO buffer. \Vhen the drive is ready, header information is
read from the disk and compared with the first sector address stored in the DAR. Once a header match
is found. the FIFO data is written on the disk in sequential sectors until the word count is complete. The
BAR and word count are incremented for each word transferred. If only part of a sector is filled by the
new data, the rest of the sector area is filled with Os. At the end of the sector, the sector part of the
OAR is incremented. At the end of a transfer, CRDY is set and an interrupt is made if I E is seL
5.7 READ DATA (6)
Prerequisite: The head must be loaded at the correct track, by issuing a Seek command if necessary.
The 2's complement of the words to be read (word count) must be loaded into the MPR.

The Read Data command causes headers to be read from the disk and compared to the sector address
stored in the DAR. When a header match is found, disk data words are transferred into the FI FO memory. Both the BAR and word count are incremented for each word transferred. After four words are
read from the disk, the microsequencer starts a DMA transfer on the LSI-II bus. The data transfer
ends when the word counter overflows. I f the word count is not complete, the next sector is read. Otherwise, CRDY is set and an interrupt is made if I E is set.
5.8 READ \VITHOUT HEADER CHECK (7)
Prerequisite: The location of the sector with the bad header must be known. The BAR must be loaded
with the starting memory location to place the words to be read. The MPR must be loaded with the
word count in 2's complement form.

5-2

The Read \Vithout Header Check allows the recovery of data if the headers cannot be read. If header
not found (HNF) or header CRC (HCRe) errors are found on a sector. then data cannot be recovered
by the usual Read Data command.
A Seek command must be issued to position the head on the sector with the bad header. Then the sector
preceding the bad sector must be found by performing consecutive Read Header commands. Finally a
Read \Vithout Header Check command must be issued within 300 IJS to recover the data in the b~ld
sector. The BAR and word count are incremented for each word transferred. Data eRe is checked at
the end of a sector. If the word count is not complete, the next sector is read. Otherwise, CRDY is set
and an interrupt is made if I E is set.

NOTE
The DAR is automaticalll incremented after each
sector is transferred.
5.~~ .,!\lA·INTIENANCE FUNCTION (0)
. Prerequisite: The BA R must be set to the first location of a lest data buffer. The \vord count register
must be set to transfer 511 words (11770 1~). Too large or too small a \VC results in a II N F error. (To
be compatible with RL V 11 software, a we of 510 should not be used.)

The maintenance function allows the RL V 12 to perform a self-test operation. This function is used to
test the controller and may be 'executed with-or without a disk drive attached. The maintenance function performs six internal testsas.follows .. The DAR is incremented after completion of each test: .
Test

Function

1 and 2
3
4
5
6

Check internal logie
Checks DMA transfers
Checks the eRC of (DAR -f... 3)
Checks the eRe of (DAR + 4)
Checks the CRe of (CRe of DAR + 4)

CAUTl[ON
Memory locations are modiified by this function.
Under DMA control, 256 words are transferred from memory. beginning at the starting address in the
BAR through BAR + 7768, to the FI FO RAM. Then all but the last word is transferred back into the
next 255 memory locations, starting at BAR + 1000g through BAR + 17748_
Next, the contents of the DAR are used to test the serial read/write data paths. The data uses an internalloop and is not transmitted to the disk drive. The CRe of the DAR + 3 and the CRC of the (CRe
of DAR + 4) are stored in the FI FO RAM and can be read by reading the MPR. The DAR's low byte
(bits 0-7) holds its original contents + 6.
The DAR's high byte (bits 8-] 5) is not incremented even when an overflow occurs out of the low byte.

5jO EXAMPLES OF USING COlVIIVIANDS
Paragraphs 5.10.1 and 5.10.2 provide examples of the use of RL V I 2 commands in software programs.

5-3

5.10.1 Seek Operation
The following example illustrates the sequence of events for programming a seek operation.
t.

Issue a Read Header command to the desired disk drive and wait for an interrupt request or
wait for CRDY.

Check error flag in the CSR.

Read the header word from the MPR.

Compute the difference address and the direction for the seek.

Write the difference word into the DAR.
'--

Issue the .S~ekcommand to the drive and wait for seek to becom-pleted as ind.!catcd by __
~,~.'..: 0 R~P y.. . -~; .. ,

6.
7.

. Check error flag in the CSR.

Steps I ~ 2 and 3 above are not needed for the next Seek commands if the software program keeps the
current cylinder address.andhead selected in memory.
. .
, Reading sequential headers gives head position and present direction so the program can optimize the
shortest distance to the new location.

5. t 0.2 Data Transfer Operation
The following example illustrates the sequence of events for programming a data transfer (read or
write) operation.
1.

Perform the steps of the seek operation previously described.

Write the bus address in the BAR.

\Vrite the extended bus address in the BAE if using 22-bit addressing.

Write the DAR with the cylinder address, head selected, and sector address of the first disk
location to be transferred.

Load the MPR with the word count (2's complement of words to be transferred).

Issue a Read Data, \Vrite Data, or \Vrite Check command in the CSR.

Wait for interrupt or test for CRDY.

Check the CSR for an error flag.

Seek commands or data transfer commands may be given to other drives between issuing a Seek to the
first drive and issuing a data transfer command.
As soon as a Seek command is issued to the first drive, it returns an interrupt and sets CROY. A Seek
command may be given to another drive while the first drive is seeking. No interrupts occur when all
the seeks arc complete, so as soon as all Seek commands are issued, data transfer commands may be
issued. Starting with the drive that was given the shortest seek distance makes it possible for the drive
that completes its seek first to immediately perform its data transfer and interrupts when done.

5-4

5.11 ERROR RECOVERY
Errors can be detected and flagged in the R LV 12 and RLO 1/R L02 subsystem. Some of the errors can
be recovcred; that is, if the operation is tried again, the error may not occur again. Some of the CrTl)rS
are fatal and could result in loss of the data, or damage to the media or equipment. The errors are listed
with the recommended action in Table 5-1. The following examples suggest the kinds of questions to
consider when programming error recovery routines.
The type of error is a factor in determining how many times to retry the operation. For example. a data
late (DLT) error could be caused by a hardware system failure. but it could also be the result of bus
activity by other I/O devices exceeding their throughput capability for a short duration. In the laler
case, the operati.on could be successful on the first retry.
, 'The rate of Cr~Qr·.~qc~~j-r~'~ce·is a good i~dicator Q'(system perforh1ance. Ane-l'ror loggIng routine should
be used' to oottli"n ihis information. If therale of DLT errors increases, it could indicate hardware s\'stem failures,' orit cou14 i!1dic~te th~t the system is reaching its throughput capacity in its present c;nfiguration.······

Another:c\(a~~lic'~-f applyingpt~cliCalto'nsi-d'enitlont(ran error is with a header not f;und (HNF) 'crror. After a rctry,jJ the error occurs again, then possibly the head is not positioned over the correct.
track. If a read header operation is performed and the address for the media is examined, the currcnt.
cylinder and head can be determined to see if it is a position problem. If it is not, then possibly there is a
bad spot on the media and another area should be tried. I f there is a bad header, that sector address
should be entered into the Bad Sector File on the disk and the software should not use this bad sector.
Error log files should be maintained and consulted to help determine error causes. \Vhen an error occurs. the program should log it with facts such as the contents of the registers, the stat.us of the unit, and
whether or not a retry was successful. The more complete the error log, the faster the cause can be
diagnosed.

5-5

Table 5-1

Controller Status Errors

Controller
Error

CSR
Bit(s)

Recommended Action

OPI

Operation incomplete; retry a limited number of times.

DCRC/HCRC

Data or header CRC error; retry a limited number of times. Record the contents of the
l)AR.

DLT

Data late; retry.

HNF

10,12

Header not found; perform a Read Header command and verify cylinder.

NXM

Nonexistent memory; retry once. ~ccord thcco!1t~nts of t h~ BA R.

Paritl~ri-or .
.... 10, 13

Abort
Drive -Error

14 .

The comma~d t? the 'controller is aborted; retry.
Perform a Get Status command and check M PR for disk drive status errors: sec Table 5-2.

Table 5-2

Disk Drhe Status Errors

MPR Drive

Drive
Error

Status Bit

Recommended Action

Cover open; close cover.

DSE

Multiple drive selection is detected. Retry once before telling operator to verify unit select plug.

WGE

Write gate error; retry. Drive is not ready. drive is write protected. or drive has another error.

SPE

Spin error: rctry.

SKTO

Seek time out; reset drive and wait for 1.5 second before sending another Seek command.

Write lock: drive is write protected.

CHE

Current head error. This error is fatal; do not retry. Write current is detected in the heads.

WDE

Write data erro~. This error is fatal: do not retry. No transitions are detected.

5-6

CHAprrER 6
DISK DRIVE
6.1 INTRODUCTION
The RLV12-AK and the RLV22-AK come complete with an RLOI or RL02 disk drive, respectively_
The following switches and indicators are found on the front of the disk drive (see Figure 6~1).
Run/Stop switch with LOAD indicator
Unit Sehect plug with READY indicator
FAULT indicator
- WRITE PROTECT switch and: indicator
Power ON/OFF control is a circuit breaker switch on the back of the disk drive. Operation of this
switch will n(>t-damage the drive; however; this SWilChisusirMlylefr ON:- -- -~ -- ---------- ---- .. -_.--The user can select the voltage and range for each disk drive on the back of the drive.

LOAD
(RUN/STOP)

READY
(UNIT SELECT)
WHITE
PROT
MR-1860

Figure 6·1

RLOI/RL02 Disk Drive (Front View)

6-1

6.2

USER SWITCHES AND INDICATORS

This paragraph provides information on each switch and indicator.
Run/Stop Switch with LOAD Indicator - The run/stop switch when pressed. energizes the spindle motor. When pressed again, the switch turns off the spindle motor as long as the heads and brushes are
home. I f the heads are loaded, pressing the switch causes the heads to unload and then turns off the
spindle motor.
The switch has a mechanical memory. If the spindle motor is energized and the main power is lost for a
short time, the spindle motor energizes again.
The LOAD indicator is on when the spindle is stopped. head is home, brushes are home~ and the spindle
. motor is not energized. A cartridge can be loaded when this indicator is lit~

. t)-"iJ~e.i~,ct~~ugi;:~j~.b ~READ_Y:·I_l}.di«;.at{);..;~~Jh~_:u~n~t. s~t~fI~~pl~gjs:.a' --ca!n~ bu'ttQn:lh~li:-is'iris:cxtcd .ina

·'

.. ·sw_it¢h"·:Tne:sWitcll_c~()ri"tac·tsare·.bihary en2~Q~.ed for'.1he.ullitsclcctnutiiber (O,],':2~' o ( 3) orithe'c~Hn- :
buttqn. ::T~he READYjndicator lights to-indicat~ a drive r.e.ao.y. condition; that is, the heads-are" knlded
on a cyiinder rea.dy for a read or a write operation.
. -- .
. ~
-". - .
.

' .

FAULT "Indicator,;... The FAULT indicator Gomes on whe.n an. error c~ndltion occurs in the drive.

WRI]?EP.RO:fECT:.:switch··-and Ifldicator:~:The·\VRlTE ...PR0TECI ·:swlt~h>--wh_en pressed~.'scts t"he
drive in \vrite protect mode. If the drive is in the processor writing atthe time that the switch is
pressed, writing continues until the next sector pulse. The WRITE PROTECT indicator is on whe:n the
write protect function is enabled. Pressing the \VRITE PROTECT switch again turns' off the write
protect mode and indicator.

6.3 110/220 VOLTAGE AND 1"\ORi\tlAL/LO\V VOLTAGE RANGE SETTING
The voltage selection and voltage range are each set by a terminal block cover, shown in Figure 6-2.
They should be set according to Table 6-1.
For systems operating with low line voltage. proceed as follows to change the NORMAL/LOW terminal block cover.
1.
2.
3.
4.

Remove the two screws from the NORlVfAL/LOW terminal block cover.
Withdraw the cover and reinsert it turned upside down.
After insertion, "LOW" must be showing through the small window in the cover.
Replace the two screws.

For systems operation at 220 Vac~ 50 or 60 Hz, proceed as follows to change the voltage selection.
1.
2.
3.
4.

Remove the two screws from the 110/220 terminal block cover.
Withdraw the cover and reinsert it upside down.
After insertion, H220" must be showing through the small window in the cover.
Replace the two screws.

6-2

NORMAL/LOW
TERMINAL BLOCK
. COV~R

TERMINA T 9R

MR 6584

Figure 6-2

RLOI/RL02 DJ!sk Drive (Rear View)

Table 6-1

Voltage and Range Selector Setting

Line Voltage

110/220
Setting

NORMAL/LO\V
Setting

90-105 Vac
100-127 Vac
180--210 Vac
200-254 Vac

110
110
220
220

LOW
NORMAL
LO\V
NORMAL

6-3

FEB 82/t~
EK-RLV12-C ~ ,

RLVi2 Disk Controller
Configuration Sheet
OPTIONS INCORPORATING THE RLV12

MODEL
NUMBER

MODULE
QTY COMPONENTS NUMBER DESCRIPTION

RLV12
RLV22-AK

1
1
1

RLV12
RLV12
RL02-AK

MS061
MS061

DISK CONTROLLER
DISK CONTROLLER
10.4 MB CARTRIDGE DISK DRIVE

The R LV12 is a R L01 /R L02 cartridge disk drive controller contained
on one quad-height multilayer module (M8061). The R LV12 may reside in any quad- or hex-size 16-, 18-, or 22-bit LSI-11 backplane and
can support up to four R L01 /R L02 disk drives in any combination.

NOTE: BCSOM CABLE SHIELD SHOULD BE CONNECTED TO CHASSIS GROUND
AT BOTH ENDS OF THE CABLE,

The R LV12 transfers data to and from the LSI-11 bus using direct
memory access (DMA) techniques. This allows data transfers to occur,
without processor intervention.

The R LV12 contains the following features.
•

Single quad-height module requiring no C-D interconnect.

•

Supports DMA data transfers in 16-, 18-, or 22-bit addressing modes.

• Software compatible with R LV 11 controller in 16- or 18-bit mode.
•

Factory configured to support 22 -bit addressing with a backplane such
as the H9275-A.

•

Controls from one to four R L01 /R L02 drives.

•

Memory parity error abort feature for use with memories that have
a parity detect option .

c:
0

';;
C\l

0
0
a.

....
c:

E
a.
'5
0w

]

:!?
0

...en
@

....

.c:

>a.
0

,..

Table 1
FUNCTION

FACTORY CONFIGURATION

DESCRIPTION

MEMORY PARITY
ERROR ABORT
VCO CLOCK
CRYSTAL CLOCK

NO JUMPER BETWEEN M23 TO M24
INSTALL JUMPER BETWEEN M24 TO M25
INSTALL JUMPER BETWEEN M23 TO M24
NO JUMPER BETWEEN M24 TO M25
INSTALL JUMPER BETWEEN M26 TO M27
INSTALL JUMPER BETWEEN M28 TO M29
NO JUMPER BETWEEN M1 TO M2
INSTALL JUMPER BETWEEN M17 TO M20
INSTALL JUMPER BETWEEN M21 TO M22
INSTALL JUMPER BETWEEN M20 TO M21
INSTALL JUMPER BETWEEN M1 TO M2
INSTALL JUMPER BETWEEN M11 TO M12
INSTALL JUMPER BETWEEN M17 TO M20
INSTALL JUMPER BETWEEN M21 TO M22
INSTALL JUMPER BETWEEN M20 TO M21
INSTALL JUMPER BETWEEN M3 TO M6
INSTALL JUMPER BETWEEN M7 TO M8
INSTALL JUMPER BETWEEN M6 TO M7

ENABLE ABORT*
DISABLE ABORT
ENABLE*
ENABLE*
16 BIT = 174400
OR
18 BIT = 774400

STANDARD
DEVICE
ADDRESS

22 BIT = 17774400*

STANDARD
VECTOR
ADDRESS

Figure 2

160*

ENABLE CRYSTAL
......--M29
:>-M2S
ENABLE
VCOCLK
M27 M26

\1
A

TEST POINT
M30

-c=J-

*FACTORY CONFIGURATION

Table 2

JUMPER LOCATIONS

JUMPER CONFIGURATION

STANDARD REGISTER ASSIGNMENTS
ADDRESS

MIl . +5V
M12· A3
M13· A4
M14· A5
MI5 A6
DEVICE
M16· A7
ADDRESS
M17 . AS
PINS
MIS A9
M19 A10
M20

;

MEMORY PARITY ERROR
ABORT SELECTION
M23
M24
{
M25

.. .

M9 M8 M7 M6 M5 M4 M3
V7 V6 V5 V4 V3 V2 VEfTOBUSH
~

DE"

CONTROL/STATUS
BUS ADDRESS
DISK ADDRESS
MULTI-PURPOSE
BUS ADDRESS EXTENSION
RESERVED 1
RESERVED 2
RESERVED 3

16 BIT

18 BIT

22 BIT

174400
174402
174404
174406

774400
774402
774404
774406

17774400
17774402
17774404
17774406
17774410
17774412
17774414
17774416

CONFIGURABLE RANGES

16BIT MODE

ADDRESS
VECTOR

160000-177770

18 BIT MODE
760000-777770

0-774

Figure 1

BANK SELECT) FOR
22-BIT ADDRESSING
ICONNECT Ml TO M21

22 BIT MODE
17760000-17777760
0-774

JUMPER
ASSEMBL Y

PASS CD PRIORITIES
ICDMG, CIAK)

Figure 3

M2
Ml
ENABLE
22·BIT ADDRESSING

VECTOR CONFIGURATION

ADDRESS CONFIGURATION

~21

"'20

M19

M18

"A1l

M~6

M15

r r 1

M14

M13

BUS ADDRESS PINS
CONNECT TO GROUND IPIN M221 TO DECODE A LOGICAL ONE. CONNECT
TO +5V IPIN Ml 11 FOR A DON'T CARE IXI CONDITION. NO CONNECTION
DECODES A LOGICAL ZERO.

,M10

M4,

INTERRUPT VECTOR PINS

Ml?

CONNECT TO PIN M3 TO DECODE A LOGICAL ONE.
NO CONNECTION DECODES A LOGICAL ZERO,