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EK-KXJCA-IN-001

December 1986

52 pages

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Document:	KXJ11-CA Single-Board Computer Installation Guide
Order Number:	EK-KXJCA-IN
Revision:	001
Pages:	52
Original Filename:	http://bitsavers.org/pdf/dec/qbus/EK-KXJCA-IN-001_inst_Dec86.pdf

OCR Text

EK-KXJCA-IN-001

KXJ11-CA
Single-Board Computer.
Installation Guide

EK-KXJCA-IN-001

KXJ11-CA
Single-Board Computer
Installation Guide

Prepared by Educational Services
of Digital Equipment Corporation

1st Edition, December 1986

Copyright @ 1986 by Digital Equipment Corporation.
All Rights Reserved.
Printed in U.S.A.
The reproduction of this material, in part or whole, is strictly prohibited. For copy
information, contact the Educational Services Department, Digital Equipment
Corporation, Marlboro, Massachusetts 01 7 52.
The information in this document is subject to change without notice. Digital
Equipment Corporation assumes no responsibility for any errors that may appear in
this document.
The following are trademarks
Massachusetts 01754.

mamaD!DTM

Q-Bus
Rainbow
RSTS
RSX
RT
UNIBUS

DEC
DECmate
DECUS
DECwriter
DIBOL

KA630
MASSBUS
MicroVAX
PDP
P/OS
Professional

Digital

Equipment

Corporation,

VAX
VAXELN
VMS
VT
Work Processor

Maynard,

Contents

Chapter 1 - Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-1
Chapter 2 - Selecting Operating Features. . . . . . . . . . . . . . . . .. 2-1
2.1 Boot/Self-Test Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
2.2 Q-Bus Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-8
2.3 Q-Bus Base Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-9
2.4 DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.5 Locked Instruction Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.6 BREAK Enable Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2. 7 HALT Option Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.8 Power-Up Option Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.9 PROM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.10 SLU1 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.11 SLU1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.12 SLU1 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.13 SLU2 Channel A Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.14 SLU2 Channel B Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.15 SLU2 Channel B Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.16 Real-Time Clock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

Chapter 3 - Power Supply Considerations. . . . . . . . . . . . . . . . .. 3-1
Chapter 4 - Installing the KXJ11-CA in a Backplane. . . . . . . . . .. 4-1
4.1 Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . ..

4-3

Chapter 5 - Connectors and External Cabling . . . . . . . . . . . . . .. 5-1
5.1 Parallel I/O Interface (J4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.2 Serial 110 Lines (J1, J2, J3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.3 Loopback Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

5-1
5-2
5-8

Chapter 6 - Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-1
6.1 Error Detection and Reporting with the LEDs. . . . . . . . . . . . . . . . . ..
6.2 Diagnostic Testing with XXDP+. . . . . . . . . . . . . . . . . . . . . . . . . ..

iii

6-1
6-3

Figures
2-1 KXJ11-CA Jumper Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2-2 Memory Mapping - PROM in Low Melnory. . . . . . . . . . . . . . . . . . .. 2-3
2-3 Memory Mapping - PROM in High Menlory . . . . . . . . . . . . . . . . . .. 2-4
2-4 Boot/Self-Test Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
2-5 Q-Bus Size Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-8
2-6 Q-Bus Base Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-7 DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2-8 Locked Instruction Enabie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-9 BREAK Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-10 HALT Option Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-11 Power-Up Option Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-12 PROM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2-13 SLU1 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-14 SLU1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2-15 SLU1 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2-16 SLU2 Channel A Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2-17 SLU2 Channel B Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2-18 SLU2 Channel B Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24·
2-19 Real-Time Clock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
4-1 Backplane Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
4-2 Using Grant Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-2
5-1 Parallel 110 Interface Pin Assignments . . . . . . . . . . . . . . . . . . . . . .. 5-1
5-2 J2 and J3 Pin Assignments (lO-Pin) . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
5-3 J1 Pin Assignments (40-Pin) . . . . . . . . . . . . . . . . . . . . . . : . . . . . .. 5-3
5-4 Loopback Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-8

Tables
2-1 Factory Shipped Jumper Configuration . . . . . . . . . . . . . . . . . . . . . .. 2-2
2-2 Boot/Self-Test Switch Functions . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
2-3 Q-Bus Base Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-9
2-4 SLU1 Baud Rate Jumpering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
4-1 KXJ11-CA Pin Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
5-1 RS422/RS423 Interface to J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-4
5-2 RS232-C Interface to J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-6
5-3 CCITTN.35 Interface to J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-7
6.. 1 LED Display Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-2

Chapter 1
Introduction

This guide describes how to install the KXJ 11-CA module.
NOTE

Before changing the factory shipped jumper configuration, make
sure the jumpers match the jumpers shown in Figure 2-1, and verify that the module is operating as described in Section 6.2.
Installation includes the following activities.
1.

Selecting operating characteristics and installing appropriate jumpers
(Chapter 2)

Determining power supply requirements (Chapter 3)

Installing the board into a backplane (Chapter 4)

Selecting and connecting cables from serial and parallel 110 interfaces to
external devices (Chapter 5)

Verifying proper operation (Chapter 6)

1-1

Chapter 2
Selecting Operating Features

Several characteristics of the KXJ11-CA are defined by jumper settings. This section
describes the characteristics that are part of the factory-shipped configuration. It also
shows how to change these characteristics by changing the appropriate jumpers.
Figure 2-1 illustrates the factory-shipped jumper settings. Table 2-1 summarizes the
meaning of each jumper setting. The sections that follow describe the various jumper
setting alternatives available.
M48

M47

M34
M32
M30
M44 0 0 M43 M28
M42~M41 M26
M40~M39 M24

!
I
r:'" II

M60~M59 0 M54
M58 0 0 M57 fOlM53
M56 ~ M55 ~ M52
SLUI

r:~cel

0
0

0
0
0
0

M33
M31
M29
0 M27
0 M25
0 M23
0
0

SLU2

'"~:""

M20~

010 ...---fI ~~~
SWITCH

;

M65
M64 I M66

Figure 2-1

D
KXJII-CA Jumper Layout

2-1

.§]

_____

000

Ml9 0
Ml8 0

1:2:2]0

M61
M62

FI:[oI' M';:"

M2 M4

~ 0 0 0 ~o

M63

Ml5

M14

0 M38
M37~

?? \
M461
M45

O-M35

f"O"Ol M36
'+-+-' '\';149
M51 M50

Table 2-1

Factory Shipped JUlnper Configuration

Function

Setting

Jumpers Installed

Q-Bus Size

22 bits

M3 to M4
M5 to M6

Q-Bus Base Address
ID Switch Position

17760240
5

M1 to M2

DMA Requests
SLU2 Channel A Receiver
8036 Counter/Timer
SLU2 Channel A Transmitter

Enabled
Disabled
Enabled

M10 to MIl
M7 to M8

Locked Instruction Enable

Disabled

M65 to M66

BREAK Enable

Enabled

M12 to M13

HALT Option Selection

MicroODT

M14 to M15

Power-U p Option Selection

Firmware

No jumper

PROM Addressing

15-bit

No jumper

SLU1 Baud Rate

9600

M56 to M55
M60 to M59

SLU1 Transmitter

RS423

M62 to M61

SLU1 Receiver

RS423

No jumper

SLU2 Channel A Receiver

RS422

M34 to M33
M32 to M31
M30 to M29
M28 to M27
M26 to M25
M24 to M23

SLU2 Channel B Transmitter

RS422

M38 to M36
M51 to M50

SLU2 Channel B Receiver

RS422

M42 to M41
M40 to M39
M20 to M21

Real-Time Clock Interrupt

60Hz

M52 to M53

Boot/Self-Test Switch Position

NOTE

The SLU2 Channel A Transmitter is not configured with jumpers,
but is configured by selecting appropriate signals on connector J1.

2-2

2.1 Boot/Self-Test Switch
The boot/self-test switch is a I6-position switch that is used if the board is configured
to execute firmware (rather than MicroODT) upon power-up. It has three functions.
1.

It determines how the KXJII-CA will act when a special interrupt condition
exists, including whether or not self-tests will run (see Section 3.5, The
KXJJJ-CA Single-Board Computer User's Guide, EK-KDJCA-UG-OOI).

It determines whether special interrupt handling is performed either by

user code or by firmware.
3.

It determines where in memory the on-board PROM is mapped. There are

two alternatives - low memory or high memory. The memory maps associated with low and high PROM mapping are shown in Figures 2-2 and 2-3,
respectively.

17777777

17774000
17773777

POWER UP

17773000
17772777

I/O PAGE

17770000
17767777
MONITOR AND
DIAGNOSTICS
17760000
17757777

,.1".

NXM

,."

,.~

"r"

2200000
2177777
2174000
2173777

POWER UP

2170000
2167777

NATIVE

2173000
2172777

FIRMWARE

MONITOR AND
DIAGNOSTICS

2160000
2157777
USER PROM

2000000
1777777
RAM
7777 7

o l~p'Ror~/RAM SPACE " : _

• ADDRESSES 77777-0 MATCH ADDRESSES 2077777-2000000
\1R-17263

Figure 2-2

Memory Mapping - PROM in Low Memory

2-3

17777777

17774000
17773777
POWER UP
17773000
17772777

17770000
17767777

I /0 PAGE

MONITOR AND
DIAGNOSTICS

17760000
1775777 7
,.1.-

NXM

220000 0
217777 7
2174000
217377 7

POWER UP

2173000
217277 7

217000 0
216777 7

.... 1.I'i""

....

NATIVE
FIRMWARE

MONITOR AND
DIAGNOSTICS

216000 0
215777 7

USER PROM
200000 0
177777 7
RAM
0
MR-17262

Figure 2-3

Memory Mapping PROM in High Memory

2-4

The location of the boot/self-test switch is shown in Figure 2-4. Table 2-2 summarizes
the functions associated with each switch position.

BOOT/SELFTEST SWITCH

....
...........

.... .

'0
.. . ..

.....

MR-16215

Figure 2-4

Boot/Self-Test Switch

Table 2-2

Boot/Self-Test Switch Functions

Switch
Position

KXJII-CA
Special Interrupt Response

Special
Interrupt
Handling

PROM
Mapping

User PROM application code is
executed. No self-tests are
performed.

Firmware

Low

User PROM application code is
executed. Auto self-tests are
performed.

Firmware

Low

2-5

Table 2-2

Boot/Self-Test Switch Functions (Cont)

Switch
Position

KXJII-CA
Special Interrupt Response

Special
Interrupt
Handling

PROM
Mapping

User PROM application code is
executed. Auto self-tests are
performed. The user (P)ROM
checksum test is also performed.

Firmware

Low

Application code is booted from
a TU58 via SLUl. Auto self-tests
are performed, then the TU 58
primary bootstrap is executed.

Firmware

High

MicroODT is entered. No self-tests
are performed.

Firmware

High

Auto self-tests are performed.
The KXJII-CA awaits command from
the arbiter via TPRO.

Firmware

High

No self-tests are performed.
The KXJII-CA awaits a command
from the arbiter via TPRO.

Firmware

High

Auto self-tests are performed
continuously. No application
code is booted or executed.
Loopback connectors (see
Section 5.3) are installed
for these tests.

None

High

User PROM application code is
executed. No self-tests are
performed.

User Code

Low

User PROM application code is
executed. Auto self-tests are
performed.

User Code

Low

User PROM application code is
executed. Auto self-tests are
performed. The user (P)ROM
checksum test is also performed.

User Code

Low

Application code is booted from
a TU58 via SLUl. Auto self-tests
are performed, then the TU 58
primary bootstrap is executed.

User Code

High

MicroODT is entered. No self-tests
are performed

User Code

High

2-6

Table 2-2

Boot/Self-Test Switch Functions (Cont)

Switch
Position

KXJII-CA
Special Interrupt Response

Special
Interrupt
Handling

PROM
Mapping

Auto self-tests are performed.
The KXJ11-CA awaits a command
from the arbiter via TPRO.

User Code

High

No self-tests are performed.
The KXJ11-CA awaits a command
from the arbiter via TPRO.

User Code

High

Auto self-tests are performed
continuously. No application
code is booted or executed.
Loopback connectors (see
Section 5.3~ are installed
for these tests.

None

High

NOTES

Switch position 5 is the factory-shipped configuration.

The encoded value of the boot/self-test switch position is available in the KXJCSRB register in bits < 7:4 >. For example,
switch position 1 would be encoded as 0001 in KXJCSRB
<7:4>.

The user (P)ROM checksum test looks for a checksum at the
highest word address of user (P)ROM. Similarly, the firmware
checksum test looks for a checksum at the highest word address of the firmware PROM. Either checksum is calculated
and checked according to the following DECPROM algorithm:
CHECKSUM = 0
FOR I = number of PROM addresses to be checksumed
DO CHECKSUM = CHECKSUM + contents of address
(high order carry from addition is discarded)
CHECKSUM = ROTATE_LEFT_ONE_BIT (bitO ~ bit1,
bit1 ~ bit2, .... ,bit15 ~ bitO) NEXT I

Special interrupt handling can be performed by user code in
switch positions 8-15. This function is useful in applications
that need to continue running after the Q-Bus signal BHALT
or the Q-Bus signal BINIT has been asserted. For switch positions 0 through 7, special interrupt handling is done by
firmware.

If the KXJ11-CA is in standalone mode, switch positions 5, 6,
13, and 14 should not be used. These positions cause the

KXJ 11-CA to idle and wait for a command. In standalone
mode, the KXJ11-CA will idle indefinitely, waiting for an arbiter command that will never come.

2·7

2.2 Q-Bus Size
The KXJ11-CA may be configured to handle 16-, 18-, or 22-bit Q-Bus addressing. This
is accomplished with the Q-Bus size jumpers (see Figure 2-5). 22-bit addressing is selected as part of the factory-shipped configuration.
Jumper Connection

Description

M3
M4

b b M6

M:5

22-bit addressing selected*

M5
M6

18-bit addressing selected

M5
M6

16-bit addressing selected

M3
M4
M3
M4

0
0

b
0

...0

ID ....01

1
L - -_ _

.. .

...... ......

M30

oM5

M40

oM6

: .. :::

MR-16216

Figure 2-5

Q-Bus Size Selection

* Factory-shipped configuration

2-8

.2.3 Q-Bus Base Address Selection
In systems with multiple I/O processor boards, make sure each board has a unique
Q-Bus base address to distinguish the boards from one another. This is accomplished
on the KXJII-CA by setting the ID switch and installing or removing a jumper which
connects Ml and M2.
Table 2-3 lists the base addresses that can be selected. Table 2-3 lists 22-bit addresses.
If the KXJII-CA is configured for 16- or 18-bit addressing, use the lower 16 or 18 bits
of the addresses specified in Table 2-3.

Table 2-3

Q-Bus Base Address Selection

ID Switch Position
0
1
2
3
4
5t
6
7
8
9
10
11
12
13
14
15

Base Address
(Jumper IN)

Base Address
(Jumper OUT)

*
*

17760100
17760140
17760200
17760240t
17760300
17760340
17775400
17775440
17775500
17775540
17775600
17775640
17775700
17775740

17762100
17762140
17762200
17762240
17762300
17762340
17777400
17777440
17777500
17777540
17777600
17777640
17777700
17777740

* These switch positions disable the Q-Bus interface. That is, the KXJII-CA is running in standalone mode.
Factory-shipped configuration

2-9

Figure 2-6 shows the locations of jumper connections M1 and M2, and the ID switch.
The factory-shipped base address is 17760240.
Jumper Connection

Description
Factory-shipped configuration
Base address = 17760240

M1
M2

. . . 0IL----------'I.~
.. .

: .. :::

MA-16217

Figure 2-6

Q- Bus Base Address Selection

2-10

2.4 DMA Requests
DMA requests to the on-board DMA transfer controller (DTC) may come from several
sources. The KXJII-CA has a set of jumpers that enable or disable DMA requests
from: (1) the SLU2 channel A receiver, (2) the SLU2 channel A transmitter, or (3) the
on-board 8036 PIO counter/timer. The location of these jumpers is shown in Figure
2-7. Only two of the three sources may be specified (jumpered) at one time. The two
sources that are jumpered as part of the factory configuration are SLU2 channel A
receiver and SLU2 channel A transnlitter.
Description

Jumper Connection
MIl MIO

0---0

MIl MIO

0----0

MIl MIO

0---0

Allows DMA channel 0 requests from SLU2
channel A receiver*
Allows DMA channel I requests from PIO
counter/timer (pin CI used as request line)
Allows DMA channel I requests from SLU2
channel A transmitter*

NOTE

Do not connect a jumper between MIO and M9. This configuration
is not supported.

Mll Ml0 M9 .MS M7
o
0
0
0
0

.....

MR-,6218

Figure 2-7

DMA Requests

* Factory-shipped configuration

2-11

2.5 Locked Instruction Enable
The KXJII-CA has a set of jumpers that enable or disable the locking characteristic of
the WRTLCK, TSTSET, and ASRB interlocked instructions. The location of the jumpers is shown in Figure 2-8. Locking is disabled as part of the factory-shipped configuration. For most applications, locking must be disabled. If locking is enabled, a Q-Bus
timeout may cause a trap to location 4 if the Q-Bus is heavily loaded, and one of these
instructions is executed.
JunIper Connection

Description

M64

M65

M66

The locking characteristic of the WRTLCK,
TSTSET, and ASRB instructions is enabled

M64

M65

M66

The locking characteristic of the WRTLCK,
TSTSET, and ASRB instructions is
disabled*

. . .01'---_I.~ ; ;pl,------,I 0
.

.. ......

D
M64 M65 M66
o
0
0

MR-l086-1235

Figure 2-8

Locked Instruction Enable

* Factory-shipped configuration

2-12

2.6 BREAK Enable Selection
There is a jumper on the board that enables or disables console BREAK requests from
SLUI (the on-board DLART) to the J-I1. The location of this jumper is shown in
Figure 2-9. A BREAK is generated by SLUI when a console terminal is attached to
the system and the BREAK key on the console keyboard is pressed. When BREAK is
received, the J-II executes MicroODT. BREAK requests are enabled as part of the
factory-shipped configuration.
Junlper Connection

Description

MI3

0----0

MI2

Console BREAK requests enabled*

MI3

MI2

Console BREAK requests disabled

M12 M13

OO~

... ..
...

.. .. :::.

MR-16219

Figure 2-9

BREAK Enable

* Factory-shipped configuration

2·13

2. 7 HALT Option Selection
A jumper on the KXJ11-CA determines what action will be taken if a HALT instruction is executed in kernel mode. The location of this jumper is shown in Figure 2-10.
The jumper affects the state of bit 3 of the Maintenance Register (see Section 3.2.10,
The KXJJJ-CA Single-Board Computer User's Guide, EK-KXJCA-UG-001). If the
jumper is installed (the factory-shipped configuration), a HALT instruction executed in
kernel mode causes the processor to enter MicroODT. If the jumper is not installed,
the KXJ11-CA traps to location 4 in kernel instruction space and sets bit 7 in the
CPU error register.
Junlper Connection

Description

M15

0-----0

M14

MicroODT is entered when a HALT instruction is
executed in kernel mode*

M15

M14

KXJ11-CA traps to location 4 in kernel instruction
space and sets bit 3 of the CPU error register if a
HALT instruction is executed in kernel mode

ID ....DI

.. .

...

fr-

_ _----M150 oM14

.....

"'R-16220

Figure 2-10

HALT Option Selection

* Factory-shipped configuration

2-14

2.8 Power-Up Option Selection
The power-up jumper (see Figure 2-11) determines what action the KXJII-CA will take
when the board is powered up or reset. The jumper affects the state of bit 2 of the
Maintenance Register (see Section 3.2.10, The KXJJJ-CA Single-Board Computer
User's Gllide, EK-KXJCA-UG-OOl). At power-up, if the jumper is installed, the processor enters MicroODT with the PS register cleared. This is also known as power-up
option 1. If the jumper is not installed, (the factory-shipped configuration), the KXJllCA executes the firmware power-up code at location 173000 during power-up (PC =
173000, PS = 340). This is also known as power-up option 3. Only power-up options 1
and 3 are used for the KXJ II-CA.
Description

Jumper Connection
M 17

()----4)

M16

MicroODT is entered during power-up

M17

M16

The KXJII-CA bootstraps
173000 during power-up*

through

location

. . ·0 I'-----I.~
.. .
~M1700M16

D
Figure 2-11

Power-Up Option Selection

2-15

.....
.. .

2.9 PROM Addressing
The KXJII-CA can be jumpered to accommodate various PROM types. The location of
the PROM addressing jumper is shown in Figure 2-12. If the jumper is not installed,
the on-board PROMs use I5-bit addresses. PROMs such as the Intel 2764 (8K x 8)
and 27128 (16K x 8) use 15-bit addresses. If the jumper is installed, the PROMs use
I6-bit addresses. This accommodates PROMs such as the Intel 27256 (32K x 8) that
use I6-bit addresses. I5-bit PROM addressing is specified as part of the factoryshipped configuration.
Jumper Connection

o
o

Description

M19
M18

15-bit addressing selected*

M19
MI8

16-bit addressing selected

. . ·0 I

10 ....01
....
......
00

00
00
0

000
000

'----__~J ...~~~~;
~::I

MR-16222

Figure 2-12

PROM Addressing

* Factory-shipped configuration

2-16

2.10 SLU1 Baud Rate
The jumpers shown in Figure 2-13 select the default baud rate for the SLU1 transmitter and receiver. The default baud rate for SLU1 is set when the KXJ11-CA is powered up or reinitialized. This rate can be changed under software control, if
KXJCSRJ < 3> is set. Table 2-4 shows the various baud rates that can be selected. A
default baud rate of 9600 is specified as part of the factory-shipped configuration.
Description

Junlper Connection
M60
M58
M56

0----0

0---0

M600
M580
M560

M59
M57
M55

Factory shipped configuration
9600 baud

M59
M57
0 M55

0
0

.....

MR-,6223

Figure 2-13

SLU1 Baud Rate

2·17

Table 2-4
Baud Rate

38400
19200
9600*
4800
2400
1200
600
300

SLU1 Baud Rate JUlnpering
M56 to M55

M58 to M57

M60 to M59

In
In
In
In
Out
Out
Out
Out

In
In
Out
Out
In
In
Out
Out

In
Out
In
Out
In
Out
In
Out

* Factory-shipped configuration

2-18

2.11 SLU1 Transmitter
The SLUI transmitter can be jumpered to send either single-ended (RS423) or differential (RS422) asynchronous serial data via connector J3. The location of the jumpers
is shown in Figure 2-14. RS423 transmission is selected as part of the factory-shipped
configuration.
Jumper Connection
1\163 1\162
o

Description

~Jl61

RS423 transmission selected*

o~--o

M63 M62

M61

0----0

...0

RS422 transmission selected

1'-----_ _I

M62 M61
o
0

000
000

.....
000

MR·16224

Figure 2-14

SLU1 Transmitter

* Factory-shipped configuration

2-19

2.12 SLU1 Receiver
The SLU1 receiver can be jumpered to receive either single-ended (RS423) or differential (RS422) asynchronous serial data via connector J3. The location of the jumper is
shown in Figure 2-15. RS423 reception is selected as part of the factory-shipped
configuration.
Jumper Connection

Description

M48

M47

RS422 reception selected

M48

M47

RS423 reception selected*

M48 M47
o 0

. . . DL---I_I:~ ~lP ,---I_ I D
0.0
000

. .....
o

000

MR-'6225

Figure 2-15

SLU1 Receiver

* Factory-shipped configuration

2-20

2.13 SLU2 Channel A Receiver
The SLU2 channel A receiver can be jumpered to receive either single-ended (RS423)
or differential (RS422) serial data via connector J1. The location of the jumpers is
shown in Figure 2-16. RS422 reception is selected as part of the factory-shipped
configuration.
Jumper Connection
M34
M32
M30
M28
M26
M24

(}---()

M34
M32
M30
M28
M26
M24

<r---{)
<r---{)
~
~

Description
M33
M31
M29
M27
M25
M23

RS422 reception selected*

M33
M31
M29
M27
M25
M23

RS423 reception selected

·. . 0I'----__I:~

M340 0 M33
M320 0 M31
M300 0 M29
M280 0 M27
M260 0 M25
M240 0 M23

10
.

.. .....
...

MR·16226

Figure 2-16

SLU2 Channel A Receiver

* Factory-shipped configuration

2-21

2.14 SLU2 Channel B Transmitter
The SLU2 channel B transmitter can be jumpered to send single-ended (RS423), differential (RS422), or party line (CCITT R1360) serial data via connector J2. The location
of the jumpers is shown in Figure 2-17. RS422 transmission is selected as part of the
factory-shipped configuration.
Description

Jumper Connection
M38
M46 M45
0

M37
0

RS422 transmission selected*
M35
0

M36

M51

M50

M49

M38

RS423 transmission selected

M46 M45
0

M37
0

M35
0

M36
0

M51

M50

M49
Party lirie transmission selected

M38
0

M46 M45

M37

Q-----{)

M35
0

M36
0

M51

M50

M49

* Factory-shipped configuration

2-22

. ·. 01

10 ....01
.. .

.... ......

10
M38

M46 M45 M37 M36 M35

:Gr

'----_---.l

M51 M50 M49
000

MR-16227

Figure 2-17

SLU2 Channel B Transmitter

2·23

2.15 SLU2 Channel B Receiver
The SLU2 channel B receiver can be jumpered to receive single-ended (RS423), differential (RS422), or party line (CCITT R1360) serial data via connector J2. Two groups
of jumpers are involved and shown in Figure 2-18. RS422 reception is selected as part
of the factory-shipped configuration.
Jumper Connection
M44

M42
M40

0---0

M44
M42
M40

0---0

0---0
0

Description

1\143
M41
M39

1\.120

M21
M22

M43
M41
M39

0
0
0

M43
M41
M39

0
0
0

RS422 reception selected*

M20
M21
M22

RS423 reception selected

M20
M21
M22

Party line reception selected

M44 0 0 M43
M420 0 M41
M40 0 0 M39

0 M20
0 M21
0 M22

·. . 0I'------~Pl'-------~.

.. .....
..

MR·16228

Figure 2-18

SLU2 Channel B Receiver

* Factory-shipped configuration

2-24

2.16 Real-Time Clock Interrupt
SLU1 (the on-board DLART) can generate real-time clock interrupts at frequencies of
50 and 60 Hz. Jumpers M52, M53, and M54 select either the 50 Hz or the 60 Hz
real-time clock as input to the interrupt control logic. If interrupts are enabled, each
clock "tick" results in a maskable priority level 6 interrupt request to the on-board
J-11. The location of the real-time clock interrupt jumpers is shown in Figure 2-19. A
real-time clock rate of 60 Hz is specified as part of the factory-shipped configuration.
Jumper Connection

Description

M54
M53
M52

60 Hz real-time clock selected *

M54
M53
M52

50 Hz real-time clock selected

o M54
o M53
o M52

. . .0 ~
1

.. ...
... ..

D ,. ,;:
D
MR-16229

Figure 2-19

Real-Time Clock Interrupt

* Factory-shipped configuration

2-25

Chapter 3
Power Supply Considerations

When installing the KXJ11-CA, make sure the power supply can handle the extra load
presented by the board. The KXJ11-CA draws a maximum of 6A at +5V. In addition,
the KXJ11-CA draws a maximum of 1.4A at + 12V, for systems with the DLV11-KA
option, or .4A maximum at +12V, for systems without the DLV11-KA option. The
board adds 2.7 ac loads and 1.0 dc loads to the bus.
In standalone mode, at least four power fingers (backplane connections) and four
ground fingers for +5 Vdc must be connected to the power supply. In addition, at
least two power fingers and two ground fingers for + 12 Vdc must be connected to the
power supply.

3.. 1

Chapter 4
Installing the KXJ11-CA in a Backplane

The KXJ11-CA plugs into any Digital standard quad-height Q-Bus backplane (see
Figure 4-1). No special backplane wiring or jumpering is required to accommodate the
KXJ11-CA. However, the grant structure must be preserved if there are blank slots
between the KXJ11-CA and the top of the backplane. This can be accomplished by
inserting grant cards where appropriate. (Figure 4-2 is an example of the use of grant
cards.) The dual-height grant card (M8659) preserves grant continuity for slots A and
B, and grant card 07272 preserves both the DMA and interrupt grant continuity for
slot C. The KXJ11-CA board must also be configured for the proper Q-Bus address
size.

Figure 4-1

Backplane Installation

4-1

U sing Grant Cards
Figure 4-2

4-2

4.1 Edge Connector Pin Assignments
Table 4-1 summarizes the edge connector pin assignments for the KXJ II-CA. The
board is designed to mate with Digital standard quad height backplanes for Q-Bus
based systems.
Table 4-1

KXJ11-CA Pin Identification

Component Side

Solder Side

KXJ11-CA
Signal

KXJI1-CA
Signal

AAI
ABI
ACI
ADI
AEI
AFI
AHI
AJI
AKI
ALI
AMI
ANI
API
ARI
ASI
ATI
AUI
AVI

NC
NC
BDALl6 L
BDALl7 L
NC
NC
NC
GND
NC
NC
GND
BDMRL
BHALT L
NC
NC
GND
NC
+5VB

AA2
AB2
AC2
AD2
AE2
AF2
AH2
AJ2
AK2
AL2
AM2
AN2
AP2
AR2
AS2
AT2
AU2
AV2

+5V
NC
GND
NC
BDOUTL
BRPLYL
BDIN L
BSYNC L
BWTBTL
BIRQ4 L
BIAKI L
BIAKO L
BBS7L
BDMGI L
BDMGOL
BINIT L
BDALOL
BDALlL

BAI
BBI
BCl
BDI
BEl
BFI
BHI
BJI
BKI
BLI
BMI
BNI
BPI
BRI
BSI
BTl
BUI
BVI

BDCOKH
BPOKH
BDAL18 L
BDALl9 L
BDAL20 L
BDAL21 L
NC
GND
NC
NC
GND
BSACKL
NC
NC
NC
GND
NC
+5V

BA2
BB2
BC2
BD2
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

+5V
NC
GND
+12V
BDAL2 L
BDAL3 L
BDAL4 L
BDAL5L
BDAL6 L
BDAL7L
BDAL8 L
BDAL9 L
BDALIO L
BDALII L
BDALl2 L
BDALl3 L
BDALl4 L
BDALl5 L

4-3

KXJ11-CA Pin Identification (Cont)

Table 4-1

Component Side

KXJ11-CA
Signal

Solder Side
KXJ11-CA
Signal

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
NC

CA2
CB2
CC2
CD2
CE2
CF2
CH2
CJ2
CK2
CL2
CM2
CN2
CP2
CR2
CS2
CT2
CU2
CV2

NC
NC
NC
NC
NC
NC
IAK L (Note 2)
IAK L (Note 2)
NC
DMG L (Note 3)
DMG L (Note 3)
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
NC

DA2
DB2
DC2
DD2
DE2
DF2
DH2
DJ2
DK2
DL2
DM2
DN2
DP2
DR2
DS2
DT2
DU2
DV2

+5V
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

CAl
CBI
CCI
CDI
CEI
CFI
CHI
CJI
CKI
CLI
CMI
CNI
CPI
CRI
CSI
CTI
CUI
CVI

NC
NC
NC

DAI
DBI
DCI
DDI
DEI
DFI
DHI
DJI
DKI
DLI
DMI
DNI
DPI
DRI
DSI
DTI
DUI
DVI

+5V
NC
GND

NOTES
1.

NC = Not connected

Pin CM2 is jumpered to pin CN2 for the interrupt acknowledge daisy chain.

Pin CR2 is jumpered to pin CS2 for the DMA grant daisy
chain.

4-4

Chapter 5
Connectors and External Cabling

The KXJ11-CA communicates with external devices via a parallel 110 connector (J4)
and three serial 110 connectors (J1, J2, and J3). This section specifies the pin assignments of these connectors and lists the types of cables that can be used with each
connector.

5.1 Parallel 1/0 Interface (J4)
The parallel 110 (PIO) interface signals appear at connector J 4. These signals are buffered. They can be driven over a 50-foot distance via a ribbon cable, or round cable
with a 40-pin AMP contact housing (AMP part number 746473-9) at each end. A PIO
cable is not provided with the KXJ11-CA. The following PIO cables are recommended
for use in the KXJ11 and are available from Digital Equipment Corporation.
•
•

Shielded ribbon cable BC06 R
"Mirror image" cable BC05 L

Figure 5-1 lists the pin assignments for J4, the parallel 110 connector.

BOARD
B

DD FF

NN RR TT

SG SG

SG I SG

A4 A3

AA CC

KK MM PP

ACE

EE HH

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE
NOTE: SG = SIGNAL GROUND
AO - A7 = PORT A
80 - 87 = PORT 8
CO - C3 = PORT C
MR-12615

Figure 5-1

Parallel 110 Interface Pin Assignments

5-1

5.2 Serial 1/0 Lines (J1, J2, J3)
The KXJII-CA has three serial 110 lines.
•

SLU2 channel A (Jl), a synchronous/asynchronous serial line with modem
control

•

SLU2 channel B (J2), a synchronous/asynchronous serial line without modem control

•

SLUI (J3), the console asynchronous serial line (no modem control)

Each serial line is compatible with the EIA RS232-C and RS422/RS423 protocols. In
addition, SLU2 channel B (J2) is compatible with the CCITT R1360 party line protocol. To interface the KXJll-CA with a 4-20 rnA current loop device via the serial lines,
use the DLVll-KA option.
Users must supply their own serial line cables. The following cables are recommended
for use for the J2 and J3 serial 110 lines and are available from Digital Equipment
Corporation.
BC20N-05

A 5-foot EIA RS232-C null modem cable for a direct connection
between the KXJll-CA and an EIA ternlinal. This cable has a 10pin (2 x 5) AMP fenlale connector on one end and a 25-pin
RS232-C female connector on the other.

BC2lB-05

A 5-foot EIA RS232-C modem cable for a connection between the
KXJll-CA and a nlodem or acoustic coupler. This cable has a 10pin (2 x 5) AMP female connector on one end and a 25-pin
RS232-C male connector on the other.

BC20M-50

A 50-foot EIA RS422 or RS423 cable for a direct connection between the KXJll-CA and a remote processor. Used in applications
requiring high data transmission speeds (up to 19.2 K baud), this
cable has a 10-pin (2 x 5) AMP female connector on each end.

5-2

The pin designations for J2 and J3 are shown in Figure 5-2.
All three serial lines are factory configured to handle differential inputs and outputs. If
you change the configuration of any of the serial lines to handle single-ended inputs or
outputs, make sure the return (-) signal(s) on the cable are tied to signal ground.
Because there is no standard cable available from Digital Equipment Corporation for
SLU2 channel A, you need to construct your own cable. A standard 40-pin AMP connector may be used (AMP part number 746473-9) for connection to J1. Figure 5-3
illustrates the pin assignments for SLU2 channel A (Jl).

SLU
CONNECTOR

BAUD RATE CLOCK OUTPUT
(16 X BAUD)
TRANSMIT DATA+

INDEXING KEY

RECEIVE DATA+

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE

RECEIVE DATA+12 VDC FUSED

•

10
2

PC BOARD

INDEX (NO PIN)

9
GND

MR'()586-0691

Figure 5-2

J2 and J3 Pin Assignments (lO-Pin)

BOARD

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE

Figure 5-3

Jl Pin Assignments (40-Pin)

5-3

Tables 5-1 through 5-3 show the correspondence between the pins of the standard connectors for the RS422/RS423, RS232, and CCITT protocols, and the pins of J1. These
tables make it easy to construct an appropriate cable. The KXJ11-CA register address
associated with each signal is specified in the last column of each table for ease of
programmer reference. For further details, see the register descriptions in Chapters 3
and 6 of The KXJJJ-CA Single-Board Computer User's Guide (EK-KXJCA-UG-001).
Table 5-1

RS4221RS423 Interface to J1

Pin Circuit

Direction

Function

1
2
3
4

SHIELD
Protective Ground
From Modem
SI
SPARE
SD
To Modem
Send Data (+)

From Modem Send Timing (+)

6
7

RS-232 CCITT Pin

Location
17777522

112

5,E

103

114

23,AA 17775706
6,F
12,N 17777520

RD
RS

From Modem Receive Data (+)
BB
To Modem
Request to Send (+) CA

104
105

8
9
10

RT
CS
LL

From Modem Receive Timing (+ )
From Modem Clear to Send (+)
To Modem
Local Loop

DD
CB

115
106
141

11
12

DM
TR

From Modem Data Mode (+ )
To Modem
Terminal Ready (+)

CC
CD

107
108/2

13
14

RR
RL

From Modem Receiver Ready (+ )
To Modem
Remote Loop

109
140

From Modem Incoming Call

125

SF/SR

To Modem

Select Frequency
Signal Rate Select
CH
Terminal Timing (+ ) DA

126
111
113

18
19
20

TM
SG
RC

From Modem Test Mode
To Modem
Signal Ground
From Modem Receive Common

21
22
23
24
25

SPARE
SDR
STR
RDR
RSR

To Modem
Send Data (-)
From Modem Send Timing (-)
From Modem Receive Data H
To Modem
Request to Send (-)

5-4

142
102
102b

17775702
8,J
13,P 17775704
18,V
14,R 17775720
16,T 17775700
25,CC Dummy
Gen.
22,Z
17775710
33,M 17777520
26,DD
24,BB 17775700
9,K
Dummy
Gen.
20,X 17775710
3,C
3,C
30,JJ
10,L
5,E
40,W
2,B
31,KK
38,TT
15,S
32,LL

17777520
17777530
17777522

Table 5-1

RS422/RS423 Interface to J1 (Cont)

Pin Circuit

Direction

26
27
28
29
30

RTR
CSR
IS
DMR
TRR

From Modem Receive Timing (-)
From Modem Clear to Send (-)
To Modem
Terminal in Service
From Modem Data Mode (-)
To Modem
Terminal Ready (-)

31
32

RRR
SS

From Modem Receiver Ready (-)
To Modem
Select Standby

33
34
35

SQ
NS
TTR

From Modem Signal Quality
To Modem
New Signal
Terminal Timing (-)
To Modem

36
37

SB
SC

From Modem Standby Indication
To Modem
Send Common

Function

RS-232 CCITT Pin

Location

37,SS
35,PP
3,C
17777520
17,V
19,W
116
CG

7,H
28,FF Dummy
Gen.

110
27,EE
117
102a

1,A

NOTES

Pins K 9, 25 CC, and 28 FF are driven by dummy generators
that disable RL (CCITT 140), LL (CCITT 141), and SS
(CCITT 116) respectively.

The label NC indicates no connection.

The suffix R in a three-letter pin label (such as RDR) signifies
that the pin is associated with the return side of a differential
driver or receiver.

Circuit IS can be redefined to mean SF. Or IS can be redefined as SR. In the second case, TM is also redefined as SI.

5-5

Table 5-2

RS232-C Interface to J1
Location

Circuit

Direction

1
2
3
4
5

Protective Ground
To Modem
Transmitted Data
From Modem Received Data
To Modem
Request to Send
From Modem Clear to Send

101
103
104
105
106

39,UU
6,F
17775706
8,J
17775702
18,V 17775704
16,T 17775700

6
7
8
9
10

CC
AB
CF

From Modem Data Set Ready
Signal Ground
From Modem Receiver Ready
(From Modem) (+ DC Test Voltage)
(To Modem)
(- DC Test Voltage)

107
102
109

22,Z
17775710
40,W
24,BB 17775700

BA
BB
CA
CB

Function

CCITT Pin

11
12

SCF

SCB

SBA

SBB

17
18
19

From Modem Secondary Received
Data
From Modem Receiver Clock
Receiver Dibit Clock
To Modem
To Modem
Secondary Request to
Send
To Modem
Data Terminal Ready

From Modem

22
23

CE
CHICI

Signal Quality
Detector
From Modem Ring Indicator
To Modem
Data Rate Selector

To Modem

SCA

Unassigned
From Modem Secondary Carrier
Detector
From Modem Secondary Clear to
Send
To Modem
Secondary Transmitted Data
From Modem Transmitter Clock

122
121
118
114

17777520

14,R

17777520

119
115
120
108/2

26,DD 17777520

110

125
111
112
External Transmitter 113
Clock
Force Busy

5-6

12,N

20,X
5,E
3,C
10,L

17775710
17777522
17777520
17777530

Table 5-3

CCITTN.35 Interface to J1

Pin Circuit

Direction

A
B
C
D
E

101
102
105
106

Protective Ground
Signal Ground
To Modem
Request to Send
From Modem Ready for Sending
From Modem Data Set Ready

109
10811

107

RS232 RS449 Pin

Function

J
R
T

125
104
104

From Modem RCV Line Signal Det
To Modem
Connect Data Set
Data Terminal Ready
To Modem
From Modem Calling Indicator
From Modem Received Data A
From Modem Received Data B

V
X

115
115
114
114
103

From Modem Receive Timing A
From Modem Receive Timing B
From Modem Transmit Timing A
From Modem Transmit Timing B
To Modem
Transmit Data A

S
U
W

103
113
113

To Modem
To Modem
To Modem

108/2

Transmit Data B
Terminal Timing A
Terminal Timing B

5-7

Location

AB
CA
CB

SG
RS
CS

39,UU
40,W
18,V 17775704
16,T 17775700
22,Z
17775710

24,BB 17775700

CD
CE
BB

TR
IC
RD
RD

26,DD 17777520
20,X 17775710
8,J
17775702

RT
RT
ST
ST
SD

14,R

17777520

12,N

17777520

6,F

17775706

10,L

17777530

DB
BA
DA

SD
TT
TT

5.3 Loopback Connectors
Loopback connectors (not provided with the KXJ11-CA) are attached to the serial or
parallel communication ports to determine whether or not they are operating correctly
(see Figure 5-4). They are typically used in conjunction with the running of diagnostic
programs, and in some firmware self-tests (see Section 2.1). These connectors may be
ordered from Digital Equipment Corporation or may be built by the user.
There are three different types of loopback connectors available from Digital. A 10-pin
loopback connector (Digital part number H3270) is plugged into either J2 to test SLU2
channel B, or into J3 to test SLUl. A 40-pin loopback connector (Digital part number
H3022) is plugged into J1 to test SLU2 channel A. This loopback connector can also
be configured to test RS422 or RS423 operation (see Figure 5-4). The third type of
loopback connector is also 40 pins (Digital part number H3021), and is plugged into J4
to test the parallel 110 port.

~~~~~~~Q~~Q
1

~U UU~ U~ U~ ~ U
Figure 5-4

R5 422 TE5T
51·1

512

51·3

51-4

51·5

51·6

51·7

51·8

51·9

51·10

OFF

51·5
OFF

51·6

51·7

51·9

51·10

OFF

RS 423 TE5T
51·1

51·2

OFF

51·3
OFF

Loopback Connectors

5-8

51·4
ON

Chapter 6
Diagnostics

6.1 Error Detection and Reporting with the LEOS
There are four LEDs on the edge of the KXJ11-CA board that the native firmware
uses to indicate the state of the board. These are especially useful for diagnostic purposes during power-up or reinitialization. These LEDs verify that the board is operating properly or, if there is a problem with the board, can help the user locate the
difficulty. Table 6-1 summarizes the conditions the LEDs can indicate.
Upon power-up or reinitialization, all four LEDs are illuminated for approximately 1/2
second, if they are working properly. When the KXJ11-CA is installed in a backplane
in a box, the LEDs are labeled L4 through L1 from left to right. If the KXJ11-CA
runs its self-tests (this is determined by the setting of the boot/self-test switch), L4 is
off and L3 - L1 should be on as the self-tests run. If one of the self-tests fails, L4 is
illuminated, and L3 - L1 indicate the test that failed. Self-tests are run in the order
listed in Table 6-1. Thus, if a test fails, the user can also determine which tests (if any)
passed.
If all the self-tests run without error, the KXJ11-CA performs a boot operation. The
boot/self-test switch setting determines which function is performed. L4 remains off
and L3 - L1 indicate the status of the executing code. Note that the boot/self-test
switch may be set so self-tests are not run. If self-tests have not been run, then L4 is
off, and L3 - L1 indicate the state of the board as it executes code.

6-1

LED Display Definitions

Table 6-1

LEDs
L2
L3

Meaning

All LEDs on for 1/2 second at the start of a power-up or
reinitialization operation

Can't access Control/Status Registers in I/O page (fatal
error); or the power-up jumper (M16-M17) is installed,
which precludes self-tests.

DMA or RTC test failed

RAM test failed

ROM checksum test failed

Serial line test of S LUI failed

Serial line test of S LU 2 channel A failed

Serial line test of SLU2 channel B failed

Parallel port test failed

Auto self-tests running. Auto self-tests do not require
loopback connectors.

Loopback tests and auto self-tests running

Q-Bus ODT mode

o·

Unused

Waiting for command

Performing DTC load

TU58 primary bootstrap executing

Executing non-native code

Quick LED Reference
L4

LEDs
L2
L3

Self-test error detected

x
x

Fatal self-test error detected
No self-test errors detected

0
0

Meaning

Application running without error

Legend
x = On
o = Off
- = Don't care (either On or Off)

6-2

6.2 Diagnostic Testing with XXDP +
The KXJII-CA can be tested by running XXDP+, a diagnostic operating system that
is booted from the user's system disk. This section explains how to run the XXDP+
diagnostics to test the KXJII-CA. More information on XXDP+ is found in The
XXDP+ System User's Manual (AC-F34BF-MC).
When you have successfully booted XXDP+ from the system disk, a message such as
the one shown below appears on the console terminal. The items that are blank (underscore) indicate values that are system-dependent.

BOOTING UP XXDP-__________ MONITOR
XXDP-SM
MONITOR VERSION
BOOTED FROM
KW OF MEMORY
NON-UNIBUS SYSTEM
RESTART ADDR:
THIS IS XXDP=

TYPE "H" or "H/L" FOR HELP

When the "period" (.) prompt appears, the user types in

R ZKXA??<CR>
This initiates the running of the tests. The message

ZKA

.BIN

appears on the console, followed by several lines of system information (the underscore
indicates characters that are system dependent). Then the following message should
appear.

USE <ESC> TO HALT
KXJ FUNCTIONAL TEST
SWR

OCTAL

FUNCTION

15
14
13
12
11
10
09
08
07

100000
040000
020000
010000
004000
002000
001000
000400
000200

HALT ON ERROR
INHIBIT ERROR SUMMARY
INHIBIT ERROR REPORTS
lOP 10# KNOWN GOOD FOR TESTING
TEST STAND ALONE lOP
ENABLE EXTENDED MEMORY TESTS
LOOP ON ERROR
LOOP ON TEST IN SWR<6:0>
INHIBIT TEST NUMBER/TITLE

SWR = 140000 NEW =

6-3

At this point, type < CR >, which runs the tests until an error is detected. As the tests
run, their results are displayed on the console. If an error is detected, a selfexplanatory error message is displayed, and the tests halt if bit 15 in the SWR is set
to 1. The halt causes an entry into MicroODT. To continue after an error has caused a
halt, type

P<CR>
using the console keyboard.
If no errors are detected, testing can be terminated, if the BREAK enable jumper is

installed, by pressing the ESCAPE key (which halts the KXJI1-CA and causes microODT to be entered), or by pressing the BREAK key (which halts the arbiter).

6-4

EK-KXJCA-IN-001
KXJ11-CA Single-Board Computer Installation Guide
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