Digital PDFs

EK-IBV11-UG-001

June 1977

79 pages

Original

3.2MB

Document:	IBV11-A LIS11/Instrument Bus Interface User's Manual
Order Number:	EK-IBV11-UG
Revision:	001
Pages:	79
Original Filename:	http://bitsavers.org/pdf/dec/qbus/EK-IBV11-UG-001_Jun77.pdf

OCR Text

IBV11-A
LSI-11/instrument bus
interface
user's manual

EK-IBV11-UG-001

IBV11-A
LSI-11/instrument bus
interface
user's manual

digital equipment corporation • maynard, massachusetts

Preliminary Edition, January 1977
1st Edition, June 1977

Copyright © 1977 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.s.A.

This document was set on DIGITAL's DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem-IO
DECSYSTEM-20

DECtape
DECUS
DIGITAL
MASSBUS

PDP
RSTS
TYPESET-8
1YPESET-l1
UNIBUS

CONTENTS
Page
CHAPTER 1

INTRODUCTION

1.1
1.1.1
1.1.2
1.1.3
1.2
1.3

GENERAL
LSI-II Systems
.....
IBVI1-A Interface Option
Instrument Bus
SCOPE
REFERENCES

CHAPTER 2

SPECIFICATIONS

2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3

2.3.6

GENERAL
.......... .
IBV11-A MODULE SPECIFICATIONS
General Specifications
LSI-II Bus Interface Signals
Instrument Bus Interface . .
Programming . . . . . . . .
INSTRUMENT BUS CONTROLLER-IN-CHARGE COMMANDS
General . . . . . . . . . . . . . . .
Addressed Command Group (ACG)
Universal Command Group (UCG)
Listener Address Group (LAG)
Talker Address Group (TAG)
Secondary Command Group (SCG)

CHAPTER 3

INSTALLATION

3.1
3.1.1
3.1.2
3.1.2.1

3.4

MINIMUM SYSTEM REQUIREMENTS
System Hardware
System Software . . . . . . . . .
General . . . . . . . . . . .
CONFIGURING THE IBV11-A MODULE
INSTALLING IN THE LSI-II BACKPLANE
CONNECTING TO EXTERNAL EQUIPMENT

CHAPTER 4

PROGRAMMING EXAMPLES

4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2

GENERAL
................... .
EXAMPLE 1 - IBV 11-A TO LISTENER DEVICE
General . . . . . . . . . . . . . . . . . . .
Program Operation . . . . . . . . . . . . .
EXAMPLE 2 - IBV11-A TO TALKER DEVICE
General . . . . . .
Program Operation . . . . . . . . . . . . .

2.3.4
2.3.5

3.2
3.3

iii

1-1
1-1
1-3
1-3
1-6
1-6

2-1
2-1
2-1
2-3
2-8
2-11
2-11
2-12
2-13
2-13
2-15
2-16

3-1
3-1

3-2
3-2
3-3
3-6
3-6

4-1
4-1
4-1
4-5
4-6
4-6
4-6

CONTENTS (CONT)
Page
CHAPTERS

TECHNICAL DESCRIPTION

5.1

5.5

GENERAL
...... .
DEVICE REGISTERS . . . .
LSI-II BUS INTERFACE ..
rnSTRUMENTBUSCONTROL
rnSTRUMENT BUS INTERFACE

CHAPTER 6

MAINTENANCE

6.1
6.2
6.3

GENERAL
......... .
IBVII-A DIAGNOSTIC SOFTWARE
DIGITAL SERVICES . . . . . . . .

APPENDIX A

IC DESCRIPTIONS

A.1
A.2

Dcaa3 INTERRUPT LOGIC
Dcaa4 PROTOCOL LOGIC .
Dcaa5 TRANSCEIVER LOGIC

5.2
5.3
5.4

A.3

5-1
5-1
5-1

5-4
5-5

6-1
6-1
6-1

A-I
A-I
A-I

FIGURES
Figure No,
I-I
1-2
1-3
2-1
2-2

2-3
3-1

3-2
3-3
3-4
3-5
4-1

4-2
4-3

4-4

Title
IBVll-A Instrument Bus Interface Module
IBVll-A Instrument Bus Cable . . . . . .
Typical System - Functional Relationship
IBVIl-A Instrument Bus Connector
Instrument Bus Signal Lines . . . . . . . .
IBVll-A Register and Bit Assignments
Configuring the IBVll-A Register Addresses
Configuring the IBVll-A Interrupt Vector Addresses
IBVll Module Switch Locations
BNllA Instrument Bus Cable . . . . . . . . . . .
Linear and Star Configurations . . . . . . . . . .
Example 1, Communicating with a Listener Device
Program Flowchart . . . . . . . . . . . . . . . .
Example 1, Communicating with a Listener Device
Program Listing . . . . . . . . . . . . . . . . .
Memory Map for Example 1 . . . . . . . . . . .
Example 2, Communicating with a Talker Device
Program Flowchart
.............. .

Page
1-2
1-4

1-5

2-4
2-6
2-8

3-3
3-4

3-5
3-6
3-7

4-2
4-3

4-4
4-7

FIGURES (CONT)
Figure No.
4-5
4-6
5-1
A-I
A-2
A-3

A-4
A-5
A-6
A-7
A-8

Title
Example 2, Communicating with a Talker Device
Program Listing . . . . . . . . . .
Memory Map for Example 2 . . . .
IBV II-A Functional Block Diagram
DC003 Simplified Logic Diagram
DC003 "A" Interrupt Section Timing Diagram
DC003 "A" and "B" Interrupt Sections Timing Diagrams
DC004 Simplified Logic Diagram . . . . . .
DC004 Timing Diagram . . . . . . . . . . .
DC004 Loading Configurations for Table A-2
DC005 Simplified Logic Diagram
DC005 Timing Diagram . . . . . . . . . . .

Page

4-8
4-9
5-3
A-3
A-5
A-6
A-9

A-IS
A-IS
A-18
A-19

TABLES
Table No.
2-1
2-2
2-3

2-4
2-5

2-6
2-7
2-8
2-9

2-10
2-11
3-1
A-I

A-2
A-3
A-4

Title
IBVII-A Backplane Pin Utilization . . . . . . . . . . . . .
BNIIA IBVII to Instrument Bus Cable - Connector Pinning
IBS Register Bits Descriptions
IBD Register Bit Descriptions
IBVII-A Interrupt Vectors
Addressed Command Group .
Universal Command Group
Listener Address Group Commands
Talker Address Group Commands .
Parallel Poll Enable/Disable Commands
My Secondary Address Commands
BN II A and BNO I A Connector Pin Assignments
DC003 Pin/Signal Descriptions . . . . .
DC004 Signal Timing vs Output Loading
DC004 Pin/Signal Descriptions
DC005 Pin/Signal Descriptions . . . . .

Page

2-2
2-5
2-9

2-10
2-11
2-12

. 2-13
2-14
2-15

2-16
2-18
3-8
A-7

A-II
A-16

A-20

PREFACE

The rapid advancement in integrated circuit technology over the past ten years has produced a new
generation of complex electronic instrumentation. This generation of instruments is less costly and
more reliable and provides measurement accuracy previously available only in standards laboratory
environments.
Most of these modern instruments are based on digital logic circuit designs, especially for control and
display functions. Recognizing the fact that logic circuits can be readily interconnected and remotely
controlled or monitored, the IEEE Standards Board approved IEEE Standard 488-1975, Digital Interface for Programmable Instrumentation. That document defines an instrument bus that has become the
industry standard.
Basically, an instrument designed with an interface connector and signals that conform with the IEEE
standard can communicate over a I6-line bus with other instruments and/or controllers designed to
the same standard. Thus, a new family of instruments is emerging that can be interconnected to form
"systems" that perform complex functions. Previously, systems were produced only by spending considerable design time and funding for each system; the instruments now conforming to the IEEE
standard allow "off the shelf' purchase of instruments and system integration at minimal cost.
High-speed, automatic, programmable instrumentation can now easily be implemented by interfacing
a computer to the "instrument bus" that conforms to the IEEE standard. DIGITAL's low-cost, highperformance LSI-II microcomputer is the ideal solution for instrumentation designs. It provides minicomputer performance based on microprocessor technology. Its instruction set is compatible with
most software presently available for the larger PDP-ll/40 minicomputer. An instrumentation system
designed in this manner is an easy to use, inexpensive, powerful tool for instrument system designers.
The IBVII-A option described in this manual is the instrument bus to LSI-II bus interface. The
information contained in this manual will enable a user to determine which LSI-II options are
required for a specific instrumentation application, to install the IBVII-A in the LSI-II system, to
connect the IBVII-A to instruments, and to program the LSI-II to communicate with the instrument
bus.

vii

CHAPTER 1
INTRODUCTION

1.1 GENERAL
The IBVII-A (Figure 1-1) is an LSI-II option that interfaces the LSI-II bus with the instrument bus as
described in IEEE Standard 488-1975, Digital Interface for Programmable Instrumentation. An IBV 11A can be installed in any basic LSI-II system configuration.
1.1.1 LSI-II Systems
Three basic LSI- i i system configurations comprise the LSI-II family: LSI-II system components, the
PDP-I 1/03, and the PDP-II V03.
LSI-II component systems include individual modules, backplane, etc., ordered as separate items. The
user purchases only those items required for a specific application.
The PDP-II /03, a boxed version of the LSI-II, is designed for users that need a packaged microcomputer system. It consists of an LSI-II microcomputer and 4K memory, a modular power supply,
and a mounting box. It is easy to use an LSI-ll-based microcomputer for system development or
dedicated applications.
The PDP-II V03 is the latest addition to the LSI-II family. It is a mass storage-based system, including
the PDP-II /03, the RXV 11 floppy disk system, a system cabinet and power distribution panel, either a
VT52 DECscope or LA36 DECwriter terminal, RT-II system software, and system diagnostics.
Refer to DIGITAL's Microcomputer Handbook for detailed information on theLSI-ii "family" of
systems, including user-assembled component LSI-II systems, the PDP-II/03 packaged LSI-II
microcomputer system, and the PDP-II V03 floppy disk-based LSI-II system.

1-1

20- PIN
INSTRUMENT BUS
CABLE CONNECTOR

DOD [DO

0 0

0 0 0 000 000
o~ 00 .~ 0~ 0D0~ 0
0 0n0 00
0

ODD

VECTOR ADDRESS
SELECT SWITCHES

(S1)

i
DEVICE
(IBS a IBD REGISTERS)
ADDRESS
SELECT
SWITCHES

(52)

D 0

11
I

,n M. "

~I I

0 IlU DIlu

,n, i
fUI i
D,

11
Ii
'-'

LJ L UU U~ U J U U
Iii

o
LSI-II BUSSTRUCTURED
BACKPLANE
FINGERS

JUl,

0
I

" - 4719

Figure 1-1

IBVI1-A Instrument Bus Interface Module

1-2

1.1.2 IBVI1-A Interface Option
The IBVII-A is contained on a 13.2 cm (5.2 in) by 22.8 cm (8.9 in) printed circuit board assembly; a
printed circuit board of this size and shape is also referred to as a "double-height module." Fingers on
one end of the module plug directly into any LSI-II bus-structured system backplane. A connector on
the module mates directly with the instrument bus via the BNllA instrument bus cable supplied with
the option.
The IBVII-A is the LSI-II bus/instrument bus interface that makes an LSI-II-based programmable
instrument system possible. On the LSI-II bus side of the interface, the IBVII-A features include:
• PDP-II software-compatible
• Board-mounted user-configured switches that allow easy device (register address) and interrupt vector address selection
• RT-ll/FORTRAN IV* and RT-II/BASIC* (easy to learn and easy to use programming
languages that are user-oriented; no need for users to become experts in computer
programming)
• System hardware-compatible with any LSI-II component system, PDP-I 1/03, and PDPII V03 systems.
On the instrument bus side of the interface, the IBVII-A features include:
• Instrument bus-compatible with IEEE Standard 488-1975
• Supports cable length up to 20 m (65.6 ft) total

• 15 devices (maximum) can connect to the bus
• Instrument bus-compatible with instrument manufacturers' devices.
1.1.3 Instrument Bus
Before the potential applications for the IBVII-A can be realized, an understanding of the instrument
bus functions is required. (The LSI-II microcomputer's I/O bus is described in the Microcomputer
Handbook and is not repeated here.)
The instrument bus is capable of supporting up to 15 devices, including the IBVll-A. The physical
structure of the instrument bus, the functional relationships of devices connected to the bus, and the 16
signals that comprise the bus are discussed in the following paragraphs.
Physical Structure
Physically, the instrument bus is composed of the cables and instrument connectors that interconnect a
system. The cables are terminated with a standard connector that will mate with any instrument or
device conforming to the IEEE standard. Each connector contains a male plug and a female receptacle
in one housing (Figure 1-2). This allows the instrument bus user to stack connectors for interconnecting instruments in a "star" or linear arrangement. Both ends of the cable are terminated with
identical connectors.

*Planned software options.

1-3

_ _ _ _ 20-PIN

CONNECTOR

BN11 A

INSTRUMENT

14----~~~S~~~~~~8~~~~Ci5
IBV11-A ONLY)

IBV11-A
INTERFACE
MODULE
RECEPTACLE FOR SECOND
(AND SUBSEQUENT)
INSTRUMENT
VIA INSTRUMENT
BUS CABLES

I
USER'S
INSTRUMENT

11 - 4715

Figure 1-2

IBVII-A Instrument Bus Cable

The instrument bus cable (type BN IIA) that connects the IBVII-A to the first instrument on the bus is
different, however. One end (the instrument end) has a connector as previously described. The other
end (at the IBVII-A) is terminated with a molded, 20-cavity housing that mates with the 20-pin connector on the IBVII-A module.
System Device Functions
System devices that connect to the instrument bus function as either "talkers," "listeners," or ··controllers," or a combination of the three functions (Figure 1-3). The function of each in the instrumentation system must be understood before the individual bus signals can be described.
System Controller - The instrument bus always contains one device designated the system controller.
The IBVII usually performs this function. It can control all devices connected to the instrument bus
comprising that system.
NOTE
When the IBV ll-A is the only system controller, the
ERI switch (SI-8) must be in the OFF position.
When the IBVII-A is used in a system that contains
another system controller, SI-8 must be in the ON
position.
Controller - A controller is capable of controlling talkers and listeners connected to the bus. Only one
controller may be active at a time and it is designated the "controller-in-charge." The IBVII-A usually
performs this function. All device addressing, device polling, commands, and data byte transfers are
controlled by the controller-in-charge.

1-4

DEVICE A

DEVICE C

ABLE TO TALK
AND LISTEN

(J)

::J

ABLE TO LISTEN,
ONLY

w
~

::J

a::

(J)

DEVICE B

ABLE TO TALK
AND LISTEN

INSTRUMENT BUS INTERFACE

DEVICE D
ABLE TO TALK,
ONLY

IBVll-A
CONTROLLER-IN-CHARGE
ABLE TO CONTROL,
TALK, AND LISTEN

LSI-ll BUS INTERFACE

PERIPHERAL
INTERFACE
14--_ PRINTERS,ETC.
MODULES
(DLV11, DRVll, ETC)

LSI-II
MICROCOMPUTER
(KDll-F, KD11-J, 14----~
ETC.)

=
I

(J)

...J
SYSTEM MEMORY
(MSVll-B, MSV11-C'I+-_ _.!
MRVI1-AA, MMV11,
ETC. )

CONSOLE
DEVICE
INTERFACE
(DLV11l

FLOPPY DISK
(RXV11l

CONSOLE
TERMINAL
11- 4718

Figure 1-3

Typical System - Functional Relationship

Listener - A listener is a device that is capable of receiving commands and data from the instrument
bus. More than one listener may be active at a time.
Talker - A talker is a device that is capable of receiving commands and transmitting data via the
instrument bus. Only one talker may be active at a time.

1-5

Bus Signal Functions
Sixteen signal lines comprise the instrument bus. Eight lines comprise an 8-bit asynchronous bidirectional data bus. Logical Is are produced by asserting data lines low (ground). The remaining eight lines
provide control functions. Three of these lines are "message handshaking" signals that control data
byte transfers over the instrument bus. The remaining five control signal lines provide general interface
management functions. A detailed description for each signal is included in Chapter 2.
Controller-In-Charge Commands
Controller-in-charge commands are the IBV II-A to instrument bus byte transfers that control
instrument system operation. The IBVII-A becomes active as controller-in-charge by asserting TCS. If
any talker is active when the controller-in-charge is to become active, the IBVII-A first inhibits additional byte transfers by asserting NRFD and waits for DA V to become not asserted, indicating that
the operation has been completed; it then asserts A TN. Approximately 0.5 J.lS later, NRFD becomes
not asserteg, and it can then transmit commands to all devices on the instrument bus.
Commands are transmitted via the DIO<7: 1> lines. Commands are coded as 7-bit ASCII characters;
the DI08 line is not used for command transfers. The actual command set conforms to the instrumentation bus standard and is described in the IBVII-A specifications. The actual commands and the
sequence in which they are issued are completely under the control of the LSI-II system software being
executed.
1.2 SCOPE
The remaining chapters of this manual contain all of the information normally required for the LSI-II
system user to install, program, and use the IBVII-A option. The manual is organized as follows:
Chapter 1

Introduction - General information and references.

Chapter 2

Specifications - Hardware and software specifications for IBV lI-A users. Software
specifications are included for programming the LSI-ll processor to communicate
with the IBV 11. The procedure for programming specific instruments varies depending
on the particular instrument; refer to the instrument manufacturer's documentation for
programming instructions.

Chapter 3

Installation - Minimum LSI-I! system requirements to support the IBVII-A, procedures for configuring IBVII-A module switches, installation in the LSI-II backplane, and instrument bus cabling.

Chapter 4

Programming Examples - Sample instrument system application programs are discussed in this chapter.

Chapter 5

Technical Description - Includes a block diagram of the IBVII-A and functional
theory of operation.

Chapter 6

Maintenance - Lists available diagnostics.

1.3 REFERENCES
Digital Equipment Corporation publications:
Basic Hardware Manuals
Microcomputer Handbook
PDP-II V03 System Manual

1-6

Hardware Option Manuals
RXVll User's Manual (Floppy Disk System)
DRVII-B General Purpose DMA Interface User's Manual
DR VII-P Foundation Module User's Manual
H780 Power Supply User's Manual
LA VII User's Manual (LSI-II bus interface controller for the LA180 DECprinter I)
MSVII-C MOS Read/ Write Memory User's Manual
MRVII-BA LSI-II UV PROM-RAM User's Manual
IEEE Publications:

Digital Interface for Programmable Instrumentation (IEEE Std. 488-1975)

1-7

CHAPTER 2
SPECIFICATIONS

2.1 GENERAL
This chapter contains detailed specifications for IBVII-A users, including hardware and programming
specifications for the module, and instrument bus specifications. Note that only the instrument bus
specifications necessary for using the IBVII-A are included; detailed instrument bus specifications for
designers are included in IEEE Standard 488-1975, Digital Interface for Programmable Instrumentation. Refer to instrument manufacturer's documentation for the correct procedure for instrument bus
addressing, commands, etc. for that particular instrument.
Each IBVII-A option includes one IBVII-A (M7954) module, one BNIIA-04 4 m (157.5 in) cable,
and user documentation.
2.2
2.2.1

IBVII-A MODULE SPECIFICATIONS
General Specifications

Power Requirements

+5 V ± 5%

Mechanical
Height
Length*
Width

13.2 cm (5.2 in)
22.8 cm (8.9 in)
1.27 cm (0.5 in)

Environmental
Temperature
Storage
Operating

--40 0 to 60 0 C (-40 0 to 140 0 F)
50 to 50 0 C (41 0 to 122 0 F)

Relative Humidity

0.8 A typical (1.5 A maximum)

10 to 95% (no condensation)

2.2.2 LSI -11 Bus Interface Signals
The IBVII-A conforms to LSI-II bus specifications stated in the Microcomputer Handbook, Section
!, Chapter 3. Refer to that document for complete LSI-II bus specifications. Backplane pin utilization
is shown in Table 2-1.

*Length as stated is approximate and includes module handle. Actual module length is 21.6 cm (8.5 in).

2-1

Electrical
Input Logic Levels
TTL Logical Low
TTL Logical High

0.8 Vdc max
2.0 Vdc min

Output Logic Levels
TTL Logical Low
TTL Logical High

0.4 Vdc max
2.4 Vdc min

Bus Receivers
Logical Low
Logical High

1.3 Vdc max, -10 J.LA max at 0 V
1.7 Vdc min, 80 J.LA max at 2.5 V

Bus Drivers
Logical Low
Logical High

0.8 Vdc max at 70 rnA
25 J.LA max at 3.5 V

Table 2-1

IBVII-A Backplane Pin Utilization
RowB

RowA
Pin

Signal
Mnemonic

Module Side 1 (Component Side)

AAI
ABl
ACI
ADI
AEI
AFI
AHI
All
AKl
ALl
AMI
ANI
API
ARI
AS}
ATI
AUI
AVI

BSPAREI
BSPARE 2
BADl6 L
BADI7 L
SSPAREI
SSPARE2
SSPARE3
GND
MSPAREA
MSPAREA
GND
BDMRL
BHALT L
BREF L
PSPARE3
GND
PSPAREI
+5B

BAI
BBi
BCI
BDl
BEl
BFl
BHI
Bli
BKI
BLI
BMI
BNI
BPI
BRI
BSI
BTl
BUI
BVl

2-2

II BDCOK
H
BPOK H
I SSPARE

I SSPARE5

f SSPARE6
I

SSPARE7
SSPARE8
GND
MSPAREB
MSPAREB
GND
BSACK L
BSPARE6
BEVNT L
PSPARE4
GND
PSPARE2
+5B

Table 2-1

IBV11-A Backplane Pin Utilization (Cont)
RowB

RowA
Pin

Signal
Mnemonic

Module Side 2 (Solder Side)
AA2
AB2
AC2
AD2
AE2
AF2
AH2
AJ2
AK2
AL2
AM2
AN2
AP2
AR2
AS2
AT2
AU2
AV2

2.2.3

BA2
BB2
BC2
BD2
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

+5
-12
GND
+12
BDOUT L
BRPLY L
BDIN L
BSYNC L
BWTBT L
BIRQ L
BIAKI L
BIAKO L
BBS7 L
BDMGI L
BDMGO L
BIN IT L
BDALO L
BDALIL

+5
-12
GND
+12
BDAL2 L
BDAL3L
BDAL4 L
BDAL5L
BDAL6L
BDAL7 L
BDAL8 L
BDAL9 L
BDALIO L
BDALIIL
BDALI2 L
BDALI3 L
BDALI4 L
BDAL15
L
I

Instrument Bus Interface

Nominal Logic Levels
o = +2.0 V minimum
1 = +0.8 V maximum
Bus Drivers and Receivers
Driver low state output voltage
Driver high state output voltage
Receiver low state output voltage
Receiver high state output voltage
Receiver input hysteresis

+0.4 V (maximum) at +48 rnA sink current
+2.6 V (minimum)
+0.4 V (maximum)
+2.4 V (minimum)
400 mV (minimum) (typically, 900 mY)

Signal Termination
Each instrument bus signal line is terminated within the device by a resistive load (3.0K pull-up to Vee,
6.2K to ground) to establish a steady-state voltage when all drivers on a line are in the high impedance
state.

2-3

Electrical Length of Instrument Bus Transmission
The length of the electrical transmission path over the bus must be within the following specifications:
Number of
Bus Segments

Bus Segments
(m)

Maximum Number
of Devices

Transmission Path
(m)

5
10
14

4
2
1

6
II
15

20
20
14

Instrument Bus Data Rate
The maximum data transfer rate over the instrument bus is 250K bytes per second (4 JIs/byte) provided that all electrical specifications stated herein are met.
Software Data Rate·
The maximum estimated data rate for a tight, dedicated routine to move data from the instrument bus
to the LSI-II memory is 40 kilobytes/second. The maximum estimated data rate for general-purpose
and high-level language routines is 5 kilobytes/second.
Instrument Bus Cable Connector Pinning
I nstrument bus cable connector pins are identified in Figure 2-1. Pin utilization and signal names for
the IBVII-A end and user's instrument end of the cable are identified in Table 2-2.

Figure 2-1

IBVII-A Instrument Bus Connector

2-4

Table 2-2

BNllA IBVll to Instrument Bus Cable - Connector Pinning

Connector Pins
on IBVll-A Module

Instrument Bus
Signal Name

DIOI
DI02
DI03
DI04
EOI
DAV
RFD
DAC
IFC
SRQ
ATN
SHIELD
DI05
DI06
DI07
DI08
REN
GND (6)
GND (7)
GND(8)
GND (9)
GND (10)
GND (11)
GND (logic)

S
P
M

R
T
V
X
B
J
F
W
K
H
E
C
D
N
N
N

A
L
L
W

Instrument Bus
Cable Connector Pins
(Instrument End)

2
3
4

5
6
7
8

9
10

11
12
13
14
15
16
17
18
19

20
21

22
23
24

NOTE
6, 7, 8, 9, 10, 11) is the ground
GND(n) (where n
return for the signal on pin "N" of the instrument
bus connector. For example, GND (6), pin 18, is the
ground return for the signal D A V on pin 6. These
ground returns are returned to the logic ground of
their respective drivers and receivers on the IBVll-A
module.

Signal Functions
Sixteen signal lines comprise the instrument bus as shown in Figure 2-2. Each signal line is partially
terminated by each device connected to the bus. Eight lines (DIO< 1:8> L) comprise an 8-bit asynchronous bidirectional data bus. Logical Is are produced by asserting data lines low (ground). The
remaining eight lines provide control functions, as described in the following paragraphs.

2-5

INSTRUMENT BUS
SIGNAL LI NES
A

DEVICE A

II I I I

t-----+-1!

-----KA
DEVICE B

DEVICE C

'~I~-'-r~rT--,,-r--~

t---~

! I II

----t-i,i

I IIIII II,
i i i

II Ii I
J I I I
I I I

DEV!CE 0

i i i

III
!

I i I

III

I
i

'----

} DIO <1: 8>

DAV
}
NRFD
NDAC

--~

1,---1

IFC
ATN
SRQ
REN
EOI

}

8- LINE DATA BUS

MESSAGE
HANDSHAKING

GENERAL
INTERFACE
MANAGEMENT

CONTROL
SIGNAL
LINES (8)

11-4717

Figure 2~2

Instrument Bus Signal Lines

2-6

Three "message handshaking" control signals control data byte transfers over the 8-1ine data bus.
They provide the necessary handshaking to complete interlocked, asynchronous data transfers. These
control signals are described below.
Data Valid (DAV) - DAV is asserted by the active talker or active controller to indicate that it has
placed valid data on the DIO signal lines. DAVis asserted only after all listener devices are ready
for data and valid data has been placed on the DIO lines for 2 f.ls (minimum).
Not Ready for Data (NRFD) - NRFD enables an active listener to indicate that it is "busy," or
not ready for data. All active listeners must be "ready" to not assert NRFD, enabling a talker to
transmit a data byte.
Not Data Accepted (NDAC) - All active listeners assert NDAC. All inactive listeners do not assert
NDAC. The active listener indicates that it has accepted data during a data transfer by not
asserting NDAC. When more than one active listener is on the instrument bus, the last active
listener to not assert NDAC indicates that all devices have accepted the data.
The remaining five control signals are for general interface management. Each signal is described
below.
Interface Clear (IFC) - IFC is a "master clear" for all devices that connect to the interface bus.
IFC is asserted by the IBVII-A only when it is an active system controller. All devices respond to
the active IFC signal by returning to the idle state within 100 f.lS
NOTE
When the IBVII-A is the only system controller, the
ERI switch (81-8) must be in the OFF position.
When the IBVII-A is used in a system that contains
another system controller, 81-8 must be in the ON
position.
Remote Enable (REN) - Typical devices (instruments) connected to the instrument bus are
capable of local (device control panel) or remote control operation via the instrument bus. The
IBVII-A, as system controller, asserts REN to enable remote operation, or negates REN to allow
local operation of all devices. When REN is asserted, the IBVII-A may return selected devices to
the local mode by addressing the devices and issuing a "go to local" command. When in the local
mode, devices may respond to control and data transmissions over the instrument bus that do not
conflict with local control functions.
Attention (ATN) - The IBVII-A, as controller-in-charge, asserts the ATN signal line when it is
transmitting commands over the DIO lines. An active A TN signal causes any previously active
talker to become inactive and all devices may receive commands from the IBVII-A.
End or Identify (EOI) - EOI can be asserted either by the IBVI1-A, as controller-in-charge, or by
an active talker. A talker asserts EOI to indicate the last byte of a message is being transmitted.
The IBVI1-A can assert EOI while also asserting ATN to conduct a parallel poll.
Service Request (SRQ) - The IBVI1-A monitors the SRQ line for service requests from devices
connected to the instrument bus. The IBVII-A's control/status register (CSR) can be programmed to cause IBVII-A-generated interrupts to occur whenever the SRQ line is asserted. Thus,
interrupt-driven routines can be included in system software that will automatically service
devices on the instrument bus.

2-7

2.2.4 Programming
The IBVII-A communicates with devices connected to the instrument bus under the control of the
LSI-II program being executed. All communication between the LSI-II and the IBVII-A is via the
instrument bus status (IBS) and instrument bus data (IBD) registers. The programmer must be aware
of the functional significance of each bit in both registers before any programs can be written that will
control specific devices on the instrument bus. In addition, the programmer must establish instrument
(device) addresses and conform to programming rules specified for each instrument connected to the
instrument bus.

IDS and IDD Registers
The IBS register provides the means for controlling the instrument bus signals and IBVII-A functions
relative to the LSI-II bus. The low byte of the IBD register, on the other hand, is used for passing
commands to devices connected to the bus and for transmitting and receiving data between the LSI-II
processor and talker and listener devices. In addition, the high byte of the IBD register allows for LSI11 processor monitoring of all instrument bus signal (data and control) lines. IBS and IBD registers are
shown in Figure 2-3 and described in Tables 2-3 and 2-4.
08

15
IBS
REGISTER

I
I
I
I

0
1

BIT

0
1

TCS(R/W)
EOP (R/W)
REM(R/W)
IBC (R/W)
LON (R/W)
I
TON (R/W)
IE (R/W)
ACC (R/W)
LNR (R)
TKR (R)
CMD (R)
(NOT USED)
(NOT USED)
ERl (R)
:
L - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ER2 (R)

I
I

' - - - - - - - - - - - - - - - - - - - - - - SRQ (R/W)

ISD
REGISTER

BIT

I i I I I I I I I I I I I I I I I
!'

)

NDAC <8: 1> (R/W)
(DATA LINES)
DAC (R) (NDAC INVERTED)
DAV (R)
RFD (R) (NRFD INVERTED)
SRQ (R)
REN (R)
IFC (R)
ATN(R)
EOI(R)

I
R/W = Read I Write Bit
R
= Read - Only Bit
*Moy be written only if ERl inhibit switch is on.
NOTE:

Figure 2-3

11 - 4716

IBVII-A Register and Bit Assignments

2-8

Table 2-3

IBS Register Bits Descriptions

Bit

Function

Take Control Synchronously (TCS). Set and cleared under program control to enable or
disable the IBVII-A controller-in-charge function by taking control synchronously or by
negating ATN. Setting TCS will cause NRFD to be asserted for at least 500 ns before DA V
is checked. A TN is then asserted when DAVis not asserted. NRFD must be un asserted and
CMD is set 500 ns (minimum) after ATN is (1sserted. TCS is cleared by BINIT Land IFC.

End or Poll (EOP). Set and cleared under program control to assert or un assert the EOI line.
EOP is cleared by BINIT Land IFC.

Remote On (REM). Set and cleared under program control to assert or un assert the REN
line. REM is cleared by BINIT Land IFC.

Interface Bus Clear (IBC). When set, the leading edge of IBC produces IFC for 125 J,LS
(approximately). At the end of IFC, TCS is automatically asserted and IBC is automatically
cleared. IBe is cleared by BI1'-~IT L.

Listener On (LON). Set or cleared by the program to enable or disable the IBV ll-A listener
function. When LON is set and the DA V line is asserted, the IBS LNR bit (bit 08) becomes
set. When LON is cleared, the IBVI1-A ignores DAV LON is cleared by BINIT Land IFC.

Talker On (TON). Set or cleared by the program to enable or disable the IBVII-A talker
function. TON is cleared by BINIT Land IFC.

Interrupt Enable (IE). Set and cleared by the program to enable or disable IBVII-A interfuptS. IE is cleared by BINIT L.

Accept Data (ACC). Set and cleared by the program. When ACC is cleared, reading a data
byte from the DIO lines will automatically assert the DAC line and clear the LNR bit (bit
08). When ACC is set, the program must clear the low byte of the IBD register in order to
clear the LNR status bit and assert the DAC line. ACC is cleared by BINIT Land IFC when
LON, TON, and TCS are all off; ACC may be set to assert NRFD.

Listener Ready (LNR). When set, LNR indicates that the IBVII-A has a data or command
byte that is ready for reading from the low byte of the IBD. LNR is set when LON is set and
the DA V line becomes asserted. LNR is cleared by reading the IBD low byte if ACC is
cleared, or by clearing the IBD low byte if ACC is set. LNR is also cleared when LON is
cleared by the program and by BINIT Land IFC.

Talker Ready (TKR). When set, TKR indicates to the LSI-II processor that the IBV II-A is
ready for the next data byte to be transmitted to the DIO lines via the low byte of the IBD
register. TKR is set when TON is set, TCS is cleared, and when listeners are ready for data.
TKR is cleared by BINIT L or IFC, by writing a command or data byte into the low byte of
the IBD register, or by the program clearing TON or setting TCS.

2-9

Table 2-3

IBS Register Bit Descriptions (Cont)

Bit

Function

Command Done (CMD). When set, CMD indicates to the LSI-II processor that the IBVllA is ready for the next command byte to be transmitted to the DIO lines via the low byte of
the IBD register. CMD is set by a successful TCS to indicate that the A TN line was asserted
and that the next command byte may be transmitted over the instrument bus. CMD is also
set when the DAC line is asserted after the command has been accepted by the addressed
device on the instrument bus. CMD is cleared by BINIT L or IFC, by writing a byte (command) into the low byte of the IBD register, or by the program clearing the TCS bit.

Not used - read as o.

Not used - read as O.

Error I (ER I). Set whenever a conflict occurs between the instrument bus A TN, IFC, ~r
REN lines and their IBVII-A control hardware. When set, ATN H is cleared and cannot be
set. This condition can only be cleared by clearing the cause of the error. ERI can occur
when another system controller is connected to the instrument bus. The error can then be
suppressed by setting the ERI inhibit switch (SI-8) on the IBVII-A module to the ON
position. If the IBVII-,A is the only system controller, set S 1-8 to the OFF position.

Error 2 (ER2). Set when the IBVI1-A tries to send a data or command byte while there is no
active listener or command acceptor on the instrument bus. ER2 is cleared by clearing both
the TON and TCS bits.

Service Request (SRQ). This bit always indicates the status of the instrument bus SRQ line.
It may be written (set and cleared) if the ER 1 inhibit switch is set.

Table 2-4

IBD Register Bit Descriptions

Bit

Function

< 15:8>

Instrument bus control line status. The program can monitor the signal status of all eight
control signals by reading this byte. Note that DAC (bit 08) and RFD (bit 10) are inverted
with respect to the actual instrument bus signal lines.

<7:0>

Instrument bus data input/output. The program can read or write via this register byte to
receive or transmit command or data bytes over the instrument bus. Bits <7:0> correspond
to DIO lines <8:1>.

Interrupts
The IBVII-A is capable of generating four separate interrupt requests; each has separate interrupt
vectors and normally would have separate service routines. Interrupts can be requested only when the
IBS interrupt enable (IE) bit is set. Interrupt requests are priority structured in the IBVII-A. A summary of the four interrupt types is provided in Table 2-5.

2-10

Table 2-5

IBVI1-A Interrupt Vectors

Priority

Vector

Associated
IBS Bit

Cause of Interrupt

Highest

OOOXNNOO

ER2, ERI

Error condition.

Second
highest

000XNN04

SRQ

A device connected to the instrument bus is
requesting service.

Third
highest

000XNNI0

TKR,CMD

The IBVII-A is an active talker and it is ready
for the LSI-ll processor to output a byte to
the low byte of the IBD register. [The IBVIIA will normally then transmit the byte over
the instrument bus to the active listener(s).]

Lowest

OOOXNNI4

LNR

The IBVII-A is an active listener and has a
data byte to be read by the LSI-II processor.
Notes

2.3

x = User-configured vector address octal digit.

N = User-configured vector address binary
bits.

Associated IBS bits shown, when set, produce
interrupt requests if the IE bit is set.

INSTRUMENT BUS CONTROLLER-IN-CHARGE COMMANDS

2.3.1 General
Controller-in-charge commands may only be issued by an active controller-in-charge. When the system controller asserts the IFC control line, it designates a specific controller as the controller-incharge. A controller may also become the controller-in-charge when the current controller-in-charge
specifically transfers control to it with the "take control" command. The IBVII-A will detect a successful transfer of control as an ERI condition (if SI-8 is in the OFF position) because it normally is
the controller-in-charge as well as the system controller; ER 1 can be avoided (when another device
becomes controller-in-charge) by setting SI-8 on the IBVII-A module to the ON position.
A controller-in-charge becomes active 2 J.LS after asserting the A TN control line. First, the controllerin-charge stops further data byte transfers between the active talker and active listeners by asserting the
NRFD line and then waits for the talker to unassert the DA V line. When DAVis unasserted, the
controller-in-charge asserts A TN to declare its contra! of the DI0 message lines. The controller-incharge waits for 0.5 J.LS after asserting ATN before uhasserting the NRFD line so that the talker and
listeners will have enough time to recognize and respond to the asserted A TN line.

2-11

While active, the controller-in-charge uses the DIO lines to issue command bytes to all devices on the
instrument bus. All controller-in-charge commands are coded into a 7-bit command byte on
DIO<7: 1>. The DI08 line remains unasserted, and is not decoded by devices when a command byte
is received. The command byte MSB is on DI07; the LSB is on DIO 1. Command bytes are restricted
to 7 bits so that their coding may be correlated to the ISO 7-bit code (or the equivalent code in the
American National Standard Code for Information Interchange, ANSI X3.4-1968) because it is convenient to both generate and interpret this code.
Command decoding in the IBVII-A, if desired, must be handled by software.
2.3.2 Addressed Command Group (A CG)
Commands in this group (Table 2-6) affect only the currently addressed talker or the currently
addressed list of listeners.

Command
Mnemonic

ASCII
Character

GTL
SDC
PPC
GET
TCT

SOH
EOT
ENQ
BS
TAB

Table 2-6

Addressed Command Group

ASCII
Code

Keyboard
Function

Devices
Affected

Command
Function

001

CTRLA
CTRLD
CTRLE
CTRLH
CTRLI

Listeners
Listeners
Listeners
Listeners
Talker

Go to Local
Selected Device Clear
Parallel Poll Configure
Group Execute Trigger
Take Control

004

005
010
011

Go to Local (GTL) - The GTL command causes addressed listeners to go from the remote mode
to the local mode. When in the local mode, a device is controlled by its front and rear panel
controls.
Selected Device Clear (SDC) - The SDC command causes addressed listeners to be cleared
(initialized).
Parallel Poll Configure (PPC) - The PPC command causes addressed listeners to enter the parallel poll configure mode. The next command must be from the secondary command group; otherwise, the listeners will exit the parallel poll configure mode. While in parallel poll configure mode,
the listeners will interpret all secondary command group commands as 1 of the 16 possible Parallel Poll Enable (PPE) commands or as the PPD (Parallel Poll Disable) command.
Group Execute Trigger (GET) - The GET command causes the addressed listeners to start the
basic operation of the device that the listener is a part of (only if that operation is at rest when this
command is received).
Take Control (TCT) - The TCT command causes the addressed talker of a controller to enable
the controller to become the controller-in-charge as soon as the current controller-in-charge unasserts A TN. Controller-in-charge status can be transferred in an orderly manner from one controller to another by the current controller-in-charge addressing the talker of the next controllerin-charge, and then issuing the TCT command followed by unasserting A TN.

2-12

2.3.3 Universal Command Group (UCG)
Commands in this group (Table 2-7) affect all devices able to respond without having to be previously
addressed. The IEEE standard permits the first three of these commands to be issued while the system
controller is asserting IFC. However, the ability to issue commands during IFC is not permitted in the
IBVII-A.
Local Lockout (LLO) - The LLO command causes all instruments to ignore their local "return to
local" signal. This command can be countermanded only by powering the instrument off and
then on, or by the system controller unasserting the REN control line.
Device Clear (DCL) - The DCL command causes all devices on the instrument bus to be cleared
(initialized).
Parallel Poll Unconfigure (PPU) - The PPU command causes all parallel poll configurations to be
cleared (unconfigured). Only devices that have been parallel poll configured will respond to a
"parallel poll" request. After the PPU command, no device will respond to a "parallel poll"
request.
Serial Poll Enable (SPE) - The SPE command causes all talkers to enter the serial poll mode.
When in serial poll mode, an addressed talker will respond to the un assertion of the A TN control
line by sending its device's status byte to the controller-in-charge. When the controller-in-charge
asserts ATN after a talker has responded with a status byte, bit 7 of the status byte will be cleared
if it was set. This will in turn cause the talker to un assert its SRQ line driver if it was asserted.
Serial Poll Disable (SPD) - The SPD command causes all talkers to exit the serial poll mode and
return to the normal data mode where an active talker sends data bytes rather than a single status
byte.
Table 2-7

Universal Command Group

Command
Mnemonic

ASCII
Character

ASCII
Code

Keyboard
Function

Command
Function

LLO
DCL
PPU
SPE
SPD

DCI
DC4
NAK
CAN
EM

021
024
025
030
031

CTRLQ
CTRLT
CTRLU
CTRLX
CTRLY

Local Lockout
Device Clear
Parallel Poll U nconfigure
Serial Poll Enable
Serial Poll Disable

2.3.4 Listener Address Group (LAG)
Commands in this group (Table 2-8) are used to address one or more listeners at a time or to unaddress
all listeners at once. Listener addresses specified by these commands are called primary listener
addresses because they can be followed by a secondary address from the secondary command group to
address an extended listener. Addressed listeners become active listeners when the controller-in-charge
unasserts A TN.

2-13

Primary and secondary listener address decoding in the IBVII-A, if desired, must be handled by
software.
My Listen Address (MLAn) - The MLA command covers 31 primary listener addresses. Any
listener that recognizes its own address becomes an addressed listener. Only addressed listeners
are able to receive data bytes from a talker.
Unlisten (UNL) - The UNL command causes all listeners to become unaddressed.

Table 2-8

Listener Address Group Commands

Command
Mnemonic

ASCII
Character

ASCII
Code

MLAOO
MLAOI
MLA02
MLA03
MLA04
MLA05
MLA06
MLA07
MLA08
MLA09
MLAIO
MLAli
MLA12
MLA13

SP
!
"

$
%
,&
(
)

*
1+
,

! Ii
MLA1~

!
I .

MLA15
MLA16
MLA17
MLAJ8
MLAI9
MLA20
MLA21
MLA22
MLA23
MLA24
MLA25
MLA26
MLA27
MLA28
MLA29
MLA30
UNL

ii 1
'2

13
4
5
6
7
8
9
,

=
>
?

040
041
042
043
044
045
046
047
050
051
052
053
054
055
!
I 056
I 057
! 060
, 061
I
' 062
063
064
065
066
067
070
071
072
073
074
075
076
077

Keyboard
Function

Command Function
My Listen Address 0
1
2
3
4
5
6
7
8
9
10
11
12
13

Space
!
"

$
%
&
,
(
)

I0i
1

II 1

3
4
5
6
7
8
9
,

=
>
?

2-14

1--1
.-r

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
My Listen Address 30
Unlisten

2.3.5 Talker Address Group (TAG)
Commands in this group (Table 2-9) are used to address or un address one talker at a time. Talker
addresses in this group are called primary talker addresses because they can be followed by a secondary address from the secondary command group to address an extended talker. An addressed talker
becomes active when the controller-in-charge un asserts A TN.
Primary and secondary talker address decoding in the IBVII-A, if desired, must be handled by
software.
My Talk Address (MTAn) - The MT A command covers 31 primary talker addresses. Any talker
that recognizes its own address becomes addressed while all other talkers become unaddressed.
Only an addressed talker is able to send data bytes.
Untalk (UNT) - The UNT command causes the addressed talker to become unaddressed without
addressing another talker.
Table 2-9

Talker Address Group Commands

Command
Mnemonic

ASCII
Character

ASCII
Code

Keyboard
Function

MTAOO
MTAOI
MTA02
MTA03
MTA04
MTA05
MTA06
MTA07
MTA08
MTA09
MTAIO
MTAII
MTAI2
MTAI3
MTAI4
MTAI5
MTAI6
MTAI7
MTAI8
MTA19
MTA20
MTA21
MTA22

100
101
102
103
104
105
106
107
110
111
112
113
114
115
116
117
120
121
122
123
124
125
126
127
130
131
132
133
134
135
i36
137

l\ATA1'l
1T • .11"'1. . . ....,

MTA24
MTA25
MTA26
MTA27
MTA28
MTA29
MTA30
UNT

A
B
C

0
E

F
G
H
I
J
K
L
M
N

0
P
Q
R
S
T
U
V
W
X
y
Z
[

\
] or i
/\
-or~

A
B
C

0
E

F
G
H
I
J
K
L
M
N

0
P
Q
R
S
T
U
V
W
X
Y
Z
[

\
] or i
1\
- or +2-15

Command Function
My Talk Address 0
1
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
My Talk Address 30
Untalk

2.3.6 Secondary Command Group (SCG)
The commands in this group are used to modify the parallel poll configure (PPC) command or to
specify an extended talker or listener address. This group consists of 32 codes starting with the ASCII
code for "grave." However, the last code, equivalent to the ASCII code for delete, is not used.
Parallel Poll Enable/Disable Commands (PPE/PPD) - Each parallel poll enable (PPE) command
(Table 2-10) must follow a parallel poll configure (PPC) command, which puts currently
addressed listeners into parallel poll configure mode. Usually, only one listener is addressed
before a PPC command is issued so that the PPE command will affect only one device at a time.
However, more than one device may be affected by a single PPE command when this is desirable.
The PPE command is used to dynamically instruct (program) some devices as to how to respond
to a parallel poll request. The response to a parallel poll request in some devices is determined by
hardware that is field-settable during system configuration. Some devices, including the IBVII-A,
are unable to respond to a parallel poll request.
A device responds to a parallel poll request by returning one bit of status to the controller-incharge on one of the eight DIO lines.
The second digit of the PPE command mnemonic specifies the DIO line to use. The first digit of
the PPE command mnemonic specifies which logical state of the status bit should cause the DIO
line to be asserted low. Thus, the PPE15 form of the PPE command instructs the device to
respond to a parallel poll request by asserting DIO line 5 if the status bit is a logical 1.

Table 2-10

Command
Mnemonic

ASCII
Character

PPEOI
PPE02
PPE03
PPE04
PPE05
PPE06
PPE07
PPE08
PPEl1
PPE12
PPE13
PPE14
PPE15
PPE16
PPE17
PPE18
PPD
(Not used)

'\.

Parallel Poll Enable/Disable Commands

ASCII
Code
5

(Not used)

140
141
142
143
144
145
146
147
150
151
152
153
154
155
156
157
160
161

~DEL

177

a
b
c
d
e
f
g
h

J
k
I
m
n
0

Keyboard
Function

\..

a
b
c
d
e
f
g
h

J
k
I
m
n
0

P
q

~DEL

2-16

Command Function
Parallel Poll Enable 1
2
3
I
4
5
6
7
8
11
12
13
14
15
16
17
Parallel Poll Enable 18
Parallel Poll Disable

The process of selecting a device by addressing a listener, commanding it to enter the parallel poll
configure mode, and instructing it how to respond to a parallel poll request is called configuring a
parallel poll response. Once configured, a device remembers how to respond to the parallel poll
request until it is reconfigured by another PPE or unconfigured by a parallel poll disable (PPD) or
a parallel poll un configure (PPU) command.
A parallel poll request is issued by the controller-in-charge by asserting the EOI control line along
with the A TN control line.
The PPD command, like all secondary commands, must follow its associated primary command.
The PPD command selectively disables (unconfigures) devices from responding to the parallel
poll request. The particular devices affected by the PPD command are those devices that have
active listeners that respond to the preceding PPC command.
My Secondary Address Commands (MSAn) - An MSA command, when used, must follow an
MLA or MT A primary address command. The 31 MSA commands are denoted by the mnemonics MSAOO through MSA30 with codes equivalent to the ASCII codes from "grave" to "tilde." A
secondary address is used to specify an extended talker or listener address. Devices that use
extended addressing do not become addressed until the proper secondary address follows the
proper primary address. "My secondary address" commands are listed in Table 2-11.

2-17

Table 2-11

My Secondary Address Commands

Command
Mnemonic

ASCII
Character

ASCII
Code

Keyboard
Function

MSAOO
MSAOI
MSA02
MSA03
MSA04
MSA05
MSA06
MSA07
MSA08
MSA09
MSAI0
MSAll
MSA12
MSA13
MSA14
MSA15
MSAI6
MSAI7
MSAl8
MSAI9
MSA20
MSA21
MSA22
MSA23
MSA24
MSA25
MSA26
MSA27
MSA28
MSA29
MSA30
Not used

140
141
142
143
144
145
146
147
150
151
152
153
154
155
156
157
160
161
162
163
164
165
166
167
170
171
172
173
174
175
176
177

a
b
c
d

e
f
g

h
1

J
k
1

m
n
0

P
q
r
s
t
u
v
w

x
Y

z
{

DEL

a
b
c
d
e
f
g

h
1

J
k
1

m
n
0

r
s
t
u
v
w

x
Y

{

DEL

2-18

Command Function
My Secondary Address 0
1
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
My Secondary Address 30

CHAPTER 3
INSTALLATION

3.1

MINIMUM SYSTEM REQUIREMENTS

3.1.1 System Hardware
System hardware can range from very simple LSI-II execute-only systems through dual floppy disk
systems running under the R T -11 operating system software. LSI-II systems fall into three general
categories: LSI-II component systems, PDP-I 1/03 systems, and PDP-II V03 systems. LSI-ll component systems and PDP-I 1/03 (packaged LSI-II) systems are configured by the user, ranging from a
basic 4K memory and LSI-II processor upward to a more complex configuration. Expansion beyond
the basic system requires the addition of various standard LSI-II options, including system memory,
serial and parallel interfaces for peripherals, floppy disk, etc. All PDP-II V03 systems, however,
include 8K memory, a console terminal (VT52 or LA36), and RT-II operating system software as part
of the basic system. The basic PDP-II V03 is factory-configured and shipped as a ready-to-use system
capable of developing user-software. The user can add hardware options, such as the IBVII-A, as
desired.
For a simple execute-only system, the minimum system hardware requirements include a console
terminal, a means for loading object programs, and the IBVII-A interface. In addition, LSI-II component systems require an LSI-11 processor and 4K memory, one or more backplanes, and +5 V and
+ 12 V power supplies. A simple execute-only system (that is, one that will execute but not develop user
application software) can consist of the basic components listed below:
Option

System Function

KDII-F* or
KDll-J

LSI-II processor and 4K memory

DLVII

Serial line interface for console terminal (an optional BC05M or BC05C
cable is required for connection to the terminal)

H9270* or
DDVII-B

System backplane

VT50, VT52,
LA36, LT33,
etc.

Console terminal

H780* (or
equivalent)

Power supply

IBVII-A

Instrument bus interface

*Included in the basic PDP-II /03 system.

3-1

Note that the KDII-F processor and 4K memory uses semiconductor memory which is volatile (programs and data are lost when system power is turned off) and programs must be loaded each time
power is turned on. The KD II-J uses non-volatile 4K core memory and normally does not require
reloading programs. Non-volatile storage can also be obtained by the use of the MRVII-AA 4K
programmable read-only memory (PROM) option or the MRVII-BA 4K UV PROM/256 RAM
option; these options are supplied without PROM integrated circuits (lCs). PROM options are available from DIGITAL.
The execute-only system, as described, is not capable of developing user application software. Minimum requirements for a paper tape system capable of program development include 8K (total)
read/write memory and a paper tape reader/punch. The paper tape reader must be capable of being
turned on and off under program control. Either a high-speed or low-speed (110 baud) reader/punch
can be used. A low-speed reader/punch function can be implemented by connecting an L T33
Teletype® (DEC-modified ASR33) to a DLVII serial line interface; the Teletype can also function as
the console device. DIG IT AL can supply a modification kit for the ASR33 as option model LT33-MB.
A modified ASR33 for 115 V, 60 Hz operation is available from DIGITAL as option model LT33-DC.
If desired, a high-speed reader/punch (user-supplied) can be interfaced to the LSI-II system as
directed in the Digital Components Group Application Note, An LSI-II Paper Tape Reader/ Punch
Interface.
Floppy-disk-based systems are capable of maximum flexibility for user program development and
applications. Any LSI-II system capable of executing RT-II operating system software is capable of
supporting IBVII-A applications, including program development. Any LSI-II system containing 8K
read/write memory and a console device can be expanded for RT-II operation by adding the RXVII
floppy disk option and appropriate software. The PDP-II V03 system includes the required hardware
and software to support RT -II.

3.1.2 System Software
3.1.2.1 General- The only software required for IBVII-A operation in an LSI-II system is the binary
program for a specific application. However, in order to generate a binary program on the system,
certain software options will aid the program development process. A brief list of software options is
provided below.
For assembly language program development:
1.

Paper tape system software
QJVIO-CB - This software option includes ED-II Text Editor, PASIIS Assembler,
LINKII Linker, DUMPAB Memory Dump Utility, ODT-II On-Line Debugging Technique, lOX Input/Output Executive, and the Absolute Loader.

QJVII-CB, PROM Formatter - This software option reads binary object tapes and produces punched paper tapes (for automatic PROM programmers) and listings that are compatible with MRVII-AA and MRVII-BA applications.
2.

Floppy disk software
QJ003-A Y or QJ003-CY, RT-II Operating System - This software option includes: EDIT
text editor, MACRO assembler (required 12K read/write memory), EXPAND macro
expander, ASEMBL assembler, and various system and utility programs. EXPAND and
ASEMBL allow program assembly on the basic 8K floppy disk LSI-II system. RT-II is a
very comprehensive software option and is described in much greater detail in the Microcomputer Handbook, Section 4.

-----®Teletype is a registered trademark of Teletype Corporation.
3-2

For high-level language program development:
1.

FORTRAN
QJ925-A Y or QJ925-CY - RT-11jFORTRAN

BASIC
QJ920-AY or QJ920-CY - RT-lljBASIC

NOTE
The above software options run under the RT-ll
operating system. Routines for IBVII-A support for
FORTRAN and BASIC are planned options; however, they are not presently available.
3.2 CONFIGURING THE IBVII-A MODULE
Each IBV 11-A module is factory-configured for standard device register and interrupt vector addresses. Switches S 1 (vector address) and S2 (device register) configure the addresses. A summary of register
and vector addressing is provided in Figures 3-1 and 3-2. Observe that only the IBS register address is
configured. The IBD register address is always the ISS address plus 2. Similarly, only the error interrupt vector address is configured. The remaining three vector addresses are permanently assigned
sequential addresses in address increments of four, as follows:
Vector
Error
Service
Command and Talker
Listener

Address
"n" (configured address)

n+4

n + 108

n + 148

Switches SI and S2 are located on the IBV11-A module as shown in Figure 3-3. Sl and S2 are switch
assemblies, each containing several individual switches. The individual switches indicated in Figures
3-1 and 3-2 are clearly marked on the S 1 and S2 assemblies. The ON and OFF positions are also
clearly marked.

IBS REGISTER ADDRESS FORMAT
15

CONF~~~~g~,~DN ~,D~O~;~~

TTTTTTI I TI

O=IBS REGISTER
1 = IBD REGISTER
NORMALLY 0
(RESERVED FOR
FUTURE USE)

S2 IN DIVI DUAL
2
3
4
56?
8
9
10
SWITCH NUMBERS LI_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....J
NOTES:
1. OFF=Logical 0; ON=Logical1
2. Only the IBS REG ISTER ADDRESS is configured via S2. The IBD REGISTER ADDRESS always equals the
ISS REGISTER ADDRESS +2.
11- 4887

Figure 3-1

Configuring the IBV 11-A Register Addresses
3-3

STANDARD VECTOR ADDRESS
CONFIGURATION (000420)

1 III
I

OFF

~ INTERRUPT VECTOR

o = ERROR

0
1

o " COMMAND AND TALKER

1 = LISTENER

t = SERVICE REQUEST

NOT USED

S1 INDIVIDUAL
SWITCH NUMBERS

ON =DISABLE ERR1

r-~--~----~--~--~~-~----------~--' (NOTE
INTERRUPTS
3)
~

2
3
4
5
6
7
____________________________________

OFF= NORMAL
(ENABLE)
INTERRUPTS

~ERR1

NOTES:
1. OFF = Logical 0; ON =Logical 1
2. Only the VECTOR ADDRESS bits (8:4) are configured via 51. Bits 3 ond 2 are IBV11-A
hardware - selected for the funC'tions shown
3. 51-8 OFF: IBVt1-A is the only system controller connected to the instrument bus.
S~-S

ON· Another system controller !s connected to the instrument bus,
11-4888

Figure 3-2 Configuring the IBVII-A Interrupt Vector Addresses

3-4

20- PIN
INSTRUMENT BUS
CABLE CONNECTOR

0 0

000 [DO

0 0 0 000 000000
o

Ilnlliillnllnll

lliill

DOD ~ODO

00
0 00

UUUUUUUUU
UUU
o
0 DOD

VECTOR ADDRESS
SELECT SWITCHES
(SI)

DEVICE
(IBS a ISD REGISTERS)
ADDRESS SELECT
SWITCHES
(S2)

o
D
I

~----'

Figure 3-3

IBV11 Module Switch Locations

3-5

I
11-4889

3.3 INSTALLING IN THE LSI-II BACKPLANE
The general procedure for installing the IBV ll-A module in the LSI-II backplane is the same as for
any other peripheral interface. Prior to installing the module, determine the desired peripheral device
priority as described in the Microcomputer Handbook, Section 1, Chapter 3, and Chapter 6, Paragraph 6.3. Module insertion and removal is described in Section 1, Chapter 6, Paragraph 6.4.
3.4 CONNECTING TO EXTERNAL EQUIPMENT
Connection from the IBVII-A to the first device on the instrument bus is via a type BNIIA cable as
shown in Figure 3-4. One end is terminated with a 20-pin connector that mates with the 20-pin connector on the IBVI1-A module. The other end is terminated with a 24-pin "double-ended" connector
that conforms with the IEEE 488-1975 standard; the cable can be connected to any device conforming
to that standard. The double-ended connector contains a male 24-pin and a female 24-pin connector in
the same connector housing. This allows for "linear" and "star" connections to instruments connected
to the instrument bus, as shown in Figure 3-5.

PIN A
11-4890

Figure 3-4

BNI1A Instrument Bus Cable

!he linear. arrang~m~nt shown in Figure 3-5 includes five devices (or instruments), A through E. There
IS n? partIcular slgmficanc~ ~o the sequence shown or electrical position along the instrument bus.
U nhke the LSI-1t bus, posItIon along the bus does not structure device priority in the system.
!he star. arrangement shown in the figure allows five devices to be connected by stacking BNOIA
!nstrument cable connectors on the BN llA's double-ended connector. Double-ended connectors on
Instrument ~us cables will normally include captive locking screws on each connector assembly (two
each), allOWIng stacked connectors to be secured together in a single assembly.

3-6

BNOl A CABLES

,----.---., [) BN11A CABLE

DEVICE A

DEVICE B

DEVICE C

DEVICE D

DEVICE E

(A) LINEAR ARRANGEMENT

DEVICE
LJ

SN01A CABLES

BNllA CABLE

u
(8)

STAR ARRANGEMENT
11- 4891

Figure 3-5

Linear and Star Configurations

BNIIA and BNOIA cable connector pin signal assignments are listed in Table 3-1 for each connector.
One 4 m (157.5 in) BNIIA-04 cable is supplied with each IBVII-A option. Additional BNIIA cables
are available in the fol1owing lengths:
Model

Length

BNllA-OI
BNIIA-02
BNIIA-04

1 m (39.4 in)
2 m (78.7 in)
4 m (157.5 in)

BNOIA cables are available in the following lengths:
Model

BNOIA-Ol
BNOIA-02
BNOIA-04

Length
1 m (39.4 in)

2 m (78.7 in)
4 m (157.5 in)

3-7

Table 3-1

BNIIA and BNOIA Connector Pin Assignments

BNIIA (only)
IBVII-A
Connector Pin
U
S
p
M
R
T
V
X
B

J
F
K
H
E
C
D

N
A,L
W

BNIIA and BNOIA
Instrument Bus
Connector Pin

Signal
Name

{
{

DIOI
DI02
DI03
DI04
EOI
DAV
NRFD
NDAC
IFC
SRQ
ATN
(SHIELD)
DI05
DI06
DI07
DI08
REN
GND (DA V GND)
GND (NRFD GND)
GND (NDAC GND)
GND (IFe GND)
GND (SRQ GND)
GND (A TN GND)
G ND (OG
L TI C,)

3-8

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21
22
23
2..1

CHAPTER 4
PROGRAMMING EXAMPLES

4.1 GENERAL
This chapter contains two programming examples that illustrate how the LSI-II system can communicate with instruments via the IBVII-A. No attempt is made to restrict these programming examples
to specific devices. Refer to programming instructions included with the programmable instruments
for specific procedures, including codes (ASCII characters) for device addressing, setting modes,
ranges, etc. LSI-II program listings, flowcharts, memory maps, and detailed descriptions are included
for each example.
Both programming examples have been executed on an LSI-II system. The programs were entered
manually via the console terminal using console ODT commands. In an actual applications environment, however, routines, similar to these programming examples, would function as parts of a larger
program. Additional features, such as the ability to enter instrument parameters directly from the
console keyboard and display processed results would be incorporated. No attempt is made in these
examples to illustrate those features since each application, available hardware, and programmer's
skill will vary. However, the examples do illustrate how the IBVII-A can be programmed to perform
useful tasks.
4.2

EXAMPLE 1 - IBVII-A TO LISTENER DEVICE

4.2.1 General
This programming example illustrates how the IBVll-A communicates with a listener device. Standard device and vector addresses are used, as shown in Figures 3-1 and 3-2. Once the program is started,
and after pointers have been initialized and the IBVII-A has taken control synchronously, the program communicates with the IBVII-A via an interrupt-driven service routine. No "background" program is used; the program simply "waits" until another interrupt occurs.
Communication with the listener device includes the transmission of 2 command bytes (read as words
from a message buffer), followed by 24 message bytes that program device functions. After all message
bytes have been transmitted, the program halts (displayed HALT PC address = 1066).
A program flowchart for this example is shown in Figure 4-1, and a symbolic listing is shown in Figure
4-2. Figure 4-3 is a memory map for the program. Refer to those figures when reading the description
of program operation in the following paragraphs.

4-1

END

I..
11-5231

Figure 4-1

Example 1, Communicating with a Listener Device
Program Flowchart

4-2

(.~DDHESS

DCTfiL
CODE

ASSEMBLER SYNT ~~X

INTR RETURN ADDRESS
PSW

() () r.) ./!. ~..:~: ::~.~

001020
000200

001000
001002
001004
001006
001010
00:1.012
00:1.0:1.4

012706
000500
012i'OO
002000
012737
000110
160150

START: MOV t500,R6

00:1.016
001020
001022
001024
001026
001030
001032
00:1.034
001036
001040

OOO"7?"?
022"700
002004
100006
012"737
000105
:L60 1. ~::j()
012037

WAIT:

001042
001044
001046

022700
002004
003003
012"737
000144

() () () .{~. :::::: ()

0010~:50

0010~52

001054
001056
001060
00106~.~

00:1.064

CO;Vi~/jENTS

SET UP STACK POINTER

MOV :JI:2()OO,RO

RO IS MSG BUFFER ADDRESS

~'10V

T(.~KE CONTROL
SYNCHRONOUSLY TO BECOME
CONTROLLER-IN-CHARGE

:fI:l10,:L601~)O

C~iP

:11=2004, F~()

BPL 20$
MOV *105,160150

WAIT FOR INTERRUPT
MORE COMMANDS TO BE SENT?
IF NO,GO TO 20$
IF YES,SET IE,REM,AND
; Tes BITS OF IBS REG TO
l~eT I VI~ TE

SEND:

CDNTHOL.i...EF~

MOV (RO>+,160152; SEND MSG TO IB

1601~')2

000002

RTI
20$:

eMF' :1=2004 !I F<O

BGT ::~O~~
MOV :11=:1.44, :l.601~:;0

160:L~50

022700
002062
100364
000000

30$:

CMF' :fI:2062!1RO
BMI SEND

RETURN TO WAIT--FOR
MSG TO BE ACCEPTED
IS TALKER ACTIVE?
IF YES.,GO TO 30$
OTHERWISE SET IE,TON
AND REM BITS OF IDS REG
TO ACTIVATE TALKER
HAD ALL MSG BEEN SENT?
IF NO,GO SEND ANOTHER MSG
OTHERWISE STOP

HI~LT

11-5232

Figure 4-2

Example 1, Communicating with a Listener Device
Program Listing

4-3

STACK

R6 (SP)

500

IBV11-A TKR/CMD
INTERRUPT
VECTOR PC & PS

{

430
432

1000

1064

r---.-

..,.....".

RO (MSG BFFR PTR)

2000

UNLCOMMAND
MLA COMMAND

1
}

SET-UP DEVICE
LISTEN ADDRESS

MESSAGE
BUFFER

SET-UP

>OPERATING

PARAMETERS
(MODE, FREOUENCY,
AMPLITUDE)

2062

HIGHEST MEMORY
LOCATION

---iJ"=
11-<:;213

Figure 4-3

Memory Map for Example 1

4-4

4.2.2 Program Operation
Prior to starting the program, it is assumed that interrupts are enabled CPS bit 07 = 0). The program is
started at address 1000. The first MOV instruction (at location 1000) initializes the stack pointer (R6)
to 500. Note that this address is first decremented by two each time a new item is "pushed" onto the
stack in the usual manner; the content of R6 always points to the address of the last word pushed onto
the stack. Conversely, R6 is incremented after "popping" a word from the stack. In this programming
example, the stack is used for servicing the IBV11-A's interrupt requests; the interrupts will always
occur while executing the "wait" (BR.) instruction at location 1016. Thus, the PC pushed onto the
stack for this example is 1016, followed by the PS. These two words are popped from the stack to
restore the wait instruction by executing the RTI instruction at location 1040.
The next MOV instruction (at location 1004) initializes RO to 2000 for use as a message buffer address
pointer. The number of messages sent, and hence, the actual size of the message buffer, is dependent on
the requirements of the instrument being programmed. In this example, 26 10 locations are reserved for
the message buffer. This means that the message buffer's last address is 2062. During program execution, the CMP instruction at location 1056 tests RO to determine if all locations of the message buffer
have been transmitted to the addressed listener device.
The MOV instruction at iocation 1010 sets the IBVII-A's IBS register IE and IBC bits (bits 06 and 03).
The IBV11-A responds by generating a 125 f.,LS IFC pulse, followed by "taking control synchronously."
Once this operation is completed, the IBS CMD bit becomes set and the IBV11-A's TKR or CMD
interrupt request is enabled. The vector address for this interrupt is 430 [the configured address (420 s)
+ lOs].
The BR. ("branch to self') instruction at location 1016 causes the program to "hang" (or wait) until
the interrupt occurs. The processor services the interrupt by pushing the previous PC and PS onto the
stack and uses the new PC (contents of location 430 = 1020) and PS (contents of location 432 = 200)
for the interrupt-driven routine; interrupts are disabled by the new PS.
In this example, the first two words in the message buffer are commands [UNL (unlisten) and MLA
(my listen address "n")]. The CMP instruction at location 1020 tests if the two commands have been
sent. Initially, RO = 2000; executing the CMP and BPL instructions results in executing the MOV
instruction at location 1026. The MOV instruction sets IBS IE, REM, and TCS bits to activate the
IBV11-A as the controller-in-charge. The MOV instruction at location 1034 is then executed, transmitting the first command byte to the instrument bus via the low byte of the IBV11-A's IBD register
(device address 160152). Note that RO is auto-incremented after it is used, causing it to point to the
next command in the message buffer. The RTI instruction at location 1040 is then executed, causing
the program to return to the BR. instruction at location 1016, and the program waits for the next
interrupt. When the interrupt occurs, it indicates that the command transfer over the instrument bus
has been completed. The second command is then transmitted in exactly the same manner. However,
note that the message buffer pointer content of RO is now 2004, and no more commands are to be sent.
When the next interrupt occurs, the CMP and BPL instructions following WAIT cause the program to
branch to 20$ (location 1042). Since the content of RO = 2004 at this point of program execution, the
branch (BGT) at location 1046 wi11 not be executed; instead; the MOV instruction at location 1050 is
executed, setting IBS register bits IE, TON, and REM, and the IBV11-A becomes an active talker.

4-5

Message bytes are now sequentially sent to the listener via the low byte of the IBVII-A's IBD register,
functioning as a talker on the instrument bus. The CMP instruction at location 1062 first checks if all
message bytes have been transmitted. If more bytes are to be transmitted, the BMI instruction causes
the program to branch to SEND. A word is then transmitted to the IBD register and the program exits
to WAIT until another interrupt occurs; the content of RO is now 2006. When the interrupt occurs,
CMP and BPL instructions cause the program to branch to 20$. Since RO now contains a message
buffer pointer greater than 2004, the eMP and BGT instructions cause the program to branch to 30$.
The program then checks if the last message buffer word has been transmitted. If not, the program
branches to SEND, another message byte is transmitted, etc., until all messages have been transmitted.
When all messages have been transmitted, the content of RO will be 2064. The CMP and BMI instructions (following 30$) will then result in the HALT instruction at location 1064 being executed, and the
program execution is completed. The instrument will then operate according to the command/program data received over the instrument bus.

4.3
4.3.1

EXAMPLE 2 - IBVII-A TO TALKER DEVICE
General

This programming example illustrates how the IBVII-A communicates 'with a talker device. As in
example 1, this programming example assumes standard IBVII-A device and interrupt vector addresses. Communication between the instrument and the LSI-II system is via IBVII-A interrupt-driven
service routines. No background program is used; the program simply "waits" until another interrupt
occurs.
Communication with the instrument involves first transmitting the content of the command message
buffer, in a manner similar to the program operation described for example 1, followed by accepting
instrument output data and storing it in a received data buffer. The content of the command message
buffer typically includes first activating the device via its listen address, followed by setting up range,
mode, etc. operating parameters for the instrument, an execute command, and, finally, activating the
device as an active talker via its talker address. Once the device has received the command message
buffer data, it performs the programmed measurements (or the function, depending on the instrument)
and returns data to the LSI-II system via the IBVI1-A; note that during this portion of program
operation, the IBV Il-A functions as an active listener on the instrument bus. Once all measurements
have been stored by the program, the program halts with a displayed PC address = 1102.
A program flowchart for this example is shown in Figure 4-4 and a symbolic program iisting is shown
in Figure 4-5. Figure 4-6 is a memory map for the program. Refer to those figures when reading the
description of program operation in the following paragraphs.

4.3.2

Program Operation

The program is started at location 1000. Prior to starting the program, it is assumed that interrupts are
enabled (PS bit 07 = 0) and the program and interrupt vector code has been loaded into system
memory as shown in Figure 4-5. The first four MOV instructions set up the stack pointer, initialize the
command message and received data buffer pointers RO and RI, respectively, and cause the IBVII-A
to take control synchronously. The program portion starting at WAIT (location 1022) through the
RTI instruction at location 1044 outputs the command message buffer in a manner similar to that
described for example 1.

4-6

11-5234

Figuie 4-4

Example 2, Communicating with a Talker Device

Program Flowchart

4-7

f:~DDF~ESb

(! <> ':,:' .:'~, :,: :; : .: '

(.-lSSEMBLEI:~

CODE

() () <> "::.'::;: ":;,
<,! .:. "',,,i -0;, ,,:';••:::.

() 00200
0 0 :l 0 ~::i t.)
000:;': () 0

00:1.000

0:1. :::~'?O6

o() :1. 0 0 ::.~

COMMENTS
COM MAN D/ TALI'< E I:~ I Nl F~
F~ETURN ADDRESS
PSW
LISTENER RETURN ADDRESS

STAF,:T!

M()~)

:1J:~:j()O!1 F~6

SET UP ST ~'~CK

j\i 0 I.)

:H:2000" F~O

IBV11-A MSG BUFFER

M()~)

:I~

MDV

l:l.lO~ :I. I.) 0 :I. ~::; ()

OOO~5()O

001004
OO:l.OOb

O:J.2/00
002()OO

0010:1.0
00:1.0:1.2

o1. :::.~ I' () :I.

002~)O()

00:1.0:1.4

():I. 21'3)'
()()O:l.:l.O

OO:l.Ol,:S

SYNTAX

00:1.020

:l.6():1.~:)()

00:1. O~.~2
OOlO::?·4

OOO"7I'?
0:1.273"7

001026

000 1. O~:.;

001030
00103::.:
00 :1. 034

160:l.~:50

W~~ IT:

BF~

2 ~:.:.i 0 0 , F~ l

BUFF FOR RECEIVED MSG
TAKE CONTROL SYNCHRONOUSLY
TO BECOME CONTROLLERIN····CHAI:~GE~, C . ·J···C
WAIT--FOR INTERRUPT
PF~EPI~I:~E TO SEND

t'·iO\.> :JI::I. 0::5 !I :I. (.)0:1. ~:50

CD~ii"irlND
:JI:20:::.~4!1 F~O

02::.:~)'()O

eMF'

0():l.O40

0020::?4
OO:l404
O:l.203?

BEQ 20$
MOV (RO)+~160152;

OO:J.042
00:1.044

OOOOO::?

00:1.046

0:1. 2'?~'~/

O():l.O~50

000320

00 :1. 036

Hf~D ~lL..L. COMMANDS
BEEN SENT?
IF YESyGO TO 20S
OTHERWISE SEND MSG

:l.60:l~52

O() 1 O~:)2

160:l.::=i()

00:1. O~54

OOOO()2

i=~ETUI:;:N TO WAIT····,· . FUF·~
MSG TO BE ACCEPTED
IBVll-A SWITCHES FRUM
CONTROLLER TO LISTENER

HTI
20$ +.;.

11DV

:1I=3::~O,:I.

60:1. ~::j()

RET Ut=~ N TO WA IT···· ..-

';'T'"
r,
, J.

;

00 :1. O~:'=;6

MESSI~:lGE~)

F()F~

DMM NSG

MOV 160:L52,(Rl)t; SAVE THE RECEIVED
I"1S(3 IN F~:l.
HAD 20 (OCTAL) MSG

O:l3)'21

001060

:U::, 0 1 52

00:1.062

00 :1. 064

() :::.~ ::~ ~:~I () 1
O()2!540

0010(~\6

00:1. 40~:~

BEG

:':)O~;

BEEN I!:tCCEPTED'?
I F YES:I GO TO 30~;

00:1.0'70

()O~.:j03?

CLF:

:I.6():I.~:)2

OTHERWISE ISSUE DAC

OO:LOl2
0010l4

:I. t.,():I. ~::.i2
000002

RTI

0010/6

OO~:;O3?

o() :1. :1. 0 ()

000000

:.30$:

CLF~

:I. 60 1 ~)2

HI!:tLT

RETURN TO WAIT--FOR
(.-IN()THEI~ DMr-f MSG
ISSUE VAC TO IE!
STOP~20 MSG RECEIVED
11-5235

Figure 4-5

Example 2, Communicating with a Talker Device
Program Listing

4-8

STACK

R6 (SP)

500

r----.
IBV11-A TKR/CMD
INTERRUPT VECTOR PC & PS
IBV11-A LNR
INTERRUPT VECTOR PC & PS

{

430

PC = 1024

432

PS=

434

PC = 1056

436

PS =

----

200

-------~
RO CMD MSG BFFR PTR)

~I-~.

2000

UNLCOMMAND

SET-UP DEVICE
LISTEN ADDR

MLA COMMAND
COMMAND
MESSAGE
BUFFER

2024
~

R1 (DATA BFFR PTR)
2500

2500

RECEIVED
DATA
BUFFER

:---

SET-UP
OPERATING
PARAMETERS,
TALKER ADDRESS
& EXECUTE COMMAND

----

2540

I
I

HIGHEST MEMORY
LOCATION
- - - . t_ _ _ _ _ _ _ _ __

11-5236

Figure 4-6

Memory Map for Example 2

4-9

When all command bytes have been transmitted to the addressed device, the program branches to 20$
(location 1046) and the MOV instruction at that address causes the IBVII-A to become an active
listener. This is followed by an RTI instruction and the program waits for the IBVII-A's listener
(LNR) interrupt to occur. When the interrupt occurs, the IBV11-A's IBD register, which contains the
first measurement data word (byte), is read and stored in the first received data buffer location (2500);
note that the received data buffer pointer (content of Rl) is incremented by two (one word address)
each time the IBD register is read. The CMP and BEQ instructions that follow test if all 16 10 data
words have been received. If not, the R TI instruction returns the program to WAIT until the next
IBVII-A LNR interrupt occurs. Operation continues in this manner until all data transfers have been
stored in the received data buffer. When the last buffer location has been filled, R 1 contains 25408 , the
last address in the received data buffer. Executing the CMP instruction (location 1062) and BEQ
instruction results in the program branching to 30$ (location 1076). Operation is then terminated by
first clearing the IBD register; the IBD responds by asserting DAC to complete the data transfer from
the instrument to the IBVII-A's IBD register. Finally, the program executes the HALT instruction
and the operation is completed.
The data contained in the received data buffer is device-dependent for its actual significance. In a
typical application, the HALT could be replaced by a branch (BR) or jump (JMP) instruction to
transfer control to a program that processes the received data.

4-10

CHAPTER 5
TECHNICAL DESCRIPTIQN

5.1 GENERAL
The functional logic blocks that comprise the IBVII-A are shown in Figure 5-1. LSI-II software
controls and communicates with the IBVII-A via programmed I/O transfers and interrupts. Refer to
the Microcomputer Handbook, Section 1, Chapter 3 for a complete description of LSI-II bus cycles,
including DA TO, DA TOB, DATI, DATIO, DA TIOB, and interrupt transactions.
5.2 DEViCE REGiSTERS
Programmed I/O transfers are made possible by assigning unique device addresses (also called "bus
addresses") to the IBS and IBD registers. The IBS register is the instrument bus status register; it is
generally similar in function to other PDP-II device control/status registers (CSRs). The IBD register
is the instrument bus data register. It is a 16-bit register that contains eight read/write data bits in the
low byte and eight read-only bits in the high byte. The eight read-only bits allow the program to read
the logical state of the instrument bus.
Functions of bits in the IBS and IBD registers are described in Paragraph 2.2.4.

5.3 LSI-II BUS INTERFACE
LSI-II bus address selection, interrupt vector address generation, and bus data driver/receiver (transceiver) functions are provided by transceiver integrated circuits (DC005). Each. integrated circuit provides the interface for four BDAL bus lines; thus, four transceivers comprise the 16-line BDAL
<00: 15> L LSI-II bus interface. Refer to Appendix A for a detailed description of the DC005 transceiver integrated circuit.
Device address switches provide a convenient means for the user to configure the IBVII-A's register
addresses. Only switches corresponding to BDAL lines <03: 12> are provided. By PDP-II convention,
the upper 4K address space (bank 7) is normally reserved for peripheral devices, such as the IBVII-A.
The LSI-II processor module asserts BBS7 L whenever a bank 7 address (BDAL < 13: 15> L are
asserted) is placed on the bus. Thus, BBS7 L must be asserted to enable an "address match" output
from the address selection function. Any address ranging from 16000X to 17777X can be configured,
as long as it does not conflict with other device addresses within the system; the X in the address
represents register and byte selection within the module.
The preferred addresses (for DEC software compatibility) are:
IBS = 160150
IBD = 160152
Bit 1 of the least significant octal digit selects the IBS or IBD register. The least significant bit (BDAL
0) is a byte pointer and it is significant for DATOB and DATIOB bus cycles only. Register address
selection is actually performed in the LSI-II bus protocol and register selection function; the transceiver integrated circuit simply routes the received low-order three address bits (DA <2:0» to that
function.
.
5-1

I
BRPLY L
LSI-II BUS
PROTOCOL
S
REGISTER
SELECTION

BSYNC L
BWTBT L
BDOUT L
BorN L

(DC004)
:I:

S2
DEVICE
ADDRESS
SWITCH
SA<12:3>

I II
I

::E

(f)
(f)

0:::
0

()
C\J

<t
0

~I
~I

0:::1

BUS
L- LSI-II
DEVICE
BSS7 L

J,CLK
SRQ
D-FLOP

DA15

LOAD IBD
LOW BYTE

::>
CD

- A
"
~ (BDAL <15:0~

r
I

SI
VECTOR
ADDRESS
SWITCH
SA<8:4>

~I CONTROL BUFFER

•

I ASSERT
I SRQ

SRQ
IBC

INTERRUPT
8
VECTOR
CONTROL

DA15

ADDRESS
SELECTION
INTERRUPT
DA <7:0>
VECTOR
GENERATION
DATA I/O
'NTERFACE I
DA <15:00>'
(DC005)

ERI
INHIBIT
SWITCH

IBS

115 ~13121IK;~ ~
~ IX
a: 0 Q §]U ~" .:.Jz
(/)
LU W
RRRRRRRR

16
REGISTER
MULTIPLEXER

...J/\
SELiECT
ISS

l?V

REM
EOP

I 765432101

TAKE
CONTROL
SYNC

I
I

(

I
I

BDIN L

ATN L

(f)

::>
CD

,f2:

::E

::>

a::
f-

NRFD L

(f)

, 2:
-

DAV

HANDSHAKE~
CONTROL
RFD

NDAC L

)

'115141312111098[765432101
t-tzuzoo>u
OJ ...... t D I O V t t > N 8!i ~ ~ ~ ~ C3 C5
~ 8 ~ S ~ S ~ ~
RRRRRRRR
WWWWWWWW

16 ,
;

LOAD IBD
LOW BYTE

INTR CTL

_IN!T

HANDSHAKE
INTERFACE

ISD

8
(DC003 )

EOI L

DAV L

BINIT L

iNSTRUMENT
BUS
CONTROL

~~~g~~S~

BIAKO L

REN L

WWWWWWWW

BIAKI L

~
NRFD

u
w

0:::'"

,I I

-f-rl

l~~_m

SRO

I I

READY
FLAGS

~ DETECTION
ERROR

~c:-!

ATN
DAV

r----

TKR

LSI-II BUS
INTERRUPT
INTERFACE

SRQ L

IFC L

CMD
LNR

INTR ••.
CTL

ENABLE

u
BIRO L

IFC
125f'os
ONE SHOT

(f)

CLK

SELECT
IBS

J
~

LOAD IBS
LOW BYTE

DA <7:0>

INSTRUMENT / - BUS
' - IB<16:1>
RECEIVERS"

(CLK)

COMMAND
AND
TALKER
OUTPUT
BUFFER

INSTRUMENT
BUS

~ DATA LINE

DIO <8:1> L

DRIVERS

11- 4897

Figure 5-1 IBVI1-A
Functional Block Diagram
5-3

All I/O transfers over the LSI-II bus are done according to a strict protocol. One bus protocol
integrated circuit (DC004) performs this function and the register address selection previously discussed. When an active ADDRESS MATCH signal is present on the leading edge of the BSYNC L
signal, the bus protocol integrated circuit is enabled to complete its register selection function.
BWTBT L, BDOUT L, and BDIN L bus signals are decoded in the integrated circuit, as appropriate,
to produce the LOAD IBS LOW BYTE, SELECT IBS, LOAD IBD LOW BYTE, and RECEIVE
internal control signals for the IBV II-A logic functions. The integrated circuit also asserts BRPLY L
as required d~lfing the I/O sequence to complete the programmed transfer. Refer to Appendix A for a
detailed description of the DC004 integrated circuit.
Interrupts are generated by one interrupt integrated circuit (DC003). Four vector addresses can be
generated by this LSI-II bus interrupt interface function. A 5-bit vector address switch allows the user
to select the lowest vector address for the IBVII-A module. The preferred lowest IBVII-A vector
address is 420. IBVII-A vector addresses can range from 0 to 774; however, they must not conflict with
other LSI-II bus device and reserved system vectors.
The error vector always has the lowest address; this is the actual address configured by the user. The
remaining three vector addresses are relative to the error vector address. For example, the preferred
vector address (420) selection produces the following vector addresses:
Address
000420
000424
000430
000434

IBVII-A Interrupt Vector
Error
Service request
Command and talker
Listener

These vector addresses allow the IBVII-A to generate interrupts that can most efficiently be serviced
by four separate service routines. Each vector address points to a pair of locations in system memory
containing the PC and PS words for the interrupt service routine. For example, an IBVII-A service
request interrupt request, when acknowledged by the processor, will be serviced by the 000424 vector
address as foHows:
System Memory Location
000424
000426

Contents
Service Routine PC word
(starting address)
Service Routine PS word

Interrupt and vector control logic on the IBVII-A module generates the INTR CTL signals that
initiate the interrupts. Inputs for this logic function include the interrupt enable (IE) IBS bit (stored in
the control buffer), command or talker (CMD or TKR) and listener (LNR) ready flags, error (ERR)
status from the error detection logic, and the device service request (instrument bus control signal).
Refer to Appendix A for a detailed description of the DCOO3 interrupt logic integrated circuit.
5.4 INSTRUMENT BUS CONTROL
The control buffer is an 8-bit register that functions as the low byte of the IBS register. Bits stored in
this register control generation of interrupts, instrument bus clear, and instrument bus control and
status logic. Setting the IBC bit actually triggers a one-shot producing a 125 IlS pulse that clears the
instrument bus. Take control sync and handshake control logic function together with instrument bus
control and handshake interface logic to communicate with instruments on the bus according to
instrument bus protocol. LSI-II output transactions with the low byte of the IBD register result in
data being stored in the 8-bit command and talker output buffer. Instrument bus line drivers gate this
byte onto the instrument bus when the IBVII-A is an active talker or when it is an active controller.

5-4

S.S INSTRUMENT BUS INTERFACE
The IBV ll-A interfaces with the instrument bus via four MC3441 integrated circuits. These integrated
circuits are bus transceivers, each containing four bus drivers, four bus receivers, and bus terminations
that comply with instrument bus specifications.

5-5

CHAPTER 6
MAINTENANCE

6.1 GENERAL
Maintenance for the IBVII-A involves executing a diagnostic program and, if required, repairing the
module. As a general rule, the user should first check that the IBV Il-A is properly installed as
described in Chapter 3. If the module appears to be properly installed (address and interrupt vector
switches are properly set, and no unoccupied device locations are located in the backplane between the
IBVII-A and the LSI-II processor module), confirm the operational status of the module by executing
the IBVi l-A's diagnostic program.
6.2 IBVII-A DIAGNOSTIC SOFTWARE
IBVII-A diagnostic software (MAINDEC-II-DVIBA) includes a diagnostic program tape and a program listing. Detailed operating instructions are included in the listing. In order to completely test the
IBV II-A option, a second "known good" IBV II-A module and BN II A instrument bus interface
cable are required. If those items are not available, the program will allow tests to be run on those
IBV II-A functions that do not require the second module.
Minimum hardware requirements for running diagnostics include the basic LSI-II system, including
4K read/write memory (minimum), a console terminal, the IBVII-A to be tested, and a paper tape
reader. A second IBVII-A (known functional) module and two BNIIA cables will allow full use of the
diagnostic program. Refer to the Microcomputer Handbook, Section I, Paragraph 9.3 for general
instructions for using paper tape diagnostics.
6.3 DIGITAL SERVICES
Maintenance services can be performed by the user or by DIGITAL, as desired. DIGITAL's services
are described in the Microcomputer Handbook, Section 5, Chapter 3.

6-1

APPENDIX A
IC DESCRIPTIONS

A.I DC003 INTERRUPT LOGIC
The interrupt chip is an IS-pin, 0.300-inch center, DIP device that provides the circuits to perform an
interrupt transaction in a computer system that uses a "pass-the-pulse" type arbitration scheme. The
device is used in peripheral interfaces and provides two interrupt channels labeled "A" and "B," with
the A section at a higher priority than the B section. Bus signals use high-impedance input circuits or
high-drive open collector outputs, which allow the device to directly attach to the computer systems
bus. Maximum current required from the Vee supply is 140 rnA.
Figure A-I is a simplified logic diagram of the DC003 IC. Figure A-2 shows the timing for the "A"
interrupt section, while Figure A-3 shows the timing for both "A" and "B" interrupt sections. Table
A-I describes the signals and pins of the DC003 by pin and signal name.
A.2 DCOO4 PROTOCOL LOGIC
The protocol chip is a 20-pin, 0.300-inch center, DIP device that functions as a register selector,
providing the signals necessary to control data flow into and out of up to four word registers (S bytes).
Bus signals can directly attach to the device because receivers and drivers are provided on the chip. An
RC delay circuit is provided to slow the response of the peripheral interface to data transfer requests.
The circuit is designed such that if tight tolerance is not required, then only an externallK ±20 percent
resistor is necessary. External RCs can be added to vary the delay. Maximum current required from
the Vee supply is 120 rnA.
Figure A-4 is a simplified logic diagram of the DCOO4 IC. Signal timing with respect to different loads
is shown in Table A-2 and in Figure A-5. Figure A-6 shows the loading for the test conditions in Table
A-2. Signal and pin definitions for the DC004 are presented in Table A-3.
A.3 DCOO5 TRANSCEIVER LOGIC
The 4-bit transceiver is a 20-pin, 0.300-inch center, DIP, low-power Schottky device; its primary use is
in peripheral device interfaces, functioning as a bidirectional buffer between a data bus and peripheral
device logic. In addition to the isolation function, the device also provides a comparison circuit for
address selection and a constant generator, useful for interrupt vector addresses. The bus I/O port
provides high-impedance inputs and high-drive (70 rnA) open collector outputs to allow direct connection to a computer's data bus structure. On the peripheral device side, a bidirectional port is also
provided, with standard TTL inputs and 20 rnA 3-state drivers. Data on this port is the logical
inversion of the data on the bus side.
Three address jumper inputs are used to compare against three bus inputs and to generate the signal
MATCH. The MATCH output is open collector, which allows the output of several transceivers to be
wire-ANDded to form a composite address match signal. The address jumpers can also be put into a
third logical state that disconnects that jumper from the address match, allowing for "don't care"
address bits. In addition to the three address jumper inputs, a fourth high-impedance input line is used
to enable/disable the MATCH output.
A-I

Three vector jumper inputs are used to generate a constant that can be passed to the computer bus.
The three inputs directly drive three of the bus lines, overriding the action of the control lines.
Two control signals are decoded to give three operational states: receive data, transmit data, and
disable.
Maximum current required from the Vee supply is 100 rnA.
Figure A-7 is a simplified logic diagram of the De005 Ie. Timing for the various functions is shown in
Figure A-8. Signal and pin definitions for the De005 are presented in Table A-4.

A-2

+VCC-@
+VCC

~------------------------------------------------------------------------------------------1'6ENAST

ROSTA H
ENAOATA H

ENACLK H

14~----i>C

VECTOR H
VECROSTB H
BOIN L
INITO L
BINH L
BlAKO L
BlAKI L
BIRO L
GND

CLR

BIAKI L

vec
ROSTA H
ENAST H
ENADATA ii
ENACLK H
ENBCLK H
ENBDATA H
ENBST H
RQSTB H

o71------+------<11
lO-----t----------i--------iI06l BlAKO L

»---I----------+---------;--------i091 BIRO L

BOIN L

ENBOATA H 12

ENBCLK H 13,t-----i>C
0
CLR

~--~--~----~O

+VCC
ROSTS H

10~------+-----~----~

~GNO

L---~----~C

L-______________________L-________________________-L______

CLR
~

____________

lK
~

__________________

INITOL
Ie - 0173

Figure A-I DC003
Simplified Logic Diagram

A-3

~5?5? 1

BINIT l

INITO L

300 :
~MINI
I
I
I
I

7~5 ~~I----------------------------------------------------------------------

--+I

I
I
I

I
ENA DATA H
I

I
I

ENA ClK H

MIN~ ~~I
I

ENA ST H

7-30~

____________________________

~r--l~

___________________________

RQSTA H

BIRQ L

15-65~
I

____

~r- --.l---i:--IF 20 - 90

BDIN l

BIAKI l

35 MIN---l
I
I
I

VECTOR H

10-45-':

I
MIN~

I
I
I

I
I

F-+l b

10 - 45

12-55~

BIAKO l

W=12-55

NOTE:
Times are in nanoseconds
11-4150

Figure A-2

DCOO3 "A" Interrupt Section Timing Diagram

A-5

13001300:

BIN IT l

~MIN,
,

~ ,
7-35

INITO l

,;,-------------------------------------------------------

12-50

ENB DATA H
I

ENB elK H

30 MIN

--.J Fl
,

I
I

ENB ST H

7-30-:

BIRQ l

~-----------------------------------------------------------

15- 65--+l

,I ~-------------------------------------------------------

RQSTB

ENA DATA H
I

,I
30 MIN~

ENA elK H

~~I______________________________________________

ENA ST H

RQSTA H

B DIN l

___________________________________I

I
1

BIAKI l

35 MIN

--! l::J
I
I

35 MIN

-+l t--

!-I--~
I

I
I

Lr-b
L_r---b
n 10__- 4_5__________1_0_-4_5_!1i--1
:,10-45
I"

v ECTOR H ________________________________1_0_-_4_5.!.!I...J

...

~--------

;r+---,
:---,15-65

__
VECRQSTB H _________________________________________________________1_5_-_6_5~~
NOTE:
Times are in nanoseconds

11-4151

Figure A-3

De003 "A" and "B" Interrupt Sections Timing Diagrams

A-6

Table A-I
Pin

DC003 Pin/Signal Descriptions
Description

Signal
VECTOR H

INTERRUPT VECTOR GATING SIGNAL. Tkis signal should
be used to gate the appropriate vector address onto the bus
and to form the bus signal called BRPL Y L.

VEC RQSTB H

VECTOR REQUEST "B" SIGNAL. When asserted indicates
RQST "B" service vector address is required. When unasserted
indicates RQST "A" service vector address is required.
VECTOR H is the gating signal for the entire vector address:
VEe RQST B H is normally bit 2 of the vector address.

BDIN L

BUS DATA IN. This signal generated by the processor BDIN
always preceeds a BIAK signal.

INITO L

INITIALIZE OUT signal. This is the buffered BINIT L signal
used in the device interface for general initialization.

BINIT L

BUS INITIALIZE signal. When asserted, this signal brings all
driven lines to their unasserted state (except INITO L).

BIAKO L

BUS INTERRUPT ACKNOWLEDGE signal (OUT). This
signal is the daisy-chained signal that is passed by all devices
not requesting interrupt service (see BIAKI L). Once passed
by a device, it must remain passed until a new BIAKI L is
generated.

BIAKI L

BUS INTERRUPT ACKNOWLEDGE signal (IN). This signal
is the processor's response to BIRQ L true. This signal is
daisy-chained such that the first requesting device blocks the
signal propagation while non-requesting devices pass the
signal on as BIAKO L to the next device in the chain. The
leading edge of BIAKI L causes BI RQ L to be unasserted by
the requesting device.

BIRQ L

ASYNCHRONOUS BUS INTERRUPT REQUEST from a
device needing interrupt service. The request is generated by
a true RQST signal along with the associated true interrupt
enable signal. The request is removed after the acceptance of
the BDIN L signal and on the leading edge of the BIAKI L
signal or the removal of the associated interrupt enable or due
to the removal of the associated request signal.

REQSTB H

REQSTA H

DEVICE INTERRUPT REQUEST SIGNAL. When asserted
with the enable "A" flip-flop asserted will cause the assertion
of BIRQ L on the bus. This signal line normally remains
asserted until the request is serviced.

A-7

Table A-I
Pin

Signal

ENB STH

ENA STH

ENB DATA H

ENA DATA H

ENB ClKH

ENA ClK H

DC003 Pin/Signal Descriptions (Cont)
Description
INTERRUPT ENABLE "A" STATUS signal. This signal indicates the state of the interrupt enable "A" internal flip-flop
which is controlled by the signal line ENA DATA H and the
ENA CLK H clock line.
INTERRUPT ENABLE "A" DATA signal. The level on this
line, in conjunction with the ENA CLK H signal, determines
the state of the internal interrupt enable "A" flip-flop. The
output of this flip-flop is monitored by the ENA ST H signal.
INTERRUPT ENABLE "A" CLOCK. When asserted (on the
positive edge), interrupt enable "A" flip-flop assumes the
state of the ENA DATA H signal line.

A-8

VECTOR H
BDAL2 L
BOALI L
BDALO L
BWTBT L
BSYNC L
BOIN L
BRPLY L
BOOUT L
GND

ENB H
BSYNC L
BDAL2 L

:
L-.I

~+Vcc

vce
ENB H
RxeXH
SELS L
SEL4 L
SEL2 L
SELO L

OUTHB L
OUTLB L
INWD L

~
U

~ VCC

IT§-- GND

2
DAL 2

10-----117

SEL 6 L

DECODER
SEL 4 L

BDALI L

03,1-------+--t

SEL 2 L

DAL 1

SEL 0 L

BDALO L
OUTHB L
OUTLB L

RXCX H

BRPLV L

BOOUT L

VECTOR H

BOIN L

INWO L
IC-0174

Figure A-4 DCOO4
Simplified Logic Diagram
A-9

Table A-2 DC004 Signal Timing vs Output Loading

Signal

With
Respect
to

Signal

Output
Being
Asserted

Test
Condo

Output
Being
Asserted
Min

Max

Min

OUTLB L

OUTHB L

BDOUT L

DBOUT L

Max
(ns)

(ns)
SEL (0,2,4,6) L BSYNC L

Fig. A-5
Ref.

Load B

LoadC

Load B

LoadC

Load B

Load C

I
I
I
I
I

t5' t6

t9' t 10

t9, t 10

INWD L

BDIN L ~

Pin 18
Connection
RX = lK ±5%
350n ±5%
15 pf±5%

BRPLY L
(Load A)

OUTLB L
(Load B)

BRPLY L

OUTHB L

(Load A)

(Load B)

BRPLY L

INWD L

(Load A)

(Load B)

BRPLY L

Load A

Load B

-10

I
I

tl1,tl2

t13, t14

-10

t13' t14

VECTORH

t13' t14

Pin 18
BRPLY L
I
Connection
I
(Load A)
RX = 4.64 K ± 1% i
BRPLY L

OUTLB L
(Load B)

300

400

-10

t13' t14

OUTHB L

300

400

-10

t13' t14

I (Load A)

(Load B)

t 13 , t14

(Load A)

A-II

Table A-2 DC0004 Signal Timing vs Output Loading (Cont)

Signal

With
Respect
to

Signal

Output
Being
Asserted

Test
Condo

Max

Min

BRPLY L

INWDL

(Load A)

(Load B)

BRPLY L

VECTORH

Max

Min
(ns)

(ns)
CX = 220 pf ± 1%

Fig. A-5
Ref.

300

400

-10

t13' t14

330

430

t13' t14

(Load A)

A-13

BOAl (2.1.0) l

~25 MIN\25 MIN

BSYNC l

SEl (0.2.4.6) l

SWSTL~
1
I
1

BOOUT l

15 MIN.-.l
I

I
I

~r:-______ M_'_N._=j~r:4_~~~~~~~~~~--*------~\_I-'---- tl________
'5
__

OUTHS L --------------------~Ii_..,
OUTLS L
-:T9!=-

-+!T10F

=iTll~

BDIN L

~TI2F

I
I

1
1

-+lI T13 \:-:

I
I

i
I

---4

Rx C x H

11~t-= 2.4V
I

I-

VECTOR H

·1

I
I

BRPLY L

~ (I

I-

1
1

IWD L

••

T15

I
I

-I

* r(
'

~ T16\:-:

* TIME REQUIRED TO DISCHARGE Rx Cx FROM ANY CONDITION ASSERTED: 150ns
NOTE:
Times are in nanoseconds
11-4348

Figure A-5

+
T

Vee

FROM
OUTPUT

DC004 Timing Diagram

200pF

LOAD A

280..0.

OU~~~~ )

FROM
OUTPUT

15pF

1
LOAD B

t50pF

rom

DIODE-

1
LOAD C
11-4349

Figure A-6

DCOO4 Loading Configurations for Table A-2

A-I5

Table A-3 DC004 Pin/Signal Descriptions
Pin

Description

Signal
VECTORH

VECTOR. This input causes BRPLY L to be generated through
the delay circuit. Independent of BSYNC Land ENB H.

BDAL2 L

BUS DATA ADDRESS LINES. These signals are latched at the
assert edge of BSYNC L. Lines 2 and 1 are decoded for the
select outputs; line 0 is used for byte selection.

BDALIL

BDALO L

BWTBTL

BUS WRITE/BYTE. While the BDOUT L input is asserted,
this signal indicates a byte or word operation: Asserted = byte.
unasserted = word. Decoded with BOUT L and latched
BDALO L to form OUTLB Land OUTHB L.

BSYNC L

BUS SYNCHRONIZE. At the assert edge of this signal, address
information is trapped in four latches. While unasserted,
disables all outputs except the vector term of BRPL Y L.

BDIN L

BUS DATA IN. This is a strobing signal to effect a data input
transaction. Generates BRPL Y L through the delay circuit and
INWD L.

BRPLY L

BUS REPLY. This signal is generated through an RC delay by
VECTOR H, and strobed by BDIN L or BDOUT L, and
BSYNC L and latched ENB H.

BDOUT L

BUS DATA OUT. This is a strobing signal to effect a data
output transaction. Decoded with BWTBT Land BDALO to
form OUTLB Land OUTHB L. Generates BRPLY L through
the delay circuit.

INWDL

IN WORD. Used to gate (read) data from a selected register on
to the data bus. Enabled by BSYNC L and strobed by
BDIN L.

OUTHB L

OUTLB L

OUT LOW BYTE, OUT HIGH BYTE. Used to load (write)
data into the lower, higher, or both bytes of a selected
register. Enabled by BSYNC L and decode of BWTBT Land
latched BDALO L, and strobed by BDOUT L.

SELO L

SEL2 L

SEL4 L

SEL6 L

SELECT LINES. One of these four signals is true as a function
of BDAL2 Land BDAL I L if ENB H is asserted at the assert
edge of BSYNC L. They indicate that a word register has been
selected for a data transaction. These signals never become
asserted except at the assertion of BSYNC L (then only if
ENB H is asserted at that time) and once asserted, are not
unasserted until BSYNC L becomes unasserted.

A-16

Table A-3 DCOO4 Pin/Signal Descriptions (Cont)
Pin

Description

Signal

RXCX

EXTERNAL RESISTOR CAPACITOR NODE. This node is
provided to vary the delay between the BDIN L, BDOUT L,
and VECTOR H inputs and BRPL Y L output. The external
resistor should be tied to VCC and the capacitor to ground.
As an output, it is the logical inversion of BRPL Y L.

ENBH

ENABLE. This signal is latched at the asserted edge of
BSYNC L and is used to enable the select outputs and the
address term of BRPL Y L.

A-I7

JAI L
JA2 L
MATCH H
REC H
XMIT H
DAB H
DAT2 H
BUS3 L
BUS2 L
GND

J A2 L

§Ir---,.-----L------l

VCC
JA3 L
DATO H
DATI H
JV3 H
JV2 H
JVl H
MENB L
BUSO L
BUSI L

:>-_ _ _--'i

I
i Ir-<]~------~i~,
--~~
I

~-------+1--.---10 JV3 H
i

JA3 L
~-~------------_+--_;03

§]-VCC

§-GND

Figure A-7

MATCH H

Ie-Deoos

DeOOS Simplified Logic Diagram

A-I8

TRANSMIT DATA TO

BUS

XMIT H

BUS L - OUTPUT

H _ 1NPUT

------r------:..,__

TO 30ns

I- -l

5 TO 25nS-l

DAT

f.- 5

I+- 5 TO :30 ns

REC H (GROUND)

1-5 TO 25ns

----'I~--'-----.----

RECEIVE DATA FROM BUS (BUS INITIALLY

HIGH)

XMIT H (GROUND)

REC H

-----,r--l

DAT H - OUTPUT

0 TO 30ns

f.- 0 TO 30ns

~I----------~--~

-.j

BUS L -I NPUT

-l

8 TO 30ns

-----....-------;IL...-__________-'-___
RECEIVE DATA FROM BUS (BUS INITIALLY LOW)

XMIT

H (GROUND)

REC H

DAT H - OUTPUT

I+- 0 TO 30ns

If.-

-l

-j

1+-0 TO 30n5

8 TO 30n5

8USL-INPUT

VECTOR TRANSFER TO BUS
JV H

~
BUS L - OUTPUT

I+- 20 ns MAX

20n5 MAX

ADDRESS DECODING

BUS L - INPUT

MATCH H

-.j
MENB L

-l

f.- 5 TO 40n5

10 TO 40ns

-.j

I
RECEIVE MODE LOG IC DELAY

XMIT H

REC H

I- 40 TO 90n5
DAT (3:0) H (OUTPUT)

Figure A-8

De005 Timing Diagram

A-19

I
1+-10 TO 40ns

Table A-4
Pin

DC005 Pin/Signal Descriptions

Name

Function

BUS<3:0> L
BUSO
BUSI
BUS2
BUS3

BUS DATA. This set of four lines constitutes the bus side of the
transceiver. Open collector outputs; high-impedance inputs. LOVI :=
1.

DAT<3:0> H
DATO
DATI
DAT2
DAT3

PERIPHERAL DEVICE DATA. These four 3-state lines carry the
inverted received data from BUS <3:0> when the transceiver is in
the receive mode. When in transmit data mode, the data carried on
these lines is passed inverted to BUS ~ 3:0>. When in the disabled
mode, these lines go open (hi-Z). HIGH = 1.

14
15
16

JV<3:1> H
JVl
JV2
JV3

VECTOR JUMPERS. These inputs, with internal pull-down resistors, directly drive BUS <3: 1>. A low or open on the jumper pin will
cause an open condition on the corresponding bus pin if XMIT H is
low. A high will cause a one (low) to be transmitted on the bus pin.
Note that BUSO L is not controlled by any jumper input.

MENBL

MATCH ENABLE. A low on this line will enable the MATCH output. A high will force MATCH low, overriding the match circuit.

MATCHH

ADDRESS MATCH. When BUS <3: 1> match with the state of JA
< 3: 1> and MENB L is low, this output is open; otherwise it is low.

JA<3:1>L
JAI L
JA2L
JA3 L

ADDRESS JUMPERS. A strap to ground on these inputs will allow
a match to occur with a one (low) on the corresponding BUS line; an
open will allow a match with a zero (high); a strap to Vcc will disconnect the corresponding address bit from the comparison.

XMITH

CONTROL INPUTS. These lines control the operation of the transceiver as follows:

RECH

12
11
9

17
7

REC

o
o
1
1

XMIT

o
1

DISABLE:
XMITDATA:
RECEIVE:
RECEIVE:

BUSDATopen
DATBUS
BUSDAT
BUSDAT

To avoid 3-state signal overlap conditions, an internal circuit delays
the change of modes between XMIT DATA and RECEIVE mode
and delays 3-state drivers on the DAT lines from enabling. This
action is independent of the DISABLE mode.

A-20

Reader's Comments
IBVII-A LSI-II iINSTRUMENT BUS
INTERFACE USER'S MANUAL
EK-IBVII-UG-OOI
Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of

our publications.

What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well
written, etc.? Is it easy to use?

What features are most useful?

-----------------------------------------------------------

What faults do you find with the manual?

Does this manual satisfy the need you think it was intended to satisfy?
Does it satisfy your needs? _ _ _ _ _ _ _ _ _ __ Why? _______________________________________

Would you please indicate any factual errors you have found.

Please describe your position.
Name _____________________ Organization
Street
City _ _ _ _ _ _ _ _ __

State ___________________

Zip or Country

-- -

FoldHere -

DoNotTear-FoldHereandStaple

FIRST CLASS
PERMIT NO. 33
MAYNARD, MASS.
BUSINESS REPLY MAIL
NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be paid by:

Digital Equipment Corporation
Technical Documentation Department
Maynard, Massachusetts 01754