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EK-DZV11-TM-001

June 1978

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Document:	DZV11 Asynchronous Multiplexer Technical Manual
Order Number:	EK-DZV11-TM
Revision:	001
Pages:	137
Original Filename:	http://bitsavers.org/pdf/dec/qbus/EK-DZV11-TM-001_DZV11_Asynchronous_Multiplexer_Technical_Manual_Jun78.pdf

OCR Text

EK-OZV11-TM-OO1

DZV11 asynchronous
multiplexer
technical manual

digital equipment corporation • maynard, massachusetts

1st Edition. June 1978

Copyright © 1978 by Digital Equipment Corporation
The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL's DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC
PDP
DEC US
UNIBUS

D ECsystem-lO
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
lAS

CONTENTS
Page
CHAPTER 1

GENERAL DESCRIPTION

l.l
1.2
1.2.1
1.2.2
1.2.3
1.3
1.3.1
1.3.2
1.3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.3.3.4
1.3.3.5
1.3.3.6
1.3.4

INTRODUCTION .............................................................................................. 1-1
PHYSICAL DESCRIPTION .............................................................................. 1-1
DZVII Configurations ................................................................................. 1-1
BC II U Interface Cable ................................................................................. 1-4
Test Connectors ........................................................................................... 1-5
SPECIFICATIONS ............................................................................................. 1-5
Environmental ............................................................................................. 1-5
Electrical ...................................................................................................... 1-5
Performance ................................................................................................. 1-5
Maximum Configurations .................................................................... 1-5
Throughput .......................................................................................... 1-7
Receivers .............................................................................................. 1-7
Transmitters ................................. '" ..................................................... 1-7
Baud Rate Generator ........................................................................... 1-7
Performance Summary ......................................................................... 1-7
Interrupts ..................................................................................................... 1-7

CHAPTER 2

INSTALLATION

2.1
2.2
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.2

SCOPE ................................................................................................................ 2-1
UNPACKING AND INSPECTION ................................................................... 2-1
INSTALLATION PROCEDURE ....................................................................... 2-1
Jumper Configuration .................................................................................. 2-1
Device Operation ................................................................................. 2-1
Modem Control Jumpers ...................................................................... 2-3
Module Installation ...................................................................................... 2-3

CHAPTER 3

DEVICE REGISTERS

3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6

SCOPE ................................................................................................................ 3-1
DEVICE REGISTERS ........................................................................................ 3-1
Control and Status Register .......................................................................... :3-1
Receiver Buffer ............................................................................................. 3-1
Line Parameters Register .............................................................................. 3-5
Transmitter Control Register ........................................................................ 3-5
Modem Status Register ................................................................................ 3-7
Transmit Data Register ................................................................................ 3-8

IJI

CONTENTS (Cont)
Page
CHAPTER 4

PROGRAMMING

4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8

SCOPE ................................................................................................................ 4-1
DEVICE ADDRESS ASSIGNMENTS .............................................................. .4-1
INTERRUPT VECTOR ADDRESS ASSIGNMENTS ..................................... .4-1
PROGRAMMING FEATURES ....................................................................... .4-2
Baud Rate .................................................................................................... 4-2
Character Length ......................................................................................... 4-2
Stop Bits ....................................................................................................... 4-3
Parity ........................................................................................................... 4-3
Interrupts ..................................................................................................... 4-3
Emptying the Silo ......................................................................................... 4-4
Transmitting a Character .............................................................................. 4-4
Data Set Control .......................................................................................... 4-5

CHAPTER 5

TECHNICAL DESCRIPTION

5.1
5.2
5.2.1
5.2.2
5.3
5.4
5.4.1
5.4.2
5.4.2.1
5.4.2.2
5.4.2.3
5.4.2.4
5.4.3
5.4.3.1
5.4.4
5.4.5
5.4.6
5.4.6.1
5.4.6.2
5.4.6.3
5.4.7
5.4.8
5.4.9
5.4.9.1
5.4.9.2
5.4.10
5.4.11
5.4.12
5.5

GENERAL .......................................................................................................... 5-1
INTERFACE FUNCTIONS ............................................................................... 5-1
LSI-II to DZII Interface .............................................................................. 5-1
DZVII to Data Set Interface ........................................................................ 5-8
CIRCUIT FUNCTIONS ................................................................................... 5-11
CIRCUIT OPERATION ................................................................................... 5-13
Bus Interface .............................................................................................. 5-13
I/O Control ................................................................................................ 5-15
Input Operation .................................................................................. 5-16
Output Operation ............................................................................... 5-17
Vector Operation ................................................................................ 5-18
Initialize Circuit. ................................................................................. 5-18
Interrupt Logic ........................................................................................... 5-19
Interrupt Transactions ........................................................................ 5-19
EIA Receivers ............................................................................................. 5-21
EIA Transmitters ........................................................................................ 5-22
UARTs ...................................................................................................... 5-22
Setting Line Parameters ...................................................................... 5-22
U ART Receiver Operation ................................................................ .5-23
UART Transmitter Operation ............................................................ 5-24
Break (BRK) Bits ....................................................................................... 5-25
Speed and Format Control ......................................................................... 5-25
Receiver Control ........................................................................................ 5-27
Receiver Scanner ................................................................................ 5-27
Silo Buffer .......................................................................................... 5-28
Transmitter Control ................................................................................... 5-30
Maintenance Mode ..................................................................................... 5-33
Power Supplies ........................................................................................... 5-33
SUMMARY OF DEVICE REGISTERS .......................................................... .5-33
iv

CONTENTS (Coot)
Page
CHAPTER 6

MAINTENANCE

6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.4.1
6.3.4.2
6.3.4.3
6.3.4.4
6.3.4.5
6.3.4.6
6.3.4.7
6.3.5
6.3.5.1
6.3.5.2
6.3.5.3
6.3.5.4
6.3.6

SCOPE ................................................................................................................ 6-1
PREVENTIVE MAINTENANCE ...................................................................... 6-1
CORRECTIVE MAINTENANCE ..................................................................... 6-1
General ........................................................................................................ 6-1
Tools, Test Equipment, and Troubleshooting Aids ....................................... 6-1
DEC/XII Exerciser Program ....................................................................... 6-2
XXDP Diagnostic Programs ........................................................................ 6-2
General ................................................................................................ 6-2
Maintenance Modes ............................................................................. 6-3
Setup Procedures .................................................................................. 6-3
Software Switch Register ...................................................................... 6-3
Auto-Sizing ........................................................................................... 6-5
Parameter Inputs and Dialogue ............................................................ 6-5
Functional Description ......................................................................... 6-8
Interprocessor Test (ITEP) ......................................................................... 6-11
Starting ITEP ..................................................................................... 6-12
Console Dialogue ............................................................................... 6-12
Operational Switch Settings ................................................................ 6-14
Testing ...............................................................................................6-15
Manual Tests .............................................................................................. 6-15

APPENDIX A

IC DESCRIPTIONS

A.I
A.2
A.3
A.4
A.5
A.6
A.7

GENERAL ......................................................................................................... A-I
UART ................................................................................................................ A-l
DCOO3 INTERRUPT CHIP ............................................................................... A-8
DCOO4 PROTOCOL CHIP ............................................................................... A-12
DCOO5 BUS TRANSCEIVER CHIP ................................................................ A-17
COM 5016 DUAL BAUD RATE GENERATOR ............................................ A-22
3341 FIFO SERIAL MEMORY ....................................................................... A-22

APPENDIX B

CONNECTOR PINNING

APPENDIX C

GLOSSARY

FIGURES
Figure No.
1-1

1-2

Title

Page

DZVII-A (M7957 Module) .................................................................................. 1-2
DZVII System Applications ................................................................................ 1-3
v

FIGURES (Coot)

Figure No.
1-3
1-4
1-5
2-1
2-2
2-3
3-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
6-1
6-2

Title

Page

DZVII-B (M7957 Module, H325 and H329 Connectors and
Cable Assembly BCII U-25) ................................................................................. 1-4
Test Connectors H325 and H329 .......................................................................... 1-5
Loopback Connections ........................................................................................ 1-6
M7957 Jumper Locations ..................................................................................... 2-2
M7957 Address Selection ..................................................................................... 2-4
M7957 Vector Selection ........................................................................................ 2-4
Register Bit Assignments ...................................................................................... 3-2
Labeling Conventions .......................................................................................... 5-1
LSI-II/DZVII Interface ...................................................................................... 5-2
Interrupt Request/Acknowledge Sequence ........................................................... 5-4
DATI Bus Cycle ................................................................................................... 5-5
DATO or DATOB Bus Cycle ............................................................................... 5-6
DATIO orDATIOB Bus Cycle ............................................................................ 5-7
Channel Established by Local Modem .................................................................. 5-9
Channel Established by Remote Modem ............................................................ 5-10
Interface with Bell Data Station .......................................................................... 5-11
Simplified Functional Block Diagram ................................................................. 5-12
Bus Interface, I/O Control and Interrupt Logic .................................................. 5-14
Data Input Timing ............................................................................................. 5-16
Data Output Timing ........................................................................................... 5-17
Initialization Signals ........................................................................................... 5-18
Interrupt Logic ................................................................................................... 5-20
Interrupt Timing ................................................................................................ 5-21
EIA Receivers .................................................................................................... 5-21
EIA Transmitters ............................................................................................... 5-22
UARTs .............................................................................................................. 5-23
UART and Break Bit Registers ........................................................................... 5-24
Speed and Format Control ................................................................................. 5-26
Receiver Control ................................................................................................ 5-27
Silo Buffer .......................................................................................................... 5-29
Transmitter Control ........................................................................................... 5-31
Transmitter Timing ............................................................................................ 5-32
Maintenance Mode ............................................................................................ 5-34
Power Supplies ................................................................................................... 5-35
Bit Labeling Scheme ........................................................................................... 5-35
Control and Status Register ................................................................................ 5-36
Receiver Buffer Register ..................................................................................... 5-37
Line Parameter Register ..................................................................................... 5-38
Transmit Control Register .................................................................................. 5-39
Modem Status Register ...................................................................................... 5-40
Transmit Data Register ...................................................................................... 5-41
Maintenance Mode Data Flow ............................................................................. 6-4
Interprocessor Test (ITEP) ................................................................................... 6-5

FIGURES (Coot)
Figure No.
A-I
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-1O
A-II
A-12
A-13
A-14
A-15
B-1

Title

Page

Format of Typical Serial Character ..................................................................... A-I
UART Transmitter ............................................................................................. A-2
UART Receiver .................................................................................................. A-6
UART Chip Pin Designations ............................................................................. A-7
DCOO3 Logic Symbol .......................................................................................... A-8
DCOO3 A Section Timing ..................................................................................... A-9
DCOO3 A and B Section Timing ......................................................................... A-IO
DCOO4 Simplified Logic Diagram ...................................................................... A-13
DCOO4 Timing Diagram .................................................................................... A-15
DCOO4 Loading Configuration .......................................................................... A -16
DCOO5 Simplified Logic Diagram ...................................................................... A-20
DCOO5 Timing Diagram .................................................................................... A-21
COM 5016 Simplified Block Diagram ................................................................ A-22
COM 5016 Pin Locations .................................................................................. A-23
3341 FIFO Serial Memory ................................................................................. A-25
Connectors .......................................................................................................... B-I

TABLES
Table No.
2-1
2-2
2-3
2-4
3-1
3-2
3-3
3-4
4-1
5-1
5-2
5-3
5-4
5-5
6-1
6-2
6-3
6-4

6-5

Title

Page

Items Supplied per Configuration ......................................................................... 2-1
Jumper Configuration .......................................................................................... 2-3
M7957 Vector Address Switch Selection ............................................................... 2-4
Vector Switch Selection ........................................................................................ 2-5
DZVII Register Address Assignments ................................................................. 3-1
CSR Bit Assignments ........................................................................................... 3-3
RBUF Bit Assignments ........................................................................................ 3-5
LPR Bit Assignments ........................................................................................... 3-6
Baud Rate Selection Chart ................................................................................... 4-2
LSI-II/DZVII Interface Signals .......................................................................... 5-2
Modem Control Signals ....................................................................................... 5-8
Multiplexer Addressing ...................................................................................... 5-15
Transceiver Switching ......................................................................................... 5-15
Byte Selection (Output Operations Only) ............................................................ 5-18
Diagnostic Programs ............................................................................................ 6-2
Multimedia Assignments ...................................................................................... 6-3
Typical Map ofDZVll Status .............................................................................. 6-6
DVDZA Tests ...................................................................................................... 6-8
DVDZB Tests .................................................................................................... 6-10

vii

TABLES (Coot)
Table No.
6-6
6-7
6-S
6-9
A-I
A-2
A-3
A-4
A-5
A-6
A-7
B-1
B-2

Title

Page

Valid Mode Combinations ................................................................................. 6-12
Meaning of Parameter No. 1............................................................................... 6-13
Parameter No.1 Examples ................................................................................. 6-13
Operational Switch Settings ................................................................................ 6-14
UART Signal Functions ...................................................................................... A-3
DCOO3 Signals ................................................................................................... A-Il
DCOO4 Signal Timing versus Output Loading .................................................... A-14
DCOO4 Pin/Signal Descriptions ......................................................................... A-16
DCOO5 Pin/Signal Descriptions ......................................................................... A-IS
COM 5016 Selectable Frequencies ..................................................................... A-23
COM 5016 Pin Functions .................................................................................. A-24
Connector Pinning ............................................................................................... B-2
DZVll Edge Connector Pinning .......................................................................... B-4

viii

CHAPTER 1
GENERAL DESCRIPTION

1.1 INTRODUCTION
The DZVll, shown in Figure 1-1, is an asynchronous multiplexer that provides an interface between
an LSI-II processor and four asynchronous serial data communication channels. It can be used with
the LSI-II processor in a variety of applications that include data concentration, real-time processing,
and cluster controlling. The DZVll provides an EIA RS232C interface and enough data set control to
permit dial-up (auto-answer) operation with modems capable of full-duplex operation, * such as the
Bell models 103, 113,212, or equivalent. Remote operation over private lines for full-duplex point-topoint or full-duplex multipoint as a control (master) station is also possible. Figure 1-2 depicts several
of the possible applications for the DZVll in an LSI-ll system.
The DZVll has several features that provide flexible control of parameters such as baud rate, character length, number of stop bits for each line, odd or even parity for each line, and transmitter-receiver
interrupts. Additional features include limited data set control, zero receiver baud rate, break generation and detection, silo buffering of received data, and line turnaround.
Program compatibility is maintained with the Unibus option DZII-A. The only compatibility exception is the number of serial channels supported. The DZV 11 does not support 20 rnA operation.

1.2 PHYSICAL DESCRIPTION
The DZVll comprises a single quad size module, 21.6 X 26.5 cm (8.51 X 10.44 inches), which is
designated as the M7957 module. All input and output leads are available on a Berg header. The
DZVII connects to the LSI-II QBus by the H9270 mounting panel or equivalent. All QBus input/output signals enter and leave the module via the mounting panel pins.
1.2.1 DZVll Configurations
The DZVll can be supplied in two configurations. The DZVII-A, as shown in Figure 1-1, consists of
the M7957 module only. Cabling assemblies for connection to terminals and modem channels are not
supplied with the DZVll-A, but are available in the DZVll-B. The DZVll-B consists of an M7957
module, BCll U-25 cable assembly, and two accessory test connectors, H329 and H325. This configuration is shown in Figure 1-3.

*The DZVII data set control does not support half-duplex operations or the secondary transmit and receive
operations available with some modems s!lch as the Bell 202, etc.

1-1

'---~_----II?

L..--_ - - - J

f,----_---'I '---~

_----I

VECTOR SE lECT
SWITCH E2

ADDRESS SELECT
SWITCH E30

MK0181

Figure I-I

DZVII-A (M7957 Module)

LOCAL

REMOTE

I"--'

en
CD

~ /'"

DZV11

-- -

....

;:)

DATA
SET

TELEPHONE
LINE

--~I

DATA
- SET

REMOTE
TERMINAL

I
I

LOCAL
TERM.

DATA
SET

I
~

--~-I~
I
I
I
I
I

TELEPHONE
LINE

LSI·11
SYSTEM

I
Figure 1-2

--41.-

DATA . .
SET

DZVII System Applications

DZV11

en
;:)
III

LSI·"
SYSTEM

MA·0553

CABLE ASSEMBLY
BCllU-25

~~]
TEST CONNECTOR H325
MK·0179

TEST CONNECTOR H329

Figure 1-3 DZVII-B (M7957 Module, H325 and H329
Connectors and Cable Assembly BCll U-25)

1.2.2 BCll U Interface Cable
The interfacing cable for terminal and modem connections to the DZV11-B is provided by the BC11 U
cable assembly (Figure 1-3). It consists of four separate cables, 762 cm (25) in length, each terminated
by a separate EIA-type connector housing and a common Berg housing. Each cable within the assembly provides nine input/output leads. The EIA connector pinning conforms to EIA standard RS232C
and CCITT* recommendation V.24. The leads supported by the DZV11-B are:
Circuit AA (CCITT 101)
Circuit AB (CCITT 102)
Circuit BA (CCITT 103)
Circuit BB (CCITT 104)
Circuit CD (CCITT 108.2)
Circuit CE (CCITT 125)
Circuit CF (CCITT 109)

Pin 1
Pin 7
Pin 2
Pin 3
Pin 20
Pin 22
Pin 8

Protective Ground
Signal Ground
Transmitted Data
Received Data
Data Terminal Ready
Ring Indicator
Carrier

NOTE
Signal ground and protective ground are connected
together.

*CCITT - The Consultive Committee International Telegraph and Telephone is an advisory committee established under the United Nations to recommend worldwide standards.

1-4

1.2.3 Test Connectors
Figure 1-4 shows the two accessory test connectors, H329 and H325, that are provided with each
DZV11-B. The H325 plugs into an EIA connector on the BC11 U to loopback data and modem signals
onto a single line. The H329 plugs into the M7957 module socket housing and provides staggered
loopback of the data and modem lines. The loopback connections are shown in Figure 1-5.
1.3 SPECIFICA TIONS
Environmental, electrical, and performance specifications for the DZV II are discussed in the following paragraphs.
1.3.1 Environmental
The DZVl1 operates in an environment from 5° to 50° C (41 ° to 122° F) and in a relative humidity of
10 to 95 percent.
1.3.2 Electrical
Power Consumption

1.l5 A@ +5 Vdc
0.39A@ +12Vdc

For each line, the DZV11 provides a voltage level interface whose levels and connections conform to
EIA standard RS232C and CCITT recommendation V.24. The leads supported by the DZVll are
listed in Paragraph l.2.2. Each DZVll meets the LSI-ll QBus interface specification and represents
one unit load as an interface.
1.3.3 Performance
The following paragraphs describe the DZV11 performance capabilities and restrictions.
1.3.3.1 Maximum Configurations - The DZV11 multiplexer is assigned a device address in the floating address space. The floating address space starts at 760010 and extends to 764000. A maximum
configuration of DZV11s is not limited by floating address space, but is limited by the rules governing
an intermediate size system configuration. Therefore, a maximum of seven DZV11 multiplexers may
reside in a 9 X 4 backplane.

...... .... . .

((e ••••.• • _. • •• -))0

H329

H325

Figure 1-4 Test Connectors H325 and H329

1-5

MK-OIBO

H329 STAGGERED TURNAROUND
TRANSMIT 0 --~----~. RECEIVE 1
DTR 0 ----~--.: RING 1

'----+ CARRIER 1

RINGO :
CARRIER 0 ..f - - - L - - - - - - DTR 1
RECEIVE 0 .....I----~--- TRANSMIT 1
NOTE:

-------------LINE 2&3 ARE STAGGERED IN THE SAME WAY.

H325 LOOPBACK CONNECTIONS
SCE

SCT~
SCR~
11
SEC XMIT~

SECRCV~

XMITDATA~.
RCV DATA

2--J
4

REQTOSEND
ClR TO SEND
CARRIER

-----i1..
14

NEW SYNC

DATA SET RDY -=-6_ _ _l.-~~O JUMPER
DTR

RING~

--0 REMOVED

MA-0551

Figure 1-5

Loopback Connections

1-6

1.3.3.2 Throughput - Each DZVII is capable of a throughput rate of 10,970 characters per second.
This rate is calculated as follows:
(Bits/second X no. lines X direction) divided by bits/character.
(9600 X 4 X 2) 1/7 equals 10,970 characters/second.
For a character service routine of 100 J.LS or less, the device throughput rate can be sustained.
1.3.3.3 Receivers - The receivers provide serial- to-parallel conversion of 5-, 6-, 7-, or 8-level code
with one start space and at least one stop mark. The character length, number of stop bits, parity
generation, and operating speed are programmable parameters for each line. A receiver and transmitter of a corresponding line share the same operating speed with provisions for enabling/disabling
of that receive line.
Each receiver is double-buffered and has an allowable input distortion of 43.75 percent on any bit.
Also, the accumulated character distortion must not exceed 43.75 percent. Break detection is provided
on each receiver.
1.3.3.4 Transmitters - The transmitters provide parallel-to-serial conversion of 5-, 6-, 7- or, 8-level
code with or without parity. The parity sense, when selected, can be either odd or even. The stop code
can be either I or 2 units except when 5-level code is selected. When 5-level code is selected, the stop
code can be set to I or 1.5 units. The character length, number of stop units, parity generation and
sense, and operating speed are programmable parameters for each line. The operating speed for the
transmitter is common with the receiver. Breaks are capable of being transmitted on any line. The
gross start-stop distortion for a transmitter's TTL output is less than 2.5 percent for an 8-bit character.
1.3.3.5 Baud Rate Generator - The baud rate generator is a MaS/LSI device which provides the
DZV II multiplexer with full programmable capability for operating speed selection. Each line has an
independent generator capable of producing I of 15 selectable baud rates. Speed tolerance for all rates
is less 0.3 percent with a clock duty of 50 percent ± 5 percent. (See below for rates.)
1.3.3.6 Performance Summary - The following summarizes the programmable features offered for
each line.
Character length

5-, 6-, 7-, or 8-level code

Number of stop bits

I or 2 for 6-, 7-, or 8-level code
I or 1.5 for 5-level code

Parity

Odd, even or none

Baud rates

50,75, 110, 134.5, 150,300,600, 1200, 1800,2000,2400,3600,
4800, 7200, and 9600

Breaks

Can be generated and detected on each line.

1.3.4 Interrupts
The following interrupts are available on the DZV11.
Receiver Done Interrupt
The Receiver Done interrupt occurs every time a character appears at the output of the receiver buffer
register and the Silo Alarm is disabled. It can be enabled or disabled from the bus.

1-7

Silo Alarm Interrupt
The Silo Alarm interrupt occurs after 16 entries have been made into the receive buffer register by the
scanner. This interrupt disables the Receiver Done interrupt and is rearmed when the receive buffer
register has been read.
Transmit Interrupt
The Transmit interrupt occurs every time the scanner finds a UART buffer empty condition, and the
transmitter control register bit is set for that line. It can be enabled or disabled from the bus.

1-8

CHAPTER 2
INSTALLATION

2.1 SCOPE
This chapter contains the procedures for the unpacking, installation, and initial checkout of the
DZVll Asynchronous Multiplexer.
2.2 UNPACKING AND INSPECfION
The DZV 11 is packaged in accordance with commercial packaging practices. First, remove all packing
material and check the equipment against the shipping list. (Table 2-1 contains a list of supplied items
per configuration.) Report damage or shortages to the shipper immediately and notify the DIGITAL
representative. Inspect all parts and carefully inspect the module for cracks, loose components, and
separations in the etched paths.

Table 2-1

Items Supplied per Configuration

Quantity

Description

1
1
1
1
1

M7957 module
BC 11 U-25 cable assembly
H329 test connector
H325 test connector
Print set (B-TC-DZVII-0-l)
DZVII-A and-B
Order number MP00462
Software kit ZJ251-RB
DZVII User's Guide
(EK-DZVII-UG)

X
X
X
X
X

X
X

1
1

2.3 INST ALLA TION PROCEDURE
The following paragraphs describe the installation of the DZVll option in an LSI-II system.
2.3.1 Jumper Configuration
There are 16 machine-insertable jumpers on the M7957 module (Figure 2-1).
2.3.1.1 Device Operation - Jumpers WlO and Wll must be installed only when the module is used on
an H9270 backplane, or one that applies LSI-II bus signals to the C and D sections of the module.

2-1

IL...--.------Il
a:::

-""'8

W6
W7

'------~_1 ~~_~

~~_I?
Wl~

~::

W12*

~W9*

c::::::J

T;T,

W13*

W14* W15* W16*

A12

lOuuuu~uuool
Wl0*

Wll *

ADDRESS SWITCHES

~c:£

pnUm

VECTOR SWITCHES

*NOTES:
JUMPERS W9, W12, W13, W14, W15, AND W16 ARE REMOVED ONLY FOR MANUFACTURING TESTS_
THEY SHOULD NOT BE RH'OVED IN THE FIELD_
JUMPERS Wl0 AND Wl1 MUST REMAIN INSTALLED WHEN THE MODULE IS USED IN
A BACKPLANE THAT SUPPLIES LSI-ll BUS SIGNALS TO THE C AND D CONNECTORS
OF THE DZVll (SUCH AS THE H9270).
WHEN THE MODULE IS USED IN A BACKPLANE THAT INTERCONNECTS THE C AND D SECTIONS TO AN ADJACENT MODULE,
JUMPERS Wl0 AND Wll MUST BE REMOVED.
MK-0064

Figure 2-1

M7957 Jumper Locations

2-2

2.3.1.2 Modem Control Jumpers - There are eight jumpers used for modem control. The jumpers
labeled WI through W4 connect Data Terminal Ready (DTR) to Request To Send (RTS). This allows
the DZVII to assert both DTR and RTS if using a modem that requires control of RTS. These
jumpers must be installed to run the cable and external test diagnostic programs. The remaining four
jumpers, W5 through W8, connect the Forced Busy (FB) leads to the RTS leads. With these jumpers
installed, the assertion of an RTS lead places an ON or BUSY signal on the corresponding Forced
Busy lead. The Forced Busy jumpers (W5 through W8) are normally cut out unless the modem requires them (Table 2-2).

Table 2-2

Jumper Configuration

Jumper

Connection

Line

WI
W2
W3
W4
W5
W6
W7
W8

DTR to RTS
DTR to RTS
DTR to RTS
DTR to RTS
RTS to FB
RTS to FB
RTSto FB
RTS to FB

03
02
01
()()

2.3.2 Module Installation
To install the M7957 module, perform the following.
1.

Refer to Paragraph 4.2 for descriptions of the address assignments. Set the switches at E30
so that the module responds to its assigned address. When a switch is closed (ON), a binary
I is decoded. When a switch is open (OFF), a binary 0 is decoded. Note that the switch
labeled I corresponds to address bit 12,2 corresponds to address bit 11, etc. (Figure 2-2 and
Table 2-3).

Vector selection is accomplished by the 8-position switch at E2. Switch positions 7 and 8 are
not used. Switch position 6 corresponds to vector bit 3, 5 corresponds to vector bit 4, etc.
When a switch is closed (ON), a binary 1 is decoded. When a switch is open (OFF), a binary
o is decoded (Figure 2-3 and Table 2-4).

If the module is part of the DZVII-A option, perform step 3. If it is a part of the DZVII-B

option, proceed to step 4 for testing.
a.

Run the DZVII diagnostics, MAINDECs DVDZA and DVDZB, in internal mode to
verify operation. Refer to the listing for assistance. Run at least three passes without
error.

Proceed to step 8.
2-3

ADDRESS SELECTOR
A12 All A10 A09 AOa A07 A06 A05 A04 A03

E30
Switch
Address

OFF

I I I I I I I I I I

1
Al2

163760
163770
X

M7957 Address Selection

Table 2-3

Address Switch Selection

2
All

3
AIO

4
A9

S
A8

X
X

SWITCH
E30

6
A7

7
A6

8
AS

9
A4

X
X

X
X
X
X

X
X

10
A3

NOTE:

Figure 2-2

160000
160010
160020
160030
160040
160050
160060
160070
160100

X =ON

- = OFF

VECTOR SELECTOR
NOT
voa V07 V06 V05 V04 V03 USED

MA-0914

Figure 2-3

M7957 Vector Selection

2-4

X
X
X

Table 2-4
E2
Switch
Vector

Vector Switch Selection

1
V08

2
V07

3
V06

X
X
X
X
X
X
X
X

760
770

X
X

NOTE:

X =ON
- = OFF

300
310
320
330
340
350
360
370
400

5
V04

6
V03

X
X

X
X
X
X

X
X

4
V05

X
X
X
X

Insert the H329 test connector in 11 with the letter side facing up. 11 is the cable connector at
the top of the M7957 module.

Insert the module in a quad QBus slot of the backplane.
CAUTION
Insert and remove modules slowly and carefully to
avoid snagging module components on the card
guides and changing switch settings inadvertently.
Run the DZVll diagnostics, MAINDECs DVDZA and DVDZB, in the staggered mode to
verify module operation. Refer to the diagnostic listing for the correct procedure. Run at
least three passes without error.

Replace the H329 test connector with the Berg end of the BCll U cable assembly. Observe
the "This Side Up" wording on the assembly. Refer to D-UA-DZVII-O-O for installation
help.

Connect the H325 test connector on the first line and run MAINDEC DVDZC. Select the
cable test portion of the diagnostic. Three passes are required without error. Repeat this step
for each line.

Run DEC/XII system exerciser to verify the absence of QBus interference with other system devices.

2-5

The DZVll is now ready for connection to external equipment. If the connection is to a
local terminal through the DZVII-B option, a null modem cable assembly must be used.
Use the BC03M or BC03P null modem cables for connection between the BCII U and the
terminal. The H312-A null modem unit may also be used in place of the null modem cables.
If connection is to a Bell 103 or equivalent modem, install the appropriate line of the BCII U
connector into the connector on the modem. A BC05D cable may be required between the
BC II U and the modem. Refer to Paragraph 2.3 .1.2, Modem Control Jumpers, for selection
of jumpers for modem options such as RTS and forced busy. All of the cables mentioned,
excluding the BCII U, must be ordered separately as they are not components of a standard
DZV II shipment. When possible, run the diagnostic DVDZC in echo test mode to verify the
cable connections and the terminal equipment.

2-6

CHAPTER 3
DEVICE REGISTERS

3.1 SCOPE
This chapter provides a description of each DZVll register, its format, and its bit functions.
3.2 DEVICE REGISTERS
The DZVII contains six addressable registers. A comprehensive pictorial of these registers' bit assignments is shown in Figure 3-1. Table 3-1 lists the registers and associated DZV II addresses.
3.2.1 Control and Status Register
The control and status register (CSR) is a byte- and word-addressable register. All bits in the CSR are
cleared by an occurrence of BINIT or by setting device Master Clear (CSR 04). The format is shown in
Figure 3-1 and the bit assignments are listed in Table 3-2.
3.2.2 Receiver Buffer
The receiver buffer (RBUF) is a 16-bit read-only register that contains the received character at the
output of the FIFO buffer. A read of the register causes the character entry to be extracted from the
buffer and all other entries to bubble down to the lowest unoccupied location. Only the Valid Data bit
(RBUF 15) is cleared by BINIT or by setting device Master Clear (CSR 04). Bits 00-14 are not
affected. The bit assignments for the RBUF register are listed in Table 3-3.

Table 3-1

DZVll Register Address Assignments

Mnemonic

Address

Program
Capability

Control and Status Register
Receiver Buffer
Line Parameter Register
Transmitter Control Register
Modern Status Register
Transmit Data Register

CSR
RBUF
LPR
TCR
MSR
TDR

76XXXO
76XXX2
76XXX2
76XXX4
76XXX6
76XXX6

Read/Write
Read Only
Write Only
Read/Write
Read Only
Write Only

xxx = Selected in accordance with floating device address scheme.

3-1

MSB

LSB

ORO

·1

{

CONTROL

RO
- -

or - - .

& STATUS

TROY

l~~__~1

rI ~~~~ ~~
I

i I

...

RECEIVER
BUFFER

'!.O__ .

TIE
___

R~_

_ _ _ __

(RBUF)

DR21

DR4

LINE
PARAMETER
(LPR)

TRANSMIT
CONTROL
(TCR)

MODEM
STATUS
(MSR)
DR6
TRANSMIT
DATA

TBUF

(_TO_R_)__~~__-L__~~____~____~__~~__~__~____~_7__~__~__5__~____~__________~__~___
O~
MA.Q552

Figure 3-1

Table 3-2

CSR Bit Assignments

Function

Bit

Title

00-02

Not used

Maintenance

This bit, when set, loops all the transmitter's serial output leads
to the corresponding receiver's serial input leads on a TTL
basis. While operating in maintenance mode, the EIA received
data leads are disabled. Normal operating mode is assumed
when this bit is cleared. This bit is read/write.

Master Clear

When written to a I, this bit generates "initialize" within the
DZVII. A read-back of the CSR with this bit set indicates initialize in progress within the device. This bit is self-clearing. All
registers, silos, and UARTS are cleared with the following exceptions.
I.

Only bit 15 of the receiver buffer register (Valid Data)
is cleared; the remaining bits 00-14 are not.

The high byte of the transmitter control register is not
cleared by Master Clear.

The modem status register is not cleared by Master
Clear.

Master Scan
Enable

This read/write bit must be set to permit the receiver and transmitter control sections to begin scanning. When cleared, Transmitter Ready (CSR 15) is inhibited from setting and the received
character buffers (silos) are cleared.

Receiver
Interrupt
Enable

This bit, when set, permits setting CSR 07 or CSR 13 to generate a receiver interrupt request. This bit is read/ write.

Receiver Done

This is a read-only bit that sets when a character appears at the
output of the first-in/first out (FIFO) buffer. To operate in interrupt per character mode, CSR 06 must be set and CSR 12
must be cleared. With CSR 06 and CSR 12 cleared, character
flag mode is indicated. Receiver Done clears when the receiver
buffer register (RBUF) is read or when Master Scan Enable
(CSR 05) is cleared. If the FIFO buffer contains an additional
character, the Receiver Done flag stays cleared a minimum of I
IlS before presenting that character.

08-09

Transmitter Line
Number

These read-only bits indicate the line number whose transmit
buffer requires servicing. These bits are valid only when Transmitter Ready (CSR 15) is set and are cleared when Master Scan
Enable is cleared. Bit 08 is the least significant bit.

10-11

Not used

3-3

Table 3-2

CSR Bit Assignments (Cont)

_B_it~, ~_-1~~~~T~it_le~~~~~G~_n~c_ti_o_n~~_ ~_~~_~~_ ~~~
12

Silo Enable
Alarm

This is a read/write bit. When set, it enables the Silo Alarm
counter to keep count of the number of characters stored in the
FIFO buffer. The counter is cleared when the Silo Alarm Enable bit is cleared. Conditioning of this bit must occur prior to
any character reception.

Silo Alarm

This is a read-only bit set by the hardware after 16 characters
have been entered into the FIFO buffer. Silo Alarm is held
cleared when Silo Alarm Enable (CSR 12) is cleared. This bit is
reset by a read to the receiver buffer register and does not set
until 16 additional characters are entered into the buffer. If Receiver Interrupt Enable (CSR 06) is set, the occurrence of Silo
Alarm generates a receiver interrupt request. Reception with
CSR 06 cleared, permits flag mode operation of the Silo Alarm
bit.

Transmitter
Interrupt
Enable

This bit must be set for Transmitter Ready to generate an interrupt. It is read/write.

Transmitter
Ready

This bit is read only and is set by the hardware. This bit sets
when the transmitter clock stops on a line whose transmit buffer
may be loaded with another character and whose associated
TCR bit is set. The transmitter line number, specified in CSR 08
and CSR 09, is only valid when Transmitter Ready is set. Transmitter Ready is cleared by any of the following conditions.
1.

When Master Scan Enable is cleared

When the associated TCR bit is cleared for the line
number pointed to in CSR 08 and CSR 09

At the conclusion of the load instruction of the transmit data register (low byte only)

If additional transmit lines require service, Transmitter Ready
reappears within 1.4 f..lS from the completion of the transmit
data register load instruction. The occurrence of Transmitter
Ready with Transmitter Interrupt Enable set, generates a transmitter interrupt request.

3-4

Table 3-3

RBUF Bit Assignments

Bit

Title

Function

00-07

Received
Character

These bits contain the received character, right justified. The
least significant bit is bit 00. Unused bits are o. The parity bit is
not shown.

08-09

Received
Character
Line Number

These bits contain the line number upon which the Received
Character was received. Bit 08 is the least significant bit.

10-11

Not used

Parity Error

This bit is set if the sense of the parity of the received character
does not agree with that designated for that line.

Framing Error

This bit is set if the received character did not have a stop bit
present at the proper time. This bit is usually interpreted as indicating the reception of a break.

Overrun Error

This bit is set if the received character was preceded by a character that was lost due to the inability of the receiver scanner to
service the UART receiver holding buffer on that line.

Valid Data

This bit, when set, indicates that the data presented in bits 00-14
is valid. This bit permits the use of a character-handling program that takes characters from the FIFO buffer until there are
no more available. This is done by reading this register and
checking bit 15 until the program obtains a word for which bit
15 is zero.

3.2.3 Line Parameter Register
The line parameter register (LPR) controls the operating parameters associated with each line in the
DZV 11. The LPR is a word-addressable, write-only register. The line parameters for all lines must be
reloaded following an occurrence of either BINIT or device Master Clear. Table 3-4 lists bit assignments.
3.2.4 Transmitter Control Register
The transmitter control register (TCR) is a byte- and word-addressable register. The low byte of the
TCR register contains the transmitter control bits which must be set to initiate transmission on a line.
Each TCR bit position corresponds to a line number. For example, TCR bit 00 corresponds to line 00,
bit 01 to line 01, etc. Setting a TCR bit causes the transmitter scanner clock to stop if the UART for
this line has a transmit buffer empty condition. An interrupt is then generated if Transmitter Interrupt
Enable is set. The scanner clock restarts when either the transmit data register (TOR) is loaded with a
character or the TCR bit is cleared for the line on which the clock has stopped. TCR bits must only be
cleared when the scanner is not running (i.e., Transmitter Ready is set or Master Scan Enable is
cleared).

3-5

Table 3-4

LPR Bit Assignments

Bit

Title

Function

00-01

Parameter Line
Number

These bits specify the line number for which the parameter information (bits 3-12) is to apply. Bit 00 is the least significant
bit.

Not used

Must always be written as a zero when specifying the parameter
line number. Writing this bit as a one extends the parameter line
number field into nonexistent lines. Parameters for lines 00-03
are not affected.

03-D4

Character
Length

These bits are set to receive and transmit characters of the
length (excluding parity) as shown below.
04

o
o
I
I

o
I
o

5 bit
6 bit
7 bit
8 bit

Stop Code

This bit sets the stop code length (0 = I unit stop, I = 2 unit
stop or 1.5 unit stop if a 5-level code is employed).

Parity Enable

If this bit is set, characters transmitted on the line have an appropriate parity bit affixed, and characters received on the line
have their parity checked.

Odd Parity

If this bit is set and bit 06 is set, characters of odd parity are
generated on the line and incoming characters are expected to
have odd parity. If this bit is not set, but bit 06 is set, characters
of even parity are generated on the line, and incoming characters are expected to have even parity. If bit 06 is not set, the
setting of this bit is immaterial.

08-11

Speed Code

The state of these bits determines the operating speed for the
transmitter and receiver of the selected line.
11

Baud Rate

0
0
0
0
0
0
0
0

0
0
0
0
1

0
0

I
I

0
0

0
0
0

0
0
1
1
0
0

50
75
110
134.5
150
300
600
1200
1800
2000
2400

1
I

I
I
I

3-6

I
I
I

0
I

0
0
0

Receiver
Enable

13-15

Not used

This bit must be set before the UART receiver logic can assemble characters from the serial input line. This bit is cleared
following a BINIT or device Master Clear.

The TCR bits are represented in bits 00-03. These bits are read/write and are cleared by BINIT or
device Master Clear. Bits 04-07 are unused and read as zero.
The high byte of the TCR register contains the writable modem control lead, data terminal ready
(DTR). Bit designations are as follows.
Bit

09
10

11
12-15

Name
DTR Line 00
DTR LineOI
DTR Line 02
DTR Line 03
Unused; read as zero

Assertion of a DTR bit puts an ON condition on the appropriate modem circuit for that line. DTR
bits are read/write and are cleared only by BINIT. Jumpers have been provided to allow the RTS
circuits to be asserted with DTR assertions.
3.2.5 Modem Status Register
The modem status register (MSR) is a 16-bit read-only register. A read to this register results in the
status of the readable modem control leads, Ring and Carrier. The ON condition of a modem control
lead is interpreted as a logical one. Bits 04-07 and 12-15 are unused and read as a zero. Remaining bit
designations are as follows.
Bit
00

01
02
03
04-07

Bit

Name
Ring Line 00
Ring Line 01
Ring Line 02
Ring Line 03
Unused; read as zero.

09
10
11

12-15

3-7

Name
Carrier Line 00
Carrier Line 01
Carrier Line 02
Carrier Line 03
Unused; read as zero.

3.2.6 Transmit Data Register
The transmit data register (TDR) is a byte- and word-addressable, write-only register. Characters for
transmission are loaded into the low byte. TDR bit ()() is the least significant bit. Loading of a character should occur only when Transmitter Ready (CSR 15) is set. The character that is loaded into this
register is directed to the line defined in CSR bits 08 and 09. The high byte of the TDR is designated as
the break control register.
Each of the four multiplexer lines has a corresponding break bit for that line. TDR bit 08 represents
the break bit for line GO, TDR bit 09 for line 01, etc. TDR bits 12-15 are unused. Setting a break bit
forces that line's output to space. This condition remains until cleared by the program. This register is
cleared by BINIT or device Master Clear. The break control register can be utilized regardless of the
state of the device Maintenance bit (CSR 03).

3-8

CHAPTER 4
PROGRAMMING

4.1

SCOPE

This chapter contains information for programming the DZVll in the most efficient manner. To do
so, the programming controls must be fully understood. The following paragraphs discuss the DZVll
from the programming point of view and describe recommended programming methods.

4.2

DEVICE ADDRESS ASSIGNMENTS

The device address assigned to the DZVll resides in the floating address space of the LSI-II. This
address space ranges from 160010s to 163776s. Each DZVll requires increments of 109 address locations and the first option should be configured with an address of 160010s. The initial configured
address assumes that the system consists of only DZVlls in the floating address field. If the DUVII
option is also configured in the floating address field, assign the DZV 11 an address that establishes a
gap of 108 address locations between the last DUVII and the first DZVll. For example: If the system
consists of one DUVII located at 160010g, the DZVll should be configured with an address of
1600308.

4.3

INTERRUPT VECTOR ADDRESS ASSIGNMENTS

The DZV 11 device vector address is selected from the floating vector space. This space ranges from
address 300g to address 776s. Each DZVll requires increments of 109 address locations for its two
contiguous interrupt vectors. If the DZV II is the only option in the floating vector area, configure it
for a vector of 300g. If there are options other than the DZVll residing in the floating vector area,
other configuration rules must be applied. When configuring the device vector, only the first vector
address must be considered. The first vector, or base vector, must start on a zero boundary.
A zero boundary is one that has the three least significant bits equal to zero. The second vector is
controlled by the first vector and data bit 02. Data bit 02 is generated by the M7957 hardware.
Any option ahead of DZVl1 in the floating vector space that is not in the configuration should not
occupy any vector space gap. For example, if only DZVll is in the system, the vector for DZVll
should be 300. The simplest case is as follows.
Option

Address

GAP
GAP
GAP
GAP
GAP
GAP
GAP
DZVII
GAP

160010
160020
160030
160040
160050
160060
160070
160100
160110

Comment

Vector

No QBus-compatible DJ11
No QBus-compatible DHII
No QBus-compatible DQll
No DUVl1
No QBus-compatible DUPII
No QBus-compatible LKII
No QBus-compatible DMCII
300
No more DZVlls

4-1

Each DZVII requires two interrupt vectors, one for the transmitter section and one for the receiver
section. If simultaneous interrupt requests are generated from each section, the receiver section would
have priority in placing its vector onto the LSI bus. A receiver interrupt to address XXO is generated
from having either a Receiver Done (CSR 07) or Silo Alarm (CSR 13) occurrence. A transmitter
interrupt to address XX4 is generated by Transmitter Ready (CSR 15). Additional prerequisites for
generating interrupts are that the individual interrupt enable bits (CSR 06 and CSR 14) be set. The
recommended method of clearing interrupt enable bits is first to raise the processor status word to level
4; next, to clear these interrupt enable bits; and then lower the processor status word to zero. Using this
method prevents false interrupts from being generated.
4.4 PROGRAMMING FEATURES
The DZVII has several programming features that allow control of baud rate, character length, stop
bits, parity, and interrupts. This paragraph discusses the application of these controls to achieve the
desired operating parameters.
4.4.1 Baud Rate
Selection of the desired transmission and reception speed is controlled by the conditions of bits 08-11
of the LPR. Table 4-1 depicts the required bit configuration for each operating speed. The baud rate
for each line is the same for both the transmitter and receiver. The receiver clock is turned on and off
by setting and clearing bit 12 in the LPR for the selected line.

Table 4-1 Baud Rate Selection Chart
- --

Bits
11
0
0
0
0
0
0
0
0
I
1
1
1
I
1
1
1

10
~

0
0
0
0
1
I
I
I
0
0
0
0
I
1
I
1

Baud Rate

09
-~- ~--~--

---~~--

0
I
0
I
0
1
0
I
0
1
0
I
0
1
0
I

0
0
1
I
0
0
I
I
0
0
1
1
0
0
I
I

-50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
Not used

4.4.2 Character Length
The selection of one of the four available character lengths is controlled by bits 03 and 04 of the LPR.
The bit conditions for bits 04 and 03, respectively, are as follows: 00 (5-level), 01 (6-level), 10 (7-level),
and 11 (8-level). For character lengths of 5, 6, and 7, the high-order bits of the received character are
forced to zero.
4-2

4.4.3 Stop Bits
The length of the stop bits in a serial character string is determined by bit 05 of the LPR. If bit 05 is a
zero, the stop length is one unit; bit 05 set to a one selects a 2-unit stop unless the 5-level character
length (bits 03 and 04 at zero) is selected, in which case the stop bit length is 1.5 units.
4.4.4 Parity
The parity option is selected by bit 06 of the LPR. Parity is enabled on transmission and reception by
setting bit 06 to a one. Bit 07 of the LPR allows selection of even or odd parity, and bit 06 must be set
for bit 07 to be significant. The parity bit is generated and checked by hardware and does not appear in
the RBUF or TBUF. The parity error (bit 12, RBUF) flag is set when the received character has a
parity error.
4.4.5 Interrupts
The Receiver Interrupt Enable (RIE) and Silo Alarm Enable (SAE) bits in the CSR control the circumstances upon which the DZVII receiver interrupts the LSI-II processor.
If RIE and SAE are both clear, the DZVII never interrupts the LSI-II processor. In this case, the

program must periodically check for the availability of data in the silo and empty the silo when data is
present. If the program operates off a clock, it should check for characters in the silo at least as often as
the time it takes for the silo to fill, allowing a safety factor to cover processor response delays and time
to empty the silo. The Receiver Done (RDONE) bit in the CSR sets when a character is available in the
silo. The program can periodically check this bit with a TSTB or BIT instruction. When RDONE is
set, the program should empty the silo.
If RIE is set and SAE is clear, the DZV II interrupts the LSI-II processor to the DZVII receiver vector

address when RDONE is set, indicating the presence of a character at the bottom of the silo. The
interrupt service routine can obtain the character by performing a MOV instruction from the RBUF.
If the program then dismisses the interrupt, the DZVII interrupts when another character is available
(which may be immediately if additional characters were placed in the silo while the interrupt was
being serviced). Alternatively, the interrupt service routine may respond to the interrupt by emptying
the silo before dismissing the interrupt.
If RIE and SAE are both set, the DZVII interrupts the LSI-II processor to the DZVII receiver vector

when the Silo Alarm (SA) bit in the CSR is set. The SA bit is set when 16 characters have been placed
in the silo since the last time the program has accessed the RBUF. Accessing the RBUF clears the SA
bit and the associated counter. The program should follow the procedure described in Paragraph 4.4.6
to empty the silo completely in response to an Silo Alarm interrupt. This ensures that any characters
placed in the silo while it is being emptied are processed by the program.
NOTE
If the program processes only 16 entries in response

to each Silo Alarm interrupt, characters coming in
while interrupts are being processed build up without
being counted by the Silo Alarm circuit and the silo
may eventually overflow without the alarm being issued.
If the Silo Alarm interrupt is used, the program will not be interrupted if fewer than 16 characters are

received. In order to respond to short messages during periods of moderate activity, the LSI-II program should periodically empty the silo. The scanning period depends on the required responsiveness
to received characters. While the program is emptying the silo, it should ensure that DZVII receiver
interrupts are inhibited. This should be Gone by raising the LSI-II processor priority. The Silo Alarm
interrupt feature can significantly reduce the LSI-II processor overhead required by the DZVII receiver by eliminating the need to enter and exit an interrupt service routine each time a character is
received.
4-3

The Transmitter Interrupt Enable (TIE) bit controls transmitter interrupts to the LSI-II processor. If
enabled, the OZVII interrupts the LSI-II processor at the OZVII transmitter interrupt vector when
the Transmitter Ready (TROY) bit in the CSR is set, indicating that the OZVII is ready to accept a
character to be transmitted.
4.4.6 Emptying the Silo
The program can empty the silo by repeatedly performing MOV instructions from the RBUF to
temporary storage. Each MOV instruction copies the bottom character in the silo so it is not lost and
clears out the bottom of the silo, allowing the next character to move down for access by a subsequent
MOV instruction. The program can determine when it has emptied the silo by testing the Oata Valid
bit in each word moved out of the RBUF. A zero value indicates that the silo has been emptied. The
test can be performed conveniently by branching on the condition code following each MOV instruction. The TST or BIT instruction must not access the RBUF because these instructions cause the next
entry in the silo to move down without saving the current bottom character. Furthermore, following a
MOV from the RBUF, the next character in the silo is not available for at least I IlS. Therefore, on fast
CPUs, the program must use sufficient instructions or NOPs to ensure that successive MOVs from the
RBUF are separated by a minimum of I IlS. This prevents a false indication of an empty silo.
4.4.7 Transmitting a Character
The program controls the OZV 11 transmitter through four registers on the QBus: the control and
status register (CSR), the line parameter register (LPR), the transmit control register (TCR), and the
transmit data register (TOR).
Following OZVll initialization, the program must use the LPR to specify the speed and character
format for each line to be used and must set the Master Scan Enable (MSE) bit in the CSR. The
program should set the TIE bit in the CSR ifit wants the OZVII transmitter to operate on a program
interrupt basis.
The TCR is used to enable and disable transmission on each line. One bit in this register is associated
with each line. The program can set and clear bits by using MOV, MOVB, BIS, BISB, BIC, and BICB
instructions. (If word instructions are used, the Line Enable bits and the OTR bits are simultaneously
accessed.)
The OZVII transmitter is controlled by a scanner which is constantly looking for an enabled line (Line
Enable bit set) which has an empty UART transmitter buffer. When the scanner finds such a line, it
loads the number of the line into the 2-bit transmit line number (TUNE) field of the CSR and sets the
TROY bit, interrupting the LSI-II processor if the TIE bit is set. The program can clear the TROY bit
by moving a character for the indicated line into the TBUF or by clearing the line enable bit. Clearing
the TROY bit frees the scanner to resume its search for lines needing service.
To initiate transmission on an idle line, the program should set the TCR bit for that line and wait for
the scanner to request service on the line, as indicated by the scanner loading the number of the line
into TUNE and setting TROY. The program should then load the character to be transmitted into the
TBUF by using a MOVB instruction. If interrupts are to be used, a convenient way of starting up a line
is to set the TCR bit in the main program and let the normal transmitter interrupt routine load the
character into the TBUF.

4-4

NOTE
The scanner may find a different line needing senice
before it finds the line being started up. This occurs if
other lines request senic~ before the scanner can find
the line being started. The program must always
check the TUNE field of the CSR when responding
to TROY to ensure that it loads characters for the
correct line. Assuming the program senices lines as
requested by the scanner, the scanner eventually
finds the Qne being started. If several lines require
senice, the scanner requests senice in priority order
as determined by line number. Line 3 has the highest
priority and line 0 the lowest.
To continue transmission on a line, the program should load the next character to be transmitted into
the TBUF each time the scanner requests service for the line as indicated by TUNE and TRDY.
To terminate transmission on a line, the program loads the last character normally and waits for the
scanner to request an additional character for the line. The program clears the Line Enable bit at this
time instead of loading the TBUF.
The normal rest condition of the transmitted data lead for any line is the one state. The Break (BRK)
bits are used to apply a continuous zero signal to the line. One bit in the TDR is associated with each
line. The line remains in this condition as long as the bit remains set. The program should use a MOVB
instruction to access the BRK bits. If the program continues to load characters for a line after setting
the BRK bit, transmitter operation appears normal to the program despite the fact that no characters
can be transmitted while the line is in the continuous zero sending state. The program may use this
facility for sending precisely timed zero signals by setting the BRK bit and using transmit ready interrupts as a timer.
It should be remembered that each line in the DZV 11 is double buffered. The program must not set the
BRK bit too soon or the two data characters preceding the break may not be transmitted. The program must also ensure that the line returns to the one state at the end of the zero sending period before
transmitting any additional data characters. The following procedure accomplishes this. When the
scanner requests service the first time after the program has loaded the last data character, the program
should load an all-zero character. When the scanner requests service the second time, the program
should set the BRK bit for the line. At the end of the zero sending period, the program should load an
all-zero character to be transmitted. When the scanner requests service, indicating this character has
begun transmission, the program should clear the BRK bit and load the next data character.

4.4.8 Data Set Control
The program may sense the state of the Carrier and Ring Indicator signals for each data set and may
control the state of the Data Terminal Ready signal to each data set. The program uses two registers to
access the DZVll data set control logic. There are no hardware interlocks between the data set control
logic and the receiver and transmitter logic. Any required coordination should be done under program
control.

4-5

The Data Terminal Ready (DTR) bits in the TCR are read/write bits. Setting or clearing a bit in this
register turns the appropriate DTR signal on or off. The program may access this register with word or
byte instructions. (If word instructions are used, the DTR and Line Enable bits are simultaneously
accessed.) The DTR bits are cleared by the INIT signal on the QBus but is not cleared if the program
clears the DZVll by setting the CLR bit of the CSR.
The Carrier (CO) and Ring (RI) bits in the MSR are read-only bits. The program can determine the
current state of the Carrier signal for a line by examining the appropriate bit in the MSR. It can
determine the current state of the Ring signal by examining the appropriate bit of the ring register. The
program can examine these registers separately by using MOVB or BITB instructions or can examine
them as a single 16-bit register by using MOV or BIT instructions. The DZVll data set control logic
does not interrupt the LSI-II processor when a Carrier or Ring signal changes state. The program
should periodically sample these registers to determine the current status. Sampling at a high rate is
not necessary.

4-6

CHAPTERS
TECHNICAL DESCRIPTION

5.1

GENERAL

This chapter describes the DZV II at three levels: interface, circuit function, and circuit operation.
Where practical, the illustrations reference the circuit schematic page number and use the signal mnemonics (Figure 5-1). Signal mnemonics in the Field Maintenance Print Set are prefaced by the page
number on which they originate. For example, DI2 VALID DATA H originates on sheet D12. The
print set is helpful, but not essential, for understanding this chapter.
For further information about the LSI chips used on the DZVII, refer to Appendix A.

j
BINIT L

INDICATES THAT SIGNAL IS IN
LOGIC LOW STATE WHEN TRUE

INDICATES THAT SIGNAL IS IN
LOGIC HIGH STATE WHEN TRUE

I/O
INITIALIZE H
CONTROL
___
LOGIC
05

•

\ . REFER TO SHEET 05 OF THE CIRCUIT SCHEMATICS
TO LOCATE THE DETAILS OF THIS CIRCUIT.
MK-0130

Figure 5-1

5.2

Labeling Conventions

INTERFACE FUNCTIONS

This paragraph illustrates the sequences of signal exchanges that occur among the LSI-II, the DZVII,
and data sets. For a detailed description of LSI-II operation, refer to the Microcomputer Handbook
(DEC part number EB 07948 53/77). For a discussion of the signals at the circuit level, refer to
Pararaph 5.4 of this manual. For information about the specific meaning and function of modem
signals, refer to the documentation for the modem with which the DZVII is to be used.

5.2.1

LSI-ll to DZVll Interface

Figure 5-2 lists the signals that interface the LSI-ll to the DZVII. Table 5-1 defines these signals.
Figures 5-3 through 5-6 indicate their interaction.

5-1

--.-,----=--="""

BDAL 00 L-BDAL 15 L
BINIT L
BIRQ L
BIAKI L
BIAKO L

LSI-11
CPU

DZV11

BBS7 L
BSYNC L
BDIN L

...

-~~~

BDOUT L
BWTBT L
BRPLY L

Figure 5-2

Table 5-1

LSI-ll/DZVll Interface

LSI-ll/DZVll Interface Signals

Mnem_o_n_ic~~~+-I~__ Description
BINIT L

Initialize - BINIT is asserted by the processor to initialize or clear all devices
connected to the I/O bus. The signal is generated in response to a power-up
condition.

BIRQ L

Interrupt Request - A device asserts this signal when its interrupt enable and
interrupt request flip-flops are set. If the processor's processor status (PS)
word bit 7 is 0, the processor responds by acknowledging the request by
asserting BDIN Land BIAKO L.

BIAKI L
BIAKO L

Interrupt Acknowledge Input and Interrupt Acknowledge Output - This is
an interrupt acknowledge signal that is generated by the processor in response to an interrupt request (BIRQ L.) The processor asserts BIAKO L,
which is routed to the BIAKI L pin ofthe first device on the bus. If the device
is requesting an interrupt, it inhibits passing BIAKO L. If it is not asserting
BIRQ L, the device passes BIAKI L to the next (lower-priority) device via its
BIAKO L pin and the lower-priority device's BIAKI L pin.

BBS7 L

Bank 7 Select - The CPU asserts BBS7 L when an address in the upper 4K
bank (address in the 28K-32K range) is placed on the bus. BSYNC L is then
asserted and BBS7 L remains active for the duration of the addressing portion of the bus cycle.

--~------~~~-------

5-2

Table 5-1

LSI-lljDZVll Interface Signals (Cont)

Mnemonic

Description

BSYNC L

Synchronize - BSYNC L is asserted by the CPU to indicate that it has placed
an address on BDALO-15 L. The transfer is in process until BSYNC L is
negated.

BDIN L

Data Input - BDIN L is used for two types of bus operations:
1. When asserted during BSYNC L time, BDIN L implies an input
transfer, and requires a response (BRPL Y L). BDIN L is asserted
when the CPU is ready to accept data from the DZVll.
2. When asserted without BSYNC L, BDIN L indicates that an interrupt operation is occurring.

BDOUT L

Data Output - BDOUT, when asserted, implies that valid data is available
on BDALO-15 L and that an output transfer is taking place. BDOUT Lis
deskewed with respect to data on the bus. The DZVll must assert BRPL Y L
to complete the transfer.

BWTBT L

Write/Byte - BWTBT L is used in two ways to control a bus cycle:
1.

It is asserted during the leading edge of BSYNC L to indicate that

an output sequence is to follow (DATO or DATOB), rather than an
input sequence.
2. It is asserted during BDOUT L, in a DATOB bus cycle, for byte
addressing.
BRPLY L

Reply - BRPLY L is asserted in response to BDIN L or BDOUT Land
during IAK transaction. It is generated by the DZVll to indicate that it has
placed its data on the BDAL bus or that it has accepted output data from the
bus.

BDALO L
BDALl L
BDAL2 L
BDAL3 L
BDAL4 L
BDAL5 L
BDAL6 L
BDAL7 L
BDAL8 L
BDAL9 L
BDALlO L
BDALlI L
BDALl2 L
BDAL13 L
BDALl4 L
BDALl5 L

Data/ Address Lines - These lines form a bidirectional bus. First, the CPU
places address information on the bus. After the desired device has been
addressed, the CPU removes the address. Then data is placed on the bus. For
an output transfer, the CPU places the data on the bus. For an input transfer, the DZVll places the data on the bus.

5-3

DZV11

LSI-11

- - ---

STROBE INTERRUPTS
• Assert BDIN L

I
I

+
GRANT REQUEST

- - --

INITIATE REQUEST
• Assert BIRQ L

-. RECEIVE BDIN L
• Store "interrupt selected"
in device

• Pause and assert
BIAKO L

RECEIVE BIAKI L
• Receive BIAK I L and inhibit
BIAK 0 L
• Place vector on BDAL 0-15 L
• Assert BRPL Y L
• Terminate BIRQ L
/"

/"
./
,/

¥
RECEIVE VECTOR & TERMINATE
REQUEST
• Input vector address
• Terminate BDIN Land BIAKO L

COMPLETE VECTOR TRANSFER
• Remove vector from
BDAL bus
• Terminate BRPL Y L

PROCESS THE INTERRUPT
• Save current program PC
and PS on stack
• Load new PC and PS from
vector addressed location
• Execute interrupt service
routine for the device

Figure 5-3

MK 0131

Interrupt Request/Acknowledge Sequence

5-4

LSI-11

DZV11

ADDRESS DZV11
• Assert BDALO-15 L with
address and
• Assert BBS7 if the
address is in the 28 - 32K range _
• Assert BSYNC L

.REQUEST DATA
• Remove the address
from BDALO-15 L
and negate BBS7 L
• Assert BDIN L

-....

------

- -- --

TERMINATE INPUT TRANSFER
• Accept data and respond by
negating BDIN L

TERMINATE BUS CYCLE
• Negate BSYNC L

----

-- -

----- - -

DECODE ADDRESS
• Store "device selected"
operation

INPUT DATA
• Place data on BDALO-15 L
• Assert BRPLY L

~-----

..... OPERATION COMPLETED
• Terminate BRPLY L

Figure 5-4 DATI Bus Cycle

5-5

LSI-ll

DZV11

ADDRESS DZVll
• Assert BDA LO-15 L with
address and
• Assert BBS7 L (if address
is in the 28 - 32K range)
• Assert BWTBT L (write
cycle)
• Assert BSYNC L

OUTPUT DATA
• Remove the address from
BDALO-15 L
and negate BBS7 Land BWTBT L
(BWTBT L remains active if
DATOB cycle)
• Place data on BDALO-15 L
• Assert BDOUT L

TERMINATE OUTPUT TRANSFER
• Remove data from BDALO-15 L
and negate BDOUT L

- --...--

DECODE ADDRESS
• Store "device selected"
operation

- - --

-- - - - -

....

... - -- - - -...
- - - --

TAKE DATA
• Receive data from BDAL lines
• Assert BRPL Y L

OPERATION COMPLETED
• Terminate BRPL Y L

~TERMINATE BUS CYCLE
• Negate BSYNC L (and BWTBT L
if a DATOB bus cycle)

Figure 5-5

MK·0133

DATO or DATOB Bus Cycle

5-6

LSI·11

DZV11

ADDRESS DZV11
• Assert BDALO·15 L with
address
• Assert BBS7 and if the
address is in the 28 . 32K range
• Assert BSYNC L

- -- --.-- - - -

- - . DECODE ADDRESS
• Store "device selected"
operation

REQUEST DATA
• Remove the address from
BDALO·15 L
and negate BBS7 L
• Assert BDIN L

TERMINATE INPUT TRANSFER
• Accept data and respond by
terminating BDIN L

OUTPUT DATA
• Place output data on BDAL0-15 L
• (Assert BWTBT L if an output
byte transfer)
• Assert BDOUT L

- - - - - - -...
..... - - - - - - -.
..- - - - - - - - ...
...-

TERMINATE OUTPUT TRANSFER
• Terminate BDOUT L, and remove _
data from BDAL lines

TERMINATE BUS CYCLE
• Negate BSYNC L
(and BWTBT L if in
a DATIOB bus cycle)

Figure 5-6

- - - - - -.

--- ---

INPUT DATA
• Place data on BDAL0-15L
• Assert BRPL Y L

COMPLETE INPUT TRANSFER
• Remove data
• Terminate BRPL Y L

TAKE DATA
• Receive data from BDAL lines
• Assert BRPL Y L

OPERATION COMPLETED
• Terminate BRPL Y L

MK~0134

DATIO or DATIOB Bus Cycle

5-7

Transactions between the LSI-II and the DZVII may be program-initiated or interrupt-driven. An
interrupt-driven transaction is illustrated in Figure 5-3. An input operation (DATI) is equivalent to a
read operation. An output operation (DATO or DA TOB) is equivalent to a write operation. A DATI
reads a word. A DA TO writes a word. A DATOB writes a byte. These operations are described further
in Paragraph 5.4.
A DATIO cycle is equivalent to a read-modify-write operation. An addressing operation and an input
word transfer are first executed in a manner similar to the DATI cycle; however, BSYNC L remains in
the active state after completing the input data transfer. This causes the addressed device or memory to
remain selected, and an output data transfer follows without any further addressing. After completing
the output data transfer, the device terminates BSYNC L, completing the DA TIO cycle. The sequence
required for a DA TIO cycle is shown in Figure 5-6. Note that the output data transfer portion of the
bus cycle can also be a byte transfer. This is a DATIOB cycle. Figure 5-6 illustrates both.
5.2.2 DZVll to Data Set Interface
When the DZVII interfaces a local terminal, the only exchanges may be EIA level data. When interfacing a data set, however, the DZVII controls from one to three signals, and monitors two others.
1able 5-2 defines the modem control signals. Figures 5-7 through 5-9 illustrate typical sequences. The
response the DZVll makes to the Ring and Carrier signals is under program control.

Table 5-2

Modem Control Signals

Signal

Function

Data TerminI Ready

Enables the local modem to be connected with a remote
modem. This signal is negated to terminate a call.

Request to Send

Holds the modem in the transmit mode.

Forced Busy

Used with Bell Model103E and I13B equipment. Signals
the modem controller to switch to another channel.

Ring Indicator

Indicates that the local modem is receiving a ringing signal
from a remote modem.

Carrier (Received Line
Signal Detector)

Indicates that the local modem is receiving a signal from a
remote modem, and that the signal meets the suitability
criteria of the local modem.

5-8

DATA COMMUNICATION
EQUIPMENT (DCE)

DATA TERMINAL
EQUIPMENT (DTE)

PROGRAM ASSERTS
DATA TERMINAL
READY (CD)

CUSTOMER DIALS NUMBER.
RING BACK IS HEARD.
ANSWERING STATION
ASSERTS DATA TERMINAL
READY. BOTH STATIONS
ENTER DATA MODE.
DATA SETS EXCHANGE
CARRIER FREQUENCIES.
CHANNEL ESTABLISHED.
CARRIER DETECT (CF)
IS ASSERTED.
RECEIVED DATA (BB)
LEAD UNCLAMPED

TRANSMITTED
DATA (BA)
DATA
COMMUNICATION
BEGINS

RECEIVED
DATA (BB)

DZV11

Figure 5-7

DATA SET
MODELS 103A/E/G/H, 113A, 212A
(ORIGINATING EQUIPMENT)

Channel Established by Local Modem

5-9

DATA COMMUNICATION
EQUIPMENT (DCEl

DATA TERMINAL
EQUIPMENT (DTE)

RINGING SIGNAL
RECEIVED FROM
REMOTE STATION
RING INDICATOR (CE)
IS ASSERTED
PROGRAM ASSERTS
DATA TERMINAL
READY (CD)
THIS ASSERTS
REQUEST TO
SEND (CA)

DATA SETS EXCHANGE
CARRIER SIGNALS
AND ESTABLISH CHANNEL
CARRIER DETECT (CF)
IS ASSERTED

TRANSMITTED
DATA (BA)
DATA
COMMUN ICATION
BEGINS

RECEIVED
DATA (BB)

DZV11

DATA SET
MODEL 202D
(ANSWERING EQUIPMENT)

NOTE:
EXAMPLE SHOWS MODEM CONFIGURED FOR UNATtENDED ANSWERING AND
FULL DUPLEX DATA-PHONE SERVICE_ (DATA-PHONE IS A SERVICE MARK OF
MK-0136
THE AT & T CO_)

Figure 5-8

Channel Established by Remote Modem

5-10

DATA TERMINAL
EQUIPMENT (DTE)

DATA COMMUNICATION
EQUIPMENT (DCE)

r-----.~

PROGRAM ASSERTS
DATA TERMINAL
READY (CD). THIS
ASSERTS BOTH
REQUEST TO SEND
(CA) AND FORCED
BUSY.

DATA TERMINAL READY

REQUEST TO SEND

rFORCED BUSY

CARRIER ASSERTED

CUSTOMER DIALS
NUMBER. DATA
STATION ESTABLISHED
CHANNEL.

CARRIER DETECT (CF)
IS ASSERTED.

TRANSMITTED DATA (BA)
DATA
COMMUNICATION
BEGINS

RECEIVED DATA (BB)

DZVll

Figure 5-9

MODEL 103E WITH
FORCED BUSY OPTION.
(ORIGINATING EQUIPMENT)

MK0157

Interface with Bell Data Station

5.3 CIRCUIT FUNCTIONS
The major functional areas ofthe DZVll circuitry are represented in Figure 5-10. The numbers in the
blocks refer to the paragraphs in which the block is discussed.
Data to be transmitted on the communication lines moves from the LSI-II bus through the bus
interface to the TDR in the UARTs. There it is converted from parallel to serial and sent to the EIA
transmitters. The transmitters convert the serial data from TTL to EIA levels and send it to the
communication line (or data set.)
Data coming in from the communication lines is converted from EIA to TTL by the EIA receivers,
then from serial to parallel by the UARTs. The parallel data leaves the UART receiver buffers and is
stored in the silo buffer. From there it is transferred via multiplexers to the bus interface. The bus
interface places the data on the LSI-II bus.
The interrupt logic requests interrupt service when a transmitter is empty and when the silo buffer has
either 1 or 16 characters of received data, as selected by the program.
The transmitter control determines which of the four possible lines is to be used, and controls the
loading of the data.
The receiver control scans the receiver status and controls the loading and unloading of the silo.

5-11

EIA
TRANS.

BREAK
LOGIC
~

PARA.

06
010

010
TRANSMITTER
CONTROL ~
PARA.

5.4.10
09

BUS
INTER·
FACE

'\
./

5.4.1

f.
02
MULTIPLEXER

INTERRUPT
LOGIC

PARA.
:::J

5.4.3

a:l

SILO
BUFFER
PARA.

5.4.9

UARTs
(lNCLUOES
TRANSMIT
ANO
RECEIVE
OATA
BUFFERS)

MAINT.
MOOE
LOGIC
PARA.

5.4.11

•

010

PARA.

5.4.1

(:
-

011
1/0
I+'
CONTROL

PARA.

5.4.2

PARA.

f4-

5.4.4

013
014

5.4.9

-l

f+o.-

RECEIVER
CONTROL

ii5

EIA
RCVR.

5.4.6

012

PARA.

.'7

PARA.

(J)

5.4.5

5.4.7

SPEEO
ANO
FORMAT
CONTROL
PARA .

5.4.8
08

03~}
t FROMrrO

REGISTERS

1
POWER
SUPPLIES
PARA.

5.4.12

Figure 5-10 Simplified Functional Block Diagram
5-12

MK·0156

The speed and format control generates clock signals for the UARTs. Under program control, it
selects baud rate and stop bit, parity bit and character length parameters.
The break logic inhibits output data to create a BRK signal. The four lines operate independently and
under program control.
The maintenance mode data selector provides the capability of switching the data outputs the data
inputs. This is used to verify module operation.
The power supplies convert voltages available on the LSI-II bus into other voltages also required by
the module.
Each of the circuits shown in Figure 5-10 is described in greater detail in Paragraph 5.4.
5.4 CIRCUIT OPERATION
The interaction between the LSI-II and the DZVII is asynchronous to the interchanges between the
DZV II and the communication lines it controls. Therefore, the circuit description in this paragraph
treats the module from three points of view. Paragraphs 5.4.1 through 5.4.3 cover the operations of
moving control, status, and character data between the LSI-II and the DZVII internal registers.
Paragraphs 5.4.4 through 5.4.7 discuss the flow of data between the external lines and the DZVII
internal registers. Paragraphs 5.4.8 through 5.4.11 discuss functions that are controlled by the computer but directly affect the movement of data between the DZVII and the lines. Paragraph 5.4.12
discusses the power supplies.

5.4.1 Bus Interface
Data and control signals move between the LSI-II bus and the DZVll transmit and receive circuitry
by means of a group of bus transceivers, multiplexers, and latches. Figure 5-11 indicates the functional
relationship of these circuits to the addressable device registers.
The bus transceivers are contained in four DC005 transceiver chips. These interface LSI-II bus lines
BDALOO through BDALl5 to the module's internal device data bus lines 00 through 15. The device
data bus lines have three logical conditions: TTL low, TTL high, and disabled. The disabled state is a
very high impedance, which permits the internal bus lines to be used in both directions by high-speed,
low-power devices.
The transceiver chips also perform the functions of address decoding and vector generation. Address
decoding is accomplished by comparing the states of BDAL03 through BDALI2 with the states selected by address switches A03 through A 12 (switches 10 through I, respectively, on switchpack E30).
When the LSI-II addresses an I/O device, it asserts BBS7 L (bank select 7) during address time. This
indicates that the address is in the 28K-32K range of addressing space, and enables the DC005 transceivers to decode the address. If the address matches the switch selection, the circuit asserts DEVICE
SELECT H to the I/O control logic.
During data time, the transceivers transfer data from the LSI-II bus lines to the device data bus lines if
the operation is an output data transfer. If the operation is an input data transfer, the I/O control logic
asserts READ L and READ DEVICE H. This switches the transceivers to their opposite state, in
which they transfer data from the device data bus to the LSI-II bus.
The bus interface logic generates vector addresses under the control of the interrupt logic and vector
address switches V03 through V08 (switches 6 through I, respectively, on switchpack E2). The vector
switches set the states of vector bits 03 through 08 when the interrupt logic enables vector generation.
Bit 02 is controlled directly by the interrupt logic. It is set for a transmitter interrupt and cleared for a
receiver interrupt.
5-13

SW1-SW10
A12-A03

~~~.

ADDRESS
SWITCH
E30

.--

~~-

~DALOOI5~ BY--0
BBS7

TRANSCEIVERS
DC005

______

"'"

--~--

02 -

TOR

SW1-SW6
V08-V03

VECTOR
SWITCH E2

___ ~I
N

I-;-

~
-co

::::>

co
~

-'";"
en

U enU

It>

w ::::>w

> co>

0
0

1 kITH~

INIT L
INTERRUPT I
~
CHIP
U
w
DC003
...J

~AKIL
~AKO L .. ____

--~

- BUS
REPLY
DELAY
CIRCUIT
04

>
w

03
SO

MSR

>
w

05 w

REQUEST

BSYNC L
BWTBT L
.J!QQUT L
BRPLY L

----1

CSR

~TCR

l/L-

BIRQ L

~RBUF

«
~
«
Cl

BINIT L

~lNJ~
ENABLE

MULTIPLEXERS

LPR

::::>

...J

~ I~

INITIALIZE
CIRCUIT

--_._-

~ t

~--

...J

«
>
w w

Cl
Cl

MUX
ADDRESS
ENCODER
03

«
w
a:

I--

INWD
I/O
CONTROL
PROTOCOL
CHIP
1
DCOO4
SELECT 00 L
SEL 6
SEL4 ~LECT02 L
gLECT04 L
SEL 2
SELECT 06 L
SEL 0
OUT HB
04 OUT LB
~-~

LD LPR REG L
LD TOR REG H
REGISTER ~ BREAK H
•
LOAD
~ TCR HIGH BYTE H
DECODER rhQ TCR LOW BYTE H
g> CSR HIGH BYTE H
LD CSR LOW BYTE H
READ RCV BUFFER H
~AD DEVICE H
04

L...--- ___

Figure 5-11

MK-0127

Bus Interface, I/O Control and Interrupt Logic

5-14

When an interrupt occurs, the conditions selected by the vector switches are immediately placed on the
LSI-II bus lines. The transceivers do this without need of READ L or READ DEVICE H from the
I/O control circuit.
5.4.2 I/O Control
The I/O control logic controls the flow of status bits and data bits between the LSI-II and the device
registers. It monitors the three least significant bits of the address word to determine which register is
to be read or loaded, and which byte in the register is affected. It monitors BWTBT L (Write Byte) to
determine if a byte is being loaded or a word is being loaded. (The LSI-ll can write bytes, but reads
only words.) Control signals BDIN Land BDOUT L indicate whether data is to be moved into the
computer or out of it.
The major element in the I/O control circuit is a DCOO4 protocol chip (Figure 5-11). The chip uses
device data bus bits 01 and 02 to decode the device register address and then asserts one offour register
select lines. It uses device data bus bit 00 and BWTBT L to select either OUT HB for a high byte or
OUT LB for a low byte. If the operation is an output data transfer (indicated by BDOUT L), the
register load decoder uses OUT LB, OUT HB (or both) and the register select signals to produce a load
pulse. The load pulse enables the proper byte or bytes of the selected register to be loaded from the
device data bus.
The register select lines are also used to control the address lines on a group of eight multiplexers. If the
operation is an input data transfer (indicated by BDIN L), the I/O control switches the multiplexers to
the selected register and asserts READ L and READ DEVICE H. READ L enables the multiplexers
to place the data from the selected register on to the device data bus (Table 5-3). READ L and READ
DEVICE H together enable the bus transceivers to transfer the data from the device data bus to the
LSI-II bus (Table 5-4).
Table 5-3
SELECfL*

Multiplexer Addressing
MUX

Selected
Register

F
F
F
T

F
F
T
F

F
T
F
F

F
F
T
T

F
T
F
T

CSR
RBUF
TCR
MSR

---~

*T = TRUE condition, that is, +3 Von signal lines with an H suffix
and 0 V on signal lines with an L suffix.

Table 5-4 Transceiver Switching

~~~* :I~R~E-A~~-DE~~

Mode

LSI-ll bus to device data bus

Does not occur

LSI-ll bus disconnected/device
data bus open

Device data bus to LSI-ll bus

*T = TRUE condition, that is, +3 V on signal lines with an H suffix and 0 V on
signal lines with an L suffix.

5-15

5.4.2.1
1.

Input Operation - An input data transfer (DATI bus cycle) proceeds as follows.
The CPU places the device address on LSI-II bus lines BDALOO L through BDAL15 L, and
asserts BBS7 L. BWTBT L is negated at this time because all input transfers are full words
(Figure 5-12).

BDIN

BRPLY

BBS7~,-~~/

=____=___________________

BmBT~-·-X=
_____

MK·0137

Figure 5-12

Data Input Timing

The bus transceivers are configured to receive from the LSI-II bus unless switched otherwise. BBS7 L enables the transceivers to decode the address and to assert DEVICE SELECT
H, which enables the I/O control circuit.

The CPU asserts BSYNC L. The leading edge of BSYNC L latches the states of DEVICE
SELECT H and device data bus bits 00 through 02 into the protocol chip. These are decoded ,
to select the desired register by addressing the multiplexers.

N ext, the CPU removes the address from the LSI-II bus lines, negates BBS7 L, and asserts
BDIN L. BDIN L causes the I/O control to generate READ L and READ DEVICE H.
These signals place the contents of the selected register on the device data bus and the LSI-II
bus. BDIN L also generates BRPL Y L. This signals the computer that the data is on the bus.

The computer reads in the data and then negates BDIN L.

The I/O control logic responds to the negation of BDIN L by negating BRPLY L.

The CPU terminates the bus cycle by negating BSYNC L.

In the absence of a TRUE condition on BSYNC L, the protocol chip releases the register
selection lines and the READ L and READ DEVICE H signals. The bus interface reverts to
its normal condition of receiving from the LSI -II bus and transmitting onto the device data
bus.

5-16

5.4.2.2 Output Operation - The DZVII can accept data from the computer in either bytes or words.
To write a word out to the module, the CPU performs a DATO bus cycle. To write a byte, it performs
a DATOB bus cycle (Figure 5-13). An output data transfer proceeds as follows.
l.

The CPU places the device address on the LSI-II bus and asserts BBS7 Land BWTBT L.
(During address time, BWTBT L is asserted for an output operation and negated for an
input operation.) BBS7 L enables the bus interface to decode the address and assert DEVICE SELECT H to the I/O control. The bus interface also applies address bits 00 through
02 to the I/O control.

~--~-

BDAL

__--JI
BDOUT

BRPLY

~.~.~J

\"---

BBS7~~~-

MK-0142

Figure 5-13

Data Output Timing

The CPU asserts BSYNC L. The leading edge of BSYNC L latches the states of DEVICE
SELECT H and bits 00 through 02 into the protocol chip. The chip decodes the register
address and asserts the appropriate select line.

The CPU removes the address from the bus lines and negates BBS7 L. If a byte is to be
transferred, BWTBT L remains asserted. If a word is to be transferred, BWTBT L is negated.

At this time, the CPU asserts BDOUT L. BDOUT L enables the protocol chip to decode the
states of BWTBT L and the latched-in address bit 00. The chip uses the signals to assert
OUT HB, OUT LB, or, for word transfers, both (Table 5-5). These signals are gated with the
select lines to produce a load pulse (or pulses) for the selected byte(s).

After the protocol chip receives BDOUT L, it initiates the Bus Reply signal. If the register
being loaded is the LPR or the TDR, the Bus Reply signal is delayed before going to the
CPU as BRPL Y L. The delay ensures a minimum of 300 ns setup time for the register being
loaded. The LPR and TDR are located inside the UART and baud rate generator chips, and
therefore require longer to set up than the high-speed latches comprising the other registers.
After the delay times out, BRPLY L is asserted to the CPU to indicate that the register is
loading data.

5-17

Table S-S Byte Selection
(Output Operations Only)
BWTBTL

Device Data
Bus Bit 00

Signals
Asserted

Bytes
Selected

Don't care

OUTLBL
and
OUTHBL

Both

OUTLBL

Low

OUTHBL

High

Next, the CPU removes the data from the bus lines and negates BDOUT L.

The protocol chip responds to this by negating BRPLY L.

The CPU then terminates the bus cycle by negating BSYNC L and, if applicable, BWTBT L.

When BSYNC L is negated, the protocol chip negates the register select and byte lines.

S.4.2.3 Vector Operation - The I/O control has the additional function of asserting BRPL Y Lin
response to VECTOR-TO-BUS H from the interrupt control circuit. This action is part of the interrupt sequence, and is independent of the BSYNC L and DEVICE SELECT H. It is discussed in
Paragraph 5.4.3.
S.4.2.4 Initialize Circuit - This circuit produces two initialization signals (INITIALIZE H and INITIALIZE L) when it receives either BINIT L from the LSI-II bus or the Master Clear bit from the
CSR. Both input signals also generate other clear signals (Figure 5-14). The initialization and clear
signals clear the registers and latches on the module to set initial conditions.

CSR
BIT04

MASTER CLEAR H

II SEC

ONE
ONESHOT

INITIALIZE H

INITIALIZE L

MODEM CLEAR L

CLEAR REPLY H
MK 0138

Figure 5-14 Initialization Signals
5-18

•

5.4.3 Interrupt Logic
Most of the logic for interrupts is contained in a single DCOO3 interrupt chip (Figure 5-15). The chip
contains two interrupt channels: one for receiver interrupts and one for transmitter interrupts. The
circuit generates a receiver interrupt either when the RBUF has one character ready for the computer
(Receiver Done interrupt) or when the silo buffer has 16 characters ready (Silo Alarm interrupt).
The Receiver Done interrupt is enabled by setting CSR bit 06. The Silo Alarm interrupt is enabled by
setting bit 12. Setting bit 12, however, inhibits the receiver done signal from the RBUF. Therefore,
Receiver Done interrupts do not occur when Silo Alarm interrupts are enabled.
The circuit generates a transmitter interrupt when the TDR is empty and ready for another data
output from the computer. The Transmitter Ready interrupt is enabled by setting CSR bit 14.
Both the TIE and RIE bits are located physically in the DCOO3 interrupt chip although they are
functionally part of the CSR.
The LSI-II 's Interrupt Acknowledge signal (BIAKI L/BIAKO L) is daisy-chained through the devices
on the LSI-II bus. A device priority is established by its position in the Interrupt Acknowledge daisychain. In the DZVII interrupt logic, the chain goes through both the receiver section and the transmitter section of the interrupt chip. It passes through the receiver section first, thereby giving receiver
interrupts priority over transmitter interrupts.
Backplanes that provide bussed LSI-II signals to the C and D sections of the module also use the
daisy-chain scheme in the C section. Jumpers WIO and WI I on the DZVII pass the Interrupt Acknowledge and DMA Grant signals to prevent breaking the chain in that section of the backplane.
5.4.3.1 Interrupt Transactions - When interrupts are enabled and a condition requiring service occurs, the interrupt sequence proceeds as follows.
l.

The interrupt logic asserts BIRQ L, the interrupt request line (Figure 5-16).

The LSI-II responds to BIRQ L by asserting BDIN L and then BIAKI L. BIAK is the
bussed Interrupt Acknowledge signal. It is passed down the priority chain until it reaches the
section of the interrupt chip that initiated the request.

When the interrupt logic receives both BDIN Land BIAKI L, it asserts VECTOR-TO-BUS
H to the vector selection switches. If the interrupt is a transmitter interrupt, the circuit also
asserts VECTOR BIT 02 H. This signal adds four to the base (receiver interrupt) vector that
is asserted by VECTOR-TO-BUS H. The circuit also negates BIRQ L.

VECTOR-TO-BUS H causes the I/O control logic to issue BRPL Y L to the LSI-II. VECTOR-TO-BUS H and, if applicable, VECTOR BIT 02 H cause the bus transceivers to place
the selected vector on the LSI-II bus lines.

The computer reads in the interrupt vector and then, as a result of receiving BRPL Y L,
negates BDIN L. Shortly after this, it also negates BIAKI L.

The interrupt logic negates VECTOR-TO-BUS H and, if applicable, VECTOR BIT 02 H.

The negation of VECTOR-TO-BUS H causes the I/O control logic to negate BRPLY L,
and the bus transceivers to remove the vector from the LSI-II bus lines.

An interrupt transaction does not require BBS7 L, DEVICE SELECT H, BSYNC L, or READ L. The
interrupt logic overrides the normal I/O protocol.
5-19

)

BDAL 00:15 L
..

'\r-;BS7 L

BUS
INTERFACE
CIRCUITS
02
V8 V7 V6 V5 V4 V3 V2

I--------

VECTOR
SWITCH
E2

VECTOR-TOBUS H

-,-

I Dco03iNTERRuPT
ICHIP

BIRQ L

I
BIAKI L

BIAKO L

I
SILO ALARM ENABLE H

CSR
BIT
12

::J

SILO ALARM
ENABLE L

'";"

U5
....J

RCVR
CIRCUITS
011,012

RECEIVER
DONE H

SILO ALARM H
RECEIVER
INTERRUPT
ENABLE

TRANSMITTER
CIRCUITS

~~~~H

TRANSMITTER READY H

BRPLY L

I
I
I
I

II~
C

:H=lJ
L.-.-

I/O
CONTROL
LOGIC

TRANSRECEIVER
MITTER
INTERRUPT
J-- INTERRUPT ~
CHANNEL
CHANNEL

DEVICE DATA ICSR BIT 141
BUS 14 H
'
I JD
LD CSR
HIGH BYTE H

09
BINIT L

DEVICE DATAIICSR B I T P , D

LOW BYTE H

TRANSMITTER
INTERRUPT
ENABLE

INTERRUPT
CONTROL
CIRCUITRY

I
BDIN L

~BUSOO:15H

VECT<?BJ!!! 02 H

~1}
4

DEVICE DATA ....

INITIALIZE L

--T---~

VECTOR-TO-BUS H

-MK,0159

04,05

Figure 5-15

Interrupt Logic
5-20

_J/

BIRO --\'---_~ _ _ _

~'--~___--II

BDIN

"--_.---II
\ ____---JI

BIAKI

BRPLY

\~_____V_EC_T_O_R____~;r___

BDAL

BSYNC

(UNASSERTED)

BBS7

(UNASSERTED)

MK·0153

Figure 5-16 Interrupt Timing

A Silo Alarm interrupt can be distinquished from a Receiver Done interrupt by checking SAE bit
(CSR bit 12) when entering a service routine.
5.4.4 EIA Receivers
The DZVII receives three modem signals for each of the four communicaton lines it interfaces. Carrier
Detect, Ring Indicator, and Received Data are received and converted from EIA levels to TTL levels.
The Carrier and Ring signals go to the modem status register. The received data signals go to the
RBUF (in the UARTs). Refer to Figure 5-17.

CARRIER DETECT
MODEM

RING INDICATOR

EIA-TO-TTL ~RIER
RECEIVERS RING

RECEIVED DATA

( PART OF MUX )
MODEM
STATUS
REGISTER

DATA IN

ONE OF FOUR CIRCUITS

MAINTENANCE
SERIAL IN
MODE DATA
SELECTOR
010

RBUF
013
014
(PART OF
UARTs)

MK 0154

Figure 5-17

EIA Receivers
5-21

5.4.5 EIA Transmitters
The DZVII can control up to three modem control signals for each ofthe four communications lines it
interfaces (Figure 5-18). Control bits from the TCR are converted from TTL levels to EIA levels to
drive modem control lines. For each line there is a single control bit that is always connected to data
terminal ready (DTR). These signals may be jumpered to also control request to send (RTS). If this
done, they may then be further jumpered to control forced busy (for Bell model 103E and I13B
modems with the forced busy option).
Data to be transmitted from the computer to the lines moves from the transmitter data buffer to the
EIA transmitters, where it is converted from TTL levels to EIA levels and placed on the lines.

lElA TRANsMiTTERS •

TRANSMIT
CONTROL
REG ISTE R
DATA TE RM RDY H I
IHIGH BYTE)

~x:)--_ _ _~D_A-,-T_A-,-T--,E,,-R_M_'N_A-=L=-R_E:::..:A...c.D"-Y~--t

I ~r-~_~~~~.-___
I- --1 I

~~~_D~6~
TRANSMIT
DATA
REGISTER
D13
D14

R_EQ
__T_O_S_E_N_D__

MODEM

FORCED BUSY
D61
MAINTENANCE
MODE
~_I____~~~,~~________T_R_A_N_S_M_'T_T_E_D__
D_A_T_A____~
DATA
SELECTOR
I

Dl0

Figure 5-18

D2£.a

ONE OF FOUR CIRCUITS

EIA Transmitters

5.4.6 UARTs
The DZVII uses four UART chips, one for each of the four communication lines. Each UART
performs part of the functions of receiver buffer (RBUF), transmitter data register (TDR), and line
parameter register (LPR) for the channel under its control. The RBUF takes serial data received by the
EIA receivers, strips off the start, stop, and parity bits, converts it to parallel data, stores it in the silo
buffer, and then places it on the device data bus. The TDR takes parallel data from the device data
bus, appends start, stop, and parity bits, converts it to serial data, and sends it to the EIA transmitters.
The LPR controls the speed, parity, and number of stop bits that the RBUF and TDR use. (Figure 519).

5.4.6.1 Setting Line Parameters - The various formats and speeds available are described in Paragraph 1.3.3 (Performance). The names and meanings ofthe LPR bits are listed in Table 3-4. The low
byte of the LPR is contained inside the UARTs, and controls the data format. The high byte is
contained in the baud rate generator circuits, and controls the speed at which data is transmitted and
received.
When the computer addresses the LPR, the I/O control logic generates a load pulse. The load pulse
enables the LPR bits 00 and 01 to strobe the selected UART and baud rate generator. Bits 03 through
07 are latched into the UART to select the data format. Bits 08 through 11 are latched into the baud
rate generator to select the speed. Bit 12 enables the Receiver Clock signal to reach the UART.
5-22

010

I
BUS
INTERFACE

I
I
(/)

:::>

<{
~

MULTIPLEXER

I
I

TOR

STATUS
(HIGH
BYTE)

OATA
(LOW
BYTE)

>
w
0

FROM/TO
REGISTERS

RBUF

I
I
I

BREAK
LOGIC

EIA
TRANSMITTERS

010

MAINT_
MOOE
OATA
SELECTOR

010

EIA
RECEIVERS

07
SPEEO
(HIGH
BYTE)

08
LPR

Figure 5-19

MK·0139

UARTs

5.4.6.2 UART Receiver Operation - Serial data coming in from the EIA receiver is applied to the
receiver section of the selected UART. The UART samples the serial input at the receiver clock rate
(16 times the data bit rate). The line is in a continuous marking state when idle. When a start bit
arrives, the UART detects the mark-to-space transition. It samples the line again at the time corresponding to the middle of the start bit. If the line is marking, the UART logic assumes that the first
sample was noise, and resumes sampling. If it finds that the line is still spacing, however, the logic
assumes it is receiving a start bit, and enters the data entry mode. In this mode, the UART shifts the
data serially into an internal register (Figure 5-20). If parity is enabled, the UART checks the total of
the received data bits plus the parity bit. (It checks for an even total if even parity has been selected,
and an odd total if odd parity has been selected.) A parity error causes the UART to set the parity
error flag bit in the high byte of the RBUF word.
5-23

)

BREAK
BITS
Dl0

UARTS

\ DEVICE DATA

D13,D14

HOLDING REGISTER

- r-. LOGIC

Dl0

~------

MAINT.
MODE
LOGIC
Dl0

SERIAL·TO·PARALLEL
RECEIVER SHIFT REGISTER

EIA
RECEIVERS

Dl0

SILO
BUFFER

D12 '\r

EIA
TRANS.

BREAK

PARALLE L-TO-SE RIAL
TRANSMITTER SHIFT REGISTER

f--

I--

V
HOLDING REGISTER

MK~0140

Figure 5-20 UART and Break Bit Registers

The UART checks the stop bit to see ifit is marking. If the line is spacing instead, the UART sets the
framing error flag bit. If the line is marking, the U ART logic assumes there is a valid stop bit.
About half way through the stop bit time, the UART transfers the received character data, the parity
error bit, and the framing error bit from the serial shift register to the holding register. At this time it
asserts the Data Available signal to the receiver control logic. If the previous character has not yet been
serviced by the receiver control logic, the U ART sets the overrun error flag bit to indicate that the
previous character was lost.
The receiver control loads the contents of the RBUF (data and status) into the silo buffer for subsequent transfer to the computer. The receiver control circuit determines when and what type of
receiver interrupt to request.
5.4.6.3 UART Transmitter Operation - During idle time, the UART transmits a continuous marking
signal and holds the Transmitter Ready (TBMT) signal asserted. The transmitter control circuitry uses
this signal to determine when to initiate a transmitter interrupt request.

5-24

When the computer has data to transmit to a communication line, it uses a DATO or DA TOB sequence to address the TDR and place the data on the bus lines. The low byte of the TDR word is
loaded into a holding register in the UART. When the data enters the holding register, the UART
negates TBMT. It then transfers the data in parallel from the holding register to a serial shift register
and reasserts TBMT. In the serial shift register, the UART attaches start, stop, and parity bits, as set
by the LPR. The assembled character is then shifted serially out to the EIA transmitter.
Because the transmitter, like the receiver, is double-buffered, it can be loaded with a second character
before the first one moves out.

5.4.7 Break (BRK) Bits
The transmission and reception of BRK bits are closely related to the transmission and reception of
data. A Break signal is a continuous spacing condition on the serial data line. When a UART receives
a Break signal, it interprets the continuous space as a character that is missing a stop bit. Therefore, it
sets the framing error flag. The program then determines how a framing error is handled.
A Break signal may be transmitted by interrupting the flow of serial data leaving the UART. The high
byte of the TDR may be thought of as a break register. It contains one BRK bit for each of the four
communication channels. Setting one of these bits inhibits the flow of data from the UART transmitter to the EIA transmitter, thereby causing a Break to be transmitted on the communication line.
Refer to Figure 5-20.

5.4.8 Speed and Format Control
The circuits controlling speed and format include the LPR, two dual baud rate generator chips, an
oscillator, and two addressable latches. Refer to Figure 5-21.
When the LSI-ll computer writes a word out to the LPR, the following events occur.
1.

During address time, the bus interface and I/O control circuitry decode the address and
produce a load pulse, LD LPR REGISTER L.

During data time, the load pulse enables two addressable latches to be addressed by bits 00
through 02. One latch routes the state of bit 12 to a gate that inhibits or enables the receiver
clock to the selected U ART.
The other latch applies an enabling signal (CONTROL STROBE) to both the UART and
the baud rate generator chip section that control the communication line selected by bits 00
through 02.

Bits 03 through 07 are strobed into the selected UART to select the number of data bits; the
number of stop bits; and odd, even, or no parity.

Bits 08 through 11 are strobed into the selected baud rate generator chip to control the
amount by which the 5 MHz oscillator is divided to produce the UART clock signal. Table
4-1 and Paragraph 4.4.1 describe the baud rate selection scheme.

Thus, the LPR is formed by the latches located in the UARTs, baud rate generators, and addressable
latches.

5-25

LPR BITS
(ON DEVIDE
DATA BUS
LINES)
RECEIVER
CLOCK
ENABLE

CLOCK
ENABLE
LATCH

.--

DEVICE DATA BUS 12

}TO THE OTHER THREE
ENABLING GATES.
D8 I-

LD LPR REG L

t
MASTER
SCAN
CLOCK
COUNTER
D8

5MHZ
OSCILLATOR
D8

~ RECEIVER CLOCK

DEVICE DATA BUS 11
SPEED
CONTROL

DEVICE DATA BUS 10
DEVICE DATA BUS 09

BAUD RATE
GENERATORS

TRANSMITTER CLOCK

DEVICE DATA BUS 08
D8

DEVICE DATA BUS 07

DEVICE DATA BUS 06
DATA
FORMAT
CONTROL

8>0

UART
(ONE OF
FOUR)

DEVICE DATA BUS 05

DEVICE DATA BUS 04

DEVICE DATA BUS 03
D13,D14
DEVICE DATA BUS 02
LINE
{
SELECTION

DEVICE DATA BUS 01
DEVICE DATA BUS 00

CONTROL STROBE
LINE
ENABLE
LATCH

}

Figure 5-21

Speed and Format Control

5-26

CONTROL STROBES
TO OTHER UARTS
MK-0152

5.4.9 Receiver Control
5.4.9.1 Receiver Scanner - The receiver scanner circuit samples the states ofthe Data Available (DA)
signals from the UARTs. When it detects a TRUE condition, it generates a load pulse to transfer the
received data from the UART to the silo buffer. The sequence in which the receiver data available flags
are scanned and the characters loaded into the silo buffer is controlled by a 4-phase timing sequencer
and a group of multiplexers, demultiplexers, and counters.
The sequencer produces four timing signals (Figure 5-22). The signals times are designated Phase 1
through Phase 4.

MASTER
SCAN
CLOCK

SILO LOAD
REQUEST H

ENABLE

LOAD
SILO
FLIP
FLOP"",

SILO LOAD H

.:..-J

RCV SCAN LEAD B

ADDRESS
GENERATOR
011

DEMUX

RCV SCAN LEAD A

bEMUX
RESET DA 00-03
S1

•

C 0
011-

UARTS
00-03

)

OR@03y1

SEQUENCER i-

~-.

SILO
BUFFER

MUX

PE 00-03:) MUX

r--'I

FE 00-03.) MUX

-:!'\

--~------

:-------.

.J...

~D 1

AVAILABLE~rt

RCVDATAENABLEOO~

,....-

IN R E A D Y , W
DATA

~-.

DA 00-03

MUX
SO S1

.,.

IN
READY

~f-t

-f-t

I
SERIAL IN

I
I
.... _-l

013,014

RD1-RD8

011

012
SILO
COUNTER
011

MK-0160

Figure 5-22

Receiver Control

5-27

~TO

SILO
ALARM
FLIP
FLOP

During Phase 1, a signal toggles the address generator to increment by one count. The two least
significant bits of the counter are used as a 2-bit address code, designated RCV SCAN LEAD A and
RCV SCAN LEAD B. These two signals address a multiplexer. The multiplexer selects the Data
Available line from the UART corresponding to the address code and applies it to a gate. The other
input to the gate is a Ready signal from the silo buffer. This signal is asserted when the silo buffer is
ready to accept data. If the Data Available signal is set and the silo buffer is ready, the gate asserts
SILO LOAD REQUEST H. The load request is applied to the load silo flip-flop.
RCV SCAN LEAD A and RCV SCAN LEAD B also address a demultiplexer. The demultiplexer
places an enabling signal (RCV DATA ENABLE) on the line to the UART addressed by the scan
leads. This is the same UART that is having its Data Available line sampled. The RCV DATA ENABLE signal enables the UART to place the contents of its receiver holding register on the lines to the
silo buffer (RD 1 through RD8).
During Phase 2, the sequencer clocks the load silo flip-flop. If SILO LOAD REQUEST H is true, the
flip-flop sets. When the flip-flop sets, one output goes to the silo buffer as LOAD SILO H and strobes
received data from the UART into the silo buffer. At the same time the data enters, status information
is also loaded into the silo. Framing Error, Overrun Error, and Parity Error bits from the selected
UART are routed via multiplexers into the silo. The states of RCV SCAN LEAD A and RCV SCAN
LEAD B are loaded into the silo to indicate which communication line the received character came
from.
LOAD SILO H also goes to a latch in the sequencer. From there it passes through a demultiplexer and
asserts RESET DA to the selected UART. RESET DA clears the data available flag in the UART so
that another character may be received.
At the beginning of Phase 3 time, the zero output of the load silo flip-flop clocks the silo counter. The
silo counter increments by one count to keep a tally of the number of times the silo buffer has been
loaded. The silo counter counts only when SAE is set.
Phase 4 re-establishes the initial conditions of the scanner circuit for the next scan cycle.
5.4.9.2 Silo Buffer - The silo buffer comprises four 4-X 64-bit 3341 serial memory chips. The chips
are arranged as a 16-bit-Iong, 64-word-deep first in/ first out (FIFO) memory. Data is entered in the
"top" of the memory as described in the previous section. The In Ready signal means there is a
vacancy in the top word of the memory. Similarly, the Out Ready signal indicates there is a word in the
"bottom" of the silo waiting to be shifted out.
The buffer stores full RBUF words. Received character data is stored in the low byte, and receiver
status data in the high byte. The buffer shifts data in when it receives LOAD SILO H from the load silo
flip-flop, and it shifts data out when it receives UNLOAD SILO H from the unload control (Figure 523).
Data is shifted out as a result of either a Receiver Done interrupt or a Silo Alarm interrupt. The
presence of an Output Ready signal from each of the four chips asserts RECEIVER DONE H to the
interrupt logic. If the Receiver Done Interrupt Enable bit is set, the interrupt logic asserts the Interrupt
Request signal to the CPU.
If the Silo Alarm Interrupt Enable bit is set, RECEIVER DONE H is inhibited at the interrupt logic.

In this case, a receiver interrupt is not requested until the silo buffer has 16 characters ready. Setting
Silo Alarm Enable allows the silo counter to increment each time the silo is loaded. On the sixteenth
count, the silo counter overflows, and the Carry Out signal sets the silo alarm flip-flop. The flip-flop, in
turn, asserts SILO ALARM H to the interrupt logic.

5-28

[SiLOBU~ -

I .I
I ==
I -:::
'----

FE, OR, PE
RCV SCAN
LEADS

RD1·RDB

SHIFT
OUT

IN
ROY

SHIFT
IN

OUT
ROY

I f-I ::::::
=:
I
I

SHIFT
IN

OUT
ROY

~
~
IN
ROY

t-- SHIFT
IN

OUT
ROY

I
I
I
I :::::
=:

::::::

SHIFT
OUT

IN
ROY

~ SHIFT.
IN

OUT
ROY

L-_

3341

DATA
AVAILABLE.....--.

"'\
J

I I
I

SILO
COUNTER

:---r--

011

SILO ALARM H

TO
INTERRUPT
LOGIC

I.SILO ALARM

SltoLoAD
FLIP FLOP

FLIP FLOP

RECEIVER DONE H

--..

r--I

SILO LOAD

I .J"'\ REQUEST H r--1 IN READY

FROM
1/0
CONTROL

READ RCV
BUFFER H

;--

o 1

VALID DATA H

C a
'---

!
i

... -

UNLOAD SILO H

ONE
I . - SHOT

I
~

3341

LOAD SILO H

IN
ROY

3341

-l
I

SHIFT
OUT

>t =:

3341

r-- SHIFT
OUT

f--

I
I

f:::

I
I
I

I=:

L- - --

_ _D d

"
~)

RBUF WORD

"
CSR

R
R
-

---....

...

MULTIPLEXER

",/
")
"

Figure 5-23 Silo Buffer

)

BUS
INTER·
FAr.E
02

MKOHil

When the interrupt request is acknowledged, the silo is unloaded. The unloading sequence is the same
for both types of receiver interrupts. It proceeds as follows.
I.

When data reaches the bottom of the silo, the Out Ready signals are gated together to
produce RECEIVER DONE H.

RECEIVER DONE H is applied to a latch. When a CPU input transaction (DATI) addresses the RBUF, READ RCV BUFFER H latches the state of RECEIVER DONE H.

The output of the latch is VALID DATA H. This signal conditions one input of a one-shot.

The trailing edge of READ RCV BUFFER H triggers the one-shot, which generates UNLOAD SILO H.

UNLOAD SILO H causes the silo buffer to shift out an RBUF word (character and status
data). The word is transferred via a multiplexer to the device data bus. From there the bus
transceivers place it on the LSI-II bus. VALID DATA H is applied to the multiplexer along
with the output of the silo buffer, where it becomes bit 15 of the RBUF word.

5.4.10 Transmitter Control
The transmitter control circuit checks the transmitter control register to determine which lines are
enabled. It checks the UARTs to determine which are ready to transmit, and it enables the UART
controlling the highest priority line to load data from the CPU.
The sequence begins with the Master Scan Enable signal from the CSR (Figures 5-24 and 5-25).
MASTER SCAN ENBL H triggers a 350 ns one-shot. The leading edge of the one-shot output clocks
a 4-bit latch. A True bit in the latch indicates that the corresponding line is enabled and that the
transmitter buffer empty flag is set for the U AR T controlling that line. Outputs from the latch are
applied to a priority encoder. The priority encoder generates a 2-bit code to represent the communication line number. When more than one channel is ready at the same time, the code always indicates
the one having the highest priority. (Line 03 has the highest priority; line 00, the lowest.) This code
addresses two multiplexers in the transmitter control circuit, and also goes to CSR bits 08 and 09. The
CSR bits TLINE A and TLINE B tell the program on which line the next character will be transmitted. The priority encoder also applies a Ready signal to the transmitter ready flip-flop when any of
the bits in the latch are true.
The trailing edge of the 350 ns one-shot output performs two functions.
I.

The zero (false) output clocks the transmitter ready flip-flop. Assuming a Line Enable bit is
set and a TBMT signal is true, the transmitter ready flip-flop asserts TRANSMITTER
READY H to the interrupt logic and the CSR. If enabled, a transmitter interrupt request is
initiated.
The transmitter ready flip-flop also disables the gate controlling the input to the 350 ns oneshot. This inhibits further clocking until the line can be serviced. At the same time, the signal
enables the contents of the line enable latch to enter a multiplexer.

The second function ofthe trailing edge of the 350 ns one-shot is to trigger a 100 ns one-shot.
The output of the 100 ns one-shot disables the input to the 350 ns one-shot. The 350 ns oneshot is inhibited to prevent losing the latched-in line number.

5-30

FROM
UAflT
TRANSMITTERS

TB~ _ _ _ _

TBMT 02
TBMT03

TRANSMITTER
READY FLIP FLOP

TCR
BITS
0(}03

DEVICE~

g~ATCH

LOGIC

TRANS MITTER
LlNEB

(,)
'--~

---Dec
n

STB

350
NS
ONE
SHOT

MUX

DEVICE
DATA BUS

-f--

---

PULSE
FORMING
CIRCUIT

TO CSR
BITS

TRANS
LINE A

}

-- -

MASTER SCAN ENBL L

LOAD IN
PROGRESS L

MASTER SCAN
ENBL H

MUX

100
NS
ON
SHO

------

6
STB .... THRL03L

-C

I'"
FROM
1/0
CONTROL

DEMUX

h-THRL 02 L
I'"

r-..THRL01 L
LDTDR
REGISTER H

TO
UART
TRANSMITTERS

ONE
US
ONE
SHOT

r---J

, ..,THRL 00 L
S1

I T

I'"

I
MK 0143

Figure 5-24 Transmitter Control

5-31

PRIORITY
ENCODER

L D C L R CLK

CLK
LD TCR
LOW BYTE H

f-CD

DATABV

TRAN SMITTER
READ

1 - - - - ~---------INTERRUPT

08,09

TRANSMITTER IDLE SEQUENCE
MASTER SCAN
ENBL H

INITIATE TIMING SEQUENCE

350 NS
ONE SHOT (1) H
100 NS
ONE SHOT (1) H --~-....

TRANSMITTER LOADING SEQUENCE
350 NS
ONE SHOT (1) H
100 NS
ONE SHOT (1) H

TBMT-TCR
CONDITION
TRANSMITTER
READY (1) H
INTERVAL
LDTDR
REGISTER H _ _ _ _ _ _ _ _ _ _ _.......
ONE SHOT
)......, --~1 JISEC (1) H _ _ _ _ _ _ _ _ _ _ _ _ _~1 JISEC.t'L_ _ _ _ _ __
NOTE 4.

NOTE 5.

NOTES:
1. CLOCK EDGE FOR SAMPLING (TBMT-TCR) CONDITIONS.
2.
CLOCK EDGE FOR TRIGGERING 100 NS ONE SHOT AND
PRESENTING (TBMT·TCR) CONDITIONS.
3.
TRANSMIT READY SETS. TIMING SEQUENCE IS DISABLED.
4.
POSITIVE EDGE CLEARS TRANSMIT READY AND KEEPS
TIMING SEQUENCE DISABLED.
5.
FALLING EDGE INITIATES TIMING SEQUENCE FOR
NEW SAMPLE.
MK0151

Figure 5-25

Transmitter Timing

5-32

The assertion of TRANSMITTER READY H ultimately results in the CPU performing a DATOB to
load data into the TDR. During address time, the I/O control asserts load pulse LO TDR REGISTER
H. LOAD IN PROGRESS L from the I/O control strobes LD TDR REGISTER H into a demultiplexer. The demultiplexer output is a transmitter-holding register load pulse (THRL). It is routed to
the UART which controls the line addressed by the priority encoder. This enables the UART transmitter to load character data from the device data bus during data time.
When LD TDR REGISTER H returns to the negated state, the trailing edge triggers a 1 J.LS one-shot.
The output of the one-shot clears the transmitter ready flip-flop. It also disables the gate controlling
the input to the 350 ns one-shot. The 350 ns one-shot is inhibited in order to allow the UART sufficient
time to drop its transmitter buffer empty flag before the circuit starts another scan cycle.
When the program is finished sending a message, it clears the Line Enable bit in the TCR. This occurs
after the enable bit and TMBT signals have already been latched in and TRANSMITTER READY H
has been asserted. It is, therefore, necessary to prevent the scanner from locking up on a line for which
there is no data. This is accomplished by clearing the transmitter ready flip-flop if it is set for a line
which is no longer enabled. The states of the Line Enable bits from the TCR are applied to a multiplexer. The bit corresponding to the line addressed by the priority encoder is passed to a pulse-forming
circuit. When the bit is cleared, a 50 ns pulse is formed. This pulse clears the transmitter ready flip-flop,
thereby negating TRANSMITTER READY H and allowing the 350 ns one-shot to fire for the next
transmitter scan cycle.
5.4.11 Maintenance Mode
The DZV 11 can be switched to receive the data that it is transmitting (Figure 5-26). The four serial
data lines leaving the UARTs are applied to both a data selector and the EIA transmitters. The data
selector controls the inputs to the UART receivers. During normal operation, data from the EIA
receivers is routed through the data selector to the UART receivers. In the maintenance mode, the data
selector ignores the inputs from the EIA receivers. Instead, it routes the output data to the UART
receivers. This internal "wrap-around" feature is enabled by setting the Maintenance bit in the CSR.
Setting CSR bit 03 asserts MAINTENANCE H, which switches the data selector. External maintenance configurations are discussed in Chapter 6.
5.4.12 Power Supplies
In addition to the +12 V and +5 V available on the LSI-ll bus, the DZVll also requires +3 V, -9 V,
and - 12V. The +3 V source is a voltage divider. The negative voltages are produced by two capacitive
charge pump circuits.
Each of the two charge pumps uses the following scheme.
1.

An oscillator running at approximately 500 kHz switches a pair of drivers on and off (Figure
5-27).

The outputs of the drivers are capacitively coupled to a rectifier.

The negative-going output of the rectifier builds up a charge on a capacitor.

The charge is Zener-regulated back to the required negative voltage.

5.5 SUMMARY OF DEVICE REGISTERS
This paragraph contains drawings that relate the bits in each register to the circuits in which they are
used. Each bit is represented by a block containing the information shown in Figure 5-28. For a
description of the meanings and functions of the bits, refer to Chapter 3. For a discussion of their
usage, refer to Chapter 4.

5-33

TOR
HIGH
BYTE
UARTS

I TOR

LOW
BYTE
1_-

SERIAL OUT
00-03

~---,

BREAK
LOGIC

EIA
TRANSMITTERS
010

010

I RBUF
LOW

I BYTE
1_-

SERIAL IN
00-03

013,014

MAINT.
MODE
DATA
SELECTOR
010

EIA
RECEIVERS

07
CSR
BIT03

MAINTENANCE H

Figure 5-26 Maintenance Mode

5-34

OSC

H
H

DRIVERS

~~ :~

RECTIFIER

f(
RECTIFIER

""1-.J

If IREGULATOR~_9V
t

+5Vi

REGULATOR f.--- -12V A

'--

REGULATOR f---- -12V B

q~---~-.+3V

MK 014!)

Figure 5-27 Power Supplies

BIT NAME
RO = READ ONLY
RW = READ/WRITE
WO = WRITE ONLY

BIT NUMBER

LINE
ENAB

D9
CIRCUIT SCHEMATIC PAGE
ON WHICH BIT IS HELD.

Figure 5-28

Bit Labeling Scheme

5-35

CSR
BITS

SOURCE

DESTINATION

TRANSM ITTE1TRANSM IHE R 15 RO
CONTROL
READYH ___ ~
TRDY
__ D9
DEVICE
D9
DATA
14 RW
TIE
F~iERFACE BUS 14
E_11_
D2
D5

MULTIPLEXER

l
.... INTERRUPT
LOGIC

~-tI

~CEIVER

~- SlLO ALARM H

DEVICE
-=-;----~-~ DATA
BUS
LSI-11 ~ INTERFACE BUS 12
D2

SA
D11
12 RW
SAE

CONTROL
D11
.

~-IMUL TlPLEXER
D3
SILO ALARM ENABLE RECEIVER
CONTROL
D11

TRANSMITTER
LlNEB
TRANSMITTER
CONTROL TRANSMITTER
LINE A
D9
.---

r--

RECEIVER
RECEIVER DONE H
CONTROL
D12
DEVICE
DATA
BUS 06

09 RO
T LINE
B
D9
MULTIPLEXER
08 RO
T LINE ~
A
D9
07 RO
R
D3
DONE ~
~12

06 RW
RIE

INTERRUPT

r- LOGIC

RECEIVER
D5
D5
.... CONTROL
05 RW
Dl1
MASTER SCAN ENBL
LSI-11 '--e BUS
MSE
INTER·
DEVICE
TRANSMITTER
D5
FACE DATA
....
CONTROL
04 RW
INITIALIZE
BUS 04
D9
CLR ~ CIRCUIT
DEVICE
D5
D5
DATA
MAINTENANCE
03
RW
___
DATA
MAINT MAINTENANCE H
SELECTOR
D2
D5
Dl0
--02
DEVICE
DATA
BUS 05

-----

~03

00
MK0158

--~-.

Figure 5-29

Control and Status Register
5-36

RBUF
BITS

SOURCE

!03

~
03

OESTINATION

15 RO
OATA
VAllO
OATA H VAlle
011
OVERRUN
14 RO
ERROR
OVRN
~
f-----ERR
012
13 RO FRAMING
FRAM ERROR
ERR
012
RECEIVER
SILO
PARITY
BUFFER
CONTROL
PAR ERROR
ERR

12R'O

~J~
11

10
UARTS

011

R07

RCV
LINE A
012

RCV OATA07

ROB

RCV
LlNEB

lffiY OATA 06

•

SILO
BUFFER RCV OATA 05

I R05 •

RCV OATA 04

RCV OATA 03

09 RO
RX
LINE
B 012
OB RO
RX
LINE
A 012
07 RO
RBUF
07012

MULTIPLEXER

06 RO
RBUF
06
012
05 RO
RBUF
05
012
04 RO
RBUF
04
012
03 RO
RBUF
03

~J£

~3.

RCV OATA 02

I-R02 •

RCV OATA 01

013, ~
014

RCV OATA 00

'---~

012

02 RO
RBUF
02
012
01 RO
RBUF01
012
00 RO
RBUF
00
012

03
MK-0146

Figure 5-30

Receiver Buffer Register
5-37

~ ~
BUS
INTERFACE

LSI-11

I""..-.--

LPR
BITS

SOURCE

DESTINATION

14
~

DEVICE DATA BUS 12

~CE DATA BU_Ul.

DEVICE DATA BUS 10

BUS
INTERFACE
~CE DATA BUS 07

LSI-11

DEVICE DATA BUS 06

DEVICE DATA BUS 05

SPEED WO
CODE
B
D8

SPEED WO
CODE
A
D8

04
DEVICE DATA BUS 04

DEVICE DATA BUS 03

D8
SPEED WO
CODE
D
D8
SPEED WO
CODE
C
D8

09
MYl(:E DATA BUS 09

DEVICE DATA BUS 08

-Vi6
RX
ENAB

ODD
PAR
PAR
ENB

WO
D2
WO

SPEED
AND
FORMAT
CONTROL

D8
~()D PARITY L

PARITY ENABLE L

D2
STOP WO
CODE
D13, D14
CHAR WO
LGTH
B 013, D14
CHAR WO
LGTH
A D13, D14

~~VICE DATA BUS 01

LINE
B

WO
D8

DEVICE DATA BUS 00

LINE
A

W6
D8

UARTS

----

D13,D14

SPEED
AND
FORMAT
CONTROL
D8
MK 0147

Figure 5-31

Line Parameter Register
5-38

DESTINATION

TCR
BITS

SOURCE
15

DEVICE DATA BUS 11

DEVICE DATA BUS_!Q.

DTR
3
DTR
2

DATA TERM ROY 03

06
RW
DATA TERM ROY 02

r-=-------~
09

~YICE DATA BUS 09

DEVICE DATA BUS 08
BUS
INTERFACE

LSI-11

DTR
1
DTR
0

DATA TERM ROY 01

~
RW

DATA TERM ROY 00

EIA
TRANSMITTERS

DEVICE DATA BUS 03

DEVICE DATA BL!~

DEVICE DATA BUS 01.

DEVICE DATA BUS OQ..

LINE
ENAB
3

LINE
ENAB
2

LINE
ENAB
1

LINE
ENAB
0

RW
09
RW
09
RW

TRANSMITTER
CONTROL

09
RW
09

09
MK0148

Figure 5-32 Transmit Control Register
5-39

MSR
BITS

SOURCE

DESTINATION

CARRIER 03 H

CARRIER 02 H
EIA
RECEIVERS

RO
CO
3
CO
2

f---t
D7
RO
~

-~~
CARRIER 01 H

RO
CO
1 D7

-~-

CAR R I E ROO_Ii...

CO
0

RO
~

07
MULTIPLEXER

BUS
INTERFACE

LSI-11

~~.-

04
D2
03
RING 03 H

EIA
RECEIVERS

RING 02 H

RO
RI3
f---4o
D7
RO
RI2
f---.

D7
RO
RING 01 H
RI 1 ~
D7
()()
RO
RING 00 H
RIO I ---.
01

Figure 5-33

MK0149

Modem Status Register
5-40

TOR
BITS

SOURCE

DESTINATION

14
1-------

~YICE DATA BU.~

DEVICE DATA BUS 10

BRK
3
BRK
2

WO
010
WO
010
WO

BREAK
LOGIC

f------- - - - -

DEVICE DATA BUS 09

BUS
DEVICE DATA BUS 08
INTERFACE

DEVICE DATA BUS 07

LSI-ll

DEVICE DATA BUS 06

DEVICE DATA B~~

BRK
1
BRK
0

010
WO

010
TBUF WO
7
013,014
TBUF WO
6
013,014
TBUF WO

010

5
013,014

DEVICE DATA BUS 04

04
~

TBUF WO
4
013,014
; -

DEVICE DATA BUS 02

TBUF WO
3
013,014
TBUF WO

DEVICE DATA BUS 01

013,014
r-o,< TBUF
WO

DEVICE DATA BUS 03

UARTS

1
013,014
DEVICE DATA BUS 00

TBUF WO
~<
0
013,014

Figure 5-34 Transmit Data Register
5-41

013,014

CHAPTER 6
MAINTENANCE

6.1 SCOPE
The DZV11 is maintained by periodically exercising its functions to verify operation, and by replacing
it with another module if it fails. Module-level repair is to be performed with automated test equipment at DIGITAL's repair centers. This chapter focuses on defining the existence of a DZV11 malfunction. If a malfunction is detected, the failing module should be tagged and turned in to the
Logistics Group at the nearest DIGITAL Field Service Branch Office.
6.2 PREVENTIVE MAINTENANCE
There are no adjustments or other special requirements for the DZV 11. Preventive maintenance consists of checking power supply voltages and running the exerciser program. This occurs as part of
normal system maintenance. Similarly, the DZVll option should be included in any cleaning and
inspection effort performed on a system operating in a harsh or dirty environment. In summary, the
preventive maintenance for the DZVll is accomplished by normal system-level preventive maintenance.
6.3

CORRECTIVE MAINTENAN CE

6.3.1 General
The need for corrective maintenance may be recognized by a failure during normal operation or by
errors detected during system maintenance. Ideally, the DEC/XII system exerciser program (MAINDEC-11-DXQLO) will indicate a failure by errors in one of its software modules. Once an error is
detected (by either the operating system or the exerciser), the diagnostic programs are run to further
isolate the failure. If the failure is isolated to a DZV11, the module is replaced. Refer to Chapter 2 for
installation information.
This chapter gives a brief description of the diagnostic programs and test modes. For details refer to
the program listings.
If it should become necessary to troubleshoot the DZVll to the component-part level, consult the

program listing on the use of looping features. By using the program to keep the option in the failing
mode, and by using Chapter 5 and the circuit schematics to locate the related circuitry, a person may
be able to isolate the problem to a failing component. This type of maintenance is not recommended if
module replacement is possible.
6.3.2 Tools, Test Equipment, and Troubleshooting Aids
The minimum requirements for corrective maintenance are the programs listed in Table 6-1 and, if
required by the system hardware configuration, a screwdriver to remove cover panels. The first two
programs can test the DZV 11 using the internal wrap-around feature described in Paragraph 5.4.11.

6-1

Table 6-1
~-~

Program
Code
-~-~~~
~

Diagnostic Programs

- - - - - ------------.

-~~

----~

-----

MAINDEC-II-DVDZA
MAINDEC-II-DVDZB
MAINDEC-II-DVDZC
MAINDEC-II-DVDZD
MAINDEC-II-DZITA

Program
Title

DZVll ASYNC MUX PRT I OF 2
DZVII ASYNC MUX PRT 2 OF 2
DZVII CABLE & ECHO TST
DZVII OVERLAY FOR ITEP
INTERPROCESSOR TEST PROGRAM (ITEP)

--------~--------

More thorough checks can be made by using the H329 and H325 test connectors. The H329 connects
data lines and control signals in a staggered loop-back configuration. This connector plugs into the
Berg header connector on the module, and allows the diagnostic program to check out the entire
board. The H325 test connector plugs into the modem end of the interface cable. It loops back data
lines and control signals without staggering the lines. This allows the program to test both the module
and the cable. These text connectors are illustrated in Figure 1-4 and their part numbers appear in
Table 2-1.
If it is necessary to troubleshoot to the component-part level, an ohmmeter, an oscilloscope, and a
quad extender card are also necessary. Before probing the module, make a thorough visual inspection
for damaged parts or printed circuits.

6.3.3 DEC/Xll Exerciser Program
The DEC/XII system run-time exerciser consists of various software modules configured to run interactively. The exerciser is unique to the system it exercises, and must be reconfigured if options are
added to the system. Unlike the diagnostic programs, which thoroughly test the option in isolation, the
exerciser tests the option's ability to run in the system environment. It does this by performing a
representative sample of the option's functions while also testing other system components.
DZVlls that are shipped as part of systems are already included in the system exerciser. Those shipped
as separate orders are not covered by the system exerciser, and DEC/XII must be reconfigured to
accommodate them. To build DEC/XII, refer to the DEC/XII User's Documentation and Reference
Guide (DEC part number MAINDEC-II-DXQBA).
The DZVII module of DEC/XII is titled, "DZBA DEC/XII DZVII ASYNCHRONOUS MODULE TEST" and is found in the DXQLO library (DEC/XII LSI OPTIONS LIBRARY No.1).

6.3.4

XXDP Diagnostic Programs

6.3.4.1 General- The diagnostic package consists of three stand-alone programs (DVDZA, DVDZB,
and DVDZC) and an overlay for the interprocessor test program (DVDZD). To run the interprocessor
test, it is necessary to first load the ITEP monitor (DZIT A). These programs are available on the
media listed in Table 6-2. Details of the programs may be found in the program listings. This paragraph presents general procedures and information.

6-2

Table 6-2

Multimedia Assignments

Media

Title

Part Number

Paper Tape

DZVll DOCjPT KIT

ZJ251-RB

Floppy Diskette

RXD P #43 LSI #4

AS-C638n*-MC

Disk Packs
(RK05)
(RK05)
(RK06)

CZZZCnn XXDP DIAG PKG3
CVZZDnn LSI-II RKDPI DIAG PKG
CZZRAnn RMDP DIAG PKG

AN-9695n-MC
AN-9696n-MC
AM-C75In-MC

*The n in the titles and part numbers indicates the revision level, and is subject to updating. For example,
CZZZCVO indicates Rev. V, patch 0 of CZZZc. Similarly, AN-9695V-MC indicates Rev. V in the part number.

6.3.4.2 Maintenance Modes - Figure 6-1 illustrates the data paths for the maintenance modes. The
two basic programs (DVDZA and DVDZB) can be run in the internal, staggered, or external modes.
The cable and echo test (DVDZC) can be selected either to loop characters from the program out
through the test connector and back to the program, or else to loop characters from a test console
through the DZVII and back out to the test terminal. The interprocessor test program requires that
another CPU be running the test along with the LSI-ll under test. The other CPU may be a local
system, or a remote system (such as the turnaround system at DIGITAL in Maynard, Massachusetts).
Refer to Figure 6-2. In this test, the two processors communicate to check the hardware from end to
end. It is possible, however, to operate the program with an H325 loopback connector instead of
another processor.
6.3.4.3 Setup Procedures - Running the internal loop back test requires no setup. The loopback function is enabled by CSR bit 03. The staggered loopback test requires that the module header connector
be removed and replaced by a H329 test connector. The preferred method of doing this is to power
down the computer, unplug the DZVII module, and switch from the interface cable to the H329 test
connector. The module is then reinstalled, taking care not to snag the components on anything, and
the computer is powered up.
The external test requires that the far end of the BCII U interface cable be disconnected from the
modem or terminal. Plug the H325 test connector into the modem-end of the cable.
Setup for the cable test also requires an H325, as indicated in Figure 6-1. The echo test requires a
terminal connected to the DZV II. This may require a null modem, depending on the type of terminal.
Setup for the interprocessor test varies depending on the equipment available.
6.3.4.4 Software Switch Register - The LSI-II uses location 176 for a switch register instead of front
panel swtiches. To change the operating parameters, load the program and then use the aDT slash
command to open location 176. Refer to the applicable program listing for a definition of bits. Assemble the corresponding octal number and enter it into location 176. Then start the program at
location 200.

6-3

DZV-ll
INTERNAL

C/')

:J
C!)

•

)
H329

-.:..
C/')

....J

DZVll
STAGGERED

C/')

:J
C!)

)

•

...

H325

'7
C/')

....J

DZVll
EXTERNAL (DVDZA or DVDZB)
or CABLE (DVDZC only)

TEST
TERMINAL

C/')

:J
C!)

'7
C/')

....J

DZVll
ECHO (DVDZC only)
* A NULL MODEM, SUCH AS AN H312, MAY BE NECESSARY,
DEPENDING ON THE TERMINAL USED FOR TEST.

Figure 6-1

Maintenance Mode Data Flow

6-4

MK0177

*(/)
:>
III

...:.

(/)

....J

DZVll

* BOTH PROCESSORS MUST BE RUNNING DZITA.

Figure 6-2

MK-0178

Interprocessor Test (lTEP)

The software switch register may be accessed while the program is running. Type a CONTROL G to
stop the program and open the switch register.
6.3.4.5 Auto-Sizing - The two basic tests (DVDZA and DVDZB) have auto-sizing capabilities, and
may therefore be run without modification of the switch register.
The auto-sizer routine detects all DZVll device and vector addresses within the floating address and
vector area. The values of the other parameters are by default set for 19.2K baud, internalloopback,
and the testing of all four lines. These values are stored in a status table in locations 1500 through 1740
(Table 6-3). They are printed by the console terminal during the test.
6.3.4.6 Parameter Inputs and Dialogue - The DVDZA and DVDZB diagnostics may be run with
parameters specified by the operator. To do this, set bit 00 in the software switch register and then start
the program at location 200. The program responds with a series of questions.
1st CSR ADDRESS (160000:163770):
Answer this question by typing in the address of the DZVll CSR at which you wish testing to begin.
Follow all answers with a carriage return.
1st VECTOR ADDRESS (300:770):
Type the vector of the DZVl1. Note that all the DZVlls must be contiguous for both address and
vector locations.

6-5

Table 6-3

Typical Map of DZVll Status*

Location

Contents

Meaning

1500

160100

CSR address of first DZV II
in system.

1502

000300

Receiver interrupt vector
for first DZVII in system.

1504

000017

TCR bit representation of
active lines to be tested.

1506

017470

LPR bits representing the
following: receiver enabled,
19.2K baud, 8 bits per
character, and 2 stop bits.

1510

O()()()()()

Indicates the selected maintenance mode, where:
00000o = Internal
000200 = External with H325
100000 = Staggered with H329

*This table is an example. Consult the program listing for details.

MAINTENANCE MODE
(EXTERNAL (H325) (E»
(INTERNAL (DZCSR03= I) (I»
(STAGGERED (H329) (S))
Type an E, I, or S, as appropriate. If running external, all selected lines must be terminated by H325
test connectors.

# OF DZVlls (IN OCTAL) (1:20):
Type the total number of DZVlls to be tested.
Other parameters (e.g., baud rate) that are not included in the opening dialogue may be entered via the
software switch register. All extra parameters are assigned to all DZVlls in the system. The program
run time is approximately 1.5 minutes on the first pass and 2.5 minutes on subsequent passes. Run at
least three error-free passes.
Operation of the cable and echo test (DVDZC) always requires an opening dialogue. Special switch
settings, however, are not required for normal operation. Start the program and respond to the questions with an answer followed by a carriage return
VECTOR ADDRESS Type the vector of the DZV II under test.
6-6

CONTROL REGISTER ADDRESS Type the CSR address of the DZVl1 under test.
WHICH TEST? ECHO OR CABLE (E OR C)
Type E or C, as required.
BAUD RATEType one of the following: 50, 75, 110, 135, 150, 300, 600, 1200, 1800, 2000, 2400, 3600, 4800, 7200, or
9600.
LINE Type the number of the line that has the H325 test connector on it. The lines are numbered 0, 1,2,3.
At this point, the test begins.
Cable Test
If the cable test (C) was selected, the system prints:
CABLE TEST
The cable text executes in approximately 15 seconds at 9600 baud. It prints an end-of-pass message
after each pass. To change lines, strike any key on the console terminal while the program is running.
The system responds with:
LINE:
At this point, change the H325 test connector to another line and type the new line number. The
system prints:
CABLE TEST
and continues.
Echo Test
If the echo test (E) is selected when the program asks which test, the subsequent baud rate and line
questions are answered the same way. After the line number is typed, the system prints:
TERMINAL ECHO TEST
on the console terminal, and prints:
THE QUICK BROWN FOX JUMPED OVER THE LAZY DOGS BACK 0123456789
on the DZVll terminal. To have this message printed continuously, type a CONTROL G on the
console terminal while the message is being printed by the DZV 11 terminal. The program prints a
prompt character on the console terminal and waits for a new switch register setting. Set the switch
register to 377 to have the program output on the quick brown fox message continuously.
To return to the normal flow of the diagnostic, type a CONTROL G and change the switch register to
something other than 377.
6-7

The console terminal prints:
TYPE A CHAR. ON OZVII TERMINAL
At this point, any printable character typed on the OZVII terminal is echoed back to that terminal.
If a CONTROL C is typed on the OZVII terminal, the program prints the end-of-pass message on the
console and then resumes with the quick brown fox message on the OZV II terminal.

To change lines, type any printable character on the console terminal. The system prints:
LINE:
and waits for a response. Plug the next line into the OZVII terminal and continue until all the lines
have been tested. Refer to the listing for explanations of error printouts.
6.3.4.7 Functional Description - This paragraph briefly describes the diagnostic programs used with
the OZVII. For a more detailed treatment, refer to the program listings.
DVDZA - This is the first of a 2-part series used for basic option checkout. It exercises the read/write
bits of the registers, performs simple transmission and reception exercises for each line, and verifies the
interrupt capabilities of the option (Table 6-4).

Table 6-4
Test
Number

DVDZA Tests

Functions
Proves the bus reply response during a read or write to the following device registers:
CSR, RBUF, TCR, and MSR.

Proves that bit CLR can be set, and that it will clear by itself.

Verifies that the read/write bits of the CSR can be set. Then verifies that they can be
cleared. Also verifies that after being set again, they can be cleared by a Master Clear.
The bits tested are: MAINT, MSE, SAE, RIE, and TIE.

Tests that all of the TCR bits can be set, cleared, and cleared by a Master Clear. Also
tests that the OTR bits can be set, cleared, and cleared by a RESET.

Verifies that ROaNE, TROY, TLINE B, TLINE A, and SA are read-only. Tests that
TROY is zero until a line is selected and MSE is set.

Tests that the following CSR bits are read-write: TIE, SAE, MSE, and MAINT.
Checks that setting CLR in the CSR will clear these bits.

Performs reset testing. Also tests read-only bits in RBUF and write-only bits in LPR.

6-8

Table 6-4
Test
Number

DVDZA Tests (Cont)

Functions

Performs reset testing. Also tests read-only bits in the MSR and write-only bits in the
TOR.

Verifies that setting OTR causes CO and RI to set under the following circumstances:
l. For the same line if in external mode
2. For the staggered line if in staggered mode.
Lines are staggered as follows: line 0 with line I, line 2 with line 3. This test is run only if
an H325 or H329 is connected to the OZVII under test.

Verifies that TROY is set when a line is ready to be loaded. Verifies that the line
specified by TUNE A and TUNE B in the CSR corresponds to the line selected in the
TCR.

Transmits one character and receives one character on one line at a time. The character
is 252. All selected lines will be turned on. This is the first time any data is checked in
the receiver. Using switch 09 with this test establishes a tight scope loop that transmits
a steady stream of characters.

Clears RX ENAB in the LPR for each line to verify that each receiving line can be
disabled. This test also verifies that the silo can be emptied by setting CLR in the CSR.

Proves that the transmitter transmits characters and the receiver receives characters.
One line at a time is tested, based upon valid lines. This is the first point at which all
data is tested.

Exercises one line at a time to prove that:
I. The transmitter BRK bit works.
2. The receiver can flag framing errors.
3. The receiver can flag parity errors.

17.

Verifies that the OZV II does not interrupt while the processor status does not allow
interrupts. Also checks that the OZVII can interrupt when the processor status does
allow interrupts.
.

Verifies that the receiver interrupts before the transmitter, even when the transmitter
was enabled first.

DVDZB - This program is the second of the two basic option diagnostics. It exercises the transmitters
and receivers in all possible operating modes and at all possible data rates. Error conditions are induced and the option is checked for the ability to recognize these errors (Table 6-5).

6-9

Table 6-5

DVDZB Tests

Verifies OVRN ERR and SA one line at a time, based upon valid lines. As each of the
first 16 characters are sent, Silo Alarm is tested to be cleared. On the 16th character, the
program tests for Silo Alarm to set. Then the entire silo is filled and an overrrun error is
expected on the 65th character.
Using switch 09 for this test sends 20 characters on the line previously selected. This
occurs continuously while SW09 = 1.
2

Tests that SAE inhibits interrupts. Sets RIE and checks that SA causes an interrupt on
the 16th character. Tests all selected lines one at a time.

Interrupt test on the transmitter and receiver. Runs all qualified lines at maximum
speed.

DZVll relative timing test.
Each selected line, one at a time, runs 16 characters at all baud rates, and then the
highest baud rate with all character lengths. Each successive parameter decreases in
time from the previously selected parameter. The time is checked aginst the previous
time. The parameters are:
1. Eight bits per character plus two stop bits at 50, 75, 110, 134.5, 150,300,600,
1200, 1800, 2000, 2400, 3600,4800, 7200, and 9600 baud.
2. Five, six, and seven bits per character with two stop bits and at 19.2K baud.
Each line completes all of the checks before the next line is tested.

Checks parity errors in staggered mode only. All selected lines are enabled simultaneously. Tests for even parity on odd lines and odd parity on even lines. Then it checks
the reverse. The test verifies that PAR ERR can be set.

DVDZC - This program verifies the cable interface connection between the module and the EIA
connector. The diagnostic includes a cable test, an echo test, and a test of modem control signals.
The cable test transmits a binary count pattern via the test connector to the receivers. The data flow is
from the program out through the interface cable to the test connector, and back.
The echo test accepts one character at a time and retransmits that character on the same line. The data
flow is from a test terminal in through the interface cable and DZVll to the program and back out to
the terminal.
The third test verifies that setting DTR for a given line causes CO and RI to set. Jumpers WI, W2, W3,
and W4 must be installed for this test.

6-10

6.3.5 Interprocessor Test (ITEP)
The interprocessor test program (ITEP) verifies the operation of the DZVII by using it in a communications link with another processor. The other processor may be on an LSI-II or PDP-II system at
the same location as the system under test, or it may be in a remote communications test center.
DVDZD is the DZVII overlay of the test program. It must be run along with DZITA-D, the monitor
program.
ITEP has four testing modes. The overlay performs the following functions in the four modes.

Internal Loopback Mode
1.

Establishes the modem connection.

Waits to receive a message terminated by the receive terminating character (001).

Verifies the data against the data selected by SW09 and SWIO (SW07 = 0).

Transmits the data selected by SW09 and SWIO (SW08 = 0), or transmits the received data
(SW08 = I).

Returns to monitor for "END PASS" (SW04 = 1), or goes to step 1 (SW04 = 0).

External Loopback Mode (Full-Duplex Only)
I.
2.
3.
4.
5.
6.

The overlay establishes the modem connection.
Transmits the selected data.
Enables the receiver.
Waits for the message to be received.
Verifies the data (SW07 = 0).
Returns to the monitor for "END PASS" (SW04 = I) or goes to step 1 (SW04 = 0).

One-Way-In Mode
1.
2.
3.
4.
5.

The overlay establishes the modem connection.
Enables the receiver.
Waits for the message to be received.
Verifies the data (SW07 = 0).
Returns to the monitor for "END PASS" (SW04 = 1) or goes to step 1 (SW04 = 0).

One-Way-Out Mode
1.
2.
3.
4.

The overlay establishes the modem connection.
Enables the transmitter.
Transmits the selected data.
Returns to monitor for "END PASS" (SW04 = 1) or goes to step 1 (SW04 = 0).

6-11

6.3.5.1 Starting ITEP- ITEP requires a complete communications loop (Figure 6-2). Ensure that a
loop is established with compatible equipment. The variable parameters must be the same in each of
the two processors. The mode must be one of the options listed in Table 6-6. The system that is to
receive data first should be loaded and started first. If the modem being used on this system has an
automatic answer feature, it should be enabled. The system that is to transmit first should then be
loaded and the connection established. If the LSI -II line clock is to be used, it should be enabled prior
to program execution. The load address is 200. Refer to the program listing for details regarding
restrictions, error messages, and optional selections.

Table 6-6

Valid Mode Combinations

CPU No.1

CPU No.2

One-Way-Out

One-Way-In

One-Way-Out

External Loopback

Internal Loopback

External Loopback

External Loopback
(full-duplex)

External Loopback
(full-duplex with
H325 test connector
on end of modem
cable)

6.3.5.2 Console Dialogue- After the program has been started, the dialogue for input parameters
proceeds as follows.
1.

The program types the name of the overlay, followed by a question mark. Uyou wish to set
up just the indicated overlay, type a carriage return.

The program types the default address of 160010. Type a carriage return if the default
address is correct for the DZVII. If not, type the actual CSR address.

The program types the default vector address of 300 and a question mark. Type a carriage
return to use the defult vector. If using a different vector, type the actual vector.

The program types 200 as the priority setting. For the LSI-II, this indicates that the processor will acknowledge interrupts. For a PDP-II, this indicates priority level 4. Type a carriage return to use this priority. If a different priority is required on a PDP-II, type the
appropriate code (240 for priority level 5, 300 for priority level 6, etc.).

6-12

Next the program types the default value for parameter no. 1 of 011070 and a question
mark. Type a carriage return to use the default value. To select a different value, refer to
Tables 6-7 and 6-8.
NOTE
If any of the values in items 2 through 5 are changed,
the new value becomes the default value for subsequent restarts of the program.

Table 6-7
Bits 0, 1
Bits 3, 4
Bit 5
Bits 6, 7
Bits 8-11
Bit 12

Meaning of Parameter No. 1

Line number being used; default setting is for line o.
Character length; default is 8 bits.
Stop bit count; default is 2 stop bits.
Parity enable and select; default is no parity.
Baud rate select; default is 110 baud.
Receiver on (this should always be set).

Table 6-8

Parameter No. 1 Examples

Value·

Baud Rate

10070
10470
11070
11470
12070
12470
13070
13470
14070
14470
15070
15470
16070
16470
17070

50
75
110

134.5
150
300
600
1200
1800
2000

2400
3600
4800
7200
9600

·These examples set the receiver for line 0, set the
baud rate as listed, and set the format for 8 bits
per character with 2 stop bits and no parity. For
definitions of the other possible settings, refer to
Table 3-4.

6-13

6.3.5.3 Operational Switch Settings - The program instructs the operator to set console switches. On
a PDP-II with front panel switches, set the switches according to Table 6-9. On an LSI-II, modify the
contents of the software switch register (location 176) according to Table 6-9. If no change is desired,
type a carriage return. If an error is made while modifying the software switch register, CONTROL U
allows re-entering the correct value. The contents of the switch register can be changed during program
run time by typing a CONTROL G and then entering a new value.

Table 6-9

Operational Switch Settings

SWI5 = I

Halt on error

SWI4 = 1

Single pass
SWI4 has no effect if SW04 = O.

SW13 = I

Inhibit error typeouts

SWI2 = I

Inhibit all typeouts except errors. If SWI2 = 0 and SW04 = I, END PASS is typed and
transmitted/received data is typed.

SWII = I

Use previously specified data.

SWIO = I

Data select (with SW09)

SW09 = I

Data select (with SWIO)
Get data from operator.
00 = I
01 = I
Test message no.l ($A quick brown fox)
10 = I
Test message no.2 ($B numerics)
II = I
Test message no.3 ($C comtest/quick brown fox/numerics)

SW08 = I

Transmit received data (internalloopback mode).

SW07 = I

Do not test received data.

SW06 = I

Monitor transmitted data on console terminal. *

SW05 = I

Monitor received data on console terminal. *

SW04 = I

Return to monitor for END PASS.
When SW04 = 0, program loops in the overlay, never returning to the monitor.

SW03 = 1

Internal loopback mode

SW02 = I

External loopback mode

SWOI = 1

One-way-in mode

SWOO = I

One-way-out mode

*In many cases, not all the data appears on the console terminal. This is especially true when the communications interface is running at a faster baud rate than the console, but even at equal or slower baud rates, not
all characters may appear on the console.

6-14

When the communication link is established and the dialogue has been completed, start the program
by using the CONTINUE switch (on a PDP-II) or the ODT P command (on an LSI-II).

6.3.5.4 Testing - If one-way-in or internalloopback modes are selected, the program sets Data Terminal Ready and waits for data. If one-way-out or externalloopback modes are selected, the program
sets Data Terminal Ready and then waits for the Carrier bit before attempting to transmit data.
NOTE
For example, to test a line in external loopback
mode with message no. 3, use a switch setting of
3024.

6.3.6 Manual Tests
This paragraph contains several short tests that can be performed using the hardware ODT commands. The examples given here assume that the reader is familiar with the use of ODT and that the
DZVII CSR address is set for 160010. The letter n is used to indicate a number that may vary. For an
explanation of ODT commands, refer to 1977-78 Microcomputer Handbook, Section 2, Chapter 2.

This test verifies that the CLR bit will clear the CSR and the low byte of the TCR.
@ 1600 10/000000 < LF >

Open the CSR

16oo12/0nnnnn <LF>

Open the RBUF.

160014/000000 <LF>

Open the TCR.

160016/000000 <CR>

Open the TDR.

@160010/000000 10050 <LF>

Open CSR; enter bits.

16oo12/Onnnnn <LF>
Open TCR; enter bits.

160014/000000 7417 <LF>
160016/000000 <CR>

Open CSR; set device clear.

@16001O/111450 20 <LF>
16oo12/Onnnnn <LF>
160014/007400 <LF>

Observe that low byte of TCR is cleared.

160016/000000 <CR>

The MSR may contain a value of 007417 if the
H329 is connected.

@1600 10/000000

Observe that CSR is cleared.

6-15

This test makes a basic check of the transmitter scanner. It performs a Master Clear, sets the
TCR bit for line 3, and then verifies that line 3 appears in the CSR. It clears the TCR bit for
line 3 and then checks that the line numbers in the CSR are clear.
@16001O/000000 20 <CR>

Set Master Clear.

@/OOOOOO 50 < LF >

Set MSE and MAINT.

160012/Oonnnn <LF>
Set TCR bit 03.

160014/000000 10 < t >
160012/0nnnnn < t >

Read CSR for TRDY set and Tx line = 3.

160010/101450 <LF>
160012/Oonnnn <LF>

Clear TCR bit 03.

160014/000010 0 < t>
160012/Oonnnn < t >

Read CSR for TRDY and TUNEs cleared.

160010/000050

To perform the same test on line 2, proceed as follows.
Set Master Clear.

@160010/000000 20 <CR>
@

/000000 50 < LF >

Set MSE and MAINT in CSR.

160012/Oonnnn <LF>
Set TCR bit 02.

160014/000000 4 < t >
160012/Oonnnn < t >

Check CSR for TRDY set and Tx line = 2.

160010/101050 <LF>
160012/Oonnnn<LF>

Clear TCR bit 02.

160014/000004 0 < t >
160012/Oonnnn < t >

Check CSR for TRDY and TUNEs cleared.

160010/000050

6-16

To perform the same test 00 lioe 1, proceed as follows.
@16OO1O/000000 20 <CR>

Set Master Clear.

@/OOOOOO 50 <LF>

Set MSE aod MAINT io CSR.

160012/000000 <LF>
160014/000000 2 < t >

Set TCR bit 01.

160012/000000 < t >
160010/100450 <LF>

Check CSR for TROY set aod Tx lioe = 1.

160012/000000 <LF>
160014/000002 0 < t >

Clear TCR bit 01.

160012/000000 < t >
1600 10/000050

Check CSR for TROY aod TUNEs cleared.

To perform the same test 00 lioe 0, proceed as follows.
@16001O/000000 20 <CR>

Set Master Clear.

@/OOOOOO 50 <LF>

set MSE aod MAINT io CSR.

160012/000000 <LF>
160014/000000 1 < t>

Set TCR bit 00.

160012/000000 <t>
160010/100050 <LF>

Check CSR for TROY set aod Tx lioe :;: o.

1600012/000000 <LF>
160014/000001 0 < t >

Clear TCR bit 00.

160012/000000 < t >
160010/000050

Check CSR for TROY aod TUNEs cleared.

6-17

This next test checks that line 3 is the highest priority line when all lines are enabled at once.
It checks that line priority goes from 3 to O.
@ 1600 10 /000000 20 < CR >

Set Master Clear.

@/OOOOOO 50 <LF>

Set MSE and MAINT in CSR.

160012/Onnnnn <LF>
Set TCR bits for lines 3, 2, 1, and o.

160014/000000 17 < t >
160012/Onnnnn < t >

Check CSR for TROY set and Tx line = 3 (highest priority line).

160010/101450 <LF>
160012/Onnnnn <LF>

Clear only TCR bit 3.

160014/000017 7 < t >
160012/0nnnnn < t >

Check CSR for TROY set and Tx line = 2 (next
highest priority).

160010/101050 <LF>
160012/Onnnnn <LF>

Clear TCR bit 02.

1600 14/000007 3 < t >
160012/Onnnnn < t >

Check CSR for TROY set and Tx line = 1 (third
highest priority).

160010/100450 <LF>
160012/Onnnnn <LF>

Clear TCR bit 01.

160014/000003 1 < t >
160012/0nnnnn< t>

Check CSR for TROY set and Tx line = 0 (lowest priority).

160010/100050 <LF>
160012/Onnnnn <LF>

Clear TCR bit 00.

160014/000001 0 < t >
160012/0nnnnn < t>
160010/000050

Check CSR for TROY and TUNEs cleared.

6-18

This test checks the receiver without using the transmitter scanner. The BRK bit is set and
the RBUF is tested to see that it contains an all-zero character and a framing error.
@160010/000000 20 <CR>

Set Master Clear.

@/OOOOOO 50 <LF>

Set MSE and MAINT in CSR.

160012/0nnnnn 17470 <LF>

Load LPR with 19.2K baud, 8-level, 2 stop bits,
and line O.

160014/000000 <LF>
160016/000000 400 <CR>

Set Break bit in TDR for line O.

@160010/000250 <LF>

Read CSR for RDONE set.

160012/120000

Check RBUF for Data Valid and FRAM ERR
set, for RX line = 0, and for all zeros in data
bits.

160010/000050 <LF>

Check CSR for RDONE cleared.

160012/020000

Check RBUF for Data Valid cleared.

To perform the same test on line 1, proceed as follows.
@16001O/000000 20 <CR>

Set Master Clear.

@/OOOOOO 50 <LF>

Set MSE and MAINT in CSR.

160012/0nnnnn 17471 <LF>

Load LPR with 19.2K baud, 8-level, 2 stop bits,
and line I.

160014/000000 <LF>
160016/000000 1000 <CR>

Set Break bit in TD R for line 1.

@16001O/000250 <LF>

Check CSR for RDONE set.

160012/120400

Check RBUF for Data Valid and FRAM ERR
set, for RX line = 1, and for all zeros in data
bits.

160010/000050 <LF>

CheQk CSR for RDONE cleared.

160012/020400

Check RBUF for Data Valid cleared.

6:-19

To perform this test on line 2, proceed as follows.
@160010/000000 20 <CR>

Set Master Clear.

@/OOOOOO 50 <LF>

Set MSE and MAINT in CSR.

160012/0nnnnn 17472 <LF>

Load LPR with 19.2K baud, 8-level, 2 stop bits,
and line 2.

160014/000000 <LF>
160016/000000 2000 <CR>

Set Break bit in TDR for line 2.

@160010/000250 <LF>

Check CSR for RDONE set.

160012/121000 <t>

Check RBUF for Data Valid and FRAM ERR
set, for RX line = 2, and for all zeros in data
bits.

160010/000050 <LF>

Check CSR for RDONE cleared.

160012/021000

Check RBUF for Data Valid cleared.

To perform this test on line 3, proceed as follows.
@16001O/000000 20 <CR>

Set Master Clear.

@/OOOOOO 50 <LF>

Set MSE and MAINT in CSR.

160012/0nnnnn 17473

Load LPR with 19.2K baud, 8-level, 2 stop bits,
and line 3.

160014/000000 <LF>
160016/000000 4000 <CR>

Set Break bit in TDR for line 3.

@16001O/000250 <LF>

Check CSR for RDONE set.

160012/121400 <t>

Check RBUF for Data Valid and FRAM ERR
set, for Rx line = 3, and for all zeros in data bits.

160010/000050 <LF>

Check CSR for RDONE cleared.

160012/021400

Check RBUF for Data Valid cleared.

6-20

This test transmits and receives several characters on line O. It uses 8-level with 2 stop bits at
19.2K baud in maintenance mode.
@160010/000000 20 <CR>

Set Master Clear.

@/OOOOOO 50 <LF>

Set MSE and MAINT in CSR.

160012/0nnnnn 17470

Set LPR bits for 19.2K baud, 8-level, 2 stop bits,
line O.

160014/000000 1

Set TCR bit 00.

160012/0nnnnn 
Check CSR for TROY set and Tx line = O.

160010/100050 <LF>
160012/0nnnnn <LF>
160014/000001 <LF>

Load octal 377 into TOR.

160016/000000 377 
160014/000001 
160012/100377

Check RBUF for Oata Valid set, for OVRN
ERR, FRAM ERR, and PAR ERR clear, for
Rx line = 0, and for the data to be 377.

160010/100050 <LF>

Check CSR for TROY set and ROONE cleared.

160012/000377 <LF>

Check RBUF for Oata Valid cleared.

160014/000001 <LF>
Load octal 252 into TOR.

160016/000000 252 
160014/000001 
160012/100252

Read RBUF for Oata Valid set, the error bits
clear, Rx line = 0, and the data to be 252.

1600 10/100050 < LF>

Check CSR for TROY set and ROONE cleared.

160012/000252 <LF>

Read RBUF for Oata Valid cleared.

160014/000001 <LF>

6-21

Load octal 125 into TOR.

160016/000000 125 
160014/000001 <t>
160012/100125 < t >

Check RBUF for Data Valid set, no error bits
set, Rx line = 0, and the data being 125.

160010/100050 <LF>

Check CSR for TROY set and ROONE cleared.

160012/000125 <LF>

Read RBUF for Data Valid cleared.

160014/000001 <LF>
160016/000000 0< t >

Load a

into TOR.

160014/000001 < t >

160012/100000< t >

Read RBUF for Data Valid set, no errors, Rx
line = 0, and the data bits being Os.

1600 10/100050

Check CSR for TROY set and ROONE cleared.

This test sets the maintenance bit but disables the receivers. It then transmits a character and
checks to see that it is not received.
@16001O/000000 20 <CR>

Set Master Clear.

@/OOOOOO 50

Set MSE and MAINT in CSR.

160012/0nnnnn 7470 <LF>

Load the LPR with RX ENAB cleared.

160014/000000 1< t >

Set TCR bit 00.

160012/0nnnnn 
Check CSR for TROY set and ROONE cleared.

160010/100050 <LF>
160012/0nnnnn <LF>
160014/000001 <LF>

Load 377 into TOR.

160016/000000 377 < t >
160014/000001 < t >
160012/0nnnnn < t >

Check RBUF to see that Data Valid did not set.

1600 10/100050

Check CSR to see that ROONE is clear.

6-22

This test sets line 0 for 5-level code and then attempts to transmit and receive 377. Transmitted bits are masked in the process, and a 37 is received. This proves that the UARTs have
switched to 5-level.
@16001O/000000 20 <CR>

Set Master Clear.

@/OOOOOO 50 <LF>

Set MSE and MAINT in CSR.
Load LPR for 19.2K baud, 5-level, line number

160012/0nnnnn 17400 <LF>

O.
Set TCR bit 00.

160014/000000 1 
160012/0nnnnn

Check CSR for TROY set and line numbers O.

160010/100050 <LF>
160012/0nnnnn <LF>
160014/000001 <LF>

Load 377 into TOR.

160016/000000 377 
160014/000001 
160012/100037

Read RBUF for Oata Valid set, no errors, line
= 0, data 37.

1600 10/100050

Check CSR for TROY set and ROONE cleared.

6-23

APPENDIX A
IC DESCRIPTIONS

A.I

GENERAL

This appendix contains data on the LSI chips used by the DZVll. The other smaller ICs are common,
widely-used logic devices. Detailed specifications on these chips are readily available, and hence are
not included here.
A.2 UART
The UART is a MOS/LSI device packaged in a 4O-pin DIP. It is a complete subsystem that transmits
and receives asynchronous data in duplex or half-duplex operation. The receiver and transmitter can
operate simultaneously. The transmitter accepts parallel binary characters and converts them to a
serial asynchronous output.
The receiver accepts serial asynchronous binary characters and converts them to a parallel output. The
receiver and transmitter clocks are separate and must be 16 times the desired baud rate. The allowable
clock rate is dc to 160 kHz.
Control bits are provided to select: character lengths of 5,6, 7, or 8 bits (excluding parity); odd, even,
or no parity; and 1 or 2 stop bits for 6-, 7-, or 8-bit characters. For 5-bit characters, 1 or 1-1/2 start bits
are used. The format of a typical input/output serial word is shown in Figure A-l.
Both the receiver and transmitter have double character buffering so that at least one complete character is always available. A register is also provided to store control information.

FIRST CHARACTER

-~--------I ~~~~ACTER

DATA DATA DATA DATA DATA DATA DATA DATA
STOP
START
1
2
3
4
5
6
7
8 PARITY 1
MARK(1)U·-T
I
' LSB ,
,
,
,
I
,
, MSB ,
,
SPACE (0)
__ -, _ _ L __ L_-'-_...J __ ..L _ _ .L _ _ .L _ _ .J

r --,--r--r-

--r--r-.--

STOP
DATA
2
START

f__--_

MK 0165

Figure A-I

Format of Typical Serial Character

A block diagram and simplified timing diagram for the UART transmitter are shown in Figure A-2.
The transmitter data buffer (holding) register can be loaded with a character when the TBMT (Transmitter Buffer Empty) line goes high. Loading is accomplished by generating a short negative pulse on
the DS (Data Strobe) line. The positive-going trailing edge of the DS pulse performs the load operation. The character is automatically transferred to the UART transmitter shift register when this
A-I

PARALLEL DATA INPUT
(OB1-DB8)
DATA STROBE (DS)

TRANSMITTER BUFFER
EMPTY (TBMT)

=:x

-~~

-U

'--~~-----~~-~~--

START
STOP START
STOP
ASYNCHRONOUS -~----.,p 1~_D_A_T·_A_J~l / I~-DA-T-A-~I·
SERIAL OUTPUT (So)
END OF CHARACTER
(EOC)

l~________~n~

________~~

TRANSMITTER TIMING DIAGRAM

36
NO. STOP BITS ..::.::.
EVEN PAR. SEL. ~
NO PARITY ~
BITS/CHAR.

~
38

DB8 ~

DB5 2Q.
DB4 ~

PAR
GEN

SERIAL
~ OUTPUT
OUTPUT
LOGIC

:B.

DB6 2.!.
DATA
BUS

134

CONTROL STROBE

DB7

CONTROL
HOLDING
REGISTER

DECODER

END OF

2~ CHARACTER
(EOC)
XMTR
SHIFT
REGISTER

XMTR
HOLDING
REGISTER

DB3 ~
DB2

3!..

DB1 ~
DATA STROBE

LOAD

·f

SHIFT
22

TBMT
F/F

CLOCK INPUT .iQ.

[
TIMING
GENERATOR

MK 0162

Figure A-2

UART Transmitter

A-2

TRANSMITTER
BUFFER
EMPTY

register becomes empty. The desired start, stop and parity bits are added to the data and transmission
begins. One-sixteenth of a bit time before a complete character (included stop bits) has been transmitted, the EOC (End-of-Character) line goes high and remains in this state until transmission of a
new character begins.
A block diagram and simplified timing diagram for the UART receiver are shown in Figure A-3. Serial
asynchronous data is sent to the SI (Serial Input) line. The UART searches for a high-to-Iow (mark-tospace) transition on the SI line. If this transition is detected, the receiver looks for the center of the start
bit as the first sampling point. If this point is low (space), the signal is assumed to be a valid start bit
and sampling continues at the center of the subsequent data and stop bits. The character is assembled
bit by bit in the receiver shift register in accordance with the control signals that determine the number
of data bits and stop bits and the type of parity, if selected. If parity is selected and does not check, the
RPE (Receiver Parity Error) line goes high. If the first stop bit is low, the FER (Framing Error) line
goes high. After the stop bit is sampled, the receiver transfers in parallel the contents of the receiver
shift register into the receiver data buffer (holding) register. The receiver then sets the DA (Received
Data Available) line and transfers the state of the framing error bits to the status holding register.
When the module accepts the receiver output, it drives the RDA (Reset Data Available) line low which
clears the DA line. If this line is not reset before a new character is transferred to the receiver holding
register, the OR (Overrun) line goes high and is held there until the next character is loaded into the
receiver holding register.
Figure A-4 is a pin/signal designation diagram for the UART. The function of each signal is given in
Table A-I. In the function column, the references to high and low signals are with respect to the pins
on the UART.

Table A-I
Pin
Number

UART Signal Functions

Mnemonic

Name

Function

Vee

+5 V

Power Supply

Vgg

-12 V

Power Supply (Later designs do not
use this pin.)

Ground

RDE

Received Data Enable

A logic low on this line places the received data onto the output lines.

5-12

RDI-RD8

Received Data

Eight data out lines that can be wire
ORed. RD8 (pin 5) is the MSB and
RDI (pin 12) is the LSB: When 5, 6,
or 7, bits are low. Character is right
justified into the least significant bits.

PER

Receiver Parity Error

Goes high if the received character
parity does not agree with the selected
parity.

FER

Framing Error

Goes high if the received character has
no valid stop bit.

A-3

Table A-I

DART Signal Functions (Cont)

Overrun

Goes high if the previously received
character is not read (DA line not reset) before the present character is
transferred to the receiver holding register.

SWE

Status Word Enable

When low, places the status word bits
(PE, OR, TMBT, FE, and DA) on the
output lines.

RCP

Receiver Clock

Input for an external clock whose frequency must be 16 times the desired
receiver baud rate.

RDA

Reset Data

When low, resets the received DA
(data available) line.

Received Data

Goes high when an entire character
has been received and transferred to
the receiver holding register.

Serial Input

Input for serial asynchronous data.

External Reset

After power is turned on, this line
should be pulsed high which resets all
registers, sets serial output line high,
sets end-of-character line high, and
sets transmitter buffer empty line
high.

TBMT

Transmitter Buffer
Empty

Goes high when the transmitter data
holding register may be loaded with
another character.

Data Strobe

Pulsed low to load the data bits into
the transmitter data holding register
during the positive-going trailing edge
of the pulse.

EOC

End-of-Character

Goes high each time a full character,
including stop bits, is transmitted. It
remains high until transmission of the
next character starts. This is defined
as the mark (high) to space (low) transition of the start bit. This line remains high when no data is being
transmitted. When full speed transmission occurs, this lead goes high for
1/16 bit time at the end of each character.

A-4

Table A-I

UART Signal Functions (Cont)

Pin
Number

Mnemonic

Name

Function

Serial Output

Output for transmitted character in
serial asynchronous format. A mark is
high and a space is low. Remains high
when no data is being transmitted.

26-33

DBl-DB8

Data Input

Eight parallel data-in lines. PB8 (pin
33) is the MSB and DBI (pin 26) is the
LSB. If 5-, 6-, or 7-bit characters are
selected, the least significant bits are
used.

Control Strobe

When high, places the control bits
(POE, NP, SB, NBl, and NB2) into
the control bits holding register.

No Parity

When high, eliminates the parity bit
from the transmitted and received
character and drives the received Parity Error (PER) line low. As a result,
the receiver does not check parity on
reception and during transmission.
The stop bits immediately follow the
last data bit.

2 SB

Two Stop Bits

Selects the number of stop bits that
immediately follow the parity bit. A
low inserts 1 stop bit. A high inserts
1.5 stop bits for 5-character formats
and 2 stop bits for other character
lengths.

37,38

NB2, NBI

Number of bits per
character
(excluding parity)

Select 5, 6, 7, or 8 data bits per character as follows.
Bits/
Char

NB2

NBI

(37)

(38)

5
6
7

L
L
H
H

L
H
L
H

8
39

POE

Even Parity Select

Selects the type of parity to be added
during transmission and checked during reception. A low selects odd parity
and a high selects even parity.

TCP

Transmitter Clock

Input for an external clock whose frequencey must be 16 times the desired
transmitter baud rate.

----------------

A-5

START

STOP START

ASYNCHRONOUS ---, \ , - - - D A T A l ' ~ DATA ~
SERIAL INPUT (SI)
l.U....-_
~
L.!...L....-_._ _ _

STOP
.

RECEIVED DATA
AVAILABLE (DA)
PARALLEL DATA OUT
(RD1·RD8)
RESET DATA
AVAILABLE (RDA)

U
RECEIVER TIMING DIAGRAM

REC DATA
AVAILABLE

~ ~t_19~
____

OVERRUN

_______

REC
PARITY
ERROR

FRAMING
ERROR

~15~ ~ 1'3_______
__

___

AND GATES

DATA BITS

REC
DATA
ENABLE

---,

f-- -------'--

SERIAL
DATA
INPUT

i
!

~ATA AVAILAB~
CLOCK
INPUT

~___~~_ _~_ _~~F_R_A_M_INGERROR _ _ _MK 0163

PARITY
SELECT

NO
NB2
NBl
PARITY NUMBER OF
BITS/CHARACTER

Figure A-3

UART Receiver

A-6

RESET DATA AVAILABLE
STATUS WORD ENABLE
RECEIVED DATA ENABLE
RECEIVER CLOCK
SERIAL INPUT

17
20

RDA

DA 19

RECEIVE DATA AVAILABLE

SWE

OR 15

OVERRUN

RDE

FER 14

FRAMING ERROR

RCP

PER 13

RECEIVE PARITY ERROR

DB8
DB7
DB6
DATA BIT INPUTS

DB5

RECEIVED DATA BITS

DB4
DB3
DB2
DB1
SERIAL OUTPUT
DATA STROBE

TRANSMITTER CLOCK

40 TCP
XR

TRANSMITTER BUFFER EMPTY
END OF CHARACTER
CS

NB2

NB1

POE

2SB

EXTERNAL RESET--....J
CONTROL STROBE------'

NOTE:
PIN 1= +5V
PIN 2= -12V*
PIN 3= GROUND

NO. OF BITS PER CHAR{_ _ _ _ _ _ _ _- - I
NO PAR ITY _ _ _ _ _ _ _ _ _ _----..J
PARITY S E L E C T - - - - - - - - - - - - - . . . J
TWO STOP BITS---------·~-----....J

MK 0166

*LATER DESIGNS DO NOT REQUIRE -12V.

Figure A-4

UART Chip Pin Designations

A-7

A.3 DCOO3 INTERRUPT CHIP
The interrupt chip is an 18-pin DIP device that provides the circuits to perform an interrupt transaction in a computer system that uses a "pass-the-pulse" type arbitration scheme. The device provides
two interrupt channels labeled A and B, with the A section at a higher priority than the B section. Bus
signals use high-impedance input circuits or high-drive open-collector outputs, which allow the device
to directly attach to the computer system bus. Maximum current required from the Vee supply is 140
rnA.

Figure A-5 is a simplified logic diagram of the DCOO3 Ie. Timing for the interrupt section is shown in
Figure A-6, while Figure A-7 shows the timing for both A and B interrupt sections. Table A-2 describes the signals and pins of the DCOO3 by pin and signal name.

"""~.-'''''''---''''''''''''''''''''''

DC003
17
ROSTA H
15

16
-~

ENA DATA H

ENA ST H

ENA ClK H

BIRO l

07
I'

BIAKI l

BIAKO l

~.-:-~

BINIT l

INITO l

BDIN l

VECTOR H

04
01

13
---~

02
ENB ClK H

VEC ROSTB H

12
ENB DATA H

10
ENB ST H

ROSTB H

MK-0164

Figure A-5

DCOO3 Logic Symbol

A-8

300
MIN,\

300
/MIN

BINITl ~
I

7-351

INITO l ~ I~:----------------------------------------------------
~

I
I

ENA DATA H

ENA ClK H

Fl
--! F
I

30 MIN--:

_LC
________

~I______
~__IL_._._

L -____________________~

~---------------------

ENA ST H

ROSTA H

7-30

I
I

BIRO l

15-65 --: '-_-""';':....JF20-90
I

BDIN l
BIAKI l

35 MIN---...!
I

U
I
I

35MIN--:
:

VECTOR H ___________
10___
45_--+1...,!1:........J1 -:

IL._1_O_-_4_5_______

I
I
I

!....:_ _ _ _

I
I
I

12-55-:

BIAKO l
NOTE:
TIMES ARE IN NANOSECONDS.

Figure A-6

DCOO3 A Section Timing

A-9

I
I

~---------_

I
I
I

b.F 12-55
MK0173

300r-=~~------

BINIT l

__________

_______________________

~MINI300:
PMIN:

I N ITO l

-:::::::J
~O
11-uJ'L:~".1\.
7--35

ENB DATA H

:
I

I'
I

ENB ClK H

30 MIN-j

~----------------------------------~------------

I
I

ENB ST H

BIRO l

7-30--:

'5-65

--l 1:::::.

~-------------------------------------------

I
I

ROSTB H

ENA DATA H

I
I

ENA ClK H

30 MIN

---+i F1L______________________

ENA ST H

ROSTA H

- - - - - - - - - ' ,r

LJ
l::J

B DIN l

I
I

BIAKI l

35 MIN-l

35 MIN-i

I
I

V ECTO R H _________________1_0_-_4_5.l.t=rR--l
: L.1_O_-_4_5_____'_O_-_4_5.',-t18-J
: 10-45
I
I
I

I
I
I

VECROSTB H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _'_5-_65-!-b-=fF=1----1
:
'5-65
NOTE:
TIMES ARE IN NANOSECONDS.

Figure A-7

MK0175

DCOO3 A and B Section Timing

A-lO

Table A-2

DCOO3 Signals

---------.------------~------------------.----------------------------------

Pin
Number

I/O Name

Symbol

Function

Interrupt
Vector Gating
Signal

VECTOR H

This signal gates the appropriate vector address onto the bus and to form
the bus signal BRPL Y L.

Vector
Request B
Signal

VEC RQSTB H

Bus Data In

BDIN L

When asserted, this signal indicates
RQST B service vector address is required. When negated, it indicates
RQST A service vector address is required. VECTOR H is the gating signal for the entire vector address; VEC
RQST B H is normally bit 2 of the address.
THE BDIN signal always precedes a
BIAK signal.

Initialize Out

INITO L

This is the buffered BINIT L signal
used in the device interface for general
initialization.

Bus Initialize

BINIT L

When asserted, this signal brings all
drive lines to their negated state (except INITO L).

Bus Interrupt
Acknowledge

BIAKO L

This signal is the daisy-chained signal
that is passed by all devices not requesting interrupt service (see BIAKI
L). Once passed by a device, it must
remain passed until a new BAIKI L is
generated.

Bus Interrupt
Acknowledge

BIAKI L

This signal is the processor's response
to BIRQ L true. This signal is daisychained such that the first requesting
device blocks the signal propagation
while non-requesting devices pass the
signal on as BIAKO L to the next device in the chain. The leading edge of
BIAKI L causes BIRQ L to be unasserted by the requesting device.

Asynchronous
Bus Interrupt
Request

BIRQ L

The request is generated by a true
RQST signal along with the associated true Interrupt Enable signal. The
request is removed after the acceptance of the BDIN L signal and on the
leading edge of the BAIKI L signal, or
the removal of the associated interrupt enable, or due to the removal of
the associated request signal.
A-ll

Table A-2
Pin
Number

DCOO3 Signals (Cont)

IjOName

Symbol

Function

17
10

Device
Interrupt
Request
Signal

RQSTA H
RQSTB H

When asserted with the enable AjB
flip-flop asserted, this signal causes
the assertion of BIRQ L on the bus.
This signal line normally remains asserted until the request is serviced.

16
11

Interrupt
Enable Status

ENA ST H
ENB ST H

This signal indicates the state of the
interrupt enable AjB internal flip-flop
which is controlled by the signal line
ENAjB DATA H and the ENAjB
CLK H clock line.

15
12

Interrupt
Enable Data

ENA DATA H
ENB DATA

The level on this line, in conjunction
with the ENAjB CLK H signal, determines the state of the internal interrupt enable A flip-flop. The output of
this flip-flop is monitored by the
ENAjB ST H signal.

14
13

Interrupt
Enable Clock

ENA CLK H
ENB CLK H

When asserted (on the positive edge),
interrupt enable AjB flip-flop assumes the state of the ENAjB DATA
H signal line.

A.4 DCOO4 PROTOCOL CHIP
The protocol chip is a 20-pin DIP device that functions as a register selector, providing the signals
necessary to control data flow into and out of up to four word registers (8 bytes). Bus signals can
directly attach to the device because receivers and drivers are provided on the chip. An RC delay
circuit is provided to slow the response of the peripheral interface to data transfer requests. The circuit
is designed such that if tight tolerance is not required, then only an external 1K ± 20 percent resistor is
necessary. External RCs can be added to vary the delay. Maximum current required from the Vee
supply is 120 rnA.
Figure A-8 is a simplified logic diagram of the DCOO4 Ie. Signal timing with respect to different loads
are tabularized in Table A-3 and are shown in Figure A-9. Figure A-IO shows the loading for the test
conditions in Table A-3. Signal and pin definitions for the DCOO4 are presented in Table A-4.

A-12

VECTOR H

VCC

BDAL 2

BDAL1

BDALO

BWTBT L

BSYNC L

ENB H
DCOO4

RXCX H
SEL6 L
SEL4 L

SEL2 L

BDIN L

SELO L

BRPLY L

OUTHB L

BDOUT L

OUTLB L
INWD L

GND
+VCC
0
ENB
LATCH
G

ENB

§-VCC

SYNC

~GND
BDAL2 L 021--~~+1D
02
LATCH
G
0~-+____________~D~A~L~24

DECODER

BOA L1 L 031----+-10
01
LATCH
G
O~-+____________~D~A~L~l~

~--------------------~~OUTHBL

BDALO L 041----+10
00
LATCH

l----------------------@OUTLB L

~--+-----I--l

----~@RXCX H

BDOUT L

---~@2]VECTOR H

BDIN L

0----------------------------------111 I NWD L
MK 0171

Figure A-8

DCOO4 Simplified Logic Diagram

A-13

Table A-3

DC004 Signal Timing versus Output Loading
Output
Being
Negated

Output
Being
Asserted
With Respect To

Test
Condition

Min
(ns)

Max
(ns)

Min
(ns)

Max
(ns)

Figure A-tO
Reference

BSYNCL

Load B
LoadC

15
15 .

35
40

5
'5

25
30

15, 1{j

OUTLB L

BDOUTL

Load B
LoadC

5
5

25
30

5
5

25
30

19,110

OUTHBL

DBOUTL

Load B
LoadC

5
5

25
30

5
5

25
30

19,111

INWDL

BDINL

Load A
Load B

5
5

25
30

5
5

25
30

111,112

BRPLYL
(Load A)

OUTLBL
(Load B)

-10

t[3,114

BRPLY L
(Load A)

OUTHBL
(Load B)

-10

t[3, tl4

BRPLYL
(Load A)

INWDL
(Load B)

-10

t[3, tl4

BRPLYL

VECTORH
(Load A)

t[3, tl4

BRPLYL
(Load A)

OUTLBL
(Load B)

300

400

-10

t[3, tl4

BRPLYL
(Load A)

OUTHBL
(Load B)

300

400

-10

t[3, tl4

BRPLYL
(Load A)

INWDL
(Load B)

300

400

-10

1[3,tI4

BRPLY L
(Load A)

VECTORH

330

430

t[3, tl4

Signal

SELn L
(n = 0,

2,4,6)

Pin 18 Connection
RX = lK ±5%

350 ±5%
15 pF ±5%

Pin 18 Connection
RX = 4.64K ±1%

CX = 220 pF ±1%

A-14

25 MIN\.
BDAL (2,1,0) L

~??~~L..L.L-_~-,---~~~~9l@?~
15 MIN""

ENBHW%[
BSYNC L

,25 MIN

I,, ~~~

I!--,~~~~---.I

SEL (0, 2, 4, 6) L

~T51

-lT6F

BWBTL~

I
I

BDOUT L

15 MIN. -1..----,-1--~\ I-

---j----,_

15 MI N. -:

BDIN L

I
I

OUTHB L
OUTLB L

I
I

FT10
-\1J

T11=1L~~
_____~

F
I

--.I

FT12

--I,!"= 2.4V
T13~ 1::L~_____:~~
-..: T14

I
I

-,I

VECTOR H _~_ _ _ _ _ _ _ _

RX Cx H

I
I

IWD L

BRPLY L

CL_-__~_1----f4---- * ----..j1..__~~

T15--:

I
I
I

r
--.

r=-

\ II

T16

*TlME REQUIRED TO DISCHARGE RX Cx FROM ANY CONDITION ASSERTED = 150ns
NOTE:
MK 0172
TIMES ARE IN NANOSECONDS.

Figure A-9

DCOO4 Timing Diagram

A-IS

Vee

Vee
6m2

280n

FROM
OUT PUT >--If------.()

FROM
OUTPUT ~~----------I

FROM

OUTPUT~DIODEFD777

200O'F

r~PF

=
LOAD B

LOAD A

LOAD C
MK 0176

Figure A-to

DCOO4 Loading Configuration

Table A-4

DCOO4 Pin/Signal Descriptions

Signal

Description

VECTOR H

Vector - This input causes BRPL Y L to be generated
through the delay circuit. Independent of BSYNC Land
ENBH.

2
3
4

BDAL2 L
BDALl L
BDALO L

Bus Data Address Lines - These signals are latched at the
assert edge of BSYNC L. Lines 2 and 1 are decoded for the
select outputs; line 0 is used for byte selection.

BWTBT L

Bus Write/Byte - While the BDOUT L input is asserted,
this signal indicates a byte or word operation: asserted =
byte, unasserted = word. Decoded with BDOUT Land
latched BDALO L to form OUTLB Land OUTHB L.

BSYNC L

Bus Synchronize - At the assert edge of this signal, address
information is trapped in four latches. While unasserted,
disables all outputs except the vector term of BRPL Y L.

BDIN L

Bus Data In - This is a strobing signal to effect a data
input transaction. Generates BRPL Y L through the delay
circuit and INWD L.

BRPLY L

Bus Reply - This signal is generated through an RC delay
by VECTOR H, and strobed by BDIN L or DBOUT L,
and BSYNC L and latched ENB H.

A-16

Table A-4

DCOO4 Pin/Signal Descriptions (Cont)

...--.--.---

-----r------------.,---.---------~-----------~

Signal

Description

BDOUT L

Bus Data Out - This is a strobing signal to effect a data
output transaction. Decoded with BWTBT Land BDALO
to form OUTLB Land OUTHB L. Generates BRPL Y L
through the delay circuit.

INWDL

In Word - Used to gate (read) data from a selected register
onto the data bus. Enabled by BSYNC L and strobed by
BDIN L.

12
13

OUTHB L
OUTLB L

Out Low Byte, Out High Byte - Used to load (write) data
into the lower, higher, or both bytes of a selected register.
Enabled by BSYNC L and decode of BWTBT Land
latched BDALO L, and strobed by BDOUT L.

14
15
16
17

SELO L
SEL2 L
SEL4 L
SEL6 L

Select Lines - One of these four signals is true as a function
of BDAL2 Land BDALl L if ENB H is asserted at the
assert edge of BSYNC L. They indicate that a word register has been selected for a data transaction. These signals
never become asserted except at the assertion of BSYN L
(then only if ENB H is asserted at that time) and, once
asserted, are not negated until BSYNC L is negated.

RXCX

External Resistor Capacitor Node - This node is provided
to vary the delay between the BDIN L, BDOUT L, and
VECTOR H inputs and BRPLY L output. The external
resistor should be tied to Vee and the capacitor to ground.
As an output, it is the logical inversion of BRPL Y L.

ENBH

Enable - This signal is latched at the asserted edge of
BSYNC L and is used to enable the select outputs and the
address term of BRPL Y L.

A.5 DCOO5 BUS TRANSCEIVER CHIP
The 4-bit transceiver is a 20-pin DIP, low-power Schottky device for primary use in peripheral device
interfaces, functioning as a bidirectional buffer between a data bus and peripheral device logic. In
addition to the isolation function, the device also provides a comparison circuit for address selection
and a constant generator, useful for interrupt vector addresses. The bus I/O port provides high-impedance inputs and high-drive (70 rnA) open-collector outputs to allow direct connection to a computer's
data bus. On the peripheral device side, a bidirectional port is also provided, with standard TTL inputs
and 20 rnA tri-state drivers. Data on this port is the logical inversion of the data on the bus side.

A-17

Three address jumper inputs are used to compare against three bus inputs and to generate the signal
MATCH. The MATCH output is open-collector, which allows the output of several transceivers to be
wire-ANDed to form a composite address match signal. The address jumpers can also be put into a
third logical state that disconnects that jumper from the address match, allowing for "don't care"
address bits. In addition to the three address jumper inputs, a fourth high-impedance input line is used
to enable/disable the MATCH output.
Three vector jumper inputs are used to generate a constant that can be passed to the computer bus.
The three inputs directly drive three of the bus lines, overriding the action of the control lines.
Two control signals are decoded to give three operational states: receiver data, transmit data, and
disable.
Maximum current required from the Vee supply is 100 rnA.
Figure A-II is a simplified logic diagram of the DCOO5 Ie. Timing for the various functions is shown
in Figure A-12. Signal and pin definitions for the DCOO5 are presented in Table A-5.

Table A-5

DCOO5 Pin/Signal Descriptions

Name

Function

12
11

BUS 0 L
BUS I L
BUS 2 L
BUS 3 L

Bus Data - This set of four lines constitutes the bus side of
the transceiver. Open-collector outputs; high-impedance
inputs. Low = 1.

DATO H
DAT 1 H
DAT2 H
DAT 3 H

Peripheral Device Data - These four tri-state lines carry
the inverted received data from BUS (3:0) when the transceiver is in the receive mode. When in transmit data mode,
the data carried on these lines is passed inverted to BUS
(3:0). When in the disabled mode, these lines go open (hiZ). High = 1.

14
15
16

JV 1 H
JV 2 H
JV 3 H

Vector Jumpers - These inputs, with internal pull-down
resistors, directly drive BUS (3: 1). A low or open on the
jumper pin causes an open condtion on the corresponding
BUS pin if XMIT H is low. A high causes a one (low) to be
transmitted on the BUS pin. Note that BUS 0 L is not
controlled by any jumper input.

MENBL

Match Enable - A low on this line enables the MATCH
output. A high forces MATCH low, overriding the match
circuit.

MATCH H

Address Match - When BUS (3:1) matches with the state
of JA (3:1) and MENB L is low, this output is open; otherwise, it is low.

8
18
17
7

A-18

Table A-5

DCOO5 Pin/Signal Descriptions (Cont)

Name

Function

1
2
19

JA 1 L
JA 2 L
JA 3 L

Address Jumpers - A strap to ground on these inputs allows a match to occur with a one (low) on the corresponding BUS line; an open allows a match with a zero (high); a
strap to Vee disconnects the corresponding address bit
from the comparison.

XMITH

Control Inputs - These lines control the operational of the
transceiver as follows.

RECH

REC XMIT

o
o
1
1

o
1
o
1

DISABLE: BUS and DA T open
XMIT DATA: DATto BUS
RECEIVE: BUS to DAT
RECEIVE: BUSto DAT

To avoid tri-state overlap conditions, an internal circuit
delays the change of modes between XMIT DATA mode,
and delays tri-state drivers on the DA T lines from enabling. This action is independent of the DISABLE mode.

A-19

DC005 TRANSCEIVER

BUSO

1
JA1 L
JA2 L 2
MATCH H 3
REC H 4
XMIT H 5
DAT3 H 6
DAT2 H 7
BUS3 L 8
BUS2 L 9
GND
10

20VCC
19 JA3 L
18 DATO H
17 DAT1 H
16 JV3 H
15 JV2 H
14 JV1 H
13 MENB L
12 BUSO L
11 BUS1 L

L
H

BUS1

JA1

l-lrn

-=-

BUS2

JV2

[QID-=-

JA2

DAT3

JA3
~~-------------+--~03

L----\--J

MENB
XMIT

REC

MK·0170

[2Q]- VCC

Figure A-II

[IQ}- GND

DCOO5 Simplified Logic Diagram
A-20

MATCH H

TRANSMIT DATA TO BUS
XMIT H _

~~~___

J------1

BUS L - OUTPUT - - - - - - DAT H - INPUT

=:J

I- 5 TO 30 ns

-I

REC H (GROUND) _ _

J -

~--~

I-

-l

5 TO 25 ns -f
~

L_----1

I- 5 TO 25 ns

L=:_

RECEIVE DATA FROM BUS (BUS INITIALLY HIGH)
XMIT H (GROUND)

lL..._~__
-f
f- 0 TO 30 ns

RECH ~_~~_~
-..j
0 TO 30 ns
DAT H - OUTPUT
~-~_I

I-

-I

BUS L - INPUT _ _ ~-------L

I- 8 TO 30 ns

___----1-L_--

RECEIVE DATA- FROM BUS (BUS INITIALLY LOW).
XMIT H (GROUND)
REC H

~~J

-l
DAT H - OUTPUT
BUS L -INPUT

~~
1-0 TO 30 ns

J-~

~~~_

-I

I- 8 TO=--=:;30::.:n~s_ _ _

-l

s---

1-0 TO 30 ns
--r_'

L-_

VECTOR TRANSFER TO BUS
JV H

___.r----

lL...--,____

-.J

-----.---.J-L-,-f- 20 ns MAX
!

BUS L - OUTPUT

._ _ __

I- 20 ns MAX

..J

ADDRESS DECODING

-----~--~--------___-.J.....L-._ ~I-l 0 TO 40 ns

BUS L - INPUT

MATCH H _ _~_ _ _

_ _ _-1_

MENB L

-x==.__-l --+-I--I-

___

I- 5 TO 40 ns

-.-J

10 TO 40 ns

RECEIVE MODE LOGIC DELAY

r=------

XMIT H
REC H

--~
-l

DAT (3:0) H (OUTPUT)

1-40T090ns._____________

[

-~-

MK0174

Figure A-12

DCOO5 Timing Diagram
A-21

A.6 COM 5016 DUAL BAUD RATE GENERATOR
The 5016 is an LSI MaS device containing two independent sections. Each section divides its input
clock frequency by one of 16 divisors to produce one of 16 different clock outputs. The divisors are
stored in ROMs on the chip. The ROMs are addressed by circuits that latch in and decode the logical
states of the address lines (Figure A-l3). The address lines may be strobed or held at a dc level. Table
A-6lists the frequencies selected by the address lines. Figure A-14 depicts the 5016 pin locations. Table
A-7 defines their functions.
A.7 3341 FIFO SERIAL MEMORY
The 3341 first-injfirst-out memory chip asserts Input Ready when it is ready to load data. Each time
Shift In is asserted, the chip accepts 4 bits of parallel data and shifts them to the output end of a 64- X
4-bit register. It then asserts Output Ready. When Shift Out is asserted, the chip places the data in the
output latches (Figure A-IS).

STT ----=------,
TA
TB

LATCH
AND
DECODE
CIRCUITS

I
I

CLOCK

-II=-

STR

ROM

CLOCK--~I~----------------------.1.---0-1V-I-O-E-R--'r-;;-- fR

RB----=-...
RC

I
I

Figure A-l3

LATCH
AND
DECODE
CIRCUITS

ROM

COM 5016 Simplified Block Diagram

A-22

Table A-6

COM 5016 Selectable Frequencies

Transmit/Receive Address

Baud
Rate

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19800

Frequency
16XCIock
(kHz)

Divisor

0.8
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8

6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16

Crystal Frequency = 5.0688 MHz

CLOCK

VCC

RB-

RC-

STT

STR

GNO

VOO

NC
MK~0185

Figure A-14

COM 5016 Pin Locations
A-23

Table A-7
Pin
Number

COM 5016 Pin Functions

Mnemonic

Name

Function

CLOCK
(XTALjEXTI)

External Clock Input

This input is either one pin of a crystal
oscillator package or one polarity of
another external input.

Vee

Power Supply

+5 V supply

Receiver Output
Frequency

This output runs at the frequency selected by the receiver address.

4-7

RA,R B

Receiver Address

The logic levels on these inputs select
the receiver output frequency, fRo

STR

Strobe-Receiver
Address

A high-level input strobe loads the receiver address (RA, RB, Re, RD) into
the latch and decode circuits. This input may be strobed or hard-wired to a
high level.

V DD

Power Supply

+ 12 V supply

No Connection

GND

Ground

STT

Strobe-Transmitter
Address

A high-level input strobe loads the
transmitter address (TA' TB, Te, TD)
into the latch and decode circuits.
This input may be strobed or hardwired to a high level.

13-16

TD, TC, TB, TA

Transmitter Address

The logic levels on these inputs select
the transmitter output frequency, fT.

Transmitter Output
Frequency

This output runs at the frequency selected by the transmitter address.

CLOCK
(XTALjEXT2)

Inverted External
Clock Input

This input is either one pin of a crystal
oscillator package or one polarity of
another external input.
-

A-24

LOGIC BLOCK DIAGRAM
13
DO

00
12

FIFO
INPUT
STAGE

01
02

FIFO
OUTPUT 11
STAGE
10

64 WORD x 4 BIT
MAIN REGISTER

7
03-

OUTPUT
CONTROL
LOGIC

SHIFT IN

MASTER RESET

PIN CONFIGURATION
(TOP VIEW)

LOGIC SYMBOL
INPUT
READY

SHIFT
OUT

SHIFT IN

OUTPUT
READY

VGG
INPUT READY
SHIFT IN
DO

3341
4

15
- SHIFT OUT
14
OUTPUT READY

VSS = PIN 16
VDD = PIN 8
VGG = PIN 1

02
03

INPUT READY

°0

°2

03
03
MASTER RESET

VSS
SHIFT OUT
OUTPUT READY
00

VDD

MK 0167

9
VSS=PIN16+5V
VDD = PIN 8 GND
VGG = PIN 1 -12V

Figure A-15

3341 FIFO Serial Memory

A-25

APPENDIX B
CONNECTOR PINNING

Table B-1 lists the DZVII header connector pinning. Table B-2 lists the edge connector pinning (Figure B-1). Table B-1 also lists the pinning of the BCII U interface cable, and the color of the wires. Note
that the wiring sequence does not simply repeat itself for each of the four cable connectors. Instead, the
sequence appears twice and then its mirror image is repeated twice. The header connector is wired this
way to prevent damage to the EIA transmitters and receivers in the event that the connector is reversed. Reversing the connector, however, reverses the line numbers. Observe the "This Side Up"
sticker on the connector.

EDGE
CONNECTOR
HEADER
CONNECTOR

Figure B-1

Connectors

B-1

Connector Pinning

Table B-1
---~-~-

EIA Signal Description
-~-~-

I._~ad.r

(Berg)
Connector
Pin

BCllucab~ . W.

I--- Connector Pin

Ire
Color
----~-

Ground

Black

Transmitted Data 00

Brown

Received Data 00

Gray

Data Terminal Ready 00

White

Ring 00

Green

Forced Busy 00

Yellow

Request to Send 00

Blue

Orange

Ground

Violet

Carrier 00

Red

Ground

Transmitted Data 01

Brown

Received Data 01

Gray

Data Terminal Ready 01

White

RingOI

Green

Forced Busy 0 1

Yellow

Request to Send 01

U
V

4
5

Blue
Orange

Ground

Violet

Carrier 01

Red

B-2

Black

Table B-1

Connector Pinning (Cont)
BCIIU Cable
Connector Pin

EIA Signal Description

Header
(Berg)
Connector
Pin

Wire
Color

Carrier 02

Red

Ground

7
5

Violet
Orange

Request to Send 02

Blue

Forced Busy 02

Yellow

Ring 02

Green

Data Terminal Ready 02

White

Received Data 02

Gray

Transmitted Data 02

Brown

Ground

Black

Carrier 03

Red

Ground

LL
MM

7
5

Violet
Orange

Request to Send 03

Blue

Forced Busy 03

Yellow

Ring03

Green

Data Terminal Ready 03

White

Received Data 03

Gray

Transmitted Data 03

Brown

Ground

Black

B-3

Table B-2

DZVll Edge Connector Pinning

Mnemonic

AA2
BA2
BVI
CA2
DA2
BD2
AP2
AU2
AV2
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2

BDALl4L
BDALl5 L
BDINL
BDOUTL
BIAKI L
BIAKO L
BINIT L
BDMGIL
BDMGOL
BIRQL
BRPLYL
BSYNCL
BDCOKH
GND
GND
GND
GND
WlO

BU2
BV2
AH2
AE2
AM2
AN2
AT2
AR2
AS2
AL2
AF2
AJ2
BAI
AC2
ATI
BC2
BTl
CR2
CS2
CM2
CN2

+12
BBS7L
BDALOL
BDALl L
BDAL2 L
BDAL3 L
BDAL4L
BDAL5L
BDAL6L
BDAL7L
BDAL8L
BDAL9L
BDALlOL
BDALll L
BDALl2 L
BDALl3 L

Wll

B-4

APPENDIX C

GLOSSARY

BBS7 L - Bussed Bank 7 Select (Table 5-1).
BDALOO L through BDALl5 L - Bussed Datal Address Lines (Table 5-1).
BDIN L - Bussed Data Input (Table 5-1).
BDOUT L - Bussed Data Out (Table 5-1).
BIAKI L - Bussed Interrupt Acknowledge In (Table 5-1).
BIAKO L - Bussed Interrupt Acknowledge Out (Table 5-1).
BINIT L - Bussed Initialize (Table 5-1).
BIRQ L - Bussed Interrupt Request (Table 5-1).
Break - A continuous spacing condition on the serial data line, interpreted as a framing error.
BRK 3 through BRK 0 - TDR bits 11 through 08. When set, the Break bit causes the transmission of a
Break signal.
BRPL Y L - Bussed Reply (Table 5-1).
BSYNC L - Bussed Sync (Table 5-1).
BWTBT L - Bussed Write Byte (Table 5-1).
Carrier - A carrier is a continuous frequency capable of being modulated or impressed with a signal.
The name Carrier, however, is used in the DZVll print set to refer to the received line signal detector
input from the modem. This signal is referred to as "Carrier Detect" and "Carrier On" in some books.
CCITT - The Consultive Committee International Telegraph and Telephone is an advisory committee
established under the United Nations to recommend worldwide standards.
CHAR LGTH A, CHAR LGTH B - LPR bits 03 and 04. These bits determine the length of the
characters the DZVll receives and transmits (Table 3-4).
CLR - CSR bit 04. Controls the device Master Clear signal (Table 3-2).
CO - Carrier On. Also referred to as "Carrier" or "Carrier Detect." Some sources abbreviate Carrier
Detect to CD. Do not confuse CD or CO with EIA signal CD. EIA signal CD is Data Terminal
Ready. The EIA signal designation for Carrier On (or Carrier Detect) is CF.
C-I

C03 through COO- MSR bits 11 through 08, representing the Carrier signal for lines 03 through 00.
CONTROL STROBE H - This signal is generated by the speed and format control circuits on circuit
schematic sheet D8. It loads the speed parameters into the baud rate generators on sheet D8, and loads
the data format parameters into the UARTs on sheets D13 and D14.
CSR - Control and Status Register (Table 3-2).
DAOO through DA03 - Data Available. These signals come from the R DONE pins on the UARTs
(sheets D13 and DI4).
DA T A IN 00 H through DATA IN 03 H - These signals are the received data from the EIA signal
lines. They originate at the EIA/TTL receivers (sheet D7) and go to the maintenance mode data
selector (sheet D 10).
DAT A TERM RDY 00 through DATA TERM RDY 03 - Data Terminal Ready signals for lines 00
through 03 (sheet D6). Refer to Table 5-2.
Data Valid - Bit 15 in the RBUF. The Output Ready signals from the four silo memory chips are
ANDed to form RECEIVER DONE H. When the RBUF is addressed, RECEIVER DONE H is
latched as VALID DATA H (sheet DI2). VALID DATA H becomes Data Valid (bit 15) in the
RBUF.
DATI - Data input bus cycle.
DATIO - Data input/output bus cycle.
DATIOB - Data input/output bus cycle involving a byte.
DATO - Data output bus cycle involving a word.
DATOB - Data output bus cycle involving a byte.
DCE - Data communication equipment.
DEVICE DATA BUS - The bidirectional tri-state bus internal to the module; signal lines DEVICE
DATA BUS 00 through DEVICE DATA BUS 15.
DEVICE SELECT H - This signal is the wired-AND of the MATCH signals from all four bus transceiver chips (sheet D2). It enables the protocol chip (sheet D4).
DTE - Data terminal equipment.
DTR - Data Terminal Ready. Refer to Table 5-2.
DTRO through DTR3 - Bits 08 through II in the transmitter control register. They represent the state
of Data Terminal Ready for each of the four lines.
EIA - Electronic Industries Association.
FB - Forced Busy. Refer to Table 5-2.
FEOO through FE 03 - Framing Error signals from the UARTs (sheets D13 and DI4).

C-2

FIFO - First-In/First-Out.
Forced Busy - Used with some modem equipment such as Bell models 103E and 113B. Signals a
modem controller to switch to another channel.
FRAM ERR - Framing Error; RBUF bit 13.
Framing Error - This error occurs when a UART receiver does not detect a stop bit at the time it tests
for one. This may be caused by a transmission error or by a Break signal.
INITIALIZE H, INITIALIZE L - These are the device initialization signals. They are generated by
either the CLR bit (CSR bit 04) or by BINIT from the LSI-II bus (sheet 05).
LO BREAK REGISTER H - Load pulse for the high byte of the transmit data register. (sheets 04
and 010).
LO CSR HIGH BYTE H - Load pulse for the high byte of the control and status register (sheet 04).
LO CSR LOW BYTE H - Load pulse for the low byte ofthe control and status register (sheet 04).
LO LPR REGISTER L - Load pulse for the line parameter register (sheets 04 and 08).
LO TCR HIGH BYTE H - Load pulse for the high byte of the transmit control register (sheet 04).
LO TCR LOW BYTE H - Load pulse for the low byte of the transmit control register (sheet 04).
LO TOR REGISTER H - Load pulse for the low byte of the transmit data register (sheet 04).
LINE A, LINE B - Bits 00 and 01 of the line parameter register. This is a 2-bit code that specifies the
number of the line to which the parameters apply.
LINE ENABO through LINE ENAB3 - Bits 00 through 03 in the transmit control register. Each of
these bits enables transmission on the corresponding line.
LOAD IN PROGRESS L - Indicates that either the line parameter register or the transmit data
register is being loaded. BRPL Y is delayed 300 ns while a load is in progress for either of these two
registers (sheet 04).
LOAD SILO H - Enables silo buffers to load data (sheets 011 and 012).
LPR - Line parameter register. Refer to Table 3-4.
MAINT - Maintenance bit (CSR bit 03). Enables the internal loop-back maintenance mode.
MAINTENANCE H - This signal is set by the MAINT bit (sheet 05) and controls the maintenance
mode data selector (sheet 010).
MASTER CLEAR H - This signal is derived from the clear bit CLR (CSR bit 04). See sheet 05.
MASTER SCAN CLOCK H - This signal is produced by dividing the master oscillator clock signal
(sheet 08). It drives the receiver scanner (sheet 011).
MASTER SCAN ENABLE H - Set by the MSE bit. Enables both transmitter and receiver control
circuitry (sheets 05, 09, 011).

C-3

MASTER SCAN ENABLE L - Set by the MSE bit. Enables the master scan clock (sheets D5 and
D8).
MSE - Master Scan Enable. CSR bit 05.
MSR - Modem Status Register. Refer to Paragraph 3.2.5.
ODD PAR - Odd Parity. Line parameter register bit 07. Refer to Table 3-4.
OR 00 through OR 03 - Overrun error signals from UARTs (sheets D13 and D14) to silo buffer (sheet
DI2).
OUT HB - Output high byte. Indicates that an output data transfer will be made to the high byte of
the selected register (sheet D4).
OUT LB - Output low byte. Indicates that an output data transfer will be made to the low byte of the
selected register (sheet D4).
OVRN ERR - Overrun Error. RBUF bit 14. Refer to Table 3-3.
PAR ENAB - Parity Enable. Line parameter register bit 06. Refer to Table 3-4.
PAR ERR - Parity Error. RBUF bit 12. Refer to Table 3-3.
PE 00 through PE 03 - Parity error signals from the UARTs (sheets D13 and D14) to silo the buffer
(sheet 12).
PSW - Processor Status Word.
QBUS - LSI-11 Bus.
RBUF - Receiver Buffer. Refer to Table 3-3.
RBUF DO through RBUF D7 - Received data bits. RBUF bits 0 through 7.
RCV CLOCK 00 H through RCV CLOCK 03 H - Receiver clocks from the baud rate generators
(sheet D8) to the UARTs (sheets D13 and DI4).
RCV DATA 00 through RCV DATA 03 - Received data bits from the silo buffer (sheet D12) to the
mUltiplexers (sheet D3).
RCV DATA ENABLE 00 through RCV DATA ENABLE 03 - These signals enable the UARTs for
the selected lines. They originate in the receiver control circuitry (sheet D 11) and go to the U ARTs
(sheets D13 and DI4).
RDI through RD8 - Received data bits from the UARTs (sheets D13 and D14) to the silo buffer
(sheet D 12).
RDONE - Receiver Done. CSR bit 07. Refer to Table 3-2.
READ DEVICE H and READ L - These signals control the operating mode of the bus transceivers
(sheets D2 and D4).
READ RCV BUFFER H - This signal controls the unloading of the silo buffer (sheets D4 and DI2).
C-4

RECEIVER DONE H - In the OZVll, this signal does not come from the UARTs. It is the result of
anding the Output Ready signals from each of the four FIFO memory chips (sheet 12). It sets the
ROONE bit in the CSR (sheet 03) to indicate that a character of received data is ready in the silo
buffer.
RECEIVER INTR ENABL - Receiver Interrupt Enable (sheet 05).
RESET OAOO through OA03 - These signals are made up in the receiver control circuitry (sheet 011)
to reset the Data Available signals in the UART (sheets 013 and 014) for the selected line.
Rl - Ring Indicator.
RIO through RI3 - Modem status register bits 0 through 3, indicating the states of the Ring signal on
the corresponding lines.
RIE - Receiver Interrupt Enable. CSR bit 06. Refer to Table 3-2.
RING 00 through RING 03 - The Ring Indicator signals for lines 0 through 3, after having been
converted from EIA to TTL levels (sheet 07).
RO - Read-Only.
RTS - Request to Send. Refer to Table 5-2.
RW - Read/Write.
RX ENAB - Receiver Enable. Line parameter register bit 12. Refer to Table 3-4.
RX LINE A, RX LINE B - Receiver Line A and B, respectively. RBUF bits 08 and 09. Refer to Table
3-3.
SA - Silo Alarm. CSR bit 13. Refer to Table 3-2.
SAE - Silo Alarm Enable. CSR bit 12. Refer to Table 3-2.
SEL 0 - Select line for device register 0 (the CSR). See sheet 04.
SEL 2 - Select line for device register 2. For an input (read) operation, this is the RBUF. For an output
(write) operation, this is the LPR. See sheet 04.
SEL 4 - Select line for device register 4 (the TCR). See sheet 04.
SEL 6 - Select line for device register 6. For an input (read) operation, this is the MSR. For an output
(write) operation, this is the TOR. See sheet 04.
SERIAL INOO H through SERIAL IN03 H - Serial input data from each of the four lines. It is called
Data In between the receivers (sheet 07) and the maintenance mode data selector (sheet 0 to). From
there to the UARTs (sheets 013 and 014), it is called Serial In.
SERIAL OUTOO through SERIAL OUT03 - Serial data out of the UARTs (sheets 013 and 014). It
goes to the EIA drivers and the maintenance mode data selector (sheet 0 to).
SILO - This term refers to a buffer that automatically shifts data from its input end to its output end.
When a silo is loaded, the data does not queue up from the input end toward the output end, as in a
shift register. Instead, it stacks up at the output end, and is immediately available for unloading.
C-5

SILO ALARM H - This signal is the output of a latch that is set when 16 characters have entered the
silo (sheet 0 II). It is cleared by either reading the RBUF or clearing the Silo Alarm Enable bit in the
CSR.
SILO LOAD REQUEST H - This signal is asserted when the Data Available signal for the selected
line is set and the In Ready signals from the silo buffer chips are set. See sheet 012.
SPEED CODE A through SPEED CODE 0 - Bits 08 through 11 of the line parameter register. Refer
to Table 3-4.
STOP CODE - Bit 05 of the line parameter register. Refer to Table 3-4.
TBMT - Transmitter Buffer Empty.
TBMTOO through TMBT03 - These are Transmitter Ready signals from the UARTs (sheets 013 and
014) to the transmitter control circuitry (sheet 09).
TBUFO through TBUF7 - Transmit data bits; bits 0 through 7 of the TOR.
TCR - Transmitter control register. Refer to Paragraph 3.2.4.
TOR - Transmit data register. Refer to Paragraph 3.2.6.
THRLOO L through THRL03 L - Transmitter Holding Register Load signal for lines 0 through 3.
From the transmitter control circuitry (sheet 09) to the UARTs (sheets l3 and 14).
TIE - Transmitter Interrupt Enable. CSR bit 14. Refer to Table 3-2.
TUNE A, TUNE B - CSR bits 08 and 09. Indicate which line is selected for transmission. Refer to
Table 3-2.
TRAN INTR ENBL H - Transmitter Interrupt Enable signal (sheet 05).
TRANSMITTER READY H - This signal indicates that a line has been selected and that the corresponding UART transmitter is ready to be loaded.
TROY - Transmitter Ready. CSR bit 15. Refer to Table 3-2.
TTL - Transistor-Transistor Logic. The normal logic levels are approximately 4 V for one state and 0
V for the other.
TX CLOCK 00 H through TX CLOCK 03 H - Transmitter clocks for lines 0 through 3. They come
from the baud rate generators (sheet 08) and go to the UARTs (sheets 013 and 014).
UART - Universal Asynchronous Receiver/Transmitter. Refer to Appendix A.
UNLOAD SILO H - The unload signal to the Shift Out pin on the silo buffer memory chips.
VECTOR BIT 02 - Bit 02 of the vector term. This determines whether the computer uses a receiver
interrupt service routine or a transmitter interrupt service routine. See sheets 05 and 02.
VECTOR-TO-BUS H - This signal asserts the vector selected by the switch pack at E2 (sheet 05). It
also goes to the protocol chip (sheet 04) to cause assertion of BRPLY.
XMIT DATA 00 through XMIT DATA 03 - Transmitted data leaving the EIA drivers.
C-6

DZVll ASYNCHRONOUS MULTIPLEXER
TECHNICAL MANUAL
EK-DZVII-TM-OOI

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