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EK-DZQ11-UG-001

August 1984

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Document:	DZQ11 Asynchronous Multiplexer User's Guide
Order Number:	EK-DZQ11-UG
Revision:	001
Pages:	39
Original Filename:	http://bitsavers.org/pdf/dec/qbus/EK-DZQ11-UG-001_DZQ11_Users_Guide_Aug84.pdf

OCR Text

EK-OZQ11-UG-001

DZQ11 Asynchronous
Multiplexer
User's Guide

Prepared by Educational Services
of
Digital Equipment Corporation

First Edition, August 1984

The information in this document is subject to change without
notice. Digital Equipment CotpOration assumes no responsibility
for any errors herein.
Printed in U.S.A.
The following are trademarks of Digital Equipment Corporation.

mamaamo™
DEC
DECmate
DECUS
DECwriter
DIBOL
MASSBUS

PDP

P/OS
Professional
Rainbow
RSTS
RSX

RT
UNIBUS
VAX
VMS
VT
Work Processor

CONTENTS
Page

CHAPTER 1

GENERAL DESCRIPTION

1.1
1.2
1.2.1
1.2.2
1.2.3
1.3
1.3.1
1.3.2
1.3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.3.3.4
1.3.3.5
1.3.3.6
1.3.3.7
1.3.4
1.3.4.1
1.3.4.2
1.3.4.3

INTRODUCTION ................................................
PHYSICAL DESCRIPTION.......................................
DZQl1 Configurations.. . . . .. .. .. . .... .. . .. ... ... ... .. ..... ....
Interface Cables ...............................................
Test Connectors ...............................................
SPECIFICATIONS ...............................................
Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical .....................................................
Performance ..................................................
Interfaces ................................................
Maximum Configurations ..................................
Throughput ........................................... . . . .
Receivers .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitters ..............................................
Baud-Rate Generator ......................................
Performance Summary. .. .............. ................ ....
Interrupts .....................................................
Receiver-Done Interrupt ...................................
Silo-Alarm Interrupt .......................................
Transmit Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 2

INSTALLATION

2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.4
2.5

SCOPE .......................................................... .
UNPACKING AND INSPECTION ............................... .
INSTALLATION PROCEDURE .................................. .
Modem Control Jumpers ...................................... .
Module Installation ........................................... .
Testing DZQlls in PDP-II Systems ........................... .
Testing in MicroVAX Systems ................................. .
DEVICE ADDRESS ASSIGNMENTS ............................ .
INTERRUPT VECTOR ADDRESS ASSIGNMENTS .............. .

CHAPTER 3

DEVICE REGISTERS

3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6

SCOPE...........................................................
DEVICE REGISTERS ............................................
Control and Status Register .....................................
Receiver Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Parameter Register ........................................
Transmitter Control Register ....................................
Modem Status Register...... ............. .. ..... ........... ....
Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

1-1
1-3
1-4
1-6
1-6
1-8
1-8
1-8
1-8
1-8
1-8
1-9
1-9
1-9
1-9
1-9
1-10
1-10
1-10
1-10

2-1
2-1
2-2
2-2
2-4
2-8
2-10
2-10
2-13

3-1
3-1
3-1
3-4
3-5
3-7
3-8
3-8

CHAPTER 4

PROGRAMMING

4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4

SCOPE...........................................................
PROGRAMMING FEATURES .................................. . .
Interrupts .....................................................
Emptying the Silo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitting a Character .......................................
Data Set Control ..............................................

4-1
4-1
4-1
4-2
4-3
4-4

FIGURES
Figure No.

Title

Page

1-1
1-2
1-3
1-4
1-5
2-1
2-2
2-3
3-1

M3106 Module. ..... ... .... ....... ....... ................... .... ..
DZQ 11 System Applications ........................................
Elements of the DZQ 11 Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Connectors H325 and H329 ....................................
Loopback Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jumper Location on M3106 Module..................................
DZQ11 Installation (BCl1 U-25) ....................................
DZQ11 Installation (70-19964-00) ... ....... ....................... ..
Register Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-2
1-3
1-5
1-6
1-7
2-3
2-5
2-8
3-2

TABLES
Table No.

Title

Page

2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3
3-4

Items Supplied per Configuration .................................... .
Jumper Configuration .............................................. .
Break Character Response Options .................................. .
Address Switch Selection .......................................... .
Vector Switch Selection ............................................ .
Floating Address Assignments ...................................... .
One DUV11 and One DZQ11 ..................................... .
Two DZQ11s .................................................... .
First Part of Q-bus Vector Address Assignments List .................. .
DZQ 11 Register Address Assignments .............................. .
CSR Bit Assignments .............................................. .
RBUF Bit Assignments ............................................ .
LPR Bit Assignments .............................................. .

2-2
2-4
2-5
2-6
2-7
2-11
2-12
2-13
2-13
3-1
3-3
3-5
3-5

CHAPTER 1
GENERAL DESCRIPTION
1.1 INTRODUCTION
The DZQll is a Q-bus option. Its outline is shown in Figure 1-1. The DZQll is an asynchronous
multiplexer that interfaces between a Q-bus processor and four asynchronous serial data communication
lines. It can be used in many applications such as data concentration, real-time processing, and cluster
controlling. The DZQll communications interfaces are compatible with RS-232-C (V.28) and RS-423-A
(V. 1O/X.26). There is enough modem control to permit dial-up ( auto-answer) operation with full-duplex
modems *, such as the Bell models 103, 113, 212, or equivalent. Remote full-duplex working, as a control
(master) station over private lines, is also possible for point-to-point or multipoint operation. Figure 1-2
shows some possible applications for the DZQ 11 in a Q-bus system.
All the DZQ 11 parameters can be easily controlled. These parameters are:
•
•
•
•
•

Baud rate
Character length
Number of stop bits for each line
Odd or even parity for each line
Transmitter receiver interrupts.

Additional features include:
•
•
•
•
•

Limited modem control
Zero receiver baud rate
Break generation and detection
Silo buffering of received data
Line turnaround.

The DZQIl is program-compatible with the Q-bus DZVll and with the UNIBUS optionDZII-A. The
only exception is the number of serial lines supported. The DZQ 11 does not support 20 rnA operation.
Documents describing the DZQ 11 are:
•
•
•
•

DZQll Asynchronous Multiplexer User's Guide - EK-DZQII-UG
DZQl1 Asynchronous Multiplexer Technical Manual- EK-DZQII-TM
Field Maintenance Printset - MP01795
DZQll Maintenance Card - EK-DZQII-MC

* The DZQll modem control does not support half-duplex operation or the secondary transmit-and-receive
operation available on some modems (such as the Bell 202).

1-1

ADDRESS
SWITCH-PACK

E28
E13

VECTOR
SWITCH-PACK

R01789

Figure 1-1

M3106 Module

1-2

1.2 PHYSICAL DESCRIPTION
The DZQ 11 is made up of two components connected by a ribbon cable. The components are:
1.

A single dual-height module, 21.6 X 13.2 cm(8.51 X 5.19 inches), called the M3106 module.
All input and output connections are available on a Berg * header. This module includes all
active circuitry as well as the line drivers and receivers.

A distribution panel 6.7 X 8.5 cm(2.6 X 3.3 in) which contains four filtered D-type connectors
and a Berg header. This header connects to the M31 06 by means of a 40-way ribbon connector.

NOTE
A 07272 Orant Continuity card may be needed.
Refer to Section 2.3.2 for an explanation.
REMOTE

LOCAL

DATA
SET

TELEPHONE
LINE

--c1t-

DATA
SET

REMOTE
TERMINAL

I
I

DZ011
LOCAL
TERM.

DATA
SET

I
I
I

__ ?~_ ~:;A
I

DZ011
TELEPHONE

I LINE

RD185D

Figure 1-2 DZQ11 System Applications

* Berg is a registered trademark of the Berg Corporation.
1-3

1.2.1 DZQII Configurations
The basic option supplied is the DZQII-M and is made up of the following:

1.
2.
3.
4.

Logic Module
User's Guide
Maintenance Card
Turnaround test connector

M3I06
EK-DZQI1-UG
EK-DZQII-MC
H329

The basic option (DZQ 11-M) can be supplied with one of five cabinet kits for installation into different
systems. These are:
1.
2.
3.
4.
5.

CK-DZQI1-DA (21-inch cable), example of use - PDP-ll/23S
CK-DZQII-DB (12-inch cable), example of use - Micro/PDP-II
CK-DZQII-DC (30-inch cable), example of use - PDP-l 1/23+
CK-DZQII-DF (36-inch cable), example of use - PDP-ll/83
CK-DZQI1-D3 unshielded option (BCll U-25 cable).

The first four cabinet kits are almost identical except for the length of the flat ribbon cables, and the
addition of an adapter plate in the CK-DZQI1-DC. They are made up of the following:
1.
2.
3.
4.

BC05L-xx cable (see NOTE)
H325 line-Ioopback connector
The distribution panel - 70-19964-00
Mounting bolts and washers for the distribution panel.

A system integrated DZQ11 option is a DZQII-DP.

NOTE
The distribution panels provide noise filtering
and static discharge protection on the communications lines. The -DC version has an adapter
plate which allows the panel to be mounted in the
PDP-I 1/23+.
BC05 L-xx cables are supplied in different lengths
for each kit as previously specified.

The CK-DZQII-D3 cabinet kit is a cable assembly made up of four cables, with D-type connectors at
one end, and the other end connected to a socket which fits in the module connector. This kit does not
provide noise filtering or static discharge protection on the communications lines.

1-4

40-WAY BERGS

CABLE BC05L

DISTRIBUTION PANEL
(70-19964-00)

~b~
c

::J

c:::::::J

c:::J

M3106 MODULE

~DD

CABLE ASSEMBLY
BC11 U-25

I: i I ~ 'III: i "

la~GI
TEST CONNECTOR H325
TEST CONNECTOR H329
RD1790

Figure 1-3

Elements of the DZQ 11 Option

1-5

1.2.2 Interface Cables
The connections from the DZQ 11 use 25-pin male subminiature D-type connectors as specified for
RS-232-C.

Circuit AA (CCITT* 101) Pin 1
Pin 7
Circuit AB (CCITT 102)
Pin 2
Circuit BA (CCITT 103)
Pin 3
Circuit BB (CCITT 104)
Circuit CD (CCITT 108.2) Pin 20
Pin 22
Circuit CE (CCITT 125)
Pin 8
Circuit CF (CCITT 109)

Protective Ground
Signal Ground
Transmitted Data
Received Data
Data Terminal Ready
Ring Indicator
Carrier

NOTE
Signal ground and protective ground are connected
together, through the chassis, by jumper WI on
the 70-19964-00 distribution panel.
1.2.3 Test Connectors
Figure 1-4 shows the two accessory test connectors, H329 and H325.

The H329 plugs into the module I/O connector and connects line 0 to line 1, and line 2 to line 3.
The H325 plugs into an EIA connector on the distribution panel, or BC11 U-25 cable assembly, to
loopback data and modem signals over a single line. The loopback connections are shown in Figure 1-5.

.... .. .....

· · · · · · · · · .. 0

H329

H325

R01S5'

Figure 1-4 Test Connectors H325 and H329

* CCITT - The International Consultative Committee for Telegraphy and Telephony is an advisory committee
created under the United Nations to recommend worldwide standards.

1-6

H329 STAGGERED TURNAROUND
TRANSMIT a ------~.~ RECEIVE 1
DTRa --------"""":~ RING 1
" - - - . CARRIER 1

RING a :
CARRIER a "'~---'"---- DTR 1
RECEIVE a "'4~------ TRANSMIT 1
NOTE:

-------------LINE 2&3 ARE STAGGERED IN THE SAME WAY.

H325 LOOPBACK CONNECTIONS

:::8

11
SEC XMIT - - - - - - ,
SECRCV

XMITDATA~

RCVDATA~
4

REQTOSEND
CLR TO SEND
CARRIER
NEW SYNC
DATA SET ROY
DTR
RING

20
22

-I

0
0

Wl JUMPER MAY BE
REMOVED OR
INSERTED

R01876

Figure 1-5

Loopback Connection

1-7

1.3 SPECIFICATIONS
Environmental, electrical, and performance specifications for the DZQ 11 are listed in the following
paragraphs.
1.3.1

Environmental
Storage temperature

o degrees C to 66 degrees C
(32 degrees F to 151 degrees F)

Operating temperature

5 degrees C to 60 degrees C
(41 degrees F to 140 degrees F)

Relative humidity

10% to 95% non-condensing

1.3.2 Electrical
Power consumption

1.100 A at +5 V dc typical
0.236 A at + 12 V dc typical

Q-bus loading

Q-bus ac loads
Q-bus dc loads

1.5 ac loads
1.0 dc loads

1.3.3 Performance
The following paragraphs describe the DZQ 11 performance capabilities and restrictions.
1.3.3.1 Interfaces - The DZQl1 interfaces with the host computer bus and also with the four data
communication lines.
1.

System Bus Interface
The DZQ 11 module interfaces directly to a Q22 or other Q-bus via connectors A and B. The
module meets the DIGITAL Q-bus specification.

Serial Interfaces
The DZQ 11 serial interfaces comply with a subset ofEIAICCITT standards RS-232-C/V.24.
The electrical characteristics are compatible with EIAICCITT standards RS-232-C/V.28 and
RS-423/V.I0 (unbalanced interface).

1.3.3.2 Maximum Configurations - The DZQl1 multiplexer is assigned a device address in the
floating address space. The floating address space starts at 7600108 and extends to 7637768. Maximum
configuration of DZQ 11 s is not limited by floating address space, but is limited by the rules controlling a
system configuration of average size.
As the DZQ 11 needs one backplane AB slot-pair, it is physically possible to mount
•
•
•

Two M3106 modules in a PDP-l1/23-S
Three M3106 modules in a Micro/PDP-II
Four to five M3106 modules in a PDP-l1/23+

These numbers are the absolute maximum, because of the limited number of 70-19964-00 distribution
panels that can be installed in the rear panel of the mounting box. These numbers may also be limited by
the available capacity of the power supply, if other options are installed in the mounting box.

1-8

1.3.3.3 Throughput - Each DZQ 11 is capable of a throughput of 10 970 characters per second
( chars/ s). This rate is computed as follows.
(Bits/s X number of lines X directions) divided by bits/char
(9 600 X 4 X 2)/7 equals 10 970 chars/ s, at 5 bits/char with one start and one stop bit and no parity.
The full device throughput can only be maintained when a character service routine takes 100
microseconds or less.
The DZQ 11 has a maximum non-standard data rate of 19 800 baud. At this rate the throughput is 22 625
characters per second.
1.3.3.4 Receivers - The receivers perform serial-tc:rparallel conversion of 5-, 6-, 7-, or 8-level code
with one start bit and at least one stop bit. The character length, number of stop bits, parity generation, and
operating speed are programmable parameters for each line. Both the receiver and the transmitter of a
corresponding line share the same operating speed, and the receiver line can be enabled or disabled.
Each receiver is double buffered and has an acceptable input distortion of 43.75% on any bit. The sum of
the character distortion must also not exceed 43.75 %. An exception to this is the stop bit. The stop bit can
tolerate an error of 50%, that is, the receiver will accept a stop bit as short as one half of a bit period. Break
detection is provided on each receiver via a register bit. In addition, the configuration of switchpack E 13-9
and E13-10 can cause the processor to boot or halt when a break is detected on line 3.
1.3.3.5 Transmitters - The transmitters provide parallel-tc:rserial conversion of 5-, 6-, 7- or 8-level
code with or without parity. The parity sense, when selected, can be either odd or even. The stop code can
be either 1 or 2 units except when 5-level code is selected. When 5-level code is selected, the stop code can
be set to 1 or 1.5 units. The character length, number of stop units, parity generation and sense, and
operating speed are programmable parameters for each line. The operating speed for the transmitter is
common with the receiver. Breaks can be transmitted on any line. The maximum start-stop distortion for
the output of a transmitter is less than 2.5% for an 8-bit character.
1.3.3.6 Baud-Rate Generator - The baud-rate generators are completely programmable. Each line
has an independent generator which can select 1 of 16 baud rates. Speed tolerance for all rates is better
than 0.3%. The baud rates are shown in Section 1.3.3.7.
1.3.3.7 Performance Summary - The following list shows the programmable features offered for
each line.
Character length

5-, 6-, 7-, or 8-level code

Number of stop bits

1 or 2 for 6-, 7-, or 8-level code.
1 or 1.5 for 5-level code

Parity

Odd, even, or none

Baud rates

50, 75, 110, 134.5, 150,300,600, 1 200, 1 800,2000,2400,3 600,
4800, 7 200, and 9 600 (and non-standard 19 800)

Breaks

Can be generated and detected on each line
Line 3 has a hardware response to detected breaks which, when
enabled, may generate a HALT or RESET. This facility can be
selected by switches.

1-9

1.3.4 Interrupts
The following interrupts are available on the DZQ 11.
1.3.4.1 Receiver-Done Interrupt - The receiver-done interrupt occurs every time a character
appears at the output of the receiver buffer register and the silo alarm is disabled. The receiver-done
interrupt can be enabled or disabled from the bus.
1.3.4.2 Silo-Alarm Interrupt - The silo-alarm interrupt occurs after 16 entries have been made into
the receive buffer register by the scanner. This interrupt disables the receiver-done interrupt, and is armed
again when the receive buffer register has been read.
1.3.4.3 Transmit Interrupt - The transmit interrupt occurs every time the scanner finds a bufferempty condition, and the transmitter control register bit is set for that line. It can be enabled or disabled
from the· bus.

1-10

CHAPTER 2
INSTALLATION
2.1 SCOPE
This chapter contains the procedures for the unpacking, installation, and initial checkout of the DZQ 11
asynchronous multiplexer. It contains information on the following:

•
•
•
•

Device and vector address selection
Recommended cables
Testing after installation
Floating address and vector assignment.

2.2 UNPACKING AND INSPECTION
The DZQll is packed following normal commercial packing practices. To unpack, first remove all
packing material and check the equipment against the shipping list. (Table 2-1 contains a list of supplied
items per configuration.) Report any damage or shortages to the shipper immediately and inform the local
DIGITAL office. Examine all parts and carefully examine the module for damage, loose components,
and breaks in the etched paths.
CAUTION
The M3106 is supplied in a protective sleeve. Do
not remove the sleeve until you are about to install
the module. Protect the module from static during
installation.
WARNING
Procedures which call for the removal of the
system covers should be performed by trained
personnel only. Information on such procedures
is included for user information only.

2-1

Table 2-1

Items Supplied per Configuration

DZQII-M Base Option
Quantity

Description

1
1
1

M3106 module
H329 test connector
DZQll User's Guide (EK-DZQII-UG)

CK-DZQII-DA/DB/DC/D3/DF Cabinet kits

Quantity

Description

DA DB DC D3 DF

70-19964-00 distribution panel

I
1

74-28684-01 adapter plate
1

BC05L-IK 21-inch cable

BC05L-Ol 12-inch cable

BC05L-2F 30-inch cable

BCll U-25 cable assembly

BC05L-03 36-inch cable
I

H325 test connector

90-06633-00 screws

90-06021-01 washers

2.3 INSTALLATION PROCEDURE
The following paragraphs describe the installation of the DZQ 11 option in a Q-bus system.
2.3.1 Modem Control Jumpers
There are eight jumpers used for modem control (Figure 2-1). The jumpers labelled WI to W 4 connect the
Data Terminal Ready (DTR) circuit to the Request To Send (RTS) circuit. This allows the DZQll to
assert both DTR and R TS when using modems that need control ofRTS. These jumpers must be installed
for running the cable and external diagnostic programs. The four jumpers W5 to W8 connect the Forced
Busy (FB) circuits to the RTS circuits. When these jumpers are installed, asserting an RTS circuit also
places an ON or BUSY level on the corresponding FB circuit. Jumpers W5 to W8 are normally cut out
unless they are needed by the modems used. Table 2-2 shows the jumper line assignments.

2-2

~~I-I

r
f'

.... 1
)

- - - - - - - - ...LL,

,
W2

I
I
L -

~
-

I
_ _ ...J

~.~__~~ _~]c:::::JW5
W6

r - -"'

L__ J

L __ J

W8~ :~W4
I

L _ _ ..J

L __ ..J

C::J, -c::=:J
.---,
--,
I

L __ .J

I
L

~-=-=-::

1----1

__ ...J

_ _ ..J

,---..,
I
I

XTAL

I
I

L ___ ...J

[]J
l

XTAL

~::::: ~~~ BAUD RATE

r=:::J

c:::::J Wll RANGE-SELECT
L _ _ ..J

~1~

OTHER CONFIGURATIONS
NOT SUPPORTED
BY DIGITAL

,..

RD1791

Figure 2-1

Jumper Location on M3106 Module

2-3

Table 2-2 Jumper Configuration

2.3.2

Jumper

Connection

Line

WI
W2
W3
W4
W5
W6
W7
W8

DTR to RTS
DTR to RTS
DTR to RTS
DTR to RTS
RTS to FB
RTS to FB
RTS to FB
RTS to FB

3
2
1

o
3
2
1

Module Installation

To install the M3106 module, perform the following.

NOTE
This checkout procedure should be performed by
trained maintenance personnel only.
CAUTION
Switch ofT power before inserting or removing
modules.
The M3106 is a fine-line-etch PCB. Handle it
carefully to avoid damaging the etch.
Take anti-static measures to protect the module.
1.

The Q-bus Interrupt Acknowledge and the DMA Grant signals are daisy-chained through the
AB slots of the Q-bus backplane. If a DZQ 11 is followed by a quad-size option in an AB/AB
(Q/Q) backplane, it may cause an AB slot-pair to be left vacant. In order to maintain the
continuity of the daisy-chained signals, a G7272 Grant Continuity card should be installed in
the vacant A slot.

Refer to Section 2.4 for descriptions of the address assignments. Set the switches at E28 so that
the module responds to its assigned address. When a switch is closed (ON), a binary 1 is
encoded. When a switch is open (OFF), a binary 0 is encoded. The switch numbered 1 is
connected to address bit 12, 2 is connected to address bit 11, and so on (Table 2-4).

The 10-position switch at E13 performs the vector selection. Switch position 7 is not used.
Switch position 6 is connected to vector bit 3,5 is connected to vector bit 4, and so on. When a
switch is closed (ON), binary 1 is encoded. When a switch is open (OFF), a binary 0 is encoded
(Table 2-5).

Position 8 of the vector selection switch is a test switch which can disconnect the DZQ 11
oscillator from all circuitry. Make sure that this switch is in the ON position before installation.

Positions 9 and 10 of switch E 13 control the DZQ 11 response to a Break character received on
Line 3. There are three valid options: HALT, BOOT, and no response. Table 2-3 lists the
switch selections.

2-4

Table 2-3
Switch
9
10
OFF
ON
OFF
ON

OFF
OFF
ON
ON

Break Character Response Options

Effect of Break Character on Line 3
No effect
Causes Processor to halt
Causes Processor to boot
Illegal Condition

(normal operation)
(specific application)
(specific application)

Make sure that +5 volts is present between AA2 and ground and that + 12 volts is present
between AD2 and ground. Measure at the nearest accessible point, if the backplane cannot be
accessed.

Remove power and insert the module in an AB slot of the backplane.

Apply power and make sure that the +5 volts and +12 volts is present with the module
installed.
CAUTION
Insert and remove modules slowly and carefully to
prevent damage to the module components on the
card guides, and to avoid changing switch selections
in error.
"THIS SIDE UP"

M3106 MODULE

nnOD 0~n~ n00
OUDO

DOnO
nnnn

0 Du

Olln 00
R01877

Figure 2-2

DZQll Installation (BCll U-25)

2-5

Table 2-4

Address Switch Selection
LSB

-+---- MSB

.14

121111101 91 a \ 71 6 1 5 1 4

SWITCHES

SWITCH
NUMBER

E28 E28 E28 E28 E28 E28 E28 E28 E28 E28
10
9
7
8
4
6
3
5
1
2
ON
ON
ON

ON
ON
ON
ON ON
ON ON ON
ON
ON

17760200

ON ON

17760300
17760400

ON
ON

ON
ON
ON ON
ON ON

DEVICE
ADDRESS
17760000
17760010
17760020
17760030
17760040
17760050
17760060
17760070
17760100

17760500

ON
ON
ON ON
ON ON ON ON
ON ON ON ON

17760600
17760700
17763760
17763770

ON = SWITCH CLOSED TO RESPOND TO A LOGICAL 1 ON THE BUS
RDt878

2-6

Table 2-5

Vector Switch Selection

MSB

SWITCH
NUMBER

REFER TO
SECTION 2.3.2
FOR SETTING
OF E13 - 7 TO 10

I I I I I

SWITCHES

LSB
1

- 1/0 0

E13 E13 E13 E13 E13 E13
1 2
4
3
6
5
ON
ON
ON
ON
ON
ON
ON
ON

ON
ON
ON
ON
ON
ON
ON
ON

ON
ON

VECTOR
ADDRESS

ON
ON
ON ON
ON
ON
ON
ON

ON
ON
ON ON

300
310
320
330
340
350
360
370
400
500

ON ON

600

ON ON ON

700

ON ON ON
ON ON ON

ON ON
ON ON ON

760
770

ON = SWITCH CLOSED TO PRODUCE A LOGICAL 1 ON THE BUS
R01879

2-7

70-19964-00

CHANNELS

DISTRIBUTION PANEL

2
3

RED LINE
TO "A"

Q-BUS BACKPLAN E

GATE ARRAY

R018S2

Figure 2-3

DZQll Installation (70-19964-00)

2.3.3 Testing DZQlls in PDP-II Systems
The following diagnostics are available to test DZQl1s installed in PDP-II systems. DZITA and
DVDZD are only used when a link between two processors is to be tested.
CVDZA
CVDZB
CVDZC
CXDZB

DZVl1/DZQll Logic Test - Part 1
DZVll/DZQl1 Logic Test - Part 2
DZVll/DZQl1 Cable/Echo Test
DECX/ll Module

DZITA
DvnZD

Interprocessor Test Program (ITEP)
Overlay for ITEP

2-8

Test the option as follows.
1.

Run diagnostics CVDZA and CVDZB in internal mode, to verify operation. Refer to the listing
for more help. Run at least three passes without error.

Insert the H329 test connector in Jl with the letter side facing up. Jl is the cable connector at
the top of the M3106 module.
Run CVDZA and CVDZB in the staggered mode, to verify module operation. Refer to the
diagnostic listing for the correct procedure. Run at least three passes without error.

If the unshielded cab-kit (D3) version is used, replace the H329 test connector with the Berg
end of the BCII U cable assembly. Follow the 'This side up' instruction on the assembly. Refer
to Figure 2-2 for assembly and interconnection instructions.

If the cab-kit versions CK-DZQ 11-DA, -DB or -DF are used, feed the cable through the rear of
the cabinet and connect the Berg plug to the distribution panel. Mount the distribution panel in
the opening at the rear of the cabinet
The -DC version is provided with an adapter plate to fit the large opening in a PDP-I 1/23+.
Mount the adapter plate on the distribution panel, with four of the eight screws provided. Mount
the distribution panel as described above.

Connect the H325 test connector on the first line and run diagnostic CVDZC. Select the cabletest part of the diagnostic. Three passes are needed without error. Repeat this step for each line.

Run the DECX/Il system exerciser to verify the absence of Q-bus interference with other
system devices.

The DZQ II is now ready for connection to external equipment. If the connection is to a local
terminal through either of the two options (BCII U-25 or 70-19964-00), a null modem cable
assembly must be used. Use the BC22A, BC22D, or BC03P null modem cables for connection
between the option and the terminal. The H312-A null modem unit may also be used in place of
the null modem cables.
Connections between the option and a modem should be made using a BC22E or BC05 D cable.
All of the cables referred to, with the exception of the BCII U-25, must be ordered separately as
they are not components of a DZQ II option.
If a terminal is available, run the diagnostic CVDZC in echo-test mode to verify the cable
connections and the terminal equipment.

2-9

2.3.4 Testing in MicroVAX Systems
The following diagnostic tests are available for testing DZQ 11 s in MicroVAX systems.
EHXDZ
EHKMV

DZVll/DZQll Test
Macroverify - MicroVAX System Test

Macroverify is a standalone diagnostic which contains a DZVll/DZQll test module.
Refer to the appropriate diagnostic listing, or to Chapters 11 and 14 of the MicroVAX Owner's Guide, for
details of how to run EHXDZ and EHKMV.
Test the option as follows.
1.

Boot from the MicroVAX system tests diskette (number 2 of2). Attach and select the DZQ 11
that is to be tested.

Run EHXDZ for three error-free passes of the internal (default) test.

Install the H329 staggered loopback connector on the M31 06 module. Run EHXDZ for three
error-free passes of the staggered test.

Remove the H329. Install the BC05L cable and the distribution panel.

If the operation of a terminal link is to be tested, connect the terminal line to the distribution
panel. Run the EHXDZ echo test on that line until the link· is proven. Depending on the
terminal, a null-modem may be needed for this test. Exit echo test 1?y A Z (CTRL/Z).

Remove all external cables and connectors from the distribution panel. Boot the CPU tests
diskette (number 1 of 2). The Macroverify diagnostic will run automatically when the boot
process is complete. When the test completes, the status of all options will be displayed.

If no device has a TEST FAILED status, the DZQ 11 is now ready for connection to external
equipment. If the connection is to a local terminal, a null modem cable assembly must be used.
Use the BC22A, BC22D, or BC03P null modem cables for connection between the option and
the terminal. The H312-A null modem unit may also be used in place of the null modem cables.
Connections between the option and a modem should be made using a BC22E or BC05 D cable.
All of the referenced cables must be ordered separately as they are not components of a DZQ II
option.

2.4 DEVICE ADDRESS ASSIGNMENTS
On UNIBUS and Q-bus systems, a range of addresses (xxx600 108 to xxx63 77 68) in the top 4 K words is
assigned as floating address space (xxx means all top address bits = 1).
The first part of the list of options (sufficient to include the DZQ 11) which can be assigned floating device
addresses is given in Table 2-6. 'Rank' gives the sequence of address assignment for both Q-bus and
UNIBUS options.
If addresses are assigned according to defined rules, configuration programs can check which options are
installed in a system. Having a combined list allows us to use one set of configuration rules and one
configuration program for both Q-bus and UNIBUS systems.

2-10

Table 2-6

Floating Address Assignments

Rank

Device

Size
(decimal)

Modulus
(octal)

DJ11

4 words

DH11

8 words

DQ11

4 words

DUll, DUV11*

4 words

DUP11

4 words

LK11A

4 words

DMC11/DMR11

4 words

DZ11, DZS11,
DZQ11*/DZV11*
DZ32

4 words

* Q-bus device
For example, the address assignment sequences could be:

UNIBUS

Q-bus

DJ11
DH11
DQ11
DUll
DUP11
LK11A
DMC11
DZ11

No Q-bus equivalent of DJ11
No Q-bus equivalent of DH11
No Q-bus equivalent of DQ 11
DUV11
No Q-bus equivalent of DUP11
No Q-bus equivalent of LKII A
No Q-bus equivalent of DMCII
DZQ 11 an~ so on.

Devices of the same type are given sequential addresses, therefore all DUV11 s in a system will have lower
addresses than DZQ 11 s or DZV11 s.
For the purpose of address assignment, DZQ 11 s and DZVll s are considered as devices of the same type.
The column Sizerdecimal) in Table 2-6, shows how many words of address space are needed for each
device. The column M odulus(octal) is the modulus used for starting addresses. For example, devices with
an octal modulus of 10 must start at an address which is a multiple of 108. The same rule is used to select a
gap address (see assignment rules) after an option, or for a nonexistent device.

2-11

The assignment rules are as follows.
1.

Addresses, starting at xxx60010, are assigned according to the sequence of Table 2-6

Option and gap addresses are assigned according to the octal modulus as follows.
a.

Devices with an octal modulus of 10 are assigned an address on a 108 boundary (the three
lowest-order address bits = 0)

Devices with an octal modulus of 20 are assigned an address on a 208 boundary (the four
lowest-order address bits = 0)

Address space equal to the device's modulus must be allowed for each device which is
connected to the bus

A one-word gap, assigned according to rule 2, must be allowed after the last device of each type.
This gap could be bigger when rule 2 is applied to the following rank

A one-word gap, assigned according to rule 2, must be allowed for each unused rank on the list if
a device with a higher address is used. This gap could be bigger when rule 2 is applied to the
following rank

Two examples of address assignment follow. Table 2-7 shows addresses for a system with one DUV11
and one DZQ 11. Table 2-8 shows addresses for a system with no DUV11 and two DZQ 11 s. Note that
where there is no Q-bus device at a specific rank, the UNIBUS device parameters must be used to assign
the gap. Vector assignments (see Section 2.5) are also shown in these tables.
Table 2-7 is supported by a description of how to apply the assignment rules.
Table 2-7

One DUVII and One DZQl1

Rank

Address

Designation

1
2
3
4

xxx60010
xxx60020
xxx60030
xxx60040
xxx60050
xxx60060
xxx60070
xxx60100
xxx60110
xxx60120

DJ11 gap
DH11 gap
DQ11 gap
DUVII
DUV11 gap
DUP11 gap
LK11A gap
DMC11 gap
DZQl1
DZQl1 gap

6
7
8

Vector

300

310

The first floating address is 760010. As a DJl1 has a modulus of 108, its gap can be assigned to 760010.
The next available location becomes 760012.
As a DH11 has a modulus of 208, it cannot be assigned to 760012. The next modulo 20 boundary is
760020, so the DH11 gap is assigned to this address. The next available location is therefore 760022.
A DQ11 has a modulus of 108. It cannot be assigned to 760022. Its gap is therefore assigned to 760030.
The next available location is 760032.

2-12

TheDUV11 has amodulusof108. It cannot be assigned to 760032. It is therefore assigned to 760040. As
the size of DUV11 is four words, the next available address is 760050.
There is no second D UV11, so a gap must be left to indicate that there are no more D UV11 s. As 760050
is on a lOs boundary. The DUVl1 gap can be assigned to this. The next available address is 760052.
And so on.

Table 2-8 Two DZQlls
Rank

Address

Designation

1
2

xxx60010
xxx60020
xxx60030
xxx60040
xxx60050
xxx60060
xxx60070
xxx60100
xxx60110
xxx60120

DJ11 gap
DHll gap
DQ11 gap
DUV11 gap
DUP11 gap
LK11Agap
DMC11 gap
1st DZQ11
2nd DZQll
DZQl1 gap

3
4
5
6
7
8
8

Vector

300
310

2.5 INTERRUPT VECTOR ADDRESS ASSIGNMENTS
Addresses between 300s and 774s are designated as the floating vector space. These addresses are
assigned in sequence as in Table 2-9.
Each device needs two 16-bit locations for each vector. For example, a device with one receive and one
transmit vector needs four words of vector space.
The vector assignment rules are as follows.
1.
2.

Each device occupies vector address space equal to 'Size' words. For example, the DLV11-J
occupies 16 words of vector space. If its vector was 3008 the next available vector would be
3408.
There are no gaps, except those needed to align an octal modulus.

The vector addresses shown in Tables 2-7 and 2-8 are assigned according to these rules.

Table 2-9

First Part of Q-bus Vector Address Assignments List

Device

Size
(decimal)

Modulus
(octal)

DLVI1-J
DLVll,DLV11-F
DRVI1-B
DRVl1
DLVI1-E
VSV11
KWV11
DUVl1
DZVl1/DZQll

16
4
4
4
4
8
4
4
4

10
10
10
10
10
10
10
10
10

2-13

CHAPTER 3
DEVICE REGISTERS
3.1 SCOPE
This chapter describes the format and bit function of each register in the DZQ 11.
3.2 DEVICE REGISTERS
The DZQll contains six addressable registers. Figure 3-1 shows the bit assignments of these registers
and Table 3-1 lists the registers and related DZQ 11 addresses.
Table 3-1

DZQll Register Address Assignments

Mnemonic

Address

Program
Capability

Control and Status Reg.
Receiver Buffer
Line Parameter Register
Transmitter Control Reg.
Modem Status Register
Transmit Data Register

CSR
RBUF
LPR
TCR
MSR
TDR

76XXXO
76XXX2
76XXX2
76XXX4
76XXX6
76XXX6

Read/Write
Read Only
Write Only
Read/Write
Read Only
Write Only

xxx = Selected in agreement with the floating device address system.
3.2.1 Control and Status Register
The control and status register (CSR) can be addressed with a byte or word address. All bits in the CSR
are cleared by an occurrence of BINIT, or by setting device Master Clear (CSR<04». The format is
shown in Figure 3-1 and the bit assignments are listed in Table 3-2.

3-1

MSB
15
RO

1----

CONTROL
& STATUS
(CSR)

RECEIVER
BUFFER
(RBUF)

TROY

RW
t----

TIE

~-- ~---

RO
RO
RO
DATA OVRN FRAM
VALID ERR
ERR

~---

(j,)
I

TRANSMIT
CONTROL
(TCR)

MODEM
STATUS
(MSR)

TRANSMIT
DATA
(TOR)

~'"

.:>

s-~
~""
.:>

~o "kQ
~t:O

~----

ERR
WO

~t:O

~,:;
~

f~
~

~ ,,~
~

.::>t"j

flW__ RW

-- RO

O~ TLiNE TLiNE
IRDONE
.::>
A
B

--- RW

RIE

MSE

1-----

CLR

RO
RO
---RX
RX

--- RO

----

1----

,s;

.::>""

LINE
B

LINE
A

RBUF
07

RBUF
06

RBUF
05

RBUF
04

MAINT

CODE CODE CODE CODE
D
C
B
A

ENAB

~o Q

~4'
~

~t:O

1 - - - - ~~--

DTR
2

DTR
3
RO
~---

---

__ !!,W__

~I!..W

DTR
1
RO
~-

DTR
0

-- RO

~---

PAR

ENAB CODE

LGTH
B

~, ~l'
, ~?;J
~".J

.:>

~~
.:>

o~
.:>

~~
.:>

~""
.;:,

~,:;

~t:O

I~" ~1;1
~

1----

RBUF
03

LGTH
A

LSB
00

RO
RO
-----

WO
---- ------SPEED SPEED SPEED SPEED --ODD --RX
PAR
STOP CHAR
CHAR

~, bi---I
, , ~trI
~o t$ ~~

i if

09
1---

~ ~l#VI
o~

SAE

RO
--- ---. PAR

~~bi

LINE
PARAMETER ~o ~Q
.:5
(LPR)

BYTES
HIGH LOW
08
07

RBUF
02

?
~o t$

~""

RO
-----

RBUF
01

RBUF
DO

WO
---

~---

LINE
B

LINE
ENAB
3

LINE
ENAB
2

RO
RO
RO
------

~---

LINE
ENAB
1

RI2

RI1

WO
WO
WO
WO
WO
WO
---------- 1WO- - - - WO
--- WO
--- foo----

BRK
2

TBUF
1

~--

BRK
3

.:>

RI3

1----

Figure 3-1

BRK
1

BRK
0

TBUF
7

TBUF
6

TBUF
5

TBUF
4

TBUF
3

LINE
ENAB
0

I- - - -

CO
2

LINE
A

~~-- _RlY_ t-R!l_ t-R~ __

CO
3

CO
1

.:5

TBUF
2

RIO

----- 1WO

TBUF
0
MA·0552

Table 3-2

CSR Bit Assignments

Bit

Title

Function

<02:00>

Not used

<03>

Maintenance
(MAINT)

This is a READ/WRITE bit. When set it loops the serial output
connections of the transmitter to the corresponding serial input
connections of the receiver at the UART. (Used for loopback test
only.)

<04>

Master Clear
(CLR)

When written to aI, this bit generates 'initialize' within the DZQ 11.
A read-back of the CSR with this bit set indicates initialize in
progress within the device. This bit is self-clearing. All registers,
silos, and UARTs are cleared with the following exceptions:
1.

Only bit 15 of the receiver buffer register (Data Valid) is
cleared; the other bits « 14:00» are not.

The high byte of the transmitter control register is not cleared by
Master Clear.

The modem status register is not cleared by Master Clear.

<05>

Master Scan
Enable
(MSE)

This read/write bit must be set to permit the receiver and transmitter
control sections to start scanning. When cleared, Transmitter Ready
(CSR<15» is inhibited from setting, and the received character
buffers (silos) are cleared.

<06>

Receiver
Interrupt
Enable
(RIE)

This bit permits the generation of an interrupt, when CSR<07> or
CSR<13> is set. This bit is read/write.

<07>

Receiver Done
(RDONE)

This is a read-only bit that is set when a character appears at the
output of the first-in/first-out (FIFO) buffer. For the DZQll to run
in the interrupt-per-character mode, CSR<06> must be set and
CSR<12> must be cleared. With CSR<06> and CSR<12>
cleared, character-flag mode is indicated. Receiver Done clears
when the receiver buffer register (RBUF) is read or when Master
Scan Enable (CSR<05» is cleared. If the FIFO buffer contains an
additional character, the Receiver Done flag stays clear for up to 1
microsecond, while that character bubbles through to the bottom of
the FIFO.

<09:08>

Transmitter
Line Number
(TLINE B and
TLINE A)

These read-only bits indicate the line number whose transmit buffer
needs servicing. These bits are valid only when Transmitter Ready
(CSR<15» is set, and are cleared when Master Scan Enable is
cleared. Bit <08> is the least-significant bit.

<11:10>

Not used

3-3

Table 3-2

CSR Bit Assignments (Cont)

Bit

Title

Function

<12>

Silo Alarm
Enable
(SAE)

This is a read/write bit. When set, it enables the silo-alarm and
prevents RDONE (bit <07» from causing interrupts. If the
receiver interrupt enable bit (bit <06> ) is set, SAE enables the siloalarm (bit < 13> ) to generate an interrupt after 16 silo entries. If siloalarm is not set, then SAE may be used as a flag to indicate that 16 or
more characters are in the silo.

<13>

Silo Alarm
(SA)

This is a read-only bit set by the hardware after 16 characters have
been entered into the FIFO buffer. Silo Alarm is held cleared when
Silo Alarm Enable (CSR< 12» is cleared. This bit is cleared by a
read to the receiver buffer register and does not set until 16 additional
characters are entered into the buffer. If Receiver Interrupt Enable
(CSR<06» is set, the occurrence of Silo Alarm generates a
receiver interrupt request. Flag mode operation of the Silo Alarm bit
is permitted with CSR<06> cleared.

<14>

Transmitter
Interrupt
Enable
(TIE)

This is a read/write bit which must be set for Transmitter Ready to
generate an interrupt.

<15>

Transmitter
Ready
(TRDY)

This read-only bit is set by the hardware when the transmitter
scanner stops on a line whose transmit buffer may be loaded with
another character and whose related TCR bit is set. The transmitter
line number, specified in CSR<09:08>, is only valid when Transmitter Ready is set. Transmitter Ready is cleared by any of the
following conditions:
1.

When Master Scan Enable is cleared.

When the related TCR bit is cleared for the line number
pointed to in CSR<09:08>

If additional transmit lines need service, Transmitter Ready appears
again within 1.4 microseconds of the completion of the 'transmit data
register load' instruction. When Transmitter Ready occurs with
Transmitter Interrupt Enable set, a transmitter interrupt request is
generated.
3.2.2 Receiver ButTer
The receiver buffer (RBUF) is a 16-bit read-only register that contains the received character at the output
of the FIFO buffer. A read of the register causes the character entry to be removed from the buffer, and all
other entries to shift down to the lowest location that is not occupied. Only the Data Valid bit
(RBUF<15» is cleared by BINIT or by setting device Master Clear (CSR<04». Bits < 14:00> are
not affected. The bit assignments for the RBUF register are listed in Table 3-3.

3-4

Table 3-3

RBUF Bit Assignments

Bit

Title

Function

<07:00>

Received
Character
(RBUF 0<7:0»

These bits contain the received character, right justified. the leastsignificant bit is bit <00>. For short characters, bits that are not
used are logic low. The parity bit is not shown.

<09:08>

These bits contain the line number on which the Received Character
Received
was received. Bit <08> is the least significant.
Line Number
(RX LINE B and
RX LINE A)

<11:10>

Not used

<12>

Parity Error
(PAR ERR)

This bit is set if the sense of the parity of the received character does
not agree with the parity defined for that line.

<13>

Framing Error
(FRAMERR)

This bit is set if the received character did not have a stop bit present
at the correct time. This bit is usually interpreted as indicating that a
break has been received.

<14>

Overrun Error
(OVRN ERR)

This bit becomes set when a received character is overwritten in the
UART buffer (by a following character), before it has been
transferred by the scanner to the FIFO.

<15>

Data Valid
(DATA VALID)

This bit, when set, indicates that the data in bits < 14:00> is valid.
This bit permits the use of a character-handling program which again
and again takes characters from the FIFO buffer until there are no
more available. This is done by reading this register and checking bit
< 15 > until the program gets a word for which bit < 15> is zero.

3.2.3 Line Parameter Register
The line parameter register (LPR) controls the operating parameters related to each line in the DZQ 11.
The LPR must be addressed with a word address and is a write-only register. The line parameters for all
lines must be loaded again following an occurrence of either BINIT or device Master Clear. Table 3-4 lists
bit assignments.
Table 3-4

LPR Bit Assignments

Bit

Title

Function

<01:00>

Parameter Line
Number
(LINE Band
LINE A)

These bits specify the line number for which the parameter information
(bits < 12:3» is to apply. Bit <00> is the least-significant bit.

<02>

Not used

Must always be written as a zero when specifying the parameter line
number. Writing this bit as a one extends the parameter line number
field into nonexistent lines. Parameters for lines 00 to 03 are not
affected.

3-5

Table 3-4

LPR Bit Assignments (Cont)

Bit

Title

Function

<04:03>

Character
Length
(CHARLGTH
B and CHAR
LGTHA)

These bits are set to receive and transmit characters of the length
(except parity) shown below.
Bit 04

Bit 03

0
0
1
1

0
1
0
1

5-bit
6-bit
7-bit
8-bit

<05>

Stop Code
(STOP CODE)

This bit sets the stop code length; 0 = 1 unit stop, 1 = 2 unit stop (or
1.5 unit stop if a 5-level code is used).

<06>

Parity Enable
(PAR ENAB)

If this bit is set, characters transmitted on the line have an
appropriate parity bit added, and characters received on the line have
their parity checked.

<07>

Odd Parity
(ODD PAR)

If this bit is set, characters of odd parity are generated on the line and
incoming characters are expected to have odd parity. If this bit is not
set, but bit <06> is set, characters of even parity are generated on
the line, and incoming characters are expected to have even parity. If
bit <06> is not set, then the setting of this bit will not have any effect.

<11:08>

Speed code
(SPEED CODE
D to SPEED
CODE A)

The state of these bits determines the operating speed for the
transmitter and receiver of the selected line.

Baud Rate

0
0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19800 *

1
1

1
1
I

Not supported by standard software.

3-6

Table 3-4 LPR Bit Assignments (Cont)
Title

Bit

Function
,

<12>

Receiver
Enabled
(RXENAB)

<15:13>

Not used

This bit must be set before the UART receiver logic can assemble
characters from the serial input line. This bit is cleared following a
BINIT or device Master Clear.

NOTE
The M3106 module can be modified by jumpers
W9 to W13, so that code IIII selects baud rates
other than 19 800. This modification is not supported
by DIGITAL.
3.2.4 Transmitter Control Register
The transmitter control register (TCR) is a byte- and word-addressable register. The low byte of the TCR
contains the transmitter control bits, and must be set to start transmission on a line. Each TCR bit position
is related to aline number. For example, J'CR<OO> is related to line 00, bit <01> to line 01, and soon.
Setting a TCR bit causes the transmitter scanner clock to stop if the UART for this line has a 'transmit
buffer empty' condition. An interrupt is then generated if Transmitter Interrupt Enable is set. The scanner
clock restarts when either the transmit data register (TDR) is loaded with a character or the TCR bit is
cleared for the line on which the clock has stopped. TCR bits must only be cleared when the scanner is not
running, (that is, Transmitter Ready is set or Master Scan Enable is cleared).
The line enable bits are represented in TCR<03:00>. These bits are read/write and are cleared by BINIT
or device Master Clear. Bits <07:04> are not used, and are read as zero.
The high byte of the TCR register contains the modem control signal that can be written, data terminal
ready (DTR). The bits are defined as follows:

Bit

Name

<08>
<09>
<10>
<11>
<15:12>

DTRLine 00
DTR Line 01
DTRLine 02
DTRLine 03
Not used; read as zero

Assertion of a DTR bit creates an ON condition on the appropriate modem circuit for that line. DTR bits
are read/write and are cleared only by BINIT. Jumpers have been provided to allow the RTS circuits to be
asserted using DTR assertions.

3-7

3.2.5 Modem Status Register
The modem status register (MSR) is a 16-bit read-only register. A read to this register gives the status of
the modem control signals that can be read, Ring and Carrier. The ON condition of a modem control signal
is interpreted as a logical one. Bits <07 :04> and < 15: 12> are not used and are read as a zero. The other
bits are defined as follows:
Bit

Name

Bit

Name

<00>
<01>
<02>
<03>
<07:04>

Ring Line 00
Ring Line 01
Ring Line 02
Ring Line 03
Not used; read as
zero

<08>
<09>
<10>
<11>
<15:12>

Carrier Line 00
Carrier Line 01
Carrier Line 02
Carrier Line 03
Not used; read as zero.

3.2.6 Transmit Data Register
The transmit data register (TDR) is a byte- and word-addressable, write-only register. Characters for
transmission are loaded into the low byte. TDR<OO> is the least-significant bit Loading of a character
should occur only when Transmitter Ready (CSR<15» is set The character that is loaded into this
register is routed to the line defmed in CSR<09:08>. The high byte of the TDR is defined as the break
control register.
There is a corresponding break bit for each of the four multiplexer lines. TDR<08> represents the break
bit for line 00, TDR<09> for line 01, and so on. TDR< 15: 12> are not used. Setting a break bit forces the
output of that line to space. This register is cleared by BINIT or device Master Clear. The break control
register can be used regardless of the state of the Device Maintenance bit (CSR<03».

3-8

CHAPTER 4
PROGRAMM1NG

4.1

SCOPE

This chapter contains information for programming the DZQ 11 in the most efficient way. To do so, the
programming controls must be completely understood. The following paragraphs discuss the DZQ 11
from the programming point of view and describe recommended programming methods.

4.2 PROGRAMMING FEATURES
The DZQll has some programming features that allow control of baud rate, character length, stop bits,
parity, and interrupts. This section discusses the application of these controls to get the wanted operating
parameters.

4.2.1

Interrupts
The Receiver Interrupt Enable (RIE) and Silo Alarm Enable (SAE) bits in the CSR control the way that
the DZQ 11 receiver interrupts the processor.
IfRIE and SAE are both clear, the DZQ 11 never interrupts the processor. In this event, the program must
regularly check that the data is available in the silo, and empty the silo when data is present. If the program
operates from a clock, it should check for characters in the silo at least as often as the time it takes for the
silo to fill, allowing a safety element to cover processor-response delays and time to empty the silo. The
Receiver Done (RDONE) bit in the CSR is set when a character is available in the silo. The program can
regularly check this bit with a test byte or bit test instruction. When RDONE is set, the program should
empty the silo.
lf RIE is set and SAE is clear, the DZQ 11 interrupts the processor and forces it to the DZQ 11 receiver
vector address, when RDONE is set. This indicates the presence of a character at the bottom of the silo.
The interrupt service routine can get the character by performing a move instruction from the RBUF. If the
program then dismisses the interrupt, the DZQ 11 interrupts when another character is available (which
may be immediately if additional characters were placed in the silo while the interrupt was being serviced).
Another way is for the interrupt service routine to respond to the interrupt by emptying the silo before it
dismisses the interrupt.

4-1

IfRIE and SAE are both set, the DZQ 11 interrupts the processor to the DZQ 11 receiver vector when the
Silo Alarm (SA) bit in the CSR is set. The SA bit is set when 16 characters have been placed in the silo
after the last time the program has accessed the RBUF. Accessing the RBUF clears the SA bit and the
related counter. The program should follow the procedure described in Section 4.2.2 to empty the silo
completely in response to a Silo Alarm interrupt. This makes sure that any characters placed in the silo
while it is being emptied are processed by the program.
NOTE
If the program processes only 16 entries in
response to each Silo Alarm interrupt, characters
coming in while interrupts are being processed
build up without being counted by the Silo Alarm
circuit. The silo may in the end overflow without
the alarm being issued.
If the Silo Alarm interrupt is used, the program will not be interrupted when fewer than 16 characters are
received. In order to respond to short messages during periods of medium activity, the program should
regularly empty the silo. The scanning period depends on the wanted response time to received characters.
While the program is emptying the silo, it should make sure that DZQ 11 receiver interrupts are inhibited.
This should be done by raising the processor priority. The Silo Alarm interrupt feature can greatly
decrease the processor overhead that would be needed by the DZQ 11 receiver. This is done by removing
the need to enter and exit an interrupt service routine each time a character is received.
The Transmitter Interrupt Enable (TIE) bit controls transmitter interrupts to the processor. If enabled, the
DZQ 11 interrupts the processor at the DZQ 11 transmitter interrupt vector when the Transmitter Ready
(TRDY) bit in the CSR is set. This indicates that the DZQll is ready to accept a character to be
transmitted.
Each DZQ 11 needs two interrupt vectors, one for the transmitter section and one for the receiver section.
If simultaneous interrupt requests are generated from each section, the receiver section would have
priority in placing its vector on the Q-bus. A receiver interrupt to address XXO is generated from having
either a Receiver Done (CSR<07» or Silo Alarm (CSR<13» occurrence. A transmitter interrupt to
address XX4 is generated by Transmitter Ready (CSR< 15». An additional prerequisite for generating
interrupts is that the individual interrupt enable bits are set. The recommended method for clearing
interrupt enable bits is first to raise the processor status word to level 4; next, to clear these interrupt enable
bits; and then lower the processor status word to zero. Using this method prevents false interrupts from
being generated.
4.2.2 Emptying the Silo
The program can empty the silo by performing consecutive move instructions from the RBUF to
temporary storage. Each move instruction copies the bottom character in the silo so that it is not lost, and
clears out the bottom of the silo, allowing the next character to move down for access by a following move
instruction. The program can determine when it has emptied the silo by testing the Data Valid bit in each
word moved out of the RBUF. A zero value indicates that the silo has been emptied. The test can be
performed by branching on the condition code following each move instruction. The test or bit test
instruction must not access the RBUF because these instructions cause the next entry in the silo to move
down without saving the current bottom character. Also, following a move from the RBUF, the next
character in the silo is not available for at least one microsecond. Therefore, on fast CPUs, the program
must use enough instructions or no-operation instructions to make sure that consecutive moves from the
RBUF are separated by not less than one microsecond. This prevents a false indication of an empty silo.

4-2

4.2.3 Transmitting a Character
The program controls the DZQ 11 transmitter through four registers on the Q-bus: the control and status
register (CSR), the line parameter register (LPR), the transmit control register (TCR), and the transmit
data register (TOR).
Following DZQ 11 initialization, the program must use the LPR to specify the speed and character format
for each line to be used and must set the Master Scan Enable (MSE) bit in the CSR. The program should
set the TIE bit in the CSR if it wants the DZQ 11 transmitter to interrupt the processor.
The TCR is used to enable and disable transmission on each line. One bit in this register is related to each
line. The program can set and clear bits by using move, move byte, bit set, bit set byte, bit clear, and bit
clear byte instructions. (If word instructions are used, the Line Enable bits and the DTR bits are accessed
together.)
The DZQ 11 transmitter is controlled by a scanner which is continuously looking for an enabled line (Line
Enable bit set) which has an empty transmitter buffer. When the scanner finds such a line, it loads the
number of the line into the 2-bit transmit line number (TLINE) field of the CSR and sets the TROY bit,
interrupting the processor if the TIE bit is set. The program can clear the TROY bit by moving a character
for the indicated line into the TBUF or by clearing the line enable bit. Clearing the TROY bit allows the
scanner to continue its search for lines needing service.
To start transmission on an idle line, the program should set the TCR bit for that line and wait for the
scanner to request service on the line, as indicated by the scanner loading the number of the line into
TLINE and setting TROY. The program should then load the character to be transmitted into the TBUF
by using a move byte instruction. If the interrupts are to be used, a useful way of starting up a line is to set
the TCR bit in the main program and let the normal transmitter interrupt routine load the character into the
TBUF.

NOTE
The scanner may find a different line needing
service before it finds the line being started up.
This occurs if other lines request service before the
scanner can find the Jine being started. The program
must always cheek the TLINE field of the CSR
when responding to TRDY, to make sure that it
loads characters for the correct line. Assuming the
program services lines as requested by the scanner,
the scanner in the end finds the line being started.
If more than one line needs service, the scanner
requests service in priority order as determined by
Jine number. Line 3 has the highest priority and
Jine 0 the lowest.
To continue transmission on a line, the program should load the next character to be transmitted into the
TBUF each time the scanner requests service for the line as indicated by TLINE and TROY. Because the
transmitters are double buffered, a high-priority line may request two consecutive loads.
To terminate transmission on a line, the program loads the last character normally, and waits for the
scanner to request an additional character for the line. The program clears the Line Enable bit at this time
instead of loading the TBUF.

4-3

The normal rest condition of the transmitted data connection for any line is the one state. The Break
(BRK) bits are used to apply a continuous zero signal to the line. One bit in the TDR is related to each line.
The line stays in this condition as long as the bit stays set. The program should use a move byte instruction
to access the BRK bits.
If the program continues to load characters for a line after setting the BRK bit, transmitter operation
appears normal to the program regardless of the fact that no characters can be transmitted while the line is
in the continuous zer<rsending state. The program may use this facility for sending correctly timed zero
signals by setting the BRK bit and using transmit ready interrupts as a timer. The program must also make
sure that the line returns to the one state at the end of the zer<rsending period before transmitting any
additional data characters.

The following procedure does this. When the scanner requests service the first time after the program has
loaded the last data character, because the lines are double buffered, the last data character has only
started transmission. The program should therefore load an all zero character, and wait for the next service
request while the last character is transmitted. When the scanner requests service the second time, the
program should set the BRK bit for the line, and the zero character is overwritten. At the end of the zer<r
sending period, the program should load an all zero character to be transmitted. When the scanner
requests service, indicating this character has started transmission, the program should clear the BRK bit
and load the next data character.

4.2.4 Data Set Control
The program may sense the state of the Carrier and Ring Indicator signals for each modem and may
control the state of the Data Terminal Ready signal to each modem. The program uses two registers to
access the DZQ 11 modem control logic. There are no hardware interlocks between the modem control
logic and the receiver and transmitter logic. Any wanted sequence should be done under program control.
The Data Terminal Ready (DTR) bits in the TCR are read/write bits. Setting or clearing a bit in this
register turns the appropriate DTR signal on or off. The program may access this register with word or byte
instructions. (If word instructions are used, the DTR and Line Enable bits are accessed together.) The
DTR bits are cleared by the INIT signal on the Q-bus but are not cleared if the program clears the DZQ 11
by setting the CLR bit of the CSR
The Carrier (CD) and Ring (RI) bits in the MSR are read-only bits. The program can determine the
current state of the Carrier signal for a line by examining the appropriate bit in the high byte of the MSR It
can determine the current state of the Ring signal for a line by examining the appropriate bit in the low byte
of the MSR. The program can examine these registers at different times by using move byte or bit test byte
instructions, or can examine them as a single 16-bit register by using move word or bit test word
instructions. The DZQ 11 modem control logic does not interrupt the processor when a Carrier or Ring
signal changes state. The program should regularly sample these registers to determine the current status.
Sampling at a high rate is not necessary.

4-4