Digital PDFs

EK-DYS50-TM-001

January 1983

164 pages

Original

6.4MB

Document:	DYS50 Technical Manual
Order Number:	EK-DYS50-TM
Revision:	001
Pages:	164
Original Filename:	http://bitsavers.org/pdf/dec/qbus/EK-DYS50-TM-001_DYS50_ISV11_Technical_Manual_Jan83.pdf

OCR Text

EK-DYS50-TM-001

DYS50
Technical Manual

Prepared by Educational Services
of
Digital Equipment Corporation

1st Edition, January 1983

Copyright © 1983 by Digital Equipment Corporation
All Rights Reserved
The reproduction of this material, in part or
whole,
is
strictly
prohibited.
For
copy
information, contact the Educational Services
Department,
Digital
Equipment
Corporation,
Maynard, Massachusetts 01754.
The information in this document is subject to
change
wi thou t
not ice.
Dig i ta I
Equ i pmen t
Corporation assumes no responsibility for any
errors that may appear in this document.
Printed in U.S.A.

Mate-N-Lok is a trademark of AMP, Inc.
The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts.

~DmDDmD

DECdataway
DECsystem-10
DECSYSTEM-20
DECUS
DECmate
DECnet

DECwriter
DIBOL
MASSBUS
PDP

RSTS
RSX
UNIBUS
VAX

P/OS

VMS

Professional
Rainbow

VT
Work Processor

CONTENTS
PREFACE
CHAPTER 1

INTRODUCTION

1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.4
1.4.1
1.4.2
1.5
1.6
1.7

Definition and Scope •••.•••..•••.••••.••••.•.•••
Introduction ••..••••••••••••••••••.••••.••••••••
Features

•............•..•.............•......•..

KDFII-BB Processor (M8189) ••••••••••••.•.••.
MS V11-P K Mem 0 r y ( M8 0 67 - KA ) •.••.•..••••.•.•••
ISVII-B DECdataway Interface ••.••••••••••••.
BAI1-Y Mounting Box ••••••••.••••..••••.•.•••
General Description ••••.•••••••••••••.••••••.•••
DY Systems

••••••••••••••••••••••••••••••••••

DYS50 Functional Description ••.•••••••...••.
Typical DYS50 Cabinet Configurations ••••.•.••••.
Related Documents .•••••••••••••••••••••••••.•••.
Specifications

..................................

CHAPTER 2

INSTALLATION

2.1
2.2
2.2.1
2.2.2
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.2
2.4
2.5
2.6
2.6.1
2.6.2
2.7
2.8
2.8.1
2.8.2
2.9
2.10
2.11
2.12
2.12.1
2.12.2
2.12.3
2.12.4
2.13
2.13.1
2.13.2
2.14

Introduction
Site Preparation ••••.••.•••••••..•..•.••.•.••••.
Site Power Requirements ••••..••••••.••.•••••
NEMA Enclosure Requirements ..•••.•••••.•.••.
DYS50 Unpacking and Inspection •••••••.••••.••••.
Factory Conf igured Uni ts •••••••••.••••.•.••.

....................................

Unpacking . . . . • • . • . . . . . • . . • . . . . • . . . . . . . • .

Inspection •••••••••••••••••••••••••••••.
Separate Uni ts •••••••••••••.•••••.•••..•.•••
DYS50 Switches and Indicators •••••••••••••.•.•••
Preliminary Configuration ••••.•.••••••••••.•.•••
Mounting the DYS50 ••••••••••••••••••••••••••.•••
Non-standard Enclosure Mounting •••••••••.••.
Standard Cabinet Mounting •••••••••••••.•.•••
Cabinet AC Power Check •••••••.••••••••••••••••••
DC Voltage Measurement •••.••••••••••••••••••.•••
Measurement of +5 Vdc ••••.•••••••.••• )•••.•••
Measurement of +12 Vdc ••••••••••••••••••.•••
Off-Dataway Operation •••••••••••••••••••.•••.•••
DYS50 to DECdataway Interface •••••••••••••••••••
On-Dataway Operation ••••••••••••••••••••••••••••
DYS 5 0 Pe rip her a 1 In t e r fa c e s •••••••••••••••••.•••
Standard Interfaces •••••••••••••••••.•••••••
Fi 1 ter ed In ter faces •••••••••••••••••••••••••
H349 Distribution Panel ••.••••••••••••••.•••
DYS50 to I/O Subsystem Interface ••••••••••••
Expanding an Existing System •.••••••••••••••.•••
Add i ng New Mod u1es ••••••••••••••••••••••••••
Adding an Expansion Chassis •••••••••••••.•••
Performance Verification ••••••••••••••••••••••••

iii

1-1
1-2
1-2
1-3
1-3
1-3
1-3
1-3
1-3
1-6
1-7
1-10
1-11

2-1
2-1
2-1
2-3
2-3
2-3
2-3
2-4
2-5
2-9
2-12
2-14
2-14
2-14
2-18
2-18
2-18
2-19
2-19
2-20
2-20
2-20
2-20
2-21
2-21
2-23
2-23
2-24
2-24
2-24

CHAPTER 3

MAINTENANCE

3.1
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.2
3.2.3
3.2.3.1
3.2.3.2
3.2.4
3.2.5
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.6
3.6.1
3.6.2

Overview ••••••••••••••••••••••••••••••••.•••.•••
Troubleshooting Tools •••••••••••••••••••••••••••
Maintenance Software (Diagnostics) •••••••.••
System Level Diagnostics •••••••••••••.••
Standalone Di agnostics •••••••••••••••.••
Hardware Troubleshooting •••••••••••••.•••••••
Built-in Diagnostics •••••••••••.••••••••••••
Hardcore Tests ••••••••••••••••••••••••••
Softcore Tests ••••••••••••..••••••••••••
ISV11 Indicators ••••••••••••••••••••••••••••
DYS50 Troubleshooting Flowchart •••••••••••••
I SV11-B Troubleshoot i ng •••••••••••••••••••••••••
Routine Maintenance ••••••••••••••••••••• ~ •••••••
Unit Removal and Replacement ••••••••••••••••••.•
Replacement of the BA11-Y Box •••••••••.•••.•
Module Insertion and Removal ••••••••••••••••
Fan Removal and Replacement •••••••••••••••••
Power Supply Removal and Replacement ••••••••
Control Module Replacement (Bezel) ••.•••••••
Backplane Replacement •.•••••••••••••••••••••
DC Voltage Measurement and Adjustment •••••••••••
Measurement ••••••.•••••••••••••••.••••••••••

CHAPTER 4

ISVI1-B DESCRIPTION

4.1
4.2
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.3
4.3.3.1
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.5
4.5.1
4.5.1.1
4.5.1.2
4.5.2
4.5.3
4.5.3.1
4.5.3.2
4.5.4

Introduction •.••..••..••••••••••••••••••.•••••••
ISV11-B Application ••.••••..••••••••.••.••••••••
Typical DY System .•••.•••.•••.••••••..••••••••••
DY System Host •••.••••••••••.••••.••••••.•••
DY System Communication Link ••••.•••••••••••
DECdataway Cable .•••••••••••••••••••••••
DECdataway Controller (ISB11) •••••••••••
DECdataway Connectors •••••••••••.•••••••
DECdataway Terminators •••••••••.••••••••
DY System Remote Devices ••••••••••••••••.•••
Typical DIS •••••••••••••••••••••••••••••
Functional Description of the ISV11-B ••••••••••.
ISV11-B Processor and Memory .•••••••••••••••
ISV11-B to DECdataway Interface •••••••••••••
ISV11-B to LSI-II Interface •.•••.•••••••••••
ISV11-B Operation •••.••••••••••••••.••••••••
ISV11-B Maintenance .••.••••••••••••••••.••••••••
Built-In Diagnostics .••••••••••••••.••••••••
Hardcore Tests ••.•••.•••••••••••••••••••
Softcore Tests ••••••••••••••.•••••••••••
ISV11 Indicators •••.•••••.•••••.•••.••••••••
Te s t Po i n t s .....•.....••....•.•..•..••..•...
M8080 Test Point Description •••••.•••••••
M8084 Test Point Description ••••••••••••
Module Troubleshooting •.••••••••.•••••••••••

3-1
3-2
3-2
3-2
3-3
3-3
3-3
3-4
3-4
3-4
3-4
3-7
3-7
3-8
3-8
3-10
3-11
3-13
3-13
3-16
3-16
3-17
Adjustment •••••••••••••••••••••••••••••••••• 3-18

4-1
4-2
4-2
4-3
4-3
4-3
4-3
4-3
4-4
4-4
4-4
4-4
4-4
4-4
4-6
4-6
4-6
4-6
4-7
4-8
4-8
4-10
4-10
4-10
4-12

4.5.4.1
4.5.4.2
4.6
4.7
4.8
4.8.1
4.8.1.1
4.8.1.2
4.8.1.3
4.9
4.9.1
4.9.2
4.9.3
4.10
4.11
4.12

Quick Check for Major Problems ••••..••.•
Manual Modem Test ••.••••.•....•••••••.••
ISVII-B Detailed Description ••••••••••.•••.•••.•
Processing unit ••••••••••••.••••••••••••••.••.••
Serial Line Unit ••••••••••••••••••••••••••••••••
Serial Transmitter-Receiver ••••••••••••.•..•
Tr a n sm i t te r ••••••••••••••••••••••••.••••
Receiver •••••••••••.••.••••••••••••.••••
Negative Voltage Converters ••••••••••.••
LSI-II Bus Interface •••••••.•••••••••••••••.••••
Port Transfers •••••••••••••••••••••.••••••••
LSI-II Interrupt Control ••••••••••••••••••••
DMA Transfers ••••••••••.•••••••••••••••.••••
Functional Flows •••••••.••••••••.••••••.•••.•.••
Specifications •••••••••••••.•••••••••••••••.••••
ISV1I-B Signal Glossary •••..••.••••.•••.•...••••

CHAPTER 5

BAII-Y POWER SYSTEM DESCRIPTION

5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
5.2.1
5.2.2
5.2.2.1
5. 2-;;2-~2
5.2.2.3
5.2.2.4
5.2.2.5
5.2.2.6
5.2.3
5.2.3.1
5.2.3.2
5.2.3.3

5.2.4

Introduction
AC Input Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H7861 Power Supply .•••..•••.••.•••..••..••.•
H9276 Backplane ••••••••••••••••••••••••.•.••
Front Bezel Assembly •••.•••••••••••.•••.••.•
Detailed Description •••••••.•••••••••••••••.••••
AC Input Panel ••••••••••••••••.••••••••.•.••
H786l Power Supply •••••.•••••••••••••••.•.••
. AC Input Circuit •••.••••••••••.••••.•..•
-f5 V----C-o-n-t-r-o-t---Ci rcu it •••••••••••••••••.••
+ 12 V Co n t r 0 1 C i r cui t •••••••••..••..•••.
+12 V/+5 V Regulators ••••••••••••••.•.••
POK/DCOK Circuits ••.••••••••••••••••••••
LTC Generator •••••..••••••••••.••••.•..•
H9276 Backplane ••••••••.••••••••••••••..••••
Extended LSI-II Bus Signals •••••••••••••
CD Bus Signals •••••.•••••••••••.•••••.••
Module Requirements for H9276
Capability •••••••••.•••••••••.•.••..••.•
Modules Designed for the H9276
Backplane Only ••••.•••••••••••..•••..•••
Electrical Protection for Quad-Height
and Double-Height Module ••••••..••••••••
Front Bezel Assembly •••.••••••••••..•••.•.••

APPENDIX A

DYS50 KERNEL SYSTEM CONFIGURATION

APPENDIX B

SPECIAL CIRCUITS

B.l
B.2
B.3

DC003 Interrupt Control ••••.••••••••••.•••.••.••
DC004 I/O Address Decoder •.••••••••••••••••••.••
DC 0 0 5 Bus Tran s c e i v e r ••••••.••••.••••••••••••.••

5.2.3.4
5.2.3.5

....................................

4-13
4-14
4-15
4-17
4-18
4-19
4 - 21
4-21
4-26
4-26
4-27
4-28
4-28
4-30
4-37
4-38

5-1
5-3
5-3
5-3
5-3
5-4
5-4
5-4
5-8
5-11
5-14
5-14
5-17
5-23
5-23
5-24
5-26
5-29
5-30
5-31
5-32

B-1
B-1
B- 7

APPENDIX C
C.l
C.2
C.3

PDP-ll/23B BACKPLANE AND MODULE CONFIGURATION
Ge n era 1

•••••••••••••••••••••••••••••••••••••••••

Single-Backplane Configuration Rules
••••••••.•
Multiple-Backplane Configuration Rules ••.•.•••..

C-l
C-l
C-2

FIGURES
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
2-1
2-2
2-3
2-4
2-5
2-6

2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11

Basic DYS50
DYS50 Enclosure Features ••••••.•••••••••••••••••
A Typical DY System ••••••.••••.••.•••••••••••••.
A Single DYS50 . . . . . . . . . . . . . . • . . . . . . . . . • . . . . . . • . .
DYS50 Block Diagram •••••••••••••••••••••••••••••
H9646 Cabi net Conf igura t i on •••••••••••••••••••••
H9646 Cabi net Conf igur a t ion •••••••••••••••.•••.•
H960 Cabinet Configuration ••••••••••••••••••••••
H960 Cabi net Conf i gur a t i on ••••.•••••••••••••••••
Si te Power . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . .
DYS50 and Accessories •.•••••••••••••••••••••••••
Module Cover ••••••••••••••••••••••••••••••••••••
DYS50 Modules

•.•••••••.•••••••••.•••••••••••••••

Cove r Removal •••••••••••••••••••••••••••••••••••
Swi tches and Indicators •••••••••••••••••••••••••
Backplane Jumpers ••••.••••••••••••••••••••••.•••
Front Bezel Jumpers ••..••••••••••••••••••.••••••
NEMA Mounting ••••••••••••••••••••••••••••••••.••
Hinge Mounting •••••••..••.••••••••••••••••••••••
Standard Mounting •••••.•••••••••••••.•••••••.•••
DECdataway and Power •.••••••.•••.••••••••.•.••••
F i 1 t e r P 1 a c em e n t
•. . ••••••••••. •••••••••• ••••
H349 Distribution Panel •.••••••••.••••••••••••••
I / a Sub s Ystem In t e r fa c e •••••.•••••••.•••••••••••
I SVll Di splay ••••.••••••••••••••••••.•••••••••••
DYS50 Troubleshooting •.•••••••••••••••••••••..••
DYS50 Chassis Removal •.•.•••••••.•••••••••••..••
Module Replacement •.••.•.••.•.••••••••••••••.•••
Fan Replacement ••••.••.•.••.•.••••••••••••••••••
Power Supply Replacement •••••.••.•••.••••••••.••
Front Panel Bezel Module Replacement ••••••.•••••
Backplane Replacement •••••••••••••••••••••••.•••
DC Voltage Adjust ••••••••••••.••••••••••••••
ISVII-B Option -- DECdataway to LSI-II
Bus Interface ••••••••.••.••••••••.••••.••••••
A Typical DY System •••••.•••••••••••••••••••••••
DIS with ISVII-B Interface •••••••••••••••••••.••
ISVII Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISVII-B Modules (Edge-On)
.••••••••••.•••••••
M8~80

Module •••••••••••••••••••••••••••••••••.••
M80'84 Module •••••••.••••.••••.••••••••••.•••••••

ISVII-B Logical Organization ••••••••••••••••••••
Transmitter Timing •.•••••••••••••••••••••.••••.•
Receiver Simplified Block Diagram •••••••••••••••
Receiver Timing .••••••••••••••••••••••••••••••••

1-2
1-4
1-5
1-7
1-7
1-8
1-8
1-9
1-9
2-2
2-5

2-7
2-7
2-8
2-9
2-12
2-13
2-15
2-15
2-16
2-17
2-21
2-22
2-23
3-5
3-6
3-9
3-10
3-12
3-14
3-15
3-17
3-18
4-1
4-2
4-5
4-9
4-11
4-11
4-12
4-16
4-21
4-22
4-23

4-12
4-13
4-14
4-15
4-16
4-17
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
A-I
A-2
A-3
A-4
A-5
A-6
B-1
B-2
B-3
B-4
B-5
B-6
B-7
B-8
C-1

Se ria 1 Lin e Ou t •••••••••••••••••••••••••••••••••
Serial Line In ••••••••••••••••••••••••••••••••••
DMA Transfer Out ••••••••••••••••••••••••••••••••
DMA Transfer In ••••.••••••••••••••••••••••••••••
ISVl1-B Interrupt Request to LSI-II •••••••••••••
LSI Interrupt Request •••••••••••••••••••••••••••
BA11-Y Major Assemblies •••••••••••••••••••••••••
BA1l-Y Functional Block Diagram •••••.••••••••••.
BA11-Y Interconnections ••••••••••• ~ •••••••••••••
AC Inpu t Schema tic •••.••••.•••••••••••••••••••••
H7861 Block Diagram ••••••••••••••••••••••••••••.
Inverter Circuit •••.••••••••••••••••••••••••••••
Current/Voltage Relationship in T3 ••••••••••••••
+5 V Control Circuit ••••••••••••••••.••••••••••.
3524 IC Block Diagram •••••••••••••••••••••••••••
Timing, +5 V Control Circuit ••••••••••••••••••••
+12 V Control Circuit •••••••••••••••••••••••••••
Block Diagram, NE555 ••••••••••.•••••••••••••••••
Timing, +12 V Control Circuit •••••••••••••••••••
+12 V Regulator ••••.•••••••••••.••.•.•••••••••••
+5 V Regulator •••••.••••••••••••••.•••••••••••••
Power-Up/Power-Down Timing ••.••••••.••••••.•••••
POK/DCOK Circuits •••••••••••••••••••••••••••••••
DCOK Power-Up Timing •••••••••••••••••••••••••.••
Power-Down Timing ••••••••••••••••••••••••••••••.
LTC Generator •••••••••••••••••••••.•••••••.••.••
H9276 Backplane •••••••••••••••••••••••••••••••••
Interrupt Acknowledge and Bus Grant Signal
Interconnection, H9276 Backplane ••••••••••••••••
CD Bus Interconnections •••••••••••••••••••••••••
H9276 Backplane Wiring (Rows A and C) •••••••••••
Front Panel Logic ••••••••••••••••••••••••••••.••
RUN Indicator Waveforms •••••••••••••••••••••••••
DYS50 Kernel System Backplane Configuration •••••
DYS50 Bezel printed Circuit Board Factory
Configuration ••••••••••••••••••••••••••••••••.••
Factory Configuration of the KDF11-BB (M8l89)
in the DYS50 •••...••.•...••..••.•.•.•••...•...••
Factory Configuration of the MSV1l-P (M8067-KA)
in a DYS50 ••••••••••••••••••••••••••••••••••••••
ISV11-B M8080 Module Standard Configuration •••••
ISV11-B M8084 Module Standard Configuration ••.••
DC003 Simplified Logic Diagram ••••••••••••••••••
DC003 Interrupt Section Timing Diagram ••••••••••
DC003 Interrupt Section Timing Diagram
sections A and B ••••••••••••••••••••••••••••••••
DC004 Simplified Logic Diagram •••••••••••••••.••
DC004 Timing Diagram ••••••••••••••••••••••••••••
DC004 Loading Configurations ••••••••••••••••••••
DC005 Simplified Logic Diagram ••••••••••••••••••
DC005 Timing Diagram ••••••••••••••••••••••••••••
PDP-1l/23B (H9276) Single Backplane
Configuration ••••••••••••••••••••••••••.•••••.••

vii

4-31
4-32
4-33
4-34
4-35
4-36
5-1
5-2
5-5
5-6
5-7
5-9
5-10
5-12
5-12
5-13
5-15
5-16
5-16
5-17
5-18
5-18
5-19
5-20
5-22
5-23
5-24
5-25
5-27
5-30
5-33
5-34
A-I
A-2
A-3

A-4
A-5
A-6
B-2
B-3
B-4
B-5
B-6
B-7
B-8
B-9
C-1

C-2
C-3

PDP-ll/23B (H9276) Two Backplane
Configurations •••••••..•••.••••.••.••.••...•••.•
PDP-ll/23B (H9276) Three Backplane
Configurations .•.••••.•••••••••••••.••••••••••.•

C-3
C-4

TABLES
2-1
2-2
2-3
2-4
4-1
4-2
5-1
5-2
5-3
5-4

Box Contents •.•••.•••.•....••.•••..•.••••••...•.
DYS50 Switches and Indicators .•••..••••••..••••.
Backplane Factory Jumper Configuration ••.•••.•••
Bezel Assembly Factory Jumper Configuration •••.•
Hardcore Tests .•.•••.••••••...•••••••.•••.••••.•
Softcore Tests ••••.•.•••••••.••.••••.•••..••••..
Extended LSI-II Bus Signal Pin Assignments •••..•
CD Bus Signal Pin Assignments .•.•••.••••.•••••..
CD Bus Signals for H9276 Compatible
Quad Modules .•••.•.•••••••••.•.•••••••••.••.••.•
Vulnerable CD Bus Double Module Connector Pins ..

viii

2-6
2-10
2-13
2-14
4-7
4-8
5-25
5-28
5-29
5-32

PREFACE

This hardware technical manual, like most technical manuals, tends
to be all-inclusive. The information is not restricted to a single
audience. It is addressed instead to several audiences -- none of
which is expected to be interested in the entire document.
Individual chapters, however, are audience-specific. For those who
want to know what to read, and what not to read, the following
describes the chapters.
Chapter 1
Introduction
This chapter defines the DYS50. The chapter is for the individual
who wants a quick summary of: the DYS50's function, its
relationship to the DECdataway, and its available options.
Chapter 2
Installation
This chapter contains the information and level-of-detail needed
by individuals who do the installation. It tells how to unpack,
inspect, mount, and power-up the DYS50. It also tells how the unit
should operate when first turned on, and how to implement some of
its interfaces.
Chapter 3
Maintenance
This chapter is for the Field Service or other maintenance person
who troubleshoots and repairs a failed DYS50. It tells how to
isolate a faulty Field Replaceable Unit (FRU) , and, once found,
how to replace it with a new FRU.
Chapter 4
ISVII-B Description
The first few paragraphs of this chapter are of general interest.
They contain a short functional description of the ISVII-B. The
remainder of the chapter contains a detailed description of the
ISVII-B logic as shown in the field maintenance print set. It is
included
so
that
engineers
and
component-level
service
technicians will have a permanent record of this information.

Chapter 5
BAII-Y Power System Description
Th i s c hap t e r con t a ins a com pIe t e ph Ysic a I and e I e c t ric a I
description of the BAII-Y mounting box. That is, the box that the
DYS50 modules are plugged into. It describes in detail: all power
supply circuits, power distribution, and all backplane and chassis
wiring for the entire BAII-Y box. It is included here for
reference,
and
so
that
engineers
and
component-level
troubleshooting technicians will have a permanent record of this
information.

CHAPTER 1
INTRODUCTION

1.1
DEFINITION AND SCOPE
The DYS50 is an LSI-ll/23B microcomputer with a DECdataway network
interface. This configuration is called a DECdataway Intelligent
Subsystem (DIS). The DYS50 functions as a fully programmable
OECdataway network node.
It operates
in an execute-only
environment under the RSXll-S operating system. It is not a
development subsystem.
The DYS50 is a product of DIGITAL's Manufacturing Distribution and
Control (MDC) group. This group designs hardware and software for
industr ial local-area netwo r ks called DECdataway (OY) systems.
OYS50s are the intelligent elements in these networks.
The DECdataway al so supports other devices besides DYS50s, but
the sea r e f ull y de sc r i be din the i r 0 wn man u a Is. Th ism a n ua 1 i s
about the DYS50 only. Moreover, it is strictly a hardware manual.
It . tells what a DYS50 is, and how to install, operate,
troubleshoot, and maintain it. It contains functional and physical
descriptions of the DYS50 subsystem and a detailed description of
its DECdataway interface, the ISVll.
Where appropriate, some ancillary topics are discussed, but not in
any depth. For example, this manual does not fully describe: the
DECdataway, the DYS50's processor, its memory, or its peripherals.
These devices are not unique to the DYS50. Their detailed
descriptions are contained in separate manuals. Neither does this
manual describe DYS50 operating or maintenance software. These
subjects also are fully discussed in separate manuals.
Finally, a DYS50 installation presumes a DY network installation.
This manual is, therefore, just a small part of your total system
documentation package. The total package incl udes not only all
documents for your particular DY system's hardware complement, but
several DY system operating and maintenance software documents as
we 11 • Par a 9 r a ph 1. 6 1 i s t s s e v era I ex i s tin g doc um en t s t hat
specifically address th~se topics.

1-1

1.2

INTRODUCTION

Figure 1 shows a DYS50 wi th its front door removed and module
cover cut away. It consists of a mounting box and four modules.
From the top, the four modules are: a processor, memory, and
DECdataway interface (2 modules). The following describes the
modules further.
BAll-YA

Mounting box with power supply, backplane, and
front panel controls

KDFll-BB

Processor (M8l89 module)

MSVll-PK

256 KB memory (M8067-KA module)

ISVll-B

DECdataway interface (consisting of an M8080
module,
an
M8084
module,
and
an
interconnecting cable)

There are five empty slots for peripheral interface options.

1.3

FEATURES

Components of the DYS50 have a number of significant features
that, taken together, make it an efficient and versatile performer
in most any distributed processing application. A brief summary of
the important features follows.

~~~--TT-l:- PROCESSOR (M8189)

MEMORY (M8067-KA)

BAll-Y MOUNTING BOX

MA-0208-82

Figure 1-1

Basic DYS50

1-2

1.3.1
KDFII-BB Processor (M81a9)
This quad-height module contains: a central processor, memory
management, line frequency clock, BDVll compatible bootstrap and
diagnostic ROM, two serial line units, floating point, and 22-bit
addressing.
1.3.2
MSV11-PK Memory (M8067-KA)
Th i s qua d - he i g h t mod u I e con t a ins 1 2 8 K wo r d s 0 f met a lox ide
semiconductor (MOS) random access memory (RAM). Words are l8-bits
-- 16 data and 2 parity.
1.3.3
ISV11-B DECdataway Interface
This unit consists of two modules: the M8080 and the M8084. They
are connected together with a short ribbon cable. The ISVll-B is
the DYS50's interface to the DECdataway and the host computer. It
has in it a microcomputer that is programmed to manage
communications between the host and the DYS50's LSI-ll/23B. It
starts, stops, boots, and runs power-up diagnostics on the DYS50.
Chapter 4 contains a complete description of the ISVll-B.
1.3.4
BAll-Y Mounting Box
This is the DYS50 enclosure (Figure 1-2). It contains an H9276
nine-slot, extended· (22-bi t) LSI-ll/23 backplane, and an H786l
power supply that provides +5 volt, and +12 volt power to the
backplane. The BAll-Y is just 26.67 cm (10.5 inches) high, and
only 27.94 cm (11 inches) deep. All modules, cables, controls,
adjustments, and test points are front-accessible, which makes the
DYS50 very easy to service. The BAll-Y is equipped for easy
mounting in ei ther a NEMA-12 industr ial type enclosure, or in a
standard cabinet. Both the backplane and power supply are Field
Replaceable Units (FRUs); they can be swapped in a matter of
minutes.
1.4
GENERAL DESCRIPTION
The best way to understand how a DYS50 works is to look at its
relationship to the DY system of which it is a part. For that
reason, we will begin with just a brief, and much simpli.fied
descr iption of how a DY system works. Readers interested 1n a
comprehensive treatment should consult the references listed in
Paragraph 1.6.
1.4.1
DY Systems
In its simplest form, a DY network has a centrally-located (host)
computer, and mul tiple, remotely-located, smaller computers. The
remotes can be placed anywhere in the local area where dedicated
processing is needed. Completing the network is a communication
channel called the DECdataway, which connects the host and all
remotes together (Figure 1-3).
As the figure shows, DYS50s are the distributed elements of the
network. The host system can be either a VAX/VMS or PDP-II
computer, running RSXll-M or RSXll-M PLUS.

1-3

FOR STANDARD
MOUNTING

FRONT ACCESS TO ALL
CABLES, MODULES
ADJUSTMENTS

SPRING HINGED P.S.
FOR EASY SERVICE OR
REPLACEMENT
P.S. ADJUSTMENT
MA-0230-82

Figure 1-2

DYS50 Enclosure Features

1-4

HOST

r----'
I ISBl1-A I
I
I

---l--~E t~aW_aY ~,....r-----..,
...
Cd.. a...

~_I_
I

ISVll-8:

DYS50

- - -

DYS50

' - - - - . - - - ...._.,....---..J

I
I
TASK1

TASK 2

_ _.......

I -, r-I,

: OTHER

I ISV11-B I

I DECdataway I
I OPTION
I L.. -

L - r -

I
-

-I

I OTHER
I oECdataway I
I OPTION

TASK 3

J '----.--DYS50
'- - r _.J
TASK n-1

TASK n
MA-0216-82

Figure 1-3

A Typical DY System

Because they are linked by the DECdataway, DYS50s are DECdataway
subsystems, and because they are programmable they are called
intelligent subsystems. Thus the name: DECdataway Intelligent
Subsystem (DIS).
DYS50s are fully programmable and are therefore not dependent on
the host for performance at their dedicated functions. What role
does the host play? The host is able to communicate with all
DYS50s
via
the
DECdataway.
It
can,
therefore,
effect
communications between tasks in different parts of the network.
It can also start, stop, and monitor the progress of each DYS50
task so that a large system can be sensibly managed by controlling
all its subsystems in a manner that optimizes total system output
and economy.
The economies are of several types. For example, DYS50s are fully
programmable, but they serve local processing needs in an
execute-only mode. They do this by running programs that have been
developed at the host and down-line loaded to them via the
DECdataway. Thus the additional hardware and software tools
normally needed for program development are. required only at the
host -- a considerable economy in a large system.
Other economies are achieved because the host can also share its
database or mass-storage devices with the remote systems. All this
is in addition to the fact that distributing the processing power
in the first place breaks an entire project into smaller, more
manageable tasks, and in so doing it achieves economies of
convenient location, reduced wiring costs, modularity, and
improved response.

1-5

Fin a 11 y t he n , a 1 tho ug h DY s Ys t em i mpI em en tat ion sma y va r y
considerably' from one application to another, they have in common
a major attribute: they modularize a large task into several
smaller, more manageable ones, which can be physically dispersed
for optimum convenience and efficiency. And the DYS50 is the
principal means of accomplishing this modularization.
1.4.2
DYSSB Functional Description
Recall that a DYS50 runs its own local programs, and that the
DECdataway networ k host relates to it and all othe r DECdataway
devices as a sort of manager. Figure 1-4 shows the physical
relationship between a single DYS50 and: the DECdataway, the host,
and the local task. From this figure it can be implied that the
DYS50 needs at least three things: a DECdataway interface, a local
task interface, and a comp~ter to run the programs.
A block diagram of the DYS50 only (Figure 1-5) shows this in more
detail. The figure is a familiar enough looking LSI-II computer
block diagram with the exception of the block labeled DECdataway
inter face, wh ich makes the DYS50 funct ionall y unique. It is the
only part of that figure that requires further discussion in this
manual, and a complete description of it is presented in Chapter
4. Discussions of the LSI-II/238 computer and its various I/O
options are contained in the references.
The ISVII-B takes DECdataway ser ial-type messages, which are in
DIGITAL ser ial bus control (DSBC) protocol format, and converts
them to LSI-II bus-compatible parallel address and data format.
It then makes a DMA transfer of this data to the DYS50' s LSI-II
memory. It performs the reverse of this process when transferring
DYS50 data to the DECdataway.
The DYS50 normally serves its local function by running its
program and processing interrupts until it receives a message from
the host via the DECdataway. The message may contain a command for
the DYS50 to start, or halt, or perhaps simply receive or transmit
some data. The DYS50 responds as it would to any other device in
its I/O page. Of course, in addi tion to the hardware, there is
network software that must be in place (both in the host and the
DYS50) to make it all work. These matters are the subject of
several references listed in Paragraph 1.6.

1-6

,....-- - -oECdataway

HOST

t-----~

DYS 50

MA-021S-82

Figure 1-4

A Single DYS50

oECdataway

DYS 50

LSI-ll/238 (KDFll-8)
PROCESSOR WITH
MEM MGMT AND
FLOATING POINT

128W MOS MEM
WITH PARITY (MSV11-PK)

I/O INTERFACE OPTIONS
• IPV12 (M7959)
• DZVll (M7957)

LOCAL TASK INTERFACE
FOR EXAMPLE:
• PROCESS CONTROL
• TERMINAL CLUSTER

MA-0213-B2

Figure 1-5

DYS50 Block Diagram

1.5
TYPICAL DYS5a CABINET CONFIGURATIONS
Figures 1-6 and 1-7 show some typical configurations for H9646
cabinets. These figures show equipment that would be used with the
DYS50 in a process control application. Figures 1-8 and 1-9 show
similar equipment configured in an H960 cabinet.

1-7

•

H332
-SCREW
TERM.

IPV12

-I/O
(H334)

-DYS50

_BAll-Y
EXPANDER

r!!::.

874
POWER CONTROll ER

u;r=r

.!!:.

Figure 1-6

;(0=0,)

DoDo·

- DDD

H349
DISTRIBUT ION
PANEL

I-

tL..;,

10£]

.. co

.n.

c!6

c!!:.
MA·0251·82

H9646 Cabinet Configuration

1c===J c===J1

RX02
~ DISK

~
f--

,....-

IPV12
~ I/O
(H334)

..... H332

SCREW
TERM.

'-----

~ DYS50

I-

H34 9
DIS TRIBUTION
PAN E l -

BAll-Y
~
EXPANDER

r!!::.

r--

Figure 1-7

"!;'

DoDo·

DDD

I-

CI
<!!:a

;(0=0)

874
PO W E R CO NTROllER

H9646 Cabinet Configuration

1-8

QL.;,

10£]
~
c!6

.n.

.. co co

cor

c!!:.
MA·0249-82

iI
-

H332
SCREW
TERM.

r---

H332
_SCREW
TERM.

1=======

i---

IPV12

_H334
I/O

1-1 /0
( H334)
L----

F====='-

I- DYS50
~D=D"

BA11-Y
EXPAND ER

Figure 1-8

...

86 1
POWER
CONTROllER

D Dr,

DOD
0

0000
0000

...

I.ID oo~

.=. 00

MA-0250-82

H960 Cabinet Configuration
,J

I
1c:=::=Jc:=::=J1

349
_
H
DI STRIBUTION
PANEl

RX02

+--DISK

t J

r----

H332
.... SCREW
TERM.

I PV12
~I /0
( H334)

F====='-

I..---

l+- DYS50

H349
DISTRIBUT ION
--+
PANEL

BA11-Y
+EXPAND ER

-15

Figure 1-9

861
POWER
CaNTRall ER

H960 Cabinet Configuration

1-9

-..

D O~'

DOD

...
~

•

~D=D"

0000
0000

....

0
o~~
.=. 00
I.ID

MA-0248-82

1.6

RELATED DOCUMENTS

The following documents are shipped with your DYS50.
Title

Document Number

DYS50 Technical Manual
DYS50 Pocket Service Card
KDFll-BA CPU Module User's Guide
MSVll-P User Guide

EK-DYS50-TM
EK-DYS50-PC
EK-KDFEB-UG
EK-MSVQP-UG

DYS50 Field Maintenance Print Set
KDFll-BA Field Maintenance Print Set
MSVll-P Field Maintenance Print Set
ISVll-B Field Maintenance Print Set
BAll-Y Field Maintenance Print Set

MP-0l403
MP-02l36
MP-0l239
MP-00609
MP-0l402

Microcomputer Interfaces Handbook

EB-20l75-20/80

The following related documents can be ordered from:
Digital Equipment Corporation
Accessories and Supplies Group
P. O. Box CS2008
Nashua, New Hampshire 03061
Title

Document Number

Digital Site Preparation Guide
I/O Subsystem User Guide
DECdataway User Guide
DPM Diagnostic User Guide
VAX-II DY32 Hardware Installation
and Diagnostic User Guide

EK-OCORP-SP
EK-0PIOS-UG
EK-ISBll-UG
EK-DPM00-DM
EK-0DY32-UG

Serial Bus Exerciser Write Up
Remote Terminal Tester Write Up
Diagnostic Monitor Write Up

MD-ll-CZKCH-D
MD-Il-CZKCI-D
MD-Il-CZKMP-D

DPM/DPM-PLUS Documentation Set
consisting of the following:
DPM/DPM-PLUS Dataway Intelligent
Subsystem User Guide

AA-J529B-TC

DPM/DPM-PLUS Terminal User Guide

AA-J530B-TC

DPM/DPM-PLUS System Generation
and Management Guide

AA-J53lC-TC

DPM/DPM-PLUS Release Notes

AA-K160B-TC

DPM/DPM-PLUS Mini-reference

AV-M195A-TC

1-10

In addition to documentation, DYS50 maintenance training is also
available from DIGITAL. Contact your local DIGITAL representative
for details.
1.7
SPECIFICATIONS
The following are the specifications for the DYS50.
CPU

KDF11-BB

Memory

128K words MOS memory

Voltage/Current
DYS50 AID
Frequency
Power
Ride-through
Input protection

6 A maximum at 115 V
3 A maximum at 230 V
47 Hz to 63 Hz
690 VA, PF=0.6 mlnlmum
15 milliseconds minimum
Fast-blow fuse: 10 A for 115 V
operation,S A for 230 V operation

Environmental
NOTE
When other equipment is mounted in the
same cabinet as a
DYS50,
use the
environmental limits of the product with
the minimum environmental capability.
Temperature
Operating
Nonoperating

50 to 50 0 C ambient
0
0
(41 to 122 F)
0
0
_40 to 66 C ambient
0
0
(-40 to 151 F)

NOTE
The
maximum
allowable
operating
temperature is based on operation at sea
level. The maximum allowable operating
teml6erature is reduced
by a factor of
o
1.8
C/I""" m (I.e
F/l"ee ft) for
operation at high altitudes.
Humidi ty
Operating

Nonoperating
Altitude
Operating
Nonoperating

10 0 percent ~o 95 percent RH
36 C (89.8 F) maximum wet bulb
2 C (35.6 F) minimum dew point
10 percent to 95 percent RH
(noncondensing)
2 • 4 km

( 8 , '" 0 0 f t)

9. 1 km

( 3 0 , 0 0 0 f t)

1-11

Physical
Height

26.416 cm (10.4 in)

Width

48.26 cm (19 in)

Depth (with door)
(without door)

32.537 cm (12.81 in)
29.464 cm (11.6 in)

Weight

20.9 kg

(46 lbs)

ADDITIONAL SPECIFICATIONS
Specifications for all LSI-II microcomputer components contained
in the DYS50 are provided in the Microcomputer Processor Handbook
and the Microcomputer Interfaces Handbook.
Specifications for the remaining DYS50 components, except the
ISVII-B, are provided in their respective user guides. The
appropriate manuals are shipped with each system. Specifications
for the ISVl1-B are listed in Chapter 4.

1-12

CHAPTER 2
INSTALLATION

2.1
INTRODUCTION
Th i s c hap te r tell s how to ins tall the DYS 5 0 • In c 1 u d e d a r e
instructions for unpacking, inspecting, interfacing, connecting
primary power, and preparing the system for operation. Finally,
there is a short checkout procedure that establishes whether or
not the basic DYS50 is operational.
The chapter does not cover installation of peripheral devices that
interface with the DYS50. It covers only: installation of the
basic DYS50, its interfaces, and some guidelines for its
expansion. Peripheral devices for the DYS50 are installed per
instructions in their respective manuals, one of which is included
with each device. These manuals are referenced where appropriate.
Chapter 1 includes a list of documents shipped with the basic
DYS50.
2.2
SITE PREPARATION
The DYS50 is only one of several devices that can be connected to
the DECdataway, and is only one part of a larger host-based
system. Th is means tha t i t s site preparat ion is prov ided for in
the pr epa r at ions fo r the DECda taway. Therefor e its ass igned
location should have a DECdataway remote device interface
connector and the appropriate primary power receptacles.
Final positioning of a DYS50 cabinet must allow sufficient
clearance from any obstruction that might hinder air flow to the
cabinet, or easy access by service personnel.
CAUTION
To maintain stability in operating and
servicing
positions,
DYS5~
cabinet
configurations must be secured to the
floor or an adjacent cabinet.
2.2.1
Site Power Requirements
Site Power Receptacles do not necessarily mate directly with the
DYS50. And which receptacles are requi red depends not only on
whether the DYS50 is 115 Vac or 230 Vae, but also on whether or
not a cabinet power controller is being used. The power controller
requirements are different because, since it usually powers more
than one device, its current rating is higher.
2-1

For example, if the DYS50 is going to plug directly into a site
power receptacle, then that receptacle must be, for example,
either a type A or type B (for 115 Vac or 230 Vac operation
respect i vel y). If, on the other hand, the DYS50 is go ing to pI ug
into a cabinet power controller, the power controller must have
type A or B receptacles for the DYS50, but the power controller
itself requires a type C or D site power receptacle because of its
higher current rating. Refer to Figure 2-1.
Note that two power cords are provided with the DYS50. One is for
115 Vac service and the other for 230 Vac service as shown in
Figure 2-1. Use the one you need and discard the other.
Verify that the site power receptacle is the correct one, that it
is wired correctly, that the voltage is correct, and that the
receptacle is properly grounded. For a more complete discussion of
these matters, refer to the Digital Site Preparation Guide
(EK-OCORP-SP).
CABINET

r----------------------,I
115V LINE CORD
PART 17-00143-00

115V

DYS50

I
I

~----------------------~
CABINET

r----------------------·
230V LINE CORD
PART 17-143-01

DYS50

~~------~------------~o

IL ______________________

r----------------------II
CABINET

POWER CONTROL BUS

115V LINE CORD
PART 17-00143-00 ,....-1------------1
DYS50

POWER
CONTROLLER
115V

L ______________________

r----------------------.
I
\k
CABINET

POWER CONTROL BUS

230V LINE CORD
PART 17-143-01

POWER
CONTROLLER
230V

DYS50

L ______________________
NOTE:

CONFIGURATIONS A,B,C, AND D MATCH TEXT EXAMPLES

Figure 2-1

Si te Power

2-2

MA-0211-82

2.2.2
NEMA Enclosure Requirements
If the DYS50 is to be installed in a NEMA enclosure, the customer
must do some advance planning. DIGITAL does not sell NEMA type
enclosures; they must be provided by the customer. Moreover, the
c us t om e r mu s t de fin e the e qui pm en t con fig u rat ion t hat go e sin to
that cabinet. When spec i fying that conf iguration, the customer
must make allowances for: heat dissipation, primary power, and I/O
cabling. Refer to Paragraph 2.6.1 for NEMA enclosure mounting
instructions and dimensions.
2.3
DYS50 UNPACKING AND INSPECTION
Some DYS50s are shipped separately and some are already mounted in
cabinets with their customer chosen peripherals. If your's is a
separate unit skip to Paragraph 2.3.2. If it is mounted in a
cabinet continue.
NOTE
To protect the warranty, the custo~er
must not unpack the system unless a
DIGITAL representative is present.
2.3.1
Factory Configured Units
Perform the following unpacking and inspection procedure for all
single and multicabinet systems.
2.3.1.1 Unpacking
If the shipment must be moved from the
receiving area, make sure doorways and passageways are wide enough
to a'ccommodate cabinet pallets before trying to move equipment to
its selected location. Regardless of where unpacking and
inspection is done, do not remove containers from the pallets
until the shipment is examined for possible damage. (Reimbursement
for damaged goods removed from the pallet is difficult.)
Perform the following unpacking procedure.
1.

Make sure all containers are sealed. If any container is
open, record it on the Installation Report or Field
Service Report.

Check the shipment against the packing list to make sure
you have received the correct number and type of
containers. If the shipment is incorrect, notify the
salesman and/or customer, and the Branch Service Manager.
The customer should check with the carrier to locate any
missing items.

Check all containers for external damage. Look for dents,
protrusions, holes, and smashed corners. Note any damage
and record it on the Installation Report or Field Service
Report.

2-3

Open each container starting with the one marked "OPEN ME
FIRST." Locate the packing slip and check the contents of
each container against its respective slip. Identify any
missing items on the Installation Report. Save any ramps
that might come with pallet-mounted equipment.

If reshipment is a possibility, retain packing materials
such as foam fillers and plastic inserts. In any case,
retain the plastic (antistatic) bags in which any
individual modules are shipped.

2.3.1.2

Inspection -- Perform the following inspection procedure.

Inspect the outside of the equipment and/or cabinet (s)
for damage such as scratches, broken switches, and broken
stabilizer feet.

2•

Ins p e c t i n sid e the e qui pm en tan d /0 rca bin e t ( s) for
damaged components such as swi tches and ind icators, or
for loose and broken cable connections. Make sure all
modules are securely seated in their connectors.

Note any damage found and record it in the Installation
Report. Notify the Branch Service Manager immediately of
any damage found.

Inspect each cabinet and freestanding peripheral to make
sure it contains the items listed on the transfer sheet.
Check the eng ineer ing change order reVISIon (ECa REV)
level and serial numbers against the transfer sheet or
ECO status sheets. Record any missing items, incorrect
serial numbers, or incorrect revision levels on the
Installation Report.

When inspect ion is complete, remove the equipment and
cabinet(s)
from the shipping pallet. Remove the
cabinet(s) as follows.
a.

Unbolt cabinet(s) from the shipping pallet. The bolts
are on the lower supporting side rails of an H96QJ
cabinet, or at the four corners of an H9646 cabinet,
and can be reached from inside the cabinet.

Raise stabilizing
casters.

Attach enclosed ramp or use wooden blocks and planks
to form a ramp from pallet to floor. Carefully roll
cabinet(s) onto floor.

Install front stabilizer feet with hardware provided.

feet

2-4

above

the

level

the

2.3.2
Separate Units
All components of the basic DYS50 are shipped in a single carton.
Optional devices are shipped in separate containers, and may
require special unpacking procedures. Consult each option's own
documentation for details.
Perform the following unpacking procedure for the DYS50.
1.

Inspect the DYS50 package for any external indication of
shipping damage. Record any such indication on your Field
Service report.

Open the package and remove the contents. Compare the
contents wi th Figur e 2- 2 and Tabl e 2-1 and ver i fy tha t
all items have been received. Check all items for damage.
Record any shortages or damage on your Field Service
report.

230 VAC LINE CORD

HINGES

115 VAC LINE CORD
FUSE FOR
230V OPERATION

~~~

fttf

MA-022B-B2

Figure 2-2

DYS50 and Accessories

2-5

Table 2-1

Box Contents

Quantity

Description

1
1
1
1
1
1
1
1
4
4
4
5

DYS50 (with KDF11-BB, MSV11-PK, ISV11-B)
Door
Top hinge
Bottom hinge
120 Vac power cord
240 Vac power cord
DECdataway interconnect cable
Fuse 5A/250 V
Hinge mounting screws phI pan sems
DYS50 mounting screws trus phI sem 10-32 X 1/2
DYS50 mounting nuts, tinnerman, 10-32
Field Maintenance Print Sets (DYS50, BA11-Y, KDFI1-B,
MSVI1-P, ISV11-B)
Technical Manuals or User Guides (DYS50, KDFI1-B,
MSV11-P)
DYS50 Pocket Service Card

3
1

NOTE
An expander box has two 5 foot cables
(BC02D-05).
A second
expander
box
requires two 10 foot cables (BC02D-10),
which must be ordered separately. See
Appendix C for details.

Save the shipping container and all packing materials
until certain that return o r r e s h i pm e n t to an 0 the r
location is not necessary.

Place the DYS50 on a bench so that its front hangs over
the edge of the bench about 4 cm (1.5 inches). Remove the
front module cover by loosening the two knurled, captive
screws near the bottom of the uni t and pulllng out and
down (Figure 2-3). Slide the unit back on the bench.

Wi thout removing any modules, inspect for any bent or
broken indicators, connectors, or any other obvious
damage. The module configuration should match that shown
in Fig u r e 2 - 4 • Do not add any mod u 1 e s a t t his tim e •
Record any damage or shortages on the Field Service
report.

2-6

MA-0224-82

Figure 2-3

Module Cover

11~===========K~D~F~11~P~R;O;C;ES~S~O~R;(M=8;1=89=)==========~

~1============M=S=V=11~M~E:M~O~R~Y~(~800==7-=KA=)==========~

2
3 1~____________~I~SV~1~1~(M~8~O~80~)~~=======r__-J1

~REDSTRIPE
THIS SIDE

9 r~____________~I~SV~1~1~(M~OO~84~)______________~1
MA-0105-82

Figure 2-4

DYS50 Modules

2-7

Place the DYS50 about 30 cm (12 inches) back from the
edge of the work bench and remove the cover as follows.
a.

Remove the two retaining screws, just forward of and
at ei ther end of the front panel, that fasten the
DYS50 to its cover. One of these is shown in Figure
2-5.

Using both hands, place your thumbs aga inst the top
front edge of the DYS50, just above the cover
lock-release levers, as shown in the boxes in Figure
2-5. Place your index fingers against the release
levers, and your middle fingers under the 1 ip just
above the modules.

1. SLIDE RELEASE LEVERS
2. PRESS FORWARD WITH THUMBS
3. PULL BACK WITH INDEX FINGERS

MA-0227-82

Figure 2-5

Cover Removal

2-8

Push on the release levers, sliding both of them
toward the center of the front panel. While holding
the levers in that position, press forward with your
thumbs, and pull back wi th your middle fingers. The
DYS50 should release and sl ide a l i ttle way out of
the cover.

Complete cover removal by gripping the lip above the
modules with one hand and pulling toward you, while,
with the other hand, holding the top rear edge of the
cover.

2.4
DYS50 SWITCHES AND INDICATORS
Before proceeding any further, study Figure 2-6 and Table 2-2.
Become familiar with the locations and functions of the basic
DYS50 switches and indicators.

POWER O.K.
REMOTE
SWITCH

RESTART

AUXILIARY

POWER

o
OFF

OFF

+12f-~!::~:~~JUST

AC
INPUT

115/230V
SELECT

ADJUST

RE;'

+12V

+5V

DIAGNOSTIC
DISPLAY (RED)

+5V (GREEN)

MSB~

LSB.r'

oQooo

' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--', PROCESSOR

~ +5V (GREEN)

PARITY

ERROR(RED~

_,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~IMEMORY
LSB

MSB

DIAGNOSTIC
DISPLAY (RED)

...---------,

ISV11

ECdataway
CARRIER (RED)

MA-0159-82

Figure 2-6

Switches and Indicators
2-9

Table 2-2

DYSS9 Switches and Indicators

Switch or
Indicator

Location

Function

DYS50 primary
power switch

Front panel

When in the ON or 1 position, this
switch connects ac power to the
DYS50 power supply and cooling
fans.

115/230 Vac
select switch

Front panel

When the 115 legend on this switch
is visible, the DYS50 is
configured to operate on 115 Vac
primary power. When the 230 legend is
visible, the DYS50 is configured
for 230 Vac primary power. To.change
the switch setting place the tip of
a ballpoint pen in the depression on
the front of the switch and push up
or down. (Note that the fuse and
power cord must also be changed.)

AUX ON/OFF

Front panel

A cable connects this switch to
the cabinet power controller.
Since all cabinet equipment is
powered from the power controller,
this switch serves as the master
on/off switch for the entire
cabinet.

HALT

Front panel

In the down posi tion, this swi tch
halts program execution by the
DYS50 processor.
In the up position, program
execution is enabled but does not
start automatically. A downline
loading procedure from the
dataway host normally starts the
DYS50.

RESTART

Front panel

When this momentary-contact switch
is moved to the up position and
released, it causes the DYS50 to
do a power-up sequence. If the
HALT switch is up, the processor
can start executing a program. If
the HALT switch is down, the
processor enters aDT mode, and
responds to aDT commands from a
console terminal.

PWR OK

Front panel

This indicator lights when power
supply dc voltages are present.

2-10

Table 2-2

DYSSe Switches and Indicators (Cont)

Switch or
Indicator

Location

Function

RUN

Front panel

This indicator lights when the
processor is executing programs.

DECdataway
interface
diagnostic
display

ISVll
M8080
module

At power-up, when one of the twelve
ISVll-B ROM-resident diagnostics
is running, these indicators
display its number (in octal MSB
at the r igh t)
An error in anyone of the first
nine (hardcore) tests causes its
number to be displayed
continuously.
An error in any of the last three
(softcore) tests causes its
number to flash on and off for
ten seconds.

DECdataway
carrier
indicator

ISVll-B
M8084
module

When the dataway is connected,
this indicator is on when there
is dataway activity. It is off if
there is no activity or if the
dataway is not connected.

Processor
diagnostic
display

KDFll
M8l89
module

These indicators are normally on.
They are not used for processor
diagnostics in the DYSS0 because
the processor is configured for
power-up-mode zero.

Processor
PWR OK

KDFll
M8089
module

This indicator lights when +5 V
is present on the processor module.

Memory
parity

MSVll
M8067
module

This indicator lights when a
parity error has been detected.

Memory
PWR OK

MSVll
M8067
module

This indicator lights when +5 V is
present on the memory module.

2-11

2.5

PRELIMINARY CONFIGURATION

Configure DYS50 switches and jumpers as follows.
DYS50 Primary Power Switch

OFF or zero position

Restart

OFF

HALT

OFF

Auxiliary

OFF

115/230 Vac Select Switch -- Make sure the position of
switch matches the voltage being used at your site.
Fuse -- Two fuses are shipped with each DYS50 -- one

this

in the

fUSe holder, and one loose. Make sure the correct one is in
the fuseholder. The 10 A fuse is for 115 Vac operation. The 5
A fuse is for 230 Vac operation.
Backplane Jumpers -- The usual configuration for these jumpe:s
is shown in Figure 2-7. Make sure that at least WI 1S
installed. W2 and W3 are not needed but do no harm if present.
Backplane jumper functions are explained in Table 2-3.
Bezel Assembly Jumpers -- These jumpers are normally factory
configured as shown in Figure 2-8. Make sure WI, W2, and W3
are out, and W4 is in. Jumper functions are explained in Table
2-4. Alternative configurations of these jumpers are explained
in Chapter 5, paragraph 5.2.4.

Figure 2-7

Backplane Jumpers
2-12

Table 2-3

Backplane Factory Jumper Configuration

Jumper

Jumper
State

WI*

The H7861 power supply generated LTC
signal is used to assert BEVNT L
signal.

W2, W3

Out

These jumpers have no effect on
DYS50 operation.

Function

* WI must be removed from all expander boxes in a multiple-box
system since only the box containing the KDFII-BB (M8l89) module
must be the source of the LTC signal.

SIDE 2

W1 C>-O() 0
W2c>-0() 0

0
0

[J
- -

C>-~

W3 W4
0

SWITCH CONTACTS
(53, S2, S1)

LED CONTACTS
(RUN, PWR OK)

NOTES:
1. VIEW IS FROM THE REAR OF THE BEZEL
WHEN THE BOARD IS MOUNTED ON THE
BEZEL.
2. JUMPERS ARE MOUNTED ON SIDE 2.
MR·6545
MA·0204·82

Figure 2-8

Front Bezel Jumpers

2-13

Table 2-4

Bezel Assembly Factory Jumper Configuration

Jumper

Jumper
State

WI, W2

Out

These jumpers allow the AUX ON/OFF
swi tch to turn the -system power on
and off.

out

CPU is mounted in this backplane.

This
jumper
enables
the
RUN
indicator because the CPU is mounted
in this backplane.

Function

2.6
MOUNTING THE DYS50
If your system was factory
Paragraph 2.7.

configured

cabinet,

skip

2.6.1
Non-standard Enclosure Mounting
If your DYS50 is being installed in a special industrial
enclosure, the following installation procedure must be modified
to sui t that enclosure's configuration. Study the procedure and
become familiar with its requirements. Although DIGITAL does not
provide industrial enclosures for DYS50s, or specify their
configuration,
the
DYS50
is
designed
to
simplify
such
installations.
Specifically, the DYS50 (without its front door or hinges) fits in
a NEMA type-12 industr ial cabinet.
(NEMA stands for National
Electrical Manufacturing Association.) A NEMA type-12 cabinet is
30.48 cm (12 in) deep. The DYS50 cover has rear mounting holes for
mounting on the rear wall in a NEMA type enclosure (Figure 2-9).
Since all DYS50 modules, switches, indicators, and adjustments are
front accessible, it is well suited for this type of installation.
For more information about NEMA enclosures, refer to DIGITAL
brochure ED0l315-126.
For examples of this type of installation,
Subsystem User Guide EK-0PIOS-UG.
2.6.2
Standard Cabinet Mounting
Perform the following if you are
standard cabinet.

refer

installing

the

DYS50

I/O

Install the power cord in the cabinet as shown on
assembly drawing E-VA-DYS50-00.

Mount the hinges
provided.

Install the DYS50 cover in the cabinet (as shown in
Figure 2-11) with hardware provided. Do not tighten the
mounting screws at this time.

(as shown in Figure 2-10)

2-14

uni t

with hardware

USE REAR SLOTS FOR
NEMA ENCLOSURE MOUNTING.
DRILL AND TAP FOUR PLACES
FOR 10·32 X 1/2 IN. SCREWS
(PROVIDED).

MA·0235·82

Figure 2-9

NEMA Mounting

MA·0229·82

Figure 2-10

Hinge Mounting

2-15

- ()

-------

()
(J

()

STANDARD

()

()
()
()
()

()
()
()
()
()

TINNERMAN

ATIACH TINNERMAN NUTS
(PROVIDED) TO SIDE RAI LS.
FASTEN COVER IN PLACE
WITH 10·32X1/2 SCREWS
(PROVIDED). FOUR PLACES.
MA-0225-82

Figure 2-11

Standard Mounting

Slide the DYS50 into the cover until it is stopped by the
locking bolts. Momentarily press the lock-release levers
to allow the DYS50 to go in the rest of the way, and
slide it in until
it locks. Now, tighten the four
mounting screws.
WARNING
Note that the DYSS8 has no restraining
mechanism to prevent its being pulled
all the way out of its mounting cover,
once
its
locking
bolts
have
been
released. Therefore, when removing it
from its mounting cover, use extreme
caution to avoid dropping it.

Leave the module cage cover off at this time, so that the
LED indicators are visible during test.

2-16

TO CABINET
POWER
CONTROLLER
MA-0221-82

Figure 2-12

DECdataway and Power

Install the power cord and DECdataway interface cable (as
shown in Figure 2-12) wi th hardware provided. Do not
connect the DECdataway at this time.

Place the DYS5~ front panel power ON/OFF switch (located
at approximately the center of the front panel) in the 1
(ON) position.

2-17

2.7
CABINET AC POWER CHECK
All uni ts in the DYS50 cabinet get the i r ac power from the 874
power controller. Remove the cabinet rear panel and use the
following procedure to make sure that cabinet power is configured
properly.
1.

At the rear of the cabinet, set the power controller main
power circuit breaker switch to 0 (OFF).

Set the power controller REMOTE/OFF/LOCAL switch to OFF.

Plug the cabinet ac power cord
into
its proper
receptacle. The ac power indicator (to the upper right of
the main power circuit breaker) should go on.

Set the power controller
swi tch to 1 (ON).

Set the REMOTE/OFF/LOCAL switch to LOCAL. All cabinet
equipment should go on, and the DYS50 front panel PWR OK
indicator should go on. The DYS50 fans should operate.

Set the REMOTE/OFF/LOCAL switch
equipment should go off.

At the front of the cabinet, set the DYS50 AUX ON/OFF
swi tch to ON. All cabinet equi pment sho uld go on as
before.

Set the AUX ON/OFF switch to OFF.

MAIN

POWER

circuit

REMOTE.

All

breaker

cabinet

2.8
DC VOLTAGE MEASUREMENT
Turn on the DYS50 using the AUX ON/OFF switch on the front panel
(Figure 2-6).

The +5 Vdc and +12 Vdc regulated voltages must be measured with a
calibrated digital voltmeter. Test points for this purpose are
located at the lower right of the front panel also shown in Figure
2-6. If these measurements are not within the limits given, do not
try to adjust the power supply until you first refer to Chapter 5.
That chapter contains the correct adjustment procedure, along with
some precautions that must be observed.
2.8.1
M'easurement of +5 Vdc
Use the following procedure to measure +5 Vdc voltage.

Attach the voltmeter leads as follows.
The plus lead to the plus 5 V test point
The minus lead to the return test point

The correct reading is +5 V ± 0.15 V.

2-18

2.8.2
Measurement of +12 Vdc
Use the followi-ng procedure to measure +12 Vdc voltage.
1.

Move the plus voltmeter lead to the +12 V test point.

The correct reading is +12 V + 0.36 V.

OFF-DATAWAY OPERATION
2.9
For this procedure you need to use one of the DYS50-site terminals
as a consol e dev ice. Refer to that term ina l' s use r guide to
determine its interface requirements, and connect it to Jl of the
pro cess 0 r • ( Th i s i s the con sol e in t e r fa c e ; i t i s nor mall y
configured at the factory for 9600 baud).
Next, turn on the terminal and place the DYS50 HALT switch in the
up position. Then, turn on the DYS50 using the AUX ON/OFF switch
on the front panel.
When power is turned on, the ISVll-B internal diagnostics keep
repeating and produce the following display on the DYS50 console.
The explanatory comments in the right column are not part of the
display.
@

ODT prompt

00067 6

Interrupt test successful

ODT prompt

001 134

LSI-II Instruction test successful

ODT prompt

The display repeats continuously about every 10 seconds.
Observe the ISVII-B indicator LEDs and confirm the following.
1.

The ISVll (M8080 module) diagnostic indicators display
the number of the diagnostic (in octal, LSB at the left)
being executed. These indicators cycle as the diagnostics
repeat, but the on/off pattern appears random because all
tests do not have the same dur at ion. However, test 13
(octal) is about ten seconds long and is noticeable.

The ISVll (M8084 module) carrier indicator is off.

2-19

2.1~
DYS5~ TO DECdataway INTERFACE
The communications I ink between the DYS50 and its host PDP-II
computer is the DECdataway. This should already be installed. If
not, its installation is covered in the DECdataway User Guide
(EK-ISBll-UG).

Part of that installation is selecting the DECdataway port address
for each connected device (by conf igur ing jumper s at each por t
connector). The DYS50 uses two port addresses; the lowest numbered
address is marked on the port connector at the DYS50 site
location. Check with the site manager to see if the address marked
on the connector is the correct one for this installation.
To interface the DECdataway to the DYS50, simply mate the
DECdataway connector with its receptacle inside the DYS50 cabinet
(Figure 2-12).
2.11
ON-DATAWAY OPERATION
When the dataway is connected, observe the terminal display again.
•

The terminal display stops repeating.

Observe the ISVll indicators.
•

The ISVll (M8080 module) diagnostic indicators display a
zero cycling from left to right through a field of ones.

•

The ISVll-B (M8084 module)
there is dataway activity.

carrier indicator lights when

Any var iation from the above resul ts indicates a faul t in the
basic DYS50 system. As an aid to isolating the faul t, refer to
Chapter 3 (Maintenance), which presents a detailed discussion of
the ISVll-B internal diagnostics and the significance of
variations from the above results.
2.12
DYS50 PERIPHERAL INTERFACES
The following paragraphs discuss interfaces for some common DYS50
peripherals.
2.12.1
Standard Interfaces
The DYS50 processor is an LSI-II device. Its peripherals interface
to the LSI-II bus via control modules. These modules plug into the
bus and connect to the peripheral devices via one or more cables.
The various control modules and their cabling requirements are
discussed at length in the Microcomputer Interfaces Handbook. A
user guide with additional interface information comes with each
peripheral; sometimes additional cables are included.

2-20

2.12.2
Filtered Interfaces
In any electrical system, cables that connect pieces of electrical
equipment carry signals that may radiate enough electrical energy
to cause objectionable amounts of electromagnetic interference
(EMI) in the local env ironment. Conver sely, any EMI in the local
environment can be conducted into a cabinet on its interfacing
cables. If that cabinet happens to contain sensitive circuits,
this interference may cause them to malfunction. To minimize the
possibility of either problem occurring with the DYS50, all signal
cables leaving or entering a DYS50 cabinet, do so through
specially constructed cable assemblies that have filtered
connectors. These connectors are mounted on an H349 distribution
panel. An example of this type of interface is shown in Figure
2-13.
2.12.3
H349 Distribution Panel
This panel is provided with all DYS50 cabinet assemblies. The
panel provides simple and convenient means of interfacing
peripheral equipment with the DYS50.
This 28.32 cm (11.15 in) by 44.10 cm (18 in) hinged panel is held
in its vertical position by two quarter~turn captive screws.
The H349 panel has ten mount ing locat ion s (J 1 thro ugh J15) fo r
moun t i ng up to f i f tee nco nne c tor cab I e ass ern b 1 i e s , a s s h 0 wn i n
Figure 2-14. Eleven cable assemblies contain 1 X 4 slots (Jl
t h r 0 ug h J 11 ) and f 0 u r con t a i n 4 X 4 s lot s (J 1 2 t h r 0 ug h J 1 5). An
adapter is available to transform four of the 1 X 4 slots (J8
through Jll) into a 4 X 4 slot. When mounted, each cable assembly
is connected to the DYS50 subsystem by ribbon cables. As Figure
2-14 shows, the J6 and J7 positions are normally used for the two
SLU interfaces on the DYS50's processor: J6 for the console
interface and J7 for a standard terminal.

H349
PANEL

INSIDE DYS50
CABINET

I
M

F
M

I OI---_Bc_22_A_-25_--IOD

EXTERNAL
PERIPHERAL

Q
VT100
EIA TERM_

FILTERED EIA
RS232 MALE
CONNECTOR

MA-7096B

Figure 2-13

Filter Placement

2-21

CONSOLE AND
TERMINAL CABLES
INCLUDED

VIEWED FROM
INSIDE CABINET

IJ3

t=======l~~:

t-------f4

~J13
DZV11

=======

J~'2

DZVl1

J15

DZVll

VIEWED FROM
REAR OF CABINET
MR-737B
MA-021B-B2

Figure 2-14

H349 Distribution Panel

2-22

2.12.4
DYS58 to 1/8 Subsystem Interface
For process I/O applications, the DYS50 must contain an M7959 I/O
control module (IDCM). This module provides an interface between
the DYS50 LSI-II bus and the I/O subsystem D-bus.
The interface is completed via a BC08R cable that plugs into Jl of
the M7959 module at one end, and the D-bus-in connector of the I/O
subsystem H334 chassis at the other end (Figure 2-15). The figure
shows the correct way to install this cable by observing proper
orientation of the stripe on the side of the cable. Additional
information about the I/O subsystem is contained in the I/O
Subsystem User Guide (EK-eJPIOS-UG).
2.13
EXPANDING AN EXISTING SYSTEM
If an existing DYS50 system needs more peripherals to meet
increased demands, interface modules for the new peripherals must
be added to the LSI-11/23B bus. The following paragraphs tell how
to add new modules to existing spare bus slots, and how to expand
the bus if there are no spare slots.

D-BUS IN

I/O SUBSYSTEM
H334 CHASSIS

DYS50-_ _ -1

IPV·'2
(M7959
10CM)

BC08R
D-8US CABLE
NOTE STRIPE
ORIENTATION
MA·0222·B2

Figure 2-15

I/O Subsystem Interface

2-23

2.13.1
Adding New Modules
If there is a spare slot on the LSI-ll/23B bus, it is easy to add
a new peripheral device to the DYS50. While observing LSI-ll/23
bus rules, (as explained in Appendix C) configure the new
peripheral's interface module address, vector, and other options
(if any); plug the module into the spare bus slot, and connect it
to the peripheral with the appropriate cable. First consult each
device's user manual to determine if there are any restrictions
and what cables can be used. In addition, the DYS50 imposes the
following restrictions for adding new modules.
1.

The ISVII-B M8080 module must be
following the new interface module.

moved

the

The ISVII-B M8084 module must remain in slot 9.

3•

Th e DZ V11 v ec tor spa c e i s fro m 3 00 to 7 77 • Ve c tor s
and 304 cannot be used because they confl ict wi th
ISVII-B.

slot

3 00
the

2.13.2
Adding an Expansion Chassis
1 f t he _ 0 rig ina 1 DYS 5 0 c has sis doe s no t h av e en 0 ug h roo m for
expansion, you can extend the bus by adding a BAII-YC expander
box. The rules for adding new modules to the first box must also
be applied to the second box. In addition, the expansion bus must
connect to 'the first bus via two BC02D cables. These cables
interface to the first chassis via an M9404-00 module in the last
usable slot, and to the second chassis via an M9405-YA module in
slot 1 (refer to Append ix C). (The opt ion consi sts of the two
cables and two modules.) Note that when adding an expander box,
the ISV11-B moves to the expander box.
2.14
PERFORMANCE VERIFICATION
You can verify the performance of the DYS50 and its peripherals
once communication is established between the DYS50 and host
computer v ia the DECdataway. When thi s i s done, the host can
down-line load diagnostic software to the DYS50. Then, using only
a local console terminal, you can ver ify that all DY subsystem
units are operational by running these diagnostic programs. Each
program exercises some integral unit of the system and provides
feedback via displays or printouts about the unit's performance.

2-24

CHAPTER 3
MAINTENANCE

3.1
OVERVIEW
Corrective maintenance of the basic DYS50 is relatively simple. It
is a modular device; if it fails, just identify and replace the
failed module.
Identification of the failed module is sometimes difficult, but
there are tools to help you do that. All that is needed is some
system knowledge and a logical approach to each problem.
The logical approach is not possible without the system knowledge.
You must be aware of, and clearly understand, the DYS50's
relationship to the system of which it is a part (the DY system) •
For example, if you want to troubleshoot a DYS50 from the host,
you must first establish that the host itself is operational, and
that the DECdataway is working properly. You must also determine
that the DYS50's interface to the DECdataway (the ISVll)
is
working. Read the related mater ial and references in Chapter 1,
and become totally familiar with DY system concepts.
This chapter describes DYS50 maintenance only. You can find
hardware maintenance information for optional units of a DYS50
subsystem in their respective user guides. These user guides are
included in the documentation package shipped with the DYS50. In
addition to maintenance information, these user guides describe
optional configurations of these units, which mayor may not be
incorporated in a given DYS50.
For example, many peripheral
inter face modules have jumper sand/or swi tches used to select
addresses, vectors, etc. All modules in a DYS50 are configured
before shipment. However, factory configurations of user selected
options may not match site requirements in all cases, so if a
module appears to have failed at installation time, check its
configuration. Even when a previously working module fails and is
replaced by a new one, verify that it is properly configured by
consulting the appropriate user guide.
As for the standard modules comprising the basic DYS50, if there
is ever any doubt about their original factory configurations,
they are listed in Appendix A for reference.

3-1

The United States Area Support Group is chartered to provide all
levels of support, including Field Service training for U.S. Area
Support personnel. Support and training in European areas is
provided by European Regional Support.
3.2
TROUBLESHOOTING TOOLS
It is impossible to describe all the ways that a DYS50 failure can
affect a DY system. Some failures are easily isolated and
cor rected; 0 thers requi re· all the troubl eshooting resources and
expertise at your command. The exact nature of a failure and its
a t ten dan t s ym p t om s . will , t 0 a 1 a r gee x ten t , d i c tat e yo u r
troubleshooting approach. Nevertheless, a logical beginning and a
thorough knowledge of troubleshooting tools can greatly reduce the
time spent in the effort.
The following is a brief description of the DYS50's hardware and
software troubleshooting tools. They have a top-down structure
that, if used intelligently, will help you quickly zero-in on even
the most obscure failure causes.
WARNING
If the DYS50 is used as an industr ial
process controller, do not initiate any
maintenance procedures or diagnostic
programs without first checking with
local si te personnel for any requi red
safety precautions and/or operating
restrictions.
Certain
of
these
processes, if interfered with in any
way, can pose extreme hazards to si te
personnel,
and
may
even
have
far-reaching and dire consequences
beyond their immediate vicinity.
3.2.1
Maintenance Software (Diagnostics)
The following is a brief discussion of what maintenance software
will do for you. How to run and interpret system-level and
standalone diagnostics are the subjects of other documents. Which
documents, depends on which host computer is used in your system.
These are listed in Chapter 1.
3.2.1.1 System Level Diagnostics
These diagnostics are run at
the host. In the event of a DYS50 caused system failure, isolation
of that failure to a specific DYS50, if not immediately obvious,
is usually achieved by logical system-level fault analysis -- that
i5, by running the system-level diagnostics and interpreting the
r e 5 u 1 t 5 • One 0 f these d i a g nos tic s test s the IS B11 con t roll e r ;
another, (called the DECdataway exerciser) establ ishes the
soundness of communications between the host and the DYS50s.

3-2

3.2.1.2 Standalone Diagnostics -- Further isolation of a failure
to a specific field replaceable unit (FRU) in the DYS50 is done by
running standalone diagnostics in the DYS50. These are down-line
loaded to the DYS50's LSI-ll/23B computer by CZKMP, a diagnostic
monitor in the host. (CZKMP also down-line loads part of itself to
the ISVl1's RAM memory. From there it monitors the down-line
loaded, standalone diagnostics and communicates with the
oper ator .) Once down-l ine loaded, standalone diagnostics are run
by the DYS50's LSI-ll/23B computer. They can be monitored remotely
at the host in two different modes (host and communication), or
locally (in local mode) at the DYS50 if it has a console terminal.
3.2.2
Hardware Troubleshooting
Before running any diagnostics, perform a quick visual inspection
of the DYS50 for any obvious signs of trouble. The following are
things to look for.
•

Are both ends of the power cord plugged in?

•

Is the fuse okay?

•

Are both fans operating?

•

Is the power ON/OFF switch on?

•

Is the 115/230
position?

•

Is the power control cable connected?

•

Ar e the HALT, RESTART,
correct positions?

•

Do the POWER OK and RUN indicators light?

•

Are all cables in
firmly seated? .

volt

select

good

and

switch

AUXI LIARY

condition

and

the

swi tches

their

correct

the

connectors

3.2.3
Built-In Diagnostics
Aside from system level and standalone diagnostics, there are
on-board diagnostics contained in the ISVll's ROM memory. These
are a ser ies of twelve tests (numbered one through four teen,
octal) that run automatically every time the DYS50 is turned on.
If the DECdataway is connected, these tests run only once,
otherwise they repeat continuously (except in the case of some
error conditions). The tests are also ·run once by one of the
system-level diagnostics: the DECdataway exerciser. Associated
with the built-in diagnostics is a display, consisting of four
LEOs, that indicates the number of the test being run. The tests
are of two types: hardcore and softcore.

3-3

3•2•3•I
Ha r d cor e Te s t s - - Th e fir s t n in e t est s (I t o l l 0 c tal )
are called hardcore because they test basic characteristics of the
ISVll-B. An error in any of these nine tests causes the eight-bit
microprocessor to loop within the test, thus continuously
displaying the number of the first failed test. A hardcore error
also means that the DYS50's communication interface is not
functioning properly. It is, therefore, prevented from trying to
communicate, so that it does not impair the communications of
other devices on the DECdataway. Table 4-1 (Chapter 4) describes
the hardcore tests.
3.2.3.2 Softcore Tests -- The last three tests (12, 13, and 14,
octal) of the ISV11-B ROM-resident diagnostic tests are called
softcore because they do not stop the ISV1l-B from communicating
with the host. These tests check the operation of the LSI-1l/23B
CPU (processor and memory). Test 13 takes about 11 seconds, but 12
and 14 are so fast their numbers may not be noticed in the LEDs. A
softcore error causes the failed test number to be displayed
flashing in the LEDs for 10 seconds. The error number (in decimal)
is also displayed at the operator's terminal. Table 4-2 (Chapter
4) describes the softcore tests.
3.2.4
ISVl1 Indicators
The LED display for the built-in diagnostics, located on the edge
of the ISVII-M8080 board, provides much helpful information for
DYS50 fault analysis. Figure 3-1 summarizes the interpretation of
this display.

A LED on the ISVl1-M8084 board flashes when a carrier is present
on the DECdataway. It flashes at a slower rate as carrier activity
increases.
3.2.5
DYS50 Troubleshooting Flowchart
It cannot be overemphasized that you must always be aware of the
total system when troubleshooting dev ices on the DECdataway. Do
not troubleshoot the DYS50 until it has been verified that the
problem is not in the host or DECdataway. The strategy for doing
that is the subject of system level documents listed in Chapter 1.
When through direct observation or system trouble analysis you
have isolated a particular DYS50 as the source of a problem, you
can then pursue a troubleshooting strategy to further isolate it
to the lowest field replaceable uni t
(FRU) in the DYS5 0. The
strategy is outlined in flowchart form in Figure 3-2. The figure
is not meant to be an exhaustive treatment of all possible
failures. It is merely a helpful guide. Troubleshooting strategies
change as more is learned about the problem, but if you begin with
the approach indicated in Figure 3-2, it should prevent you from
wasting valuable time misreading the symptoms.

3-4

TEST NUMBER
DECIMAL OCTAL

**11

LSB

DISPLAY*
MSB

_000
0_00

_eoo
00_0
_oeo
oeeo
_eeo

000.
_00_
0.0 • }

_e
o
0 0e e
_
.O ••}

oe_e
_e_e

- - - NINE HARDCORE ERROR CONDITIONS:
OCTAL NUMBER IS DISPLAYED PERMANENTLY IF TEST FAILS (lSV11
CAN'T COMMUNICATE WITH HOST).
REPLACE ISV11. t

THREE SOFTCORE ERROR CONDITIONS.
OCTAL NUMBER FLASHES FOR 10SECONDS. ITS DECIMAL EQUIVALENT
IS UPLINE LOADED TO HOST IF OAT·
AWAY IS CONNECTED. THE TEST
CYCLE THEN CONTINUES. COMMUNICATION WITH HOST IS POSSIBLE.
IF ERROR IS 12 OR 13, REPLACE
LSI-11 MEMORY-IF 14, THE PROCESSOR. t

--NOTUSED.
- - - FATAL ERROR-MEANS ISV11
IS TOTALLY INOPERATIVE.
REPLACE ISV11. t

*BLACK = ON
** TEST 13 (OCTAL) LASTS ABOUT 11 SECONDS. ITS NUMBER IS DISPLAYED
ALL DURING THE TEST, BUT UNLESS IT IS FLASHING, THE TEST HAS
NOT FAILED.

t MODULE REPLACEMENT SUGGESTIONS ARE FOR MOST PROBABLE
FAILURES. OTHER FAILURES MAY SHOW THE SAME SYMPTOMS.

NOTE: THERE ARE TWO NO-ERROR DISPLAY CONDITIONS

IF THERE ARE NO FAILURES, AND THE DATAWAY IS CONNECTED, THE LEOS DISPLAY A ZERO CYCLING FROM LEFT
TO RIGHT THROUGH A FIELD OF ONES.

IF THERE ARE NO FAILURES, AND THE DATAWAY IS NOT
CONNECTED, THE ON-BOARD DIAGNOSTICS KEEP REPEATING. THE LEOS DISPLAY EACH TEST NUMBER AS IT RUNS,
BUT 13 (OCTAL) IS THE ONLY ONE OF SUFFICIENT DURATION TO BE READ EASILY.
MA-Ol04-B2

Figure 3-1

ISV11 Display

3-5

TROUBLESHOOTING AT HOST
5

INVESTIGATE OTHER
PROBLEM

GOTO DIS

GO TO DIS

ANALYZE ERRORS
SELECT LOCAL
MODE GO TO DIS

4
MA-8315

Figure 3-2

DYS50 Troubleshooting (Sheet 1 of 2)

3-6

TROUBLESHOOTING AT DIS
4

RUN PERIPHERAL
DIAGNOSTICS IN
LOCAL MODE. IF
THERE IS NO LOCAL
TERMINAL PROVIDE
A PORTABLE

REPLACE
MEMORY MODULE

YES

REPLACING MODULES
DOES NOT FIX DIS
CAN'T GET
DIS ON LINE

DIAGNOSTIC REPORTS NO ERRORS.
BUT DIS STILL DOES NOT WORK
NO
CALL
SUPPORT
MA·8316

Figure 3-2

DYS50 Troubleshooting (Sheet 2 of 2)

3.3
ISVII-B TROUBLESHOOTING
Maintenance philosophy for the ISVII-B is option replacement (both
modules). However, careful analysis of faults using diagnostics
and available test points should permit service personnel to
isolate a problem to one of the two modules. Chapter 4 contains a
troubleshooting procedure for doing this. Note that the ISVll-B
operates only as a unit, that is, with the M8080 and M8084 modules
connected together. However, they are not a matched set; a single
module can be replaced if necessary.
3.4
ROUTINE MAINTENANCE
Routine maintenance procedures (when and,if required) for integral
units of a DYS50 subsystem are found in their respective user
guides (Paragraph 1.6). Most maintenance procedures can be
performed by removing the rear panel and/or sliding out one of the
drawers.

3-7

3.5
UNIT REMOVAL AND REPLACEMENT
Once identified, a faulty unit in a DYS50 is easily replaced using
one of the following procedures. Field replaceable units (FRUs)
include the following:
•
•
•
•
•
•

Entire DYS50 box (the BAlI-Y)
Any plug-in module
Fans
Power supply
Control panel module (bezel module)
Backplane
WARNING
Note that the DYS5fJ has no restraining
mechanism to prevent its being pulled
all the way out of its mounting cover,
once
its
locking
bolts have
been
released. Therefore, when removing it
from its mounting cover, use extreme
caution to avoid dropping it.

3.5.1
Replacement of the BA11-Y Box
Use the following procedure to remove the DYS50.
1.

Place the AUX ON/OFF switch in the OFF position.

Place the ac power 1/0
position.

Unplug the power-control cable (if used), and the ac
power cord from their sockets at the left end of the
front panel. Place these out of the way by tucking them
into the rectangular opening just to the left of the
front panel. Put the power-control cable in first. It
will be held in place by the power-cord plug, which will
be held neatly in place if you tuck it into the front
par t of the opening. There is a channel the right si ze
for it (Figure 3-3).

Loosen the two knurled-captive screws near the bottom of
the DYS50. Remove the module cover by pulling out at the
bottom and then down.

Remove any cables attached to the modules. Do this
carefully, taking special note of the position of each
connector, and of its or ientation (some connectors are
not mechanically keyed and can be pI ugged in backwards
unless you pay attention to this). Also note the routing
of these cables so that you can put them back neatly when
reinstalling the DYS50.

(ON/OFF) switch in the zero

3-8

(OFF)

RELEASE
LEVER

MA-0220-82

Figure 3-3

DYS50 Chassis Removal

Remove the two retaining screws that fasten the DYS50 in
place. There is one at each end of, and just forward of
the front panel (Figure 3-3).

Release the DYS50 from its mounting cover and pull it out
only about two inches. This is done by pressing the
release levers wi th your index fingers, while pull ing
with your middle fingers hooked under the lip just over
the module cage. Keep in mind that the DYS50 is not
restrained in its mounting cover in any way, slide it the
rest of the way out of the cover very carefully,
supporting it with your hands on both sides.

The replacement procedure for the DYS50 is nearly the reverse of
the removal procedure -- except for the release levers. These will
prevent you from sl iding the DYS50 all the way back into its
mounting cover. Press the release levers and push the DYS50 past
that point. Then push the DYS50 in until you hear them lock.

3-9

3.5.2

Module Insertion and Removal
CAUTION
Modules and/or the backplane assembly
might be damaged if modules are inserted
or removed with power on, or if inserted
upside down.

It is absolutely imperative that you turn the power off before
trying to insert or remove any DYS50 module. Use the ac 1/0
(ON/OFF) switch to turn off a DYS50 or expander box only. If your
system has a power controller, and if its remote ON/OFF feature
has been implemented on your DYS50, you can use the AUX ON/OFF
switch to turn off the entire system.
Your DYS50 may have both quad modules and dual modules. Dual
modules go only in the left side of the module cage (Figure 3-4).
All modules are installed component side up.
All modules must be inserted or removed with extreme caution, to
prevent damage to any of their components or to the components of
adjacent modules. Do not grab a module by its handle(s) and yank
it out of the card cage. Module removal is really a two step
process: First pull with only enou9h force to release it from its
connector, and then carefully guide it out of its slot. Th is
prevents damage to components, as well as the unintentional
changing of any switch settings on the module itself or the one
below it.

CARD GUIDES
DUAL MODULE

MA·0223-82

Figure 3-4

Module Replacement

3-10

Most quad modules are equipped wi th extractor-type handles that
help with module insertion and removal. Pulling back on both of
these handles at the same time releases the module from its
connector, making removal easy. To reinstall one of these modules,
carefully guide it into its slot, making sure that it is in its
proper card guide on both sides. With the extractor handles
extended outward, you will be able to guide the card far enough
into its connector for the forked ends of the handles to engage
the slots on the sides of the card cage entrance (Figure 3-4).
Insertion is completed by pressing on both handles until they are
parallel to the card end.
3.5.3
Fan Removal and Replacement
The DYS50 has two cooling fans: one for the modules, and another
for the power supply. To replace either fan, you must first turn
off the power and remove the DYS50 from its mounting cover in the
manner previously discussed.
Use the following procedure to remove the power supply fan.
1.

Unplug the ac cord on the right side of the fan.

Remove the four screws that fasten the power supply
bracket, fan, and fan bracket to the DYS50 chassis, and
remove that entire assembly (Figure 3-5).

Use the following procedure to replace the power supply fan.
1.

Check the arrow on the side of the new fan for proper
air-flow direction, and also orient the fan so the ac
plug is in the correct position.

Attach the
assembly.

Plug in the ac cord.

brackets

the

new

fan

The logic assembly fan appears difficult to
quite easy with the following procedure.

and

reinstall

the

remove but is really

Use the following procedure to remove the logic assembly fan.
1.

Unplug the ac cord on the right side of the fan.

Remove the four mounting screws.

Push the fan back as far as it will go and tip the top
forward. By sliding the fan to one side, you will be able
to slide out one top corner and then the other to remove
the fan (Figure 3-5).

3-11

REMOVE THIS ENTIRE ASSEMBLY
TO REPLACE POWER SUPPLY FAN

PUSH FAN BOTTOM BACK
AND TIP TOP FORWARD.
SLIDE SIDEWAYS TO
REMOVE ONE TOP COR·
NER, THEN THE OTHER.
MA·0231·82

Figure 3-5

Fan Replacement

Use the following procedure to replace the logic assembly fan.
1.

Check the arrow on the side of the new fan for proper
air-flow direction, and also orient the fan so the ac
plug is in the right position.

Install the new fan in the chassis by putting the bottom
in first and then sliding the top corners in one at a
time.

Finally, fasten the four mounting screws, and plug in the
ac cord.

3-12

Power Supply Removal and Replacement
3.5.4
Use the following procedure to remove the power supply.
1•

Turn off power.

Remove cover.

Remove two screws on top of supply and tip back.

Unplug Jl

Loosen the screws of the dc harness terminal
disconnect it (Figure 3-6).

Unplug the control board (the small pc board on the left
Figure 3-6) to access J5 and J6. Unplug J5 and J6.

Tip supply down to normal position.

Unlock hinges (Figure 3-6).

LLft suppl y out.

(ac power harness).
str ip and

Use the following procedure to replace the power supply.
1.

Make sure the power supply hinges are in the
position; set it in place, and lock the hinges.

unlocked

Replace: J5 and J6, the power supply control module, the
dc harness terminal strip, the ac power harness, and the
two screws.

Reinstall the DYS50 in its mounting cover.

3.5.5
Control Module Replacement (Bezel)
This is a 7.6 X 11.4 cm (3 X 4.5 in) printed circuit module. It is
mounted on standoffs, and is located just behind the front panel
(Figure 3-7).
Use the following procedure to remove the control module.
1.

Turn off power.

Remove cover.

Unplug the two cables that plug into the control module.

Remove the four mounting screws that attach the module to
the standoffs, and remove the module.

3-13

MA-0400-82

Figure 3-6

Power Supply Replacement

3-14

FOUR MOUNTING SCREWS

Jl IS POWER SUPPLY INTERFACE
J2 IS POWER CONTROLLER INTERFACE
J3 IS NOT USED

MA-0239-82

Figure 3-7

Front Panel Bezel Module Replacement

Use the following procedure to replace the control module.
1.

Check jumpers WI through W4. Normally, jumpers WI, W2,
and W3 should be out; W4 should be in. However, there are
other configuration options as explained in Chapter 5, so
configure the new module like the old one unless directed
to do otherwise by the site manager.

Install the mod ule on the standoffs as shown
3-7, and fasten with the four mounting screws.

Reconnect the cables to JI and J2

Reinstall the DYS50 in its mounting cover.

3-15

(J3 is not used).

Figur e

3.5.6
Backplane Replacement
To replace the backplane, first turn off power and remove the
DYS50 from its mounting cover in the manner previously described.
Having done that, remove the backplane as follows.
1.

Remove all modules plugged into the backplane.

Di sconnect the dc harness at the backplane
the screws to disconnect the harness.

Disconnect
end.

signal

cable

the

backplane

Remove the bottom two mounting
cooling fan.

screws

the

card-cage

At the rear of the power supply (Figure 3-8), remove the
three screws that fasten the rear of the backplane
enclosure to the DYS50.

On the bottom of the DYS50, remove the six screws that
fasten the bottom cover to the module cage. This frees
the L-shaped, bottom-and-back cover from the DYS50. The
backplane, which is mounted to the back part of this
cover, is now accessible.

Remove the four screws that fasten
place, and remove the backplane.

the

backplane

the

end.

Loosen

backplane

Use the following procedure to replace the backplane.
1.

Verify that jumpers WI, W2, and W3, on the front of the
new backplane are configured correctly.

Fasten the new backplane to the
screws removed from the old one.

Reassemble the DYS50, following the previous procedure in
reverse.

cover

wi th

the

four

3.6
DC VOLTAGE MEASUREMENT AND ADJUSTMENT
If the +5 Vdc and +12 Vdc regulated voltages appear to be out of
limits, do not try to adjust them without first remeasuring as
directed here. Furthermore, if adjustment is indeed necessary, you
must use the exact procedure and precautions given here.

3-16

3 REAR SCREWS ~

BACKPLANE
SIGNAL CABLE

DC HARNESS
BOTTOM
COVER

4 BACKPLANE --.....
SCREWS
'

BACKPLANE

6 BOTTOM SCREWS

MA-0232-B2

Figure 3-8

Backplane Replacement

3.6.1
Measurement
Use a calibrated digital voltmeter to measure the voltages under
typical conditions.
NOTE
Do not measure the de voltages without a
load on the power supply (at least 2
amps). If you do, you will get incorrect'
readings.
Use the test points provided at the lower right of the front panel
to measure the voltages (Figure 3-9). The +5 Vdc output should be
between 4.85 V and 5.15 V. The +12 Vdc output should be between
11.64 V and 12.36 V. If either voltage is out of tolerance, use
the following adjustment procedure.

3-17

R22

R1
+12 V
ADJUST

ADJUSTMENT
ACCESS

MA-0226-82

Figure 3-9

DC voltage Adjust

3.6.2
Adjustment
Voltage adjustment potentiometers are located on the control board
inside the power supply (Figure 3-9). Access to these adjustments
is possible through holes in the front panel.
NOTE
If both voltages need adjustment, adjust
the +5 Vdc supply first. Adjusting the
+12 Vdc supply first -- beyond its range
-- may cause crowbarring.
The cor rect output is reached when a potentiometer is near its
midrange position. If it must be turned to near an extreme
position to reach tolerance limits, there may be a problem in the
regulator. If the output cannot be brought wi thin 1 imi ts, replace
the power supply control board.

3-18

CHAPTER 4
ISVII-B DESCRIPTION

4.1
INTRODUCTION
The ISVII-B is a dev ice that inter faces LSI-II compute r s to the
DECdataway. That is, an LSI-II computer equipped with an ISVII-B
can be attached to a DECdataway network. An LSI-II computer so
equipped is called a Distributed Intelligent Subsystem (DIS). The
ISVII-B wor ks wi th all cur rent vers ions of the LSI-II f am i ly of
computers.
The ISVII-B consists of two quad-height modules: the M8080 and the
M8084 (Figur e 4-1). These are connected together wi th a short
ribbon cable. One of the modules, the M8080, interfaces with the
LSI-II bus via its etched edge connector when it is plugged into
an LSI-II backplane. The other module, the M8084, does not pI ug
into the backplane at all; it has no edge connector. It does,
however, occupy a slot in the module cage. It interfaces with the
DE Cd a t a wa y cab 1 e con n e c to r v i a a 0 n e met e r ( 3 • 3 f t) s e ria 1-bus
cable. This cable and the ribbon cable that interconnects the two
modules are part of the ISVII-B option.

INTERCONNECTING
RIBBON CABLE

M8084

FINGER LESS

DECdataway
RECEPTACLE
SIDE VIEW

REAR VIEW
NOTE: THE M8080 MODULE IS ALWAYS ASSIGNED AS THE LAST
OPTION ON THE LSI-" BUS. THE M8084 IS ALWAYS ASSIGNED
TO THE LAST AVAILABLE SLOT IN THE MODULE ASSEMBLY AND
DOES NOT PLUG INTO THE BUS. THERE CAN BE EMPTY SLOTS
BETWEEN THE TWO MODULES.

Figure 4-1

ISVII-B Option -- DECdataway
to LSI-II Bus Interface

4-1

MA-7082

4.2
ISVII-8 APPLICATION
Recall that an ISVII-B plugged into an LSI-II computer creates a
DIS. A DIS fulfills a modular function in a class of computer
communication networks called DY (DECdataway) systems. These
systems are local area networks that implement distributed
processing in industrial complexes. To see how an ISVII-B works in
one of these systems, we must first see how a typical DY system
works.
4.3
TYPICAL DY SYSTEM
In its simplest form, a DY network has a centrally-located (host)
computer, and multiple, remotely-located, smaller computers. The
remotes are deployed throughout the site wherever dedicated
processing is needed. Completing the network is a communication
channel called the DECdataway, which connects the host and- all
remotes together (Figure 4-2).
As Figure 4-2 shows, LSI-lIs (the DISs)
are the distributed
e 1 em en t s 0 f
the net wo r k , and I S VII - B s
are the i r net wo r k
interfaces. Because they are linked by the DECdataway, the LSI-lIs
are DECdataway subsystems, and because they are programmable they
are called intelligent subsystems. Thus the name, DECdataway
Intelligent Subsystem (DIS).

HOST

r----'
I ISBll-A I
I

DECdataway

h. I__, ~_l~ I -, r-I,
-.---~~
-!- -_

_DECdatawa y

TERMINATOR __

~,....--'"""--,....

I
I ISV11-8 I
L -

DIS

...J

I
I ISV11-B I
l

DIS

TASKl

TASK 2

I
I OTHER

II I ISV11-B I I OTHER
I
I DECdataway I
.J
I OPTION I

I DECdataway I
I OPTION
I L. -

DIS

'--.-.1

TASK 3

TASK n-l

TASK n
MA-021SA-82

Figure 4-2

A Typical DY System

4-2

4.3.1
DY System Host
The host computer of a DY system local-area network can be either
a PDP-II, or VAX/VMS computer. The same DECdataway hardware is
used in either case, but the software is different. Moreover, the
host operating system can regard all units of a local area as
belonging to the same network even though more than one DECdataway
may be used to connect all of them to the host. Different hosts
can support different numbers of DECdataways and each DECdataway
needs a separate ISB11 DECdataway Controller.
By the way, the host and its ISB11 DECdataway controller are not
restricted to any particular network node; they can be at one end
of the DECdataway or at any node along the entire cable. The
host's node, however, does need an ISBl1-unique DECdataway
connector.
4.3.2
DY System Communication Link
A DECdataway cons i sts of more than only a cable. The DECdataway
controller, its connectors, and its two cable-terminating
resistors, as well as the cable, are all part of the DECdataway
(Figure 4-2). Each of these is described briefly.
4.3.2.1 DECdataway Cable
This cable is a
pair. It can be up to 4572 m (15,000 ft) long.

shielded,

twisted

4.3.2.2 DECdataway Controller (ISB11) -- One of the DECdataway
nodes plugs into the ISB11 DECdataway controller, which in turn,
pI ug s i n t o t h e h 0 s t com put e r • Th i s con t roll e r man age s a I l
communications between the host and any remote devices attached to
its DECdataway cable.
The controller
supports up to 63
remote-device addresses.
Communication over the DECdataway is synchronous serial at 55,556
bits per second, and is carried out in a block or message-oriented
fashion. Most communications are two-part transactions:
(1) a
command message from the host to a remote and, (2) a response
message from the remote back to the host.
Excepted are
com mu n i cat ion s fro m the h 0 s t to add res s z e r 0 • Th i sad d res s
functions as a broadcast channel for sending command messages from
the host to all remotes at the same time. Remotes are not allowed
to respond to these messages.
All messages on the DECdataway are formatted in DIGITAL Serial Bus
Control (DSBC) protocol, which makes sure that message content is
not modified during transmission.
4.3.2.3 DECdataway Connectors
Each DECdataway has one
controller connector, and from one to 63 remote-device connectors.
The controller connector has only four pins; remote-device
connectors have sixteen.
During installation, the extra pins in the remote connectors are
configured with jumpers that define a device's DECdataway address.
Connectors of devices that use more than one DECdataway address
are configured with that device's lowest address.
4-3

4.3.2.4 DECdataway Terminators -- The two DECdataway cable ends
are always terminated in the cables characteristic impedance (200
ohms) •
4.3.3
DY System Remote Devices
Although we are not concerned with them here, it should be
mentioned that other devices besides DISs attach to the
DECdataway. This was indicated in Figure 4-2.
If there were nothing but OISs on the DECdataway, we could say
that since a DIS uses two addresses, the DECdataway accommodates
31 of them. But this, in fact, may not be true. Other devices may
be present, and since these other devices also have varying
numbers of addresses, the number of DISs that can be attached to
the DECdataway is not always that straightforward.
Since the ISVII-B is our concern here, and since it is a DIS's
interface to the DECdataway, we will briefly discuss a typical
DIS.
4.3.3.1 Typical DIS -- Figure 4-3 shows a typical DIS. If you
ignore the block labell ed: OECdataway Inter face (ISVll-B), it is
an ordinary computer block diagram. It has: a memory to store
programs, a processor to run the programs, and I/O devices to
receive and dispatch data. But a few things are missing: there is
no console, and there are no mass storage or boot devices. That is
where the ISVII-B comes in; it takes the place of the extra
devices that would be needed if the DIS were not part of a
network.
So, to repeat what we said at the outset, a DIS is an LSI-II
computer with a DECdataway interface. How that interface works is
the next subject for discussion.
4.4
FUNCTIONAL DESCRIPTION OF THE ISVI1-B
As Figure 4-3 shows, the ISVII-B is i tsel f a computer: it has a
processor, a memory, and two I/O interfaces. One interface is to
the DECdatawaYi the other is to the LSI-II bus.
4.4.1
ISVll-B Processor and Memory
The processor is an 8080, and the memory is a combination of ROM
and RAM.
4.4.2
ISVI1-B to DECdataway Interface
This interface consists of a Universal Synchronous Receiver
Transmitter (USYNRT) chip, and a modem. It responds to commands
from a looping routine in the 8080.
Its function is to accept a serial, analog signal from the
DECdataway, and: demodulate it, digitize it, disassemble it from
its DSBC format, and reassemble it into 8-bit 8080 bus format. It
also does the reverse of this process.

4-4

ISVll-8
HOST

I
I
I

~--------~----~v~--------------~

LOCAL

TASK
INTERFACE

Figure 4-3

MA-7081B

DIS with ISVII-B Interface

4-5

4.4.3
ISVII-B to LSI-II Interface
This interface consists of: address decoders, data registers, CSRs
and multiplexers. It responds to commands from either the LSI-II
bus or the 8080 bus.
Its funct ion is to accept I6-bi t format LSI-II bus data, and
convert it to 8080 bus 8-bit format. It also does the reverse of
this process.
4.4.4
ISV1I-B Operation
Upon decoding a specific command in its received message stream
from the DECdataway, the ISVII-B's microprocessor executes one of
the programs stored in the ISVll-B's memory. Among the things that
these various programs cause the ISV11-B to do, are the following.
1•

Do wn -1 in e 1 0 ad p r og r am s f r om the h 0 s t to LSI -11 Memo r y
(including application programs, operating systems, and
diagnostics)

Down-l ine
memory

Boot the LSI-II

Halt the LSI-II

Run its own ROM-resident diagnostics (These
automatically when the power is turned on.)

load

blocks of data

from

the

host

LSI-II

also

run

4.5
ISVl1-B MAINTENANCE
Maintenance philosophy for the ISVlI-B is option replacement (both
modules). However, careful analysis of faults using diagnostics
and available test points should permit service personnel to
isolate a problem to one of the two modules. Note that the ISV1l-B
operates only as a unit, that is, with the M8080 and M8084 modules
connected together. However, they are not a matched set; a single
module can be replaced if necessary.
4.5.1
Built-In Diagnostics
There are on-board diagnostics contained in the ISVll's ROM
memory. These are a series of twelve tests (numbered one through
four teen, octal) tha t r un automat icall y every time the DIS is
turned on. If the DECdataway is connected, these tests run only
once, otherwise they repeat continuously (except in the case of
some error conditions). The tests are also run once by one of the
system-level diagnostics: the DECdataway exerciser. Associated
with the built-in diagnostics is a display, consisting of four
LEDs, that indicates the number of the test being run. There are
two types of tests: hardcore and softcore.

4-6

4.5.1.1 Hardcore Tests -- The first nine tests (1 to 11 octal)
are called hardcore because they test basic characteristics of the
ISVII-B. An error in any of these nine tests causes the ISVll-B's
microprocessor to loop within the test, thus continuously
displaying the number of the first-failed test. A hardcore error
also means that the DIS's communication interface is not
functioning properly. It is, therefore, prevented from trying to
communicate, so that it will not impair the communications of
other devices on the DECdataway. Table 4-1 describes the hardcore
tests.

Table 4-1

Hardcore Tests

Test

Module

Description

M8080

This test checks power-up configuration of 8080
I/O registers 1 and 2, and does basic 8080
instruction test.

M8084

This test does individual cyclic redundancy
check on each 8080 ROM.

M8084

This test checks writing and reading in the 8080
RAM and checks out RAM addresses.

M8084

This test checks transmission and reception in
USYNRT communications chip, using maintenance
mode.

M8084

If the dataway connector is unplugged (i.e.,
address 77 is read), this test checks
transmission and reception in the USYNRT through
the modem; otherwise the test is skipped.

M8084

This test checks ISVII-B interrupt system.

M8080

This test checks 8080 I/O register 2 and 8080
I/O registers (3--5) that are common with LSI-II
control and status registers (CSR2 and CSR4).

M8080

This test checks time-out feature of DMA logic
for access to LSI-II memory.

Both

This test checks LSI-II interrupt circuit in
ISVII-B.

4-7

4.5.1.2 Softcore Tests -- The last three tests (12, 13, and 14,
octal) of the ISVII-B ROM-resident diagnostic tests are called
softcore because they do not stop the ISVII-8 from communicating
with the host. These tests check the operation of the LSI-II CPU
(processor and memory). Test 13 takes about 11 seconds, but 12 and
14 are so fast thei r numbers may not be noticed in the LEDs. A
softcore error causes the failed test number to be displayed
flashing in the LEDs for 10 seconds. The error number (in decimal)
is also displayed at the operator's terminal. Table 4-2 describes
the softcore tests.
4.5.2
ISVII Indicators
The LED display for the built-in diagnostics, located on the edge
of the ISVII-M8080 board, provides much helpful information for
DYS50 fault analysis. Figure 4-4 summarizes the interpretation of
this display.
A LED on the ISVII-M8084 board flashes when a carrier is present
on the DECdataway. It flashes at a slower rate as carrier activity
increases.

Table 4-2

Softcore Tests

Test

Module

Description

LSI-II

This test loads a program into LSI-II memory and
then boots the LSI-II; this checks ability of
ISVII-8 to interrupt the LSI-II and vice versa.

MSVII

This test runs address and data tests on 28K
words of LSI-II memory.

LSI-II

This test runs LSI-II instruction test by
loading it into LSI-II memory and booting the
LSI-II to run it.

4-8

TEST NUMBER
DECIMAL OCTAL

**11

DISPLAY*
MSB

eooo
oeoo
eeoo
ooeo
eoeo
oeeo
e_eo

- - - NINE HARDCORE ERROR CONDITIONS:
OCTAL NUMBER IS DISPLAYED PERMANENTLY IF TEST FAILS (lSV11
CAN'T COMMUNICATE WITH HOST).
REPLACE ISV11. t

I
e}

LSB

o
oo
eo
0 .e
_

0_0
e _ 0- eO
0 ee}
eo.
_

THREE SOFTCORE ERROR CONDITIONS.
OCTAL NUMBER FLASHES FOR 10SECONDS. ITS DECIMAL EQUIVALENT
IS UPLINE LOADED TO HOST IF DATAWAY IS CONNECTED_ THE TEST
CYCLE THEN CONTINUES_ COMMUNICATION WITH HOST IS POSSIBLE.
IF ERROR IS 12 OR 13, REPLACE

oeee
e e e e ---

LSI-11 MEMORY-IF 14, THE PROCESSOR. t

--NOTUSED.
FATAL ERROR-MEANS ISV11
IS TOTALLY INOPERATIVE.
REPLACE ISV11. t

*BLACK = ON
** TEST 13 (OCTAL) LASTS ABOUT 11 SECONDS. ITS NUMBER IS DISPLAYED
ALL DURING THE TEST, BUT UNLESS IT IS FLASHING, THE TEST HAS
NOT FAILED.
t MODULE REPLACEMENT SUGGESTIONS ARE FOR MOST PROBABLE
FAILURES. OTHER FAILURES MAY SHOW THE SAME SYMPTOMS.

NOTE: THERE ARE TWO NO-ERROR DISPLAY CONDITIONS
1.

IF THERE ARE NO FAILURES, AND THE DATAWAY IS CONNECTED, THE LEDS DISPLAY A ZERO CYCLING FROM LEFT
TO RIGHT THROUGH A FIELD OF ONES.

IF THERE ARE NO FAILURES, AND THE DATAWAY IS NOT
CONNECTED, THE ON-BOARD DIAGNOSTICS KEEP REPEATING. THE LEDS DISPLAY EACH TEST NUMBER AS IT RUNS,
BUT 13 (OCTALIIS THE ONLY ONE OF SUFFICIENT DURATION TO BE READ EASI L Y.
MA-Ol04-B2

Figure 4-4

ISVll Display

4-9

4.5.3
Test Points
This paragraph identifies the locations and functions of ISVII-B
test points. This information helps when troubleshooting the
ISVII-B.
Lugs for the test points appear near the LEDs in Figure 4-5. On
the M8080, the three test points are to the right of the LEDs and
are numbered 4 to 6 from left to right. On the 8084, the test
points are to the left of the LED and are numbered 1 to 13 from
right to left.
4.5.3.1 M8080 Test Point Description -- Refer
M8080 module test point locations.

to Figure 4-6 for

Point

Signal

Meaning

TP4
TP5
TP6

DMR H
FRPLY H
WAIT L

Internal DMA request
Failed to receive DMA reply
Force 8080 wait state

4.5.3.2 M8084 Test Point Description -- Refer
M8084 module test point locations.

to Figure 4-7 for

Point

Signal*

Meaning

TPl
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TPll
TP12

PCS2 BUS MEMR L
SL5 T DATA H
+12 V
SLS T ENA H
-5 VB
-12 V
+5 V
-5 VA
GND
SLl DROPOUT H
SLl R DATA H
SLl T CLOCK H

8080 memory read
USYNRT serial output to modem
USYNRT transmit enable to modem

No signal on dataway
Received data to USYNRT
Transmitter clock from
KHz)

TP13

SLl R CLOCK H

Receiver clock to USYNRT

* Includes print on which it appears.
4-10

¢2

(55.556

DIAGNOSTIC
LIGHTS

TEST
POINTS

.-----.,. .-----.,.
IXI

M8080
MODULE

.-INTERCONNECTING
RIBBON CABLE
DECdataway
CONNECTOR",

M8084
MODULE

I
MA-71 00

Figure 4-5

ISVII-B Modules (Edge-On)

MA-2267C

Figure 4-6

M8080 Module

4-11

USYNRT
TP1

LED

PROM 0

PROM 1

PROM 2

PROM 3

PROM 4

SPARE
PROM
SOCKET
MA-2268C

Figure 4-7

M8084 Module

4.5.4
Module Troubleshooting
Use the following procedures to troubleshoot an ISVll-8 to one of
its two modules.
Service personnel can perform most ISVII-B checks with the modules
installed because all test points and LEDs are located at the
module edge. However, when it is necessary to access internal
points on the module, use the following set-up procedure.
1.
2.
3.
4.

Remove the ISVII-B module set.
Install a quad-height module extender (W987).
Plug the M8080 into the module extender.
Let the M8084 hang by the interconnecting cable.
CAUTION
Be careful
that the M8984 touches
nothing that will short any of its
components.

4-12

4.5.4.1 Quick Check for Major Problems -- These tests check the
basic functions of ISVII-B modules. They are particularly useful
if the 8080 does not run. (All maintenance LEDs are on.) Unless
otherwise ind icated, all test po ints are on the outside edge of
the M8084. Testing requires a voltmeter and an oscilloscope
(preferred) or logic probe.
NOTE
TP7 (+5 V) and TP9 (GND) can be used to
power the logic probe.
1.

Using TP9 as a ground reference, make
following supply voltages are present.

sure

that

the

+5 V + 5% at TP7
+12 V-+ 5% at TP3
-12 V + 10% at TP6
-5 VA + 5% at TP8
-5 VB + 5% at TP5
2.

Check that the modem transmitter clock, T CLOCK H, is
present on TPI2. It is a square wave with period 18 us.
This test also verifies that the 8080 clock generator is
working.

Check that 8080 memory read pulses, BUS MEMR L, are
present on TPI. This verifies that the 8080 is fetching
instructions and running. If not, ver ify on the M8080
that BPOK H (E14-12) and READY H (E70-23) are asserted.
Then replace the 8080 (E70).

The carrier-detected LED should turn on (dim or bright
glow) when a running dataway is connected, and turn off
when the dataway is removed. If the LED stays on, check
that T ENA L (TP4) is high. If T ENA L is asserted, the
USYNRT chip (E20 on the M8084) or the 8080 program flow
is defective.

4-13

4.5.4.2 Manual Modem Test -- Perform this test if test 5 (modem
test) in the power-up diagnostics fails. Test 5 does not execute
unless the dataway is disconnected. Furthermore, do not perform
this manual test unless the dataway is disconnected, to prevent
disruption of its ongoing activity.
The test checks out most of the circuitry interfacing the USYNRT
chip to the dataway. In particular, it ver ifies the following
items.
1.

The transmitter turns on and off.

The transmitter transmits ones and zeros.

The modem analog circuits transmit and receive data.

The receiver decodes ones and zeros.

The receiver detects the sync pattern (two successive
zeros following a one) that locks in carrier detected.

The receiver detects the pattern that drops
detected (absence of any transition for 1 to
times) •

carrier
1.5 bi t

NOTE
There may be subtle failures in ei ther
the analog or digital circuitry of the
receiver; these can cause occasional CRC
errors or other problems. However, these
failures may not be detected by this
test or test 5. If such a failure is
suspected, replace the ISVll-B.
The following tools are required to perform this test.
•

Two 6-inch jumpers with alligator clips or miniclips at
each end

•

Oscilloscope (or logic probe)

Observe the carrier-detected
success or failure.

LED

4-14

after

each

step

determine

Step

Effect

LED

Power up ISVlI-B with dataway.

Transmitter idle

Off

Connect jumper 1 from TP4
(E ENA L) to TP9 (GND) •

Transmit Is

Off

Connect jumper 2 from TP2
(T DATA H) to TP9 (GND) •

Transmit 0s

Disconnect jumper

1•

Transmit Is

Disconnect jumper

Transmitter idle

Off

these

with

If the test fails, repeat
scope after each step.
Step
1
2
3
4
5

R CLOCK H (TP13)
Log ic 0
Log ic 0
Square wave ( 18 us)
Square wave ( 18 us)
Log ic 0

it,

observing

points

the

R DATA H (TPll)
Log ic 1
Square wave ( 18 us)
Log i c 0
Square wave ( 18 us)
Log i c 1

4.6
ISVII-B DETAILED DESCRIPTION
The ISVII-B option consists of two quad-height printed circuit
boards. It is built around two large-scale monolithic integrated
circuits: an 8080 microprocessor, and an LSI synchronous
communications device (USYNRT). To understand how the hardware
functions, you must be familiar with the operation of these two
circuits as explained in the vendor manuals. A signal name
glossary appears at the end of this chapter.
Figure 4-8 is a block diagram showing the logical organization of
the hardware on the M8080 ISVll-B microprocessor and the M8084
serial
line unit.
Logically the system has
three major
subdivisions organized around two internal buses, one of which is
simply an extension of the LSI-II bus. The processing unit (upper
left in Figure 4-8) consists of elements of both boards. It
includes the 8080 microprocessor, its associated clock and gating
circuits, and local memory.
Communication between microprocessor and local memory is over the
8080 bus. This bus runs through both boards, connecting the
processing uni t to the other two major parts of the log ic. The
interface between the 8080 bus and the DECdataway (upper right in
Figure 4-8) is entirely on the M8084 module. This subsystem is
based on the USYNRT communications chip and connects to the
dataway by a modem. The remaining hardware (lower half of Figure
4-8) is on the M8080 module. It includes registers, decoders, and
other minor logic elements that connect the 8080 bus to the LSI-II
bus. The LSI-II bus in turn connects to the LSI-II, its memory,
and peripheral equipment.

4-15

RESE~ROCESrNG ..
U_N_IT_ _ _ _ _ _,--_ _ _ _ _ _ _r-.,-_ _ _I"'A_3__-7---,---s-E-R-'A-L-L-'N_E_U_N_'.,T
8224
CLOCK
PCS 2

</>2 TTL

I I

~~TK ~~g~~~~

tNT

! -.J
PCS 2
STROBE

ROM

ISL3

I
,
I

CONTROL &
ADDRESS

5KX8!

PCdl Jl
SL6 J2

MEM
BUS

1r---

INTERRUPT

r-n

SL3

B22B &
S241
DRIVERS i+--

[

U..--z----&.-"
/
~SL2 2X8/

SL2

I.1-

BO-87
SL5

B I+-

SL5

7X8

BUS 00-7

STATUS

8A-BF

PORT 90

SL5

5X8

SL5

DATAWAY

PORTS

•

'---...,r

Maoao
IADDRESS

I DMA D~'VERS'
lpes 8

DATA

IID~A

I ~r L

DRIVE!S'

PC S 8

DATA

IlD~A

DRIVERS'

CS
;:~ PL
8

,---J

8641

;

,---J

J~~:TROL

~j-1 P~

AO-7

tDO.4

PORT 2
pes 7
al- -

~~~ERRUPT 1----+--------+-------,

CONTROL

rrL.........i---+-~-I
5 ,6

PCS4

14-1----1

PORT 1
1+---+-+--+-......-t\PCS 7

I --f

81 [7

t-'-:"~=:-::--Il

PCS 4- 7

PCS 87°80
ADDRESS

1t 1L t

.-SRO

r1pc: a

I ____I_.....
-L~PC~S~L!!,'r_.1_1...JJ

PORTS 1 & 2 \

~ ~~:~~~~,VERS t-+-+-_C_ON_T_R_O_L_L_'N_E_S_+----....~--_+_---"--_+---I_'-----t'----+---_ _.....1

DECODERS

B DAL

DC005
BUS

DAL 0-15

LSI·ll INTERFACE
VECTOR

DAL 0-2

DO 3

pO- RT 5

PORT 4

~-~----+------------L-------~---~-r---+--~ CSR4

M_A_T_e_H_II_ _ _ _ _

ADDRESS
PORT BO
SL4
,6

M~_84______ (~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .

BOBO
BUS

PORTS

INTE:RUPT r---PORT AO f4"-

1 KX8

r r r
---J

CONTROL

6
1

14-------+-411-+-'1

~ fL.:=~-~-;-+

All
1u
( ~ \

\
1..----.....
LSL1

L-.lSL5
SL2

}_
- - - -...
RA M

DATA

SL1AI

-----+j USYNRT 'I+------t' MODEM

PRIORITY

Q
y ____________________

PCS 2

'---

CONNECTORI

~S~L~4~__j

BOBO

DECdataway

-v-

</>2 TTL

AO-3

INTERNAL LSI.ll BUS EXTENSION

DALO-3

,'pcs

3 4 PCS 3

,
PORT 3 i
CSR2
16

CSRO

PCS 7
DAL °

DAL 0-3

~ TRANSCEIVERS~~~-----~----~------------------------L-S-,-,I-O-A-D-D-R-ES-S-E-S-:-16~O-1-4-0-+-C-S-R~N-U-M-B-ER------. .----~
PCS 4

Figure 4-8

8080 M EMORY ADDRESSES FOR PORTS: 4000 + PORT NUMaER

ISVll-B Logical Organization

The hardware on each module appears in a set of circuit
schematics, code CS. Each set has a drawing number in the form
X-0-1. (X is the board designation.) A revised schematic has a
revision letter to the right of the drawing number. The individual
sheets of each drawing set are labeled for convenient referencing.
For example, the labels on the six sheets of 54-13290-0-1 (M8084
module) are SLI to SL6, and those on the eight sheets of M8080-0-l
are PCSI to PCS8. These labels serve as prefixes in signal names
to indicate signal origin. They also appear in the text and block
diagrams for referencing individual prints.
In Figure 4-8 these labels appear in the lower left corners of
each block to indicate which print contains the logic represented
by the block. Parts of a print are indicated by combining the
let ter sand number s along the edges. Par ag raphs 4.7 thro ugh 4.9
give a detailed descr iption of the hardware on the two modules.
Discussion is geared to the prints, but you should also refer to
Figure 4-8 whenever necessary.
Some logic signals on the boards are available at test sockets
sh 0 wn in the lowe r 1 eft 0 n S L6 and the u ppe r rig h ton PC S 6 • In
some cases the lines to these test pins are not true logic signals
at all, but gate inputs tied to +5 V. Therefore, they play no real
role in system operation; but they can be pulled low to disable
var ious parts of the log ic for GR test purposes. These pseudo
signals are identified on the prints by the word test.
4.7
PROCESSING UNIT
This unit occupies part of both boards and appears on three
pr ints: PCS2, SL 2, and SL 3. PCS2 shows the 8080 microprocesso r
with its clock and gating circuits. The 8228 has bidirectional
drivers for the 8 data lines in the 8080 bus; the two 74S241s
below it provide unidirectional driving for the 16 address lines.
The 8224 clock circuit at the left supplies the 01 and ~2 clocks
for the microprocessor chip, and the ¢2 TTL clock for the serial
line unit. (All clocks are 2 MHz.)
At the beginning of every microprocessor machine cycle, the 8080
places status information identifying the use of the cycle on its
D outputs; it also sends a sync signal to the 8224. The 8224
responds by sending a strobe to the 8228, causing it to load
s tat us i n t 0 a set 0 f 1 at c h e s • Th i s f r e e s t h e d a t a l in e s for
transfers during the cycle. The status information indicates the
kinds of events that occur during the cycle. From the latched
status bits and 8080 control signals WR (write) and DBIN (data bus
in), 8228 sets up memory, I/O control signals, and interrupt
acknowledgement for the cycle.
A memory read can fetch an instruction, an operand, or an item
from the stack; writing in memory can be for an operand or a stack
i tern. Bus I/O control signals (in field DI on the pr int) are
produced by the 8228 I/O outputs. However, they are also asserted
by the memory control signals when the address is in the 4000 to
7FFF range (the area of the ISV11-B address space reserved for I/O
reg isters) •
4-17

The ready input to the 8080 through the 8224 is high, except when
a wait is needed for a DMA operation. ENA DMA enables the 8093 so
that WAIT goes low; when the acknowledgement appears, READY goes
high and the 8080 continues. But, the DMA signals have no effect
when I/O WR is true. This prevents an unwanted wait from hanging
up the 8080 if DMA signals are generated inadvertently because an
I/O operation looks like a DMA operation to DMA logic. When the
8080 does an input or output instruction, it puts the one-byte
address on both the upper and lower half of the address lines.
Therefore, an I/O port address of 80 or above puts a one on line
15, which may generate ENA DMA. The I/O WR prevents any wait
during an IN instruction; however, the I/O WR occurs later during
an OUT, and the 8080 may enter the wait state for a single cycle.
The RAM and ROM that constitute local memory are on SL2 and SL3
res pe c t i vel y • Th e RAM i s rna de up 0 f e i g h t 1 K X I chi P s , e a c h
storing a single bit of each byte in the IK. The ROM is made up of
five lK X 8 chips (with space for a sixth), each storing the
entire byte for IK locations. Logic gates at the upper left on SL2
produce a memory select when the 8080 calls for a memory read or
write with an address in the 0 to IFFF range. The select, in turn,
enables the decoding of address bits 10 to 12 at the lower left on
SL3 to select a single ROM chip or the set of eight RAM chips. The
10 least significant address bits are applied to the address
inputs of all chips to select the individual location.
When the RAM is selected and the function is write, bits from the
eight data lines are written into the eight RAM chips. The output
o f t h e s e 1 e c ted ROM, 0 r set 0 f RAMs, i s a v ail a b 1 eon the S L3
memory bus. During a read, the data is placed on the 8080 bus via
the multiplexer at the upper right on SL2. Drawing TD-ISV11A-0-7
shows the timing of the signals involved in the 8080 reading and
writing memory.

4.8
SERIAL LINE UNIT
The heart of this unit is the USYNRT synchronous communications
chip at the left on SLS. It is set up for byte operation by a high
level at pin 22 and connects corresponding pins for the left and
right bytes of its 16 data inputs-outputs. These connect to the
eight data lines of the 8080 bus. The 8080 governs the device by
supplying control bytes and reading status. The USYNRT in turn
uses the modem for handling communication over the serial
DECdataway. Serial data received from the modem at RSI is
assembled into bytes, and available to the processing unit via the
eight data 1 ines. Transmi t bytes suppl ied over data 1 ines are
passed on serially to the modem from TSO.
The 8080 moves bytes to and from the interface via its I/O ports.
Port selection is made by the address decoder at the right on SL4.
Th e n umbe r 0 f po r t s i s sm all, and a n I/O bus con t r 0 1 s i g n a l i s
generated by either an I/O transfer or memory access in the
appropriate address range. Therefore, decoding a few address bits

4-18

and the I/O signals is sufficient to select among ports 90, A0,
B0, and the USYNRT registers. From port B0 the 8080 can learn its
own dataway port address, wired into the DECdataway connector and
available through the gates at the left. SEL 8X enables the USYNRT
data lines.
Selection among various registers is made by address bits 0 to 2,
applied to the USYNRT address inputs on SLS. Register reading and
writing uses separate addresses, so A03 is connected to the USYNRT
wr i te input. A one enables wr i ting and dr ives the USYNRT data
lines from the 8080 bus through the two 74S241s at the lower
right. When a zero places a register on the data lines, READ 8X
from the addr ess decoder dr i ves the 8080 bus from them. The E30
gate below the decoder on SL4 prevents any register selection if
the 8080 should give a read function for a write port.
The remaining two ports are at the upper right on SLS, where
address 90 reads status bits from the USYNRT and modem, and the
LSI-II interrupt request through E22. Address A0 loads a byte from
the 8080 bus into the register in E27. The control bits supplied
include enables for transmitter and receiver in the USYNRT
maintenance mode, and for var ious condi tions that can request
interrupts through gates at the upper right.
Select ing rna intenance mode inhibi ts gener ation of the tr ansmi t
enable to the modem (T ENA at eI), even if the USYNRT transmitter
is active (TX ACT). The interrupt request levels are applied to
the latch and pr ior i ty networ k at the upper left on SL2. Any
interrupt request produces the INT signal, which goes to the 8080.
An acknowledgement from the 8080 latches the current request,
enables the multiplexer for the SL2 bus (8080 bus data lines), and
selects as multiplexer input an RST instruction encoded from the
number of the highest priority request. The 8080 then executes the
RST as a call to the cor respond ing locat ion (as listed in the
table at the lower right on SLS).
4.8.1
Serial Transmitter-Receiver
The modem for the serial line unit takes up most of SLI. The basic
time reference is the f(j2 TTL clock suppl ied by the 8224 clock
circuit associated with the 8080 microprocessor. This clock drives
the receiver directly. For the transmitter, the exclusive OR gate
at A7 (with the delay introduced by two inverters at one of its
inputs) acts as an edge detector to multiply the basic clock to 4
MHz. From this, the E28 counter produce~ the 8X clock by dividing
by nine. This is accomplished by loading 7 at the clock following
the carry out produced by a count of IS. The 8X clock counts the
E23 counter, which runs on a continuous 16-count cycle so that its
two mid dIe bit s pro v ide d i vis ion by 4 and 8. Th e T ( 1 X) c I 0 c k
drives the USYNRT transmitter and shifts out the data; the IX and
2X clocks 1:;ogether are used for biphase encoding of data
transmitted over the dataway. Table 4-3 lists characteristics of
the various clocks.

4-19

Table 4-3

Clock Characteristics

Clock

Period (us)

Frequency

¢2 TTL

0.50

2 MHz

ax CLK

2.25

444.444 KHz

2X CLK

9.00

111.111 KHz

T CLOCK

18.00

55.555 KHz

The modern is coupled to the DECdataway by transformer Tl; its
secondary winding connects the serial line at pins 9 and 10 of the
internal dataway connector. The transformer is the 1-1-1 type. A
pul se tra in in from the I ine generates two output tr a ins, one
positive and the other negative; both have the same amplitude as
the input. The transmitter uses only one primary coil each way, so
the output is a 5 V signal, either positive or negative.
The two Zener diodes back-to-back (shown at the left of the
connector) draw no current until the potential reaches 9 V; then
they draw a great deal. This prevents a surge on the dataway from
burning out the operational amplifiers. During transmission the
Zen e r s 1 i mit 0 u t pu t to 9 V , even tho ug h the t ran sm itt ere ire u i t
output is about 12 V. There is an effective 100 ohm load with the
dataway connected. This is due to either the 200 ohm terminating
resistor being in parallel with the cable or mounted in the middle
of the 200 ohm cable. Therefore, the line is actually driven at
abo ut 5 V.
The only control signal supplied by the USYNRT to the modem is T
ENA at D8. When this signal is true, the TI primary can be driven
at one side or the other to drive the serial line. When T ENA is
false, the transmitter is disabled, and the receiver picks up any
data corning from the DECdataway.
The disable and external inputs, as well as various circuit
outputs, are available at the test socket on SL6. Test inputs
allow for disabling the clock and the raw received data; then
external inputs can be substituted for them. Conversely, without
the disables, the external connections make the internal clock and
raw data available at the test socket.

4-20

4.8.1.1 Transmitter
Data from the USYNRT enters the
t ran sm itt e r c i r cui t a t E31-1 3 ( C8), AN De d wit h the T c I 0 c k • Th e
gate keeps the J and K inputs to the E12-5 flip-flop high, except
when the data bit is one and T clock is high. Therefore, a zero
enables JK for the whole bit period, and a one enables it for half
the bit period. You can see this in Figure 4-9, which shows the
relationship between data, flip-flop signals, and transmitter
clocks. The flip-flop toggles twice during a zero bit, but only
once during a one. The state of the flip-flop drives one side or
the other of the T1 primary.
Therefore, there are two
zero-crossings during transmission of a zero on the dataway, but
onl y one dur ing a one. Th i s i s the so-called biphase modulat ion
technique of data transmission.
The circuit in D8 senses the +5 V. Should the voltage drop
slightly, Q4 conducts and disables T ENA. Therefore, if the power
is fa i ling, the transmi t ter is disabled even if the USYNRT is
sending data (which may be invalid).
4.8.1.2 Receiver
Changes in current flow through the T1
primary are sensed by the receiver circuit (shown at top-center on
SL1). A switch in direction, caused either by the serial line
( sec 0 nd a r y) 0 r t ran sm itt e r, rever s e s t he s tat e 0 f the raw d a t a
outputs (shown at the upper right). A string of logic components
is shown from left to right, across the center, and in the lower
right of the print. These logic components process this raw data
to detect the start of message, derive data bits and a clock to
pass on to the USYNRT, and detect a dropout of the received
signal. The logic is driven by the 2 MHz ~2 TTL clock, which runs
at 36 times the bit rate of the dataway. Therefore, the clock not
only synchronizes the raw data to the ISV11-B, but also provides a
finer resolution for sampling it.

4-21

Figure 4-10 is a simplified diagram of the receiver with most
components in the same relative position as they appear on the
print. The dual signal generated by the Tl primary from the
dataway is applied to a pair of operational amplifiers. These have
gain +1 and high input impedance for isolation. The 56K input
resistors prevent a power turn-off in the ISV11-B receiver from
dragging down the dataway. The bandpass of the filters at the
amplifier outputs eliminates both high and low frequency noise,
but it attenuates the signal to about one third.
For generating raw data, the threshold comparator uses a reference
of 50 mV; this guarantees the spec of 100 mV, one-third of the 300
mV minimum dataway signal. A swi tch in the comparator outputs
occurs only when the signal goes above the positive threshold
after having been negative, or below the negative threshold after
having been positive. Changes in the raw data are synchronized to
the clock by a flip-flop.

THRESHOLD
COMPARATOR

TRANSITION
DETECTOR

SAMPLE
INPUT

1/>2 TTL H

+3V

R CLOCK L

lSB IN

PHASE
COUNTER

TRANSITION
HISTORY
SHIFT
REGISTER

CNT EN
CARRY
OUT
ClK

ClK

PHASE
COUNTER

lD
ClK
L.--_--I CNT
EN

CARRY
OUT

MA-2287

Figure 4-10

Receiver Simplified Block Diagram

4-22

The logic shown across the lower part of Figure 4-10 contains
three main parts: a transition detector at the left, a
phase-locked clock generator, and a shift register for recording
recent transition history in raw data from the receiver circuit.
This history is necessary for recognizing the start of message and
modem dropout. It also distinguishes between zeros and ones in the
received data it supplies to the USYNRT. Figure 4-11 shows the
timing of major signals associated with this transition processing
logic.
A message always starts with several ones followed by at least two
zeros for synchronization. Figure 4-11 shows signal configuration
for a message beg inning wi th 100, followed by several arbi trary
bits, and then a modem dropout. The transition detector generates
three signals associated with a transition in the raw data.
Following synchronization of a transition, the first 2 MHz clock
produces the transition-detected signal. This is on for two clock
periods; during that time it turns off the detector to inhibit
further sampling of the raw data. This filters out noise near the
modem comparator threshold, preventing any noise surrounding a
transition from being mistaken for another transition. The second
signal, transition delayed, has the same form as transition
detected; however, it has opposite polarity and is offset by one
clock period.
Th e d iff ere nee in the s e t wo s i g n a 1 s i s t hat t ran sit ion de tee ted
inhibits the detector (resetting the phase counter), and
transition low actually represents the transition for processing
by the remaining logic. The third signal from the detector
produces the phase-locked clock, which occurs at the end of
transition detected.

(\[Y7

\-36-1
4J2TTLH

11~lml~llllllmllllll~ll~m~IIIIIIIIIIIII~llmll~mllllllmlIlmllllllllmmllllllllllllllllllllllllllllllllllllllllllllOOlll1111~llllllllllllllllllllllllmlllllllllllllllllllllllllllllIllmllllllllllllllllllllllllllllllllllllllllmlllllllllllllllllIIIIIIIII
LINE IDLE

RAW DATA

--J._. . . . . . ____-

TRANSITION DETECTED _....JL----'I'--~L_JL__..H._ _--'L_ _

---'~

TRANSITION DL YD
T
PHASE-LOCKED CLOCK

I I I I I
I I
I I I I
____________~*____~I.+. . .___~---t~---------

R DATA L

Figure 4-11

MA-2288

Receiver Timing

4-23

The phase counter is reset at every transition, but in the absence
of transitions it simulates the phase-locked clock every time it
reaches 30. The Ts and Ns in the timing diagram distinguish
phase-locked clocks produced by transi tions (T) from those that
are not (N). Figure 4-11 illustrates the exact-theoretical timing
for a serral signal from the bus. In a real situation, transitions
can be quite late without adversely affecting reception.
Each phase-locked clock shifts the transition history. Where the
bit shifted into the register reflects transition low, detection
of a transition causes a zero to be entered. After ~he line has
been idle, the phase-locked clock that occurs at the fifth
consecutive transition (a one succeeded by two zeros) clears the
dropout flag, turning on the LED. From that point on, the data
represented by the bottom line in the diagram is available to the
USYNRT from the second bit ~osition in the history shift register.
The USYNRT samples incoming data at the R clock, which is
represented by arrows and occurs at the trailing edge of the
phase-locked clock. The absence of two transitions in a row sets
the dropout flag, turning off the receiver clock.
The above discussion should provide a basic understanding of what
the receiver does, and how the incoming data is supplied to the
USYNRT. But to understand in detail how the logic works, turn to
the circuit schematic (print SLl) and the complete timing diagram
(TD-ISVIIA-0-8), which show all associated signals. Raw data
synchronization is provided by flip-flop E8-9 located at 83 on the
print. The transition detector at the left is made up of a shift
register and three exclusive OR gates. When pin 9 of Ell is high,
each clock shifts the register, sampling the raw data at the LSB.
Wh e n pin 9 i s low, e a c h c 1 0 c k loa d s the r eg i s t e r fro m the d a t a
inputs; but these are connected so the register still shifts,
ignoring the raw data. Therefore, each transition is shifted
through the register, giving a sequence of signals through the
exclusive OR gates.
E9-1l and E9-6 are transi tion detected and transi tion delayed.
These gates are driven from pins 13 and 15, and 11 respectively
(not 14 of Ell), so they generate signal trains with on times of
two clock periods (E9-6 offset by one period). E9-8, which
generates the phase-locked clock, is fed from Ell-13 and 11, and
thus occupies the second half of the transition-delayed on time.
Binary counters E3 and El are configured for a count of 30, 17 in
E3 plus 13 in El. Detection of a transition clears E3 and sets an
enable-disable flip-flop (E8-5). This allows E3 to count the 2 MHz
clock after transition detected goes off, but inhibits El from
doing so. When E3 counts to 15, the carry out loads three into El
and sets the flip-flop. This disables E3 and enables El, which can
then continue the count. When El reaches 15 (total 30), the carry
out produces a phase-locked clock and clears the flip-flop; the
next 2 MHz clock clears E3 to restart the count. Therefore, a
phase-locked clock occurs at each transition, and also when there
i s a c 0 un t 0 f 30 wit h 0 uta t ran sit ion. ElSi s the his tor y s hi f t
register.
4-24

Initially the Ell bits are alike: E9-11 is low, which causes the 2
MHz clock to shift Ell; E9-8 is high, so the phase-locked clock is
low; and E9-6 is also high. When the raw data changes, the next 2
MHz clock shifts Ell. This causes pin 15 to differ from the other
three outputs. In particular, pin 15 differs from pin 13, so E9-11
goes ~Jgh, en~bling ~~~ load function at both Ell and E3.
'The first clock after detection of the transition loads zero into
E3 and shifts Ell without sampling the raw data. That is, pin 15
remains the same and the transition lies between pins 14 and 13.
With this change, E9-6 supplies a low input to E15 D0 and E2 J.
The second clock loads again, moving the transition between pins
13 and 11. Thi s causes E9-8 to drop, produc ing a phase-locked
clock which shifts E15 and loads zero into E15 R0 since E9-6 is
still low.
E9-11 also drops, which reenables shifting and counting. The third
clock then counts E3 to one and shifts Ell, resampl ing the raw
data and shifting out the preceding transition. This raises both
E9-6 and E9-8, dropping the phase-locked clock. If a transi tion
were detected, E9-11 would again go high and start the whole
sequence over.
Serial line transmission always begins with a few ones followed by
at least two zeros. The final one and the two zeros prov ide a
string of five transitions, a half bit time apart. Following the
jus t de fin e d pro c e d u r e , yo u can see t hat the fir s t f 0 u r
transitions result in four zeros being shifted into EIS. This
enables the AND gates at the clear input to the dropout flip-flop
E2. At the fifth transition, the phase-locked clock clears E2.
This removes both the dropout signal to the USYNRT and the
hold-clear on flip-flop E12-3, generating the R clock for the
USYNRT receiver.
Once the system is synchronized to the incoming serial signal, a
transition that occurs before a count of 30 following a preceding
transition produces a phase-locked clock that loads a zero into
E15. If there is no transition by clock 29, clock 30 counts E3 to
15, and the carry out produces a phase-locked clock that loads a
one into El5 (since E9-6 ish igh). But subsequent detect ion 0 f a
transition before the next 29 count (restarting the count with no
transition detected ships the extra load) generates a phase-locked
c I 0 c k t hat loa d s a z e r 0 in toE 1 5 • Th ere for e , a z e rod a t a b i t
causes the loading of two successive zeros into the first two
stages of E15. A one results in a zero in R0 and a one in RI
following a pair of shifts. Thus, at the end of each bit time, the
state of R1 represents the received data.
Since at this time R0 is zero for either a zero or a one data bit,
the trailing edge of the phase-locked clock sets E12-3 to start a
cycle of the R clock. Since the K input is held high, the
flip-flop clears in the middle of the next bit time regardless of
what the first phase-locked clock brings into R0. The first data
bit the USYNRT actually reads is the second zero in the sync pair.

4-25

If no transition is detected through the fifty-eighth clock, the
fifty-ninth counts E3 to 15 a second time. This produces a second
nontransition phase-locked clock. With E9-6 still high and a one
al ready in E15 R0, this sets E2, ind icat ing a modem d ropo ut and
disabling the receiver clock.
4.8.1.3 Negative Voltage Converters -- The circuit at the left on
SL6 provides one -12 V and two -5 V supplies from +5 V. Two
separate -5 V supplies are necessary for handling the large power
requirements of the PROMs.
Each -5 V converter consists of an inverter oscillator using a
saturable core transformer, a negative rectifier, a filter, and a
three-terminal regulator chip that produces the regulated -5 V.
Oscillator frequency is about 40 KHz. The transformer primary has
a 9 V square wave centered at +5 Vi the secondary has an 18 V
square wave centered at ground. Filter output to the regulator is
approximately -8 V.
The -12 V converter uses the 9 V square wave across the T3 primary
to drive a charge pump (C55, 010, 011, C56). The pump output is
superimposed on the -8 V rectified secondary output to produce an
unregulated -17 Vi this is converted to a regulated -12 V by Zener
diode 012.
To prevent large instantaneous switching currents in the
oscillators from coupling into the main +5 V supply, they have
separate, inner layer ground and V
planes. The separate V
plane is decoup1ed from the main plcirre by an LC fil ter, and tfi~
separate ground plane is connected to the main ground plane at a
single point.
4.9
LSI-II 8US INTERFACE
This unit handles all communication (progr·ammed transfers, OMA
transfers, and interrupts) between the ISVll-8 and the LSI-II
processor and memory. The bidirectional LSI-II internal bus
extension (PCS4 OAL) interfaces to the bidirectional LSI-II bus
data and address lines (8 OAL) via the OC005 transceivers at the
left on PCS4.
The XMIT input is enabled for dr i v ing the LSI-II bus from its
extension during one of two events: when the LSI-II is reading a
control status register (CSR), or when the ISV11-B is sending OMA
address or data to the LSI-II memory or I/O bank. At all other
times the REC input is enabled, driving the extension from the
LSI-II bus. However, enabling REC also allows high levels at the
JAV inputs to dr i ve the LSI-II bus 1 ines independentl y. These
inputs are connected for VECTOR to place an interrupt vector on
the 8 OAL lines, where a jumper in is a one.

4-26

Wh e nth e I/O ba n k s e 1 e c t s i g na 1 BS 7 i s t rue atE 2 3 -1 3 , the J A
inputs are compared with levels on certain LSI-II bus lines. The
I ines are not connected to the chips in order; this allows a
compar ison between JA inputs and bus 1 ines 3 to 12. The match
output is true when BS7 is true and bus lines 3 to 12 contain the
address of the ISVII-B CSRs set into the JA jumpers. A jumper in
is a one.
Type 8641 transceivers are used for interfacing to LSI-II bus
control signals (usually bidirectional). These transceivers appear
on various prints, next to the logic with which they are
associated.
4.9.1
Port Transfers
programmed transfers are handled through what are regarded as
16-bit control status registers from the LSI-II, and 8-bit ports
from the 8080 microprocessor in the ISVII-B. Furthermore, since
addressing is from different buses and the I/O banks occupy
different parts of the processor's address spaces, there are two
completely separate address decoders.
The LSI-II decoder is a standard OC004 (PCS4 right) enabled by
matching the ISVII-B CSR jumper address with the address supplied
on the B OAL lines. Bus control signals come to the DC004 via the
transceivers on PCS6, since the same signals are also involved in
DMA control. The sync latches the three least significant address
bits, which are decoded for selecting the CSRs. (Select signals
are backward, since high levels are applied to the OAL inputs.)
For output, OOUT generates a high or low byte strobe, or both,
depending on OAL 0 and whether WTBT selects a byte or whole word.
For input, DIN gives an INWD strobe. Both the address latch and
the data strobe produce a bus reply through the 8641.
The LSI-II suppl ies the address of the transfer control block
(TCB) via the CSRs on PCS3. The only other data comes to the
ISVII-B via CSR0, when a one on DAL 0 sets the flip-flop in the
lower right corner on PCS7 to request an 8080 interrupt. The gate
just above provides a read strobe for CSR0, allowing the LSI-II to
read its own interrupt request and other status information via
the 74LS367 (E7) at the lower left corner on PCS8. For test
purposes the ISVII-B can load the CSRs via the I/O page in LSI-II
address space.
Decoding addresses of 8080 ports in the LS-I-II bus interface is
accomplished by the logic at the top on PCS7. There, address bits
o to 2 are decoded to select the port on an I/O function when bits
3 to 7 are all zero. Only ports 1 and 2 (the E39 and E36 registers
below the decoder) can be written by the 8080, and for these the
select lines also generate write signals on an I/O write. From
these two ports, the only bit the LSI-II can read is boot status
( po r t 1 bit I ) t h r 0 ug h CS R 0 • Se t t i ng and c 1 ear in g po r t 1 bit 7
boots the LSI-II by simulating a power-up signal on the DCOK line
of the LSI-II bus. To halt the LSI-II, port 1 bit 6 is handled by
a separate flip-flop, so it can also be set by a power failure.

4-27

Port 2 bit 5 is not included in the register, because it is used
to clear the LSI interrupt request flip-flop at the lower right.
Port 1 bit 0 and port 2 bit 4 do not show up here at all; they are
used to request interrupts at the LSI-II as described in the
following discussion.
The 8080 can read most of what it supplies to ports 1 and 2, plus
a few other bits from interrupt and DMA control, via the E38 and
E40 multiplexers at the left. Port 0 is not used; ports 3, 4, and
5 correspond to the three bytes of the TCB address in CSR2, CSR3,
and CSR4 (PCS3).
4.9.2
LSI-II Interrupt Control
Interrupt requests from the 8080 to the LSI-II are handled by the
standard DC003 dual-interrupt circuit at the upper right on PCS4.
The 8080 can make requests on two levels, A and B, associated with
vector locations 300 and 304 respectively in the LSI-II. Request
inputs to the DC003 are held high, so making and dropping requests
on levels A and B respectively, are under writing control in port
1 bit 0 and po r t 2 bit 4 • S tat us 0 f cur r en t i n t err up t r e que s t s
(LSI-II bus A and B) is available to the LSI-II via CSR0, and to
the M8080 via ports 1 and 2.
A request made on either level asserts the BIRQ signal to the
LSI-II. Once the LSI-II responds with DIN and the acknowledgement
SIAKI, the DC003 disables BIRQ and asserts VECTOR. This produces a
bus reply through the DC004 below and places the vector address on
the LSI-II bus via the DC005 JAV inputs at the left. The signal
VEC RQST B puts a zero or one on line two, depending on whether
the interrupt is on level A or B.
4.9.3
DMA Transfers
The upper 32K-byte half of the 8080 address space is used for
referencing any 32K-byte section of the LSI-II address space by
means of DMA transfers. Before initiating any DMA operation with a
28K memory, the 8080 must set up AD 15, which is port 2 bit 0
(PCS7 B4), as address bit 15 on the LSI-II bus. This indicates
which half of the LSI-II address space is referenced when AI5 on
the 8080 bus is one. Then, the 8080 simply makes a memory
reference in the upper hal f of its own space, to reference the
selected half of the LSI-II space, using DMA request and control
logic on PCS5 and PCS6. (A 124K memory would require that AD 16
and AD 17 be set up as well.) The 8080 must also set BS7 (port 2
bit 3) if the address location lies in the I/O bank. Two timing
diagrams,
TD-ISV-IIA-0-5
and
TD-ISU-IIA-0-6,
show
the
relationships among the various quantities involved in output and
input DMA transfers: LSI-II bus signals, control signals for the
8 0 8 0 , the 8 0 8 0 c I 0 c k s, and mac h i n e s t ate s • An R 0 r T i n
parentheses next to a signal name means it is received or
transmitted by the ISVII-B over the LSI-II bus.
Addresses and data move between the two buses via the 74LS367
drivers on PCS8. The signal T ADDR EN places the address on the

4-28

LSI-II bus through parts of the driver chips at the left. However,
only 15 bits come from the 8080 bus address lines; bit 15 (A8)
comes from port 2 instead. Each data transfer is a single byte,
with the low or high position on the DAL lines selected by A00.
Data is gated from the 8080 bus to LSI-II bus by T DATA EN, with
the low byte handled by E60 and part of E46, and the high byte by
ES9 and part of ESI. Gating from the LSI-II bus to 8080 bus is
controlled by a DMA signal derived directly from the 8080 memory
read, with the low byte handled by E6l and part of E7, and high
byte by ES2 and part of ESI.
An 8080 memory reference in the 8000 to FFFF range produces ENA
DMA at the upper left on PCSS. This causes the 8080 to wait by
pulling down the 8224 ready input on PCS2. On PCSS it generates
the appropriate DMA memory read or write level, and a DMA requestthat goes out on the LSI-II bus and also clears flip-flop ElS-9 at
the lower left. When the LSI-II sends the DMA grant in, E12-S
sets, preventing the grant from passing out to the next device.
With the grant on, negation of both the sync and the reply at the
end of the current bus cycle sets E12-9. This generates SACK on
the LSI-II bus to acknowledge that the ISVll-B has become bus
master; it al so drops the request, following which the LSI-II
drops the grant.
The acknowledgement also triggers a timing circuit based on shift
register E9 at the upper left on PCS6. SACK sets E19-S to feed a
one into the LSB register and causes the output of the E17-8 AND
gate to go low. The output of this gate is fed back to one of its
inputs·. This makes the output oscillate, which supplies a
rising-edge clock with a period of 110 ns beginning about half a
period after SACK goes true. Since the setting of E9 R0 clears
E19-S, the clock provides timing for the transfer by passing a
single one through the shift register.
This moving one, in turn, controls the column of flip-flops shown
at the center of the drawing. Al in R0 sets T ADDR EN to place the
address on the LSI-II bus, and to gate the state of BS7 from port
2 onto the B BS7 line. This indicates whether the transfer is for
memory or the I/O bank. At the same time a write function turns on
T WTBT to specify an output byte. Time 330 turns on T SYNC, and
time 440 clears T ADDR EN. For writing, 440 also sets T DATA EN to
gate the byte onto the LSI-II bus, and SS0 turns on T DOUT to make
the slave accept it. But for reading, SS0 turns on T DIN to tell
the slave to send data; the read level itself gates the DAL lines
onto the 8080 bus, with the transfer time determined by the slave.
With SACK still asserted, the reply from the slave produces the
DMA acknowledgement (C7) that frees the 8080. The freed 8080
negates the memory signals, negating DMR (PCSS). DMR then cancels
either T DOUT or T DIN, whichever is on. Finally the trailing edge
of RRPLY triggers an identical reset timer based on shift register
E10. Reset time Rl10 turns off T SYNC, T DATA EN, and T WTBT (if
on); it al so sets ElS-9 (at the lower left on PCSS) to turn off
SACK.
4-29

Each request triggers the 39 us one-shot in the time-out circuit
at the bottom on PCS6. Completion of a transfer clears it and
prevents the clear ing from affecting the EIS-5 fl ip-flop at the
right. However, should the one-shot time out, it indicates failure
of the slave to reply in a reasonable time; then the flip-flop
sets to generate FRPLY. This signal produces the DMA ACK to free
the 8080. When DMR subsequently goes off, it clears FRPLY but also
sets E19-9, triggering the reset time to clear the DMA logic.
4.10
FUNCTIONAL FLOWS
Figures 4-12 through 4-17 show the system's major operations in
terms of functional flow, that is, as the signal paths and logic
elements that enter into their execution. All logic elements are
labeled for the circuit schematics on which they appear. To help
pinpoint the trouble, the figures identify all significant
elements that playa role in a given operational sequence. You can
then turn to the referenced schematics for details of circuit,
signals, and pin connections.
These flows are meant to stand alone; no written description
accompanies them since the detailed description of the logic,
geared to schematics, has already been presented. All lines are
labeled with the actual signal names from the schematics; wherever
possible the logic elements are represented by the symbols in the
schematics. It has, however, been necessary in some cases to use
ordinary blocks as logic elements. These are easily identified
because the signal lines entering them have arrowheads.
None of the diagrammed operations comprise only a single sequence
o f even t s • Ra the r, e a chi sma de up 0 f s eve r a l l 0 g i call y dis tin c t
but interdependent sequences, such as an 8080 instruction followed
in order by an interrupt and another 8080 instruction. Another
sequence is an 8080 instruction followed in order by a response
f r om the LS I -1 1 and a n act ion by the I SV 11 -B. Th e n urn be r s i n
circles indicate the order in which the hardware parts are
employed for these sequences. Sections of the hardware tested by
power-up diagnostics are labeled with test numbers.
The six flows are in three pairs, and all operations shown involve
the microprocessor. The first two drawings show the movement of
information in either direction through the serial line unit. The
next pair show DMA transfers through the LSI-II bus interface.
Figur e 4-16 shows an ISVII-B inter rupt request to the LSI-II.
Figure 4-17 shows an interrupt request in the opposite direction,
the only operation that uses elements of both interfaces in the
ISVII-B. There are many other minor operations, such as the 8080
reading or writing a port, and the LSI-II making a CSR transfer.
You can easily identify compon~nts that enter into these simpler
operations directly from the circuit schematics.

4-30

TRANSMITTER
CIRCUIT

w::.
I

.....

(TEST 51
TX ClK
SL5
CLOCK
L -_ _ _ _ _ _ _ _ _ _

~~'~2~TT~l~H~----------------------------~COUNTERS
(x2 + 9 + 4,81
SL1

t_T~C~lO~C~K~H~______________~~'~'~

2X ClK H
t-..;.....:..;;;.;..;....:.:.------------------I

Sl1

Figur e 4-12

Ser ia1 Line Out

MA-2289

PCS1 J1.
SL6 J2

r"'. INT H
8080
ETC

BUS INT ACK L

PCS 2

INTERRUPT
LATCH &
PRIORITY
ENCODER

~SEL

-0

BUS 1/0 R L

• BUS A03-07 H

PORT
ADDRESS
DECODER

. / SL4

R4 , . - R5

SL5

CLK

SEL AO L
READ

03
r - - - 05

RSA

RDA H

PORT
AO

~O/C SL2/

BUS I/O W L

+3V- D

• • • • • • • • +3 V

• BUS DO-7 H

SL51

S L5

L-

\. SL5

INT RQ 6 H
(TEST 6)

SL2

DROPOUT L -. H OR RSA H

INT RQ 7 H

-C

SL5

SL5 ~
RX ENA
DRIVERS
PORT
80

SL5

ax L

USYNRT
(TEST 4)

SEL 8X H

DP ENA

~ ADR SEL

AOO-03 H

RSI RX CLK

SL5

RDATA~

I RCLOCK~
I

1/12 TTL H

'-'"

TRANSITION
DETECTOR.
HISTORY. ETC
SL1

(TEST 5)

DROPOUT H

RECEIVER
CIRCUIT

RAW DATA H
SL1

Figure 4-13

Serial Line In

DMA MEMW H

OMA ENS H

W M R H.

PCS 5
B DMR L

~tA-.VPCS>-~W~A~IT~L~Ri[D)y :- ~B~U~S~M~E~M~R~L:...I~CS? ~
2

_
PCS 5

8080
BUS A15 H~

ETC

BDMGI L _

,JV

....P
...C_S.,.2_--ar-'

SACK L
DMA

p::A:T

BSYNCl--<:v~ I

fEtC
5 S B SACK L
-

DMA
TIMER

SACK H

330 H
440 H

f-_-...............--..:;.;.,...:;.;.,.----.f PCS 6

----+ B DOUT L
DMA
CONTROL - - - B SYNC L
----+ B WTBT L

550 H

BOM~Ol

PCS6

DMAACKH

~~
RESET
PCS"M.~U-_--L._-+-_R_R_P....;.L....;.Y_L---1H-_ _ _-+-___+I TI M ER
R110 H

4
B RPL Y L -0 PCS 4

DMRL

--B-- PCS6

F RPLY H

l+j TIMEOUT /(TEST 10)

---ipcs 6

AOO H

f--------------------------------------------------------------~TADDREN

"
BUS AOO-14 HV"

~ DO

RO AD ,. H

PORT

2
PCS 7

PCS 8 - BUS 0 -+DAL HB L

L)
~

Figure 4-14

~4Sf----r----

DRIVERS ~-O--1-5----,

PCS 8 16

~p_CS

__------T--D-A-T-A-E-N-H-----__
. _

BUS 03 H - 03

DRIVERS ~-----~DAL~V~~--X-M~I-T----.
8-15
DC005
PCS 8 8
TRANSCEIVERS

I 0

BUS DO-7 H

PCS 4

__
7rBS7H
PCS7

L-J

r-B BS7 L

PORT

2
PCS7
/~
~S 7
PCS 7 0-R BS7 L
(FOR TEST ONLY - LOADS OWN CSR"':"S'K..'"
(TESTS 7 AND 1 1 ) ' ...........

...J
Ll)

DRIVERS
0-7

'I
o
...J

PCS8

«
o

III

MA-2291

DMA Transfer Out

WAIT L

ROY

B SACK L

8080
ETC

OMA
TIMER

OMA
CONTROL

330 H
.wOH

PCS6

550 H

RESET
TIMER

Rll0 H

B DIN L
B SYNC L

PCS6

B SYNC L

R RPLY L

B RPLY L

PCS 6

r---------------------------------------------------------------------~TAOORENH

AOO H

B BS7 L

o H DO

1----"

......._-.0..1

PORT

PORT
2

pes 7

PCS 7

BUS 00-7 H

OAL LB ~ BUS 0 L
MA·2292

Figure 4-15

DMA Transfer In

BUS DO H

BUS 04 H

B080
ETC
BUS IfOWL

PCS2

8080
PORT
ADDRESS
DECODER
PCS 7

WRITE 1 H
WRITE 2 H

0
ENA OAT

BIRO

BIRO L

ENB OAT

BIAKI

BIAKI L

BDIN
DC003 DUAL
INTERRUPT CIRCUIT
ENA CLK

VEC ROST

ENS CLK

VECTOR

PCS4
(TEST 12)

0
B DIN L
DC005

VEC ROST B H
VECTOR H

DC004

BUS

B DAL 0-15 L

PCS4

VECTOR
BRPLY

BRPLY L

PCS4
MA·2293

Figur~

4-16

ISVII-B Interrupt Request to LSI-II

INTERRUPT
LATCH & t-_N_T_H________---,
'
PRIORITY

r---------------------------~D
r---~~-..,DAl 0 H

B DAL 0-15 L

OAT DAl1 H
DAL2 H

DC005
TRANSCEIVERS

B BS7 L

BS7 L

XJ~-~ MENB

DAlO
DAll

PCS 7

DC004

MATCH 1------..... ENB

SEL 0 L
SEL 61------<..lI
OUT LB L

PORT
AO
SL5 ClK

OUTLB~----~U--~

BUS DO H

L - - - -l

0'\
B SYNC l

~I__--------------------~SYNC

WTBT

BRPlY

DOUT
, - -_ _ _ _ _ _ _ _ _ _ _ _ _- - J

B WTBT l

DAl2

PCS4

INT RQ4 H

SEl AO L
I
I
I

8080
ETC

PORT
ADDRESS

DECODER ..........;;;...;;..;;...~----+----.tf+-l

S~
I
1L ________________ J

PCS4

PCS 2

BUS 05 H

8080

B DOUT L

WRITE 2 H

PORT

BUS AOO-07 H

ADDRESS
BUS 1/0 W l
DECODER ....--~~..;..;....;;.....--------.j
PCS7
MA-2294

Figure 4-17

LSI Interrupt Request

4.11
SPECIFICATIONS
The ISVII-B places one dc unit load and four ac unit loads on the
LSI-I! bus, and has the following dc current requirements.
+5 V

3 • 0 A ma x i mum

+12 V

o• 3 7 A rna x i murn

LSI-II Interface
CSRs

160140, 160142, 160144

Interrupts

300, 304

DECdataway Interface (modem)
Port addresses

Two consecutive, lower wired
into connector

Operating mode

Hal f-dupl ex

Data format

Synchronous, serial, LSB first
(DSBC)

Character size

8 bits plus 0 to 2 stuffing
bits

Data rate

55,556 bits per second

Transmission technique

Biphase modulation

Transmitter timing

Crystal clock

Receiver timing

From received signal

Line interface

Transformer coupled

Transmitted signal

5 V peak-to-peak into
terminated 200 ohm cable

Receivable signal threshold

150 mV peak-to-peak minimum

Error-free signal level

300 mV peak-to-peak minimum

Common mode isolation

350 Vac rms, 500 Vdc

Receiver bandpass

6 KHz to 130 KHz (-3 dB points)

4-37

4.12
ISVII-B Signal Glossary
This glossary lists all signals that appear on the circuit
schematics for the M8080 and M8084 modules, as well as the print
on which each appears. Some bus signals are generated on several
prints. Many LSI-II bus signals originate outside the ISVII-B as
well as inside. A pr int designation in parentheses indicates a
signal that appears on that print as an input but is never
generated by the ISVII-B.
Signal

Definition

¢ 1 , 2, C LOC K H

PCS2

2 MHz clocks generated by the
8224 for the 8080.

¢2 TTL H

PCS2

2 MHz clocks generated by the
8224 for the USYNRT.

IX CLK H

SLI

Equals T CLOCK H.

2X CLK H

SLI

For biphase encoding, this clock
has twice the frequency of T
CLOCK.

ax CLK H,L

SLI

Intermediate signal in
transmitter clock (eight times
dataway bit rate).

PCS6

Timing signals for DMA.

AD 15-17 H

PCS7

Hig"h-order address bi ts for DMA.

BAD 16,17 L

PCS7

Expansion address bits for LSI-II
bus.

B BS7 L

PCS7

Bank select 7 -- LSI-II bus
signal to select I/O page in
LSI-II address space.

B DAL 0-15 L

PCS4

LSI-II bus data and address
lines.

B DCOR H

PCS7

LSI-II bus dc power okay.

B DIN L

PCS6

LSI-II bus - master requesting
input, or LSI-II getting vector
address in response to interrupt.

BDMGI L

(PCSS)

LSI-II bus DMA grant in.

BDMGO L

PCSS

LSI-II bus DMA grant out.

330 H
440 H
550 H

4-38

Signal
B DMR L

Print
PCSS

Definition
LSI-II bus DMA request.

B DOUT L

PCS6

LSI-II bus
master has data
available for output.

B HALT L

PCS?

LSI-II bus

BIAKI L

(PCS4)

LSI-II bus interrupt acknowledge
in.

BIAKO L

PCS4

LSI-II bus interrupt acknowledge
out.

B INIT L

(PCS4)

LSI-ll bus -- in ISVll-B
initializes only interrupt
control.

BIRQ L

PCS4

LSI-ll bus interrupt request (to
LSI-II).

BOOT LSI H

PCS?

Boots LSI-II by simulating power
up (through control of B DeOK).

BPOK H

(PCSS)

LSI-ll bus ac power okay.

BRPLY L

PCS4

LSI-Il bus reply.

BS? H

PCS?

Bank select ? for I/O page -conditions TBS? when address
placed on LSI-ll bus.

B SACK L

PCSS

LSI-ll bus -- acknowledges that
ISVII-B has been granted master
status in DMA operation.

B SYNC L

PCS6

LSI-II bus -- master has placed
address on bus.

BUS A00 L

PCS?

From BUS A00 H.

BUS A00-IS H

PCS2

8080 bus address lines.

BUS D0-? H

PCS2,3,?
SL2,4

8080 buS data lines.

BUS D2 DAL HB L

PCS8

8080 data to LSI-ll bus high
byte.

BUS INT ACK L

PCS2

8080 interrupt acknowledge.

BUS I/O R L

PCS2

8080 reading an I/O register
(por t) •

4-39

halt processor.

Signal

Definition

BUS I/O W L

PCS2

8080 writing an I/O register
(por t) •

BUS OUT EN L

SL2

8080 reading local memory or
receiving interrupt RST.

BUS MEMR L

PCS2

8080 reading memory or I/O
register addressed as memory.

BUS MEMW L

PCS2

8080 writing memory or I/O
register addressed as memory.

B WTBT L

PCS6

LSI-II bus write/byte.

CARRIED LED

SLI

Controls carrier-detected LED.

CPU SYNCH H

PCS2

8080 signal to 8224 to indicate
first state in each machine
cycle.

DAL 0-15 H

PCS4, 7

Data and address lines on
LSI-II bus extension.

DAL LB2 BUS D L

PCS8

LSI-II bus data low byte to
8080.

DIN L

PCS6

Received B WTBT.

DIS 8X CLK L

SL6

GR test disable for 8X eLK.

DIS I/O L

SL6

GR test disable for 8080 I/O
address decoder.

DIS MEM L

SL6

GR test disable local memory.

DIS RAW DATA L

SL6

GR test disable receiver.

DMA ACK H

PCS6

DMA request has been
acknowledged by LSI-II bus.

DMA MEMR H

PCSS

8080 reading in LSI-II address
space.

DMA MEMW H

PCSS

8080 writing in LSI-II address
space.

DMR H,L

PCSS

DMA request -- generates B DMR
for 8080 to access LSI-II
address space.

DOUT L

PCS6

Received B DOUT.

DROPOUT H,L

SLI

Dataway signal absent.
4-40

Signal
DROPOUT L2 H
OR RSA H

Print
SL5

Definition
Dataway signal dropped out (1.5
bit times without transition) or
USYNRT receiver status available.

ENA DMA H

PCS5

8080 addressing LSI-II space.

EXT 8X CLK L

SL6

8X CLK at test socket; or can
be used for external clock if
DIS 8X CLK.

EXT RAW DATA H

SL6

RAW DATA at test socket; or can
be used for external data if
DIS RAW DATA.

EXT R CLOCK L

SL6

External test receiver clock
for USYNRT.

EXT R DATA L

SL6

External test received data for
USYNRT.

FRPLY H,L

DCS6

Forced bus reply.

HALT LSI H

PCS?

Generates B HALT.

INT H

SL2

Interrupt to 8080.

INT Q BUS A H

PCS4

LSI-II bus interrupt control
waiting for interrupt on A
level, or has vector 300 on B
DAL lines.

INT RQ 4-7 H

SL5

Interrupt requests to 8080.

INWD L

PCS4

From B DIN sent by LSI-II for
CSR.

I/O PAGE L

PCS2

8080 addressing I/O register as
memory location.

I/O R L

PCS2

8080 IN instruction (I/O read).

I/O W L

PCS2

8080 OUT instruction (I/O
wr i te) •

I/O WR H

PCS?

Equals I/O R "OR" I/O W.

PCS4

Jumper address inputs to
DC005s.

JAV

PCS4

Jumper vector address inputs to
DC005s.

LITE 1-4 L

PCS?

Control M8080 LEOs.
4-41

Signal

Definition

LSI INT REQ H

PCS7

Equals CSR 0 bit 0; this is an
LSI-II request for an 8080
interrupt.

MARGIN -5 V

SL6

GR test margin for -5 V for
PROMs.

MATCH

PCS4

Address on B DAL equals jumper
address (JA) on DC00Ss (LSI-II
addressing ISVII-B CSRs) •

MEM BUS D0-7 H

SL2,3

Data bus for output from local
memory.

MEMR H

PCSS

Equals BUS MEMR.

MEMW H

PCSS

Equals BUS MEMW.

MEM SEL L

SL2

8080 accessing local memory.

MENB

PCS4

Enables match with JA in
DC005s.

OUT HB H

PCS3

From OUT HB 1.

OUT HB L

PCS4

LSI-II loading CSR high byte.

OUT LB H

PCS3

From OUT LB L.

OUT LB L

PCS4

LSI-II loading CSR low byte.

PHASE-LOCKED
CLK H

SLI

A clock (train) geared to last
signal transition detected on
dataway.

PORT ADDR 1-6 H

(SL4)

Port address wired into dataway
connector.

Rl10 H

PCS6

Reset time for DMA.

RAM SEL L

SL3

8080 accessing the RAM.

RAW DATA L

SLI

Output of modem receiver
circuit.

R BS7 L

PCS7

Received B BS7.

R CLOCK H,L

SLI

Receiver clock derived from
incoming bit stream.

RDA H

SLS

USYNRT output -- received data
available.

4-42

Signal

R DATA H,L

SLI

Definition
Modem received data output to
USYNRT.

R DCOK L

PCS7

Re c e i v e d a DC 0 K•

READ 8X L

SL4

8080 reading I/O register in
address range 80--87.

READ CSR L

PCS7

LSI-II reading CSR 0.

READY H

PCS2

Pulled down by the 8224 on a
wait to idle the 8080.

REC H

PCS4

ISVII-B is not now sending
information on LSI-II bus a DAL
lines.

RESET 1 H

PCS2

Generated by 8224 when apOK H
goes down.

RESET H,L

PCS2

Equals RESET 1.

RESET H,L

SL6

M8084 reset from PCS2 RESET L.

R HALT H

PCS7

Received a HALT.

RPOK L

PCSS

Received apOK.

RRPLY H,L

PCS4

Received aRPLY.

RSA H

SL5

USYNRT output
available.

RX ACT H

SL5

USYNRT receiver active.

SACK H

PCSS

Send a SACK for DMA.

SEL 0,2,4 L

PCS4

CSR address decoder outputs.

SEL 8X H

SL4

8080 accessing I/O register in
address range 80--87.

SEL 90 L

SL4

8080 reading I/O register 90
(USYNRT status) •

SEL A0 L

SL4

8080 writing I/O register A0
(USYNRT control) •

SEL B0 L

SL4

8080 reading I/O register B0
(port address) •

4-43

receiver status

Signal

Definition

SELECT 1-5 L

PCS7

Address decoder outputs for
8080 I/O registers in LSI-II
bus interface.

SRPLY H

PCS4

Send BRPLY.

STROBE

PCS2

Send 8224 to 8228 in response
to CPU SYNC; latches 8080 cycle
status in 8228.

SYNC L

PCS6

Received B SYNC.

T ADDR EN H,L

PCS6

Transmit address on B DAL for
DMA.

TBMT H

SL5

USYNRT transmit buffer empty.

TBS7 H

PCS7

Transmit B BS7.

T CLOCK H

SLI

Transmitter clock -- 55,556 KHz.

T DATA H

SL5

USYNRT serial data output.

T DATA EN H,L

PCS6

Transmit data on B DAL for DMA.

T DIN H

PCS6

Transmit B DIN for DMA.

T DOUT H

PCS6

Transmit B DOUT for DMA.

T ENA H,L

SL5

Enable modem transmitter (when
USYNRT transmitter active but not
in maintenance mode) •

TEST DISABLE
8080 L

PCS6

GR test disable 8080 operation.

TEST DISABLE
I/O L

PCS6

GR test disable 8080 I/O
register addressing.

TME H

PCS7

Time-out enable for DMA.

TMO H

PCS7

DMA time-out.

TMO ERR H

PCS7

Time-out error status bit (8080
to LSI-II).

TRANSITION
DETECTED H

SLI

Receiver detected a zerocrossing.

TRANSITION
DLYD L

SLI

Transition detected inverted and
delayed 500 ns.

4-44

Signal

Definition

T RAW DATA H

SLI

Flip-flop biphase-encoded data
signal applied to transmitter
circuit.

T SYNC H

PCS6

Transmit B SYNC for DMA.

T WTBT H

PCS6

Transmit B WTBT for DMA.

TX ACT H

SL5

USYNRT transmitter active.

VEC RQST B H

PCS4

Makes vector jumper address 304
when VECTOR is true.

VECTOR H

PCS4

Places vector jumper address
(JAV) on B DAL when the 8080
interrupts the LSI-II.

WAIT L

PCS2

Puts 8080 in wait state until DMA
acknowledged.

WRITE 1,2 H

PCS?

Select 8080 I/O registers 1 and 2
for writing.

WTBT L

PCS6

Received B WTBT.

4-45

CHAPTER 5
BAII-Y POWER SYSTEM DESCRIPTION

5.1
INTRODUCTION
The BAl1-Y power system has four major assemblies.
1.
2.
3.
4.

Power supply (H7861)
Backplane (H9276)
Modul e cage
AC input panel (front panel)

These are identi f ied in Figur e 5-1, which shows the BA11-Y wi th
its cover removed. In addition to the major assemblies, the figure
shows the locations of several subassemblies that are of interest
to anyone servicing the unit. These are:
1.
2.
3.
4.

Module-assembly and power-supply fans.
AC and dc harnesses.
Bezel PC board assembly.
Power supply control and power-monitor boards.

Figure 5-2 links these components functionally.

POWER
MONITOR
BOARD

POWER

kimmi-ii7-T,'III7""""--"--supp LY
FAN

H7861
POWER
SUPPLY

MODULE
CAGE
ASSEMBLY
MA-0233-82

Figure 5-1

BA11-Y Major Assemblies
5-1

POWER SUPPLY, H7861

r;,;s,.E-;Bo;R~(54-i45i"3)

I
I

- - - - ...,
I
I

SWITCHING AND POWER TRANSFORMERS,
DC VOLTAGE REGULATORS

ACIN

(70-17971-0)
DC HARNESS
+5 VDC
+12 VDC

I
I
L ~_--I~ - + - -....... -+---+- -+--........
SIGNAL CABLE
(70-11411-0K)

U1
I

TO POWER
CONTROLLER

IV
SIGNAL CABLE (7011411)

+12V
TEST
POINTS

RTN
+5V

FRONT PANEL

P1
MR-6517
MA-l0.495

Figure 5-2

BAII-Y Functional Block Diagram

5.1.1
AC Input Panel
The ac input panel is also the front panel. Power is provided to
the panel from the ac mains by either a 120 V line cord or a 240 V
line cord.
The panel includes an ac input connector, a line filter, a fuse,
an ON/OFF switch, and a switch that makes the correct connections
to the fans and the power supply for both 120 Vac and 240 Vac line
voltages.
The output of the panel is taken to the fans and the power supply
by an ac power harness. Connector PI of the harness is a
Mate-N-Lok connector (9-pin), while P2 and P3 are molded ac plugs
that break out of the harness to plug into terminals on the fans.
5.1.2
87861 Power Supply
The H7861 power supply occupies the upper, rear quarter of the
DYS50 space. It is attached to the logic cover assembly with two
releasable hinges. It is fastened to the power supply bracket with
two screws. When the two screws are removed, the supply can be
tipped back to allow service access. The entire power supply can
be removed easily by removing the two screws, unlatching the two
hinges, and disconnecting four cables.
Th r e e p r i n ted c i r cui t boa r d s co n t a i n a 11 the po we r sup ply
components. The control board and the power moni tor board are
inserted in connectors that are mounted on the master board. The
regulated dc vol tages generated on the master board are sent to
the H9276 backplane by a dc harness that connects on both ends to
screw terminal s. The signal s gener ated on the cont rol boa rd are
applied to the backplane and to the front panel by two different
signal cable assemblies.
5.1.3
89276 Backplane
The H9276 is a 9 X 4 backplane, i.e., nine slots of four rows
each; both double and quad modules can be inserted. Rows A and B
of each slot supply the extended LSI-II bus signals; these signals
are bused to each of the nine slots.
The pins of the C and D rows are not bused; however, the pins of
adjacent slots are connected. This not only precludes the
necessi ty of top connectors, but al so prov ides the means for
designing buses whose lengths are determined by the number of
modules in a set. The C and D rows of the backplane are referred
to collectively as the CD bus.
5.1.4
Front Bezel Assembly
The front panel can be blank or it can be equipped with switches
and indicators. The switches allow an operator to turn the power
on and off (only when connected to a power controller), to reboot
the CPU, and to suspend the CPU's usual program execution. The
indicators, when lit, tell the operator that the power supply
vol tages are enough for operation and the CPU is running. The
front panel is connected to the power supply master board by a
signal cable and, if appropriate, to a power controller by a
twisted-pair cable that can be provided.
5-3

5.2
DETAILED DESCRIPTION
A detailed description of each component of the power system
follows. Figure 5-3 is a unit assembly drawing that shows details
of the power system interconnections.
5.2.1
AC Input Panel
Figure 5-4 is a schematic of the ac input panel. The fans and part
of the power supply master board are shown to present the primary
power connections. T4 of the master board is the +12 V start-up
transformer; Dl, C2, and Cl convert the ac voltage to nonregulated
dc voltage, as described in Paragraph 5.2.2.1.
The line cord that supplies primary power is inserted in the male
connector, FLI. The line voltage is controlled by SW2, which is
used as an ON/OFF switch when a power controller is not used. When
SW2 is closed, the line voltage is applied through Fl and the line
filter to the voltage selection switch, SWI. This switch is
mounted below SW2 on the front panel and is in the correct
position when the printing over the switch lever agrees with the
line voltage being used. SWI allows the system to run on 120 Vac
or 240 Vac by connecting the line to the power supply input and
the two fans. For example, the fans are provided with 120 Vac,
even when the line voltage is 240 Vac.
5.2.2
87861 Power Supply
Figure 5-5 is a block diagram of the H7861 power supply. All of
the power supply components are mounted on three printed circuit
boards -- a master board, a control board, and a power moni tor
board.
The master board consists of an ac input circuit, the +5 V and +12
V regulators, and a +12 V start-up supply. The ac input includes a
thermostat that protects the supply from too much heat. The
thermostat swi tch opens, disconnecting the ac input, when the
ambient temperature reaches 85 0 C (185 0 F); the 0swi tch closes
0
automatically when the temperature returns to 64.4
C (148
F).
The ac input circuit converts the 120 Vac or 240 Vac input to raw
dc vol tage. Thi s dc vol tage is appl ied to a power converte r
circuit that is switched on and off to produce rectangular-wave
vol tag e s t hat are a p pI i e d t 0 the reg u 1 a tor c i r cui t s • Th e
rectangular-wave input to each switching regulator has a duty
cycle that differs with the level of the unregulated input
vol tage. If, for example, the input vol tage dec reases, the 5 V
control circuit on the control board causes the power converter
circuit to increase the duty cycle of the rectangular wave.
Therefore, the output voltage is maintained at its correct level.
The 12 V c i rcui t has a swi tching transistor in ser ies wi th the
inverter circuit output. This switch corrects the converter output
pulse to maintain a duty cycle that will average 12 V.
Each regulator circuit is a switching regulator with an averaging
filter and includes overvoltage and overcurrent circuits that
protect the supply against overload conditions. The regulated
outputs are monitored by the control board. The outputs are also
applied to the H9276 backplane.
5-4

LOGIC
FAN

PWR. SUP.
FAN

r;"R; ;;N~ - - -,
P2 0

~OI~~~~

I
I
I
I
I

",-ZZLOLn_

_________
r J - lJ2 1
- .
J2-2

1 +5 VDC
2 +5 VDC

J2-3
J2-4

3 +5 VDC

J2.5

4 GND

J2.6

5 GND

J2·8

Ic=:=:::::l c=:=:::::l c:::::==J c=:=:::::ll
•

ROW 0

ROW CROW B

7 GND
8 +12 VDC

H7861
CONTROL BOARD

..,:.
a:

- 1--BPOK H .
BB1--W
BR1·B EVENT L - - L T C .
A F 1 - - - S RUN L
BLANK PIN

Jl·5

5 GND

Jl·4

4 GND

Jl·3

3 +5 VDC

I>.

P2·3
P2·4
P2·5
P2·6
P2-7
P2·8
P2·9
P2·10

I~
g~~'----+5 e~~:

GND •

Pl·6
SW2·3
Pl-4

P2·1
P2·2

1
2
3

Fl·2
FL 1·3
SW1·8
SW1·5
SW1·3

Pl·8
FL1·l
SW2·'

CABLE SIGNAL
7011411

H7861
POWER MONITOR
BOARD

NEUT~3
GND 2 •

Fl·1

LINE

ONMLj(JTHGFEDCBA

!--=-J.:..,.'.:..,.7.......-1""'17GND
Jl-6
6 GND

e.>

•

c..

1 Pl

1--""";;"-+-1"'" 18 +12 VDC

-.=-- _"2- - -

en
>

IAUX POWER

::t:

<t
I-

_ _ _ __

::>

Jl·2

VID SYNC H •
I
AP1---B HALT L •
BA1---B DCOK H •
==-~-==~SL~ _ _ _ _ _ _

I>.

IC,!)C,!)+++

J31
SLOT 1

ROW A

L.! ____.__ I

DC POWER
HARNESS
7018964·00

Jl.8

H9276
I LOGIc' ASSEMBLY
I BACKPLANE
I

~J2~..:..7""'-016 GND

I-

R!!!.O~~E__

Pl·3
P3·2
SW2·4
Pl-3

L K J

~~~f-f-:I-ff-X-:S:- __
-1f-f-ffif-f-:1f-fffib:e
~

~ I-~ I-~

I-

::::;1-1-

H G F E ,0 C B A

I-

J3 _10 2..!..7

)
.Joe.>
a:(!l>
I0
M
::>
N
UJ

<tz<t

I-

UJ
a:
a:
::>
e.>

e.>

::t:.J
~I-

O.J
(.)<t
o::t:
alal

2 +5 VDC

I--"-J1;....1'----+<t1) I 1 +5 VDC

lSI ___

J6{

I
I CABLE
I REMOTE
I SWITCH

~ 4~ 1

J5{

e.>
0
>00
",zz
+(!lC,!)

::t:

UJe.>

(.)0

It)

Pl·l
Pl·2
Pl·3
Pl·5

CABLE SIGNAL 7011411

(o 0

•

S RUN L
BLANK PIN
GND
GND
+5 VDC

•

Pl-7
Pl·8
Pl·9
Pl·l0

OJI
I
; I : ~~~K
I
I
I
I •
I•
I
8 I •
I •
I
I•
I
L: ~ZEL
31
41
5
6
7

)

•••

(.)

«
>

::>e.>0
a:1-1>.
en.Jal

z<t

:J>

FL1

•

SPARE
B HALT L
B DCOK H

9
10
P2

TPl +5 V

MA·10,494

Figure 5-3

BAII-Y Interconnections

r;,;;:;;S;'- - - --,

AC POWER
HARNESS

*
3

FL 1

SWl 230V
7

P1
) 7

J) I MAlTER BOARD

) 4

8
U1

I
0'\

I
I
I
I
I
I
I

L_____ ...I
S1

r:-~

P21~1
1-------42

>t-L:J

L---~P3, r-:---L.::J
k

'--------~ 2

L:_~
MA-0214-82

Figure 5-4

AC Input Schematic

rCONTRoLBO- -

I
I
I
I
I
I
115VAC--r-+----------------------,

COMMON~~~

OVER-CURRENT
DETECT
+5 VDC

230VAC~~~-----,r_----~~

~--+-----~---'@36A

I
U1

I
....,J

L _______ _

+12 V START-UP

I
I
.J

r - - - -POwERl
MONITOR BO

I
B POK H

B DCOK H

LTC

L _____ ...J
MR·6576
MA-0185-82

Figure 5-5

H7861 Block Diagram

The +12 V start-up supply produces a dc voltage that is necessary
during start-up operations. When steady conditions are attained,
the +12 V regulated output takes over for the start-up voltage. If
the +12 V regulated output should be lost dur ing operation, the
start-up voltage is available to keep the control board and power
monitor board circuits operating.
The control board circuits monitor the regulated output voltages,
comparing them to control board-generated reference voltages, and
feed them back to the main converter. When either regulated
voltage varies from its prescribed value, the appropriate control
circuit varies the duty cycle of the rectangular-wave as needed.
This forces the output to return to the correct value. Adjustment
potentiometers are provided in each control circuit, enabling the
output voltages to be adjusted to account for initial tolerances
of circuit components.
The power monitor board generates two signals -- BPOK Hand BDCOK
H
that enable the CPU to carry out specific power-up and
power-down operations. The signals are asserted in a set sequence
both when the power is turned on and when the power is turned off
or lost because of failure (the sequence is described in Paragraph
5.2.2.5). Also included on the board is a clock generator that
produces a line-time clock (LTC) signal. This signal is applied at
the CPU, where it generates vectored interrupts at the line
frequency.
5.2.2.1 AC Input Circuit -- Figure 5-6 shows the ac input circuit
of the power supply. The ac input vol tage is converted to dc
voltage by bridge rectifier D1 and capacitors Cl and C2. When the
input is 240 Vac, D1 corrects the ac voltage, and Cl and C2 smooth
the ripple that appears on the dc output of the rectifier.
However, when the input is 120 Vac, Dl, el, and C2 become a
voltage
doubler.
Therefore,
the
dc
voltage
produced
is
approximately the same for both line vol tages and can change
between 200 and 375 Vdc.
This dc voltage is applied to a switching circuit that includes
transistors Q1 and Q2 and transformer Tl. Ql and Q2 are switched
on and off at 30 kHz. The duty ratio is determined by the +5 V
control circuit on the control board. When the transistors are on,
the corrected dc voltage appears across the primary of transformer
T2 (pins 1-2) and is combined with each secondary of T2. The dots
on the windings of T2 (Figure 5-6) represent the more positive
side of each winding at this time. When the transistors are
switched off, the voltage across the primary of T2 reverses its
polarity instantaneously. The same polarity reversal occurs in the
secondaries of T2; then, an alternating wave is generated at the
secondaries of T2. Each regulator uses the positive half cycle of
the secondary voltage to produce a positive dc voltage. The +5 V
regulator winding also uses the negative half-cycle of the
secondary voltage to produce a nonregulated, negative dc voltage
(-12 Vdc) , which is used to bias ICs on the power monitor board.

5-8

FROM OVER VOLTAGE PROTECT

T1 6
R1

II 5

COMMON--"T---JVI,.,.........~

} FROM +5 V CONTROL CKT

1'.

FROM 12 V
CONTROL

115 VAC--+---.---+--~----1
230 VAC--+-+--.--+------'

2.
R10

12.6 VAC
~--------------------~~ 4
2

......._t--T"-'-+12 V START·UP

MR·6556
MA·0194·82

Figure 5-6

Inverter Circuit

The rest of this section expands the preceding short description
by focu~ing on the current and voltage relationship in transformer
T2. Figure 5-7 links the current and voltage waveforms in the
primary and secondary windings of T2. At time A, transistors Ql
and Q2 are off. During this time, a steady current is moving
through the secondary winding of transformer Tl from pin 5 to pin
6 (Figure 5-6). At time B, the +5 V control circuit causes the
current in winding 5-6 to stops moving. A voltage that opposes the
decrease in current (i.e., a counter-EMF)
is produced across
winding 5-6; thus, pin 5 becomes negative with respect to pin 6.
Voltages having the same polarity are induced in the other
secondaries and the primary of Tl. These voltages forward-bias the
emitter-base junction of both Ql and Q2,· turning on the
transistors. Collector current starts to flow from Ql through the
pr imary of T2 from pin 2 to pin 6, through Q2, and through
secondary winding 2-1 of Tl. Then, the corrected dc voltage
appears across the primary of T2, pin 2 being the more positive
side of the winding.

5-9

1 - - T = 3 3 J . L s - - -1t1
It-

11-2

__________ ..I

V1-2

V5-6

,
I

........._.A-_~

V3-4

MR-6557
MA-0195-82

Figure 5-7

Current/Voltage Relationship in T3

The current moving in the primary of T2 is determined by the load
on each secondary winding. At time B, a steady current is moving
in the primary of transform~r T3 from pin 6 to pin 5, and
transistor Q3, which is part of the +12 V regulator circuit, is
not conducting. Then, there is no load on secondary winding 7-8 of
T2, and the primary current of T2 is a function of only the +5 V
regulator. At time C, the +12 V control circuit causes the current
in wind ing 5-6 of T3 to stop mov ing. The counter-EMF genera ted
across the primary winding is coupled to both secondaries of T3,
and the polarity of the induced voltage forward-biases the
emitter-base junction of Q3. The +12 V regulator starts to operate
and the current drawn from the secondary of T2 is echoed back to
the p rim a r y 0 f t hat t ran sf 0 r mer. Th en, the tot a 1 cur r en t i n the
primary of T2 quickly grows, as shown by the current waveform in
Figure 5-7.
After the sudden increase at time C, the primary current begins a
more gradual, linear increase, resulting from a constant voltage
across the primary winding. At time 0, the +5 V control circuit
causes a steady current to start moving once more in winding 5-6
of transformer Tl. The bias vol tage is removed from Ql and Q2,
turning them off. As the current through the primary of T2 starts
to decrease, the primary voltage reverses polarity to oppose the
changing current. Now pin 6 becomes the more positive side of
wind ing 2-6. The charg ing path is from pin 6, through diode 08
capacitors C2 and CI, and diode 02 back to pin 2 of the winding.
The -~DC voltage is clamped across the primary winding; then the
primary current decays linearly toward zero. When this value is
attained, the pr imary vol tage drops to zero, and the cycle is
repeated.
5-10

As Figure 5-7 indicates, the frequency ef the veltage waveforms is
constant. This frequency is determined by circuit cempenents in
the +5 V control circuit. Hewever, the duty cycle of the veltage
pulses can change to, shew the conditien of the centrolled dc
voltages, (The duty cycle is defined as the ratio' tON/T and has a
maximum value of 50 percent.) Fer example, if the leaa on the +5 V
output increases, the +5 V control circuit causes switching
transisters Ql and Q2 to, stay on for a longer period of time to
make up fer increased voltage drops due to, circuit resistance.
That is, point D and point E in Figure 5-7 move to, the right, as
ind icated by the dashed 1 ines. Then, the aver age val ue ef the
input to, the +5 V regulater increases; this increase forces the
eutput back to its eriginal value.
The increased duty cycle ferces up the +12 Vdc centrolled output,
as well. Because this eutput was at the proper value (we assume),
any increase is false. Therefore, the +12 V centrol circuit causes
Q3 to, switch en later to lower the average value ef the input to
the +12 V regulater. The result ef this en the waveferms in Figure
5-7 is shewn as a detted line.
5.2.2.2 +5 V Control Circuit -- Figure 5-8 shows the +5 V centrel
circuit. The circuit meniters the +5 Vdc contrelled output and, by
turning Q2 en and off, centrels the flew ef current in winding 5-6
ef transfermer Tl.
To, monitor the centrelled voltage, the circuit includes a 3524
integrated circui t (Ie) -- a centrolled pulse-width medulator.
Figure 5-9 shews a bleck diagram ef this IC. When the 3524 is used
in the +5 V centrel circuit, the +5 Vdc controlled eutput is
appl i ed to, one input ef the er rer ampl if i er. The other input of
the error amplifier is cennected to, an internally generated +5 V
reference (pin 16). The error signal developed at pin 9 is applied
to, a cemparater together with an internally ge.nerated sawteoth
waveform (the outputs frem the internal oscillater are set by
external compenents at pins 6 and 7). The comparater eutput is a
pulse whese width depends on the level at which the error signal
slices the sawteeth. This pulse is applied to NOR gates aleng with
the internal escillater eutput and beth sides of the internal
flip-flep. The resulting eutput signals at pins 12 and 13 are used
in beth the +5 V contrel circuit and the +12 V centrel circuit.
These eutput signals from the 3524 Ie are related to, the internal
signals by the waveferms in Figure 5-10. The circuit cempenents
cennected to, pins 6 and 7 result in an oscillator eutput fer a
per ied of 16.5 us. The esc i llator eutput pul ses (the tep 1 ine)
cleck the internal flip-flep, ene eutput ef which is shewn in the
secend line. The third line shews the sawtoeth signal being sliced
by the error signal, which is represented by the herizental selid
line (the dashed line will be explained later); line 4 shows the
resulting cemparater eutput. When the signals shewn en lines 1, 2,
and 4 are NORed, they preduce the output signals shewn cn lines 5
and 6.

5-11

TO +12V
CONTROLCKT

.....

+12 V START-UP

+5VDC

\1
.II

R 27

R22

16~

- - 3
- -4
-

R28

E2
3524

13
12

.----- -

;::;:

I 08
..'

.... ,

... ........

;:;:
\1
.II

I
1
n-6
1

f-+ n - 5

;::~

T2-3

;:;~
~,

':-

......

NOTE:
UNLESS NOTED, LOGIC IS
PIO CONTROL BOARD

OVERCURRENT
DETECT
MR·6558

MA-0189-82

Figure 5-8

+5 V Control Circuit

~_..L.-_ _

+5 V TO ALL
INTERNAL CIRCUITRY

+5V
INV_INPUT 11------1
NON INV_
INPUT

0------,

GROUND
(SUBSTRATE)

~
9 COMPENSAnON
MR-6559
MA-0188-82

Figure 5-9

3524 IC Block Diagram

5-12

I-- 16.5J.Ls --I
E2.3---1l

n~_---Jn~_......an~_--,nL-_---,n~

INTERNAL F/F
OUTPUT, 1 SID~
E2-7 (RAMP)
E2·9(ERROR)

- - - 6 - - - - 6 - --- -~- - - A

--~- -

- 6--- -,L

\7' \ 7 ' \ 7 \ 7 \ 7 \7

COMPARATOR
OUTPUT
I

__ J

E2-1_3___

- - - - - U__ j

.T"""!

V1-2(T3)

--1
MR·6560
MA·0193-82

Figure 5-10

Timing, +5 V Control Circuit

The output from pin 12 of Zl is used in the +12 V control circuit.
The output from pin 13 is applied to transistor pair Q3/Q4 in the
+5 V control circuit. When pin 13 goes low, Q4 is turned on and Q3
is turned off. Q2 turns off and the current that had been moving
in transformer Tl begins to decrease. The counter-EMF induced in
the windings of Tl forward-biases switches Ql and Q2 in the ac
input circuit. Then, Ql and Q2 switch on and E
is applied to the
primary of power transformer T2, as shown by t e signal of line 7.
When pin 13 of E2 goes high, Q3 is turned on and Q4 is turned off.
Therefore, Q2 conducts and steady current again moves through Tl.
Swi tches Ql and Q2 in the ac input circui t turn off, and the
primary voltage of T2 reverses polarity. When the primary current
of T2 has decayed to zero, the vol tage returns to zero and the
cycle is repeated.

The dashed lines show what occurs, for example, when the +5 Vdc
controlled output tends to decrease. The error signal in the 3524
IC increases, narrowing the output of the IC's comparator. As a
result, switches Ql and Q2 in the ac input conduct for a longer
period of time. The increased duty cycle of the voltages across
the windings of T2 counteracts the threatened decrease of the +5
Vdc controlled output.
Both regulator circuits are equipped with overcurrent detectors.
When such a condition results in either regulator, pin 9 of Zl is
taken near ground and the comparator output pulse width reaches a
maximum. Then, the duty cycle of the power transformer voltages is
lowered to a minimum.
5-13

5.2.2.3 +12 V Control Circuit -- The +12 V control circuit is
represented in Figure 5-11. The circuit monitors the +12 Vdc
controlled output and, by turning Q1 on and off, control s the
movement of current in winding 5-6 of transformer T3. The control
circuit includes an operational amplifier, E1, and an NE555 timer,
E3.
A simpl e biock d iag r am of the timer is shown in Fig ure 5-12 (Q5
and C13 are part of the +12 V control circuit). A trigger pulse
applied to comparator B causes both the output phase to generate a
gate and the internal transistor to turn off. The external
capacitor, C13, starts to charge at a rate determined by the
amount of current provided by Q5. When the charge voltage on C13
reaches the threshold level started by the control input (pin 5),
comparator A causes both the output phase to terminate the gate
and the internal transistor to turn on. C13 discharges through the
internal transistor to ground, and the cycle repeats when the next
trigger pulse is applied.
The dashed lines in Figure 5-13 represents what occurs, for
example, when the +12 Vdc controlled output decreases. The output
of the operational amplifier in the control circuit increases.
Therefore, Q5 supplies a larger amount of current to C13, which
charges at a more rapid rate. Transistor Q1 turns on earlier to
increase the duty cycle of the secondary voltage of T2 and,
thereby, to aid the slight decrease in the output voltage.
5.2.2.4 +12 V/+5 V Regulators -- The +12 V regulator is shown in
Figure 5-14. The circuit includes a switching regulator, an
o v e r cur r en t sen so r, and a nove r vol tag e de t e c tor • Th e rna i n
components of the switching regulator are diode D11, choke coil
L3, and filter capacitor C5. When Q3 is turned on by the +12 V
control circuit, the voltage at the secondary of T2 is applied
across DI1, at the input of the LC filter. The constant voltage
across L3 results in a linear current buildup, which is absorbed
by the output capacitance. Therefore, the +12 Vdc output tends to
r i s e. Wh e nth e + 1 2 V con t r 0 1 c i r cui t t urn s 0 f f Q3 , the vol tag e
across L3 reverses polarity, and L3 discharges through D11 into C5
and the load. The +12 Vdc output decreases until Q3 is turned on
aga in. Thi s cycle repeats, wi th the per iod either incr easing or
decreasing, depending on the level of the controlled output;
therefore, the output is a ripple centered at the +12 V level.
Overcurrent sens ing is accompl i shed by compar ator E1. When the
current drawn from the supply reaches 7 A, the voltage at the
inverting input of E1 predominates and the output of El goes to
ground. This ground is applied to the +5 V control circuit,
causing it to decrease the duty cycle of the power transformer
vo 1 tag e s t 0 ami n i murn • Th en, the 0 u t put vol tag e i s dec rea sed to
make sure the current is kept below 7 A. When the overload
condition is removed, typical regulator operation continues.

5-14

+12 VDC

D15

~------~~~------~----------~------~--;d

+12 V START-UP
D5

~-----....L..y----r------""---'\Mr------'-- n6
8

......-I_----r---4-_

7E3
21---+--+----1
NE555

fl To-I

T3sIJ·
I

P/OMASTER

3~-+----4----~1--"T'""""'NY----'--IM---..,.---I~

LB~~ _ .J

+5V
(FROM E2-16, +5 V
CONTROL CKT)
(FROM E2-12,+5V
CONTROL CKT)
NOTE:
UNLESS NOTED, LOGIC IS
PART OF CONTROL BOARD
MR-6562
MA-OI97-82

Figur e 5-11

+12 V Control Circuit

5-15

Vee
8

~E;;

- - - - - - - - -,

I 5
1-r..J.-------I~ CONTROL (+5 V)

2
""'---0 TRIGGER

t---------r---O RESET

I
I

___ ...1
3
OUTPUT

MR-6564
MA-0196-82

Figure 5-12

Block Diagram, NE555

LJ
E3- 2

E3-5
(+5 V) -~----_-_--------~I11'"--------~----------::oo!:""r---

E3-6,7~
E3-3

---.J

I_~~_~L
;L.....I _ _---'

!L• ..LI_ _ _---'

V1-2
(T3)

V3-4
(T3)

~~~~R _ _ _ _ _ _ _~f~.r_l~________ufr_l~______.u:~
MR6561
MA-0191-82

Figure 5-13

Timing, +12 V Control Circuit

5-16

TO
J4-7
+12 V START-UP

Jr--~

r--T-rI"l"'W1r---------r---r----r-----r----y--+-L-,--rvv'ot')--+ +12 (a}5 A

TO J2-8

L...-....L.----------'---'-.......L...-----'---'---'--_ _ _-+--'--f-...L.---L-_ _-+-+-...I...-.L-...J'--...I...-1-+ TO J2-6

TO J4-8

L1,
L4

C16, R18
R30,
020

MA-0192-82

Figure 5-14

+12 V Regulator

Overvo 1 tage protect ion is prov ided by the c i rcui try center ed on
020, Q5, Q6, and 024. If the output voltage approaches 14 Vdc,
Zener diode 020 conducts, turning on unijunction transistor Q5. Q5
provides gate current for SCR Q6, which triggers on. A near-ground
voltage is applied through 024 to pin 6 of transformer T1 in the
ac input circuit. Hence, the transistor switches in the ac input
circuit are turned off, and the voltage on the power transformer
goes to zero. Normal operation resumes only when the overvoltage
condition is corrected and the power is switched off.
The +5 V regulator is shown in Figure 5-15. Like the +12 V
regulator, this circuit includes a switching regulator, an
overcurrent sensor, and an overvol tage detector. Each of these
works exactly as its equal in the +12 V regulator, except that the
voltage and current limits are different; i.e., the overcurrent
starts to operate before 48 A and the overvoltage circuit starts
to operate at 5.7 V. Also present in the +5 V regulator is the -12
Vdc generator, which is, basically, diode 017 and Zener diode 023.

5.2.2.5 POR/DCOR Circuits -- The power monitor circuits control
two signals, BPOK Hand BOCOK H. These signals are asserted when
the power is turned on or off, or when a power failure occurs.
They cause the CPU to carry out specific power-up and power-down
operations. Figure 5-16 shows the bus timing specification that
BOCOK Hand BPOK H must meet; these minimum timing requi rements
are met by the circuits shown in Figure 5-17.

5-17

+12 VOC
L1
r-~~__~r--Jrn~__r -________'-.--'~-r

__~+5VOC
@36A

018

IoVERCURRENTI

I DETECT

I CKT
I (SEE +12 V

• 5
021

C21
C23

I
I

REG FOR
CKT)

L.......II-------'---I

~r--I----+--~--L.. +5V GNO
TO +12 VOC
CROW BAR

~_~YY-"""""'T--r---12 VOC

033

MR-6566

MA-0187-82

Figure 5-15

+5 V Regulator

/4MS (MIN)
70 MS
I--(MIN)--I
3 MS(MIN)--I

I--

4 MS (MIN),

I I

I
I
SS
,.-----~--\r_-______\
I

ACINPUT

I
I
I

OCOUTPUT

II :I

:L
I

I
I

--'r

BPOK H _____________
L

-I 1- 5115 (MIN)

I I

BOCOK H

tAl

t
L_ POWER-OOWN----l

POWE R-UP .-..1
SEQUENCE ----.

r- SEQUENCE

-I
MR-6567

MA-019Q.82

Figure 5-16

Power-Up/power-Down Timing

5-18

+12 V
-12 V ...I\A_-'--L.~

~--4----'5

(Pl·L)
, -__- - 8 POK H

~~-~~--+-4--~6 E2 3~t--;~~~R~25~_ _ _ _ _ _+-_____~
7

NE555

-12V

Pl·J

(Pl·N)
B DCOK H

R23
C5

Cll

-12 V

Figure 5-17

POK/DCOK Circuits

The POK circuit and the DCOK circuit work the same way during a
power-up sequence. Figure 5-18 presents the timing of significant
signals in the DCOK circuit during such a sequence. The signal at
P1-J is from the secondary of power transformer T3 in the ac input
c ire u it. Wh e nth e des tar t - ups up ply vol tag e s h a v e a t t a in e d a
level that is enough to operate the logic, the signal at P1-J is
compared to a reference level by voltage comparator EIA. The
output of E1A, pin 1, is high when the reference level at the
noninverting input is higher than the signal level at the
inverting input. When the signal at E1-1goes high, capacitor C5
charges; when the signal goes low, C5 discharges through R15 to
ground. If the peak vol tage of the signal at Pl-J often rises
above 14. 5 V, E1-l goes low occasionally; therefore, C5 charges
and discharges repeatedly.
After. the circuit starts to operate, the first negative change at
E1-1 triggers the timer, E3, and pin 3 goes high. As long as the
voltage at pin 6 of the timer stays below the threshold at pin 5,
pin 3 stays high. The timer output is applied to comparator E4C,
the leading edge of the output being integrated by R23 and CII.
Wh e n E3 - 3 g 0 e s h i g h , the 0 u t put atE 4 -1 3 a 1 so go e s h i g h ;
therefore, D4 is turned off and 0 V are applied to the gate (G) of
Q2, a field-effect transistor (FET). Q2 conducts, holding the
BDCOK H signal near ground level.

P1-J

E1-1

E3-5
(THRESHOLD)

----------------------'.~ ~~----

E3-6

E3-3

I,....---------------------I,~ \

E4-10

=-:::=-=:...----,-------~'J',

E4-13

~~--~------_4~\-----

BDCOKH~I_ _ _ _ _ _ _ _ _ _~~------------~~~~----..
1.. - - - - 3 M S (MIN)----+l_1
MR·6569
MA-0198-82

Figure 5-18

DCOK Power-Up Timing

5-20

When the signal at E4-13 starts to drop, 04 conducts and a
negative voltage is applied to the gate of Q2; ultimately, this
voltage becomes negative enough to turn off Q2. At this time BOCOK
H is asserted. The time constant of R23/Cll is such that at least
30 ms elapse from the time dc voltages become active to the time
that BOCOK H is asserted.
The same type of circuit causes the BPOR H signal to be asserted
during the power-up sequence.
However, the time constant of
R25/C12 at the output of timer E2 is such that at least 100 ms
elapse from the time BOCOK H goes high to the time that BPOK H
does so. In addition, the POK circuit makes up circuit components
that have no counterparts in the OCOK circuit. These components
include equals E4A and E4B, which set the circuit timing during a
power-down sequence.
Figure 5-19 shows the relationship of significant signals in the
POK/OCOK circuits during a power-down sequence. This sequence is
started when the ac input at PI-J (Figure 5-17) drops below a
predetermined minimum. If the input signal decreases greatly (to
below 14.5 V), both the POK circuit and DCOK circuit cause their
respective inputs to be asserted. However, the input can decrease
just enough to cause only the POK circuit to be turned off (to
below approximately 17 V). In this instance, the POK circuit
forces the BOOK H signal to go low; so, the result is as if the
OCOK circuit had been turned off.
Figure 5-19 shows this condition. That is, the input signal, PI-J,
has decreased so that the inverting input of comparator EIB does
not rise above the reference level at the noninverting input.
Then, the output of EIB fails to go low to discharge capacitor C6
before the threshold level is reached. However, the voltage
divider at the inverting input of EIA (R5/R6) differs from its
equal at EIB (R7/R8). The voltage at the inverting input of EIA is
still enough (in thi s exampl e) to cause the output of E lA to go
low occasionally; therefore, capacitor C5 is repeatedly discharged
before reaching the threshold level.
When the voltage at pin 6 of timer E2 reaches the threshold level,
the 0 u t pu t 0 f E2 (p i n 3) go e s I ow • Th e 0 u t pu t 0 f co mpa rat 0 r E 4 0
goes high, closing off 05 and causing Q3 to conduct; thus, the
BPOK H signal is negated. Now the POK circuit uses comparators E4A
and E4B to force the BOCOK H signal low. The output of timer E2 is
applied through the comparators to the reset input (pin 4) of each
timer, E2 and E3. This causes the output of E3 to go low and holds
both timer outputs low regardless of what occurs at the timer
inputs. When E3-3 goes low, the output of E4C goes high, closing
off 04, Q2 turns on, negating the BOCOK H signal.
If the input signal, PI-J, experiences only a momentary fault, as
shown in Figure 5-19, the power-up sequence starts automatically
when the timer reset inputs are allowed to go high. The BOCOK H
signal is asserted 30 ms after E3-3 goes high, while the BPOK H
signal is canceled some 100 ms later.

5-21

r-f1r1l

Pl-J

El-14

fLrLJ

U u u u

E2-6

-----""j ~

E3-5

----------------------------------~(~f--------

E3-6

E2-5

~--------~~------~r-

E2-3

E4-2

E2-4
E3-4

""--______~ \-{-_----II

E3-3

B POK H

B DCOK H

~--------4~ ~(-------

----------------------------4S~\--~L-~1·--------8MS------~·1
MR·6570

MA·0203-82

Figure 5-19

Power-Down Timing

5-22

5.2.2.6 LTC Generator
Figure 5-20 shows the circuit that
generates the LTC signal. The 12.6 Vac output of transformer Tl is
applied to both inputs of comparator El. The waveforms represent
how the comparator output controls transistor Ql to generate LTC.
5.2.3
H9276 Backplane
The BAll-Y backplane is a 9 X 4 backplane that accepts both
double-height and quad-height modules. The backplane structure is
unique, providing two sep'arate buses, the extended LSI-II bus and
the CD bus. These two buses are shown in Figure 5-21, which also
shows the backplane and points out the power and signal connectors
(Jl--J3). Modules are inserted in slots 1 through 9 of the
backplane. The extended LSI-II bus signals appear on rows A and B;
the CD bus signals appear on rows C and D.
The paragraphs that follow include information that
when designing modules for the two buses.

r-:: - -

I PIS MASTER so I

12.6VAC

is necessary

+12 V START-UP

I ~4 I
I!
II'---..,;I~-+--+---,~~
I

L __ ..J

12.6VAC-~E1,+INPUT

E1,-INPUT

LTC

nJL.J
MR-6563

MA-0199-82

Figure 5-20

LTC Generator

5-23

EXTENDED LSI-ll BUS ROWS

CD-BUS ROWS

~----~k~----__~V~

ROWA
SIDE 1

SLOT 1

______~A~____~\

ROWB

ROWC

ROWD

6--~

6 --~
W3

21Gt 1

J1
11(1
I2", I
13G
4'"
... 1
150

I<X)

IGOI
{Xii

10 {iG9
L..J

r .,
IGla
1015
1014
1(113
1(11 2

Ila"... 1
7"... 1

ISG
L._

1~/11
.... ..J

...

~- I\~-

SLOT 9

\ A1

NOTE:
VIEW IS FROM MODULE
SIDE OF CONNECTORS

\V2

MR-6571

MA-020D-82

Figure 5-21

H9276 Backplane

5.2.3.1 Extended LSI-II Bus Signals -- The extended LSI-II bus
signals in the H9276 backplane are provided by rows A and B. Most
of these signals are bused to the same pin in all nine slots of
the backplane. Certain defined spare pins are not bused. Al so,
interrupt acknowledge and bus grant signals (BIAKD
L, BIAKI L,
BDMGO L, amd BDMGI L) are not bused, being connected, instead, as
shown in Figure 5-22. The inte r r upt acknowl edge and bus grant
signals are passed from module to' module by etch jumpers that
connect pin M2 to pin N2 and pin R2 to pin S2 on connector A of
the module. Therefore, there can be no empty module posi tions
between the CPU (which occupies slot 1) and an I/O device option
that uses these signals.
If the extended LSI-II bus is to be continued to a second
backplane, an M9404 connector module is inserted into connectors A
and B of the last usable slot in the first backplane, while an
M9405 connector module is inserted into slot I (rows A and B) of
the second backplane (refer to Paragraph 2.13.2 and Appendix C for
details). A pair of BC02D-05 cables are used with these modules to
connect one H9276 backplane to another.
Table 5-1 lists the extended LSI-II bus signals and the assigned
pin numbers.
5-24

ROWA
SLOT 1

eM2

eR2

SLOT 2

SLOT8

SLOT 9

I
I

I
I
I
I

PIN M2: BIAKI L
PIN N2: BIAKO L
PIN R2: BDMGI L
PIN S2: BDMGO L

MR-6572
MA-0206-82

Figure 5-22

Table 5-1
Slot, Side

Interrupt Acknowledge and Bus Grant Signal
Interconnection, H9276 Backplane

Extended LSI-II Bus Signal Pin Assignments
Al

BIRQ 5 L*
BIRQ 6 L*
BDAL 16 L
BDAL 17 L
SSPARE 1+
SSPARE 2
SSPARE 3
GND
MSPARE A
MSPARE A
GND
BDMR L
BHALT L
BREF L
+12 B
GND
PSPARE 1
+5B

+5
-12
GND
+12
BDOUT L
BRPLY L
BDIN L
BSYNC L
BWTBT L
BIRQ L
BIAKI L
BIAKO L
BBS7 L
BDMGI L
BDMGO L
BINIT L
BDAL0 L
BDALl L

BDCOK H
BPOK H
BDAL 18 L*
BDAL 19 L*
BDAL 20 L*
BDAL 21 L*
SSPARE 8
GND
M SPARE B
M SPARE B
GND
BSACK L
BSPARE 5
BEVENT L
+12 B
GND
P SPARE 2
+5

+5
-12
GND
+12
BDAL 2 L
BDAL 3 L
BDAL 4 L
BDAL 5 L
BDAL 6 L
BDAL 7 L
BDAL 8 L
BDAL 9 L
BDAL 10 L
BDAL 11 L
BDAL 12 L
BDAL 13 L
BDAL 14 L
BDAL 15 L

Pin
A
B
C
D
E
F
H
J

K
L
M
N
P
R
S
T

U
V

* Extended LSI-II bus pins.

+ Some memory module types may require +5 VB to be jumpered from

connector pins AV1 to AE1 on the extended LSI-II bus rows A and
B slots (2 through 9 only) for that module.
5-25

5.2.3.2 CD Bus Signals -- Rows C and D supply the CD bus signals.
Figure 5-23 shows the connections to the CD bus. Clearly, only
five of the nine slots are pictured. The +5 V supply is bused to
all slots on pin A2 of rows C and D (i. e., pins CA2 and DA2).
Also, ground connections on pins CC2, CTl, DC2, and DTI are bused
to all slots. All other pins connect only to an adjacent slot. For
example, pin CF2 of any slot connects only to pin CFl of the
adjacent higher numbered slot. Pins on side 2 of the row (B2, C2,
etc.) connect at the adjacent higher numbered slot (except DT2,
which connects to CT2 of the adjacent lower numbered slot), while
pins on side 1 of the row (Bl, Cl, etc.) connect to the adjacent
lower numbered slot (except pin AI, which connects to Cl of the
adjacent higher numbered slot). Then, each slot, except 1. and 9,
has 33 signal connections (i.e., connections other than +5 V and
ground) to both the adjacent higher numbered slot and the adjacent
lower numbered slot. To help reference to these two groups of 33
signals, group I is defined as making up the signals connecting a
s lot ( s lot X) to its ad j ace n t lowe r n urn b ere d s lot ( s lot X-I),
while group 2 is defined as making up the signals connecting a
slot to its adj acen t higher numbered slot (slot X+l). Th i s group
distinction is maintained in Table 5-2, which lists row C and D
pins for slot X and assigns signal names to each pin. Generally,
group 1 signals are found on side 1 pins, while group 2 signals
are found on side 2 pins.
1.

NOTES
Bus pins are called out as AKI, ASI,
BC2, etc. A callout such as ASI, for
example, means row A, pin S, side 1.

The following spare pins are not
bused: S SPARE 1
S SPARE 8; M
SPARE A
and M SPARE B (in each
slot, AKI is connected to ALI and
BKI is connected to BLI); P SPARE 1
and P SPARE 2. The following signals
are not bused: BIAKI L, BIAKO L,
BDMGI L, and BDMGO L.

If a CPU is installed in slot 1, pin
AFI of slot 1 (formerly a spare)
becomes S RUN L.

Descriptions of these signals can
Microcomputer Processor Handbook.

found

the

1979--1980

WI, W2, and W3 backpl ane j umpe rs are removed when the BAll-Y
mounting box is used as an expander box (without a CPU module).
Otherwise, these jumpers short to.gether pins in the first
backplane slot COIKI to COlLI and DOIKI to DOlLI, respectively.

5-26

Rowe
+5 V

GND

ROWD
GND

SLOT

U1
I
(IV

-....J

NOTE:
WITH SOME PROCESSORS, W2 AND W3 INSTALLED ENABLE THE CPU TO OPERATE
IN SLOT 1. I F THE BACKPLANE IS BEING USED AS AN EXTENDED BUS REMOVE
THE JUMPERS (THE CPU MUST BE PLACED IN SLOT 1 OF THE MAIN BOX ONLY).
IN THE DYS50, JUMPERS W2 AND W3 HAVE NO FUNCTION. THEY ARE NOT CONNECTED
TO ANYTHING.

Figure 5-23

CD Bus Interconnections

+5V

CD Bus Signal Pin Assignments

Table 5-2
Row

Side 1

Side 2

INTCON 1, Group 2
INTCON 2, Group 1
INTCON 2, Group 1
INTCON 3, Group 1
INTCON 4, Group 1
INTCON 5, Group 1
INTCON 6, Group 1
INTCON 7, Group 1
INTCON 8, Group 1
INTCON 9, Grol;lp 1
INTCON 10, Group 1
INTCON 11, Group 1
INTCON 12, Group 1
INTCON 13, Group 1
INTCON 14, Group 1
GND
INTCON 15, Group 1
INTCON 16, Group 1

+5 V
INTCON 2, Group 2
GND
INTCON 3, Group 2
INTCON 4, Group 2
INTCON 5, Group 2
INTCON 6, Group 2
INTCON 7, Group 2
INTCON 8, Group 2
INTCON 9, Gr:oup 2
INTCON 10, Group 2
INTCON 11, Group 2
INTCON 12, Group 2
INTCON 13, Group 2
INTCON 14, Group 2
INTCON 33, Group 2
INTCON 15, Group 2
INTCON 16, Group 2

INTCON 1 7,
INTCON 18,
INTCON 17,
INTCON 19,
INTCON 20,
INTCON 21,
INTCON 22,
INTCON 23,
INTCON 24,
INTCON 25,
INTCON 26,
INTCON 27,
INTCON 28,
INTCON 29,
INTCON 30,
GND
INTCON 31,
INTCON 32,

+5 V
INTCON 18,
GND
INTCON 19,
INTCON 20,
INTCON 21,
INTCON 22,
INTCON 23,
INTCON 24,
INTCON 25,
INTCON 26,
INTCON 27,
INTCON 28,
INTCON 29,
INTCON 30,
INTCON 33,
INTCON 31,
INTCON 32,

C
D
E

F
H
J
K
L
M

N
p

R
S

T
U

A
B
C

D
E

F
H
J
K
L
M

N
p

R
S

T
U

Group 2
Group 1
Group 1
Group 1
Group 1
Group 1
Group 1
Group 1
Group 1
Group 1
Group 1
Group 1
Group 1
Group 1
Group 1
Group 1
Group 1

5-28

Group 2
Group 2
Group 2
Group 2
Group 2
Group 2
Group 2
Group 2
Group 2
Group 2
Group 2
Group 2
Group 2
Group 1
Group 2
Group 2

5.2.3.3 Module Requirements for H9276 Capability -- Modules used
in the BAII-Y box are of two classes: those that function with
18-bit addressing and those that function with 22-bit addressing.
A double-height module that has been designed for 18-bit
addressing capability can be used with both the KOFII-A and the
KDFII-B processor modules. Such a system is limited to 256 Kb of
memory; however, both the KDFII-A Rev C and later and the KDFl1-B
function use a 22-bi t addressing system. A double-height module
designed for the CD bus can only be inserted into the H9276
backplane CD bus rows. Table 5-3 lists the compatible CD bus
signals.
Quad modules designed to be used wi th an H9273 backplane, are
compatible wi th the H9276 backplane as long as they do not use
BDAL 18--21 for another reason. Both backplanes have etch jumpers
connecting pin M2 to pin N2 and from pin R2 to pin S2 on the
module connector A only. Also, these jumpers permit passage of the
BlAK and BDMG signals.
Figure 5-24 shows a portion of each backplane to show the
differences between the wiring of pins M, N, Rand S in rows A and
C of both the H9273 and H9276 backplanes.
Table 5-3

CD Bus Signals for H9276 Compatible Quad Modules

CD Bus Signal

Pin Number

+5 V
GND
lNTCON 4, Group 1
lNTCON 5, Group 1
lNTCON 6, Group 1
lNTCON 10, Group 2
lNTCON 11, Group 2
lNTCON 13, Group 2
lNTCON 14, Group 2
lNTCON 17, Group 1
lNTCON 19, Group 1
lNTCON 20, Group 1
lNTCON 21, Group 1
lNTCON 22, Group 1

CA2, OA2
CT1, CC2, DTI, DC2
CEI
CFl
CHI
CM2*
CN2*
CR2*
CS2*
DCl
DOl
DEI
DFI
OHI

* Etch jumpers between CM2 and CN2, CR2 and CS2, respectively,
must be placed on modules used in an H9270 backplane to allow
passage of the BlAK and BDMG signals.

5-29

SLOTS

ROW A

ROWS

Rowe

ROWD

{

X+1

)

X+2

H9276

MR·6573
MA·0212·82

Figure 5-24

H9276 Backplane Wiring

(Rows A and C)

5.2.3.4 Modules Designed for the H9276 Backplane Only -- Modules
can be used in the H9276 backplane either singly or in sets. The
single, or standalone, module communicates with other modules only
through the extended LSI-II bus. A double-height, standalone
module is inserted into extended LSI-II rows A and B. A
quad-height, standalone module can use the group I INTCON signals
but cannot use the group 2 signals.*
A modul e set is made up of more than one modul e. The modul e
occupying the highest numbered slot of the set must not use the
group 2 INTCON signals. All other modules of the set can use both
the group 1 and group 2 INTCON signals. The module in the lowest
number ed slot can use the group I signal s as test po ints; * its
group 2 signals communicate wi th the second module of the set.
Each module after the first communicates with its neighbors with
both the group 1 and group 2 signals except, of course, the last
module of the set, which does not use the group 2 signals.
A bus can be created for each module set by connecting group 1
pins to group 2 pins on each center module. For example, if you
have a four-module set, you can create an INTCON 4 bus by
connecting pin CEI to pin CE2 on both the second and third modules
of the set.
Module sets can be expanded at any time. However, the set can be
expanded upward, only. That is, if a module is added to an
existing set, it must occupy the lowest numbered slot of the new
set.

* A standalone module might have INTCON 10, group 1, shorted to
INTCON 11, group 1, and INTCON 13, group 1, shorted to INTCON
14, group 1. Refer to Paragraph 5.2.3.3 for an explanation.

5-30

5.2.3.5 Electrical Protection for Quad-Height and Double-Height
Module -- Use only quad-height modules that have extractor-type
handles in the 89276 backplane. (The extractor-type handle is
shown in Figure 3-4). These handles help you to insert and extract
the module. More importantly, the card frame of the BAII-Y is
designed so that these handles prevent a module from being
inserted upside down. If a quad module having plastic U-shaped
handles must be used, confirm that the module is inserted
correctly; i.e., the component side of the mod~le must be on top.
Double modules have only plastic U-shaped handles. These modules
can be inserted in backplane rows A and B or C and D, depending on
whether they are designed to use the extended LSI-II bus or the CD
bus, in order. Obviously, it is possible to insert these modules
not only backwards but also in the wrong bus. Therefore,
electrical protection must be included in the design of double
modules; i.e., the assignment of supply voltages to connector pins
must be done so that if a module is incorrectly inserted in the
backplane, supply voltage will not be applied to signal pins.
Electrical protection for extended LSI-II bus double modules is
afforded by the design of the 89276 backplane. A double module
designed to be inserted in the extended LSI-II rows (A and 8) can
be inserted upside down with no damage to power supply voltages.
That is, d module pin that is supposed to receive +12 Vdc, gets
+12 Vdc whether the module is right-side up 0 r ups ide down. The
same protection is afforded if the module is inserted in the CD
bus, rig h t - sid e up 0 r ups ide down. 0 f co u r s e , a n i nco r r e c t I Y
inserted module will not work correctly. If the system fails to
operate (either totally or in a specific area)
after module
installation or replacement, be sure that all modules are inserted
correctly in the backplane before trying other troubleshooting
methods.
Unfortunately, the backplane cannot provide protection for modules
des igned to use the CD bus. Therefore, the protection must be
designed into the module itself. The pins listed in Table 5-4 are
those that must be protected from incorrect placement of the CD
bus module (the double-module connectors are labeled A and 8 even
though they are inserted in CD bus rows C and D, in order). For
example, a module designed for the CD bus receives +5 Vdc from
backplane pins CA2 and DA2, and no other voltage. If the module
was inserted in the extended LSI-II bus (A and B), it would
receive +5 Vdc, -12 Vdc and +12 Vdc on the pins listed in Table
5-4.

5-31

Table 5-4

Vulnerable CD Bus Double Module Connector Pins

Module Pin

voltage to Which Pin
Might Be Exposed

AV1, BVl, AEl*
AB2, AU1, BB2, BU1
AD2, A8l, BD2, BSI

+5 V, +5 VB
-12 V
+12 V, +12 VB

5.2.4
Front Bezel Assembly
Figure 5-25 represents the log ic 1 inked wi th the front panel
·swi tches and indica tors. (Par agraph 2.4 tell s how to use the
switches and how to interpret the indicators.) The logic
components are mounted on a printed circuit board that is attached
to the rear of the front panel. A signal cable that plugs into Jl
of the printed circuit board carries the signals between the front
panel and the power supply master board. J2 is cabled to the
remote switch connector on the front panel.
Indicator lights Dl and D2 light when the power supply is
operating correctly and when the CPU is running. D1, the PWR OK
indicator, lights when the B POK H signal from the power supply is
asserted. D2, the RUN indicator, lights as long as the CPU
generates the signal 8 RUN L. This signal is appl ied to the
positive trigger input of retriggerable one-shot multivibrator
E3A. The basic pulse width of E3A is greater than the period (t)
of 8 RUN L (Figure 5-26); therefore, E3A is continually
retriggered by S RUN L and stays on until 8 RUN L is negated. The
1 output of E3A causes the RUN indicator to light (the jumper in
W4 is in place when the CPU is inserted into the backplane).
In meeting its more obvious function, switch 82 grounds the B HALT
L signal when it is moved to the HALT position (down). Then, the
CPU can be forced to halt typical program execution from the front
panel of either the main box or an expander box. To continue
operation after using the HALT switch, return the HALT switch to
the enable position (up) and enter a P command from the console
term ina I • ( Re fer to Ch apt e r 4 0 f the 1 979 -1 98 0 M i c roc 0 mput e r
Processor Handbook for a description of console ODT command
usage. )
Not only can you halt the CPU from the front panel, but you can
also reboot it. When you lift and release the momentary RESTART
switch, 81, the CPU halts and then automatically carries out a
power-up sequence. Figure 5-25 shows swi tch 81 in the typical
operating position (down). When the operator lifts and then
releases SI, allowing it to return to the down position, a
positive-to-negative change is applied to the negative-trigger
input of one-shot multivibrator E3B. This negative change causes
the one-shot to generate a gate of 1 us (minimum) duration; this
gate first negates SDCOK H and then permits it to be reasserted to
complete the reboot operation.
5-32

J2
J1

LTC
S RUN L

2
o

BPOK H

~S3
W2

re1---- ----,

OFF
+5
W1

GND

+5VDC
SPARE

B HALT L
B DCOK H

W
W

1-1J.Ls(MIN)

L
NOTE:
S2 IS SHOWN IN THE OPERATING
POSITION (UP); Sl IS SHOWN IN
THE OPERATING POSITION (DOWN).
MR·6579
MA·0186·82

Figure 5-25

Front Panel Logic

I-t-I
S RUN L~I. . .

_--..J

E3A

BASIC
:-PULSE-:
I
WIDTH
I

MA·6574
MA·0207·82

Figure 5-26

RUN Indicator Waveforms

The third switch shown in Figure 5-25 is the AUX switch, 83. The
switch contacts can be used for any function; however, the
following two mutually exclusive functions are the most common.
One function is to operate as a system on/off switch when a power
controll er is par t of the system; jumper s WI and W2 must be
removed if this feature is to be used. The other function is to
operate as an on/off switch for the power supply generated LTC
signal; jumpers WI and W2 must be installed if this feature is to
be used.
When used as a system on/off switch, 83 is connected to a power
controller by a cable that plugs into connector J2. With 83 in the
ON position, primary power is applied to the power controller and
distributed by it through the system. In the LTC application, 83,
when in the ON position, permits the LTC signal to be used as an
LTC interrupt in the cpu. In the OFF position, 83 grounds the LTC
signal, which is a necessary feature when certain diagnostic
programs are being executed.

5-34

APPENDIX A
DYS50 KERNEL SYSTEM CONFIGURATION

Fig u res A- 1 t h r 0 ug h A- 6 s how the fa c tor y set t i ng s
kernel system jumpers and switches.

CONNECTOR 2

CONNECTOR 1
SLOTA
PROCESSOR
MODULE

SLOT B

for

SLOT D

ROW 1

MEMORY
MODULE
DECdataway
INTERFACE

ROW2
ROW3
ROW4

OPTION 1
(HIGHEST PRIORITY)
OPTION 2

ROW5

OPTION 3

ROW6

OPTION 4

ROW7

OPTION 5
(LOWEST PRIORITY)

ROW8
ROW9
VIEW IS FROM MODULE SIDE OF BACKPLANE
H9276 OPTION POSITIONS

STANDARD FACTORY JUMPER CONFIGURATION

*W1

JUMPER
STATE
IN

W2, W3

OUT

JUMPER

FUNCTION
THE H7861 POWER SUPPLY
GENERATED LTC SIGNAL IS USED
TO ASSERT BEVNT L SIGNAL
THESE JUMPERS HAVE NO EFFECT
ON DYS50 OPERATION

*W1 MUST BE REMOVED FROM ALL EXPANDER BOXES
IN A MULTIPLE-BOX SYSTEM SINCE ONLY
THE BOX CONTAINING THE KDF11-BB (M8189)
MODULE MUST BE THE SOURCE OF THE LTC SIGNAL

Figure A-l

MA-7101B

DYS50 Kernel System Backplane
Configuration

A-I

all DYS 50

SIDE2

0
0
0
o-W'io 0
O---<>CJ-O

c>~_1_0 0

SWITCH CONTACTS
(53.52.51)

IT}

LED CONTACTS
(RUN. PWR OK)

NOTES;
1. VIEW IS FROM THE REAR OF THE BEZEL
WHEN THE BOARD IS MOUNTED ON
THE BEZEL.
2. JUMPERS ARE MOUNTED ON SIDE 2.
FACTORY JUMPER CONFIGURATION

JUMPER

JUMPER
STATE

FUNCTION

W1, W2

OUT

ALLOWS THE AUX ON/OFF SWITCH
TO TURN THE SYSTEM POWER
ON AND OFF

OUT

CPU IS MOUNTED IN THIS
BACKPLANE

ENABLES THE RUN INDICATOR
BECAUSE THE CPU IS MOUNTED
IN THIS BACKPLANE
MA·0737B

Figure A-2

DYS50 Bezel Printed Circuit Board
Factory Configuration

A-2

r------,
J46
oJ40
oJ39
J38
J37
oJ36

I
I
I

J27
J26
oJ25

IL-

J35
J34
oJ33

I
I
I

COMMERCIAL INSTRUCTION
SET (KEF11-BB OPTION)
E78

COMMERCIAL INSTRUCTION

II:

SET

E77

~ (;)~ D2 ~

ll--LSD~

J7
LoJ6

MSDJ

DIAGNOSTIC
DISPLAY

FLOATING POINT
(KEF11-AA OPTION)
E76
oJ32
oJ31
J30
J29
OJ28

C
:J:!I

IT]

SLU 1

DATA AND CONTROL
(CPU)

BAUD
BOOT/
RATE
SELECT (S2) DIAGNOSTIC (S1)
ON
ON OFF
OFF

4
5
SLU 2

CD
CD
C.
o:::J
o:::J
o:::J

E75

c.. IDAL 00
c..
o:::J
c-.

MEMORY MANAGEMENT
(MMU)
E74

CD
o:::J

c..

E114

o:::J

IDAL 07

E102

oJ19
oJ18
o J17
o J16
oJ15
OJ14
OJ13
J12
oJ11

J23

J24

J22
W2

vV1

o-c::J-o o-c::::J-o

[
J10

ro J5

Lo J4
o J3
NOTES:
1. INSTALLED JUMPERS SHOW THE
FACTORY CONFIGURATION.
2. WHEN MASKED ROM S ARE USED
J24 IS CONNECTED TO J23.
J22 IS NOT CONNECTED.
3. WHEN EPROM S ARE USED J22 IS
CONNECTED TO J23. J24 IS
NOT CONNECTED.
4. SWITCHES S1-1,2,4,7, AND
S2-1,5 ARE SHOWN IN
"ON" POSITION.

MA-5448

Figure A-3

Factory Configuration of the KDFII-BB (M8189)
DYS50

in the

MA-0219-82

16K MOS CHIPS
BITS

BITS

~D8[][]8DD8
@][J~[J~[JDD~

Rowa (

ROW 1 (
BYTE

WRITE WRONG
PARITY TESTING
PIN 6 TO 7

BITS
MB067-KA
ROW LATCH
1---;:--~3-'

I
I

r-t--0 4 ,'
I'

~----olOl

011 ,

'----09

43_441
_ _ _ _45
__
...J

-= X °

r - :.-_-: --: 14l
I
:
15
I
I
I
.... -t--0 16 I

voro¥

° 17 I

- oS

I
I

:
:

INHIBIT
,....-------.

r---O

:r-:: n :
IL _
'=' _
21 _23
22..JI
__

oN
oM
o-L

018 I

I
L __ ~~::.J

ROWO[

--1

~
_ _6 _ 7_ _
-_JI

I r~~J
rtl....;L-.;1;;;,;0=T-_ _.,STARTING ADDRESS
~X~...J
JUMPERS

COLUMN LATCH
ROW3 {

[DAL16HnI
L

r---,

18/22 BIT
SYSTEM

L ___ ~~J

ROW2(

1-0-11

iTIM190-H

..r.-oo.E

ROW 1 {

'='

BYTE
ROW 2 {

Fo
POWER JUMPERS
ROW3{

~VDD

POWER JUMPERS
~

16K MULTIPLE VOLTAGE DEVICES
NON-BAT BACK-UP

BAT BACKUP

VOLTAGES

W3
W11
W13

W3
W10
W12

-5
+12 VDO
+5 CR

oC
oB
oA
0 H

CSR ADDRESS JUMPERS

W15 •
W14
o
0
0
W13W12
~

I~~I
~
GRANT CONTINUITY
W1 AND W2 IN FOR
010 MACHINE, 022/022
MACHINE
W1 AND W2 OUT FOR
OICD AND 022/CD MACHINE

POWER JUMPERS FOR 16K MOS CHIPS
WITHOUT BATTERY BACKUP
_

POWER JUMPER IN FOR 64K CHIPS

--c::1- POWER JUMPER IN FOR 16K CHIPS
---=:}- POWER JUMPER IN FOR BOTH 64K/16K CHIPS

64K SINGLE VOLTAGE DEVICES
NON-BAT BACK-UP

BAT BACKUP

VOLTAGES

W4
W5
W9
W13/W15

W4
W5
W12
W14

DECOUPLE +5
DECOUPLE +5
+5 CR
+5 VDD
MA-7148B

Figure A-4

Factory Configuration of the MSVII-P (M8067-KA)

in a DYS50

FACTORY JUMPER CONFIGURATION
IN: W7, W8. W9, Wl0, W17, W18, W19, W20
OUT: ALL OTHERS
JUMPER FUNCTIONS
JUMPER

USE

Wl-W8, W12, W13

LSI-ll BUS ADDRESS

W9-Wl1" W14, W15

VECTOR ADDRESS

W16

HOLD ON B SACK L

W17, W20

DMA TIMERS

W18, W19

CONNECT PINS

W21-W23

RESERVED
MA-71 04

Figure A-5

ISVII-B M8080 Module Standard
Configuration

A-5

FACTORY JUMPER CONFIGURATION
IN: Wl, W3, W5, W7, W9
OUT: ALL OTHERS

JUMPER FUNCTIONS
JUMPER

USE

W7, W8

PROM SELECTION

Wl-W6, W9, Wl0

PROM POWER
MA-7105

Figure A-6

ISVII-B M8084 Module
Standard Configuration

A-6

APPENDIX B
SPECIAL CIRCUITS

B.l
DC003 INTERRUPT CONTROL (Figures B-1, B-2, and B-3)
The interrupt control chip is an 18-pin, 0.762 cm (0.300 in)
center, DIP device. It provides circuits to perform an interrupt
transaction in a computer system that uses a pass-the-pulse
arbitration scheme. The device is used in peripheral interfaces
and has two interrupt channels labeled A and B. The A section is
at a higher priority than the B section. Bus signals use high
impedance input c ircui ts or high dr i ve open collector outputs,
which allow the device to attach directly to the computer system
bus. Maximum current required from the Vcc supply is 140 rnA.
B.2
DC004 I/O ADDRESS DECODER (Figures B-4, B-5, and B-6)
Th e pro to col chi p i s a 2 0 - pin, 0 • 762 cm ( 0 • 30" in) c en t e r, DIP
device. It functions as a register selector, providing signals
necessary to control data flow into and out of up to four word
registers (eight bytes). Bus signals can directly attach to the
device because receivers and drivers are included on the chip. An
RC delay circuit slows the peripheral interface response to data
transfer requests. The circuit is designed so that if tight
tolerance is not required, only an external IK 20 percent resistor
is necessary. External RCs can be added to vary the delay. Maximum
current required from the V
supply is 120 rnA.
cc

B-1

VCC

r--------------------------------------------------------------------------------------------ENAST H

RQSTA H---'--------1f--------,
EN'AOATA H

VECTOR H
VECRQSTB H
BOIN L 3
INITO L
BINIT L
BIAKO L
BIAKI L
BIRQ L
GNO 9

ENA
ENACLK H-----4>C 0
CLR

VCC
RQSTAH
ENAST H
ENAOATAH
ENACLK H

'-------'

ENBCLK H
ENBDATAH
ENBST H
RQSTB H

BIAKI L
BIAKO L

BINIT L
tJj

BIRQ L

BOIN L

ENBST H
VECTOR H
ENBOATA H
ENBCLK H - - - - I >

VECRQSTB H
VCC

RQSTO H _______/--________....J

~--------------------....J~-----------------------~------~------------L------------------INITOL

rC-0t73
MA-5505

Figure 8-1

DC003 Simplified Logic Diagram

BINIT l

~.9.91300 :

~MINI

I
I

INITO L

I
7~5 ~~I-------------------------------------------------------------------I
I
I
I

~
-+I

ENA DATA H
I

I
I

ENA ClK H

MIN~ ~~______________________________r--l~
I

ENA ST H

7-30~

___________________________

RQSTA H

Il1

BIRQ l

15-65-':

.t-.__ F
---+'_r-:....

20 - 90

I
I
I

BDIN L

BIAKI L

35 MIN--+l
I
I
I

VECTOR H

10-45-':

BIAKO l

35 MIN-+!
I

I
I

F-.: rI

10 45
-

12-55--';

b-+: F

12-55

NOTE:
Times are in nanoseconds
11-4150

MA-5503

Figure 8-2

DC003 Interrupt Section Timing Diagram

BINIT L

~1~~ i
1

III

INITO l

7-35

12-50
I
I
I

ENB DATA H
I

I
ENB ClK H

30 MIN-.j

Fl
I

I
I

ENB ST H

7-30~

BIRQ l

~----------------------------------------------------------

15-65~b:-

--J
__~~F20-90

L ___________________________________

RQSTB H

iI
I

ENA DATA H
I

I
I

ENA ClK H

30 MIN-+J

ENA ST H

RQSTA H

BDIN l
1

BIAKI l

35 MIN--':
I

l::J
I
I

I
I

LriJ

VECTOR H _________________________________
'0_-_4_5~!1~

VECRQSTB H

: I
35 MIN ---.:

H :=1

I~~'_0_-4_5
__________'_0_-4_5~1~

10 - 45

I
I

:==1

15-65H

15-65

NOTE:
Times are in nanoseconds
11-4151

MA-5502

Figure B-3

DC003 Interrupt Section Timing Diagram Sections A
and B

B-4

VECTOR H
BDAL2 L
BDAL1 L
BDALO L
BWTBT L
BSYNC L
BOIN L
BRPLY L
BDOUT L
GND

VCC
ENB H
RXCXH
SEL6 L
SEL4 L
SEL2 L
SELO L
OUTHB L
OUTLB L
INWO L

ENB H ~--------t
BSYNC L
03

BOA L2 L - - - - - + - - - - t

02
01

BDALI L - - - - - + - - - - t

SEL 6 L
DECODER
SEL 4 L
SEL 2 L

SEL 0 L

BDALO L ------+---t
~------------OUTHBL

00
LATCH

C Or-----+---r--a

~~__~------------OUTLBL

BWTBT L

r----------RXCX H

BRPLY L
BDOUT L
BOIN L

~-------------------------------------------VECTORH

~__________~~~-------------------------------------------INWO

IC- 0114
MA- 5504

Figure 8-4

DC004 Simplified Logic Diagram

B-S

BDAL (2,1,0) L

~25 MINI25 MIN

BSYNC L

SEL (0,2,4,6) L

BWBT L
I

I
I

BDOUT L

15 MIN.--.l
I

15 MIN.--:I..
t+~C______
~~-------*----~.~
I

I
I

~ T9 b -

OUTHB L
OUTLB L

~ T10

=+J

BDIN L

I ____

T11

~I..::::::::::~-*-------~-~-(~j----------~·:~1_________
I
I

~T12F

INWD L
____________________________
BRPLY L

~I--~

--+lT13bI
I

11~t-= 2.4V

--:

________~I~-JI
I

I..

VECTOR H __________________________.....

* ----~·~I

--1

Rx C x H

T15

--1 t-__________________________
T16 ...

* TIME REQUIRED TO DISCHARGE Rx Cx FROM ANY CONDITION ASSERTED = 150 ns
NOTE:
Times are in nanoseconds
11- 4348
MA-5501

Figure 8-5

DC004 Timing Diagram

B-6

Vee

60n

280.0.

FROM
OUTPUT

FROM )
OUTPUT

I·

5PF

1200PF

LOAD A

LOAD

DIODEFD777

'50pF

LOAD C
11-4349
MA-5499

Figure B-6

DC004 Loading Configurations

DC995 BUS TRANSCEIVER (Figures B-7 and B-8)
Th e 4 - bit t ran s c e i ve r i s a 20 - pin, 0 • 76 2 c m ( 0 • 30 0 in) c en t e r ,
DIP, low-power Schottky device. Its primary use is in peripheral
logic. In addition to the isolation function, the device also
provides a comparison circuit for address selection and a constant
generator, useful for interrupt vector addresses~ The bus I/O port
has high impedance inputs and high dr ive (70 rnA) open collector
outputs to allow direct connection to a computer's data bus. The
peripheral side includes a bidirectional port, with standard TTL
inputs and 20 rnA three-state drivers. Data on this port is the
logical inversion of the data on the bus side.
B.3

Three address jumper inputs are used to compare against three bus
inputs and to generate the signal MATCH. The MATCH output is open
collector, which allows the output of several transceivers to be
wired-ANDed to form a composite address match signal. The address
jumpers can also be put into a third logical state that
disconnects that jumper from the address match, allowing for
"don't care" address bits. In addition to the three address jumper
inputs, a fourth high impedance input line is used to
enable/disable the MATCH output.
Three vector jumper inputs are used to generate a constant that
can be passed to the computer bus. The three inputs directly drive
three of the bus lines, overriding control line action. Two
control signals are decoded to give three operational states:
receive data, transmit data, and disable. Maximum current required
from the V
supply is 100 rnA.
cc

B-7

JA1 L
JA2 L

20
2

18 DATO H

MATCH H 3

BUSO

BUS1

JA1

JA2

BUS3

JA3

REC H

17 DAT1 H

XMIT H

DAT3 H

15 JV2 H

JV3 H

DAT2 H

JV1 H

BUS3 L

MENS L

BUS2 L

BUSO l

GND

BUS1 L

BUS2

Vee

19 JA3 L

DATO

JV1

DAT1

____________________+-________~~~----~~====t-.- JV2

DAT2

JV3

DAT3

MATCH H
MENS

-,---------r,

XMIT

REC

H ~~----------------------------------_L__I

IC-DC005
MA-5498

Figure B-7

DC005 Simplified Logic Diagram

B-8

TRANSMIT DATA TO

BUS

XMIT H

REC H (GROUND)

BUS L-OUTPUT

5 TO 30ns

5 TO 25 ns
H-INPUT - - - - - , - - - - - ;.....

-l

I+-

--l

OAT

5 TO 30ns

----------------------------------------------------I+- 5 TO 25 ns

1___;1-.:...-----,---

RECEIVE DATA FROM BUS (BUS INITIALLY HIGH)
XMIT H (GROUND)

-----------------------------------------------------

REC H

OAT H - OUTPUT

-..j
0 TO 30ns
-I
I+- 0 TO 30ns
H iZ -----.L--_----:-_~I~----------:..-----'I...- - - - HZ
-.j
I+- 8 TO 30 ns

BUS L - I N PUT -----------.---------____'...
1 ______________________--'-_____

RECEIVE DATA FROM BUS (BUS INITIALLY LOW)
XMIT

H '(GROUND)

. . 11

I
-+I

REC H _ _ _ _ _

-+I
OAT H - OUTPUT

Hi Z

j.- 0 TO 30ns

----1

0 TO 30ns
HiZ

!-I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1

-l

j.- 8 TO 30n5

---',;---=------------,---

BUS L - INPUT _ _ _ _--'-_ _ _

VECTOR TRANSFER TO BUS
JV H

I
I
I+-i
~
-------------'---:1__________________________. . 1
-=I

BUS L - OUTPUT

20ns MAX

ADDRESS DECODING
BUS I - INPUT

__________

~x~

-I

- r_ _ _ _ _ _ _ _ __

10 TO 40ns

~~...I-------------~::---=X~---__:_-_+I----I
I-- 5 TO 40ns
...j
j.-l0 TO 40ns

MATCH H _ _ _ _ _ _
MENB L

------------~I

________________________~·~I--~--------

RECEIVE MODE LOGIC DELA'(
XMIT H

REC H

j+- 40 TO 90ns

DAT (3:0) H (OUTPUT)
HZ

----------------------~-

11- 4892
MA-5500

Figure 8-8

DC005 Timing Diagram

B-9

APPENDIX C
PDP-II/23B BACKPLANE AND MODULE CONFIGURATION

e.l
GENERAL
LSI-II systems can be either single or multi-backplane systems. If
yours is a single backplane system (Figure C-I), observe the
following three bus loading rules when configuring it.
e.2
SINGLE-BACKPLANE CONFIGURATION RULES
The following are the rules for single-backplane configuration.
1.

The extended LSI-II bus can support up to 20 ac loads;
i.e., the processor has on-board termination for one end
of the bus; after 20 ac loads, the other end of the bus
must be terminated with 120 ohms.

The terminated bus can support up to 35 ac loads.

The bus can support up to 20 dc loads.

EXTENDED LSI-ll BUS

CoD BUS

H9276 BACKPLANE
B
C

A
1 -

KDFll-B----,r-----~---___.---

2 -MSVll-P--lI-----+-----+--I

3 -ISVll-B (M8080),----'-------=-~"""'--

4 -QUADOPTION---~----~_+_-I

5 - DUAL OPTION - - - I

6 - QUAD O P T I O N - - - - - - L . . - - - - ' - - - + - - -

7 -DUAL O P T I O N - - - -

8 -DUAL O P T I O N - - - - + - - - - t - - - t - - 9 -ISVll-B (M8084)---....L--------L=:Zl:iL...BAll

MAIN BOX

MA-0205-82

Figure e-l

PDP-Il/238 (H9276) Single
Backplane Configuration

C-l

If your system has more than one backplane
observe the following eight rules.

(Figures C-2 and C-3),

C.3
MULTIPLE-BACKPLANE CONFIGURATION RULES
The following are the rules for multiple-backplane configuration.
1.

No more than three backplanes can be connected together.

No backplane can have more than 20 ac loads.

The total number of dc loads cannot be more than 20.

Both ends of the termination line (PDP-11/23B) must be
terminated with 120 ohms; i.e., the first backplane must
have an impedance of 120 ohms and the last backplane must
have a termination of 120 ohms.

The cable connecting the first two backplanes (i.e., the
main box and expander box 1) must be at least 150 cm (5
ft) long.

The cable connecting the backplane of expander box 1 to
the backplane of expander box 2 must be at least 122 cm
(4 ft)
longer or shorter than the cable connecting the
main box and expander box 1. A 305 cm (10 ft) length of
cable is advised for ease of installation.

The combined length of both cables in the three-backplane
system cannot exceed 488 cm (16 ft).

If the cables
characteristic
systems.

are customer-supplied, they must have a
impedance of 120 ohms for the PDP-11/23B

C-2

BAll-YA
H9276 BACKPLANE
1 ---KDF11-BB----+----------2 ---MSV11-P - - - - + - - - - - - - - - - 3 --DUALOPTION--4 --DUAL OPTION--5 --QUAD O P T l O N - - - + - - - - - - - - - - 6 --DUAL OPTION--7 --QUAD O P T I O N - - - + - - - - - - - - - - 8 --DUAL OPTION--9 ---M9404-00---

BC02D-05
(TYPICAL)----"

BAll-YC
H9276 BACKPLANE

10 - - - M 9 4 0 5 - Y A - - 11 --QUAD O P T I O N - - - - f - - - - - - - - - 12 --QUAD O P T I O N - - - - + - - - - - - - - - 1j--ISV11-B (M8080)---+--------J~~::::::;;;;:;;:::::::¥i:::::::;;:,;;;;:::::::~:- 14
15
16
17
18 --ISV11-B (M8084)---+-----...f;;
fIT'1l: :" ': ;:;: ~: : : tr rJ~: =: : <; ;J: : :_ _
NOTES:
1. THE TOTAL DC LOADS OF BOTH BOXES CANNOT EXCEED 20_
2. EACH BC02D CABLE MUST BE AT LEAST 150 CM (5 FT) LONG,
IF CONNECTED FROM THE MAIN BOX TO THE FIRST EXPANSION BOX.
3. EACH BC02D CABLE MUST BE AT LEAST 300 CM (10 FT) LONG,
WHEN CONNECTED BETWEEN THE SECOND AND THIRD EXPANSION BOX.
MR-6594

MA·0201-82

Figure C-2

PDP-ll/23B (H9276) Two
Backplane Configurations

C-3

H9276
1

KDF"-BB

MSV"-P

3 ---OPTIONS
4
BA11-YA
5
MAIN BOX
6
7
8

OPTIONS

M9404-00

BC02D-03
(TYPICA L) ---H9276
10---M9405-00--11
12
13
BA"-YC
EXPANDER
BOX

OPTIONS

15
16

18 - - - M9404-00--BC02D-10
(TYPICAL )--H9276
19---M9405-YA--20

OPTION
~

21--ISV1'-B (M8080)
22
BA"-YC
EXPANDER
BOX

23
24

25
26

rnrJ:)mm

27--ISV1'-B (M8084)

MR-6597

MA-0202-82

Figure C-3

PDP-ll/23B (H9276) Three
Backplane Configurations

C-4

Ba c k pI an e con fig u rat ion fig u res ( Fig u res C-1 t h r 0 ug h C- 3 ) are
provided to help you follow these configuration rules. First, you
must select which backplane configuration is best suited for a
specific application. Use the backplane selector figures to
determine this configuration.
The col umn layout of the backplanes makes it easy to establ ish
interrupt and DMA priorities of the modules; i.e., the closer to
the top of the column a module is placed, the higher the priority
of the module. Furthermore, the column layout easily depicts the
correct placement of cable and termination modules.
To configure an extended LSI-II system, take the following steps.
1.

Select the type of memory (MOS, PROM,
needed for the specific application.

Select the CPU and memory combination most suited for the
application (the PDP-II/23B uses a KDFll-B).

Select added memory,
needed.

Count the total number of module positions.

Count the total number of bus posi tions.

Select a backplane configuration that answers the module
position requirement, the bus position requirement, and
also provides sufficient expansion space.

Enter the option names in the backplane positions of the
selected configuration.

Review the initial backplane configuration to determine
if changes must be made.

If no changes are necessary, move to the appropriate
backplane configuration table (Figures A-I through A-3).
Total the power consumption and the ac and dc loads. If
any of these exceed the limits specified, modify the
module
configuration
or
use
a
new
backplane
configuration.

interface,

C-5

and

combination)

peripheral

options

Digital Eq.• uJpment Corporation. Mayndrd,MAQ1.754
I "