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EK-DRVWA-UG-002

April 1986

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Document:	DRV11-WA General Purpose DMA Interface User's Guide
Order Number:	EK-DRVWA-UG
Revision:	002
Pages:	64
Original Filename:	http://bitsavers.org/pdf/dec/qbus/EK-DRVWA-UG-002_DRV11W_UG.pdf

OCR Text

EK-ORVWA-UG-002

DRV11-WA
General Purpose
DMA Interface
User's Guide

Prepared by
Computer Special Systems

2nd Edition. April 1986

Digital Equipment Corporation 1986
All Rights Reserved

The information in this document is subject to change without notice and should not be
construed as a commitment by Digital Equipment Corporation. Digital Equipment
Corporation assumes no responsibility for any errors that may appear in this document.

Printed in U.S.A.

This document was set on a DIGITAL DEC set Integrated Publishing System.

The following are trademarks of Digital Equipment Corporation:

~DmDDmDTM
DEC
DECmate
DECset
DECsystem-l0
DECSYSTEM-20

DECUS
DECwriter
DIBOL
MASSBUS
PDP

P/OS
Professional
Rainbow

RSTS
RSX
Scholar
ULTRIX
UNIBUS
VAX
VMS
VT
Work Processor

CONTENTS

page
CHAPTER 1

INTRODUCTION

1.1
1.2
1.3

GENERAL DESCRIPTION

CHAPTER 2

INSTAL,LATION

2.1
2.2
2 . 2. 1
2.2.2
2.2. 3
2.2.4
2.3
2.3.1
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.5
2.5. 1
2.5.2

GENERA.L

SPECIFICATIONS

••••.•••••••••••••••••••••.•••••••

RELATED LITERATURE ••..•.••••••••.•..•.••••••••••

1-1
1-4
1-5

•••••••••••••••••••••••••••••••••••••••••

2-1

2-1
2-1
2-1
2-1
2-1
2-2
2-2
2-2
2-2
2-5
2-5
2-6
2-6
2-7
2-8
2-8

2.6
2.7
2.8
2 .8. 1
2.8.1.1
2.8.1.2
2.8.1.3

SYSTEM 'CONSIDERATIONS .••..•••.•••••••.•....•....
LSI-II Bus Loading............................
Power Requirements ••.•••••.••••••.••••..•.•.••
priority Requirements .•.•••••••.•••••••.••...•
Space Requirements ••.••••••••••••.•.••.•..••.•
USER I/O CABLES •.•••••••.••••••.•••••.....•.•.••
User Termination Connector •••••••.••••••.•••••
JUMPER. AND SWITCH CONFIGURATION.................
Device Address Selection .•.•••••.••••.••••••.•
Interrupt vector Address Selection •.•.•.....••
Addressing Mode Selection .••••••.•••••••••••..
Burst Mode Jumper ..•..•....•.••••...•••.••••.•
Interprocessor Link Mode Jumper ••.•••.••••••••
Independent Interrupts Jumper ....•.••.........
MODULE INSTALLATION •.••..••••..••.•.•.•..•••.•.•
Inst q l1ing the DRVll-WA in an LSI-II CPU ....••
Installing the DRVll-WA in the BA23
Enclosure (MICRO-ll/MicroVAX) .••...••.....•...
Installing the DRVll-WA in the BA123
Enclosure (MICRO-11/MicroVAX) . . . . . . . • . . • . . . . . .
INITIA,L TURN-ON ••••••..•••••••.•.•••••••..•.•.••
DIAGNOSTIC PROGRAM - LSI-II •••••.••••••••••••..•
DIAGNOSTIC PROGRA~1 - MicroVAX ••..•••••••.•.•....
Runnling MOM .•...•..••.........••..•.•.•.•.•.•.
MDM Diskette Boot •.•...••••••••.••••.•.•....
MDM Tape Boot .•••.••.•..•••.•.•.•...........
MDM Examples ..••••.•••....••...•••••...•••..

CHAPTER 3

BASIC OPERATION

3.1
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
3.2.1.4

•••••••••••••••••••••••••••••••••••••••••

3- 1

FUNCTIONAL DESCRIPTION ..•••••••.•••........••...
DRVll-WA Registers............................
Word Count Register (WCR) .•••.•.••.•••••••.•
Bus Address Register (BAR) .•.••••••.•••••.••
Extended Bus Adc1ress Register (BAE) •....•...
Control/Status Register (CSR) .•.•.••••••••••

3-1
5-1
3-1
3-1
3-1
5-3

2.5.3

G ENE R fl... fJ

iii

2-10
2-11
2-12
2-13
2-14
2-14
2-14
2-15
2-16

CONTENTS

(Cont)

Page

3.3

Input and Output Data Buffer Registers
(DBRs)
User Interface Lines
LSI-II Bus Lines
User's I/O Device to Q-Bus Memory Transfer
(DATa or DATOB)
Interrupts
LSI-II Memory to User's Device Transfers
(DATIO or DATI)
TIM I NG ...••.•...

CHAPTER 4

PROGRAMMING

4.1
4.2
4.3
4.3.1
4 .3. 2
4.3.3
4.3.4
4.3.5
4.4
4.4.1
4 .4. 2
4.5
4.6

GENFRAL
PROGRAMMING INSTRUCTIONS
DRVll-WA REGISTERS
WCR
BAR
BAE
CSR
DBRs
PROGRAM INTERRUPTS
Word Count Overflow . . . . . . . . . . . . . . .
CSR ERROR Bit (Bit 15)
FUNCTION AND STATUS BITS
PROGRAMMING EXAMPLE

CHAPTER 5

INTERPROCESSOR LINKS

5.1
5.2
5.2. 1
5.2.2
5.2.3
5.3
5.3. 1
5.3.2
5.3. 3

GENERAL ..•.••••
OPERATING MODES
Word Mode
Single Cycle
Burst Mode
PROGRAMMING
Word Count Register (WCR)
Bus Address Register (BAR)
Output Data Buffer Register/Input Data
Buffer Register (ODBR/IDBR)
Control ana Status Register (CSR)

3.2.1.5
3 • 2. 2
3.2.3
3.2.4
3.2.4.1
3.2.5

5.3.4

3-3
1-3
3-5

3-7
3-8
3-9
3-11

4-1
4-1
4-1
4-1
4-1
4-2
4-2
4-2
4-2
4-2
4-2
4-3
4-5

5-1
5-1
5-2
5-1
C)-5
5-6
5-6
5-6
5-6
S-6

FIGURES
Figure No.
1-1
2-1
2-2
2-3

2-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
4-1
5-1
5-2
5-3

Title

Page

DRVI1-WA Simplified Interface Diagram •••••••••••
1-3
DRVII-WA Connector and Switch Locations .••.•••••
2-4
DRVII-WA Device Address Select Format .••••••.•.•
2-4
DRVII-WA Interrupt vector Address Select
Format . . . . . . . . . . . . . . . . . . . . . . . . . .
2-5
DRVll-WA Connector Pin Ass ignments •.•••••.••••••• 2-9
DRVI1-WA Block Diagram •.••.••••. ~ ••••••••••••••.
3-2
DMA DATO/DATOB Data Flow Diagram
3-8
DMA DArrrO/DATI Data Flow Diagram . . . . . . . . . . . . . . . . . 3-10
DRVI1-WA Single Cycle, User-Initiated, Timing
Diagrarn . • . . . • • . . . . • • . • . . • • • • . • • •
3-12
DRVII-WA Single Cycle, Program-Initiated,
Timing Diagram .•.•••.•.••••.•••.
3-13
DRVII-WA Burst Mode, user-Initiated, Timing
Diagrarn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
ORVII-WA Burst Mode, program-Initiated, Timing
Diagrarn .....••..•.•.••••••••.•••••••••.••••••••• 3-15
DRV11-WA DATTO Timing Diagram ••••••••••••••••••• 3-16
Fo]~mat

•••••••••••••••

•••••••••••••••••••••• e _ • • • • • • • • • • • • • •

4-3

Interprocessor Link Block Program ••••••••••••••.
Interrupt Sequence for Word Mode
Interprocessor Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Cycle Transfer Sequence for
Tnterprocessor Link .••••

5-1

CSR

It.......................

5-3
5-5

TABLES
Table No.
2-1
2-2

2-3
2-4
2-5
4-1
5-1

Page

Title

Recommended Cable Assemblies ••••••••••.•••••••••
2-2
Burst Mode Jumper ••••••• ~ •••••••••••••••••••••••
2-fi
Interprocessor Link Mode ,Jumper •.•••...•••••.•••
2-7
Independent Interrupts ••
2-7
DRVII-WA Diagnostic Tests ••••••..••.••..•••••••• 2-14
CSR Bit Functions •••••••
4-3
Correlation of CSR Function and Status Bits in
Interprocessor Link Operation •••••••••••••••••••
5-2
0

•••••••••••••••••••••••

0.......................

CHAPTER 1
INTRODUCTION

1.1 GENERAL DESCRIPTION
The DRV11-WA is a general-purpose Direct Memory Access (DMA) interface for t.ransferrin.g 16-bit data words directly between the
Q-bus memory and a user's I/O device. " Data Transfer Out (DATO) or
Data Transfer In (DATI) takes place over the Q-bus after a DMA request, once the DRVll-WA becomes bus master.
Burst modes (four-~
word or continuous), byte addressing, and read-modify-wri te opera- "
tion (DATIO")" are possible wi th the DRVl1-WA •• ~. The DRVll-WA features switch-selectable device and vector addresses, two 40-pin
connectors, and one 2-pin connector that provide simple interfaci ng to the user's I/O dev ice.
(The DRVl1-WA is compat ible wi th
both standard and extended Q-buses.)
There are six registers in the DRVll-WA.

They are as follows:

•

Word Count Register

(WCRl,

•

Bus Address Register

(BAR),

•

Extended Bus Address Register

•

Control/Status Register

•

Input and Output Data Buffer Registers (DBRs).

(BAE',

(CSR) , and

The CSR and DBRs are word- and byte-addressable, whereas the WCR,
BAR, and BAE are only word-addressable.
DRVll-WA operation is initialized under program control by:
1.

Loading the WCR with the 2's complement of
transfers,

Loading the BAR and BAE with the first address to or from
which data is to be transferred, and

Loading the CSR with the desired function bits.

Data transfers may now proceed under the control of
DMA logic.

1-1

the number of

the DRVll-WA

Figure 1-1 shows
the primary interface signals between the
DRVll-WA and the user's I/O device.
DMA input (DATI) or output
(DATa) data transfers take place when the processor clears READY.
For a DATO cycle (DRVll-WA to memory transfer), the user's I/O device first presets the CONTROL BITS (word count increment enable,
bus address increment enable, Cl, CO, A00, and ATTN), and then asserts CYCLE REQUEST to gain use of the Q-bus.
When CYCLE REQUEST
is asserted, input data is latched into the input DBR, the CONTROL
BITS are latched into the DRVll-WA DMA control, and BUSY goes low.
(A DATI cycle memory to DRVll-WA transfer is handled in a similar
manner, except that the output data is latched into the output DBR
during the bus cycle.)
When the DRVll-WA becomes bus master, a DATO or DATI cycle is performed directly to or from the Q-bus memory location specified by
the BAR and BAE.
At the end of each cycle, the WCR and BAR are
incremented and BUSY goes high while READY remains low.
A second
DATa or DATI cycle is performed when the user's I/O device again
asserts CYCLE REQUEST.
DMA transfers will continue asynchronously
until the WCR increments to zero, at which time READY goes high
and the DRVll-WA generates an interrupt (if intE~rrupt enable is
set) to the Q-bus processor.
If continuous burst mode is selected (SINGLE CYCLE low), only one
CYCLE REQUEST is required for the complete synchronous transfer of
the specified number of data words.

1-2

~
16-0UTPUT DATA BITS

16-DATA/ADDRESS BITS

6 - EXTENDED ADDRESS BITS

ATTN

READY

I--'

.....,

iI
!

FUNCTION BITS (1,2,3)
DRVll-WA
DMA
INTERFACE

en
...J

CYCLE REQUEST

CJ)

::J
CD

"\
vi

STATUS BITS (A.S,C)

..
USER'S
I/O
DEVICE

INIT, INIT V2
BUSY

BUS CONTROL

CONTROL BITS
BA INC ENB, WC INC ENB .. CO, C1, AOO

16-INPUT DATA BITS

C5-4719

Figure 1-1

DRVII-WA Simplified Interface Diagram

1.2 SPECIFICATIONS
The following specifications and particulars are for informational
purposes and are subject to change without notice.
Physical
Dual height, single width, extended length module.
Dimensions:
Circuit Card

Circuit Card Plus Handle

Length: 21.6 cm (8 • 5 in)
Height: 12.7 cm (5.0 in)
width:
1.3 cm ( .5 in)

Length: 22.8 cm (8 .9 in)
Height: 13.2 cm (5.2 in)
Width:
1.3 cm ( .5 in)

Weight:

215 grams

User I/O Connections:

Two 40-pin connectors, one 2-pin connector

M0 un tin g Re qui r em en t s :

P 1 u g s d ire c t 1 yin t 0 Q - b 11 S
Q-bus expansion backplane.

Electrical
Logic Power Requirements:
LSI-II Bus Loading:

1.8 A @ +5V + 5%

Presents one bus load

User Loading:
Input Data Lines
1 TTL unit load each
HIGH = Logic one
LOW = Logic zero
Input Control Lines
1 TTL unit load each
HIGH = Logic one
LOW == Log ic zero
Output Data Lines
10 TTL unit loads (drive)
HIGH = Logic one
LOW:: Logic zero

each

Output Control Lines
10 TTL unit loads (drive)
HIGH = Logic one
LOW:: Logic zero

each

1-4

(nominal)

b a c k pIa n e

0 r

Module Type:

M7651

operational:
Transfer Mode: DMA or program-controlled with interrupts
Data Transfer Rate:
up to 250,000 16-bit words per second in single cycle mode
Up to 400,000 16-bit words per second in burst mode*
Environmental
Temperature:

0 0 0

Storage: -40 to 66 C (-4~· to 150 F)
.
OperatIng:
5 0 to 50 0 C (41 0 to 122 0 F )

Relative Humidity: 10% to 95% noncondensing
1.3 RELATED LITERATURE
In addition to the M7651 print set (MP01582), the Microcomputer
Processor Handbook and the Microcomputer Interface Handbook contain useful information for installIng and operating the DRVII-WA
general-purpose DMA interface.
Handbooks may be ordered from the
nearest Digital Equipment Corporation Sales Office.

While doing continuous burst mode transfers, the DRV11-WA becomes bus master and holds the bus until the entire transfer is
complete.
This action may potentially lock out other devices
from accessing the bus while the transfers are ongoing.
This
mode of operation is consistent with the operation of the
18-bit predecessor product, DRV11-B.
1-5

CHAPTER 2
INSTALLATION

2.1 GENERAL
Installation of the DRVII-WA general-purpose DMA interface consists of selecting the device and interrupt vector addresses,
selecting mode of operation (18- or 22-bit addressing), selecting
functional operating modes as necessary (independent interrupts,
four-word or continuous burst mode, interprocessor link mode), and
then inserting the interface into an LSI-11/MicroVAX processor
system.
2.2 SYSTEM CONSIDERATIONS
Before installing the DRV11-WA into a Q-bus system, consideration
must be given to bus loading, power, priority, and space requirements.
2.2.1 LSI-II Bus Loading
The DRV11-WA presents one bus load to the Q-bus.
Fifteen bus
loads can be handled by the Q-bus; therefore, the user must determine the existing Q-bus load when installing additional Q-bus
modules.
2.2.2 Power Requirements
The DRVI1-WA requires 1.8 A @ +5V + 5% (nominal).
Power for
DRVI1-WA is obtained from the Q-bus-system power supply.

the

2.2.3 priority Requirements
Each device on the Q-bus has an interrupt and DMA priority based
on its relative position from the processor.
The DRVl1-WA is a
priority 4 device.
Since the user may install the DRVII-WA on the
bus along wi th other devices that use the same interrupt or DMA
priority, the user must bear in mind that when more than one device is requesting service, the device electrically nearest the
Q-bus processor has the highest priority and will be serviced
first.
In addition, if the REVll DMA refresh option is used (for LSI-II
systems), the REVII must be at a priority level higher than that
of the DRVII-WA.
Refer to the Microcomputer Processor Handbook
for detailed information on the REVII options.
2.2.4
Space Requirements
The DRVlI-WA requires one double height module slot.

2-1

2.3 USER I/O CABLES
The DRVII-WA has two 40-pin connectors which provide the interface
to the user's device.
Two cable assemblies are required.
It is
recommended that cable assemblies from Table 2-1 be used to connect the DRVII-WA to the user's device.
The listed cables are
terminated (one or both ends) with H856 40-pin connectors that
mate with the connectors on the DRVll-WA.
Cable selection is determined by the type of connections used on the user's device.
Th e des ire d cab 1 e len g t h ( XX) mus t be s p e c i f i ed when 0 r de r i n g .
(Lengths longer than 25 feet are not recommended for use with the
DRVll-WA.)
Cables may be ordered from the nearest Digital Equipment Corporation Sales Office.
Non-standard length cables may be
ordered at additional cost.
2.3.1 User Termination connector
The DRVll-WA has one 2-pin connector which optionally allows the
user to provide additional signal termination when cables other
than the one listed in Table 2-1 is used.
Table 2-1

Recommended Cable Assemblies

Cable No.

Connectors

Type

Standard Lengths

BC08R-XX

H856 to H856

Shielded flat

1, 6, 10, 12, 20, 25 ft
(0.305, 1.830, 3.050,
3.660, 6.100, 7.625 m)

(ft/m)

2.4 JUMPER AND SWITCH CONFIGURATION
The DRVll-WA contains two DIP (dual in-line package) switch units
(E40 and E50) and a number of jumpers that allow the user to select the module features desired.
The location of the switch
units and jumpers is shown in Figure 2-1.
The address selection
switch (E50) consists of ten switches that let the user select the
device addr~ss.
The second switch unit (E40) consists of ten
switches that let the user select the interrupt vector address and
l8-bit or 22-bit addressing mode.
2.4.1 Device Address Selection
The DRV11-WA contains six registers:

•
•
•
•

•
•

WCR
BAR
BAE
CSR
Input DBR
Output DBR

2-2

These registers must be addressed for data and status transfers
between the DRVll-WA and the LSI-ll/MicroVAX processor.
The BAR
and BAE use the same address.
The two DBRs use the same address.
The register addresses are sequential by even numbers and are as
follows.
Register

BBS7

Octal Address

Hex Address

WCR
BAR
BAE
CSR
DBRs

1
1
1
1
1

XXXXX0
XXXXX2
XXXXX2
XXXXX4
XXXXX6

3FF508
XXXXXA
XXXXXA
XXXXXC
XXXXXE

The assigned DMA interface base address is 772410 , 3FF508'h.
The
user selects a base address for assignment to the 8 WCR and sets the
device address selection switches on the DRVll-WA module to decode
this address.
The remaining BAR, BAE, CSR and DBR addresses are
then properly decoded by the module as they are received from,the
LSI-ll processor.
Figure 2-1 shows the location of the device address selection
switches on the DRVll-WA module.
Switches are set to the ON
(closed) position for bits to be decoded as "ONE" bits in the base
address.
Bi ts decoded as "ZERO" bi ts in the address have thei r
switches set to the OFF (open) position.
Figure 2-2 shows the address select format and presents the swi tch-to-bi t relationship
for the device address selection switches.

2-3

LINK MODE
SELECTION JUMPER

VECTOR ADDRESS, 022/Q18
SELECTION SWITCHES

DEVICE ADDRESS
SELECTION SWITCHES

BURST MODE
SELECTION JUMPER

000
W1

ESO

ATTENTION INTERRUPT
SELECTION JUMPER
C5·4720

Figure 2-1

DRVII-WA Connector and Switch Locations

DECODED BY BBS7

DECODED FOR
1 OF 4
REGISTERS

SELECTED BY SWITCHES

r~---------~~--------~v~------------------~~~--------------~
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01

DEVICE
ADDRESS
SELECTION
SWITCHES

ON 1
OFF

I I I I I I I I I I

OFF = "ZERO"
ON = "ONE"
CS·3958

Figure 2-2

DRVII-WA Device Address Select Format

2-4

2.4.2
Interrupt vector Address Selection
vector ad~resse~ 0-1774 8 are reserved for Q-bus system users.
The
DRVIl-WA IS asslgned vector address 124 .
The user selects the
8
interrupt vector address by means of switches
on the DRVll-WA module.
Figure 2-1 shows the location of the vector address selection swi tches.
vector address selection swi tches are set to the
ON (closed) position for bits to be encoded as "ONE" bits in the
vector address.
Bi ts encoded as "ZERO" bi ts in the address have
their switches set to the OFF (open) position.
Figure 2-3 shows
the address select format and presents the switch-to-bit relationship for the vector address selection switches.
NOTE
The DRVll-WA is designed to be compatible with the DRVll-Bi therefore, its assigned base address is 772410 (8) .
However, under MicroVMS, the DRV1l-WA is
treated, as much as possible, like a
DR11-W.
Therefore, in order for the device to autoconfigure correctly,
you
must set the device address and interrupt vector address to those reserved
for the DR11-Wi namely, set the device
address to rank 19 and the interrupt
vector address to rank 40,
both in
floating address space.
2.4.3 Addressing Mode Selection
The user selects 18- or 22-bit addressing by setting E40 switch 10
OFF (OFF=0) for l8-bit addressing, or ON (ON=l) for 22-bit addressing (see Figure 2-3).

1ST
OCTAL
DIGIT

2ND
OCTAL
DIGIT

4TH
OCTAL
DIGIT
10 OR 41

3RD
OCTAL
DIGIT

PREASSIGNED
AS ZEROS

VECTOR
ADDRESS
SELECTION
SWITCHES

ON 1

OFF

I I I

OFF
ON

= "ZERO"
= "ONE"

I I I I I I
NOT
USED

ON
OFF

= 22·BIT ADDRESS

= 1 8·BIT ADDRESS
C5-3t69

Figure 2-3

DRVII-WA Interrupt vector Address Select Format

2-5

2.4.4 Burst Mode Jumper
The DRVII-WA will, by default (W2 jumper installed), relinquish
and re-request bus mastership after every four DMA transfers.
The
user may select continuous burst mode transfers by removing the
push-on jumper from W2 and installing it at WI.
(Refer to Table
2-2 and Figure 2-1.)

NOTE
If continuous burst mode is selected,
the DRVII-WA will not relinquish the bus
until the entire transfer is complete.
This action is not recommended as it may
potentially lock out other devices from
gaining access to the bus while the
transfers are ongoing.
Table 2-2

Jumper

Burst Mode Jumper

Function

Factory
setting

Module is backward compatible with the
DRVll-B and will perform continuous burst
mode transfers and will not release the
bus until all transfers are completed.

Module will relinquish and re-request the
bus after every four DMA cycles.

R = Removed
I = Installed
2.4.5
Interprocessor Link Mode Jumper
The user may operate the DRVll-WA as an interprocessor link with
another DRVII-WA by removing the push-on jumper from W3 and installing it at W4.
(Refer to Table 2-3 and Figure 2-1).
This is
the recommended setting to use the DRVII-WA as an interprocessor
link.
In the default setting (W3 jumper installed), the DRVII-WA is
backward compatible with the DRVll-B and will not function as an
interprocessor link unless one of the processors acts as the
slave, and the other acts as the master.
Use of the DRVII-WA
within this configuration (W3 jumper installed) for interprocessor
link is not recommended.

2-6

Table 2-3

Interprocessor Link Mode Jumper

Function

Jumper

Factory
Setting

Module is backward compatible with DRVll-B
and should not be used as an interprocessor
link.

Module may be used as an interprocessor
link between two DRVll-WA modules.

R = Removed
I = Installed
2.4~6
Independent Interrupts Jumper
While in the default interrupt mode (W5 jumper installed), it is
not necessary for the READY bi t (CSR Bi t 7) to be CLEAR for the
DRVll-WA to interrupt.
With the IE bit (CSR Bit 6) set, the
DRVll-WA will interrupt when the ATTN bit (CSR Bit 13) or the NEX
bit (CSR Bit 14) is set.

For backward compatibility with the DRVll-B, the user may remove
the push-on jumper from W5 and install it at W6.
(Refer to Table
2-4 and Figure 2-1).
In this setting, the DRV11-WA will only interrupt when the READY bit (Bit 7) cf the CSR is set, and the IE
bit (Bit 6) in the CSR is set.
Table 2-4

Jumper

Independent Interrupts

Function

Factory
setting

With the CSR IE bit set, module will
interrupt when CSR ATTN or NEX bits are
set, independent of the READY bit being
set.

Module is backward compatible with DRV11-B.
with the CSR IE bit set, module will
interrupt only when the READY bit is set.

R = Removed
I = Installed

2-7

2.5 MODULE INSTALLATION
The type of CPU and its current configuration determines which of
the following procedures must be performed.
2.5.1
Installing the DRVII-WA in an LSI-II CPU
With the exception of the first two/four slots (the LSI-II processor always occupies the first two/four slots depending on CPU
type) ,the DRVII-WA can be installen into any Q22 slot (see Section 2.2.4) of the LSI-Il backplane.
However, JLf REVII DMA refresh option is used, the DRV11-WA must be at a lower priority
than the REVII.
When inserting the module into the backplane,
make sure that the deep notch on the module seats against the
connector block rib.
Do not insert or remove the module with
power applied.
After performing-the-lnitial turn~on (see Section
2.8);---c-onne-ctthe user's I/O cables to JI and J2 on the DRVII-WA
I/O connectors. Connector locations for the DRVII-WA are shown in
Figure 2-1.
Pin assignments for JI and J~ are shown in Figure 2-4
and are specified in Chapter 1, Section 1.2.

2-8

A
CYCLE REQUEST H

- ..

-H

INIT V2 H

- READY H

SINGLE CYCLE H

-P

...

INIT H
STATUS B H

\..0

C1 H

FNCT 1 H

...

81N H

MM NN

...-

3 OUT H
2 OUT H

pp 'RR

1 OUT H

...

o OUT H

l!..U

7 IN H

9 OUT H

61N H

10 OUT H

51N H

. 11 OUT H
f---~

- TT..
w

12 OUT H
13 OUT H
14 OUT H

.. 15 OUT H

41N H
3 IN H

- FF...
EE
- JJ
HH
KK
...- LL
MM NN

-..

C...C

-..
-

..-

1 IN H

o IN H

91N H

10 IN H

"""-

11 IN H

12 IN H

-...

21N H

13 IN H
141N H

--"

15 IN H

CO H
FNCT 2 H

8 OUT H

BA INC ENB H

-S T-

AOO H

FNCT 3 H

5 OUT H
4 OUT H

ATTNH

7 OUT H
6 OUT H

AA BB
I

- BUSY H

- V-

STATUS C H

WC INC ENB H

C
H

STATUS A H

+5V

•

.. GND

J3
C5-4721

Figure 2-4

DRVII-WA connector Pin Assignments

2.5.2

Installing the DRV11-WA in the BA23 Enclosure

(MICRO-l1/

MicroVAX)
1.

Remove the ac power cable from the wall outlet.

Remove the rear cover and all external cables.
cables for reinst~llation later.

Loosen the two screws retaining the rear I/O panel assembly.
Swi ng the assembly open and remove both ret a i n i ng
straps.

Disconnect any internal cables attached to the back of the
I/O panel assembly.
Note their specific location and the
or i en tat ion 0 f the con n e c tor 0 n e a c h cab 1 e .
Rem 0 v e t he
rear I/O panel assembly.

Set the dev ice and vector address swi tches
jumper options (refer to Section 2.4).

connect the BC08R-XX ribbon cables from Jl and J2 on the
module to the insert connector assemblies on the I/O
panel.
Label the insert connectors for connection to the
user's I/O cables later.

7 ..

Wh en ins taIl i n g the f) RV 11-WA i n t h e B A2 3 en c los u r e , 0 bserve the configuration rules and guidelines outline in
the CPU technical manual(s).

Label all

and

des ired

Slide the module into the appropriate backplane slot.

Reconnect any internal cables removed from the I/O panel.

Replace
closed.

the retaining straps and swing the I/O
Tighten the two panel retaining screws.

10. Do not replace the rear cover at this time.
external cables.

panel

Replace all

11. Connect the ac power cord.
12. Perform the initial turn-on procedures (Section

2.~)

•

.13. Connect the user I/O cables to the insert connector assemblies on the I/O panel.
14. Replace the rear cover.

2-10

2.5.3
Installing
MicroVAX)

the DRVII-WA

the

BAl23

Enclosure

(MICRO-II/

Remove the ac power cable from the wall outlet.

Open the rear door.

Loosen the captive screw that fastens the right-side panel
to the rear of the enclosure frame.

Pullout on the bottom of the right-side panel until it
releases from the two snap fasteners holding it to the
bottom of the frame.

Lift the panel far enough to release it from the slot
the lip at the top of the frame.

Release the clasps at the front of
swing the door open, and remove it.

Set the device and vector address switches
jumper options (refer to Section 2.4).

Connect the BC08R-XX ribbon cables from Jl and J2 on the
module to the insert connector assemblies on the I/O
panel.
Label the insert connectors for connection to the
user's I/O cables later.

9•

When ins tall i n g the DF V11-WA i n the B 1 2 3 en c I os u r e , 0 bserve the configuration rules and guidelines outlined in
the CPU technical manual (s) .

the

card-cage
and

door,

desired

Slide the module into the appropriate backplane slot.
10. Do not replace the card-cage door
this time.

right-side panel

11. Connect the ac power cord.
12. Perform the initial turn-on procedures (Section 2.6).
13. Connect the user I/O cables to the insert connector assemblies on the I/O panel.
14. Replace the card-cage door and the right-side panel,
versing steps 2 through 6 of this section.

2-11

re-

2.6
INITIAL TURN-ON
After completing the module installation, turn-on the LSI-ll/
MicroVAX and initialize the system.
With no I/O cables connected
and using the console terminal and operating procedures, perform
the following quick operational verification.
LSI-II
1.

Load the addresses of the WCR, BAR, CSR, AND DBRs through
the system terminal and examine the locations.
The terminal will indicate the following:
18-Bit

22-Bit
WCR contents
BAR contents
BAE contents
CSR contents
DBR contents
2.

will
will
will
will
will

be
be
be
be
be

WCR contents will be 000000
BAR contents will be 000001

000000
000001
100000
127200
177777

CSR contents will be 127200
DBR contents will be 177777

The WeR, BAR, and BAE (if 22 bit addressing is selected)
can be loaded with data from the system terminal and the
corresponding data read back on the terminal.
BAR bit 0
will read as a one (1) with no I/O cables connected.
NOTE
BAE (ADDRESS xxxxx2) is read by first
examining the BAR (ADDRESS xxxxx2) and
then exami ni ng ADDRESS xxxxx2 aga into
access the BAE.

MicroVAX
1.

Enter MicroVAX console mode (see MicroVAX Owner's Manual).
The console mode prompt is "»>".

Examine the addresses of the WCR, BAR, CSR, and DBRs (refer to Section 2.4.1) through the system console using· the
console-mode commands shown in Example 2-1.
This example
shows the expected contents of the registers, assuming the
assigned base device address for the module is used.
The
hex addresses used in the example were determined as follows:

2-12

22-bit register address:
22-bit I/O space base address:
I/O address offset:
32-bit I/O space select (bit 29):
32-bit physical register address:

3FF5nn
3FE000
--ISnn
+ 2CHHHHHH3
-2-00015nn

»>
P
»>
P
»>
P
»>
P
»>
P

WCR
" contents
BAR
" contents
BAE
" contents
CSR
" contents
!DBRs
! " contents

E/W/P 20001508<Return>
2000'1508
0000
E/W/P 2000l50A<Return>
2000l50.A 0'001
E/W/P 2000150A<Return>
2000I50A 8000
E/W/P 2000l50C<Return>
2000150C AE80
E/W/P 2000150E<Return>
2000150E FFFF

Example 2-1

Module Register Check on MicroVAX

NOTE
For an explanation of the MicroVAX console commands, refer to the MicroVAX
Technical Manual(s).
The user's I/O device cables can now be connected to the DRVll-WA
(Figure 2-1).
2.7 DIAGNOSTIC PROGRAM - LSI-II
The check procedure performed in Section 2.6 does not completely
verify the operation of the DRVIl-WA.
Complete module operation
can be verified through the use of the diagnostic software program
AC-T974C-MC.
The pro~ram can be loaded into the LSI-II system by
means of any standard loadable device.
A BC05L or BC06R maintenance cable (not longer than 25 ft) is requireCl to loop the DBR
output to the ORR input for checking the I/O data path.
A complete description of the diagnostic software program and its implementation is provided in AC-T974C-MC.
When you execute the ,.Z\,C;;.;;.,A9~1,4.C:;-MC diagnostic, you must select software Switch 12 (SW12) of the SWR to correspond with your selection
of hardware Swi tch 10-E40.
SW12 must be ON (ON=l) to enable 22bit address testing, or OFF (OFF=0) to enable l8-bit address testing.
The default setting is OFF.
S10-E40

SW12 of Diagnostic

ON = 22-bit addressing
OFF = 18-bit addressing

ON = Enable 22-bit address testing
OFF = Disable 22-bit address testing

The diagnostic will continue to run until
control character.

2-11

is terminated with a

2.8 DIAGNOSTIC PROGRAM - MicroVAX
The DRVII-WA MicroVAX diagnostic is called NADRAE and runs under
MOM (MicroVAX Diagnostic Monitor).
The diagnostic comprises the
tests listed in Table 2-5.
Table 2-5

DRVII-WA Diagnostic Tests

Test

Function/Component Tested

WCR (Word Count Register)
BAR (Bus Address Register)
BAE (Extended Bus Address Register)
CSR (Control and Status Register)
CSR Byte/Word addressing and interrupts
CSR GO, READY, FUNCTION 1:3, and STATUS A:C bits
Read/Write to the DBR (Data Buffer Registers)
READY controls BAR BIT 0
DBR is clocked by the cycle bit
Memory to device single-word transfers (DATI)
Device to memory single-word transfers (DATO)
Memory to device multiple-word transfers
Device to memory multiple-word transfers
Memory to device multiple-word burst mode transfers
Device to memory multiple-word burst mode transfers
Maintenance bit control of Cl and single cycle
NXM (Non-existent memory) bit functionality
NPR transfers in maintenance mode

3
4
5
6
7
8
9

10
11

13
14
15

The MOM VERIFY mode (see Example 2-2) runs tests 1 through 4, and
requires no loopback.
SERVICE mode runs all 15 tests, and requires the digital loopback to be installed.
The loopback should
be installed at the bulkhead panel, connecting output (.Jl) to
input (J2).
2.8.1 Running MDM
The DRVII-WA MicroVAX diagnostic is supplied as one of the diagnostics on the MDM diskette or tape.
Each media requires a different boot procedure, oescribed in detail in Chapter 1 of the
appropriate MicroVAX II Technical Manual(s) (Table H-3, page H-2).
Briefly, the boot procedures are as follows.
2.8.1.1

MDM Diskette Boot --

Insert the MOM diskette in diskette drive 1.

Set the Mi croVAX I I power swi tch to 1 (turn power on),
press RESTART.
The diagnostic will boot as follows:
a.

If Halts are
automatically.

disabled,

2-14

the

diagnostic

will

boot

If Halts are enabled, the MicroVAX II will enter console mode and display the console prompt.
Manually
boot the aiagnostic from DUAl:
»> B DUAl

Several information screens will be displayed followed by
prompts to enter da te and time, to insert the rema i n i ng
diskettes, and to continue.
Respond to the prompts.

The MAIN MENU will then be displayed:

•

Select item #4 to display the Service Menu.

•

Select item #4 to enter system commands.

The MOM prompt will then be displayed:
MOM»
Examples
they are

2.8.1.2

2-2

through

2-5

show

the

MOM

commands

and

how

place

the

USE?d.

MOM Tape Boot

Push the Fixed-disk 0 Ready
fixed-disk unites) off-line.

pushbutton(s)

Set the MicroVAX II power switch to 1

Tnsert the MOM tape cartridge into tape drive 1.

Push the Load/Unload pushbutton.
as follows:

(turn power on) .

The diagnostic will boot

Tf Halts are disabled,
matically.

the diagnostic will boot auto-

If Halts are enabled, the MicroVAX II will enter console mode and display the console prompt.
Manually
boot the diagnostic from MUA0:
»> B MUA0

Several information screens will be displayed followed by
prompts to enter da te and time, and to cont i nue.
Respond
to the prompts.

The MAIN MENU will then be displayed:
•

Select item #4 to display the Service Menu.

•

Select item #4 to enter system commands.

2-15

The MOM prompt will then be displayed:
MOM»>
Examples 2-2 through
they are used.

2-5

show

the

MOM

commands

and

how

2.8.1.3 MOM Examples -- Example 2-2 shows how the HELP command is
entered to display a list of current MOM commands.
MOM»

HELP<Return>

Current Commands are:
CONFIGURE
SELECT Diag name
DISABLE Dia9 name
ENABLE Diag_name
SET DETAILED ON
DETAILED OFF
MODE VERIFY
SERVICE
PROGRESS OFF
PROGRESS BRIEF
PROGRESS FULL
SECTION FUNCTIONAL
UTILITY
EXERCISER
TEST ALL
xx
PASSES xx
START
START ALL
SHOW CONFIGURATION
SHOW DEFAULT
SHOW DEVICE UTILITIES
SHOW ERRORS
MOM»

Example 2-2

Configure system
Select a diagnostic (all units) to run
Prevent a diagnostic from running
Allow a diagnostic to run
Display detailed messages
DO NOT display detailed messages
Set verify mode tests
Set service mode tests
Display no progre~s messages
Controller progress messages
Controller and test progress messages
Set functional test section
Set utility test section
Set exerciser test section
Run all enabled tests
Run only test number xx
Run tests for xx passes
Start selected tests running
Start all enabled tests running
Show system configuration information
Show default 'settinqs
Show utility titles
Show reported errors

MOM HELP Command

2-16

Example 2-3 shows the defaults for the ORVll-WA diagnostic.
Note
that commands can be abbreviated by typing only enough of the command to uniquely identify it.
For example, typing SH DEF is the
same as typing SHOW DEFAULT.
MOM»

CONFIG<Return>

MOM»

SHOW CONFIG<Return>

MOM»

SEL ORVI1WA<Return>

MOM»

SH OEF<Return>

Selected device:
1
DRVllWA Enabled
Mode is SERVICE
Selection is FUNCTIONAL
Number of passes is: 1
No time limit
Tests to be run: ALL
Continue on error
Detailed message is Off
Progress message is Off
MOM»
Example 2-3

MOM SHOW DEFAULT Command

The SHOW DEFAULT command shows the current setting of default
parameters.
The "real" defaults (shown in Example 2-3) are listed
only when the diaqnostic is first booted and no parameters are
changed wi th MOM commands.
The parameter of a speci fic command
can only be changed by entering the command with a new parameter.
For example, the default test SECTION is FUNCTIONAL and can only
be changed by typing either:
MOM»

SET SEC UT

MOM»

SET SEC EX

2-17

Example 2-4 shows the commands to run the full
tests.
MOM»

CONFIG<Return)

MDM»

SEL DRVIIWA<Return)

MDM»

SET PROG FULL<Return)

MDM»

SET DET ON <Return)

MDM»

SET MODE SERVICE<Return)

MDM»

SET SECT FUNCTIONAL<Return)

MDM» ST<Return)
DRVIIWA started.
please follow instructions carefully!
All testing will be done from the bulkhead
please attach loopback cable from output (Jl)
to input (J2) CKDRVI-KA connector
Press RETURN when completed ...
Thank you, you may continue your testing
DRVIIWA pass I test number 1 started.
DRVllWA pass 1 test number 2 starteo.
DRVllWA pass 1 test number 3 starte0.
DRVIIWA pass 1 test number 4 started.
DRVIIWA pass 1 test number 5 started.
DRVllWA pass 1 test number 6 started.
DRVllWA pass 1 test number 7 started.
DRVIIWA pass 1 test number 8 started.
DRVIIWA pass 1 test number 9 startet1.
DRV11WA pass 1 test number 10 started.
Start of DATI section of test
Start of DATO section of test
DRVIIWA pass 1 test number 11 started.
Start of DATI section of test
Start of DATO section of test
DRVIIWA pass 1 test number 12 started.
Start of DATI section of test
Start of DATO section of test
DRVIIWA pass 1 test number 13 started.
DRVllWA pass I test number 14 started.
Start of DATI section of test
Start of DATO section of test
DRVI1WA pass 1 test number 15 started.
Start of DATI section of test
DRVllWA passed.
MDM»

2-18

set of

functional

Example 2-5 shows how the UTILITY section is run.
MOM»

CONFIG<Return>

MOM»

SEL DRV1lWA<Return>

MDM»

SET DET ON<Return>

MOM»

SET PROG BRIEF<Return>

MOM»

SET MODE SERVICE<Return>

MOM»

SET SECT UTILITY<Return>

MDM» ST<Return>
ORVI1WA started.
ORV1lWA pass 1 -

test number 1 started.

DRV1lWA passed.
MOM»
Example 2-5

MOM Commands to Run the UTILITY Section

NOTE
To run the UTILITY Section, SERVICE Mode
must be set and the digital loopback
must be installed.

2-19

CHAPTER 3
BASIC OPERATION

3.1 GENERAL
This chapter contains a functional description of the DRV11-WA.
The DRVI1-WA reg i sters are descr i bed as well ,as user dev ice and
bus operations necessary to perform DMA transfers.
Figure 3-1 is
a block diagram of the DRV11-WA.
All descriptions are written to
this diagram.
The chapter ends with a brief description of the
timing associated with DMA transfers.
3.2

FUNCTIONAL DESCRIPTION

3.2.1 DRV11-WA Registers
The DRV1l-WA contains six registers:
•
•
•
•
•

Word Count Register (WCR) ,
Bus Address Register -(BAR) ,
Extended Bus Address Register (BAE) ,
Control status Register (CSR) , and
Input and Output Data Buffer Registers

(DBRs).

3.2.1.1 c~W6rd Count Register (WCR) __ The WCR is a 16-bit read/
write regist~r that controls the numb~r of transfers.
This register is loaded (under program control) with the 2's complement
(negative number) of the number of words to be transferred.
At
the end of each transfer, the word count register is incremented
(i f WC INC ENB is high).
When the contents of the WCR is incremented to zero, transfers are terminated, READY is set, and if the
interrupt enable bit is set, an interrupt is requested.
The WCR
is word-addressable only.
.i

3.2.1.2 _Biis~~Add:ress __ Register (BAR) -- The BAR is a 15-bit read/
write register.
This register is loaded (under program control)
with a bus address (not including address bit 0) that specifies
the location to or from which data is to be transferred.
The BAR
is incremented after each transfer (if BA INC ENB is high), and
can be incremented across 32K memory boundaries by means of the
extended address feature of the DRV11-WA _
Systems wi th only 16
address bits will uwrap-around" to location zero when the extended
address bi ts are incremented.
On systems wi th extended addressing, an overflow in the BAR will increment the XA16, XA17 bits in
the CSR when in Q18 mode or the BAE register when in Q22 mode.
The BAR is word-addressable only.
3.2.1.3 _EXIended~__AddressRegister (BAE)
The BAE is a 6-bit
read/write register accessible when -exten-ded addressing mode (Q22)
is selected.
This register is loaded (under program control) with
bits 16-21 of a bus address that specifies the location to or from
which data ,is to be transferred.
If the BAR overflows, it will
increment the extended address bits in Q22 mode.
The BAE is wordaddressable only_
3-1

EXTENDED
BUS
ADDRESS
REGISTER
(BAE)

f.--- 022ENB
CUP15l

/'~
BWTBTL
BBS7

BDAL '6L

<....

If"

::>
L

BIAKI

BIANO

BIRQ

WORD COUNT
(DA 00-15 H)

K....

A3-A12

DEVICE
ADDRESS
SELECTION
SWITCHES

....

V2-V9

DEVICE
ADDRESS
SELECTION
SWITCHES

F,~:,fOA01t'

ATTNH

... ,,,",.'

I=J.E CM06r ,: "

CONTROL
STATUS
REGISTER
(CSR)

BAD

SYNC
DIN

L
L
L
L
L

~
INPUT
DATA
BUFFER
(DBR)

TO
CSR
WCR
BAR

CYCLE
REQUEST H

USER'S
I/O
DEVICE

IE (1) H

DAO.1.2 H

STAT A.B.C H

BAD

XAD 16.1 7(DA04.05)

GO (DAO)

FNCT 1.2.3 H

FNCT 1.2.3(DA01.02.031

READY H

ATTN (DA13)

CYCLE (DA08)

INTERRUPT
LOGIC

WC INC ENB H

STATUS A.B.C(D~ 11 .10.09)
.A

PROTOCOL
LOGIC

WORD
COUNT
REGISTER
(WCR)

NEX(DA14)

BWTBT L

BDOUT
BDMR
BSACK
BDMGO
BDMGI
BRPLY
BDIN
BSYNC

..
)

MAINT(DA12)

IE (1) H

:>
AOO H

READY (1) H

;

tI..

BA INC ENB H

(DA 00-1 5 H)

3-STATE BUS (DATA/ADDRESS BITS DAOO-15 H)

BINIT

OUTPUT DATA BITS
(0-15 OUT H)

ERROR (DA15)

VECTOR
ADDRESS
GENERATION

OUTPUT
DATA
BUFFER
REGISTER
(DBR)

"'I

TRANSCEIVERS

-------

(

DEVICE
ADDRESS
SELECTOR

)

ADDRESS

(0-5)

r------BBS7 L

A
ADDRESS]

...

)
16-BUS DATA/ADDRESSI
VECTOR BITS
(BDAL 00-15LI

I--

TRANSCEIVERS
EXTENDED
ADDRESS

022
~

I--

BUS
ADDRESS
REGISTER
(BAR)

('.~

CSR
(018)

BDAL 18-21L

I--

ADDRESS

}FROM-~

BDAL 17L

i---

...

LSI-11
BUS

...

K' f

INPUT DATA BITS
(0-15 IN H)

DBRs
SAE
CO H
C1 H
DMA
CONTROL
LOGIC

SINGLE CYCLE H

l
L
L

.......

Figure 3-1

DRV11-WA Block Diagram

INIT H

INITV2H

3.2.1.4 Control/Status Register (CSR) -~ The CSR is a l~-bit register used to control the functions and monitor the status of the
interface.
Bit 00 is a write-only bit and always reads as a zero.
Bits 01-06, 08, and 12 are read/write bits, while bits 07, 09-11,
and 13-15 are read-only bits.
Bit 14 can be written to a zero.
Bits 04 and 05 are the extended addressing bits.
If extenoen address mode (Q22) is selected, bi ts 04 and 05 are read-only bi ts.
CSR functions are fully described in Chapter 4.
The CSR is both
byte- and word-addressable.
3.2.1.5
Input and Output Data Buffer Registers (DBRs) -- The two
DBRs are l6-bit registers.
The input OBR is a read-only register;
the output OBR is a write-only register.
Data is loaded into the
input OBR by the user's device and subsequently transferred to
memory under OMA control by the ORV11-WA, or unner program control
by the Q-bus processor.
Conversely, data is written into the output OBR from memory under OMA control by the DRVll-WA, or under
program control by the Q-bus processor, and read by the user's
device.
The input and output OBRs interface to the user's device
by means of two separate 40-pin I/O connectors.
These connectors
may be cabled together (for maintenance purposes) to function as a
read/write register.
The input and output OBRs share the same bus
address and are byte- and word-addressable.
3.2.2 User Interface Lines
There are 50 interface lines (25 per connector) between the
DRV11-WA and the user's I/O device.
Of these lines, 32 are I/O
data lines, three are for status, and IS are for control.
A brief
description of these interface lines follows.
Description

Mnemonic
00 OUT - 15 OUT

16 TTL data output lines from the DRVII-WA.
One = high.
Correspond to ODBR <00:15>.

00 IN -

16 TTL data input lines from the user's
device.
One = high.
Correspond to IOBR
<00:15>.

15 IN

STATUS A, B, C

Three TTL status
input
lines from the
user's device.
The function of these lines
is defined by the user.
Correspond to CSR
<09:11> (Table 4-1).

FUNCT 1, 2, 3

Three TTL output 1 i nes to the user's device.
The function of these lines is defined by the user.
Correspond to CSR
<01:03> (Table 4-1).

INIT

One TTL output line; used to initialize the
user's device.

3-3

Description

Mnemonic
INIT V2

One TTL output line; present when INIT is
asserted or when FUNCT 2 is written to a
one.
Used for interprocessor buffer applications.

A00

One TTL input line from the user's device.
This line is normally low for word transfers.
During byte transfers this line controls address bit 00.

BUSY

One TTL output line to the user's device.
BtTSY is low when the DRVll-WA DMA control
logic is requesting control of the Q-bus or
when a DMA cycle is in progress.
A lowto-high transition indicates end of cycle.

READY

One TTL output line to the user's device.
When the READY line goes low, DMA transfers
may be initiated by the user's device.

C0, Cl

Two TTL input lines from the user's device.
These lines control the Q-bus cycle for DMA
transfers.
C0 and Cl codes for the four
possible bus cycles are listed as follows.
C0 and Cl Codes
Bus Cycle
DATI
DATI0
DATO
DATOB

SINGLE CYCLE

0
1

0
0

0
1

One TTL input line from the user's device.
This line is internally pulled high for
normal DMA transfers.
For burst mode operation, SINGLE CYCLE is driven low by the
user's device.
CAUTION
When SINGLE CYCL'E i's dr i ven low, total
system operation is affected because the
Q-bus becomes 2dedt(::,at.,~d :tot.pe DMA device,;,. other devices, tticludlIigt'y,the MOS
memory refresh function, cannot use the
bus.

WC INC ENB

One TTL input line from the user's device.
This line is normally high to enable incrementing the DRVII-WA word counter.
Low inhibits incrementing.
3-4

Description

Mnemonic
BA INC ENB

One TTL input line from the user's device.
This line is normally high to enable incrementing the bus address counter.
Low
inhibits incrementing.

CYCLE REQUEST

One TTL input line from the user's device.
A low-to-high transition of this line initiates a DMA request.

ATTN

One TTL input line from the user's device.
This line is driven high to terminate DMA
transfers, to set READY, and request an
interrupt if the interrupt enable bit is
set.
This line must be low to execute DMA
transfers.
Corresponds to CSR <13> (Table
4 -1) •

3.2.3 LSI-II Bus Lines
There are 38 LSI-II bus signal lines used by the DRVII-WA; 16 of
these are multiplexed and bidirectional lines that carry data and
address bits.
Six lines are used for extended address bits, while
16 lines are used for control signals.
A brief description of the
38 bus lines follows.
Description

Mnemonic
BDAL 0 - BDAL 15

16 bus data/address lines.
An address is
first placed on these lines followed by the
data.
These lines are asserted when driven
low.

BDAL 16, 17

Two bus lines used to address beyond 32K of
memory by the DRVll-WA.
These lines are
asserted when low.

BDAL 18-21

Four bus lines used to address beyond 128K
of memory.
These 1 i nes are asserted when
low.

BDOUT

One bus line; when asserted (low), indicates that data is available on the BDAL
1 i nes and an output transfer (wi th respect
to the bus master) is taking place.

BRPLY

One bus line; asserted (low) in response to
BDIN or BDOUT and in response to BIAK
transactions.
It is generated by the slave
device for address recognition.

3-5

Mnemonic

Description

BDIN

One bus line; when asserted (low) during
BSYNC time, indicates an input transfer
(with respect to the bus master).
Requires
a BRPLY response.
BDIN is asserted when
the bus master is ready to accept data from
the slave.
When asserted wi thout BSYNC,
indicate·s that an interrupt operation is
occurring.

BSYNC

One bus line; asserted (low) by the bus
master to indicate that it has placed an
address on the BDAL lines.
The transfer is
in progress until BSYNC is negated (high).

BWTBT

One -bus line; asserted (low) during address
time to indicate that an output sequence
(DATO or DATOB) is to follow.
BWTBT is
also asserted during data time for byte addresing during a DATOB.

BIRQ

One bus line; device asserts (low) this
line when its interrupt enable, interrupt
request,
and ready flip-flops are set.
BIRQ informs the LSI-II processor that service is requested.

BIAKI, BIAKO

Two bus lines; one is interrupt acknowledge
in, the other is interrupt acknowledge out.
BIAKI is generated by the LSI-II processor
in response to BIRQ.
The processor asserts
(low) BIAKO wnich is routed to the BIAKI
pin of the first device on the bus.
If the
device is not requesting an
interrupt,
BIAKO is passed (as BIAKI) to the next device.

BBS7

One bus line; asserted (low) by the LSI-II
processor when addressing a device for program-controlled transfers.
The DRVII-WA
can assert BBS7 and address other devices
on the LSI-II bus without processor intervention.

BDMGI, BDMGO

Two bus lines; one is DMA grant in, the
other is DMA grant out.
The LSI-II processor generates BDMGO which is routed to
the BDMGI pin of the first bus device.
If
the device is requesting the bus, it will
inhibit passing BDMGO to the next bus device.
If the device is not requesting the
bus, it will pass BDMGO as (BDMGI) to the
next device.
3-6

Mnemonic

Description

BINIT

One bus line; asserteCi (low) by the LSI-II
processor to initialize or clear devices
connected to the LSI-II bus.

BSACK

One bus line; BSACK is asserted (low) by a
DMA nevice in response to the LS1-1l processor's BDMGO signal, indicating that the
DMA device is bus master.

BDMR

One bus line; a device asserts this signal
for DMA requests and to become bus master.

3.2.4 user's I/O Device to Q-Bus Memory Transfer (DATO or DATOB)
Data transfers from the user's I/O device to the Q-bus memory are
DMA transfers.
Figure 3-2 illustrates the data flow for a DMA
DATa or DATOB cycle.
Referring to Figure 3-1, DMA transfers are
initialized under program control by loading the DRVII-WA ~veR .(in
2' s complement) wi th a count equal to the number of worns to be
transferred; loading the BAR (and BAP. if Q22 is selecten) with the
starting memory address for word storage; and setting the CSR for
transfers.
The user's I/O device must set ATTN low (ZERO), then the GO bit of
the CSR is wr i tten to a "one", READY goes low ann the user's I/O
device conditions the A00, BA INC ENB, 'NC INC ENB, SINGLE CYCLE
(high for norma 1 DMA transfers), and the C0, Cl 1 i nes (refer to
Section 3.2.2), and then asserts CYCLE REQUEST.
The INPUT DATA
BITS and control bits (C0, Cl and SINGLE CYCLE, BA INC ENABLE, we
INC ENABLE) are latched into the respective DRVII-WA registers (at
the high-to-Iow transition of BUSY).
CYCLE REOUEST sets CYCLE and
causes the DRVII-WA to assert BDMR, the processor asserts BDMGO
which is received as BDMGI.
The DRVll-WA becomes bus master and
asserts BSACK and negates BDMR.
The processor then terminates the
bus grant sequence by negating BDMGO.
As bus master, the DRVII-WA performs a DATO or DATOB bus cycle by
placing the memory address on BDAL lines, asserting B'NTBT, and
then asserting BSYNC.
The LSI-II memory decodes the address;
then, the ORVII-WA removes the address from the BDAL lines, negates BWTBT (BWTBT will remain active for a DATOR) and then places
the user's input data on the BOAL lines and asserts BDOUT.
Memory
recei ves the data and asserts BRPLY.
In response to BRPLY, the
DRVII-WA negates BOOUT and then removes the user's input data from
the BDAL lines.
Memory now negates BRPLY, the bus cycle is terminated, and the bus is released when the DRVll-WA negates BSACK
and BSYNC.

3-7

At the end of the first transfer, the DRVll-WA WCR and BAR are incremented (for normal DMA transfers), BUSY goes high, while READY
remains low.
With BUSY high and READY low, the user's I/O device
can initiate another DATa or DATOB cycle by again asserting CYCLE
REQUEST.
DMA transfers can continue until the WCR increments to
zero and generates an interrupt request, if the interrupt enable
bit is set.

USER'S
DEVICE

DRV11-WA

\. ~

. . - DATO OR DATOB + - -

DATA FLOW

---.

MEMORY

LSI-11
PROCESSOR

C5-3962

Figure 3-2

DMA DATO/DATOB Data Flow Diagram

3.2.4.1
Interrupts -- When the WCR increments to zero, READY goes
high and the DRVll-WA generates an interrupt request (if the interrupt ci rcui ts are enabled).
The Q-bus processor responds to
the interrupt request (BIRQ) by asserting BDIN followed by BIAKI
(interrupt acknowledge).
BIAKI is received by the DRVll-WA and in
response places a vector address on the BDAL lines, asserts BRPLY,
and negates BIRQ.
The Q-bus processor receives the vector address
and negates BDIN and BIAKI.
The DRVll-WA now negates BRPLY, while
the procesor exits from the main program and enters a service program for the DRVll-WA as indicated by the vector address.

3-8

Interrupt requests from the DRVII-WA occur for
ditions:

the following con-

When the WCR increments to zero.
This is a normal interrupt at the end of a designated number of transfers.

When the user's I/O device asserts ATTN.
This is a special condition interrupt which overrides the WCR or, if
the independent interrupt jumper is installed, may independently cause interrupts.

3•

When a non-ex i stent memory loca t ion is
DRVII-WA.
Th i s cond i t i on interrupt is
BRPLY is received from the Q-Bus memory.

Interrupts are explained
manual.

in greater detai 1

addressed by the
produced when no
Chapter

this

NOTE
As of module CS Revision C, the DRVII-WA
module will no longer generate an interrupt if the IE bit of the CSR is written
to a one without simultaneously setting
the GO bit.
In earlier module revisions, setting the IE bit without setting the GO bit simultaneously would
generate a spurious interrupt.
Software
written to ignore this first interrupt
should be modified to process the interrupt.
3.2.5 Q-Bus Memory to User's Device Transfers (DATIO or DATI)
DMA transfers from the O-Bus memory to the user's I/O device occur
in a manner similar to that described for user's I/O device to
memory transfers.
Figure 3-3 illustrates the data flow for a DMA
DATIO or DATI cycle.
Under program control, the DRVII-WA WCR
(Figure 3-1) is loaded with a count equal to the number of transfers, while the BAR is loaded with the starting address from which
the first word will come.
The CSR is set for transfers.
The user's I/O dev ice must set ATTN low (zero).
Then, \Vi th the
CSR set, READY goes low and the user's I/O device conditions the
C0, Cl lines (refer to Section 3.2.2) for a DATI or a DATIO, and
conditions the WC INC ENB, BA INC END, SINGLE CYCLE (high for normal DMA transfers), and asserts CYCLE REQUEST.
BUSY from the
DRVII-WA goes low and the user's control bits are latched into the
DRVII-WA.
The DRVII-WA then asserts BDMR, which makes a bus request.
When the request is arbitrated as described in Section
3.2.4, the DRVII-WA becomes bus master.
When the DRVII-WA becom~s bus master, a DATI or DATIO bus cycle is
performed (the following describes a DATI).
The DRV1I-WA places
the address of the memory location from which the first word is
taken on the BDAL lines and asserts BSYNC.
Memory decodes and

3-9

latches the address.
The DRVII-WA then removes t.he address from
the BDAL lines and asserts BDIN~
Input data is now placed on the
BDAL lines by the memory and the memory asserts BRPLY.
The input
data is accepted by the DRVII-WA and BDIN is negated.
Memory negates BRPLY and the DRVII-WA negates BSACK and BSYNC to terminate
the bus cycle and release the bus.
The OUTPUT DATA BITS for the
user's I/O device are stored in the DRVII-WA output data buffer
register.
These bits can be read by the user's device at the
low-to-high transition of BUSY.
At the end of the first transfer, the DRVII-WA 1ATCR and BAR (or
BAE, if extended add ress i ng is selected) are incremented, BUSY
goes high, while READY remains low.
The user's device can initiate another DATI or DATTO cycle by again setting CYCLE REQUEST.
DMA transfers to the user's device can continue until the WCR increments to zero and causes an interrupt request to be generated
(see Section 3.2.4.1).

DRVll-WA

USER'S
DEVICE

LSI-ll
PROCESSOR

CS·3963

Figure 3-3

DMA DATIO/DATI Data Flow Diagram

3-10

3.3 TIMING
Input and output timing for the DRVII-WA is shown in Figures 3-4
through 3-8.
The timing diagrams show user signal timing for single cycle and burst mode operations which can be either programor user-initiated.

3-11

LOAD WCR

LOAD BAR

ATTN

INT ENABLE

W//ZZ?J

CQ,C1

WC/BA
INC ENABLE

AOO

~#A

SINGLE CYCLE

READY

CYCLE REO

BUSY

//////A

DATA FROM USER
(IF DATO(B))

X____~_C

DATA FROM DBV11-WA
(IF DATI OR DATIO)

WORD TRANSFER

BYTE TRANSFER
C5-4722

Figure 3-4

DRVll-WA Single Cycle, User-Initiated, Timing Diagram

3-12

LOAD WCR

LOAD BAR
ATTN
INT ENABLE

Ca,C1

l/7//\

I
~~

WC/BA
INC ENABLE

AOO

SINGLE CYCLE

I
I

~001

READY

CYCLE REO

BUSY

DATA FROM USER
(IF DATO(B))

DATA FROM DRV11-WA
(IF DATI OR DATIO)

J..-~~~ nsX'--___. .JX _ _ _ X
~

WORD TRANSFER

....J ' - - - - -

BYTE TRANSFER
C5-4723

Figure 3-5

DRVll-WA Single Cycle,
Diagram

3-13

program-Initiated, Timing

LOADWCR

LOAD BAR

ATTN
INT ENABLE

CO,C1

V
V

ij/ff~

W////4

WC/BA
INC ENABLE

]

AOO

SINGLE CYCLE

READY

111s MIN

CYCLE REO

227dX~ \

BUSY

DATA FROM USER
(IF DATO(B))

{l~~1

~
I

]

DATA FROM DRV11-A
(IF DATI OR DATIO)

7i ~ ~~~ X
ns

WORD TRANSFER

BYTE TRANSFER

* NOTE: If W2 jumper is installed, the DRV11-WA will relinquish bus mastership and re-request
mastership after every four words transferred.
C5-4724

Figure 3-6

DRV11-WA Burst Mode, User-Initiated, Timing Diagram

3-14

LOAD WCR

LOAD BAR
ATTN

INT ENABLE

CO,C1
WC/BA
INC ENABLE

\'---____1
_ _ _ _ _ _---ll

AOO

SINGLE CYCLE

\----------

READY

CYCLE REQ

BUSY

fX_'_--J

DATA FROM USER
(IF DATO(B))

~//2A

DATA FROM DRV11-WA
(IF DATI OR DATIO)

~
~~'_____....JX'________'X~_

X ___ X

WORD TRANSFER

....J ' - - - - -

BYTE TRANSFER

* NOTE: IF W2 jumper is installed, the DRV11-WA will relinquish bus mastership and re-request
mastership after every four words transferred.
CS·4725

Figure 3-7

DRVI1-WA Burst Mode, Program-Initiated, Timing Diagram

3-15

CYCLE (1) H

BUSY H

TX DIN H

TX DOUT H

\'----------

~~----------------_----II
\'---------- - - - _ - - - - 11

\'-------1

RX RPLY H

LD ODBH/L L
15:00 OUT H

15:00 IN H

150n5d~2

LD IDB H

\~--------/

RD IDB L
*1

OUTPUT DATA (READ DATA FROM MEMORY) LATCH TIMING TO
THE USER'S DEVICE (ODBR). DATA OUTPUT STARTS HERE.

READ DATA (WRITE TO MEMORY) INTERNAL LATCH TlIVIING (IDBR).

NOTE:

*1 AND *2 CANNOT BE ACKNOWLEDGED FROM USER SIDE. TIMING FROM
*1 TO *2 IS APPROXIMATELY 150 nS.
CS-4904

Figure 3-8

DRV11-WA DATTO Timing Diagram

3-16

CHAPTER 4
PROGRAMMING

4.1

GENERAL

This chapter presents basic programming
information
for
the
DRVll-WA.
The tYPE~S of programming instructions, the use of the
registers, program interrupts, and special program considerations
are presented.

4.2

PROGRAMMING INSTRUCTIONS

All programming instructions used for
used for programming the DRVIl-WA.

4.3

the Q-Bus processor may be

DRV11-WA REGISTERS

Six registers are used by the DRVTI-WA':
•
•
•
•
•

Word Count (WCR),
Bus Address (BAR),
Extended Bus Address Register
Control/Status (CSR), and
Input and Output Data Buffers

(BAE),
(DBRs).

The input and output nata buffer registers share the same bus address while WCR, BAR, and CSR have unique addresses.
If extended
addressing mode (Q22) is selected, thE? BAR and BAE share the same
address.
To access the BAE for reading/writing, you must first
access the BAR.
The BAR and BAE are read/written to alternately.

4.3.1

WCR

Load the l6-bit WCH with the 2's complement (negative number) of
DMA data transfers.
At the end of each DMA cycle, the WCR is incremented by one (if WC INC ENB is high).
When the last transfer
is made, the WCR is incremented to zero and an interrupt is requested.
The WCR is not byte-addressable.

4.3.2

BAR

Load the I5-bi t BAR wi th the add ress tha t spec if i es the memory
location into which the first word is written, or from which the
first word is read.
Following the transfer of each word, the BAR
is incremented by two, (if BA INC ENB is high) to point to the
next higher sequential memory word location.
In I8-bit mode, if
the BAR overflows, it will increment the extended address bits in
the CSR and "wrap-around" to location zero.
In extended addressi n g ( Q 2 2 ) mod e, i f the BAR 0 v e r flo ws, i t will inc r erne n t the BAE
and "wrap-around" t.o location zero.
Address bit A00 used for byte
transfers, is drivE?n by the user's device.
The BAR is not byteaddressable.

4-1

4.3.3 BAE
If extended addressing mode (Q22) is selected, load the 6-bit BAE
with the add~ess that specifies the memory location into/from
which the first word is written/read.
If the Bi\R overflows, it
will increment the BAE extended address bits and "wrap-around" to
location zero.
The RAE is not byte-addressable.
As of module CS
Revision C, BAE bit 15 will always read as a "one".
4.3.4 CSR
The l6-bit CSR is monitored for interface status and loadea with
cont rol bits.
The CSR is byte-add ressab Ie.
Figur e 4 -1 shows the
CSR bit assignments.
The function of each bit is described in
Table 4-1.
4.3.5 DBRs
The DBRs hold the l6-bit data words for transfer to memory from
the user's I/O device (input DRR), or from memory to the user's
I/O drive (output DBR).
Both DBRs share the same bus address and
are word- and byte-addressable.
4.4 PROGRAM INTERRUPTS
DRVll-WA interrupts are enabled by setting bit 06 (IE) of the CSR
(Figure 4-1 and Table 4-1).
Interrupts can OCCUJ:- when the READY
bit is set, or if independent interrupts are enabled when ATTN is
set.
The READY bit is set when:
•

Word count overflow (normal interrupt).

•

CSR ERROR bit (bit 15)

is set (special condition).

4.4.1 Word Count Overflow
An interrupt request is generated when the DRVll-WA WCR increments
to zero and producesWC OFLO (word count overflow).
we OFLO sets
READY in the CSR at the end of the DMA cycle.
4.4.2 CSR ERROR Bit (Bit 15)
The CSR ERROR bit can set for two possible reasons:
1.

When bit 14

(NEX)

When CSR bit 13

of the CSR is set, or

(ATTN)

is set.

CSR bit 14 is set when a non-existent (NEX) memory location is addressed and a reply from the addressed location is not received
within 20 s.
Bit 14 will set if a DATO bus cycle does not occur
performing a DATIO bus cycle.
ATTN bit 13 sets the CSR ERROR bit when the user's
drives ATTN high.

4-2

20~

after

I/O device

ATTN is a user-defined function that can be utilized to generate
an independent inte:rrupt request. When independent interrupts are
enabled, an interrupt can be generated regardless of the state of
READY.
4.5 FUNCTION AND STATUS BITS
There are three function bits (FNCT 1, 2, 3) and three status bits
(STAT A, B, C), which the user can employ (at his option) to control and indicate the status of the DMA transfers and/or the user
interface.
The function bits (CSR bits 01, 02, and (3) can be
used to transfer control data to the user's interface by means of
the OUTPUT DATA BIT lines of the DRVll-WA.
The status bits (CSR
bits 09, 10, and 11) can be used to indicate the status information is on the DRVll-WA INPUT DATA BIT lines.

NEX

MAINT

STAT B

CYCLE

XAD 16

FNCT 2

LEGEND:
R = READ ONLY
R/W = READ/WRITE
R/WO = READ/WRITE TO 0
W = WRITE ONLY. ALWAYS READS AS A O.
C5-3969

Figure 4-1
Table 4-1
Bit

01, 02, 03

CSR Format

CSR Bit Functions
Function

GO:

write-only bit; always reads as a zero.

Causes READY to be sent to the user's dev ice,
indicating that a command has been issued.

Allows DMA operation.

FNCT 1, 2, 3:

Read/write bits.

Three output bits available for
functions.

Cleared by INIT.

4-3

user-defined

Table 4-1

CSR Bit Functions (Cont)

Bit

Function

04, 05

XAD16, 17:
For standard Q-Buses (non-Q22).
Read/
write bits.
Two bits used for extended addressing.
Bits 04 and 05 increment with the address count when
the BAR "wraps-around" to zero.
E'or extended addressing Q-Buses, if extended addressing mode is
selected, these bits are read-only.

!tIE:
l .

Enables i nter'rupts to occur when READY is set.

2•

Enables interrupts to occur when ERROR is set. *

3•

Cleared by INIT.

Read-on 1 y bi t .
Tnd i ca tes tha t
is able to accept a new command:

the DRVII-WA

READY:-

09,

Read/write bit.

Set by INIT.

Set by WCOFLO.

Set by ERROR.

Cleared by GO (bit 00).

CYCLE:
Read/write bit.
DMA bus cycle:

10, l1

CYCLE

Set by CYCLE REQUEST.

Cleared during DMA cycle by

used

pr ime a

INIT~

STAT A, B ,e:
Read-only bi ts.
Thrl2e device status
input bits that indicate the state of the DSTAT A,
B, and C user signals.
These bits are set and
cleared by the user.

MAINT:
Read/write bit., Maintenance bit for
with the MAINDEC diagnostic.

use

ATTN:
Read-only bit.
Indicates the
ATTN user signal; sets READY, ERROR. *

the

* See Section 4.4.2.
4-4

state

Table 4-1

CSR Bit Functions (Cont)

Bit

Function

NEX:

Read/write to zero bit.

Non-existent memory; indicates that as bus master, the DRVll-WA did not receive BRPLY or that
a DATIO cycle was not completed.

Sets ERROR.

Cleared by INIT or by writing it to a zero.

ERROR:

Read-only bit.

Indicates
tions:

one

Cl.

NEX (bit 14)

ATTN (bit 13)

the

following

special

Sets READY (bit 7)
(bit 6) is set. *

and causes an interrupt if IE

Cleared by removing the special condition as
follows:
a.

NEX is cleared by writing bit 14 to zero.

ATTN is cleared by the user device.

* See Section 4.4.2.
4.6 LSI-II PROGRAMMING EXAMPLE
The following programs are sample programs for the DRVll-WA.

;*
;*

SAMPLE PROGRAM FOR Q18 BIT MODE
DO A 200 NPR DATA TRANSFER
DRVWCR=
172410
DRVBAR=
172412
DRVCSR=
172414
DRVDBR=
172416
PRO=
0
START:

WAIT:

MOV
MOV
MTPS
MOV
BIS
BR

condi-

#-,200. ,@#DRVWCR
#DBUF,@#DRVBAR
#PRO
#10l,@#DRVCSR
#400,@#DRVCSR
WA,IT

4-5

;WILL DO 200 XFER'S
iSET UP BUFFER ADDRESS
;ENABLE INTR
;SET IE & GO
iSET CYCLE
iWAIT HERE

i* SAMPLE PROGRAM FOR Q22 BIT MODE
i* DO A 200 NPR DATA TRANSFER
DRVWCR=
172410
DRVBAR=
172412
DRVBAE=
172412
DRVCSR=
172414
DRVDBR=
172416
PRO=
0

START:

WAIT:

MOV
TST
MOV
MOV
MTPS
MOV
BIS
BR

#-200.,@#DRVWCR
@DRVWCR
#DBUF,@#DRVBAR
#DBUF1,@#DRVBAE
#PRO
#101,@#DRVCSR
#400,@#DRVCSR
WAIT

iWILL DO 200 XFER'S
;CLEAR BAE FLAG *
iSET UP BUFFER ADDRESS
iSET UP EXTENDED BUFFER ADDRESS
;ENABLE INTR
;SET IE & GO
iSET CYCLE
;WAIT HERE

* By accessing the BAR,

a flag gets set to a one (1) (BAEFLAG=1).
This flag automatically gets cleared by accessin9 the BAE register.
To ensure that you will be accessing the BAR on your next
attempt, it is advisable to clear the BAE flag in your program.
This can be done by accessing any of the other registers (that
is, TST @DRVWCR).

4-6

CHAPTER 5
INTERPROCESSOR LINKS

5.1 GENERAL
The DRV11-WA can be configured for operation as a DMA paralleldata transfer link between two computer systems (Figure 5-1) by
installing jumper W4 and removing jumper W3.
The link operates in
a half-duplex communications mode; that is, it has the capability
of transmitting data bidirectionnlly between the two computer systems, but in only one direction at a ti~e.
5.2 OPERATING MODES
From a hardware standpoint, the link can operate in one of
modes: word mode, single cycle mode, and burst mode .

three

.In word mode, information can be passed between two computers in a
word-by-word sequence controlled by an interrupt-driven program.
In the single cycle and burst modes (which to the software are essentially identical), the link transmits a contiguous block of
memory data from one computer to the other.
DMA transfer is used
in both machines.
The principal difference between the two modes
of operation is that in the single cycle mode, the DRV11-WA must
obtain and release the bus for each data transfer made.
In the
burst mode, the DRVII-WA holds onto the bus once the bus grant is
received, until the requested 4-cycle or N-cycle transfer is completed.
BC08R CABLE
25 FT MAX.
r~------~~-----~~

en
co

:::>

en
:::>
co

DRV11-WA

CS-4905

Figure 5-1

Interprocessor Link Block Program

5-1

Each of the computers in the link configuration maintains independent control of its own interface.
The programs for the two computers must be written so as to ensure compatibility in terms of
information flow direction, setting bus address registers, ann
control of word count at the respective computer interfaces with
the DRVII-WA.
In the environment provided by the VAX-system software (ana recommended for the PDP-II systems) the communication between the
1 inked computers is establ i shed by means of CSR bi ts ((13: (1) and
(11:09), respectively (see Chapter 4, Figure 4-1 and Table 4-1 for
this register).
When CSR bits (03:01) are loaded into the CSR of
one ORVll-WA, the information appears in the other DRVll-WA of the
link configuration.
Table 5-1 shows the functional correlation of
these bit relationships for the DRVll-WA interprocessor links.
Table 5-1

Correlation of CSR Function and Status Bits in
Interprocessor Link Operation

CSR Bits
TransferTransferInitiating Responding
Computer
Computer
Bit 3
(FNCT 3)

Bit 11
( STAT A)

DR11-W/DRV11-B
Function
Single Cycle/
Burst NPR
Transfer

Meaning of CSR Bit status
at Transfer-Initiating
Computer
Set

Clear

Bit 2
(FNCT 2)

Bit 1(1
(STAT B)

INTR
( Interrupt)
Request

Set -

Bit 1
(FNCT 1)

Bit 9
(STAT C)

DATI/DATa

Set Clear

Single cycle NPR
tl::-ansfer
Burst NPR transfer
Interrupt of responding computer
DATO

- Dl\TI

5.2.1 Word Mode
Setting CSR bit 2 (FUNC 2) in the transmitting DHVll-WA sets both
CSR bit 10 (STATUS B) and CSR bit 13 (ATTN) in the receiving
DRVll-WA.
ATTN generates ERROR, which in turn generates an interrupt if IE is set.
In all three transfer modes, when power failure occurs in one computer, an ACLO is transmitted to the other computer, where it sets
ATTN and (as described above) causes an interrupt.
During word-mode transfers, the data must be maintained in the
ODBR until read by the other computer.
In general, this operation
requires that the receiving computer send back a "handshaking"
signal to indicate that it has read the data, and that the transmitting computer cannot modify the data in its OOBR.

5-2

The interrupt capability incorporated in the CSR can be used in
conjunction with the ODRR to pass information between computers in
a word-transfer interrupt sequence (Figure 5-2).

TRANSFER - INITIATING COMPUTER

TRANSFER - RESPONDING COMPUTER

1. LOAD ODBR WITH FIRST WORD.
2. SET CSR BIT 2~*.

L-------------J.~

1. ENTER INTR SERVICE ROUTINE.
2. READ CSR.
3. READ IDBR.
4. SET CSR BIT 2.

1. ENTER INTR SERVICE ROUTINE.
2. LOAD ODBR WITH SECOND WORD.
3. CLEAR. THEN SET CSR BIT 2.

L ____________•

REPEAT.

* BIT 2 CALLS FOR FAR - END INTR.
CS-4906

Figure 5-2

Interrupt Sequence for Word Mode Interprocessor Link

5-3

5.2.2
Single Cycle
NPR transfers by the link may be requested by either computer, and
may flow in either direction.
The NPR cycles always occur in
pairs: the first cycle is a DATI (read from memory) by the transmitter~ the second cycle is a DATO (write into memory)
by the receiver.
These alternating pairs of cycles repeat until the entire
buffer has been transmitteo.

The computer o.esignated as a link transmitter sets GO and CYCLE to
generate the first NPR cycle.
Subsequent NPR cycles are generated
by hardware handshaking between the DRVIl-WAs.
The programming sequence used to initiate a block transfer
given in Figure 5-3.

When the transmitter has read the data word from its memory and
loaded the word onto its OOBR, BUSY is deasserted.
BUSY is connected to CYCLE RQ at the receiving DRVIl-WA.
The trailing edge
of BUSY triggers an NPR cycle that writes the data word into the
receiver's memory.
Completion of the write cycle deasserts BUSY
in the receiving DRVII-WA.
BUSY returns to the transmitting
DRVII-WA as CYCLE RQ A.
This alternating sequence continues until
the word count register overflows and halts the block transfer.

5-4

TRANSFER - INITIATING COMPUTER

TRANSFER - RESPONDING COMPUTER

TRANSMITS MESSAGE DESCRIBING DATA
TO BE EXCHANGED (LENGTH. DIRECTION. ETC.)

ACKNOWLEDGES DATA TO BE
EXCHANGED.

DATA TRANSMITTER

DATA RECEIVER

1. SETS UP ITS OWN WC AND BA.

2. LOADS CSR:

•

SETS GO TO 1 TO CLEAR
READY.

•

SETS GO TO 1 TO CLEAR
READY.

•

CLEARS FNCT 1 TO 0
TO INDICATE DATI.

•

SETS FNCT 1 TO 1 TO
INDICATE DATO

•

SETS FNCT 3 TO 1 TO
INDICATE SINGLE CYCLE
TRANSFER.

•

SETS FNCT 3 TO 1 TO
INDICATE SINGLE CYCLE
TRANSFER.

•

SETS CYCl.E TO 1 TO
INITIATE.FIRST NPR CYCLE.
CS-4907

Figure 5-3

Single Cycle Transfer Sequence for Interprocessor Link

5.2.3 Burst Mode
The NPR burst mode requires that FNCT 3 be cleared on both
DRVll-WAs.
The programming procedure is similar to the single
cycle.
Clearing FNCT 3 drives SINGLE CYCLE H Iowan the other DRVII-WA.
During the first NPR cycle, the SINGLE CYCLE flip-flop clears and
stays clear until the last NPR'cycle, during which WCOF occurs.
When the single cycle flop is cleared, it effectively holds the
bus from releasing.
NOTE
N-cycle burst mode is not supported in a
VAX/DRVII-WA link.

5-5

5.3 PROGRAMMING
The programming characteristics of the interprocessor link are
basically the same as those of a single DRVIl-WA configuration.
However, when two DRV11-WAs are interconnected, the programming of
the registers is slightly modified, as explained in the following
sections.
5.3.1 Word Count Register (WCR)
The function of the WCR is the same as in the non-link mode.
However, the WC INC ENB signal is asserted continually in link mode.
5.3.2 Bus Address Register (BAR)
The basic function of the BAR is unchanged when the DRVll-WA is
operated in link mode.
However, since the hardware configuration
of the link permanently sets bit 00 to 0, interprocessor transfers
are for full words only.
5.3.3
Output Data Buffer Register/Input Data Buffer
(ODBR/IDBR)
The basic function of the ODBR/IDBR remains unchanged
DRVII-WA is operated in link mode.

the

5.3.4

Control and Status Register (CSR)
In interprocessor link operation, the CSR bits are defined somewhat differently than in link operation.
The differences are:
BIT 00

(GO)

Wh ens e t by its elf, GO con d i t ion s
transmit or a receive transfer.

BITS I,?,?

the

D RV 1 1 - t~7 A for

~ i the r

(FNCT 1,2,3)

FNCT 1

Is 1 to a receiving DRVII-WA, and 0 to a transmitting
DRVII-WA.
If set in one DRVII-WA, it is cleared in
the other DRVII-WA.
It is initialized by the software.

FNCT?

Sen~s an interrupt request to the companion computer;
sets STATUS R, A~~N, and RFADY in the compAnion computer, thereby causing an interrupt request if the
computer's IE bit is set, and ATTN interrunts are
enabled.

FNC~

If FNCT ? is a ~, the companion computer performs DMA
transfers in the burst mode ~ if FNCT 3 is a 1, the
companion computer performs DMA transfers in singlecycle mode.

BITS 4,5

(XBA 16, 17)

The funct ions of these bi ts are the same in both link and
non-l ink modes.
Refer to Chapter 4, Table 4-1 for definitions.

1)-6

BIT 6
The function of this bit is the same in both link and nonlink modes.
Refer to Table 4-1 for bit definition.
When
set, this bit permits the DRVII-WA to generate an interrupt
request if STATUS B sets as a result of FNCT 2 being set in
the companion computer.
BIT 7

(READY)
The function
link modes.
tion.

BIT 8

of this bit is the same in both link and nonRefer to Chapter 4, Table 4-1 for bit defini-

(CYCLE)
This bit is used to initiate single cycle and burst transfers
when the associated DRVII-WA is the transmi tter.
When this
bit is set in conjunction with bit 00 (GO), an immediate NPR
cycle occurs.

BITS 9, 10, 11
STATUS C

(STATUS C, B A)
This bit is read by the computer initiating the
transfer.
If Status C is set, the responding computer initiates a DATO; if the bit is cleared, the
responding computer initiates a DATI.

STATUS BReads FNCT 2 of the companion computer.
When set,
this bit indicates that an interprocessor interrupt
has been requested by the companion computer.
This
bit also sets ~TTN and READY, and causes an interrupt request if the IE bit is set.
STATUS A

BIT 13

Bit 11 (STATUS A) at 0 indicates a burst mode NPR
transfer; if bit 11 is a 1, a single cycle NPR
transfer is indicated.

(ATTN)

The function of this bit is the same in the link and non-link
modes.
ATTN is also set by either FNCT 2 or ACLO of the companion computer.
ATTN generates ERROR.
BIT 1.4
The function
link modes.
tion.
BIT 15

of this bit is the same in both link and nonRefer to Chapter 4, Table 4-1 for bit defini-

(ERROR)

The function
link modes.
tion.

of this bit is the same in both link and nonRefer to Chapter 4, Table 4-1 for bit defini-

5-7

DRV11-WA GENERAL PURPOSE
DMA INTERFACE
USER'S GUIDE
EK-DRVWA-UG-002

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